16-BIT 250-KSPS SERIAL CMOS SAMPLING ANALOG-TO-DIGITAL CONVERTER ADS8509 FEATURES DESCRIPTION
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SLAS324C – OCTOBER 2004 – REVISED APRIL 2010
16-BIT 250-KSPS SERIAL CMOS SAMPLING ANALOG-TO-DIGITAL CONVERTER
Check for Samples: ADS8509
1
FEATURES
2
• 250-kHz Sampling Rate
• 4-V, 5-V, 10-V, ±3.33-V, ±5-V, and ±10-V Input
Ranges
• ±2 LSB Max INL
• ±1 LSB Max DNL, 16-Bit No Missing Codes
• SPI Compatible Serial Output with Daisy-Chain
(TAG) Feature
• Single 5-V Supply
• Pin-Compatible with ADS7809 (Low Speed) and 12-Bit ADS8508/7808
• Uses Internal or External Reference
• 70-mW Typ Power Dissipation at 250 KSPS
• 20-Pin SO and 28-Pin SSOP Packages
• Simple DSP Interface
APPLICATIONS
• Industrial Process Control
• Data Acquisition Systems
• Digital Signal Processing
• Medical Equipment
• Instrumentation
DESCRIPTION
The ADS8509 is a complete 16-bit sampling analog-to-digital (A/D) converter using state-of-the-art
CMOS structures. It contains a complete 16-bit, capacitor-based, successive approximation register
(SAR) A/D converter with sample-and-hold, reference, clock, and a serial data interface. Data can be output using the internal clock or can be synchronized to an external data clock. The ADS8509 also provides an output synchronization pulse for ease of use with standard DSP processors.
The ADS8509 is specified at a 250-kHz sampling rate over the full temperature range. Precision resistors provide various input ranges including ±10 V and 0 V to 5 V, while the innovative design allows operation from a single +5-V supply with power dissipation under 100 mW.
The ADS8509 is available in 20-pin SO and 28-pin
SSOP packages, both fully specified for operation over the industrial -40°C to 85°C temperature range.
Successive Approximation Register
Clock EXT/INT
R1
IN
R2
IN
R3
IN
9.8 k
Ω
4.9 k
Ω
2.5 k
Ω
CAP
10 k
Ω
CDAC
Buffer
4 k
Ω
Internal
+2.5 V Ref
Comparator
Serial
Data
Out
&
Control
BUSY
DATACLK
DATA
R/C
SB/BTC
CS
PWRD
REF
1
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas
Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
2
All trademarks are the property of their respective owners.
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not necessarily include testing of all parameters.
Copyright © 2004–2010, Texas Instruments Incorporated
2
ADS8509
SLAS324C – OCTOBER 2004 – REVISED APRIL 2010
www.ti.com
This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with appropriate precautions. Failure to observe proper handling and installation procedures can cause damage.
ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more susceptible to damage because very small parametric changes could cause the device not to meet its published specifications.
PACKAGE/ORDERING INFORMATION
(1)
PRODUCT
MINIMUM
RELATIVE
ACCURACY
(LSB)
NO
MISSING
CODE
MINIMUM
SINAD
(dB)
SPECIFICATION
TEMPERATURE
RANGE
PACKAGE
LEAD
PACKAGE
DESIGNATOR
ORDERING
NUMBER
TRANSPORT
MEDIA, QTY
ADS8509IB
ADS8509I
±2
±3
16
15
85
83
–40°C to 85°C
–40°C to 85°C
SO-20
SSOP-28
SO-20
SSOP-28
DW
DB
DW
DB
ADS8509IBDW Tube, 25
ADS8509IBDWR Tape and Reel, 2000
ADS8509IBDB Tube, 50
ADS8509IBDBR
ADS8509IDW
ADS8509IDWR
ADS8509IDB
ADS8509IDBR
Tape and Reel, 2000
Tube, 25
Tape and Reel, 2000
Tube, 50
Tape and Reel, 2000
(1) For the most current package and ordering information, see the Package Option Addendum at the end of this document, or visit the device product folder on www.ti.com
.
ABSOLUTE MAXIMUM RATINGS
over operating free-air temperature range (unless otherwise noted)
(1)
Analog inputs
R1
IN
R2
IN
R3
IN
REF
CAP
Ground voltage differences
DGND, AGND2
V
ANA
V
DIG to V
ANA
V
DIG
Digital inputs
Maximum junction temperature
Storage temperature range
Internal power dissipation
Lead temperature (soldering, 1.6 mm from case 10 seconds)
(1) All voltage values are with respect to network ground terminal.
UNIT
±25 V
±25 V
±25 V
+V
ANA
+ 0.3 V to AGND2 – 0.3 V
Indefinite short to AGND2, momentary short to V
ANA
±0.3 V
6 V
0.3 V
6 V
–0.3 V to +V
DIG
+ 0.3 V
165°C
–65°C to 150°C
700 mW
260°C
Product Folder Link(s):
ADS8509
Copyright © 2004–2010, Texas Instruments Incorporated
ADS8509 www.ti.com
SLAS324C – OCTOBER 2004 – REVISED APRIL 2010
ELECTRICAL CHARACTERISTICS
At T
A
= –40°C to 85°C, f s
= 250 kHz, V
DIG
= V
ANA
= 5 V, using internal reference and 0.1%, 0.25-W fixed resistors (see
and
) (unless otherwise specified)
ADS8509I ADS8509IB
PARAMETER TEST CONDITIONS
MIN TYP MAX
16
MIN TYP MAX
16 Resolution
ANALOG INPUT
Voltage range
(1)
Impedance
(1)
Capacitance 50 50
UNIT
Bits pF
THROUGHPUT SPEED
Conversion cycle
Throughput rate
DC ACCURACY
INL
DNL
Integral linearity error
Differential linearity error
No missing codes
Transition noise
(3)
Full-scale error
(4) (5)
±10-V Range
All other ranges
Acquire and convert
Int. ref. with 0.1% external fixed resistors
Full-scale error drift
Full-scale error
(4) (5)
±10-V Range
All other ranges
Full-scale error drift
Bipolar zero error
(4)
Int. ref.
Ext. ref. with 0.1% external fixed resistors
Ext. ref.
Bipolar zero error drift
10-V Range
Unipolar zero error
(4) 4-V and 5-V
Range
Unipolar zero error drift
Recovery to rated accuracy after 1m
F Capacitor to CAP power down
Power supply sensitivity
(V
DIG
= V
ANA
= V
D
)
AC ACCURACY
SFDR Spurious-free dynamic range
THD Total harmonic distortion
SINAD
Signal-to-(noise+distortion) f f f
+4.75 V < V
I
I
I
= 20 kHz
= 20 kHz
= 20 kHz
–60-dB Input f
I
= 20 kHz
D
< +5.25 V
SNR Signal-to-noise ratio
Full-power bandwidth
(7)
SAMPLING DYNAMICS
Aperture delay
Transient response
Overvoltage recovery
(8)
FS Step
250
–3
–2
15
–0.5
–0.5
–0.5
–0.5
–10
–5
–3
–8
90
83
83
1
±7
±2
±0.4
±2
1
99
–98
88
30
88
500
5
150
4
3
2
10
5
3
8
–90
2
250
–2
–1
16
0.5
–0.5
0.5
–0.5
0.5
–0.5
0.5
–0.5
–5
–5
–3
–8
95
85
86
1
±7
±2
±0.4
±2
1
99
–98
88
32
88
500
5
150
4
0.5
0.5
0.5
0.5
2
1
5
5
3
8
–93
2 m s kHz
LSB
(2)
LSB
Bits
LSB
%FSR ppm/°C
%FSR ppm/°C mV ppm/°C mV ppm/°C ms
LSB ns m s ns dB
(6) dB dB dB dB kHz
(1) ±10 V, 0 V to 5 V, etc. (see
Table 2 ). For normal operation, the analog input should not exceed configured range ±20%.
(2) LSB means least significant bit. For the ±10-V input range, one LSB is 305 m
V.
(3) Typical rms noise at worst case transitions and temperatures.
(4) As measured with fixed resistors shown in
and
. Adjustable to zero with external potentiometer. Factory calibrated with 0.1%, 0.25-W resistors.
(5) For bipolar input ranges, full-scale error is the worst case of –full-scale or +full-scale uncalibrated deviation from ideal first and last code transitions, divided by the transition voltage (not divided by the full-scale range) and includes the effect of offset error. For unipolar input ranges, full-scale error is the deviation of the last code transition divided by the transition voltage. It also includes the effect of offset error.
(6) All specifications in dB are referred to a full-scale ±10-V input.
(7) Full-power bandwidth is defined as the full-scale input frequency at which signal-to-(noise + distortion) degrades to 60 dB.
(8) Recovers to specified performance after 2 x FS input overvoltage.
Copyright © 2004–2010, Texas Instruments Incorporated
3
Product Folder Link(s):
ADS8509
4
ADS8509
SLAS324C – OCTOBER 2004 – REVISED APRIL 2010
www.ti.com
ELECTRICAL CHARACTERISTICS (continued)
At T
A
= –40°C to 85°C, f s
= 250 kHz, V
DIG
= V
ANA
= 5 V, using internal reference and 0.1%, 0.25-W fixed resistors (see
and
) (unless otherwise specified)
PARAMETER TEST CONDITIONS
MIN
ADS8509I
TYP MAX MIN
ADS8509IB
TYP MAX
REFERENCE
Internal reference voltage
Internal reference source current
(must use external buffer)
Internal reference drift
External reference voltage range for specified linearity
External reference current drain
DIGITAL INPUTS
Logic levels
No load
Ext. 2.5-V ref.
V
IL
V
IH
Low-level input voltage
High-level input voltage
I
IL
I
IH
Low-level input current
High-level input current
DIGITAL OUTPUTS
Data format (serial 16-bits)
Data coding (binary 2's complement or straight binary)
V
V
OL
OH
Pipeline delay (conversion results only available after completed conversion)
Data clock (selectable for internal or external data clock)
Internal clock (output only when EXT/INT Low transmitting data)
External clock (can run continually but not recommended for optimum performance)
Low-level output voltage
High-level output voltage
Leakage current
I
I
V
V
IL
IH
= 0 V
EXT/INT High
SINK
= 5 V
= 1.6 mA
SOURCE
= 500 m
A
Hi-Z State,
V
OUT
= 0 V to V
DIG
Hi-Z State Output capacitance
POWER SUPPLIES
V
DIG
V
ANA
Digital input voltage
Analog input voltage
I
DIG
I
ANA
Digital input current
Analog input current
POWER DISSIPATION
PWRD Low
PWRD High f
Must be
S
≤ V
= 250 kHz
ANA
TEMPERATURE RANGE
Specified performance
Derated performance
(9)
Storage
THERMAL RESISTANCE (
q
JA
)
SSOP
SO
2.48
2.3
–0.3
2.0
0.1
4
4.75
4.75
–40
–55
–65
2.5
1
8
2.5
9
5
5
4
10
70
50
62
46
2.52
2.48
2.7
100
26
0.4
±5
15
100
85
125
150
2.3
V
DIG
0.8
–0.3
+0.3 V
±10
2.0
±10
0.1
4
5.25
4.75
5.25
4.75
–40
–55
–65
2.5
1
8
2.5
9
5
5
4
10
70
50
62
46
2.52
2.7
100
0.8
V
DIG
+0.3 V
±10
±10
26
0.4
±5
15
5.25
5.25
100
85
125
150
UNIT
V m A ppm/°C
V m A
V
V m A
V
V mA mA
°C
°C
°C
V
V m
A m A
MHz
MHz pF mW m
W
°C/W
°C/W
(9) The internal reference may not be started correctly beyond the industrial temperature range (–40°C to 85°C), therefore use of an external reference is recommended.
Product Folder Link(s):
ADS8509
Copyright © 2004–2010, Texas Instruments Incorporated
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ADS8509
PIN CONFIGURATIONS
DW PACKAGE
SO-20
(TOP VIEW)
R1
IN
1
AGND1 2
R2
IN
R3
IN
3
4
CAP 5
REF
6
AGND2
7
SB/BTC
8
EXT/INT
9
DGND 10
20
V
DIG
19
V
ANA
18 PWRD
17
BUSY
16
CS
15
R/C
14 TAG
13 DATA
12 DATACLK
11 SYNC
SLAS324C – OCTOBER 2004 – REVISED APRIL 2010
R1
IN
1
AGND1 2
R2
IN
R3
IN
3
4
NC
5
CAP 6
REF 7
NC
AGND2
8
9
NC 10
NC 11
SB/BTC 12
EXT/INT
13
DGND 14
DB PACKAGE
SSOP-28
(TOP VIEW)
28
V
DIG
27
V
ANA
26
PWRD
25
BUSY
24
CS
23
NC
22 NC
21
R/C
20 NC
19 TAG
18 NC
17 DATA
16 DATACLK
15 SYNC
Copyright © 2004–2010, Texas Instruments Incorporated
Product Folder Link(s):
ADS8509
5
6
ADS8509
SLAS324C – OCTOBER 2004 – REVISED APRIL 2010
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Terminal Functions
TERMINAL
NAME DB NO.
DW NO.
I/O
AGND1
AGND2
BUSY
2
9
25
2
7
17
CAP
CS
DATA
DATACLK
6
24
17
16
5
16
13
12
DESCRIPTION
– Analog ground. Used internally as ground reference point. Minimal current flow.
– Analog ground
O Busy output. Falls when a conversion is started and remains low until the conversion is completed and the data is latched into the output shift register.
– Reference buffer capacitor. 2.2m
F Tantalum to ground.
– Chip select. Internally ORed with R/C.
O Serial data output. Data is synchronized to DATACLK with the format determined by the level of
SB/BTC. In the external clock mode, after 16 bits of data, the ADS8509 outputs the level input on
TAG as long as CS is low and R/C is high (see
and
Figure 9 ). If EXT/INT is low, data is
valid on both the rising and falling edges of DATACLK, and between conversions DATA stays at the level of the TAG input when the conversion was started.
I/O Either an input or an output depending on the EXT/INT level. Output data is synchronized to this clock. If EXT/INT is low, DATACLK transmits 16 pulses after each conversion and then remains low between conversions.
DGND
EXT/INT
NC
14
13
10
9
–
– Digital ground
– Selects external or internal clock for transmitting data. If high, data is output synchronized to the clock input on DATACLK. If low, a convert command initiates the transmission of the data from the previous conversion, along with 16-clock pulses output on DATACLK.
– No connect
PWRD
5, 8, 10,
11, 18,
20, 22,
23
26 18
R/C
REF
R1
IN
R2
IN
R3
IN
SB/BTC
SYNC
TAG
V
ANA
V
DIG
21
7
1
3
4
12
15
19
27
28
15
6
1
3
4
8
11
14
19
20
I
I
I
I Power down input. If high, conversions are inhibited and power consumption is significantly reduced. Results from the previous conversion are maintained in the output shift register.
Read/convert input. With CS low, a falling edge on R/C puts the internal sample-and-hold into the hold state and starts a conversion. When EXT/INT is low, this also initiates the transmission of the data results from the previous conversion. If EXT/INT is high, a rising edge on R/C with CS low or a falling edge on CS with R/C high transmits a pulse on SYNC and initiates the transmission of data from the previous conversion.
I/O Reference input/output. Outputs internal 2.5-V reference. Can also be driven by external system reference. In both cases, bypass to ground with a 2.2m F tantalum capacitor.
Analog input. See
for input range connections.
Analog input. See
for input range connections.
I
I
I
Analog input. See
for input range connections.
Select straight binary or binary 2's complement data output format. If high, data is output in a straight binary format. If low, data is output in a binary 2's complement format.
O Sync output. This pin is used to supply a data synchronization pulse when the EXT level is high and at least one external clock pulse has occurred when not in the read mode. See the external clock modes desciptions.
I Tag input for use in the external clock mode. If EXT is high, digital data input from TAG is output on DATA with a delay that is dependent on the external clock mode. See
and
I Analog supply input. Nominally +5 V. Connect directly to pin 20 and decouple to ground with
0.1m
F ceramic and 10m
F tantalum capacitors.
Digital supply input. Nominally +5 V. Connect directly to pin 19. Must be ≤ V
ANA
.
Product Folder Link(s):
ADS8509
Copyright © 2004–2010, Texas Instruments Incorporated
ADS8509 www.ti.com
TIMING REQUIREMENTS, T
A
= –40°C to 85°C
PARAMETER
t d8 t d9 t d10 t su3 t d11 t w3 t w4 t su1 t su2 t d7 t su3 t h1 t w1 t d1 t w2 t d2 t d3 t conv t acq t conv
+ t acq t d4 t c1 t d5 t d6 t c2
Pulse duration, convert
Delay time, BUSY from R/C low
Pulse duration, BUSY low
Delay time, BUSY, after end of conversion
Delay time, aperture
Conversion time
Acquisition time
Cycle time
Delay time, R/C low to internal DATACLK output
Cycle time, internal DATACLK
Delay time, data valid to internal DATACLK high
Delay time, data valid after internal DATACLK low
Cycle time, external DATACLK
Pulse duration, external DATACLK high
Pulse duration, external DATACLK low
Setup time, R/C rise/fall to external DATACLK high
Setup time, R/C transition to CS transition
Delay time, SYNC, after external DATACLK high
Delay time, data valid
Delay time, CS to rising edge
Delay time, previous data available after CS, R/C low
Setup time, BUSY transition to first external DATACLK
Delay time, final external DATACLK to BUSY falling edge
Setup time, TAG valid
Hold time, TAG valid
SLAS324C – OCTOBER 2004 – REVISED APRIL 2010
PARAMETER MEASUREMENT INFORMATION
CS
R/C t su1 t su1
External
DATACLK
CS Set Low, Discontinuous Ext DATACLK
R/C
CS t su1 t su1
External
DATACLK
R/C Set Low, Discontinuous Ext DATACLK
CS
R/C t su2
BUSY t su2 t su3
1 2
External
DATACLK
CS Set Low, Discontinuous Ext DATACLK
Figure 1. Critical Timing
3
2
10
2
5
15
20
35
15
15
15
10
MIN TYP MAX UNIT
40 ns
6 20
2.2
ns m s
1.8
5
5
2.2
4 ns ns m s m s m s
270
110
35
35
35
20 ns ns ns ns ns ns ns ns ns
0
2
1 m s ns m s ns ns ns ns ns
Copyright © 2004–2010, Texas Instruments Incorporated
Product Folder Link(s):
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8
ADS8509
SLAS324C – OCTOBER 2004 – REVISED APRIL 2010
PARAMETER MEASUREMENT INFORMATION (continued)
www.ti.com
t w1 t w1
R/C t d1 t w2 t d1 t w2
BUSY
STATUS t d3
Nth Conversion
Error
Correction
t d2 t d11
(N+1)th Accquisition
t d3
(N+1)th Conversion
Error
Correction
t d2 t d11
(N+2)th Accquisition
t conv t c1 t d4
Internal
DATACLK
1 2 16
t d6 t d5
DATA
TAG = 0
D15 D0
(N−1)th Conversion Data
CS, EXT/INT, and TAG are tied low
t acq
TAG = 0
t d4 t conv
1 2 16
D15 D0
Nth Conversion Data
t acq
TAG = 0
8 starts READ
Figure 2. Basic Conversion Timing (Internal DATACLK - Read Previous Data During Conversion) t w1 t w1
R/C
BUSY
STATUS t d3 t d1 t w2 t d1 t w2
External
DATACLK t su1
Nth Conversion
t d11
Error
Correction
t conv
1
16
t d2
(N+1)th Accquisition
t su3 t acq
1
2
t d3
16
t su1 t d11
(N+1)th Conversion
Error
Correction
t conv
1 16
t d2
(N+2)th Accquisition
t acq t su3
1
2
16
DATA
TAG = 0
No more data to shift out
TAG = 0
Nth Data
TAG = 0
No more data to shift out
TAG = 0
EXT/INT tied high, CS and TAG are tied low t w1
+ t su1
starts READ
Figure 3. Basic Conversion Timing (External DATACLK)
(N+1)th Data TAG = 0
Product Folder Link(s):
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Copyright © 2004–2010, Texas Instruments Incorporated
ADS8509 www.ti.com
SLAS324C – OCTOBER 2004 – REVISED APRIL 2010
PARAMETER MEASUREMENT INFORMATION (continued)
t w1 t su1 t w2 t d1
R/C
BUSY
STATUS t d3 t d1
External
DATACLK
Nth Conversion
t d11
Error
Correction
t conv t w3 t c2 t d2
(N+1) th Accquisition
t su3 t w4
0 1 2 3 4 5
t acq
10 11 12 13 14 15 16
t d3 t su1
SYNC = 0
DATA
TAG t su3 t d8
T00
D15
t h1
T01
D14
T02
D13 D12 D11
T03
D10
T04 T05 T06
Nth Conversion Data
D05 D04 D03 D02 D01
t d8
D00
Null
T00 Txx
T11 T12 T13 T14 T15 T16
Null
T17
Tyy
EXT/INT tied high, CS tied low t w1
+ t su1
starts READ
Figure 4. Read After Conversion (Discontinuous External DATACLK) t w1
R/C t d1 t w2
BUSY
STATUS t d3 t d10
Nth Conversion
t su3 t su1 t w3
0
t c2
1
t w4
2 3 4 5
t conv
10 11 12 13 14 15 16
External
DATACLK
SYNC = 0 t d8
D15 D14 D13 D12 D11 D10
Nth Conversion Data
D05 D04 D03 D02 D01
t d8
D00
DATA
EXT/INT tied high, CS and TAG tied low
Rising DATACLK change DATA, t w1
+ t su1
Starts READ
TAG is not recommended for this mode. There is not enough time to do so without violating t d11
.
Figure 5. Read During Conversion (Discontinuous External DATACLK) t d2
Error
Correction
t d11
Copyright © 2004–2010, Texas Instruments Incorporated
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SLAS324C – OCTOBER 2004 – REVISED APRIL 2010
PARAMETER MEASUREMENT INFORMATION (continued)
www.ti.com
t w1
R/C t d1 t su1 t w2
BUSY t d3
STATUS
External t su1
DATACLK t d11
Nth Conversion
Error
Correction
t conv t su3
0 t d7
SYNC
=0
DATA
TAG t t d2 su1
(N+1)th Accquisition
t c2
1
t w3
2
t c2
3
t w4
4 5 6 7
t t d8 t su3
T00
D15
t h1
D14
T01 T02
D13 D12 D11 D10
T03 T04 T05 T06
acq
12 13 14 15 16 17 18
T11 T12 T13 T14 T15 T16 T17
t d3 t su1
Nth Conversion Data
D05 D04 D03 D02 D01
t d8
D00 Null
T00 Txx
Tyy
t d1
EXT/INT tied high, CS tied low t w1
+ t su1
starts READ
Figure 6. Read After Conversion With SYNC (Discontinuous External DATACLK) t w1
R/C t d1 t w2
BUSY t d3
STATUS t su1
External
DATACLK
SYNC = 0
DATA
0 t su1 t d10
Nth Conversion
t su3 t su1 t d7 t w3
1 2
t c2
3
t c2 t w4
4 5 6
t d8
7
t
D15 D14 D13 D12 D11 D10
conv
12 13 14 15 16 17 18
Nth Conversion Data
D05 D04 D03 D02 D01
t d8
D00
EXT/INT tied high, CS and TAG tied low t w1
+ t su1
Starts READ
TAG is not recommended for this mode. There is not enough time to do so without violating t d11
.
Figure 7. Read During Conversion With SYNC (Discontinuous External DATACLK) t d2
Error
Correction
t d11
10
Product Folder Link(s):
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Copyright © 2004–2010, Texas Instruments Incorporated
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ADS8509
SLAS324C – OCTOBER 2004 – REVISED APRIL 2010
PARAMETER MEASUREMENT INFORMATION (continued)
t su2
Figure 8. Conversion and Read Timing with Continuous External DATACLK (EXT/INT Tied High) Read
After Conversions (Not Recommended)
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ADS8509
SLAS324C – OCTOBER 2004 – REVISED APRIL 2010
PARAMETER MEASUREMENT INFORMATION (continued)
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12
Figure 9. Conversion and Read Timing with Continous External DATACLK (EXT/INT Tied High) Read
Previous Conversion Results During Conversion (Not Recommended)
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SLAS324C – OCTOBER 2004 – REVISED APRIL 2010
105
TYPICAL CHARACTERISTICS
SPURIOUS FREE DYNAMIC RANGE vs
FREE-AIR TEMPERATURE
TOTAL HARMONIC DISTORTION vs
FREE-AIR TEMPERATURE
−100
100
95
90
85
80 f s
= 250 KSPS, f i
= 20 kHz
75
−40 25
T
A
− Free-Air Temperature −
5
C
Figure 10.
85
−95
−90
−85
−80
−75 f s
= 250 KSPS, f i
= 20 kHz
−70
−40 25
T
A
− Free-Air Temperature −
5
C
Figure 11.
85
90
85
80
75
100
SIGNAL-TO-NOISE RATIO vs
FREE-AIR TEMPERATURE
f s
= 250 KSPS, f i
= 20 kHz
95
70
−40 25
T
A
− Free-Air Temperature −
5
C
Figure 12.
85
90
SIGNAL-TO-NOISE RATIO vs
INPUT FREQUENCY
SIGNAL-TO-NOISE AND DISTORTION vs
FREE-AIR TEMPERATURE
100 f s
= 250 KSPS, f i
= 20 kHz
95
90
85
80
75
70
−40 25
T
A
− Free-Air Temperature −
5
C
Figure 13.
85
SIGNAL-TO-NOISE AND DISTORTION vs
INPUT FREQUENCY
90
85 85
80
75
70
65
1 10
f i
− Input Frequency − kHz
100
Figure 14.
80
75
70
65
1 10
f i
− Input Frequency − kHz
Figure 15.
100
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TYPICAL CHARACTERISTICS (continued)
SPURIOUS FREE DYNAMIC RANGE vs
INPUT FREQUENCY
105
TOTAL HARMONIC DISTORTION vs
INPUT FREQUENCY
−105
−100
100
95
90
−95
−90
85
80
75
70
1 10
f i
− Input Frequency − kHz
Figure 16.
100
−85
−80
−75
−70
1 10
f i
− Input Frequency − kHz
Figure 17.
100
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INTERNAL REFERENCE VOLTAGE vs
FREE-AIR TEMPERATURE
2.510
2.508
2.506
2.504
2.502
2.500
2.498
2.496
2.494
2.492
2.490
−55 −35 −15 5 25 45 65 85 105
T
A
− Free-Air Temperature −
5
C
Figure 18.
0.05
0
−0.05
−0.10
−0.15
0.20
FULL SCALE ERROR vs
FREE-AIR TEMPERATURE
0.15
0.10
External Reference,
±
10 V Range for 5 Representative
Parts
−0.20
−40 −25 −10 5 20 35 50 65 80
T
A
− Free-Air Temperature −
5
C
Figure 20.
BIPOLAR ZERO SCALE ERROR vs
FREE-AIR TEMPERATURE
5
4
3
External Reference,
±
10-V Range
0
−1
2
1
−2
−3
−4
−5
−40 −25 −10 5 20 35 50 65 80
T
A
− Free-Air Temperature −
5
C
Figure 19.
20
SUPPLY CURRENT vs
FREE-AIR TEMPERATURE
16
15
14
13
19
18
17
12
11
10
−40 −25 −10 5 20 35 50 65 80
T
A
− Free-Air Temperature −
5
C
Figure 21.
14
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SLAS324C – OCTOBER 2004 – REVISED APRIL 2010
2500
2000
1500
1000
500
0
4500
4000
3500
3000
TYPICAL CHARACTERISTICS (continued)
HISTOGRAM
8192
Conversions of a DC Input
2082
1484
4
−3
149
−2 −1 0
Code
Figure 22.
1
238
2
11
3
PERFORMANCE vs
CAP PIN CAPACITOR ESR
100
95
90
85
80
SINAD
|THD|
75
70
65
60
55
2.2
µ
F Capacitor on
CAP Pin (pin 6)
50
0 1 2 3 4 5 6 7 8 9 10 11
ESR − Resistance −
W
Figure 23.
INTEGRAL NONLINEARITY
2.5
2
1.5
1
0.5
0
−0.5
−1
−1.5
−2
−2.5
0 f s
= 250 KSPS
49152 65536 16384 32768
Code
Figure 24.
DIFFERENTIAL NONLINEARITY
2.5
2
1.5
1
0.5
0
−0.5
−1
−1.5
−2
−2.5
0 f s
= 250 KSPS
16384 49152 65536 32768
Code
Figure 25.
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SLAS324C – OCTOBER 2004 – REVISED APRIL 2010
TYPICAL CHARACTERISTICS (continued)
FFT (20-kHz Input)
−100
−120
−140
−160
−180
0
20
0
−20
−40
−60
−80
25 50
f − Frequency − kHz
75
Figure 26.
100
8192 Points, f s
= 250 KSPS, f i
= 20 kHz, 0 dB
SINAD = 86.0 dB,
THD = −98.7 dB
125
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BASIC OPERATION
Two signals control conversion in the ADS8509: CS and R/C. These two signals are internally ORed together. To start a conversion the chip must be selected, CS low, and the conversion signal must be active, R/C low. Either signal can be brought low first. Conversion starts on the falling edge of the second signal. BUSY goes low when conversion starts and returns high after the data from that conversion is shifted into the internal storage register.
Sampling begins when BUSY goes high.
To reduce the number of control pins CS can be tied low permanently. The R/C pin now controls conversion and data reading exclusively. In the external clock mode this means that the ADS8509 clocks out data whenever R/C is brought high and the external clock is active. In the internal clock mode data is clocked out every convert cycle regardless of the states of CS and R/C. The ADS8509 provides a TAG input for cascading multiple converters together.
READING DATA
The conversion result is available as soon as BUSY returns to high, therefore data always represents the conversion previously completed even when it is read during a conversion. The ADS8509 outputs serial data in either straight binary or binary two’s compliment format. The SB/BTC pin controls the format. Data is shifted out
MSB first. The first conversion immediately following a power-up does not produce a valid conversion result.
Data can be clocked out with either the internally generated clock or with an external clock. The EXT/INT pin controls this function. If an external clock is used, the TAG input can be used to daisy-chain multiple ADS8509 data pins together.
INTERNAL DATACLK
In internal clock mode data for the previous conversion is clocked out during each conversion period. The internal data clock is synchronized to the internal conversion clock so that is does not interfere with the conversion process.
The DATACLK pin becomes an output when EXT/INT is low. 16 Clock pulses are generated at the beginning of each conversion after timing t
8 is satisfied, i.e. only the previous conversion result can be read during conversion.
DATACLK returns to low when it is inactive. The 16 bits of serial data are shifted out the DATA pin synchronous to this clock with each bit available on a rising and then a falling edge. The DATA pin returns to the state of the
TAG pin input sensed at the start of transmission.
EXTERNAL DATACLK
The external clock mode offers several ways to retrieve conversion results. However, since the external clock cannot be synchronized to the internal conversion clock care must be taken to avoid corrupting the data.
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When EXT/INT is set high, the R/C and CS signals control the read state. When the read state is initiated, the result from the previously completed conversion is shifted out the DATA pin synchronous to the external clock that is connected to the DATACLK pin. Each bit is available on a falling and then a rising edge. The maximum external clock speed of 28.5 MHz allows data to be shifted out quickly either at the beginning of conversion or the beginning of sampling.
There are several modes of operation available when using an external clock. It is recommended that the external clock run only while reading data. This is discontinuous clock mode. Since the external clock is not synchronized to the internal clock that controls conversion slight changes in the external clock can cause conflicts that can corrupt the conversion process. Specifications with a continuously running external clock cannot be ensured. It is especially important that the external clock does not run during the second half of the conversion cycle (approximately the time period specified by t d11
, see the TIMING REQUIREMENTS table).
In discontinuous clock mode data can be read during conversion or during sampling, with or without a SYNC pulse. Data read during conversion must meet the t complete before starting a conversion.
d11 timing specification. Data read during sampling must be
Whether reading during sampling or during conversion a SYNC pulse is generated whenever at least one rising edge of the external clock occurs while the part is not in the read state. In the discontinuous external clock with
SYNC mode a SYNC pulse follows the first rising edge after the read command. The data is shifted out after the
SYNC pulse. The first rising clock edge after the read command generates a SYNC pulse. The SYNC pulse can be detected on the next falling edge and then the next rising edge. Successively, each bit can be read first on the falling edge and then on the next rising edge. Thus 17 clock pulses after the read command are required to read on the falling edge. 18 Clock pulses are necessary to read on the rising edge.
DESCRIPTION
Read on falling edge of DATACLK
Read on rising edge of DATACLK
Table 1. DATACLK Pulses
DATACLK PULSES REQUIRED
WITH SYNC WITHOUT SYNC
17
18
16
17
If the clock is entirely inactive when not in the read state a SYNC pulse is not generated. In this case the first rising clock edge shifts out the MSB. The MSB can be read on the first falling edge or on the next rising edge. In this discontinuous external clock mode with no SYNC, 16 clocks are necessary to read the data on the falling edge and 17 clocks for reading on the rising edge. Data always represents the conversion already completed.
TAG FEATURE
The TAG feature allows the data from multiple ADS8509 converters to be read on a single serial line. The converters are cascaded together using the DATA pins as outputs and the TAG pins as inputs as illustrated in
through each converter, synchronous to the externally supplied data clock, onto the serial data line. The internal clock cannot be used for this configuration.
The preferred timing uses the discontinuous external data clock during the sampling period. Data must be read during the sampling period because there is not sufficient time to read data from multiple converters during a conversion period without violating the t d11 constraint (see the EXTERNAL DATACLOCK section). The sampling period must be sufficiently long to allow all data words to be read before starting a new conversion.
Note, in
the end of a READ cycle reflects the state of the TAG pin at the start of the cycle. This is true in all READ modes, including the internal clock mode. For example, when a single converter is used in internal clock mode, the state of the TAG pin determines the state of the DATA pin after all 16 bits have shifted out. When multiple converters are cascaded together, this state forms the NULL bit that separates the words. Thus, with the TAG pin of the first converter grounded as shown in
the NULL bit becomes a zero between each data word.
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ADS8509
SLAS324C – OCTOBER 2004 – REVISED APRIL 2010
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Processor
SCLK
GPIO
GPIO
SDI
R/C
(both A & B )
BUSY
(both A & B )
SYNC
(both A & B )
ADS8509A
TAG
DATA
CS
R/C
DATACLK
ADS 8509B
TAG
DATA
CS
R/C
DATACLK
TAG(A)
D
Null
Q D
A00
Q
DATACLK
TAG(B)
D
Null
Q D
B00
Q
D
A15
Q D
A16
Q
DATA (A)
D
B15
Q D
B16
Q
DATA (B)
External
DATACLK
1 2 3 4 16 17
18
19 20 21 34 35 36
DATA ( A )
DATA ( B )
A15 A14 A13
B15
B14 B13
A01 A00
B01
B00
Null
A
TAG(A) = 0
Nth Conversion Data
Null
B
A15
A14 A13 A01 A00
Null
A
TAG(A) = 0
EXT/INT tied high, CS of both converter A and B, TAG input of converter A are tied low.
.
Figure 27. Timing of TAG Feature With Single Conversion (Using External DATACLK)
ANALOG INPUTS
The ADS8509 has six analog input ranges as shown in
Table 2 . The offset and gain specifications are factory
calibrated with 0.1%, 0.25-W, external resistors as shown in
and
. The external resistors can be omitted if larger gain and offset errors are acceptable or if using software calibration. The hardware trim circuitry shown in
and
can reduce the errors to zero.
The analog input pins R1
IN
, R2
IN
, and R3
IN have ±25-V overvoltage protection. The input signal must be referenced to AGND1. This minimizes the ground loop problem typical to analog designs. The analog input should be driven by a low impedance source. A typical driving circuit using OPA627 or OPA132 is shown in
The ADS8509 can operate with its internal 2.5-V reference or an external reference. An external reference connected to pin 6 (REF) bypasses the internal reference. The external reference must drive the 4-k Ω resistor that separates pin 6 from the internal reference (see the illustration on page 1). The load varies with the difference between the internal and external reference voltages. The external reference voltage can vary from
2.3 V to 2.7 V. The internal reference is approximately 2.5 V. The reference, whether internal or external, is buffered internally with a buffer with its output on pin 5 (CAP).
The ADS8509 is factory tested with 2.2m F capacitors connected to pins 5 and 6 (CAP and REF). Each capacitor should be placed as close as possible to its pin. The capacitor on pin 6 band limits the internal reference noise. A smaller capacitor can be used but it may degrade SNR and SINAD. The capacitor on pin 5 stabilizes the reference buffer and provides switching charge to the CDAC during conversion. Capacitors smaller than 1 m
F can cause the buffer to become unstable and may not hold sufficient charge for the CDAC. The parts are tested to specifications with 2.2
m
F so larger capacitors are not necessary. The equivalent series resistor (ESR) of these compensation capacitors is also critical. The total ESR must be kept under 3 Ω . See the TYPICAL
CHARACTERISTICS section concerning how ESR affects performance.
Neither the internal reference nor the buffer should be used to drive an external load. Such loading can degrade performance. Any load on the internal reference causes a voltage drop across the 4-k Ω resistor and affects gain.
The internal buffer is capable of driving ±2-mA loads but any load can cause perturbations of the reference at the
CDAC, degrading performance. It should be pointed out that, unlike other competitor’s parts with similar input structure, the ADS8509 does not require a second high-speed amplifier used as a buffer to isolate the CAP pin from the signal dependent current in the R3
IN pin but can tolerate it if one does exist.
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The external reference voltage can vary from 2.3 V to 2.7 V. The reference voltage determines the size of the least significant bit (LSB). The larger reference voltages produce a larger LSB, which can improve SNR. Smaller reference voltages can degrade SNR.
+15 V
2.2
m
F
22 pF
GND
100 nF
2 k
W
200
W
ADS8509
R1
IN
AGND1
Vin
2 k
W
22 pF
GND
Pin 7
Pin 1
Pin 2
Pin3
−
OPA 627 or
OPA 132
+
Pin4
2.2
m
F
Pin 6
100
W
GND
2.2
m
F
33.2 k
W
R2
IN
R3
IN
CAP
REF
GND 2.2
m
F
DGND
100 nF
GND
AGND2
−15 V
GND
Figure 28. Typical Driving Circuitry (±10 V, No Trim)
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ADS8509
SLAS324C – OCTOBER 2004 – REVISED APRIL 2010
Table 2. Input Range Connections (See
and
for Complete
Information)
ANALOG
INPUT RANGE
±10 V
±5 V
±3.33 V
0 V to 10 V
0 V to 5 V
0 V to 4 V
CONNECT R1
IN
200 Ω TO
VIA CONNECT R2
IN
100 Ω TO
VIA
AGND V
IN
AGND
V
IN
AGND
AGND
V
IN
V
V
V
IN
IN
IN
AGND
AGND
CONNECT
R3 TO
CAP
CAP
CAP
AGND
V
IN
V
IN
IMPEDANCE
11.5 k Ω
6.7 k Ω
5.4 k Ω
6.7 k Ω
5.0 k Ω
5.4 k Ω
SPECIFIC FUNCTION
Initiate conversion and output data using internal clock
Initiate conversion and output data using external clock
No actions
Power down
Select output format
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CS
1 > 0
0
R/C
0
1 > 0
1 > 0
0
1 > 0
0
1 > 0
1
BUSY
1
1
1
1
1
1 > 0
0
0 x
1
0 > 1
0 x
0
0
0 > 1 x x x x x x x x x x
Table 3. Control Truth Table
EXT/INT
0
0
DATACLK
Output
Output
PWRD
0
0
SB/BTC
x x
1
1
1
Input
Input
Input
0
0 x x x x x x
1
1 x x x
Input
Input x x x x x
0
0
0
0
1 x x x x x x x
0
1
OPERATION
Initiates conversion n. Data from conversion n - 1 clocked out on DATA synchronized to 16 clock pulses output on DATACLK.
Initiates conversion n.
Initiates conversion n.
Outputs data with or without SYNC pulse. See section READING DATA.
Outputs data with or without SYNC pulse. See section READING DATA.
This is an acceptable condition.
Analog circuitry powered. Conversion can proceed..
Analog circuitry disabled. Data from previous conversion maintained in output registers.
Serial data is output in binary 2's complement format.
Serial data is output in straight binary format.
DESCRIPTI
ON
Table 4. Output Codes and Ideal Input Voltages
ANALOG INPUT
DIGITAL OUTPUT
BINARY 2'S
COMPLEMENT
(SB/BTC LOW)
BINARY CODE HEX CODE
STRAIGHT
BINARY
(SB/BTC HIGH)
BINARY CODE HEX CODE
±3.33 V 0 V to 10 V 0 V to 5 V 0 V to 4 V
Full-scale range
Least significant bit (LSB)
Full scale
(FS - 1LSB)
Midscale
One LSB below midscale
–Full scale
±10
305 m V
9.999695 V
0 V
–305 m
–10 V
V
±5
153 V 61 m
4.999847
V
0 V
3.333231 V 9.999847 V 4.999924 V 3.999939 V
0 V 5 V 2.5 V 2 V
153 m m
–5 V
V
V
102 m V
±102 µV
–3.333333 V
153 m
0 V
V
4.999847 V
76 m
2.499924 V
0 V 0 V
V
1.999939 V
0111 1111 1111 1111
0000 0000 0000 0000
1111 1111 1111 1111
1000 0000 0000 0000
7FFF
0000
FFFF
8000
1111 1111 1111 1111
1000 0000 0000 0000
0111 1111 1111 1111
0000 0000 0000 0000
FFFF
8000
7FFF
0000
20
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SLAS324C – OCTOBER 2004 – REVISED APRIL 2010
Input Range
0 V − 10 V
0 V − 5 V
Without Trim
200
Ω
R1
IN
AGND1
2.2
µ
F
+
V
IN
33.2 k
Ω
100
Ω
R2
R3
IN
IN
CAP
2.2
µ
F
+
REF
AGND2
With Trim
(Adjust Offset First at 0 V, Then Adjust Gain)
200
Ω
R1
IN
AGND1
100
Ω
33.2 k
Ω
V
IN
R2
IN
50 k
Ω
+ 5 V
50 k
Ω
2.2
µ
F
+
+ 5 V
576 k
Ω
2.2
µ
F
+
R3
IN
CAP
REF
AGND2
200
Ω
33.2 k
2.2
Ω
µ
F
+
R1
IN
AGND1
100
Ω
R2
IN
R3
IN V
IN
2.2
µ
F
+
CAP
REF
AGND2
200
Ω
R1
IN
AGND1
100
Ω
50 k
Ω
33.2 k
Ω
V
IN
R2
IN
R3
IN
+5 V
2.2
µ
F
+
+5 V
50 k
Ω
CAP
576 k
Ω
2.2
µ
F
+
REF
AGND2
0 V − 4 V
V
IN
200
Ω
100
Ω
33.2 k
Ω
2.2
µ
F
+
2.2
µ
F
+
R1
IN
AGND1
R2
IN
R3
IN
CAP
REF
AGND2
50 k
Ω
100
+5 V
Ω
V
IN
200
Ω
33.2 k
Ω
+5 V
2.2
µ
F
+
576 k
Ω
50 k
Ω
2.2
µ
F
+
R1
IN
AGND1
R2
IN
R3
IN
CAP
REF
AGND2
Figure 29. Offset/Gain Circuits for Unipolar Input Ranges
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SLAS324C – OCTOBER 2004 – REVISED APRIL 2010
Input Range
±
±
10 V
5 V
V
IN
Without Trim
200
Ω
R1
IN
AGND1
100
Ω
33.2 k
Ω
R2
IN
R3
IN
+
2.2 F
2.2 F
+
CAP
REF
AGND2
200
Ω
33.2 k
Ω
V
IN
100
Ω
R1
IN
AGND1
R2
IN
R3
IN
+
2.2
µ
F
2.2
µ
F
+
CAP
REF
AGND2
±
3.3 V
V
IN
+
100
Ω
33.2 k
Ω
2.2 F
200
Ω
R1
IN
AGND1
R2
IN
R3
IN
CAP
+
2.2 F
REF
AGND2
With Trim
(Adjust Offset First at 0 V, Then Adjust Gain)
200
Ω
V
IN
R1
IN
AGND1
100
Ω
R2
IN
R3
IN
+5 V
33.2 k
Ω
50 k
Ω
50 k
Ω
+5 V
2.2
µ
F
576 k
Ω
+
2.2
µ
F
+
CAP
REF
AGND2
200
Ω
R1
IN
50 k
Ω
+5 V
AGND1
100
Ω
V
IN
33.2 k
Ω
50 k
Ω
2.2
µ
F
+5 V
+
576 k
Ω
+
2.2
µ
F
R2
IN
R3
IN
CAP
REF
AGND2
200
Ω
V
IN
100
Ω
50 k
Ω
+5 V
33.2 k
Ω
2.2
µ
F
+5 V
+
576 k
Ω
50 k
Ω
2.2
µ
F
+
R1
IN
AGND1
R2
IN
R3
IN
CAP
REF
AGND2 www.ti.com
Figure 30. Offset/Gain Circuits for Bipolar Input Ranges
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REVISION HISTORY
Page numbers for previous revisions may differ from page numbers in the current version.
Changes from Revision B (April 2007) to Revision C Page
• Deleted Lead Temperature from Absolute Maximum Ratings ..............................................................................................
• Changed SB/BTC pin from "O" to "I" ....................................................................................................................................
• Changed location of Timing Requirements table to be closer to timing diagrams ...............................................................
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PACKAGE OPTION ADDENDUM
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PACKAGING INFORMATION
Orderable Device
ADS8509IBDB
Status
(1) Package Type Package
Drawing
ACTIVE SSOP DB
Pins Package Qty
28 50
ADS8509IBDBG4
ADS8509IBDBR
ACTIVE
ACTIVE
SSOP
SSOP
DB
DB
28
28
50
2000
ADS8509IBDBRG4
ADS8509IBDW
ADS8509IBDWG4
ADS8509IBDWR
ADS8509IBDWRG4
ADS8509IDB
ADS8509IDBG4
ADS8509IDBR
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ADS8509IDBRG4
ADS8509IDW
ADS8509IDWG4
ADS8509IDWR
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ADS8509IDWRG4 ACTIVE SOIC
(1)
The marketing status values are defined as follows:
SSOP
SOIC
SOIC
SOIC
SOIC
SSOP
SSOP
SSOP
SSOP
SOIC
SOIC
SOIC
DB
DW
DW
DW
DW
DW
DB
DB
DB
DB
DW
DW
DW
20
20
28
20
20
28
28
20
28
20
20
28
20
2000
25
25
2000
2000
2000
50
50
2000
2000
25
25
2000
Eco Plan
(2)
Green (RoHS
& no Sb/Br)
Green (RoHS
& no Sb/Br)
Green (RoHS
& no Sb/Br)
Green (RoHS
& no Sb/Br)
Green (RoHS
& no Sb/Br)
Green (RoHS
& no Sb/Br)
Green (RoHS
& no Sb/Br)
Green (RoHS
& no Sb/Br)
Green (RoHS
& no Sb/Br)
Green (RoHS
& no Sb/Br)
Green (RoHS
& no Sb/Br)
Green (RoHS
& no Sb/Br)
Green (RoHS
& no Sb/Br)
Green (RoHS
& no Sb/Br)
Green (RoHS
& no Sb/Br)
Green (RoHS
& no Sb/Br)
Lead/
Ball Finish
MSL Peak Temp
CU NIPDAU Level-2-260C-1 YEAR
(3)
CU NIPDAU Level-2-260C-1 YEAR
CU NIPDAU Level-2-260C-1 YEAR
CU NIPDAU Level-2-260C-1 YEAR
CU NIPDAU Level-2-260C-1 YEAR
CU NIPDAU Level-2-260C-1 YEAR
CU NIPDAU Level-2-260C-1 YEAR
CU NIPDAU Level-2-260C-1 YEAR
CU NIPDAU Level-2-260C-1 YEAR
CU NIPDAU Level-2-260C-1 YEAR
CU NIPDAU Level-2-260C-1 YEAR
CU NIPDAU Level-2-260C-1 YEAR
CU NIPDAU Level-2-260C-1 YEAR
CU NIPDAU Level-2-260C-1 YEAR
CU NIPDAU Level-2-260C-1 YEAR
CU NIPDAU Level-2-260C-1 YEAR
Addendum-Page 1
28-Oct-2010
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PACKAGE OPTION ADDENDUM
www.ti.com
28-Oct-2010
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material)
(3)
MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
Addendum-Page 2
www.ti.com
TAPE AND REEL INFORMATION
PACKAGE MATERIALS INFORMATION
3-Jan-2013
*All dimensions are nominal
Device
ADS8509IBDBR
ADS8509IBDWR
ADS8509IDBR
ADS8509IDWR
Package
Type
Package
Drawing
SSOP
SOIC
SSOP
SOIC
DB
DW
DB
DW
Pins
28
20
28
20
SPQ
2000
2000
2000
2000
Reel
Diameter
(mm)
Reel
Width
W1 (mm)
330.0
16.4
A0
(mm)
330.0
330.0
330.0
24.4
16.4
24.4
B0
(mm)
8.1
10.4
10.8
13.3
8.1
10.4
10.8
13.3
K0
(mm)
P1
(mm)
2.5
2.7
12.0
12.0
W
(mm)
Pin1
Quadrant
16.0
2.7
12.0
24.0
2.5
12.0
16.0
24.0
Q1
Q1
Q1
Q1
Pack Materials-Page 1
www.ti.com
PACKAGE MATERIALS INFORMATION
3-Jan-2013
*All dimensions are nominal
Device
ADS8509IBDBR
ADS8509IBDWR
ADS8509IDBR
ADS8509IDWR
Package Type Package Drawing Pins
SSOP
SOIC
SSOP
SOIC
DB
DW
DB
DW
28
20
28
20
SPQ
2000
2000
2000
2000
Length (mm) Width (mm) Height (mm)
367.0
367.0
367.0
367.0
367.0
367.0
367.0
367.0
38.0
45.0
38.0
45.0
Pack Materials-Page 2
MECHANICAL DATA
MSSO002E – JANUARY 1995 – REVISED DECEMBER 2001
PLASTIC SMALL-OUTLINE DB (R-PDSO-G**)
28 PINS SHOWN
0,65
28
0,38
0,22
15
0,15
M
0,25
0,09
5,60
5,00
8,20
7,40
1
A
14
0
°
–
ā
8
°
Gage Plane
0,25
0,95
0,55
2,00 MAX
Seating Plane
0,10
0,05 MIN
PINS **
DIM
A MAX
14
6,50
16
6,50
20 24 28 30 38
7,50 8,50 10,50 10,50 12,90
A MIN
5,90 5,90 6,90 7,90 9,90 9,90 12,30
NOTES: A. All linear dimensions are in millimeters.
B. This drawing is subject to change without notice.
C. Body dimensions do not include mold flash or protrusion not to exceed 0,15.
D. Falls within JEDEC MO-150
4040065 /E 12/01
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•
DALLAS, TEXAS 75265
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