MAX5072 2.2MHz, Dual-Output Buck or Boost Converter with POR and Power-Fail Output

MAX5072 2.2MHz, Dual-Output Buck or Boost Converter with POR and Power-Fail Output
19-3503; Rev 2; 2/06
KIT
ATION
EVALU
E
L
B
A
IL
AVA
2.2MHz, Dual-Output Buck or Boost
Converter with POR and Power-Fail Output
32 Thin QFN-EP*
T3255-4
(5mm x 5mm)
*EP = Exposed pad.
Ordering Information continued at end of data sheet.
♦ Digital Soft-Start and Independent Converter
Shutdown
♦ SYNC Input, Power-On Reset, Manual Reset, And
Power-Fail Output
♦ Short-Circuit Protection (Buck)/Maximum DutyCycle Limit (Boost)
♦ Thermal Shutdown
♦ Thermally Enhanced 32-Pin Thin QFN Package
Dissipates up to 2.7W at +70°C
DRAIN1
DRAIN1
EN1
FB1
COMP1
RST
TOP VIEW
BST1/VDD1
Pin Configuration
24
23
22
21
20
19
18
17
PGOOD1
25
16
MR
SOURCE1
26
15
BYPASS
SOURCE1
27
14
VL
PGND
28
13
VL
12
V+
SGND
29
MAX5072
PGND
30
11
OSC
SOURCE2
31
10
PFI
SOURCE2
32
9
SYNC
1
2
3
4
5
6
7
8
PFO
PKG
CODE
♦ Switching Frequency Programmable from 200kHz
to 2.2MHz
COMP2
-40°C to +85°C
PIN-PACKAGE
♦ Clock Output for Four-Phase Operation
FB2
MAX5072ETJ
TEMP RANGE
♦ 180° Out-of-Phase Operation
EN2
PART
♦ IOUT1 and IOUT2 of 2A and 1A (Respectively) in
Buck Mode
DRAIN2
Ordering Information
♦ Each Output can be Configured in Buck or Boost
Mode
DRAIN2
Applications
xDSL Modems
xDSL Routers
Point-of-Load DC-DC Converters
♦ Two Independent Output DC-DC Converters with
Internal Power MOSFETs
BST2/VDD2
The MAX5072 is available in a thermally enhanced 32-pin
thin QFN package that can dissipate 2.7W at +70°C ambient temperature. The device is rated for operation over the
-40°C to +85°C extended, or -40°C to +125°C automotive
temperature range.
♦ 0.8V (Buck) to 28V (Boost) Output Voltage
FSEL1
The MAX5072 includes an internal digital soft-start that
reduces inrush current, eliminates output-voltage overshoot, and ensures monotonic rise in output voltage during power-up. The device includes a power-good output
and power-on reset as well as manual reset. In addition,
each converter output can be shut down individually. The
MAX5072 features a "dying gasp" output, which goes low
when the input voltage drops below a preprogrammed
voltage. Protection features include output short-circuit
protection for buck mode and maximum duty-cycle limit
for boost operation, as well as thermal shutdown.
♦ 4.5V to 5.5V or 5.5V to 23V Input Supply Voltage
Range
CLKOUT
The MAX5072 is a dual-output DC-DC converter with integrated high-side n-channel power MOSFETs. Each output
can be configured either as a buck converter or a boost
converter. The MAX5072 is designed to manage the
power requirements of xDSL modems. The wide 5.5V to
23V input voltage range allows for the use of inexpensive
AC adapters to power the device in xDSL modem applications. Each output is programmable down to 0.8V in the
buck mode and up to 28V in the boost mode with an output voltage accuracy of ±1%. In the buck mode, converter 1 and converter 2 can deliver 2A and 1A, respectively.
The output switching frequency of each converter can be
programmed from 200kHz to 2.2MHz to avoid harmonics
in the xDSL frequency band of operation. Each output
operates 180° out-of-phase, thus reducing input-capacitor ripple current, size, and cost. A SYNC input facilitates
external frequency synchronization. Moreover, a CLKOUT
output provides out-of-phase clock signal with respect to
converter 2, allowing four-phase operation using two
MAX5072 ICs in master-slave configuration.
Features
THIN QFN
________________________________________________________________ Maxim Integrated Products
For pricing, delivery, and ordering information, please contact Maxim/Dallas Direct! at
1-888-629-4642, or visit Maxim’s website at www.maxim-ic.com.
1
MAX5072
General Description
MAX5072
2.2MHz, Dual-Output Buck or Boost
Converter with POR and Power-Fail Output
ABSOLUTE MAXIMUM RATINGS
V+ to PGND............................................................-0.3V to +25V
SGND to PGND .....................................................-0.3V to +0.3V
VL to SGND...................-0.3V to the lower of +6V or (V+ + 0.3V)
BST1/VDD1, BST2/VDD2, DRAIN_, PFO, RST, PGOOD1 to
SGND .................................................................-0.3V to +30V
BST1/VDD1 to SOURCE1,
BST2/VDD2 to SOURCE2 ....................................-0.3V to +6V
SOURCE_ to SGND................................................-0.6V to +25V
EN_ to SGND ................................................-0.3V to (VL + 0.3V)
CLKOUT, BYPASS, OSC, FSEL1, COMP1,
COMP2, PFI, MR, SYNC, FB_ to SGND....-0.3V to (VL + 0.3V)
SOURCE1, DRAIN1 Peak Current ..............................5A for 1ms
SOURCE2, DRAIN2 Peak Current ..............................3A for 1ms
VL, BYPASS to SGND Short Circuit............................Continuous
Continuous Power Dissipation (TA = +70°C)
32-Pin Thin QFN (derate 21.3mW/°C above +70°C).....2758mW*
Package Junction-to-Case Thermal Resistance (θJC).......2°C/W
Operating Temperature Ranges:
MAX5072ETJ (TMIN to TMAX)...........................-40°C to +85°C
MAX5072ATJ (TMIN to TMAX).........................-40°C to +125°C
Junction Temperature ......................................................+150°C
Storage Temperature Range .............................-65°C to +150°C
Lead Temperature (soldering, 10s) .................................+300°C
*As per JEDEC51 standard.
Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional
operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to
absolute maximum rating conditions for extended periods may affect device reliability.
ELECTRICAL CHARACTERISTICS
(V+ = VL = 5.2V or V+ = 5.5V to 23V, EN_ = VL, SYNC = GND, IVL = 0, PGND = SGND, CBYPASS = 0.22µF, CVL = 4.7µF (ceramic),
ROSC = 10kΩ (circuit of Figure 1), TA = TJ = TMIN to TMAX, unless otherwise noted.) (Note 1)
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
SYSTEM SPECIFICATIONS
Input Voltage Range
V+
Operating Supply Current
IQ
V+ Standby Supply Current
Efficiency
ISTBY
η
(Note 2)
5.5
23
VL = V+
4.5
5.5
VL unloaded, no switching,
VFB_ = 1V, V+ = 12V, ROSC = 60kΩ
2.2
1.2
EN_ = 0, MR, PFO, and PGOOD_ floating,
V+ = 12V, ROSC = 60kΩ (MAX5072ETJ)
0.6
1.4
EN_ = 0, MR, PFO, and PGOOD_ floating,
V+ = 12V, ROSC = 60kΩ (MAX5072ATJ)
0.6
1.4
VOUT1 = 3.3V at 1.5A,
VOUT2 = 2.5V at 0.75A
(fSW = 1.25MHz)
V
mA
mA
V+ = VL = 5V
82
V+ = 12V
80
V+ = 16V
78
%
STARTUP/VL REGULATOR
VL Undervoltage Lockout Trip
Level
UVLO
VL falling
3.95
VL Undervoltage Lockout
Hysteresis
VL Output Voltage
4.1
4.25
175
VL
V
mV
V+ = 5.5V to 23V, ISOURCE = 0 to 40mA
4.9
5.2
5.5
IBYPASS = 0, ROSC = 60kΩ (MAX5072ETJ)
1.98
2.00
2.02
IBYPASS = 0, ROSC = 60kΩ (MAX5072ATJ)
1.975
2.00
2.025
0
2
10
V
BYPASS OUTPUT
BYPASS Voltage
BYPASS Load Regulation
VBYPASS
∆VBYPASS
0 ≤ IBYPASS ≤ 50µA, ROSC = 60kΩ
V
mV
SOFT-START
Digital Ramp Period
Soft-Start Steps
2
Internal 6-bit DAC
2048
fOSC
clock
cycles
64
steps
_______________________________________________________________________________________
2.2MHz, Dual-Output Buck or Boost
Converter with POR and Power-Fail Output
(V+ = VL = 5.2V or V+ = 5.5V to 23V, EN_ = VL, SYNC = GND, IVL = 0, PGND = SGND, CBYPASS = 0.22µF, CVL = 4.7µF (ceramic),
ROSC = 10kΩ (circuit of Figure 1), TA = TJ = TMIN to TMAX, unless otherwise noted.) (Note 1)
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
250
nA
VOLTAGE-ERROR AMPLIFIER
FB_ Input Bias Current
IFB
FB_ Input Voltage Set Point
FB_ to COMP_
Transconductance
gM
0°C ≤ TA ≤+70°C
0.792
0.8
0.808
-40°C ≤ TA ≤+85°C
0.788
0.8
0.812
-40°C ≤ TJ ≤+125°C (MAX5072ATJ only)
0.788
0.8
0.812
0°C to +85°C
1.25
2.00
2.70
-40°C to +85°C
1.2
2.0
2.9
-40°C to +125°C (MAX5072ATJ only)
1.2
2.0
2.9
ISWITCH = 100mA,
VBST1/VDD1 to VSOURCE1 = 5.2V
(MAX5072ETJ)
195
290
ISWITCH = 100mA,
VBST1/VDD1 to VSOURCE1 = 5.2V
(MAX5072ATJ)
195
330
V
mS
INTERNAL MOSFETS
On-Resistance Converter 1
RON1
On-Resistance Converter 2
RON2
mΩ
ISWITCH = 100mA,
VBST1/VDD1 to VSOURCE1 = 4.5V
(MAX5072ETJ)
200
315
ISWITCH = 100mA,
VBST1/VDD1 to VSOURCE1 = 4.5V
(MAX5072ATJ)
200
350
ISWITCH = 100mA,
VBST2/VDD2 to VSOURCE2 = 5.2V
330
630
ISWITCH = 100mA,
VBST2/VDD2 to VSOURCE2 = 4.5V
350
mΩ
690
Minimum Converter 1 Output
Current
IOUT1
VOUT1 = 3.3V, V+ = 12V (Note 3)
2
A
Minimum Converter 2 Output
Current
IOUT2
VOUT2 = 2.5V, V+ = 12V (Note 3)
1
A
Converter 1 MOSFET Leakage
Current
ILK1
EN1 = 0V, VDS = 23V
10
µA
Converter 2 MOSFET Leakage
Current
ILK2
EN2 = 0V, VDS = 23V
10
µA
INTERNAL SWITCH CURRENT LIMIT
Current-Limit Converter 1
ICL1
Current-Limit Converter 2
ICL2
V+ = 12V (MAX5072ETJ)
2.3
3
4.3
V+ = 12V (MAX5072ATJ)
2.3
3
4.6
MAX5072ETJ
1.38
1.8
2.10
MAX5072ATJ
1.38
1.8
2.10
A
A
_______________________________________________________________________________________
3
MAX5072
ELECTRICAL CHARACTERISTICS (continued)
MAX5072
2.2MHz, Dual-Output Buck or Boost
Converter with POR and Power-Fail Output
ELECTRICAL CHARACTERISTICS (continued)
(V+ = VL = 5.2V or V+ = 5.5V to 23V, EN_ = VL, SYNC = GND, IVL = 0, PGND = SGND, CBYPASS = 0.22µF, CVL = 4.7µF (ceramic),
ROSC = 10kΩ (circuit of Figure 1), TA = TJ = TMIN to TMAX, unless otherwise noted.) (Note 1)
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
SYNC = SGND, fSW = 1.25MHz
84
86
95
SYNC = SGND, fSW = 2.2MHz
84
86
95
2200
kHz
1250
1375
kHz
INTERNAL OSCILLATOR/SYNC
Maximum Duty Cycle
DMAX
Switching Frequency Range
fSW
Each converter
200
Switching Frequency
fSET
ROSC = 10kΩ, each converter
1125
Switching Frequency Accuracy
SYNC Frequency Range
fSYNC
SYNC High Threshold
VSYNCH
SYNC Low Threshold
VSYNCL
SYNC Input MIN Pulse Width
tSYNCIN
Clock Output Phase Delay
CLKOUT
PHASE
SYNC to SOURCE 1 Phase Delay
%
5.6kΩ ≤ ROSC ≤ 56kΩ, 1%, each converter
-15
+15
%
SYNC input frequency is twice the
individual converter frequency
400
4400
kHz
2.4
V
0.8
ROSC = 60kΩ, 1%, with respect to
converter 2/SOURCE2 waveform
SYNCPHASE ROSC = 60kΩ, 1%
Clock Output High Level
VCLKOUTH
VL = 5.2V, sourcing 5mA
Clock Output Low Level
VCLKOUTL
VL = 5.2V, sinking 5mA
FSEL1
FSEL1 Input High Threshold
VIH
V+ = VL = +5.2V
FSEL1 Input Low Threshold
VIL
V+ = VL = +5.2V
VIH
VIL
V+ = VL = +5.2V
V+ = VL = +5.2V
V
100
ns
45
degrees
45
degrees
4
V
0.4
2.4
V
V
0.8
V
0.8
V
V
250
nA
10
µs
EN_ INPUTS
EN_ Input High Threshold
EN_ Input Low Threshold
EN_ Bias Current
2.4
1.8
1.2
IB(EN)
MANUAL RESET (MR) AND POWER-ON-RESET (RST)
MR Minimum Pulse Width
tMR
Maximum glitch pulse width allowed for
RST to remain high
MR Glitch Immunity
MR to RST Propagation Delay
MR Input High Threshold
MR Input Low Threshold
MR Internal Pullup Resistor
tMD
VIH
VIL
RMR
V+ = VL = +5.2V
V+ = VL = +5.2V
Power-On-Reset Threshold
VTH
RST goes high 180ms after VOUT1 and
VOUT2 cross this threshold
FB_ to RST Propagation Delay
tFD
FB overdrive from 0.8V to 0.6V
RST Active Timeout Period
tRP
RST Output Voltage
VRST_
RST Output Leakage Current
IRSTLK
4
100
ns
1
µs
V
V
kΩ
2.4
0.8
44
90
92.5
140
200
95
% VOUT
ms
ISINK = 3mA (MAX5072ETJ)
360
0.4
ISINK = 3mA (MAX5072ATJ)
0.52
1.1
V+ = VL = 5.2V, VRST = 23V, VFB_ = 0.8V
_______________________________________________________________________________________
µs
1
V
µA
2.2MHz, Dual-Output Buck or Boost
Converter with POR and Power-Fail Output
(V+ = VL = 5.2V or V+ = 5.5V to 23V, EN_ = VL, SYNC = GND, IVL = 0, PGND = SGND, CBYPASS = 0.22µF, CVL = 4.7µF (ceramic),
ROSC = 10kΩ (circuit of Figure 1), TA = TJ = TMIN to TMAX, unless otherwise noted.) (Note 1)
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
90
92.5
95
% VOUT
POWER-GOOD OUTPUT (PGOOD1)
PGOOD1 Threshold
PGOOD1VTH
PGOOD1 Output Voltage
VPGOOD1
PGOOD1 Output Leakage Current
ILKPGOOD1
PGOOD1 goes high after VOUT crosses
PGOOD1 threshold
ISINK = 3mA (MAX5072ETJ)
0.4
ISINK = 3mA (MAX5072ATJ)
0.52
V+ = VL = 5.2V, VPGOOD1 = 23V, VFB1 = 1V
V
1
µA
0.80
V
mV
500
nA
DYING GASP POWER-FAIL INPUT (PFI), POWER-FAIL OUTPUT (PFO)
PFI Trip Level
PFI Hysteresis
VTH
VTHH
PFI falling
PFI Input Bias Current
IB(PFI)
VPFI = 0.75V
PFI Glitch Immunity
PFI to PFO Propagation Delay
PFO Output Low Voltage
tPFD
VPFO
0.76
0.78
20
100mV overdrive
35
50mV overdrive
ISINK = 3mA (MAX5072ETJ)
35
µs
µs
0.4
ISINK = 3mA (MAX5072ATJ)
0.52
1
V
PFO Output Leakage Current
ILKPFO
V+ = VL = 5.2V, VPFO = 5.5V, VPFI = 1V
THERMAL MANAGEMENT
Thermal Shutdown
µA
TSHDN
Junction temperature
+150
°C
Thermal Hysteresis
THYST
Junction temperature
30
°C
Note 1: Specifications at -40°C are guaranteed by design and not production tested.
Note 2: Operating supply range (V+) is guaranteed by VL line regulation test. Connect V+ to VL for 5V operation.
Note 3: Output current may be limited by the power dissipation of the package, see the Power Dissipation section in the
Applications Information.
_______________________________________________________________________________________
5
MAX5072
ELECTRICAL CHARACTERISTICS (continued)
Typical Operating Characteristics
(V+ = VL = 5.2V, TA = +25°C, unless otherwise noted.)
VIN = 12.0V
50
VIN = 16.0V
40
70
60
30
30
20
20
VOUT = 3.3V
fSW = 2.2MHz
10
VIN = 12.0V
50
VIN = 16.0V
40
0.3
0.4
0.6
0.7
0.8
0.9
40
1.0
VOUT = 12V
fSW = 2.2MHz
0.02
0.08
0.20
0.14
LOAD (A)
LOAD (A)
OUTPUT2 VOLTAGE (BUCK CONVERTER)
vs. LOAD CURRENT
VL OUTPUT VOLTAGE vs. CONVERTER
SWITCHING FREQUENCY
5.50
5.45
BOTH CONVERTERS SWITCHING
5.40
5.35
VL (V)
2.55
5.30
VIN = 23V
5.25
5.20
2.50
5.15
3.25
5.10
VIN = 5.5V
5.05
2.45
3.20
0
0.5
1.0
1.5
5.00
0
2.0
0.25
0.50
0.75
0.1
1.00
0.6
1.1
1.6
2.1
LOAD (A)
LOAD (A)
SWITCHING FREQUENCY (fSW)(MHz)
VL DROPOUT VOLTAGE vs. EACH CONVERTER
SWITCHING FREQUENCY
EACH CONVERTER SWITCHING
FREQUENCY vs. ROSC
EACH CONVERTER SWITCHING
FREQUENCY vs. TEMPERATURE
0.25
VIN = 5V
0.20
0.15
0.10
VIN = 4.5V
0.05
0
1
0.1
0
0.5
1.0
1.5
2.0
SWITCHING FREQUENCY (fSW) (MHz)
2.5
2.6
MAX5072 toc09
10.00
SWITCHING FREQUENCY (fSW) (MHz)
0.30
10
MAX5072 toc08
VIN = 5.5V
SWITCHING FREQUENCY (fSW) (MHz)
MAX5072 toc07
0.35
6
MAX5072 toc03
50
10
MAX5072 toc05
MAX5072 toc04
3.30
0.5
2.60
OUTPUT2 VOLTAGE (V)
OUTPUT1 VOLTAGE (V)
3.35
VIN = 3.3V
60
0
0.2
OUTPUT1 VOLTAGE (BUCK CONVERTER)
vs. LOAD CURRENT
70
20
VOUT = 2.5V
fSW = 2.2MHz
LOAD (A)
3.40
80
0
0.2 0.4 0.6 0.8 1.0 1.2 1.4 1.6 1.8 2.0
VIN = 5.0V
90
30
10
0
100
EFFICIENCY (%)
60
VIN = 5V
80
70
EFFICIENCY (%)
EFFICIENCY (%)
80
90
OUTPUT2 EFFICIENCY (BOOST CONVERTER)
vs. LOAD CURRENT
MAX5072 toc02
VIN = 5V
90
100
MAX5072 toc01
100
OUTPUT2 EFFICIENCY (BUCK CONVERTER)
vs. LOAD CURRENT
MAX5072 toc06
OUTPUT1 EFFICIENCY (BUCK CONVERTER)
vs. LOAD CURRENT
DROPOUT VOLTAGE (V)
MAX5072
2.2MHz, Dual-Output Buck or Boost
Converter with POR and Power-Fail Output
2.2MHz
1.25MHz
1.00
0.6MHz
0.3MHz
0.10
0
20
40
ROSC (kΩ)
60
80
-50
0
50
TEMPERATURE (°C)
_______________________________________________________________________________________
100
150
2.2MHz, Dual-Output Buck or Boost
Converter with POR and Power-Fail Output
LINE-TRANSIENT RESPONSE
(BUCK CONVERTER)
CONVERTER 2 LOAD-TRANSIENT RESPONSE
(BUCK CONVERTER)
CONVERTER 1 LOAD-TRANSIENT RESPONSE
(BUCK CONVERTER)
MAX5072 toc10
MAX5072 toc12
MAX5072 toc11
VOUT1 = 3.3V
AC-COUPLED
400mV/div
VIN
5V/div
VOUT2 = 2.5V
AC-COUPLED
100mV/div
VOUT1 = 3.3V
AC-COUPLED
200mV/div
0V
VOUT1 = 3.3V/1.5A
AC-COUPLED
200mV/div
IOUT2
500mA/div
IOUT1
1A/div
0A
VOUT2 = 2.5V/0.75A
AC-COUPLED
200mV/div
1ms/div
0A
100µs/div
100µs/div
LOAD-TRANSIENT RESPONSE
(BOOST CONVERTER)
SOFT-START/SOFT-STOP
MAX5072 toc13
MAX5072 toc14
VOUT1 = 3.3V
AC-COUPLED
200mV/div
ENABLE
5V/div
0V
VOUT2 = 12V
AC-COUPLED
200mV/div
VOUT1 = 3.3V/1A
2V/div
0V
VOUT2 = 2.5V/0.5A
2V/div
IOUT2
50mA/div
0V
0A
V+ = VL = 5.2V
2ms/div
100µs/div
RST ACTIVE TIMEOUT PERIOD
OUT-OF-PHASE OPERATION
MAX5072 toc15
MAX5072 toc16
0V
ENABLE
5V/div
0V
0V RST
5V/div
SOURCE 1
5V/div
0V
VOUT1
0V 5V/div
VOUT2
2V/div
0V
40ms/div
SOURCE 2
5V/div
0V
INPUT RIPPLE
AC-COUPLED
20mV/div
CLKOUT
5V/div
100ns/div
_______________________________________________________________________________________
7
MAX5072
Typical Operating Characteristics (continued)
(V+ = VL = 5.2V, TA = +25°C, unless otherwise noted.)
Typical Operating Characteristics (continued)
(V+ = VL = 5.2V, TA = +25°C, unless otherwise noted.)
MAX5072 toc17
SYNC
5V/div
1.8
SOURCE 1
5V/div
1.4
ROSC = 10kΩ
VOUT1 RIPPLE
AC-COUPLED
20mV/div
0V
ISTBY (mA)
0V
0V
MAX5072 toc18
V+ STANDBY SUPPLY CURRENT (ISTBY)
vs. TEMPERATURE
EXTERNAL SYNCHRONIZATION
1.0
ROSC = 60kΩ
0.6
CLKOUT
5V/div
0.2
-40
200ns/div
-7
26
59
92
125
TEMPERATURE (°C)
OUTPUT1 VOLTAGE (BUCK CONVERTER)
vs. TEMPERATURE
V+ SWITCHING SUPPLY CURRENT (ISUPPLY)
vs. TEMPERATURE
3.38
3.36
OUTPUT1 VOLTAGE (V)
fSW = 2.2MHz
25
fSW = 1.25MHz
20
fSW = 600kHz
15
MAX5072 toc20
30
ISUPPLY (mA)
3.40
MAX5072 toc19
35
fSW = 300kHz
NO LOAD
3.34
3.32
3.30
50% LOAD
3.28
3.26
3.24
10
3.22
5
3.20
-7
26
59
92
-50
125
0
50
100
TEMPERATURE (°C)
TEMPERATURE (°C)
OUTPUT2 VOLTAGE (BUCK CONVERTER)
vs. TEMPERATURE
OUTPUT LOAD CURRENT LIMIT
vs. TEMPERATURE
50% LOAD
2.55
NO LOAD
2.50
2.45
3.00
VIN = 5.5V
fSW = 2.2MHz
2.75
OUTPUT CURRENT LIMIT (A)
MAX5072 toc21
2.60
150
MAX5072 toc22
-40
OUTPUT2 VOLTAGE (V)
MAX5072
2.2MHz, Dual-Output Buck or Boost
Converter with POR and Power-Fail Output
2.50
OUTPUT1
2.25
2.00
OUTPUT2
1.75
1.50
1.25
1.00
2.40
-50
0
50
TEMPERATURE (°C)
8
100
150
-40
-5
30
65
TEMPERATURE (°C)
_______________________________________________________________________________________
100
2.2MHz, Dual-Output Buck or Boost
Converter with POR and Power-Fail Output
FOUR-PHASE OPERATION
(SEE FIGURE 3)
MANUAL RESET (MR)
MAX5072 toc23
MAX5072 toc24
MR
5V/div
RST
5V/div
0V
SOURCE 1
(MASTER)
SOURCE 2
VOUT1 = 3.3V
5V/div
0V (MASTER)
VOUT2 = 2.5V
5V/div
0V
SOURCE 1
(SLAVE)
SOURCE 2
(SLAVE)
100ms/div
400ns/div
Pin Description
PIN
1
2
NAME
CLKOUT
FUNCTION
Clock Output. CLKOUT is 45° phase-shifted with respect to converter 2 (SOURCE2, Figure 3). Connect
CLKOUT (master) to the SYNC of a second MAX5072 (slave) for a four-phase converter.
Buck Converter Operation—Bootstrap Flying-Capacitor Connection for Converter 2. Connect BST2/VDD2
to an external ceramic capacitor and diode according to the Standard Application Circuit (Figure 1).
BST2/VDD2
Boost Converter Operation—Driver Bypass Capacitor Connection. Connect a low-ESR 0.1µF ceramic
capacitor from BST2/VDD2 to PGND (Figure 9).
3, 4
DRAIN2
Connection to Converter 2 Internal MOSFET Drain. Buck converter operation—use the MOSFET as a
high-side switch and connect DRAIN2 to the input supply. Boost converter operation—use the MOSFET
as a low-side switch and connect DRAIN2 to the inductor and diode junction (Figure 9).
5
EN2
Active-High Enable Input for Converter 2. Drive EN2 low to shut down converter 2, drive EN2 high for normal
operation. Use EN2 in conjunction with EN1 for supply sequencing. Connect to VL for always-on operation.
6
FB2
Feedback Input for Converter 2. Connect FB2 to a resistive divider between converter 2’s output and SGND
to adjust the output voltage. To set the output voltage below 0.8V, connect FB2 to a resistive voltage-divider
from BYPASS to regulator 2’s output (Figure 6). See the Setting the Output Voltage section.
7
COMP2
Compensation Connection for Converter 2. See the Compensation section to compensate converter 2’s
control loop.
8
PFO
Dying Gasp Comparator Output. The PFO open-drain output goes low when PFI falls below the 0.78V reference.
9
SYNC
External Clock Synchronization Input. Connect SYNC to a 400kHz to 4400kHz clock to synchronize the
switching frequency with the system clock. Each converter frequency is one half the frequency applied to
SYNC. Connect SYNC to SGND when not used.
10
PFI
Dying Gasp Comparator Noninverting Input. Connect a resistor-divider from the input supply to PFI. PFI
forces PFO low when VPFI falls below 0.78V. The PFI comparator has a 20mV (typ) hysteresis. This is an
uncommitted comparator and can be used for any protection feature such as OVP or POWER-GOOD.
_______________________________________________________________________________________
9
MAX5072
Typical Operating Characteristics (continued)
(V+ = VL = 5.2V, TA = +25°C, unless otherwise noted.)
2.2MHz, Dual-Output Buck or Boost
Converter with POR and Power-Fail Output
MAX5072
Pin Description (continued)
PIN
FUNCTION
Oscillator Frequency Set Input. Connect a resistor from OSC to SGND (ROSC) to set the switching
frequency (see the Oscillator section). Set ROSC for equal to or lower oscillator frequency than the SYNC
input frequency when using external synchronization (0.2fSYNC < fOSC < 1.2fSYNC). ROSC is still required
when an external clock is connected to the SYNC input.
11
OSC
12
V+
Input Supply Voltage. V+ voltage range from 5.5V to 23V. Connect the V+ and VL together for 4.5V to
5.5V input operation. Bypass with a minimum 0.1µF ceramic capacitor to SGND.
13, 14
VL
Internal 5.2V Linear Regulator Output. Use VL to drive the high-side switch at BST1/VDD1 and
BST2/VDD2. Bypass VL with a 0.1µF capacitor to PGND and a 4.7µF ceramic capacitor to SGND.
15
BYPASS
16
MR
Active-Low Manual Reset Input. Drive MR low to initiate a reset. RST remains asserted while MR is low
and for 180ms (tRP) after MR returns high. MR requires no external debounce circuitry. MR is internally
pulled high by a 44kΩ resistor and can be left open if not used.
17
RST
Open-Drain Reset Output. RST remains low when either output voltage is below 92.5% of its regulation
point or while MR is low. After soft-start is completed and both outputs exceed 92.5% of their nominal
output voltage, RST becomes high impedance after a 180ms (typ) delay. RST remains high impedance
as long as both outputs maintain regulation.
18
COMP1
19
FB1
Feedback Input for Converter 1. Connect FB1 to a resistive divider between converter 1’s output and SGND
to program the output voltage. To set the output voltage below 0.8V, connect FB1 to a resistive voltagedivider from BYPASS to regulator 1’s output (Figure 6). See the Setting the Output Voltage section.
20
EN1
Active-High Enable Input for Converter 1. Drive EN1 low to shut down converter 1, drive EN1 high for normal
operation. Use EN1 in conjunction with EN2 for supply sequencing. Connect to VL for always-on operation.
DRAIN1
Connection to the Converter 1 Internal MOSFET Drain.
Buck converter operation—use the MOSFET as a high-side switch and connect DRAIN1 to the input supply.
Boost converter operation—use the MOSFET as a low-side switch and connect DRAIN1 to the inductor
and diode junction.
21, 22
23
10
NAME
2.0V Output. Bypass to SGND with a 0.22µF or greater ceramic capacitor.
Compensation Connection for Converter 1 (See the Compensation Section)
Buck Converter Operation—Bootstrap Flying-Capacitor Connection for Converter 1. Connect BST1/VDD1
to an external ceramic capacitor and diode according to the Standard Application Circuit (Figure 1).
BST1/VDD1
Boost Converter Operation—Driver Bypass Capacitor Connection. Connect a low-ESR 0.1µF ceramic
capacitor from BST1/VDD1 to PGND (Figure 9).
Converter 1 Frequency Select Input. Connect FSEL1 to VL for normal operation. Connect FSEL1 to SGND
to reduce converter 1’s switching frequency to 1/2 converter 2’s switching frequency (converter 1
switching frequency will be 1/4 the SYNC frequency). Do not leave FSEL1 unconnected.
24
FSEL1
25
PGOOD1
Converter 1 Power-Good Output. Open-drain output goes low when converter 1’s output falls below
92.5% of its set regulation voltage. Use PGOOD1 and EN2 to sequence the converters.
26, 27
SOURCE1
Connection to the Converter 1 Internal MOSFET Source.
Buck Converter Operation—connect SOURCE1 to the switched side of the inductor as shown in Figure 1.
Boost Converter Operation—connect SOURCE1 to PGND.
______________________________________________________________________________________
2.2MHz, Dual-Output Buck or Boost
Converter with POR and Power-Fail Output
PIN
NAME
FUNCTION
28, 30
PGND
Power Ground. Connect rectifier diode anode, input capacitor negative, output capacitor negative, and
VL bypass capacitor returns to PGND.
29
SGND
Signal Ground. Connect SGND to the exposed pad. Connect SGND and PGND together at a single point.
31, 32
SOURCE2
EP
SGND
Connection to the Converter 2 Internal MOSFET Source.
Buck Converter Operation—connect SOURCE2 to the switched side of the inductor as shown in Figure 1.
Boost Converter Operation—connect SOURCE2 to PGND (Figure 9).
Exposed Paddle. Connect to SGND. Solder EP to the SGND plane for better thermal performance.
PGOOD1
VL
OUTPUT
2.5V/1A
OUTPUT
3.3V/2A
32
VL
CLOCK
OUT
31
30
29
28
2 BST2/VDD2
SGND
EP
3 DRAIN2
5 EN2
DYING GASP
8 PFO
SYNC PFI
9
10
VL
BST1/VDD1 23
ON
OFF
EN1 20
FB1 19
COMP1 18
7 COMP2
PFO
25
DRAIN1 21
MAX5072
6 FB2
VL
26
DRAIN1 22
4 DRAIN2
ON
OFF
27
SOURCE2 PGND SGND PGND SOURCE1 PGOOD1
FSEL1 24
1 CLKOUT
OSC
11
V+
12
VL
13
VOUT1
RST 17
VL BYPASS MR
14 15 16
SGND
µP RESET INPUT
SYSTEM
CLOCK
MANUAL
RESET
VIN = 5.5V TO 23V
PGND
SGND*
*CONNECT PGND AND SGND TOGETHER AT ONE POINT NEAR THE
RETURN TERMINALS OF THE V+ AND VL BYPASS CAPACITORS.
Figure 1. MAX5072 Dual Buck Regulator Application Circuit
______________________________________________________________________________________
11
MAX5072
Pin Description (continued)
MAX5072
2.2MHz, Dual-Output Buck or Boost
Converter with POR and Power-Fail Output
Detailed Description
PWM Controller
The MAX5072 converter uses a pulse-width modulation
(PWM) voltage-mode control scheme for each out-ofphase controller. It is nonsynchronous rectification and
uses an external low-forward-drop Schottky diode for
rectification. The controller generates the clock signal
by dividing down the internal oscillator or the SYNC
input when driven by an external clock, so each controller’s switching frequency equals half the oscillator
frequency (fSW = fOSC / 2). An internal transconductance error amplifier produces an integrated error voltage at the COMP pin, providing high DC accuracy. The
voltage at COMP sets the duty cycle using a PWM
comparator and a ramp generator. At each rising edge
of the clock, converter 1’s high-side n-channel MOSFET
turns on and remains on until either the appropriate or
maximum duty cycle is reached, or the maximum current limit for the switch is detected. Converter 2 operates out-of-phase, so the second high-side MOSFET
turns on at each falling edge of the clock.
In the case of buck operation (Figure 1), during each
high-side MOSFET’s on-time, the associated inductor
current ramps up. During the second half of the switching cycle, the high-side MOSFET turns off and forward
biases the Schottky rectifier. During this time, the
SOURCE voltage is clamped to 0.4V (V D ) below
ground. The inductor releases the stored energy as its
current ramps down, and provides current to the output. The bootstrap capacitor is also recharged from the
inductance energy when the MOSFET turns off. The circuit goes in discontinuous conduction mode operation
at light load, when the inductor current completely discharges before the next cycle commences. Under
overload conditions, when the inductor current exceeds
the peak current limit of the respective switch, the highside MOSFET turns off quickly and waits until the next
clock cycle.
In the case of boost operation, the MOSFET is a lowside switch (Figure 9). During each on-time, the inductor current ramps up. During the second half of the
switching cycle, the low-side switch turns off and forward biases the Schottky diode. During this time the
DRAIN voltage is clamped to 0.4V (VD) above VOUT_
and the inductor provides energy to the output as well
as replenishes the output capacitor charge.
Internal Oscillator/Out-of-Phase Operation
The internal oscillator generates the 180° out-of-phase
clock signal required by each regulator. The internal
oscillator frequency is programmable from 400kHz to
4.4MHz using a single 1% resistor at ROSC. Use the following equation to calculate ROSC:
12
ROSC =
25 × 109
fOSC
where fOSC is the internal oscillator frequency in hertz
and ROSC in ohms.
The two independent regulators in the MAX5072 switch
180° out-of-phase to reduce input filtering requirements, to reduce electromagnetic interference (EMI),
and to improve efficiency. This effectively lowers component cost and saves board space, making the
MAX5072 ideal for cost-sensitive applications.
With dual synchronized out-of-phase operation, the
MAX5072’s high-side MOSFETs turn on 180° out-ofphase. The instantaneous input current peaks of both
regulators do not overlap, resulting in reduced RMS ripple current and input voltage ripple. This reduces the
required input capacitor ripple current rating, allows for
fewer or less expensive capacitors, and reduces
shielding requirements for EMI. The out-of-phase waveforms in the Typical Operating Characteristics demonstrate synchronized 180° out-of-phase operation.
Synchronization (SYNC)/Clock
Output (CLKOUT)
The main oscillator can be synchronized to the system
clock by applying an external clock (fSYNC) at SYNC.
The fSYNC frequency must be twice the required operating frequency of an individual converter. Use a TTL
logic signal for the external clock with at least a 100ns
pulse width. ROSC is still required when using external
synchronization. Program the internal oscillator frequency so 0.2f SYNC < f OSC < 1.2f SYNC . The rising
edge of fSYNC synchronizes the turn-on edge of internal
MOSFET (see Figure 3).
ROSC =
25 × 109
fOSC
where fOSC is the internal oscillator frequency in hertz
and ROSC in ohms, fOSC = 2 x fSW.
Two MAX5072s can be connected in master-slave configuration for four ripple-phase operation. The MAX5072
provides a clock output (CLKOUT) that is 45° phaseshifted with respect to the internal switch turn-on edge.
Feed the CLKOUT of the master to the SYNC input of
the slave. The effective input ripple switching frequency
shall be four times the individual converter’s switching
frequency. When driving the master converter using
external clock at SYNC, set the clock duty cycle to 50%
for a 90° phase-shifted operation.
______________________________________________________________________________________
2.2MHz, Dual-Output Buck or Boost
Converter with POR and Power-Fail Output
LDO
MAX5072
VL
CONVERTER 1
VL
DEAD-TIME
CONTROL
OSCILLATOR
BST1/VDD1
FREQUENCY
FOLDBACK
DRAIN1
BYPASS
Q
N
Q
F_SEL1
FREQUENCY
DIVIDER
SOURCE1
Q
PGOOD1
fSW/4
VREF
VREF
DIGITAL
SOFT-START
EN1
FB1
COMP1
VCC
0.5VREF
0.92VREF
SYNC
CKO
OSC
VCC
VCC
MAIN
OSCILLATOR
RESET
180mS
DELAY
DEBOUNCE
MR
VREF
OPEN
DRAIN
PFO
35µS GLITCH
IMMUNITY
PFI
BST2/VDD2
VL
DRAIN2
RESET2
OSCILLATOR
VDD2
CONVERTER 2
EN2
SOURCE2
FB2
COMP2
Figure 2. Functional Diagram
______________________________________________________________________________________
13
MAX5072
V+
MAX5072
2.2MHz, Dual-Output Buck or Boost
Converter with POR and Power-Fail Output
VIN
CIN
V+
V+
DRAIN2
OUTPUT2
DRAIN1
SOURCE2
OUTPUT1
SOURCE1
OUTPUT4
DRAIN2
DRAIN1
SOURCE2
OUTPUT3
SOURCE1
DUTY CYCLE = 50%
CLKIN
SYNC
CLKOUT
SYNC
MASTER
SLAVE
SYNC
CLKOUT
(MASTER)
CLKOUT
(SLAVE)
SOURCE1
(MASTER)
SYNCPHASE
CLKOUTPHASE
SOURCE2
(MASTER)
SOURCE1
(SLAVE)
SOURCE2
(SLAVE)
CIN (RIPPLE)
Figure 3. Synchronized Controllers
Frequency Select (FSEL1)
Sometimes it is necessary to operate the converter at a
lower switching frequency to keep the losses low for
lower power dissipation. However, it is not possible to
have different frequencies for two converters operating
out-of-phase. Also, frequency beating may occur if the
individual converter frequencies are not selected carefully. To avoid these issues, and still achieve the lower
14
power dissipation in the package, the MAX5072 provides a frequency select (FSEL1) pin. Connecting
FSEL1 to ground reduces the switching frequency of
converter 1 to 1/2 the switching frequency of converter
2 and 1/4th of the internal oscillator switching frequency. In this case, the input capacitor ripple frequency is
1.5 times the converter 2 switching frequency and also
has unsymmetrical ripple waveform.
______________________________________________________________________________________
2.2MHz, Dual-Output Buck or Boost
Converter with POR and Power-Fail Output
All internal control circuitry operates from an internally
regulated nominal voltage of 5.2V (VL). At higher input
voltages (V+) of 5.5V to 23V, VL is regulated to 5.2V. At
5.5V or below, the internal linear regulator operates in
dropout mode, where VL follows V+. Depending on the
load on VL, the dropout voltage can be high enough to
reduce VL below the undervoltage lockout (UVLO)
threshold.
For input voltages of less than 5.5V, connect V+ and VL
together. The load on VL is proportional to the switching frequency of converter 1 and converter 2. See the
VL Dropout Voltage vs. Each Converter Switching
Frequency graph in the Typical Operating
Characteristics. For input voltage ranges higher than
5.5V, use the internal regulator.
Bypass V+ to SGND with a low-ESR, 0.1µF or greater
ceramic capacitor placed close to the MAX5072. Current
spikes from VL may disturb internal circuitry powered by
VL. Bypass VL with a low-ESR, ceramic 0.1µF capacitor
to PGND and a 4.7µF capacitor to SGND.
Undervoltage Lockout/Soft-Start
The MAX5072 includes an undervoltage lockout with
hysteresis and a power-on-reset circuit for smooth converter turn-on and monotonic rise of the output voltage.
The rising UVLO threshold is internally set to 4.3V with
a 175mV hysteresis. Hysteresis at UVLO eliminates
“chattering” during startup. When VL drops below
UVLO, the internal switches are turned off and RST is
forced low.
Digital soft-start/soft-stop is provided internally to
reduce input surge currents and glitches at the input
during turn-on/turn-off. When UVLO is cleared and EN_
is high, digital soft-start slowly ramps up the internal
reference voltage in 64 steps. The total soft-start period
is 2048 switching cycles of the internal oscillator.
To calculate the soft-start period, use the following
equation:
t SS =
2048
fOSC
where fOSC is the internal oscillator frequency in hertz,
which is twice the switching frequency of each converter.
Enable
The MAX5072 dual converter provides separate enable
inputs EN1 and EN2 to individually control or sequence
the output voltages. These active-high enable inputs are
TTL compatible. Pulling EN_ high ramps up the reference
slowly, which provides soft-start at the outputs. Forcing
the EN_ low externally disables the individual output and
generates a RST signal. Use EN1, EN2, and PGOOD1 for
sequencing (see Figure 4). Connect PGOOD1 to EN2 to
make sure converter 1’s output is within regulation before
converter 2 starts. Add an RC network from VL to EN1
and EN2 to delay the individual converter. A larger RC
time constant means a more delayed output. Sequencing
reduces input inrush current and possible chattering.
Connect the EN_ to VL for always-on operation.
MR
Microprocessor-based products require manual reset
capability, allowing the operator or external logic circuitry
to initiate a reset. A logic low on MR asserts reset. Reset
remains asserted while MR is low, and for the Reset
Active Timeout Period (tRP) after MR returns high. MR
has an internal 44kΩ pullup resistor to VL, so it can be
left unconnected if not used. MR can be driven to TTL
logic levels.
Connect a normally open momentary switch from MR to
SGND to create a manual reset function. Note that
external debounce circuitry is not required. If MR is driven from long cables or if the device is used in a noisy
environment, connect a 0.1µF capacitor from MR to
SGND to provide additional noise immunity.
RST Output
RST is an open-drain output. RST pulls low when either
output falls below 92.5% of its nominal regulation voltage. Once both outputs exceed 92.5% of their nominal
regulated voltages and both soft-start cycles are completed, RST enters a high-impedance state after the
180ms active timeout period. To obtain a logic-voltage
output, connect a pullup resistor from RST to a logic
supply voltage. The internal open-drain MOSFET can
sink 3mA while providing a TTL logic-low signal. If
unused, ground RST or leave it unconnected.
PGOOD1
In addition to RST, converter 1 also includes a powergood flag. Pull PGOOD1 to a logic voltage to provide
logic-level output. PGOOD1 is an open-drain output and
can sink 3mA while providing the TTL logic-low
signal. PGOOD1 goes low when converter 1’s output
drops to 92.5% of its nominal regulated voltage. Connect
PGOOD1 to SGND or leave unconnected, if not used.
______________________________________________________________________________________
15
MAX5072
Input Voltage (V+)/Internal Linear
Regulator (VL)
MAX5072
2.2MHz, Dual-Output Buck or Boost
Converter with POR and Power-Fail Output
VIN
VIN
VL
OUTPUT2
VL
VL
DRAIN2
V+
DRAIN1
SOURCE2
SOURCE1
OUTPUT1
OUTPUT2
VL
DRAIN2
V+
DRAIN1
SOURCE2
SOURCE1
MAX5072
FB2
OUTPUT1
MAX5072
FB1
FB2
FB1
EN2
EN1
R2
EN2
VL
VL
EN1
R1
VL
C2
PGOOD1
SEQUENCING—OUTPUT 2 DELAYED WITH RESPECT TO OUTPUT 1.
VL
C1
R1/C1 AND R2/C2 ARE SIZED FOR REQUIRED SEQUENCING.
Figure 4. Power-Supply Sequencing Configurations
Dying Gasp Comparator (PFI/PFO)
The MAX5072 contains an uncommitted comparator
with an open-drain output. The inverting input of the
comparator is connected to an internal precision 0.78V
reference. Connect the noninverting input (PFI) to VIN
through a resistor-divider to program the input trip
threshold (VTRIP). The power-fail output (PFO) is pulled
low when PFI drops below 0.78V. PFI provides 20mV
hysteresis to avoid glitches during transition. The PFO
signal provides an advance signal to the processor
before the converter 1/converter 2 loses regulation. The
input trip threshold (VTRIP) can be adjusted to provide
advance signaling before the outputs drop to 92.5% of
the regulation voltage.
The input capacitors hold charge and provide energy
to the converter after VIN is disconnected. The hold-up
time (tHOLD) is defined as the time when the input voltage drops below VTRIP and the output falls out of regulation at the low end of the input voltage range VIN(MIN)
(Figure 5). Use the following equations to calculate the
resistor-divider and the C IN required for the proper
hold-up time.
CIN =
⎛P
⎞
P
2⎜ OUT1 + OUT2 ⎟
η2 ⎠
⎝ η1
2
⎛ V2
⎞
⎝ TRIP − V IN(MIN) ⎠
VL
OUTPUT2
CIN
VL
DRAIN2
V+
DRAIN1
SOURCE2
SOURCE1
OUTPUT1
R1
MAX5072
PFI
VL
R2
PFO
PFO
Figure 5. Dying Gasp Feature Monitors Input Supply
⎛V
⎞
R1 = R2 ⎜ TRIP − 1⎟
⎝ 0.78
⎠
R2 can be any value from 10kΩ to 100kΩ (Figure 5).
Current Limit
× t HOLD
where η1 and η2 are efficiencies of the converter 1 and
converter 2, respectively.
16
VIN
The internal switch current of each converter is sensed
using an internal current mirror. Converter 1 and converter 2 have 2A and 1A internal switches. When the
peak switch current crosses the current-limit threshold
of 3A (typ) and 1.8A (typ) for converter 1 and converter
2, respectively, the on cycle is terminated immediately
and the inductor is allowed to discharge. The next
cycle resumes at the next clock pulse.
______________________________________________________________________________________
2.2MHz, Dual-Output Buck or Boost
Converter with POR and Power-Fail Output
LX_
MAX5072
In deep overload or short-circuit conditions when the
FB voltage drops below 0.4V, the switching frequency
is reduced to 1/4 x fSW to provide sufficient time for the
inductor to discharge. During overload conditions, if the
voltage across the inductor is not high enough to allow
for the inductor current to properly discharge, current
runaway may occur. Current runaway can destroy the
device in spite of internal thermal-overload protection.
Reducing the switching frequency during overload conditions prevents current runaway.
BYPASS
RA
RC
FB_
FB_
RB
MAX5072
RA
MAX5072
LX_
VOUT_ > 0.8V
VOUT_ < 0.8V
Thermal-Overload Protection
During continuous short circuit or overload at the output, the power dissipation in the IC can exceed its limit.
Internal thermal shutdown is provided to avoid irreversible damage to the device. When the die temperature or junction temperature exceeds +150°C, an
on-chip thermal sensor shuts down the device, forcing
the internal switches to turn off, allowing the IC to cool.
The thermal sensor turns the part on again after the
junction temperature cools by +30°C. During thermal
shutdown, both regulators shut down, RST goes low,
and soft-start resets.
Applications Information
Setting the Switching Frequency
The controller generates the clock signal by dividing
down the internal oscillator or the SYNC input signal
when driven by an external oscillator. The switching
frequency equals half the oscillator frequency (fSW =
fOSC / 2). The internal oscillator frequency is set by a
resistor (ROSC) connected from OSC to SGND. The
relationship between fSW and ROSC is:
12.5 × 109
ROSC =
fSW
where fSW and fOSC are in hertz, and ROSC is in ohms.
For example, a 1250kHz switching frequency is set with
ROSC = 10kΩ. Higher frequencies allow designs with
lower inductor values and less output capacitance.
Consequently, peak currents and I2R losses are lower
at higher switching frequencies, but core losses, gatecharge currents, and switching losses increase.
A rising clock edge on SYNC is interpreted as a synchronization input. If the SYNC signal is lost, the internal oscillator takes control of the switching rate,
returning the switching frequency to that set by ROSC.
This maintains output regulation even with intermittent
SYNC signals. When an external synchronization signal
is used, ROSC should be set for the oscillator frequency
to be lower than or equal to the SYNC rate (fSYNC).
Figure 6. Adjustable Output Voltage
Buck Converter
Effective Input Voltage Range
Although the MAX5072 converters can operate from
input supplies ranging from 4.5V to 23V, the input voltage range can be effectively limited by the MAX5072
duty-cycle limitations for a given output voltage. The
maximum input voltage is limited by the minimum ontime (tON(MIN)):
VIN(MAX) ≤
VOUT
t ON(MIN) × fSW
where tON(MIN) is 100ns. The minimum input voltage is
limited by the maximum duty cycle (DMAX = 0.88):
+ VDROP1 ⎤
⎡V
VIN(MIN) = ⎢ OUT
⎥ + VDROP2 − VDROP1
0
.88
⎣
⎦
where VDROP1 is the total parasitic voltage drops in the
inductor discharge path, which includes the forward
voltage drop (VD) of the rectifier, the series resistance of
the inductor, and the PC board resistance. VDROP2 is
the total resistance in the charging path, which includes
the on-resistance of the high-side switch, the series
resistance of the inductor, and the PC board resistance.
Setting the Output Voltage
For 0.8V or greater output voltages, connect a voltagedivider from OUT_ to FB_ to SGND (Figure 6). Select
RB (FB_ to SGND resistor) to between 1kΩ and 10kΩ.
Calculate RA (OUT_ to FB_ resistor) with the following
equation:
⎡⎛ V
⎞ ⎤
RA = RB ⎢⎜ OUT ⎟ − 1⎥
⎢⎣⎝ VFB ⎠ ⎥⎦
where VFB_ = 0.8V (see the Electrical Characteristics table)
and VOUT_ can range from VFB_ to 28V (boost operation).
______________________________________________________________________________________
17
MAX5072
2.2MHz, Dual-Output Buck or Boost
Converter with POR and Power-Fail Output
For output voltages below 0.8V, set the MAX5072 output voltage by connecting a voltage-divider from the
output to FB_ to BYPASS (Figure 6). Select RC (FB to
BYPASS resistor) higher than a 50kΩ range. Calculate
RA with the following equation:
⎡ V − VOUT ⎤
RA = RC ⎢ FB
⎥
⎣ VBYPASS − VFB ⎦
where VFB = 0.8V, VBYPASS = 2V (see the Electrical
Characteristics table), and VOUT_ can range from 0V to
VFB_.
Inductor Selection
Three key inductor parameters must be specified for
operation with the MAX5072: inductance value (L), peak
inductor current (IL), and inductor saturation current
(ISAT). The minimum required inductance is a function of
operating frequency, input-to-output voltage differential
and the peak-to-peak inductor current (∆IL). Higher ∆IL
allows for a lower inductor value while a lower ∆I L
requires a higher inductor value. A lower inductor value
minimizes size and cost, improves large-signal transient
response, but reduces efficiency due to higher peak currents and higher peak-to-peak output ripple voltage for
the same output capacitor. On the other hand, higher
inductance increases efficiency by reducing the ripple
current. However, resistive losses due to extra wire turns
can exceed the benefit gained from lower ripple current
levels, especially when the inductance is increased without also allowing for larger inductor dimensions. A good
compromise is to choose ∆IL equal to 30% of the full
load current. To calculate the inductance use the following equation:
L=
VOUT (VIN − VOUT )
VIN × fSW × ∆IL
where VIN and VOUT are typical values (so that efficiency
is optimum for typical conditions). The switching frequency is set by R OSC (see the Setting the Switching
Frequency section). The peak-to-peak inductor current,
which reflects the peak-to-peak output ripple, is worst at
the maximum input voltage. See the Output Capacitor
Selection section to verify that the worst-case output ripple is acceptable. The inductor saturating current is also
important to avoid runaway current during the output
overload and continuous short circuit. Select the ISAT to
be higher than the maximum peak current limits of 4.5A
and 2.2A for converter 1 and converter 2.
18
Input Capacitors
The discontinuous input current waveform of the buck
converter causes large ripple currents at the input. The
switching frequency, peak inductor current, and the
allowable peak-to-peak voltage ripple dictate the input
capacitance requirement. Increasing the switching frequency or the inductor value lowers the peak to average current ratio, yielding a lower input capacitance
requirement. Note that two converters of MAX5072 run
180° out-of-phase, thereby effectively doubling the
switching frequency at the input.
The input ripple waveform would be unsymmetrical due
to the difference in load current and duty cycle between
converter 1 and converter 2. The input ripple is comprised of ∆VQ (caused by the capacitor discharge) and
∆VESR (caused by the ESR of the capacitor). A higher
load converter dictates the ESR requirement, while the
capacitance requirement is a function of the loading
mismatch between the two converters. The worst-case
mismatch is when one converter is at full load while the
other is at no load or in shutdown. Use low-ESR ceramic
capacitors with high ripple-current capability at the
input. Assume the contribution from the ESR and capacitor discharge equal to 50%. Calculate the input capacitance and ESR required for a specified ripple using the
following equations:
∆VESR
ESRIN =
∆IL ⎞
⎛
⎜IOUT +
⎟
⎝
2 ⎠
where
∆IL =
(VIN − VOUT )
× VOUT
VIN × fSW × L
and
CIN =
IOUT × D(1 − D)
∆VQ × fSW
where
V
D = OUT
VIN
where IOUT is the maximum output current from either
converter 1 or converter 2, and D is the duty cycle for
that converter. fSW is the frequency of each individual
converter. For example, at VIN = 12V, VOUT = 3.3V at
I OUT = 2A, and with L = 3.3µH, the ESR and input
capacitance are calculated for a peak-to-peak input
______________________________________________________________________________________
2.2MHz, Dual-Output Buck or Boost
Converter with POR and Power-Fail Output
Output Capacitor Selection
The allowable output ripple voltage and the maximum
deviation of the output voltage during step load currents
determines the output capacitance and its ESR.
The output ripple is comprised of ∆VQ (caused by the
capacitor discharge) and ∆VESR (caused by the ESR of
the capacitor). Use low-ESR ceramic or aluminum electrolytic capacitors at the output. For aluminum electrolytic
capacitors, the entire output ripple is contributed by
∆VESR. Use the ESROUT equation to calculate the ESR
requirement and choose the capacitor accordingly. If
using ceramic capacitors, assume the contribution to
the output ripple voltage from the ESR and the capacitor
discharge are equal. Calculate the output capacitance
and ESR required for a specified ripple using the following equations:
ESROUT =
COUT =
∆VESR
∆IL
∆IL
8 × ∆VQ × fSW
tronics being powered. When using a ceramic capacitor, assume 80% and 20% contribution from the output
capacitance discharge and the ESR drop, respectively.
Use the following equations to calculate the required
ESR and capacitance value:
ESROUT =
I
× t RESPONSE
COUT = STEP
∆VQ
where I STEP is the load step and t RESPONSE is the
response time of the controller. Controller response
time depends on the control-loop bandwidth.
Boost Converter
The MAX5072 can be configured for step-up conversion
since the internal MOSFET can be used as a low-side
switch. Use the following equations to calculate the
inductor (LMIN), input capacitor (CIN), and output capacitor (COUT) when using the converter in boost operation.
Inductor
Choose the minimum inductor value so the converter
remains in continuous mode operation at minimum output current (IOMIN).
LMIN =
where
∆VO _ RIPPLE ≅ ∆VESR + ∆VQ
where ∆IL is the peak-to-peak inductor current as calculated above and fSW is the individual converter’s
switching frequency.
The allowable deviation of the output voltage during
fast transient loads also determines the output capacitance and its ESR. The output capacitor supplies the
step load current until the controller responds with a
greater duty cycle. The response time (tRESPONSE )
depends on the closed-loop bandwidth of the converter. The high switching frequency of MAX5072 allows for
higher closed-loop bandwidth, reducing tRESPONSE
and the output capacitance requirement. The resistive
drop across the output capacitor ESR and the capacitor discharge causes a voltage droop during a step
load. Use a combination of low-ESR tantalum and
ceramic capacitors for better transient load and
ripple/noise performance. Keep the maximum output
voltage deviation above the tolerable limits of the elec-
∆VESR
ISTEP
V2IN × D × η
2 × fSW × VO × IOMIN
where
V + VD − VIN
D= O
VO + VD − VDS
and IOMIN = 0.25 x IO
The VD is the forward voltage drop of the external Schottky
diode, D is the duty cycle, and VDS is the voltage drop
across the internal switch. Select the inductor with low DC
resistance and with a saturation current (ISAT) rating higher than the peak switch current limit of 4.5A and 2.2A of
converter 1 and converter 2, respectively.
Input Capacitor
The input current for the boost converter is continuous
and the RMS ripple current at the input is low. Calculate
the capacitor value and ESR of the input capacitor
using the following equations.
______________________________________________________________________________________
19
MAX5072
ripple of 100mV or less, yielding an ESR and capacitance value of 20mΩ and 6.8µF for 1.25MHz frequency.
Use a 100µF capacitor at low input voltages to avoid
possible undershoot below the undervoltage lockout
threshold during power-on and transient loading.
MAX5072
2.2MHz, Dual-Output Buck or Boost
Converter with POR and Power-Fail Output
CIN =
VOUT
∆IL × D
4 × fSW × ∆VQ
ESR =
R1
-
∆VESR
∆IL
COMP
gM
R2
VREF
+
RF
where
∆IL
(VIN − VDS )
=
CF
L × fSW
where VDS is the total voltage drop across the internal
MOSFET plus the voltage drop across the inductor
ESR. ∆IL is the peak-to-peak inductor ripple current as
calculated above. ∆VQ is the portion of input ripple due
to the capacitor discharge and ∆VESR is the contribution due to ESR of the capacitor.
Output Capacitor Selection
For the boost converter, the output capacitor supplies
the load current when the main switch is ON. The
required output capacitance is high, especially at higher duty cycles. Also, the output capacitor ESR needs to
be low enough to minimize the voltage drop due to the
ESR while supporting the load current. Use the following equation to calculate the output capacitor for a
specified output ripple tolerance.
∆VESR
ESR =
IO
I × DMAX
COUT = O
∆VQ × fSW
Figure 7. Type II Compensation Network.
VOUT
CCF
RI
Power Dissipation
The MAX5072 includes a high-frequency, low RDS_ON
switching MOSFET. At +85°C, the RDS_ON of the internal switch for converter 1 and converter 2 are 290mΩ
and 630mΩ, respectively. The DC loss is a function of
the RMS current in the switch while the switching loss is
a function of switching frequency and input voltage. Use
the following equations to calculate the RMS current,
DC loss, and switching loss of each converter. The
MAX5072 device is available in a thermally enhanced
package and can dissipate up to 2.7W at +70°C ambi-
CF
RF
R1
CI
gM
R2
VREF
COMP
+
Figure 8. Type III Compensation Network
ent temperature. The total power dissipation in the package must be limited so the junction temperature does not
exceed its absolute maximum rating of +150°C at maximum ambient temperature.
For the buck converter:
D
IRMS = (I2DC +I2PK +(IDC × IPK )) × MAX
3
IO is the load current, ∆VQ is the portion of the ripple
due to the capacitor discharge and ∆VESR is the contribution due to the ESR of the capacitor. DMAX is the
maximum duty cycle at minimum input voltage.
20
CCF
× D
PDC = I2RMS × RDS(ON)MAX
where
IDC = IO −
∆IL
2
IPK = IO +
∆IL
2
See the Electrical Characteristics table for the RDS(ON)MAX
value.
______________________________________________________________________________________
2.2MHz, Dual-Output Buck or Boost
Converter with POR and Power-Fail Output
4
For the boost converter:
D
IRMS = (I2DC +I2PK +(IDC × IPK )) × MAX
3
V ×I
IIN = O O
VIN × η
∆IL =
(VIN − VDS ) × D
L × fSW
IDC = IIN −
IPK = IIN +
∆IL
2
∆IL
2
PDC = I2RMS × RDS(ON)MAX
where VDS is the drop across the internal MOSFET. See
the Electrical Characteristics for the RDS(ON)MAX value.
V × I × (t R + t F ) × fSW
PSW = O IN
4
where tR and tF are rise and fall times of the internal
MOSFET. The tR and tF are typically 20ns, and can be
measured in the actual application.
The supply current in the MAX5072 is dependent on
the switching frequency. See the Typical Operating
Characteristics to find the supply current of the
MAX5072 at a given operating frequency. The power
dissipation (PS) in the device due to supply current (IS)
is calculated using following equation.
PS = VINMAX × ISUPPLY
The total power dissipation PT in the device is:
PT = PDC1 + PDC2 + PSW1 + PSW2 + PS
where PDC1 and PDC2 are DC losses in converter 1 and
converter 2, respectively. PSW1 and PSW2 are switching
losses in converter 1 and converter 2, respectively.
Calculate the temperature rise of the die using the following equation:
TJ = TC + (PT x θJ-C)
where θJ-C is the junction-to-case thermal impedance
of the package equal to +2°C/W. Solder the exposed
pad of the package to a large copper area to minimize
the case-to-ambient thermal impedance. Measure the
temperature of the copper area near the device at a
worst-case condition of power dissipation and use
+2°C/W as θJ-C thermal impedance. The case-to-ambient thermal impedance (θC-A) is dependent on how
well the heat is transferred from the PC board to the
ambient. Use large copper area to keep the PC board
temperature low. The θC-A is usually in the +20°C/W to
+40°C/W range.
Compensation
The MAX5072 provides an internal transconductance
amplifier with its inverting input and its output available
to the user for external frequency compensation. The
flexibility of external compensation for each converter
offers wide selection of output filtering components,
especially the output capacitor. For cost-sensitive
applications, use high-ESR aluminum electrolytic
capacitors; for component size-sensitive applications,
use low-ESR tantalum or ceramic capacitors at the output. The high switching frequency of MAX5072 allows
use of ceramic capacitors at the output.
Choose all the passive power components that meet
the output ripple, component size, and component cost
requirements. Choose the small-signal components for
the error amplifier to achieve the desired closed-loop
bandwidth and phase margin. Use a simple pole-zero
pair (Type II) compensation if the output capacitor ESR
zero frequency is below the unity-gain crossover frequency (fC). Type III compensation is necessary when
the ESR zero frequency is higher than fC or when compensating for a continuous mode boost converter that
has a right-half plane zero.
Use the following procedure 1 to calculate the compensation network components when fZERO,ESR < fC.
Buck Converter Compensation
Procedure 1 (see Figure 7):
Calculate the fZERO,ESR and LC double pole:
______________________________________________________________________________________
21
MAX5072
PSW =
VINMAX × IO × (t R + t F ) × fSW
MAX5072
2.2MHz, Dual-Output Buck or Boost
Converter with POR and Power-Fail Output
If the fZERO,ESR is lower than fC and close to fLC, use a
Type II compensation network where RFCF provides a
midband zero fmid,zero, and RFCCF provides a high-frequency pole.
Calculate modulator gain GM at the crossover frequency.
1
fZERO, ESR =
2π × ESR × COUT
1
fLC =
2π × LOUT × COUT
GM =
Calculate the unity-gain crossover frequency as:
VIN
ESR
0.8
×
×
VOSC
ESR + 2π × fC × LOUT
VOUT
where VOSC is a peak-to-peak ramp amplitude equal
to 1V.
f
fC = SW
20
PGOOD1
VL
CLOCK
OUT
VL
OUTPUT
3.3V/2A
32
31
30
29
28
27
26
25
SOURCE2 PGND SGND PGND SOURCE1 PGOOD1
FSEL1 24
1 CLKOUT
SGND BST1/VDD1 23
2 BST2/VDD2 EP
OUTPUT
2.5V/1A
ON
OFF
3 DRAIN2
DRAIN1 22
4 DRAIN2
DRAIN1 21
MAX5072
5 EN2
VL
6 FB2
EN1 20
ON
OFF
FB1 19
COMP1 18
7 COMP2
VOUT1
VL
PFO
DYING GASP
8 PFO
SYNC PFI
9
10
OSC
11
V+
12
VL
13
RST 17
VL BYPASS MR
14 15 16
SGND
µP RESET INPUT
SYSTEM
CLOCK
MANUAL
RESET
VIN = 5.5V TO 23V
PGND
SGND*
*CONNECT PGND AND SGND TOGETHER AT ONE POINT NEAR THE
RETURN TERMINALS OF THE V+ AND VL BYPASS CAPACITORS.
Figure 9. Buck-Boost Application
22
______________________________________________________________________________________
2.2MHz, Dual-Output Buck or Boost
Converter with POR and Power-Fail Output
Calculate CI for a target unity crossover frequency, fC:
GE / A = gm × RF
CI =
The total loop gain at fC should be equal to 1
GM × GE / A = 1
Place a pole
2π × fC × LOUT × COUT × VOSC
VIN × RF
1
2π × RI × CI at fZERO,ESR.
(fP1 =
1
RI =
or
VOSC (ESR + 2π × fC × L OUT ) VOUT
RF =
0.8 × VIN × gm × ESR
Place a zero at or below the LC double pole:
CF =
2π × fZERO, ESR × CI
Place a second zero, fZ2, at 0.2fC or at fLC, whichever
is lower.
1
2π × RF × fLC
R1 =
1
− RI
2π × fZ2 × CI
Place a high-frequency pole at fP = 0.5 x fSW.
Procedure 2 (See Figure 8):
If the output capacitor used is a low-ESR ceramic type,
the ESR frequency is usually far away from the targeted
unity crossover frequency (fC). In this case, Type III compensation is recommended. Type III compensation provides two-pole zero pairs. The locations of the zero and
poles should be such that the phase margin peaks at fC.
fC
f
= P =5
fC
The fZ
is a good number to get about 60°
phase margin at fC. However, it is important to place
the two zeros at or below the double pole to avoid the
conditional stability issue.
Select a crossover frequency:
f
fC ≤ SW
20
Place a second pole
switching frequency.
CCF =
1
1
CF =
2π × 0.75 × fLC × RF
and RF ≥ 10kΩ.
at 1/2 the
1− D
2π × LOUTCOUT
where:
D =1−
where:
)
(1 − D)2 R(MIN)
fZERO, RHP =
2π × LOUT
2π × LOUT × COUT
1
at 0.75 × fLC
2π × R F × C F
2π × RF × CCF
CF
(2π × 0.5 × fSW × RF × CF ) − 1
fLC =
Place a zero
fZ =
1
Boost Converter Compensation
The boost converter compensation gets complicated
due to the presence of a right-half-plane zero
FZERO,RHP. The right-half-plane zero causes a drop inphase while adding positive (+1) slope to the gain curve.
It is important to drop the gain significantly below unity
before the RHP frequency. Use the following procedure
to calculate the compensation components.
Calculate the LC double-pole frequency, fLC, and the
right half plane zero frequency.
Calculate the LC double-pole frequency, fLC:
fLC =
(fP2 =
VIN
VOUT
VOUT
R(MIN) =
IOUT(MAX)
Target the unity-gain crossover frequency for:
______________________________________________________________________________________
23
MAX5072
The transconductance error-amplifier gain is:
MAX5072
2.2MHz, Dual-Output Buck or Boost
Converter with POR and Power-Fail Output
fC ≤
Place a zero
(fZ1 =
CF =
Improving Noise Immunity
fZERO, RHP
5
1
2π × R F × C F
)
at 0.75 x fLC.
1
2π × 0.75 × fLC × RF
PC Board Layout Guidelines
where RF ≥ 10kΩ.
Calculate CI for a target crossover frequency, fC:
⎡
⎤
2
VOSC ⎢(1 − D)2 + ω C × LO × CO ⎥
⎢⎣
⎥⎦
CI =
ω C × RF × VIN
where ωC = 2πfC.
Place a pole
(fP1 =
RI =
1
)
2π × RI × CI at fZERO,RHP.
1
2π × fZERO,RHP × CI
(fZ2 =
Place the second zero
R1 =
1
2π × fLC × CI
Place the second pole
the switching frequency.
CCF =
1
)
2π × R1 × CI
(fP2 =
In applications where the MAX5072 are subject to noisy
environments, adjust the controller’s compensation to
improve the system’s noise immunity. In particular,
high-frequency noise coupled into the feedback loop
causes jittery duty cycles. One solution is to lower the
crossover frequency (see the Compensation section).
at fLC.
− RI
1
)
2π × RF × CCF at 1/2
CF
(2π × 0.5 fSW × RF × CF ) − 1
Careful PC board layout is critical to achieve low
switching losses and clean, stable operation. This is
especially true for dual converters where one channel
can affect the other. Refer to the MAX5072 EV kit data
sheet for a specific layout example. Use a multilayer
board whenever possible for better noise immunity.
Follow these guidelines for good PC board layout:
1) For SGND, use a large copper plane under the IC
and solder it to the exposed paddle. To effectively
use this copper area as a heat exchanger between
the PC board and ambient, expose this copper area
on the top and bottom side of the PC board. Do not
make a direct connection from the exposed pad
copper plane to SGND (pin 29) underneath the IC.
2) Isolate the power components and high-current
path from the sensitive analog circuitry. Use a separate PGND plane under the OUT1 and OUT2 sides
(referred to as PGND1 and PGND2). Connect the
PGND1 and PGND2 planes together at one point
near the IC.
3) Keep the high-current paths short, especially at the
ground terminals. This practice is essential for stable, jitter-free operation.
4) Connect SGND and PGND together close to the IC
at the ground terminals of VL and V+ bypass capacitors. Do not connect them together anywhere else.
5) Keep the power traces and load connections short.
This practice is essential for high efficiency. Use
thick copper PC boards (2oz vs. 1oz) to enhance
full-load efficiency.
6) Ensure that the feedback connection to COUT is
short and direct.
7) Route high-speed switching nodes (BST_/VDD_,
SOURCE_) away from the sensitive analog areas
(BYPASS, COMP_, and FB_). Use the internal PC
board layer for SGND as EMI shields to keep radiated noise away from the IC, feedback dividers, and
analog bypass capacitors.
24
______________________________________________________________________________________
2.2MHz, Dual-Output Buck or Boost
Converter with POR and Power-Fail Output
2) Group the gate-drive components (bootstrap
diodes and capacitors, and VL bypass capacitor)
together near the controller IC.
b) Connect this plane to SGND and use this plane
for the ground connection for the reference
(BYPASS), enable, compensation components,
feedback dividers, and OSC resistor.
c) Connect SGND and PGND together near the
input bypass capacitors and the IC (this is the
only connection between SGND and PGND).
3) Make the DC-DC controller ground connections as
follows:
a) Create a small-signal ground plane underneath
the IC.
Ordering Information (continued)
PKG
CODE
PART
TEMP RANGE
PIN-PACKAGE
MAX5072ETJ+
-40°C to +85°C
32 Thin QFN-EP*
T3255-4
(5mm x 5mm)
MAX5072ATJ
-40°C to +125°C
32 Thin QFN-EP*
T3255-4
(5mm x 5mm)
MAX5072ATJ+ -40°C to +125°C
32 Thin QFN-EP*
T3255-4
(5mm x 5mm)
Chip Information
TRANSISTOR COUNT: 5994
PROCESS: BiCMOS
*EP = Exposed pad.
+Denotes lead-free package.
______________________________________________________________________________________
25
MAX5072
Layout Procedure
1) Place the power components first, with ground terminals adjacent (inductor, CIN_, and COUT_). Make
all these connections on the top layer with wide,
copper-filled areas (2oz copper recommended).
Package Information
(The package drawing(s) in this data sheet may not reflect the most current specifications. For the latest package outline information
go to www.maxim-ic.com/packages.)
QFN THIN.EPS
MAX5072
2.2MHz, Dual-Output Buck or Boost
Converter with POR and Power-Fail Output
26
______________________________________________________________________________________
2.2MHz, Dual-Output Buck or Boost
Converter with POR and Power-Fail Output
Maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim product. No circuit patent licenses are
implied. Maxim reserves the right to change the circuitry and specifications without notice at any time.
Maxim Integrated Products, 120 San Gabriel Drive, Sunnyvale, CA 94086 408-737-7600 ____________________ 27
© 2006 Maxim Integrated Products
is a registered trademark of Maxim Integrated Products, Inc.
MAX5072
Package Information (continued)
(The package drawing(s) in this data sheet may not reflect the most current specifications. For the latest package outline information
go to www.maxim-ic.com/packages.)
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