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Embedded Processing & DSP
Resource Guide
2013 Edition
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Welcome to the 2013 Embedded Processing
& DSP Resource Guide
Texas Instruments is pleased to be the official sponsor of the Embedded Processing & DSP Resource
Guide. This guide provides engineers, designers and embedded developers with a purchasing guide on
TI processor-based development tools, embedded software, engineering services and end-equipment
solutions provided by our worldwide TI Design Network members.
Embedded Processing & DSP
Resource Guide 2013 Edition
www.eecatalog.com/dsp
VP/Associate Publisher
Clair Bright
[email protected]
(415) 255-0390 ext. 15
Editorial
Editorial Director
TI Design Network members offer various levels of system integration, optimization and system expertise on products to enable you to meet project demands, reduce costs and get to market quickly. Please
contact the companies listed in the guide for more information on TI platforms including, C2000™ realtime control microcontrollers, MSP430™ ultra-low-power microcontrollers, Stellaris® 32-bit ARM®
Cortex™-M microcontrollers and Hercules™ safety microcontrollers, Sitara™ ARM® Cortex™-A processors, TMS320C6000™ high-performance, single core and multicore processors, TMS320C5000™
ultra-low power DSPs and DaVinci™ video processors. For the latest products and information, visit the
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2
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The Embedded Processing & DSP Resource Guide 2013 Edition is published by
Extension Media LLC. Extension Media makes no warranty for the use of its products
and assumes no responsibility for any errors which may appear in this Catalog nor
does it make a commitment to update the information contained
herein. Embedded
Processing & DSP Resource Guide 2013 Edition is Copyright ®2012 Extension Media
LLC. No information in this Catalog may be reproduced without expressed written
permission from Extension Media @ 1786 18th Street, San Francisco, CA 941072343.All registered trademarks and trademarks included in this Catalog are held by
their respective companies. Every attempt was made to include all trademarks and
registered trademarks where indicated by their companies.
All registered trademarks and trademarks included in this Catalog are held by their
respective companies. Every attempt was made to include all trademarks and
registered trademarks where indicated by their companies.
C2000, DaVinci, OMAP, TMS320C2000, TMS320C24x, TMS320C28x, C24x,
C28x, C5000, TMS320C5000, TMS320C54x, TMS320C55x, C54x, C55x, C6000,
TMS320C6000, TMS320C62x, TMS320C64x, TMS320C64x+, TMS320C67x,
C62x, C64x, C64x+, C67x, TMS320DM64x, DM64x, TMS320C5x, Code Composer
Studio, DSP/BIOS, eXpressDSP, MicroStar BGA, NanoFree, NanoStar, ProbePoint,
RTDX, TMS320, XDAIS, XDS510 and XDS560 are trademarks of Texas Instruments. All
other trademarks are property of their respective owners.
Embedded Processing & DSP Resource Guide 2013
Contents
Extending System Trace to Blackhawk USB560m Emulators on Multicore TI C66xx KeyStone™ SoCs
By Andrew Ferrari, Blackhawk..................................................................................................................................................8
Small Cells Connecting a Big World Require Huge Integration
By Chris Ciufo, Senior Editor................................................................................................................................................... 12
Analysis of LTE Base Station Software Deployment on Multicore SoCs
By Sneha Namakaje and Zhihong Lin, Texas Instruments...................................................................................................... 18
Top 3 Mistakes with Static Analysis for Embedded and Safety-Critical Development
By Arthur Hicken, Evangelist, Parasoft....................................................................................................................................23
Embedded Processing Overview
Embedded Processors
Texas Instruments
Embedded Processing Overview............................................................................................................................................25
TMS320C6000 and TMS302C5000 DSPs, Fixed- and Floating-Point...................................................................................26
C2000™ Microcontrollers, Fixed-Point and Floating-Point....................................................................................................27
MSP430™ Microcontrollers...................................................................................................................................................28
Sitara™ ARM® Cortex™-A8 and ARM9™ Processors...........................................................................................................30
Stellaris® 32-Bit ARM® Cortex™-M MCUs............................................................................................................................31
TMS320C66x Multicore DSP, Fixed- and Floating-Point........................................................................................................32
Hercules™ Safety Microcontrollers........................................................................................................................................33
DaVinci™ Video Processors: Optimized for Digital Video......................................................................................................34
Products and Services
Development Tools
Daughter Cards
Kentec Display
LM4F232/LM4F120 LCD Interface Expansion Board
(Stellaris Boosterpack)........................................................... 35
Link Research
Multi-channel Data Acquisition daughtercard for the
F2812/F28335 eZdsp™ Development Kit............................... 36
Development Boards
4
Avnet TI OMAP™ Processor / Spartan-6 FPGA
Co-Processing Kit................................................................... 37
Development Boards/EVMs
D.SignT GmbH & Co. KG
D.Module2 High-Performance DSP Processor and I/O
Boards.................................................................................... 38
Traquair Data Systems, Inc.
micro-line TMS320C641x-based Integer DSP/FPGA Boards...... 39
micro-line TMS320C6713 DSP-based Floating-Point
DSP/FPGA Boards.................................................................. 40
Xilinx
Xilinx
Avnet Spartan-6 FPGA DSP Kit.............................................. 37
Avnet Kintex-7 FPGA DSP Kit with High-Speed Analog........ 41
Embedded Processing & DSP Resource Guide 2013
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mouser.com/ti
;OL5L^LZ[7YVK\J[[email protected]\Y5L^LZ[+LZPNUZŽ
4V\ZLYHUK4V\ZLY,SLJ[YVUPJZHYLYLNPZ[LYLK[YHKLTHYRZVM4V\ZLY,SLJ[YVUPJZ0UJ6[OLYWYVK\J[ZSVNVZHUKJVTWHU`UHTLZTLU[PVULKOLYLPUTH`IL[YHKLTHYRZVM[OLPYYLZWLJ[P]LV^ULYZ
Development Tools
Signum Systems
D.SignT GmbH & Co. KG
Signum Systems Emulators for TI DSPs, OMAP™ and
DaVinci™ Processors............................................................. 42
D.SignT TCP/IP Stack for TI C2000™ MCUs, C5000™, and
C6000™ DSPs......................................................................... 56
Sundance Digital Signal Processing Inc
Hand-coded, Optimized DSP/Vector, LINPACK, EISPACK,
and CBLAS Libraries............................................................... 43
Emulators/Analyzers
Framework Software
Adaptive Digital Technologies
G.PAK bridges the gap between inflexible fixed-function
chips and custom programmed solutions.............................. 57
Blackhawk
HCC Embedded
Advanced JTAG XDS510 Emulators....................................... 44
Blackhawk Emulator Product Matrix...................................... 45
High Performance JTAG Emulators........................................ 46
USB100v2 JTAG Controllers.................................................. 47
XDS560v2 System Trace (STM)............................................. 48
Advanced Embedded Middleware......................................... 58
Kane Computing Ltd
Kane Computing Company Profile.......................................... 49
Signum Systems
JTAGjet In-Circuit Debuggers for DSP, OMAP™ and
DaVinci™ Processors............................................................. 50
Embedded Software
Algorithms/Codecs
Adaptive Digital Technologies
Adaptive Digital Echo Cancellation Library: Acoustic,
Packet, Network, & Line........................................................ 51
Voice Algorithms and Solutions on the Texas Instruments
TMS320™ Family of DSPs, OMAP™, DM-Series,
Multi-Core, and ARM® processors....................................... 52
DSP Innovations Inc.
New TWELP Vocoder (600…9600 bps)................................. 53
Application-Specific Libraries
Adaptive Digital Technologies
IP phone/intercom/ATA for OMAP3530, OMAP3730,
DM814X, DM816X, and Stellaris® devices.......................... 54
DelCom Systems, Inc.
GSM/EGPRS/EDGE LayerONE Physical Layer Software....... 55
6
Drivers/IO/Control Software
End-Equipment Solutions
End-Equipment Solutions
Anaren
Anaren Integratec Radio 110L Series.................................... 59
Critical Link
MityARM System on Modules based on TI AM335x
processors.............................................................................. 60
MityDSP™ and MityARM System on Modules
with FPGA............................................................................... 60
Z3 Technology, LLC
Compact Low-Power Software- Enabled HD Multimedia
Module................................................................................... 61
Engineering Services
Digital Hardware / Board Design
Advantech Co., Ltd.
DSPC-8681 Half-length PCI Express Multimedia
Processing Card ..................................................................... 62
Full Turnkey Designs
Benchmark Electronics
World Wide Electronics Design and Manufacturing
Services.................................................................................. 63
Micross Components
DSP & Microcontroller Die and Alternative Packaging......... 64
Embedded Processing & DSP Resource Guide 2013
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Advertorial
Extending System Trace to
Blackhawk USB560m Emulators on
TI’s C66x KeyStone Multicore SoCs
By Andrew Ferrari, Blackhawk
System Trace
The System Trace (STM) capability offered by Texas Instruments employs the MIPI System Trace Protocol, which
provides developers with a “printf ” capability. In a multicore
environment, information from each core can by analyzed
because they are globally time stamped. This is a powerful
tool for looking at what
each core is processing in a
common timeline. TI offers
STM for CTools-enabled
devices.
Figure 1 - New CCS Project Dialog
This article provides a
brief overview of how
to configure a Blackhawk USB560m JTAG
emulator to collect STM
data via embedded trace
buffer (ETB) on TI C66xx
KeyStone™
multicore
architecture.
Figure 2 - New Target Configuration Dialog
For additional TI STM
information or to download the complete demo
project code and examples
mentioned in this article,
please visit: www.blackhawk-dsp.com/STM.
CCS Project Creation (Code Composer
Studio™ IDE)
To demonstrate how easy it is to add STM data collection to
an application, a simple, “hello world”-type project for the
C6678 will be used.
To recreate the demo project for this or a different STM supported target:
1. Start Code Composer Studio IDE v5.x
2. Select the main menu option File → New → CCS Project. This will
display the New CCS Project wizard dialog (Figure 1) where you
can enter a project name, select the Family (demo uses “C6000”)
and its variant (demo uses “Generic C66xx Device”).
8
3. Leave the default advanced settings and choose “Empty
Project” from the Project Templates and Examples.
4. Click finished when done. This will create a main.c file with
a single function, main() and add it to the eclipse Project
Explorer window.
5. Now locate a C66xx linker command file, copy it to the
project workspace and specify the file in the project properties (demo uses a file downloaded in one of the TI C667x
CTools Examples). The project will now build successfully.
Adding STMLib to the Project
After the project is configured in CCS:
1. Download and install the STMLib files.
2. Include the STM header file and add and the path of the STM
library file to the linker in project.
3. Add the STM API calls to the code. The project’s main.c file
will look something like the following code snippet.
#include “StmLibrary.h”
#include <stdio.h>
#include <stdlib.h>
void main(void) {
int jj=0;
pSTMhdl=STMXport_open(pSTMBufInfo, &STMConfigInfo);
STMXport_printf(pSTMhdl, STM_HelperCh, “%s”, “C667x
Demo1 - BEG LOOP” );
for (ii=0; ii<880000; ii++) {
if ((ii%250) == 0) {
STMXport_putShort(pSTMhdl, STM_HelperCh, (short)jj );
jj++;
}
}
STMXport_printf(pSTMhdl, STM_HelperCh, “%s”, “C667x
Demo1 - END LOOP” );
STMXport_flush(pSTMhdl);
STMXport_close(pSTMhdl);
exit (0)
}
Embedded Processing & DSP Resource Guide 2013
Advertorial
lected STM data will be
displayed (Figure 5).
2.
Load the demo
program to C66xx_0 and
run (Resume | F8) the
program. Because the
option to synchronize
with target execution
Figure 6 - Trace Receiver Selection was selected in the trace
Dialog
controls, the trace display
will update automatically
with the STM data collected in the ETB when the program
terminates or is halted.
The “Data Message” column of the trace display (Figure 5) shows
the output from the function STMXport_printf() and the “Data”
column is from the function STMXport_putShort ().
Figure 3 - Debug Window
Configuring CCS
To create a target configuration and setup trace:
1. Select the main menu
option, File → New → Target
Configuration
File,
and
choose the emulator connection and device (see Figure 2).
2. Launch the debug session.
That is all that is required to begin collecting STM debug
information from your application using a Blackhawk
USB560m JTAG emulator (or any Blackhawk XDS560-class
emulator).
Multicore STM Data Collection
To collect STM from more than one core, simply connect to
another CPU core (i.e. C66xx_1) prior to setting up the trace
controls. It is also helpful to group the CPUs in the debug
window to synchronize program load and target execution.
3. Connect to the necessary devices to enable STM
collection using the ETB
(see Figure 3). These devices should be labeled similar
to C66xx_0 (first CPU core), CSSTM_0 (STM node), and
TETB_STM (ETB node).
You may need to select
the option to “Show all
cores”.
In the trace display, the “Master Name” column will differentiate the data for each CPU and the time stamp will order
each debug message in the proper sequence.
4.
Configure
settings in the trace system
control dialog from the
main menu Tools → Trace
Control (see Figure 4).
The setup requires that you change the target connection to
the “Blackhawk XDS560v2 STM Emulator”, selecting “560v2
System Trace” as the trace receiver and only connecting to
the CSSTM_0 and C66xx_0 devices (do not connect to the
TETB_STM node).
5. Select the CSSTM_0 tab. If the ETB settings are not displayed, select the “Receiver…” button and choose ETB from
the list (Figure 6). Make sure the ETB type is “Auto” and
“Synchronize trace with target execution” is selected.
For more information, visit: www.blackhawk-dsp.com/STM.
Figure 4 - Trace System Control
Figure 5 - Trace Display Window with
STM Data
6. Press the “OK” button to apply these settings.
Collecting STM Data
1. Open the trace display window for the CSSTM_0 node from
the main menu (Tools → Trace → Analyzer → Open Trace
Connection in New View → CSSTM_0). This is where the col-
www.eecatalog.com/dsp
XDS560v2 STM Data Collection
This article describes how to extend Blackhawk XDS560class emulators to collect STM data using the ETB. If you
own a Blackhawk XDS560v2 STM model, you can collect
STM data directly, without using the ETB.
CONTACT INFORMATION
Blackhawk
123 Gaither Drive
Mt. Laurel, NJ 08054
USA
856-234-2629 Telephone
856-866-1100 Fax
[email protected]
http://www.blackhawk-dsp.com
9
Spectrum Digital, Inc.
12502 Exchange Drive, Suite 440
Stafford, TX. 77477 USA
Tel: 281.494.4500 x-113
Fax: 281.494.5310
Spectrum Digital Emulators for TI Processors
XDS510PP
MPSD
SPI530
MPSD
XDS100v2
USB
XDS100v3
USB CJTAG
C2000
XDS510LC USB
XDS510PP
PLUS
XDS510
USB
XDS510 USB
Galvanic
XDS510
USB PLUS
XDS560v2 LC
Traveler
XDS560v2 STM
Traveler
XDS560v2 STM
Part Number
701041
701121
702302
702305
701902
701014
701900
701910
701905
702597
702598
702592
Price in USD
$ 1299
Parallel
Port
PS
$ 2499
Parallel
Port
PS
$ 89
$ 129
$ 249
$989
$ 1995
$1199
$ 695
$ 1199
USB
USB
USB
USB
USB
USB
USB
USB
USB
USB
USB
$ 495
Parallel
Port
PS/Target
USB
USB
USB
USB
USB
$ 1495
USB,
Ethernet
PS
Yes
Yes
TMS320VC33
Yes
Yes
Yes
TMS320C4x
Yes
PC Interface
Powered by
TMS320C30-32
TMS320C5x
Yes
TMS320F24x/F240x
TMS320F28xx
TMS320C54x
TM
TMS320C55xx
TM
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
TMS320C64xx/C64x+
C64x+
C64x+
Yes
Yes
Yes
Yes
Yes
Yes
Yes
TMS320C64+, C66xx
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
ARM 9
ARM 9
Yes
Yes
Yes
Yes
Yes
Yes
Yes
TM
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Processors
Yes
Yes
Yes *
Yes *
Yes *
Yes *
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
TMS470 ARM7
TMS470 ARM9/11
ARM Cortex / OMAP
DaVinci
TM
TM
Sitara
Processors
TM
C6-Integra
+3.3V to +5V
Yes
Yes
+1.8V to +3.3V
Yes
Yes
Supports CCS
v4.x
v5.x
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
v4.2+
v4.2+
v4.2+
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
System Trace Spt
Embedded Trace Buf
C-JTAG Spt (CCS5.x)
Yes
SDFlash Support
Yes
Yes
Yes
Yes
Yes
XMLGUI Support
Yes
Yes
Yes
Yes
Yes
Boundary Scan Spt
Yes
Accessories
Part Number
TI14 Pin Low Voltage Adapter for JTAG Emulators (LVA)
TM
TM
Processors
Price
701208
$ 99
701210
701212
$ 149
$ 149
CTI20(in)-TI14(out)
701218
$ 69
TI14(in)-CTI20(out)
701219
$ 69
CTI20(in)-TI60(out)
701220
$ 74
CTI20(in)-ARM20(out)
701222
TI14(in)-ARM20(out)
701280
$ 69
$ 69
XDS560v2 STM adapter kit, MIPI60 to TI14, CTI20, ARM20, TI60
701238
$ 299
701204
$ 995
TI14-TI14 Pin LVA with Adaptive clock for OMAP /DaVinci
TM
TI14-CTI20 Pin LVA with Adaptive clock for OMAP /DaVinci
4 Channel JTAG Ex
Emulator pander for JTAG Emulators
www.spectrumdigital.com
TM
Processors
©Copyright Spectrum Digital 2012, 09/05/2012
[email protected]
Spectrum Digital, Inc.
12502 Exchange Drive, Suite 440
Stafford, TX. 77477 USA
Tel: 281.494.4500 x-113
Fax: 281.494.5310
Spectrum Digital TI Processor Target Platforms
Processor Family
Target Module
TMS320C3x
TMS320VC33
D.Module.C31eco (OEM)
TM
eZdsp VC33
D.Module.VC33
TM
eZdsp LF2401A
eZdspTM LF2407A
TM
eZdsp F2808
TM
eZdsp F2808/socket
eZdspTM F2812
eZdspTM F2812/socket
TM
eZdsp R2812
TM
eZdsp F28335
TM
eZdsp F28335/socket
DSK VC5416
EVM320VC5502
EVM320VC5505
DSK VC5509A
DSK VC5510
C5515 eZdspTM USB Stick
TM
C5502 eZdsp USB Stick
EVM320C5515
D.Module.C6201 (OEM)
D.Module.C6203
D.Module.C6701 (OEM)
D.Module.C6713
D.Module.C6747
DSK C6713
DSK C6416T, 1Ghz.
EVM DM642, 720 Mhz.
D.Module2.DM642
EVM C6424
EVM DM6455
EVM DM6474
OMAP-L137 EVM
DaVinci DM6437 DVEVM
DaVinci DM6446
DaVinci DM6467
DaVinci DM355 DVEVM
DaVinci DM357
DaVinci DM365 DVEVM
DaVinci DM368 DVEVM
eZ470R1A256
EVM AM1810
EVM C6A816x DDR3
TMS320F24x
TMS320F28xx
TMS320VC54x
TMS320VC55x
TMS320C6000TM
TMS320C64x
TMS320C64x+
OMAP-L13x
DaVinciTM Processors
TMS470 ARM
TM
Sitara
TMS320C6A816x
Scan/Interface Part Number Price
MPSD
PP/JTAG
JTAG
PP/JTAG
PP/JTAG
USB/JTAG
USB/JTAG
PP/JTAG
PP/JTAG
USB/JTAG
USB/JTAG
USB/JTAG
USB/JTAG
JTAG
USB/JTAG
USB/JTAG
USB/JTAG
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EECatalog
SPECIAL FEATURE
Small Cells Connecting a Big
World Require Huge Integration
While Texas Instruments no longer calls itself a “DSP company”, it still leverages
DSP expertise and IP to create dense, feature-packed KeyStone™ SOCs targeting
small cell base stations.
By Chris A. Ciufo, Senior Editor
Take a look at the growth of the Internet, smartphone handsets, tablet computers, M2M, or just about any device that
connects to the Internet and there are two common traits: 1.
growth ranges from “up” to “really up!”; and 2. it’s the need
for data exchange that is driving demand. Increasingly, this
data moves wirelessly over Wi-Fi when inside a building,
and over cellular when outside or traveling around. Wireless
operators are frantically looking for ways to handle increased
demand without investing in expensive wholesale buildout
of their networks. One way to add more bandwidth is by
intelligently handling device data requirements through DPI,
compression, local routing, RF spectrum optimization, and
heterogeneous cellular networks that self-organize.
According to documentation from AirHop Communications, a provider of intelligent Radio Access Network
(RAN) software for multi, small, and macro cell networks:
“network operators are turning to small cell base stations to increase capacity and
complement existing macrocell networks.” The resulting
‘HetNet’ (heterogeneous network) requires self-organizing
network (SON) technology specifically designed for small cell
networks to actively optimize
system capacity and power, and
manage inter-cell interference
when so many cell sites are
situated close by each other.
vide wireline to RF solutions for 3G, 4G, and LTE radio nets.
The density and array of features in these devices is simply
astounding, showcasing a balance of on-chip DSP, RISC CPU,
packet processing, and hierarchical crossbar fabric engines.
Most impressive is how optimized the chips are for making
decisions, moving data, and autonomously handling the task
at hand: making RAN SON small cells work efficiently.
Functional Block Party
TI’s small cell family consists of three devices (Figure 1),
including the TCI6636 designed for up to 256 users. The
system organization of the 6614 shown in Figure 2 shows a
highly integrated SOC broken in several major functional
blocks, all interconnected by the TeraNet fabric crossbar supporting up to 2 Tbits/s data. TeraNet is hierarchical and low
latency, moving the most important data so that on-chip accelerator resources avoid starvation. As well, power consumption
is lower in idle states.
Analysts predict a ratio of 10:1
in favor of small cells vs tradi- Figure 1: TI’s KeyStone™ multicore architecture small cell portfolio includes the TMS320™ TCI6612/14 distional macro cell base stations. cussed here, plus the TCI6636 designed for high capacity small cells and “green power macro cells”. The ‘12
and ‘14 use ARM® Cortex™-A8 cores, while the ‘36 uses an industry-leading ARM® Cortex™-A15.
TI claims to have captured some
The devices are organized as: processor resources; multi50 percent of the designs for small cells, and aims to win
core shared memory; external memory and low-speed I/O;
over 70 percent of the total market. With devices like their
new KeyStone TCI6612 and TCI6614, it’s understandable
high speed I/O; Layer 1 and 2 Bit Rate Coprocessor (BCP)/
why the company is so enthusiastic.
network coprocessors.
All of the onboard functional
blocks, connected by the TeraNet fabric, are under the conAirHop has partnered with Texas Instruments, making
trol of a packet-based manager called Multicore Navigator.
their eSON software available on TI’s KeyStone™ multicore
Navigator handles “fire and forget” communications,
job management and data transfers to assure dynamic
architecture TMS320C66x/ARM® Cortex™-A8-based SOCs
resource scheduling, load balancing, and hardware-based
for small cell base stations. There are two devices – the
TMS320™ TCI6612 and TMS320™ TCI6614 SoCs – that protask prioritization. Between Navigator and TeraNet, data
12
Embedded Processing & DSP Resource Guide 2013
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EECatalog
SPECIAL FEATURE
is designed to flow into and out of the SOC as quickly as
possible with minimal latency or bottlenecks.
According to TI’s Tom Flannigan, Director of Technology
Strategy, MultiCore processors: “For 2G, 2.5G, 3G and 4G
standards a lot is done in hardware, not software.” That means
that packet processing is done in hardware in a network processor-like way; however, unlike the often proprietary nature
of NPUs, standard Eclipse-based tools are used to program the
TI devices, along with the popular and expansive ecosystem
available for C66x and ARM®-based platforms.
We’ll discuss a few of the chips’ subsystems below.
cores folks, churning out a whopping 76.8 GFLOPs. They
also handle fixed point math, and TI claims a 5x increase
over standalone fixed point solutions.
L3 SRAM memory is shared between the cores for data
and for ARM processor program stores. The L3 multicore shared memory is under the control of a dedicated
controller (MSMC) to prevent memory contention, data
starvation, and arbitrates accesses between L2, L3 and
the three (in the ‘12) or five (in the ‘14) cores. The MSMC
also performs another high-performance function in that
it keeps memory data off of the TeraNet fabric, allowing
atomic movement between the cores and freeing up the
fabric for moving packet data between the rest of the
peripherals. TI claims the MSMC has L3 latency that’s
“nearly identical” to the local L2 memories.
Lastly, there’s a 64-bit, 1,600 MHz bus external memory
interface for off-board DDR3 memory under the MSMC’s
control. Because advanced 3G and 4G small cells handle
loads of data, latency is kept low with this interface. The
EMIF can also control 16-bit external NAND and NOR flash.
Garden Variety Peripherals
Before we get to the really fun peripherals, it’s important
to mention the more common interfaces, without which
the chip wouldn’t make a very cooperative system player.
Here again, TI shows off the company’s expertise in
building high density SOCs. On the low-speed side, there’s
I2C, SPI and twin UARTs. There’s also a 32-pin GPIO port
with programmable interrupts fired from key events.
On the high-speed side are four serial RapidIO lanes at 5
Gbits/s, PCI Express (two lanes, GEN1 and GEN2), and the
obligatory Gigabit Ethernet ports (two). Since getting data
between the Ethernet backbone and the air interface is
the IC’s primary function, additional on-chip accelerators
speed network data handling functions.
Figure 2: Block diagram of the TCI6612 and TCI6614. The ‘12 has two
C66x cores whereas the ‘14 has four.
KeyStone™ Multicore Architecture - DSP
and ARM® Processors Married Once Again
Perhaps no company has so successfully married DSP with
ARM cores as TI, as exemplified in their handset OMAP™
processors and SOCs. They’re again hitched together in
the 6612/14 where the C66x boasts “four times the processing power of previous generations of DSPs”. The ARM
Cortex-A8 (and A15 in the TCI6636) handles control plane
processing with 32 KB of L1 SRAM for each C66x core. As
well, there are two C66x cores in the ‘12, and four in the
‘14, with each core supported by its own 1 MB L2 memory
giving a total of 4.8 GHz of DSP processing and up to 153.6
16-bit GMACs per second. And these are floating point
14
There are two Ethernet media access controllers to pipeline
data between the PHY and the DSP cores. This is partly
handled by a data I/O module that continuously polls all
32 addresses “in order to enumerate all PHY devices in the
system”. A packet processor can classify Layer 2 to Layer
4 data at up to 1.5 Gbits/s, while an embedded security
accelerator works at 1 Gbits/s (wire speed) performing
IPSec, SRTP, and 3GPP air interface security protocols.
TI also includes HyperLink and AIF2 ports. The former
is the proprietary 12.5 Gbaud/lane inter-processor backbone used to connect multiple SOCs together. The low
protocol/high rate link between TI KeyStone SoC devices
allows scalable small cell solutions with MultiCore Navigator software dispatching tasks to multiple devices which
appear as local resources in a multiprocessing fashion.
The AIF2 interface is a peripheral module used for transferring baseband IQ data between baseband DSPs and a
Embedded Processing & DSP Resource Guide 2013
ŵĞĚŝĂƚĞĐŚŶŽůŽŐŝĞƐĂŶĚƐLJƐƚĞŵƐ
for placing you first in the market in time and performance
automotive | broadcast | mobile | video communication | video networking
software| hardware| turnkey systems
Ittiam Systems | www.ittiam.com
WƵďůŝĐ>ŝƐƚŽĨ>ŝĐĞŶƐĞĞƐ Carl Zeiss Meditec | Cisco Corporation | Conmed Corporation | FLIR Systems | L3 Communications |
Leadtek | LG Ericsson | Microsoft Corporation | Mitel Corporation |Panasonic Avionics Corporations |
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EECatalog
SPECIAL FEATURE
high-speed serial interface. On the ‘12 and ‘14, the AIF2
second-generation SERDES-based antenna interface is
capable of up to 6.144 Gbits/s per link, and there are six
links available. AIF2 supports OBSAI RP3 and CPRI protocols for the following RF standards: WCDMA/FDD, LTE
cessing that avoids disturbing the DSP cores, they are
lumped together into the bit rate coprocessor (BCP) block
shown in Figure 2 as “Layer 1” and “Layer 2”. The BCP’s
top-level functions are shown in Figure 3 which includes
a CRC engine, turbo interference cancellation for MIMO
equalization - a critical function of small cell
base stations - and various mod/demodulators and interleaver/deinterleavers.
Collectively, the configurable accelerators
and co-processors maximize flow-through
system performance while also reducing
base station complexity through single chip
operation. For example, there’s no need to
implement in off-board FPGAs FFT or DFT
transforms, Viterbi decoders, or LTE decode
logic. Some typical performance numbers are
shown in Figure 4.
Summary
Figure 3: The on-board bit-rate coprocessor (BCP) is designed to move and process data
through the chips without burdening the DSP cores. As such, the BCP includes Layer 1
and Layer 2 processing engines tied together via the TeraNet fabric.
As on-the-go Internet traffic increases
through data transfers, there’s an acute need
for small cell base stations. These offload
macro cells by cost effectively adding users,
bridging wireless standards, and increasing
coverage. Seizing the market with high-integration, high intelligence peripherals, Texas
Instruments’ TMS320TCI6612/14 SOCs offer
barn-burning performance without consuming much power. Taking advantage of all
on-board resources, TI quotes small cell base
station power levels at 26mW per Mbits/s of
data transferred. That’s a tidy way to connect
a big world’s huge demand for wireless data,
one cell site at a time.
Chris A. Ciufo is senior editor for embedded content at Extension Media,
which includes the EECatalog print
and digital publications and website, Embedded Intel® Solutions, and
Figure 4: On-board coprocessors and accelerators, coupled with the TCI6612/14’s flow- other related blogs and embedded
through architecture, returns impressive performance numbers for typical small cell channels. He has 29 years of embedded technology
operations. TI’s goal was to build an SOC needing no external FPGA or ASIC.
experience split between the semiconductor industry
(AMD, Sharp Microelectronics) and the defense industry (VISTA Controls and Dy4 Systems), and in content creation.
(FDD and TDD), WiMax, TD-SCDMA, and GSM/Edge. AIF2
He co-founded and ran COTS Journal, created and ran Military
connects externally to either RF units or other baseband
Embedded Systems, and most recently oversaw the Embedded
devices. The AIF2 interface is so important that it has its
franchise at UBM Electronics. He’s considered the foremost expert
own 433 page manual, separate from the rest of the chip.
on critically applying COTS to the military and aerospace industries,
Not So Garden Variety Peripherals
and is a sought-after speaker at tech conferences. He has degrees in
While the “garden variety” peripherals are impressive,
electrical engineering, and in materials science, emphasizing solid
even more so are the accelerators and co-processors TI
state physics. He can be reached at [email protected]
packs into the twin devices. Designed for bit rate pro-
16
Embedded Processing & DSP Resource Guide 2013
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EECatalog
SPECIAL FEATURE
Analysis of LTE Base Station Software
Deployment on Multicore SoCs
To achieve full multicore entitlement, SoCs require a hardware infrastructure
without bottlenecks, as well as a simplified software infrastructure.
By Sneha Narnakaje and Zhihong Lin, Texas Instruments
The advent of high-speed cellular services
like 4G LTE is driving a paradigm change
in the complexity of wireless base station
design. As wireless technology continues
to evolve, the demand for higher data rates
increases, causing growth in data traffic.
The data deluge has significant implications on the type of processing required.
Data traffic is packet-based and allows
for hundreds of users to be connected to a
base station at the same time, all sharing
the airwaves. Managing data traffic efficiently requires the system to handle large
volumes of data packets moving through all
processing layers. It is becoming increasingly important for OEMs and operators
to effectively handle LTE technology using
multicore systems-on-chip (SoCs), as
multicore architectures bring new levels
of efficiency to base station designs. To
achieve full multicore entitlement, SoCs Figure 2: eNB Protocol Stack
require a hardware infrastructure without
bottlenecks, as well as a simplified software infrastrucNodeB), provide user-plane and control-plane protocol
ture. This article discusses the challenges encountered
terminations (Uu) toward the user equipment (UE,
in traditional software implementation of LTE base stamobile) as well as transport terminations (Iu) toward
tion on a multicore SoC. Further, this paper will show an
the core network. eNodeBs are interconnected through
example of software implementation on a multicore SoC,
X2 interface and also connected to core network EPC
leveraging the hardware infrastructure to effectively and
through S1 interface.
efficiently overcome those challenges.
The eNodeB protocol structure is comprised of two main
LTE Base Station Overview
layers: the radio network layer and the transport net4G LTE is defined
work layer. The radio interface is implemented within
by 3GPP 36 series
three protocol layers: physical layer (Layer 1, PHY), data
technical specificalink layer (Layer 2) and network layer (Layer 3). Layer
tions. LTE provides
2 is partitioned into sublayers called media access conincreased
data
trol (MAC), radio link control (RLC) and packet data
rate and capacity,
convergence protocol (PDCP). Layer 3 includes the radio
better
spectrum
resource control (RRC) sublayer
efficiency, reduced
latency and simeNodeB Implementation Challenges on a
plified
network
Multicore SoC
architecture.
Traditionally, eNodeB implementation in the macro
space has been based on multiple fragmented devices.
LTE base stations,
While multicore DSP devices are used for baseband
also referred to as
(PHY) processing, multicore general-purpose processors
Figure 1: E-UTRAN Architecture eNodeB (E-UTR AN
are used for radio protocol stack processing. In addition,
18
Embedded Processing & DSP Resource Guide 2013
EECatalog
dedicated network processor units, ASIC and FPGA, are
used as bridging devices for transport/backhaul and
radio processing. A combination of fragmented devices
increases the system cost, system power and complexity
to implement the eNodeB on multiple multicore devices.
With the emergence of heterogeneous networks in the
base station market, operators and base station vendors
are focusing on the SoC concept to reduce system cost,
power and complexity, expediting time to market. A basic
approach is to integrate all, if not most, of the functions
on a single chip. Today, we see many SoC architectures
with multicore DSP and RISC cores integrated with a
hardware infrastructure to
enable parallel access to all
cores.
SPECIAL FEATURE
with dedicated packet DMA subsystem. LTE baseband
processing (PHY) is running on two DSP cores, while LTE
user-plane processing (layer 2) is running on the other
two DSP cores. An ARM core runs the LTE control-plane
processing (layer 3 and application). This example of
software implementation of eNodeB leverages high-level
operating system (Linux) services on the ARM core for
the LTE control-plane processing, with real-time operating system (RTOS) on DSPs for the hard real-time layer
2 and PHY processing. The layer 2 downlink timing is
constrained by HARQ retransmission loop and supplying
PDSCH data load to the PHY, while uplink timing is
constrained PUSCH HARQ
process. By allocating layer
2 on the DSP core closer to
the PHY processing, latency
is minimized.
Operators and base station
vendors are focusing on the
SoC concept to reduce system
cost, power and complexity,
expediting time to market.
eNodeB
implementation
on a multicore SoC brings
significant challenges. LTE
brings a paradigm shift for
base station vendors and
their suppliers, with more
complex data processing
and scheduling to achieve
spectral efficiency. While
data processing requires low
latency and higher throughput, scheduling needs to be
dynamic and channel-aware. Multicore SoC architectures
come with their own complexity with parallelism across
cores, hardware abstraction for full multicore entitlement, partitioning of application software, inter-process
communication and shared resource management. A
traditional approach to solving these challenges uses
shared memory-based multithreading. LTE eNodeB functional tasks are distributed across the cores with data
distribution and handled by shared memory. However,
the performance is dependent on the memory access
times, bus bandwidth and cache effectiveness. Hardware
infrastructure bottlenecks have
also made it nearly impossible
to achieve the low latency and
higher throughput required by
LTE data processing.
Many SoC architectures
today harden the network
and security functionality
for eNodeB. However these
hardware accelerators follow
the look-aside approach
requiring CPU cycles to
perform pre- and post-processing for each functional block (e.g., IPSec, Ciphering).
With this approach, the throughput varies with the
packet size. Instead, hardware accelerators enabled with
f low-through fast-path processing can achieve maximum
throughput for all packet sizes. In addition, after all the
fast-path processing, if the packets land in dedicated prioritized hardware queues, the CPU is not burdened with
data handling.
Hardware queues play an important role in implementing
eNodeB packet processing. When eNodeB packet processing
(PHY, layer 2 and 3) tasks are distributed across multiple
An Example of Software Implementation
of eNodeB on a Multicore SoC
The example of software implementation of eNodeB is based
on a multicore SoC for small
cells. The architecture for this
multicore SoC integrates four
DSP cores with an ARM core.
The hardware infrastructure
includes a network and security
accelerator and a queue manager Figure 3: eNodeB Software Deployment on a Multicore SoC
www.eecatalog.com/dsp
19
EECatalog
SPECIAL FEATURE
cores, packets need to be handled efficiently and effectively,
without any bottlenecks. Hardware queues in this architecture guarantee the multicore atomicity of all accesses to the
queues, enabling the zero-copy approach for the eNodeB
packet processing. The zero-copy RLC/MAC concept leverages the fact that the data payload requires no processing
between the PDCP (de)ciphering and the CRC generation
(or check) at the PHY encoder/decoder. RLC and MAC sublayers need to aggregate/deaggregate, segment/desegment,
multiplex/demultiplex data packets and add/remove control information and headers. Accomplishing this without
touching the payload data (zero-copy) saves 90-95 percent
of processing cycles. Therefore, payload data resides in DDR
and can never be touched by layer 2 software. For example,
in the downlink direction, packets are received, IPSec
decrypted, classified, GTPU processed, air ciphered by
network and security accelerator, then allocated and delivered to the per radio bearer hardware queue by dedicated
packet DMA. All steps above are performed without software intervention. RLC/MAC software operates on packet
descriptors and does not need to access the packet payload.
It builds MAC PDUs, which are sent out and reassembled
back to contiguous memory by the packet DMA.
With key benefits such as spectral efficiency, flexible
channel bandwidth and capital expenditure savings, LTE is
driving operators to deploy LTE networks. While effective
LTE systems can be designed on a multicore architecture,
achieving full multicore entitlement is the key to unleashing
multicore performance and reaping the benefits of 4G systems. Supporting efficient and effective LTE system designs
require a number of innovations in multicore architecture
design. One such innovation is a hardware infrastructure
without bottlenecks, enabling packet processing, memory
access and core-to-core communication.
Based on a presentation at the 2012 Multicore DevCon.
Sneha Narnakaje is the software product manager for TI’s wireless base station infrastructure
team. In this role, she is responsible for TI’s common software strategy and roadmap across the
wireless base station infrastructure team and
driving business development activities. She
earned her MBA from the University of Maryland (Smith) and
BS in computer engineering from Mangalore University, India.
As a strategic marketing manager for TI’s multicore processors group, Zhihong Lin is responsible
for defining and planning key requirement for
multicore SoC for wireless base station applications. Zhihong has over 18 years of experience
in both communications and networking industries. Zhihong holds a US patent on communications and
received her MSEE degrade from University of Texas at Dallas.
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22
Embedded Processing & DSP Resource Guide 2013
EECatalog
SPECIAL FEATURE
Top 3 Mistakes with Static
Analysis for Embedded and
Safety-Critical Development
By Arthur Hicken, Evangelist, Parasoft
The high cost of repairing defects shipped in embedded
devices, paired with the increasing need to follow regulatory compliance initiatives for safety-critical embedded
systems software (FDA, DO-178B/C, IEC 61508) has
driven many organizations to adopt static analysis as a
key part of their quality strategies.
Static analysis is one of the most effective and least burdensome of such industry-standard best practices. In fact,
it is often explicitly recommended (e.g., per the FDA's recommendation for infusion pumps) as one key component
of a comprehensive quality strategy. When properly implemented, static analysis is a very powerful tool for exposing
error-prone code. Finding and fixing such code from the
earliest phases of the software development lifecycle has
been proven to be a very effective (and cost-efficient) way
to prevent defects from being shipped in the final product.
Static analysis is a critical component of a comprehensive
quality process...but it is just one component. It's important
to remember that most effective quality processes involve
a combination of test and analysis practices embedded
throughout the SDLC. In addition to static analysis, an
effective quality strategy covers practices such as:
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t 3FHSFTTJPOUFTUJOH
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to be the top three reasons why static analysis initiatives
don’t deliver real value in embedded and safety-critical
development environments—and some critically important tips for avoiding these common pitfalls.
3. Starting With Too Many Rules
Some eager teams take the "big bang" approach to static
analysis. With all the best intentions, they plan to invest
considerable time and resources into carving out the
penultimate static analysis implementation from the
start—one that is so good, it will last them for years.
They assemble a team of their best engineers. They read stacks
of programming best practices books. They vow to examine
all of their reported defects and review the rule descriptions
for all of the rules that their selected vendor provides.
I've found that teams who take this approach have too
many rules to start with and too few implemented later
on. It's much better to start with a very small rule set, and
as you come into compliance with it, phase in more rules.
Static analysis actually delivers better results if you don't
bite off more than you can chew. When you perform static
analysis, it's like you're having an experienced engineer
stand over the shoulder of an inexperienced engineer and
give him tips as he writes code. If the experienced engineer is constantly harping on nitpicky issues in every few
lines of code, the junior engineer will soon become overwhelmed and start filtering out all advice—good and bad.
However, if the experienced engineer focuses on one or
two issues that he knows are likely to cause serious problems, the junior engineer is much more likely to remember
what advice he was given, start writing better code, and
actually appreciate receiving this kind of feedback.
t 3FRVJSFNFOUTUSBDFBCJMJUZ
At Parasoft, we've been assisting software development organizations to implement and optimize static
analysis since 1996. Over the years of analyzing static
analysis deployments across safety critical, embedded,
and enterprise software development organizations, we've
determined what mistakes are most likely to result in
failed static analysis initiatives. Here's what we've found
www.eecatalog.com/dsp
It's the same for static analysis. Work incrementally—with
an initial focus on truly critical issues—and you'll end up
teaching your engineers more and having them resent the
process much less. Would you rather have a smaller set of
rules that are followed, or a larger set that isn't?
23
EECatalog
SPECIAL FEATURE
Out of the hundreds or sometimes even thousands of rules
that are available with many static analysis tools, how do
you know where to start? Here are a few simple guidelines:
how you can fix it (e.g., by fine-tuning the rule set, using
suppressions judiciously).
1. Lack of a Clear Policy
1. Would team leaders stop shipping if a violation of this
rule was found?
2. (In the beginning only) Does everyone agree that a violation of this rule should be fixed?
3. Are there too many violations from this rule?
In regulated environments, this rule is elevated to the
status of a commandment. The more you get into the habit
of frequently suppressing or ignoring rule violations, the
more likely you are to have to tell an auditor or attorney
why you ignored reports of an issue that ultimately caused
a serious defect in the field. From a negligence perspective, it's much safer to define a tight rule set and ensure
that every violation is addressed than to have a large one
that is loosely followed.
2. No Automated Process Enforcement
Without automated process enforcement, engineers
are likely to perform static analysis sporadically and
inconsistently—which is not only problematic from a
compliance perspective, but also diminishes your ability
to derive maximum defect-prevention value from static
analysis. The more you can automate the tedious static
analysis process, the less it will burden engineers and
distract them from the more challenging tasks they truly
enjoy. Plus, the added automation will help you achieve
consistent results across the team and organization.
Avoid the false economy of an automated run that still
requires a manual triage process at the end. A tighter
configuration will provide more value without the need
for manual review and selection of what to fix.
Many organizations follow a multi-level automated
process. Each day, as the engineer works on code in the
development environment, he or she can run analysis
on demand—or configure an automated analysis to run
continuously in the background (like spell check does).
Engineers clean these violations before adding new or
modified code to source control.
Then, a server-based analysis can run as part of continuous integration, or on a nightly basis, to make sure
nothing slipped through the cracks.
It's common for organizations to overlook policy because
they think that simply making the tool available is sufficient. It's not. Even though static analysis (done properly)
will save engineers time in the long run, they're not going
to be attracted to the extra work it adds upfront. If you
really want to ensure that static analysis is performed as
you expect—even when the team's in crunch mode, scrambling to just take care of the essentials—policy is key.
Every team has a policy, whether or not it's formally
defined. You might as well codify the process and make it
official. After all, it's a lot easier to identify and diagnose
problems with a formalized policy than an unwritten one.
Ideally, you want your policy to have a direct correlation to
the problems you're currently experiencing (and/or committed to preventing). This way, there's a good rationale
behind both the general policy and the specific ways that
it's implemented.
With these goals in mind, the policy should clarify:
t 8IBUUFBNTOFFEUPQFSGPSNTUBUJDBOBMZTJT
t 8IBUQSPKFDUTSFRVJSFTUBUJDBOBMZTJT
t 8IBUSVMFTBSFSFRVJSFE
t 8IBUEFHSFFPGDPNQMJBODFJTSFRVJSFE
t 8IFOTVQQSFTTJPOTBSFBMMPXFE
t 8IFOWJPMBUJPOTJOMFHBDZDPEFOFFEUPCFGJYFE
t 8IFUIFSZPVTIJQDPEFXJUITUBUJDBOBMZTJTWJPMBUJPOT
Arthur Hicken, Evangelist for Parasoft, has
been involved in automating various practices
at Parasoft for almost 20 years. He has worked
on projects including database development, the
software development lifecycle, web publishing
and monitoring, and integration with legacy systems.
Assuming that you have a policy requiring that all violations from the designated rule set are cleaned before check
in, any violations reported at this level indicate that the
policy is not being followed. If this occurs, don't just have
the engineers fix the reported problems. Take the extra
step to figure out where the process is breaking down, and
24
Embedded Processing & DSP Resource Guide 2013
Embedded Processing Overview
DaVinci™ Video Processors:
Optimized for Digital Video
DaVinci™ video processor solutions are tailored
for digital video, imaging, and vision applications.
Optimized for video encode and decode applications,
the DaVinci platform includes a general purpose
processor, video accelerators, an optional DSP,
and related peripherals. A wide range of devices
are available, offering a variety of performance,
power and price points.
High Performance: TMS320C6000™
DSP Platform
The C6000™ DSP platform offers the industry’s
highest-performance single- and multicore DSPs,
ideal for networking, telecommunication, video,
imaging, infrastructure, test and equipment,
military, and industrial applications. The platform
includes C64x high-performance DSPs,
C674x fixed-/floating-point DSPs and C66x
fixed-/floating-point multicore DSPs. It also
includes the OMAPL series which combines
a C674x DSP with an ARM9™ processor to handle
networking and control for computational efficiency.
Ultra-Low-Power TMS320C5000™
DSP Platform
The C5000™ DSP platform provides a broad
portfolio of the industry’s lowest power 16-bit DSPs.
Total active core power at less than 0.15 mW/MHz
at 1.05V and standby power at less than 0.15mW
extends the battery life of portable applications.
Increase processing capability with C5000 DSP
processors that offer up to 300MHz (600 MIPs).
High peripheral integration and large on-chip
memory helps reduce overall system cost. Ultra low
cost development boards, system development kits,
free and highly mature software libraries with an
extensive database of code examples enables fast
time to market. With these advantages, the C5000
has become a very popular choice for a variety of
low-power and cost-efficient embedded signal
processing solutions, including portable devices in
audio, voice, communications, medical, security
and industrial applications.
C2000™ 32-Bit Microcontroller for
Real-Time Control
The C2000™ microcontroller family combines
advanced control peripherals with the processing
power of a 32-bit core. With the low-cost,
high-integration Piccolo™ MCUs, the powerful
Delfino™ floating-point MCUs and the connectivity
and control featured in the Concerto™ MCUs, C2000
MCUs offer a broad range of options and are ideal for
embedded industrial control and green
energy applications such as digital motor control,
digital power supplies, solar and wind energy, LED
lighting, and automotive HEV/EV.
MSP430™ Ultra-Low-Power
Microcontroller Platform
The MSP430 family of ultra-low-power
16-bit RISC mixed-signal processors provides
the ultimate solution for battery-powered
measurement applications. Using leadership
in both mixed-signal and digital technologies,
TI has created the MSP430 MCU, enabling system
designers to simultaneously interface to analog
signals, sensors and digital components while
maintaining unmatched low power.
Sitara™ ARM® Processors
The high-performance Sitara ARM-based
processors include solutions based on the
ARM Cortex™-A8 and ARM9™. The platform
includes the AM1x, AM35x, AM37x and AM335x
processors, which offer a software-compatible
roadmap for customers using TI’s OMAP35x
and OMAP-L1x processors.
Stellaris® 32-Bit ARM Cortex-M MCUs
Texas Instruments is the industry leader in
bringing 32-bit capabilities and the full benefits
of ARM® Cortex™-M microcontrollers (MCUs) to
the deepest reach of the microcontroller market.
With more than 220 compatible ARM Cortex-M
Stellaris MCUs and more than 30 Stellaris evaluation,
development, and reference design kits, Stellaris fits
the performance, integration, power, and price-point
requirements of nearly any industrial application.
Stellaris with Cortex-M offers a direct path to the
strongest ecosystem of development tools, software
and knowledge in the industry. Designers who
migrate to Stellaris benefit from great tools, small
code footprint, and outstanding performance. With
StellarisWare® Software, Stellaris gives developers
a huge jump start by providing a free, royalty-free
software package that includes a peripheral driver
library, graphics library, USB library, code examples,
and much more.
Embedded Processors
Embedded Processors
Texas Instruments has the broadest portfolio of scalable DSP, MCU, differentiated ARM® and complementary analog products, offering
complete system solutions for electronics manufacturers. This portfolio offers the full range of power/performance requirements ensuring
the right combination of attributes for the smallest portable devices to the largest multichannel systems and everything in between. In
addition, TI offers design resources including extensive software (including open source), tools, technical training, in-person and online tech
support, and engineer-to-engineer forums at www.e2e.ti.com. Visit www.ti.com for technical literature, system block diagrams and more.
Hercules™ Safety Microcontrollers
Hercules safety microcontrollers are based on
TI’s 20+ years of safety-critical system expertise,
industry collaboration and proven hardware for the
automotive market. The platform consists of three
ARM® Cortex™-based microcontroller families
(RM48x, TMS570 and TMS470M) that deliver
scalable performance, connectivity, memory and
safety features. Unlike many microcontrollers that
rely heavily on software for safety capabilities,
Hercules microcontrollers implement safety in
hardware to maximize performance and reduce
software overhead.
Software and Development Tools
TMS320™ DSPs are supported by eXpressDSP™
software and development tools, including Code
Composer Studio™ IDE, DSP/BIOS™ kernel, the
TMS320 DSP algorithm standard and numerous
reusable, modular software from the largest
developer network in the industry.
Complementary Analog Products
TI offers a range of complementary data
converter, power management, amplifiers,
interface and logic products to complete
your design.
Applications Matrix Guideline
DaVinci™
Video
Processors
C6000™
Digital Signal
Processors
C5000™
Digital Signal
Processors
C2000™
MSP430™
Microcontrollers Microcontrollers
Sitara™
32-bit ARM®
Cortex™-A
Processors
Stellaris® 32-Bit
Hercules™
ARM® Cortex-M
Safety
MCUs
Microcontrollers
Video
processing
High
performance
Ultra-low
power
Performance,
integration for Ultra-low power
greener industrial
applications
Low power,
high
performance
Open architecture software, Safety Integrated
rich communicain H/W
tions options
Audio
Automotive
Communications
Industrial
Medical
Security
Video
Wireless
Key Feature
www.eecatalog.com/dsp
25
TMS320C6x and TMS320C5x DSPs, Fixed- and Floating-Point
High-Performance, Low-Power DSPs
Specifications
t $™ high performance fixed/
floating-point DSP
t $™ ultra-low power fixed-point
DSP; industry’s lowest cost and
lowest power DSPs
t 3PCVTUTPGUXBSFBOEUPPMT$PEF
Composer Studio™ IDE, Software
Development Kits, Application
Software and Libraries
t 4ZT#*044UBSUFS8BSFBOE-JOVY
software development kits, developed
and supported by TI
t 3FBMUJNFTJHOBMQSPDFTTJOH
Targeted Applications
Biometric Security, Smart E-Meter
AMR/AMI, Industrial Drives, Portable
audio/voice, Portable Medical
Key Features
C5000 Ultra-low-power DSPs
t 6QUP.)[
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t 6QUP,#3".
t 6QUP,#30.
t 41**2C, I2S
t )464#
t -$%
t .D#41
t UP
C6000 High-performance DSPs
t 6QUP.)[
t 'JYFEGMPBUJOHQPJOU%41
t 6QUP,#3".,#
internal RAM
t %%3.%%3
t .D#41.D"412C, SPI
t -$%DPOUSPMMFSWJEFP*0611
t UP
C6000 DSP+ARM9™
t 6QUP.)[
fixed-/floating-point DSP
t 6QUP.)["3.
t .D"41.D#41*2C, SPI
t -$%DPOUSPMMFSWJEFP*0611
t ,TIBSFE3".
t 64#64#
ethernet MAC, SATA
t %%3.%%3
t UP
26
Production
%FWFMPQNFOU
4BNQMJOH
'VUVSF
1JO$PNQBUJCMF
C66x+ARM
C674x+ARM9
DSP+
Low Power ARM
0."1-Y
C674x+ARM9
C66x+ARM
t%416QUP.)[
t"3.6QUP.)[
t&."$64#
PRU
t-$%71*'4"5"
t4%3".-1%%3%%3
DSP + ARM
SoCs
C6000
t*ODSFBTFE1FSGPSNBODF
t*ODSFBTFE$POOFDUJWJUZ
$0/$&15
C6000
C66x
C6424/1
General
Purpose
DSPs
t%416QUP.)[
t&%."&."$
.D"412$7144
t6QUP.#-
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C5000
C5504/5/14/15
Ultra-Low
Power DSPs
t6QUP.)[64#
SDRAM
t''5-$%-%0T
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tN8.)[
C674x
C6xx DSP
t%416QUP.)[
t&."$64#
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C5000
t*ODSFBTFE1FSGPSNBODF
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C5000
$
t6QUP.)[
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t''5-$%
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tN8.)[
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C5000
C5xx Next
C5517
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t6QUP.)[64#
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$0/$&15
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Low $
)
Low $
)
Singlecore DSP Roadmap
Single-core DSP focuses on real-time applications, driving the lowest system cost and power, with
differentiated solutions.
TMS320C553x DSP Block Diagram
The C553x ultra-low-power DSP generation featuring the lowest power and lowest cost DSP in the
industry, starting at $1.95/1ku, offers the industry’s lowest power with active power less than 0.15
mW/MHz at 1.05V and standby power less than 0.15 mW. These highly integrated processors
enable developers to get DSP sophistication at a microcontroller price and power consumption.
Embedded Processing & DSP Resource Guide 2013
Embedded Processors
Embedded Processors
Get samples, data sheets, tools and app reports at: www.ti.com/singlecore
C2000™ Microcontrollers, Fixed-Point and Floating-Point
MCU Real-time Control, 32-Bit Performance
Applications
Green energy (solar, wind, fuel cells), digital
motor control (home appliances, industrial
drives, medical), Intelligent LED Lighting,
digital power supplies (telecom and server
rectifiers, wireless basestations, UPS),
automotive (HEV/EV, electric power
steering, driver’s assistance radar, wipers,
HVAC), Power Line Communications
MIPS
150
100
80
60
F2823x
www.eecatalog.com/dsp
Connectivity and
performance
Delfino™
(176 – 256 pins)
$9 – $16
Floating Point
performance
Piccolo™
(38 – 100 pins)
$<2 – $8
Floating Point
with co-processor
options
Next
F28M35x
ENET
USB
CAN
C2834x
CAN
F28M35x
Next
60-100 MHz M3
60-150 MHz28x FPU
Industrial safety
512 KB-1MB Flash
Ethrnet, USB OTG, VCU
Performance
Connectivity
Safety enhancements
F2833x
CAN
C2834x
Up to 600 MFLOPS
196-516 KB SRAM
External ADC
Low active power
F2833x
Up to 300 MFLOPS
128-512 KB Flash
52-68 KB SRAM
F281x
F2806x
F280x
Next
F2806x
USB
CAN
F2803x
CAN
Next
90 MHz 28x, 90 MHz CLA Performance
Co-processor, FPU, VCU Memory
Connectivity
128-256 KB Flash
36-100 KB RAM
DMA, USB FS host
F2803x
Fixed- Point
with co-processor
options
F2801x
60 MHz 28x
60 MHz CLA co-processor,
64-128 KB Flash,
20kB RAM
F2802x
Production
Development
40
Sampling
Future
F2802x
Fixed- Point
low cost
40-60 MHz,
32-64 KB Flash,
6-12 KB RAM
Next
Low power
Small packaging
More analog
Next
100+ Code compatible devices All pricing is to be considered budgetary and subject to change. Pricing is 1KU -40 to 50˚ C.
TMS320C2000 Microcontroller Platform Roadmap
The C2000™ controller platform provides an optimized combination of DSP performance
and MCU integration for digital control systems.
Features
t *OEVTUSZTNPTUFGGJDJFOU$DPNQJMFS
for 32-bit controllers
t 6QUP.)[PQFSBUJPO
t 4JOHMFQSFDJTJPOCJUGMPBUJOHQPJOU
unit on select devices
t 6MUSBGBTUJOUFSSVQUSFTQPOTFUJNF
t *OUFHSBUFESFBMUJNFEFCVHHJOHTJNQMJGJFT
control system development
t 4JOHMFDZDMFYCJU
multiply-accumulate
t .VMUJQMFDPNNVOJDBUJPOJOUFSGBDFT
including Ethernet and USB
t "OBMPHJOUFHSBUJPOUPSFEVDFCJMMPG
materials costs and simply design
t $PODFSUP"3.$YEFWJDFTPGGFSJOH
the best ofC28x control and ARM
connectivity
Peripherals
t 6QUP,#GMBTIBOE,#3".
t 6MUSBGBTUCJU"%DPOWFSUFSXJUIVQ
to 80-ns conversion time
t )JHISFTPMVUJPO18.BMMPXTEVUZDZDMF
modulation down to 55-ps accuracy
t 'MFYJCMF18.HFOFSBUJPOBMMPXTFBTZ
generation of any switching waveform
t 2VBESBUVSFFODPEFSJOUFSGBDFTBOE
capture peripherals for easy motor
feedback
t $PEFTFDVSJUZNPEVMFXJUICJU
password protection
t .VMUJQMFDPNNVOJDBUJPOTJOUFSGBDFT
Concerto™
(144 pins)
$<7 – $20
300
Performance and memory
Specifications
t CJU$Y™ MCU core with
floating-point option
t .$6TSBOHJOHGSPN.)[VQUP
.)[BOE.'-01T
t *OEVTUSZMFBEJOH18.BOE"%$
control peripherals
t 0OMZQSPDFTTPSTXJUIGVMMTPGUXBSF
compatibility between fixed-point and
floating-point
t "MM$YDPOUSPMMFSTBSF"&$2
qualified for automotive applications
Embedded Processors
Embedded Processors
Get samples, data sheets, tools and app guides at: www.ti.com/c2000
Piccolo™ Microcontrollers
Real Control. Real Time. For Real Systems.
Highly-integrated microcontrollers for real-time control
of cost-sensitive power electronics applications. With
control-optimized performance, specialized peripherals,
and a control-focused architecture, Piccolo MCUs bring
innovation solutions to demanding control challenges.
Starting
at $1.50
Packages
from 38
to 100
pins
Starting
Delfino™ Microcontrollers
High Performance. For High End Control. at $8.95
The leading microcontroller platform for high performance
control needs. With up to 300 MHz performance, industry
leading PWM control resolution, and blazing ADC conversion speeds, Delfino MCUs tackle the toughest control
challenges.
Packages
from 176
to 256
pins
Concerto™ Microcontrollers
Connectivity. Control. No Compromise.
Starting
at $6.71
Differentiated microcontroller platform combining the
ARM® Cortex™-M3 core with C2000’s C28x core in
a single MCU package. Concerto MCUs bring together
leading host communications and leading real-time
control without compromise of control performance or
communications.
High Voltage Motor
Control & PFC Kit
DC/DC LED
Lighting Kit
High Voltage
Bridgeless PFC Kit
Packages
from 144
pins
F28069 Piccolo
USB Stick
Access the latest C2000 MCU software, documentation, and more through controlSUITE software.
Download today at www.ti.com/controlsuite
27
MSP430™ Microcontrollers
Ultra-Low Power, Easy-to-Use, 16-Bit RISC Microcontrollers
Key Features
t Ultra-low-power (ULP) architecture
and flexible clock system extend
battery life:
0.1-μA RAM retention
<1-μA RTC mode
<100 μA MHz
t Integrated intelligent peripherals
including a wide range of high-performance analog and digital peripherals that off-load the CPU
t&BTZUPVTF16-bit RISC CPU
architecture enables new applications
with industry-leading code density
t&BTZUPHFUTUBSUFEComplete
development ecosystem with tools
TUBSUJOHBU
t&OIBODFEMJCSBSJFTto benefit several
applications such as capacitive touch,
metering metrology, low power
design and debugging
Ultra-Low Power Performance — Analog Integration — Easy-to-Use
All devices feature:
0.9V-1.65V
Speed: 4 MHz
tCJUUJNFST
ROM: Up to 2Kb
t8BUDIEPHUJNFS
RAM: Up to 2Kb
t*OUFSOBM%JHJUBMMZ
GPIO: 11
Controlled Oscillator
FRAM
Comp
Speed: 16 MHz
Flash: 0.5-16Kb
RAM: Up to 512b
GPIO: 10-24
SVS
LCD
BOR
F5xx/6xx
USCI
Speed: 8/16 MHz ADC10,12 Speed: 25 MHz
Flash: 4-120Kb
Flash: 8-256Kb
RAM: Up to 8Kb SD16 RAM: Up to 18Kb
GPIO: 14-80
GPIO: 32-83
Comp
Comp
Temp
SVS
BOR
CC430
SVM Speed: 20 MHz
Flash: 8-16Kb
LDO RAM: Up to 4Kb
GPIO: 40
MPY
SVS
SVM
LDO
MPY
UART
DAC12
USCI
Cap sense
I/Os
DMA
MPY
DMA
DMA
ADC8
BOR
OpAmp
MPY
USB
SVS
BOR
ADC10,12
SVS
OpAmp
ADC10
Sub 1 GHz
RF
AES
SVM
ADC10, 12
SD24
USART
SVS
Comp
Comp
Comp
USCI
USART
RTC
RTC
DAC12
USCI
ESP430
WDT
ADC12
SIF
ESP430
LCD
LCD
SD24
SVS
Basic
SCAN_IF
Timer
Basic
WDT+
Timer
RTC_C
WDT+
USCI
RTC
LDO
ADC10
ADC12
F1xx
Speed: 8 MHz
Flash: 1-60Kb
RAM: Up to 10Kb
GPIO: 14-48
USCI
Comp
DAC12
DMA
DMA
MPY
MPY
SVS
OpAmp
USART
All Devices
F2xx
Speed: 16 MHz
Flash: 1-120Kb
RAM: Up to 8Kb
GPIO: 10-64
USCI
USI
MSP430 portfolio overview
t MSP430x1xxo'MBTI30.CBTFE.$6T
offering 1.8-V to 3.6-V operation, up to 60
KB, 8 MIPS and a wide range of peripherals.
t MSP430F2xxo'MBTICBTFEGBNJMZGFBUVSing even lower power and up to 16 MIPS
with 1.8-V to 3.6-V operation. Additional
enhancements include ±1 percent on-chip
very-low-power oscillator, internal pull-up/
pull-down resistors and low-pin-count
PQUJPOT'MBTICBTFE.$6TXJUI77
PQFSBUJPOVQUPL#'MBTIBOEVQUP
B RAM. MSP430G2xx2 and MSP43G2xx3
provide unique capacitive touch sense I/O
ports.
t MSP430x4xxo'MBTI30.CBTFEEFWJDFT
offering 1.8-V to 3.6-V operation, up to
,#GMBTI30.BOE.*14XJUI'--
+ SVS along with an integrated LCD controller. Ideal for low-power metering and medical
applications.
28
F4xx
WDT
DMA
Some Devices
ADC10
A-POOL
t&YUFSOBM
crystal support
tO"QJOMFBLBHF
t˜TXBLFVQ
Speed 24 MHz
FRAM 4-16kB
GPIO 14-28
Non-volatile
memory
G2xxx
BOR
BOR
BOR
DAC8
PMM
BOR
L092
PMM
MSP430™
16-bit RISC CPU
PMM
Key Applications
t -PXQPXFSXJSFMFTTBQQMJDBUJPOT
t $POTVNFSFMFDUSPOJDT
t 6UJMJUZNFUFSJOH
t *OUFMMJHFOUTFOTJOHBOEDPOUSPM
t 1PSUBCMFNFEJDBMBOEJOTUSVNFOUBUJPO
t 4FDVSJUZTZTUFNT
t MSP430F5xx/6xx – New flash-based
microcontroller family featuring the lowest
power consumption and performance up to
25 MIPS. It offers a wide operating voltage
SBOHFGSPN7UP7'FBUVSFTJODMVEF
an innovative power management module
for optimizing power consumption, an internally controlled voltage regulator, integrated
LDC driver on select devices and a wide
range of memory options up to 256 KB.
t MSP430FR57xx – 16-bit microcontroller
GBNJMZGFBUVSJOHFNCFEEFE'3".NFNPSZ
Cuts the industry’s lowest active power consumption by 50%, operating at less than
V".)['FBUVSFTXSJUFTQFFETY
faster than flash-based MCUs and virtually
unlimited write endurance. True unified
memory means designers can partition the
memory between code or data depending
on the application.
Embedded Processing & DSP Resource Guide 2013
Embedded Processors
Embedded Processors
Get samples, data sheets, tools and app reports at: www.ti.com/msp430
t -BSHFSFHJTUFSGJMFFMJNJOBUFT
accumulator bottleneck
t 0QUJNJ[FEGPS$BOEBTTFNCMFS
programming
t $PNQBDUDPSFEFTJHOSFEVDFTQPXFS
and cost
t 6QUP.*14PGQFSGPSNBODFBWBJMBCMF
The MSP430™ MCU’s orthogonal architecture provides the flexibility of 16 fully
addressable, single-cycle 16-bit CPU
registers and the power of a RISC. The
modern design of the CPU offers versatility
using only 27 easy-to-understand instructions and seven consistent addressing
modes. This results in a 16-bit low-power
CPU that has more effective processing, is
smaller-sized and more code-efficient than
other microcontrollers. Develop new ultralow power, high-performance applications
at a fraction of the code size.
15
RO/PC Program Counter
R1/SP
Stack Pointer
R2/SR/CG1
Status
0
R3/CG2 Constant Generator
R4
General Purpose
R15
General Purpose
The MSP430 CPU core with sixteen 16-bit
registers, 27 core instructions and seven
addressing modes results in higher processing
efficiency and code density.
Embedded Processors
Embedded Processors
16-Bit RISC CPU
Ultra-Low Power Performance
The MSP430 microcontroller is designed
to provide industry-leading ultra-low
power performance. A flexible clocking
system, multiple operating modes and
zero-power always-on brown-out reset
(BOR) are implemented to reduce power
consumption and dramatically extend
battery life. The MSP430 BOR function
is always active, even in all low-power
modes, to ensure the most reliable performance possible. The MSP430 CPU architecture with 16 registers, 16-bit data and
16-/20-bit address buses minimizes
power consuming fetches to memory,
while a fast vectored-interrupt structure
reduces the need for wasteful CPU software flag polling. Intelligent hardware
peripheral features were also designed to
allow tasks to be completed more efficiently and independent of the CPU. Many
MSP430 customers have developed
battery-based products that will last for
over 10 years from the original battery.
Ultra-Low Power Checklist:
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t 0.1-μA RAM retention
t <1-μA real-time clock mode
t <100μA/MHz
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used by the high-speed peripherals. By
design, the DCO is active and stable in
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MSP430 device-based solutions efficiently
use 16-bit RISC CPU high performance
in very short burst intervals. This results
in very high performance and ultra-low
power consumption.
Flexible Clock System
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ultra-low power standby mode
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high-performance processing
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The MSP430 MCU clock system is
designed specifically for battery-powered
applications. Multiple oscillators are utilized to support event-driven burst activity.
A low-frequency auxiliary clock (ACLK) is
driven directly from a common 32-kHz
watch crystal or the internal very-lowpower oscillator (VLO) – with no additional
external components. The ACLK can be
used for a background real-time clock self
wake-up function. An integrated highspeed digitally controlled oscillator (DCO)
can source the master clock (MCLK) used
by the CPU and sub-main clock (SMCLK)
www.eecatalog.com/dsp
Very-Low Power
Oscillator (VLO)
Up to 20 kHz
ACLK 32 kHz
32.768 kHz
fCrystal
Low-Power Peripherals
Control
MCLK 100 kHz – 16 MHz
Digitally
Controlled
Oscillator
CPU and Peripherals
Multiple oscillator clock system
29
Sitara™ ARM® Cortex™-A8 and ARM9™ Processors
High-Performance, Low-Power Processors
30
Cortex-A8
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performance
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Cortex-A8
Performance + Integration
Specifications
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accelerator
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Targeted Applications
Automation and control, human machine
interface, medical, portable data terminals
Key Features
AM335x ARM Cortex-A8 processors
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up to 20M/tri/s performance
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additional device flexibility
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AM37x ARM Cortex-A8 processors
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Technology’s POWERVR SGX graphics
accelerator
AM35x ARM Cortex-A8 processors
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AM18x and ARM9 processors
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Key Peripherals
ARM Cortex-A8 processors
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t CAN
t SATAII + PHY
AM37x ARM Cortex-A8 processors
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interface x3, 1.8-V input/output and display
subsystem with LCD controller and video
encoder with composite and S-video support
AM35x ARM Cortex-A8 processors
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AM18x ARM9 processors
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video input options
AM17x ARM9 processors
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Ethernet MAC, LCD controller
AM335x
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ICSS
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Concept
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2012
2013
Sitara ARM Microprocessor Roadmap
By utilizing ARM processors and common peripheral sets, Sitara ARM processors offer highly
reusable software code bases that allow designers to easily scale within the product family.
Multiple operating frequencies, 3-D graphics acceleration, multiple packaging options and
temperature operating points further provide optimal flexibility to fit most application requirements.
AM335x Processor
Graphics
ARM®
Cortex-A8
up to
720* MHz
Display
24-bit LCD Control (WXGA)
Touch Scr. Control (TSC)**
PowerVR
SGX
3D Gfx
20 M/Tri/s
32K/32K L1 w/ SED
Security
w/crypto acc.
256K L2 w/ ECC
64K
Shared RAM
64K RAM
PRU-ICSS
EtherCAT®
PROFINET®
Ethernet/IP™
and more
L3/L4 Interconnect
System
Parallel
UART×6
EDMA
SPI ×2
Timers ×8
MMC/SD/
SDIO ×3
I2C ×3
WDT
McASP ×2
(4 ch)
RTC
Serial Interface
CAN ×2
(2.0B)
eHRPWM ×3
eQEP ×3
eCAP ×3
JTAG/ETB
ADC (8 ch)
12-bit SAR**
GPIO
USB 2.0 OTG
+ PHY ×2
EMAC 2port
10/100/1G
w/1588 and
switch
(MII, RMII, RGMII)
Memory Interface
LPDDR1/DDR2/DDR3
NAND/NOR
(16b ECC)
* 720 MHz only available on 15x15 package. 13x13 is planned for 500 MHz.
** Use of TSC will limit available ADC channels.
SED: Single error detection/parity.
Embedded Processing & DSP Resource Guide 2013
Embedded Processors
Embedded Processors
Get samples, data sheets, tools and app reports at: www.ti.com/sitara
Stellaris® 32-Bit ARM® Cortex™-M MCUs
Overview
TI Stellaris MCUs are the industry’s
leading family of robust, real-time
microcontrollers based on the
revolutionary Cortex-M technology
from ARM. The award-winning
Stellaris 32-bit MCUs combine
sophisticated, flexible mixed-signal
system-on-chip integration with
unparalleled real-time multitasking
capabilities. Complex applications
previously impossible with legacy
MCUs can now be accommodated
with ease by powerful, cost-effective
and simple-to-program Stellaris
MCUs. With more than 280 devices,
the Stellaris family offers the widest
selection of precisely compatible
MCUs in the industry.
The Stellaris family is positioned for
cost-conscious applications requiring
significant control processing and
connectivity capabilities, including
motion control, monitoring (remote,
fire/security, etc.), HVAC and
building controls, power and energy
monitoring and conversion, network
appliances and switches, factory
automation, electronic point-of-sale
machines, test and measurement
equipment, medical instrumentation,
and gaming equipment.
Why Choose Cortex-M?
Cortex-M is the MCU version of ARM’s V7
instruction set architecture family of cores:
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always 12 cycles, or just 6 cycles with
tail chaining
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for low power
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hardware divide
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instruction set
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ARM7 and ARM9
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data watchpoints and flash patching
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(MAC) instructions
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saturating arithmetic instructions
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precision floating point unit
In addition to MCUs configured for
general-purpose real-time systems,
the Stellaris family offers distinct
solutions for advanced motion control
and energy-conversion applications,
real-time networking and real-time
internetworking, and combinations
of these applications including
connected motion control and hard
real-time networking. Welcome to the
future of microcontrollers.
Why Choose the Stellaris
Family?
Designed for serious microcontroller
applications, the Stellaris family provides
the entry into the industry’s strongest
ecosystem, with code compatibility
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64%JOTZTUFNDPTU
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members to choose from
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interrupts, are 5-V-tolerant and have
programmable drive strength and
slew- rate control
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USB and USB OTG and CAN controllers
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hardware and software
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functionality provide on-chip system
options to balance hardware and
software performance
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royalty-free StellarisWare® Software
Embedded Processors
Embedded Processors
Get samples, data sheets, tools and app reports at: www.ti.com/stellaris
ARM Cortex-M3 MCU Evaluate with the fun EK-EVALBOT kit
Stellaris® family block diagram
ARM Cortex-M4F MCU Evaluate Cortex-M4 with floating point
with the EK-LM4F232 kit
www.eecatalog.com/dsp
31
TMS320C66x DSP Generation, Fixed- and Floating-Point
High Performance Multicore DSPs
Specifications
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and
C66x platforms
t *OEVTUSZTGJSTU(I[%41XJUI
(."$T('-01T
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point DSP
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multicore architecture
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tools & complier
Target Markets
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– Military & defense
– Public safety
– Satellite
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– Smart camera
– Currency counter
– Video analytics server
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– Counterfeit & verification
– Composition & purity
– Oil & gas
t $PNNVOJDBUJPOT/FUXPSLJOH
– Small cell base station
– Media gateway
– Session border controller
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– Cloud computing server
– Cloud RAN
– Thin client server
C66x KeyStone Features
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SoC architecture for highest
performance
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programming model support for ease
of use & performance
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network for quick development
32
Production
'VUVSF
Sampling
Development
C6670
Communications
Optimized
Multicore
General
Purpose
Multicore
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C6000 Multicore Roadmap
C64x & C66x multicore DSPs provide the highest performance solutions for various
market segments.
C6678 Processor Block Diagram
For developers of products in mission critical, medical imaging, test and automation and highperformance computing markets,TI’s TMS320C6672/74/78 (C667x) DSP family offers the industry’s
first 10-GHz DSP. Based on TI’s KeyStone multicore architecture, and integrated with the new and
innovative C66x DSP core, C6672/74/78 devices come with two, four or eight cores, respectively.
Embedded Processing & DSP Resource Guide 2013
Embedded Processors
Embedded Processors
Get samples, data sheets, tools and app reports at: www.ti.com/NVMUJDPSF
Hercules™ Safety Microcontrollers
Make the world safer with the new Hercules safety MCU platform
Key Applications
Industrial/medical applications
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t4BGFUZ1SPHSBNNBCMF-PHJD$POUSPMMFST
(PLCs)
t1PXFSHFOFSBUJPOBOEEJTUSJCVUJPO
t5VSCJOFTBOEXJOENJMMT
t7FOUJMBUPSTBOEEFGJCSJMMBUPST
t*OGVTJPOBOEJOTVMJOQVNQT
Embedded Processors
Embedded Processors
Get samples, data sheets, tools and app guides at: www.ti.com/IFSDVMFT
Transportation applications
t#SBLJOHTZTUFNT"#4BOE&4$
t&MFDUSJDQPXFSTUFFSJOH&14
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and signaling
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communication, parking assist
Key Features
RM4x Safety MCUs
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support
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– Ethernet, USB, CAN
– Dual Timer Co-processors with up
to 44 pins
– Dual12-bit analog/Digital Converters
– External memory interface
TMS570LS Safety MCUs
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– Dual Timer Co-processors with up
to 44 pins
– 12-bit analog/Digital Converters
– External memory interface
TMS470M Safety MCUs
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ECC protection and EEPROM emulation
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– 2 CAN, 2 MibSPIs, 2 LIN/UART
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– 10-bit analog/digital converter (16 ch)
– Safety features (ECC, BISTs, CRC)
– Pin and software compatible family
– Embedded debug module
www.eecatalog.com/dsp
Hercules RM4x and TMS570 Integrated Safety Features
33
DaVinci™ Video Processors: Optimized for Digital Video
Best-in-class video solution
Get samples, data sheets, tools and app reports at: www.ti.com/EBWJODJ
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up to 30 MTriangles/s
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video image coprocessing engines for
1080p/60
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enhanced MPEG/JPEG coprocessor
form
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Video encode/decode/transcode/transrate,
video security, video conferencing, video
infrastructure, media server, IP phone, thin
client and digital signage.
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DaVinci Roadmap
Key Peripherals
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ARM®
microprossor
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®
C674x
DSP Core
ARM
Cortex A8™
3D graphics
engine
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34
Resizer
Video I/O
Key Features
DM8168
On-screen
display
SD DAC HD DAC
(x3)
(x3)
DM8148
YQ
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Display
HD video
coprocessor
(x3)
HDMI PHY
HD video
I/O (x2)
Switched Central Resource (SCR)
Peripherals
PCIe
2 lanes
McASP x3
SPDIF
McBSP
I2C x2
UART x3
SPI
USB 2.0
x2
GPIO
GMII
EMAC x2
Memory interfaces
DDR3 x2
SDIO/IO
Async
EMIF/NAND
SATA2
x2
TMS320DM816x SoC Block Diagram
The high-performance DM8168 DaVinci video processor offers 3x the video streaming capability
over competing solutions enabling customers to build video-centric systems that
capture, encode, decode and analyze multiple video streams simultaneously on up to three
independent displays.
Embedded Processing & DSP Resource Guide 2013
Embedded Processors
Embedded Processors
Specifications
Kentec Display
2, Interface,
two interface options available for customer selection
Interface Option 1.
For EK-LM4F232
1 EB-LM4F232/LM4F120-LCD Overview
The EB-LM4F232/LM4F120-LCD is an extension board
for the EK-LM4F232 Development Board and Stellaris®
LaunchPad (see Figure 1).
Figure 1. LCD expansion board for EK-LM4F232 and
Stellaris® LaunchPad
The expansion board has build in LED backlight driver
circuit and 60pin FPC connector for the following Kentec
TFT LCD modules
P1 Pin
1
2
3
4
5
6
7
P2 Pin
1
2
3
4
5
Symbol
LCD_D17
LCD_D16
LCD_D15
LCD_D14
LCD_D13
LCD_D12
LCD_D11
Symbol
LCD_D10
GND
LCD_CS
LCD_RST
LCD_RS
EK-LM4F232
PJ7
PJ6
PJ5
PJ4
PJ3
PJ2
PJ1
EK-LM4F232
PJ0
GND
PL5
PL4
PL3
Description
Data bit 17 for LCD
Data bit 16 for LCD
Data bit 15 for LCD
Data bit 14 for LCD
Data bit 13 for LCD
Data bit 12 for LCD
Data bit 11 for LCD
Description
Data bit 10 for LCD
Ground (0V)
Chip select signal for LCD
Reset input for LCD
Register/Data select
signal for LCD
6
LCD_RD
PL2
Read control signal for LCD
7
LCD_WR
PL1
Write control signal for LCD
8
NC
PL0
No connection
9
GND
GND
Ground (0V)
10
TOUCH_YN
PK7
4-wire resistor touch screen
terminal
11
TOUCH_XN
PK6
12
NC
PK5
No connection
13
NC
PK4
No connection
14
3.3V
3.3V
Power supply (3.3V)
P3 Pin
Symbol
EK-LM4F232
Description
1
GND
GND
Ground (0V)
2-9
NC
PF0 - PF7 No connection
10
GND
GND
Ground (0V)
11
LCD_BL
PG3
LCD backlight control signal
12-13
NC
PG6 - PG7 No connection
14
GND
GND
Ground (0V)
15-18
NC
PH0 - PH3 No connection
19
GND
GND
Ground (0V)
20
TOUCH_XP
PK3
4-wire resistor touch screen
terminal
21
TOUCH_YP
PK2
22-23
NC
PK1 - PK0 No connection
24
GND
GND
Ground (0V)
25-26
NC
PA6 – PA7 No connection
27
3.3V
3.3V
Power supply (3.3V)
- 3.2” QVGA TFT module: K320QVG-V1-F;
- 3.5” QVGA TFT module: K350QVG-V2-F;
- 4.3” 480*272dots TFT module: K430WQC-V3-FF;
Interface Option 2. For
Stellaris® LaunchPad
J1 Pin
Symbol
LaunchPad
1
3V3
+3.3V
2
LCD_D5
PB5
Data bit 5 for LCD
3
Description
Power supply
LCD_D0
PB0
Data bit 0 for LCD
4
LCD_D1
PB1
Data bit 1 for LCD
5
TOUCH_XP
PE4
6
TOUCH_YP
PE5
4-wire resistor touch screen
terminal
7
LCD_D4
8
LCD_WR
PA5
9
LCD_RS
PA6
Register/Data select for LCD
10
LCD_CS
PA7
Chip select for LCD
J2 Pin
PB4
Data bit 4 for LCD
Write control signal for LCD
Symbol
LaunchPad
1
GND
GND
Ground
2
LCD_D2
PB2
Data bit 2 for LCD
PE0
No connection
3
NC
Description
4
NC
PF0
5
RESET
RST
Reset signal for LCD/MCU
6
LCD_D7
PB7
Data bit 7 for LCD
7
LCD_D6
PB6
Data bit 6 for LCD
LCD_RD
8
Daughter Cards
Daughter Cards
LM4F232/LM4F120 LCD
Interface Expansion Board
(Stellaris Boosterpack)
No connection
PA4
Read control signal for LCD
9
TOUCH_XN
PA3
10
TOUCH_YN
PA2
4-wire resistor touch screen
terminal
J3 Pin
Symbol
LaunchPad
1
5V0
VBUS
2
GND
GND
Ground
3
NC
PD0
No connection
4
NC
PD1
No connection
5
NC
PD2
No connection
6
NC
PD3
No connection
7
NC
PE1
No connection
8
NC
PE2
No connection
9
NC
PE3
No connection
No connection
Description
Power supply
10
NC
PF1
J4 Pin
Symbol
LaunchPad
1
LCD_BL
PF2
2
NC
PF3
LCD backlight ON/OFF
control
No connection
3
LCD_D3
PB3
Data bit 3 for LCD
4
NC
PC4
No connection
5
NC
PC5
No connection
6
NC
PC6
No connection
7
NC
PC7
No connection
8
NC
PD6
No connection
9
NC
PD7
No connection
10
NC
PF4
No connection
Description
- 5.0” WVGA TFT module: K50DWN2-V1-FF;
3 LCD driver code examples
- 7.0” WVGA TFT module: K70DWN2-V1-FF;
h t t p: // w w w. ke n t e c d i s p l a y. c o m / D o w n l o a d s / Ke n tec320x240x16_ssd2119_8bit.c
- 9.0” WVGA TFT module: K90DWN2-V1-FF.
The above TFT modules are also compatible to TI Cortex
M3 development kits
- DK-LM3S9D96
- RDK-IDM-L35
- RDK-IDM-SBC
CONTACT INFORMATION
Kentec Display
(852)95121814 Telephone
[email protected]
http://www.kentecdisplay.com
XXXFFDBUBMPHDPNETQ
%FWFMPQNFOU5PPMTt
Link Research
Supported TI Processors: F28x Delfino™ floating-point MCUs,
F28x Fixed-point Series
Daughter Cards
Daughter Cards
Multi-channel Data Acquisition
daughtercard for the F2812/
F28335 eZdsp™ Development Kit
The Link Research models LR-F2812DAQ and LRF28335DAQ daughtercards plug directly into the F2812
and F28335 eZdsp™ development kits respectively.
The daughtercards feature up to 16 channels of 14-bit,
simultaneous sampling A/Ds, and up to 16 channels of
simultaneous updating D/As. All analog I/O channels feature a full ±10 volt I/O range. A/D sampling rates of up to
350kHz on a single channel, or 100 kHz with all channels
operating are possible.
The standard version of the daughtercard includes an
RS-232 interface with a maximum data rate of 921.6 kbps,
eight digital I/Os, two user LEDs and a Hitachi 44780
compatible LCD display interface (F2812 version only).
Also available as optional interfaces are a fiber optic
serial communications interface allowing true galvanic
isolation between the daughtercard and the PC, and an
802.3 compatible Ethernet interface.
TECHNICAL SPECS
◆ Analog Input Range: ±10 volts.
◆ A/D Channels: Three versions having 4, 8, or 16,
14-bit converters with simultaneous sampling.
The daughtercard ships with everything needed to get
up and running fast, including a ±15 volt analog power
pack, a 6 foot RS-232 cable, an extra set of connectors to
be soldered into the eZdsp development kit, and framework software and documentation on CD.
◆ D/A Channels: Two versions having 8 or 16, 14-bit
FEATURES & BENEFITS
AVAILABILITY
◆ Adds high precision, multi-channel data conversion
In production since 2006
◆
◆
◆
◆
capability to the F2812 or F28335 eZdsp development kit
Includes complete CCS projects demonstrating both
DSP/BIOS™ software kernel foundation as well as
non-BIOS applications
Optional Ethernet interface includes software demonstrating a web browser JAVA applet model for
accessing development system data.
Achieve a maximum of 16 A/D and 16 D/A channels
by stacking a second daughtercard (model LRF2812DAQ8X8/LR-F28335DAQ8X8)
These daughtercards are also available bundled with
a Spectrum Digital eZdsp development system
converters with simultaneous updating.
◆ Sampling Rate: 350 kbps using one channel, 100
kbps per channel using all channels.
◆ RS-232 Interface: Operates up to 921.6 kbps
APPLICATION AREAS
Power Supply Design, Power Factor Correction, Three
Phase Power Inverters, Motor Control, Uninterruptible
Power Supply.
CONTACT INFORMATION
Link Research
131 Fairview Street
Providence, RI 02908
USA
401-270-4445 Telephone
401-270-5221 Fax
[email protected]
www.link-research.com
t%FWFMPQNFOU5PPMT
Embedded Processing & DSP Resource Guide 2013
Xilinx
Xilinx® FPGAs exceed the computing power of DSPs with
their inherent parallelism and offer co-processing methods
of performance acceleration for signal processing. The
Xilinx Spartan®-6 FPGA DSP Kit integrates hardware, IP,
software development tools and methodologies together
into solutions that accelerate development for experienced
users and simplify the adoption of FPGAs for new users.
With the addition of targeted reference designs, these
DSP platforms enable users to focus on creating their
own unique differentiation from the very beginning of the
product development process.
This kit includes the Xilinx Spartan-6 LX150T board and
allows users to quickly learn the different tool flows and
design techniques involved in creating DSP centric designs
with the Spartan-6 FPGA family. Traditional RTL design
methodologies are also supported through a design implementation that uses ISE Design Suite: Logic Edition and
LogicCore DSP IP.
FEATURES & BENEFITS
◆ Xilinx Spartan-6 LX150T board
◆ Cables, Power Supply and Compact Flash
◆ Xilinx ISE® Design Suite – System Edition Software
◆
◆
◆
◆
(device locked to Spartan-6 LX150T)
Includes EDK and System Generator™ for DSP
The MathWorks Simulink® evaluation tools
DSP reference design tutorials
Kit documentation
Development Boards
Development Boards
Avnet Spartan-6 FPGA DSP Kit
CONTACT INFORMATION
Xilinx
2100 Logic Drive
San Jose, CA 95124
408-559-7778 Telephone
[email protected]
http://www.xilinx.com/products/
boards_kits/dsp.htm
Xilinx
Avnet TI OMAP™ Processor /
Spartan-6 FPGA Co-Processing Kit
FPGAs can be used to accelerate traditional processor/
DSP systems up to 15X. Conventional system design
methods, however, are insufficient to meet the requirements of today’s ultra-high performance applications.
The inherent parallel nature and optimized DSP blocks in
an FPGA enable intelligent “co-processing” execution of
massive signal processing computations that accelerate
your system to optimally meet your most demanding
performance requirements.
The TI OMAP™ processor/Spartan®-6 FPGA Co-Processing
Development Kit is a sophisticated platform that delivers
breakthrough system performance by integrating and
optimizing the key strengths of high performance FPGAs,
system control processing, and digital signal processing,
all within one single environment. While an ARM9 CPU
provides run control and executes Real Time Operating
Systems like embedded Linux, and a C674X DSP can be
dedicated to specific signal processing algorithms, a flexible Spartan-6 FPGA can be focused on the performance
bottlenecks to accelerate data path applications.
XXXFFDBUBMPHDPNETQ
FEATURES & BENEFITS
◆ Avnet Spartan-6 Development Board including
Spartan-6 LX45T FPGA
◆ Cables, power supply and compact flash
◆ ISE® Design Suite: System Edition (Device-locked to
the Spartan-6 LX45T FPGA)
◆ Texas Instruments Code Composer Studio™ inte-
grated development environment
◆ MathWorks® MATLAB – evaluation version
◆ Kit documentation
CONTACT INFORMATION
Xilinx
2100 Logic Drive
San Jose, CA 95124
408-559-7778 Telephone
[email protected]
http://www.xilinx.com/products/
boards_kits/dsp.htm
%FWFMPQNFOU5PPMTt
D.SignT GmbH & Co. KG
Development Boards/EVMs
Development Boards/EVMs
D.Module2 High-Performance
DSP Processor and I/O Boards
Supported TI Processors: DM64x, C674x Low Power DSP, C67x
DSP, C66x DSPs, C665x Multicore DSPs
The D.Module2 family of DSP and I/O boards make up
a highly integrated and scalable stand-alone signal
processing platform. With a small form factor, modular
design, and stacking capability, these boards are ideally
suited as the heart of your industrial control, material
inspection, imaging, or test & measurement application.
Versatile communication and expansion interfaces ease
system integration. Built-in tools for in-field updates of programs, parameters, and reconfiguration address the needs
of maintenance-friendly installations. The D.Module2.BIOS
is a system-resident set of functions which encapsulates
hardware dependencies, handles initialization and configuration, and provides a consistent programming interface
throughout the entire board family. This concept assures
long-term availability and compatibility.
◆ D.Module2.C6747: floating-point DSP, 1800 MFLOPS
FEATURES & BENEFITS
peak. Interfaces: PWM, Capture/Compare, Quadrature
Encoder, Memory Card, Real-Time Clock, USB Host.
Applications: Industrial Control and Automation.
◆ D.Module2.C6657: ultra-high performance 2-core DSP,
1.25GHz. UPP Interface for high-speed ADC/DACs.
PCIe, SRIO, Gigabit-Ethernet. Applications: Material
Inspection, Machine Vision, Medical Imaging.
◆ D.Module2.ADDA500K16: six analog inputs, two
analog outputs, 16 bit resolution, 500KHz sampling,
calibration. ADC8556 and DAC8822 converters.
◆ D.Module2.6SLX45T: Xilinx Spartan-6 FPGA daughter card
for high-speed data acquisition and preprocessing. I/O
compatible with FMC standard, FMC base board available.
◆ Stackable small-sized boards (87x59mm), industry-
AVAILABILITY
The D.Module2 family features various DSP boards
(DM642, C6747, and - coming soon - C6657). Common to
all DSP boards are processor, power supply, DRAM and
non-volatile memories, USB, Ethernet, RS232/485, GPIO,
synchronous serial ports, and a parallel external bus
interface. Processor and board-specific peripherals are
brought out on a separate expansion connector. These
DSP boards are accompanied by data acquisition peripherals, an FPGA board (Xilinx Spartan 6), and base boards
for prototyping and evaluation.
◆
◆
◆
◆
standard IEEE1386 high density connectors, 3.3V
single supply, 3.3V IO
On-board memory expansion: DRAM and non-volatile
Flash Memory
Communication Interfaces: USB, Ethernet, UART
(RS232/RS485), SPI, I2C, GPIO
External Parallel Bus Interface and Synchronous Serial
Ports to connect data acquisition peripherals and/or
FPGAs
D.Module2.BIOS system-resident programming support
functions, Utilities for in-field updates via USB and UART
TECHNICAL SPECS
◆ D.Module2.DM642: high performance fixed-point DSP
board, 5760 MIPS peak. Three Video Capture/Display
Ports with FIFO’s. Applications: Ultrasonics, Surveillance,
Video, Biometrics, Machine Vision.
t%FWFMPQNFOU5PPMT
D.Module2.C6657: end 2012, all others in full production.
APPLICATION AREAS
Audio, Broadband, Communications & Telecom, Industrial,
Medical, Security, Video, Wireless
CONTACT INFORMATION
D.SignT GmbH & Co. KG
Marktstr. 10
Kerken, 47647
Germany
+49 2833 570977 Telephone
+49 2833 3328 Fax
[email protected]
www.dsignt.de
Embedded Processing & DSP Resource Guide 2013
Traquair Data Systems, Inc.
Development Boards / EVMs
Development Boards / EVMs
micro-line TMS320C641x-based
Integer DSP/FPGA Boards
Supported TI Processors: C6410/12/13/18
The micro-line series of embedded DSP/FPGA boards
provides embedded systems developers with a tightly
integrated suite of programmable DSP, FPGA and I/O
resources in small, stand-alone-capable board formats.
micro-line C6412Compact and C641xCPU DSP/FPGA boards
target high-performance integer DSP applications using
Texas Instruments TMS320C6410/6412/6413/6418 DSPs.
The C6412Compact combines Texas Instruments’
powerful 720-MHz TMS320C6412 DSP, up to 128-MB
SDRAM, 8- or 32-MB boot program ROM and a highdensity 1-MGate or 4-MGate Xilinx® Spartan®-3 FPGA.
The optionally programmable FPGA greatly expands
processing and interfacing options. Two independent
400-Mbps 1394a FireWire interfaces are included,
enabling simultaneous high-bandwidth video-in/out
for completely integrated video processing. A 64-bit
bus connects the DSP, FPGA, SDRAM and FireWire
resources. On-board USB 2.0 and 10/100BaseTx Ethernet
interfaces round off the impressive array of features.
The C641xCPU family of boards features a smaller
(98-mm x 67-mm footprint) and leaner configuration,
with up to 64-MB SDRAM, 8-MB boot program ROM,
and a high-density 500-KGate, 1-MGate, or 1.6-MGate
Spartan-3E FPGA.
Analog I/O daughtercards can also be combined with
these boards:
• ORS-112 (16-bit A/D/A)
• 4-ch A/D 2.5 MSPS; 4-ch D/A 625 KSPS
• ORS-114 (14-bit A/D/A)
• 2-ch A/D 65 MSPS; 2-ch D/A 125 MSPS
• ORS-116 (16-bit A/D/A)
• 12-ch A/D 250 KSPS; 12-ch D/A 100 KSPS
TECHNICAL SPECS
◆ C6412Compact
• 720-MHz TI TMS320C6412-based integer DSP board
• 1-MGate or 4-MGate Spartan-3 FPGA
• Up to 128-MB SDRAM; up to 32-MB boot program
ROM
• Two independent IEEE1394a FireWire interfaces
for streaming data in/out simultaneously
• 10/100BaseTx Ethernet, USB 2.0 and RS-232 interfaces; 16-/32-bit host port interface
AVAILABILITY
In production since 2006
APPLICATION AREAS
Audio, Automotive, Broadband, Communications &
Telecom, Industrial, Medical, Military, Security, Video
and Imaging, Wireless
FEATURES & BENEFITS
◆ Small form factor, embeddable DSP/FPGA boards for
OEM applications
◆ Suitable for product development and volume production
◆ User-programmable DSP, optionally programmable FPGA
◆ Extensive connectivity options via DSP, FPGA,
FireWire, USB, Ethernet, RS-232
◆ Optional A/D/A
www.eecatalog.com/dsp
Contact Information
Traquair Data Systems, Inc.
114 Sheldon Road
Ithaca, NY 14850
USA
607.266.6000 Telephone
607.266.8221 Fax
[email protected]
www.traquair.com
Development Tools • 39
Traquair Data Systems, Inc.
Development Boards / EVMs
Development Boards / EVMs
micro-line TMS320C6713 DSP-based
Floating-Point DSP/FPGA Boards
Supported TI Processors: C67x DSPs
The micro-line series of embedded DSP/FPGA boards
provides embedded systems developers with a tightly
integrated suite of programmable DSP, FPGA and I/O
resources in small, stand-alone capable board formats.
micro-line C6713Compact and C6713CPU DSP/FPGA
boards target high-performance floating-point DSP
applications using the powerful Texas Instruments
TMS320C6713 DSP.
The C6713Compact incorporates up to 128-MB SDRAM,
8-MB boot program ROM and an on-board, high-density
Xilinx® Spartan®-6 LX or Virtex-II FPGA (optionally programmable). The FPGA greatly expands processing and
hardware interfacing options. An on-board 400-Mbps
IEEE 1394a FireWire interface allows for communications with other embedded DSP resources, cameras,
sensors and PCs. Software APIs are available to utilize
the FireWire interface for general purposes, video frame
capture from cameras, and data storage to hard drives
and CompactFlash memory.
The C6713CPU offers a smaller (98-mm x 67-mm footprint) and leaner configuration, with up to 64-MB SDRAM,
2-MB boot program ROM and a high-density 400-kGate or
1-MGate Xilinx Spartan-3 FPGA.
Analog I/O daughtercards can also be combined with
these boards:
• ORS-112 (16-bit A/D/A)
• 4-ch A/D 2.5 MSPS; 4-ch D/A 625 KSPS
• ORS-114 (14-bit A/D/A)
• 2-ch A/D 65 MSPS; 2-ch D/A 125 MSPS
• ORS-116 (16-bit A/D/A)
• 12-ch A/D 250 KSPS; 12-ch D/A 100 KSPS
FEATURES & BENEFITS
TECHNICAL SPECS
◆ C6713Compact
• 300-MHz floating-point TMS320C6713 DSP
• Spartan-6 (LX45, LX75, LX100, or LX150) or VirtexII (250-kGate, 500kGate, or 1MGate) FPGA; up to
160 configurable digital I/O pins
• On-board 400-Mbps IEEE1394a FireWire interface;
RS-232 interface also included
• External access to TMS320C6713 DSP I/O interfaces:
32-bit EMIF, XF0/1 pins, timer input/output pins,
McASP and McBSP ports, I²C, and Host Port Interface
• 67-mm x 120-mm footprint; ISO9001:2000 accredited production and CE certification
AVAILABILITY
C6713Compact with Spartan-6 LX FPGA: 2012; others in
production since 2003
APPLICATION AREAS
Audio, Automotive, Broadband, Communications &
Telecom, Industrial, Medical, Military, Security, Video
and Imaging, Wireless
◆ Small form factor, embeddable DSP/FPGA boards for
OEM applications
◆ Suitable for product development and volume production
◆ User-programmable DSP, optionally programmable FPGA
◆ Extensive connectivity options via DSP, FPGA,
FireWire, RS-232
◆ Optional A/D/A
40 • Development Tools
Contact Information
Traquair Data Systems, Inc.
114 Sheldon Road
Ithaca, NY 14850
USA
607.266.6000 Telephone
607.266.8221 Fax
[email protected]
www.traquair.com
Embedded Processing & DSP Resource Guide 2013
Xilinx
Development Boards/EVMs
Development Boards/EVMs
Avnet Kintex-7 FPGA DSP Kit
with High-Speed Analog
The Kintex™-7 FPGA DSP Kit with high-speed analog
brings digital and analog hardware, development
tools, high-level design methodologies, IP, and verified reference designs together into a development
platform that accelerates development of DSP applications for experienced users and simplifies the
adoption of FPGAs for DSP for new users. By combining all the elements of a total solution, users can
focus on the unique value of a design at the beginning
of the design process.
Standard with every kit, the Kintex-7 FPGA DSP Targeted Reference Design includes a DSP datapath
connected to a high-speed analog interface in a loop
back configuration. Xilinx DSP IP is used to create
digital filters used for digital up / down conversion to
the interface. The design is tuned for maximum performance from the Kintex-7 FPGA programmable logic
and the analog interface. Key features of the Kintex-7
FPGA DSP Targeted Reference Design include:
• Xilinx FIR Compiler
• Mux isolation of both the analog and digital
logic for debug
• Selectable sine wave or impulse pattern generation
• Dynamic updates to the data converter configuration registers from the FPGA using
ChipScope™ VIO AXI4 Streaming interface
FEATURES & BENEFITS
◆ KC705 XC7K325T-2FFG900C Evaluation Board
◆ 4DSP FMC150 Dual 14-bit 250 Msps A/D, Dual 16-bit
800Msps D/A
◆Full seat ISE® Design Suite: System Edition
• Device locked to the Kintex-7 XC7K325T FPGA
◆Reference Designs, Example Designs, and Demos
◆Board Design Files
◆Documentation including Step-by-Step Getting
Started Guide
◆ Cables & Power Supply
AVAILABILITY
Available now at www.xilinx.com/products/boards-and-kits
Contact Information
Xilinx
2100 Logic Drive
San Jose, CA 95124
408-559-7778 Telephone
[email protected]
http://www.xilinx.com/products/
boards_kits/dsp.htm
www.eecatalog.com/dsp
Development Tools • 41
Signum Systems
Signum Systems JTAGjet™ line of In-Circuit Debuggers
(emulators) cover the entire line of TI DSP, OMAP™,
Sitara™ and DaVinci™ processors as well as other ARM®
platform-based devices. We offer many preconfigured
models or you can create your own, custom emulator. If
you need more options later, no problem – most can be
emailed to you whenever they are needed. This unusual
flexibility protects your investment in embedded tools
and simplifies the debugging process. And YES, you can
use almost any ARM C/C++ compiler with JTAGjet: Code
Composer Studio™ integrated development environment (IDE), IAR Embedded Workbench® for ARM, ARM
RealView, MetroWerks, GDB, Eclipse, Keil™, Mentor
Graphics® and others. JTAGjet is fully compatible with
TI Code Composer Studio IDE (ARM® & DSP) and IAR
Systems C-SPY® (ARM) debuggers and most models
come with Chameleon Debugger for ARM capable of
embedded Linux debugging.
Contact Information
IAR SYSTEMS® INC.
1065 E. Hillsdale Blvd., #420
Foster City, CA 94404
650-287-4250
[email protected]
www.signum.com
42 • Development Tools
Embedded Processing & DSP Resource Guide 2013
Development Tools
Development Tools
Signum Systems Emulators for TI DSPs,
OMAP™ and DaVinci™ Processors
Sundance Digital Signal Processing Inc
Supported TI Processors: DaVinci™ DM64x, DaVinci DM81x, DaVinci
DM64x, DaVinci DM37x, DaVinci DM3x, DM81x Video SoC, DM64x Video
SoC, DM646x, DM644x, DM643x, DM64x, DM37x, DM3x, DM814x,
DM816x, OMAP35x, OMAP3525/30 SoC, TMS320DM37x SoC, TMS320DM3x Video SoC, OMAPL1x, C67x DSP, C66x, C64x, C62x DSP, C647x
Multicore, C645x Multicore, C667x Multicore, C665x Multicore, AM35x/
AM37x ARM® Cortex™-A8, AM18x ARM9, AM17x ARM9
arithmetic on the C67x and simulation for TMS320C6000™
DSPs. It can processes real & complex data vectors and matrices.
TECHNICAL SPECS
◆ All libraries are algorithmically optimized and some are
GDD0300 library functions perform operations like FFT, Fast
Hartley Transform, Discrete Cosine Transform, FIR/IIR filters,
vector operations, complex-number arithmetic, and more.
GDD7000 LINPACK library solves systems of simultaneous
equations for many applications like radar and Telecom. It
can handle a wide variety of matrices including triangular,
band, Hermitian and Toeplitz.
even hand-coded
◆ Functions within GDD libraries are interruptible and give
Development Tools
Development Tools
Hand-coded, Optimized DSP/Vector,
LINPACK, EISPACK, and CBLAS Libraries
additional control to time-critical
applications
◆ GDD Libraries help reduce
application time to market
CONTACT INFORMATION
Sundance Digital Signal
Processing Inc
4790 Cauhghlin pkwy #233
Reno, NV 89519
USA
+1 775 8273103 Tel, West Coast
+1 514 684 0130 Tel, East Coast
[email protected]
www.sundancedsp.com
GDD8000 ECC EISPACK library functions solve linear algebraic eigen systems with various matrices, real or complex,
general, band, symmetric or Hermitian. Several types of
matrix decompositions like SVD or QR are performed.
The GDD9000 CBLAS 123 functions perform operations on
IEEE-754 SP and DP floating-point numbers. It uses native FP
Embedded Processing & DSP ONLINE
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Blackhawk
Blackhawk is a recognized leader in providing advanced
JTAG Emulators for Texas Instruments DSPs and the
first company to develop a USB JTAG Emulator for TI
TMS320™ DSPs. Our XDS510™-class emulators & controllers provide a full range of features and benefits with
support for a wide-range of TI DSPs. Blackhawk XDS510class JTAG Emulators & Controllers are also compatible
with Code Composer Studio™ Flash-burner utility.
Feature Set of All Emulators
t #VTQPXFSFEWJB64#DBCMF
t #J$PMPS4UBUVT-&%SFEHSFFO
t 'VMM$PEF$PNQPTFS4UVEJP*%&DPNQBUJCJMJUZ
t 8JOEPXT¥1MVHO1MBZ*OTUBMMBUJPO
t %SJWFSTBSFQSPWJEFEGPS-JOVYBOE8JOEPXT¥
including 64-bit support
t "MMESJWFSVQEBUFTBSFBWBJMBCMFGPSEPXOMPBEGSFF
of-charge from our website
t $PNQBUJCJMJUZXJUIUIF$PEF$PNQPTFS4UVEJP*%&
Flashburn plugin and Blackhawk FlashBurn Utility
add-on
t 'SFFUFDIOJDBMTVQQPSUBOEXFCEPXOMPBET
t 0OF:FBS8BSSBOUZ
t "VUPTFOTJOHMPX*0WPMUBHFTVQQPSU
1.8v/3.3v/5.0v
t 'VMMZBTTFNCMFEBOEUFTUFEJOUIF64
t 3P)4$PNQMJBOU
t 5*QJO5BSHFU$POOFDUJPOD5*QJOGPS
USB510W)
t 0QUJPOBM*TPMBUJPO"EBQUFS"WBJMBCMF
t $PEF$PNQPTFS4UVEJP*%&WWYWYBOEMBUFS
USB510L Features
t "GGPSEBCMF9%4FNVMBUPSDMBTT$POUSPMMFS
t 4VQQPSUT5*5.4™%JHJUBM4JHOBM1SPDFTTPST
t )JHIQFSGPSNBODFCJU$™DPOUSPMMFST.$6T
t $™VMUSBMPXQPXFSQSPDFTTPST
t $™ýPBUJOHQPJOU%41T
t $™QSPDFTTPSTIJHIQFSGPSNBODF%41T
t $™QSPDFTTPSTIJHIQFSGPSNBODFNVMUJ
core DSPs)
t %B7JODJ™WJEFP1SPDFTTPST
t 5.4"3.¥QSPDFTTPST
t 5.4-4"3.¥$PSUFY™3CBTFE.$6T
t CJU4UFMMBSJT¥"3.$PSUFY.CBTFE.$6T
t 4JUBSB™GBNJMZPG"3.$PSUFY""3.™
t 0."1™QSPDFTTPST
t *OUFHSB™%41"3.QSPDFTTPST
USB510W Features
t "MMUIFGFBUVSFTPGUIF64# t *OUFHSBUFE*&&&¥5SBOTDFJWFS
t%FWFMPQNFOU5PPMT
Emulators/Analyzers
Emulators/Analyzers
Advanced JTAG XDS510 Emulators
t #J$PMPS8JSFMFTT4UBUVT-&%SFEHSFFO
t &YUFSOBM1PXFS4VQQMZGPSTUBOEBMPOF8J'JVTF
t 1JO$POWFSUFST
GPS5*QJOBOE"3.QJO
USB2000 Features
t 4VQFS-PX$PTU9%4FNVMBUPSDMBTT$POUSPMMFS
t 4VQQPSUT5*$.$6T
t 'Y'Y'Y
t 'YY
t -'Y
t $PEF$PNQPTFS4UVEJP*%&W43PSMBUFS
AVAILABILITY
All Blackhawk Emulators are available for immediate
delivery from a world wide network of industry resellers
and distributors. Please visit www.blackhawk-dsp.com
for a complete list.
APPLICATION AREAS
Audio, Automotive, Communications, Military, Telecom,
Telecom Infrastructure, Telephony,
Video Conferencing, Video Security, Video and Imaging, Wireless.
CONTACT INFORMATION
Blackhawk
123 Gaither Drive
Mt. Laurel, NJ 08054
USA
856-234-2629 Telephone
856-866-1100 Fax
[email protected]
http://www.blackhawk-dsp.com
Embedded Processing & DSP Resource Guide 2013
Blackhawk
XDS560v2BP
XDS560v2PoE
USB560m
USB560bp
LAN560
PCI560
USB510W
USB510
USB510L
USB2000
USB100v2D
USB100v2ARM
System Trace
c-JTAG (IEEE 1149.7)
BHFlashburn
Boundary Scan
USB (bus-powered)
USB560v2
Model Highlight Indicates a
Blackhawk Unique Feature.
Yes
Yes
Yes
-
-
-
-
-
-
-
-
-
-
Yes
Yes
Yes
-
-
-
-
-
-
-
-
-
-
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
-
-
Yes
Yes
Yes
Yes
Yes
Yes
Yes
-
-
-
-
-
-
Yes
Yes
Yes
-
Yes
-
-
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
-
Yes
Yes
Yes
Yes
Yes
Yes
-
Yes
Yes
-
-
Yes
-
-
-
-
-
-
-
-
-
-
-
-
-
-
Yes
-
-
-
-
-
-
-
-
-
-
-
Yes
-
-
-
-
-
-
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
-
-
-
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
-
-
-
Yes
Yes
Yes
Yes
-
Yes
-
-
-
-
Host Interface
USB
Ethernet-Wired
Ethernet-Wireless
PCI
Code Composer Studio™
(CCS) IDE Support
CCS v5.x
CCS v4.x
CCS v3.3/v3.2/v3.1
CCS v3.0/v2.2
Device Support
TMS320C24xx
TMS320C28xx
TMS320C54xx
TMS320C55xx
TMS320C6xxx
TMS320C64xx
TMS320C64+
TMS320C66xx
TMS470 ARM7/9/11®
Stellaris® ARM® Cortex™
MCUs
OMAP™ processors
Integra™ DSP+ARM/Sitara™
ARM® processors
DaVinci™ processors
OS Support
Windows 2000/XP/XP64
Windows Vista/7 (32/64bit)
Linux (32/64 bit)
I/O Voltage Support
1.8v/3.3v
5.0v
Target Connections
MIPI 60
TI 60 (trace)
TI 14
cTI 20
ARM 20
ARM 10
-
-
-
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
-
-
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
-
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
-
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
-
C674x
C674x
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
-
-
-
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
-
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
-
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
-
ARM9
ARM9
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
-
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
-
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
-
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
-
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
-
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
-
-
-
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
-
-
Yes
Yes
Yes
-
-
-
-
-
-
-
-
-
-
option
Yes
Yes
Yes
Yes
Yes
Yes
option
option
option
option
option
-
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
-
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
option
option
option
Yes
-
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
-
-
-
option
Yes
-
-
-
-
-
-
-
-
-
-
-
-
Yes
Blackhawk offers a complete line of JTAG Emulator for
TI Embedded Processors including features not found
on other similar products. Contact Blackhawk for any
feature or emulator model not listed.
XXXFFDBUBMPHDPNETQ
Emulators/Analyzers
Emulators/Analyzers
Blackhawk Emulator Product Matrix
CONTACT INFORMATION
Blackhawk
123 Gaither Drive
Mt. Laurel, NJ 08054
USA
856-234-2629 Telephone
856-866-1100 Fax
[email protected]
http://www.blackhawk-dsp.com
%FWFMPQNFOU5PPMTt
Blackhawk
The Blackhawk XDS560-class emulators are the standard
of high-performance debugging of TI embedded processors and each includes support for the Code Composer
Studio™ integrated development environment (IDE) v3.3
and later plus the ability to collect system trace data (read
below). These emulator models are a great value with new
reduced pricing and continue to offer up-to-date features.
Feature Set of All Blackhawk 560 Emulators
t 4VQQPSUGPS$PSFMJT4DBO&YQSFTT1SPHSBNNFSBOE
Scan Express Jet Boundary Scan tools
t 4VQQPSUGPS5.4™5.4™"3.¥QSPDFTsors) and OMAP™ processor families including the
DaVinci™ platform
t )JHITQFFE35%9™UFDIOPMPHZXJUIEBUBSBUFTPG
over 2 MB/sec
t *ODMVEFT9%43FWJTJPO%DBCMFFMFDUSPOJDTBOEGFBtures with 20-pin cTI JTAG Header (SYSRESET signal)
t *ODMVEFTQJOD5*UPQJOBEBQUFSGPSCPBSET
using standard 2x7 target header
t "VUPTFOTJOHMPX*0WPMUBHFTVQQPSUEPXOUPW
t 3FBMUJNFOPOJOUSVTJWF"EWBODFE&WFOU5SJHHFSJOH
(AET) capability
t $PEF$PNQPTFS4UVEJP*%&DPNQBUJCJMJUZGPSW
and later
t 8JOEPXT¥1MVHO1MBZ*OTUBMMBUJPO
t 8JOEPXT917JTUB4VQQPSUBOECJUFEJUJPOT
t -*/69TVQQPSUVOEFS$$4UVEJPWBOECJU
editions) *PCI560 excluded
t "MMESJWFSVQEBUFTBSFBWBJMBCMFGPSEPXOMPBEGSFF
of-charge from our website
t $PNQBUJCJMJUZXJUIUIF$PEF$PNQPTFS4UVEJP*%&
Flash-burner utility
t 6QUPUJNFTGBTUFSUIBO9%4™FNVMBUPST
USB560M Features
t $PNQBDUQPEXJUIQPXFSBOE64#TUBUVTJOEJDBUPS
LED’s
t )JHITQFFE64#.CJUTTFD
QPSU
t 'MFYJCMFJODIIJHITQFFENJDSPDPBY+5"(DBCMF
with 20-pin cTI (Compact TI) header
t *ODMVEFT
QJODPOWFSUFSTGPS5*QJO
20-pin(ARM®-based platforms) and TI 60-pin
(Trace) target headers
LAN560 Features
The LAN560 includes all the features of the USB560m, plus…
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gateway address
t%FWFMPQNFOU5PPMT
PCI560 Features
t 6MUSBDPNQBDUIBMGIFJHIUBOEIBMGMFOHUIGPSNGBDUPS
t 'MFYJCMF›GPPUIJHITQFFENJDSPDPBY+5"(
cable with 20-pin cTI (Compact TI) header
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BOETUBOEBSE
height bracket
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20-pin(ARM-based platform) and TI 60-pin (Trace)
target headers
USB560 BP Features
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QPE
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QPSU
t *ODMVEFTBQJODPOWFSUFSTGPS5*QJOUBSHFUIFBEFST
System Trace (STM) Support
All Blackhawk XDS560-class Emulators are capable
of collecting System Trace (STM) data from TI CToolsenabled devices. For more information, please visit
www.blackhawk-dsp.com/STM.
AVAILABILITY
All Blackhawk Emulators are available for immediate
delivery from a world wide network of industry resellers
and distributors. Please visit www.blackhawk-dsp.com
for a complete list.
APPLICATION AREAS
Audio, Automotive, Communications, Military, Telecom,
Telecom Infrastructure, Telephony,
Video Conferencing, Video Security, Video and Imaging, Wireless.
CONTACT INFORMATION
Blackhawk
123 Gaither Drive
Mt. Laurel, NJ 08054
USA
856-234-2629 Telephone
856-866-1100 Fax
[email protected]
http://www.blackhawk-dsp.com
Embedded Processing & DSP Resource Guide 2013
Emulators/Analyzers
Emulators/Analyzers
High Performance JTAG Emulators
Blackhawk
The Blackhawk™ USB100v2 JTAG Controllers are very
low-cost controllers for basic debugging of Texas Instruments DSPs. Requiring no external power source, they
can support most of the basic features of higher priced
controllers and require no additional drivers when
installed using the Code Composer Studio™ integrated
development environment (IDE) v4 or later.
Emulators/Analyzers
Emulators/Analyzers
USB100v2 JTAG Controllers
Both models are TI XDS100v2-compatible controllers
fully supported under Code Composer Studio IDE v4/
v5 and future Texas Instruments roadmap software
development environments. Faster code downloads and
assembly code stepping are provided by the use a highspeed USB2.0 (480 Mb/s) port instead of slower USB1.x
(12 Mb/s) implementations.
Both models are identical in hardware and software support, but offer different, native target connection options
- check your target board’s JTAG connector.
USB100v2 Common Features
t )JHI4QFFE64#.CT
)PTU*OUFSGBDF
t 1PXFS4UBUVT-&%
t 8JOEPXTBOE-JOVY4VQQPSUBOECJUFEJUJPOT
t 4VQQPSUFE%FWJDFT
t 5.4$Y)JHI1FSGPSNBODFCJUDPOUSPMMFST
t 5.4$Y1PXFS&GåDJFOU%41T
t 5.4$Y'JYFEQPJOU%41T
t 5.4$Y-PX1PXFS%41T
t 5.4$Y%41T
t 5.4$Y)JHI1FSGPSNBODF%41T
t "3.¥$PSUFY™.CBTFE.$6T
t "3.$PSUFY3QSPDFTTPST
t "3.$PSUFY""3.™.16T
t *OUFHSB™%41"3.QSPDFTTPS
t %B7JODJ™WJEFPQSPDFTTPSTOPUJODMVEJOH%.Y
t WPMUEFWJDF*0TVQQPSU
t 0OMJOF4VQQPSUGSPN5*
USB100v2 Unique Features
t 4VQQPSUGPS$PEF$PNQPTFS4UVEJP*%&W
(XDS100v1 backwards compatibility)
t 0OMZTVQQPSUT5.4$YBOE5.4$Y
devices
USB100v2D Features
t /BUJWFQJOD5*UBSHFUSJCCPODBCMF
t *ODMVEFE5*QJODPOWFSUFS
t 0QUJPOBM"3.QJODPOWFSUFSBWBJMBCMF
USB100v2-ARM Features
t %FTJHOGPS5BSHFUCPBSETXJUI"3.+5"(DPOOFDUJPOT
XXXFFDBUBMPHDPNETQ
t /BUJWFQJO"3.UBSHFUSJCCPODBCMF
t /BUJWFQJO"3.UBSHFUSJCCPODBCMF
AVAILABILITY
All Blackhawk Emulators are available for immediate
delivery from a world wide network of industry resellers
and distributors. Please visit www.blackhawk-dsp.com
for a complete list.
APPLICATION AREAS
Audio, Automotive, Motor Control, Communications, Military, Telecom, Telecom Infrastructure, Industrial, Telephony,
Video Conferencing, Video Security, Video and Imaging, Wireless.
CONTACT INFORMATION
Blackhawk
123 Gaither Drive
Mt. Laurel, NJ 08054
USA
856-234-2629 Telephone
856-866-1100 Fax
[email protected]
http://www.blackhawk-dsp.com
%FWFMPQNFOU5PPMTt
Blackhawk
The Blackhawk XDS560v2 System Trace Emulator models
are is based on the Texas Instruments XDS560v2 JTAG
emulator reference design (XDS560v2). The XDS560v2
design is the next-generation of the high-performance
XDS560-class technology first made available by Blackhawk with the USB560/LAN560 and XDS560 Trace. The
XDS560v2 design adds support for IEEE® 1149.7 and
System Trace (STM), an interface on the TI SOC multicore (ARM® + DSP) devices.
Emulators/Analyzers
Emulators/Analyzers
XDS560v2 System Trace (STM)
XDS560v2POE
IEEE® 1149.7 (cJTAG) Support
MIPI System Trace (STM) Support
RoHS Compliant - Pb free
LEDs for Status / Mode / Activity
Target IO Voltage Range +1.2v - +4.1v
Code Composer Studio™ IDE v4.2 and
later
DSS Java Scripting Support
Variable/Programmable TCK up to 50
MHz
100 MHz STM Export Clock
High-Speed STM Capable JTAG Cable
USB bus-powered
PoE Switch Capable
External Power Supply option
High-Speed USB 2.0 Host Interface
Ethernet (10-100 Mb) Host Interface
Linux 32 and 64-bit Support
Windows 32 and 64-bit Support
Configuration and Test GUI Program
MIPI 60 Target Connection
TI 14 Target Connection
cTI 20 Target Connection
ARM 20 Target Connection
TI 60 (XDS560 Trace) Connection
Price
XDS560v2BP
Model Highlight Indicates a
Blackhawk Unique Feature.
USB560v2
The Blackhawk XDS560v2 models meet all the TI
XDS560v2 reference design features and requirements
- no short-cuts. All models support System Trace data
collection. Here is an overview of features.
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
option
$999
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
$1500
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
$1600
AVAILABILITY
All Blackhawk Emulators are available for immediate
delivery from a world wide network of industry resellers
and distributors. Please visit www.blackhawk-dsp.com
for a complete list.
APPLICATION AREAS
Audio, Automotive, Communications, Military, Telecom,
Telecom Infrastructure, Telephony, Video Conferencing,
Video Security, Video and Imaging, Wireless.
CONTACT INFORMATION
See www.blackhawk-dsp.com for a complete list of features and device support.
t%FWFMPQNFOU5PPMT
Blackhawk
123 Gaither Drive
Mt. Laurel, NJ 08054
USA
856-234-2629 Telephone
856-866-1100 Fax
[email protected]
http://www.blackhawk-dsp.com
Embedded Processing & DSP Resource Guide 2013
Kane Computing Ltd
Kane Computing Company Profile
Kane Computing supply cost effective and reliable DSP solutions to match the user’s needs. We have the widest range
of DSP development tools, hardware and software, in the
UK and we have an intimate knowledge of these products.
◆ TI-trained engineers with the widest range of DSP
development tools in the UK.
◆ UK Distributor/Agent for a wide range of TI 3rd party
products.
◆ Application Areas: Audio, Automotive, Broadband
Kane Computing also have vast experience in video and
audio processing, particularly for compression, streaming
and storage. Kane Computing also works with a number of
members of TI’s Third Party Network who provide hardware
platforms, software libraries and technical resources, to
allow Kane Computing to offer complete packages not available from any other single source.
Solutions, Communications, Imaging, Industrial, Military,
Motor Control, Optical Networking, Telecom, Telephony,
Broadcast, Video, Video
Infrastructure, Wireless.
Emulators/Analyzers
Emulators/Analyzers
Supported TI Processors: DM64x, OMAP35x, DM81xx, C6A816x,
C5xxx, C67xx, C64xx, MSP430™ MCU, C2xxx and DM3xx.
CONTACT INFORMATION
TECHNICAL SPECS
Kane Computing Ltd
Suite I, Ascot Court,
71-73 Middlewich Road
Northwich, Cheshire CW9 7BP
UK
01606 351006 Telephone
01606 351007 Fax
[email protected]
www.kanecomputing.co.uk
◆ Consultants and providers of DSP Development Tools,
hardware and software, for the complete range of TI
DSPs.
◆ Many years of industrial experience of DSPs and
signal/video processing.
A network dedicated
edicated to the needs
edicate
n
off
s, de
designers
rs and
a
engineers, developers,
gers
engineering managers
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XXXFFDBUBMPHDPNETQ
%FWFMPQNFOU5PPMTt
Signum Systems
Supported TI Processors: DM646x, DM644x, DM643x, DM64x,
DM355, OMAP35x, F283x, F282x, F281x, F280x, LF240x, C55x, C54x,
C672x, C67x, C645x, C6414T/15T/16T, C642x, C6410/12/13/18, C62x,
TMS470, TMS570, Stellaris®, Cortex™-M3, Sitara™ AM37x, AM35x,
AM18x, AM17x
JTAGjet is a USB 2.0 based In-Circuit Debugger
designed to support all ARM7/9/11®, Cortex™-M/R/A
as well as all TI DSP, OMAP™, DaVinci™ and Sitara™
devices. JTAGjet comes with a multi-core Chameleon
Debugger for ARM and it can also be used with a variety
of 3rd party debuggers, like IAR Embedded Workbench® for ARM, Texas Instruments Code Composer
Studio™ integrated development environment (IDE),
Eclipse, GNU and others. When used with Chameleon
Debugger, JTAGjet features ETM & ETB real-time
trace, Serial Wire Debugging (SWD), integrated Flash
programming, code profiling, timing analysis and complex triggering events making the debugging process
faster and easier.
Emulators/Analyzers
Emulators/Analyzers
JTAGjet In-Circuit Debuggers for DSP,
OMAP™ and DaVinci™ Processors
◆ Coverage Analysis (ARM and Cortex cores only –
requires ETM)
TECHNICAL SPECS
◆ Supports ARM7, ARM9, ARM11 and Cortex-M/R/A
One of the unique JTAGjet features is that it may
be used concurrently with two different debuggers
offering a complete multi-core debug environment for
systems that use different RTOSes on different cores
FEATURES & BENEFITS
◆ Supports all ARM, Cortex, TI DSP, OMAP, DaVinci
devices from all manufacturers
◆ Supports C2000™, C5000™, C6000™, TMS470,
TMS570, Stellaris, OMAP, OMAP3, DM, DaVinci and
Sitara devices
◆ High-speed USB 2.0 port (480Mbps) allows super
fast RAM downloads and Flash programming
◆ ETM trace clock of up to 200MHz allows debugging
devices running at speeds > 1GHz
and Sitara devices
◆ Available with ETM and/or ETB real-time trace
◆
◆
◆
◆
◆
for quicker, more efficient debugging with timing
analysis
Multi-core support on single and multiple JTAG
chains
Compatible with major ARM and DSP compilers and
debuggers
Integrated GUI and batch mode Flash programming
Real-time trace history of program execution and
variables along with CPU cycle-accurate timing
helps to locate even the most elusive bugs
Embedded Linux support speeds-up debugging
of uBoot, Linux kernel, kernel modules, peripheral
drivers and applications.
AVAILABILITY
Now
APPLICATION AREAS
Audio, Automotive, Broadband, Communications &
Telecom, Computers & Peripherals, Consumer Electronics,
Industrial, Medical, Military, Security, Video and Imaging,
Wireless
CONTACT INFORMATION
IAR SYSTEMS® INC.
1065 E. Hillsdale Blvd., #420
Foster City, CA 94404
650-287-4250
[email protected]
www.signum.com
t%FWFMPQNFOU5PPMT
Embedded Processing & DSP Resource Guide 2013
Adaptive Digital Technologies
Adaptive Digital Echo
Cancellation Library: Acoustic,
Packet, Network, & Line
With a strong focus on providing optimum voice quality,
Adaptive Digital developed an echo canceller unparalleled in quality and efficiency. The “carrier-grade” echo
canceller carries with it the robustness that comes from
the combination of careful design, relentless testing, and
widespread deployment.
The G.168 Plus™ packet EC has the distinctive ability to
handle round-trip delays of up to 512 msec. This ability coupled with a built-in awareness and handling of packet-loss
makes G.168 Plus uniquely suitable for VoIP applications.
Adaptive Digital’s G.168 EC features, enhanced beyond
ITU recommendation include tandem free operation,
dynamic NLP, rapid convergence, convergence monitor,
stationary signal detector, split pre and post processing,
and the ability to cancels multiple reflectors.
G.168 EC Highlights
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FEATURES
◆
◆
◆
◆
◆
Superb speech quality
User Configurable
Cancels multiple independent echo tails
G.168 echo canceller AT&T certified as “Carrier Grade”
Capable of packet echo cancellation: Handles round-trip
delays of up to 512 milliseconds
Algorithms/Codecs
Algorithms/Codecs
Supported TI Processors: DaVinci DM64x, DaVinci DM81x,
DaVinci DM64x, DM646x, DM644x, DM643x, DM64x, DM814x,
DM816x, OMAP35x, OMAP3525/30 SoC, C55x, C55x Dual MAC
DSPs, C54x DSPs, C674x Low Power DSP, C67x DSP, C66x DSPs,
C64x DSP, C62x DSP, C647x Multicore DSP, C645x Multicore DSP,
C667x Multicore DSPs, C665x Multicore DSPs, AM37/AM35x
ARM® Cortex™-A8, AM18x ARM9® , AM17x ARM9, Stellaris®
ARM® Cortex™-M based
BENEFITS
◆
◆
◆
◆
Field-hardened, deployed in 49 countries
ITU G.168 compliant beyond requirements
Available as a chip solution
Included in VoIP Engine
AVAILABILITY
All products are available now.
ACOUSTIC ECHO CANCELLATION
Adaptive Digital’s acoustic echo canceller (AEC) enables
true full-duplex hands-free telephony in mobile phones,
speakerphones, and hands-free intercoms.
AEC Highlights
AEC G4 – Designed for high-end speakerphones and conferencing endpoints. Supports HD Voice, integrated noise
reduction and AGC, supports tail length up to 256 msec,
superior double-talk performance. C6000™, ARM, and
x86 platforms
AEC G2 - Designed for traditional speakerphones, with
enhancements specifically designed for mobile handsets.
C6000, C5000™, ARM, and x86 platforms
XXXFFDBUBMPHDPNETQ
APPLICATION AREAS
Broadband, Communications & Telecom, Consumer
Electronics, Medical, Military,
Security, Wireless
CONTACT INFORMATION
Adaptive Digital Technologies
525 Plymouth Road
Suite 316
Plymouth Meeting, PA 19462
USA
1-800-340-2066 Toll Free
610-825-0182 x120 Telephone
[email protected]
www.adaptivedigital.com
&NCFEEFE4PGUXBSFt
Adaptive Digital Technologies
Voice Algorithms and Solutions on
the Texas Instruments TMS320™
Family of DSPs, OMAP™, DM-Series,
Multi-Core, and ARM® processors
Supported TI Processors: DaVinci DM64x, DaVinci DM81x, DaVinci
DM64x, DM81x Video SoC, DM64x Video SoC, DM646x, DM644x,
DM643x, DM64x, OMAP35x, OMAP3525/30 SoC, C55x, C55x Dual
MAC DSPs, C54x DSPs, C674x Low Power DSP, C66x DSPs, C64x DSP,
C62x DSP, C647x Multicore DSP, C645x Multicore DSP, C667x Multicore DSPs, C665x Multicore DSPs, AM35x/AM37x ARM® Cortex™-A8,
AM18x ARM9™, AM17x ARM9™, Stellaris® ARM® Cortex™ -M based
FEATURES & BENEFITS
◆
◆
VoIP Engine™ is at the core of our ARM-based VoIP applications, it is a software engine package that handles all the
voice processing from PCM to Packet and back. Its intended
use is in VoIP enabled handsets or desktop phones.
G.PAK™, the core technology behind our turnkey solutions, is a VoIP application that runs on a TI DSP or SOC
that handles the complete data flow between the TDM
and Packet interfaces.
◆
◆
◆
Adaptive Digital’s Algorithm Library Includes:
◆
Voice Quality Algorithms: Echo Cancellation – G.168
Line, Network, & Packet, G.168Plus™ Packet EC, Acoustic
Echo Cancellation (AEC), AEC G2 (mobile devices) & HD
AEC G4 (NB/WB), Noise Reduction, Noise Suppression,
and Comfort Noise Generation.
All of the ITU G.XXX vocoders and many of the ETSI and
3GPP compression algorithms.
◆
excellent voice quality while leading the industry in
CPU and memory utilization efficiency.
HD Full-Duplex Acoustic Echo Cancellation for applications ranging from high-end conference endpoints
to desktop phones and mobile handsets.
Customers have the flexibility to choose a turnkey
solution (G.PAK), a highly integrated framework (VoIP
Engine), or a set of algorithm libraries.
Evaluation software is available for testing in your
design. Contact sales or login to our extranet to
download demos.
Adaptive Digital provides support throughout all
project phases; customers have access to our technical team directly over the phone or via email.
Developers of voice-centric applications find both our
algorithms and solutions easy to integrate and well
optimized for their requirements.
Adaptive Digital’s solutions support a low-cost product development model with short time-to-market.
Using its proprietary Echo Analysis test system,
Adaptive Digital can analyze customer’s recorded data
and isolate circuitry and acoustic problems, as well as
assist in echo canceller and voice quality tuning.
AVAILABILITY
All products are available now.
HD Audio/Voice algorithms: HD AEC, HD Conferencing,
G.722, G.722.1, G.722.2 (AMR-WB), Speex
Telephony algorithms: Tone Detect and Suppress, DTMF,
AGC, Arbitrary Tone Detect, R1/R2 Detect, Voice Activity
Detection, Tone Relay, and High Density Conferencing
(NB/WB)
APPLICATION AREAS
Audio, Communications & Telecom,
Medical, Military, Security, Wireless
CONTACT INFORMATION
Military and Defense codecs: MELP/MELPe, CVSD, LPC,
G.729D
Encryption algorithms: AES, SRTP
Modem software: Caller ID, T.38 Fax Relay, V.xx (21, 27,
29, 22Bis, & 32Bis), Modem Relay, and G.165 detect
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Adaptive Digital Technologies
525 Plymouth Road
Suite 316
Plymouth Meeting, PA 19462
USA
1-800-340-2066 Toll Free
610-825-0182 x120 Telephone
[email protected]
www.adaptivedigital.com
Embedded Processing & DSP Resource Guide 2013
Algorithms/Codecs
Algorithms/Codecs
◆ Certified carrier class G.168 Echo Canceller achieves
Adaptive Digital is a developer of voice algorithms, softchip solutions, and VoIP Engine software for VoIP and
traditional telecommunications systems and applications. Our expertise is in the development of solutions
that maximize voice quality as well as channel density.
DSP Innovations Inc.
New TWELP Vocoder
(600…9600 bps)
DSPINI’s high-quality vocoder provides the best speech
quality among competitors today. It has a wide range of
bit rates from 600 bps up to 9600 bps and is intended for
Digital Radio (HF, UHF, DMR, dPMR, etc.), wire communication, VoIP and other markets.
TWELP is:
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◆ Any platforms (DSP, RISC or general-purposes) are
Although the technology is based on well-known
LPC-method, where output speech is gotten by the synthesizing LPC-filter, it is not a variety or combination of
well-known speech coding methods, patented comprehensively during last 20-30 years.
TWELP is a unique three-component representation
of pitch-synchronous LPC residual that is quantized by
unique speech-driven quantizers in conjunction with
LPC-parameters.
available for porting.
◆ Integrated Circuit (Chip). TWELP 2400/3600 bps
vocoder is available also as specialized chip (IC) from
CML Microcircuits.
Algorithms/Codecs
Algorithms/Codecs
The vocoder is based on the newest speech coding technology, called “Tri-Wave Excited Linear Prediction”™
(TWELP™), developed by experts of DSPINI.
◆ One license. No third-party IP holders.
◆ Related software: Linear and Acoustic Echo Cancel-
lers (LEC and AEC), Multi-Channel Noise Cancellers,
modems for radio and wire channels for any bit rates.
FEATURES & BENEFITS
AVAILABILITY
◆ Superiority in speech quality. ITU-T P.50 multi-
language speech base and ITU-T P.862 utility were
used for objective estimation and pair comparisons
by listening were used for subjective estimation.
Varies. Check www.twelp.pro website and contact to
find out current availability.
APPLICATION AREAS
◆ Superiority in non-speech signals (sirens, etc.)
Communications & Telecom, Military, Security, Wireless
◆ High robustness to acoustic noise.
◆ High robustness to channel errors, thanks to FEC,
integrated using “joint source-channel coding”
approach. “Soft Decisions” and “Hard Decisions”
from a modem can be used.
◆ Automatic Gain Control (AGC), Noise Cancellation for
Speech Enhancement (NCSE), Voice Activity Detector
(VAD), Tone Relay (transparence) for any single and
dual tones.
◆ Guarantee of quality thanks to accurate testing and
CONTACT INFORMATION
DSP Innovations Inc.
4 Slavi
Penza, 440600
Russian Federation
7 963 105 32 18 Telephone
[email protected]
www.dspini.com
www.twelp.pro
methods of quality control. Reliable support.
XXXFFDBUBMPHDPNETQ
&NCFEEFE4PGUXBSFt
Adaptive Digital Technologies
IP phone/intercom/ATA for
OMAP3530, OMAP3730, DM814X,
DM816X, and Stellaris® devices.
Adaptive Digital simplifies software design of an IP
Phone, IP Intercom or ATA. We provide the software that
runs on the DSP consisting of a fully functioning and
complete SIP solution with RTP, UDP/IP, G711, G.729AB,
tone handling, and echo cancellation. Additionally we
offer what we call ISS (Intercom Server System), which
is a software component that runs on the ARM under
Linux. The ISS deals with the DSP interface and control,
and RTP streaming over UDP/IP. The ISS also provides an
interface to your ARM-based application.
Adaptive Digital’s ISS software subsystem simplifies
software design of an IP intercom or IP phone that runs
on TI’s OMAP3530 and DM814x/DM816x devices. ISS
implements complete VoIP capability all the way from
PCM to Packet and back. This includes a process running
on the ARM under Linux as well as the necessary voiceprocessing running on the DSP core.
◆ VOICE PROCESSING FUNTIONS INCLUDE: Digital
◆
Adaptive Digital’s ATA solution is a software and
hardware reference design that provides equipment
manufacturers a fast path to market for a low-cost ATA.
The application runs completely within the Stellaris®
MCU’s internal flash memory and RAM. A Silicon Labs
ProSLIC™ provides the FXS line interface and a Codec as
well as POTS protection circuitry that typically requires
additional circuitry. Stellaris MCU-based ATA and IP
Phone software solutions share a similar base set of protocols and algorithms while separately addressing the
features that are unique to these two solutions.
◆
◆
◆
Gain Control, Noise Reduction, Vad/CNG, RTP & Jitter
Buffer, AGC, G.711 u-Law, G.711 A-Law, and G.729AB.
The combination of TI’s ARM® and DSP processors
and Adaptive Digital’s superior algorithms and G.PAK
framework, provide a solid foundation for the development of differentiated next-gen telecom products.
Adaptive Digital’s VoIP Intercom ISS enables equipment manufacturers to develop products quickly and
cost-effectively.
Our engineering team has over thirty years’ experience in practical and theoretical aspects of DSP
Software, and Communications.
Should modifications be necessary for your project,
customization is available.
FEATURES
APPLICATION AREAS
◆ Stellaris MCU-based IP Phone, IP Intercom, and ATA
Broadband, Communications & Telecom, Medical,
Military, Security, Wireless
ATA - Highly integrated, low chip count. Supports
single or dual port, call control and management.
◆ ATA Software includes: Line EC, G.711 with PLC,
G.729AB, SIP, RTP Packetization, Caller ID, Tone Det/
Gen, and Configurable Jitter Buffer.
◆ OMAP™ processor, DM814x, and DM816x based-IP
Phone, and IP Intercom
◆ The VoIP software includes Adaptive Digital’s Gen-4
Acoustic Echo cancellation, which incorporates a
noise reduction feature, as well as anti-howling,
nonlinear processing, and double-talk detection.
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CONTACT INFORMATION
Adaptive Digital Technologies
525 Plymouth Road
Suite 316
Plymouth Meeting, PA 19462
USA
1-800-340-2066 Toll Free
610-825-0182 x120 Telephone
[email protected]
www.adaptivedigital.com
Embedded Processing & DSP Resource Guide 2013
Application-Specific Libraries
Application-Specific Libraries
Supported TI Processors: DaVinci™ DM81x processor, DM81x
Video SoC, DM814x, DM816x, OMAP35x, OMAP3525/30 SoC,
Stellaris® ARM® Cortex™-M based MCUs: 3000 Series
DelCom Systems, Inc.
GSM/EGPRS/EDGE LayerONE
Physical Layer Software
DelCom’s GSM LayerONE is a turnkey 2.75G physical layer
solution based on software-defined radio (SDR). Designed
with ease of integration in mind, the software framework
allows for rapid product development without the need for
expertise in the intricacies of modulation, channel coding,
interleaving, and physical channel multiplexing. Clean and
concise Layer 2, Layer 3, and base-band interfaces and extensive logging capabilities make integration a snap. Available
for a variety of processors including some of TI’s OMAP™
processors, DaVinci™ video processors, TCI, Faraday, and
TMS320C6000™, and TMS320C5000™ DSPs. DelCom’s LayerONE physical layer framework offers the scalability and
flexibility only a software solution can provide.
◆ Packet-switched traffic modes include GPRS CS-1
FEATURES & BENEFITS
Application-Specific Libraries
Application-Specific Libraries
Supported TI Processors: DaVinci™ DM64x, DaVinci DM81x, DaVinci
DM64x, DaVinci DM37x, DaVinci DM3x, DM81x Video SoC, DM64x
Video SoC, DM646x, DM644x, DM643x, DM64x, DM37x, DM3x,
DM814x, DM816x, OMAP35x, OMAP3525/30 SoC, TMS320DM37x SoC,
TMS320DM3x Video SoC, OMAPL1x, C6A816x, C6A814x, C55x, C55x
Dual MAC DSPs, C54x™ DSPs, C674x Low Power DSP, C67x DSP, C66x
DSPs, C64x DSP, C62x DSP, C647x Multicore DSP, C645x Multicore
DSP, C66x Multicore DSPs, C647x Multicore DSP, C645x Multicore DSP,
C667x Multicore DSPs, C665x Multicore DSPs, AM389x/AM35x/AM37x
ARM® Cortex™-A8, AM18x ARM9, AM17x ARM9
through 4 and EDGE/EGPRS MCS-1 through 9.
◆ Automatic system information message scheduling
◆ Portable to almost any commercially available DSP,
◆
◆
◆
◆
general-purpose processor, or proprietary core with
customizable interfaces to drop into your existing
design or network stack.
Perfect for femtocell and picocell applications as well
as standard BTS designs.
Ideal for use in specialty applications such as pointof-sale devices, test and measurement equipment,
proprietary modems, network load monitors, IMSI/
IMEI catchers, and lawful call interceptors (SIGINT).
Extensive built-in test functionality and L3, L2, and
base-band logging capabilities simplify integration
and hardware qualification.
Flexible terms including full source code licenses
are available to qualified customers. All core library
modules for both MS and BTS devices including the
GMSK and 8PSK (EDGE) equalizers are also available
for license individually.
TECHNICAL SPECS
◆ Circuit-switched traffic modes include TCH/FS, TCH/
EFS, TCH/AFS, TCH/WFS, TCH/HS, TCH/AHS, TCH/
F14.4, TCH/F9.6, TCH/F4.8, and TCH/F2.4.
XXXFFDBUBMPHDPNETQ
and transmission.
◆ A5/1, A5/2, and A5/3 ciphering support.
◆ Includes support for detection of neighboring cells
for femtocell and custom applications.
AVAILABILITY
Available now.
APPLICATION AREAS
Broadband, Communications & Telecom, Consumer
Electronics, Industrial, Military, Security, Wireless
CONTACT INFORMATION
DelCom Systems, Inc.
260 Bear Hill Rd
Suite 101
Waltham, MA 02451
USA
781-890-4650 Telephone
781-890-2055 Fax
[email protected]
www.delcomsys.com
&NCFEEFE4PGUXBSFt
D.SignT GmbH & Co. KG
D.SignT TCP/IP Stack for TI C2000™
MCUs, C5000™, and C6000™ DSPs
Supported TI Processors: DM64x, C55x, C67x DSP, C64x DSP,
F28x Delfino™ MCU floating-point series, F28x fixed-point series
The D.SignT TCP/IP stack has been carefully tailored
to the requirements of DSP systems. Code and data
memory size are minimized, and no additional resources
like DSP interrupts or timers are required. The TCP/IP
protocol stack does not require an underlying real-time
operating system and can be used in a linear C program.
In addition the stack can run as a task in a RTOS, e.g.
DSP/BIOS. The user has full control to balance the processor time for communications and signal processing.
No large memory buffers are required because the
zero-copy stack feature transfers data directly out of
or into the application data buffers, thereby minimizing
memory requirements, latencies and processor time. An
overview of memory requirements for a typical configuration (including ARP, IP, ICMP, UDP, TCP, DHCP and DNS)
is given below in the Technical Specs.
To evaluate and test the D.SignT TCP/IP stack, DSK Ethernet Daughter Cards for C2000™ MCUs and, C5000™,
C6000™ processors EVMs, and DSKs are available. The
Quantity and OEM licenses include design-in support
to integrate Ethernet communications into your custom
hardware. Various Ethernet network controllers are supported.
TECHNICAL SPECS
◆ TMS320F2812/28335 typical resource requirements:
code: 27.4K bytes,
data: 5.6K bytes + 604 bytes per socket
◆ TMS320C55x typical resource requirements:
code: 35K bytes,
data: 8K bytes + 640 bytes per socket
◆ TMS320C6000™ DSP typical resource requirements:
code: 72K bytes,
data: 7.2K bytes + 604 bytes per socket
AVAILABILITY
FEATURES & BENEFITS
now
◆ does not require a real-time operating system
◆ zero-copy stack minimizes data memory resource
APPLICATION AREAS
consumption
◆ application has full control to balance communica-
Industrial,
Wireless
Security,
Video,
tions and signal processing resources
◆ Evaluation Hardware Platform (DSK Daughter Cards)
available for C2000™ MCUs, C5000™ and C6000™
processors
◆ Licensing Models: Test and Development License,
Small Quantity (10) License, Medium Quantity (100)
license, OEM license. License includes hardware
design-in support.
t&NCFEEFE4PGUXBSF
CONTACT INFORMATION
D.SignT GmbH & Co. KG
Marktstr. 10
Kerken, 47647
Germany
+49 2833 570977 Telephone
+49 2833 3328 Fax
[email protected]
www.dsignt.de
Embedded Processing & DSP Resource Guide 2013
Drivers/IO/Control Software
Drivers/IO/Control Software
TCP/IP communications on an embedded DSP system
greatly differs from Personal Computer requirements. A
DSP is not required to handle hundreds of simultaneous
connections as does a PC based server. On the other
hand, latencies and resource consumption are much
more critical to avoid compromising signal processing
performance.
Adaptive Digital Technologies
G.PAK bridges the gap between
inflexible fixed-function chips and
custom programmed solutions
Supported TI Processors: DaVinci™ DM64x, DM646x, DM644x,
DM643x, DM64x, DM814x, DM816x, OMAP35x, C54x DSPs, C66x
DSPs, C64x DSP, C647x Multicore DSP, C645x Multicore DSP
G.PAK provides all of the DSP components necessary in
a voice-over-packet system and provides an application
interface to allow easy integration into a user’s application. It includes one or more algorithms like conferencing,
vocoders, echo cancellation, tone detection, etc. G.PAK
runs the entire DSP and interfaces with peripherals such
as the serial port.
G.PAK is run time configurable allowing channels to be setup
for individualized processing. Channel setup (identification
of input and output ports, vocoders, and voice algorithms),
conference setup, and teardown operations are performed
at run time. G.PAK DSPs interface to a host control processor.
Adaptive Digital’s G.PAK DSP software solutions address
the need for high-density, VoIP, and traditional telecommunications applications. Adaptive Digital provides pre-built
G.PAK software images for telephony applications such as
VoIP gateway, conferencing, and transcoding. These solutions include host API software to simplify the process of
integrating a host processor with the DSP applications.
G.PAK can easily be customized to include only the necessary algorithms, channel configurations, and interfaces of
a particular application’s requirements. If G.PAK’s built-in
flexibility is not enough, source code can be licensed.
◆ G.PAK enables developers to implement high-density,
multi-channel, voice-over-packet applications in the
shortest possible time with maximum processing
performance.
◆ G.PAK is a “built” to order, voice over packet software
solution. Spend your engineering resources on
features that differentiate your product.
◆ Adaptive Digital’s G.PAK is also interoperable with TI’s
Telogy Software® on the TNETV™ VoIP system-onchip (SOC) series.
◆ A video demonstration of the G.PAK build process can
be found on Adaptive Digital’s web site at http://www.
adaptivedigital.com/video_training/GPAK/GPAK.htm.
Framework Software
Framework Software
G.PAK™ integrates the building blocks that are required
voice-over-IP and voice-over-LTE systems into a turnkey
solution. G.PAK is a scalable, build time configurable voiceover-packet DSP software application that runs on the TI’s
TMS320C5000™ and TMS320C6000™ families of DSPs.
AVAILABILITY
This product is available now.
FEATURES & BENEFITS
APPLICATION AREAS
◆ G.PAK supports several channel types: TDM to Packet,
PCM to TDM, Packet to Packet, TDM to Conference,
Packet to Conference, and Conference Composite.
◆ For those who want to customize the G.PAK software
beyond the capabilities of the automated configuration utility, application source code is available,
encouraged, and supported.
◆ The combination of TI’s High Density DSPs with
Adaptive Digital’s field-tested algorithms and G.PAK
framework provide a solid foundation for the development of high-quality, differentiated telecom products.
XXXFFDBUBMPHDPNETQ
Communications
Wireless
&
Telecom,
CONTACT INFORMATION
Adaptive Digital Technologies
525 Plymouth Road
Suite 316
Plymouth Meeting, PA 19462
USA
1-800-340-2066 Toll Free
610-825-0182 x120 Telephone
[email protected]
www.adaptivedigital.com
&NCFEEFE4PGUXBSFt
HCC Embedded
Advanced Embedded Middleware
Supported TI Processors: DaVinci™ DM37x, DaVinci DM3x,
OMAP35x, TMS320DM37x SoC, C54x DSPs, C66x DSPs, C64x DSP,
C62x DSP, AM37x ARM® Cortex™-A8 , AM35x ARM Cortex-A8,
AM18x ARM9 , AM17x ARM9, F28M35x Concerto™ Series, F28x Delfino™ MCU floating-point series, F28x Piccolo™ MCU series, F28x
fixed-point series, MSP430L092 Series – Low Voltage, MSP430F1xx
Series – Up to 8 MHz, MSP430G2xx Value Series – Up to 16 MHz,
MSP430F2xx Series – Up to 16 MHz, MSP430AFE2xx Series – Up
to 12 MHz, MSP430F4xx Series – Up to 8 or 16 MHz, MSP430F5xx/
F6xx Series – Up to 25 MHz, MSP430FR57xx FRAM Series – Up to 8
or 24 MHz, 1000 Series, 2000 Series, 3000 Series, 5000 Series, 6000
Series, 8000 Series, 9000 Series
TECHNICAL SPECS
FEATURES & BENEFITS
◆
◆
◆
◆
Layer provides a high-performance solution to interface
with any Flash-based media. SafeFTL presents a simple
logical sector interface and manages the underlying
complexity efficiently and safely.
Fail-safe File Systems: five highly optimized file systems which can be used even on the smallest MCUs.
Support for any target media with incredibly high
performance and support for all NAND/NOR flash.
USB Device, Host & OTG: support for all speeds and all
end-point types. Advanced class drivers which can support multi-media network and file system integration.
MISRA Compliant TCP/IP: advanced, high speed,
embedded networking software built to fully
verifiable standards. Support for IPv4 & IPv6 and
extensive range of protocols.
Boot-loaders: customizable boot-loaders supporting
file, USB or serial interfaces. Fully fail-safe recovery
from interrupted programming. AES encryption
module for secure data transfer.
◆ Verifiable Middleware Components: using a strong
◆
◆
◆
◆
development methodology, HCC supplies a cooperative scheduler and TCP/IP stack which are developed
to the highest verifiable standards.
Seamless RTOS Integration: all HCC middleware is
developed with no dependence on the hardware or
software environment. Software is supplied with
efficient abstractions to nearly all popular commercial RTOS (and none).
High Performance: with a focus only on storage and
communications software, HCC has attained memory
utilisation and speed of execution which is unrivalled.
Extensive Tool Support: projects can be supplied for
almost any popular IDE or compiler with no need for
engineers to perform integration or complex peripheral configuration to get a project started.
Royalty Free Licensing: straightforward licensing
with no run-time fees and support and maintenance
included in the price.
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AVAILABILITY
Immediately
APPLICATION AREAS
Audio, Automotive, Broadband, Communications &
Telecom, Computers & Peripherals, Consumer Electronics, Industrial, Medical, Military, Security, Video,
Wireless
CONTACT INFORMATION
HCC Embedded
444 East 82nd Street
New York, NY 10028
USA
+1 212 734 1345 Telephone
[email protected]
www.hcc-embedded.com
Embedded Processing & DSP Resource Guide 2013
Framework Software
Framework Software
◆ Flash Management: truly fail-safe Flash Translation
Advanced Embedded Framework: all software components from HCC can be integrated easily with almost any
common RTOS, development environment, peripheral
or flash device. The ability to achieve this efficiently is a
central part of the company’s technology strategy. It also
provides an important benefit for those companies who
do not want to rely on proprietary operating systems in
their design. HCC developed its Advanced Embedded
Framework to enable consistent abstractions and interfaces to any embedded environment. This means that
engineers can easily integrate HCC middleware whether
they have proprietary or commercial software platforms.
The framework not only provides a consistent set of
interfaces, but it also creates the environment for HCC to
apply its rigorous coding standard in the development of
MISRA compliant and verifiable software components.
Anaren
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End-Equipment Solutions
End-Equipment Solutions
CONTACT INFORMATION
Anaren
6635 Kirkville Road
East Syracuse, NY 13057
USA
800-411-6596 Toll Free
[email protected]
www.anaren.com
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Critical Link
MityARM System on Modules
based on TI AM335x processors
Supported TI Processors: AM335x ARM® Cortex™-A8
MityARM-335x is a family of highly-configurable, small
form-factor AM335x based modules optimized for
numerous commercial and industrial communications
protocols and high performance user interfaces. With
multiple versions, the MityARM-335x family meets a broad
range of processing requirements and product needs.
MityARM-335x is based on the ARM® Cortex™-A8 32-bit
RISC processor includes optional graphics acceleration. It
provides a complete and flexible CPU infrastructure for
highly integrated embedded systems.
The MityARM-335x is optimized to speed your development
of a robust, high quality product at a price point to fit within
your cost targets. Critical Link provides superior product
support and a life-cycle that ensures long-term availability.
◆ Robust OS support, including Real-Time Embedded
Linux, QNX and Windows Embedded Compact 7
◆ Small form factor: 68mm x 38mm; std. SODIMM-204
connector; ind. temp -40C to +85C available
◆ Industrial communications: CAN Bus, EtherCAT, PRO-
TECHNICAL SPECS
FIBUS, Profinet, Powerlink, Secos-IIII and Ethernet/IP
◆ Applications: medical, industrial automation, instru-
◆ ARM Cortex-A8 up to 720Mhz; integrated SGX530
3D graphics accelerator; onboard NOR, NAND, and
DDR3; integrated power management
mentation; scientific instrumentation; custom kiosks;
scales; security; building
automation; rich UIs
MityDSP™ and MityARM System
on Modules with FPGA
Supported TI Processors: OMAP-L138, C6748, AM1808
MityDSP and MityARM SOMs support a wide range of application requirements. In addition to modules built around TI’s
C6711 and C645x DSPs, Critical Link SOMs supports some
of TI’s OMAP™ and Sitara™ ARM® processors – the OMAPL138, AM1808, and C6748 DSP-based devices built for apps
requiring minimal power consumption. The MityDSP-L138F
combines DSP, ARM® processor, and Xilinx® Spartan®-6
FPGA processing power. The MityARM-1808F combines an
ARM processor with a Spartan-6 FPGA; the MityDSP-6748F
pairs a floating point DSP with a Spartan-6 FPGA. FPGA can
be used for I/O expansion, signal processing, and high speed
data acquisition. CPU-only versions are also offered. All modules are interchangeable, allowing for a single solution that
takes advantage of a highly scalable CPU/FPGA subsystem.
TECHNICAL SPECS
◆ OMAP-L138 (ARM + floating point DSP), AM1808
(ARM only), or TMS320C6748 processor (floating
point DSP only) in multiple speeds up to 456MHz
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◆ Xilinx Spartan-6 FPGA available in multiple sizes
◆ OS supported: Real-Time Embedded Linux, QNX,
DSP/BIOS™, StarterWare, VxWorks, ThreadX, Windows Embedded CE 6.0
◆ SOMs include 128MB DDR2, 8 MB NOR flash, 256MB
NAND flash; multiple I/O, additional memory options
◆ Applications: industrial automation; scientific, medical, industrial instrumentation; network enabled data
acquisition; test & measurement; machine vision
CONTACT INFORMATION
Critical Link
6712 Brooklawn Parkway
Syracuse, NY 13211
US
315.425.4045 Telephone
315.425.4048 Fax
[email protected]
www.mitydsp.com
Embedded Processing & DSP Resource Guide 2013
End-Equipment Solutions
End-Equipment Solutions
Critical Link
Z3 Technology, LLC
Compact Low-Power SoftwareEnabled HD Multimedia Module
DaVinci™Video Processors: DM8107 DaVinci video SoC
Z3 Technology’s Z3-DM8107-MOD low-power, high
definition multimedia encoder/decoder module is
based on the Texas Instruments TMS320DM8107
DaVinci video processor. It measures only 82mm x
43mm, less area than a typical business card.
Z3 offers customized, fully integrated video encoding
and decoding modules based on open-source Linux. The
TMS320DM8107-based module allows for user expansion with additional audio, video and image codecs,
as well as customer-specific application software. It is
capable of H.264 encoding or decoding up to 1080p60.
◆ Compact Size: 82mm x 43mm
◆ Supports H.264 HP QCIF to 1080p60
◆ Supports TMS320DM8107 processors running at
720MHz ARM® Cortex™-A8 microprocessors
◆ 1GB DDR3, 256MB Flash
◆ Parallel and serial CMOS sensor ports
AVAILABILITY
Available Today. Contact [email protected] for more
details or visit us on the web at www.z3technology.com
FEATURES & BENEFITS
APPLICATION AREAS
◆ OEM-ready HD multimedia module based on the low-
Audio, Automotive, Broadband, Communications &
Telecom, Consumer Electronics, Industrial, Medical,
Military, Security, Video
◆
◆
◆
◆
power multimedia TMS320DM8107 DaVinci video
processor technology.
The H.264 encoder supports full parameter control
via API and leverages hardware acceleration of the
TMS320DM8107 to support a full H.264 1080p60.
Ready-to-run software multimedia executables for
encode and stream, decode from stream, encode to
storage and decode from storage.
Z3-DM8107-MOD can support up to 4 inputs, 4 output
digital video ports.
Module supports open-source Linux 2.6.3x.
Complete Linux OS, multimedia software and SDK
available for application development and system
integration.
End-Equipment Solutions
End-Equipment Solutions
The Z3-DM8107-MOD module supports pre-compiled, pre-loaded, ready-to-run software executables.
The combination of Z3’s Z3-DM8107-MOD and precompiled executables enable ODM/OEMs to rapidly
develop video products in application areas such
as digital video recorders, network video recorders,
industrial video interface displays and medical
imaging.
TECHNICAL SPECS
CONTACT INFORMATION
Z3 Technology, LLC
100 N. 8th Street
STE 250
Lincoln, NE 68508
USA
+1.402.323.0702 Telephone
+1.801.697.6829 Fax
[email protected]
www.z3technology.com
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Advantech Co., Ltd.
DSPC-8681 Half-length PCI Express
Multimedia Processing Card
Supported TI Processors: C667x multicore DSPs
DSPC-8681 includes Serial RapidIO and SGMII daisy-chains
for connecting DSP devices. Each DSP device is connected
by 2 separate PCIe lanes (PCIe x2) via PEX8624 enabling up
to 10Gbps non-blocking throughput. The card supports 120
channels in a H.264 mobile video application (CIF, 30fps)
and 60 channels in a content delivery network (SD, 30fps).
For HD Broadcast applications, DSPC-8681 supports 4
channels of AVCIntra-50, 10-bit, 4:2.0 at 60fps. The 32 DSP
cores make it ideal for power efficient solutions and it is
perfect for applications such as digital media, communications, video-surveillance, medical imaging, bioinformatics,
radar, sonar and instrumentation, high performance computing as well as test and measurement.
◆ 1 GB DDR-1333 on board memory per DSP
◆ Support XDS560v2 evaluation module via JTAG for
Code Composer Studio IDE connection
◆ Support both Linux and Windows drivers
CONTACT INFORMATION
TECHNICAL SPECS
Advantech Co., Ltd.
[email protected]
www.advantech.com
◆ 4 TI TMS320C6678 DSPs on single half-length PCI
Express Card with PCIe Gen 2 x8 interface to the
edge connector
◆ 8 TMS320C66x DSP Core Subsystems (C66x CorePacs) @ 1.0 GHz per DSP
Embedded Processing & DSP ONLINE
www.eecatalog.com/dsp
Explore...
➔ Directory of leading DSP & Embedded Solutions
t&OHJOFFSJOH4FSWJDFT
➔ White Papers
➔ Expert Opinions (Blogs)
➔ Exclusive Videos
CONTACT INFORMATION
➔ Valuable Articles
Sign up for the quarterly
Embedded Processing & DSP E-Product Alert
at www.eecatalog.com/dsp
Embedded Processing & DSP Resource Guide 2013
Digital Hardware / Board Design
Digital Hardware / Board Design
➔ Top Stories and News
Benchmark Electronics
World Wide Electronics Design
and Manufacturing Services
Project Description
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Design Services
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◆ Cameras:
◆
◆
TECHNICAL SPECS
◆
◆ Software:
◆
◆
◆
◆
◆
◆
◆
CONTACT INFORMATION
Benchmark Electronics
(507) 535-4274 Telephone
[email protected]
www.bench.com
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Full Turnkey Designs
Full Turnkey Designs
◆
Android – 2.3 Gingerbread
4.0 Ice Cream Sandwich; QNX
Processor:
TI OMAP™ 4 family of processors
Memory:
Micron 8Gb POP LPDDR2
Display / User Interface:
10.1” Projected Capacitive Multi-Touch interface
WSVGA 1024 x 600 LCD with LED Backlight - 262K
(RGB 6-bits).
Accelerometer / Gyro:
STMicro LSM303DLHC 3-axis MEMS accelerometer –
3 axis magnetometer
STMicro L3G4200D 3-axis MEMS gyroscope
Omnivision - 5MPI Rear Facing OV5640 Auto Focus –
OV7739 VGA FF Front Facing
Audio:
TI TWL6040A
WiFi / BT:
Bluetooth and WLAN 802.11 b/g/n
LSR TiWi-R2
Other interfaces:
HDMI, USB OTG, RS-232 (Debug)
Non-Volatile Memory:
Up to 32GB μSD – 8GB on board eMMC
Power Management:
TI (TWL6030 Power Management Companion IC)
Cellular Interface:
Socketed Wireless modules – support for UMTS/
HSDPA and CDMA
Battery:
25Wh Battery Dual Cell Polymer Li-Ion
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Micross Components
DSP & Microcontroller Die
and Alternative Packaging
The Micross family of COTS DDR and DDR2 SDRAM is
designed to provide PCB engineers with high density
memory solutions that support the wide data widths
and extended environments demanded by embedded
applications.
Micross high performance memory is available in BGA
packages as small as 1 in2 with either 1.27mm or 1.0mm
pitch. Our memory also features data transfer rates of
up to DDR2-667 and adjustable data with output drive
strength and 4-bit pre-fetch architecture.
With densities of 256MB, 512MB, and 1GB in x72
and x64 configurations, our SDRAM memory provides significant benefits for designers. By typically
providing greater than 50% space savings over conventional TSOP or FBGA designs, PCB layout takes
advantage of lower component counts. Simplified
memory-down routing can reduce routing time for
board designers and save up to 4 layers in the PCB.
This enables Class 3 PCB rule compliance since .5mm
and .65mm pitch memory parts can be avoided. Accurate placement of wider pitch parts on larger capture
pads are advantages accrued by the assembly side of
the business. Simplified routing opens up board real
estate for additional product features for the user.
The result is an opportunity to capture more sales
with a richer feature set.
Micross memory products also improve parasitic performance at both the first and second level. Use of
Micross iPEM provides reduced bus capacitance and
increased signal integrity.
FEATURES & BENEFITS
◆ Board real estate savings of up to 60%
◆ Extended environment for industrial and military
applications
◆ Simplified I/O down routing
◆ Reduced trace lengths for improved parasitic perfor-
mance at first and second level and superior signal
integrity
◆ Reduced component count and wider pitch ball
placements
AVAILABILITY
Die and packaging solutions from Micross Components
are available now. For more information please visit our
website at www.micross.com
APPLICATION AREAS
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CONTACT INFORMATION
Micross Components
7725 N. Orange Blossom Trail
Orlando, Florida 32810
USA
1-855-4COMPONENTS Toll Free
407-298-7100 Telephone
407-290-0164 Fax
[email protected]
www.micross.com
Embedded Processing & DSP Resource Guide 2013
Full Turnkey Designs
Full Turnkey Designs
Audio, Automotive, Communications & Telecom, High
Performance Compute, Industrial, Medical, Military,
Security, Video, Wireless
One Source For High
Performance TI DSP
Development Tools
SPECTRUM DIGITAL
ST SOLUTIONS
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XDS560v2, XDS560v2 STM Traveler,
XDS560v2 LC Traveler, XDS510 USB,
XDS510USB PLUS, XDS100v2/v3,
XDS100v3, XDS510USB Galvanic,
XDS510PP PLUS, C2000 XDS510LC,
SPI530 MPSD, JTAG Pin Adapters
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12502 Exchange Drive, Suite 440
Stafford, Texas 77477
T: 281.494.4500 F: 281.494.5310
www.spectrumdigital.com
8/15/12
INTERNATIONAL RESELLERS
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>ULGARIA: 359.2.953.0078
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