Infineon TLE7182EM Gate Driver Data Sheet
Below you will find brief information for H-Bridge Driver IC TLE7182 EM. The TLE7182 EM is a H-bridge driver IC dedicated to control 4 N-channel MOSFETs typically forming the converter for a high current DC motor drives in the automotive sector. It incorporates several protection features such as over current and short circuit detection as well as under-, over voltage and over temperature diagnosis.
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Data Sheet, Rev 1.1, Sept. 2010
TLE7182EM
H-Bridge and Dual Half Bridge Driver IC
Automotive Power
Table of Contents
Pin Definitions and Functions 5
General Product Characteristics 7
Description and Electrical Characteristics 10
Driving MOSFET Output Stages 10
Dead Time and Shoot Through Protection 11
Reverse polarity protection of motor bridge 12
Protection and Diagnostic Functions 16
Vs and VDH Over Voltage Warning 16
Further Application Information 25
H-Bridge and Dual Half Bridge Driver IC
TLE7182EM
Table of Contents
Data Sheet 2 Rev 1.1, 2010-09-30
H-Bridge and Dual Half Bridge Driver IC
TLE7182EM
1 Overview
Features
• Drives 4 N-Channel Power MOSFETs
• Separate control input for each MOSFET
• Unlimited D.C. switch on time of Low and Highside MOSFETs
• 0 …95% at 20kHz & 100% Duty cycle of High Side MOSFETs
• 0 ... 100 % Duty cycle of Low Side MOSFETs
• Additional output to drive a reverse polarity protection N-MOSFET
• Current sense OPAMP
• Low quiescent current mode
PG-SSOP-24
• Internal shoot through protection and minimum internal dead time option
• 1 bit diagnosis / ERR
• Over current warning based on current sense OPAMP with fixed warning level
• Analog adjustable Short Circuit Protection levels via SCDL pin with open pin detection and SCD deactivation
• Over temperature warning
• Over voltage warning
• Under voltage warning and shutdown
• Green Product (RoHS compliant)
• AEC Qualified
Description
The TLE7182EM is a H-bridge driver IC dedicated to control 4 N-channel MOSFETs typically forming the converter for a high current DC motor drives in the automotive sector. It incorporates several protection features such as over current and short circuit detection as well as under-, over voltage and over temperature diagnosis.
The TLE7182EM perfectly fits for driving 2 valves or solenoids too.
Typical applications are fans, pumps and electric power steering. The TLE7182EM is designed for a 12V power net.
Table 1 Product Summary
Specified operating voltage
Junction temperature
Maximum output source resistance
Maximum output sink resistance maximum quiescent current
1)
1) typical value at
T
j
=25°C
C
V
SOP
T
j
R
Sou
R
Sink
I
QVS
7.0 V … 34 V
-40 °C .. 150°C
13.5
Ω
9
Ω
8 µA
Type
TLE7182EM
Data Sheet
Package
PG-SSOP-24
3
Marking
TLE7182EM
Rev 1.1, 2010-09-30
H-Bridge and Dual Half Bridge Driver IC
TLE7182EM
Block Diagram
2 Block Diagram
____
ERR
SCDL
ENA
___
IH1
IL1
___
IH2
IL2
ISO
VREG
VS
Charge pump
HS2
Charge pump
HS1
VREG
Floating HS driver
Short circuit detection
Diagnostic logic
Under voltage
Over voltage
Over current
Overtemperature
Short circuit
Reset
L
E
V
E
L
I
F
S
H
T
E
R
Input control
Shoot through protection dead time
Floating LS driver
Short circuit detection
Floating HS driver
Short circuit detection
Floating LS driver
Short circuit detection
Shunt signal conditioning
Over current detection
RPP
RPP
VDH
BH1
GH1
SH1
GL1
BH2
GH2
SH2
GL2
SL
ISP
ISN
Figure 1 Block diagram TLE7182EM
Data Sheet
GND
4 Rev 1.1, 2010-09-30
H-Bridge and Dual Half Bridge Driver IC
TLE7182EM
Pin Configuration
3
3.1
Pin Configuration
Pin Assignment
BH2
GH2
SH2
GL2
VDH
RPP
Vs
VREG
ENA
ISN
ISP
ISO
1
2
3
4
5
10
11
12
8
9
6
7
24
23
22
21
20
15
14
13
19
18
17
16
BH1
GH1
SH1
GL1
SL
GND
ERR
IH1
IH2
Figure 2
3.2
6
7
4
5
8
9
# of
Pins
1
2
3
14
15
16
10
11
12
13
Data Sheet
ISN
ISP
ISO
IH2
IL2
IH1
IL1
Pin Configuration
Pin Definitions and Functions
Symbol Function
BH2
GH2
SH2
GL2
VDH
RPP
VS
VREG
ENA
Pin for + terminal of the bootstrap capacitor of phase 2
Output pin for gate of high side MOSFET 2
Pin for source connection of high side MOSFET 2
Output pin for gate of low side MOSFET 2
Voltage input common drain high side for short circuit detection charge pump output for reverse polarity protection of the motor bridge
Pin for supply voltage
Output of supply for driver output stage - connect to a capacitor
Input pin for reset of ERR registers, active switch off of external MOSFETs and low quiescent current mode, set HIGH to enable operation
Input for OPAMP + terminal
Input for OPAMP - terminal
Output of OPAMP
Input for high side switch 2 (active low)
Input for low side switch 2 (active high)
Input for high side switch 1 (active low)
Input for low side switch 1 (active high)
5 Rev 1.1, 2010-09-30
21
22
23
24
Tab
# of
Pins
17
18
19
20
Symbol
ERR
SCDL
GND
SL
GL1
SH1
GH1
BH1
Tab
H-Bridge and Dual Half Bridge Driver IC
TLE7182EM
Pin Configuration
Function
Push pull output stage
Input pin for adjustable Short Circuit Detection function and SCD deactivation
Ground pin
Pin for common source of lowside MOSFETs
Output pin for gate of low side MOSFET 1
Pin for source connection of high side MOSFET 1
Output pin for gate of high side MOSFET 1
Pin for + terminal of the bootstrap capacitor of phase 1 should be connected to GND
Data Sheet 6 Rev 1.1, 2010-09-30
H-Bridge and Dual Half Bridge Driver IC
TLE7182EM
General Product Characteristics
4 General Product Characteristics
4.1
Absolute Maximum Ratings
Absolute Maximum Ratings
1)
40
°C ≤
T
j
≤ 150 °C ; all voltages with respect to ground, positive current flowing into pin (unless otherwise specified)
Pos.
Parameter Symbol Unit Conditions
Min.
Limit Values
Max.
Voltages
4.1.9
4.1.10
4.1.11
4.1.12
4.1.13
4.1.14
4.1.15
4.1.16
4.1.17
4.1.18
4.1.1
4.1.2
4.1.3
4.1.4
4.1.5
4.1.6
4.1.7
4.1.8
Supply voltage at VS
Supply voltage at VS
Voltage range at VDH
Voltage range at RPP maximum current at RPP
Voltage range at ENA
Voltage range at SCDL
Voltage range at IH1, IL1, IH2, IL2
Voltage range at ERR, ISO
Voltage range at ISP, ISN
Voltage range at VREG
Voltage range at BHx
Voltage range at GHx
Voltage range at GHx
Voltage range at SHx
Voltage range at SHx
Voltage range at GLx
Voltage range at GLx
V
VS
V
VSRP
V
DPO
V
OPI
V
VREG
V
BH
V
GH
V
GHP
V
SH
V
SHP
V
GL
V
GLP
V
VDH
V
RPP
I
RPP
V
ENA
V
SCDL
V
DPI
-0.3
-4.0
-0.3
-0.3
-25
-0.3
-0.3
-0.3
-0.3
-5.0
-0.3
-0.3
-0.3
-7.0
-2.0
-7.0
-0.3
-7.0
45
45
55
55
25
45
6
6
55
55
45
45
6
5.0
15
55
18
18
V
V
V
V
V
V
V
V
V
V
V
V
V
V
–
–
–
–
–
R
VS
≥10Ω
–
– mA –
V
V
V
–
–
–
–
t
P
<1µs;
f
=50kHz
–
t
P
<1µs;
f
=50kHz
–
t
P
<0.5µs;
f
=50kHz
4.1.19
4.1.20
Voltage range at SL
Voltage range at SL
V
SL
V
SLP
V
V
GS
BS
-1.0
-7.0
-0.3
-0.3
5.0
5.0
15
15
V
V
V
V
–
t
P
<0.5µs;
f
=50kHz;
C
BS
≥330nF
–
–
4.1.21
4.1.22
Voltage difference Gxx-Sxx
Voltage difference BHx-SHx
Temperatures
4.1.23
Junction temperature
4.1.24
4.1.25
4.1.26
Storage temperature
Lead soldering temperature
(1/16’’ from body)
Peak reflow soldering temperature
Power Dissipation
2)
4.1.27
Power Dissipation (DC)
ESD Susceptibility
4.1.28
ESD Resistivity
3)
T
j
T
stg
T
sol
T
ref
P
tot
V
ESD
-40
-55
–
–
–
–
150
150
260
260
2
2
°C
°C
°C
°C
W kV
–
–
–
–
–
Data Sheet 7 Rev 1.1, 2010-09-30
H-Bridge and Dual Half Bridge Driver IC
TLE7182EM
General Product Characteristics
Absolute Maximum Ratings (cont’d)
1)
40
°C ≤
T
j
≤ 150 °C ; all voltages with respect to ground, positive current flowing into pin (unless otherwise specified)
Pos.
Parameter Symbol Limit Values Unit Conditions
Min.
– kV 4.1.29
CDM
V
CDM
1) Not subject to production test, specified by design.
2) Reflow profile IPC/JEDEC J-STD-020C
3) ESD susceptibility HBM according to EIA/JESD 22-A 114B
Max.
1
Note: Stresses above the ones listed here may cause permanent damage to the device. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.
Note: Integrated protection functions are designed to prevent IC destruction under fault conditions described in the data sheet. Fault conditions are considered as “outside” normal operating range. Protection functions are not designed for continuous repetitive operation.
4.2
Functional Range
Pos.
4.2.1
4.2.2
4.2.3
4.2.4
4.2.5
4.2.6
Parameter
Specified supply voltage range supply voltage range
1)
Quiescent current at VS
Quiescent current at VS
Quiescent current at VDH
Quiescent current at VDH
Symbol
V
V
I
I
I
I
VS1
VS2
QVS1
QVS2
QVDH1
QVDH2
4.2.7
4.2.8
Supply current at Vs (device enabled)
2)
Supply current at Vs (device enabled)
4.2.9
D.C. switch on time of output stages
4.2.10
Duty cycle Highside output stage
3)
I
Vs(1)
I
Vs(2)
D
DC
D
HS
Min.
7.0
–
–
–
–
–
–
–
5.5
Limit Values
Max.
34
45
8
10
8
10
22
45
∞
Unit
V
V
µA
µA
µA
µA mA mA s
Conditions
–
V
VS
<7V reduced functionality
V
VS
,V
VDH
=12V;
ENA=Low; T j
=25°C
V
VS
,V
VDH
<15V;
ENA=Low; T j
≤85°C
V
VS
,V
VDH
=12V;
ENA=Low; T j
=25°C
V
VS
,V
VDH
<15V;
ENA=Low; T j
≤85°C no switching
4xQ
GS xf
PWM
; V
VS
=7.0..34V
–
0 95 %
4.2.11
Duty cycle Lowside output stage
D
LS
0 100
1) operation above 34V limited by max. allowed power dissipation and max. ratings
%
2) Current can be higher, if driver output stages are unsupplied
3) max. limit of D.C. will increase, if
f
PWM
or external gate charge of the MOSFETs is reduced
f
PWM
=20kHz; continuous operation;
C
BS
≥330nF
–
≤
20mA
The PWM frequency is limited by thermal constraints and the maximum duty cycle (minimum charging time of bootstrap capacitor).
Data Sheet 8 Rev 1.1, 2010-09-30
H-Bridge and Dual Half Bridge Driver IC
TLE7182EM
General Product Characteristics
Note: Within the functional range the IC operates as described in the circuit description. The electrical characteristics are specified within the conditions given in the related electrical characteristics table.
4.3
Thermal Resistance
Note: This thermal data was generated in accordance with JEDEC JESD51 standards. For more information, go to
www.jedec.org
.
Pos.
Parameter Symbol Limit Values Unit Conditions
Min.
Typ.
Max.
4.3.1
4.3.2
Junction to Case
1)
Junction to Ambient
R
thJC
R
thJA
–
–
–
35
5
–
K/W –
K/W
2)
1) Not subject to production test, specified by design.
2) Exposed Heatslug Package use this sentence: Specified
R
thJA
value is according to Jedec JESD51-2,-5,-7 at natural convection on FR4 2s2p board; The Product (Chip+Package) was simulated on a 76.2 x 114.3 x 1.5 mm board with 2 inner copper layers (2 x 70µm Cu, 2 x 35µm Cu). Where applicable a thermal via array under the exposed pad contacted the first inner copper layer.
4.4
Table 2
Default State of Inputs
Default State of Inputs (if left open)
Characteristic
Default state of IHx
Default state of ILx
Default state of ENA
State
High
Low
Low
Default state of SCDL OPEN
Remark
High side MOSFETs off
Low side MOSFETs off
Output stages disabled device in sleep mode
Short circuit detection deactivation & warning
Data Sheet 9 Rev 1.1, 2010-09-30
H-Bridge and Dual Half Bridge Driver IC
TLE7182EM
Description and Electrical Characteristics
5 Description and Electrical Characteristics
5.1
MOSFET Driver
5.1.1
Driving MOSFET Output Stages
The TLE7182EM incorporates 2 high side and low side output stages for 4 external MOSFETs.
Unlike other H-Bridge drivers the TLE7182EM offers 4 independent control inputs to control the MOSFETs individually. However, the control inputs for the Highs Side MOSFETs IHx are inverted. Hence, the control inputs for High Side IHx and Low Side MOSFETs ILx of the same half bridge can be tight together to control one half bridge by one control signal. To avoid shoot through currents within the half bridges, a minimum dead time is provided by the TLE7182EM. Minimum dead time is only generated, if the short circuit detection is activated.
If the TLE7182EM drives a load in between the high side MOSFET and the low side MOSFET or the driver is used to drive 4 low side MOSFETs, the short circuit detection and the minimum dead time has to be deactivated by pulling the SCDL pin to 5V.
For more details about the dead time please see
.
and
show the differed states of the output stages subject to the input conditions for activated and deactivated shout through protection.
Table 3 Truth table (shoot through active)
1
1
1
1
ENA IL1 IH1 IL2 IH2 Lowside switch1 Highside switch1 Lowside switch2 Highside switch2
0 x x x x OFF OFF OFF OFF
1 0 1 0 1 OFF OFF OFF OFF
0 0 0 0 OFF ON OFF ON
1
0
1
1
0
1
0
1
1
0
1
1
ON
OFF
ON
OFF
ON
OFF
OFF
ON
ON
ON
OFF
OFF
Table 4 Truth table (shoot through inactive)
1
1
1
1
1
ENA IL1 IH1 IL2 IH2 Lowside switch1 Highside switch1 Lowside switch2 Highside switch2
0 x x x x OFF OFF OFF OFF
0
0
1
0
0
0
1
1
OFF
OFF
OFF
ON
OFF
OFF
OFF
OFF
1
0
0
0
1
1
0
0
1
1
0
0
ON
OFF
OFF
ON
OFF
OFF
OFF
OFF
ON
OFF
ON
ON
5.1.2
MOSFET Output Stages
The six push-pull MOSFET driver stages of the TLE7182EM are realized as separate floating blocks. This means that the output stage is follows the individual MOSFET source voltages and so ensuring stable MOSFET driving even in harsh electrical environment.
All 4 output stages have the same output power and thanks to the used bootstrap principle they can be switched all up to high frequencies.
Each output stage has its own short circuit detection block. For more details about short circuit detection see
Data Sheet 10 Rev 1.1, 2010-09-30
H-Bridge and Dual Half Bridge Driver IC
TLE7182EM
Description and Electrical Characteristics
VS ENA VDH
Voltage regulator
VREG
BHx
RPP
Charge pump
____
ERR
+
-
GHx
Error logic
Reset
Power On Reset
V RE G
V DH
V
S CP lock / unloc k
S CD
Level shifter
Floating HS driver 2x
VREG
SHx blanking
Short Circuit
Detection Level
S CD
S CD short circuit filter
GLx
Input Logic
Shoot Through
Protection
Dead Time
+
-
IH2
IH1
IL2
IL1
ON / OFF
ON / OFF
Level shifter
V
S CP
Floating LS driver 2x
SL
GND
SCDL
Block Diagram of Driver Stages including Short Circuit Detection Figure 3
5.1.3
Dead Time and Shoot Through Protection
In bridge applications it has to be assured that the external high side and low side MOSFETs are not “on” at the same time, connecting directly the battery voltage to GND.
In TLE7182EM a minimum dead time applied. It is fixed internally and can not be programmed.
If an exact dead time of the bridge is needed, the use of the µC PWM generation unit is recommended.
In addition to this dead time, the TLE7182EM provides a locking mechanism, avoiding that both external
MOSFETs of one half bridge can be switched on at the same time. This functionality is called shoot through protection. If the command to switch on both high and low side switches in the same half bridge is given at the input pins, the command will be ignored. The outputs will stay in the situation like before the conflicting input.
The Shoot through protection and the dead time of the TLE7182EM will be deactivated, if a voltage of 5V is applied at pin SCDL. The deactivation of the shoot through protection is necessary to drive valves or solenoids which are designed in between the Lowside and Highside MOSFET of one half bridge or 4 separate low side MOSFETs.
For more detailed information how to drive valves or solenoid in between one half bridge please see
5.1.4
Bootstrap Principle
The TLE7182EM provides a bootstrap based supply for its high side output stages.
The bootstrap capacitors are charged by switching on the external low side MOSFETs, connecting the bootstrap capacitor to GND. Under this condition the bootstrap capacitor will be charged from the VREG capacitor via the integrated bootstrap diode. If the low side MOSFET is switched off and the high side MOSFET is switched on, the bootstrap capacitor will float together with the SHx voltage to the supply voltage of the bridge. Under this condition the supply current of the high side output stage will discharge the bootstrap capacitor. This current is specified.
Data Sheet 11 Rev 1.1, 2010-09-30
H-Bridge and Dual Half Bridge Driver IC
TLE7182EM
Description and Electrical Characteristics
The size of the capacitor together with this current will determine how long the high side MOSFET can be kept on without recharging the bootstrap capacitor.
5.1.5
100% D.C. charge pumps
100% D.C. charge pumps are implemented for each high side output stage. Therefore the high side output stages can be switch on for an unlimited time. These integrated charge pumps can handle leakage currents which will be caused by external MOSFETs and the TLE7182EM itself. They are not strong enough to drive a 99% duty cycle for a longer time. the charge pumps are running when the driver is not in sleep mode and assure that the bootstrap capacitors are charged as long as the user does not apply critical duty cycle for a longer time.
5.1.6
Reverse polarity protection of motor bridge
The TLE7182EM provides an additional RPP pin to protect motor bridge for reverse polarity. This RPP pin can drive an additional external N-channel power MOSFET designed in between battery and the motor bridge. The
RPP pin is internally supplied by the two integrated 100% D.C. charge pumps. They are especially designed to handle additional current which is needed to drive a the gate charge of the reverse polarity MOSFET. The guarantied output current of the charge pumps is specified.
5.1.7
Sleep mode
If ENA pin is set to low, the ERR flag will be set to low and the output stages will be switched off.
After ENA pin is kept low for t
LQM the sleep mode of the Driver IC will be activated.
In Sleep mode the complete chip is deactivated. This means the internal supply structure of the TLE7182EM will be switched off. This mode is designed for lowest current consumption from the power net of the car. The passive clamping is active. For details see the description of passive clamping, see
The TLE7182EM will wake up, if ENA is set to high.The ENA pin is 45V compatible, so ENA can be directly be connected to the ignition key signal KL15.
5.1.8
Electrical Characteristics
Electrical Characteristics MOSFET Drivers
V
S
= 7.0 to 34V,
T
j
= -40 to +150
°C all voltages with respect to ground, positive current flowing into pin
(unless otherwise specified)
Pos.
Parameter Symbol
Min.
Limit Values
Typ.
Max.
Unit Conditions
Control inputs
5.1.1
Low level input voltage of Ixx
5.1.2
High level input voltage of Ixx
5.1.3
5.1.4
Input hysteresis of Ixx
ILx pull-down resistor to GND
V
V
I_LL
I_HL
d
VI
R
IL
–
2.0
100
320
–
–
200
540
1.0
–
–
770
V
V mV k
Ω
–
–
5.1.5
5.1.6
5.1.7
5.1.8
ILx pull-down resistor to GND
IHx pull-up resistor to internal VDD
Low level input voltage of ENA
High level input voltage of ENA
5.1.9
Input hysteresis of ENA
5.1.10
ENA pull-down resistor to GND
R
R
V
V
IL
IH
E_LL
E_HL
d
VE
R
IL
19
30
–
2.1
50
70
–
–
32
–
200
125
50
80
0.75
–
–
200
V
V k
Ω k
Ω mV k
Ω
–
–
–
–
–
V
VS
=0V and
VDH=0V or open
V
VS
or VDH >5.0V
–
Data Sheet 12 Rev 1.1, 2010-09-30
H-Bridge and Dual Half Bridge Driver IC
TLE7182EM
Description and Electrical Characteristics
Electrical Characteristics MOSFET Drivers
V
S
= 7.0 to 34V,
T
j
= -40 to +150
°C all voltages with respect to ground, positive current flowing into pin
(unless otherwise specified)
Pos.
Parameter Symbol
Min.
Limit Values
Typ.
Max.
Unit Conditions
MOSFET driver output
5.1.11
5.1.12
Output source resistance
Output sink resistance
5.1.13
High level output voltage Gxx vs.
Sxx
5.1.14
High level output voltage Gxx vs.
Sxx
5.1.15
High level output voltage GHx vs.
SHx
1)
5.1.16
High level output voltage GLx vs.
GND
5.1.17
High level output voltage GHx vs.
SHx
5.1.18
High level output voltage GHx vs.
SHx
5.1.19
High level output voltage GLx vs.
5.1.20
High level output voltage GHx vs.
SHx
5.1.21
High level output voltage GLx vs.
5.1.22
Rise time
5.1.23
Fall time
t t
R
R
V
V
V
V
V
V
V
V
V
Sou
Sink
Gxx1
Gxx2
GHx3
GLx3
GHx4
GHx5
GLx5
GHx5
GLx5 rise fall
2
2
–
–
–
–
5.0
+
V
diode
5.0
6.0
10
6.5
–
–
–
–
11
11
V
V
–
–
–
–
–
13.5
9.0
15
13.5
VS
-1.5 –
VS
-0.5 –
250
200
–
–
–
–
–
–
–
Ω
Ω
V
V
V
V
V
V
V
V
V ns ns
I
Load
=-20mA
I
Load
=20mA
I
13.5V
≤V
VS
Load
=0mA
≤
34V;
13.5V
C
Load
≤V
VS
≤
=20nF;
34V;
D.C.=50%;
f
PWM
=20kHz
7.0V<V
C
VS
<13.5V;
Load
=20nF;
D.C.=50%;
f
PWM
=20kHz
f
7.0V<V
VS
<13.5V;
C
Load
=20nF;
PWM
=20kHz &
D.C.=50%; or D.C=100%
V
C
VS
=7.0V;
Load
=20nF;
D.C.=95%;
f
PWM
=20kHz; passive freewheeling
V
C
VS
=7.0V;
Load
=20nF;
D.C.=95%;
f
PWM
=20kHz
V
C
VS
=7.0V;
Load
=20nF;
D.C.=95%;
f
PWM
=20kHz
7.0V
C
Load
≤V
VS
≤
13.5V;
=20nF;
D.C.=100%
V
C
VS
=7.0V;
Load
=20nF;
D.C.=100%
C
R
V
Load
=11nF;
Load
=1
Ω;
VS
=7V;
20-80%
Data Sheet 13 Rev 1.1, 2010-09-30
H-Bridge and Dual Half Bridge Driver IC
TLE7182EM
Description and Electrical Characteristics
Electrical Characteristics MOSFET Drivers
V
S
= 7.0 to 34V,
T
j
= -40 to +150
°C all voltages with respect to ground, positive current flowing into pin
(unless otherwise specified)
Pos.
Parameter Symbol Unit Conditions
5.1.24
High level output voltage (in
5.1.25
Pull-down resistor at BHx to GND
5.1.26
Pull-down resistor at VREG to GND
5.1.27
Bias current into BHx
5.1.28
Bias current out of SHx
5.1.29
Bias current out of SL
I
I
I
V
R
R
GxxUV
BHUVx
VRUV
BHx
SHx
SL
Min.
–
–
–
–
–
–
Limit Values
Typ.
–
Max.
1.2
–
–
–
40
–
85
30
150
–
1.4
V k
Ω k
Ω
µA
µA mA
Sleep mode or
VS_UVLO
Sleep mode or
VS_UVLO
Sleep mode or
VS_UVLO
V
CBS
>5V; no switching
V
SHx
=
V
SL
;
ENA=HIGH; affected highside output stage static on;
V
CBS
>5V
0≤V
SHx
≤
V
VS
+1V;
ENA=HIGH; no switching;
V
CBS
>5V
Dead time & input propagation delay times
5.1.30
Min. internal dead time
5.1.31
Dead time deviation between channels
t
DT_MIN
d
tDT2
5.1.32
Dead time deviation between channels LSoff -> HS on
d
tDT2
5.1.33
Dead time deviation between channels HSoff -> LS on
d
tDT2
5.1.34
Input propagation time (low on)
5.1.35
Input propagation time (low off)
5.1.36
Input propagation time (high on)
5.1.37
Input propagation time (high off)
5.1.38
Absolute input propagation time difference between above propagation times
t
P(ILN)
t
P(ILF)
t
P(IHN)
t
P(IHF)
t
P(diff)
VREG
5.1.39
VREG output voltage
V
VREG
5.1.40
VREG over current limitation
5.1.41
Voltage drop between Vs and
VREG
I
V
VREGOCL
VsVREG
0
0
0
0
0.08
-15
-12
-12
–
11
100
–
–
–
50
12.5
–
–
0.11
–
100
100
100
100
0.2
15
12
12
200
200
200
200
100
14
500
0.5
µs
%
%
% ns ns ns ns ns
V mA
V
–
–
–
–
C
R
Load
=10nF;
Load
=1
Ω
I
V
VS
≥13.5V;
Load
=-35mA
–
3)
V
VS
≥7V;
I
Load
=-35mA;
Ron operation
Data Sheet 14 Rev 1.1, 2010-09-30
H-Bridge and Dual Half Bridge Driver IC
TLE7182EM
Description and Electrical Characteristics
Electrical Characteristics MOSFET Drivers
V
S
= 7.0 to 34V,
T
j
= -40 to +150
°C all voltages with respect to ground, positive current flowing into pin
(unless otherwise specified)
Pos.
Parameter Symbol
Min.
Limit Values
Typ.
Max.
Unit Conditions
100% D.C. charge pump
5.1.42
Charge pump frequency
f
CP
Motor bridge reverse polarity protection output
5.1.43
High level output voltage RPP vs.
VS
V
RPP1
5.1.44
High level output voltage RPP vs.
VS
V
RPP2
5.1.45
D.C. output current at RPP
I
RPP1
–
–
–
21
11
11
–
15
12.5
MHz –
V
V
I
Load
=0µA
I
Load
≥-30µA
5.1.46
Rise time
5.1.47
Rise time
ENA and Low quiescent current mode
5.1.48
ENA propagation time to output stages switched off
5.1.49
Low time of ENA signal without clearing error register
t
RPPrise
t
RPPrise
t
PENA_H-L
t
RST0
–
–
–
–
–
-110
1
10
2.0
–
-150
2
20
3.0
1.2
µA ms
µs
µs
µs
V
RPP
≥10V;
Lowside on
C
LOAD
=10nF
C
LOAD
=100pF
–
–
5.1.50
High time of ENA signal after ENA rising edge for error logic active
t
RST1
4 5.75
7 µs –
5.1.51
go to sleep time
t
sleep
310 415 540 µs –
5.1.52
wake up time
t
wake
– 50 100 µs
C
C
REG
=2.2µF;
BS
=330nF
1) Not subject to production test, specified by design.
2)
V
diode
is the bulk diode of the external low side MOSFET
3) normally no error flag; Error flag might by triggered by under voltage VREG caused by very high load current
Data Sheet 15 Rev 1.1, 2010-09-30
H-Bridge and Dual Half Bridge Driver IC
TLE7182EM
5.2
Protection and Diagnostic Functions
5.2.1
Short Circuit Protection
The TLE7182EM provides a short circuit protection for the external MOSFETs by monitoring the drain-source voltage of the external MOSFETs.
This monitoring of the short circuit detection for a certain external MOSFET is active as soon as the corresponding driver output stage is set to “on” and the dead time and the blanking time are expired.
The blanking time starts when the dead time has expired and assures that the switch on process of the MOSFET is not taken into account. It is recommended to keep the switching times of the MOSFETs below the blanking time.
The short circuit detection level is adjustable in an analog way by the voltage setting at the SCDL pin. There is a
1:1 translation between the voltage applied to the SCDL pin and the drain-source voltage limit. E.g. to trigger the
SCD circuit at 1 V drain-source voltage, the SCDL pin must be set to 1 V. The drain-source voltage limit can be chosen between 0.2 ... 2 V.
If after the expiration of the blanking time the drain source voltage of the observed MOSFET is still higher then the
SCDL level, the SCD filter time
t
SCP
starts to run. A capacitor is charged with a current. If the capacitor voltage reaches a specific level (filter time
t
SCP
), the error signal is set and the IC goes into SCDL Error Mode. If the SCD condition is removed before the SC is detected, the capacitor is discharged with the same current. The discharging of the capacitor happens as well when the MOSFET is switched off. It has to be considered that the high side and the low side output of one phase are working with the same capacitor.
The Short Circuit protection of the TLE7182EM will be deactivated, if 5V is applied at pin SCDL.
5.2.2
SCDL Pin Open Detection
An integrated structure at the SCDL pin assures that in case of an open pin the SCDL voltage is pulled to a medium voltage level. The external MOSFETs are actively switched off and an ERR flag is set. This error is self-clearing.
5.2.3
Vs and VDH Over Voltage Warning
The TLE7182EM has an integrated over voltage warning to minimize risk of destruction of the IC at high supply voltages caused by violation of the maximum ratings. For the over voltage warning the voltage is observed at the pin VS and VDH. If the voltage level has reached, the fixed over voltage threshold
V
OVW
for the filter time
t
OV, a warning at ERR pin is set and TLE7182EM will go in normal operation with warning.
The over voltage warning is self clearing. If the voltage at pin VS and VDH returns into the specified voltage range, the Error register will be cleared and TLE7182EM returns to normal operation mode.
It is the decision of the user, if and how to react on the over voltage warning.
5.2.4
VS Under Voltage Shutdown
The TLE7182EM has an integrated VS Under Voltage Shutdown, to assure that the behavior of the complete IC is predictable in all supply voltage ranges. As soon as the under voltage threshold
V
UVVR is reached for a specified filter time the TLE7181EM is in VS_UVLO error mode. The error signal will be set and output stages, voltage regulator and charge pump will be switched off so the IC will go into sleep mode. An enable is necessary to restart the TLE7181EM.
5.2.5
VREG Under Voltage Warning
The TLE7182EM has an integrated under voltage warning detection at VREG. If the supply voltage at VREG reaches the VREG under voltage threshold
V
UVVR
, a warning at ERR pin is set and the TLE7182EM will go into
VREG error mode. In case of VREG error mode all output stages will actively switched off to prevent low gate source voltages at the power MOSFETs causing high RDSon. If supply voltage at the VREG pin recovers; the error flag will be cleared and the TLE7182EM will return in normal operation mode.
Data Sheet 16 Rev 1.1, 2010-09-30
H-Bridge and Dual Half Bridge Driver IC
TLE7182EM
5.2.6
Over Temperature Warning
The TLE7182EM provides an integrated digital over temperature warning to minimize risk of destruction of the IC at high temperature. The temperature will be detected by a embedded sensor. During over temperature warning the ERR signal is set and the TLE7182EM is in normal operation mode with warning.
The over temperature warning is self clearing. So if temperature is below
T
j(PW)
-dT j(OW)
, the warning will be cleared and TLE7182EM returns to normal operation mode.
It is the decision of the user to react on the over temperature warning.
5.2.7
Over Current Warning
The TLE7182EM offers an integrated over current detection. The output signal of the current sense OpAmp will be monitored. If the output signal reaches the specified voltage threshold be detected. After the comparator the filter time
t
V
OCTH
for a certain time, over current will
OC
is implemented to avoid false triggering caused by overswing of the current sense signal. The ERR pin will be set to low and the TLE7182EM will go into normal operation mode with warning.
The error signal disappears as soon as the current decreases below the over current threshold
V
OCTH
. The error signal disappears as well when the current commutates from the low side MOSFET to the associated high side
MOSFET and is no longer flowing over the shunt resistor.
It is the decision of the user to react on the over current signal by modifying input patterns.
5.2.8
Passive Gxx Clamping
If VS Under Voltage shutdown is detected or the device is in Sleep Mode, a passive clamping is active as long as the voltage at VS or VDH is higher than 3V. Even below 3V it is assured that the MOSFET driver stage will not switch on the MOSFET actively.
The passive clamping means that the BHx and the VREG pin are pulled to GND with specified pull down resistors.
Together with the intrinsic diode of the push stage of the output stages which connect the gate output to BHx respectively VREG, this assures that the gate of the external MOSFETs are not floating undefined.
5.2.9
ERR Pin
The TLE7182EM has a status pin to provide diagnostic feedback to the µC. The logical output of this pin is a push
pull output stage with an integrated pull-down resistor to GND (see
Reset of error registers and Disable
The TLE7182EM can be reset by the enable pin ENA. If the ENA pin is pulled to low for a specified minimum time, the error registers are cleared. ERR output is still set to low. After the next rising edge at ENA pin ERR pin will be set to high and no error condition is applied.
Data Sheet 17 Rev 1.1, 2010-09-30
H-Bridge and Dual Half Bridge Driver IC
TLE7182EM
µC
TLE718xEM
Internal
5V
internal
Error
Logic
ERR
Interface_ µC
GND GND
Figure 4 Structure of ERR output
Table 5 Overview of error condition
ERR
High
Low
Low
Low
Low
Low
Low
Low
Low
Low
Driver conditions
no errors
Over temperature
Over voltage VS/VDH
Over current OPAMP
Under voltage error VREG
Under voltage shutdown based on VS
SCDL open pin
Short circuit detection
Go to sleep mode
Wake up mode
1) When SC detected, reset with ENA necessary
Driver action
Fully functional
Warning only
Warning only
Warning only
All MOSFETs actively switched off
MOSFET, charge pump,
Vreg switched off
All MOSFETs actively switched off
All MOSFETs actively switched off
All MOSFETs actively switched off start up
Table 6
Priority
0
1
2
Prioritization of Errors
Errors and Warnings
Under voltage lockout at Vs (VS_UVLO)
Short circuit detection error (SCD)
SCDL pin open warning (SCDLPOD)
Under voltage detection VREG (UV_VREG)
Over voltage detection warning (OVD)
Over temperature warning (OTD)
Over current warning (OCD)
Restart
–
Self clearing
Self clearing
Self clearing
Self clearing
Self clearing restart when enable high
1)
Self clearing
Reset at ENA needed immediate restart when
ENA goes high
–
Data Sheet 18 Rev 1.1, 2010-09-30
H-Bridge and Dual Half Bridge Driver IC
TLE7182EM
5.2.10
Electrical Characteristics
Electrical Characteristics - Protection and diagnostic functions
V
S
= 7.0 to 34V,
T
j
= -40 to +150
°C , all voltages with respect to ground, positive current flowing into pin
(unless otherwise specified)
Pos.
Parameter Symbol
Min.
Limit Values
Typ.
Max.
Unit Conditions
Short circuit protection
5.2.1
Short circuit protection detection level input range
5.2.2
Short circuit protection detection accuracy
V
A
SCDL
SCP1
0.2
-50
–
–
2.0
+50
V
% programmed by
SCDL pin
0.2V
≤
V
SCDL
≤
0.3V
5.2.3
A
SCP2
-30 – +30 % 0.3V
≤
V
SCDL
≤
1.2V
5.2.4
5.2.5
5.2.6
5.2.7
5.2.8
Short circuit protection detection accuracy
Short circuit protection detection accuracy
Filter time of short circuit protection
Filter time and blanking time of short circuit protection
Internal pull-up resistor SCDL to 3V
SCDL open pin detection level
5.2.9
Filter time of SCDL open pin detection
5.2.10
SCDL open pin detection level hysteresis
1)
5.2.11
Threshold voltage for deactivation of:
- SC detection
- dead-time generation
- shoot-through protection
5.2.12
Filter time of SCD deactivation
t t t
A
R
V t
SCPOP
V
V
SCP3
SCP(off)
SCPBT
SCDL
SCPOP
SCOPH
SCPDIS
SCPDIS
-10
2.5
4
180
2.1
1.5
–
4.5
1.0
–
3.5
6
300
–
2.5
0.3
–
2.0
+10
4.5
8
475
3.2
3.5
–
–
3.1
%
µs
µs k
Ω
V
µs
V
V
µs
1.2V
–
–
–
–
–
–
–
–
≤
V
SCDL
≤
2.0V
Over- and under voltage monitoring
5.2.13
Over voltage warning at Vs and/or
VDH
V
OVW
34.5
36.5
38.5
V
V
VS
and/or increasing
V
VDH
V
OVWhys
2.1
3.1
4.1
V – 5.2.14
Over voltage warning hysteresis for
Vs and/or VDH
5.2.15
Over voltage warning filter time for
Vs and/or VDH
5.2.16
Under voltage shutdown at Vs
5.2.17
Under voltage shutdown filter time for VS
5.2.18
Under voltage warning at VREG
5.2.19
Under voltage diagnosis filter time for VREG
5.2.20
Under voltage hysteresis at VREG
t
OV
V
UVVR
t
UVLO
V
UVVR
t
UVVR
V
UWRhys
13
4.5
–
5.5
10
–
19
5.0
20
6.0
–
0.5
25
5.5
–
6.5
30
–
µs
V
µs
V
µs
V
–
V
VS
decreasing
–
V
VS
decreasing
–
–
Data Sheet 19 Rev 1.1, 2010-09-30
H-Bridge and Dual Half Bridge Driver IC
TLE7182EM
Electrical Characteristics - Protection and diagnostic functions
(cont’d)
V
S
= 7.0 to 34V,
T
j
= -40 to +150
°C , all voltages with respect to ground, positive current flowing into pin
(unless otherwise specified)
Pos.
Parameter Symbol
Min.
Limit Values
Typ.
Max.
Unit Conditions
Temperature monitoring
5.2.21
Over temperature warning
5.2.22
Hysteresis for over temperature warning
T
j(PW)
dT
j(OW)
160
10
170
–
180
20
°C
°C
–
–
Over current detection
5.2.23
Over current detection level
5.2.24
Filter time for over current detection
ERR pin
2)
V
OCTH
t
OC
4.5
2.3
–
–
4.99
4.3
V
µs
–
–
5.2.25
ERR output voltage
5.2.26
Rise time ERR (20 - 80% of internal
5V)
V
ERR
t
f(ERR)
4.6
–
–
–
–
3
V
µs
V
VS
=7V;
C
LOAD
=1nF;
5.2.27
Internal pull-down resistor ERR to
GND
R
f(ERR)
60 100 170 k
Ω
–
1) Not subject to production test, specified by design.
2) ERR pin and Reset & Enable functional between
V
VS
=6 ... 7V, but characteristics might be out of specified range
Data Sheet 20 Rev 1.1, 2010-09-30
H-Bridge and Dual Half Bridge Driver IC
TLE7182EM
5.3
Shunt Signal Conditioning
The TLE7182EM incorporates a fast and precise operational amplifier for conditioning and amplification of the current sense shunt signal. The gain of the OpAmp is adjustable by external resistors within a range higher than 5.
The usage of higher gains in the application might be limited by required settling time and band width.
It is recommended to apply a small offset to the OpAmp, to avoid operation in the lower rail at low currents.
The output of the OpAmp ISO is not short-circuit proof.
V
DD
R
REF1
R shunt
R
S1
R
S2 external
R
REF2
ISP
ISN
TLE718xEM
+
-
ERR
+
-
V
OCTH
ISO
Figure 5
.
R
FB
R
FB
=(R
REF1
||R
REF2
Shunt Signal Conditioning Block Diagram and Over Current Limitation
)
5.3.1
Electrical Characteristics
Electrical Characteristics - Current sense signal conditioning
V
S
= 7.0 to 36V,
T
j
= -40 to +150
°C, gain = 5 to 75, all voltages with respect to ground, positive current flowing into pin
(unless otherwise specified)
Pos.
Parameter Symbol Unit Conditions
5.3.1
5.3.2
Series resistors
Feedback resistor
Limited by the output voltage dynamic range
R
R
S fb
Min.
100
2000
Limit Values
Typ.
Max.
500 1000
7500 –
Ω
Ω
–
–
5.3.3
5.3.4
Resistor ratio (gain ratio)
Steady state differential input voltage range across VIN
R
fb/RS
V
IN(ss)
5
-400
–
–
–
400
– mV
–
–
5.3.5
5.3.6
Input differential voltage (ISP - ISN)
Input voltage (Both Inputs - GND)
(ISP - GND) or (ISN -GND)
V
IDR
V
LL
-800
-800
–
–
800
2000 mV mV
–
–
5.3.7
5.3.8
5.3.9
Input offset voltage of the I-DC link
OpAmp, including temperature drift
Input bias current (ISN,ISP to GND)
Low level output voltage of ISO
I
V
V
IO
IB
OL
–
-300
-0.1
–
–
–
+/-2
–
0.2
mV
µA
V
R
V
S
=500
Ω;
V
ISO
=1.65V;
CM
=0V;
V
CM
=0V;
V
ISO
=open
I
OH
=3mA
Data Sheet 21 Rev 1.1, 2010-09-30
H-Bridge and Dual Half Bridge Driver IC
TLE7182EM
Electrical Characteristics - Current sense signal conditioning (cont’d)
V
S
= 7.0 to 36V,
T
j
= -40 to +150
°C, gain = 5 to 75, all voltages with respect to ground, positive current flowing into pin
(unless otherwise specified)
Pos.
Parameter Symbol Unit Conditions
5.3.10
High level output voltage of ISO
V
OH
Min.
4.75
Limit Values
Typ.
–
Max.
5.2
V
I
OH
=-3mA
5.3.11
Output short circuit current
5.3.12
Differential input resistance
1)
5.3.13
Common mode input capacitance
I
SCOP
R
I
C
CM
C
MRR
5
100
–
–
–
–
–
–
10 mA k
Ω pF
–
–
10kHz
5.3.14
Common mode rejection ratio at
DC
CMRR =
20*Log((Vout_diff/Vin_diff) *
(Vin_CM/Vout_CM))
5.3.15
Common mode suppression
2)
with
CMS = 20*Log(Vout_CM/Vin_CM)
Freq =100kHz
Freq = 1MHz
Freq = 10MHz
C
MS
80
–
100
62
43
23
–
– dB dB
–
V
IN
=360mV* sin(2*
π*freq*t);
R
s
R
fb
=500
Ω;
=7500
Ω
5.3.16
Slew rate
d
V/dt
– 10 – V/µs Gain
≥ 5;
R
C
L
=1.0k
Ω;
L
=500pF dB – 5.3.17
Large signal open loop voltage gain
(DC)
A
OL
80 100 –
5.3.18
5.3.19
Phase margin
G
F
BW
M
10
–
20
50
–
–
MHz
°
R
L
=1k
Ω;
C
L
=100pF
Gain
≥ 5;
R
L
=1k
Ω;
C
L
=100pF
R
L
=1k
Ω;
C
L
=100pF 5.3.20
Gain margin
5.3.21
Bandwidth
5.3.22
Output settle time to 98%
t
A
M
B
WG set1
–
0.7
–
12
1.3
1
–
–
1.8
dB
MHz Gain=15;
R
C
L
=1k
Ω;
R
s
L
=500pF;
=500
Ω
µs Gain=15;
R
C
R
L
=1k
Ω;
L
=500pF;
0.3< s
V
ISO
=500
Ω
< 4.8V;
5.3.23
Output settle time to 98%
t
set2
– 4.6
– µs Gain=75;
R
C
L
=1k
Ω;
0.3<
R
s
L
=500pF;
V
ISO
=500
Ω
< 4.8V;
1) Not subjected to production test; specified by design
2) Without considering any offsets such as input offset voltage, internal mismatch and assuming no tolerance error in external resistors.
Data Sheet 22 Rev 1.1, 2010-09-30
H-Bridge and Dual Half Bridge Driver IC
TLE7182EM
Application Information
6 Application Information
Note: The following information is given as a hint for the implementation of the device only and shall not be regarded as a description or warranty of a certain functionality, condition or quality of the device.
This is the description how the IC is used in its environment…
L
2,2µH
V
BAT
R
VS
C
VS1
2,2µF
PGND
C
VS2
10nF C
REG2
10nF
PGND
C
REG1
2,2µF
GND
R
G
R
RPS
4.7k
Ω
R
VDH
VS VREG
RPP
IL1
___
IH1
IL2
___
IH2
ENA
____
ERR
TLE
7182EM
VDH
BH1
GH1
SH1
BH2
GH2
SH2
C
BS1
330nF
T
HS1
R
GH1
C
BS2
330nF
C
SNH1
R
SNH1
C
C1
+
C
B1
PGND
T
HS2
R
GH2
C
SNH2
R
SNH2
C
C2
+
C
B2
PGND
M
µC e.g.:
XC2xxx
GND
R
SC1
V
DD
R
SC2
SCDL
R
ISO
C
ISO
100pF
ISO
GND
GL1
R
GL1
T
LS 1
C
SNL1
R
SNL1
GL2
SL
V ref
R
REF1
ISP
ISN
R
FB
R
S2
C
IS
50pF
R
REF2
GND
R
S1
R
FB
= (R
REF1
||R
REF2
)
R
GL2
Shunt
T
LS 2
C
SNL2
R
SNL2
Figure 6
GND
GND
PGND
Application Diagram 1: DC-Brush motor controlled by TLE7182EM
Data Sheet 23 Rev 1.1, 2010-09-30
µC e.g.:
XC2xxx
GND
H-Bridge and Dual Half Bridge Driver IC
TLE7182EM
Application Information
L
2,2µH
V
BAT
R
VS
C
VS1
2,2µF
PGND
C
VS2
10nF C
REG2
10nF
PGND
C
REG1
2,2µF
GND
R
G
R
RPS
4.7k
Ω
R
VDH VS VREG
RPP
ENA
____
ERR
IH1
IL2
___
IH2
TLE
7182EM
VDH
BH1
GH1
SH1
BH2
GH2
SH2
C
BS1
330nF
T
HS1
R
GH1
C
BS2
330nF
V
C
SNH1
R
SNH1
C
C1
+
C
B1
PGND
T
HS2
R
GH2
C
SNH2
R
SNH2
C
C2
+
C
B2
PGND
R
SC1
V
DD
R
SC2
SCDL
R
ISO C
ISO
100pF
ISO
GND
GL1
R
GL1
T
LS 1
C
SNL1
R
SNL1
GL2
SL
V ref
R
REF1
ISP
ISN
R
FB
R
S2
C
IS
50pF
R
REF2
GND
R
S1
R
FB
= (R
REF1
||R
REF2
)
R
GL2
Shunt
T
LS 2
V
C
SNL2
R
SNL2
GND
GND
PGND
Figure 7 Application Diagram 2: 2 inductive loads driven by TLE7182EM
Note: This are very simplified examples of an application circuit. The function must be verified in the real application.
Data Sheet 24 Rev 1.1, 2010-09-30
H-Bridge and Dual Half Bridge Driver IC
TLE7182EM
Application Information
6.1
Layout Guide Lines
Please refer also to the simplified application example.
• Two separated bulk capacitors C
B
should be used - one per half bridge
• Two separated ceramic capacitors C
C
should be used - one per half bridge
• Each of the two bulk capacitors C
B
and each of the two ceramic capacitors C
C should be assigned to one of the half bridges and should be placed very close to it
• The components within one half bridge should be placed close to each other: high side MOSFET, low side
MOSFET, bulk capacitor C
B
and ceramic capacitor C
C
(C
B
and C
C
are in parallel) and the shunt resistor form a loop that should be as small and tight as possible. The traces should be short and wide
• The connection between the source of the high side MOSFET and the drain of the low side MOSFET should be as low inductive and as low resistive as possible.
• VDH is the sense pin used for short circuit detection; VDH should be routed (via Rvdh) to the common point of the drains of the high side MOSFETs to sense the voltage present on drain high side
• SL is the sense pin used for short circuit detection; SL should be routed o the common point of the source of the low side MOSFETs to sense the voltage present on source low side
• Additional R-C snubber circuits (R and C in series) can be placed to attenuate/suppress oscillations during switching of the MOSFETs, there may be one or two snubber circuits per half bridge, R (several Ohm) and C
(several nF) must be low inductive in terms of routing and packaging (ceramic capacitors)
• if available the exposed pad on the backside of the package should be connected to GND
6.2
Further Application Information
• For further information you may contact
http://www.infineon.com/
Data Sheet 25 Rev 1.1, 2010-09-30
H-Bridge and Dual Half Bridge Driver IC
TLE7182EM
Package Outlines
7 Package Outlines
0.25
±0.05
2)
0.65
+0 -0.1
C
0.2
M
C A-B D 24x
0.35 x 45˚
2x
0.1
C D
3.9
±0.1
1)
+0.06
0.19
0.08 C
Seating Plane
D
6
±0.2
0.64
±0.25
0.2
M
D
24
A
13
Bottom View
1 12
1
24
12
B
6.4
±0.25
0.1
C A-B 2x
8.65
±0.1
Index Marking
1) Does not include plastic or metal protrusion of 0.15 max. per side
2) Does not include dambar protrusion of 0.13 max.
13
PG-SSOP-24-4-PO V01
Figure 8 PG-SSOP-24-4
Green Product (RoHS compliant)
To meet the world-wide customer requirements for environmentally friendly products and to be compliant with government regulations the device is available as a green product. Green products are RoHS-Compliant (i.e
Pb-free finish on leads and suitable for Pb-free soldering according to IPC/JEDEC J-STD-020).
For further information on alternative packages, please visit our website:
http://www.infineon.com/packages
.
Data Sheet 26
Dimensions in mm
Rev 1.1, 2010-09-30
H-Bridge and Dual Half Bridge Driver IC
TLE7182EM
Revision History
8
Revision
1.1
1.0
0.8
0.7
0.6
Revision History
Date Changes
2010-09-30 Datasheet
Max rating of current at RPP pin increased
2010-09-29 Datasheet
Thermal resistance of package adjusted
Output rise time adjusted
Pull up and pull down resistor values adapted
Dead time values centered
Go to sleep time modified
Filter time of short circuit detection adjusted
SCDL pin open detection description improved
Overview of error condition table improved
Filter time and blanking time of short circuit detection adjusted
SCDL open pin detection level added
Filter time of SCDL open pin detection adjusted
Over voltage warning at Vs and/or VDH centered
Over voltage warning hysteresis for Vs and/or VDH centered
Over voltage warning filter time for Vs and/or VDH centered
ERR output voltage added
OpAmp bandwidth adjusted
2010-08-31
2009-11-19 Target data sheet
2008-30-10
Data Sheet 27 Rev 1.1, 2010-09-30
Edition 2010-09-30
Published by
Infineon Technologies AG
81726 Munich, Germany
©
2010 Infineon Technologies AG
All Rights Reserved.
Legal Disclaimer
The information given in this document shall in no event be regarded as a guarantee of conditions or characteristics. With respect to any examples or hints given herein, any typical values stated herein and/or any information regarding the application of the device, Infineon Technologies hereby disclaims any and all warranties and liabilities of any kind, including without limitation, warranties of non-infringement of intellectual property rights of any third party.
Information
For further information on technology, delivery terms and conditions and prices, please contact the nearest
Infineon Technologies Office (
www.infineon.com
).
Warnings
Due to technical requirements, components may contain dangerous substances. For information on the types in question, please contact the nearest Infineon Technologies Office.
Infineon Technologies components may be used in life-support devices or systems only with the express written approval of Infineon Technologies, if a failure of such components can reasonably be expected to cause the failure of that life-support device or system or to affect the safety or effectiveness of that device or system. Life support devices or systems are intended to be implanted in the human body or to support and/or maintain and sustain and/or protect human life. If they fail, it is reasonable to assume that the health of the user or other persons may be endangered.

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Key features
- Drives 4 N-Channel Power MOSFETs
- Separate control input for each MOSFET
- Unlimited D.C. switch on time of Low and Highside MOSFETs
- Internal shoot through protection and minimum internal dead time option
- 1 bit diagnosis / ERR
- Over current warning based on current sense OPAMP with fixed warning level
- Analog adjustable Short Circuit Protection levels via SCDL pin with open pin detection and SCD deactivation
- Over temperature warning
- Over voltage warning
- Under voltage warning and shutdown