MOSFET DataSheet OptiMOS PowerManagement&Multimarket

MOSFET DataSheet OptiMOS PowerManagement&Multimarket
MOSFET
MetalOxideSemiconductorFieldEffectTransistor
OptiMOSTM
OptiMOSª3Power-Transistor,100V
IPB065N10N3G
DataSheet
Rev.2.0
Final
PowerManagement&Multimarket
OptiMOSª3Power-Transistor,100V
IPB065N10N3G
1Description
D²PAK
Features
•N-channel,normallevel
•ExcellentgatechargexRDS(on)product(FOM)
•Verylowon-resistanceRDS(on)
•175°Coperatingtemperature
•Pb-freeleadplating;RoHScompliant
•QualifiedaccordingtoJEDEC1)fortargetapplication
•Idealforhigh-frequencyswitchingandsynchronousrectification
•Halogen-freeaccordingtoIEC61249-2-21
Table1KeyPerformanceParameters
Parameter
Value
Unit
VDS
100
V
RDS(on),max
6.5
mΩ
ID
80
A
Drain
Pin 2, Tab
Gate
Pin 1
Source
Pin 3
Type/OrderingCode
Package
Marking
RelatedLinks
IPB065N10N3 G
PG-TO 263-3
065N10N
-
1)
J-STD20 and JESD22
Final Data Sheet
2
Rev.2.0,2014-07-04
OptiMOSª3Power-Transistor,100V
IPB065N10N3G
TableofContents
Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2
Maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
Thermal characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
Electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
Electrical characteristics diagrams . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
Package Outlines . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
Revision History . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
Disclaimer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
Final Data Sheet
3
Rev.2.0,2014-07-04
OptiMOSª3Power-Transistor,100V
IPB065N10N3G
2Maximumratings
atTj=25°C,unlessotherwisespecified
Table2Maximumratings
Parameter
Symbol
Continuous drain current
Values
Unit
Note/TestCondition
80
73
A
TC=25°C1)
TC=100°C
-
320
A
TC=25°C
-
-
160
mJ
ID=80A,RGS=25Ω
VGS
-20
-
20
V
-
Power dissipation
Ptot
-
-
150
W
TC=25°C
Operating and storage temperature
Tj,Tstg
-55
-
175
°C
IEC climatic category;
DIN IEC 68-1: 55/175/56
Unit
Note/TestCondition
Min.
Typ.
Max.
ID
-
-
Pulsed drain current1)
ID,pulse
-
Avalanche energy, single pulse
EAS
Gate source voltage
3Thermalcharacteristics
Table3Thermalcharacteristics
Parameter
Symbol
Thermal resistance, junction - case
Values
Min.
Typ.
Max.
RthJC
-
-
1
K/W
-
Thermal resistance, junction - ambient,
RthJA
minimal footprint
-
-
62
K/W
-
Thermal resistance, junction - ambient,
RthJA
6 cm2 cooling area2)
-
-
40
K/W
-
1)
See figure 3
Device on 40 mm x 40 mm x 1.5 mm epoxy PCB FR4 with 6 cm2 (one layer, 70 µm thick) copper area for drain connection.
PCB is vertical in still air.
2)
Final Data Sheet
4
Rev.2.0,2014-07-04
OptiMOSª3Power-Transistor,100V
IPB065N10N3G
4Electricalcharacteristics
Table4Staticcharacteristics
Parameter
Symbol
Drain-source breakdown voltage
Values
Unit
Note/TestCondition
-
V
VGS=0V,ID=1mA
2.7
3.5
V
VDS=VGS,ID=90µA
-
0.1
10
1
100
µA
VDS=100V,VGS=0V,Tj=25°C
VDS=100V,VGS=0V,Tj=125°C
IGSS
-
1
100
nA
VGS=20V,VDS=0V
Drain-source on-state resistance
RDS(on)
-
5.9
7.3
6.5
12.4
mΩ
VGS=10V,ID=80A
VGS=6V,ID=40A
Gate resistance1)
RG
-
1.6
2.4
Ω
-
Transconductance
gfs
50
99
-
S
|VDS|>2|ID|RDS(on)max,ID=80A
Unit
Note/TestCondition
Min.
Typ.
Max.
V(BR)DSS
100
-
Gate threshold voltage
VGS(th)
2
Zero gate voltage drain current
IDSS
Gate-source leakage current
Table5Dynamiccharacteristics1)
Parameter
Symbol
Input capacitance
Values
Min.
Typ.
Max.
Ciss
-
3690
4910
pF
VGS=0V,VDS=50V,f=1MHz
Output capacitance
Coss
-
646
859
pF
VGS=0V,VDS=50V,f=1MHz
Reverse transfer capacitance
Crss
-
25
44
pF
VGS=0V,VDS=50V,f=1MHz
Turn-on delay time
td(on)
-
19
-
ns
VDD=50V,VGS=10V,ID=80A,
RG,ext=1.6Ω
Rise time
tr
-
37
-
ns
VDD=50V,VGS=10V,ID=80A,
RG,ext=1.6Ω
Turn-off delay time
td(off)
-
37
-
ns
VDD=50V,VGS=10V,ID=80A,
RG,ext=1.6Ω
Fall time
tf
-
9
-
ns
VDD=50V,VGS=10V,ID=80A,
RG,ext=1.6Ω
Unit
Note/TestCondition
Table6Gatechargecharacteristics2)
Parameter
Symbol
Values
Min.
Typ.
Max.
Qgs
-
18
-
nC
VDD=50V,ID=80A,VGS=0to10V
Gate to drain charge
Qgd
-
10
15
nC
VDD=50V,ID=80A,VGS=0to10V
Switching charge
Qsw
-
16
-
nC
VDD=50V,ID=80A,VGS=0to10V
Gate charge total
Qg
-
51
64
nC
VDD=50V,ID=80A,VGS=0to10V
Gate plateau voltage
Vplateau
-
4.9
-
V
VDD=50V,ID=80A,VGS=0to10V
Qoss
-
68
91
nC
VDD=50V,VGS=0V
Gate to source charge
1)
1)
Output charge
1)
2)
Defined by design. Not subject to production test.
See ″Gate charge waveforms″ for parameter definition
Final Data Sheet
5
Rev.2.0,2014-07-04
OptiMOSª3Power-Transistor,100V
IPB065N10N3G
Table7Reversediode
Parameter
Symbol
Diode continous forward current
Diode pulse current
Diode forward voltage
1)
Reverse recovery time
1)
Reverse recovery charge
1)
Values
Unit
Note/TestCondition
80
A
TC=25°C
-
320
A
TC=25°C
-
1
1.2
V
VGS=0V,IF=80A,Tj=25°C
trr
-
73
146
ns
VR=50V,IF=IS,diF/dt=100A/µs
Qrr
-
139
278
nC
VR=50V,IF=IS,diF/dt=100A/µs
Min.
Typ.
Max.
IS
-
-
IS,pulse
-
VSD
Defined by design. Not subject to production test.
Final Data Sheet
6
Rev.2.0,2014-07-04
OptiMOSª3Power-Transistor,100V
IPB065N10N3G
5Electricalcharacteristicsdiagrams
Diagram1:Powerdissipation
Diagram2:Draincurrent
175
100
150
80
60
100
ID[A]
Ptot[W]
125
75
40
50
20
25
0
0
50
100
150
0
200
0
50
100
TC[°C]
150
200
TC[°C]
Ptot=f(TC)
ID=f(TC);VGS≥10V
Diagram3:Safeoperatingarea
Diagram4:Max.transientthermalimpedance
3
101
10
1 µs
10 µs
102
100 µs
100
ID[A]
ZthJC[K/W]
1 ms
101
10 ms
0
10
0.5
0.2
0.1
10-1
DC
0.05
0.02
0.01
10-1
single pulse
10-2
10-1
100
101
102
103
10-2
10-5
10-4
VDS[V]
10-2
10-1
100
tp[s]
ID=f(VDS);TC=25°C;D=0;parameter:tp
Final Data Sheet
10-3
ZthJC=f(tp);parameter:D=tp/T
7
Rev.2.0,2014-07-04
OptiMOSª3Power-Transistor,100V
IPB065N10N3G
Diagram5:Typ.outputcharacteristics
Diagram6:Typ.drain-sourceonresistance
400
12
4.5 V
10 V
320
7.5 V
5V
6V
9
RDS(on)[mΩ]
240
ID[A]
6V
160
6
10 V
3
5V
80
7.5 V
4.5 V
0
0
1
2
3
4
0
5
0
50
100
VDS[V]
150
200
RDS(on)=f(ID);Tj=25°C;parameter:VGS
Diagram7:Typ.transfercharacteristics
Diagram8:Typ.forwardtransconductance
160
160
120
120
gfs[S]
ID[A]
ID=f(VDS);Tj=25°C;parameter:VGS
80
40
300
80
40
175 °C
0
250
ID[A]
0
2
25 °C
4
6
8
0
0
VGS[V]
100
150
ID[A]
ID=f(VGS);|VDS|>2|ID|RDS(on)max;parameter:Tj
Final Data Sheet
50
gfs=f(ID);Tj=25°C
8
Rev.2.0,2014-07-04
OptiMOSª3Power-Transistor,100V
IPB065N10N3G
Diagram9:Drain-sourceon-stateresistance
Diagram10:Typ.gatethresholdvoltage
14
4.0
12
3.5
3.0
10
900 µA
2.5
max
VGS(th)[V]
RDS(on)[mΩ]
8
typ
6
90 µA
2.0
1.5
4
1.0
2
0.5
0
-60
-20
20
60
100
140
0.0
-60
180
-20
20
Tj[°C]
60
100
140
180
Tj[°C]
RDS(on)=f(Tj);ID=80A;VGS=10V
VGS(th)=f(Tj);VGS=VDS;parameter:ID
Diagram11:Typ.capacitances
Diagram12:Forwardcharacteristicsofreversediode
4
103
10
25 °C
175 °C
25 °C max
175 °C max
Ciss
Coss
102
IF[A]
C[pF]
103
102
101
Crss
101
0
20
40
60
80
100
0.0
0.5
VDS[V]
C=f(VDS);VGS=0V;f=1MHz
Final Data Sheet
1.0
1.5
2.0
VSD[V]
IF=f(VSD);parameter:Tj
9
Rev.2.0,2014-07-04
OptiMOSª3Power-Transistor,100V
IPB065N10N3G
Diagram13:Avalanchecharacteristics
Diagram14:Typ.gatecharge
102
10
150 °C
8
25 °C
100 °C
80 V
50 V
20 V
VGS[V]
IAS[A]
6
101
4
2
100
10-1
100
101
102
103
0
0
tAV[µs]
20
40
60
Qgate[nC]
IAS=f(tAV);RGS=25Ω;parameter:Tj(start)
VGS=f(Qgate);ID=80Apulsed;parameter:VDD
Diagram15:Drain-sourcebreakdownvoltage
Gate charge waveforms
110
VBR(DSS)[V]
105
100
95
90
-60
-20
20
60
100
140
180
Tj[°C]
VBR(DSS)=f(Tj);ID=1mA
Final Data Sheet
10
Rev.2.0,2014-07-04
OptiMOSª3Power-Transistor,100V
IPB065N10N3G
6PackageOutlines
Figure1OutlinePG-TO263-3,dimensionsinmm/inches
Final Data Sheet
11
Rev.2.0,2014-07-04
OptiMOSª3Power-Transistor,100V
IPB065N10N3G
RevisionHistory
IPB065N10N3 G
Revision:2014-07-04,Rev.2.0
Previous Revision
Revision
Date
Subjects (major changes since last revision)
2.0
2014-07-04
Release of final version
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Publishedby
InfineonTechnologiesAG
81726München,Germany
©2014InfineonTechnologiesAG
AllRightsReserved.
LegalDisclaimer
Theinformationgiveninthisdocumentshallinnoeventberegardedasaguaranteeofconditionsorcharacteristics.With
respecttoanyexamplesorhintsgivenherein,anytypicalvaluesstatedhereinand/oranyinformationregardingtheapplication
ofthedevice,InfineonTechnologiesherebydisclaimsanyandallwarrantiesandliabilitiesofanykind,includingwithout
limitation,warrantiesofnon-infringementofintellectualpropertyrightsofanythirdparty.
Information
Forfurtherinformationontechnology,deliverytermsandconditionsandpricespleasecontactyournearestInfineon
TechnologiesOffice(www.infineon.com).
Warnings
Duetotechnicalrequirements,componentsmaycontaindangeroussubstances.Forinformationonthetypesinquestion,
pleasecontactthenearestInfineonTechnologiesOffice.
TheInfineonTechnologiescomponentdescribedinthisDataSheetmaybeusedinlife-supportdevicesorsystemsand/or
automotive,aviationandaerospaceapplicationsorsystemsonlywiththeexpresswrittenapprovalofInfineonTechnologies,ifa
failureofsuchcomponentscanreasonablybeexpectedtocausethefailureofthatlife-support,automotive,aviationand
aerospacedeviceorsystemortoaffectthesafetyoreffectivenessofthatdeviceorsystem.Lifesupportdevicesorsystemsare
intendedtobeimplantedinthehumanbodyortosupportand/ormaintainandsustainand/orprotecthumanlife.Iftheyfail,itis
reasonabletoassumethatthehealthoftheuserorotherpersonsmaybeendangered.
Final Data Sheet
12
Rev.2.0,2014-07-04
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