MOSFET DataSheet OptiMOS PowerManagement&Multimarket

MOSFET DataSheet OptiMOS PowerManagement&Multimarket
MOSFET
MetalOxideSemiconductorFieldEffectTransistor
OptiMOSTM
OptiMOSª5Power-Transistor,100V
IPP083N10N5
DataSheet
Rev.2.0
Final
PowerManagement&Multimarket
OptiMOSª5Power-Transistor,100V
IPP083N10N5
1Description
TO-220-3
tab
Features
•Idealforhighfrequencyswitchingandsync.rec.
•ExcellentgatechargexRDS(on)product(FOM)
•Verylowon-resistanceRDS(on)
•N-channel,normallevel
•100%avalanchetested
•Pb-freeplating;RoHScompliant
•QualifiedaccordingtoJEDEC1)fortargetapplications
•Halogen-freeaccordingtoIEC61249-2-21
Table1KeyPerformanceParameters
Parameter
Value
Unit
VDS
100
V
RDS(on),max
8.3
mΩ
ID
73
A
Qoss
40
nC
QG(0V..10V)
30
nC
Type/OrderingCode
Package
IPP083N10N5
PG-TO220-3
1)
Drain
Pin 2, Tab
Gate
Pin 1
Source
Pin 3
Marking
083N10N5
RelatedLinks
-
J-STD20 and JESD22
Final Data Sheet
2
Rev.2.0,2014-12-17
OptiMOSª5Power-Transistor,100V
IPP083N10N5
TableofContents
Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2
Maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
Thermal characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
Electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
Electrical characteristics diagrams . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
Package Outlines . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
Revision History . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
Disclaimer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
Final Data Sheet
3
Rev.2.0,2014-12-17
OptiMOSª5Power-Transistor,100V
IPP083N10N5
2Maximumratings
atTj=25°C,unlessotherwisespecified
Table2Maximumratings
Parameter
Symbol
Continuous drain current
Values
Unit
Note/TestCondition
73
53
A
TC=25°C
TC=100°C
-
292
A
TC=25°C
-
-
42
mJ
ID=73A,RGS=25Ω
VGS
-20
-
20
V
-
Power dissipation
Ptot
-
-
100
W
TC=25°C
Operating and storage temperature
Tj,Tstg
-55
-
175
°C
IEC climatic category;
DIN IEC 68-1: 55/175/56
Unit
Note/TestCondition
Min.
Typ.
Max.
ID
-
-
Pulsed drain current1)
ID,pulse
-
Avalanche energy, single pulse
EAS
Gate source voltage
3Thermalcharacteristics
Table3Thermalcharacteristics
Parameter
Symbol
Thermal resistance, junction - case
Values
Min.
Typ.
Max.
RthJC
-
1.1
1.5
K/W
-
Thermal resistance, junction - ambient,
RthJA
minimal footprint
-
-
62
K/W
-
Thermal resistance, junction - ambient,
RthJA
6 cm2 cooling area2)
-
-
40
K/W
-
Soldering temperature, wave and
reflow soldering are allowed
-
-
260
°C
-
Tsold
1)
see figure 3
Device on 40 mm x 40 mm x 1.5 mm epoxy PCB FR4 with 6 cm2 (one layer, 70 µm thick) copper area for drain connection.
PCB is vertical in still air.
2)
Final Data Sheet
4
Rev.2.0,2014-12-17
OptiMOSª5Power-Transistor,100V
IPP083N10N5
4Electricalcharacteristics
Table4Staticcharacteristics
Parameter
Symbol
Drain-source breakdown voltage
Values
Unit
Note/TestCondition
-
V
VGS=0V,ID=1mA
3.0
3.8
V
VDS=VGS,ID=49µA
-
0.1
10
1
100
µA
VDS=100V,VGS=0V,Tj=25°C
VDS=100V,VGS=0V,Tj=125°C
IGSS
-
1
100
nA
VGS=20V,VDS=0V
Drain-source on-state resistance
RDS(on)
-
7.3
8.9
8.3
11.0
mΩ
VGS=10V,ID=73A
VGS=6V,ID=37A
Gate resistance1)
RG
-
1.2
1.8
Ω
-
Transconductance
gfs
48
96
-
S
|VDS|>2|ID|RDS(on)max,ID=73A
Unit
Note/TestCondition
Min.
Typ.
Max.
V(BR)DSS
100
-
Gate threshold voltage
VGS(th)
2.2
Zero gate voltage drain current
IDSS
Gate-source leakage current
Table5Dynamiccharacteristics1)
Parameter
Symbol
Input capacitance
Values
Min.
Typ.
Max.
Ciss
-
2100
2730
pF
VGS=0V,VDS=50V,f=1MHz
Output capacitance
Coss
-
337
438
pF
VGS=0V,VDS=50V,f=1MHz
Reverse transfer capacitance
Crss
-
16
28
pF
VGS=0V,VDS=50V,f=1MHz
Turn-on delay time
td(on)
-
13
-
ns
VDD=50V,VGS=10V,ID=73A,
RG,ext=1.6Ω
Rise time
tr
-
5
-
ns
VDD=50V,VGS=10V,ID=73A,
RG,ext=1.6Ω
Turn-off delay time
td(off)
-
21
-
ns
VDD=50V,VGS=10V,ID=73A,
RG,ext=1.6Ω
Fall time
tf
-
5
-
ns
VDD=50V,VGS=10V,ID=73A,
RG,ext=1.6Ω
Unit
Note/TestCondition
Table6Gatechargecharacteristics2)
Parameter
Symbol
Values
Min.
Typ.
Max.
Qgs
-
11
-
nC
VDD=50V,ID=73A,VGS=0to10V
Gate to drain charge
Qgd
-
6.5
10
nC
VDD=50V,ID=73A,VGS=0to10V
Switching charge
Qsw
-
11
-
nC
VDD=50V,ID=73A,VGS=0to10V
Gate charge total
Qg
-
30
37
nC
VDD=50V,ID=73A,VGS=0to10V
Gate plateau voltage
Vplateau
-
5.2
-
V
VDD=50V,ID=73A,VGS=0to10V
Qoss
-
40
53
nC
VDD=50V,VGS=0V
Gate to source charge
1)
1)
1)
Output charge
1)
2)
Defined by design. Not subject to production test.
See ″Gate charge waveforms″ for parameter definition
Final Data Sheet
5
Rev.2.0,2014-12-17
OptiMOSª5Power-Transistor,100V
IPP083N10N5
Table7Reversediode
Parameter
Symbol
Diode continous forward current
Diode pulse current
Diode forward voltage
1)
Reverse recovery time
1)
Reverse recovery charge
1)
Values
Unit
Note/TestCondition
73
A
TC=25°C
-
292
A
TC=25°C
-
1.0
1.2
V
VGS=0V,IF=73A,Tj=25°C
trr
-
58
116
ns
VR=50V,IF=IS,diF/dt=100A/µs
Qrr
-
118
236
nC
VR=50V,IF=IS,diF/dt=100A/µs
Min.
Typ.
Max.
IS
-
-
IS,pulse
-
VSD
Defined by design. Not subject to production test.
Final Data Sheet
6
Rev.2.0,2014-12-17
OptiMOSª5Power-Transistor,100V
IPP083N10N5
5Electricalcharacteristicsdiagrams
Diagram1:Powerdissipation
Diagram2:Draincurrent
120
80
70
60
80
ID[A]
Ptot[W]
50
40
30
40
20
10
0
0
50
100
150
0
200
0
50
100
TC[°C]
150
200
TC[°C]
Ptot=f(TC)
ID=f(TC);VGS≥10V
Diagram3:Safeoperatingarea
Diagram4:Max.transientthermalimpedance
3
101
10
1 µs
10 µs
102
100
100 µs
ZthJC[K/W]
ID[A]
0.5
1 ms
101
10 ms
0.2
0.1
10
0
10
10-1
10-1
-1
DC
100
101
0.05
0.02
0.01
single pulse
102
103
10-2
10-5
10-4
VDS[V]
10-2
10-1
100
tp[s]
ID=f(VDS);TC=25°C;D=0;parameter:tp
Final Data Sheet
10-3
ZthJC=f(tp);parameter:D=tp/T
7
Rev.2.0,2014-12-17
OptiMOSª5Power-Transistor,100V
IPP083N10N5
Diagram5:Typ.outputcharacteristics
Diagram6:Typ.drain-sourceonresistance
300
20
5V
10 V
6V
4.5 V
8V
16
RDS(on)[mΩ]
200
ID[A]
6V
12
8V
8
10 V
100
4
5V
4.5 V
0
0
1
2
3
4
0
5
0
50
100
VDS[V]
150
200
RDS(on)=f(ID);Tj=25°C;parameter:VGS
Diagram7:Typ.transfercharacteristics
Diagram8:Typ.forwardtransconductance
300
120
250
100
200
80
gfs[S]
ID[A]
ID=f(VDS);Tj=25°C;parameter:VGS
150
40
50
20
0
0
2
100
120
25 °C
4
6
8
10
0
0
20
VGS[V]
40
60
80
ID[A]
ID=f(VGS);|VDS|>2|ID|RDS(on)max;parameter:Tj
Final Data Sheet
300
60
100
175 °C
250
ID[A]
gfs=f(ID);Tj=25°C
8
Rev.2.0,2014-12-17
OptiMOSª5Power-Transistor,100V
IPP083N10N5
Diagram9:Drain-sourceon-stateresistance
Diagram10:Typ.gatethresholdvoltage
18
4.0
16
3.5
14
490 µA
3.0
12
49 µA
max
10
VGS(th)[V]
RDS(on)[mΩ]
2.5
typ
8
2.0
1.5
6
1.0
4
0.5
2
0
-60
-20
20
60
100
140
0.0
-60
180
-20
20
Tj[°C]
60
100
140
180
Tj[°C]
RDS(on)=f(Tj);ID=73A;VGS=10V
VGS(th)=f(Tj);VGS=VDS;parameter:ID
Diagram11:Typ.capacitances
Diagram12:Forwardcharacteristicsofreversediode
4
103
10
25 °C
175 °C
25 °C, max
175 °C, max
Ciss
102
C[pF]
103
IF[A]
Coss
102
101
Crss
101
0
20
40
60
80
100
0.0
0.5
VDS[V]
C=f(VDS);VGS=0V;f=1MHz
Final Data Sheet
1.0
1.5
2.0
VSD[V]
IF=f(VSD);parameter:Tj
9
Rev.2.0,2014-12-17
OptiMOSª5Power-Transistor,100V
IPP083N10N5
Diagram13:Avalanchecharacteristics
Diagram14:Typ.gatecharge
102
10
8
50 V
25 °C
VGS[V]
IAS[A]
100 °C
80 V
20 V
6
101
4
150 °C
2
100
100
101
102
103
0
0
tAV[µs]
10
20
30
Qgate[nC]
IAS=f(tAV);RGS=25Ω;parameter:Tj(start)
VGS=f(Qgate);ID=73Apulsed;parameter:VDD
Diagram15:Drain-sourcebreakdownvoltage
Gate charge waveforms
110
VBR(DSS)[V]
105
100
95
90
-60
-20
20
60
100
140
180
Tj[°C]
VBR(DSS)=f(Tj);ID=1mA
Final Data Sheet
10
Rev.2.0,2014-12-17
OptiMOSª5Power-Transistor,100V
IPP083N10N5
6PackageOutlines
Figure1OutlinePG-TO220-3,dimensionsinmm/inches
Final Data Sheet
11
Rev.2.0,2014-12-17
OptiMOSª5Power-Transistor,100V
IPP083N10N5
RevisionHistory
IPP083N10N5
Revision:2014-12-17,Rev.2.0
Previous Revision
Revision
Date
Subjects (major changes since last revision)
2.0
2014-12-17
Release of final version
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Publishedby
InfineonTechnologiesAG
81726München,Germany
©2014InfineonTechnologiesAG
AllRightsReserved.
LegalDisclaimer
Theinformationgiveninthisdocumentshallinnoeventberegardedasaguaranteeofconditionsorcharacteristics.With
respecttoanyexamplesorhintsgivenherein,anytypicalvaluesstatedhereinand/oranyinformationregardingtheapplication
ofthedevice,InfineonTechnologiesherebydisclaimsanyandallwarrantiesandliabilitiesofanykind,includingwithout
limitation,warrantiesofnon-infringementofintellectualpropertyrightsofanythirdparty.
Information
Forfurtherinformationontechnology,deliverytermsandconditionsandpricespleasecontactyournearestInfineon
TechnologiesOffice(www.infineon.com).
Warnings
Duetotechnicalrequirements,componentsmaycontaindangeroussubstances.Forinformationonthetypesinquestion,
pleasecontactthenearestInfineonTechnologiesOffice.
TheInfineonTechnologiescomponentdescribedinthisDataSheetmaybeusedinlife-supportdevicesorsystemsand/or
automotive,aviationandaerospaceapplicationsorsystemsonlywiththeexpresswrittenapprovalofInfineonTechnologies,ifa
failureofsuchcomponentscanreasonablybeexpectedtocausethefailureofthatlife-support,automotive,aviationand
aerospacedeviceorsystemortoaffectthesafetyoreffectivenessofthatdeviceorsystem.Lifesupportdevicesorsystemsare
intendedtobeimplantedinthehumanbodyortosupportand/ormaintainandsustainand/orprotecthumanlife.Iftheyfail,itis
reasonabletoassumethatthehealthoftheuserorotherpersonsmaybeendangered.
Final Data Sheet
12
Rev.2.0,2014-12-17
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