RL78/G14 User`s Manual: Hardware

RL78/G14 User`s Manual: Hardware
User’s Manual
16
RL78/G14
User’s Manual: Hardware
16-Bit Single-Chip Microcontrollers
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Rev.1.00
Dec 2011
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All information included in this document is current as of the date this document is issued. Such information, however, is
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NOTES FOR CMOS DEVICES
(1) VOLTAGE APPLICATION WAVEFORM AT INPUT PIN: Waveform distortion due to input noise or a
reflected wave may cause malfunction. If the input of the CMOS device stays in the area between VIL
(MAX) and VIH (MIN) due to noise, etc., the device may malfunction. Take care to prevent chattering noise
from entering the device when the input level is fixed, and also in the transition period when the input level
passes through the area between VIL (MAX) and VIH (MIN).
(2) HANDLING OF UNUSED INPUT PINS: Unconnected CMOS device inputs can be cause of malfunction. If
an input pin is unconnected, it is possible that an internal input level may be generated due to noise, etc.,
causing malfunction. CMOS devices behave differently than Bipolar or NMOS devices. Input levels of
CMOS devices must be fixed high or low by using pull-up or pull-down circuitry. Each unused pin should be
connected to VDD or GND via a resistor if there is a possibility that it will be an output pin. All handling
related to unused pins must be judged separately for each device and according to related specifications
governing the device.
(3) PRECAUTION AGAINST ESD: A strong electric field, when exposed to a MOS device, can cause
destruction of the gate oxide and ultimately degrade the device operation. Steps must be taken to stop
generation of static electricity as much as possible, and quickly dissipate it when it has occurred.
Environmental control must be adequate. When it is dry, a humidifier should be used. It is recommended
to avoid using insulators that easily build up static electricity. Semiconductor devices must be stored and
transported in an anti-static container, static shielding bag or conductive material. All test and measurement
tools including work benches and floors should be grounded. The operator should be grounded using a wrist
strap. Semiconductor devices must not be touched with bare hands. Similar precautions need to be taken
for PW boards with mounted semiconductor devices.
(4) STATUS BEFORE INITIALIZATION: Power-on does not necessarily define the initial status of a MOS
device. Immediately after the power source is turned ON, devices with reset functions have not yet been
initialized. Hence, power-on does not guarantee output pin levels, I/O settings or contents of registers. A
device is not initialized until the reset signal is received. A reset operation must be executed immediately
after power-on for devices with reset functions.
(5) POWER ON/OFF SEQUENCE: In the case of a device that uses different power supplies for the internal
operation and external interface, as a rule, switch on the external power supply after switching on the internal
power supply. When switching the power supply off, as a rule, switch off the external power supply and then
the internal power supply. Use of the reverse power on/off sequences may result in the application of an
overvoltage to the internal elements of the device, causing malfunction and degradation of internal elements
due to the passage of an abnormal current. The correct power on/off sequence must be judged separately
for each device and according to related specifications governing the device.
(6) INPUT OF SIGNAL DURING POWER OFF STATE : Do not input signals or an I/O pull-up power supply
while the device is not powered. The current injection that results from input of such a signal or I/O pull-up
power supply may cause malfunction and the abnormal current that passes in the device at this time may
cause degradation of internal elements. Input of signals during the power off state must be judged
separately for each device and according to related specifications governing the device.
How to Use This Manual
Readers
This manual is intended for user engineers who wish to understand the functions of the
RL78/G14 and design and develop application systems and programs for these devices.
The target products are as follows.
• 30-pin: R5F104Ax (x = A, C to G)
• 48-pin:
R5F104Gx (x = A, C to H, J)
• 32-pin: R5F104Bx (x = A, C to G)
• 52-pin:
R5F104Jx (x = C to H, J)
• 36-pin: R5F104Cx (x = A, C to G)
• 64-pin:
R5F104Lx (x = C to H, J)
• 40-pin: R5F104Ex (x = A, C to H)
• 80-pin:
R5F104Mx (x = F, G, H, J)
• 44-pin: R5F104Fx (x = A, C to H, J)
• 100-pin:
R5F104Px (x = F, G, H, J)
Purpose
This manual is intended to give users an understanding of the functions described in the
Organization below.
Organization
The RL78/G14 manual is separated into two parts: this manual and the software edition
(common to the RL78 family).
RL78/G14
RL78 Family
User’s Manual
User’s Manual
Hardware
Software
(This Manual)
• Pin functions
• CPU functions
• Internal block functions
• Instruction set
• Interrupts
• Explanation of each instruction
• Other on-chip peripheral functions
• Electrical specifications
How to Read This Manual
It is assumed that the readers of this manual have general knowledge of electrical
engineering, logic circuits, and microcontrollers.
• To gain a general understanding of functions:
→ Read this manual in the order of the CONTENTS. The mark “<R>” shows major
revised points. The revised points can be easily searched by copying an “<R>” in the
PDF file and specifying it in the “Find what:” field.
• How to interpret the register format:
→ For a bit number enclosed in angle brackets, the bit name is defined as a reserved
word in the assembler, and is defined as an sfr variable using the #pragma sfr
directive in the compiler.
• To know details of the RL78/G14 Microcontroller instructions:
→ Refer to the separate document RL78 Family User's Manual Software
(R01US0015E).
Conventions
Data significance:
Higher digits on the left and lower digits on the right
Active low representations: ××× (overscore over pin and signal name)
Note:
Footnote for item marked with Note in the text
Caution:
Information requiring particular attention
Remark:
Supplementary information
...×××× or ××××B
Numerical representations: Binary
...××××
Decimal
Hexadecimal
Related Documents
...××××H
The related documents indicated in this publication may include preliminary versions.
However, preliminary versions are not marked as such.
Documents Related to Devices
Document Name
Document No.
RL78/G14 User’s Manual Hardware
This manual
RL78 Family User's Manual Software
R01US0015E
Documents Related to Flash Memory Programming (User’s Manual)
Document Name
PG-FP5 Flash Memory Programmer
Document No.
R20UT0008E
Caution The related documents listed above are subject to change without notice. Be sure to use the latest
version of each document when designing.
Other Documents
Document Name
RENESAS MICROCOMPUTER GENERAL CATALOG
Document No.
R01CS0001E
Semiconductor Device Mount Manual
Note
Quality Grades on NEC Semiconductor Devices
C11531E
NEC Semiconductor Device Reliability/Quality Control System
C10983E
Guide to Prevent Damage for Semiconductor Devices by Electrostatic Discharge (ESD)
C11892E
Note See the “Semiconductor Device Mount Manual” website (http://www.renesas.com/prod/package/manual/index.html).
Caution The related documents listed above are subject to change without notice. Be sure to use the latest
version of each document when designing.
All trademarks and registered trademarks are the property of their respective owners.
EEPROM is a trademark of Renesas Electronics Corporation.
Windows, Windows NT and Windows XP are registered trademarks or trademarks of Microsoft Corporation in the
United States and/or other countries.
PC/AT is a trademark of International Business Machines Corporation.
SuperFlash is a registered trademark of Silicon Storage Technology, Inc. in several countries including the United States
and Japan.
Caution: This product uses SuperFlash® technology licensed from Silicon Storage Technology, Inc.
CONTENTS
CHAPTER 1 OUTLINE............................................................................................................................... 1
1.1 Features........................................................................................................................................... 1
1.2 Ordering Information ..................................................................................................................... 3
1.3 Pin Configuration (Top View) ........................................................................................................ 6
1.3.1 30-pin products................................................................................................................................... 6
1.3.2 32-pin products................................................................................................................................... 7
1.3.3 36-pin products................................................................................................................................... 8
1.3.4 40-pin products................................................................................................................................... 9
1.3.5 44-pin products................................................................................................................................. 10
1.3.6 48-pin products................................................................................................................................. 11
1.3.7 52-pin products................................................................................................................................. 13
1.3.8 64-pin products................................................................................................................................. 14
1.3.9 80-pin products................................................................................................................................. 17
1.3.10 100-pin products............................................................................................................................. 18
1.4 Pin Identification .......................................................................................................................... 20
1.5 Block Diagram .............................................................................................................................. 21
1.5.1 30-pin products................................................................................................................................. 21
1.5.2 32-pin products................................................................................................................................. 22
1.5.3 36-pin products................................................................................................................................. 23
1.5.4 40-pin products................................................................................................................................. 24
1.5.5 44-pin products................................................................................................................................. 25
1.5.6 48-pin products................................................................................................................................. 26
1.5.7 52-pin products................................................................................................................................. 27
1.5.8 64-pin products................................................................................................................................. 28
1.5.9 80-pin products................................................................................................................................. 29
1.5.10 100-pin products............................................................................................................................. 30
1.6 Outline of Functions .................................................................................................................... 31
CHAPTER 2 PIN FUNCTIONS ............................................................................................................... 41
2.1 Pin Function List .......................................................................................................................... 41
2.1.1 30-pin products................................................................................................................................. 42
2.1.2 32-pin products................................................................................................................................. 44
2.1.3 36-pin products................................................................................................................................. 46
2.1.4 40-pin products................................................................................................................................. 48
2.1.5 44-pin products................................................................................................................................. 50
2.1.6 48-pin products................................................................................................................................. 52
2.1.7 52-pin products................................................................................................................................. 54
Index-1
2.1.8 64-pin products................................................................................................................................. 56
2.1.9 80-pin products................................................................................................................................. 58
2.1.10 100-pin products............................................................................................................................. 61
2.1.11 Pins for each product (pins other than port pins)............................................................................ 64
2.2 Description of Pin Functions ...................................................................................................... 70
2.2.1 P00 to P06 (port 0) ........................................................................................................................... 70
2.2.2 P10 to P17 (port 1) ........................................................................................................................... 71
2.2.3 P20 to P27 (port 2) ........................................................................................................................... 72
2.2.4 P30, P31 (port 3) .............................................................................................................................. 73
2.2.5 P40 to P47 (port 4) ........................................................................................................................... 74
2.2.6 P50 to P57 (port 5) ........................................................................................................................... 75
2.2.7 P60 to P67 (port 6) ........................................................................................................................... 76
2.2.8 P70 to P77 (port 7) ........................................................................................................................... 76
2.2.9 P80 to P87 (port 8) ........................................................................................................................... 77
2.2.10 P100 to P102 (port 10) ................................................................................................................... 77
2.2.11 P110, P111 (port 11) ...................................................................................................................... 78
2.2.12 P120 to P124 (port 12) ................................................................................................................... 78
2.2.13 P130 and P137 (port 13) ................................................................................................................ 79
2.2.14 P140 to P147 (port 14) ................................................................................................................... 79
2.2.15 P150 to P156 (port 15) ................................................................................................................... 80
2.2.16 VDD, EVDD0, EVDD1, VSS, EVSS0, EVSS1 ............................................................................................ 81
2.2.17 RESET ........................................................................................................................................... 81
2.2.18 REGC ............................................................................................................................................. 81
2.3 Pin I/O Circuits and Recommended Connection of Unused Pins ........................................... 82
CHAPTER 3 CPU ARCHITECTURE ...................................................................................................... 88
3.1 Memory Space .............................................................................................................................. 88
3.1.1 Internal program memory space..................................................................................................... 100
3.1.2 Mirror area...................................................................................................................................... 103
3.1.3 Internal data memory space ........................................................................................................... 105
3.1.4 Special function register (SFR) area .............................................................................................. 106
3.1.5 Extended special function register (2nd SFR: 2nd Special Function Register) area ..................... 106
3.1.6 Data memory addressing ............................................................................................................... 107
3.2 Processor Registers .................................................................................................................. 116
3.2.1 Control registers ............................................................................................................................. 116
3.2.2 General-purpose registers.............................................................................................................. 119
3.2.3 ES and CS registers....................................................................................................................... 121
3.2.4 Special function registers (SFRs) ................................................................................................... 122
3.2.5 Extended special function registers (2nd SFRs: 2nd Special Function Registers) ......................... 128
3.3 Instruction Address Addressing............................................................................................... 138
3.3.1 Relative addressing........................................................................................................................ 138
Index-2
3.3.2 Immediate addressing .................................................................................................................... 138
3.3.3 Table indirect addressing ............................................................................................................... 139
3.3.4 Register direct addressing.............................................................................................................. 140
3.4 Addressing for Processing Data Addresses ........................................................................... 141
3.4.1 Implied addressing ......................................................................................................................... 141
3.4.2 Register addressing ....................................................................................................................... 141
3.4.3 Direct addressing ........................................................................................................................... 142
3.4.4 Short direct addressing .................................................................................................................. 143
3.4.5 SFR addressing.............................................................................................................................. 144
3.4.6 Register indirect addressing ........................................................................................................... 145
3.4.7 Based addressing........................................................................................................................... 146
3.4.8 Based indexed addressing ............................................................................................................. 149
3.4.9 Stack addressing............................................................................................................................ 150
CHAPTER 4 PORT FUNCTIONS ......................................................................................................... 151
4.1 Port Functions ............................................................................................................................ 151
4.2 Port Configuration...................................................................................................................... 152
4.2.1 Port 0.............................................................................................................................................. 153
4.2.2 Port 1.............................................................................................................................................. 162
4.2.3 Port 2.............................................................................................................................................. 172
4.2.4 Port 3.............................................................................................................................................. 175
4.2.5 Port 4.............................................................................................................................................. 179
4.2.6 Port 5.............................................................................................................................................. 187
4.2.7 Port 6.............................................................................................................................................. 196
4.2.8 Port 7.............................................................................................................................................. 199
4.2.9 Port 8.............................................................................................................................................. 205
4.2.10 Port 10.......................................................................................................................................... 209
4.2.11 Port 11.......................................................................................................................................... 212
4.2.12 Port 12.......................................................................................................................................... 214
4.2.13 Port 13.......................................................................................................................................... 218
4.2.14 Port 14.......................................................................................................................................... 221
4.2.15 Port 15.......................................................................................................................................... 229
4.3 Registers Controlling Port Function ........................................................................................ 231
4.4 Port Function Operations .......................................................................................................... 251
4.4.1 Writing to I/O port ........................................................................................................................... 251
4.4.2 Reading from I/O port ..................................................................................................................... 251
4.4.3 Operations on I/O port .................................................................................................................... 251
4.4.4 Connecting to external device with different potential (1.8 V, 2.5 V, 3 V) ....................................... 252
4.5 Settings of Port Mode Register, and Output Latch When Using Alternate Function.......... 254
4.6 Cautions When Using Port Function........................................................................................ 262
4.6.1 Cautions on 1-Bit Manipulation Instruction for Port Register n (Pn) ............................................... 262
Index-3
4.6.2 Cautions on the pin settings on the products other than 100-pin.................................................... 263
CHAPTER 5 CLOCK GENERATOR .................................................................................................... 264
5.1 Functions of Clock Generator................................................................................................... 264
5.2 Configuration of Clock Generator ............................................................................................ 266
5.3 Registers Controlling Clock Generator.................................................................................... 268
5.4 System Clock Oscillator ............................................................................................................ 286
5.4.1 X1 oscillator.................................................................................................................................... 286
5.4.2 XT1 oscillator.................................................................................................................................. 286
5.4.3 High-speed on-chip oscillator ......................................................................................................... 290
5.4.4 Low-speed on-chip oscillator .......................................................................................................... 290
5.5 Clock Generator Operation ....................................................................................................... 291
5.6 Controlling Clock ....................................................................................................................... 293
5.6.1 Example of setting high-speed on-chip oscillator ........................................................................... 293
5.6.2 Example of setting X1 oscillation clock........................................................................................... 295
5.6.3 Example of setting XT1 oscillation clock ........................................................................................ 296
5.6.4 CPU clock status transition diagram............................................................................................... 297
5.6.5 Condition before changing CPU clock and processing after changing CPU clock ......................... 303
5.6.6 Time required for switchover of CPU clock and main system clock ............................................... 305
5.6.7 Conditions before clock oscillation is stopped ................................................................................ 306
5.7 Operation-Verified Resonators and Reference Oscillator Constants
As of December 2011 .............................................................................................................. 307
CHAPTER 6 TIMER ARRAY UNIT...................................................................................................... 311
6.1 Functions of Timer Array Unit................................................................................................... 313
6.1.1 Independent channel operation function ........................................................................................ 313
6.1.2 Simultaneous channel operation function....................................................................................... 314
6.1.3 8-bit timer operation function (channels 1 and 3 only).................................................................... 315
6.1.4 LIN-bus supporting function (channel 3 of unit 0 only) ................................................................... 316
6.2 Configuration of Timer Array Unit ............................................................................................ 317
6.3 Registers Controlling Timer Array Unit ................................................................................... 323
6.4 Basic Rules of Timer Array Unit ............................................................................................... 348
6.4.1 Basic rules of simultaneous channel operation function................................................................. 348
6.4.2 Basic rules of 8-bit timer operation function (channels 1 and 3 only) ............................................. 350
6.5 Operation Timing of Counter .................................................................................................... 351
6.5.1 Count clock (fTCLK) .......................................................................................................................... 351
6.5.2 Start timing of counter .................................................................................................................... 353
6.6 Channel Output (TOmn pin) Control ........................................................................................ 359
6.6.1 TOmn pin output circuit configuration............................................................................................. 359
6.6.2 TOmn Pin Output Setting ............................................................................................................... 360
6.6.3 Cautions on Channel Output Operation ......................................................................................... 361
Index-4
6.6.4 Collective manipulation of TOmn bit............................................................................................... 367
6.6.5 Timer Interrupt and TOmn Pin Output at Operation Start ............................................................... 368
6.7 Independent Channel Operation Function of Timer Array Unit............................................. 369
6.7.1 Operation as interval timer/square wave output ............................................................................. 369
6.7.2 Operation as external event counter .............................................................................................. 375
6.7.3 Operation as frequency divider (channel 0 of unit 0 only) .............................................................. 380
6.7.4 Operation as input pulse interval measurement ............................................................................. 384
6.7.5 Operation as input signal high-/low-level width measurement........................................................ 388
6.7.6 Operation as delay counter ............................................................................................................ 392
6.8 Simultaneous Channel Operation Function of Timer Array Unit .......................................... 397
6.8.1 Operation as one-shot pulse output function .................................................................................. 397
6.8.2 Operation as PWM function............................................................................................................ 404
6.8.3 Operation as multiple PWM output function ................................................................................... 411
6.9 Cautions When Using Timer Array Unit................................................................................... 419
6.9.1 Cautions When Using Timer output................................................................................................ 419
CHAPTER 7 TIMER RJ......................................................................................................................... 420
7.1 Overview...................................................................................................................................... 420
7.2 I/O Pins ........................................................................................................................................ 421
7.3 Registers ..................................................................................................................................... 422
7.3.1 Peripheral enable register 1 (PER1)............................................................................................... 423
7.3.2 Operation Speed Mode Control Register (OSMC) ......................................................................... 424
7.3.3 Timer RJ Counter Register 0 (TRJ0), Timer RJ Reload Register................................................... 425
7.3.4 Timer RJ Control Register 0 (TRJCR0) .......................................................................................... 426
7.3.5 Timer RJ I/O Control Register 0 (TRJIOC0) ................................................................................... 428
7.3.6 Timer RJ Mode Register 0 (TRJMR0) ............................................................................................ 430
7.3.7 Timer RJ Event Pin Select Register 0 (TRJISR0) .......................................................................... 431
7.3.8 Port mode registers 0, 3, 4, 5 (PM0, PM3, PM4, PM5) .................................................................. 432
7.4 Operation..................................................................................................................................... 433
7.4.1 Reload Register and Counter Rewrite Operation ........................................................................... 433
7.4.2 Timer Mode .................................................................................................................................... 434
7.4.3 Pulse Output Mode......................................................................................................................... 435
7.4.4 Event Counter Mode ...................................................................................................................... 436
7.4.5 Pulse Width Measurement Mode ................................................................................................... 437
7.4.6 Pulse Period Measurement Mode .................................................................................................. 438
7.4.7 Coordination with Event Link Controller (ELC) ............................................................................... 439
7.4.8 Output Settings for Each Mode ...................................................................................................... 439
7.5 Notes on Timer RJ...................................................................................................................... 440
7.5.1 Count Operation Start and Stop Control......................................................................................... 440
7.5.2 Access to Flags (Bits TEDGF and TUNDF in TRJCR0 Register)................................................... 440
7.5.3 Access to Counter Register............................................................................................................ 440
Index-5
7.5.4 When Changing Mode.................................................................................................................... 440
7.5.5 Procedure for Setting Pins TRJO0 and TRJIO0 ............................................................................. 441
7.5.6 When Timer RJ is not Used............................................................................................................ 441
7.5.7 When Timer RJ Operating Clock is Stopped .................................................................................. 441
7.5.8 Procedure for Setting STOP Mode (Event Counter Mode)............................................................. 441
7.5.9 Functional Restriction in STOP Mode (Event Counter Mode Only) ................................................ 442
7.5.10 When Count is Forcibly Stopped by TSTOP Bit ........................................................................... 442
7.5.11 Digital Filter .................................................................................................................................. 442
7.5.12 When Selecting fIL as Count Source............................................................................................. 442
CHAPTER 8 TIMER RD ........................................................................................................................ 443
8.1 Overview...................................................................................................................................... 443
8.2 Registers ..................................................................................................................................... 445
8.2.1 Peripheral enable register 1 (PER1)............................................................................................... 446
8.2.2 Timer RD ELC Register (TRDELC) ................................................................................................ 447
8.2.3 Timer RD Start Register (TRDSTR) ............................................................................................... 448
8.2.4 Timer RD Mode Register (TRDMR) ............................................................................................... 449
8.2.5 Timer RD PWM Function Select Register (TRDPMR).................................................................... 450
8.2.6 Timer RD Function Control Register (TRDFCR) ............................................................................ 451
8.2.7 Timer RD Output Master Enable Register 1 (TRDOER1) .............................................................. 453
8.2.8 Timer RD Output Master Enable Register 2 (TRDOER2) .............................................................. 454
8.2.9 Timer RD Output Control Register (TRDOCR)............................................................................... 455
8.2.10 Timer RD Digital Filter Function Select Register i (TRDDFi) (i = 0 or 1)....................................... 458
8.2.11 Timer RD Control Register i (TRDCRi) (i = 0 or 1) ....................................................................... 460
8.2.12 Timer RD I/O Control Register Ai (TRDIORAi) (i = 0 or 1)............................................................ 465
8.2.13 Timer RD I/O Control Register Ci (TRDIORCi) (i = 0 or 1) ........................................................... 467
8.2.14 Timer RD Status Register i (TRDSRi) (i = 0 or 1) ......................................................................... 469
8.2.15 Timer RD Interrupt Enable Register i (TRDIERi) (i = 0 or 1)......................................................... 473
8.2.16 Timer RD PWM Function Output Level Control Register i (TRDPOCRi) (i = 0 or 1)..................... 474
8.2.17 Timer RD Counter i (TRDi) (i = 0 or 1).......................................................................................... 475
8.2.18 Timer RD General Registers Ai, Bi, Ci, and Di (TRDGRAi, TRDGRBi,TRDGRCi, TRDGRDi)
(i = 0 or 1) .................................................................................................................................... 477
8.2.19 Port mode register 1 (PM1) .......................................................................................................... 486
8.3 Operation..................................................................................................................................... 487
8.3.1 Items Common to Multiple Modes .................................................................................................. 487
8.3.2 Input Capture Function ................................................................................................................... 495
8.3.3 Output Compare Function .............................................................................................................. 499
8.3.4 PWM Function................................................................................................................................ 504
8.3.5 Reset Synchronous PWM Mode .................................................................................................... 508
8.3.6 Complementary PWM Mode .......................................................................................................... 511
8.3.7 PWM3 Mode................................................................................................................................... 515
Index-6
8.4 Timer RD Interrupt...................................................................................................................... 518
8.5 Notes on Timer RD ..................................................................................................................... 519
8.5.1 SFR Read/Write Access................................................................................................................. 519
8.5.2 Mode Switching .............................................................................................................................. 519
8.5.3 Count Source ................................................................................................................................. 520
8.5.4 Input Capture Function ................................................................................................................... 520
8.5.5 Procedure for Setting Pins TRDIOAi, TRDIOBi, TRDIOCi, and TRDIODi (i = 0 or 1)..................... 520
8.5.6 External clock TRDCLK.................................................................................................................. 520
8.5.7 Reset Synchronous PWM Mode .................................................................................................... 521
8.5.8 Complementary PWM Mode .......................................................................................................... 521
CHAPTER 9 TIMER RG......................................................................................................................... 526
9.1 Overview...................................................................................................................................... 526
9.2 Registers ..................................................................................................................................... 528
9.2.1 Peripheral enable register 1 (PER1)............................................................................................... 529
9.2.2 Timer RG Mode Register (TRGMR) ............................................................................................... 530
9.2.3 Timer RG Count Control Register (TRGCNTC).............................................................................. 531
9.2.4 Timer RG Control Register (TRGCR)............................................................................................. 532
9.2.5 Timer RG Interrupt Enable Register (TRGIER) .............................................................................. 533
9.2.6 Timer RG Status Register (TRGSR) .............................................................................................. 534
9.2.7 Timer RG I/O Control Register (TRGIOR) ...................................................................................... 536
9.2.8 Timer RG Counter (TRG) ............................................................................................................... 538
9.2.9 Timer RG General Registers A, B, C, and D (TRGGRA, TRGGRB, TRGGRC, TRGGRD) ........... 539
9.2.10 Port mode registers 0, 5 (PM0, PM5).......................................................................................... 541
9.3 Operation..................................................................................................................................... 542
9.3.1 Items Common to Multiple Modes and Functions........................................................................... 542
9.3.2 Timer Mode (Input Capture Function) ............................................................................................ 547
9.3.3 Timer Mode (Output Compare Function)........................................................................................ 550
9.3.4 PWM Mode..................................................................................................................................... 554
9.3.5 Phase Counting Mode .................................................................................................................... 558
9.4 Notes on Timer RG..................................................................................................................... 561
9.4.1 Phase Difference, Overlap, and Pulse Width in Phase Counting Mode ......................................... 561
9.4.2 Mode Switching .............................................................................................................................. 561
9.4.3 Count Source Switching ................................................................................................................. 561
9.4.4 Procedure for Setting Pins TRGIOA and TRGIOB ......................................................................... 561
9.4.5 External Clock TRGCLKA, TRGCLKB ........................................................................................... 562
9.4.6 SFR Read/Write Access................................................................................................................. 562
9.4.7 Input Capture Operation when Count is Stopped ........................................................................... 562
CHAPTER 10 REAL-TIME CLOCK....................................................................................................... 563
10.1 Functions of Real-time Clock.................................................................................................. 563
Index-7
10.2 Configuration of Real-time Clock ........................................................................................... 563
10.3 Registers Controlling Real-time Clock................................................................................... 565
10.4 Real-time Clock Operation ...................................................................................................... 580
10.4.1 Starting operation of real-time clock ............................................................................................. 580
10.4.2 Shifting to HALT/STOP mode after starting operation.................................................................. 581
10.4.3 Reading/writing real-time clock..................................................................................................... 582
10.4.4 Setting alarm of real-time clock .................................................................................................... 584
10.4.5 1 Hz output of real-time clock ....................................................................................................... 585
10.4.6 Example of watch error correction of real-time clock.................................................................... 586
CHAPTER 11 12-BIT INTERVAL TIMER .............................................................................................. 589
11.1 Functions of 12-bit Interval Timer .......................................................................................... 589
11.2 Configuration of 12-bit Interval Timer .................................................................................... 589
11.3 Registers Controlling 12-bit Interval Timer ........................................................................... 590
11.4 12-bit Interval Timer Operation ............................................................................................... 593
CHAPTER 12 CLOCK OUTPUT/BUZZER OUTPUT CONTROLLER............................................... 594
12.1 Functions of Clock Output/Buzzer Output Controller .......................................................... 594
12.2 Configuration of Clock Output/Buzzer Output Controller.................................................... 596
12.3 Registers Controlling Clock Output/Buzzer Output Controller ........................................... 596
12.4 Operations of Clock Output/Buzzer Output Controller ........................................................ 599
12.4.1 Operation as output pin ................................................................................................................ 599
CHAPTER 13 WATCHDOG TIMER ..................................................................................................... 600
13.1 Functions of Watchdog Timer................................................................................................. 600
13.2 Configuration of Watchdog Timer .......................................................................................... 601
13.3 Register Controlling Watchdog Timer ................................................................................... 602
13.4 Operation of Watchdog Timer................................................................................................. 603
13.4.1 Controlling operation of watchdog timer ....................................................................................... 603
13.4.2 Setting overflow time of watchdog timer ....................................................................................... 604
13.4.3 Setting window open period of watchdog timer ............................................................................ 605
13.4.4 Setting watchdog timer interval interrupt ...................................................................................... 606
CHAPTER 14 A/D CONVERTER .......................................................................................................... 607
14.1 Function of A/D Converter....................................................................................................... 607
14.2 Configuration of A/D Converter .............................................................................................. 609
14.3 Registers Used in A/D Converter............................................................................................ 611
14.4 A/D Converter Conversion Operations .................................................................................. 636
14.5 Input Voltage and Conversion Results .................................................................................. 638
14.6 A/D Converter Operation Modes............................................................................................. 639
Index-8
14.6.1 Software trigger mode (select mode, sequential conversion mode) ............................................. 639
14.6.2 Software trigger mode (select mode, one-shot conversion mode) ............................................... 640
14.6.3 Software trigger mode (scan mode, sequential conversion mode)............................................... 641
14.6.4 Software trigger mode (scan mode, one-shot conversion mode) ................................................. 642
14.6.5 Hardware trigger no-wait mode (select mode, sequential conversion mode) ............................... 643
14.6.6 Hardware trigger no-wait mode (select mode, one-shot conversion mode).................................. 644
14.6.7 Hardware trigger no-wait mode (scan mode, sequential conversion mode) ................................. 645
14.6.8 Hardware trigger no-wait mode (scan mode, one-shot conversion mode) ................................... 646
14.6.9 Hardware trigger wait mode (select mode, sequential conversion mode) .................................... 647
14.6.10 Hardware trigger wait mode (select mode, one-shot conversion mode)..................................... 648
14.6.11 Hardware trigger wait mode (scan mode, sequential conversion mode) .................................... 649
14.6.12 Hardware trigger wait mode (scan mode, one-shot conversion mode) ...................................... 650
14.7 A/D Converter Setup Flowchart .............................................................................................. 651
14.7.1 Setting up software trigger mode.................................................................................................. 652
14.7.2 Setting up hardware trigger no-wait mode.................................................................................... 653
14.7.3 Setting up hardware trigger wait mode ......................................................................................... 654
14.7.4 Setup when using temperature sensor (example for software trigger mode and one-shot
conversion mode) ........................................................................................................................ 655
14.7.5 Setting up test mode .................................................................................................................... 656
14.8 SNOOZE Mode Function.......................................................................................................... 657
14.9 How to Read A/D Converter Characteristics Table............................................................... 660
14.10 Cautions for A/D Converter ................................................................................................... 662
CHAPTER 15 D/A CONVERTER .......................................................................................................... 666
15.1 Function of D/A Converter....................................................................................................... 666
15.2 Configuration of D/A Converter .............................................................................................. 667
15.3 Configuration of A/D Converter .............................................................................................. 668
15.4 Operations of D/A Converter................................................................................................... 671
15.4.1 Operation in Normal Mode ........................................................................................................... 671
15.4.2 Operation in Real-Time Output Mode........................................................................................... 672
15.5 Cautions for D/A Converter ..................................................................................................... 673
CHAPTER 16 COMPARATOR ............................................................................................................... 674
16.1 Overview.................................................................................................................................... 674
16.2 I/O Pins ...................................................................................................................................... 675
16.3 Registers ................................................................................................................................... 676
16.4 Operation................................................................................................................................... 683
16.4.1 Comparator i Digital Filter (i = 0 or 1) ........................................................................................... 686
16.4.2 Comparator i (i = 0 or 1) Interrupts ............................................................................................... 686
16.4.3 Comparator i ELC Event Output (i = 0 or 1) ................................................................................. 687
16.4.4 Comparator i Output (i = 0 or 1).................................................................................................... 688
Index-9
16.4.5 Stopping or Supplying Comparator Clock..................................................................................... 688
CHAPTER 17 SERIAL ARRAY UNIT.................................................................................................. 689
17.1 Functions of Serial Array Unit................................................................................................. 691
17.1.1 3-wire serial I/O (CSI00, CSI01, CSI10, CSI11, CSI20, CSI21, CSI30, CSI31)............................ 691
17.1.2 UART (UART0 to UART3)............................................................................................................ 692
17.1.3 Simplified I2C (IIC00, IIC01, IIC10, IIC11, IIC20, IIC21, IIC30, IIC31)........................................... 693
17.2 Configuration of Serial Array Unit .......................................................................................... 694
17.3 Registers Controlling Serial Array Unit ................................................................................. 700
17.4 Operation stop mode ............................................................................................................... 726
17.4.1 Stopping the operation by units .................................................................................................... 727
17.4.2 Stopping the operation by channels ............................................................................................. 728
17.5 Operation of 3-Wire Serial I/O (CSI00, CSI01, CSI10, CSI11, CSI20, CSI21, CSI30, CSI31)
Communication ....................................................................................................................... 729
17.5.1 Master transmission ..................................................................................................................... 732
17.5.2 Master reception........................................................................................................................... 742
17.5.3 Master transmission/reception...................................................................................................... 751
17.5.4 Slave transmission ....................................................................................................................... 760
17.5.5 Slave reception............................................................................................................................. 769
17.5.6 Slave transmission/reception........................................................................................................ 776
17.5.7 SNOOZE mode function............................................................................................................... 786
17.5.8 Calculating transfer clock frequency............................................................................................. 790
17.5.9 Procedure for processing errors that occurred during 3-wire serial I/O (CSI00, CSI01, CSI10,
CSI11, CSI20, CSI21, CSI30, CSI31) communication ................................................................. 792
17.6 Clock Synchronous Serial Communication with Slave Select Input Function.................. 793
17.6.1 Slave transmission ....................................................................................................................... 797
17.6.2 Slave reception............................................................................................................................. 807
17.6.3 Slave transmission/reception........................................................................................................ 814
17.6.4 Calculating transfer clock frequency............................................................................................. 824
17.6.5 Procedure for processing errors that occurred during Slave Select Input Function communication.. 826
17.7 Operation of UART (UART0 to UART3) Communication...................................................... 827
17.7.1 UART transmission ...................................................................................................................... 830
17.7.2 UART reception............................................................................................................................ 840
17.7.3 SNOOZE mode function............................................................................................................... 847
17.7.4 Calculating baud rate ................................................................................................................... 852
17.7.5 Procedure for processing errors that occurred during UART (UART0 to UART3) communication.... 856
17.8 LIN Communication Operation ............................................................................................... 857
17.8.1 LIN transmission........................................................................................................................... 857
17.8.2 LIN reception ................................................................................................................................ 860
17.9 Operation of Simplified I2C (IIC00, IIC01, IIC10, IIC11, IIC20, IIC21, IIC30, IIC31)
Communication ....................................................................................................................... 865
Index-10
17.9.1 Address field transmission............................................................................................................ 868
17.9.2 Data transmission......................................................................................................................... 874
17.9.3 Data reception .............................................................................................................................. 878
17.9.4 Stop condition generation............................................................................................................. 883
17.9.5 Calculating transfer rate ............................................................................................................... 884
17.9.6 Procedure for processing errors that occurred during simplified I2C (IIC00, IIC01, IIC10, IIC11,
IIC20, IIC21, IIC30, IIC31) communication .................................................................................. 887
CHAPTER 18 SERIAL INTERFACE IICA ........................................................................................... 888
18.1 Functions of Serial Interface IICA........................................................................................... 888
18.2 Configuration of Serial Interface IICA .................................................................................... 891
18.3 Registers Controlling Serial Interface IICA............................................................................ 894
18.4 I2C Bus Mode Functions .......................................................................................................... 908
18.4.1 Pin configuration........................................................................................................................... 908
18.4.2 Setting transfer clock by using IICWL0 and IICWH0 registers...................................................... 909
2
18.5 I C Bus Definitions and Control Methods .............................................................................. 911
18.5.1 Start conditions............................................................................................................................. 911
18.5.2 Addresses .................................................................................................................................... 912
18.5.3 Transfer direction specification..................................................................................................... 912
18.5.4 Acknowledge (ACK) ..................................................................................................................... 913
18.5.5 Stop condition............................................................................................................................... 914
18.5.6 Wait .............................................................................................................................................. 915
18.5.7 Canceling wait .............................................................................................................................. 917
18.5.8 Interrupt request (INTIICA0) generation timing and wait control................................................... 918
18.5.9 Address match detection method ................................................................................................. 919
18.5.10 Error detection............................................................................................................................ 919
18.5.11 Extension code........................................................................................................................... 919
18.5.12 Arbitration ................................................................................................................................... 920
18.5.13 Wakeup function......................................................................................................................... 922
18.5.14 Communication reservation........................................................................................................ 925
18.5.15 Cautions ..................................................................................................................................... 929
18.5.16 Communication operations......................................................................................................... 930
18.5.17 Timing of I2C interrupt request (INTIICA0) occurrence ............................................................... 937
18.6 Timing Charts ........................................................................................................................... 958
CHAPTER 19 DTC ................................................................................................................................. 973
19.1 Overview.................................................................................................................................... 973
19.2 Registers ................................................................................................................................... 975
19.2.1 Allocation of DTC Control Data Area and DTC Vector Table Area............................................... 976
19.2.2 DTC Control Data Allocation ........................................................................................................ 977
19.2.3 DTC Vector Table......................................................................................................................... 978
Index-11
19.2.4 Peripheral enable register 1 (PER1)............................................................................................. 981
19.2.5 DTC Control Register j (DTCCRj) (j = 0 to 23) ............................................................................. 982
19.2.6 DTC Block Size Register j (DTBLSj) (j = 0 to 23) ......................................................................... 983
19.2.7 DTC Transfer Count Register j (DTCCTj) (j = 0 to 23).................................................................. 983
19.2.8 DTC Transfer Count Reload Register j (DTRLDj) (j = 0 to 23) ..................................................... 984
19.2.9 DTC Source Address Register j (DTSARj) (j = 0 to 23) ................................................................ 984
19.2.10 DTC Destination Address Register j (DTDARj) (j = 0 to 23) ....................................................... 984
19.2.11 DTC Activation Enable Register i (DTCENi) (i = 0 to 4).............................................................. 985
19.2.12 DTC Base Address Register (DTCBAR) .................................................................................... 988
19.3 Operation................................................................................................................................... 989
19.3.1 Activation Sources........................................................................................................................ 989
19.3.2 Normal Mode................................................................................................................................ 990
19.3.3 Repeat Mode................................................................................................................................ 993
19.3.4 Chain Transfers............................................................................................................................ 997
19.4 Notes on DTC............................................................................................................................ 999
19.4.1 Setting DTC Registers and Vector Table...................................................................................... 999
19.4.2 Allocation of DTC Control Data Area and DTC Vector Table Area............................................... 999
19.4.3 DTC Pending Instruction ............................................................................................................ 1000
19.4.4 Operation when Accessing Data Flash Memory Space ............................................................. 1000
19.4.5 Number of DTC Execution Clock Cycles .................................................................................... 1001
19.4.6 DTC Response Time .................................................................................................................. 1002
19.4.7 DTC Activation Sources ............................................................................................................. 1002
19.4.8 Operation in Standby Mode Status............................................................................................. 1003
CHAPTER 20 EVENT LINK CONTROLLER (ELC) ............................................................................ 1004
20.1 Overview.................................................................................................................................. 1004
20.2 Registers ................................................................................................................................. 1005
20.2.1 Event Output Destination Select Register n (ELSELRn) (n = 00 to 25) ...................................... 1006
20.3 Operation................................................................................................................................. 1009
CHAPTER 21 INTERRUPT FUNCTIONS........................................................................................... 1010
21.1 Interrupt Function Types ....................................................................................................... 1010
21.2 Interrupt Sources and Configuration ................................................................................... 1010
21.3 Registers Controlling Interrupt Functions........................................................................... 1017
21.4 Interrupt Servicing Operations ............................................................................................. 1029
21.4.1 Maskable interrupt request acknowledgment ............................................................................. 1029
21.4.2 Software interrupt request acknowledgment .............................................................................. 1032
21.4.3 Multiple interrupt servicing.......................................................................................................... 1032
21.4.4 Interrupt servicing during division instruction.............................................................................. 1036
21.4.5 Interrupt request hold ................................................................................................................. 1037
Index-12
CHAPTER 22 KEY INTERRUPT FUNCTION ................................................................................... 1038
22.1 Functions of Key Interrupt .................................................................................................... 1038
22.2 Configuration of Key Interrupt .............................................................................................. 1038
22.3 Register Controlling Key Interrupt ....................................................................................... 1040
CHAPTER 23 STANDBY FUNCTION ................................................................................................ 1041
23.1 Standby Function and Configuration................................................................................... 1041
23.1.1 Standby function......................................................................................................................... 1041
23.1.2 Registers controlling standby function........................................................................................ 1042
23.2 Standby Function Operation ................................................................................................. 1045
23.2.1 HALT mode ................................................................................................................................ 1045
23.2.2 STOP mode................................................................................................................................ 1050
23.2.3 SNOOZE mode .......................................................................................................................... 1055
CHAPTER 24 RESET FUNCTION...................................................................................................... 1058
24.1 Register for Confirming Reset Source................................................................................. 1068
CHAPTER 25 POWER-ON-RESET CIRCUIT .................................................................................... 1070
25.1 Functions of Power-on-reset Circuit .................................................................................... 1070
25.2 Configuration of Power-on-reset Circuit.............................................................................. 1071
25.3 Operation of Power-on-reset Circuit .................................................................................... 1071
25.4 Cautions for Power-on-reset Circuit .................................................................................... 1074
CHAPTER 26 VOLTAGE DETECTOR ................................................................................................ 1076
26.1 Functions of Voltage Detector .............................................................................................. 1076
26.2 Configuration of Voltage Detector........................................................................................ 1077
26.3 Registers Controlling Voltage Detector ............................................................................... 1077
26.4 Operation of Voltage Detector .............................................................................................. 1083
26.4.1 When used as reset mode.......................................................................................................... 1083
26.4.2 When used as interrupt mode .................................................................................................... 1085
26.4.3 When used as interrupt and reset mode .................................................................................... 1087
26.5 Cautions for Voltage Detector............................................................................................... 1093
CHAPTER 27 SAFETY FUNCTIONS ................................................................................................... 1095
27.1 Overview of Safety Functions ............................................................................................... 1095
27.2 Registers Used by Safety Functions.................................................................................... 1096
27.3 Operation of Safety Functions .............................................................................................. 1096
27.3.1 Flash memory CRC operation function (high-speed CRC)......................................................... 1096
27.3.2 CRC operation function (general-purpose CRC) ........................................................................ 1100
27.3.3 RAM parity error detection function ............................................................................................ 1102
Index-13
27.3.4 RAM guard function.................................................................................................................... 1103
27.3.5 SFR guard function .................................................................................................................... 1104
27.3.6 Invalid memory access detection function .................................................................................. 1105
27.3.7 Frequency detection function ..................................................................................................... 1107
27.3.8 A/D test function ......................................................................................................................... 1109
27.3.9 Digital output signal level detection function for I/O ports........................................................... 1112
CHAPTER 28 REGULATOR ............................................................................................................... 1113
28.1 Regulator Overview................................................................................................................ 1113
CHAPTER 29 OPTION BYTE............................................................................................................. 1114
29.1 Functions of Option Bytes .................................................................................................... 1114
29.1.1 User option byte (000C0H to 000C2H/010C0H to 010C2H)....................................................... 1114
29.1.2 On-chip debug option byte (000C3H/ 010C3H).......................................................................... 1115
29.2 Format of User Option Byte .................................................................................................. 1116
29.3 Format of On-chip Debug Option Byte ................................................................................ 1122
29.4 Setting of Option Byte ........................................................................................................... 1123
CHAPTER 30 FLASH MEMORY ........................................................................................................ 1124
30.1 Writing to Flash Memory by Using Flash Memory Programmer ....................................... 1125
30.1.1 Programming Environment......................................................................................................... 1127
30.1.2 Communication Mode ................................................................................................................ 1127
30.2 Writing to Flash Memory by Using External Device (that Incorporates UART) ............... 1128
30.2.1 Programming Environment......................................................................................................... 1128
30.2.2 Communication Mode ................................................................................................................ 1129
30.3 Connection of Pins on Board................................................................................................ 1130
30.3.1 P40/TOOL0 pin .......................................................................................................................... 1130
30.3.2 RESET pin.................................................................................................................................. 1130
30.3.3 Port pins ..................................................................................................................................... 1131
30.3.4 REGC pin ................................................................................................................................... 1131
30.3.5 X1 and X2 pins ........................................................................................................................... 1131
30.3.6 Power supply.............................................................................................................................. 1131
30.4 Data Flash ............................................................................................................................... 1132
30.4.1 Data flash overview .................................................................................................................... 1132
30.4.2 Register controlling data flash memory ...................................................................................... 1133
30.4.3 Procedure for accessing data flash memory .............................................................................. 1134
30.5 Programming Method ............................................................................................................ 1135
30.5.1 Controlling flash memory............................................................................................................ 1135
30.5.2 Flash memory programming mode............................................................................................. 1136
30.5.3 Selecting communication mode.................................................................................................. 1137
Index-14
30.5.4 Communication commands ........................................................................................................ 1138
30.5.5 Description of signature data...................................................................................................... 1139
30.6 Security Settings .................................................................................................................... 1140
30.7 Flash Memory Programming by Self-Programming ........................................................... 1142
30.7.1 Boot swap function ..................................................................................................................... 1144
30.7.2 Flash shield window function...................................................................................................... 1146
CHAPTER 31 ON-CHIP DEBUG FUNCTION ................................................................................... 1147
31.1 Connecting E1 On-chip Debugging Emulator to RL78/G14............................................... 1147
31.2 On-Chip Debug Security ID ................................................................................................... 1148
31.3 Securing of User Resources ................................................................................................. 1148
CHAPTER 32 BCD CORRECTION CIRCUIT ................................................................................... 1150
32.1 BCD Correction Circuit Function.......................................................................................... 1150
32.2 Registers Used by BCD Correction Circuit ......................................................................... 1150
32.3 BCD Correction Circuit Operation ........................................................................................ 1151
CHAPTER 33 INSTRUCTION SET...................................................................................................... 1153
33.1 Conventions Used in Operation List .................................................................................... 1154
33.1.1 Operand identifiers and specification methods........................................................................... 1154
33.1.2 Description of operation column ................................................................................................. 1155
33.1.3 Description of flag operation column .......................................................................................... 1156
33.1.4 PREFIX instruction ..................................................................................................................... 1156
33.2 Operation List ......................................................................................................................... 1157
CHAPTER 34 ELECTRICAL SPECIFICATIONS ............................................................................... 1175
34.1 Pins Mounted According to Product.................................................................................... 1175
34.1.1 Port functions ............................................................................................................................. 1175
34.1.2 Non-port functions ...................................................................................................................... 1175
34.2 Absolute Maximum Ratings .................................................................................................. 1176
34.3 Oscillator Characteristics...................................................................................................... 1178
34.3.1 Main system clock oscillator characteristics ............................................................................... 1178
34.3.2 On-chip oscillator characteristics................................................................................................ 1179
34.3.3 Subsystem clock oscillator characteristics.................................................................................. 1180
34.4 DC Characteristics ................................................................................................................. 1181
34.4.1 Pin characteristics ...................................................................................................................... 1181
34.4.2 Supply current characteristics .................................................................................................... 1186
34.5 AC Characteristics ................................................................................................................. 1196
34.5.1 Basic operation........................................................................................................................... 1196
34.6 Peripheral Functions Characteristics .................................................................................. 1198
Index-15
34.6.1 Serial array unit .......................................................................................................................... 1198
34.6.2 Serial interface IICA ................................................................................................................... 1222
34.6.3 On-chip debug (UART)............................................................................................................... 1223
34.7 Analog Characteristics .......................................................................................................... 1223
34.7.1 A/D converter characteristics...................................................................................................... 1223
34.7.2 Temperature sensor characteristics ........................................................................................... 1227
34.7.3 D/A converter characteristics...................................................................................................... 1227
34.7.4 Comparator ................................................................................................................................ 1228
34.7.5 POR circuit characteristics ......................................................................................................... 1228
34.7.6 LVD circuit characteristics .......................................................................................................... 1229
34.8 Power Supply Rise Time........................................................................................................ 1231
34.9 Data Memory STOP Mode Low Supply Voltage Data Retention Characteristics ............ 1231
34.10 Flash Memory Programming Characteristics.................................................................... 1231
34.11 Timing Specs for Switching Modes.................................................................................... 1232
CHAPTER 35 PACKAGE DRAWINGS ............................................................................................... 1233
35.1 30-pin products ...................................................................................................................... 1234
35.2 32-pin products ...................................................................................................................... 1235
35.3 36-pin products ...................................................................................................................... 1237
35.4 40-pin products ...................................................................................................................... 1238
35.5 44-pin products ...................................................................................................................... 1239
35.6 48-pin products ...................................................................................................................... 1240
35.7 52-pin products ...................................................................................................................... 1242
35.8 64-pin products ...................................................................................................................... 1243
35.9 80-pin products ...................................................................................................................... 1247
35.10 100-pin products .................................................................................................................. 1249
APPENDIX A REVISION HISTORY ................................................................................................... 1251
A.1 Major Revisions in This Edition ............................................................................................. 1251
A.2 Revision History of Preceding Editions ................................................................................ 1258
Index-16
R01UH0186EJ0100
Rev.1.00
RL78/G14
RENESAS MCU
Dec 28, 2011
CHAPTER 1 OUTLINE
1.1 Features
{ Minimum instruction execution time can be changed from high speed (0.03125 μs: @ 32 MHz operation with highspeed on-chip oscillator clock) to ultra low-speed (30.5 μs: @ 32.768 kHz operation with subsystem clock)
{ General-purpose register: 8 bits × 32 registers (8 bits × 8 registers × 4 banks)
{ ROM: 16 to 256 KB, RAM: 2.5 to 24 KB, Data flash memory: 4/8 KB
{ High-speed on-chip oscillator clocks
• Selectable from 64 MHz (TYP.), 48 MHz (TYP.), 32 MHz (TYP.), 24 MHz (TYP.), 16 MHz (TYP.), 12 MHz (TYP.),
8 MHz (TYP.), 4 MHz (TYP.), and 1 MHz (TYP.)
{ On-chip single-power-supply flash memory (with prohibition of block erase/writing function)
{ Self-programming (with boot swap function/flash shield window function)
{ On-chip debug function
{ On-chip power-on-reset (POR) circuit and voltage detector (LVD)
{ On-chip watchdog timer (operable with the dedicated low-speed on-chip oscillator clock)
{ Multiply/divide/multiply & accumulate instructions are supported.
{ On-chip key interrupt function
{ On-chip clock output/buzzer output controller
{ On-chip BCD adjustment
{ I/O ports: 26 to 92 (N-ch open-drain: 2 to 4)
{ Timer
•16-bit timer
: 8 to 12 channels
(TAU: 4 to 8 channels, Timer RJ: 1 channel, Timer RD: 2 channels, Timer RG: 1
• Watchdog timer
channel)
: 1 channel
• Real-time clock
: 1 channel (Correction clock output)
• 12-bit interval timer
: 1 channel
{ Serial interface
• CSI
• UART/UART (LIN-bus supported)
• I2C/Simplified I2C communication
{ Different potential interface: Can connect to a 2.5/3 V device when operating at 4.0 V to 5.5 V
{ 8/10-bit resolution A/D converter (VDD = EVDD =1.6 to 5.5 V): 8 to 20 channels
{ Standby function: HALT, STOP, SNOOZE mode
{ On-chip D/A converter
{ On-chip Comparator
{ On-chip data transfer controller (DTC)
{ On-chip event link controller (ELC)
{ Power supply voltage: VDD = 1.6 to 5.5 V
{ Operating ambient temperature: TA = −40 to +85°C
Remark The functions mounted depend on the product. See 1.6 Outline of Functions.
R01UH0186EJ0100 Rev.1.00
Dec 28, 2011
1
RL78/G14
CHAPTER 1 OUTLINE
{ ROM, RAM capacities
Flash ROM Data flash
RAM
RL78/G14
30 pins
32 pins
36 pins
40 pins
192 KB
8 KB
20 KB
--
--
--
R5F104EH
128 KB
8 KB
16KB
R5F104AG
R5F104BG
R5F104CG
R5F104EG
96 KB
8KB
12 KB
R5F104AF
R5F104BF
R5F104CF
R5F104EF
R5F104AE
R5F104BE
R5F104CE
R5F104EE
R5F104AD
R5F104BD
R5F104CD
R5F104ED
64 KB
4 KB
5.5 KB
Note 1
48 KB
4 KB
32 KB
4 KB
4 KB
R5F104AC
R5F104BC
R5F104CC
R5F104EC
16 KB
4 KB
2.5 KB
R5F104AA
R5F104BA
R5F104CA
R5F104EA
Flash ROM Data flash
5.5 KB
Note 1
RAM
24 KB
Note 2
RL78/G14
44 pins
48 pins
52 pins
64 pins
R5F104FJ
R5F104GJ
R5F104JJ
R5F104LJ
256 KB
8 KB
192 KB
8 KB
20 KB
R5F104FH
R5F104GH
R5F104JH
R5F104LH
128 KB
8 KB
16 KB
R5F104FG
R5F104GG
R5F104JG
R5F104LG
96 KB
8 KB
12 KB
R5F104FF
R5F104GF
R5F104JF
R5F104LF
64 KB
4 KB
R5F104FE
R5F104GE
R5F104JE
R5F104LE
R5F104FD
R5F104GD
R5F104JD
R5F104LD
5.5 KB
Note 1
48 KB
4 KB
32 KB
4 KB
4 KB
R5F104FC
R5F104GC
R5F104JC
R5F104LC
16 KB
4 KB
2.5 KB
R5F104FA
R5F104GA
--
--
Flash ROM Data flash
5.5 KB
Note 1
RAM
24 KB
Note 2
RL78/G14
80 pins
100 pins
R5F104MJ
R5F104PJ
256 KB
8 KB
192 KB
8 KB
20 KB
R5F104MH
R5F104PH
128 KB
8 KB
16 KB
R5F104MG
R5F104PG
96 KB
8 KB
12 KB
R5F104MF
R5F104PF
Notes 1. This is about 4.5 KB when the self-programming function and data flash function are used. (For details, see
CHAPTER 3)
2. This is about 23 KB when the self-programming function and data flash function are used. (For details, see
CHAPTER 3)
R01UH0186EJ0100 Rev.1.00
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2
RL78/G14
CHAPTER 1 OUTLINE
<R> 1.2 Ordering Information
(1/2)
Pin count
30 pins
Package
30-pin plastic SSOP (7.62 mm (300))
Part Number
R5F104AAASP, R5F104ACASP, R5F104ADASP, R5F104AEASP,
R5F104AFASP, R5F104AGASP
R5F104AADSP, R5F104ACDSP, R5F104ADDSP, R5F104AEDSP,
R5F104AFDSP, R5F104AGDSP
32 pins
32-pin plastic WQFN (fine pitch) (5 × 5)
R5F104BAANA, R5F104BCANA, R5F104BDANA, R5F104BEANA,
R5F104BFANA, R5F104BGANA
R5F104BADNA, R5F104BCDNA, R5F104BDDNA, R5F104BEDNA,
R5F104BFDNA, R5F104BGDNA
32-pin plastic LQFP (7 × 7)
R5F104BAAFP, R5F104BCAFP, R5F104BDAFP, R5F104BEAFP,
R5F104BFAFP, R5F104BGAFP
R5F104BADFP, R5F104BCDFP, R5F104BDDFP, R5F104BEDFP,
R5F104BFDFP, R5F104BGDFP
36 pins
36-pin plastic FLGA (4 × 4)
R5F104CAALA, R5F104CCALA, R5F104CDALA, R5F104CEALA,
R5F104CFALA, R5F104CGALA
R5F104CADLA, R5F104CCDLA, R5F104CDDLA, R5F104CEDLA,
R5F104CFDLA, R5F104CGDLA
40 pins
40-pin plastic WQFN (fine pitch)(6 × 6)
R5F104EAANA, R5F104ECANA, R5F104EDANA, R5F104EEANA,
R5F104EFANA, R5F104EGANA, R5F104EHANA
R5F104EADNA, R5F104ECDNA, R5F104EDDNA, R5F104EEDNA,
R5F104EFDNA, R5F104EGDNA, R5F104EHDNA
44 pins
44-pin plastic LQFP (10 × 10)
R5F104FAAFP, R5F104FCAFP, R5F104FDAFP, R5F104FEAFP,
R5F104FFAFP, R5F104FGAFP,R5F104FHAFP, R5F104FJAFP
R5F104FADFP, R5F104FCDFP, R5F104FDDFP, R5F104FEDFP,
R5F104FFDFP, R5F104FGDFP,R5F104FHDFP, R5F104FJDFP
48 pins
48-pin plastic LQFP (fine pitch) (7 × 7)
R5F104GAAFB, R5F104GCAFB, R5F104GDAFB, R5F104GEAFB,
R5F104GFAFB, R5F104GGAFB, R5F104GHAFB, R5F104GJAFB
R5F104GADFB, R5F104GCDFB, R5F104GDDFB, R5F104GEDFB,
R5F104GFDFB, R5F104GGDFB, R5F104GHDFB, R5F104GJDFB
48-pin plastic WQFN (7 × 7)
R5F104GAANA, R5F104GCANA, R5F104GDANA, R5F104GEANA,
R5F104GFANA, R5F104GGANA, R5F104GHANA, R5F104GJANA
R5F104GADNA, R5F104GCDNA, R5F104GDDNA, R5F104GEDNA,
R5F104GFDNA, R5F104GGDNA, R5F104GHDNA, R5F104GJDNA
52 pins
52-pin plastic LQFP (10 × 10)
R5F104JCAFA, R5F104JDAFA, R5F104JEAFA, R5F104JFAFA,
R5F104JGAFA, R5F104JHAFA, R5F104JJAFA
R5F104JCDFA, R5F104JDDFA, R5F104JEDFA, R5F104JFDFA,
R5F104JGDFA, R5F104JHDFA, R5F104JJDFA
R01UH0186EJ0100 Rev.1.00
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RL78/G14
CHAPTER 1 OUTLINE
(2/2)
Pin count
64 pins
Package
64-pin plastic LQFP (12 × 12)
Part Number
R5F104LCAFA, R5F104LDAFA, R5F104LEAFA, R5F104LFAFA,
R5F104LGAFA, R5F104LHAFA, R5F104LJAFA
R5F104LCDFA, R5F104LDDFA, R5F104LEDFA, R5F104LFDFA,
R5F104LGDFA, R5F104LHDFA, R5F104LJDFA
64-pin plastic LQFP (fine pitch) (10 × 10)
R5F104LCAFB, R5F104LDAFB, R5F104LEAFB, R5F104LFAFB,
R5F104LGAFB, R5F104LHAFB, R5F104LJAFB
R5F104LCDFB, R5F104LDDFB, R5F104LEDFB, R5F104LFDFB,
R5F104LGDFB, R5F104LHDFB, R5F104LJDFB
64-pin plastic FLGA (5 × 5)
R5F104LCALA, R5F104LDALA, R5F104LEALA, R5F104LFALA,
R5F104LGALA, R5F104LHALA, R5F104LJALA
R5F104LCDLA, R5F104LDDLA, R5F104LEDLA, R5F104LFDLA,
R5F104LGDLA, R5F104LHDLA, R5F104LJDLA
64-pin plastic LQFP (14 × 14)
R5F104LCAFP, R5F104LDAFP, R5F104LEAFP, R5F104LFAFP,
R5F104LGAFP, R5F104LHAFP, R5F104LJAFP
R5F104LCDFP, R5F104LDDFP, R5F104LEDFP, R5F104LFDFP,
R5F104LGDFP, R5F104LHDFP, R5F104LJDFP
80 pins
80-pin plastic LQFP (fine pitch) (12 × 12)
R5F104MFAFB, R5F104MGAFB, R5F104MHAFB, R5F104MJAFB
R5F104MFDFB, R5F104MGDFB, R5F104MHDFB, R5F104MJDFB
80-pin plastic LQFP (14 × 14)
R5F104MFAFA, R5F104MGAFA, R5F104MHAFA, R5F104MJAFA
R5F104MFDFA, R5F104MGDFA, R5F104MHDFA, R5F104MJDFA
100 pins
100-pin plastic LQFP (fine pitch) (14 × 14)
R5F104PFAFB, R5F104PGAFB, R5F104PHAFB, R5F104PJAFB
100-pin plastic LQFP (14 × 20)
R5F104PFAFA, R5F104PGAFA, R5F104PHAFA, R5F104PJAFA
R5F104PFDFB, R5F104PGDFB, R5F104PHDFB, R5F104PJDFB
R5F104PFDFA, R5F104PGDFA, R5F104PHDFA, R5F104PJDFA
R01UH0186EJ0100 Rev.1.00
Dec 28, 2011
4
RL78/G14
<R>
CHAPTER 1 OUTLINE
Figure 1-1. Part Number, Memory Size, and Package of RL78/G14
Part No. R 5 F 1 0 4 L E A x x x F B
Package type:
SP : SSOP, 0.65 mm pitch
FP : LQFP, 0.80 mm pitch
FA : LQFP, 0.65 mm pitch
FB : LQFP, 0.50 mm pitch
NA : WQFN, 0.50 mm pitch
LA : LGA, 0.50 mm pitch
ROM number (Omitted with blank products)
Classification:
A : Consumer applications, operating ambient temperature : −40˚C to 85˚C
D : Industrial applications, operating ambient temperature : −40˚C to 85˚C
ROM capacity:
A : 16 KB
C : 32 KB
D : 48 KB
E : 64 KB
F : 96 KB
G : 128 KB
H : 192 KB
J : 256 KB
Pin count:
A : 30-pin
B : 32-pin
C : 36-pin
E : 40-pin
F : 44-pin
G : 48-pin
J : 52-pin
L : 64-pin
M : 80-pin
P : 100-pin
RL78/G14
Memory type:
F : Flash memory
Renesas MCU
Renesas semiconductor product
R01UH0186EJ0100 Rev.1.00
Dec 28, 2011
5
RL78/G14
CHAPTER 1 OUTLINE
<R> 1.3 Pin Configuration (Top View)
1.3.1 30-pin products
• 30-pin plastic SSOP (7.62 mm (300))
P20/ANI0/AVREFP
P01/ANI16/TO00/RxD1/TRGCLKB/TRJIO0
P00/ANI17/TI00/TxD1/TRGCLKA/(TRJO0)
P120/ANI19/VCOUT0 Note
P40/TOOL0
RESET
P137/INTP0
P122/X2/EXCLK
P121/X1
REGC
VSS
VDD
P60/SCLA0
P61/SDAA0
P31/TI03/TO03/INTP4/PCLBUZ0/SSI00/(TRJIO0)
Note
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
P21/ANI1/AVREFM
P22/ANI2/ANO0Note
P23/ANI3
P147/ANI18/VCOUT1Note
P10/SCK11/SCL11/TRDIOD1
P11/SI11/SDA11/TRDIOC1
P12/SO11/TRDIOB1/IVREF1Note
P13/TxD2/SO20/TRDIOA1/IVCMP1Note
P14/RxD2/SI20/SDA20/TRDIOD0/(SCLA0)
P15/PCLBUZ1/SCK20/SCL20/TRDIOB0/(SDAA0)
P16/TI01/TO01/INTP5/TRDIOC0/IVREF0 Note/(RXD0)
P17/TI02/TO02/TRDIOA0/TRDCLK0/IVCMP0 Note/(TXD0)
P51/INTP2/SO00/TxD0/TOOLTxD/TRGIOB
P50/INTP1/SI00/RxD0/TOOLRxD/SDA00/TRGIOA/(TRJO0)
P30/INTP3/SCK00/SCL00/TRJO0
Mounted on the 96 KB or more code flash memory products.
Caution Connect the REGC pin to Vss pin via a capacitor (0.47 to 1 μF).
Remarks 1. For pin identification, see 1.4 Pin Identification.
2. Functions in parentheses in the above figure can be assigned via settings in the peripheral I/O redirection
register 0, 1 (PIOR0, 1).
R01UH0186EJ0100 Rev.1.00
Dec 28, 2011
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RL78/G14
CHAPTER 1 OUTLINE
1.3.2 32-pin products
• 32-pin plastic WQFN (fine pitch) (5 × 5)
P10/SCK11/SCL11/TRDIOD1
P11/SI11/SDA11/TRDIOC1
P12/SO11/TRDIOB1/IVREF1Note
P13/TxD2/SO20/TRDIOA1/IVCMP1Note
P14/RxD2/SI20/SDA20/TRDIOD0/(SCLA0)
P15/PCLBUZ1/SCK20/SCL20/TRDIOB0/(SDAA0)
P16/TI01/TO01/INTP5/TRDIOC0/IVREF0 Note/(RXD0)
P17/TI02/TO02/TRDIOA0/TRDCLK0/IVCMP0Note/(TXD0)
• 32-pin plastic LQFP (7 × 7)
exposed die pad
24 23 22 21 20 19 18 17
25
16
26
15
27
14
28
13
29
12
30
11
31
10
32
9
1 2 3 4 5 6 7 8
P51/INTP2/SO00/TxD0/TOOLTxD/TRGIOB
P50/INTP1/SI00/RxD0/TOOLRxD/SDA00/TRGIOA/(TRJO0)
P30/INTP3/SCK00/SCL00/TRJO0
P70
P31/TI03/TO03/INTP4/PCLBUZ0/(TRJIO0)
P62/SSI00
P61/SDAA0
P60/SCLA0
P40/TOOL0
RESET
P137/INTP0
P122/X2/EXCLK
P121/X1
REGC
VSS
VDD
P147/ANI18/VCOUT1Note
P23/ANI3/ANO1Note
P22/ANI2/ANO0 Note
P21/ANI1/AVREFM
P20/ANI0/AVREFP
P01/ANI16/TO00/RxD1/TRGCLKB/TRJIO0
P00/ANI17/TI00/TxD1/TRGCLKA/(TRJO0)
P120/ANI19/VCOUT0 Note
Note
Mounted on the 96 KB or more code flash memory products.
Caution Connect the REGC pin to Vss pin via a capacitor (0.47 to 1 μF).
Remarks 1. For pin identification, see 1.4 Pin Identification.
2. Functions in parentheses in the above figure can be assigned via settings in the peripheral I/O redirection
register 0, 1 (PIOR0, 1).
R01UH0186EJ0100 Rev.1.00
Dec 28, 2011
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RL78/G14
CHAPTER 1 OUTLINE
1.3.3 36-pin products
• 36-pin plastic FLGA (4 × 4)
Top View
Bottom View
6
5
4
3
2
1
A
B
C
D
E
F
F
E
D
C
B
A
INDEX MARK
A
P60/SCLA0
B
VDD
C
P121/X1
D
P122/X2/EXCLK
E
P137/INTP0
F
P40/TOOL0
6
6
P62/SSI00
P61/SDAA0
VSS
REGC
RESET
5
P72/SO21
P71/SI21/
SDA21
P14/RxD2/SI20/S
DA20/TRDIOD0/
(SCLA0)
P31/TI03/TO03/
INTP4/PCLBUZ0/
(TRJIO0)
P00/TI00/TxD1/
TRGCLKA/
(TRJO0)
P01/TO00/
RxD1/
TRGCLKB/
TRJIO0
P50/INTP1/
SI00/RxD0/
TOOLRxD/
SDA00/TRGIOA
/(TRJO0)
P70/SCK21/
SCL21
P15/PCLBUZ1/
SCK20/SCL20/
TRDIOB0/
(SDAA0)
P22/ANI2/
Note
ANO0
P20/ANI0/
AVREFP
P21/ANI1/
AVREFM
P30/INTP3/
SCK00/SCL00/
TRJO0
P16/TI01/TO01/
INTP5/TRDIOC0/
Note
IVREF0
/(RXD0)
P12/SO11/
TRDIOB1/
Note
IVREF1
P11/SI11/
SDA11/
TRDIOC1
P24/ANI4
P51/INTP2/
SO00/TxD0/
TOOLTxD/
TRGIOB
P17/TI02/TO02/T
RDIOA0/
TRDCLK0/
Note
IVCMP0
/(TXD0)
B
P13/TxD2/
SO20/TRDIOA1/
Note
IVCMP1
P10/SCK11/
SCL11/
TRDIOD1
P147/ANI18/
Note
VCOUT1
4
3
2
1
A
Note
P120/ANI19/
Note
VCOUT0
5
4
3
C
P23/ANI3/ANO1
Note
2
D
P25/ANI5
1
E
F
Mounted on the 96 KB or more code flash memory products.
Caution Connect the REGC pin to Vss pin via a capacitor (0.47 to 1 μF).
Remarks 1. For pin identification, see 1.4 Pin Identification.
2. Functions in parentheses in the above figure can be assigned via settings in the peripheral I/O redirection
register 0, 1 (PIOR0, 1).
R01UH0186EJ0100 Rev.1.00
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RL78/G14
CHAPTER 1 OUTLINE
1.3.4 40-pin products
P147/ANI18/VCOUT1Note
P10/SCK11/SCL11/TRDIOD1
P11/SI11/SDA11/TRDIOC1
P12/SO11/TRDIOB1/IVREF1Note
P13/TxD2/SO20/TRDIOA1/IVCMP1Note
P14/RxD2/SI20/SDA20/TRDIOD0/(SCLA0)
P15/PCLBUZ1/SCK20/SCL20/TRDIOB0/(SDAA0)
P16/TI01/TO01/INTP5/TRDIOC0/IVREF0 Note/(RXD0)
P17/TI02/TO02/TRDIOA0/TRDCLK0/IVCMP0 Note/(TXD0)
P51/INTP2/SO00/TxD0/TOOLTxD/TRGIOB
• 40-pin plastic WQFN (fine pitch) (6 × 6)
30 29 28 27 26 25 24 23 22 21
31
20
exposed die pad
32
19
33
18
34
17
35
16
36
15
37
14
38
13
39
12
40
11
1 2 3 4 5 6 7 8 9 10
P50/INTP1/SI00/RxD0/TOOLRxD/SDA00/TRGIOA/(TRJO0)
P30/INTP3/RTC1HZ/SCK00/SCL00/TRJO0
P70/KR0/SCK21/SCL21
P71/KR1/SI21/SDA21
P72/KR2/SO21
P73/KR3
P31/TI03/TO03/INTP4/PCLBUZ0/(TRJIO0)
P62/SSI00
P61/SDAA0
P60/SCLA0
P40/TOOL0
RESET
P124/XT2/EXCLKS
P123/XT1
P137/INTP0
P122/X2/EXCLK
P121/X1
REGC
VSS
VDD
P26/ANI6
P25/ANI5
P24/ANI4
P23/ANI3/ANO1Note
P22/ANI2/ANO0 Note
P21/ANI1/AVREFM
P20/ANI0/AVREFP
P01/TO00/RxD1/TRGCLKB/TRJIO0
P00/TI00/TxD1/TRGCLKA/(TRJO0)
P120/ANI19/VCOUT0 Note
Note
Mounted on the 96 KB or more code flash memory products.
Caution Connect the REGC pin to Vss pin via a capacitor (0.47 to 1 μF).
Remarks 1. For pin identification, see 1.4 Pin Identification.
2. Functions in parentheses in the above figure can be assigned via settings in the peripheral I/O redirection
register 0, 1 (PIOR0, 1).
R01UH0186EJ0100 Rev.1.00
Dec 28, 2011
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RL78/G14
CHAPTER 1 OUTLINE
1.3.5 44-pin products
P147/ANI18/VCOUT1Note
P146
P10/SCK11/SCL11/TRDIOD1
P11/SI11/SDA11/TRDIOC1
P12/SO11/TRDIOB1/IVREF1Note
P13/TxD2/SO20/TRDIOA1/IVCMP1Note
P14/RxD2/SI20/SDA20/TRDIOD0/(SCLA0)
P15/PCLBUZ1/SCK20/SCL20/TRDIOB0/(SDAA0)
P16/TI01/TO01/INTP5/TRDIOC0/IVREF0 Note/(RXD0)
P17/TI02/TO02/TRDIOA0/TRDCLK0/IVCMP0Note/(TXD0)
P51/INTP2/SO00/TxD0/TOOLTxD/TRGIOB
• 44-pin plastic LQFP (10 × 10)
33 32 31 30 29 28 27 26 25 24 23
34
35
36
37
38
39
40
41
42
43
44
22
21
20
19
18
17
16
15
14
13
12
1 2 3 4 5 6 7 8 9 10 11
P50/INTP1/SI00/RxD0/TOOLRxD/SDA00/TRGIOA/(TRJO0)
P30/INTP3/RTC1HZ/SCK00/SCL00/TRJO0
P70/KR0/SCK21/SCL21
P71/KR1/SI21/SDA21
P72/KR2/SO21
P73/KR3
P31/TI03/TO03/INTP4/PCLBUZ0/(TRJIO0)
P63
P62/SSI00
P61/SDAA0
P60/SCLA0
P41
P40/TOOL0
RESET
P124/XT2/EXCLKS
P123/XT1
P137/INTP0
P122/X2/EXCLK
P121/X1
REGC
VSS
VDD
P27/ANI7
P26/ANI6
P25/ANI5
P24/ANI4
P23/ANI3/ANO1Note
P22/ANI2/ANO0 Note
P21/ANI1/AVREFM
P20/ANI0/AVREFP
P01/TO00/RxD1/TRGCLKB/TRJIO0
P00/TI00/TxD1/TRGCLKA/(TRJO0)
P120/ANI19/VCOUT0 Note
Note
Mounted on the 96 KB or more code flash memory products.
Caution Connect the REGC pin to Vss pin via a capacitor (0.47 to 1 μF).
Remarks 1. For pin identification, see 1.4 Pin Identification.
2. Functions in parentheses in the above figure can be assigned via settings in the peripheral I/O redirection
register 0, 1 (PIOR0, 1).
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RL78/G14
CHAPTER 1 OUTLINE
1.3.6 48-pin products
P140/PCLBUZ0/INTP6
P00/TI00/TxD1/TRGCLKA/(TRJO0)
P01/TO00/RxD1/TRGCLKB/TRJIO0
P130
P20/ANI0/AVREFP
P21/ANI1/AVREFM
P22/ANI2/ANO0Note
P23/ANI3/ANO1Note
P24/ANI4
P25/ANI5
P26/ANI6
P27/ANI7
• 48-pin plastic LQFP (fine pitch) (7 × 7)
36 35 34 33 32 31 30 29 28 27 26 25
24
37
23
38
22
39
21
40
20
41
19
42
18
43
17
44
16
45
15
46
14
47
13
48
1 2 3 4 5 6 7 8 9 10 11 12
P147/ANI18/VCOUT1Note
P146
P10/SCK11/SCL11/TRDIOD1
P11/SI11/SDA11/TRDIOC1
P12/SO11/TRDIOB1/IVREF1Note
P13/TxD2/SO20/TRDIOA1/IVCMP1Note
P14/RxD2/SI20/SDA20/TRDIOD0/(SCLA0)
P15/PCLBUZ1/SCK20/SCL20/TRDIOB0/(SDAA0)
P16/TI01/TO01/INTP5/TRDIOC0/IVREF0 Note/(RXD0)
P17/TI02/TO02/TRDIOA0/TRDCLK0/IVCMP0 Note/(TXD0)
P51/INTP2/SO00/TxD0/TOOLTxD/TRGIOB
P50/INTP1/SI00/RxD0/TOOLRxD/SDA00/TRGIOA/(TRJO0)
P60/SCLA0
P61/SDAA0
P62/SSI00
P63
P31/TI03/TO03/INTP4/(PCLBUZ0)/(TRJIO0)
P75/KR5/INTP9/SCK01/SCL01
P74/KR4/INTP8/SI01/SDA01
P73/KR3/SO01
P72/KR2/SO21
P71/KR1/SI21/SDA21
P70/KR0/SCK21/SCL21
P30/INTP3/RTC1HZ/SCK00/SCL00/TRJO0
P120/ANI19/VCOUT0 Note
P41/(TRJIO0)
P40/TOOL0
RESET
P124/XT2/EXCLKS
P123/XT1
P137/INTP0
P122/X2/EXCLK
P121/X1
REGC
VSS
VDD
Note
Mounted on the 96 KB or more code flash memory products.
Caution Connect the REGC pin to Vss pin via a capacitor (0.47 to 1 μF).
Remarks 1. For pin identification, see 1.4 Pin Identification.
2. Functions in parentheses in the above figure can be assigned via settings in the peripheral I/O redirection
register 0, 1 (PIOR0, 1).
R01UH0186EJ0100 Rev.1.00
Dec 28, 2011
11
RL78/G14
CHAPTER 1 OUTLINE
P140/PCLBUZ0/INTP6
P00/TI00/TxD1/TRGCLKA/(TRJO0)
P01/TO00/RxD1/TRGCLKB/TRJIO0
P130
P20/ANI0/AVREFP
P21/ANI1/AVREFM
P22/ANI2/ANO0 Note
P23/ANI3/ANO1Note
P24/ANI4
P25/ANI5
P26/ANI6
P27/ANI7
• 48-pin plastic WQFN (7 × 7)
36 35 34 33 32 31 30 29 28 27 26 25
24
37
23
exposed die pad
38
22
39
21
40
20
41
19
42
18
43
17
44
16
45
15
46
14
47
13
48
1 2 3 4 5 6 7 8 9 10 11 12
P147/ANI18/VCOUT1Note
P146
P10/SCK11/SCL11/TRDIOD1
P11/SI11/SDA11/TRDIOC1
P12/SO11/TRDIOB1/IVREF1Note
P13/TxD2/SO20/TRDIOA1/IVCMP1Note
P14/RxD2/SI20/SDA20/TRDIOD0/(SCLA0)
P15/PCLBUZ1/SCK20/SCL20/TRDIOB0/(SDAA0)
P16/TI01/TO01/INTP5/TRDIOC0/IVREF0 Note/(RXD0)
P17/TI02/TO02/TRDIOA0/TRDCLK0/IVCMP0 Note/(TXD0)
P51/INTP2/SO00/TxD0/TOOLTxD/TRGIOB
P50/INTP1/SI00/RxD0/TOOLRxD/SDA00/TRGIOA/(TRJO0)
P60/SCLA0
P61/SDAA0
P62/SSI00
P63
P31/TI03/TO03/INTP4/(PCLBUZ0)/(TRJIO0)
P75/KR5/INTP9/SCK01/SCL01
P74/KR4/INTP8/SI01/SDA01
P73/KR3/SO01
P72/KR2/SO21
P71/KR1/SI21/SDA21
P70/KR0/SCK21/SCL21
P30/INTP3/RTC1HZ/SCK00/SCL00/TRJO0
P120/ANI19/VCOUT0 Note
P41/(TRJIO0)
P40/TOOL0
RESET
P124/XT2/EXCLKS
P123/XT1
P137/INTP0
P122/X2/EXCLK
P121/X1
REGC
VSS
VDD
Note
Mounted on the 96 KB or more code flash memory products.
Caution Connect the REGC pin to Vss pin via a capacitor (0.47 to 1 μF).
Remarks 1. For pin identification, see 1.4 Pin Identification.
2. Functions in parentheses in the above figure can be assigned via settings in the peripheral I/O redirection
register 0, 1 (PIOR0, 1).
R01UH0186EJ0100 Rev.1.00
Dec 28, 2011
12
RL78/G14
CHAPTER 1 OUTLINE
P30/INTP3/RTC1HZ/SCK00/SCL00/TRJO0
P51/INTP2/SO00/TxD0/TOOLTxD/TRGIOB
P17/TI02/TO02/TRDIOA0/TRDCLK0/IVCMP0Note/(TXD0)
P16/TI01/TO01/INTP5/TRDIOC0/IVREF0 Note/(RXD0)
P15/PCLBUZ1/SCK20/SCL20/TRDIOB0/(SDAA0)
P14/RxD2/SI20/SDA20/TRDIOD0/(SCLA0)
P13/TxD2/SO20/TRDIOA1/IVCMP1Note
P12/SO11/TRDIOB1/IVREF1Note
P11/SI11/SDA11/TRDIOC1
P10/SCK11/SCL11/TRDIOD1
P146
P147/ANI18/VCOUT1Note
• 52-pin plastic LQFP (10 × 10)
P50/INTP1/SI00/RxD0/TOOLRxD/SDA00/TRGIOA/(TRJO0)
1.3.7 52-pin products
39 38 37 36 35 34 33 32 31 30 29 28 27
24
P72/KR2/SO21
P24/ANI4
43
23
P73/KR3/SO01
P23/ANI3/ANO1Note
44
22
P74/KR4/INTP8/SI01/SDA01
P22/ANI2/ANO0 Note
45
21
P75/KR5/INTP9/SCK01/SCL01
P21/ANI1/AVREFM
46
20
P76/KR6/INTP10/(RXD2)
P20/ANI0/AVREFP
47
19
P77/KR7/INTP11/(TXD2)
P130
48
18
P31/TI03/TO03/INTP4/(PCLBUZ0)/(TRJIO0)
P03/ANI16/RxD1
49
17
P63
P02/ANI17/TxD1
50
16
P62/SSI00
P01/TO00/TRGCLKB/TRJIO0
51
15
P61/SDAA0
P00/TI00/TRGCLKA/(TRJO0)
52
14
P60/SCLA0
Note
VDD
VSS
REGC
8 9 10 11 12 13
P121/X1
6 7
P122/X2/EXCLK
5
P123/XT1
3 4
P40/TOOL0
2
P120/ANI19/VCOUT0
1
P137/INTP0
42
P124/XT2/EXCLKS
P71/KR1/SI21/SDA21
P25/ANI5
RESET
25
P41/(TRJIO0)
P70/KR0/SCK21/SCL21
41
Note
26
P26/ANI6
P140/PCLBUZ0/INTP6
P27/ANI7
40
Mounted on the 96 KB or more code flash memory products.
Caution Connect the REGC pin to Vss pin via a capacitor (0.47 to 1 μF).
Remarks 1. For pin identification, see 1.4 Pin Identification.
2. Functions in parentheses in the above figure can be assigned via settings in the peripheral I/O redirection
register 0, 1 (PIOR0, 1).
R01UH0186EJ0100 Rev.1.00
Dec 28, 2011
13
RL78/G14
CHAPTER 1 OUTLINE
1.3.8 64-pin products
• 64-pin plastic LQFP (14 × 14)
• 64-pin plastic LQFP (12 × 12)
P147/ANI18/VCOUT1Note
P146
P10/SCK11/SCL11/TRDIOD1
P11/SI11/SDA11/TRDIOC1
P12/SO11/TRDIOB1/IVREF1Note/(INTP5)
P13/TxD2/SO20/TRDIOA1/IVCMP1Note
P14/RxD2/SI20/SDA20/TRDIOD0/(SCLA0)
P15/SCK20/SCL20/TRDIOB0/(SDAA0)
P16/TI01/TO01/INTP5/TRDIOC0/IVREF0 Note/(SI00)/(RXD0)
P17/TI02/TO02/TRDIOA0/TRDCLK0/IVCMP0 Note/(SO00)/(TXD0)
P55/(PCLBUZ1)/(SCK00)/(INTP4)
P54/(INTP3)
P53/(INTP2)
P52/(INTP1)
P51/INTP2/SO00/TxD0/TOOLTxD/TRGIOB
P50/INTP1/SI00/RxD0/TOOLRxD/SDA00/TRGIOA/(TRJO0)
• 64-pin plastic LQFP (fine pitch) (10 × 10)
48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33
P27/ANI7
P26/ANI6
P25/ANI5
P24/ANI4
P23/ANI3/ANO1Note
P22/ANI2/ANO0 Note
P21/ANI1/AVREFM
P20/ANI0/AVREFP
P130
P04/SCK10/SCL10
P03/ANI16/SI10/RxD1/SDA10
P02/ANI17/SO10/TxD1
P01/TO00/TRGCLKB/TRJIO0
P00/TI00/TRGCLKA/(TRJO0)
P141/PCLBUZ1/INTP7
P140/PCLBUZ0/INTP6
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
32
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
6 7 8 9 10 11 12 13 14 15 16
P120/ANI19/VCOUT0 Note
P43/(INTP9)
P42/(INTP8)
P41/(TRJIO0)
P40/TOOL0
RESET
P124/XT2/EXCLKS
P123/XT1
P137/INTP0
P122/X2/EXCLK
P121/X1
REGC
VSS
EVSS0
VDD
EVDD0
1 2 3 4 5
P30/INTP3/RTC1HZ/SCK00/SCL00/TRJO0
P05/(INTP10)
P06/(INTP11)/(TRJIO0)
P70/KR0/SCK21/SCL21
P71/KR1/SI21/SDA21
P72/KR2/SO21
P73/KR3/SO01
P74/KR4/INTP8/SI01/SDA01
P75/KR5/INTP9/SCK01/SCL01
P76/KR6/INTP10/(RXD2)
P77/KR7/INTP11/(TXD2)
P31/TI03/TO03/INTP4/(PCLBUZ0)/(TRJIO0)
P63
P62/SSI00
P61/SDAA0
P60/SCLA0
Note
Mounted on the 96 KB or more code flash memory products.
Cautions 1. Make EVSS0 pin the same potential as VSS pin.
2. Make VDD pin the same potential as EVDD0 pin, or the potential that is higher than the EVDD0 pin.
3. Connect the REGC pin to Vss pin via a capacitor (0.47 to 1 μF).
Remarks 1. For pin identification, see 1.4 Pin Identification.
2. When using the microcontroller for an application where the noise generated inside the microcontroller
must be reduced, it is recommended to supply separate powers to the VDD and EVDD0 pins and connect
the VSS and EVSS0 pins to separate ground lines.
3. Functions in parentheses in the above figure can be assigned via settings in the peripheral I/O redirection
register 0, 1 (PIOR0, 1).
R01UH0186EJ0100 Rev.1.00
Dec 28, 2011
14
RL78/G14
CHAPTER 1 OUTLINE
• 64-pin plastic FLGA (5 × 5)
Top View
Bottom View
8
7
6
5
4
3
2
1
A
B
C D E
F
G H
H
G
F
E D
C
B A
INDEX MARK
A
B
EVSS0
EVDD0
C
P121/X1
8
P60/SCLA0
VDD
VSS
D
E
P122/X2/
EXCLK
P137/INTP0
REGC
RESET
7
P61/SDAA0
P62/SSI00
P63
P40/TOOL0
6
5
4
P77/KR7/
INTP11/
(TXD2)
P31/TI03/
TO03/INTP4/
(PCLBUZ0)/
(TRJIO0)
P53/(INTP2)
P75/KR5/
INTP9/
SCK01/
SCL01
P76/KR6/
INTP10/
(RXD2)
P52/(INTP1)
P70/KR0/
SCK21/
SCL21
P73/KR3/
SO01
P74/KR4/
INTP8/SI01/
SDA01
2
P30/INTP3/
RTC1HZ/
SCK00/
SCL00/
TRJO0
P72/KR2/
SO21
P05/
(INTP10)
P50/INTP1/
SI00/RxD0/
TOOLRxD/
SDA00/
TRGIOA/
(TRJO0)
B
1
A
Note
P01/TO00/
TRGCLKB/
TRJIO0
P43/(INTP9)
G
P120/ANI19/
Note
VCOUT0
P00/TI00/
TRGCLKA/
(TRJO0)
P02/ANI17/
SO10/TxD1
P140/
PCLBUZ0/
INTP6
P141/
PCLBUZ1/
INTP7
P20/ANI0/
AVREFP
P04/SCK10/
SCL10
P130
P16/TI01/
TO01/INTP5/
TRDIOC0/
Note
/
IVREF0
(SI00)/(RXD0)
P21/ANI1/
AVREFM
P22/ANI2/
Note
ANO0
P17/TI02/
TO02/
TRDIOA0/
TRDCLK0/
Note
/
IVCMP0
(SO00)/
(TXD0)
P15/SCK20/
SCL20/
TRDIOB0/
(SDAA0)
P12/SO11/
TRDIOB1/
Note
/
IVREF1
(INTP5)
P24/ANI4
P06/
(INTP11)/
(TRJIO0)
P14/RxD2/
SI20/SDA20/
TRDIOD0/
(SCLA0)
P11/SI11/
SDA11/
TRDIOC1
P25/ANI5
P51/INTP2/
SO00/TxD0/
TOOLTxD/
TRGIOB
P55/
(PCLBUZ1)/
(SCK00)/
(INTP4)
P13/TxD2/
SO20/
TRDIOA1/
Note
IVCMP1
P10/SCK11/
SCL11/
TRDIOD1
P146
C
D
E
F
P71/KR1/
SI21/SDA21
P54/(INTP3)
H
P124/XT2/
EXCLKS
P03/ANI16/
SI10/RxD1/
SDA10
3
P42/(INTP8)
P41/
(TRJIO0)
F
P123/XT1
8
7
6
5
P23/ANI3/
Note
ANO1
4
P26/ANI6
3
P27/ANI7
2
P147/ANI18/
Note
VCOUT1
1
G
H
Mounted on the 96 KB or more code flash memory products.
Cautions 1. Make EVSS0 pin the same potential as VSS pin.
2. Make VDD pin the same potential as EVDD0 pin, or the potential that is higher than the EVDD0 pin.
3. Connect the REGC pin to Vss pin via a capacitor (0.47 to 1 μF).
(Remarks are listed on the next page.)
R01UH0186EJ0100 Rev.1.00
Dec 28, 2011
15
RL78/G14
CHAPTER 1 OUTLINE
Remarks 1.
For pin identification, see 1.4 Pin Identification.
2. When using the microcontroller for an application where the noise generated inside the microcontroller
must be reduced, it is recommended to supply separate powers to the VDD and EVDD0 pins and connect
the VSS and EVSS0 pins to separate ground lines.
3. Functions in parentheses in the above figure can be assigned via settings in the peripheral I/O redirection
register 0, 1 (PIOR0, 1).
R01UH0186EJ0100 Rev.1.00
Dec 28, 2011
16
RL78/G14
CHAPTER 1 OUTLINE
1.3.9 80-pin products
• 80-pin plastic LQFP (14 × 14)
P153/ANI11
P100/ANI20/(INTP10)
P147/ANI18/VCOUT1
P146
P111
P110/(INTP11)
P10/SCK11/SCL11/TRDIOD1
P11/SI11/SDA11/TRDIOC1
P12/SO11/TRDIOB1/IVREF1/(INTP5)
P13/TxD2/SO20/TRDIOA1/IVCMP1
P14/RxD2/SI20/SDA20/TRDIOD0/(SCLA0)
P15/SCK20/SCL20/TRDIOB0/(SDAA0)
P16/TI01/TO01/INTP5/TRDIOC0/IVREF0/(SI00)/(RXD0)
P17/TI02/TO02/TRDIOA0/TRDCLK0/IVCMP0/(SO00)/(TXD0)
P55/(PCLBUZ1)/(SCK00)/(INTP4)
P54/SCK31/SCL31/(INTP3)
P53/SI31/SDA31/(INTP2)
P52/SO31/(INTP1)
P51/INTP2/SO00/TxD0/TOOLTxD/TRGIOB
P50/INTP1/SI00/RxD0/TOOLRxD/SDA00/TRGIOA/(TRJO0)
• 80-pin plastic LQFP (fine pitch) (12 × 12)
60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41
P152/ANI10
P151/ANI9
P150/ANI8
P27/ANI7
P26/ANI6
P25/ANI5
P24/ANI4
P23/ANI3/ANO1
P22/ANI2/ANO0
P21/ANI1/AVREFM
P20/ANI0/AVREFP
P130
P04/SCK10/SCL10
P03/ANI16/SI10/RxD1/SDA10
P02/ANI17/SO10/TxD1
P01/TO00/TRGCLKB/TRJIO0
P00/TI00/TRGCLKA/(TRJO0)
P144/SO30/TxD3
P143/SI30/RxD3/SDA30
P142/SCK30/SCL30
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
24
23
22
21
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
P30/INTP3/RTC1HZ/SCK00/SCL00/TRJO0
P05
P06/(TRJIO0)
P70/KR0/SCK21/SCL21
P71/KR1/SI21/SDA21
P72/KR2/SO21
P73/KR3
P74/KR4/INTP8
P75/KR5/INTP9
P76/KR6/INTP10/(RXD2)
P77/KR7/INTP11/(TXD2)
P67/TI13/TO13
P66/TI12/TO12
P65/TI11/TO11
P64/TI10/TO10
P31/TI03/TO03/INTP4/(PCLBUZ0)/(TRJIO0)
P63/SDAA1
P62/SSI00/SCLA1
P61/SDAA0
P60/SCLA0
P141/PCLBUZ1/INTP7
P140/PCLBUZ0/INTP6
P120/ANI19/VCOUT0
P45/SO01
P44/SI01/SDA01
P43/SCK01/SCL01/(INTP9)
P42/(INTP8)
P41/(TRJIO0)
P40/TOOL0
RESET
P124/XT2/EXCLKS
P123/XT1
P137/INTP0
P122/X2/EXCLK
P121/X1
REGC
VSS
EVSS0
VDD
EVDD0
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20
Cautions 1. Make EVSS0 pin the same potential as VSS pin.
2. Make VDD pin the same potential as EVDD0 pin, or the potential that is higher than the EVDD0 pin.
3. Connect the REGC pin to Vss pin via a capacitor (0.47 to 1 μF).
Remarks 1. For pin identification, see 1.4 Pin Identification.
2. When using the microcontroller for an application where the noise generated inside the microcontroller
must be reduced, it is recommended to supply separate powers to the VDD and EVDD0 pins and connect
the VSS and EVSS0 pins to separate ground lines.
3. Functions in parentheses in the above figure can be assigned via settings in the peripheral I/O redirection
register 0, 1 (PIOR0, 1).
R01UH0186EJ0100 Rev.1.00
Dec 28, 2011
17
RL78/G14
CHAPTER 1 OUTLINE
1.3.10 100-pin products
P100/ANI20/(INTP10)
P147/ANI18/VCOUT1
P146/(INTP4)
P111
P110/(INTP11)
P101
P10/SCK11/SCL11/TRDIOD1
P11/SI11/SDA11/TRDIOC1
P12/SO11/TRDIOB1/IVREF1/(INTP5)
P13/TxD2/SO20/TRDIOA1/IVCMP1
P14/RxD2/SI20/SDA20/TRDIOD0/(SCLA0)
P15/SCK20/SCL20/TRDIOB0/(SDAA0)
P16/TI01/TO01/INTP5/TRDIOC0/IVREF0/(SI00)/(RXD0)
P17/TI02/TO02/TRDIOA0/TRDCLK0/IVCMP0/(SO00)/(TXD0)
P57/(INTP3)
P56/(INTP1)
P55/(PCLBUZ1)/(SCK00)
P54/SCK31/SCL31
P53/SI31/SDA31
P52/SO31
P51/SO00/TxD0/TOOLTxD/TRGIOB
P50/SI00/RxD0/TOOLRxD/SDA00/TRGIOA/(TRJO0)
EVDD1
P30/INTP3/RTC1HZ/SCK00/SCL00/TRJO0
P87/(INTP9)
• 100-pin plastic LQFP (fine pitch) (14 × 14)
75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51
50
76
49
77
48
78
47
79
46
80
45
81
44
82
43
83
42
84
41
85
40
86
39
87
38
88
37
89
36
90
35
91
34
92
33
93
32
94
31
95
30
96
29
97
28
98
27
99
26
100
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25
P86/(INTP8)
P85/(INTP7)
P84/(INTP6)
P83
P82/(SO10)/(TXD1)
P81/(SI10)/(RXD1)/(SDA10)
P80/(SCK10)/(SCL10)
EVSS1
P05
P06/(TRJIO0)
P70/KR0/SCK21/SCL21
P71/KR1/SI21/SDA21
P72/KR2/SO21
P73/KR3
P74/KR4/INTP8
P75/KR5/INTP9
P76/KR6/INTP10/(RXD2)
P77/KR7/INTP11/(TXD2)
P67/TI13/TO13
P66/TI12/TO12
P65/TI11/TO11
P64/TI10/TO10
P31/TI03/TO03/INTP4/(PCLBUZ0)/(TRJIO0)
P63/SDAA1
P62/SSI00/SCLA1
P142/SCK30/SCL30
P141/PCLBUZ1/INTP7
P140/PCLBUZ0/INTP6
P120/ANI19/VCOUT0
P47/INTP2
P46/INTP1
P45/SO01
P44/SI01/SDA01
P43/SCK01/SCL01
P42
P41/(TRJIO0)
P40/TOOL0
RESET
P124/XT2/EXCLKS
P123/XT1
P137/INTP0
P122/X2/EXCLK
P121/X1
REGC
VSS
EVSS0
VDD
EVDD0
P60/SCLA0
P61/SDAA0
P156/ANI14
P155/ANI13
P154/ANI12
P153/ANI11
P152/ANI10
P151/ANI9
P150/ANI8
P27/ANI7
P26/ANI6
P25/ANI5
P24/ANI4
P23/ANI3/ANO1
P22/ANI2/ANO0
P21/ANI1/AVREFM
P20/ANI0/AVREFP
P130
P102
P04/SCK10/SCL10
P03/ANI16/SI10/RxD1/SDA10
P02/ANI17/SO10/TxD1
P01/TO00/TRGCLKB/TRJIO0
P00/TI00/TRGCLKA/(TRJO0)
P145
P144/SO30/TxD3
P143/SI30/RxD3/SDA30
Cautions 1. Make EVSS0, EVSS1 pins the same potential as VSS pin.
2. Make VDD pin the same potential as EVDD0 pin, or the potential that is higher than the EVDD0 pin.
Make EVDD1 pin the same potential as EVDD0 pin.
3. Connect the REGC pin to Vss pin via a capacitor (0.47 to 1 μF).
Remarks 1. For pin identification, see 1.4 Pin Identification.
2. When using the microcontroller for an application where the noise generated inside the microcontroller
must be reduced, it is recommended to supply separate powers to the VDD, EVDD0 and EVDD1 pins and
connect the VSS, EVSS0 and EVSS1 pins to separate ground lines.
3. Functions in parentheses in the above figure can be assigned via settings in the peripheral I/O redirection
register 0, 1 (PIOR0, 1).
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Dec 28, 2011
18
RL78/G14
CHAPTER 1 OUTLINE
P140/PCLBUZ0/INTP6
P141/PCLBUZ1/INTP7
P142/SCK30/SCL30
P143/SI30/RxD3/SDA30
P144/SO30/TxD3
P145
P00/TI00/TRGCLKA/(TRJO0)
P01/TO00/TRGCLKB/TRJIO0
P02/ANI17/SO10/TxD1
P03/ANI16/SI10/RxD1/SDA10
P04/SCK10/SCL10
P102
P130
P20/ANI0/AVREFP
P21/ANI1/AVREFM
P22/ANI2/ANO0
P23/ANI3/ANO1
P24/ANI4
P25/ANI5
P26/ANI6
P27/ANI7
P150/ANI8
P151/ANI9
P152/ANI10
P153/ANI11
P154/ANI12
P155/ANI13
P156/ANI14
P100/ANI20/(INTP10)
P147/ANI18/VCOUT1
• 100-pin plastic LQFP (fine pitch) (14 × 20)
80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51
50
81
49
82
48
83
47
84
46
85
45
86
44
87
43
88
42
89
41
90
40
91
39
92
38
93
37
94
36
95
35
96
34
97
33
98
32
99
31
100
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30
P146/(INTP4)
P111
P110/(INTP11)
P101
P10/SCK11/SCL11/TRDIOD1
P11/SI11/SDA11/TRDIOC1
P12/SO11/TRDIOB1/IVREF1/(INTP5)
P13/TxD2/SO20/TRDIOA1/IVCMP1
P14/RxD2/SI20/SDA20/TRDIOD0/(SCLA0)
P15/SCK20/SCL20/TRDIOB0/(SDAA0)
P16/TI01/TO01/INTP5/TRDIOC0/IVREF0/(SI00)/(RXD0)
P17/TI02/TO02/TRDIOA0/TRDCLK0/IVCMP0/(SO00)/(TXD0)
P57/(INTP3)
P56/(INTP1)
P55/(PCLBUZ1)/(SCK00)
P54/SCK31/SCL31
P53/SI31/SDA31
P52/SO31
P51/SO00/TxD0/TOOLTxD/TRGIOB
P50/SI00/RxD0/TOOLRxD/SDA00/TRGIOA/(TRJO0)
P60/SCLA0
P61/SDAA0
P62/SSI00/SCLA1
P63/SDAA1
P31/TI03/TO03/INTP4/(PCLBUZ0)/(TRJIO0)
P64/TI10/TO10
P65/TI11/TO11
P66/TI12/TO12
P67/TI13/TO13
P77/KR7/INTP11/(TXD2)
P76/KR6/INTP10/(RXD2)
P75/KR5/INTP9
P74/KR4/INTP8
P73/KR3
P72/KR2/SO21
P71/KR1/SI21/SDA21
P70/KR0/SCK21/SCL21
P06/(TRJIO0)
P05
EVSS1
P80/(SCK10)/(SCL10)
P81/(SI10)/(RXD1)/(SDA10)
P82/(SO10)/(TXD1)
P83
P84/(INTP7)
P85/(INTP7)
P86/(INTP8)
P87/(INTP9)
P30/INTP3/RTC1HZ/SCK00/SCL00/TRJO0
EVDD1
P120/ANI19/VCOUT0
P47/INTP2
P46/INTP1
P45/SO01
P44/SI01/SDA01
P43/SCK01/SCL01
P42
P41/(TRJIO0)
P40/TOOL0
RESET
P124/XT2/EXCLKS
P123/XT1
P137/INTP0
P122/X2/EXCLK
P121/X1
REGC
VSS
EVSS0
VDD
EVDD0
Cautions 1. Make EVSS0, EVSS1 pins the same potential as VSS pin.
2. Make VDD pin the same potential as EVDD0 pin, or the potential that is higher than the EVDD0 pin.
Make EVDD1 pin the same potential as EVDD0 pin.
3. Connect the REGC pin to Vss pin via a capacitor (0.47 to 1 μF).
Remarks 1. For pin identification, see 1.4 Pin Identification.
2. When using the microcontroller for an application where the noise generated inside the microcontroller
must be reduced, it is recommended to supply separate powers to the VDD, EVDD0 and EVDD1 pins and
connect the VSS, EVSS0 and EVSS1 pins to separate ground lines.
3. Functions in parentheses in the above figure can be assigned via settings in the peripheral I/O redirection
register 0, 1 (PIOR0, 1).
R01UH0186EJ0100 Rev.1.00
Dec 28, 2011
19
RL78/G14
CHAPTER 1 OUTLINE
1.4 Pin Identification
ANI0 to ANI14, :
Analog input
RxD0 to RxD3:
Receive data
SCK00, SCK01, SCK10,: Serial clock input/output
ANI16 to ANI20
ANO0, ANO1:
Analog output
SCK11, SCK20, SCK21,
AVREFM:
A/D converter reference
potential (− side) input
SCK30, SCK31
SCLA0, SCLA1, SCL00,: Serial clock input/output
A/D converter reference
SCL01,SCL10, SCL11,
potential (+ side) input
SCL20, SCL21, SCL30,
EVDD0, EVDD1:
Power supply for port
SCL31
EVSS0, EVSS1:
Ground for port
SDAA0, SDAA1,SDA00,: Serial data input/output
EXCLK:
External clock input
SDA01, SDA10, SDA11,
(main system clock)
SDA20, SDA21,SDA30,
External clock input
SDA31
(sub system clock)
SI00, SI01, SI10, SI11,:
AVREFP:
EXCLKS:
Serial data input
INTP0 to INTP11: External interrupt input
SI20, SI21, SI30, SI31
IVCMP0, IVCMP1: Comparator input
SO00, SO01, SO10, :
IVREF0, IVREF1: Comparator reference input
SO11, SO20, SO21,
KR0 to KR7:
Key return
SO30, SO31
P00 to P06:
Port 0
SSI00:
P10 to P17:
Port 1
TI00 to TI03, TI10 to TI13: Timer input
P20 to P27:
Port 2
TO00 to TO03,:
P30, P31:
Port 3
TO10 to TO13, TRJO0
P40 to P47:
Port 4
TOOL0:
Data input/output for tool
P50 to P57:
Port 5
TOOLRxD, TOOLTxD:
Data input/output for external device
P60 to P67:
Port 6
TRDCLK0, TRGCLKA, : Timer external input clock
P70 to P77:
Port 7
TRGCLKB
P80 to P87:
Port 8
TRDIOA0, TRDIOB0,:
P100 to P102:
Port 10
TRDIOC0, TRDIOD0,
P110, P111:
Port 11
TRDIOA1, TRDIOB1,
P120 to P124:
Port 12
TRDIOC1, TRDIOD1,
P130, P137:
Port 13
TRGIOA, TRGIOB, TRJIO0
P140 to P147:
Port 14
TxD0 to TxD3:
Transmit data
P150 to P156:
Port 15
Serial data output
Serial interface chip select input
Timer output
Timer input/output
VCOUT0, VCOUT1:
Comparator output
PCLBUZ0, PCLBUZ1: Programmable clock
VDD:
Power supply
output/buzzer output
VSS:
Ground
Regulator capacitance
X1, X2:
Crystal oscillator (main system clock)
RESET:
Reset
XT1, XT2:
Crystal oscillator (subsystem clock)
RTC1HZ:
Real-time clock correction
REGC:
clock (1 Hz) output
R01UH0186EJ0100 Rev.1.00
Dec 28, 2011
20
RL78/G14
CHAPTER 1 OUTLINE
1.5 Block Diagram
1.5.1 30-pin products
TIMER ARRAY
UNIT (4ch)
PORT 0
2
P00, P01
TI00/P00
TO00/P01
ch0
PORT 1
8
P10 to P17
TI01/TO01/P16
ch1
PORT 2
4
P20 to P23
TI02/TO02/P17
ch2
PORT 3
2
P30, P31
TI03/TO03/P31
RxD0/P50 (LINSEL)
ch3
TIMER RD (2ch)
TRDIOA0/TRDCLK0/P17
TRDIOB0/P15, TRDIOC0/P16,
TRDIOD0/P14
3
TRDIOA1/P13 toTRDIOD1/P10
4
2
TRGIOA/P50,
TRGIOB/P51
2
TRGCLKA/P00,
TRGCLKB/P01
TIMER RG
ch0
PORT 4
P40
PORT 5
2
P50, P51
PORT 6
2
P60, P61
2
P121, P122
TRJIO0/P01
ch1
TIMER RJ
TRJO0/P30
WINDOW
WATCHDOG
TIMER
INTERVAL
TIMER
PORT 12
P120
PORT 13
LOW-SPEED
ON-CHIP
OSCILLATOR
P137
P147
PORT 14
REAL-TIME
CLOCK
SERIAL ARRAY
UNIT0 (4ch)
RxD0/P50
TxD0/P51
UART0
LINSEL
RxD1/P01
TxD1/P00
UART1
SCK00/P30
SI00/P50
SO00/P51
SSI00/P31
CSI00
SCK11/P10
SI11/P11
SO11/P12
CSI11
SCL00/P30
SDA00/P50
IIC00
SCL11/P10
SDA11/P11
IIC11
A/D CONVERTER
RL78 CPU CORE
MULTIPLIER,
DIVIDER &
MULTIPLYACCUMULATOR
4
ANI0/P20 to
ANI3/P23
4
ANI16/P01, ANI17/P00
ANI18/P147, ANI19/P120
AVREFP/P20
AVREFM/P21
CODE FLASH MEMORY
DATA FLASH MEMORY
POWER ON RESET/
VOLTAGE
DETECTOR
POR/LVD
CONTROL
RAM
RESET CONTROL
TOOL0/P40
ON-CHIP DEBUG
VDD
SERIAL ARRAY
UNIT1 (2ch)
VSS TOOLRxD/P50,
TOOLTxD/P51
SYSTEM
CONTROL
RESET
X1/P121
X2/EXCLK/P122
HIGH-SPEED
ON-CHIP
RxD2/P14
TxD2/P13
UART2
SCK20/P15
SI20/P14
SO20/P13
CSI20
SCL20/P15
SDA20/P14
IIC20
SDAA0/P61
SCLA0/P60
SERIAL
INTERFACE IICA0
OSCILLATOR
VOLTAGE
REGULATOR
REGC
BUZZER OUTPUT
2
CLOCK OUTPUT
CONTROL
PCLBUZ0/P31,
PCLBUZ1/P15
DATA TRANSFER
CONTROL
RxD0/P50 (LINSEL)
INTP0/P137
INTERRUPT
CONTROL
2
INTP1/P50,
INTP2/P51
2
INTP3/P30,
INTP4/P31
INTP5/P16
EVENT LINK
CONTROLLER
BCD
ADJUSTMENT
D/A CONVERTERNote
ANO0/P22
COMPARATORNote
(2ch)
Note
COMPARATOR0
VCOUT0/P120
IVCMP0/P17
IVREF0/P16
COMPARATOR1
VCOUT1/P147
IVCMP1/P13
IVREF1/P12
Mounted on the 96 KB or more code flash memory products.
R01UH0186EJ0100 Rev.1.00
Dec 28, 2011
21
RL78/G14
CHAPTER 1 OUTLINE
1.5.2 32-pin products
TIMER ARRAY
UNIT (4ch)
PORT 0
2
P00, P01
TI00/P00
TO00/P01
ch0
PORT 1
8
P10 to P17
TI01/TO01/P16
ch1
PORT 2
4
P20 to P23
TI02/TO02/P17
ch2
PORT 3
2
P30, P31
TI03/TO03/P31
RxD0/P50 (LINSEL)
ch3
TIMER RD (2ch)
TRDIOA0/TRDCLK0/P17
TRDIOB0/P15, TRDIOC0/P16,
TRDIOD0/P14
3
TRDIOA1/P13 toTRDIOD1/P10
4
2
TRGIOA/P50,
TRGIOB/P51
2
TRGCLKA/P00,
TRGCLKB/P01
TIMER RG
ch0
PORT 4
P40
PORT 5
2
P50, P51
PORT 6
3
P60 to P62
TRJIO0/P01
ch1
TIMER RJ
TRJO0/P30
WINDOW
WATCHDOG
TIMER
INTERVAL
TIMER
PORT 7
PORT 12
P70
P120
2
P121, P122
PORT 13
LOW-SPEED
ON-CHIP
OSCILLATOR
P137
P147
PORT 14
REAL-TIME
CLOCK
SERIAL ARRAY
UNIT0 (4ch)
RxD0/P50
TxD0/P51
UART0
LINSEL
RxD1/P01
TxD1/P00
UART1
SCK00/P30
SI00/P50
SO00/P51
SSI00/P62
CSI00
SCK11/P10
SI11/P11
SO11/P12
CSI11
SCL00/P30
SDA00/P50
IIC00
SCL11/P10
SDA11/P11
IIC11
A/D CONVERTER
RL78 CPU CORE
MULTIPLIER,
DIVIDER &
MULTIPLYACCUMULATOR
4
ANI0/P20 to
ANI3/P23
4
ANI16/P01, ANI17/P00
ANI18/P147, ANI19/P120
AVREFP/P20
AVREFM/P21
CODE FLASH MEMORY
DATA FLASH MEMORY
POWER ON RESET/
VOLTAGE
DETECTOR
POR/LVD
CONTROL
RAM
RESET CONTROL
TOOL0/P40
ON-CHIP DEBUG
VDD
SERIAL ARRAY
UNIT1 (2ch)
SYSTEM
CONTROL
RESET
X1/P121
X2/EXCLK/P122
HIGH-SPEED
ON-CHIP
RxD2/P14
TxD2/P13
UART2
SCK20/P15
SI20/P14
SO20/P13
CSI20
SCL20/P15
SDA20/P14
VSS TOOLRxD/P50,
TOOLTxD/P51
SDAA0/P61
SCLA0/P60
SERIAL
INTERFACE IICA0
OSCILLATOR
VOLTAGE
REGULATOR
REGC
BUZZER OUTPUT
IIC20
2
CLOCK OUTPUT
CONTROL
PCLBUZ0/P31,
PCLBUZ1/P15
DATA TRANSFER
CONTROL
RxD0/P50 (LINSEL)
INTP0/P137
INTERRUPT
CONTROL
2
INTP1/P50,
INTP2/P51
2
INTP3/P30,
INTP4/P31
INTP5/P16
EVENT LINK
CONTROLLER
BCD
ADJUSTMENT
D/A CONVERTERNote
ANO0/P22
ANO1/P23
COMPARATORNote
(2ch)
Note
COMPARATOR0
VCOUT0/P120
IVCMP0/P17
IVREF0/P16
COMPARATOR1
VCOUT1/P147
IVCMP1/P13
IVREF1/P12
Mounted on the 96 KB or more code flash memory products.
R01UH0186EJ0100 Rev.1.00
Dec 28, 2011
22
RL78/G14
CHAPTER 1 OUTLINE
1.5.3 36-pin products
TIMER ARRAY
UNIT (4ch)
PORT 0
2
P00, P01
TI00/P00
TO00/P01
ch0
PORT 1
8
P10 to P17
TI01/TO01/P16
ch1
PORT 2
6
P20 to P25
TI02/TO02/P17
ch2
PORT 3
2
P30, P31
TI03/TO03/P31
RxD0/P50 (LINSEL)
ch3
TIMER RD (2ch)
TRDIOA0/TRDCLK0/P17
TRDIOB0/P15, TRDIOC0/P16,
TRDIOD0/P14
3
TRDIOA1/P13 toTRDIOD1/P10
4
2
TRGIOA/P50,
TRGIOB/P51
2
TRGCLKA/P00,
TRGCLKB/P01
TIMER RG
ch0
PORT 4
P40
PORT 5
2
P50, P51
PORT 6
3
P60 to P62
PORT 7
3
P70 to P72
2
P121, P122
TRJIO0/P01
ch1
TIMER RJ
TRJO0/P30
WINDOW
WATCHDOG
TIMER
INTERVAL
TIMER
PORT 12
P120
PORT 13
LOW-SPEED
ON-CHIP
OSCILLATOR
P137
P147
PORT 14
REAL-TIME
CLOCK
SERIAL ARRAY
UNIT0 (4ch)
RxD0/P50
TxD0/P51
UART0
LINSEL
RxD1/P01
TxD1/P00
UART1
SCK00/P30
SI00/P50
SO00/P51
SSI00/P62
CSI00
SCK11/P10
SI11/P11
SO11/P12
CSI11
SCL00/P30
SDA00/P50
IIC00
SCL11/P10
SDA11/P11
IIC11
A/D CONVERTER
RL78 CPU CORE
MULTIPLIER,
DIVIDER &
MULTIPLYACCUMULATOR
2
ANI18/P147, ANI19/P120
AVREFP/P20
AVREFM/P21
DATA FLASH MEMORY
POWER ON RESET/
VOLTAGE
DETECTOR
POR/LVD
CONTROL
RAM
RESET CONTROL
TOOL0/P40
ON-CHIP DEBUG
VDD
SCK20/P15
SI20/P14
SO20/P13
SCK21/P70
SI21/P71
SO21/P72
ANI0/P20 to
ANI5/P25
CODE FLASH MEMORY
SERIAL ARRAY
UNIT1 (2ch)
RxD2/P14
TxD2/P13
6
VSS TOOLRxD/P50,
TOOLTxD/P51
SYSTEM
CONTROL
RESET
X1/P121
X2/EXCLK/P122
HIGH-SPEED
ON-CHIP
UART2
SDAA0/P61
SCLA0/P60
SERIAL
INTERFACE IICA0
OSCILLATOR
VOLTAGE
REGULATOR
CSI20
REGC
BUZZER OUTPUT
CSI21
SCL20/P15
SDA20/P14
IIC20
SCL21/P70
SDA21/P71
IIC21
2
CLOCK OUTPUT
CONTROL
PCLBUZ0/P31,
PCLBUZ1/P15
DATA TRANSFER
CONTROL
RxD0/P50 (LINSEL)
INTP0/P137
INTERRUPT
CONTROL
2
INTP1/P50,
INTP2/P51
2
INTP3/P30,
INTP4/P31
INTP5/P16
EVENT LINK
CONTROLLER
BCD
ADJUSTMENT
D/A CONVERTERNote
ANO0/P22
ANO1/P23
COMPARATORNote
(2ch)
Note
COMPARATOR0
VCOUT0/P120
IVCMP0/P17
IVREF0/P16
COMPARATOR1
VCOUT1/P147
IVCMP1/P13
IVREF1/P12
Mounted on the 96 KB or more code flash memory products.
R01UH0186EJ0100 Rev.1.00
Dec 28, 2011
23
RL78/G14
CHAPTER 1 OUTLINE
1.5.4 40-pin products
TIMER ARRAY
UNIT (4ch)
PORT 0
2
P00, P01
TI00/P00
TO00/P01
ch0
PORT 1
8
P10 to P17
TI01/TO01/P16
ch1
PORT 2
7
P20 to P26
TI02/TO02/P17
ch2
PORT 3
2
P30, P31
TI03/TO03/P31
RxD0/P50 (LINSEL)
ch3
TIMER RD (2ch)
TRDIOA0/TRDCLK0/P17
TRDIOB0/P15, TRDIOC0/P16,
TRDIOD0/P14
3
TRDIOA1/P13 toTRDIOD1/P10
4
2
TRGIOA/P50,
TRGIOB/P51
2
TRGCLKA/P00,
TRGCLKB/P01
TIMER RG
ch0
PORT 4
P40
PORT 5
2
P50, P51
PORT 6
3
P60 to P62
PORT 7
4
P70 to P73
4
P121 to P124
TRJIO0/P01
ch1
TIMER RJ
TRJO0/P30
WINDOW
WATCHDOG
TIMER
INTERVAL
TIMER
PORT 12
P120
PORT 13
LOW-SPEED
ON-CHIP
OSCILLATOR
P137
P147
PORT 14
RTC1HZ/P30
REAL-TIME
CLOCK
SERIAL ARRAY
UNIT0 (4ch)
RxD0/P50
TxD0/P51
UART0
LINSEL
RxD1/P01
TxD1/P00
UART1
SCK00/P30
SI00/P50
SO00/P51
SSI00/P62
CSI00
SCK11/P10
SI11/P11
SO11/P12
CSI11
SCL00/P30
SDA00/P50
IIC00
SCL11/P10
SDA11/P11
IIC11
A/D CONVERTER
RL78 CPU CORE
MULTIPLIER,
DIVIDER &
MULTIPLYACCUMULATOR
DATA FLASH MEMORY
2
ANI18/P147, ANI19/P120
AVREFP/P20
AVREFM/P21
KEY RETURN
POWER ON RESET/
VOLTAGE
DETECTOR
KR0/P70 to
KR3/P73
4
POR/LVD
CONTROL
RAM
RESET CONTROL
TOOL0/P40
ON-CHIP DEBUG
VDD
SCK20/P15
SI20/P14
SO20/P13
SCK21/P70
SI21/P71
SO21/P72
ANI0/P20 to
ANI6/P26
CODE FLASH MEMORY
SERIAL ARRAY
UNIT1 (2ch)
RxD2/P14
TxD2/P13
7
VSS TOOLRxD/P50,
TOOLTxD/P51
SYSTEM
CONTROL
RESET
X1/P121
X2/EXCLK/P122
HIGH-SPEED
XT1/P123
ON-CHIP
UART2
SDAA0/P61
SCLA0/P60
SERIAL
INTERFACE IICA0
OSCILLATOR
XT2/EXCLKS/P124
VOLTAGE
REGULATOR
CSI20
REGC
BUZZER OUTPUT
CSI21
SCL20/P15
SDA20/P14
IIC20
SCL21/P70
SDA21/P71
IIC21
2
CLOCK OUTPUT
CONTROL
PCLBUZ0/P31,
PCLBUZ1/P15
DATA TRANSFER
CONTROL
RxD0/P50 (LINSEL)
INTP0/P137
INTERRUPT
CONTROL
2
INTP1/P50,
INTP2/P51
2
INTP3/P30,
INTP4/P31
INTP5/P16
EVENT LINK
CONTROLLER
BCD
ADJUSTMENT
D/A CONVERTERNote
ANO0/P22
ANO1/P23
COMPARATORNote
(2ch)
Note
COMPARATOR0
VCOUT0/P120
IVCMP0/P17
IVREF0/P16
COMPARATOR1
VCOUT1/P147
IVCMP1/P13
IVREF1/P12
Mounted on the 96 KB or more code flash memory products.
R01UH0186EJ0100 Rev.1.00
Dec 28, 2011
24
RL78/G14
CHAPTER 1 OUTLINE
1.5.5 44-pin products
TIMER ARRAY
UNIT (4ch)
PORT 0
2
P00, P01
TI00/P00
TO00/P01
ch0
PORT 1
8
P10 to P17
TI01/TO01/P16
ch1
PORT 2
8
P20 to P27
TI02/TO02/P17
ch2
PORT 3
2
P30, P31
PORT 4
2
P40, P41
PORT 5
2
P50, P51
PORT 6
4
P60 to P63
PORT 7
4
P70 to P73
4
P121 to P124
TI03/TO03/P31
RxD0/P50 (LINSEL)
ch3
TIMER RD (2ch)
TRDIOA0/TRDCLK0/P17
TRDIOB0/P15, TRDIOC0/P16,
TRDIOD0/P14
3
TRDIOA1/P13 toTRDIOD1/P10
4
2
TRGIOA/P50,
TRGIOB/P51
2
TRGCLKA/P00,
TRGCLKB/P01
TIMER RG
ch0
TRJIO0/P01
ch1
TIMER RJ
TRJO0/P30
WINDOW
WATCHDOG
TIMER
INTERVAL
TIMER
PORT 12
PORT 13
LOW-SPEED
ON-CHIP
OSCILLATOR
PORT 14
RTC1HZ/P30
REAL-TIME
CLOCK
SERIAL ARRAY
UNIT0 (4ch)
RxD0/P50
TxD0/P51
UART0
LINSEL
RxD1/P01
TxD1/P00
UART1
SCK00/P30
SI00/P50
SO00/P51
SSI00/P62
CSI00
SCK11/P10
SI11/P11
SO11/P12
CSI11
SCL00/P30
SDA00/P50
IIC00
SCL11/P10
SDA11/P11
IIC11
A/D CONVERTER
RL78 CPU CORE
MULTIPLIER,
DIVIDER &
MULTIPLYACCUMULATOR
DATA FLASH MEMORY
2
P146, P147
8
ANI0/P20 to
ANI7/P27
2
ANI18/P147, ANI19/P120
AVREFP/P20
AVREFM/P21
KEY RETURN
POWER ON RESET/
VOLTAGE
DETECTOR
KR0/P70 to
KR3/P73
4
POR/LVD
CONTROL
RAM
RESET CONTROL
TOOL0/P40
ON-CHIP DEBUG
VDD
SCK20/P15
SI20/P14
SO20/P13
SCK21/P70
SI21/P71
SO21/P72
P137
CODE FLASH MEMORY
SERIAL ARRAY
UNIT1 (2ch)
RxD2/P14
TxD2/P13
P120
VSS TOOLRxD/P50,
TOOLTxD/P51
SYSTEM
CONTROL
RESET
X1/P121
X2/EXCLK/P122
HIGH-SPEED
XT1/P123
ON-CHIP
UART2
SDAA0/P61
SCLA0/P60
SERIAL
INTERFACE IICA0
OSCILLATOR
XT2/EXCLKS/P124
VOLTAGE
REGULATOR
CSI20
REGC
BUZZER OUTPUT
CSI21
SCL20/P15
SDA20/P14
IIC20
SCL21/P70
SDA21/P71
IIC21
2
CLOCK OUTPUT
CONTROL
PCLBUZ0/P31,
PCLBUZ1/P15
DATA TRANSFER
CONTROL
RxD0/P50 (LINSEL)
INTP0/P137
INTERRUPT
CONTROL
2
INTP1/P50,
INTP2/P51
2
INTP3/P30,
INTP4/P31
INTP5/P16
EVENT LINK
CONTROLLER
BCD
ADJUSTMENT
D/A CONVERTERNote
ANO0/P22
ANO1/P23
COMPARATORNote
(2ch)
Note
COMPARATOR0
VCOUT0/P120
IVCMP0/P17
IVREF0/P16
COMPARATOR1
VCOUT1/P147
IVCMP1/P13
IVREF1/P12
Mounted on the 96 KB or more code flash memory products.
R01UH0186EJ0100 Rev.1.00
Dec 28, 2011
25
RL78/G14
CHAPTER 1 OUTLINE
1.5.6 48-pin products
TIMER ARRAY
UNIT (4ch)
PORT 0
2
P00, P01
TI00/P00
TO00/P01
ch0
PORT 1
8
P10 to P17
TI01/TO01/P16
ch1
PORT 2
8
P20 to P27
TI02/TO02/P17
ch2
PORT 3
2
P30, P31
PORT 4
2
P40, P41
PORT 5
2
P50, P51
PORT 6
4
P60 to P63
PORT 7
6
P70 to P75
4
P121 to P124
TI03/TO03/P31
RxD0/P50 (LINSEL)
ch3
TIMER RD (2ch)
TRDIOA0/TRDCLK0/P17
TRDIOB0/P15, TRDIOC0/P16,
TRDIOD0/P14
3
TRDIOA1/P13 toTRDIOD1/P10
4
2
TRGIOA/P50,
TRGIOB/P51
2
TRGCLKA/P00,
TRGCLKB/P01
TIMER RG
ch0
TRJIO0/P01
ch1
TIMER RJ
TRJO0/P30
WINDOW
WATCHDOG
TIMER
INTERVAL
TIMER
PORT 12
PORT 14
REAL-TIME
CLOCK
SERIAL ARRAY
UNIT0 (4ch)
RxD0/P50
TxD0/P51
UART0
LINSEL
RxD1/P01
TxD1/P00
UART1
SCK00/P30
SI00/P50
SO00/P51
SSI00/P62
CSI00
SCK01/P75
SI01/P74
SO01/P73
CSI01
SCK11/P10
SI11/P11
SO11/P12
CSI11
SCL00/P30
SDA00/P50
IIC00
SCL01/P75
SDA01/P74
IIC01
SCL11/P10
SDA11/P11
IIC11
SCK20/P15
SI20/P14
SO20/P13
SCK21/P70
SI21/P71
SO21/P72
A/D CONVERTER
RL78 CPU CORE
MULTIPLIER,
DIVIDER &
MULTIPLYACCUMULATOR
3
P140,
P146, P147
8
ANI0/P20 to
ANI7/P27
2
ANI18/P147, ANI19/P120
AVREFP/P20
AVREFM/P21
CODE FLASH MEMORY
DATA FLASH MEMORY
KEY RETURN
POWER ON RESET/
VOLTAGE
DETECTOR
KR0/P70 to
KR5/P75
6
POR/LVD
CONTROL
RAM
RESET CONTROL
TOOL0/P40
ON-CHIP DEBUG
VDD
VSS TOOLRxD/P50,
TOOLTxD/P51
SYSTEM
CONTROL
RESET
X1/P121
X2/EXCLK/P122
HIGH-SPEED
XT1/P123
ON-CHIP
SERIAL ARRAY
UNIT1 (2ch)
RxD2/P14
TxD2/P13
P130
P137
PORT 13
LOW-SPEED
ON-CHIP
OSCILLATOR
RTC1HZ/P30
P120
UART2
SDAA0/P61
SCLA0/P60
SERIAL
INTERFACE IICA0
OSCILLATOR
XT2/EXCLKS/P124
VOLTAGE
REGULATOR
REGC
BUZZER OUTPUT
2
CLOCK OUTPUT
CONTROL
PCLBUZ0/P140,
PCLBUZ1/P15
RxD0/P50 (LINSEL)
INTP0/P137
2
CSI20
DATA TRANSFER
CONTROL
INTERRUPT
CONTROL
2
INTP5/P16
CSI21
EVENT LINK
CONTROLLER
SCL20/P15
SDA20/P14
IIC20
SCL21/P70
SDA21/P71
IIC21
INTP1/P50,
INTP2/P51
INTP3/P30,
INTP4/P31
INTP6/P140
2
INTP8/P74,
INTP9/P75
BCD
ADJUSTMENT
D/A CONVERTERNote
ANO0/P22
ANO1/P23
COMPARATORNote
(2ch)
Note
COMPARATOR0
VCOUT0/P120
IVCMP0/P17
IVREF0/P16
COMPARATOR1
VCOUT1/P147
IVCMP1/P13
IVREF1/P12
Mounted on the 96 KB or more code flash memory products.
R01UH0186EJ0100 Rev.1.00
Dec 28, 2011
26
RL78/G14
CHAPTER 1 OUTLINE
1.5.7 52-pin products
TIMER ARRAY
UNIT (4ch)
PORT 0
4
P00 to P03
TI00/P00
TO00/P01
ch0
PORT 1
8
P10 to P17
TI01/TO01/P16
ch1
PORT 2
8
P20 to P27
TI02/TO02/P17
ch2
PORT 3
2
P30, P31
PORT 4
2
P40, P41
PORT 5
2
P50, P51
PORT 6
4
P60 to P63
PORT 7
8
P70 to P77
4
P121 to P124
TI03/TO03/P31
RxD0/P50 (LINSEL)
ch3
TIMER RD (2ch)
TRDIOA0/TRDCLK0/P17
TRDIOB0/P15, TRDIOC0/P16,
TRDIOD0/P14
3
TRDIOA1/P13 toTRDIOD1/P10
4
2
TRGIOA/P50,
TRGIOB/P51
2
TRGCLKA/P00,
TRGCLKB/P01
TIMER RG
ch0
TRJIO0/P01
ch1
TIMER RJ
TRJO0/P30
WINDOW
WATCHDOG
TIMER
INTERVAL
TIMER
PORT 12
PORT 14
REAL-TIME
CLOCK
SERIAL ARRAY
UNIT0 (4ch)
RxD0/P50
TxD0/P51
UART0
LINSEL
RxD1/P03
TxD1/P02
UART1
SCK00/P30
SI00/P50
SO00/P51
SSI00/P62
CSI00
SCK01/P75
SI01/P74
SO01/P73
CSI01
SCK11/P10
SI11/P11
SO11/P12
CSI11
SCL00/P30
SDA00/P50
IIC00
SCL01/P75
SDA01/P74
IIC01
SCL11/P10
SDA11/P11
IIC11
P130
P137
PORT 13
LOW-SPEED
ON-CHIP
OSCILLATOR
RTC1HZ/P30
P120
A/D CONVERTER
RL78 CPU CORE
MULTIPLIER,
DIVIDER &
MULTIPLYACCUMULATOR
3
P140,
P146, P147
8
ANI0/P20 to
ANI7/P27
4
ANI16/P03, ANI17/P02,
ANI18/P147, ANI19/P120
AVREFP/P20
AVREFM/P21
CODE FLASH MEMORY
DATA FLASH MEMORY
KEY RETURN
POWER ON RESET/
VOLTAGE
DETECTOR
KR0/P70 to
KR7/P77
8
POR/LVD
CONTROL
RAM
RESET CONTROL
TOOL0/P40
ON-CHIP DEBUG
VDD
VSS TOOLRxD/P50,
TOOLTxD/P51
SYSTEM
CONTROL
RESET
X1/P121
X2/EXCLK/P122
HIGH-SPEED
XT1/P123
ON-CHIP
SERIAL ARRAY
UNIT1 (2ch)
RxD2/P14
TxD2/P13
SCK20/P15
SI20/P14
SO20/P13
SCK21/P70
SI21/P71
SO21/P72
UART2
SDAA0/P61
SCLA0/P60
SERIAL
INTERFACE IICA0
OSCILLATOR
XT2/EXCLKS/P124
VOLTAGE
REGULATOR
REGC
BUZZER OUTPUT
2
CLOCK OUTPUT
CONTROL
PCLBUZ0/P140,
PCLBUZ1/P15
RxD0/P50 (LINSEL)
INTP0/P137
2
CSI20
DATA TRANSFER
CONTROL
INTERRUPT
CONTROL
2
INTP5/P16
CSI21
EVENT LINK
CONTROLLER
SCL20/P15
SDA20/P14
IIC20
SCL21/P70
SDA21/P71
IIC21
INTP1/P50,
INTP2/P51
INTP3/P30,
INTP4/P31
INTP6/P140
4
INTP8/P74 to
INTP11/P77
BCD
ADJUSTMENT
D/A CONVERTERNote
ANO0/P22
ANO1/P23
COMPARATORNote
(2ch)
Note
COMPARATOR0
VCOUT0/P120
IVCMP0/P17
IVREF0/P16
COMPARATOR1
VCOUT1/P147
IVCMP1/P13
IVREF1/P12
Mounted on the 96 KB or more code flash memory products.
R01UH0186EJ0100 Rev.1.00
Dec 28, 2011
27
RL78/G14
CHAPTER 1 OUTLINE
1.5.8 64-pin products
TIMER ARRAY
UNIT (4ch)
PORT 0
7
P00 to P06
TI00/P00
TO00/P01
ch0
PORT 1
8
P10 to P17
TI01/TO01/P16
ch1
PORT 2
8
P20 to P27
TI02/TO02/P17
ch2
PORT 3
2
P30, P31
PORT 4
4
P40 to P43
PORT 5
6
P50 to P55
PORT 6
4
P60 to P63
PORT 7
8
P70 to P77
4
P121 to P124
TI03/TO03/P31
RxD0/P50 (LINSEL)
ch3
TIMER RD (2ch)
TRDIOA0/TRDCLK0/P17
TRDIOB0/P15, TRDIOC0/P16,
TRDIOD0/P14
3
TRDIOA1/P13 toTRDIOD1/P10
4
2
TRGIOA/P50,
TRGIOB/P51
2
TRGCLKA/P00,
TRGCLKB/P01
TIMER RG
ch0
TRJIO0/P01
ch1
TIMER RJ
TRJO0/P30
WINDOW
WATCHDOG
TIMER
INTERVAL
TIMER
PORT 12
PORT 14
REAL-TIME
CLOCK
SERIAL ARRAY
UNIT0 (4ch)
RxD0/P50
TxD0/P51
UART0
LINSEL
RxD1/P03
TxD1/P02
UART1
SCK00/P30
SI00/P50
SO00/P51
SSI00/P62
CSI00
SCK01/P75
SI01/P74
SO01/P73
CSI01
SCK10/P04
SI10/P03
SO10/P02
CSI10
SCK11/P10
SI11/P11
SO11/P12
CSI11
SCL00/P30
SDA00/P50
IIC00
A/D CONVERTER
RL78 CPU CORE
MULTIPLIER,
DIVIDER &
MULTIPLYACCUMULATOR
4
P140, P141,
P146, P147
8
ANI0/P20 to
ANI7/P27
4
ANI16/P03, ANI17/P02,
ANI18/P147, ANI19/P120
AVREFP/P20
AVREFM/P21
CODE FLASH MEMORY
DATA FLASH MEMORY
KEY RETURN
POWER ON RESET/
VOLTAGE
DETECTOR
KR0/P70 to
KR7/P77
8
POR/LVD
CONTROL
RAM
RESET CONTROL
TOOL0/P40
ON-CHIP DEBUG
VDD, VSS, TOOLRxD/P50,
EVDD0 EVSS0 TOOLTxD/P51
SCL01/P75
SDA01/P74
IIC01
SCL10/P04
SDA10/P03
IIC10
SYSTEM
CONTROL
RESET
X1/P121
X2/EXCLK/P122
HIGH-SPEED
XT1/P123
ON-CHIP
SDAA0/P61
SCLA0/P60
SERIAL
INTERFACE IICA0
OSCILLATOR
XT2/EXCLKS/P124
VOLTAGE
REGULATOR
REGC
BUZZER OUTPUT
SCL11/P10
SDA11/P11
2
IIC11
CLOCK OUTPUT
CONTROL
SERIAL ARRAY
UNIT1 (2ch)
RxD2/P14
TxD2/P13
SCK20/P15
SI20/P14
SO20/P13
SCK21/P70
SI21/P71
SO21/P72
Note
P130
P137
PORT 13
LOW-SPEED
ON-CHIP
OSCILLATOR
RTC1HZ/P30
P120
PCLBUZ0/P140,
PCLBUZ1/P141
DATA TRANSFER
CONTROL
UART2
RxD0/P50 (LINSEL)
INTP0/P137
INTERRUPT
CONTROL
EVENT LINK
CONTROLLER
2
INTP1/P50,
INTP2/P51
2
INTP3/P30,
INTP4/P31
2
INTP6/P140,
INTP7/P141
4
INTP8/P74 to
INTP11/P77
INTP5/P16
CSI20
CSI21
BCD
ADJUSTMENT
D/A CONVERTERNote
SCL20/P15
SDA20/P14
IIC20
SCL21/P70
SDA21/P71
IIC21
ANO0/P22
ANO1/P23
COMPARATORNote
(2ch)
COMPARATOR0
VCOUT0/P120
IVCMP0/P17
IVREF0/P16
COMPARATOR1
VCOUT1/P147
IVCMP1/P13
IVREF1/P12
Mounted on the 96 KB or more code flash memory products.
R01UH0186EJ0100 Rev.1.00
Dec 28, 2011
28
RL78/G14
CHAPTER 1 OUTLINE
1.5.9 80-pin products
TIMER ARRAY
UNIT0 (4ch)
TI00/P00
TO00/P01
TIMER ARRAY
UNIT1 (4ch)
ch0
TI10/TO10/P64
ch1
TI11/TO11/P65
ch2
TI12/TO12/P66
ch3
TI13/TO13/P67
ch0
TI01/TO01/P16
ch1
TI02/TO02/P17
ch2
TI03/TO03/P31
RxD0/P50 (LINSEL)
PORT 0
7
P00 to P06
PORT 1
8
P10 to P17
PORT 2
8
P20 to P27
PORT 3
2
P30, P31
PORT 4
6
P40 to P45
PORT 5
6
P50 to P55
PORT 6
8
P60 to P67
PORT 7
8
P70 to P77
ch3
TIMER RD (2ch)
TRDIOA0/TRDCLK0/P17
TRDIOB0/P15, TRDIOC0/P16,
TRDIOD0/P14
3
TRDIOA1/P13 toTRDIOD1/P10
4
2
TRGIOA/P50,
TRGIOB/P51
2
TRGCLKA/P00,
TRGCLKB/P01
TIMER RG
ch0
TRJIO0/P01
ch1
TIMER RJ
TRJO0/P30
WINDOW
WATCHDOG
TIMER
PORT 11
LOW-SPEED
ON-CHIP
OSCILLATOR
A/D CONVERTER
RTC1HZ/P30
RxD0/P50
TxD0/P51
UART0
LINSEL
RxD1/P03
TxD1/P02
UART1
SCK00/P30
SI00/P50
SO00/P51
SSI00/P62
CSI00
SCK01/P43
SI01/P44
SO01/P45
CSI01
SCK10/P04
SI10/P03
SO10/P02
CSI10
SCK11/P10
SI11/P11
SO11/P12
CSI11
SCL00/P30
SDA00/P50
IIC00
SCL01/P43
SDA01/P44
5
PORT 12
P110, P111
2
P120
4
P121 to P124
P130
P137
PORT 13
PORT 14
7
P140 to P144,
P146, P147
CODE FLASH MEMORY
PORT 15
4
P150 to P153
DATA FLASH MEMORY
KEY RETURN
8
KR0/P70 to
KR7/P77
POWER ON RESET/
VOLTAGE
DETECTOR
POR/LVD
CONTROL
RAM
RESET CONTROL
TOOL0/P40
ON-CHIP DEBUG
VDD, VSS, TOOLRxD/P50,
EVDD0 EVSS0 TOOLTxD/P51
IIC01
SDAA0/P61
SCLA0/P60
SDAA1/P63
SCLA1/P62
SCL11/P10
SDA11/P11
IIC11
BUZZER OUTPUT
2
SERIAL ARRAY
UNIT1 (4ch)
UART2
SYSTEM
CONTROL
CLOCK OUTPUT
CONTROL
DATA TRANSFER
CONTROL
CSI21
XT2/EXCLKS/P124
VOLTAGE
REGULATOR
REGC
RxD0/P50 (LINSEL)
INTP0/P137
PCLBUZ0/P140,
PCLBUZ1/P141
INTERRUPT
CONTROL
UART3
BCD
ADJUSTMENT
XT1/P123
ON-CHIP
OSCILLATOR
EVENT LINK
CONTROLLER
CSI20
RESET
X1/P121
X2/EXCLK/P122
HIGH-SPEED
SERIAL
INTERFACE IICA0
IIC10
SCK20/P15
SI20/P14
SO20/P13
SCK21/P70
SI21/P71
SO21/P72
ANI8/P150 to ANI11/P153
ANI16/P03, ANI17/P02,
ANI18/P147, ANI19/P120,
ANI20/P100
AVREFP/P20
AVREFM/P21
MULTIPLIER,
DIVIDER &
MULTIPLYACCUMULATOR
SCL10/P04
SDA10/P03
RxD3/P143
TxD3/P144
ANI0/P20 to ANI7/P27
4
RL78 CPU CORE
SERIAL
INTERFACE IICA1
RxD2/P14
TxD2/P13
8
REAL-TIME
CLOCK
SERIAL ARRAY
UNIT0 (4ch)
P100
PORT 10
INTERVAL
TIMER
D/A CONVERTER
2
INTP1/P50,
INTP2/P51
2
INTP3/P30,
INTP4/P31
2
INTP6/P140,
INTP7/P141
4
INTP8/P74 to
INTP11/P77
INTP5/P16
ANO0/P22
ANO1/P23
COMPARATOR
(2ch)
SCK30/P142
CSI30
COMPARATOR0
VCOUT0/P120
IVCMP0/P17
IVREF0/P16
SCK31/P54
SI31/P53
SO31/P52
CSI31
COMPARATOR1
VCOUT1/P147
IVCMP1/P13
IVREF1/P12
SCL20/P15
SDA20/P14
IIC20
SCL21/P70
SDA21/P71
IIC21
SCL30/P142
SDA30/P143
IIC30
SCL31/P54
SDA31/P53
IIC31
SI30/P143
SO30/P144
R01UH0186EJ0100 Rev.1.00
Dec 28, 2011
29
RL78/G14
CHAPTER 1 OUTLINE
1.5.10 100-pin products
TIMER ARRAY
UNIT0 (4ch)
TI00/P00
TO00/P01
TIMER ARRAY
UNIT1 (4ch)
ch0
TI10/TO10/P64
ch1
TI11/TO11/P65
ch2
TI12/TO12/P66
ch3
TI13/TO13/P67
ch0
TI01/TO01/P16
ch1
TI02/TO02/P17
ch2
TI03/TO03/P31
RxD0/P50 (LINSEL)
TRDIOA0/TRDCLK0/P17
TRDIOB0/P15, TRDIOC0/P16,
TRDIOD0/P14
3
TRDIOA1/P13 toTRDIOD1/P10
4
2
TRGIOA/P50,
TRGIOB/P51
2
TRGCLKA/P00,
TRGCLKB/P01
TIMER RG
ch0
WINDOW
WATCHDOG
TIMER
INTERVAL
TIMER
A/D CONVERTER
UART0
LINSEL
RxD1/P03
TxD1/P02
UART1
SCK00/P30
SI00/P50
SO00/P51
SSI00/P62
CSI00
SCK01/P43
SI01/P44
SO01/P45
CSI01
SCK10/P04
SI10/P03
SO10/P02
CSI10
SCK11/P10
SI11/P11
SO11/P12
CSI11
SCL00/P30
SDA00/P50
IIC00
SCL01/P43
SDA01/P44
IIC01
IIC10
IIC11
RxD3/P143
TxD3/P144
SCK20/P15
SI20/P14
SO20/P13
SCK21/P70
SI21/P71
SO21/P72
UART2
UART3
CSI20
8
P10 to P17
PORT 2
8
P20 to P27
PORT 3
2
P30, P31
PORT 4
8
P40 to P47
PORT 5
8
P50 to P57
PORT 6
8
P60 to P67
PORT 7
8
P70 to P77
PORT 8
8
P80 to P87
ANI8/P150 to ANI14/P156
ANI16/P03, ANI17/P02,
ANI18/P147, ANI19/P120,
ANI20/P100
AVREFP/P20
AVREFM/P21
PORT 10
3
P100 to P102
5
PORT 11
2
P110, P111
4
P121 to P124
PORT 12
MULTIPLIER,
DIVIDER &
MULTIPLYACCUMULATOR
CODE FLASH MEMORY
PORT 14
8
P140 to P147
DATA FLASH MEMORY
PORT 15
7
P150 to P156
KEY RETURN
8
KR0/P70 to
KR7/P77
POWER ON RESET/
VOLTAGE
DETECTOR
RAM
IIC20
SCL21/P70
SDA21/P71
IIC21
SCL30/P142
SDA30/P143
IIC30
SCL31/P54
SDA31/P53
IIC31
R01UH0186EJ0100 Rev.1.00
Dec 28, 2011
TOOL0/P40
ON-CHIP DEBUG
VDD, VSS, TOOLRxD/P50,
EVDD0, EVSS0, TOOLTxD/P51
EVDD1 EVSS1
SDAA0/P61
SERIAL
SCLA0/P60
INTERFACE IICA0
SDAA1/P63
SCLA1/P62
SERIAL
INTERFACE IICA1
BUZZER OUTPUT
CLOCK OUTPUT
CONTROL
PCLBUZ0/P140,
PCLBUZ1/P141
SYSTEM
CONTROL
HIGH-SPEED
XT1/P123
ON-CHIP
XT2/EXCLKS/P124
VOLTAGE
REGULATOR
REGC
RxD0/P50 (LINSEL)
INTP0/P137
DATA TRANSFER
CONTROL
EVENT LINK
CONTROLLER
RESET
X1/P121
X2/EXCLK/P122
OSCILLATOR
INTERRUPT
CONTROL
BCD
ADJUSTMENT
COMPARATOR
(2ch)
SCL20/P15
SDA20/P14
POR/LVD
CONTROL
RESET CONTROL
CSI30
CSI31
P130
P137
PORT 13
D/A CONVERTER
SCK31/P54
SI31/P53
SO31/P52
P120
RL78 CPU CORE
CSI21
SCK30/P142
SI30/P143
SO30/P144
ANI0/P20 to ANI7/P27
7
2
SERIAL ARRAY
UNIT1 (4ch)
RxD2/P14
TxD2/P13
8
REAL-TIME
CLOCK
SERIAL ARRAY
UNIT0 (4ch)
SCL11/P10
SDA11/P11
PORT 1
TIMER RJ
LOW-SPEED
ON-CHIP
OSCILLATOR
SCL10/P04
SDA10/P03
P00 to P06
TRJIO0/P01
ch1
TRJO0/P30
RxD0/P50
TxD0/P51
7
ch3
TIMER RD (2ch)
RTC1HZ/P30
PORT 0
2
INTP1/P47,
INTP2/P46
2
INTP3/P30,
INTP4/P31
2
INTP6/P140,
INTP7/P141
4
INTP8/P74 to
INTP11/P77
INTP5/P16
ANO0/P22
ANO1/P23
COMPARATOR0
VCOUT0/P120
IVCMP0/P17
IVREF0/P16
COMPARATOR1
VCOUT1/P147
IVCMP1/P13
IVREF1/P12
30
RL78/G14
CHAPTER 1 OUTLINE
1.6 Outline of Functions
[30-pin, 32-pin, 36-pin, 40-pin products (code flash memory 16 KB to 64 KB)]
<R> Caution This outline describes the functions at the time when Peripheral I/O redirection register 0, 1 (PIOR0, 1)
are set to 00H.
(1/2)
Item
30-pin
32-pin
36-pin
40-pin
R5F104Ax
(x = A, C to E)
R5F104Bx
(x = A, C to E)
R5F104Cx
(x = A, C to E)
R5F104Ex
(x = A, C to E)
16 to 64
16 to 64
16 to 64
16 to 64
Code flash memory (KB)
Data flash memory (KB)
4
4
Note
RAM (KB)
2.5 to 5.5
Memory space
Main system
clock
2.5 to 5.5
4
Note
2.5 to 5.5
4
Note
2.5 to 5.5
Note
1 MB
High-speed system
clock
X1 (crystal/ceramic) oscillation, external main system clock input (EXCLK)
1 to 20 MHz: VDD = 2.7 to 5.5 V, 1 to 8 MHz: VDD = 1.8 to 2.7 V, 1 to 4 MHz: VDD = 1.6 to 1.8 V
High-speed on-chip
oscillator clock (fIH)
High-speed operation: 1 to 32 MHz (VDD = 2.7 to 5.5 V), High-speed operation: 1 to 16 MHz (VDD =
2.4 to 5.5 V), Low-speed operation: 1 to 8 MHz (VDD = 1.8 to 5.5 V), Low-voltage operation: 1 to 4
MHz (VDD = 1.6 to 5.5 V)
−
Subsystem clock
XT1 (crystal) oscillation
32.768 kHz (TYP.):
VDD = 1.6 to 5.5 V
Low-speed on-chip oscillator clock
15 kHz (TYP.): VDD = 1.6 to 5.5 V
General-purpose register
8 bits × 32 registers (8 bits × 8 registers × 4 banks)
Minimum instruction execution time
0.03125 μs (High-speed on-chip oscillator clock: fIH = 32 MHz operation)
0.05 μs (High-speed system clock: fMX = 20 MHz operation)
30.5 μs (Subsystem clock:
fSUB = 32.768 kHz
operation)
−
•
•
•
•
•
Instruction set
I/O port
Timer
Data transfer (8/16 bits)
Adder and subtractor/logical operation (8/16 bits)
Multiplication (8 bits × 8 bits, 16 bits × 16 bits), Division (16 bits ÷ 16 bits, 32 bits ÷ 32 bits)
Multiplication and Accumulation (16 bits × 16 bits + 32 bits)
Rotate, barrel shift, and bit manipulation (Set, reset, test, and Boolean operation), etc.
Total
26
28
32
36
CMOS I/O
21
22
26
28
CMOS input
3
3
3
5
CMOS output
−
−
−
−
N-ch open-drain I/O
(6 V tolerance)
2
3
3
3
16-bit timer
8 channels
(TAU: 4 channels, Timer RJ: 1 channel, Timer RD: 2 channels, Timer RG: 1 channel)
Watchdog timer
1 channel
Real-time clock (RTC)
1 channel
12-bit interval timer
1 channel
Timer output
16
(TAU: 4, Timer RJ: 2, Timer RD: 8, Timer RG: 2)
PWM outputs: 10 (TAU: 3, Timer RD: 6, Timer RG: 1)
RTC output
−
1
• 1 Hz (subsystem clock: fSUB
= 32.768 kHz)
Note
In the case of the 5.5 KB, this is about 4.5 KB when the self-programming function and data flash function are
used. (For details, see CHAPTER 3)
R01UH0186EJ0100 Rev.1.00
Dec 28, 2011
31
RL78/G14
CHAPTER 1 OUTLINE
(2/2)
Item
30-pin
R5F104Ax
(x = A, C to E)
32-pin
R5F104Bx
(x = A, C to E)
36-pin
R5F104Cx
(x = A, C to E)
40-pin
R5F104Ex
(x = A, C to E)
2
2
2
2
Clock output/buzzer output
[30-pin, 32-pin, 36-pin products]
• 2.44 kHz, 4.88 kHz, 9.76 kHz, 1.25 MHz, 2.5 MHz, 5 MHz, 10 MHz
(Main system clock: fMAIN = 20 MHz operation)
[40-pin products]
• 2.44 kHz, 4.88 kHz, 9.76 kHz, 1.25 MHz, 2.5 MHz, 5 MHz, 10 MHz
(Main system clock: fMAIN = 20 MHz operation)
• 256 Hz, 512 Hz, 1.024 kHz, 2.048 kHz, 4.096 kHz, 8.192 kHz, 16.384 kHz, 32.768 kHz
(Subsystem clock: fSUB = 32.768 kHz operation)
8/10-bit resolution A/D converter
8 channels
8 channels
8 channels
9 channels
Serial interface
[30-pin, 32-pin products]
2
• CSI: 1 channel/UART (UART supporting LIN-bus): 1 channel/simplified I C: 1 channel
• CSI: 1 channel/UART: 1 channel/simplified I C: 1 channel
2
• CSI: 1 channel/UART: 1 channel/simplified I C: 1 channel
2
[36-pin, 40-pin products]
2
• CSI: 1 channel/UART (UART supporting LIN-bus): 1 channel/simplified I C: 1 channel
• CSI: 1 channel/UART: 1 channel/simplified I C: 1 channel
2
• CSI: 2 channels/UART: 1 channel/simplified I C: 2 channels
2
2
I C bus
1 channel
1 channel
Data transfer controller (DTC)
28 sources
Event link controller (ELC)
Event input: 20
1 channel
1 channel
29 sources
Event trigger output: 7
Vectored interrupt Internal
sources
External
24
24
24
24
6
6
6
7
Key interrupt
−
−
−
4
• Reset by RESET pin
Reset
• Internal reset by watchdog timer
• Internal reset by power-on-reset
• Internal reset by voltage detector
• Internal reset by illegal instruction execution
Note
• Internal reset by RAM parity error
• Internal reset by illegal-memory access
Power-on-reset circuit
• Power-on-reset:
1.51 ±0.03 V
• Power-down-reset: 1.50 ±0.03 V
Voltage detector
1.63 V to 4.06 V (14 stages)
On-chip debug function
Provided
Power supply voltage
VDD = 1.6 to 5.5 V
Operating ambient temperature
TA = −40 to +85 °C
Note The illegal instruction is generated when instruction code FFH is executed.
Reset by the illegal instruction execution not is issued by emulation with the in-circuit emulator or on-chip debug
emulator.
R01UH0186EJ0100 Rev.1.00
Dec 28, 2011
32
RL78/G14
CHAPTER 1 OUTLINE
[30-pin, 32-pin, 36-pin, 40-pin products (code flash memory 96 KB to 256 KB)]
<R> Caution This outline describes the functions at the time when Peripheral I/O redirection register 0, 1 (PIOR0, 1)
are set to 00H.
(1/2)
Item
30-pin
32-pin
36-pin
40-pin
R5F104Ax
(x = F, G)
R5F104Bx
(x = F, G)
R5F104Cx
(x = F, G)
R5F104Ex
(x = F to H)
Code flash memory (KB)
96 to 128
96 to 128
96 to 128
96 to 192
Data flash memory (KB)
8
8
8
8
12 to 16
12 to 16
12 to 16
12 to 20
RAM (KB)
Memory space
Main system
clock
1 MB
High-speed system
clock
X1 (crystal/ceramic) oscillation, external main system clock input (EXCLK)
1 to 20 MHz: VDD = 2.7 to 5.5 V, 1 to 8 MHz: VDD = 1.8 to 2.7 V, 1 to 4 MHz: VDD = 1.6 to 1.8 V
High-speed on-chip
oscillator clock (fIH)
High-speed operation: 1 to 32 MHz (VDD = 2.7 to 5.5 V), High-speed operation: 1 to 16 MHz (VDD =
2.4 to 5.5 V), Low-speed operation: 1 to 8 MHz (VDD = 1.8 to 5.5 V), Low-voltage operation: 1 to 4
MHz (VDD = 1.6 to 5.5 V)
−
Subsystem clock
XT1 (crystal) oscillation
32.768 kHz (TYP.):
VDD = 1.6 to 5.5 V
Low-speed on-chip oscillator clock
15 kHz (TYP.): VDD = 1.6 to 5.5 V
General-purpose register
8 bits × 32 registers (8 bits × 8 registers × 4 banks)
Minimum instruction execution time
0.03125 μs (High-speed on-chip oscillator clock: fIH = 32 MHz operation)
0.05 μs (High-speed system clock: fMX = 20 MHz operation)
30.5 μs (Subsystem clock:
fSUB = 32.768 kHz operation)
−
•
•
•
•
•
Instruction set
I/O port
Timer
Data transfer (8/16 bits)
Adder and subtractor/logical operation (8/16 bits)
Multiplication (8 bits × 8 bits, 16 bits × 16 bits), Division (16 bits ÷ 16 bits, 32 bits ÷ 32 bits)
Multiplication and Accumulation (16 bits × 16 bits + 32 bits)
Rotate, barrel shift, and bit manipulation (Set, reset, test, and Boolean operation), etc.
Total
26
28
32
36
CMOS I/O
21
22
26
28
CMOS input
3
3
3
5
CMOS output
−
−
−
−
N-ch open-drain I/O
(6 V tolerance)
2
3
3
3
16-bit timer
8 channels
(TAU: 4 channels, Timer RJ: 1 channel, Timer RD: 2 channels, Timer RG: 1 channel)
Watchdog timer
1 channel
Real-time clock (RTC)
1 channel
12-bit interval timer
1 channel
Timer output
16
(TAU: 4, Timer RJ: 2, Timer RD: 8, Timer RG: 2)
PWM outputs: 10 (TAU: 3, Timer RD: 6, Timer RG: 1)
RTC output
−
1
• 1 Hz (subsystem clock: fSUB
= 32.768 kHz)
R01UH0186EJ0100 Rev.1.00
Dec 28, 2011
33
RL78/G14
CHAPTER 1 OUTLINE
(2/2)
Item
30-pin
R5F104Ax
(x = F, G)
32-pin
R5F104Bx
(x = F, G)
36-pin
R5F104Cx
(x = F, G)
40-pin
R5F104Ex
(x = F to H)
2
2
2
2
Clock output/buzzer output
[30-pin, 32-pin, 36-pin products]
• 2.44 kHz, 4.88 kHz, 9.76 kHz, 1.25 MHz, 2.5 MHz, 5 MHz, 10 MHz
(Main system clock: fMAIN = 20 MHz operation)
[40-pin products]
• 2.44 kHz, 4.88 kHz, 9.76 kHz, 1.25 MHz, 2.5 MHz, 5 MHz, 10 MHz
(Main system clock: fMAIN = 20 MHz operation)
• 256 Hz, 512 Hz, 1.024 kHz, 2.048 kHz, 4.096 kHz, 8.192 kHz, 16.384 kHz, 32.768 kHz
(Subsystem clock: fSUB = 32.768 kHz operation)
8/10-bit resolution A/D converter
8 channels
8 channels
8 channels
9 channels
D/A converter
1 channel
2 channels
Comparator
2 channels
Serial interface
[30-pin, 32-pin products]
2
• CSI: 1 channel/UART (UART supporting LIN-bus): 1 channel/simplified I C: 1 channel
• CSI: 1 channel/UART: 1 channel/simplified I C: 1 channel
2
• CSI: 1 channel/UART: 1 channel/simplified I C: 1 channel
2
[36-pin, 40-pin products]
2
• CSI: 1 channel/UART (UART supporting LIN-bus): 1 channel/simplified I C: 1 channel
• CSI: 1 channel/UART: 1 channel/simplified I C: 1 channel
2
• CSI: 2 channels/UART: 1 channel/simplified I C: 2 channels
2
2
I C bus
1 channel
1 channel
Data transfer controller (DTC)
28 sources
Event link controller (ELC)
Event input: 20
1 channel
1 channel
29 sources
Event trigger output: 7
Vectored interrupt Internal
24
24
24
24
sources
6
6
6
7
−
−
−
4
External
Key interrupt
• Reset by RESET pin
Reset
• Internal reset by watchdog timer
• Internal reset by power-on-reset
• Internal reset by voltage detector
• Internal reset by illegal instruction execution
Note
• Internal reset by RAM parity error
• Internal reset by illegal-memory access
Power-on-reset circuit
• Power-on-reset:
1.51 ±0.03 V
• Power-down-reset: 1.50 ±0.03 V
Voltage detector
1.63 V to 4.06 V (14 stages)
On-chip debug function
Provided
Power supply voltage
VDD = 1.6 to 5.5 V
Operating ambient temperature
TA = −40 to +85 °C
Note The illegal instruction is generated when instruction code FFH is executed.
Reset by the illegal instruction execution not is issued by emulation with the in-circuit emulator or on-chip debug
emulator.
R01UH0186EJ0100 Rev.1.00
Dec 28, 2011
34
RL78/G14
CHAPTER 1 OUTLINE
[44-pin, 48-pin, 52-pin, 64-pin products (code flash memory 16 KB to 64 KB)]
<R> Caution
This outline describes the functions at the time when Peripheral I/O redirection register 0, 1 (PIOR0, 1)
are set to 00H.
(1/2)
Item
44-pin
48-pin
52-pin
64-pin
R5F104Fx
(x = A, C to E)
R5F104Gx
(x = A, C to E)
R5F104Jx
(x = C to E)
R5F104Lx
(x = C to E)
Code flash memory (KB)
16 to 64
16 to 64
32 to 64
32 to 64
Data flash memory (KB)
4
4
4
4
Note
RAM (KB)
2.5 to 5.5
Memory space
Main system
clock
2.5 to 5.5
Note
4 to 5.5
Note
4 to 5.5
Note
1 MB
High-speed system
clock
X1 (crystal/ceramic) oscillation, external main system clock input (EXCLK)
1 to 20 MHz: VDD = 2.7 to 5.5 V, 1 to 8 MHz: VDD = 1.8 to 2.7 V, 1 to 4 MHz: VDD = 1.6 to 1.8 V
High-speed on-chip
oscillator clock (fIH)
High-speed operation: 1 to 32 MHz (VDD = 2.7 to 5.5 V), High-speed operation: 1 to 16 MHz (VDD =
2.4 to 5.5 V), Low-speed operation: 1 to 8 MHz (VDD = 1.8 to 5.5 V), Low-voltage operation: 1 to 4
MHz (VDD = 1.6 to 5.5 V)
Subsystem clock
XT1 (crystal) oscillation
32.768 kHz (TYP.): VDD = 1.6 to 5.5 V
Low-speed on-chip oscillator clock
15 kHz (TYP.): VDD = 1.6 to 5.5 V
General-purpose register
8 bits × 32 registers (8 bits × 8 registers × 4 banks)
Minimum instruction execution time
0.03125 μs (High-speed on-chip oscillator clock: fIH = 32 MHz operation)
0.05 μs (High-speed system clock: fMX = 20 MHz operation)
30.5 μs (Subsystem clock: fSUB = 32.768 kHz operation)
•
•
•
•
•
Instruction set
I/O port
Timer
Data transfer (8/16 bits)
Adder and subtractor/logical operation (8/16 bits)
Multiplication (8 bits × 8 bits, 16 bits × 16 bits), Division (16 bits ÷ 16 bits, 32 bits ÷ 32 bits)
Multiplication and Accumulation (16 bits × 16 bits + 32 bits)
Rotate, barrel shift, and bit manipulation (Set, reset, test, and Boolean operation), etc.
Total
40
44
48
58
CMOS I/O
31
34
38
48
CMOS input
5
5
5
5
CMOS output
−
1
1
1
N-ch open-drain I/O
(6 V tolerance)
4
4
4
4
16-bit timer
8 channels
(TAU: 4 channels, Timer RJ: 1 channel, Timer RD: 2 channels, Timer RG: 1 channel)
Watchdog timer
1 channel
Real-time clock (RTC)
1 channel
12-bit interval timer
1 channel
Timer output
16
(TAU: 4, Timer RJ: 2, Timer RD: 8, Timer RG: 2)
PWM outputs: 10 (TAU: 3, Timer RD: 6, Timer RG: 1)
RTC output
Note
1
• 1 Hz (subsystem clock: fSUB = 32.768 kHz)
In the case of the 5.5 KB, this is about 4.5 KB when the self-programming function and data flash function are
used. (For details, see CHAPTER 3)
R01UH0186EJ0100 Rev.1.00
Dec 28, 2011
35
RL78/G14
CHAPTER 1 OUTLINE
(2/2)
Item
44-pin
48-pin
52-pin
64-pin
R5F104Fx
(x = A, C to E)
R5F104Gx
(x = A, C to E)
R5F104Jx
(x = C to E)
R5F104Lx
(x = C to E)
2
2
2
2
Clock output/buzzer output
• 2.44 kHz, 4.88 kHz, 9.76 kHz, 1.25 MHz, 2.5 MHz, 5 MHz, 10 MHz
(Main system clock: fMAIN = 20 MHz operation)
• 256 Hz, 512 Hz, 1.024 kHz, 2.048 kHz, 4.096 kHz, 8.192 kHz, 16.384 kHz, 32.768 kHz
(Subsystem clock: fSUB = 32.768 kHz operation)
8/10-bit resolution A/D converter
10 channels
Serial interface
[44-pin products]
10 channels
12 channels
12 channels
• CSI: 1 channel/UART (UART supporting LIN-bus): 1 channel/simplified I C: 1 channel
2
• CSI: 1 channel/UART: 1 channel/simplified I C: 1 channel
2
• CSI: 2 channels/UART: 1 channel/simplified I C: 2 channels
2
[48-pin, 52-pin products]
• CSI: 2 channels/UART (UART supporting LIN-bus): 1 channel/simplified I C: 2 channels
2
• CSI: 1 channel/UART: 1 channel/simplified I C: 1 channel
2
• CSI: 2 channels/UART: 1 channel/simplified I C: 2 channels
2
[64-pin products]
• CSI: 2 channels/UART(UART supporting LIN-bus): 1 channel/simplified I C: 2 channels
2
• CSI: 2 channels/UART: 1 channel/simplified I C: 2 channels
2
• CSI: 2 channels/UART: 1 channel/simplified I C: 2 channels
2
2
I C bus
1 channel
1 channel
1 channel
Data transfer controller (DTC)
29 sources
30 sources
Event link controller (ELC)
Event input: 20
1 channel
31 sources
Event trigger output: 7
Vectored
Internal
24
24
24
24
interrupt sources
External
7
10
12
13
4
6
8
8
Key interrupt
• Reset by RESET pin
Reset
• Internal reset by watchdog timer
• Internal reset by power-on-reset
• Internal reset by voltage detector
• Internal reset by illegal instruction execution
Note
• Internal reset by RAM parity error
• Internal reset by illegal-memory access
Power-on-reset circuit
• Power-on-reset:
1.51 ±0.03 V
• Power-down-reset: 1.50 ±0.03 V
Voltage detector
1.63 V to 4.06 V (14 stages)
On-chip debug function
Provided
Power supply voltage
VDD = 1.6 to 5.5 V
Operating ambient temperature
TA = −40 to +85 °C
Note
The illegal instruction is generated when instruction code FFH is executed.
Reset by the illegal instruction execution is not issued by emulation with the in-circuit emulator or on-chip
debug emulator.
R01UH0186EJ0100 Rev.1.00
Dec 28, 2011
36
RL78/G14
CHAPTER 1 OUTLINE
[44-pin, 48-pin, 52-pin, 64-pin products (code flash memory 96 KB to 256 KB)]
<R> Caution
This outline describes the functions at the time when Peripheral I/O redirection register 0, 1 (PIOR0, 1)
are set to 00H.
(1/2)
Item
44-pin
48-pin
52-pin
64-pin
R5F104Fx
(x = F to H, J)
R5F104Gx
(x = F to H, J)
R5F104Jx
(x = F to H, J)
R5F104Lx
(x = F to H, J)
Code flash memory (KB)
96 to 256
96 to 256
96 to 256
96 to 256
Data flash memory (KB)
8
8
8
8
Note
RAM (KB)
12 to 24
Memory space
Main system
clock
Note
12 to 24
Note
12 to 24
Note
12 to 24
1 MB
High-speed system
clock
X1 (crystal/ceramic) oscillation, external main system clock input (EXCLK)
1 to 20 MHz: VDD = 2.7 to 5.5 V, 1 to 8 MHz: VDD = 1.8 to 2.7 V, 1 to 4 MHz: VDD = 1.6 to 1.8 V
High-speed on-chip
oscillator clock (fIH)
High-speed operation: 1 to 32 MHz (VDD = 2.7 to 5.5 V), High-speed operation: 1 to 16 MHz (VDD =
2.4 to 5.5 V), Low-speed operation: 1 to 8 MHz (VDD = 1.8 to 5.5 V), Low-voltage operation: 1 to 4
MHz (VDD = 1.6 to 5.5 V)
Subsystem clock
XT1 (crystal) oscillation
32.768 kHz (TYP.): VDD = 1.6 to 5.5 V
Low-speed on-chip oscillator clock
15 kHz (TYP.): VDD = 1.6 to 5.5 V
General-purpose register
8 bits × 32 registers (8 bits × 8 registers × 4 banks)
Minimum instruction execution time
0.03125 μs (High-speed on-chip oscillator clock: fIH = 32 MHz operation)
0.05 μs (High-speed system clock: fMX = 20 MHz operation)
30.5 μs (Subsystem clock: fSUB = 32.768 kHz operation)
•
•
•
•
•
Instruction set
I/O port
Timer
Data transfer (8/16 bits)
Adder and subtractor/logical operation (8/16 bits)
Multiplication (8 bits × 8 bits, 16 bits × 16 bits), Division (16 bits ÷ 16 bits, 32 bits ÷ 32 bits)
Multiplication and Accumulation (16 bits × 16 bits + 32 bits)
Rotate, barrel shift, and bit manipulation (Set, reset, test, and Boolean operation), etc.
Total
40
44
48
58
CMOS I/O
31
34
38
48
CMOS input
5
5
5
5
CMOS output
−
1
1
1
N-ch open-drain I/O
(6 V tolerance)
4
4
4
4
16-bit timer
8 channels
(TAU: 4 channels, Timer RJ: 1 channel, Timer RD: 2 channels, Timer RG: 1 channel)
Watchdog timer
1 channel
Real-time clock (RTC)
1 channel
12-bit interval timer
1 channel
Timer output
16
(TAU: 4, Timer RJ: 2, Timer RD: 8, Timer RG: 2)
PWM outputs: 10 (TAU: 3, Timer RD: 6, Timer RG: 1)
RTC output
Note
1
• 1 Hz (subsystem clock: fSUB = 32.768 kHz)
In the case of the 24 KB, this is about 23 KB when the self-programming function and data flash function are
used. (For details, see CHAPTER 3)
R01UH0186EJ0100 Rev.1.00
Dec 28, 2011
37
RL78/G14
CHAPTER 1 OUTLINE
(2/2)
Item
44-pin
48-pin
52-pin
64-pin
R5F104Fx
(x = F to H, J)
R5F104Gx
(x = F to H, J)
R5F104Jx
(x = F to H, J)
R5F104Lx
(x = F to H, J)
2
2
2
2
Clock output/buzzer output
• 2.44 kHz, 4.88 kHz, 9.76 kHz, 1.25 MHz, 2.5 MHz, 5 MHz, 10 MHz
(Main system clock: fMAIN = 20 MHz operation)
• 256 Hz, 512 Hz, 1.024 kHz, 2.048 kHz, 4.096 kHz, 8.192 kHz, 16.384 kHz, 32.768 kHz
(Subsystem clock: fSUB = 32.768 kHz operation)
8/10-bit resolution A/D converter
10 channels
D/A converter
2 channels
Comparator
2 channels
Serial interface
[44-pin products]
10 channels
12 channels
12 channels
• CSI: 1 channel/UART (UART supporting LIN-bus): 1 channel/simplified I C: 1 channel
2
• CSI: 1 channel/UART: 1 channel/simplified I C: 1 channel
2
• CSI: 2 channels/UART: 1 channel/simplified I C: 2 channels
2
[48-pin, 52-pin products]
• CSI: 2 channels/UART (UART supporting LIN-bus): 1 channel/simplified I C: 2 channels
2
• CSI: 1 channel/UART: 1 channel/simplified I C: 1 channel
2
• CSI: 2 channels/UART: 1 channel/simplified I C: 2 channels
2
[64-pin products]
• CSI: 2 channels/UART(UART supporting LIN-bus): 1 channel/simplified I C: 2 channels
2
• CSI: 2 channels/UART: 1 channel/simplified I C: 2 channels
2
• CSI: 2 channels/UART: 1 channel/simplified I C: 2 channels
2
2
I C bus
1 channel
1 channel
1 channel
Data transfer controller (DTC)
29 sources
30 sources
Event link controller (ELC)
Event input: 20
1 channel
31 sources
Event trigger output: 7
Vectored
Internal
24
24
24
24
interrupt sources
External
7
10
12
13
4
6
8
8
Key interrupt
• Reset by RESET pin
Reset
• Internal reset by watchdog timer
• Internal reset by power-on-reset
• Internal reset by voltage detector
• Internal reset by illegal instruction execution
Note
• Internal reset by RAM parity error
• Internal reset by illegal-memory access
Power-on-reset circuit
• Power-on-reset:
1.51 ±0.03 V
• Power-down-reset: 1.50 ±0.03 V
Voltage detector
1.63 V to 4.06 V (14 stages)
On-chip debug function
Provided
Power supply voltage
VDD = 1.6 to 5.5 V
Operating ambient temperature
TA = −40 to +85 °C
Note
The illegal instruction is generated when instruction code FFH is executed.
Reset by the illegal instruction execution is not issued by emulation with the in-circuit emulator or on-chip
debug emulator.
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38
RL78/G14
CHAPTER 1 OUTLINE
[80-pin, 100-pin products (code flash memory 96 KB to 256 KB)]
<R> Caution
This outline describes the functions at the time when Peripheral I/O redirection register 0, 1 (PIOR0, 1)
are set to 00H.
(1/2)
Item
80-pin
Code flash memory (KB)
Data flash memory (KB)
100-pin
R5F104Mx
R5F104Px
(x = F to H, J)
(x = F to H, J)
96 to 256
96 to 256
8
RAM (KB)
12 to 24
8
Note
12 to 24
Note
Memory space
1 MB
Main system High-speed system
clock
clock
X1 (crystal/ceramic) oscillation, external main system clock input (EXCLK)
1 to 20 MHz: VDD = 2.7 to 5.5 V, 1 to 8 MHz: VDD = 1.8 to 2.7 V, 1 to 4 MHz: VDD = 1.6 to 1.8 V
High-speed on-chip
oscillator clock (fIH)
High-speed operation: 1 to 32 MHz (VDD = 2.7 to 5.5 V), High-speed operation: 1 to 16 MHz (VDD =
2.4 to 5.5 V), Low-speed operation: 1 to 8 MHz (VDD = 1.8 to 5.5 V), Low-voltage operation: 1 to 4
MHz (VDD = 1.6 to 5.5 V)
Subsystem clock
XT1 (crystal) oscillation
32.768 kHz (TYP.): VDD = 1.6 to 5.5 V
Low-speed on-chip oscillator clock
15 kHz (TYP.): VDD = 1.6 to 5.5 V
General-purpose register
8 bits × 32 registers (8 bits × 8 registers × 4 banks)
Minimum instruction execution time
0.03125 μs (High-speed on-chip oscillator clock: fIH = 32 MHz operation)
0.05 μs (High-speed system clock: fMX = 20 MHz operation)
30.5 μs (Subsystem clock: fSUB = 32.768 kHz operation)
•
•
•
•
•
Instruction set
I/O port
Timer
Data transfer (8/16 bits)
Adder and subtractor/logical operation (8/16 bits)
Multiplication (8 bits × 8 bits, 16 bits × 16 bits), Division (16 bits ÷ 16 bits, 32 bits ÷ 32 bits)
Multiplication and Accumulation (16 bits × 16 bits + 32 bits)
Rotate, barrel shift, and bit manipulation (Set, reset, test, and Boolean operation), etc.
Total
74
92
CMOS I/O
64
82
CMOS input
5
5
CMOS output
1
1
N-ch open-drain I/O
(6 V tolerance)
4
4
16-bit timer
12 channels
(TAU: 8 channels, Timer RJ: 1 channel, Timer RD: 2 channels, Timer RG: 1 channel)
Watchdog timer
1 channel
Real-time clock (RTC)
1 channel
12-bit interval timer
1 channel
Timer output
20
(TAU: 8, Timer RJ: 2, Timer RD: 8, Timer RG: 2)
PWM outputs: 13 (TAU: 6, Timer RD: 6, Timer RG: 1)
RTC output
Note
1
• 1 Hz (subsystem clock: fSUB = 32.768 kHz)
In the case of the 24 KB, this is about 23 KB when the self-programming function and data flash function are
used. (For details, see CHAPTER 3)
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RL78/G14
CHAPTER 1 OUTLINE
(2/2)
Item
80-pin
100-pin
R5F104Mx
R5F104Px
(x = F to H, J)
(x = F to H, J)
2
2
Clock output/buzzer output
• 2.44 kHz, 4.88 kHz, 9.76 kHz, 1.25 MHz, 2.5 MHz, 5 MHz, 10 MHz
(Main system clock: fMAIN = 20 MHz operation)
• 256 Hz, 512 Hz, 1.024 kHz, 2.048 kHz, 4.096 kHz, 8.192 kHz, 16.384 kHz, 32.768 kHz
(Subsystem clock: fSUB = 32.768 kHz operation)
8/10-bit resolution A/D converter
17 channels
20 channels
D/A converter
2 channels
2 channels
Comparator
2 channels
2 channels
Serial interface
[80-pin, 100-pin products]
• CSI: 2 channels/UART (UART supporting LIN-bus): 1 channel/simplified I C: 2 channels
2
• CSI: 2 channels/UART: 1 channel/simplified I C: 2 channels
2
• CSI: 2 channels/UART: 1 channel/simplified I C: 2 channels
2
• CSI: 2 channels/UART: 1 channel/simplified I C: 2 channels
2
2
I C bus
2 channels
2 channels
Data transfer controller (DTC)
39 sources
39 sources
Event link controller (ELC)
Event input: 26
Event trigger output: 9
Vectored
Internal
32
32
interrupt sources
External
13
13
8
8
Key interrupt
• Reset by RESET pin
Reset
• Internal reset by watchdog timer
• Internal reset by power-on-reset
• Internal reset by voltage detector
• Internal reset by illegal instruction execution
Note
• Internal reset by RAM parity error
• Internal reset by illegal-memory access
Power-on-reset circuit
• Power-on-reset:
1.51 ±0.03 V
• Power-down-reset: 1.50 ±0.03 V
Voltage detector
1.63 V to 4.06 V (14 stages)
On-chip debug function
Provided
Power supply voltage
VDD = 1.6 to 5.5 V
Operating ambient temperature
TA = −40 to +85 °C
Note
The illegal instruction is generated when instruction code FFH is executed.
Reset by the illegal instruction execution is not issued by emulation with the in-circuit emulator or on-chip
debug emulator.
R01UH0186EJ0100 Rev.1.00
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40
RL78/G14
CHAPTER 2 PIN FUNCTIONS
<R>
CHAPTER 2 PIN FUNCTIONS
2.1 Pin Function List
Pin I/O buffer power supplies depend on the product. The relationship between these power supplies and the pins is
shown below.
Table 2-1. Pin I/O Buffer Power Supplies
(1) 30-pin, 32-pin, 36-pin, 40-pin, 44-pin, 48-pin, 52-pin products
Power Supply
VDD
Corresponding Pins
All pins
(2) 64-pin products
Power Supply
Corresponding Pins
EVDD0
Port pins other than P20 to P27, P121 to P124, and P137
VDD
• P20 to P27, P121 to P124, and P137
• Pins other than port pins
(3) 80-pin products
Power Supply
Corresponding Pins
EVDD0
Port pins other than P20 to P27, P121 to P124, P137, and P150 to
P153
VDD
• P20 to P27, P121 to P124, P137, and P150 to P153
• Pins other than port pins
(4) 100-pin products
Power Supply
Corresponding Pins
EVDD0, EVDD1
Port pins other than P20 to P27, P121 to P124, P137, and P150 to
P156
VDD
• P20 to P27, P121 to P124, P137, and P150 to P156
• Pins other than port pins
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CHAPTER 2 PIN FUNCTIONS
<R> 2.1.1 30-pin products
(1/2)
Function Name
P00
I/O
I/O
P01
Function
After Reset
Alternate Function
Port 0.
Analog input
ANI17/TI00/TxD1/
2-bit I/O port.
port
TRGCLKA/(TRJO0)
Input of P01 can be set to TTL input buffer.
ANI16/TO00/RxD1/
Output of P00 can be set to N-ch open-drain output (EVDD0
TRGCLKB/TRJIO0
tolerance).
P00 and P01 can be set to analog input.
Input/output can be specified in 1-bit units.
Use of an on-chip pull-up resistor can be specified by a
software setting.
P10
I/O
P11
Port 1.
Input port
TRDIOD1
Input of P10 and P14 to P17 can be set to TTL input buffer.
SI11/SDA11/
Output of P10, P11, P13 to P15, and P17 can be set to N-ch
TRDIOC1
open-drain output (EVDD0 tolerance).
P12
SO11/TRDIOB1/
Note
IVREF1
Input/output can be specified in 1-bit units.
Use of an on-chip pull-up resistor can be specified by a
P13
SCK11/SCL11/
8-bit I/O port.
TxD2/SO20/
Note
TRDIOA1/IVCMP1
software setting.
RxD2/SI20/SDA20/
P14
TRDIOD0/(SCLA0)
PCLBUZ1/SCK20/
P15
SCL20/TRDIOB0/
(SDAA0)
TI01/TO01/INTP5/
Note
TRDIOC0/IVREF0 /
P16
(RXD0)
TI02/TO02/
P17
TRDIOA0/TRDCLK0/
Note
IVCMP0 /(TXD0)
P20
I/O
P21
Port 2.
Analog input
ANI0/AVREFP
4-bit I/O port.
port
ANI1/AVREFM
Input/output can be specified in 1-bit units.
P22
ANI2/ANO0
ANI3
P23
P30
Note
I/O
P31
Port 3.
Input port
INTP3/SCK00/SCL00/
2-bit I/O port.
TRJO0
Input of P30 can be set to TTL input buffer.
TI03/TO03/INTP4/
Output of P30 can be set to N-ch open-drain output (EVDD0
PCLBUZ0/SSI00/
tolerance).
(TRJIO0)
Input/output can be specified in 1-bit units.
Use of an on-chip pull-up resistor can be specified by a
software setting.
P40
I/O
Port 4.
Input port
TOOL0
1-bit I/O port.
Input/output can be specified.
Use of an on-chip pull-up resistor can be specified by a
software setting.
Note
Mounted on the 96 KB or more code flash memory products.
Remark Functions in parentheses in the above figure can be assigned via settings in the peripheral I/O redirection
registers 0, 1 (PIOR0, 1).
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CHAPTER 2 PIN FUNCTIONS
(2/2)
Function Name
P50
I/O
I/O
P51
Function
Port 5.
After Reset
Input port
Alternate Function
INTP1/SI00/RxD0/
2-bit I/O port.
TOOLRxD/SDA00/
Input of P50 can be set to TTL input buffer.
TRGIOA/(TRJO0)
Output of P50 and P51 can be set to N-ch open drain output
INTP2/SO00/TxD0/
(EVDD0 tolerance).
TOOLTxD/TRGIOB
Input/output can be specified in 1-bit units.
Use of an on-chip pull-up resistor can be specified by a
software setting.
P60
I/O
Port 6.
Input port
2-bit I/O port.
P61
SCLA0
SDAA0
Output of P60 and P61 is N-ch open-drain output (6 V
tolerance).
Input/output can be specified in 1-bit units.
P120
P121
I/O
Input
Port 12.
Analog input
1-bit I/O port and 2-bit input port.
port
P120 can be set to analog input.
Input port
For only P120, input/output can be specified.
P122
ANI19/VCOUT0
Note
X1
X2/EXCLK
For only P120, use of an on-chip pull-up resistor can be
specified by a software setting.
P137
Input
Port 13.
Input port
INTP0
Port 14.
Analog input
ANI18/VCOUT1
1-bit I/O port.
port
1-bit input port.
P147
I/O
Note
P147 can be set to analog input.
Input/output can be specified.
Use of an on-chip pull-up resistor can be specified by a
software setting.
Note
Mounted on the 96 KB or more code flash memory products.
Remark Functions in parentheses in the above figure can be assigned via settings in the peripheral I/O redirection
registers 0, 1 (PIOR0, 1).
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CHAPTER 2 PIN FUNCTIONS
<R> 2.1.2 32-pin products
(1/2)
Function Name
P00
I/O
I/O
P01
Function
After Reset
Alternate Function
Port 0.
Analog input
ANI17/TI00/TxD1/
2-bit I/O port.
port
TRGCLKA/(TRJO0)
Input of P01 can be set to TTL input buffer.
ANI16/TO00/RxD1/
Output of P00 can be set to N-ch open-drain output (EVDD0
TRGCLKB/TRJIO0
tolerance).
P00 and P01 can be set to analog input.
Input/output can be specified in 1-bit units.
Use of an on-chip pull-up resistor can be specified by a
software setting.
P10
I/O
P11
Port 1.
Input port
TRDIOD1
Input of P10 and P14 to P17 can be set to TTL input buffer.
SI11/SDA11/
Output of P10, P11, P13 to P15, and P17 can be set to N-ch
TRDIOC1
open-drain output (EVDD0 tolerance).
P12
SO11/TRDIOB1/
Note
IVREF1
Input/output can be specified in 1-bit units.
Use of an on-chip pull-up resistor can be specified by a
P13
SCK11/SCL11/
8-bit I/O port.
TxD2/SO20/
Note
TRDIOA1/IVCMP1
software setting.
RxD2/SI20/SDA20/
P14
TRDIOD0/(SCLA0)
PCLBUZ1/SCK20/
P15
SCL20/TRDIOB0/
(SDAA0)
TI01/TO01/INTP5/
Note
TRDIOC0/IVREF0 /
P16
(RXD0)
TI02/TO02/
P17
TRDIOA0/TRDCLK0/
Note
IVCMP0 /(TXD0)
P20
I/O
P21
Port 2.
Analog input
ANI0/AVREFP
4-bit I/O port.
port
ANI1/AVREFM
Input/output can be specified in 1-bit units.
P22
P23
P30
I/O
P31
Port 3.
Input port
ANI2/ANO0
Note
ANI3/ANO1
Note
INTP3/SCK00/SCL00/
2-bit I/O port.
TRJO0
Input of P30 can be set to TTL input buffer.
TI03/TO03/INTP4/
Output of P30 can be set to N-ch open-drain output (EVDD0
PCLBUZ0/(TRJIO0)
tolerance).
Input/output can be specified in 1-bit units.
Use of an on-chip pull-up resistor can be specified by a
software setting.
P40
I/O
Port 4.
Input port
TOOL0
1-bit I/O port.
Input/output can be specified.
Use of an on-chip pull-up resistor can be specified by a
software setting.
Note
Mounted on the 96 KB or more code flash memory products.
Remark Functions in parentheses in the above figure can be assigned via settings in the peripheral I/O redirection
registers 0, 1 (PIOR0, 1).
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CHAPTER 2 PIN FUNCTIONS
(2/2)
Function Name
P50
I/O
I/O
P51
Function
Port 5.
After Reset
Input port
Alternate Function
INTP1/SI00/RxD0/
2-bit I/O port.
TOOLRxD/SDA00/
Input of P50 can be set to TTL input buffer.
TRGIOA/(TRJO0)
Output of P50 and P51 can be set to N-ch open-drain output
INTP2/SO00/TxD0/
(EVDD0 tolerance).
TOOLTxD/TRGIOB
Input/output can be specified in 1-bit units.
Use of an on-chip pull-up resistor can be specified by a
software setting.
P60
I/O
Port 6.
Input port
3-bit I/O port.
P61
SDAA0
Output of P60 to P62 is N-ch open-drain output (6 V
P62
SCLA0
SSI00
tolerance).
Input/output can be specified in 1-bit units.
P70
I/O
Port 7.
−
Input port
1-bit I/O port.
Input/output can be specified.
Use of an on-chip pull-up resistor can be specified by a
software setting.
P120
I/O
P121
Input
Port 12.
Analog input
1-bit I/O port and 2-bit input port.
port
P120 can be set to analog input.
Input port
For only P120, input/output can be specified.
P122
ANI19/VCOUT0
Note
X1
X2/EXCLK
For only P120, use of an on-chip pull-up resistor can be
specified by a software setting.
P137
Input
Port 13.
Input port
INTP0
Port 14.
Analog input
ANI18/VCOUT1
1-bit I/O port.
port
1-bit input port.
P147
I/O
Note
P147 can be set to analog input.
Input/output can be specified.
Use of an on-chip pull-up resistor can be specified by a
software setting.
Note
Mounted on the 96 KB or more code flash memory products.
Remark Functions in parentheses in the above figure can be assigned via settings in the peripheral I/O redirection
registers 0, 1 (PIOR0, 1).
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CHAPTER 2 PIN FUNCTIONS
<R> 2.1.3 36-pin products
(1/2)
Function Name
P00
I/O
I/O
P01
Function
Port 0.
After Reset
Input port
Alternate Function
TI00/TxD1/
2-bit I/O port.
TRGCLKA/(TRJO0)
Input of P01 can be set to TTL input buffer.
TO00/RxD1/
Output of P00 can be set to N-ch open-drain output (EVDD0
TRGCLKB/TRJIO0
tolerance).
Input/output can be specified in 1-bit units.
Use of an on-chip pull-up resistor can be specified by a
software setting.
P10
I/O
P11
Port 1.
Input port
TRDIOD1
Input of P10 and P14 to P17 can be set to TTL input buffer.
SI11/SDA11/
Output of P10, P11, P13 to P15, and P17 can be set to N-ch
TRDIOC1
open-drain output (EVDD0 tolerance).
P12
SO11/TRDIOB1/
Note
IVREF1
Input/output can be specified in 1-bit units.
Use of an on-chip pull-up resistor can be specified by a
P13
SCK11/SCL11/
8-bit I/O port.
TxD2/SO20/
Note
TRDIOA1/IVCMP1
software setting.
RxD2/SI20/SDA20/
P14
TRDIOD0/(SCLA0)
P15
PCLBUZ1/SCK20/
SCL20/TRDIOB0/
(SDAA0)
TI01/TO01/INTP5/
Note
TRDIOC0/IVREF0 /
P16
(RXD0)
TI02/TO02/
P17
TRDIOA0/TRDCLK0/
Note
IVCMP0 /(TXD0)
P20
I/O
P21
Port 2.
Analog input
ANI0/AVREFP
6-bit I/O port.
port
ANI1/AVREFM
Input/output can be specified in 1-bit units.
ANI2/ANO0
Note
P23
ANI3/ANO1
Note
P24
ANI4
P25
ANI5
P22
P30
I/O
P31
Port 3.
Input port
INTP3/SCK00/SCL00/
2-bit I/O port.
TRJO0
Input of P30 can be set to TTL input buffer.
TI03/TO03/INTP4/
Output of P30 can be set to N-ch open-drain output (EVDD0
PCLBUZ0/(TRJIO0)
tolerance).
Input/output can be specified in 1-bit units.
Use of an on-chip pull-up resistor can be specified by a
software setting.
P40
I/O
Port 4.
Input port
TOOL0
1-bit I/O port.
Input/output can be specified.
Use of an on-chip pull-up resistor can be specified by a
software setting.
Note
Mounted on the 96 KB or more code flash memory products.
Remark Functions in parentheses in the above figure can be assigned via settings in the peripheral I/O redirection
registers 0, 1 (PIOR0, 1).
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CHAPTER 2 PIN FUNCTIONS
(2/2)
Function Name
P50
I/O
I/O
P51
Function
Port 5.
After Reset
Input port
Alternate Function
INTP1/SI00/RxD0/
2-bit I/O port.
TOOLRxD/SDA00/
Input of P50 can be set to TTL input buffer.
TRGIOA/(TRJO0)
Output of P50 and P51 can be set to N-ch open-drain output
INTP2/SO00/TxD0/
(EVDD0 tolerance).
TOOLTxD/TRGIOB
Input/output can be specified in 1-bit units.
Use of an on-chip pull-up resistor can be specified by a
software setting.
P60
I/O
Port 6.
Input port
3-bit I/O port.
P61
SDAA0
Output of P60 to P62 is N-ch open-drain output (6 V
P62
SCLA0
SSI00
tolerance).
Input/output can be specified in 1-bit units.
P70
I/O
Port 7.
Input port
3-bit I/O port.
P71
SI21/SDA21
Output of P71 can be set to N-ch open-drain output (EVDD0
P72
SCK21/SCL21
SO21
tolerance).
Input/output can be specified in 1-bit units.
Use of an on-chip pull-up resistor can be specified by a
software setting.
P120
I/O
P121
Input
Port 12.
Analog input
1-bit I/O port and 2-bit input port.
port
P120 can be set to analog input.
Input port
For only P120, input/output can be specified.
P122
ANI19/VCOUT0
Note
X1
X2/EXCLK
For only P120, use of an on-chip pull-up resistor can be
specified by a software setting.
P137
Input
Port 13.
Input port
INTP0
Port 14.
Analog input
ANI18/VCOUT1
1-bit I/O port.
port
1-bit input port.
P147
I/O
Note
P147 can be set to analog input.
Input/output can be specified.
Use of an on-chip pull-up resistor can be specified by a
software setting.
Note
Mounted on the 96 KB or more code flash memory products.
Remark Functions in parentheses in the above figure can be assigned via settings in the peripheral I/O redirection
registers 0, 1 (PIOR0, 1).
R01UH0186EJ0100 Rev.1.00
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RL78/G14
CHAPTER 2 PIN FUNCTIONS
<R> 2.1.4 40-pin products
(1/2)
Function Name
P00
I/O
I/O
P01
Function
Port 0.
After Reset
Input port
Alternate Function
TI00/TxD1/
2-bit I/O port.
TRGCLKA/(TRJO0)
Input of P01 can be set to TTL input buffer.
TO00/RxD1/
Output of P00 can be set to N-ch open-drain output (EVDD0
TRGCLKB/TRJIO0
tolerance).
Input/output can be specified in 1-bit units.
Use of an on-chip pull-up resistor can be specified by a
software setting.
P10
I/O
P11
Port 1.
Input port
TRDIOD1
Input of P10 and P14 to P17 can be set to TTL input buffer.
SI11/SDA11/TRDIOC1
Output of P10, P11, P13 to P15, and P17 can be set to N-ch
P12
SO11/TRDIOB1/
Note
IVREF1
open-drain output (EVDD0 tolerance).
Input/output can be specified in 1-bit units.
P13
SCK11/SCL11/
8-bit I/O port.
TxD2/SO20/
Note
TRDIOA1/IVCMP1
Use of an on-chip pull-up resistor can be specified by a
software setting.
RxD2/SI20/SDA20/
P14
TRDIOD0/(SCLA0)
PCLBUZ1/SCK20/
P15
SCL20/TRDIOB0/
(SDAA0)
TI01/TO01/INTP5/
Note
TRDIOC0/IVREF0 /
P16
(RXD0)
TI02/TO02/
P17
TRDIOA0/TRDCLK0/
Note
IVCMP0 /(TXD0)
P20
I/O
P21
Port 2.
Analog input
ANI0/AVREFP
7-bit I/O port.
port
ANI1/AVREFM
Input/output can be specified in 1-bit units.
ANI2/ANO0
Note
P23
ANI3/ANO1
Note
P24
ANI4
P25
ANI5
P22
ANI6
P26
P30
I/O
P31
Port 3.
Input port
INTP3/RTC1HZ/
2-bit I/O port.
SCK00/SCL00/
Input of P30 can be set to TTL input buffer.
TRJO0
Output of P30 can be set to N-ch open-drain output (EVDD0
TI03/TO03/INTP4/
tolerance).
PCLBUZ0/(TRJIO0)
Input/output can be specified in 1-bit units.
Use of an on-chip pull-up resistor can be specified by a
software setting.
P40
I/O
Port 4.
Input port
TOOL0
1-bit I/O port.
Input/output can be specified.
Use of an on-chip pull-up resistor can be specified by a
software setting.
Note
Mounted on the 96 KB or more code flash memory products.
Remark Functions in parentheses in the above figure can be assigned via settings in the peripheral I/O redirection
registers 0, 1 (PIOR0, 1).
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Function Name
P50
I/O
I/O
P51
Function
Port 5.
After Reset
Input port
Alternate Function
INTP1/SI00/RxD0/
2-bit I/O port.
TOOLRxD/SDA00/
Input of P50 can be set to TTL input buffer.
TRGIOA/(TRJO0)
Output of P50 and P51 can be set to N-ch open-drain output
INTP2/SO00/TxD0/
(EVDD0 tolerance).
TOOLTxD/TRGIOB
Input/output can be specified in 1-bit units.
Use of an on-chip pull-up resistor can be specified by a
software setting.
P60
I/O
Port 6.
Input port
3-bit I/O port.
P61
SDAA0
Output of P60 to P62 is N-ch open-drain output (6 V
P62
SCLA0
SSI00
tolerance).
Input/output can be specified in 1-bit units.
P70
I/O
Port 7.
Input port
4-bit I/O port.
P71
KR1/SI21/SDA21
Output of P71 can be set to N-ch open-drain output (EVDD0
P72
KR2/SO21
tolerance).
P73
KR0/SCK21/SCL21
KR3
Input/output can be specified in 1-bit units.
Use of an on-chip pull-up resistor can be specified by a
software setting.
P120
I/O
P121
Input
Port 12.
Analog input
1-bit I/O port and 4-bit input port.
port
P120 can be set to analog input.
Input port
For only P120, input/output can be specified.
P122
X1
XT1
specified by a software setting.
P124
P137
Note
X2/EXCLK
For only P120, use of an on-chip pull-up resistor can be
P123
ANI19/VCOUT0
XT2/EXCLKS
Input
Port 13.
Input port
INTP0
Port 14.
Analog input
ANI18/VCOUT1
1-bit I/O port.
port
1-bit input port.
P147
I/O
Note
P147 can be set to analog input.
Input/output can be specified.
Use of an on-chip pull-up resistor can be specified by a
software setting.
Note
Mounted on the 96 KB or more code flash memory products.
Remark Functions in parentheses in the above figure can be assigned via settings in the peripheral I/O redirection
registers 0, 1 (PIOR0, 1).
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CHAPTER 2 PIN FUNCTIONS
<R> 2.1.5 44-pin products
(1/2)
Function Name
P00
I/O
I/O
P01
P10
I/O
P11
P12
P13
Function
After Reset
Port 0.
2-bit I/O port.
Input of P01 can be set to TTL input buffer.
Output of P00 can be set to N-ch open-drain output (EVDD0
tolerance).
Input/output can be specified in 1-bit units.
Use of an on-chip pull-up resistor can be specified by a
software setting.
Input port
Port 1.
8-bit I/O port.
Input of P10 and P14 to P17 can be set to TTL input buffer.
Output of P10, P11, P13 to P15, and P17 can be set to N-ch
open-drain output (EVDD0 tolerance).
Input/output can be specified in 1-bit units.
Use of an on-chip pull-up resistor can be specified by a
software setting.
Input port
Alternate Function
TI00/TxD1/
TRGCLKA/(TRJO0)
TO00/RxD1/
TRGCLKB/TRJIO0
SCK11/SCL11/
TRDIOD1
SI11/SDA11/TRDIOC1
SO11/TRDIOB1/
Note
IVREF1
TxD2/SO20/
Note
TRDIOA1/IVCMP1
P14
RxD2/SI20/SDA20/
TRDIOD0/(SCLA0)
P15
PCLBUZ1/SCK20/
SCL20/TRDIOB0/
(SDAA0)
P16
TI01/TO01/INTP5/
Note
TRDIOC0/IVREF0
(RXD0)
P17
P20
TI02/TO02/
TRDIOA0/TRDCLK0/
Note
IVCMP0 /(TXD0)
I/O
P21
Port 2.
8-bit I/O port.
Input/output can be specified in 1-bit units.
Analog input
port
ANI0/AVREFP
ANI1/AVREFM
ANI2/ANO0
Note
P23
ANI3/ANO1
Note
P24
ANI4
P25
ANI5
P26
ANI6
P27
ANI7
P22
P30
I/O
P31
P40
P41
Note
/
I/O
Port 3.
2-bit I/O port.
Input of P30 can be set to TTL input buffer.
Output of P30 can be set to N-ch open-drain output (EVDD0
tolerance).
Input/output can be specified in 1-bit units.
Use of an on-chip pull-up resistor can be specified by a
software setting.
Input port
Port 4.
2-bit I/O port.
Input/output can be specified in 1-bit units.
Use of an on-chip pull-up resistor can be specified by a
software setting.
Input port
INTP3/RTC1HZ/
SCK00/SCL00/
TRJO0
TI03/TO03/INTP4/
PCLBUZ0/(TRJIO0)
TOOL0
−
Mounted on the 96 KB or more code flash memory products.
Remark Functions in parentheses in the above figure can be assigned via settings in the peripheral I/O redirection
registers 0, 1 (PIOR0, 1).
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Function Name
P50
I/O
I/O
P51
Function
Port 5.
After Reset
Input port
Alternate Function
INTP1/SI00/RxD0/
2-bit I/O port.
TOOLRxD/SDA00/
Input of P50 can be set to TTL input buffer.
TRGIOA/(TRJO0)
Output of P50 and P51 can be set to N-ch open-drain output
INTP2/SO00/TxD0/
(EVDD0 tolerance).
TOOLTxD/TRGIOB
Input/output can be specified in 1-bit units.
Use of an on-chip pull-up resistor can be specified by a
software setting.
P60
I/O
Input port
4-bit I/O port.
P61
SSI00
tolerance).
P63
SCLA0
SDAA0
Output of P60 to P63 is N-ch open-drain output (6 V
P62
P70
Port 6.
−
Input/output can be specified in 1-bit units.
I/O
Port 7.
Input port
4-bit I/O port.
P71
KR1/SI21/SDA21
Output of P71 can be set to N-ch open-drain output (EVDD0
P72
KR2/SO21
tolerance).
P73
KR0/SCK21/SCL21
KR3
Input/output can be specified in 1-bit units.
Use of an on-chip pull-up resistor can be specified by a
software setting.
P120
I/O
P121
Input
Port 12.
Analog input
1-bit I/O port and 4-bit input port.
port
P120 can be set to analog input.
Input port
For only P120, input/output can be specified.
P122
X1
XT1
specified by a software setting.
P124
P137
Note
X2/EXCLK
For only P120, use of an on-chip pull-up resistor can be
P123
ANI19/VCOUT0
XT2/EXCLKS
Input
Port 13.
Input port
INTP0
1-bit input port.
P146
P147
I/O
Port 14.
Input port
2-bit I/O port.
Analog input
P147 can be set to analog input.
port
−
ANI18/VCOUT1
Note
Input/output can be specified in 1-bit units.
Use of an on-chip pull-up resistor can be specified by a
software setting.
Note
Mounted on the 96 KB or more code flash memory products.
Remark Functions in parentheses in the above figure can be assigned via settings in the peripheral I/O redirection
registers 0, 1 (PIOR0, 1).
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CHAPTER 2 PIN FUNCTIONS
<R> 2.1.6 48-pin products
(1/2)
Function Name
P00
I/O
I/O
P01
P10
I/O
P11
P12
P13
Function
After Reset
Port 0.
2-bit I/O port.
Input of P01 can be set to TTL input buffer.
Output of P00 can be set to N-ch open-drain output (EVDD0
tolerance).
Input/output can be specified in 1-bit units.
Use of an on-chip pull-up resistor can be specified by a
software setting.
Input port
Port 1.
8-bit I/O port.
Input of P10 and P14 to P17 can be set to TTL input buffer.
Output of P10, P11, P13 to P15, and P17 can be set to N-ch
open-drain output (EVDD0 tolerance).
Input/output can be specified in 1-bit units.
Use of an on-chip pull-up resistor can be specified by a
software setting.
Input port
Alternate Function
TI00/TxD1/TRGCLKA/
(TRJO0)
TO00/RxD1/
TRGCLKB/TRJIO0
SCK11/SCL11/
TRDIOD1
SI11/SDA11/TRDIOC1
SO11/TRDIOB1/
Note
IVREF1
TxD2/SO20/
Note
TRDIOA1/IVCMP1
P14
RxD2/SI20/SDA20/
TRDIOD0/(SCLA0)
P15
PCLBUZ1/SCK20/
SCL20/TRDIOB0/
(SDAA0)
P16
TI01/TO01/INTP5/
Note
TRDIOC0/IVREF0 /
(RXD0)
P17
TI02/TO02/
TRDIOA0/TRDCLK0/
Note
IVCMP0 /(TXD0)
P20
I/O
P21
Port 2.
8-bit I/O port.
Input/output can be specified in 1-bit units.
Analog input
port
ANI0/AVREFP
ANI1/AVREFM
ANI2/ANO0
Note
P23
ANI3/ANO1
Note
P24
ANI4
P25
ANI5
P26
ANI6
P27
ANI7
P22
P30
I/O
P31
P40
P41
Note
I/O
Port 3.
2-bit I/O port.
Input of P30 can be set to TTL input buffer.
Output of P30 can be set to N-ch open-drain output (EVDD0
tolerance).
Input/output can be specified in 1-bit units.
Use of an on-chip pull-up resistor can be specified by a
software setting.
Input port
Port 4.
2-bit I/O port.
Input/output can be specified in 1-bit units.
Use of an on-chip pull-up resistor can be specified by a
software setting.
Input port
INTP3/RTC1HZ/
SCK00/SCL00/
TRJO0
TI03/TO03/INTP4/
(PCLBUZ0)/(TRJIO0)
TOOL0
(TRJIO0)
Mounted on the 96 KB or more code flash memory products.
Remark Functions in parentheses in the above figure can be assigned via settings in the peripheral I/O redirection
registers 0, 1 (PIOR0, 1).
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Function Name
P50
I/O
I/O
P51
Function
Port 5.
After Reset
Input port
Alternate Function
INTP1/SI00/RxD0/
2-bit I/O port.
TOOLRxD/SDA00/
Input of P50 can be set to TTL input buffer.
TRGIOA/(TRJO0)
Output of P50 and P51 can be set to N-ch open-drain output
INTP2/SO00/TxD0/
(EVDD0 tolerance).
TOOLTxD/TRGIOB
Input/output can be specified in 1-bit units.
Use of an on-chip pull-up resistor can be specified by a
software setting.
P60
I/O
Input port
4-bit I/O port.
P61
SSI00
tolerance).
P63
SCLA0
SDAA0
Output of P60 to P63 is N-ch open-drain output (6 V
P62
P70
Port 6.
−
Input/output can be specified in 1-bit units.
I/O
Port 7.
Input port
6-bit I/O port.
P71
KR1/SI21/SDA21
Output of P71 and P74 can be set to N-ch open-drain output
P72
KR0/SCK21/SCL21
KR2/SO21
(EVDD0 tolerance).
P73
Input/output can be specified in 1-bit units.
KR3/SO01
P74
Use of an on-chip pull-up resistor can be specified by a
KR4/INTP8/SI01/
software setting.
SDA01
P75
KR5/INTP9/SCK01/
SCL01
P120
P121
I/O
Input
Port 12.
Analog input
1-bit I/O port and 4-bit input port.
port
P120 can be set to analog input.
Input port
For only P120, input/output can be specified.
P122
Note
X1
X2/EXCLK
For only P120, use of an on-chip pull-up resistor can be
P123
ANI19/VCOUT0
XT1
specified by a software setting.
P124
XT2/EXCLKS
−
Output
Port 13.
Output port
P137
Input
1-bit output port and 1-bit input port.
Input port
INTP0
P140
I/O
Port 14.
Input port
PCLBUZ0/INTP6
P130
P146
P147
3-bit I/O port.
P147 can be set to analog input.
Input/output can be specified in 1-bit units.
Use of an on-chip pull-up resistor can be specified by a
−
Analog input
ANI18/VCOUT1
Note
port
software setting.
Note
Mounted on the 96 KB or more code flash memory products.
Remark Functions in parentheses in the above figure can be assigned via settings in the peripheral I/O redirection
registers 0, 1 (PIOR0, 1).
R01UH0186EJ0100 Rev.1.00
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RL78/G14
CHAPTER 2 PIN FUNCTIONS
<R> 2.1.7 52-pin products
(1/2)
Function Name
P00
I/O
I/O
P01
P02
P03
P10
I/O
P11
P12
P13
Function
After Reset
Alternate Function
Port 0.
4-bit I/O port.
Input of P01 and P03 can be set to TTL input buffer.
Output of P00, P02, and P03 can be set to N-ch open-drain
output (EVDD0 tolerance).
P02 and P03 can be set to analog input.
Input/output can be specified in 1-bit units.
Use of an on-chip pull-up resistor can be specified by a
software setting.
Input port
Analog input
port
ANI17/TxD1
Port 1.
8-bit I/O port.
Input of P10 and P14 to P17 can be set to TTL input buffer.
Output of P10, P11, P13 to P15, and P17 can be set to N-ch
open-drain output (EVDD0 tolerance).
Input/output can be specified in 1-bit units.
Use of an on-chip pull-up resistor can be specified by a
software setting.
Input port
SCK11/SCL11/
TRDIOD1
TI00/TRGCLKA/
(TRJO0)
TO00/TRGCLKB/
TRJIO0
ANI16/RxD1
SI11/SDA11/TRDIOC1
SO11/TRDIOB1/
Note
IVREF1
TxD2/SO20/
Note
TRDIOA1/IVCMP1
P14
RxD2/SI20/SDA20/
TRDIOD0/(SCLA0)
P15
PCLBUZ1/SCK20/
SCL20/TRDIOB0/
(SDAA0)
P16
TI01/TO01/INTP5/
Note
TRDIOC0/IVREF0 /
(RXD0)
P17
TI02/TO02/
TRDIOA0/TRDCLK0/
Note
IVCMP0 /(TXD0)
P20
I/O
P21
Port 2.
8-bit I/O port.
Input/output can be specified in 1-bit units.
Analog input
port
ANI0/AVREFP
ANI1/AVREFM
ANI2/ANO0
Note
P23
ANI3/ANO1
Note
P24
ANI4
P25
ANI5
P26
ANI6
P27
ANI7
P22
P30
I/O
P31
P40
P41
Note
I/O
Port 3.
2-bit I/O port.
Input of P30 can be set to TTL input buffer.
Output of P30 can be set to N-ch open-drain output (EVDD0
tolerance).
Input/output can be specified in 1-bit units.
Use of an on-chip pull-up resistor can be specified by a
software setting.
Input port
Port 4.
2-bit I/O port.
Input/output can be specified in 1-bit units.
Use of an on-chip pull-up resistor can be specified by a
software setting.
Input port
INTP3/RTC1HZ/
SCK00/SCL00/
TRJO0
TI03/TO03/INTP4/
(PCLBUZ0)/(TRJIO0)
TOOL0
(TRJIO0)
Mounted on the 96 KB or more code flash memory products.
Remark Functions in parentheses in the above figure can be assigned via settings in the peripheral I/O redirection
registers 0, 1 (PIOR0, 1).
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Function Name
P50
I/O
I/O
P51
Function
Port 5.
After Reset
Input port
Alternate Function
INTP1/SI00/RxD0/
2-bit I/O port.
TOOLRxD/SDA00/
Input of P50 can be set to TTL input buffer.
TRGIOA/(TRJO0)
Output of P50 and P51 can be set to N-ch open-drain output
INTP2/SO00/TxD0/
(EVDD0 tolerance).
TOOLTxD/TRGIOB
Input/output can be specified in 1-bit units.
Use of an on-chip pull-up resistor can be specified by a
software setting.
P60
I/O
Input port
4-bit I/O port.
P61
SSI00
tolerance).
P63
SCLA0
SDAA0
Output of P60 to P63 is N-ch open-drain output (6 V
P62
P70
Port 6.
−
Input/output can be specified in 1-bit units.
I/O
Port 7.
Input port
8-bit I/O port.
P71
KR1/SI21/SDA21
Output of P71 and P74 can be set to N-ch open-drain output
P72
KR0/SCK21/SCL21
KR2/SO21
(EVDD0 tolerance).
P73
Input/output can be specified in 1-bit units.
KR3/SO01
P74
Use of an on-chip pull-up resistor can be specified by a
KR4/INTP8/SI01/
software setting.
SDA01
P75
KR5/INTP9/SCK01/
SCL01
P76
KR6/INTP10/(RXD2)
P77
KR7/INTP11/(TXD2)
P120
P121
I/O
Input
Port 12.
Analog input
1-bit I/O port and 4-bit input port.
port
P120 can be set to analog input.
Input port
For only P120, input/output can be specified.
P122
Note
X1
X2/EXCLK
For only P120, use of an on-chip pull-up resistor can be
P123
ANI19/VCOUT0
XT1
specified by a software setting.
P124
XT2/EXCLKS
−
P130
Output
Port 13.
Output port
P137
Input
1-bit output port and 1-bit input port.
Input port
INTP0
P140
I/O
Port 14.
Input port
PCLBUZ0/INTP6
P146
P147
3-bit I/O port.
P147 can be set to analog input.
Input/output can be specified in 1-bit units.
Use of an on-chip pull-up resistor can be specified by a
−
Analog input
ANI18/VCOUT1
Note
port
software setting.
Note
Mounted on the 96 KB or more code flash memory products.
Remark Functions in parentheses in the above figure can be assigned via settings in the peripheral I/O redirection
registers 0, 1 (PIOR0, 1).
R01UH0186EJ0100 Rev.1.00
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RL78/G14
CHAPTER 2 PIN FUNCTIONS
<R> 2.1.8 64-pin products
(1/2)
Function Name
P00
I/O
I/O
P01
P02
P03
P04
Function
Port 0.
7-bit I/O port.
Input of P01, P03, and P04 can be set to TTL input buffer.
Output of P00, P02 to P04 can be set to N-ch open-drain
output (EVDD0 tolerance).
P02 and P03 can be set to analog input.
Input/output can be specified in 1-bit units.
Use of an on-chip pull-up resistor can be specified by a
software setting.
After Reset
Input port
Alternate Function
TI00/TRGCLKA/
(TRJO0)
TO00/TRGCLKB/
TRJIO0
Analog input
port
Input port
ANI17/SO10/TxD1
ANI16/SI10/RxD1/
SDA10
SCK10/SCL10
P05
(INTP10)
P06
(INTP11)/(TRJIO0)
P10
I/O
P11
P12
P13
Port 1.
8-bit I/O port.
Input of P10 and P14 to P17 can be set to TTL input buffer.
Output of P10, P11, P13 to P15, and P17 can be set to N-ch
open-drain output (EVDD0 tolerance).
Input/output can be specified in 1-bit units.
Use of an on-chip pull-up resistor can be specified by a
software setting.
Input port
SCK11/SCL11/
TRDIOD1
SI11/SDA11/
TRDIOC1
SO11/TRDIOB1/
Note
IVREF1 /(INTP5)
TxD2/SO20/
Note
TRDIOA1/IVCMP1
P14
RxD2/SI20/SDA20/
TRDIOD0/(SCLA0)
P15
SCK20/SCL20/
TRDIOB0/(SDAA0)
P16
TI01/TO01/INTP5/
Note
TRDIOC0/IVREF0 /
(SI00)/(RXD0)
P17
TI02/TO02/TRDIOA0/
Note
TRDCLK0/IVCMP0 /
(SO00)/(TXD0)
P20
I/O
P21
Port 2.
8-bit I/O port.
Input/output can be specified in 1-bit units.
Analog input
port
ANI0/AVREFP
ANI1/AVREFM
ANI2/ANO0
Note
P23
ANI3/ANO1
Note
P24
ANI4
P25
ANI5
P26
ANI6
P27
ANI7
P22
P30
P31
Note
I/O
Port 3.
2-bit I/O port.
Input of P30 can be set to TTL input buffer.
Output of P30 can be set to N-ch open-drain output (EVDD0
tolerance).
Input/output can be specified in 1-bit units.
Use of an on-chip pull-up resistor can be specified by a
software setting.
Input port
INTP3/RTC1HZ/
SCK00/SCL00/
TRJO0
TI03/TO03/INTP4
Mounted on the 96 KB or more code flash memory products.
Remark Functions in parentheses in the above figure can be assigned via settings in the peripheral I/O redirection
registers 0, 1 (PIOR0, 1).
R01UH0186EJ0100 Rev.1.00
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CHAPTER 2 PIN FUNCTIONS
(2/2)
Function Name
P40
I/O
I/O
P41
P42
P43
P50
I/O
P51
Function
After Reset
Port 4.
4-bit I/O port.
Input/output can be specified in 1-bit units.
Use of an on-chip pull-up resistor can be specified by a
software setting.
Input port
Port 5.
Input port
−
−
INTP1/SI00/RxD0/
6-bit I/O port.
TOOLRxD/SDA00/
Input of P50 and P55 can be set to TTL input buffer.
TRGIOA/(TRJO0)
Output of P50, P51, and P55 can be set to N-ch open-drain
INTP2/SO00/TxD0/
output (EVDD0 tolerance).
TOOLTxD/TRGIOB
(INTP1)
Use of an on-chip pull-up resistor can be specified by a
P53
TOOL0
(TRJIO0)
Input/output can be specified in 1-bit units.
P52
Alternate Function
(INTP2)
software setting.
P54
(INTP3)
P55
(PCLBUZ1)/(SCK00)/
(INTP4)
P60
I/O
Input port
4-bit I/O port.
P61
SSI00
tolerance).
P63
SCLA0
SDAA0
Output of P60 to P63 is N-ch open-drain output (6 V
P62
P70
Port 6.
−
Input/output can be specified in 1-bit units.
I/O
Port 7.
Input port
8-bit I/O port.
P71
KR1/SI21/SDA21
Output of P71 and P74 can be set to N-ch open-drain output
P72
KR0/SCK21/SCL21
KR2/SO21
(EVDD0 tolerance).
P73
Input/output can be specified in 1-bit units.
KR3/SO01
P74
Use of an on-chip pull-up resistor can be specified by a
KR4/INTP8/SI01/
software setting.
SDA01
P75
KR5/INTP9/SCK01/
SCL01
P76
KR6/INTP10/(RXD2)
P77
KR7/INTP11/(TXD2)
P120
P121
I/O
Input
Port 12.
Analog input
1-bit I/O port and 4-bit input port.
port
P120 can be set to analog input.
Input port
For only P120, input/output can be specified.
P122
Note
X1
X2/EXCLK
For only P120, use of an on-chip pull-up resistor can be
P123
ANI19/VCOUT0
XT1
specified by a software setting.
P124
XT2/EXCLKS
−
Output
Port 13.
Output port
P137
Input
1-bit output port and 1-bit input port.
Input port
INTP0
P140
I/O
Port 14.
Input port
PCLBUZ0/INTP6
P130
P141
P146
P147
Note
4-bit I/O port.
PCLBUZ1/INTP7
P147 can be set to analog input.
−
Input/output can be specified in 1-bit units.
Use of an on-chip pull-up resistor can be specified by a
Analog input
software setting.
port
ANI18/VCOUT1
Note
Mounted on the 96 KB or more code flash memory products.
Remark Functions in parentheses in the above figure can be assigned via settings in the peripheral I/O redirection
registers 0, 1 (PIOR0, 1).
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CHAPTER 2 PIN FUNCTIONS
<R> 2.1.9 80-pin products
(1/3)
Function Name
P00
I/O
I/O
P01
Function
Port 0.
After Reset
Input port
Alternate Function
TI00/TRGCLKA/
7-bit I/O port.
(TRJO0)
Input of P01, P03, and P04 can be set to TTL input buffer.
TO00/TRGCLKB/
Output of P00, P02 to P04 can be set to N-ch open-drain
TRJIO0
output (EVDD0 tolerance).
P02
P02 and P03 can be set to analog input.
P03
Input/output can be specified in 1-bit units.
Analog input
ANI17/SO10/TxD1
port
ANI16/SI10/RxD1/
SDA10
Use of an on-chip pull-up resistor can be specified by a
software setting.
P04
Input port
SCK10/SCL10
−
P05
P06
P10
(TRJIO0)
I/O
P11
Port 1.
Input port
TRDIOD1
Input of P10 and P14 to P17 can be set to TTL input buffer.
SI11/SDA11/
Output of P10, P11, P13 to P15, and P17 can be set to N-ch
TRDIOC1
open-drain output (EVDD0 tolerance).
P12
SO11/TRDIOB1/
P12, P13, P16, and P17 can be set to analog input.
IVREF1/(INTP5)
Input/output can be specified in 1-bit units.
P13
SCK11/SCL11/
8-bit I/O port.
Use of an on-chip pull-up resistor can be specified by a
TxD2/SO20/
software setting.
TRDIOA1/IVCMP1
RxD2/SI20/SDA20/
P14
TRDIOD0/(SCLA0)
SCK20/SCL20/
P15
TRDIOB0/(SDAA0)
TI01/TO01/INTP5/
P16
TRDIOC0/IVREF0/
(SI00)/(RXD0)
TI02/TO02/TRDIOA0/
P17
TRDCLK0/IVCMP0/
(SO00)/(TXD0)
P20
I/O
P21
Port 2.
Analog input
ANI0/AVREFP
8-bit I/O port.
port
ANI1/AVREFM
Input/output can be specified in 1-bit units.
P22
ANI2/ANO0
P23
ANI3/ANO1
P24
ANI4
P25
ANI5
P26
ANI6
P27
ANI7
P30
P31
I/O
Port 3.
Input port
INTP3/RTC1HZ/
2-bit I/O port.
SCK00/SCL00/
Input of P30 can be set to TTL input buffer.
TRJO0
Output of P30 can be set to N-ch open-drain output (EVDD0
tolerance).
Input/output can be specified in 1-bit units.
TI03/TO03/INTP4/
(PCLBUZ0)/(TRJIO0)
Use of an on-chip pull-up resistor can be specified by a
software setting.
Remark Functions in parentheses in the above figure can be assigned via settings in the peripheral I/O redirection
registers 0, 1 (PIOR0, 1).
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Function Name
P40
I/O
I/O
Port 4.
After Reset
Input port
6-bit I/O port.
P41
P44
(EVDD0 tolerance).
SCK01/SCL01/
Input/output can be specified in 1-bit units.
(INTP9)
Use of an on-chip pull-up resistor can be specified by a
SI01/SDA01
software setting.
P45
I/O
P51
Port 5.
SO01
Input port
TOOLRxD/SDA00/
Input of P50 and P53 to P55 can be set to TTL input buffer.
TRGIOA
Output of P50 to P55 can be set to N-ch open-drain output
INTP2/SO00/TxD0/
(EVDD0 tolerance).
TOOLTxD/TRGIOB
SO31/(INTP1)
Use of an on-chip pull-up resistor can be specified by a
P53
INTP1/SI00/RxD0/
6-bit I/O port.
Input/output can be specified in 1-bit units.
P52
TOOL0
(INTP8)
Output of P43 to P45 can be set to N-ch open-drain output
P43
Alternate Function
(TRJIO0)
Input of P43 and P44 can be set to TTL input buffer.
P42
P50
Function
SI31/SDA31/(INTP2)
software setting.
SCK31/SCL31/
P54
(INTP3)
(PCLBUZ1)/(SCK00)/
P55
(INTP4)
P60
I/O
Port 6.
Input port
8-bit I/O port.
P61
SDAA0
Output of P60 to P63 is N-ch open-drain output (6 V
P62
SCLA0
SSI00/SCLA1
tolerance).
P63
Input/output can be specified in 1-bit units.
SDAA1
P64
For P64 to P67, use of an on-chip pull-up resistor can be
TI10/TO10
specified by a software setting.
P65
TI11/TO11
P66
TI12/TO12
P67
P70
TI13/TO13
I/O
Port 7.
Input port
8-bit I/O port.
P71
KR1/SI21/SDA21
Output of P71 and P74 can be set to N-ch open-drain output
P72
KR0/SCK21/SCL21
KR2/SO21
(EVDD0 tolerance).
P73
Input/output can be specified in 1-bit units.
KR3
P74
Use of an on-chip pull-up resistor can be specified by a
KR4/INTP8
software setting.
P75
KR5/INTP9
P76
KR6/INTP10/(RXD2)
P77
P100
KR7/INTP11/(TXD2)
I/O
Port 10.
Analog input
1-bit I/O port.
port
ANI20/(INTP10)
P100 can be set to analog input.
Input/output can be specified.
Use of an on-chip pull-up resistor can be specified by a
software setting.
Remark Functions in parentheses in the above figure can be assigned via settings in the peripheral I/O redirection
registers 0, 1 (PIOR0, 1).
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Function Name
P110
I/O
I/O
Function
Port 11.
After Reset
−
Input port
2-bit I/O port.
P111
Alternate Function
(INTP11)
Input/output can be specified in 1-bit units.
Use of an on-chip pull-up resistor can be specified by a
software setting.
P120
P121
I/O
Input
Port 12.
Analog input
1-bit I/O port and 4-bit input port.
port
P120 can be set to analog input.
Input port
For only P120, input/output can be specified.
P122
X1
X2/EXCLK
For only P120, use of an on-chip pull-up resistor can be
P123
ANI19/VCOUT0
XT1
specified by a software setting.
P124
XT2/EXCLKS
−
Output
Port 13.
Output port
P137
Input
1-bit output port and 1-bit input port.
Input port
INTP0
P140
I/O
Port 14.
Input port
PCLBUZ0/INTP6
P130
7-bit I/O port.
P141
PCLBUZ1/INTP7
Input of P142 and P143 can be set to TTL input buffer.
P142
SCK30/SCL30
Output of P142 to P144 can be set to N-ch open-drain output
P143
(EVDD0 tolerance).
SI30/RXD3/SDA30
P144
P147 can be set to analog input.
SO30/TXD3
Input/output can be specified in 1-bit units.
P146
−
Use of an on-chip pull-up resistor can be specified by a
P147
software setting.
Analog input
ANI18/VCOUT1
port
P150
P151
P152
I/O
Port 15.
Analog input
ANI8
4-bit I/O port.
port
ANI9
Input/output can be specified in 1-bit units.
P153
ANI10
ANI11
Remark Functions in parentheses in the above figure can be assigned via settings in the peripheral I/O redirection
registers 0, 1 (PIOR0, 1).
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CHAPTER 2 PIN FUNCTIONS
<R> 2.1.10 100-pin products
(1/3)
Function Name
P00
I/O
I/O
P01
Function
Port 0.
After Reset
Input port
Alternate Function
TI00/TRGCLKA/
7-bit I/O port.
(TRJO0)
Input of P01, P03, and P04 can be set to TTL input buffer.
TO00/TRGCLKB/
Output of P00, P02 to P04 can be set to N-ch open-drain
TRJIO0
output (EVDD0 tolerance).
P02
P02 and P03 can be set to analog input.
P03
Input/output can be specified in 1-bit units.
Analog input
ANI17/SO10/TxD1
port
ANI16/SI10/RxD1/
SDA10
Use of an on-chip pull-up resistor can be specified by a
software setting.
P04
Input port
SCK10/SCL10
−
P05
P06
P10
(TRJIO0)
I/O
P11
Port 1.
Input port
TRDIOD1
Input of P10 and P14 to P17 can be set to TTL input buffer.
SI11/SDA11/
Output of P10, P11, P13 to P15, and P17 can be set to N-ch
TRDIOC1
open-drain output (EVDD0 tolerance).
P12
SO11/TRDIOB1/
P12, P13, P16, and P17 can be set to analog input.
IVREF1/(INTP5)
Input/output can be specified in 1-bit units.
P13
SCK11/SCL11/
8-bit I/O port.
Use of an on-chip pull-up resistor can be specified by a
TxD2/SO20/
software setting.
TRDIOA1/IVCMP1
RxD2/SI20/SDA20/
P14
TRDIOD0/(SCLA0)
SCK20/SCL20/
P15
TRDIOB0/(SDAA0)
TI01/TO01/INTP5/
P16
TRDIOC0/IVCMP0/
(SI00)/(RXD0)
TI02/TO02/TRDIOA0/
P17
TRDCLK0/IVCMP0/
(SO00)/(TXD0)
P20
I/O
P21
Port 2.
Analog input
ANI0/AVREFP
8-bit I/O port.
port
ANI1/AVREFM
Input/output can be specified in 1-bit units.
P22
ANI2/ANO0
P23
ANI3/ANO1
P24
ANI4
P25
ANI5
P26
ANI6
P27
ANI7
P30
P31
I/O
Port 3.
Input port
INTP3/RTC1HZ/
2-bit I/O port.
SCK00/SCL00/
Input of P30 can be set to TTL input buffer.
TRJO0
Output of P30 can be set to N-ch open-drain output (EVDD0
tolerance).
Input/output can be specified in 1-bit units.
TI03/TO03/INTP4/
(PCLBUZ0)/(TRJIO0)
Use of an on-chip pull-up resistor can be specified by a
software setting.
Remark Functions in parentheses in the above figure can be assigned via settings in the peripheral I/O redirection
registers 0, 1 (PIOR0, 1).
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Function Name
P40
I/O
I/O
Function
Port 4.
After Reset
Input port
8-bit I/O port.
P41
Alternate Function
TOOL0
(TRJIO0)
Input of P43 and P44 can be set to TTL input buffer.
P42
−
Output of P43 to P45 can be set to N-ch open-drain output
P43
(EVDD0 tolerance).
SCK01/SCL01
P44
Input/output can be specified in 1-bit units.
SI01/SDA01
Use of an on-chip pull-up resistor can be specified by a
P45
SO01
software setting.
P46
INTP1
P47
INTP2
P50
I/O
P51
Port 5.
Input port
SDA00/TRGIOA/
Input of P50 and P53 to P55 can be set to TTL input buffer.
(TRJO0)
Output of P50 to P55 can be set to N-ch open-drain output
SO00/TxD0/TOOLTxD
(EVDD0 tolerance).
/TRGIOB
Input/output can be specified in 1-bit units.
P52
SO31
Use of an on-chip pull-up resistor can be specified by a
P53
SI00/RxD0/TOOLRxD/
8-bit I/O port.
SI31/SDA31
software setting.
P54
SCK31/SCL31
P55
(PCLBUZ1)/(SCK00)
P56
(INTP1)
P57
(INTP3)
P60
I/O
Port 6.
Input port
8-bit I/O port.
P61
SDAA0
Output of P60 to P63 is N-ch open-drain output (6 V
P62
SCLA0
SSI00/SCLA1
tolerance).
P63
Input/output can be specified in 1-bit units.
SDAA1
P64
For P64 to P67, use of an on-chip pull-up resistor can be
TI10/TO10
specified by a software setting.
P65
TI11/TO11
P66
TI12/TO12
P67
TI13/TO13
P70
P71
P72
I/O
Port 7.
8-bit I/O port.
Output of P71 and P74 can be set to N-ch open-drain output
(EVDD0 tolerance).
Input port
KR0/SCK21/SCL21
KR1/SI21/SDA21
KR2/SO21
P73
Input/output can be specified in 1-bit units.
KR3
P74
Use of an on-chip pull-up resistor can be specified by a
KR4/INTP8
P75
software setting.
KR5/INTP9
P76
KR6/INTP10/(RXD2)
P77
KR7/INTP11/(TXD2)
Remark Functions in parentheses in the above figure can be assigned via settings in the peripheral I/O redirection
registers 0, 1 (PIOR0, 1).
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Function Name
P80
I/O
I/O
P81
Function
Port 8.
After Reset
Input port
(SI10)/(RXD1)/
Input of P80 and P81 can be set to TTL input buffer.
(SDA10)
(SO10)/(TXD1)
(EVDD0 tolerance).
P83
Input/output can be specified in 1-bit units.
P84
Use of an on-chip pull-up resistor can be specified by a
−
(INTP6)
software setting.
P85
(SCK10)/(SCL10)
8-bit I/O port.
Output of P80 to P82 can be set to N-ch open-drain output
P82
Alternate Function
(INTP7)
P86
(INTP8)
P87
(INTP9)
P100
I/O
P101
Port 10.
Analog input
3-bit I/O port.
port
P100 can be set to analog input.
Input port
ANI20/(INTP10)
−
Input/output can be specified in 1-bit units.
P102
−
Use of an on-chip pull-up resistor can be specified by a
software setting.
P110
I/O
Port 11.
Input port
(INTP11)
2-bit I/O port.
P111
−
Input/output can be specified in 1-bit units.
Use of an on-chip pull-up resistor can be specified by a
software setting.
P120
P121
I/O
Input
Port 12.
Analog input
1-bit I/O port and 4-bit input port.
port
P120 can be set to analog input.
Input port
For only P120, input/output can be specified.
P122
X1
X2/EXCLK
For only P120, use of an on-chip pull-up resistor can be
P123
ANI19/VCOUT0
XT1
specified by a software setting.
P124
XT2/EXCLKS
−
Output
Port 13.
Output port
P137
Input
1-bit output port and 1-bit input port.
Input port
INTP0
P140
I/O
Port 14.
Input port
PCLBUZ0/INTP6
P130
8-bit I/O port.
P141
PCLBUZ1/INTP7
Input of P142 and P143 can be set to TTL input buffer.
P142
SCK30/SCL30
Output of P142 to P144 can be set to N-ch open-drain output
P143
(EVDD0 tolerance).
SI30/RXD3/SDA30
P144
P147 can be set to analog input.
SO30/TXD3
Input/output can be specified in 1-bit units.
P145
−
Use of an on-chip pull-up resistor can be specified by a
P146
(INTP4)
software setting.
Analog input
P147
ANI18/VCOUT1
port
P150
P151
P152
I/O
Port 15.
Analog input
ANI8
7-bit I/O port.
port
ANI9
Input/output can be specified in 1-bit units.
ANI10
P153
ANI11
P154
ANI12
P155
ANI13
P156
ANI14
Remark Functions in parentheses in the above figure can be assigned via settings in the peripheral I/O redirection
registers 0, 1 (PIOR0, 1).
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CHAPTER 2 PIN FUNCTIONS
2.1.11 Pins for each product (pins other than port pins)
(1/6)
100-
80-
64-
52-
48-
44-
40-
36-
32-
30-
pin
pin
pin
pin
pin
pin
pin
pin
pin
pin
A/D converter analog
√
√
√
√
√
√
√
√
√
√
input
√
√
√
√
√
√
√
√
√
√
ANI2
√
√
√
√
√
√
√
√
√
√
ANI3
√
√
√
√
√
√
√
√
√
√
ANI4
√
√
√
√
√
√
√
√
−
−
ANI5
√
√
√
√
√
√
√
√
−
−
ANI6
√
√
√
√
√
√
√
−
−
−
ANI7
√
√
√
√
√
√
−
−
−
−
ANI8
√
√
−
−
−
−
−
−
−
−
ANI9
√
√
−
−
−
−
−
−
−
−
ANI10
√
√
−
−
−
−
−
−
−
−
ANI11
√
√
−
−
−
−
−
−
−
−
ANI12
√
−
−
−
−
−
−
−
−
−
ANI13
√
−
−
−
−
−
−
−
−
−
ANI14
√
−
−
−
−
−
−
−
−
−
ANI16
√
√
√
√
−
−
−
−
√
√
ANI17
√
√
√
√
−
−
−
−
√
√
ANI18
√
√
√
√
√
√
√
√
√
√
ANI19
√
√
√
√
√
√
√
√
√
√
ANI20
√
√
−
−
−
−
−
−
−
−
√
√
Note Note Note Note Note Note Note Note
√
√
Note Note Note Note Note Note Note
External interrupt request
√
√
√
√
√
√
√
√
√
√
input
√
√
√
√
√
√
√
√
√
√
INTP2
√
√
√
√
√
√
√
√
√
√
INTP3
√
√
√
√
√
√
√
√
√
√
INTP4
√
√
√
√
√
√
√
√
√
√
INTP5
√
√
√
√
√
√
√
√
√
√
INTP6
√
√
√
√
√
−
−
−
−
−
INTP7
√
√
√
−
−
−
−
−
−
−
INTP8
√
√
√
√
√
−
−
−
−
−
INTP9
√
√
√
√
√
−
−
−
−
−
INTP10
√
√
√
√
−
−
−
−
−
−
INTP11
√
√
√
√
−
−
−
−
−
−
Comparator analog
√
√
Note Note Note Note Note Note Note Note
voltage input
√
√
Note Note Note Note Note Note Note Note
Comparator reference
√
√
Note Note Note Note Note Note Note Note
voltage input
√
√
Note Note Note Note Note Note Note Note
Function
I/O
Function
Name
ANI0
Input
ANI1
ANO0
Output
D/A converter output
ANO1
INTP0
Input
INTP1
IVCMP0
Input
IVCMP1
IVREF0
IVREF1
Note
Input
−
Mounted on the 96 KB or more code flash memory products.
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(2/6)
Function
100-
80-
64-
52-
48-
44-
40-
36-
32-
30-
pin
pin
pin
pin
pin
pin
pin
pin
pin
pin
√
√
√
√
√
√
√
−
−
−
KR1
√
√
√
√
√
√
√
−
−
−
KR2
√
√
√
√
√
√
√
−
−
−
KR3
√
√
√
√
√
√
√
−
−
−
KR4
√
√
√
√
√
−
−
−
−
−
KR5
√
√
√
√
√
−
−
−
−
−
KR6
√
√
√
√
−
−
−
−
−
−
KR7
√
√
√
√
−
−
−
−
−
−
PCLBUZ0 Output
Clock output/buzzer
√
√
√
√
√
√
√
√
√
√
PCLBUZ1
output
√
√
√
√
√
√
√
√
√
√
Connecting regulator
√
√
√
√
√
√
√
√
√
√
√
√
√
√
√
√
√
−
−
−
I/O
Function
Name
KR0
Input
−
REGC
Key interrupt input
output stabilization
capacitance for internal
operation.
Connect to VSS via a
capacitor (0.47 to 1 μF).
RTC1HZ
Output
Real-time clock correction
clock (1 Hz) output
RESET
Input
System reset input
√
√
√
√
√
√
√
√
√
√
RxD0
Input
Serial data input to
√
√
√
√
√
√
√
√
√
√
√
√
√
√
√
√
√
√
√
√
√
√
√
√
√
√
√
√
√
√
√
√
−
−
−
−
−
−
−
−
Clock input/output for
√
√
√
√
√
√
√
√
√
√
CSI00, CSI01, CSI10,
√
√
√
√
√
−
−
−
−
−
√
√
√
−
−
−
−
−
−
−
SCK11
√
√
√
√
√
√
√
√
√
√
SCK20
√
√
√
√
√
√
√
√
√
√
SCK21
√
√
√
√
√
√
√
√
−
−
SCK30
√
√
−
−
−
−
−
−
−
−
SCK31
√
√
−
−
−
−
−
−
−
−
√
√
√
√
√
√
√
√
√
√
√
√
−
−
−
−
−
−
−
−
UART0
Serial data input to
RxD1
UART1
Serial data input to
RxD2
UART2
Serial data input to
RxD3
UART3
SCK00
I/O
SCK01
CSI11, CSI20, CSI21,
SCK10
SCLA0
CSI30, and CSI31
I/O
2
Clock input/output for I C
SCLA1
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CHAPTER 2 PIN FUNCTIONS
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Function
100-
80-
64-
52-
48-
44-
40-
36-
32-
30-
pin
pin
pin
pin
pin
pin
pin
pin
pin
pin
√
√
√
√
√
√
√
√
√
√
√
√
√
√
√
−
−
−
−
−
SCL10
√
√
√
−
−
−
−
−
−
−
SCL11
√
√
√
√
√
√
√
√
√
√
SCL20
√
√
√
√
√
√
√
√
√
√
SCL21
√
√
√
√
√
√
√
√
−
−
SCL30
√
√
−
−
−
−
−
−
−
−
√
√
−
−
−
−
−
−
−
−
√
√
√
√
√
√
√
√
√
√
√
√
−
−
−
−
−
−
−
−
√
√
√
√
√
√
√
√
√
√
√
√
√
√
√
−
−
−
−
−
SDA10
√
√
√
−
−
−
−
−
−
−
SDA11
√
√
√
√
√
√
√
√
√
√
SDA20
√
√
√
√
√
√
√
√
√
√
I/O
Function
Name
SCL00
I/O
Clock input/output for
2
simplified I C
SCL01
SCL31
SDAA0
I/O
2
Serial data I/O for I C
SDAA1
SDA00
I/O
Serial data I/O for
2
simplified I C
SDA01
SDA21
√
√
√
√
√
√
√
√
−
−
SDA30
√
√
−
−
−
−
−
−
−
−
SDA31
√
√
−
−
−
−
−
−
−
−
Serial data input to
√
√
√
√
√
√
√
√
√
√
CSI00, CSI01, CSI10,
√
√
√
√
√
−
−
−
−
−
√
√
√
−
−
−
−
−
−
−
SI11
√
√
√
√
√
√
√
√
√
√
SI20
√
√
√
√
√
√
√
√
√
√
SI21
√
√
√
√
√
√
√
√
−
−
SI30
√
√
−
−
−
−
−
−
−
−
SI31
√
√
−
−
−
−
−
−
−
−
Serial data output from
√
√
√
√
√
√
√
√
√
√
CSI00, CSI01, CSI10,
√
√
√
√
√
−
−
−
−
−
√
√
√
−
−
−
−
−
−
−
SO11
√
√
√
√
√
√
√
√
√
√
SO20
√
√
√
√
√
√
√
√
√
√
SO21
√
√
√
√
√
√
√
√
−
−
SO30
√
√
−
−
−
−
−
−
−
−
SO31
√
√
−
−
−
−
−
−
−
−
√
√
√
√
√
√
√
√
√
√
SI00
Input
SI01
CSI11, CSI20, CSI21,
SI10
SO00
CSI30, and CSI31
Output
SO01
CSI11, CSI20, CSI21,
SO10
SSI00
CSI30, and CSI31
Input
Chip select input to CSI00
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CHAPTER 2 PIN FUNCTIONS
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Function
100-
80-
64-
52-
48-
44-
40-
36-
32-
30-
pin
pin
pin
pin
pin
pin
pin
pin
pin
pin
√
√
√
√
√
√
√
√
√
√
√
√
√
√
√
√
√
√
√
√
√
√
√
√
√
√
√
√
√
√
√
√
√
√
√
√
√
√
√
√
√
√
−
−
−
−
−
−
−
−
√
√
−
−
−
−
−
−
−
−
√
√
−
−
−
−
−
−
−
−
√
√
−
−
−
−
−
−
−
−
16-bit timer 00 output
√
√
√
√
√
√
√
√
√
√
TO01
16-bit timer 01 output
√
√
√
√
√
√
√
√
√
√
TO02
16-bit timer 02 output
√
√
√
√
√
√
√
√
√
√
TO03
16-bit timer 03 output
√
√
√
√
√
√
√
√
√
√
TO10
16-bit timer 10 output
√
√
−
−
−
−
−
−
−
−
TO11
16-bit timer 11 output
√
√
−
−
−
−
−
−
−
−
TO12
16-bit timer 12 output
√
√
−
−
−
−
−
−
−
−
TO13
16-bit timer 13 output
√
√
−
−
−
−
−
−
−
−
√
√
√
√
√
√
√
√
√
I/O
Function
Name
TI00
Input
External count clock input to
16-bit timer 00
External count clock input to
TI01
16-bit timer 01
External count clock input to
TI02
16-bit timer 02
External count clock input to
TI03
16-bit timer 03
External count clock input to
TI10
16-bit timer 10
External count clock input to
TI11
16-bit timer 11
External count clock input to
TI12
16-bit timer 12
External count clock input to
TI13
16-bit timer 13
TO00
Output
TRJIO0
I/O
Timer RJ input/output
√
TRJO0
Output
Timer RJ output
√
√
√
√
√
√
√
√
√
√
TRDCLK0
Input
Timer RD external clock
√
√
√
√
√
√
√
√
√
√
Timer RD0 input/output
√
√
√
√
√
√
√
√
√
√
TRDIOB0
Timer RD0 input/output
√
√
√
√
√
√
√
√
√
√
TRDIOC0
Timer RD0 input/output
√
√
√
√
√
√
√
√
√
√
TRDIOD0
Timer RD0 input/output
√
√
√
√
√
√
√
√
√
√
TRDIOA1
Timer RD1 input/output
√
√
√
√
√
√
√
√
√
√
TRDIOB1
Timer RD1 input/output
√
√
√
√
√
√
√
√
√
√
TRDIOC1
Timer RD1 input/output
√
√
√
√
√
√
√
√
√
√
TRDIOD1
Timer RD1 input/output
√
√
√
√
√
√
√
√
√
√
TRGIOA
Timer RG input/output
√
√
√
√
√
√
√
√
√
√
TRGIOB
Timer RG input/output
√
√
√
√
√
√
√
√
√
√
TRGCLKA Input
Timer RG external clock
√
√
√
√
√
√
√
√
√
√
√
√
√
√
√
√
√
√
√
√
input
TRDIOA0
I/O
input
TRGCLKB
Timer RG external clock
input
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CHAPTER 2 PIN FUNCTIONS
(5/6)
Function
I/O
Function
Name
TxD0
Output
Serial data output from
100-
80-
64-
52-
48-
44-
40-
36-
32-
30-
pin
pin
pin
pin
pin
pin
pin
pin
pin
pin
√
√
√
√
√
√
√
√
√
√
√
√
√
√
√
√
√
√
√
√
√
√
√
√
√
√
√
√
√
√
√
√
−
−
−
−
−
−
−
−
√
√
Note Note Note Note Note Note Note Note
√
√
Note Note Note Note Note Note Note Note
UART0
Serial data output from
TxD1
UART1
TxD2
Serial data output from
TxD3
Serial data output from
UART2
UART3
VCOUT0
Output
Comparator output
VCOUT1
−
Resonator connection for
√
√
√
√
√
√
√
√
√
√
X2
−
main system clock
√
√
√
√
√
√
√
√
√
√
EXCLK
Input
External clock input for
√
√
√
√
√
√
√
√
√
√
√
√
√
√
√
√
√
−
−
−
X1
main system clock
EXCLKS
Input
External clock input for
subsystem clock
−
Resonator connection for
√
√
√
√
√
√
√
−
−
−
XT2
−
subsystem clock
√
√
√
√
√
√
√
−
−
−
VDD
−
<30-pin, 32-pin, 36-pin,
√
√
√
√
√
√
√
√
√
√
XT1
40-pin, 44-pin, 48-pin,
52-pin>
Positive power supply for
all pins
<64-pin, 80-pin, 100-pin>
Positive power supply for
P20 to P27, P121 to
P124, P137, P150 to
P156 and other than
ports
EVDD0
−
Positive power supply for
√
√
√
−
−
−
−
−
−
−
EVDD1
−
ports (other than P20 to
√
−
−
−
−
−
−
−
−
−
P27, P121 to P124,
P137, P150 to P156)
Note
Mounted on the 96 KB or more code flash memory products.
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CHAPTER 2 PIN FUNCTIONS
(6/6)
Function
I/O
Function
Name
AVREFP
Input
A/D converter reference
100-
80-
64-
52-
48-
44-
40-
36-
32-
30-
pin
pin
pin
pin
pin
pin
pin
pin
pin
pin
√
√
√
√
√
√
√
√
√
√
potential (+ side) input
AVREFM
Input
A/D converter reference
potential (− side) input
√
√
√
√
√
√
√
√
√
√
VSS
−
<30-pin, 32-pin, 36-pin,
√
√
√
√
√
√
√
√
√
√
40-pin, 44-pin, 48-pin,
52-pin >
Ground potential for all
pins
<64-pin, 80-pin, 100-pin >
Ground potential for P20
to P27, P121 to P124,
P137, 150 to P156 and
other than ports
EVSS0
EVSS1
−
Ground potential for ports
√
√
√
−
−
−
−
−
−
−
−
(other than P20 to P27,
√
−
−
−
−
−
−
−
−
−
√
√
√
√
√
√
√
√
√
√
√
√
√
√
√
√
√
√
√
√
√
√
√
√
√
√
√
√
√
√
P121 to P124, P137,
P150 to P156)
TOOLRxD Input
UART reception pin for
the external device
connection used during
flash memory
programming
TOOLTxD Output
UART transmission pin
for the external device
connection used during
flash memory
programming
TOOL0
I/O
Data I/O for flash
memory
programmer/debugger
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CHAPTER 2 PIN FUNCTIONS
2.2 Description of Pin Functions
Remark
The pins mounted depend on the product. See 1.3 Pin Configuration (Top View) and 2.1 Pin Function
List.
2.2.1 P00 to P06 (port 0)
P00 to P06 function as an I/O port. These pins also function as timer I/O, A/D converter analog input, serial interface
data I/O, and clock I/O.
Use of an on-chip pull-up resistor can be specified by pull-up resistor option register 0 (PU0).
Input to the P01, P03, and P04 pins can be specified through a normal input buffer or a TTL input buffer in 1-bit units,
using port input mode register 0 (PIM0).
Output from the P00 and P02 to P04 pins can be specified as normal CMOS output or N-ch open-drain output (EVDD0
tolerance) in 1-bit units, using port output mode register 0 (POM0).
When the following pins are used as input, specify them as either digital or analog in Port mode control register 0
(PMC0). This register can be specified in 1-bit unit.
・ P00 and P01 pins of the 30 and 32-pin products
・ P02 and P03 pins of the 52, 64, 80, and 100-pin products
The following operation modes can be specified in 1-bit units.
(1) Port mode
P00 to P06 function as an I/O port. P00 to P06 can be set to input or output port in 1-bit units using port mode
register 0 (PM0).
(2) Control mode
P00 to P06 function as timer I/O, A/D converter analog input, serial interface data I/O, and clock I/O.
(a) ANI16, ANI17
These are the analog input pins (ANI16, ANI17) of A/D converter.
When using these pins as analog input pins, see 14.10 (5) Analog input (ANIn) pins.
(b) SCK10
This is a serial clock I/O pin of serial interface CSI10.
(c) SI10
This is a serial data input pin of serial interface CSI10.
(d) SO10
This is a serial data output pin of serial interface CSI10.
(e) TI00
This is a pin for inputting an external count clock/capture trigger to 16-bit timer 00.
(f) TO00
This is a timer output pin of 16-bit timer 00.
(g) TxD1
This is a serial data output pin of serial interface UART1.
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CHAPTER 2 PIN FUNCTIONS
(h) RxD1
This is a serial data input pin of serial interface UART1.
(i)
SDA10
This is a serial data I/O pin of serial interface for simplified I2C.
(j)
SCL10
This is a serial clock I/O pin of serial interface for simplified I2C.
(k) TRGCLKA, TRGCLKB
These are the external clock input pins to timer RG.
(l)
TRJIO0
This is a timer I/O pin to timer RJ.
2.2.2 P10 to P17 (port 1)
P10 to P17 function as an I/O port. These pins also function as serial interface data I/O, clock I/O, timer I/O, external
interrupt request input, comparator reference voltage input, and comparator analog voltage input.
Use of an on-chip pull-up resistor can be specified by pull-up resistor option register 1 (PU1).
Input to the P10 and P14 to P17 pins can be specified through a normal input buffer or a TTL input buffer in 1-bit units,
using port input mode register 1 (PIM1).
Output from the P10, P11, P13 to P15 and P17 pins can be specified as normal CMOS output or N-ch open-drain
output (EVDD0 tolerance) in 1-bit units, using port output mode register 1 (POM1).
Input to the P12, P13, P16, and P17 pins of the products with 96 KB or more code flash memory can be specified as
analog input or digital I/O in 1-bit units, using port mode control register 1 (PMC1).
The following operation modes can be specified in 1-bit units.
(1) Port mode
P10 to P17 function as an I/O port. P10 to P17 can be set to input or output port in 1-bit units using port mode
register 1 (PM1).
(2) Control mode
P10 to P17 function as serial interface data I/O, clock I/O, timer I/O, external interrupt request input, comparator
reference voltage input, and comparator analog voltage input.
(a) INTP5
This is an external interrupt request input pin for which the valid edge (rising edge, falling edge, or both rising and
falling edges) can be specified.
(b) TxD2
This is a serial data output pins of serial interface UART2.
(c) RxD2
This is a serial data input pins of serial interface UART2.
(d) SCK11, SCK20
These are the serial clock I/O pins of serial interface CSI11 and CSI20.
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CHAPTER 2 PIN FUNCTIONS
(e) SI11, SI20
These are the serial data input pins of serial interface CSI11 and CSI20.
(f) SO11, SO20
These are the serial data output pins of serial interface CSI11 and CSI20.
(g) TI01, TI02
These are the pins for inputting an external count clock/capture trigger to 16-bit timers 01 and 02.
(h) TO01, TO02
These are the timer output pins of 16-bit timers 01 and 02.
(i)
SDA11, SDA20
These are the serial data I/O pins of serial interface for simplified I2C.
(j)
SCL11, SCL20
These are the serial clock I/O pins of serial interface for simplified I2C.
(k) TRDIOA0, TRDIOB0, TRDIOC0, TRDIOD0, TRDIOA1, TRDIOB1, TRDIOC1, TRDIOD1
These are the timer I/O pins of timer RD.
(l)
TRDCLK0
This is a external input pin to timer RD.
(m) IVCMP0, IVCMP1
These are the comparator analog voltage input pins.
(n) IVREF0, IVREF1
These are the comparator reference voltage input pins.
2.2.3 P20 to P27 (port 2)
P20 to P27 function as an I/O port. These pins also function as A/D converter analog input and reference voltage input,
and D/A converter output in products with 96 KB code flash memory.
Setting digital or analog to each pin can be done in A/D port configuration register (ADPC).
The following operation modes can be specified in 1-bit units.
(1) Port mode
P20 to P27 function as an I/O port. P20 to P27 can be set to input or output port in 1-bit units using port mode
register 2 (PM2).
(2) Control mode
P20 to P27 function as A/D converter analog input, reference voltage input and D/A converter output.
(a) ANI0 to ANI7
These are the analog input pins (ANI0 to ANI7) of A/D converter.
When using these pins as analog input pins, see 14.10 (5) Analog input (ANIn) pins.
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(b) AVREFP
This is a pin that inputs the A/D converter reference potential (+ side).
(c) AVREFM
This is a pin that inputs the A/D converter reference potential (−side).
(d) ANO0, ANO1
These are the D/A converter output pins.
2.2.4 P30, P31 (port 3)
P30 and P31 function as an I/O port. These pins also function as external interrupt request input, real-time clock
correction clock output, serial interface clock I/O, and timer I/O.
Use of an on-chip pull-up resistor can be specified by pull-up resistor option register 3 (PU3).
Input to the P30 pin can be specified through a normal input buffer or a TTL input buffer in 1-bit units, using port input
mode register 3 (PIM3).
Output from the P30 pin can be specified as normal CMOS output or N-ch open-drain output (EVDD0 tolerance) in 1-bit
units, using port output mode register 3 (POM3).
The following operation modes can be specified in 1-bit units.
(1) Port mode
P30 and P31 function as an I/O port. P30 and P31 can be set to input or output port in 1-bit units using port mode
register 3 (PM3).
(2) Control mode
P30 and P31 function as external interrupt request input, real-time clock correction clock output, serial interface clock
I/O, and timer I/O.
(a) INTP3, INTP4
These are the external interrupt request input pins for which the valid edge (rising edge, falling edge, or both
rising and falling edges) can be specified.
(b) RTC1HZ
This is a real-time clock correction clock (1 Hz) output pin.
(c) SCK00
This is a serial clock I/O pin of serial interface CSI00.
(d) SCL00
This is a serial clock I/O pin of serial interface for simplified I2C.
(e) TI03
This is a pin for inputting an external count clock/capture trigger to 16-bit timer 03.
(f) TO03
This is a timer output pin from 16-bit timer 03.
(g) TRJO0
This is a timer RJ output pin.
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2.2.5 P40 to P47 (port 4)
P40 to P47 function as an I/O port. These pins also function as data I/O for a flash memory programmer/debugger,
serial interface data I/O, clock I/O, and external interrupt request input.
Use of an on-chip pull-up resistor can be specified by pull-up resistor option register 4 (PU4).
Be sure to connect an external pull-up resistor to P40 when on-chip debugging is enabled (by using an option byte).
Input to the P43 and P44 pins can be specified through a normal input buffer or a TTL input buffer in 1-bit units, using
port input mode register 4 (PIM4).
Output from the P43 to P45 pins can be specified as normal CMOS output or N-ch open-drain output (EVDD0 tolerance)
in 1-bit units, using port output mode register 4 (POM4).
The following operation modes can be specified in 1-bit units.
(1) Port mode
P40 to P47 function as an I/O port. P40 to P47 can be set to input or output port in 1-bit units using port mode
register 4 (PM4).
(2) Control mode
P40 to P47 function as data I/O for a flash memory programmer/debugger, serial interface data I/O, clock I/O, and
external interrupt request input.
(a) TOOL0
This is a data I/O pin for a flash memory programmer/debugger.
Be sure to pull up this pin externally when on-chip debugging is enabled (pulling it down is prohibited).
(b) SCK01
This is a serial clock I/O pin of serial interface CSI01.
(c) SCL01
This is a serial clock I/O pin of serial interface for simplified I2C.
(d) SI01
This is a serial data input pin of serial interface CSI01.
(e) SO01
This is a serial data output pin of serial interface CSI01.
(f) SDA01
This is a serial data I/O pins of serial interface for simplified I2C.
(g) INTP1, INTP2
These are the external interrupt request input pins for which the valid edge (rising edge, falling edge, or both
rising and falling edges) can be specified.
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Caution After reset release, the relationships between P40/TOOL0 and the operating mode are as follows.
For details, see 30. 5 Programming Method.
Table 2-2. Relationships Between P40/TOOL0 and Operation Mode After Reset Release
P40/TOOL0
EVDD0
0V
Operating mode
Normal operation mode
Flash memory programming mode
2.2.6 P50 to P57 (port 5)
P50 to P57 function as an I/O port. These pins also function as external interrupt request input, serial interface data I/O,
clock I/O, programming UART I/O, and timer I/O.
Use of an on-chip pull-up resistor can be specified by pull-up resistor option register 5 (PU5).
Input to the P50, and P53 to P55 pins can be specified through a normal input buffer or a TTL input buffer in 1-bit units,
using port input mode register 5 (PIM5).
Output from the P50 to P55 pins can be specified as normal CMOS output or N-ch open-drain output (EVDD0 tolerance)
in 1-bit units, using port output mode register 5 (POM5).
The following operation modes can be specified in 1-bit units.
(1) Port mode
P50 to P55 function as an I/O port. P50 to P55 can be set to input or output port in 1-bit units using port mode
register 5 (PM5).
(2) Control mode
P50 to P55 function as external interrupt request input, serial interface data I/O, clock I/O, programming UART I/O,
and timer I/O.
(a) SI00, SI31
These are the serial data input pins of serial interface CSI00 and CSI31.
(b) SO00, SO31
These are the serial data output pins of serial interface CSI00 and CSI31.
(c) SDA00, SDA31
These are the serial data I/O pins of serial interface for simplified I2C.
(d) SCK31
This is a serial clock I/O pin of serial interface CSI31.
(e) SCL31
This is a serial clock I/O pin of serial interface for simplified I2C.
(f) TxD0
This is a serial data output pin of serial data interface UART0.
(g) RxD0
This is a serial data input pin of serial data interface UART0.
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(h) TOOLTxD
This is the UART serial data output pin for the external device connection used during flash memory
programming.
(i)
TOOLRxD
This is the UART serial data input pin for the external device connection used during flash memory programming.
(j)
TRGIOA, TRGIOB
These are the timer I/O pins for timer RG.
2.2.7 P60 to P67 (port 6)
P60 to P67 function as an I/O port. These pins also function as serial interface data I/O, clock I/O, chip select input,
and timer I/O.
Only for P64 to P67, use of an on-chip pull-up resistor can be specified by pull-up resistor option register 6 (PU6).
Output of P60 to P63 is N-ch open-drain output (6 V tolerance).
The following operation modes can be specified in 1-bit units.
(1) Port mode
P60 to P67 function as an I/O port. P60 to P67 can be set to input port or output port in 1-bit units using port mode
register 6 (PM6).
(2) Control mode
P60 to P67 function as serial interface data I/O, clock I/O, chip select input, and timer I/O.
(a) SCLA0, SCLA1
These are the serial clock I/O pins of serial interface IICA0 and IICA1.
(b) SDAA0, SDAA1
These are the serial data I/O pins of serial interface IICA0 and IICA1.
(c) SSI00
This is a chip select input pin of serial interface CSI00.
(d) TI10 to TI13
These are the pins for inputting an external count clock/capture trigger to 16-bit timers 10 to 13.
(e) TO10 to TO13
These are the timer output pins of 16-bit timers 10 to 13.
2.2.8 P70 to P77 (port 7)
P70 to P77 function as an I/O port. These pins also function as key interrupt input, serial interface data I/O, clock I/O,
and external interrupt request input.
Use of an on-chip pull-up resistor can be specified by pull-up resistor option register 7 (PU7).
Output from the P71 and P74 pins can be specified as normal CMOS output or N-ch open-drain output (EVDD0
tolerance) in 1-bit units, using port output mode register 7 (POM7).
The following operation modes can be specified in 1-bit units.
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(1) Port mode
P70 to P77 function as an I/O port. P70 to P77 can be set to input or output port in 1-bit units using port mode
register 7 (PM7).
(2) Control mode
P70 to P77 function as key interrupt input, serial interface data I/O, clock I/O, and external interrupt request input.
(a) INTP8 to INTP11
These are the external interrupt request input pins for which the valid edge (rising edge, falling edge, or both
rising and falling edges) can be specified.
(b) KR0 to KR7
These are the key interrupt input pins.
(c) SI21
This is a serial data input pin of serial interface CSI21.
(d) SO21
This is a serial data output pin of serial interface CSI21.
(e) SCK21
This is a serial clock I/O pin of serial interface CSI21.
(f) SCL21
This is a serial clock I/O pin of serial interface for simplified I2C.
(g) SDA21
This is a serial data I/O pin of serial interface for simplified I2C.
2.2.9 P80 to P87 (port 8)
P80 to P87 function as an I/O port.
Use of an on-chip pull-up resistor can be specified by pull-up resistor option register 8 (PU8).
Input to the P80 and P81 pins can be specified through a normal input buffer or a TTL input buffer in 1-bit units, using
port input mode register 8 (PIM8).
Output from the P80 to P82 pins can be specified as normal CMOS output or N-ch open-drain output (EVDD0 tolerance)
in 1-bit units, using port output mode register 8 (POM8).
(1) Port mode
P80 to P87 function as an I/O port. P80 to P87 can be set to input or output port in 1-bit units using port mode
register 8 (PM8).
2.2.10 P100 to P102 (port 10)
P100 to P102 function as an I/O port. P100 to P102 function as an I/O port. These pins also function as A/D converter
analog input.
Use of an on-chip pull-up resistor can be specified by pull-up resistor option register 10 (PU10).
Input to the P100 pin can be specified as analog input or digital input in 1-bit units, using port mode control register 10
(PMC10).
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(1) Port mode
P100 to P102 function as an I/O port. P100 to P102 can be set to input or output port in 1-bit units using port mode
register 10 (PM10).
(2) Control mode
P100 functions as A/D converter analog input.
(a) ANI20
This is an analog input pin of A/D converter.
When using this pin as analog input pin, see 14.10 (5) Analog input (ANIn) pins.
2.2.11 P110, P111 (port 11)
P110 and P111 function as an I/O port.
Use of an on-chip pull-up resistor can be specified by pull-up resistor option register 11 (PU11).
(1) Port mode
P110 and P111 function as an I/O port. P110 and P111 can be set to input or output port in 1-bit units using port
mode register 11 (PM11).
2.2.12 P120 to P124 (port 12)
P120 functions as an I/O port and P121 to P124 function as an input port. These pins also function as A/D converter
analog input, connecting resonator for main system clock, connecting resonator for subsystem clock, external clock input
for main system clock, external clock input for subsystem clock, and comparator output.
For P120, use of an on-chip pull-up resistor can be specified by pull-up resistor option register 12 (PU12).
Input to the P120 pin can be specified as analog input or digital I/O in 1-bit units, using port mode control register 12
(PMC12).
The following operation modes can be specified in 1-bit units.
(1) Port mode
P120 functions as a 1-bit I/O port. P120 can be set to input or output port using port mode register 12 (PM12).
P121 to P124 function as a 4-bit input port.
(2) Control mode
P120 to P124 function as A/D converter analog input, connecting resonator for main system clock, connecting
resonator for subsystem clock, external clock input for main system clock, external clock input for subsystem clock,
and comparator output.
(a) ANI19
This is an analog input pin of A/D converter.
When using this pin as analog input pin, see 14.10 (5) Analog input (ANIn) pins.
(b) X1, X2
These are the pins for connecting a resonator for main system clock.
(c) EXCLK
This is an external clock input pin for main system clock.
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(d) XT1, XT2
These are the pins for connecting a resonator for subsystem clock.
(e) EXCLKS
This is an external clock input pin for subsystem clock.
(f) VCOUT0
This is a comparator output pin.
2.2.13 P130 and P137 (port 13)
P130 functions as a 1-bit output port. P137 functions as a 1-bit input port. P137 pin also functions as external interrupt
request input.
(1) Port mode
P130 functions as a 1-bit output port.
P137 functions as a 1-bit input port.
(2) Control mode
P137 functions as external interrupt request input.
(a) INTP0
This is an external interrupt request input pin for which the valid edge (rising edge, falling edge, or both rising and
falling edges) can be specified.
2.2.14 P140 to P147 (port 14)
P140 to P147 function as an I/O port. These pins also function as clock/buzzer output, external interrupt request input,
A/D converter analog input, serial interface data I/O, clock I/O, and comparator output.
Use of an on-chip pull-up resistor can be specified by pull-up resistor option register 14 (PU14).
Input to the P142 and P143 pins can be specified through a normal input buffer or a TTL input buffer in 1-bit units,
using port input mode register 14 (PIM14).
Output from the P142 to P144 pins can be specified as normal CMOS output or N-ch open-drain output (EVDD0
tolerance) in 1-bit units, using port output mode register 14 (POM14).
Input to the P147 pin can be specified as analog input or digital I/O in 1-bit units, using port mode control register 14
(PMC14).
The following operation modes can be specified in 1-bit units.
(1) Port mode
P140 to P147 function as an I/O port. P140 to P147 can be set to input or output port in 1-bit units using port mode
register 14 (PM14).
(2) Control mode
P140 to P147 function as clock/buzzer output, external interrupt request input, A/D converter analog input, serial
interface data I/O, clock I/O, and comparator output.
(a) ANI18
This is an analog input pin of A/D converter.
When using this pin as analog input pin, see 14.10 (5) Analog input (ANIn) pins.
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(b) INTP6, INTP7
These are the external interrupt request input pins for which the valid edge (rising edge, falling edge, or both
rising and falling edges) can be specified.
(c) PCLBUZ0, PCLBUZ1
These are the clock/buzzer output pins.
(d) SI30
This is a serial data input pin of serial interface CSI30.
(e) SO30
This is a serial data output pin of serial interface CSI30.
(f) SDA30
This is a serial data I/O pin of serial interface for simplified I2C.
(g) SCL30
This is a serial clock I/O pin of serial interface for simplified I2C.
(h) SCK30
This is a serial clock I/O pin of serial interface CSI30.
(i)
TxD3
This is a serial data output pin of serial data interface UART3.
(j)
RxD3
This is a serial data input pin of serial data interface UART3.
(k) VCOUT1
This is a comparator output pin.
2.2.15 P150 to P156 (port 15)
P150 to P156 function as an I/O port. These pins also function as A/D converter analog input.
The following operation modes can be specified in 1-bit units.
(1) Port mode
P150 to P156 function as an I/O port. P150 to P156 can be set to input or output port in 1-bit units using port mode
register 15 (PM15).
(2) Control mode
P150 to P156 function as A/D converter analog input.
(a) ANI8 to ANI14
These are the analog input pins (ANI8 to ANI14) of A/D converter.
When using these pins as analog input pins, see 14.10 (5) Analog input (ANIn) pins.
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2.2.16 VDD, EVDD0, EVDD1, VSS, EVSS0, EVSS1
(1) VDD, EVDD0, EVDD1
VDD is the positive power supply pin. When using the 64, 80, and 100 pin products, VDD is the positive power supply
pin for P20 to P27, P121 to P124, P137, P150 to P156 and pins other than ports.
EVDD0, EVDD1 is the positive power supply pin for ports other than P20 to P27, P121 to P124, P137, and P150 to P156.
(2) VSS, EVSS0, EVSS1
VSS is the ground potential pin. When using the 64, 80, and 100 pin products, VSS is the ground potential pin for P20
to P27, P121 to P124, P137, P150 to P156 and pins other than ports.
EVSS0, EVSS1 is the ground potential pin for ports other than P20 to P27, P121 to P124, P137, and P150 to P156.
<R>
Remark Use bypass capacitors (about 0.1 μF) as noise and latch up countermeasures with relatively thick
wires at the shortest distance to VDD to VSS, EVDD0 to EVSS0 and EVDD1 to EVSS1 lines.
2.2.17 RESET
This is the active-low system reset input pin.
When the external reset pin is not used, connect this pin directly or via a resistor to VDD.
When the external reset pin is used, design the circuit based on VDD.
2.2.18 REGC
This is the pin for connecting regulator output stabilization capacitance for internal operation. Connect this pin to VSS
via a capacitor (0.47 to 1 μF).
Also, use a capacitor with good characteristics, since it is used to stabilize internal voltage.
REGC
VSS
Caution Keep the wiring length as short as possible for the broken-line part in the above figure.
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2.3 Pin I/O Circuits and Recommended Connection of Unused Pins
Table 2-3 shows the types of pin I/O circuits and the recommended connections of unused pins.
<R>
Table 2-3. Connection of Unused Pins (100-pin products) (1/3)
Pin Name
I/O Circuit Type
P00/TI00/TRGCLKA/(TRJO0)
8-R
P01/TO00/TRGCLKB/TRJIO0
5-AN
P02/ANI17/SO10/TxD1
11-U
P03/ANI16/SI10/RxD1/
11-V
I/O
I/O
Recommended Connection of Unused Pins
Input:
Independently connect to EVDD0, EVDD1 or EVSS0, EVSS1
via a resistor.
Output: Leave open.
SDA10
P04/SCK10/SCL10
5-AN
P05
8-R
P06/(TRJIO0)
P10/SCK11/SCL11/TRDIOD1
5-AN
P11/SI11/SDA11/TRDIOC1
8-R
P12/SO11/TRDIOB1/IVREF1/
5-BB
(INTP5)
P13/TxD2/SO20/TRDIOA1/
IVCMP1
P14/RxD2/SI20/SDA20/
5-AN
TRDIOD0/(SCLA0)
P15/SCK20/SCL20/TRDIOB0
/(SDAA0)
P16/TI01/TO01/INTP5/
5-BC
TRDIOC0/IVREF0/(SI00)/
(RXD0)
P17/TI02/TO02/TRDIOA0/
TRDCLK0/IVCMP0/(SO00)/
(TXD0)
P20/ANI0/AVREFP
11-T
Independently connect to VDD or VSS via a resistor.
Output: Leave open.
P21/ANI1/AVREFM
P22/ANI2/ANO0
Input:
44
P23/ANI3/ANO1
P24/ANI4
11-G
P25/ANI5
P26/ANI6
P27/ANI7
P30/INTP3/RTC1HZ/
5-AN
SCK00/SCL00/TRJO0
P31/TI03/TO03/INTP4/
Input:
Independently connect to EVDD0, EVDD1 or EVSS0, EVSS1
via a resistor.
Output: Leave open.
(PCLBUZ0)/(TRJIO0)
Remarks 1. With products not provided with an EVDD0, EVDD1, EVSS0, or EVSS1 pin, replace EVDD0 and EVDD1 with VDD, or
replace EVSS0 and EVSS1 with VSS.
2. Functions in parentheses in the above figure can be assigned via settings in the peripheral I/O redirection
registers 0, 1 (PIOR0, 1).
3. In products without a comparator, the I/O circuit type of the P12 pin is 8-R and that of the P13, P16, and P17
pins is 5-AN.
4. In products without a D/A converter, the I/O circuit type of the P22 and P23 pins is 11-G.
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<R>
Table 2-3. Connection of Unused Pins (100-pin products) (2/3)
Pin Name
P40/TOOL0
I/O Circuit Type
8-R
I/O
I/O
Recommended Connection of Unused Pins
Input:
Independently connect to EVDD0 via a resistor, or leave
open.
Output: Leave open.
Input:
P41/(TRJIO0)
Independently connect to EVDD0, EVDD1 or EVSS0, EVSS1
via a resistor.
P42
P43/SCK01/SCL01
5-AN
Output: Leave open.
P44/SI01/SDA01
P45/SO01
8-R
P46/INTP1
P47/INTP2
P50/SI00/RxD0/TOOLRxD/
5-AN
SDA00/TRGIOA/(TRJO0)
P51/SO00/TxD0/
8-R
TOOLTxD/TRGIOB
P52/SO31
P53/SI31/SDA31
5-AN
P54/SCK31/SCL31
P55/(PCLBUZ1)/(SCK00)
8-R
P56/(INTP1)
P57/(INTP3)
P60/SCLA0
13-R
P61/SDAA0
P62/SSI00/SCLA1
P63/SDAA1
P64/TI10/TO10
8-R
P65/TI11/TO11
P66/TI12/TO12
P67/TI13/TO13
P70/KR0/SCK21/SCL21
8-R
P71/KR1/SI21/SDA21
P72/KR2/SO21
P73/KR3
P74/KR4/INTP8
P75/KR5/INTP9
P76/KR6/INTP10/(RXD2)
P77/KR7/INTP11/(TXD2)
Remarks 1. With products not provided with an EVDD0, EVDD1, EVSS0, or EVSS1 pin, replace EVDD0 and EVDD1 with VDD, or
replace EVSS0 and EVSS1 with VSS.
2. Functions in parentheses in the above figure can be assigned via settings in the peripheral I/O redirection
registers 0, 1 (PIOR0, 1).
3. For 64-pin products, I/O circuit type for P43, P53 and P54 pins is 8-R.
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Table 2-3. Connection of Unused Pins (100-pin products) (3/3)
<R>
Pin Name
P80/(SCK10)/(SCL10)
I/O Circuit Type
5-AN
I/O
Recommended Connection of Unused Pins
Input:
I/O
via a resistor.
P81/(SI10)/(RXD1)/(SDA10)
P82/(SO10)/(TXD1)
Independently connect to EVDD0, EVDD1 or EVSS0, EVSS1
Output: Leave open.
8-R
P83
P84/(INTP6)
P85/(INTP7)
P86/(INTP8)
P87/(INTP9)
P100/ANI20/(INTP10)
11-U
P101
8-R
P102
P110/(INTP11)
8-R
P111
P120/ANI19/VCOUT0
11-U
P121/X1
37-C
Input
Independently connect to VDD or VSS via a resistor.
P130
3-C
Output
Leave open.
P137/INTP0
2
Input
Independently connect to VDD or VSS via a resistor.
P140/PCLBUZ0/INTP6
8-R
I/O
Input:
P122/X2/EXCLK
P123/XT1
P124/XT2/EXCLKS
via a resistor.
P141/PCLBUZ1/INTP7
P142/SCK30/SCL30
Independently connect to EVDD0, EVDD1 or EVSS0, EVSS1
Output: Leave open.
5-AN
P143/SI30/RXD3/SDA30
P144/SO30/TXD3
8-R
P145
P146/(INTP4)
P147/ANI18/VCOUT1
11-U
P150/ANI8
11-G
Input:
Independently connect to VDD or VSS via a resistor.
Output: Leave open.
P151/ANI9
P152/ANI10
P153/ANI11
P154/ANI12
P155/ANI13
P156/ANI14
RESET
2
Input
−
REGC
−
Connect to VDD directly or via a resistor.
Connect to VSS via a capacitor (0.47 to 1 µF: target).
Remarks 1. With products not provided with an EVDD0, EVDD1, EVSS0, or EVSS1 pin, replace EVDD0 and EVDD1 with VDD, or
replace EVSS0 and EVSS1 with VSS.
2. Functions in parentheses in the above figure can be assigned via settings in the peripheral I/O redirection
registers 0, 1 (PIOR0, 1).
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Figure 2-1. Pin I/O Circuit List (1/3)
Type 2
Type 3-C
EVDD
P-ch
IN
data
OUT
N-ch
Schmitt-triggered input with hysteresis characteristics
EVSS
Type 5-AN
Type 5-BB
EVDD
EVDD
pull-up
enable
P-ch
pullup
enable
P-ch
EVDD
data
P-ch
output
disable
N-ch
EVDD
IN/OUT
data
P-ch
IN/OUT
EVSS
output
disable
CMOS
N-ch
EVSS
input
enable
TTL
input
characteristic
Comparator
Type 5-BC
Type 8-R
EVDD
pull-up
enable
EVDD
P-ch
EVDD
data
P-ch
IN/OUT
output
disable
pullup
enable
N-ch
EVSS
P-ch
EVDD
data
P-ch
CMOS
IN/OUT
TTL
input
characteristic
output
disable
N-ch
EVSS
input enable
Comparator
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Figure 2-1. Pin I/O Circuit List (2/3)
Type 11-G
Type 11-T
EVDD
data
P-ch
VDD
IN/OUT
data
P-ch
output
disable
N-ch
IN/OUT
EVSS
output
disable
N-ch
P-ch
Comparator
VSS
+
_
Comparator
N-ch
P-ch
Series resistor string voltage
+
_
VSS
N-ch
Series resistor string voltage
VSS
input enable
input enable
P-ch
AVREFP, AVREFM
N-ch
Type 11-U
Type 11-V
EVDD
EVDD
pull-up
enable
pull-up
enable
P-ch
EVDD
P-ch
data
P-ch
output
disable
N-ch
EVDD
data
IN/OUT
P-ch
IN/OUT
output
disable
N-ch
EVSS
EVSS
CMOS
input enable
P-ch
Comparator
TTL
input
characteristic
+
_
N-ch
P-ch
Comparator
+
_
Series resistor string voltage
N-ch
VSS
Series resistor string voltage
VSS
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Figure 2-1. Pin I/O Circuit List (3/3)
Type 13-R
Type 37-C
IN/OUT
data
output disable
input
enable
N-ch
X2,
XT2
amp
enable
input
enable
P-ch
N-ch
EVSS
X1,
XT1
Type 44
VDD
data
P-ch
IN/OUT
output
disable
N-ch
VSS
P-ch
Comparator
+
_
N-ch
VREF
(Threshold voltage)
VSS
input enable
P-ch
Analog output voltage
N-ch
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CHAPTER 3 CPU ARCHITECTURE
3.1 Memory Space
Products in the RL78/G14 can access a 1 MB memory space. Figures 3-1 to 3-8 show the memory maps.
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Figure 3-1. Memory Map (R5F104xA (x = A to C, E to G)
FFFFFH
03FFFH
Special function register (SFR)
256 bytes
FFF00H
FFEFFH
FFEE0H
FFEDFH
General-purpose register
32 bytes
RAM Note 1
2.5 KB
FF500H
FF4FFH
Program area
Reserved
F4000H
F3FFFH
Mirror
8 KB
F2000H
F1FFFH
F1000H
F0FFFH
01FFFH
Data flash memory
4 KB
010CEH
010CDH
Reserved
010C4H
010C3H
F0800H
F07FFH
Special function register (2nd SFR)
2 KB
Data memory
space
010C0H
010BFH
01080H
0107FH
F0000H
EFFFFH
On-chip debug security
ID setting area Note 2
10 bytes
Option byte area Note 2
4 bytes
Boot cluster 1
CALLT table area
64 bytes
Vector table area
128 bytes
01000H
00FFFH
Program area
Reserved
000CEH
000CDH
000C4H
000C3H
000C0H
000BFH
00080H
0007FH
Program
memory
space
04000H
03FFFH
00000H
On-chip debug security
ID setting area Note 2
10 bytes
Option byte area Note 2
4 bytes
Boot cluster 0 Note 3
CALLT table area
64 bytes
Vector table area
128 bytes
Code flash memory
16 KB
00000H
Notes 1. Instructions can be executed from the RAM area excluding the general-purpose register area.
2. When boot swap is not used: Set the option bytes to 000C0H to 000C3H, and the on-chip debug security
IDs to 000C4H to 000CDH.
When boot swap is used:
Set the option bytes to 000C0H to 000C3H and 010C0H to 010C3H, and the
on-chip debug security IDs to 000C4H to 000CDH and 010C4H to 010CDH.
3. Writing boot cluster 0 can be prohibited depending on the setting of security (see 30.6 Security Setting).
<R>
Caution
When executing instructions from the RAM area while RAM parity error resets are enabled (RPERDIS
= 0), be sure to initialize the used RAM area + 10 bytes.
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Figure 3-2. Memory Map (R5F104xC (x = A to C, E to G, J, L))
07FFFH
FFFFFH
Special function register (SFR)
256 bytes
FFF00H
FFEFFH
FFEE0H
FFEDFH
General-purpose register
32 bytes
RAM Note 1
4 KB
FEF00H
FEEFFH
Program area
Reserved
F8000H
F7FFFH
Mirror
24 KB
F2000H
F1FFFH
F1000H
F0FFFH
01FFFH
Data flash memory
4 KB
010CEH
010CDH
Reserved
010C4H
010C3H
F0800H
F07FFH
Special function register (2nd SFR)
2 KB
Data memory
space
F0000H
EFFFFH
010C0H
010BFH
01080H
0107FH
On-chip debug security
ID setting area Note 2
10 bytes
Option byte area Note 2
4 bytes
Boot cluster 1
CALLT table area
64 bytes
Vector table area
128 bytes
01000H
00FFFH
Reserved
Program area
000CEH
000CDH
000C4H
000C3H
000C0H
000BFH
00080H
0007FH
Program
memory
space
08000H
07FFFH
On-chip debug security
ID setting area Note 2
10 bytes
Option byte area Note 2
4 bytes
Boot cluster 0 Note 3
CALLT table area
64 bytes
Vector table area
128 bytes
Code flash memory
32KB
00000H
00000H
Notes 1. Instructions can be executed from the RAM area excluding the general-purpose register area.
2. When boot swap is not used: Set the option bytes to 000C0H to 000C3H, and the on-chip debug security
IDs to 000C4H to 000CDH.
When boot swap is used:
Set the option bytes to 000C0H to 000C3H and 010C0H to 010C3H, and the
on-chip debug security IDs to 000C4H to 000CDH and 010C4H to 010CDH.
3. Writing boot cluster 0 can be prohibited depending on the setting of security (see 30.6 Security Setting).
<R>
Caution
When executing instructions from the RAM area while RAM parity error resets are enabled (RPERDIS
= 0), be sure to initialize the used RAM area + 10 bytes.
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Figure 3-3. Memory Map (R5F104xD (x = A to C, E to G, J, L))
0BFFFH
FFFFFH
Special function register (SFR)
256 bytes
FFF00H
FFEFFH
FFEE0H
FFEDFH
General-purpose register
32 bytes
RAM Notes 1, 2
5.5 KB
Program area
FE900H
FE8FFH
Reserved
FC000H
FBFFFH
01FFFH
Mirror
40 KB
F2000H
F1FFFH
F1000H
F0FFFH
Data flash memory
4 KB
010CEH
010CDH
Reserved
010C4H
010C3H
F0800H
F07FFH
Special function register (2nd SFR)
2 KB
Data memory
space
F0000H
EFFFFH
010C0H
010BFH
01080H
0107FH
On-chip debug security
ID setting area Note 3
10 bytes
Option byte area Note 3
4 bytes
Boot cluster 1
CALLT table area
64 bytes
Vector table area
128 bytes
01000H
00FFFH
Reserved
Program area
000CEH
000CDH
000C4H
000C3H
000C0H
000BFH
00080H
0007FH
0C000H
0BFFFH
Program
memory
space
Option byte area Note 3
4 bytes
Boot cluster 0 Note 4
CALLT table area
64 bytes
Vector table area
128 bytes
Code flash memory
48 KB
00000H
00000H
<R>
On-chip debug security
ID setting area Note 3
10 bytes
Notes 1. Use of the area FE900H to FED09H that is used as a work area for the library is prohibited when using the
self-programming and data flash functions.
2. Instructions can be executed from the RAM area excluding the general-purpose register area.
3. When boot swap is not used: Set the option bytes to 000C0H to 000C3H, and the on-chip debug security
IDs to 000C4H to 000CDH.
When boot swap is used:
Set the option bytes to 000C0H to 000C3H and 010C0H to 010C3H, and the
on-chip debug security IDs to 000C4H to 000CDH and 010C4H to 010CDH.
4. Writing boot cluster 0 can be prohibited depending on the setting of security (see 30.6 Security Setting).
<R>
Caution
When executing instructions from the RAM area while RAM parity error resets are enabled (RPERDIS
= 0), be sure to initialize the used RAM area + 10 bytes.
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Figure 3-4. Memory Map (R5F104xE (x = A to C, E to G, J, L))
0FFFFH
FFFFFH
Special function register (SFR)
256 bytes
FFF00H
FFEFFH
FFEE0H
FFEDFH
General-purpose register
32 bytes
RAMNotes 1, 2
5.5 KB
Program area
FE900H
FE8FFH
Mirror
50.25 KB
F2000H
F1FFFH
01FFFH
Data flash memory
4 KB
F1000H
F0FFFH
Reserved
010C4H
010C3H
F0800H
F07FFH
Special function register (2nd SFR)
2 KB
Data memory
space
010CEH
010CDH
F0000H
EFFFFH
010C0H
010BFH
01080H
0107FH
On-chip debug security
ID setting areaNote 3
10 bytes
Option byte areaNote 3
4 bytes
Boot cluster 1
CALLT table area
64 bytes
Vector table area
128 bytes
01000H
00FFFH
Reserved
Program area
000CEH
000CDH
000C4H
000C3H
000C0H
000BFH
00080H
0007FH
10000H
0FFFFH
Program
memory
space
<R>
Option byte areaNote 3
4 bytes
Boot cluster 0Note 4
CALLT table area
64 bytes
Vector table area
128 bytes
Code flash memory
64 KB
00000H
On-chip debug security
ID setting areaNote 3
10 bytes
00000H
Notes 1. Use of the area FE900H to FED09H that is used as a work area for the library is prohibited when using the
self-programming and data flash functions.
2. Instructions can be executed from the RAM area excluding the general-purpose register area.
3. When boot swap is not used: Set the option bytes to 000C0H to 000C3H, and the on-chip debug security
IDs to 000C4H to 000CDH.
When boot swap is used:
Set the option bytes to 000C0H to 000C3H and 010C0H to 010C3H, and the
on-chip debug security IDs to 000C4H to 000CDH and 010C4H to 010CDH.
4. Writing boot cluster 0 can be prohibited depending on the setting of security (see 30.6 Security Setting).
<R>
Caution
When executing instructions from the RAM area while RAM parity error resets are enabled (RPERDIS
= 0), be sure to initialize the used RAM area + 10 bytes.
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Figure 3-5. Memory Map (R5F104xF (x = A to C, E to G, J, L, M, P))
17FFFH
FFFFFH
Special function register (SFR)
256 bytes
FFF00H
FFEFFH
FFEE0H
FFEDFH
General-purpose register
32 bytes
RAMNote 1
12 KB
Program area
FCF00H
FCEFFH
Mirror
39.75 KB
F3000H
F2FFFH
01FFFH
Data flash memory
8 KB
F1000H
F0FFFH
Reserved
010C4H
010C3H
F0800H
F07FFH
Special function register (2nd SFR)
2 KB
Data memory
space
010CEH
010CDH
F0000H
EFFFFH
010C0H
010BFH
01080H
0107FH
On-chip debug security
ID setting areaNote 2
10 bytes
Option byte areaNote 2
4 bytes
Boot cluster 1
CALLT table area
64 bytes
Vector table area
128 bytes
01000H
00FFFH
Reserved
Program area
000CEH
000CDH
000C4H
000C3H
000C0H
000BFH
00080H
0007FH
18000H
17FFFH
Program
memory
space
Option byte areaNote 2
4 bytes
Boot cluster 0Note 3
CALLT table area
64 bytes
Vector table area
128 bytes
Code flash memory
96 KB
00000H
On-chip debug security
ID setting areaNote 2
10 bytes
00000H
Notes 1. Instructions can be executed from the RAM area excluding the general-purpose register area.
2. When boot swap is not used: Set the option bytes to 000C0H to 000C3H, and the on-chip debug security
IDs to 000C4H to 000CDH.
When boot swap is used:
Set the option bytes to 000C0H to 000C3H and 010C0H to 010C3H, and the
on-chip debug security IDs to 000C4H to 000CDH and 010C4H to 010CDH.
3. Writing boot cluster 0 can be prohibited depending on the setting of security (see 30.6 Security Setting).
<R>
Caution
When executing instructions from the RAM area while RAM parity error resets are enabled (RPERDIS
= 0), be sure to initialize the used RAM area + 10 bytes.
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Figure 3-6. Memory Map (R5F104xG (x = A to C, E to G, J, L, M, P))
1FFFFH
FFFFFH
Special function register (SFR)
256 bytes
FFF00H
FFEFFH
FFEE0H
FFEDFH
General-purpose register
32 bytes
RAMNote 1
16 KB
FBF00H
FBEFFH
F3000H
F2FFFH
F1000H
F0FFFH
Program area
Mirror
35.75 KB
01FFFH
Data flash memory
8 KB
Reserved
010C4H
010C3H
F0800H
F07FFH
Special function register (2nd SFR)
2 KB
F0000H
EFFFFH
Data memory
space
010CEH
010CDH
010C0H
010BFH
01080H
0107FH
On-chip debug security
ID setting areaNote 2
10 bytes
Option byte areaNote 2
4 bytes
Boot cluster 1
CALLT table area
64 bytes
Vector table area
128 bytes
01000H
00FFFH
Reserved
Program area
000CEH
000CDH
000C4H
000C3H
000C0H
000BFH
20000H
1FFFFH
Program
memory
space
00080H
0007FH
Option byte areaNote 2
4 bytes
Boot cluster 0Note 3
CALLT table area
64 bytes
Vector table area
128 bytes
Code flash memory
128 KB
00000H
On-chip debug security
ID setting areaNote 2
10 bytes
00000H
Notes 1. Instructions can be executed from the RAM area excluding the general-purpose register area.
2. When boot swap is not used: Set the option bytes to 000C0H to 000C3H, and the on-chip debug security
IDs to 000C4H to 000CDH.
When boot swap is used:
Set the option bytes to 000C0H to 000C3H and 010C0H to 010C3H, and the
on-chip debug security IDs to 000C4H to 000CDH and 010C4H to 010CDH.
3. Writing boot cluster 0 can be prohibited depending on the setting of security (see 30.6 Security Setting).
<R>
Caution
When executing instructions from the RAM area while RAM parity error resets are enabled (RPERDIS
= 0), be sure to initialize the used RAM area + 10 bytes.
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Figure 3-7. Memory Map (R5F104xH (x = E to G, J, L, M, P))
2FFFFH
FFFFFH
Special function register (SFR)
256 bytes
FFF00H
FFEFFH
FFEE0H
FFEDFH
General-purpose register
32 bytes
RAMNote 1
20 KB
FAF00H
FAEFFH
Program area
Mirror
31.75 KB
F3000H
F2FFFH
01FFFH
Data flash memory
8 KB
F1000H
F0FFFH
Reserved
010C4H
010C3H
F0800H
F07FFH
Special function register (2nd SFR)
2 KB
Data memory
space
010CEH
010CDH
F0000H
EFFFFH
010C0H
010BFH
01080H
0107FH
On-chip debug security
ID setting areaNote 2
10 bytes
Option byte areaNote 2
4 bytes
Boot cluster 1
CALLT table area
64 bytes
Vector table area
128 bytes
01000H
00FFFH
Reserved
Program area
000CEH
000CDH
000C4H
000C3H
000C0H
000BFH
30000H
2FFFFH
Program
memory
space
00080H
0007FH
Option byte areaNote 2
4 bytes
Boot cluster 0Note 3
CALLT table area
64 bytes
Vector table area
128 bytes
Code flash memory
192 KB
00000H
On-chip debug security
ID setting areaNote 2
10 bytes
00000H
Notes 1. Instructions can be executed from the RAM area excluding the general-purpose register area.
2. When boot swap is not used: Set the option bytes to 000C0H to 000C3H, and the on-chip debug security
IDs to 000C4H to 000CDH.
When boot swap is used:
Set the option bytes to 000C0H to 000C3H and 010C0H to 010C3H, and the
on-chip debug security IDs to 000C4H to 000CDH and 010C4H to 010CDH.
3. Writing boot cluster 0 can be prohibited depending on the setting of security (see 30.6 Security Setting).
<R>
Caution
When executing instructions from the RAM area while RAM parity error resets are enabled (RPERDIS
= 0), be sure to initialize the used RAM area + 10 bytes.
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Figure 3-8. Memory Map (R5F104xJ (x = F, G, J, L, M, P))
3FFFFH
FFFFFH
Special function register (SFR)
256 bytes
FFF00H
FFEFFH
FFEE0H
FFEDFH
General-purpose register
32 bytes
RAMNotes 1, 2, 3
24 KB
F9F00H
F9EFFH
Mirror
27.75 KB
F3000H
F2FFFH
01FFFH
Data flash memory
8 KB
F1000H
F0FFFH
Reserved
010CEH
010CDH
010C4H
010C3H
F0800H
F07FFH
Special function register (2nd SFR)
2 KB
Data memory
space
Program area
F0000H
EFFFFH
010C0H
010BFH
01080H
0107FH
On-chip debug security
ID setting areaNote 4
10 bytes
Option byte areaNote 4
4 bytes
Boot cluster 1
CALLT table area
64 bytes
Vector table area
128 bytes
01000H
00FFFH
Reserved
Program area
000CEH
000CDH
000C4H
000C3H
000C0H
000BFH
40000H
3FFFFH
Program
memory
space
00080H
0007FH
<R>
Option byte areaNote 4
4 bytes
Boot cluster 0Note 5
CALLT table area
64 bytes
Vector table area
128 bytes
Code flash memory
256 KB
00000H
On-chip debug security
ID setting areaNote 4
10 bytes
00000H
Notes 1. Use of the area F9F00H to FA309H that is used as a work area for the library is prohibited when using the
self-programming and data flash functions.
<R>
2. Use of the area FA300H to FA6FFH is prohibited when using the on-chip debugging trace function.
3. Instructions can be executed from the RAM area excluding the general-purpose register area.
4. When boot swap is not used: Set the option bytes to 000C0H to 000C3H, and the on-chip debug security
IDs to 000C4H to 000CDH.
When boot swap is used:
Set the option bytes to 000C0H to 000C3H and 010C0H to 010C3H, and the
on-chip debug security IDs to 000C4H to 000CDH and 010C4H to 010CDH.
5. Writing boot cluster 0 can be prohibited depending on the setting of security (see 30.6 Security Setting).
<R>
Caution
When executing instructions from the RAM area while RAM parity error resets are enabled (RPERDIS
= 0), be sure to initialize the used RAM area + 10 bytes.
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Remark
CHAPTER 3 CPU ARCHITECTURE
The flash memory is divided into blocks (one block = 1 KB). For the address values and block numbers, see
Table 3-1 Correspondence Between Address Values and Block Numbers in Flash Memory.
0FFFFH
Block 3FH
0FC00H
0FBFFH
007FFH
00400H
003FFH
Block 01H
Block 00H
1 KB
00000H
(R5F104xE (x = A to C, E to G, J, L))
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Correspondence between the address values and block numbers in the flash memory are shown below.
Table 3-1. Correspondence Between Address Values and Block Numbers in Flash Memory (1/2)
Address Value
Block
Address Value
00000H to 003FFH
00H
Block
Address Value
08000H to 083FFH
20H
Block
Address Value
10000H to 103FFH
40H
Block
Number
Number
Number
Number
18000H to 183FFH
60H
00400H to 007FFH
01H
08400H to 087FFH
21H
10400H to 107FFH
41H
18400H to 187FFH
61H
00800H to 00BFFH
02H
08800H to 08BFFH
22H
10800H to 10BFFH
42H
18800H to 18BFFH
62H
00C00H to 00FFFH
03H
08C00H to 08FFFH
23H
10C00H to 10FFFH
43H
18C00H to 18FFFH
63H
01000H to 013FFH
04H
09000H to 093FFH
24H
11000H to 113FFH
44H
19000H to 193FFH
64H
01400H to 017FFH
05H
09400H to 097FFH
25H
11400H to 117FFH
45H
19400H to 197FFH
65H
01800H to 01BFFH
06H
09800H to 09BFFH
26H
11800H to 11BFFH
46H
19800H to 19BFFH
66H
01C00H to 01FFFH
07H
09C00H to 09FFFH
27H
11C00H to 11FFFH
47H
19C00H to 19FFFH
67H
02000H to 023FFH
08H
0A000H to 0A3FFH
28H
12000H to 123FFH
48H
1A000H to 1A3FFH
68H
02400H to 027FFH
09H
0A400H to 0A7FFH
29H
12400H to 127FFH
49H
1A400H to 1A7FFH
69H
02800H to 02BFFH
0AH
0A800H to 0ABFFH
2AH
12800H to 12BFFH
4AH
1A800H to 1ABFFH
6AH
02C00H to 02FFFH
0BH
0AC00H to 0AFFFH
2BH
12C00H to 12FFFH
4BH
1AC00H to 1AFFFH
6BH
03000H to 033FFH
0CH
0B000H to 0B3FFH
2CH
13000H to 133FFH
4CH
1B000H to 1B3FFH
6CH
03400H to 037FFH
0DH
0B400H to 0B7FFH
2DH
13400H to 137FFH
4DH
1B400H to 1B7FFH
6DH
03800H to 03BFFH
0EH
0B800H to 0BBFFH
2EH
13800H to 13BFFH
4EH
1B800H to 1BBFFH
6EH
03C00H to 03FFFH
0FH
0BC00H to 0BFFFH
2FH
13C00H to 13FFFH
4FH
1BC00H to 1BFFFH
6FH
04000H to 043FFH
10H
0C000H to 0C3FFH
30H
14000H to 143FFH
50H
1C000H to 1C3FFH
70H
04400H to 047FFH
11H
0C400H to 0C7FFH
31H
14400H to 147FFH
51H
1C400H to 1C7FFH
71H
04800H to 04BFFH
12H
0C800H to 0CBFFH
32H
14800H to 14BFFH
52H
1C800H to 1CBFFH
72H
04C00H to 04FFFH
13H
0CC00H to 0CFFFH
33H
14C00H to 14FFFH
53H
1CC00H to 1CFFFH
73H
05000H to 053FFH
14H
0D000H to 0D3FFH
34H
15000H to 153FFH
54H
1D000H to 1D3FFH
74H
05400H to 057FFH
15H
0D400H to 0D7FFH
35H
15400H to 157FFH
55H
1D400H to 1D7FFH
75H
05800H to 05BFFH
16H
0D800H to 0DBFFH
36H
15800H to 15BFFH
56H
1D800H to 1DBFFH
76H
05C00H to 05FFFH
17H
0DC00H to 0DFFFH
37H
15C00H to 15FFFH
57H
1DC00H to 1DFFFH
77H
06000H to 063FFH
18H
0E000H to 0E3FFH
38H
16000H to 163FFH
58H
1E000H to 1E3FFH
78H
06400H to 067FFH
19H
0E400H to 0E7FFH
39H
16400H to 167FFH
59H
1E400H to 1E7FFH
79H
06800H to 06BFFH
1AH
0E800H to 0EBFFH
3AH
16800H to 16BFFH
5AH
1E800H to 1EBFFH
7AH
06C00H to 06FFFH
1BH
0EC00H to 0EFFFH
3BH
16C00H to 16FFFH
5BH
1EC00H to 1EFFFH
7BH
07000H to 073FFH
1CH
0F000H to 0F3FFH
3CH
17000H to 173FFH
5CH
1F000H to 1F3FFH
7CH
07400H to 077FFH
1DH
0F400H to 0F7FFH
3DH
17400H to 177FFH
5DH
1F400H to 1F7FFH
7DH
07800H to 07BFFH
1EH
0F800H to 0FBFFH
3EH
17800H to 17BFFH
5EH
1F800H to 1FBFFH
7EH
07C00H to 07FFFH
1FH
0FC00H to 0FFFFH
3FH
17C00H to 17FFFH
5FH
1FC00H to 1FFFFH
7FH
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Table 3-1. Correspondence Between Address Values and Block Numbers in Flash Memory (2/2)
Address Value
Block
Address Value
Number
20000H to 203FFH
80H
Block
Address Value
Number
28000H to 283FFH
A0H
Block
Address Value
Number
30000H to 303FFH
C0H
Block
Number
38000H to 383FFH
E0H
20400H to 207FFH
81H
28400H to 287FFH
A1H
30400H to 307FFH
C1H
38400H to 387FFH
E1H
20800H to 20BFFH
82H
28800H to 28BFFH
A2H
30800H to 30BFFH
C2H
38800H to 38BFFH
E2H
20C00H to 20FFFH
83H
28C00H to 28FFFH
A3H
30C00H to 30FFFH
C3H
38C00H to 38FFFH
E3H
21000H to 213FFH
84H
29000H to 293FFH
A4H
31000H to 313FFH
C4H
39000H to 393FFH
E4H
21400H to 217FFH
85H
29400H to 297FFH
A5H
31400H to 317FFH
C5H
39400H to 397FFH
E5H
21800H to 21BFFH
86H
29800H to 29BFFH
A6H
31800H to 31BFFH
C6H
39800H to 39BFFH
E6H
21C00H to 21FFFH
87H
29C00H to 29FFFH
A7H
31C00H to 31FFFH
C7H
39C00H to 39FFFH
E7H
22000H to 223FFH
88H
2A000H to 2A3FFH
A8H
32000H to 323FFH
C8H
3A000H to 3A3FFH
E8H
22400H to 227FFH
89H
2A400H to 2A7FFH
A9H
32400H to 327FFH
C9H
3A400H to 3A7FFH
E9H
22800H to 22BFFH
8AH
2A800H to 2ABFFH
AAH
32800H to 32BFFH
CAH
3A800H to 3ABFFH
EAH
22C00H to 22FFFH
8BH
2AC00H to 2AFFFH
ABH
32C00H to 32FFFH
CBH
3AC00H to 3AFFFH
EBH
23000H to 233FFH
8CH
2B000H to 2B3FFH
ACH
33000H to 333FFH
CCH
3B000H to 3B3FFH
ECH
23400H to 237FFH
8DH
2B400H to 2B7FFH
ADH
33400H to 337FFH
CDH
3B400H to 3B7FFH
EDH
23800H to 23BFFH
8EH
2B800H to 2BBFFH
AEH
33800H to 33BFFH
CEH
3B800H to 3BBFFH
EEH
23C00H to 23FFFH
8FH
2BC00H to 2BFFFH
AFH
33C00H to 33FFFH
CFH
3BC00H to 3BFFFH
EFH
24000H to 243FFH
90H
2C000H to 2C3FFH
B0H
34000H to 343FFH
D0H
3C000H to 3C3FFH
F0H
24400H to 247FFH
91H
2C400H to 2C7FFH
B1H
34400H to 347FFH
D1H
3C400H to 3C7FFH
F1H
24800H to 24BFFH
92H
2C800H to 2CBFFH
B2H
34800H to 34BFFH
D2H
3C800H to 3CBFFH
F2H
24C00H to 24FFFH
93H
2CC00H to 2CFFFH
B3H
34C00H to 34FFFH
D3H
3CC00H to 3CFFFH
F3H
25000H to 253FFH
94H
2D000H to 2D3FFH
B4H
35000H to 353FFH
D4H
3D000H to 3D3FFH
F4H
25400H to 257FFH
95H
2D400H to 2D7FFH
B5H
35400H to 357FFH
D5H
3D400H to 3D7FFH
F5H
25800H to 25BFFH
96H
2D800H to 2DBFFH
B6H
35800H to 35BFFH
D6H
3D800H to 3DBFFH
F6H
25C00H to 25FFFH
97H
2DC00H to 2DFFFH
B7H
35C00H to 35FFFH
D7H
3DC00H to 3DFFFH
F7H
26000H to 263FFH
98H
2E000H to 2E3FFH
B8H
36000H to 363FFH
D8H
3E000H to 3E3FFH
F8H
26400H to 267FFH
99H
2E400H to 2E7FFH
B9H
36400H to 367FFH
D9H
3E400H to 3E7FFH
F9H
26800H to 26BFFH
9AH
2E800H to 2EBFFH
BAH
36800H to 36BFFH
DAH
3E800H to 3EBFFH
FAH
26C00H to 26FFFH
9BH
2EC00H to 2EFFFH
BBH
36C00H to 36FFFH
DBH
3EC00H to 3EFFFH
FBH
27000H to 273FFH
9CH
2F000H to 2F3FFH
BCH
37000H to 373FFH
DCH
3F000H to 3F3FFH
FCH
27400H to 277FFH
9DH
2F400H to 2F7FFH
BDH
37400H to 377FFH
DDH
3F400H to 3F7FFH
FDH
27800H to 27BFFH
9EH
2F800H to 2FBFFH
BEH
37800H to 37BFFH
DEH
3F800H to 3FBFFH
FEH
27C00H to 27FFFH
9FH
2FC00H to 2FFFFH
BFH
37C00H to 37FFFH
DFH
3FC00H to 3FFFFH
FFH
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3.1.1 Internal program memory space
The internal program memory space stores the program and table data.
The RL78/G14 products incorporate internal ROM (flash memory), as shown below.
Table 3-2. Internal ROM Capacity
Part Number
Internal ROM
Structure
R5F104xA (x = A to C, E to G)
Flash memory
Capacity
16384 × 8 bits (00000H to 03FFFH)
R5F104xC (x = A to C, E to G, J, L)
32768 × 8 bits (00000H to 07FFFH)
R5F104xD (x = A to C, E to G, J, L)
49152 × 8 bits (00000H to 0BFFFH)
R5F104xE (x = A to C, E to G, J, L)
65536 × 8 bits (00000H to 0FFFFH)
R5F104xF (x = A to C, E to G, J, L, M, P)
98304 × 8 bits (00000H to 17FFFH)
R5F104xG (x = A to C, E to G, J, L, M, P)
131072 × 8 bits (00000H to 1FFFFH)
R5F104xH (x = E to G, J, L, M, P)
196608 × 8 bits (00000H to 2FFFFH)
R5F104xJ (x = F, G, J, L, M, P)
262144 × 8 bits (00000H to 3FFFFH)
The internal program memory space is divided into the following areas.
(1) Vector table area
The 128-byte area 00000H to 0007FH is reserved as a vector table area. The program start addresses for branch
upon reset or generation of each interrupt request are stored in the vector table area. Furthermore, the interrupt jump
address is a 64 K address of 00000H to 0FFFFH, because the vector code is assumed to be 2 bytes.
Of the 16-bit address, the lower 8 bits are stored at even addresses and the higher 8 bits are stored at odd addresses.
To use the boot swap function, set a vector table also at 01000H to 0107FH.
Table 3-3 lists the vector table. “√” indicates an interrupt source which is supported. “−” indicates an interrupt source
which is not supported.
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Table 3-3. Vector Table (1/2)
64-pin
52-pin
48-pin
44-pin
40-pin
36-pin
32-pin
30-pin
RESET, POR, LVD, WDT,
80-pin
0000H
Interrupt Source
100-pin
Vector Table Address
√
√
√
√
√
√
√
√
√
√
TRAP, IAW, RAMTOP
0004H
INTWDTI
√
√
√
√
√
√
√
√
√
√
0006H
INTLVI
√
√
√
√
√
√
√
√
√
√
0008H
INTP0
√
√
√
√
√
√
√
√
√
√
000AH
INTP1
√
√
√
√
√
√
√
√
√
√
000CH
INTP2
√
√
√
√
√
√
√
√
√
√
000EH
INTP3
√
√
√
√
√
√
√
√
√
√
0010H
INTP4
√
√
√
√
√
√
√
√
√
√
0012H
INTP5
√
√
√
√
√
√
√
√
√
√
0014H
INTST2/INTCSI20/INTIIC20
√
√
√
√
√
√
√
√
√
√
0016H
INTSR2/INTCSI21/INTIIC21
√
√
√
√
√
√
√
√
0018H
INTSRE2
√
√
√
√
√
√
√
√
√
√
INTTM11H
√
√
−
−
−
−
−
−
−
−
001EH
INTST0/INTCSI00/INTIIC00
√
√
√
√
√
√
√
√
√
√
0020H
INTSR0/INTCSI01/INTIIC01
√
√
√
√
√
0022H
INTSRE0
√
√
√
√
√
√
√
√
√
√
INTTM01H
√
√
√
√
√
√
√
√
√
√
0024H
INTST1/INTCSI10/INTIIC10
√
√
√
0026H
INTSR1/INTCSI11/INTIIC11
√
√
√
√
√
√
√
√
√
√
0028H
INTSRE1
√
√
√
√
√
√
√
√
√
√
INTTM03H
√
√
√
√
√
√
√
√
√
√
002AH
INTIICA0
√
√
√
√
√
√
√
√
√
√
002CH
INTTM00
√
√
√
√
√
√
√
√
√
√
002EH
INTTM01
√
√
√
√
√
√
√
√
√
√
0030H
INTTM02
√
√
√
√
√
√
√
√
√
√
0032H
INTTM03
√
√
√
√
√
√
√
√
√
√
0034H
INTAD
√
√
√
√
√
√
√
√
√
√
0036H
INTRTC
√
√
√
√
√
√
√
√
√
√
0038H
INTIT
√
√
√
√
√
√
√
√
√
√
003AH
INTKR
√
√
√
√
√
√
√
−
−
−
003CH
INTST3/INTCSI30/INTIIC30
√
√
−
−
−
−
−
−
−
−
003EH
INTSR3/INTCSI31/INTIIC31
√
√
−
−
−
−
−
−
−
−
0040H
INTTRJ0
√
√
√
√
√
√
√
√
√
√
0042H
INTTM10
√
√
−
−
−
−
−
−
−
−
0044H
INTTM11
√
√
−
−
−
−
−
−
−
−
0046H
INTTM12
√
√
−
−
−
−
−
−
−
−
0048H
INTTM13
√
√
−
−
−
−
−
−
−
−
Notes 1.
Note 1 Note 1
Note 2 Note 2 Note 2 Note 2 Note 2
Note 3 Note 3 Note 3 Note 3 Note 3 Note 3 Note 3
Only INTSR2 is supported.
2.
Only INTSR0 is supported.
3.
Only INTST1 is supported.
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Table 3-3. Vector Table (2/2)
100-pin
80-pin
64-pin
52-pin
48-pin
44-pin
40-pin
36-pin
32-pin
30-pin
004AH
INTP6
√
√
√
√
√
−
−
−
−
−
004CH
INTP7
√
√
√
−
−
−
−
−
−
−
004EH
INTP8
√
√
√
√
√
−
−
−
−
−
0050H
INTP9
√
√
√
√
√
−
−
−
−
−
0052H
INTP10
√
√
√
√
−
−
−
−
−
−
INTCMP0
√
√
INTP11
√
√
INTCMP1
√
√
0056H
INTTRD0
√
√
√
√
√
√
√
√
√
√
0058H
INTTRD1
√
√
√
√
√
√
√
√
√
√
005AH
INTTRG
√
√
√
√
√
√
√
√
√
√
005CH
INTSRE3
√
√
−
−
−
−
−
−
−
−
INTTM13H
√
√
−
−
−
−
−
−
−
−
0060H
INTIICA1
√
√
−
−
−
−
−
−
−
−
0062H
INTFL
√
√
√
√
√
√
√
√
√
√
007EH
BRK
√
√
√
√
√
√
√
√
√
√
Vector Table Address
0054H
Interrupt Source
Note Note Note Note Note Note Note Note
√
√
−
−
−
−
−
−
Note Note Note Note Note Note Note Note
Note Supported only in the products with 96 KB or more code flash memory.
(2) CALLT instruction table area
The 64-byte area 00080H to 000BFH can store the subroutine entry address of a 2-byte call instruction (CALLT). Set
the subroutine entry address to a value in a range of 00000H to 0FFFFH (because an address code is 2 bytes).
To use the boot swap function, set a CALLT instruction table also at 01080H to 010BFH.
(3) Option byte area
A 4-byte area of 000C0H to 000C3H can be used as an option byte area. Set the option byte at 010C0H to 010C3H
when the boot swap is used. For details, see CHAPTER 29 OPTION BYTE.
(4) On-chip debug security ID setting area
A 10-byte area of 000C4H to 000CDH and 010C4H to 010CDH can be used as an on-chip debug security ID setting
area. Set the on-chip debug security ID of 10 bytes at 000C4H to 000CDH when the boot swap is not used and at
000C4H to 000CDH and at 010C4H to 010CDH when the boot swap is used. For details, see CHAPTER 31 ONCHIP DEBUG FUNCTION.
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3.1.2 Mirror area
The RL78/G14 mirrors the code flash area of 00000H to 0FFFFH, to F0000H to FFFFFH. The products with 96 KB or
more flash memory mirror the code flash area of 00000H to 0FFFFH or 10000H to 1FFFFH, to F0000H to FFFFFH (the
code flash area to be mirrored is set by the processor mode control register (PMC)).
By reading data from F0000H to FFFFFH, an instruction that does not have the ES register as an operand can be used,
and thus the contents of the code flash can be read with the shorter code. However, the code flash area is not mirrored to
the SFR, extended SFR, RAM, data flash memory, and use prohibited areas.
See 3.1 Memory Space for the mirror area of each product.
The mirror area can only be read and no instruction can be fetched from this area.
The following show examples.
Example R5F104xE (x = A to C, E to G, J, L) (Flash memory: 64 KB, RAM: 5.5 KB)
FFFFFH
Special-function register (SFR)
256 bytes
FFF00H
FFEFFH
FFEE0H
FFEDFH
General-purpose register
32 bytes
RAM
5.5 KB
FE900H
FE8FFH
Mirror
(same data as 02000H to 0E8FFH)
F2000H
F1FFFH
Data flash memory
F1000H
F0FFFH
Reserved
F0800H
F07FFH
Special-function register (2nd SFR)
2 KB
F0000H
EFFFFH
Mirror
For example, 0E789H is mirrored to
Reserved
FE789H. Data can therefore be read
by MOV A, !E789H, instead of MOV
ES, #00H and MOV A, ES:!E789H.
10000H
0FFFFH
Code flash memory
0E900H
0E8FFH
Code flash memory
02000H
01FFFH
Code flash memory
00000H
The PMC register is described below.
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• Processor mode control register (PMC)
This register sets the flash memory space for mirroring to area from F0000H to FFFFFH.
The PMC register can be set by a 1-bit or 8-bit memory manipulation instruction.
Reset signal generation sets this register to 00H.
Figure 3-9. Format of Configuration of Processor Mode Control Register (PMC)
Address: FFFFEH After reset: 00H R/W
Symbol
7
6
5
4
3
2
1
<0>
PMC
0
0
0
0
0
0
0
MAA
MAA
Selection of flash memory space for mirroring to area from F0000H to FFFFFH
0
00000H to 0FFFFH is mirrored to F0000H to FFFFFH
1
10000H to 1FFFFH is mirrored to F0000H to FFFFFH Note
Note This setting is prohibited in products with 64 KB or less flash memory
Cautions 1. In products with 64 KB or less flash memory, be sure to clear bit 0 (MAA) of this register to 0
(default value).
2. Set the PMC register only once during the initial settings prior to operating the data transfer
controller (DTC). Rewriting the PMC register other than during the initial settings is prohibited.
3. After setting the PMC register, wait for at least one instruction and access the mirror area.
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3.1.3 Internal data memory space
The RL78/G14 products incorporate the following RAMs.
Table 3-4. Internal RAM Capacity
Part Number
Internal RAM
R5F104xA (x = A to C, E to G)
2560 × 8 bits (FF500H to FFEFFH)
R5F104xC (x = A to C, E to G, J, L)
4096 × 8 bits (FEF00H to FFEFFH)
R5F104xD (x = A to C, E to G, J, L)
5632 × 8 bits (FE900H to FFEFFH)
R5F104xE (x = A to C, E to G, J, L)
R5F104xF (x = A to C, E to G, J, L, M, P)
12288 × 8 bits (FCF00H to FFEFFH)
R5F104xG (x = A to C, E to G, J, L, M, P)
16384 × 8 bits (FBF00H to FFEFFH)
R5F104xH (x = E to G, J, L, M, P)
20480 × 8 bits (FAF00H to FFEFFH)
R5F104xJ (x = F, G, J, L, M, P)
24576 × 8 bits (F9F00H to FFEFFH)
The internal RAM can be used as a data area and a program area where instructions are written and executed. Four
general-purpose register banks consisting of eight 8-bit registers per bank are assigned to the 32-byte area of FFEE0H to
FFEFFH of the internal RAM area. However, instructions cannot be executed by using the general-purpose registers.
The internal RAM is used as a stack memory.
Cautions 1. It is prohibited to use the general-purpose register (FFEE0H to FFEFFH) space for fetching
instructions or as a stack area.
<R>
2. The internal RAM in the following products cannot be used as stack memory when using the selfprogramming and data flash functions.
R5F104xD (x = A to C, E to G, J, L):
<R>
FE900H to FED09H
R5F104xE (x = A to C, E to G, J, L):
FE900H to FED09H
R5F104xJ (x = F, G, J, L, M, P):
F9F00H to FA309H
3. The internal RAM area in the following products cannot be used as stack memory when using the
on-chip debugging trace function.
R5F104xJ (x = A to C, E to G, J, L):
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3.1.4 Special function register (SFR) area
On-chip peripheral hardware special function registers (SFRs) are allocated in the area FFF00H to FFFFFH (see Table
3-5 in 3.2.4 Special function registers (SFRs)).
Caution Do not access addresses to which SFRs are not assigned.
3.1.5 Extended special function register (2nd SFR: 2nd Special Function Register) area
On-chip peripheral hardware special function registers (2nd SFRs) are allocated in the area F0000H to F07FFH (see
Table 3-6 in 3.2.5 Extended Special function registers (2nd SFRs: 2nd Special Function Registers)).
SFRs other than those in the SFR area (FFF00H to FFFFFH) are allocated to this area. An instruction that accesses
the extended SFR area, however, is 1 byte longer than an instruction that accesses the SFR area.
Caution Do not access addresses to which extended SFRs are not assigned.
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3.1.6 Data memory addressing
Addressing refers to the method of specifying the address of the instruction to be executed next or the address of the
register or memory relevant to the execution of instructions.
Several addressing modes are provided for addressing the memory relevant to the execution of instructions for the
RL78/G14, based on operability and other considerations.
For areas containing data memory in particular, special
addressing methods designed for the functions of the special function registers (SFR) and general-purpose registers are
available for use. Figures 3-10 to 3-17 show correspondence between data memory and addressing. For details of each
addressing, see 3.4 Addressing for Processing Data Addresses.
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Figure 3-10. Correspondence Between Data Memory and Addressing (R5F104xA (x = A to C, E to G))
FFFFFH
FFF20H
FFF1FH
FFF00H
FFEFFH
FFEE0H
FFEDFH
FFE20H
FFE1FH
FF500H
FF4FFH
Special function register (SFR)
256 bytes
General-purpose register
32 bytes
SFR addressing
Register addressing
Short direct
addressing
RAM
2.5 KB
Reserved
F4000H
F3FFFH
F2000H
F1FFFH
F1000H
F0FFFH
Mirror
8 KB
Data flash memory
4 KB
Reserved
F0800H
F07FFH
Special function register (2nd SFR)
2 KB
F0000H
EFFFFH
Direct addressing
Register indirect addressing
Based addressing
Based indexed addressing
Reserved
04000H
03FFFH
Code flash memory
16 KB
00000H
<R>
Caution
When executing instructions from the RAM area while RAM parity error resets are enabled (RPERDIS
= 0), be sure to initialize the used RAM area + 10 bytes.
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Figure 3-11. Correspondence Between Data Memory and Addressing (R5F104xC (x = A to C, E to G, J, L))
FFFFFH
FFF20H
FFF1FH
FFF00H
FFEFFH
FFEE0H
FFEDFH
FFE20H
FFE1FH
FEF00H
FEEFFH
F8000H
F7FFFH
F2000H
F1FFFH
F1000H
F0FFFH
Special function register (SFR)
256 bytes
General-purpose register
32 bytes
SFR addressing
Register addressing
Short direct
addressing
RAM
4 KB
Reserved
Mirror
24 KB
Data flash memory
4 KB
Reserved
F0800H
F07FFH
Special function register (2nd SFR)
2 KB
Direct addressing
Register indirect addressing
F0000H
EFFFFH
Based addressing
Based indexed addressing
Reserved
08000H
07FFFH
Code flash memory
32 KB
00000H
<R>
Caution
When executing instructions from the RAM area while RAM parity error resets are enabled (RPERDIS
= 0), be sure to initialize the used RAM area + 10 bytes.
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Figure 3-12. Correspondence Between Data Memory and Addressing (R5F104xD (x = A to C, E to G, J, L))
FFFFFH
FFF20H
FFF1FH
FFF00H
FFEFFH
FFEE0H
FFEDFH
FFE20H
FFE1FH
FE900H
FE8FFH
FC000H
FBFFFH
F2000H
F1FFFH
F1000H
F0FFFH
Special function register (SFR)
256 bytes
General-purpose register
32 bytes
SFR addressing
Register addressing
Short direct
addressing
RAMNote
5.5 KB
Reserved
Mirror
40 KB
Data flash memory
4 KB
Reserved
F0800H
F07FFH
Special function register (2nd SFR)
2 KB
Direct addressing
Register indirect addressing
F0000H
EFFFFH
Based addressing
Based indexed addressing
Reserved
0C000H
0BFFFH
Code flash memory
48 KB
00000H
<R>
Note Use of the area FE900H to FED09H that is used as a work area for the library is prohibited when using the selfprogramming and data flash functions.
<R>
Caution
When executing instructions from the RAM area while RAM parity error resets are enabled (RPERDIS
= 0), be sure to initialize the used RAM area + 10 bytes.
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Figure 3-13. Correspondence Between Data Memory and Addressing (R5F104xE (x = A to C, E to G, J, L))
FFFFFH
FFF20H
FFF1FH
FFF00H
FFEFFH
FFEE0H
FFEDFH
FFE20H
FFE1FH
Special function register (SFR)
256 bytes
General-purpose register
32 bytes
SFR addressing
Register addressing
Short direct
addressing
RAMNote
5.5 KB
FE900H
FE8FFH
Mirror
50.25 KB
F2000H
F1FFFH
F1000H
F0FFFH
Data flash memory
4 KB
Reserved
F0800H
F07FFH
Special function register (2nd SFR)
2 KB
Direct addressing
Register indirect addressing
F0000H
EFFFFH
Based addressing
Based indexed addressing
Reserved
10000H
0FFFFH
Code flash memory
64 KB
00000H
<R>
Note Use of the area FE900H to FED09H that is used as a work area for the library is prohibited when using the selfprogramming and data flash functions.
<R>
Caution
When executing instructions from the RAM area while RAM parity error resets are enabled (RPERDIS
= 0), be sure to initialize the used RAM area + 10 bytes.
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Figure 3-14. Correspondence Between Data Memory and Addressing (R5F104xF (x = A to C, E to G, J, L, M, P))
FFFFFH
FFF20H
FFF1FH
FFF00H
FFEFFH
FFEE0H
FFEDFH
FFE20H
FFE1FH
FCF00H
FCEFFH
F3000H
F2FFFH
F1000H
F0FFFH
Special function register (SFR)
256 bytes
General-purpose register
32 bytes
SFR addressing
Register addressing
Short direct
addressing
RAM
12 KB
Mirror
39.75 KB
Data flash memory
8 KB
Reserved
F0800H
F07FFH
Special function register (2nd SFR)
2 KB
Direct addressing
Register indirect addressing
F0000H
EFFFFH
Based addressing
Based indexed addressing
Reserved
18000H
17FFFH
Code flash memory
96 KB
00000H
<R>
Caution
When executing instructions from the RAM area while RAM parity error resets are enabled (RPERDIS
= 0), be sure to initialize the used RAM area + 10 bytes.
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Figure 3-15. Correspondence Between Data Memory and Addressing (R5F104xG (x = A to C, E to G, J, L, M, P))
FFFFFH
FFF20H
FFF1FH
FFF00H
FFEFFH
FFEE0H
FFEDFH
FFE20H
FFE1FH
FBF00H
FBEFFH
F3000H
F2FFFH
F1000H
F0FFFH
Special function register (SFR)
256 bytes
General-purpose register
32 bytes
SFR addressing
Register addressing
Short direct
addressing
RAM
16 KB
Mirror
35.75 KB
Data flash memory
8 KB
Reserved
F0800H
F07FFH
Special function register (2nd SFR)
2 KB
Direct addressing
Register indirect addressing
F0000H
EFFFFH
Based addressing
Based indexed addressing
Reserved
20000H
1FFFFH
Code flash memory
128 KB
00000H
<R>
Caution
When executing instructions from the RAM area while RAM parity error resets are enabled (RPERDIS
= 0), be sure to initialize the used RAM area + 10 bytes.
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Figure 3-16. Correspondence Between Data Memory and Addressing (R5F104xH (x = E to G, J, L, M, P))
FFFFFH
FFF20H
FFF1FH
FFF00H
FFEFFH
FFEE0H
FFEDFH
FFE20H
FFE1FH
FAF00H
FAEFFH
F3000H
F2FFFH
F1000H
F0FFFH
Special function register (SFR)
256 bytes
General-purpose register
32 bytes
SFR addressing
Register addressing
Short direct
addressing
RAM
20 KB
Mirror
31.75 KB
Data flash memory
8 KB
Reserved
F0800H
F07FFH
Special function register (2nd SFR)
2 KB
Direct addressing
Register indirect addressing
F0000H
EFFFFH
Based addressing
Based indexed addressing
Reserved
30000H
2FFFFH
Code flash memory
192 KB
00000H
<R>
Caution
When executing instructions from the RAM area while RAM parity error resets are enabled (RPERDIS
= 0), be sure to initialize the used RAM area + 10 bytes.
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Figure 3-17. Correspondence Between Data Memory and Addressing (R5F104xJ (x = F, G, J, L, M, P))
FFFFFH
Special function register (SFR)
256 bytes
FFF20H
FFF1FH
FFF00H
FFEFFH
General-purpose register
32 bytes
FFEE0H
FFEDFH
SFR addressing
Register addressing
Short direct
addressing
RAMNotes 1, 2
FFE20H
FFE1FH
24 KB
F9F00H
F9EFFH
Mirror
27.75 KB
F3000H
F2FFFH
Data flash memory
8 KB
F1000H
F0FFFH
Reserved
F0800H
F07FFH
Special function register (2nd SFR)
2 KB
Direct addressing
Register indirect addressing
F0000H
EFFFFH
Based addressing
Based indexed addressing
Reserved
40000H
3FFFFH
Code flash memory
256 KB
00000H
<R>
Notes 1. Use of the area F9F00H to FA309H that is used as a work area for the library is prohibited when using the
self-programming and data flash functions.
<R>
<R>
2. Use of the area FA300H to FA6FFH is prohibited when using the on-chip debugging trace function.
Caution
When executing instructions from the RAM area while RAM parity error resets are enabled (RPERDIS
= 0), be sure to initialize the used RAM area + 10 bytes.
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3.2 Processor Registers
The RL78/G14 products incorporate the following processor registers.
3.2.1 Control registers
The control registers control the program sequence, statuses and stack memory. The control registers consist of a
program counter (PC), a program status word (PSW) and a stack pointer (SP).
(1) Program counter (PC)
The program counter is a 20-bit register that holds the address information of the next program to be executed.
In normal operation, PC is automatically incremented according to the number of bytes of the instruction to be fetched.
When a branch instruction is executed, immediate data and register contents are set.
Reset signal generation sets the reset vector table values at addresses 0000H and 0001H to the program counter.
Figure 3-18. Format of Program Counter
19
0
PC
(2) Program status word (PSW)
The program status word is an 8-bit register consisting of various flags set/reset by instruction execution.
Program status word contents are stored in the stack area upon vectored interrupt request is acknowledged or PUSH
PSW instruction execution and are restored upon execution of the RETB, RETI and POP PSW instructions. Reset
signal generation sets the PSW register to 06H.
Figure 3-19. Format of Program Status Word
7
PSW
IE
0
Z
RBS1
AC
RBS0
ISP1
ISP0
CY
(a) Interrupt enable flag (IE)
This flag controls the interrupt request acknowledge operations of the CPU.
When 0, the IE flag is set to the interrupt disabled (DI) state, and all maskable interrupt requests are disabled.
When 1, the IE flag is set to the interrupt enabled (EI) state and interrupt request acknowledgment is controlled
with an in-service priority flag (ISP1, ISP0), an interrupt mask flag for various interrupt sources, and a priority
specification flag.
The IE flag is reset (0) upon DI instruction execution or interrupt acknowledgment and is set (1) upon EI
instruction execution.
(b) Zero flag (Z)
When the operation result is zero, this flag is set (1). It is reset (0) in all other cases.
(c) Register bank select flags (RBS0, RBS1)
These are 2-bit flags to select one of the four register banks.
In these flags, the 2-bit information that indicates the register bank selected by SEL RBn instruction execution is
stored.
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(d) Auxiliary carry flag (AC)
If the operation result has a carry from bit 3 or a borrow at bit 3, this flag is set (1). It is reset (0) in all other cases.
(e) In-service priority flags (ISP1, ISP0)
This flag manages the priority of acknowledgeable maskable vectored interrupts. Vectored interrupt requests
specified lower than the value of ISP0 and ISP1 flags by the priority specification flag registers (PRn0L, PRn0H,
PRn1L, PRn1H, PRn2L, PRn2H) (see 21.3 (3)) can not be acknowledged. Actual request acknowledgment is
controlled by the interrupt enable flag (IE).
Remark n = 0, 1
(f) Carry flag (CY)
This flag stores overflow and underflow upon add/subtract instruction execution. It stores the shift-out value upon
rotate instruction execution and functions as a bit accumulator during bit operation instruction execution.
(3) Stack pointer (SP)
This is a 16-bit register to hold the start address of the memory stack area. Only the internal RAM area can be set as
the stack area.
Figure 3-20. Format of Stack Pointer
0
15
SP SP15 SP14 SP13 SP12 SP11 SP10 SP9 SP8 SP7 SP6 SP5 SP4 SP3 SP2 SP1 SP0
The SP is decremented ahead of write (save) to the stack memory and is incremented after read (restored) from the
stack memory.
Each stack operation saves data as shown in Figure 3-21.
Cautions 1. Since reset signal generation makes the SP contents undefined, be sure to initialize the SP
before using the stack.
2. It is prohibited to use the general-purpose register (FFEE0H to FFEFFH) space as a stack area.
<R>
3. The internal RAM in the following products cannot be used as stack memory when using the
self-programming and data flash function.
<R>
R5F104xD (x = A to C, E to G, J, L):
FE900H to FED09H
R5F104xE (x = A to C, E to G, J, L):
FE900H to FED09H
R5F104xJ (x = F, G, J, L, M, P):
F9F00H to FA309H
4. The internal RAM area in the following products cannot be used as stack memory when using
the on-chip debugging trace function.
R5F104xJ (x = A to C, E to G, J, L):
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Figure 3-21. Data to Be Saved to Stack Memory
PUSH PSW instruction
PUSH rp instruction
SP←SP−2
↑
SP−2
↑
SP−1
↑
SP →
Register pair lower
Register pair higher
CALL, CALLT instructions
(4-byte stack)
SP←SP−4
↑
SP−4
↑
SP−3
↑
SP−2
↑
SP−1
↑
SP →
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PC15 to PC8
PC19 to PC16
00H
SP←SP−2
↑
SP−2
↑
SP−1
↑
SP →
00H
PSW
Interrupt, BRK instruction
(4-byte stack)
SP←SP−4
↑
SP−4
↑
SP−3
↑
SP−2
↑
SP−1
↑
SP →
PC7 to PC0
PC15 to PC8
PC19 to PC16
PSW
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3.2.2 General-purpose registers
General-purpose registers are mapped at particular addresses (FFEE0H to FFEFFH) of the data memory. The generalpurpose registers consists of 4 banks, each bank consisting of eight 8-bit registers (X, A, C, B, E, D, L, and H).
Each register can be used as an 8-bit register, and two 8-bit registers can also be used in a pair as a 16-bit register (AX,
BC, DE, and HL).
These registers can be described in terms of function names (X, A, C, B, E, D, L, H, AX, BC, DE, and HL) and absolute
names (R0 to R7 and RP0 to RP3).
Register banks to be used for instruction execution are set by the CPU control instruction (SEL RBn). Because of the 4register bank configuration, an efficient program can be created by switching between a register for normal processing and
a register for interrupts for each bank.
Cautions 1. It is prohibited to use the general-purpose register (FFEE0H to FFEFFH) space for fetching
instructions or as a stack area.
<R>
2. The internal RAM in the following products cannot be used as stack memory when using the selfprogramming and data flash function.
R5F104xD (x = A to C, E to G, J, L):
<R>
FE900H to FED09H
R5F104xE (x = A to C, E to G, J, L):
FE900H to FED09H
R5F104xJ (x = F, G, J, L, M, P):
F9F00H to FA309H
3. The internal RAM area in the following products cannot be used as stack memory when using the
on-chip debugging trace function.
R5F104xJ (x = A to C, E to G, J, L):
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Figure 3-22. Configuration of General-Purpose Registers
(a) Function name
16-bit processing
8-bit processing
FFEFFH
H
Register bank 0
HL
L
FFEF8H
D
Register bank 1
DE
E
FFEF0H
B
BC
Register bank 2
C
FFEE8H
A
AX
Register bank 3
X
FFEE0H
15
0
7
0
(b) Absolute name
16-bit processing
8-bit processing
FFEFFH
R7
Register bank 0
RP3
R6
FFEF8H
R5
Register bank 1
RP2
R4
FFEF0H
R3
RP1
Register bank 2
R2
FFEE8H
R1
RP0
Register bank 3
R0
FFEE0H
15
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7
0
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3.2.3 ES and CS registers
The ES register is used for data access and the CS register is used to specify the higher address when a branch
instruction is executed.
The default value of the ES register after reset is 0FH, and that of the CS register is 00H.
Figure 3-23. Configuration of ES and CS Registers
ES
CS
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6
5
4
3
2
1
0
0
0
0
0
ES3
ES2
ES1
ES0
7
6
5
4
3
2
1
0
0
0
0
0
CS3
CP2
CP1
CP0
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3.2.4 Special function registers (SFRs)
Unlike a general-purpose register, each SFR has a special function.
SFRs are allocated to the FFF00H to FFFFFH area.
SFRs can be manipulated like general-purpose registers, using operation, transfer, and bit manipulation instructions.
The manipulable bit units, 1, 8, and 16, depend on the SFR type.
Each manipulation bit unit can be specified as follows.
• 1-bit manipulation
Describe the symbol reserved by the assembler for the 1-bit manipulation instruction operand (sfr.bit).
This manipulation can also be specified with an address.
• 8-bit manipulation
Describe the symbol reserved by the assembler for the 8-bit manipulation instruction operand (sfr).
This manipulation can also be specified with an address.
• 16-bit manipulation
Describe the symbol reserved by the assembler for the 16-bit manipulation instruction operand (sfrp).
When specifying an address, describe an even address.
Table 3-5 gives a list of the SFRs. The meanings of items in the table are as follows.
• Symbol
This item indicates the address of a special function register. It is a reserved word in the assembler, and is defined
as an sfr variable using the #pragma sfr directive in the compiler. When using the assembler, debugger, and
simulator, symbols can be written as an instruction operand.
• R/W
This item indicates whether the corresponding SFR can be read or written.
R/W: Read/write enable
R: Read only
W: Write only
• Manipulable bit units
“√” indicates the manipulable bit unit (1, 8, or 16). “−” indicates a bit unit for which manipulation is not possible.
• After reset
This item indicates each register status upon reset signal generation.
Caution Do not access addresses to which SFRs are not assigned.
Remark
For extended SFRs (2nd SFRs), see 3.2.5 Extended special function registers (2nd SFRs: 2nd Special
Function Registers).
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Table 3-5. SFR List (1/5)
Address Special Function Register (SFR) Name
FFF00H Port register 0
Symbol
P0
R/W
Manipulable Bit Range
After Reset
1-bit
8-bit
16-bit
R/W
√
√
−
00H
√
−
00H
FFF01H Port register 1
P1
R/W
√
FFF02H Port register 2
P2
R/W
√
√
−
00H
FFF03H Port register 3
P3
R/W
√
√
−
00H
FFF04H Port register 4
P4
R/W
√
√
−
00H
FFF05H Port register 5
P5
R/W
√
√
−
00H
FFF06H Port register 6
P6
R/W
√
√
−
00H
FFF07H Port register 7
P7
R/W
√
√
−
00H
√
−
00H
FFF08H Port register 8
P8
R/W
√
FFF0AH Port register 10
P10
R/W
√
√
−
00H
FFF0BH Port register 11
P11
R/W
√
√
−
00H
FFF0CH Port register 12
P12
R/W
√
√
−
Undefined
FFF0DH Port register 13
P13
R/W
√
√
−
Undefined
FFF0EH Port register 14
P14
R/W
√
√
−
00H
FFF0FH Port register 15
P15
R/W
√
√
−
00H
TXD0/ SDR00 R/W
SIO00
−
√
√
0000H
−
−
−
√
√
0000H
−
−
−
√
√
0000H
−
−
−
√
√
0000H
−
−
−
−
√
0000H
√
00H
FFF10H Serial data register 00
−
FFF11H
FFF12H Serial data register 01
RXD0/ SDR01 R/W
SIO01
−
FFF13H
FFF14H Serial data register 12
TXD3/ SDR12 R/W
SIO30
−
FFF15H
FFF16H Serial data register 13
RXD3/ SDR13 R/W
SIO31
−
FFF17H
FFF18H Timer data register 00
TDR00
R/W
FFF19H
FFF1AH Timer data register 01
FFF1BH
TDR01L TDR01 R/W
−
√
TDR01H
−
√
00H
FFF1EH 10-bit A/D conversion result
register
ADCR
R
−
−
√
0000H
FFF1FH
ADCRH
R
−
√
−
00H
8-bit A/D conversion
result register
FFF20H Port mode register 0
PM0
R/W
√
√
−
FFH
FFF21H Port mode register 1
PM1
R/W
√
√
−
FFH
FFF22H Port mode register 2
PM2
R/W
√
√
−
FFH
FFF23H Port mode register 3
PM3
R/W
√
√
−
FFH
FFF24H Port mode register 4
PM4
R/W
√
√
−
FFH
√
−
FFH
FFF25H Port mode register 5
PM5
R/W
√
FFF26H Port mode register 6
PM6
R/W
√
√
−
FFH
FFF27H Port mode register 7
PM7
R/W
√
√
−
FFH
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Table 3-5. SFR List (2/5)
Address Special Function Register (SFR) Name
FFF28H Port mode register 8
Symbol
PM8
R/W
Manipulable Bit Range
After Reset
1-bit
8-bit
16-bit
R/W
√
√
−
FFH
√
−
FFH
FFF2AH Port mode register 10
PM10
R/W
√
FFF2BH Port mode register 11
PM11
R/W
√
√
−
FFH
FFF2CH Port mode register 12
PM12
R/W
√
√
−
FFH
FFF2EH Port mode register 14
PM14
R/W
√
√
−
FFH
FFF2FH Port mode register 15
PM15
R/W
√
√
−
FFH
FFF30H A/D converter mode register 0
ADM0
R/W
√
√
−
00H
FFF31H Analog input channel
specification register
ADS
R/W
√
√
−
FFF32H A/D converter mode register 1
ADM1
R/W
√
√
−
FFF34H D/A conversion value setting
register 0
DACS0
R/W
−
√
−
FFF35H D/A conversion value setting
register 1
DACS1
R/W
−
√
−
FFF36H D/A converter mode register
DAM
R/W
√
√
−
00H
FFF37H Key return mode register
KRM
R/W
√
√
−
00H
EGP0
R/W
√
√
−
00H
EGN0
R/W
√
√
−
00H
EGP1
R/W
√
√
−
00H
EGN1
R/W
√
√
−
00H
TXD1/ SDR02 R/W
−
√
√
0000H
−
−
−
√
√
0000H
−
−
−
√
√
0000H
−
−
−
√
√
0000H
−
−
FFF38H External interrupt rising edge
00H
00H
00H
00H
enable register 0
FFF39H External interrupt falling edge
enable register 0
FFF3AH External interrupt rising edge
enable register 1
FFF3BH External interrupt falling edge
enable register 1
FFF44H Serial data register 02
SIO10
FFF45H
FFF46H Serial data register 03
−
RXD1/ SDR03 R/W
SIO11
FFF47H
FFF48H Serial data register 10
−
TXD2/ SDR10 R/W
SIO20
FFF49H
FFF4AH Serial data register 11
−
RXD2/ SDR11 R/W
SIO21
FFF4BH
−
FFF50H IICA shift register 0
IICA0
R/W
−
√
−
00H
FFF51H IICA status register 0
IICS0
R
√
√
−
00H
FFF52H IICA flag register 0
IICF0
R/W
√
√
−
00H
FFF54H IICA shift register 1
IICA1
R/W
−
√
−
00H
√
−
00H
√
−
00H
FFF55H IICA status register 1
IICS1
R
√
FFF56H IICA flag register 1
IICF1
R/W
√
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Table 3-5. SFR List (3/5)
Address Special Function Register (SFR) Name
Symbol
R/W
1-bit
8-bit
16-bit
TRDGRC0
R/W
−
−
√
FFFFH
Note 1
TRDGRD0
R/W
−
−
√
FFFFH
Note 1
TRDGRC1
R/W
−
−
√
FFFFH
Note 1
TRDGRD1
R/W
−
−
√
FFFFH
Note 1
TRGGRC
R/W
−
−
√
FFFFH
TRGGRD
R/W
−
−
√
FFFFH
TDR02
R/W
−
−
√
0000H
FFF66H Timer data register 03
TDR03L TDR03 R/W
−
√
√
00H
FFF67H
TDR03H
0000H
FFF58H Timer RD general register C0
Manipulable Bit Range
After Reset
FFF59H
FFF5AH Timer RD general register D0
FFF5BH
FFF5CH Timer RD general register C1
FFF5DH
FFF5EH Timer RD general register D1
FFF5FH
FFF60H Timer RG general register C
FFF61H
FFF62H Timer RG general register D
FFF63H
FFF64H Timer data register 02
FFF65H
FFF70H Timer data register 10
TDR10
R/W
−
√
−
−
√
√
00H
FFF71H
FFF72H Timer data register 11
TDR11L TDR11 R/W
−
√
FFF73H
TDR11H
−
√
R/W
−
−
√
0000H
FFF76H Timer data register 13
TDR13L TDR13 R/W
−
√
√
00H
FFF77H
TDR13H
−
√
FFF74H Timer data register 12
TDR12
00H
00H
FFF75H
00H
ITMC
R/W
−
−
√
0FFFH
FFF92H Second count register
SEC
R/W
−
√
−
00H
FFF93H Minute count register
MIN
R/W
−
√
−
00H
√
−
FFF90H 12-bit interval timer control
FFF91H register
FFF94H Hour count register
HOUR
R/W
−
FFF95H Week count register
WEEK
R/W
−
√
−
00H
FFF96H Day count register
DAY
R/W
−
√
−
01H
√
−
01H
12H
Note 2
FFF97H Month count register
MONTH
R/W
−
FFF98H Year count register
YEAR
R/W
−
√
−
00H
FFF99H Watch error correction register
SUBCUD
R/W
−
√
−
00H
FFF9AH Alarm minute register
ALARMWM
R/W
−
√
−
00H
FFF9BH Alarm hour register
ALARMWH
R/W
−
√
−
12H
FFF9CH Alarm week register
ALARMWW
R/W
−
√
−
00H
Notes 1. The timer RD SFRs are undefined when FRQSEL4 = 1 in the user option byte
(000C2H/010C2H) and TRD0EN = 0 in the PER1 register. If it is necessary to read the
initial value, set fCLK to fIH and TRD0EN = 1 before reading.
2. The value of this register is 00H if the AMPM bit (bit 3 of real-time clock control register
0 (RTCC0)) is set to 1 after reset.
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Table 3-5. SFR List (4/5)
Address Special Function Register (SFR) Name
Symbol
R/W
Manipulable Bit Range
After Reset
1-bit
8-bit
16-bit
RTCC0
R/W
√
√
−
00H
RTCC1
R/W
√
√
−
00H
CMC
R/W
−
√
−
00H
CSC
R/W
√
√
−
C0H
OSTC
R
√
√
−
00H
OSTS
R/W
−
√
−
07H
FFFA4H System clock control register
CKC
R/W
√
√
−
00H
FFFA5H Clock output select register 0
CKS0
R/W
√
√
−
00H
FFFA6H Clock output select register 1
CKS1
R/W
√
√
−
00H
R
−
√
−
FFF9DH Real-time clock control
register 0
FFF9EH Real-time clock control
register 1
FFFA0H Clock operation mode control
register
FFFA1H Clock operation status control
register
FFFA2H Oscillation stabilization time
counter status register
FFFA3H Oscillation stabilization time
select register
FFFA8H Reset control flag register
RESF
Undefined
Note 1
FFFA9H Voltage detection register
LVIM
R/W
√
√
−
00H
FFFAAH Voltage detection level register
LVIS
R/W
√
√
−
00H/01H/81H
FFFABH Watchdog timer enable register
WDTE
R/W
−
√
−
1AH/9AH
FFFACH CRC input register
CRCIN
R/W
−
√
−
00H
R/W
√
√
√
00H
R/W
√
√
R/W
√
√
√
FFH
R/W
√
√
R/W
√
√
R/W
√
√
R/W
√
√
R/W
√
√
FFFD0H Interrupt request flag register 2L IF2L
IF2
FFFD1H Interrupt request flag register 2H IF2H
FFFD4H Interrupt mask flag register 2L
MK2L
FFFD5H Interrupt mask flag register 2H
MK2H
MK2
FFFD8H Priority specification flag register PR02L PR02
Note 2
Note 3
Note 4
00H
FFH
√
FFH
02L
FFFD9H Priority specification flag register PR02H
FFH
02H
FFFDCH Priority specification flag register PR12L PR12
√
FFH
12L
FFFDDH Priority specification flag register PR12H
FFH
12H
Notes 1.
The reset value of the RESF register varies depending on the reset source.
2.
The reset value of the LVIM register varies depending on the reset source.
3.
The reset value of the LVIS register varies depending on the reset source and the
setting of the option byte.
4.
The reset value of the WDTE register is determined by the setting of the option byte.
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Table 3-5. SFR List (5/5)
Address Special Function Register (SFR) Name
Symbol
FFFE0H Interrupt request flag register 0L IF0L
IF0
FFFE1H Interrupt request flag register 0H IF0H
FFFE2H Interrupt request flag register 1L IF1L
IF1
FFFE3H Interrupt request flag register 1H IF1H
FFFE4H Interrupt mask flag register 0L
MK0L
FFFE5H Interrupt mask flag register 0H
MK0H
FFFE6H Interrupt mask flag register 1L
MK1L
FFFE7H Interrupt mask flag register 1H
MK1H
MK0
MK1
FFFE8H Priority specification flag register PR00L PR00
R/W
Manipulable Bit Range
1-bit
8-bit
16-bit
R/W
√
√
√
R/W
√
√
R/W
√
√
R/W
√
√
R/W
√
√
R/W
√
√
R/W
√
√
R/W
√
√
R/W
√
√
R/W
√
√
R/W
√
√
R/W
√
√
R/W
√
√
R/W
√
√
R/W
√
√
R/W
√
√
After Reset
00H
00H
√
00H
00H
√
FFH
FFH
√
FFH
FFH
√
FFH
00L
FFFE9H Priority specification flag register PR00H
FFH
00H
FFFEAH Priority specification flag register PR01L PR01
√
FFH
01L
FFFEBH Priority specification flag register PR01H
FFH
01H
FFFECH Priority specification flag register PR10L PR10
√
FFH
10L
FFFEDH Priority specification flag register PR10H
FFH
10H
FFFEEH Priority specification flag register PR11L PR11
√
FFH
11L
FFFEFH Priority specification flag register PR11H
FFH
11H
FFFF0H Multiply and accumulation register
FFFF1H (L)
MACRL
R/W
−
−
√
0000H
FFFF2H Multiply and accumulation register
FFFF3H (H)
MACRH
R/W
−
−
√
0000H
R/W
√
√
−
00H
FFFFEH Processor mode control register PMC
Remark
nd
nd
For extended SFRs (2 SFRs), see Table 3-6 Extended SFR (2 SFR) List.
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3.2.5 Extended special function registers (2nd SFRs: 2nd Special Function Registers)
Unlike a general-purpose register, each extended SFR (2nd SFR) has a special function.
Extended SFRs are allocated to the F0000H to F07FFH area. SFRs other than those in the SFR area (FFF00H to
FFFFFH) are allocated to this area. An instruction that accesses the extended SFR area, however, is 1 byte longer than
an instruction that accesses the SFR area.
Extended SFRs can be manipulated like general-purpose registers, using operation, transfer, and bit manipulation
instructions. The manipulable bit units, 1, 8, and 16, depend on the SFR type.
Each manipulation bit unit can be specified as follows.
• 1-bit manipulation
Describe the symbol reserved by the assembler for the 1-bit manipulation instruction operand (!addr16.bit). This
manipulation can also be specified with an address.
• 8-bit manipulation
Describe the symbol reserved by the assembler for the 8-bit manipulation instruction operand (!addr16). This
manipulation can also be specified with an address.
• 16-bit manipulation
Describe the symbol reserved by the assembler for the 16-bit manipulation instruction operand (!addr16). When
specifying an address, describe an even address.
Table 3-6 gives a list of the extended SFRs. The meanings of items in the table are as follows.
• Symbol
This item indicates the address of an extended SFR. It is a reserved word in the assembler, and is defined as an sfr
variable using the #pragma sfr directive in the compiler. When using the assembler, debugger, and simulator,
symbols can be written as an instruction operand.
• R/W
This item indicates whether the corresponding extended SFR can be read or written.
R/W: Read/write enable
R:
Read only
W: Write only
• Manipulable bit units
“√” indicates the manipulable bit unit (1, 8, or 16). “−” indicates a bit unit for which manipulation is not possible.
• After reset
This item indicates each register status upon reset signal generation.
Caution Do not access addresses to which extended SFRs are not assigned.
Remark
For SFRs in the SFR area, see 3.2.4 Special function registers (SFRs).
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nd
Table 3-6. Extended SFR (2 SFR) List (1/9)
Address Special Function Register (SFR) Name
F0010H
A/D converter mode register 2
Symbol
ADM2
R/W
Manipulable Bit Range
After Reset
1-bit
8-bit
R/W
√
√
16-bit
−
00H
√
−
FFH
F0011H
Conversion result comparison
upper limit setting register
ADUL
R/W
−
F0012H
Conversion result comparison
lower limit setting register
ADLL
R/W
−
√
−
00H
F0013H
A/D test register
ADTES
R/W
−
√
−
00H
F0030H
Pull-up resistor option register 0 PU0
R/W
√
√
−
00H
F0031H
Pull-up resistor option register 1 PU1
R/W
√
√
−
00H
F0033H
Pull-up resistor option register 3 PU3
R/W
√
√
−
00H
√
−
01H
F0034H
Pull-up resistor option register 4 PU4
R/W
√
F0035H
Pull-up resistor option register 5 PU5
R/W
√
√
−
00H
√
−
00H
F0036H
Pull-up resistor option register 6 PU6
R/W
√
F0037H
Pull-up resistor option register 7 PU7
R/W
√
√
−
00H
F0038H
Pull-up resistor option register 8 PU8
R/W
√
√
−
00H
F003AH Pull-up resistor option register 10
PU10
R/W
√
√
−
00H
F003BH Pull-up resistor option register 11
PU11
R/W
√
√
−
00H
F003CH Pull-up resistor option register 12
PU12
R/W
√
√
−
00H
F003EH Pull-up resistor option register 14
PU14
R/W
√
√
−
00H
√
−
00H
F0040H
Port input mode register 0
PIM0
R/W
√
F0041H
Port input mode register 1
PIM1
R/W
√
√
−
00H
F0043H
Port input mode register 3
PIM3
R/W
√
√
−
00H
F0044H
Port input mode register 4
PIM4
R/W
√
√
−
00H
F0045H
Port input mode register 5
PIM5
R/W
√
√
−
00H
F0048H
Port input mode register 8
PIM8
R/W
√
√
−
00H
PIM14
R/W
√
√
−
00H
√
−
00H
F004EH Port input mode register 14
F0050H
Port output mode register 0
POM0
R/W
√
F0051H
Port output mode register 1
POM1
R/W
√
√
−
00H
F0053H
Port output mode register 3
POM3
R/W
√
√
−
00H
F0054H
Port output mode register 4
POM4
R/W
√
√
−
00H
F0055H
Port output mode register 5
POM5
R/W
√
√
−
00H
F0057H
Port output mode register 7
POM7
R/W
√
√
−
00H
F0058H
Port output mode register 8
POM8
R/W
√
√
−
00H
F005EH Port output mode register 14
POM14
R/W
√
√
−
00H
F0060H
Port mode control register 0
PMC0
R/W
√
√
−
FFH
F0061H
Port mode control register 1
PMC1
R/W
√
√
−
00H
F006AH Port mode control register 10
PMC10
R/W
√
√
−
FFH
F006CH Port mode control register 12
PMC12
R/W
√
√
−
FFH
F006EH Port mode control register 14
PMC14
R/W
√
√
−
FFH
F0070H
Noise filter enable register 0
NFEN0
R/W
√
√
−
00H
F0071H
Noise filter enable register 1
NFEN1
R/W
√
√
−
00H
F0072H
Noise filter enable register 2
NFEN2
R/W
√
√
−
00H
F0073H
Input switch control register
ISC
R/W
√
√
−
00H
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Table 3-6. Extended SFR (2nd SFR) List (2/9)
Address Special Function Register (SFR) Name
F0074H
Timer input select register 0
Symbol
TIS0
R/W
Manipulable Bit Range
1-bit
8-bit
16-bit
R/W
−
√
−
After Reset
00H
F0076H
A/D port configuration register
ADPC
R/W
−
√
−
00H
F0077H
Peripheral I/O redirection
register 0
PIOR0
R/W
−
√
−
00H
F0078H
Invalid memory access
detection control register
IAWCTL
R/W
−
√
−
00H
F0079H
Peripheral I/O redirection
register 1
PIOR1
R/W
−
√
−
00H
F007AH Peripheral enable register1
PER1
R/W
√
√
−
00H
F007BH Port mode select resister
PMS
R/W
√
√
−
00H
R/W
√
√
−
00H
F007DH Global digital input disable
register
GDIDIS
F0090H
DFLCTL
R/W
√
√
−
00H
F00A0H High-speed on-chip oscillator
trimming register
HIOTRM
R/W
−
√
−
Note
F00A8H High-speed on-chip oscillator
HOCODIV
R/W
−
√
−
Undefined
PER0
R/W
√
√
−
00H
R/W
−
√
−
00H
R/W
√
√
−
00H
R
−
√
−
Undefined
R
−
√
√
0000H
−
−
−
√
√
0000H
−
−
−
√
√
0000H
−
−
−
√
√
0000H
−
−
−
√
√
0000H
−
−
−
√
√
0000H
−
−
−
√
√
0000H
−
−
−
√
√
0000H
−
−
Data flash control register
frequency select register
F00F0H Peripheral enable register 0
F00F3H Operation speed mode control
register
OSMC
F00F5H RAM parity error control register RPECTL
F00FEH BCD adjust result register
F0100H
Serial status register 00
Serial status register 01
Serial status register 02
Serial status register 03
SSR02L SSR02
R
SSR03L SSR03
R
−
F0107H
Serial flag clear trigger register
00
SIR00L SIR00 R/W
F010AH Serial flag clear trigger register
F010BH 01
SIR01L SIR01 R/W
F010CH Serial flag clear trigger register
F010DH 02
SIR02L SIR02 R/W
F010EH Serial flag clear trigger register
F010FH 03
SIR03L SIR03 R/W
F0108H
F0109H
<R>
R
−
F0105H
F0106H
SSR01L SSR01
−
F0103H
F0104H
SSR00L SSR00
−
F0101H
F0102H
BCDADJ
−
−
−
−
Note The reset value differs for each chip.
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CHAPTER 3 CPU ARCHITECTURE
Table 3-6. Extended SFR (2nd SFR) List (3/9)
Address
Special Function Register (SFR)
Name
Symbol
R/W
Manipulable Bit Range
After Reset
1-bit
8-bit
16-bit
Serial mode register 00
SMR00
R/W
−
−
√
0020H
Serial mode register 01
SMR01
R/W
−
−
√
0020H
Serial mode register 02
SMR02
R/W
−
−
√
0020H
Serial mode register 03
SMR03
R/W
−
−
√
0020H
Serial communication
operation setting register 00
SCR00
R/W
−
−
√
0087H
F011AH Serial communication
F011BH operation setting register 01
SCR01
R/W
−
−
√
0087H
F011CH Serial communication
F011DH operation setting register 02
SCR02
R/W
−
−
√
0087H
F011EH Serial communication
F011FH operation setting register 03
SCR03
R/W
−
−
√
0087H
√
√
√
0000H
−
−
√
0000H
√
0000H
√
0000H
F0110H
F0111H
F0112H
F0113H
F0114H
F0115H
F0116H
F0117H
F0118H
F0119H
Serial channel enable status
register 0
SE0L
F0121H
F0122H
Serial channel start register 0
SS0L
F0120H
Serial channel stop register 0
Serial clock select register 0
R/W
ST0L
ST0
R/W
SPS0L
Serial output register 0
√
√
−
−
√
√
−
−
−
√
−
−
R/W
−
−
√
0F0FH
SOE0
R/W
√
√
√
0000H
−
−
SOL0
R/W
−
√
√
0000H
−
−
SSC0
R/W
√
0000H
√
0000H
√
0000H
√
0000H
√
0000H
SPS0
R/W
−
F0127H
F0128H
SS0
−
F0125H
F0126H
R
−
F0123H
F0124H
SE0
−
SO0
F0129H
F012AH Serial output enable register 0 SOE0L
−
F012BH
F0134H
Serial output level register 0
SOL0L
Serial standby control
register 0
SSC0L
Serial status register 10
SSR10L SSR10
−
F0135H
F0138H
F0140H
Serial status register 11
Serial status register 12
SSR11
R
SSR12L SSR12
R
−
F0145H
F0146H
SSR11L
−
F0143H
F0144H
R
−
F0141H
F0142H
−
Serial status register 13
F0147H
R01UH0186EJ0100 Rev.1.00
Dec 28, 2011
SSR13L
−
SSR13
R
−
√
−
−
−
√
−
−
−
√
−
−
−
√
−
−
−
√
−
−
131
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CHAPTER 3 CPU ARCHITECTURE
Table 3-6. Extended SFR (2nd SFR) List (4/9)
Address Special Function Register (SFR) Name
Symbol
R/W
Serial flag clear trigger register
10
SIR10L SIR10 R/W
F014AH Serial flag clear trigger register
F014BH 11
SIR11L SIR11 R/W
F014CH Serial flag clear trigger register
F014DH 12
SIR12L SIR12 R/W
F014EH Serial flag clear trigger register
F014FH 13
SIR13L SIR13 R/W
F0148H
F0149H
−
−
−
−
Manipulable Bit Range
After Reset
1-bit
8-bit
16-bit
−
√
√
0000H
−
−
−
√
√
0000H
−
−
−
√
√
0000H
−
−
−
√
√
0000H
−
−
Serial mode register 10
SMR10
R/W
−
−
√
0020H
Serial mode register 11
SMR11
R/W
−
−
√
0020H
Serial mode register 12
SMR12
R/W
−
−
√
0020H
Serial mode register 13
SMR13
R/W
−
−
√
0020H
Serial communication operation
setting register 10
SCR10
R/W
−
−
√
0087H
F015AH Serial communication operation
F015BH setting register 11
SCR11
R/W
−
−
√
0087H
F015CH Serial communication operation
F015DH setting register 12
SCR12
R/W
−
−
√
0087H
F015EH Serial communication operation
F015FH setting register 13
SCR13
R/W
−
−
√
0087H
R
√
√
√
0000H
−
−
√
√
√
0000H
−
−
√
√
√
0000H
−
−
−
√
√
0000H
−
−
F0150H
F0151H
F0152H
F0153H
F0154H
F0155H
F0156H
F0157H
F0158H
F0159H
SE1L
F0161H
Serial channel enable status
register 1
F0162H
Serial channel start register 1
SS1L
Serial channel stop register 1
ST1L
Serial clock select register 1
SPS1L SPS1
F0160H
R/W
ST1
R/W
R/W
−
F0167H
F0168H
SS1
−
F0165H
F0166H
−
−
F0163H
F0164H
SE1
Serial output register 1
SO1
R/W
−
−
√
0F0FH
SOE1L SOE1
R/W
√
√
√
0000H
−
−
−
√
√
0000H
−
−
−
√
√
0000H
−
−
F0169H
F016AH Serial output enable register 1
−
F016BH
F0174H
Serial output level register 1
F0178H
F0179H
SOL1L SOL1
R/W
−
F0175H
Serial standby control
register 1
R01UH0186EJ0100 Rev.1.00
Dec 28, 2011
SSC1L SSC1
−
R/W
132
RL78/G14
CHAPTER 3 CPU ARCHITECTURE
Table 3-6. Extended SFR (2nd SFR) List (5/9)
Address Special Function Register (SFR) Name
F0180H
Symbol
R/W
Manipulable Bit Range
After Reset
1-bit
8-bit
16-bit
Timer counter register 00
TCR00
R
−
−
√
FFFFH
Timer counter register 01
TCR01
R
−
−
√
FFFFH
Timer counter register 02
TCR02
R
−
−
√
FFFFH
Timer counter register 03
TCR03
R
−
−
√
FFFFH
Timer mode register 00
TMR00
R/W
−
−
√
0000H
Timer mode register 01
TMR01
R/W
−
−
√
0000H
Timer mode register 02
TMR02
R/W
−
−
√
0000H
Timer mode register 03
TMR03
R/W
−
−
√
0000H
R
−
√
√
0000H
−
−
−
√
√
0000H
−
−
−
√
√
0000H
−
−
−
√
√
0000H
−
−
√
√
√
0000H
−
−
√
√
√
0000H
−
−
√
√
√
0000H
F0181H
F0182H
F0183H
F0184H
F0185H
F0186H
F0187H
F0190H
F0191H
F0192H
F0193H
F0194H
F0195H
F0196H
F0197H
F01A0H Timer status register 00
F01A1H
F01A2H Timer status register 01
F01A3H
F01A4H Timer status register 02
F01A5H
F01A6H Timer status register 03
F01A7H
TSR00L TSR00
−
TSR01L TSR01
TSR02L TSR02
TSR03L TSR03
F01B2H Timer channel start register 0
TS0L
F01B5H
F01B6H Timer clock select register 0
R
−
TE0L
F01B4H Timer channel stop register 0
R
−
F01B0H Timer channel enable status
F01B1H register 0
F01B3H
R
−
TE0
R
−
TS0
R/W
TT0
R/W
−
TT0L
−
TPS0
−
−
R/W
−
−
√
0000H
R/W
−
√
√
0000H
−
−
√
√
√
0000H
−
−
−
√
√
0000H
−
−
−
√
√
0000H
−
−
F01B7H
F01B8H Timer output register 0
F01B9H
F01BAH Timer output enable register 0
F01BBH
F01BCH Timer output level register 0
F01BDH
F01BEH Timer output mode register 0
F01BFH
R01UH0186EJ0100 Rev.1.00
Dec 28, 2011
TO0L
TO0
−
TOE0L TOE0
R/W
−
TOL0L TOL0
R/W
−
TOM0L TOM0 R/W
−
133
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CHAPTER 3 CPU ARCHITECTURE
Table 3-6. Extended SFR (2nd SFR) List (6/9)
Address Special Function Register (SFR) Name
F01C0H Timer counter register 10
Symbol
R/W
Manipulable Bit Range
After Reset
1-bit
8-bit
16-bit
TCR10
R
−
−
√
FFFFH
TCR11
R
−
−
√
FFFFH
TCR12
R
−
−
√
FFFFH
TCR13
R
−
−
√
FFFFH
TMR10
R/W
−
−
√
0000H
TMR11
R/W
−
−
√
0000H
TMR12
R/W
−
−
√
0000H
TMR13
R/W
−
−
√
0000H
R
−
√
√
0000H
−
−
−
√
√
0000H
−
−
−
√
√
0000H
−
−
−
√
√
0000H
−
−
√
√
√
0000H
−
−
√
√
√
0000H
−
−
√
√
√
0000H
F01C1H
F01C2H Timer counter register 11
F01C3H
F01C4H Timer counter register 12
F01C5H
F01C6H Timer counter register 13
F01C7H
<R>
F01D0H Timer mode register 10
F01D1H
<R>
F01D2H Timer mode register 11
F01D3H
<R>
F01D4H Timer mode register 12
F01D5H
<R>
F01D6H Timer mode register 13
F01D7H
F01E0H Timer status register 10
F01E1H
F01E2H Timer status register 11
F01E3H
F01E4H Timer status register 12
F01E5H
F01E6H Timer status register 13
F01E7H
TSR10L TSR10
−
TSR11L TSR11
TSR12L TSR12
TSR13L TSR13
F01F2H Timer channel start register 1
TS1L
F01F5H
F01F6H Timer clock select register 1
R
−
TE1L
F01F4H Timer channel stop register 1
R
−
F01F0H Timer channel enable status
F01F1H register 1
F01F3H
R
−
TE1
R
−
TS1
R/W
TT1
R/W
−
TT1L
−
TPS1
−
−
R/W
−
−
√
0000H
R/W
−
√
√
0000H
−
−
√
√
√
0000H
−
−
−
√
√
0000H
−
−
−
√
√
0000H
−
−
F01F7H
F01F8H Timer output register 1
F01F9H
F01FAH Timer output enable register 1
F01FBH
F01FCH Timer output level register 1
F01FDH
F01FEH Timer output mode register 1
F01FFH
R01UH0186EJ0100 Rev.1.00
Dec 28, 2011
TO1L
TO1
−
TOE1L TOE1
R/W
−
TOL1L TOL1
R/W
−
TOM1L TOM1 R/W
−
134
RL78/G14
CHAPTER 3 CPU ARCHITECTURE
Table 3-6. Extended SFR (2nd SFR) List (7/9)
Address Special Function Register (SFR) Name
F0230H
IICA control register 00
Symbol
IICCTL00
R/W
Manipulable Bit Range
After Reset
1-bit
8-bit
16-bit
R/W
√
√
−
√
−
00H
00H
F0231H
IICA control register 01
IICCTL01
R/W
√
F0232H
IICA low-level width setting
register 0
IICWL0
R/W
−
√
−
FFH
F0233H
IICA high-level width setting
register 0
IICWH0
R/W
−
√
−
FFH
F0234H
Slave address register 0
SVA0
R/W
−
√
−
00H
F0238H
IICA control register 10
IICCTL10
R/W
√
√
−
00H
F0239H
IICA control register 11
IICCTL11
R/W
√
√
−
00H
√
−
FFH
F023AH IICA low-level width setting
register 1
IICWL1
R/W
−
F023BH IICA high-level width setting
register 1
IICWH1
R/W
−
√
−
FFH
F023CH Slave address register 1
SVA1
R/W
−
√
−
00H
F0240H
Timer RJ control resister 0
TRJCR0
R/W
−
√
−
00H
F0241H
Timer RJ I/O control resister 0
TRJIOC0
R/W
√
√
−
00H
F0242H
Timer RJ mode resister 0
TRJMR0
R/W
√
√
−
00H
F0243H
Timer RJ event pin select
resister 0
TRJISR0
R/W
√
√
−
00H
F0250H
Timer RG mode resister
TRGMR
R/W
√
√
−
00H
F0251H
Timer RG count control resister
TRGCNTC
R/W
√
√
−
00H
F0252H
Timer RG control resister
TRGCR
R/W
√
√
−
00H
F0253H
Timer RG interrupt enable
resister
TRGIER
R/W
√
√
−
00H
F0254H
Timer RG status resister
TRGSR
R/W
√
√
−
00H
F0255H
Timer RG I/O control resister
TRGIOR
R/W
√
√
−
00H
F0256H
Timer RG counter
TRG
R/W
−
−
√
0000H
Timer RG general register A
TRGGRA
R/W
−
−
√
FFFFH
F025AH Timer RG general register B
TRGGRB
R/W
−
−
√
FFFFH
F0257H
F0258H
F0259H
F025BH
Note
F0260H
Timer RD ELC register
TRDELC
R/W
√
√
−
00H
Note
F0263H
Timer RD start register
TRDSTR
R/W
−
√
−
0CH
Note
F0264H
Timer RD mode register
TRDMR
R/W
√
√
−
00H
Note
F0265H
Timer RD PWM function select
register
TRDPMR
R/W
√
√
−
00H
Note
F0266H
Timer RD function control
register
TRDFCR
R/W
√
√
−
80H
Note
F0267H
Timer RD output master enable
register 1
TRDOER1
R/W
√
√
−
FFH
Note
F0268H
Timer RD output master enable
register 2
TRDOER2
R/W
√
√
−
00H
Note
F0269H
Timer RD output control register TRDOCR
R/W
√
√
−
00H
Note
The timer RD SFRs are undefined when FRQSEL4 = 1 in the user option byte (000C2H/010C2H) and TRD0EN =
0 in the PER1 register. If it is necessary to read the initial value, set fCLK to fIH and TRD0EN = 1 before reading.
R01UH0186EJ0100 Rev.1.00
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135
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CHAPTER 3 CPU ARCHITECTURE
Table 3-6. Extended SFR (2nd SFR) List (8/9)
Address Special Function Register (SFR) Name
Symbol
R/W
Manipulable Bit Range
After Reset
1-bit
8-bit
16-bit
F026AH Timer RD digital filter function
select register 0
TRDDF0
R/W
√
√
−
00H
Note
F026BH Timer RD digital filter function
select register 1
TRDDF1
R/W
√
√
−
00H
Note
F0270H
Timer RD control register 0
TRDCR0
R/W
√
√
−
00H
Note
F0271H
Timer RD I/O control register A0 TRDIORA0
R/W
√
√
−
00H
Note
F0272H
Timer RD I/O control register C0 TRDIORC0
R/W
√
√
−
88H
Note
F0273H
Timer RD status register 0
TRDSR0
R/W
√
√
−
00H
Note
F0274H
Timer RD interrupt enable
register 0
TRDIER0
R/W
√
√
−
00H
Note
F0275H
Timer RD PWM function output
level control register 0
TRDPOCR0
R/W
√
√
−
00H
Note
F0276H
Timer RD counter 0
TRD0
R/W
−
−
√
0000H
Note
Timer RD general register A0
TRDGRA0
R/W
−
−
√
FFFFH
Note
F027AH Timer RD general register B0
TRDGRB0
R/W
−
−
√
FFFFH
Note
TRDCR1
R/W
√
√
−
00H
Note
F0277H
F0278H
F0279H
F027BH
F0280H
Timer RD control register 1
F0281H
Timer RD I/O control register A1 TRDIORA1
R/W
√
√
−
00H
Note
F0282H
Timer RD I/O control register C1 TRDIORC1
R/W
√
√
−
88H
Note
F0283H
Timer RD status register 1
TRDSR1
R/W
√
√
−
00H
Note
F0284H
Timer RD interrupt enable
register 1
TRDIER1
R/W
√
√
−
00H
Note
F0285H
Timer RD PWM function output
level control register 1
TRDPOCR1
R/W
√
√
−
00H
Note
F0286H
Timer RD counter 1
TRD1
R/W
−
−
√
0000H
Note
Timer RD general register A1
TRDGRA1
R/W
−
−
√
FFFFH
Note
F028AH Timer RD general register B1
TRDGRB1
R/W
−
−
√
FFFFH
Note
DTCBAR
R/W
−
√
−
FDH
F02E8H DTC activation enable register 0 DTCEN0
R/W
√
√
−
00H
F02E9H DTC activation enable register 1 DTCEN1
R/W
√
√
−
00H
F02EAH DTC activation enable register 2 DTCEN2
R/W
√
√
−
00H
F02EBH DTC activation enable register 3 DTCEN3
R/W
√
√
−
00H
F02ECH DTC activation enable register 4 DTCEN4
R/W
√
√
−
00H
F02F0H Flash memory CRC control
CRC0CTL
R/W
√
√
−
00H
PGCRCL
R/W
−
−
√
0000H
CRCD
R/W
−
−
√
0000H
F0287H
F0288H
F0289H
F028BH
F02E0H DTC base address register
register
F02F2H Flash memory CRC operation
result register
F02FAH CRC data register
Note
The timer RD SFRs are undefined when FRQSEL4 = 1 in the user option byte (000C2H/010C2H) and TRD0EN =
0 in the PER1 register. If it is necessary to read the initial value, set fCLK to fIH and TRD0EN = 1 before reading.
R01UH0186EJ0100 Rev.1.00
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136
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CHAPTER 3 CPU ARCHITECTURE
Table 3-6. Extended SFR (2nd SFR) List (9/9)
Address
Special Function Register (SFR) Name
Symbol
R/W
Manipulable Bit
Range
After Reset
1-bit 8-bit 16-bit
F0300H
Event output destination select register 00
ELSELR00
R/W
√
√
−
00H
F0301H
Event output destination select register 01
ELSELR01
R/W
√
√
−
00H
F0302H
Event output destination select register 02
ELSELR02
R/W
√
√
−
00H
F0303H
Event output destination select register 03
ELSELR03
R/W
√
√
−
00H
F0304H
Event output destination select register 04
ELSELR04
R/W
√
√
−
00H
√
−
00H
F0305H
Event output destination select register 05
ELSELR05
R/W
√
F0306H
Event output destination select register 06
ELSELR06
R/W
√
√
−
00H
F0307H
Event output destination select register 07
ELSELR07
R/W
√
√
−
00H
√
−
00H
F0308H
Event output destination select register 08
ELSELR08
R/W
√
F0309H
Event output destination select register 09
ELSELR09
R/W
√
√
−
00H
F030AH Event output destination select register 10
ELSELR10
R/W
√
√
−
00H
√
−
00H
F030BH Event output destination select register 11
ELSELR11
R/W
√
F030CH Event output destination select register 12
ELSELR12
R/W
√
√
−
00H
F030DH Event output destination select register 13
ELSELR13
R/W
√
√
−
00H
F030EH Event output destination select register 14
ELSELR14
R/W
√
√
−
00H
F030FH Event output destination select register 15
ELSELR15
R/W
√
√
−
00H
F0310H
Event output destination select register 16
ELSELR16
R/W
√
√
−
00H
F0311H
Event output destination select register 17
ELSELR17
R/W
√
√
−
00H
F0312H
Event output destination select register 18
ELSELR18
R/W
√
√
−
00H
F0313H
Event output destination select register 19
ELSELR19
R/W
√
√
−
00H
F0314H
Event output destination select register 20
ELSELR20
R/W
√
√
−
00H
√
−
00H
F0315H
Event output destination select register 21
ELSELR21
R/W
√
F0316H
Event output destination select register 22
ELSELR22
R/W
√
√
−
00H
F0317H
Event output destination select register 23
ELSELR23
R/W
√
√
−
00H
√
−
00H
F0318H
Event output destination select register 24
ELSELR24
R/W
√
F0319H
Event output destination select register 25
ELSELR25
R/W
√
√
−
00H
F0340H
Comparator mode setting Register
COMPMD
R/W
√
√
−
00H
R
F0341H
Comparator filter control Register
COMPFIR
R/W
√
√
−
00H
F0342H
Comparator output control Register
COMPOC
R/W
√
√
−
00H
R/W
−
−
√
FFFFH
R
F0500H
TRJ counter
TRJ0
F0501H
Remark
For SFRs in the SFR area, see Table 3-5 SFR List.
R01UH0186EJ0100 Rev.1.00
Dec 28, 2011
137
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CHAPTER 3 CPU ARCHITECTURE
3.3 Instruction Address Addressing
3.3.1 Relative addressing
[Function]
Relative addressing stores in the program counter (PC) the result of adding a displacement value included in the
instruction word (signed complement data: −128 to +127 or −32768 to +32767) to the program counter (PC)’s value
(the start address of the next instruction), and specifies the program address to be used as the branch destination.
Relative addressing is applied only to branch instructions.
Figure 3-24 Outline of Relative Addressing
PC
OP code
DISPLACE
8/16 bits
3.3.2 Immediate addressing
[Function]
Immediate addressing stores immediate data of the instruction word in the program counter, and specifies the
program address to be used as the branch destination.
For immediate addressing, CALL !!addr20 or BR !!addr20 is used to specify 20-bit addresses and CALL !addr16 or
BR !addr16 is used to specify 16-bit addresses. 0000 is set to the higher 4 bits when specifying 16-bit addresses.
Figure 3-25 Example of CALL !!addr20/BR !!addr20
PC
OP code
Low Addr.
High Addr.
Seg Addr.
Figure 3-26 Example of CALL !addr16/BR !addr16
PC
PCS
PCH
PCL
OP code
0000
Low Addr.
High Addr.
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3.3.3 Table indirect addressing
[Function]
Table indirect addressing specifies a table address in the CALLT table area (0080H to 00BFH) with the 5-bit
immediate data in the instruction word, stores the contents at that table address and the next address in the program
counter (PC) as 16-bit data, and specifies the program address. Table indirect addressing is applied only for CALLT
instructions.
In the RL78 microcontrollers, branching is enabled only to the 64 KB space from 00000H to 0FFFFH.
Figure 3-27 Outline of Table Indirect Addressing
OP code
High Addr.
<R>
00000000
10
0
Low Addr.
Table address
Memory
0000
PC
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PCH
PCL
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3.3.4 Register direct addressing
[Function]
Register direct addressing stores in the program counter (PC) the contents of a general-purpose register pair
(AX/BC/DE/HL) and CS register of the current register bank specified with the instruction word as 20-bit data, and
specifies the program address. Register direct addressing can be applied only to the CALL AX, BC, DE, HL, and BR
AX instructions.
Figure 3-28 Outline of Register Direct Addressing
OP code
rp
CS
PC
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PCH
PCL
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3.4 Addressing for Processing Data Addresses
3.4.1 Implied addressing
[Function]
Instructions for accessing registers (such as accumulators) that have special functions are directly specified with the
instruction word, without using any register specification field in the instruction word.
[Operand format]
Because implied addressing can be automatically employed with an instruction, no particular operand format is
necessary.
Implied addressing can be applied only to MULU X.
Figure 3-29 Outline of Implied Addressing
OP code
A register
Memory
3.4.2 Register addressing
[Function]
Register addressing accesses a general-purpose register as an operand. The instruction word of 3-bit long is used
to select an 8-bit register and the instruction word of 2-bit long is used to select a 16-bit register.
[Operand format]
Identifier
Description
r
X, A, C, B, E, D, L, H
rp
AX, BC, DE, HL
Figure 3-30 Outline of Register Addressing
OP code
Register
Memory
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3.4.3 Direct addressing
[Function]
Direct addressing uses immediate data in the instruction word as an operand address to directly specify the target
address.
[Operand format]
Identifier
Description
ADDR16
Label or 16-bit immediate data (only the space from F0000H to FFFFFH is specifiable)
ES: ADDR16
Label or 16-bit immediate data (higher 4-bit addresses are specified by the ES register)
Figure 3-31. Example of ADDR16
FFFFFH
OP code
Low Addr.
Target memory
High Addr.
F0000H
Memory
Figure 3-32. Example of ES:ADDR16
FFFFFH
ES
OP code
Low Addr.
Target memory
High Addr.
00000H
Memory
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3.4.4 Short direct addressing
[Function]
Short direct addressing directly specifies the target addresses using 8-bit data in the instruction word. This type of
addressing is applied only to the space from FFE20H to FFF1FH.
[Operand format]
Identifier
SADDR
Description
Label, FFE20H to FFF1FH immediate data, or 0FE20H to 0FF1FH immediate data
(only the space from FFE20H to FFF1FH is specifiable)
SADDRP
Label, FFE20H to FFF1FH immediate data, or 0FE20H to 0FF1FH immediate data (even address only)
(only the space from FFE20H to FFF1FH is specifiable)
Figure 3-33. Outline of Short Direct Addressing
OP code
FFF1FH
saddr
saddr
FFE20H
Memory
Remark SADDR and SADDRP are used to describe the values of addresses FE20H to FF1FH with 16-bit immediate
data (higher 4 bits of actual address are omitted), and the values of addresses FFE20H to FFF1FH with 20bit immediate data.
Regardless of whether SADDR or SADDRP is used, addresses within the space from FFE20H to FFF1FH
are specified for the memory.
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3.4.5 SFR addressing
[Function]
SFR addressing directly specifies the target SFR addresses using 8-bit data in the instruction word. This type of
addressing is applied only to the space from FFF00H to FFFFFH.
[Operand format]
Identifier
SFR
SFRP
Description
SFR name
16-bit-manipulatable SFR name (even address only)
Figure 3-34. Outline of SFR Addressing
FFFFFH
OP code
SFR
FFF00H
SFR
Memory
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3.4.6 Register indirect addressing
[Function]
Register indirect addressing directly specifies the target addresses using the contents of the register pair specified
with the instruction word as an operand address.
[Operand format]
Identifier
Description
−
[DE], [HL] (only the space from F0000H to FFFFFH is specifiable)
−
ES:[DE], ES:[HL] (higher 4-bit addresses are specified by the ES register)
Figure 3-35. Example of [DE], [HL]
FFFFFH
OP code
rp
Target memory
F0000H
Memory
Figure 3-36. Example of ES:[DE], ES:[HL]
FFFFFH
ES
OP code
rp
Target memory
00000H
Memory
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3.4.7 Based addressing
[Function]
Based addressing uses the contents of a register pair specified with the instruction word as a base address, and 8bit immediate data or 16-bit immediate data as offset data. The sum of these values is used to specify the target
address.
[Operand format]
Identifier
Description
−
[HL + byte], [DE + byte], [SP + byte] (only the space from F0000H to FFFFFH is specifiable)
−
word[B], word[C] (only the space from F0000H to FFFFFH is specifiable)
−
word[BC] (only the space from F0000H to FFFFFH is specifiable)
−
ES:[HL + byte], ES:[DE + byte] (higher 4-bit addresses are specified by the ES register)
−
ES:word[B], ES:word[C] (higher 4-bit addresses are specified by the ES register)
−
ES:word[BC] (higher 4-bit addresses are specified by the ES register)
Figure 3-37. Example of [SP+byte]
FFFFFH
SP
Target memory
F0000H
OP code
byte
Memory
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Figure 3-38. Example of [HL + byte], [DE + byte]
FFFFFH
rp (HL/DE)
Target memory
F0000H
OP code
byte
Memory
Figure 3-39. Example of word[B], word[C]
FFFFFH
r (B/C)
Target memory
F0000H
OP code
Low Addr.
High Addr.
Memory
Figure 3-40. Example of word[BC]
FFFFFH
rp (BC)
Target memory
F0000H
OP code
Low Addr.
High Addr.
Memory
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Figure 3-41. Example of ES:[HL + byte], ES:[DE + byte]
FFFFFH
ES
rp (HL/DE)
Target memory
OP code
00000H
byte
Memory
Figure 3-42. Example of ES:word[B], ES:word[C]
FFFFFH
ES
r (B/C)
Target memory
OP code
00000H
Low Addr.
Memory
High Addr.
Figure 3-43. Example of ES:word[BC]
FFFFFH
ES
rp (BC)
Target memory
OP code
00000H
Low Addr.
Memory
High Addr.
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3.4.8 Based indexed addressing
[Function]
Based indexed addressing uses the contents of a register pair specified with the instruction word as the base
address, and the content of the B register or C register similarly specified with the instruction word as offset address.
The sum of these values is used to specify the target address.
[Operand format]
Identifier
Description
−
[HL+B], [HL+C] (only the space from F0000H to FFFFFH is specifiable)
−
ES:[HL+B], ES:[HL+C] (higher 4-bit addresses are specified by the ES register)
Figure 3-44. Example of [HL+B], [HL+C]
FFFFFH
OP code
rp (HL)
Target memory
F0000H
r (B/C)
Memory
Figure 3-45. Example of ES:[HL+B], ES:[HL+C]
FFFFFH
OP code
ES
rp (HL)
Target memory
00000H
r (B/C)
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3.4.9 Stack addressing
[Function]
The stack area is indirectly addressed with the stack pointer (SP) contents.
This addressing is automatically
employed when the PUSH, POP, subroutine call, and return instructions are executed or the register is
saved/restored upon generation of an interrupt request.
Stack addressing is applied only to the internal RAM area.
[Operand format]
Identifier
−
Description
PUSH AX/BC/DE/HL
POP AX/BC/DE/HL
CALL/CALLT
RET
BRK
RETB
(Interrupt request generated)
RETI
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CHAPTER 4 PORT FUNCTIONS
4.1 Port Functions
Pin I/O buffer power supplies depend on the product. The relationship between these power supplies and the pins is
shown below.
Table 4-1. Pin I/O Buffer Power Supplies
(1) 30-pin, 32-pin, 36-pin, 40-pin, 44-pin, 48-pin, 52-pin products
Power Supply
VDD
Corresponding Pins
All pins
(2) 64-pin products
Power Supply
Corresponding Pins
EVDD0
Port pins other than P20 to P27, P121 to P124 and P137
VDD
• P20 to P27, P121 to P124, and P137
• Pins other than port pins
(3) 80-pin products
Power Supply
Corresponding Pins
EVDD0
Port pins other than P20 to P27, P121 to P124, P137, and P150 to
P153
VDD
• P20 to P27, P121 to P124, P137, and P150 to P153
• Pins other than port pins
(4) 100-pin products
Power Supply
Corresponding Pins
EVDD0, EVDD1
Port pins other than P20 to P27, P121 to P124, P137, and P150 to
P156
VDD
• P20 to P27, P121 to P124, P137, and P150 to P156
• Pins other than port pins
The RL78/G14 microcontrollers are provided with digital I/O ports, which enable variety of control operations.
In addition to the function as digital I/O ports, these ports have several alternate functions. For details of the alternate
functions, see CHAPTER 2 PIN FUNCTIONS.
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4.2 Port Configuration
Ports include the following hardware.
Table 4-2. Port Configuration
Item
Control registers
Configuration
Port mode registers (PM0 to PM8, PM10 to PM12, PM14, PM15)
Port registers (P0 to P8, P10 to P15)
Pull-up resistor option registers (PU0, PU1, PU3 to PU8, PU10 to PU12, PU14)
Port input mode registers (PIM0, PIM1, PIM3 to PIM5, PIM8, PIM14)
Port output mode registers (POM0, POM1, POM3 to POM5, POM7, POM8, POM14)
Port mode control registers (PMC0, PMC1, PMC10, PMC12, PMC14)
A/D port configuration register (ADPC)
Peripheral I/O redirection registers (PIOR0, PIOR1)
Global digital input disable register (GDIDIS)
Port
• 30-pin products
Total: 26 (CMOS I/O: 21, CMOS input: 3, N-ch open-drain I/O: 2)
• 32-pin products
Total: 28 (CMOS I/O: 22, CMOS input: 3, N-ch open-drain I/O: 3)
• 36-pin products
Total: 32 (CMOS I/O: 26, CMOS input: 3, N-ch open-drain I/O: 3)
• 40-pin products
Total: 36 (CMOS I/O: 28, CMOS input: 5, N-ch open-drain I/O: 3)
• 44-pin products
Total: 40 (CMOS I/O: 31, CMOS input: 5, N-ch open-drain I/O: 4)
• 48-pin products
Total: 44 (CMOS I/O: 34, CMOS input: 5, CMOS output: 1, N-ch open-drain I/O: 4)
• 52-pin products
Total: 48 (CMOS I/O: 38, CMOS input: 5, CMOS output: 1, N-ch open-drain I/O: 4)
• 64-pin products
Total: 58 (CMOS I/O: 48, CMOS input: 5, CMOS output: 1, N-ch open-drain I/O: 4)
• 80-pin products
Total: 74 (CMOS I/O: 64, CMOS input: 5, CMOS output: 1, N-ch open-drain I/O: 4)
• 100-pin products
Total: 92 (CMOS I/O: 82, CMOS input: 5, CMOS output: 1, N-ch open-drain I/O: 4)
Pull-up resistor
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• 30-pin products
Total: 17
• 32-pin products
Total: 18
• 36-pin products
Total: 20
• 40-pin products
Total: 21
• 44-pin products
Total: 23
• 48-pin products
Total: 26
• 52-pin products
Total: 30
• 64-pin products
Total: 40
• 80-pin products
Total: 52
• 100-pin products
Total: 67
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Caution Most of the following descriptions in this chapter use the 100-pin products with the 00H setting in
peripheral I/O redirection register 0, 1 (PIOR0, 1) as an example.
4.2.1 Port 0
Port 0 is an I/O port with an output latch. Port 0 can be set to the input mode or output mode in 1-bit units using port
mode register 0 (PM0). When the P00 to P06 pins are used as an input port, use of an on-chip pull-up resistor can be
specified in 1-bit units by pull-up resistor option register 0 (PU0).
Input to the P01, P03 and P04 pins can be specified through a normal input buffer or a TTL input buffer in 1-bit units
using port input mode register 0 (PIM0).
Output from the P00, and P02 to P04 pins can be specified as N-ch open-drain output (EVDD0 tolerance) in 1-bit units
using port output mode register 0 (POM0).
Input to the P00 to P03 pins can be specified as analog input or digital input in 1-bit units, using port mode control
register 0 (PMC0).
This port can also be used for timer I/O, A/D converter analog input, serial interface data I/O, and clock I/O.
<R>
When reset signal is generated, the following configuration will be set.
· P00 and P01 pins of the 30 and 32-pin products ··· Analog input
· P00, P01 and P04 to P06 pins of the other products ··· Input mode
· P02 and P03 pins of the other products ··· Analog input
Table 4-3. Settings of Registers When Using Port 0
<R>
Pin Name
Name
P00
PM0×
PIM0×
POM0×
1
−
×
Alternate Function Setting
Output
0
0
Input
1
1
Output
0
0
0
0
0
1
0
−
0
0
1
×
0
Note 1
Note 1
×
TxD1 output = 1
Note 3
Input
Output
1
−
0
0
P03
Input
1
1
Output
P04
Input
Output
P05, P06
Notes 1.
2.
0
0
1
×
×
0
0
1
0
×
0
×
0
0
×
1
1
0
×
1
1
×
0
×
0
1
−
0
×
Input
1
−
Output
0
0
0
0
0
CMOS output
Note 1
N-ch O.D. output
Note 1
×
Note 1
×
Note 1
TO00 output = 0
CMOS input
TTL input
Note 4
TRJIO01 output = 1
P02
Remark
I/O
Input
P01
PMC0×
Note 2
Note 2
Note 5
×
SO10/TxD1 output = 1
Note 6
Note 2
N-ch O.D. output
Note 2
×
Note 2
×
Note 2
SDA10 output = 1
CMOS input
TTL input
Note 6
Note 2
−
CMOS output
CMOS output
N-ch O.D. output
×
CMOS input
×
SCK10/SCL10 output = 1
TTL input
Note 6
CMOS output
N-ch O.D. output
−
−
30-, 32-pin products only
52-, 64-, 80-, 100-pin products only
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Notes 3.
To use a pin multiplexed with the serial array unit function as a general-purpose port in 30- to 48-pin
products, set the SOmn bit in serial output register m (SOm), the SOEmn bit in serial output enable
register m (SOEm), and the SEmn bit in serial channel enable status register m (SEm) for the
corresponding unit channel to the default value. (mn = 02)
4.
To use a pin multiplexed with the timer output function of the timer array unit as a general-purpose port, set
the TOmn bit in timer output register m (TOm) and the TOEmn bit in timer output enable register m
(TOEm) for the corresponding unit channel to the default status. (m = 0, n = 0)
5.
To use a pin multiplexed with the timer I/O function of timer RJ as a general-purpose port, set bits TMOD2
to TMOD0 in timer RJ mode register 0 (TRJMR0) to the default value or a value other than 001B.
6.
To use a pin multiplexed with the serial array unit function as a general-purpose port in 52- to 100-pin
products, set the SOmn bit in serial output register m (SOm), the SOEmn bit in serial output enable
register m (SOEm), and the SEmn bit in serial channel enable status register m (SEm) for the
corresponding unit channel to the default value. (mn = 02)
Remark
×:
don’t care
PM0×:
Port mode register 0
PIM0×:
Port input mode register 0
POM0×:
Port output mode register 0
PMC0×:
Port mode control register 0
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For example, figures 4-1 to 4-7 show block diagrams of port 0 for 100-pin products when PIOR0 = 00H, PIOR1 = 00H.
Figure 4-1. Block Diagram of P00
EVDD
WRPU
PU0
PU00
P-ch
Alternate
function
Selector
Internal bus
RD
WRPORT
P0
Output latch
(P00)
P00/TI00/
TRGCLKA
WRPOM
POM0
POM00
WRPM
PM0
PM00
WRPMS
PMS
<R>
PMS0
P0:
Port register 0
PU0:
Pull-up resistor option register 0
PM0:
Port mode register 0
POM0: Port output mode register 0
PMS:
Port mode select register
RD:
Read signal
WR××: Write signal
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Figure 4-2. Block Diagram of P01
WRPIM
PIM0
PIM01
EVDD
WRPU
PU0
PU01
P-ch
Alternate
function
CMOS
Selector
Internal bus
RD
TTL
WRPORT
P0
Output latch
(P01)
WRPM
PM0
P01/TO00/
TRGCLKB/
TRJIO0
PM01
WRPMS
PMS
<R>
PMS0
Alternate
function
(TO00)
Alternate
function
(TRJIO0)
P0:
Port register 0
PU0:
Pull-up resistor option register 0
PM0:
Port mode register 0
PIM0:
Port input mode register 0
PMS:
Port mode select register
RD:
Read signal
WR××: Write signal
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Figure 4-3. Block Diagram of P02
EVDD
WRPU
PU0
PU02
P-ch
WRPMC
PMC0
PMC02
Internal bus
Selector
RD
WRPORT
P0
Output latch
(P02)
P02/SO10/TxD1/ANI17
WRPOM
POM0
POM02
WRPM
PM0
PM02
WRPMS
PMS
<R>
PMS0
A/D converter
Alternate
function
(SO10/TxD1)
P0:
Port register 0
PU0:
Pull-up resistor option register 0
PM0:
Port mode register 0
POM0: Port output mode register 0
PMC0: Port mode control register 0
PMS:
Port mode select register
RD:
Read signal
WR××: Write signal
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Figure 4-4. Block Diagram of P03
WRPIM
PIM0
PIM03
EVDD
WRPU
PU0
PU03
P-ch
WRPMC
PMC0
PMC03
PMC03
CMOS
Selector
Internal bus
RD
TTL
WRPORT
P0
Output latch
(P03)
P03/SI10/RxD1/
SDA10/ANI16
WRPOM
POM0
POM03
WRPM
PM0
PM03
WRPMS
PMS
<R>
PMS0
A/D converter
Alternate
function
(SDA10)
P0:
Port register 0
PU0:
Pull-up resistor option register 0
PM0:
Port mode register 0
PIM0:
Port input mode register 0
POM0: Port output mode register 0
PMC0: Port mode control register 0
PMS:
Port mode select register
RD:
Read signal
WR××: Write signal
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Figure 4-5. Block Diagram of P04
WRPIM
PIM0
PIM04
EVDD
WRPU
PU0
PU04
P-ch
Alternate
function
CMOS
Selector
Internal bus
RD
TTL
WRPORT
P0
Output latch
(P04)
P04/SCK10/SCL10
WRPOM
POM0
POM04
WRPM
PM0
PM04
WRPMS
PMS
<R>
PMS0
Alternate
function
(SCK10/SCL10)
P0:
Port register 0
PU0:
Pull-up resistor option register 0
PM0:
Port mode register 0
PIM0:
Port input mode register 0
POM0: Port output mode register 0
PMS:
Port mode select register
RD:
Read signal
WR××: Write signal
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Figure 4-6. Block Diagram of P05
EVDD
WRPU
PU0
PU05
P-ch
Selector
Internal bus
RD
WRPORT
P0
Output latch
(P05)
P05
WRPM
PM0
PM05
WRPMS
PMS
<R>
PMS0
P0:
Port register 0
PU0:
Pull-up resistor option register 0
PM0:
Port mode register 0
PMS:
Port mode select register
RD:
Read signal
WR××: Write signal
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Figure 4-7. Block Diagram of P06
EVDD
WRPU
PU0
PU06
P-ch
Selector
Internal bus
RD
WRPORT
P0
Output latch
(P06)
P06
WRPM
PM0
PM06
WRPMS
PMS
<R>
PMS0
P0:
Port register 0
PU0:
Pull-up resistor option register 0
PM0:
Port mode register 0
PMS:
Port mode select register
RD:
Read signal
WR××: Write signal
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4.2.2 Port 1
Port 1 is an I/O port with an output latch. Port 1 can be set to the input mode or output mode in 1-bit units using port
mode register 1 (PM1). When the P10 to P17 pins are used as an input port, use of an on-chip pull-up resistor can be
specified in 1-bit units by pull-up resistor option register 1 (PU1).
Input to the P10 and P14 to P17 pins can be specified through a normal input buffer or a TTL input buffer in 1-bit units
using port input mode register 1 (PIM1).
Output from the P10, P11, P13 to P15 and P17 pins can be specified as N-ch open-drain output (EVDD0 tolerance) in 1bit units using port output mode register 1 (POM1).
Only in the products with 96 KB or more code flash memory, to use the P12, P13, P16, or P17 pin as analog input,
specify either digital or analog using port mode control register 1 (can be specified in 1-bit units).
This port can also be used for serial interface data I/O, clock I/O, timer I/O, external interrupt request input, comparator
reference voltage input, and comparator analog voltage input.
Reset signal generation sets port 1 to input mode.
Table 4-4. Settings of Registers When Using Port 1 (1/2)
<R>
Pin Name
Name
P10
PM1×
PIM1×
POM1×
PMC1×
1
0
×
−
1
1
×
Input
0
×
×
1
Input
1
−
×
Output
0
Input
1
Output
0
−
×
TTL input
SCK11/SCL11 output = 1
TRDIOD1 output = 0
−
SDA11 output = 1
1
TRDIOC1 output = 0
0
0
Note 1
Note 1
Input
Output
1
−
0
0
0
P14
Input
Output
×
1
0
0
0
Note 1
Note 1
Note 1
−
SO11 output = 1
Input
TRDIOA1 output = 0
1
×
0
×
0
SDA20 output = 1
0
×
1
TRDIOD0 output = 0
Output
×
1
1
×
0
×
0
×
Note 4
Note 3
×
N-ch O.D. output
TTL input
Note 4
CMOS output
Note 3
Note 5
N-ch O.D. output
)
×
CMOS input
×
TTL input
Note 6
0
PCLBUZ1 output = 0
1
SCK20/SCL20 output = 1
TRDIOB0 output = 0
(SDAA0 output = 0
CMOS output
CMOS input
×
−
N-ch O.D. output
Note 3
TxD2/SO20 output = 1
1
0
CMOS output
Note 3
×
×
1
N-ch O.D. output
Note 4
(SCLA0 output = 0
P15
CMOS output
×
0
1
Note 3
Note 4
0
−
Note 2
×
TRDIOB1 output = 0
P13
Remark
CMOS input
×
0
0
0
P12
Note 9
I/O
Output
P11
Alternate Function Setting
CMOS output
Note 2
Note 3
Note 5
N-ch O.D. output
)
(Notes and Remark are listed on the next page.)
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Table 4-4. Settings of Registers When Using Port 1 (2/2)
<R>
Pin Name
Name
PM1×
PIM1×
POM1×
1
0
−
PMC1×
Alternate Function Setting
Remark
Note 1
×
CMOS input
Note 1
×
I/O
P16
Input
1
Output
0
0
0
1
×
0
Note 1
TO01 output = 0
TTL input
Note 7
TRDIOC0 output = 0
P17
Input
1
Output
0
×
0
0
1
1
×
0
×
0
0
0
×
1
0
Note 1
×
Note 1
×
Note 1
TO02 output = 0
Note 1
Note 3
CMOS input
TTL input
Note 7
TRDIOA0 output = 0
Note 3
(SO00/TxD0 output = 1
Notes 1.
CMOS output
Note 8
)
N-ch O.D. output
Only for products with 96 KB or more code flash memory.
2.
To use a pin multiplexed with the serial array unit function as a general-purpose port, set the CKOmn bit in
serial output register m (SOm), the SOEmn bit in serial output enable register m (SOEm), and the SEmn
bit in serial channel enable status register m (SEm) for the corresponding unit channel to the default value.
(mn = 03, 10)
3.
To use a pin multiplexed with the timer RD function as a general-purpose port, set the output control bit in
timer RD output master enable register 1 (TRDOER1) for the corresponding TRDIOij pin to the default
value. (i = A, B, C, D; j = 0, 1)
4.
To use a pin multiplexed with the serial array unit function as a general-purpose port, set the SOmn bit in
serial output register m (SOm), the SOEmn bit in serial output enable register m (SOEm), and the SEmn
bit in serial channel enable status register m (SEm) for the corresponding unit channel to the default value.
(mn = 03, 10)
5
To use a pin multiplexed with the serial interface IICA function as a general-purpose port when the PIOR02
bit in peripheral I/O redirection register 0 (PIOR0) is 1, stop the operation of the corresponding serial
interface IICA.
6.
To use a pin multiplexed with the clock/buzzer output function as a general-purpose port in 30- to 52-pin
products, set the PCLOEi bit in clock output select register i (CKSi) to the default status. (i = 1)
7.
To use a pin multiplexed with the timer output function of the timer array unit as a general-purpose port, set
the TOmn bit in timer output register m (TOm) and the TOEmn bit in timer output enable register m
(TOEm) for the corresponding unit channel to the default status. (m = 0, n = 1, 2)
8.
To use a pin multiplexed with the serial array unit function as a general-purpose port when the PIOR01 bit
in peripheral I/O redirection register 0 (PIOR0) is 1, set the SOmn bit in serial output register m (SOm), the
SOEmn bit in serial output enable register m (SOEm), and the SEmn bit in serial channel enable status
register m (SEm) for the corresponding unit channel to the default value. (mn = 00)
9.
Functions in parentheses in the above table can be assigned via settings in the peripheral I/O redirection
registers 0, 1 (PIOR0, 1).
Remark
×:
don’t care
PM1×:
Port mode register 1
PIM1×:
Port input mode register 1
POM1×:
Port output mode register 1
PMC1×:
Port mode control register 1
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For example, figures 4-8 to 4-15 show block diagrams of port 1 for 100-pin products when PIOR0 = 00H, PIOR1 = 00H.
Figure 4-8. Block Diagram of P10
WRPIM
PIM1
PIM10
EVDD
WRPU
PU1
PU10
P-ch
Alternate
function
CMOS
Selector
Internal bus
RD
TTL
WRPORT
P1
Output latch
(P10)
WRPOM
POM1
P10/SCK11/
SCL11/
TRDIOD1
POM10
WRPM
PM1
PM10
WRPMS
PMS
<R>
PMS0
Alternate
function
(SCK11/SCL11)
Alternate
function
(TRDIOD1)
P1:
Port register 1
PU1:
Pull-up resistor option register 1
PM1:
Port mode register 1
PIM1:
Port input mode register 1
POM1: Port output mode register 1
PMS:
Port mode select register
RD:
Read signal
WR××: Write signal
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Figure 4-9. Block Diagram of P11
EVDD
WRPU
PU1
PU11
P-ch
Alternate
function
Selector
Internal bus
RD
WRPORT
P1
Output latch
(P11)
WRPOM
P11/SI11/SDA11/
TRDIOC1
POM1
POM11
WRPM
PM1
PM11
WRPMS
PMS
<R>
PMS0
Alternate
function
(SDA11)
Alternate
function
(TRDIOC1)
P1:
Port register 1
PU1:
Pull-up resistor option register 1
PM1:
Port mode register 1
POM1: Port output mode register 1
PMS:
Port mode select register
RD:
Read signal
WR××: Write signal
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Figure 4-10. Block Diagram of P12
EVDD
WRPU
PU1
PU12
P-ch
WRPMC
PMC1
PMC12
Selector
Internal bus
RD
WRPORT
P1
Output latch
(P12)
P12/SO11/
TRDIOB1/IVREF1
WRPM
PM1
PM12
WRPMS
PMS
<R>
PMS0
Alternate
function
(SO11)
Comparator reference
voltage input
Alternate
function
(TRDIOB1)
P1:
Port register 1
PU1:
Pull-up resistor option register 1
PM1:
Port mode register 1
PMC1: Port mode control register 1
PMS:
Port mode select register
RD:
Read signal
WR××: Write signal
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Figure 4-11. Block Diagram of P13
EVDD
WRPU
PU1
PU13
P-ch
WRPMC
PMC1
PMC13
Selector
Internal bus
RD
WRPORT
P1
Output latch
(P13)
P13/TxD2/SO10/
TRDIOA1/IVCMP1
WRPOM
POM1
POM13
WRPM
PM1
PM13
WRPMS
PMS
<R>
PMS0
Alternate
function
(TxD2/SO10)
Comparator analog
voltage input
Alternate
function
(TRDIOA1)
P1:
Port register 1
PU1:
Pull-up resistor option register 1
PM1:
Port mode register 1
POM1: Port output mode register 1
PMC1: Port mode control register 1
PMS:
Port mode select register
RD:
Read signal
WR××: Write signal
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Figure 4-12. Block Diagram of P14
WRPIM
PIM1
PIM14
EVDD
WRPU
PU1
PU14
P-ch
Alternate
function
CMOS
Internal bus
Selector
RD
TTL
WRPORT
P1
Output latch
(P14)
WRPOM
P14/SI20/
RxD2/SDA20/
TRDIOD0
POM1
POM14
WRPM
PM1
PM14
WRPMS
PMS
<R>
PMS0
Alternate
function
(SDA20)
Alternate
function
(TRDIOD0)
P1:
Port register 1
PU1:
Pull-up resistor option register 1
PM1:
Port mode register 1
PIM1:
Port input mode register 1
POM1: Port output mode register 1
PMS:
Port mode select register
RD:
Read signal
WR××: Write signal
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Figure 4-13. Block Diagram of P15
WRPIM
PIM1
PIM15
EVDD
WRPU
PU1
PU15
P-ch
Alternate
function
CMOS
Selector
RD
TTL
Internal bus
WRPORT
P1
Output latch
(P15)
WRPOM
P15/SCK20/
SCL20/
TRDIOB0
POM1
POM15
WRPM
PM1
PM15
WRPMS
PMS
<R>
PMS0
Alternate
function
(SCK20/SCL20)
Alternate
function
(TRDIOB0)
P1:
Port register 1
PU1:
Pull-up resistor option register 1
PM1:
Port mode register 1
PIM1:
Port input mode register 1
POM1: Port output mode register 1
PMS:
Port mode select register
RD:
Read signal
WR××: Write signal
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Figure 4-14. Block Diagram of P16
WRPIM
PIM1
PIM16
EVDD
WRPU
PU1
PU16
P-ch
WRPMC
PMC1
PMC16
CMOS
RD
Selector
Internal bus
Alternate
function
TTL
WRPORT
P1
P16/TI01/
TO01/INTP5/
TRDIOC0/IVREF0
Output latch
(P16)
WRPM
PM1
PM16
WRPMS
PMS
<R>
PMS0
Comparator reference
voltage input
Alternate
function
(TO01)
Alternate
function
(TRDIOC0)
P1:
Port register 1
PU1:
Pull-up resistor option register 1
PM1:
Port mode register 1
PIM1:
Port input mode register 1
PMC1: Port mode control register 1
PMS:
Port mode select register
RD:
Read signal
WR××: Write signal
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Figure 4-15. Block Diagram of P17
WRPIM
PIM1
PIM17
EVDD
WRPU
PU1
PU17
P-ch
WRPMC
PMC1
PMC17
Alternate
function
CMOS
Selector
Internal bus
RD
TTL
WRPORT
P1
P17/TI02/TO02/
TRDIOA0/
TRDCLK0/IVCMP0
Output latch
(P17)
WRPOM
POM1
POM17
WRPM
PM1
PM17
WRPMS
PMS
<R>
PMS0
Comparator analog
voltage input
Alternate
function
(TO02)
Alternate
function
(TRDIOA0)
P1:
Port register 1
PU1:
Pull-up resistor option register 1
PM1:
Port mode register 1
PIM1:
Port input mode register 1
POM1: Port output mode register 1
PMC1: Port mode control register 1
PMS:
Port mode select register
RD:
Read signal
WR××: Write signal
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4.2.3 Port 2
Port 2 is an I/O port with an output latch. Port 2 can be set to the input mode or output mode in 1-bit units using port
mode register 2 (PM2).
This port can also be used for A/D converter analog input, (+side and – side) reference voltage input, and D/A
converter output.
To use P20/ANI0, P21/ANI1, P22/ANI2/ANO0, P23/ANI3/ANO1, P24/ANI4 to P27/ANI7 as digital input pins, set them
in the digital I/O mode by using the A/D port configuration register (ADPC) and in the input mode by using the PM2
register. Use these pins starting from the upper bit.
To use P20/ANI0, P21/ANI1, P22/ANI2/ANO0, P23/ANI3/ANO1, P24/ANI4-P27/ANI7 as digital output pins, set them in
the digital I/O mode by using the ADPC register and in the output mode by using the PM2 register.
To use P20/ANI0, P21/ANI1, P22/ANI2/ANO0, P23/ANI3/ANO1, P24/ANI4-P27/ANI7 as analog I/O pins, set them in
the analog I/O mode by using the A/D port configuration register (ADPC) and in the input mode by using the PM2 register.
Use these pins starting from the lower bit.
<R>
Table 4-5. Settings of Registers When Using Port 2
PM2×
ADPC
Alternate Function Setting
Remark
Input
1
01 to n+1H
−
To use P2n as a port, use these
Output
0
01 to n+1H
Pin Name
Name
P2n
I/O
pins from a higher bit.
Remarks 1. PM2×: Port mode register 2
ADPC: A/D port configuration register
2. n = 0 to 7
<R>
Table 4-6. Setting Functions of P20/ANI0 to P27/ANI7 Pins (64 KB or less code flash memory products)
ADPC Register
Digital I/O selection
Analog input selection
PM2 Register
ADS Register
P20/ANI0 to P27/ANI7 Pins
Input mode
−
Digital input
Output mode
−
Digital output
Input mode
Output mode
Selects ANI.
Analog input (to be converted)
Does not select ANI.
Analog input (not to be converted)
Selects ANI.
Setting prohibited
Does not select ANI.
All P20/ANI0 to P27/ANI7 are set in the analog input mode when the reset signal is generated.
<R> Table 4-7.
Setting Functions of P20/ANI0, P21/ANI1, P24/ANI4 to P27/ANI7 Pins (96 KB or more code flash
memory products)
ADPC Register
PM2 Register
ADS Register
P20/ANI0, P21/ANI1,
P24/ANI4 to P27/ANI7 Pins
Digital I/O selection
Analog input selection
Input mode
−
Digital input
Output mode
−
Digital output
Input mode
Output mode
Selects ANI.
Analog input (to be converted)
Does not select ANI.
Analog input (not to be converted)
Selects ANI.
Setting prohibited
Does not select ANI.
All P20/ANI0, P21/ANI1, P24/ANI4 to P27/ANI7 are set in the analog input mode when the reset signal is generated.
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<R> Table 4-8.
Setting Functions of P22/ANI2/ANO0, P23/ANI3/ANO1 Pins (96 KB or more code flash memory
products)
ADPC Register
PM2 Register
DAM Register
ADS Register
P22/ANI2/ANO0,
P23/ANI3/ANO1 Pins
Digital I/O selection
Analog input
Input mode
−
−
Digital input
Output mode
−
−
Digital output
Input mode
selection
Enables D/A
Selects ANI.
Setting prohibited
conversion
Does not select ANI.
Analog output
Selects ANI.
Analog input (to be
operation
Stops D/A
converted)
conversion
operation
Does not select ANI.
Analog input (not to be
Enables D/A
Selects ANI.
Setting prohibited
conversion
Does not select ANI.
converted)
Output mode
operation
Stops D/A
conversion
Selects ANI.
Does not select ANI.
operation
All P22/ANI2/ANO0, P23/ANI3/ANO1 are set in the analog I/O mode when the reset signal is generated.
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For example, figures 4-16, 4-17 show block diagrams of port 2 for 100-pin products.
<R>
Figure 4-16. Block Diagram of P20, P21, P24 to P27
WRADPC
ADPC
0:Analog input
1:Digital I/O
ADPC3 to ADPC0
Internal bus
Selector
RD
WRPORT
P2
P20/ANI0/AVREFP,
P21/ANI1/AVREFM,
P24/ANI4-P27/ANI7
Output latch
(P20, P21, P24 to P27)
WRPM
PM2
PM20, PM21,
PM24 to PM27
WRPMS
PMS
PMS0
P2:
Port register 2
PM2:
Port mode register 2
PMS:
Port mode select register
A/D converter
RD:
Read signal
WR××: Write signal
Figure 4-17. Block Diagram of P22 and P23
<R>
WRADPC
ADPC
0:Analog input
1:Digital I/O
ADPC3 to ADPC0
Selector
Internal bus
RD
WRPORT
P2
Output latch
(P22, P23)
P22/ANI2/ANO0,
P23/ANI3/ANO1
WRPM
PM2
PM22, PM23
WRPMS
PMS
PMS0
A/D converter
D/A converter
P2:
Port register 2
PM2:
Port mode register 2
PMS:
Port mode select register
RD:
Read signal
WR××: Write signal
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4.2.4 Port 3
Port 3 is an I/O port with an output latch. Port 3 can be set to the input mode or output mode in 1-bit units using port
mode register 3 (PM3). When the P30 and P31 pins are used as an input port, use of an on-chip pull-up resistor can be
specified in 1-bit units by pull-up resistor option register 3 (PU3).
Input to the P30 pin can be specified through a normal input buffer or a TTL input buffer in 1-bit units using port input
mode register 3 (PIM3).
Output from the P30 pin can be specified as N-ch open-drain output (EVDD0 tolerance) in 1-bit units using port output
mode register 3 (POM3).
This port can also be used for external interrupt request input, real-time clock correction clock output, serial interface
clock I/O, and timer I/O.
Reset signal generation sets port 3 to input mode.
Table 4-9. Settings of Registers When Using Port 3
<R>
Pin Name
Name
P30
PM3×
PIM3×
POM3×
1
0
×
×
1
1
×
×
Alternate Function Setting
Input
0
0
×
×
0
1
CMOS input
TTL input
RTC1HZ output = 0
Input
Output
1
0
−
Note 1
SCK00/SCL00 output = 0
TRJO0 output = 0
−
CMOS output
Note 2
Note 3
TO03 output = 0
N-ch O.D.
output
×
CMOS input
Note 4
PCLBUZ0 output = 0
(PCLBUZ0 output = 0
(TRJIO0 output = 0
Notes 1.
Remark
I/O
Output
P31
Note 8
Note 5
Note 6
Note 7
)
)
To use a pin multiplexed with the output (1 Hz) function of the RTC1HZ pin as a general-purpose port in
40- to 100-pin products, set the RCLOE1 bit in real-time clock control register 0 (RTCC0) to the default
value.
2.
To use a pin multiplexed with the serial array unit function as a general-purpose port, set the CKOmn bit in
serial output register m (SOm), the SOEmn bit in serial output enable register m (SOEm), and the SEmn
bit in serial channel enable status register m (SEm) for the corresponding unit channel to the default value.
(mn = 00)
3.
To use a pin multiplexed with the output function of timer RJ as a general-purpose port, set bit 2 (TOENA)
in timer RJ I/O control register 0 (TRJIOC0) to the default value.
4.
To use a pin multiplexed with the timer output function of the timer array unit as a general-purpose port, set
the TOmn bit in timer output register m (TOm) and the TOEmn bit in timer output enable register m
(TOEm) for the corresponding unit channel to the default status. (m = 0, n = 4)
5.
To use a pin multiplexed with the clock/buzzer output function as a general-purpose port in 30- to 44-pin
products, set the PCLOEi bit in clock output select register i (CKSi) to the default value. (i = 0)
6.
To use a pin multiplexed with the clock/buzzer output function as a general-purpose port in 48- to 100-pin
products when the PIOR03 bit in peripheral I/O redirection register 0 (PIOR0) is 1, set the PCLOEi bit in
clock output select register i (CKSi) to the default value. (i = 0)
7.
To use a pin multiplexed with the timer I/O function of timer RJ as a general-purpose port when bits
PIOR11 and PIOR10 in peripheral I/O redirection register 1 (PIOR1) are 01B, set bits TMOD2 to TMOD0
in timer RJ mode register 0 (TRJMR0) to the default value or a value other than 001B.
8.
Functions in parentheses in the above table can be assigned via settings in the peripheral I/O redirection
registers 0, 1 (PIOR0, 1).
(Remark is listed on the next page)
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Remark
CHAPTER 4 PORT FUNCTIONS
×:
don’t care
PM3×:
Port mode register 3
PIM3×:
Port input mode register 3
POM3×:
Port output mode register 3
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For example, figures 4-18, 4-19 show block diagrams of port 3 for 100-pin products when PIOR1 = 00H.
Figure 4-18. Block Diagram of P30
WRPIM
PIM3
PIM30
EVDD
WRPU
PU3
PU30
P-ch
Alternate
function
CMOS
Selector
RD
TTL
WRPORT
Internal bus
P3
Output latch
(P30)
WRPOM
P30/RTC1HZ/
INTP3/SCK00/
SCL00/TRJO0
POM3
POM30
WRPM
PM3
PM30
WRPMS
PMS
<R>
PMS0
Alternate
function
(SCK00/SCL00)
Alternate
function
(RTC1HZ)
Alternate
function
(TRJO0)
P3:
Port register 3
PU3:
Pull-up resistor option register 3
PM3:
Port mode register 3
PIM3:
Port input mode register 3
POM3: Port output mode register 3
PMS:
Port mode select register
RD:
Read signal
WR××: Write signal
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Figure 4-19. Block Diagram of P31
EVDD
WRPU
PU3
PU31
P-ch
Alternate
function
Internal bus
Selector
RD
WRPORT
P3
Output latch
(P31)
P31/TI03/TO03/INTP4
WRPM
PM3
PM31
WRPMS
PMS
<R>
PMS0
Alternate
function
(TO03)
P3:
Port register 3
PU3:
Pull-up resistor option register 3
PM3:
Port mode register 3
PMS:
Port mode select register
RD:
Read signal
WR××: Write signal
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4.2.5 Port 4
Port 4 is an I/O port with an output latch. Port 4 can be set to the input mode or output mode in 1-bit units using port
mode register 4 (PM4). When the P40 to P47 pins are used as an input port, use of an on-chip pull-up resistor can be
specified in 1-bit units by pull-up resistor option register 4 (PU4).
Input to the P43 and P44 pins can be specified through a normal input buffer or a TTL input buffer in 1-bit units using
port input mode register 4 (PIM4).
Output from the P43 to P45 pins can be specified as N-ch open-drain output (EVDD0 tolerance) in 1-bit units using port
output mode register 4 (POM4).
This port can also be used for data I/O for a flash memory programmer/debugger, serial interface data I/O, clock I/O,
and external interrupt request input.
Reset signal generation sets port 4 to input mode.
Table 4-10. Settings of Registers When Using Port 4
<R>
PM4×
PIM4×
POM4×
Alternate Function Setting
Input
1
−
−
×
Output
0
Input
1
0
×
×
1
1
×
×
Pin Name
Name
I/O
P40 to P42
P43
Output
P44
Input
Output
P45
Input
Output
P46, P47
Input
×
0
×
0
×
1
1
0
×
×
1
1
×
×
0
0
×
0
0
×
1
1
−
×
0
0
0
1
1
Output
Notes 1.
Remark
−
−
0
CMOS input
TTL input
SCK01/SCL01 output = 1
Note 1
CMOS output
N-ch O.D. output
CMOS input
TTL input
SDA01 output = 1
Note 2
CMOS output
N-ch O.D. output
×
SO01 output = 1
CMOS input
Note 2
CMOS output
N-ch O.D. output
×
×
To use a pin multiplexed with the serial array unit function as a general-purpose port in 80- and 100-pin
products, set the CKOmn bit in serial output register m (SOm), the SOEmn bit in serial output enable register
m (SOEm), and the SEmn bit in serial channel enable status register m (SEm) for the corresponding unit
channel to the default value. (mn = 01)
2.
To use a pin multiplexed with the serial array unit function as a general-purpose port in 80- and 100-pin
products, set the SOmn bit in serial output register m (SOm), the SOEmn bit in serial output enable register m
(SOEm), and the SEmn bit in serial channel enable status register m (SEm) for the corresponding unit
channel to the default value. (mn = 01)
Caution
Remark
When a tool is connected, the P40 pin cannot be used as a port pin.
×:
don’t care
PM4×:
Port mode register 4
PIM4×:
Port input mode register 4
POM4×:
Port output mode register 4
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For example, figures 4-20 to 4-26 show block diagrams of port 4 for 100-pin products.
Figure 4-20. Block Diagram of P40
EVDD
WRPU
PU4
PU40
P-ch
Alternate
function
Selector
WRPORT
P4
Output latch
(P40)
WRPM
Selector
Internal bus
RD
P40/TOOL0
PM4
PM40
WRPMS
PMS
<R>
PMS0
Alternate
function
(TOOL0)
P4:
Port register 4
PU4:
Pull-up resistor option register 4
PM4:
Port mode register 4
PMS:
Port mode select register
RD:
Read signal
WR××: Write signal
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Figure 4-21. Block Diagram of P41
EVDD
WRPU
PU4
PU41
P-ch
Selector
Internal bus
RD
WRPORT
P4
Output latch
(P41)
P41
WRPM
PM4
PM41
WRPMS
PMS
<R>
PMS0
P4:
Port register 4
PU4:
Pull-up resistor option register 4
PM4:
Port mode register 4
PMS:
Port mode select register
RD:
Read signal
WR××: Write signal
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Figure 4-22. Block Diagram of P42
EVDD
WRPU
PU4
PU42
P-ch
Selector
Internal bus
RD
WRPORT
P4
Output latch
(P42)
P42
WRPM
PM4
PM42
WRPMS
PMS
<R>
PMS0
P4:
Port register 4
PU4:
Pull-up resistor option register 4
PM4:
Port mode register 4
PMS:
Port mode select register
RD:
Read signal
WR××: Write signal
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Figure 4-23. Block Diagram of P43
WRPIM
PIM4
PIM43
EVDD
WRPU
PU4
PU43
P-ch
Alternate
function
CMOS
Internal bus
Selector
RD
TTL
WRPORT
P4
Output latch
(P43)
P43/SCK01/
SCL01
WRPOM
POM4
POM43
WRPM
PM4
PM43
WRPMS
PMS
<R>
PMS0
Alternate
function
(SCK01/SCL01)
P4:
Port register 4
PU4:
Pull-up resistor option register 4
PM4:
Port mode register 4
PIM4:
Port input mode register 4
POM4: Port output mode register 4
PMS:
Port mode select register
RD:
Read signal
WR××: Write signal
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Figure 4-24. Block Diagram of P44
WRPIM
PIM4
PIM44
EVDD
WRPU
PU4
PU44
P-ch
Alternate
function
CMOS
Selector
Internal bus
RD
TTL
WRPORT
P4
Output latch
(P44)
P44/SI01/SDA01
WRPOM
POM4
POM44
WRPM
PM4
PM44
WRPMS
PMS
<R>
PMS0
Alternate
function
(SDA01)
P4:
Port register 4
PU4:
Pull-up resistor option register 4
PM4:
Port mode register 4
PIM4:
Port input mode register 4
POM4: Port output mode register 4
PMS:
Port mode select register
RD:
Read signal
WR××: Write signal
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Figure 4-25. Block Diagram of P45
EVDD
WRPU
PU4
PU45
P-ch
Selector
Internal bus
RD
WRPORT
P4
Output latch
(P45)
P45/SO01
WRPOM
POM4
POM45
WRPM
PM4
PM45
WRPMS
PMS
<R>
PMS0
Alternate
function
(SO01)
P4:
Port register 4
PU4:
Pull-up resistor option register 4
PM4:
Port mode register 4
POM4: Port output mode register 4
PMS:
Port mode select register
RD:
Read signal
WR××: Write signal
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Figure 4-26. Block Diagram of P46, P47
EVDD
WRPU
PU4
PU46, PU47
P-ch
Alternate
function
Selector
Internal bus
RD
WRPORT
P4
Output latch
(P46, P47)
P46/INTP1,
P47/INTP2
WRPM
PM4
PM46, PM47
WRPMS
PMS
<R>
PMS0
P4:
Port register 4
PU4:
Pull-up resistor option register 4
PM4:
Port mode register 4
PMS:
Port mode select register
RD:
Read signal
WR××: Write signal
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4.2.6 Port 5
Port 5 is an I/O port with an output latch. Port 5 can be set to the input mode or output mode in 1-bit units using port
mode register 5 (PM5). When the P50 to P57 pins are used as an input port, use of an on-chip pull-up resistor can be
specified in 1-bit units by pull-up resistor option register 5 (PU5).
Input to the P50, P53 to P55 pin can be specified through a normal input buffer or a TTL input buffer in 1-bit units using
port input mode register 5 (PIM5).
Output from the P50 to P55 pins can be specified as N-ch open-drain output (EVDD0 tolerance) in 1-bit units using port
output mode register 5 (POM5).
This port can also be used for external interrupt request input, serial interface data I/O, clock I/O, programming UART
transmission/reception, and timer I/O.
Reset signal generation sets port 5 to input mode.
Table 4-11. Settings of Registers When Using Port 5
<R>
Pin Name
Name
PM5×
PIM5×
POM5×
1
0
×
×
1
1
×
×
Input
Output
P51
0
×
0
0
×
1
Input
1
−
×
Output
0
0
0
Input
P52
Output
1
−
1
0
Input
P53
Output
1
1
0
1
1
0
Input
1
1
Output
Input
P55
Output
P56, P57
0
Note 1
Note 1
×
0
P54
×
0
0
2.
Note 7
Remark
I/O
P50
Notes 1.
Alternate Function Setting
×
0
1
0
1
Note 1
Note 1
×
0
CMOS output
Note 3
N-ch O.D. output
×
SO00/TxD0 output = 1
TRGIOB output = 0
Note 4
Note 3
Note 1
×
SO31 output = 1
CMOS output
Note 4
N-ch O.D. output
×
×
×
×
CMOS input
Note 1
Note 1
SDA31 output = 1
CMOS output
Note 4
N-ch O.D. output
×
×
×
×
Note 1
CMOS input
TTL input
SCK31/SCL31 output = 1
Note 4
Note 1
CMOS output
N-ch O.D. output
0
×
×
1
1
×
×
0
CMOS output
N-ch O.D. output
Note 1
1
×
Note 2
TRGIOA output = 0
×
0
TTL input
SDA00 output = 1
0
1
CMOS input
(SCK00 output = 1
CMOS input
TTL input
Note 6
(PCLBUZ1 output = 0
0
×
1
Input
1
0
×
×
Output
0
×
0
×
CMOS output
)
Note 5
)
N-ch O.D. output
80-, 100-pin products only
To use a pin multiplexed with the serial array unit function as a general-purpose port, set the CKOmn bit in
serial output register m (SOm), the SOEmn bit in serial output enable register m (SOEm), and the SEmn
bit in serial channel enable status register m (SEm) for the corresponding unit channel to the default value.
(mn = 03, 10)
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Notes 3.
To use a pin multiplexed with the timer RD function as a general-purpose port, set the output control bit in
timer RD output master enable register 1 (TRDOER1) for the corresponding TRDIOij pin to the default
value. (i = A, B, C, D; j = 0, 1)
4.
To use a pin multiplexed with the serial array unit function as a general-purpose port, set the SOmn bit in
serial output register m (SOm), the SOEmn bit in serial output enable register m (SOEm), and the SEmn
bit in serial channel enable status register m (SEm) for the corresponding unit channel to the default value.
(mn = 03, 10)
5.
To use a pin multiplexed with the clock/buzzer output function as a general-purpose port when the PIOR04
bit in peripheral I/O redirection register 0 (PIOR0) is 1, set the PCLOEi bit in clock output select register i to
the default status. (i = 1)
6.
To use a pin multiplexed with the serial array unit function as a general-purpose port when the PIOR01 bit
in peripheral I/O redirection register 0 (PIOR0) is 1, set the SOmn bit in serial output register m (SOm), the
SOEmn bit in serial output enable register m (SOEm), and the SEmn bit in serial channel enable status
register m (SEm) for the corresponding unit channel to the default value. (mn = 00)
7.
Functions in parentheses in the above table can be assigned via settings in the peripheral I/O redirection
registers 0, 1 (PIOR0, 1).
Remark
×
: don’t care
PM5×
: Port mode register 5
PIM5×
: Port input mode register 5
POM5×
: Port output mode register 5
PMC5×
: Port mode control register 5
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For example, figures 4-27 to 4-33 show block diagrams of port 5 for 100-pin products when PIOR0 = 00H.
Figure 4-27. Block Diagram of P50
WRPIM
PIM5
PIM50
EVDD
WRPU
PU5
PU50
P-ch
Alternate
function
CMOS
Selector
RD
TTL
Internal bus
WRPORT
P5
Output latch
(P50)
WRPOM
P50/SI00/
RxD0/TOOLRxD/
SDA00/
TRGIOA
POM5
POM50
WRPM
PM5
PM50
WRPMS
PMS
<R>
PMS0
Alternate
function
(SDA00)
Alternate
function
(TRGIOA)
P5:
Port register 5
PU5:
Pull-up resistor option register 5
PM5:
Port mode register 5
PIM5:
Port input mode register 5
POM5: Port output mode register 5
PMS:
Port mode select register
RD:
Read signal
WR××: Write signal
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Figure 4-28. Block Diagram of P51
EVDD
WRPU
PU5
PU51
P-ch
Alternate
function
Selector
RD
Internal bus
WRPORT
P5
Output latch
(P51)
WRPOM
POM5
P51/SO00/
TxD0/
TOOLTxD/
TRGIOB
POM51
WRPM
PM5
PM51
WRPMS
PMS
<R>
PMS0
Alternate
function
(SO00/TxD0)
Alternate
function
(TRGIOB)
P5:
Port register 5
PU5:
Pull-up resistor option register 5
PM5:
Port mode register 5
POM5: Port output mode register 5
PMS:
Port mode select register
RD:
Read signal
WR××: Write signal
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Figure 4-29. Block Diagram of P52
EVDD
WRPU
PU5
PU52
P-ch
Selector
Internal bus
RD
WRPORT
P5
Output latch
(P52)
P52/SO31
WRPOM
POM5
POM52
WRPM
PM5
PM52
WRPMS
PMS
<R>
PMS0
Alternate
function
(SO31)
P5:
Port register 5
PU5:
Pull-up resistor option register 5
PM5:
Port mode register 5
POM5: Port output mode register 5
PMS:
Port mode select register
RD:
Read signal
WR××: Write signal
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Figure 4-30. Block Diagram of P53
WRPIM
PIM5
PIM53
EVDD
WRPU
PU5
PU53
P-ch
Alternate
function
CMOS
Selector
Internal bus
RD
TTL
WRPORT
P5
Output latch
(P53)
P53/SI31/SDA31
WRPOM
POM5
POM53
WRPM
PM5
PM53
WRPMS
PMS
<R>
PMS0
Alternate
function
(SDA31)
P5:
Port register 5
PU5:
Pull-up resistor option register 5
PM5:
Port mode register 5
PIM5:
Port input mode register 5
POM5: Port output mode register 5
PMS:
Port mode select register
RD:
Read signal
WR××: Write signal
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Figure 4-31. Block Diagram of P54
WRPIM
PIM5
PIM54
EVDD
WRPU
PU5
PU54
P-ch
Alternate
function
CMOS
Internal bus
Selector
RD
TTL
WRPORT
P5
Output latch
(P54)
P54/SCK31/
SCL31
WRPOM
POM5
POM54
WRPM
PM5
PM54
WRPMS
PMS
<R>
PMS0
Alternate
function
(SCK31/SCL31)
P5:
Port register 5
PU5:
Pull-up resistor option register 5
PM5:
Port mode register 5
PIM5:
Port input mode register 5
POM5: Port output mode register 5
PMS:
Port mode select register
RD:
Read signal
WR××: Write signal
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Figure 4-32. Block Diagram of P55
WRPIM
PIM5
PIM55
EVDD
WRPU
PU5
PU55
P-ch
CMOS
Selector
Internal bus
RD
TTL
WRPORT
P5
Output latch
(P55)
P55
WRPOM
POM5
POM55
WRPM
PM5
PM55
WRPMS
PMS
<R>
PMS0
P5:
Port register 5
PU5:
Pull-up resistor option register 5
PM5:
Port mode register 5
PIM5:
Port input mode register 5
POM5: Port output mode register 5
PMS:
Port mode select register
RD:
Read signal
WR××: Write signal
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Figure 4-33. Block Diagram of P56, P57
EVDD
WRPU
PU5
PU56, PU57
P-ch
Selector
Internal bus
RD
WRPORT
P5
Output latch
(P56, P57)
P56, P57
WRPM
PM5
PM56, PM57
WRPMS
PMS
<R>
PMS0
P5:
Port register 5
PU5:
Pull-up resistor option register 5
PM5:
Port mode register 5
PMS:
Port mode select register
RD:
Read signal
WR××: Write signal
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4.2.7 Port 6
Port 6 is an I/O port with an output latch. Port 6 can be set to the input mode or output mode in 1-bit units using port
mode register 6 (PM6). When the P64 to P67 pins are used as an input port, use of an on-chip pull-up resistor can be
specified in 1-bit units by pull-up resistor option register 6 (PU6).
The output of the P60 to P63 pins is N-ch open-drain output (6 V tolerance).
This port can also be used for serial interface data I/O and clock I/O, chip select input, and timer I/O.
Reset signal generation sets port 6 to input mode.
Table 4-12. Settings of Registers When Using Port 6
<R>
PM6×
Alternate Function Setting
Input
1
×
Output
0
Input
1
Output
0
Input
1
Output
0
Pin Name
Name
Remark
I/O
P60
P61
P62
P63
P64
P65
P66
P67
Notes 1.
Input
1
Output
0
Input
1
Output
0
Input
1
Output
0
Input
1
Output
0
Input
1
Output
0
SCLA0 output = 0
Note 1
×
SDAA0 output = 0
Note 1
×
SCLA1 output = 0
Note 1
×
SCLA1 output = 0
Note 1
×
TO10 output = 0
Note 2
×
TO11 output = 0
Note 2
×
TO12 output = 0
Note 2
×
TO13 output = 0
Note 2
To use a pin multiplexed with the serial interface IICA function as a general-purpose port, stop the
operation of the corresponding serial interface IICA.
2.
To use a pin multiplexed with the timer output function of the timer array unit as a general-purpose port, set
the TOmn bit in timer output register m (TOm) and the TOEmn bit in timer output enable register m for the
corresponding unit channel to the default status. (m = 1, n = 0 to 3)
Remark
×
: don’t care
PM6×
: Port mode register 6
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For example, figures 4-34, 4-35 show block diagrams of port 6 for 100-pin products.
Figure 4-34. Block Diagram of P60 to P63
Alternate
function
Selector
RD
WRPORT
Internal bus
P6
Output latch
(P60 to P63)
WRPM
PM6
P60/SCLA0,
P61/SDAA0,
P62/SSI00/SCLA1,
P63/SDAA1
PM60 to PM63
WRPMS
PMS
<R>
PMS0
Alternate
function
(SCLA0, SDAA0,
SCLA1, SDAA1)
P6:
Port register 6
PM6:
Port mode register 6
PMS:
Port mode select register
RD:
Read signal
WR××: Write signal
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Figure 4-35. Block Diagram of P64 to P67
EVDD
WRPU
PU6
PU64 to PU67
P-ch
Alternate
function
Selector
Internal bus
RD
WRPORT
P6
Output latch
(P64 to P67)
WRPM
PM6
P64/TI10/TO10,
P65/TI11/TO11,
P66/TI12/TO12,
P67/TI13/TO13
PM64-PM67
WRPMS
PMS
<R>
PMS0
Alternate
function
(TO10, TO11,
TO12, TO13)
P6:
Port register 6
PU6:
Pull-up resistor option register 6
PM6:
Port mode register 6
PMS:
Port mode select register
RD:
Read signal
WR××: Write signal
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4.2.8 Port 7
Port 7 is an I/O port with an output latch. Port 7 can be set to the input mode or output mode in 1-bit units using port
mode register 7 (PM7). When used as an input port, use of an on-chip pull-up resistor can be specified in 1-bit units by
pull-up resistor option register 7 (PU7).
Output from the P71 and P74 pins can be specified as N-ch open-drain output (EVDD0 tolerance) in 1-bit units using port
output mode register 7 (POM7).v
This port can also be used for key interrupt input, serial interface data I/O, clock I/O, and external interrupt request input.
Reset signal generation sets port 7 to input mode.
Table 4-13. Settings of Registers When Using Port 7
<R>
PM7×
POM7×
Input
1
×
Output
0
0
Input
1
×
Output
0
0
0
1
Input
1
−
Output
0
Input
1
×
Output
0
0
Input
1
×
Output
0
0
Pin Name
Name
Alternate Function Setting
Note 4
Remark
I/O
P70
P71
P72
P73
P74
P75
P76
P77
Notes 1.
×
×
SDA21 output = 1
0
1
1
×
Output
0
0
Input
1
−
Output
0
Input
1
×
Output
0
0
Note 2
CMOS output
N-ch O.D. output
×
SO21 output = 1
Input
Note 1
SCK21/SCL21 output = 1
Note 2
×
SO01 output = 1
Note 2
×
SDA01 output = 1
Note 2
CMOS output
N-ch O.D. output
×
SCK01/SCL01 output = 1
Note 1
×
×
×
(TxD2 output = 1
Note 3
)
To use a pin multiplexed with the serial array unit function as a general-purpose port, set the CKOmn bit in
serial output register m (SOm), the SOEmn bit in serial output enable register m (SOEm), and the SEmn
bit in serial channel enable status register m (SEm) for the corresponding unit channel to the default value.
(mn = 01, 11)
2.
To use a pin multiplexed with the serial array unit function as a general-purpose port, set the SOmn bit in
serial output register m (SOm), the SOEmn bit in serial output enable register m (SOEm), and the SEmn
bit in serial channel enable status register m (SEm) for the corresponding unit channel to the default value.
(mn = 01, 11)
3.
To use a pin multiplexed with the serial array unit function as a general-purpose port when the PIOR01 bit
in peripheral I/O redirection register 0 (PIOR0) is 1, set the SOmn bit in serial output register m (SOm), the
SOEmn bit in serial output enable register m (SOEm), and the SEmn bit in serial channel enable status
register m (SEm) for the corresponding unit channel to the default value. (mn = 00)
4.
Functions in parentheses in the above table can be assigned via settings in the peripheral I/O redirection
register 0 (PIOR0).
Remark
×
: don’t care
PM7×
: Port mode register 7
POM7×
: Port output mode register 7
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For example, figures 4-36 to 4-40 show block diagrams of port 7 for 100-pin products when PIOR0 = 00H.
Figure 4-36. Block Diagram of P70
EVDD
WRPU
PU7
PU70
P-ch
Alternate
function
Internal bus
Selector
RD
WRPORT
P7
Output latch
(P70)
P70/KR0/SCK21/SCL21
WRPM
PM7
PM70
WRPMS
PMS
<R>
PMS0
Alternate
function
(SCK21/SCL21)
P7:
Port register 7
PU7:
Pull-up resistor option register 7
PM7:
Port mode register 7
PMS:
Port mode select register
RD:
Read signal
WR××: Write signal
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Figure 4-37. Block Diagram of P71
EVDD
WRPU
PU7
PU71
P-ch
Alternate
function
Selector
Internal bus
RD
WRPORT
P7
Output latch
(P71)
P71/KR1/SI21/SDA21
WRPOM
POM7
POM71
WRPM
PM7
PM71
WRPMS
PMS
<R>
PMS0
Alternate
function
(SDA21)
P7:
Port register 7
PU7:
Pull-up resistor option register 7
PM7:
Port mode register 7
POM7: Port output mode register 7
PMS:
Port mode select register
RD:
Read signal
WR××: Write signal
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Figure 4-38. Block Diagram of P72
EVDD
WRPU
PU7
PU72
P-ch
Alternate
function
Selector
Internal bus
RD
WRPORT
P7
Output latch
(P72)
P72/KR2/SO21
WRPM
PM7
PM72
WRPMS
PMS
<R>
PMS0
Alternate
function
(SO21)
P7:
Port register 7
PU7:
Pull-up resistor option register 7
PM7:
Port mode register 7
PMS:
Port mode select register
RD:
Read signal
WR××: Write signal
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Figure 4-39. Block Diagram of P73, P75 to P77
EVDD
WRPU
PU7
PU73, PU75 to PU77
P-ch
Alternate
function
Selector
Internal bus
RD
WRPORT
P7
Output latch
(P73, P75 to P77)
WRPM
P73/KR3,
P75/KR5/INTP9,
P76/KR6/INTP10,
P77/KR7/INTP11
PM7
PM73, PM75 to PM77
WRPMS
PMS
<R>
PMS0
P7:
Port register 7
PU7:
Pull-up resistor option register 7
PM7:
Port mode register 7
PMS:
Port mode select register
RD:
Read signal
WR××: Write signal
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Figure 4-40. Block Diagram of P74
EVDD
WRPU
PU7
PU74
P-ch
Alternate
function
Selector
Internal bus
RD
WRPORT
P7
Output latch
(P74)
P74/KR4/INTP8
WRPOM
POM7
POM74
WRPM
PM7
PM74
WRPMS
PMS
<R>
PMS0
P7:
Port register 7
PU7:
Pull-up resistor option register 7
PM7:
Port mode register 7
POM7: Port output mode register 7
PMS:
Port mode select register
RD:
Read signal
WR××: Write signal
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4.2.9 Port 8
Port 8 is an I/O port with an output latch. Port 8 can be set to the input mode or output mode in 1-bit units using port
mode register 8 (PM8). When the P80 to P87 pins are used as an input port, use of an on-chip pull-up resistor can be
specified in 1-bit units by pull-up resistor option register 8 (PU8).
Input to the P80 and P81 pins can be specified through a normal input buffer or a TTL input buffer in 1-bit units using
port input mode register 8 (PIM8).
Output from the P80 to P82 pin can be specified as N-ch open-drain output (EVDD0 tolerance) in 1-bit units using port
output mode register 8 (POM8).
Reset signal generation sets port 8 to input mode.
Table 4-14. Settings of Registers When Using Port 8
<R>
Pin Name
Name
PM8×
PIM8×
POM8×
1
0
×
×
1
1
×
×
Alternate Function Setting
Note 3
Remark
I/O
P80
Input
0
×
0
0
×
1
1
0
×
1
1
×
0
×
0
0
×
1
Input
1
−
×
Output
0
0
0
1
Output
P81
Input
Output
P82
P83 to P87
Notes 1.
Input
1
Output
0
−
−
CMOS input
TTL input
(SCK10/SCL10 output = 1
Note 1
)
CMOS output
N-ch O.D. output
×
CMOS input
×
(SDA10 output = 1
TTL input
Note 2
)
CMOS output
N-ch O.D. output
×
(TxD1/SO10 output = 0
Note 2
)
CMOS output
N-ch O.D. output
×
×
To use a pin multiplexed with the serial array unit function as a general-purpose port when the PIOR05 bit
in peripheral I/O redirection register 0 (PIOR0) is 1, set the SOmn bit in serial output register m (SOm), the
SOEmn bit in serial output enable register m (SOEm), and the SEmn bit in serial channel enable status
register m (SEm) for the corresponding unit channel to the default value. (mn = 02)
2.
To use a pin multiplexed with the serial array unit function as a general-purpose port when the PIOR05 bit
in peripheral I/O redirection register 0 (PIOR0) is 1, set the CKOmn bit in serial output register m (SOm),
the SOEmn bit in serial output enable register m (SOEm), and the SEmn bit in serial channel enable status
register m (SEm) for the corresponding unit channel to the default value. (mn = 02)
3.
Functions in parentheses in the above table can be assigned via settings in the peripheral I/O redirection
register 0 (PIOR0).
Remark
×
: don’t care
PM8×
: Port mode register 8
PIM8×
: Port input mode register 8
POM8×
: Port output mode register 8
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For example, figures 4-41 to 4-43 show block diagrams of port 7 for 100-pin products when PIOR0 = 00H.
Figure 4-41. Block Diagram of P80, P81
WRPIM
PIM8
PIM80, PIM81
EVDD
WRPU
PU8
PU80, PU81
P-ch
CMOS
Selector
Internal bus
RD
TTL
WRPORT
P8
Output latch
(P80, P81)
P80, P81
WRPOM
POM8
POM80, POM81
WRPM
PM8
PM80, PM81
WRPMS
PMS
<R>
PMS0
P8:
Port register 8
PU8:
Pull-up resistor option register 8
PM8:
Port mode register 8
PIM8:
Port input mode register 8
POM8: Port output mode register 8
PMS:
Port mode select register
RD:
Read signal
WR××: Write signal
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Figure 4-42. Block Diagram of P82
EVDD
WRPU
PU8
PU82
P-ch
RD
Selector
Internal bus
<R>
WRPORT
P8
Output latch
(P82)
P82
WRPOM
POM8
POM82
WRPM
PM8
PM82
WRPMS
PMS
<R>
PMS0
P8:
Port register 8
PU8:
Pull-up resistor option register 8
PM8:
Port mode register 8
POM8: Port output mode register 8
PMS:
Port mode select register
RD:
Read signal
WR××: Write signal
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Figure 4-43. Block Diagram of P83 to P87
EVDD
WRPU
PU8
PU83 to PU87
P-ch
Selector
Internal bus
RD
WRPORT
P8
Output latch
(P83 to P87)
P83-P87
WRPM
PM8
PM83-PM87
WRPMS
PMS
<R>
PMS0
P8:
Port register 8
PU8:
Pull-up resistor option register 8
PM8:
Port mode register 8
PMS:
Port mode select register
RD:
Read signal
WR××: Write signal
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4.2.10 Port 10
Port 10 is an I/O port with an output latch. Port 10 can be set to the input mode or output mode in 1-bit units using port
mode register 10 (PM10). When the P100 to P102 pins are used as an input port, use of an on-chip pull-up resistor can
be specified in 1-bit units by pull-up resistor option register 10 (PU10).
Input to the P100 pin can be specified as analog input or digital input in 1-bit units, using port mode control register 10
(PMC10).
This port can also be used for A/D converter analog input.
Reset signal generation sets P100 to analog input, P101, P102 to input mode.
Table 4-15. Settings of Registers When Using Port 10
<R>
PM10×
PMC10×
Alternate Function Setting
Input
1
0
×
Output
0
0
×
Input
1
−
×
Output
0
Input
1
Output
0
Pin Name
Name
I/O
P100
P101
P102
Remark
Remark
×
×
−
×
×
: don’t care
PM10×
: Port mode register 10
PMC10×
: Port mode control register 10
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For example, figures 4-44, 4-45 show block diagrams of port 10 for 100-pin products.
Figure 4-44. Block Diagram of P100
EVDD
WRPU
PU10
PU100
P-ch
WRPMC
PMC10
PMC100
Selector
Internal bus
RD
WRPORT
P10
Output latch
(P100)
P100/ANI20
WRPM
PM10
PM100
WRPMS
PMS
A/D converter
<R>
PMS0
P10:
Port register 10
PU10:
Pull-up resistor option register 10
PM10:
Port mode register 10
PMC10: Port mode controlregister 10
PMS:
Port mode select register
RD:
Read signal
WR××: Write signal
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Figure 4-45. Block Diagram of P101, P102
EVDD
WRPU
PU10
PU101, PU102
P-ch
Selector
Internal bus
RD
WRPORT
P10
Output latch
(P101, P102)
P101, P102
WRPM
PM10
PM101, PM102
WRPMS
PMS
<R>
PMS0
P10:
Port register 10
PU10:
Pull-up resistor option register 10
PM10:
Port mode register 10
PMS:
Port mode select register
RD:
Read signal
WR××: Write signal
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4.2.11 Port 11
Port 11 is an I/O port with an output latch. Port 11 can be set to the input mode or output mode in 1-bit units using port
mode register 11 (PM11). When the P110 and P111 pins are used as an input port, use of an on-chip pull-up resistor can
be specified in 1-bit units by pull-up resistor option register 11 (PU11).
Reset signal generation sets port 11 to input mode.
Table 4-16. Settings of Registers When Using Port 11
<R>
Pin Name
Name
PM11×
Alternate Function Setting
I/O
P110,
Input
1
×
P111
Output
0
×
Remark
Remark
×
: don’t care
PM11×
: Port mode register 11
PMC11×
: Port mode control register 11
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For example, figure 4-46 shows block diagram of port 11 for 100-pin products.
Figure 4-46. Block Diagram of P110 and P111
EVDD
WRPU
PU11
PU110, PU111
P-ch
Selector
Internal bus
RD
WRPORT
P11
Output latch
(P110, P111)
P110, P111
WRPM
PM11
PM110, PM111
WRPMS
PMS
<R>
PMS0
P11:
Port register 11
PU11:
Pull-up resistor option register 11
PM11:
Port mode register 11
PMS:
Port mode select register
RD:
Read signal
WR××: Write signal
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4.2.12 Port 12
P120 is an I/O port with an output latch. Port 12 can be set to the input mode or output mode in 1-bit units using port
mode register 12 (PM12). When used as an input port, use of an on-chip pull-up resistor can be specified by pull-up
resistor option register 12 (PU12).
P121 to P124 are 4-bit input ports.
Input to the P120 pin can be specified as analog input or digital input in 1-bit units, using port mode control register 12
(PMC12).
This port can also be used for A/D converter analog input, connecting resonator for main system clock, connecting
resonator for subsystem clock, external clock input for main system clock, external clock input for subsystem clock, and
comparator output.
Reset signal generation sets P120 to analog input, and sets P121 to P124 to input mode.
Table 4-17. Settings of Registers When Using Port 12
<R>
PM12×
PMC12×
Alternate Function Setting
Input
1
0
×
Output
0
0
Input
−
−
Pin Name
Name
Remark
I/O
P120
P121
VCOUT0 output = 0
Note
OSCSEL bit of CMC register = 0
or EXCLK bit = 1
P122
Input
−
−
OSCSEL bit of CMC register = 0
P123
Input
−
−
OSCSELS bit of CMC register = 0
or EXCLKS bit = 1
P124
Note
−
Input
−
OSCSELS bit of CMC register = 0
To use a pin multiplexed with the comparator output function as a general-purpose port in products with 96
KB or more code flash memory, set the CnOE bit in the comparator output control register (COMPOCR) to
the default value. (n = 0)
Caution The function setting on P121 to P124 is available only once after the reset release. The port once set
for connection to an oscillator cannot be used as an input port unless the reset is performed.
Remark
×
: don’t care
PM12×
: Port mode register 12
PMC12×
: Port mode control register 12
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For example, figures 4-47 to 4-49 show block diagrams of port 12 for 100-pin products.
Figure 4-47. Block Diagram of P120
EVDD
WRPU
PU12
PU120
P-ch
WRPMC
PMC12
PMC120
Selector
Internal bus
RD
WRPORT
P12
Output latch
(P120)
P120/ANI19/
VCOUT0
WRPM
PM12
PM120
WRPMS
PMS
<R>
PMS0
A/D converter
Alternate
function
(VCOUT0)
P12:
Port register 12
PU12:
Pull-up resistor option register 12
PM12:
Port mode register 12
PMC12: Port mode control register 12
PMS:
Port mode select register
RD:
Read signal
WR××: Write signal
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<R>
Figure 4-48. Block Diagram of P121 and P122
Clock generator
CMC
OSCSEL
Internal bus
RD
P122/X2/EXCLK
CMC
EXCLK
RD
P121/X1
CMC:
Clock operation mode control register
RD:
Read signal
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<R>
Figure 4-49. Block Diagram of P123 and P124
Clock generator
CMC
OSCSELS
Internal bus
RD
P124/XT2
RD
P123/XT1
CMC:
Clock operation mode control register
RD:
Read signal
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4.2.13 Port 13
P130 is a 1-bit output-only port with an output latch.
P137 is a 1-bit input-only port.
P130 is fixed an output port, and P137 is fixed an input ports.
This port can also be used for external interrupt request input.
Table 4-18. Settings of Registers When Using Port 13
<R>
Pin Name
Name
Remark
Alternate Function Setting
Remark
I/O
P130
Output
−
P137
Input
×
×
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For example, figures 4-50, 4-51 show block diagrams of port 13 for 100-pin products.
Figure 4-50. Block Diagram of P130
Internal bus
RD
WRPORT
P13
Output latch
(P130)
P13:
P130
Port register 13
RD:
Read signal
WR××: Write signal
Remark When reset is effected, P130 outputs a low level. If P130 is set to output a high level before reset is effected,
the output signal of P130 can be dummy-output as the CPU reset signal.
Reset signal
P130
Set by software
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Figure 4-51. Block Diagram of P137
Internal bus
RD
P137/INTP0
Alternate
function
RD:
Read signal
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4.2.14 Port 14
Port 14 is an I/O port with an output latch. Port 14 can be set to the input mode or output mode in 1-bit units using port
mode register 14 (PM14). When the P140 to P147 pins are used as an input port, use of an on-chip pull-up resistor can
be specified in 1-bit units by pull-up resistor option register 14 (PU14).
Input to the P142 and P143 pins can be specified through a normal input buffer or a TTL input buffer in 1-bit units using
port input mode register 14 (PIM14).
Output from the P140 to P142 pin can be specified as N-ch open-drain output (EVDD0 tolerance) in 1-bit units using port
output mode register 14 (POM14).
Input to the P147 pin can be specified as analog input or digital input in 1-bit units, using port mode control register 14
(PMC14).
This port can also be used for clock/buzzer output, external interrupt request input, A/D converter analog input, serial
interface data I/O, clock I/O, and comparator output.
Reset signal generation sets P140 to P146 to input mode, and sets P147 to analog input.
Table 4-19. Settings of Registers When Using Port 14
<R>
PM14×
PIM14×
POM14×
PMC14×
Alternate Function Setting
Input
1
−
−
−
×
Output
0
Input
1
Output
0
Input
1
Pin Name
Name
P140
P141
P142
I/O
Output
P143
Input
PCLBUZ0 output = 0
−
×
1
1
×
0
×
0
0
×
1
1
0
×
1
1
×
×
0
0
×
1
Input
1
−
×
Output
0
1
P146
Output
0
P147
Input
1
Output
0
−
Note 1
×
Note 1
×
CMOS input
×
TTL input
SCK30/SCL30 output = 1
Note 2
−
×
CMOS input
×
SDA30 output = 1
TTL input
Note 3
−
CMOS output
N-ch O.D. output
−
×
SO30/TxD3 output = 1
Note 3
CMOS output
N-ch O.D. output
1
−
CMOS output
N-ch O.D. output
0
0
Input
−
PCLBUZ1 output = 0
0
P145,
Notes 1.
−
0
Output
P144
Remark
−
×
×
−
−
0
0
×
VCOUT1 output = 0
Note 4
To use a pin multiplexed with the clock/buzzer output function as a general-purpose port, set the PCLOEi
bit in clock output select register i (CKSi) to the default value. (i = 0, 1)
2.
To use a pin multiplexed with the serial array unit function as a general-purpose port, set the CKOmn bit in
serial output register m (SOm), the SOEmn bit in serial output enable register m (SOEm), and the SEmn
bit in serial channel enable status register m (SEm) for the corresponding unit channel to the default value.
(mn = 12)
3.
To use a pin multiplexed with the serial array unit function as a general-purpose port, set the SOmn bit in
serial output register m (SOm), the SOEmn bit in serial output enable register m (SOEm), and the SEmn
bit in serial channel enable status register m (SEm) for the corresponding unit channel to the default value.
(mn = 12)
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Notes 4.
To use a pin multiplexed with the comparator output function as a general-purpose port in products with 96
KB or more code flash memory, set the CnOE bit in the comparator output control register (COMPOCR) to
the default value. (n = 1)
Remark
×
: don’t care
PM14×
: Port mode register 14
PIM14×
: Port input mode register 14
POM14× : Port output mode register 14
PMC14×
: Port mode control register 14
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For example, figures 4-52 to 4-57 show block diagrams of port 14 for 100-pin products.
Figure 4-52. Block Diagram of P140 and P141
EVDD
WRPU
PU14
PU140, PU141
P-ch
Alternate
function
Selector
Internal bus
RD
WRPORT
P14
Output latch
(P140, P141)
P140/PCLBUZ0/INTP6,
P141/PCLBUZ1/INTP7
WRPM
PM14
PM140, PM141
WRPMS
PMS
<R>
PMS0
Alternate
function
(PCLBUZ0,
PCLBUZ1)
P14:
Port register 14
PU14:
Pull-up resistor option register 14
PM14:
Port mode register 14
PMS:
Port mode select register
RD:
Read signal
WR××: Write signal
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Figure 4-53. Block Diagram of P142
WRPIM
PIM14
PIM142
EVDD
WRPU
PU14
PU142
P-ch
Alternate
function
CMOS
Selector
Internal bus
RD
TTL
WRPORT
P14
Output latch
(P142)
P142/SCK30/SCL30
WRPOM
POM14
POM142
WRPM
PM14
PM142
WRPMS
PMS
<R>
PMS0
Alternate
function
(SCK30/SCL30)
P14:
Port register 14
PU14:
Pull-up resistor option register 14
PM14:
Port mode register 14
PIM14: Port input mode register 14
POM14: Port output mode register 14
PMS:
Port mode select register
RD:
Read signal
WR××: Write signal
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Figure 4-54. Block Diagram of P143
WRPIM
PIM14
PIM143
EVDD
WRPU
PU14
PU143
P-ch
Alternate
function
CMOS
Selector
Internal bus
RD
TTL
WRPORT
P14
Output latch
(P143)
P143/SI30/RxD3/SDA30
WRPOM
POM14
POM143
WRPM
PM14
PM143
WRPMS
PMS
<R>
PMS0
Alternate
function
(SDA30)
P14:
Port register 14
PU14:
Pull-up resistor option register 14
PM14:
Port mode register 14
PIM14: Port input mode register 14
POM14: Port output mode register 14
PMS:
Port mode select register
RD:
Read signal
WR××: Write signal
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Figure 4-55. Block Diagram of P144
EVDD
WRPU
PU14
PU144
P-ch
RD
Internal bus
Selector
<R>
WRPORT
P14
Output latch
(P144)
P144/SO30/TxD3
WRPOM
POM14
POM144
WRPM
PM14
PM144
WRPMS
PMS
<R>
PMS0
Alternate
function
(SO30/TxD3)
P14:
Port register 14
PU14:
Pull-up resistor option register 14
PM14:
Port mode register 14
POM14: Port output mode register 14
PMS:
Port mode select register
RD:
Read signal
WR××: Write signal
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Figure 4-56. Block Diagram of P145 and P146
EVDD
WRPU
PU14
PU145, PU146
P-ch
Selector
Internal bus
RD
WRPORT
P14
Output latch
(P145, P146)
P145, P146
WRPM
PM14
PM145, PM146
WRPMS
PMS
<R>
PMS0
P14:
Port register 14
PU14:
Pull-up resistor option register 14
PM14:
Port mode register 14
PMS:
Port mode select register
RD:
Read signal
WR××: Write signal
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CHAPTER 4 PORT FUNCTIONS
Figure 4-57. Block Diagram of P147
EVDD
WRPU
PU14
PU147
P-ch
WRPMC
PMC14
PMC147
Selector
Internal bus
RD
WRPORT
P14
Output latch
(P147)
P147/ANI18/
VCOUT1
WRPM
PM14
PM147
WRPMS
PMS
<R>
PMS0
A/D converter
Alternate
function
(VCOUT1)
P14:
Port register 14
PU14:
Pull-up resistor option register 14
PM14:
Port mode register 14
PMC14: Port mode control register 14
PMS:
Port mode select register
RD:
Read signal
WR××: Write signal
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CHAPTER 4 PORT FUNCTIONS
4.2.15 Port 15
Port 15 is an I/O port with an output latch. Port 15 can be set to the input mode or output mode in 1-bit units using port
mode register 15 (PM15).
This port can also be used for A/D converter analog input.
To use P150/ANI8 to P156/ANI14 as digital input pins, set them in the digital I/O mode by using the A/D port
configuration register (ADPC) and in the input mode by using the PM15 register. Use these pins starting from the upper
bit.
To use 150/ANI8 to P156/ANI14 as digital output pins, set them in the digital I/O mode by using the ADPC register and
in the output mode by using the PM15 register.
To use 150/ANI8 to P156/ANI14 as analog input pins, set them in the analog input mode by using the A/D port
configuration register (ADPC) and in the input mode by using the PM15 register. Use these pins starting from the lower bit.
Table 4-20. Settings of Registers When Using Port 15
<R>
PM15×
Pin Name
Name
P15n
2.
Alternate Function Setting
Remark
−
To use P15n as a port, use these
I/O
Input
Output
Remarks 1.
ADPC
1
01H to
0
n+9H
pins from a higher bit.
PM15×
:
Port mode register 15
ADPC
:
A/D port configuration register
n = 0 to 6
Table 4-21. Setting Functions of P150/ANI8 to P156/ANI14 Pins
ADPC Register
Digital I/O selection
Analog input selection
PM15 Register
ADS Register
P150/ANI8 to P156/ANI14 Pins
Input mode
−
Digital input
Output mode
−
Digital output
Input mode
Output mode
Selects ANI.
Analog input (to be converted)
Does not select ANI.
Analog input (not to be converted)
Selects ANI.
Setting prohibited
Does not select ANI.
All P150/ANI8 to P156/ANI14 are set in the analog input mode when the reset signal is generated.
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CHAPTER 4 PORT FUNCTIONS
For example, figure 4-58 shows block diagram of port 15 for 100-pin products.
<R>
Figure 4-58. Block Diagram of P150 to P156
WRADPC
ADPC
0:Analog input
1:Digital I/O
ADPC3 to ADPC0
Selector
Internal bus
RD
WRPORT
P15
Output latch
(P150 to P156)
P150/ANI8-P156/ANI14
WRPM
PM15
PM150 to PM156
A/D converter
ADPC: A/D port cofiguration register
P15:
Port register 15
PM15:
Port mode register 15
RD:
Read signal
WR××: Write signal
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CHAPTER 4 PORT FUNCTIONS
4.3 Registers Controlling Port Function
Port functions are controlled by the following registers.
•
•
•
•
•
•
•
•
•
Port mode registers (PMxx)
Port registers (Pxx)
Pull-up resistor option registers (PUxx)
Port input mode registers (PIMxx)
Port output mode registers (POMxx)
Port mode control registers (PMCxx)
A/D port configuration register (ADPC)
Peripheral I/O redirection registers 0, 1 (PIOR0, PIOR1)
Global digital input disable register (GDIDIS)
Table 4-22. PMxx, Pxx, PUxx, PIMxx, POMxx, PMCxx registers and the bits mounted on each product
(30-pin products to 64-pin products) (1/3)
Port
Port 0
Port 1
2.
48-
44-
40-
36-
32-
30-
pin
pin
pin
pin
pin
pin
pin
Note1
√
√
√
√
√
√
√
√
Note1
√
√
√
√
√
√
√
√
PMC02
√
√
−
−
−
−
−
−
√
−
−
−
−
−
−
Pxx
PUxx
PIMxx
POMxx
PMCxx
register
register
register
register
register
register
0
PM00
P00
PU00
−
1
PM01
P01
PU01
PIM01
−
2
PM02
P02
PU02
−
POM02
POM00 PMC00
PMC01
3
PM03
P03
PU03
PIM03
POM03
PMC03
√
4
PM04
P04
PU04
PIM04
POM04
−
√
−
−
−
−
−
−
−
5
PM05
P05
PU05
−
−
−
√
−
−
−
−
−
−
−
6
PM06
P06
PU06
−
−
−
√
−
−
−
−
−
−
−
7
−
−
−
−
−
−
−
−
−
−
−
−
−
−
0
PM10
P10
PU10
PIM10
POM10
−
√
√
√
√
√
√
√
√
1
PM11
P11
PU11
−
POM11
−
PU12
−
−
PM12
P12
√
√
√
√
√
√
√
√
PMC12
Note2
√
√
√
√
√
√
√
√
POM13 PMC13
Note2
√
√
√
√
√
√
√
√
√
√
√
√
√
√
√
√
3
PM13
P13
PU13
−
4
PM14
P14
PU14
PIM14
POM14
−
5
PM15
P15
PU15
PIM15
POM15
−
PIM16
−
6
Notes 1.
52-
pin
PMxx
2
Port 2
64-
Bit name
PM16
P16
PU16
√
√
√
√
√
√
√
√
PMC16
Note2
√
√
√
√
√
√
√
√
POM17 PMC17
Note2
√
√
√
√
√
√
√
√
7
PM17
P17
PU17
PIM17
0
PM20
P20
−
−
−
−
√
√
√
√
√
√
√
√
1
PM21
P21
−
−
−
−
√
√
√
√
√
√
√
√
2
PM22
P22
−
−
−
−
√
√
√
√
√
√
√
√
3
PM23
P23
−
−
−
−
√
√
√
√
√
√
√
√
4
PM24
P24
−
−
−
−
√
√
√
√
√
√
−
−
−
−
−
√
√
√
√
√
√
−
−
5
PM25
P25
−
6
PM26
P26
−
−
−
−
√
√
√
√
√
−
−
−
7
PM27
P27
−
−
−
−
√
√
√
√
−
−
−
−
30-pin and 32-pin products only.
R5F104xF (x = A to C, E to G, J, L, M, P), R5F104xG (x = A to C, E to G, J, L, M, P), R5F104xH (x = E to G,
J, L, M, P) only.
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CHAPTER 4 PORT FUNCTIONS
Table 4-22. PMxx, Pxx, PUxx, PIMxx, POMxx, PMCxx registers and the bits mounted on each product
(30-pin products to 64-pin products) (2/3)
Port
Port 3
Port 4
Port 5
Port 6
Port 7
Bit name
64pin
52pin
48pin
44pin
40pin
36pin
32pin
30pin
PMxx
register
Pxx
register
PUxx
register
PIMxx
register
POMxx
register
PMCxx
register
0
PM30
P30
PU30
PIM30
POM30
−
√
√
√
√
√
√
√
√
1
PM31
P31
PU31
−
−
−
√
√
√
√
√
√
√
√
2
−
−
−
−
−
−
−
−
−
−
−
−
−
−
3
−
−
−
−
−
−
−
−
−
−
−
−
−
−
4
−
−
−
−
−
−
−
−
−
−
−
−
−
−
5
−
−
−
−
−
−
−
−
−
−
−
−
−
−
6
−
−
−
−
−
−
−
−
−
−
−
−
−
−
7
−
−
−
−
−
−
−
−
−
−
−
−
−
−
0
PM40
P40
PU40
−
−
−
√
√
√
√
√
√
√
√
1
PM41
P41
PU41
−
−
−
√
√
√
√
−
−
−
−
2
PM42
P42
PU42
−
−
−
√
−
−
−
−
−
−
−
3
PM43
P43
PU43
−
−
−
√
−
−
−
−
−
−
−
4
−
−
−
−
−
−
−
−
−
−
−
−
−
−
5
−
−
−
−
−
−
−
−
−
−
−
−
−
−
6
−
−
−
−
−
−
−
−
−
−
−
−
−
−
7
−
−
−
−
−
−
−
−
−
−
−
−
−
−
0
PM50
P50
PU50
PIM50
POM50
−
√
√
√
√
√
√
√
√
1
PM51
P51
PU51
−
POM51
−
√
√
√
√
√
√
√
√
2
PM52
P52
PU52
−
−
−
√
−
−
−
−
−
−
−
3
PM53
P53
PU53
−
−
−
√
−
−
−
−
−
−
−
4
PM54
P54
PU54
−
−
−
√
−
−
−
−
−
−
−
5
PM55
P55
PU55
PIM55
POM55
−
√
−
−
−
−
−
−
−
6
−
−
−
−
−
−
−
−
−
−
−
−
−
−
7
−
−
−
−
−
−
−
−
−
−
−
−
−
−
0
PM60
P60
−
−
−
−
√
√
√
√
√
√
√
√
1
PM61
P61
−
−
−
−
√
√
√
√
√
√
√
√
2
PM62
P62
−
−
−
−
√
√
√
√
√
√
√
−
3
PM63
P63
−
−
−
−
√
√
√
√
−
−
−
−
4
−
−
−
−
−
−
−
−
−
−
−
−
−
−
5
−
−
−
−
−
−
−
−
−
−
−
−
−
−
6
−
−
−
−
−
−
−
−
−
−
−
−
−
−
7
−
−
−
−
−
−
−
−
−
−
−
−
−
−
0
PM70
P70
PU70
−
−
−
√
√
√
√
√
√
√
−
1
PM71
P71
PU71
−
POM71
−
√
√
√
√
√
√
−
−
2
PM72
P72
PU72
−
−
−
√
√
√
√
√
√
−
−
3
PM73
P73
PU73
−
−
−
√
√
√
√
√
−
−
−
4
PM74
P74
PU74
−
POM74
−
√
√
√
−
−
−
−
−
5
PM75
P75
PU75
−
−
−
√
√
√
−
−
−
−
−
6
PM76
P76
PU76
−
−
−
√
√
−
−
−
−
−
−
7
PM77
P77
PU77
−
−
−
√
√
−
−
−
−
−
−
R01UH0186EJ0100 Rev.1.00
Dec 28, 2011
232
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CHAPTER 4 PORT FUNCTIONS
Table 4-22. PMxx, Pxx, PUxx, PIMxx, POMxx, PMCxx registers and the bits mounted on each product
(30-pin products to 64-pin products) (3/3)
Port
Port 12
Port 13
Port 14
Bit name
64-
52-
48-
44-
40-
36-
32-
30-
pin
pin
pin
pin
pin
pin
pin
pin
PMxx
Pxx
PUxx
PIMxx
POMxx
PMCxx
register
register
register
register
register
register
0
PM120
P120
PU120
−
−
PMC120
√
√
√
√
√
√
√
√
1
−
P121
−
−
−
−
√
√
√
√
√
√
√
√
2
−
P122
−
−
−
−
√
√
√
√
√
√
√
√
3
−
P123
−
−
−
−
√
√
√
√
√
−
−
−
4
−
P124
−
−
−
−
√
√
√
√
√
−
−
−
5
−
−
−
−
−
−
−
−
−
−
−
−
−
−
6
−
−
−
−
−
−
−
−
−
−
−
−
−
−
7
−
−
−
−
−
−
−
−
−
−
−
−
−
−
0
−
P130
−
−
−
−
√
√
√
−
−
−
−
−
1
−
−
−
−
−
−
−
−
−
−
−
−
−
−
2
−
−
−
−
−
−
−
−
−
−
−
−
−
−
3
−
−
−
−
−
−
−
−
−
−
−
−
−
−
4
−
−
−
−
−
−
−
−
−
−
−
−
−
−
5
−
−
−
−
−
−
−
−
−
−
−
−
−
−
6
−
−
−
−
−
−
−
−
−
−
−
−
−
−
7
−
P137
−
−
−
−
√
√
√
√
√
√
√
√
0
PM140
P140
PU140
−
−
−
√
√
√
−
−
−
−
−
1
PM141
P141
PU141
−
−
−
√
−
−
−
−
−
−
−
2
−
−
−
−
−
−
−
−
−
−
−
−
−
−
3
−
−
−
−
−
−
−
−
−
−
−
−
−
−
4
−
−
−
−
−
−
−
−
−
−
−
−
−
−
5
−
−
−
−
−
−
−
−
−
−
−
−
−
−
6
PM146
P146
PU146
−
−
−
√
√
√
√
−
−
−
−
7
PM147
P147
PU147
−
−
PMC147
√
√
√
√
√
√
√
√
R01UH0186EJ0100 Rev.1.00
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233
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CHAPTER 4 PORT FUNCTIONS
Table 4-23. PMxx, Pxx, PUxx, PIMxx, POMxx, PMCxx registers and the bits mounted on each product
(80-pin products to 128-pin products) (1/4)
Port
Port 0
Port 1
Port 2
Port 3
R01UH0186EJ0100 Rev.1.00
Dec 28, 2011
Bit name
100-
80-
pin
pin
PMxx
Pxx
PUxx
PIMxx
POMxx
PMCxx
register
register
register
register
register
register
0
PM00
P00
PU00
−
POM00
−
√
√
1
PM01
P01
PU01
PIM01
−
−
√
√
2
PM02
P02
PU02
−
POM02
PMC02
√
√
3
PM03
P03
PU03
PIM03
POM03
PMC03
√
√
4
PM04
P04
PU04
PIM04
POM04
−
√
√
5
PM05
P05
PU05
−
−
−
√
√
6
PM06
P06
PU06
−
−
−
√
√
7
−
−
−
−
−
−
−
−
0
PM10
P10
PU10
PIM10
POM10
−
√
√
1
PM11
P11
PU11
−
POM11
−
√
√
2
PM12
P12
PU12
−
−
PMC12
√
√
3
PM13
P13
PU13
−
POM13
PMC13
√
√
4
PM14
P14
PU14
PIM14
POM14
−
√
√
5
PM15
P15
PU15
PIM15
POM15
−
√
√
6
PM16
P16
PU16
PIM16
−
PMC16
√
√
7
PM17
P17
PU17
PIM17
POM17
PMC17
√
√
0
PM20
P20
−
−
−
−
√
√
1
PM21
P21
−
−
−
−
√
√
2
PM22
P22
−
−
−
−
√
√
−
−
−
√
√
3
PM23
P23
−
4
PM24
P24
−
−
−
−
√
√
5
PM25
P25
−
−
−
−
√
√
6
PM26
P26
−
−
−
−
√
√
7
PM27
P27
−
−
−
−
√
√
0
PM30
P30
PU30
PIM30
POM30
−
√
√
1
PM31
P31
PU31
−
−
−
√
√
2
−
−
−
−
−
−
−
−
3
−
−
−
−
−
−
−
−
4
−
−
−
−
−
−
−
−
5
−
−
−
−
−
−
−
−
6
−
−
−
−
−
−
−
−
7
−
−
−
−
−
−
−
−
234
RL78/G14
CHAPTER 4 PORT FUNCTIONS
Table 4-23. PMxx, Pxx, PUxx, PIMxx, POMxx, PMCxx registers and the bits mounted on each product
(80-pin products and 100-pin products) (2/4)
Port
Port 4
Port 5
Port 6
Port 7
Port 8
R01UH0186EJ0100 Rev.1.00
Dec 28, 2011
Bit name
100-
80pin
PMxx
register
Pxx
register
PUxx
register
PIMxx
register
POMxx
register
PMCxx
register
pin
0
PM40
P40
PU40
−
−
−
√
√
1
PM41
P41
PU41
−
−
−
√
√
2
PM42
P42
PU42
−
−
−
√
√
3
PM43
P43
PU43
PIM43
POM43
−
√
√
4
PM44
P44
PU44
PIM44
POM44
−
√
√
5
PM45
P45
PU45
−
POM45
−
√
√
6
PM46
P46
PU46
−
−
−
√
−
7
PM47
P47
PU47
−
−
−
√
−
0
PM50
P50
PU50
PIM50
POM50
−
√
√
1
PM51
P51
PU51
−
POM51
−
√
√
2
PM52
P52
PU52
−
POM52
−
√
√
3
PM53
P53
PU53
PIM53
POM53
−
√
√
4
PM54
P54
PU54
PIM54
POM54
−
√
√
5
PM55
P55
PU55
PIM55
POM55
−
√
√
6
PM56
P56
PU56
−
−
−
√
−
7
PM57
P57
PU57
−
−
−
√
−
0
PM60
P60
−
−
−
−
√
√
1
PM61
P61
−
−
−
−
√
√
2
PM62
P62
−
−
−
−
√
√
3
PM63
P63
−
−
−
−
√
√
4
PM64
P64
PU64
−
−
−
√
√
5
PM65
P65
PU65
−
−
−
√
√
6
PM66
P66
PU66
−
−
−
√
√
7
PM67
P67
PU67
−
−
−
√
√
0
PM70
P70
PU70
−
−
−
√
√
1
PM71
P71
PU71
−
POM71
−
√
√
2
PM72
P72
PU72
−
−
−
√
√
3
PM73
P73
PU73
−
−
−
√
√
4
PM74
P74
PU74
−
POM74
−
√
√
5
PM75
P75
PU75
−
−
−
√
√
6
PM76
P76
PU76
−
−
−
√
√
7
PM77
P77
PU77
−
−
−
√
√
0
PM80
P80
PU80
PIM80
POM80
−
√
−
1
PM81
P81
PU81
PIM81
POM81
−
√
−
2
PM82
P82
PU82
−
POM82
−
√
−
3
PM83
P83
PU83
−
−
−
√
−
4
PM84
P84
PU84
−
−
−
√
−
5
PM85
P85
PU85
−
−
−
√
−
6
PM86
P86
PU86
−
−
−
√
−
7
PM87
P87
PU87
−
−
−
√
−
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Table 4-23. PMxx, Pxx, PUxx, PIMxx, POMxx, PMCxx registers and the bits mounted on each product
(80-pin products and 100-pin products) (3/4)
Port
Port 10
Port 11
Port 12
Port 13
R01UH0186EJ0100 Rev.1.00
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Bit name
100-
80-
pin
pin
PMxx
Pxx
PUxx
PIMxx
POMxx
PMCxx
register
register
register
register
register
register
0
PM100
P100
PU100
−
−
PMC110
√
√
1
PM101
P101
PU101
−
−
−
√
−
2
PM102
P102
PU102
−
−
−
√
−
3
−
−
−
−
−
−
−
−
4
−
−
−
−
−
−
−
−
5
−
−
−
−
−
−
−
−
6
−
−
−
−
−
−
−
−
7
−
−
−
−
−
−
−
−
0
PM110
P110
PU110
−
−
−
√
√
1
PM111
P111
PU111
−
−
−
√
√
2
−
−
−
−
−
−
−
−
3
−
−
−
−
−
−
−
−
4
−
−
−
−
−
−
−
−
5
−
−
−
−
−
−
−
−
6
−
−
−
−
−
−
−
−
7
−
−
−
−
−
−
−
−
0
PM120
P120
PU120
−
−
PMC120
√
√
1
−
P121
−
−
−
−
√
√
2
−
P122
−
−
−
−
√
√
3
−
P123
−
−
−
−
√
√
4
−
P124
−
−
−
−
√
√
5
−
−
−
−
−
−
−
−
6
−
−
−
−
−
−
−
−
7
−
−
−
−
−
−
−
−
0
−
P130
−
−
−
−
√
√
1
−
−
−
−
−
−
−
−
2
−
−
−
−
−
−
−
−
3
−
−
−
−
−
−
−
−
4
−
−
−
−
−
−
−
−
5
−
−
−
−
−
−
−
−
6
−
−
−
−
−
−
−
−
7
−
P137
−
−
−
−
√
√
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CHAPTER 4 PORT FUNCTIONS
Table 4-23. PMxx, Pxx, PUxx, PIMxx, POMxx, PMCxx registers and the bits mounted on each product
(80-pin products and 100-pin products) (4/4)
Port
Port 14
Port 15
Bit name
100-
80pin
PMxx
register
Pxx
register
PUxx
register
PIMxx
register
POMxx
register
PMCxx
register
pin
0
PM140
P140
PU140
−
−
−
√
√
1
PM141
P141
PU141
−
−
−
√
√
2
PM142
P142
PU142
PIM142 POM142
−
√
√
3
PM143
P143
PU143
PIM143 POM143
−
√
√
4
PM144
P144
PU144
−
POM144
−
√
√
5
PM145
P145
PU145
−
−
−
√
−
6
PM146
P146
PU146
−
−
−
√
√
7
PM147
P147
PU147
−
−
PMC147
√
√
0
PM150
P150
−
−
−
−
√
√
1
PM151
P151
−
−
−
−
√
√
2
PM152
P152
−
−
−
−
√
√
3
PM153
P153
−
−
−
−
√
√
4
PM154
P154
−
−
−
−
√
−
5
PM155
P155
−
−
−
−
√
−
6
PM156
P156
−
−
−
−
√
−
7
−
−
−
−
−
−
−
−
The format of each register is described below. The description here uses the 100-pin products as an example.
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For the registers mounted on others than 100-pin products, refer to table 4-22 and 4-23.
(1) Port mode registers (PMxx)
These registers specify input or output mode for the port in 1-bit units.
These registers can be set by a 1-bit or 8-bit memory manipulation instruction.
Reset signal generation sets these registers to FFH.
When port pins are used as alternate-function pins, set the port mode register by referencing 4.5 Settings of Port
Mode Register, and Output Latch When Using Alternate Function.
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Figure 4-59. Format of Port Mode Register (100-pin products)
Symbol
7
6
5
4
3
2
1
0
Address
After reset
R/W
PM0
1
PM06
PM05
PM04
PM03
PM02
PM01
PM00
FFF20H
FFH
R/W
PM1
PM17
PM16
PM15
PM14
PM13
PM12
PM11
PM10
FFF21H
FFH
R/W
PM2
PM27
PM26
PM25
PM24
PM23
PM22
PM21
PM20
FFF22H
FFH
R/W
PM3
1
1
1
1
1
1
PM31
PM30
FFF23H
FFH
R/W
PM4
PM47
PM46
PM45
PM44
PM43
PM42
PM41
PM40
FFF24H
FFH
R/W
PM5
PM57
PM56
PM55
PM54
PM53
PM52
PM51
PM50
FFF25H
FFH
R/W
PM6
PM67
PM66
PM65
PM64
PM63
PM62
PM61
PM60
FFF26H
FFH
R/W
PM7
PM77
PM76
PM75
PM74
PM73
PM72
PM71
PM70
FFF27H
FFH
R/W
PM8
PM87
PM86
PM85
PM84
PM83
PM82
PM81
PM80
FFF28H
FFH
R/W
PM10
1
1
1
1
1
PM102
PM101
PM100
FFF2AH
FFH
R/W
PM11
1
1
1
1
1
1
PM111
PM110
FFF2BH
FFH
R/W
PM12
1
1
1
1
1
1
1
PM120
FFF2CH
FFH
R/W
PM14
PM147
PM146
PM145
PM144
PM143
PM142
PM141
PM140
FFF2EH
FFH
R/W
PM15
1
PM156
PM155
PM154
PM153
PM152
PM151
PM150
FFF2FH
FFH
R/W
Pmn pin I/O mode selection
PMmn
(m = 0 to 8, 10 to 12, 14, 15; n = 0 to 7)
0
Output mode (output buffer on)
1
Input mode (output buffer off)
Caution Be sure to set bit 7 of the PM0 register, bits 2 to 7 of the PM3 register, bits 3 to 7 of the PM10 register,
bits 2 to 7 of the PM11 register, bits 1 to 7 of the PM12 register, and bit 7 of the PM15 register to “1”.
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CHAPTER 4 PORT FUNCTIONS
(2) Port registers (Pxx)
These registers set the output latch value of a port.
If the data is read in the input mode, the pin level is read. If it is read in the output mode, the output latch value is
readNote.
These registers can be set by a 1-bit or 8-bit memory manipulation instruction.
Reset signal generation clears these registers to 00H.
Note If P02, P03, P20 to P27, P100, P120, and P147 are set up as analog inputs of the A/D converter or P12, P13,
P16, and P17 are set up as analog inputs of the comparator, or when a port is read while in the input mode, 0
is always returned, not the pin level.
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CHAPTER 4 PORT FUNCTIONS
Figure 4-60. Format of Port Register (100-pin products)
Symbol
7
6
5
4
3
2
1
0
Address
P0
0
P06
P05
P04
P03
P02
P01
P00
FFF00H
00H (output latch) R/W
P1
P17
P16
P15
P14
P13
P12
P11
P10
FFF01H
00H (output latch) R/W
P2
P27
P26
P25
P24
P23
P22
P21
P20
FFF02H
00H (output latch) R/W
P3
0
0
0
0
0
0
P31
P30
FFF03H
00H (output latch) R/W
P4
P47
P46
P45
P44
P43
P42
P41
P40
FFF04H
00H (output latch) R/W
P5
P57
P56
P55
P54
P53
P52
P51
P50
FFF05H
00H (output latch) R/W
P6
P67
P66
P65
P64
P63
P62
P61
P60
FFF06H
00H (output latch) R/W
P7
P77
P76
P75
P74
P73
P72
P71
P70
FFF07H
00H (output latch) R/W
P8
P87
P86
P85
P84
P83
P82
P81
P80
FFF08H
00H (output latch) R/W
P10
0
0
0
0
0
P102
P101
P100
FFF0AH
00H (output latch) R/W
P11
0
0
0
0
0
0
P111
P110
FFF0BH
00H (output latch) R/W
P12
0
0
0
P124
P123
P122
P121
P120
FFF0CH
Undefined
R/W
Note
P13
P137
0
0
0
0
0
0
P130
FFF0DH
Undefined
R/W
Note
P14
P147
P146
P145
P144
P143
P142
P141
P140
FFF0EH
00H (output latch) R/W
P15
0
P156
P155
P154
P153
P152
P151
P150
FFF0FH
00H (output latch) R/W
Pmn
After reset
R/W
m = 0 to 8, 10 to 15; n = 0 to 7
Output data control (in output mode)
Input data read (in input mode)
0
Output 0
Input low level
1
Output 1
Input high level
Note P121 to P124, and P137 are read-only.
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CHAPTER 4 PORT FUNCTIONS
(3) Pull-up resistor option registers (PUxx)
These registers specify whether the on-chip pull-up resistors are to be used or not. On-chip pull-up resistors can be
used in 1-bit units only for the bits set to input mode (PMmn = 1 and POMmn = 0) for the pins to which the use of an
on-chip pull-up resistor has been specified in these registers. On-chip pull-up resistors cannot be connected to bits
set to output mode and bits used as alternate-function output pins, regardless of the settings of these registers.
These registers can be set by a 1-bit or 8-bit memory manipulation instruction.
Reset signal generation clears these registers to 00H (Only PU4 is set to 01H).
Figure 4-61. Format of Pull-up Resistor Option Register (100-pin products)
Symbol
7
6
5
4
3
2
1
0
Address
After reset
R/W
PU0
0
PU06
PU05
PU04
PU03
PU02
PU01
PU00
F0030H
00H
R/W
PU1
PU17
PU16
PU15
PU14
PU13
PU12
PU11
PU10
F0031H
00H
R/W
PU3
0
0
0
0
0
0
PU31
PU30
F0033H
00H
R/W
PU4
PU47
PU46
PU45
PU44
PU43
PU42
PU41
PU40
F0034H
01H
R/W
PU5
PU57
PU56
PU55
PU54
PU53
PU52
PU51
PU50
F0035H
00H
R/W
PU6
PU67
PU66
PU65
PU64
0
0
0
0
F0036H
00H
R/W
PU7
PU77
PU76
PU75
PU74
PU73
PU72
PU71
PU70
F0037H
00H
R/W
PU8
PU87
PU86
PU85
PU84
PU83
PU82
PU81
PU80
F0038H
00H
R/W
PU10
0
0
0
0
0
PU102
PU101
PU100
F003AH
00H
R/W
PU11
0
0
0
0
0
0
PU111
PU110
F003BH
00H
R/W
PU12
0
0
0
0
0
0
0
PU120
F003CH
00H
R/W
PU14
PU147
PU146
PU145
PU144
PU143
PU142
PU141
PU140
F003EH
00H
R/W
Pmn pin on-chip pull-up resistor selection
PUmn
(m = 0, 1, 3 to 8, 10 to 12, 14; n = 0 to 7)
0
On-chip pull-up resistor not connected
1
On-chip pull-up resistor connected
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CHAPTER 4 PORT FUNCTIONS
(4) Port input mode registers (PIM0, PIM1, PIM3 to PIM5, PIM8, PIM14)
These registers set the input buffer of P01, P03, P04, P10, P14 to P17, P30, P43, P44, P50, P53 to P55, P80, P81,
P142, and P143 in 1-bit units.
TTL input buffer can be selected during serial communication with an external device of the different potential.
These registers can be set by a 1-bit or 8-bit memory manipulation instruction.
Reset signal generation clears these registers to 00H.
Figure 4-62. Format of Port Input Mode Register (100-pin products)
<R>
Symbol
7
6
5
4
3
2
1
0
Address
After reset
R/W
PIM0
0
0
0
PIM04
PIM03
0
PIM01
0
F0040H
00H
R/W
PIM1
PIM17
PIM16
PIM15
PIM14
0
0
0
PIM10
F0041H
00H
R/W
PIM3
0
0
0
0
0
0
0
PIM30
F0043H
00H
R/W
PIM4
0
0
0
PIM44
PIM43
0
0
0
F0044H
00H
R/W
PIM5
0
0
PIM55
PIM54
PIM53
0
0
PIM50
F0045H
00H
R/W
PIM8
0
0
0
0
0
0
PIM81
PIM80
F0048H
00H
R/W
PIM14
0
0
0
0
PIM143
PM142
0
0
F004EH
00H
R/W
Pmn pin input buffer selection
PIMmn
(m = 0, 1, 3 to 5, 8, 14; n = 0 to 7)
0
Normal input buffer
1
TTL input buffer
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CHAPTER 4 PORT FUNCTIONS
(5) Port output mode registers (POM0, POM1, POM3 to POM5, POM7, POM8, POM14)
These registers set the output mode of P00, P02 to P04, P10, P11, P13 to P15, P17, P30, P43 to P45, P50 to P55,
P71, P74, P80 to P82, P142 to P144 in 1-bit units.
N-ch open-drain output (EVDD0 tolerance) mode can be selected during serial communication with an external device
of the different potential, and for the SDA00, SDA01, SDA10, SDA11, SDA20, SDA21, SDA30, and SDA31 pins
2
during simplified I C communication with an external device of the same potential.
These registers can be set by a 1-bit or 8-bit memory manipulation instruction.
Reset signal generation clears these registers to 00H.
Figure 4-63. Format of Port Output Mode Register (100-pin products)
Symbol
7
6
5
4
3
2
1
0
Address
After reset
R/W
POM0
0
0
0
POM04
POM03
POM02
0
POM00
F0050H
00H
R/W
POM1
POM17
0
POM15
POM14
POM13
0
POM11
POM10
F0051H
00H
R/W
POM3
0
0
0
0
0
0
0
POM30
F0053H
00H
R/W
POM4
0
0
POM45
POM44
POM43
0
0
0
F0054H
00H
R/W
POM5
0
0
POM55
POM54
POM53
POM52
POM51
POM50
F0055H
00H
R/W
POM7
0
0
0
POM74
0
0
POM71
0
F0057H
00H
R/W
POM8
0
0
0
0
0
POM82
POM81
POM80
F0058H
00H
R/W
POM14
0
0
0
0
0
F005EH
00H
R/W
POM144 POM143 POM142
Pmn pin output mode selection
POMmn
(m = 0, 1, 3 to 5, 7, 8, 14; n = 0 to 5, 7)
0
Normal output mode
1
N-ch open-drain output (EVDD0 tolerance) mode
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(6) Port mode control registers (PMC0, PMC1, PMC10, PMC12, PMC14)
These registers set the P02, P03, P12, P13, P16, P17, P100, P120, and P147 digital I/O/analog input in 1-bit units.
These registers can be set by a 1-bit or 8-bit memory manipulation instruction.
Reset signal generation clears these registers to FFH.
Figure 4-64. Format of Port Mode Control Register (100-pin products)
<R>
Symbol
7
6
5
4
3
2
1
0
Address
After reset
R/W
PMC0
1
1
1
1
PMC03
PMC02
PMC01
PMC00
F0060H
FFH
R/W
Note 2
Note 2
Note 1
Note 1
PMC13
PMC12
0
0
F0061H
00H
R/W
Note 3
Note 3
1
1
1
PMC100
F006AH
FFH
R/W
PMC1
PMC17
PMC16
Note 3
Note 3
1
1
PMC10
0
1
0
1
Note 4
PMC12
1
1
1
1
1
1
1
PMC120
F006CH
FFH
R/W
PMC14
PMC147
1
1
1
1
1
1
1
F006EH
FFH
R/W
Pmn pin digital I/O/analog input selection
PMCmn
(m = 0, 1, 10, 12, 14; n = 0, 2, 3, 6, 7)
Notes 1.
0
Digital I/O (alternate function other than analog input)
1
Analog input
30-, 32-pin products only
2.
52-, 64-, 80-, 100-pin products only
3.
96 KB or more code flash memory products only
4.
80-, 100-pin products only
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(7) A/D port configuration register (ADPC)
This register is used to switch the P20/ANI0, P21/ANI1, P22/ANI2/ANO0, P23/ANI3/ANO1, P24/ANI4 to P27/ANI7,
ANI8/P150 to ANI14/P156 pins to digital I/O of port or analog input of A/D converter and to switch the
P22/ANO0/ANI2 and P23/ANO1/ANI3 pins to digital I/O of port or analog output of D/A converter.
The ADPC register can be set by an 8-bit memory manipulation instruction.
Reset signal generation sets this register to 00H.
Figure 4-65. Format of A/D Port Configuration Register (ADPC)
Address: F0076H
After reset: 00H
R/W
Symbol
7
6
5
4
3
2
1
0
ADPC
0
0
0
0
ADPC3
ADPC2
ADPC1
ADPC0
ADPC3
ADPC2
ADPC1
ADPC0
ANI14/P156
ANI13/P155
ANI12/P154
ANI11/P153
ANI10/P152
ANI9/P151
ANI8/P150
ANI7/P27
ANI6/P26
ANI5/P25
ANI4/P24
ANI3/ANO1/P23
ANI2/ANO0/P22
ANI1/P21
ANI0/P20
Analog I/O (A)/digital I/O (D) switching
0
0
0
0
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
0
0
0
1
D
D
D
D
D
D
D
D
D
D
D
D
D
D
D
0
0
1
0
D
D
D
D
D
D
D
D
D
D
D
D
D
D
A
0
0
1
1
D
D
D
D
D
D
D
D
D
D
D
D
D
A
A
0
1
0
0
D
D
D
D
D
D
D
D
D
D
D
D
A
A
A
0
1
0
1
D
D
D
D
D
D
D
D
D
D
D
A
A
A
A
0
1
1
0
D
D
D
D
D
D
D
D
D
D
A
A
A
A
A
0
1
1
1
D
D
D
D
D
D
D
D
D
A
A
A
A
A
A
1
0
0
0
D
D
D
D
D
D
D
D
A
A
A
A
A
A
A
1
0
0
1
D
D
D
D
D
D
D
A
A
A
A
A
A
A
A
1
0
1
0
D
D
D
D
D
D
A
A
A
A
A
A
A
A
A
1
0
1
1
D
D
D
D
D
A
A
A
A
A
A
A
A
A
A
1
1
0
0
D
D
D
D
A
A
A
A
A
A
A
A
A
A
A
1
1
0
1
D
D
D
A
A
A
A
A
A
A
A
A
A
A
A
1
1
1
0
D
D
A
A
A
A
A
A
A
A
A
A
A
A
A
1
1
1
1
D
A
A
A
A
A
A
A
A
A
A
A
A
A
A
Other than above
Setting prohibited
Cautions 1. Set the channel used for A/D conversion to the input mode by using port mode registers 2, 15
(PM2, PM15).
2. Set the channel used for D/A conversion to the input mode by using port mode register 2 (PM2).
3. Do not set the pin set by the ADPC register as digital I/O by the analog input channel
specification register (ADS).
4. Do not set the pin set by the ADPC register as digital I/O by D/A converter mode register (DAM)
as D/A conversion operation enable.
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(8) Peripheral I/O redirection register 0 (PIOR0)
This register is used to specify whether to enable or disable the peripheral I/O redirect function.
This function is used to switch ports to which alternate functions are assigned.
The PIOR0 register can be set by an 8-bit memory manipulation instruction.
Reset signal generation sets this register to 00H.
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Figure 4-66. Format of Peripheral I/O Redirection Register 0 (PIOR0)
Address: F0077H
After reset: 00H
R/W
Symbol
7
6
5
4
3
2
1
0
PIOR0
0
0
PIOR05
PIOR04
PIOR03
PIOR02
PIOR01
PIOR00
Bit
PIOR05
PIOR04
Function
100-pin
80-pin
Setting value
Setting value
0
1
INTP1
P46
P56
INTP3
P30
P57
INTP4
P31
P146
INTP6
P140
P84
INTP7
P141
P85
INTP8
P74
P86
INTP9
P75
P87
TxD1
P02
P82
RxD1
P03
P81
SCL10
P04
P80
SDA10
P03
P81
SI10
P03
P81
SO10
P02
P82
0
64-pin
1
52-pin
48-pin
Setting value Setting value
0
1
0
1
44-pin
40/36/32/30-pin
Setting value Setting value Setting value
0
1
0
1
0
1
This area cannot be used. Be set to 0 (default value).
SCK10
P04
P80
PCLBUZ1
P141
P55
P141
P55
P141
P55
INTP5
P16
P12
P16
P12
P16
P12
PIOR03
PCLBUZ0
P140
P31
P140
P31
P140
P31
P140
P31
P140
P31
PIOR02
SCLA0
P60
P14
P60
P14
P60
P14
P60
P14
P60
P14
P60
P14
P60
P14
SDAA0
P61
P15
P61
P15
P61
P15
P61
P15
P61
P15
P61
P15
P61
P15
PIOR01
INTP10
P76
P100
P76
P100
P76
P05
P76
−
−
−
−
−
−
−
INTP11
P77
P110
P77
P110
P77
P06
P77
−
−
−
−
−
−
−
PIOR00
TxD2
P13
P77
P13
P77
P13
P77
P13
P77
P13
−
P13
−
P13
−
RxD2
P14
P76
P14
P76
P14
P76
P14
P76
P14
−
P14
−
P14
−
SCL20
P15
−
P15
−
P15
−
P15
−
P15
−
P15
−
P15
−
SDA20
P14
−
P14
−
P14
−
P14
−
P14
−
P14
−
P14
−
SI20
P14
−
P14
−
P14
−
P14
−
P14
−
P14
−
P14
−
SO20
P13
−
P13
−
P13
−
P13
−
P13
−
P13
−
P13
−
SCK20
P15
−
P15
−
P15
−
P15
−
P15
−
P15
−
P15
−
TxD0
P51
P17
P51
P17
P51
P17
P51
P17
P51
P17
P51
P17
P51
P17
RxD0
P50
P16
P50
P16
P50
P16
P50
P16
P50
P16
P50
P16
P50
P16
SCL00
P30
−
P30
−
P30
−
P30
−
P30
−
P30
−
P30
−
SDA00
P50
−
P50
−
P50
−
P50
−
P50
−
P50
−
P50
−
SI00
P50
P16
P50
P16
P50
P16
P50
−
P50
−
P50
−
P50
−
SO00
P51
P17
P51
P17
P51
P17
P51
−
P51
−
P51
−
P51
−
SCK00
P30
P55
P30
P55
P30
P55
P30
−
P30
−
P30
−
P30
−
P50
P52
P50
P52
P51
P53
P51
P53
P30
P54
P30
P54
P31
P55
P31
P55
INTP1
INTP2
INTP3
INTP4
INTP8
This area
cannot be
used. Be
set to 0
(default
value).
INTP9
P74
P42
P74
P42
P75
P43
P75
P43
This area cannot be used. Be set to 0 (default value).
(Cautions are listed on the next page)
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Cautions 1. If bit 1 (PIOR01) of the PIOR0 register is set to 1, the TxD2 and RxD2 pins are redirected, but
SCL20, SDA20, SI20, SO20, SCK20 pins are not redirected. Therefore, IIC20 and CSI20 cannot be
used in its setting. However, even if the bit is set to 1, CSI21/IIC21 can be used if UART2 is not
used.
2. If bit 1 (PIOR01) of the PIOR0 register is set to 1, the SO00 and SI00 pins are redirected even in
the 52-pin or less products, but the SCK00 pin is not redirected. Therefore, CSI00 cannot be
used in its setting.
(9) Peripheral I/O redirection register 1 (PIOR1)
This register is used to specify whether to enable or disable the peripheral I/O redirect function.
This function is used to switch ports to which alternate functions are assigned.
The PIOR1 register can be set by an 8-bit memory manipulation instruction.
Reset signal generation sets this register to 00H.
Figure 4-67. Format of Peripheral I/O Redirection Register 1 (PIOR1)
Address: F0079H
After reset: 00H
R/W
Symbol
7
6
5
4
3
2
1
0
PIOR1
0
0
0
0
PIOR13
PIOR12
PIOR11
PIOR10
PIOR13
PIOR12
0
0
Timer RJ TRJO0 pin select
Double as P30/INTP3/RTC1HZ/SCK00/SCL00
0
1
Double as P50/SI00/RxD0/TOOLRxD/SDA00/TRGIOA
1
0
Double as P00/TI00/TRGCLKA
1
1
Setting prohibited
PIOR11
PIOR10
0
0
Double as P01/TO00/TRGCLKB
0
1
Double as P31/TI03/TO03/INTP4
1
0
Double as P41 only in 44-pin, 48-pin, 52-pin, 64-pin, 80-pin, and 100-pin
products
1
1
Double as P06 only in 64-pin. 80-pin and 100-pin products
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(10) Global digital input disable register (GDIDIS)
This register is used to prevent through-current flowing from the input buffers when EVDD is 0 V.
By setting the GDIDIS0 bit to 1, input to any input buffer connected to EVDD is prohibited, preventing through-current
from flowing when the power supply connected to EVDD is turned off.
When using the GDIDIS register, be sure to set the GDIDIS0 bit to 1 before turning off the EVDD power supply, and
then clear the GDIDIS0 bit to 0 after turning on the EVDD power supply.
<R>
The GDIDIS register can be set by a 1-bit or 8-bit memory manipulation instruction.
Reset signal generation sets this register to 00H.
Figure 4-68. Format of Global Digital Input Disable Register (GDIDIS)
Address: F007DH After reset: 00H R/W
Symbol
7
6
5
4
3
2
1
0
GDIDIS
0
0
0
0
0
0
0
GDIDIS0
GDIDIS0
Setting of input buffers when EVDD is 0 V
0
Input to input buffers permitted (default)
1
Input to input buffers prohibited. No through-current flows to the input buffers.
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4.4 Port Function Operations
Port operations differ depending on whether the input or output mode is set, as shown below.
4.4.1 Writing to I/O port
(1) Output mode
A value is written to the output latch by a transfer instruction, and the output latch contents are output from the pin.
Once data is written to the output latch, it is retained until data is written to the output latch again.
The data of the output latch is cleared when a reset signal is generated.
(2) Input mode
A value is written to the output latch by a transfer instruction, but since the output buffer is off, the pin status does not
change.
Once data is written to the output latch, it is retained until data is written to the output latch again.
The data of the output latch is cleared when a reset signal is generated.
4.4.2 Reading from I/O port
(1) Output mode
The output latch contents are read by a transfer instruction. The output latch contents do not change.
(2) Input mode
The pin status is read by a transfer instruction. The output latch contents do not change.
4.4.3 Operations on I/O port
(1) Output mode
An operation is performed on the output latch contents, and the result is written to the output latch. The output latch
contents are output from the pins.
Once data is written to the output latch, it is retained until data is written to the output latch again.
The data of the output latch is cleared when a reset signal is generated.
(2) Input mode
The pin level is read and an operation is performed on its contents. The result of the operation is written to the output
latch, but since the output buffer is off, the pin status does not change.
The data of the output latch is cleared when a reset signal is generated.
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<R> 4.4.4 Connecting to external device with different potential (1.8 V, 2.5 V, 3 V)
It is possible to connect to an external device with a different potential (1.8 V, 2.5 V or 3 V) by changing EVDD0 to
accord with the power supply of the connected device. In products in which EVDD0 cannot be specified independently or if
EVDD0 cannot be changed to accord with the power supply of the connected device for some reason, I/O connection with
an external device operating on 1.8 V, 2.5 V or 3 V when the system is operating on VDD = 4.0 V to 5.5 V is still possible
via the serial interface by using ports 0, 1, 4, 5, and 14.
Regarding inputs, CMOS/TTL switching is possible on a bit-by-bit basis by the port input mode registers (PIM0, PIM1,
PIM3 to PIM5, PIM14).
Moreover, regarding outputs, different potentials can be supported by switching the output buffer to the N-ch open-drain
(EVDD0 tolerance) by the port output mode registers (POM0, POM1, POM3 to POM5, POM7, POM14).
(1) Setting procedure when using I/O pins of UART0 to UART3, CSI00, CSI01, CSI10, CSI20, CSI30, and CSI31
functions
(a) Use as 1.8 V, 2.5 V, 3 V input port
<1> If pull-up is needed, externally pull up the pin to be used (on-chip pull-up resistor cannot be used).
In case of UART0:
P50
In case of UART1:
P03
In case of UART2:
P14
In case of UART3:
P143
In case of CSI00:
P30, P50
In case of CSI01:
P43, P44
In case of CSI10:
P03, P04
In case of CSI20:
P14, P15
In case of CSI30:
P142, P143
In case of CSI31:
P53, P54
<2> After reset release, the port mode is the input mode (Hi-Z).
<3> Set the corresponding bit of the PIM0, PIM1, PIM3 to PIM5, PIM14 registers to 1 to switch to the TTL
input buffer.
<4> VIH/VIL operates on 1.8 V, 2.5 V, 3 V operating voltage.
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(b) Use as 1.8 V, 2.5 V, 3 V output port
<1> Pull up externally the pin to be used (on-chip pull-up resistor cannot be used).
In case of UART0:
P51
In case of UART1:
P02
In case of UART2:
P13
In case of UART3:
P144
In case of CSI00:
P30, P51
In case of CSI01:
P43, P45
In case of CSI10:
P02, P04
In case of CSI20:
P13, P15
In case of CSI30:
P142, P144
In case of CSI31:
P52, P54
<2> After reset release, the port mode is the input mode (Hi-Z).
<3> Set the output latch of the corresponding port to 1.
<4> Set the corresponding bit of the POM0, POM1, POM3 to POM5, and POM14 registers to 1 to set the N-ch
open-drain output (EVDD0 tolerance) mode.
<5> Set the output mode by manipulating the PM0, PM1, PM3 to PM5, and PM14 registers.
At this time, the output data is high level, so the pin is in the Hi-Z state.
<6> Communication is started by setting the serial array unit.
(2) Setting procedure when using I/O pins of simplified IIC00, IIC01, IIC10, IIC11, IIC20, IIC30, and IIC31 functions
<1> Externally pull up the pin to be used (on-chip pull-up resistor cannot be used).
In case of simplified IIC00:
P30, P50
In case of simplified IIC01:
P43, P44
In case of simplified IIC10:
P03, P04
In case of simplified IIC11:
P10, P11
In case of simplified IIC20:
P14, P15
In case of simplified IIC30:
P142, P143
In case of simplified IIC31:
P53, P54
<2> After reset release, the port mode is the input mode (Hi-Z).
<3> Set the output latch of the corresponding port to 1.
<4> Set the corresponding bit of the POM0, POM1, POM3 to POM5, and POM14 registers to 1 to set the N-ch
open-drain output (EVDD0 tolerance) mode.
<5> Set the corresponding bit of the PM0, PM1, PM3 to PM5, and PM14 registers to the output mode (data
I/O is possible in the output mode).
At this time, the output data is high level, so the pin is in the Hi-Z state.
<6> Enable the operation of the serial array unit and set the mode to the simplified IIC mode.
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<R> 4.5 Settings of Port Mode Register, and Output Latch When Using Alternate Function
To use the alternate function of a port pin, set the port mode register, and output latch as shown in Table 4-24.
Table 4-24. Settings of Port Mode Register, and Output Latch When Using Alternate Function (1/6)
Pin
Name
P00
Alternate Function
Function Name
I/O
TI00
Input
TRGCLKA
P01
P02
P××
×
×
−
1
×
×
×
−
1
×
0
Output
PIOR13, PIOR12 = 10B
0
−
0
×
−
−
0
0
TRGCLKA
Input
×
−
−
1
×
TRJIO0
Input
PIOR13, PIOR12 = 00B
−
−
1
×
Output
PIOR13, PIOR12 = 00B
−
−
0
0
Input
Output
Output
Input
Input
Input
I/O
Input
×
PIOR05 = 0
PIOR05 = 0
×
PIOR05 = 0
PIOR05 = 0
PIOR05 = 0
×
0/1
0/1
×
×
×
1
1
0
0
1
0
0
0
1
0
0
1
1
1
0
×
1
1
×
×
×
1
PIOR05 = 0
×
−
1
×
Output
PIOR05 = 0
0/1
−
0
1
SCL10
Output
PIOR05 = 0
0/1
−
0
1
(TRJIO0)
Input
PIOR13, PIOR12 = 11B
-
−
1
×
Output
PIOR13, PIOR12 = 11B
-
−
0
0
SCK10
P12
PM××
Output
P04
P11
PMC××
(TRJO0)
P03
P10
POM××
TO00
ANI17
SO10
TxD1
ANI16
SI10
RxD1
SDA10
P06
Input
PIOR××
SCK11
Input
×
×
−
1
×
Output
×
0/1
−
0
1
SCL11
Output
×
1
−
0
1
TRDIOD1
Input
×
×
−
1
×
Output
×
0
−
0
0
SI11
Input
×
×
−
1
×
SDA11
I/O
×
1
−
0
1
TRDIOC1
Input
×
×
−
1
×
Output
×
0
−
0
0
SO11
Output
×
−
0
0
1
TRDIOB1
Input
×
−
0
1
×
Output
×
−
0
0
0
IVREF1
Input
×
−
1
1
×
(INTP5)
Input
PIOR04 = 1
−
0
1
×
Remarks 1.
2.
3.
×:
don’t care
PIOR×: Peripheral I/O redirection register
POM××: Port output mode register
PMC××: Port mode control register
PM××: Port mode register
P××:
Port output latch
The relationship between pins and their alternate functions shown in this table indicates the relationship
when a 100-pin product is used. In other products, alternate functions might be assigned to different
pins, but even in this case, the PIORxx, POMxx, PMCxx, PMxx, and Pxx set in the same way.
Functions in parentheses in the above table can be assigned via settings in the peripheral I/O
redirection registers 0, 1 (PIOR0, 1).
(The notes are described after the last table.)
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Table 4-24. Settings of Port Mode Register, and Output Latch When Using Alternate Function (2/6)
Pin
Name
P13
P14
P15
P16
P17
P20
Note 4
Alternate Function
Function Name
I/O
PIOR××
POM××
PMC××
PM××
P××
TxD2
Output
PIOR01 = 0
0/1
0
0
1
SO20
Output
PIOR01 = 0
0/1
0
0
1
TRDIOA1
Input
×
×
0
1
×
×
0
0
0
0
IVCMP1
Output
Input
×
×
1
1
×
RxD2
Input
PIOR01 = 0
×
−
1
×
SI20
Input
PIOR01 = 0
×
−
1
×
SDA20
I/O
PIOR01 = 0
1
−
0
1
TRDIOD0
Input
×
×
−
1
×
Output
×
0
−
0
0
(SCLA0)
I/O
PIOR02 = 1
1
−
0
0
SCK20
Input
PIOR01 = 0
×
−
1
×
Output
PIOR01 = 0
0/1
−
0
1
SCL20
Output
PIOR01 = 0
0/1
−
0
1
TRDIOB0
Input
×
×
−
1
×
Output
×
0
−
0
0
PIOR02 = 1
1
−
0
1
(SDAA0)
I/O
TI01
Input
×
−
0
1
×
TO01
Output
×
−
0
0
0
INTP5
Input
PIOR04 = 0
−
0
1
×
TRDIOC0
Input
×
−
0
1
×
Output
×
−
0
0
0
IVREF0
Input
×
−
1
1
×
(SI00)
Input
PIOR01 = 1
−
0
1
×
(RxD0)
Input
PIOR01 = 1
−
0
1
×
TI02
TO02
TRDIOA0
Input
Output
Input
Output
×
×
×
×
×
0
×
0
0
0
0
0
1
0
1
0
×
0
×
0
TRDCLK0
IVCMP0
(SO00)
(TxD0)
ANI0
Input
Input
Output
Output
×
×
PIOR01 = 1
PIOR01 = 1
×
×
0/1
0/1
0
1
0
0
1
1
0
0
×
×
1
1
Input
×
−
−
1
×
AVREFP
Input
×
−
−
1
×
Remarks 1.
2.
3.
×:
don’t care
PIOR×: Peripheral I/O redirection register
POM××: Port output mode register
PMC××: Port mode control register
PM××: Port mode register
P××:
Port output latch
The relationship between pins and their alternate functions shown in this table indicates the relationship
when a 100-pin product is used. In other products, alternate functions might be assigned to different
pins, but even in this case, the PIORxx, POMxx, PMCxx, PMxx, and Pxx set in the same way.
Functions in parentheses in the above table can be assigned via settings in the peripheral I/O
redirection registers 0, 1 (PIOR0, 1).
(The notes are described after the last table.)
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Table 4-24. Settings of Port Mode Register, and Output Latch When Using Alternate Function (3/6)
Pin
Name
Alternate Function
Function Name
PIOR××
POM××
PMC××
PM××
P××
I/O
P21
ANI1
Input
×
−
−
1
×
AVREFM
Input
×
−
−
1
×
P22
ANI2
Input
×
−
−
1
×
ANO0
Output
×
−
−
1
×
ANI3
Input
×
−
−
1
×
ANO1
Output
×
−
−
1
×
P24-P27 ANI4-ANI7
Input
×
−
−
1
×
P30
INTP3
Input
PIOR05 = 0
×
−
1
×
RTC1HZ
Output
×
0
−
0
0
SCK00
Input
PIOR01 = 0
×
−
1
×
P23
P31
Output
PIOR01 = 0
0/1
−
0
1
SCL00
Output
PIOR01 = 0
0/1
−
0
1
TRJO0
Output
PIOR13, PIOR12 = 00B
0
−
0
0
TI03
Input
×
−
−
1
×
TO03
Output
×
−
−
0
0
INTP4
Input
PIOR05 = 0
−
−
1
×
(PCLBUZ0)
Output
PIOR03 = 1
−
−
0
0
(TRJIO0)
Input
PIOR13, PIOR12 = 01B
−
−
1
×
Output
PIOR13, PIOR12 = 01B
−
−
0
0
×
×
P40
TOOL0
I/O
−
−
×
P41
(TRJIO0)
Input
PIOR13, PIOR12 = 10B
−
−
1
×
Output
PIOR13, PIOR12 = 10B
−
−
0
0
Input
×
−
−
1
×
Output
×
−
−
0
1
SCL01
Output
×
−
−
0
1
SI01
Input
×
−
−
1
×
SDA01
I/O
×
−
−
0
1
P45
SO01
Output
×
−
−
0
1
P46
INTP1
Input
PIOR05 = 0
−
−
1
×
P47
INTP2
Input
×
−
−
1
×
P43
P44
SCK01
Remarks 1.
2.
3.
×:
don’t care
PIOR×: Peripheral I/O redirection register
POM××: Port output mode register
PMC××: Port mode control register
PM××: Port mode register
P××:
Port output latch
The relationship between pins and their alternate functions shown in this table indicates the relationship
when a 100-pin product is used. In other products, alternate functions might be assigned to different
pins, but even in this case, the PIORxx, POMxx, PMCxx, PMxx, and Pxx set in the same way.
Functions in parentheses in the above table can be assigned via settings in the peripheral I/O
redirection registers 0, 1 (PIOR0, 1).
(The notes are described after the last table.)
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Table 4-24. Settings of Port Mode Register, and Output Latch When Using Alternate Function (4/6)
Pin
Name
P50
P51
Alternate Function
Function Name
PIOR××
POM××
PMC××
PM××
P××
I/O
SI00
Input
PIOR01 = 0
×
−
1
×
RxD0
Input
PIOR01 = 0
×
−
1
×
TOOLRxD
Input
×
×
−
1
×
SDA00
I/O
PIOR01 = 0
1
−
0
1
TRGIOA
Input
×
×
−
1
×
Output
×
0
−
0
0
(TRJO0)
Output
PIOR13, PIOR12 = 01B
0
−
0
0
SO00
Output
PIOR01 = 0
0/1
−
0
1
TxD0
Output
PIOR01 = 0
0/1
−
0
1
TOOLTxD
Output
×
0/1
−
0
1
TRGIOB
Input
×
×
−
1
×
Output
×
0
−
0
0
P52
SO31
Output
×
0/1
−
0
1
P53
SI31
Input
×
×
−
1
×
SDA31
I/O
×
1
−
0
1
P54
SCK31
Input
×
×
−
1
×
Output
×
0/1
−
0
1
P55
SCL31
Output
×
0/1
−
0
1
(PCLBUZ1)
Output
PIOR04 = 1
0
−
0
0
(SCK00)
Input
PIOR01 = 1
×
−
1
×
Output
PIOR01 = 1
0/1
−
0
1
P56
(INTP1)
Input
PIOR05 = 1
−
−
1
×
P57
(INTP3)
Input
PIOR05 = 1
−
−
1
×
P60
SCLA0
I/O
PIOR02 = 0
−
−
0
0
P61
SDAA0
I/O
PIOR02 = 0
−
−
0
0
P62
SSI00
Input
×
−
−
1
×
SCLA1
I/O
×
−
−
0
0
P63
SDAA1
I/O
×
−
−
0
1
P64
TI10
Input
×
−
−
1
×
TO10
Output
×
−
−
0
0
TI11
Input
×
−
−
1
×
TO11
Output
×
−
−
0
0
P65
Remarks 1.
2.
3.
×:
don’t care
PIOR×: Peripheral I/O redirection register
POM××: Port output mode register
PMC××: Port mode control register
PM××: Port mode register
P××:
Port output latch
The relationship between pins and their alternate functions shown in this table indicates the relationship
when a 100-pin product is used. In other products, alternate functions might be assigned to different
pins, but even in this case, the PIORxx, POMxx, PMCxx, PMxx, and Pxx set in the same way.
Functions in parentheses in the above table can be assigned via settings in the peripheral I/O
redirection registers 0, 1 (PIOR0, 1).
(The notes are described after the last table.)
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Table 4-24. Settings of Port Mode Register, and Output Latch When Using Alternate Function (5/6)
Pin
Name
Alternate Function
Function Name
I/O
PIOR××
POM××
PMC××
PM××
P××
P66
TI12
Input
×
−
−
1
×
TO12
Output
×
−
−
0
0
P67
TI13
Input
×
−
−
1
×
TO13
Output
×
−
−
0
0
KR0
Input
×
−
−
1
×
SCK21
Input
×
−
−
1
×
Output
×
−
−
0
1
P70
P71
SCL21
Output
×
−
−
0
1
KR1
Input
×
×
−
1
×
SI21
Input
×
×
−
1
×
0
1
×
SDA21
I/O
×
1
−
KR2
Input
×
−
−
1
SO21
Output
×
−
−
0
1
P73
KR3
Input
×
−
−
1
×
P74
KR4
Input
×
×
−
1
×
INTP8
Input
PIOR05 = 0
×
−
1
×
KR5
Input
×
−
−
1
×
INTP9
Input
PIOR05 = 0
−
−
1
×
KR6
Input
×
−
−
1
×
INTP10
Input
PIOR01 = 0
−
−
1
×
P72
P75
P76
P77
P80
P81
P82
(RxD2)
Input
PIOR01 = 1
−
−
1
×
KR7
Input
×
−
−
1
×
INTP11
Input
PIOR01 = 0
−
−
1
×
(TxD2)
Output
PIOR01 = 1
−
−
0
1
(SCK10)
Input
PIOR05 = 1
×
−
1
×
Output
PIOR05 = 1
0/1
−
0
1
(SCL10)
Output
PIOR05 = 1
0/1
−
0
1
(SI10)
Input
PIOR05 = 1
×
−
1
×
(RxD1)
Input
PIOR05 = 1
×
−
1
×
(SDA10)
I/O
PIOR05 = 1
1
−
0
1
(SO10)
Output
PIOR05 = 1
0/1
−
0
1
(TxD1)
Output
PIOR05 = 1
0/1
−
0
1
Input
PIOR05 = 1
−
−
1
×
P84-P87 (INTP6) to
(INTP9)
Remarks 1.
2.
3.
×:
don’t care
PIOR×: Peripheral I/O redirection register
POM××: Port output mode register
PMC××: Port mode control register
PM××: Port mode register
P××:
Port output latch
The relationship between pins and their alternate functions shown in this table indicates the relationship
when a 100-pin product is used. In other products, alternate functions might be assigned to different
pins, but even in this case, the PIORxx, POMxx, PMCxx, PMxx, and Pxx set in the same way.
Functions in parentheses in the above table can be assigned via settings in the peripheral I/O
redirection registers 0, 1 (PIOR0, 1).
(The notes are described after the last table.)
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Table 4-24. Settings of Port Mode Register, and Output Latch When Using Alternate Function (6/6)
Pin
Name
PIOR××
POM××
PMC××
PM××
P××
Input
×
−
1
1
×
0
1
×
Alternate Function
Function Name
I/O
P100
ANI20
(INTP10)
Input
PIOR01 = 1
−
P110
(INTP11)
Input
PIOR01 = 1
−
−
1
×
P120
ANI19
Input
×
−
1
1
×
VCOUT0
Output
×
−
0
0
0
P137
INTP0
Input
×
−
−
1
×
P140
PCLBUZ0
Output
PIOR03 = 0
−
−
0
0
INTP6
Input
PIOR05 = 0
−
−
1
×
PCLBUZ1
Output
PIOR04 = 0
−
−
0
0
INTP7
Input
PIOR05 = 0
−
−
1
×
SCK30
Input
×
×
−
1
×
Output
×
0/1
−
0
1
SCL30
Output
×
0/1
−
0
1
SI30
Input
×
×
−
1
×
RxD3
Input
×
×
−
1
×
SDA30
I/O
×
1
−
0
1
SO30
Output
×
0/1
−
0
1
TxD3
Output
×
0/1
−
0
1
P146
(INTP4)
Input
PIOR05 = 1
−
−
1
×
P147
ANI18
Input
×
−
1
1
×
VCOUT1
Output
×
−
0
0
0
ANI8 to ANI14
Input
−
−
1
×
P141
P142
P143
P144
P150 to
P156
Remarks 1.
2.
3.
×
×:
don’t care
PIOR×: Peripheral I/O redirection register
POM××: Port output mode register
PMC××: Port mode control register
PM××: Port mode register
P××:
Port output latch
The relationship between pins and their alternate functions shown in this table indicates the relationship
when a 100-pin product is used. In other products, alternate functions might be assigned to different
pins, but even in this case, the PIORxx, POMxx, PMCxx, PMxx, and Pxx set in the same way.
Functions in parentheses in the above table can be assigned via settings in the peripheral I/O
redirection registers 0, 1 (PIOR0, 1).
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Notes 1. The functions of the ANI16/P03, ANI17/P02, ANI18/VCOUT1/P147, ANI19/VCOUT0/P120, ANI20/P100,
IVREF0/P16, IVCMP0/P17, IVREF1/P12, and IVCMP1/P13 pins can be selected by using the port mode
control registers 0, 1, 10, 12, 14 (PMC0, PMC1, PMC10, PMC12, PMC14), analog input channel
specification register (ADS), and port mode registers 0, 1, 10, 12, 14 (PM0, PM1, PM10, PM12, PM14).
Table 4-25. Settings Function of ANI16/P03, ANI17/P02, ANI18/VCOUT1/P147, ANI19/VCOUT0/P120, ANI20/P100,
IVREF0/P16, IVCMP0/P17, IVREF1/P12, and IVCMP1/P13 Pins
PMC0, PMC1, PMC10,
PMC12, PMC14
Registers
Digital I/O selection
Analog I/O selection
PM0, PM1, PM10,
PM12, PM14
Registers
ADS Register
ANI16/P03, ANI17/P02,
ANI18/VCOUT1/P147,
ANI19/VCOUT0/P120,
ANI20/P100, IVREF0/P16,
IVCMP0/P17, IVREF1/P12,
IVCMP1/P13 Pins
Input mode
−
Digital input
Output mode
−
Digital output (including
comparator output)
Input mode
Output mode
Selects ANI.
Analog input (to be converted)
Does not select ANI.
Analog input (not to be converted)
Selects ANI.
Setting prohibited
Does not select ANI.
2.
The functions of the P20/ANI0, P21/ANI1, P22/ANI2/ANO0, P23/ANI3/ANO1, P24/ANI4 to P27/ANI7 pins
can be selected by using the A/D port configuration register (ADPC), analog input channel specification
register (ADS), D/A converter mode register (DAM), and port mode registers 2 (PM2).
Table 4-26. Setting Functions of P20/ANI0, P21/ANI1, P22/ANI2/ANO0, P23/ANI3/ANO1, P24/ANI4-P27/ANI7 Pins
ADPC Register
PM2 Register
DAM Register
ADS Register
P20/ANI0, P21/ANI1,
P22/ANI2/ANO0, P23/ANI3/ANO1,
P24/ANI4-P27/ANI7
Digital I/O selection
Analog I/O selection
Input mode
−
−
Digital input
Output mode
−
−
Digital output
Input mode
Output mode
Enables D/A conversion
Selects ANI.
Setting prohibited
operation
Does not select ANI.
Analog output
Stops D/A conversion
Selects ANI.
Analog input (to be converted)
operation
Does not select ANI.
Analog input (not to be converted)
Enables D/A conversion
Selects ANI.
Setting prohibited
operation
Does not select ANI.
Stops D/A conversion
Selects ANI.
operation
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Notes 3. The functions of the P150/ANI8 to P156/ANI14 pins can be selected by using the A/D port configuration
register (ADPC), analog input channel specification register (ADS), and port mode register 15 (PM15).
Table 4-27. Settings Function of P150/ANI8 to P156/ANI14 Pins
ADPC Register
Digital I/O selection
Analog input selection
PM15 Register
ADS Register
P150/ANI8 to P156/ANI14 Pins
Input mode
−
Digital input
Output mode
−
Digital output
Input mode
Output mode
Selects ANI.
Analog input (to be converted)
Does not select ANI.
Analog input (not to be converted)
Selects ANI.
Setting prohibited
Does not select ANI.
4.
In the products other than 100-pin products, multiple alternate output functions are assigned to the pins. In
such cases, the output from the alternate functions that are not used in any settings except the one
indicated in table 4-24 must be set to the same value as the one in the initial status. For more detail about
the targets and the method of processing, refer to the section 4.6.2.
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4.6 Cautions When Using Port Function
4.6.1 Cautions on 1-Bit Manipulation Instruction for Port Register n (Pn)
When a 1-bit manipulation instruction is executed on a port that provides both input and output functions, the output
latch value of an input port that is not subject to manipulation may be written in addition to the targeted bit.
Therefore, it is recommended to rewrite the output latch when switching a port from input mode to output mode.
<Example>
When P10 is an output port, P11 to P17 are input ports (all pin statuses are high level), and the port
latch value of port 1 is 00H, if the output of output port P10 is changed from low level to high level via a
1-bit manipulation instruction, the output latch value of port 1 is FFH.
Explanation:
The targets of writing to and reading from the Pn register of a port whose PMnm bit is 1 are the output
latch and pin status, respectively.
A 1-bit manipulation instruction is executed in the following order in the RL78/G14.
<1> The Pn register is read in 8-bit units.
<2> The targeted one bit is manipulated.
<3> The Pn register is written in 8-bit units.
In step <1>, the output latch value (0) of P10, which is an output port, is read, while the pin statuses of
P11 to P17, which are input ports, are read. If the pin statuses of P11 to P17 are high level at this time,
the read value is FEH.
The value is changed to FFH by the manipulation in <2>.
FFH is written to the output latch by the manipulation in <3>.
Figure 4-69. Bit Manipulation Instruction (P10)
1-bit manipulation
instruction
(set1 P1.0)
is executed for P10
bit.
P10
Low-level output
P11 to P17
P10
High-level output
P11 to P17
Pin status: High level
Port 1 output latch
0
0
0
Pin status: High level
Port 1 output latch
0
0
0
0
0
1
1
1
1
1
1
1
1
1-bit manipulation instruction for P10 bit
<1> Port register 1 (P1) is read in 8-bit units.
• In the case of P10, an output port, the value of the port output latch (0) is read.
• In the case of P11 to P17, input ports, the pin status (1) is read.
<2> Set the P10 bit to 1.
<3> Write the results of <2> to the output latch of port register 1 (P1)
in 8-bit units.
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<R> 4.6.2 Cautions on the pin settings on the products other than 100-pin
In the products other than 100-pin products, multiple alternate output functions may be assigned to P15 pin.
In such cases, the output from the alternate functions that are not used in any settings except the one indicated in
Table 4-24 must be set to the same value as the one in the initial status.
The following indicates the specific targets and the method of processing;
(1) 30- to 52-pin products: P15/PCLBUZ1/SCK20/SCL20/TRDIOB0/(SDAA0)
· Using PCLBUZ1: SCK20/SCL20 output set to 1, TRDIOB0 output clear to 0
Set the SO10 bit in serial output register 1 (SO1), the SOE10 bit in serial output enable register 1 (SOE1), and the
SE10 bit in serial channel enable status register 1 (SE1) to the default value.
Set the output control bit in timer RD output master enable register 1 (TRDOER1) for the TRDIOB0 pin to the
default value.
· Using SCK20/SCL20: PCLBUZ1 output clear to 0, TRDIOB0 output clear to 0
Set the PCLOE1 bit in clock output select register 1 (CKS1) to the default value.
Set the output control bit in timer RD output master enable register 1 (TRDOER1) for the TRDIOB0 pin to the
default value.
· Using TRDIOB0: SCK20/SCL20 output set to 1, PCLBUZ1 output clear to 0
Set the PCLOE1 bit in clock output select register 1 (CKS1) to the default value.
Set the SO10 bit in serial output register 1 (SO1), the SOE10 bit in serial output enable register 1 (SOE1), and the
SE10 bit in serial channel enable status register 1 (SE1) to the default value.
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CHAPTER 5 CLOCK GENERATOR
The presence or absence of connecting resonator pin for main system clock, connecting resonator pin for subsystem
clock, external clock input pin for main system clock, and external clock input pin for subsystem clock, depends on the
product.
Caution
30, 32, 36-pin products
40, 44, 48, 52, 64, 80, 100-pin products
X1, X2 pins
√
√
EXCLK pin
√
√
XT1, XT2 pins
−
√
EXCLKS pin
−
√
The 30, 32, and 36-pin products don’t have the subsystem clock.
5.1 Functions of Clock Generator
The clock generator generates the clock to be supplied to the CPU and peripheral hardware.
The following three kinds of system clocks and clock oscillators are selectable.
(1) Main system clock
<1> X1 oscillator
This circuit oscillates a clock of fX = 1 to 20 MHz by connecting a resonator to X1 and X2.
Oscillation can be stopped by executing the STOP instruction or setting of the MSTOP bit (bit 7 of the clock
operation status control register (CSC)).
<2> High-speed on-chip oscillator (High-speed OCO)
The frequency at which to oscillate can be selected from among fHOCO = 64, 48, 32, 24, 16, 12, 8, 4, or 1 MHz
(TYP.) by using the option byte (000C2H). When 64 MHz or 48 MHz is selected as fHOCO, fIH is set to 32 MHz
or 24 MHz, respectively. When 32 MHz or less is selected as fHOCO, fIH is not divided and set to the same
frequency as fHOCO. After a reset release, the CPU always starts operating with this high-speed on-chip
oscillator clock
Note
. Oscillation can be stopped by executing the STOP instruction or setting of the HIOSTOP
bit (bit 0 of the CSC register).
An external main system clock (fEX = 1 to 20 MHz) can also be supplied from the EXCLK/X2/P122 pin. An external
main system clock input can be disabled by executing the STOP instruction or setting of the MSTOP bit.
As the main system clock, a high-speed system clock (X1 clock or external main system clock) or high-speed onchip oscillator clock can be selected by setting of the MCM0 bit (bit 4 of the system clock control register (CKC)).
Note
When selecting 64 MHz or 48 MHz, the selected clock (fHOCO) is supplied to timer RD.
However, 32 MHz or 24 MHz of two frequency division of fHOCO is supplied to the other functions (including the
<R>
CPU). When supplying 64 MHz or 48 MHz to timer RD, set fCLK to fIH.
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(2) Subsystem clock
• XT1 clock oscillator
This circuit oscillates a clock of fXT = 32.768 kHz by connecting a 32.768 kHz resonator to XT1 and XT2.
Oscillation can be stopped by setting the XTSTOP bit (bit 6 of the clock operation status control register (CSC)).
An external subsystem clock (fEXS = 32.768 kHz) can also be supplied from the EXCLKS/XT2/P124 pin. An
external subsystem clock input can be disabled by executing the STOP instruction.
(3) Low-speed on-chip oscillator (Low-speed OCO)
This circuit oscillates a clock of fIL = 15 kHz (TYP.).
The low-speed on-chip oscillator clock cannot be used as the CPU clock.
Only the following peripheral hardware runs on the low-speed on-chip oscillator clock.
• Watchdog timer
• Real-time clock
• 12-bit interval timer
• Timer RJ
This clock operates when bit 4 (WDTON) of the option byte (000C0H), bit 4 (WUTMMCK0) of the operation
speed mode control register (OSMC), or both are set to 1.
However, when WDTON = 1, WUTMMCK0 = 0, and bit 0 (WDSTBYON) of the option byte (000C0H) is 0,
oscillation of the low-speed on-chip oscillator stops if the HALT or STOP instruction is executed.
Caution The low-speed on-chip oscillator clock (fIL) can only be selected as the real-time clock
operation clock when the fixed-cycle interrupt function is used.
Remark
fX:
X1 clock oscillation frequency
fHOCO: High-speed on-chip oscillator clock frequency (64 MHz max.)
fIH:
High-speed on-chip oscillator clock frequency (32 MHz max.)
fEX:
External main system clock frequency
fXT:
XT1 clock oscillation frequency
Note
fEXS: External subsystem clock frequency
fIL:
Note
<R>
Low-speed on-chip oscillator clock frequency
fIH is controlled by hardware to be set to two frequency division of fHOCO when fHOCO is set to 64 MHz or 48 MHz,
and the same clock frequency as fHOCO when fHOCO is set to 32 MHz or less. When supplying 64 MHz or 48
MHz to timer RD, set fCLK to fIH.
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5.2 Configuration of Clock Generator
The clock generator includes the following hardware.
Table 5-1. Configuration of Clock Generator
Item
Configuration
Control registers
Clock operation mode control register (CMC)
System clock control register (CKC)
Clock operation status control register (CSC)
Oscillation stabilization time counter status register (OSTC)
Oscillation stabilization time select register (OSTS)
Peripheral enable registers 0, 1 (PER0, PER1)
Operation speed mode control register (OSMC)
High-speed on-chip oscillator frequency select register (HOCODIV)
High-speed on-chip oscillator trimming register (HIOTRM)
Oscillators
X1 oscillator
XT1 oscillator
High-speed on-chip oscillator clock
Low-speed on-chip oscillator clock
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Figure 5-1. Block Diagram of Clock Generator
Internal bus
Clock operation mode
control register
(CMC)
Clock operation status
control register
(CSC)
AMPH EXCLK OSCSEL
System clock control
register (CKC)
Oscillation stabilization
time select register (OSTS)
CLS
OSTS2 OSTS1 OSTS0
MSTOP
CSS MCS MCM0
Standby controller
3
HALT mode
X2/EXCLK
/P122
Normal
operation mode
MOST MOST MOST MOST MOST MOST MOST MOST
8
9
10
11 13 15 17 18
High-speed
High-speedsystem
system
clock
clockoscillator
oscillator
X1/P121
STOP mode
X1 oscillation
stabilization time counter
STOP mode
signal
Crystal/ceramic
oscillation
fX
External input
clock
fEX
Oscillation stabilization
time counter status
register (OSTC)
fMX
Clock output/
buzzer output
Option byte (000C2H)
FRQSEL0 to FRQSEL4
High-speed on-chip oscillator
fMAIN
fHOCO
(48 MHz (TYP.))
(32 MHz (TYP.))
(24 MHz (TYP.))
(16 MHz (TYP.))
(12 MHz (TYP.))
(8 MHz (TYP.))
(4 MHz (TYP.))
1/2
Selector
(64 MHz (TYP.))
fCLK
Main system clock
source selector
fIH
WUTMMCK0
Option byte (000C0H)
WDTON
Low-speed on-chip
oscillator
fIL
WDSTBYON
HAL/STOP mode signal
Watchdog timer,
channel 1 of timer array unit
(15 kHz (TYP.))
WUTMMCK0
(8 MHz (TYP.))
Timer RJ
Controller
Selector
Subsystem clock
oscillator
XT1/P123
fXT
External input
clock
fEXS
AMPHS1 AMPHS0
Clock operation mode
control register
(CMC)
EXCLKS OSCSELS
Real-time clock,
12-bit interval timer
Clock output/buzzer output, timer RJ
Controller
CLS
HOCODIV2 HOCODIV1 HOCODIV0
6
XTSTOP HIOSTOP
High-speed on-chip
oscillator frequency select
register (HOCODIV)
HIOTRM5 HIOTRM4 HIOTRM3 HIOTRM2 HIOTRM1 HIOTRM0
Clock operation status
control register
(CSC)
High-speed on-chip oscillator
trimming register(HIOTRM)
Internal bus
(Remark is listed on the next page after next.)
Timer array unit 0
Timer array unit 1
Serial array unit 0
Serial array unit 1
Serial interface IICA0
Serial interface IICA1
A/D converter
Timer RJ
DTC
Timer RD
Timer RG
Comparator
D/A converter
RTCLPC
WUTMM
CKO
RTC
EN
IICA1
EN
Operation speed mode
control register (OSMC)
ADC
EN
IICA0
EN
SAU1
EN
SAU0
EN
TAU1
EN
Peripheral enable
register 0 (PER0)
TAU0
EN
DAC
EN
TRG
EN
CMP
EN
TRD0
EN
DTC
EN
Peripheral enable
register 1 (PER1)
TRJ0
EN
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CHAPTER 5 CLOCK GENERATOR
XT2/EXCLKS
/P124
fSUB
Crystal
oscillation
CPU
CPU clock
and peripheral
hardware
clock source
selection
Controller
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Remark
Note
<R>
CHAPTER 5 CLOCK GENERATOR
fX:
X1 clock oscillation frequency
fHOCO:
High-speed on-chip oscillator clock frequency (64 MHz max.)
fIH:
High-speed on-chip oscillator clock frequency (32 MHz max.)
fEX:
External main system clock frequency
fMX:
High-speed system clock frequency
fMAIN:
Main system clock frequency
fXT:
XT1 clock oscillation frequency
fEXS:
External subsystem clock frequency
fSUB:
Subsystem clock frequency
fCLK:
CPU/peripheral hardware clock frequency
fIL:
Low-speed on-chip oscillator clock frequency
Note
fIH is controlled by hardware to be set to two frequency division of fHOCO when fHOCO is set to 64 MHz or 48 MHz,
and the same clock frequency as fHOCO when fHOCO is set to 32 MHz or less. When supplying 64 MHz or 48
MHz to timer RD, set fCLK to fIH.
5.3 Registers Controlling Clock Generator
The following nine registers are used to control the clock generator.
• Clock operation mode control register (CMC)
• System clock control register (CKC)
• Clock operation status control register (CSC)
• Oscillation stabilization time counter status register (OSTC)
• Oscillation stabilization time select register (OSTS)
• Peripheral enable registers 0, 1 (PER0, PER1)
• Operation speed mode control register (OSMC)
• High-speed on-chip oscillator frequency select register (HOCODIV)
• High-speed on-chip oscillator trimming register (HIOTRM)
(1) Clock operation mode control register (CMC)
This register is used to set the operation mode of the X1/P121, X2/EXCLK/P122, XT1/P123, and XT2/EXCLKS/P124
pins, and to select a gain of the oscillator.
The CMC register can be written only once by an 8-bit memory manipulation instruction after reset release. This
register can be read by an 8-bit memory manipulation instruction.
Reset signal generation clears this register to 00H.
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Figure 5-2. Format of Clock Operation Mode Control Register (CMC)
Address: FFFA0H
After reset: 00H
R/W
Symbol
7
6
5
4
3
2
1
0
CMC
EXCLK
OSCSEL
EXCLKS
OSCSELS
0
AMPHS1
AMPHS0
AMPH
EXCLK
OSCSEL
High-speed system clock
pin operation mode
0
0
Input port mode
Input port
0
1
X1 oscillation mode
Crystal/ceramic resonator connection
1
0
Input port mode
Input port
1
1
External clock input mode
Input port
EXCLKS
OSCSELS
Subsystem clock pin
operation mode
0
0
X2/EXCLK/P122 pin
External clock input
XT1/P123 pin
Input port mode
Input port
XT2/EXCLKS/P124 pin
0
1
XT1 oscillation mode
Crystal/ceramic resonator connection
1
0
Input port mode
Input port
1
1
External clock input mode
Input port
AMPHS1
AMPHS0
0
0
Low power consumption oscillation (default)
Oscillation margin: Medium
0
1
Normal oscillation
Oscillation margin: high
1
0
Ultra-low power consumption oscillation
Oscillation margin: Low
1
1
Setting prohibited
External clock input
XT1 oscillator oscillation mode selection
AMPH
<R>
X1/P121 pin
Note
Control of X1 clock oscillation frequency
0
1 MHz ≤ fX ≤ 10 MHz
1
10 MHz < fX ≤ 20 MHz
Note As the XT oscillator becomes oscillation mode with lower power consumption, then its oscillation
margin becomes smaller.
Cautions 1. The CMC register can be written only once after reset release, by an 8-bit memory
manipulation instruction. When the CMC register is used at the default value (00H),
be sure to set 00H to this register after reset release in order to prevent
malfunctioning during a program loop.
2. After reset release, set the CMC register before X1 or XT1 oscillation is started as set
by the clock operation status control register (CSC).
3. Be sure to set the AMPH bit to 1 if the X1 clock oscillation frequency exceeds 10 MHz.
4. The XT1 oscillator is a circuit with low amplification in order to achieve low-power
consumption. Note the following points when designing the circuit.
• Pins and circuit boards include parasitic capacitance. Therefore, perform
oscillation evaluation using a circuit board to be actually used and confirm that
there are no problems.
• When using the ultra-low power consumption oscillation (AMPHS1, AMPHS0 = 1,
0) as the mode of the XT1 oscillator, use the recommended resonators described
in 5.7 Operation-Verified Resonators and Reference Oscillator Constants.
(Cautions and Remark are given on the next page.)
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• Make the wiring between the XT1 and XT2 pins and the resonators as short as
possible, and minimize the parasitic capacitance and wiring resistance. Note
this particularly when the ultra-low power consumption oscillation (AMPHS1,
AMPHS0 = 1, 0) is selected.
• Configure the circuit of the circuit board, using material with little parasitic
capacitance and wiring resistance.
• Place a ground pattern that has the same potential as VSS as much as possible
near the XT1 oscillator.
• Be sure that the signal lines between the XT1 and XT2 pins, and the resonators
do not cross with the other signal lines. Do not route the wiring near a signal
line through which a high fluctuating current flows.
• The impedance between the XT1 and XT2 pins may drop and oscillation may be
disturbed due to moisture absorption of the circuit board in a high-humidity
environment or dew condensation on the board. When using the circuit board in
such an environment, take measures to damp-proof the circuit board, such as by
coating.
• When coating the circuit board, use material that does not cause capacitance or
leakage between the XT1 and XT2 pins.
Remark fX: X1 clock frequency
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(2) System clock control register (CKC)
This register is used to select a CPU/peripheral hardware clock and a main system clock.
The CKC register can be set by a 1-bit or 8-bit memory manipulation instruction.
Reset signal generation sets this register to 00H.
Figure 5-3. Format of System Clock Control Register (CKC)
Address: FFFA4H
After reset: 00H
R/W
Note 1
Symbol
<7>
<6>
<5>
<4>
3
2
1
0
CKC
CLS
CSS
MCS
MCM0
0
0
0
0
CLS
Status of CPU/peripheral hardware clock (fCLK)
0
Main system clock (fMAIN)
1
Subsystem clock (fSUB)
CSS
Note 2
Selection of CPU/peripheral hardware clock (fCLK)
0
Main system clock (fMAIN)
1
Subsystem clock (fSUB)
MCS
Status of Main system clock (fMAIN)
0
High-speed on-chip oscillator clock (fIH)
1
High-speed system clock (fMX)
MCM0
Note 2
Main system clock (fMAIN) operation control
0
Selects the high-speed on-chip oscillator clock (fIH) as the main system clock (fMAIN)
1
Selects the high-speed system clock (fMX) as the main system clock (fMAIN)
Notes 1. Bits 7 and 5 are read-only.
2. Changing the value of the MCM0 bit is prohibited while the CSS bit is set to 1.
Remark
fHOCO:
High-speed on-chip oscillator clock frequency (64 MHz max.)
fIH:
High-speed on-chip oscillator clock frequency (32 MHz max.)
fMX:
High-speed system clock frequency
fMAIN:
Main system clock frequency
fSUB:
Subsystem clock frequency
Note
Note
fIH is controlled by hardware to be set to two frequency division of fHOCO when fHOCO is set to
64 MHz or 48 MHz, and the same clock frequency as fHOCO when fHOCO is set to 32 MHz or
<R>
less. When supplying 64 MHz or 48 MHz to timer RD, set fCLK to fIH.
(Cautions are listed on the next page.)
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Cautions 1. Be sure to set bits 0 to 3 of the CKC register to 0.
2. The clock set by the CSS bit is supplied to the CPU and peripheral hardware. If the
CPU clock is changed, therefore, the clock supplied to peripheral hardware (except
the real-time clock, 12-bit interval timer, clock output/buzzer output, and watchdog
timer) is also changed at the same time.
Consequently, stop each peripheral
function when changing the CPU/peripheral hardware clock.
3. If the subsystem clock is used as the peripheral hardware clock, the operations of
the A/D converter and IICA are not guaranteed. For the operating characteristics of
the peripheral hardware, refer to the chapters describing the various peripheral
hardware as well as CHAPTER 34 ELECTRICAL SPECIFICATIONS.
4. When selecting fHOCO as the count source for timer RD, set fCLK to fIH before setting
bit 4 (TRD0EN) in peripheral enable register 1 (PER1). When changing fCLK to a clock
other than fIH, clear bit 4 (TRD0EN) in peripheral enable register 1 (PER1) before
changing.
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(3) Clock operation status control register (CSC)
This register is used to control the operations of the high-speed system clock, high-speed on-chip oscillator clock, and
subsystem clock (except the low-speed on-chip oscillator clock).
The CSC register can be set by a 1-bit or 8-bit memory manipulation instruction.
Reset signal generation sets this register to C0H.
Figure 5-4. Format of Clock Operation Status Control Register (CSC)
Address: FFFA1H
After reset: C0H
R/W
Symbol
<7>
<6>
5
4
3
2
1
<0>
CSC
MSTOP
XTSTOP
0
0
0
0
0
HIOSTOP
MSTOP
High-speed system clock operation control
X1 oscillation mode
External clock input mode
0
X1 oscillator operating
External clock from EXCLK
pin is valid
1
X1 oscillator stopped
External clock from EXCLK
pin is invalid
XTSTOP
Input port mode
Input port
Subsystem clock operation control
XT1 oscillation mode
External clock input mode
0
XT1 oscillator operating
External clock from EXCLKS
pin is valid
1
XT1 oscillator stopped
External clock from EXCLKS
pin is invalid
HIOSTOP
Input port mode
Input port
High-speed on-chip oscillator clock operation control
0
High-speed on-chip oscillator operating
1
High-speed on-chip oscillator stopped
Cautions 1. After reset release, set the clock operation mode control register (CMC) before
setting the CSC register.
2. Set the oscillation stabilization time select register (OSTS) before setting the MSTOP
bit to 0 after releasing reset. Note that if the OSTS register is being used with its
default settings, the OSTS register is not required to be set here.
3. To start X1 oscillation as set by the MSTOP bit, check the oscillation stabilization
time of the X1 clock by using the oscillation stabilization time counter status register
(OSTC).
4. When starting XT1 oscillation by setting the XSTOP bit, wait for oscillation of the
subsystem clock to stabilize by setting a wait time using software.
5. Do not stop the clock selected for the CPU peripheral hardware clock (fCLK) with the
OSC register.
6. The setting of the flags of the register to stop clock oscillation (invalidate the external
clock input) and the condition before clock oscillation is to be stopped are as Table
5-2.
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Table 5-2. Condition Before Stopping Clock Oscillation and Flag Setting
Clock
X1 clock
External main system
clock
XT1 clock
External subsystem
clock
High-speed on-chip
oscillator clock
Condition Before Stopping Clock
(Invalidating External Clock Input)
CPU and peripheral hardware clocks operate with a clock
other than the high-speed system clock.
Setting of CSC
Register Flags
MSTOP = 1
(CLS = 0 and MCS = 0, or CLS = 1)
CPU and peripheral hardware clocks operate with a clock
other than the subsystem clock.
XTSTOP = 1
(CLS = 0)
CPU and peripheral hardware clocks operate with a clock
other than the high-speed on-chip oscillator clock.
HIOSTOP = 1
(CLS = 0 and MCS = 1, or CLS = 1)
(4) Oscillation stabilization time counter status register (OSTC)
This is the register that indicates the count status of the X1 clock oscillation stabilization time counter.
The X1 clock oscillation stabilization time can be checked in the following case,
• If the X1 clock starts oscillation while the high-speed on-chip oscillator clock or subsystem clock is being used as
the CPU clock.
• If the STOP mode is entered and then released while the high-speed on-chip oscillator clock is being used as the
CPU clock with the X1 clock oscillating.
The OSTC register can be read by a 1-bit or 8-bit memory manipulation instruction.
The generation of reset signal, the STOP instruction and MSTOP (bit 7 of clock operation status control register
(CSC)) = 1 clear the OSTC register to 00H.
Remark The oscillation stabilization time counter starts counting in the following cases.
• When oscillation of the X1 clock starts (EXCLK, OSCSEL = 0, 1 → MSTOP = 0)
• When the STOP mode is released
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Figure 5-5. Format of Oscillation Stabilization Time Counter Status Register (OSTC)
Address: FFFA2H
Symbol
OSTC
After reset: 00H
7
6
5
R
4
3
2
1
0
MOST MOST MOST MOST MOST MOST MOST MOST
8
9
10
11
13
15
17
18
MOST MOST MOST MOST MOST MOST MOST MOST
8
9
10
11
13
15
17
18
Oscillation stabilization time status
fX = 10 MHz
25.6 μs max. 12.8 μs max.
8
25.6 μs min.
12.8 μs min.
9
51.2 μs min.
25.6 μs min.
10
102.4 μs min. 51.2 μs min.
11
204.8 μs min. 102.4 μs min.
13
819.2 μs min. 409.6 μs min.
15
3.27 ms min. 1.64 ms min.
17
13.11 ms min. 6.55 ms min.
18
26.21 ms min. 13.11 ms min.
0
0
0
0
0
0
0
0
2 /fX max.
1
0
0
0
0
0
0
0
2 /fX min.
1
1
0
0
0
0
0
0
2 /fX min.
1
1
1
0
0
0
0
0
2 /fX min.
1
1
1
1
0
0
0
0
2 /fX min.
1
1
1
1
1
1
1
1
1
1
0
0
1
0
0
0
fX = 20 MHz
8
2 /fX min.
2 /fX min.
1
1
1
1
1
1
1
0
2 /fX min.
1
1
1
1
1
1
1
1
2 /fX min.
Cautions 1. After the above time has elapsed, the bits are set to 1 in order from the MOST8
bit and remain 1.
2. The oscillation stabilization time counter counts up to the oscillation
stabilization time set by the oscillation stabilization time select register
(OSTS).
In the following cases, set the oscillation stabilization time of the OSTS
register to the value greater than the count value which is to be checked by
the OSTC register.
• If the X1 clock starts oscillation while the high-speed on-chip oscillator
clock or subsystem clock is being used as the CPU clock.
• If the STOP mode is entered and then released while the high-speed on-chip
oscillator clock is being used as the CPU clock with the X1 clock oscillating.
(Note, therefore, that only the status up to the oscillation stabilization time
set by the OSTS register is set to the OSTC register after the STOP mode is
released.)
3. The X1 clock oscillation stabilization wait time does not include the time until
clock oscillation starts (“a” below).
STOP mode release
X1 pin voltage
waveform
a
Remark
fX: X1 clock oscillation frequency
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(5) Oscillation stabilization time select register (OSTS)
This register is used to select the X1 clock oscillation stabilization wait time when the STOP mode is released.
When the X1 clock is selected as the CPU clock, the operation automatically waits for the time set using the OSTS
register after the STOP mode is released.
When the high-speed on-chip oscillator clock is selected as the CPU clock, confirm with the oscillation stabilization
time counter status register (OSTC) that the desired oscillation stabilization time has elapsed after the STOP mode is
released. The oscillation stabilization time can be checked up to the time set using the OSTC register.
The OSTS register can be set by an 8-bit memory manipulation instruction.
Reset signal generation sets the OSTS register to 07H.
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Figure 5-6. Format of Oscillation Stabilization Time Select Register (OSTS)
Address: FFFA3H
After reset: 07H
R/W
Symbol
7
6
5
4
3
2
1
0
OSTS
0
0
0
0
0
OSTS2
OSTS1
OSTS0
OSTS2
OSTS1
OSTS0
Oscillation stabilization time selection
fX = 10 MHz
<R>
0
0
0
2 /fX
0
0
1
2 /fX
0
1
0
2 /fX
0
1
1
2 /fX
51.2 μs
25.6 μs
10
102.4 μs
51.2 μs
11
204.8 μs
102.4 μs
13
819.2 μs
409.6 μs
15
3.27 ms
1.64 ms
17
13.11 ms
6.55 ms
18
26.21 ms
13.11 ms
0
0
2 /fX
1
0
1
2 /fX
1
1
0
2 /fX
1
1
fX = 20 MHz
12.8 μs
9
1
1
25.6 μs
8
2 /fX
Cautions 1. To set the STOP mode when the X1 clock is used as the CPU clock, set the OSTS
register before executing the STOP instruction.
2. Change the setting of the OSTS register before setting the MSTOP bit of the clock
operation status control register (CSC) to 0.
3. Do not change the value of the OSTS register during the X1 clock oscillation
stabilization time.
4. The oscillation stabilization time counter counts up to the oscillation stabilization
time set by the OSTS register.
In the following cases, set the oscillation stabilization time of the OSTS register to
the value greater than the count value which is to be checked by the OSTC register
after the oscillation starts.
• If the X1 clock starts oscillation while the high-speed on-chip oscillator clock or
subsystem clock is being used as the CPU clock.
• If the STOP mode is entered and then released while the high-speed on-chip
oscillator clock is being used as the CPU clock with the X1 clock oscillating. (Note,
therefore, that only the status up to the oscillation stabilization time set by the
OSTS register is set to the OSTC register after the STOP mode is released.)
5. The X1 clock oscillation stabilization wait time does not include the time until clock
oscillation starts (“a” below).
STOP mode release
X1 pin voltage
waveform
a
Remark fX: X1 clock oscillation frequency
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(6) Peripheral enable registers 0, 1 (PER0, PER1)
These registers are used to enable or disable supplying the clock to the peripheral hardware. Clock supply to the
hardware that is not used is also stopped so as to decrease the power consumption and noise.
To use the peripheral functions below, which are controlled by these registers, set (1) the bit corresponding to each
function before specifying the initial settings of the peripheral functions.
• Real-time clock and 12-bit interval timer
• Serial interface IICA1
• A/D converter
• Serial interface IICA0
• Serial array unit 1
• Serial array unit 0
• Timer array unit 1
• Timer array unit 0
• D/A converter
• Timer RG
• Comparator
• Timer RD
• DTC
• Timer RJ
The PER0 and PER1 registers can be set by a 1-bit or 8-bit memory manipulation instruction.
Reset signal generation clears these registers to 00H.
Figure 5-7. Format of Peripheral Enable Register 0 (PER0) (1/3)
Address: F00F0H
Symbol
After reset: 00H
<7>
PER0
<6>
RTCEN
RTCEN
IICA1EN
R/W
<5>
Note 1
ADCEN
<4>
<3>
IICA0EN
Control of supplying input clock
Note 2
SAU1EN
<2>
SAU0EN
<1>
TAU1EN
<0>
Note 1
TAU0EN
for real-time clock (RTC) and 12-bit interval timer
Stops input clock supply.
• SFR used by the real-time clock (RTC) and 12-bit interval timer cannot be written.
0
• The real-time clock (RTC) and 12-bit interval timer are in the reset status.
Enables input clock supply.
• SFR used by the real-time clock (RTC) and 12-bit interval timer can be read and written.
1
Notes 1. 80 and 100-pin products only.
2. The input clock that can be controlled by the RTCEN bit is used when the register that is used
by the real-time clock (RTC) and 12-bit interval timer is accessed from the CPU. The RTCEN
bit cannot control supply of the operating clock (fSUB) to RTC and 12-bit interval timer.
Caution
Be sure to clear the following bits to 0.
30, 32, 36, 40, 44, 48, 52, 64-pin products: bits 1, 6
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Figure 5-7. Format of Peripheral Enable Register 0 (PER0) (2/3)
Address: F00F0H
Symbol
After reset: 00H
<7>
PER0
<6>
RTCEN
IICA1EN
IICA1EN
R/W
<5>
Note
<4>
ADCEN
Note
IICA0EN
<3>
SAU1EN
<2>
SAU0EN
<1>
TAU1EN
<0>
Note
TAU0EN
Control of serial interface IICA1 input clock supply
Stops input clock supply.
• SFR used by the serial interface IICA1 cannot be written.
0
• The serial interface IICA1 is in the reset status.
Enables input clock supply.
• SFR used by the serial interface IICA1 can be read and written.
1
ADCEN
Control of A/D converter input clock supply
Stops input clock supply.
• SFR used by the A/D converter cannot be written.
0
• The A/D converter is in the reset status.
Enables input clock supply.
• SFR used by the A/D converter can be read and written.
1
IICA0EN
Control of serial interface IICA0 input clock supply
Stops input clock supply.
• SFR used by the serial interface IICA0 cannot be written.
0
• The serial interface IICA0 is in the reset status.
Enables input clock supply.
• SFR used by the serial interface IICA0 can be read and written.
1
SAU1EN
Control of serial array unit 1 input clock supply
Stops input clock supply.
• SFR used by the serial array unit 1 cannot be written.
0
• The serial array unit 1 is in the reset status.
Enables input clock supply.
• SFR used by the serial array unit 1 can be read and written.
1
SAU0EN
Control of serial array unit 0 input clock supply
Stops input clock supply.
• SFR used by the serial array unit 0 cannot be written.
0
• The serial array unit 0 is in the reset status.
Enables input clock supply.
• SFR used by the serial array unit 0 can be read and written.
1
Note
80 and 100-pin products only.
Caution
Be sure to clear the following bits to 0.
30, 32, 36, 40, 44, 48, 52, 64-pin products: bits 1, 6
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Figure 5-7. Format of Peripheral Enable Register 0 (PER0) (3/3)
Address: F00F0H
Symbol
After reset: 00H
<7>
PER0
<6>
RTCEN
TAU1EN
IICA1EN
R/W
<5>
Note
ADCEN
Note
<4>
IICA0EN
<3>
SAU1EN
<2>
SAU0EN
<1>
TAU1EN
<0>
Note
TAU0EN
Control of timer array unit 1 input clock supply
Stops input clock supply.
• SFR used by timer array unit 1 cannot be written.
0
• Timer array unit 1 is in the reset status.
Enables input clock supply.
• SFR used by timer array unit 1 can be read and written.
1
TAU0EN
Control of timer array unit 0 input clock supply
Stops input clock supply.
• SFR used by timer array unit 0 cannot be written.
0
• Timer array unit 0 is in the reset status.
Enables input clock supply.
• SFR used by timer array unit 0 can be read and written.
1
Note
80 and 100-pin products only.
Caution
Be sure to clear the following bits to 0.
30, 32, 36, 40, 44, 48, 52, 64-pin products: bits 1, 6
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Figure 5-8. Format of Peripheral Enable Register 1 (PER1) (1/2)
Address: F007AH
After reset: 00H
R/W
Symbol
<7>
<6>
<5>
<4>
<3>
2
1
<0>
PER1
DACEN
TRGEN
CMPEN
TRD0EN
DTCEN
0
0
TRJ0EN
Note 1
Note 1
DACEN
Control of D/A converter input clock supply
Note 1
Stops input clock supply.
• SFR used by the D/A converter cannot be written.
0
• The D/A converter is in the reset status.
Enables input clock supply.
• SFR used by the D/A converter can be read and written.
1
TRGEN
Control of timer RG input clock supply
Stops input clock supply.
• SFR used by timer RG cannot be written.
0
• Timer RG is in the reset status.
Enables input clock supply.
• SFR used by timer RG can be read and written.
1
CMPEN
Control of comparator input clock supply
Note 1
Stops input clock supply.
• SFR used by comparator cannot be written.
0
• Comparator is in the reset status.
Enables input clock supply.
• SFR used by comparator can be read and written.
1
TRD0EN
Control of timer RD input clock supply
Note 2
Stops input clock supply.
• SFR used by timer RD cannot be written.
0
• Timer RD is in the reset status.
Enables input clock supply.
• SFR used by timer RD can be read and written.
1
<R>
Notes 1. Only for products with 96 KB or more code flash memory.
<R>
2. When FRQSEL4 = 1 in the user option byte (000C2H/010C2H), set fCLK to fIH before setting bit
4 (TRD0EN) in peripheral enable register 1 (PER1). When changing fCLK to a clock other than
fIH, clear bit 4 (TRD0EN) in peripheral enable register 1 (PER1) before changing.
Caution
Be sure to clear the following bits to 0.
Products with 64 KB or less code flash memory: bits 1, 2, 5, and 7
Products with 96 KB or more code flash memory: bits 1 and 2
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Figure 5-8. Format of Peripheral Enable Register 1 (PER1) (2/2)
Address: F007AH
Symbol
PER1
After reset: 00H
<7>
<6>
DACEN
Note
TRGEN
R/W
<5>
CMPEN
Note
DTCEN
<3>
2
1
<0>
TRD0EN
DTCEN
0
0
TRJ0EN
Control of DTC input clock supply
0
Stops input clock supply.
• DTC cannot run.
1
Enables input clock supply.
• DTC can run.
TRJ0EN
<4>
Control of timer RJ0 input clock supply
Stops input clock supply.
• SFR used by timer RJ0 cannot be written.
0
• Timer RJ0 is in the reset status.
Enables input clock supply.
• SFR used by timer RJ0 can be read and written.
1
<R>
Note
Only for products with 96 KB or more code flash memory.
Caution
Be sure to clear the following bits to 0.
Products with 64 KB or less code flash memory: bits 1, 2, 5, and 7
Products with 96 KB or more code flash memory: bits 1 and 2
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(7) Operation speed mode control register (OSMC)
This register is used to reduce power consumption by stopping unnecessary clock functions.
If the RTCLPC bit is set to 1, power consumption can be reduced, because clock supply to the peripheral functions,
except the real-time clock and 12-bit interval timer, is stopped in STOP mode or HALT mode while subsystem clock is
selected as CPU clock. Set bit 7 (RTCEN) of peripheral enable registers 0 (PER0) to 1 before this setting.
In addition, the OSMC register can be used to select the operation clock of the real-time clock and 12-bit interval timer.
The OSMC register can be set by an 8-bit memory manipulation instruction.
Reset signal generation clears this register to 00H.
Figure 5-9. Format of Operation Speed Mode Control Register (OSMC)
Address: F00F3H
After reset: 00H
R/W
Symbol
7
6
5
4
3
2
1
0
OSMC
RTCLPC
0
0
WUTMMCK0
0
0
0
0
RTCLPC
0
Setting in STOP mode or HALT mode while subsystem clock is selected as CPU clock
Enables supply of subsystem clock to peripheral functions
(See Table 23-1 for peripheral functions whose operations are enabled.)
Stops supply of subsystem clock to peripheral functions other than real-time clock and 12-bit
1
interval timer.
<R>
WUTMMCK0
Selection of operation clock for real-time clock, 12-bit interval timer, and timer RJ
0
• The subsystem clock is selected as the operation clock for the real-time clock and the 12bit interval timer.
• The low-speed on-chip oscillator cannot be selected as the count source for timer RJ.
1
• The low-speed on-chip oscillator clock is selected as the operation clock for the real-time
clock and the 12-bit interval timer.
• Either the low-speed on-chip oscillator or the subsystem clock can be selected as the
count source for timer RJ.
Caution
The STOP mode current or HALT mode current when the subsystem clock is
used can be reduced by setting the RTCLPC bit to 1. However, no clock can be
supplied to the peripheral functions other than the real-time clock and 12-bit
interval timer during HALT mode while subsystem clock is selected as CPU
clock. Set bit 7 (RTCEN) of peripheral enable registers 0 (PER0), to 1, and bits 0
to 6 of the PER0 register to 0 before setting subsystem clock HALT mode.
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<R> (8) High-speed on-chip oscillator frequency select register (HOCODIV)
The frequency of the high-speed on-chip oscillator which is set by an option byte (000C2H/0102CH) can be changed
by using high-speed on-chip oscillator frequency select register (HOCODIV). However, the selectable frequency
depends on the FRQSEL4 and FRQSEL3 bits of the option byte (000C2H/0102CH).
The HOCODIV register can be set by an 8-bit memory manipulation instruction.
Reset signal generation clears this register to default value (undefined).
Figure 5-10. Format of High-speed on-chip oscillator frequency select register (HOCODIV)
Address: F00A8H
After reset: undefined
R/W
Symbol
7
6
5
4
3
HOCODIV
0
0
0
0
0
HOCODIV2
HOCODIV1 HOCODIV0
2
1
HOCODIV2 HOCODIV1 HOCODIV0
Selection of high-speed on-chip oscillator clock frequency
FRQSEL4 = 0
FRQSEL3 = 0
0
0
0
0
0
0
0
fIH = 12 MHz
0
1
1
fIH = 24 MHz
1
1
fIH = 6 MHz
1
0
fIH = 3 MHz
Setting
0
FRQSEL4 = 1
FRQSEL3 = 1
FRQSEL3 = 0
FRQSEL3 = 1
fIH = 32 MHz
fIH = 24 MHz
fIH = 32 MHz
fHOCO = 48 MHz
fHOCO = 64 MHz
fIH = 16 MHz
fIH = 12 MHz
fIH = 16 MHz
fHOCO = 24 MHz
fHOCO = 32 MHz
fIH = 8 MHz
fIH = 6 MHz
fIH = 8 MHz
fHOCO = 12 MHz
fHOCO = 16 MHz
fIH = 4 MHz
fIH = 3 MHz
fIH = 4 MHz
fHOCO = 6 MHz
fHOCO = 8 MHz
fIH = 2 MHz
prohibited
1
0
0
Setting
1
fIH = 1 MHz
prohibited
Other than above
Setting
fIH = 2 MHz
prohibited
fHOCO = 4 MHz
Setting
fIH = 1 MHz
prohibited
fHOCO = 2 MHz
Setting prohibited
Cautions 1. Set the HOCODIV register within the operable voltage range both before and after
changing the frequency.
2. Use the device within the voltage of the flash operation mode set by the option
byte (000C2H/010C2H) even after the frequency has been changed by using the
HOCODIV register.
Option Byte
(000C2H/010C2H) Value
CMODE1
Flash Operation Mode
Operating
Operating Voltage
Frequency Range
Range
CMODE2
0
0
LV (low-voltage main) mode
1 to 4 MHz
1.6 to 5.5 V
1
0
LS (low-speed main) mode
1 to 8 MHz
1.8 to 5.5 V
1 to 16 MHz
2.4 to 5.5 V
1 to 32 MHz
2.7 to 5.5 V
1
1
HS (high-speed main) mode
3. When setting of high-speed on-chip oscillator clock as system clock, the device
operates at the old frequency for the duration of 3 clocks after the frequency value
has been changed by using the HOCODIV register.
4. To change the frequency of the high-speed on-chip oscillator when X1 oscillation,
external oscillation input or subclock is set for the system clock, stop the highspeed on-chip oscillator by setting bit 0 (HIOSTOP) of the CSC register to 1 and
then change the frequency.
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(9) High-speed on-chip oscillator trimming register (HIOTRM)
This register is used to adjust the accuracy of the high-speed on-chip oscillator.
<R>
With self-measurement of the high-speed on-chip oscillator frequency via a timer using high-accuracy external clock
input, and so on, the accuracy can be adjusted.
The HIOTRM register can be set by an 8-bit memory manipulation instruction.
<R>
Caution The frequency will vary if the temperature and VDD pin voltage change after accuracy
adjustment. When the temperature and VDD voltage change, accuracy adjustment must be
executed regularly or before the frequency accuracy is required.
Figure 5-11. Format of High-Speed On-Chip Oscillator Trimming Register (HIOTRM)
Address: F00A0H
After reset: Note
R/W
Symbol
7
6
5
4
3
2
1
0
HIOTRM
0
0
HIOTRM5
HIOTRM4
HIOTRM3
HIOTRM2
HIOTRM1
HIOTRM0
HIOTRM5
HIOTRM4
HIOTRM3
HIOTRM2
HIOTRM1
HIOTRM0
High-speed on-chip
Minimum speed
oscillator
0
0
0
0
0
0
0
0
0
0
0
1
0
0
0
0
1
0
0
0
0
0
1
1
0
0
0
1
0
0
•
•
•
<R>
1
1
1
1
1
1
0
1
1
1
1
1
1
1
Maximum speed
Note The reset value differs for each chip.
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5.4 System Clock Oscillator
5.4.1 X1 oscillator
The X1 oscillator oscillates with a crystal resonator or ceramic resonator (1 to 20 MHz) connected to the X1 and X2
pins.
An external clock can also be input. In this case, input the clock signal to the EXCLK pin.
To use the X1 oscillator, set bits 7 and 6 (EXCLK, OSCSEL) of the clock operation mode control register (CMC) as
follows.
• Crystal or ceramic oscillation: EXCLK, OSCSEL = 0, 1
• External clock input:
EXCLK, OSCSEL = 1, 1
When the X1 oscillator is not used, set the input port mode (EXCLK, OSCSEL = 0, 0).
When the pins are not used as input port pins, either, see Table 2-2 Connection of Unused Pins.
Figure 5-12 shows an example of the external circuit of the X1 oscillator.
Figure 5-12. Example of External Circuit of X1 Oscillator
(a) Crystal or ceramic oscillation
(b) External clock
VSS
X1
X2
External clock
EXCLK
Crystal resonator
or
ceramic resonator
Cautions are listed on the next page.
5.4.2 XT1 oscillator
The XT1 oscillator oscillates with a crystal resonator (standard: 32.768 kHz) connected to the XT1 and XT2 pins.
To use the XT1 oscillator, set bit 4 (OSCSELS) of the clock operation mode control register (CMC) to 1.
An external clock can also be input. In this case, input the clock signal to the EXCLKS pin.
To use the XT1 oscillator, set bits 5 and 4 (EXCLKS, OSCSELS) of the clock operation mode control register (CMC) as
follows.
• Crystal oscillation:
• External clock input:
EXCLKS, OSCSELS = 0, 1
EXCLKS, OSCSELS = 1, 1
When the XT1 oscillator is not used, set the input port mode (EXCLKS, OSCSELS = 0, 0).
When the pins are not used as input port pins, either, see Table 2-2 Connection of Unused Pins.
Figure 5-13 shows an example of the external circuit of the XT1 oscillator.
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Figure 5-13. Example of External Circuit of XT1 Oscillator
(a) Crystal oscillation
(b) External clock
VSS
XT1
32.768
kHz
XT2
External clock
EXCLKS
Caution 1. When using the X1 oscillator and XT1 oscillator, wire as follows in the area enclosed by the
broken lines in the Figures 5-12 and 5-13 to avoid an adverse effect from wiring capacitance.
• Keep the wiring length as short as possible.
• Do not cross the wiring with the other signal lines. Do not route the wiring near a signal line
through which a high fluctuating current flows.
• Always make the ground point of the oscillator capacitor the same potential as VSS. Do not
ground the capacitor to a ground pattern through which a high current flows.
• Do not fetch signals from the oscillator.
The XT1 oscillator is a circuit with low amplification in order to achieve low-power consumption.
Note the following points when designing the circuit.
• Pins and circuit boards include parasitic capacitance. Therefore, perform oscillation evaluation
using a circuit board to be actually used and confirm that there are no problems.
• When using the ultra-low power consumption oscillation (AMPHS1, AMPHS0 = 1, 0) as the mode
of the XT1 oscillator, use the recommended resonators described in 5.7 Operation-Verified
Resonators and Reference Oscillator Constants.
• Make the wiring between the XT1 and XT2 pins and the resonators as short as possible, and
minimize the parasitic capacitance and wiring resistance. Note this particularly when the ultralow power consumption oscillation (AMPHS1, AMPHS0 = 1, 0) is selected.
• Configure the circuit of the circuit board, using material with little wiring resistance.
• Place a ground pattern that has the same potential as VSS as much as possible near the XT1
oscillator.
• Be sure that the signal lines between the XT1 and XT2 pins, and the resonators do not cross
with the other signal lines. Do not route the wiring near a signal line through which a high
fluctuating current flows.
• The impedance between the XT1 and XT2 pins may drop and oscillation may be disturbed due
to moisture absorption of the circuit board in a high-humidity environment or dew
condensation on the board.
When using the circuit board in such an environment, take
measures to damp-proof the circuit board, such as by coating.
• When coating the circuit board, use material that does not cause capacitance or leakage
between the XT1 and XT2 pins.
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Figure 5-14 shows examples of incorrect resonator connection.
Figure 5-14. Examples of Incorrect Resonator Connection (1/2)
(a) Too long wiring
(b) Crossed signal line
PORT
VSS
X1
X2
VSS
X1
X2
NG
NG
NG
(c) The X1 and X2 signal line wires cross.
(d) A power supply/GND pattern exists
under the X1 and X2 wires.
VSS
VSS
X1
X1
X2
X2
Note
Power supply/GND pattern
Note
Do not place a power supply/GND pattern under the wiring section (section indicated by a broken line in the
figure) of the X1 and X2 pins and the resonators in a multi-layer board or double-sided board.
Do not configure a layout that will cause capacitance elements and affect the oscillation characteristics.
Remark
When using the subsystem clock, replace X1 and X2 with XT1 and XT2, respectively. Also, insert resistors
in series on the XT2 side.
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Figure 5-14. Examples of Incorrect Resonator Connection (2/2)
(e) Wiring near high alternating current
(f) Current flowing through ground line of oscillator
(potential at points A, B, and C fluctuates)
VDD
Pmn
X1
X2
High current
VSS
VSS
A
X1
B
X2
C
High current
(g) Signals are fetched
VSS
Caution
X1
X2
When X2 and XT1 are wired in parallel, the crosstalk noise of X2 may increase with XT1, resulting in
malfunctioning.
Remark
When using the subsystem clock, replace X1 and X2 with XT1 and XT2, respectively. Also, insert resistors
in series on the XT2 side.
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5.4.3 High-speed on-chip oscillator
The high-speed on-chip oscillator is incorporated in the RL78/G14. The frequency can be selected from among 64, 48,
32, 24, 16, 12, 8, 4, or 1 MHz by using the option byte (000C2H). When 64 MHz or 48 MHz is selected, the two frequency
division of the selected clock is supplied to CPU clock. Oscillation can be controlled by bit 0 (HIOSTOP) of the clock
operation status control register (CSC).
The high-speed on-chip oscillator automatically starts oscillating after reset release.
5.4.4 Low-speed on-chip oscillator
The low-speed on-chip oscillator is incorporated in the RL78/G14.
The low-speed on-chip oscillator clock is used only as the watchdog timer, real-time clock, 12-bit interval timer, and
timer RJ clock. The internal low-speed oscillation clock cannot be used as the CPU clock.
This clock operates when bit 4 (WDTON) of the option byte (000C0H), bit 4 (WUTMMCK0) of the operation speed
mode control register (OSMC), or both are set to 1.
Unless the watchdog timer is stopped and WUTMMCK0 is a value other than zero, oscillation of the low-speed on-chip
oscillator continues. While the watchdog timer operates, the low-speed on-chip oscillator clock does not stop even if the
program freezes.
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5.5 Clock Generator Operation
The clock generator generates the following clocks and controls the operation modes of the CPU, such as standby
mode (see Figure 5-1).
• Main system clock fMAIN
• High-speed system clock fMX
X1 clock fX
External main system clock fEX
• High-speed on-chip oscillator clock fIH
• Subsystem clock fSUB
• XT1 clock fXT
• External subsystem clock fEXS
• Low-speed on-chip oscillator clock fIL
• CPU/peripheral hardware clock fCLK
The CPU starts operation when the high-speed on-chip oscillator starts outputting after a reset release in the RL78/G14.
When the power supply voltage is turned on, the clock generator operation is shown in Figure 5-15.
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Figure 5-15. Clock Generator Operation When Power Supply Voltage Is Turned On
Power supply
voltage (VDD)
1.6 V
1.51 V
(TYP.)
0V
<1>
Internal reset signal
Switched by software
Note 3
Reset processing
<3>
<5>
High-speed on-chip
oscillator clock
CPU clock
<5>
High-speed
system clock
Subsystem
clock
<2>
High-speed on-chip
oscillator clock (fIH)
High-speed
system clock (fMX)
(when X1 oscillation
selected)
Note 1
Subsystem clock (fSUB)
(when XT1 oscillation
selected)
<4>
X1 clock
oscillation stabilization timeNote 2
Starting X1 oscillation
is specified by software.
<4>
Starting XT1 oscillation
is specified by software.
<1> When the power is turned on, an internal reset signal is generated by the power-on-reset (POR) circuit.
<2> When the power supply voltage exceeds 1.51 V (TYP.), the reset is released and the high-speed on-chip
oscillator automatically starts oscillation.
<3> The CPU starts operation on the high-speed on-chip oscillator clock after a reset processing such as waiting for
the voltage of the power supply or regulator to stabilize has been performed after reset release.
<4> Set the start of oscillation of the X1 or XT1 clock via software (see 5.6.2 Example of setting X1 oscillation
clock and 5.6.3 Example of setting XT1 oscillation clock).
<5> When switching the CPU clock to the X1 or XT1 clock, wait for the clock oscillation to stabilize, and then set
switching via software (see 5.6.2 Example of setting X1 oscillation clock and 5.6.3 Example of setting XT1
oscillation clock).
Notes 1.
The internal reset processing time includes the oscillation accuracy stabilization time of the high-speed onchip oscillator clock.
<R>
2.
When releasing a reset, confirm the oscillation stabilization time for the X1 clock using the oscillation
3.
stabilization time counter status register (OSTC).
Reset processing time: 387 to 720 μ s (When LVD is used)
155 to 407 μ s (When LVD off)
Caution It is not necessary to wait for the oscillation stabilization time when an external clock input from the
EXCLK pin is used.
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5.6 Controlling Clock
5.6.1 Example of setting high-speed on-chip oscillator
After a reset release, the CPU/peripheral hardware clock (fCLK) always starts operating with the high-speed on-chip
oscillator clock. The frequency of the high-speed on-chip oscillator can be selected from 64, 48, 32, 24, 16, 12, 8, 4, and 1
MHz by using FRQSEL0 to FRQSEL4 of the option byte (000C2H). In addition, Oscillation can be changed by the internal
high-speed on-chip oscillator frequency select register (HOCODIV).
[Option byte setting]
Address: 000C2H
Option
byte
7
6
5
4
3
2
1
0
CMODE1
CMODE0
(000C2H)
FRQSEL4
FRQSEL3
FRQSEL2
FRQSEL1
FRQSEL0
0/1
0/1
0/1
0/1
0/1
0/1
0/1
CMODE1
CMODE0
0
0
LV (low voltage main) mode
1
0
LS (low speed main) mode
VDD = 1.8 V to 5.5 V @ 1 MHz to 8 MHz
1
1
HS (high speed main) mode
VDD = 2.4 V to 5.5 V @ 1 MHz to 16 MHz
VDD = 2.7 V to 5.5 V @ 1 MHz to 32 MHz
FRQSEL4
FRQSEL3
FRQSEL2
FRQSEL1
FRQSEL0
1
1
0
0
0
64 MHz
32 MHz
1
0
0
0
0
48 MHz
24 MHz
0
1
0
0
0
32 MHz
32 MHz
0
0
0
0
0
24 MHz
24 MHz
0
1
0
0
1
16 MHz
16 MHz
0
0
0
0
1
12 MHz
12 MHz
0
1
0
1
0
8 MHz
8 MHz
0
1
0
1
1
4 MHz
4 MHz
0
1
1
0
1
1 MHz
1 MHz
1
Setting of flash operation mode
VDD = 1.6 V to 5.5 V @ 1 MHz to 4 MHz
Frequency of the high-speed on-chip
oscillator
fIH
fHOCO
Other than above
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[High-speed on-chip oscillator frequency select register (HOCODIV) setting]
Address: F00A8H
HOCODIV
7
6
5
4
3
2
1
0
0
0
0
0
0
HOCODIV2
HOCODIV1
HOCODIV0
HOCODIV2
HOCODIV1 HOCODIV0
Selection of high-speed on-chip oscillator lock frequency
FRQSEL4 = 0
FRQSEL3 = 0
0
0
0
0
0
1
0
1
0
1
0
1
fIH = 24 MHz
fIH = 12 MHz
fIH = 6 MHz
fIH = 3 MHz
FRQSEL4 = 1
FRQSEL3 = 1
FRQSEL3 = 0
FRQSEL3 = 1
fIH = 32 MHz
fIH = 24 MHz
fIH = 32 MHz
fHOCO = 48 MHz
fHOCO = 64 MHz
fIH = 16 MHz
fIH = 12 MHz
fIH = 16 MHz
fHOCO = 24 MHz
fHOCO = 32 MHz
fIH = 8 MHz
fIH = 6 MHz
fIH = 8 MHz
fHOCO = 12 MHz
fHOCO = 16 MHz
fIH = 3 MHz
fIH = 4 MHz
fIH = 4 MHz
fHOCO = 6 MHz
1
0
0
Setting
fIH = 2 MHz
prohibited
1
0
1
Setting
prohibited
Other than above
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fHOCO = 8 MHz
Setting
fIH = 2 MHz
prohibited
fHOCO = 4 MHz
Setting
fIH = 1 MHz
prohibited
fHOCO = 2 MHz
Setting prohibited
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5.6.2 Example of setting X1 oscillation clock
After a reset release, the CPU/peripheral hardware clock (fCLK) always starts operating with the high-speed on-chip
oscillator clock. To subsequently change the clock to the X1 oscillation clock, set the oscillator and start oscillation by
using the clock operation mode control register (CMC) and clock operation status control register (CSC) and wait for
oscillation to stabilize by using the oscillation stabilization time counter status register (OSTC).
After the oscillation
stabilizes, set the X1 oscillation clock to fCLK by using the system clock control register (CKC).
[Register settings] Set the register in the order of <1> to <5> below.
<R>
<1> Set (1) the OSCSEL bit of the CMC register, except for the cases where the frequency is equal or more than
10MHz, in such cases set (1) the AMPH bit, to operate the X1 oscillator.
CMC
7
6
5
4
EXCLK
OSCSEL
EXCLKS
OSCSELS
0
1
0
0
3
0
2
1
0
AMPHS1
AMPHS0
AMPH
0
0
1
AMPH bit: Set this bit to 0 if the X1 oscillation clock is 10 MHz or less.
<R>
<2> Using the OSTS register, select the oscillation stabilization time of the X1 oscillator at releasing of the STOP mode.
Example: Setting values when a wait of at least 102.4 μs is set based on a 10 MHz resonator.
OSTS
7
6
5
4
3
0
0
0
0
0
2
1
0
OSTS2
OSTS1
OSTS0
0
1
0
1
0
<3> Clear (0) the MSTOP bit of the CSC register to start oscillating the X1 oscillator.
CSC
7
6
MSTOP
XTSTOP
0
1
5
4
3
2
HIOSTOP
0
0
0
0
0
0
<4> Use the OSTC register to wait for oscillation of the X1 oscillator to stabilize.
Example: Wait until the bits reach the following values when a wait of at least 102.4 μs is set based on a 10 MHz
resonator.
OSTC
7
6
5
4
3
2
1
0
MOST8
MOST9
MOST10
MOST11
MOST13
MOST15
MOST17
MOST18
1
1
1
0
0
0
0
0
<5> Use the MCM0 bit of the CKC register to specify the X1 oscillation clock as the CPU/peripheral hardware clock.
CKC
7
6
5
4
CLS
CSS
MCS
MCM0
0
0
0
1
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5.6.3 Example of setting XT1 oscillation clock
After a reset release, the CPU/peripheral hardware clock (fCLK) always starts operating with the high-speed on-chip
oscillator clock. To subsequently change the clock to the XT1 oscillation clock, set the oscillator and start oscillation by
using the operation speed mode control register (OSMC), clock operation mode control register (CMC), and clock
operation status control register (CSC), set the XT1 oscillation clock to fCLK by using the system clock control register
(CKC).
[Register settings] Set the register in the order of <1> to <5> below.
<1> To run only the real-time clock and 12-bit interval timer on the subsystem clock (ultra-low current consumption)
when in the STOP mode or sub-HALT mode, set the RTCLPC bit to 1.
7
6
5
0/1
3
2
1
0
0
0
0
0
2
1
0
AMPHS1
AMPHS0
AMPH
0/1
0/1
0
WUTMMCK0
RTCLPC
OSMC
4
0
0
0
<2> Set (1) the OSCSELS bit of the CMC register to operate the XT1 oscillator.
CMC
7
6
5
4
EXCLK
OSCSEL
EXCLKS
OSCSELS
0
0
0
1
3
0
AMPHS0 and AMPHS1 bits: These bits are used to specify the oscillation mode of the XT1 oscillator.
<3> Clear (0) the XTSTOP bit of the CSC register to start oscillating the XT1 oscillator.
CSC
7
6
MSTOP
XTSTOP
1
0
5
4
3
2
1
0
0
0
0
0
0
HIOSTOP
0
<4> Use the timer function or another function to wait for oscillation of the subsystem clock to stabilize by using
software.
<5> Use the CSS bit of the CKC register to specify the XT1 oscillation clock as the CPU/peripheral hardware clock.
CKC
7
6
5
4
CLS
CSS
MCS
MCM0
0
1
0
0
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5.6.4 CPU clock status transition diagram
Figure 5-16 shows the CPU clock status transition diagram of this product.
Figure 5-16. CPU Clock Status Transition Diagram
High-speed on-chip oscillator: Woken up
X1 oscillation/EXCLK input: Stops (input port mode)
XT1 oscillation/EXCLKS input: Stops (input port mode)
Power ON
VDD < 1.51 V±0.03
(A)
High-speed on-chip oscillator: Operating
X1 oscillation/EXCLK input: Selectable by CPU
XT1 oscillation/EXCLKS input: Selectable by CPU
High-speed on-chip oscillator:
Selectable by CPU
X1 oscillation/EXCLK input:
Selectable by CPU
XT1 oscillation/EXCLKS input:
Operating
Reset release
VDD ≥ 1.51 V±0.03
High-speed on-chip oscillator: Operating
X1 oscillation/EXCLK input: Stops (input port mode)
XT1 oscillation/EXCLKS input: Stops (input port mode)
(B)
(H)
CPU: Operating
with high-speed
on-chip oscillator
CPU: High-speed
on-chip oscillator
→ STOP
(D)
CPU: Operating
with XT1 oscillation or
EXCLKS input
(J)
(E)
CPU: High-speed
on-chip oscillator
→ HALT
(C)
(G)
CPU: XT1
oscillation/EXCLKS
input → HALT
High-speed on-chip oscillator:
Oscillatable
X1 oscillation/EXCLK input:
Oscillatable
XT1 oscillation/EXCLKS input:
Operating
CPU: Operating
with X1 oscillation or
EXCLK input
High-speed on-chip
oscillator: Selectable by CPU
X1 oscillation/EXCLK input:
Operating
XT1 oscillation/EXCLKS input:
Selectable by CPU
CPU: High-speed
on-chip oscillator
→ SNOOZE
High-speed on-chip oscillator: Stops
X1 oscillation/EXCLK input: Stops
XT1 oscillation/EXCLKS input:
Oscillatable
High-speed on-chip oscillator: Operating
X1 oscillation/EXCLK input: Stops
XT1 oscillation/EXCLKS input: Oscillatable
High-speed on-chip oscillator: Operating
X1 oscillation/EXCLK input: Oscillatable
XT1 oscillation/EXCLKS input: Oscillatable
(I)
(F)
CPU: X1
oscillation/EXCLK
input → STOP
CPU: X1
oscillation/EXCLK
input → HALT
High-speed on-chip oscillator: Stops
X1 oscillation/EXCLK input: Stops
XT1 oscillation/EXCLKS input:
Oscillatable
High-speed on-chip
oscillator: Oscillatable
X1 oscillation/EXCLK input:
Operating
XT1 oscillation/EXCLKS input:
Oscillatable
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Table 5-3 shows transition of the CPU clock and examples of setting the SFR registers.
Table 5-3. CPU Clock Transition and SFR Register Setting Examples (1/5)
(1) CPU operating with high-speed on-chip oscillator clock (B) after reset release (A)
Status Transition
SFR Register Setting
(A) → (B)
SFR registers do not have to be set (default status after reset release).
(2) CPU operating with high-speed system clock (C) after reset release (A)
(The CPU operates with the high-speed on-chip oscillator clock immediately after a reset release (B).)
(Setting sequence of SFR registers)
Setting Flag of SFR Register
CMC Register
Note
CSC
OSTC Register
CKC
Register
Register
MCM0
Status Transition
EXCLK
OSCSEL
AMPH
MSTOP
(A) → (B) → (C)
0
1
0
0
Must be checked
1
0
1
1
0
Must be checked
1
1
1
×
0
Need not be checked
1
(X1 clock: 1 MHz ≤ fX ≤ 10 MHz)
(A) → (B) → (C)
(X1 clock: 10 MHz < fX ≤ 20 MHz)
(A) → (B) → (C)
(external main clock)
Note
The clock operation mode control register (CMC) can be written only once by an 8-bit memory manipulation
instruction after reset release.
Caution Set the clock after the supply voltage has reached the operable voltage of the clock to be set (see
CHAPTER 34 ELECTRICAL SPECIFICATIONS).
(3) CPU operating with subsystem clock (D) after reset release (A)
(The CPU operates with the high-speed on-chip oscillator clock immediately after a reset release (B).)
(Setting sequence of SFR registers)
Setting Flag of SFR Register
Status Transition
(A) → (B) → (D)
CMC Register
Note
EXCLKS OSCSELS AMPHS1 AMPHS0
CSC
Waiting for
CKC
Register
Oscillation
Register
XTSTOP
Stabilization
CSS
0
1
0/1
0/1
0
Necessary
1
1
1
×
×
0
Unnecessary
1
(XT1 clock)
(A) → (B) → (D)
(external sub clock)
Note The clock operation mode control register (CMC) can be written only once by an 8-bit memory manipulation
instruction after reset release.
Remarks 1. ×: don’t care
2. (A) to (J) in Table 5-3 correspond to (A) to (J) in Figure 5-16.
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Table 5-3. CPU Clock Transition and SFR Register Setting Examples (2/5)
(4) CPU clock changing from high-speed on-chip oscillator clock (B) to high-speed system clock (C)
(Setting sequence of SFR registers)
CMC Register
Setting Flag of SFR Register
Status Transition
(B) → (C)
Note 1
OSTS
CSC
Register
Register
Register
CKC
MSTOP
MCM0
OSTC Register
EXCLK
OSCSEL
AMPH
0
1
0
Note 2
0
Must be checked
1
0
1
1
Note 2
0
Must be checked
1
1
1
×
Note 2
0
Need not be
1
(X1 clock: 1 MHz ≤ fX ≤ 10 MHz)
(B) → (C)
(X1 clock: 10 MHz < fX ≤ 20 MHz)
(B) → (C)
checked
(external main clock)
Unnecessary if these registers Unnecessary if the CPU is operating with
the high-speed system clock
are already set
Notes 1. The clock operation mode control register (CMC) can be changed only once after reset release. This
setting is not necessary if it has already been set.
2. Set the oscillation stabilization time as follows.
• Desired the oscillation stabilization time counter status register (OSTC) oscillation stabilization time ≤
Oscillation stabilization time set by the oscillation stabilization time select register (OSTS)
Caution Set the clock after the supply voltage has reached the operable voltage of the clock to be set (see
CHAPTER 34 ELECTRICAL SPECIFICATIONS).
(5) CPU clock changing from high-speed on-chip oscillator clock (B) to subsystem clock (D)
(Setting sequence of SFR registers)
Setting Flag of SFR Register
Status Transition
(B) → (D)
CMC Register
Note
CSC
Waiting for
Register
Oscillation
CKC Register
EXCLKS
OSCSELS
XTSTOP
Stabilization
CSS
0
1
0
Necessary
1
1
1
0
Unnecessary
1
(XT1 clock)
(B) → (D)
(external sub clock)
Unnecessary if the CPU is operating
with the subsystem clock
Note The clock operation mode control register (CMC) can be written only once by an 8-bit memory manipulation
instruction after reset release.
Remarks 1. ×: don’t care
2. (A) to (J) in Table 5-3 correspond to (A) to (J) in Figure 5-16.
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Table 5-3. CPU Clock Transition and SFR Register Setting Examples (3/5)
(6) CPU clock changing from high-speed system clock (C) to high-speed on-chip oscillator clock (B)
(Setting sequence of SFR registers)
Setting Flag of SFR Register
Status Transition
<R>
(C) → (B)
CSC Register
Oscillation accuracy
CKC Register
HIOSTOP
stabilization time
MCM0
0
30 μ s
0
Unnecessary if the CPU is operating with the
high-speed on-chip oscillator clock
(7) CPU clock changing from high-speed system clock (C) to subsystem clock (D)
(Setting sequence of SFR registers)
Setting Flag of SFR Register
CSC Register
Waiting for Oscillation
CKC Register
XTSTOP
Stabilization
CSS
0
Necessary
1
Status Transition
(C) → (D)
Unnecessary if the CPU is operating with the
subsystem clock
(8) CPU clock changing from subsystem clock (D) to high-speed on-chip oscillator clock (B)
(Setting sequence of SFR registers)
Setting Flag of SFR Register
Status Transition
(D) → (B)
CSC Register
CKC Register
HIOSTOP
MCM0
CSS
0
0
0
Unnecessary if the CPU
Unnecessary if this
is operating with the
register is already set
high-speed on-chip
oscillator clock
Remark (A) to (J) in Table 5-3 correspond to (A) to (J) in Figure 5-16.
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Table 5-3. CPU Clock Transition and SFR Register Setting Examples (4/5)
(9) CPU clock changing from subsystem clock (D) to high-speed system clock (C)
(Setting sequence of SFR registers)
Setting Flag of SFR Register
<R>
OSTS
CSC Register
Register
MSTOP
Note
0
Note
Note
OSTC Register
CKC Register
CSS
MCM0
Must be checked
0
1
0
Must be checked
0
1
0
Need not be checked
0
1
Status Transition
(D) → (C) (X1 clock: 1 MHz ≤
fX ≤ 10 MHz)
(D) → (C) (X1 clock: 10 MHz <
fX ≤ 20 MHz)
(D) → (C) (external main
clock)
Unnecessary if the CPU is operating with the high-speed
system clock
Note
Unnecessary if these
registers are already set
Set the oscillation stabilization time as follows.
• Desired the oscillation stabilization time counter status register (OSTC) oscillation stabilization time ≤
Oscillation stabilization time set by the oscillation stabilization time select register (OSTS)
Caution Set the clock after the supply voltage has reached the operable voltage of the clock to be set (see
CHAPTER 34 ELECTRICAL SPECIFICATIONS).
(10) • HALT mode (E) set while CPU is operating with high-speed on-chip oscillator clock (B)
• HALT mode (F) set while CPU is operating with high-speed system clock (C)
• HALT mode (G) set while CPU is operating with subsystem clock (D)
Status Transition
(B) → (E)
Setting
Executing HALT instruction
(C) → (F)
(D) → (G)
Remark (A) to (J) in Table 5-3 correspond to (A) to (J) in Figure 5-16.
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Table 5-3. CPU Clock Transition and SFR Register Setting Examples (5/5)
(11) • STOP mode (H) set while CPU is operating with high-speed on-chip oscillator clock (B)
• STOP mode (I) set while CPU is operating with high-speed system clock (C)
(Setting sequence)
Status Transition
(B) → (H)
Setting
−
Stopping peripheral
functions that cannot
(C) → (I)
In X1 oscillation
operate in STOP mode
Executing STOP
instruction
Sets the OSTS
register
External main
−
system clock
(12) CPU changing from STOP mode (H) to SNOOZE mode (J)
For details about the setting for switching from the STOP mode to the SNOOZE mode, see 14.8 SNOOZE Mode
Function, 17.5.7 SNOOZE mode function and 17.7.3 SNOOZE mode function.
Remark (A) to (J) in Table 5-3 correspond to (A) to (J) in Figure 5-16.
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5.6.5 Condition before changing CPU clock and processing after changing CPU clock
Condition before changing the CPU clock and processing after changing the CPU clock are shown below.
Table 5-4. Changing CPU Clock (1/2)
CPU Clock
Before Change
Condition Before Change
Processing After Change
After Change
Stabilization of X1 oscillation
• OSCSEL = 1, EXCLK = 0, MSTOP = 0
Operating current can be reduced by
chip oscillator
clock
• After elapse of oscillation stabilization time
(HIOSTOP = 1).
High-speed on-
X1 clock
External main
Enabling input of external clock from the
system clock
EXCLK pin
• OSCSEL = 1, EXCLK = 1, MSTOP = 0
XT1 clock
Stabilization of XT1 oscillation
• OSCSELS = 1, EXCLKS = 0, XTSTOP = 0
stopping high-speed on-chip oscillator
• After elapse of oscillation stabilization time
X1 clock
External
Enabling input of external clock from the
subsystem clock
EXCLKS pin
• OSCSELS = 1, EXCLKS = 1, XTSTOP = 0
High-speed on-
Oscillation of high-speed on-chip oscillator
• HIOSTOP = 0
chip oscillator
X1 oscillation can be stopped (MSTOP = 1).
clock
External main
Transition not possible
system clock
(To change the clock, set it again after
XT1 clock
Stabilization of XT1 oscillation
• OSCSELS = 1, EXCLKS = 0, XTSTOP = 0
−
executing reset once.)
X1 oscillation can be stopped (MSTOP = 1).
• After elapse of oscillation stabilization time
External
Enabling input of external clock from the
subsystem clock
EXCLKS pin
• OSCSELS = 1, EXCLKS = 1, XTSTOP = 0
External main
High-speed on-
system clock
chip oscillator
Oscillation of high-speed on-chip oscillator
• HIOSTOP = 0
X1 oscillation can be stopped (MSTOP = 1).
External main system clock input can be
disabled (MSTOP = 1).
clock
X1 clock
Transition not possible
−
(To change the clock, set it again after
executing reset once.)
XT1 clock
Stabilization of XT1 oscillation
• OSCSELS = 1, EXCLKS = 0, XTSTOP = 0
External main system clock input can be
disabled (MSTOP = 1).
• After elapse of oscillation stabilization time
External
Enabling input of external clock from the
External main system clock input can be
subsystem clock
EXCLKS pin
• OSCSELS = 1, EXCLKS = 1, XTSTOP = 0
disabled (MSTOP = 1).
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Table 5-4. Changing CPU Clock (2/2)
CPU Clock
Before Change
XT1 clock
Condition Before Change
Processing After Change
After Change
High-speed on-
Oscillation of high-speed on-chip oscillator
XT1 oscillation can be stopped (XTSTOP =
chip oscillator
and selection of high-speed on-chip
1)
clock
oscillator clock as main system clock
• HIOSTOP = 0, MCS = 0
X1 clock
Stabilization of X1 oscillation and selection
of high-speed system clock as main system
clock
• OSCSEL = 1, EXCLK = 0, MSTOP = 0
• After elapse of oscillation stabilization time
• MCS = 1
External main
Enabling input of external clock from the
system clock
EXCLK pin and selection of high-speed
system clock as main system clock
• OSCSEL = 1, EXCLK = 1, MSTOP = 0
• MCS = 1
External
Transition not possible
subsystem clock
(To change the clock, set it again after
−
executing reset once.)
External
High-speed on-
Oscillation of high-speed on-chip oscillator
External subsystem clock input can be
subsystem clock
chip oscillator
and selection of high-speed on-chip
disabled (XTSTOP = 1).
clock
oscillator clock as main system clock
• HIOSTOP = 0, MCS = 0
X1 clock
Stabilization of X1 oscillation and selection
of high-speed system clock as main system
clock
• OSCSEL = 1, EXCLK = 0, MSTOP = 0
• After elapse of oscillation stabilization time
• MCS = 1
External main
Enabling input of external clock from the
system clock
EXCLK pin and selection of high-speed
system clock as main system clock
• OSCSEL = 1, EXCLK = 1, MSTOP = 0
• MCS = 1
XT1 clock
Transition not possible
−
(To change the clock, set it again after
executing reset once.)
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5.6.6 Time required for switchover of CPU clock and main system clock
By setting bits 4 and 6 (MCM0, CSS) of the system clock control register (CKC), the CPU clock can be switched
(between the main system clock and the subsystem clock), and main system clock can be switched (between the highspeed on-chip oscillator clock and the high-speed system clock).
The actual switchover operation is not performed immediately after rewriting to the CKC register; operation continues
on the pre-switchover clock for several clocks (see Table 5-5 to Table 5-7).
Whether the CPU is operating on the main system clock or the subsystem clock can be ascertained using bit 7 (CLS) of
the CKC register. Whether the main system clock is operating on the high-speed system clock or high-speed on-chip
oscillator clock can be ascertained using bit 5 (MCS) of the CKC register.
When the CPU clock is switched, the peripheral hardware clock is also switched.
Table 5-5. Maximum Time Required for Main System Clock Switchover
Clock A
Switching directions
Clock B
Remark
fIH
fMX
See Table 5-6
fMAIN
fSUB
See Table 5-7
Table 5-6. Maximum Number of Clocks Required for fIH ↔ fMX
Set Value Before Switchover
Set Value After Switchover
MCM0
MCM0
0
1
(f MAIN = f IH )
(f MAIN = f MX )
0
f MX ≥f IH
2 clock
(f MAIN = f IH )
f MX <f IH
2fIH/fMX clock
1
f MX ≥f IH
2fMX/fIH clock
(f MAIN = f MX )
f MX <f IH
2 clock
Table 5-7. Maximum Number of Clocks Required for fMAIN ↔ fSUB
Set Value Before Switchover
Set Value After Switchover
CSS
CSS
0
1
(f CLK = f MAIN )
(f CLK = f SUB )
0
1 + 2fMAIN/fSUB clock
(f CLK = f MAIN )
1
3 clock
(f CLK = f SUB)
Remarks 1. The number of clocks listed in Table 5-6 to Table 5-7 is the number of CPU clocks before switchover.
2. Calculate the number of clocks in Table 5-6 to Table 5-7 by rounding up the number after the decimal
position.
Example When switching the main system clock from the high-speed on-chip oscillator clock (when 8
MHz selected) to the high-speed system clock (@ oscillation with fIH = 8 MHz, fMX = 10 MHz)
1 + fIH/fMX = 1 + 8/10 = 1 + 0.8 = 1.8 → 2 clocks
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5.6.7 Conditions before clock oscillation is stopped
The following lists the register flag settings for stopping the clock oscillation (disabling external clock input) and
conditions before the clock oscillation is stopped.
Table 5-8. Conditions Before the Clock Oscillation Is Stopped and Flag Settings
Clock
Conditions Before Clock Oscillation Is Stopped
Flag Settings of SFR
(External Clock Input Disabled)
Register
High-speed on-chip
MCS = 1 or CLS = 1
oscillator clock
(The CPU is operating on a clock other than the high-speed on-chip
HIOSTOP = 1
oscillator clock.)
X1 clock
MCS = 0 or CLS = 1
External main system clock
(The CPU is operating on a clock other than the high-speed system clock.)
XT1 clock
CLS = 0
External subsystem clock
(The CPU is operating on a clock other than the subsystem clock.)
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<R> 5.7 Operation-Verified Resonators and Reference Oscillator Constants
As of December 2011
The following shows operation-verified resonators and their reference oscillator constants.
These oscillator constants are reference values based on evaluation in a specific environment by the resonator
manufacturer.
If it is necessary to optimize the oscillator characteristics in the actual application, apply to the resonator manufacturer
for evaluation on the implementation circuit.
The oscillation voltage and oscillation frequency only indicate the oscillator characteristic.
Use the RL78/G14 so that the internal operation conditions are within the specifications of the DC and AC
characteristics.
Figure 5-17. Example of External Circuit
(a) X1 oscillation
VSS X1
C1
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Rd
C2
(b) XT1 oscillation
VSS XT2
C4
XT1
Rd
C3
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(1) X1 oscillation
Manufacturer
Resonator
Part Number
SMD/
Frequ
Lead
ency
Operation
(MHz)
Mode
Flash
Circuit Constants
(Reference)
Voltage
Note 2
Range (V)
C1 (pF)
C2 (pF)
Rd (kΩ )
MIN.
MAX.
(39)
(39)
0
1.6
5.5
(15)
(15)
0
(39)
(39)
0
1.8
5.5
(15)
(15)
0
(15)
(15)
0
(15)
(15)
0
(15)
(15)
0
(15)
(15)
0
(10)
(10)
0
(15)
(15)
0
(15)
(15)
0
2.4
5.5
(15)
(15)
0
(15)
(15)
0
(15)
(15)
0
(10)
(10)
0
(15)
(15)
0
(10)
(10)
0
(15)
(15)
0
(15)
(15)
0
(5)
(5)
0
(5)
(5)
0
2.7
5.5
(5)
(5)
0
1.8
5.5
2.4
5.5
2.7
5.5
Note 1
Murata
Ceramic
CSTCR4M00G55-R0
SMD
Manufacturing
resonator
CSTLS4M00G53-B0
Lead
Co., Ltd.
Nihon Dempa
Ceramic
Kogyo
resonator
CSTCR4M00G55-R0
SMD
CSTLS4M00G53-B0
Lead
CSTCR5M00G53-R0
SMD
CSTLS5M00G53-B0
Lead
CSTCR6M00G53-R0
SMD
CSTLS6M00G53-B0
Lead
CSTCE8M00G52-R0
SMD
CSTLS8M00G53-B0
Lead
CSTCR5M00G53-R0
SMD
CSTLS5M00G53-B0
Lead
CSTCR6M00G53-R0
SMD
CSTLS6M00G53-B0
Lead
CSTCE8M00G52-R0
SMD
CSTLS8M00G53-B0
Lead
CSTCE10M0G52-R0
SMD
CSTLS10M0G53-B0
Lead
CSTCE16M0V53-R0
SMD
CSTLS16M0X51-B0
Lead
CSTCE20M0V51-R0
SMD
CSTLS20M0X51-B0
Lead
4.0
LV
LS
5.0
6.0
8.0
5.0
HS
6.0
8.0
10.0
16.0
20.0
HS
NX8045GB
Note 3
SMD
8
LS
NX8045GB
Note 3
SMD
8
HS
NX5032GA
Note 3
SMD
16
HS
NX3225HA
Note 3
SMD
20
HS
Co., Ltd.
Notes 1.
4.0
Note 3
Set the flash operation mode by using the CMODE1 and CMODE0 bits of the option byte
(000C2H/010C2H).
2.
Values in parentheses in the C1 and C2 columns indicate an internal capacitance.
3.
When using these resonators, contact Nihon Dempa Kogyo Co., Ltd (http://www.ndk.com/en) for more
information on matching.
(Cautions are listed on the next page.)
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Cautions 1.
The parameters of operation-verified resonators and the reference oscillator constants shown
above are only reference values based on the information provided from the resonator
manufacturer. Renesas Electronics Corporation disclaims any warranties regarding the values.
The reference oscillator constants are the results of tests carried out by the resonator
manufacturer under fixed operating conditions. Values may differ for actual systems. Confirm
the optimal oscillator constants applicable to your systems with the resonator manufacturer for
evaluation on the implementation circuit. In addition, the above conditions are for oscillating the
resonator which is connected to the MCU, and do not show MCU operation conditions. Use the
MCU so that the internal operation conditions are within the specifications of the DC and AC
characteristics.
2.
Left open because feed-back resistors are internally provided in the MCU.
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(2) XT1 oscillation (crystal resonator)
Manufacturer
Part Number
SMD/
Freque
Lead
ncy
Capacita
(kHz)
nce
Load
X1 oscillation
Mode
Circuit Constants
Voltage
(Reference)
Range (V)
Note 1
C3 (pF)
C4 (pF)
Rd (kΩ )
MIN.
MAX.
1.6
5.5
1.6
5.5
CL (pF)
SSP-T7-FL
Seiko
SMD
32.768
6.0
Normal oscillation
10
9
0
4.4
Low power
7
5
0
6
3
0
Note 2
Instruments
Inc.
consumption
oscillation
3.7
Ultra-low power
consumption
oscillation
VT-200-FL
Lead
6.0
Normal oscillation
10
9
0
4.4
Low power
7
5
0
6
3
0
Note 2
consumption
oscillation
3.7
Ultra-low power
consumption
oscillation
Nihon Dempa
NX3215SA
Kogyo
Note 3
SMD
32.768
6.0
Normal oscillation
Note 3
Low power
Co., Ltd.
consumption
oscillation
Ultra-low power
consumption
oscillation
Notes 1.
Set the XT1 oscillation mode by using the AMPHS0 and AMPHS1 bits of the clock operation mode control
register (CMC).
2.
When using these resonators, contact Seiko Instruments Inc., Ltd (http://www.sii-crystal.com) for more
information on matching.
3.
When using these resonators, contact Nihon Dempa Kogyo Co., Ltd (http://www.ndk.com/en) for more
information on matching.
Cautions 1.
The parameters of operation-verified resonators and the reference oscillator constants shown
above are only reference values based on the information provided from the resonator
manufacturer. Renesas Electronics Corporation disclaims any warranties regarding the values.
The reference oscillator constants are the results of tests carried out by the resonator
manufacturer under fixed operating conditions. Values may differ for actual systems. Confirm
the optimal oscillator constants applicable to your systems with the resonator manufacturer for
evaluation on the implementation circuit. In addition, the above conditions are for oscillating the
resonator which is connected to the MCU, and do not show MCU operation conditions. Use the
MCU so that the internal operation conditions are within the specifications of the DC and AC
characteristics.
2.
Left open because feed-back resistors are internally provided in the MCU.
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CHAPTER 6 TIMER ARRAY UNIT
The number of units or channels of the timer array unit differs, depending on the product.
Units
Channels
30, 32, 36, 40, 44, 48, 52, 64-pin
80, 100-pin
Unit 0
Channel 0
√
√
Channel 1
√
√
Channel 2
√
√
Channel 3
√
√
Channel 0
−
√
Channel 1
−
√
Channel 2
−
√
Channel 3
−
√
Unit 1
Cautions 1. The presence or absence of timer I/O pins depends on the product. See Table 6-2 Timer I/O Pins
provided in Each Product for details.
2. Most of the following descriptions in this chapter use the 100-pin products as an example.
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The timer array unit has four 16-bit timers.
Each 16-bit timer is called a channel and can be used as an independent timer. In addition, two or more “channels” can
be used to create a high-accuracy timer.
TIMER ARRAY UNIT
channel 0
16-bit timers
channel 1
channel 2
channel 3
For details about each function, see the table below.
Independent channel operation function
Simultaneous channel operation function
• Interval timer (→ refer to 6.7.1)
• One-shot pulse output(→ refer to 6.8.1)
• Square wave output (→ refer to 6.7.1)
• PWM output(→ refer to 6.8.2)
• Multiple PWM output(→ refer to 6.8.3)
• External event counter (→ refer to 6.7.2)
• Divider function
Note
(→ refer to 6.7.3)
• Input pulse interval measurement (→ refer to 6.7.4)
• Measurement of high-/low-level width of input signal
(→ refer to 6.7.5)
• Delay counter (→ refer to 6.7.6)
Note Only channel 0 of timer arra unit 0.
It is possible to use the 16-bit timer of channels 1 and 3 of the units 0 and 1 as two 8-bit timers (higher and lower). The
functions that can use channels 1 and 3 as 8-bit timers are as follows:
• Interval timer
• External event counter (lower 8-bit timer only)
• Delay counter (lower 8-bit timer only)
Channel 3 of timer array unit 0 can be used to realize LIN-bus communication operating in combination with UART0 of
the serial array unit.
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6.1 Functions of Timer Array Unit
Timer array unit has the following functions.
6.1.1 Independent channel operation function
By operating a channel independently, it can be used for the following purposes without being affected by the operation
mode of other channels.
(1) Interval timer
Each timer of a unit can be used as a reference timer that generates an interrupt (INTTMmn) at fixed intervals.
Operation clock
Compare operation
Channel n
Interrupt signal
(INTTMmn)
(2) Square wave output
A toggle operation is performed each time INTTMmn interrupt is generated and a square wave with a duty factor of
50% is output from a timer output pin (TOmn).
Operation clock
Compare operation
Channel n
Timer output
(TOmn)
(3) External event counter
Each timer of a unit can be used as an event counter that generates an interrupt when the number of the valid
edges of a signal input to the timer input pin (TImn) has reached a specific value.
Timer input
(TImn)
Edge detection
Compare operation
Interrupt signal
(INTTMmn)
Channel n
(4) Divider function (channel 0 only)
A clock input from a timer input pin (TI00) is divided and output from an output pin (TOm0).
Timer input
(TI00)
Compare operation
Channel 0
Timer output
(TO00)
(5) Input pulse interval measurement
Counting is started by the valid edge of a pulse signal input to a timer input pin (TImn). The count value of the
timer is captured at the valid edge of the next pulse. In this way, the interval of the input pulse can be measured.
Timer input
(TImn)
Edge detection
Capture operation
Channel n
xxH
00H
Start Capture
(Note, Caution, and Remark are listed on the next page.)
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(6) Measurement of high-/low-level width of input signal
Counting is started by a single edge of the signal input to the timer input pin (TImn), and the count value is
captured at the other edge. In this way, the high-level or low-level width of the input signal can be measured.
Edge detection
Capture operation
Timer input
(TImn)
Channel n
00H xxH
Start Capture
(7) Delay counter
Counting is started at the valid edge of the signal input to the timer input pin (TImn), and an interrupt is generated
after any delay period.
Edge detection
Compare operation
Timer input
(TImn)
Channel n
Interrupt signal
(INTTMmn)
Remarks 1 n: Channel number (n = 0 to 3)
2. The presence or absence of timer I/O pins depends on the product. See Table 6-2 Timer I/O Pins
provided in Each Product for details.
6.1.2 Simultaneous channel operation function
By using the combination of a master channel (a reference timer mainly controlling the cycle) and slave channels
(timers operating according to the master channel), channels can be used for the following purposes.
(1) One-shot pulse output
Two channels are used as a set to generate a one-shot pulse with a specified output timing and a specified pulse
width.
Timer input
(TImn)
Edge detection
Compare operation
Interrupt signal (INTTMmn)
Channel n (master)
Compare operation
Channel p (slave)
Output
timing
Timer output
(TOmp)
Toggle
(Master)
Start
(Master)
Pulse width
Toggle
(Slave)
(2) PWM (Pulse Width Modulation) output
Two channels are used as a set to generate a pulse with a specified period and a specified duty factor.
Operation clock
Compare operation
Interrupt signal (INTTMmn)
Channel n (master)
Compare operation
Channel p (slave)
Timer output
(TOmp)
Duty
Period
(Caution is listed on the next page.)
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(3) Multiple PWM (Pulse Width Modulation) output
By extending the PWM function and using one master channel and two or more slave channels, up to three types
of PWM signals that have a specific period and a specified duty factor can be generated.
Operation clock
Compare operation
Interrupt signal (INTTMmn)
Channel n (master)
Compare operation
Channel p (slave)
Timer output
(TOmp)
Duty
Period
Compare operation
Channel q (slave)
Caution
Timer output
(TOmq)
Duty
Period
The following rules apply when using multiple channels simultaneously.
• Only an even-numbered channel (channel 0, 2) can be specified as the master channel.
• Only channels with lower channel numbers than the master channel can be specified as slave
channels (multiple slave channels can be set).
For details about the rules of simultaneous channel operation function, see 6.4.1 Basic rules of
simultaneous channel operation function.
Remark
m: Unit number (m = 0, 1), n: Channel number (n = 0 to 3),
p, q: Slave channel number (n < p < q ≤ 3)
6.1.3 8-bit timer operation function (channels 1 and 3 only)
The 8-bit timer operation function makes it possible to use a 16-bit timer channel in a configuration consisting of two 8bit timer channels. This function can only be used for channels 1 and 3.
Caution
There are several rules for using 8-bit timer operation function.
For details, see 6.4.2 Basic rules of 8-bit timer operation function (channels 1 and 3 only).
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6.1.4 LIN-bus supporting function (channel 3 of unit 0 only)
Timer array unit is used to check whether signals received in LIN-bus communication match the LIN-bus
communication format.
(1) Detection of wakeup signal
The timer starts counting at the falling edge of a signal input to the serial data input pin (RxD0) of UART0 and the
count value of the timer is captured at the rising edge. In this way, a low-level width can be measured. If the lowlevel width is greater than a specific value, it is recognized as a wakeup signal.
(2) Detection of sync break field
The timer starts counting at the falling edge of a signal input to the serial data input pin (RxD0) of UART0 after a
wakeup signal is detected, and the count value of the timer is captured at the rising edge. In this way, a low-level
width is measured. If the low-level width is greater than a specific value, it is recognized as a sync break field.
(3) Measurement of pulse width of sync field
After a sync break field is detected, the low-level width and high-level width of the signal input to the serial data
input pin (RxD0) of UART0 are measured. From the bit interval of the sync field measured in this way, a baud rate
is calculated.
Remark For details about setting up the operations used to implement the LIN-bus, see 6.3 (13) Input switch control
register (ISC) and 6.7.5 Operation as input signal high-/low-level width measurement.
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6.2 Configuration of Timer Array Unit
Timer array unit includes the following hardware.
Table 6-1. Configuration of Timer Array Unit
Item
Timer/counter
Configuration
Timer count register mn (TCRmn)
Register
Timer data register mn (TDRmn)
Timer input
TI00 to TI03, TI10 to TI13
Timer output
TO00 to TO03, TO10 to TO13 pins
Control registers
<Registers of unit setting block>
• Peripheral enable register 0 (PER0)
• Timer clock select register m (TPSm)
• Timer channel enable status register m (TEm)
• Timer channel start register m (TSm)
• Timer channel stop register m (TTm)
• Timer input select register 0 (TIS0)
• Timer output enable register m (TOEm)
• Timer output register m (TOm)
• Timer output level register m (TOLm)
• Timer output mode register m (TOMm)
Note 1
, RxD0 pin (for LIN-bus)
Note 1
, output controller
<Registers of each channel>
• Timer mode register mn (TMRmn)
• Timer status register mn (TSRmn)
• Input switch control register (ISC)
• Noise filter enable registers 1, 2 (NFEN1, NFEN2)
Note 2
• Port mode register (PMxx)
Note 2
• Port register (Pxx)
Notes 1. The presence or absence of timer I/O pins of channel 0 to 3 depends on the product. See Table 6-2 Timer
I/O Pins provided in Each Product for details.
2. The port mode registers (PMxx) and port registers (Pxx) to be set differ depending on the product. for
details, see 6. 3 (15) Port mode registers 0, 1, 3, 6 (PM0, PM1, PM3, PM6).
Remark
m: Unit number (m = 0, 1), n: Channel number (n = 0 to 3)
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The presence or absence of timer I/O pins in each timer array unit channel depends on the product.
Table 6-2. Timer I/O Pins provided in Each Product
Timer array unit
Unit 1
Unit 0
channels
I/O Pins of Each Product
100-pin
80-pin
30, 32, 36, 40, 44, 48, 52, 64-pin
Channel 0
P00/TI00, P01/TO00
Channel 1
P16/TI01/TO01
Channel 2
P17/TI02/TO02
Channel 3
P31/TI03/TO03
Channel 0
P64/TI10/TO10
×
×
×
×
×
Channel 1
P65/TI11/TO11
×
×
×
×
×
Channel 2
P66/TI12/TO12
×
×
×
×
×
Channel 3
P67/TI13/TO13
×
×
×
×
×
Remarks 1. When timer input and timer output are shared by the same pin, either only timer input or only timer output
can be used.
2. ×: The channel is not available.
Figures 6-1 and 6-2 show the block diagrams of the timer array unit.
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Figure 6-1. Entire Configuration of Timer Array Unit 0 (Example: 100-pin products)
Timer clock select register 0 (TPS0)
PRS031PRS030 PRS021 PRS020 PRS013 PRS012PRS011 PRS010 PRS003 PRS002 PRS001 PRS000
Timer input select
register 0 (TIS0)
2
TIS04 TIS02 TIS01 TIS00
2
4
4
Prescaler
fCLK
fCLK/21, fCLK/22,
fCLK/28, fCLK/210, fCLK/24,fCLK/26,
fCLK/212,fCLK/214,
Peripheral
enable
TAU0EN
register 0
(PER0)
Selector
Selector
Selector
Slave/master controller
Selector
Event input
from ELC
TI00
Selector
fCLK/20 - fCLK/215
TO00
INTTM00
(Timer interrupt)
Channel 0
TO01
fSUB
Channel 1
Selector
fIL
TI01
Slave/master controller
INTTM01
INTTM01H
TO02
Event input
from ELC
TI02
Channel 2
INTTM02
TO03
TI03
RxD0
(Serial input pin)
Remark
INTTM03
INTTM03H
Channel 3 (LIN-bus supported)
fSUB: Subsystem clock frequency
fIL:
Low-speed on-chip oscillator clock frequency
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Figure 6-2. Internal Block Diagram of Channel of Timer Array Unit 0
Slave/master
controller
CK01
Count clock
selection
CK00
Operating
clock selection
Trigger signal to slave channel
Clock signal to slave channel
Interrupt signal to slave channel
fMCK
TI0n
Output
controller
TO0n
Output latch
(Pxx)
Mode
selection
Trigger
selection
Edge
detection
Timer controller
fTCLK
PMxx
Interrupt
controller
INTTM0n
(Timer interrupt)
Timer counter register 0n (TCR0n)
Timer status
register 0n (TSR0n)
Timer data register 0n (TDR0n)
Slave/master
controller
CKS0n CCS0n
OVF
0n
MAS
STS0n2 STS0n1 STS0n0 CIS0n1 CIS0n0 MD0n3 MD0n2 MD0n1 MD0n0
TER0n
Channel n
Remark
Overflow
Timer mode register 0n (TMR0n)
n = 0, 2
(1) Timer count register mn (TCRmn)
The TCRmn register is a 16-bit read-only register and is used to count clocks.
The value of this counter is incremented or decremented in synchronization with the rising edge of a count clock.
Whether the counter is incremented or decremented depends on the operation mode that is selected by the
MDmn3 to MDmn0 bits of timer mode register mn (TMRmn) (refer to 6.3 (3) Timer mode register mn (TMRmn)).
Figure 6-3. Format of Timer Count Register mn (TCRmn)
Address: F0180H, F0181H (TCR00) to F0186H, F0187H (TCR03),
After reset: FFFFH
R
F01C0H, F01C1H (TCR10) to F01C6H, F01C7H (TCR13)
F0181H (TCR00)
15
14
13
12
11
F0180H (TCR00)
10
9
8
7
6
5
4
3
2
1
0
TCRmn
Remark
m: Unit number (m = 0, 1), n: Channel number (n = 0 to 3)
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The count value can be read by reading timer count register mn (TCRmn).
The count value is set to FFFFH in the following cases.
• When the reset signal is generated
• When the TAUmEN bit of peripheral enable register 0 (PER0) is cleared
• When counting of the slave channel has been completed in the PWM output mode
<R>
• When counting of the slave channel has been completed in the delay count mode
• When counting of the master/slave channel has been completed in the one-shot pulse output mode
• When counting of the slave channel has been completed in the multiple PWM output mode
The count value is cleared to 0000H in the following cases.
• When the start trigger is input in the capture mode
• When capturing has been completed in the capture mode
Caution
The count value is not captured to timer data register mn (TDRmn) even when the TCRmn
register is read.
The TCRmn register read value differs as follows according to operation mode changes and the operating status.
Table 6-3. Timer Count Register mn (TCRmn) Read Value in Various Operation Modes
Operation Mode
Count Mode
Timer count register mn (TCRmn) Read Value
Value if the
operation mode
was changed after
releasing reset
Interval timer
mode
Count down
Note
Value if the
operation mode was
changed after count
operation paused
(TTmn = 1)
Value if the
Operation was
restarted after count
operation paused
(TTmn = 1)
Value when waiting
for a start trigger
after one count
FFFFH
Undefined
Stop value
−
Capture mode
Count up
0000H
Undefined
Stop value
−
Event counter
mode
Count down
FFFFH
Undefined
Stop value
−
One-count mode
Count down
FFFFH
Undefined
Stop value
FFFFH
Capture & onecount mode
Count up
0000H
Undefined
Stop value
Capture value of
TDRmn register + 1
Note This indicates the value read from the TCRmn register when channel n has stopped operating as a timer (TEmn = 0)
and has been enabled to operate as a counter (TSmn = 1). The read value is held in the TCRmn register until the
count operation starts.
Remark
m: Unit number (m = 0, 1), n: Channel number (n = 0 to 3)
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(2) Timer data register mn (TDRmn)
This is a 16-bit register from which a capture function and a compare function can be selected.
The capture or compare function can be switched by selecting an operation mode by using the MDmn3 to MDmn0
bits of timer mode register mn (TMRmn).
The value of the TDRmn register can be changed at any time.
This register can be read or written in 16-bit units.
In addition, for the TDRm1 and TDRm3 registers, while in the 8-bit timer mode (when the SPLIT bits of timer mode
registers 01 and 03 (TMRm1, TMRm3) are 1), it is possible to rewrite the data in 8-bit units, with TDRm1H and
TDRm3H used as the higher 8 bits, and TDRm1L and TDRm3L used as the lower 8 bits. However, reading is only
possible in 16-bit units.
Reset signal generation clears this register to 0000H.
Figure 6-4. Format of Timer Data Register mn (TDRmn) (n = 0, 2)
Address: FFF18H, FFF19H (TDR00), FFF64H, FFF65H (TDR02),
After reset: 0000H
R/W
FFF70H, FFF71H (TDR10), FFF74H, FFF75H (TDR12)
FFF19H (TDR00)
15
14
13
12
11
10
FFF18H (TDR00)
9
8
7
6
5
4
3
2
1
0
2
1
0
TDRmn
Figure 6-5. Format of Timer Data Register mn (TDRmn) (n = 1, 3)
Address: FFF1AH, FFF1BH (TDR01), FFF66H, FFF67H (TDR03),
After reset: 0000H
R/W
FFF72H, FFF73H (TDR11), FFF76H, FFF77H (TDR13)
FFF1BH (TDR01H)
15
14
13
12
11
10
FFF1AH (TDR01L)
9
8
7
6
5
4
3
TDRmn
(i) When timer data register mn (TDRmn) is used as compare register
Counting down is started from the value set to the TDRmn register. When the count value reaches 0000H, an
interrupt signal (INTTMmn) is generated. The TDRmn register holds its value until it is rewritten.
Caution
The TDRmn register does not perform a capture operation even if a capture trigger is input,
when it is set to the compare function.
(ii) When timer data register mn (TDRmn) is used as capture register
The count value of timer count register mn (TCRmn) is captured to the TDRmn register when the capture
trigger is input.
A valid edge of the TImn pin can be selected as the capture trigger. This selection is made by timer mode
register mn (TMRmn).
Remark
m: Unit number (m = 0, 1), n: Channel number (n = 0 to 3)
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6.3 Registers Controlling Timer Array Unit
Timer array unit is controlled by the following registers.
• Peripheral enable register 0 (PER0)
• Timer clock select register m (TPSm)
• Timer mode register mn (TMRmn)
• Timer status register mn (TSRmn)
• Timer channel enable status register m (TEm)
• Timer channel start register m (TSm)
• Timer channel stop register m (TTm)
• Timer input select register 0 (TIS0)
• Timer output enable register m (TOEm)
• Timer output register m (TOm)
• Timer output level register m (TOLm)
• Timer output mode register m (TOMm)
• Input switch control register (ISC)
• Noise filter enable registers 1, 2 (NFEN1, NFEN2)
• Port mode register (PMxx)
• Port register (Pxx)
Note
Note
Note
The port mode registers (PMxx) and port registers (Pxx) to be set differ depending on the product. For details,
see 6. 3 (15) Port mode registers 0, 1, 3, 6 (PM0, PM1, PM3, PM6).
Remark
m: Unit number (m = 0, 1), n: Channel number (n = 0 to 3)
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(1) Peripheral enable register 0 (PER0)
This registers is used to enable or disable supplying the clock to the peripheral hardware. Clock supply to a
hardware macro that is not used is stopped in order to reduce the power consumption and noise.
When the timer array unit 0 is used, be sure to set bit 0 (TAU0EN) of this register to 1.
When the timer array unit 1 is used, be sure to set bit 1 (TAU1EN) of this register to 1.
The PER0 register can be set by a 1-bit or 8-bit memory manipulation instruction.
Reset signal generation clears this register to 00H.
Figure 6-6. Format of Peripheral Enable Register 0 (PER0)
Address: F00F0H
Symbol
PER0
After reset: 00H
<7>
R/W
<6>
IICA1EN
RTCEN
<5>
Note
ADCEN
TAU1EN
<4>
IICA0EN
<3>
SAU1EN
<2>
SAU0EN
<1>
TAU1EN
<0>
Note
TAU0EN
Control of timer array unit 1 input clock
Stops supply of input clock.
• SFR used by the timer array unit 1 cannot be written.
0
• The timer array unit 1 is in the reset status.
Supplies input clock.
• SFR used by the timer array unit 1 can be read/written.
1
TAU0EN
0
Control of timer array 0 unit input clock
Stops supply of input clock.
• SFR used by the timer array unit 0 cannot be written.
• The timer array unit 0 is in the reset status.
1
Supplies input clock.
• SFR used by the timer array unit 0 can be read/written.
Note 80 and 100-pin products only.
Cautions 1. When setting the timer array unit, be sure to set the TAUmEN bit to 1 first. If TAUmEN = 0,
writing to a control register of timer array unit is ignored, and all read values are default
values (except for the timer input select register 0 (TIS0), input switch control register
(ISC), noise filter enable registers 1, 2 (NFEN1, NFEN2), port mode registers 0, 1, 3, 6
(PM0, PM1, PM3, PM6), and port registers 0, 1, 3, 6 (P0, P1, P3, P6)).
2. Be sure to clear the following bits to 0.
30, 32, 36, 40, 44, 48, 52, 64-pin products: bits 1, 6
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(2) Timer clock select register m (TPSm)
The TPSm register is a 16-bit register that is used to select two types or four types of operation clocks (CKm0,
CKm1) that are commonly supplied to each channel from external prescaler. CKm1 is selected by using bits 7 to 4
of the TPSm register, and CKm0 is selected by using bits 3 to 0. In addition, for channel 1 and 3, CKm2 is selected
by using bits 9 and 8 of the TPSm register, and CKm3 is selected by using bits 13 and 12.
Rewriting of the TPSm register during timer operation is possible only in the following cases.
If the PRSm00 to PRSm03 bits can be rewritten (n = 0 to 3):
All channels for which CKm0 is selected as the operation clock (CKSmn1, CKSmn0 = 0, 0) are stopped (TEmn =
0).
If the PRSm10 to PRSm13 bits can be rewritten (n = 0 to 3):
All channels for which CKm1 is selected as the operation clock (CKSmn1, CKSmn0 = 0, 1) are stopped (TEmn =
0).
If the PRSm20 and PRSm21 bits can be rewritten (n = 1, 3):
All channels for which CKm2 is selected as the operation clock (CKSmn1, CKSmn0 = 1, 0) are stopped (TEmn =
0).
If the PRSm30 and PRSm31 bits can be rewritten (n = 1, 3):
All channels for which CKm3 is selected as the operation clock (CKSmn1, CKSmn0 = 1, 1) are stopped (TEmn =
0).
The TPSm register can be set by a 16-bit memory manipulation instruction.
Reset signal generation clears this register to 0000H.
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Figure 6-7. Format of Timer Clock Select register m (TPSm) (1/2)
Address: F01B6H, F01B7H (TPS0), F01F6H, F01F7H (TPS1)
After reset: 0000H
R/W
Symbol
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
TPSm
0
0
PRS
PRS
0
0
PRS
PRS
PRS
PRS
PRS
PRS
PRS
PRS
PRS
PRS
m31
m30
m21
m20
m13
m12
m11
m10
m03
m02
m01
m00
PRS
PRS
PRS
mk3
mk2
mk1
mk0
0
0
0
0
fCLK
2 MHz
5 MHz
10 MHz
20 MHz
32 MHz
0
0
0
1
fCLK/2
1 MHz
2.5 MHz
5 MHz
10 MHz
16 MHz
0
0
1
0
fCLK/2
2
500 kHz
1.25 MHz
2.5 MHz
5 MHz
8 MHz
fCLK/2
3
250 kHz
625 kHz
1.25 MHz
2.5 MHz
4 MHz
fCLK/2
4
125 kHz
312.5 kHz
625 kHz
1.25 MHz
2 MHz
fCLK/2
5
62.5 kHz
156.2 kHz
312.5 kHz
625 kHz
1 MHz
fCLK/2
6
31.25 kHz
78.1 kHz
156.2 kHz
312.5 kHz
500 kHz
fCLK/2
7
15.62 kHz
39.1 kHz
78.1 kHz
156.2 kHz
250 kHz
0
0
0
0
0
0
1
1
1
1
1
0
0
1
1
1
0
1
0
1
Selection of operation clock (CKmk)
fCLK = 2 MHz
(k = 0, 1)
fCLK = 5 MHz fCLK = 10 MHz fCLK = 20 MHz fCLK = 32 MHz
1
0
0
0
fCLK/2
8
7.81 kHz
19.5 kHz
39.1 kHz
78.1 kHz
125 kHz
1
0
0
1
fCLK/2
9
3.91 kHz
9.76 kHz
19.5 kHz
39.1 kHz
62.5 kHz
fCLK/2
10
1.95 kHz
4.88 kHz
9.76 kHz
19.5 kHz
31.25 kHz
fCLK/2
11
976 Hz
2.44 kHz
4.88 kHz
9.76 kHz
15.63 kHz
fCLK/2
12
488 Hz
1.22 kHz
2.44 kHz
4.88 kHz
7.81 kHz
fCLK/2
13
244 Hz
610 Hz
1.22 kHz
2.44 kHz
3.91 kHz
fCLK/2
14
122 Hz
305 Hz
610 Hz
1.22 kHz
1.95 kHz
fCLK/2
15
61 Hz
153 Hz
305 Hz
610 Hz
976 Hz
1
1
1
1
1
1
Note
Note
PRS
0
0
1
1
1
1
1
1
0
0
1
1
0
1
0
1
0
1
When changing the clock selected for fCLK (by changing the system clock control register (CKC)
value), stop timer array unit (TTm = 00FFH).
The timer array unit must also be stopped if the operating clock (fMCK) specified by using the
CKSmn0 and CKSmn1 bits or the valid edge of the signal input from the TImn pin is selected as the
count clock (fTCLK).
Caution
Be sure to clear bits 15, 14, 11, 10 to “0”.
Remarks 1. fCLK: CPU/peripheral hardware clock frequency
2. The above fCLK/2r is not a signal which is simply divided fCLK by 2r, but a signal which becomes high
level for one period of fCLK from its rising edge (r = 1 to 15). For details, see 6.5.1 Count clock
(fTCLK).
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Figure 6-7. Format of Timer Clock Select register m (TPSm) (2/2)
Address: F01B6H, F01B7H (TPS0), F01F6H, F01F7H (TPS1)
After reset: 0000H
R/W
Symbol
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
TPSm
0
0
PRS
PRS
0
0
PRS
PRS
PRS
PRS
PRS
PRS
PRS
PRS
PRS
PRS
m31
m30
m21
m20
m13
m12
m11
m10
m03
m02
m01
m00
PRS
PRS
m21
m20
0
0
fCLK/2
0
1
fCLK/2
2
1
0
fCLK/2
fCLK/2
1
1
PRS
PRS
m31
m30
0
Note
0
Selection of operation clock (CKm2)
Note
fCLK = 2 MHz
fCLK = 5 MHz fCLK = 10 MHz fCLK = 20 MHz fCLK = 32 MHz
1 MHz
2.5 MHz
5 MHz
10 MHz
16 MHz
500 kHz
1.25 MHz
2.5 MHz
5 MHz
8 MHz
4
125 kHz
312.5 kHz
625 kHz
1.25 MHz
2 MHz
6
31.25 kHZ
78.1 kHz
156.2 kHz
312.5 kHz
500 kHZ
Selection of operation clock (CKm3)
Note
fCLK = 2 MHz
fCLK = 5 MHz fCLK = 10 MHz fCLK = 20 MHz fCLK = 32 MHz
fCLK/2
8
7.81 kHz
19.5 kHz
39.1 kHz
78.1 kHz
125 kHz
0
1
fCLK/2
10
1.95 kHz
4.88 kHz
9.76 kHz
19.5 kHz
31.25 kHz
1
0
fCLK/2
12
488 Hz
1.22 kHz
2.44 kHz
4.88 kHz
7.81 kHz
1
1
fCLK/2
14
122 HZ
305 Hz
610 Hz
1.22 kHz
1.95 kHZ
When changing the clock selected for fCLK (by changing the system clock control register (CKC)
value), stop timer array unit (TTm = 00FFH).
The timer array unit must also be stopped if the operating clock (fMCK) specified by using the
CKSmn0, and CKSmn1 bits or the valid edge of the signal input from the TImn pin is selected as the
count clock (fTCLK).
Caution
Be sure to clear bits 15, 14, 11, 10 to “0”.
By using channels 1 and 3 in the 8-bit timer mode and specifying CKm2 or CKm3 as the operation clock, the
interval times shown in Table 6-4 can be achieved by using the interval timer function.
Table 6-4. Interval Times Available for Operation Clock CKSm2 or CKSm3
Interval time (fCLK = 32 MHz)
Clock
10 μs
CKm2
CKm3
<R>
100 μs
Note
1 ms
10 ms
√
−
−
−
fCLK/2
2
√
−
−
−
fCLK/2
4
√
√
−
−
fCLK/2
6
√
√
−
−
fCLK/2
8
−
√
√
−
fCLK/2
10
−
√
√
−
fCLK/2
12
−
−
√
√
fCLK/2
14
−
−
√
√
fCLK/2
Note The margin is within 5 %.
Remarks 1. fCLK: CPU/peripheral hardware clock frequency
2. For details of asignal of fCLK/2r selected with the TPSm register, see 6.5.1 Count clock (fTCLK).
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CHAPTER 6 TIMER ARRAY UNIT
(3) Timer mode register mn (TMRmn)
The TMRmn register sets an operation mode of channel n. This register is used to select the operation clock (fMCK),
select the count clock, select the master/slave, select the 16 or 8-bit timer (only for channels 1 and 3), specify the
start trigger and capture trigger, select the valid edge of the timer input, and specify the operation mode (interval,
capture, event counter, one-count, or capture and one-count).
Rewriting the TMRmn register is prohibited when the register is in operation (when TEmn = 1). However, bits 7 and
6 (CISmn1, CISmn0) can be rewritten even while the register is operating with some functions (when TEmn = 1)
(for details, see 6.7 Independent Channel Operation Function of Timer Array Unit and 6.8 Simultaneous
Channel Operation Function of Timer Array Unit.
The TMRmn register can be set by a 16-bit memory manipulation instruction.
Reset signal generation clears this register to 0000H.
Caution
The bits mounted depend on the channels in the bit 11 of TMRmn register.
TMRm2:
MASTERmn bit (n = 2)
TMRm1, TMRm3:
SPLITmn bit (n = 1, 3)
TMRm0:
Fixed to 0
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Figure 6-8. Format of Timer Mode Register mn (TMRmn) (1/4)
Address: F0190H, F0191H (TMR00) to F0196H, F0197H (TMR03),
After reset: 0000H
R/W
F01D0H, F01D1H (TMR10) to F01D6H, F01D7H (TMR13)
Symbol
15
14
13
12
11
10
9
8
TMRmn
CKS
CKS
0
CCS
MAST
STS
STS
STS
(n = 2)
mn1
mn0
mn
ERmn
mn2
mn1
mn0
Symbol
15
14
13
12
11
10
9
8
7
6
5
4
TMRmn
CKS
CKS
0
CCS
SPLIT
STS
STS
STS
CIS
CIS
0
0
(n = 1, 3)
mn1
mn0
mn
mn
mn2
mn1
mn0
mn1
mn0
Symbol
15
14
13
12
11
10
9
8
7
6
5
4
TMRmn
CKS
CKS
0
CCS
0
STS
STS
STS
CIS
CIS
0
0
(n = 0)
mn1
mn0
mn2
mn1
mn0
mn1
mn0
CKS
CKS
mn1
mn0
0
0
Operation clock CKm0 set by timer clock select register m (TPSm)
0
1
Operation clock CKm2 set by timer clock select register m (TPSm)
1
0
Operation clock CKm1 set by timer clock select register m (TPSm)
1
1
Operation clock CKm3 set by timer clock select register m (TPSm)
mn
7
6
5
4
CIS
CIS
0
0
mn1
mn0
3
2
1
0
MD
MD
MD
MD
mn3
mn2
mn1
mn0
3
2
1
0
MD
MD
MD
MD
mn3
mn2
mn1
mn0
3
2
1
0
MD
MD
MD
MD
mn3
mn2
mn1
mn0
Selection of operation clock (fMCK) of channel n
Operation clock (fMCK ) is used by the edge detector. A count clock (fTCLK) and a sampling clock are generated
depending on the setting of the CCSmn bit.
The operation clocks CKm2 and CKm3 can only be selected for channels 1 and 3.
CCS
Selection of count clock (fTCLK) of channel n
mn
0
Operation clock (fMCK) specified by the CKSmn0 and CKSmn1 bits
1
Valid edge of input signal input from the TImn pin
Count clock (fTCLK) is used for the timer/counter, output controller, and interrupt controller.
Cautions 1. Be sure to clear bits 13, 5, and 4 to “0”.
2. The timer array unit must be stopped (TTm = 00FFH) if the clock selected for fCLK is changed
(by changing the value of the system clock control register (CKC)), even if the operating clock
specified by using the CKSmn0 and CKSmn1 bits (fMCK) or the valid edge of the signal input
from the TImn pin is selected as the count clock (fTCLK).
Remark
m: Unit number (m = 0, 1), n: Channel number (n = 0 to 3)
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Figure 6-8. Format of Timer Mode Register mn (TMRmn) (2/4)
Address: F0190H, F0191H (TMR00) to F0196H, F0197H (TMR03),
After reset: 0000H
R/W
F01D0H, F01D1H (TMR10) to F01D6H, F01D7H (TMR13)
Symbol
15
14
13
12
11
10
9
8
TMRmn
CKS
CKS
0
CCS
MAST
STS
STS
STS
(n = 2)
mn1
mn0
mn
ERmn
mn2
mn1
mn0
Symbol
15
14
13
12
11
10
9
8
7
6
5
4
TMRmn
CKS
CKS
0
CCS
SPLIT
STS
STS
STS
CIS
CIS
0
0
(n = 1, 3)
mn1
mn0
mn
mn
mn2
mn1
mn0
mn1
mn0
Symbol
15
14
13
12
11
10
9
8
7
6
5
4
TMRmn
CKS
CKS
0
CCS
0
STS
STS
STS
CIS
CIS
0
0
(n = 0)
mn1
mn0
mn2
mn1
mn0
mn1
mn0
mn
7
6
5
4
CIS
CIS
0
0
mn1
mn0
3
2
1
0
MD
MD
MD
MD
mn3
mn2
mn1
mn0
3
2
1
0
MD
MD
MD
MD
mn3
mn2
mn1
mn0
3
2
1
0
MD
MD
MD
MD
mn3
mn2
mn1
mn0
(Bit 11 of TMRmn (n = 2))
MAS
Selection between using channel n independently or
TER
simultaneously with another channel(as a slave or master)
mn
Operates in independent channel operation function or as slave channel in simultaneous channel operation
0
function.
1
Operates as master channel in simultaneous channel operation function.
Only channel 2 can be set as a master channel (MASTERmn = 1).
Channel 0 is fixed to 0 (channel 0 always operates as master regardless of the bit setting, because it is the highest
channel).
Clear the MASTERmn bit to 0 for a channel that is used with the independent channel operation function.
(Bit 11 of TMRmn (n = 1, 3))
SPLI
Selection of 8 or 16-bit timer operation for channels 1 and 3
Tmn
0
Operates as 16-bit timer.
(Operates in independent channel operation function or as slave channel in simultaneous channel operation
function.)
1
Operates as 8-bit timer.
STS
STS
STS
mn2
mn1
mn0
0
0
0
Only software trigger start is valid (other trigger sources are unselected).
0
0
1
Valid edge of the TImn pin input is used as both the start trigger and capture trigger.
0
1
0
Both the edges of the TImn pin input are used as a start trigger and a capture trigger.
1
0
0
Interrupt signal of the master channel is used (when the channel is used as a slave channel
Setting of start trigger or capture trigger of channel n
with the simultaneous channel operation function).
Other than above
Remark
Setting prohibited
m: Unit number (m = 0, 1), n: Channel number (n = 0 to 3)
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Figure 6-8. Format of Timer Mode Register mn (TMRmn) (3/4)
Address: F0190H, F0191H (TMR00) to F0196H, F0197H (TMR03),
After reset: 0000H
R/W
F01D0H, F01D1H (TMR10) to F01D6H, F01D7H (TMR13)
Symbol
15
14
13
12
11
10
9
8
TMRmn
CKS
CKS
0
CCS
MAST
STS
STS
STS
(n = 2)
mn1
mn0
mn
ERmn
mn2
mn1
mn0
Symbol
15
14
13
12
11
10
9
8
7
6
5
4
TMRmn
CKS
CKS
0
CCS
SPLIT
STS
STS
STS
CIS
CIS
0
0
(n = 1, 3)
mn1
mn0
mn
mn
mn2
mn1
mn0
mn1
mn0
Symbol
15
14
13
12
11
10
9
8
7
6
5
4
TMRmn
CKS
CKS
0
CCS
0
STS
STS
STS
CIS
CIS
0
0
(n = 0)
mn1
mn0
mn2
mn1
mn0
mn1
mn0
mn
7
6
5
4
CIS
CIS
0
0
mn1
mn0
CIS
CIS
mn1
mn0
0
0
Falling edge
0
1
Rising edge
1
0
Both edges (when low-level width is measured)
3
2
1
0
MD
MD
MD
MD
mn3
mn2
mn1
mn0
3
2
1
0
MD
MD
MD
MD
mn3
mn2
mn1
mn0
3
2
1
0
MD
MD
MD
MD
mn3
mn2
mn1
mn0
Selection of TImn pin input valid edge
Start trigger: Falling edge, Capture trigger: Rising edge
1
1
Both edges (when high-level width is measured)
Start trigger: Rising edge, Capture trigger: Falling edge
If both the edges are specified when the value of the STSmn2 to STSmn0 bits is other than 010B, set the CISmn1
to CISmn0 bits to 10B.
MD
MD
MD
MD
mn3
mn2
mn1
mn0
0
0
0
1/0
Operation mode of channel n
Corresponding function
Count operation of
TCR
Interval timer mode
Interval timer / Square wave
Counting down
output / Divider function / PWM
output (master)
0
1
0
1/0
Capture mode
Input pulse interval
Counting up
measurement
0
1
1
0
1
0
0
1/0
Event counter mode
External event counter
Counting down
One-count mode
Delay counter / One-shot pulse
Counting down
output / PWM output (slave)
1
1
0
0
Capture & one-count mode
Measurement of high-/low-level
Counting up
width of input signal
Other than above
Setting prohibited
The operation of the MDmn0 bit varies depending on each operation mode (see table below).
Remark
m: Unit number (m = 0, 1), n: Channel number (n = 0 to 3)
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Figure 6-8. Format of Timer Mode Register mn (TMRmn) (4/4)
Address: F0190H, F0191H (TMR00) to F0196H, F0197H (TMR03),
After reset: 0000H
R/W
F01D0H, F01D1H (TMR10) to F01D6H, F01D7H (TMR13)
Symbol
15
14
13
12
11
10
9
8
TMRmn
CKS
CKS
0
CCS
MAST
STS
STS
STS
(n = 2)
mn1
mn0
mn
ERmn
mn2
mn1
mn0
Symbol
15
14
13
12
11
10
9
8
7
6
5
4
TMRmn
CKS
CKS
0
CCS
SPLIT
STS
STS
STS
CIS
CIS
0
0
(n = 1, 3)
mn1
mn0
mn
mn
mn2
mn1
mn0
mn1
mn0
Symbol
15
14
13
12
11
10
9
8
7
6
5
4
TMRmn
CKS
CKS
0
CCS
0
STS
STS
STS
CIS
CIS
0
0
(n = 0)
mn1
mn0
mn2
mn1
mn0
mn1
mn0
mn
Operation mode
MD
(Value set by the MDmn3 to MDmn1 bits
mn0
7
6
5
4
CIS
CIS
0
0
mn1
mn0
3
2
1
0
MD
MD
MD
MD
mn3
mn2
mn1
mn0
3
2
1
0
MD
MD
MD
MD
mn3
mn2
mn1
mn0
3
2
1
0
MD
MD
MD
MD
mn3
mn2
mn1
mn0
Setting of starting counting and interrupt
(see table above))
• Interval timer mode
0
(0, 0, 0)
Timer interrupt is not generated when counting is started
(timer output does not change, either).
• Capture mode
1
(0, 1, 0)
Timer interrupt is generated when counting is started
(timer output also changes).
• Event counter mode
0
(0, 1, 1)
Timer interrupt is not generated when counting is started
(timer output does not change, either).
• One-count mode
Note 1
0
Start trigger is invalid during counting operation.
At that time, interrupt is not generated, either.
(1, 0, 0)
1
Note 2
Start trigger is valid during counting operation
.
At that time, interrupt is also generated.
• Capture & one-count mode
(1, 1, 0)
0
Timer interrupt is not generated when counting is started
(timer output does not change, either).
Start trigger is invalid during counting operation.
At that time interrupt is not generated, either.
Other than above
Setting prohibited
Notes 1. In one-count mode, interrupt output (INTTMmn) when starting a count operation and TOmn output are not
controlled.
2. If the start trigger (TSmn = 1) is issued during operation, the counter is initialaized, an interrupt is
generated, and recounting is started.
Remark
m: Unit number (m = 0, 1), n: Channel number (n = 0 to 3)
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(4) Timer status register mn (TSRmn)
The TSRmn register indicates the overflow status of the counter of channel n.
The TSRmn register is valid only in the capture mode (MDmn3 to MDmn1 = 010B) and capture & one-count mode
(MDmn3 to MDmn1 = 110B). See Table 6-5 for the operation of the OVF bit in each operation mode and set/clear
conditions.
The TSRmn register can be read by a 16-bit memory manipulation instruction.
The lower 8 bits of the TSRmn register can be set with an 8-bit memory manipulation instruction with TSRmnL.
Reset signal generation clears this register to 0000H.
Figure 6-9. Format of Timer Status Register mn (TSRmn)
Address: F01A0H, F01A1H (TSR00) to F01A6H, F01A7H (TSR03),
After reset: 0000H
R
F01E0H, F01E1H (TSR10) to F01E6H, F01E7H (TSR13)
Symbol
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
TSRmn
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
OVF
OVF
Counter overflow status of channel n
0
Overflow does not occur.
1
Overflow occurs.
When OVF = 1, this flag is cleared (OVF = 0) when the next value is captured without overflow.
Remark
m: Unit number (m = 0, 1), n: Channel number (n = 0 to 3)
Table 6-5. OVF Bit Operation and Set/Clear Conditions in Each Operation Mode
Timer operation mode
OVF bit
Set/clear conditions
• Capture mode
clear
When no overflow has occurred upon capturing
• Capture & one-count mode
set
When an overflow has occurred upon capturing
• Interval timer mode
clear
• Event counter mode
• One-count mode
Remark
set
−
(Use prohibited)
The OVF bit does not change immediately after the counter has overflowed, but changes upon the
subsequent capture.
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(5) Timer channel enable status register m (TEm)
The TEm register is used to enable or stop the timer operation of each channel.
Each bit of the TEm register corresponds to each bit of the timer channel start register m (TSm) and the timer
channel stop register m (TTm). When a bit of the TSm register is set to 1, the corresponding bit of this register is
set to 1. When a bit of the TTm register is set to 1, the corresponding bit of this register is cleared to 0.
The TEm register can be read by a 16-bit memory manipulation instruction.
The lower 8 bits of the TEm register can be set with a 1-bit or 8-bit memory manipulation instruction with TEmL.
Reset signal generation clears this register to 0000H.
Figure 6-10. Format of Timer Channel Enable Status register m (TEm)
Address: F01B0H, F01B1H (TE0), F01F0H, F01F1H (TE1)
After reset: 0000H
R
Symbol
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
TEm
0
0
0
0
TEHm
0
TEHm
0
0
0
0
0
TEm
TEm
TEm
TEm
3
2
1
0
3
1
TEH
Indication of whether operation of the higher 8-bit timer is enabled or stopped when channel 3 is in the 8-bit
m3
timer mode
0
Operation is stopped.
1
Operation is enabled.
TEH
Indication of whether operation of the higher 8-bit timer is enabled or stopped when channel 1 is in the 8-bit
m1
timer mode
0
Operation is stopped.
1
Operation is enabled.
TEmn
Indication of operation enable/stop status of channel n
0
Operation is stopped.
1
Operation is enabled.
This bit displays whether operation of the lower 8-bit timer for TEm1 and TEm3 is enabled or stopped when channel
1 or 3 is in the 8-bit timer mode.
Remark
m: Unit number (m = 0, 1), n: Channel number (n = 0 to 3)
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(6) Timer channel start register m (TSm)
The TSm register is a trigger register that is used to initialize timer count register mn (TCRmn) and start the
counting operation of each channel.
When a bit of this register is set to 1, the corresponding bit of timer channel enable status register m (TEm) is set to
1. The TSmn, TSHm1, TSHm3 bits are immediately cleared when operation is enabled (TEmn, TEHm1, TEHm3 =
1), because they are trigger bits.
The TSm register can be set by a 16-bit memory manipulation instruction.
The lower 8 bits of the TSm register can be set with a 1-bit or 8-bit memory manipulation instruction with TSmL.
Reset signal generation clears this register to 0000H.
Figure 6-11. Format of Timer Channel Start register m (TSm)
Address: F01B2H, F01B3H (TS0), F01F2H, F01F3H (TS1)
After reset: 0000H
R/W
Symbol
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
TSm
0
0
0
0
TSHm
0
TSHm
0
0
0
0
0
TSm
TSm
TSm
TSm
3
2
1
0
3
1
TSH Trigger to enable operation (start operation) of the higher 8-bit timer when channel 3 is in the 8-bit timer mode
m3
0
No trigger operation
1
The TEHm3 bit is set to 1 and the count operation becomes enabled.
The TCRm3 register count operation start in the interval timer mode in the count operation enabled state
(see Table 6-6 in 6.5.2 Start timing of counter).
TSH Trigger to enable operation (start operation) of the higher 8-bit timer when channel 1 is in the 8-bit timer mode
m1
0
No trigger operation
1
The TEHm1 bit is set to 1 and the count operation becomes enabled.
The TCRm1 register count operation start in the interval timer mode in the count operation enabled state
(see Table 6-6 in 6.5.2 Start timing of counter).
TSm
Operation enable (start) trigger of channel n
n
0
No trigger operation
1
The TEmn bit is set to 1 and the count operation becomes enabled.
The TCRmn register count operation start in the count operation enabled state varies depending on each
operation mode (see Table 6-6 in 6.5.2 Start timing of counter).
This bit is the trigger to enable operation (start operation) of the lower 8-bit timer for TSm1 and TSm3 when
channel 1 or 3 is in the 8-bit timer mode.
Cautions 1. Be sure to clear bits 15 to 12, 10, 8 to 4 to “0”
2. When switching from a function that does not use TImn pin input to one that does, the
following wait period is required from when timer mode register mn (TMRmn) is set until the
TSmn (TSHm1, TSHm3) bit is set to 1.
When the TImn pin noise filter is enabled (TNFENmn = 1): Four cycles of the operation clock
(fMCK)
When the TImn pin noise filter is disabled (TNFENmn = 0): Two cycles of the operation clock
(fMCK)
Remarks 1. When the TSm register is read, 0 is always read.
2. m: Unit number (m = 0, 1), n: Channel number (n = 0 to 3)
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(7) Timer channel stop register m (TTm)
The TTm register is a trigger register that is used to stop the counting operation of each channel.
When a bit of this register is set to 1, the corresponding bit of timer channel enable status register m (TEm) is
cleared to 0. The TTmn, TTHm1, TTHm3 bits are immediately cleared when operation is stopped (TEmn, TTHm1,
TTHm3 = 0), because they are trigger bits.
The TTm register can be set by a 16-bit memory manipulation instruction.
The lower 8 bits of the TTm register can be set with a 1-bit or 8-bit memory manipulation instruction with TTmL.
Reset signal generation clears this register to 0000H.
Figure 6-12. Format of Timer Channel Stop register m (TTm)
Address: F01B4H, F01B5H (TT0), F01F4H, F01F5H (TT1)
After reset: 0000H
R/W
Symbol
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
TTm
0
0
0
0
TTHm
0
TTHm
0
0
0
0
0
TTm
TTm
TTm
TTm
3
2
1
0
3
TTH
1
Trigger to stop operation of the higher 8-bit timer when channel 3 is in the 8-bit timer mode
m3
0
No trigger operation
1
Operation is stopped (stop trigger is generated).
TTH
Trigger to stop operation of the higher 8-bit timer when channel 1 is in the 8-bit timer mode
m1
0
No trigger operation
1
Operation is stopped (stop trigger is generated).
TTm
Operation stop trigger of channel n
n
0
No trigger operation
1
Operation is stopped (stop trigger is generated).
This bit is the trigger to stop operation of the lower 8-bit timer for TTm1 and TTm3 when channel 1 or 3 is in
the 8-bit timer mode.
Caution
Be sure to clear bits 15 to 12, 10, 8 to 4 of the TTm register to “0”.
Remarks 1. When the TTm register is read, 0 is always read.
2. m: Unit number (m = 0, 1),n: Channel number (n = 0 to 3)
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(8) Timer input select register 0 (TIS0)
The TIS0 register is used to select the channel 0 and 1 timer input.
The TIS0 register can be set by an 8-bit memory manipulation instruction.
Reset signal generation clears this register to 00H.
Figure 6-13. Format of Timer Input Select register 0 (TIS0)
Address: F0074H
After reset: 00H
R/W
Symbol
7
6
5
4
3
2
1
0
TIS0
0
0
0
TIS04
0
TIS02
TIS01
TIS00
TIS04
Selection of timer input used with channel 0
0
Input signal of timer input pin (TI00)
1
Event input signal from ELC
TIS02
TIS01
TIS00
0
0
0
Input signal of timer input pin (TI01)
0
0
1
Event input signal from ELC
0
1
0
Input signal of timer input pin (TI01)
0
1
1
1
0
0
Low-speed on-chip oscillator clock (fIL)
1
0
1
Subsystem clock (fSUB)
Other than above
<R>
Caution
Selection of timer input used with channel 1
Setting prohibited
When selecting an event input signal from the ELC using timer input select register 0 (TIS0),
select fCLK using timer clock select register 0 (TPS0).
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(9) Timer output enable register m (TOEm)
The TOEm register is used to enable or disable timer output of each channel.
Channel n for which timer output has been enabled becomes unable to rewrite the value of the TOmn bit of timer
output register m (TOm) described later by software, and the value reflecting the setting of the timer output function
through the count operation is output from the timer output pin (TOmn).
The TOEm register can be set by a 16-bit memory manipulation instruction.
The lower 8 bits of the TOEm register can be set with a 1-bit or 8-bit memory manipulation instruction with TOEmL.
Reset signal generation clears this register to 0000H.
Figure 6-14. Format of Timer Output Enable register m (TOEm)
Address: F01BAH, F01BBH (TOE0), F01FAH, F01FBH (TOE1)
<R>
After reset: 0000H
R/W
Symbol
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
TOEm
0
0
0
0
0
0
0
0
0
0
0
0
TOE
TOE
TOE
TOE
m3
m2
m1
m0
TOE
Timer output enable/disable of channel n
mn
0
Timer output is disabled.
Timer operation is not applied to the TOmn bit and the output is fixed.
Writing to the TOmn bit is enabled.
1
Timer output is enabled.
Timer operation is applied to the TOmn bit and an output waveform is generated.
Writing to the TOmn bit is ignored.
Caution
Be sure to clear bits 15 to 4 to “0”.
Remark
m: Unit number (m = 0, 1), n: Channel number (n = 0 to 3)
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(10) Timer output register m (TOm)
The TOm register is a buffer register of timer output of each channel.
The value of each bit in this register is output from the timer output pin (TOmn) of each channel.
The TOmn bit oh this register can be rewritten by software only when timer output is disabled (TOEmn = 0). When
timer output is enabled (TOEmn = 1), rewriting this register by software is ignored, and the value is changed only
by the timer operation.
To use the P00/TI00, P01/TO00, P16/TI01/TO01, P17/TI02/TO02, P31/TI03/TO03, P64/TI10/TO10-P67/TI13/TO13
pins as a port function pin, set the corresponding TOmn bit to “0”.
The TOm register can be set by a 16-bit memory manipulation instruction.
The lower 8 bits of the TOm register can be set with an 8-bit memory manipulation instruction with TOmL.
Reset signal generation clears this register to 0000H.
Figure 6-15. Format of Timer Output register m (TOm)
Address: F01B8H, F01B9H (TO0), F01F8H, F01F9H (TO1)
After reset: 0000H
R/W
Symbol
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
TOm
0
0
0
0
0
0
0
0
0
0
0
0
TOm
TOm
TOm
TOm
3
2
1
0
TOm
Timer output of channel n
n
0
Timer output value is “0”.
1
Timer output value is “1”.
Caution
Be sure to clear bits 15 to 4 to “0”.
Remark
m: Unit number (m = 0, 1), n: Channel number (n = 0 to 3)
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(11) Timer output level register m (TOLm)
The TOLm register is a register that controls the timer output level of each channel.
The setting of the inverted output of channel n by this register is reflected at the timing of set or reset of the timer
output signal while the timer output is enabled (TOEmn = 1) in the Slave channel output mode (TOMmn = 1). In
the master channel output mode (TOMmn = 0), this register setting is invalid.
The TOLm register can be set by a 16-bit memory manipulation instruction.
The lower 8 bits of the TOLm register can be set with an 8-bit memory manipulation instruction with TOLmL.
Reset signal generation clears this register to 0000H.
Figure 6-16. Format of Timer Output Level register m (TOLm)
Address: F01BCH, F01BDH (TOL0), F01FCH, F01FDH (TOL1)
After reset: 0000H
R/W
Symbol
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
TOLm
0
0
0
0
0
0
0
0
0
0
0
0
TOL
TOL
TOL
0
m3
m2
m1
TOL
Control of timer output level of channel n
mn
0
Positive logic output (active-high)
1
Negative logic output (active-low)
Caution
Be sure to clear bits 15 to 4, and 0 to “0”.
Remarks 1.
If the value of this register is rewritten during timer operation, the timer output logic is inverted when
the timer output signal changes next, instead of immediately after the register value is rewritten.
2.
m: Unit number (m = 0, 1), n: Channel number (n = 0 to 3)
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(12) Timer output mode register m (TOMm)
The TOMm register is used to control the timer output mode of each channel.
When a channel is used for the independent channel operation function, set the corresponding bit of the channel
to be used to 0.
When a channel is used for the simultaneous channel operation function (PWM output, one-shot pulse output, or
multiple PWM output), set the corresponding bit of the master channel to 0 and the corresponding bit of the slave
channel to 1.
The setting of each channel n by this register is reflected at the timing when the timer output signal is set or reset
while the timer output is enabled (TOEmn = 1).
The TOMm register can be set by a 16-bit memory manipulation instruction.
The lower 8 bits of the TOMm register can be set with an 8-bit memory manipulation instruction with TOMmL.
Reset signal generation clears this register to 0000H.
Figure 6-17. Format of Timer Output Mode register m (TOMm)
Address: F01BEH, F01BFH (TOM0), F01FEH, F01FFH (TOM1)
After reset: 0000H
R/W
Symbol
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
TOMm
0
0
0
0
0
0
0
0
0
0
0
0
TOM
TOM
TOM
0
m3
m2
m1
TOM
Control of timer output mode of channel n
mn
0
Master channel output mode (to produce toggle output by timer interrupt request signal (INTTMmn))
1
Slave channel output mode (output is set by the timer interrupt request signal (INTTMmn) of the master
channel, and reset by the timer interrupt request signal (INTTM0p) of the slave channel)
Caution
Be sure to clear bits 15 to 4, and 0 to “0”.
Remark
m: Unit number (m = 0, 1)
n: Channel number
n = 0 to 3 (n = 0, 2 for master channel)
p: Slave channel number
n = 0, p = 1, 2, 3
n = 2, p = 3
(For details of the relation between the master channel and slave channel, refer to 6.4.1 Basic rules of
simultaneous channel operation function.)
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(13) Input switch control register (ISC)
The ISC1 and ISC0 bits of the ISC register are used to implement LIN-bus communication operation by using
channel 3 in association with the serial array unit. When the ISC1 bit is set to 1, the input signal of the serial data
input pin (RxD0) is selected as a timer input signal.
For details about setting the SSIE00 bit, see 17.3 (15) Input switch control register (ISC).
The ISC register can be set by a 1-bit or 8-bit memory manipulation instruction.
Figure 6-18. Format of Input Switch Control Register (ISC)
Address: F0073H
After reset: 00H
R/W
Symbol
7
6
5
4
3
2
1
0
ISC
SSIE00
0
0
0
0
0
ISC1
ISC0
SSIE00
Setting SSI00 pin input when CSI00 communication and slave mode are applied
0
SSI00 pin input is invalid.
1
SSI00 pin input is valid.
ISC1
0
1
Switching channel 3 input of timer array unit 0
Uses the input signal of the TI03 pin as a timer input (normal operation).
Input signal of the RXD0 pin is used as timer input (detects the wakeup signal and measures the low
width of the sync break field and the pulse width of the sync field).
ISC0
Caution
Switching external interrupt (INTP0) input
0
Uses the input signal of the INTP0 pin as an external interrupt (normal operation).
1
Uses the input signal of the RXD0 pin as an external interrupt (wakeup signal detection).
Be sure to clear bits 6 to 2 to “0”.
Remark When the LIN-bus communication function is used, select the input signal of the RxD0 pin by setting
ISC1 to 1.
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(14) Noise filter enable registers 1, 2 (NFEN1, NFEN2)
The NFEN1, NFEN2 registers is used to set whether the noise filter can be used for the timer input signal to each
channel.
Enable the noise filter by setting the corresponding bits to 1 on the pins in need of noise removal.
When the noise filter is ON, match detection and synchronization of the 2 clocks is performed with the
CPU/peripheral hardware clock (fMCK). When the noise filter is OFF, only synchronization is performed with the
CPU/peripheral hardware clock (fMCK) Note.
The NFEN1, NFEN2 registers can be set by a 1-bit or 8-bit memory manipulation instruction.
Reset signal generation clears this register to 00H.
Note For details, see 6.5.1 (2) When valid edge of input signal input from the TImn pin is selected (CCSmn
= 1) and 6.5.2 Start timing of counter.
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Figure 6-19. Format of Noise Filter Enable Registers 1, 2 (NFEN1, NFEN2) (1/2)
Address: F0071H
After reset: 00H
R/W
Symbol
7
6
5
4
3
2
1
0
NFEN1
0
0
0
0
TNFEN03
TNFEN02
TNFEN01
TNFEN00
Address: F0072H
After reset: 00H
R/W
Symbol
7
6
5
4
3
2
1
0
NFEN2
0
0
0
0
TNFEN13
TNFEN12
TNFEN11
TNFEN10
TNFEN03
Enable/disable using noise filter of TI03/TO03/P31 pin or RxD0/P50 pin input signal
0
Noise filter OFF
1
Noise filter ON
TNFEN02
Note
Enable/disable using noise filter of TI02/TO02/P17 pin input signal
0
Noise filter OFF
1
Noise filter ON
TNFEN01
Enable/disable using noise filter of TI01/P01/P16 pin input signal
0
Noise filter OFF
1
Noise filter ON
TNFEN00
Enable/disable using noise filter of TI00/P00 pin input signal
0
Noise filter OFF
1
Noise filter ON
Note The applicable pin can be switched by setting the ISC1 bit of the ISC register.
ISC1 = 0: Whether or not to use the noise filter of the TI03 pin can be selected.
ISC1 = 1: Whether or not to use the noise filter of the RxD0 pin can be selected.
Remark
The presence or absence of timer I/O pins of channel 0 to 3 depends on the product. See Table 6-2
Timer I/O Pins provided in Each Product for details.
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Figure 6-19. Format of Noise Filter Enable Registers 1, 2 (NFEN1, NFEN2) (2/2)
Address: F0071H
After reset: 00H
R/W
Symbol
7
6
5
4
3
2
1
0
NFEN1
0
0
0
0
TNFEN03
TNFEN02
TNFEN01
TNFEN00
Address: F0072H
After reset: 00H
R/W
Symbol
7
6
5
4
3
2
1
0
NFEN2
0
0
0
0
TNFEN13
TNFEN12
TNFEN11
TNFEN10
TNFEN13
Enable/disable using noise filter of TI13/TO13/P67 pin input signal
0
Noise filter OFF
1
Noise filter ON
TNFEN12
Enable/disable using noise filter of TI12/TO12/P66 pin input signal
0
Noise filter OFF
1
Noise filter ON
TNFEN11
Enable/disable using noise filter of TI11/P11/P65 pin input signal
0
Noise filter OFF
1
Noise filter ON
TNFEN10
Remark
Enable/disable using noise filter of TI00/P64 pin input signal
0
Noise filter OFF
1
Noise filter ON
The presence or absence of timer I/O pins of channel 0 to 3 depends on the product. See Table 6-2
Timer I/O Pins provided in Each Product for details.
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(15) Port mode registers 0, 1, 3, 6 (PM0, PM1, PM3, PM6)
These registers set input/output of ports 0, 1, 3, 6 in 1-bit units.
The presence or absence of timer I/O pins depends on the product. When using the timer array unit, set the
following port mode registers according to the product used.
30, 32, 36, 40, 44, 48, 52, and 64-pin products: PM0, PM1, PM3
80 and 100-pin products: PM0, PM1, PM3, PM6
When using the ports (such as P01/TO00 and P17/TO02/TI02) to be shared with the timer output pin for timer
output, set the port mode register (PMxx) bit and port register (Pxx) bit corresponding to each port to 0.
Example: When using P17/TO02/TI02 for timer output
Set the PM17 bit of port mode register 1 to 0.
Set the P17 bit of port register 1 to 0.
When using the ports (such as P00/TI00 and P17/TO02/TI02) to be shared with the timer output pin for timer input,
set the port mode register (PMxx) bit corresponding to each port to 1. At this time, the port register (Pxx) bit may
be 0 or 1.
Example: When using P17/TO02/TI02 for timer input
Set the PM17 bit of port mode register 1 to 1.
P17 bit of port register may be 0 or 1.
The PM0, PM1, PM3, PM6 registers can be set by a 1-bit or 8-bit memory manipulation instruction.
Reset signal generation sets these registers to FFH.
<R>
Remark
In the 30-pin and 32-pin products, TI00 (P00) and TO00 (P01) pins alternate analog input pins. When
using the timer I/O function, the corresponding bit of the PMC0x register for switching digital I/O or
analog input is sure to set to “0”.
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Figure 6-20. Format of Port Mode Registers 0, 1, 3, 6 (PM0, PM1, PM3, PM6) (100-pin products)
Address: FFF20H
After reset: FFH
R/W
Symbol
7
6
5
4
3
2
1
0
PM0
1
PM06
PM05
PM04
PM03
PM02
PM01
PM00
Address: FFF21H
After reset: FFH
R/W
Symbol
7
6
5
4
3
2
1
0
PM1
PM17
PM16
PM15
PM14
PM13
PM12
PM11
PM10
Address: FFF23H
After reset: FFH
R/W
Symbol
7
6
5
4
3
2
1
0
PM3
1
1
1
1
1
1
PM31
PM30
Address: FFF26H
After reset: FFH
R/W
Symbol
7
6
5
4
3
2
1
0
PM6
PM67
PM66
PM65
PM64
PM63
PM62
PM61
PM60
PMmn
Remark
Pmn pin I/O mode selection (m = 0, 1, 3, 6; n = 0 to 7)
0
Output mode (output buffer on)
1
Input mode (output buffer off)
The figure shown above presents the format of port mode registers 0, 1, 3, and 6 of the 100-pin products. The
format of the port mode register of other products, see Table 4-5. or Table 4-6. PMxx, Pxx, PUxx, PIMxx,
POMxx, PMCxx registers and the bits mounted on each product.
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6.4 Basic Rules of Timer Array Unit
6.4.1 Basic rules of simultaneous channel operation function
When simultaneously using multiple channels, namely, a combination of a master channel (a reference timer mainly
counting the cycle) and slave channels (timers operating according to the master channel), the following rules apply.
(1) Only an even channel (channel 0, 2) can be set as a master channel.
(2) Any channel, except channel 0, can be set as a slave channel.
(3) The slave channel must be lower than the master channel.
Example: If channel 0 is set as a master channel, channel 1 or those that follow (channels 1, 2, 3) can be set as a
slave channel.
(4) Two or more slave channels can be set for one master channel.
(5) When two or more master channels are to be used, slave channels with a master channel between them may not
be set.
Example: If channels 0 and 2 are set as master channels, channels 1 can be set as the slave channel of master
channel 0. Channel 3 cannot be set as the slave channel of master channel 0.
(6) The operating clock for a slave channel in combination with a master channel must be the same as that of the
master channel. The CKSmn0, CKSmn1 bits (bit 15, 14 of timer mode register mn (TMRmn)) of the slave channel
that operates in combination with the master channel must be the same value as that of the master channel.
(7) A master channel can transmit INTTMmn (interrupt), start software trigger, and count clock to the lower channels.
(8) A slave channel can use INTTMmn (interrupt), a start software trigger, or the count clock of the master channel as
a source clock, but cannot transmit its own INTTMmn (interrupt), start software trigger, or count clock to channels
with lower channel numbers.
(9) A master channel cannot use INTTMmn (interrupt), a start software trigger, or the count clock from the other higher
master channel as a source clock.
(10) To simultaneously start channels that operate in combination, the channel start trigger bit (TSmn) of the channels
in combination must be set at the same time.
<R>
(11) During the counting operation, a TSmn bit of a master channel or TSmn bits of all channels which are operating
simultaneously can be set. It cannot be applied to TSmn bits of slave channels alone.
(12) To stop the channels in combination simultaneously, the channel stop trigger bit (TTmn) of the channels in
combination must be set at the same time.
<R>
(13) CKm2/CKm3 cannot be selected while channels are operating simultaneously, because the operating clocks of
master channels and slave channels have to be synchronized.
<R>
(14) Timer mode register m0 (TMRm0) has no master bit (it is fixed as “0”). However, as channel 0 is the highest
channel, it can be used as a master channel during simultaneous operation.
The rules of the simultaneous channel operation function are applied in a channel group (a master channel and slave
channels forming one simultaneous channel operation function).
If two or more channel groups that do not operate in combination are specified, the basic rules of the simultaneous
channel operation function in 6.4.1 Basic rules of simultaneous channel operation function do not apply to the
channel groups.
Remark
m: Unit number (m = 0, 1), n: Channel number (n = 0 to 3)
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Example1
TAU0
CK00
Channel 0: Master
Channel group 1
(Simultaneous channel operation
function)
Channel 1: Slave
Channel group 2
(Simultaneous channel operation
function)
CK01
Channel 2: Master
Channel 3: Slave
* The operating clock of channel group 1 may
be different from that of channel group 2.
Example2
TAU0
CK00
CK01
Channel 0: Master
Channel group 1
(Simultaneous channel operation
function)
Channel 1: Independent channel
operation function
Channel 2: Slave
CK00
Channel 3: Independent channel
operation function
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channel operation function may be between
a master and a slave of channel group 1.
Furthermore, the operating clock may be set
separately.
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6.4.2 Basic rules of 8-bit timer operation function (channels 1 and 3 only)
The 8-bit timer operation function makes it possible to use a 16-bit timer channel in a configuration consisting of two 8bit timer channels.
This function can only be used for channels 1 and 3, and there are several rules for using it.
The basic rules for this function are as follows:
(1) The 8-bit timer operation function applies only to channels 1 and 3.
(2) When using 8-bit timers, set the SPLIT bit of timer mode register mn (TMRmn) to 1.
(3) The higher 8 bits can be operated as the interval timer function.
(4) At the start of operation, the higher 8 bits output INTTMm1H/INTTMm3H (an interrupt) (which is the same
operation performed when MDmn0 is set to 1).
(5) The operation clock of the higher 8 bits is selected according to the CKSmn1 and CKSmn0 bits of the lower-bit
TMRmn register.
(6) For the higher 8 bits, the TSHm1/TSHm3 bit is manipulated to start channel operation and the TTHm1/TTHm3 bit
is manipulated to stop channel operation. The channel status can be checked using the TEHm1/TEHm3 bit.
(7) The lower 8 bits operate according to the TMRmn register settings.
The following three functions support
operation of the lower 8 bits:
• Interval timer function
• External event counter function
• Delay count function
(8) For the lower 8 bits, the TSm1/TSm3 bit is manipulated to start channel operation and the TTm1/TTm3 bit is
manipulated to stop channel operation. The channel status can be checked using the TEm1/TEm3 bit.
(9) During 16-bit operation, manipulating the TSHm1, TSHm3, TTHm1, and TTHm3 bits is invalid. The TSm1, TSm3,
TTm1, and TTm3 bits are manipulated to operate channels 1 and 3. The TEHm3 and TEHm1 bits are not changed.
(10) For the 8-bit timer function, the simultaneous operation functions (one-shot pulse, PWM, and multiple PWM)
cannot be used.
Remark
m: Unit number (m = 0, 1), n: Channel number (n = 1, 3)
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6.5 Operation Timing of Counter
6.5.1 Count clock (fTCLK)
The count clock (fTCLK) of the timer array unit can be selected between following by CCSmn bit of timer mode register
mn (TMRmn).
• Operation clock (fMCK) specified by the CKSmn0 and CKSmn1 bits
• Valid edge of input signal input from the TImn pin
Because the timer array unit is designed to operate in synchronization with fCLK, the timings of the count clock (fTCLK) are
shown below.
(1) When operation clock (fMCK) specified by the CKSmn0 and CKSmn1 bits is selected (CCSmn = 0)
The count clock (fTCLK) is between fCLK to fCLK /215 by setting of timer clock select register m (TPSm). When a
divided fCLK is selected, however, the count clock is not a signal which is simply divided fCLK by 2r, but a signal which
becomes high level for one period of fCLK from its rising edge (r = 1 to 15).
Counting of timer count register mn (TCRmn) delayed by one period of fCLK from rising edge of the count clock,
because of synchronization with fCLK. But, this is described as “counting at rising edge of the count clock”, as a
matter of convenience.
Figure 6-21. Timing of fCLK and count clock (fTCLK) (When CCSmn = 0)
fCLK
fCLK/2
fCLK/4
fTCLK
( = fMCK
= CKmn)
fCLK/8
fCLK/16
Remarks 1.
: Rising edge of the count clock
: Synchronization, increment/decrement of counter
2. fCLK: CPU/peripheral hardware clock
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(2) When valid edge of input signal via the TImn pin is selected (CCSmn = 1)
The count clock (fTCLK) becomes the signal that detects valid edge of input signal via the TImn pin and synchronizes
next rising fMCK. The count clock (fTCLK) is delayed for 1 to 2 period of fMCK from the input signal via the TImn pin
(when a noise filter is used, the delay becomes 3 to 4 clock).
Counting of timer count register mn (TCRmn) delayed by one period of fCLK from rising edge of the count clock,
because of synchronization with fCLK. But, this is described as “counting at valid edge of input signal via the TImn
pin”, as a matter of convenience.
Figure 6-22. Timing of count clock (fTCLK) (When CCSmn = 1, noise filter unused)
fCLK
fMCK
TSmn(Write)
<1>
TEmn
TImn input
<2>
Sampling wave
Edge detection
<3>
Edge detection
Rising edge
detection signal (fTCLK)
<1> Setting TSmn bit to 1 enables the timer to be started and to become wait state for valid edge of input
signal via the TImn pin.
<2> The rise of input signal via the TImn pin is sampled by fMCK.
<3> The edge is detected by the rising of the sampled signal and the detection signal (count clock) is output.
Remarks 1.
: Rising edge of the count clock
: Synchronization, increment/decrement of counter
2.
fCLK: CPU/peripheral hardware clock
fMCK: Operation clock of channel n
3.
The waveform of the input signal via TImn pin of the input pulse interval measurement, the
measurement of high/low width of input signal, and the delay counter, and the one-shot pulse output
are the same as that shown in Figure 6-22.
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6.5.2 Start timing of counter
Timer count register mn (TCRmn) becomes enabled to operation by setting of TSmn bit of timer channel start register
m (TSm).
Operations from count operation enabled state to timer count Register mn (TCRmn) count start is shown in Table 6-6.
Table 6-6. Operations from Count Operation Enabled State to Timer count Register mn (TCRmn) Count Start
Timer operation mode
• Interval timer mode
Operation when TSmn = 1 is set
No operation is carried out from start trigger detection (TSmn=1) until count clock
generation.
The first count clock loads the value of the TDRmn register to the TCRmn
register and the subsequent count clock performs count down operation (see
6.5.2 (a) Start timing in interval timer mode).
• Event counter mode
Writing 1 to the TSmn bit loads the value of the TDRmn register to the TCRmn
register.
The subsequent count clock performs count down operation.
The external trigger detection selected by the STSmn2 to STSmn0 bits in the
TMRmn register does not start count operation (see 6.5.2 (b) Start timing in
event counter mode).
• Capture mode
No operation is carried out from start trigger detection until count clock
generation.
The first count clock loads 0000H to the TCRmn register and the subsequent
count clock performs count up operation (see 6.5.2 (c) Start timing in capture
mode).
• One-count mode
The waiting-for-start-trigger state is entered by writing 1 to the TSmn bit while the
timer is stopped (TEmn = 0).
No operation is carried out from start trigger detection until count clock
generation.
The first count clock loads the value of the TDRmn register to the TCRmn
register and the subsequent count clock performs count down operation (see
6.5.2 (d) Start timing in one-count mode).
• Capture & one-count mode
The waiting-for-start-trigger state is entered by writing 1 to the TSmn bit while the
timer is stopped (TEmn = 0).
No operation is carried out from start trigger detection until count clock
generation.
The first count clock loads 0000H to the TCRmn register and the subsequent
count clock performs count up operation (see 6.5.2 (e) Start timing in capture &
one-count mode).
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(a) Start timing in interval timer mode
<1> Operation is enabled (TEmn = 1) by writing 1 to the TSmn bit. Timer count register mn (TCRmn) holds the
initial value until count clock generation.
<2> A start trigger is generated at the first count clock after operation is enabled.
<3> When the MDmn0 bit is set to 1, INTTMmn is generated by the start trigger.
<4> By the first count clock after the operation enable, the value of timer data register mn (TDRmn) is loaded
to the TCRmn register and counting starts in the interval timer mode.
<5> When the TCRmn register counts down and its count value is 0000H, INTTMmn is generated and the
value of timer data register mn (TDRmn) is loaded to the TCRmn register and counting keeps on.
Figure 6-23. Start Timing (In Interval Timer Mode)
fMCK
(fTCLK)
TSmn(Write)
<1>
TEmn
<2>
Start trigger
detection signal
TCRmn
TDRmn
Initial
value
<3>
m
0001
m-1
<4>
0000
m
m
<5>
<R>
INTTMmn
When MDmn0 = 1 setting
Remark fMCK, the start trigger detection signal, and INTTMmn become active between one clock in
synchronization with fCLK.
Caution In the first cycle operation of count clock after writing the TSmn bit, an error at a maximum of one
clock is generated since count start delays until count clock has been generated. When the
information on count start timing is necessary, an interrupt can be generated at count start by
setting MDmn0 = 1.
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(b) Start timing in event counter mode
<1> Timer count register mn (TCRmn) holds its initial value while operation is stopped (TEmn = 0).
<2> Operation is enabled (TEmn = 1) by writing 1 to the TSmn bit.
<3> As soon as 1 has been written to the TSmn bit and 1 has been set to the TEmn bit, the value of timer data
register mn (TDRmn) is loaded to the TCRmn register to start counting.
<4> After that, the TCRmn register value is counted down according to the count clock of the valid edge of the
TImn input .
Figure 6-24. Start Timing (In Event Counter Mode)
fMCK
TSmn(Write)
<1>
TEmn
<2>
TImn input
Edge detection
Edge detection
Count clock
Start trigger
detection signal
<4>
<1>
TCRmn
<3>
Initial
value
m-1
m
m-2
<3>
TDRmn
m
Remark The timing is shown in Figure 6-24 indicates while the noise filter is not used. By making the noise filter
on-state, the edge detection becomes 2 fMCK cycles (it sums up to 3 to 4 cycles) later than the normal
cycle of TImn input.
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(c) Start timing in capture mode
<1> Operation is enabled (TEmn = 1) by writing 1 to the TSmn bit.
<2> Timer count register mn (TCRmn) holds the initial value until count clock generation.
<3> A start trigger is generated at the first count clock after operation is enabled. And the value of 0000H is
loaded to the TCRmn register and counting starts in the capture mode. (When the MDmn0 bit is set to 1,
INTTMmn is generated by the start trigger.)
<4> On detection of the valid edge of the TImn input, the value of the TCRmn register is captured to timer data
register mn (TDRmn) and INTTMmn is generated. However, this capture value is no meaning. The
TCRmn register keeps on counting from 0000H.
<5> On next detection of the valid edge of the TImn input, the value of the TCRmn register is captured to timer
data register mn (TDRmn) and INTTMmn is generated.
Figure 6-25. Start Timing (In Capture Mode)
fMCK
(fTCLK)
TSmn(Write)
<1>
TEmn
<3>
TImn input
Edge detection
Edge detection
Rising edge
<4>
Start trigger
detection signal
<2>
TCRmn Initial value
<3>
0000
0001
TDRmn
<R>
<5>
0000
0001
m-1
m
0000
m
INTTMmn
When MDmn0=1
setting
Remark The timing is shown in Figure 6-25 indicates while the noise filter is not used. By making the noise filter
on-state, the edge detection becomes 2 fMCK cycles (it sums up to 3 to 4 cycles) later than the normal
cycle of TImn input.
Since the start of the count and the timing of TIm input are asynchronous, the first capture value (<4> in
Figure 6-25) has absolutely no connection with the pulse interval. Therefore, ignore the first capture
value.
Caution In the first cycle operation of count clock after writing the TSmn bit, an error at a maximum of one
clock is generated since count start delays until count clock has been generated. When the
information on count start timing is necessary, an interrupt can be generated at count start by
setting MDmn0 = 1.
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(d) Start timing in one-count mode
<1> Operation is enabled (TEmn = 1) by writing 1 to the TSmn bit.
<2> Timer count register mn (TCRmn) holds the initial value until start trigger generation.
<3> Rising edge of the TImn input is detected.
<4> On start trigger detection, the value of timer data register mn (TDRmn) is loaded to the TCRmn register
and count starts.
<5> When the TCRmn register counts down and its count value is 0000H, INTTMmn is generated and the
value of the TCRmn register becomes FFFFH and counting stops
.
Figure 6-26. Start Timing (In One-count Mode)
fMCK
(fTCLK)
TSmn(Write)
<1>
TEmn
TImn input
<3>
Edge detection
Rising edge
<4>
Start trigger
detection signal
<5>
<2>
TCRmn
<R>
Initial value
m
1
0
FFFF
INTTMmn
Start trigger input wait status
Remark The timing is shown in Figure 6-26 indicates while the noise filter is not used. By making the noise filter
on-state, the edge detection becomes 2 fMCK cycles (it sums up to 3 to 4 cycles) later than the normal
cycle of TImn input. The error per one period occurs be the asynchronous between the period of the
TImn input and that of the count clock (fMCK).
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(e) Start timing in capture & one-count mode (when high-level width is measured)
<1> Operation is enabled (TEmn = 1) by writing 1 to the TSmn bit of timer channel start register m (TSm).
<2> Timer count register mn (TCRmn) holds the initial value until start trigger generation.
<3> Rising edge of the TImn input is detected.
<4> On start trigger detection, the value of 0000H is loaded to the TCRmn register and count starts.
<5> On detection of the falling edge of the TImn input, the value of the TCRmn register is captured to timer
data register mn (TDRmn) and INTTMmn is generated.
Figure 6-27. Start Timing (In Capture & One-count Mode)
fMCK
(fTCLK)
TSmn(Write)
<1>
TEmn
TImn input
<3>
Edge detection
Edge detection
Rising edge
<4>
Falling edge
<5>
Start trigger
detection signal
<2>
TCRmn
TDRmn
<R>
Initial value
0000
0000
m-1
m
0000
m
INTTMmn
Remark The timing is shown in Figure 6-27 indicates while the noise filter is not used. By making the noise filter
on-state, the edge detection becomes 2 fMCK cycles (it sums up to 3 to 4 cycles) later than the normal
cycle of TImn input.
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6.6 Channel Output (TOmn pin) Control
6.6.1 TOmn pin output circuit configuration
Figure 6-28. Output Circuit Configuration
<5>
TOmn register
Controller
Interrupt signal of the master channel
(INTTMmn)
Interrupt signal of the slave channel
(INTTMmp)
Set
TOmn pin
Reset/toggle
<1>
<2>
<3>
<4>
TOLmn
TOMmn
Internal bus
TOEmn
TOmn write signal
The following describes the TOmn pin output circuit.
<1> When TOMmn = 0 (master channel output mode), the set value of timer output level register m (TOLm) is
ignored and only INTTM0p (slave channel timer interrupt) is transmitted to timer output register m (TOm).
<2>
When TOMmn = 1 (slave channel output mode), both INTTMmn (master channel timer interrupt) and
INTTM0p (slave channel timer interrupt) are transmitted to the TOm register.
At this time, the TOLm register becomes valid and the signals are controlled as follows:
When TOLmn = 0:
Forward operation (INTTMmn → set, INTTM0p → reset)
When TOLmn = 1:
Reverse operation (INTTMmn → reset, INTTM0p → set)
When INTTMmn and INTTM0p are simultaneously generated, (0% output of PWM), INTTM0p (reset signal)
takes priority, and INTTMmn (set signal) is masked.
<3> While timer output is enabled (TOEmn = 1), INTTMmn (master channel timer interrupt) and INTTM0p (slave
channel timer interrupt) are transmitted to the TOm register. Writing to the TOm register (TOmn write signal)
becomes invalid.
When TOEmn = 1, the TOmn pin output never changes with signals other than interrupt signals.
To initialize the TOmn pin output level, it is necessary to set timer operation is stopped (TOEmn = 0) and to
write a value to the TOm register.
<4> While timer output is disabeled (TOEmn = 0), writing to the TOmn bit to the target channel (TOmn write signal)
becomes valid. When timer output is disabled (TOEmn = 0), neither INTTMmn (master channel timer
interrupt) nor INTTM0p (slave channel timer interrupt) is transmitted to the TOm register.
<5> The TOm register can always be read, and the TOmn pin output level can be checked.
Remark
m: Unit number (m = 0, 1)
n: Channel number
n = 0 to 3 (n = 0, 2 for master channel)
p: Slave channel number
n = 0: p = 1, 2, 3
n = 2: p = 3
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6.6.2 TOmn Pin Output Setting
The following figure shows the procedure and status transition of the TOmn output pin from initial setting to timer
operation start.
Figure 6-29. Status Transition from Timer Output Setting to Operation Start
TCRmn
(Counter)
Undefined value (FFFFH after reset)
Hi-Z
Timer alternate-function pin
Timer output signal
TOmn
TOEmn
Write operation enabled period to TOmn
<1> Set TOMmn
Set TOLmn
<2> Set TOmn
Write operation disabled period to TOmn
<3> Set TOEmn
<4> Set the port to <5> Timer operation start
output mode
<1> The operation mode of timer output is set.
• TOMmn bit (0: Master channel output mode, 1: Slave channel output mode)
• TOLmn bit (0: Positive logic output, 1: Negative logic output)
<2> The timer output signal is set to the initial status by setting timer output register m (TOm).
<3> The timer output operation is enabled by writing 1 to the TOEmn bit (writing to the TOm register is disabled).
<4> The port I/O setting is set to output (see 6.3 (15) Port mode registers 0, 1, 3, 6 (PM0, PM1, PM3, PM6)).
<5> The timer operation is enabled (TSmn = 1).
Remark
m: Unit number (m = 0, 1), n: Channel number (n = 0 to 3)
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6.6.3 Cautions on Channel Output Operation
(1) Changing values set in the registers TOm, TOEm, TOLm, and TOMm during timer operation
Since the timer operations (operations of timer count register mn (TCRmn) and timer data register mn (TDRmn)) are
independent of the TOmn output circuit and changing the values set in timer output register m (TOm), timer output
enable register m (TOEm), timer output level register m (TOLm), and timer output mode register m (TOMm) does not
affect the timer operation, the values can be changed during timer operation. To output an expected waveform from the
TOmn pin by timer operation, however, set the TOm, TOEm, TOLm, and TOMm registers to the values stated in the
register setting example of each operation shown by 6.7 and 6.8.
When the values set to the TOEm, TOLm, and TOMm registers (but not the TOm register) are changed close to the
occurrence of the timer interrupt (INTTMmn) of each channel, the waveform output to the TOmn pin might differ,
depending on whether the values are changed immediately before or immediately after the timer interrupt (INTTMmn)
occurs.
Remark
m: Unit number (m = 0, 1), n: Channel number (n = 0 to 3)
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(2) Default level of TOmn pin and output level after timer operation start
The change in the output level of the TOmn pin when timer output register m (TOm) is written while timer output is
disabled (TOEmn = 0), the initial level is changed, and then timer output is enabled (TOEmn = 1) before port
output is enabled, is shown below.
(a) When operation starts with master channel output mode (TOMmn = 0) setting
The setting of timer output level register m (TOLm) is invalid when master channel output mode (TOMmn = 0).
When the timer operation starts after setting the default level, the toggle signal is generated and the output
level of the TOmn pin is reversed.
Figure 6-30. TOmn Pin Output Status at Toggle Output (TOMmn = 0)
TOEmn
Default level, TOLmn setting
TOmn = 0, TOLmn = 0
Hi-Z
TOmn = 1, TOLmn = 0
Hi-Z
TOmn = 0, TOLmn = 1
(Same output waveform as TOLmn = 0)
Hi-Z
TOmn = 1, TOLmn = 1
(Same output waveform as TOLmn = 0)
Hi-Z
Dependent on TOmn setting
Independent of TOLmn setting
Port output is enabled
Toggle
Toggle
Toggle
Toggle
Toggle
TO0n pin transition
Remarks 1. Toggle:
Reverse TOmn pin output status
2. m: Unit number (m = 0, 1), n: Channel number (n = 0 to 3)
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(b) When operation starts with slave channel output mode (TOMmn = 1) setting (PWM output))
When slave channel output mode (TOMmn = 1), the active level is determined by timer output level register m
(TOLm) setting.
Figure 6-31. TOmn Pin Output Status at PWM Output (TOMmn = 1)
TOEmn
Default level, TOLmn setting
TOmn = 0, TOLmn = 0
(Active high)
Hi-Z
TOmn = 1, TOLmn = 0
(Active high)
Hi-Z
TOmn = 0, TOLmn = 1
(Active low)
Hi-Z
TOmn = 1, TOLmn = 1
(Active low)
Hi-Z
No change
Dependent on TOmn setting
Independent of TOLmn setting
Port output is enabled
Set
Reset
Set
Reset
Set
TOmn pin transition
Remarks 1. Set:
Reset:
The output signal of the TOmn pin changes from inactive level to active level.
The output signal of the TOmn pin changes from active level to inactive level.
2. m: Unit number (m = 0, 1), n: Channel number (n = 0 to 3)
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(3) Operation of TOmn pin in slave channel output mode (TOMmn = 1)
(a) When timer output level register m (TOLm) setting has been changed during timer operation
When the TOLm register setting has been changed during timer operation, the setting becomes valid at the
generation timing of the TOmn pin change condition. Rewriting the TOLm register does not change the output
level of the TOmn pin.
The operation when TOMmn is set to 1 and the value of the TOLm register is changed while the timer is
operating (TEmn = 1) is shown below.
Figure 6-32. Operation when TOLm Register Has Been Changed during Timer Operation
Output set signal
(Internal signal)
Output reset signal
(Internal signal)
TOLmn
TOmn pin
TOmn does not change
Remarks 1. Set:
Reset:
Set/reset signals are inverted
The output signal of the TOmn pin changes from inactive level to active level.
The output signal of the TOmn pin changes from active level to inactive level.
2. m: Unit number (m = 0, 1), n: Channel number (n = 0 to 3)
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(b) Set/reset timing
To realize 0%/100% output at PWM output, the TOmn pin/TOmn bit set timing at master channel timer interrupt
(INTTMmn) generation is delayed by 1 count clock by the slave channel.
If the set condition and reset condition are generated at the same time, a higher priority is given to the latter.
Figure 6-33 shows the set/reset operating statuses where the master/slave channels are set as follows.
Master channel:
TOEmn = 1, TOMmn = 0, TOLmn = 0
Slave channel:
TOEmp = 1, TOMmp = 1, TOLmp = 0
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Figure 6-33. Set/Reset Timing Operating Statuses
(1) Basic operation timing
fTCLK
INTTMmn
Master
channel
Internal reset
signal
TOmn pin/
TOmn
Toggle
Toggle
Internal set
signal
1 clock delay
Slave
channel
INTTMmp
Internal reset
signal
TOmp pin/
TOmp
Set
Set
Reset
(2) Operation timing when 0 % duty
fTCLK
INTTMmn
Master
channel
Internal reset
signal
TOmn pin/
Toggle
Toggle
Internal set
signal
1 clock delay
TCRmp
Slave
channel
0000
0001
0000
0001
INTTMmp
Set
Internal reset
signal
TOmp pin/
TOmp
Reset
Set
Reset has priority.
Reset
Reset has priority.
Remarks 1. Internal reset signal: TOmn pin reset/toggle signal
Internal set signal:
TOmn pin set signal
2. m: Unit number (m = 0, 1)
n: Channel number
n = 0 to 3 (n = 0, 2 for master channel)
p: Slave channel number
n = 0: p = 1, 2, 3
n = 2: p = 3
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6.6.4 Collective manipulation of TOmn bit
In timer output register m (TOm), the setting bits for all the channels are located in one register in the same way as
timer channel start register m (TSm). Therefore, the TOmn bit of all the channels can be manipulated collectively.
Only the desired bits can also be manipulated by enabling writing only to the TOmn bits (TOEmn = 0) that correspond
to the relevant bits of the channel used to perform output (TOmn).
Figure 6-34 Example of TO0n Bit Collective Manipulation
Before writing
TO0
0
0
0
0
0
0
0
0
0
0
0
0
TO03 TO02 TO01 TO00
1
TOE0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
0
TOE03 TOE02 TOE01 TOE00
0
0
0
1
0
1
1
1
O
×
Data to be written
0
0
0
0
0
0
0
0
0
0
0
0
O O
After writing
TO0
0
0
0
0
0
0
0
0
0
0
0
0
TO03 TO02 TO01 TO00
0
1
1
0
Writing is done only to the TOmn bit with TOEmn = 0, and writing to the TOmn bit with TOEmn = 1 is ignored.
TOmn (channel output) to which TOEmn = 1 is set is not affected by the write operation. Even if the write operation is
done to the TOmn bit, it is ignored and the output change by timer operation is normally done.
Caution While timer output is enabled (TOEmn = 1), even if the output by timer interrupt of each timer
(INTTMmn) contends with writing to the TOmn bit, output is normally done to the TOmn pin.
Remark m: Unit number (m = 0, 1), n: Channel number (n = 0 to 3)
Figure 6-35. TO0n Pin Statuses by Collective Manipulation of TO0n Bit
Two or more TO0n output can
be changed simultaneously
Output does not change
when value does not
change
TO03
Writing to the TO0n bit is
ignored when TOE0n
=1
TO02
TO01
TO00
Before writing
Writing to the TO0n bit
(Caution and Remark are given on the next page.)
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Caution While timer output is enabled (TOEmn = 1), even if the output by timer interrupt of each timer
(INTTMmn) contends with writing to the TOmn bit, output is normally done to the TOmn pin.
Remark m: Unit number (m = 0, 1), n: Channel number (n = 0 to 7)
6.6.5 Timer Interrupt and TOmn Pin Output at Operation Start
In the interval timer mode or capture mode, the MDmn0 bit in timer mode register mn (TMRmn) sets whether or not to
generate a timer interrupt at count start.
When MDmn0 is set to 1, the count operation start timing can be known by the timer interrupt (INTTMmn) generation.
In the other modes, neither timer interrupt at count operation start nor TOmn output is controlled.
Figures 6-36 show operation examples when the interval timer mode (TOEmn = 1, TOMmn = 0) is set.
Figure 6-36. Operation examples of timer interrupt at count operation start and TOmn output
(a) When MDmn0 is set to 1
TCRmn
TEmn
INTTMmn
TOmn
Count operation start
(b) When MDmn0 is set to 0
TCRmn
TEmn
INTTMmn
TOmn
Count operation start
When MDmn0 is set to 1, a timer interrupt (INTTMmn) is output at count operation start, and TOmn performs a toggle
operation.
When MDmn0 is set to 0, a timer interrupt (INTTMmn) is not output at count operation start, and TOmn does not
change either. After counting one cycle, INTTMmn is output and TOmn performs a toggle operation.
Remark m: Unit number (m = 0, 1), n: Channel number (n = 0 to 3)
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6.7 Independent Channel Operation Function of Timer Array Unit
6.7.1 Operation as interval timer/square wave output
(1) Interval timer
The timer array unit can be used as a reference timer that generates INTTMmn (timer interrupt) at fixed intervals.
The interrupt generation period can be calculated by the following expression.
Generation period of INTTMmn (timer interrupt) = Period of count clock × (Set value of TDRmn + 1)
(2) Operation as square wave output
TOmn performs a toggle operation as soon as INTTMmn has been generated, and outputs a square wave with a
duty factor of 50%.
The period and frequency for outputting a square wave from TOmn can be calculated by the following expressions.
• Period of square wave output from TOmn = Period of count clock × (Set value of TDRmn + 1) × 2
• Frequency of square wave output from TOmn = Frequency of count clock/{(Set value of TDRmn + 1) × 2}
Timer count register mn (TCRmn) operates as a down counter in the interval timer mode.
The TCRmn register loads the value of timer data register mn (TDRmn) at the first count clock after the channel
start trigger bit (TSmn, TSHm1, TSHm3) of timer channel start register m (TSm) is set to 1. If the MDmn0 bit of
timer mode register mn (TMRmn) is 0 at this time, INTTMmn is not output and TOmn is not toggled. If the MDmn0
bit of the TMRmn register is 1, INTTMmn is output and TOmn is toggled.
After that, the TCRmn register count down in synchronization with the count clock.
When TCRmn = 0000H, INTTMmn is output and TOmn is toggled at the next count clock. At the same time, the
TCRmn register loads the value of the TDRmn register again. After that, the same operation is repeated.
The TDRmn register can be rewritten at any time. The new value of the TDRmn register becomes valid from the
next period.
Remark m: Unit number (m = 0, 1), n: Channel number (n = 0 to 3)
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Clock selection
Figure 6-37. Block Diagram of Operation as Interval Timer/Square Wave Output
CKm1
CKm0
Trigger selection
Operation clockNote
TSmn
<R>
Timer counter
register mn (TCRmn)
Output
controller
Timer data
register mn(TDRmn)
Interrupt
controller
TOmn pin
Interrupt signal
(INTTMmn)
Note When channels 1 and 3, the clock can be selected from CKm0, CKm1, CKm2 and CKm3.
Figure 6-38. Example of Basic Timing of Operation as Interval Timer/Square Wave Output (MDmn0 = 1)
TSmn
TEmn
TCRmn
0000H
TDRmn
a
b
TOmn
INTTMmn
a+1
a+1
a+1
b+1
b+1
b+1
Remarks 1. m: Unit number (m = 0, 1), n: Channel number (n = 0 to 3)
2. TSmn:
TEmn:
Bit n of timer channel start register m (TSm)
Bit n of timer channel enable status register m (TEm)
TCRmn:
Timer count register mn (TCRmn)
TDRmn:
Timer data register mn (TDRmn)
TOmn:
TOmn pin output signal
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Figure 6-39. Example of Set Contents of Registers During Operation as Interval Timer/Square Wave Output (1/2)
(a) Timer mode register mn (TMRmn)
15
TMRmn
14
13
CKSmn1 CKSmn0
1/0
1/0
12
11
CCSmn M/S
0
0
Note
10
9
8
7
6
5
4
0
0
STSmn2 STSmn1 STSmn0 CISmn1 CISmn0
0/1
0
0
0
0
3
2
1
0
MDmn3 MDmn2 MDmn1 MDmn0
0
0
0
0
1/0
Operation mode of channel n
000B: Interval timer
Setting of operation when counting is started
0: Neither generates INTTMmn nor inverts
timer output when counting is started.
1: Generates INTTMmn and inverts timer
output when counting is started.
Selection of TImn pin input edge
00B: Sets 00B because these are not used.
Start trigger selection
000B: Selects only software start.
Setting of MASTERmn or SPLITmn bit
0: Independent channel operation function.
(This is set to 1 when using channels 1 and 3 (TMRm1 and TMRm3) in the 8-bit
timer mode.)
Count clock selection
0: Selects operation clock (fMCK).
Operation clock (fMCK) selection
00B: Selects CKm0 as operation clock of channel n.
10B: Selects CKm1 as operation clock of channel n.
01B: Selects CKm2 as operation clock of channels 1, 3 (This can only be selected channels 1 and 3).
11B: Selects CKm3 as operation clock of channels 1, 3 (This can only be selected channels 1 and 3).
(b) Timer output register m (TOm)
Bit n
TOm
TOmn
0: Outputs 0 from TOmn.
1/0
1: Outputs 1 from TOmn.
(c) Timer output enable register m (TOEm)
Bit n
TOEm
TOEmn
1/0
0: Stops the TOmn output operation by counting operation.
1: Enables the TOmn output operation by counting operation.
Note TMRm2:
MASTERmn bit
TMRm1, TMRm3: SPLITmn bit
TMRm0:
Fixed to 0
Remark m: Unit number (m = 0, 1), n: Channel number (n = 0 to 3)
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Figure 6-39. Example of Set Contents of Registers During Operation as Interval Timer/Square Wave Output (2/2)
(d) Timer output level register m (TOLm)
Bit n
TOLm
TOLmn
0: Cleared to 0 when TOMmn = 0 (master channel output mode)
0
(e) Timer output mode register m (TOMm)
Bit n
TOMm
TOMmn
0: Sets master channel output mode.
0
Remark m: Unit number (m = 0, 1), n: Channel number (n = 0 to 3)
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Figure 6-40. Operation Procedure of Interval Timer/Square Wave Output Function (1/2)
Software Operation
TAU
default
setting
Hardware Status
Power-off status
(Clock supply is stopped and writing to each register is
disabled.)
Sets the TAUmEN bit of peripheral enable register 0
(PER0) to 1.
Power-on status. Each channel stops operating.
(Clock supply is started and writing to each register is
enabled.)
Sets timer clock select register m (TPSm).
Determines clock frequencies of CKm0 and CKm1 (or
CKm2 and CKm3 when using the 8-bit timer mode).
Channel
default
setting
Operation is resumed.
Operation
start
Sets timer mode register mn (TMRmn) (determines
operation mode of channel).
Sets interval (period) value to timer data register mn
(TDRmn).
Channel stops operating.
(Clock is supplied and some power is consumed.)
To use the TOmn output
Clears the TOMmn bit of timer output mode register m
(TOMm) to 0 (master channel output mode).
Clears the TOLmn bit to 0.
Sets the TOmn bit and determines default level of the
TOmn output.
The TOmn pin goes into Hi-Z output state.
Sets the TOEmn bit to 1 and enables operation of TOmn.
Clears the port register and port mode register to 0.
TOmn does not change because channel stops operating.
The TOmn pin outputs the TOmn set level.
(Sets the TOEmn bit to 1 only if using TOmn output and
resuming operation.).
Sets the TSmn (TSHm1, TSHm3) bit to 1.
The TSmn (TSHm1, TSHm3) bit automatically returns
to 0 because it is a trigger bit.
The TOmn default setting level is output when the port mode
register is in the output mode and the port register is 0.
TEmn (TEHm1, TEHm3) = 1, and count operation starts.
Value of the TDRmn register is loaded to timer count
register mn (TCRmn) at the count clock input. INTTMmn is
generated and TOmn performs toggle operation if the
MDmn0 bit of the TMRmn register is 1.
During
operation
Set values of the TMRmn register, TOMmn, and TOLmn
bits cannot be changed.
Set value of the TDRmn register can be changed.
The TCRmn register can always be read.
The TSRmn register is not used.
Set values of the TOm and TOEm registers can be
changed.
Counter (TCRmn) counts down. When count value reaches
0000H, the value of the TDRmn register is loaded to the
TCRmn register again and the count operation is continued.
By detecting TCRmn = 0000H, INTTMmn is generated and
TOmn performs toggle operation.
After that, the above operation is repeated.
Operation
stop
The TTmn (TTHm1, TTHm3) bit is set to 1.
The TTmn (TTHm1, TTHm3) bit automatically returns
to 0 because it is a trigger bit.
TEmn (TEHm1, TEHm3), and count operation stops.
The TCRmn register holds count value and stops.
The TOmn output is not initialized but holds current status.
The TOEmn bit is cleared to 0 and value is set to the TOmn bit.
The TOmn pin outputs the TOmn bit set level.
(Remark is listed on the next page.)
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Figure 6-40. Operation Procedure of Interval Timer/Square Wave Output Function (2/2)
Software Operation
TAU
stop
To hold the TOmn pin output level
Clears the TOmn bit to 0 after the value to
be held is set to the port register.
When holding the TOmn pin output level is not necessary
Setting not required.
The TAUmEN bit of the PER0 register is cleared to 0.
Hardware Status
The TOmn pin output level is held by port function.
Power-off status
All circuits are initialized and SFR of each channel is also
initialized.
(The TOmn bit is cleared to 0 and the TOmn pin is set to
port mode.)
Remark m: Unit number (m = 0, 1), n: Channel number (n = 0 to 3)
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6.7.2 Operation as external event counter
The timer array unit can be used as an external event counter that counts the number of times the valid input edge
(external event) is detected in the TImn pin. When a specified count value is reached, the event counter generates an
interrupt. The specified number of counts can be calculated by the following expression.
Specified number of counts = Set value of TDRmn + 1
Timer count register mn (TCRmn) operates as a down counter in the event counter mode.
The TCRmn register loads the value of timer data register mn (TDRmn) by setting any channel start trigger bit (TSmn,
TSHm1, TSHm3) of timer channel start register m (TSm) to 1.
The TCRmn register counts down each time the valid input edge of the TImn pin has been detected. When TCRmn =
0000H, the TCRmn register loads the value of the TDRmn register again, and outputs INTTMmn.
After that, the above operation is repeated.
An irregular waveform that depends on external events is output from the TOmn pin. Stop the output by setting the
TOEmn bit of timer output enable register m (TOEm) to 0.
The TDRmn register can be rewritten at any time. The new value of the TDRmn register becomes valid during the next
count period.
TSmn
Trigger selection
Edge
detection
TImn pin
Clock selection
Figure 6-41. Block Diagram of Operation as External Event Counter
Timer counter
register mn (TCRmn)
Timer data
register mn (TDRmn)
Interrupt
controller
Interrupt signal
(INTTMmn)
Remark m: Unit number (m = 0, 1), n: Channel number (n = 0 to 3)
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Figure 6-42. Example of Basic Timing of Operation as External Event Counter
TSmn
TEmn
TImn
3
TCRmn
0000H
TDRmn
2
3
1
2
0
1
2
0
0003H
1
2
0
1
0002H
INTTMmn
4 events
4 events
3 events
Remarks 1. m: Unit number (m = 0, 1), n: Channel number (n = 0 to 3)
2. TSmn:
Bit n of timer channel start register m (TSm)
TEmn:
Bit n of timer channel enable status register m (TEm)
TImn:
TImn pin input signal
TCRmn:
Timer count register mn (TCRmn)
TDRmn:
Timer data register mn (TDRmn)
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Figure 6-43. Example of Set Contents of Registers in External Event Counter Mode (1/2)
(a) Timer mode register mn (TMRmn)
15
TMRmn
14
13
CKSmn1 CKSmn0
1/0
1/0
12
11
CCSmn M/S
0
1
Note
10
9
8
7
6
5
4
0
0
STSmn2 STSmn1 STSmn0 CISmn1 CISmn0
0/1
0
0
0
1/0
3
2
1
0
MDmn3 MDmn2 MDmn1 MDmn0
1/0
0
1
1
0
Operation mode of channel n
011B: Event count mode
Setting of operation when counting is started
0: Neither generates INTTMmn nor inverts
timer output when counting is started.
Selection of TImn pin input edge
00B: Detects falling edge.
01B: Detects rising edge.
10B: Detects both edges.
11B: Setting prohibited
Start trigger selection
000B: Selects only software start.
Setting of MASTERmn or SPLITmn bit
0: Independent channel operation function.
(This is set to 1 when using channels 1 and 3 (TMRm1 and TMRm3) in the 8-bit
timer mode.)
Count clock selection
1: Selects the TImn pin input valid edge.
Operation clock (fMCK) selection
00B: Selects CKm0 as operation clock of channel n.
10B: Selects CKm1 as operation clock of channel n.
01B: Selects CKm2 as operation clock of channels 1, 3 (This can only be selected channels 1 and 3).
11B: Selects CKm3 as operation clock of channels 1, 3 (This can only be selected channels 1 and 3).
(b) Timer output register m (TOm)
Bit n
TOm
TOmn
0: Outputs 0 from TOmn.
0
(c) Timer output enable register m (TOEm)
Bit n
TOEm
TOEmn
0: Stops the TOmn output operation by counting operation.
0
Note TMRm2:
MASTERmn bit
TMRm1, TMRm3: SPLITmn bit
TMRm0:
Fixed to 0
Remark m: Unit number (m = 0, 1), n: Channel number (n = 0 to 3)
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Figure 6-43. Example of Set Contents of Registers in External Event Counter Mode (2/2)
(d) Timer output level register m (TOLm)
Bit n
TOLm
TOLmn
0: Cleared to 0 when TOMmn = 0 (master channel output mode).
0
(e) Timer output mode register m (TOMm)
Bit n
TOMm
TOMmn
0: Sets master channel output mode.
0
Remark m: Unit number (m = 0, 1), n: Channel number (n = 0 to 3)
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Figure 6-44. Operation Procedure When External Event Counter Function Is Used
Software Operation
Hardware Status
Power-off status
TAU
default
(Clock supply is stopped and writing to each register is
setting
disabled.)
Sets the TAUmEN bit of peripheral enable register 0
(PER0) to 1.
Power-on status. Each channel stops operating.
(Clock supply is started and writing to each register is
enabled.)
Sets timer clock select register m (TPSm).
Determines clock frequencies of CKm0 and CKm1 (or
CKm2 and CKm3 when using the 8-bit timer mode).
Channel
Sets timer mode register mn (TMRmn) (determines
Channel stops operating.
default
operation mode of channel).
(Clock is supplied and some power is consumed.)
setting
Sets number of counts to timer data register mn
(TDRmn).
Clears the TOEmn bit of timer output enable register m
(TOEm) to 0.
Operation
Operation is resumed.
start
Sets the TSmn bit to 1.
TEmn = 1, and count operation starts.
The TSmn bit automatically returns to 0 because it is a
Value of the TDRmn register is loaded to timer count
trigger bit.
register mn (TCRmn) and detection of the TImn pin
input edge is awaited.
During
Set value of the TDRmn register can be changed.
Counter (TCRmn) counts down each time input edge of
operation
The TCRmn register can always be read.
the TImn pin has been detected. When count value
The TSRmn register is not used.
reaches 0000H, the value of the TDRmn register is loaded
Set values of the TMRmn register, TOMmn, TOLmn,
to the TCRmn register again, and the count operation is
TOmn, and TOEmn bits cannot be changed.
continued. By detecting TCRmn = 0000H, the INTTMmn
output is generated.
After that, the above operation is repeated.
Operation
stop
The TTmn bit is set to 1.
The TTmn bit automatically returns to 0 because it is a
TEmn = 0, and count operation stops.
The TCRmn register holds count value and stops.
trigger bit.
TAU
The TAUmEN bit of the PER0 register is cleared to 0.
stop
Power-off status
All circuits are initialized and SFR of each channel is
also initialized.
Remark m: Unit number (m = 0, 1), n: Channel number (n = 0 to 3)
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6.7.3 Operation as frequency divider (channel 0 of unit 0 only)
The timer array unit can be used as a frequency divider that divides a clock input to the TI00 pin and outputs the result
from the TO00 pin.
The divided clock frequency output from TO00 can be calculated by the following expression.
• When rising edge/falling edge is selected:
Divided clock frequency = Input clock frequency/{(Set value of TDR00 + 1) × 2}
• When both edges are selected:
Divided clock frequency ≅ Input clock frequency/(Set value of TDR00 + 1)
Timer count register 00 (TCR00) operates as a down counter in the interval timer mode.
After the channel start trigger bit (TS00) of timer channel start register 0 (TS0) is set to 1, the TCR00 register loads the
value of timer data register 00 (TDR00) when the TI00 valid edge is detected.
If the MD000 bit of timer mode register 00 (TMR00) is 0 at this time, INTTM00 is not output and TO00 is not toggled. If
the MD000 bit of timer mode register 00 (TMR00) is 1, INTTM00 is output and TO00 is toggled.
After that, the TCR00 register counts down at the valid edge of the TI00 pin. When TCR00 = 0000H, it toggles TO00.
At the same time, the TCR00 register loads the value of the TDR00 register again, and continues counting.
If detection of both the edges of the TI00 pin is selected, the duty factor error of the input clock affects the divided clock
period of the TO00 output.
The period of the TO00 output clock includes a sampling error of one period of the operation clock.
Clock period of TO00 output = Ideal TO00 output clock period ± Operation clock period (error)
The TDR00 register can be rewritten at any time. The new value of the TDR00 register becomes valid during the next
count period.
TS00
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Trigger selection
Edge
detection
TI00 pin
Clock selection
Figure 6-45. Block Diagram of Operation as Frequency Divider
Timer counter
register 00 (TCR00)
Output
controller
TO00 pin
Timer data
register 00 (TDR00)
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Figure 6-46. Example of Basic Timing of Operation as Frequency Divider (MD000 = 1)
TS00
TE00
TI00
2
2
1
TCR00
0000H
TDR00
2
1
0
1
0
1
0
0002H
1
1
0
0
1
0
0
0001H
TO00
INTTM00
Divided
by 6
Remark TS00:
Divided
by 4
Bit n of timer channel start register 0 (TS0)
TE00:
Bit n of timer channel enable status register 0 (TE0)
TI00:
TI00 pin input signal
TCR00: Timer count register 00 (TCR00)
TDR00: Timer data register 00 (TDR00)
TO00:
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Figure 6-47. Example of Set Contents of Registers During Operation as Frequency Divider
(a) Timer mode register 00 (TMR00)
15
TMR00
14
13
CKS0n1 CKS0n0
1/0
0
0
12
11
CCS00
MAS
TER00
1
0
10
9
8
7
6
5
4
0
0
STS002 STS001 STS000 CIS001 CIS000
0
0
0
1/0
3
2
1
0
MD003 MD002 MD001 MD000
1/0
0
0
0
1/0
Operation mode of channel 0
000B: Interval timer
Setting of operation when counting is started
0: Neither generates INTTM00 nor inverts
timer output when counting is started.
1: Generates INTTM00 and inverts timer
output when counting is started.
Selection of TI00 pin input edge
00B: Detects falling edge.
01B: Detects rising edge.
10B: Detects both edges.
11B: Setting prohibited
Start trigger selection
000B: Selects only software start.
Slave/master selection
0: Independent channel operation function.
Count clock selection
1: Selects the TI00 pin input valid edge.
Operation clock (fMCK) selection
00B: Selects CK00 as operation clock of channel 0.
10B: Selects CK01 as operation clock of channel 0.
(b) Timer output register 0 (TO0)
Bit 0
TO0
TO00
0: Outputs 0 from TO00.
1/0
1: Outputs 1 from TO00.
(c) Timer output enable register 0 (TOE0)
Bit 0
TOE0
TOE00
1/0
0: Stops the TO00 output operation by counting operation.
1: Enables the TO00 output operation by counting operation.
(d) Timer output level register 0 (TOL0)
Bit 0
TOL0
TOL00
0: Cleared to 0 when TOM00 = 0 (master channel output mode)
0
(e) Timer output mode register 0 (TOM0)
Bit 0
TOM0
TOM00
0: Sets master channel output mode.
0
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Figure 6-48. Operation Procedure When Frequency Divider Function Is Used
Software Operation
TAU
default
setting
Hardware Status
Power-off status
(Clock supply is stopped and writing to each register is
disabled.)
Sets the TAU0EN bit of peripheral enable register 0
(PER0) to 1.
Power-on status. Each channel stops operating.
(Clock supply is started and writing to each register is
enabled.)
Sets timer clock select register 0 (TPS0).
Determines clock frequencies of CK00 and CK01.
Channel
default
setting
Sets timer mode register 0n (TMR0n) (determines
operation mode of channel and selects the detection
edge).
Sets interval (period) value to timer data register 00
(TDR00).
Channel stops operating.
(Clock is supplied and some power is consumed.)
Clears the TOM00 bit of timer output mode register 0
(TOM0) to 0 (master channel output mode).
Clears the TOL00 bit to 0.
Sets the TO00 bit and determines default level of the
TO00 output.
The TO00 pin goes into Hi-Z output state.
Operation is resumed.
Sets the TOE00 bit to 1 and enables operation of TO00.
Clears the port register and port mode register to 0.
The TO00 default setting level is output when the port mode
register is in output mode and the port register is 0.
TO00 does not change because channel stops operating.
The TO00 pin outputs the TO00 set level.
Operation
start
Sets the TOE00 bit to 1 (only when operation is
resumed).
Sets the TS00 bit to 1.
The TS00 bit automatically returns to 0 because it is a
trigger bit.
During
operation
Set value of the TDR00 register can be changed.
The TCR00 register can always be read.
The TSR00 register is not used.
Set values of the TO0 and TOE0 registers can be
changed.
Set values of the TMR00 register, TOM00, and TOL00
bits cannot be changed.
Counter (TCR00) counts down. When count value reaches
0000H, the value of the TDR00 register is loaded to the
TCR00 register again, and the count operation is continued.
By detecting TCR00 = 0000H, INTTM00 is generated and
TO00 performs toggle operation.
After that, the above operation is repeated.
Operation
stop
The TT00 bit is set to 1.
The TT00 bit automatically returns to 0 because it is a
trigger bit.
TE00 = 0, and count operation stops.
The TCR00 register holds count value and stops.
The TO00 output is not initialized but holds current status.
The TOE00 bit is cleared to 0 and value is set to the TO00 bit.
The TO00 pin outputs the TO00 set level.
TAU
stop
To hold the TO00 pin output level
Clears the TO00 bit to 0 after the value to be held is
set to the port register.
When holding the TO00 pin output level is not
necessary
Setting not required.
The TAU0EN bit of the PER0 register is cleared to 0.
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TE00 = 1, and count operation starts.
Value of the TDR00 register is loaded to timer count
register 00 (TCR00) at the count clock input. INTTM00 is
generated and TO00 performs toggle operation if the
MD000 bit of the TMR00 register is 1.
The TO00 pin output level is held by port function.
Power-off status
All circuits are initialized and SFR of each channel is also
initialized.
(The TO00 bit is cleared to 0 and the TO00 pin is set to
port mode).
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6.7.4 Operation as input pulse interval measurement
The count value can be captured at the TImn valid edge and the interval of the pulse input to TImn can be measured.
The pulse interval can be calculated by the following expression.
TImn input pulse interval = Period of count clock × ((10000H × TSRmn: OVF) + (Capture value of TDRmn + 1))
Caution The TImn pin input is sampled using the operating clock selected with the CKSmn bit of timer
mode register mn (TMRmn), so an error of up to one operating clock cycle occurs.
Timer count register mn (TCRmn) operates as an up counter in the capture mode.
When the channel start trigger bit (TSmn) of timer channel start register m (TSm) is set to 1, the TCRmn register counts
up from 0000H in synchronization with the count clock.
When the TImn pin input valid edge is detected, the count value of the TCRmn register is transferred (captured) to
timer data register mn (TDRmn) and, at the same time, the TCRmn register is cleared to 0000H, and the INTTMmn is
output. If the counter overflows at this time, the OVF bit of timer status register mn (TSRmn) is set to 1. If the counter
does not overflow, the OVF bit is cleared. After that, the above operation is repeated.
As soon as the count value has been captured to the TDRmn register, the OVF bit of the TSRmn register is updated
depending on whether the counter overflows during the measurement period. Therefore, the overflow status of the
captured value can be checked.
If the counter reaches a full count for two or more periods, it is judged to be an overflow occurrence, and the OVF bit of
the TSRmn register is set to 1. However, a normal interval value cannot be measured for the OVF bit, if two or more
overflows occur.
Set the STSmn2 to STSmn0 bits of the TMRmn register to 001B to use the valid edges of TImn as a start trigger and a
capture trigger.
When TEmn = 1, a software operation (TSmn = 1) can be used as a capture trigger, instead of using the TImn pin input.
CKm1
CKm0
Edge
detection
TImn pin
TSmn
<R>
Trigger selection
Operation clock Note
Clock selection
Figure 6-49. Block Diagram of Operation as Input Pulse Interval Measurement
Timer counter
register mn (TCRmn)
Timer data
register mn (TDRmn)
Interrupt
controller
Interrupt signal
(INTTMmn)
Note When channels 1 and 3, the clock can be selected from CKm0, CKm1, CKm2 and CKm3.
Remark m: Unit number (m = 0, 1), n: Channel number (n = 0 to 3)
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Figure 6-50. Example of Basic Timing of Operation as Input Pulse Interval Measurement (MDmn0 = 0)
TSmn
TEmn
TImn
FFFFH
b
a
TCRmn
d
c
0000H
TDRmn
0000H
a
b
c
d
INTTMmn
OVF
Remarks 1. m: Unit number (m = 0, 1)n: Channel number (n = 0 to 3)
2. TSmn:
Bit n of timer channel start register m (TSm)
TEmn:
Bit n of timer channel enable status register m (TEm)
TImn:
TImn pin input signal
TCRmn:
Timer count register mn (TCRmn)
TDRmn:
Timer data register mn (TDRmn)
OVF:
Bit 0 of timer status register mn (TSRmn)
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Figure 6-51. Example of Set Contents of Registers to Measure Input Pulse Interval
(a) Timer mode register mn (TMRmn)
15
TMRmn
14
13
CKSmn1 CKSmn0
1/0
0
12
11
CCSmn M/S
0
0
Note
0
10
9
8
7
6
5
4
0
0
STSmn2 STSmn1 STSmn0 CISmn1 CISmn0
0
0
1
1/0
1/0
3
2
1
0
MDmn3 MDmn2 MDmn1 MDmn0
0
1
0
1/0
Operation mode of channel n
010B: Capture mode
Setting of operation when counting is started
0: Does not generate INTTMmn when
counting is started.
1: Generates INTTMmn when counting is
started.
Selection of TImn pin input edge
00B: Detects falling edge.
01B: Detects rising edge.
10B: Detects both edges.
11B: Setting prohibited
Capture trigger selection
001B: Selects the TImn pin input valid edge.
Setting of MASTERmn or SPLITmn bit
0: Independent channel operation function.
Count clock selection
0: Selects operation clock (fMCK).
Operation clock (fMCK) selection
00B: Selects CKm0 as operation clock of channel n.
10B: Selects CKm1 as operation clock of channel n.
01B: Selects CKm2 as operation clock of channels 1, 3 (This can only be selected channels 1 and 3).
11B: Selects CKm3 as operation clock of channels 1, 3 (This can only be selected channels 1 and 3).
(b) Timer output register m (TOm)
Bit n
TOm
TOmn
0: Outputs 0 from TOmn.
0
(c) Timer output enable register m (TOEm)
Bit n
TOEm
TOEmn
0: Stops TOmn output operation by counting operation.
0
(d) Timer output level register m (TOLm)
Bit n
TOLm
TOLmn
0: Cleared to 0 when TOMmn = 0 (master channel output mode).
0
(e) Timer output mode register m (TOMm)
Bit n
TOMm
TOMmn
0: Sets master channel output mode.
0
Note TMRm2:
MASTERmn bit
TMRm1, TMRm3: SPLITmn bit
TMRm0:
Fixed to 0
Remark m: Unit number (m = 0, 1), n: Channel number (n = 0 to 3)
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Figure 6-52. Operation Procedure When Input Pulse Interval Measurement Function Is Used
Software Operation
Hardware Status
Power-off status
TAU
default
(Clock supply is stopped and writing to each register is
setting
disabled.)
Sets the TAUmEN bit of peripheral enable register 0
(PER0) to 1.
Power-on status. Each channel stops operating.
(Clock supply is started and writing to each register is
enabled.)
Sets timer clock select register m (TPSm).
Determines clock frequencies of CKm0 and CKm1.
Channel
Sets timer mode register mn (TMRmn) (determines
Channel stops operating.
default
operation mode of channel).
(Clock is supplied and some power is consumed.)
Sets TSmn bit to 1.
TEmn = 1, and count operation starts.
setting
Operation
start
The TSmn bit automatically returns to 0 because it is a
Timer count register mn (TCRmn) is cleared to 0000H
trigger bit.
at the count clock input.
When the MDmn0 bit of the TMRmn register is 1,
Operation is resumed.
INTTMmn is generated.
During
Set values of only the CISmn1 and CISmn0 bits of the
Counter (TCRmn) counts up from 0000H. When the TImn
operation
TMRmn register can be changed.
pin input valid edge is detected, the count value is
The TDRmn register can always be read.
transferred (captured) to timer data register mn (TDRmn).
The TCRmn register can always be read.
At the same time, the TCRmn register is cleared to
The TSRmn register can always be read.
0000H, and the INTTMmn signal is generated.
Set values of the TOMmn, TOLmn, TOmn, and TOEmn
If an overflow occurs at this time, the OVF bit of timer
bits cannot be changed.
status register mn (TSRmn) is set; if an overflow does not
occur, the OVF bit is cleared.
After that, the above operation is repeated.
Operation
stop
TAU
The TTmn bit is set to 1.
TEmn = 0, and count operation stops.
The TTmn bit automatically returns to 0 because it is a
The TCRmn register holds count value and stops.
trigger bit.
The OVF bit of the TSRmn register is also held.
The TAUmEN bit of the PER0 register is cleared to 0.
stop
Power-off status
All circuits are initialized and SFR of each channel is
also initialized.
Remark m: Unit number (m = 0, 1), n: Channel number (n = 0 to 3)
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6.7.5 Operation as input signal high-/low-level width measurement
Caution When using a channel to implement the LIN-bus, set bit 1 (ISC1) of the input switch control
register (ISC) to 1. In the following descriptions, read TImn as RxD0.
By starting counting at one edge of the TImn pin input and capturing the number of counts at another edge, the signal
width (high-level width/low-level width) of TImn can be measured. The signal width of TImn can be calculated by the
following expression.
Signal width of TImn input = Period of count clock × ((10000H × TSRmn: OVF) + (Capture value of TDRmn + 1))
Caution The TImn pin input is sampled using the operating clock selected with the CKSmn bit of timer
mode register mn (TMRmn), so an error equivalent to one operation clock occurs.
Timer count register mn (TCRmn) operates as an up counter in the capture & one-count mode.
When the channel start trigger bit (TSmn) of timer channel start register m (TSm) is set to 1, the TEmn bit is set to 1
and the TImn pin start edge detection wait status is set.
When the TImn pin input start edge (rising edge of the TImn pin input when the high-level width is to be measured) is
detected, the counter counts up from 0000H in synchronization with the count clock. When the valid capture edge (falling
edge of the TImn pin input when the high-level width is to be measured) is detected later, the count value is transferred to
timer data register mn (TDRmn) and, at the same time, INTTMmn is output. If the counter overflows at this time, the OVF
bit of timer status register mn (TSRmn) is set to 1. If the counter does not overflow, the OVF bit is cleared. The TCRmn
register stops at the value “value transferred to the TDRmn register + 1”, and the TImn pin start edge detection wait status
is set. After that, the above operation is repeated.
As soon as the count value has been captured to the TDRmn register, the OVF bit of the TSRmn register is updated
depending on whether the counter overflows during the measurement period. Therefore, the overflow status of the
captured value can be checked.
If the counter reaches a full count for two or more periods, it is judged to be an overflow occurrence, and the OVF bit of
the TSRmn register is set to 1. However, a normal interval value cannot be measured for the OVF bit, if two or more
overflows occur.
Whether the high-level width or low-level width of the TImn pin is to be measured can be selected by using the CISmn1
and CISmn0 bits of the TMRmn register.
Because this function is used to measure the signal width of the TImn pin input, the TSmn bit cannot be set to 1 while
the TEmn bit is 1.
CISmn1, CISmn0 of TMRmn register = 10B: Low-level width is measured.
CISmn1, CISmn0 of TMRmn register = 11B: High-level width is measured.
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CKm1
CKm0
Edge
detection
TImn pin
<R>
Timer counter
register mn (TCRmn)
Trigger selection
Operation clock Note
Clock selection
Figure 6-53. Block Diagram of Operation as Input Signal High-/Low-Level Width Measurement
Timer data
register mn (TDRmn)
Interrupt
controller
Interrupt signal
(INTTMmn)
Note For channels 1 and 3, the clock can be selected from CKm0, CKm1, CKm2 and CKm3.
Figure 6-54. Example of Basic Timing of Operation as Input Signal High-/Low-Level Width Measurement
TSmn
TEmn
TImn
FFFFH
a
b
TCRmn
c
0000H
TDRmn
0000H
a
b
c
INTTMmn
OVF
Remarks 1. m: Unit number (m = 0, 1), n: Channel number (n = 0 to 3)
2. TSmn:
Bit n of timer channel start register m (TSm)
TEmn:
Bit n of timer channel enable status register m (TEm)
TImn:
TImn pin input signal
TCRmn:
Timer count register mn (TCRmn)
TDRmn:
Timer data register mn (TDRmn)
OVF:
Bit 0 of timer status register mn (TSRmn)
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Figure 6-55. Example of Set Contents of Registers to Measure Input Signal High-/Low-Level Width
(a) Timer mode register mn (TMRmn)
15
TMRmn
14
13
CKSmn1 CKSmn0
1/0
0
12
11
CCSmn M/S
0
0
Note
10
9
8
7
6
5
4
0
0
STSmn2 STSmn1 STSmn0 CISmn1 CISmn0
0
0
1
0
1
3
2
1
0
MDmn3 MDmn2 MDmn1 MDmn0
1/0
1
1
0
0
Operation mode of channel n
110B: Capture & one-count
Setting of operation when counting is started
0: Does not generate INTTMmn when
counting is started.
Selection of TImn pin input edge
10B: Both edges (to measure low-level width)
11B: Both edges (to measure high-level width)
Start trigger selection
010B: Selects the TImn pin input valid edge.
Setting of MASTERmn or SPLITmn bit
0: Independent channel operation function.
Count clock selection
0: Selects operation clock (fMCK).
Operation clock (fMCK) selection
00B: Selects CKm0 as operation clock of channel n.
10B: Selects CKm1 as operation clock of channel n.
01B: Selects CKm2 as operation clock of channels 1, 3 (This can only be selected channels 1 and 3).
11B: Selects CKm3 as operation clock of channels 1, 3 (This can only be selected channels 1 and 3).
(b) Timer output register m (TOm)
Bit n
TOm
TOmn
0: Outputs 0 from TOmn.
0
(c) Timer output enable register m (TOEm)
Bit n
TOEm
TOEmn
0: Stops the TOmn output operation by counting operation.
0
(d) Timer output level register m (TOLm)
Bit n
TOLm
TOLmn
0: Cleared to 0 when TOMmn = 0 (master channel output mode).
0
(e) Timer output mode register m (TOMm)
Bit n
TOMm
TOMmn
0: Sets master channel output mode.
0
Note TMRm2:
MASTERmn bit
TMRm1, TMRm3: SPLITmn bit
TMRm0:
Fixed to 0
Remark m: Unit number (m = 0, 1), n: Channel number (n = 0 to 3)
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Figure 6-56. Operation Procedure When Input Signal High-/Low-Level Width Measurement Function Is Used
Software Operation
Hardware Status
Power-off status
TAU
default
(Clock supply is stopped and writing to each register is
setting
disabled.)
Sets the TAUmEN bit of peripheral enable register 0
(PER0) to 1.
Power-on status. Each channel stops operating.
(Clock supply is started and writing to each register is
enabled.)
Sets timer clock select register m (TPSm).
Determines clock frequencies of CKm0 and CKm1.
Channel
Sets timer mode register mn (TMRmn) (determines
Channel stops operating.
default
operation mode of channel).
(Clock is supplied and some power is consumed.)
setting
Clears the TOEmn bit to 0 and stops operation of TOmn.
Operation
Sets the TSmn bit to 1.
start
The TSmn bit automatically returns to 0 because it is a
TEmn = 1, and the TImn pin start edge detection wait
status is set.
trigger bit.
Operation is resumed.
Detects the TImn pin input count start valid edge.
Clears timer count register mn (TCRmn) to 0000H and
starts counting up.
During
Set value of the TDRmn register can be changed.
When the TImn pin start edge is detected, the counter
operation
The TCRmn register can always be read.
(TCRmn) counts up from 0000H. If a capture edge of the
The TSRmn register is not used.
TImn pin is detected, the count value is transferred to
Set values of the TMRmn register, TOMmn, TOLmn,
timer data register mn (TDRmn) and INTTMmn is
TOmn, and TOEmn bits cannot be changed.
generated.
If an overflow occurs at this time, the OVF bit of timer
status register mn (TSRmn) is set; if an overflow does not
occur, the OVF bit is cleared. The TCRmn register stops
the count operation until the next TImn pin start edge is
detected.
Operation
stop
TAU
The TTmn bit is set to 1.
TEmn = 0, and count operation stops.
The TTmn bit automatically returns to 0 because it is a
The TCRmn register holds count value and stops.
trigger bit.
The OVF bit of the TSRmn register is also held.
The TAUmEN bit of the PER0 register is cleared to 0.
stop
Power-off status
All circuits are initialized and SFR of each channel is
also initialized.
Remark m: Unit number (m = 0, 1), n: Channel number (n = 0 to 3)
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6.7.6 Operation as delay counter
It is possible to start counting down when the valid edge of the TImn pin input is detected (an external event), and then
generate INTTMmn (a timer interrupt) after any specified interval.
<R>
It can also generate INTTMmn (timer interrupt) at any interval by making a software set TSmn = 1 and the count down
start during the period of TEmn = 1.
The interrupt generation period can be calculated by the following expression.
Generation period of INTTMmn (timer interrupt) = Period of count clock × (Set value of TDRmn + 1)
Timer count register mn (TCRmn) operates as a down counter in the one-count mode.
When the channel start trigger bit (TSmn, TSHm1, TSHm3) of timer channel start register m (TSm) is set to 1, the
TEmn, TEHm1, TEHm3 bits are set to 1 and the TImn pin input valid edge detection wait status is set.
Timer count register mn (TCRmn) starts operating upon TImn pin input valid edge detection and loads the value of
timer data register mn (TDRmn). The TCRmn register counts down from the value of the TDRmn register it has loaded, in
synchronization with the count clock. When TCRmn = 0000H, it outputs INTTMmn and stops counting until the next TImn
pin input valid edge is detected.
The TDRmn register can be rewritten at any time. The new value of the TDRmn register becomes valid from the next
period.
CKm1
CKm0
TSmn
TImn pin
<R>
Edge
detection
Trigger selection
Operation clockNote
Clock selection
Figure 6-57. Block Diagram of Operation as Delay Counter
Timer counter
register mn (TCRmn)
Timer data
register mn (TDRmn)
Interrupt
controller
Interrupt signal
(INTTMmn)
Note For using channels 1 and 3, the clock can be selected from CKm0, CKm1, CKm2 and CKm3.
Remark
m: Unit number (m = 0, 1), n: Channel number (n = 0 to 3)
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Figure 6-58. Example of Basic Timing of Operation as Delay Counter
TSmn
TEmn
TImn
FFFFH
TCRmn
0000H
TDRmn
a
b
INTTMmn
a+1
b+1
Remarks 1. m: Unit number (m = 0, 1), n: Channel number (n = 0 to 3)
2. TSmn:
Bit n of timer channel start register m (TSm)
TEmn:
Bit n of timer channel enable status register m (TEm)
TImn:
TImn pin input signal
TCRmn:
Timer count register mn (TCRmn)
TDRmn:
Timer data register mn (TDRmn)
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Figure 6-59. Example of Set Contents of Registers to Delay Counter (1/2)
(a) Timer mode register mn (TMRmn)
15
TMRmn
14
13
CKSmn1 CKSmn0
1/0
1/0
12
11
CCSmn M/S
0
0
Note
10
9
8
7
6
5
4
STSmn2 STSmn1 STSmn0 CISmn1 CISmn0
0/1
0
0
1
1/0
3
2
1
0
MDmn3 MDmn2 MDmn1 MDmn0
1/0
0
0
1
0
0
0
Operation mode of channel n
100B: One-count mode
Start trigger during operation
0: Trigger input is invalid.
1: Trigger input is valid.
Selection of TImn pin input edge
00B: Detects falling edge.
01B: Detects rising edge.
10B: Detects both edges.
11B: Setting prohibited
Start trigger selection
001B: Selects the TImn pin input valid edge.
Setting of MASTERmn or SPLITmn bit
0: Independent channel operation function.
(This is set to 1 when using channels 1 and 3 (TMRm1 and TMRm3) in the 8-bit
timer mode.)
Count clock selection
0: Selects operation clock (fMCK).
Operation clock (fMCK) selection
00B: Selects CKm0 as operation clock of channel n.
10B: Selects CKm1 as operation clock of channel n.
01B: Selects CKm2 as operation clock of channels 1, 3 (This can only be selected channels 1 and 3).
11B: Selects CKm3 as operation clock of channels 1, 3 (This can only be selected channels 1 and 3).
(b) Timer output register m (TOm)
Bit n
TOm
TOmn
0: Outputs 0 from TOmn.
0
(c) Timer output enable register m (TOEm)
Bit n
TOEm
TOEmn
0: Stops the TOmn output operation by counting operation.
0
Note TMRm2:
MASTERmn bit
TMRm1, TMRm3: SPLITmn bit
TMRm0:
Fixed to 0
Remark m: Unit number (m = 0, 1), n: Channel number (n = 0 to 3)
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Figure 6-59. Example of Set Contents of Registers to Delay Counter (2/2)
(d) Timer output level register m (TOLm)
Bit n
TOLm
TOLmn
0: Cleared to 0 when TOMmn = 0 (master channel output mode).
0
(e) Timer output mode register m (TOMm)
Bit n
TOMm
TOMmn
0: Sets master channel output mode.
0
Remark m: Unit number (m = 0, 1), n: Channel number (n = 0 to 3)
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Figure 6-60. Operation Procedure When Delay Counter Function Is Used
Software Operation
Hardware Status
Power-off status
TAU
default
(Clock supply is stopped and writing to each register is
setting
disabled.)
Sets the TAUmEN bit of peripheral enable register 0
(PER0) to 1.
Power-on status. Each channel stops operating.
(Clock supply is started and writing to each register is
enabled.)
Sets timer clock select register m (TPSm).
Determines clock frequencies of CKm0 and CKm1 (or
CKm2 and CKm3 when using the 8-bit timer mode).
Channel
Sets timer mode register mn (TMRmn) (determines
Channel stops operating.
default
operation mode of channel).
(Clock is supplied and some power is consumed.)
setting
INTTMmn output delay is set to timer data register mn
(TDRmn).
Clears the TOEmn bit to 0 and stops operation of TOmn.
Operation
start
Sets the TSmn bit to 1.
The TSmn bit automatically returns to 0 because it is a
TEmn = 1, and the TImn pin input valid edge detection
wait status is set.
trigger bit.
Operation is resumed.
Detects the TImn pin input valid edge.
Value of the TDRmn register is loaded to the timer count
register mn (TCRmn).
During
Set value of the TDRmn register can be changed.
The counter (TCRmn) counts down. When TCRmn
operation
The TCRmn register can always be read.
counts down to 0000H, INTTMmn is output, and counting
The TSRmn register is not used.
stops (which leaves TCRmn at 0000H) until the next TImn
pin input.
Operation
stop
The TTmn bit is set to 1.
The TTmn bit automatically returns to 0 because it is a
TEmn = 0, and count operation stops.
The TCRmn register holds count value and stops.
trigger bit.
TAU
The TAUmEN bit of the PER0 register is cleared to 0.
stop
Power-off status
All circuits are initialized and SFR of each channel is
also initialized.
Remark m: Unit number (m = 0, 1), n: Channel number (n = 0 to 3)
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6.8 Simultaneous Channel Operation Function of Timer Array Unit
6.8.1 Operation as one-shot pulse output function
By using two channels as a set, a one-shot pulse having any delay pulse width can be generated from the signal input
to the TImn pin.
The delay time and pulse width can be calculated by the following expressions.
Delay time = {Set value of TDRmn (master) + 2} × Count clock period
Pulse width = {Set value of TDRmp (slave)} × Count clock period
The master channel operates in the one-count mode and counts the delays. Timer count register mn (TCRmn) of the
master channel starts operating upon start trigger detection and loads the value of timer data register mn (TDRmn).
The TCRmn register counts down from the value of the TDRmn register it has loaded, in synchronization with the count
clock. When TCRmn = 0000H, it outputs INTTMmn and stops counting until the next start trigger is detected.
The slave channel operates in the one-count mode and counts the pulse width. The TCRmp register of the slave
channel starts operation using INTTMmn of the master channel as a start trigger, and loads the value of the TDRmp
register. The TCRmp register counts down from the value of The TDRmp register it has loaded, in synchronization with
the count value. When count value = 0000H, it outputs INTTMmp and stops counting until the next start trigger (INTTMmn
of the master channel) is detected.
The output level of TOmp becomes active one count clock after generation of
INTTMmn from the master channel, and inactive when TCRmp = 0000H.
Instead of using the TImn pin input, a one-shot pulse can also be output using the software operation (TSmn = 1) as a
start trigger.
Caution The timing of loading of timer data register mn (TDRmn) of the master channel is different from that of
the TDRmp register of the slave channel. If the TDRmn and TDRmp registers are rewritten during
operation, therefore, an illegal waveform is output. Rewrite the TDRmn register after INTTMmn is
generated and the TDRmp register after INTTMmp is generated.
Remark
m: Unit number (m = 0, 1), n: Channel number (n = 0, 2)
p: Slave channel number (n = 0: p = 1, 2, 3, n = 2: p = 3)
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Figure 6-61. Block Diagram of Operation as One-Shot Pulse Output Function
CKm1
Operation clock
CKm0
TSmn
Edge
detection
TImn pin
Trigger selection
Clock selection
Master channel
(one-count mode)
Timer counter
register mn (TCRmn)
Timer data
register mn (TDRmn)
Interrupt
controller
Timer counter
register mp (TCRmp)
Output
controller
Timer data
register mp (TDRmp)
Interrupt
controller
Interrupt signal
(INTTMmn)
CKm1
Operation clock
Trigger selection
CKm0
Clock selection
Slave channel
(one-count mode)
Remark
TOmp pin
Interrupt signal
(INTTMmp)
m: Unit number (m = 0, 1), n: Channel number (n = 0, 2)
p: Slave channel number (n = 0: p = 1, 2, 3, n = 2: p = 3)
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Figure 6-62. Example of Basic Timing of Operation as One-Shot Pulse Output Function
TSmn
TEmn
TImn
Master
channel
FFFFH
TCRmn
0000H
TDRmn
a
TOmn
INTTMmn
TSmp
TEmp
FFFFH
TCRmp
Slave
channel
0000H
TDRmp
b
TOmp
INTTMmp
a+2
b
a+2
b
Remarks 1. m: Unit number (m = 0, 1), n: Channel number (n = 0, 2)
p: Slave channel number (n = 0: p = 1, 2, 3, n = 2: p = 3)
2. TSmn, TSmp:
Bit n, p of timer channel start register m (TSm)
TEmn, TEmp:
Bit n, p of timer channel enable status register m (TEm)
TImn, TImp:
TImn and TImp pins input signal
TCRmn, TCRmp: Timer count registers mn, mp (TCRmn, TCRmp)
TDRmn, TDRmp: Timer data registers mn, mp (TDRmn, TDRmp)
TOmn, TOmp:
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Figure 6-63. Example of Set Contents of Registers When One-Shot Pulse Output Function Is Used (Master Channel)
(a) Timer mode register mn (TMRmn)
15
TMRmn
14
13
CKSmn1 CKSmn0
1/0
0
12
CCSmn
0
0
11
10
9
8
7
6
5
4
MAS
STSmn2 STSmn1 STSmn0 CISmn1 CISmn0
TERmn
1
0
0
1
1/0
3
2
1
0
MDmn3 MDmn2 MDmn1 MDmn0
1/0
0
0
1
0
0
0
Operation mode of channel n
100B: One-count mode
Start trigger during operation
0: Trigger input is invalid.
Selection of TImn pin input edge
00B: Detects falling edge.
01B: Detects rising edge.
10B: Detects both edges.
11B: Setting prohibited
Start trigger selection
001B: Selects the TImn pin input valid edge.
Slave/master selection
1: Master channel.
Count clock selection
0: Selects operation clock (fMCK).
Operation clock (fMCK) selection
00B: Selects CKm0 as operation clock of channels n.
10B: Selects CKm1 as operation clock of channels n.
(b) Timer output register m (TOm)
Bit n
TOm
TOmn
0: Outputs 0 from TOmn.
0
(c) Timer output enable register m (TOEm)
Bit n
TOEm
TOEmn
0: Stops the TOmn output operation by counting operation.
0
(d) Timer output level register m (TOLm)
Bit n
TOLm
TOLmn
0: Cleared to 0 when TOMmn = 0 (master channel output mode).
0
(e) Timer output mode register m (TOMm)
Bit n
TOMm
TOMmn
0: Sets master channel output mode.
0
Remark m: Unit number (m = 0, 1), n: Channel number (n = 0, 2)
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Figure 6-64. Example of Set Contents of Registers When One-Shot Pulse Output Function Is Used (Slave Channel)
(a) Timer mode register mp (TMRmp)
15
TMRmp
14
13
CKSmp1 CKSmp0
1/0
0
12
11
CCSmp M/S
0
0
Note
0
10
9
8
7
6
5
4
0
0
STSmp2 STSmp1 STSmp0 CISmp1 CISmp0
1
0
0
0
3
2
1
0
MDmp3 MDmp2 MDmp1 MDmp0
0
1
0
0
0
Operation mode of channel p
100B: One-count mode
Start trigger during operation
0: Trigger input is invalid.
Selection of TImp pin input edge
00B: Sets 00B because these are not used.
Start trigger selection
100B: Selects INTTMmn of master channel.
Setting of MASTERmp or SPLITmp bit
0: Slave channel.
Count clock selection
0: Selects operation clock (fMCK).
Operation clock (fMCK) selection
00B: Selects CKm0 as operation clock of channel p.
10B: Selects CKm1 as operation clock of channel p.
* Make the same setting as master channel.
(b) Timer output register m (TOm)
Bit p
TOm
TOmp
0: Outputs 0 from TOmp.
1/0
1: Outputs 1 from TOmp.
(c) Timer output enable register m (TOEm)
Bit p
TOEm
TOEmp
1/0
0: Stops the TOmp output operation by counting operation.
1: Enables the TOmp output operation by counting operation.
(d) Timer output level register m (TOLm)
Bit p
TOLm
TOLmp
0: Positive logic output (active-high)
1/0
1: Negative logic output (active-low)
(e) Timer output mode register m (TOMm)
Bit p
TOMm
TOMmp
1: Sets the slave channel output mode.
1
Note TMRm2: MASTERmp bit
TMRm1, TMRm3: SPLITmp bit
Remark
m: Unit number (m = 0, 1), n: Channel number (n = 0, 2)
p: Slave channel number (n = 0: p = 1, 2, 3, n = 2: p = 3)
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Figure 6-65. Operation Procedure of One-Shot Pulse Output Function (1/2)
Software Operation
Hardware Status
Power-off status
TAU
default
(Clock supply is stopped and writing to each register is
setting
disabled.)
Sets the TAUmEN bit of peripheral enable registers 0
(PER0) to 1.
Power-on status. Each channel stops operating.
(Clock supply is started and writing to each register is
enabled.)
Sets timer clock select register m (TPSm).
Determines clock frequencies of CKm0 and CKm1.
Channel
Sets timer mode register mn, mp (TMRmn, TMRmp) of
Channel stops operating.
default
two channels to be used (determines operation mode of
(Clock is supplied and some power is consumed.)
setting
channels).
An output delay is set to timer data register mn (TDRmn)
of the master channel, and a pulse width is set to the
TDRmp register of the slave channel.
Sets slave channel.
The TOmp pin goes into Hi-Z output state.
The TOMmp bit of timer output mode register m
(TOMm) is set to 1 (slave channel output mode).
Sets the TOLmp bit.
Sets the TOmp bit and determines default level of the
TOmp output.
The TOmp default setting level is output when the port
mode register is in output mode and the port register is 0.
Sets the TOEmp bit to 1 and enables operation of TOmp.
TOmp does not change because channel stops operating.
Clears the port register and port mode register to 0.
The TOmp pin outputs the TOmp set level.
(Remark is listed on the next page.)
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Figure 6-65. Operation Procedure of One-Shot Pulse Output Function (2/2)
Software Operation
Sets the TOEmp bit (slave) to 1 (only when operation is
resumed).
The TSmn (master) and TSmp (slave) bits of timer
channel start register m (TSm) are set to 1 at the same
time.
The TSmn and TSmp bits automatically return to 0
because they are trigger bits.
The TEmn and TEmp bits are set to 1 and the master
channel enters the TImn input edge detection wait status.
Counter stops operating.
Detects the TImn pin input valid edge of master channel.
Master channel starts counting.
During
operation
Set values of only the CISmn1 and CISmn0 bits of the
TMRmn register can be changed.
Set values of the TMRmp, TDRmn, TDRmp registers,
TOMmn, TOMmp, TOLmn, and TOLmp bits cannot be
changed.
The TCRmn and TCRmp registers can always be read.
The TSRmn and TSRmp registers are not used.
Set values of the TOm and TOEm registers can be
changed.
Master channel loads the value of the TDRmn register to
timer count register mn (TCRmn) when the TImn pin valid
input edge is detected, and the counter starts counting
down. When the count value reaches TCRmn = 0000H,
the INTTMmn output is generated, and the counter stops
until the next valid edge is input to the TImn pin.
The slave channel, triggered by INTTMmn of the master
channel, loads the value of the TDRmp register to the
TCRmp register, and the counter starts counting down.
The output level of TOmp becomes active one count clock
after generation of INTTMmn from the master channel. It
becomes inactive when TCRmp = 0000H, and the
counting operation is stopped.
After that, the above operation is repeated.
Operation
stop
The TTmn (master) and TTmp (slave) bits are set to 1 at
the same time.
The TTmn and TTmp bits automatically return to 0
because they are trigger bits.
Operation is resumed.
Operation
start
Hardware Status
TAU
stop
TEmn, TEmp = 0, and count operation stops.
The TCRmn and TCRmp registers hold count value and
stop.
The TOmp output is not initialized but holds current
status.
The TOEmp bit of slave channel is cleared to 0 and
value is set to the TOmp bit.
The TOmp pin outputs the TOmp set level.
To hold the TOmp pin output level
Clears the TOmp bit to 0 after the value to
be held is set to the port register.
The TOmp pin output level is held by port function.
When holding the TOmp pin output level is not
necessary
Setting not required.
The TAUmEN bit of the PER0 register is cleared to 0.
Power-off status
All circuits are initialized and SFR of each channel is
also initialized.
(The TOmp bit is cleared to 0 and the TOmp pin is set to
port mode.)
Remark m: Unit number (m = 0, 1), n: Channel number (n = 0, 2)
p: Slave channel number (n = 0: p = 1, 2, 3, n = 2: p = 3)
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6.8.2 Operation as PWM function
Two channels can be used as a set to generate a pulse of any period and duty factor.
The period and duty factor of the output pulse can be calculated by the following expressions.
Pulse period = {Set value of TDRmn (master) + 1} × Count clock period
Duty factor [%] = {Set value of TDRmp (slave)}/{Set value of TDRmn (master) + 1} × 100
0% output:
Set value of TDRmp (slave) = 0000H
100% output: Set value of TDRmp (slave) ≥ {Set value of TDRmn (master) + 1}
Remark
The duty factor exceeds 100% if the set value of TDRmp (slave) > (set value of TDRmn (master) + 1), it
summarizes to 100% output.
The master channel operates in the interval timer mode. If the channel start trigger bit (TSmn) of timer channel start
register m (TSm) is set to 1, an interrupt (INTTMmn) is output, the value set to timer data register mn (TDRmn) is loaded
to timer count register mn (TCRmn), and the counter counts down in synchronization with the count clock. When the
counter reaches 0000H, INTTMmn is output, the value of the TDRmn register is loaded again to the TCRmn register, and
the counter counts down. This operation is repeated until the channel stop trigger bit (TTmn) of timer channel stop
register m (TTm) is set to 1.
If two channels are used to output a PWM waveform, the period until the master channel counts down to 0000H is the
PWM output (TOmp) cycle.
The slave channel operates in one-count mode. By using INTTMmn from the master channel as a start trigger, the
TCRmp register loads the value of the TDRmp register and the counter counts down to 0000H. When the counter
reaches 0000H, it outputs INTTMmp and waits until the next start trigger (INTTMmn from the master channel) is generated.
If two channels are used to output a PWM waveform, the period until the slave channel counts down to 0000H is the
PWM output (TOmp) duty.
PWM output (TOmp) goes to the active level one clock after the master channel generates INTTMmn and goes to the
inactive level when the TCRmp register of the slave channel becomes 0000H.
Caution
To rewrite both timer data register mn (TDRmn) of the master channel and the TDRmp register of the
slave channel, a write access is necessary two times. The timing at which the values of the TDRmn
and TDRmp registers are loaded to the TCRmn and TCRmp registers is upon occurrence of INTTMmn
of the master channel.
Thus, when rewriting is performed split before and after occurrence of
INTTMmn of the master channel, the TOmp pin cannot output the expected waveform. To rewrite both
the TDRmn register of the master and the TDRmp register of the slave, therefore, be sure to rewrite
both the registers immediately after INTTMmn is generated from the master channel.
Remark
m: Unit number (m = 0, 1), n: Channel number (n = 0, 2)
p: Slave channel number (n = 0: p = 1, 2, 3, n = 2: p = 3)
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CKm1
Operation clock
CKm0
TSmn
Trigger selection
Master channel
(interval timer mode)
Clock selection
Figure 6-66. Block Diagram of Operation as PWM Function
Timer counter
register mn (TCRmn)
Timer data
register mn (TDRmn)
Interrupt
controller
Timer counter
register mp (TCRmp)
Output
controller
Timer data
register mp (TDRmp)
Interrupt
controller
Interrupt signal
(INTTMmn)
CKm1
Operation clock
Trigger selection
CKm0
Clock selection
Slave channel
(one-count mode)
Remark
TOmp pin
Interrupt signal
(INTTMmp)
m: Unit number (m = 0, 1), n: Channel number (n = 0, 2)
p: Slave channel number (n = 0: p = 1, 2, 3, n = 2: p = 3)
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Figure 6-67. Example of Basic Timing of Operation as PWM Function
TSmn
TEmn
FFFFH
Master
channel
TCRmn
0000H
TDRmn
a
b
TOmn
INTTMmn
TSmp
TEmp
FFFFH
TCRmp
Slave
channel
0000H
TDRmp
c
d
TOmp
INTTMmp
a+1
c
a+1
c
b+1
d
Remarks 1. m: Unit number (m = 0, 1), n: Channel number (n = 0, 2)
p: Slave channel number (n = 0: p = 1, 2, 3, n = 2: p = 3)
2. TSmn, TSmp:
TEmn, TEmp:
Bit n, p of timer channel start register m (TSm)
Bit n, p of timer channel enable status register m (TEm)
TCRmn, TCRmp: Timer count registers mn, mp (TCRmn, TCRmp)
TDRmn, TDRmp: Timer data registers mn, mp (TDRmn, TDRmp)
TOmn, TOmp:
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Figure 6-68. Example of Set Contents of Registers When PWM Function (Master Channel) Is Used
(a) Timer mode register mn (TMRmn)
15
TMRmn
14
13
0
11
10
9
8
7
6
5
4
0
0
MAS
CCSmn
STSmn2 STSmn1 STSmn0 CISmn1 CISmn0
TERmn
CKSmn1 CKSmn0
1/0
12
0
0
1
0
0
0
0
3
2
1
0
MDmn3 MDmn2 MDmn1 MDmn0
0
0
0
0
1
Operation mode of channel n
000B: Interval timer
Setting of operation when counting is started
1: Generates INTTMmn when counting is
started.
Selection of TImn pin input edge
00B: Sets 00B because these are not used.
Start trigger selection
000B: Selects only software start.
Slave/master selection
1: Master channel.
Count clock selection
0: Selects operation clock (fMCK).
Operation clock (fMCK) selection
00B: Selects CKm0 as operation clock of channel n.
10B: Selects CKm1 as operation clock of channel n.
(b) Timer output register m (TOm)
Bit n
TOm
TOmn
0: Outputs 0 from TOmn.
0
(c) Timer output enable register m (TOEm)
Bit n
TOEm
TOEmn
0: Stops the TOmn output operation by counting operation.
0
(d) Timer output level register m (TOLm)
Bit n
TOLm
TOLmn
0: Cleared to 0 when TOMmn = 0 (master channel output mode).
0
(e) Timer output mode register m (TOMm)
Bit n
TOMm
TOMmn
0: Sets master channel output mode.
0
Remark
m: Unit number (m = 0, 1), n: Channel number (n = 0, 2)
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Figure 6-69. Example of Set Contents of Registers When PWM Function (Slave Channel) Is Used
(a) Timer mode register mp (TMRmp)
15
TMRmp
14
13
CKSmp1 CKSmp0
1/0
0
12
11
CCSmp M/S
0
0
Note
0
10
9
8
7
6
5
4
0
0
STSmp2 STSmp1 STSmp0 CISmp1 CISmp0
1
0
0
0
3
2
1
0
MDmp3 MDmp2 MDmp1 MDmp0
0
1
0
0
1
Operation mode of channel p
100B: One-count mode
Start trigger during operation
1: Trigger input is valid.
Selection of TImp pin input edge
00B: Sets 00B because these are not used.
Start trigger selection
100B: Selects INTTMmn of master channel.
Setting of MASTERmp or SPLITmp bit
0: Slave channel.
Count clock selection
0: Selects operation clock (fMCK).
Operation clock (fMCK) selection
00B: Selects CKm0 as operation clock of channel p.
10B: Selects CKm1 as operation clock of channel p.
* Make the same setting as master channel.
(b) Timer output register m (TOm)
Bit p
TOm
TOmp
0: Outputs 0 from TOmp.
1/0
1: Outputs 1 from TOmp.
(c) Timer output enable register m (TOEm)
Bit p
TOEm
TOEmp
1/0
0: Stops the TOmp output operation by counting operation.
1: Enables the TOmp output operation by counting operation.
(d) Timer output level register m (TOLm)
Bit p
TOLm
TOLmp
0: Positive logic output (active-high)
1/0
1: Negative logic output (active-low)
(e) Timer output mode register m (TOMm)
Bit p
TOMm
TOMmp
1: Sets the slave channel output mode.
1
Note TMRm2: MASTERmp bit
TMRm1, TMRm3: SPLITmp bit
Remark
m: Unit number (m = 0, 1), n: Channel number (n = 0, 2)
p: Slave channel number (n = 0: p = 1, 2, 3, n = 2: p = 3)
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Figure 6-70. Operation Procedure When PWM Function Is Used (1/2)
Software Operation
Hardware Status
Power-off status
TAU
default
(Clock supply is stopped and writing to each register is
setting
disabled.)
Sets the TAUmEN bit of peripheral enable register 0
(PER0) to 1.
Power-on status. Each channel stops operating.
(Clock supply is started and writing to each register is
enabled.)
Sets timer clock select register m (TPSm).
Determines clock frequencies of CKm0 and CKm1.
Channel
Sets timer mode registers mn, mp (TMRmn, TMRmp) of
Channel stops operating.
default
two channels to be used (determines operation mode of
(Clock is supplied and some power is consumed.)
setting
channels).
An interval (period) value is set to timer data register mn
(TDRmn) of the master channel, and a duty factor is set
to the TDRmp register of the slave channel.
Sets slave channel.
The TOmp pin goes into Hi-Z output state.
The TOMmp bit of timer output mode register m
(TOMm) is set to 1 (slave channel output mode).
Sets the TOLmp bit.
Sets the TOmp bit and determines default level of the
TOmp output.
The TOmp default setting level is output when the port
mode register is in output mode and the port register is 0.
Sets the TOEmp bit to 1 and enables operation of TOmp.
TOmp does not change because channel stops operating.
Clears the port register and port mode register to 0.
The TOmp pin outputs the TOmp set level.
(Remark is listed on the next page.)
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Figure 6-70. Operation Procedure When PWM Function Is Used (2/2)
Software Operation
Operation
Sets the TOEmp bit (slave) to 1 (only when operation is
start
resumed).
Hardware Status
The TSmn (master) and TSmp (slave) bits of timer
channel start register m (TSm) are set to 1 at the same
TEmn = 1, TEmp = 1
When the master channel starts counting, INTTMmn is
time.
The TSmn and TSmp bits automatically return to 0
generated. Triggered by this interrupt, the slave
because they are trigger bits.
channel also starts counting.
Set values of the TMRmn and TMRmp registers,
The counter of the master channel loads the TDRmn
operation
TOMmn, TOMmp, TOLmn, and TOLmp bits cannot be
register value to timer count register mn (TCRmn), and
changed.
counts down. When the count value reaches TCRmn =
Set values of the TDRmn and TDRmp registers can be
0000H, INTTMmn output is generated. At the same time,
changed after INTTMmn of the master channel is
the value of the TDRmn register is loaded to the TCRmn
generated.
register, and the counter starts counting down again.
The TCRmn and TCRmp registers can always be read.
At the slave channel, the value of the TDRmp register is
The TSRmn and TSRmp registers are not used.
loaded to the TCRmp register, triggered by INTTMmn of
Operation is resumed.
During
the master channel, and the counter starts counting down.
The output level of TOmp becomes active one count clock
after generation of the INTTMmn output from the master
channel. It becomes inactive when TCRmp = 0000H, and
the counting operation is stopped.
After that, the above operation is repeated.
Operation
The TTmn (master) and TTmp (slave) bits are set to 1 at
stop
the same time.
TEmn, TEmp = 0, and count operation stops.
The TTmn and TTmp bits automatically return to 0
The TCRmn and TCRmp registers hold count value and
because they are trigger bits.
stop.
The TOmp output is not initialized but holds current
status.
The TOEmp bit of slave channel is cleared to 0 and value
is set to the TOmp bit.
TAU
stop
The TOmp pin outputs the TOmp set level.
To hold the TOmp pin output level
Clears the TOmp bit to 0 after the value to
The TOmp pin output level is held by port function.
be held is set to the port register.
When holding the TOmp pin output level is not
necessary
Setting not required.
The TAUmEN bit of the PER0 register is cleared to 0.
Power-off status
All circuits are initialized and SFR of each channel is
also initialized.
(The TOmp bit is cleared to 0 and the TOmp pin is set
to port mode.)
Remark m: Unit number (m = 0, 1), n: Channel number (n = 0, 2)
p: Slave channel number (n = 0: p = 1, 2, 3, n = 2: p = 3)
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6.8.3 Operation as multiple PWM output function
By extending the PWM function and using multiple slave channels, many PWM waveforms with different duty values
can be output.
For example, when using two slave channels, the period and duty factor of an output pulse can be calculated by the
following expressions.
Pulse period = {Set value of TDRmn (master) + 1} × Count clock period
Duty factor 1 [%] = {Set value of TDRmp (slave 1)}/{Set value of TDRmn (master) + 1} × 100
Duty factor 2 [%] = {Set value of TDRmq (slave 2)}/{Set value of TDRmn (master) + 1} × 100
Remark
Although the duty factor exceeds 100% if the set value of TDRmp (slave 1) > {set value of TDRmn
(master) + 1} or if the {set value of TDRmq (slave 2)} > {set value of TDRmn (master) + 1}, it is
summarized into 100% output.
Timer count register mn (TCRmn) of the master channel operates in the interval timer mode and counts the periods.
The TCRmp register of the slave channel 1 operates in one-count mode, counts the duty factor, and outputs a PWM
waveform from the TOmp pin. The TCRmp register loads the value of timer data register mp (TDRmp), using INTTMmn of
the master channel as a start trigger, and starts counting down. When TCRmp = 0000H, TCRmp outputs INTTMmp and
stops counting until the next start trigger (INTTMmn of the master channel) has been input. The output level of TOmp
becomes active one count clock after generation of INTTMmn from the master channel, and inactive when TCRmp =
0000H.
In the same way as the TCRmp register of the slave channel 1, the TCRmq register of the slave channel 2 operates in
one-count mode, counts the duty factor, and outputs a PWM waveform from the TOmq pin. The TCRmq register loads the
value of the TDRmq register, using INTTMmn of the master channel as a start trigger, and starts counting down. When
TCRmq = 0000H, the TCRmq register outputs INTTMmq and stops counting until the next start trigger (INTTMmn of the
master channel) has been input. The output level of TOmq becomes active one count clock after generation of INTTMmn
from the master channel, and inactive when TCRmq = 0000H.
When channel 0 is used as the master channel as above, up to three types of PWM signals can be output at the same
time.
Caution To rewrite both timer data register mn (TDRmn) of the master channel and the TDRmp register of the
slave channel 1, write access is necessary at least twice. Since the values of the TDRmn and TDRmp
registers are loaded to the TCRmn and TCRmp registers after INTTMmn is generated from the master
channel, if rewriting is performed separately before and after generation of INTTMmn from the master
channel, the TOmp pin cannot output the expected waveform. To rewrite both the TDRmn register of
the master and the TDRmp register of the slave, be sure to rewrite both the registers immediately
after INTTMmn is generated from the master channel (This applies also to the TDRmq register of the
slave channel 2).
Remark
m: Unit number (m = 0, 1), n: Channel number (n = 0)
p: Slave channel number 1, q: Slave channel number 2
n < p < q ≤ 3 (Where p and q are consecutive integers greater than n)
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CKm1
Operation clock
CKm0
TSmn
Trigger selection
Master channel
(interval timer mode)
Clock selection
Figure 6-71. Block Diagram of Operation as Multiple PWM Output Function (output two types of PWMs)
Timer counter
register mn (TCRmn)
Timer data
register mn (TDRmn)
Interrupt
controller
Timer counter
register mp (TCRmp)
Output
controller
Timer data
register mp (TDRmp)
Interrupt
controller
Timer counter
register mq (TCRmq)
Output
controller
Timer data
register mq (TDRmq)
Interrupt
controller
Interrupt signal
(INTTMmn)
Operation clock
CKm1
Trigger selection
CKm0
Clock selection
Slave channel 1
(one-count mode)
TOmp pin
Interrupt signal
(INTTMmp)
CKm1
Operation clock
Trigger selection
CKm0
Clock selection
Slave channel 2
(one-count mode)
Remark
TOmq pin
Interrupt signal
(INTTMmq)
m: Unit number (m = 0, 1), n: Channel number (n = 0)
p: Slave channel number 1, q: Slave channel number 2
n < p < q ≤ 3 (Where p and q are consecutive integers greater than n)
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Figure 6-72. Example of Basic Timing of Operation as Multiple PWM Output Function
(Output two types of PWMs) (1/2)
TSmn
TEmn
FFFFH
Master
channel
TCRmn
0000H
TDRmn
a
b
TOmn
INTTMmn
TSmp
TEmp
FFFFH
Slave
channel 1
TCRmp
0000H
TDRmp
c
d
TOmp
INTTMmp
a+1
a+1
c
c
b+1
d
d
TSmq
TEmq
FFFFH
Slave
channel 2
TCRmq
0000H
TDRmq
e
f
TOmq
INTTMmq
a+1
e
a+1
e
b+1
f
f
(Remark is listed on the next page.)
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Figure 6-72. Example of Basic Timing of Operation as Multiple PWM Output Function
(Output two types of PWMs) (2/2)
Remarks 1. m: Unit number (m = 0, 1), n: Channel number (n = 0)
p: Slave channel number 1, q: Slave channel number 2
n < p < q ≤ 3 (Where p and q are consecutive integers greater than n)
2. TSmn, TSmp, TSmq:
TEmn, TEmp, TEmq:
Bit n, p, q of timer channel start register m (TSm)
Bit n, p, q of timer channel enable status register m (TEm)
TCRmn, TCRmp, TCRmq:
Timer count registers mn, mp, mq (TCRmn, TCRmp, TCRmq)
TDRmn, TDRmp, TDRmq:
Timer data registers mn, mp, mq (TDRmn, TDRmp, TDRmq)
TOmn, TOmp, TOmq:
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Figure 6-73. Example of Set Contents of Registers
When Multiple PWM Output Function (Master Channel) Is Used
(a) Timer mode register mn (TMRmn)
15
TMRmn
14
13
0
11
10
9
8
7
6
5
4
0
0
MAS
CCSmn
STSmn2 STSmn1 STSmn0 CISmn1 CISmn0
TERmn
CKSmn1 CKSmn0
1/0
12
0
0
1
0
0
0
0
3
2
1
0
MDmn3 MDmn2 MDmn1 MDmn0
0
0
0
0
1
Operation mode of channel n
000B: Interval timer
Setting of operation when counting is started
1: Generates INTTMmn when counting is
started.
Selection of TImn pin input edge
00B: Sets 00B because these are not used.
Start trigger selection
000B: Selects only software start.
Slave/master selection
1: Master channel.
Count clock selection
0: Selects operation clock (fMCK).
Operation clock (fMCK) selection
00B: Selects CKm0 as operation clock of channel n.
10B: Selects CKm1 as operation clock of channel n.
(b) Timer output register m (TOm)
Bit n
TOm
TOmn
0: Outputs 0 from TOmn.
0
(c) Timer output enable register m (TOEm)
Bit n
TOEm
TOEmn
0: Stops the TOmn output operation by counting operation.
0
(d) Timer output level register m (TOLm)
Bit n
TOLm
TOLmn
0: Cleared to 0 when TOMmn = 0 (master channel output mode).
0
(e) Timer output mode register m (TOMm)
Bit n
TOMm
TOMmn
0: Sets master channel output mode.
0
Remark
m: Unit number (m = 0, 1), n: Channel number (n = 0)
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Figure 6-74. Example of Set Contents of Registers
When Multiple PWM Output Function (Slave Channel) Is Used (output two types of PWMs)
(a) Timer mode register mp, mq (TMRmp, TMRmq)
15
TMRmp
TMRmq
14
13
CKSmp1 CKSmp0
0
0
15
14
13
CKSmq1 CKSmq0
0
11
CCSmp M/S
1/0
1/0
12
0
0
12
11
CCSmq M/S
0
Note
0
Note
0
10
9
8
7
6
5
4
STSmp2 STSmp1 STSmp0 CISmp1 CISmp0
0
0
0
0
0
0
10
9
8
7
6
5
4
STSmq2 STSmq1 STSmq0 CISmq1 CISmq0
0
0
0
0
2
1
0
MDmp3 MDmp2 MDmp1 MDmp0
1
1
3
1
0
0
1
3
2
1
0
MDmq3 MDmq2 MDmq1 MDmq0
0
0
1
0
0
1
Operation mode of channel p, q
100B: One-count mode
Start trigger during operation
1: Trigger input is valid.
Selection of TImp and TImq pins input edge
00B: Sets 00B because these are not used.
Start trigger selection
100B: Selects INTTMmn of master channel.
Setting of MASTERmp, MASTERmq or SPLITmp, SPLITmq bit
0: Slave channel.
Count clock selection
0: Selects operation clock (fMCK).
Operation clock (fMCK) selection
00B: Selects CKm0 as operation clock of channel p, q.
10B: Selects CKm1 as operation clock of channel p, q.
* Make the same setting as master channel.
(b) Timer output register m (TOm)
TOm
Bit q
Bit p
TOmq
TOmp
1/0
1/0
0: Outputs 0 from TOmp or TOmq.
1: Outputs 1 from TOmp or TOmq.
(c) Timer output enable register m (TOEm)
Bit q
TOEm
Bit p
TOEmq TOEmp
1/0
1/0
0: Stops the TOmp or TOmq output operation by counting operation.
1: Enables the TOmp or TOmq output operation by counting operation.
(d) Timer output level register m (TOLm)
Bit q
TOLm
Bit p
TOLmq TOLmp
1/0
1/0
0: Positive logic output (active-high)
1: Negative logic output (active-low)
(e) Timer output mode register m (TOMm)
Bit q
TOMm
Bit p
TOMmq TOMmp
1
1: Sets the slave channel output mode.
1
Note TMRm2: MASTERmp, MASTERmq bit
TMRm1, TMRm3: SPLITmp, SPLITmq bit
Remark
m: Unit number (m = 0, 1), n: Channel number (n = 0)
p: Slave channel number 1, q: Slave channel number 2
n < p < q ≤ 3 (Where p and q are consecutive integers greater than n)
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Figure 6-75. Operation Procedure When Multiple PWM Output Function Is Used (output two types of PWMs)
(1/2)
Software Operation
Hardware Status
Power-off status
TAU
default
(Clock supply is stopped and writing to each register is
setting
disabled.)
Sets the TAUmEN bit of peripheral enable register 0
(PER0) to 1.
Power-on status. Each channel stops operating.
(Clock supply is started and writing to each register is
enabled.)
Sets timer clock select register m (TPSm).
Determines clock frequencies of CKm0 and CKm1.
Channel
Sets timer mode registers mn, mp, mq (TMRmn,
Channel stops operating.
default
TMRmp, TMRmq) of each channel to be used
(Clock is supplied and some power is consumed.)
setting
(determines operation mode of channels).
An interval (period) value is set to timer data register mn
(TDRmn) of the master channel, and a duty factor is set
to the TDRmp and TDRmq registers of the slave
channels.
Sets slave channels.
The TOmp and TOmq pins go into Hi-Z output state.
The TOMmp and TOMmq bits of timer output mode
register m (TOMm) are set to 1 (slave channel output
mode).
Clears the TOLmp and TOLmq bits to 0.
Sets the TOmp and TOmq bits and determines default
level of the TOmp and TOmq outputs.
The TOmp and TOmq default setting levels are output
when the port mode register is in output mode and the port
register is 0.
Sets the TOEmp and TOEmq bits to 1 and enables
operation of TOmp and TOmq.
TOmp and TOmq do not change because channels stop
operating.
Clears the port register and port mode register to 0.
The TOmp and TOmq pins output the TOmp and TOmq
set levels.
(Remark is listed on the next page.)
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Figure 6-75. Operation Procedure When Multiple PWM Output Function Is Used (output two types of PWMs)
(2/2)
Software Operation
Operation (Sets the TOEmp and TOEmq (slave) bits to 1 only when
resuming operation.)
start
The TSmn bit (master), and TSmp and TSmq (slave) bits
of timer channel start register m (TSm) are set to 1 at the
same time.
The TSmn, TSmp, and TSmq bits automatically return
to 0 because they are trigger bits.
Set values of the TMRmn, TMRmp, TMRmq registers,
TOMmn, TOMmp, TOMmq, TOLmn, TOLmp, and TOLmq
bits cannot be changed.
Set values of the TDRmn, TDRmp, and TDRmq registers
can be changed after INTTMmn of the master channel is
generated.
The TCRmn, TCRmp, and TCRmq registers can always
be read.
The TSRmn, TSRmp, and TSRmq registers are not used.
Operation
stop
The TTmn bit (master), TTmp, and TTmq (slave) bits are
set to 1 at the same time.
The TTmn, TTmp, and TTmq bits automatically return
to 0 because they are trigger bits.
Operation is resumed.
During
operation
The TOEmp and TOEmq bits of slave channels are
cleared to 0 and value is set to the TOmp and TOmq bits.
TAU
stop
To hold the TOmp and TOmq pin output levels
Clears the TOmp and TOmq bits to 0 after
the value to be held is set to the port register.
When holding the TOmp and TOmq pin output levels are
not necessary
Setting not required
The TAUmEN bit of the PER0 register is cleared to 0.
Remark
Hardware Status
TEmn = 1, TEmp, TEmq = 1
When the master channel starts counting, INTTMmn is
generated. Triggered by this interrupt, the slave
channel also starts counting.
The counter of the master channel loads the TDRmn
register value to timer count register mn (TCRmn) and
counts down. When the count value reaches TCRmn =
0000H, INTTMmn output is generated. At the same time,
the value of the TDRmn register is loaded to the TCRmn
register, and the counter starts counting down again.
At the slave channel 1, the values of the TDRmp register
are transferred to the TCRmp register, triggered by
INTTMmn of the master channel, and the counter starts
counting down. The output levels of TOmp become active
one count clock after generation of the INTTMmn output
from the master channel. It becomes inactive when
TCRmp = 0000H, and the counting operation is stopped.
At the slave channel 2, the values of the TDRmq register
are transferred to TCRmq regster, triggered by INTTMmn
of the master channel, and the counter starts counting
down. The output levels of TOmq become active one count
clock after generation of the INTTMmn output from the
master channel. It becomes inactive when TCRmq =
0000H, and the counting operation is stopped.
After that, the above operation is repeated.
TEmn, TEmp, TEmq = 0, and count operation stops.
The TCRmn, TCRmp, and TCRmq registers hold count
value and stop.
The TOmp and TOmq output are not initialized but hold
current status.
The TOmp and TOmq pins output the TOmp and TOmq
set levels.
The TOmp and TOmq pin output levels are held by port
function.
Power-off status
All circuits are initialized and SFR of each channel is
also initialized.
(The TOmp and TOmq bits are cleared to 0 and the
TOmp and TOmq pins are set to port mode.)
m: Unit number (m = 0, 1), n: Channel number (n = 0)
p: Slave channel number, q: Slave channel number
n < p < q ≤ 3 (Where p and q are a consecutive integer greater than n)
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<R> 6.9 Cautions When Using Timer Array Unit
6.9.1 Cautions When Using Timer output
Depends on products, a pin is assigned atimer output and other alternate functions. In this case, outputs of the other
alternate functions must be set in initial status.
(1) Using TO03 output assigned to the P31 for 30 to 44-pin products
So that the alternated PCLBUZ0 output becomes 0, not only set the port mode register (the PM31 bit) and the port
register (the P31 bit) to 0, but also use the bit 7 of the clock output select register 0 (CKS0) with the same setting
as the initial status.
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CHAPTER 7 TIMER RJ
Timer RJ is a 16-bit timer that can be used for pulse output, external pulse width or period measurement, and counting
external events.
7.1 Overview
This 16-bit timer consists of a reload register and a down counter. The reload register and the down counter are
allocated to the same address, and they can be accessed by accessing the TRJ0 register.
Table 7-1 lists the Timer RJ Specifications. Figure 7-1 shows the Timer RJ Block Diagram.
Table 7-1. Timer RJ Specifications
Item
Description
Operating
Timer mode
The count source is counted.
modes
Pulse output mode
The count source is counted and the output is inverted at each underflow of the
Event counter mode
An external event is counted.
timer.
Operation is possible in STOP mode.
Pulse width measurement
An external pulse width is measured.
mode
Pulse period measurement
An external pulse period is measured.
mode
Count source (Operating clock)
fCLK, fCLK/2, fCLK/8, fIL, fSUB, or event input from the event link controller (ELC)
selectable
Interrupt
• When the counter underflows.
• When the measurement of the active width of the external input (TRJIO0) is
completed in pulse width measurement mode.
• When the set edge of the external input (TRJIO0) is input in pulse period
measurement mode.
Selectable functions
• Coordination with the event link controller (ELC).
Event input from the ELC is selectable as a count source.
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Figure 7-1. Timer RJ Block Diagram
TCK2 to TCK0
= 000B
fCLK
fCLK/8
fCLK/2
Note 1
fIL
Event input from event link controller
(ELC)
fSUB
= 001B
= 011B
= 100B
= 101B
= 110B
Data bus
TIOGT1 and TIOGT0
= 00B
Event is always counted
= 01B
Event is counted during polarity period specified for INTP4 Note 2
= 10B
Note 2
Event is counted during polarity period specified for timer output signal
TIPF1 and TIPF0
= 01B
fCLK
= 10B
fCLK/8
= 11B
fCLK/32
TRDIOD1
TRDIOC1
TO02
TO03
= 00B
= 01B
= 10B
= 11B
TMOD2 to
TMOD0
= other than
010B
= 00B
TRJIO0 pin
TSTART
Underflow signal
RCCPSEL1 and
RCCPSEL0
16-bit counter
= 010B
TIPF1 and TIPF0
= 01B or 10B
Digital
filter
TRJ0
counter
Timer
RJ0
interrupt
TMOD2 to TMOD0
= 011B or 100B
One edge/
both edges
switching
Polarity
selection
TEDGPL
TEDGSEL
TMOD2 to TMOD0 = 001B
Counter
control
circuit
TEDGSEL = 1
Measurement
complete signal
Q
CK
Toggle flip-flop
TEDGSEL = 0
Q
TRJO0 pin
16-bit
reload
register
CLR
TOENA
Write to TRJMR0 register
Write 1 to TSTOP
TSTART, TSTOP: Bits in TRJCR0 register
TEDGSEL, TOENA, TIPF0, TIPF1, TIOGT0, TIOGT1: Bits in TRJIOC0 register
TMOD0 to TMOD2, TEDGPL, TCK0 to TCK2: Bits in TRJMR0 register
RCCPSEL0, RCCPSEL1: Bits in TRJISR0 register
<R>
Notes 1. When selecting fIL as the count source, set the WUTMMCK0 bit in the operation speed mode control register
(OSMC) to 1. However, fIL cannot be selected as the count source for timer RJ when fSUB is selected as the
count source for the 12-bit interval timer.
2. The polarity can be selected by the RCCPSEL2 bit in the TRJISR0 register.
7.2 I/O Pins
Table 7-2 lists the Timer RJ Pin Configuration.
Table 7-2. Timer RJ Pin Configuration
Pin Name
INTP4
I/O
Function
Input
External input for timer RJ
TRJIO0
Note
Input/output
External event input and pulse output for timer RJ
TRJO0
Note
Output
Pulse output for timer RJ
Note
The assignment of the TRJO0 pin is selected by bits PIOR12 and PIOR13 in the PIOR1 register. The
assignment of the TRJIO0 pin is selected by bits PIOR10 and PIOR11 in the PIOR1 register. Refer
to CHAPTER 4 PORT FUNCTIONS for details.
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7.3 Registers
Table 7-3 lists the Timer RJ Register Configuration.
Table 7-3. Timer RJ Register Configuration
Register Name
Symbol
After Reset
Address
Access Size
Peripheral I/O Redirection Register 1
PIOR1
00H
F0079H
8
Peripheral Enable Register 1
PER1
00H
F007AH
8
OSMC
00H
F00F3H
8
TRJ0
FFFFH
F0500H
16
Timer RJ Control Register 0
TRJCR0
00H
F0240H
8
Timer RJ I/O Control Register 0
TRJIOC0
00H
F0241H
8
Timer RJ Mode Register 0
TRJMR0
00H
F0242H
8
Timer RJ Event Pin Select Register 0
Operation speed mode control register
Timer RJ Counter Register 0
<R>
Note
TRJISR0
00H
F0243H
8
Port Register 0
P0
00H
FFF00H
8
Port Register 3
P3
00H
FFF03H
8
Port Register 4
P4
00H
FFF04H
8
Port Register 5
P5
00H
FFF05H
8
Port Mode Register 0
PM0
FFH
FFF20H
8
Port Mode Register 3
PM3
FFH
FFF23H
8
Port Mode Register 4
PM4
FFH
FFF24H
8
Port Mode Register 5
PM5
FFH
FFF25H
8
Note When the TRJ0 register is accessed, the CPU does not proceed to the next instruction processing but enters the
wait state for CPU processing. For this reason, if this wait state occurs, the number of instruction execution
clocks is increased by the number of wait clocks. The number of wait clocks for access to the TRJ0 register is
one clock for both writing and reading.
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7.3.1 Peripheral enable register 1 (PER1)
The PER1 register is used to enable or disable supplying the clock to the peripheral hardware. Clock supply to the
hardware that is not used is also stopped so as to decrease the power consumption and noise.
To use Timer RJ, be sure to set bit 0 (TRJ0EN) to 1.
The PER1 register can be set by a 1-bit or 8-bit memory manipulation instruction.
Reset signal generation clears this register to 00H.
Figure 7-2. Format of Peripheral Enable Register 1 (PER1)
Address: F007AH
Symbol
PER1
After reset: 00H
<7>
<6>
DACEN
Note
TRGEN
R/W
<5>
CMPEN
Note
TRJ0EN
<4>
<3>
2
1
<0>
TRD0EN
DTCEN
0
0
TRJ0EN
Control of timer RJ0 input clock supply
Stops input clock supply.
• SFR used by timer RJ0 cannot be written.
0
• Timer RJ0 is in the reset status.
Enables input clock supply.
• SFR used by timer RJ0 can be read and written.
1
Note
Only for products with 96 KB or more code flash memory.
Cautions 1. When setting timer RJ, be sure to set the TRJ0EN bit to 1 first. If TRJ0EN = 0, writing
to a control register of timer RJ is ignored, and all read values are default values
(except for port mode registers 0, 3, 4, 5 (PM0, PM3, PM4, PM5), and port registers 0,
3, 4, 5 (P0, P3, P4, P5)).
2. Be sure to set the following bits to 0:
Products with 64 KB or less code flash memory: bits 1, 2, 5, and 7
Products with 96 KB or more code flash memory: bits 1 and 2
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<R> 7.3.2 Operation Speed Mode Control Register (OSMC)
The WUTMMCK0 bit can be used to select the timer RJ operation clock.
In addition, by stopping clock functions that are unnecessary, the RTCLPC bit can be used to reduce power
consumption. For details about setting the RTCLPC bit, see CHAPTER 5 CLOCK GENERATOR.
The OSMC register can be set by an 8-bit memory manipulation instruction.
Reset signal generation clears this register to 00H.
Figure 7-3. Format of Operation Speed Mode Control Register (OSMC)
Address: F00F3H
After reset: 00H
R/W
Symbol
7
6
5
4
3
2
1
0
OSMC
RTCLPC
0
0
WUTMMCK0
0
0
0
0
WUTMMCK0
0
Selection of operation clock (fRTC) for real-time clock, 12-bit interval timer, and timer RJ
Subsystem clock (fSUB)
• The subsystem clock is selected as the operation clock for the real-time clock and the 12bit interval timer.
• The low-speed on-chip oscillator cannot be selected as the count source for timer RJ.
1
Low-speed on-chip oscillator clock (fIL)
• The low-speed on-chip oscillator clock is selected as the operation clock for the real-time
clock and the 12-bit interval timer.
• Either the low-speed on-chip oscillator or the subsystem clock can be selected as the
count source for timer RJ.
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7.3.3 Timer RJ Counter Register 0 (TRJ0), Timer RJ Reload Register
TRJ0 is a 16-bit register. The write value is written to the reload register and the read value is read from the counter.
The states of the reload register and the counter are changed depending on the TSTART bit in the TRJCR0 register.
For details, see 7. 4. 1 Reload Register and Counter Rewrite Operation.
Figure 7-4. Format of Timer RJ Counter Register 0 (TRJ0), Timer RJ Reload Register
Address : F0500H After Reset: FFFFH
Symbol
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
TRJ0
−
−
−
−
−
−
−
−
−
−
−
−
−
−
−
−
—
Function
16-bit counter and reload register
Bits
Notes 1, 2, 3
Setting Range
0000H to FFFFH
R/W
R/W
15 to 0
Notes 1. When 1 is written to the TSTOP bit in the TRJCR0 register, the 16-bit counter is forcibly stopped and set to
FFFFH.
2. The TRJ0 register must be accessed in 16-bit units. Do not access this register in 8-bit units.
3. When the setting of bits TCK2 to TCK0 in the TRJMR0 register is other than 001B (fCLK/8) or 011B (fCLK/2),
if the TRJ0 register is set to 0000H, a request signal to the data transfer controller (DTC) and the event link
<R>
controller (ELC) is generated only once immediately after the count starts. However, the TRJO0 and
TRJIO0 output is toggled.
When the TRJ0 register is set to 0000H in event counter mode, regardless of the value of bits TCK2 to
TCK0, a request signal to the DTC and the ELC is generated only once immediately after the count starts.
In addition, the TRJO0 output is toggled even during a period other than the specified count period.
When the TRJ0 register is set to 0000H or a higher value, a request signal is generated each time TRJ
underflows.
<R>
Caution When the TRJ0 register is accessed, the CPU does not proceed to the next instruction
processing but enters the wait state for CPU processing. For this reason, if this wait state
occurs, the number of instruction execution clocks is increased by the number of wait
clocks. The number of wait clocks for access to the TRJ0 register is one clock for both
writing and reading.
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7.3.4 Timer RJ Control Register 0 (TRJCR0)
Figure 7-5. Format of Timer RJ Control Register 0 (TRJCR0)
Address : F0240H After Reset: 00H
Symbol
7
6
5
4
3
2
1
0
TRJCR0
—
—
TUNDF
TEDGF
—
TSTOP
TCSTF
TSTART
Bits
Nothing is assigned
R/W
7 to 6
—
The write value must be 0. The read value is 0.
Timer RJ underflow flag
TUNDF
0
No underflow
1
Underflow
R
Note 1
R/W
R/W
[Condition for setting to 0]
• When 0 is written to this bit by a program.
[Condition for setting to 1]
• When the counter underflows.
Active edge judgement flag
TEDGF
0
No active edge received
1
Active edge received
Note 1
R/W
R/W
[Condition for setting to 0]
• When 0 is written to this bit by a program.
[Conditions for setting to 1]
• When the measurement of the active width of the external input (TRJIO) is completed in pulse
width measurement mode.
• The set edge of the external input (TRJIO) is input in pulse period measurement mode.
Bit 3
—
Nothing is assigned
R/W
The write value must be 0. The read value is 0.
Timer RJ count forced stop
TSTOP
R
Note 2
When 1 is written to this bit, the count is forcibly stopped. The read value is 0.
Timer RJ count status flag
TCSTF
0
Count stops
1
Count in progress
Note 3
R/W
W
R/W
R
[Conditions for setting to 0]
• When 0 is written to the TSTART bit (the TCSTF bit is set to 0 in synchronization with the count source).
• When 1 is written to the TSTOP bit.
[Condition for setting to 1]
• When 1 is written to the TSTART bit (the TCSTF bit is set to 1 in synchronization with the count source).
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Timer RJ count start
TSTART
0
Count stops
1
Count starts
Note 3
R/W
R/W
Count operation is started by writing 1 to the TSTART bit and stopped by writing 0. When the TSTART bit is
set to 1 (count starts), the TCSTF bit is set to 1 (count in progress) in synchronization with the count source.
Also, after 0 is written to the TSTART bit, the TCSTF bit is set to 0 (count stops) in synchronization with the
count source. For details, see 7. 5. 1 Count Operation Start and Stop Control.
Notes 1. The TRJCR0 register can be set by an 8-bit memory manipulation instruction.
2. When 1 (count is forcibly stopped) is written to the TSTOP bit, bits TSTART and TCSTF are initialized at the
same time. The pulse output level is also initialized.
3. For notes on using bits TSTART and TCSTF, see 7. 5. 1 Count Operation Start and Stop Control.
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7.3.5 Timer RJ I/O Control Register 0 (TRJIOC0)
Figure 7-6. Format of Timer RJ I/O Control Register 0 (TRJIOC0)
Address : F0241H After Reset: 00H
<R>
Symbol
7
6
5
4
3
2
1
0
TRJIOC0
TIOGT1
TIOGT0
TIPF1
TIPF0
—
TOENA
—
TEDGSEL
TRJIO count control
Notes 1, 2
TIOGT1
TIOGT0
0
0
Event is always counted
0
1
Event is counted during polarity period specified for INTP4
1
0
Event is counted during polarity period specified for timer output signal
1
1
Do not set.
R/W
R/W
Notes 1. When INTP4 or the timer output signal is used, the polarity to count an event can be selected by the
RCCPSEL2 bit in the TRJISR0 register.
2. Bits TIOGT0 and TIOGT1 are enabled only in event counter mode.
TIPF1
TIPF0
0
0
No filter
TRJIO input filter select
0
1
Filter sampled at fCLK
1
0
Filter sampled at fCLK/8
1
1
Filter sampled at fCLK/32
R/W
R/W
These bits are used to specify the sampling frequency of the filter for the TRJIO input. If the input to the
TRJIO0 pin is sampled and the value matches three successive times, that value is taken as the input value.
Bit 3
—
Nothing is assigned
The write value must be 0. The read value is 0.
TOENA
TRJO output enable
0
TRJO output disabled (port)
1
TRJO output enabled
Bit 1
—
R
R/W
R/W
Nothing is assigned
The write value must be 0. The read value is 0.
TEDGSEL
R/W
I/O polarity switch
Function varies depending on the operating mode (see Table 7-4 and Table 7-5). The TEDGSEL bit is used
R/W
R
R/W
R/W
to switch the TRJO output polarity and the TRJIO I/O edge and polarity. In pulse output mode, only the
inversion/non-inversion of toggle flip-flop is controlled. The toggle flip-flop is initialized when the TRJMR0
register is written or 1 is written to the TSTOP bit in the TRJCR0 register.
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Table 7-4. TRJIO I/O Edge and Polarity Switching
Operating Mode
Function
Timer mode
Not used (I/O port)
Pulse output mode
0: Output is started at high (Initialization level: High)
1: Output is started at low (Initialization level: Low)
Event counter mode
0: Count at rising edge
1: Count at falling edge
Pulse width measurement mode
0: Low-level width is measured
Pulse period measurement mode
0: Measure from one rising edge to the next rising edge
1: High-level width is measured
1: Measure from one falling edge to the next falling edge
Table 7-5. TRJO Output Polarity Switching
Operating Mode
All modes
Function
0: Output is started at low (Initialization level: Low)
1: Output is started at high (Initialization level: High)
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7.3.6 Timer RJ Mode Register 0 (TRJMR0)
Figure 7-7. Format of Timer RJ Mode Register 0 (TRJMR0)
Address : F0242H After Reset: 00H
Symbol
7
6
5
4
3
2
1
0
TRJMR0
—
TCK2
TCK1
TCK0
TEDGPL
TMOD2
TMOD1
TMOD0
Bit 7
Nothing is assigned
—
R/W
The write value must be 0. The read value is 0.
R
Timer RJ count source select
TCK2
TCK1
TCK0
0
0
0
fCLK
0
0
1
fCLK/8
0
1
1
fCLK/2
1
0
0
fIL
1
0
1
Event input from event link controller (ELC)
1
1
0
fSUB
Other than above
R/W
Setting prohibited
TRJIO edge polarity select
One edge
1
Both edges
R/W
Note 4
TEDGPL
0
Notes 1, 2
Note 5
R/W
R/W
Timer RJ operating mode select
TMOD2
TMOD1
TMOD0
0
0
0
Timer mode
0
0
1
Pulse output mode
0
1
0
Event counter mode
0
1
1
Pulse width measurement mode
1
0
0
Pulse period measurement mode
Other than above
Note 3
R/W
R/W
Setting prohibited
Notes 1. When event counter mode is selected, the external input (TRJIO) is selected as the count source regardless
of the setting of bits TCK0 to TCK2.
2. Do not switch count sources during count operation. Count sources should be switched when both the
TSTART and TCSTF bits in the TRJCR0 register are set to 0 (count stops).
3. The operating mode can be changed only when the count is stopped while both the bits TSTART and TCSTF
in the TRJCR0 register are set to 0 (count stops). Do not change the operating mode during count operation.
<R>
4. When selecting fIL as the count source, set the WUTMMCK0 bit in the operation speed mode register
(OSMC) to 1.
However, fIL cannot be selected as the count source for timer RJ when fSUB is selected as the count source for
the real-time clock or the 12-bit interval timer.
<R>
5. The TEDGPL bit is enabled only in event counter mode.
<R>
6. Write access to the TRJMR0 register initializes the output from pins TRJO0 and TRJIO0 of timer RJ.
For details on the output level at initialization, refer to the description shown below Figure 7-6 Format of
Timer RJ I/O control register 0 (TRJIOC0).
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7.3.7 Timer RJ Event Pin Select Register 0 (TRJISR0)
Figure 7-8. Format of Timer RJ Event Pin Select Register 0 (TRJISR0)
Address : F0243H After Reset: 00H
Symbol
7
6
5
4
3
2
1
0
TRJISR0
—
—
—
—
—
RCCPSEL2
RCCPSEL1
RCCPSEL0
Note
Note
Note
Bit 7 to
Nothing is assigned
R/W
3
—
The write value must be 0. The read value is 0.
RCCPS
Timer output signal and INTP4 polarity selection
R
R/W
EL2
<R>
0
An event is counted during the low-level period
1
An event is counted during the high-level period
RCCPS
RCCPS
EL1
EL0
Timer output signal selection
0
0
TRDIOD1
0
1
TRDIOC1
1
0
TO02
1
1
TO03
R/W
R/W
R/W
Note Bits RCCPSEL0 to RCCPSEL2 are enabled only in event counter mode.
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7.3.8 Port mode registers 0, 3, 4, 5 (PM0, PM3, PM4, PM5)
These registers set input/output of ports 0, 3, 4, 5 in 1-bit units.
When using the ports (P01/TRJIO0, P30/TRJO0, etc.) to be shared with the timer output pin for timer output, set the
port mode register (PMxx) bit and port register (Pxx) bit corresponding to each port to 0.
Example: When using P01/TRJIO0 for timer output
Set the PM01 bit of port mode register 0 to 0.
Set the P01 bit of port register 0 to 0.
When using the ports (P01/TRJIO0, etc.) to be shared with the timer input pin for timer input, set the port mode register
(PMxx) bit corresponding to each port to 1. At this time, the port register (Pxx) bit may be 0 or 1.
Example: When using P01/TRJIO0 for timer input
Set the PM01 bit of port mode register 0 to 1.
Set the P01 bit of port register 0 to 0 or 1.
The PM0, PM3, PM4, PM5 registers can be set by a 1-bit or 8-bit memory manipulation instruction.
Reset signal generation sets these registers to FFH.
Figure 7-9. Format of Port Mode Registers 0, 3, 4, 5 (PM0, PM3, PM4, PM5) (100-pin products)
Address: FFF20H
After reset: FFH
R/W
Symbol
7
6
5
4
3
2
1
0
PM0
1
PM06
PM05
PM04
PM03
PM02
PM01
PM00
Address: FFF23H
After reset: FFH
R/W
Symbol
7
6
5
4
3
2
1
0
PM3
1
1
1
1
1
1
PM31
PM30
Address: FFF24H
After reset: FFH
R/W
Symbol
7
6
5
4
3
2
1
0
PM4
PM47
PM46
PM45
PM44
PM43
PM42
PM41
PM40
Address: FFF25H
After reset: FFH
R/W
Symbol
7
6
5
4
3
2
1
0
PM5
PM57
PM56
PM55
PM54
PM53
PM52
PM51
PM50
Pmn pin I/O mode selection
PMmn
(m = 0, 3, 4, 5; n = 0 to 7)
Remark
0
Output mode (output buffer on)
1
Input mode (output buffer off)
The figure shown above presents the format of port mode registers 0, 3, 4, and 5 of the 100-pin products. The
format of the port mode register of other products, see Table 4-5. or Table 4-6. PMxx, Pxx, PUxx, PIMxx,
POMxx, PMCxx registers and the bits mounted on each product.
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7.4 Operation
7.4.1 Reload Register and Counter Rewrite Operation
Regardless of the operating mode, the timing of the rewrite operation to the reload register and the counter differs
depending on the value in the TSTART bit in the TRJCR0 register. When the TSTART bit is 0 (count stops), the count value
is directly written to the reload register and the counter. When the TSTART bit is 1 (count starts), the value is written to the
reload register in synchronization with the count source, and then to the counter in synchronization with the next count
source.
Figure 7-10 shows the Timing of Rewrite Operation with TSTART Bit Value.
Figure 7-10. Timing of Rewrite Operation with TSTART Bit Value
Write 1 to TSTART bit in TRJCR0 register by a program
Write 1234H to TRJ0 register by a program
Write 5678H to TRJ0 register by a program
Register write clock
Count source
TSTART bit in TRJCR0
register
TRJ0 register
FFFFH
5678H
1234H
Reload register load signal
Reload register load clock
Counter load signal
Counter load clock
Reload register
FFFFH
Timer RJ0 counter
FFFFH
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5678H
1234H
5677H 5676H 5675H 5674H 5673H 5672H 5671H 5670H566FH1234H 1233H 1232H 1231H1230H
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7.4.2 Timer Mode
In this mode, the counter is decremented by the count source selected by bits TCK0 to TCK2 in the TRJMR0 register.
In timer mode, the count value is decremented by 1 each time the count source is input. When the count value reaches
0000H and the next count source is input, an underflow occurs and an interrupt request is generated.
Figure 7-11 shows the Operation Example in Timer Mode.
Figure 7-11. Operation Example in Timer Mode
Count source
Reload register
Previous value
(0300H)
New value (1010H)
Counter reloading occurs
Timer RJ0 counter
02FAH02F9H02F8H02F7H1010H100FH100EH •••••
••••• 0000H 1010H100FH100EH100DH100CH100BH
TUNDF bit in
TRJCR0 register
An underflow
occurs
Set to 0 by a
program
IF bit in INTC register
Acknowledgement of an interrupt request
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7.4.3 Pulse Output Mode
In this mode, the counter is decremented by the count source selected by bits TCK0 to TCK2 in the TRJMR0 register,
and the output level of pins TRJIO and TRJO pin is inverted each time an underflow occurs.
In pulse output mode, the count value is decremented by 1 each time the count source is input. When the count value
reaches 0000H and the next count source is input, an underflow occurs and an interrupt request is generated.
In addition, a pulse can be output from pins TRJIO0 and TRJO0. The output level is inverted each time an underflow
occurs. The pulse output from the TRJO0 pin can be stopped by the TOENA bit in the TRJIOC0 register.
Also, the output level can be selected by the TEDGSEL bit in the TRJIOC0 register.
Figure 7-12 shows the Operation Example in Pulse Output Mode.
Figure 7-12. Operation Example in Pulse Output Mode
Write 1 to TSTART bit in TRJCR0 register
by a program
Write 0002H to
TRJ0 register by
a program
Write 0004H to
TRJ0 register by a
program
Write 1 to port mode register (PMxx)
bit corresponding to port multiplexed
with TRJIO0 function
Count source
TSTART bit in
TRJCR0 register
TRJ0 register
FFFFH
Reload register
FFFFH
Timer RJ0 counter
FFFFH
0002H
0004H
0002H
0002H
0004H
0001H0000H0002H0001H0000H 0002H 0001H 0000H 0002H 0001H 0004H 0003H 0002H 0001H 0000H 0004H 0003H
TEDGSEL bit in
TRJIOC0 register
<R>
0
Port mode register (PMxx) bit
corresponding to port multiplexed
with TRJIO0 function
TRJO0 pin output
High-impedance
state (Note 1)
TRJIO0 pin output
TUNDF bit in
TRJCR0 register
Set to 0 by a program
IF bit in
INTC register
Acknowledgement of
an interrupt request
Note 1: The TRJIO0 pin becomes high impedance by output enable control on the port selected as the TRJIO function.
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7.4.4 Event Counter Mode
In this mode, the counter is decremented by an external event signal (count source) input to the TRJIO0 pin. Various
periods for counting events can be set by bits TIOGT0 and TIOGT1 in the TRJIOC0 register and the TRJISR0 register. In
addition, the filter function for the TRJIO0 input can be specified by bits TIPF0 and TIPF1 in the TRJIOC0 register.
Also, the output from the TRJO0 pin can be toggled even in event counter mode.
When event counter mode is used, see 7. 5. 5 Procedure for Setting Pins TRJO0 and TRJIO0.
Figure 7-13 shows the Operation Example in Event Counter Mode.
Figure 7-13. Operation Example 1 in Event Counter Mode
Event counter mode is entered
Bits TMOD2 to TMOD0
in TRJMR0 register
Control bit in
TRJIOC0 register
010B
Event is counted at rising edge
00H
TSTART bit
in TRJCR0 register
Event input is started
Event input is completed
TRJIO0 pin
event input
Timer RJ0 counter
FFFFH
FFFEH FFFDH
0000H
FFFFH
FFFEH
Counter initial value is set
TUNDF bit in
TRJCR0 register
Set to 0 by a program
IF bit in
INTC register
Acknowledgement of an interrupt request
Figure 7-14 shows an operation example for counting during the specified period in event counter mode (bits TlOGT1
and TlOGT0 in the TRJIO0 register are set to 01B or 10B).
<R>
Figure 7-14. Operation Example 2 in Event Counter Mode
Timing example when the setting of operating mode is as follows:
TRJMR0 register: TMOD2, 1, 0 = 010B (event counter mode)
TRJIOC0 register: TIOGT1, 0 = 01B (event is counted during specified period for external interrupt pin)
TIPF1, 0 = 00B (no filter)
TEDGSEL = 0 (count at rising edge)
TRJISR0 register: RCCPSEL2 = 1 (high-level period is counted)
TSTART bit in
TRJCR0 register
Event input starts
Note 2
Event input to
TRJIO0 pin
Note 1
INTP4 or
timer output signal
FFFFH
Timer RJ0 counter
FFFEH FFFDH
FFFCH
FFFBH FFFAH FFF9H FFF8H
The counter initial value is set
The following notes apply only when bits TIOGT1 and TIOGT0 in the TRJIOC0 register are 01B or 10B for the setting of operating mode in event count mode.
Notes 1. To control synchronization, there is a delay of two cycles of the count source until count operation is affected.
2. Count operation may be performed for two cycles of the count source immediately after the count is started, depending on the previous state before
the count is stopped.
To disable the count for two cycles immediately after the count is started, write 1 to the TSTOP bit in the TRJCR0 register to initialize the internal
circuit, and then make operation settings before starting count operation.
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7.4.5 Pulse Width Measurement Mode
In this mode, the pulse width of an external signal input to the TRJIO0 pin is measured.
When the level specified by the TEDGSEL bit in the TRJIOC0 register is input to the TRJIO0 pin, the decrement is started
with the selected count source. When the specified level on the TRJIO0 pin ends, the counter is stopped, the TEDGF bit in
the TRJCR0 register is set to 1 (active edge received), and an interrupt request is generated. The measurement of pulse
width data is performed by reading the count value while the counter is stopped. Also, when the counter underflows during
measurement, the TUNDF bit in the TRJCR0 register is set to 1 (underflow) and an interrupt request is generated.
Figure 7-15 shows the Operation Example in Pulse Width Measurement Mode.
When accessing bits TEDGF and TUNDF in the TRJCR0 register, see 7. 5. 2 Access to Flags (Bits TEDGF and TUNDF
in TRJCR0 Register).
Figure 7-15. Operation Example in Pulse Width Measurement Mode
This example applies when the high-level width of the measurement pulse is measured (TEDGSEL bit in TRJIOC0 register = 1)
FFFFH
n = TRJ0 register content
Measurement is started
Underflow
Counter content (hex)
n
Measurement
is stopped
Measurement
is stopped
Measurement
is started
0000H
Measurement
is started
Time
TSTART bit in
TRJCR0 register
Set to 1 by a program
Measurement pulse
input to TRJIO0 pin
IF bit in
INTC register
Acknowledgement of an
interrupt request
TEDGF bit in
TRJCR0 register
Set to 0 by a program
Set to 0 by a program
TUNDF bit in
TRJCR0 register
Set to 0 by a program
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7.4.6 Pulse Period Measurement Mode
In this mode, the pulse period of an external signal input to the TRJIO0 pin is measured.
The counter is decremented by the count source selected by bits TCK0 to TCK2 in the TRJMR0 register. When a pulse
with the period specified by the TEDGSEL bit in the TRJIOC0 register is input to the TRJIO0 pin, the count value is
transferred to the read-out buffer at the rising edge of the count source. The value in the reload register is loaded to the
counter at the next rising edge. Simultaneously, the TEDGF bit in the TRJCR0 register is set to 1 (active edge received)
and an interrupt request is generated. The read-out buffer (TRJ0 register) is read at this time and the difference from the
reload value is the period data of the input pulse. The period data is retained until the read-out buffer is read. When the
counter underflows, the TUNDF bit in the TRJCR0 register is set to 1 (underflow) and an interrupt request is generated.
Figure 7-16 shows the Operation Example in Pulse Period Measurement Mode.
Only input pulses with a period longer than twice the period of the count source. Also, the low-level and high-level
widths must be both longer than the period of the count source. If a pulse period shorter than these conditions is input, the
input may be ignored
Figure 7-16. Operation Example in Pulse Period Measurement Mode
Count source
TSTART bit
in TRJCR0 register
Measurement pulse input
Counter is reloaded
Timer RJ0 counter
Content of read-out buffer
0300H
0300H
02FFH02FEH0300H02FFH02FEH 02FDH
02FFH
02FCH
02FBH02FAH02F9H02F8H02F7H 0300H 02FFH ••••
02FEH
02FBH02FAH02F9H02F8H
02F7H
•••• 0001H 0000H 0300H02FFH02FEH
••••
•••• 0001H 0000H 0300H 02FFH
Counter value is read (Note 1)
Read signal of counter
(Note 2)
02FEH
(Note 2)
02F7H
Read data
TEDGF bit in
TRJCR0 register
TUNDF bit in
TRJCR0 register
IF bit in
INTC register
(Note 3)
(Note 3)
Set to 0 by a program
(Note 4)
Set to 0 by a program
(Note 5)
Acknowledgement of an interrupt request
This example applies when the initial value of the TRJ0 register is set to 0300H, the TEDGSEL bit in the TRJIOC0 register is set to 0, and the
period from one rising edge to the next edge of the measurement pulse is measured.
Notes:
1. Reading from the TRJ0 register must be performed during the period from when the TEDGF bit is set to 1 (active edge received) until the
next active edge is input. The content of the read-out buffer is retained until the TRJ0 register is read. If it is not read before the active
edge is input, the measurement result of the previous period is retained.
2. When the TRJ0 register is read in pulse period measurement mode, the content of the read-out buffer is read.
3. When the active edge of the measurement pulse is input and then the set edge of an external pulse is input, the TEDGF bit in the
TRJCR0 register is set to 1 (active edge received).
4. To set to 0 by a program, write 0 to the TEDGF bit in the TRJCR0 register using an 8-bit memory manipulation instruction.
5. To set to 0 by a program, write 0 to the TUNDF bit in the TRJCR0 register using an 8-bit memory manipulation instruction.
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7.4.7 Coordination with Event Link Controller (ELC)
Through coordination with the ELC, event input from the ELC can be set to be the count source. Bits TCK0 to TCK2
in the TRJMR0 register count at the rising edge of event input from the ELC. However, ELC input does not function in event
counter mode.
<R>
The ELC setting procedure is shown below:
• Procedure for starting operation
(1) Set the event output destination select register (ELSELRn) for the event link controller (ELC).
(2) Set the operating mode for the event generation source.
(3) Set the mode for timer RJ.
(4) Start the count operation of timer RJ.
(5) Start the operation of the event generation source.
• Procedure for stopping operation
(1) Stop the operation of the event generation source.
(2) Stop the count operation of timer RJ.
(3) Set the event output destination select register (ELSELRn) for the event link controller (ELC) to 0.
7.4.8 Output Settings for Each Mode
Table 7-6 and Table 7-7 list the states of pins TRJO0 and TRJIO0 in each mode.
Table 7-6. TRJO0 Pin Setting
Operating Mode
All modes
TRJIOC0 Register
TRJO0 Pin Output
TOENA Bit
TEDGSEL Bit
1
1
Inverted output
0
Normal output
0
0 or 1
Output disabled
Table 7-7. TRJIO0 Pin Setting
Operating Mode
TRJIOC0 Register
PMXX Bit
Timer mode
Pulse output mode
Note
TRJIO0 Pin I/O
TEDGSEL Bit
0 or 1
0 or 1
1
0 or 1
Input (Not used)
Output disabled
(Hi-z output)
0
<R>
Event counter mode
1
1
Normal output
0
Inverted output
0 or 1
Input
Pulse width measurement mode
Pulse period measurement mode
Note The port mode register (PMxx) bit corresponding to port multiplexed with TRJIO0 function.
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7.5 Notes on Timer RJ
7.5.1 Count Operation Start and Stop Control
• When event count mode is set or the count source is set to other than the ELC
After 1 (count starts) is written to the TSTART bit in the TRJCR0 register while the count is stopped, the TCSTF bit in
the TRJCR0 register remains 0 (count stops) for three cycles of the count source. Do not access the registers associated
with timer RJ Note other than the TCSTF bit until this bit is set to 1 (count in progress).
After 0 (count stops) is written to the TSTART bit during a count operation, the TCSTF bit remains 1 for three cycles of
the count source. When the TCSTF bit is set to 0, the count is stopped. Do not access the registers associated with timer
RJ Note other than the TCSTF bit until this bit is set to 0.
Clear the interrupt register before changing the TATART bit from 0 to 1. Refer to CHAPTER 21
INTERRUPT
FUNCTIONS for details.
Note Registers associated with timer RJ: TRJ0, TRJCR0, TRJIOC0, TRJMR0, and TRJISR0
<R> • When event count mode is set or the count source is set to the ELC
After 1 (count starts) is written to the TSTART bit in the TRJCR0 register while the count is stopped, the TCSTF bit in
the TRJCR0 register remains 0 (count stops) for two cycles of the CPU clock. Do not access the registers associated with
timer RJ Note other than the TCSTF bit until this bit is set to 1 (count in progress).
After 0 (count stops) is written to the TSTART bit during a count operation, the TCSTF bit remains 1 for two cycles of
the CPU clock. When the TCSTF bit is set to 0, the count is stopped. Do not access the registers associated with timer RJ
Note
other than the TCSTF bit until this bit is set to 0.
Clear the interrupt register before changing the TATART bit from 0 to 1. Refer to CHAPTER 21 INTERRUPT
FUNCTIONS for details.
Note Registers associated with timer RJ: TRJ0, TRJCR0, TRJIOC0, TRJMR0, and TRJISR0
7.5.2 Access to Flags (Bits TEDGF and TUNDF in TRJCR0 Register)
Bits TEDGF and TUNDF in the TRJCR0 register are set to 0 by writing 0 by a program, but writing 1 to these bits has
no effect. If a read-modify-write instruction is used to set the TRJCR0 register, bits TEDGF and TUNDF may be
erroneously set to 0 depending on the timing, even when the TEDGF bit is set to 1 (active edge received) and the TUNDF
bit is set to 1 (underflow) during execution of the instruction. Use an 8-bit memory manipulation instruction to access to the
TRJCR0 register.
7.5.3 Access to Counter Register
When bits TSTART and TCSTF in the TRJCR0 register are both 1 (count starts), allow at least three cycles of the count
source clock between writes when writing to the TRJ0 register successively.
<R> 7.5.4 When Changing Mode
The registers associated with timer RJ operating mode (TRJIOC0,TRJMR0, and TRJISR0) can be changed only
when the count is stopped with both the TSTART and TCSTF bits set to 0 (count stops). Do not change these registers
during count operation.
When the registers associated with timer RJ operating mode are changed, the values of bits TSTART and TCSTF are
undefined. Write 0 (no active edge received) to the TEDGF bit and 0 (no underflow) to the TUNDF bit before starting the
count.
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7.5.5 Procedure for Setting Pins TRJO0 and TRJIO0
After a reset, the I/O ports multiplexed with pins TRJO0 and TRJIO0 function as input ports.
To output from pins TRJO0 and TRJIO0, use the following setting procedure:
Changing procedure
(1) Set the mode.
(2) Set the initial value/output enabled.
(3) Set the port register bits corresponding to pins TRJO0 and TRJIO0 to 0.
(4) Set the port mode register bits corresponding to pins TRJO0 and TRJIO0 to output mode.
(Output is started from pins TRJO0 and TRJIO0)
(5) Start the count (TSTART in TRJCR0 register = 1).
To input from the TRJIO0 pin, use the following setting procedure:
(1) Set the mode.
(2) Set the initial value/edge selected.
(3) Set the port mode register bit corresponding to TRJIO0 pin to input mode.
(Input is started from the TRJIO0 pin)
(4) Start the count (TSTART in TRJMR0 register = 1).
(5) Wait until the TCSTF bit in the TRJCR0 register is set to 1 (count in progress).
(In event counter mode only)
(6) Input an external event from the TRJIO0 pin.
(7) The processing on completion of the first measurement is invalid (the measured value is valid for the second and
subsequent times). (In pulse width measurement mode and pulse period measurement mode only)
7.5.6 When Timer RJ is not Used
When timer RJ is not used, set bits TMOD2 to TMOD0 in the TRJMR0 register to 000B (timer mode) and set the
TOENA bit in the TRJIOC0 register to 0 (TRJO output disabled).
7.5.7 When Timer RJ Operating Clock is Stopped
Supplying or stopping the timer RJ clock can be controlled by the TRJ0EN bit in the PER1 register. Note that the
following SFRs cannot be accessed while the timer RJ clock is stopped. Make sure the timer RJ clock is supplied before
accessing any of these registers.
Registers TRJ0, TRJCR0, TRJMR0, TRJIOC0, and TRJISR0.
7.5.8 Procedure for Setting STOP Mode (Event Counter Mode)
To perform event counter mode operation during STOP mode, first supply the timer RJ clock and then use the following
procedure to enter STOP mode.
Setting procedure
(1) Set the operating mode.
(2) Start the count (TSTART = 1, TCSTF = 1).
(3) Stop supplying the timer RJ clock.
To stop event counter mode operation during STOP mode, use the following procedure to stop operation.
(1) Supply the timer RJ clock.
(2) Stop the count (TSTART = 0, TCSTF = 0)
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7.5.9 Functional Restriction in STOP Mode (Event Counter Mode Only)
When event counter mode operation is performed during STOP mode, the digital filter function cannot be used.
7.5.10 When Count is Forcibly Stopped by TSTOP Bit
After the counter is forcibly stopped by the TSTOP bit in the TRJCR0 register, do not access the following SFRs for one
cycle of the count source.
Registers TRJ0, TRJCR0, and TRJMR0
<R> 7.5.11 Digital Filter
When the digital filter is used, do not start timer operation for five cycles of the digital filter clock after setting bits TIPF1
and TIPF0.
Also, do not start timer operation for five cycles of the digital filter clock when the TEDGSEL bit in the TRJIOC register
is changed while the digital filter is used.
<R> 7.5.12 When Selecting fIL as Count Source
When selecting fIL as the count source, set the WUTMMCK0 bit in the operation speed mode control register (OSMC)
to 1. However, fIL cannot be selected as the count source for timer RJ when fSUB is selected as the count source for the
real-time clock or the 12-bit interval timer.
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CHAPTER 8 TIMER RD
CHAPTER 8 TIMER RD
Timer RD contains two 16-bit timers (timer RD0 and timer RD1).
8.1 Overview
Timer RD0 and timer RD1 have four I/O pins.
The operating clock for timer RD is fCLK or fHOCO.
Figure 8-1 shows the Timer RD Block Diagram and Table 8-1 lists the Timer RD Pin Configuration.
Timer RD has four modes:
• Timer mode
- Input capture function
Transfer the counter value to a register with an external signal as the trigger
- Output compare function
Detect register value matches with a counter (Pin output can be changed at detection)
- PWM function
Output pulse of any width continuously
The following three modes use the PWM function.
• Reset synchronous PWM mode Output three-phase waveforms (6) without sawtooth wave modulation and dead time
• Complementary PWM mode
Output three-phase waveforms (6) with triangular wave modulation and dead time
• PWM3 mode
Output PWM waveforms (2) with a fixed period
The timer mode input capture function, output compare function, and PWM function are equivalent in timer RD0 and
timer RD1, and these functions can be selected individually for each pin. Also, a combination of these functions can be
used in timer RD0 and timer RD1.
In reset synchronous PWM mode, complementary PWM mode, and PWM3 mode, a waveform is output with a
combination of counters and registers in timer RD0 and timer RD1. Pin functions depend on the mode.
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Figure 8-1. Timer RD Block Diagram
fHOCO, fCLK, fCLK/2, fCLK/4, fCLK/8, fCLK/32
Timer RDi
TRDi register
TRDGRAi register
TRDGRBi register
INTP0
Count source
select circuit
TRDGRCi register
TRDIOA0/TRDCLK0
TRDGRDi register
TRDIOB0
TRDDFi register
Timer RD control
circuit
Data bus
TRDCRi register
TRDIOC0
TRDIOD0
TRDIORAi register
TRDIOA1
TRDIORCi register
TRDIOB1
TRDSRi register
TRDIOC1
TRDIERi register
TRDIOD1
TRDPOCRi register
Timer RD0 interrupt
request
Timer RD1 interrupt
request
TRDELC register
TRDSTR register
TRDMR register
TRDPMR register
TRDFCR register
TRDOER1 register
TRDOER2 register
TRDOCR register
Remark
i = 0 or 1
Table 8-1. Timer RD Pin Configuration
Pin Name
Assigned Pin
TRDIOA0/TRDCLK0
P17
Input/Output
TRDIOB0
P15
Input/Output
TRDIOC0
P16
Input/Output
TRDIOD0
P14
Input/Output
TRDIOA1
P13
Input/Output
TRDIOB1
P12
Input/Output
TRDIOC1
P11
Input/Output
TRDIOD1
P10
Input/Output
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Function
Function varies depending on the mode.
Refer to descriptions of individual modes for details.
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8.2 Registers
Table 8-2 lists the Timer RD Register Configuration.
Table 8-2. Timer RD Register Configuration
Register Name
Peripheral Enable Register 1
Symbol
PER1
After Reset
Address
Access Size
00H
F007AH
8
Note
F0260H
8
Note
F0263H
8
00H
Note
F0264H
8
F0265H
8
Timer RD ELC Register
TRDELC
00H
Timer RD Start Register
TRDSTR
0CH
Timer RD Mode Register
TRDMR
Timer RD PWM Function Select Register
TRDPMR
00H
Note
Timer RD Function Control Register
TRDFCR
80H
Note
F0266H
8
Timer RD Output Master Enable Register 1
TRDOER1
FFH
Note
F0267H
8
Timer RD Output Master Enable Register 2
TRDOER2
00H
Note
F0268H
8
Timer RD Output Control Register
TRDOCR
00H
Note
F0269H
8
Timer RD Digital Filter Function Select Register 0
TRDDF0
00H
Note
F026AH
8
Timer RD Digital Filter Function Select Register 1
TRDDF1
00H
Note
F026BH
8
Timer RD Control Register 0
TRDCR0
00H
Note
F0270H
8
Timer RD I/O Control Register A0
TRDIORA0
00H
Note
F0271H
8
Timer RD I/O Control Register C0
TRDIORC0
88H
Note
F0272H
8
TRDSR0
00H
Note
F0273H
8
TRDIER0
00H
Note
F0274H
8
TRDPOCR0
00H
Note
F0275H
8
TRD0
0000H
Note
F0276H
16
TRDGRA0
FFFFH
Note
F0278H
16
Timer RD General Register B0
TRDGRB0
FFFFH
Note
F027AH
16
Timer RD General Register C0
TRDGRC0
FFFFH
Note
FFF58H
16
Timer RD General Register D0
TRDGRD0
FFFFH
Note
FFF5AH
16
TRDCR1
00H
Note
F0280H
8
Timer RD Status Register 0
Timer RD Interrupt Enable Register 0
Timer RD PWM Function Output Level Control
Register 0
Timer RD Counter 0
Timer RD General Register A0
Timer RD Control Register 1
Timer RD I/O Control Register A1
TRDIORA1
00H
Note
F0281H
8
Timer RD I/O Control Register C1
TRDIORC1
88H
Note
F0282H
8
Timer RD Status Register 1
TRDSR1
00H
Note
F0283H
8
Timer RD Interrupt Enable Register 1
TRDIER1
00H
Note
F0284H
8
TRDPOCR1
00H
Note
F0285H
8
TRD1
0000H
Note
F0286H
16
Timer RD General Register A1
TRDGRA1
FFFFH
Note
F0288H
16
Timer RD General Register B1
TRDGRB1
FFFFH
Note
F028AH
16
Timer RD General Register C1
TRDGRC1
FFFFH
Note
FFF5CH
16
Timer RD General Register D1
TRDGRD1
FFFFH
Note
FFF5EH
16
Timer RD PWM Function Output Level Control
Register 1
Timer RD Counter 1
Port Register 1
Port Mode Register 1
Note
<R>
P1
00H
FFF01H
8
PM1
FFH
FFF21H
8
The timer RD SFRs are undefined when FRQSEL4 = 1 in the user option byte (000C2H/010C2H) and
TRD0EN = 0 in the PER1 register. If it is necessary to read the initial value, set fCLK to fIH and TRD0EN = 1
before reading.
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8.2.1 Peripheral enable register 1 (PER1)
The PER1 register is used to enable or disable supplying the clock to the peripheral hardware. Clock supply to the
hardware that is not used is also stopped so as to decrease the power consumption and noise.
To use timer RD, be sure to set bit 4 (TRD0EN) to 1.
The PER1 register can be set by a 1-bit or 8-bit memory manipulation instruction.
Reset signal generation clears this register to 00H.
Figure 8-2. Format of Peripheral Enable Register 1 (PER1)
Address: F007AH
Symbol
PER1
After reset: 00H
<7>
<6>
DACEN
Note
TRGEN
TRD0EN
R/W
<5>
CMPEN
Note
<4>
<3>
2
1
<0>
TRD0EN
DTCEN
0
0
TRJ0EN
Control of timer RD input clock supply
Stops input clock supply.
• SFR used by timer RD cannot be written.
0
• Timer RD is in the reset status.
Enables input clock supply.
• SFR used by timer RD can be read and written.
1
Note
Only for products with 96 KB or more code flash memory.
Cautions 1. When setting timer RD, be sure to set the TRD0EN bit to 1 first. If TRD0EN = 0,
writing to a control register of timer RD is ignored, and all read values are default
values (except for port mode register 1 (PM1), and port register 1 (P1)).
2. Be sure to clear the following bits to 0.
Products with 64 KB or less code flash memory: bits 1, 2, 5, and 7
Products with 96 KB or more code flash memory: bits 1 and 2
<R>
3. When selecting fHOCO as the count source for timer RD, set fCLK to fIH before setting
bit 4 (TRD0EN) in peripheral enable register 1 (PER1). When changing fCLK to a clock
other than fIH, clear bit 4 (TRD0EN) in peripheral enable register 1 (PER1) before
changing.
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8.2.2 Timer RD ELC Register (TRDELC)
Figure 8-3. Format of Timer RD ELC Register (TRDELC)
Address: F0260H After Reset: 00H
Note
Symbol
7
6
5
4
3
2
1
0
TRDELC
—
—
ELCOBE1
ELCICE1
—
—
ELCOBE0
ELCICE0
Bits 7 to 6
—
Nothing is assigned
The write value must be 0. The read value is 0.
ELC event input 1 enable for timer RD pulse output forced cutoff
ELCOBE1
0
Forced cutoff is disabled
1
Forced cutoff is enabled
Input capture D1 is selected
1
Event input 1 from the event link controller (ELC) is selected
—
Nothing is assigned
The write value must be 0. The read value is 0.
ELC event input 0 enable for timer RD pulse output forced cutoff
ELCOBE0
0
Forced cutoff is disabled
1
Forced cutoff is enabled
ELC event input 0 select for timer RD input capture D0
ELCICE0
Note
<R>
R/W
R/W
R/W
0
Bits 3 to 2
R
R/W
ELC event input 1 select for timer RD input capture D1
ELCICE1
R/W
0
Input capture D0 is selected
1
Event input 0 from the event link controller (ELC) is selected
R/W
R
R/W
R/W
R/W
R/W
The value after reset is undefined when FRQSEL4 = 1 in the user option byte (000C2H/010C2H) and TRD0EN =
0 in the PER1 register. If it is necessary to read the initial value, set fCLK to fIH and TRD0EN = 1 before reading.
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8.2.3 Timer RD Start Register (TRDSTR)
The TRDSTR register can be set by an 8-bit memory manipulation instruction. See 8. 4. 1 (2) TRDSTR Register in the
usage notes on timer RD.
Figure 8-4. Format of Timer RD Start Register (TRDSTR)
Address: F0263H After Reset: 0CH
Note 1
Symbol
7
6
5
4
3
2
1
0
TRDSTR
—
—
—
—
CSEL1
CSEL0
TSTART1
TSTART0
Bits 7 to 4
—
Nothing is assigned
The write value must be 0. The read value is 0.
1
1
Note 2
Count stops at compare match with TRDGRA1 register
Count continues after compare match with TRDGRA1 register
CSEL0
0
R
TRD1 count operation select
CSEL1
0
R/W
R/W
Note 3
TRD0 count operation select
R/W
Count stops at compare match with TRDGRA0 register
Count continues after compare match with TRDGRA0 register
TRD1 count start flag
TSTART1
0
Count stops
1
Count starts
0
Count stops
1
Count starts
R/W
Note 3
R/W
R/W
TRD0 count start flag
TSTART0
Notes 4, 5
R/W
Notes 6, 7
R/W
R/W
Notes 1. The value after reset is undefined when FRQSEL4 = 1 in the user option byte (000C2H/010C2H) and
<R>
TRD0EN = 0 in the PER1 register. If it is necessary to read the initial value, set fCLK to fIH and TRD0EN = 1
before reading.
2. Do not use in PWM3 mode.
3. Set to 1 for the input capture function.
4. Write 0 to the TSTART1 bit while the CSEL1 bit is set to 1.
5. When the CSEL1 bit is 0 and a compare match signal (TRDIOA1) is generated, this flag is set to 0 (count
stops).
6. Write 0 to the TSTART0 bit while the CSEL0 bit is set to 1.
7. When the CSEL0 bit is 0 and a compare match signal (TRDIOA0) is generated, this flag is set to 0 (count
stops).
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8.2.4 Timer RD Mode Register (TRDMR)
Figure 8-5. Format of Timer RD Mode Register (TRDMR)
Address: F0264H After Reset:00H
<R>
Note 1
Symbol
<7>
<6>
<5>
<4>
3
2
1
<0>
TRDMR
TRDBFD1
TRDBFC1
TRDBFD0
TRDBFC0
0
0
0
TRDSYNC
TRDGRD1 register function select
TRDBFD1
0
General register
1
Buffer register for TRDGRB1 register
0
General register
1
Buffer register for TRDGRA1 register
0
General register
1
Buffer register for TRDGRB0 register
0
General register
1
Buffer register for TRDGRA0 register
Bits 3 to1
—
Note 2
Notes 2, 3
R/W
R/W
R/W
Nothing is assigned
The write value must be 0. The read value is 0.
Timer RD synchronous
TRDSYNC
R/W
R/W
TRDGRC0 register function select
TRDBFC0
Note 2
R/W
TRDGRD0 register function select
TRDBFD0
R/W
R/W
TRDGRC1 register function select
TRDBFC1
Note 2
0
TRD0 and TRD1 operate independently
1
TRD0 and TRD1 operate synchronously
R/W
R
Note 4
R/W
R/W
Notes 1. The value after reset is undefined when FRQSEL4 = 1 in the user option byte (000C2H/010C2H) and
<R>
TRD0EN = 0 in the PER1 register. If it is necessary to read the initial value, set fCLK to fIH and TRD0EN = 1
before reading.
2. In the output compare function, if 0 (TRDGRji register output pin is changed) is selected for the IOj3 (j = C or
D) bit in the TRDIORCi (i = 0 or 1) register, set the BFji bit in the TRDMR register to 0.
3. Set to 0 (general register) in complementary PWM mode.
4. Set to 0 (TRD0 and TRD1 operate independently) in reset synchronous PWM mode, complementary PWM
mode, and PWM3 mode.
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8.2.5 Timer RD PWM Function Select Register (TRDPMR)
Figure 8-6. Format of Timer RD PWM Functon Select Register (TRDPMR) [Timer Mode]
Address: F0265H After Reset:00H
<R>
Note
Symbol
7
<6>
<5>
<4>
3
<2>
<1>
<0>
TRDPMR
0
TRDPWMD1
TRDPWMC1
TRDPWMB1
0
TRDPWMD0
TRDPWMC0
TRDPWMB0
Bit 7
—
Nothing is assigned
The write value must be 0. The read value is 0.
TRDPWMD1
PWM function of TRDIOD1 select
0
Input capture function or output compare function
1
PWM function
TRDPWMC1
PWM function of TRDIOC1 select
0
Input capture function or output compare function
1
PWM function
TRDPWMB1
PWM function of TRDIOB1 select
0
Input capture function or output compare function
1
PWM function
Bit 3
—
Nothing is assigned
The write value must be 0. The read value is 0.
TRDPWMD0
PWM function of TRDIOD0 select
0
Input capture function or output compare function
1
PWM function
TRDPWMC0
PWM function of TRDIOC0 select
0
Input capture function or output compare function
1
PWM function
TRDPWMB0
PWM function of TRDIOB0 select
0
Input capture function or output compare function
1
PWM function
R/W
R
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R
R/W
R/W
R/W
R/W
R/W
R/W
Note The value after reset is undefined when FRQSEL4 = 1 in the user option byte (000C2H/010C2H) and TRD0EN =
<R>
0 in the PER1 register. If it is necessary to read the initial value, set fCLK to fIH and TRD0EN = 1 before reading.
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8.2.6 Timer RD Function Control Register (TRDFCR)
Figure 8-7. Format of Timer RD Function Control Register (TRDFCR)
Address: F0266H After Reset: 80H
Note 1
Symbol
7
6
5
4
3
2
1
0
TRDFCR
PWM3
STCLK
0
0
OLS1
OLS0
CMD1
CMD0
PWM3 mode select
PWM3
Note 2
• In the timer mode, set to 1 (other than PWM3 mode).
R/W
R/W
• In PWM3 mode, set to 0 (PWM3 mode).
• Disabled in reset synchronous and complementary PWM modes.
STCLK
External clock input select
• In the timer mode, the reset synchronous PWM mode, and the complementary PWM mode,
R/W
R/W
0: External clock input disabled
1: External clock input enabled
• In PWM3 mode, set to 0 (external clock input disabled).
Reserved
Bits 5 to 4
0
Set to 0.
R/W
R/W
OLS1
Counter-phase output level select
R/W
(in reset synchronous PWM mode or complementary PWM mode)
• In reset synchronous and complementary PWM modes,
R/W
0: High initial output and low active level
1: Low initial output and high active level
• Disabled in timer and PWM3 modes.
OLS0
Phase output level select
R/W
(in reset synchronous PWM mode or complementary PWM mode)
• In reset synchronous and complementary PWM modes,
R/W
0: High initial output and low active level
1: Low initial output and high active level
• Disabled in timer and PWM3 modes.
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CMD1
CMD0
Combination mode select
Notes 3, 4
• In timer and PWM3 modes, set to 00B (timer mode or PWM3 mode).
R/W
R/W
• In reset synchronous PWM mode, set to 01B (reset synchronous PWM mode).
• In complementary PWM mode,
CMD1 CMD0
1
0: Complementary PWM mode (transfer from the buffer register to the general register when TRD1
1
1: Complementary PWM mode (transfer from the buffer register to the general register at compare
underflows)
match between registers TRD0 and TRDGRA0)
Other than the above: Do not set.
Notes 1. The value after reset is undefined when FRQSEL4 = 1 in the user option byte (000C2H/010C2H) and
<R>
TRD0EN = 0 in the PER1 register. If it is necessary to read the initial value, set fCLK to fIH and TRD0EN = 1
before reading.
2. When bits CMD1 and CMD0 are set to 00B (timer mode or PWM3 mode), the setting of the PWM3 bit is
enabled.
3. Set bits CMD0 and CMD1 when both the TSTART0 and TSTART1 bits in the TRDSTR register are set to 0
(count stops).
4. When bits CMD1 and CMD0 are set to 01B, 10B, or 11B, the MCU enters reset synchronous PWM mode or
complementary PWM mode regardless of the settings of the TRDPMR register.
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8.2.7 Timer RD Output Master Enable Register 1 (TRDOER1)
Figure 8-8. Format of Timer RD Output Master Enable Register 1 (TRDOER1)
[Output Compare Function, PWM Function, Reset Synchronous PWM Mode,
Complementary PWM Mode, and PWM3 Mode]
Address: F0267H After Reset: FFH
Note 1
Symbol
7
6
5
4
3
2
1
0
TRDOER1
ED1
EC1
EB1
EA1
ED0
EC0
EB0
EA0
TRDIOD1 output disable
Note 2
ED1
0
Output enabled
1
Output disabled (TRDIOD1 pin functions as an I/O port.)
R/W
TRDIOC1 output disable
EC1
0
Output enabled
1
Output disabled (TRDIOC1 pin functions as an I/O port.)
Output enabled
1
Output disabled (TRDIOB1 pin functions as an I/O port.)
TRDIOA1 output disable
Output enabled
1
Output disabled (TRDIOA1 pin functions as an I/O port)
Notes 2, 3
TRDIOD0 output disable
0
Output enabled
1
Output disabled (TRDIOD0 pin functions as an I/O port.)
0
Output enabled
1
Output disabled (TRDIOC0 pin functions as an I/O port.)
EB0
R/W
Note 2
R/W
Note 2
R/W
R/W
TRDIOB0 output disable
R/W
R/W
0
Output enabled
1
Output disabled (TRDIOB0 pin functions as an I/O port.)
TRDIOA0 output disable
EA0
R/W
R/W
TRDIOC0 output disable
EC0
Note 2
R/W
0
ED0
R/W
R/W
0
EA1
Note 2
R/W
TRDIOB1 output disable
EB1
R/W
0
Output enabled
1
Output disabled (TRDIOA0 pin functions as an I/O port)
Notes 3, 4
R/W
R/W
Notes 1. The value after reset is undefined when FRQSEL4 = 1 in the user option byte (000C2H/010C2H) and
<R>
TRD0EN = 0 in the PER1 register. If it is necessary to read the initial value, set fCLK to fIH and TRD0EN = 1
before reading.
2. Set to 1 in PWM3 mode.
3. Set to 1 in PWM function.
4. Set to 1 in reset synchronous PWM mode and complementary PWM mode.
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8.2.8 Timer RD Output Master Enable Register 2 (TRDOER2)
Figure 8-9. Format of Timer RD Output Master Enable Register 2 (TRDOER2)
[PWM Function, Reset Synchronous PWM Mode, Complementary PWM Mode, and PWM3 Mode]
Address: F0268H After Reset: 00H
<R>
Note 1
Symbol
<7>
6
5
4
3
2
1
<0>
TRDOER2
TRDPTO
0
0
0
0
0
0
TRDSHUTS
INTP0 of pulse output forced cutoff signal input enabled
TRDPTO
0
Pulse output forced cutoff input disabled
1
Pulse output forced cutoff input enabled
Note 2
R/W
R/W
(The TRDSHUTS bit is set to 1 when a low level is applied to the INTP0 pin.)
Bits 6 to 1
—
Nothing is assigned
The write value must be 0. The read value is 0.
TRDSHUTS
Forced cutoff flag
0
Not forcibly cut off
1
Forcibly cut off
R/W
R
R/W
R/W
This bit is set to 1 when the pulse is forcibly cut off by an INTP0 or ELC input event. This bit is not
automatically cleared. To stop the forced cutoff of the pulse, write 0 to this bit while the count is stopped
(TSTARTi = 0). The pulse is also forcibly cut off when 1 is written to the TRDSHUTS bit in an enabled mode.
Notes 1.
<R>
The value after reset is undefined when FRQSEL4 = 1 in the user option byte (000C2H/010C2H) and
TRD0EN = 0 in the PER1 register. If it is necessary to read the initial value, set fCLK to fIH and TRD0EN
= 1 before reading.
2.
See 8. 3. 1 (4) Pulse Output Forced Cutoff.
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8.2.9 Timer RD Output Control Register (TRDOCR)
Write to the TRDOCR register when bits TSTART0 and TSTART1 in the TRDSTR register are both 0 (count stops).
Figure 8-10. Format of Timer RD Output Control Register (TRDOCR) [Output Compare Function]
Address: F0269H After Reset: 00H
Note 1
Symbol
7
6
5
4
3
2
1
0
TRDOCR
TOD1
TOC1
TOB1
TOA1
TOD0
TOC0
TOB0
TOA0
TRDIOD1 initial output level select
TOD1
0
Low initial output
1
High initial output
0
Low initial output
1
High initial output
0
Low initial output
1
High initial output
TOA1
Note 2
Note 2
Low initial output
1
High initial output
0
Low initial output
1
High initial output
0
Low initial output
1
High initial output
0
Low initial output
1
High initial output
TOA0
Note 2
Note 2
Low initial output
1
High initial output
Notes 1.
R/W
R/W
R/W
TRDIOA0 initial output level select
0
R/W
R/W
TRDIOB0 initial output level select
TOB0
Note 2
R/W
TRDIOC0 initial output level select
TOC0
R/W
R/W
TRDIOD0 initial output level select
TOD0
R/W
R/W
TRDIOA1 initial output level select
0
R/W
R/W
TRDIOB1 initial output level select
TOB1
R/W
R/W
TRDIOC1 initial output level select
TOC1
Note 2
R/W
R/W
The value after reset is undefined when FRQSEL4 = 1 in the user option byte (000C2H/010C2H) and
TRD0EN = 0 in the PER1 register. If it is necessary to read the initial value, set fCLK to fIH and TRD0EN
<R>
= 1 before reading.
2.
If the pin function is set for waveform output, the initial output level is output when the TRDOCR
register is set.
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Figure 8-11. Format of Timer RD Output Control Register (TRDOCR) [PWM Function]
Address: F0269H After Reset: 00H
Note 1
Symbol
7
6
5
4
3
2
1
0
TRDOCR
TOD1
TOC1
TOB1
TOA1
TOD0
TOC0
TOB0
TOA0
TRDIOD1 initial output level select
TOD1
0
Initial output is not active level
1
Initial output is active level
0
Initial output is not active level
1
Initial output is active level
0
Initial output is not active level
1
Initial output is active level
TOA1
Note 2
R/W
R/W
TRDIOB1 initial output level select
TOB1
R/W
R/W
TRDIOC1 initial output level select
TOC1
Note 2
Note 2
R/W
R/W
TRDIOA1 initial output level select
Set to 0.
R/W
R/W
TRDIOD0 initial output level select
TOD0
0
Initial output is not active level
1
Initial output is active level
0
Initial output is not active level
1
Initial output is active level
R/W
R/W
TRDIOC0 initial output level select
TOC0
Note 2
Note 2
R/W
R/W
Enabled in reset synchronous and complementary PWM modes.
TRDIOB0 initial output level select
TOB0
0
Initial output is not active level
1
Initial output is active level
TOA0
Note 2
R/W
TRDIOA0 initial output level select
Set to 0.
Notes 1.
<R>
R/W
R/W
R/W
The value after reset is undefined when FRQSEL4 = 1 in the user option byte (000C2H/010C2H) and
TRD0EN = 0 in the PER1 register. If it is necessary to read the initial value, set fCLK to fIH and TRD0EN
= 1 before reading.
2.
If the pin function is set for waveform output, the initial output level is output when the TRDOCR
register is set.
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Figure 8-12. Format of Timer RD Output Control Register (TRDOCR) [PWM3 Mode]
Address: F0269H After Reset: 00H
Note 1
Symbol
7
6
5
4
3
2
1
0
TRDOCR
TOD1
TOC1
TOB1
TOA1
TOD0
TOC0
TOB0
TOA0
TOD1
TRDIOD1 initial output level select
Disabled in PWM3 mode.
TOC1
R/W
TRDIOC1 initial output level select
Disabled in PWM3 mode.
TOB1
TRDIOB1 initial output level select
Disabled in PWM3 mode.
TRDIOD0 initial output level select
Disabled in PWM3 mode.
0
R/W
R/W
TRDIOC0 initial output level select
R/W
R/W
TRDIOB0 initial output level select
TOB0
R/W
R/W
Disabled in PWM3 mode.
TOC0
R/W
R/W
TRDIOA1 initial output level select
TOD0
R/W
R/W
Disabled in PWM3 mode.
TOA1
R/W
Note 2
Low initial output, high active level, high output at TRDGRB1 compare match, and low
R/W
R/W
output at TRDGRB0 compare match
1
High initial output, low active level, low output at TRDGRB1 compare match, and high
output at TRDGRB0 compare match
TOA0
0
TRDIOA0 initial output level select
Low initial output, high active level, high output at TRDGRA1 compare match, and low
R/W
R/W
output at TRDGRA0 compare match
1
High initial output, low active level, low output at TRDGRA1 compare match, and high
output at TRDGRA0 compare match
Notes 1. The value after reset is undefined when FRQSEL4 = 1 in the user option byte (000C2H/010C2H) and
<R>
TRD0EN = 0 in the PER1 register. If it is necessary to read the initial value, set fCLK to fIH and TRD0EN =
1 before reading.
2. If the pin function is set for waveform output, the initial output level is output when the TRDOCR register
is set.
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8.2.10 Timer RD Digital Filter Function Select Register i (TRDDFi) (i = 0 or 1)
Figure 8-13. Format of Timer RD Digital Filter Function Select Register i (TRDDFi) (i = 0 or 1)
[Input Capture Function]
Address: F026AH (TRDDF0), F026BH (TRDDF1) After Reset: 00H
Note 1
Symbol
7
6
5
4
3
2
1
0
TRDDFi
DFCK1
DFCK0
PENB1
PENB0
DFD
DFC
DFB
DFA
DFCK1
Clock select for digital filter function
DFCK0
0
0
fCLK/32
0
1
fCLK/8
Note 2
Note 3
R/W
R/W
Note 3
Note 3
1
0
fCLK
1
1
Count source (clock selected by bits TCK0 to TCK2 in the TRDCRi register)
PENB1
PENB0
0
0
TRDIOB pin pulse forced cutoff control
Set to 00B.
DFD
R/W
TRDIOD pin digital filter function select
0
Function is not used
1
Function is used
R/W
R/W
R/W
If the digital filter is enabled, edge detection is performed after five or more cycles of the digital filter sampling
clock have elapsed.
DFC
TRDIOC pin digital filter function select
0
Function is not used
1
Function is used
R/W
R/W
If the digital filter is enabled, edge detection is performed after five or more cycles of the digital filter sampling
clock have elapsed.
DFB
TRDIOB pin digital filter function select
0
Function is not used
1
Function is used
R/W
R/W
If the digital filter is enabled, edge detection is performed after five or more cycles of the digital filter sampling
clock have elapsed.
DFA
TRDIOA pin digital filter function select
0
Function is not used
1
Function is used
R/W
R/W
If the digital filter is enabled, edge detection is performed after five or more cycles of the digital filter sampling
clock have elapsed.
Notes 1.
The value after reset is undefined when FRQSEL4 = 1 in the user option byte (000C2H/010C2H) and
TRD0EN = 0 in the PER1 register. If it is necessary to read the initial value, set fCLK to fIH and TRD0EN
<R>
= 1 before reading.
2.
Set bits DFCK0 and DFCK1 before starting count operation.
3.
When FRQSEL4 = 1 in the user option byte (000C2H/010C2H), fCLK/32, fCLK/8, and fCLK are set to
fHOCO/32, fHOCO/8, and fHOCO, respectively.
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Figure 8-14. Format of Timer RD Digital Filter Function Select Register i (TRDDFi) (i = 0 or 1)
[PWM Function, Reset Synchronous PWM Mode, Complementary PWM Mode, and PWM3 Mode]
Address: F026AH (TRDDF0), F026BH (TRDDF1) After Reset: 00H
Note
Symbol
7
6
5
4
3
2
1
0
TRDDFi
DFCK1
DFCK0
PENB1
PENB0
DFD
DFC
DFB
DFA
DFCK1
DFCK0
0
0
TRDIOA pin pulse forced cutoff control
Forced cutoff disabled
0
1
High-impedance output
1
0
Low output
1
1
High output
R/W
R/W
Set these bits to 00B (forced cutoff disabled) if the corresponding pin is not used as a timer RD output port in
these modes. Also, set these bits while the count is stopped.
PENB1
PENB0
0
0
TRDIOB pin pulse forced cutoff control
Forced cutoff disabled
0
1
High-impedance output
1
0
Low output
1
1
High output
R/W
R/W
Set these bits to 00B (forced cutoff disabled) if the corresponding pin is not used as a timer RD output port in
these modes. Also, set these bits while the count is stopped.
DFD
DFC
0
0
TRDIOC pin pulse forced cutoff control
0
1
High-impedance output
1
0
Low output
1
1
High output
R/W
R/W
Forced cutoff disabled
Set these bits to 00B (forced cutoff disabled) if the corresponding pin is not used as a timer RD output port in
these modes. Also, set these bits while the count is stopped.
DFB
DFA
0
0
Forced cutoff disabled
TRDIOD pin pulse forced cutoff control
0
1
High-impedance output
1
0
Low output
1
1
High output
R/W
R/W
Set these bits to 00B (forced cutoff disabled) if the corresponding pin is not used as a timer RD output port in
these modes. Also, set these bits while the count is stopped.
Note The value after reset is undefined when FRQSEL4 = 1 in the user option byte (000C2H/010C2H) and TRD0EN = 0
<R>
in the PER1 register. If it is necessary to read the initial value, set fCLK to fIH and TRD0EN = 1 before reading.
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8.2.11 Timer RD Control Register i (TRDCRi) (i = 0 or 1)
The TRDCR1 register is not used in reset synchronous PWM mode or PWM3 mode.
Figure 8-15. Format of Timer RD Control Register i (TRDCRi) (i = 0 or 1)
[Input Capture Function and Output Compare Function]
Address: F0270H (TRDCR0), F0280H (TRDCR1) After Reset: 00H
Note 1
Symbol
7
6
5
4
3
2
1
0
TRDCRi
CCLR2
CCLR1
CCLR0
CKEG1
CKEG0
TCK2
TCK1
TCK0
CCLR2
CCLR1
CCLR0
TRDi counter clear select
R/W
R/W
0
0
0
Clear disabled (free-running operation)
0
0
1
Clear by input capture/compare match with TRDGRAi
0
1
0
Clear by input capture/compare match with TRDGRBi
0
1
1
Synchronous clear (clear simultaneously with other timer RDi counter)
Note 2
1
0
0
Do not set.
1
0
1
Clear by input capture/compare match with TRDGRCi
1
1
0
Clear by input capture/compare match with TRDGRDi
1
1
1
Do not set.
CKEG1
External clock edge select
CKEG0
0
0
Count at the rising edge
0
1
Count at the falling edge
1
0
Count at both edges
1
1
Do not set.
TCK2
TCK1
TCK0
0
0
0
fCLK, fHOCO
0
0
1
fCLK/2
Note 5
0
1
0
fCLK/4
Note 5
0
1
1
fCLK/8
Note 5
1
0
0
fCLK/32
1
0
1
TRDCLK input
1
1
0
Do not set.
1
1
1
Do not set.
Notes 1.
Note 3
R/W
R/W
Count source select
Note 4
R/W
R/W
Note 5
Note 6
The value after reset is undefined when FRQSEL4 = 1 in the user option byte (000C2H/010C2H) and
TRD0EN = 0 in the PER1 register. If it is necessary to read the initial value, set fCLK to fIH and TRD0EN = 1
<R>
before reading.
2.
Enabled when the TRDSYNC bit in the TRDMR register is 1 (TRD0 and TRD1 operate synchronously).
3.
Valid when bits TCK2 to TCK0 are set to 101B (TRDCLK input) and the STCLK bit is set to 1 (external
clock input enabled).
4.
<R>
fCLK is selected when FRQSEL4 = 0 and fHOCO is selected when FRQSEL4 = 1 in the user option byte
(000C2H/010C2H). When selecting fHOCO as the count source for timer RD, set fCLK to fIH before setting bit
4 (TRD0EN) in peripheral enable register 1 (PER1). When changing fCLK to a clock other than fIH, clear bit
4 (TRD0EN) in peripheral enable register 1 (PER1) before changing.
5.
Do not set this value when FRQSEL4 = 1 in the user option byte (000C2H/010C2H).
6.
Valid when the STCLK bit in the TRDFCR register is set to 1 (external clock input enabled).
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Figure 8-16. Format of Timer RD Control Register i (TRDCRi) (i = 0 or 1) [PWM Mode]
Address: F0270H (TRDCR0), F0280H (TRDCR1) After Reset: 00H
Note 1
Symbol
7
6
5
4
3
2
1
0
TRDCRi
CCLR2
CCLR1
CCLR0
CKEG1
CKEG0
TCK2
TCK1
TCK0
CCLR2
CCLR1
CCLR0
TRDi counter clear select
Set to 001B (TRDi register is cleared at compare match with TRDGRAi register).
CKEG1
CKEG0
0
0
External clock edge select
Note 2
1
Count at the falling edge
1
0
Count at both edges
1
1
Do not set.
TCK2
TCK1
TCK0
0
0
0
fCLK, fHOCO
0
0
1
fCLK/2
Note 4
0
1
0
fCLK/4
Note 4
0
1
1
fCLK/8
Note 4
1
0
0
fCLK/32
1
0
1
TRDCLK input
1
1
0
Do not set.
1
1
1
Do not set.
R/W
R/W
Count at the rising edge
0
R/W
R/W
Count source select
Note 3
R/W
R/W
Note 4
Note 5
Notes 1. The value after reset is undefined when FRQSEL4 = 1 in the user option byte (000C2H/010C2H) and
<R>
TRD0EN = 0 in the PER1 register. If it is necessary to read the initial value, set fCLK to fIH and TRD0EN = 1
before reading.
2. Valid when bits TCK2 to TCK0 are set to 101B (TRDCLK input) and the STCLK bit is set to 1 (external clock
input enabled).
3. fCLK is selected when FRQSEL4 = 0 and fHOCO is selected when FRQSEL4 = 1 in the user option byte
<R>
(000C2H/010C2H). When selecting fHOCO as the count source for timer RD, set fCLK to fIH before setting bit 4
(TRD0EN) in peripheral enable register 1 (PER1). When changing fCLK to a clock other than fIH, clear bit 4
(TRD0EN) in peripheral enable register 1 (PER1) before changing.
4. Do not set this value when FRQSEL4 = 1 in the user option byte (000C2H/010C2H).
5. Valid when the STCLK bit in the TRDFCR register is set to 1 (external clock input enabled).
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Figure 8-17. Format of Timer RD Control Register 0 (TRDCR0) [Reset Synchronous PWM Mode]
Address: F0270H (TRDCR0) After Reset: 00H
Note 1
Symbol
7
6
5
4
3
2
1
0
TRDCR0
CCLR2
CCLR1
CCLR0
CKEG1
CKEG0
TCK2
TCK1
TCK0
CCLR2
CCLR1
CCLR0
TRD0 counter clear select
Set to 001B (TRD0 register is cleared at compare match with TRDGRA0 register).
CKEG1
CKEG0
0
0
External clock edge select
1
Count at the falling edge
1
0
Count at both edges
1
1
Do not set.
TCK2
TCK1
TCK0
0
0
0
fCLK, fHOCO
0
0
1
fCLK/2
Note 4
0
1
0
fCLK/4
Note 4
0
1
1
fCLK/8
Note 4
1
0
0
fCLK/32
1
0
1
TRDCLK input
1
1
0
Do not set.
1
1
1
Do not set.
R/W
R/W
Count at the rising edge
0
Notes 1.
Note 2
R/W
R/W
Count source select
Note 3
R/W
R/W
Note 4
Note 5
The value after reset is undefined when FRQSEL4 = 1 in the user option byte (000C2H/010C2H) and
TRD0EN = 0 in the PER1 register. If it is necessary to read the initial value, set fCLK to fIH and TRD0EN = 1
<R>
before reading.
2.
Valid when bits TCK2 to TCK0 are set to 101B (TRDCLK input) and the STCLK bit is set to 1 (external
clock input enabled).
3.
fCLK is selected when FRQSEL4 = 0 and fHOCO is selected when FRQSEL4 = 1 in the user option byte
(000C2H/010C2H). When selecting fHOCO as the count source for timer RD, set fCLK to fIH before setting bit
<R>
4 (TRD0EN) in peripheral enable register 1 (PER1). When changing fCLK to a clock other than fIH, clear bit
4 (TRD0EN) in peripheral enable register 1 (PER1) before changing.
4.
Do not set this value when FRQSEL4 = 1 in the user option byte (000C2H/010C2H).
5.
Valid when the STCLK bit in the TRDFCR register is set to 1 (external clock input enabled).
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Figure 8-18. Format of Timer RD Control Register 0 (TRDCR0) [Complementary PWM Mode]
Address: F0270H (TRDCR0) After Reset: 00H
Note 1
Symbol
7
6
5
4
3
2
1
0
TRDCR0
CCLR2
CCLR1
CCLR0
CKEG1
CKEG0
TCK2
TCK1
TCK0
CCLR2
CCLR1
CCLR0
TRD0 counter clear select
Set to 000B (clear disabled (free-running operation)).
CKEG1
CKEG0
0
0
External clock edge select
R/W
Notes 2, 3
R/W
Count at the rising edge
0
1
Count at the falling edge
1
0
Count at both edges
1
1
Do not set.
TCK2
TCK1
TCK0
0
0
0
fCLK, fHOCO
0
0
1
fCLK/2
Note 5
0
1
0
fCLK/4
Note 5
0
1
1
fCLK/8
Note 5
1
0
0
fCLK/32
1
0
1
TRDCLK input
1
1
0
Do not set.
1
1
1
Do not set.
R/W
R/W
Count source select
Note 4
R/W
R/W
Note 5
Note 6
Notes 1. The value after reset is undefined when FRQSEL4 = 1 in the user option byte (000C2H/010C2H) and
<R>
TRD0EN = 0 in the PER1 register. If it is necessary to read the initial value, set fCLK to fIH and TRD0EN = 1
before reading.
2. Valid when bits TCK2 to TCK0 are set to 101B (TRDCLK input) and the STCLK bit is set to 1 (external clock
input enabled).
3. Set the same value to bits TCK0 to TCK2, CKEG0, and CKEG1 in registers TRDCR0 and TRDCR1.
4. fCLK is selected when FRQSEL4 = 0 and fHOCO is selected when FRQSEL4 = 1 in the user option byte
<R>
(000C2H/010C2H). When selecting fHOCO as the count source for timer RD, set fCLK to fIH before setting bit 4
(TRD0EN) in peripheral enable register 1 (PER1). When changing fCLK to a clock other than fIH, clear bit 4
(TRD0EN) in peripheral enable register 1 (PER1) before changing.
5. Do not set this value when FRQSEL4 = 1 in the user option byte (000C2H/010C2H).
6. Valid when the STCLK bit in the TRDFCR register is set to 1 (external clock input enabled).
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Figure 8-19. Format of Timer RD Control Register 0 (TRDCR0) [PWM3 Mode]
Address: F0270H (TRDCR0) After Reset: 00H
Note 1
Symbol
7
6
5
4
3
2
1
0
TRDCR0
CCLR2
CCLR1
CCLR0
CKEG1
CKEG0
TCK2
TCK1
TCK0
CCLR2
CCLR1
CCLR0
TRD0 counter clear select
Set to 001B (TRD0 register is cleared at compare match with TRDGRA0 register).
CKEG1
CKEG0
External clock edge select
R/W
R/W
R/W
Disabled in PWM3 mode.
R/W
TCK2
TCK1
TCK0
0
0
0
fCLK, fHOCO
Count source select
0
0
1
fCLK/2
Note 3
0
1
0
fCLK/4
Note 3
0
1
1
fCLK/8
Note 3
1
0
0
fCLK/32
1
0
1
Do not set.
1
1
0
Do not set.
1
1
1
Do not set.
Note 2
R/W
R/W
Note 3
Notes 1. The value after reset is undefined when FRQSEL4 = 1 in the user option byte (000C2H/010C2H) and
TRD0EN = 0 in the PER1 register. If it is necessary to read the initial value, set fCLK to fIH and TRD0EN
<R>
= 1 before reading.
2.
<R>
fCLK is selected when FRQSEL4 = 0 and fHOCO is selected when FRQSEL4 = 1 in the user option byte
(000C2H/010C2H). When selecting fHOCO as the count source, select fIH as fCLK before starting timer
count operation.
3. Do not set this value when FRQSEL4 = 1 in the user option byte (000C2H/010C2H).
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8.2.12 Timer RD I/O Control Register Ai (TRDIORAi) (i = 0 or 1)
Figure 8-20. Format of Timer RD I/O Control Register Ai (TRDIORAi) (i = 0 or 1) [Input Capture Function]
Address: F0271H (TRDIORA0), F0281H (TRDIORA1) After Reset: 00H
Note 1
Symbol
7
6
5
4
3
2
1
0
TRDIORAi
—
IOB2
IOB1
IOB0
0
IOA2
IOA1
IOA0
Bit 7
—
Nothing is assigned
The write value must be 0. The read value is 0.
TRDGRB mode select
IOB2
R
Note 2
Set to 1 (input capture) in the input capture function.
IOB0
0
0
Input capture to TRDGRBi at the rising edge
0
1
Input capture to TRDGRBi at the falling edge
TRDGRB control
1
0
Input capture to TRDGRBi at both edges
1
1
Do not set.
0
R/W
R/W
IOB1
Bit 3
R/W
R/W
R/W
Reserved
R/W
Set to 0.
R/W
TRDGRA mode select
IOA2
Note 3
Set to 1 (input capture) in the input capture function.
R/W
R/W
IOA1
IOA0
TRDGRA control
0
0
Input capture to TRDGRAi at the rising edge
0
1
Input capture to TRDGRAi at the falling edge
1
0
Input capture to TRDGRAi at both edges
1
1
Do not set.
R/W
R/W
Notes 1. The value after reset is undefined when FRQSEL4 = 1 in the user option byte (000C2H/010C2H) and
<R>
TRD0EN = 0 in the PER1 register. If it is necessary to read the initial value, set fCLK to fIH and TRD0EN = 1
before reading.
2. If 1 (buffer register for TRDGRBi register) is selected for the BFDi bit in the TRDMR register, set the same
value to the IOB2 bit in the TRDIORAi register and the IOD2 bit in the TRDIORCi register.
3. If 1 (buffer register for TRDGRAi register) is selected for the BFCi bit in the TRDMR register, set the same
value to the IOA2 bit in the TRDIORAi register and the IOC2 bit in the TRDIORCi register.
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Figure 8-21. Format of Timer RD I/O Control Register Ai (TRDIORAi) (i = 0 or 1) [Output Compare Function]
Address: F0271H (TRDIORA0), F0281H (TRDIORA1) After Reset: 00H
Note 1
Symbol
7
6
5
4
3
2
1
0
TRDIORAi
—
IOB2
IOB1
IOB0
0
IOA2
IOA1
IOA0
Bit 7
—
Nothing is assigned
The write value must be 0. The read value is 0.
TRDGRB mode select
IOB2
R
Note 2
Set to 0 (output compare) in the output compare function.
IOB0
0
0
Pin output by compare match is disabled (TRDIOBi pin functions as an I/O port)
0
1
Low output by compare match with TRDGRBi
1
0
High output by compare match with TRDGRBi
1
1
Toggle output by compare match with TRDGRBi
0
TRDGRB control
Reserved
R/W
R/W
TRDGRA mode select
Note 3
Set to 0 (output compare) in the output compare function.
R/W
R/W
IOA1
IOA0
0
0
Pin output by compare match is disabled (TRDIOAi pin functions as an I/O port)
0
1
Low output by compare match with TRDGRAi
TRDGRA control
1
0
High output by compare match with TRDGRAi
1
1
Toggle output by compare match with TRDGRAi
Notes 1.
R/W
R/W
Set to 0.
IOA2
<R>
R/W
R/W
IOB1
Bit 3
R/W
R/W
R/W
The value after reset is undefined when FRQSEL4 = 1 in the user option byte (000C2H/010C2H) and
TRD0EN = 0 in the PER1 register. If it is necessary to read the initial value, set fCLK to fIH and TRD0EN = 1
before reading.
2.
If 1 (buffer register for TRDGRBi register) is selected for the BFDi bit in the TRDMR register, set the same
value to the IOB2 bit in the TRDIORAi register and the IOD2 bit in the TRDIORCi register.
3. If 1 (buffer register for TRDGRAi register) is selected for the BFCi bit in the TRDMR register, set the same
value to the IOA2 bit in the TRDIORAi register and the IOC2 bit in the TRDIORCi register.
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8.2.13 Timer RD I/O Control Register Ci (TRDIORCi) (i = 0 or 1)
Figure 8-22. Format of Timer RD I/O Control Register Ci (TRDIORCi) [Input Capture Function]
Address: F0272H (TRDIORC0), F0282H (TRDIORC1) After Reset: 88H
Note 1
Symbol
7
6
5
4
3
2
1
0
TRDIORCi
IOD3
IOD2
IOD1
IOD0
IOC3
IOC2
IOC1
IOC0
IOD3
TRDGRD register function select
Set to 1 (general register or buffer register) in the input capture function.
TRDGRD mode select
IOD2
Note 2
Set to 1 (input capture) in the input capture function.
IOD0
0
0
Input capture to TRDGRDi at the rising edge
TRDGRD control
0
1
Input capture to TRDGRDi at the falling edge
1
0
Input capture to TRDGRDi at both edges
1
1
Do not set.
Set to 1 (general register or buffer register) in the input capture function.
TRDGRC mode select
Note 3
Set to 1 (input capture) in the input capture function.
R/W
R/W
R/W
R/W
IOC1
IOC0
0
0
Input capture to TRDGRCi at the rising edge
0
1
Input capture to TRDGRCi at the falling edge
1
0
Input capture to TRDGRCi at both edges
1
1
Do not set.
Notes 1.
R/W
R/W
TRDGRC register function select
IOC2
R/W
R/W
IOD1
IOC3
R/W
R/W
TRDGRC control
R/W
R/W
The value after reset is undefined when FRQSEL4 = 1 in the user option byte (000C2H/010C2H) and
TRD0EN = 0 in the PER1 register. If it is necessary to read the initial value, set fCLK to fIH and TRD0EN = 1
<R>
before reading.
2.
If 1 (buffer register for TRDGRBi register) is selected for the BFDi bit in the TRDMR register, set the same
value to the IOB2 bit in the TRDIORAi register and the IOD2 bit in the TRDIORCi register.
3.
If 1 (buffer register for TRDGRAi register) is selected for the BFCi bit in the TRDMR register, set the same
value to the IOA2 bit in the TRDIORAi register and the IOC2 bit in the TRDIORCi register.
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Figure 8-23. Format of Timer RD I/O Control Register Ci (TRDIORCi) (i = 0 or 1) [Output Compare Function]
Address: F0272H (TRDIORC0), F0282H (TRDIORC1) After Reset: 88H
Note 1
Symbol
7
6
5
4
3
2
1
0
TRDIORCi
IOD3
IOD2
IOD1
IOD0
IOC3
IOC2
IOC1
IOC0
IOD3
TRDGRD register function select
0
(see 8. 3. 3 (2) Changing Output Pins in Registers TRDGRCi (i = 0 or 1) and TRDGRDi)
General register or buffer register
1
TRDGRD mode select
IOD2
Note 2
Set to 0 (output compare) in the output compare function.
IOD0
TRDGRD control
0
0
Pin output by compare match is disabled
0
1
Low output by compare match with TRDGRDi
1
0
High output by compare match with TRDGRDi
1
1
Toggle output by compare match with TRDGRDi
IOC3
TRDGRC register function select
R/W
R/W
(see 8. 3. 3 (2) Changing Output Pins in Registers TRDGRCi (i = 0 or 1) and TRDGRDi)
General register or buffer register
1
TRDGRC mode select
IOC2
Note 3
Set to 0 (output compare) in the output compare function.
R/W
R/W
IOC1
IOC0
0
0
Pin output by compare match is disabled
0
1
Low output by compare match with TRDGRCi
TRDGRC control
1
0
High output by compare match with TRDGRCi
1
1
Toggle output by compare match with TRDGRCi
Notes 1.
R/W
R/W
TRDIOA output register
0
R/W
R/W
IOD1
<R>
R/W
R/W
TRDIOB output register
R/W
R/W
The value after reset is undefined when FRQSEL4 = 1 in the user option byte (000C2H/010C2H) and
TRD0EN = 0 in the PER1 register. If it is necessary to read the initial value, set fCLK to fIH and TRD0EN = 1
before reading.
2.
If 1 (buffer register for TRDGRBi register) is selected for the BFDi bit in the TRDMR register, set the same
value to the IOB2 bit in the TRDIORAi register and the IOD2 bit in the TRDIORCi register.
3.
If 1 (buffer register for TRDGRAi register) is selected for the BFCi bit in the TRDMR register, set the same
value to the IOA2 bit in the TRDIORAi register and the IOC2 bit in the TRDIORCi register.
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8.2.14 Timer RD Status Register i (TRDSRi) (i = 0 or 1)
Figure 8-24. Format of Timer RD Status Register i (TRDSRi) (i = 0 or 1) [Input Capture Function]
Address: F0273H (TRDSR0), F0283H (TRDSR1) After Reset: 00H
Note 1
Symbol
7
6
5
4
3
2
1
0
TRDSRi
—
—
UDF
OVF
IMFD
IMFC
IMFB
IMFA
Bits 7 to 6
—
Nothing is assigned
R/W
The write value must be 0. The read value is 0.
R
Underflow flag
UDF
Note 2
R/W
Disabled in the input capture function.
Overflow flag
OVF
[Source for setting to 0]
Note
Write 0 after reading.
R/W
Note 3
R/W
R/W
4
[Source for setting to 1]
When the TRDi register overflows
Input capture/compare match flag D
IMFD
[Source for setting to 0]
Note
Write 0 after reading.
Note 7
R/W
R/W
4
[Source for setting to 1]
Note 5
Input edge of TRDIODi pin
Input capture/compare match flag C
IMFC
[Source for setting to 0]
Note
Write 0 after reading.
Note 7
R/W
R/W
4
[Source for setting to 1]
Note 5
Input edge of TRDIOCi pin
Input capture/compare match flag B
IMFB
[Source for setting to 0]
Note
Write 0 after reading.
Note 7
R/W
R/W
4
[Source for setting to 1]
Note 6
Input edge of TRDIOBi pin
Input capture/compare match flag A
IMFA
[Source for setting to 0]
Note
Write 0 after reading.
Note 7
R/W
R/W
4
[Source for setting to 1]
Note
Input edge of TRDIOAi pin
6
(Notes are listed on the next page.)
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Notes 1. The value after reset is undefined when FRQSEL4 = 1 in the user option byte (000C2H/010C2H) and
<R>
TRD0EN = 0 in the PER1 register. If it is necessary to read the initial value, set fCLK to fIH and TRD0EN = 1
before reading.
2. Nothing is assigned to bit 5 in the TRDSR0 register. The write value must be 0 for bit 5. The read value is 0.
3. When the counter value of timer RDi changes from FFFFH to 0000H, the overflow flag is set to 1. Also, if
the counter value of timer RDi changes from FFFFH to 0000H due to an input capture/compare match
during operation according to the settings of bits CCLR0 to CCLR2 in the TRDCRi register, the overflow
flag is set to 1.
4. The writing results are as follows:
• If the read value is 1, writing 0 to the bit sets it to 0.
• If the read value is 0, the bit remains unchanged even if 0 is written to it. (Even if the bit is changed from 0
to 1 after reading and then 0 is written to it, it remains 1.)
•
Writing 1 has no effect.
5. Edge selected by bits IOk1 and IOk0 (k = C or D) in the TRDIORCi register.
Including when the BFki bit in the TRDMR register is 1 (TRDGRki is buffer register).
6. Edge selected by bits IOj1 and IOj0 (j = A or B) in the TRDIORAi register.
7. When the DTC is used, bits IMFA, IMFB, IMFC, and IMFD are set to 1 after DTC transfer is completed.
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Figure 8-25. Format of Timer RD Status Register i (TRDSRi) (i = 0 or 1)
[Functions Other Than Input Capture Function]
Address: F0273H (TRDSR0), F0283H (TRDSR1) After Reset: 00H
Note 1
Symbol
7
6
5
4
3
2
1
0
TRDSRi
—
—
UDF
OVF
IMFD
IMFC
IMFB
IMFA
Bits 7 to 6
—
Nothing is assigned
R/W
The write value must be 0. The read value is 0.
R
Underflow flag
UDF
Note 2
R/W
R/W
In complementary PWM mode
[Source for setting to 0]
Write 0 after reading.
Note 3
[Sources for setting to 1]
When TRDi underflows.
Enabled only in complementary PWM mode.
Overflow flag
OVF
[Source for setting to 0]
Note
Write 0 after reading.
Note 4
R/W
R/W
3
[Source for setting to 1]
When the TRDi register overflows
Input capture/compare match flag D
IMFD
[Source for setting to 0]
Note
Write 0 after reading.
3
5
Input capture/compare match flag C
IMFC
Note 6
R/W
R/W
3
[Source for setting to 1]
Note
When the values of TRDi and TRDGRCi match.
5
Input capture/compare match flag B
IMFB
[Source for setting to 0]
Note
Write 0 after reading.
R/W
R/W
[Source for setting to 1]
Note
When the values of TRDi and TRDGRDi match.
[Source for setting to 0]
Note
Write 0 after reading.
Note 6
Note 6
R/W
R/W
3
[Source for setting to 1]
When the values of TRDi and TRDGRBi match.
Input capture/compare match flag A
IMFA
[Source for setting to 0]
Note
Write 0 after reading.
Note 6
R/W
R/W
3
[Source for setting to 1]
When the values of TRDi and TRDGRAi match.
(Notes are listed on the next page.)
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Notes 1. The value after reset is undefined when FRQSEL4 = 1 in the user option byte (000C2H/010C2H) and
<R>
TRD0EN = 0 in the PER1 register. If it is necessary to read the initial value, set fCLK to fIH and TRD0EN = 1
before reading.
2. Nothing is assigned to bit 5 in the TRDSR0 register. The write value must be 0 for bit 5. The read value is 0.
3. The writing results are as follows:
• If the read value is 1, writing 0 to the bit sets it to 0.
• If the read value is 0, the bit remains unchanged even if 0 is written to it. (Even if the bit is changed from 0
to 1 after reading and then 0 is written to it, it remains 1.)
• Writing 1 has no effect.
4. When the counter value of timer RDi changes from FFFFH to 0000H, the overflow flag is set to 1. Also, if
the counter value of timer RDi changes from FFFFH to 0000H due to an input capture/compare match
during operation according to the settings of bits CCLR0 to CCLR2 in the TRDCRi register, the overflow
flag is set to 1.
5. Including when the BFki bit (k = C or D) in the TRDMR register is set to 1 (TRDGRKi is buffer register).
6. When the DTC is used, bits IMFA, IMFB, IMFC, and IMFD are set to 1 after DTC transfer is completed.
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8.2.15 Timer RD Interrupt Enable Register i (TRDIERi) (i = 0 or 1)
Figure 8-26. Format of Timer RD Interrupt Enable Register i (TRDIERi) (i = 0 or 1)
Address: F0274H (TRDIER0), F0284H (TRDIER1) After Reset: 00H
Note
Symbol
7
6
5
4
3
2
1
0
TRDIERi
—
—
—
OVIE
IMIED
IMIEC
IMIEB
IMIEA
Bits 7 to 5
—
Nothing is assigned
The write value must be 0. The read value is 0.
OVIE
Overflow/underflow interrupt enable
0
Interrupt (OVI) by bits OVF and UDF disabled
1
Interrupt (OVI) by bits OVF and UDF enabled
IMIED
Input capture/compare match interrupt enable D
0
Interrupt (IMID) by the IMFD bit is disabled
1
Interrupt (IMID) by the IMFD bit is enabled
IMIEC
Input capture/compare match interrupt enable C
0
Interrupt (IMIC) by the IMFC bit is disabled
1
Interrupt (IMIC) by the IMFC bit is enabled
IMIEB
Input capture/compare match interrupt enable B
0
Interrupt (IMIB) by the IMFB bit is disabled
1
Interrupt (IMIB) by the IMFB bit is enabled
IMIEA
Input capture/compare match interrupt enable A
0
Interrupt (IMIA) by the IMFA bit is disabled
1
Interrupt (IMIA) by the IMFA bit is enabled
R/W
R
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Note The value after reset is undefined when FRQSEL4 = 1 in the user option byte (000C2H/010C2H) and TRD0EN = 0
<R>
in the PER1 register. If it is necessary to read the initial value, set fCLK to fIH and TRD0EN = 1 before reading.
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8.2.16 Timer RD PWM Function Output Level Control Register i (TRDPOCRi) (i = 0 or 1)
Settings to the TRDPOCRi register are enabled only in PWM function. When not in PWM function, they are disabled.
Figure 8-27. Format of Timer RD PWM Function Output Level Control Register i (TRDPOCRi) (i= 0 or 1)
[PWM Function]
Address: F0275H (TRDPOCR0), F0285H (TRDPOCR1) After Reset: 00H
Note
Symbol
7
6
5
4
3
2
1
0
TRDPOCRi
—
—
—
—
—
POLD
POLC
POLB
Bits 7 to 3
—
Nothing is assigned
The write value must be 0. The read value is 0.
POLD
PWM function output level control D
0
TRDIODi output level is low active
1
TRDIODi output level is high active
POLC
PWM function output level control C
0
TRDIOCi output level is low active
1
TRDIOCi output level is high active
POLB
PWM function output level control B
0
TRDIOBi output level is low active
1
TRDIOBi output level is high active
R/W
R
R/W
R/W
R/W
R/W
R/W
R/W
Note The value after reset is undefined when FRQSEL4 = 1 in the user option byte (000C2H/010C2H) and TRD0EN = 0
<R>
in the PER1 register. If it is necessary to read the initial value, set fCLK to fIH and TRD0EN = 1 before reading.
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8.2.17 Timer RD Counter i (TRDi) (i = 0 or 1)
[Timer Mode]
Access the TRDi register in 16-bit units. Do not access it in 8-bit units.
[Reset Synchronous PWM Mode and PWM3 Mode]
Access the TRD0 register in 16-bit units. Do not access it in 8-bit units. The TRD1 register is not used in reset
synchronous PWM mode and PWM3 mode.
[Complementary PWM Mode (TRD0)]
Access the TRD0 register in 16-bit units. Do not access it in 8-bit units.
[Complementary PWM Mode (TRD1)]
Access the TRD1 register in 16-bit units. Do not access it in 8-bit units.
Figure 8-28. Format of Timer RD Counter i (TRDi) (i = 0 or 1) [Timer Mode]
Address: F0276H (TRD0), F0286H (TRD1) After Reset: 0000H
Note
Symbol
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
TRDi
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
Bits 15 to 0
Function
Setting Range
Count the count source. Count operation is incremented.
R/W
0000H to FFFFH
R/W
When an overflow occurs, the OVF bit in the TRDSRi register is set to 1.
Note The value after reset is undefined when FRQSEL4 = 1 in the user option byte (000C2H/010C2H) and TRD0EN = 0
<R>
in the PER1 register. If it is necessary to read the initial value, set fCLK to fIH and TRD0EN = 1 before reading.
Figure 8-29. Format of Timer RD Counter i (TRDi) (i = 0 or 1) [Reset Synchronous PWM Mode and PWM3 Mode]
Address: F0276H (TRD0), F0286H (TRD1) After Reset: 0000H
Note
Symbol
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
TRDi
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
Bits 15 to 0
Function
Count the count source. Count operation is incremented.
Setting Range
0000H to FFFFH
R/W
R/W
When an overflow occurs, the OVF bit in the TRDSR0 register is set to 1.
Note The value after reset is undefined when FRQSEL4 = 1 in the user option byte (000C2H/010C2H) and TRD0EN = 0
<R>
in the PER1 register. If it is necessary to read the initial value, set fCLK to fIH and TRD0EN = 1 before reading.
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Figure 8-30. Format of Timer RD Counter i (TRDi) (i = 0 or 1) [Complementary PWM Mode (TRD0)]
Address: F0276H (TRD0), F0286H (TRD1) After Reset: 0000H
Note
Symbol
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
TRDi
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
Bits 15 to 0
Function
Setting Range
Dead time must be set.
R/W
0001H to FFFFH
R/W
Count the count source. Count operation is incremented or decremented.
When an overflow occurs, the OVF bit in the TRDSR0 register is set to 1.
Note The value after reset is undefined when FRQSEL4 = 1 in the user option byte (000C2H/010C2H) and TRD0EN = 0
<R>
in the PER1 register. If it is necessary to read the initial value, set fCLK to fIH and TRD0EN = 1 before reading.
Figure 8-31. Format of Timer RD Counter i (TRDi) (i = 0 or 1) [Complementary PWM Mode (TRD1)]
Address: F0276H (TRD0), F0286H (TRD1) After Reset: 0000H
Note
Symbol
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
TRDi
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
Bits 15 to 0
Function
Set to 0000H.
Setting Range
0000H to FFFFH
R/W
R/W
Count the count source. Count operation is incremented or decremented.
When an underflow occurs, the UDF bit in the TRDSR1 register is set to 1.
Note The value after reset is undefined when FRQSEL4 = 1 in the user option byte (000C2H/010C2H) and TRD0EN = 0
<R>
in the PER1 register. If it is necessary to read the initial value, set fCLK to fIH and TRD0EN = 1 before reading.
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8.2.18 Timer RD General Registers Ai, Bi, Ci, and Di (TRDGRAi, TRDGRBi,TRDGRCi, TRDGRDi) (i = 0 or 1)
[Input Capture Function]
Access registers TRDGRAi to TRDGRDi in 16-bit units. Do not access them in 8-bit units.
The following registers are disabled in the input capture function:
TRDOER1, TRDOER2, TRDOCR, TRDPOCR0, and TRDPOCR1
Set the pulse width of the input capture signal applied to the TRDIOji pin to three or more cycles of the timer RD
operating clock (fCLK) when no digital filter is used (the DFj bit in the TRDDFi register is 0).
[Output Compare Function]
Access registers TRDGRAi to TRDGRDi in 16-bit units. Do not access them in 8-bit units.
The following registers are disabled in the output compare function:
TRDDF0, TRDDF1, TRDPOCR0, and TRDPOCR1
[PWM Function]
Access registers TRDGRAi to TRDGRDi in 16-bit units. Do not access them in 8-bit units.
The following registers are disabled in PWM function:
TRDDF0, TRDDF1, TRDIORA0, TRDIORC0, TRDIORA1, and TRDIORC1
[Reset Synchronous PWM Mode]
Access registers TRDGRAi to TRDGRDi in 16-bit units. Do not access them in 8-bit units.
The following registers are disabled in reset synchronous PWM mode:
TRDPMR, TRDOCR Note , TRDDF0, TRDDF1, TRDIORA0, TRDIORC0, TRDPOCR0, TRDIORA1, TRDIORC1, and
TRDPOCR1
Note The TOC0 bit in the TRDOCR register is enabled as an initial output setting of TRDIOC0 in reset synchronous
PWM mode and complementary PWM mode.
[Complementary PWM Mode]
Access registers TRDGRAi to TRDGRDi in 16-bit units. Do not access them in 8-bit units.
The TRDGRC0 register is not used in complementary PWM mode.
The following registers are disabled in complementary PWM mode.
TRDPMR, TRDOCR Note , TRDDF0 TRDDF1, TRDIORA0, TRDIORC0, TRDPOCR0, TRDIORA1, TRDIORC1, and
TRDPOCR1
Note The TOC0 bit in the TRDOCR register is enabled as an initial output setting of TRDIOC0 in reset synchronous
PWM mode and complementary PWM mode.
Since values cannot be written to the TRDGRB0, TRDGRA1, or TRDGRB1 register directly after count operation starts
(prohibited item), use the TRDGRD0, TRDGRC1, or TRDGRD1 register as a buffer register.
However, to write data to the TRDGRD0, TRDGRC1, or TRDGRD1 register, set bits TRDBFD0, TRDBFC1, and
TRDBFD1 to 0 (general register). After this, bits TRDBFD0, TRDBFC1, and TRDBFD1 may be set to 1 (buffer register).
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[PWM3 Mode]
Access registers TRDGRAi to TRDGRDi in 16-bit units. Do not access them in 8-bit units.
The following registers are disabled in PWM3 mode:
TRDPMR, TRDDF0, TRDDF1, TRDIORA0, TRDIORC0, TRDPOCR0, TRDIORA1, TRDIORC1, and TRDPOCR1
Registers TRDGRC0, TRDGRC1, TRDGRD0, and TRDGRD1 are not used in PWM3 mode. To use them as buffer
registers, set bits TRDBFC0, TRDBFC1, TRDBFD0, and TRDBFD1 to 0 (general register) and write a value to the
TRDGRC0, TRDGRC1, TRDGRD0, or TRDGRD1 register. After this, bits TRDBFC0, TRDBFC1, TRDBFD0, and
TRDBFD1 may be set to 1 (buffer register).
Figure 8-32. Format of Timer RD General Registers Ai, Bi, Ci, and Di (TRDGRAi, TRDGRBi,TRDGRCi, TRDGRDi)
(i = 0 or 1) [Input Capture Function]
Address: F0278H (TRDGRA0), F027AH (TRDGRB0),
After Reset: FFFFH
Note
FFF58H (TRDGRC0), FFF5AH (TRDGRD0),
F0288H (TRDGRA1), F028AH (TRDGRB1),
FFF5CH (TRDGRC1), FFF5EH (TRDGRD1)
Symbol
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
TRDGRAi
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
TRDGRBi
TRDGRCi
TRDGRDi
—
Function
Bits 15 to 0
R/W
See Table 8-3 TRDGRji Register Functions in Input Capture Function.
R/W
Note The value after reset is undefined when FRQSEL4 = 1 in the user option byte (000C2H/010C2H) and TRD0EN = 0
<R>
in the PER1 register. If it is necessary to read the initial value, set fCLK to fIH and TRD0EN = 1 before reading.
Table 8-3 TRDGRji Register Functions in Input Capture Function
Register
TRDGRAi
Setting
—
Register Function
Input-Capture Input Pin
General register. The value of the TRDi register can be read at
TRDIOAi
input capture.
TRDIOBi
BFCi = 0
General register. The value of the TRDi register can be read at
TRDIOCi
TRDGRDi
BFDi = 0
input capture.
TRDIODi
TRDGRCi
BFCi = 1
Buffer register. The value of the TRDi register can be read at
TRDIOAi
TRDGRDi
BFDi = 1
input capture (see 8. 3. 1 (2) Buffer Operation).
TRDIOBi
TRDGRBi
TRDGRCi
Remark
i = 0 or 1, j = A, B, C, or D
BFCi, BFDi: Bits in TRDMR register
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Figure 8-33. Format of Timer RD General Registers Ai, Bi, Ci, and Di (TRDGRAi, TRDGRBi, TRDGRCi, TRDGRDi)
(i = 0 or 1) [Output Compare Function]
Address: F0278H (TRDGRA0), F027AH (TRDGRB0),
After Reset: FFFFH
Note
FFF58H (TRDGRC0), FFF5AH (TRDGRD0),
F0288H (TRDGRA1), F028AH (TRDGRB1),
FFF5CH (TRDGRC1), FFF5EH (TRDGRD1)
Symbol
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
TRDGRAi
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
TRDGRBi
TRDGRCi
TRDGRDi
—
Function
Bits 15 to 0
R/W
See Table 8-4 TRDGRji Register Functions in Output Compare Function.
R/W
Note The value after reset is undefined when FRQSEL4 = 1 in the user option byte (000C2H/010C2H) and TRD0EN = 0
<R>
in the PER1 register. If it is necessary to read the initial value, set fCLK to fIH and TRD0EN = 1 before reading.
Table 8-4 TRDGRji Register Functions in Output Compare Function
Register
TRDGRAi
Setting
BFji
IOj3
—
—
Register Function
Output Pin
General register. Write the compare value.
TRDGRBi
TRDGRCi
0
1
General register. Write the compare value.
TRDIOCi
1
1
Buffer register. Write the next compare value
TRDIOAi
(see 8. 3. 1 (2) Buffer Operation).
TRDIOBi
TRDIOAi
TRDIODi
TRDGRDi
TRDGRCi
TRDIOAi
TRDIOBi
TRDGRDi
TRDGRCi
Output-Compare
0
0
TRDGRDi
TRDIOAi output
(See 8. 3. 3 (2) Changing Output Pins in
control
Registers TRDGRCi (i = 0 or 1) and
TRDIOBi output
TRDGRDi.)
TRDIOBi
control
Caution When the setting of bits TCK2 to TCK0 in the TRDCRi register is 000B (fCLK, fHOCO) and the compare
value is set to 0000H, a request signal to the data transfer controller (DTC) and the event link
controller (ELC) is generated only once immediately after the count starts. When the compare value
is 0001H or higher, a request signal is generated each time a compare match occurs.
Remark
i = 0 or 1, j = A, B, C, or D
BFji: Bit in TRDMR register, IOj3: Bit in TRDIORCi register
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Figure 8-34. Format of Timer RD General Registers Ai, Bi, Ci, and Di (TRDGRAi, TRDGRBi,TRDGRCi, TRDGRDi)
(i = 0 or 1) [PWM Mode]
Address: F0278H (TRDGRA0), F027AH (TRDGRB0),
After Reset: FFFFH
Note
FFF58H (TRDGRC0), FFF5AH (TRDGRD0),
F0288H (TRDGRA1), F028AH (TRDGRB1),
FFF5CH (TRDGRC1), FFF5EH (TRDGRD1)
Symbol
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
TRDGRAi
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
TRDGRBi
TRDGRCi
TRDGRDi
—
Function
Bits 15 to 0
R/W
See Table 8-5 TRDGRji Register Functions in PWM Function.
R/W
Note The value after reset is undefined when FRQSEL4 = 1 in the user option byte (000C2H/010C2H) and TRD0EN = 0
<R>
in the PER1 register. If it is necessary to read the initial value, set fCLK to fIH and TRD0EN = 1 before reading.
Table 8-5 TRDGRji Register Functions in PWM Function
Register
Setting
Register Function
PWM Output Pin
TRDGRAi
—
General register. Set the PWM period.
—
TRDGRBi
—
General register. Set the changing point of PWM output.
TRDIOBi
TRDGRCi
BFCi = 0
General register. Set the changing point of PWM output.
TRDGRDi
BFDi = 0
TRDGRCi
BFCi = 1
TRDIOCi
TRDIODi
Buffer register. Set the next PWM period
—
(see 8. 3. 1 (2) Buffer Operation).
TRDGRDi
BFDi = 1
Buffer register. Set the changing point of the next PWM output
TRDIOBi
(see 8. 3. 1 (2) Buffer Operation).
Caution When the setting of bits TCK2 to TCK0 in the TRDCRi register is 000B (fCLK, fHOCO) and the compare
value is set to 0000H, a request signal to the data transfer controller (DTC) and the event link
controller (ELC) is generated only once immediately after the count starts. When the compare value
is 0001H or higher, a request signal is generated each time a compare match occurs.
Remark
i = 0 or 1, j = A, B, C, or D
BFCi, BFDi: Bits in TRDMR register
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Figure 8-35. Format of Timer RD General Registers Ai, Bi, Ci, and Di (TRDGRAi, TRDGRBi,TRDGRCi, TRDGRDi)
(i = 0 or 1) [Reset Synchronous PWM Mode]
Address: F0278H (TRDGRA0), F027AH (TRDGRB0),
After Reset: FFFFH
Note
FFF58H (TRDGRC0), FFF5AH (TRDGRD0),
F0288H (TRDGRA1), F028AH (TRDGRB1),
FFF5CH (TRDGRC1), FFF5EH (TRDGRD1)
Symbol
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
TRDGRAi
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
TRDGRBi
TRDGRCi
TRDGRDi
—
Function
Bits 15 to 0
R/W
See Table 8-6 TRDGRji Register Functions in Reset Synchronous PWM Mode.
R/W
Note The value after reset is undefined when FRQSEL4 = 1 in the user option byte (000C2H/010C2H) and TRD0EN = 0
<R>
in the PER1 register. If it is necessary to read the initial value, set fCLK to fIH and TRD0EN = 1 before reading.
Table 8-6 TRDGRji Register Functions in Reset Synchronous PWM Mode
Register
TRDGRA0
Setting
—
Register Function
General register. Set the PWM period.
PWM Output Pin
(TRDIOC0, output
inverted every
PWM period)
TRDGRB0
—
General register. Set the changing point of PWM1 output.
TRDIOB0
TRDGRC0
TRDBFC0 = 0
(Not used in reset synchronous PWM mode.)
—
General register. Set the changing point of PWM2 output.
TRDIOA1
TRDIOD0
TRDGRD0
TRDBFC0 = 0
TRDGRA1
—
TRDIOC1
TRDGRB1
—
General register. Set the changing point of PWM3 output.
TRDIOB1
TRDGRC1
TRDBFC1= 0
(Not used in reset synchronous PWM mode.)
—
TRDGRD1
TRDBFD1 = 0
TRDGRC0
TRDBFC0 = 1
Buffer register. Set the next PWM period
(TRDIOC0, output
(see 8. 3. 1 (2) Buffer Operation).
inverted every
TRDIOD1
PWM period)
TRDGRD0
TRDGRC1
TRDGRD1
Caution
TRDBFD0 = 1
TRDBFC1 = 1
TRDBFD1 = 1
Buffer register. Set the changing point of the next PWM1
TRDIOB0
(see 8. 3. 1 (2) Buffer Operation).
TRDIOD0
Buffer register. Set the changing point of the next PWM2
TRDIOA1
(see 8. 3. 1 (2) Buffer Operation).
TRDIOC1
Buffer register. Set the changing point of the next PWM3
TRDIOB1
(see 8. 3. 1 (2) Buffer Operation).
TRDIOD1
When the setting of bits TCK2 to TCK0 in the TRDCR0 register is 000B (fCLK, fHOCO) and the compare
value is set to 0000H, a request signal to the data transfer controller (DTC) and the event link
controller (ELC) is generated only once immediately after the count starts. When the compare value
is 0001H or higher, a request signal is generated each time a compare match occurs.
Remark
i = 0 or 1, j = A, B, C, or D
TRDBFC0, TRDBFD0, TRDBFC1, TRDBFD1: Bits in TRDMR register
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Figure 8-36. Format of Timer RD General Registers Ai, Bi, Ci, and Di (TRDGRAi, TRDGRBi,TRDGRCi, TRDGRDi)
(i = 0 or 1) [Complementary PWM Mode]
Address: F0278H (TRDGRA0), F027AH (TRDGRB0),
After Reset: FFFFH
Note
FFF58H (TRDGRC0), FFF5AH (TRDGRD0),
F0288H (TRDGRA1), F028AH (TRDGRB1),
FFF5CH (TRDGRC1), FFF5EH (TRDGRD1)
Symbol
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
TRDGRAi
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
TRDGRBi
TRDGRCi
TRDGRDi
—
Bits 15 to 0
Function
See Table 8-7 TRDGRji Register Functions in Complementary PWM Mode.
R/W
R/W
Note The value after reset is undefined when FRQSEL4 = 1 in the user option byte (000C2H/010C2H) and TRD0EN = 0
<R>
in the PER1 register. If it is necessary to read the initial value, set fCLK to fIH and TRD0EN = 1 before reading.
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Table 8-7 TRDGRji Register Functions in Complementary PWM Mode
Register
Setting
TRDGRA0
—
TRDGRB0
—
TRDGRA1
—
TRDGRB1
—
TRDGRC0
—
TRDGRD0
TRDBFD0 = 1
TRDGRC1
TRDBFC1 = 1
TRDGRD1
TRDBFD1 = 1
Caution
Register Function
General register. Set the PWM period at initialization.
Setting range: ≥ Value set in TRD0 register
≤ FFFFh - value set in TRD0 register
Do not write to this register when bits TSTART0 and TSTART1
in the TRDSTR register are set to 1 (count starts).
General register. Set the changing point of PWM1 output at initialization.
Setting range: ≥ Value set in TRD0 register
≤ Value set in TRDGRA0 register - value set in TRD0 register
Do not write to this register when bits TSTART0 and TSTART1
in the TRDSTR register are set to 1 (count starts).
General register. Set the changing point of PWM2 output at initialization.
Setting range: ≥ Value set in TRD0 register
≤ Value set in TRDGRA0 register - value set in TRD0 register
Do not write to this register when bits TSTART0 and TSTART1
in the TRDSTR register are set to 1 (count starts).
General register. Set the changing point of PWM3 output at initialization.
Setting range: ≥ Value set in TRD0 register
≤ Value set in TRDGRA0 register - value set in TRD0 register
Do not write to this register when bits TSTART0 and TSTART1
in the TRDSTR register are set to 1 (count starts).
(Not used in complementary PWM mode.)
Buffer register. Set the changing point of next PWM1 output
(see 8. 3. 1 (2) Buffer Operation).
Setting range: ≥ Value set in TRD0 register
≤ Value set in TRDGRA0 register - value set in TRD0 register
Set this register to the same value as the TRDGRB0 register for
initialization.
Buffer register. Set the changing point of next PWM2 output
(see 8. 3. 1 (2) Buffer Operation).
Setting range: ≥ Value set in TRD0 register
≤ Value set in TRDGRA0 register - value set in TRD0 register
Set this register to the same value as the TRDGRA1 register
for initialization.
Buffer register. Set the changing point of next PWM3 output
(see 8. 3. 1 (2) Buffer Operation).
Setting range: ≥ Value set in TRD0 register
≤ Value set in TRDGRA0 register - value set in TRD0 register
Set this register to the same value as the TRDGRB1 register
for initialization.
PWM
Output Pin
(TRDIOC0,
output
inverted
every half
period)
TRDIOB0
TRDIOD0
TRDIOA1
TRDIOC1
TRDIOB1
TRDIOD1
—
TRDIOB0
TRDIOD0
TRDIOA1
TRDIOC1
TRDIOB1
TRDIOD1
When the setting of bits TCK2 to TCK0 in the TRDCRi register is 000B (fCLK, fHOCO) and the compare
value is set to 0000H, a request signal to the data transfer controller (DTC) and the event link
controller (ELC) is generated only once immediately after the count starts. When the compare value
is 0001H or higher, a request signal is generated each time a compare match occurs.
Remark
i = 0 or 1, j = A, B, C, or D
TRDBFD0, TRDBFC1, TRDBFD1: Bits in TRDMR register
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Figure 8-37. Format of Timer RD General Registers Ai, Bi, Ci, and Di (TRDGRAi, TRDGRBi,TRDGRCi, TRDGRDi)
(i = 0 or 1) [PWM3 Mode]
Address: F0278H (TRDGRA0), F027AH (TRDGRB0),
After Reset: FFFFH
Note
FFF58H (TRDGRC0), FFF5AH (TRDGRD0),
F0288H (TRDGRA1), F028AH (TRDGRB1),
FFF5CH (TRDGRC1), FFF5EH (TRDGRD1)
Symbol
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
TRDGRAi
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
TRDGRBi
TRDGRCi
TRDGRDi
—
Bits 15 to 0
Function
See Table 8-8 TRDGRji Register Functions in PWM3 Mode.
R/W
R/W
Note The value after reset is undefined when FRQSEL4 = 1 in the user option byte (000C2H/010C2H) and TRD0EN = 0
<R>
in the PER1 register. If it is necessary to read the initial value, set fCLK to fIH and TRD0EN = 1 before reading.
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Table 8-8 TRDGRji Register Functions in PWM3 Mode
Register
Setting
TRDGRA0
—
TRDGRA1
Register Function
General register. Set the PWM period .
Setting range: ≥ Value set in TRDGRA1 register
General register. Set the changing point (active level timing) of PWM output
Setting range: ≤ Value set in TRDGRA0 register
TRDGRB0
General register. Set the changing point (the timing for returning to initial
output level) of PWM output.
Setting range: ≥ Value set in TRDGRB1 register and ≤ Value set in
TRDGRA0 register
TRDGRB1
General register. Set the changing point (active level timing) of PWM output
Setting range: ≤ Value set in TRDGRB0 register
TRDGRC0
TRDBFC0 = 0
TRDGRC1
TRDBFC1 = 0
TRDGRD0
TRDBFD0 = 0
PWM Output
Pin
TRDIOA0
TRDIOB0
(Not used in PWM3 mode.)
—
Buffer register. Set the next PWM period (see 8. 3. 1 (2) Buffer Operation).
Setting range: ≥ Value set in TRDGRC1 register
Buffer register. Set the changing point of next PWM output
(see 8. 3. 1 (2) Buffer Operation).
Setting range: ≤ Value set in TRDGRC0 register
TRDIOA0
TRDIOB0
TRDGRD1
TRDBFD1 = 0
TRDGRC0
TRDBFC0 = 1
TRDGRC1
TRDBFC1 = 1
TRDGRD0
TRDBFD0 = 1
Buffer register. Set the changing point of next PWM output
(see 8. 3. 1 (2) Buffer Operation).
Setting range: ≥ Value set in TRDGRD1 register and ≤ Value set in
TRDGRC0 register
TRDGRD1
TRDBFD1 = 1
Buffer register. Set the changing point of next PWM output
(see 8. 3. 1 (2) Buffer Operation).
Setting range: ≤ Value set in TRDGRD0 register
Caution When the setting of bits TCK2 to TCK0 in the TRDCR0 register is 000B (fCLK, fHOCO) and the compare
value is set to 0000H, a request signal to the data transfer controller (DTC) and the event link
controller (ELC) is generated only once immediately after the count starts. When the compare value
is 0001H or higher, a request signal is generated each time a compare match occurs.
Remark
i = 0 or 1, j = A, B, C, or D
TRDBFC0, TRDBFD0, TRDBFC1, TRDBFD1: Bits in TRDMR register
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8.2.19 Port mode register 1 (PM1)
This register sets input/output of port 1 in 1-bit units.
When using the ports (P10/TRDIOD1, P11/TRDIOC1, etc.) to be shared with the timer output pin for timer output, set
the port mode register (PMxx) bit and port register (Pxx) bit corresponding to each port to 0.
Example: When using P10/TRDIOD1 for timer output
Set the PM10 bit of port mode register 1 to 0.
Set the P10 bit of port register 1 to 0.
When using the ports (P10/TRDIOD1, P11/TRDIOC1, etc.) to be shared with the timer input pin for timer input, set the
port mode register (PMxx) bit corresponding to each port to 1. At this time, the port register (Pxx) bit may be 0 or 1.
Example: When using P10/TRDIOD1 for timer input
Set the PM10 bit of port mode register 1 to 1.
Set the P10 bit of port register 1 to 0 or 1.
The PM1 register can be set by a 1-bit or 8-bit memory manipulation instruction.
Reset signal generation sets this register to FFH.
Figure 8-38. Format of Port Mode Register 1 (100-pin products)
Address: FFF21H
After reset: FFH
R/W
Symbol
7
6
5
4
3
2
1
0
PM1
PM17
PM16
PM15
PM14
PM13
PM12
PM11
PM10
Pmn pin I/O mode selection
PMmn
(m = 1; n = 0 to 7)
Remark
0
Output mode (output buffer on)
1
Input mode (output buffer off)
The figure shown above presents the format of port mode register 1 of the 100-pin products. The format of
the port mode register of other products, see Table 4-5. or Table 4-6. PMxx, Pxx, PUxx, PIMxx, POMxx,
PMCxx registers and the bits mounted on each product.
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8.3 Operation
8.3.1 Items Common to Multiple Modes
(1) Count Sources
The count source selection method is the same in all modes. However, the external clock cannot be selected
in PWM3 mode.
Table 8-9. Count Source Selection
Count Source
fCLK, fHOCO
Note
Selection
, fCLK/2,
The count source is selected by bits TCK2 to TCK0 in the TRDCRi register.
fCLK/4, fCLK/8, fCLK/32
External signal input to
The STCLK bit in the TRDFCR register is set to 1 (external clock input enabled).
TRDCLK pin
Bits TCK2 to TCK0 in the TRDCRi register are set to 101B (count source: external clock).
The active edge is selected by bits CKEG1 and CKEG0 in the TRDCRi register.
The port mode register bit for the I/O port multiplexed with the TRDCLK pin is set to 1 (input mode).
Remark
Note
<R>
i = 0 or 1
fCLK is selected when FRQSEL4 = 0 and fHOCO is selected when FRQSEL4 = 1 in the user option byte
(000C2H/010C2H). When selecting fHOCO as the count source for timer RD, set fCLK to fIH before setting bit 4
(TRD0EN) in peripheral enable register 1 (PER1). When changing fCLK to a clock other than fIH, clear bit 4
(TRD0EN) in peripheral enable register 1 (PER1) before changing.
Figure 8-39. Count Source Block Diagram
FRQSEL4 = 0
fCLK
TCK2 to TCK0
fHOCO
= 000B
FRQSEL4 = 1
= 001B
fCLK/2
= 010B
fCLK/4
Count source
= 011B
fCLK/8
TRDi register
= 100B
fCLK/32
STCLK = 1
TRDCLK/
TRDIOA0
CKEG0 and CKEG1
Active edge
selection
= 101B
TRDIOA0 I/O or I/O port
STCLK = 0
Remark
i = 0 or 1
TCK0 to TCK2, CKEG0, CKEG1: Bits in TRDCRi register
STCLK: Bit in TRDFCR register
FRQSEL4: Bit in user option byte (000C2H/010C2H)
Set the pulse width of the external clock applied to the TRDCLK pin to three or more cycles of the timer RD
operating clock (fCLK).
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(2) Buffer Operation
The TRDGRCi register (i = 0 or 1) can be used as the buffer register for the TRDGRAi register, and the TRDGRDi
register can be used as the buffer register for the TRDGRBi register by means of bits BFCi and BFDi in the TRDMR
register.
• TRDGRAi buffer register: TRDGRCi register
• TRDGRBi buffer register: TRDGRDi register
Buffer operation depends on the mode. Table 8-10 lists the Buffer Operation in Each Mode.
Table 8-10. Buffer Operation in Each Mode
Function and Mode
Timer
Transfer Timing
Transfer Register
Input capture function
Input capture signal input
Output compare function
Compare match with TRDi register and
Transfer content of buffer register to
PWM function
TRDGRAi (TRDGRBi) register
TRDGRAi (TRDGRBi) register
Compare match with TRD0 register and
Transfer content of buffer register to
TRDGRA0 register
TRDGRAi (TRDGRBi) register
Compare match with TRD0 register and
Transfer content of buffer register to
TRDGRA0 register
registers TRDGRB0, TRDGRA1, and
TRD1 register underflow
TRDGRB1
Compare match with TRD0 register and
Transfer content of buffer register to
TRDGRA0 register
TRDGRAi (TRDGRBi) register
mode
Transfer content of TRDGRAi
(TRDGRBi) register to buffer register
Reset synchronous PWM mode
Complementary PWM mode
PWM3 mode
Remark i = 0 or 1
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Figure 8-40. Buffer Operation in Input Capture Function
TRDIOAi input
(input capture signal)
TRDGRAi
register
TRDGRCi register
(buffer)
TRDi
TRDIOAi input
TRDi register
n
n-1
n+1
Transfer
TRDGRAi register
m
n
Transfer
TRDGRCi register
(buffer)
m
Remark
i = 0 or 1
The above diagram applies under the following conditions:
• The BFCi bit in the TRDMR register is set to 1 (TRDGRCi register is buffer register for TRDGRAi register).
• Bits IOA2 to IOA0 in the TRDIORAi register are set to 100B (input capture at the rising edge).
Figure 8-41. Buffer Operation in Output Compare Function
Compare match signal
TRDGRAi
register
TRDGRCi register
(buffer)
TRDi register
TRDGRAi register
Comparator
m
m-1
TRDi
m+1
m
n
Transfer
TRDGRCi register
(buffer)
n
TRDIOAi output
Remark
i = 0 or 1
The above diagram applies under the following conditions:
• The BFCi bit in the TRDMR register is set to 1 (TRDGRCi register is buffer register for TRDGRAi register).
• Bits IOA2 to IOA0 in the TRDIORAi register are set to 001B (low output by compare match).
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Perform the following for the timer mode (input capture and output compare functions).
When using the TRDGRCi (i = 0 or 1) register as the buffer register for the TRDGRAi register
• Set the IOC3 bit in the TRDIORCi register to 1 (general register or buffer register).
• Set the IOC2 bit in the TRDIORCi register to the same value as the IOA2 bit in the TRDIORAi register.
When using the TRDGRDi register as the buffer register for the TRDGRBi register
• Set the IOD3 bit in the TRDIORCi register to 1 (general register or buffer register).
• Set the IOD2 bit in the TRDIORCi register to the same value as the IOB2 bit in the TRDIORAi register.
In the input capture function, when the TRDGRCi register or TRDGRDi register is used as a buffer register, the
IMFC bit or IMFD bit in the TRDSRi register is set to 1 at the input edge of the TRDIOCi pin or TRDIODi pin.
When also using registers TRDGRCi and TRDGRDi as buffer registers for the output compare function, PWM
function, reset synchronous PWM mode, complementary PWM mode, and PWM3 mode, bits IMFC and IMFD in
the TRDSRi register are set to 1 by a compare match with the TRDi register.
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(3) Synchronous Operation
The TRD1 register is synchronized with the TRD0 register
• Synchronous preset
When the TRDSYNC bit in the TRDMR register is set to 1 (synchronous operation), the data is written to both the
TRD0 and TRD1 registers after writing to the TRDi register.
• Synchronous clear
When the TRDSYNC bit is 1 and bits CCLR2 to CCLR0 in the TRDCR0 register are 011B (synchronous clear),
the TRD0 register is set to 0000H at the same time as the TRD1 register is set to 0000H.
Also, when the TRDSYNC bit is 1 and bits CCLR2 to CCLR0 are 011B (synchronous clear), the TRD1 register is
set to 0000H at the same time as the TRD0 register is set to 0000H.
Figure 8-42. Synchronous Operation
TRDIOA0 input
Set to 0000H by input capture
Value in
TRD0 register
n
n writing
n is set
Value in
TRD1 register
n
n is set
Set to 0000H in synchronization with TRD0
The above diagram applies under the following conditions:
• The TRDSYNC bit in the TRDMR register is set to 1 (synchronous operation).
• Bits CCLR2 to CCLR0 in the TRDCR0 register are set to 001B (TRD0 is set to 0000H by input capture).
Bits CCLR2 to CCLR0 in the TRDCR1 register are set to 011B (TRD1 is set to 0000H in synchronization with TRD0).
• Bits IOA2 to IOA0 in the TRDIORA0 register are set to 100B.
• Bits CMD1 to CMD0 in the TRDFCR register are set to 00B. (Input capture at the rising edge of TRDIOA0 input)
The PWM 3 bit in the TRDFCR register is set to 1.
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(4) Pulse Output Forced Cutoff
In the PWM function, reset synchronous PWM mode, complementary PWM mode, and PWM3 mode, the TRDIOji
output pin (i = 0 or 1, j = A, B, C, or D) can be forcibly set to an I/O port by the INTP0 pin input, and pulse output
can be cut off.
The pins used for output in these functions or modes can function as the output pin of timer RD when the
corresponding bit in the TRDOER1 register is set to 0 (timer RD output enabled). When the TRDPTO bit in the
TRDOER2 register is 1 (pulse output forced cutoff signal input INTP0 enabled), the output pin used as a timer RD
output port outputs the output value set by the DFCK1, DFCK0, PENB1, PENB0, DFD, DFC, DFB, or DFA bit in the
TRDDF0 or TRDDF1 register.
Make the following settings to use this function:
• Set the pin state when the pulse output is forcibly cut off (high impedance, low output, or high output) using
TRDDFi.
• Refer to 8. 3. 1 (5) Event Input from Event Link Controller (ELC) for details on pulse forced cutoff by ELC
event input.
• When pulse output is forcibly cut out, the TRDSHUTS bit in the TRDOER2 register is set to 1. To suspend the
forced cutoff of the pulse output, set the TRDSHUTS bit to 0 while the count is stopped (TSTARTi = 0).
• Set the TRDPTO bit in the TRDOER2 register to 1 (pulse output forced cutoff signal input INTP0 enabled).
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Figure 8-43. Pulse Output Forced Cutoff
Setting when cutting off
ELC event input 0 operation
TRDSHUTS bit
INTP0 input
Timer RD output data
D Q
TRDPTO
ELC event input 1 operation
S
SFR write
Output data from
multiplexed I/O
port
TRDIOA0
Hi-Z selection signal
GPIO direction register
Input data to
multiplexed I/O port
Setting when cutting off
Timer RD output data
Output data from
multiplexed I/O
port
TRDIOB0
Hi-Z selection signal
GPIO direction register
Input data to
multiplexed I/O port
Setting when cutting off
Timer RD output data
TRDIOC1
Output data from
multiplexed I/O
port
Hi-Z selection signal
GPIO direction register
Input data to
multiplexed I/O port
Setting when cutting off
Timer RD output data
TRDIOD1
Output data from
multiplexed I/O
port
Hi-Z selection signal
GPIO direction register
TRDPTO, TRDSHUTS: Bits in TRDOER2 register
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(5) Event Input from Event Link Controller (ELC)
Timer RD performs two operations by event input from the ELC.
(a) Input capture operation D0/D1
Timer RD performs input capture operation D0/D1 by event input from the ELC. The IMFD bit in the TRDSRi
register is set to 1 at this time. To use this function, select the input capture function in timer mode and set the
ELCICE0 or ELCICE1 bit in the TRDELC register to 1. This function is disabled in any other modes (for the
output compare function in timer mode, PWM function, reset synchronous PWM mode, complementary PWM
mode, and PWM3 mode).
(b) Pulse output forced cutoff operation Note
The pulse output is forcibly cutoff by event input from the ELC. To use this function, select pulse output mode
(PWM function, reset synchronous PWM mode, complementary PWM mode, or PWM3 mode) and set the
ELCOBE0 or ELCOBE1 bit to 1. This function is disabled for the input capture function in timer mode.
Note The pulse output is cutoff during the low input period for forced cutoff from the INTP0 pin, but the pulse output is
cutoff once by a single event input from the ELC for forced cutoff by the ELC event.
[Setting Procedure]
(1) Set timer RD as the ELC event link destination.
(2) Set bits ELCICEi (i = 0 or 1) and ELCOBEi (i = 0 or 1) to 1 in the TRDELC register.
(6) Event Output to Event Link Controller (ELC)/DTC
Table 8-11 lists the Timer RD Modes and Event Output to ELC/DTC.
Table 8-11. Timer RD Modes and Event Output to ELC/DTC
Used Mode
Input capture function
Output Source
TRDIOA0 edge detection set by bits IOA1 and IOA0 in the
ELC
DTC
Available
Available
Available
Available
Available
Available
Available
Available
Available
Available
Available
Available
Available
Available
Available
Available
TRDIORA0 register
TRDIOB0 edge detection set by bits IOB1 and IOB0 in the
TRDIORA0 register
TRDIOC0 edge detection set by bits IOC1 and IOC0 in the
TRDIORC0 register
TRDIOD0 edge detection set by bits IOD1 and IOD0 in the
TRDIORD0 register
TRDIOA1 edge detection set by bits IOA1 and IOA0 in the
TRDIORA1 register
TRDIOB1 edge detection set by bits IOB1 and IOB0 in the
TRDIORA1 register
TRDIOC1 edge detection set by bits IOC1 and IOC0 in the
TRDIORC1 register
TRDIOD1 edge detection set by bits IOD1 and IOD0 in the
TRDIORD1 register
Output compare function,
Compare match between registers TRD0 and TRDGRA0
Available
Available
PWM function, reset
Compare match between registers TRD0 and TRDGRB0
Available
Available
synchronous PWM mode,
Compare match between registers TRD0 and TRDGRC0
Available
Available
complementary PWM mode,
Compare match between registers TRD0 and TRDGRD0
Available
Available
Compare match between registers TRD1 and TRDGRA1
Available
Available
Compare match between registers TRD1 and TRDGRB1
Available
Available
Compare match between registers TRD1 and TRDGRC1
Available
Available
Compare match between registers TRD1 and TRDGRD1
Available
Available
TRD1 register underflow
Available
-
and PWM3 mode
Complementary PWM mode
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8.3.2 Input Capture Function
The input capture function measures the external signal width and period. The content of the TRDi register (counter) is
transferred to the TRDGRji register as a trigger of the TRDIOji pin (i = 0 or 1, j = A, B, C, or D) external signal (input
capture). Since this function is enabled with a combination of the TRDIOji pin and TRDGRji register, the input capture
function, or any other mode or function, can be selected for each individual pin.
Figure 8-44 shows the Block Diagram of Input Capture Function, Table 8-12 lists the Input Capture Function
Specifications, and Figure 8-45 shows an Operation Example of Input Capture Function.
Figure 8-44. Block Diagram of Input Capture Function
TRDIOAi
Input capture signal
Edge
selection
(Note 1)
TRDGRAi
register
TRDi register
TRDGRCi
register
TRDIOCi
Edge
selection
TRDIOBi
Edge
selection
Input capture signal
Input capture signal
(Note 2)
TRDGRBi
register
TRDGRDi
register
TRDIODi
Edge
selection
Input capture signal
Remark
i = 0 or 1
Notes:
1. When the BFCi bit in the TRDMR register is set to 1 (TRDGRCi register is buffer register for TRDGRAi register).
2. When the BFDi bit in the TRDMR register is set to 1 (TRDGRDi register is buffer register for TRDGRBi register).
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Table 8-12. Input Capture Function Specifications
Item
Count sources
Specification
fHOCO
Note
, fCLK, fCLK/2, fCLK/4, fCLK/8, fCLK/32
External signal input to the TRDCLK pin (active edge selected by a program)
Count operations
Increment
Count period
When bits CCLR2 to CCLR0 in the TRDCRi register are set to 000B (freerunning operation).
1/fk × 65536 fk: Frequency of count source
Count start condition
1 (count starts) is written to the TSTARTi bit in the TRDSTR register.
Count stop condition
0 (count stops) is written to the TSTARTi bit in the TRDSTR register when the CSELi
bit in the TRDSTR register is set to 1.
Interrupt request generation timing
• Input capture (active edge of TRDIOji input)
• TRDi register overflow
TRDIOA0 pin function
I/O port, input-capture input, or TRDCLK (external clock) input
TRDIOB0, TRDIOC0, TRDIOD0,
I/O port or input-capture input (selectable for each pin)
TRDIOA1 to TRDIOD1 pin function
INTP0 pin function
Not used (I/O port or INTP0 interrupt input)
Read from timer
The count value can be read by reading the TRDi register.
Write to timer
• When the TRDSYNC bit in the TRDMR register is 0 (timer RD0 and timer RD1
operate independently).
Data can be written to the TRDi register.
• When the TRDSYNC bit in the TRDMR register is 1 (timer RD0 and timer RD1
operate synchronously).
Data can be written to both the TRD0 and TRD1 registers by writing to the TRDi
register.
Selectable functions
• Input-capture input pin selection
Either one pin or multiple pins of TRDIOAi, TRDIOBi, TRDIOCi, and TRDIODi.
• Input-capture input active edge selection
Rising edge, falling edge, or both rising and falling edges
• Timing for setting the TRDi register to 0000H.
At overflow or input capture
• Buffer operation (see 8. 3. 1 (2) Buffer Operation)
• Synchronous operation (see 8. 3. 1 (3) Synchronous Operation)
• Digital filter.
The TRDIOji input is sampled, and when the sampled input level match three
times, that level is determined.
• Input capture operation by event input from event link controller (ELC).
<R>
Note
fHOCO is selected only when FRQSEL4 = 1 in the user option byte (000C2H/010C2H). When selecting fHOCO as
the count source for timer RD, set fCLK to fIH before setting bit 4 (TRD0EN) in peripheral enable register 1
(PER1). When changing fCLK to a clock other than fIH, clear bit 4 (TRD0EN) in peripheral enable register 1
(PER1) before changing.
Remark i = 0 or 1, j = A, B, C, or D
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(1) Operation Example
By setting bits CCLR0 to CCLR2 in the TRDCRi register (i = 0 or 1), the timer RDi counter value is reset by an input
capture/compare match. Figure 8-45 shows an operation example with bits CCLR2 to CCLR0 set to 001B.
If the input capture operation has been set to clear the count during operation and is performed when the timer
count value is FFFFH, depending on the timing between the count source and input capture operation interrupt
flags bits IMFA to IMFD and OVF in the TRDSRi register may be set to 1 simultaneously.
Figure 8-45. Operation Example of Input Capture Function
TRDCLK input
count source
Count value
in TRDi register
FFFFH
0009H
0006H
0000H
Time
TSTARTi bit in
TRDSTR register
65536
TRDIOAi input
0006H
TRDGRAi register
Transfer
TRDGRCi register
0009H
Transfer
0006H
IMFA bit in
TRDSRi register
OVF bit in
TRDSRi register
Set to 0 by a program
Remark
i = 0 or 1
The above diagram applies under the following conditions:
Bits CCLR2 to CCLR0 in the TRDCRi register are set to 001B (TRDi register is set to 0000H by TRDGRAi register input capture).
Bits TCK2 to TCK0 in the TRDCRi register are set to 101B (TRDCLK input for the count source).
Bits CKEG1 and CKEG0 in the TRDCRi register are set to 01B (count at the falling edge for the count source).
Bits IOA2 to IOA0 in the TRDIORAi register are set to 101B (input capture at the falling edge of TRDIOAi input).
The BFCi bit in the TRDMR register is set to 1 (TRDGRCi register is buffer register for TRDGRAi register).
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(2) Digital Filter
The TRDIOji input (i = 0 or 1, j = A, B, C, or D) is sampled, and when the sampled input level matches three times,
its level is determined. Select the digital filter function and sampling clock using the TRDDFi register.
Figure 8-46 shows the Block Diagram of Digital Filter.
Figure 8-46. Block Diagram of Digital Filter
TCK2 to TCK
DFCK1 and DFCK0
= 101B
TRDCLK
= 100B
fCLK/32
fCLK/8
= 10B
= 11B
= 010B
fCLK/4
= 01B
Note2
fCLKNote2
= 011B
fCLK/8
= 00B
fCLK/32Note2
Count source
= 001B
fCLK/2
Synchronized by two
flip-flops
= 000B
Note1
fCLK, fHOCO
Sampling clock
Timer RD operating clock
fCLK
C
TRDIOji input signal
D
C
Q
Latch
D
Q
Latch
D
DFj
C
C
Q
Latch
D
Q
Latch
Match detection
circuit
(flip-flop output)
Edge detection
circuit
IOA2 to IOA0
IOB2 to IOB0
IOC3 to IOC0
IOD3 to IOD0
1
0
Edge detection
circuit
Clock period selected by
bits TCK2 to TCK0 or bits
DFCK1 and DFCK0
Sampling clock
TRDIOji input signal
Matched three times,
so recognized as
a signal change
Input signal through
digital filtering
Signal transmission delayed
up to five sampling clocks
If fails to match three times, is assumed
to be noise and not transmitted
Remark
i = 0 or 1, j = A, B, C, or D
TCK0 to TCK2: Bits in TRDCRi register
DFCK0, DFCK1, DFj: Bits in TRDDF register
IOA0 to IOA2, IOB0 to IOB2: Bits in TRDIORAi register
IOC0 to IOC3, IOD0 to IOD3: Bits in TRDIORCi register
Notes 1. fCLK is selected when FRQSEL4 = 0 and fHOCO is selected when FRQSEL4 = 1 in the user option byte
(000C2H/010C2H).
2. When FRQSEL4 = 1 in the user option byte (000C2H/010C2H), fCLK/32, fCLK/8, and fCLK are set to
fHOCO/32, fHOCO/8, and fHOCO, respectively.
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8.3.3 Output Compare Function
This function detects matches (compare match) between the content of the TRDGRji register (j = A, B, C, or D) and the
content of the TRDi register (counter) (i = 0 or 1). When the contents match, an arbitrary level is output from the TRDIOji
pin. Since this function is enabled with a combination of the TRDIOji pin and TRDGRji register, the output compare function,
or any other mode or function, can be selected for each individual pin.
Figure 8-47 shows the Block Diagram of Output Compare Function, Table 8-13 lists the Output Compare Function
Specifications, and Figure 8-48 shows an Operation Example of Output Compare Function.
Figure 8-47. Block Diagram of Output Compare Function
Timer RD0
TRD0
Compare match signal
TRDIOA0
Output
control
IOC3 = 0 in
TRDIORC0 register
Comparator
TRDGRA0
Comparator
TRDGRC0
Comparator
TRDGRB0
Comparator
TRDGRD0
Compare match signal
TRDIOC0
Output
control
IOC3 = 1
Compare match signal
TRDIOB0
Output
control
IOD3 = 0 in
TRDIORC0 register
Compare match signal
TRDIOD0
Output
control
IOD3 = 1
Timer RD1
TRD1
Compare match signal
TRDIOA1
Output
control
IOC3 = 0 in
TRDIORC1 register
Comparator
TRDGRA1
Comparator
TRDGRC1
Comparator
TRDGRB1
Comparator
TRDGRD1
Compare match signal
TRDIOC1
Output
control
IOC3 = 1
Compare match signal
TRDIOB1
Output
control
IOD3 = 0 in
TRDIORC1 register
Compare match signal
TRDIOD1
Output
control
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Table 8-13. Output Compare Function Specifications
Item
Count sources
Specification
fHOCO
Note
, fCLK, fCLK/2, fCLK/4, fCLK/8, fCLK/32
External signal input to the TRDCLK pin (active edge selected by a program)
Count operations
Increment
Count period
• When bits CCLR2 to CCLR0 in the TRDCRi register are set to 000B (free-running
operation).
1/fk × 65536 fk: Frequency of count source
• When bits CCLR1 and CCLR0 in the TRDCRi register are set to 01B or 10B
(TRDi register is set to 0000H at compare match with TRDGRji register).
1/fk × (n + 1)
n: Value set in the TRDGRji register
Waveform output timing
Compare match (contents of registers TRDi and TRDGRji match)
Count start condition
1 (count starts) is written to the TSTARTi bit in the TRDSTR register.
Count stop conditions
• 0 (count stops) is written to the TSTARTi bit in the TRDSTR register when the CSELi
bit in the TRDSTR register is set to 1.
The output compare output pin holds the output level before the count stops.
• When the CSELi bit in the TRDSTR register is set to 0, the count stops at the
compare match with the TRDGRAi register.
The output compare output pin holds the level after output change by compare match.
Interrupt request generation timing
• Compare match (contents of registers TRDi and TRDGRji match)
TRDIOA0 pin function
I/O port, output-compare output, or TRDCLK (external clock) input
TRDIOB0, TRDIOC0, TRDIOD0,
I/O port or output-compare output (selectable for each pin)
• TRDi register overflow
TRDIOA1 to TRDIOD1 pin function
INTP0 pin function
I/O port or INTP0 interrupt input
Read from timer
The count value can be read by reading the TRDi register.
Write to timer
• When the TRDSYNC bit in the TRDMR register is set to 0 (timer RD0 and timer RD1
operate independently). Data can be written to the TRDi register.
• When the TRDSYNC bit in the TRDMR register is set to 1 (timer RD0 and timer RD1
operate synchronously). Data can be written to both the TRD0 and TRD1 registers by
writing to the TRDi register.
Selectable functions
• Output-compare output pin selection
Either one pin or multiple pins of TRDIOAi, TRDIOBi, TRDIOCi, and TRDIODi.
• Output level selection at compare match
Low output, high output, or inverted output level
• Initial output level selection
The level can be set for the period from the count start to the compare match.
• Timing for setting the TRDi register to 0000H
Overflow or compare match in the TRDGRAi register
• Buffer operation (see 8. 3. 1 (2) Buffer Operation)
• Synchronous operation (see 8. 3. 1 (3) Synchronous Operation)
• Changing output pins for registers TRDGRCi and TRDGRDi
The TRDGRCi register can be used as output control of the TRDIOAi pin and the
TRDGRDi register can be used as output control of the TRDIOBi pin.
• Pulse output forced cutoff signal input (see 8. 3. 1 (4) Pulse Output Forced Cutoff)
• Timer RD can be used as the internal timer without output.
<R>
Note
fHOCO is selected only when FRQSEL4 = 1 in the user option byte (000C2H/010C2H). When selecting fHOCO as
the count source for timer RD, set fCLK to fIH before setting bit 4 (TRD0EN) in peripheral enable register 1
(PER1). When changing fCLK to a clock other than fIH, clear bit 4 (TRD0EN) in peripheral enable register 1
(PER1) before changing.
Remark i = 0 or 1, j = A, B, C, or D
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(1) Operation Example
By setting bits CCLR0 to CCLR2 in the TRDCRi register (i = 0 or 1), the timer RDi counter value is reset by an input
capture/compare match. If the expected compare value is FFFFH at this time, FFFFH changes to 0000H, same as
the overflow operation, and the overflow flag is set to 1.
Figure 8-48. Operation Example of Output Compare Function
Count source
Value in TRDi register
m
n
p
Count
restarts
Time
Count
stops
TSTARTi bit in
TRDSTR register
m+1
m+1
Output level
held
TRDIOAi output
Output inverted by compare match
Initial output is low
IMFA bit in
TRDSRi register
Set to 0 by a program
n+1
TRDIOBi output
High output by compare match
Initial output is low
Output level
held
IMFB bit in
TRDSRi register
Set to 0 by a program
p+1
Low output by compare match
Output level
held
TRDIOCi output
Initial output is high
IMFC bit in
TRDSRi register
Remark
i = 0 or 1
M: Value set in TRDGRAi register
n: Value set in TRDGRBi register
p: Value set in TRDGRCi register
Set to 0 by a program
The above diagram applies under the following conditions :
The CSELi bit in the TRDSTR register is set to 1 (TRDi is not stopped by compare match).
Bits BFCi and BFDi in the TRDMR register are set to 0 (TRDGRCi and TRDGRDi do not operate as buffers).
Bits EAi, EBi, and ECi in the TRDOER1 register are set to 0 (TRDIOAi, TRDIOBi and TRDIOCi output enabled).
Bits CCLR2 to CCLR0 in the TRDCRi register are set to 001B (TRDi is set to 0000H by compare match with TRDGRAi).
Bits TOAi and TOBi in the TRDOCR register is set to 0 (initial output is low until compare match), the TOCi bit is set to 1 (initial output is high until
compare match).
Bits IOA2 to IOA0 in the TRDIORAi register are set to 011B (TRDIOAi output inverted at TRDGRAi compare match).
Bits IOB2 to IOB0 in the TRDIORAi register are set to 010B (TRDIOBi high output at TRDGRBi compare match).
Bits IOC3 to IOC0 in the TRDIORCi register are set to 1001B (TRDIOCi low output at TRDGRCi register compare match).
Bits IOD3 to IOD0 in the TRDIORCi register are set to 1000B (TRDGRDi register does not control TRDIOBi pin output. Pin output by compare
match is disabled).
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(2) Changing Output Pins in Registers TRDGRCi (i = 0 or 1) and TRDGRDi
The TRDGRCi register can be used for output control of the TRDIOAi pin, and the TRDGRDi register can be used
for output control of the TRDIOBi pin. Therefore, each pin output can be controlled as follows:
• TRDIOAi output is controlled by the values in registers TRDGRAi and TRDGRCi.
• TRDIOBi output is controlled by the values in registers TRDGRBi and TRDGRDi.
Figure 8-49. Changing Output Pins in Registers TRDGRCi and TRDGRDi
Timer RD0
TRD0
Compare match signal
TRDIOA0
Output
control
IOC3 = 0 in
TRDIORC0 register
Comparator
TRDGRA0
Comparator
TRDGRC0
Comparator
TRDGRB0
Comparator
TRDGRD0
Compare match signal
TRDIOC0
Output
control
IOC3 = 1
Compare match signal
TRDIOB0
Output
control
IOD3 = 0 in
TRDIORC0 register
Compare match signal
TRDIOD0
Output
control
IOD3 = 1
Timer RD1
TRD1
Compare match signal
TRDIOA1
Output
control
IOC3 = 0 in
TRDIORC1 register
Comparator
TRDGRA1
Comparator
TRDGRC1
Comparator
TRDGRB1
Comparator
TRDGRD1
Compare match signal
TRDIOC1
Output
control
IOC3 = 1
Compare match signal
TRDIOB1
Output
control
IOD3 = 0 in
TRDIORC1 register
Compare match signal
TRDIOD1
Output
control
IOD3 = 1
Change output pins in registers TRDGRCi and TRDGRDi as follows:
• Select 0 (TRDGRji register output pin is changed) using the IOj3 (j = C or D) bit in the TRDIORCi register.
• Set the BFji bit in the TRDMR register to 0 (general register).
•
Set different values in registers TRDGRCi and TRDGRAi. Also, set different values in registers TRDGRDi and
TRDGRBi.
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Figure 8-50 shows an Operation Example When TRDGRCi Register is Used for Output Control of TRDIOAi Pin and
TRDGRDi Register is Used for Output Control of TRDIOBi Pin.
Figure 8-50. Operation Example When TRDGRCi Register is Used for Output Control of TRDIOAi Pin
and TRDGRDi Register is Used for Output Control of TRDIOBi Pin
Count source
Value in TRDi register
FFFFH
m
n
p
q
0000H
Time
m+1
n+1
m-n
p+1
q+1
p-q
Initial output is low
TRDIOAi output
Output inverted by compare match
IMFA bit in
TRDSRi register
Set to 0 by a program
Set to 0 by a program
IMFC bit in
TRDSRi register
Initial output is low
TRDIOBi output
Output inverted by compare match
IMFB bit in
TRDSRi register
Set to 0 by a program
Set to 0 by a program
IMFD bit in
TRDSRi register
Remark
i = 0 or 1
m: Value set in TRDGRAi register
n: Value set in TRDGRCi register
p: Value set in TRDGRBi register
q: Value set in TRDGRDi register
The above diagram applies under the following conditions :
The CSELi bit in the TRDSTR register is set to 1 (TRDi register is not stopped by compare match).
Bits BFCi and BFDi in the TRDMR register are set to 0 (TRDGRCi and TRDGRDi do not operate as buffers).
Bits EAi and EBi in the TRDOER1 register are set to 0 (TRDIOAi and TRDIOBi output enabled).
Bits CCLR2 to CCLR0 in the TRDCRi register are set to 001B (TRDi is set to 0000H by compare match with TRDGRAi).
Bits TOAi and TOBi in the TRDOCR register are set to 0 (initial output is low until compare match).
Bits IOA2 to IOA0 in the TRDIORAi register are set to 011B (TRDIOAi output inverted at TRDGRAi compare match).
Bits IOB2 to IOB0 in the TRDIORAi register are set to 011B (TRDIOBi output inverted at TRDGRBi compare match).
Bits IOC3 to IOC0 in the TRDIORCi register are set to 0011B (TRDIOAi output inverted at TRDGRCi compare match).
Bits IOD3 to IOD0 in the TRDIORCi register are set to 0011B (TRDIOBi output inverted at TRDGRDi compare match).
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8.3.4 PWM Function
In PWM function, a PWM waveform is output. Up to three PWM waveforms with the same period can be output by timer
RDi (i = 0 or 1). Also, up to six PWM waveforms with the same period can be output by synchronizing timer RD0 and timer
RD1.
Since this mode functions by a combination of the TRDIOji pin (i = 0 or 1, j = B, C, or D) and TRDGRji register, PWM
function, or any other mode or function, can be selected for each individual pin. (However, since the TRDGRAi register is
used when using any pin for PWM function, the TRDGRAi register cannot be used for other modes.)
Figure 8-51 shows the Block Diagram of PWM function, Table 8-14 lists the PWM Function Specifications, and Figure
8-52 and Figure 8-53 show Operation Examples in PWM Function.
Figure 8-51. Block Diagram of PWM Function
TRDi
Compare match signal
Comparator
TRDIOBi
TRDIOCi
TRDGRAi
Compare match signal
Output
control
TRDIODi
(Note 1)
Comparator
TRDGRBi
Comparator
TRDGRCi
Compare match signal
Compare match signal
(Note 2)
Comparator
TRDGRDi
Remark
i = 0 or 1
Notes:
1. When the BFCi bit in the TRDMR register is set to 1 (TRDGRCi register is buffer register for TRDGRAi register).
2. When the BFDi bit in the TRDMR register is set to 1 (TRDGRDi register is buffer register for TRDGRBi register).
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Table 8-14. PWM Mode Specifications
Item
Count sources
Specification
fHOCO
Note
, fCLK, fCLK/2, fCLK/4, fCLK/8, fCLK/32
External signal input to the TRDCLK pin (active edge selected by a program)
Count operations
Increment
PWM waveform
PWM period: 1/fk x (m + 1)
Active level width: 1/fk x (m - n)
Inactive level width: 1/fk x (n + 1)
fk: Frequency of count source
m: Value set in the TRDGRAi register
n: Value set in the TRDGRji register
m+1
n+1
m-n
(When low is selected as the active level)
Count start condition
1 (count starts) is written to the TSTARTi bit in the TRDSTR register.
Count stop conditions
• 0 (count stops) is written to the TSTARTi bit in the TRDSTR register when the CSELi
bit in the TRDSTR register is set to 1.
The PWM output pin holds the output level before the count stops.
• When the CSELi bit in the TRDSTR register is set to 0, the count stops at the
compare match with the TRDGRAi register.
The PWM output pin holds the level after output change by compare match.
Interrupt request generation timing
• Compare match (content of the TRDi register matches content of the TRDGRhi
register)
• TRDi register overflow
TRDIOA0 pin function
I/O port or TRDCLK (external clock) input
TRDIOA1 pin function
I/O port
TRDIOB0, TRDIOC0, TRDIOD0,
I/O port or pulse output (selectable for each pin)
TRDIOB1, TRDIOC1, TRDIOD1
pin function
INTP0 pin function
Pulse output forced cutoff signal input (I/O port or INTP0 interrupt input)
Read from timer
The count value can be read by reading the TRDi register.
Write to timer
The value can be written to the TRDi register.
Selectable functions
• One to three PWM output pins selectable with timer RDi
Either one pin or multiple pins of TRDIOBi, TRDIOCi, and TRDIODi.
• Active level selectable for each pin.
• Initial output level selectable for each pin.
• Synchronous operation (see 8. 3. 1 (3) Synchronous Operation)
• Buffer operation (see 8. 3. 1 (2) Buffer Operation)
• Pulse output forced cutoff signal input (see 8. 3. 1 (4) Pulse Output Forced Cutoff)
<R>
Note
fHOCO is selected only when FRQSEL4 = 1 in the user option byte (000C2H/010C2H). When selecting fHOCO as
the count source for timer RD, set fCLK to fIH before setting bit 4 (TRD0EN) in peripheral enable register 1
(PER1). When changing fCLK to a clock other than fIH, clear bit 4 (TRD0EN) in peripheral enable register 1
(PER1) before changing.
Remark i = 0 or 1, j = B, C, or D, h = A, B, C, or D
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(1) Operation Example
Figure 8-52. Operation Example in PWM Function
Count source
Value in TRDi register
m
n
p
q
0000H
Time
m+1
n+1
TRDIOBi output
Active level is high
Inactive level is low
p+1
Initial output is low
until compare match
TRDIOCi output
m-n
m-p
Inactive level is high
Initial output is high
until compare match
q+1
m-q
Active level is low
TRDIODi output
Inactive level is high
IMFA bit in
TRDSRi register
Initial output is low
until compare match
Set to 0 by a program
IMFB bit in
TRDSRi register
Set to 0 by a program
IMFC bit in
TRDSRi register
IMFD bit in
TRDSRi register
Set to 0 by a program
Set to 0 by a program
Remark
i = 0 or 1
m: Value set in TRDGRAi register
n: Value set in TRDGRBi register
p: Value set in TRDGRCi register
q: Value set in TRDGRDi register
The above diagram applies under the following conditions :
Bits BFCi and BFDi in the TRDMR register are set to 0 (TRDGRCi and TRDGRDi do not operate as buffers).
Bits EBi, ECi, and EDi in the TRDOER1 register are set to 0 (TRDIOBi, TRDIOCi and TRDIODi output enabled).
Bits TOBi and TOCi in the TRDOCR register are set to 0 (inactive level), the TODi bit is set to 1 (active level).
The POLB bit in the TRDPOCRi register is set to 1 (active level is high), bits POLC and POLD are set to 0 (active level is low).
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Figure 8-53. Operation Example in PWM Function (Duty Cycle 0%, Duty Cycle 100%)
Value in TRDi register
p
m
q
n
Time
0000H
TSTARTi bit in
TRDSTR register
1
Since no compare match in the TRDGRBi register is
generated, a low level is not applied to the TRDIOBi
output.
TRDIOBi output
Duty cycle 0%
n
TRDGRBi register
p (p > m)
q
Rewrite by a program
IMFA bit in
TRDSRi register
Set to 0 by a program
Set to 0 by a program
IMFB bit in
TRDSRi register
Value in TRDi register
m
p
n
Time
0000H
TSTARTi bit in
TRDSTR register
1
When compare matches with registers TRDGRAi and TRDGRBi are generated
simultaneously, the compare match with the TRDGRBi register has priority.
A low level is applied to the TRDIOBi output without any change .
Duty cycle 100%
TRDIOBi output
A low level is applied to TRDIOBi output by compare
match with the TRDGRBi register with no change.
TRDGRBi register
n
m
p
Rewrite by a program
IMFA bit in
TRDSRi register
Set to 0 by a program
Set to 0 by a program
IMFB bit in
TRDSRi register
Remark
i = 0 or 1
m: Value set in TRDGRAi register
The above diagram applies under the following conditions :
The EBi bit in the TRDOER1 register is set to 0 (TRDIOBi output enabled).
The POLB bit in the TRDPOCRi register is set to 0 (active level is low).
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8.3.5 Reset Synchronous PWM Mode
In this mode, three normal-phases and three counter-phases of the PWM waveform are output with the same period
(three-phase, sawtooth wave modulation, and no dead time).
Figure 8-54 shows the Block Diagram of Reset Synchronous PWM Mode, Table 8-15 lists the Reset Synchronous PWM
Mode Specifications, Figure 8-55 shows an Operation Example in Reset Synchronous PWM Mode.
See Figure 8-53 Operation Example in PWM Function (Duty Cycle 0%, Duty Cycle 100%) for an operation example
in PWM Mode with duty cycle 0% and duty cycle 100%.
Figure 8-54. Block Diagram of Reset Synchronous PWM Mode
Buffer (1)
TRDGRC0
register
Waveform control
TRDGRA0
register
Period
TRDIOC0
Normal-phase
TRDGRD0
register
TRDGRB0
register
PWM1
TRDIOB0
Counter-phase
Normal-phase
TRDGRC1
register
TRDGRA1
register
PWM2
Counter-phase
Normal-phase
TRDGRD1
register
TRDGRB1
register
PWM3
Counter-phase
TRDIOD0
TRDIOA1
TRDIOC1
TRDIOB1
TRDIOD1
Note:
1. When bits TRDBFC0, TRDBFD0, TRDBFC1, and TRDBFD1 in the TRDMR register are set to 1 (buffer register).
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Table 8-15. Reset Synchronous PWM Mode Specifications
Item
Count sources
Specification
fHOCO
Note
, fCLK, fCLK/2, fCLK/4, fCLK/8, fCLK/32
External signal input to the TRDCLK pin (active edge selected by a program)
Count operations
The TRD0 register is incremented (the TRD1 register is not used).
PWM waveform
PWM period: 1/fk x (m + 1)
Active level of normal-phase: 1/fk x (m - n)
Inactive level of counter-phase: 1/fk x (n + 1)
fk: Frequency of count source
m: Value set in the TRDGRA0 register
n: Value set in the TRDGRB0 register (PWM1 output)
Value set in the TRDGRA1 register (PWM2 output)
Value set in the TRDGRB1 register (PWM3 output)
m+1
Normal-phase
m-n
Counter-phase
n+1
(When low is selected as the active level)
Count start condition
1 (count starts) is written to the TSTART0 bit in the TRDSTR register.
Count stop conditions
• 0 (count stops) is written to the TSTART0 bit when the CSEL0 bit in the TRDSTR
register is set to 1.
The PWM output pin outputs the initial output level selected by bits OLS0 and OLS1
in the TRDFCR register.
• When the CSEL0 bit in the TRDSTR register is set to 0, the count stops at the
compare match with the TRDGRA0 register.
The PWM output pin outputs the initial output level selected by bits OLS0 and OLS1
in the TRDFCR register.
Interrupt request generation timing
• Compare match (content of the TRD0 register matches content of registers
TRDGRj0, TRDGRA1, and TRDGRB1)
• TRD0 register overflow
TRDIOA0 pin function
I/O port or TRDCLK (external clock) input
TRDIOB0 pin function
PWM1 output normal-phase output
TRDIOD0 pin function
PWM1 output counter-phase output
TRDIOA1 pin function
PWM2 output normal-phase output
TRDIOC1 pin function
PWM2 output counter-phase output
TRDIOB1 pin function
PWM3 output normal-phase output
TRDIOD1 pin function
PWM3 output counter-phase output
TRDIOC0 pin function
Output inverted every PWM period
INTP0 pin function
Pulse output forced cutoff signal input (I/O port or INTP0 interrupt input)
Read from timer
The count value can be read by reading the TRD0 register.
Write to timer
The value can be written to the TRD0 register.
Selectable functions
•The normal-phase and counter-phase active level and initial output level are selected
individually.
• Buffer operation (see 8. 3. 1 (2) Buffer Operation)
• Pulse output forced cutoff signal input (see 8. 3. 1 (4) Pulse Output Forced Cutoff)
Note
<R>
fHOCO is selected only when FRQSEL4 = 1 in the user option byte (000C2H/010C2H). When selecting fHOCO as
the count source for timer RD, set fCLK to fIH before setting bit 4 (TRD0EN) in peripheral enable register 1
(PER1). When changing fCLK to a clock other than fIH, clear bit 4 (TRD0EN) in peripheral enable register 1
(PER1) before changing.
Remark j = A, B, C, or D
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(1) Operation Example
Figure 8-55. Operation Example in Reset Synchronous PWM Mode
Count source
Value in TRD0 register
m
n
p
q
0000H
Time
TSTART0 bit in
TRDSTR register
m+1
m-n
TRDIOB0 output
n+1
TRDIOD0 output
m-p
TRDIOA1 output
p+1
TRDIOC1 output
m-q
TRDIOB1 output
Initial output is high
q +1
Active level is low
TRDIOD1 output
Initial output is high
Active level is low
TRDIOC0 output
IMFA bit in
TRDSR0 register
Set to 0 by a program
IMFB bit in
TRDSR0 register
Set to 0 by a program
IMFA bit in
TRDSR1 register
IMFB bit in
TRDSR1 register
Remark
i = 0 or 1
m: Value set in TRDGRA0 register
n: Value set in TRDGRB0 register
p: Value set in TRDGRA1 register
q: Value set in TRDGRB1 register
Set to 0 by a program
Transfer from the buffer register to the
general register during buffer operation
Set to 0 by a program
Transfer from the buffer register to the
general register during buffer operation
The above diagram applies under the following condition :
Bits OLS1 and OLS0 in the TRDFCR register are set to 0 (initial output level is high, active level is low).
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8.3.6 Complementary PWM Mode
In this mode, three normal-phases and three counter-phases of the PWM waveform are output with the same period
(three-phase, triangular wave modulation, and with dead time).
Figure 8-56 shows the Block Diagram of Complementary PWM Mode, Table 8-16 lists the Complementary PWM Mode
Specifications, and Figure 8-57 shows the Output Model of Complementary PWM Mode, and Figure 8-58 shows an
Operation Example in Complementary PWM Mode.
Figure 8-56. Block Diagram of Complementary PWM Mode
Buffer
Waveform control
TRDGRA0
register
Period
TRDIOC0
Normal-phase
TRDGRD0
register
TRDGRB0
register
PWM1
Counter-phase
Normal-phase
TRDGRC1
register
TRDGRA1
register
PWM2
Counter-phase
Normal-phase
TRDGRD1
register
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register
PWM3
Counter-phase
TRDIOB0
TRDIOD0
TRDIOA1
TRDIOC1
TRDIOB1
TRDIOD1
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Table 8-16. Complementary PWM Mode Specifications
Item
Count sources
Specification
fHOCO
Note 1
, fCLK, fCLK/2, fCLK/4, fCLK/8, fCLK/32
External signal input to the TRDCLK pin (active edge selected by a program)
Set bits TCK2 to TCK0 in the TRDCR1 register to the same value (same count
source) as bits TCK2 to TCK0 in the TRDCR0 register.
Count operations
Increment or decrement.
Registers TRD0 and TRD1 are decremented with the compare match with registers
TRD0 and TRDGRA0 during increment operation. When the TRD1 register changes
from 0000H to FFFFH during decrement operation, and registers TRD0 and TRD1 are
incremented.
PWM operations
PWM period: 1/fk × (m + 2 - p) × 2
Note 2
Dead time: p
Active level width of normal-phase: 1/fk × (m - n - p + 1) × 2
Active level width of counter-phase: 1/fk × (n + 1 - p) × 2
fk: Frequency of count source
m: Value set in the TRDGRA0 register
n: Value set in the TRDGRB0 register (PWM1 output)
Value set in the TRDGRA1 register (PWM2 output)
Value set in the TRDGRB1 register (PWM3 output)
p: Value set in the TRD0 register
m+2-p
n+1
Normal-phase
Counter-phase
n+1-p
p
m-p-n+1
(When low is selected as the active level)
Count start condition
1 (count starts) is written to bits TSTART0 and TSTART1 in the TRDSTR register.
Count stop condition
0 (count stops) is written to bits TSTART0 and TSTART1 in the TRDSTR register when
the CSEL0 bit in the TRDSTR register is set to 1. (The PWM output pin outputs the
initial output level selected by bits OLS0 and OLS1 in the TRDFCR register.)
Interrupt request generation timing
• Compare match (content of the TRDi register matches content of the TRDGRji
register)
• TRD1 register underflow
TRDIOA0 pin function
I/O port or TRDCLK (external clock) input
TRDIOB0 pin function
PWM1 output normal-phase output
TRDIOD0 pin function
PWM1 output counter-phase output
TRDIOA1 pin function
PWM2 output normal-phase output
TRDIOC1 pin function
PWM2 output counter-phase output
TRDIOB1 pin function
PWM3 output normal-phase output
TRDIOD1 pin function
PWM3 output counter-phase output
TRDIOC0 pin function
Output inverted every 1/2 period of PWM
INTP0 pin function
Pulse output forced cutoff signal input (I/O port or INTP0 interrupt input)
Read from timer
The count value can be read by reading the TRDi register.
Write to timer
The value can be written to the TRDi register.
Selectable functions
• Pulse output forced cutoff signal input (see 8. 3. 1 (4) Pulse Output Forced Cutoff)
• The normal-phase and counter-phase active level and initial output level are selected
individually.
• Transfer timing from the buffer register selection
<R>
Notes 1.
2.
fHOCO is selected only when FRQSEL4 = 1 in the user option byte (000C2H/010C2H). When selecting
fHOCO as the count source for timer RD, set fCLK to fIH before setting bit 4 (TRD0EN) in peripheral enable
register 1 (PER1). When changing fCLK to a clock other than fIH, clear bit 4 (TRD0EN) in peripheral enable
register 1 (PER1) before changing.
After a count starts, the PWM period is fixed.
Remark i = 0 or 1, j = A, B, C, or D
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(1) Operation Example
Figure 8-57. Output Model of Complementary PWM Mode
Value in TRDi register
Value in TRD0 register
Value in TRDGRA0
register
Value in TRD1 register
Value in TRDGRB0
register
Value in TRDGRA1
register
Value in TRDGRB1
register
Time
0000H
TRDIOB0 output
TRDIOD0 output
TRDIOA1 output
TRDIOC1 output
TRDIOB1 output
TRDIOD1 output
TRDIOC0 output
Remark i = 0 or 1
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Figure 8-58. Operation Example in Complementary PWM Mode
Count source
Value in TRDi register
m+1
m
Value in TRD0 register
n
Value in TRD1 register
p
Time
0000H
Set to
FFFFH
Bits TSTART0 and TSTART1
in TRDSTR register
TRDIOB0 output
Initial output is high
Active level is low
TRDIOD0 output
TRDIOC0 output
Initial output is high
m+2-p
m-p-n+1
n+1
n+1-p
p
p
(m-p-n+1) × 2
Width of normalphase active level
Dead
time
n+1-p
(n + 1 - p) × 2
Width of counter-phase active level
UDF bit in
TRDSR1 register
IMFA bit in
TRDSR0 register
TRDGRB0 register
Set to 0 by a program
n
n
Transfer (when bits CMD1 and CMD0 are set to 11B)
TRDGRD0 register
n
Transfer (when bits CMD1 and CMD0
are set to 10B)
Following data
Modify with a program
IMFB bit in
TRDSR0 register
Set to 0 by a program
Set to 0 by a program
Remark
CMD0, CMD1: Bits in TRDFCR register
i = 0 or 1
m: Value set in TRDGRA0 register
n: Value set in TRDGRB0 register
p: Value set in TRD0 register
The above diagram applies under the following condition :
Bits OLS1 and OLS0 in TRDFCR are set to 0 (initial output level is high, active level is low for normal-phase and counter-phase).
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(2) Transfer Timing from Buffer Register
• Transfer from the TRDGRD0, TRDGRC1, or TRDGRD1 register to the TRDGRB0, TRDGRA1, or TRDGRB1
register.
When bits CMD1 and CMD0 in the TRDFCR register are set to 10B, the content is transferred when the TRD1
register underflows.
When bits CMD1 and CMD0 are set to 11B, the content is transferred at compare match between registers TRD0
and TRDGRA0.
8.3.7 PWM3 Mode
In this mode, two PWM waveforms are output with the same period.
Figure 8-59 shows the Block Diagram of PWM3 Mode, Table 8-17 lists the PWM3 Mode Specifications, and Figure 8-60
shows an Operation Example in PWM3 Mode.
Figure 8-59. Block Diagram of PWM3 Mode
Buffer
Compare match signal
TRD0
TRDIOA0
Output
control
Comparator
TRDGRA0
TRDGRC0
Comparator
TRDGRA1
TRDGRC1
Comparator
TRDGRB0
TRDGRD0
Comparator
TRDGRB1
TRDGRD1
Compare match signal
Compare match signal
TRDIOB0
Output
control
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Table 8-17. PWM3 Mode Specifications
Item
Specification
Note
, fCLK, fCLK/2, fCLK/4, fCLK/8, fCLK/32
Count sources
fHOCO
Count operations
The TRD0 register is incremented (the TRD1 register is not used).
PWM waveform
PWM period: 1/fk × (m + 1)
Active level width of TRDIOA0 output: 1/fk × (m - n)
Active level width of TRDIOB0 output: 1/fk × (p - q)
fk: Frequency of count source
m: Value set in the TRDGRA0 register
n: Value set in the TRDGRA1 register
p: Value set in the TRDGRB0 register
q: Value set in the TRDGRB1 register
m+1
n+1
p+1
q+1
TRDIOA0 output
m-n
TRDIOB0 output
p-q
(When high is selected as the active level )
Count start condition
1 (count starts) is written to the TSTART0 bit in the TRDSTR register.
Count stop conditions
• 0 (count stops) is written to the TSTART0 bit in the TRDSTR register when the
CSEL0 bit in the TRDSTR register is set to 1.
The PWM output pin holds the output level before the count stops.
• When the CSEL0 bit in the TRDSTR register is set to 0, the count stops at compare
match with the TRDGRA0 register.
The PWM output pin holds the level after output change by compare match.
Interrupt request generation timing
• Compare match (content of the TRDi register matches content of the TRDGRji
register)
• TRD0 register overflow
TRDIOA0, TRDIOB0 pin function
PWM output
TRDIOA0, TRDIOD0, and
I/O port
TRDIOA1 to TRDIOD1 pin function
INTP0 pin function
Pulse output forced cutoff signal input (I/O port or INTP0 interrupt input)
Read from timer
The count value can be read by reading the TRD0 register.
Write to timer
The value can be written to the TRD0 register.
Selectable functions
• Pulse output forced cutoff signal input (see 8. 3. 1 (4) Pulse Output Forced Cutoff)
• Active level selectable for each pin.
• Buffer operation (see 8. 3. 1 (2) Buffer Operation)
<R>
Note
fHOCO is selected only when FRQSEL4 = 1 in the user option byte (000C2H/010C2H). When selecting fHOCO as
the count source for timer RD, set fCLK to fIH before setting bit 4 (TRD0EN) in peripheral enable register 1
(PER1). When changing fCLK to a clock other than fIH, clear bit 4 (TRD0EN) in peripheral enable register 1
(PER1) before changing.
Remark i = 0 or 1, j = A, B, C, or D
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(1) Operation Example
Figure 8-60. Operation Example in PWM3 Mode
Count source
Value in TRD0 register
FFFFH
m
n
p
q
0000H
Time
TSTART0 bit in
TRDSTR register
Count stops
Set to 0 by a program
CSEL0 bit in
TRDSTR register
m+1
n+1
m-n
p+1
q+1
High output by compare
match with TRDGRA1
register
TRDIOA0 output
TRDIOB0 output
p-q
Low output by compare
match with TRDGRA0
register
Initial output is
low
IMFA bit in
TRDSR0 register
Set to 0 by a program
Set to 0 by a program
IMFB bit in
TRDSR0 register
Set to 0 by a program
TRDGRA0 register
Set to 0 by a program
m
m
Transfer
TRDGRC0 register
Remark
j = A or B
m: Value set in TRDGRA0 register
n: Value set in TRDGRA1 register
p: Value set in TRDGRB0 register
q: Value set in TRDGRB1 register
m
Transfer
Following data
Transfer from buffer register
to general register
Transfer from buffer register
to general register
The above diagram applies under the following conditions :
• Both the TOA0 and TOB0 bits in the TRDOCR register are set to 0 (initial output is low, high output by compare
match with TRDGRj1 register, low output by compare match with TRDGRj0 register).
• The TRDBFC0 bit in the TRDMR register is set to 1 (TRDGRC0 register is buffer register for TRDGRA0 register).
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<R> 8.4 Timer RD Interrupt
Timer RD generates the timer RDi (i = 0 or 1) interrupt request from six sources for each timer RD0 and timer RD1.
Table 8-18 lists the Registers Associated with Timer RD Interrupt and Figure 8-61 shows the Timer RD Interrupt Block
Diagram.
Table 8-18. Registers Associated with Timer RD Interrup
Timer RD
Timer RD
Interrupt Request Flag
Interrupt Mask Flag
Priority Specification Flag
Status
Interrupt Enable
(Register)
(Register)
(Register)
Register
Register
Timer RD0
TRDSR0
TRDIER0
TRDIF0 (IF2H)
TRDMK0 (MK2H)
TRDPR00 (PR02H)
Timer RD1
TRDSR1
TRDIER1
TRDIF1 (IF2H)
TRDMK1 (MK2H)
TRDPR01 (PR02H)
TRDPR10 (PR12H)
TRDPR11 (PR12H)
Figure 8-61. Timer RD Interrupt Block Diagram
Timer RDi
IMFA bit
IMIEA bit
Timer RDi
interrupt request
IMFB bit
IMIEB bit
IMFC bit
IMIEC bit
IMFD bit
IMIED bit
UDF bit
OVF bit
OVIE bit
i = 0 to 1
IMFA, IMFB, IMFC, IMFD, OVF, UDF : TRDSRi register bit
IMIEA, IMIEB, IMIEC, IMIED, OVIE : TRDIERi register bit
Since the interrupt source (timer RD interrupt) is generated by a combination of multiple interrupt request sources for
timer RD, the following differences from other maskable interrupts apply:
• When a bit in the TRDSRi register is 1 and the corresponding bit in the TRDIERi register is 1 (interrupt enabled),
the TRDIFi bit in the IF2H register is set to 1 (interrupt requested).
• If multiple bits in the TRDIERi register are set to 1, use the TRDSRi register to determine the source of the
interrupt request.
• Since the bits in the TRDSRi register are not automatically set to 0 even if the interrupt is acknowledged, set the
corresponding bit to 0 in the interrupt routine.
• While multiple bits in the TRDIERi register are set to 1, if the first request source is met and the TRDIFi bit is set
to 1, and then the next request source is met, the TRDIFi bit is cleared to 0 when the interrupt is acknowledged.
However, if the previously met request source is cleared, the TRDIFi bit is set to 1 by the next generated request
source.
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8.5 Notes on Timer RD
<R> 8.5.1 SFR Read/Write Access
The timer RD SFRs are undefined when FRQSEL4 = 1 in the user option byte (000C2H/010C2H) and TRD0EN = 0 in
the PER1 register. If it is necessary to read the initial value, set fCLK to fIH and TRD0EN = 1 before reading.
When setting timer RD, set the TRD0EN bit in the PER1 register to 1 first. If the TRD0EN bit is 0, writes to the timer RD
control registers are ignored and all the read values are the initial values (except for the port registers and the port mode
registers).
The following registers must not be rewritten during count operation:
TRDELC, TRDMR, TRDPMR, TRDFCR, TRDOER1, PTO bit in TRDOER2, TRDDFi, TRDCRi, TRDIORAi, TRDIORCi,
TRDPOCRi
(1) TRDSTR Register
• The TRDSTR register can be set by an 8-bit memory manipulation instruction.
• When the CSELi bit (i = 0 or 1) in the TRDSTR register is set to 0 (count stops at compare match between
registers TRDi and TRDGRAi), the count does not stop and the TSTARTi bit remains unchanged even if 0 (count
stops) is written to the TSTARTi bit.
The TSTARTi bit is set to 0 (count stops) only by a compare match with the TRDGRAi register.
If the CSELi bit is 0 when rewriting the TRDSTR register, write 0 to the TSTARTi bit to change the CSELi bit to 1
without affecting count operation.
If 1 is written to the TSTARTi bit while the counter is stopped, count may be started.
To stop counting by a program, set the TSTARTi bit after setting the CSELi bit to 1. Even if 1 is written to the
CSELi bit and 0 is written to the TSTARTi bit at the same time (using one instruction), the count cannot be
stopped.
• Table 8-19 lists the TRDIOji (j = A, B, C, or D) Pin Output Level When Count Stops while using the TRDIOji (j = A,
B, C, or D) pin for timer RD output.
Table 8-19. TRDIOji (j = A, B, C, or D) Pin Output Level When Count Stops
Count Stop
TRDIOji Pin Output When Count Stops
When the CSELi bit is set to 1, write 0 to the
The pin holds the output level immediately before the count stops.
TSTARTi bit and the count stops.
(The pin outputs the initial output level selected by bits OLS0 and
OLS1 in the TRDFCR register in timer RD complementary and reset
synchronous PWM modes.)
When the CSELi bit is set to 0, the count stops at
The pin holds the output level after the output changes by compare
compare match with registers TRDi and TRDGRAi.
match. (The pin outputs the initial output level selected by bits OLS0
and OLS1 in the TRDFCR register in timer RD complementary and
reset synchronous PWM modes.)
Remark i = 0 or 1, j = A, B, C, or D
(2) TRDDFi Register (i = 0 or 1)
Set bits DFCK0 and DFCK1 in the TRDDFi register before starting count operation.
8.5.2 Mode Switching
• Set the count to stopped (set bits TSTART0 and TSTART1 to 0) before switching modes during operation.
• Set bits TRDIF0 and TRDIF1 to 0 before changing bits TSTART0 and TSTART1 from 0 to 1. Refer to CHAPTER 21
INTERRUPT FUNCTIONS for details.
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8.5.3 Count Source
• Switch the count source after the count stops.
[Changing procedure]
(1) Set the TSTARTi bit (i = 0 or 1) in the TRDSTR register to 0 (count stops).
<R>
(2) Change bits TCK0 to TCK2 in the TRDCRi register.
• When selecting fHOCO (64 MHz or 48 MHz) as the count source for timer RD, set fCLK to fIH before setting bit 4
(TRD0EN) in peripheral enable register 1 (PER1). When changing fCLK to a clock other than fIH, clear bit 4 (TRD0EN)
in peripheral enable register 1 (PER1) before changing.
8.5.4 Input Capture Function
• Set the pulse width of the input capture signal to three or more cycles of the timer RD operating clock.
• The value of the TRDi register is transferred to the TRDGRji register two to three cycles of the timer RD operating
clock (fCLK) after the input capture signal is applied to the TRDIOji pin (i = 0 or 1, j = A, B, C, or D) (when no digital
filter is used).
• In input capture mode, an input capture interrupt request for the active edge of the TRDIOji input is also generated
when the TRDTSTARTi bit in the TRDSTR register is 0 (count stops) if the edge selected by bits TRDIOj0 and
TRDIOj1 in the TRDIORji register is input to the TRDIOji pin (i = 0 or 1; j = A, B, C, or D).
8.5.5 Procedure for Setting Pins TRDIOAi, TRDIOBi, TRDIOCi, and TRDIODi (i = 0 or 1)
After a reset, the I/O ports multiplexed with pins TRDIOAi, TRDIOBi, TRDIOCi, and TRDIODi function as input ports.
To output from pins TRDIOAi, TRDIOBi, TRDIOCi, and TRDIODi, use the following setting procedure:
Changing procedure
(1) Set the mode and the initial value.
(2) Enable output from pins TRDIOAi, TRDIOBi, TRDIOCi, and TRDIODi (TRDOER1 register).
(3) Set the port register bits corresponding to pins TRDIOAi, TRDIOBi, TRDIOCi, and TRDIODi to 0.
(4) Set the port mode register bits corresponding to pins TRDIOAi, TRDIOBi, TRDIOCi, and TRDIODi to output mode.
(Output is started from pins TRDIOAi, TRDIOBi, TRDIOCi, and TRDIODi)
(5) Start the count (set bits TSTART0 and TSTART1 to 1).
To change the port mode register bits corresponding to pins TRDIOAi, TRDIOBi, TRDIOCi, and TRDIODi from output
mode to input mode, use the following setting procedure:
(1) Set the port mode register bits corresponding to pins TRDIOAi, TRDIOBi, TRDIOCi, and TRDIODi to input mode
(input is started from pins TRDIOAi, TRDIOBi, TRDIOCi, and TRDIODi).
(2) Set to the input capture function.
(3) Start the count (set bits TSTART0 and TSTART1 to 1).
When switching pins TRDIOAi, TRDIOBi, TRDIOCi, and TRDIODi from output mode to input mode, input capture
operation may be performed depending on the pin states. When the digital filter is not used, edge detection is performed
after two or more cycles of the operation clock have elapsed. When the digital filter is used, edge detection is performed
after five or more cycles of the sampling clock have elapsed.
8.5.6 External clock TRDCLK
Set the pulse width of the external clock applied to the TRDCLK pin to three or more cycles of the timer RD operating
clock.
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8.5.7 Reset Synchronous PWM Mode
• When reset synchronous PWM mode is used for motor control, make sure OLS0 = OLS1.
• Set to reset synchronous PWM mode by the following procedure:
[Changing procedure]
(1) Set the TSTART0 bit in the TRDSTR register to 0 (count stops).
(2) Set bits CMD1 and CMD0 in the TRDFCR register to 00B (timer mode, PWM mode, and PWM3 mode).
(3) Set bits CMD1 and CMD0 to 01B (reset synchronous PWM mode).
(4) Set the other registers associated with timer RD again.
8.5.8 Complementary PWM Mode
• When complementary PWM mode is used for motor control, make sure OLS0 = OLS1.
• Change bits CMD0 and CMD1 in the TRDFCR register in the following procedure.
Changing procedure: When setting to complementary PWM mode (including re-set), or changing the transfer timing
from the buffer register to the general register in complementary PWM mode.
(1) Set both the TSTART0 and TSTART1 bits in the TRDSTR register to 0 (count stops).
(2) Set bits CMD1 and CMD0 in the TRDFCR register to 00B (timer mode, PWM mode, and PWM3 mode).
(3) Set bits CMD1 and CMD0 to 10B or 11B (complementary PWM mode).
(4) Set the registers associated with other timer RD again.
Changing procedure: When stopping complementary PWM mode
(1) Set both the TSTART0 and TSTART1 bits in the TRDSTR register to 0 (count stops).
(2) Set bits CMD1 to CMD0 to 00B (timer mode, PWM mode, and PWM3 mode).
• Do not write to the TRDGRA0, TRDGRB0, TRDGRA1, or TRDGRB1 register during operation.
When changing the PWM waveform, transfer the values written to registers TRDGRD0, TRDGRC1, and TRDGRD1 to
registers TRDGRB0, TRDGRA1, and TRDGRB1 using the buffer operation.
However, to write data to the TRDGRD0, TRDGRC1, or TRDGRD1 register, set bits TRDBFD0, TRDBFC1, and
TRDBFD1 to 0 (general register). After this, bits TRDBFD0, TRDBFC1, and TRDBFD1 may be set to 1 (buffer register).
The PWM period cannot be changed.
• If the value set in the TRDGRA0 register is assumed to be m, the TRD0 register counts m - 1, m, m + 1, m, m - 1, in
that order, when changing from increment to decrement operation.
When changing from m to m + 1, the IMFA bit in the TRDSRi register is set to 1. Also, bits CMD1 and CMD0 in the
TRDFCR register are set to 11B (complementary PWM mode, buffer data transferred at compare match between
registers TRD0 and TRDGRA0), the content of the buffer registers (TRDGRD0, TRDGRC1, and TRDGRD1) is
transferred to the general registers (TRDGRB0, TRDGRA1, and TRDGRB1).
During operation of m + 1, m, and m - 1, the IMFA bit remains unchanged and data is not transferred to registers such
as the TRDGRA0 register.
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Figure 8-62. Operation at Compare Match between Registers TRD0 and TRDGRA0 in Complementary PWM Mode
Count value in
TRD0 register
m+1
Value set in TRDGRA0
register m
Time
Set to 0 by a program
No change
IMFA bit in
TRDSR0 register
Transferred from buffer
register
TRDGRB0 register
TRDGRA1 register
TRDGRB1 register
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register
When bits CMD1 and CMD0 in the
TRDFCR register are set to 11B
(transfer from the buffer register to the
general register at compare match
between registers TRD0 and TRDGRA0).
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The TRD1 register counts 1, 0, FFFFH, 0, 1, in that order, when changing from decrement to increment operation.
Counting from 1, to 0, to FFFFH causes the UDF bit in the TRDSRi register to be set to 1. Also, when bits CMD1 and
CMD0 in the TRDFCR register are set to 10B (complementary PWM mode, buffer data transferred at underflow of the
TRD1 register), the content of the buffer registers (TRDGRD0, TRDGRC1, and TRDGRD1) is transferred to the
general registers (TRDGRB0, TRDGRA1, and TRDGRB1).
During operation of FFFFH, 0, and 1, data is not transferred to registers such as the TRDGRB0 register.
Also, at this time, the OVF bit in the TRDSRi register remains unchanged.
Figure 8-63. Operation When TRD1 Register Underflows in Complementary PWM Mode
Count value in
TRD1 register
1
0
Time
FFFFH
Set to 0 by a program
UDF bit in
TRDSR1 register
OVF bit in
TRDSR1 register
No change
0
Transferred from
buffer register
TRDGRB0 register
TRDGRA1 register
TRDGRB1 register
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register
When bits CMD1 and CMD0 in the
TRDFCR register are set to 10B
(transfer from the buffer register to the
general register when the TRD1 register
underflows).
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• The timing of data transfer from the buffer register to the general register should be selected using bits CMD0
and CMD1 in the TRDFCR register. However, regardless of the values of bits CMD0 and CMD1, transfer takes
place with the following timing when duty cycle is 0% and duty cycle is 100%.
Value in buffer register ≥ value in TRDGRA0 register (duty cycle is 0%):
Transfer take place at underflow of the TRD1 register.
After this, when the buffer register is set to 0001H or above and a smaller value than the value of the
TRDGRA0 register, and the TRD1 register underflows for the first time after setting, the value is transferred to
the general register. After that, the value is transferred with the timing selected by bits CMD1 and CMD0.
However, no waveform with duty cycle 0% can be generated while the initial value of the buffer register is
FFFFH. To generate a waveform with duty cycle 0%, set the value of the buffer register ≥ TRDGRA0 by writing
to the buffer register.
Figure 8-64. Operation When Value in Buffer Register ≥Value in TRDGRA0 Register in Complementary
PWM Mode
Value in
TRDi register
n3
m+1
n2
Count value in TRD0
n1
Count value in TRD1
Time
0000H
TRDGRD0 register
n2
Transfer
TRDGRB0 register
n1
Transfer with timing set by
bits CMD1 and CMD0
n2
n3
Transfer
n2
Transfer at
underflow of
TRD1 register
because of n3 >
m
n1
Transfer
n3
Transfer
n2
Transfer at
underflow of TRD1
register because
of first setting to
n2 < m
n1
Transfer with timing set by
bits CMD1 and CMD0
TRDIOB0 output
TRDIOD0 output
Remark
m: Value set in TRDGRA0 register
The above diagram applies under the following conditions :
• Bits CMD1 and CMD0 in the TRDFCR register are set to 11B
(data in the buffer register is transferred at compare match between registers TRD 0 and TRDGRA0 in complementary
PWM mode).
• Both the OSL0 and OLS1 bits in the TRDFCR register are set to 1 (active high for normal-phase and counter-phase).
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When the value in the buffer register is set to 0000H (duty cycle is 100%):
Transfer takes place at compare match between registers TRD0 and TRDGRA0.
After this, when the buffer register is set to 0001H or above and a smaller value than the value of the TRDGRA0
register, and a compare match occurs between registers TRD0 and TRDGRA0 for the first time after setting, the
value is transferred to the general register. After that, the value is transferred with the timing selected by bits CMD0
and CMD1.
Figure 8-65. Operation When Value in Buffer Register is Set to 0000H in Complementary PWM Mode
Value in
TRDi register
m+1
n2
Count value in TRD0
n1
Count value in TRD1
Time
0000H
0000H
n1
TRDGRD0 register
Transfer
TRDGRB0 register
n2
n1
Transfer
n1
Transfer with timing
set by bits CMD1
and CMD0
Transfer
0000H
Transfer at compare
match between
registers TRD0 and
TRDGRA0 because
content in TRDGRD0
register is set to 0000H
Transfer
n1
Transfer at compare
match between
registers TRD0 and
TRDGRA0 because
of first setting to
0001H < 1 < m
Transfer with timing
set by bits CMD1 and
CMD0
TRDIOB0 output
TRDIOD0 output
Remark
m: Value set in TRDGRA0 register
The above diagram applies under the following conditions :
• Bits CMD1 and CMD0 in the TRDFCR register are set to 10B (data in the buffer register is transferred at underflow of the
TRD1 register in complementary PWM mode).
• Both the OLS0 and OLS1 bits in the TRDFCR register are set to 1 (active high for normal-phase and counter-phase).
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CHAPTER 9 TIMER RG
Timer RG is a 16-bit timer with two input pins and two I/O pins.
9.1 Overview
Timer RG uses fCLK as its operating clock.
Figure 9-1 shows the Timer RG Block Diagram and Table 9-1 lists the Timer RG Pin Configuration.
Timer RG supports the following three modes:
• Timer mode:
- Input capture function: Count at the rising edge, falling edge, or both rising/falling edges
- Output compare function: Low output/high output/toggle output
• PWM mode: PWM output available with any duty cycle
• Phase counting mode: Automatic measurement available for the counts of the two-phase encoder
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Figure 9-1. Timer RG Block Diagram
fCLK, fCLK/2, fCLK /4, fCLK/8, fCLK /32
TRG register
TRGGRA register
Comparator
TRGGRB register
Count source
selection circuit
Data bus
TRGGRC register
TRGGRD register
TRGCLKA
TRGCLKB
TRGIOA
Timer RG Control Circuit
TRGMR register
TRGIOB
TRGCNTC register
TRGCR register
TRGIER register
TRGSR register
Timer RG
interrupt request
TRGIOR register
Table 9-1. Timer RG Pin Configuration
Pin Name
TRGCLKA
Assigned Pin
I/O
P00
Input
Function
• In phase counting mode
A-phase input
• In other than phase counting mode
External clock A input
TRGCLKB
P01
Input
• In phase counting mode
B-phase input
• In other than phase counting mode
External clock B input
TRGIOA
P50
Input/ Output
• In timer mode (output compare function)
TRGGRA output-compare output
• In timer mode (input capture function)
TRGGRA input-capture input
• In PWM mode
PWM output
TRGIOB
P51
Input/ Output
• In timer mode (output compare function)
TRGGRB output-compare output
• In timer mode (input capture function)
TRGGRB input-capture input
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9.2 Registers
Table 9-2 lists the Timer RG Register Configuration.
Table 9-2. Timer RG Register Configuration
Register Name
Peripheral enable register 1
Timer RG Mode Register
Symbol
After Reset
Address
Access Size
PER1
00H
F007AH
8
TRGMR
00H
F0250H
8
TRGCNTC
00H
F0251H
8
Timer RG Control Register
TRGCR
00H
F0252H
8
Timer RG Interrupt Enable Register
TRGIER
00H
F0253H
8
Timer RG Status Register
TRGSR
00H
F0254H
8
Timer RG I/O Control Register
TRGIOR
00H
F0255H
8
TRG
0000H
F0256H
16
TRGGRA
FFH
F0258H
16
FFH
F0259H
FFH
F025AH
FFH
F025BH
FFH
FFF60H
FFH
FFF61H
FFH
FFF62H
FFH
FFF63H
00H
FFF00H
Timer RG Count Control Register
Timer RG Counter
Timer RG General Register A
Timer RG General Register B
Timer RG General Register C
Timer RG General Register D
Port register 0
Port register 5
TRGGRB
TRGGRC
TRGGRD
P0
16
16
16
8
P5
00H
FFF05H
8
Port mode register 0
PM0
FFH
FFF20H
8
Port mode register 5
PM5
FFH
FFF25H
8
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CHAPTER 9 TIMER RG
9.2.1 Peripheral enable register 1 (PER1)
The PER1 register is used to enable or disable supplying the clock to the peripheral hardware. Clock supply to the
hardware that is not used is also stopped so as to decrease the power consumption and noise.
When using the timer RG, be sure to set bit 6 (TRGEN) to 1.
The PER1 register can be set by a 1-bit or 8-bit memory manipulation instruction.
Reset signal generation clears this register to 00H.
Figure 9-2. Format of Peripheral Enable Register 1 (PER1)
Address: F007AH
Symbol
PER1
After reset: 00H
<7>
DACEN
<6>
Note
TRGEN
TRGEN
R/W
<5>
CMPEN
Note
<4>
<3>
2
1
<0>
TRD0EN
DTCEN
0
0
TRJ0EN
Control of timer RG input clock supply
Stops input clock supply.
• SFR used by timer RG cannot be written.
0
• Timer RG is in the reset status.
Enables input clock supply.
• SFR used by timer RG can be read and written.
1
Note
Only for products with 96 KB or more code flash memory.
Cautions 1. When setting timer RG, be sure to set the TRGEN bit to 1 first. If TRGEN = 0, writing
to a control register of timer RG is ignored, and all read values are default values
(except for port mode registers 0, 5 (PM0, PM5), and port registers 0, 5 (P0, P5)).
2. Be sure to clear the following bits to 0.
Products with 64 KB or less code flash memory: bits 1, 2, 5, and 7
Products with 96 KB or more code flash memory: bits 1 and 2
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9.2.2 Timer RG Mode Register (TRGMR)
Figure 9-3. Format of Timer RG Mode Register (TRGMR)
Address: F0250H
Symbol
After reset: 00H
<7>
TRGMR
<6>
<5>
TRGSTART TRGELCICE TRGDFCK1
TRGSTART
<4>
<3>
<2>
<1>
<0>
TRGDFCK0
TRGDFB
TRGDFA
TRGMDF
TRGPWM
TRG count start
0
Count stops, and PWM output signal (TRGIOA pin) is initialized (in PWM mode)
1
Count starts
ELC input capture request select Notes 1, 2
TRGELCICE
0
External output signal B/digital filtering signal B is selected
1
Event input (input capture) from ELC is selected
Digital filter function clock select Note 1
TRGDFCK1
TRGDFCK0
0
0
fCLK/32
0
1
fCLK/8
R/W
R/W
R/W
R/W
R/W
1
0
fCLK
1
1
Clock selected by bits TRGTCK0 to TRGTCK2 in TRGCR register
TRGDFB
R/W
Digital filer function select for TRGIOB pin
0
Digital filter function not used
1
Digital filter function used
R/W
R/W
If the digital filter function is enabled, edge detection is performed after five or more cycles of the digital filter
sampling clock have elapsed.
TRGDFA
Digital filer function select for TRGIOA pin
0
Digital filter function not used
1
Digital filter function used
R/W
R/W
If the digital filter function is enabled, edge detection is performed after five or more cycles of the digital filter
sampling clock have elapsed.
TRGMDF
Phase counting mode select
0
Increment
1
Phase counting mode
R/W
R/W
When the TRGMDF bit is set to 0, the counter counts the count source set by bits TRGTCK0 to TRGTCK2 in
the TRGCR register.
When the TRGMDF bit is set to 1, the counter counts the phase of input signals from the TRGCLKj pin(j = A or
B) as listed in table 9-15 Increment/Decrement Conditions for TRG Register
TRGPWM
Notes
PWM mode select
0
Timer Mode
1
PWM mode
R/W
R/W
1. Set this bit while the TRGSTART bit is 0 (count stops).
2. To enable event input (input capture) from the event link controller (ELC), set TRGIOB2 = 1 and TRGIOB1
and TRGIOB0 = 00B (rising edge) in the TRGIOR register.
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9.2.3 Timer RG Count Control Register (TRGCNTC)
The TRGCNTC register is used in phase counting mode. This register is used to set the count conditions for phase
counting mode.
Figure 9-4. Format of Timer RG Count Control Register (TRGCNTC)
Address: F0251H
After reset: 00H
Symbol
7
6
5
4
3
2
1
0
TRGCNTC
CNTEN7
CNTEN6
CNTEN5
CNTEN4
CNTEN3
CNTEN2
CNTEN1
CNTEN0
CNTEN7
Counter enable 7
0
Disabled
1
Increment
R/W
R/W
When TRGCLKA input is low level and at the rising edge of TRGCLKB input
CNTEN6
Counter enable 6
0
Disabled
1
Increment
R/W
R/W
When TRGCLKB input is high level and at the rising edge of TRGCLKA input
CNTEN5
Counter enable 5
0
Disabled
1
Increment
R/W
R/W
When TRGCLKA input is high level and at the falling edge of TRGCLKB input
CNTEN4
Counter enable 4
0
Disabled
1
Increment
R/W
R/W
When TRGCLKB input is low level and at the falling edge of TRGCLKA input
CNTEN3
Counter enable 3
0
Disabled
1
Decrement
R/W
R/W
When TRGCLKB input is high level and at the falling edge of TRGCLKA input
CNTEN2
Counter enable 2
0
Disabled
1
Decrement
R/W
R/W
When TRGCLKA input is low level and at the falling edge of TRGCLKB input
CNTEN1
Counter enable 1
0
Disabled
1
Decrement
R/W
R/W
When TRGCLKB input is low level and at the rising edge of TRGCLKA input
CNTEN0
Counter enable 0
0
Disabled
1
Decrement
R/W
R/W
When TRGCLKA input is high level and at the rising edge of TRGCLKB input
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9.2.4 Timer RG Control Register (TRGCR)
When writing to the TRGCR register, make sure the TRGSTART bit in the TRGMR register is 0 (count stops).
Figure 9-5. Format of Timer RG Control Register (TRGCR)
Address: F0252H
After reset: 00H
Symbol
7
<6>
<5>
<4>
<3>
<2>
<1>
<0>
TRGCR
-
TRGCCLR1
TRGCCLR0
TRGCKEG1
TRGCKEG0
TRGTCK2
TRGTCK1
TRGTCK0
Bit 7
-
Nothing is assigned
The write value must be 0. The read value is 0.
R/W
R
TRGCCLR1
TRGCCLR0
TRG register clear source select
0
0
Clear disabled
0
1
Clear by input capture or compare match with TRGGRA
1
0
Clear by input capture or compare match with TRGGRB
1
1
Do not set.
TRGCKEG1
TRGCKEG0
0
0
Count at the rising edge
0
1
Count at the falling edge
1
0
Count at both the rising/falling edges
1
1
Do not set.
R/W
R/W
External clock active edge select Notes 1, 2
R/W
Count source select Note 1
TRGTCK2
TRGTCK1
TRGTCK0
0
0
0
fCLK
0
0
1
fCLK/2
0
1
0
fCLK/4
0
1
1
fCLK/8
1
0
0
fCLK/32
1
0
1
TRGCLKA input
1
1
0
Do not set.
1
1
1
TRGCLKB input
R/W
R/W
R/W
Notes 1. In phase counting mode, the settings of bits TRGTCK0 to TRGTCK2 and bits TRGCKEG0 and TRGCKEG1
are disabled and the operation of phase counting mode has priority.
2. Bits TRGCKEG0 and TRGCKEG1 are enabled when bits TRGTCK0 to TRGTCK2 are set to an external
clock (TRGCLKA or TRGCLKB). When not set to an external clock, they are disabled.
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9.2.5 Timer RG Interrupt Enable Register (TRGIER)
Figure 9-6. Format of Timer RG Interrupt Enable Register (TRGIER)
Address: F0253H
After reset: 00H
Symbol
7
6
5
4
<3>
<2>
<1>
<0>
TRGIER
-
-
-
-
TRGOVIE
TRGUDIE
TRGIMIEB
TRGIMIEA
Bit 7 to 4
-
Nothing is assigned
The write value must be 0. The read value is 0.
TRGOVIE
Overflow interrupt enable
0
Interrupt by TRGOVF bit disabled
1
Interrupt by TRGOVF bit enabled
TRGUDIE
Interrupt by TRGUDF bit disabled
1
Interrupt by TRGUDF bit enabled
TRGIMIEB
Input-capture/compare-match interrupt enable B
0
Interrupt by TRGIMFB bit disabled
1
Interrupt by TRGIMFB bit enabled
TRGIMIEA
Remark
Input-capture/compare-match interrupt enable A
0
Interrupt by TRGIMFA bit disabled
1
Interrupt by TRGIMFA bit enabled
R
R/W
R/W
Underflow interrupt enable
0
R/W
R/W
R/W
R/W
R/W
R/W
R/W
TRGIMFA, TRGIMFB, TRGUDF, TRGOVF: Bits in TRGSR register
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9.2.6 Timer RG Status Register (TRGSR)
Figure 9-7. Format of Timer RG Status Register (TRGSR)
Address: F0254H
After reset: 00H
Symbol
7
6
5
<4>
<3>
<2>
<1>
<0>
TRGSR
-
-
-
TRGDIRF
TRGOVF
TRGUDF
TRGIMFB
TRGIMFA
Bit 7 to 5
-
Nothing is assigned
The write value must be 0. The read value is 0.
TRGDIRF
Count direction flag
0
TRG register is decremented
1
TRG register is incremented
TRGOVF
R/W
R
R/W
R
Overflow flag Note 1
[Condition for setting to 0]
R/W
R/W
Write 0 after reading Note 2
[Condition for setting to 1]
See Table 9-3 Conditions for Setting Each Flag to 1
TRGUDF
Underflow flag
[Condition for setting to 0]
R/W
R/W
Write 0 after reading Note 2
[Condition for setting to 1]
See Table 9-3 Conditions for Setting Each Flag to 1
TRGIMFB
Input-capture/compare-match flag B
[Condition for setting to 0]
R/W
R/W
Write 0 after reading Notes 2, 3
[Condition for setting to 1]
See Table 9-3 Conditions for Setting Each Flag to 1
TRGIMFA
Input-capture/compare-match flag A
[Condition for setting to 0]
R/W
R/W
Write 0 after reading Notes 2, 3
[Condition for setting to 1]
See Table 9-3 Conditions for Setting Each Flag to 1
Notes 1. When the counter value of timer RG changes from FFFFH to 0000H, the TRGOVF bit is set to 1. Also, if the
counter value of timer RG changes from FFFFH to 0000H due to an input capture/compare match during
operation according to the settings of bits TRGCCLR0 and TRGCCLR1 in the TRGCR register, the TRGOVF
bit is set to 1.
2. The writing results are as follows:
• If the read value is 1, writing 0 to the bit sets it to 0.
• If the read value is 0, the bit remains unchanged even if 0 is written to it. (Even if the bit is changed from 0
to 1 after reading and then 0 is written to it, it remains 1.)
• Writing 1 has no effect.
3. When the DTC is used, bits TRGIMFA and TRGIMFB are set to 1 after DTC transfer is completed.
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Table 9-3. Conditions for Setting Each Flag to 1
Timer Mode Note 1
Bit Symbol
Input Capture Function
PWM Mode
Output Compare Function
TRGOVF
When the TRG register overflows.
TRGUDF
When the TRG register underflows (only in phase counting mode).
TRGIMFB
Input edge of TRGIOB pin Note 2
When the values of registers TRG and TRGGRB match.
TRGIMFA
Note 2
When the values of registers TRG and TRGGRA match.
Input edge of TRGIOA pin
Notes 1. Phase counting mode is the counting method of the timer RG count register. The above timer modes and
PWM mode can be used by making the corresponding settings.
2. Edge selected by bits TRGIOj0 and TRGIOj1 (j = A or B) in the TRGIOR register.
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9.2.7 Timer RG I/O Control Register (TRGIOR)
Figure 9-8. Format of Timer RG I/O Control Register (TRGIOR)
Address: F0255H
After reset: 00H
Symbol
<7>
<6>
<5>
<4>
<3>
<2>
<1>
<0>
TRGIOR
TRGBUFB
TRGIOB2
TRGIOB1
TRGIOB0
TRGBUFA
TRGIOA2
TRGIOA1
TRGIOA0
TRGBUFB
TRGGRD register function select
0
Not used as buffer register for TRGGRB register
1
Used as buffer register for TRGGRB register
TRGGRB mode select Notes 1, 2
TRGIOB2
0
Output compare function
1
Input capture function
R/W
R/W
R/W
R/W
TRGIOB1
TRGIOB0
TRGGRB control
0
0
Pin output by compare match is disabled
0
1
Low output
1
0
High output
1
1
Toggle output
R/W
R/W
In the output compare function, output of compare match between registers TRG and TRGGRB
TRGIOB1
TRGIOB0
0
0
TRGGRB control
R/W
Rising edge of TRGIOB
0
1
Falling edge of TRGIOB
1
0
Both edges of TRGIOB
1
1
Do not set.
R/W
In the input capture function, input capture of content of TRG register to TRGGRB register
TRGBUFA
TRGGRC register function select
0
Not used as buffer register for TRGGRA register
1
Used as buffer register for TRGGRA register
TRGGRA mode select Notes 1, 2
TRGIOA2
0
Output compare function
1
Input capture function
R/W
R/W
R/W
R/W
TRGIOA1
TRGIOA0
TRGGRA control
0
0
Pin output by compare match is disabled
0
1
Low output
1
0
High output
1
1
Toggle output
R/W
R/W
In the output compare function, output of compare match between registers TRG and TRGGRA
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TRGIOA1
TRGIOA0
TRGGRA control
0
0
Rising edge of TRGIOA
0
1
Falling edge of TRGIOA
1
0
Both edges of TRGIOA
1
1
Do not set.
R/W
R/W
In the input capture function, input capture of content of TRG register to TRGGRA register
Notes 1. When the TRGIOj2 (j = A or B) bit is 1 (input capture function), the TRGGRj register functions as an input
capture register.
2. When the TRGIOj2 (j = A or B) bit is 0 (output compare function), the TRGGRj register functions as a
compare match register. After a reset, the TRGIOj pin outputs as follows until bits TRGIOj0 and TRGIOj1 are
set and the first compare match occurs.
TRGIOj1 and TRGIOj0 = 01B: High output
10B: Low output
11B: Low output
<R>
This TRGIOR register controls I/O pins in timer mode. It is disabled in PWM mode. Set the TRGIOR register
while the count is stopped (TRGSTART in TRGMR register = 0).
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9.2.8 Timer RG Counter (TRG)
The TRG register is connected to the CPU via the internal 16-bit bus and should be always accessed in 16-bit units.
This register operates incrementing and can also operate free-running, period counting, or external event counting. It can
be cleared to 0000H by the compare match with the corresponding TRGGRA or TRGGRB register, or the input capture to
registers TRGGRA and TRGGRB (count clear function).
When the TRG register overflows (FFFFH → 0000H), the TRGOVF flag in the TRGSR register is set to 1.
When the TRG register underflows (0000H → FFFFH), the TRGUDF flag in the TRGSR register is set to 1.
Figure 9-9. Format of Timer RG Counter (TRG)
Address: F0256H
After reset: 0000H
Symbol
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
TRG
TRG
TRG
TRG
TRG
TRG
TRG
TRG
TRG
TRG
TRG
TRG
TRG
TRG
TRG
TRG
TRG
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
TRG15 to TRG0
Bits 15 to 0
Function
In phase counting mode, count operation is increment/decrement.
Setting Range
R/W
0000H to FFFFH
R/W
In other modes, count operation is increment.
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9.2.9 Timer RG General Registers A, B, C, and D (TRGGRA, TRGGRB, TRGGRC, TRGGRD)
Registers TRGGRA and TRGGRB are 16-bit readable/writable registers with both the output compare and input capture
register functions. These functions can be switched by setting the TRGIOR register.
When registers TRGGRA and TRGGRB are used as output compare registers, the values of registers TRGGRA and
TRGGRB and the value of the TRG register are always compared. When their values match (compare match), bits
TRGIMFA and TRGIMFB in the TRGSR register are set to 1. Compare match output can be set by the TRGIOR register.
When registers TRGGRA and TRGGRB are used as input capture registers, the value of the TRG register is stored
upon detecting externally input capture signals. At this time, the TRGIMFA/TRGIMFB bit is set to 1. The detection edge of
input capture signals is selected by setting the TRGIOR register.
The TRGGRC register can also be used as the buffer register for the TRGGRA register and the TRGGRD register can
be used as the buffer register for the TRGGRB register, respectively. These functions can be selected by setting bits
TRGBUFA and TRGBUFB in the TRGIOR register.
For example, when the TRGGRA register is set as an output compare register and the TRGGRC register is set as the
buffer register for the TRGGRA register, the value of the TRGGRC register is transferred to the TRGGRA register each
time compare match A occurs.
When the TRGGRA register is set as an input capture register and the TRGGRC register is set as the buffer register for
the TRGGRA register, the value of the TRG register is transferred to the TRGGRA register and the value of the TRGGRA
register value is transferred to the TRGGRC register each time an input capture occurs.
Registers TRGGRA, TRGGRB, TRGGRC, and TRGGRD can be read or written in 16-bit units
Figure 9-10. Format of Timer RG General Registers A, B, C, and D (TRGGRA, TRGGRB, TRGGRC, TRGGRD)
Address : F0258H (TRGGRA), F025AH (TRGGRB), FFF60H (TRGGRC), FFF62H (TRGGRD)
After Reset: FFFFH
Symbol
TRGGRi
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
TRG
TRG
TRG
TRG
TRG
TRG
TRG
TRG
TRG
TRG
TRG
TRG
TRG
TRG
TRG
TRG
GRi15
GRi14
GRi13
GRi12
GRi11
GRi10
GRi9
GRi8
GRi7
GRi6
GRi5
GRi4
GRi3
GRi2
GRi1
GRi0
Remark
i = A, B, C, D
TRGGRi15
Function
R/W
to TRGGRi0
Bits 15 to 0
Function varies depending on the mode or the function.
R/W
Table 9-4 lists the TRGGRA, TRGGRB, TRGGRC, and TRGGRD Register Functions.
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Table 9-4. TRGGRA, TRGGRB, TRGGRC, and TRGGRD Register Functions
Mode,
Register
Setting
Function
Function
TRGIOR (TRGIOA2 = 1)
Input capture
Input capture register (stores value of TRG register)
TRGGRA
TRGMR (TRGPWM = 0)
TRGIOR (TRGIOB2 = 1)
Input capture register (stores value of TRG register)
TRGGRB
TRGMR (TRGPWM = 0)
Output
TRGIOR (TRGIOA2 = 0)
Output compare register (stores compare value with TRG register and
TRGMR (TRGPWM = 0)
outputs set value to TRGIOA at compare match)
TRGIOR (TRGIOB2 = 0)
Output compare register (stores compare value with TRG register and
TRGMR (TRGPWM = 0)
outputs set value to TRGIOB at compare match)
TRGGRA
compare
TRGGRB
Output compare register (outputs high level to TRGIOA at compare
PWM
TRGGRA
match)
TRGMR (TRGPWM = 1)
Output compare register (outputs low level to TRGIOA at compare
TRGGRB
match)
Common
TRGGRC
TRGIOR (TRGBUFA = 0)
Not used
TRGGRD
TRGIOR (TRGBUFB = 0)
Not used
Buffer register for TRGGRA (transfers from/to TRGGRA)
• When TRGIOA2 = 1
Input capture signal: Receive previous input capture value from
TRGGRC
TRGIOR (TRGBUFA = 1)
TRGGRA
• When TRGIOA2 = 0
TRG and TRGGRA compare match: Send next expected compare
value to TRGGRA
Buffer register for TRGGRB (transfers from/to TRGGRB)
• When TRGIOB2 = 1
Input capture signal: Receive previous input capture value from
TRGGRD
TRGIOR (TRGBUFB = 1)
TRGGRB
• When TRGIOB2 = 0
TRG and TRGGRB compare match: Send next expected compare
value to TRGGRB
Caution When the setting of bits TRGTCK2 to TRGTCK0 in the TRGCR register is 000B (fCLK) and the compare
value is set to 0000H, a request signal to the data transfer controller (DTC) and the event link
controller (ELC) is generated only once immediately after the count starts.
When the compare value is 0001H or higher, a request signal is generated each time a compare
match occurs.
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CHAPTER 9 TIMER RG
Port mode registers 0, 5 (PM0, PM5)
These registers set input/output of ports 0, 5 in 1-bit units.
When using the ports (P50/TRGIOA, P51/TRGIOB) to be shared with the timer output pin for timer output, set the port
mode register (PMxx) bit and port register (Pxx) bit corresponding to each port to 0.
Example:
When using P50/TRGIOA for timer output
Set the PM50 bit of port mode register 5 to 0.
Set the P50 bit of port register 5 to 0.
When using the ports (P50/TRGIOA, P51/TRGIOB) to be shared with the timer input pin for timer input, set the port
mode register (PMxx) bit corresponding to each port to 1. At this time, the port register (Pxx) bit may be 0 or 1.
Example:
When using P50/TRGIOA for timer input
Set the PM50 bit of port mode register 5 to 1.
Set the P50 bit of port register 5 to 0 or 1.
The PM0 and PM5 registers can be set by a 1-bit or 8-bit memory manipulation instruction.
Reset signal generation sets these registers to FFH.
Figure 9-11. Format of Port Mode Registers 0, 5 (PM0, PM5) (100-pin products)
Address: FFF20H After reset: FFH R/W
Symbol
7
6
5
4
3
2
1
0
PM0
1
PM06
PM05
PM04
PM03
PM02
PM01
PM00
Address: FFF25H After reset: FFH R/W
Symbol
7
6
5
4
3
2
1
0
PM5
PM57
PM56
PM55
PM54
PM53
PM52
PM51
PM50
Pmn pin I/O mode selection
PMmn
(m = 0, 5; n = 0 to 7)
Remark
0
Output mode (output buffer on)
1
Input mode (output buffer off)
The figure shown above presents the format of port mode registers 0 and 5 of the 100-pin products. The
format of the port mode register of other products, see Table 4-5. or Table 4-6. PMxx, Pxx, PUxx, PIMxx,
POMxx, PMCxx registers and the bits mounted on each product.
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9.3 Operation
9.3.1 Items Common to Multiple Modes and Functions
(1) Count Sources
Table 9-5 lists the Count Source Selection and Figure 9-12 shows the Count Source Block Diagram.
When phase counting mode is selected, the settings of bits TRGTCK0 to TRGTCK2 and bits TRGCKEG0 and
TRGCKEG1 in the TRGCR register are disabled.
Table 9-5. Count Source Selection
Count Source
Selection Method
fCLK, fCLK/2, fCLK/4, fCLK/8,
The count source is selected by bits TRGTCK0 to TRGTCK2 in the TRGCR register.
fCLK/32
External signal input to
Bits TRGTCK2 to TRGTCK0 in the TRGCR register are set to 101B (TRGCLKA input) or 111B
TRGCLKA or TRGCLKB pin
(TRGCLKB input).
The active edge is selected by bits TRGCKEG0 and TRGCKEG1 in the TRGCR register.
The corresponding bit of the port mode register is set to 1 (input mode).
Figure 9-12. Count Source Block Diagram
TRGTCK2 to TRGTCK0
fCLK
= 000B
= 001B
fCLK/2
= 010B
fCLK/4
= 011B
fCLK/8
Count source
TRG register
= 100B
fCLK/32
= 101B
TRGCLKA
= 111B
TRGCLKB
Remark TRGTCK0 to TRGTCK2: Bits in TRGCR register
The pulse width of an external clock input to the TRGCLKj pin (j = A or B) should be set to three cycles or more of the
timer RG operating clock (fCLK).
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(2) Buffer Operation
The TRGBUFA or TRGBUFB bit in the TRGIOR register can be used to select the TRGGRC or TRGGRD register
as the buffer register for the TRGGRA or TRGGRB register.
• Buffer register for TRGGRA register: TRGGRC register
• Buffer register for TRGGRB register: TRGGRD register
Buffer operation differs depending on the mode. Table 9-6 lists the Buffer Operation in Each Mode, figure 9-13
shows the Buffer Operation for Input Capture Function and figure 9-14 shows the Buffer Operation for Output
Compare Function.
Table 9-6. Buffer Operation in Each Mode
Function, Mode
Transfer Timing
Input capture function
Transfer Destination Register
Input capture signal input
The content of the TRGGRA (TRGGRB) register is
transferred to the buffer register.
Output compare function
Compare match between the TRG register
The content of the buffer register is transferred to the
PWM mode
and the TRGGRA (TRGGRB) register
TRGGRA (TRGGRB) register.
Figure 9-13. Buffer Operation for Input Capture Function
TRGIOA input
(input capture signal)
TRGGRC
register
TRGGRA
register
TRG
register
TRGIOA input
TRG register
n
n-1
n+1
Transfer
TRGGRA register
m
n
Transfer
TRGGRC register
(buffer)
m
The above diagram applies under the following conditions:
• The TRGBUFA bit in the TRGIOR register is set to 1 (TRGGRC register is used as buffer register for TRGGRA register).
• Bits TRGIOA2 to TRGIOA0 in the TRGIOR register are set to 100B (input capture at the rising edge).
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Figure 9-14. Buffer Operation for Output Compare Function
Compare match signal
TRGGRC
register
TRG register
TRGGRA register
TRGGRA
register
m
m-1
TRG
register
Comparator
m+1
m
n
Transfer
TRGGRC register
(buffer)
n
TRGIOA output
The above diagram applies under the following conditions:
• The TRGBUFA bit in the TRGIOR register is set to 1 (TRGGRC register is used as buffer register for TRGGRA register).
• Bits TRGIOA2 to TRGIOA0 in the TRGIOR register are set to 001B (low output by compare match).
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(3) Digital Filter
The TRGIOj input (j = A or B) is sampled, and when the sampled input level matches three times, its level is
determined. Select the digital filter function and sampling clock using the TRGMR register.
Figure 9-15 shows a Block Diagram of Digital Filter.
Figure 9-15. Block Diagram of Digital Filter
TRGTCK2 to TRGTCK0
fCLK
= 001B
= 010B
fCLK/2
fCLK/4
= 000B
= 011B
fCLK/8
= 100B
= 101B
fCLK/32
TRGCLKA
TRGDFCK1 and TRGDFCK0
fCLK/32 = 00B
= 01B
fCLK/8
fCLK = 10B
= 11B
Count source
Synchronized by two flip-flops
= 111B
TRGCLKB
Sampling clock
Timer RG operating clock
fCLK
TRGIOj input
signal
C
D
C
Q
Latch
C
D
Q
Latch
D
C
Q
Latch
D
Match detection
circuit
(flip-flop output)
Q
Latch
Edge
detection
circuit
TRGIOA2 to TRGIOA0
TRGIOB2 to TRGIOB0
DFj
1
0
Edge
detection
circuit
Clock cycle selected by
TRGTCK2 to TRGTCK0
(or TRGDFCK0 and TRGDFCK1)
Sampling clock
Matched three times, so
recognized as a signal
change
TRGIOj input signal
Input signal
after digital filtering
Remark
j = A or B
If fails to match three times, is
assumed to be noise and not
transmitted
Signal transmission delayed
up to five sampling clocks
TRGTCK0 to TRGTCK2: Bits in TRGCR register
TRGDFCK0, TRGDFCK1, TRGDFj: Bits in TRGMR register
TRGIOA0 to TRGIOA2, TRGIOB0 to TRGIOB2: Bits in TRGIOR register
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(4) Event Input from Event Link Controller (ELC)
Timer RG performs input capture operation B by event input from the ELC. The TRGIMFB bit in the TRGSR register
is set to 1 at this time.
To use this function, select the input capture function of timer mode/phase counting mode, and set the TRGELCICE
bit in the TRGMR register to 1. This function is disabled in other modes (the output compare function of timer
mode/phase counting mode and PWM mode).
Setting procedure
<1> Set timer RG as the ELC event link destination.
<2> Set the TRGELCICE bit in the TRGMR register to 1.
(5) Event Output to Event Link Controller (ELC)
Table 9-7 lists the ELC Event Output according to TRGIMFA Bit. Table 9-8 lists the ELC Event Output according to
TRGIMFB Bit.
Table 9-7. ELC Event Output according to TRGIMFA Bit
Mode, Function
ELC Source
Input capture function
Detection of TRGIOA edge set by bits TRGIOA0 and
(TRGPWM = 0, TRGIOA2 = 1)
TRGIOA1
Output compare function
Compare match between registers TRG and TRGGRA
(TRGPWM = 0, TRGIOA2 = 0)
PWM mode (TRGPWM = 1)
Compare match between registers TRG and TRGGRA
Remark TRGPWM: Bit in TRGMR register
TRGIOA0, TRGIOA1, TRGIOA2: Bits in TRGIOR register
Table 9-8. ELC Event Output according to TRGIMFB Bit
Mode, Function
ELC Source
Input capture function
Detection of TRGIOB edge set by bits TRGIOB0 and
(TRGPWM = 0, TRGIOB2 = 1)
TRGIOB1
Output compare function
Compare match between registers TRG and TRGGRB
(TRGPWM = 0, TRGIOB2 = 0)
PWM mode (TRGPWM = 1)
Compare match between registers TRG and TRGGRB
Remark TRGPWM: Bit in TRGMR register
TRGIOB0, TRGIOB1, TRGIOB2: Bits in TRGIOR register
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9.3.2 Timer Mode (Input Capture Function)
The value of the TRG register can be transferred to registers TRGGRA and TRGGRB upon detecting the input edge of
the input capture/output compare pins (TRGIOA and TRGIOB). The detection edge can be selected from the rising
edge/falling edge/both edges.
The input capture function can be used for measuring pulse widths and periods.
Table 9-9 lists the Input Capture Function Specifications.
Table 9-9. Input Capture Function Specifications
Item
Count sources
Specification
fCLK, fCLK/2, fCLK/4, fCLK/8, fCLK/32
External signal input to the TRGCLKA or TRGCLKB pin (active edge selectable by a
program)
Count operation
Increment
Count period
When bits TRGCCLR1 to TRGCCLR0 in the TRGCR register are set to 00B (freerunning operation)
1/fk × 65,536 fk: Frequency of count source
Count start condition
1 (count starts) is written to the TRGSTART bit in the TRGMR register.
Count stop condition
0 (count stops) is written to the TRGSTART bit in the TRGMR register.
Interrupt request generation timing
• Input capture (active edge of TRGIOA and TRGIOB pin input)
TRGIOA, TRGIOB pin function
I/O port or input-capture input (selectable for each pin)
TRGCLKA, TRGCLKB pin function
I/O port or external clock input
Read from timer
The count value can be read by reading the TRG register.
Write to timer
The TRG register can be written to.
Selectable functions
• Input-capture input pin selection
• TRG register overflow
Either one or both of pins TRGIOA and TRGIOB
• Active edge selection for input-capture input
Rising edge, falling edge, or both rising and falling edges
• Timing for setting the TRG register to 0000H
At overflow or input capture
• Buffer operation (see 9. 3. 1. (2) Buffer Operation)
• Digital filter (see 9. 3. 1. (3) Digital Filter)
• Input capture operation by event input signal (input capture) from event link controller
(ELC)
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(1) Procedure Example for Setting Input Capture Operation
Figure 9-16 shows a Procedure Example for Setting Input Capture Operation.
Figure 9-16. Procedure Example for Setting Input Capture Operation
Input selection
(1) Use the TRGIOR register to set TRGGRj (j = A or B) as an input
capture register and select the input edge of input capture signals
from the following three: the rising edge/falling edge/both edges.
Select input-capture input
(1)
Count operation starts
(2)
(2) Set the TRGSTART bit in the TRGMR register to 1 to start the
count operation of the TRG register.
Input capture operation
(2) Input Capture Signal Timing
For input-capture input, the rising edge/falling edge/both edges can be selected by setting the TRGIOR register.
Figure 9-17 shows the Input-Capture Input Signal Timing.
The pulse width of input-capture input signals should be 1.5fCLK or more for a single edge and 2.5fCLK or more for
both edges.
Figure 9-17. Input-Capture Input Signal Timing
fCLK
TRGIOj input
Input capture signal
(internal signal)
N
TRG register
N
TRGGRj register
j = A or B
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(3) Operation Example
Figure 9-18 shows an Operation Example of Input Capture.
This example applies when both the rising/falling edges are selected as the input-capture input edge of the
TRGIOA pin and the falling edge is selected as the input-capture input edge of the TRGIOB pin, and the TRG
register is set to be cleared by the input capture to the TRGGRB register.
(a) Use the TRGIOR register to set registers TRGGRA and TRGGRB as input capture registers and select the
input edge of input capture signals from the following three: the rising edge/falling edge/both edges.
(b) Set the TRGSTART bit in TRGMR to 1 and start the count operation of the TRG register.
Figure 9-18. Operation Example of Input Capture
TRG register value
TRGIOB
0180H
0160H
0005H
0000H
Time
TRGIOB input
TRGIOA input
TRGGRA register
0005H
TRGGRB register
0160H
0180H
By setting bits TRGCCLR0 and TRGCCLR1 in the TRGCR register, the count can be cleared by input capture A or
B.
Figure 9-18 shows an operation example with bits TRGCCLR1 and TRGCCLR0 set to 10B. If the input capture
operation has been set to clear the count during operation and is performed when the timer count value is FFFFH,
depending on the timing between the count source and input capture operation interrupt flags bits TRGIMFA,
TRGIMFB, and TRGOVF may be set to 1 simultaneously.
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9.3.3 Timer Mode (Output Compare Function)
This mode (output compare function) detects when the contents of the TRG register and the TRGGRA or TRGGRB
register match (compare match). When a match occurs, a signal is output from the TRGIOA or TRGIOB pin at a given
level.
Table 9-10 lists the Output Compare Function Specifications.
Table 9-10. Output Compare Function Specifications
Item
Count sources
Specification
fCLK, fCLK/2, fCLK/4, fCLK/8, fCLK/32
External signal input to the TRGCLKj pin (active edge selectable by a program)
Count operation
Increment
Count periods
• When bits TRGCCLR1 and TRGCCLR0 in the TRGCR register are set to 00B (freerunning operation)
1/fk × 65,536 fk: Frequency of count source
• When bits TRGCCLR1 and TRGCCLR0 in the TRGCR register are set to 01B or 10B
(TRG is set to 0000H by compare match with TRGGRj)
1/fk × (n + 1)
n: Value set in the TRGGRj register
Waveform output timing
Compare match (contents of registers TRG and TRGGRj match)
Count start condition
1 (count starts) is written to the TRGSTART bit in the TRGMR register.
Count stop condition
0 (count stops) is written to the TRGSTART bit in the TRGMR register.
Interrupt request generation timing
• Compare match (contents of registers TRG and TRGGRj match)
• TRG register overflow
TRGIOA, TRGIOB pin function
I/O port or output-compare output (selectable for each pin)
TRGCLKA, TRGCLKB pin function
I/O port or external clock input
Read from timer
The count value can be read by reading the TRG register.
Write to timer
The TRG register can be written to.
Selectable functions
• Output-compare output pin selection
Either one or both of pins TRGIOA and TRGIOB
• Output level selection at compare match
Low output, high output, or inverted output level
• Timing for setting the TRG register to 0000H
Overflow or compare match with the TRGGRj register
• Buffer operation (see 9. 3. 1. (2) Buffer Operation)
Remark
j = A or B
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(1) Procedure Example for Setting Waveform Output by Compare Match
Figure 9-19 shows a Procedure Example for Setting Waveform Output by Compare Match.
Figure 9-19. Procedure Example for Setting Waveform Output by Compare Match
Output selection
Select waveform output mode
(1)
Set the output timing
(2)
(1) Use the TRGIOR register to select the compare match output
from the following three: Low output/high output/toggle output.
When waveform output mode is set, the ports function as
compare match output pins (TRGIOA and TRGIOB).
The output levels of these pins depend on the settings of bits
TRGIOA0 and TRGIOA1 and bits TRGIOB0 and TRGIOB1 in the
TRGIOR register until the first compare match occurs.
(2) Set the timing for generating a compare match into registers
TRGGRA and TRGGRB.
Count operation starts
(3)
(3) Set the TRGSTART bit in the TRGMR register to 1 to start the
count operation of the TRG register.
Waveform output
(2) Output-Compare Output Timing
A compare match signal is generated at the last state when the TRG register and the TRGGRA or TRGGRB
register match (at the timing for updating the count value that the TRG register matches). When the compare match
signal is generated, the output value set by the TRGIOR register is output to the output-compare output pin
(TRGIOA or TRGIOB). After the TRG register and the TRGGRA or TRGGRB register match, no compare match
signal is generated until the TRG input clock is generated.
Figure 9-20 shows the Output-Compare Output Timing.
Figure 9-20. Output-Compare Output Timing
fCLK
TRG input clock
TRG register
N
N+1
TRGGRA register
N
TRGGRB register
N+1
N+2
Compare match A signal
(internal signal)
Compare match B signal
(internal signal)
TRGIOA output
TRGIOB output
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(3) Operation Example
Figure 9-21 shows an Operation Example of Low Output and High Output.
This example applies when the TRG register is set for free-running operation, and low output is set at compare
match A, and high output is set at compare match B. When the set level and the pin level match, the pin level does
not change.
Figure 9-21. Operation Example of Low Output and High Output
TRG register value
FFFFH
TRGGRB register
TRGGRA register
0000H
TRGIOB output
Time
No change
No change
TRGIOA output
No change
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High output
Low output
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Figure 9-22 shows the Operation Example of Toggle Output. This example applies when the TRG register is set for
period counting operation (counter clear at compare match B), and toggle output is set at both compare match A
and B.
(a) Use the TRGIOR register to select the compare match output from the following three: Low output/high
output/toggle output. When waveform output mode is set, the ports function as compare match output pins
(TRGIOA and TRGIOB).
(b) Set the timing for generating a compare match into registers TRGGRA and TRGGRB.
(c) Set the TRGSTART bit in the TRGMR register to 1 to start the count operation of the TRG register.
The compare match output pins (TRGIOA and TRGIOB) are not initialized by setting the TRGSTART bit to 0 during
operation. To return to initial values, write to the TRGIOR register to initialize the output. (The output is only
initialized when bits TRGIOA0, TRGIOA1, TRGIOB0, and TRGIOB1 in the TRGIOR register are set to low output or
high output.) By setting bits TRGCCLR0 and TRGCCLR1 in the TRGCR register, the timer RG counter value is
reset by an input capture/compare match (match with the TRGGRA or TRGGRB register). If the expected compare
value is FFFFH at this time, FFFFH changes to 0000H, same as the overflow operation, and the TRGOVF bit is set
to 1.
This operation is the same for modes where the output compare function is used on the timer RG counter value
and expected compare value.
Figure 9-22. Operation Example of Toggle Output
TRG register value
Counter cleared by compare match with TRGGRB register
TRGGRB register
TRGGRA register
0000H
TRGIOB output
Time
Toggle output
TRGIOA output
Toggle output
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9.3.4 PWM Mode
In PWM mode, registers TRGGRA and TRGGRB are used as a pair and a PWM waveform is output from the TRGIOA
output pin. The output setting by the TRGIOR register is invalid for the pins set to PWM mode. Set the high output timing
for a PWM waveform into the TRGGRA register and the low output timing for a PWM waveform into the TRGGRB register.
By setting the compare match with either the TRGGRA or TRGGRB register as the counter clear source for the TRG
register, a PWM waveform with duty cycle 0% to 100% can be output from the TRGIOA pin.
Table 9-11 lists the PWM Mode Specifications and table 9-12 lists the Combination of PWM Output Pins and Registers.
When the setting values in registers TRGGRA and TRGGRB are the same, the output value does not change even if a
compare match occurs.
Table 9-11. PWM Mode Specifications
Item
Specification
Count sources
fCLK, fCLK/2, fCLK/4, fCLK/8, fCLK/32
External signal input to the TRGCLKj pin (active edge selectable by a program)
Count operation
Increment
PWM waveform
• The high output timing of a PWM waveform is set into the TRGGRA register.
• The low output timing of a PWM waveform is set into the TRGGRB register.
Count start condition
1 (count starts) is written to the TRGSTART bit in the TRGMR register.
Count stop condition
0 (count stops) is written to the TRGSTART bit in the TRGMR register.
Interrupt request generation timing
• Compare match (contents of registers TRG and TRGGRj match)
• TRG register overflow
TRGIOA pin function
PWM output
TRGIOB pin function
I/O port
TRGCLKA, TRGCLKB pin function
I/O port or external clock input
Read from timer
The count value can be read by reading the TRG register.
Write to timer
The TRG register can be written to.
Selectable functions
• Timing for setting the TRG register to 0000H
Overflow or compare match with the TRGGRj register
• Buffer operation (see 9. 3. 1. (2) Buffer Operation)
Remark
j = A or B
Table 9-12. Combination of PWM Output Pins and Registers
Output Pin
High Output
Low Output
TRGIOA
TRGGRA
TRGGRB
TRGIOB
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(1) Procedure Example for Setting PWM Mode
Figure 9-23 shows a Procedure Example for Setting PWM Mode.
Figure 9-23. Procedure Example for Setting PWM Mode
PWM mode
Select the counter clock
(1)
Select the counter clear
source
(2)
Set TRGGRA
(3)
Set TRGGRB
(4)
Set PWM mode
(5)
Count operation starts
(6)
PWM mode
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(1) Use bits TRGTCK0 to TRGTCK2 in the TRGCR register to select
the count source. When an external clock is selected, use bits
TRGCKEG0 and TRGCKEG1 in the TRGCR register to select the
edge of the clock.
(2) Use bits TRGCCLR0 and TRGCCLR1 in the TRGCR register to
select the counter clear source.
(3) Set the high output timing for a PWM output waveform into the
TRGGRA register.
(4) Set the low output timing for a PWM output waveform into the
TRGGRB register.
(5) Use the TRGPWM bit in the TRGMR register to set PWM mode.
When PWM mode is set, registers TRGGRA and TRGGRB are set
as the output compare registers for setting the high output/low
output timing for a PWM output waveform, regardless of the
content of the TRGIOR register.
When the PM00 bit in the PM0 register is 0 and the P00 bit in the
P0 register is 0, the TRGIOA pin automatically functions as a PWM
output pin. However, the TRGIOB pin functions as an I/O port.
(6) Set the TRGSTART bit in the TRGMR register to 1 to start the
count operation of the TRG register.
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(2) Operation Example
Figure 9-24 shows an Operation Example (1) in PWM Mode.
When the PM00 bit in the PM0 register is 0 and the P00 bit in the P0 register is 0, the TRGIOA pin automatically
functions as an output pin, and high output is set at the compare match with the TRGGRA register and low output
is set at the compare match with the TRGGRB register. However, regardless of the setting of the TRGIOR register,
the TRGIOB pin functions as an I/O port.
This example applies when the compare match with the TRGGRA or TRGGRB register is set as the counter clear
source for the TRG register. The initial state of the TRGIOA pin depends only on the counter clear sources. This
correspondence is shown in Table 9-13.
This initialization is performed when the TRGSTART bit in the TRGMR register is 0 (count stops).
Table 9-13. Correspondence between Initial State of TRGIOA Pin and Counter Clear Sources
Counter Clear Source
Initial State of TRGIOA Pin
Compare match with TRGGRA register
High
Compare match with TRGGRB register
Low
When bits TRGCCLR1 and TRGCCLR0 in the TRGCR register are set to 00B (clear disabled), the initial state of
the TRGIOA pin becomes high.
Figure 9-24. Operation Example (1) in PWM Mode
TRG register value
Counter cleared by compare match A
TRGGRA register
TRGGRB register
0000H
Time
TRGIOA output
(a) Counter clear by the compare match with the TRGGRA register
TRG register value
Counter cleared by compare match B
TRGGRB register
TRGGRA register
0000H
Time
TRGIOA output
(b) Counter clear by the compare match with the TRGGRB register
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Figure 9-25 shows an example for outputting a PWM waveform with duty cycle 0% and duty cycle 100%.
A PWM waveform is set to duty cycle 0% when the compare match with the TRGGRB register is set as the counter
clear source with the following:
• Value set in TRGGRA register > Value set in TRGGRB register
A PWM waveform is set to duty cycle 100% when the compare match with TRGGRA register is set as the counter
clear source with the following:
• Value set in TRGGRB register > Value set in TRGGRA register
Output value is unchanged even if a compare match is generated with the following:
• Value set in TRGGRA register = Value set in TRGGRB register
Figure 9-25. Operation Example (2) in PWM Mode
TRG register value
Counter cleared by compare match B
TRGGRB register
TRGGRA register
0000H
Time
TRGIOA output
TRGGRA register setting value
written
TRGGRA register setting value
written
(a) Duty cycle 0%
TRG register value
Counter cleared by compare match A
TRGGRA register
TRGGRB register
Time
0000H
TRGIOA output
TRGGRB register setting value
written
TRGGRB register setting value
written
(b) Duty cycle 100%
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9.3.5 Phase Counting Mode
In phase counting mode, a phase difference between external input signals from two pins TRGCLKA and TRGCLKB is
detected and the TRG register is incremented/decremented.
When phase counting mode is set when bits PM00 and PM01 in the PM0 register are 1, regardless of the settings of
bits TRGTCK0 to TRGTCK2 and bits TRGCKEG0 and TRGCKEG1 in the TRGCR register, pins TRGCLKA and
TRGCLKB automatically function as external clock input pins and the TRG register is incremented/decremented by bits
CNTEN0 to CNTEN7 in the TRGCNTC register. However, bits TRGCCLR0 and TRGCCLR1 in the TRGCR register and
registers TRGIOR, TRGIER, TRGSR, TRGGRA, and TRGGRB are enabled. This allows the input capture/output compare
functions, PWM output function, and interrupt sources to be used.
The TRG register operates counting at both the rising/falling edges of pins TRGCLKA and TRGCLKB by bits CNTEN0
to CNTEN7.
Table 9-14 lists the Phase Counting Mode Specifications and table 9-15 lists the Increment/Decrement Conditions for
TRG Register.
Table 9-14. Phase Counting Mode Specifications
Item
Specification
Count source
External signal input to the TRGCLKj pin
Count operations
Increment/decrement
Count start condition
1 (count starts) is written to the TRGSTART bit in the TRGMR register.
Count stop condition
0 (count stops) is written to the TRGSTART bit in the TRGMR register.
Interrupt request generation timing
• Input capture (active edge of TRGIOj input)
• Compare match (contents of registers TRG and TRGGRj match)
• TRG register overflow
• TRG register underflow
TRGIOA pin function
I/O port, input-capture input, output-compare output, or PWM output
TRGIOB pin function
I/O port, input-capture input, or output-compare output
TRGCLKA, TRGCLKB pin function
External clock input
Read from timer
The count value can be read by reading the TRG register.
Write to timer
The TRG register can be written to.
Selectable functions
• Selection of counter increment/decrement conditions
Selectable by bits CNTEN0 to CNTEN7 in the TRGCNTC register.
• Input capture/output compare functions and PWM function can be used.
Remark j = A or B
Table 9-15. Increment/Decrement Conditions for TRG Register
TRGCLKB pin
TRGCLKA pin
Low
High
Low
High
Low
Low
High
High
Bits CNTEN7 to
CNTEN0 in
CNTEN7
CNTEN6
CNTEN5
CNTEN4
CNTEN3
CNTEN2
CNTEN1
CNTEN0
+1
+1
+1
+1
-1
-1
-1
-1
TRGCNTC register
Count direction
Note
Note The count direction when each bit in the TRGCNTC register is 1 (decrement or increment) is shown. When a bit
is 0 (disabled), count is not performed.
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(1) Procedure Example for Setting Phase Counting Mode
Figure 9-26 shows a Procedure Example for Setting Phase Counting Mode.
Figure 9-26. Procedure Example for Setting Phase Counting Mode
Phase counting mode
(1) Set the TRGMDF bit in the TRGMR register to 1 to select phase
counting mode.
Select phase counting mode
(1)
Count operation starts
(2)
(2) Set the TRGSTART bit in the TRGMR register to 1 to start count
operation of the TRG register.
Phase counting mode
(2) Operation Example
Figure 9-27 to figure 9-30 show Operation Examples in Phase Counting Mode.
In phase counting mode, the TRG register is incremented/decremented at both the rising(
)/falling(
) edges of
pins TRGCLKA and TRGCLKB by bits CNTEN0 to CNTEN7 in the TRGCNTC register.
Figure 9-27. Operation Example 1 in Phase Counting Mode
• When the TRGCNTC register value is FFH
TRGCLKB input
TRGCLKA input
TRG register value
Increment
Decrement
Time
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Figure 9-28. Operation Example 2 in Phase Counting Mode
• When the TRGCNTC register value is 24H
TRGCLKB input
TRGCLKA input
TRG register value
Increment
Decrement
Time
Figure 9-29. Operation Example 3 in Phase Counting Mode
• When the TRGCNTC register value is 28H
TRGCLKB input
TRGCLKA input
TRG register value
Increment
Decrement
Time
Figure 9-30. Operation Example 4 in Phase Counting Mode
• When the TRGCNTC register value is 5AH
TRGCLKB input
TRGCLKA input
TRG register value
Increment
Decrement
Time
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9.4 Notes on Timer RG
9.4.1 Phase Difference, Overlap, and Pulse Width in Phase Counting Mode
The phase difference and overlap between external input signals from pins TRGCLKA and TRGCLKB should be 1.5fCLK
or more, respectively. The pulse width should be 2.5fCLK or more.
Figure 9-31 shows the Phase Difference, Overlap, and Pulse Width in Phase Counting Mode.
Figure 9-31. Phase Difference, Overlap, and Pulse Width in Phase Counting Mode
Phase
difference
Phase
difference
Pulse width
Pulse width
TRGCLKA input
TRGCLKB input
Overlap
Overlap
Phase difference and overlap: 1.5 fCLK or more
Pulse width: 2.5 fCLK or more
9.4.2 Mode Switching
• When switching modes during operation, set the TRGSTART bit in the TRGMR register to 0 (count stops) before
switching.
• After switching modes, set the TRGIF bit to 0 before starting operation.
Refer to CHAPTER 21 INTERRUPT FUNCTIONS for details.
9.4.3 Count Source Switching
• Stop the count before switching the count source Note.
Changing procedure
(1) Set the TRGSTART bit in the TRGMR register to 0 (count stops).
(2) Change bits TRGTCK0 to TRGTCK2 in the TRGCR register.
<R>
Note The registers and bits that cannot be rewritten during count operation are as follows:
• All bits except TRGSTART in the TRGMR register
• The TRGCNTC register
• The TRGCR register
• The TRGIOR register
9.4.4 Procedure for Setting Pins TRGIOA and TRGIOB
To output from pins TRGIOA and TRGIOB, use the following setting procedure:
Changing procedure
(1) Set the mode and the initial value/output enabled (in order to make the initial value and enable settings using
the same SFRs).
(2) Set the port register bits corresponding to pins TRGIOA and TRGIOB to 0.
(3) Set the port mode register bits corresponding to pins TRGIOA and TRGIOB to output mode (output is started
from pins TRGIOA and TRGIOB).
(4) Start the count (TRGSTART in TRGMR register = 1).
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To change the port mode register bits corresponding to pins TRGIOA and TRGIOB from output mode to input mode,
use the following setting procedure:
(1) Set the port mode register bits corresponding to pins TRGIOA and TRGIOB to input mode (input is started
from pins TRGIOA and TRGIOB).
(2) Set to the input capture function.
(3) Start the count (TRGSTART in TRGMR register = 1).
When switching pins TRGIOA and TRGIOB from output mode to input mode, input capture operation may be
performed depending on the states of these pins. When the digital filter is not used, edge detection is performed after two
or more cycles of the CPU clock have elapsed. When the digital filter is used, edge detection is performed after five or
more cycles of the sampling clock have elapsed.
9.4.5 External Clock TRGCLKA, TRGCLKB
The pulse width of an external clock input to the TRGCLKj pin (j = A or B) should be set to three cycles or more of the
timer RG operating clock (fCLK).
9.4.6 SFR Read/Write Access
When setting timer RG, set the TRGEN bit in the PER1 register to 1 first. If the TRGEN bit is 0, writes to the timer RG
control registers are ignored and all the read values are the initial values (except for the port registers and the port mode
registers).
(1) TRGMR Register
Use the following setting procedure when switching the digital filter clock.
(a) With the TRGSTART bit set to 0 (count stops), set bits TRGDFA and TRGDFB (digital filter function select
bits of pins TRGIOA and TRGIOB) in the TRGMR register, and bits TRGDFCK0 and TRGDFCK1 (clock
select bits used by digital filter function) in the TRGMR register.
(b) Set the TRGSTART bit to 1.
However, when the digital filter is not set and TRGDFCK1 and TRGDFCK0 = 00B remain unchanged after a reset,
the setting can be performed in a single step.
Besides external input pins (TRGIOA and TRGIOB), event input from the event link controller (ELC) can also be
selected as an operating source for input capture. To use this function, set the TRGELCICE bit in the TRGMR
register to 1, and set the input capture function (the rising edge as the active edge for input capture (TRGIOB2 to
TRGIOB0 = 100B)).
This function is disabled in PWM mode and the timer mode output compare function (TRGPWM = 1 and TRGIOB2
= 0).
(2) TRG Register
•
Writing to the TRGMR register has priority over count reset operations generated by timer RG operating
conditions.
<R>
9.4.7 Input Capture Operation when Count is Stopped
In input capture mode, an input capture interrupt request for the active edge of the TRGIOj input is also generated
when the TRGSTART bit in the TRGMR register is 0 (count stops) if the edge selected by bits TRGIOj0 and TRGIOj1 in
the TRGIOR register is input to the TRGIOj pin (j = A or B).
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CHAPTER 10 REAL-TIME CLOCK
CHAPTER 10 REAL-TIME CLOCK
10.1 Functions of Real-time Clock
The real-time clock has the following features.
• Having counters of year, month, week, day, hour, minute, and second, and can count up to 99 years.
• Constant-period interrupt function (period: 0.5 seconds, 1 second, 1 minute, 1 hour, 1 day, 1 month)
• Alarm interrupt function (alarm: week, hour, minute)
• Pin output function of 1 Hz (40, 44, 48, 52, 64, 80, and 100-pin products only)
<R>
Caution The count of year, month, week, day, hour, minutes and second can only be performed when a
subsystem clock (fSUB = 32.768 kHz) is selected as the operation clock of the real-time clock. When
the low-speed oscillation clock (fIL) is selected, only the constant-period interrupt function is available.
The 30-, 32-, and 36-pin products have the constant-period interrupt function only, because these
products have no subsystem clock.
However, the constant-period interrupt interval when fIL is selected will be calculated with the
constant-period (the value selected with RTCC0 register) × fSUB/fIL.
10.2 Configuration of Real-time Clock
The real-time clock includes the following hardware.
Table 10-1. Configuration of Real-time Clock
Item
Configuration
Counter
Sub-count register
Control registers
Peripheral enable register 0 (PER0)
Operation speed mode control register (OSMC)
Real-time clock control register 0 (RTCC0)
Real-time clock control register 1 (RTCC1)
Second count register (SEC)
Minute count register (MIN)
Hour count register (HOUR)
Day count register (DAY)
Week count register (WEEK)
Month count register (MONTH)
Year count register (YEAR)
Watch error correction register (SUBCUD)
Alarm minute register (ALARMWM)
Alarm hour register (ALARMWH)
Alarm week register (ALARMWW)
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Figure 10-1. Block Diagram of Real-time Clock
Real-time clock control register 1
WALE
WALIE WAFG
RIFG
Real-time clock control register 0
RTCE RCLOE1 AMPM
RWST RWAIT
Alarm week
register
(ALARMWW)
(7-bit)
Alarm hour
register
(ALARMWH)
(6-bit)
CT2
CT1
CT0
WUTMM
CK0
Operation speed mode
control register (OSMC)
RTC1HZ
Alarm minute
register
(ALARMWM)
(7-bit)
INTRTC
CT0 to CT2
Selector
RIFG
AMPM
Month count
register
(MONTH)
(5-bit)
Week count
register
(WEEK)
(3-bit)
Day count
register
(DAY)
(6-bit)
1 hour
Hour count
register
(HOUR)
(6-bit)
1 minute
Minute count
register
(MIN)
(7-bit)
RWST RWAIT
0.5
seconds
1 seconds
Second
Sub-count
count
register
register
Wait control
(SEC)
(16-bit)
(7-bit)
Count enable/
disable circuit
Buffer
Buffer
Buffer
Buffer
Buffer
Buffer
Buffer
RTCE
fRTC
Watch error
correction
register
(SUBCUD)
(8-bit)
Selector
<R>
Year count
register
(YEAR)
(8-bit)
1 day
1 month
1 year
fSUB
fIL
WUTMMCK0
Internal bus
<R>
Caution
The count of year, month, week, day, hour, minutes and second can only be performed when a
subsystem clock (fSUB = 32.768 kHz) is selected as the operation clock of the real-time clock.
When the low-speed oscillation clock (fIL) is selected, only the constant-period interrupt
function is available. The 30-, 32-, and 36-pin products have the constant-period interrupt
function only, because these products have no subsystem clock.
However, the constant-period interrupt interval when fIL is selected will be calculated with the
constant-period (the value selected with RTCC0 register) × fSUB/fIL.
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10.3 Registers Controlling Real-time Clock
The real-time clock is controlled by the following registers.
• Peripheral enable register 0 (PER0)
• Operation speed mode control register (OSMC)
• Real-time clock control register 0 (RTCC0)
• Real-time clock control register 1 (RTCC1)
• Second count register (SEC)
• Minute count register (MIN)
• Hour count register (HOUR)
• Day count register (DAY)
• Week count register (WEEK)
• Month count register (MONTH)
• Year count register (YEAR)
• Watch error correction register (SUBCUD)
• Alarm minute register (ALARMWM)
• Alarm hour register (ALARMWH)
• Alarm week register (ALARMWW)
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(1) Peripheral enable register 0 (PER0)
This register is used to enable or disable supplying the clock to the peripheral hardware. Clock supply to a
hardware macro that is not used is stopped in order to reduce the power consumption and noise.
When the real-time clock is used, be sure to set bit 7 (RTCEN) of this register to 1.
The PER0 register can be set by a 1-bit or 8-bit memory manipulation instruction.
Reset signal generation clears this register to 00H.
Figure 10-2. Format of Peripheral Enable Register 0 (PER0)
Address: F00F0H
Symbol
PER0
After reset: 00H
<7>
RTCEN
IICA1EN
<5>
Note 1
ADCEN
<4>
IICA0EN
<3>
SAU1EN
<2>
SAU0EN
<1>
TAU1EN
<0>
Note 1
Control of real-time clock (RTC) and 12-bit interval timer input clock supply
RTCEN
0
R/W
<6>
TAU0EN
Note 2
Stops input clock supply.
• SFR used by the real-time clock (RTC) and 12-bit interval timer cannot be written.
• The real-time clock (RTC) and 12-bit interval timer are in the reset status.
1
Enables input clock supply.
• SFR used by the real-time clock (RTC) and 12-bit interval timer can be read/written.
Notes 1. 80 and 100-pin products only.
2. The input clock that can be controlled by the RTCEN bit is used when the register that is used
by the real-time clock (RTC) and 12-bit interval timer are accessed from the CPU. The RTCEN
bit cannot control supply of the operating clock (fSUB) to RTC and 12-bit interval timer.
Cautions 1. When using the real-time clock, first set the RTCEN bit to 1, while oscillation of the
input clock (fRTC) is stable. If RTCEN = 0, writing to a control register of the real-time
clock or 12-bit interval timer is ignored, and, even if the register is read, only the
default value is read.
2. Clock supply to peripheral functions other than the real-time clock and 12-bit interval
timer can be stopped in STOP mode or HALT mode when the subsystem clock is
used, by setting the RTCLPC bit of the operation speed mode control register
(OSMC) to 1. In this case, set the RTCEN bit of the PER0 register to 1 and the other
bits (bits 0 to 6) to 0.
3. Be sure to clear the following bits to 0.
30, 32, 36, 40, 44, 48, 52, 64-pin products: bits 1, 6
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(2) Operation speed mode control register (OSMC)
The WUTMMCK0 bit can be used to select the real-time clock operation clock (fRTC).
In addition, by stopping clock functions that are unnecessary, the RTCLPC bit can be used to reduce power
consumption. For details about setting the RTCLPC bit, see CHAPTER 5 CLOCK GENERATOR.
The OSMC register can be set by an 8-bit memory manipulation instruction.
Reset signal generation clears this register to 00H.
Figure 10-3. Format of Operation Speed Mode Control Register (OSMC)
<R>
Address: F00F3H
After reset: 00H
R/W
Symbol
7
6
5
4
3
2
1
0
OSMC
RTCLPC
0
0
WUTMMCK0
0
0
0
0
Selection of operation clock (fRTC) for real-time clock, 12-bit interval timer,
WUTMMCK0
and timer RJ operation clock
0
Subsystem clock (fSUB)
• The subsystem clock is selected as the operation clock for the real-time clock and the 12bit interval timer.
• The low-speed on-chip oscillator cannot be selected as the count source for timer RJ.
1
Low-speed on-chip oscillator clock (fIL)
• The low-speed on-chip oscillator clock is selected as the operation clock for the real-time
clock and the 12-bit interval timer.
• Either the low-speed on-chip oscillator or the subsystem clock can be selected as the
count source for timer RJ.
Caution
The count of year, month, week, day, hour, minutes and second can only be performed
when a subsystem clock (fSUB = 32.768 kHz) is selected as the operation clock of the
real-time clock. When the low-speed oscillation clock (fIL) is selected, only the constantperiod interrupt function is available. The 30-, 32-, and 36-pin products have the
constant-period interrupt function only, because these products have no subsystem
clock.
However, the constant-period interrupt interval when fIL is selected will be calculated
with the constant-period (the value selected with RTCC0 register) × fSUB/fIL.
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(3) Real-time clock control register 0 (RTCC0)
The RTCC0 register is an 8-bit register that is used to start or stop the real-time clock operation, control the
RTC1HZ pin, and set a 12- or 24-hour system and the constant-period interrupt function.
The RTCC0 register can be set by a 1-bit or 8-bit memory manipulation instruction.
Reset signal generation clears this register to 00H.
Figure 10-4. Format of Real-time Clock Control Register 0 (RTCC0)
Address: FFF9DH
After reset: 00H
R/W
Symbol
<7>
6
<5>
4
3
2
1
0
RTCC0
RTCE
0
RCLOE1
0
AMPM
CT2
CT1
CT0
RTCE
Real-time clock operation control
0
Stops counter operation.
1
Starts counter operation.
RCLOE1
RTC1HZ pin output control
0
Disables output of the RTC1HZ pin (1 Hz).
1
Enables output of the RTC1HZ pin (1 Hz).
AMPM
Selection of 12-/24-hour system
0
12-hour system (a.m. and p.m. are displayed.)
1
24-hour system
• Rewrite the AMPM bit value after setting the RWAIT bit (bit 0 of real-time clock control register 1 (RTCC1)) to 1. If
the AMPM bit value is changed, the values of the hour count register (HOUR) change according to the specified
time system.
• Table 10-2 shows the displayed time digits that are displayed.
CT2
CT1
CT0
0
0
0
Does not use fixed-cycle interrupt function.
0
0
1
Once per 0.5 s (synchronized with second count up)
0
1
0
Once per 1 s (same time as second count up)
0
1
1
Once per 1 m (second 00 of every minute)
1
0
0
Once per 1 hour (minute 00 and second 00 of every hour)
1
0
1
Once per 1 day (hour 00, minute 00, and second 00 of every day)
1
×
Once per 1 month (Day 1, hour 00 a.m., minute 00, and second 00 of
1
Constant-period interrupt (INTRTC) selection
every month)
When changing the values of the CT2 to CT0 bits while the counter operates (RTCE = 1), rewrite the values of the
CT2 to CT0 bits after disabling interrupt servicing INTRTC by using the interrupt mask flag register. Furthermore,
after rewriting the values of the CT2 to CT0 bits, enable interrupt servicing after clearing the RIFG and RTCIF flags.
Cautions 1. Do not change the value of the RTCLOE1 bit when RTCE = 1.
<R>
2. Set the RCLOE1 bit to 0 in 30-, 32-, and 36-pin products.
Remark ×: don’t care
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(4) Real-time clock control register 1 (RTCC1)
The RTCC1 register is an 8-bit register that is used to control the alarm interrupt function and the wait time of the
counter.
The RTCC1 register can be set by a 1-bit or 8-bit memory manipulation instruction.
Reset signal generation clears this register to 00H.
Figure 10-5. Format of Real-time Clock Control Register 1 (RTCC1) (1/2)
Address: FFF9EH
After reset: 00H
R/W
Symbol
<7>
<6>
5
<4>
<3>
2
<1>
<0>
RTCC1
WALE
WALIE
0
WAFG
RIFG
0
RWST
RWAIT
WALE
Alarm operation control
0
Match operation is invalid.
1
Match operation is valid.
When setting a value to the WALE bit while the counter operates (RTCE = 1) and WALIE = 1, rewrite the WALE bit
after disabling interrupt servicing INTRTC by using the interrupt mask flag register. Furthermore, clear the WAFG
and RTCIF flags after rewriting the WALE bit. When setting each alarm register (WALIE flag of real-time clock
control register 1 (RTCC1), the alarm minute register (ALARMWM), the alarm hour register (ALARMWH), and the
alarm week register (ALARMWW)), set match operation to be invalid (“0”) for the WALE bit.
WALIE
Control of alarm interrupt (INTRTC) function operation
0
Does not generate interrupt on matching of alarm.
1
Generates interrupt on matching of alarm.
WAFG
Alarm detection status flag
0
Alarm mismatch
1
Detection of matching of alarm
This is a status flag that indicates detection of matching with the alarm. It is valid only when WALE = 1 and is set to
“1” one clock (fRTC) after matching of the alarm is detected. This flag is cleared when “0” is written to it. Writing “1”
to it is invalid.
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Figure 10-5. Format of Real-time Clock Control Register 1 (RTCC1) (2/2)
RIFG
Constant-period interrupt status flag
0
Fixed-cycle interrupt is not generated.
1
Fixed-cycle interrupt is generated.
This flag indicates the status of generation of the fixed-cycle interrupt. When the fixed-cycle interrupt is generated,
it is set to “1”.
This flag is cleared when “0” is written to it. Writing “1” to it is invalid.
RWST
Wait status flag of real-time clock
0
Counter is operating.
1
Mode to read or write counter value
This status flag indicates whether the setting of the RWAIT bit is valid.
Before reading or writing the counter value, confirm that the value of this flag is 1.
RWAIT
<R>
Wait control of real-time clock
0
Sets counter operation.
1
Stops SEC to YEAR counters. Mode to read or write counter value
This bit controls the operation of the counter.
Be sure to write “1” to it to read or write the counter value.
As the sub-count register is continuing to run, complete reading or writing within one second and turn back to 0.
When RWAIT = 1, it takes up to 1 clock (fRTC) until the counter value can be read or written (RWST = 1).
When the sub-count register overflowed while RWAIT = 1, it keeps the event of overflow until RWAIT = 0, then
counts up.
However, when it wrote a value to second count register, it will not keep the overflow event.
Caution If writing is performed to the RTCC1 register with a 1-bit manipulation instruction, the RIFG flag
and WAFG flag may be cleared. Therefore, to perform writing to the RTCC1 register, be sure to
use an 8-bit manipulation instruction.
To prevent the RIFG flag and WAFG flag from being
cleared during writing, disable writing by setting 1 to the corresponding bit. If the RIFG flag and
WAFG flag are not used and the value may be changed, the RTCC1 register may be written by
using a 1-bit manipulation instruction.
Remark Fixed-cycle interrupts and alarm match interrupts use the same interrupt source (INTRTC). When using
these two types of interrupts at the same time, which interrupt occurred can be judged by checking the
fixed-cycle interrupt status flag (RIFG) and the alarm detection status flag (WAFG) upon INTRTC
occurrence.
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(5) Second count register (SEC)
The SEC register is an 8-bit register that takes a value of 0 to 59 (decimal) and indicates the count value of
seconds.
It counts up when the sub-count register overflows.
When data is written to this register, it is written to a buffer and then to the counter up to 2 clocks (fRTC) later. Set a
decimal value of 00 to 59 to this register in BCD code.
The SEC register can be set by an 8-bit memory manipulation instruction.
Reset signal generation clears this register to 00H.
Figure 10-6. Format of Second Count Register (SEC)
Address: FFF92H
After reset: 00H
R/W
Symbol
7
6
5
4
3
2
1
0
SEC
0
SEC40
SEC20
SEC10
SEC8
SEC4
SEC2
SEC1
Caution When it reads or writes from/to the register while the counter is in operation (RTCE = 1), follow
the procedures described in the section 10.4.3 Reading/writing real-time clock.
(6) Minute count register (MIN)
The MIN register is an 8-bit register that takes a value of 0 to 59 (decimal) and indicates the count value of minutes.
It counts up when the second counter overflows.
When data is written to this register, it is written to a buffer and then to the counter up to 2 clocks (fRTC) later. Even
if the second count register overflows while this register is being written, this register ignores the overflow and is set
to the value written. Set a decimal value of 00 to 59 to this register in BCD code.
The MIN register can be set by an 8-bit memory manipulation instruction.
Reset signal generation clears this register to 00H.
Figure 10-7. Format of Minute Count Register (MIN)
Address: FFF93H
After reset: 00H
R/W
Symbol
7
6
5
4
3
2
1
0
MIN
0
MIN40
MIN20
MIN10
MIN8
MIN4
MIN2
MIN1
Caution When it reads or writes from/to the register while the counter is in operation (RTCE = 1), follow
the procedures described in the section 10.4.3 Reading/writing real-time clock.
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(7) Hour count register (HOUR)
The HOUR register is an 8-bit register that takes a value of 00 to 23 or 01 to 12 and 21 to 32 (decimal) and
indicates the count value of hours.
It counts up when the minute counter overflows.
When data is written to this register, it is written to a buffer and then to the counter up to 2 clocks (fRTC) later. Even
if the minute count register overflows while this register is being written, this register ignores the overflow and is set
to the value written. Specify a decimal value of 00 to 23, 01 to 12, or 21 to 32 by using BCD code according to the
time system specified using bit 3 (AMPM) of real-time clock control register 0 (RTCC0).
If the AMPM bit value is changed, the values of the HOUR register change according to the specified time system.
The HOUR register can be set by an 8-bit memory manipulation instruction.
Reset signal generation clears this register to 12H.
However, the value of this register is 00H if the AMPM bit (bit 3 of the RTCC0 register) is set to 1 after reset.
Figure 10-8. Format of Hour Count Register (HOUR)
Address: FFF94H
After reset: 12H
R/W
Symbol
7
6
5
4
3
2
1
0
HOUR
0
0
HOUR20
HOUR10
HOUR8
HOUR4
HOUR2
HOUR1
Cautions 1. Bit 5 (HOUR20) of the HOUR register indicates AM(0)/PM(1) if AMPM = 0 (if the 12-hour system
is selected).
2. When it reads or writes from/to the register while the counter is in operation (RTCE = 1),
follow the procedures described in the section 10.4.3 Reading/writing real-time clock.
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Table 10-2 shows the relationship between the setting value of the AMPM bit, the hour count register (HOUR) value,
and time.
Table 10-2. Displayed Time Digits
24-Hour Display (AMPM = 1)
12-Hour Display (AMPM = 1)
Time
HOUR Register
Time
HOUR Register
0
00H
12 a.m.
12H
1
01H
1 a.m.
01H
2
02H
2 a.m.
02H
3
03H
3 a.m.
03H
4
04H
4 a.m.
04H
5
05H
5 a.m.
05H
6
06H
6 a.m.
06H
7
07H
7 a.m.
07H
8
08H
8 a.m.
08H
9
09H
9 a.m.
09H
10
10H
10 a.m.
10H
11
11H
11 a.m.
11H
12
12H
12 p.m.
32H
13
13H
1 p.m.
21H
14
14H
2 p.m.
22H
15
15H
3 p.m.
23H
16
16H
4 p.m.
24H
17
17H
5 p.m.
25H
18
18H
6 p.m.
26H
19
19H
7 p.m.
27H
20
20H
8 p.m.
28H
21
21H
9 p.m.
29H
22
22H
10 p.m.
30H
23
23H
11 p.m.
31H
The HOUR register value is set to 12-hour display when the AMPM bit is “0” and to 24-hour display when the AMPM bit
is “1”.
In 12-hour display, the fifth bit of the HOUR register displays 0 for AM and 1 for PM.
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(8) Day count register (DAY)
The DAY register is an 8-bit register that takes a value of 1 to 31 (decimal) and indicates the count value of days.
It counts up when the hour counter overflows.
This counter counts as follows.
• 01 to 31 (January, March, May, July, August, October, December)
• 01 to 30 (April, June, September, November)
• 01 to 29 (February, leap year)
• 01 to 28 (February, normal year)
When data is written to this register, it is written to a buffer and then to the counter up to 2 clocks (fRTC) later. Even
if the hour count register overflows while this register is being written, this register ignores the overflow and is set to
the value written. Set a decimal value of 01 to 31 to this register in BCD code.
The DAY register can be set by an 8-bit memory manipulation instruction.
Reset signal generation clears this register to 01H.
Figure 10-9. Format of Day Count Register (DAY)
Address: FFF96H
After reset: 01H
R/W
Symbol
7
6
5
4
3
2
1
0
DAY
0
0
DAY20
DAY10
DAY8
DAY4
DAY2
DAY1
Caution When it reads or writes from/to the register while the counter is in operation (RTCE = 1), follow
the procedures described in the section 10.4.3 Reading/writing real-time clock.
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(9) Week count register (WEEK)
The WEEK register is an 8-bit register that takes a value of 0 to 6 (decimal) and indicates the count value of
weekdays.
It counts up in synchronization with the day counter.
When data is written to this register, it is written to a buffer and then to the counter up to 2 clocks (fRTC) later. Set a
decimal value of 00 to 06 to this register in BCD code.
The WEEK register can be set by an 8-bit memory manipulation instruction.
Reset signal generation clears this register to 00H.
Figure 10-10. Format of Week Count Register (WEEK)
Address: FFF95H
After reset: 00H
R/W
Symbol
7
6
5
4
3
2
1
0
WEEK
0
0
0
0
0
WEEK4
WEEK2
WEEK1
Cautions 1. The value corresponding to the month count register (MONTH) or the day count register (DAY)
is not stored in the week count register (WEEK) automatically. After reset release, set the
week count register as follow.
Day
WEEK
Sunday
00H
Monday
01H
Tuesday
02H
Wednesday
03H
Thursday
04H
Friday
05H
Saturday
06H
2. When it reads or writes from/to the register while the counter is in operation (RTCE = 1),
follow the procedures described in the section 10.4.3 Reading/writing real-time clock.
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(10) Month count register (MONTH)
The MONTH register is an 8-bit register that takes a value of 1 to 12 (decimal) and indicates the count value of
months.
It counts up when the day counter overflows.
When data is written to this register, it is written to a buffer and then to the counter up to 2 clocks (fRTC) later. Even
if the day count register overflows while this register is being written, this register ignores the overflow and is set to
the value written. Set a decimal value of 01 to 12 to this register in BCD code.
The MONTH register can be set by an 8-bit memory manipulation instruction.
Reset signal generation clears this register to 01H.
Figure 10-11. Format of Month Count Register (MONTH)
Address: FFF97H
After reset: 01H
R/W
Symbol
7
6
5
4
3
2
1
0
MONTH
0
0
0
MONTH10
MONTH8
MONTH4
MONTH2
MONTH1
Caution When it reads or writes from/to the register while the counter is in operation (RTCE = 1), follow
the procedures described in the section 10.4.3 Reading/writing real-time clock.
(11) Year count register (YEAR)
The YEAR register is an 8-bit register that takes a value of 0 to 99 (decimal) and indicates the count value of years.
It counts up when the month count register (MONTH) overflows.
Values 00, 04, 08, …, 92, and 96 indicate a leap year.
When data is written to this register, it is written to a buffer and then to the counter up to 2 clocks (fRTC) later. Even
if the MONTH register overflows while this register is being written, this register ignores the overflow and is set to
the value written. Set a decimal value of 00 to 99 to this register in BCD code.
The YEAR register can be set by an 8-bit memory manipulation instruction.
Reset signal generation clears this register to 00H.
Figure 10-12. Format of Year Count Register (YEAR)
Address: FFF98H
After reset: 00H
R/W
Symbol
7
6
5
4
3
2
1
0
YEAR
YEAR80
YEAR40
YEAR20
YEAR10
YEAR8
YEAR4
YEAR2
YEAR1
Caution When it reads or writes from/to the register while the counter is in operation (RTCE = 1), follow
the procedures described in the section 10.4.3 Reading/writing real-time clock.
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(12) Watch error correction register (SUBCUD)
This register is used to correct the watch with high accuracy when it is slow or fast by changing the value that
overflows from the sub-count register to the second count register (SEC) (reference value: 7FFFH).
The SUBCUD register can be set by an 8-bit memory manipulation instruction.
Reset signal generation clears this register to 00H.
Figure 10-13. Format of Watch Error Correction Register (SUBCUD)
Address: FFF99H
After reset: 00H
R/W
Symbol
7
6
5
4
3
2
1
0
SUBCUD
DEV
F6
F5
F4
F3
F2
F1
F0
DEV
Setting of watch error correction timing
0
Corrects watch error when the second digits are at 00, 20, or 40 (every 20 seconds).
1
Corrects watch error only when the second digits are at 00 (every 60 seconds).
Writing to the SUBCUD register at the following timing is prohibited.
• When DEV = 0 is set: For a period of SEC = 00H, 20H, 40H
• When DEV = 1 is set: For a period of SEC = 00H
F6
Setting of watch error correction value
0
Increases by {(F5, F4, F3, F2, F1, F0) – 1} × 2.
1
Decreases by {(/F5, /F4, /F3, /F2, /F1, /F0) + 1} × 2.
When (F6, F5, F4, F3, F2, F1, F0) = (*, 0, 0, 0, 0, 0, *), the watch error is not corrected. * is 0 or 1.
/F5 to /F0 are the inverted values of the corresponding bits (000011 when 111100).
Range of correction value: (when F6 = 0) 2, 4, 6, 8, … , 120, 122, 124
(when F6 = 1) –2, –4, –6, –8, … , –120, –122, –124
The range of value that can be corrected by using the watch error correction register (SUBCUD) is shown below.
DEV = 0 (correction every 20 seconds)
DEV = 1 (correction every 60 seconds)
Correctable range
–189.2 ppm to 189.2 ppm
–63.1 ppm to 63.1 ppm
Maximum excludes
± 1.53 ppm
± 0.51 ppm
± 3.05 ppm
± 1.02 ppm
quantization error
Minimum resolution
Remark If a correctable range is − 63.1 ppm or lower and 63.1 ppm or higher, set 0 to DEV.
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(13) Alarm minute register (ALARMWM)
This register is used to set minutes of alarm.
The ALARMWM register can be set by an 8-bit memory manipulation instruction.
Reset signal generation clears this register to 00H.
Caution
Set a decimal value of 00 to 59 to this register in BCD code. If a value outside the range is set,
the alarm is not detected.
Figure 10-14. Format of Alarm Minute Register (ALARMWM)
Address: FFF9AH
After reset: 00H
R/W
Symbol
7
6
5
4
3
2
1
0
ALARMWM
0
WM40
WM20
WM10
WM8
WM4
WM2
WM1
(14) Alarm hour register (ALARMWH)
This register is used to set hours of alarm.
The ALARMWH register can be set by an 8-bit memory manipulation instruction.
Reset signal generation clears this register to 12H.
However, the value of this register is 00H if the AMPM bit is set to 1 after reset.
Caution
Set a decimal value of 00 to 23, 01 to 12, or 21 to 32 to this register in BCD code. If a value
outside the range is set, the alarm is not detected.
Figure 10-15. Format of Alarm Hour Register (ALARMWH)
Address: FFF9BH
After reset: 12H
R/W
Symbol
7
6
5
4
3
2
1
0
ALARMWH
0
0
WH20
WH10
WH8
WH4
WH2
WH1
Caution Bit 5 (WH20) of the ALARMWH register indicates AM(0)/PM(1) if AMPM = 0 (if the 12-hour system
is selected).
(15) Alarm week register (ALARMWW)
This register is used to set date of alarm.
The ALARMWW register can be set by an 8-bit memory manipulation instruction.
Reset signal generation clears this register to 00H.
Figure 10-16. Format of Alarm Week Register (ALARMWW)
Address: FFF9CH
After reset: 00H
R/W
Symbol
7
6
5
4
3
2
1
0
ALARMWW
0
WW6
WW5
WW4
WW3
WW2
WW1
WW0
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Here is an example of setting the alarm.
Time of Alarm
Day
12-Hour Display
Sunday Monday Tuesday Wednesday Thursday Friday Saturday Hour
Hour
24-Hour Display
Hour
Hour
10
1
Minute Minute
10
1
10
1
Minute Minute
10
1
W
W
W
W
W
W
W
W
W
W
W
W
W
W
0
1
2
3
4
5
6
Every day, 0:00 a.m.
1
1
1
1
1
1
1
1
2
0
0
0
0
0
0
Every day, 1:30 a.m.
1
1
1
1
1
1
1
0
1
3
0
0
1
3
0
Every day, 11:59 a.m.
1
1
1
1
1
1
1
1
1
5
9
1
1
5
9
Monday through
0
1
1
1
1
1
0
3
2
0
0
1
2
0
0
Sunday, 1:30 p.m.
1
0
0
0
0
0
0
2
1
3
0
1
3
3
0
Monday, Wednesday,
0
1
0
1
0
1
0
3
1
5
9
2
3
5
9
Friday, 0:00 p.m.
Friday, 11:59 p.m.
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10.4 Real-time Clock Operation
10.4.1 Starting operation of real-time clock
Figure 10-17. Procedure for Starting Operation of Real-time Clock
Start
RTCEN = 1Note 1
RTCE = 0
Setting WUTMMCK0
<R>
Setting SEC
Setting AMPM, CT2 to CT0
Stops counter operation.
Sets fRTC
Selects 12-/24-hour system and interrupt (INTRTC).
Setting SEC
Sets second count register.
Setting MIN
Sets minute count register.
Setting HOUR
Sets hour count register.
Setting WEEK
Sets week count register.
Setting DAY
Setting MONTH
Setting YEAR
Setting SUBCUDNote 2
Sets day count register.
Sets month count register.
Sets year count register.
Sets watch error correction register.
Clearing IF flags of interrupt
Clears interrupt request flags (RTCIF).
Clearing MK flags of interrupt
Clears interrupt mask flags (RTCMK).
RTCE = 1Note 3
No
Supplies input clock.
Starts counter operation.
INTRTC = 1?
Yes
End
Notes 1. First set the RTCEN bit to 1, while oscillation of the input clock (fRTC) is stable.
2. Set up the SUBCUD register only if the watch error must be corrected. For details about how to
calculate the correction value, see 10.4.6 Example of watch error correction of real-time clock.
3. Confirm the procedure described in 10.4.2 Shifting to HALT/STOP mode after starting operation
when shifting to HALT/STOP mode without waiting for INTRTC = 1 after RTCE = 1.
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<R> 10.4.2 Shifting to HALT/STOP mode after starting operation
Perform one of the following processing when shifting to HALT/STOP mode immediately after setting the RTCE bit to 1.
However, after setting the RTCE bit to 1, this processing is not required when shifting to HALT/STOP mode after
INTRTC interrupt has occurred.
• Shifting to HALT/STOP mode when at least two input clocks (fRTC) have elapsed after setting the RTCE bit to 1 (see
Figure 10-18, Example 1).
• Checking by polling the RWST bit to become 1, after setting the RTCE bit to 1 and then setting the RWAIT bit to 1.
Afterward, setting the RWAIT bit to 0 and shifting to HALT/STOP mode after checking again by polling that the RWST
bit has become 0 (see Figure 10-18, Example 2).
Figure 10-18. Procedure for Shifting to HALT/STOP Mode After Setting RTCE bit to 1
Example 1
RTCE = 1
Example 2
RTCE = 1
Sets to counter operation
start
counters, reads the counter
value, write mode
fRTC clocks
execution
start
Sets to stop the SEC to YEAR
RWAIT = 1
Waiting at least for 2
HALT/STOP instruction
Sets to counter operation
Shifts to HALT/STOP
No
mode
RWST = 1 ?
Checks the counter wait status
Yes
RWAIT = 0
No
Sets the counter operation
RWST = 0 ?
Yes
HALT/STOP instruction
execution
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Shifts to HALT/STOP
mode
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10.4.3 Reading/writing real-time clock
Read or write the counter after setting 1 to RWAIT first.
<R>
Set RWAIT to 0 after completion of reading or writing the counter.
Figure 10-19. Procedure for Reading Real-time Clock
Start
No
RWAIT = 1
Stops SEC to YEAR counters.
Mode to read and write count values
RWST = 1?
Checks wait status of counter.
Yes
Reading SEC
Reads second count register.
Reading MIN
Reads minute count register.
Reading HOUR
Reads hour count register.
Reading WEEK
Reads week count register.
Reading DAY
Reading MONTH
Reading YEAR
RWAIT = 0
No
Reads day count register.
Reads month count register.
Reads year count register.
Sets counter operation.
RWST = 0?Note
Yes
End
Note Be sure to confirm that RWST = 0 before setting HALT/STOP mode.
Caution Complete the series of process of setting the RWAIT bit to 1 to clearing the RWAIT bit to 0 within 1
second.
Remark
The second count register (SEC), minute count register (MIN), hour count register (HOUR), week count
register (WEEK), day count register (DAY), month count register (MONTH), and year count register (YEAR)
may be read in any sequence.
All the registers do not have to read and only some registers may be read.
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Figure 10-20. Procedure for Writing Real-time Clock
Start
No
RWAIT = 1
Stops SEC to YEAR counters.
Mode to read and write count values
RWST = 1?
Checks wait status of counter.
Yes
Writing SEC
Writes second count register.
Writing MIN
Writes minute count register.
Writing HOUR
Writes hour count register.
Writing WEEK
Writes week count register.
Writing DAY
Writing MONTH
No
Writes day count register.
Writes month count register.
Writing YEAR
Writes year count register.
RWAIT = 0
Sets counter operation.
RWST = 0?Note
Yes
End
Note Be sure to confirm that RWST = 0 before setting HALT/STOP mode.
Cautions 1. Complete the series of operations of setting the RWAIT bit to 1 to clearing the RWAIT bit to 0
within 1 second.
2. When changing the values of the SEC, MIN, HOUR, WEEK, DAY, MONTH, and YEAR register
<R>
while the counter operates (RTCE = 1), rewrite the values of the MIN register after disabling
interrupt servicing INTRTC by using the interrupt mask flag register. Furthermore, clear the
WAFG, RIFG and RTCIF flags after rewriting the MIN register.
Remark
The second count register (SEC), minute count register (MIN), hour count register (HOUR), week count
register (WEEK), day count register (DAY), month count register (MONTH), and year count register (YEAR)
may be written in any sequence.
All the registers do not have to be set and only some registers may be written.
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10.4.4 Setting alarm of real-time clock
Set time of alarm after setting 0 to WALE first.
Figure 10-21. Alarm Setting Procedure
Start
WALE = 0
Match operation of alarm is invalid.
WALIE = 1
Interrupt is generated when alarm matches.
Setting ALARMWM
Sets alarm minute register.
Setting ALARMWH
Sets alarm hour register.
Setting ALARMWW
Sets alarm week register.
WALE = 1
No
Match operation of alarm is valid.
INTRTC = 1?
Yes
WAFG = 1?
No
Match detection of alarm Yes
Alarm processing
Constant-period interrupt servicing
Remarks 1. The alarm week register (ALARMWW), alarm hour register (ALARMWH), and alarm week register
(ALARMWW) may be written in any sequence.
2. Fixed-cycle interrupts and alarm match interrupts use the same interrupt source (INTRTC). When using
these two types of interrupts at the same time, which interrupt occurred can be judged by checking the
fixed-cycle interrupt status flag (RIFG) and the alarm detection status flag (WAFG) upon INTRTC
occurrence.
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10.4.5 1 Hz output of real-time clock
Figure 10-22. 1 Hz Output Setting Procedure
Start
RTCE = 0
<R>
Stops counter operation.
Setting port
Sets P30 and PM30
RCLOE1 = 1
Enables output of the RTC1HZ pin (1 Hz).
RTCE = 1
Starts counter operation.
Output start from RTC1HZ pin
Cautions 1.
2.
First set the RTCEN bit to 1, while oscillation of the input clock (fSUB) is stable.
The 1 Hz output function of the real-time clock is not provided in 30-, 32-, and 36-pin products.
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10.4.6 Example of watch error correction of real-time clock
The watch can be corrected with high accuracy when it is slow or fast, by setting a value to the watch error correction
register.
Example of calculating the correction value
The correction value used when correcting the count value of the sub-count register is calculated by using the
following expression.
Set the DEV bit to 0 when the correction range is −63.1 ppm or less, or 63.1 ppm or more.
(When DEV = 0)
Correction valueNote = Number of correction counts in 1 minute ÷ 3 = (Oscillation frequency ÷ Target frequency − 1)
¯ 32768 ¯ 60 ÷ 3
(When DEV = 1)
Correction valueNote = Number of correction counts in 1 minute = (Oscillation frequency ÷ Target frequency − 1) ¯
32768 ¯ 60
Note The correction value is the watch error correction value calculated by using bits 6 to 0 of the watch error
correction register (SUBCUD).
(When F6 = 0) Correction value = {(F5, F4, F3, F2, F1, F0) − 1} ¯ 2
(When F6 = 1) Correction value = − {(/F5, /F4, /F3, /F2, /F1, /F0) + 1} ¯ 2
When (F6, F5, F4, F3, F2, F1, F0) is (*, 0, 0, 0, 0, 0, *), watch error correction is not performed. “*” is 0 or 1.
/F5 to /F0 are bit-inverted values (000011 when 111100).
Remarks 1.
2.
The correction value is 2, 4, 6, 8, … 120, 122, 124 or −2, −4, −6, −8, … −120, −122, −124.
The oscillation frequency is the input clock (fRTC).
It can be calculated from the output frequency of the RTC1HZ pin ¯ 32768 when the watch error
correction register is set to its initial value (00H).
3.
The target frequency is the frequency resulting after correction performed by using the watch error
correction register.
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Correction example
Example of correcting from 32767.4 Hz to 32768 Hz (32767.4 Hz + 18.3 ppm)
[Measuring the oscillation frequency]
The oscillation frequencyNote of each product is measured by outputting about 1 Hz from the RTC1HZ pin when the
watch error correction register (SUBCUD) is set to its initial value (00H).
Note See 10.4.5 1 Hz output of real-time clock for the setting procedure of outputting about 1 Hz from the RTC1HZ
pin.
[Calculating the correction value]
(When the output frequency from the RTCCL pin is 0.9999817 Hz)
Oscillation frequency = 32768 ¯ 0.99