PM8916/PM8916-1 Device Specification

Qualcomm Technologies, Inc.

PM8916/PM8916-1

Device Specification

LM80-P0436-35 Rev. A

August 2015

© 2015 Qualcomm Technologies, Inc. All rights reserved.

Qualcomm Snapdragon is a product of Qualcomm Technologies, Inc. Other Qualcomm products referenced herein are products of Qualcomm

Technologies, Inc. or its other subsidiaries.

DragonBoard, Qualcomm and Snapdragon are trademarks of Qualcomm Incorporated, registered in the United States and other countries. All

Qualcomm Incorporated trademarks are used with permission. Other product and brand names may be trademarks or registered trademarks of their respective owners.

This technical data may be subject to U.S. and international export, re-export, or transfer (“export”) laws. Diversion contrary to U.S. and international law is strictly prohibited.

Use of this document is subject to the license set forth in Exhibit 1.

Qualcomm Technologies, Inc.

5775 Morehouse Drive

San Diego, CA 92121

U.S.A.

LM80-P0436-35 Rev. A

Revision history

Revision

A

Date

August 11, 2015

Initial release

Description

LM80-P0436-35 Rev. A

MAY CONTAIN U.S. AND INTERNATIONAL EXPORT CONTROLLED INFORMATION

2

Contents

1 Introduction ........................................................................................................................... 7

1.1 Documentation overview ............................................................................................................................ 7

1.2 PM8916 introduction .................................................................................................................................. 8

1.3 PM8916 features........................................................................................................................................ 9

1.3.1 Highlighted features integrated into the PM8916 ...................................................................... 9

1.3.2 Summary of PM8916 device features ..................................................................................... 10

1.4 Terms and acronyms ............................................................................................................................... 12

1.5 Special marks .......................................................................................................................................... 13

2 Pin Definitions ......................................................................................................................14

2.1 I/O parameter definitions .......................................................................................................................... 15

2.2 Pin descriptions ....................................................................................................................................... 16

3 Electrical Specifications ......................................................................................................24

3.1 Absolute maximum ratings ....................................................................................................................... 24

3.2 Operating conditions ................................................................................................................................ 25

3.3 DC power consumption ............................................................................................................................ 26

3.4 Digital logic characteristics ....................................................................................................................... 27

3.5 Input power management ........................................................................................................................ 27

3.5.1 Over-voltage protection .......................................................................................................... 27

3.5.2 External supply detection........................................................................................................ 27

3.5.3 Linear battery charger............................................................................................................. 29

3.5.4 Battery voltage monitoring system .......................................................................................... 32

3.5.5 Voltage mode battery monitoring system (VM-BMS) .............................................................. 32

3.5.6 Battery interface parameters (BTM and BPD) ........................................................................ 33

3.5.7 Coin cell charging ................................................................................................................... 35

3.6 Output power management ..................................................................................................................... 35

3.6.1 Reference circuit ..................................................................................................................... 38

3.6.2 Buck SMPS ............................................................................................................................ 38

3.6.3 Linear regulators ..................................................................................................................... 42

3.6.4 Internal voltage-regulator connections .................................................................................... 45

3.7 General housekeeping ............................................................................................................................. 46

3.7.1 Analog multiplexer and scaling circuits ................................................................................... 46

3.7.2 AMUX input to ADC output end-to-end accuracy ................................................................... 49

3.7.3 HK/XO ADC circuit ................................................................................................................. 52

3.7.4 System clocks ......................................................................................................................... 52

3.7.5 Real-time clock ....................................................................................................................... 55

3.7.6 Over-temperature protection (smart thermal control) .............................................................. 55

3.8 User interfaces ......................................................................................................................................... 56

3.8.1 Current drivers ........................................................................................................................ 56

3.8.2 Vibration motor driver ............................................................................................................. 56

3.9 IC-level interfaces .................................................................................................................................... 57

3.9.1 Poweron circuits and the power sequences ........................................................................... 57

3.9.2 OPT[2:1] hardwired controls ................................................................................................... 60

3.9.3 SPMI and the interrupt managers ........................................................................................... 60

3.10 General-purpose input/output specifications .......................................................................................... 60

3.11 Multipurpose pin specifications .............................................................................................................. 62

3.12 Audio codec ........................................................................................................................................... 62

LM80-P0436-35 Rev. A


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PM8916/PM8916-1 Device Specification

3.12.1 Audio inputs and Tx processing ............................................................................................ 63

3.12.2 Audio outputs and Rx processing ......................................................................................... 65

3.12.3 Support circuits ..................................................................................................................... 69

4 Mechanical Information .......................................................................................................70

4.1 Device physical dimensions ..................................................................................................................... 70

4.2 Part marking ............................................................................................................................................ 72

4.2.1 Specification-compliant devices .............................................................................................. 72

4.3 Device ordering information ..................................................................................................................... 73

4.3.1 Specification-compliant devices .............................................................................................. 73

4.4 Device moisture-sensitivity level .............................................................................................................. 74

5 Carrier, Storage, and Handling Information .......................................................................75

5.1 Carrier ...................................................................................................................................................... 75

5.1.1 Tape and reel information ....................................................................................................... 75

5.2 Storage .................................................................................................................................................... 76

5.2.1 Bagged storage conditions ..................................................................................................... 76

5.2.2 Out-of-bag duration ................................................................................................................ 76

5.3 Handling ................................................................................................................................................... 76

5.3.1 Baking..................................................................................................................................... 76

5.3.2 Electrostatic discharge............................................................................................................ 76

6 PCB Mounting Guidelines ...................................................................................................78

6.1 RoHS compliance .................................................................................................................................... 78

6.2 SMT parameters ...................................................................................................................................... 78

6.2.1 Land pad and stencil design ................................................................................................... 78

6.2.2 Reflow profile .......................................................................................................................... 79

6.2.3 SMT peak package-body temperature ................................................................................... 80

6.2.4 SMT process verification ........................................................................................................ 81

6.3 Board-level reliability ................................................................................................................................ 81

7 Part Reliability ......................................................................................................................82

7.1 Reliability qualifications summary ............................................................................................................ 82

7.1.1 PM8916 reliability evaluation report for NSP device ............................................................... 82

7.2 Qualification sample description .............................................................................................................. 84

A Exhibit 1 ...............................................................................................................................85

Contents

LM80-P0436-35 Rev. A


4


Figures

Figure 1-1 High-level PM8916 functional block diagram ................................................................................................ 9

Figure 2-1 PM8916 pin assignments (top view) ........................................................................................................... 14

Figure 3-1 LBC flowchart ............................................................................................................................................. 31

Figure 3-2 Battery-temperature monitoring .................................................................................................................. 34

Figure 3-3 S1 PFM efficiency plots .............................................................................................................................. 40




Figure 3-7 Multiplexer offset and gain errors ................................................................................................................ 51

Figure 3-8 Analog-multiplexer load condition for settling time specification ................................................................. 51

Figure 3-9 Poweron sequence for BB code ‘01’ and ‘02’ ............................................................................................. 59

Figure 3-10 Poweron sequence for BB code ‘VV’ ........................................................................................................ 60

Figure 4-1 6.2 x 6.2 x 0.86 mm outline drawing ........................................................................................................... 71

Figure 4-2 PM8916 device marking (top view, not to scale) ......................................................................................... 72

Figure 4-3 Device identification code ........................................................................................................................... 73

Figure 5-1 Carrier tape drawing with part orientation ................................................................................................... 75

Figure 5-2 Tape handling ............................................................................................................................................. 76

Figure 6-1 Stencil printing aperture area ratio (AR)...................................................................................................... 79

Figure 6-2 Acceptable solder-paste geometries ........................................................................................................... 79

Figure 6-3 QTI typical SMT reflow profile ..................................................................................................................... 80

Tables

Table 1-1 Primary PM8916 device documentation......................................................................................................... 7

Table 1-2 PM8916 device features .............................................................................................................................. 10

Table 1-3 Terms and acronyms ................................................................................................................................... 12

Table 1-4 Special symbols ........................................................................................................................................... 13

Table 2-1 I/O description (pad type) parameters .......................................................................................................... 15

Table 2-2 Pin descriptions – Input power management functions ................................................................................ 16

Table 2-3 Pin descriptions – output power management functions .............................................................................. 17

Table 2-4 Pin descriptions – general housekeeping functions ..................................................................................... 18

Table 2-5 Pin descriptions – User interface functions .................................................................................................. 19

Table 2-6 Pin descriptions – Audio............................................................................................................................... 19

Table 2-7 Pin descriptions – IC-level interface functions .............................................................................................. 20

Table 2-8 Pin descriptions – configurable input/output functions ................................................................................. 21

Table 2-9 Pin descriptions – input DC power ............................................................................................................... 22

Table 2-10 Pin descriptions – grounds ......................................................................................................................... 22

Table 3-1 Absolute maximum ratings ........................................................................................................................... 24

Table 3-2 Operating conditions .................................................................................................................................... 25

Table 3-3 DC power supply currents ............................................................................................................................ 26

Table 3-4 Audio power supply peak current ................................................................................................................. 26

Table 3-5 Digital I/O characteristics ............................................................................................................................. 27

Table 3-6 External source interface performance specifications .................................................................................. 28

Table 3-7 Linear charger specifications ....................................................................................................................... 29

Table 3-8 Trickle charging performance specifications ................................................................................................ 29

Table 3-9 UVLO performance specifications ................................................................................................................ 32

Table 3-10 SMPL performance specifications .............................................................................................................. 32

Table 3-11 Battery fuel-gauge specifications ............................................................................................................... 32

Table 3-12 State of charge (SOC) specifications ......................................................................................................... 33

Contents

LM80-P0436-35 Rev. A


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Table 3-13 Battery interface specifications .................................................................................................................. 33

Table 3-14 Battery-temperature monitoring calculations .............................................................................................. 35

Table 3-15 Coin cell charging performance specifications ........................................................................................... 35

Table 3-16 Regulator high-level summary ................................................................................................................... 36

Table 3-17 Voltage-reference performance specifications ........................................................................................... 38

Table 3-18 SMPS performance specifications ............................................................................................................. 39

Table 3-19 LDO performance specifications ................................................................................................................ 42

Table 3-20 Internal voltage regulator connections ....................................................................................................... 45

Table 3-21 Boost specifications ................................................................................................................................... 45

Table 3-22 Analog multiplexer and scaling functions ................................................................................................... 46

Table 3-23 Analog multiplexer performance specifications .......................................................................................... 47

Table 3-24 AMUX input to ADC output end-to-end accuracy ....................................................................................... 49

Table 3-25 HK/XO ADC performance specifications .................................................................................................... 52

Table 3-26 XO controller, buffer, and circuit performance specifications ..................................................................... 53

Table 3-27 RC oscillator performance specifications ................................................................................................... 54

Table 3-28 RTC performance specifications ................................................................................................................ 55

Table 3-29 Vibration motor driver performance specifications ..................................................................................... 56

Table 3-30 Poweron circuit performance specifications ............................................................................................... 57

Table 3-31 OPT_1 and OPT_2 PON parameters......................................................................................................... 60

Table 3-32 Programmable GPIO configurations .......................................................................................................... 61

Table 3-33 VOL and VOH for different driver strengths ............................................................................................... 61

Table 3-34 Multipurpose pin performance specifications ............................................................................................. 62

Table 3-35 Analog microphone input performance ...................................................................................................... 63

Table 3-36 Ear output performance, 32

Ω load unless specified.................................................................................. 65

Table 3-37 HPH output performance, 16

Ω load unless specified ................................................................................ 66

Table 3-

38 Mono speaker driver outputs performance, 8 Ω load and + 12 dB gain unless otherwise specified .......... 67

Table 3-39 Microphone bias specifications .................................................................................................................. 69

Table 4-1 PM8916 device marking line definitions ....................................................................................................... 72

Table 4-2 PM8916 device identification details ............................................................................................................ 73

Table 4-3 Feature codes .............................................................................................................................................. 73

Table 4-4 Source configuration code ........................................................................................................................... 74

Table 6-1 QTI typical SMT reflow-profile conditions (for reference only) ...................................................................... 79

Table 7-1 Silicon reliability results for SMIC ................................................................................................................. 82

Table 7-2 Silicon reliability results for TSMC ................................................................................................................ 83

Table 7-3 Package reliability results for SMIC/TSMC ................................................................................................. 83

Contents

LM80-P0436-35 Rev. A


6

1 Introduction

1.1 Documentation overview

This device specification defines the following power management IC devices: PM8916 and

PM8916-1. Throughout this document, the devices are referred to as PM8916 when material being presented applies to both, unless mentioned otherwise for PM8916-1.

Technical information for PM8916 is primarily covered by the documents listed in Table 1-1 , and

all should be studied for a thorough understanding of the IC and its applications. Released

PM8916 documents are available for download at https://developer.qualcomm.com/hardware/dragonboard-410c/tools .

Table 1-1 Primary PM8916 device documentation

Document number

Title/description

LM80-P0436-34

LM80-P0436-36

PM8916/PM8916-1 Device Revision Guide

Provides a history of PM8916 revisions. It explains how to identify the various IC revisions and discusses known issues (or bugs) for each revision and how to work around them.

LM80-P0436-35

(this document)

PM8916/PM8916-1 Device Specification

Provides all PM8916 electrical and mechanical specifications. Additional material includes pin assignment definitions; shipping, storage, and handling instructions; PCB mounting guidelines; and part reliability. This document can be used by the company purchasing departments to facilitate procurement.

PM8916 Hardware Register Description Document

This PM8916 device specification is organized as follows:

Chapter 1

– Provides an overview of PM8916 documentation, shows a high-level PM8916 functional block diagram, lists the device features, and lists terms and acronyms used throughout the document.

Chapter 2

– Defines the IC pin assignments.

Chapter 3

– Defines the IC electrical performance specifications, including absolute maximum ratings and recommended operating conditions.

Chapter 4 – Provides IC mechanical information, including dimensions, markings, ordering information, moisture sensitivity, and thermal characteristics.

Chapter 5 – Discusses shipping, storage, and handling of PM8916 devices.

Chapter 6 – Presents procedures and specifications for mounting the PM8916 onto printed circuit boards (PCBs).

Chapter 7 – Presents PM8916 reliability data, including definitions of the qualification samples and a summary of qualification test results.

LM80-P0436-35 Rev. A


7

PM8916/PM8916-1 Device Specification Introduction

1.2 PM8916 introduction

The PM8916 device ( Figure 1-1 ) integrates all wireless handset power management, general

housekeeping, and user interface support functions into a single mixed-signal IC. Its versatile design is suitable for multimode, multiband phones, and other wireless products such as data cards and PDAs.

The PM8916 mixed-signal HV-CMOS device is available in the 176-pin nanoscale package

(NSP) that includes several ground pins for improved electrical ground, mechanical stability, and thermal continuity.

PM8916 supports APQ8016 platforms and PM8916-1 supports APQ8009 platforms. The only difference between PM8916 and PM8916-1 is the default power-on voltage settings.

Since the PM8916 device includes many diverse functions, its operation can be understood better by studying the major functional blocks individually. Therefore, the PM8916 document set is organized by the device functionality as follows:



Input power management



Output power management



General housekeeping



User interfaces



IC interfaces



Configurable pins – either multipurpose pins (MPPs) or general-purpose input/output

(GPIOs) – that can be configured to function within some of the other categories.



Most of the information contained in this document is organized accordingly – including the

circuit groupings within the block diagram ( Figure 1-1 ), pin descriptions (

Chapter 2 ), and detailed electrical specifications ( Chapter 3 ). Refer to the PM8916 Power Management IC

Training Slides (80-NK808-21) for more detailed diagrams and descriptions of the PM8916 device functions and interfaces.

LM80-P0436-35 Rev. A


8


Five major functional blocks:

1) Input power management

2) Output power management

3) General housekeeping

4) User interfaces

5) IC-level interfaces

Regulated V_OUTs (4)






Regulated V_OUT (1)

Regulated V_OUT (1)

Regulated V_OUT (1)

Regulated V_OUT (1)

VBAT

Battery

Module

PM8916

• 4 MPPs

• 4 GPIOs

USB connector

Headset coin cell/ capacitor

OVP

Coin Cell

Charger

1

Input power management

VBAT or 5V

Ext boost

WLED driver

Vibration motor

Analog mics

Mic bias

Home row driver – MPP2

Vib motor driver

User

Interfaces

4

PWM dimming – MPP4

Audio

Integrated Codec

HS detect

Earpiece

Loud

Speaker

Analog I/Os

Bgap

VREF

Linear regulators

VREFs

DIV

XO

Buffers / controls

2

HK / XO

ADC & controller

General

Housekeeping

19.2 M

XO

DDR

VREF

Output Power Management

3

OVP = over-voltage protection

ATC = auto trickle charging

PWM = pulse width modulation

WLED = white LED (high voltage)

Poweron circuits

SPMI & interrupt mgr

Memory & controls

5

IC-level interfaces

Scaling & multiplexing

SWs

PON events external

REG controls

BUA

PS_HOLD

SPMI

PON_RST_N to/from modem IC

BUA = Bidirectional

Battery/UICC Alarm

SPMI = System power

management interface

SMPL = Sudden momentary

power loss

RTC = Real-time clock

XO = Crystal oscillator

HK = Housekeeping

RCO = RC oscillator

Analog inputs to scaling

Analog inputs to switches

Low noise XO outputs (RF)

Low power XO output (BB)

XO output enables (BB&RF)

VREF_OUTs

Sleep clock output

Figure 1-1 High-level PM8916 functional block diagram

1.3 PM8916 features

NOTE:

Some of the hardware features integrated within the PM8916 must be enabled through the host IC software. Refer to the latest version of the applicable software release notes to identify the enabled PMIC features.

1.3.1 Highlighted features integrated into the PM8916



Dual SIM dual active (DSDA) support



Bidirectional battery UICC alarm (BUA) for graceful UICC shutdown upon battery or UICC removal.



Linear battery charger



USB source with built-in 16 V over-voltage protection (OVP)



Integrated OVP FET



Four GPIOs of which two can output high-speed clocks



Pulse width modulator (PWM) for dimming control of external WLED IC driver

LM80-P0436-35 Rev. A


9




Home row LED driver



Plug-and-play support



Programmable reset control



Audio codec (ADCs and DACs), stereo head phone, ear and speaker amplifiers. The digital decimator and interpolator chains exist in the corresponding APQ8016/APQ8009.

1.3.2 Summary of PM8916 device features

Table 1-2 lists the features of the PM8916 device.

Table 1-2 PM8916 device features

Feature

Input power management

Supported external power source

Over-voltage protection

Supported battery technologies

Charger regulation method

Supported charging modes

PM8916 capability

USB

Fully integrated up to +16 V (integrated OVP FET)

Lithium-ion, lithium-ion polymer


 Autonomous charging modes

 Trickle charging

Trickle, constant current, and constant voltage modes.

Enhanced automation for lesser software interaction

Dedicated charging indication LED current sink

Internal and external nodes; reported to on-chip state-machine

Charger on indication

Voltage, current, and temperature sensors

Battery monitoring system

Coin cell or capacitor backup

Output voltage regulation

Switched-mode power supplies:

Voltage Mode Battery Monitoring system (VM-BMS)

Keep-alive power source; orchestrated charging

Low dropout linear regulators

 Four buck converters

 One 5 V boost converter

 20 LDOs

 Three NMOS LDOs

 15 PMOS LDOs

 Two custom low-noise LDOs for the clock system

All LDOs except L1, L2, and L3

Reference voltage output for LPDDR2/LPDDR3

Pseudo-capless LDO designs

LPDDR support

General housekeeping

On-chip ADC

Analog multiplexing for ADC

 HK inputs

 XO input

Over-temperature protection

Shared housekeeping (HK) and XO support

 Many internal nodes and external inputs, including configurable MPPs

 Dedicated pin (XO_THERM)

Multistage smart thermal control

LM80-P0436-35 Rev. A


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19.2 MHz oscillator support

XO controller and XO outputs

Sleep clock output

32 kHz clock source

Real-time clock

Audio inputs

Audio outputs

Feature

Multi-button headset control (MBHC)

PM8916 capability

XO (with on-chip ADC)

Four sets:

 Two low-noise RF outputs

 Two low-power baseband outputs

One (dedicated)

XO/586 and RC CAL circuits provide real-time clock with alarm.

32,768 Hz crystal oscillator is not supported.

RTC clock circuits and alarms

 Three single-ended inputs

 Two ADCs

 Up to five button MBHC headset support

 One input for headset jack detection

 Four outputs – Ear, HPHL + HPHR, Class-D speaker driver

 Three DACs

 Over current protection on HPH, EAR, and speaker outputs

Multiple input/output audio sample rates Supports sample rates 8 kHz, 16 kHz, 32 kHz, and 48 kHz

User interfaces

Pulse width modulator

Home row LED driver

Other current drivers

Dimming control of external WLED driver

Current sink through even MPPs

Even MPPs can be configured to sink up to 40 mA

ATC indicator (see input power management features)

1.2 to 3.1 V in 100 mV increments

Vibration motor driver

IC-level interfaces

Primary status and control

Interrupt managers

Optional hardware configurations

Power sequencing

Extra features

2-line SPMI

Supported by SPMI

OPT bits select hardware configuration

Power on, power off, and soft resets

External regulator; detects inputs; battery-enabled UICC alarm;

UIM support (x2)

Configurable I/Os

MPPs

GPIO pins

Four; configurable as digital in/out; unidirectional leveltranslating I/Os; analog multiplexer inputs; current sinks; VREF buffer outputs; MPP1 and MPP3 is fixed for VDD_PX_BIAS and

VREF_DAC respectively

Four; configurable as digital inputs or outputs or level-translating

I/Os; all are faster than MPPs

Package

Size

Pin count and package type

6.2 mm × 6.2 mm

176 pin WB-NSP

LM80-P0436-35 Rev. A


11


1.4 Terms and acronyms

Table 1-3 defines terms and acronyms used throughout this document.

Table 1-3 Terms and acronyms

Term or acronym

I2S

IIR kbps

LBC

LDO

LPF

MAD

MBHC

MIC or mic

NS

NVM

OEM

OSR

PA

PCB

PCM

PGA

RoHS

Rx

SLIMbus

SMT

ADC

AMSS

ANC

BOM

BPF bps

CDMA

CP

DAC

DMIC

DRE

ESD

ESR

I2C

Definition

Analog-to-digital converter

Advanced mobile subscriber station (software)

Active noise cancellation

Bill of materials

Bandpass filter

Bits per second

Code division multiple access

Charge pump

Digital-to-analog converter

Digital microphone

Dynamic range enhancement

Electrostatic discharge

Effective series resistance

Inter-integrated circuit

Inter-IC sound

Infinite impulse response

Kilobits per second


Low dropout (linear regulator)

Low-pass filter

Microphone activity detection

Multi-button headset control

Microphone

Noise shaper

Nonvolatile memory

Original equipment manufacturer

Over-sampling rate

Power amplifier

Printed circuit board

Pulse-coded modulation

Programmable gain amplifier

Restriction of hazardous substances

Receive, receiver

Serial low-power inter-chip media bus

Surface-mount technology

LM80-P0436-35 Rev. A


Introduction

12


Term or acronym

SNR

ST

TCXO

Tx

VM-BMS

WCD

WLNSP

WSP

XO

ZIF

Definition

Signal-to-noise ratio

Sidetone

Temperature-compensated crystal oscillator

Transmit, transmitter

Voltage mode battery monitoring system

WSP coder/decoder

Wafer-level nanoscale package

Wafer-scale package

Crystal oscillator

Zero intermediate frequency

1.5 Special marks

Table 1-4 lists some special symbols used in this document.

Table 1-4 Special symbols

Mark

[ ]

_N

0x0000

|

Definition

Brackets ([ ]) sometimes follow a pin, register, or bit name. These brackets enclose a range of numbers. For example, DATA [7:4] may indicate a range that is 4 bits in length, or DATA[7:0] may refer to eight DATA pins.

A suffix of _N indicates an active low signal. For example, PON_RESET_N.

Hexadecimal numbers are identified with an x in the number, (for example,

0x0000). All numbers are decimal (base 10) unless otherwise specified.

Non-obvious binary numbers have the term binary enclosed in parentheses at the end of the number [for example, 0011 (binary)].

A vertical bar in the outside margin of a page indicates that a change has been made since the previous revision of this document.

LM80-P0436-35 Rev. A


13

2 Pin Definitions

The PM8916 is available in the 176 NSP – see Chapter 4

for package details. Figure 2-1 shows

a high-level view of the pin assignments for the PM8916.

A

1

VREG

_L18

2

VREF

_LPDDR

3

VREG

_L17

B

VDD_L8_9_ VDD_L8_9_

10_11_12_13 10_11_12_13

18 18

VREG

_L12

C

VREG

_L9

AVDD

_BYP

RESIN

_N

G

H

J

K

VREG

_L15

XTAL_

19M_IN

VREG

_XO

VREG

_L14

XTAL_

19M_OUT

GND

_XO

XO_

THERM

VREG

_L11

GND_

XO_ISO

GND

_RF

VREG_

RFCLK

4

GND

_S1

GND

_S1

GND

_S1

GND

MPP_3

MPP_2

5

VSW

_S1

VSW

_S1

VSW

_S1

PS_

HOLD

MPP_4

GND

6

VDD

_S1

VDD

_S1

VDD

_S1

D

REF

_BYP

GND

_REF

VREG

_L13

VREG

_L10

OPT_1

E

VDD_L8_9_

10_11_12_13

VDD_L8_9_

10_11_12_13

18 18

VREG

_L16

BB_

CLK1_EN

VREG

_S1

F

VREG

_L8

BB_

CLK1

BB_

CLK2

PON_

RST_N

GND

SLEEP

_CLK

OPT_2 GPIO_2

GND

7

VDD

_S2

VDD

_S2

VDD

_S2

GND

GND

VREG

_S2

GND

GND

GPIO

_1

8

VSW

_S2

VSW

_S2

VSW

_S2

PDM_

SYNC

9

GND

_S2

GND

_S2

GND

_S2

GND

10

SPMI

_CLK

SPMI

_DATA

GND

PDM_

RX0

11

VREG_

BOOST

12

VSW_

BOOST

13

NC

VREG_

BOOST

VSW_

BOOST

GND_

BOOST

VDD

_CP

GND

PDM_

TX

14

GND_

BOOST

CP_

C1_P

VDD

_CP

GND

_CP

CP_

C1_N

VDD_

AUDIO

_IO

CP_

VNEG

CP_

VNEG

SPKR_

DRV_M

SPKR_

DRV_M

GND

_SPKR

PDM_

CLK

GND

GND

VREG

_S3

VREG

_S4

PDM_

RX2

BAT

_ID

GND

PDM_

RX1

PA_

THERM

HPH_L EARO_P

SPKR_

DRV_P

GND HPH_REF HPH_R EARO_M

VDD_

EAR_

SPKR

GND GND GND

VDD_

HPH

MIC3_IN

MIC_

BIAS2

KPD_

PWR_N

MIC2_IN

GND_

AUDIO

_REF

GND

_CFILT

HPH_

VNEG

MIC1_IN

HS_

DET

L

RF_

CLK1

RF_

CLK2

VREG

_L7

M

VREG

_L2

VDD_

XO_

RFCLK

VDD

_L7

N

VDD_L1_2 VDD_L1_2

_3 _3

GND

_S3

MPP_1

VSW

_S3

VSW

_S3

VDD

_S3

VDD

_S3

VDD

_S4

VDD

_S4

VSW

_S4

VSW

_S4

GPIO_4

VREG

_L6

GND

_S4

VREG

_L4

VDD_

L4_5_6

CBL_

PWR_N

VCOIN

MIC_

BIAS1

VREG

_L4

GND_

XOADC

BAT_

THERM

GPIO_3

VBAT

_SNS

VBAT

GND

_DRV

CHG_

LED_

SINK

VIB_

DRV_N

USB

_IN

VREF_

BAT_THM

P

VREG

_L3

VREG

_L1

AUDIO

GND

_S3

INPUT

PWR MGT

VSW

_S3

VDD

_S3

OUTPUT

PWR MGT

VDD

_S4

GEN HK

VSW

_S4

GND

_S4

VDD_

L4_5_6

VREG

_L5

USER I/F

Figure 2-1 PM8916 pin assignments (top view)

IC I/F

GPIO or

MPP

VBAT

Pow er

USB

_IN

VPRE

_BYP

Ground

LM80-P0436-35 Rev. A


14


2.1 I/O parameter definitions

Table 2-1 I/O description (pad type) parameters

Symbol Description

Pad attribute

AI

AO

DI

DO

PI

PO

Z

Analog input

Analog output

Digital input (CMOS)

Digital output (CMOS)

Power input; a pin that handles 10 mA or more of current flow into the device

Power output; a pin that handles 10 mA or more of current flow out of the device

High-impedance (high-Z) output

Pad voltage groupings

V_INT

V_PAD

V_XBB

V_XRF

V_G

V_M

Internally generated supply voltage for some power on circuits

Supply for host IC interfaces; connected internally to VREG_L5

Supply for XO low-power (BB) output buffers; connected internally to VREG_L7

Supply for XO low-noise (RF) output buffers; connected internally to

LDO VREG_RFCLK

Pad voltage grouping (GPIO_1 and GPIO_2 cannot be configured to VBAT supply group)

Selectable supply for GPIO circuits; options include:

0 = VBAT

1 = VBAT

2 = VREG_L2

3 = VREG_L5

Selectable supply for MPP circuits; options include:

0 = VBAT

1 = VBAT

2 = VREG_L2

3 = VREG_L5

GPIO pin configurations

GPIO pins, when configured as inputs, have configurable pull settings

NP

No internal pull enabled

PU

Internal pull-up enabled

PD

Internal pull-down enabled

GPIO pins, when configured as outputs, have configurable drive strengths

H

M

L

High: ~ 0.9 mA at 1.8 V; ~ 1.9 mA at 2.6 V

Medium: ~ 0.6 mA at 1.8 V; ~ 1.25 mA at 2.6 V

Low: ~ 0.15 mA at 1.8 V; ~ 0.3 mA at 2.6 V

Pin Definitions

LM80-P0436-35 Rev. A


15

PM8916/PM8916-1 Device Specification Pin Definitions

2.2 Pin descriptions

The following tables list the descriptions of all the respective pins, organized by their functional group:



Table 2-2 – Input power management



Table 2-3 – Output power management



Table 2-4 – General housekeeping



Table 2-5 – User interfaces



Table 2-6 – Audio



Table 2-7 – IC-level interfaces



Table 2-8 – Configurable input/output – GPIO and MPPs



Table 2-9 – Power supply pins



Table 2-10 – Ground pins

Table 2-2 Pin descriptions – Input power management functions

Pad #

Pad name and/or function

Pad name or alt function

Pad characteristics

1

Voltage

Type

Linear charger

N13, P13

C2

P14

BMS circuits

N12, P12

M12

USB_IN

AVDD_BYP

VPRE_BYP

VBAT

VBAT_SNS

–

–

–

–

–

PI

AO

AO

Functional description

Input power from USB source

Bypass cap for internal analog circuits

VPRE regulator load capacitor

PI, PO Battery node; input during battery operation, output during charging, and sense point for

UVLO detection

AI Main battery voltage sense point for

VM-BMS, Vtrkl, VDD_MAX, and

VBAT_WEAK

Coin cell or keep-alive battery

L11 VCOIN

–

AI, AO Sense input or charge output

1

See Table 2-1 for parameter and acronym definition.

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16


Table 2-3 Pin descriptions – output power management functions

Pad #



1

Voltage Type

Switched-mode power supply (SMPS) circuits

A5, B5, C5

E5

A8, B8, C8

F7

M4, N4, P4

J8

M7, N7, P7

K8

A12, B12

A11, B11

VSW_S1

VREG_S1

VSW_S2

VREG_S2

VSW_S3

VREG_S3

VSW_S4

VREG_S4

VSW_BOOST

VREG_BOOST

–

–

–

–

–

–

–

–

–

–

D4

G3

B3

D3

G2

G1

E3

A3

P2

M1

P1

M10, M9

P10

M8

L3

F1

C1

A1

K3

K1

LDO linear regulators

VREG_L1

VREG_L2

VREG_L3

VREG_L4

VREG_L5

VREG_L6

VREG_L7

VREG_L8

VREG_L9

VREG_L10

VREG_L11

VREG_L12

VREG_L13

VREG_L14

VREG_L15

VREG_L16

VREG_L17

VREG_L18

VREG_RFCLK

VREG_XO

Bandgap voltage reference (VREF) circuits

D1

REF_BYP –

–

–

–

–

–

–

–

–

–

–

–

–

–

–

–

–

–

–

–

–

AO

1


PO

AI

PO

AI

PO

AI

PO

AI

PI

PO

PO

PO

PO

PO

PO

PO

PO

PO

PO

PO

PO

PO

PO

PO

PO

PO

PO

PO

PO

PO


Buck converter S1 switching output

Buck converter S1 sense point







Boost converter switching net

Boost converter output voltage

Linear regulator L1 output


















Linear regulator for RF CLK output

Linear regulator for XO output

Bandgap reference bypass cap

Pin Definitions

LM80-P0436-35 Rev. A


17


Table 2-4 Pin descriptions – general housekeeping functions

Pad #




Voltage

GPIO assignments for general housekeeping functions

2

MPP assignments for general housekeeping functions

3

Analog multiplexer and HK/XO ADC circuits

K2

F11

XO_THERM

PA_THERM

–

–

M11 BAT_THERM

G9 BAT_ID

19.2 MHz XO circuits

–

–

J1

H2

L1

L2

XTAL_19M_IN

XTAL_19M_OUT

RF_CLK1

RF_CLK2

–

–

V_XRF

V_XRF

F2

F3

BB_CLK1

BB_CLK2

E4 BB_CLK1_EN

Sleep clock

G6 SLEEP_CLK

VREF outputs

N14 VREF_BAT_THM

A2 VREF_LPDDR

V_XBB

V_XBB

V_PAD

V_PAD

–

–

Type

AI

AI

AI

AI

DO

AO

AO

1

AI

AO

DO

DO

DO

DO

DI


ADC input – XO thermistor

AMUX input – PA thermistor output

AMUX input – Battery thermistor output

AMUX input – Battery ID

19.2 MHz crystal input

19.2 MHz crystal output

RF (low-noise) XO output 1

RF (low-noise) XO output 2

Baseband (low power) XO output 1

Baseband (low power) XO output 2

Baseband XO output 1 enable

Sleep clock to host IC and others

Reference voltage for XO thermistor

Reference voltage for

LPDDR 2 / LPDDR 3 memory

1

See Table 2-1 for parameter and acronym definition

2

GPIOs are used for other general housekeeping functions not listed here; those details will be included in future revisions of this document. To assign a GPIO a particular function, identify the application’s requirements and map

each GPIO to its function – carefully avoiding assignment conflicts. Table 2-8 lists all the GPIOs.

3

MPPs are used for other general housekeeping functions not listed here; those details will be included in future revisions of this document. To assign an MPP a particular function, identify the application’s requirements and map

each MPP to its function – carefully avoiding assignment conflicts. Table 2-8 lists all the MPPs.

LM80-P0436-35 Rev. A


18


Table 2-5 Pin descriptions – User interface functions

Pad #




1

Voltage Type

GPIO assignments for user interface functions

2

MPP assignments for user interface functions

3

Low-voltage current drivers

M13

CHG_LED_SINK

Vibration motor driver

M14

VIB_DRV_N

–

–

AO

PO


Charging indication LED driver output

Vibration motor driver output control

Table 2-6 Pin descriptions – Audio

Pad #


L12

J11

D13, D14

B14

C14

K13

K11

MIC_BIAS1

MIC_BIAS2

CP_VNEG

CP_C1_P

CP_C1_N

MIC1_IN

MIC2_IN

J10

K14

F13

G13

F12

G11

G12

F14

MIC3_IN

HS_DET

EARO_P

EARO_M

HPH_L

HPH_REF

HPH_R

SPKR_DRV_P

E12, E13 SPKR_DRV_M

F8 PDM_CLK


E8

E11

E10

PDM_SYNC

PDM_TX

PDM_RX0


4

Voltage

–

–

–

–

–

–

–

–

–

–

–

–

–

–

–

–

–

Type

AI

AI

AO

AO

AO

AI

AO

AO

AO

DI

AO

AO

AO

AO

AO

AI

AI

–

–

–

DI

DO

DI


Microphone bias #1

Microphone bias #2

Charge pump negative output

Charge pump fly cap terminal 1

Charge pump fly cap terminal 2

Main mic

Headset mic

Second mic

Headset detection

Earpiece PA + output

Earpiece PA – output

Headphone PA left channel output

Headphone PA ground sensing

Headphone PA right channel output

Class-D speaker amp + output

Class-D speaker amp – output

PDM clock signal and master clock for codec

PDM synchronization signal

PDM Tx data channel

PDM RX0 data channel

1


2

GPIOs are used for other general housekeeping functions not listed here; those details will be included in future revisions of this document. To assign a GPIO a particular function, identify the application’s

requirements and map each GPIO to its function – carefully avoiding assignment conflicts. Table 2-8 lists all

the GPIOs.

3

MPPs are used for other general housekeeping functions not listed here; those details will be included in future revisions of this document. To assign an MPP a particular function, identify the application’s

requirements and map each MPP to its function – carefully avoiding assignment conflicts. Table 2-8 lists all

the MPPs.

4

See Table 2-1 for parameter and acronym definitions.

LM80-P0436-35 Rev. A


19


Pad #

F10

F9

J14


PDM_RX1

PDM_RX2

HPH_VNEG



4

Voltage

–

–

–

Type

DI

DI

AI




Headphone amplifier negative supply

Table 2-7 Pin descriptions – IC-level interface functions

Pad #




Voltage

GPIO assignments for IC-level interface functions

2

Type

1

MPP assignments for IC-level interface functions

3

Poweron circuit inputs

L10

K10

H5

D5

G5

C3

CBL_PWR_N

KPD_PWR_N

OPT_2

OPT_1

PS_HOLD

RESIN_N

V_INT

V_INT

V_INT

V_INT

V_PAD

V_INT

DI

DI

DI

DI

DI

DI


Cable poweron detect input

Keypad poweron detect input

Option HW configuration control bit 2

Option HW configuration control bit 1

Power-supply hold control input

PMIC reset input

Poweron circuit outputs and primary PM/host IC interface signals

A10

B10

F5

SPMI_CLK

SPMI_DATA

PON_RST_N

V_PAD

V_PAD

V_PAD

DI Slave and PBUS interface clock

DI, DO Slave and PBUS interface data

DO

Poweron reset output control

Pin Definitions

1


2

GPIOs are used for other general housekeeping functions not listed here; those details will be included in future revisions of this document. To assign a GPIO a particular function, identify the application’s

requirements and map each GPIO to its function – carefully avoiding assignment conflicts. Table 2-8 lists all

the GPIO1s.

3

MPPs are used for other general housekeeping functions not listed here; those details will be included in future revisions of this document. To assign an MPP a particular function, identify the application’s

requirements and map each MPP to its function – carefully avoiding assignment conflicts. Table 2-8 lists all

the MPPs.

LM80-P0436-35 Rev. A


20


Table 2-8 Pin descriptions – configurable input/output functions

Pad # Pad name

Configurable function


1

Voltage Type


Predefined MPP functions – available only at the assigned MPPs

L4

K4

J4

J5

MPP_1

MPP_2

MPP_3

MPP_4

VDD_PX_BIAS

Digital I/O

(optional)

SKIN_TEMP

HR_LED_SNK

Digital I/O

(optional)

VREF_DAC

Digital I/O

(optional)

WLED_PWM

Digital I/O

(optional)

–

–

V_M

–

–

–

V_M

–

–

V_M

–

V_M

V_M

AO-Z

AO

DI, DO

AO-Z

AI

AI

DI, DO

AO-Z

AO

DI, DO

AO-Z

DO

DI, DO

Configurable MPP

Reference for host IC I/O

Digital input/output usage (optional)

Configurable MPP

Skin temperature measurement

Home row LED current sink


Configurable MPP

Reference for host IC DAC


Configurable MPP

PWM control for external WLED driver


Predefined GPIO functions – available only at the assigned GPIOs

J7

H6

N11

GPIO_1

GPIO_2

GPIO_3

UIM_BATT_AL

M

NFC_CLK_REQ

WCN_LDO_EN

V_G

–

V_G

–

V_G

–

DO-Z

DI, DO

DO-Z

DI

DO-Z

DO

Configurable GPIO

Battery removal alarm for UIM and UIM battery alarm input to the APQ

Configurable GPIO

NFC control signal to request clock

Configurable GPIO

Enable signal to power WCN with external 1.35 V

LDO in PM8916-1

L8

GPIO_4

EXT_BUCK_EN

V_G

–

DO-Z

DO

Configurable GPIO

Enable signal for external buck converter to power applications core.

NOTE:

All MPPs default to their high-Z state at powerup and must be configured after powerup for their intended purposes. All GPIOs default to 10 µA pulldown at powerup and must be configured after powerup for their intended purposes.

NOTE:

Configure unused MPPs as 0 mA current sinks (high-Z) and GPIOs as digital inputs with their internal pull-downs enabled.

NOTE:

Only even MPPs can be configured as current sink and only odd MPPs can be configured as analog output.

1


LM80-P0436-35 Rev. A


21


Table 2-9 Pin descriptions – input DC power

Pad # Pad name Functional description

N1, N2

N9, P9

1

B1, B2, E1, E2

2

M2

M3

A6, B6, C6

A7, B7, C7

M5, N5, P5

M6, N6, P6

Audio input power

VDD_L1_2_3

VDD_L4_5_6

VDD_L8_9_10_11_12_13_

14_15_16_17_18

VDD_XO_RFCLK

VDD_L7

VDD_S1

VDD_S2

VDD_S3

VDD_S4

Power supply for LDO L1, L2, and L3 circuits

Power supply for LDO L4, L5, and L6 circuits

Power supply for LDO L8 to L18 circuits

Power supply for LDO VREG_XO and VREG_RFCLK circuits

Power supply for LDO L7 circuits

Power supply for S1 buck converter




A13

H13

G14

NC

VDD_HPH

VDD_EAR_SPKR

Can be connected to VBAT to maintain backward compatibility with version 1.1 of PM8916

Headphone amplifier positive supply

Ear and class-D speaker amplifier supply

D12

VDD_AUDIO_IO I/O supply for codec

C11, C12

VDD_CP Charge pump power supply

Table 2-10 Pin descriptions – grounds

Pad #

Pad name


PM88916

A14, B13

GND_BOOST

D6, D7, D10, D11,

E7, E9, G4, G7, G8,

G10, H7, H8, H10,

H11, H12, J6, K5, K9

GND

L13

GND_DRV

D2

GND_REF

A4, B4, C4

GND_S1

A9, B9, C9

GND_S2

N3, P3

GND_S3

N8, P8

GND_S4

J2

GND_XO

J3

GND_RF

N10

GND_XOADC

H3

GND_XO_ISO

Boost ground net

Ground for non-specialized circuits

Ground for vibrator driver

Ground for bandgap reference circuit

Ground for S1 buck converter circuits




Ground for XO circuits

Ground for RF circuits

Ground for XO ADC circuits

Dedicated ground for XO substrate noise isolation

1

Pad N1 and N2 have been combined to same input voltage group from Rev. 2.0.

2

Pads B1, B2 and E1, E2 have been combined to same input voltage group from Rev 2.0.

LM80-P0436-35 Rev. A


22


C13

E14

J13

J12

Pad #

Pad name


GND_CP

GND_SPKR

GND_CFILT

Charge pump ground

Class-D speaker amp ground

Ground reference for PMIC bias

GND_AUDIO_REF Ground reference; connection for audio codec

Pin Definitions

LM80-P0436-35 Rev. A


23

3 Electrical Specifications

3.1 Absolute maximum ratings

Absolute maximum ratings ( Table 3-1 ) reflect conditions that PM8916 may be exposed to outside

of the operating limits, without experiencing immediate functional failure. They are limiting values, to be considered individually when all other parameters are within their specified operating ranges. Functionality and long-term reliability can only be expected within the

operating conditions, as described in Section 3.2

.

Table 3-1 Absolute maximum ratings

Parameter

Power supply and related sense voltages

USB_IN

VDD_xx

VBAT, VBAT_SNS

VDD_CDC_VBAT

VDD_EAR_SPKR

Signal pins


PMIC power-supply voltages not listed elsewhere

Main battery voltage

Steady state

Transient (< 10 ms)

Power for audio codec

Power for ear and speaker driver

V_IN

Voltage on any non-power-supply pin1

ESD protection and thermal conditions – see Section 7.1

.

Min

-0.5

-0.5

-0.5

-0.5

-0.5

-0.5

-0.5

Max

16

6

6

7

6

6

VXX + 0.5

Units

V

V

V

V

V

V

V

1

VXX is the supply voltage associated with the input or output pin to which the test voltage is applied

LM80-P0436-35 Rev. A


24

PM8916/PM8916-1 Device Specification Electrical Specifications

3.2 Operating conditions

Operating conditions include parameters that are under the control of the user: power-supply

voltage and ambient temperature ( Table 3-2 ). The PM8916 meets all performance specifications

listed in Section 3.3

through Section 3.11

when used within the operating conditions, unless

otherwise noted in those sections (provided the absolute maximum ratings have never been exceeded).

Table 3-2 Operating conditions

Parameter

Power supply and related sense voltages

USB_IN

VDD_xx

VBAT, VBAT_SNS

VCOIN

VDD_CDC_VBAT

VDD_EAR_SPKR


PMIC power-supply voltages not listed elsewhere1

Main battery voltage1

Coin cell voltage

Power for audio codec


Signal pins

V_IN

Voltage on any non-power-supply pin1

Thermal conditions

Tc

Operating temperature (case)

Min Typ

4.35

3.0

3.0

–

3.6

3.6

2.0

TBD

3.0

3.7

3.0 3.7/5.0

0

- 30

–

+25

Max

6.2

4.5

4.5

3.25

TBD

5.50

VXX + 0.5

+85

Units

V

°C

V

V

V

V

V

V

1

V

XX

is the supply voltage associated with the input or output pin to which the test voltage is applied.

LM80-P0436-35 Rev. A


25


3.3 DC power consumption

This section specifies DC power supply currents for the various IC operating modes ( Table 3-3 ).

Typical currents are based on IC operation at room temperature (+25°C) using default parameter settings.

Table 3-3 DC power supply currents

IDD active1

1

IDD active2

2

IDD sleep

3

IDD off_ship

4

IDD coin

IDD

CHG

7

IDD

USB

8

Parameter

Supply current, active mode

Supply current, active mode

Supply current, sleep mode

32 kHz sleep clock

Supply current, off mode

Coincell supply current, off mode

XTAL off (IDDcc_xoff)

5

RC calibration (IDDcc_rccal)

6

USB charger supply current

USB charger current in suspend

Comments

Average current

Sleep mode

Good battery, not charging

Min

–

–

–

–

–

–

–

–

Typ

4.2

5.5

290

5

2

5

13.3

–

Max Units

6

7.5

450 mA mA

µA

18

2.5

8

15

1.65

µA

µA

µA mA mA

Table 3-4 Audio power supply peak current

VDD_EAR_SPKR

Parameter


Min

–

Typ

–

Max

1.0

Units

A

1

IDDacti ve1 is the total supply current from a main battery with PM8916 on, crystal oscillators on, XO and

BBCLK1 on at 19.2 MHz, driving no load, and these voltage regulators on with no load at the following:

VREG_S1 = 1.15 V, VREG_S2 = 1.15 V, VREG_S3 = 1.35 V, VREG_S4 = 2.15 V, VREG_L2 = 1.2 V,

VREG_L3 = 1.15 V,VREG_L5 = 1.8 V, VREG_L7 = 1.8 V, VREG_L8 = 2.9 V, VREG_L11 = VREG_L12 =

2.95 V, VREG_L13 = 3.075 V, MPP1 is on as analog buffer, and VREF_LPDDR is on.

2

IDDacti ve2 is the total supply current from a main battery with PM8916 on and

IDDactiv e1 condition plus:

VREG_L1 = 1.225 V, VREG_L4 = 2.05 V, VREG_L6 = 1.8 V, VREG_L14 = 1.8 V, VREG_L17 = 2.85 V,

VREG_RFCLK and RFCLK1 on.

3

IDDsl eep is the total supply current from a main battery with PM8916 on, crystal oscillators on and these voltage regulators on with no load at the following: VREG_S1 = 1.15 V (PFM), VREG_S3 (PFM) = 1.35

V,VREG_S4 (PFM) = 2.15 V, VREG_L2 (LPM) = 1.2 V, VREG_L3 (LPM) = 1.15 V, VREG_L5 (LPM) = 1.8

V, and VREF_LPDDR is on.

4

Total supply current from a main battery with PM8916 off and the 32 kHz crystal oscillator on. This only applies when the temperature is between -30°C and 60°C.

5

IDDcc_x off is the total supply current from a 3.0 V coin cell with PM8916 off and the 32 kHz crystal oscillator off. This only applies when the temperature is between -30°C and 60°C.

6

IDDcc_rc cal is the total supply current from a 3.0 V coin cell with PM8916 off, the 32 kHz crystal oscillator off and RCCAL enabled with nominal settings. This only applies when the temperature is between -30°C and

60°C.

7

5CHG is the total supply current from a charger, with the device configured into the sleep mode as specified in Note 2 above with USB_IN = 6 V and VMAXSEL setting = 4.2 V.

8

IDDU

SB is the total supply current drawn from a USB charger when the phone has a good battery

(> 3.2 V), and the phone is not drawing charging current from USB. When USB is suspended, the phone is not allowed to draw more than 2.5 mA from a PC. Specification allows for 850 µA current into external components connected to VBUS in this case.

LM80-P0436-35 Rev. A


26


3.4 Digital logic characteristics

PM8916 digital I/O characteristics such as voltage levels, current levels, and capacitance are

specified in Table 3-5 .

Table 3-5 Digital I/O characteristics

V

IH

V

IL

V

SHYS

I

L

V

OH

V

OL

I

OH

I

OL

I

OH_XO

I

OL_XO

C

IN

Parameter Comments

High-level input voltage

1

Low-level input voltage

Schmitt hysteresis voltage

Input leakage current

3

V

IO

= max, V

IN

= 0 V to V

IO

High-level output voltage

Low-level output voltage

I out

= I

OH

I out

= I

OL

High-level output current

4

V out

= V

OH

Low-level output current

4

V out

= V

OL

High-level output current

4

XO digital clock outputs only

Low-level output current

4

Input capacitance

5

XO digital clock outputs only

Min Typ Max

0.65 × V

IO

–

-0.3

15

V

IO

+ 0.3

2

– 0.35 × V

IO

2

– –

-200

V

IO –

0.5

0

3

–

–

–

–

+ 200

V

IO

0.45

–

–

6

–

–

–

–

–

–

-3

–

-6

5

Units

V

V mA mA mA

V

V mV nA mA pF

3.5 Input power management

All parameters associated with input power management functions are specified.

3.5.1 Over-voltage protection

PM8916 has power FET and charging current sensing feature. After the OVP/UVD comparators detect a valid charging source, the power FET driver is enabled. The USB_IN voltage is monitored by the OVP comparator with a threshold voltage of 6.2 V. When USB_IN exceeds this threshold, the comparator outputs a logic signal to turn off the power FET driver, which turns off the power FET within 1

µs.

3.5.2 External supply detection

The PMIC continually monitors the external supply voltages like USB_IN and the battery supply voltage VBAT. Internal detector circuits measure these voltages to recognize when an external supply is connected or removed, and verify that it is within its valid range when connected.

Hysteresis prevents undesired switching near the thresholds, and status is reported to the on-chip state machine and to the host IC via interrupts.

1

VIO is the supply voltage for the APQ/PMIC interface (most PMIC digital I/Os).

2

MPP and GPIO pins comply with the input leakage specification only when configured as digital inputs, or set to their tristate mode.

3

Output current specifications apply to all digital outputs unless specified otherwise, and are superseded by specifications for specific pins (such as MPP and GPIO pins.

4

Input capacitance is guaranteed by design, but is not 100% tested.

5

V

IO = VREG_L5.

LM80-P0436-35 Rev. A


27


Performance specifications related to detecting external supply voltages and protecting the PMIC are presented in future revisions of this document.

For a valid USB detection and PON trigger to happen, USB_IN voltage must be greater than under-voltage detection (UVD) and less than over-voltage detection (OVD) threshold.

Table 3-6 External source interface performance specifications

Comments Parameter

Negative voltage protection

V_NEG

Negative input voltage

UVD

V(thr_coarse)

V(thr_uvd_r)

V(hyst_uvd)

OVD

1

Coarse detect threshold

UVD threshold

UVD threshold hysteresis

V(thr_ovd_r)

V(hyst_ovd) t(db_ovd_r) t(db_ovd_f)

R(ovp_fet_on)

OVD setting

OVD threshold hysteresis

OVD debounce

OVD debounce

OVP FET Rds(on)

2

Recommended OVP output (LBC input)

USB_IN

Charger input voltage

3

V

IN_MIN

Charge current accuracy

Input voltage limit programmable range

Input voltage limit accuracy

USB_IN

USB_IN – rising

USB_IN – rising

USB_IN

USB_IN – rising

USB_IN – falling

USB_IN – rising

USB_IN – falling

USB_IN = 5 V

26.2 mV steps

Min

-0.3

1.0

150

6.0

150

–

–

–

4.35

-10

4.229

-3

Typ

–

1.7

4.0

200

–

6.2

200

1.0

0

220

Max Units

–

2.0

250

6.4

250

–

300

6.5

+10

5.0652

3

V

V

V mV

V mV

µs ms m

Ω

V

%

V

%

1

Meets the 4.4 V VBUS minimum from an unloaded bus-powered hub as specified in the USB 2.0 specification.

2

USB OVP FET on, USB_IN voltage jumps from 10 V to 15 V in 20 μs.

3

This is the recommended operating range. The acceptable operating range is defined by the UVD and OVD thresholds specified elsewhere in this table.

LM80-P0436-35 Rev. A


28


3.5.3 Linear battery charger

3.5.3.1 LBC specifications

Table 3-7 Linear charger specifications

Parameter

Battery/VDD voltage programmable range

Battery/VDD voltage accuracy

(Including line & load regulation and temperature variation – up to 150 mA load)

Charge current programmable range

Charge current accuracy

FET resistance from USBIN to VBAT

VBATDET comparator threshold accuracy

Battery charge termination current

I

BAT_MAX

: 90–450 mA

I

BAT_MAX

: 540–1440 mA

IBAT_TERM accuracy

I

BAT_MAX

= 90 mA

I

BAT_MAX

: 180–450 mA

I

BAT_MAX

: 540–810 mA

I

BAT_MAX

: 900–1440 mA

Min

4.0

-1

90

-10

-2

-3

-7

-20

-15

Typ

4.20

Max

4.775

1

Unit

V

Note

25 mV steps

%

332

7

7.4

1440

+10

420

2

+7

+7

+20

+15 mA 90 mA steps

% m

Ω

%

% mA mA

%

%

3.5.3.2 Charging-specific linear charger specifications

Battery charging is controlled by a PMIC state-machine. The first step in the automated charging process determines if trickle charging is needed. Charging of a severely depleted battery must

begin with trickle charging ( Table 3-8 ) to limit the current, avoid pulling VDD down, and protect

the battery from more charging current than it can handle. Once a minimum battery voltage is established using trickle charging, constant-current charging is enabled to charge the battery quickly – this mode is sometimes called fast charging. Once the battery approaches its target voltage, the charge is completed using constant-voltage charging.

Table 3-8 Trickle charging performance specifications

Parameter

Trickle charge – current

Trickle charge – current accuracy

Trickle voltage – threshold programmable range

Trickle voltage – threshold accuracy

Trickle voltage – threshold hysteresis

Trickle voltage – threshold debounce

Comments

15.62 mV steps, 2.796 V default

VBAT falling

VBAT rising

VBAT falling

Min

81

2.5

Typ Max

90

±10%

–

99

2.9842

-2

50

–

–

–

90

2

1

+2

130

–

–

Units

mA

V

% mV sec ms

LM80-P0436-35 Rev. A


29


Parameter

System weak – threshold programmable range

System weak – threshold accuracy

System weak – threshold falling hysteresis

System weak – threshold debounce

Comments

18.75 mV steps; 3.2 V default

Detect depleted battery

VBAT falling

VBAT rising/falling

Min

3.0

Typ Max

3.206 3.581

-2

70

–

–

110

1

+2

150

–

Constant-current charging

The PMIC parameters associated with constant-current charging are specified in the following subsections:





External supply detection

Battery voltage monitoring system

Section 3.5.2

Section 3.5.4

Additional performance specifications for constant-current charging are not required.

Constant-voltage charging

The PMIC parameters associated with constant-voltage charging are specified in the following subsections:





External supply detection

Battery voltage monitoring system

Section 3.5.2

Section 3.5.4

Additional performance specifications for constant-voltage charging are not required.

Units

V

% mV ms

LM80-P0436-35 Rev. A


30


Figure 3-1 shows the LBC flowchart.

VPH_PWR_EN 0

à1

For case with

Battery present or NOT present.

VPH_PWR_OK

= 0.

N

V

BAT

> V

BAT_WEAK

?

Y

Power-On from

Charger

I

BAT_MAX

= 1440mA

Corner Case: If a dead battery is inserted, it will be charged at a high current (1.44A) for brief time. However the dead battery will cause the

VBAT node to crash and

UVLO the system. The

PON trigger will still be there (Charger attach) and the PMIC will trickle charge the battery.

Power-On from Battery

Charger in

Interface PMIC not being used.

For Factory Test Mode:

No battery and USB cable inserted.

Power-On from

Battery & Charger

I

BAT_MAX

= 450mA

N

OPT1

_PIN = 1?

Y

N

BATT_PRES = 1?

N

Y

USB_Valid ?

Y

ENUM_TIMER_EN =1?

Y

N (default)

Y

V

BAT

>V

BAT_WEAK

?

N

BAT_THM (default)

Or

BAT_ID

Auto Trickle Charge A

I

BAT_MAX

= 90mA

V

BAT

rises to V

BAT_TRKL

Auto Trickle Charge B

I

BAT_MAX

= 90mA

(Enum Timer Expired)

I

BAT_MAX

= 450/990mA

V

BAT

rises to V

BAT_WEAK

Power-On from Battery & Charger

I

BAT_MAX

= 90mA

(Enum Timer Expired)

I

BAT_MAX

= 450/990mA

↑ HW-controlled charging

Legend:

Charger

Hardware

Charger

Software

Shutdown

Phone

Restart PON

Y

N

V

BAT_WEAK

>

V

BAT_WEAK(MAX)

?

Non-charger

Hardware

Non-charger

Software

N

Increase

V

Y (default)

Adaptive

Boot = 1?

Y

N

Boot Timer

Expire?

Enable

Boot Timer

N

Boot Done?

Y

Disable

Boot Timer

VPH_PWR_OK 0

à1

PMIC PON sequence

Turn on VREGs; Turn on Clocks;

PON_RESET_N

Start

Enum Timer

N

System Boot

PS_HOLD = 1;

…

Y

USB?

Set I

BAT_MAX

= 90mA

Charging Port Detection

& Enumeration

>= 500mA?

Y

N

ENUM_TIMER_STOP = 1

…

Enum Timer

Expire?

N

Y

Stop

Enum Timer

BOOT_DONE = 1

Electrical Specifications

Charging SW configuration

Set charging parameters

↓ HW-managed

SW configurable

autonomous charging

V

BAT

> V

BAT_DET

V

BAT

level?

V

BAT_WEAK

< V

BAT

< V

BAT_DET

Fast Charging

CC: I

BAT

= I

BAT_MAX

, V

CV: V

BAT

= V

DD_MAX

, I

BAT rises

BAT

drops

Float Charge

ITERM comparator

N

COMP_EN =1?

Y (default)

I

BAT

drops below I

TERM

(10% of I

BAT_MAX

)

Charging Done

Charger Off

Power-On from Battery

V

BAT

drops below V

BAT_DET

Figure 3-1 LBC flowchart

LM80-P0436-35 Rev. A


31


3.5.4 Battery voltage monitoring system

3.5.4.1 Under-voltage lockout

The handset supply voltage (VDD) is monitored continuously by a circuit that automatically turns off the device at severely low VDD conditions.

UVLO events do not generate interrupts. They are reported to the host IC via the

PON_RESET_N signal. UVLO-related voltage and timing specifications are listed in Table 3-9 .

Table 3-9 UVLO performance specifications

Parameter

Rising threshold voltage

Hysteresis

Falling threshold voltage

UVLO detection interval

Comments

Programmable value, 50 mV steps

175 mV setting

300 mV setting

175 mV hysteresis setting

300 mV hysteresis setting

Min Typ Max Units

1.675 2.725 3.225

125 175 225

250 300 350

1.500 2.550 3.050

1.375 2.425 2.925

– 1 –

V mV mV

V

V

µs

3.5.4.2 SMPL

The PMIC SMPL feature initiates a power-on sequence if the monitored VDD drops out of range and then returns in-range within a programmable interval. When enabled by software, SMPL achieves immediate and automatic recovery from momentary power loss (such as a brief battery disconnect when the device is jarred).

SMPL performance specifications are given in Table 3-10 .

Table 3-10 SMPL performance specifications

Parameter

Minimum SMPL interval

Comments

Programmable range

Min

0.5

Typ

–

Max Units

2 s

3.5.5 Voltage mode battery monitoring system (VM-BMS)

Table 3-11 Battery fuel-gauge specifications

Parameter

Effective number of bits (ENOB) of battery-voltage measurement

OCV measurement

Comments

Accuracy

Repeatability (with charger attached)

Min

–

-15

-3

Typ

13

–

–

Max Units

– bits

15

3 mV mV

LM80-P0436-35 Rev. A


32


Table 3-12 State of charge (SOC) specifications


SOC accuracy at power on

Battery capacity > 80% or < 20%)

Battery capacity between 20% and

80%

SOC accuracy immediately after powering on with settled battery with capacity > 80% or < 20%

SOC accuracy immediately after powering on with settled battery, with capacity between 20% and

80%

SOC accuracy after power on

Battery capacity > 80% or < 20%)

SOC accuracy at any time during a charge or discharge cycle after powering on with settled battery with capacity > 80% or < 20%

Battery capacity between 20% and

80%

Battery capacity 0% to 100%

SOC accuracy at any time during a charge or discharge cycle after powering on with settled battery, with capacity between 20% and

80%

Average SoC accuracy over complete charge/discharge cycle

Typ

±0.5

±3

–

–

5

Max

1

±3

±15

±15

±25

–


Units

%

%

%

%

%

3.5.6 Battery interface parameters (BTM and BPD)

The PMIC interface with the battery enables battery-temperature monitoring (BTM) and battery-

presence detection (BPD); pertinent performance specifications are given in Table 3-13 .

If BAT_ID is not used, that pin can be grounded. If BAT_THERM is not used, it too can be grounded, and the software’s battery temperature feature must be disabled. If external charger is used, then BAT_THERM should be grounded.

Table 3-13 Battery interface specifications

Typ Max Units Parameter Comments

Battery-temperature monitoring (BTM)

Cold-comparator threshold programmable settings

Cold-comparator offset

Cold-comparator voltage hysteresis

70% setting

80% setting

Cold-comparator debounce

Fraction of VREF_BAT_THM; selectable as 70% or 80%

VREF_BAT_THM falling

(battery warming)

VBAT_THM rising

VBAT_THM falling

Hot-comparator threshold programmable settings Fraction of VREF_BAT_THM; selectable as 25% or 35%

Hot-comparator offset

1

Valid over a temperature range of -20°C to 70°C.

Min

70

-10

-80

-70

0.5

0.5

25

-10

–

–

–

–

–

–

–

–

80

+10

-40

-35

2.5

2.5

35

+10

% mV mV mV mV ms s

%

LM80-P0436-35 Rev. A


33


Parameter

Hot-comparator voltage hysteresis

35% setting

25% setting

Hot-comparator debounce

Battery-presence detection (BPD)

BPD-comparator threshold

BPD-comparator offset

BPD-comparator debounce

VREF_BAT_THM rising (battery removal)

VREF_BAT_THM falling (battery insertion)

Comments

VREF_BAT_THM failing

(battery cooling)

VBAT_THM rising

VBAT_THM falling

Min

25

15

0.5

0.5

Typ Max Units

–

–

–

–

50

30

2.5

2.5 mV mV ms s

Fraction of VREF_BAT_THM –

-50

1

–

95

–

–

2

–

+50

6

–

% mV

µs s

Figure 3-2

shows the BTM block diagram, and Table 3-14 lists the equations for calculating the

R s1 and R s2 external resistors needed to support the BTM feature.

SPMI_EN

CHG_EN

ADC_EN

On-chip 1.875 V aVdd

EN

VREG_L6

1.8 V

VREG

_OK

VREF_BAT_THM

SPMI

HK/XO

ADC

BAT_ID_GONE

BAT_THERM

BAT_ID

R_S1

R_S2

1% resistors

Rth

Rid

Battery pack

BAT_GONE

Battery

Presence

Detection

BAT_THM_GONE

95%

BAT_COLD

BAT_HOT

Battery

Temperature

Monitor

Figure 3-2 Battery-temperature monitoring

80%

70%

35%

25%

LM80-P0436-35 Rev. A


34


Table 3-14 Battery-temperature monitoring calculations

Battery charging window BTM comparator thresholds

0 to 40 or 45ºC

-10 to 60ºC

70% to 35%

80% to 25%

Minimum resistor values

R_S1 = 39 × (R_cold – R_hot) / 70

R_S2 = (3 × R_cold –13×R_hot) / 10

R_S1 = 3 × (R_cold – R_hot) / 11

R_S2 = (R_cold – 12 × R_hot) / 11

3.5.7 Coin cell charging

Coin cell charging is enabled through software control and powered from VBAT. The on-chip charger is implemented using a programmable voltage source and a programmable series resistor.

The host IC reads the coin cell voltage through the PMIC’s analog multiplexer to monitor

charging. Coin cell charging performance is specified in Table 3-15 .

Table 3-15 Coin cell charging performance specifications

Parameter

Target regulator voltage

Target series resistance

Coin cell charger voltage error

Coin cell charger resistor error

Dropout voltage

1

Ground current, charger enabled

VBAT = 3.6 V, T = 27ºC

VBAT = 2.5 to 5.5 V

Comments

VIN > 3.3 V, ICHG = 100 µA

ICHG = 0 µA

ICHG = 2 mA

PMIC = off; VCOIN = open

Min

2.5

800

-5

-20

–

–

–

Typ

3.1

–

–

–

–

4.5

–

Max Units

3.2

2100

5

20

200

–

8

V



%

% mV

µA

µA

3.6 Output power management

Output power management circuits include:



Bandgap voltage reference circuit



Buck SMPS circuits



LDO linear regulators

The PM8916 provides all the regulated voltages needed for most wireless handset applications.

Independent regulated power sources are required for various electronic functions to avoid signal corruption between diverse circuits, support power-management sequencing, and to meet different voltage-level requirements.

A total of 24 programmable voltage regulators are provided by the PM8916, with all outputs derived from a common bandgap reference circuit. Each regulator can be set to a low-power mode for power savings.

A high-level summary of all regulators and their intended uses is presented in Table 3-16 .

1

Set the input voltage (VBAT) to 3.5 V. Note the charger output voltage; call this value V

0

. Decrease the input voltage until the regulated output voltage (V

1

) drops 100 mV (V

1

= V

0

– 0.1 V). The voltage drop across the regulator under this condition is the dropout voltage (V dropout

= VBAT – V

1

).

LM80-P0436-35 Rev. A


35


Table 3-16 Regulator high-level summary

Function

S1

Circuit type

SMPS

Default voltage (V) with

P code = 0

1

1.15


P code = 11

1.225

Programmable range (V)

0.375–1.562

Specified range (V)

0.5–1.35

Rated current

2

(mA)

Default on

2500 Y

Expected use

APQ8016/APQ8009 camera SS, graphics core, etc.

S2

SMPS 1.15 1.225 0.375–1.562 0.9–1.35 3000 Y APQ8016/APQ8009application processor cores

S3

S4

L1

L2

L3

L4

L5

L6

SMPS

SMPS

NMOS LDO

NMOS LDO

NMOS LDO

PMOS LDO

PMOS LDO

PMOS LDO

1.35

2.1

1.2875

1.2

1.15

2.05

1.8

1.8

1.35

2.05

1.0

1.2

1.225

1.8

1.8

1.8

0.375–1.562

1.55–2.325

1.25–1.35

1.85–2.15

0.375–1.525

0.375–1.525

1.0–1.2875

1.2

0.375–1.525

1.75–3.337

1.75–3.337

1.75–3.337

0.65–1.35

1.8–2.1

1.8

1.8

1800

1500

250

600

350

250

200

150

Y

Y

Y

N

Y

Y

N

Y

Analog blocks of WAN, WLAN, source for GR1 (LDOs

L1 and L3) and GR2 (LDO L2) rails

Codec analog and source for GR3 (LDOs L4, L5 & L6) and GR7 (LDO L7) rails

Low voltage rail

Memory (EBI/LPDDR2/LPDDR3/eMMC) and MIPI analog rails

Host IC

GPS eLNA

Codec and memory 1.8 V rails, WLAN IO

Camera, display and transducer 1.8 V rails and HK ADC

L7

PMOS LDO 1.8 1.8 1.75–3.337 1.8–1.9 110 Y Host, BB_CLK driver

1

Default voltages and power-on states may depend on option pin (OPT_x) or SBL settings.

2

Since PM8916 has wire bond package, rated current of the LDOs will be less than the design specification. For example, although L1 is N1200 LDO type which is designed for 1.2 A, its rated current is limited to 250 mA mainly due to losses in the bond wire.

LM80-P0436-35 Rev. A


36


L8

L9

L10

L11

L12

Function

Circuit type

PMOS LDO

PMOS LDO

PMOS LDO

PMOS LDO

PMOS LDO


P code = 0

1

2.9


P code = 11

2.9

Programmable range (V)

1.75–3.337

Specified range (V)

2.9

3.3 3.3 1.75–3.337 3.3

2.8

2.95

2.95

2.8

2.95

2.95

1.75–3.337

1.75–3.337

1.75–3.337

2.8

2.95

1.8/2.95

Rated current

2

(mA)

Default on

400

600

150

8001

50

Y

N

N

Y

Y

Expected use

eMMC/NAND core

Connectivity IC (WCN3620/WCN3660)

Camera (Front and Rear) analog rails

SD/MMC card

APQ8016/APQ8009 memory rail for SD

L13

L14

PMOS LDO

PMOS LDO

L15

PMOS LDO

L16

L17

PMOS LDO

PMOS LDO

L18

VREF_LPD

DR

MPP1

PMOS LDO

—

—

VREG_XO Low noise LDO

3.075

1.8

1.8

1.8

2.85

2.7

0.6125

1.250

1.8

3.075

1.8

1.8

1.8

2.85

2.7

0.6125

1.250

1.8

1.75–3.337

1.75–3.337

1.75–3.337

1.75–3.337

1.75–3.337

1.75–3.337

—

—

1.38–2.22

3.075

1.8/3.3

1.8/3.3

1.8/3.3

2.85

2.7

—

—

1.8

50

55

55

55

450

150

5

Y

N

N

N

N

N

Y

Y

Codec and USB 3 V analog rails

UIM 1

UIM 2

UIM 3

LCD, transducers and camera 2.85 V rails

Qualcomm RF360™

LPDDR reference

APQ pad bias

XO oscillator circuits

VREG_RF

CLK

Low noise LDO 1.8 1.8 1.38–2.22 1.8 5 Low noise clock buffers

1

LDO L11 would be able to provide current of 800 mA to support SDR104 mode. The regulation specification of 3% would not be met. Since minimum voltage needed at SD card is only 2.7 V, accuracy of 8.4% will be sufficient. The LDO L11 can provide current of 600 mA meeting all regulation specification.

LM80-P0436-35 Rev. A


37


3.6.1 Reference circuit

All PMIC regulator circuits and some other internal circuits are driven by a common, on-chip voltage reference circuit. An on-chip series resistor supplements an off-chip 0.1 µF bypass capacitor at the REF_BYP pin to create a low-pass function that filters the reference voltage distributed throughout the device.

NOTE:

Do not load the REF_BYP pin. Use an odd MPP configured as an analog output if the reference voltage is needed off-chip.

Applicable voltage-reference performance specifications are given in Table 3-17 .

Table 3-17 Voltage-reference performance specifications

Parameter

Nominal internal VREF

At REF_BYP pin

Comments Min

–

Typ

1.250

Max Units

– V

Output voltage deviations

Normal operation

Normal operation

Sleep mode

Over-temperature only, -20 to +120ºC

All operating conditions

All operating conditions

-0.32

-0.50

-1.0

–

–

–

+0.32

+0.50

+1.0

%

%

%

3.6.2 Buck SMPS

The buck converter is a switched-mode power supply that provides an output voltage lower than its input voltage, and is therefore also known as a step-down converter. The PM8916 IC includes four SMPS. The SMPS bucks support PWM and PFM modes.

Pertinent performance specification is given in Table 3-18 .

LM80-P0436-35 Rev. A


38


Table 3-18 SMPS performance specifications

Parameter

Input voltage range

Output voltage ranges

Programmable range

Comments

25 mV steps

12.5 mV steps

Continuous current delivery

Min

3

TBD

TBD

Typ Max Units

–

–

4.5

TBD

TBD

V

V

V

Rated load current (I_rated)

PWM mode

S1

S2

S3

S4

PFM mode

Peak current limit (through inductor)

Voltage error

PWM mode

PFM mode

Overall error (includes voltage error, load and line regulation and errors due to temperature and process)

PWM mode

PFM mode

Temperature coefficient

Efficiency

PWM mode

PFM mode

Enable settling time

Enable overshoot

Voltage step settling time per LSB

Response to load transitions

Dip due to low-to-high load

Spike due to high-to-low load

V

IN

= 3.0 V

V

IN

= 3.2 V

V

IN

= 3.4 V

V

IN

= 3.0 V

V

IN

= 3.2 V

V

IN

= 3.4 V

V

IN

= 3.0 V

V

IN

= 3.2 V

V

IN

= 3.4 V

V

IN

= 3.0 V

V

IN

= 3.2 V

V

IN

= 3.4 V

Programmable

VREG pin shorted; current limit is set via SPMI programming.

V_out > 1.0 V, I_rated / 2

V_out < 1.0 V, I_rated / 2

V_out > 1.0 V, I_rated / 2

V_out < 1.0 V, I_rated / 2

V_out > 1.0 V, I_rated /2

V_out < 1.0 V, I_rated /2

V_out > 1.0 V, I_rated /2

V_out < 1.0 V, I_rated /2

VBAT 3.6 V

V_out = 1.8 V, I_load = 300 mA

V_out = 1.8 V, I_load = 10 to 600 mA



From enable to within 1% of final value programmable in PBS

V_out > 1.0 V, no load

V_out < 1.0 V, no load

To within 1% of final value

PWM mode

S1, S3, S4: 40 mA to 440 mA

S2: 40 mA to 1040 mA

S1, S3, S4: 440 mA to 40 mA

S2: 1040 mA to 40 mA

–

–

–

–

-1

-10

-3

-30

-2

-20

-5

-50

-100

–

–

–

–

1.5

2.0

2.5

2.0

2.2

3.0

1.0

1.2

1.8

0.8

1.0

1.5

80

70% *

I_limit

–

–

–

–

–

TBD

TBD

TBD

TBD

500

–

–

40

70

–

–

–

–

–

–

–

–

–

–

–

–

I_limit 130%

*

I_limit

–

–

–

–

1

10

3

30

–

–

–

–

–

–

–

–

–

–

–

–

–

–

3

30

10

A mA mA

% mV

% mV

–

–

–

–

2

20

5

50

% mV

% mV

100 ppm/C

%

%

%

%

µs

% mV

µs mV mV

LM80-P0436-35 Rev. A


39


Parameter Comments Min

Line transient response

Output ripple voltage

PWM pulse-skipping mode

PWM non-pulse-skipping mode

PFM mode

Load regulation

Using 3.6 V to 3.0 V square waveform with 10 µs rise/fall time and frequency of 217 Hz, I_load = 750 mA

Tested at the switching frequency;

Cap ESR < 20 m

Ω

40 mA load; 20 MHz measurement bandwidth

I_rated; 20 MHz measurement bandwidth

50 mA load; 20 MHz measurement bandwidth

V_in

≥ V_out + 1 V;

I_load = 0.05 * I_rated to I_rated

–

V_in = 3.2 V to 4.2 V; I_load = 100 mA –

–

–

–

Line regulation

Power-supply ripple rejection (PSRR)

50 Hz to 1 kHz

1 kHz to 100 kHz

100 kHz to 1 MHz

VREF = 0.625 V

Output noise

F < 5 kHz

F = 5 kHz to 10 kHz

F = 10 kHz to 500 kHz

F = 500 kHz to 1 MHz

F > 1 MHz

–

–

–

–

–

–

–

–

–

Peak output impedance vs frequency 1 kHz–1 MHz

Ground current

PWM mode, no load

PFM mode, no load

PFM mode, no load (with current boost)

–

–

–

Typ

8

20

10

50

Max

40

20

70

Units

mV mVpp mVpp mVpp

0.25 – %

0.25

40

20

30

-101

-106

-106

-116

-116

150

550

20

30

–

–

–

–

–

–

–

–

–

–

750

30

45

%/V dB dB dB dBm/Hz dBm/Hz dBm/Hz dBm/Hz dBm/Hz m

Ω

µA

µA

µA

3.6.2.1 Efficiency plots

Figure 3-3

through Figure 3-6 show the efficiency plots for V

in

= 3.7 V.

S1 PFM Efficiency

90

85

80

75

70

65

60 i e

55

50

45

40

0.0001

( %

0.001

Load (A)

0.01

0.1

100

90

80

70 f f i c i e

60

50

40

0.01

( %

S1 PWM Efficiency

0.1

Load (A)

1

Figure 3-3 S1 PFM efficiency plots

LM80-P0436-35 Rev. A


40






LM80-P0436-35 Rev. A


41


3.6.3 Linear regulators

20 low dropout linear regulator designs are implemented within the PMIC:



3 NMOS LDOs



15 PMOS LDOs



PMOS for on-chip clock circuits

 These LDOs are not used off-chip, so their performance specifications are not published.

All other LDO performance specifications are presented in Table 3-19 .

Table 3-19 LDO performance specifications

Parameter

Output voltage ranges

Programmable range

All NMOS

All PMOS

L6

L7

L8

L9

L10

L11

L12

L13

Rated load current (I_rated), normal

L1

L2

L3

L4

L5

L14

L15

L16

L17

L18

Rated load current, low-power mode

L1, L2

L3

L4 – L13, L17, L18

L14 – L16

Pass FET power dissipation

Comments

12.5 mV steps

12.5 mV steps



Typ

–

–

–

–

–

–

–

–

–

–

–

–

–

–

–

–

–

–

–

–

–

–

–

–

–

Min

0.375

1.75

–

–

–

–

–

–

–

–

–

–

–

–

–

–

–

–

–

–

–

–

–

–

–

Max Units

1.525

3.337

250

600

350

250

200

150

110

400

600

150

800

1

50

50

55

55

55

450

150

V

V mA mA mA mA mA mA mA mA mA mA mA mA mA mA mA mA mA mA

100

60

10

5

600 mA mA mA mA mW

1

For LDO L11 alone, overall error is specified for a load of 0-400 mA instead of its rated current.

LM80-P0436-35 Rev. A


42


Parameter

Overall error at default voltage

(includes DC voltage error, load

1

and line regulations and errors due to temperature and process)

Normal mode

Low-power mode


Transient settling time

Comments

To within 1% of final value

Transient over/under-shoot

Normal mode

All NMOS LDOs

All PMOS LDOs

0.25 * I_rated to 0.75 * I_rated load step

0.1 * I_rated to 0.9 * I_rated load step

NPM, I_load = I_rated

Normal dropout voltage

2 3

L1, L3

L2, L4

L5, L6, L7

L8, L11

L9

L10

L12, L13, L14, L15, L16

L17

L18

All NMOS LDOs

All PMOS LDOs

LPM, I_load = I_rated

-100

20

-4

-70

Min

-3

-4

–

100

–

–

Typ

–

–

Max Units

3

4

%

%

100 ppm°C

200 µs

4

100

% mV

–

–

–

–

–

–

–

–

–

–

–

–

–

–

–

–

–

–

–

–

–

–

62.5

150

250

450

275

600

325

550

700

15

300 mV mV mV

1

LDO voltage dropout measurement:

• Program the LDO for its desired operating voltage (V_set_d).

• Measure the output voltage; call this value V_set_m.

• Adjust the load such that the LDO delivers its rated output current (I_rated).

• Adjust the input voltage until V_in = V_set_m + 0.5 V.

• Decrease V_in until V_out drops 100 mV (until V_out = V_set_m – 0.1 V); call the resulting input value

V_in_do and call this output value V_out_do.

• The voltage drop across the regulator under this condition is the dropout voltage (V_do = V_in_do –

V_out_do).

3

The dropout voltage is specified at rated current of the LDO. The voltage headroom required to maintain the LDO in regulation depends on the load current of the LDO. The current that an LDO can provide needs to be derated based on the headroom. Typical example, the LDO L5 has a dropout voltage of 250 mV.

When headroom is 75 mV, the PMOS LDO can provide 200 * (75/250) = 60 mA current without going out of regulation.

2

If a short is anticipated at the output of any of the LDOs, additional current protection circuits should be added. Alternatively, an external LDO with short circuit protection in lieu of PM8916 internal LDO should be used.

3

LDO L11 would be able to provide current of 800 mA to support SDR104 mode. The regulation specification of 3% would not be met. Since minimum voltage needed at SD card is only 2.7 V, accuracy of

8.4% will be sufficient. The LDO L11 can provide current of 600 mA meeting all regulation specifications.

LM80-P0436-35 Rev. A


43


Parameter

Load regulation

Normal mode, all LDOs except L11

Normal mode, L11

Comments

V_in > V_out + 0.5 V;

0.01 * I_rated to I_rated

6 mA to 600 mA

Line regulation

Normal mode

Power-supply ripple rejection

Normal mode

50 Hz to 1 kHz

1 kHz to 10 kHz

10 kHz to 100 kHz

100 kHz to 1 MHz

50 Hz to 1 kHz

1 kHz to 10 kHz

10 kHz to 100 kHz

100 kHz to 1 MHz

Low-power mode

50 Hz to 1 kHz

1 kHz to 100 kHz

Short-circuit current limiting

1

Soft current limit during startup

Ground current

Normal mode, no load

All NMOS

All PMOS

Low-power mode, no load

All NMOS

All PMOS LDOs

Bypass mode

All NMOS LDOs

All PMOS LDOs

Bypass mode on-resistance

L1 & L2

L3

L4

L6

L7, L10, L12, L18

L8, L9, L11, L17

L13, L16

All NMOS LDOs

All PMOS LDOs

All NMOS LDOs

Current above I_rated


Min

–

–

Typ

–

–

Max Units

2.1

2.1

%

%

– – 0.75 %/V

–

–

–

–

–

–

–

–

–

13

13

50

40

70

60

40

30

43

35

–

–

–

–

–

–

–

–

–

–

–

–

–

–

–

–

–

–

–

–

–

–

Not present for any of the LDOs.

– I_rated

+ 150

10

–

20

30

0.75

75

35

12

5

1.1

2.2

0.56

6.6

– mA

13

1

40

60

1.15

100

60

15

6.5

1.66

2.4

0.84

10

µA

µA m  m 











µA

µA

µA

µA dB dB dB dB dB dB dB dB dB dB

1

For LDO L11 alone, overall error is specified for a load of 0-400 mA instead of its rated current.

LM80-P0436-35 Rev. A


44


3.6.4 Internal voltage-regulator connections

Some regulator supply voltages and/or outputs are connected internally to power other PMIC circuits. These circuits will not operate properly unless their supplies are correct; this requires:



Certain regulator supply voltages must be delivered at the right value.



Corresponding regulator sources must be enabled and set to the proper voltages.

These requirements are summarized in Table 3-20 .

Table 3-20 Internal voltage regulator connections

GPIO

MPP

Clocks

Feature

Regulator/

Connection

VPH_PWR

1

VREG_L2

VREG_L5

VPH_PWR

VREG_L2

VREG_L5

VREG_L5

VREG_XO

VREG_RFCLK

VREG_L7

Default V

3.6

1.2

1.8

3.6

1.2

1.8

1.8

1.8

1.8

1.8

SPMI

AMUX

BMS

VREG_L5 max{VBAT,

USB_IN}

VREG_L6

1.8

–

1.8

Comments

Available supplies for GPIO

Available supplies for MPP

Sleep clock pad (Vio)

XO core

Low-noise output buffers (RF_CLKx)

Low-power output buffers (BB_CLKx)

The BB_CLKx buffer supply L7 is forced on by

BB_CLKx_EN.

SPMI pad (Vio)

VADC (AMUX + XOADC) supply

Miscellaneous

VREG_L5 1.8

BMS VADC supply

L6 is forced on by BMS for OCV measurement.

Table 3-21 Boost specifications

Parameter Test conditions

Boost efficiency

Absolute voltage accuracy


3.7 V input, 2.2 µH inductor,

600 mA load

3.7 V input, 2.2 µH inductor,

900 mA load

CCM at 5.5 V

600 mA load current

Overshoot

Regulator turn on/off, load off, voltage step

6 mA to 600 mA current step

Voltage dip due to transient

Voltage spike due to transient 600 mA to 6 mA current step

Settling time

Min

84

80

-3

-100

–

–

–

–

Typ

88

87

0

–

5

340

300

–

Max

–

–

3

100

9

500

500

200

Units

%

%

% ppm/°C

% mV mV

µs

1

GPIO_1 and GPIO_2 do not support VPH_PWR domain.

LM80-P0436-35 Rev. A


45


Parameter

Load regulation

Line regulation

Zero-load Idle current

Boost output ripple

Boost output voltage

Boost output voltage step

Boost output current

Test conditions

Vin < Vout + 1 V with load from

Irated/100 to Irated

600 mA load current

600 mA load, 20 µF capacitor,

1.6 MHz clock rate

8

Ω

4

Ω

Min

–

4.0

4.0

–

–

–

–

–

Typ

–

2

0.5

–

5.0

5.0

50

–

Max

3

2

2

80

5.5

5.0

–

900

Units

%

%/V mA mV

V

V mV mA

3.7 General housekeeping

The PMIC includes many circuits that support handset-level housekeeping functions – various tasks that must be performed to keep the handset in order. Integration of these functions reduces the external parts count and the associated size and cost. Housekeeping functions include an analog switch matrix, multiplexers, and voltage scaling; an HK/XO ADC circuit; system clock circuits; a real-time clock for time and alarm functions; and over-temperature protection.

3.7.1 Analog multiplexer and scaling circuits

A set of analog switches, analog multiplexers, and voltage scaling circuits select and condition a single analog signal for routing to the on-chip HK/XO ADC. The multiplexer and scaling

functions are summarized in Table 3-22 .

Table 3-22 Analog multiplexer and scaling functions

Ch # Description

0

1 to 4

USB_IN pin

RESERVED

5

VCOIN

6

7

VBAT_SNS

VBAT_VPH_PWR

8

9

DIE_TEMP

VREF_0P625

10

11

VREF_1P25

CHG_TEMP

12

13

BUFFERED_VREF_0P625

RESERVED

14

15

GND_REF

VDD_VADC

16

MPP1

17

18

MPP2

MPP3

19

MPP4

20 to 31 RESERVED

Typical input range (V)

0.5–16

–

0.15–3.25

2.5–4.5

0.15–1.8

0.4–0.9

0.625

1.25

0.1–1.7

0.625

–

For calibration

For calibration

0.1–1.7

0.1–1.7

0.1–1.7

0.1–1.7

–

Scaling

1/1

1/1

1/1

1/1

1/1

–

–

1/10

–

1/3

1/3

1/3

–

1/1

1/1

1/1

1/1

–

Typical output range (V)

0.05–1.6

–

0.05–1.08

0.83–1.5

0.05–0.72

0.4–0.9

0.625

1.25

0.1–1.7

0.625

–

–

–

0.1–1.7

0.1–1.7

0.1–1.7

0.1–1.7

–

LM80-P0436-35 Rev. A


46


Ch # Description

32

33

34

35

MPP1

MPP2

MPP3

MPP4

36 to 47 RESERVED

48

BAT_THERM

49

BAT_ID

50

XO_THERM without AMUX buffer

51 to 53 RESERVED

54

PA_THERM

55 to 59 RESERVED

60

XO_THERM through AMUX buffer

1

255

Module power off2

Typical input range (V)

0.3–4.5

0.3–4.5

0.3–4.5

0.3–4.5

–

0.1–1.7

0.1–1.7

0.1–1.7

–

0.1–1.7

–

0.1–1.7

–

Scaling

1/1

1/1

–

1/1

–

1/1

–

1/3

1/3

1/3

1/3

–

1/1

Typical output range (V)

0.1–1.7

0.1–1.7

0.1–1.7

0.1–1.7

–

0.1–1.7

0.1–1.7

0.1–1.7

–

0.1–1.7

–

0.1–1.7

–

NOTE:

Gain and offset errors are different through each analog multiplexer channel. Each path should be calibrated individually over its valid gain and offset settings for best accuracy.

Performance specifications pertaining to the analog multiplexer and its associated circuits are

listed in Table 3-23 .

Table 3-23 Analog multiplexer performance specifications

Parameter

Supply voltage

Output voltage range

Full specification compliance

Degraded accuracy at edges

Comments

3

Connected internally to VREG_L6

Min

–

0.20

0.05

Typ

1.8 V

–

–

Max

–

VL6 – 0.20

VL6 – 0.05

Units

V

V

V

1

These AMUX inputs come from off-chip thermistor circuits.

2

Channel 32 should be selected when the analog multiplexer is not being used; this prevents the scalers from loading the inputs.

3

Multiplexer offset error, gain error, and INL are measured as shown in Figure 3-7 . Supporting comments:

• The nonlinearity curve is exaggerated for illustrative purposes.

• Input and output voltages must stay within the ranges stated in this table; voltages beyond these ranges result in nonlinearity and are beyond specification.

• Offset is determined by measuring the slope of the endpoint line (m) and calculating its Y-intercept value

(b): Offset = b = y1 – m·x1

• Gain error is calculated from the ideal response and the endpoint line as the ratio of their two slopes (in percentage):

Gain_error = [(slope of endpoint line)/(slope of ideal response) – 1]·100%

• INL is the worst-case deviation from the endpoint line. The endpoint line removes the gain and offset errors to isolate nonlinearity:

INLmin = min[Vout (actual at Vx input) – Vout (endpoint line at Vx input)]

INLmax = max[Vout (actual at Vx input) – Vout (endpoint line at Vx input)]

LM80-P0436-35 Rev. A


47


Parameter

Input referred offset errors

Channels with x1 scaling

Channels with 1/3 scaling



Gain errors, including scaling





Integrated nonlinearity (INL)

Input resistance





Channel-to-channel isolation

Output settling time

1

Output noise level f = 1 kHz

C load

= 65 pF f = 1 kHz

Comments

3

Excludes VREG_L8 output error

Input referred to account for scaling

Input referred to account for scaling

Max

+2.0

+1.5

+3.0

+3.0

+0.20

+0.15

+0.30

+0.30

+3

–

–

–

–

–

25

2

Typ

–

–

–

–

–

–

–

–

–

–

–

–

–

–

–

–

Min

-2.0

-1.5

-3.0

-3.0

-0.20

-0.15

-0.30

-0.30

-3

10

1

0.5

0.5

50

–

–

AMUX input to ADC output end-to-end accuracy specifications are listed in Table 3-24 .

Units

mV mV mV mV

%

%

%

% mV

M

Ω

M

Ω

M

Ω

M

Ω dB

µs

µV/Hz

1/2

1

The AMUX output and a typical load are modeled in Figure 3-8 . After S1 closes, the voltage across C2

settles within the specified settling time.

LM80-P0436-35 Rev. A


48


3.7.2 AMUX input to ADC output end-to-end accuracy

Table 3-24 AMUX input to ADC output end-to-end accuracy

AMUX ch #

0

1–4

5

6

7

8

9

10

11

12

13

14–15

16–19

20–31

Function

Typical input range

Min

(V)

Max

(V)

Automatic scaling

Typical output range

Min

(V)

AMUX input to ADC output end-to-end accuracy, RSS

2 , 3

(%) AMUX input to ADC output end-to-end accuracy, WCS

1 , 4

(%)

Max

(V)

Without calibration Internal calibration

Accuracy corresponding to min input voltage

Accuracy corresponding to max input voltage



Without calibration



Internal calibration



Recommended method of calibration

1

,

5 for the channel

USB_IN pin (divided by

10)

VCOIN pin

4.35

–

2

2.5

6.3

–

3.25

4.5 VBAT_SNS pin

VBAT pin

Die-temperature monitor

2.5

0.4

4.5

0.9

0.625 V reference voltage 0.625 0.625

1/10

–

1/3

1/3

1/3

1

1

0.435 0.63

–

0.67

0.83

0.83

0.4

–

1.08

1.5

1.5

0.9

0.625 0.625

4.97

–

3.1

2.64

2.64

4.75

3.27

3.92

–

2.2

1.89

1.89

2.4

3.27

2.38

–

0.7

0.6

0.6

1.0

0.71

2.3

–

0.52

0.47

0.47

1.22

0.71

9.59

–

5.7

5.0

5.0

8.0

5.95

7.92

–

4.37

3.76

3.76

4.7

5.95

3.86

–

1.4

1.24

1.24

2.00

1.47

3.46

–

1.08

0.93

0.93

1.22

1.47

Absolute

1.25 V reference voltage

Charger temperature

VREF_0p625_buf

GND_REF, VDD_ADC

MPP_01 to MPP_04 pin

1.25

0.1

0.625

–

–

0.1

–

1.25

1.7

0.625

–

–

1.7

–

1

1

1

–

–

1

–

1.25

0.1

0.625

–

–

0.1

–

1.25

1.7

0.625

–

–

1.7

–

2.05

18.42

3.27

–

–

18.00

–

2.05

1.79

3.27

–

–

1.76

–

0.5

3.66

0.71

–

–

4.0

–

0.5

0.46

0.71

–

–

0.47

–

4.08

25.64

5.95

–

–

26.00

–

4.08

3.58

5.95

–

–

3.59

–

1.01

6.22

1.47

–

–

6.00

–

1.01

0.9

1.47

–

–

0.88

–

Absolute

Absolute

Absolute

Absolute

Absolute – part of calibration


Absolute


Absolute or ratiometric depending on application

1

Absolute uses 0.625 V and 1.25 V MBG voltage reference as calibration points. Ratiometric uses the GND_XO and VREF_XO_THM as calibration points.

2

XO_THERM to ADC output end-to-end accuracy.

3

The min and max accuracy values correspond to min and max input voltage to the AMUX channel.

4

Accuracy is based on root sum square (RSS) of the individual errors.

5

Accuracy is based on worst-case straight sum (WCS) of all errors.

LM80-P0436-35 Rev. A


49


36–47

48

49

50

51–53

54

55–59

60

AMUX ch #

32–35

255

Function

MPP_01 to MPP_04 pin

BAT_THERM

BAT_ID

XO_THERM pin direct

1

PA THERM

XO_THERM pin through

AMUX

Module power off

Typical input range

Min

(V)

0.3

–

0.1

0.1

0.1

–

0.1

–

0.1

Max

(V)

Automatic scaling

5.1

–

1.7

1.7

1.7

–

2.0

–

1.7

1/3

–

1.0

1.0

1

–

1.0

–

1

–

0.1

0.1

0.1

–

0.1

–

0.1

Typical output range

Min

(V)

0.1

AMUX input to ADC output end-to-end accuracy, RSS

2 , 3

(%) AMUX input to ADC output end-to-end accuracy, WCS

1 , 4

(%)

–

1.7

1.7

1.7

–

1.7

–

1.7

Max

(V)

1.7

Without calibration Internal calibration





Without calibration



Internal calibration



Recommended method of calibration

1

,

5 for the channel

18.33 1.78 3.67 0.45 25.67 3.59 6.33 0.9

–

18.42

18.42

18.42

–

18.42

–

18.42

–

1.79

1.79

1.79

–

1.79

–

1.79

–

3.7

3.7

3.66

–

3.7

–

3.66

–

0.46

0.46

0.46

–

0.46

–

0.46

–

25.64

25.64

25.64

–

25.64

–

25.64

–

3.58

3.58

3.58

–

3.58

–

3.58

–

6.22

6.22

6.22

–

6.22

–

6.22

–

0.9

0.9

0.9

–

0.9

–

0.9

Absolute or

Ratiometric depending on application

Ratiometric

Ratiometric

Ratiometric

Ratiometric

Ratiometric

– – – – – – – – – – – – –

1

XO_THERM to ADC output end-to-end accuracy.

2

The min and max accuracy values correspond to min and max input voltage to the AMUX channel.

3

Accuracy is based on root sum square (RSS) of the individual errors.

4

Accuracy is based on worst-case straight sum (WCS) of all errors.

5

Absolute uses 0.625 V and 1.25 V MBG voltage reference as calibration points. Ratiometric uses the GND_XO and VREF_XO_THM as calibration points.

LM80-P0436-35 Rev. A


50


ideal curve output voltage range

INL(min) endpoint line actual curve

Y-intercept of endpoint line

= offset voltage

Figure 3-7 Multiplexer offset and gain errors

INL(max)

V(in)

Figure 3-8 Analog-multiplexer load condition for settling time specification

LM80-P0436-35 Rev. A


51


3.7.3 HK/XO ADC circuit

The analog-to-digital converter circuit is shared by the housekeeping (HK) and 19.2 MHz crystal oscillator (XO) functions. A 2:1 analog multiplexer selects which source is applied to the ADC:



The HK source – the analog multiplexer output discussed in Section 3.7.1

; or



The XO source – the thermistor network output that estimates the 19.2 MHz crystal temperature.

HK/XO ADC performance specifications are listed in Table 3-25 .

Table 3-25 HK/XO ADC performance specifications

Parameter

Supply voltage

Resolution

Analog input bandwidth

Sample rate

Offset error

Gain error

INL

DNL

Comments

Connected internally to VREG_L6

XO/8

Relative to full-scale

Relative to full-scale

15-bit output

15-bit output

Min

–

-1

-1

-8

-4

–

–

–

Typ Max Units

1.8

–

100

2.4

–

–

–

–

–

15

–

–

1

1

8

4

V bits kHz

MHz

%

%

LSB

LSB

3.7.4 System clocks

The PMIC includes several clock circuits whose outputs are used for general housekeeping functions, and elsewhere within the handset system. These circuits include a 19.2 MHz XO with multiple controllers and buffers, an RC oscillator, and sleep clock outputs. Performance specifications for these functions are presented in the following subsections.

3.7.4.1 19.2 MHz XO circuits

An external crystal is supplemented by on-chip circuits to generate the desired 19.2 MHz reference signal. Using an external thermistor network, the on-chip ADC, and advanced temperature-compensation software, the PMIC eliminates the large and expensive VCTCXO module required by previous-generation chipsets. The XO circuits initialize and maintain valid pulse waveforms and measure time intervals for higher-level handset functions. Multiple controllers manage the XO warmup and signal buffering, and generate the desired clock outputs

(all derived from one source):



Low-noise outputs RF_CLKx – enabled internally or can be enabled via properly configured

GPIOs.



Low-power output BB_CLK1 – enabled by the dedicated control pin BB_CLK1_EN; this output is used as the host IC’s clock signal.



Low-power output BB_CLK2 – enabled internally through SPMI or can be enabled through pin control by properly configuring GPIO2.

Since the different controllers and outputs are independent, circuits other than those needed for the WAN can operate even while the host IC is asleep and its RF circuits are powered down.

LM80-P0436-35 Rev. A


52


The XTAL_19M_IN and XTAL_19M_OUT pins are incapable of driving a load – the oscillator will be significantly disrupted if either pin is externally loaded.

As described in Section 3.7.4.3

, an RC oscillator is used to drive some clock circuits until the XO

source is established.

The 19.2 MHz XO circuit and related performance specifications are listed in Table 3-26 .

Table 3-26 XO controller, buffer, and circuit performance specifications

Parameter Comments Min Typ

XO circuits

Operating frequency

Set by external crystal

Load conditions

Capacitance

Resistance

Startup time

When XO is disabled in mission mode

When XO is disabled in CalRC mode

Supply voltage = VREG_XO

Input buffer and core XO circuits

Power-supply quiescent current

Low-noise outputs: RF_CLKx

Voltage swing

Duty cycle

Buffer output impedance

at 1x drive strength




Phase noise in NPM

at 10 Hz

at 100 Hz

at 1 kHz

at 10 kHz

at 100 kHz

at 1 MHz

Supply = VREG_RFCLK

Output buffers

Low-power outputs: BB_CLKx

Output levels

Logic high (V

OH

)

Logic low (V

OL

)

Output duty cycle

USB jitter

0.5 MHz to 2 MHz

> 2 MHz

Specified values are peak-topeak period jitter.

–

–

1.1

–

–

–

–

0.65 x V

DD

–

44

–

–

1.65

48

40

31

24

17

–

–

–

–

–

–

–

1.8

60

19.2

7.0

–

–

–

–

–

50

–

–

1.8

50

50

38

28

20

-86

-116

-134

-144

-144

-144

1.8

Max

1.95

52

62

50

36

25

–

–

–

–

–

–

–

–

–

–

10.0

20.0

–

–

–

0.35 x V

DD

56

50

100

Units

V

V

% ps ps

Vpp

%

Ω

Ω

Ω

Ω dBc/Hz dBc/Hz dBc/Hz dBc/Hz dBc/Hz dBc/Hz

V

MHz pF k

Ω ms ms

V

µA

LM80-P0436-35 Rev. A


53


Parameter

Buffer output impedance





Supply voltage = VREG_L7

Comments

Current drive capabilities meet the output levels specified above.

Output buffers

Min

40

31

24

17

–

Typ

50

38

28

20

1.8

Max

62

50

36

25

–

Units

Ω

Ω

Ω

Ω

V

3.7.4.2 19.2 MHz XO crystal requirements

Crystal performance is critical to a wireless product’s overall performance. Guidance is available within 19.2 MHz Modem Crystal Qualification Requirements and Approved Suppliers

(80-V9690-19). This document includes:



Data needed from crystal suppliers to demonstrate compliance



Approved suppliers for different crystal configurations



Discussion of various schematic options

3.7.4.3 RC oscillator

The PMIC includes an on-chip RC oscillator that is used during startup, and as a backup to other

oscillators. Pertinent performance specifications are listed in Table 3-27 .

Table 3-27 RC oscillator performance specifications

Parameter

Oscillation frequency

Duty cycle

Divider in SLEEP_CLK path

Power-supply current

Comments Min

14

30

–

–

Typ

19.2

50

586

–

Max Units

24

70

–

80

MHz

%

–

µA

3.7.4.4 Sleep clock

Source options:



Calibrated low-frequency RC oscillator.

 Used as a source of RTC clock when PMIC is off; requires a qualified coin cell or super capacitor to support RTC when the battery is removed.

 Periodically uses the XO signal for calibration, achieving accuracy suitable for RTC without an external crystal.



The 19.2 MHz XO divided by 586 (32.7645 kHz nominal) – This is the source of sleep clock and RTC clock when the device is in active and sleep mode.



The 19.2 MHz RC oscillator divided by 586 (32.7645 kHz nominal) – The 19.2 MHz RC oscillator is an on-chip circuit with coarse frequency accuracy.

 Used during PMIC power-up until the software switches over to XO/586.

 Used in active or sleep mode only if other sources are unavailable.

LM80-P0436-35 Rev. A


54


The PMIC sleep-clock output is routed to the host IC via SLEEP_CLK. It is also available for other applications using properly configured GPIOs.

Related specifications presented elsewhere include:



19.2 MHz XO circuits (Section 3.7.4.1

)



RC oscillator (Section 3.7.4.3

)



Output characteristics (voltage levels, drive strength, etc.) are defined in Section 3.4

.

3.7.5 Real-time clock

The real-time clock (RTC) functions are implemented by a 32-bit real-time counter and one

32-bit alarm, both configurable in one-second increments. The primary input to the RTC circuits is the selected sleep-clock source (calibrated low-frequency oscillator, or divided-down 19.2

MHz XO). Even when the phone is off, the selected oscillator and RTC continue to run off the main battery.

If the main battery is present and an SMPL event occurs, RTC contents are corrupted. As power is restored, the RTC pauses and skips a few seconds. The device must reacquire system time from the network to resume the usual RTC accuracy. Similarly, if the main battery is not present and the voltage at VCOIN drops too low, RTC contents are again corrupted. In either case, the RTC reset interrupt is generated. A different interrupt is generated if the oscillator stops, also causing

RTC errors.

If RTC support is needed when the battery is removed, a qualified coin-cell or super capacitor is required on the VCOIN pin of the PMIC. If only SMPL support is needed when the battery is removed, a capacitor with effective capacitance of at least 10 µF is required on the VCOIN pin of the PMIC.

Pertinent RTC specifications are listed in Table 3-28 .

Table 3-28 RTC performance specifications

Parameter

Tuning resolution

Tuning range

Accuracy (phone off)

XO/586 as RTC source

CalRC as RTC source

Comments

With known calibrated source

Phone on

Phone off, valid battery present

Phone off, valid coin cell present

Min

–

-192

–

–

–

Typ

3.05

–

–

–

–

Max Units

– ppm

192 ppm

24

50

200 ppm ppm ppm

3.7.6 Over-temperature protection (smart thermal control)

The PMIC includes over-temperature protection in stages, depending on the level of urgency as the die temperature rises:



Stage 0 – normal operating conditions (less than 110°C).



Stage 1 – 110°C to 130°C; an interrupt is sent to the host IC without shutting down any PMIC circuits.

LM80-P0436-35 Rev. A


55




Stage 2 – 130°C to 150°C; an interrupt is sent to the host IC and unnecessary high-current circuits are shut down.



Stage 3 – greater than 150°C; an interrupt is sent to the host IC and the PMIC is completely shut down.

Temperature hysteresis is incorporated such that the die temperature must cool significantly before the device can be powered on again. If any start signals are present while at Stage 3, they are ignored until Stage 0 is reached. When the device cools enough to reach Stage 0 and a start signal is present, the PMIC will power up immediately.

3.8 User interfaces

In addition to housekeeping functions, the PMIC also includes these circuits in support of common handset-level user interfaces: LED current sinks; and vibration motor driver.

3.8.1 Current drivers

There are three current drivers available:



Even numbered MPPs can be used as the home row driver or other current sink function





CHG_LED_SINK to drive LED during charging. This pin cannot be used to drive LED if

LBC is not used (OPT_1 is grounded).

MPPs or GPIOs can be used to control external LED drivers with at least 1 M

Ω pull down at the output

3.8.2 Vibration motor driver

The PMIC supports silent incoming-call alarms with its vibration motor driver. The vibration driver is a programmable voltage output that is referenced to VDD; when off, its output voltage is

VDD. The motor is connected between VDD and the VIB_DRV_N pin.

Performance specifications for the vibration motor driver circuit are listed in Table 3-29 .

Table 3-29 Vibration motor driver performance specifications

Parameter

Output voltage (V m

) error

1

Relative error

Absolute error

Headroom

2

Short-circuit current

Comments

VDD > 3.2 V; I m

= 0 to 175 mA;

V m

setting = 1.2 to 3.1 V

Total error = relative + absolute

I m

= 175 mA

VIB_DRV_N = VDD

Min

-6

-60

–

225

Typ

–

–

–

–

Max Units

6

60

200

600

% mV mV mA

1

The vibration motor driver circuit is a low-side driver. The motor is connected directly to VDD, and the voltage across the motor is Vm = VDD – Vout, where Vout is the PMIC voltage at VIB_DRV_N.

2

Adjust the programmed voltage until the lowest motor voltage occurs while still meeting the voltage accuracy specification. This lowest motor voltage (Vm = VDD – Vout) is the headroom.

LM80-P0436-35 Rev. A


56


3.9 IC-level interfaces

The IC-level interfaces include power-on circuits; the SPMI; interrupt managers; and miscellaneous digital I/O functions like level translators, detectors, and controllers. Parameters associated with these IC-level interface functions are specified in the following subsections.

GPIO and MPP functions are also considered part of the IC-level interface functional block, but

they are specified in their own sections (Section 3.10

and Section 3.11

).

3.9.1 Poweron circuits and the power sequences

Dedicated circuits continuously monitor several events that might trigger a poweron sequence, including KPD_PWR_N, CBL_PWR_N, charger insertion, RTC, or SMPL. If any of these events occur, the PMIC circuits are powered on, the handset's available power sources are determined, the correct source is enabled, and the host IC is taken out of reset.

Hardware configuration controls (OPT[2:1]) determine which regulators are included during the

initial poweron sequence, as defined in Section 3.9.2

. An example sequence will be made

available in future revisions of the document.

The I/Os to/from the poweron circuits are basic digital control signals that must meet the

voltage-level requirements stated in Section 3.4

. The KPD_PWR_N and CBL_PWR_N inputs are

pulled up to an internal voltage, dVdd (CBL_PWR_N is internally pulled high to dVdd using additional weak FET). Additional poweron circuit performance specifications are listed in

Table 3-30 . More complete definitions for time intervals included in this table are provided in the

PM8916 Power Management IC Training Slides (80-NK808-21).

Table 3-30 Poweron circuit performance specifications


Internal pull-up resistor At KPD_PWR_N and CBL_PWR_N pins

t

Sequence time intervals

1

reg1

Poweron event to first regulator on

2

Min

–

–

.

Typ

200

33

Max Units

– k

Ω

– ms

t

reset1

t

ps_hold

t

reset0

t

ps_hold_off

Last default regulator on to PON_RESET_N = H – 450

Time after which PMIC will turn off if PS_HOLD is not driven high by APQ

PON_RESET_N = L to first regulator off

133.33 200

– 6.4

Delay from PS_HOLD dropping to PON_RESET_N going low

–

.

175

–

300

–

– us ms ms us

Primary PON sequence

KYPD_PWR_N

Could be any PON trigger – 0.00 – ms

1

Timing is derived from the divided-down XO clock source (32.7645 kHz typical); tolerances are set accordingly.

2

The first regulator poweron time treg1 depends on the bandgap reference decoupling capacitor at

REF_BYP. The specified value is based on 0.1 µF. This time does not include the default 16 ms keypad debounce and the16 ms UVLO debounce timers. If these debounce timers are increased, then the treg1

value will also increase.

LM80-P0436-35 Rev. A


57


Parameter

S4

S3

L3

S1

S2

GPIO4

MPP1

L5

L7

BB_CLK1

L6

L2

L13

L8

L12

L11

PON_RESET_N

PS_HOLD

Comments

Time from PON trigger to S4 being enabled

Time from S4 enable to S3 being enabled

Time from S3 enable to L3 being enabled

Time from L3 enable to S1 being enabled

Time from S1 enable to S2 being enabled

Time from S2 enable to GPIO4 being enabled

Time from GPIO4 enable to MPP1 being enabled

Time from MPP1 enable to L5 being enabled

Time from L5 enable to L7 being enabled

Time from L7 enable to BB_CLK1 being enabled





Time from L8 trigger to L12 being enabled

Time from L12 trigger to L11 being enabled

Time from L11 enable to PON_RESET_N going high

Time from PON_RESET_N high to PS_HOLD going high

–

–

–

–

–

–

Min

–

–

–

–

–

–

–

–

–

–

–

–

400.00

220.00

350.00

350.00

350.00 t reset1 t ps_hold

Typ

56.00

4.00

2.40

340.00

1.80

Max Units

–

–

– ms ms ms

–

– us ms

1.60

6.70

725.00

125.00

25.00

500.00

–

–

–

–

–

– ms ms us us ms us

–

–

–

–

–

–

– us ms us us us ms ms

LM80-P0436-35 Rev. A


58


KPD_PWR_N (in)

VREG_S4 (2.2 V)

VREG_S3 (1.35 V)

56ms

VREG_L3 (1.15 V)

VREG_S1 (1.15 V)

VREG_S2 (1.15 V)

GPIO4 DO (VPH_PWR)

( + EXT-BUCK-S5)

MPP1 (1.25 V) must stay low at least until PS_HOLD is driven high by the baseband circuits level = don’t care for power-off

Supply for Codec PA/CP, L4, L5, L6, L7, & LDOs for XO & RF_CLK

4ms

Supply for L1, L2, L3

2.4ms

340us

1.8ms

1.6ms

6.7ms

Supply for VDDMX

Supply for VDDCX, GFX, Q6, ADSP

Supply for APC rails in APQ8016

*

EN for S5 (Ext APC Buck)

(Use if OPT2=GND)

Reference for modem IC I/O

725us

Codec and memory 1.8 V rails, WLAN I/O

Enables BB_CLK1, SLEEP_CLK, XO, VREG_XO, LDO7

VREG_L5 (1.8 V )

VREG_L7 (1.8 V)

125us USB_1p8V, SR2_PLLs, ComboDAC, HVDDA_BBRX, ComboDAC, BBCLK driver

(20 ms for XO warm up before BBCLK1 is available)

XO HKADC, thermistor supply;

500us

VREG_L6 (1.8 V)

(+ BMS Enabled)

VREG_L2 (1.2 V)

(+VREF_LPDDR2/3 (VDD/2, typ 0.6 V )

25 ms

400us

VDDPX1, LPDDR2_VDD2/VDDQ/VDDCA

BBCLK1

220ms

BMS OCV enabled here

VDDA_USB3p3, Codec Mic Bias

VREG_L13 (3.075 V)

350us eMMC/NAND

350us VDD_PX2(SD)

VREG_L8 (2.9 V)

VREG_L12 (2.95 V)

VREG_L11 (2.95 V)

350us

SD/MMC Card VDD t reset1 t reset0

PON_RESET_N 850us t ps_hold

Enable SPMI logic after primary PON

POFF sequence as initiated by APQ

PS_HOLD

Operating state OFF Primary PON

*

VDD_MSS and VDDCX rails are merged on APQ8016.

ON

All other VREGs

(L1, L4, VEG_RF_CLK, L9, L10, L14, L15, L16, L17, L18)

Software Controlled

Figure 3-9 Poweron sequence for BB code ‘01’ and ‘02’

Power-off sequence

OFF

NOTE:

For default voltage levels of PM8916 and PM8916-1 during PON sequence see Table 3-13 .

LM80-P0436-35 Rev. A


59


VREG_L7 (1.8 V)

25 ms

BB_CLK1

510us

XO HKADC, thermistor supply;

PON OCV measurement start - Wait for the measurement to finish

VREG_L6 (1.8 V)

(+ BMS Enabled)

210ms VDDPX1, LPDDR2_VDD2/VDDQ/VDDCA

VREG_L2 (1.2 V)

+VREF_LPDDR (VDD/2, typ 0.6 V )

350us

VDDA_USB3p3, Codec Mic Bias

VREG_L13 (3.075 V)

Figure 3-10 Poweron sequence for BB code ‘VV’

POFF

After L6->L5->BBCLK1->L7

3.9.2 OPT[2:1] hardwired controls

Two pins (OPT_1 and OPT_2) can be used to configure PON parameters. The usable

configurations are shown in Table 3-31 .

Table 3-31 OPT_1 and OPT_2 PON parameters

Pins

OPT_1

OPT_2

Hi-Z

External charger not present

External APC buck (S5) not present

GND

External charger present

External APC busk (S5) present

Each OPT combination results in a unique set of poweron parameters: which regulators default on at powerup, the order those regulators are turned on, the voltage settings of some of those regulators, and whether external regulators are turned on via MPP or GPIO controls during the poweron sequence. In essence, the OPT combination customizes the poweron sequence for each chipset.

NOTE:

Connecting either of these pins to VDD will force the PMIC to shut down.

3.9.3 SPMI and the interrupt managers

The SPMI is a bidirectional, two-line digital interface that meets the voltage- and current-level

requirements stated in Section 3.4

.

PMIC interrupt managers support the chipset host and its processors, and communicate with the host IC via SPMI. Since the interrupt managers are entirely embedded functions, additional performance specifications are not required.

3.10 General-purpose input/output specifications

The four general-purpose input/output (GPIO) ports are digital I/Os that can be programmed for a

variety of configurations ( Table 3-32 ). Performance specifications for the different configurations

are included in Section 3.4

.

NOTE:

Unused GPIO pins should be configured as inputs with 10

µA pulldown.

LM80-P0436-35 Rev. A


60


Table 3-32 Programmable GPIO configurations

Configuration type

Input

Output

Input/output pair

Configuration description

1. No pullup

2. Pullup (1.5, 30, or 31.5

µA)

3. Pulldown (10 µA)

4. Keeper

Open-drain or CMOS

Inverted or non-inverted

Programmable drive current; see Table 3-33 for options

Requires two GPIOs. Input and output stages can use different power supplies,

thereby implementing a level translator. See Table 3-33 for supply options.

GPIOs default to digital input with 10 uA pulldown at poweron. During poweron (OPT2 = GND), PBS programs GPIO_4 as digital output high at VDD level to enable the external buck converter. Before they can be used for their desired purposes, they need to be reconfigured appropriately.

GPIO_4 can also be used as SLEEP_CLK output special function if OPT2 is not grounded.

GPIO_2 can be used to pin control BB_CLK2 output by configuring it appropriately.

GPIO_1 and GPIO_2 do not support VPH_PWR domain.

GPIOs are designed to run at a 4 MHz rate to support high-speed applications (only GPIO1 and

GPIO2 are GPIOC capable). The supported rate depends on the load capacitance and IR drop requirements. If the application specifies load capacitance, then the maximum rate is determined by the IR drop. If the application does not require a specific IR drop, then the maximum rate can be increased by increasing the supply voltage and adjusting the drive strength according to the

actual load capacitance. Table 3-33 lists output voltages for different driver strengths.

Table 3-33 VOL and VOH for different driver strengths

Supply voltage

1.8 V

2.6 V

2.85 V

3.3 V

VOL, VOH

VOH = VDD – 0.3 V = 1.5 V

VOL = 0.3 V

VOH = VDD – 0.45 V = 2.15 V

VOL = 0.45 V

VOH = VDD – 0.4 V = 2.45 V

VOL = 0.4 V

VOH = VDD – 0.45 V = 2.85 V

VOL = 0.45 V

Low-strength driver

0.15 mA

Minimum load current

Medium-strength driver

0.6 mA

High-strength driver

0.9 mA

0.3 mA

0.3 mA

0.39 mA

1.25 mA

1.1 mA

1.4 mA

1.9 mA

1.7 mA

2.1 mA

LM80-P0436-35 Rev. A


61


3.11 Multipurpose pin specifications

The PM8916 includes four multipurpose pins (MPPs), and they can be configured for any of the

functions specified within Table 3-34 . All MPPs are high-Z at poweron. During poweron, PBS

programs MPP_1 as analog output, which is used as a reference for host IC.

Table 3-34 Multipurpose pin performance specifications

Comments Parameter

MPP configured as digital input

1

Logic high input voltage

Logic low input voltage

Min

0.65 * V_M

–

Typ

–

–

Max

–

0.35 *

V_M

Units

V

V

MPP configured as digital output

1

Logic high output voltage

Logic low output voltage

Iout = IOH

Iout = IOL

MPP configured as analog input (analog multiplexer input)

Input current

Input capacitance

MPP configured as analog output (buffered VREF output)

2

Output voltage error

Temperature variation

-50 µA to +50 µA

Due to buffer only; does not include

VREF variation (see Table 3-17 )

Load capacitance


MPP configured as current sink

2

Power supply voltage

Sink current

Sink current accuracy


Programmable in 5 mA increment

VOUT = 0.7 V to (VDD – 1 V)

MPP configured as level translator

Maximum frequency

V_M – 0.45

0

–

–

–

-0.03

–

–

–

0

-20

4

–

–

–

–

–

–

–

0.17

VDD

105

–

V_M

0.45

100

10

12.5

0.03

25

0.2

–

40

+20

115

–

V

V nA pF mV

% pF mA

V mA

%

µA

MHz

3.12 Audio codec

NOTE:

All audio performance data are collected above PMIC Vbatt of 3.4 V, unless otherwise specified.

1

Input and output stages can use different power supplies, thereby implementing a level translator. See

Table 2-1

for V_M supply options. Other specifications are included in Section 3.4

.

2

Only even MPPs (MPP_2 and MPP_4) can be configured as current sink and only odd MPPs (MPP_1 and

MPP_3) can be configured as analog output.

LM80-P0436-35 Rev. A


62


3.12.1 Audio inputs and Tx processing

Table 3-35 Analog microphone input performance


Microphone amplifier gain = 0 dB (minimum gain)

Input referred noise

Single-ended, A-weighted, capless

Signal to noise ratio

THD+N ratio

Single-ended, A-weighted, capless f = 1.02 kHz; single-ended input; bandwidth

200 Hz to 20 kHz, capless

Analog input = -1 dBV

Analog input = -60 dBV, A-weighted

Microphone amplifier gain = 6 dB



THD+N






Microphone amplifier gain = 12 dB (typical gain)



THD+N









THD+N









THD+N


Single-ended A-weighted, capless f = 1.02 kHz; single-ended input; bandwidth



Analog input = -60 dBV A-weighted

Microphone amplifier gain = 24 dB (maximum gain)



Single-ended A-weighted, capless

Single-ended A-weighted, capless

Min

–

91.0

–

–

–

91.0

–

–

–

85.0

–

–

–

92.0

–

–

–

84.0

–

87

–

–

Typ

18.5

94.0

-83.0

-35.0

25.1

µVrms

– dB

-70.0

-32.0 dB dB

10.0

94.0

-82.5

-34.0

13.0 µVrms

– dB

-70.0

-30.0 dB dB

5.5

93.5

-83.0

-33.5

7.1

–

-70.0

-30.0

µVrms dB dB dB

3.5

91.0

-82.0

-31.0

6.3

–

-70.0

-28.0

µVrms dB dB dB

2.8

89.0

-81.5

-28.5

4.2

–

-70.0

-25.0

µVrms dB dB dB

2.6

87.5

Max Units

4.2

–

µVrms dB

LM80-P0436-35 Rev. A


63


THD+N


f = 1.02 kHz; single-ended input; bandwidth



Analog input = -60 dBV A-weighted

Frequency response (from mic input to PCM all sample rates)

Frequency response

Digital gain = 0 dB; analog gain = 0 dB;


Passband: 20 Hz to 200 Hz

Passband: 200 Hz to 0.4 * Fs

Transition band 1 at 0.4375 * Fs

Transition band 2 at 0.499 * Fs

Stopband at 0.5625 * Fs

Min

–

–

-0.05

-0.05

-1.5

–

–

General requirements

Absolute gain error

Full-scale input voltage

Power supply rejection

(1.8 V)

Intermodulation distortion

(IMD2)

Input impedance

Input capacitance

Rx

→Tx crosstalk attenuation

Inter-channel isolation

Analog input = -20 dBV, 1.02 kHz

Single-ended 1 kHz input. Input signal level required to get 0 dBFS digital output

100 mVpp square wave imposed on the

PMIC Vbatt input; analog input = 0 Vrms, terminated with 0 Ω; keep the bypass capacitors on power pins and measure

100 mV ripple at the power pins

0 < f < 1 kHz

1< f < 5 kHz f > 5 kHz

Analog input = 12993 Hz and 14993 Hz equal amplitude tones at -6 dBV; wideband

(WB) audio

Analog input = 41 Hz and 7993 Hz equal amplitude tones at -6 dBV, WB voice

Analog input = 498 Hz and 2020 Hz equal amplitude tones at -6 dBV, narrowband (NB) voice

Capless input

Input disabled

Capless input

Tx path measurement with -5 dBV Rx path signal; f = 1 kHz, 10 kHz, and 20 kHz

20 < f < 20 kHz, one input terminated with

1 k

Ω and the other input gets 1 kHz at

-5 dBV; measure the digital output of the terminated channel

-20.5

-0.5

75.0

75.0

60.0

65.0

50.0

60.0

1.0

3.0

–

80.0

90.0

Typ

-82.0

-26.0

0

0

-0.7

-25.0

-75.0

-20.0

0

86.0

82.0

70.0

85.0

90.0

90.0

–

–

–

97.0

100.0

Max Units

-60.0

-22.0 dB dB

0.05

0.05

0.5

-24.0

-70.0

–

–

–

–

–

15.0

– dB dB dB

M

Ω

M

Ω pF dB dB dB dB dB dB

-19.5

0.5 dB dBV

–

–

–

– dB dB dB dB

LM80-P0436-35 Rev. A


64


3.12.2 Audio outputs and Rx processing

Table 3-36 Ear output performance, 32

Ω load unless specified

Parameter Test conditions Min Typ Max Units

EAR: 8 kHz, 16 bits

Receive noise


THD+N

A-weighted; input = -999 dBFS, 6 dB gain mode

A-weighted; input = -999 dBFS, 1.5 dB gain mode

Ratio of full scale output to output noise level,

VDD_EAR_SPKR = 3.7 V or 5 V, 1.5 dB gain mode


VDD_EAR_SPKR = 3.7 V or 5 V, 6 dB gain mode

PCMI = -1 dBFS (band limited from

200 Hz to 20 kHz), VDD_EAR_SPKR = 3.7 V or 5 V

PCMI = -60 dBFS (band limited from 200 Hz to 20 kHz),

VDD_EAR_SPKR = 3.7 V or 5 V, A-weighted

EAR: 16 kHz, 16 bits

Receive noise


THD+N

A-weighted; input = -999 dBFS, 6 dB gain mode

A-weighted; input = -999 dBFS, 1.5 dB gain mode


VDD_EAR_SPKR = 3.7 V or 5 V, 1.5 dB gain


VDD_EAR_SPKR = 3.7 V or 5 V, 6 dB gain mode

PCMI = -1 dBFS (band limited from

200 Hz to 20 kHz), VDD_EAR_SPKR = 3.7 V or 5 V


VDD_EAR_SPKR = 3.7 V or 5 V, A-weighted

Other characteristics

Full-scale output voltage f = 1.02 kHz, 6 dB gain mode f = 1.02 kHz, 1.5 dB gain mode

DAC full-scale output

Output power f = 1.02 kHz, 6 dB gain mode, 32

Ω, THD+N <1% f = 1.02 kHz, 6 dB gain mode, 16

Ω THD+N < 1% f = 1.02 kHz, 6 dB gain mode, 10.67

Ω THD+N < 1%

Output load

Output capacitance

Total capacitance between EARO_P and EARO_M, including PCB capacitance and EMI

Tx

→ Rx crosstalk attenuation

Rx path measurement with -5 dBFS Tx path signal; f = 1 kHz


0 < f < 1 kHz; 100 mVpp sine wave imposed on

VDD_EAR_SPKR; PCMI = -999 dBFS, 6 dB gain mode

1 kHz < f < 5 kHz; 100 mVpp sine wave imposed on


5 kHz < f < 20 kHz; 100 mVpp sine wave imposed on


Disabled output impedance

Measured externally, with amplifier disabled

–

–

–

–

–

–

102.0 108.0

–

–

1.8

1.0

–

–

90.0

70.0

60.0

50.0

1.0

7.8

5.8

102.0 108.0

100.0 106.0

-80.0

-34.5

7.8

5.8

100.0 106.0

-74.0

-34.5

2.0

1.2

–

120.0 124.5

235.0 243.0

310.0 320.0

–

100.0

90.0

82.0

78.0

–

16.0 µVrms

12.0 µVrms

–

–

-70.0

-31.0

10.7 32.0 50000 dB dB dB dB

16.0

µVrms

12.0 µVrms

–

–

-70.0

-31.0

2.1

1.3

1.0

–

–

–

500

–

–

–

–

– dB dB dB dB

Vrms

Vrms

Vrms mW mW mW

 pF dB dB dB dB

M 

LM80-P0436-35 Rev. A


65


Parameter

Output common mode voltage

Output DC offset

Turn on/off click and pop level

Test conditions


A-weighted

Table 3-37 HPH output performance, 16

Ω load unless specified


HPH: 8 kHz, 16 bits

Receive noise


THD+N

A-weighted; input = -999 dBFS, VDD_CP = 1.9 V


VDD_CP = 1.9 V


VDD_CP = 1.9 V


VDD_CP = 1.9 V, A-weighted

HPH: 48 kHz, 16 bits

Receive noise




VDD_CP = 1.9 V

THD+N


VDD_CP = 1.9 V


VDD_CP = 1.9 V or, A-weighted

HPH: 48 kHz, 24 bits

Receive noise


THD+N



VDD_CP = 1.9 V


VDD_CP = 1.9 V


VDD_CP = 1.9 V, A-weighted


Full-scale output voltage f = 1.02 kHz, 0 dB FS; 16

Ω load; VDD_CP = 1.9 V f = 1.02 kHz, 0 dB FS; 32

Ω load; VDD_CP = 1.9 V


Output power f = 1.02 kHz, 16 Ω load; VDD_CP = 1.9 V f = 1.02 kHz, 32 Ω load; VDD_CP = 1.9 V

Output load

0 dBV maximum output

-4.5 dBV maximum output


1.52 1.60 1.68 V

0

–

Min

0.135 3.0 mV

-66.0 -54.0 dBVpp

Typ Max Units

–

99.0

4.7

102.5

6.5 µVrms

– dB

–

-80.0 -70.0 dB

–

-35.0 -31.0 dB

–

4.7

99.0

102.5

6.5 µVrms

– dB

–

-88.0 -75.0 dB

–

-36.0 -32.0 dB

–

99.0

4.7

102.5

6.5 µVrms

– dB

–

-89.0 -80.0 dB

–

-43.0 -40.0 dB

0.50

0.59 0.64 Vrms

0.96

–

15.6

27.0

26

13

0.99 1.00 Vrms

– 1.00

Vrms

21.5 25.6 mW

30.8

32

16

32.0

50000

50000 mW

Ω

Ω

LM80-P0436-35 Rev. A


66



Output capacitance

Total capacitance on HPH output (single-ended), including PCB capacitance and EMI

Tx

→ Rx crosstalk attenuation

Inter-channel phase error

Rx path measurement with -5 dBFS Tx path signal. f = 1 kHz

Inter-channel isolation

(separate GND for

HPH_L & R)

20 < f < 20 kHz, measured channel output = -999 dBFS, second DAC channel output = -5 dBFS

Inter-channel gain error

Delta between left and right channels, input = 1 kHz at -20 dBFS

Delta between left and right channels, input = 1 kHz at -20 dBFS


0 < f < 20 kHz; 100 mVpp sine wave imposed on

VPH_PWR; PCMI = -999 dBFS

Intermodulation distortion (IMD2)

Digital input = 12993 Hz and 14993 Hz equal amplitude tones at -6 dBFS

Digital input = 41 Hz and 7993 Hz equal amplitude tones at -6 dBFS

Analog input = 498 Hz and 2020 Hz equal amplitude tones at -6 dBFS



Output DC offset

Turn on/off click and pop level

Input = -999 dBFS

A-weighted, 16

Ω or 32 Ω

1.0

0

–

–

90.0

90.0

–

–

70.0

65.0

70.0

–

0.1

–

100.0

97.0

0.03

0.07

80.0

90.9

81.0

75.0

77.0

–

1000

–

–

0.30

0.50

1.5

–

–

–

–

M pF dB dB dB deg dB dB dB dB

Ω mV

-81.0 -62.0 dBVpp

Table 3-38 Mono speaker driver outputs performance, 8

Ω load and + 12 dB gain unless otherwise specified


SPKR_DRV; 48 kHz, 16 bits

Receive noise

THD+N

A-weighted; input = -999 dBFS,

VDD_EAR_SPKR = 5 V

Pout = 1.5 W, 1 kHz, VDD_EAR_SPKR = 5.5 V

Pout = 1.2 W, 1 kHz, VDD_EAR_SPKR = 5 V

Pout = 1 W, 1 kHz, VDD_EAR_SPKR = 4.2 V

Pout = 850 mW, 1 kHz, VDD_EAR_SPKR = 4.2 V

Pout = 700 mW, 1 kHz, VDD_EAR_SPKR = 3.8 V

Pout = 250 mW 1 kHz, VDD_EAR_SPKR = 3.4 V

–

–

–

–

–

–

–

50.0 100.0 µVrms

-86.5 -80.0 dB

-86.0 -80.0 dB

-36.0 -20.0 dB

-78.0 -40.0 dB

-76.0 -40.0 dB

-77.0 -40.0 dB

LM80-P0436-35 Rev. A


67





Level translation f = 1 kHz, gain = 12 dB

Input = -3 dBFS, VDD_EAR_SPKR = 3.7 V

Input = -1.5 dBFS, VDD_EAR_SPKR = 5.5 V

Output power

(Pout)


Output DC offset

Efficiency f = 1 kHz

Vdd = 3.6 V THD + N ≤ 1%; 15 µH + 8 Ω + 15 µH

Vdd = 3.6 V THD + N ≤ 1%; 15 µH + 4 Ω + 15 µH

Vdd = 3.8 V THD + N ≤ 1%; 15 µH + 8 Ω + 15 µH

Vdd = 4.2 V THD + N ≤ 1%; 15 µH + 8 Ω + 15 µH

Vdd = 5 V THD+N ≤1%; 15 µH + 8 Ω + 15 µH

Vdd = 5 V THD+N ≤1%; 15 µH + 4 Ω + 15 µH

200 mVpp sine wave imposed on PMIC_BATT; digital input = -999 dBFS

1

f = 217 Hz f = 1 kHz f = 10 kHz f = 20 kHz

Speaker driver enabled, input = -999 dBFS

Vdd = 3.7 V

Pout = 500 mW; 15 µH + 8

Ω + 15 µH

Pout = 1 W; 15 µH + 4

Ω + 15 µH

Vdd = 5 V

Pout = 1 W, 115 µH + 8

Ω + 15 µH

Pout = 2 W, 15 µH + 4

Ω + 15 µH

Shutdown current Amplifier disabled

Turn on time

Click and pop

No signal, turn on/off, mute/unmute, A-weighted


Load capacitance

VDD/GND inductance

Vdd = 5.5 V, square wave, 20 Hz to 20 kHz,

40 hours



–

–

–

–

25

60.0

60.0

40.0

40.0

-3.0

85

78

73

61

–

–

7.3

9.2

670

900

698

929

1200

1500

– 1

Vrms

8.9 9.5 dBV

10.4 11.5 dBV

690

1100

720

956

1500

2000

–

–

–

–

–

– mW mW mW mW mW mW

79.0

79.0

50.0

50.0

0.20 3.0

90

85

–

–

–

–

–

81

72

0.1

0.2

0.6

–

–

–

%

%

1

10

µA ms

10 mVpp

– k

Ω dB dB dB mV

%

%

–

–

–

0.5

2

pF nH

1

With 200 mVpp sine wave imposed on VSW_BOOST and digital input = -999 dBFS, PSRR is higher than

90 dB typical for all test cases

2

Bypass capacitors should be placed after the series ferrite bead at the amplifier’s output. Having a capacitor directly at the speaker-driver output reduces class-D efficiency and increases power consumption

LM80-P0436-35 Rev. A


68


3.12.3 Support circuits

Table 3-39 Microphone bias specifications


Output voltage

Output voltage accuracy

Output current

Output switch to ground

Output noise


Inter-mic isolation

Output capacitor value

3 mA microphone load

Two microphone loads of 1 to 1.5 mA each

On resistance

Sink current

0.1 µF bypass

100 mVpp applied to PMIC Vbatt input at 20 Hz at 200 Hz to 1 kHz at 5 Hz at 10 kHz at 20 kHz

DC current = 50 µA, 2.2 k

Ω bias resistor;

20 Hz to 200 Hz

200 Hz to 1 kHz

1 kHz to 2 kHz

2 kHz to 5 kHz

5 kHz to 10 kHz

10 kHz to 20 kHz

20 kHz to 80 kHz

External bypass mode

No external bypass mode

Min

1.6

-3

2.0

–

2.0

0.0

90

90

90

90

85

70.0

67.0

67.0

65.0

60.0

54.0

32.0

0.1

–

Typ

–

3.0

–

–

2.4

–

–

–

–

–

72.6

72.6

72.0

70.9

69.2

66.4

–

0.1

–

Max

2.85

+3

–

20

–

3.0

–

–

–

–

–

–

–

–

–

–

–

–

0.5

270

Units

V

% mA

Ω mA

µVrms dB dB dB dB dB dB dB dB dB dB dB dB

µF pF

LM80-P0436-35 Rev. A


69

4 Mechanical Information

4.1 Device physical dimensions

The PM8916 is available in the 176-pin nanoscale package (176 NSP) that includes dedicated ground pins for improved grounding, mechanical strength, and thermal continuity. The 176 NSP has a 6.2 × 6.2 mm body with a maximum height of 0.86 mm. Pin 1 is located by an indicator

mark on the top of the package. Figure 4-1 shows a simplified version of the 176 NSP outline

drawing.

LM80-P0436-35 Rev. A


70

PM8916/PM8916-1 Device Specification Mechanical Information

Figure 4-1 6.2 x 6.2 x 0.86 mm outline drawing

This is a simplified outline drawing.

LM80-P0436-35 Rev. A


71


4.2 Part marking

4.2.1 Specification-compliant devices

Mechanical Information

Figure 4-2 PM8916 device marking (top view, not to scale)

Table 4-1 PM8916 device marking line definitions

Line

1

2

3

Marking

QUALCOMM

PM8916

PBB

E

4

5

Blank or random

FXXXXXXX

AXYWWRR

Description

Qualcomm® name or logo

Qualcomm Technologies Inc. (QTI) product name

P = product configuration code

See Table 4-2 for assigned values.

BB = feature code


Additional content as necessary

F = supply source code

F = A: SMIC

F = B: TSMC

XXXXXXX = traceability information

A = assembly site code

A = U: Amkor, China

A = V: StatsChipPAC, China

A = E: ASE, Taiwan

A = K: SPIL, Taiwan

X = Traceability information

YWW = Date code

RR = product revision


• = dot identifying pin 1

For complete marking definitions of all PM8916 variants and revisions, refer to

PM8916/PM8916-1 Device Revision Guide (LM80-P0436-34).

LM80-P0436-35 Rev. A


72


4.3 Device ordering information

4.3.1 Specification-compliant devices

This device can be ordered using the identification code shown in Figure 4-3 and explained

below.

Device ID code

Symbol definition

Example

AA-AAAA — P — CCC DDDDD — EE — RR — S — BB

Product name

PM-8916

Config code

Number of pins

Package type

Shipping package

Product revision

Source code

Feature code

— 0 — 176 NSP — TR — 02 — 0 — VV

Feature code (BB) may not be included when identifying older devices.

Figure 4-3 Device identification code

Device ordering information details for all samples available to date are summarized in Table 4-2 .

Table 4-2 PM8916 device identification details

PM8916 variant

PM8916

ES1

PM8916

ES2

PM8916

CS1

PM8916

CS2

PM8916-1

CS3

Product configuration code (P)

1

Product revision (RR)

Feature code

BB value

2

S value

3

Hardware revision

Date code

(YWW)

0

0

0

0

1

01

02

02

02

02

VV

VV

VV

01

02

0

0

0

1

1 v1.1 v2.0 v2.0 v2.0.1 v2.0.1

≤ 418

419 to 425

≥ 420

4

NA

NA

Table 4-3 Feature codes

BB value

VV

01 & 02

Feature description

PON sequence – VM-BMS OCV measurement is enabled after L6 power on.

PON sequence – VM-BMS OCV measurement is enabled after L2 power on.

1

P code 0 will be called PM8916 and is integrated with the APQ8016 platform.

P code 1 will be called PM8916-1 and is integrated with the APQ8009 platform.

2

“BB” is the feature code that identifies an IC’s specific feature set, which distinguishes it from other versions or variants.

3

“S” is the source configuration code that identifies all of the qualified die fabrication-source combinations available at the time a particular sample type was shipped.

4

For date codes 420–425, contact your customer service team.

LM80-P0436-35 Rev. A


73


Table 4-4 Source configuration code

S value

0

Die

CMOS

F value = TBD F value = TBD F value = TBD F value = TBD

TBD – –

Other columns and rows will be added in future revisions of this document if needed.

–

4.4 Device moisture-sensitivity level

Plastic-encapsulated surface mount packages are susceptible to damage induced by absorbed moisture and high temperature. QTI follows the latest IPC/JEDEC J-STD-020 standard revision for moisture-sensitivity qualification. The PM8916 devices are classified as MSL3 at 250ºC. This is the MSL classification temperature, which is defined as the minimum temperature of moisture sensitivity testing during device qualification.

Additional MSL information is included in:

Section 5.2

– Storage

Section 5.3

– Handling

Section 7.1

– Reliability qualifications summary

LM80-P0436-35 Rev. A


74

5 Carrier, Storage, and Handling

Information

5.1 Carrier

5.1.1 Tape and reel information

All QTI carrier tape systems conform to EIA-481 standards.

A simplified sketch of the PM8916 tape carrier is shown in Figure 5-1 , including the proper part

orientation, maximum number of devices per reel, and key dimensions.

Pin 1 faces feed holes

Taping direction

Tape feed:

Units per reel:

Single

4000

Reel diameter:

Hub diameter:

330 mm

102 mm

Pocket pitch

Tape width:

Pocket pitch:

16.00

+/- 0.3

12.00 +/- 0.10

Figure 5-1 Carrier tape drawing with part orientation

LM80-P0436-35 Rev. A


75


Tape-handling recommendations are shown in Figure 5-2 .

Carrier, Storage, and Handling Information

Figure 5-2 Tape handling

5.2 Storage

5.2.1 Bagged storage conditions

PM8916 devices delivered in tape and reel carriers must be stored in sealed, moisture barrier, antistatic bags.

5.2.2 Out-of-bag duration

The out-of-bag duration is the time a device can be on the factory floor before being installed onto a PCB. It is defined by the device MSL rating.

5.3 Handling

Tape handling was described in Section 5.1.1

. Other (IC-specific) handling guidelines are

presented below.

5.3.1 Baking

It is not necessary to bake the PM8916 devices if the conditions specified in Sections 5.2.1

and

5.2.2

have not been exceeded.

It is necessary to bake the PM8916 devices if any condition specified in Section 5.2.1

or 5.2.2

has

been exceeded. The baking conditions are specified on the moisture-sensitive caution label attached to each bag.

If baking is required, the devices must be transferred into trays that can be baked to at least

125°C. Devices should not be baked in tape and reel carriers at any temperature

5.3.2 Electrostatic discharge

Electrostatic discharge (ESD) occurs naturally in laboratory and factory environments. An established high-voltage potential is always at risk of discharging to a lower potential. If this discharge path is through a semiconductor device, destructive damage may result.

ESD countermeasures and handling methods must be developed and used to control the factory environment at each manufacturing site.

LM80-P0436-35 Rev. A


76

PM8916/PM8916-1 Device Specification Carrier, Storage, and Handling Information

QTI products must be handled according to the ESD Association standard: ANSI/ESD S20.20-

1999, Protection of Electrical and Electronic Parts, Assemblies, and Equipment.

PM8916 ESD ratings will be available in future revisions of this document.

LM80-P0436-35 Rev. A


77

6 PCB Mounting Guidelines

6.1 RoHS compliance

The device is lead-free and RoHS-compliant. QTI defines its lead-free (or Pb-free) semiconductor products as having a maximum lead concentration of 1000 ppm (0.1% by weight) in raw

(homogeneous) materials and end products.

6.2 SMT parameters

This section describes QTI board-level characterization-process parameters. It is included to assist customers with their SMT process development; it is not intended to be a specification for their SMT processes.

6.2.1 Land pad and stencil design

The land-pattern and stencil recommendations presented in this section are based on QTI internal characterizations for lead-free solder pastes on an eight-layer PCB, built primarily to the specifications described in JEDEC JESD22-B111.

QTI recommends characterizing the land patterns according to each customer's processes, materials, equipment, stencil design, and reflow profile prior to PCB production. Optimizing the solder-stencil pattern design and print process is critical to ensure print uniformity, decrease voiding, and increase board-level reliability.

General land-pattern guidelines:



Non-solder-mask-defined (NSMD) pads provide the best reliability.



Keep the solder-able area consistent for each pad, especially when mixing via-in-pad and non-via-in-pad in the same array.



Avoid large solder mask openings over ground planes.



Traces for external routing are recommended to be less than or equal to half the pad diameter, to ensure consistent solder-joint shapes.

One key parameter that should be evaluated is the ratio of aperture area to sidewall area, known as the area ratio (AR). QTI recommends square apertures for optimal solder-paste release. In this case, a simple equation can be used relating the side length of the aperture to the stencil thickness

(as shown and explained in Figure 6-1 ). Larger area ratios enable better transfer of solder paste to

the PCB, minimize defects, and ensure a more stable printing process. Inter-aperture spacing should be at least as thick as the stencil; otherwise, paste deposits may bridge.

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PM8916/PM8916-1 Device Specification PCB Mounting Guidelines

Figure 6-1 Stencil printing aperture area ratio (AR)

Guidelines for an acceptable relationship between L and T are listed below, and are shown in

Figure 6-2 :





R = L/4T > 0.65 – best

0.60

≤ R ≤ 0.65 – acceptable



R < 0.60 – not acceptable

Figure 6-2 Acceptable solder-paste geometries

6.2.2 Reflow profile

Reflow profile conditions typically used by QTI for lead-free systems are listed in Table 6-1 and

are shown in Figure 6-3 .

Table 6-1 QTI typical SMT reflow-profile conditions (for reference only)

Profile stage

Preheat

Soak

Ramp

Reflow

Cool down

Description

Initial ramp

Flux activation

Transition to liquidus (solder-paste melting point)

Time above liquidus

Cool rate – ramp to ambient

Temp range

< 150°C

150 to 190°C

190 to 220°C

220 to 245°C

1

< 220°C

Condition

3°C/sec max

60 to 75 sec

< 30 sec

50 to 70 sec

6°C/sec max

1

During the reflow process, the recommended peak temperature is 245°C (minimum). This temperature should not be confused with the peak temperature reached during MSL testing, as described in

Section 6.2.3

.

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Figure 6-3 QTI typical SMT reflow profile

6.2.3 SMT peak package-body temperature

This document states a peak package-body temperature in three other places within this document; without explanation, they may appear to conflict. The three places are listed below, along with an explanation of the stated value and its meaning within that section’s context.

1. Device moisture-sensitivity level

PM8916 devices are classified as MSL3 @ 250°C. The temperature (250°C) included in this designation is the lower limit of the range stated for moisture resistance testing during the device qualification process, as explained in #2 below.

2. Reliability qualifications summary

One of the tests conducted for device qualification is the moisture resistance test. QTI follows

J-STD-020-C, and hits a peak reflow temperature that falls within the range of 260°C +0/-5 C

(255 to 260 °C).

3. Reflow profile

During a production board’s reflow process, the temperature seen by the package must be controlled. Obviously, the temperature must be high enough to melt the solder and provide reliable connections. However, it must not go so high that the device might be damaged. The recommended peak temperature during production assembly is 245°C. This is comfortably above the solder melting point (220°C), yet well below the proven temperature reached during qualification (250°C or more).

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6.2.4 SMT process verification

QTI recommends verification of the SMT process prior to high-volume board assembly, including:



In-line solder-paste deposition monitoring



Reflow-profile measurement and verification



Visual and X-ray inspection after soldering to confirm adequate alignment, solder voids, solder-ball shape, and solder bridging



Cross-section inspection of solder joints for wetting, solder-ball shape, and voiding

6.3 Board-level reliability

QTI conducts characterization tests to assess the device’s board-level reliability, including the following physical tests on evaluation boards:



Drop shock (JESD22-B111)



Temperature cycling (JESD22-A104)



Cyclic bend testing – optional (JESD22-B113)

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7 Part Reliability

7.1 Reliability qualifications summary

7.1.1 PM8916 reliability evaluation report for NSP device

Table 7-1 Silicon reliability results for SMIC

Tests, standards, and conditions

DPPM rate (ELFR) and average failure rate (AFR) in FIT (l) failure in billion device-hours

HTOL: JESD22-A108

Use condition: temperature: 85°C, voltage: 4.75 V

Total samples from three different wafer lots

Mean time to failure (MTTF) t = 1/

λ in million hours


ESD – Human-body model (HBM) rating:

JESD22-A114

Total samples from one wafer lot

ESD – Charge-device model (CDM) rating:

JESD22-C101

Target 500 V


Latch-up (I-test):

EIA/JESD78C

Trigger current: ±100 mA; temperature: 85°C


Latch-up (Vsupply overvoltage):

EIA/JESD78A

Trigger voltage: Each VDD pin, stress at 1.5 × VDD max per device specification; temperature: 85°C


Sample size

2331

2331

3

3

6

6

Result

DPPM < 1000

1

Cum FITs < 25 FITs

1

> 401

2000 V

500 V

Pass

Pass

1

Cum FITs from multiple products under SMIC-S1, 0.18 µm process.

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PM8916/PM8916-1 Device Specification Part Reliability

Table 7-2 Silicon reliability results for TSMC


DPPM rate (ELFR) and average failure rate (AFR) in FIT (l) failure in billion device-hours

HTOL: JESD22-A108

Use condition: temperature: 8°C, voltage: 4.75 V


Mean time to failure (MTTF) t = 1/l in million hours


ESD – Human-body model (HBM) rating:

JESD22-A114


ESD – Charge-device model (CDM) rating:

JESD22-C101

Target 500 V


Latch-up (I-test):

EIA/JESD78C

Trigger current: ±100 mA; temperature: 85°C


Latch-up (V supply overvoltage):

EIA/JESD78A

Trigger voltage: Each VDD pin, stress at 1.5 × VDD max per device specification; temperature: 85°C


Sample size

472

472

3

3

6

6

Result

DPPM < 1000

1

Cum FITs < 25 FITs

1

> 401

2000 V

2

500 V

Pass

3

Pass

Table 7-3

Package reliability results for SMIC/TSMC


Moisture resistance test (MRT): J-STD-020C

Reflow at 260°C +0/-5°C

Total samples from three different assembly lots at each

SAT

Temperature cycle: JESD22-A104-D

Temperature: -55°C to 125°C; number of cycles: 1000

Soak time at min/max temperature: 8-10 min

Cycle rate: 2 cycles per hour (cph)

Preconditioning: JESD22-A113-F

MSL1; reflow temperature: 260°C +0/-5°C


SAT

SCC assembly source sample size

ASE-kh assembly source sample size

ATC assembly source sample size

SPIL assembly source sample size

462 462 462 462

Result

Pass

231 231 231 231 Pass

1

Cum DPPM and FITs from multiple products under TSMC, 0.18 µm process.

2

ESD-HBM: All pins pass 2 kV except two pins, which pass at 1.5 kV: GND_DRV and VIB_DRV_N

3

Latch-up:

All pins pass 100 mA JEDEC specification except option 2 pin which pass at 70 mA for APQ8016/APQ8009 application. Option 2 pin is “NC” in this configuration. Chance of exposure is low.

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PM8916/PM8916-1 Device Specification Part Reliability


SCC assembly source sample size

ASE-kh assembly source sample size

ATC assembly source sample size

SPIL assembly source sample size

231 231 231

Result

Pass

Unbiased highly accelerated stress test

JESD22-A118

130

C/85% RH a nd 96 h

Preconditioning: JESD22-A113-F

MSL1; reflow temperature: 260°C +0/-5

C


SAT

High-temperature storage life: JESD22-A103-C

Temperature 150

C; dura tion


SAT

Flammability

UL-STD-94

Note: Flammability test – not required

QTI ICs are exempt from the flammability requirements due to their sizes per UL/EN 60950-1, as long as they are mounted on materials rated V-1 or better. Most PWBs onto which QTI ICs mount are rated V-0 (better than V-1).

Physical dimensions: JESD22-B100-A

Case outline drawing: QTI internal document


SAT

Solder ball shear: JESD22-B117


SAT

Internal/external visual


SAT

231

231

NA

78

15

78

231

NA

78

15

78

231

NA

78

15

78

231

NA

78

15

78

Pass

Pass

Pass

Pass

Pass

7.2 Qualification sample description

Device characteristics



Device name: PM8916



Package type: 176 NSP



Package body size: 6.2 mm × 6.2 mm × 0.86 mm



Lead count: 176





Lead composition: SAC125Ni

Fab process: 0.18

µm HV-CMOS



Fab sites: SMIC and TSMC



Assembly sites: Amkor, China; STATSChipPAC, China; ASE, Taiwan; SPIL, Taiwan



Solder ball pitch: 0.4 mm

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LM80-P0436-35 Rev. A


85

PM8916/PM8916-1 Device Specification

Qualcomm Technologies, Inc.

Device Specification

August 2015

Revision history

Contents

Figures

Tables

1 Introduction

1.1 Documentation overview

1.2 PM8916 introduction

1.3 PM8916 features

1.4 Terms and acronyms

1.5 Special marks

2 Pin Definitions

2.1 I/O parameter definitions

2.2 Pin descriptions

3 Electrical Specifications

3.1 Absolute maximum ratings

3.2 Operating conditions

3.3 DC power consumption

3.4 Digital logic characteristics

3.5 Input power management

1% resistors

Battery pack

3.6 Output power management

3.7 General housekeeping

3.8 User interfaces

3.9 IC-level interfaces

3.10 General-purpose input/output specifications

3.11 Multipurpose pin specifications

3.12 Audio codec

4 Mechanical Information

4.1 Device physical dimensions

4.2 Part marking

4.3 Device ordering information

4.4 Device moisture-sensitivity level

5 Carrier, Storage, and Handling

Information

5.1 Carrier

5.2 Storage

5.3 Handling

6 PCB Mounting Guidelines

6.1 RoHS compliance

6.2 SMT parameters

6.3 Board-level reliability

7 Part Reliability

7.1 Reliability qualifications summary

7.2 Qualification sample description

Device characteristics

A Exhibit 1

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Table of contents