UM10398 LPC111x/LPC11Cxx User manual

UM10398 LPC111x/LPC11Cxx User manual

UM10398

LPC111x/LPC11Cxx User manual

Rev. 12.4 — 22 December 2016 User manual

Document information

Info

Keywords

Content

ARM Cortex-M0, LPC1111, LPC1112, LPC1113, LPC1114, LPC1115,

LPC11C12, LPC11C14, LPC1100, LPC1100L, LPC11C00, LPC11C22,

LPC11C24, LPC11D14, LPC1100XL

Abstract

LPC111x/LPC11Cxx User manual

NXP Semiconductors

UM10398

LPC111x/LPC11Cxx User manual

Revision history

Rev Date Description

12.4

Modifications:

12.3

20161222

LPC111x/LPC11C1x/LPC11C2x User manual

Added part LPC111x/303 to the LPC1100XL series. See

Section 1.1 “Introduction” .

Update Bit 7 (RX) of Table 251 “CAN test register (CANTEST, address 0x4005 0014) bit description”

:

0: Dominant. The CAN bus is dominant (CAN_RXD = 0).

1: Recessive. The CAN bus is recessive (CAN_RXD = 1).

Updated

Section 26.3.1 “Bootloader” : Added text:

PIO1_6 is ISP_RXD and PIO1_7 is ISP_TXD.

20140610 LPC111x/LPC11C1x/LPC11C2x User manual

Modifications:

Section 5.2

added to describe the requirement to disable all interrupts before calling the power profiles and the requirement to use default mode when calling the IAP functions.

12.2

Modifications:

20140324

LPC111x/LPC11C1x/LPC11C2x User manual

Parts LPC1112JHI33/203, LPC1114JHN33/333, LPC1115JET48/303, and LPC1115JBD48/303 added.

C_CAN Figure 67 “Bit timing” and TSEG1 bit description in Table 249 “CAN bit timing register (CANBT, address 0x4005 000C) bit description” updated for clarification.

Section 16.7.5.2 “Calculating the C_CAN bit rate” added.

Parts added: LPC1114JHI33/303, LPC1111JHN33/103, LPC1112JHN33/203, LPC1113JHN33/203,

LPC1114JHN33/303, LPC1114JBD48/333, LPC1112FHI33/102, LPC1114JBD48/303,

LPC1114JBD48/323, LPC1113JHN33/303, LPC1112JHN33/103, LPC1111JHN33/203,

LPC1114JHN33/203.

Pin description tables for RESET/PIO0_0 updated: In deep power-down mode, this pin must be pulled

HIGH externally. The RESET pin can be left unconnected or be used as a GPIO pin if an external

RESET function is not needed.

Pin description notes relating to open-drain I2C-bus pins updated for clarity.

Pin description of the WAKEUP pin updated for clarity.

Remark added to Section 3.9.3.3 “Wake-up from Deep-sleep mode”: After wake-up, reprogram the clock source for the main clock.

12.1

Modifications:

20130807

LPC111x/LPC11C1x/LPC11C2x User manual

Remove instruction breakpoints from feature list for SWD. See Section 27.2.

IRQLATENCY register added in SYSCON block. See Table 35.

Reset value of the C_CAN CANCLKDIV register changed to 0x1, See Table 275.

RAM used by ISP sizes updated. See Section 26.4.8, Section 26.4.9.

SSEL1_LOC Register description corrected. See Table 152.

Added LPC1115FET48.

Editorial updates.

Updated Go command Section 26.5.8.

12

Modifications:

20120924

LPC111x/LPC11C1x/LPC11C2x User manual

BOD level 0 for reset added. See Table 33.

Description of the TEMT bit in the UART LSR register updated. See Table 196.

11

Modifications:

10

20120726

LPC111x/LPC11C1x/LPC11C2x User manual

Function SSEL1 added to pin PIO2_0 in Table 170 and Figure 28.

BOD level 0 for reset and interrupt removed.

20120626 LPC111x/LPC11C1x/LPC11C2x User manual

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Rev. 12.4 — 22 December 2016

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LPC111x/LPC11Cxx User manual

Revision history

…continued

Rev

Modifications:

Date

Description

LPC1112FHN24 pinout corrected in Table 161 and Figure 18.

Description of BYPASS bit corrected in Table 12 “System oscillator control register (SYSOSCCTRL, address 0x4004 8020) bit description”.

Contact information

For more information, please visit:

http://www.nxp.com

For sales office addresses, please send an email to:

[email protected]

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User manual

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Rev. 12.4 — 22 December 2016

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Chapter :

3

2

1

5

4

7

6

Revision history

…continued

Rev Date Description

9

Modifications:

8

20120517

LPC111x/LPC11C1x/LPC11C2x/LPC11D14 User manual

LPC11D14/PCF8576D block diagram updated (see Figure 5).

Description of interrupt use with IAP calls updated (see Section 26.4.7).

SYSRSTSTAT register access changed to R/W (Table 7).

Frequency values for FREQSEL bits in the WDTOSCCTRL register corrected (see Table 13).

Figure 9 updated (RESET changed to internal reset).

Limit number of bytes copied in Copy RAM to flash ISP and IAP commands for parts with less than

4 kB SRAM (see Table 381 and Table 396).

Figure 14 updated with pseudo open-drain mode.

Part LPC1112FHN24/202 added.

Part IDs added for parts LPC1110FD20, LPC1111FDH20/002, LPC1112FD20/102,

LPC1112FDH20/102, LPC1112FDH28/102, LPC1114FDH28/102, LPC1114FN28/102.

SRAM use by bootloader specified in Section 26.3.1.

20120308 LPC111x/LPC11C1x/LPC11C2x User manual

20110919

20110822

20110621

20110304

20110114

20101102

20100721

LPC111x/LPC11C1x/LPC11C2x User manual

LPC111x/LPC11C1x/LPC11C2x User manual

LPC111x/LPC11C1x/LPC11C2x User manual

LPC111x/LPC11C1x/LPC11C2x User manual

LPC111x/LPC11C1x/LPC11C2x User manual

LPC111x/LPC11C1x User manual

LPC111x/LPC11C1x User manual

UM10398

User manual

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Rev. 12.4 — 22 December 2016

© NXP B.V. 2016. All rights reserved.

4 of 548

UM10398

Chapter 1: LPC111x/LPC11Cxx Introductory information

Rev. 12.4 — 22 December 2016 User manual

1.1 Introduction

The LPC111x/LPC11Cxx are a ARM Cortex-M0 based, low-cost 32-bit MCU family, designed for 8/16-bit microcontroller applications, offering performance, low power, simple instruction set and memory addressing together with reduced code size compared to existing 8/16-bit architectures.

The LPC111x/LPC11Cxx operate at CPU frequencies of up to 50 MHz.

The peripheral complement of the LPC111x/LPC11Cxx includes up to 32 kB of flash memory, up to 8 kB of data memory, one C_CAN controller (LPC11Cxx), one Fast-mode

Plus I

2

C-bus interface, one RS-485/EIA-485 UART, up to two SPI interfaces with SSP features, four general purpose timers, a 10-bit ADC, and up to 42 general purpose I/O pins.

On-chip C_CAN drivers and flash In-System Programming tools via C_CAN are included on the LPC11Cxx. In addition, parts LPC11C2x are equipped with an on-chip CAN transceiver.

Remark:

This user manual covers the LPC111x/LPC11Cxx parts and the LPC11D14 dual-chip part with PCF8576D LCD controller. The LPC111x/LPC11Cxx parts are grouped by the following series and part names (see

Table 1

for a feature overview):

LPC1100 series (parts LPC111x/101/201/301)

LPC1100L series (parts LPC111x/102/202/302) and part LPC11D14 with LCD controller.

LPC1100XL series (parts LPC111x/103/203/303/323/333)

LPC11C00 series (parts LPC11C1x/301 and LPC11C2x/301) with C_CAN controller.

For related documentation, see Section 29.2 “References”

.

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User manual

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Rev. 12.4 — 22 December 2016

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UM10398

Chapter 1: LPC111x/LPC11Cxx Introductory information

Table 1.

LPC111x/LPC11Cxx feature changes

Series

LPC1100 series

LPC1100L series

LPC1100XL series

LPC11C00 series

Features overview

I2C, SSP, UART, GPIO

Timers and watch dog timer

10-bit ADC

Flash/SRAM memory

For a full feature list, see

Section 1.2

.

LPC1100 series features plus the following additional features:

Power profiles with lower power consumption in Active and Sleep modes.

Internal pull-up resistors pull up pins to full V

DD

level.

Programmable pseudo open-drain mode for GPIO pins.

WWDT with clock source lock capability.

Small packages (TSSOP, SO, DIP, HVQFN)

LPC1100L series features plus the following new features:

Flash page erase In-Application Programming (IAP) function.

Timer, UART, and SSP functions pinned out on additional pins.

One capture function added for each timer.

Capture-clear feature on the 16-bit and 32-bit timers for easy pulse-width measurements.

LPC1100 series features plus the following additional features:

CAN controller.

On-chip CAN drivers.

On-chip CAN transceiver (LPC11C2x).

WDT (not windowed) with clock source lock capability.

LPC1100L series with LCD controller PCF8576D in a dual-chip package.

LPC11D14

(LPC1100L series)

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Chapter 1: LPC111x/LPC11Cxx Introductory information

1.2 Features

UM10398

User manual

System:

ARM Cortex-M0 processor, running at frequencies of up to 50 MHz.

ARM Cortex-M0 built-in Nested Vectored Interrupt Controller (NVIC).

Serial Wire Debug.

System tick timer.

Memory:

On-chip flash programming memory for LPC1100, LPC1100L, and LPC1100C series: 32 kB (LPC1114/LPC11C14), 24 kB (LPC1113), 16 kB

(LPC1112/LPC11C12), or 8 kB (LPC1111), 4kB (LPC1110).

On-chip flash programming memory for LPC1100XL series: 8 kB (LPC1111), 16 kB

(LPC1112), 24 kB (LPC1113), 32 kB (LPC1114/203/303), 48 kB (LPC1114/323),

56 kB (LPC1114/333), 64 kB (LPC1115).

8 kB, 4 kB, 2 kB, or 1 kB SRAM.

In-System Programming (ISP) and In-Application Programming (IAP) via on-chip bootloader software.

LPC1100XL series only: page erase IAP command.

Digital peripherals:

Up to 42 General Purpose I/O (GPIO) pins with configurable pull-up/pull-down resistors. Number of GPIO pins is reduced for smaller packages and

LPC11C22/C24.

GPIO pins can be used as edge and level sensitive interrupt sources.

High-current output driver (20 mA) on one pin.

High-current sink drivers (20 mA) on two I

2

C-bus pins in Fast-mode Plus.

Four general purpose timers/counters with a total of four capture inputs and up to

13 match outputs.

Programmable WatchDog Timer (WDT).

Analog peripherals:

10-bit ADC with input multiplexing among up to 8 pins.

Serial interfaces:

UART with fractional baud rate generation, internal FIFO, and RS-485 support.

Two SPI controllers with SSP features and with FIFO and multi-protocol capabilities (second SPI on LQFP48 packages only).

I

2

C-bus interface supporting full I

2

C-bus specification and Fast-mode Plus with a data rate of 1 Mbit/s with multiple address recognition and monitor mode.

C_CAN controller (LPC11Cxx only). On-chip CAN and CANopen drivers included.

On-chip, high-speed CAN transceiver (parts LPC11C22/C24 only).

Clock generation:

12 MHz internal RC oscillator trimmed to 1% accuracy that can optionally be used as a system clock.

Crystal oscillator with an operating range of 1 MHz to 25 MHz.

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Rev. 12.4 — 22 December 2016

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Chapter 1: LPC111x/LPC11Cxx Introductory information

Programmable watchdog oscillator with a frequency range of 7.8 kHz to 1.8 MHz.

PLL allows CPU operation up to the maximum CPU rate without the need for a high-frequency crystal. May be run from the system oscillator or the internal RC oscillator.

Clock output function with divider that can reflect the system oscillator clock, IRC clock, CPU clock, and the Watchdog clock.

Power control:

Integrated PMU (Power Management Unit) to minimize power consumption during

Sleep, Deep-sleep, and Deep power-down modes.

Power profiles residing in boot ROM allowing to optimize performance and minimize power consumption for any given application through one simple function call. (On LPC1100L and LPC1100XL parts only).

Three reduced power modes: Sleep, Deep-sleep, and Deep power-down.

Processor wake-up from Deep-sleep mode via a dedicated start logic using up to

13 of the functional pins.

Power-On Reset (POR).

Brownout detect with up to four separate thresholds for interrupt and forced reset.

Unique device serial number for identification.

Single 3.3 V power supply (1.8 V to 3.6 V).

Available as LQFP48 package, HVQFN33 package.

LPC1100L series also available as HVQFN24, TSSOP28 package, DIP28 package,

TSSOP20 package, and SO20 package.

Available as dual-chip module consisting of the LPC1114 single-chip microcontroller combined with a PCF8576D Universal LCD driver in a 100-pin LQFP package (part

LPC11D14FBD100/302).

1

1.

For details on the PCF8576D operation, see

Ref. 3 .

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UM10398

Chapter 1: LPC111x/LPC11Cxx Introductory information

1.3 Ordering information

Table 2.

Type number

Ordering information

Package

Name Description

SO20, TSSOP20, TSSOP28, and DIP28 packages

LPC1110FD20

LPC1111FDH20/002

LPC1112FD20/102

LPC1112FDH20/102

SO20

TSSOP20

SO20

TSSOP20

SO20: plastic small outline package; 20 leads; body width 7.5 mm

TSSOP20: plastic thin shrink small outline package; 20 leads; body width 4.4 mm

SO20: plastic small outline package; 20 leads; body width 7.5 mm

TSSOP20: plastic thin shrink small outline package; 20 leads; body width 4.4 mm

Version

SOT163-1

SOT360-1

SOT163-1

SOT360-1

LPC1112FDH28/102 TSSOP28

LPC1114FDH28/102 TSSOP28

TSSOP28: plastic thin shrink small outline package; 28 leads; body width 4.4 mm

SOT361-1

TSSOP28: plastic thin shrink small outline package; 28 leads; body width 4.4 mm

SOT361-1

LPC1114FN28/102 DIP28 DIP28: plastic dual in-line package; 28 leads (600 mil)

HVQFN24/33, LQFP48, and TFBGA48 packages

LPC1111FHN33/101 HVQFN33

LPC1111FHN33/102

LPC1111FHN33/201

LPC1111FHN33/202

LPC1111FHN33/103

LPC1111JHN33/103

LPC1111FHN33/203

LPC1111JHN33/203

LPC1112FHN33/101

LPC1112FHN33/102

LPC1112FHN33/201

LPC1112FHN33/202

LPC1112FHN24/202

HVQFN33

HVQFN33

HVQFN33

HVQFN33

HVQFN33

HVQFN33

HVQFN33

HVQFN33

HVQFN33

HVQFN33

HVQFN33

HVQFN24

SOT117-1

HVQFN: plastic thermal enhanced very thin quad flat package; no leads; 33 terminals; body 7

7

0.85 mm

HVQFN: plastic thermal enhanced very thin quad flat package; no leads; 33 terminals; body 7

7

0.85 mm

HVQFN: plastic thermal enhanced very thin quad flat package; no leads; 33 terminals; body 7

7

0.85 mm

HVQFN: plastic thermal enhanced very thin quad flat package; no leads; 33 terminals; body 7

7

0.85 mm

HVQFN: plastic thermal enhanced very thin quad flat package; no leads; 33 terminals; body 7

7

0.85 mm

HVQFN: plastic thermal enhanced very thin quad flat package; no leads; 33 terminals; body 7

7

0.85 mm

HVQFN: plastic thermal enhanced very thin quad flat package; no leads; 33 terminals; body 7

7

0.85 mm

HVQFN: plastic thermal enhanced very thin quad flat package; no leads; 33 terminals; body 7

7

0.85 mm n/a n/a n/a n/a n/a n/a n/a n/a

HVQFN: plastic thermal enhanced very thin quad flat package; no leads; 33 terminals; body 7

7

0.85 mm

HVQFN: plastic thermal enhanced very thin quad flat package; no leads; 33 terminals; body 7

7

0.85 mm

HVQFN: plastic thermal enhanced very thin quad flat package; no leads; 33 terminals; body 7

7

0.85 mm

HVQFN: plastic thermal enhanced very thin quad flat package; no leads; 33 terminals; body 7

7

0.85 mm n/a n/a n/a n/a

HVQFN24: plastic thermal enhanced very thin quad flat package; no leads; 24 terminals; body 4 x 4 x 0.85 mm

SOT616-3

LPC1112FHI33/102

LPC1112FHI33/202

HVQFN33

HVQFN33

HVQFN: plastic thermal enhanced very thin quad flat package; no leads; 33 terminals; body 5

5

0.85 mm

HVQFN: plastic thermal enhanced very thin quad flat package; no leads; 33 terminals; body 5

5

0.85 mm n/a n/a

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Rev. 12.4 — 22 December 2016

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Chapter 1: LPC111x/LPC11Cxx Introductory information

Table 2.

Ordering information

…continued

Type number Package

Name Description

LPC1112FHI33/203

LPC1112JHI33/203

LPC1112FHN33/103

LPC1112JHN33/103

LPC1112JHN33/203

LPC1112FHN33/203

LPC1113FHN33/201

LPC1113FHN33/202

LPC1113FHN33/203

LPC1113JHN33/203

LPC1113FHN33/301

LPC1113FHN33/302

LPC1113FHN33/303

LPC1113JHN33/303

LPC1114FHN33/201

LPC1114FHN33/202

LPC1114FHN33/301

LPC1114FHN33/302

LPC1114FHI33/302

LPC1114FHI33/303

LPC1114JHI33/303

LPC1114FHN33/203

LPC1114JHN33/203

HVQFN33

HVQFN33

HVQFN33

HVQFN33

HVQFN33

HVQFN33

HVQFN33

HVQFN33

HVQFN33

HVQFN33

HVQFN33

HVQFN33

HVQFN33

HVQFN33

HVQFN33

HVQFN33

HVQFN33

HVQFN33

HVQFN33

HVQFN33

HVQFN33

HVQFN33

HVQFN33

HVQFN: plastic thermal enhanced very thin quad flat package; no leads; 33 terminals; body 5

5

0.85 mm

HVQFN: plastic thermal enhanced very thin quad flat package; no leads; 33 terminals; body 5

5

0.85 mm

HVQFN: plastic thermal enhanced very thin quad flat package; no leads; 33 terminals; body 7

7

0.85 mm

HVQFN: plastic thermal enhanced very thin quad flat package; no leads; 33 terminals; body 7

7

0.85 mm

HVQFN: plastic thermal enhanced very thin quad flat package; no leads; 33 terminals; body 7

7

0.85 mm

HVQFN: plastic thermal enhanced very thin quad flat package; no leads; 33 terminals; body 7

7

0.85 mm

HVQFN: plastic thermal enhanced very thin quad flat package; no leads; 33 terminals; body 7

7

0.85 mm

HVQFN: plastic thermal enhanced very thin quad flat package; no leads; 33 terminals; body 7

7

0.85 mm

HVQFN: plastic thermal enhanced very thin quad flat package; no leads; 33 terminals; body 7

7

0.85 mm

HVQFN: plastic thermal enhanced very thin quad flat package; no leads; 33 terminals; body 7

7

0.85 mm

HVQFN: plastic thermal enhanced very thin quad flat package; no leads; 33 terminals; body 7

7

0.85 mm

HVQFN: plastic thermal enhanced very thin quad flat package; no leads; 33 terminals; body 7

7

0.85 mm

HVQFN: plastic thermal enhanced very thin quad flat package; no leads; 33 terminals; body 7

7

0.85 mm

HVQFN: plastic thermal enhanced very thin quad flat package; no leads; 33 terminals; body 7

7

0.85 mm

HVQFN: plastic thermal enhanced very thin quad flat package; no leads; 33 terminals; body 7

7

0.85 mm

HVQFN: plastic thermal enhanced very thin quad flat package; no leads; 33 terminals; body 7

7

0.85 mm

HVQFN: plastic thermal enhanced very thin quad flat package; no leads; 33 terminals; body 7

7

0.85 mm

HVQFN: plastic thermal enhanced very thin quad flat package; no leads; 33 terminals; body 7

7

0.85 mm

HVQFN: plastic thermal enhanced very thin quad flat package; no leads; 33 terminals; body 5

5

0.85 mm

HVQFN: plastic thermal enhanced very thin quad flat package; no leads; 33 terminals; body 5

5

0.85 mm

HVQFN: plastic thermal enhanced very thin quad flat package; no leads; 33 terminals; body 5

5

0.85 mm

HVQFN: plastic thermal enhanced very thin quad flat package; no leads; 33 terminals; body 7

7

0.85 mm

HVQFN: plastic thermal enhanced very thin quad flat package; no leads; 33 terminals; body 7

7

0.85 mm

Version

n/a n/a n/a n/a n/a n/a n/a n/a n/a n/a n/a n/a n/a n/a n/a n/a n/a n/a n/a n/a n/a n/a n/a

UM10398

User manual

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Rev. 12.4 — 22 December 2016

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10 of 548

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UM10398

Chapter 1: LPC111x/LPC11Cxx Introductory information

Table 2.

Ordering information

…continued

Type number Package

Name Description

LPC1114FHN33/303

LPC1114JHN33/303

LPC1114FHN33/333

LPC1114JHN33/333

LPC1113FBD48/301

LPC1113FBD48/302

LPC1113FBD48/303

LPC1113JBD48/303

LPC1114FBD48/301

LPC1114FBD48/302

LPC1114FBD48/303

LPC1114JBD48/303

LPC1114FBD48/323

LPC1114JBD48/323

LPC1114FBD48/333

LPC1114JBD48/333

LPC1115FBD48/303

LPC1115JBD48/303

LPC1115FET48/303

LPC1115JET48/303

HVQFN33

HVQFN33

HVQFN33

HVQFN33

LQFP48

LQFP48

LQFP48

LQFP48

LQFP48

LQFP48

LQFP48

LQFP48

LQFP48

LQFP48

LQFP48

LQFP48

LQFP48

LQFP48

TFBGA48

TFBGA48

Version

HVQFN: plastic thermal enhanced very thin quad flat package; no leads; 33 terminals; body 7

7

0.85 mm

HVQFN: plastic thermal enhanced very thin quad flat package; no leads; 33 terminals; body 7

7

0.85 mm n/a n/a

HVQFN: plastic thermal enhanced very thin quad flat package; no leads; 33 terminals; body 7

7

0.85 mm n/a

HVQFN: plastic thermal enhanced very thin quad flat package; no leads; 33 terminals; body 7

7

0.85 mm

LQFP48: plastic low profile quad flat package; 48 leads; body 7

7

1.4 mm

LQFP48: plastic low profile quad flat package; 48 leads; body 7

7

1.4 mm

LQFP48: plastic low profile quad flat package; 48 leads; body 7

7

1.4 mm

LQFP48: plastic low profile quad flat package; 48 leads; body 7

7

1.4 mm

LQFP48: plastic low profile quad flat package; 48 leads; body 7

7

1.4 mm

LQFP48: plastic low profile quad flat package; 48 leads; body 7

7

1.4 mm

LQFP48: plastic low profile quad flat package; 48 leads; body 7

7

1.4 mm

LQFP48: plastic low profile quad flat package; 48 leads; body 7

7

1.4 mm

LQFP48: plastic low profile quad flat package; 48 leads; body 7

7

1.4 mm

LQFP48: plastic low profile quad flat package; 48 leads; body 7

7

1.4 mm

LQFP48: plastic low profile quad flat package; 48 leads; body 7

7

1.4 mm

LQFP48: plastic low profile quad flat package; 48 leads; body 7

7

1.4 mm

LQFP48: plastic low profile quad flat package; 48 leads; body 7

7

1.4 mm

LQFP48: plastic low profile quad flat package; 48 leads; body 7

7

1.4 mm plastic thin fine-pitch ball grid array package; 48 balls; body 4.5

4.5

0.7 mm plastic thin fine-pitch ball grid array package; 48 balls; body 4.5

4.5

0.7 mm n/a

SOT313-2

SOT313-2

SOT313-2

SOT313-2

SOT313-2

SOT313-2

SOT313-2

SOT313-2

SOT313-2

SOT313-2

SOT313-2

SOT313-2

SOT313-2

SOT313-2

SOT1155-2

SOT1155-2

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Table 3.

Type number

Ordering options

Series Flash

UM10398

Chapter 1: LPC111x/LPC11Cxx Introductory information

Package

yes yes yes yes yes yes no yes yes yes yes yes no yes yes yes

1

2

2

2

2

1

1

2

1

1

2

1

1

1

1

1

8

8

8

8

8

6

8

8

8

8

8

8

8

5

5

6

8

8

8

8

8

8

8

5

8

8

8

8

8

8

5

8

8

16 F SO20

28

28

28

28

16

28

28

28

28

F

F

F

J

F

J

F

F

F

-

-

-

-

-

-

-

-

TSSOP20

HVQFN33

HVQFN33

HVQFN33

HVQFN33

HVQFN33

HVQFN33

HVQFN33

HVQFN33

28

28

28

28

28

28

28

19

28

28

28

28

28

16

14

22

F

F

F

J

J

F

F

J

F

F

F

F

F

F

F

F

-

-

-

-

-

-

-

-

-

-

-

-

-

-

-

SO20

TSSOP20

TSSOP28

HVQFN33

HVQFN33

HVQFN33

HVQFN33

HVQFN33

HVQFN33

HVQFN24

HVQFN33

HVQFN33

HVQFN33

HVQFN33

HVQFN33

HVQFN33

28

28

28

28

28

28

28

F

F

F

F

J

F

F

-

-

-

-

-

-

HVQFN33

HVQFN33

HVQFN33

HVQFN33

HVQFN33

HVQFN33

HVQFN33

© NXP B.V. 2016. All rights reserved.

12 of 548

NXP Semiconductors

Table 3.

Ordering options

…continued

Type number Series Flash

UM10398

Chapter 1: LPC111x/LPC11Cxx Introductory information

Package

LPC1113JHN33/303

LPC1113FBD48/301

LPC1113FBD48/302

LPC1113FBD48/303

LPC1113JBD48/303

LPC1114

LPC1114FDH28/102

LPC1114FN28/102

LPC1114FHN33/201

LPC1114FHN33/202

LPC1114FHN33/203

LPC1114JHN33/203

LPC1114FHN33/301

LPC1114FHN33/302

LPC1114FHN33/303

LPC1114JHN33/303

LPC1114FHN33/333

LPC1114JHN33/333

LPC1114FHI33/302

LPC1114FHI33/303

LPC1114JHI33/303

LPC1114FBD48/301

LPC1114FBD48/302

LPC1114FBD48/303

LPC1114JBD48/303

LPC1114FBD48/323

LPC1114JBD48/323

LPC1114FBD48/333

LPC1114JBD48/333

LPC1115

LPC1115FET48/303

LPC1115JET48/303

LPC1115FBD48/303

LPC1115JBD48/303

LPC11C12/LPC11C14

LPC11C12FBD48/301

LPC11C14FBD48/301

LPC1100XL

LPC1100

LPC1100L

LPC1100XL

LPC1100XL

LPC1100XL

LPC1100XL

LPC1100XL

LPC1100XL

LPC11C00

LPC11C00

24 kB

24 kB

24 kB

24 kB

24 kB

64 kB

64 kB

64 kB

64 kB

16 kB

32 kB

32 kB

32 kB

56 kB

56 kB

32 kB

32 kB

32 kB

32 kB

32 kB

32 kB

32 kB

32 kB

32 kB

32 kB

32 kB

32 kB

32 kB

32 kB

32 kB

48 kB

48 kB

56 kB

56 kB

LPC1100L

LPC1100L

LPC1100

LPC1100L

LPC1100XL

LPC1100XL

LPC1100

LPC1100L

LPC1100XL

LPC1100XL

LPC1100XL

LPC1100XL

LPC1100L

LPC1100XL

LPC1100XL

LPC1100

LPC1100L

LPC1100XL

LPC1100XL

LPC1100XL

LPC1100XL

LPC1100XL

LPC1100XL

UM10398

User manual

8 kB

8 kB

8 kB

8 kB

8 kB

8 kB

8 kB

8 kB

8 kB

8 kB

8 kB

8 kB

8 kB

4 kB

4 kB

4 kB

4 kB

4 kB

4 kB

8 kB

8 kB

8 kB

8 kB

8 kB

8 kB

8 kB

8 kB

8 kB

8 kB

8 kB

8 kB

8 kB

8 kB

8 kB

1

1

1

1

1

1

1

1

1

1

1

1

1

1

1

1

1

1

1

1

1

1

1

1

1

1

1

1

1

1

1

1

1

1

1

1

1

1

1

1

1

1

1

1

1

1

1

1

1

1

1

1

1

1

1

1

1

1

1

1

1

1

1

1

1

1

1

1

2

2

2

2

2

2

2

2

2 yes no yes yes yes yes yes yes yes

2

2 no no

All information provided in this document is subject to legal disclaimers.

Rev. 12.4 — 22 December 2016

8

8

8

8

8

8

8

8

8

8

8 yes yes yes no yes yes yes yes yes yes no yes yes yes no yes yes yes yes yes yes yes yes

2

2

1

2

2

2

2

2

1

1

2

2

1

1

1

1

2

2

2

2

2

2

2

8

8

8

8

8

8

8

8

8

8

8

8

8

8

6

6

8

8

8

8

8

8

8

28

42

42

42

42

-

-

-

-

-

F

F

J

F

J

HVQFN33

LQFP48

LQFP48

LQFP48

LQFP48

28

28

28

42

28

28

28

28

28

28

28

28

22

22

28

28

42

42

42

42

42

42

42

J

F

F

F

F

J

F

J

F

F

F

J

F

F

F

F

J

F

J

J

F

F

F -

-

-

-

-

-

-

-

-

-

-

-

-

-

-

-

-

-

-

-

-

TSSOP28

DIP28

HVQFN33

HVQFN33

HVQFN33

HVQFN33

HVQFN33

HVQFN33

HVQFN33

HVQFN33

HVQFN33

HVQFN33

HVQFN33

HVQFN33

HVQFN33

LQFP48

LQFP48

LQFP48

LQFP48

LQFP48

LQFP48

LQFP48

LQFP48

42

42

42

42 -

-

-

-

F

J

F

J

TFBGA48

TFBGA48

LQFP48

LQFP48

40

40

1

1

F

F

LQFP48

LQFP48

© NXP B.V. 2016. All rights reserved.

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NXP Semiconductors

Table 3.

Ordering options

…continued

Type number Series Flash

UM10398

Chapter 1: LPC111x/LPC11Cxx Introductory information

Package

LPC11C22/LPC11C24 with on-chip, high-speed CAN transceiver

LPC11C22FBD48/301 LPC11C00 16 kB 8 kB 1 1

LPC11C24FBD48/301 LPC11C00 32 kB 8 kB 1

LPC11D14 dual-chip module with PCF8576D LCD driver

1

LPC11D14FBD100/302 LPC1100L 32 kB 8 kB 1 1

2

2

2

[1] F =

40

C to +85

C, J =

40

C to +105

C.

no no yes

8

8

8

36

36

1

1

F

F

LQFP48

LQFP48

42 F LQFP100

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User manual

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UM10398

Chapter 1: LPC111x/LPC11Cxx Introductory information

1.4 Block diagram

SWD

XTALIN

XTALOUT

(3)

RESET

GPIO ports

PIO0/1/2/3

RXD

TXD

DTR, DSR, CTS

(5)

,

DCD, RI, RTS

(5)

CT32B0_MAT[3:0]

(3)

CT32B0_CAP0

(3)

CT32B1_MAT[3:0]

(3)

CT32B1_CAP0

(3)

CT16B0_MAT[2:0]

(3)

CT16B0_CAP0

(3)

CT16B1_MAT[1:0]

(3)

CT16B1_CAP0

(3)

LPC1110/11/12/13/14

HIGH-SPEED

GPIO slave

TEST/DEBUG

INTERFACE

ARM

CORTEX-M0

system bus

IRC

POR

CLOCK

GENERATION,

POWER CONTROL,

SYSTEM

FUNCTIONS clocks and controls

FLASH

4/8/16/24/32 kB slave

SRAM

1/2/4/8 kB slave slave

ROM

AHB-LITE BUS slave

AHB TO APB

BRIDGE

UART

10-bit ADC

32-bit COUNTER/TIMER 0

32-bit COUNTER/TIMER 1

16-bit COUNTER/TIMER 0

16-bit COUNTER/TIMER 1

SPI0

SPI1

(1)

I

2

C-BUS

(2)

WDT

IOCONFIG

CLKOUT

AD[7:0]

(4)

SCK0, SSEL0

MISO0, MOSI

SCK1, SSEL1

MISO1, MOSI

SCL

SDA

SYSTEM CONTROL

PMU

002aae696

(1) LQFP48 packages only.

(2) Not on LPC1112FDH20/102.

(3) All pins available on LQFP48 and HVQFN33 packages. CT16B1_MAT1 not available on TSSOP28/DIP28 packages.

CT32B1_MAT3, CT16B1_CAP0, CT16B1_MAT[1:0], CT32B0_CAP0 not available on TSSOP20/SO20 packages.

CT16B1_MAT[1:0], CT32B0_CAP0 not available on the HVQFN24 package. XTALOUT not available on LPC1112FHN24.

(4) AD[7:0] available on LQFP48 and HVQFN33 packages. AD[5:0] available on TSSOP28/DIP28/HVQFN24packages. AD[4:0] available on TSSOP20/SO20 packages.

(5) All pins available on LQFP48 packages. RXD, TXD, DTR, CTS, RTS available on HVQFN 33 packages. RXD, TXD, CTS, RTS available on TSSOP28/DIP28 packages. RXD, TXD available on TSSOP20/SO20 packages.

Fig 1.

LPC111x block diagram (LPC1100 and LPC1100L series)

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User manual

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UM10398

Chapter 1: LPC111x/LPC11Cxx Introductory information

SWD

XTALIN

XTALOUT

RESET

GPIO ports

PIO0/1/2/3

RXD

TXD

DTR, DSR

(1)

, CTS,

DCD

(1)

, RI

(1)

, RTS

CT32B0_MAT[3:0]

CT32B0_CAP[1:0]

CT32B1_MAT[3:0]

CT32B1_CAP[1:0]

CT16B0_MAT[2:0]

CT16B0_CAP[1:0]

CT16B1_MAT[1:0]

CT16B1_CAP[1:0]

LPC1111/12/13/14/15XL

TEST/DEBUG

INTERFACE

ARM

CORTEX-M0

system bus

HIGH-SPEED

GPIO slave

UART

32-bit COUNTER/TIMER 0

32-bit COUNTER/TIMER 1

16-bit COUNTER/TIMER 0

16-bit COUNTER/TIMER 1

IRC

POR

CLOCK

GENERATION,

POWER CONTROL,

SYSTEM

FUNCTIONS

FLASH

8/16/24/32/

48/56/64 kB slave

SRAM

2/4/8 kB slave slave

ROM clocks and controls

AHB-LITE BUS slave

AHB TO APB

BRIDGE

10-bit ADC

SPI0

SPI1

I

2

C-BUS

WWDT

IOCONFIG

SYSTEM CONTROL

PMU

002aag780

CLKOUT

AD[7:0]

SCK0, SSEL0

MISO0, MOSI0

SCK1, SSEL1

MISO1, MOSI1

SCL

SDA

(1) Available on LQFP packages only.

Fig 2.

LPC111x block diagram (LPC1100XL series)

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User manual

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UM10398

Chapter 1: LPC111x/LPC11Cxx Introductory information

GPIO ports

PIO0/1/2/3

RXD

TXD

DTR, DSR, CTS,

DCD, RI, RTS

CT32B0_MAT[3:0]

CT32B0_CAP0

CT32B1_MAT[3:0]

CT32B1_CAP0

CT16B0_MAT[2:0]

CT16B0_CAP0

CT16B1_MAT[1:0]

(1)

CT16B1_CAP0

CAN_TXD

CAN_RXD

CANL, CANH

STB

V

CC

, VDD_CAN

SWD

XTALIN

XTALOUT

RESET

LPC11Cxx

LPC11D14

TEST/DEBUG

INTERFACE

ARM

CORTEX-M0

system bus

HIGH-SPEED

GPIO slave

UART

32-bit COUNTER/TIMER 0

32-bit COUNTER/TIMER 1

16-bit COUNTER/TIMER 0

16-bit COUNTER/TIMER 1

IRC

POR

CLOCK

GENERATION,

POWER CONTROL,

SYSTEM

FUNCTIONS clocks and controls

FLASH

16/32 kB slave slave

SRAM

8 kB slave

ROM

AHB-LITE BUS slave

AHB TO APB

BRIDGE

10-bit ADC

SPI0

SPI1

I

2

C-BUS

C_CAN (LPC11C12/C14)

C_CAN/

ON-CHIP TRANSCEIVER

(LPC11C22/C24)

WDT

IOCONFIG

SYSTEM CONTROL

PMU

(1) Not available on LPC11C22/C24.

Fig 3.

LPC11Cxx/LPC11D14 block diagram (LPC1100C series and LPC11D14)

CLKOUT

AD[7:0]

SCK0, SSEL0

MISO0, MOSI0

SCK1, SSEL1

MISO1, MOSI1

SCL

SDA

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NXP Semiconductors

PIO0, PIO1, PIO2, PIO3

LPC1114

MCU

UM10398

Chapter 1: LPC111x/LPC11Cxx Introductory information

PCF8576D

LCD

CONTROLLER

S[39:0]

BP[3:0]

V

LCD

002aag449

Fig 4.

LPC11D14 block diagram

V

LCD

BP0 BP2 BP1 BP3

BACKPLANE

OUTPUTS

LCD

VOLTAGE

SELECTOR

LCD BIAS

GENERATOR

V

SS(LCD)

CLK

SYNC

CLOCK SELECT

AND TIMING

V

SS(LCD)

OSC

OSCILLATOR

V

DD(LCD)

LCD_SCL

LCD_SDA

INPUT

FILTERS

BLINKER

TIMEBASE

POWER-ON

RESET

I

2

C-BUS

CONTROLLER

SA0

V

SS(LCD)

DISPLAY

CONTROLLER

PCF8576D

COMMAND

DECODER

WRITE DATA

CONTROL

S0 to S39

40

DISPLAY SEGMENT

OUTPUTS

DISPLAY

REGISTER

OUTPUT BANK SELECT

AND BLINK CONTROL

DISPLAY RAM

40 x 4-BIT

DATA POINTER AND

AUTO INCREMENT

A0

SUBADDRESS

COUNTER

A1 A2

V

SS(LCD)

002aag451

Fig 5.

PCF8576D block diagram

UM10398

User manual

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UM10398

Chapter 1: LPC111x/LPC11Cxx Introductory information

1.5 ARM Cortex-M0 processor

The ARM Cortex-M0 processor is described in detail in Section 28.3 “About the

Cortex-M0 processor and core peripherals” . For the LPC111x/LPC11Cxx, the ARM

Cortex-M0 processor core is configured as follows:

System options:

The Nested Vectored Interrupt Controller (NVIC) is included and supports up to 32 interrupts.

The system tick timer is included.

Debug options: Serial Wire Debug is included with two watchpoints and four breakpoints.

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User manual

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Rev. 12.4 — 22 December 2016

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UM10398

Chapter 2: LPC111x/LPC11Cxx Memory mapping

Rev. 12.4 — 22 December 2016 User manual

2.1 How to read this chapter

Table 4 and Table 5 show the memory configurations for different LPC111x/LPC11Cxx

parts.

Table 4.

Part

Suffix

LPC111x memory configuration

Flash SRAM

/101; /102; /103 /201; /202; /203 /301; /302;

/303; /323; /333

LPC1111

LPC1112

LPC1113

LPC1114/LPC11D14

8 kB

16 kB

24 kB

32 kB

-

-

2 kB

2 kB

4 KB

4 KB

4 KB

4 KB

-

-

8 kB

8 kB

LPC1114/323

LPC1114/333

LPC1115

48 kB

56 kB

64 kB

-

-

-

-

-

-

8 kB

8 kB

8 kB

Table 5.

LPC11Cxx memory configuration

Part

LPC11C12/301

Flash

16 kB

LPC11C14/301

LPC11C22/301

LPC11C24/301

32 kB

16 kB

32 kB

SRAM

8 kB

8 kB

8 kB

8 kB

2.2 Memory map

Figure 6 and

Figure 7

show the memory and peripheral address space of the

LPC111x/LPC11Cxx.

The AHB peripheral area is 2 MB in size and is divided to allow for up to 128 peripherals.

On the LPC111x/LPC11Cxx, the GPIO ports are the only AHB peripherals. The APB peripheral area is 512 kB in size and is divided to allow for up to 32 peripherals. Each peripheral of either type is allocated 16 kB of space. This allows simplifying the address decoding for each peripheral.

All peripheral register addresses are 32-bit word aligned regardless of their size. An implication of this is that word and half-word registers must be accessed all at once. For example, it is not possible to read or write the upper byte of a word register separately.

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User manual

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NXP Semiconductors

UM10398

Chapter 2: LPC111x/LPC11Cxx Memory mapping

4 GB

LPC1111/12/13/14

LPC11Cxx

LPC11D14

reserved

0xFFFF FFFF

AHB peripherals

0x5020 0000

1 GB

0.5 GB private peripheral bus reserved

AHB peripherals reserved

APB peripherals reserved

0xE010 0000

0xE000 0000

0x5020 0000

0x5000 0000

0x4008 0000

0x4000 0000

0x2000 0000 reserved

16 kB boot ROM

0x1FFF 4000

0x1FFF 0000 reserved

0x1000 2000

8 kB SRAM (LPC1113/14/301/302; LPC11D14;

LPC11Cxx)

4 kB SRAM (LPC1111/12/13/14/201/202)

2 kB SRAM (LPC1111/12/101/102)

0x1000 1000

0x1000 0800

0x1000 0000 reserved

0x0000 8000

32 kB on-chip flash (LPC1114; LPC11D14;

LPC11Cx4)

24 kB on-chip flash (LPC1113)

16 kB on-chip flash (LPC1112; LPC11Cx2)

8 kB on-chip flash (LPC1111)

0x0000 6000

0x0000 4000

0x0000 2000

0x0000 0000

16 - 127 reserved

18

17

16

15

14

12-15

8-11

4-7

0-3

GPIO PIO3

GPIO PIO2

GPIO PIO1

GPIO PIO0

APB peripherals

22

20

23 - 31 reserved

SPI1

(1) reserved

C_CAN

(2)

reserved system control

IOCONFIG

SPI0 flash controller

PMU

10 - 13 reserved reserved reserved

ADC

32-bit counter/timer 1

32-bit counter/timer 0

16-bit counter/timer 1

16-bit counter/timer 0

UART

WDT

I

2

C-bus

0x5004 0000

0x5003 0000

0x5002 0000

0x5001 0000

0x5000 0000

0x4008 0000

0x4005 C000

0x4005 8000

0x4005 4000

0x4005 0000

0x4004 C000

0x4004 8000

0x4004 4000

0x4004 0000

0x4003 C000

0x4003 8000

0x4002 8000

0x4002 4000

0x4002 0000

0x4001 C000

0x4001 8000

0x4001 4000

0x4001 0000

0x4000 C000

0x4000 8000

0x4000 4000

0x4000 0000 active interrupt vectors

0x0000 00C0

0x0000 0000

0 GB

(1) LQFP100/LQFP48 packages only.

(2) LPC11Cxxonly.

Fig 6.

LPC111x/LPC11Cxx memory map (LPC1100 and LPC1100L series)

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Chapter 2: LPC111x/LPC11Cxx Memory mapping

4 GB

LPC1111/12/13/14/15XL

reserved private peripheral bus reserved

AHB peripherals

0xFFFF FFFF

0xE010 0000

0xE000 0000

0x5020 0000

0x5000 0000 reserved

1 GB

APB peripherals

0x4008 0000

0x4000 0000 reserved

0.5 GB

0x2000 0000 reserved

16 kB boot ROM reserved

8 kB SRAM (LPC1113/14/15/303/323/333)

4 kB SRAM (LPC1111/12/13/14/203)

2 kB SRAM (LPC1111/12/103) reserved

0x1FFF 4000

0x1FFF 0000

0x1000 2000

0x1000 1000

0x1000 0800

0x1000 0000

64 kB on-chip flash (LPC1115)

56 kB on-chip flash (LPC1114/333)

48 kB on-chip flash (LPC1114/323)

32 kB on-chip flash (LPC1114)

24 kB on-chip flash (LPC1113)

16 kB on-chip flash (LPC1112)

8 kB on-chip flash (LPC1111)

0x0001 0000

0x0000 E000

0x0000 C000

0x0000 8000

0x0000 6000

0x0000 4000

0x0000 2000

0x0000 0000

0 GB

Fig 7.

LPC111x memory map (LPC1100XL series)

AHB peripherals

0x5020 0000

127-16 reserved

18

17

16

15

14

6

5

4

3

2

1

0

9

8

7

12-15

8-11

4-7

0-3

22

GPIO PIO3

GPIO PIO2

GPIO PIO1

GPIO PIO0

0x5004 0000

0x5003 0000

0x5002 0000

0x5001 0000

0x5000 0000

APB peripherals

31-23 reserved

SPI1

21-19 reserved system control

IOCONFIG

SPI0 flash controller

PMU

0x4008 0000

0x4005 C000

0x4005 8000

0x4004 C000

0x4004 8000

0x4004 4000

0x4004 0000

0x4003 C000

0x4003 8000

13-10 reserved reserved reserved

ADC

32-bit counter/timer 1

32-bit counter/timer 0

16-bit counter/timer 1

16-bit counter/timer 0

UART

WWDT

I

2

C-bus

0x4002 8000

0x4002 4000

0x4002 0000

0x4001 C000

0x4001 8000

0x4001 4000

0x4001 0000

0x4000 C000

0x4000 8000

0x4000 4000

0x4000 0000 active interrupt vectors

0x0000 00C0

0x0000 0000

002aag788

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UM10398

Chapter 3: LPC111x/LPC11Cxx System configuration

(SYSCON)

Rev. 12.4 — 22 December 2016 User manual

3.1 How to read this chapter

The following functions of the system configuration block depend on the specific part number:

DEVICE_ID register

The DEVICE_ID register is valid 0x4004 83F4 for parts of the LPC1100, LPC1100C, and

LPC1100L series only.

The device ID cannot be read through the SYSCON block for the LPC1100XL series. Use the ISP part ID command (

Table 400

) to obtain the device ID for the LPC1100XL parts.

C_CAN controller

The C_CAN clock control bit 17 in the SYSAHBCLKCTRL register ( Table 21 ) and the

C_CAN reset control bit 3 in the PRESETCTRL register ( Table 9

) are only functional for parts LPC11Cxx/101/201/301.

Entering Deep power-down mode

Status of the IRC before entering Deep power-down mode (see

Section 3.9.4.2

):

IRC must be enabled for parts LPC111x/101/201/301 and parts

LPC11Cxx/101/201/301.

IRC status has no effect for parts in the LPC1100L and LPC1100XL series.

Enabling sequence for UART clock

Requirements for enabling the UART peripheral clock:

The UART pins must be configured in the IOCON block before the UART clock can be enabled in the in the SYSAHBCLKCTRL register (

Table 21

) for parts LPC111x/101/201/301.

The sequence of configuring the UART pins and the UART clock has no effect for parts in the LPC1100L and LPC1100XL series and parts LPC1100C series.

NMI source selection register

The NMI source selection register is only available on parts in the LPC1100XL series.

3.2 General description

The system configuration block controls oscillators, start logic, and clock generation of the

LPC111x/LPC11Cxx. Also included in this block is a register for remapping flash, SRAM, and ROM memory areas.

3.3 Pin description

Table 6

shows pins that are associated with system control block functions.

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Chapter 3: LPC111x/LPC11Cxx System configuration (SYSCON)

Table 6.

Pin name

CLKOUT

Pin summary

PIO0_0 to PIO0_11

PIO1_0 I

I

Pin direction

O

Pin description

Clockout pin

Start logic wake-up pins port 0

Start logic wake-up pin port 1

3.4 Clock generation

See

Figure 8 for an overview of the LPC111x/LPC11Cxx Clock Generation Unit (CGU).

The LPC111x/LPC11Cxx include three independent oscillators. These are the system oscillator, the Internal RC oscillator (IRC), and the watchdog oscillator. Each oscillator can be used for more than one purpose as required in a particular application.

Following reset, the LPC111x/LPC11Cxx will operate from the Internal RC oscillator until switched by software. This allows systems to operate without any external crystal and the bootloader code to operate at a known frequency.

The SYSAHBCLKCTRL register gates the system clock to the various peripherals and memories. UART, the WDT, and SPI0/1 have individual clock dividers to derive peripheral clocks from the main clock.

The main clock and the clock outputs from the IRC, the system oscillator, and the watchdog oscillator can be observed directly on the CLKOUT pin.

For details on power control see Section 3.9

.

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Chapter 3: LPC111x/LPC11Cxx System configuration (SYSCON)

ARM

CORTEX-M0

SYSTEM CLOCK

DIVIDER system clock

SYSAHBCLKDIV

18

SYSAHBCLKCTRL[1:18]

AHB clocks

1 to 18

(memories and peripherals)

IRC oscillator watchdog oscillator main clock

SPI0 PERIPHERAL

CLOCK DIVIDER

UART PERIPHERAL

CLOCK DIVIDER

SPI1 PERIPHERAL

CLOCK DIVIDER

SPI0_PCLK

UART_PCLK

SPI1_PCLK

MAINCLKSEL

(main clock select)

IRC oscillator system oscillator

SYSPLLCLKSEL

(system PLL clock select) sys_pllclkout sys_pllclkin

SYSTEM PLL

IRC oscillator

WDT CLOCK

DIVIDER watchdog oscillator

WDTUEN

(WDT clock update enable)

IRC oscillator system oscillator watchdog oscillator

CLKOUT PIN CLOCK

DIVIDER

CLKOUTUEN

(CLKOUT update enable)

WDCLK

CLKOUT pin

Fig 8.

LPC111x/LPC11Cxx CGU block diagram

3.5 Register description

All registers, regardless of size, are on word address boundaries. Details of the registers appear in the description of each function.

Table 7.

Name

See

Section 3.12

for the flash access timing register, which can be re-configured as part

the system setup. This register is not part of the system configuration block.

Register overview: system control block (base address 0x4004 8000)

Access Address offset Description Reference

SYSMEMREMAP

PRESETCTRL

SYSPLLCTRL

-

SYSPLLSTAT

-

R

R/W

R/W

R/W

0x000

0x004

0x008

0x00C

0x010 - 0x01C

System memory remap

Peripheral reset control

System PLL control

System PLL status

Reserved

Reset value

0x002

0x000

0x000

-

0x000

Table 8

Table 9

Table 10

Table 11

-

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Chapter 3: LPC111x/LPC11Cxx System configuration (SYSCON)

Table 7.

Name

Register overview: system control block (base address 0x4004 8000)

…continued

Access Address offset Description Reset value

SYSOSCCTRL

WDTOSCCTRL

-

IRCCTRL

-

0x000

0x000

0x080

-

SYSRSTSTAT

SYSPLLCLKSEL

SYSPLLCLKUEN

-

MAINCLKSEL

MAINCLKUEN

SYSAHBCLKDIV

-

0x000

0x000

0x000

-

0x000

0x000

0x001

-

SYSAHBCLKCTRL

-

SSP0CLKDIV

UARTCLKDIV

SSP1CLKDIV

-

WDTCLKSEL

WDTCLKUEN

WDTCLKDIV

-

CLKOUTCLKSEL

CLKOUTUEN

CLKOUTCLKDIV

-

PIOPORCAP0

-

-

-

PIOPORCAP1

BODCTRL

SYSTCKCAL

IRQLATENCY

NMISRC

STARTAPRP0

STARTERP0

-

-

R

R

R/W

R/W

R/W

R/W

R/W

R/W

0x104

0x108 - 0x14C

0x150

0x154

0x158 - 0x16C

0x170

0x174

0x178 - 0x1FC

0x200

0x204

POR captured PIO status 1

Reserved

BOD control

System tick counter calibration

Reserved

IQR delay. Allows trade-off between interrupt latency and determinism.

NMI source selection

Reserved

Start logic edge control register 0

Start logic signal enable register 0

-

-

0x85F

-

0x000

0x000

0x000

-

0x000

0x000

0x000

-

0x000

0x000

0x000

user dependent

user dependent

0x000

0x004

-

0x10

0x000

Reference

Table 32

-

Table 33

Table 34

-

Table 35

Table 36

-

Table 37

Table 38

Table 19

Table 20

-

Table 21

-

Table 22

Table 23

Table 24

-

Table 25

Table 26

Table 27

-

Table 28

Table 29

Table 30

-

Table 31

Table 12

Table 13

Table 14

-

Table 15

-

Table 16

Table 17

-

Table 18

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Chapter 3: LPC111x/LPC11Cxx System configuration (SYSCON)

Table 7.

Name

Register overview: system control block (base address 0x4004 8000)

…continued

Access Address offset Description Reset value

STARTRSRP0CLR

STARTSRP0

-

PDSLEEPCFG

-

W

R

R/W

0x208

0x20C

0x210 - 0x22C

0x230

Start logic reset register 0

Start logic status register 0

Reserved

Power-down states in Deep-sleep mode

-

PDAWAKECFG

PDRUNCFG

DEVICE_ID

-

R/W

R/W

R

0x234

0x238

0x23C - 0x3F0

0x3F4

Power-down states after wake-up from

Deep-sleep mode

Power-down configuration register

Reserved

Device ID register 0 for parts LPC1100,

LPC1100C, LPC1100L.

n/a n/a

-

0x0000

0000

-

0x0000

EDF0

0x0000

EDF0 part dependent

Reference

Table 39

Table 40

-

Table 42

Table 43

Table 44

-

Table 45

3.5.1 System memory remap register

The system memory remap register selects whether the ARM interrupt vectors are read from the boot ROM, the flash, or the SRAM. By default, the flash memory is mapped to address 0x0000 0000. When the MAP bits in the SYSMEMREMAP register are set to 0x0 or 0x1, the boot ROM or RAM respectively are mapped to the bottom 512 bytes of the memory map (addresses 0x0000 0000 to 0x0000 0200).

Table 8.

Bit

System memory remap register (SYSMEMREMAP, address 0x4004 8000) bit description

Symbol Value Description Reset value

1:0

31:2 -

MAP

-

0x0

0x1

0x2

System memory remap

Boot Loader Mode. Interrupt vectors are re-mapped to Boot

ROM.

User RAM Mode. Interrupt vectors are re-mapped to Static

RAM.

User Flash Mode. Interrupt vectors are not re-mapped and reside in Flash.

Reserved

10

0x00

3.5.2 Peripheral reset control register

This register allows software to reset the SPI and I2C peripherals. Writing a zero to the

SSP0/1_RST_N or I2C_RST_N bits resets the SPI0/1 or I2C peripheral. Writing a one de-asserts the reset.

Remark:

Before accessing the SPI and I2C peripherals, write a one to this register to ensure that the reset signals to the SPI and I2C are de-asserted.

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Chapter 3: LPC111x/LPC11Cxx System configuration (SYSCON)

Table 9.

Bit

0

Peripheral reset control register (PRESETCTRL, address 0x4004 8004) bit description

Symbol Value Description

SSP0_RST_N SPI0 reset control

Reset value

0

1 I2C_RST_N

0

1

0

1

Resets the SPI0 peripheral.

SPI0 reset de-asserted.

I2C reset control

Resets the I2C peripheral.

0

2

3

SSP1_RST_N

CAN_RST_N

0

1

I2C reset de-asserted.

SPI1 reset control

Resets the SPI1 peripheral.

SPI1 reset de-asserted.

C_CAN reset control. See

Section 3.1

for part specific details.

0

0

31:4 -

0

1

Resets the C_CAN peripheral.

C_CAN reset de-asserted.

Reserved 0x00

3.5.3 System PLL control register

This register connects and enables the system PLL and configures the PLL multiplier and divider values. The PLL accepts an input frequency from 10 MHz to 25 MHz from various clock sources. The input frequency is multiplied up to a high frequency, then divided down to provide the actual clock used by the CPU, peripherals, and memories. The PLL can produce a clock up to the maximum allowed for the CPU.

Table 10.

Bit

System PLL control register (SYSPLLCTRL, address 0x4004 8008) bit description

Symbol Value Description Reset value

4:0

6:5

31:7

MSEL

-

PSEL

-

0x0

0x1

0x2

0x3

Feedback divider value. The division value M is the programmed MSEL value + 1.

00000: Division ratio M = 1 to

11111: Division ratio M = 32.

Post divider ratio P. The division ratio is 2

P.

P = 1

P = 2

P = 4

P = 8

Reserved. Do not write ones to reserved bits.

0x000

0x00

0x0

3.5.4 System PLL status register

This register is a Read-only register and supplies the PLL lock status (see Section 3.11.1

).

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Chapter 3: LPC111x/LPC11Cxx System configuration (SYSCON)

Table 11.

Bit

System PLL status register (SYSPLLSTAT, address 0x4004 800C) bit description

Symbol Value Description Reset value

0 LOCK 0x0

31:1 -

0

1

PLL lock status

PLL not locked

PLL locked

Reserved 0x00

3.5.5 System oscillator control register

This register configures the frequency range for the system oscillator.

Table 12.

Bit

System oscillator control register (SYSOSCCTRL, address 0x4004 8020) bit description

Symbol Value Description Reset value

0 BYPASS

0

1

Bypass system oscillator

Oscillator is not bypassed.

0x0

1 FREQRANGE

Bypass enabled. PLL input (sys_osc_clk) is fed directly from the XTALIN pin bypassing the oscillator. Use this mode when using an external clock source instead of the crystal oscillator.

Determines frequency range for Low-power oscillator.

0x0

31:2 -

0

1

1 - 20 MHz frequency range.

15 - 25 MHz frequency range

Reserved 0x00

3.5.6 Watchdog oscillator control register

This register configures the watchdog oscillator. The oscillator consists of an analog and a digital part. The analog part contains the oscillator function and generates an analog clock

(Fclkana). With the digital part, the analog output clock (Fclkana) can be divided to the required output clock frequency wdt_osc_clk. The analog output frequency (Fclkana) can be adjusted with the FREQSEL bits between 600 kHz and 4.6 MHz. With the digital part

Fclkana will be divided (divider ratios = 2, 4,...,64) to wdt_osc_clk using the DIVSEL bits.

The output clock frequency of the watchdog oscillator can be calculated as wdt_osc_clk = Fclkana/(2

(1 + DIVSEL)) = 9.4 kHz to 2.3 MHz (nominal values).

Remark:

Any setting of the FREQSEL bits will yield a Fclkana value within

40% of the listed frequency value. The watchdog oscillator is the clock source with the lowest power consumption. If accurate timing is required, use the IRC or system oscillator.

Remark:

The frequency of the watchdog oscillator is undefined after reset. The watchdog oscillator frequency must be programmed by writing to the WDTOSCCTRL register before using the watchdog oscillator.

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Chapter 3: LPC111x/LPC11Cxx System configuration (SYSCON)

Table 13.

Bit

Watchdog oscillator control register (WDTOSCCTRL, address 0x4004 8024) bit description

Symbol Value Description

4:0 DIVSEL

Reset value

0

8:5 FREQSEL

0x1

Select divider for Fclkana. wdt_osc_clk = Fclkana/ (2

(1 + DIVSEL))

00000: 2

(1 + DIVSEL) = 2

00001: 2

(1 + DIVSEL) = 4 to

11111: 2

(1 + DIVSEL) = 64

Select watchdog oscillator analog output frequency

(Fclkana).

0.6 MHz

0x00

0x2

0x3

0x4

0x5

1.05 MHz

1.4 MHz

1.75 MHz

2.1 MHz

31:9 -

0x6

0x7

0x8

0x9

0xA

0xB

0xC

0xD

-

0xE

0xF

2.4 MHz

2.7 MHz

3.0 MHz

3.25 MHz

3.5 MHz

3.75 MHz

4.0 MHz

4.2 MHz

4.4 MHz

4.6 MHz

Reserved 0x00

3.5.7 Internal resonant crystal control register

This register is used to trim the on-chip 12 MHz oscillator. The trim value is factory-preset and written by the boot code on start-up.

Table 14.

Bit

Internal resonant crystal control register (IRCCTRL, address 0x4004 8028) bit description

Symbol Description Reset value

7:0 TRIM Trim value

31:8 Reserved

0x1000 0000, then flash will reprogram

0x00

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3.5.8 System reset status register

The SYSRSTSTAT register shows the source of the latest reset event. Write a one to clear the reset.

The POR event clears all other bits in this register. If any reset signal - for example

EXTRST - remains asserted after the POR signal is negated, then its bit is set to detected in this register.

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Chapter 3: LPC111x/LPC11Cxx System configuration (SYSCON)

The reset value given in Table 15 applies to the POR reset.

Table 15.

Bit

System reset status register (SYSRSTSTAT, address 0x4004 8030) bit description

Symbol Value Description Reset value

0 POR 0x0

1 EXTRST

0

1

POR reset status

No POR detected.

POR detected. Writing a one clears this reset.

Status of the external RESET pin.

0x0

0

1

2

3

WDT

BOD

0

1

0

1

No RESET event detected.

RESET detected. Writing a one clears this reset.

Status of the Watchdog reset

No WDT reset detected.

WDT reset detected. Writing a one clears this reset.

Status of the Brown-out detect reset

No BOD reset detected.

BOD reset detected. Writing a one clears this reset.

0x0

0x0

4

31:5 -

SYSRST

-

0

1

Status of the software system reset

No System reset detected.

System reset detected. Writing a one clears this reset.

Reserved

0x0

0x0

3.5.9 System PLL clock source select register

This register selects the clock source for the system PLL. The SYSPLLCLKUEN register

(see Section 3.5.10

) must be toggled from LOW to HIGH for the update to take effect.

Remark:

When switching clock sources, both clocks must be running before the clock source is updated.

Remark:

When using the C_CAN controller with baudrates above 100 kbit/s, the system oscillator must be selected.

Table 16.

Bit

System PLL clock source select register (SYSPLLCLKSEL, address 0x4004 8040) bit description

Symbol Value Description Reset value

1:0 SEL 0x00

0x0

0x1

0x2

System PLL clock source

IRC oscillator

System oscillator

Reserved

31:2 -

0x3 Reserved

Reserved 0x00

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Chapter 3: LPC111x/LPC11Cxx System configuration (SYSCON)

3.5.10 System PLL clock source update enable register

This register updates the clock source of the system PLL with the new input clock after the

SYSPLLCLKSEL register has been written to. In order for the update to take effect, first write a zero to the SYSPLLUEN register and then write a one to SYSPLLUEN.

Remark:

When switching clock sources, both clocks must be running before the clock source is updated.

Table 17.

Bit

System PLL clock source update enable register (SYSPLLCLKUEN, address

0x4004 8044) bit description

Symbol Value Description Reset value

0 ENA 0x0

31:1 -

0

1

Enable system PLL clock source update

No change

Update clock source

Reserved 0x00

3.5.11 Main clock source select register

This register selects the main system clock which can be either any input to the system

PLL, the output from the system PLL (sys_pllclkout), or the watchdog or IRC oscillators directly. The main system clock clocks the core, the peripherals, and the memories.

The MAINCLKUEN register (see

Section 3.5.12

) must be toggled from LOW to HIGH for

the update to take effect.

Remark:

When switching clock sources, both clocks must be running before the clock source is updated.

Remark:

When using the C_CAN controller with baudrates above 100 kbit/s, the system oscillator must be selected.

Table 18.

Bit

1:0

Main clock source select register (MAINCLKSEL, address 0x4004 8070) bit description

Symbol

SEL

Value Description

Clock source for main clock

Reset value

0x00

31:2 -

0x0

0x1

0x2

0x3

IRC oscillator

Input clock to system PLL

WDT oscillator

System PLL clock out

Reserved 0x00

3.5.12 Main clock source update enable register

This register updates the clock source of the main clock with the new input clock after the

MAINCLKSEL register has been written to. In order for the update to take effect, first write a zero to the MAINCLKUEN register and then write a one to MAINCLKUEN.

Remark:

When switching clock sources, both clocks must be running before the clock source is updated.

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Chapter 3: LPC111x/LPC11Cxx System configuration (SYSCON)

Table 19.

Bit

0

Main clock source update enable register (MAINCLKUEN, address 0x4004 8074) bit description

Symbol

ENA

Value

0

Description

Enable main clock source update

No change

Reset value

0x0

31:1 -

1 Update clock source

Reserved 0x00

3.5.13 System AHB clock divider register

This register divides the main clock to provide the system clock to the core, memories, and the peripherals. The system clock can be shut down completely by setting the DIV bits to 0x0.

Table 20.

Bit

System AHB clock divider register (SYSAHBCLKDIV, address 0x4004 8078) bit description

Symbol Description Reset value

7:0 DIV 0x01

31:8 -

System AHB clock divider values

0: System clock disabled.

1: Divide by 1.

to

255: Divide by 255.

Reserved 0x00

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3.5.14 System AHB clock control register

The AHBCLKCTRL register enables the clocks to individual system and peripheral blocks.

The system clock (sys_ahb_clk[0], bit 0 in the AHBCLKCTRL register) provides the clock for the AHB to APB bridge, the AHB matrix, the ARM Cortex-M0, the Syscon block, and the PMU. This clock cannot be disabled.

Table 21.

Bit

System AHB clock control register (SYSAHBCLKCTRL, address 0x4004 8080) bit description

Symbol Value Description Reset value

0 SYS Enables clock for AHB to APB bridge, to the AHB matrix, to the Cortex-M0 FCLK and HCLK, to the

SysCon, and to the PMU. This bit is read only.

1

1 ROM

0

1

0

1

Reserved

Enable

Enables clock for ROM.

Disable

1

2 RAM

0

1

Enable

Enables clock for RAM.

Disable

Enable

1

3 FLASHREG

0

1

Enables clock for flash register interface.

Disabled

Enabled

1

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Chapter 3: LPC111x/LPC11Cxx System configuration (SYSCON)

Table 21.

Bit

System AHB clock control register (SYSAHBCLKCTRL, address 0x4004 8080) bit description

…continued

Symbol Value Description Reset value

4 FLASHARRAY 1

0

1

Enables clock for flash array access.

Disabled

Enabled

5 I2C 0

6

7

GPIO

CT16B0

0

1

0

1

0

1

Enables clock for I2C.

Disable

Enable

Enables clock for GPIO.

Disable

Enable

Enables clock for 16-bit counter/timer 0.

Disable

1

0

8

9

10

CT16B1

CT32B0

CT32B1

0

1

0

1

Enable

Enables clock for 16-bit counter/timer 1.

Disable

Enable

Enables clock for 32-bit counter/timer 0.

Disable

Enable

Enables clock for 32-bit counter/timer 1.

0

0

0

0

1

11

12

13

14

15

16

-

SSP0

UART

ADC

WDT

IOCON

0

1

0

1

0

1

0

1

0

1

Disable

Enable

Enables clock for SPI0.

Disable

Enable

Enables clock for UART. See

Section 3.1

for part specific details.

Disable

Enable

Enables clock for ADC.

Disable

Enable

Reserved

Enables clock for WDT.

Disable

Enable

Enables clock for I/O configuration block.

Disable

Enable

1

0

0

0

0

0

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Chapter 3: LPC111x/LPC11Cxx System configuration (SYSCON)

Table 21.

Bit

System AHB clock control register (SYSAHBCLKCTRL, address 0x4004 8080) bit description

…continued

Symbol Value Description Reset value

17 CAN

0

1

Enables clock for C_CAN. See Section 3.1

for part

specific details.

Disable

0

18

31:19 -

SSP1

-

0

1

Enable

Enables clock for SPI1.

Disable

Enable

Reserved

0

0x00

3.5.15 SPI0 clock divider register

This register configures the SPI0 peripheral clock SPI0_PCLK. The SPI0_PCLK can be shut down by setting the DIV bits to 0x0.

Table 22.

Bit

7:0

SPI0 clock divider register (SSP0CLKDIV, address 0x4004 8094) bit description

Symbol

DIV

Description

SPI0_PCLK clock divider values

0: Disable SPI0_PCLK.

1: Divide by 1.

to

255: Divide by 255.

Reset value

0x00

31:8 Reserved 0x00

3.5.16 UART clock divider register

This register configures the UART peripheral clock UART_PCLK. The UART_PCLK can be shut down by setting the DIV bits to 0x0.

Remark:

Note that for some parts the UART pins must be configured in the IOCON block before the UART clock can be enabled.

See

Section 3.1

for part specific details.

Table 23.

Bit

7:0

UART clock divider register (UARTCLKDIV, address 0x4004 8098) bit description

Symbol

DIV

Description

UART_PCLK clock divider values

0: Disable UART_PCLK.

1: Divide by 1.

to

255: Divide by 255.

Reset value

0x00

31:8 Reserved 0x00

3.5.17 SPI1 clock divider register

This register configures the SPI1 peripheral clock SPI1_PCLK. The SPI1_PCLK can be shut down by setting the DIV bits to 0x0.

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Table 24.

Bit

SPI1 clock divider register (SSP1CLKDIV, address 0x4004 809C) bit description

Symbol Description Reset value

7:0

31:8

DIV

-

SPI1_PCLK clock divider values

0: Disable SPI1_PCLK.

1: Divide by 1.

to

255: Divide by 255.

Reserved

0x00

0x00

3.5.18 WDT clock source select register

This register selects the clock source for the watchdog timer. The WDTCLKUEN register

(see Section 3.5.19

) must be toggled from LOW to HIGH for the update to take effect.

Remark:

When switching clock sources, both clocks must be running before the clock source is updated.

Table 25.

Bit

WDT clock source select register (WDTCLKSEL, address 0x4004 80D0) bit description

Symbol Value Description Reset value

1:0 SEL 0x00

0x0

0x1

0x2

WDT clock source

IRC oscillator

Main clock

Watchdog oscillator

31:2 -

0x3 Reserved

Reserved 0x00

3.5.19 WDT clock source update enable register

This register updates the clock source of the watchdog timer with the new input clock after the WDTCLKSEL register has been written to. In order for the update to take effect at the input of the watchdog timer, first write a zero to the WDTCLKUEN register and then write a one to WDTCLKUEN.

Remark:

When switching clock sources, both clocks must be running before the clock source is updated.

Table 26.

Bit

WDT clock source update enable register (WDTCLKUEN, address 0x4004 80D4) bit description

Symbol Value Description Reset value

0 ENA 0x0

31:1 -

0

1

Enable WDT clock source update

No change

Update clock source

Reserved 0x00

3.5.20 WDT clock divider register

This register determines the divider values for the watchdog clock wdt_clk.

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Table 27.

Bit

7:0

WDT clock divider register (WDTCLKDIV, address 0x4004 80D8) bit description

Symbol

DIV

Description

WDT clock divider values

0: Disable WDCLK.

1: Divide by 1.

to

255: Divide by 255.

Reset value

0x00

31:8 Reserved 0x00

3.5.21 CLKOUT clock source select register

This register configures the clkout_clk signal to be output on the CLKOUT pin. All three oscillators and the main clock can be selected for the clkout_clk clock.

The CLKOUTCLKUEN register (see

Section 3.5.22

) must be toggled from LOW to HIGH

for the update to take effect.

Remark:

When switching clock sources, both clocks must be running before the clock source is updated.

Table 28.

Bit

CLKOUT clock source select register (CLKOUTCLKSEL, address 0x4004 80E0) bit description

Symbol Value Description Reset value

1:0 SEL CLKOUT clock source 0x00

31:2 -

0x0

0x1

0x2

0x3

IRC oscillator

System oscillator

Watchdog oscillator

Main clock

Reserved 0x00

3.5.22 CLKOUT clock source update enable register

This register updates the clock source of the CLKOUT pin with the new clock after the

CLKOUTCLKSEL register has been written to. In order for the update to take effect at the input of the CLKOUT pin, first write a zero to the CLKCLKUEN register and then write a one to CLKCLKUEN.

Remark:

When switching clock sources, both clocks must be running before the clock source is updated.

Table 29.

Bit

0

CLKOUT clock source update enable register (CLKOUTUEN, address 0x4004

80E4) bit description

Symbol

ENA

Value Description

Enable CLKOUT clock source update

Reset value

0x0

31:1 -

0

1

No change

Update clock source

Reserved 0x00

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3.5.23 CLKOUT clock divider register

This register determines the divider value for the clock output signal on the CLKOUT pin.

Table 30.

Bit

7:0

CLKOUT clock divider registers (CLKOUTCLKDIV, address 0x4004 80E8) bit description

Symbol

DIV

Description

Clock output divider values

0: Disable CLKOUT.

1: Divide by 1.

to

255: Divide by 255.

Reset value

0x00

31:8 Reserved 0x00

3.5.24 POR captured PIO status register 0

The PIOPORCAP0 register captures the state (HIGH or LOW) of the PIO pins of ports 0,1, and 2 (pins PIO2_0 to PIO2_7) at power-on-reset. Each bit represents the reset state of one GPIO pin. This register is a read-only status register.

Table 31.

Bit

POR captured PIO status registers 0 (PIOPORCAP0, address 0x4004 8100) bit description

Symbol Description Reset value

11:0 CAPPIO0_n User implementation dependent

23:12 CAPPIO1_n

Raw reset status input PIO0_n:

PIO0_11 to PIO0_0

Raw reset status input PIO1_n:

PIO1_11 to PIO1_0

User implementation dependent

31:24 CAPPIO2_n Raw reset status input PIO2_n:

PIO2_7 to PIO2_0

User implementation dependent

3.5.25 POR captured PIO status register 1

The PIOPORCAP1 register captures the state (HIGH or LOW) of the PIO pins of port 2

(PIO2_8 to PIO2_11) and port 3 at power-on-reset. Each bit represents the reset state of one PIO pin. This register is a read-only status register.

6

7

4

5

8

9

31:10

2

3

0

1

Table 32.

Bit

POR captured PIO status registers 1 (PIOPORCAP1, address 0x4004 8104) bit description

Symbol Description Reset value

CAPPIO2_8

CAPPIO2_9

CAPPIO2_10

CAPPIO2_11

Raw reset status input PIO2_8

Raw reset status input PIO2_9

Raw reset status input PIO2_10

Raw reset status input PIO2_11

User implementation dependent

User implementation dependent

User implementation dependent

User implementation dependent

-

CAPPIO3_0

CAPPIO3_1

CAPPIO3_2

CAPPIO3_3

CAPPIO3_4

CAPPIO3_5

Raw reset status input PIO3_0

Raw reset status input PIO3_1

Raw reset status input PIO3_2

Raw reset status input PIO3_3

Raw reset status input PIO3_4

Raw reset status input PIO3_5

Reserved -

User implementation dependent

User implementation dependent

User implementation dependent

User implementation dependent

User implementation dependent

User implementation dependent

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3.5.26 BOD control register

The BOD control register selects up to four separate threshold values for sending a BOD interrupt to the NVIC and for forced reset. Reset and interrupt threshold values listed are typical values.

Table 33.

Bit

1:0

BOD control register (BODCTRL, address 0x4004 8150) bit description

Symbol

BODRSTLEV

Value Description

0x0

Reset value

BOD reset level

Level 0: The reset assertion threshold voltage is 1.46 V; the reset de-assertion threshold voltage is 1.63 V.

00

0x1

3:2 BODINTVAL

0x2

0x3

0x0

0x1

0x2

Level 1: The reset assertion threshold voltage is 2.06 V; the reset de-assertion threshold voltage is 2.15 V.

Level 2: The reset assertion threshold voltage is 2.35 V; the reset de-assertion threshold voltage is 2.43 V.

Level 3: The reset assertion threshold voltage is 2.63 V; the reset de-assertion threshold voltage is 2.71 V.

BOD interrupt level

Level 0: Reserved.

00

Level 1:The interrupt assertion threshold voltage is 2.22 V; the interrupt de-assertion threshold voltage is 2.35 V.

Level 2: The interrupt assertion threshold voltage is 2.52 V; the interrupt de-assertion threshold voltage is 2.66 V.

4

31:5 -

BODRSTENA

-

0x3

0

1

Level 3: The interrupt assertion threshold voltage is 2.80 V; the interrupt de-assertion threshold voltage is 2.90 V.

BOD reset enable

Disable reset function.

0

Enable reset function.

Reserved 0x00

3.5.27 System tick counter calibration register

This register determines the value of the SYST_CALIB register (see

Table 361 ).

Table 34.

Bit

System tick timer calibration register (SYSTCKCAL, address 0x4004 8154) bit description

Symbol Description Reset value

25:0 CAL System tick timer calibration value 0x04

31:26 Reserved 0x00

3.5.28 IRQ latency register

The IRQLATENCY register is an eight-bit register which specifies the minimum number of cycles (0-255) permitted for the system to respond to an interrupt request. The intent of this register is to allow the user to select a trade-off between interrupt response time and determinism.

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Setting this parameter to a very low value (e.g. zero) will guarantee the best possible interrupt performance but will also introduce a significant degree of uncertainty and jitter.

Requiring the system to always take a larger number of cycles (whether it needs it or not) will reduce the amount of uncertainty but may not necessarily eliminate it.

Theoretically, the ARM Cortex-M0 core should always be able to service an interrupt request within 15 cycles. System factors external to the cpu, however, bus latencies, peripheral response times, etc. can increase the time required to complete a previous instruction before an interrupt can be serviced. Therefore, accurately specifying a minimum number of cycles that will ensure determinism will depend on the application.

The default setting for this register is 0x010.

Table 35.

Bit

IRQ latency register (IRQLATENCY, address 0x4004 8170) bit description

Symbol Description Reset value

7:0

31:8 -

LATENCY 8-bit latency value

Reserved -

0x010

3.5.29 NMI source selection register

The NMI source selection register selects a peripheral interrupts as source for the NMI interrupt of the ARM Cortex-M0 core. For a list of all peripheral interrupts and their IRQ numbers see

Table 55

. For a description of the NMI functionality, see Section 28.4.3.2

.

Remark:

See

Section 3.1

for LPC111x parts using this register.

Table 36.

Bit

NMI source selection register (NMISRC, address 0x4004 8174) bit description

Symbol Description Reset value

4:0 IRQNO The IRQ number of the interrupt that acts as the Non-Maskable Interrupt

(NMI) if bit 31 in this register is 1. See Table 55

for the list of interrupt sources and their IRQ numbers.

0

30:5

31

-

NMIEN

Reserved

Write a 1 to this bit to enable the Non-Maskable Interrupt (NMI) source selected by bits 4:0.

-

0

Note:

If the NMISRC register is used to select an interrupt as the source of Non-Maskable interrupts, and the selected interrupt is enabled, one interrupt request can result in both a

Non-Maskable and a normal interrupt. Avoid this situation by disabling the normal interrupt in the NVIC, as described in

Section 28.6.2

.

3.5.30 Start logic edge control register 0

The STARTAPRP0 register controls the start logic inputs of ports 0 (PIO0_0 to PIO0_11) and 1 (PIO1_0). This register selects a falling or rising edge on the corresponding PIO input to produce a falling or rising clock edge, respectively, for the start logic (see

Section 3.10.2

).

Every bit in the STARTAPRP0 register controls one port input and is connected to one wake-up interrupt in the NVIC. Bit 0 in the STARTAPRP0 register corresponds to interrupt

0, bit 1 to interrupt 1, etc. (see

Table 55 ), up to a total of 13 interrupts.

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Remark:

Each interrupt connected to a start logic input must be enabled in the NVIC if the corresponding PIO pin is used to wake up the chip from Deep-sleep mode.

Table 37.

Bit

Start logic edge control register 0 (STARTAPRP0, address 0x4004 8200) bit description

Symbol Description Reset value

11:0 APRPIO0_n Edge select for start logic input PIO0_n: PIO0_11 to PIO0_0

0 = Falling edge

1 = Rising edge

0x0

12

31:13 -

APRPIO1_0 Edge select for start logic input PIO1_0

0 = Falling edge

1 = Rising edge

Reserved. Do not write a 1 to reserved bits in this register.

0x0

0x0

3.5.31 Start logic signal enable register 0

This STARTERP0 register enables or disables the start signal bits in the start logic. The bit

assignment is identical to Table 37

.

Table 38.

Bit

Start logic signal enable register 0 (STARTERP0, address 0x4004 8204) bit description

Symbol Description Reset value

11:0 ERPIO0_n 0x0

12 ERPIO1_0

31:13 -

Enable start signal for start logic input PIO0_n: PIO0_11 to

PIO0_0

0 = Disabled

1 = Enabled

Enable start signal for start logic input PIO1_0

0 = Disabled

1 = Enabled

Reserved. Do not write a 1 to reserved bits in this register.

0x0

0x0

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3.5.32 Start logic reset register 0

Writing a one to a bit in the STARTRSRP0CLR register resets the start logic state. The bit

assignment is identical to Table 37 . The start-up logic uses the input signals to generate a

clock edge for registering a start signal. This clock edge (falling or rising) sets the interrupt for waking up from Deep-sleep mode. Therefore, the start-up logic states must be cleared before being used.

Table 39.

Bit

Start logic reset register 0 (STARTRSRP0CLR, address 0x4004 8208) bit description

Symbol Description Reset value

11:0 RSRPIO0_n n/a

12

31:13 -

RSRPIO1_0

Start signal reset for start logic input PIO0_n:PIO0_11 to

PIO0_0

0 = Do nothing.

1 = Writing 1 resets the start signal.

Start signal reset for start logic input PIO1_0

0 = Do nothing.

1 = Writing 1 resets the start signal.

Reserved. Do not write a 1 to reserved bits in this register.

n/a n/a

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3.5.33 Start logic status register 0

This register reflects the status of the enabled start signal bits. The bit assignment is identical to

Table 37

. Each bit (if enabled) reflects the state of the start logic, i.e. whether or not a wake-up signal has been received for a given pin.

Table 40.

Bit

Start logic status register 0 (STARTSRP0, address 0x4004 820C) bit description

Symbol Description Reset value

11:0 SRPIO0_n n/a

12

31:13 -

SRPIO1_0

Start signal status for start logic input PIO0_n: PIO0_11 to

PIO0_0

0 = No start signal received.

1 = Start signal pending.

Start signal status for start logic input PIO1_0

0 = No start signal received.

1 = Start signal pending.

Reserved n/a n/a

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3.5.34 Deep-sleep mode configuration register

This register controls the behavior of the WatchDog (WD) oscillator and the BOD circuit when the device enters Deep-sleep mode.

This register

must be initialized at least once before entering Deep-sleep mode

with

one of the four values shown in Table 41

:

Table 41.

Allowed values for PDSLEEPCFG register

Configuration

WD oscillator on

BOD on

BOD off

WD oscillator off

PDSLEEPCFG = 0x0000 18B7 PDSLEEPCFG = 0x0000 18F7

PDSLEEPCFG = 0x0000 18BF PDSLEEPCFG = 0x0000 18FF

Remark:

Failure to initialize and program this register correctly may result in undefined

behavior of the microcontroller. The values listed in Table 41

are the only values allowed for PDSLEEPCFG register.

To select the appropriate power configuration for Deep-sleep mode, consider the following:

BOD: Leaving the BOD circuit enabled will protect the part from a low voltage event occurring while the part is in Deep-sleep mode. However, the BOD circuit causes an additional current drain in Deep-sleep mode.

WD oscillator: The watchdog oscillator can be left running in Deep-sleep mode to provide a clock for the watchdog timer or a general purpose timer if they are needed for timing a wake-up event (see

Section 3.10.3

for details). In this case, the watchdog oscillator analog output frequency must be set to its lowest value (bits FREQSEL in

the WDTOSCCTRL = 0001, see Table 13

) and all peripheral clocks other than the

timer clock must be disabled in the SYSAHBCLKCTRL register (see Table 21 ) before

entering Deep-sleep mode.

The watchdog oscillator, if running, contributes an additional current drain in

Deep-sleep mode.

Remark:

Reserved bits in this register must always be written as indicated. This register must be initialized correctly before entering Deep-sleep mode.

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Table 42.

Bit

Deep-sleep configuration register (PDSLEEPCFG, address 0x4004 8230) bit description

Symbol Value Description

2:0

3

NOTUSED

BOD_PD

Reserved.

BOD power-down control in Deep-sleep mode, see

Table 41

.

Always write these bits as 111.

Reset value

0

0

0

1

5:4

6

NOTUSED

WDTOSC_PD

0

1

Powered

Powered down

Reserved.

Always write these bits as 11.

Watchdog oscillator power control in Deep-sleep

mode, see Table 41

.

Powered

0

0

7

10:8

12:11

31:13 -

NOTUSED

NOTUSED

NOTUSED

0

Powered down

Reserved.

Always write this bit as 1.

Reserved.

Always write these bits as 000.

Reserved.

Always write these bits as 11.

Reserved

0

0

0

0

3.5.35 Wake-up configuration register

The bits in this register determine the state the chip enters when it is waking up from

Deep-sleep mode.

By default, the IRC and flash memory are powered and running and the BOD circuit is enabled when the chip wakes up from Deep-sleep mode.

Remark:

Reserved bits must be always written as indicated.

Table 43.

Bit

Wake-up configuration register (PDAWAKECFG, address 0x4004 8234) bit description

Symbol Value Description Reset value

0 IRCOUT_PD IRC oscillator output wake-up configuration 0

1 IRC_PD

0

1

0

1

Powered

Powered down

IRC oscillator power-down wake-up configuration

Powered

0

2 FLASH_PD

0

1

Powered down

Flash wake-up configuration

Powered

Powered down

0

3 BOD_PD

0

1

BOD wake-up configuration

Powered

Powered down

0

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8

9

10

11

12

15:13

31:16

Table 43.

Bit

Wake-up configuration register (PDAWAKECFG, address 0x4004 8234) bit description

…continued

Symbol Value Description Reset value

4 ADC_PD 1

0

1

ADC wake-up configuration

Powered

Powered down

5 SYSOSC_PD 1

6

7

WDTOSC_PD

SYSPLL_PD

0

1

0

1

0

1

System oscillator wake-up configuration

Powered

Powered down

Watchdog oscillator wake-up configuration

Powered

Powered down

System PLL wake-up configuration

Powered

1

1

-

-

-

-

-

-

-

-

Powered down

Reserved.

Always write this bit as 1.

Reserved.

Always write this bit as 0.

Reserved.

Always write this bit as 1.

Reserved.

Always write this bit as 1.

Reserved.

Always write this bit as 0.

Reserved.

Always write these bits as 111.

Reserved

1

0

1

1

0

-

111

3.5.36 Power-down configuration register

The bits in the PDRUNCFG register control the power to the various analog blocks. This register can be written to at any time while the chip is running, and a write will take effect immediately with the exception of the power-down signal to the IRC.

To avoid glitches when powering down the IRC, the IRC clock is automatically switched off at a clean point. Therefore, for the IRC a delay is possible before the power-down state takes effect.

By default, the IRC and flash memory are powered and running and the BOD circuit is enabled.

Remark:

Reserved bits must be always written as indicated.

Table 44.

Bit

Power-down configuration register (PDRUNCFG, address 0x4004 8238) bit description

Symbol Value Description Reset value

0 IRCOUT_PD IRC oscillator output power-down 0

0

1

Powered

Powered down

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Chapter 3: LPC111x/LPC11Cxx System configuration (SYSCON)

8

9

10

11

12

15:13

31:16

Table 44.

Bit

Power-down configuration register (PDRUNCFG, address 0x4004 8238) bit description

…continued

Symbol Value Description Reset value

1 IRC_PD 0

0

1

IRC oscillator power-down

Powered

Powered down

2 FLASH_PD 0

3

4

BOD_PD

ADC_PD

0

1

0

1

0

1

Flash power-down

Powered

Powered down

BOD power-down

Powered

Powered down

ADC power-down

Powered

0

1

5

6

7

SYSOSC_PD

WDTOSC_PD

SYSPLL_PD

0

1

0

1

Powered down

System oscillator power-down

Powered

Powered down

Watchdog oscillator power-down

Powered

Powered down

System PLL power-down

1

1

1

-

-

-

-

-

-

-

-

0

1

Powered

Powered down

Reserved.

Always write this bit as 1.

Reserved.

Always write this bit as 0.

Reserved.

Always write this bit as 1.

Reserved.

Always write this bit as 1.

Reserved.

Always write this bit as 0.

Reserved.

Always write these bits as 111.

Reserved

1

1

1

0

-

0

111

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3.5.37 Device ID register

This device ID register is a read-only register and contains the part ID for each

LPC111x/LPC11Cxx part. This register is also read by the ISP/IAP commands

(

Section 26.5.11

).

Remark:

This register returns the part ID for parts of the LPC1100, LPC1100C, and

LPC1100L series only. Use ISP/IAP to obtain the part ID for the LPC1100XL series.

The part IDs for the various parts are shown in the following list. Some parts have two valid part IDs.

LPC1110

0x0A07 102B = LPC1110FD20

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0x1A07 102B = LPC1110FD20

LPC1111

0x0A16 D02B = LPC1111FDH20/002

0x1A16 D02B = LPC1111FDH20/002

0x041E 502B = LPC1111FHN33/101

0x2516 D02B = LPC1111FHN33/101; LPC1111FHN33/102

0x0416 502B = LPC1111FHN33/201

0x2516 902B = LPC1111FHN33/201; LPC1111FHN33/202

LPC1112

0x0A24 902B = LPC1112FD20/102; LPC1112FDH20/102; LPC1112FDH28/102

0x1A24 902B = LPC1112FD20/102; LPC1112FDH20/102; LPC1112FDH28/102

0x042D 502B = LPC1112FHN33/101

0x2524 D02B = LPC1112FHN33/101; LPC1112FHN33/102

0x0425 502B = LPC1112FHN33/201

0x2524 902B = LPC1112FHN33/201; LPC1112FHN33/202; LPC1112FHI33/202;

LPC1112FHN24/202

LPC1113

0x0434 502B = LPC1113FHN33/201

0x2532 902B = LPC1113FHN33/201; LPC1113FHN33/202

0x0434 102B = LPC1113FHN33/301; LPC1113FBD48/301

0x2532 102B = LPC1113FHN33/301; LPC1113FHN33/302; LPC1113FBD48/301;

LPC1113FBD48/302

LPC1114

0x0A40 902B = LPC1114FDH28/102; LPC1114FN28/102

0x1A40 902B = LPC1114FDH28/102; LPC1114FN28/102

0x0444 502B = LPC1114FHN33/201

0x2540 902B = LPC1114FHN33/201; LPC1114FHN33/202

0x0444 102B = LPC1114FHN33/301; LPC1114FBD48/301

0x2540 102B = LPC1114FHN33/301; LPC1114FHN33/302; LPC1114FHI33/302;

LPC1114FBD48/301; LPC1114FBD48/302; LPC11D14FBD100/302

LPC11Cxx

0x1440 102B = LPC11C14/FBD48/301

0x1431 102B = LPC11C22/FBD48/301

0x1430 102B = LPC11C24/FBD48/301

Table 45.

Bit

31:0

Device ID register (DEVICE_ID, address 0x4004 83F4) bit description

Symbol

DEVICEID

Description

Part ID numbers for LPC111x/LPC11Cxx parts

Reset value

part-dependent

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3.6 Reset

Reset has four sources on the LPC111x/LPC11Cxx: the RESET pin, Watchdog Reset,

Power-On Reset (POR), and Brown Out Detect (BOD). In addition, there is an ARM software reset.

The RESET pin is a Schmitt trigger input pin. Assertion of chip Reset by any source, once the operating voltage attains a usable level, starts the IRC causing reset to remain asserted until the external Reset is de-asserted, the oscillator is running, and the flash controller has completed its initialization.

On the assertion of any reset source (ARM software reset, POR, BOD reset, External reset, and Watchdog reset), the following processes are initiated:

1. The IRC starts up. After the IRC-start-up time (maximum of 6

 s on power-up), the

IRC provides a stable clock output.

2. The flash is powered up. This takes approximately 100

 s. Then the flash initialization sequence is started.

3. The boot code in the ROM starts. The boot code performs the boot tasks and may jump to the flash.

When the internal Reset is removed, the processor begins executing at address 0, which is initially the Reset vector mapped from the boot block. At that point, all of the processor and peripheral registers have been initialized to predetermined values.

3.7 Start-up behavior

See

Figure 9 for the start-up timing after reset. The IRC is the default clock at Reset and

provides a clean system clock shortly after the supply voltage reaches the threshold value of 1.8 V.

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IRC starts

IRC status internal reset

V

DD valid threshold

= 1.8V

GND

80 μs 101 μs supply ramp-up time boot time

55 μs user code processor status boot code execution finishes; user code starts

Fig 9.

Start-up timing

3.8 Brown-out detection

The LPC111x/LPC11Cxx includes up to four levels for monitoring the voltage on the V

DD pin. If this voltage falls below one of the selected levels, the BOD asserts an interrupt signal to the NVIC. This signal can be enabled for interrupt in the Interrupt Enable

Register in the NVIC in order to cause a CPU interrupt; if not, software can monitor the signal by reading the NVIC status register (see

Table 55

). Four threshold levels can be

selected to cause a forced reset of the chip (see Table 33 ).

3.9 Power management

The LPC111x/LPC11Cxx support a variety of power control features. In Active mode, when the chip is running, power and clocks to selected peripherals can be optimized for power consumption. In addition, there are three special modes of processor power reduction: Sleep mode, Deep-sleep mode, and Deep power-down mode.

Remark:

The Debug mode is not supported in Sleep, Deep-sleep, or Deep power-down modes.

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3.9.1 Active mode

In Active mode, the ARM Cortex-M0 core and memories are clocked by the system clock, and peripherals are clocked by the system clock or a dedicated peripheral clock.

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The chip is in Active mode after reset and the default power configuration is determined by the reset values of the PDRUNCFG and SYSAHBCLKCTRL registers. The power configuration can be changed during run time.

3.9.1.1 Power configuration in Active mode

Power consumption in Active mode is determined by the following configuration choices:

The SYSAHBCLKCTRL register controls which memories and peripherals are running (

Table 21 ).

The power to various analog blocks (PLL, oscillators, the ADC, the BOD circuit, and the flash block) can be controlled at any time individually through the PDRUNCFG

register ( Table 44 ).

The clock source for the system clock can be selected from the IRC (default), the

system oscillator, or the watchdog oscillator (see Figure 8

and related registers).

The system clock frequency can be selected by the SYSPLLCTRL ( Table 10 ) and the

SYSAHBCLKDIV register (

Table 20 ).

Selected peripherals (UART, SPI0/1, WDT) use individual peripheral clocks with their own clock dividers. The peripheral clocks can be shut down through the

corresponding clock divider registers ( Table 22 to

Table 24

).

3.9.2 Sleep mode

In Sleep mode, the system clock to the ARM Cortex-M0 core is stopped, and execution of instructions is suspended until either a reset or an enabled interrupt occurs.

Peripheral functions, if selected to be clocked in the SYSAHBCLKCTRL register, continue operation during Sleep mode and may generate interrupts to cause the processor to resume execution. Sleep mode eliminates dynamic power used by the processor itself, memory systems and their related controllers, and internal buses. The processor state and registers, peripheral registers, and internal SRAM values are maintained, and the logic levels of the pins remain static.

3.9.2.1 Power configuration in Sleep mode

Power consumption in Sleep mode is configured by the same settings as in Active mode:

The clock remains running.

The system clock frequency remains the same as in Active mode, but the processor is not clocked.

Analog and digital peripherals are selected as in Active mode.

3.9.2.2 Programming Sleep mode

The following steps must be performed to enter Sleep mode:

1. The DPDEN bit in the PCON register must be set to zero (

Table 50

).

2. The SLEEPDEEP bit in the ARM Cortex-M0 SCR register must be set to zero, see

(

Table 453 ).

3. Use the ARM Cortex-M0 Wait-For-Interrupt (WFI) instruction.

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3.9.2.3 Wake-up from Sleep mode

Sleep mode is exited automatically when an interrupt enabled by the NVIC arrives at the processor or a reset occurs. After wake-up due to an interrupt, the microcontroller returns to its original power configuration defined by the contents of the PDRUNCFG and the

SYSAHBCLKDIV registers. If a reset occurs, the microcontroller enters the default configuration in Active mode.

3.9.3 Deep-sleep mode

In Deep-sleep mode, the system clock to the processor is disabled as in Sleep mode. All analog blocks are powered down, except for the BOD circuit and the watchdog oscillator, which must be selected or deselected during Deep-sleep mode in the PDSLEEPCFG register.

Deep-sleep mode eliminates all power used by the flash and analog peripherals and all dynamic power used by the processor itself, memory systems and their related controllers, and internal buses. The processor state and registers, peripheral registers, and internal SRAM values are maintained, and the logic levels of the pins remain static.

3.9.3.1 Power configuration in Deep-sleep mode

Power consumption in Deep-sleep mode is determined by the Deep-sleep power configuration setting in the PDSLEEPCFG (

Table 42 ) register:

The only clock source available in Deep-sleep mode is the watchdog oscillator. The watchdog oscillator can be left running in Deep-sleep mode if required for

timer-controlled wake-up (see Section 3.10.3

). All other clock sources (the IRC and system oscillator) and the system PLL are shut down. The watchdog oscillator analog output frequency must be set to the lowest value of its analog clock output (bits

FREQSEL in the WDTOSCCTRL = 0001, see Table 13

).

The BOD circuit can be left running in Deep-sleep mode if required by the application.

If the watchdog oscillator is running in Deep-sleep mode, only the watchdog timer or one of the general-purpose timers should be enabled in SYSAHBCLKCTRL register to minimize power consumption.

3.9.3.2 Programming Deep-sleep mode

The following steps must be performed to enter Deep-sleep mode:

1. The DPDEN bit in the PCON register must be set to zero (

Table 50

).

2. Select the power configuration in Deep-sleep mode in the PDSLEEPCFG (

Table 42

) register.

a. If a timer-controlled wake-up is needed, ensure that the watchdog oscillator is powered in the PDRUNCFG register and switch the clock source to WD oscillator

in the MAINCLKSEL register ( Table 18

).

b. If no timer-controlled wake-up is needed and the watchdog oscillator is shut down, ensure that the IRC is powered in the PDRUNCFG register and switch the clock source to IRC in the MAINCLKSEL register (

Table 18 ). This ensures that the

system clock is shut down glitch-free.

3. Select the power configuration after wake-up in the PDAWAKECFG (

Table 43 )

register.

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4. If an external pin is used for wake-up, enable and clear the wake-up pin in the start

logic registers ( Table 37

to

Table 40 ), and enable the start logic interrupt in the NVIC.

5. In the SYSAHBCLKCTRL register (

Table 21 ), disable all peripherals except

counter/timer or WDT if needed.

6. Write one to the SLEEPDEEP bit in the ARM Cortex-M0 SCR register ( Table 453

).

7. Use the ARM WFI instruction.

3.9.3.3 Wake-up from Deep-sleep mode

The microcontroller can wake up from Deep-sleep mode in the following ways:

Signal on an external pin. For this purpose, pins PIO0_0 to PIO0_11 and PIO1_0 can be enabled as inputs to the start logic. The start logic does not require any clocks and generates the interrupt if enabled in the NVIC to wake up from Deep-sleep mode.

Input signal to the start logic created by a match event on one of the general purpose timer external match outputs. The pin holding the timer match function must be enabled as start logic input in the NVIC, the corresponding timer must be enabled in the SYSAHBCLKCTRL register, and the watchdog oscillator must be running in

Deep-sleep mode (for details see

Section 3.10.3

).

Reset from the BOD circuit. In this case, the BOD circuit must be enabled in the

PDSLEEPCFG register, and the BOD reset must be enabled in the BODCTRL register (

Table 33 ).

Reset from the watchdog timer. In this case, the watchdog oscillator must be running in Deep-sleep mode (see PDSLEEPCFG register), and the WDT must be enabled in the SYSAHBCLKCTRL register.

A reset signal from the external RESET pin.

Remark:

If the watchdog oscillator is running in Deep-sleep mode, its frequency determines the wake-up time causing the wake-up time to be longer than waking up with the IRC.

Remark:

After wake-up, reprogram the clock source for the main clock.

3.9.4 Deep power-down mode

In Deep power-down mode, power and clocks are shut off to the entire chip with the exception of the WAKEUP pin.

During Deep power-down mode, the contents of the SRAM and registers are not retained except for a small amount of data which can be stored in the five 32-bit general purpose registers of the PMU block.

All functional pins are tri-stated in Deep power-down mode except for the WAKEUP pin.

3.9.4.1 Power configuration in Deep power-down mode

Deep power-down mode has no configuration options. All clocks, the core, and all peripherals are powered down. Only the WAKEUP pin is powered.

3.9.4.2 Programming Deep power-down mode

The following steps must be performed to enter Deep power-down mode:

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1. Write one to the DPDEN bit in the PCON register (see

Table 50 ).

2. Store data to be retained in the general purpose registers (

Table 51

).

3. Write one to the SLEEPDEEP bit in the ARM Cortex-M0 SCR register ( Table 453

).

4. Ensure that the IRC is powered by setting bits IRCOUT_PD and IRC_PD to zero in the PDRUNCFG register before entering Deep power-down mode.

Remark:

This step is part dependent.

See

Section 3.1

for part specific details.

5. Use the ARM WFI instruction.

Remark:

The WAKEUP pin must be pulled HIGH externally before entering Deep power-down mode.

3.9.4.3 Wake-up from Deep power-down mode

Pulling the WAKEUP pin LOW wakes up the LPC111x/LPC11Cxx from Deep power-down,

and the chip goes through the entire reset process ( Section 3.6

). The minimum pulse width for the HIGH-to-LOW transition on the WAKEUP pin is 50 ns.

Follow these steps to wake up the chip from Deep power-down mode:

1. A wake-up signal is generated when a HIGH-to-LOW transition occurs externally on the WAKEUP pin with a pulse length of at least 50 ns while the part is in Deep power-down mode.

The PMU will turn on the on-chip voltage regulator. When the core voltage reaches the power-on-reset (POR) trip point, a system reset will be triggered and the chip re-boots.

All registers except the GPREG0 to GPREG4and PCON will be in their reset state.

2. Once the chip has booted, read the deep power-down flag in the PCON register

(

Table 50

) to verify that the reset was caused by a wake-up event from Deep power-down.

3. Clear the deep power-down flag in the PCON register (

Table 50 ).

4. (Optional) Read the stored data in the general purpose registers (

Table 51

and

Table 52

).

5. Set up the PMU for the next Deep power-down cycle.

Remark:

The RESET pin has no functionality in Deep power-down mode.

3.10 Deep-sleep mode details

3.10.1 IRC oscillator

The IRC is the only oscillator on the LPC111x/LPC11Cxx that can always shut down glitch-free. Therefore it is recommended that the user switches the clock source to IRC before the chip enters Deep-sleep mode.

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3.10.2 Start logic

The Deep-sleep mode is exited when the start logic indicates an interrupt to the ARM core. The port pins PIO0_0 to PIO0_11 and PIO1_0 are connected to the start logic and serve as wake-up pins. The user must program the start logic registers for each input to

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set the appropriate edge polarity for the corresponding wake-up event. Furthermore, the interrupts corresponding to each input must be enabled in the NVIC. Interrupts 0 to 12 in

the NVIC correspond to 13 PIO pins (see Section 3.5.30

).

The start logic does not require a clock to run because it uses the input signals on the enabled pins to generate a clock edge when enabled. Therefore, the start logic signals should be cleared (see

Table 39

) before use.

The start logic can also be used in Active mode to provide a vectored interrupt using the

LPC111x/LPC11Cxx’s input pins.

3.10.3 Using the general purpose counter/timers to create a self-wake-up event

If enabled in Deep-sleep mode through the SYSAHBCLKCFG register, the counter/timers can count clock cycles of the watchdog oscillator and create a match event when the number of cycles equals a preset match value. The match event causes the corresponding match output pin to go HIGH, LOW, or toggle. The state of the match output pin is also monitored by the start logic and can trigger a wake-up interrupt if that pin is enabled in the NVIC and the start logic trigger is configured accordingly in the start logic

edge control register (see Table 37 ).

The following steps must be performed to configure the counter/timer and create a timed

Deep-sleep self-wake-up event:

1. Configure the port pin as match output in the IOCONFIG block. Select from pins

PIO0_1 or PIO0_8 to PIO0_11, which are inputs to the start logic and also hold a match output function.

2. In the corresponding counter/timer, set the match value, and configure the match output for the selected pin.

3. Select the watchdog oscillator to run in Deep-sleep mode in the PDSLEEPCFG register.

4. Switch the clock source to the watchdog oscillator in the MAINCLKSEL register

(

Table 18

) and ensure the watchdog oscillator is powered in the PDRUNCFG register.

5. Enable the pin, configure its edge detect function, and reset the start logic in the start

logic registers ( Table 37

to

Table 40 ), and enable the interrupt in the NVIC.

6. Disable all other peripherals in the SYSAHBCLKCTRL register.

7. Ensure that the DPDEN bit in the PCON register is set to zero (

Table 50 ).

8. Write one to the SLEEPDEEP bit in the ARM Cortex-M0 SCR register ( Table 453

).

9. Start the counter/timer.

10. Use the ARM WFI instruction to enter Deep-sleep mode.

3.11 System PLL functional description

The LPC111x/LPC11Cxx uses the system PLL to create the clocks for the core and peripherals.

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irc_osc_clk sys_osc_clk

FCLKIN

SYSPLLCLKSEL

PFD pd

LOCK

FCCO pd

PSEL<1:0>

2 cd

/2P

LOCK

DETECT

FCLKOUT analog section pd cd

/M

5

MSEL<4:0>

Fig 10. System PLL block diagram

The block diagram of this PLL is shown in

Figure 10

. The input frequency range is 10 MHz to 25 MHz. The input clock is fed directly to the Phase-Frequency Detector (PFD). This block compares the phase and frequency of its inputs, and generates a control signal when phase and/ or frequency do not match. The loop filter filters these control signals and drives the current controlled oscillator (CCO), which generates the main clock and optionally two additional phases. The CCO frequency range is 156 MHz to

320 MHz.These clocks are either divided by 2

P by the programmable post divider to create the output clock(s), or are sent directly to the output(s). The main output clock is then divided by M by the programmable feedback divider to generate the feedback clock.

The output signal of the phase-frequency detector is also monitored by the lock detector, to signal when the PLL has locked on to the input clock.

Remark:

The divider values for P and M must be selected so that the PLL output clock frequency FCLKOUT is lower than 100 MHz.

3.11.1 Lock detector

The lock detector measures the phase difference between the rising edges of the input and feedback clocks. Only when this difference is smaller than the so called “lock criterion” for more than eight consecutive input clock periods, the lock output switches from low to high. A single too large phase difference immediately resets the counter and causes the lock signal to drop (if it was high). Requiring eight phase measurements in a row to be below a certain figure ensures that the lock detector will not indicate lock until both the phase and frequency of the input and feedback clocks are very well aligned. This effectively prevents false lock indications, and thus ensures a glitch free lock signal.

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3.11.2 Power-down control

To reduce the power consumption when the PLL clock is not needed, a Power-down mode has been incorporated. This mode is enabled by setting the SYSPLL_PD bits to one

in the Power-down configuration register ( Table 44 ). In this mode, the internal current

reference will be turned off, the oscillator and the phase-frequency detector will be

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stopped and the dividers will enter a reset state. While in Power-down mode, the lock output will be low to indicate that the PLL is not in lock. When the Power-down mode is terminated by setting the SYSPLL_PD bits to zero, the PLL will resume its normal operation and will make the lock signal high once it has regained lock on the input clock.

3.11.3 Divider ratio programming

Post divider

The division ratio of the post divider is controlled by the PSEL bits. The division ratio is two times the value of P selected by PSEL bits as shown in

Table 10

. This guarantees an output clock with a 50% duty cycle.

Feedback divider

The feedback divider’s division ratio is controlled by the MSEL bits. The division ratio between the PLL’s output clock and the input clock is the decimal value on MSEL bits plus

one, as specified in Table 10 .

Changing the divider values

Changing the divider ratio while the PLL is running is not recommended. As there is no way to synchronize the change of the MSEL and PSEL values with the dividers, the risk exists that the counter will read in an undefined value, which could lead to unwanted spikes or drops in the frequency of the output clock. The recommended way of changing between divider settings is to power down the PLL, adjust the divider settings and then let the PLL start up again.

3.11.4 Frequency selection

The PLL frequency equations use the following parameters (also see Figure 8

):

Table 46.

Parameter

FCLKIN

FCCO

PLL frequency parameters

System PLL

Frequency of sys_pllclkin (input clock to the system PLL) from the

SYSPLLCLKSEL multiplexer (see

Section 3.5.9

).

Frequency of the Current Controlled Oscillator (CCO); 156 to 320 MHz.

FCLKOUT

P

M

Frequency of sys_pllclkout. FCLKOUT must be < 100 MHz.

System PLL post divider ratio; PSEL bits in SYSPLLCTRL (see

System PLL feedback divider register; MSEL bits in SYSPLLCTRL (see

Section 3.5.3

).

Section 3.5.3

).

3.11.4.1 Normal mode

In normal mode the post divider is enabled, giving a 50% duty cycle clock with the following frequency relations:

(1)

FCLKOUT

=

M

FCLKIN

=

FCCO

  

2

P

To select the appropriate values for M and P, it is recommended to follow these steps:

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1. Specify the input clock frequency FCLKIN.

2. Calculate M to obtain the desired output frequency FCLKOUT with

M = FCLKOUT / FCLKIN.

3. Find a value so that FCCO = 2

P

FCLKOUT.

4. Verify that all frequencies and divider values conform to the limits specified in

Table 10

.

5. Ensure that FCLKOUT < 100 MHz.

Table 47

shows how to configure the PLL for a 12 MHz crystal oscillator using the

SYSPLLCTRL register (

Table 10 ). The main clock is equivalent to the system clock if the

system clock divider SYSAHBCLKDIV is set to one (see

Table 20

).

Table 47.

PLL input clock sys_pllclkin

(FCLKIN)

PLL configuration examples

Main clock

(FCLKOUT)

MSEL bits

Table 10

12 MHz 48 MHz 00011

12 MHz

12 MHz

36 MHz

24 MHz

00010

00001

M divider value

PSEL bits

Table 10

4

3

2

01

10

10

2

4

4

P divider value

FCCO frequency

192 MHz

288 MHz

192 MHz

3.11.4.2 Power-down mode

In this mode, the internal current reference is turned off, the oscillator and the phase-frequency detector are stopped, and the dividers enter a reset state. While in

Power-down mode, the lock output is be LOW to indicate that the PLL is not in lock. When the Power-down mode is terminated by setting the SYSPLL_PD bit to zero in the

Power-down configuration register ( Table 44

), the PLL resumes its normal operation and asserts the lock signal HIGH once it has regained lock on the input clock.

3.12 Flash memory access

Depending on the system clock frequency, access to the flash memory can be configured with various access times by writing to the FLASHCFG register at address 0x4003 C010.

This register is part of the flash configuration block (see Figure 6

).

Remark:

Improper setting of this register may result in incorrect operation of the

LPC111x/LPC11Cxx flash memory. Do not manipulate the FLASHCFG register when using power profiles (set_power() and/or set_pll() API’s).

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Table 48.

Bit

Flash configuration register (FLASHCFG, address 0x4003 C010) bit description

Symbol Value Description Reset value

1:0 FLASHTIM 10

00

Flash memory access time. FLASHTIM +1 is equal to the number of system clocks used for flash access.

1 system clock flash access time (for system clock frequencies of up to 20 MHz).

01

31:2 -

10

11

2 system clocks flash access time (for system clock frequencies of up to 40 MHz).

3 system clocks flash access time (for system clock frequencies of up to 50 MHz).

Reserved.

Reserved.

User software must not change the value of these bits. Bits 31:2 must be written back exactly as read

.

-

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4.1 How to read this chapter

Remark:

For parts LPC11(D)1x/102/202/302, also refer to Chapter 5

for power control.

4.2 Introduction

The PMU controls the Deep power-down mode. Four general purpose register in the PMU can be used to retain data during Deep power-down mode.

4.3 Register description

Table 49.

Name

PCON

GPREG0

GPREG1

GPREG2

GPREG3

GPREG4

Register overview: PMU (base address 0x4003 8000)

Access Address offset

Description

R/W 0x000 Power control register

R/W

R/W

R/W

R/W

R/W

0x004

0x008

0x00C

0x010

0x014

General purpose register 0

General purpose register 1

General purpose register 2

General purpose register 3

General purpose register 4

Reset value

0x0

0x0

0x0

0x0

0x0

0x0

4.3.1 Power control register

The power control register selects whether one of the ARM Cortex-M0 controlled power-down modes (Sleep mode or Deep-sleep mode) or the Deep power-down mode is entered and provides the flags for Sleep or Deep-sleep modes and Deep power-down

modes respectively. See Section 3.9

for details on how to enter the power-down modes.

Table 50.

Bit

0

1

7:2

-

-

Power control register (PCON, address 0x4003 8000) bit description

Symbol

DPDEN

-

-

Value

0

1

Description

Reserved. Do not write 1 to this bit.

Deep power-down mode enable

ARM WFI will enter Sleep or Deep-sleep mode (clock to

ARM Cortex-M0 core turned off).

ARM WFI will enter Deep-power down mode (ARM

Cortex-M0 core powered-down).

Reserved. Do not write ones to this bit.

Reset value

0x0

0

0x0

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Table 50.

Bit

Power control register (PCON, address 0x4003 8000) bit description

Symbol Value Description

…continued

Reset value

8 SLEEPFLAG 0

10:9

11

31:12 -

-

DPDFLAG

-

-

0

1

0

1

Sleep mode flag

Read: No power-down mode entered.

LPC111x/LPC11Cxx is in Active mode.

Write: No effect.

Read: Sleep/Deep-sleep or Deep power-down mode entered.

Write: Writing a 1 clears the SLEEPFLAG bit to 0.

Reserved. Do not write ones to this bit.

Deep power-down flag

Read: Deep power-down mode

not

entered.

Write: No effect.

Read: Deep power-down mode entered.

Write: Clear the Deep power-down flag.

Reserved. Do not write ones to this bit.

0x0

0x0

0x0

0x0

0x0

4.3.2 General purpose registers 0 to 3

The general purpose registers retain data through the Deep power-down mode when power is still applied to the V

DD

pin but the chip has entered Deep power-down mode.

Only a “cold” boot when all power has been completely removed from the chip will reset the general purpose registers.

Table 51.

Bit

General purpose registers 0 to 3 (GPREG0 - GPREG3, address 0x4003 8004 to

0x4003 8010) bit description

Symbol Description Reset value

31:0 GPDATA Data retained during Deep power-down mode.

0x0

4.3.3 General purpose register 4

The general purpose register 4 retains data through the Deep power-down mode when power is still applied to the V

DD

pin but the chip has entered Deep power-down mode.

Only a “cold” boot, when all power has been completely removed from the chip, will reset the general purpose registers.

Remark:

If there is a possibility that the external voltage applied on pin V

DD

drops below

2.2 V during Deep power-down, the hysteresis of the WAKEUP input pin has to be disabled in this register before entering Deep power-down mode in order for the chip to wake up.

Table 52.

Bit

General purpose register 4 (GPREG4, address 0x4003 8014) bit description

Symbol Value Description Reset value

9:0 Reserved. Do not write ones to this bit.

0x0

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Chapter 4: LPC111x/LPC11Cxx Power Monitor Unit (PMU)

Table 52.

Bit

General purpose register 4 (GPREG4, address 0x4003 8014) bit description

Symbol Value Description Reset value

10 WAKEUPHYS 0x0

31:11 GPDATA

1

0

WAKEUP pin hysteresis enable

Hysteresis for WAKEUP pin enabled.

Hysteresis for WAKUP pin disabled.

Data retained during Deep power-down mode.

0x0

4.4 Functional description

For details of entering and exiting Deep power-down mode, see Section 3.9.4

.

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Chapter 5: LPC111x/LPC11Cxx Power profiles

Rev. 12.4 — 22 December 2016 User manual

5.1 How to read this chapter

The power profiles are available for parts LPC11(D)1x/102/202/302 only (LPC1100L series).

5.2 Basic configuration

Specific power profile settings are required in the following situation: When using IAP commands, configure the power profiles in Default mode.

Disable all interrupts before making calls to the power profile API. You can re-enable the interrupts after the power profile API calls have completed.

5.3 Features

Includes ROM-based application services

Power Management services

Clocking services

5.4 Description

The API calls to the ROM are performed by executing functions which are pointed by a pointer within the ROM Driver Table.

Figure 11 shows the pointer structure used to call the

Power Profiles API.

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Power API function table set_pll set_power

Ptr to ROM Driver table

0x1FFF 2004

0x1FFF 1FF8

0x1FFF 1FFC

0x1FFF 2000

0x1FFF 2004

ROM Driver Table

Ptr to Device Table 0

Ptr to Device Table 1

Ptr to Device Table 2

Ptr to PowerAPI Table

Device n

Ptr to Function 0

Ptr to Function 1

Ptr to Function 2

Ptr to Function n

Ptr to Device Table n

Fig 11. Power profiles pointer structure

irc_osc_clk main clock

CLOCK

DIVIDER system clock

SYSAHBCLKDIV

SYSAHBCLKCTRL[1]

(ROM enable)

ARM

CORTEX-M0

ROM wdt_osc_clk

SPI1 irc_osc_clk sys_osc_clk

MAINCLKSEL sys_pllclkout sys_pllclkin

SYS PLL

7

CLOCK

DIVIDER

SYSPLLCLKSEL

Fig 12. LPC111x/102/202/302 clock configuration for power API use

SYSAHBCLKCTRL[18]

(SPI1 enable)

Peripherals

5.5 Definitions

The following elements have to be defined in an application that uses the power profiles:

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typedef struct _PWRD { void (*set_pll)(unsigned int cmd[], unsigned int resp[]); void (*set_power)(unsigned int cmd[], unsigned int resp[]);

} PWRD; typedef struct _ROM { const PWRD * pWRD;

} ROM;

ROM ** rom = (ROM **) (0x1FFF1FF8 + 3 * sizeof(ROM**)); unsigned int command[4], result[2];

5.6 Clocking routine

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5.6.1 set_pll

This routine sets up the system PLL according to the calling arguments. If the expected clock can be obtained by simply dividing the system PLL input,

set_pll

bypasses the PLL to lower system power consumption.

Remark:

Before this routine is invoked, the PLL clock source (IRC/system oscillator) must

be selected ( Table 16 ), the main clock source must be set to the input clock to the system

PLL (

Table 18

) and the system/AHB clock divider must be set to 1 (

Table 20

).

set_pll

attempts to find a PLL setup that matches the calling parameters. Once a combination of a feedback divider value (SYSPLLCTRL, M), a post divider ratio

(SYSPLLCTRL, P) and the system/AHB clock divider (SYSAHBCLKDIV) is found,

set_pll

applies the selected values and switches the main clock source selection to the system

PLL clock out (if necessary).

The routine returns a result code that indicates if the system PLL was successfully set

(PLL_CMD_SUCCESS) or not (in which case the result code identifies what went wrong).

The current system frequency value is also returned. The application should use this information to adjust other clocks in the device (the SSP, UART, and WDT clocks, and/or clockout).

Table 53.

Routine

Input

Result

set_pll routine set_pll

Param0:

system PLL input frequency (in kHz)

Param1:

expected system clock (in kHz)

Param2:

mode (CPU_FREQ_EQU, CPU_FREQ_LTE, CPU_FREQ_GTE,

CPU_FREQ_APPROX)

Param3:

system PLL lock time-out

Result0:

PLL_CMD_SUCCESS | PLL_INVALID_FREQ | PLL_INVALID_MODE |

PLL_FREQ_NOT_FOUND | PLL_NOT_LOCKED

Result1:

system clock (in kHz)

The following definitions are needed when making set_pll power routine calls:

/* set_pll mode options */

#define CPU_FREQ_EQU

#define

#define

#define

CPU_FREQ_LTE

CPU_FREQ_GTE

CPU_FREQ_APPROX

0

1

2

3

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/* set_pll result0 options */

#define PLL_CMD_SUCCESS

#define

#define

#define

#define

PLL_INVALID_FREQ

PLL_INVALID_MODE

PLL_FREQ_NOT_FOUND

PLL_NOT_LOCKED

0

1

2

3

4

For a simplified clock configuration scheme see

Figure 12

. For more details see Figure 8

.

5.6.1.1 Param0: system PLL input frequency and Param1: expected system clock

set_pll

looks for a setup in which the system PLL clock does not exceed 50 MHz. It easily finds a solution when the ratio between the expected system clock and the system PLL input frequency is an integer value, but it can also find solutions in other cases.

The system PLL input frequency (

Param0

) must be between 10000 to 25000 kHz (10

MHz to 25 MHz) inclusive. The expected system clock (

Param1

) must be between 1 and

50000 kHz inclusive. If either of these requirements is not met,

set_pll

returns

PLL_INVALID_FREQ and returns

Param0

as

Result1

since the PLL setting is unchanged.

5.6.1.2 Param2: mode

The first priority of

set_pll

is to find a setup that generates the system clock at exactly the rate specified in

Param1

. If it is unlikely that an exact match can be found, input parameter mode (

Param2

) should be used to specify if the actual system clock can be less than or equal, greater than or equal or approximately the value specified as the expected system clock (

Param1

).

A call specifying CPU_FREQ_EQU will only succeed if the PLL can output exactly the frequency requested in

Param1

.

CPU_FREQ_LTE can be used if the requested frequency should not be exceeded (such as overall current consumption and/or power budget reasons).

CPU_FREQ_GTE helps applications that need a minimum level of CPU processing capabilities.

CPU_FREQ_APPROX results in a system clock that is as close as possible to the requested value (it may be greater than or less than the requested value).

If an illegal mode is specified,

set_pll

returns PLL_INVALID_MODE. If the expected system clock is out of the range supported by this routine,

set_pll

returns

PLL_FREQ_NOT_FOUND. In these cases the current PLL setting is not changed and

Param0

is returned as

Result1

.

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5.6.1.3 Param3: system PLL lock time-out

It should take no more than 100

 s for the system PLL to lock if a valid configuration is selected. If

Param3

is zero,

set_pll

will wait indefinitely for the PLL to lock. A non-zero value indicates how many times the code will check for a successful PLL lock event before it returns PLL_NOT_LOCKED. In this case the PLL settings are unchanged and

Param0

is returned as

Result1

.

Remark:

The time it takes the PLL to lock depends on the selected PLL input clock source (IRC/system oscillator) and its characteristics. The selected source can experience more or less jitter depending on the operating conditions such as power

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supply and/or ambient temperature. This is why it is suggested that when a good known clock source is used and a PLL_NOT_LOCKED response is received, the set_pll routine should be invoked several times before declaring the selected PLL clock source invalid.

Hint:

setting

Param3

equal to the system PLL frequency [Hz] divided by 10000 will provide more than enough PLL lock-polling cycles.

5.6.1.4 Code examples

The following examples illustrate some of the features of

set_pll

discussed above.

5.6.1.4.1

Invalid frequency (device maximum clock rate exceeded)

command[0] = 12000; command[1] = 60000; command[2] = CPU_FREQ_EQU; command[3] = 0;

(*rom)->pWRD->set_pll(command, result);

The above code specifies a 12 MHz PLL input clock and a system clock of exactly

60 MHz. The application was ready to infinitely wait for the PLL to lock. But the expected system clock of 60 MHz exceeds the maximum of 50 MHz. Therefore

set_pll

returns

PLL_INVALID_FREQ in

result[0]

and 12000 in

result[1]

without changing the PLL settings.

5.6.1.4.2

Invalid frequency selection (system clock divider restrictions)

command[0] = 12000; command[1] = 40; command[2] = CPU_FREQ_LTE; command[3] = 0;

(*rom)->pWRD->set_pll(command, result);

The above code specifies a 12 MHz PLL input clock, a system clock of no more than

40 kHz and no time-out while waiting for the PLL to lock. Since the maximum divider value for the system clock is 255 and running at 40 kHz would need a divide by value of 300,

set_pll

returns PLL_INVALID_FREQ in

result[0]

and 12000 in

result[1]

without changing the PLL settings.

5.6.1.4.3

Exact solution cannot be found (PLL)

command[0] = 12000; command[1] = 25000; command[2] = CPU_FREQ_EQU; command[3] = 0;

(*rom)->pWRD->set_pll(command, result);

The above code specifies a 12 MHz PLL input clock and a system clock of exactly

25 MHz. The application was ready to infinitely wait for the PLL to lock. Since there is no valid PLL setup within earlier mentioned restrictions,

set_pll

returns

PLL_FREQ_NOT_FOUND in

result[0]

and 12000 in

result[1]

without changing the PLL settings.

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5.6.1.4.4

System clock less than or equal to the expected value

command[0] = 12000; command[1] = 25000; command[2] = CPU_FREQ_LTE; command[3] = 0;

(*rom)->pWRD->set_pll(command, result);

The above code specifies a 12 MHz PLL input clock, a system clock of no more than

25 MHz and no locking time-out.

set_pll

returns PLL_CMD_SUCCESS in

result[0]

and

24000 in

result[1]

. The new system clock is 24 MHz.

5.6.1.4.5

System clock greater than or equal to the expected value

command[0] = 12000; command[1] = 25000; command[2] = CPU_FREQ_GTE; command[3] = 0;

(*rom)->pWRD->set_pll(command, result);

The above code specifies a 12 MHz PLL input clock, a system clock of at least 25 MHz and no locking time-out.

set_pll

returns PLL_CMD_SUCCESS in

result[0]

and 36000 in

result[1]

. The new system clock is 36 MHz.

5.6.1.4.6

System clock approximately equal to the expected value

command[0] = 12000; command[1] = 16500; command[2] = CPU_FREQ_APPROX; command[3] = 0;

(*rom)->pWRD->set_pll(command, result);

The above code specifies a 12 MHz PLL input clock, a system clock of approximately

16.5 MHz and no locking time-out.

set_pll

returns PLL_CMD_SUCCESS in

result[0]

and

16000 in

result[1]

. The new system clock is 16 MHz.

5.7 Power routine

5.7.1 set_power

This routine configures the device’s internal power control settings according to the calling arguments. The goal is to reduce active power consumption while maintaining the feature of interest to the application close to its optimum.

Remark:

The set_power routine was designed for systems employing the configuration of

SYSAHBCLKDIV = 1 (System clock divider register, see

Table 20

and Figure 12

). Using this routine in an application with the system clock divider not equal to 1 might not improve microcontroller’s performance as much as in setups when the main clock and the system clock are running at the same rate.

set_power

returns a result code that reports whether the power setting was successfully changed or not.

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Chapter 5: LPC111x/LPC11Cxx Power profiles

using power profiles and changing system clock current_clock, new_clock , new_mode use power routine call to change mode to

DEFAULT use either clocking routine call or custom code to change system clock from current_clock to new_clock use power routine call to change mode to new_mode end

Fig 13. Power profiles usage

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Table 54.

Routine

Input

Result

set_power routine set_power

Param0:

main clock (in MHz)

Param1:

mode (PWR_DEFAULT, PWR_CPU_PERFORMANCE, PWR_

EFFICIENCY, PWR_LOW_CURRENT)

Param2:

system clock (in MHz)

Result0:

PWR_CMD_SUCCESS | PWR_INVALID_FREQ |

PWR_INVALID_MODE

The following definitions are needed for set_power routine calls:

/* set_power mode options */

#define

#define

PWR_DEFAULT 0

PWR_CPU_PERFORMANCE 1

#define

#define

PWR_EFFICIENCY

PWR_LOW_CURRENT

2

3

/* set_power result0 options */

#define PWR_CMD_SUCCESS

#define

#define

PWR_INVALID_FREQ

PWR_INVALID_MODE

0

1

2

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For a simplified clock configuration scheme see

Figure 12

. For more details see Figure 8

.

5.7.1.1 Param0: main clock

The main clock is the clock rate the microcontroller uses to source the system’s and the peripherals’ clock. It is configured by either a successful execution of the clocking routine call or a similar code provided by the user. This operand must be an integer between 1 to

50 MHz inclusive. If a value out of this range is supplied,

set_power

returns

PWR_INVALID_FREQ and does not change the power control system.

5.7.1.2 Param1: mode

The input parameter mode (

Param1

) specifies one of four available power settings. If an illegal selection is provided,

set_power

returns PWR_INVALID_MODE and does not change the power control system.

PWR_DEFAULT keeps the device in a baseline power setting similar to its reset state.

PWR_CPU_PERFORMANCE configures the microcontroller so that it can provide more processing capability to the application. CPU performance is 30% better than the default option.

PWR_EFFICIENCY setting was designed to find a balance between active current and the CPU’s ability to execute code and process data. In this mode the device outperforms the default mode both in terms of providing higher CPU performance and lowering active current.

PWR_LOW_CURRENT is intended for those solutions that focus on lowering power consumption rather than CPU performance.

5.7.1.3 Param2: system clock

The system clock is the clock rate at which the microcontroller core is running when

set_power

is called. This parameter is an integer between from 1 and 50 MHz inclusive.

5.7.1.4 Code examples

The following examples illustrate some of the

set_power

features discussed above.

5.7.1.4.1

Invalid frequency (device maximum clock rate exceeded)

command[0] = 60; command[1] = PWR_CPU_PERFORMANCE; command[2] = 60;

(*rom)->pWRD->set_power(command, result);

The above setup would be used in a system running at the main and system clock of

60 MHz, with a need for maximum CPU processing power. Since the specified 60 MHz clock is above the 50 MHz maximum,

set_power

returns PWR_INVALID_FREQ in

result[0]

without changing anything in the existing power setup.

5.7.1.4.2

An applicable power setup

command[0] = 24; command[1] = PWR_CPU_EFFICIENCY; command[2] = 24;

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(*rom)->pWRD->set_power(command, result);

The above code specifies that an application is running at the main and system clock of

24 MHz with emphasis on efficiency.

set_power

returns PWR_CMD_SUCCESS in

result[0]

after configuring the microcontroller’s internal power control features.

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Chapter 6: LPC111x/LPC11Cxx Nested Vectored Interrupt

Controller (NVIC)

Rev. 12.4 — 22 December 2016 User manual

6.1 How to read this chapter

The C_CAN controller interrupt is available on parts LPC11Cxx only.

6.2 Introduction

The Nested Vectored Interrupt Controller (NVIC) is an integral part of the Cortex-M0. The tight coupling to the CPU allows for low interrupt latency and efficient processing of late arriving interrupts.

6.3 Features

Nested Vectored Interrupt Controller that is an integral part of the ARM Cortex-M0

Tightly coupled interrupt controller provides low interrupt latency

Controls system exceptions and peripheral interrupts

The NVIC supports 32 vectored interrupts

4 programmable interrupt priority levels with hardware priority level masking

Software interrupt generation

6.4 Interrupt sources

Table 55

lists the interrupt sources for each peripheral function. Each peripheral device may have one or more interrupt lines to the Vectored Interrupt Controller. Each line may represent more than one interrupt source. There is no significance or priority about what line is connected where, except for certain standards from ARM.

See

Section 28.6.2

for the NVIC register bit descriptions.

Table 55.

Exception

Number

Connection of interrupt sources to the Vectored Interrupt Controller

Vector

Offset

Function Flag(s)

12 to 0

13

14

15 I start logic wake-up interrupts

C_CAN

SPI/SSP1

2

C

Each interrupt is connected to a PIO input pin serving as wake-up pin from Deep-sleep mode; Interrupt 0 to

11 correspond to PIO0_0 to PIO0_11 and interrupt

12 corresponds to PIO1_0; see Section 3.5.30

.

C_CAN interrupt

Tx FIFO half empty

Rx FIFO half full

Rx Timeout

Rx Overrun

SI (state change)

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Table 55.

Exception

Number

Connection of interrupt sources to the Vectored Interrupt Controller

Vector

Offset

Function Flag(s)

16 CT16B0

17

18

19

CT16B1

CT32B0

CT32B1

Match 0 - 2

Capture 0

Match 0 - 1

Capture 0

Match 0 - 3

Capture 0

Match 0 - 3

Capture 0

20 SPI/SSP0

21

26

27

28

29

22

23

24

25

30

31

-

-

UART

ADC

WDT

-

BOD

PIO_3

PIO_2

PIO_1

PIO_0

Tx FIFO half empty

Rx FIFO half full

Rx Timeout

Rx Overrun

Rx Line Status (RLS)

Transmit Holding Register Empty (THRE)

Rx Data Available (RDA)

Character Time-out Indicator (CTI)

End of Auto-Baud (ABEO)

Auto-Baud Time-Out (ABTO)

Reserved

Reserved

A/D Converter end of conversion

Watchdog interrupt (WDINT)

Brown-out detect

Reserved

GPIO interrupt status of port 3

GPIO interrupt status of port 2

GPIO interrupt status of port 1

GPIO interrupt status of port 0

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Chapter 7: LPC1100/LPC1100C/LPC1100L series: I/O configuration (IOCONFIG)

Rev. 12.4 — 22 December 2016 User manual

7.1 How to read this chapter

Remark:

This chapter applies to parts in the following series (see

Table 1

):

LPC1100

LPC1100L

LPC1100C

LPC11D14

Pin configuration

The implementation of the I/O configuration registers varies for different

LPC111x/LPC11Cxx parts and packages.

Table 57

shows which IOCON registers are used on the different packages.

C_CAN pins

For the LPC11C12/C14, functions PIO3_4 and PIO3_5 are not available. Instead, two pins are dedicated to the C_CAN receive and transmit functions (see

Table 57

) without pull-up or pull-down resistors. The C_CAN pins have no programmable pin configuration.

For the LPC11C22/C24, pins PIO1_9, PIO2_4, PIO2_5, and PIO2_9 are not available and are replaced by the on-chip CAN transceiver pins. The CAN transceiver pins have no programmable pin configuration.

Pseudo open-drain function

For the LPC11(D)1x/102/202/302, a pseudo open-drain mode can be selected in the

IOCON registers for each digital pin except the I2C pins (see Figure 14

). The open-drain mode is not available for the LPC111x/101/201/301 parts.

Pull-up level

If the pull-up resistor is enabled (default), all non-I2C pins are pulled up to 2.6 V for

LPC111x/101/201/301 parts and pulled up to 3.3 V for LPC11Cxx parts and

LPC111x/102/202/302 (V

DD

= 3.3 V).

7.2 Features

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The I/O configuration registers control the electrical characteristics of the pads. The following features are programmable:

Pin function.

Internal pull-up/pull-down resistor or bus keeper function.

Hysteresis.

Analog input or digital mode for pads hosting the ADC inputs.

I

2

C mode for pads hosting the I

2

C-bus function.

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Pseudo open-drain mode for non-I2C pins (see Section 7.1

for part specific details).

7.3 General description

pin configured as digital output driver

The IOCON registers control the function (GPIO or peripheral function), the input mode, and the hysteresis of all PIOn_m pins. In addition, the I

2

C-bus pins can be configured for different I

2

C-bus modes. If a pin is used as input pin for the ADC, an analog input mode can be selected.

V

DD

V

DD open-drain enable output enable data output strong pull-up

ESD

PIN strong pull-down

ESD

V

SS pin configured as digital input repeater mode enable pull-up enable pull-down enable

V

DD weak pull-up weak pull-down data input select analog input pin configured as analog input analog input

002aah159

For open-drain mode, see Section 7.1

.

Fig 14. Standard I/O pin configuration

7.3.1 Pin function

The FUNC bits in the IOCON registers can be set to GPIO (FUNC = 000) or to a peripheral function. If the pins are GPIO pins, the GPIOnDIR registers determine whether

the pin is configured as an input or output (see Section 12.3.2

). For any peripheral function, the pin direction is controlled automatically depending on the pin’s functionality.

The GPIOnDIR registers have no effect for peripheral functions.

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Chapter 7: LPC1100/LPC1100C/LPC1100L series: I/O configuration

7.3.2 Pin mode

The MODE bits in the IOCON register allow the selection of on-chip pull-up or pull-down resistors for each pin or select the repeater mode.

The possible on-chip resistor configurations are pull-up enabled, pull-down enabled, or no

pull-up/pull-down. The default value is pull-up enabled. See Section 7.1

for part specific details.

The repeater mode enables the pull-up resistor if the pin is at a logic HIGH and enables the pull-down resistor if the pin is at a logic LOW. This causes the pin to retain its last known state if it is configured as an input and is not driven externally. The state retention is not applicable to the Deep power-down mode. Repeater mode may typically be used to prevent a pin from floating (and potentially using significant power if it floats to an indeterminate state) if it is temporarily not driven.

7.3.3 Hysteresis

The input buffer for digital functions can be configured with hysteresis or as plain buffer through the IOCON registers (see the

LPC111x and LPC11Cx data sheets

for details).

If the external pad supply voltage V

DD

is between 2.5 V and 3.6 V, the hysteresis buffer can be enabled or disabled. If V

DD

is below 2.5 V, the hysteresis buffer must be

disabled

to use the pin in input mode.

7.3.4 A/D-mode

In A/D-mode, the digital receiver is disconnected to obtain an accurate input voltage for analog-to-digital conversions. This mode can be selected in those IOCON registers that control pins with an analog function. HYS and MODE should be zero when AD mode is used.

For pins without analog functions, the A/D-mode setting has no effect.

7.3.5 I

2

C mode

If the I

2

C function is selected by the FUNC bits of registers IOCON_PIO0_4 ( Table 68 )

and IOCON_PIO0_5 ( Table 69

), then the I

2

C-bus pins can be configured for different

I

2

C-modes:

Standard mode/Fast-mode I

2

C with input glitch filter (this includes an open-drain output according to the I

2

C-bus specification).

Fast-mode Plus with input glitch filter (this includes an open-drain output according to the I

2

C-bus specification). In this mode, the pins function as high-current sinks.

Standard open-drain I/O functionality without input filter.

Remark:

Either Standard mode/Fast-mode I

2

C or Standard I/O functionality should be selected if the pin is used as GPIO pin.

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7.3.6 Open-drain Mode

When output is selected, either by selecting a special function in the FUNC field, or by selecting GPIO function for a pin having a 1 in its GPIODIR register, a 1 in the OD bit selects open-drain operation, that is, a 1 disables the high-drive transistor. This option has no effect on the primary I

2

C pins.

Remark:

The open-drain mode is not available on all parts (see

Section 7.1

).

7.4 Register description

The I/O configuration registers control the PIO port pins, the inputs and outputs of all peripherals and functional blocks, the I

2

C-bus pins, and the ADC input pins.

Each port pin PIOn_m has one IOCON register assigned to control the pin’s function and electrical characteristics.

Some input functions (SCK0, DSR, DCD, and RI) are multiplexed to several physical pins.

The IOCON_LOC registers select the pin location for each of these functions.

Remark:

The IOCON registers are listed in order of their memory locations in Table 56 ,

which correspond to the order of their physical pin numbers in the LQFP48 package

starting at the upper left corner with pin 1 (PIO2_6). See Table 57 for a listing of IOCON

registers ordered by port number.

The IOCON location registers are used to select a physical pin for multiplexed functions.

Remark:

Note that once the pin location has been selected, the function still must be configured in the corresponding IOCON registers for the function to be usable on that pin.

Table 56.

Name

Register overview: I/O configuration (base address 0x4004 4000)

Access Address offset

Description

IOCON_PIO2_6 R/W 0x000 I/O configuration for pin PIO2_6

-

IOCON_PIO2_0

IOCON_RESET_PIO0_0

IOCON_PIO0_1

R/W

R/W

R/W

R/W

0x004

0x008

0x00C

0x010

Reset value

0xD0

Reference

Reserved

I/O configuration for pin

PIO2_0/DTR/SSEL1

-

0xD0

I/O configuration for pin RESET/PIO0_0 0xD0

0xD0

Table 58

-

Table 59

Table 60

Table 61

IOCON_PIO1_8 R/W 0x014

I/O configuration for pin

PIO0_1/CLKOUT/CT32B0_MAT2

I/O configuration for pin

PIO1_8/CT16B1_CAP0

0xD0

Table 62

-

IOCON_PIO0_2

R/W

R/W

0x018

0x01C

Reserved

I/O configuration for pin

PIO0_2/SSEL0/CT16B0_CAP0

I/O configuration for pin PIO2_7

-

0xD0

-

Table 63

IOCON_PIO2_7

IOCON_PIO2_8

IOCON_PIO2_1

IOCON_PIO0_3

IOCON_PIO0_4

R/W

R/W

R/W

R/W

R/W

0x020

0x024

0x028

0x02C

0x030

I/O configuration for pin PIO2_8

I/O configuration for pin

PIO2_1/DSR/SCK1

I/O configuration for pin PIO0_3

I/O configuration for pin PIO0_4/SCL

0xD0

0xD0

0xD0

0xD0

0x00

Table 64

Table 65

Table 66

Table 67

Table 68

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Table 56.

Name

Register overview: I/O configuration (base address 0x4004 4000)

Access Address offset

Description

IOCON_PIO0_5

IOCON_PIO1_9

R/W

R/W

0x034

0x038

I/O configuration for pin PIO0_5/SDA

I/O configuration for pin

PIO1_9/CT16B1_MAT0

I/O configuration for pin PIO3_4 IOCON_PIO3_4

IOCON_PIO2_4

IOCON_PIO2_5

IOCON_PIO3_5

IOCON_PIO0_6

IOCON_PIO0_7

IOCON_PIO2_9

R/W

R/W

R/W

R/W

R/W

R/W

R/W

0x03C

0x040

0x044

0x048

0x04C

0x050

0x054

I/O configuration for pin PIO2_4

I/O configuration for pin PIO2_5

I/O configuration for pin PIO3_5

I/O configuration for pin PIO0_6/SCK0

IOCON_PIO2_10

IOCON_PIO2_2

IOCON_PIO0_8

IOCON_PIO0_9

IOCON_SWCLK_PIO0_10

IOCON_PIO1_10

R/W

R/W

R/W

R/W

R/W

R/W

0x058

0x05C

0x060

0x064

0x068

0x06C

I/O configuration for pin PIO0_7/CTS

I/O configuration for pin PIO2_9

I/O configuration for pin PIO2_10

I/O configuration for pin

PIO2_2/DCD/MISO1

I/O configuration for pin

PIO0_8/MISO0/CT16B0_MAT0

I/O configuration for pin

PIO0_9/MOSI0/CT16B0_MAT1

I/O configuration for pin

SWCLK/PIO0_10/

SCK0/CT16B0_MAT2

I/O configuration for pin

PIO1_10/AD6/CT16B1_MAT1

IOCON_PIO2_11

IOCON_R_PIO0_11

R/W

R/W

0x070

0x074

IOCON_R_PIO1_0

IOCON_R_PIO1_1

IOCON_R_PIO1_2

IOCON_PIO3_0

IOCON_PIO3_1

IOCON_PIO2_3

IOCON_SWDIO_PIO1_3

IOCON_PIO1_4

IOCON_PIO1_11

IOCON_PIO3_2

IOCON_PIO1_5

R/W

R/W

R/W

R/W

R/W

R/W

R/W

R/W

R/W

R/W

R/W

0x078

0x07C

0x080

0x084

0x088

0x08C

0x090

0x094

0x098

0x09C

0x0A0

I/O configuration for pin PIO2_11/SCK0

I/O configuration for pin

R/PIO0_11/AD0/CT32B0_MAT3

I/O configuration for pin

R/PIO1_0/AD1/CT32B1_CAP0

I/O configuration for pin

R/PIO1_1/AD2/CT32B1_MAT0

I/O configuration for pin

R/PIO1_2/AD3/CT32B1_MAT1

I/O configuration for pin PIO3_0/DTR

I/O configuration for pin PIO3_1/DSR

I/O configuration for pin

PIO2_3/RI/MOSI1

I/O configuration for pin

SWDIO/PIO1_3/AD4/CT32B1_MAT2

I/O configuration for pin

PIO1_4/AD5/CT32B1_MAT3

I/O configuration for pin PIO1_11/AD7

I/O configuration for pin PIO3_2/DCD

I/O configuration for pin

PIO1_5/RTS/CT32B0_CAP0

Reset value

Reference

0x00

0xD0

Table 69

Table 70

0xD0

0xD0

0xD0

0xD0

0xD0

0xD0

0xD0

0xD0

0xD0

0xD0

0xD0

0xD0

0xD0

0xD0

0xD0

0xD0

0xD0

0xD0

0xD0

0xD0

0xD0

0xD0

0xD0

0xD0

0xD0

0xD0

Table 71

Table 72

Table 73

Table 74

Table 75

Table 76

Table 77

Table 78

Table 79

Table 80

Table 81

Table 82

Table 83

Table 84

Table 85

Table 86

Table 87

Table 88

Table 89

Table 90

Table 91

Table 92

Table 93

Table 94

Table 95

Table 96

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PIO0_0

PIO0_1

PIO0_2

PIO0_3

PIO0_4

PIO0_5

PIO0_6

PIO0_7

PIO0_8

PIO0_9

PIO0_10

PIO0_11

PIO1_0

PIO1_1

PIO1_2

PIO1_3

PIO1_4

PIO1_5

PIO1_6

PIO1_7

PIO1_8

PIO1_9

PIO1_10

PIO1_11

PIO2_0

PIO2_1

Table 56.

Name

Register overview: I/O configuration (base address 0x4004 4000)

Access Address offset

Description

IOCON_PIO1_6 R/W 0x0A4

IOCON_PIO1_7 R/W 0x0A8

I/O configuration for pin

PIO1_6/RXD/CT32B0_MAT0

I/O configuration for pin

PIO1_7/TXD/CT32B0_MAT1

IOCON_PIO3_3

IOCON_SCK_LOC

IOCON_DSR_LOC

IOCON_DCD_LOC

IOCON_RI_LOC

R/W

R/W

R/W

R/W

R/W

0x0AC

0x0B0

0x0B4

0x0B8

0x0BC

I/O configuration for pin PIO3_3/RI

SCK pin location select register

DSR pin location select register

DCD pin location select register

RI pin location register

Table 57.

Port pin

I/O configuration registers ordered by port number

Register name LPC1112 LPC1111/

12/13/14

IOCON_RESET_PIO0_0

IOCON_PIO0_1

IOCON_PIO0_2

IOCON_PIO0_3

IOCON_PIO0_4

IOCON_PIO0_5

IOCON_PIO0_6

IOCON_PIO0_7

IOCON_PIO0_8

IOCON_PIO0_9

IOCON_SWCLK_PIO0_10

IOCON_R_PIO0_11

IOCON_R_PIO1_0

IOCON_R_PIO1_1

IOCON_R_PIO1_2

IOCON_SWDIO_PIO1_3

IOCON_PIO1_4

IOCON_PIO1_5

IOCON_PIO1_6

IOCON_PIO1_7

IOCON_PIO1_8

IOCON_PIO1_9

IOCON_PIO1_10

IOCON_PIO1_11

IOCON_PIO2_0

IOCON_PIO2_1

HVQFN24

yes yes yes no yes yes yes yes yes yes yes yes yes yes yes yes yes no yes yes yes no no no no no

HVQFN33

yes yes yes yes yes yes yes yes yes yes yes yes yes yes yes yes yes yes yes yes yes yes yes yes yes no

Reset value

0xD0

0xD0

0xD0

0x00

0x00

0x00

0x00

Reference

Table 97

Table 98

Table 99

Table 100

Table 101

Table 102

Table 103

yes yes yes yes yes yes yes yes yes yes yes yes yes yes yes yes yes yes yes yes

LQFP48

yes yes yes yes yes yes

LPC1113/

14

yes yes yes yes yes yes yes yes yes yes yes yes yes yes yes yes yes yes yes yes yes yes yes yes

/

LPC11C12

C14

LQFP48

LPC11C22/

C24

LQFP48

yes yes yes yes yes yes yes yes yes yes yes yes yes yes yes yes yes yes yes yes yes no yes yes yes yes yes yes

Reference

Table 60

Table 58

Table 63

Table 67

Table 68

Table 69

Table 75

Table 76

Table 80

Table 81

Table 82

Table 85

Table 86

Table 87

Table 88

Table 92

Table 93

Table 96

Table 97

Table 98

Table 62

Table 70

Table 83

Table 94

Table 59

Table 66

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Chapter 7: LPC1100/LPC1100C/LPC1100L series: I/O configuration

-

-

-

PIO2_2

PIO2_3

PIO2_4

PIO2_5

PIO2_6

PIO2_7

PIO2_8

PIO2_9

PIO2_10

PIO2_11

PIO3_0

PIO3_1

-

PIO3_2

PIO3_3

PIO3_4

PIO3_5

Table 57.

Port pin

I/O configuration registers ordered by port number

Register name

IOCON_PIO2_2

IOCON_PIO2_3

IOCON_PIO2_4

IOCON_PIO2_5

IOCON_PIO2_6

IOCON_PIO2_7

IOCON_PIO2_8

IOCON_PIO2_9

IOCON_PIO2_10

IOCON_PIO2_11

IOCON_PIO3_0

IOCON_PIO3_1

IOCON_PIO3_2

IOCON_PIO3_3

IOCON_PIO3_4

IOCON_PIO3_5

IOCON_SCK_LOC

IOCON_DSR_LOC

IOCON_DCD_LOC

IOCON_RI_LOC

LPC1112

HVQFN24

no no no no no no no no no no no no no no no no no no no no

LPC1111/

12/13/14

no no yes no no no no no no no no no

HVQFN33

no no yes yes yes yes yes (SCKLOC

= 01 reserved) yes no yes no no yes yes yes yes yes yes yes yes yes yes

LQFP48

yes yes yes yes yes yes

LPC1113/

14

yes yes yes yes yes yes yes yes yes yes no no yes

/

LPC11C12

C14

LQFP48

LPC11C22/

C24

LQFP48

yes yes yes yes yes yes no no yes yes yes no yes yes yes yes yes yes no no yes

Reference

yes yes yes yes yes yes

Table 79

Table 91

Table 72

Table 73

Table 58

Table 64

Table 65

Table 77

Table 78

Table 84

Table 89

Table 90

Table 95

Table 99

Table 71

Table 74

Table 100

Table 101

Table 102

Table 103

7.4.1 IOCON_PIO2_6

Table 58.

Bit

IOCON_PIO2_6 register (IOCON_PIO2_6, address 0x4004 4000) bit description

Symbol Value Description Reset value

2:0 FUNC Selects pin function. All other values are reserved.

000

4:3 MODE

0x0 Selects function PIO2_6.

Selects function mode (on-chip pull-up/pull-down resistor control).

Inactive (no pull-down/pull-up resistor enabled).

10

5 HYS

0x0

0x1

0x2

0x3

Pull-down resistor enabled.

Pull-up resistor enabled.

Repeater mode.

Hysteresis.

0

9:6 -

0

1

Disable.

Enable.

Reserved 0011

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Table 58.

Bit

IOCON_PIO2_6 register (IOCON_PIO2_6, address 0x4004 4000) bit description

Symbol Value Description Reset value

10 OD 0

31:11 -

0

1

Selects pseudo open-drain mode. See

Section 7.1

for part specific details.

Standard GPIO output

Open-drain output

Reserved -

7.4.2 IOCON_PIO2_0

Table 59.

Bit

IOCON_PIO2_0 register (IOCON_PIO2_0, address 0x4004 4008) bit description

Symbol Value Description Reset value

2:0 FUNC 000

4:3 MODE

0x0

0x1

0x2

Selects pin function. All other values are reserved.

Selects function PIO2_0.

Select function DTR.

Select function SSEL1.

Selects function mode (on-chip pull-up/pull-down resistor control).

10

5

9:6

10

-

HYS

OD

-

0x0

0x1

0x2

0x3

0

1

Inactive (no pull-down/pull-up resistor enabled).

Pull-down resistor enabled.

Pull-up resistor enabled.

Repeater mode.

Hysteresis.

Disable.

Enable.

Reserved

Selects pseudo open-drain mode. See

Section 7.1

for part specific details.

0

0011

0

31:11 -

0

1

Standard GPIO output

Open-drain output

Reserved -

7.4.3 IOCON_PIO_RESET_PIO0_0

Table 60.

Bit

IOCON_RESET_PIO0_0 register (IOCON_RESET_PIO0_0, address 0x4004 400C) bit description

Symbol Value Description Reset value

2:0 FUNC Selects pin function. All other values are reserved.

000

0x0

0x1

Selects function RESET.

Selects function PIO0_0.

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Table 60.

Bit

IOCON_RESET_PIO0_0 register (IOCON_RESET_PIO0_0, address 0x4004 400C) bit description

Symbol Value Description Reset value

4:3 MODE Selects function mode (on-chip pull-up/pull-down resistor control).

Inactive (no pull-down/pull-up resistor enabled).

10

5 HYS

0x0

0x1

0x2

0x3

Pull-down resistor enabled.

Pull-up resistor enabled.

Repeater mode.

Hysteresis.

0

9:6

10

31:11

-

-

OD

-

-

0

1

0

1

Disable.

Enable.

Reserved

Selects pseudo open-drain mode. See

Section 7.1

for part specific details.

Standard GPIO output

Open-drain output

Reserved -

0011

0

7.4.4 IOCON_PIO0_1

Table 61.

Bit

IOCON_PIO0_1 register (IOCON_PIO0_1, address 0x4004 4010) bit description

Symbol Value Description Reset value

2:0 FUNC Selects pin function. All other values are reserved.

000

4:3 MODE

0x0

0x1

0x2

Selects function PIO0_1.

Selects function CLKOUT.

Selects function CT32B0_MAT2.

Selects function mode (on-chip pull-up/pull-down resistor control).

Inactive (no pull-down/pull-up resistor enabled).

10

5 HYS

0x0

0x1

0x2

0x3

Pull-down resistor enabled.

Pull-up resistor enabled.

Repeater mode.

Hysteresis.

0

9:6

10

31:11

-

-

OD

-

-

0

1

0

1

Disable.

Enable.

Reserved

Selects pseudo open-drain mode. See

Section 7.1

for part specific details.

Standard GPIO output

Open-drain output

Reserved -

0011

0

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7.4.5 IOCON_PIO1_8

Table 62.

Bit

IOCON_PIO1_8 register (IOCON_PIO1_8, address 0x4004 4014) bit description

Symbol Value Description Reset value

2:0 FUNC Selects pin function. All other values are reserved.

000

4:3 MODE

0x0

0x1

Selects function PIO1_8.

Selects function CT16B1_CAP0.

Selects function mode (on-chip pull-up/pull-down resistor control).

10

5

9:6

10

-

HYS

OD

-

0x0

0x1

0x2

0x3

0

1

Inactive (no pull-down/pull-up resistor enabled).

Pull-down resistor enabled.

Pull-up resistor enabled.

Repeater mode.

Hysteresis.

Disable.

Enable.

Reserved

Selects pseudo open-drain mode. See

Section 7.1

for part specific details.

0

0011

0

31:11 -

0

1

Standard GPIO output

Open-drain output

Reserved -

7.4.6 IOCON_PIO0_2

Table 63.

Bit

IOCON_PIO0_2 register (IOCON_PIO0_2, address 0x4004 401C) bit description

Symbol Value Description Reset value

2:0 FUNC 000

4:3 MODE

0x0

0x1

0x2

Selects pin function. All other values are reserved.

Selects function PIO0_2.

Selects function SSEL0.

Selects function CT16B0_CAP0.

Selects function mode (on-chip pull-up/pull-down resistor control).

10

5

9:6 -

HYS

-

0x0

0x1

0x2

0x3

0

1

Inactive (no pull-down/pull-up resistor enabled).

Pull-down resistor enabled.

Pull-up resistor enabled.

Repeater mode.

Hysteresis.

Disable.

Enable.

Reserved

0

0011

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Chapter 7: LPC1100/LPC1100C/LPC1100L series: I/O configuration

Table 63.

Bit

IOCON_PIO0_2 register (IOCON_PIO0_2, address 0x4004 401C) bit description

Symbol Value Description Reset value

10 OD 0

31:11 -

0

1

Selects pseudo open-drain mode. See

Section 7.1

for part specific details.

Standard GPIO output

Open-drain output

Reserved -

7.4.7 IOCON_PIO2_7

Table 64.

Bit

IOCON_PIO2_7 register (IOCON_PIO2_7, address 0x4004 4020) bit description

Symbol Value Description Reset value

2:0 FUNC 000

4:3 MODE

0x0

Selects pin function. All other values are reserved.

Selects function PIO2_7.

Selects function mode (on-chip pull-up/pull-down resistor control).

10

5

9:6

10

-

HYS

OD

-

0x0

0x1

0x2

0x3

0

1

Inactive (no pull-down/pull-up resistor enabled).

Pull-down resistor enabled.

Pull-up resistor enabled.

Repeater mode.

Hysteresis.

Disable.

Enable.

Reserved

Selects pseudo open-drain mode. See

Section 7.1

for part specific details.

0

0011

0

31:11 -

0

1

Standard GPIO output

Open-drain output

Reserved -

7.4.8 IOCON_PIO2_8

Table 65.

Bit

IOCON_PIO2_8 register (IOCON_PIO2_8, address 0x4004 4024) bit description

Symbol Value Description Reset value

2:0 FUNC 000

4:3 MODE

0x0

Selects pin function. All other values are reserved.

Selects function PIO2_8.

Selects function mode (on-chip pull-up/pull-down resistor control).

10

0x0

0x1

0x2

0x3

Inactive (no pull-down/pull-up resistor enabled).

Pull-down resistor enabled.

Pull-up resistor enabled.

Repeater mode.

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Table 65.

Bit

IOCON_PIO2_8 register (IOCON_PIO2_8, address 0x4004 4024) bit description

Symbol Value Description Reset value

5 HYS 0

9:6

10

-

OD

-

0

1

Hysteresis.

Disable.

Enable.

Reserved

Selects pseudo open-drain mode. See

Section 7.1

for part specific details.

0011

0

31:11 -

0

1

Standard GPIO output

Open-drain output

Reserved -

7.4.9 IOCON_PIO2_1

Table 66.

Bit

IOCON_PIO2_1 register (IOCON_PIO2_1, address 0x4004 4028) bit description

Symbol Value Description Reset value

2:0 FUNC 000

4:3 MODE

0x0

0x1

0x2

Selects pin function. All other values are reserved.

Selects function PIO2_1.

Select function DSR.

Select function SCK1.

Selects function mode (on-chip pull-up/pull-down resistor control).

10

5

9:6

10

-

HYS

OD

-

0x0

0x1

0x2

0x3

0

1

Inactive (no pull-down/pull-up resistor enabled).

Pull-down resistor enabled.

Pull-up resistor enabled.

Repeater mode.

Hysteresis.

Disable.

Enable.

Reserved

Selects pseudo open-drain mode. See

Section 7.1

for part specific details.

0

0011

0

31:11 -

0

1

Standard GPIO output

Open-drain output

Reserved -

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Chapter 7: LPC1100/LPC1100C/LPC1100L series: I/O configuration

7.4.10 IOCON_PIO0_3

Table 67.

Bit

IOCON_PIO0_3 register (IOCON_PIO0_3, address 0x4004 402C) bit description

Symbol Value Description Reset value

2:0 FUNC Selects pin function. All other values are reserved.

000

4:3 MODE

0x0 Selects function PIO0_3.

Selects function mode (on-chip pull-up/pull-down resistor control).

Inactive (no pull-down/pull-up resistor enabled).

10

5 HYS

0x0

0x1

0x2

0x3

Pull-down resistor enabled.

Pull-up resistor enabled.

Repeater mode.

Hysteresis.

0

9:6

10

31:11

-

-

OD

-

-

0

1

0

1

Disable.

Enable.

Reserved

Selects pseudo open-drain mode.

Standard GPIO output

Open-drain output

Reserved -

0011

0

7.4.11 IOCON_PIO0_4

Table 68.

Bit

IOCON_PIO0_4 register (IOCON_PIO0_4, address 0x4004 4030) bit description

Symbol Value Description Reset value

2:0 FUNC

7:3

9:8 I2CMODE

-

0x0

0x1

Selects pin function. All other values are reserved.

Selects function PIO0_4 (open-drain pin).

Selects I2C function SCL (open-drain pin).

Reserved.

000

00000

Selects I2C mode. Select Standard mode (I2CMODE = 00, default) or Standard I/O functionality (I2CMODE = 01) if the pin function is GPIO (FUNC = 000).

00

Standard mode/ Fast-mode I2C.

31:10 -

0x0

0x1

0x2

0x3

Standard I/O functionality

Fast-mode Plus I2C

Reserved.

Reserved.

-

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Chapter 7: LPC1100/LPC1100C/LPC1100L series: I/O configuration

7.4.12 IOCON_PIO0_5

Table 69.

Bit

IOCON_PIO0_5 register (IOCON_PIO0_5, address 0x4004 4034) bit description

Symbol Value Description Reset value

2:0 FUNC Selects pin function. All other values are reserved.

000

7:3

9:8 I2CMODE

-

0x0

0x1

Selects function PIO0_5 (open-drain pin).

Selects I2C function SDA (open-drain pin).

Reserved.

Selects I2C mode. Select Standard mode (I2CMODE = 00, default) or Standard I/O functionality (I2CMODE = 01) if the pin function is GPIO (FUNC = 000).

00000

00

31:10 -

0x0

0x1

0x2

0x3

Standard mode/ Fast-mode I2C.

Standard I/O functionality

Fast-mode Plus I2C

Reserved.

Reserved.

-

7.4.13 IOCON_PIO1_9

Remark:

See

Section 7.1

for part specific details.

Table 70.

Bit

IOCON_PIO1_9 register (IOCON_PIO1_9, address 0x4004 4038) bit description

Symbol Value Description Reset value

2:0 FUNC 000

4:3 MODE

0x0

0x1

Selects pin function. All other values are reserved.

Selects function PIO1_9.

Selects function CT16B1_MAT0.

Selects function mode (on-chip pull-up/pull-down resistor control).

Inactive (no pull-down/pull-up resistor enabled).

10

5 HYS

0x0

0x1

0x2

0x3

Pull-down resistor enabled.

Pull-up resistor enabled.

Repeater mode.

Hysteresis.

0

9:6

10

31:11

-

-

OD

-

-

0

1

0

1

Disable.

Enable.

Reserved

Selects pseudo open-drain mode. See

Section 7.1

for part specific details.

Standard GPIO output

Open-drain output

Reserved -

0011

0

UM10398

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7.4.14 IOCON_PIO3_4

Remark:

See

Section 7.1

for part specific details.

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UM10398

User manual

Table 71.

Bit

IOCON_PIO3_4 register (IOCON_PIO3_4, address 0x4004 403C) bit description

Symbol Value Description Reset value

2:0 FUNC 000

4:3 MODE

0x0

Selects pin function. All other values are reserved.

Selects function PIO3_4.

Selects function mode (on-chip pull-up/pull-down resistor control).

10

5

9:6

10

-

HYS

OD

-

0x0

0x1

0x2

0x3

0

1

Inactive (no pull-down/pull-up resistor enabled).

Pull-down resistor enabled.

Pull-up resistor enabled.

Repeater mode.

Hysteresis.

Disable.

Enable.

Reserved

Selects pseudo open-drain mode. See

Section 7.1

for part specific details.

0

0011

0

31:11 -

0

1

Standard GPIO output

Open-drain output

Reserved -

7.4.15 IOCON_PIO2_4

Remark:

See

Section 7.1

for part specific details.

Table 72.

Bit

IOCON_PIO2_4 register (IOCON_PIO2_4, address 0x4004 4040) bit description

Symbol Value Description Reset value

2:0 FUNC 000

4:3 MODE

0x0

Selects pin function. All other values are reserved.

Selects function PIO2_4.

Selects function mode (on-chip pull-up/pull-down resistor control).

10

5

9:6

10

-

HYS

OD

-

0x0

0x1

0x2

0x3

0

1

Inactive (no pull-down/pull-up resistor enabled).

Pull-down resistor enabled.

Pull-up resistor enabled.

Repeater mode.

Hysteresis.

Disable.

Enable.

Reserved

Selects pseudo open-drain mode. See

Section 7.1

for part specific details.

0

0011

0

31:11 -

0

1

Standard GPIO output

Open-drain output

Reserved -

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Chapter 7: LPC1100/LPC1100C/LPC1100L series: I/O configuration

7.4.16 IOCON_PIO2_5

Remark:

See

Section 7.1

for part specific details.

Table 73.

Bit

IOCON_PIO2_5 register (IOCON_PIO2_5, address 0x4004 4044) bit description

Symbol Value Description Reset value

2:0 FUNC Selects pin function. All other values are reserved.

000

4:3 MODE

0x0 Selects function PIO2_5.

Selects function mode (on-chip pull-up/pull-down resistor control).

Inactive (no pull-down/pull-up resistor enabled).

10

5 HYS

0x0

0x1

0x2

0x3

Pull-down resistor enabled.

Pull-up resistor enabled.

Repeater mode.

Hysteresis.

0

9:6

10

31:11

-

-

OD

-

-

0

1

0

1

Disable.

Enable.

Reserved

Selects pseudo open-drain mode.

Standard GPIO output

Open-drain output

Reserved -

0011

0

7.4.17 IOCON_PIO3_5

Remark:

See

Section 7.1

for part specific details.

Table 74.

Bit

IOCON_PIO3_5 register (IOCON_PIO3_5, address 0x4004 4048) bit description

Symbol Value Description Reset value

2:0 FUNC Selects pin function. All other values are reserved.

000

4:3 MODE

0x0 Selects function PIO3_5.

Selects function mode (on-chip pull-up/pull-down resistor control).

Inactive (no pull-down/pull-up resistor enabled).

10

5 HYS

0x0

0x1

0x2

0x3

Pull-down resistor enabled.

Pull-up resistor enabled.

Repeater mode.

Hysteresis.

0

9:6 -

0

1

Disable.

Enable.

Reserved 0011

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Chapter 7: LPC1100/LPC1100C/LPC1100L series: I/O configuration

Table 74.

Bit

IOCON_PIO3_5 register (IOCON_PIO3_5, address 0x4004 4048) bit description

Symbol Value Description Reset value

10 OD 0

31:11 -

0

1

Selects pseudo open-drain mode. See

Section 7.1

for part specific details.

Standard GPIO output

Open-drain output

Reserved -

7.4.18 IOCON_PIO0_6

Table 75.

Bit

IOCON_PIO0_6 register (IOCON_PIO0_6, address 0x4004 404C) bit description

Symbol Value Description Reset value

2:0 FUNC 000

4:3 MODE

0x0

0x1

0x2

Selects pin function. All other values are reserved.

Selects function PIO0_6.

Reserved.

Selects function SCK0 (only if pin PIO0_6/SCK0 selected in

Table 100 ).

Selects function mode (on-chip pull-up/pull-down resistor control).

Inactive (no pull-down/pull-up resistor enabled).

10

5 HYS

0x0

0x1

0x2

0x3

Pull-down resistor enabled.

Pull-up resistor enabled.

Repeater mode.

Hysteresis.

0

9:6

10

31:11

-

-

OD

-

-

0

1

0

1

Disable.

Enable.

Reserved

Selects pseudo open-drain mode. See

Section 7.1

for part specific details.

Standard GPIO output

Open-drain output

Reserved -

0011

0

7.4.19 IOCON_PIO0_7

Table 76.

Bit

IOCON_PIO0_7 register (IOCON_PIO0_7, address 0x4004 4050) bit description

Symbol Value Description Reset value

2:0 FUNC Selects pin function. All other values are reserved.

000

0x0

0x1

Selects function PIO0_7.

Select function CTS.

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Chapter 7: LPC1100/LPC1100C/LPC1100L series: I/O configuration

Table 76.

Bit

IOCON_PIO0_7 register (IOCON_PIO0_7, address 0x4004 4050) bit description

Symbol Value Description Reset value

4:3 MODE 10

5 HYS

0x0

0x1

0x2

0x3

Selects function mode (on-chip pull-up/pull-down resistor control).

Inactive (no pull-down/pull-up resistor enabled).

Pull-down resistor enabled.

Pull-up resistor enabled.

Repeater mode.

Hysteresis.

Disable.

0

9:6

10

-

OD

0

-

1 Enable.

Reserved

Selects pseudo open-drain mode. See specific details.

Section 7.1

for part

0011

0

31:11 -

0

1

Standard GPIO output

Open-drain output

Reserved -

7.4.20 IOCON_PIO2_9

Remark:

See

Section 7.1

for part specific details.

Table 77.

Bit

IOCON_PIO2_9 register (IOCON_PIO2_9, address 0x4004 4054) bit description

Symbol Value Description Reset value

2:0 FUNC 000

4:3 MODE

0x0

Selects pin function. All other values are reserved.

Selects function PIO2_9.

Selects function mode (on-chip pull-up/pull-down resistor control).

10

5

9:6

10

-

HYS

OD

-

0x0

0x1

0x2

0x3

0

1

Inactive (no pull-down/pull-up resistor enabled).

Pull-down resistor enabled.

Pull-up resistor enabled.

Repeater mode.

Hysteresis.

Disable.

Enable.

Reserved

Selects pseudo open-drain mode. See

Section 7.1

for part specific details.

0

0011

0

31:11 -

0

1

Standard GPIO output

Open-drain output

Reserved -

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Chapter 7: LPC1100/LPC1100C/LPC1100L series: I/O configuration

7.4.21 IOCON_PIO2_10

Table 78.

Bit

IOCON_PIO2_10 register (IOCON_PIO2_10, address 0x4004 4058) bit description

Symbol Value Description Reset value

2:0 FUNC Selects pin function. All other values are reserved.

000

4:3 MODE

0x0 Selects function PIO2_10.

Selects function mode (on-chip pull-up/pull-down resistor control).

Inactive (no pull-down/pull-up resistor enabled).

10

5 HYS

0x0

0x1

0x2

0x3

Pull-down resistor enabled.

Pull-up resistor enabled.

Repeater mode.

Hysteresis.

0

9:6

10

31:11

-

-

OD

-

-

0

1

0

1

Disable.

Enable.

Reserved

Selects pseudo open-drain mode. See

Section 7.1

for part specific details.

Standard GPIO output

Open-drain output

Reserved -

0011

0

7.4.22 IOCON_PIO2_2

Table 79.

Bit

IOCON_PIO2_2 register (IOCON_PIO2_2, address 0x4004 405C) bit description

Symbol Value Description Reset value

2:0 FUNC Selects pin function. All other values are reserved.

000

4:3 MODE

0x0

0x1

0x2

Selects function PIO2_2.

Select function DCD.

Select function MISO1.

Selects function mode (on-chip pull-up/pull-down resistor control).

Inactive (no pull-down/pull-up resistor enabled).

10

5 HYS

0x0

0x1

0x2

0x3

Pull-down resistor enabled.

Pull-up resistor enabled.

Repeater mode.

Hysteresis.

0

9:6 -

0

1

Disable.

Enable.

Reserved 0011

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Chapter 7: LPC1100/LPC1100C/LPC1100L series: I/O configuration

Table 79.

Bit

IOCON_PIO2_2 register (IOCON_PIO2_2, address 0x4004 405C) bit description

Symbol Value Description Reset value

10 OD 0

31:11 -

0

1

Selects pseudo open-drain mode.

Standard GPIO output

Open-drain output

Reserved -

7.4.23 IOCON_PIO0_8

Table 80.

Bit

IOCON_PIO0_8 register (IOCON_PIO0_8, address 0x4004 4060) bit description

Symbol Value Description Reset value

2:0 FUNC Selects pin function. All other values are reserved.

000

4:3 MODE

0x0

0x1

0x2

Selects function PIO0_8.

Selects function MISO0.

Selects function CT16B0_MAT0.

Selects function mode (on-chip pull-up/pull-down resistor control).

Inactive (no pull-down/pull-up resistor enabled).

10

5 HYS

0x0

0x1

0x2

0x3

Pull-down resistor enabled.

Pull-up resistor enabled.

Repeater mode.

Hysteresis.

0

9:6

10

31:11

-

-

OD

-

-

0

1

0

1

Disable.

Enable.

Reserved

Selects pseudo open-drain mode. See

Section 7.1

for part specific details.

Standard GPIO output

Open-drain output

Reserved -

0011

0

7.4.24 IOCON_PIO0_9

Table 81.

Bit

IOCON_PIO0_9 register (IOCON_PIO0_9, address 0x4004 4064) bit description

Symbol Value Description Reset value

2:0 FUNC Selects pin function. All other values are reserved.

000

0x0

0x1

0x2

Selects function PIO0_9.

Selects function MOSI0.

Selects function CT16B0_MAT1.

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Chapter 7: LPC1100/LPC1100C/LPC1100L series: I/O configuration

Table 81.

Bit

IOCON_PIO0_9 register (IOCON_PIO0_9, address 0x4004 4064) bit description

Symbol Value Description Reset value

4:3 MODE 10

5 HYS

0x0

0x1

0x2

0x3

Selects function mode (on-chip pull-up/pull-down resistor control).

Inactive (no pull-down/pull-up resistor enabled).

Pull-down resistor enabled.

Pull-up resistor enabled.

Repeater mode.

Hysteresis.

Disable.

0

9:6

10

-

OD

0

-

1 Enable.

Reserved

Selects pseudo open-drain mode. See specific details.

Section 7.1

for part

0011

0

31:11 -

0

1

Standard GPIO output

Open-drain output

Reserved -

7.4.25 IOCON_SWCLK_PIO0_10

Table 82.

Bit

IOCON_SWCLK_PIO0_10 register (IOCON_SWCLK_PIO0_10, address 0x4004

4068) bit description

Symbol Value Description Reset value

2:0 FUNC Selects pin function. All other values are reserved.

000

0x0

0x1

0x2

Selects function SWCLK.

Selects function PIO0_10.

Selects function SCK0 (only if pin

SWCLK/PIO0_10/SCK0/CT16B0_MAT2 selected in

4:3

5

9:6 -

MODE

HYS

-

0x3

0x0

0x1

0x2

0x3

0

1

Table 100

).

Selects function CT16B0_MAT2.

Selects function mode (on-chip pull-up/pull-down resistor control).

Inactive (no pull-down/pull-up resistor enabled).

Pull-down resistor enabled.

Pull-up resistor enabled.

Repeater mode.

Hysteresis.

Disable.

Enable.

Reserved

10

0

0011

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Chapter 7: LPC1100/LPC1100C/LPC1100L series: I/O configuration

Table 82.

Bit

IOCON_SWCLK_PIO0_10 register (IOCON_SWCLK_PIO0_10, address 0x4004

4068) bit description

…continued

Symbol Value Description Reset value

10 OD 0

31:11 -

0

1

Selects pseudo open-drain mode.

Standard GPIO output

Open-drain output

Reserved -

7.4.26 IOCON_PIO1_10

Table 83.

Bit

IOCON_PIO1_10 register (IOCON_PIO1_10, address 0x4004 406C) bit description

Symbol Value Description Reset value

2:0 FUNC 000

4:3 MODE

0x0

0x1

0x2

Selects pin function. All other values are reserved.

Selects function PIO1_10.

Selects function AD6.

Selects function CT16B1_MAT1.

Selects function mode (on-chip pull-up/pull-down resistor control).

10

5

6

7

9:8

10

31:11

-

-

HYS

0

-

ADMODE

-

1

0

-

1

OD

-

0x0

0x1

0x2

0x3

0

1

Inactive (no pull-down/pull-up resistor enabled).

Pull-down resistor enabled.

Pull-up resistor enabled.

Repeater mode.

Hysteresis.

Disable.

Enable.

Reserved

Selects Analog/Digital mode

Analog input mode

Digital functional mode

Reserved

Selects pseudo open-drain mode. See specific details.

Standard GPIO output

Open-drain output

Reserved

Section 7.1

for part

-

0

1

1

00

0

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Chapter 7: LPC1100/LPC1100C/LPC1100L series: I/O configuration

7.4.27 IOCON_PIO2_11

Table 84.

Bit

IOCON_PIO2_11 register (IOCON_PIO2_11, address 0x4004 4070) bit description

Symbol Value Description Reset value

2:0 FUNC Selects pin function. All other values are reserved.

000

4:3 MODE

0x0

0x1

Selects function PIO2_11.

Select function SCK0 (only if pin PIO2_11/SCK0 selected in

Table 100 ).

Selects function mode (on-chip pull-up/pull-down resistor control).

Inactive (no pull-down/pull-up resistor enabled).

10

5 HYS

0x0

0x1

0x2

0x3

Pull-down resistor enabled.

Pull-up resistor enabled.

Repeater mode.

Hysteresis.

0

9:6

10

31:11

-

-

OD

-

-

0

1

0

1

Disable.

Enable.

Reserved

Selects pseudo open-drain mode. See

Section 7.1

for part specific details.

Standard GPIO output

Open-drain output

Reserved -

0011

0

UM10398

User manual

7.4.28 IOCON_R_PIO0_11

Table 85.

Bit

IOCON_R_PIO0_11 register (IOCON_R_PIO0_11, address 0x4004 4074) bit description

Symbol Value Description Reset value

2:0 FUNC

0x0

Selects pin function. All other values are reserved.

Selects function R. This function is reserved. Select one of the alternate functions below.

Selects function PIO0_11.

000

4:3 MODE

0x1

0x2

0x3

Selects function AD0.

Selects function CT32B0_MAT3.

Selects function mode (on-chip pull-up/pull-down resistor control).

10

5 HYS

0x0

0x1

0x2

0x3

0

1

Inactive (no pull-down/pull-up resistor enabled).

Pull-down resistor enabled.

Pull-up resistor enabled.

Repeater mode.

Hysteresis.

Disable.

Enable.

0

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User manual

Table 85.

Bit

IOCON_R_PIO0_11 register (IOCON_R_PIO0_11, address 0x4004 4074) bit description

…continued

Symbol Value Description Reset value

6

7

-

ADMODE

-

0

Reserved

Selects Analog/Digital mode

Analog input mode

1

1

9:8

10

31:11 -

-

OD

-

-

1

0

1

Digital functional mode

Reserved

Selects pseudo open-drain mode.

Standard GPIO output

Open-drain output

Reserved -

00

0

7.4.29 IOCON_R_PIO1_0

Table 86.

Bit

IOCON_R_PIO1_0 register (IOCON_R_PIO1_0, address 0x4004 4078) bit description

Symbol Value Description

2:0 FUNC

Reset value

000

0x0

Selects pin function. All other values are reserved.

Selects function R. This function is reserved. Select one of the alternate functions below.

Selects function PIO1_0.

4:3 MODE

0x1

0x2

0x3

Selects function AD1.

Selects function CT32B1_CAP0.

Selects function mode (on-chip pull-up/pull-down resistor control).

10

5

6

7

9:8

10

31:11

-

-

HYS

0x0

0x1

0x2

0x3

0

-

ADMODE

-

1

0

-

1

OD

-

0

1

Inactive (no pull-down/pull-up resistor enabled).

Pull-down resistor enabled.

Pull-up resistor enabled.

Repeater mode.

Hysteresis.

Disable.

Enable.

Reserved

Selects Analog/Digital mode

Analog input mode

Digital functional mode

Reserved

Selects pseudo open-drain mode. See

Section 7.1

for part specific details.

Standard GPIO output

Open-drain output

Reserved -

0

1

1

00

0

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7.4.30 IOCON_R_PIO1_1

Table 87.

Bit

IOCON_R_PIO1_1 register (IOCON_R_PIO1_1, address 0x4004 407C) bit description

Symbol Value Description Reset value

2:0 FUNC 000

0x0

Selects pin function. All other values are reserved.

Selects function R. This function is reserved. Select one of the alternate functions below.

Selects function PIO1_1.

4:3 MODE

0x1

0x2

0x3

Selects function AD2.

Selects function CT32B1_MAT0.

Selects function mode (on-chip pull-up/pull-down resistor control).

10

5

6

7

9:8

10

31:11

-

-

HYS

0

-

ADMODE

-

1

0

-

1

OD

-

0x0

0x1

0x2

0x3

0

1

Inactive (no pull-down/pull-up resistor enabled).

Pull-down resistor enabled.

Pull-up resistor enabled.

Repeater mode.

Hysteresis.

Disable.

Enable.

Reserved

Selects Analog/Digital mode

Analog input mode

Digital functional mode

Reserved

Selects pseudo open-drain mode. See specific details.

Standard GPIO output

Open-drain output

Reserved

Section 7.1

for part

-

0

1

1

00

0

7.4.31 IOCON_R_PIO1_2

Table 88.

Bit

IOCON_R_PIO1_2 register (IOCON_R_PIO1_2, address 0x4004 4080) bit description

Symbol Value Description

2:0 FUNC

Reset value

000

0x0

Selects pin function. All other values are reserved.

Selects function R. This function is reserved. Select one of the alternate functions below.

0x1

0x2

0x3

Selects function PIO1_2.

Selects function AD3.

Selects function CT32B1_MAT1.

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Table 88.

Bit

IOCON_R_PIO1_2 register (IOCON_R_PIO1_2, address 0x4004 4080) bit description

…continued

Symbol Value Description

4:3 MODE

Reset value

10 Selects function mode (on-chip pull-up/pull-down resistor control).

Inactive (no pull-down/pull-up resistor enabled).

5 HYS

0x0

0x1

0x2

0x3

Pull-down resistor enabled.

Pull-up resistor enabled.

Repeater mode.

Hysteresis.

0

6

7

9:8

10

31:11

-

-

ADMODE

-

0

1

-

0

1

OD

-

0

1

Disable.

Enable.

Reserved

Selects Analog/Digital mode

Analog input mode

Digital functional mode

Reserved

Selects pseudo open-drain mode. See

Section 7.1

for part specific details.

Standard GPIO output

Open-drain output

Reserved -

1

1

00

0

7.4.32 IOCON_PIO3_0

Table 89.

Bit

IOCON_PIO3_0 register (IOCON_PIO3_0, address 0x4004 4084) bit description

Symbol Value Description Reset value

2:0 FUNC Selects pin function. All other values are reserved.

000

4:3 MODE

0x0

0x1

Selects function PIO3_0.

Selects function DTR.

Selects function mode (on-chip pull-up/pull-down resistor control).

10

5

9:6 -

HYS

-

0x0

0x1

0x2

0x3

0

1

Inactive (no pull-down/pull-up resistor enabled).

Pull-down resistor enabled.

Pull-up resistor enabled.

Repeater mode.

Hysteresis.

Disable.

Enable.

Reserved

0

0011

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Table 89.

Bit

IOCON_PIO3_0 register (IOCON_PIO3_0, address 0x4004 4084) bit description

Symbol Value Description Reset value

10 OD 0

31:11 -

0

1

Selects pseudo open-drain mode.

Standard GPIO output

Open-drain output

Reserved -

7.4.33 IOCON_PIO3_1

Table 90.

Bit

IOCON_PIO3_1 register (IOCON_PIO3_1, address 0x4004 4088) bit description

Symbol Value Description Reset value

2:0 FUNC Selects pin function. All other values are reserved.

000

4:3 MODE

0x0

0x1

Selects function PIO3_1.

Selects function DSR.

Selects function mode (on-chip pull-up/pull-down resistor control).

10

5

9:6

10

-

HYS

OD

-

0x0

0x1

0x2

0x3

0

1

Inactive (no pull-down/pull-up resistor enabled).

Pull-down resistor enabled.

Pull-up resistor enabled.

Repeater mode.

Hysteresis.

Disable.

Enable.

Reserved

Selects pseudo open-drain mode. See

Section 7.1

for part specific details.

0

0011

0

31:11 -

0

1

Standard GPIO output

Open-drain output

Reserved -

7.4.34 IOCON_PIO2_3

Table 91.

Bit

IOCON_PIO2_3 register (IOCON_PIO2_3, address 0x4004 408C) bit description

Symbol Value Description Reset value

2:0 FUNC 000

0x0

0x1

0x2

Selects pin function. All other values are reserved.

Selects function PIO2_3.

Selects function RI.

Selects function MOSI1.

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Table 91.

Bit

IOCON_PIO2_3 register (IOCON_PIO2_3, address 0x4004 408C) bit description

Symbol Value Description Reset value

4:3 MODE 10

5 HYS

0x0

0x1

0x2

0x3

Selects function mode (on-chip pull-up/pull-down resistor control).

Inactive (no pull-down/pull-up resistor enabled).

Pull-down resistor enabled.

Pull-up resistor enabled.

Repeater mode.

Hysteresis.

Disable.

0

9:6

10

-

OD

0

-

1 Enable.

Reserved

Selects pseudo open-drain mode. See specific details.

Section 7.1

for part

0011

0

31:11 -

0

1

Standard GPIO output

Open-drain output

Reserved -

7.4.35 IOCON_SWDIO_PIO1_3

Table 92.

Bit

IOCON_SWDIO_PIO1_3 register (IOCON_SWDIO_PIO1_3, address 0x4004 4090) bit description

Symbol Value Description Reset value

2:0 FUNC Selects pin function. All other values are reserved.

000

4:3 MODE

0x0

0x1

0x2

0x3

Selects function SWDIO.

Selects function PIO1_3.

Selects function AD4.

Selects function CT32B1_MAT2.

Selects function mode (on-chip pull-up/pull-down resistor control).

10

5

6

7

9:8 -

HYS

0x0

0x1

0x2

0x3

0

-

ADMODE

-

1

0

-

1

Inactive (no pull-down/pull-up resistor enabled).

Pull-down resistor enabled.

Pull-up resistor enabled.

Repeater mode.

Hysteresis.

Disable.

Enable.

Reserved

Selects Analog/Digital mode

Analog input mode

Digital functional mode

Reserved

0

1

1

00

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Chapter 7: LPC1100/LPC1100C/LPC1100L series: I/O configuration

Table 92.

Bit

IOCON_SWDIO_PIO1_3 register (IOCON_SWDIO_PIO1_3, address 0x4004 4090) bit description

…continued

Symbol Value Description Reset value

10 OD 0

31:11 -

0

1

Selects pseudo open-drain mode.

Standard GPIO output

Open-drain output

Reserved -

7.4.36 IOCON_PIO1_4

Table 93.

Bit

IOCON_PIO1_4 register (IOCON_PIO1_4, address 0x4004 4094) bit description

Symbol Value Description Reset value

2:0 FUNC Selects pin function. This pin functions as WAKEUP pin if the

LPC111x/LPC11Cxx is in Deep power-down mode regardless of the value of FUNC. All other values are reserved.

000

Selects function PIO1_4.

4:3 MODE

0x0

0x1

0x2

Selects function AD5.

Selects function CT32B1_MAT3.

Selects function mode (on-chip pull-up/pull-down resistor control).

10

5

6

7

9:8

10

31:11

-

-

HYS

0

-

ADMODE

-

1

0

-

1

OD

-

0x0

0x1

0x2

0x3

0

1

Inactive (no pull-down/pull-up resistor enabled).

Pull-down resistor enabled.

Pull-up resistor enabled.

Repeater mode.

Hysteresis.

Disable.

Enable.

Reserved

Selects Analog/Digital mode

Analog input mode

Digital functional mode

Reserved

Selects pseudo open-drain mode. See specific details.

Standard GPIO output

Open-drain output

Reserved

Section 7.1

for part

-

0

1

1

00

0

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7.4.37 IOCON_PIO1_11

Table 94.

Bit

IOCON_PIO1_11 register (IOCON_PIO1_11, address 0x4004 4098) bit description

Symbol Value Description Reset value

2:0 FUNC Selects pin function. All other values are reserved.

000

4:3 MODE

0x0

0x1

Selects function PIO1_11.

Selects function AD7.

Selects function mode (on-chip pull-up/pull-down resistor control).

10

5

6

7

9:8

10

31:11

-

-

HYS

0x0

0x1

0x2

0x3

0

-

ADMODE

-

1

0

-

1

OD

-

0

1

Inactive (no pull-down/pull-up resistor enabled).

Pull-down resistor enabled.

Pull-up resistor enabled.

Repeater mode.

Hysteresis.

Disable.

Enable.

Reserved

Selects Analog/Digital mode

Analog input mode

Digital functional mode

Reserved

Selects pseudo open-drain mode. See

Section 7.1

for part specific details.

Standard GPIO output

Open-drain output

Reserved -

0

1

1

00

0

7.4.38 IOCON_PIO3_2

Table 95.

Bit

IOCON_PIO3_2 register (IOCON_PIO3_2, address 0x4004 409C) bit description

Symbol Value Description Reset value

2:0 FUNC 000

4:3 MODE

0x0

0x1

Selects pin function. All other values are reserved.

Selects function PIO3_2.

Selects function DCD.

Selects function mode (on-chip pull-up/pull-down resistor control).

Inactive (no pull-down/pull-up resistor enabled).

10

5 HYS

0x0

0x1

0x2

0x3

Pull-down resistor enabled.

Pull-up resistor enabled.

Repeater mode.

Hysteresis.

0

0

1

Disable.

Enable.

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Table 95.

Bit

IOCON_PIO3_2 register (IOCON_PIO3_2, address 0x4004 409C) bit description

Symbol Value Description Reset value

9:6

10

31:11 -

-

OD

-

-

0

1

Reserved

Selects pseudo open-drain mode.

Standard GPIO output

Open-drain output

Reserved -

0011

0

7.4.39 IOCON_PIO1_5

Table 96.

Bit

IOCON_PIO1_5 register (IOCON_PIO1_5, address 0x4004 40A0) bit description

Symbol Value Description Reset value

2:0 FUNC 000

4:3 MODE

0x0

0x1

0x2

Selects pin function. All other values are reserved.

Selects function PIO1_5.

Selects function RTS.

Selects function CT32B0_CAP0.

Selects function mode (on-chip pull-up/pull-down resistor control).

10

5

9:6

10

-

HYS

OD

-

0x0

0x1

0x2

0x3

0

1

Inactive (no pull-down/pull-up resistor enabled).

Pull-down resistor enabled.

Pull-up resistor enabled.

Repeater mode.

Hysteresis.

Disable.

Enable.

Reserved

Selects pseudo open-drain mode. See

Section 7.1

for part specific details.

0

0011

0

31:11 -

0

1

Standard GPIO output

Open-drain output

Reserved -

7.4.40 IOCON_PIO1_6

Table 97.

Bit

IOCON_PIO1_6 register (IOCON_PIO1_6, address 0x4004 40A4) bit description

Symbol Value Description Reset value

2:0 FUNC 000

0x0

0x1

0x2

Selects pin function. All other values are reserved.

Selects function PIO1_6.

Selects function RXD.

Selects function CT32B0_MAT0.

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Chapter 7: LPC1100/LPC1100C/LPC1100L series: I/O configuration

Table 97.

Bit

IOCON_PIO1_6 register (IOCON_PIO1_6, address 0x4004 40A4) bit description

Symbol Value Description Reset value

4:3 MODE 10

5 HYS

0x0

0x1

0x2

0x3

Selects function mode (on-chip pull-up/pull-down resistor control).

Inactive (no pull-down/pull-up resistor enabled).

Pull-down resistor enabled.

Pull-up resistor enabled.

Repeater mode.

Hysteresis.

Disable.

0

9:6

10

-

OD

0

-

1 Enable.

Reserved

Selects pseudo open-drain mode. See specific details.

Section 7.1

for part

0011

0

31:11 -

0

1

Standard GPIO output

Open-drain output

Reserved -

7.4.41 IOCON_PIO1_7

Table 98.

Bit

IOCON_PIO1_7 register (IOCON_PIO1_7, address 0x4004 40A8) bit description

Symbol Value Description Reset value

2:0 FUNC 000

4:3 MODE

0x0

0x1

0x2

Selects pin function. All other values are reserved.

Selects function PIO1_7.

Selects function TXD.

Selects function CT32B0_MAT1.

Selects function mode (on-chip pull-up/pull-down resistor control).

10

5

9:6

10

-

HYS

OD

-

0x0

0x1

0x2

0x3

0

1

Inactive (no pull-down/pull-up resistor enabled).

Pull-down resistor enabled.

Pull-up resistor enabled.

Repeater mode.

Hysteresis.

Disable.

Enable.

Reserved

Selects pseudo open-drain mode. See

Section 7.1

for part specific details.

0

0011

0

31:11 -

0

1

Standard GPIO output

Open-drain output

Reserved -

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Chapter 7: LPC1100/LPC1100C/LPC1100L series: I/O configuration

7.4.42 IOCON_PIO3_3

Table 99.

Bit

IOCON_PIO3_3 register (IOCON_PIO3_3, address 0x4004 40AC) bit description

Symbol Value Description Reset value

2:0 FUNC Selects pin function. All other values are reserved.

000

4:3 MODE

0x0

0x1

Selects function PIO3_3.

Selects function RI.

Selects function mode (on-chip pull-up/pull-down resistor control).

10

5

9:6

10

-

HYS

OD

-

0x0

0x1

0x2

0x3

0

1

Inactive (no pull-down/pull-up resistor enabled).

Pull-down resistor enabled.

Pull-up resistor enabled.

Repeater mode.

Hysteresis.

Disable.

Enable.

Reserved

Selects pseudo open-drain mode. See

Section 7.1

for part specific details.

0

0011

0

31:11 -

0

1

Standard GPIO output

Open-drain output

Reserved -

7.4.43 IOCON_SCK_LOC

Table 100. IOCON SCK location register (IOCON_SCK_LOC, address 0x4004 40B0) bit description

Bit Symbol Value Description

1:0 SCKLOC Selects pin location for SCK0 function.

Reset value

00

0x0

0x1

Selects SCK0 function in pin location

SWCLK/PIO0_10/SCK0/CT16B0_MAT2 (see Table 82

).

Selects SCK0 function in pin location PIO2_11/SCK0 (see

Table 84

.

31:2 -

0x2

0x3

Selects SCK0 function in pin location PIO0_6/SCK0 (see

Table 75

).

Reserved.

Reserved.

-

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Chapter 7: LPC1100/LPC1100C/LPC1100L series: I/O configuration

7.4.44 IOCON_DSR_LOC

Table 101. IOCON DSR location register (IOCON_DSR_LOC, address 0x4004 40B4) bit description

Bit Symbol Value Description Reset value

1:0 DSRLOC 00

0x0

0x1

0x2

Selects pin location for DSR function.

Selects DSR function in pin location PIO2_1/DSR/SCK1.

Selects DSR function in pin location PIO3_1/DSR.

Reserved.

31:2 -

0x3 Reserved.

Reserved.

-

7.4.45 IOCON_DCD_LOC

Table 102. IOCON DCD location register (IOCON_DCD_LOC, address 0x4004 40B8) bit description

Bit Symbol Value Description

1:0 DCDLOC

0x0

Selects pin location for DCD function.

Selects DCD function in pin location PIO2_2/DCD/MISO1.

Reset value

00

31:2 -

0x1

0x2

-

0x3

Selects DCD function in pin location PIO3_2/DCD.

Reserved.

Reserved.

Reserved.

-

7.4.46 IOCON_RI_LOC

Table 103. IOCON RI location register (IOCON_RI_LOC, address 0x4004 40BC) bit description

Bit Symbol Value Description

1:0 RILOC

Reset value

00

31:2 -

0x0

0x1

0x2

-

0x3

Selects pin location for RI function.

Selects RI function in pin location PIO2_3/RI/MOSI1.

Selects RI function in pin location PIO3_3/RI.

Reserved.

Reserved.

Reserved.

-

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Rev. 12.4 — 22 December 2016 User manual

8.1 How to read this chapter

Remark:

This chapter applies to parts in the following series (see

Table 1

):

LPC1100XL

The implementation of the I/O configuration registers varies for different LPC1100XL parts

and packages. Table 105

shows which IOCON registers are used on the different packages.

8.2 Features

The I/O configuration registers control the electrical characteristics of the pads. The following features are programmable:

Pin function.

Internal pull-up/pull-down resistor or bus keeper function.

Hysteresis.

Analog input or digital mode for pads hosting the ADC inputs.

I

2

C mode for pads hosting the I

2

C-bus function.

Pseudo open-drain mode for non-I2C pins.

8.3 General description

The IOCON registers control the function (GPIO or peripheral function), the input mode, and the hysteresis of all PIOn_m pins. In addition, the I

2

C-bus pins can be configured for different I

2

C-bus modes. An analog input mode can be selected for the input pins to the

ADC.

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pin configured as digital output driver pin configured as digital input

UM10398

Chapter 8: LPC1100XL series: I/O configuration (IOCONFIG)

open-drain enable output enable data output repeater mode enable pull-up enable pull-down enable

V

DD strong pull-up strong pull-down

V

DD

ESD

ESD

V

SS

V

DD weak pull-up weak pull-down

PIN data input select analog input pin configured as analog input analog input

002aah159

Fig 15. Standard I/O pin configuration

8.3.1 Pin function

The FUNC bits in the IOCON registers can be set to GPIO (FUNC = 000) or to a peripheral function. If the pins are GPIO pins, the GPIOnDIR registers determine whether

the pin is configured as an input or output (see Section 12.3.2

). For any peripheral function, the pin direction is controlled automatically depending on the pin’s functionality.

The GPIOnDIR registers have no effect for peripheral functions.

8.3.2 Pin mode

The MODE bits in the IOCON register allow the selection of on-chip pull-up or pull-down resistors for each pin or select the repeater mode.

The possible on-chip resistor configurations are pull-up enabled, pull-down enabled, or no pull-up/pull-down. The default value is pull-up enabled. If the pull-up resistor is enabled

(default), all non-I2C pins are pulled up to 3.3 V (V

DD

= 3.3 V).

The repeater mode enables the pull-up resistor if the pin is at a logic HIGH and enables the pull-down resistor if the pin is at a logic LOW. This causes the pin to retain its last known state if it is configured as an input and is not driven externally. The state retention is

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Chapter 8: LPC1100XL series: I/O configuration (IOCONFIG)

not applicable to the Deep power-down mode. Repeater mode may typically be used to prevent a pin from floating (and potentially using significant power if it floats to an indeterminate state) if it is temporarily not driven.

8.3.3 Hysteresis

The input buffer for digital functions can be configured with hysteresis or as plain buffer through the IOCON registers (see the

LPC1100XL data sheet

for details).

If the external pad supply voltage V

DD

is between 2.5 V and 3.6 V, the hysteresis buffer can be enabled or disabled. If V

DD

is below 2.5 V, the hysteresis buffer must be

disabled

to use the pin in input mode.

8.3.4 A/D-mode

In A/D-mode, the digital receiver is disconnected to obtain an accurate input voltage for analog-to-digital conversions. This mode can be selected in those IOCON registers that control pins with an analog function. If A/D mode is selected, Hysteresis and Pin mode settings have no effect.

For pins without analog functions, the A/D-mode setting has no effect.

8.3.5 I

2

C mode

If the I

2

C function is selected by the FUNC bits of registers IOCON_PIO0_4 ( Table 116

)

and IOCON_PIO0_5 ( Table 117

), then the I

2

C-bus pins can be configured for different

I

2

C-modes:

Standard mode/Fast-mode I

2

C with input glitch filter (this includes an open-drain output according to the I

2

C-bus specification).

Fast-mode Plus with input glitch filter (this includes an open-drain output according to the I

2

C-bus specification). In this mode, the pins function as high-current sinks.

Standard open-drain I/O functionality without input filter.

Remark:

Either Standard mode/Fast-mode I

2

C or Standard I/O functionality should be selected if the pin is used as GPIO pin.

8.3.6 Open-drain Mode

When output is selected, either by selecting a special function in the FUNC field, or by selecting GPIO function for a pin having a 1 in its GPIODIR register, a 1 in the OD bit selects open-drain operation, that is, a 1 disables the high-drive transistor. This option has no effect on the primary I

2

C pins.

8.4 Register description

The I/O configuration registers control the PIO port pins, the inputs and outputs of all peripherals and functional blocks, the I

2

C-bus pins, and the ADC input pins.

Each port pin PIOn_m has one IOCON register assigned to control the pin’s function and electrical characteristics.

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Chapter 8: LPC1100XL series: I/O configuration (IOCONFIG)

Some input functions (SCK0, DSR, DCD, RI, SSEL1, CT16B0_CAP0, SCK1, MISO1,

MOSI1, CT32B0_CAP0, and RXD) are multiplexed to several physical pins. The

IOCON_LOC registers select the pin location for each of these functions.

Remark:

The IOCON registers are listed in order of their memory locations in Table 104

, which correspond to the order of their physical pin numbers in the LQFP48 package

starting at the upper left corner with pin 1 (PIO2_6). See Table 105

for a listing of IOCON registers ordered by port number.

The IOCON location registers are used to select a physical pin for multiplexed functions.

Remark:

Note that once the pin location has been selected, the function still must be configured in the corresponding IOCON registers for the function to be usable on that pin.

Table 104. Register overview: I/O configuration (base address 0x4004 4000)

Name Access Address offset

Description

IOCON_PIO2_6 R/W 0x000

R/W 0x004

I/O configuration for pin PIO2_6/

CT32B0_MAT1

Reserved

IOCON_PIO2_0

IOCON_RESET_PIO0_0

IOCON_PIO0_1

IOCON_PIO1_8

IOCON_SSEL1_LOC

IOCON_PIO0_2

IOCON_PIO2_7

R/W

R/W

R/W

R/W

R/W

R/W

R/W

0x008

0x00C

0x010

0x014

0x018

0x01C

0x020

Reset value

0xD0

I/O configuration for pin

PIO2_0/DTR/SSEL1

-

0xD0

I/O configuration for pin RESET/PIO0_0 0xD0

I/O configuration for pin

PIO0_1/CLKOUT/CT32B0_MAT2

0xD0

0xD0 I/O configuration for pin

PIO1_8/CT16B1_CAP0

SSEL1 pin location select register 0x0

0xD0 I/O configuration for pin

PIO0_2/SSEL0/CT16B0_CAP0

I/O configuration for pin PIO2_7/

CT32B0_MAT2/RXD

0xD0

-

Reference

Table 106

Table 107

Table 108

Table 106

Table 110

Table 152

Table 111

Table 112

IOCON_PIO2_8

IOCON_PIO2_1

R/W

R/W

0x024

0x028

I/O configuration for pin PIO2_8/

CT32B0_MAT3/TXD

I/O configuration for pin

PIO2_1/DSR/SCK1

0xD0

0xD0

Table 113

Table 114

IOCON_PIO0_3

IOCON_PIO0_4

IOCON_PIO0_5

IOCON_PIO1_9

IOCON_PIO3_4

IOCON_PIO2_4

IOCON_PIO2_5

IOCON_PIO3_5

IOCON_PIO0_6

R/W

R/W

R/W

R/W

R/W

R/W

R/W

R/W

R/W

0x02C

0x030

0x034

0x038

0x03C

0x040

0x044

0x048

0x04C

I/O configuration for pin PIO0_3

I/O configuration for pin PIO0_4/SCL

I/O configuration for pin PIO0_5/SDA

I/O configuration for pin

PIO1_9/CT16B1_MAT0/ MOSI1

I/O configuration for pin PIO3_4/

CT16B0_CAP1/RXD

I/O configuration for pin PIO2_4/

CT16B1_MAT1/ SSEL1

I/O configuration for pin PIO2_5/

CT32B0_MAT0

I/O configuration for pin PIO3_5/

CT16B1_CAP1/TXD

I/O configuration for pin PIO0_6/SCK0

0xD0

0x00

0x00

0xD0

0xD0

0xD0

0xD0

0xD0

0xD0

Table 115

Table 116

Table 117

Table 118

Table 119

Table 120

Table 121

Table 122

Table 123

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Chapter 8: LPC1100XL series: I/O configuration (IOCONFIG)

Table 104. Register overview: I/O configuration (base address 0x4004 4000)

Name Access Address offset

Description

IOCON_PIO0_7

IOCON_PIO2_9

IOCON_PIO2_10

IOCON_PIO2_2

R/W

R/W

R/W

R/W

0x050

0x054

0x058

0x05C

I/O configuration for pin PIO0_7/CTS

I/O configuration for pin PIO2_9/

CT32B0_CAP0

I/O configuration for pin PIO2_10

IOCON_PIO0_8 R/W 0x060

I/O configuration for pin

PIO2_2/DCD/MISO1

I/O configuration for pin

PIO0_8/MISO0/CT16B0_MAT0

IOCON_PIO0_9

IOCON_SWCLK_PIO0_10

IOCON_PIO1_10

IOCON_PIO2_11

IOCON_R_PIO0_11

IOCON_R_PIO1_0

IOCON_R_PIO1_1

IOCON_R_PIO1_2

IOCON_PIO3_0

IOCON_PIO3_1

IOCON_PIO2_3

IOCON_SWDIO_PIO1_3

IOCON_PIO1_4

IOCON_PIO1_11

IOCON_PIO3_2

IOCON_PIO1_5

IOCON_PIO1_6

IOCON_PIO1_7

R/W

R/W

R/W

R/W

R/W

R/W

R/W

R/W

R/W

R/W

R/W

R/W

R/W

R/W

R/W

R/W

R/W

R/W

0x064

0x068

0x06C

0x070

0x074

0x078

0x07C

0x080

0x084

0x088

0x08C

0x090

0x094

0x098

0x09C

0x0A0

0x0A4

0x0A8

Reset value

0xD0

0xD0

0xD0

0xD0

0xD0

I/O configuration for pin

PIO0_9/MOSI0/CT16B0_MAT1

0xD0

I/O configuration for pin

SWCLK/PIO0_10/

SCK0/CT16B0_MAT2

I/O configuration for pin

PIO1_10/AD6/CT16B1_MAT1/ MISO1

0xD0

0xD0

I/O configuration for pin PIO2_11/SCK0/

CT32B0_CAP1

0xD0

0xD0 I/O configuration for pin

R/PIO0_11/AD0/CT32B0_MAT3

I/O configuration for pin

R/PIO1_0/AD1/CT32B1_CAP0

0xD0

0xD0 I/O configuration for pin

R/PIO1_1/AD2/CT32B1_MAT0

I/O configuration for pin

R/PIO1_2/AD3/CT32B1_MAT1

I/O configuration for pin

PIO3_0/DTR/CT16B0_MAT0/TXD

I/O configuration for pin

PIO3_1/DSR/CT16B0_MAT1/RXD

0xD0

0xD0

0xD0

0xD0 I/O configuration for pin

PIO2_3/RI/MOSI1

I/O configuration for pin

SWDIO/PIO1_3/AD4/CT32B1_MAT2

I/O configuration for pin

PIO1_4/AD5/CT32B1_MAT3

I/O configuration for pin

PIO1_11/AD7/CT32B1_CAP1

I/O configuration for pin PIO3_2/DCD/

CT16B0_MAT2/SCK1

I/O configuration for pin

PIO1_5/RTS/CT32B0_CAP0

I/O configuration for pin

PIO1_6/RXD/CT32B0_MAT0

I/O configuration for pin

PIO1_7/TXD/CT32B0_MAT1

0xD0

0xD0

0xD0

0xD0

0xD0

0xD0

0xD0

Reference

Table 124

Table 125

Table 126

Table 127

Table 128

Table 129

Table 130

Table 131

Table 132

Table 133

Table 134

Table 135

Table 136

Table 137

Table 138

Table 139

Table 140

Table 141

Table 142

Table 143

Table 144

Table 145

Table 146

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Chapter 8: LPC1100XL series: I/O configuration (IOCONFIG)

Table 104. Register overview: I/O configuration (base address 0x4004 4000)

Name Access Address offset

Description

IOCON_PIO3_3 R/W 0x0AC

IOCON_SCK0_LOC

IOCON_DSR_LOC

IOCON_DCD_LOC

IOCON_RI_LOC

IOCON_CT16B0_CAP0_LOC

R/W

R/W

R/W

R/W

R/W

0x0B0

0x0B4

0x0B8

0x0BC

0x0C0

I/O configuration for pin PIO3_3/RI/

CT16B0_CAP0

SCK0 pin location select register

DSR pin location select register

DCD pin location select register

RI pin location select register

CT16B0_CAP0 pin location select register

IOCON_SCK1_LOC

IOCON_MISO1_LOC

IOCON_MOSI1_LOC

IOCON_CT32B0_CAP0_LOC

IOCON_RXD_LOC

R/W

R/W

R/W

R/W

R/W

0x0C4

0x0C8

0x0CC

0x0D0

0x0D4

SCK1 pin location select register

MISO1 pin location select register

MOSI1 pin location select register

CT32B0_CAP0 pin location select register

RXD pin location select register

Reset value

0xD0

0x00

0x00

0x00

0x00

0x00

0x00

0x00

0x00

0x00

0x00

Reference

Table 147

Table 148

Table 149

Table 150

Table 151

Table 153

Table 154

Table 155

Table 156

Table 157

Table 158

PIO1_0

PIO1_1

PIO1_2

PIO1_3

PIO1_4

PIO1_5

PIO1_6

PIO1_7

PIO1_8

PIO1_9

Table 105. I/O configuration registers ordered by port number

Port pin Register name LPC1111/

12/13/14

LPC1113/14/15

HVQFN33 LQFP48

PIO0_0

PIO0_1

PIO0_2

PIO0_3

IOCON_RESET_PIO0_0

IOCON_PIO0_1

IOCON_PIO0_2

IOCON_PIO0_3 yes yes yes yes yes yes yes yes

PIO0_4

PIO0_5

PIO0_6

PIO0_7

PIO0_8

PIO0_9

PIO0_10

PIO0_11

IOCON_PIO0_4

IOCON_PIO0_5

IOCON_PIO0_6

IOCON_PIO0_7

IOCON_PIO0_8

IOCON_PIO0_9

IOCON_SWCLK_PIO0_10

IOCON_R_PIO0_11 yes yes yes yes yes yes yes yes yes yes yes yes yes yes yes yes

IOCON_R_PIO1_0

IOCON_R_PIO1_1

IOCON_R_PIO1_2

IOCON_SWDIO_PIO1_3

IOCON_PIO1_4

IOCON_PIO1_5

IOCON_PIO1_6

IOCON_PIO1_7

IOCON_PIO1_8

IOCON_PIO1_9 yes yes yes yes yes yes yes yes yes yes yes yes yes yes yes yes yes yes yes yes

Reference

Table 108

Table 106

Table 111

Table 115

Table 116

Table 117

Table 123

Table 124

Table 128

Table 129

Table 130

Table 133

Table 134

Table 135

Table 136

Table 140

Table 141

Table 144

Table 145

Table 146

Table 110

Table 118

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Chapter 8: LPC1100XL series: I/O configuration (IOCONFIG)

Table 105. I/O configuration registers ordered by port number

Port pin Register name LPC1111/

12/13/14

LPC1113/14/15

HVQFN33

yes

LQFP48

yes PIO1_10

PIO1_11

PIO2_0

PIO2_1

PIO2_2

PIO2_3

PIO2_4

PIO2_5

PIO2_6

PIO2_7

PIO2_8

PIO2_9

PIO2_10

PIO2_11

PIO3_0

PIO3_1

PIO3_2

PIO3_3

PIO3_4

PIO3_5

IOCON_PIO1_10

IOCON_PIO1_11

IOCON_PIO2_0

IOCON_PIO2_1

IOCON_PIO2_2

IOCON_PIO2_3

IOCON_PIO2_4

IOCON_PIO2_5

IOCON_PIO2_6

IOCON_PIO2_7

IOCON_PIO2_8

IOCON_PIO2_9

IOCON_PIO2_10

IOCON_PIO2_11

IOCON_PIO3_0

IOCON_PIO3_1

IOCON_PIO3_2

IOCON_PIO3_3

IOCON_PIO3_4

IOCON_PIO3_5 yes yes no no no no no no no no no no no no no yes no yes yes yes yes yes yes yes yes yes yes yes yes yes yes yes yes yes yes yes yes yes

Reference

Table 131

Table 142

Table 107

Table 114

Table 127

Table 139

Table 120

Table 121

Table 106

Table 112

Table 113

Table 125

Table 126

Table 132

Table 137

Table 138

Table 143

Table 147

Table 119

Table 122

8.4.1 IOCON_PIO2_6

Table 106. IOCON_PIO2_6 register (IOCON_PIO2_6, address 0x4004 4000) bit description

Bit Symbol Value Description Reset value

2:0 FUNC 000

4:3 MODE

0x0

0x1

Selects pin function. All other values are reserved.

Selects function PIO2_6.

Selects function CT32B0_MAT1.

Selects function mode (on-chip pull-up/pull-down resistor control).

Inactive (no pull-down/pull-up resistor enabled).

10

5 HYS

0x0

0x1

0x2

0x3

Pull-down resistor enabled.

Pull-up resistor enabled.

Repeater mode.

Hysteresis.

0

9:6 -

0

1

Disable.

Enable.

Reserved 0011

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Chapter 8: LPC1100XL series: I/O configuration (IOCONFIG)

Table 106. IOCON_PIO2_6 register (IOCON_PIO2_6, address 0x4004 4000) bit description

Bit Symbol Value Description Reset value

10 OD 0

31:11 -

0

1

Selects pseudo open-drain mode.

Standard GPIO output

Open-drain output

Reserved -

8.4.2 IOCON_PIO2_0

Table 107. IOCON_PIO2_0 register (IOCON_PIO2_0, address 0x4004 4008) bit description

Bit Symbol Value Description Reset value

2:0 FUNC Selects pin function. All other values are reserved.

000

4:3 MODE

0x0

0x1

0x2

Selects function PIO2_0.

Select function DTR.

Select function SSEL1.

Selects function mode (on-chip pull-up/pull-down resistor control).

Inactive (no pull-down/pull-up resistor enabled).

10

5 HYS

0x0

0x1

0x2

0x3

Pull-down resistor enabled.

Pull-up resistor enabled.

Repeater mode.

Hysteresis.

0

9:6

10

31:11

-

-

OD

-

-

0

1

0

1

Disable.

Enable.

Reserved

Selects pseudo open-drain mode.

Standard GPIO output

Open-drain output

Reserved -

0011

0

8.4.3 IOCON_PIO_RESET_PIO0_0

Table 108. IOCON_RESET_PIO0_0 register (IOCON_RESET_PIO0_0, address 0x4004 400C) bit description

Bit Symbol Value Description

2:0 FUNC Selects pin function. All other values are reserved.

Reset value

000

0x0

0x1

Selects function RESET.

Selects function PIO0_0.

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Chapter 8: LPC1100XL series: I/O configuration (IOCONFIG)

Table 108. IOCON_RESET_PIO0_0 register (IOCON_RESET_PIO0_0, address 0x4004 400C) bit description

Bit Symbol Value Description Reset value

4:3 MODE Selects function mode (on-chip pull-up/pull-down resistor control).

Inactive (no pull-down/pull-up resistor enabled).

10

5 HYS

0x0

0x1

0x2

0x3

Pull-down resistor enabled.

Pull-up resistor enabled.

Repeater mode.

Hysteresis.

0

9:6

10

31:11

-

-

OD

-

-

0

1

0

1

Disable.

Enable.

Reserved

Selects pseudo open-drain mode.

Standard GPIO output

Open-drain output

Reserved -

0011

0

8.4.4 IOCON_PIO0_1

Table 109. IOCON_PIO0_1 register (IOCON_PIO0_1, address 0x4004 4010) bit description

Bit Symbol Value Description Reset value

2:0 FUNC 000

4:3 MODE

0x0

0x1

0x2

Selects pin function. All other values are reserved.

Selects function PIO0_1.

Selects function CLKOUT.

Selects function CT32B0_MAT2.

Selects function mode (on-chip pull-up/pull-down resistor control).

10

5

9:6

10

-

HYS

OD

-

0x0

0x1

0x2

0x3

0

1

Inactive (no pull-down/pull-up resistor enabled).

Pull-down resistor enabled.

Pull-up resistor enabled.

Repeater mode.

Hysteresis.

Disable.

Enable.

Reserved

0

0011

0

31:11 -

0

1

Selects pseudo open-drain mode.

Standard GPIO output

Open-drain output

Reserved -

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Chapter 8: LPC1100XL series: I/O configuration (IOCONFIG)

8.4.5 IOCON_PIO1_8

Table 110. IOCON_PIO1_8 register (IOCON_PIO1_8, address 0x4004 4014) bit description

Bit Symbol Value Description Reset value

2:0 FUNC 000

4:3 MODE

0x0

0x1

Selects pin function. All other values are reserved.

Selects function PIO1_8.

Selects function CT16B1_CAP0.

Selects function mode (on-chip pull-up/pull-down resistor control).

10

5

9:6

10

-

HYS

OD

-

0x0

0x1

0x2

0x3

0

1

Inactive (no pull-down/pull-up resistor enabled).

Pull-down resistor enabled.

Pull-up resistor enabled.

Repeater mode.

Hysteresis.

Disable.

Enable.

Reserved

0

0011

0

31:11 -

0

1

Selects pseudo open-drain mode.

Standard GPIO output

Open-drain output

Reserved -

8.4.6 IOCON_PIO0_2

Table 111. IOCON_PIO0_2 register (IOCON_PIO0_2, address 0x4004 401C) bit description

Bit Symbol Value Description Reset value

2:0 FUNC Selects pin function. All other values are reserved.

000

4:3 MODE

0x0

0x1

0x2

Selects function PIO0_2.

Selects function SSEL0.

Selects function CT16B0_CAP0.

Selects function mode (on-chip pull-up/pull-down resistor control).

Inactive (no pull-down/pull-up resistor enabled).

10

5 HYS

0x0

0x1

0x2

0x3

Pull-down resistor enabled.

Pull-up resistor enabled.

Repeater mode.

Hysteresis.

0

9:6 -

0

1

Disable.

Enable.

Reserved 0011

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Chapter 8: LPC1100XL series: I/O configuration (IOCONFIG)

Table 111. IOCON_PIO0_2 register (IOCON_PIO0_2, address 0x4004 401C) bit description

Bit Symbol Value Description Reset value

10 OD 0

31:11 -

0

1

Selects pseudo open-drain mode.

Standard GPIO output

Open-drain output

Reserved -

8.4.7 IOCON_PIO2_7

Table 112. IOCON_PIO2_7 register (IOCON_PIO2_7, address 0x4004 4020) bit description

Bit Symbol Value Description Reset value

2:0 FUNC Selects pin function. All other values are reserved.

000

4:3 MODE

0x0

0x1

0x2

Selects function PIO2_7.

Selects function CT32B0_MAT2.

Selects function RXD.

Selects function mode (on-chip pull-up/pull-down resistor control).

Inactive (no pull-down/pull-up resistor enabled).

10

5 HYS

0x0

0x1

0x2

0x3

Pull-down resistor enabled.

Pull-up resistor enabled.

Repeater mode.

Hysteresis.

0

9:6

10

31:11

-

-

OD

-

-

0

1

0

1

Disable.

Enable.

Reserved

Selects pseudo open-drain mode.

Standard GPIO output

Open-drain output

Reserved -

0011

0

8.4.8 IOCON_PIO2_8

Table 113. IOCON_PIO2_8 register (IOCON_PIO2_8, address 0x4004 4024) bit description

Bit Symbol Value Description Reset value

2:0 FUNC 000

0x0

0x1

0x2

Selects pin function. All other values are reserved.

Selects function PIO2_8.

Selects function CT32B0_MAT3.

Selects function TXD.

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Chapter 8: LPC1100XL series: I/O configuration (IOCONFIG)

Table 113. IOCON_PIO2_8 register (IOCON_PIO2_8, address 0x4004 4024) bit description

Bit Symbol Value Description Reset value

4:3 MODE 10

5 HYS

0x0

0x1

0x2

0x3

Selects function mode (on-chip pull-up/pull-down resistor control).

Inactive (no pull-down/pull-up resistor enabled).

Pull-down resistor enabled.

Pull-up resistor enabled.

Repeater mode.

Hysteresis.

Disable.

0

9:6

10

-

OD

0

-

1 Enable.

Reserved

Selects pseudo open-drain mode.

Standard GPIO output

0011

0

31:11 -

0

-

1 Open-drain output

Reserved -

8.4.9 IOCON_PIO2_1

Table 114. IOCON_PIO2_1 register (IOCON_PIO2_1, address 0x4004 4028) bit description

Bit Symbol Value Description Reset value

2:0 FUNC Selects pin function. All other values are reserved.

000

4:3 MODE

0x0

0x1

0x2

Selects function PIO2_1.

Select function DSR.

Select function SCK1.

Selects function mode (on-chip pull-up/pull-down resistor control).

Inactive (no pull-down/pull-up resistor enabled).

10

5 HYS

0x0

0x1

0x2

0x3

Pull-down resistor enabled.

Pull-up resistor enabled.

Repeater mode.

Hysteresis.

0

9:6

10

31:11

-

-

OD

-

-

0

1

0

1

Disable.

Enable.

Reserved

Selects pseudo open-drain mode.

Standard GPIO output

Open-drain output

Reserved -

0011

0

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Chapter 8: LPC1100XL series: I/O configuration (IOCONFIG)

8.4.10 IOCON_PIO0_3

Table 115. IOCON_PIO0_3 register (IOCON_PIO0_3, address 0x4004 402C) bit description

Bit Symbol Value Description Reset value

2:0 FUNC Selects pin function. All other values are reserved.

000

0x0

4:3

5

MODE

HYS

0x0

0x1

0x2

0x3

Selects function PIO0_3.

Selects function mode (on-chip pull-up/pull-down resistor control).

Inactive (no pull-down/pull-up resistor enabled).

Pull-down resistor enabled.

Pull-up resistor enabled.

Repeater mode.

Hysteresis.

10

0

9:6

10

31:11

-

-

OD

-

-

0

1

0

1

Disable.

Enable.

Reserved

Selects pseudo open-drain mode.

Standard GPIO output

Open-drain output

Reserved -

0011

0

8.4.11 IOCON_PIO0_4

Table 116. IOCON_PIO0_4 register (IOCON_PIO0_4, address 0x4004 4030) bit description

Bit Symbol Value Description Reset value

2:0 FUNC

7:3

9:8 I2CMODE

-

0x0

0x1

Selects pin function. All other values are reserved.

Selects function PIO0_4 (open-drain pin).

Selects I2C function SCL (open-drain pin).

Reserved.

000

00000

Selects I2C mode. Select Standard mode (I2CMODE = 00, default) or Standard I/O functionality (I2CMODE = 01) if the pin function is GPIO (FUNC = 000).

00

Standard mode/ Fast-mode I2C.

31:10 -

0x0

0x1

0x2

0x3

Standard I/O functionality

Fast-mode Plus I2C

Reserved.

Reserved.

-

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Chapter 8: LPC1100XL series: I/O configuration (IOCONFIG)

8.4.12 IOCON_PIO0_5

Table 117. IOCON_PIO0_5 register (IOCON_PIO0_5, address 0x4004 4034) bit description

Bit Symbol Value Description Reset value

2:0 FUNC 000

7:3

9:8 I2CMODE

-

0x0

0x1

Selects pin function. All other values are reserved.

Selects function PIO0_5 (open-drain pin).

Selects I2C function SDA (open-drain pin).

Reserved.

Selects I2C mode. Select Standard mode (I2CMODE = 00, default) or Standard I/O functionality (I2CMODE = 01) if the pin function is GPIO (FUNC = 000).

00000

00

31:10 -

0x0

0x1

0x2

0x3

Standard mode/ Fast-mode I2C.

Standard I/O functionality

Fast-mode Plus I2C

Reserved.

Reserved.

-

8.4.13 IOCON_PIO1_9

Remark:

See

Section 8.1

for part specific details.

Table 118. IOCON_PIO1_9 register (IOCON_PIO1_9, address 0x4004 4038) bit description

Bit Symbol Value Description Reset value

2:0 FUNC 000

4:3 MODE

0x0

0x1

0x2

Selects pin function. All other values are reserved.

Selects function PIO1_9.

Selects function CT16B1_MAT0.

Selects function MOSI1.

Selects function mode (on-chip pull-up/pull-down resistor control).

10

5

9:6

10

-

HYS

OD

-

0x0

0x1

0x2

0x3

0

1

Inactive (no pull-down/pull-up resistor enabled).

Pull-down resistor enabled.

Pull-up resistor enabled.

Repeater mode.

Hysteresis.

Disable.

Enable.

Reserved

0

0011

0

31:11 -

0

1

Selects pseudo open-drain mode.

Standard GPIO output

Open-drain output

Reserved -

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8.4.14 IOCON_PIO3_4

Remark:

See

Section 8.1

for part specific details.

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Chapter 8: LPC1100XL series: I/O configuration (IOCONFIG)

Table 119. IOCON_PIO3_4 register (IOCON_PIO3_4, address 0x4004 403C) bit description

Bit Symbol Value Description Reset value

2:0 FUNC 000

4:3 MODE

0x0

0x1

0x2

Selects pin function. All other values are reserved.

Selects function PIO3_4.

Selects function CT16B0_CAP1.

Selects function RXD.

Selects function mode (on-chip pull-up/pull-down resistor control).

10

5

9:6

10

-

HYS

OD

-

0x0

0x1

0x2

0x3

0

1

Inactive (no pull-down/pull-up resistor enabled).

Pull-down resistor enabled.

Pull-up resistor enabled.

Repeater mode.

Hysteresis.

Disable.

Enable.

Reserved

0

0011

0

31:11 -

0

1

Selects pseudo open-drain mode.

Standard GPIO output

Open-drain output

Reserved -

8.4.15 IOCON_PIO2_4

Remark:

See

Section 8.1

for part specific details.

Table 120. IOCON_PIO2_4 register (IOCON_PIO2_4, address 0x4004 4040) bit description

Bit Symbol Value Description Reset value

2:0 FUNC Selects pin function. All other values are reserved.

000

4:3 MODE

0x0

0x1

0x2

Selects function PIO2_4.

Selects function CT16B1_MAT1.

Selects function SSEL1.

Selects function mode (on-chip pull-up/pull-down resistor control).

Inactive (no pull-down/pull-up resistor enabled).

10

5 HYS

0x0

0x1

0x2

0x3

Pull-down resistor enabled.

Pull-up resistor enabled.

Repeater mode.

Hysteresis.

0

9:6 -

0

1

Disable.

Enable.

Reserved 0011

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Chapter 8: LPC1100XL series: I/O configuration (IOCONFIG)

Table 120. IOCON_PIO2_4 register (IOCON_PIO2_4, address 0x4004 4040) bit description

Bit Symbol Value Description Reset value

10 OD 0

31:11 -

0

1

Selects pseudo open-drain mode.

Standard GPIO output

Open-drain output

Reserved -

8.4.16 IOCON_PIO2_5

Remark:

See

Section 8.1

for part specific details.

Table 121. IOCON_PIO2_5 register (IOCON_PIO2_5, address 0x4004 4044) bit description

Bit Symbol Value Description Reset value

2:0 FUNC Selects pin function. All other values are reserved.

000

4:3 MODE

0x0

0x1

Selects function PIO2_5.

Selects function CT32B0_MAT0.

Selects function mode (on-chip pull-up/pull-down resistor control).

10

5

9:6

10

-

HYS

OD

-

0x0

0x1

0x2

0x3

0

1

Inactive (no pull-down/pull-up resistor enabled).

Pull-down resistor enabled.

Pull-up resistor enabled.

Repeater mode.

Hysteresis.

Disable.

Enable.

Reserved

0

0011

0

31:11 -

0

1

Selects pseudo open-drain mode.

Standard GPIO output

Open-drain output

Reserved -

8.4.17 IOCON_PIO3_5

Remark:

See

Section 8.1

for part specific details.

Table 122. IOCON_PIO3_5 register (IOCON_PIO3_5, address 0x4004 4048) bit description

Bit Symbol Value Description Reset value

2:0 FUNC 000

0x0

0x1

0x2

Selects pin function. All other values are reserved.

Selects function PIO3_5.

Selects function CT16B1_CAP1.

Selects function TXD.

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Chapter 8: LPC1100XL series: I/O configuration (IOCONFIG)

Table 122. IOCON_PIO3_5 register (IOCON_PIO3_5, address 0x4004 4048) bit description

Bit Symbol Value Description Reset value

4:3 MODE 10

5 HYS

0x0

0x1

0x2

0x3

Selects function mode (on-chip pull-up/pull-down resistor control).

Inactive (no pull-down/pull-up resistor enabled).

Pull-down resistor enabled.

Pull-up resistor enabled.

Repeater mode.

Hysteresis.

Disable.

0

9:6

10

-

OD

0

-

1 Enable.

Reserved

Selects pseudo open-drain mode.

Standard GPIO output

0011

0

31:11 -

0

-

1 Open-drain output

Reserved -

8.4.18 IOCON_PIO0_6

Table 123. IOCON_PIO0_6 register (IOCON_PIO0_6, address 0x4004 404C) bit description

Bit Symbol Value Description Reset value

2:0 FUNC Selects pin function. All other values are reserved.

000

0x0

0x1

0x2

Selects function PIO0_6.

Reserved.

4:3 MODE

Selects function SCK0 (only if pin PIO0_6/SCK0 selected in

Table 148 ).

Selects function mode (on-chip pull-up/pull-down resistor control).

10

5

9:6

10

-

HYS

OD

-

0x0

0x1

0x2

0x3

0

1

Inactive (no pull-down/pull-up resistor enabled).

Pull-down resistor enabled.

Pull-up resistor enabled.

Repeater mode.

Hysteresis.

Disable.

Enable.

Reserved

0

0011

0

31:11 -

0

1

Selects pseudo open-drain mode.

Standard GPIO output

Open-drain output

Reserved -

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Chapter 8: LPC1100XL series: I/O configuration (IOCONFIG)

8.4.19 IOCON_PIO0_7

Table 124. IOCON_PIO0_7 register (IOCON_PIO0_7, address 0x4004 4050) bit description

Bit Symbol Value Description Reset value

2:0 FUNC 000

4:3 MODE

0x0

0x1

Selects pin function. All other values are reserved.

Selects function PIO0_7.

Select function CTS.

Selects function mode (on-chip pull-up/pull-down resistor control).

10

5

9:6

10

-

HYS

OD

-

0x0

0x1

0x2

0x3

0

1

Inactive (no pull-down/pull-up resistor enabled).

Pull-down resistor enabled.

Pull-up resistor enabled.

Repeater mode.

Hysteresis.

Disable.

Enable.

Reserved

0

0011

0

31:11 -

0

1

Selects pseudo open-drain mode.

Standard GPIO output

Open-drain output

Reserved -

8.4.20 IOCON_PIO2_9

Remark:

See

Section 8.1

for part specific details.

Table 125. IOCON_PIO2_9 register (IOCON_PIO2_9, address 0x4004 4054) bit description

Bit Symbol Value Description Reset value

2:0 FUNC Selects pin function. All other values are reserved.

000

4:3 MODE

0x0

0x1

Selects function PIO2_9.

Selects function CT32B0_CAP0.

Selects function mode (on-chip pull-up/pull-down resistor control).

10

5

9:6 -

HYS

-

0x0

0x1

0x2

0x3

0

1

Inactive (no pull-down/pull-up resistor enabled).

Pull-down resistor enabled.

Pull-up resistor enabled.

Repeater mode.

Hysteresis.

Disable.

Enable.

Reserved

0

0011

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UM10398

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Table 125. IOCON_PIO2_9 register (IOCON_PIO2_9, address 0x4004 4054) bit description

Bit Symbol Value Description Reset value

10 OD 0

31:11 -

0

1

Selects pseudo open-drain mode.

Standard GPIO output

Open-drain output

Reserved -

8.4.21 IOCON_PIO2_10

Table 126. IOCON_PIO2_10 register (IOCON_PIO2_10, address 0x4004 4058) bit description

Bit Symbol Value Description Reset value

2:0 FUNC Selects pin function. All other values are reserved.

000

4:3 MODE

0x0 Selects function PIO2_10.

Selects function mode (on-chip pull-up/pull-down resistor control).

Inactive (no pull-down/pull-up resistor enabled).

10

5 HYS

0x0

0x1

0x2

0x3

Pull-down resistor enabled.

Pull-up resistor enabled.

Repeater mode.

Hysteresis.

0

9:6

10

31:11

-

-

OD

-

-

0

1

0

1

Disable.

Enable.

Reserved

Selects pseudo open-drain mode.

Standard GPIO output

Open-drain output

Reserved -

0011

0

8.4.22 IOCON_PIO2_2

Table 127. IOCON_PIO2_2 register (IOCON_PIO2_2, address 0x4004 405C) bit description

Bit Symbol Value Description Reset value

2:0 FUNC 000

4:3 MODE

0x0

0x1

0x2

Selects pin function. All other values are reserved.

Selects function PIO2_2.

Select function DCD.

Select function MISO1.

Selects function mode (on-chip pull-up/pull-down resistor control).

10

0x0

0x1

0x2

0x3

Inactive (no pull-down/pull-up resistor enabled).

Pull-down resistor enabled.

Pull-up resistor enabled.

Repeater mode.

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Chapter 8: LPC1100XL series: I/O configuration (IOCONFIG)

Table 127. IOCON_PIO2_2 register (IOCON_PIO2_2, address 0x4004 405C) bit description

Bit Symbol Value Description Reset value

5 HYS 0

9:6

10

-

OD

-

0

1

Hysteresis.

Disable.

Enable.

Reserved 0011

0

31:11 -

0

1

Selects pseudo open-drain mode.

Standard GPIO output

Open-drain output

Reserved -

8.4.23 IOCON_PIO0_8

Table 128. IOCON_PIO0_8 register (IOCON_PIO0_8, address 0x4004 4060) bit description

Bit Symbol Value Description Reset value

2:0 FUNC Selects pin function. All other values are reserved.

000

4:3 MODE

0x0

0x1

0x2

Selects function PIO0_8.

Selects function MISO0.

Selects function CT16B0_MAT0.

Selects function mode (on-chip pull-up/pull-down resistor control).

Inactive (no pull-down/pull-up resistor enabled).

10

5 HYS

0x0

0x1

0x2

0x3

Pull-down resistor enabled.

Pull-up resistor enabled.

Repeater mode.

Hysteresis.

0

9:6

10

31:11

-

-

OD

-

-

0

1

0

1

Disable.

Enable.

Reserved

Selects pseudo open-drain mode.

Standard GPIO output

Open-drain output

Reserved -

0011

0

UM10398

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8.4.24 IOCON_PIO0_9

Table 129. IOCON_PIO0_9 register (IOCON_PIO0_9, address 0x4004 4064) bit description

Bit Symbol Value Description Reset value

2:0 FUNC 000

0x0

0x1

0x2

Selects pin function. All other values are reserved.

Selects function PIO0_9.

Selects function MOSI0.

Selects function CT16B0_MAT1.

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Chapter 8: LPC1100XL series: I/O configuration (IOCONFIG)

UM10398

User manual

Table 129. IOCON_PIO0_9 register (IOCON_PIO0_9, address 0x4004 4064) bit description

Bit Symbol Value Description Reset value

4:3 MODE 10

5 HYS

0x0

0x1

0x2

0x3

Selects function mode (on-chip pull-up/pull-down resistor control).

Inactive (no pull-down/pull-up resistor enabled).

Pull-down resistor enabled.

Pull-up resistor enabled.

Repeater mode.

Hysteresis.

Disable.

0

9:6

10

-

OD

0

-

1 Enable.

Reserved

Selects pseudo open-drain mode.

Standard GPIO output

0011

0

31:11 -

0

-

1 Open-drain output

Reserved -

8.4.25 IOCON_SWCLK_PIO0_10

Table 130. IOCON_SWCLK_PIO0_10 register (IOCON_SWCLK_PIO0_10, address 0x4004

4068) bit description

Bit Symbol Value Description

2:0 FUNC

0x0

Selects pin function. All other values are reserved.

Selects function SWCLK.

Reset value

000

0x1

0x2

4:3 MODE

0x3

Selects function PIO0_10.

Selects function SCK0 (only if pin

SWCLK/PIO0_10/SCK0/CT16B0_MAT2 selected in

Table 148

).

Selects function CT16B0_MAT2.

Selects function mode (on-chip pull-up/pull-down resistor control).

Inactive (no pull-down/pull-up resistor enabled).

10

5 HYS

0x0

0x1

0x2

0x3

Pull-down resistor enabled.

Pull-up resistor enabled.

Repeater mode.

Hysteresis.

0

9:6

10

31:11 -

-

OD

-

-

0

1

0

1

Disable.

Enable.

Reserved

Selects pseudo open-drain mode.

Standard GPIO output

Open-drain output

Reserved -

0011

0

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Chapter 8: LPC1100XL series: I/O configuration (IOCONFIG)

UM10398

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8.4.26 IOCON_PIO1_10

Table 131. IOCON_PIO1_10 register (IOCON_PIO1_10, address 0x4004 406C) bit description

Bit Symbol Value Description Reset value

2:0 FUNC 000

4:3 MODE

0x0

0x1

0x2

0x3

Selects pin function. All other values are reserved.

Selects function PIO1_10.

Selects function AD6.

Selects function CT16B1_MAT1.

Selects function MISO1.

Selects function mode (on-chip pull-up/pull-down resistor control).

10

5

6

7

9:8

10

31:11

-

-

HYS

0

-

ADMODE

-

1

0

-

1

OD

0

-

1

0x0

0x1

0x2

0x3

Inactive (no pull-down/pull-up resistor enabled).

Pull-down resistor enabled.

Pull-up resistor enabled.

Repeater mode.

Hysteresis.

Disable.

Enable.

Reserved

Selects Analog/Digital mode

Analog input mode

Digital functional mode

Reserved

Selects pseudo open-drain mode.

Standard GPIO output

Open-drain output

Reserved -

0

1

1

00

0

8.4.27 IOCON_PIO2_11

Table 132. IOCON_PIO2_11 register (IOCON_PIO2_11, address 0x4004 4070) bit description

Bit Symbol Value Description Reset value

2:0 FUNC Selects pin function. All other values are reserved.

000

0x0

0x1

0x2

Selects function PIO2_11.

Select function SCK0 (only if pin PIO2_11/SCK0 selected in

Table 148 ).

Select function CT32B0_CAP1.

4:3 MODE 10

0x0

0x1

0x2

0x3

Selects function mode (on-chip pull-up/pull-down resistor control).

Inactive (no pull-down/pull-up resistor enabled).

Pull-down resistor enabled.

Pull-up resistor enabled.

Repeater mode.

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Chapter 8: LPC1100XL series: I/O configuration (IOCONFIG)

Table 132. IOCON_PIO2_11 register (IOCON_PIO2_11, address 0x4004 4070) bit description

Bit Symbol Value Description Reset value

5 HYS 0

9:6

10

-

OD

-

0

1

Hysteresis.

Disable.

Enable.

Reserved 0011

0

31:11 -

0

1

Selects pseudo open-drain mode.

Standard GPIO output

Open-drain output

Reserved -

8.4.28 IOCON_R_PIO0_11

Table 133. IOCON_R_PIO0_11 register (IOCON_R_PIO0_11, address 0x4004 4074) bit description

Bit Symbol Value Description

2:0 FUNC

Reset value

000

0x0

0x1

Selects pin function. All other values are reserved.

Selects function R. This function is reserved. Select one of the alternate functions below.

Selects function PIO0_11.

4:3 MODE

0x2

0x3

Selects function AD0.

Selects function CT32B0_MAT3.

Selects function mode (on-chip pull-up/pull-down resistor control).

10

5

6

7

9:8

10

31:11

-

-

HYS

0

-

ADMODE

-

1

0

-

1

OD

0x0

0x1

0x2

0x3

0

-

1

Inactive (no pull-down/pull-up resistor enabled).

Pull-down resistor enabled.

Pull-up resistor enabled.

Repeater mode.

Hysteresis.

Disable.

Enable.

Reserved

Selects Analog/Digital mode

Analog input mode

Digital functional mode

Reserved

Selects pseudo open-drain mode.

Standard GPIO output

Open-drain output

Reserved -

0

1

1

00

0

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Chapter 8: LPC1100XL series: I/O configuration (IOCONFIG)

8.4.29 IOCON_R_PIO1_0

Table 134. IOCON_R_PIO1_0 register (IOCON_R_PIO1_0, address 0x4004 4078) bit description

Bit Symbol Value Description

2:0 FUNC

Reset value

000

0x0

Selects pin function. All other values are reserved.

Selects function R. This function is reserved. Select one of the alternate functions below.

Selects function PIO1_0.

4:3 MODE

0x1

0x2

0x3

Selects function AD1.

Selects function CT32B1_CAP0.

Selects function mode (on-chip pull-up/pull-down resistor control).

10

5

6

7

9:8

10

31:11

-

-

HYS

0

-

ADMODE

-

1

0

-

1

OD

0x0

0x1

0x2

0x3

0

-

1

Inactive (no pull-down/pull-up resistor enabled).

Pull-down resistor enabled.

Pull-up resistor enabled.

Repeater mode.

Hysteresis.

Disable.

Enable.

Reserved

Selects Analog/Digital mode

Analog input mode

Digital functional mode

Reserved

Selects pseudo open-drain mode.

Standard GPIO output

Open-drain output

Reserved -

0

1

1

00

0

8.4.30 IOCON_R_PIO1_1

Table 135. IOCON_R_PIO1_1 register (IOCON_R_PIO1_1, address 0x4004 407C) bit description

Bit Symbol Value Description

2:0 FUNC

Reset value

000

0x0

0x1

Selects pin function. All other values are reserved.

Selects function R. This function is reserved. Select one of the alternate functions below.

Selects function PIO1_1.

0x2

0x3

Selects function AD2.

Selects function CT32B1_MAT0.

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Table 135. IOCON_R_PIO1_1 register (IOCON_R_PIO1_1, address 0x4004 407C) bit description

…continued

Bit Symbol Value Description Reset value

4:3 MODE Selects function mode (on-chip pull-up/pull-down resistor control).

Inactive (no pull-down/pull-up resistor enabled).

10

5 HYS

0x0

0x1

0x2

0x3

Pull-down resistor enabled.

Pull-up resistor enabled.

Repeater mode.

Hysteresis.

0

6

7

9:8

10

31:11

-

-

ADMODE

-

0

1

-

0

1

OD

-

0

1

Disable.

Enable.

Reserved

Selects Analog/Digital mode

Analog input mode

Digital functional mode

Reserved

Selects pseudo open-drain mode.

Standard GPIO output

Open-drain output

Reserved -

1

1

00

0

8.4.31 IOCON_R_PIO1_2

Table 136. IOCON_R_PIO1_2 register (IOCON_R_PIO1_2, address 0x4004 4080) bit description

Bit Symbol Value Description

2:0 FUNC

Reset value

000

0x0

Selects pin function. All other values are reserved.

Selects function R. This function is reserved. Select one of the alternate functions below.

4:3 MODE

0x1

0x2

0x3

Selects function PIO1_2.

Selects function AD3.

Selects function CT32B1_MAT1.

Selects function mode (on-chip pull-up/pull-down resistor control).

Inactive (no pull-down/pull-up resistor enabled).

10

5

6 -

HYS

-

0x0

0x1

0x2

0x3

0

1

Pull-down resistor enabled.

Pull-up resistor enabled.

Repeater mode.

Hysteresis.

Disable.

Enable.

Reserved

0

1

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Chapter 8: LPC1100XL series: I/O configuration (IOCONFIG)

Table 136. IOCON_R_PIO1_2 register (IOCON_R_PIO1_2, address 0x4004 4080) bit description

…continued

Bit Symbol Value Description

7 ADMODE

Reset value

1

9:8

10

31:11 -

-

OD

-

-

0

1

0

1

Selects Analog/Digital mode

Analog input mode

Digital functional mode

Reserved

Selects pseudo open-drain mode.

Standard GPIO output

Open-drain output

Reserved -

00

0

8.4.32 IOCON_PIO3_0

Table 137. IOCON_PIO3_0 register (IOCON_PIO3_0, address 0x4004 4084) bit description

Bit Symbol Value Description Reset value

2:0 FUNC 000

0x0

0x1

0x2

0x3

Selects pin function. All other values are reserved.

Selects function PIO3_0.

Selects function DTR.

Selects function CT16B0_MAT0.

4:3 MODE

Selects function TXD.

Selects function mode (on-chip pull-up/pull-down resistor control).

Inactive (no pull-down/pull-up resistor enabled).

10

5 HYS

0x0

0x1

0x2

0x3

Pull-down resistor enabled.

Pull-up resistor enabled.

Repeater mode.

Hysteresis.

0

9:6

10

31:11

-

-

OD

-

-

0

1

0

1

Disable.

Enable.

Reserved

Selects pseudo open-drain mode.

Standard GPIO output

Open-drain output

Reserved -

0011

0

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Chapter 8: LPC1100XL series: I/O configuration (IOCONFIG)

8.4.33 IOCON_PIO3_1

Table 138. IOCON_PIO3_1 register (IOCON_PIO3_1, address 0x4004 4088) bit description

Bit Symbol Value Description Reset value

2:0 FUNC 000

4:3 MODE

0x0

0x1

0x2

0x3

Selects pin function. All other values are reserved.

Selects function PIO3_1.

Selects function DSR.

Selects function CT16B0_MAT1.

Selects function RXD.

Selects function mode (on-chip pull-up/pull-down resistor control).

10

5

9:6

10

-

HYS

OD

-

0x0

0x1

0x2

0x3

0

1

Inactive (no pull-down/pull-up resistor enabled).

Pull-down resistor enabled.

Pull-up resistor enabled.

Repeater mode.

Hysteresis.

Disable.

Enable.

Reserved

0

0011

0

31:11 -

0

1

Selects pseudo open-drain mode.

Standard GPIO output

Open-drain output

Reserved -

8.4.34 IOCON_PIO2_3

Table 139. IOCON_PIO2_3 register (IOCON_PIO2_3, address 0x4004 408C) bit description

Bit Symbol Value Description Reset value

2:0 FUNC Selects pin function. All other values are reserved.

000

4:3 MODE

0x0

0x1

0x2

Selects function PIO2_3.

Selects function RI.

Selects function MOSI1.

Selects function mode (on-chip pull-up/pull-down resistor control).

Inactive (no pull-down/pull-up resistor enabled).

10

5 HYS

0x0

0x1

0x2

0x3

Pull-down resistor enabled.

Pull-up resistor enabled.

Repeater mode.

Hysteresis.

0

9:6 -

0

1

Disable.

Enable.

Reserved 0011

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Chapter 8: LPC1100XL series: I/O configuration (IOCONFIG)

Table 139. IOCON_PIO2_3 register (IOCON_PIO2_3, address 0x4004 408C) bit description

Bit Symbol Value Description Reset value

10 OD 0

31:11 -

0

1

Selects pseudo open-drain mode.

Standard GPIO output

Open-drain output

Reserved -

8.4.35 IOCON_SWDIO_PIO1_3

Table 140. IOCON_SWDIO_PIO1_3 register (IOCON_SWDIO_PIO1_3, address 0x4004 4090) bit description

Bit Symbol Value Description

2:0 FUNC

0x0

Selects pin function. All other values are reserved.

Selects function SWDIO.

Reset value

000

4:3 MODE

0x1

0x2

0x3

Selects function PIO1_3.

Selects function AD4.

Selects function CT32B1_MAT2.

Selects function mode (on-chip pull-up/pull-down resistor control).

Inactive (no pull-down/pull-up resistor enabled).

10

5 HYS

0x0

0x1

0x2

0x3

Pull-down resistor enabled.

Pull-up resistor enabled.

Repeater mode.

Hysteresis.

0

6

7

9:8

10

31:11

-

-

ADMODE

-

0

1

-

0

1

OD

-

0

1

Disable.

Enable.

Reserved

Selects Analog/Digital mode

Analog input mode

Digital functional mode

Reserved

Selects pseudo open-drain mode.

Standard GPIO output

Open-drain output

Reserved -

1

1

00

0

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8.4.36 IOCON_PIO1_4

Table 141. IOCON_PIO1_4 register (IOCON_PIO1_4, address 0x4004 4094) bit description

Bit Symbol Value Description Reset value

2:0 FUNC

0x0

0x1

0x2

Selects pin function. This pin functions as WAKEUP pin if the

LPC111x/LPC11Cxx is in Deep power-down mode regardless of the value of FUNC. All other values are reserved.

000

Selects function PIO1_4.

Selects function AD5.

4:3 MODE

Selects function CT32B1_MAT3.

Selects function mode (on-chip pull-up/pull-down resistor control).

Inactive (no pull-down/pull-up resistor enabled).

10

5 HYS

0x0

0x1

0x2

0x3

Pull-down resistor enabled.

Pull-up resistor enabled.

Repeater mode.

Hysteresis.

0

6

7

9:8

10

31:11

-

-

ADMODE

-

0

1

-

0

1

OD

-

0

1

Disable.

Enable.

Reserved

Selects Analog/Digital mode

Analog input mode

Digital functional mode

Reserved

Selects pseudo open-drain mode.

Standard GPIO output

Open-drain output

Reserved -

1

1

00

0

8.4.37 IOCON_PIO1_11

Table 142. IOCON_PIO1_11 register (IOCON_PIO1_11, address 0x4004 4098) bit description

Bit Symbol Value Description Reset value

2:0 FUNC 000

4:3 MODE

0x0

0x1

0x2

Selects pin function. All other values are reserved.

Selects function PIO1_11.

Selects function AD7.

Selects function CT32B1_CAP1.

Selects function mode (on-chip pull-up/pull-down resistor control).

10

0x0

0x1

0x2

0x3

Inactive (no pull-down/pull-up resistor enabled).

Pull-down resistor enabled.

Pull-up resistor enabled.

Repeater mode.

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Chapter 8: LPC1100XL series: I/O configuration (IOCONFIG)

Table 142. IOCON_PIO1_11 register (IOCON_PIO1_11, address 0x4004 4098) bit description

Bit Symbol Value Description Reset value

5 0

6

7

9:8

10

31:11 -

HYS

-

0

-

ADMODE

-

1

0

-

1

OD

0

-

1

Hysteresis.

Disable.

Enable.

Reserved

Selects Analog/Digital mode

Analog input mode

Digital functional mode

Reserved

Selects pseudo open-drain mode.

Standard GPIO output

Open-drain output

Reserved -

1

1

00

0

8.4.38 IOCON_PIO3_2

Table 143. IOCON_PIO3_2 register (IOCON_PIO3_2, address 0x4004 409C) bit description

Bit Symbol Value Description Reset value

2:0 FUNC Selects pin function. All other values are reserved.

000

4:3 MODE

0x0

0x1

0x2

0x3

Selects function PIO3_2.

Selects function DCD.

Selects function CT16B0_MAT2.

Selects function SCK1.

Selects function mode (on-chip pull-up/pull-down resistor control).

10

5

9:6

10

-

HYS

OD

-

0x0

0x1

0x2

0x3

0

1

Inactive (no pull-down/pull-up resistor enabled).

Pull-down resistor enabled.

Pull-up resistor enabled.

Repeater mode.

Hysteresis.

Disable.

Enable.

Reserved

0

0011

0

31:11 -

0

1

Selects pseudo open-drain mode.

Standard GPIO output

Open-drain output

Reserved -

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Chapter 8: LPC1100XL series: I/O configuration (IOCONFIG)

8.4.39 IOCON_PIO1_5

Table 144. IOCON_PIO1_5 register (IOCON_PIO1_5, address 0x4004 40A0) bit description

Bit Symbol Value Description Reset value

2:0 FUNC 000

0x0

0x1

0x2

Selects pin function. All other values are reserved.

Selects function PIO1_5.

Selects function RTS.

4:3 MODE

Selects function CT32B0_CAP0.

Selects function mode (on-chip pull-up/pull-down resistor control).

Inactive (no pull-down/pull-up resistor enabled).

10

5 HYS

0x0

0x1

0x2

0x3

Pull-down resistor enabled.

Pull-up resistor enabled.

Repeater mode.

Hysteresis.

0

9:6

10

31:11

-

-

OD

-

-

0

1

0

1

Disable.

Enable.

Reserved

Selects pseudo open-drain mode.

Standard GPIO output

Open-drain output

Reserved -

0011

0

8.4.40 IOCON_PIO1_6

Table 145. IOCON_PIO1_6 register (IOCON_PIO1_6, address 0x4004 40A4) bit description

Bit Symbol Value Description Reset value

2:0 FUNC 000

4:3 MODE

0x0

0x1

0x2

Selects pin function. All other values are reserved.

Selects function PIO1_6.

Selects function RXD.

Selects function CT32B0_MAT0.

Selects function mode (on-chip pull-up/pull-down resistor control).

10

5

9:6 -

HYS

-

0x0

0x1

0x2

0x3

0

1

Inactive (no pull-down/pull-up resistor enabled).

Pull-down resistor enabled.

Pull-up resistor enabled.

Repeater mode.

Hysteresis.

Disable.

Enable.

Reserved

0

0011

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Chapter 8: LPC1100XL series: I/O configuration (IOCONFIG)

Table 145. IOCON_PIO1_6 register (IOCON_PIO1_6, address 0x4004 40A4) bit description

Bit Symbol Value Description Reset value

10 OD 0

31:11 -

0

1

Selects pseudo open-drain mode.

Standard GPIO output

Open-drain output

Reserved -

8.4.41 IOCON_PIO1_7

Table 146. IOCON_PIO1_7 register (IOCON_PIO1_7, address 0x4004 40A8) bit description

Bit Symbol Value Description Reset value

2:0 FUNC Selects pin function. All other values are reserved.

000

4:3 MODE

0x0

0x1

0x2

Selects function PIO1_7.

Selects function TXD.

Selects function CT32B0_MAT1.

Selects function mode (on-chip pull-up/pull-down resistor control).

Inactive (no pull-down/pull-up resistor enabled).

10

5 HYS

0x0

0x1

0x2

0x3

Pull-down resistor enabled.

Pull-up resistor enabled.

Repeater mode.

Hysteresis.

0

9:6

10

31:11

-

-

OD

-

-

0

1

0

1

Disable.

Enable.

Reserved

Selects pseudo open-drain mode.

Standard GPIO output

Open-drain output

Reserved -

0011

0

8.4.42 IOCON_PIO3_3

Table 147. IOCON_PIO3_3 register (IOCON_PIO3_3, address 0x4004 40AC) bit description

Bit Symbol Value Description Reset value

2:0 FUNC 000

0x0

0x1

0x2

Selects pin function. All other values are reserved.

Selects function PIO3_3.

Selects function RI.

Selects function CT16B0_CAP0.

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Chapter 8: LPC1100XL series: I/O configuration (IOCONFIG)

Table 147. IOCON_PIO3_3 register (IOCON_PIO3_3, address 0x4004 40AC) bit description

Bit Symbol Value Description Reset value

4:3 MODE 10

5 HYS

0x0

0x1

0x2

0x3

Selects function mode (on-chip pull-up/pull-down resistor control).

Inactive (no pull-down/pull-up resistor enabled).

Pull-down resistor enabled.

Pull-up resistor enabled.

Repeater mode.

Hysteresis.

Disable.

0

9:6

10

-

OD

0

-

1 Enable.

Reserved

Selects pseudo open-drain mode.

Standard GPIO output

0011

0

31:11 -

0

-

1 Open-drain output

Reserved -

8.4.43 IOCON_SCK0_LOC

Table 148. IOCON SCK0 location register (IOCON_SCK0_LOC, address 0x4004 40B0) bit description

Bit Symbol Value Description

1:0 SCKLOC

Reset value

00

31:2 -

0x0

0x1

0x2

0x3

Selects pin location for SCK0 function.

Selects SCK0 function in pin location

SWCLK/PIO0_10/SCK0/CT16B0_MAT2 (see Table 130 ).

Selects SCK0 function in pin location PIO2_11/SCK0 (see

Table 132 ).

Selects SCK0 function in pin location PIO0_6/SCK0 (see

Table 123 ).

Reserved.

Reserved.

-

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Chapter 8: LPC1100XL series: I/O configuration (IOCONFIG)

8.4.44 IOCON_DSR_LOC

Table 149. IOCON DSR location register (IOCON_DSR_LOC, address 0x4004 40B4) bit description

Bit Symbol Value Description Reset value

1:0 DSRLOC

0x0

0x1

Selects pin location for DSR function.

Selects DSR function in pin location PIO2_1/DSR/SCK1 (see

Table 114 ).

00

Selects DSR function in pin location PIO3_1/DSR (see

Table 138 ).

Reserved.

31:2 -

0x2

-

0x3 Reserved.

Reserved.

-

8.4.45 IOCON_DCD_LOC

Table 150. IOCON DCD location register (IOCON_DCD_LOC, address 0x4004 40B8) bit description

Bit Symbol Value Description

1:0 DCDLOC

Reset value

00

0x0

0x1

0x2

Selects pin location for DCD function.

Selects DCD function in pin location PIO2_2/DCD/MISO1

(see Table 127 ).

Selects DCD function in pin location PIO3_2/DCD (see

Table 143 ).

Reserved.

31:2 -

0x3 Reserved.

Reserved.

-

8.4.46 IOCON_RI_LOC

Table 151. IOCON RI location register (IOCON_RI_LOC, address 0x4004 40BC) bit description

Bit Symbol Value Description

1:0 RILOC

0x0

Reset value

Selects pin location for RI function.

Selects RI function in pin location PIO2_3/RI/MOSI1 (see

Table 139 ).

Selects RI function in pin location PIO3_3/RI (see

Table 147

).

00

31:2 -

0x1

0x2

0x3

Reserved.

Reserved.

Reserved.

-

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Chapter 8: LPC1100XL series: I/O configuration (IOCONFIG)

8.4.47 IOCON_SSEL1_LOC

Table 152. IOCON SSEL1 location register (IOCON_SSEL1_LOC, address 0x4004 4018) bit description

Bit Symbol Value Description Reset value

1:0 SSEL1LOC 00

0x0

0x1

Selects pin location for SSEL1 function.

Selects SSEL1 function in pin location

PIO2_0/DTR/SSEL1 (see Table 107 ).

Selects SSEL1 function in pin location

PIO2_4/CT16B1_MAT1/SSEL1 (see Table 120 ).

31:2 -

0x2

0x3

Reserved.

Reserved.

Reserved.

-

8.4.48 IOCON_CT16B0_CAP0_LOC

Table 153. IOCON CT16B0_CAP0 location register (IOCON_CT16B0_CAP0_LOC, address

0x4004 40C0) bit description

Bit Symbol Value Description

1:0 CT16B0_CAP0LOC Selects pin location for CT16B0_CAP0 function.

Reset value

00

0x0

0x1

Selects CT16B0_CAP0 function in pin location

PIO0_2/SSEL0/CT16B0_CAP0 (see Table 111 ).

Selects CT16B0_CAP0 function in pin location

PIO3_3/RI/CT16B0 (see Table 147

).

31:2 -

0x2

0x3

Reserved.

Reserved.

Reserved.

-

8.4.49 IOCON_SCK1_LOC

Table 154. IOCON SCK1 location register (IOCON_SCK1_LOC, address 0x4004 40C4) bit description

Bit Symbol Value Description

1:0 SCK1LOC Selects pin location for SCK1 function.

Reset value

00

0x0

0x1

Selects SCK1 function in pin location PIO2_1/DSR/SCK1

(see

Table 114

).

Selects SCK1 function in pin location

PIO3_2/DCD/CT16B0_MAT2/SCK1 (see

Table 143

).

31:2 -

0x2

0x3

Reserved.

Reserved.

Reserved.

-

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Chapter 8: LPC1100XL series: I/O configuration (IOCONFIG)

8.4.50 IOCON_MISO1_LOC

Table 155. IOCON MISO1 location register (IOCON_MISO1_LOC, address 0x4004 40C8) bit description

Bit Symbol Value Description Reset value

1:0 MISO1LOC 00

0x0

0x1

Selects pin location for the MISO1 function.

Selects MISO1 function in pin location

PIO2_2/DCD/MISO1 (see Table 127

).

Selects MISO1 function in pin location

PIO1_10/AD6/CT16B1_MAT1/MISO1 (see Table 131 ).

Reserved.

31:2 -

0x2

-

0x3 Reserved.

Reserved.

-

8.4.51 IOCON_MOSI1_LOC

Table 156. IOCON MOSI1 location register (IOCON_MOSI1_LOC, address 0x4004 40CC) bit description

Bit Symbol Value Description

1:0 MOSI1LOC

Reset value

00

0x0

0x1

0x2

Selects pin location for the MOSI1 function.

Selects MOSI1 function in pin location PIO2_3/RI/MOSI1

(see

Table 139

).

Selects MOSI1 function in pin location

PIO1_9/CT16B1_MAT0/MOSI1 (see

Table 118

).

Reserved.

31:2 -

0x3 Reserved.

Reserved.

-

8.4.52 IOCON_CT32B0_CAP0_LOC

Table 157. IOCON CT32B0_CAP0 location register (IOCON_CT32B0_CAP0_LOC, address

0x4004 40D0) bit description

Bit Symbol Value Description

1:0 CT32B0_CAP0LOC

Reset value

00

0x0

Selects pin location for the CT32B0_CAP0 function.

Selects CT32B0_CAP0 function in pin location

PIO1_5/RTS/CT32B0_CAP0 (see

Table 144

).

0x1

31:2 -

0x2

0x3

Selects CT32B0_CAP0 function in pin location

PIO2_9/CT32B0_CAP0 (

Table 125

).

Reserved.

Reserved.

Reserved.

-

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Chapter 8: LPC1100XL series: I/O configuration (IOCONFIG)

8.4.53 IOCON_RXD_LOC

Table 158. IOCON RXD location register (IOCON_RXD_LOC, address 0x4004 40D4) bit description

Bit Symbol Value Description Reset value

1:0 RXDLOC 00

31:2 -

0x0

0x1

0x2

0x3

Selects pin location for the RXD function.

Selects RXD function in pin location

PIO1_6/RXD/CT32B0_MAT0 (see Table 145 ).

Selects RXD function in pin location

PIO2_7/CT32B0_MAT2/RXD (see Table 112 ).

Selects RXD function in pin location

PIO3_1/DSR/CT16B0_MAT1/RXD (see

Table 138

).

Selects RXD function in pin location

PIO3_4/CT16B0_CAP1/RXD (see

Table 119

).

Reserved.

-

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Chapter 9: LPC111x/LPC11Cxx Pin configuration (LPC1100,

LPC1100C, and LPC1100L series, HVQFN/LQFP packages)

Rev. 12.4 — 22 December 2016 User manual

9.1 How to read this chapter

Remark:

This chapter applies to parts in the LPC1100, LPC1100C, and LPC1100L series for LQFP and HVQFN packages.

The LPC111x are available in three packages: LQFP48 (LPC1113, LPC1114), and

HVQFN33 (LPC1111, LPC1112, LPC1113, LPC1114).

The LPC11Cxx parts are available in a LQFP48 package.

The LPC11D14 part is available as a dual-chip module in a LQFP100 package.

Table 159. LPC11(D)1x/LPC11Cxx pin configurations

Part LQFP48 HVQFN24

LPC1111

LPC1112

Pin configuration

Pin description

Pin configuration

Pin description -

-

-

-

-

-

Figure 18

Table 162

LPC1113

LPC1114

LPC11C12

LPC11C14

Pin configuration

Pin description

Pin configuration

Pin description

Pin configuration

Pin description

Pin configuration

Pin description

Figure 16

Table 160

Figure 16

Table 160

Figure 19

Table 160

Figure 19

Table 160

-

-

-

-

-

-

-

-

LPC11C22

LPC11C24

LPC11D14

Pin configuration

Pin description

Pin configuration

Pin description

Pin configuration

Pin description -

-

Figure 20

Table 163

Figure 20

Table 163

-

-

-

-

-

-

-

-

-

-

HVQFN33

Figure 17

Table 161

Figure 17

Table 161

Figure 17

Table 161

-

-

-

-

-

-

Figure 17

Table 161

-

-

-

-

-

-

-

-

-

-

-

-

-

-

LQFP100

-

-

Figure 21

Table 164

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Chapter 9: LPC111x/LPC11Cxx Pin configuration (LPC1100, LPC1100C,

9.2 LPC111x Pin configuration

PIO2_6

PIO2_0/DTR/SSEL1

1

2

RESET/PIO0_0

PIO0_1/CLKOUT/CT32B0_MAT2

3

4

V

SS

XTALIN

5

6

XTALOUT

V

DD

PIO1_8/CT16B1_CAP0

PIO0_2/SSEL0/CT16B0_CAP0

PIO2_7

PIO2_8

7

8

9

10

11

12

LPC1113FBD48/301

LPC1113FBD48/302

LPC1114FBD48/301

LPC1114FBD48/302

32

31

30

29

36

35

34

33

PIO3_0/DTR

R/PIO1_2/AD3/CT32B1_MAT1

R/PIO1_1/AD2/CT32B1_MAT0

R/PIO1_0/AD1/CT32B1_CAP0

R/PIO0_11/AD0/CT32B0_MAT3

PIO2_11/SCK0

PIO1_10/AD6/CT16B1_MAT1

SWCLK/PIO0_10/SCK0/CT16B0_MAT2

28

27

26

25

PIO0_9/MOSI0/CT16B0_MAT1

PIO0_8/MISO0/CT16B0_MAT0

PIO2_2/DCD/MISO1

PIO2_10

002aae697

Fig 16. Pin configuration LQFP48 package

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Chapter 9: LPC111x/LPC11Cxx Pin configuration (LPC1100, LPC1100C,

terminal 1 index area

PIO2_0/DTR

RESET/PIO0_0

PIO0_1/CLKOUT/CT32B0_MAT2

XTALIN

XTALOUT

V

DD

PIO1_8/CT16B1_CAP0

PIO0_2/SSEL0/CT16B0_CAP0

1

2

3

4

5

6

7

8

33 V

SS

24

23

22

21

20

19

18

17

R/PIO1_2/AD3/CT32B1_MAT1

R/PIO1_1/AD2/CT32B1_MAT0

R/PIO1_0/AD1/CT32B1_CAP0

R/PIO0_11/AD0/CT32B0_MAT3

PIO1_10/AD6/CT16B1_MAT1

SWCLK/PIO0_10/SCK0/CT16B0_MAT2

PIO0_9/MOSI0/CT16B0_MAT1

PIO0_8/MISO0/CT16B0_MAT0

002aae698

Fig 17. Pin configuration HVQFN33 package

Transparent top view terminal 1 index area

RESET/PIO0_0

PIO0_1

V

SS

XTALIN

V

DD

PIO1_8

3

4

5

6

1

2

LPC1112FHN24

18

17

16

15

14

13

PIO1_2

PIO1_1

PIO1_0

PIO0_11

PIO0_10

PIO0_9

002aah173

Transparent top view

Fig 18. Pin configuration HVQFN24 package

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Chapter 9: LPC111x/LPC11Cxx Pin configuration (LPC1100, LPC1100C,

9.3 LPC11Cxx Pin configuration

PIO2_6

PIO2_0/DTR/SSEL1

1

2

RESET/PIO0_0

PIO0_1/CLKOUT/CT32B0_MAT2

3

4

V

SS

XTALIN

5

6

XTALOUT

V

DD

PIO1_8/CT16B1_CAP0

PIO0_2/SSEL0/CT16B0_CAP0

PIO2_7

PIO2_8

7

8

9

10

11

12

LPC11C12FBD48/301

LPC11C14FBD48/301

32

31

30

29

36

35

34

33

28

27

26

25

PIO3_0/DTR

R/PIO1_2/AD3/CT32B1_MAT1

R/PIO1_1/AD2/CT32B1_MAT0

R/PIO1_0/AD1/CT32B1_CAP0

R/PIO0_11/AD0/CT32B0_MAT3

PIO2_11/SCK0

PIO1_10/AD6/CT16B1_MAT1

SWCLK/PIO0_10/SCK0/CT16B0_MAT2

PIO0_9/MOSI0/CT16B0_MAT1

PIO0_8/MISO0/CT16B0_MAT0

PIO2_2/DCD/MISO1

PIO2_10

002aaf266

Fig 19. Pin configuration LQFP48 package

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Chapter 9: LPC111x/LPC11Cxx Pin configuration (LPC1100, LPC1100C,

PIO2_6

PIO2_0/DTR/SSEL1

RESET/PIO0_0

PIO0_1/CLKOUT/CT32B0_MAT2

V

SS

XTALIN

5

6

XTALOUT

V

DD

PIO1_8/CT16B1_CAP0

PIO0_2/SSEL0/CT16B0_CAP0

PIO2_7

PIO2_8

7

8

9

10

11

12

3

4

1

2

LPC11C22FBD48/301

LPC11C24FBD48/301

32

31

30

29

36

35

34

33

28

27

26

25

PIO3_0/DTR

R/PIO1_2/AD3/CT32B1_MAT1

R/PIO1_1/AD2/CT32B1_MAT0

R/PIO1_0/AD1/CT32B1_CAP0

R/PIO0_11/AD0/CT32B0_MAT3

PIO2_11/SCK0

PIO1_10/AD6/CT16B1_MAT1

SWCLK/PIO0_10/SCK0/CT16B0_MAT2

PIO0_9/MOSI0/CT16B0_MAT1

PIO0_8/MISO0/CT16B0_MAT0

PIO2_2/DCD/MISO1

PIO2_10

002aaf909

Fig 20. Pin configuration (LPC11C22/C24)

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Chapter 9: LPC111x/LPC11Cxx Pin configuration (LPC1100, LPC1100C,

9.4 LPC11D14 Pin configuration

PIO1_7

PIO3_3 n.c.

PIO2_6

PIO2_0

RESET/PIO0_0

PIO0_1

V

SS

XTALIN

XTALOUT

V

DD

PIO1_8

PIO0_2

PIO2_7

PIO2_8

PIO2_1

PIO0_3

PIO0_4

17

18

PIO0_5 19

13

14

15

16

9

10

11

12

7

8

5

6

3

4

1

2

PIO1_9

PIO3_4

PIO2_4

PIO2_5

20

21

22

23

PIO3_5

PIO0_6

24

25

Fig 21. Pin configuration LQFP100 package

LPC11D14FBD100/302

S17

S16

S15

S14

S21

S20

S19

S18

S25

S24

S23

S22

S29

S28

S27

S26

59

58

S13

S12

57 S11

56

55

54

53

S10

S9

S8

S7

52 S6

51 S5

63

62

61

60

67

66

65

64

71

70

69

68

75

74

73

72

002aag450

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Chapter 9: LPC111x/LPC11Cxx Pin configuration (LPC1100, LPC1100C,

9.5 LPC111x/LPC11Cxx Pin description

Table 160. LPC1113/14 and LPC11C12/C14 pin description table (LQFP48 package)

Symbol

PIO0_0 to PIO0_11

RESET/PIO0_0

Pin

3

[1][2]

I

Type

I/O

Description

Port 0 —

Port 0 is a 12-bit I/O port with individual direction and function controls for each bit. The operation of port 0 pins depends on the function selected through the IOCONFIG register block.

RESET —

External reset input: A LOW on this pin resets the device, causing I/O ports and peripherals to take on their default states, and processor execution to begin at address 0.

In deep power-down mode, this pin must be pulled HIGH externally. The

RESET pin can be left unconnected or be used as a GPIO pin if an external

RESET function is not needed.

PIO0_1/CLKOUT/

CT32B0_MAT2

4

[3][2]

I/O

I/O

PIO0_0 —

General purpose digital input/output pin.

PIO0_1 —

General purpose digital input/output pin. A LOW level on this pin during reset starts the flash ISP command handler via UART (if PIO0_3 is

HIGH) or via C_CAN (if PIO0_3 is LOW).

PIO0_2/SSEL0/

CT16B0_CAP0

PIO0_3

PIO0_4/SCL

10

14

15

[3][2]

[3][2]

[4][2]

O

O

I/O

O

I

I/O

I/O

I/O

CLKOUT —

PIO0_2 —

SSEL0 —

Clockout pin.

CT32B0_MAT2 —

Match output 2 for 32-bit timer 0.

General purpose digital input/output pin.

Slave Select for SPI0.

CT16B0_CAP0 —

Capture input 0 for 16-bit timer 0.

PIO0_3 —

General purpose digital input/output pin. This pin is monitored during reset: Together with a LOW level on pin PIO0_1, a LOW level starts the flash ISP command handler via C_CAN and a HIGH level starts the flash ISP command handler via UART.

PIO0_4 —

General purpose digital input/output pin (open-drain).

SCL —

I

2

C-bus, open-drain clock input/output. High-current sink only if I

2

C

Fast-mode Plus is selected in the I/O configuration register.

PIO0_5/SDA

16

[4][2]

I/O

I/O

PIO0_6/SCK0

PIO0_7/CTS

22

23

[3][2]

[3][2]

I/O

I/O

I/O

PIO0_5 —

General purpose digital input/output pin (open-drain).

SDA —

I

2

C-bus, open-drain data input/output. High-current sink only if I

2

C

Fast-mode Plus is selected in the I/O configuration register.

PIO0_6 —

General purpose digital input/output pin.

SCK0 —

Serial clock for SPI0.

PIO0_7 —

General purpose digital input/output pin (high-current output driver).

CTS —

Clear To Send input for UART.

PIO0_8/MISO0/

CT16B0_MAT0

PIO0_9/MOSI0/

CT16B0_MAT1

SWCLK/PIO0_10/

SCK0/CT16B0_MAT2

27

28

29

[3][2]

[3][2]

[3][2]

I

I

I/O

I/O

O

I/O

I/O

O

I/O

I/O

O

PIO0_8 —

MISO0 —

PIO0_9 —

MOSI0 —

General purpose digital input/output pin.

Master In Slave Out for SPI0.

CT16B0_MAT0 —

CT16B0_MAT1 —

Match output 0 for 16-bit timer 0.

General purpose digital input/output pin.

Master Out Slave In for SPI0.

Match output 1 for 16-bit timer 0.

SWCLK —

Serial wire clock.

PIO0_10 —

General purpose digital input/output pin.

SCK0 —

Serial clock for SPI0.

CT16B0_MAT2 —

Match output 2 for 16-bit timer 0.

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Chapter 9: LPC111x/LPC11Cxx Pin configuration (LPC1100, LPC1100C,

Table 160. LPC1113/14 and LPC11C12/C14 pin description table (LQFP48 package)

…continued

Symbol

R/PIO0_11/

AD0/CT32B0_MAT3

Pin

32

[5][2]

I

Type Description

R —

Reserved. Configure for an alternate function in the IOCONFIG block.

I

I/O

PIO0_11 —

General purpose digital input/output pin.

AD0 —

A/D converter, input 0.

PIO1_0 to PIO1_11

O

I/O

CT32B0_MAT3 —

Match output 3 for 32-bit timer 0.

Port 1 —

Port 1 is a 12-bit I/O port with individual direction and function controls for each bit. The operation of port 1 pins depends on the function selected through the IOCONFIG register block.

R/PIO1_0/

AD1/CT32B1_CAP0

33

[5][2]

I

I

I

I/O

R —

Reserved. Configure for an alternate function in the IOCONFIG block.

PIO1_0 —

AD1 —

General purpose digital input/output pin.

A/D converter, input 1.

CT32B1_CAP0 —

Capture input 0 for 32-bit timer 1.

R/PIO1_1/

AD2/CT32B1_MAT0

34

[5]

O

I/O

I

O

R —

Reserved. Configure for an alternate function in the IOCONFIG block.

PIO1_1 —

AD2 —

General purpose digital input/output pin.

A/D converter, input 2.

CT32B1_MAT0 —

Match output 0 for 32-bit timer 1.

R/PIO1_2/

AD3/CT32B1_MAT1

35

[5]

I

I/O

I

O

R —

Reserved. Configure for an alternate function in the IOCONFIG block.

PIO1_2 —

AD3 —

General purpose digital input/output pin.

A/D converter, input 3.

CT32B1_MAT1 —

Match output 1 for 32-bit timer 1.

SWDIO/PIO1_3/AD4/

CT32B1_MAT2

39

[5]

PIO1_4/AD5/

CT32B1_MAT3/WAKEUP

40

[5]

I/O

I/O

I

O

I/O

SWDIO —

Serial wire debug input/output.

PIO1_3 —

General purpose digital input/output pin.

AD4 —

A/D converter, input 4.

CT32B1_MAT2 —

Match output 2 for 32-bit timer 1.

PIO1_4 —

General purpose digital input/output pin. In Deep power-down mode, this pin serves as the Deep power-down mode wake-up pin with 20 ns glitch filter. Pull this pin HIGH externally before entering Deep power-down mode. Pull this pin LOW to exit Deep power-down mode. A

LOW-going pulse as short as 50 ns wakes up the part.

AD5 —

A/D converter, input 5.

PIO1_5/RTS/

CT32B0_CAP0

PIO1_6/RXD/

CT32B0_MAT0

PIO1_7/TXD/

CT32B0_MAT1

PIO1_8/CT16B1_CAP0

45

46

47

9

[3]

[3]

[3]

[3]

I

I

I

O

I/O

O

I

I/O

O

I/O

O

O

I/O

CT32B1_MAT3 —

PIO1_5 —

Match output 3 for 32-bit timer 1.

General purpose digital input/output pin.

RTS —

Request To Send output for UART.

CT32B0_CAP0 —

Capture input 0 for 32-bit timer 0.

PIO1_6 —

RXD —

CT32B0_MAT0 —

Match output 0 for 32-bit timer 0.

PIO1_7 —

General purpose digital input/output pin.

TXD —

General purpose digital input/output pin.

Receiver input for UART.

Transmitter output for UART.

CT32B0_MAT1 —

Match output 1 for 32-bit timer 0.

PIO1_8 —

General purpose digital input/output pin.

CT16B1_CAP0 —

Capture input 0 for 16-bit timer 1.

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Chapter 9: LPC111x/LPC11Cxx Pin configuration (LPC1100, LPC1100C,

Table 160. LPC1113/14 and LPC11C12/C14 pin description table (LQFP48 package)

…continued

Symbol

PIO1_9/CT16B1_MAT0

Pin

17

[3]

Type

I/O

Description

PIO1_9 —

General purpose digital input/output pin.

PIO1_10/AD6/

CT16B1_MAT1

30

[5]

O

I/O

I

O

CT16B1_MAT0 —

PIO1_10 —

AD6 —

Match output 0 for 16-bit timer 1.

General purpose digital input/output pin.

A/D converter, input 6.

CT16B1_MAT1 —

Match output 1 for 16-bit timer 1.

PIO1_11/AD7

42

[5]

PIO2_0 to PIO2_11

PIO2_0/DTR/SSEL1

2

[3]

I

I/O

I/O

PIO1_11 —

General purpose digital input/output pin.

AD7 —

A/D converter, input 7.

Port 2 —

Port 2 is a 12-bit I/O port with individual direction and function controls for each bit. The operation of port 2 pins depends on the function selected through the IOCONFIG register block.

PIO2_0 —

General purpose digital input/output pin.

PIO2_1/DSR/SCK1

PIO2_2/DCD/MISO1

PIO2_3/RI/MOSI1

PIO2_4

PIO2_4

PIO2_5

PIO2_5

PIO2_6

PIO2_7

PIO2_8

PIO2_9

PIO2_10

PIO2_11/SCK0

PIO3_0 to PIO3_5

13

26

38

[3]

[3]

[3]

19

[3]

18

[3]

20

[3]

21

[3]

1

[3]

11

[3]

12

[3]

24

[3]

25

[3]

31

[3]

I

I

I/O

O

O

I/O

I/O

I/O

I/O

I

I/O

I/O

I/O

I/O

I/O

I/O

I/O

I/O

I/O

I/O

I/O

I/O

I/O

I/O

DTR —

Data Terminal Ready output for UART.

SSEL1 —

SCK1 —

Serial clock for SPI1.

PIO2_2 —

PIO2_3 —

RI —

PIO2_4 —

PIO2_5 —

PIO2_5 —

PIO2_6 —

PIO2_7 —

PIO2_8 —

PIO2_9 —

Slave Select for SPI1.

PIO2_1 —

General purpose digital input/output pin.

DSR —

Data Set Ready input for UART.

General purpose digital input/output pin.

DCD —

Data Carrier Detect input for UART.

MISO1 —

Master In Slave Out for SPI1.

General purpose digital input/output pin.

Ring Indicator input for UART.

MOSI1 —

Master Out Slave In for SPI1.

PIO2_4 —

General purpose digital input/output pin. (LPC1113/14 only).

General purpose digital input/output pin. (LPC11C12/C14 only).

General purpose digital input/output pin. LPC1113/14 only).

General purpose digital input/output pin. (LPC11C12/C14 only).

General purpose digital input/output pin.

General purpose digital input/output pin.

General purpose digital input/output pin.

General purpose digital input/output pin.

PIO2_10 —

PIO2_11 —

SCK0 —

General purpose digital input/output pin.

General purpose digital input/output pin.

Serial clock for SPI0.

Port 3 —

Port 3 is a 12-bit I/O port with individual direction and function controls for each bit. The operation of port 3 pins depends on the function selected through the IOCONFIG register block. Pins PIO3_6 to PIO3_11 are not available.

PIO3_0/DTR

36

[3]

PIO3_1/DSR

37

[3]

I/O

O

I

I/O

PIO3_0 —

General purpose digital input/output pin.

DTR —

Data Terminal Ready output for UART.

PIO3_1 —

General purpose digital input/output pin.

DSR —

Data Set Ready input for UART.

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Chapter 9: LPC111x/LPC11Cxx Pin configuration (LPC1100, LPC1100C,

Table 160. LPC1113/14 and LPC11C12/C14 pin description table (LQFP48 package)

…continued

Symbol

PIO3_2/DCD

Pin

43

[3]

Type

I/O

Description

PIO3_2 —

General purpose digital input/output pin.

PIO3_3/RI

PIO3_4

PIO3_5

CAN_RXD

CAN_TXD

V

XTALIN

XTALOUT

V

DD

SS

48

18

[3]

21

[3]

19

[6]

20

[6]

8; 44

6

7

[3]

[7]

[7]

5; 41 I

I

I

I

I

I/O

I

I/O

I/O

O

O

DCD —

RI —

Data Carrier Detect input for UART.

PIO3_3 —

Ring Indicator input for UART.

PIO3_4 —

PIO3_5 —

General purpose digital input/output pin.

General purpose digital input/output pin. (LPC1113/14 only).

Input to the oscillator circuit and internal clock generator circuits. Input voltage must not exceed 1.8 V.

Output from the oscillator amplifier.

Ground.

General purpose digital input/output pin. (LPC1113/14 only).

CAN_RXD —

C_CAN receive data input. (LPC11C12/14 only).

CAN_TXD —

C_CAN transmit data output. (LPC11C12/14 only).

3.3 V supply voltage to the internal regulator, the external rail, and the ADC.

Also used as the ADC reference voltage.

[1]

[2]

[3]

[4]

[5]

[6]

[7]

5 V tolerant pad. RESET functionality is not available in Deep power-down mode. Use the WAKEUP pin to reset the chip and wake up from Deep power-down mode.

Serves as Deep-sleep wake-up input pin to the start logic independently of selected pin function (see the

LPC111x/11C1x user manual

).

5 V tolerant pad providing digital I/O functions with configurable pull-up/pull-down resistors and configurable hysteresis.

I

2

C-bus pads compliant with the I

2

C-bus specification for I

2

C standard mode and I

2

C Fast-mode Plus. The pin requires an external pull-up to provide output functionality. When power is switched off, this pin is floating and does not disturb the I2C lines. Open-drain configuration applies to all functions on this pin.

5 V tolerant pad providing digital I/O functions with configurable pull-up/pull-down resistors, configurable hysteresis, and analog input.

When configured as a ADC input, digital section of the pad is disabled and the pin is not 5 V tolerant.

5 V tolerant digital I/O pad without pull-up/pull-down resistors.

When the system oscillator is not used, connect XTALIN and XTALOUT as follows: XTALIN can be left floating or can be grounded

(grounding is preferred to reduce susceptibility to noise). XTALOUT should be left floating.

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UM10398

Chapter 9: LPC111x/LPC11Cxx Pin configuration (LPC1100, LPC1100C,

Table 161. LPC1111/12/13/14 pin description table (HVQFN33 package)

Symbol

PIO0_0 to PIO0_11

Pin Type

I/O

Description

Port 0 —

Port 0 is a 12-bit I/O port with individual direction and function controls for each bit. The operation of port 0 pins depends on the function selected through the IOCONFIG register block.

RESET/PIO0_0

2

[1][2]

I

PIO0_1/CLKOUT/

CT32B0_MAT2

3

[3][2]

I/O

I/O

RESET —

External reset input: A LOW on this pin resets the device, causing I/O ports and peripherals to take on their default states, and processor execution to begin at address 0.

In deep power-down mode, this pin must be pulled HIGH externally. The

RESET pin can be left unconnected or be used as a GPIO pin if an external

RESET function is not needed.

PIO0_0 —

General purpose digital input/output pin.

PIO0_1 —

General purpose digital input/output pin. A LOW level on this pin during reset starts the ISP command handler.

PIO0_2/SSEL0/

CT16B0_CAP0

8

[3][2]

O

O

I/O

O

CLKOUT —

PIO0_2 —

SSEL0 —

Clock out pin.

CT32B0_MAT2 —

Match output 2 for 32-bit timer 0.

General purpose digital input/output pin.

Slave select for SPI0.

PIO0_3

PIO0_4/SCL

PIO0_5/SDA

9

[3][2]

10

11

[4][2]

[4][2]

I

I/O

I/O

I/O

I/O

I/O

CT16B0_CAP0 —

Capture input 0 for 16-bit timer 0.

PIO0_3 —

General purpose digital input/output pin.

PIO0_4 —

General purpose digital input/output pin (open-drain).

SCL —

I

2

C-bus, open-drain clock input/output. High-current sink only if I

2

C

Fast-mode Plus is selected in the I/O configuration register.

PIO0_5 —

General purpose digital input/output pin (open-drain).

SDA —

I

2

C-bus, open-drain data input/output. High-current sink only if I

2

C

Fast-mode Plus is selected in the I/O configuration register.

PIO0_6/SCK0 15

[3][2]

PIO0_7/CTS

PIO0_8/MISO0/

CT16B0_MAT0

PIO0_9/MOSI0/

CT16B0_MAT1

SWCLK/PIO0_10/SCK0/

CT16B0_MAT2

R/PIO0_11/AD0/

CT32B0_MAT3

16

17

18

19

21

[3][2]

[3][2]

[3][2]

[3][2]

[5][2]

I

I

I/O

I/O

I/O

I/O

I/O

O

I/O

I/O

I

O

I/O

I/O

O

I

I/O

O

PIO0_6 —

General purpose digital input/output pin.

SCK0 —

Serial clock for SPI0.

PIO0_7 —

General purpose digital input/output pin (high-current output driver).

CTS —

Clear To Send input for UART.

PIO0_8 —

General purpose digital input/output pin.

MISO0 —

Master In Slave Out for SPI0.

CT16B0_MAT0 —

Match output 0 for 16-bit timer 0.

PIO0_9 —

MOSI0 —

Master Out Slave In for SPI0.

CT16B0_MAT1 —

SWCLK —

General purpose digital input/output pin.

Match output 1 for 16-bit timer 0.

Serial wire clock.

PIO0_10 —

General purpose digital input/output pin.

SCK0 —

Serial clock for SPI0.

CT16B0_MAT2 —

Match output 2 for 16-bit timer 0.

R —

Reserved. Configure for an alternate function in the IOCONFIG block.

PIO0_11 —

General purpose digital input/output pin.

AD0 —

A/D converter, input 0.

CT32B0_MAT3 —

Match output 3 for 32-bit timer 0.

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UM10398

Chapter 9: LPC111x/LPC11Cxx Pin configuration (LPC1100, LPC1100C,

Table 161. LPC1111/12/13/14 pin description table (HVQFN33 package)

…continued

Symbol

PIO1_0 to PIO1_11

Pin Type

I/O

Description

Port 1 —

Port 1 is a 12-bit I/O port with individual direction and function controls for each bit. The operation of port 1 pins depends on the function selected through the IOCONFIG register block.

R/PIO1_0/AD1/

CT32B1_CAP0

22

[5][2]

I

I/O

R —

Reserved. Configure for an alternate function in the IOCONFIG block.

PIO1_0 —

General purpose digital input/output pin.

R/PIO1_1/AD2/

CT32B1_MAT0

23

[5]

I

I

O

I/O

AD1 —

R —

A/D converter, input 1.

CT32B1_CAP0 —

Capture input 0 for 32-bit timer 1.

Reserved. Configure for an alternate function in the IOCONFIG block.

PIO1_1 —

General purpose digital input/output pin.

R/PIO1_2/AD3/

CT32B1_MAT1

SWDIO/PIO1_3/AD4/

CT32B1_MAT2

PIO1_4/AD5/

CT32B1_MAT3/WAKEUP

24

25

26

[5]

[5]

[5]

I

O

I/O

I/O

I

O

I

I/O

I

O

I/O

AD2 —

R —

AD3 —

AD4 —

A/D converter, input 2.

CT32B1_MAT0 —

SWDIO —

PIO1_3 —

Match output 0 for 32-bit timer 1.

Reserved. Configure for an alternate function in the IOCONFIG block.

PIO1_2 —

General purpose digital input/output pin.

A/D converter, input 3.

CT32B1_MAT1 —

Match output 1 for 32-bit timer 1.

Serial wire debug input/output.

General purpose digital input/output pin.

A/D converter, input 4.

CT32B1_MAT2 —

Match output 2 for 32-bit timer 1.

PIO1_4 —

General purpose digital input/output pin. In Deep power-down mode, this pin serves as the Deep power-down mode wake-up pin with 20 ns glitch filter. Pull this pin HIGH externally before entering Deep power-down mode. Pull this pin LOW to exit Deep power-down mode. A

LOW-going pulse as short as 50 ns wakes up the part.

AD5 —

A/D converter, input 5.

PIO1_5/RTS/

CT32B0_CAP0

PIO1_6/RXD/

CT32B0_MAT0

PIO1_7/TXD/

CT32B0_MAT1

PIO1_8/CT16B1_CAP0

PIO1_9/CT16B1_MAT0

PIO1_10/AD6/

CT16B1_MAT1

30

31

32

7

[3]

12

20

[3]

[3]

[3]

[3]

[5]

I

I

I/O

I/O

O

O

I/O

O

O

I

O

I/O

I

O

I

I/O

I/O

O

CT32B1_MAT3 —

PIO1_5 —

RTS —

General purpose digital input/output pin.

Request To Send output for UART.

CT32B0_CAP0 —

PIO1_6 —

RXD —

CT32B0_MAT0 —

Match output 0 for 32-bit timer 0.

PIO1_7 —

General purpose digital input/output pin.

TXD —

Match output 3 for 32-bit timer 1.

Capture input 0 for 32-bit timer 0.

General purpose digital input/output pin.

Receiver input for UART.

Transmitter output for UART.

CT32B0_MAT1 —

PIO1_8 —

CT16B1_CAP0 —

PIO1_9 —

CT16B1_MAT0 —

Match output 1 for 32-bit timer 0.

General purpose digital input/output pin.

Capture input 0 for 16-bit timer 1.

General purpose digital input/output pin.

Match output 0 for 16-bit timer 1.

PIO1_10 —

General purpose digital input/output pin.

AD6 —

A/D converter, input 6.

CT16B1_MAT1 —

Match output 1 for 16-bit timer 1.

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UM10398

Chapter 9: LPC111x/LPC11Cxx Pin configuration (LPC1100, LPC1100C,

Table 161. LPC1111/12/13/14 pin description table (HVQFN33 package)

…continued

Symbol

PIO1_11/AD7

Pin

27

[5]

Type

I/O

Description

PIO1_11 —

General purpose digital input/output pin.

PIO2_0

PIO2_0/DTR

PIO3_0 to PIO3_5

PIO3_2

PIO3_4

PIO3_5

V

DD

1

[3]

28

[3]

13

[3]

14

[3]

6; 29 I

I

I/O

I/O

O

I/O

I/O

I/O

I/O

AD7 —

A/D converter, input 7.

Port 2 —

Port 2 is a 12-bit I/O port with individual direction and function controls for each bit. The operation of port 2 pins depends on the function selected through the IOCONFIG register block. Pins PIO2_1 to PIO2_11 are not available.

PIO2_0 —

General purpose digital input/output pin.

DTR —

Data Terminal Ready output for UART.

Port 3 —

Port 3 is a 12-bit I/O port with individual direction and function controls for each bit. The operation of port 3 pins depends on the function selected through the IOCONFIG register block. Pins PIO3_0, PIO3_1,

PIO3_3 and PIO3_6 to PIO3_11 are not available.

PIO3_2 —

General purpose digital input/output pin.

PIO3_4 —

General purpose digital input/output pin.

PIO3_5 —

General purpose digital input/output pin.

XTALIN

XTALOUT

V

SS

4

5

[6]

[6]

33 -

I

O

3.3 V supply voltage to the internal regulator, the external rail, and the ADC.

Also used as the ADC reference voltage.

Input to the oscillator circuit and internal clock generator circuits. Input voltage must not exceed 1.8 V.

Output from the oscillator amplifier.

Thermal pad. Connect to ground.

[1]

[2]

[3]

[4]

[5]

[6]

5 V tolerant pad. RESET functionality is not available in Deep power-down mode. Use the WAKEUP pin to reset the chip and wake up from Deep power-down mode.

Serves as Deep-sleep wake-up input pin to the start logic independently of selected pin function (see the

LPC111x/11C1x user manual

).

5 V tolerant pad providing digital I/O functions with configurable pull-up/pull-down resistors and configurable hysteresis.

I

2

C-bus pads compliant with the I

2

C-bus specification for I

2

C standard mode and I

2

C Fast-mode Plus. The pin requires an external pull-up to provide output functionality. When power is switched off, this pin is floating and does not disturb the I2C lines. Open-drain configuration applies to all functions on this pin.

5 V tolerant pad providing digital I/O functions with configurable pull-up/pull-down resistors, configurable hysteresis, and analog input.

When configured as a ADC input, digital section of the pad is disabled, and the pin is not 5 V tolerant.

When the system oscillator is not used, connect XTALIN and XTALOUT as follows: XTALIN can be left floating or can be grounded

(grounding is preferred to reduce susceptibility to noise). XTALOUT should be left floating.

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UM10398

Chapter 9: LPC111x/LPC11Cxx Pin configuration (LPC1100, LPC1100C,

Table 162. LPC1112FHN24 Pin description table (HVQFN24 package)

Symbol

RESET/PIO0_0

HVQFN pin

1

[1]

Start logic input

yes I

Type Reset state

[1]

I; PU

Description

PIO0_1/CLKOUT/

CT32B0_MAT2

2

[3]

yes

I/O

I/O

O -

-

I; PU

RESET —

External reset input with 20 ns glitch filter. A

LOW-going pulse as short as 50 ns on this pin resets the device, causing I/O ports and peripherals to take on their default states, and processor execution to begin at address 0.

In deep power-down mode, this pin must be pulled HIGH externally. The RESET pin can be left unconnected or be used as a GPIO pin if an external RESET function is not needed.

PIO0_0 —

General purpose digital input/output pin with 10 ns glitch filter.

PIO0_1 —

General purpose digital input/output pin. A LOW level on this pin during reset starts the ISP command handler.

CLKOUT —

Clockout pin.

PIO0_2/SSEL0/

CT16B0_CAP0

PIO0_4/SCL

PIO0_5/SDA

7

8

9

[3]

[4]

[4]

yes yes yes

O

I/O

I

I/O

I/O

I/O

I/O

I/O -

-

-

-

-

I; PU

I; IA

I; IA

CT32B0_MAT2 —

PIO0_2 —

SSEL0 —

Match output 2 for 32-bit timer 0.

General purpose digital input/output pin.

Slave Select for SPI0.

CT16B0_CAP0 —

Capture input 0 for 16-bit timer 0.

PIO0_4 —

General purpose digital input/output pin

(open-drain).

SCL —

I

2

C-bus, open-drain clock input/output. High-current sink only if I

2

C Fast-mode Plus is selected in the I/O configuration register.

PIO0_5 —

General purpose digital input/output pin

(open-drain).

SDA —

I

2

C-bus, open-drain data input/output. High-current sink only if I

2

C Fast-mode Plus is selected in the I/O configuration register.

PIO0_6/SCK0 10

[3]

yes

PIO0_7/CTS 11

[3]

yes

I/O

I/O

I/O

-

I; PU

I; PU

PIO0_6 —

General purpose digital input/output pin.

SCK0 —

Serial clock for SPI0.

PIO0_7 —

General purpose digital input/output pin

(high-current output driver).

PIO0_8/MISO0/

CT16B0_MAT0

PIO0_9/MOSI0/

CT16B0_MAT1

SWCLK/PIO0_10/

SCK0/

CT16B0_MAT2

12

13

14

[3]

[3]

[3]

yes yes yes

I/O

I/O

I

O

I

I/O

I/O

O

I/O

I/O

O

-

-

-

-

-

-

-

-

I; PU

I; PU

I; PU

CTS —

Clear To Send input for UART.

PIO0_8 —

MISO0 —

PIO0_9 —

MOSI0 —

SWCLK —

SCK0 —

General purpose digital input/output pin.

Master In Slave Out for SPI0.

CT16B0_MAT0 —

PIO0_10 —

Match output 0 for 16-bit timer 0.

General purpose digital input/output pin.

Master Out Slave In for SPI0.

CT16B0_MAT1 —

Match output 1 for 16-bit timer 0.

Serial wire clock.

General purpose digital input/output pin.

Serial clock for SPI0.

CT16B0_MAT2 —

Match output 2 for 16-bit timer 0.

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UM10398

Chapter 9: LPC111x/LPC11Cxx Pin configuration (LPC1100, LPC1100C,

Table 162. LPC1112FHN24 Pin description table (HVQFN24 package)

Symbol

R/PIO0_11/

AD0/CT32B0_MAT3

HVQFN pin

15

[5]

Start logic input

yes I

Type

I/O -

Reset state

[1]

I; PU

Description

R —

Reserved. Configure for an alternate function in the

IOCONFIG block.

PIO0_11 —

General purpose digital input/output pin.

R/PIO1_0/

AD1/CT32B1_CAP0

16

[5]

yes I

I

O -

-

I; PU

AD0 —

R —

A/D converter, input 0.

CT32B0_MAT3 —

Match output 3 for 32-bit timer 0.

Reserved. Configure for an alternate function in the

IOCONFIG block.

R/PIO1_1/

AD2/CT32B1_MAT0

17

[5]

no

I

I/O

I

O

-

-

-

I; PU

PIO1_0 —

General purpose digital input/output pin.

AD1 —

A/D converter, input 1.

CT32B1_CAP0 —

Capture input 0 for 32-bit timer 1.

R —

Reserved. Configure for an alternate function in the

IOCONFIG block.

PIO1_1 —

General purpose digital input/output pin.

R/PIO1_2/

AD3/CT32B1_MAT1

SWDIO/PIO1_3/

AD4/CT32B1_MAT2

PIO1_4/AD5/

CT32B1_MAT3/

WAKEUP

18

19

20

[5]

[5]

[5]

no no no

I

I

I/O

I

O

I/O

O

I/O

I

I/O

O

I/O

-

-

-

-

-

-

-

-

-

I; PU

I; PU

I; PU

AD2 —

CT32B1_MAT0 —

R —

A/D converter, input 2.

Reserved. Configure for an alternate function in the

IOCONFIG block.

Match output 0 for 32-bit timer 1.

PIO1_2 —

General purpose digital input/output pin.

AD3 —

A/D converter, input 3.

CT32B1_MAT1 —

Match output 1 for 32-bit timer 1.

SWDIO —

Serial wire debug input/output.

PIO1_3 —

General purpose digital input/output pin.

AD4 —

A/D converter, input 4.

CT32B1_MAT2 —

Match output 2 for 32-bit timer 1.

PIO1_4 —

General purpose digital input/output pin with 10 ns glitch filter. In Deep power-down mode, this pin serves as the

Deep power-down mode wake-up pin with 20 ns glitch filter.

Pull this pin HIGH externally before entering Deep power-down mode. Pull this pin LOW to exit Deep power-down mode. A

LOW-going pulse as short as 50 ns wakes up the part.

AD5 —

A/D converter, input 5.

PIO1_6/RXD/

CT32B0_MAT0

PIO1_7/TXD/

CT32B0_MAT1

PIO1_8/

CT16B1_CAP0

23

24

6

[3]

[3]

[3]

no no no

I

I

O

I/O

I

O

I/O

O

O

I/O

-

-

-

-

I; PU

-

-

-

I; PU

I; PU

CT32B1_MAT3 —

PIO1_6 —

RXD —

CT32B0_MAT0 —

PIO1_7 —

TXD —

Match output 3 for 32-bit timer 1.

General purpose digital input/output pin.

Receiver input for UART.

Match output 0 for 32-bit timer 0.

General purpose digital input/output pin.

Transmitter output for UART.

CT32B0_MAT1 —

Match output 1 for 32-bit timer 0.

PIO1_8 —

General purpose digital input/output pin.

CT16B1_CAP0 —

Capture input 0 for 16-bit timer 1.

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NXP Semiconductors

UM10398

Chapter 9: LPC111x/LPC11Cxx Pin configuration (LPC1100, LPC1100C,

Table 162. LPC1112FHN24 Pin description table (HVQFN24 package)

Symbol

XTALIN

HVQFN pin

4

[7]

-

Start logic input

I

Type

-

Reset state

[1]

Description

V

V

DD

SS

5; 22

3; 21 -

-

I

I

-

-

Input to the oscillator circuit and internal clock generator circuits. Input voltage must not exceed 1.8 V.

3.3 V supply voltage to the internal regulator, the external rail, and the ADC. Also used as the ADC reference voltage.

Ground.

[1]

[2]

[3]

[4]

[5]

[6]

Pin state at reset for default function: I = Input; O = Output; PU = internal pull-up enabled (pins pulled up to full V

DD

level); IA = inactive, no pull-up/down enabled.

RESET functionality is not available in Deep power-down mode. Use the WAKEUP pin to reset the chip and wake up from Deep power-down mode. An external pull-up resistor is required on this pin for the Deep power-down mode.

Pad providing digital I/O functions with configurable pull-up/pull-down resistors and configurable hysteresis.

I

2

C-bus pads compliant with the I

2

C-bus specification for I

2

C standard mode and I

2

C Fast-mode Plus. The pin requires an external pull-up to provide output functionality. When power is switched off, this pin is floating and does not disturb the I2C lines. Open-drain configuration applies to all functions on this pin.

Pad providing digital I/O functions with configurable pull-up/pull-down resistors, configurable hysteresis, and analog input. When configured as a ADC input, digital section of the pad is disabled.

When the system oscillator is not used, connect XTALIN and XTALOUT as follows: XTALIN can be left floating or can be grounded

(grounding is preferred to reduce susceptibility to noise). XTALOUT should be left floating.

Table 163. LPC11C24/C22 pin description table (LQFP48 package)

Symbol Pin Type Description

PIO0_0 to PIO0_11

RESET/PIO0_0

3

[1]

I

Port 0 —

Port 0 is a 12-bit I/O port with individual direction and function controls for each bit. The operation of port 0 pins depends on the function selected through the

IOCONFIG register block.

RESET —

External reset input with 20 ns glitch filter. A LOW-going pulse as short as

50 ns on this pin resets the device, causing I/O ports and peripherals to take on their default states, and processor execution to begin at address 0.

In deep power-down mode, this pin must be pulled HIGH externally. The RESET pin can be left unconnected or be used as a GPIO pin if an external RESET function is not needed.

PIO0_1/CLKOUT/

CT32B0_MAT2

PIO0_2/SSEL0/

CT16B0_CAP0

PIO0_3

4

[3]

10

14

[3]

[3]

I/O

I/O

O

O

I/O

I/O

I

I/O

PIO0_0 —

General purpose digital input/output pin with 10 ns glitch filter.

PIO0_1 —

General purpose digital input/output pin. A LOW level on this pin during reset starts the flash ISP command handler via UART (if PIO0_3 is HIGH) or via

C_CAN (if PIO0_3 is LOW).

CLKOUT —

Clockout pin.

CT32B0_MAT2 —

Match output 2 for 32-bit timer 0.

PIO0_2 —

General purpose digital input/output pin.

SSEL0 —

Slave Select for SPI0.

PIO0_4/SCL 15

[4]

I/O

I/O

CT16B0_CAP0 —

Capture input 0 for 16-bit timer 0.

PIO0_3 —

General purpose digital input/output pin. This pin is monitored during reset:

Together with a LOW level on pin PIO0_1, a LOW level starts the flash ISP command handler via C_CAN and a HIGH level starts the flash ISP command handler via UART.

PIO0_4 —

General purpose digital input/output pin (open-drain).

SCL —

I

2

C-bus, open-drain clock input/output. High-current sink only if I

2

C Fast-mode

Plus is selected in the I/O configuration register.

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Chapter 9: LPC111x/LPC11Cxx Pin configuration (LPC1100, LPC1100C,

Table 163. LPC11C24/C22 pin description table (LQFP48 package)

Symbol

PIO0_5/SDA

Pin

16

[4]

Type

I/O

I/O

Description

PIO0_5 —

General purpose digital input/output pin (open-drain).

SDA —

I

2

C-bus, open-drain data input/output. High-current sink only if I

2

C Fast-mode

Plus is selected in the I/O configuration register.

PIO0_6/SCK0 23

[3]

I/O

I/O

PIO0_6 —

SCK0 —

General purpose digital input/output pin.

Serial clock for SPI0.

PIO0_7/CTS 24

[3]

I

I/O

PIO0_7 —

CTS —

General purpose digital input/output pin (high-current output driver).

Clear To Send input for UART.

PIO0_8/MISO0/

CT16B0_MAT0

27

[3]

I/O

I/O

PIO0_8 —

MISO0 —

General purpose digital input/output pin.

Master In Slave Out for SPI0.

PIO0_9/MOSI0/

CT16B0_MAT1

28

[3]

O

I/O

I/O

O

CT16B0_MAT0 —

PIO0_9 —

MOSI0 —

Match output 0 for 16-bit timer 0.

General purpose digital input/output pin.

Master Out Slave In for SPI0.

CT16B0_MAT1 —

Match output 1 for 16-bit timer 0.

29

[3]

SWCLK/PIO0_10/

SCK0/

CT16B0_MAT2

I

I/O

I/O

O

SWCLK —

Serial wire clock.

PIO0_10 —

General purpose digital input/output pin.

SCK0 —

Serial clock for SPI0.

CT16B0_MAT2 —

Match output 2 for 16-bit timer 0.

32

[5]

R/PIO0_11/

AD0/

CT32B0_MAT3

-

I/O

I

O

R —

Reserved. Configure for an alternate function in the IOCONFIG block.

PIO0_11 —

General purpose digital input/output pin.

AD0 —

A/D converter, input 0.

CT32B0_MAT3 —

Match output 3 for 32-bit timer 0.

PIO1_0 to PIO1_11

R/PIO1_0/AD1/

CT32B1_CAP0

R/PIO1_1/AD2/

CT32B1_MAT0

33

34

[5]

[5]

I

-

I

-

I/O

I

I/O

Port 1 —

Port 1 is a 12-bit I/O port with individual direction and function controls for each bit. The operation of port 1 pins depends on the function selected through the

IOCONFIG register block.

R —

Reserved. Configure for an alternate function in the IOCONFIG block.

PIO1_0 —

General purpose digital input/output pin.

AD1 —

A/D converter, input 1.

CT32B1_CAP0 —

Capture input 0 for 32-bit timer 1.

R —

Reserved. Configure for an alternate function in the IOCONFIG block.

R/PIO1_2/AD3/

CT32B1_MAT1

SWDIO/PIO1_3/

AD4/

CT32B1_MAT2

35

39

[5]

[5]

-

I

O

I/O

O

I/O

I

I/O

O

PIO1_1 —

General purpose digital input/output pin.

AD2 —

A/D converter, input 2.

CT32B1_MAT0 —

Match output 0 for 32-bit timer 1.

R —

Reserved. Configure for an alternate function in the IOCONFIG block.

PIO1_2 —

General purpose digital input/output pin.

AD3 —

A/D converter, input 3.

CT32B1_MAT1 —

Match output 1 for 32-bit timer 1.

SWDIO —

Serial wire debug input/output.

PIO1_3 —

AD4 —

General purpose digital input/output pin.

A/D converter, input 4.

CT32B1_MAT2 —

Match output 2 for 32-bit timer 1.

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Chapter 9: LPC111x/LPC11Cxx Pin configuration (LPC1100, LPC1100C,

Table 163. LPC11C24/C22 pin description table (LQFP48 package)

Symbol

PIO1_4/AD5/

CT32B1_MAT3/

WAKEUP

Pin

40

[5]

Type

I/O

Description

PIO1_4 —

General purpose digital input/output pin with 10 ns glitch filter. In Deep power-down mode, this pin serves as the Deep power-down mode wake-up pin with

20 ns glitch filter. Pull this pin HIGH externally before entering Deep power-down mode. Pull this pin LOW to exit Deep power-down mode. A LOW-going pulse as short as 50 ns wakes up the part.

PIO1_5/RTS/

CT32B0_CAP0

45

[3]

I

O

I/O

O

AD5 —

RTS —

A/D converter, input 5.

CT32B1_MAT3 —

PIO1_5 —

Match output 3 for 32-bit timer 1.

General purpose digital input/output pin.

Request To Send output for UART.

PIO1_6/RXD/

CT32B0_MAT0

PIO1_7/TXD/

CT32B0_MAT1

PIO1_8/

CT16B1_CAP0

46

47

9

[3]

[3]

[3]

I/O

O

O

I/O

I

I/O

I

O

CT32B0_CAP0 —

PIO1_6 —

RXD —

PIO1_7 —

TXD —

PIO1_8 —

Capture input 0 for 32-bit timer 0.

General purpose digital input/output pin.

Receiver input for UART.

CT32B0_MAT0 —

Match output 0 for 32-bit timer 0.

General purpose digital input/output pin.

Transmitter output for UART.

CT32B0_MAT1 —

Match output 1 for 32-bit timer 0.

General purpose digital input/output pin.

PIO1_10/AD6/

CT16B1_MAT1

PIO1_11/AD7

PIO2_0 to PIO2_11

PIO2_0/DTR/

SSEL1

30

42

2

[3]

[5]

[5]

I

I/O

I

O

I

I/O

CT16B1_CAP0 —

Capture input 0 for 16-bit timer 1.

PIO1_10 —

General purpose digital input/output pin.

AD6 —

A/D converter, input 6.

CT16B1_MAT1 —

Match output 1 for 16-bit timer 1.

PIO1_11 —

General purpose digital input/output pin.

AD7 —

A/D converter, input 7.

Port 2 —

Port 2 is a 12-bit I/O port with individual direction and function controls for each bit. The operation of port 2 pins depends on the function selected through the

IOCONFIG register block.

PIO2_0 —

General purpose digital input/output pin.

PIO2_1/DSR/SCK1

PIO2_2/DCD/

MISO1

13

26

[3]

[3]

I/O

I/O

I/O

I

I/O

I/O

I/O

DTR —

Data Terminal Ready output for UART.

SSEL1 —

Slave Select for SPI1.

PIO2_1 —

General purpose digital input/output pin.

DSR —

Data Set Ready input for UART.

SCK1 —

Serial clock for SPI1.

PIO2_2 —

General purpose digital input/output pin.

DCD —

Data Carrier Detect input for UART.

MISO1 —

Master In Slave Out for SPI1.

PIO2_3/RI/MOSI1

PIO2_6

PIO2_7

PIO2_8

PIO2_10

38

1

[3]

25

[3]

11

[3]

12

[3]

[3]

I/O

I/O

I/O

I/O

I/O

I

I/O

I

I/O

PIO2_3 —

RI —

MOSI1 —

PIO2_6 —

PIO2_7 —

PIO2_8 —

General purpose digital input/output pin.

Ring Indicator input for UART.

Master Out Slave In for SPI1.

General purpose digital input/output pin.

General purpose digital input/output pin.

General purpose digital input/output pin.

PIO2_10 —

General purpose digital input/output pin.

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Chapter 9: LPC111x/LPC11Cxx Pin configuration (LPC1100, LPC1100C,

Table 163. LPC11C24/C22 pin description table (LQFP48 package)

Symbol

PIO2_11/SCK0

Pin

31

[3]

Type

I/O

Description

PIO2_11 —

General purpose digital input/output pin.

PIO3_0 to PIO3_3

I/O

SCK0 —

Serial clock for SPI0.

Port 3 —

Port 3 is a 12-bit I/O port with individual direction and function controls for each bit. The operation of port 3 pins depends on the function selected through the

IOCONFIG register block. Pins PIO3_4 to PIO3_11 are not available.

PIO3_0/DTR 36

[3]

PIO3_1/DSR 37

[3]

I/O

O

I

I/O

PIO3_0 —

General purpose digital input/output pin.

DTR —

Data Terminal Ready output for UART.

PIO3_1 —

General purpose digital input/output pin.

DSR —

Data Set Ready input for UART.

PIO3_2/DCD 43

[3]

PIO3_3/RI 48

[3]

I

I/O

I

I/O

PIO3_2 —

General purpose digital input/output pin.

DCD —

Data Carrier Detect input for UART.

PIO3_3 —

General purpose digital input/output pin.

RI —

Ring Indicator input for UART.

CANL

CANH

STB

18

19

22 I

I/O

I/O

VDD_CAN

V

CC

GND

V

V

DD

XTALIN

XTALOUT

SS

17

20

21

8;44

6

7

[7]

[7]

5; 41

-

-

-

I

I

I

O

LOW-level CAN bus line.

HIGH-level CAN bus line.

Silent mode control input for CAN transceiver (LOW = Normal mode, HIGH = silent mode).

Supply voltage for I/O level of CAN transceiver.

Supply voltage for CAN transceiver.

Ground for CAN transceiver.

Supply voltage to the internal regulator, the external rail, and the ADC. Also used as the ADC reference voltage.

Input to the oscillator circuit and internal clock generator circuits. Input voltage must not exceed 1.8 V.

Output from the oscillator amplifier.

Ground.

[1]

[2]

[3]

[4]

[5]

[6]

5 V tolerant pad. RESET functionality is not available in Deep power-down mode. Use the WAKEUP pin to reset the chip and wake up from Deep power-down mode. An external pull-up resistor is required on this pin for the Deep power-down mode.

5 V tolerant pad providing digital I/O functions with configurable pull-up/pull-down resistors and configurable hysteresis.

I

2

C-bus pads compliant with the I

2

C-bus specification for I

2

C standard mode and I

2

C Fast-mode Plus. The pin requires an external pull-up to provide output functionality. When power is switched off, this pin is floating and does not disturb the I2C lines. Open-drain configuration applies to all functions on this pin.

5 V tolerant pad providing digital I/O functions with configurable pull-up/pull-down resistors, configurable hysteresis, and analog input.

When configured as a ADC input, digital section of the pad is disabled and the pin is not 5 V tolerant.

5 V tolerant digital I/O pad without pull-up/pull-down resistors.

When the system oscillator is not used, connect XTALIN and XTALOUT as follows: XTALIN can be left floating or can be grounded

(grounding is preferred to reduce susceptibility to noise). XTALOUT should be left floating.

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Chapter 9: LPC111x/LPC11Cxx Pin configuration (LPC1100, LPC1100C,

Table 164. LPC11D14 pin description table (LQFP100 package)

Symbol Pin Start logic input

Type Reset state

[1]

Description

Microcontroller pins

PIO0_0 to PIO0_11 I/O

Port 0 —

Port 0 is a 12-bit I/O port with individual direction and function controls for each bit. The operation of port 0 pins depends on the function selected through the IOCONFIG register block.

RESET/PIO0_0

6

[1]

yes I I; PU

RESET —

External reset input with 20 ns glitch filter. A

LOW-going pulse as short as 50 ns on this pin resets the device, causing I/O ports and peripherals to take on their default states, and processor execution to begin at address 0.

In deep power-down mode, this pin must be pulled HIGH externally. The RESET pin can be left unconnected or be used as a GPIO pin if an external RESET function is not needed.

I/O -

PIO0_1/CLKOUT/

CT32B0_MAT2

7

[3]

yes I/O I; PU

PIO0_0 —

General purpose digital input/output pin with 10 ns glitch filter.

PIO0_1 —

General purpose digital input/output pin. A LOW level on this pin during reset starts the ISP command handler.

PIO0_2/SSEL0/

CT16B0_CAP0

PIO0_3

PIO0_4/SCL

PIO0_5/SDA

13

17

18

19

[3]

[3]

[4]

[4]

yes yes yes yes

O

O

I/O

I/O

I

I/O

I/O

I/O

I/O

I/O -

-

-

-

-

-

I; PU

I; PU

I; IA

I; IA

CLKOUT —

PIO0_2 —

SSEL0 —

Clockout pin.

CT32B0_MAT2 —

Match output 2 for 32-bit timer 0.

General purpose digital input/output pin.

Slave Select for SPI0.

CT16B0_CAP0 —

Capture input 0 for 16-bit timer 0.

PIO0_3 —

General purpose digital input/output pin.

PIO0_4 —

General purpose digital input/output pin

(open-drain).

SCL —

I

2

C-bus, open-drain clock input/output. High-current sink only if I

2

C Fast-mode Plus is selected in the I/O configuration register.

PIO0_5 —

General purpose digital input/output pin

(open-drain).

SDA —

I

2

C-bus, open-drain data input/output. High-current sink only if I

2

C Fast-mode Plus is selected in the I/O configuration register.

PIO0_6/SCK0 25

[3]

yes

PIO0_7/CTS

PIO0_8/MISO0/

CT16B0_MAT0

PIO0_9/MOSI0/

CT16B0_MAT1

26

81

82

[3]

[3]

[3]

yes yes yes

I

I/O

I/O

I/O

I/O

I/O

O

I/O

I/O

O

-

-

-

-

-

-

I; PU

I; PU

I; PU

I; PU

PIO0_6 —

General purpose digital input/output pin.

SCK0 —

Serial clock for SPI0.

PIO0_7 —

General purpose digital input/output pin

(high-current output driver).

CTS —

Clear To Send input for UART.

PIO0_8 —

General purpose digital input/output pin.

MISO0 —

Master In Slave Out for SPI0.

CT16B0_MAT0 —

Match output 0 for 16-bit timer 0.

PIO0_9 —

MOSI0 —

General purpose digital input/output pin.

Master Out Slave In for SPI0.

CT16B0_MAT1 —

Match output 1 for 16-bit timer 0.

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Chapter 9: LPC111x/LPC11Cxx Pin configuration (LPC1100, LPC1100C,

Table 164. LPC11D14 pin description table (LQFP100 package)

…continued

Symbol Pin Start logic input

Type Reset state

[1]

Description

83

[3]

yes I I; PU

SWCLK —

Serial wire clock.

SWCLK/PIO0_10/

SCK0/

CT16B0_MAT2

I/O

I/O

-

-

PIO0_10 —

SCK0 —

General purpose digital input/output pin.

Serial clock for SPI0.

R/PIO0_11/

AD0/CT32B0_MAT3

PIO1_0 to PIO1_11

R/PIO1_0/

AD1/CT32B1_CAP0

86

87

[5]

[5]

yes yes I

I

I

O

I/O

O

I/O

-

I; PU

-

-

-

I; PU

CT16B0_MAT2 —

R —

Reserved. Configure for an alternate function in the

IOCONFIG block.

Match output 2 for 16-bit timer 0.

PIO0_11 —

General purpose digital input/output pin.

AD0 —

A/D converter, input 0.

CT32B0_MAT3 —

Match output 3 for 32-bit timer 0.

Port 1 —

Port 1 is a 12-bit I/O port with individual direction and function controls for each bit. The operation of port 1 pins depends on the function selected through the IOCONFIG register block.

R —

Reserved. Configure for an alternate function in the

IOCONFIG block.

R/PIO1_1/

AD2/CT32B1_MAT0

88

[5]

no

I

I/O

I

O

-

-

-

I; PU

PIO1_0 —

General purpose digital input/output pin.

AD1 —

A/D converter, input 1.

CT32B1_CAP0 —

Capture input 0 for 32-bit timer 1.

R —

Reserved. Configure for an alternate function in the

IOCONFIG block.

PIO1_1 —

General purpose digital input/output pin.

R/PIO1_2/

AD3/CT32B1_MAT1

SWDIO/PIO1_3/

AD4/CT32B1_MAT2

PIO1_4/AD5/

CT32B1_MAT3/

WAKEUP

PIO1_5/RTS/

CT32B0_CAP0

89

93

94

99

[5]

[5]

[5]

[3]

no no no no

I

I

I

I

I/O

I

O

I/O

O

I/O

I

I/O

O

I/O

O

I/O

O -

-

-

-

-

-

-

-

-

-

-

-

-

I; PU

I; PU

I; PU

I; PU

AD2 —

CT32B1_MAT0 —

R —

A/D converter, input 2.

Reserved. Configure for an alternate function in the

IOCONFIG block.

Match output 0 for 32-bit timer 1.

PIO1_2 —

General purpose digital input/output pin.

AD3 —

A/D converter, input 3.

CT32B1_MAT1 —

Match output 1 for 32-bit timer 1.

SWDIO —

Serial wire debug input/output.

PIO1_3 —

General purpose digital input/output pin.

AD4 —

A/D converter, input 4.

CT32B1_MAT2 —

Match output 2 for 32-bit timer 1.

PIO1_4 —

General purpose digital input/output pin with 10 ns glitch filter. In Deep power-down mode, this pin serves as the

Deep power-down mode wake-up pin with 20 ns glitch filter.

Pull this pin HIGH externally before entering Deep power-down mode. Pull this pin LOW to exit Deep power-down mode. A

LOW-going pulse as short as 50 ns wakes up the part.

AD5 —

A/D converter, input 5.

CT32B1_MAT3 —

Match output 3 for 32-bit timer 1.

PIO1_5 —

General purpose digital input/output pin.

RTS —

Request To Send output for UART.

CT32B0_CAP0 —

Capture input 0 for 32-bit timer 0.

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UM10398

Chapter 9: LPC111x/LPC11Cxx Pin configuration (LPC1100, LPC1100C,

Table 164. LPC11D14 pin description table (LQFP100 package)

…continued

Symbol Pin Start logic input

Type Reset state

[1]

Description

PIO1_6/RXD/

CT32B0_MAT0

100

[3]

no I/O I; PU

PIO1_6 —

General purpose digital input/output pin.

I

O -

-

RXD —

Receiver input for UART.

CT32B0_MAT0 —

Match output 0 for 32-bit timer 0.

PIO1_7/TXD/

CT32B0_MAT1

1

[3]

no I/O

O -

I; PU

PIO1_7 —

TXD —

General purpose digital input/output pin.

Transmitter output for UART.

PIO1_8/

CT16B1_CAP0

PIO1_9/

CT16B1_MAT0

12

20

[3]

[3]

no no

O

I/O

I

I/O

-

-

I; PU

I; PU

CT32B0_MAT1 —

PIO1_8 —

PIO1_9 —

Match output 1 for 32-bit timer 0.

General purpose digital input/output pin.

CT16B1_CAP0 —

Capture input 0 for 16-bit timer 1.

General purpose digital input/output pin.

PIO1_10/AD6/

CT16B1_MAT1

84

[5]

no

O

I/O

I

O -

-

-

I; PU

CT16B1_MAT0 —

Match output 0 for 16-bit timer 1.

PIO1_10 —

General purpose digital input/output pin.

AD6 —

A/D converter, input 6.

CT16B1_MAT1 —

Match output 1 for 16-bit timer 1.

PIO1_11/AD7

PIO2_0 to PIO2_11

96

[5]

no

I

I/O

I/O

-

I; PU

PIO1_11 —

AD7 —

General purpose digital input/output pin.

A/D converter, input 7.

Port 2 —

Port 2 is a 12-bit I/O port with individual direction and function controls for each bit. The operation of port 2 pins depends on the function selected through the IOCONFIG register block.

PIO2_0/DTR/SSEL1

5

[3]

no

PIO2_1/DSR/SCK1 16

[3]

no

I/O

O

I/O

I/O

-

I; PU

-

I; PU

PIO2_0 —

General purpose digital input/output pin.

DTR —

Data Terminal Ready output for UART.

SSEL1 —

Slave Select for SPI1.

PIO2_1 —

General purpose digital input/output pin.

PIO2_2/DCD/MISO1

PIO2_3/RI/MOSI1

80

92

[3]

[3]

no no

I/O

I/O

I

I/O

I

I/O

I

I/O

-

-

-

-

-

-

I; PU

I; PU

DSR —

DCD —

RI —

Data Set Ready input for UART.

SCK1 —

Serial clock for SPI1.

PIO2_2 —

PIO2_3 —

General purpose digital input/output pin.

Data Carrier Detect input for UART.

MISO1 —

Master In Slave Out for SPI1.

General purpose digital input/output pin.

Ring Indicator input for UART.

MOSI1 —

Master Out Slave In for SPI1.

PIO2_4

PIO2_5

PIO2_6

PIO2_7

PIO2_8

PIO2_9

PIO2_10

PIO2_11/SCK0

22

[3]

23

[3]

4

[3]

14

[3]

15

[3]

27

[3]

28

[3]

85

[3]

no no no no no no no no

I/O

I/O

I/O

I/O

I/O

I/O

I/O

I/O

I/O -

I; PU

I; PU

I; PU

I; PU

I; PU

I; PU

I; PU

I; PU

PIO2_4 —

PIO2_5 —

PIO2_6 —

PIO2_7 —

PIO2_8 —

PIO2_9 —

SCK0 —

General purpose digital input/output pin.

General purpose digital input/output pin.

General purpose digital input/output pin.

General purpose digital input/output pin.

General purpose digital input/output pin.

General purpose digital input/output pin.

PIO2_10 —

PIO2_11 —

General purpose digital input/output pin.

General purpose digital input/output pin.

Serial clock for SPI0.

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Chapter 9: LPC111x/LPC11Cxx Pin configuration (LPC1100, LPC1100C,

S4

S5

S6

S7

S0

S1

S2

S3

Table 164. LPC11D14 pin description table (LQFP100 package)

…continued

Symbol Pin Start logic input

Type Reset state

[1]

Description

PIO3_0 to PIO3_5

PIO3_0/DTR 90

[3]

no

I/O

Port 3 —

Port 3 is a 12-bit I/O port with individual direction and function controls for each bit. The operation of port 3 pins depends on the function selected through the IOCONFIG register block. Pins PIO3_6 to PIO3_11 are not available.

PIO3_0 —

General purpose digital input/output pin.

PIO3_1/DSR

PIO3_2/DCD

PIO3_3/RI

91

97

2

[3]

[3]

[3]

no no no

I

I/O

O

I/O

I/O

I

I/O

-

-

I; PU

-

I; PU

I; PU

I; PU

DTR —

PIO3_1 —

DSR —

Data Set Ready input for UART.

PIO3_2 —

General purpose digital input/output pin.

DCD —

Data Terminal Ready output for UART.

General purpose digital input/output pin.

Data Carrier Detect input for UART.

PIO3_3 —

General purpose digital input/output pin.

RI —

Ring Indicator input for UART.

PIO3_4 —

General purpose digital input/output pin.

PIO3_4

PIO3_5

V

DD

21

[3]

24

[3]

11; 98 no

no

I

I/O

I

I/O

-

I; PU

-

I; PU

XTALIN

XTALOUT

V

SS

LCD display pins

9

[7]

10

[7]

8; 95

-

-

-

I

I

O -

-

-

PIO3_5 —

General purpose digital input/output pin.

3.3 V supply voltage to the internal regulator, the external rail, and the ADC. Also used as the ADC reference voltage.

Input to the oscillator circuit and internal clock generator circuits. Input voltage must not exceed 1.8 V.

Output from the oscillator amplifier.

Ground.

S8

S9

S10

S11

S12

S13

S14

S15

S16

S17

S18

S19

46

47

48

49

50

51

52

53

54

55

56

57

58

59

60

61

62

63

64

65

-

-

-

-

-

-

-

-

-

-

-

-

-

-

-

-

-

-

-

-

O

O

O

O

O

O

O

O

O

O

O

O

O

O

O

O

O

O

O

O

V

LCD

[7]

V

LCD

[7]

V

LCD

[7]

V

LCD

[7]

V

LCD

[7]

V

LCD

[7]

V

LCD

[7]

V

LCD

[7]

V

LCD

[7]

V

LCD

[7]

V

LCD

[7]

V

LCD

[7]

V

LCD

[7]

V

LCD

[7]

V

LCD

[7]

V

LCD

[7]

V

LCD

[7]

V

LCD

[7]

V

LCD

[7]

V

LCD

[7]

LCD segment output.

LCD segment output.

LCD segment output.

LCD segment output.

LCD segment output.

LCD segment output.

LCD segment output.

LCD segment output.

LCD segment output.

LCD segment output.

LCD segment output.

LCD segment output.

LCD segment output.

LCD segment output.

LCD segment output.

LCD segment output.

LCD segment output.

LCD segment output.

LCD segment output.

LCD segment output.

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Chapter 9: LPC111x/LPC11Cxx Pin configuration (LPC1100, LPC1100C,

Table 164. LPC11D14 pin description table (LQFP100 package)

…continued

Symbol Pin Start logic input

Type Reset state

[1]

Description

S20

S21

S22

S23

S24

S25

S26

S27

S28

S29

S30

S31

S32

S33

S34

S35

S36

S37

S38

S39

BP0

BP1

BP2

BP3

LCD_SDA

LCD_SCL

SYNC

66

67

68

69

70

71

72

73

74

75

76

77

78

79

29

30

31

32

33

34

42

44

43

45

35

36

37

-

-

-

-

-

-

-

-

-

-

-

-

-

-

-

-

-

-

-

-

-

-

-

-

-

-

O

O

O

O

O

O

O

O

O

O

O

O

O

O

O

O

O

O

O

O

O

O

O

O

I/O

I/O

I/O

V

LCD

[7]

V

LCD

[7]

V

LCD

[7]

V

LCD

[7]

V

LCD

[7]

V

LCD

[7]

V

LCD

[7]

V

LCD

[7]

V

LCD

[7]

V

LCD

[7]

V

LCD

[7]

V

LCD

[7]

V

LCD

[7]

V

LCD

[7]

V

LCD

[7]

V

LCD

[7]

V

LCD

[7]

V

LCD

[7]

V

LCD

[7]

V

LCD

[7]

V

LCD

[7]

V

LCD

[7]

V

LCD

[7]

V

LCD

[7]

[7]

[7]

[7]

LCD segment output.

LCD segment output.

LCD segment output.

LCD segment output.

LCD segment output.

LCD segment output.

LCD segment output.

LCD segment output.

LCD segment output.

LCD segment output.

LCD segment output.

LCD segment output.

LCD segment output.

LCD segment output.

LCD segment output.

LCD segment output.

LCD segment output.

LCD segment output.

LCD segment output.

LCD segment output.

LCD backplane output.

LCD backplane output.

LCD backplane output.

LCD backplane output.

I

2

C-bus serial data input/output.

I

2

C-bus serial clock input.

Cascade synchronization input/output.

[7]

CLK

V

DD(LCD)

38

39

40 -

-

-

-

-

I/O

-

-

External clock input/output.

1.8 V to 5.5 V power supply: Power supply voltage for the

PCF8576D.

LCD ground.

V

SS(LCD)

V

LCD n.c.

41

3

-

-

-

-

LCD power supply; LCD voltage.

Not connected.

[1]

[2]

[3]

[4]

Pin state at reset for default function: I = Input; O = Output; PU = internal pull-up enabled (pins pulled up to full V

DD

level (V

DD

= 3.3 V));

IA = inactive, no pull-up/down enabled.

RESET functionality is not available in Deep power-down mode. Use the WAKEUP pin to reset the chip and wake up from Deep power-down mode. An external pull-up resistor is required on this pin for the Deep power-down mode.

5 V tolerant pad providing digital I/O functions with configurable pull-up/pull-down resistors and configurable hysteresis.

I

2

C-bus pads compliant with the I

2

C-bus specification for I

2

C standard mode and I

2

C Fast-mode Plus. The pin requires an external pull-up to provide output functionality. When power is switched off, this pin is floating and does not disturb the I2C lines. Open-drain configuration applies to all functions on this pin.

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Chapter 9: LPC111x/LPC11Cxx Pin configuration (LPC1100, LPC1100C,

[5]

[6]

[7]

5 V tolerant pad providing digital I/O functions with configurable pull-up/pull-down resistors, configurable hysteresis, and analog input.

When configured as a ADC input, digital section of the pad is disabled and the pin is not 5 V tolerant.

When the system oscillator is not used, connect XTALIN and XTALOUT as follows: XTALIN can be left floating or can be grounded

(grounding is preferred to reduce susceptibility to noise). XTALOUT should be left floating.

See the

LPC11D4 data sheet

.

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Chapter 10: LPC111x Pin configuration (LPC1100L series,

TSSOP, DIP, SO packages)

Rev. 12.4 — 22 December 2016 User manual

10.1 How to read this chapter

This chapter describes the small pin packages for the LPC111x parts in TSSOP, DIP, and

SO packages.

Table 165. LPC11xx pin configurations for 20-pin and 28-pin packages

Part

LPC1110FD20 Pin configuration

SO20

Figure 22

-

TSSOP20

LPC1111FDH20/002

LPC1112FD20/102

Pin description

Pin configuration

Pin description

Pin configuration

-

-

Table 166

Figure 22

-

-

Figure 23

Table 166

LPC1112FDH20/102

LPC1112FDH28/102

LPC1114FDH28/102

LPC1114FN28/102

Pin description

Pin configuration

Pin description

Pin configuration

Pin description

Pin configuration

Pin description

Pin configuration

Pin description

-

-

-

-

-

-

-

-

Table 166

-

-

-

-

-

-

-

Figure 24

Table 167

-

-

-

-

-

-

-

TSSOP28

-

Figure 25

Table 168

Figure 25

-

-

Table 168

-

-

-

-

-

-

-

DIP28

-

-

-

-

-

Figure 26

Table 168

10.2 Pin configuration (LPC1110/11/12)

PIO0_8/MISO0/CT16B0_MAT0

PIO0_9/MOSI0/CT16B0_MAT1

SWCLK/PIO0_10/SCK0/CT16B0_MAT2

R/PIO0_11/AD0/CT32B0_MAT3

PIO0_5/SDA

PIO0_6/SCK0

R/PIO1_0/AD1/CT32B1_CAP0

R/PIO1_1/AD2/CT32B1_MAT0

R/PIO1_2/AD3/CT32B1_MAT1

SWDIO/PIO1_3/AD4/CT32B1_MAT2

9

10

7

8

5

6

3

4

1

2

LPC1110FD20

LPC1112FD20/

102

20

19

18

17

16

15

14

PIO0_4/SCL

PIO0_2/SSEL0/CT16B0_CAP0

PIO0_1/CLKOUT/CT32B0_MAT2

RESET/PIO0_0

V

V

SS

DD

XTALIN

13

12

11

XTALOUT

PIO1_7/TXD/CT32B0_MAT1

PIO1_6/RXD/CT32B0_MAT0

002aag595

Fig 22. Pin configuration SO20 package

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Chapter 10: LPC111x Pin configuration (LPC1100L series, TSSOP, DIP,

PIO0_8/MISO0/CT16B0_MAT0

PIO0_9/MOSI0/CT16B0_MAT1

SWCLK/PIO0_10/SCK0/CT16B0_MAT2

R/PIO0_11/AD0/CT32B0_MAT3

PIO0_5/SDA

PIO0_6/SCK0

R/PIO1_0/AD1/CT32B1_CAP0

R/PIO1_1/AD2/CT32B1_MAT0

R/PIO1_2/AD3/CT32B1_MAT1

SWDIO/PIO1_3/AD4/CT32B1_MAT2

9

10

7

8

5

6

3

4

1

2

LPC1111FDH20/002

002aag596

20

19

18

17

16

15

14

PIO0_4/SCL

PIO0_2/SSEL0/CT16B0_CAP0

PIO0_1/CLKOUT/CT32B0_MAT2

RESET/PIO0_0

V

V

SS

DD

XTALIN

13

12

11

XTALOUT

PIO1_7/TXD/CT32B0_MAT1

PIO1_6/RXD/CT32B0_MAT0

Fig 23. Pin configuration TSSOP20 package with I

2

C-bus pins

Table 166. LPC1110/11/12 pin description table (SO20 and TSSOP20 package with I

2

C-bus pins)

Symbol Start logic input

Type Reset state

[1]

Description

PIO0_0 to PIO0_11

RESET/PIO0_0

PIO0_1/CLKOUT/

CT32B0_MAT2

PIO0_2/SSEL0/

CT16B0_CAP0

PIO0_4/SCL

PIO0_5/SDA

PIO0_6/SCK0

17

18

19

20

5

6

[2]

yes

[3]

yes

[3]

yes

[4]

yes

[4]

yes

[3]

yes

I

I/O

I/O

I/O

O

O

I/O

I/O

I

I/O

I/O

I/O

I/O

I/O

I/O

-

-

I; PU

I; PU

-

-

-

I; PU

-

-

I; IA

I; IA

-

I; PU

Port 0 —

Port 0 is a 12-bit I/O port with individual direction and function controls for each bit. The operation of port 0 pins depends on the function selected through the IOCONFIG register block.

RESET —

External reset input with 20 ns glitch filter. A LOW-going pulse as short as 50 ns on this pin resets the device, causing I/O ports and peripherals to take on their default states, and processor execution to begin at address 0.

In deep power-down mode, this pin must be pulled HIGH externally.

The RESET pin can be left unconnected or be used as a GPIO pin if an external RESET function is not needed.

PIO0_0 —

General purpose digital input/output pin with 10 ns glitch filter.

PIO0_1 —

General purpose digital input/output pin. A LOW level on this pin during reset starts the ISP command handler.

CLKOUT —

Clockout pin.

CT32B0_MAT2 —

Match output 2 for 32-bit timer 0.

PIO0_2 —

General purpose digital input/output pin.

SSEL0 —

Slave Select for SPI0.

CT16B0_CAP0 —

Capture input 0 for 16-bit timer 0.

PIO0_4 —

General purpose digital input/output pin (open-drain).

SCL —

I

2

C-bus, open-drain clock input/output. High-current sink only if I

2

C Fast-mode Plus is selected in the I/O configuration register.

PIO0_5 —

General purpose digital input/output pin (open-drain).

SDA —

I

2

C-bus, open-drain data input/output. High-current sink only if I

2

C Fast-mode Plus is selected in the I/O configuration register.

PIO0_6 —

General purpose digital input/output pin.

SCK0 —

Serial clock for SPI0.

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Chapter 10: LPC111x Pin configuration (LPC1100L series, TSSOP, DIP,

Table 166. LPC1110/11/12 pin description table (SO20 and TSSOP20 package with I

2

C-bus pins)

…continued

Symbol Start logic input

Type Reset state

[1]

Description

PIO0_8/MISO0/

CT16B0_MAT0

PIO0_9/MOSI0/

CT16B0_MAT1

SWCLK/PIO0_10/

SCK0/

CT16B0_MAT2

R/PIO0_11/

AD0/CT32B0_MAT3

PIO1_0 to PIO1_7

R/PIO1_0/

AD1/CT32B1_CAP0

R/PIO1_1/

AD2/CT32B1_MAT0

R/PIO1_2/

AD3/CT32B1_MAT1

PIO1_6/RXD/

CT32B0_MAT0

1

2

3

4

7

8

9

SWDIO/PIO1_3/

AD4/CT32B1_MAT2

10

11

[3]

yes

[3]

yes

[3]

yes

[5]

yes

[5]

yes

[5]

[5]

[5]

[3]

no no no no

I

I/O

I

O

I/O

I

I

I/O

O

I

I/O

I

O

I/O

I/O

O

I/O

I/O

I

O

I/O

I/O

I

O

I/O

I

O

I/O

I/O

I

O

I

I/O

O

-

-

-

-

-

I; PU

-

I; PU

-

I; PU

-

-

-

I; PU

I; PU

-

-

-

I; PU

-

-

-

I; PU

-

-

-

-

-

-

I; PU

-

-

I; PU

PIO0_8 —

General purpose digital input/output pin.

MISO0 —

Master In Slave Out for SPI0.

CT16B0_MAT0 —

Match output 0 for 16-bit timer 0.

PIO0_9 —

General purpose digital input/output pin.

MOSI0 —

Master Out Slave In for SPI0.

CT16B0_MAT1 —

Match output 1 for 16-bit timer 0.

SWCLK —

Serial wire clock.

PIO0_10 —

General purpose digital input/output pin.

SCK0 —

Serial clock for SPI0.

CT16B0_MAT2 —

Match output 2 for 16-bit timer 0.

R —

Reserved. Configure for an alternate function in the

IOCONFIG block.

PIO0_11 —

General purpose digital input/output pin.

AD0 —

A/D converter, input 0.

CT32B0_MAT3 —

Match output 3 for 32-bit timer 0.

Port 1 —

Port 1 is a 12-bit I/O port with individual direction and function controls for each bit. The operation of port 1 pins depends on the function selected through the IOCONFIG register block.

R —

Reserved. Configure for an alternate function in the

IOCONFIG block.

PIO1_0 —

General purpose digital input/output pin.

AD1 —

A/D converter, input 1.

CT32B1_CAP0 —

Capture input 0 for 32-bit timer 1.

R —

Reserved. Configure for an alternate function in the

IOCONFIG block.

PIO1_1 —

General purpose digital input/output pin.

AD2 —

A/D converter, input 2.

CT32B1_MAT0 —

Match output 0 for 32-bit timer 1.

R —

Reserved. Configure for an alternate function in the

IOCONFIG block.

PIO1_2 —

General purpose digital input/output pin.

AD3 —

A/D converter, input 3.

CT32B1_MAT1 —

Match output 1 for 32-bit timer 1.

SWDIO —

Serial wire debug input/output.

PIO1_3 —

General purpose digital input/output pin.

AD4 —

A/D converter, input 4.

CT32B1_MAT2 —

Match output 2 for 32-bit timer 1.

PIO1_6 —

General purpose digital input/output pin.

RXD —

Receiver input for UART.

CT32B0_MAT0 —

Match output 0 for 32-bit timer 0.

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Chapter 10: LPC111x Pin configuration (LPC1100L series, TSSOP, DIP,

Table 166. LPC1110/11/12 pin description table (SO20 and TSSOP20 package with I

2

C-bus pins)

…continued

Symbol Start logic input

Type Reset state

[1]

Description

PIO1_7/TXD/

CT32B0_MAT1

V

DD

XTALIN

12

15

14

[3]

[6]

-

no

I

I/O

O

O

-

-

-

-

-

-

I; PU

PIO1_7 —

General purpose digital input/output pin.

TXD —

Transmitter output for UART.

CT32B0_MAT1 —

Match output 1 for 32-bit timer 0.

3.3 V supply voltage to the internal regulator, the external rail, and the ADC. Also used as the ADC reference voltage.

Input to the oscillator circuit and internal clock generator circuits.

Input voltage must not exceed 1.8 V.

Output from the oscillator amplifier.

Ground.

XTALOUT

V

SS

13

16

[6]

-

-

O

[1]

[2]

[3]

[4]

[5]

[6]

Pin state at reset for default function: I = Input; O = Output; PU = internal pull-up enabled (pins pulled up to full V

DD

level); IA = inactive, no pull-up/down enabled.

RESET functionality is not available in Deep power-down mode.

5 V tolerant pad providing digital I/O functions with configurable pull-up/pull-down resistors and configurable hysteresis.

I

2

C-bus pads compliant with the I

2

C-bus specification for I

2

C standard mode and I

2

C Fast-mode Plus. The pin requires an external pull-up to provide output functionality. When power is switched off, this pin is floating and does not disturb the I2C lines. Open-drain configuration applies to all functions on this pin.

5 V tolerant pad providing digital I/O functions with configurable pull-up/pull-down resistors, configurable hysteresis, and analog input.

When configured as a ADC input, digital section of the pad is disabled and the pin is not 5 V tolerant.

When the system oscillator is not used, connect XTALIN and XTALOUT as follows: XTALIN can be left floating or can be grounded

(grounding is preferred to reduce susceptibility to noise). XTALOUT should be left floating.

10.3 Pin configuration (LPC1112)

PIO0_8/MISO0/CT16B0_MAT0

PIO0_9/MOSI0/CT16B0_MAT1

1

2

SWCLK/PIO0_10/SCK0/CT16B0_MAT2

R/PIO0_11/AD0/CT32B0_MAT3

3

4

V

DDA

V

SSA

R/PIO1_0/AD1/CT32B1_CAP0

5

6

R/PIO1_1/AD2/CT32B1_MAT0

R/PIO1_2/AD3/CT32B1_MAT1

SWDIO/PIO1_3/AD4/CT32B1_MAT2

7

8

9

10

LPC1112FDH20/102

20

19

PIO0_3

PIO0_2/SSEL0/CT16B0_CAP0

18

17

PIO0_1/CLKOUT/CT32B0_MAT2

RESET/PIO0_0

16

15

14

V

SS

V

DD

XTALIN

13

12

11

XTALOUT

PIO1_7/TXD/CT32B0_MAT1

PIO1_6/RXD/CT32B0_MAT0

002aag597

Fig 24. Pin configuration TSSOP20 package with V

DDA

and V

SSA

pins

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Chapter 10: LPC111x Pin configuration (LPC1100L series, TSSOP, DIP,

Table 167. LPC1112 pin description table (TSSOP20 with V

DDA

and V

SSA

pins)

Symbol Start logic input

Type Reset state

[1]

Description

PIO0_0 to PIO0_11

RESET/PIO0_0

UM10398

User manual

17

[2]

yes I

PIO0_1/CLKOUT/

CT32B0_MAT2

PIO0_2/SSEL0/

CT16B0_CAP0

PIO0_3

PIO0_8/MISO0/

CT16B0_MAT0

PIO0_9/MOSI0/

CT16B0_MAT1

SWCLK/PIO0_10/

SCK0/

CT16B0_MAT2

PIO1_0 to PIO1_7

18

R/PIO0_11/

AD0/CT32B0_MAT3

4

[3]

yes

19

[3]

yes

20

1

[3]

[3]

yes yes

2

3

[3]

[3]

[4]

yes yes yes

I/O

I/O

I

I/O

I/O

O

I

O

I/O

I/O

O

I

I/O

I/O

I/O

O

O

I/O

I/O

I

I/O

O

I/O

I/O

-

-

-

-

I; PU

I; PU

-

-

-

I; PU

-

-

-

I; PU

I; PU

-

-

-

I; PU

-

I; PU

-

I; PU

Port 0 —

Port 0 is a 12-bit I/O port with individual direction and function controls for each bit. The operation of port 0 pins depends on the function selected through the IOCONFIG register block.

RESET —

External reset input with 20 ns glitch filter. A

LOW-going pulse as short as 50 ns on this pin resets the device, causing I/O ports and peripherals to take on their default states, and processor execution to begin at address 0.

In deep power-down mode, this pin must be pulled HIGH externally. The RESET pin can be left unconnected or be used as a GPIO pin if an external RESET function is not needed.

PIO0_0 —

General purpose digital input/output pin with 10 ns glitch filter.

PIO0_1 —

General purpose digital input/output pin. A LOW level on this pin during reset starts the ISP command handler.

CLKOUT —

Clockout pin.

CT32B0_MAT2 —

Match output 2 for 32-bit timer 0.

PIO0_2 —

General purpose digital input/output pin.

SSEL0 —

Slave Select for SPI0.

CT16B0_CAP0 —

Capture input 0 for 16-bit timer 0.

PIO0_3 —

General purpose digital input/output pin.

PIO0_8 —

General purpose digital input/output pin.

MISO0 —

Master In Slave Out for SPI0.

CT16B0_MAT0 —

Match output 0 for 16-bit timer 0.

PIO0_9 —

General purpose digital input/output pin.

MOSI0 —

Master Out Slave In for SPI0.

CT16B0_MAT1 —

Match output 1 for 16-bit timer 0.

SWCLK —

Serial wire clock.

PIO0_10 —

General purpose digital input/output pin.

SCK0 —

Serial clock for SPI0.

CT16B0_MAT2 —

Match output 2 for 16-bit timer 0.

R —

Reserved. Configure for an alternate function in the

IOCONFIG block.

PIO0_11 —

General purpose digital input/output pin.

AD0 —

A/D converter, input 0.

CT32B0_MAT3 —

Match output 3 for 32-bit timer 0.

Port 1 —

Port 1 is a 12-bit I/O port with individual direction and function controls for each bit. The operation of port 1 pins depends on the function selected through the IOCONFIG register block.

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UM10398

Chapter 10: LPC111x Pin configuration (LPC1100L series, TSSOP, DIP,

Table 167. LPC1112 pin description table (TSSOP20 with V

DDA

and V

SSA

pins)

…continued

Symbol Start logic input

Type Reset state

[1]

Description

R/PIO1_0/

AD1/CT32B1_CAP0

R/PIO1_1/

AD2/CT32B1_MAT0

R/PIO1_2/

AD3/CT32B1_MAT1

SWDIO/PIO1_3/

AD4/CT32B1_MAT2

PIO1_6/RXD/

CT32B0_MAT0

PIO1_7/TXD/

CT32B0_MAT1

V

V

DD

DDA

XTALIN

XTALOUT

V

SS

V

SSA

7

8

9

10

11

12

15

5

14

13

16

6

[4]

[4]

[4]

[4]

[3]

[3]

[5]

[5]

-

-

-

-

-

yes no no no no no

I

I

I

I

I

I

I

I

I/O

O

I/O

I/O

O

I/O

O

I/O

O

O

I

I/O

O

I/O

O

I

I

I

I

O

-

-

-

-

-

I; PU

-

-

-

I; PU

-

-

-

I; PU

-

-

-

-

I; PU

-

I; PU

-

-

-

-

-

-

I; PU

R —

Reserved. Configure for an alternate function in the

IOCONFIG block.

PIO1_0 —

General purpose digital input/output pin.

AD1 —

A/D converter, input 1.

CT32B1_CAP0 —

Capture input 0 for 32-bit timer 1.

R —

Reserved. Configure for an alternate function in the

IOCONFIG block.

PIO1_1 —

General purpose digital input/output pin.

AD2 —

A/D converter, input 2.

CT32B1_MAT0 —

Match output 0 for 32-bit timer 1.

R —

Reserved. Configure for an alternate function in the

IOCONFIG block.

PIO1_2 —

General purpose digital input/output pin.

AD3 —

A/D converter, input 3.

CT32B1_MAT1 —

Match output 1 for 32-bit timer 1.

SWDIO —

Serial wire debug input/output.

PIO1_3 —

General purpose digital input/output pin.

AD4 —

A/D converter, input 4.

CT32B1_MAT2 —

Match output 2 for 32-bit timer 1.

PIO1_6 —

General purpose digital input/output pin.

RXD —

Receiver input for UART.

CT32B0_MAT0 —

Match output 0 for 32-bit timer 0.

PIO1_7 —

General purpose digital input/output pin.

TXD —

Transmitter output for UART.

CT32B0_MAT1 —

Match output 1 for 32-bit timer 0.

3.3 V supply voltage to the internal regulator and the external rail.

3.3 V supply voltage to the ADC. Also used as the ADC reference voltage.

Input to the oscillator circuit and internal clock generator circuits. Input voltage must not exceed 1.8 V.

Output from the oscillator amplifier.

Ground.

Analog ground.

[1]

[2]

[3]

[4]

Pin state at reset for default function: I = Input; O = Output; PU = internal pull-up enabled (pins pulled up to full V

DD

level); IA = inactive, no pull-up/down enabled.

RESET functionality is not available in Deep power-down mode.

5 V tolerant pad providing digital I/O functions with configurable pull-up/pull-down resistors and configurable hysteresis.

5 V tolerant pad providing digital I/O functions with configurable pull-up/pull-down resistors, configurable hysteresis, and analog input.

When configured as a ADC input, digital section of the pad is disabled and the pin is not 5 V tolerant.

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Chapter 10: LPC111x Pin configuration (LPC1100L series, TSSOP, DIP,

[5] When the system oscillator is not used, connect XTALIN and XTALOUT as follows: XTALIN can be left floating or can be grounded

(grounding is preferred to reduce susceptibility to noise). XTALOUT should be left floating.

10.4 Pin configuration (LPC1112/14)

PIO0_8/MISO0/CT16B0_MAT0

PIO0_9/MOSI0/CT16B0_MAT1

SWCLK/PIO0_10/SCK0/CT16B0_MAT2

R/PIO0_11/AD0/CT32B0_MAT3

PIO0_5/SDA

PIO0_6/SCK0

V

DDA

V

SSA

R/PIO1_0/AD1/CT32B1_CAP0

R/PIO1_1/AD2/CT32B1_MAT0

R/PIO1_2/AD3/CT32B1_MAT1

SWDIO/PIO1_3/AD4/CT32B1_MAT2

PIO1_4/AD5/CT32B1_MAT3/WAKEUP

PIO1_5/RTS/CT32B0_CAP0

13

14

9

10

11

12

3

4

1

2

7

8

5

6

LPC1112FDH28/102

LPC1114FDH28/102

28

27

26

25

PIO0_7/CTS

PIO0_4/SCL

PIO0_3

PIO0_2/SSEL0/CT16B0_CAP0

24

23

22

21

PIO0_1/CLKOUT/CT32B0_MAT2

RESET/PIO0_0

V

SS

V

DD

XTALIN 20

19

18

XTALOUT

PIO1_9/CT16B1_MAT0

17

16

15

PIO1_8/CT16B1_CAP0

PIO1_7/TXD/CT32B0_MAT1

PIO1_6/RXD/CT32B0_MAT0

002aag598

Fig 25. Pin configuration TSSOP28 package

PIO0_8/MISO0/CT16B0_MAT0

PIO0_9/MOSI0/CT16B0_MAT1

SWCLK/PIO0_10/SCK0/CT16B0_MAT2

R/PIO0_11/AD0/CT32B0_MAT3

PIO0_5/SDA

PIO0_6/SCK0

5

6

V

DDA

V

SSA

R/PIO1_0/AD1/CT32B1_CAP0

7

8

R/PIO1_1/AD2/CT32B1_MAT0

R/PIO1_2/AD3/CT32B1_MAT1

SWDIO/PIO1_3/AD4/CT32B1_MAT2

PIO1_4/AD5/CT32B1_MAT3/WAKEUP

PIO1_5/RTS/CT32B0_CAP0

9

10

11

12

13

14

3

4

1

2

LPC1114FN28/

102

002aag599

28

27

26

25

PIO0_7/CTS

PIO0_4/SCL

PIO0_3

PIO0_2/SSEL0/CT16B0_CAP0

24

23

22

21

PIO0_1/CLKOUT/CT32B0_MAT2

RESET/PIO0_0

V

SS

V

DD

XTALIN 20

19

18

XTALOUT

PIO1_9/CT16B1_MAT0

17

16

15

PIO1_8/CT16B1_CAP0

PIO1_7/TXD/CT32B0_MAT1

PIO1_6/RXD/CT32B0_MAT0

Fig 26. Pin configuration DIP28 package

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UM10398

Chapter 10: LPC111x Pin configuration (LPC1100L series, TSSOP, DIP,

Table 168. LPC1112/14 pin description table (TSSOP28 and DIP28 packages)

Symbol Start logic input

Type Reset state

[1]

Description

PIO0_0 to PIO0_11

RESET/PIO0_0

PIO0_1/CLKOUT/

CT32B0_MAT2

PIO0_2/SSEL0/

CT16B0_CAP0

PIO0_3

PIO0_4/SCL

PIO0_5/SDA

PIO0_6/SCK0

PIO0_7/CTS

PIO0_8/MISO0/

CT16B0_MAT0

PIO0_9/MOSI0/

CT16B0_MAT1

23

24

25

26

27

5

6

28

1

2

[2]

[3]

yes yes

[3]

yes

[3]

[4]

[3]

[3]

[3]

[3]

yes yes

[4]

yes yes yes yes yes

I

I/O

I/O

I/O

O

O

I/O

I

I/O

I/O

I/O

I/O

I/O

I/O

I/O

I/O

I/O

I

I/O

I/O

O

I/O

I/O

O

-

-

I; PU

I; PU

-

-

I; PU

-

-

-

I; PU

I; IA

I; IA

I; PU

-

I; PU

-

-

I; PU

-

-

-

I; PU

Port 0 —

Port 0 is a 12-bit I/O port with individual direction and function controls for each bit. The operation of port 0 pins depends on the function selected through the IOCONFIG register block.

RESET —

External reset input with 20 ns glitch filter. A LOW-going pulse as short as 50 ns on this pin resets the device, causing I/O ports and peripherals to take on their default states, and processor execution to begin at address 0.

In deep power-down mode, this pin must be pulled HIGH externally. The RESET pin can be left unconnected or be used as a

GPIO pin if an external RESET function is not needed.

PIO0_0 —

General purpose digital input/output pin with 10 ns glitch filter.

PIO0_1 —

General purpose digital input/output pin. A LOW level on this pin during reset starts the ISP command handler.

CLKOUT —

Clockout pin.

CT32B0_MAT2 —

Match output 2 for 32-bit timer 0.

PIO0_2 —

General purpose digital input/output pin.

SSEL0 —

Slave Select for SPI0.

CT16B0_CAP0 —

Capture input 0 for 16-bit timer 0.

PIO0_3 —

General purpose digital input/output pin.

PIO0_4 —

General purpose digital input/output pin (open-drain).

SCL —

I

2

C-bus, open-drain clock input/output. High-current sink only if I

2

C Fast-mode Plus is selected in the I/O configuration register.

PIO0_5 —

General purpose digital input/output pin (open-drain).

SDA —

I

2

C-bus, open-drain data input/output. High-current sink only if I

2

C Fast-mode Plus is selected in the I/O configuration register.

PIO0_6 —

General purpose digital input/output pin.

SCK0 —

Serial clock for SPI0.

PIO0_7 —

General purpose digital input/output pin (high-current output driver).

CTS —

Clear To Send input for UART.

PIO0_8 —

General purpose digital input/output pin.

MISO0 —

Master In Slave Out for SPI0.

CT16B0_MAT0 —

Match output 0 for 16-bit timer 0.

PIO0_9 —

General purpose digital input/output pin.

MOSI0 —

Master Out Slave In for SPI0.

CT16B0_MAT1 —

Match output 1 for 16-bit timer 0.

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UM10398

Chapter 10: LPC111x Pin configuration (LPC1100L series, TSSOP, DIP,

Table 168. LPC1112/14 pin description table (TSSOP28 and DIP28 packages)

…continued

Symbol Start logic input

Type Reset state

[1]

Description

SWCLK/PIO0_10/

SCK0/

CT16B0_MAT2

R/PIO0_11/

AD0/CT32B0_MAT3

PIO1_0 to PIO1_9

R/PIO1_0/

AD1/CT32B1_CAP0

R/PIO1_1/

AD2/CT32B1_MAT0

10

R/PIO1_2/

AD3/CT32B1_MAT1

SWDIO/PIO1_3/

AD4/CT32B1_MAT2

PIO1_4/AD5/

CT32B1_MAT3/

WAKEUP

3

4

9

11

12

13

[3]

yes

[5]

yes I

I

I/O

I/O

O

[5]

yes I

[5]

[5]

[5]

[5]

no no no no

I

I

I/O

O

I/O

I

I/O

I

O

I

I/O

I

O

I

I/O

O

I/O

I

I/O

O

I/O

O -

-

-

-

-

-

-

-

I; PU

I; PU

I; PU

-

-

-

I; PU

-

-

-

I; PU

-

-

-

I; PU

-

-

-

I; PU

SWCLK —

Serial wire clock.

PIO0_10 —

General purpose digital input/output pin.

SCK0 —

Serial clock for SPI0.

CT16B0_MAT2 —

Match output 2 for 16-bit timer 0.

R —

Reserved. Configure for an alternate function in the

IOCONFIG block.

PIO0_11 —

General purpose digital input/output pin.

AD0 —

A/D converter, input 0.

CT32B0_MAT3 —

Match output 3 for 32-bit timer 0.

Port 1 —

Port 1 is a 12-bit I/O port with individual direction and function controls for each bit. The operation of port 1 pins depends on the function selected through the IOCONFIG register block.

R —

Reserved. Configure for an alternate function in the

IOCONFIG block.

PIO1_0 —

General purpose digital input/output pin.

AD1 —

A/D converter, input 1.

CT32B1_CAP0 —

Capture input 0 for 32-bit timer 1.

R —

Reserved. Configure for an alternate function in the

IOCONFIG block.

PIO1_1 —

General purpose digital input/output pin.

AD2 —

A/D converter, input 2.

CT32B1_MAT0 —

Match output 0 for 32-bit timer 1.

R —

Reserved. Configure for an alternate function in the

IOCONFIG block.

PIO1_2 —

General purpose digital input/output pin.

AD3 —

A/D converter, input 3.

CT32B1_MAT1 —

Match output 1 for 32-bit timer 1.

SWDIO —

Serial wire debug input/output.

PIO1_3 —

General purpose digital input/output pin.

AD4 —

A/D converter, input 4.

CT32B1_MAT2 —

Match output 2 for 32-bit timer 1.

PIO1_4 —

General purpose digital input/output pin with 10 ns glitch filter. In Deep power-down mode, this pin serves as the Deep power-down mode wake-up pin with 20 ns glitch filter. Pull this pin

HIGH externally before entering Deep power-down mode. Pull this pin LOW to exit Deep power-down mode. A LOW-going pulse as short as 50 ns wakes up the part.

AD5 —

A/D converter, input 5.

CT32B1_MAT3 —

Match output 3 for 32-bit timer 1.

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UM10398

Chapter 10: LPC111x Pin configuration (LPC1100L series, TSSOP, DIP,

Table 168. LPC1112/14 pin description table (TSSOP28 and DIP28 packages)

…continued

Symbol Start logic input

Type Reset state

[1]

Description

PIO1_5/RTS/

CT32B0_CAP0

PIO1_6/RXD/

CT32B0_MAT0

PIO1_7/TXD/

CT32B0_MAT1

PIO1_8/

CT16B1_CAP0

PIO1_9/

CT16B1_MAT0

V

V

DD

DDA

XTALIN

14

15

16

17

18

21

7

20

[3]

[3]

[3]

[3]

[3]

[6]

[6]

-

-

-

-

-

no no no no no

I

I

I

I

-

I/O

O

I/O

O

I/O

O

O

I/O

I/O

O

-

-

-

-

-

-

-

-

I; PU

-

I; PU

-

I; PU

-

I; PU

-

-

-

I; PU

PIO1_5 —

General purpose digital input/output pin.

RTS —

Request To Send output for UART.

CT32B0_CAP0 —

Capture input 0 for 32-bit timer 0.

PIO1_6 —

General purpose digital input/output pin.

RXD —

Receiver input for UART.

CT32B0_MAT0 —

Match output 0 for 32-bit timer 0.

PIO1_7 —

General purpose digital input/output pin.

TXD —

Transmitter output for UART.

CT32B0_MAT1 —

Match output 1 for 32-bit timer 0.

PIO1_8 —

General purpose digital input/output pin.

CT16B1_CAP0 —

Capture input 0 for 16-bit timer 1.

PIO1_9 —

General purpose digital input/output pin.

CT16B1_MAT0 —

Match output 0 for 16-bit timer 1.

3.3 V supply voltage to the internal regulator and the external rail.

3.3 V supply voltage to the ADC. Also used as the ADC reference voltage.

Input to the oscillator circuit and internal clock generator circuits.

Input voltage must not exceed 1.8 V.

Output from the oscillator amplifier.

Ground.

Analog ground.

XTALOUT

V

SS

V

SSA

19

22

8 -

O

[1]

[2]

[3]

[4]

[5]

[6]

Pin state at reset for default function: I = Input; O = Output; PU = internal pull-up enabled (pins pulled up to full V

DD

level); IA = inactive, no pull-up/down enabled.

RESET functionality is not available in Deep power-down mode. Use the WAKEUP pin to reset the chip and wake up from Deep power-down mode. An external pull-up resistor is required on this pin for the Deep power-down mode.

5 V tolerant pad providing digital I/O functions with configurable pull-up/pull-down resistors and configurable hysteresis.

I

2

C-bus pads compliant with the I

2

C-bus specification for I

2

C standard mode and I

2

C Fast-mode Plus. The pin requires an external pull-up to provide output functionality. When power is switched off, this pin is floating and does not disturb the I2C lines. Open-drain configuration applies to all functions on this pin.

5 V tolerant pad providing digital I/O functions with configurable pull-up/pull-down resistors, configurable hysteresis, and analog input.

When configured as a ADC input, digital section of the pad is disabled and the pin is not 5 V tolerant.

When the system oscillator is not used, connect XTALIN and XTALOUT as follows: XTALIN can be left floating or can be grounded

(grounding is preferred to reduce susceptibility to noise). XTALOUT should be left floating.

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Chapter 11: LPC111x Pin configuration (LPC1100XL series,

HVQFN/LQFP/TFBGA48 packages)

Rev. 12.4 — 22 December 2016 User manual

11.1 How to read this chapter

Remark:

This chapter applies to parts in the LPC1100XL series for LQFP, HVQFN, and

TFBGA48 packages.

The LPC111x are available in three packages: LQFP48 (LPC1113, LPC1114, LPC1115),

HVQFN33 (LPC1111, LPC1112, LPC1113, LPC1114), and TFBGA48 (LPC1115).

Table 169. LPC1100XL pin configurations

Part

LPC1111 Pin configuration -

LQFP48

LPC1112

LPC1113

Pin description

Pin configuration

Pin description

Pin configuration

-

-

-

Figure 27

LPC1114

LPC1115

Pin description

Pin configuration

Pin description

Pin configuration

Pin description

Table 170

Figure 27

Table 170

Figure 27

Table 170

HVQFN33

Figure 29

Table 171

Figure 29

Table 171

Figure 29

Table 171

Figure 29

-

-

Table 171

-

-

-

-

-

-

-

TFBGA48

-

Figure 28

Table 170

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11.2 LPC111x Pin configuration

UM10398

Chapter 11: LPC111x Pin configuration (LPC1100XL series,

PIO2_6/CT32B0_MAT1

PIO2_0/DTR/SSEL1

1

2

RESET/PIO0_0

PIO0_1/CLKOUT/CT32B0_MAT2

3

4

V

SS

XTALIN

5

6

XTALOUT

V

DD

PIO1_8/CT16B1_CAP0

PIO0_2/SSEL0/CT16B0_CAP0

PIO2_7/CT32B0_MAT2/RXD

PIO2_8/CT32B0_MAT3/TXD

7

8

9

10

11

12

LPC1113, LPC1114, LPC1115

32

31

30

29

36

35

34

33

28

27

26

25

PIO3_0/DTR/CT16B0_MAT0/TXD

R/PIO1_2/AD3/CT32B1_MAT1

R/PIO1_1/AD2/CT32B1_MAT0

R/PIO1_0/AD1/CT32B1_CAP0

R/PIO0_11/AD0/CT32B0_MAT3

PIO2_11/SCK0/CT32B0_CAP1

PIO1_10/AD6/CT16B1_MAT1/MISO1

SWCLK/PIO0_10/SCK0/CT16B0_MAT2

PIO0_9/MOSI0/CT16B0_MAT1

PIO0_8/MISO0/CT16B0_MAT0

PIO2_2/DCD/MISO1

PIO2_10

002aag781

Fig 27. Pin configuration LQFP48 package

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Chapter 11: LPC111x Pin configuration (LPC1100XL series,

ball A1 index area

1 2 3

LPC1115

4 5 6 7 8

A

B

C

D

E

F

G

H

Transparent top view

Fig 28. LPC1100XL series pin configuration TFBGA48 package

aaa-008364

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Chapter 11: LPC111x Pin configuration (LPC1100XL series,

terminal 1 index area

PIO2_0/DTR/SSEL1

RESET/PIO0_0

PIO0_1/CLKOUT/CT32B0_MAT2

XTALIN

XTALOUT

V

DD

PIO1_8/CT16B1_CAP0

PIO0_2/SSEL0/CT16B0_CAP0

1

2

3

4

5

6

7

8

33 V

SS

24

23

22

21

20

19

18

17

R/PIO1_2/AD3/CT32B1_MAT1

R/PIO1_1/AD2/CT32B1_MAT0

R/PIO1_0/AD1/CT32B1_CAP0

R/PIO0_11/AD0/CT32B0_MAT3

PIO1_10/AD6/CT16B1_MAT1/MISO1

SWCLK/PIO0_10/SCK0/CT16B0_MAT2

PIO0_9/MOSI0/CT16B0_MAT1

PIO0_8/MISO0/CT16B0_MAT0

002aag782

Fig 29. Pin configuration HVQFN33 package

Transparent top view

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Chapter 11: LPC111x Pin configuration (LPC1100XL series,

11.3 LPC1100XL Pin description

Table 170. LPC1100XL series: LPC1113/14/15 pin description table (LQFP48 and TFBGA48 package)

Symbol Start logic input

Type Reset state

[1]

Description

PIO0_0 to PIO0_11

RESET/PIO0_0

PIO0_1/CLKOUT/

CT32B0_MAT2

PIO0_2/SSEL0/

CT16B0_CAP0

PIO0_3

PIO0_4/SCL

PIO0_5/SDA

PIO0_6/SCK0

PIO0_7/CTS

PIO0_8/MISO0/

CT16B0_MAT0

UM10398

User manual

3

[2]

4

[3]

10

[3]

14

[3]

15

[4]

16

[4]

22

[3]

23

[3]

27

[3]

C1

C2

F1

H2

G3

H3

H6

G7

[3]

F8

[2]

[3]

[3]

[3]

[4]

[4]

[3]

[3]

yes yes yes yes yes yes yes yes yes

I

I

I/O

I/O

I/O

O

O

I/O

I/O

I/O

I/O

I/O

I/O

I/O

I/O

I/O

I/O

I

I/O

I/O

O

-

-

-

-

-

-

I; PU

I; PU

-

-

I; PU

-

-

I; PU

I; IA

I; IA

I; PU

-

I; PU

I; PU

Port 0 —

Port 0 is a 12-bit I/O port with individual direction and function controls for each bit. The operation of port 0 pins depends on the function selected through the IOCONFIG register block.

RESET —

External reset input with 20 ns glitch filter. A

LOW-going pulse as short as 50 ns on this pin resets the device, causing I/O ports and peripherals to take on their default states, and processor execution to begin at address 0.

In deep power-down mode, this pin must be pulled

HIGH externally. The RESET pin can be left unconnected or be used as a GPIO pin if an external

RESET function is not needed.

PIO0_0 —

General purpose digital input/output pin with

10 ns glitch filter.

PIO0_1 —

General purpose digital input/output pin. A

LOW level on this pin during reset starts the ISP command handler.

CLKOUT —

Clockout pin.

CT32B0_MAT2 —

Match output 2 for 32-bit timer 0.

PIO0_2 —

General purpose digital input/output pin.

SSEL0 —

Slave Select for SPI0.

CT16B0_CAP0 —

Capture input 0 for 16-bit timer 0.

PIO0_3 —

General purpose digital input/output pin.

PIO0_4 —

General purpose digital input/output pin

(open-drain).

SCL —

I

2

C-bus, open-drain clock input/output.

High-current sink only if I

2

C Fast-mode Plus is selected in the I/O configuration register.

PIO0_5 —

General purpose digital input/output pin

(open-drain).

SDA —

I

2

C-bus, open-drain data input/output.

High-current sink only if I

2

C Fast-mode Plus is selected in the I/O configuration register.

PIO0_6 —

General purpose digital input/output pin.

SCK0 —

Serial clock for SPI0.

PIO0_7 —

General purpose digital input/output pin

(high-current output driver).

CTS —

Clear To Send input for UART.

PIO0_8 —

MISO0 —

General purpose digital input/output pin.

Master In Slave Out for SPI0.

CT16B0_MAT0 —

All information provided in this document is subject to legal disclaimers.

Rev. 12.4 — 22 December 2016

Match output 0 for 16-bit timer 0.

© NXP B.V. 2016. All rights reserved.

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UM10398

Chapter 11: LPC111x Pin configuration (LPC1100XL series,

Table 170. LPC1100XL series: LPC1113/14/15 pin description table (LQFP48 and TFBGA48 package)

…continued

Symbol Start logic input

Type Reset state

[1]

Description

PIO0_9/MOSI0/

CT16B0_MAT1

SWCLK/PIO0_10/

SCK0/

CT16B0_MAT2

R/PIO0_11/

AD0/CT32B0_MAT3

PIO1_0 to PIO1_11

R/PIO1_0/

AD1/CT32B1_CAP0

R/PIO1_1/

AD2/CT32B1_MAT0

R/PIO1_2/

AD3/CT32B1_MAT1

SWDIO/PIO1_3/

AD4/CT32B1_MAT2

28

[3]

29

32

33

34

35

39

[3]

[5]

[5]

[5]

[5]

[5]

F7

E7

D8

C7

C8

B7

B6

[3]

[3]

[5]

[5]

[5]

[5]

[5]

yes yes yes yes no no no

I

I

I

I

I

I

I

I

I/O

I/O

O

I

I

I/O

I/O

O

I/O

O

I/O

I/O

O

I/O

O

I/O

O

I/O

I/O

O

-

-

-

-

-

I; PU

-

-

-

I; PU

I; PU

I; PU

-

-

-

I; PU

-

-

-

I; PU

-

-

-

-

-

-

I; PU

PIO0_9 —

General purpose digital input/output pin.

MOSI0 —

Master Out Slave In for SPI0.

CT16B0_MAT1 —

Match output 1 for 16-bit timer 0.

SWCLK —

Serial wire clock.

PIO0_10 —

General purpose digital input/output pin.

SCK0 —

Serial clock for SPI0.

CT16B0_MAT2 —

Match output 2 for 16-bit timer 0.

R —

Reserved. Configure for an alternate function in the IOCONFIG block.

PIO0_11 —

General purpose digital input/output pin.

AD0 —

A/D converter, input 0.

CT32B0_MAT3 —

Match output 3 for 32-bit timer 0.

Port 1 —

Port 1 is a 12-bit I/O port with individual direction and function controls for each bit. The operation of port 1 pins depends on the function selected through the IOCONFIG register block.

R —

Reserved. Configure for an alternate function in the IOCONFIG block.

PIO1_0 —

General purpose digital input/output pin.

AD1 —

A/D converter, input 1.

CT32B1_CAP0 —

Capture input 0 for 32-bit timer 1.

R —

Reserved. Configure for an alternate function in the IOCONFIG block.

PIO1_1 —

General purpose digital input/output pin.

AD2 —

A/D converter, input 2.

CT32B1_MAT0 —

Match output 0 for 32-bit timer 1.

R —

Reserved. Configure for an alternate function in the IOCONFIG block.

PIO1_2 —

General purpose digital input/output pin.

AD3 —

A/D converter, input 3.

CT32B1_MAT1 —

Match output 1 for 32-bit timer 1.

SWDIO —

Serial wire debug input/output.

PIO1_3 —

General purpose digital input/output pin.

AD4 —

A/D converter, input 4.

CT32B1_MAT2 —

Match output 2 for 32-bit timer 1.

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UM10398

Chapter 11: LPC111x Pin configuration (LPC1100XL series,

Table 170. LPC1100XL series: LPC1113/14/15 pin description table (LQFP48 and TFBGA48 package)

…continued

Symbol Start logic input

Type Reset state

[1]

Description

PIO1_4/AD5/

CT32B1_MAT3/

WAKEUP

PIO1_5/RTS/

CT32B0_CAP0

PIO1_6/RXD/

CT32B0_MAT0

PIO1_7/TXD/

CT32B0_MAT1

PIO1_8/

CT16B1_CAP0

PIO1_9/

CT16B1_MAT0/

MOSI1

PIO1_10/AD6/

CT16B1_MAT1/

MISO1

PIO1_11/AD7/

CT32B1_CAP1

PIO2_0 to PIO2_11

PIO2_0/DTR/SSEL1

PIO2_1/DSR/SCK1

40

[5]

45

46

47

9

[3]

17

30

42

2

[3]

13

[3]

[3]

[3]

[3]

[5]

[5]

[3]

A6

A3

B3

B2

F2

G4

E8

A5

B1

H1

[5]

[3]

[3]

[3]

[3]

[3]

[5]

[5]

[3]

[3]

no no no no no no no no no no

I

I

I

I

I

I

I

I

I/O

O

I/O

O

I/O

O

I/O

O

O

I/O

I/O

O

I/O

I/O

O

I/O

I/O

I/O

I/O

O

I/O

I/O

I/O

I; PU

-

-

I; PU

-

-

I; PU

-

I; PU

-

I; PU

-

-

-

I; PU

-

-

-

I; PU

-

-

-

I; PU

-

-

-

I; PU

-

-

I; PU

PIO1_4 —

General purpose digital input/output pin with

10 ns glitch filter. In Deep power-down mode, this pin serves as the Deep power-down mode wake-up pin with 20 ns glitch filter. Pull this pin HIGH externally before entering Deep power-down mode. Pull this pin

LOW to exit Deep power-down mode. A LOW-going pulse as short as 50 ns wakes up the part.

AD5 —

A/D converter, input 5.

CT32B1_MAT3 —

Match output 3 for 32-bit timer 1.

PIO1_5 —

General purpose digital input/output pin.

RTS —

Request To Send output for UART.

CT32B0_CAP0 —

Capture input 0 for 32-bit timer 0.

PIO1_6 —

General purpose digital input/output pin.

RXD —

Receiver input for UART.

CT32B0_MAT0 —

Match output 0 for 32-bit timer 0.

PIO1_7 —

General purpose digital input/output pin.

TXD —

Transmitter output for UART.

CT32B0_MAT1 —

Match output 1 for 32-bit timer 0.

PIO1_8 —

General purpose digital input/output pin.

CT16B1_CAP0 —

Capture input 0 for 16-bit timer 1.

PIO1_9 —

General purpose digital input/output pin.

CT16B1_MAT0 —

Match output 0 for 16-bit timer 1.

MOSI1 —

Master Out Slave In for SPI1.

PIO1_10 —

General purpose digital input/output pin.

AD6 —

A/D converter, input 6.

CT16B1_MAT1 —

Match output 1 for 16-bit timer 1.

MISO1 —

Master In Slave Out for SPI1.

PIO1_11 —

General purpose digital input/output pin.

AD7 —

A/D converter, input 7.

CT32B1_CAP1 —

Capture input 1 for 32-bit timer 1.

Port 2 —

Port 2 is a 12-bit I/O port with individual direction and function controls for each bit. The operation of port 2 pins depends on the function selected through the IOCONFIG register block.

PIO2_0 —

General purpose digital input/output pin.

DTR —

Data Terminal Ready output for UART.

SSEL1 —

Slave Select for SPI1.

PIO2_1 —

General purpose digital input/output pin.

DSR —

Data Set Ready input for UART.

SCK1 —

Serial clock for SPI1.

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UM10398

Chapter 11: LPC111x Pin configuration (LPC1100XL series,

Table 170. LPC1100XL series: LPC1113/14/15 pin description table (LQFP48 and TFBGA48 package)

…continued

Symbol Start logic input

Type Reset state

[1]

Description

PIO2_2/DCD/MISO1 26

[3]

PIO2_3/RI/MOSI1

PIO2_4/

CT16B1_MAT1/

SSEL1

19

[3]

PIO2_5/

CT32B0_MAT0

20

[3]

PIO2_6/

CT32B0_MAT1

1

[3]

PIO2_7/

CT32B0_MAT2/RXD

11

[3]

PIO2_8/

CT32B0_MAT3/TXD

PIO2_9/

CT32B0_CAP0

PIO2_10

PIO2_11/SCK0/

CT32B0_CAP1

PIO3_0 to PIO3_5

PIO3_0/DTR/

CT16B0_MAT0/TXD

PIO3_1/DSR/

CT16B0_MAT1/RXD

38

12

24

25

31

36

37

[3]

[3]

[3]

[3]

[3]

[3]

[3]

G8

A7

G5

H5

A1

G2

G1

H7

H8

D7

B8

A8

[3]

[3]

[3]

[3]

[3]

[3]

[3]

[3]

[3]

[3]

[3]

[3]

no no no no no no no no no no no no

I

I

I

I/O

I/O

I/O

I

I/O

O

O

I

I/O

I/O

I/O

O

I/O

O

O

O

I/O

O

I/O

I

I/O

I

I/O

I/O

I/O

I/O

O

O

O

I/O

O

-

-

I; PU

-

-

-

-

I; PU

-

-

-

I; PU

-

I; PU

-

I; PU

-

-

I; PU

-

I; PU

-

I; PU

-

-

-

-

-

I; PU

-

I; PU

I; PU

I; PU

PIO2_2 —

General purpose digital input/output pin.

DCD —

Data Carrier Detect input for UART.

MISO1 —

Master In Slave Out for SPI1.

PIO2_3 —

General purpose digital input/output pin.

RI —

Ring Indicator input for UART.

MOSI1 —

Master Out Slave In for SPI1.

PIO2_4 —

General purpose digital input/output pin.

CT16B1_MAT1 —

Match output 1 for 16-bit timer 1.

SSEL1 —

Slave Select for SPI1.

PIO2_5 —

General purpose digital input/output pin.

CT32B0_MAT0 —

Match output 0 for 32-bit timer 0.

PIO2_6 —

General purpose digital input/output pin.

CT32B0_MAT1 —

Match output 1 for 32-bit timer 0.

PIO2_7 —

General purpose digital input/output pin.

CT32B0_MAT2 —

Match output 2 for 32-bit timer 0.

RXD —

Receiver input for UART.

PIO2_8 —

General purpose digital input/output pin.

CT32B0_MAT3 —

Match output 3 for 32-bit timer 0.

TXD —

Transmitter output for UART.

PIO2_9 —

General purpose digital input/output pin.

CT32B0_CAP0 —

Capture input 0 for 32-bit timer 0.

PIO2_10 —

General purpose digital input/output pin.

PIO2_11 —

General purpose digital input/output pin.

SCK0 —

Serial clock for SPI0.

CT32B0_CAP1 —

Capture input for 32-bit timer 0.

Port 3 —

Port 3 is a 12-bit I/O port with individual direction and function controls for each bit. The operation of port 3 pins depends on the function selected through the IOCONFIG register block. Pins

PIO3_6 to PIO3_11 are not available.

PIO3_0 —

General purpose digital input/output pin.

DTR —

Data Terminal Ready output for UART.

CT16B0_MAT0 —

Match output 0 for 16-bit timer 0.

TXD —

Transmitter Output for UART.

PIO3_1 —

General purpose digital input/output pin.

DSR —

Data Set Ready input for UART.

CT16B0_MAT1 —

Match output 1 for 16-bit timer 0.

RXD —

Receiver input for UART.

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185 of 548

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UM10398

Chapter 11: LPC111x Pin configuration (LPC1100XL series,

Table 170. LPC1100XL series: LPC1113/14/15 pin description table (LQFP48 and TFBGA48 package)

…continued

Symbol Start logic input

Type Reset state

[1]

Description

PIO3_2/DCD/

CT16B0_MAT2/

SCK1

PIO3_3/RI/

CT16B0_CAP0

PIO3_4/

CT16B0_CAP1/RXD

PIO3_5/

CT16B1_CAP1/TXD

V

DD

XTALIN

43

48

18

21

8; 44

6

[6]

[3]

[3]

[3]

[3]

A4

A2

H4

G6

[3]

[3]

[3]

[3]

E2;

B4

D1

[6]

-

no no no no

I

I

I

I

I

I

I

I

I/O

O

I/O

I/O

I/O

I/O

O

-

-

-

-

-

-

-

I; PU

-

I; PU

-

-

I; PU

-

-

-

I; PU

PIO3_2 —

General purpose digital input/output pin.

DCD —

Data Carrier Detect input for UART.

CT16B0_MAT2 —

Match output 2 for 16-bit timer 0.

SCK1 —

Serial clock for SPI1.

PIO3_3 —

General purpose digital input/output pin.

RI —

Ring Indicator input for UART.

CT16B0_CAP0 —

Capture input 0 for 16-bit timer 0.

PIO3_4 —

General purpose digital input/output pin.

CT16B0_CAP1 —

Capture input 1 for 16-bit timer 0.

RXD —

Receiver input for UART

PIO3_5 —

General purpose digital input/output pin.

CT16B1_CAP1 —

Capture input 1 for 16-bit timer 1.

TXD —

Transmitter output for UART

3.3 V supply voltage to the internal regulator, the external rail, and the ADC. Also used as the ADC reference voltage.

Input to the oscillator circuit and internal clock generator circuits. Input voltage must not exceed 1.8 V.

Output from the oscillator amplifier.

Ground.

XTALOUT

V

SS

7

[6]

5; 41

E1

[6]

D2;

B5

-

-

I

O

[1]

[2]

[3]

[4]

[5]

[6]

Pin state at reset for default function: I = Input; O = Output; PU = internal pull-up enabled (pins pulled up to full V

DD

level (V

DD

= 3.3 V));

IA = inactive, no pull-up/down enabled.

5 V tolerant pad. RESET functionality is not available in Deep power-down mode. Use the WAKEUP pin to reset the chip and wake up from Deep power-down mode. An external pull-up resistor is required on this pin for the Deep power-down mode.

5 V tolerant pad providing digital I/O functions with configurable pull-up/pull-down resistors and configurable hysteresis.

I

2

C-bus pads compliant with the I

2

C-bus specification for I

2

C standard mode and I

2

C Fast-mode Plus. The pin requires an external pull-up to provide output functionality. When power is switched off, this pin is floating and does not disturb the I2C lines. Open-drain configuration applies to all functions on this pin.

5 V tolerant pad providing digital I/O functions with configurable pull-up/pull-down resistors, configurable hysteresis, and analog input.

When configured as a ADC input, digital section of the pad is disabled and the pin is not 5 V tolerant.

When the system oscillator is not used, connect XTALIN and XTALOUT as follows: XTALIN can be left floating or can be grounded

(grounding is preferred to reduce susceptibility to noise). XTALOUT should be left floating.

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NXP Semiconductors

UM10398

Chapter 11: LPC111x Pin configuration (LPC1100XL series,

Table 171. LPC1111/12/13/14XL pin description table (HVQFN33 package)

Symbol Pin Start logic input

Type Reset state

[1]

Description

PIO0_0 to PIO0_11

Port 0 —

Port 0 is a 12-bit I/O port with individual direction and function controls for each bit. The operation of port 0 pins depends on the function selected through the IOCONFIG register block.

RESET/PIO0_0 2

[2]

yes I I;PU

RESET —

External reset input with 20 ns glitch filter. A LOW-going pulse as short as 50 ns on this pin resets the device, causing I/O ports and peripherals to take on their default states and processor execution to begin at address 0.

In deep power-down mode, this pin must be pulled HIGH externally.

The RESET pin can be left unconnected or be used as a GPIO pin if an external RESET function is not needed.

I/O -

PIO0_1/CLKOUT/

CT32B0_MAT2

3

[3]

yes I/O I;PU

PIO0_0 —

General purpose digital input/output pin with 10 ns glitch filter.

PIO0_1 —

General purpose digital input/output pin. A LOW level on this pin during reset starts the ISP command handler.

PIO0_2/SSEL0/

CT16B0_CAP0

PIO0_3

PIO0_4/SCL

PIO0_5/SDA

8

9

[3]

[3]

10

11

[4]

[4]

yes yes yes yes

I

I/O

I/O

I/O

O

O

I/O

I/O

I/O

I/O -

-

-

-

-

-

I;PU

I;PU

I;PU

I;PU

CLKOUT —

PIO0_2 —

SSEL0 —

PIO0_3 —

Clock out pin.

CT32B0_MAT2 —

CT16B0_CAP0 —

Match output 2 for 32-bit timer 0.

General purpose digital input/output pin.

Slave select for SPI0.

Capture input 0 for 16-bit timer 0.

General purpose digital input/output pin.

PIO0_4 —

General purpose digital input/output pin (open-drain).

SCL —

I

2

C-bus, open-drain clock input/output. High-current sink only if I

2

C Fast-mode Plus is selected in the I/O configuration register.

PIO0_5 —

General purpose digital input/output pin (open-drain).

SDA —

I

2

C-bus, open-drain data input/output. High-current sink only if

I

2

C Fast-mode Plus is selected in the I/O configuration register.

PIO0_6/SCK0

15

[3]

yes

PIO0_7/CTS

PIO0_8/MISO0/

CT16B0_MAT0

16

17

[3]

[3]

yes yes

I/O

I/O

I/O

-

I;PU

I;PU

PIO0_6 —

General purpose digital input/output pin.

SCK0 —

Serial clock for SPI0.

PIO0_7 —

General purpose digital input/output pin (high-current output driver).

CTS —

Clear To Send input for UART.

PIO0_8 —

General purpose digital input/output pin.

MISO0 —

Master In Slave Out for SPI0.

CT16B0_MAT0 —

Match output 0 for 16-bit timer 0.

PIO0_9/MOSI0/

CT16B0_MAT1

18

19

[3]

[3]

yes yes

I/O

I/O

I

O

I

I/O

I/O

O

SWCLK/PIO0_10/

SCK0/

CT16B0_MAT2

I/O

I/O

O

-

-

-

-

-

-

I;PU

-

I;PU

-

I;PU

PIO0_9 —

General purpose digital input/output pin.

MOSI0 —

Master Out Slave In for SPI0.

CT16B0_MAT1 —

Match output 1 for 16-bit timer 0.

SWCLK —

Serial wire clock.

PIO0_10 —

General purpose digital input/output pin.

SCK0 —

Serial clock for SPI0.

CT16B0_MAT2 —

Match output 2 for 16-bit timer 0.

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NXP Semiconductors

UM10398

Chapter 11: LPC111x Pin configuration (LPC1100XL series,

Table 171. LPC1111/12/13/14XL pin description table (HVQFN33 package)

…continued

Symbol Pin Start logic input

Type Reset state

[1]

Description

R/PIO0_11/AD0/

CT32B0_MAT3

21

[5]

yes -

I/O -

I;PU

R —

block.

Reserved. Configure for an alternate function in the IOCONFIG

PIO0_11 —

General purpose digital input/output pin.

I

O -

-

PIO1_0 to PIO1_11

R/PIO1_0/AD1/

CT32B1_CAP0

22

[5]

yes I;PU

AD0 —

A/D converter, input 0.

CT32B0_MAT3 —

Match output 3 for 32-bit timer 0.

Port 1 —

Port 1 is a 12-bit I/O port with individual direction and function controls for each bit. The operation of port 1 pins depends on the function selected through the IOCONFIG register block.

R —

Reserved. Configure for an alternate function in the IOCONFIG block.

PIO1_0 —

General purpose digital input/output pin.

R/PIO1_1/AD2/

CT32B1_MAT0

23

[5]

no

I

I

-

I/O

-

-

-

I;PU

AD1 —

R —

block.

A/D converter, input 1.

CT32B1_CAP0 —

Capture input 0 for 32-bit timer 1.

Reserved. Configure for an alternate function in the IOCONFIG

R/PIO1_2/AD3/

CT32B1_MAT1

24

[5]

no

I

I/O

-

O

-

-

-

I;PU

PIO1_1 —

General purpose digital input/output pin.

AD2 —

A/D converter, input 2.

CT32B1_MAT0 —

Match output 0 for 32-bit timer 1.

R —

Reserved. Configure for an alternate function in the IOCONFIG block.

PIO1_2 —

General purpose digital input/output pin.

SWDIO/PIO1_3/

AD4/CT32B1_MAT2

25

26

[5]

[5]

no no

I/O

I

O

I/O

I/O

I

O

I/O

-

-

-

-

-

-

I;PU

I;PU PIO1_4/AD5/

CT32B1_MAT3/

WAKEUP

AD3 —

A/D converter, input 3.

CT32B1_MAT1 —

Match output 1 for 32-bit timer 1.

SWDIO —

Serial wire debug input/output.

PIO1_3 —

General purpose digital input/output pin.

AD4 —

A/D converter, input 4.

CT32B1_MAT2 —

Match output 2 for 32-bit timer 1.

PIO1_4 —

General purpose digital input/output pin with 10 ns glitch filter. In Deep power-down mode, this pin serves as the Deep power-down mode wake-up pin with 20 ns glitch filter. Pull this pin

HIGH externally before entering Deep power-down mode. Pull this pin

LOW to exit Deep power-down mode. A LOW-going pulse as short as

50 ns wakes up the part.

PIO1_5/RTS/

CT32B0_CAP0

PIO1_6/RXD/

CT32B0_MAT0

30

31

[3]

[3]

no no

I

I/O

I

O

I

O

I/O

O

-

-

-

I;PU

-

-

-

I;PU

AD5 —

A/D converter, input 5.

CT32B1_MAT3 —

Match output 3 for 32-bit timer 1.

PIO1_5 —

General purpose digital input/output pin.

RTS —

Request To Send output for UART.

CT32B0_CAP0 —

Capture input 0 for 32-bit timer 0.

PIO1_6 —

General purpose digital input/output pin.

RXD —

Receiver input for UART.

CT32B0_MAT0 —

Match output 0 for 32-bit timer 0.

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Chapter 11: LPC111x Pin configuration (LPC1100XL series,

Table 171. LPC1111/12/13/14XL pin description table (HVQFN33 package)

…continued

Symbol Pin Start logic input

Type Reset state

[1]

Description

PIO1_7/TXD/

CT32B0_MAT1

32

[3]

no I/O I;PU

PIO1_7 —

General purpose digital input/output pin.

O

O -

-

TXD —

Transmitter output for UART.

CT32B0_MAT1 —

Match output 1 for 32-bit timer 0.

PIO1_8/

CT16B1_CAP0

7

[3]

no

I

I/O

-

I;PU

PIO1_8 —

General purpose digital input/output pin.

CT16B1_CAP0 —

Capture input 0 for 16-bit timer 1.

12

[3]

no PIO1_9/

CT16B1_MAT0/

MOSI

I/O

O -

I;PU

PIO1_9 —

General purpose digital input/output pin.

CT16B1_MAT0 —

Match output 0 for 16-bit timer 1.

20

[5]

no

I/O

I/O

-

I;PU

MOSI —

Master Out Slave In for SPI1

PIO1_10 —

General purpose digital input/output pin.

PIO1_10/AD6/

CT16B1_MAT1/

MISO

I

O

-

-

AD6 —

A/D converter, input 6.

CT16B1_MAT1 —

Match output 1 for 16-bit timer 1.

PIO1_11/AD7/

CT32B1_CAP1

PIO2_0

27

[5]

no

I

I

I/O

I/O

-

-

-

I;PU

MISO1 —

AD7 —

Master In Slave Out for SPI1

PIO1_11 —

General purpose digital input/output pin.

A/D converter, input 7.

CT32B1_CAP1 —

Capture input 1 for 32-bit timer 1.

Port 2 —

Port 2 is a 12-bit I/O port with individual direction and function controls for each bit. The operation of port 2 pins depends on the function selected through the IOCONFIG register block. Pins

PIO2_1 to PIO2_11 are not available.

PIO2_0/DTR/SSEL1 1

[3]

no

PIO3_0 to PIO3_5

28

[3]

no

I/O

O

I/O -

-

I;PU

PIO2_0 —

General purpose digital input/output pin.

DTR —

Data Terminal Ready output for UART.

SSEL1 —

Slave Select for SPI1.

Port 3 —

Port 3 is a 12-bit I/O port with individual direction and function controls for each bit. The operation of port 3 pins depends on the function selected through the IOCONFIG register block. Pins

PIO3_0, PIO3_1, PIO3_3 and PIO3_6 to PIO3_11 are not available.

PIO3_2 —

General purpose digital input/output pin.

PIO3_2/

CT16B0_MAT2/

SCK1

PIO3_4/

CT16B0_CAP1/RXD

PIO3_5/

CT16B1_CAP1/TXD

13

14

[3]

[3]

no no

I

I/O

O

I/O

I/O

I

I/O

-

-

I;PU

CT16B0_MAT2 —

SCK1 —

Match output 2 for 16-bit timer 0.

Serial clock for SPI1.

PIO3_4 —

General purpose digital input/output pin.

CT16B0_CAP1 —

Capture input 1 for 16-bit timer 0.

I

O -

-

-

I;PU

-

I;PU

RXD —

Receiver input for UART.

PIO3_5 —

General purpose digital input/output pin.

CT16B1_CAP1 —

Capture input 1 for 16-bit timer 1.

TXD —

Transmitter output for UART.

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Chapter 11: LPC111x Pin configuration (LPC1100XL series,

Table 171. LPC1111/12/13/14XL pin description table (HVQFN33 package)

…continued

Symbol Pin Start logic input

Type Reset state

[1]

Description

V

DD

6; 29 I -

XTALIN

XTALOUT

V

SS

4

5

[6]

[6]

33

-

-

-

-

I

O -

-

-

3.3 V supply voltage to the internal regulator, the external rail, and the

ADC. Also used as the ADC reference voltage.

Input to the oscillator circuit and internal clock generator circuits. Input voltage must not exceed 1.8 V.

Output from the oscillator amplifier.

Thermal pad. Connect to ground.

[1]

[2]

[3]

[4]

[5]

[6]

Pin state at reset for default function: I = Input; O = Output; PU = internal pull-up enabled (pins pulled up to full V

DD

level (V

DD

= 3.3 V));

IA = inactive, no pull-up/down enabled.

RESET functionality is not available in Deep power-down mode. Use the WAKEUP pin to reset the chip and wake up from Deep power-down mode. An external pull-up resistor is required on this pin for the Deep power-down mode.

5 V tolerant pad providing digital I/O functions with configurable pull-up/pull-down resistors and configurable hysteresis.

I

2

C-bus pads compliant with the I

2

C-bus specification for I

2

C standard mode and I

2

C Fast-mode Plus. The pin requires an external pull-up to provide output functionality. When power is switched off, this pin is floating and does not disturb the I2C lines. Open-drain configuration applies to all functions on this pin.

5 V tolerant pad providing digital I/O functions with configurable pull-up/pull-down resistors, configurable hysteresis, and analog input.

When configured as a ADC input, digital section of the pad is disabled, and the pin is not 5 V tolerant.

When the system oscillator is not used, connect XTALIN and XTALOUT as follows: XTALIN can be left floating or can be grounded

(grounding is preferred to reduce susceptibility to noise). XTALOUT should be left floating.

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Chapter 12: LPC111x/LPC11Cxx General Purpose I/O (GPIO)

Rev. 12.4 — 22 December 2016 User manual

12.1 How to read this chapter

The number of GPIO pins available on each port depends on the LPC111x/LPC11Cxx part and the package. See

Table 172 for available GPIO pins:

Table 172. GPIO configuration

Part

LPC1110

LPC1111

LPC1112

LPC1113

LPC1114

LPC11D14

LPC11C12

LPC11C14

LPC11C22

LPC11C24

Package

SO20/

TSSOP20

HVQFN33

TSSOP20

TSSOP28

HVQFN33

HVQFN33

HVQFN33

LQFP48

TSSOP28

HVQFN33

LQFP48

LQFP100

LQFP48

LQFP48

LQFP48

LQFP48

GPIO port 0 GPIO port 1 GPIO port 2 GPIO port 3

PIO0_0 to PIO0_2;

PIO0_4 to PIO0_6;

PIO0_8 to PIO0_11

PIO1_0 to PIO1_3;

PIO1_6 to PIO1_7

-

PIO0_0 to PIO0_11 PIO1_0 to PIO1_11 PIO2_0

-

PIO0_0 to PIO0_3;

PIO0_8 to PIO0_11

PIO1_0 to PIO1_3;

PIO1_6 to PIO1_7

-

PIO0_0 to PIO0_11 PIO1_0 to PIO1_9 -

PIO0_0 to PIO0_11 PIO1_0 to PIO1_11 PIO2_0

-

PIO3_2; PIO3_4; PIO3_5 28

14

-

22

PIO3_2; PIO3_4; PIO3_5 28

PIO0_0 to PIO0_3;

PIO0_4 to PIO0_11

PIO1_0 to PIO1_4;

PIO1_6 to PIO1_8

-

PIO0_0 to PIO0_11 PIO1_0 to PIO1_11 PIO2_0

PIO0_0 to PIO0_11 PIO1_0 to PIO1_11 PIO2_0 to PIO2_11

PIO0_0 to PIO0_11 PIO1_0 to PIO1_9 -

PIO0_0 to PIO0_11 PIO1_0 to PIO1_11 PIO2_0

PIO3_2; PIO3_4; PIO3_5 28

PIO3_0 to PIO3_5 42

22

PIO3_2; PIO3_4; PIO3_5 28

PIO0_0 to PIO0_11 PIO1_0 to PIO1_11 PIO2_0 to PIO2_11

PIO0_0 to PIO0_11 PIO1_0 to PIO1_11 PIO2_0 to PIO2_11

PIO3_0 to PIO3_5

PIO3_0 to PIO3_5

PIO0_0 to PIO0_11 PIO1_0 to PIO1_11 PIO2_0 to PIO2_11 PIO3_0 to PIO3_3

PIO0_0 to PIO0_11 PIO1_0 to PIO1_11 PIO2_0 to PIO2_11 PIO3_0 to PIO3_3

PIO3_0 to PIO3_3 PIO0_0 to PIO0_11 PIO1_0 to PIO1_11 except PIO1_9

PIO2_0 to PIO2_11 except PIO2_4,

PIO2_5, PIO2_9

PIO0_0 to PIO0_11 PIO1_0 to PIO1_11 except PIO1_9

PIO2_0 to PIO2_11 except PIO2_4,

PIO2_5, PIO2_9

PIO3_0 to PIO3_3

42

42

40

40

36

36

Total

GPIO pins

16

Register bits corresponding to PIOn_m pins which are not available are reserved.

12.2 Introduction

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12.2.1 Features

GPIO pins can be configured as input or output by software.

Each individual port pin can serve as an edge or level-sensitive interrupt request.

Interrupts can be configured on single falling or rising edges and on both edges.

Level-sensitive interrupt pins can be HIGH or LOW-active.

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Chapter 12: LPC111x/LPC11Cxx General Purpose I/O (GPIO)

All GPIO pins are inputs by default.

Reading and writing of data registers are masked by address bits 13:2.

12.3 Register description

Each GPIO register can be up to 12 bits wide and can be read or written using word or half-word operations at word addresses.

Table 173. Register overview: GPIO (base address port 0: 0x5000 0000; port 1: 0x5001 0000, port 2: 0x5002 0000; port 3: 0x5003 0000)

Name Access Address offset Description

GPIOnDATA R/W 0x0000 to 0x3FF8

Reset value

n/a

-

GPIOnDATA R/W 0x3FFC

Port n data address masking register locations for pins PIOn_0 to PIOn_11 (see

Section 12.4.1

).

Port n data register for pins PIOn_0 to

PIOn_11 reserved n/a

GPIOnDIR

GPIOnIS

GPIOnIBE

GPIOnIEV

R/W

R/W

R/W

R/W

0x8000

0x8004

0x8008

0x800C

Data direction register for port n

Interrupt sense register for port n

Interrupt both edges register for port n

Interrupt event register for port n

0x00

0x00

0x00

0x00

-

GPIOnIE

GPIOnRIS

GPIOnMIS

GPIOnIC

-

R/W

R

R

W

0x8010

0x8014

0x8018

0x801C

0x8020 - 0xFFFF

Interrupt mask register for port n

Raw interrupt status register for port n

Masked interrupt status register for port n

Interrupt clear register for port n reserved

0x00

0x00

0x00

0x00

0x00

12.3.1 GPIO data register

The GPIOnDATA register holds the current logic state of the pin (HIGH or LOW), independently of whether the pin is configured as an GPIO input or output or as another digital function. If the pin is configured as GPIO output, the current value of the

GPIOnDATA register is driven to the pin.

Table 174. GPIOnDATA register (GPIO0DATA, address 0x5000 0000 to 0x5000 3FFC;

GPIO1DATA, address 0x5001 0000 to 0x5001 3FFC; GPIO2DATA, address 0x5002

0000 to 0x5002 3FFC; GPIO3DATA, address 0x5003 0000 to 0x5003 3FFC) bit description

Bit Symbol Description Reset value

Access

11:0 DATA R/W

31:12 -

Logic levels for pins PIOn_0 to PIOn_11. HIGH = 1, LOW =

0.

n/a

Reserved -

A read of the GPIOnDATA register always returns the current logic level (state) of the pin independently of its configuration. Because there is a single data register for both the value of the output driver and the state of the pin’s input, write operations have different effects depending on the pin’s configuration:

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Chapter 12: LPC111x/LPC11Cxx General Purpose I/O (GPIO)

If a pin is configured as GPIO input, a write to the GPIOnDATA register has no effect on the pin level. A read returns the current state of the pin.

If a pin is configured as GPIO output, the current value of GPIOnDATA register is driven to the pin. This value can be a result of writing to the GPIOnDATA register, or it can reflect the previous state of the pin if the pin is switched to GPIO output from

GPIO input or another digital function. A read returns the current state of the output latch.

If a pin is configured as another digital function (input or output), a write to the

GPIOnDATA register has no effect on the pin level. A read returns the current state of the pin even if it is configured as an output. This means that by reading the

GPIOnDATA register, the digital output or input value of a function other than GPIO on that pin can be observed.

The following rules apply when the pins are switched from input to output:

Pin is configured as input with a HIGH level applied:

Change pin to output: pin drives HIGH level.

Pin is configured as input with a LOW level applied:

Change pin to output: pin drives LOW level.

The rules show that the pins mirror the current logic level. Therefore floating pins may drive an unpredictable level when switched from input to output.

12.3.2 GPIO data direction register

Table 175. GPIOnDIR register (GPIO0DIR, address 0x5000 8000 to GPIO3DIR, address

0x5003 8000) bit description

Bit

11:0

Symbol

IO

Description

Selects pin x as input or output (x = 0 to 11).

0 = Pin PIOn_x is configured as input.

1 = Pin PIOn_x is configured as output.

Reset value

0x00

Access

R/W

31:12 Reserved -

12.3.3 GPIO interrupt sense register

Table 176. GPIOnIS register (GPIO0IS, address 0x5000 8004 to GPIO3IS, address 0x5003

8004) bit description

Bit Symbol Description Reset value

Access

11:0 ISENSE R/W

31:12 -

Selects interrupt on pin x as level or edge sensitive (x = 0 to

11).

0 = Interrupt on pin PIOn_x is configured as edge sensitive.

1 = Interrupt on pin PIOn_x is configured as level sensitive.

0x00

Reserved -

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Chapter 12: LPC111x/LPC11Cxx General Purpose I/O (GPIO)

12.3.4 GPIO interrupt both edges sense register

Table 177. GPIOnIBE register (GPIO0IBE, address 0x5000 8008 to GPIO3IBE, address 0x5003

8008) bit description

Bit Symbol Description Reset value

Access

11:0 IBE R/W

31:12 -

Selects interrupt on pin x to be triggered on both edges (x = 0 to 11).

0 = Interrupt on pin PIOn_x is controlled through register

GPIOnIEV.

1 = Both edges on pin PIOn_x trigger an interrupt.

0x00

Reserved -

12.3.5 GPIO interrupt event register

Table 178. GPIOnIEV register (GPIO0IEV, address 0x5000 800C to GPIO3IEV, address 0x5003

800C) bit description

Bit Symbol Description Reset value

Access

11:0 IEV 0x00 R/W

31:12 -

Selects interrupt on pin x to be triggered rising or falling edges (x = 0 to 11).

0 = Depending on setting in register GPIOnIS (see

Table 176 ), falling edges or LOW level on pin PIOn_x

trigger an interrupt.

1 = Depending on setting in register GPIOnIS (see

Table 176 ), rising edges or HIGH level on pin PIOn_x

trigger an interrupt.

Reserved -

12.3.6 GPIO interrupt mask register

Bits set to HIGH in the GPIOnIE register allow the corresponding pins to trigger their individual interrupts and the combined GPIOnINTR line. Clearing a bit disables interrupt triggering on that pin.

Table 179. GPIOnIE register (GPIO0IE, address 0x5000 8010 to GPIO3IE, address 0x5003

8010) bit description

Bit Symbol Description Reset value

Access

11:0

31:12 -

MASK Selects interrupt on pin x to be masked (x = 0 to 11).

0 = Interrupt on pin PIOn_x is masked.

1 = Interrupt on pin PIOn_x is not masked.

Reserved -

0x00

-

R/W

12.3.7 GPIO raw interrupt status register

Bits read HIGH in the GPIOnRIS register reflect the raw (prior to masking) interrupt status of the corresponding pins indicating that all the requirements have been met before they are allowed to trigger the GPIOIE. Bits read as zero indicate that the corresponding input pins have not initiated an interrupt. The register is read-only.

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Chapter 12: LPC111x/LPC11Cxx General Purpose I/O (GPIO)

Table 180. GPIOnRIS register (GPIO0RIS, address 0x5000 8014 to GPIO3RIS, address 0x5003

8014) bit description

Bit Symbol Description

11:0 RAWST

Reset value

Access

0x00 R Raw interrupt status (x = 0 to 11).

0 = No interrupt on pin PIOn_x.

1 = Interrupt requirements met on PIOn_x.

31:12 Reserved -

12.3.8 GPIO masked interrupt status register

Bits read HIGH in the GPIOnMIS register reflect the status of the input lines triggering an interrupt. Bits read as LOW indicate that either no interrupt on the corresponding input pins has been generated or that the interrupt is masked. GPIOMIS is the state of the interrupt after masking. The register is read-only.

Table 181. GPIOnMIS register (GPIO0MIS, address 0x5000 8018 to GPIO3MIS, address

0x5003 8018) bit description

Bit Symbol Description Reset value

Access

11:0

31:12 -

MASK Selects interrupt on pin x to be masked (x = 0 to 11).

0 = No interrupt or interrupt masked on pin PIOn_x.

1 = Interrupt on PIOn_x.

Reserved -

0x00

-

R

12.3.9 GPIO interrupt clear register

This register allows software to clear edge detection for port bits that are identified as edge-sensitive in the Interrupt Sense register. This register has no effect on port bits identified as level-sensitive.

Table 182. GPIOnIC register (GPIO0IC, address 0x5000 801C to GPIO3IC, address 0x5003

801C) bit description

Bit Symbol Description Reset value

Access

11:0 CLR W

31:12 -

Selects interrupt on pin x to be cleared (x = 0 to 11). Clears the interrupt edge detection logic. This register is write-only.

0x00

Remark:

The synchronizer between the GPIO and the

NVIC blocks causes a delay of 2 clocks. It is recommended to add two NOPs after the clear of the interrupt edge detection logic before the exit of the interrupt service routine.

0 = No effect.

1 = Clears edge detection logic for pin PIOn_x.

Reserved -

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Chapter 12: LPC111x/LPC11Cxx General Purpose I/O (GPIO)

12.4 Functional description

12.4.1 Write/read data operation

In order for software to be able to set GPIO bits without affecting any other pins in a single write operation, bits [13:2] of a 14-bit wide address bus are used to create a 12-bit wide mask for write and read operations on the 12 GPIO pins for each port. Only GPIOnDATA bits masked by 1 are affected by read and write operations. The masked GPIOnDATA register can be located anywhere between address offsets 0x0000 to 0x3FFC in the

GPIOn address space. Reading and writing to the GPIOnDATA register at address

0x3FFC sets all masking bits to 1.

Write operation

If the address bit (i+2) associated with the GPIO port bit i (i = 0 to 11) to be written is

HIGH, the value of the GPIODATA register bit i is updated. If the address bit (i+2) is LOW, the corresponding GPIODATA register bit i is left unchanged.

ADDRESS[13:2] 13 12 11 10 9 8 7 6 5 4 3 2 address 0x098

0 0 0 0 0 0 1 0 0 1 1 0 0 0 data 0xFE4

1 1 1 1 1 1 1 0 0 1 0 0

GPIODATA register at address + 0x098 u u u u u u 1 u u 1 0 u u = unchanged

Fig 30. Masked write operation to the GPIODATA register

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Chapter 12: LPC111x/LPC11Cxx General Purpose I/O (GPIO)

Read operation

If the address bit associated with the GPIO data bit is HIGH, the value is read. If the address bit is LOW, the GPIO data bit is read as 0. Reading a port DATA register yields the state of port pins 11:0 ANDed with address bits 13:2.

ADDRESS[13:2]

13 12 11 10 9 8 7 6 5 4 3 2 address 0x0C4 0 0 0 0 0 0 1 1 0 0 0 1 0 0 port pin settings

1 1 1 1 1 1 1 0 0 1 0 0 data read

0 0 0 0 0 0 1 0 0 0 0 0

Fig 31. Masked read operation

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Chapter 13: LPC111x/LPC11Cxx UART

Rev. 12.4 — 22 December 2016 User manual

13.1 How to read this chapter

The UART block is identical for all LPC111x, LPC11D14, and LPC11Cxx parts. The DSR,

DCD, and RI modem signals are fully pinned out on the LQFP48 packages only.

Note that for parts of the LPC1100 series (LPC111x/101/201/301), the UART pins must be configured before the UART clock can be enabled. No enabling sequence requirement exists for parts LPC11Cxx , parts in the LPC1100L and LPC1100XL series, and

LPC11D14.

13.2 Basic configuration

The UART is configured using the following registers:

1. Pins: For the LPC111x/101/201/301 parts, the UART pins must be configured in the

IOCONFIG register block ( Section 7.4

) before the UART clocks can be enabled in the

SYSAHBCLKCTRL register. For all other parts, no special enabling sequence is required.

Remark:

If the modem input pins are used, the modem function location must be also selected in the UART location registers (

Section 7.4

)

2. Power: In the SYSAHBCLKCTRL register, set bit 12 ( Table 21 ).

3. Peripheral clock: Enable the UART peripheral clock by writing to the UARTCLKDIV register (

Table 23 ).

13.3 Features

16-byte receive and transmit FIFOs.

Register locations conform to ‘550 industry standard.

Receiver FIFO trigger points at 1, 4, 8, and 14 bytes.

Built-in baud rate generator.

UART allows for implementation of either software or hardware flow control.

RS-485/EIA-485 9-bit mode support with output enable.

Modem control.

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Chapter 13: LPC111x/LPC11Cxx UART

13.4 Pin description

Table 183. UART pin description

Pin Type Description

RXD

TXD

RTS

DTR

DSR

[1]

CTS

DCD

[1]

RI

[1]

Input

Output

Serial Input.

Serial receive data.

Serial Output.

Serial transmit data.

Output Request To Send. RS-485 direction control pin.

Output Data Terminal Ready.

Input

Input

Input

Input

Data Set Ready.

Clear To Send.

Data Carrier Detect.

Ring Indicator.

[1] LQFP48 packages only.

The DSR, DCD, and RI modem inputs are multiplexed to two different pin locations. Use

the IOCON_LOC registers (see Section 7.4

) to select a physical location for each function on the LQFP48 pin package in addition to selecting the function in the IOCON registers.

The DTR output is available in two pin locations as well. The output value of the DTR pin is driven in both locations identically, and the DTR function at any location can be selected simply by selecting the function in the IOCON register for that pin location.

13.5 Register description

The UART contains registers organized as shown in Table 184 . The Divisor Latch Access

Bit (DLAB) is contained in U0LCR[7] and enables access to the Divisor Latches.

The reset value reflects the data stored in used bits only. It does not include the content of reserved bits.

Table 184. Register overview: UART (base address: 0x4000 8000)

Name Access Address offset

Description

U0RBR RO 0x000

U0THR WO 0x000

Receiver Buffer Register. Contains the next received character to be read.

(DLAB=0)

Transmit Holding Register. The next character to be transmitted is written here. (DLAB=0)

U0DLL R/W 0x000

U0DLM

U0IER

U0IIR

U0FCR

R/W

R/W

RO

WO

0x004

0x004

0x008

0x008

Reset value

NA

NA

Divisor Latch LSB. Least significant byte of the baud rate divisor value. The full divisor is used to generate a baud rate from the fractional rate divider.

(DLAB=1)

0x01

Divisor Latch MSB. Most significant byte of the baud rate divisor value. The full divisor is used to generate a baud rate from the fractional rate divider.

(DLAB=1)

0x00

Interrupt Enable Register. Contains individual interrupt enable bits for the 7 potential UART interrupts. (DLAB=0)

0x00

Interrupt ID Register. Identifies which interrupt(s) are pending.

FIFO Control Register. Controls UART FIFO usage and modes.

0x01

0x00

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Table 184. Register overview: UART (base address: 0x4000 8000)

Name Access Address offset

Description

U0LCR R/W 0x00C

U0MCR

U0LSR

U0MSR

U0SCR

U0ACR

R/W

RO

RO

R/W

R/W

0x010

0x014

0x018

0x01C

0x020

Line Control Register. Contains controls for frame formatting and break generation.

Modem control register

Line Status Register. Contains flags for transmit and receive status, including line errors.

Modem status register

Scratch Pad Register. Eight-bit temporary storage for software.

Auto-baud Control Register. Contains controls for the auto-baud feature.

-

U0FDR

-

R/W

0x024

0x028

-

-

U0TER

-

-

R/W

0x02C

0x030

0x00

0x60

Reserved -

Fractional Divider Register. Generates a clock input for the baud rate divider.

0x10

Reserved -

Transmit Enable Register. Turns off UART transmitter for use with software flow control.

0x80

Reserved -

U0RS485CTRL R/W

0x034 -

0x048

0x04C

Reset value

0x00

0x00

0x00

0x00

U0RS485ADR

MATCH

U0RS485DLY

R/W

R/W

0x050

0x054

RS-485/EIA-485 Control. Contains controls to configure various aspects of

RS-485/EIA-485 modes.

0x00

0x00 RS-485/EIA-485 address match. Contains the address match value for

RS-485/EIA-485 mode.

RS-485/EIA-485 direction control delay.

0x00

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13.5.1 UART Receiver Buffer Register (U0RBR - 0x4000 8000, when

DLAB = 0, Read Only)

The U0RBR is the top byte of the UART RX FIFO. The top byte of the RX FIFO contains the oldest character received and can be read via the bus interface. The LSB (bit 0) represents the “oldest” received data bit. If the character received is less than 8 bits, the unused MSBs are padded with zeroes.

The Divisor Latch Access Bit (DLAB) in U0LCR must be zero in order to access the

U0RBR. The U0RBR is always Read Only.

Since PE, FE and BI bits (see Table 196

) correspond to the byte sitting on the top of the

RBR FIFO (i.e. the one that will be read in the next read from the RBR), the right approach for fetching the valid pair of received byte and its status bits is first to read the content of the U0LSR register, and then to read a byte from the U0RBR.

Table 185. UART Receiver Buffer Register (U0RBR - address 0x4000 8000 when DLAB = 0,

Read Only) bit description

Bit

7:0

Symbol

RBR

31:8 -

Description

The UART Receiver Buffer Register contains the oldest received byte in the UART RX FIFO.

Reserved -

Reset Value

undefined

13.5.2 UART Transmitter Holding Register (U0THR - 0x4000 8000 when

DLAB = 0, Write Only)

The U0THR is the top byte of the UART TX FIFO. The top byte is the newest character in the TX FIFO and can be written via the bus interface. The LSB represents the first bit to transmit.

The Divisor Latch Access Bit (DLAB) in U0LCR must be zero in order to access the

U0THR. The U0THR is always Write Only.

Table 186. UART Transmitter Holding Register (U0THR - address 0x4000 8000 when

DLAB = 0, Write Only) bit description

Bit Symbol Description Reset Value

7:0 THR

31:8 -

Writing to the UART Transmit Holding Register causes the data to be stored in the UART transmit FIFO. The byte will be sent when it reaches the bottom of the FIFO and the transmitter is available.

Reserved -

NA

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13.5.3 UART Divisor Latch LSB and MSB Registers (U0DLL - 0x4000 8000 and U0DLM - 0x4000 8004, when DLAB = 1)

The UART Divisor Latch is part of the UART Baud Rate Generator and holds the value used, along with the Fractional Divider, to divide the UART_PCLK clock in order to produce the baud rate clock, which must be 16x the desired baud rate. The U0DLL and

U0DLM registers together form a 16-bit divisor where U0DLL contains the lower 8 bits of the divisor and U0DLM contains the higher 8 bits of the divisor. A 0x0000 value is treated like a 0x0001 value as division by zero is not allowed. The Divisor Latch Access Bit

(DLAB) in U0LCR must be one in order to access the UART Divisor Latches. Details on how to select the right value for U0DLL and U0DLM can be found in

Section 13.5.15

.

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Table 187. UART Divisor Latch LSB Register (U0DLL - address 0x4000 8000 when DLAB = 1) bit description

Bit

7:0

Symbol

DLLSB

31:8 -

Description

The UART Divisor Latch LSB Register, along with the U0DLM register, determines the baud rate of the UART.

Reserved -

Reset value

0x01

Table 188. UART Divisor Latch MSB Register (U0DLM - address 0x4000 8004 when

DLAB = 1) bit description

Bit Symbol Description Reset value

7:0 DLMSB 0x00

31:8 -

The UART Divisor Latch MSB Register, along with the U0DLL register, determines the baud rate of the UART.

Reserved -

13.5.4 UART Interrupt Enable Register (U0IER - 0x4000 8004, when

DLAB = 0)

The U0IER is used to enable the four UART interrupt sources.

Table 189. UART Interrupt Enable Register (U0IER - address 0x4000 8004 when DLAB = 0) bit description

Bit Symbol Value Description Reset value

0 RBRIE RBR Interrupt Enable. Enables the Receive Data Available interrupt for UART. It also controls the Character Receive

Time-out interrupt.

0

1 THREIE

0

1

0

1

Disable the RDA interrupt.

Enable the RDA interrupt.

THRE Interrupt Enable. Enables the THRE interrupt for

UART. The status of this interrupt can be read from

U0LSR[5].

Disable the THRE interrupt.

0

2

3

6:4 -

-

RXLIE

0

1

-

Enable the THRE interrupt.

RX Line Interrupt Enable. Enables the UART RX line status interrupts. The status of this interrupt can be read from U0LSR[4:1].

Disable the RX line status interrupts.

Enable the RX line status interrupts.

0

7

8

-

ABEOINTEN

-

0

1

Reserved -

Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined.

NA

Reserved 0

0 Enables the end of auto-baud interrupt.

Disable end of auto-baud Interrupt.

Enable end of auto-baud Interrupt.

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Table 189. UART Interrupt Enable Register (U0IER - address 0x4000 8004 when DLAB = 0) bit description

…continued

Bit Symbol Value Description Reset value

9 ABTOINTEN

31:10 -

0

1

Enables the auto-baud time-out interrupt.

Disable auto-baud time-out Interrupt.

Enable auto-baud time-out Interrupt.

0

Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined.

NA

13.5.5 UART Interrupt Identification Register (U0IIR - 0x4004 8008, Read

Only)

U0IIR provides a status code that denotes the priority and source of a pending interrupt.

The interrupts are frozen during a U0IIR access. If an interrupt occurs during a U0IIR access, the interrupt is recorded for the next U0IIR access.

Table 190. UART Interrupt Identification Register (U0IIR - address 0x4004 8008, Read Only) bit description

Bit

0

Symbol

INTSTATUS

Valu e

Description Reset value

1 Interrupt status. Note that U0IIR[0] is active low. The pending interrupt can be determined by evaluating

U0IIR[3:1].

0

1

At least one interrupt is pending.

No interrupt is pending.

3:1 INTID

5:4

7:6

8

9

-

FIFOENABLE

ABEOINT

ABTOINT

31:10 -

0x3

0x2

0x6

0x1

0x0

Interrupt identification. U0IER[3:1] identifies an interrupt corresponding to the UART Rx FIFO. All other combinations of U0IER[3:1] not listed below are reserved (100,101,111).

0

1 - Receive Line Status (RLS).

2a - Receive Data Available (RDA).

2b - Character Time-out Indicator (CTI).

3 - THRE Interrupt.

4 - Modem interrupt.

Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined.

These bits are equivalent to U0FCR[0].

End of auto-baud interrupt. True if auto-baud has finished successfully and interrupt is enabled.

Auto-baud time-out interrupt. True if auto-baud has timed out and interrupt is enabled.

Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined.

NA

0

0

0

NA

Bits U0IIR[9:8] are set by the auto-baud function and signal a time-out or end of auto-baud condition. The auto-baud interrupt conditions are cleared by setting the corresponding

Clear bits in the Auto-baud Control Register.

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If the IntStatus bit is one and no interrupt is pending and the IntId bits will be zero. If the

IntStatus is 0, a non auto-baud interrupt is pending in which case the IntId bits identify the type of interrupt and handling as described in

Table 191 . Given the status of U0IIR[3:0], an

interrupt handler routine can determine the cause of the interrupt and how to clear the active interrupt. The U0IIR must be read in order to clear the interrupt prior to exiting the

Interrupt Service Routine.

The UART RLS interrupt (U0IIR[3:1] = 011) is the highest priority interrupt and is set whenever any one of four error conditions occur on the UART RX input: overrun error

(OE), parity error (PE), framing error (FE) and break interrupt (BI). The UART Rx error condition that set the interrupt can be observed via U0LSR[4:1]. The interrupt is cleared upon a U0LSR read.

The UART RDA interrupt (U0IIR[3:1] = 010) shares the second level priority with the CTI interrupt (U0IIR[3:1] = 110). The RDA is activated when the UART Rx FIFO reaches the trigger level defined in U0FCR7:6 and is reset when the UART Rx FIFO depth falls below the trigger level. When the RDA interrupt goes active, the CPU can read a block of data defined by the trigger level.

The CTI interrupt (U0IIR[3:1] = 110) is a second level interrupt and is set when the UART

Rx FIFO contains at least one character and no UART Rx FIFO activity has occurred in

3.5 to 4.5 character times. Any UART Rx FIFO activity (read or write of UART RSR) will clear the interrupt. This interrupt is intended to flush the UART RBR after a message has been received that is not a multiple of the trigger level size. For example, if a peripheral wished to send a 105 character message and the trigger level was 10 characters, the

CPU would receive 10 RDA interrupts resulting in the transfer of 100 characters and 1 to 5

CTI interrupts (depending on the service routine) resulting in the transfer of the remaining

5 characters.

Table 191. UART Interrupt Handling

U0IIR[3:0]

value

[1]

Priority Interrupt type

Interrupt source

0001

0110

None None

OE

[2]

or PE

[2]

or FE

[2]

or BI

[2]

0100

Highest RX Line

Status /

Error

Second RX Data

Available

Rx data available or trigger level reached in FIFO

(U0FCR0=1)

-

Interrupt reset

U0LSR

Read

[2]

U0RBR

Read

[3]

or

UART FIFO drops below trigger level

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Table 191. UART Interrupt Handling

U0IIR[3:0] value

[1]

Priority Interrupt type

Interrupt source

1100

0010

0000

Interrupt reset

Second Character

Time-out indication

Minimum of one character in the RX FIFO and no character input or removed during a time period depending on how many characters are in FIFO and what the trigger level is set at (3.5 to 4.5 character times).

Third THRE

The exact time will be:

[(word length)

7 - 2]

8 + [(trigger level - number of characters)

8 + 1] RCLKs

THRE

[2]

U0RBR

Read

[3]

U0IIR

Read

[4]

(if

source of interrupt) or

THR write

Fourth Modem status

CTS or DSR or RI or DCD MSR read

[1]

[2]

[3]

[4]

Values “0000”, “0011”, “0101”, “0111”, “1000”, “1001”, “1010”, “1011”,”1101”,”1110”,”1111” are reserved.

For details see

Section 13.5.9 “UART Line Status Register (U0LSR - 0x4000 8014, Read Only)”

For details see

Section 13.5.1 “UART Receiver Buffer Register (U0RBR - 0x4000 8000, when DLAB = 0,

Read Only)”

For details see

Section 13.5.5 “UART Interrupt Identification Register (U0IIR - 0x4004 8008, Read Only)”

and Section 13.5.2 “UART Transmitter Holding Register (U0THR - 0x4000 8000 when DLAB = 0, Write

Only)”

The UART THRE interrupt (U0IIR[3:1] = 001) is a third level interrupt and is activated when the UART THR FIFO is empty provided certain initialization conditions have been met. These initialization conditions are intended to give the UART THR FIFO a chance to fill up with data to eliminate many THRE interrupts from occurring at system start-up. The initialization conditions implement a one character delay minus the stop bit whenever

THRE = 1 and there have not been at least two characters in the U0THR at one time since the last THRE = 1 event. This delay is provided to give the CPU time to write data to

U0THR without a THRE interrupt to decode and service. A THRE interrupt is set immediately if the UART THR FIFO has held two or more characters at one time and currently, the U0THR is empty. The THRE interrupt is reset when a U0THR write occurs or a read of the U0IIR occurs and the THRE is the highest interrupt (U0IIR[3:1] = 001).

It is the lowest priority interrupt and is activated whenever there is any state change on modem inputs pins, DCD, DSR or CTS. In addition, a low to high transition on modem input RI will generate a modem interrupt. The source of the modem interrupt can be determined by examining MSR[3:0]. A MSR read will clear the modem interrupt.

13.5.6 UART FIFO Control Register (U0FCR - 0x4000 8008, Write Only)

The U0FCR controls the operation of the UART RX and TX FIFOs.

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Table 192. UART FIFO Control Register (U0FCR - address 0x4000 8008, Write Only) bit description

Bit Symbol Value Description

0 FIFOEN

Reset value

0

0

FIFO Enable

UART FIFOs are disabled. Must not be used in the application.

1

1 RXFIFORES

0

1

Active high enable for both UART Rx and TX FIFOs and

U0FCR[7:1] access. This bit must be set for proper UART operation. Any transition on this bit will automatically clear the UART FIFOs.

RX FIFO Reset

No impact on either of UART FIFOs.

Writing a logic 1 to U0FCR[1] will clear all bytes in UART

Rx FIFO, reset the pointer logic. This bit is self-clearing.

0

2 TXFIFORES

3

5:4

7:6

31:8 -

-

-

RXTL

-

-

0

1

0x0

0x1

0x2

0x3

TX FIFO Reset

No impact on either of UART FIFOs.

Writing a logic 1 to U0FCR[2] will clear all bytes in UART

TX FIFO, reset the pointer logic. This bit is self-clearing.

-

0

Reserved

Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined.

RX Trigger Level. These two bits determine how many receiver UART FIFO characters must be written before an interrupt is activated.

0

Trigger level 0 (1 character or 0x01).

0

NA

Trigger level 1 (4 characters or 0x04).

Trigger level 2 (8 characters or 0x08).

Trigger level 3 (14 characters or 0x0E).

Reserved

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13.5.7 UART Line Control Register (U0LCR - 0x4000 800C)

The U0LCR determines the format of the data character that is to be transmitted or received.

Table 193. UART Line Control Register (U0LCR - address 0x4000 800C) bit description

Bit Symbol Value Description Reset

Value

1:0 WLS Word Length Select 0

0x0

0x1

0x2

0x3

5-bit character length.

6-bit character length.

7-bit character length.

8-bit character length.

2 SBS

0

1

Stop Bit Select

1 stop bit.

2 stop bits (1.5 if U0LCR[1:0]=00).

0

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Table 193. UART Line Control Register (U0LCR - address 0x4000 800C) bit description

Bit Symbol Value Description Reset

Value

3 PE 0

5:4 PS

0

1

Parity Enable

Disable parity generation and checking.

Enable parity generation and checking.

Parity Select 0

0x0

6

7

31:

8

-

BC

DLAB

-

0

1

0

1

0x1

0x2

0x3

Odd parity. Number of 1s in the transmitted character and the attached parity bit will be odd.

Even Parity. Number of 1s in the transmitted character and the attached parity bit will be even.

Forced 1 stick parity.

Forced 0 stick parity.

Break Control

Disable break transmission.

Enable break transmission. Output pin UART TXD is forced to logic

0 when U0LCR[6] is active high.

0

0 Divisor Latch Access Bit

Disable access to Divisor Latches.

Enable access to Divisor Latches.

Reserved -

13.5.8 UART Modem Control Register

The U0MCR enables the modem loopback mode and controls the modem output signals.

Table 194. UART0 Modem Control Register (U0MCR - address 0x4000 8010) bit description

Bit Symbol Value Description Reset value

0 DTRC

1

3:2 -

RTSC

DTR Control. Source for modem output pin, DTR. This bit reads as 0 when modem loopback mode is active.

0

RTS Control. Source for modem output pin RTS. This bit reads as

0 when modem loopback mode is active.

0

Reserved, user software should not write ones to reserved bits.

The value read from a reserved bit is not defined.

0

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Table 194. UART0 Modem Control Register (U0MCR - address 0x4000 8010) bit description

Bit Symbol Value Description Reset value

4 LMS

5

6

-

RTSEN

0

1

Loopback Mode Select. The modem loopback mode provides a mechanism to perform diagnostic loopback testing. Serial data from the transmitter is connected internally to serial input of the receiver. Input pin, RXD, has no effect on loopback and output pin, TXD is held in marking state. The four modem inputs (CTS,

DSR, RI and DCD) are disconnected externally. Externally, the modem outputs (RTS, DTR) are set inactive. Internally, the four modem outputs are connected to the four modem inputs. As a result of these connections, the upper four bits of the U0MSR will be driven by the lower four bits of the U0MCR rather than the four modem inputs in normal mode. This permits modem status interrupts to be generated in loopback mode by writing the lower four bits of U0MCR.

Disable modem loopback mode.

0

Enable modem loopback mode.

Reserved, user software should not write ones to reserved bits.

The value read from a reserved bit is not defined.

RTS flow control

0

0

0

1

7 CTSEN

31:8 -

0

1

Disable auto-rts flow control.

Enable auto-rts flow control.

CTS flow control

Disable auto-cts flow control.

Enable auto-cts flow control.

Reserved -

0

13.5.8.1 Auto-flow control

If auto-RTS mode is enabled the UART‘s receiver FIFO hardware controls the RTS output of the UART. If the auto-CTS mode is enabled the UART‘s U0TSR hardware will only start transmitting if the CTS input signal is asserted.

13.5.8.1.1

Auto-RTS

The auto-RTS function is enabled by setting the RTSen bit. Auto-RTS data flow control originates in the U0RBR module and is linked to the programmed receiver FIFO trigger level. If auto-RTS is enabled, the data-flow is controlled as follows:

When the receiver FIFO level reaches the programmed trigger level, RTS is deasserted

(to a high value). It is possible that the sending UART sends an additional byte after the trigger level is reached (assuming the sending UART has another byte to send) because it might not recognize the deassertion of RTS until after it has begun sending the additional byte. RTS is automatically reasserted (to a low value) once the receiver FIFO has reached the previous trigger level. The reassertion of RTS signals the sending UART to continue transmitting data.

If Auto-RTS mode is disabled, the RTSen bit controls the RTS output of the UART. If

Auto-RTS mode is enabled, hardware controls the RTS output, and the actual value of

RTS will be copied in the RTS Control bit of the UART. As long as Auto-RTS is enabled, the value of the RTS Control bit is read-only for software.

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Example: Suppose the UART operating in type ‘550 mode has the trigger level in U0FCR set to 0x2, then, if Auto-RTS is enabled, the UART will deassert the RTS output as soon as the receive FIFO contains 8 bytes (

Table 192 on page 206

). The RTS output will be reasserted as soon as the receive FIFO hits the previous trigger level: 4 bytes.

UART1 Rx

~ ~ start byte N stop start bits0..7

stop start bits0..7

stop

~ ~

RTS1 pin

UART1 Rx

FIFO read

UART1 Rx

FIFO level

N-1

N

Fig 32. Auto-RTS Functional Timing

N-1 N-2 N-1 N-2

~ ~

~ ~

~ ~

M+2 M+1 M M-1

13.5.8.1.2

Auto-CTS

The Auto-CTS function is enabled by setting the CTSen bit. If Auto-CTS is enabled, the transmitter circuitry in the U0TSR module checks CTS input before sending the next data byte. When CTS is active (low), the transmitter sends the next byte. To stop the transmitter from sending the following byte, CTS must be released before the middle of the last stop bit that is currently being sent. In Auto-CTS mode, a change of the CTS signal does not trigger a modem status interrupt unless the CTS Interrupt Enable bit is set,

Delta CTS bit in the U0MSR will be set though.

Table 195

lists the conditions for generating a Modem Status interrupt.

1

1

1

1

1

1

1

1

Table 195. Modem status interrupt generation

Enable modem status interrupt

(U0ER[3])

0

CTSen

(U0MCR[7])

x

CTS interrupt enable

(U0IER[7])

x

Delta CTS

(U0MSR[0])

x

Delta DCD or trailing edge

RI or

Delta DSR (U0MSR[3] or

U0MSR[2] or U0MSR[1])

x

0

0

0

1 x x x

0

0

1 x x

0 x

1

0

1

1

1

1

1

1

0

1

1 x x

0 x

1

1

0

Modem status interrupt

No

No

Yes

Yes

No

Yes

No

Yes

Yes

The auto-CTS function reduces interrupts to the host system. When flow control is enabled, a CTS state change does not trigger host interrupts because the device automatically controls its own transmitter. Without Auto-CTS, the transmitter sends any data present in the transmit FIFO and a receiver overrun error can result.

Figure 33

illustrates the Auto-CTS functional timing.

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Chapter 13: LPC111x/LPC11Cxx UART

UART1 TX

~ ~ ~ ~ start bits0..7

stop start bits0..7

stop start bits0..7

stop

~ ~

CTS1 pin

Fig 33. Auto-CTS Functional Timing

~ ~

While starting transmission of the initial character, the CTS signal is asserted.

Transmission will stall as soon as the pending transmission has completed. The UART will continue transmitting a 1 bit as long as CTS is de-asserted (high). As soon as CTS gets de-asserted, transmission resumes and a start bit is sent followed by the data bits of the next character.

13.5.9 UART Line Status Register (U0LSR - 0x4000 8014, Read Only)

The U0LSR is a Read Only register that provides status information on the UART TX and

RX blocks.

Table 196. UART Line Status Register (U0LSR - address 0x4000 8014, Read Only) bit description

Bit Symbol Value Description Reset

Value

0 RDR Receiver Data Ready. U0LSR[0] is set when the U0RBR holds an unread character and is cleared when the UART RBR FIFO is empty.

0

0

1

1 OE

0

1

U0RBR is empty.

U0RBR contains valid data.

Overrun Error. The overrun error condition is set as soon as it occurs. A U0LSR read clears U0LSR[1]. U0LSR[1] is set when

UART RSR has a new character assembled and the UART

RBR FIFO is full. In this case, the UART RBR FIFO will not be overwritten and the character in the UART RSR will be lost.

0

Overrun error status is inactive.

2 PE

0

1

Overrun error status is active.

Parity Error. When the parity bit of a received character is in the wrong state, a parity error occurs. A U0LSR read clears

U0LSR[2]. Time of parity error detection is dependent on

U0FCR[0].

Note:

A parity error is associated with the character at the top of the UART RBR FIFO.

0

Parity error status is inactive.

Parity error status is active.

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Table 196. UART Line Status Register (U0LSR - address 0x4000 8014, Read Only) bit description

…continued

Bit Symbol Value Description Reset

Value

3 FE

0

1

Framing Error. When the stop bit of a received character is a logic 0, a framing error occurs. A U0LSR read clears

U0LSR[3]. The time of the framing error detection is dependent on U0FCR0. Upon detection of a framing error, the

RX will attempt to re-synchronize to the data and assume that the bad stop bit is actually an early start bit. However, it cannot be assumed that the next received byte will be correct even if there is no Framing Error.

0

Note:

A framing error is associated with the character at the top of the UART RBR FIFO.

Framing error status is inactive.

Framing error status is active.

4 BI

0

1

Break Interrupt. When RXD1 is held in the spacing state (all zeros) for one full character transmission (start, data, parity, stop), a break interrupt occurs. Once the break condition has been detected, the receiver goes idle until RXD1 goes to marking state (all ones). A U0LSR read clears this status bit.

The time of break detection is dependent on U0FCR[0].

Note:

The break interrupt is associated with the character at the top of the UART RBR FIFO.

Break interrupt status is inactive.

0

5 THRE

0

1

Break interrupt status is active.

Transmitter Holding Register Empty. THRE is set immediately upon detection of an empty UART THR and is cleared on a

U0THR write.

1

U0THR contains valid data.

U0THR is empty.

6 TEMT

7

31:

8

-

RXFE

-

0

1

0

1

Transmitter Empty. TEMT is set when both U0THR and

U0TSR are empty; TEMT is cleared when either the U0TSR or the U0THR contain valid data. This bit is updated as soon as

50 % of the first stop bit has been transmitted or a byte has been written into the THR.

1

U0THR and/or the U0TSR contains valid data.

U0THR and the U0TSR are empty.

Error in RX FIFO. U0LSR[7] is set when a character with a RX error such as framing error, parity error or break interrupt, is loaded into the U0RBR. This bit is cleared when the U0LSR register is read and there are no subsequent errors in the

UART FIFO.

0

U0RBR contains no UART RX errors or U0FCR[0]=0.

UART RBR contains at least one UART RX error.

Reserved -

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13.5.10 UART Modem Status Register

The U0MSR is a read-only register that provides status information on the modem input signals. U0MSR[3:0] is cleared on U0MSR read. Note that modem signals have no direct effect on the UART operation. They facilitate the software implementation of modem signal operations.

Table 197. UART Modem Status Register (U0MSR - address 0x4000 8018) bit description

Bit Symbol Value Description Reset

Value

0 DCTS 0

1 DDSR

0

1

Delta CTS. Set upon state change of input CTS. Cleared on a

U0MSR read.

No change detected on modem input CTS.

State change detected on modem input CTS.

Delta DSR. Set upon state change of input DSR. Cleared on a

U0MSR read.

0

0

1

2

3

TERI

DDCD

0

1

No change detected on modem input DSR.

State change detected on modem input DSR.

Trailing Edge RI. Set upon low to high transition of input RI. Cleared on a U0MSR read.

0

No change detected on modem input, RI.

Low-to-high transition detected on RI.

Delta DCD. Set upon state change of input DCD. Cleared on a

U0MSR read.

0

0

1

4

5

6

7

31:

8

-

CTS

DSR

RI

DCD

-

No change detected on modem input DCD.

State change detected on modem input DCD.

Clear To Send State. Complement of input signal CTS. This bit is connected to U0MCR[1] in modem loopback mode.

Data Set Ready State. Complement of input signal DSR. This bit is connected to U0MCR[0] in modem loopback mode.

0

0

Ring Indicator State. Complement of input RI. This bit is connected to U0MCR[2] in modem loopback mode.

0

0 Data Carrier Detect State. Complement of input DCD. This bit is connected to U0MCR[3] in modem loopback mode.

Reserved -

13.5.11 UART Scratch Pad Register (U0SCR - 0x4000 801C)

The U0SCR has no effect on the UART operation. This register can be written and/or read at user’s discretion. There is no provision in the interrupt interface that would indicate to the host that a read or write of the U0SCR has occurred.

Table 198. UART Scratch Pad Register (U0SCR - address 0x4000 801C) bit description

Bit Symbol Description Reset

Value

7:0 Pad

31:

8

-

A readable, writable byte.

Reserved -

0x00

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13.5.12 UART Auto-baud Control Register (U0ACR - 0x4000 8020)

The UART Auto-baud Control Register (U0ACR) controls the process of measuring the incoming clock/data rate for the baud rate generation and can be read and written at user’s discretion.

Table 199. Auto baud Control Register (U0ACR - address 0x4000 8020) bit description

Bit Symbol Value Description Reset value

0 START 0

0

1

Start bit. This bit is automatically cleared after auto-baud completion.

Auto-baud stop (auto-baud is not running).

Auto-baud start (auto-baud is running). Auto-baud run bit. This bit is automatically cleared after auto-baud completion.

1 MODE 0

2

7:3

8

-

AUTORESTART

ABEOINTCLR

0

1

0

1

Auto-baud mode select

Mode 0.

Mode 1.

Restart enable

No restart

Restart in case of time-out (counter restarts at next

UART Rx falling edge)

Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined.

End of auto-baud interrupt clear (write only accessible)

0

0

0

0

9 ABTOINTCLR

31:10 -

0

1

0

1

Writing a 0 has no impact.

Writing a 1 will clear the corresponding interrupt in the U0IIR.

Auto-baud time-out interrupt clear (write only accessible)

Writing a 0 has no impact.

Writing a 1 will clear the corresponding interrupt in the U0IIR.

Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined.

0

0

13.5.13 Auto-baud

The UART auto-baud function can be used to measure the incoming baud rate based on the ”AT" protocol (Hayes command). If enabled the auto-baud feature will measure the bit time of the receive data stream and set the divisor latch registers U0DLM and U0DLL accordingly.

Auto-baud is started by setting the U0ACR Start bit. Auto-baud can be stopped by clearing the U0ACR Start bit. The Start bit will clear once auto-baud has finished and reading the bit will return the status of auto-baud (pending/finished).

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Two auto-baud measuring modes are available which can be selected by the U0ACR

Mode bit. In Mode 0 the baud rate is measured on two subsequent falling edges of the

UART Rx pin (the falling edge of the start bit and the falling edge of the least significant bit). In Mode 1 the baud rate is measured between the falling edge and the subsequent rising edge of the UART Rx pin (the length of the start bit).

The U0ACR AutoRestart bit can be used to automatically restart baud rate measurement if a time-out occurs (the rate measurement counter overflows). If this bit is set, the rate measurement will restart at the next falling edge of the UART Rx pin.

The auto-baud function can generate two interrupts.

The U0IIR ABTOInt interrupt will get set if the interrupt is enabled (U0IER ABToIntEn is set and the auto-baud rate measurement counter overflows).

The U0IIR ABEOInt interrupt will get set if the interrupt is enabled (U0IER ABEOIntEn is set and the auto-baud has completed successfully).

The auto-baud interrupts have to be cleared by setting the corresponding U0ACR

ABTOIntClr and ABEOIntEn bits.

The fractional baud rate generator must be disabled (DIVADDVAL = 0) during auto-baud.

Also, when auto-baud is used, any write to U0DLM and U0DLL registers should be done before U0ACR register write. The minimum and the maximum baud rates supported by

UART are function of UART_PCLK, number of data bits, stop bits and parity bits.

(2)

ratemin

=

P CLK

16

215

UART baudrate

16

 

2

+

databits

+

paritybits

+

stopbits

=

ratemax

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13.5.14 Auto-baud modes

When the software is expecting an ”AT" command, it configures the UART with the expected character format and sets the U0ACR Start bit. The initial values in the divisor latches U0DLM and U0DLM don‘t care. Because of the ”A" or ”a" ASCII coding

(”A" = 0x41, ”a" = 0x61), the UART Rx pin sensed start bit and the LSB of the expected character are delimited by two falling edges. When the U0ACR Start bit is set, the auto-baud protocol will execute the following phases:

1. On U0ACR Start bit setting, the baud rate measurement counter is reset and the

UART U0RSR is reset. The U0RSR baud rate is switched to the highest rate.

2. A falling edge on UART Rx pin triggers the beginning of the start bit. The rate measuring counter will start counting UART_PCLK cycles.

3. During the receipt of the start bit, 16 pulses are generated on the RSR baud input with the frequency of the UART input clock, guaranteeing the start bit is stored in the

U0RSR.

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4. During the receipt of the start bit (and the character LSB for Mode = 0), the rate counter will continue incrementing with the pre-scaled UART input clock

(UART_PCLK).

5. If Mode = 0, the rate counter will stop on next falling edge of the UART Rx pin. If

Mode = 1, the rate counter will stop on the next rising edge of the UART Rx pin.

6. The rate counter is loaded into U0DLM/U0DLL and the baud rate will be switched to normal operation. After setting the U0DLM/U0DLL, the end of auto-baud interrupt

U0IIR ABEOInt will be set, if enabled. The U0RSR will now continue receiving the remaining bits of the ”A/a" character.

'A' (0x41) or 'a' (0x61) start bit0 bit1 bit2 bit3 bit4 bit5 bit6 bit7 parity stop

UARTn RX start bit LSB of 'A' or 'a'

U0ACR start rate counter

16xbaud_rate

16 cycles a. Mode 0 (start bit and LSB are used for auto-baud)

16 cycles

'A' (0x41) or 'a' (0x61) start bit0 bit1 bit2 bit3 bit4 bit5 bit6 bit7 parity stop

UARTn RX start bit LSB of 'A' or 'a'

U1ACR start rate counter

16xbaud_rate

16 cycles b. Mode 1 (only start bit is used for auto-baud)

Fig 34. Auto-baud a) mode 0 and b) mode 1 waveform

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Chapter 13: LPC111x/LPC11Cxx UART

13.5.15 UART Fractional Divider Register (U0FDR - 0x4000 8028)

The UART Fractional Divider Register (U0FDR) controls the clock pre-scaler for the baud rate generation and can be read and written at the user’s discretion. This pre-scaler takes the APB clock and generates an output clock according to the specified fractional requirements.

Important:

If the fractional divider is active (DIVADDVAL > 0) and DLM = 0, the value of the DLL register must be 3 or greater.

Table 200. UART Fractional Divider Register (U0FDR - address 0x4000 8028) bit description

Bit Function Description Reset value

3:0 DIVADDVAL

7:4

31:8 -

MULVAL

Baud rate generation pre-scaler divisor value. If this field is 0, fractional baud rate generator will not impact the UART baud rate.

0

Baud rate pre-scaler multiplier value. This field must be greater or equal 1 for UART to operate properly, regardless of whether the fractional baud rate generator is used or not.

1

Reserved, user software should not write ones to reserved bits.

The value read from a reserved bit is not defined.

0

This register controls the clock pre-scaler for the baud rate generation. The reset value of the register keeps the fractional capabilities of UART disabled making sure that UART is fully software and hardware compatible with UARTs not equipped with this feature.

The UART baud rate can be calculated as:

(3)

UART baudrate

=

16

 

256

U0DLM

+

U0DLL

 

1

+

-----------------------------

MulVal

Where UART_PCLK is the peripheral clock, U0DLM and U0DLL are the standard UART baud rate divider registers, and DIVADDVAL and MULVAL are UART fractional baud rate generator specific parameters.

The value of MULVAL and DIVADDVAL should comply to the following conditions:

1. 1



MULVAL

15

2. 0

DIVADDVAL

14

3. DIVADDVAL< MULVAL

The value of the U0FDR should not be modified while transmitting/receiving data or data may be lost or corrupted.

If the U0FDR register value does not comply to these two requests, then the fractional divider output is undefined. If DIVADDVAL is zero then the fractional divider is disabled, and the clock will not be divided.

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13.5.15.1 Baud rate calculation

UART can operate with or without using the Fractional Divider. In real-life applications it is likely that the desired baud rate can be achieved using several different Fractional Divider settings. The following algorithm illustrates one way of finding a set of DLM, DLL,

MULVAL, and DIVADDVAL values. Such set of parameters yields a baud rate with a relative error of less than 1.1% from the desired one.

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Chapter 13: LPC111x/LPC11Cxx UART

Calculating UART baudrate (BR)

PCLK,

BR

DL est

= PCLK/(16 x BR)

DL est

is an integer?

FR est

= 1.5

False

Pick another FR est

from the range [1.1, 1.9]

DL est

= Int(PCLK/(16 x BR x FR est

))

FR est

= PCLK/(16 x BR x DL est

)

True

DIVADDVAL = 0

MULVAL = 1

False

1.1 < FR est

< 1.9?

True

DIVADDVAL = table(FR

MULVAL = table(FR est

) est

)

DLM = DL est

DLL = DL est

[15:8]

[7:0]

Fig 35. Algorithm for setting UART dividers

End

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Chapter 13: LPC111x/LPC11Cxx UART

1.100

1.111

1.125

1.133

1.143

1.154

1.167

1.182

Table 201. Fractional Divider setting look-up table

FR

1.000

1.067

DivAddVal/

MulVal

0/1

1/15

FR

1.250

1.267

DivAddVal/

MulVal

1/4

4/15

FR

1.500

1.533

1.071

1.077

1.083

1.091

1/14

1/13

1/12

1/11

1.273

1.286

1.300

1.308

3/11

2/7

3/10

4/13

1.538

1.545

1.556

1.571

1.200

1.214

1.222

1.231

1/10

1/9

1/8

2/15

1/7

2/13

1/6

2/11

1/5

3/14

2/9

3/13

1.333

1.357

1.364

1.375

1.385

1.400

1.417

1.429

1.444

1.455

1.462

1.467

1/3

5/14

4/11

3/8

5/13

2/5

5/12

3/7

4/9

5/11

6/13

7/15

1.700

1.714

1.727

1.733

1.583

1.600

1.615

1.625

1.636

1.643

1.667

1.692

2/3

9/13

7/10

5/7

8/11

11/15

5/9

4/7

7/12

3/5

8/13

5/8

7/11

9/14

DivAddVal/

MulVal

1/2

8/15

7/13

6/11

FR

1.833

1.846

1.857

1.867

1.875

1.889

1.900

1.909

1.750

1.769

1.778

1.786

1.800

1.818

1.917

1.923

1.929

1.933

13.5.15.1.1

Example 1: UART_PCLK = 14.7456 MHz, BR = 9600

According to the provided algorithm DL est

= PCLK/(16 x BR) = 14.7456 MHz / (16 x 9600)

= 96. Since this DL est

is an integer number, DIVADDVAL = 0, MULVAL = 1, DLM = 0, and

DLL = 96.

13.5.15.1.2

Example 2: UART_PCLK = 12 MHz, BR = 115200

According to the provided algorithm DL est

= PCLK/(16 x BR) = 12 MHz / (16 x 115200) =

6.51. This DL est

is not an integer number and the next step is to estimate the FR parameter. Using an initial estimate of FR est is recalculated as FR est

= 1.628. Since FR est

= 1.5 a new DL est

= 4 is calculated and FR est

= 1.628 is within the specified range of 1.1 and 1.9, DIVADDVAL and MULVAL values can be obtained from the attached look-up table.

The closest value for FRest = 1.628 in the look-up Table 201

is FR = 1.625. It is equivalent to DIVADDVAL = 5 and MULVAL = 8.

Based on these findings, the suggested UART setup would be: DLM = 0, DLL = 4,

DIVADDVAL = 5, and MULVAL = 8. According to

Equation 3

, the UART’s baud rate is

115384. This rate has a relative error of 0.16% from the originally specified 115200.

9/10

10/11

11/12

12/13

13/14

14/15

4/5

9/11

5/6

11/13

6/7

13/15

7/8

8/9

DivAddVal/

MulVal

3/4

10/13

7/9

11/14

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13.5.16 UART Transmit Enable Register (U0TER - 0x4000 8030)

In addition to being equipped with full hardware flow control (auto-cts and auto-rts mechanisms described above), U0TER enables implementation of software flow control.

When TxEn = 1, UART transmitter will keep sending data as long as they are available. As soon as TxEn becomes 0, UART transmission will stop.

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Although Table 202

describes how to use TxEn bit in order to achieve hardware flow control, it is strongly suggested to let UART hardware implemented auto flow control features take care of this, and limit the scope of TxEn to software flow control.

Table 202 describes how to use TXEN bit in order to achieve software flow control.

Table 202. UART Transmit Enable Register (U0TER - address 0x4000 8030) bit description

Bit

6:0

7

-

Symbol

TXEN

31:8 -

Description

Reserved, user software should not write ones to reserved bits.

The value read from a reserved bit is not defined.

Reset Value

NA

When this bit is 1, as it is after a Reset, data written to the THR is output on the TXD pin as soon as any preceding data has been sent. If this bit cleared to 0 while a character is being sent, the transmission of that character is completed, but no further characters are sent until this bit is set again. In other words, a 0 in this bit blocks the transfer of characters from the THR or TX

FIFO into the transmit shift register. Software can clear this bit when it detects that the a hardware-handshaking TX-permit signal (CTS) has gone false, or with software handshaking, when it receives an XOFF character (DC3). Software can set this bit again when it detects that the TX-permit signal has gone true, or when it receives an XON (DC1) character.

1

Reserved -

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13.5.17 UART RS485 Control register (U0RS485CTRL - 0x4000 804C)

The U0RS485CTRL register controls the configuration of the UART in RS-485/EIA-485 mode.

Table 203. UART RS485 Control register (U0RS485CTRL - address 0x4000 804C) bit description

Bit Symbol Value Description Reset value

0

1

NMMEN

RXDIS

0

1

NMM enable.

RS-485/EIA-485 Normal Multidrop Mode (NMM) is disabled.

0

RS-485/EIA-485 Normal Multidrop Mode (NMM) is enabled. In this mode, an address is detected when a received byte causes the UART to set the parity error and generate an interrupt.

Receiver enable.

0

0

1

2

3

AADEN

SEL

0

1

0

1

The receiver is enabled.

The receiver is disabled.

AAD enable.

Auto Address Detect (AAD) is disabled.

0

Auto Address Detect (AAD) is enabled.

Select direction control pin

If direction control is enabled (bit DCTRL = 1), pin

RTS is used for direction control.

If direction control is enabled (bit DCTRL = 1), pin

DTR is used for direction control.

0

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Table 203. UART RS485 Control register (U0RS485CTRL - address 0x4000 804C) bit description

…continued

Bit Symbol Value Description Reset value

4 DCTRL 0

0

1

Auto direction control enable.

Disable Auto Direction Control.

Enable Auto Direction Control.

5 OINV

31:6 -

0

1

Polarity control. This bit reverses the polarity of the direction control signal on the RTS (or DTR) pin.

The direction control pin will be driven to logic 0 when the transmitter has data to be sent. It will be driven to logic 1 after the last bit of data has been transmitted.

0

The direction control pin will be driven to logic 1 when the transmitter has data to be sent. It will be driven to logic 0 after the last bit of data has been transmitted.

Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined.

NA

13.5.18 UART RS485 Address Match register (U0RS485ADRMATCH - 0x4000

8050)

The U0RS485ADRMATCH register contains the address match value for RS-485/EIA-485 mode.

Table 204. UART RS485 Address Match register (U0RS485ADRMATCH - address

0x4000 8050) bit description

Bit

7:0

31:8 -

Symbol

ADRMATCH

Description

Contains the address match value.

Reserved -

Reset value

0x00

13.5.19 UART1 RS485 Delay value register (U0RS485DLY - 0x4000 8054)

The user may program the 8-bit RS485DLY register with a delay between the last stop bit leaving the TXFIFO and the de-assertion of RTS (or DTR). This delay time is in periods of the baud clock. Any delay time from 0 to 255 bit times may be programmed.

Table 205. UART RS485 Delay value register (U0RS485DLY - address 0x4000 8054) bit description

Bit

7:0

31:8 -

Symbol

DLY

Description

Contains the direction control (RTS or DTR) delay value. This register works in conjunction with an 8-bit counter.

Reserved, user software should not write ones to reserved bits.

The value read from a reserved bit is not defined.

Reset value

0x00

NA

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13.5.20 RS-485/EIA-485 modes of operation

The RS-485/EIA-485 feature allows the UART to be configured as an addressable slave.

The addressable slave is one of multiple slaves controlled by a single master.

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The UART master transmitter will identify an address character by setting the parity (9th) bit to ‘1’. For data characters, the parity bit is set to ‘0’.

Each UART slave receiver can be assigned a unique address. The slave can be programmed to either manually or automatically reject data following an address which is not theirs.

RS-485/EIA-485 Normal Multidrop Mode (NMM)

Setting the RS485CTRL bit 0 enables this mode. In this mode, an address is detected when a received byte causes the UART to set the parity error and generate an interrupt.

If the receiver is disabled (RS485CTRL bit 1 = ‘1’), any received data bytes will be ignored and will not be stored in the RXFIFO. When an address byte is detected (parity bit = ‘1’) it will be placed into the RXFIFO and an Rx Data Ready Interrupt will be generated. The processor can then read the address byte and decide whether or not to enable the receiver to accept the following data.

While the receiver is enabled (RS485CTRL bit 1 =’0’), all received bytes will be accepted and stored in the RXFIFO regardless of whether they are data or address. When an address character is received a parity error interrupt will be generated and the processor can decide whether or not to disable the receiver.

RS-485/EIA-485 Auto Address Detection (AAD) mode

When both RS485CTRL register bits 0 (9-bit mode enable) and 2 (AAD mode enable) are set, the UART is in auto address detect mode.

In this mode, the receiver will compare any address byte received (parity = ‘1’) to the 8-bit value programmed into the RS485ADRMATCH register.

If the receiver is disabled (RS485CTRL bit 1 = ‘1’), any received byte will be discarded if it is either a data byte OR an address byte which fails to match the RS485ADRMATCH value.

When a matching address character is detected it will be pushed onto the RXFIFO along with the parity bit, and the receiver will be automatically enabled (RS485CTRL bit 1 will be cleared by hardware). The receiver will also generate an Rx Data Ready Interrupt.

While the receiver is enabled (RS485CTRL bit 1 = ‘0’), all bytes received will be accepted and stored in the RXFIFO until an address byte which does not match the

RS485ADRMATCH value is received. When this occurs, the receiver will be automatically disabled in hardware (RS485CTRL bit 1 will be set), The received non-matching address character will not be stored in the RXFIFO.

RS-485/EIA-485 Auto Direction Control

RS485/EIA-485 mode includes the option of allowing the transmitter to automatically control the state of the DIR pin as a direction control output signal.

Setting RS485CTRL bit 4 = ‘1’ enables this feature.

Direction control, if enabled, will use the RTS pin when RS485CTRL bit 3 = ‘0’. It will use the DTR pin when RS485CTRL bit 3 = ‘1’.

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When Auto Direction Control is enabled, the selected pin will be asserted (driven LOW) when the CPU writes data into the TXFIFO. The pin will be de-asserted (driven HIGH) once the last bit of data has been transmitted. See bits 4 and 5 in the RS485CTRL register.

The RS485CTRL bit 4 takes precedence over all other mechanisms controlling the direction control pin with the exception of loopback mode.

RS485/EIA-485 driver delay time

The driver delay time is the delay between the last stop bit leaving the TXFIFO and the de-assertion of RTS. This delay time can be programmed in the 8-bit RS485DLY register.

The delay time is in periods of the baud clock. Any delay time from 0 to 255 bit times may be used.

RS485/EIA-485 output inversion

The polarity of the direction control signal on the RTS (or DTR) pins can be reversed by programming bit 5 in the U0RS485CTRL register. When this bit is set, the direction control pin will be driven to logic 1 when the transmitter has data waiting to be sent. The direction control pin will be driven to logic 0 after the last bit of data has been transmitted.

13.6 Architecture

The architecture of the UART is shown below in the block diagram.

The APB interface provides a communications link between the CPU or host and the

UART.

The UART receiver block, U0RX, monitors the serial input line, RXD, for valid input. The

UART RX Shift Register (U0RSR) accepts valid characters via RXD. After a valid character is assembled in the U0RSR, it is passed to the UART RX Buffer Register FIFO to await access by the CPU or host via the generic host interface.

The UART transmitter block, U0TX, accepts data written by the CPU or host and buffers the data in the UART TX Holding Register FIFO (U0THR). The UART TX Shift Register

(U0TSR) reads the data stored in the U0THR and assembles the data to transmit via the serial output pin, TXD1.

The UART Baud Rate Generator block, U0BRG, generates the timing enables used by the

UART TX block. The U0BRG clock input source is UART_PCLK. The main clock is divided down per the divisor specified in the U0DLL and U0DLM registers. This divided down clock is a 16x oversample clock, NBAUDOUT.

The interrupt interface contains registers U0IER and U0IIR. The interrupt interface receives several one clock wide enables from the U0TX and U0RX blocks.

Status information from the U0TX and U0RX is stored in the U0LSR. Control information for the U0TX and U0RX is stored in the U0LCR.

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U0INTR

INTERRUPT

U0IER

U0IIR

U0SCR

PA[2:0]

PSEL

PSTB

PWRITE

PD[7:0]

AR

MR

PCLK

Fig 36. UART block diagram

APB

INTERFACE

U0FCR

U0LSR

U0LCR

U0THR

U0TX

U0TSR

NTXRDY

TXD

U0BRG

U0DLL

U0DLM

NBAUDOUT

RCLK

U0RBR

U0RX

U0RSR

NRXRDY

RXD

DDIS

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14.1 How to read this chapter

The SPI blocks are identical for all LPC111x, LPC11D14, and LPC11Cxx parts. The second SPI block, SPI1, is available on LQFP48 packages.

For parts in the LPC1100 and LPC1100L series, SPI1 is not available on HVQFN33 packages.

For parts in the LPC1100XL series, SPI1 is supported on all packages.

Remark:

Both SPI blocks include the full SSP feature set, and all register names use the

SSP prefix.

14.2 Basic configuration

The SPI0/1 are configured using the following registers:

1. Pins: The SPI pins must be configured in the IOCONFIG register block. In addition,

use the IOCON_LOC register (see Section 7.4

) to select a location for the SCK0 function.

2. Power: In the SYSAHBCLKCTRL register, set bit 11 and bit 18 ( Table 21 ).

3. Peripheral clock: Enable the SPI0/1 peripheral clock by writing to the SSP0/1CLKDIV

registers ( Section 3.5.15

and

Section 3.5.17

).

4. Reset: Before accessing the SPI blocks, ensure that the SSP_RST_N bits (bit 0 and bit 2) in the PRESETCTRL register (

Table 9 ) is set to 1. This de-asserts the reset

signal to the SPI blocks.

14.3 Features

Compatible with Motorola SPI, 4-wire TI SSI, and National Semiconductor Microwire buses.

Synchronous Serial Communication.

Supports master or slave operation.

Eight-frame FIFOs for both transmit and receive.

4-bit to 16-bit frame.

14.4 General description

The SPI/SSP is a Synchronous Serial Port (SSP) controller capable of operation on a SPI,

4-wire SSI, or Microwire bus. It can interact with multiple masters and slaves on the bus.

Only a single master and a single slave can communicate on the bus during a given data transfer. Data transfers are in principle full duplex, with frames of 4 bits to 16 bits of data flowing from the master to the slave and from the slave to the master. In practice it is often the case that only one of these data flows carries meaningful data.

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The LPC111x/LPC11Cxx has two SPI/Synchronous Serial Port controllers.

14.5 Pin description

Table 206. SPI pin descriptions

Pin name

Type

Interface pin name/function

SPI SSI Microwire

SCK0/1 I/O SCK CLK SK

Pin description

SSEL0/1 I/O

MISO0/1 I/O

MOSI0/1 I/O

SSEL FS

MISO DR(M)

DX(S)

MOSI DX(M)

DR(S)

CS

SI(M)

SO(S)

SO(M)

SI(S)

Serial Clock.

SCK/CLK/SK is a clock signal used to synchronize the transfer of data. It is driven by the master and received by the slave. When

SPI/SSP interface is used, the clock is programmable to be active-high or active-low, otherwise it is always active-high. SCK only switches during a data transfer. Any other time, the

SPI/SSP interface either holds it in its inactive state or does not drive it (leaves it in high-impedance state).

Frame Sync/Slave Select.

When the SPI/SSP interface is a bus master, it drives this signal to an active state before the start of serial data and then releases it to an inactive state after the data has been sent.The active state of this signal can be high or low depending upon the selected bus and mode. When the SPI/SSP interface is a bus slave, this signal qualifies the presence of data from the

Master according to the protocol in use.

When there is just one bus master and one bus slave, the Frame Sync or Slave Select signal from the Master can be connected directly to the slave’s corresponding input. When there is more than one slave on the bus, further qualification of their Frame

Select/Slave Select inputs will typically be necessary to prevent more than one slave from responding to a transfer.

Master In Slave Out.

The MISO signal transfers serial data from the slave to the master. When the

SPI/SSP is a slave, serial data is output on this signal. When the SPI/SSP is a master, it clocks in serial data from this signal. When the SPI/SSP is a slave and is not selected by FS/SSEL, it does not drive this signal (leaves it in high-impedance state).

Master Out Slave In.

The MOSI signal transfers serial data from the master to the slave. When the

SPI/SSP is a master, it outputs serial data on this signal. When the SPI/SSP is a slave, it clocks in serial data from this signal.

Remark:

The SCK0 function is multiplexed to three different pin locations (two locations on the HVQFN package). Use the IOCON_LOC register (see

Section 7.4

) to select a

physical location for the SCK0 function in addition to selecting the function in the IOCON registers. The SCK1 pin is not multiplexed.

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14.6 Register description

The register addresses of the SPI controllers are shown in

Table 207 and Table 208

.

The reset value reflects the data stored in used bits only. It does not include the content of reserved bits.

Remark:

Register names use the SSP prefix to indicate that the SPI controllers have full

SSP capabilities.

Table 207. Register overview: SPI0 (base address 0x4004 0000)

Name Access Address offset

Description

SSP0CR0 R/W 0x000

SSP0CR1

SSP0DR

SSP0SR

R/W

R/W

RO

0x004

0x008

0x00C

Control Register 1. Selects master/slave and other modes.

Data Register. Writes fill the transmit FIFO, and reads empty the receive

FIFO.

Status Register

Clock Prescale Register

Reset value

0

0

0x0000

0003

0 SSP0CPSR

SSP0IMSC

SSP0RIS

SSP0MIS

SSP0ICR

R/W

R/W

RO

RO

WO

0x010

0x014

0x018

0x01C

0x020

Interrupt Mask Set and Clear Register

Raw Interrupt Status Register

Masked Interrupt Status Register

SSPICR Interrupt Clear Register

0

0x0000

0008

0

NA

Table 208. Register overview: SPI1 (base address 0x4005 8000)

Name Access Address offset

Description

SSP1CR0

SSP1CR1

SSP1DR

R/W 0x000

R/W

R/W

0x004

0x008

SSP1SR

SSP1CPSR

SSP1IMSC

SSP1RIS

RO

R/W

R/W

RO

0x00C

0x010

0x014

0x018

Reset value

Control Register 1. Selects master/slave and other modes.

0

Data Register. Writes fill the transmit FIFO, and reads empty the receive

FIFO.

0

Status Register

Clock Prescale Register

Interrupt Mask Set and Clear Register

Raw Interrupt Status Register

0x0000

0003

0

0

0x0000

0008

SSP1MIS

SSP1ICR

RO

WO

0x01C

0x020

Masked Interrupt Status Register

SSPICR Interrupt Clear Register

0

NA

14.6.1 SPI/SSP Control Register 0

This register controls the basic operation of the SPI/SSP controller.

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Table 209: SPI/SSP Control Register 0 (SSP0CR0 - address 0x4004 0000, SSP1CR0 - address

0x4005 8000) bit description

Bit Symbol Value Description

3:0 DSS

Reset

Value

0000 Data Size Select. This field controls the number of bits transferred in each frame. Values 0000-0010 are not supported and should not be used.

0x3

0x4

0x5

0x6

4-bit transfer

5-bit transfer

6-bit transfer

7-bit transfer

0x7

0x8

0x9

0xA

0xB

0xC

0xD

0xE

0xF

8-bit transfer

9-bit transfer

10-bit transfer

11-bit transfer

12-bit transfer

13-bit transfer

14-bit transfer

15-bit transfer

5:4

6

FRF

CPOL

0x0

0x1

0x2

0x3

0

1

16-bit transfer

Frame Format.

SPI

TI

Microwire

This combination is not supported and should not be used.

Clock Out Polarity. This bit is only used in SPI mode.

SPI controller maintains the bus clock low between frames.

00

0

7

15:8

31:16 -

CPHA

SCR

-

0

1

SPI controller maintains the bus clock high between frames.

Clock Out Phase. This bit is only used in SPI mode.

SPI controller captures serial data on the first clock transition of the frame, that is, the transition

away from

the inter-frame state of the clock line.

SPI controller captures serial data on the second clock transition of the frame, that is, the transition

back to

the inter-frame state of the clock line.

0

Serial Clock Rate. The number of prescaler output clocks per bit on the bus, minus one. Given that CPSDVSR is the prescale divider, and the APB clock PCLK clocks the prescaler, the bit frequency is PCLK / (CPSDVSR

[SCR+1]).

0x00

Reserved -

14.6.2 SPI/SSP0 Control Register 1

This register controls certain aspects of the operation of the SPI/SSP controller.

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Table 210: SPI/SSP Control Register 1 (SSP0CR1 - address 0x4004 0004, SSP1CR1 - address

0x4005 8004) bit description

Bit Symbol Value Description

0 LBM Loop Back Mode.

Reset

Value

0

0

1

During normal operation.

Serial input is taken from the serial output (MOSI or MISO) rather than the serial input pin (MISO or MOSI respectively).

1 SSE

2 MS

0

1

0

SPI Enable.

The SPI controller is disabled.

The SPI controller will interact with other devices on the serial bus. Software should write the appropriate control information to the other SPI/SSP registers and interrupt controller registers, before setting this bit.

0

Master/Slave Mode.This bit can only be written when the

SSE bit is 0.

The SPI controller acts as a master on the bus, driving the

SCLK, MOSI, and SSEL lines and receiving the MISO line.

0

3

31:4 -

SOD

1 The SPI controller acts as a slave on the bus, driving MISO line and receiving SCLK, MOSI, and SSEL lines.

Slave Output Disable. This bit is relevant only in slave mode (MS = 1). If it is 1, this blocks this SPI controller from driving the transmit data line (MISO).

0

Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined.

NA

14.6.3 SPI/SSP Data Register

Software can write data to be transmitted to this register and read data that has been received.

Table 211: SPI/SSP Data Register (SSP0DR - address 0x4004 0008, SSP1DR - address

0x4005 8008) bit description

Bit Symbol Description Reset Value

15:0 DATA

31:16 -

Write:

software can write data to be sent in a future frame to this register whenever the TNF bit in the Status register is 1, indicating that the Tx FIFO is not full. If the Tx FIFO was previously empty and the SPI controller is not busy on the bus, transmission of the data will begin immediately. Otherwise the data written to this register will be sent as soon as all previous data has been sent (and received). If the data length is less than

16 bit, software must right-justify the data written to this register.

0x0000

Read:

software can read data from this register whenever the

RNE bit in the Status register is 1, indicating that the Rx FIFO is not empty. When software reads this register, the SPI controller returns data from the least recent frame in the Rx FIFO. If the data length is less than 16 bit, the data is right-justified in this field with higher order bits filled with 0s.

Reserved.

-

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14.6.4 SPI/SSP Status Register

This read-only register reflects the current status of the SPI controller.

Table 212: SPI/SSP Status Register (SSP0SR - address 0x4004 000C, SSP1SR - address

0x4005 800C) bit description

Bit

0

1

2

Symbol

TFE

TNF

RNE

Description

Transmit FIFO Empty. This bit is 1 is the Transmit FIFO is empty, 0 if not.

Reset Value

1

Transmit FIFO Not Full. This bit is 0 if the Tx FIFO is full, 1 if not. 1

0

3 RFF

Receive FIFO Not Empty. This bit is 0 if the Receive FIFO is empty, 1 if not.

Receive FIFO Full. This bit is 1 if the Receive FIFO is full, 0 if not.

0

4 BSY

31:5 -

Busy. This bit is 0 if the SPI controller is idle, 1 if it is currently sending/receiving a frame and/or the Tx FIFO is not empty.

0

Reserved, user software should not write ones to reserved bits.

The value read from a reserved bit is not defined.

NA

14.6.5 SPI/SSP Clock Prescale Register

This register controls the factor by which the Prescaler divides the SPI peripheral clock

SPI_PCLK to yield the prescaler clock that is, in turn, divided by the SCR factor in the

SSPCR0 registers, to determine the bit clock.

Table 213: SPI/SSP Clock Prescale Register (SSP0CPSR - address 0x4004 0010, SSP1CPSR - address 0x4005 8010) bit description

Bit

7:0

Symbol Description

CPSDVSR This even value between 2 and 254, by which SPI_PCLK is divided to yield the prescaler output clock. Bit 0 always reads as 0.

Reset Value

0

31:8 Reserved.

-

Important:

the SSPnCPSR value must be properly initialized, or the SPI controller will not be able to transmit data correctly.

In Slave mode, the SPI clock rate provided by the master must not exceed 1/12 of the SPI peripheral clock selected in

Section 3.5.15

. The content of the SSPnCPSR register is not

relevant.

In master mode, CPSDVSR min

= 2 or larger (even numbers only).

14.6.6 SPI/SSP Interrupt Mask Set/Clear Register

This register controls whether each of the four possible interrupt conditions in the SPI controller are enabled. Note that ARM uses the word “masked” in the opposite sense from classic computer terminology, in which “masked” meant “disabled”. ARM uses the word

“masked” to mean “enabled”. To avoid confusion we will not use the word “masked”.

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Table 214: SPI/SSP Interrupt Mask Set/Clear register (SSP0IMSC - address 0x4004 0014,

SSP1IMSC - address 0x4005 8014) bit description

Bit Symbol

0

1

2

3

31:4 -

RORIM

RTIM

RXIM

TXIM

Description

Software should set this bit to enable interrupt when a Receive

Overrun occurs, that is, when the Rx FIFO is full and another frame is completely received. The ARM spec implies that the preceding frame data is overwritten by the new frame data when this occurs.

0

Reset

Value

Software should set this bit to enable interrupt when a Receive

Time-out condition occurs. A Receive Time-out occurs when the Rx

FIFO is not empty, and no has not been read for a time-out period.

The time-out period is the same for master and slave modes and is determined by the SSP bit rate: 32 bits at PCLK / (CPSDVSR

[SCR+1]).

0

Software should set this bit to enable interrupt when the Rx FIFO is at least half full.

0

Software should set this bit to enable interrupt when the Tx FIFO is at least half empty.

0

Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined.

NA

14.6.7 SPI/SSP Raw Interrupt Status Register

This read-only register contains a 1 for each interrupt condition that is asserted, regardless of whether or not the interrupt is enabled in the SSPIMSC registers.

Table 215: SPI/SSP Raw Interrupt Status register (SSP0RIS - address 0x4004 0018, SSP1RIS

- address 0x4005 8018) bit description

Bit Symbol Description Reset Value

0 RORRIS This bit is 1 if another frame was completely received while the

RxFIFO was full. The ARM spec implies that the preceding frame data is overwritten by the new frame data when this occurs.

0

1 RTRIS

2

3

31:4 -

RXRIS

TXRIS

This bit is 1 if the Rx FIFO is not empty, and has not been read for a time-out period. The time-out period is the same for master and slave modes and is determined by the SSP bit rate: 32 bits at PCLK / (CPSDVSR

[SCR+1]).

0

This bit is 1 if the Rx FIFO is at least half full.

This bit is 1 if the Tx FIFO is at least half empty.

0

1

Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined.

NA

14.6.8 SPI/SSP Masked Interrupt Status Register

This read-only register contains a 1 for each interrupt condition that is asserted and enabled in the SSPIMSC registers. When an SPI interrupt occurs, the interrupt service routine should read this register to determine the cause(s) of the interrupt.

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Table 216: SPI/SSP Masked Interrupt Status register (SSP0MIS - address 0x4004 001C,

SSP1MIS - address 0x4005 801C) bit description

Bit

0

Symbol

RORMIS

Description

This bit is 1 if another frame was completely received while the

RxFIFO was full, and this interrupt is enabled.

Reset Value

0

1

2

3

31:4 -

RTMIS

RXMIS

TXMIS

This bit is 1 if the Rx FIFO is not empty, has not been read for a time-out period, and this interrupt is enabled. The time-out period is the same for master and slave modes and is determined by the SSP bit rate: 32 bits at PCLK / (CPSDVSR

[SCR+1]).

0

This bit is 1 if the Rx FIFO is at least half full, and this interrupt is enabled.

0

0 This bit is 1 if the Tx FIFO is at least half empty, and this interrupt is enabled.

Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined.

NA

14.6.9 SPI/SSP Interrupt Clear Register

Software can write one or more one(s) to this write-only register, to clear the corresponding interrupt condition(s) in the SPI controller. Note that the other two interrupt conditions can be cleared by writing or reading the appropriate FIFO or disabled by clearing the corresponding bit in SSPIMSC registers.

Table 217: SPI/SSP interrupt Clear Register (SSP0ICR - address 0x4004 0020, SSP1ICR - address 0x4005 8020) bit description

Bit

0

1

31:2 -

Symbol

RORIC

RTIC

Description

Writing a 1 to this bit clears the “frame was received when

RxFIFO was full” interrupt.

Writing a 1 to this bit clears the Rx FIFO was not empty and has not been read for a timeout period interrupt. The timeout period is the same for master and slave modes and is determined by the SSP bit rate: 32 bits at PCLK / (CPSDVSR

[SCR+1]).

Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined.

Reset Value

NA

NA

NA

14.7 Functional description

14.7.1 Texas Instruments synchronous serial frame format

Figure 37

shows the 4-wire Texas Instruments synchronous serial frame format supported by the SPI module.

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CLK

FS

DX/DR

MSB LSB

4 to 16 bits a. Single frame transfer

CLK

FS

DX/DR

MSB LSB MSB LSB

4 to 16 bits 4 to 16 bits b. Continuous/back-to-back frames transfer

Fig 37. Texas Instruments Synchronous Serial Frame Format: a) Single and b) Continuous/back-to-back Two

Frames Transfer

For device configured as a master in this mode, CLK and FS are forced LOW, and the transmit data line DX is in 3-state mode whenever the SSP is idle. Once the bottom entry of the transmit FIFO contains data, FS is pulsed HIGH for one CLK period. The value to be transmitted is also transferred from the transmit FIFO to the serial shift register of the transmit logic. On the next rising edge of CLK, the MSB of the 4-bit to 16-bit data frame is shifted out on the DX pin. Likewise, the MSB of the received data is shifted onto the DR pin by the off-chip serial slave device.

Both the SSP and the off-chip serial slave device then clock each data bit into their serial shifter on the falling edge of each CLK. The received data is transferred from the serial shifter to the receive FIFO on the first rising edge of CLK after the LSB has been latched.

14.7.2 SPI frame format

The SPI interface is a four-wire interface where the SSEL signal behaves as a slave select. The main feature of the SPI format is that the inactive state and phase of the SCK signal are programmable through the CPOL and CPHA bits within the SSPCR0 control register.

14.7.2.1 Clock Polarity (CPOL) and Phase (CPHA) control

When the CPOL clock polarity control bit is LOW, it produces a steady state low value on the SCK pin. If the CPOL clock polarity control bit is HIGH, a steady state high value is placed on the CLK pin when data is not being transferred.

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The CPHA control bit selects the clock edge that captures data and allows it to change state. It has the most impact on the first bit transmitted by either allowing or not allowing a clock transition before the first data capture edge. When the CPHA phase control bit is

LOW, data is captured on the first clock edge transition. If the CPHA clock phase control bit is HIGH, data is captured on the second clock edge transition.

14.7.2.2 SPI format with CPOL=0,CPHA=0

Single and continuous transmission signal sequences for SPI format with CPOL = 0,

CPHA = 0 are shown in Figure 38

.

SCK

SSEL

MOSI

MISO

MSB

MSB

LSB

LSB Q

4 to 16 bits a. Single transfer with CPOL=0 and CPHA=0

SCK

SSEL

MOSI

MISO

MSB

MSB

LSB

LSB Q

MSB

MSB

4 to 16 bits 4 to 16 bits b. Continuous transfer with CPOL=0 and CPHA=0

Fig 38. SPI frame format with CPOL=0 and CPHA=0 (a) Single and b) Continuous Transfer)

LSB

LSB Q

In this configuration, during idle periods:

The CLK signal is forced LOW.

SSEL is forced HIGH.

The transmit MOSI/MISO pad is in high impedance.

If the SPI/SSP is enabled and there is valid data within the transmit FIFO, the start of transmission is signified by the SSEL master signal being driven LOW. This causes slave data to be enabled onto the MISO input line of the master. Master’s MOSI is enabled.

One half SCK period later, valid master data is transferred to the MOSI pin. Now that both the master and slave data have been set, the SCK master clock pin goes HIGH after one further half SCK period.

The data is captured on the rising and propagated on the falling edges of the SCK signal.

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In the case of a single word transmission, after all bits of the data word have been transferred, the SSEL line is returned to its idle HIGH state one SCK period after the last bit has been captured.

However, in the case of continuous back-to-back transmissions, the SSEL signal must be pulsed HIGH between each data word transfer. This is because the slave select pin freezes the data in its serial peripheral register and does not allow it to be altered if the

CPHA bit is logic zero. Therefore the master device must raise the SSEL pin of the slave device between each data transfer to enable the serial peripheral data write. On completion of the continuous transfer, the SSEL pin is returned to its idle state one SCK period after the last bit has been captured.

14.7.2.3 SPI format with CPOL=0,CPHA=1

The transfer signal sequence for SPI format with CPOL = 0, CPHA = 1 is shown in

Figure 39

, which covers both single and continuous transfers.

SCK

SSEL

MOSI

MISO

Q

MSB

MSB

LSB

LSB Q

4 to 16 bits

Fig 39. SPI frame format with CPOL=0 and CPHA=1

In this configuration, during idle periods:

The CLK signal is forced LOW.

SSEL is forced HIGH.

The transmit MOSI/MISO pad is in high impedance.

If the SPI/SSP is enabled and there is valid data within the transmit FIFO, the start of transmission is signified by the SSEL master signal being driven LOW. Master’s MOSI pin is enabled. After a further one half SCK period, both master and slave valid data is enabled onto their respective transmission lines. At the same time, the SCK is enabled with a rising edge transition.

Data is then captured on the falling edges and propagated on the rising edges of the SCK signal.

In the case of a single word transfer, after all bits have been transferred, the SSEL line is returned to its idle HIGH state one SCK period after the last bit has been captured.

For continuous back-to-back transfers, the SSEL pin is held LOW between successive data words and termination is the same as that of the single word transfer.

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14.7.2.4 SPI format with CPOL = 1,CPHA = 0

Single and continuous transmission signal sequences for SPI format with CPOL=1,

CPHA=0 are shown in

Figure 40

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SCK

SSEL

MOSI

MISO

MSB

MSB

LSB

LSB Q

4 to 16 bits a. Single transfer with CPOL=1 and CPHA=0

SCK

SSEL

MOSI

MISO

MSB

MSB

LSB

LSB Q

MSB

MSB

4 to 16 bits 4 to 16 bits b. Continuous transfer with CPOL=1 and CPHA=0

Fig 40. SPI frame format with CPOL = 1 and CPHA = 0 (a) Single and b) Continuous Transfer)

LSB

LSB Q

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In this configuration, during idle periods:

The CLK signal is forced HIGH.

SSEL is forced HIGH.

The transmit MOSI/MISO pad is in high impedance.

If the SPI/SSP is enabled and there is valid data within the transmit FIFO, the start of transmission is signified by the SSEL master signal being driven LOW, which causes slave data to be immediately transferred onto the MISO line of the master. Master’s MOSI pin is enabled.

One half period later, valid master data is transferred to the MOSI line. Now that both the master and slave data have been set, the SCK master clock pin becomes LOW after one further half SCK period. This means that data is captured on the falling edges and be propagated on the rising edges of the SCK signal.

In the case of a single word transmission, after all bits of the data word are transferred, the

SSEL line is returned to its idle HIGH state one SCK period after the last bit has been captured.

However, in the case of continuous back-to-back transmissions, the SSEL signal must be pulsed HIGH between each data word transfer. This is because the slave select pin freezes the data in its serial peripheral register and does not allow it to be altered if the

CPHA bit is logic zero. Therefore the master device must raise the SSEL pin of the slave device between each data transfer to enable the serial peripheral data write. On completion of the continuous transfer, the SSEL pin is returned to its idle state one SCK period after the last bit has been captured.

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14.7.2.5 SPI format with CPOL = 1,CPHA = 1

The transfer signal sequence for SPI format with CPOL = 1, CPHA = 1 is shown in

Figure 41

, which covers both single and continuous transfers.

SCK

SSEL

MOSI

MISO

Q

MSB

MSB

LSB

LSB Q

4 to 16 bits

Fig 41. SPI Frame Format with CPOL = 1 and CPHA = 1

In this configuration, during idle periods:

The CLK signal is forced HIGH.

SSEL is forced HIGH.

The transmit MOSI/MISO pad is in high impedance.

If the SPI/SSP is enabled and there is valid data within the transmit FIFO, the start of transmission is signified by the SSEL master signal being driven LOW. Master’s MOSI is enabled. After a further one half SCK period, both master and slave data are enabled onto their respective transmission lines. At the same time, the SCK is enabled with a falling edge transition. Data is then captured on the rising edges and propagated on the falling edges of the SCK signal.

After all bits have been transferred, in the case of a single word transmission, the SSEL line is returned to its idle HIGH state one SCK period after the last bit has been captured.

For continuous back-to-back transmissions, the SSEL pins remains in its active LOW state, until the final bit of the last word has been captured, and then returns to its idle state as described above. In general, for continuous back-to-back transfers the SSEL pin is held LOW between successive data words and termination is the same as that of the single word transfer.

14.7.3 Semiconductor Microwire frame format

Figure 42

shows the Microwire frame format for a single frame.

Figure 43 shows the same

format when back-to-back frames are transmitted.

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Chapter 14: LPC111x/LPC11Cxx SPI0/1 with SSP

SK

CS

MSB LSB

SO

SI

8-bit control

0 MSB LSB

4 to 16 bits of output data

Fig 42. Microwire frame format (single transfer)

SK

CS

SO

SI

LSB MSB

8-bit control

LSB

0 MSB LSB

4 to 16 bits of output data

MSB LSB

4 to 16 bits of output data

Fig 43. Microwire frame format (continuous transfers)

Microwire format is very similar to SPI format, except that transmission is half-duplex instead of full-duplex, using a master-slave message passing technique. Each serial transmission begins with an 8-bit control word that is transmitted from the SPI/SSP to the off-chip slave device. During this transmission, no incoming data is received by the

SPI/SSP. After the message has been sent, the off-chip slave decodes it and, after waiting one serial clock after the last bit of the 8-bit control message has been sent, responds with the required data. The returned data is 4 to 16 bit in length, making the total frame length anywhere from 13 to 25 bits.

In this configuration, during idle periods:

The SK signal is forced LOW.

CS is forced HIGH.

The transmit data line SO is arbitrarily forced LOW.

A transmission is triggered by writing a control byte to the transmit FIFO.The falling edge of CS causes the value contained in the bottom entry of the transmit FIFO to be transferred to the serial shift register of the transmit logic, and the MSB of the 8-bit control frame to be shifted out onto the SO pin. CS remains LOW for the duration of the frame transmission. The SI pin remains tristated during this transmission.

The off-chip serial slave device latches each control bit into its serial shifter on the rising edge of each SK. After the last bit is latched by the slave device, the control byte is decoded during a one clock wait-state, and the slave responds by transmitting data back to the SPI/SSP. Each bit is driven onto SI line on the falling edge of SK. The SPI/SSP in

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turn latches each bit on the rising edge of SK. At the end of the frame, for single transfers, the CS signal is pulled HIGH one clock period after the last bit has been latched in the receive serial shifter, that causes the data to be transferred to the receive FIFO.

Note:

The off-chip slave device can tristate the receive line either on the falling edge of

SK after the LSB has been latched by the receive shiftier, or when the CS pin goes HIGH.

For continuous transfers, data transmission begins and ends in the same manner as a single transfer. However, the CS line is continuously asserted (held LOW) and transmission of data occurs back to back. The control byte of the next frame follows directly after the LSB of the received data from the current frame. Each of the received values is transferred from the receive shifter on the falling edge SK, after the LSB of the frame has been latched into the SPI/SSP.

14.7.3.1 Setup and hold time requirements on CS with respect to SK in Microwire mode

In the Microwire mode, the SPI/SSP slave samples the first bit of receive data on the rising edge of SK after CS has gone LOW. Masters that drive a free-running SK must ensure that the CS signal has sufficient setup and hold margins with respect to the rising edge of SK.

Figure 44

illustrates these setup and hold time requirements. With respect to the SK rising edge on which the first bit of receive data is to be sampled by the SPI/SSP slave, CS must have a setup of at least two times the period of SK on which the SPI/SSP operates. With respect to the SK rising edge previous to this edge, CS must have a hold of at least one

SK period.

t

HOLD

= t

SK t

SETUP

=2*t

SK

SK

CS

SI

Fig 44. Microwire frame format setup and hold details

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Chapter 15: LPC111x/LPC11Cxx I2C-bus controller

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15.1 How to read this chapter

The I

2

C-bus block is identical for all LPC111x, LPC11D14, and LPC11Cxx parts.

The I2C-bus is interface is not available on part LPC1112FDH20/102.

15.2 Basic configuration

The I

2

C-bus interface is configured using the following registers:

1. Pins: The I2C pin functions and the I2C mode are configured in the IOCONFIG

register block ( Section 7.4

, Table 68

and Table 69

).

2. Power and peripheral clock: In the SYSAHBCLKCTRL register, set bit 5 ( Table 21 ).

3. Reset: Before accessing the I2C block, ensure that the I2C_RST_N bit (bit 1) in the

PRESETCTRL register ( Table 9

) is set to 1. This de-asserts the reset signal to the I2C block.

15.3 Features

Standard I

2

C-compliant bus interfaces may be configured as Master, Slave, or

Master/Slave.

Arbitration is handled between simultaneously transmitting masters without corruption of serial data on the bus.

Programmable clock allows adjustment of I

2

C transfer rates.

Data transfer is bidirectional between masters and slaves.

Serial clock synchronization allows devices with different bit rates to communicate via one serial bus.

Serial clock synchronization is used as a handshake mechanism to suspend and resume serial transfer.

Supports Fast-mode Plus.

Optional recognition of up to four distinct slave addresses.

Monitor mode allows observing all I

2

C-bus traffic, regardless of slave address.

I

2

C-bus can be used for test and diagnostic purposes.

The I

2

C-bus contains a standard I

2

C-compliant bus interface with two pins.

15.4 Applications

Interfaces to external I

2

C standard parts, such as serial RAMs, LCDs, tone generators, other microcontrollers, etc.

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Chapter 15: LPC111x/LPC11Cxx I2C-bus controller

15.5 General description

A typical I

2

C-bus configuration is shown in Figure 45 . Depending on the state of the

direction bit (R/W), two types of data transfers are possible on the I

2

C-bus:

Data transfer from a master transmitter to a slave receiver. The first byte transmitted by the master is the slave address. Next follows a number of data bytes. The slave returns an acknowledge bit after each received byte.

Data transfer from a slave transmitter to a master receiver. The first byte (the slave address) is transmitted by the master. The slave then returns an acknowledge bit.

Next follows the data bytes transmitted by the slave to the master. The master returns an acknowledge bit after all received bytes other than the last byte. At the end of the last received byte, a “not acknowledge” is returned. The master device generates all of the serial clock pulses and the START and STOP conditions. A transfer is ended with a STOP condition or with a Repeated START condition. Since a Repeated

START condition is also the beginning of the next serial transfer, the I

2

C bus will not be released.

The I

2

C interface is byte oriented and has four operating modes: master transmitter mode, master receiver mode, slave transmitter mode and slave receiver mode.

The I

2

C interface complies with the entire I

2

C specification, supporting the ability to turn power off to the ARM Cortex-M0 without interfering with other devices on the same

I

2

C-bus. pull-up resistor pull-up resistor

SDA

I 2 C bus

SCL

SDA

SCL

LPC11xx

OTHER DEVICE WITH

I

2

C INTERFACE

OTHER DEVICE WITH

I

2

C INTERFACE

Fig 45. I

2

C-bus configuration

15.5.1 I

2

C Fast-mode Plus

Fast-Mode Plus supports a 1 Mbit/sec transfer rate to communicate with the I

2

C-bus products which NXP Semiconductors is now providing.

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Chapter 15: LPC111x/LPC11Cxx I2C-bus controller

15.6 Pin description

Table 218. I

2

C-bus pin description

Pin Type

SDA

SCL

Input/Output

Input/Output

Description

I

2

C Serial Data

I

2

C Serial Clock

The I

2

C-bus pins must be configured through the IOCON_PIO0_4 ( Table 68 ) and

IOCON_PIO0_5 ( Table 69 ) registers for Standard/ Fast-mode or Fast-mode Plus. In

Fast-mode Plus, rates above 400 kHz and up to 1 MHz may be selected. The I

2

C-bus pins are open-drain outputs and fully compatible with the I

2

C-bus specification.

15.7 Register description

Table 219. Register overview: I

2

C (base address 0x4000 0000)

Name

I2C0CONSET

I2C0STAT

Access Address

R/W

RO

offset

0x000

0x004

Description Reset

value

[1]

I2C Control Set Register.

When a one is written to a bit of this register, the corresponding bit in the I

2

C control register is set. Writing a zero has no effect on the corresponding bit in the I

2

C control register.

I2C Status Register.

During I

2

C operation, this register provides detailed status codes that allow software to determine the next action needed.

0x00

0xF8

I2C0DAT R/W 0x008

I2C0ADR0

I2C0SCLH

I2C0SCLL

R/W

R/W

R/W

I2C0CONCLR WO

0x00C

0x010

0x014

0x018

I2C Data Register.

During master or slave transmit mode, data to be transmitted is written to this register. During master or slave receive mode, data that has been received may be read from this register.

I2C Slave Address Register 0.

Contains the 7-bit slave address for operation of the I

2

C interface in slave mode, and is not used in master mode. The least significant bit determines whether a slave responds to the General Call address.

0x00

0x00

SCH Duty Cycle Register High Half Word.

Determines the high time of the I

2

C clock.

0x04

SCL Duty Cycle Register Low Half Word.

Determines the low time of the I

2

C clock. I2nSCLL and I2nSCLH together determine the clock frequency generated by an I

2

C master and certain times used in slave mode.

0x04

I2C Control Clear Register.

When a one is written to a bit of this register, the corresponding bit in the I

2

C control register is cleared. Writing a zero has no effect on the corresponding bit in the I

2

C control register.

NA

I2C0MMCTRL R/W 0x01C

Monitor mode control register.

0x00

I2C0ADR1

I2C0ADR2

R/W

R/W

0x020

0x024

I2C Slave Address Register 1.

Contains the 7-bit slave address for operation of the I

2

C interface in slave mode, and is not used in master mode. The least significant bit determines whether a slave responds to the General Call address.

I2C Slave Address Register 2.

Contains the 7-bit slave address for operation of the I

2

C interface in slave mode, and is not used in master mode. The least significant bit determines whether a slave responds to the General Call address.

0x00

0x00

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Chapter 15: LPC111x/LPC11Cxx I2C-bus controller

Table 219. Register overview: I

2

C (base address 0x4000 0000)

…continued

Name Access Address offset

Description

I2C0ADR3 R/W 0x028

I2C0DATA_

BUFFER

RO 0x02C

I2C Slave Address Register 3.

Contains the 7-bit slave address for operation of the I

2

C interface in slave mode, and is not used in master mode. The least significant bit determines whether a slave responds to the General Call address.

Data buffer register.

The contents of the 8 MSBs of the I2DAT shift register will be transferred to the DATA_BUFFER automatically after every nine bits (8 bits of data plus ACK or NACK) has been received on the bus.

I2C0MASK0

I2C0MASK1

I2C0MASK2

I2C0MASK3

R/W

R/W

R/W

R/W

0x030

0x034

0x038

0x03C

I2C Slave address mask register 0

. This mask register is associated with I2ADR0 to determine an address match. The mask register has no effect when comparing to the General Call address (‘0000000’).

I2C Slave address mask register 1

. This mask register is associated with I2ADR1 to determine an address match. The mask register has no effect when comparing to the General Call address (‘0000000’).

I2C Slave address mask register 2

. This mask register is associated with I2ADR2 to determine an address match. The mask register has no effect when comparing to the General Call address (‘0000000’).

I2C Slave address mask register 3

. This mask register is associated with I2ADR3 to determine an address match. The mask register has no effect when comparing to the General Call address (‘0000000’).

Reset value

[1]

0x00

0x00

0x00

0x00

0x00

0x00

[1] Reset value reflects the data stored in used bits only. It does not include reserved bits content.

15.7.1 I

2

C Control Set register (I2C0CONSET - 0x4000 0000)

The CONSET registers control setting of bits in the CON register that controls operation of the I

2

C interface. Writing a one to a bit of this register causes the corresponding bit in the

I

2

C control register to be set. Writing a zero has no effect.

4

5

2

3

Table 220. I

2

C Control Set register (I2C0CONSET - address 0x4000 0000) bit description

Bit Symbol Description Reset value

1:0 -

6

31:7 -

AA

SI

STO

STA

I2EN

Reserved. User software should not write ones to reserved bits. The value read from a reserved bit is not defined.

NA

Assert acknowledge flag.

I

2

C interrupt flag.

0

STOP flag.

START flag.

I

2

C interface enable.

Reserved. The value read from a reserved bit is not defined.

-

0

0

0

I2EN

I

2

C Interface Enable. When I2EN is 1, the I

2

C interface is enabled. I2EN can be cleared by writing 1 to the I2ENC bit in the CONCLR register. When I2EN is 0, the I

2

C interface is disabled.

When I2EN is “0”, the SDA and SCL input signals are ignored, the I

2

C block is in the “not addressed” slave state, and the STO bit is forced to “0”.

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Chapter 15: LPC111x/LPC11Cxx I2C-bus controller

I2EN should not be used to temporarily release the I

2

C-bus since, when I2EN is reset, the

I

2

C-bus status is lost. The AA flag should be used instead.

STA

is the START flag. Setting this bit causes the I

2

C interface to enter master mode and transmit a START condition or transmit a Repeated START condition if it is already in master mode.

When STA is 1 and the I

2

C interface is not already in master mode, it enters master mode, checks the bus and generates a START condition if the bus is free. If the bus is not free, it waits for a STOP condition (which will free the bus) and generates a START condition after a delay of a half clock period of the internal clock generator. If the I

2

C interface is already in master mode and data has been transmitted or received, it transmits a

Repeated START condition. STA may be set at any time, including when the I

2

C interface is in an addressed slave mode.

STA can be cleared by writing 1 to the STAC bit in the CONCLR register. When STA is 0, no START condition or Repeated START condition will be generated.

If STA and STO are both set, then a STOP condition is transmitted on the I

2

C-bus if it the interface is in master mode, and transmits a START condition thereafter. If the I

2

C interface is in slave mode, an internal STOP condition is generated, but is not transmitted on the bus.

STO

is the STOP flag. Setting this bit causes the I

2

C interface to transmit a STOP condition in master mode, or recover from an error condition in slave mode. When STO is

1 in master mode, a STOP condition is transmitted on the I

2

C-bus. When the bus detects the STOP condition, STO is cleared automatically.

In slave mode, setting this bit can recover from an error condition. In this case, no STOP condition is transmitted to the bus. The hardware behaves as if a STOP condition has been received and it switches to “not addressed” slave receiver mode. The STO flag is cleared by hardware automatically.

SI

is the I

2

C Interrupt Flag. This bit is set when the I

2

C state changes. However, entering state F8 does not set SI since there is nothing for an interrupt service routine to do in that case.

While SI is set, the low period of the serial clock on the SCL line is stretched, and the serial transfer is suspended. When SCL is HIGH, it is unaffected by the state of the SI flag.

SI must be reset by software, by writing a 1 to the SIC bit in the CONCLR register.

AA

is the Assert Acknowledge Flag. When set to 1, an acknowledge (low level to SDA) will be returned during the acknowledge clock pulse on the SCL line on the following situations:

1. The address in the Slave Address Register has been received.

2. The General Call address has been received while the General Call bit (GC) in the

ADR register is set.

3. A data byte has been received while the I

2

C is in the master receiver mode.

4. A data byte has been received while the I

2

C is in the addressed slave receiver mode

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Chapter 15: LPC111x/LPC11Cxx I2C-bus controller

The AA bit can be cleared by writing 1 to the AAC bit in the CONCLR register. When AA is

0, a not acknowledge (HIGH level to SDA) will be returned during the acknowledge clock pulse on the SCL line on the following situations:

1. A data byte has been received while the I

2

C is in the master receiver mode.

2. A data byte has been received while the I

2

C is in the addressed slave receiver mode.

15.7.2 I

2

C Status register (I2C0STAT - 0x4000 0004)

Each I

2

C Status register reflects the condition of the corresponding I

2

C interface. The I

2

C

Status register is Read-Only.

Table 221. I

2

C Status register (I2C0STAT - 0x4000 0004) bit description

Bit

2:0

7:3

-

Symbol

Status

Description

These bits are unused and are always 0.

These bits give the actual status information about the I

2

C interface.

31:8 Reserved. The value read from a reserved bit is not defined.

Reset value

0

0x1F

-

The three least significant bits are always 0. Taken as a byte, the status register contents represent a status code. There are 26 possible status codes. When the status code is

0xF8, there is no relevant information available and the SI bit is not set. All other 25 status codes correspond to defined I

2

C states. When any of these states entered, the SI bit will

be set. For a complete list of status codes, refer to tables from Table 236

to Table 241

.

15.7.3 I

2

C Data register (I2C0DAT - 0x4000 0008)

This register contains the data to be transmitted or the data just received. The CPU can read and write to this register only while it is not in the process of shifting a byte, when the

SI bit is set. Data in DAT register remains stable as long as the SI bit is set. Data in DAT register is always shifted from right to left: the first bit to be transmitted is the MSB (bit 7), and after a byte has been received, the first bit of received data is located at the MSB of the DAT register.

Table 222. I

2

C Data register (I2C0DAT - 0x4000 0008) bit description

Bit

7:0

31:8 -

Symbol

Data

Description Reset value

This register holds data values that have been received or are to be transmitted.

0

Reserved. The value read from a reserved bit is not defined.

-

15.7.4 I

2

C Slave Address register 0 (I2C0ADR0- 0x4000 000C)

This register is readable and writable and are only used when an I

2

C interface is set to slave mode. In master mode, this register has no effect. The LSB of the ADR register is the General Call bit. When this bit is set, the General Call address (0x00) is recognized.

If this register contains 0x00, the I

2

C will not acknowledge any address on the bus. All four registers (ADR0 to ADR3) will be cleared to this disabled state on reset. See also

Table 229 .

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Chapter 15: LPC111x/LPC11Cxx I2C-bus controller

Table 223. I

2

C Slave Address register 0 (I2C0ADR0- 0x4000 000C) bit description

Bit

0

7:1

Symbol

GC

Address

31:8 -

Description

General Call enable bit.

The I

2

C device address for slave mode.

Reserved. The value read from a reserved bit is not defined.

-

Reset value

0

0x00

15.7.5 I

2

C SCL HIGH and LOW duty cycle registers (I2C0SCLH - 0x4000 0010 and I2C0SCLL- 0x4000 0014)

Table 224. I

2

C SCL HIGH Duty Cycle register (I2C0SCLH - address 0x4000 0010) bit description

Bit

15:0

31:16 -

Symbol

SCLH

Description

Count for SCL HIGH time period selection.

Reserved. The value read from a reserved bit is not defined.

-

Reset value

0x0004

Table 225. I

2

C SCL Low duty cycle register (I2C0SCLL - 0x4000 0014) bit description

Bit

15:0

31:16 -

Symbol

SCLL

Description

Count for SCL low time period selection.

Reserved. The value read from a reserved bit is not defined.

-

Reset value

0x0004

15.7.5.1 Selecting the appropriate I

2

C data rate and duty cycle

Software must set values for the registers SCLH and SCLL to select the appropriate data rate and duty cycle. SCLH defines the number of I2C_PCLK cycles for the SCL HIGH time, SCLL defines the number of I2C_PCLK cycles for the SCL low time. The frequency is determined by the following formula (I2C_PCLK is the frequency of the peripheral I2C clock):

(4)

I2C bitfrequency

=

SCLH

+

SCLL

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The values for SCLL and SCLH must ensure that the data rate is in the appropriate I

2

C

data rate range. Each register value must be greater than or equal to 4. Table 226

gives some examples of I

2

C-bus rates based on I2C_PCLK frequency and SCLL and SCLH values.

Table 226. SCLL + SCLH values for selected I

2

C clock values

I

2

C mode I

2

C bit frequency

6 8 10

I2C_PCLK (MHz)

12 16 20

SCLH + SCLL

Standard mode

Fast-mode

Fast-mode Plus

100 kHz

400 kHz

1 MHz -

60

15

80

20

8

100

25

10

120

30

12

160

40

16

200

50

20

30

300

75

30

40

400

100

40

50

500

125

50

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SCLL and SCLH values should not necessarily be the same. Software can set different duty cycles on SCL by setting these two registers. For example, the I

2

C-bus specification defines the SCL low time and high time at different values for a Fast-mode and Fast-mode

Plus I

2

C.

15.7.6 I

2

C Control Clear register (I2C0CONCLR - 0x4000 0018)

The CONCLR register control clearing of bits in the CON register that controls operation of the I

2

C interface. Writing a one to a bit of this register causes the corresponding bit in the I

2

C control register to be cleared. Writing a zero has no effect.

5

6

7

2

3

4

Table 227. I

2

C Control Clear register (I2C0CONCLR - 0x4000 0018) bit description

Bit Symbol Description

1:0 -

Reset value

NA

31:8 -

-

-

AAC

SIC

STAC

I2ENC

Reserved. User software should not write ones to reserved bits. The value read from a reserved bit is not defined.

Assert acknowledge Clear bit.

I

2

C interrupt Clear bit.

Reserved. User software should not write ones to reserved bits. The value read from a reserved bit is not defined.

START flag Clear bit.

I

2

C interface Disable bit.

Reserved. User software should not write ones to reserved bits. The value read from a reserved bit is not defined.

Reserved. The value read from a reserved bit is not defined.

-

0

NA

0

0

NA

AAC

is the Assert Acknowledge Clear bit. Writing a 1 to this bit clears the AA bit in the

CONSET register. Writing 0 has no effect.

SIC

is the I

2

C Interrupt Clear bit. Writing a 1 to this bit clears the SI bit in the CONSET register. Writing 0 has no effect.

STAC

is the START flag Clear bit. Writing a 1 to this bit clears the STA bit in the CONSET register. Writing 0 has no effect.

I

2ENC

is the I

2

C Interface Disable bit. Writing a 1 to this bit clears the I2EN bit in the

CONSET register. Writing 0 has no effect.

15.7.7 I

2

C Monitor mode control register (I2C0MMCTRL - 0x4000 001C)

This register controls the Monitor mode which allows the I

2

C module to monitor traffic on the I

2

C bus without actually participating in traffic or interfering with the I

2

C bus.

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Chapter 15: LPC111x/LPC11Cxx I2C-bus controller

Table 228. I

2

C Monitor mode control register (I2C0MMCTRL - 0x4000 001C) bit description

Bit Symbol Value Description Reset value

0 MM_ENA

1 ENA_SCL

0

1

0

Monitor mode enable.

Monitor mode disabled.

The I

2

C module will enter monitor mode. In this mode the

SDA output will be forced high. This will prevent the I

2

C module from outputting data of any kind (including ACK) onto the I

2

C data bus.

Depending on the state of the ENA_SCL bit, the output may be also forced high, preventing the module from having control over the I

2

C clock line.

0

SCL output enable.

When this bit is cleared to ‘0’, the SCL output will be forced high when the module is in monitor mode. As described above, this will prevent the module from having any control over the I

2

C clock line.

0

2

31:3 -

MATCH_ALL

1

0

1

-

When this bit is set, the I

2

C module may exercise the same control over the clock line that it would in normal operation.

This means that, acting as a slave peripheral, the I

2

C module can “stretch” the clock line (hold it low) until it has had time to respond to an I

2

C interrupt.

[1]

Select interrupt register match.

When this bit is cleared, an interrupt will only be generated when a match occurs to one of the (up-to) four address registers described above. That is, the module will respond as a normal slave as far as address-recognition is concerned.

When this bit is set to ‘1’ and the I

2

C is in monitor mode, an interrupt will be generated on ANY address received. This will enable the part to monitor all traffic on the bus.

Reserved. The value read from reserved bits is not defined.

0

[1] When the ENA_SCL bit is cleared and the I

2

C no longer has the ability to stall the bus, interrupt response time becomes important. To give the part more time to respond to an I

2

C interrupt under these conditions, a

DATA _BUFFER register is used (

Section 15.7.9

) to hold received data for a full 9-bit word transmission

time.

Remark:

The ENA_SCL and MATCH_ALL bits have no effect if the MM_ENA is ‘0’ (i.e. if the module is NOT in monitor mode).

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15.7.7.1 Interrupt in Monitor mode

All interrupts will occur as normal when the module is in monitor mode. This means that the first interrupt will occur when an address-match is detected (any address received if the MATCH_ALL bit is set, otherwise an address matching one of the four address registers).

Subsequent to an address-match detection, interrupts will be generated after each data byte is received for a slave-write transfer, or after each byte that the module “thinks” it has transmitted for a slave-read transfer. In this second case, the data register will actually contain data transmitted by some other slave on the bus which was actually addressed by the master.

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Following all of these interrupts, the processor may read the data register to see what was actually transmitted on the bus.

15.7.7.2 Loss of arbitration in Monitor mode

In monitor mode, the I

2

C module will not be able to respond to a request for information by the bus master or issue an ACK). Some other slave on the bus will respond instead. This will most probably result in a lost-arbitration state as far as our module is concerned.

Software should be aware of the fact that the module is in monitor mode and should not respond to any loss of arbitration state that is detected. In addition, hardware may be designed into the module to block some/all loss of arbitration states from occurring if those state would either prevent a desired interrupt from occurring or cause an unwanted interrupt to occur. Whether any such hardware will be added is still to be determined.

15.7.8 I

2

C Slave Address registers (I2C0ADR[1, 2, 3] - 0x4000 00[20, 24, 28])

These registers are readable and writable and are only used when an I

2

C interface is set to slave mode. In master mode, this register has no effect. The LSB of the ADR register is the General Call bit. When this bit is set, the General Call address (0x00) is recognized.

If these registers contain 0x00, the I

2

C will not acknowledge any address on the bus. All

four registers will be cleared to this disabled state on reset (also see Table 223 ).

Table 229. I

2

C Slave Address registers (I2C0ADR[1, 2, 3]- 0x4000 00[20, 24, 28]) bit description

Bit Symbol Description Reset value

0

7:1

31:8 -

GC

Address

General Call enable bit.

The I

2

C device address for slave mode.

Reserved. The value read from a reserved bit is not defined.

0

0x00

0

15.7.9 I

2

C Data buffer register (I2C0DATA_BUFFER - 0x4000 002C)

In monitor mode, the I

2

C module may lose the ability to stretch the clock (stall the bus) if the ENA_SCL bit is not set. This means that the processor will have a limited amount of time to read the contents of the data received on the bus. If the processor reads the DAT shift register, as it ordinarily would, it could have only one bit-time to respond to the interrupt before the received data is overwritten by new data.

To give the processor more time to respond, a new 8-bit, read-only DATA_BUFFER register will be added. The contents of the 8 MSBs of the DAT shift register will be transferred to the DATA_BUFFER automatically after every nine bits (8 bits of data plus

ACK or NACK) has been received on the bus. This means that the processor will have nine bit transmission times to respond to the interrupt and read the data before it is overwritten.

The processor will still have the ability to read the DAT register directly, as usual, and the behavior of DAT will not be altered in any way.

Although the DATA_BUFFER register is primarily intended for use in monitor mode with the ENA_SCL bit = ‘0’, it will be available for reading at any time under any mode of operation.

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Chapter 15: LPC111x/LPC11Cxx I2C-bus controller

Table 230. I

2

C Data buffer register (I2C0DATA_BUFFER - 0x4000 002C) bit description

Bit

7:0

31:8 -

Symbol

Data

Description

This register holds contents of the 8 MSBs of the DAT shift register.

Reserved. The value read from a reserved bit is not defined.

Reset value

0

0

15.7.10 I

2

C Mask registers (I2C0MASK[0, 1, 2, 3] - 0x4000 00[30, 34, 38, 3C])

The four mask registers each contain seven active bits (7:1). Any bit in these registers which is set to ‘1’ will cause an automatic compare on the corresponding bit of the received address when it is compared to the ADDRn register associated with that mask register. In other words, bits in an ADDRn register which are masked are not taken into account in determining an address match.

On reset, all mask register bits are cleared to ‘0’.

The mask register has no effect on comparison to the General Call address (“0000000”).

Bits(31:8) and bit(0) of the mask registers are unused and should not be written to. These bits will always read back as zeros.

When an address-match interrupt occurs, the processor will have to read the data register

(DAT) to determine what the received address was that actually caused the match.

Table 231. I

2

C Mask registers (I2C0MASK[0, 1, 2, 3] - 0x4000 00[30, 34, 38, 3C]) bit description

Bit Symbol Description Reset value

0 0

7:1

31:8 -

MASK

Reserved. User software should not write ones to reserved bits. This bit reads always back as 0.

Mask bits.

Reserved. The value read from reserved bits is undefined.

0x00

0

15.8 I

2

C operating modes

In a given application, the I

2

C block may operate as a master, a slave, or both. In the slave mode, the I

2

C hardware looks for any one of its four slave addresses and the General Call address. If one of these addresses is detected, an interrupt is requested. If the processor wishes to become the bus master, the hardware waits until the bus is free before the master mode is entered so that a possible slave operation is not interrupted. If bus arbitration is lost in the master mode, the I

2

C block switches to the slave mode immediately and can detect its own slave address in the same serial transfer.

15.8.1 Master Transmitter mode

In this mode data is transmitted from master to slave. Before the master transmitter mode

can be entered, the CONSET register must be initialized as shown in Table 232 . I2EN

must be set to 1 to enable the I

2

C function. If the AA bit is 0, the I

2

C interface will not acknowledge any address when another device is master of the bus, so it can not enter slave mode. The STA, STO and SI bits must be 0. The SI Bit is cleared by writing 1 to the

SIC bit in the CONCLR register. THe STA bit should be cleared after writing the slave address.

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Table 232. I2C0CONSET and I2C1CONSET used to configure Master mode

Bit

Symbol

Value

-

-

7 6

I2EN

1

5

STA

0

4

STO

0

3

SI

0

2

AA

0 -

-

1

-

-

0

The first byte transmitted contains the slave address of the receiving device (7 bits) and the data direction bit. In this mode the data direction bit (R/W) should be 0 which means

Write. The first byte transmitted contains the slave address and Write bit. Data is transmitted 8 bits at a time. After each byte is transmitted, an acknowledge bit is received.

START and STOP conditions are output to indicate the beginning and the end of a serial transfer.

The I

2

C interface will enter master transmitter mode when software sets the STA bit. The

I

2

C logic will send the START condition as soon as the bus is free. After the START condition is transmitted, the SI bit is set, and the status code in the STAT register is 0x08.

This status code is used to vector to a state service routine which will load the slave address and Write bit to the DAT register, and then clear the SI bit. SI is cleared by writing a 1 to the SIC bit in the CONCLR register.

When the slave address and R/W bit have been transmitted and an acknowledgment bit has been received, the SI bit is set again, and the possible status codes now are 0x18,

0x20, or 0x38 for the master mode, or 0x68, 0x78, or 0xB0 if the slave mode was enabled

(by setting AA to 1). The appropriate actions to be taken for each of these status codes are shown in

Table 236 to

Table 241 .

S SLAVE ADDRESS RW=0 A DATA A DATA

A/A

P n bytes data transmitted

UM10398

User manual

from Master to Slave from Slave to Master

Fig 46. Format in the Master Transmitter mode

A = Acknowledge (SDA low)

A = Not acknowledge (SDA high)

S = START condition

P = STOP condition

15.8.2 Master Receiver mode

In the master receiver mode, data is received from a slave transmitter. The transfer is initiated in the same way as in the master transmitter mode. When the START condition has been transmitted, the interrupt service routine must load the slave address and the data direction bit to the I

2

C Data register (DAT), and then clear the SI bit. In this case, the data direction bit (R/W) should be 1 to indicate a read.

When the slave address and data direction bit have been transmitted and an acknowledge bit has been received, the SI bit is set, and the Status Register will show the status code. For master mode, the possible status codes are 0x40, 0x48, or 0x38. For slave mode, the possible status codes are 0x68, 0x78, or 0xB0. For details, refer to

Table 237 .

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S SLAVE ADDRESS RW=1 A DATA A DATA

A

P n bytes data received from Master to Slave from Slave to Master

A = Acknowledge (SDA low)

A = Not acknowledge (SDA high)

S = START condition

P = STOP condition

Fig 47. Format of Master Receiver mode

After a Repeated START condition, I

2

C may switch to the master transmitter mode.

S SLA R A DATA A DATA A Sr SLA W A DATA A P n bytes data transmitted

From master to slave

From slave to master

A = Acknowledge (SDA low)

A = Not acknowledge (SDA high)

S = START condition

P = STOP condition

SLA = Slave Address

Sr = Repeated START condition

Fig 48. A Master Receiver switches to Master Transmitter after sending Repeated START

15.8.3 Slave Receiver mode

In the slave receiver mode, data bytes are received from a master transmitter. To initialize the slave receiver mode, write any of the Slave Address registers (ADR0-3) and write the

I

2

C Control Set register (CONSET) as shown in Table 233

.

Table 233. I2C0CONSET and I2C1CONSET used to configure Slave mode

Bit 7 6 5 4 3 2 1

Symbol

Value -

I2EN

1

STA

0

STO

0

SI

0

AA

1 -

-

-

-

0

I2EN must be set to 1 to enable the I

2

C function. AA bit must be set to 1 to acknowledge its own slave address or the General Call address. The STA, STO and SI bits are set to 0.

After ADR and CONSET are initialized, the I

2

C interface waits until it is addressed by its own address or general address followed by the data direction bit. If the direction bit is 0

(W), it enters slave receiver mode. If the direction bit is 1 (R), it enters slave transmitter mode. After the address and direction bit have been received, the SI bit is set and a valid

status code can be read from the Status register (STAT). Refer to Table 240

for the status codes and actions.

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S SLAVE ADDRESS RW=0 A DATA A DATA

A/A

P/Sr n bytes data received from Master to Slave from Slave to Master

A = Acknowledge (SDA low)

A = Not acknowledge (SDA high)

S = START condition

P = STOP condition

Sr = Repeated START condition

Fig 49. Format of Slave Receiver mode

15.8.4 Slave Transmitter mode

The first byte is received and handled as in the slave receiver mode. However, in this mode, the direction bit will be 1, indicating a read operation. Serial data is transmitted via

SDA while the serial clock is input through SCL. START and STOP conditions are recognized as the beginning and end of a serial transfer. In a given application, I

2

C may operate as a master and as a slave. In the slave mode, the I

2

C hardware looks for its own slave address and the General Call address. If one of these addresses is detected, an interrupt is requested. When the microcontrollers wishes to become the bus master, the hardware waits until the bus is free before the master mode is entered so that a possible slave action is not interrupted. If bus arbitration is lost in the master mode, the I

2

C interface switches to the slave mode immediately and can detect its own slave address in the same serial transfer.

S SLAVE ADDRESS RW=1 A DATA A DATA

A

P n bytes data transmitted from Master to Slave from Slave to Master

A = Acknowledge (SDA low)

A = Not acknowledge (SDA high)

S = START condition

P = STOP condition

Fig 50. Format of Slave Transmitter mode

15.9 I

2

C implementation and operation

Figure 51

shows how the on-chip I

2

C-bus interface is implemented, and the following text describes the individual blocks.

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Chapter 15: LPC111x/LPC11Cxx I2C-bus controller

SDA

SCL

INPUT

FILTER

OUTPUT

STAGE

INPUT

FILTER

OUTPUT

STAGE status bus

STATUS

DECODER

8

ADDRESS REGISTERS

I2CnADDR0 to I2CnADDR3

MASK and COMPARE

SHIFT REGISTER

I2CnDAT

MATCHALL

I2CnMMCTRL[3]

MASK REGISTERS

I2CnMASK0 to I2CnMASK3

I2CnDATABUFFER

ACK

8

MONITOR MODE

REGISTER

I2CnMMCTRL

BIT COUNTER/

ARBITRATION and

SYNC LOGIC

PCLK

TIMING and

CONTROL

LOGIC interrupt

SERIAL CLOCK

GENERATOR

CONTROL REGISTER and

SCL DUTY CYLE REGISTERS

I2CnCONSET, I2CnCONCLR, I2CnSCLH, I2CnSCLL

16

STATUS REGISTER

I2CnSTAT

8

Fig 51. I

2

C serial interface block diagram

15.9.1 Input filters and output stages

Input signals are synchronized with the internal clock, and spikes shorter than three clocks are filtered out.

The output for I

2

C is a special pad designed to conform to the I

2

C specification.

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Chapter 15: LPC111x/LPC11Cxx I2C-bus controller

15.9.2 Address Registers, ADDR0 to ADDR3

These registers may be loaded with the 7-bit slave address (7 most significant bits) to which the I

2

C block will respond when programmed as a slave transmitter or receiver. The

LSB (GC) is used to enable General Call address (0x00) recognition. When multiple slave addresses are enabled, the actual address received may be read from the DAT register at the state where the own slave address has been received.

15.9.3 Address mask registers, MASK0 to MASK3

The four mask registers each contain seven active bits (7:1). Any bit in these registers which is set to ‘1’ will cause an automatic compare on the corresponding bit of the received address when it is compared to the ADDRn register associated with that mask register. In other words, bits in an ADDRn register which are masked are not taken into account in determining an address match.

When an address-match interrupt occurs, the processor will have to read the data register

(DAT) to determine what the received address was that actually caused the match.

15.9.4 Comparator

The comparator compares the received 7-bit slave address with its own slave address (7 most significant bits in ADR). It also compares the first received 8-bit byte with the General

Call address (0x00). If an equality is found, the appropriate status bits are set and an interrupt is requested.

15.9.5 Shift register, DAT

This 8-bit register contains a byte of serial data to be transmitted or a byte which has just been received. Data in DAT is always shifted from right to left; the first bit to be transmitted is the MSB (bit 7) and, after a byte has been received, the first bit of received data is located at the MSB of DAT. While data is being shifted out, data on the bus is simultaneously being shifted in; DAT always contains the last byte present on the bus.

Thus, in the event of lost arbitration, the transition from master transmitter to slave receiver is made with the correct data in DAT.

15.9.6 Arbitration and synchronization logic

In the master transmitter mode, the arbitration logic checks that every transmitted logic 1 actually appears as a logic 1 on the I

2

C-bus. If another device on the bus overrules a logic

1 and pulls the SDA line low, arbitration is lost, and the I

2

C block immediately changes from master transmitter to slave receiver. The I

2

C block will continue to output clock pulses (on SCL) until transmission of the current serial byte is complete.

Arbitration may also be lost in the master receiver mode. Loss of arbitration in this mode can only occur while the I

2

C block is returning a “not acknowledge: (logic 1) to the bus.

Arbitration is lost when another device on the bus pulls this signal low. Since this can occur only at the end of a serial byte, the I

2

C block generates no further clock pulses.

Figure 52

shows the arbitration procedure.

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Chapter 15: LPC111x/LPC11Cxx I2C-bus controller

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(1) (1) (2) (3)

SDA line

SCL line

1 2 3 4 8 9

ACK

(1) Another device transmits serial data.

(2) Another device overrules a logic (dotted line) transmitted this I

2

C master by pulling the SDA line low. Arbitration is lost, and this I

2

C enters Slave Receiver mode.

(3) This I

2

C is in Slave Receiver mode but still generates clock pulses until the current byte has been transmitted. This I

2

C will not generate clock pulses for the next byte. Data on SDA originates from the new master once it has won arbitration.

Fig 52. Arbitration procedure

The synchronization logic will synchronize the serial clock generator with the clock pulses on the SCL line from another device. If two or more master devices generate clock pulses, the “mark” duration is determined by the device that generates the shortest “marks,” and the “space” duration is determined by the device that generates the longest “spaces”.

Figure 53

shows the synchronization procedure.

SDA line

(1) (3) (1)

SCL line high period low period

(2)

(1) Another device pulls the SCL line low before this I

2

C has timed a complete high time. The other device effectively determines the (shorter) HIGH period.

(2) Another device continues to pull the SCL line low after this I

2

C has timed a complete low time and released SCL. The I

2

C clock generator is forced to wait until SCL goes HIGH. The other device effectively determines the (longer) LOW period.

(3) The SCL line is released , and the clock generator begins timing the HIGH time.

Fig 53. Serial clock synchronization

A slave may stretch the space duration to slow down the bus master. The space duration may also be stretched for handshaking purposes. This can be done after each bit or after a complete byte transfer. the I

2

C block will stretch the SCL space duration after a byte has been transmitted or received and the acknowledge bit has been transferred. The serial interrupt flag (SI) is set, and the stretching continues until the serial interrupt flag is cleared.

15.9.7 Serial clock generator

This programmable clock pulse generator provides the SCL clock pulses when the I

2

C block is in the master transmitter or master receiver mode. It is switched off when the I

2

C block is in slave mode. The I

2

C output clock frequency and duty cycle is programmable

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Chapter 15: LPC111x/LPC11Cxx I2C-bus controller

via the I

2

C Clock Control Registers. See the description of the I2CSCLL and I2CSCLH registers for details. The output clock pulses have a duty cycle as programmed unless the bus is synchronizing with other SCL clock sources as described above.

15.9.8 Timing and control

The timing and control logic generates the timing and control signals for serial byte handling. This logic block provides the shift pulses for DAT, enables the comparator, generates and detects START and STOP conditions, receives and transmits acknowledge bits, controls the master and slave modes, contains interrupt request logic, and monitors the I

2

C-bus status.

15.9.9 Control register, CONSET and CONCLR

The I

2

C control register contains bits used to control the following I

2

C block functions: start and restart of a serial transfer, termination of a serial transfer, bit rate, address recognition, and acknowledgment.

The contents of the I

2

C control register may be read as CONSET. Writing to CONSET will set bits in the I

2

C control register that correspond to ones in the value written. Conversely, writing to CONCLR will clear bits in the I

2

C control register that correspond to ones in the value written.

15.9.10 Status decoder and status register

The status decoder takes all of the internal status bits and compresses them into a 5-bit code. This code is unique for each I

2

C-bus status. The 5-bit code may be used to generate vector addresses for fast processing of the various service routines. Each service routine processes a particular bus status. There are 26 possible bus states if all four modes of the I

2

C block are used. The 5-bit status code is latched into the five most significant bits of the status register when the serial interrupt flag is set (by hardware) and remains stable until the interrupt flag is cleared by software. The three least significant bits of the status register are always zero. If the status code is used as a vector to service routines, then the routines are displaced by eight address locations. Eight bytes of code is sufficient for most of the service routines (see the software example in this section).

15.10 Details of I

2

C operating modes

The four operating modes are:

Master Transmitter

Master Receiver

Slave Receiver

Slave Transmitter

Data transfers in each mode of operation are shown in

Figure 54 ,

Figure 55 ,

Figure 56

,

Figure 57

, and

Figure 58 .

Table 234

lists abbreviations used in these figures when describing the I

2

C operating modes.

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Chapter 15: LPC111x/LPC11Cxx I2C-bus controller

Table 234. Abbreviations used to describe an I

2

C operation

Abbreviation

S

Explanation

START Condition

SLA

R

W

A

7-bit slave address

Read bit (HIGH level at SDA)

Write bit (LOW level at SDA)

Acknowledge bit (LOW level at SDA)

A

Data

P

Not acknowledge bit (HIGH level at SDA)

8-bit data byte

STOP condition

In Figure 54 to

Figure 58 , circles are used to indicate when the serial interrupt flag is set.

The numbers in the circles show the status code held in the STAT register. At these points, a service routine must be executed to continue or complete the serial transfer. These service routines are not critical since the serial transfer is suspended until the serial interrupt flag is cleared by software.

When a serial interrupt routine is entered, the status code in STAT is used to branch to the appropriate service routine. For each status code, the required software action and details of the following serial transfer are given in tables from

Table 236

to Table 242 .

15.10.1 Master Transmitter mode

In the master transmitter mode, a number of data bytes are transmitted to a slave receiver

(see Figure 54

). Before the master transmitter mode can be entered, I2CON must be initialized as follows:

Table 235. I2C0CONSET used to initialize Master Transmitter mode

Bit

Symbol

Value

-

-

7 6

I2EN

1

5

STA

0

4

STO

0

3

SI

0

2

AA x -

-

1

-

-

0

The I

2

C rate must also be configured in the SCLL and SCLH registers. I2EN must be set to logic 1 to enable the I

2

C block. If the AA bit is reset, the I

2

C block will not acknowledge its own slave address or the General Call address in the event of another device becoming master of the bus. In other words, if AA is reset, the I

2

C interface cannot enter slave mode. STA, STO, and SI must be reset.

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Chapter 15: LPC111x/LPC11Cxx I2C-bus controller

The master transmitter mode may now be entered by setting the STA bit. The I

2

C logic will now test the I

2

C-bus and generate a START condition as soon as the bus becomes free.

When a START condition is transmitted, the serial interrupt flag (SI) is set, and the status code in the status register (STAT) will be 0x08. This status code is used by the interrupt service routine to enter the appropriate state service routine that loads DAT with the slave address and the data direction bit (SLA+W). The SI bit in CON must then be reset before the serial transfer can continue.

When the slave address and the direction bit have been transmitted and an acknowledgment bit has been received, the serial interrupt flag (SI) is set again, and a number of status codes in STAT are possible. There are 0x18, 0x20, or 0x38 for the master mode and also 0x68, 0x78, or 0xB0 if the slave mode was enabled (AA = logic 1).

The appropriate action to be taken for each of these status codes is detailed in Table 236

.

After a Repeated START condition (state 0x10). The I

2

C block may switch to the master receiver mode by loading DAT with SLA+R).

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Chapter 15: LPC111x/LPC11Cxx I2C-bus controller

Table 236. Master Transmitter mode

Status

Code

)

(I2CSTAT

Status of the I

2

C-bus and hardware

Application software response

To/From DAT To CON

STA STO SI

0x08

0x10

0x18

A START condition has been transmitted.

A Repeated START condition has been transmitted.

Load SLA+W; clear STA

Load SLA+W or

Load SLA+R;

Clear STA

Load data byte or

X

X

X

0

0

0

0

0

0

0

0

0 SLA+W has been transmitted; ACK has been received.

No DAT action or

No DAT action or

1

0

0

1

0

0

0x20

0x28

0x30

0x38

SLA+W has been transmitted; NOT ACK has been received.

Data byte in DAT has been transmitted;

ACK has been received.

Data byte in DAT has been transmitted;

NOT ACK has been received.

Arbitration lost in

SLA+R/W or Data bytes.

No DAT action

Load data byte or

No DAT action or

No DAT action or

No DAT action

Load data byte or

No DAT action or

No DAT action or

No DAT action

Load data byte or

No DAT action or

No DAT action or

No DAT action

No DAT action or

No DAT action

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

1

0

0

1

1

0

0

1

1

0

0

1

1

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

Next action taken by I

2

C hardware

X

X

X

X

X

X

X

X

X

X

AA

X

X

X

X

X

X

X

X

X

X

X

SLA+W will be transmitted; ACK bit will be received.

As above.

SLA+R will be transmitted; the I

2

C block will be switched to MST/REC mode.

Data byte will be transmitted; ACK bit will be received.

Repeated START will be transmitted.

STOP condition will be transmitted; STO flag will be reset.

STOP condition followed by a START condition will be transmitted; STO flag will be reset.

Data byte will be transmitted; ACK bit will be received.

Repeated START will be transmitted.

STOP condition will be transmitted; STO flag will be reset.

STOP condition followed by a START condition will be transmitted; STO flag will be reset.

Data byte will be transmitted; ACK bit will be received.

Repeated START will be transmitted.

STOP condition will be transmitted; STO flag will be reset.

STOP condition followed by a START condition will be transmitted; STO flag will be reset.

Data byte will be transmitted; ACK bit will be received.

Repeated START will be transmitted.

STOP condition will be transmitted; STO flag will be reset.

STOP condition followed by a START condition will be transmitted; STO flag will be reset.

I

2

C-bus will be released; not addressed slave will be entered.

A START condition will be transmitted when the bus becomes free.

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MT successful transmission to a Slave

Receiver

S

08H

SLA

W A

18H next transfer started with a

Repeated Start condition

Not

Acknowledge received after the Slave address

A

20H

P

Not

Acknowledge received after a

Data byte

DATA A P

28H

S

10H

SLA W

R

A P

30H arbitration lost in Slave address or

Data byte

A OR A other Master continues

38H

A OR A other Master continues

38H arbitration lost and addressed as

Slave

A other Master continues

68H 78H B0H to corresponding states in Slave mode from Master to Slave

DATA from Slave to Master any number of data bytes and their associated Acknowledge bits n this number (contained in I2STA) corresponds to a defined state of the

I

2

C bus

Fig 54. Format and states in the Master Transmitter mode

to Master receive mode, entry

= MR

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Chapter 15: LPC111x/LPC11Cxx I2C-bus controller

15.10.2 Master Receiver mode

In the master receiver mode, a number of data bytes are received from a slave transmitter

(see Figure 55

). The transfer is initialized as in the master transmitter mode. When the

START condition has been transmitted, the interrupt service routine must load DAT with the 7-bit slave address and the data direction bit (SLA+R). The SI bit in CON must then be cleared before the serial transfer can continue.

When the slave address and the data direction bit have been transmitted and an acknowledgment bit has been received, the serial interrupt flag (SI) is set again, and a number of status codes in STAT are possible. These are 0x40, 0x48, or 0x38 for the master mode and also 0x68, 0x78, or 0xB0 if the slave mode was enabled (AA = 1). The appropriate action to be taken for each of these status codes is detailed in

Table 237 . After

a Repeated START condition (state 0x10), the I

2

C block may switch to the master transmitter mode by loading DAT with SLA+W.

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Chapter 15: LPC111x/LPC11Cxx I2C-bus controller

Table 237. Master Receiver mode

Status

Code

(STAT)

Status of the I

2

C-bus and hardware

Application software response

To/From DAT To CON

STA STO SI

0x08 Load SLA+R X 0 0

0x10

A START condition has been transmitted.

A Repeated START condition has been transmitted.

Load SLA+R or

Load SLA+W

X

X

0

0

0

0

0x38 0 0 0 Arbitration lost in NOT

ACK bit.

No DAT action or

No DAT action 1 0 0

0x40

0x48

0x50

0x58

SLA+R has been transmitted; ACK has been received.

SLA+R has been transmitted; NOT ACK has been received.

Data byte has been received; ACK has been returned.

Data byte has been received; NOT ACK has been returned.

No DAT action or

No DAT action

No DAT action or

No DAT action or

No DAT action

Read data byte or

Read data byte

Read data byte or

Read data byte or

Read data byte

0

0

1

0

1

0

0

1

0

1

0

0

0

1

1

0

0

0

1

1

0

0

0

0

0

0

0

0

0

0

Next action taken by I

2

C hardware

X

X

AA

X

X

X

0

1

X

X

X

0

1

X

X

X

SLA+R will be transmitted; ACK bit will be received.

As above.

SLA+W will be transmitted; the I

2

C block will be switched to MST/TRX mode.

I

2

C-bus will be released; the I

2

C block will enter slave mode.

A START condition will be transmitted when the bus becomes free.

Data byte will be received; NOT ACK bit will be returned.

Data byte will be received; ACK bit will be returned.

Repeated START condition will be transmitted.

STOP condition will be transmitted; STO flag will be reset.

STOP condition followed by a START condition will be transmitted; STO flag will be reset.

Data byte will be received; NOT ACK bit will be returned.

Data byte will be received; ACK bit will be returned.

Repeated START condition will be transmitted.

STOP condition will be transmitted; STO flag will be reset.

STOP condition followed by a START condition will be transmitted; STO flag will be reset.

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MR successful transmission to a Slave transmitter

S

08H next transfer started with a

Repeated Start condition

SLA

Not Acknowledge received after the

Slave address

R A DATA A DATA

A

P

40H

A

P

50H 58H

S

10H

SLA R

W

48H arbitration lost in

Slave address or

Acknowledge bit

A OR A other Master continues

38H

A

38H other Master continues arbitration lost and addressed as Slave

A other Master continues

68H 78H B0H to corresponding states in Slave mode from Master to Slave from Slave to Master

DATA n

A any number of data bytes and their associated

Acknowledge bits this number (contained in I2STA) corresponds to a defined state of the I

2

C bus

Fig 55. Format and states in the Master Receiver mode

to Master transmit mode, entry

= MT

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Chapter 15: LPC111x/LPC11Cxx I2C-bus controller

15.10.3 Slave Receiver mode

In the slave receiver mode, a number of data bytes are received from a master transmitter

(see Figure 56

). To initiate the slave receiver mode, ADR and CON must be loaded as follows:

Table 238. I2C0ADR and I2C1ADR usage in Slave Receiver mode

Bit

Symbol

7 6 5 4 3

own slave 7-bit address

2 1 0

GC

The upper 7 bits are the address to which the I

2

C block will respond when addressed by a master. If the LSB (GC) is set, the I

2

C block will respond to the General Call address

(0x00); otherwise it ignores the General Call address.

Table 239. I2C0CONSET and I2C1CONSET used to initialize Slave Receiver mode

Bit 7 6 5 4 3 2 1

Symbol

Value -

I2EN

1

STA

0

STO

0

SI

0

AA

1 -

-

-

-

0

The I

2

C-bus rate settings do not affect the I

2

C block in the slave mode. I2EN must be set to logic 1 to enable the I

2

C block. The AA bit must be set to enable the I

2

C block to acknowledge its own slave address or the General Call address. STA, STO, and SI must be reset.

When ADR and CON have been initialized, the I

2

C block waits until it is addressed by its own slave address followed by the data direction bit which must be “0” (W) for the I

2

C block to operate in the slave receiver mode. After its own slave address and the W bit have been received, the serial interrupt flag (SI) is set and a valid status code can be read from STAT. This status code is used to vector to a state service routine. The appropriate

action to be taken for each of these status codes is detailed in Table 240

. The slave receiver mode may also be entered if arbitration is lost while the I

2

C block is in the master mode (see status 0x68 and 0x78).

If the AA bit is reset during a transfer, the I

2

C block will return a not acknowledge (logic 1) to SDA after the next received data byte. While AA is reset, the I

2

C block does not respond to its own slave address or a General Call address. However, the I

2

C-bus is still monitored and address recognition may be resumed at any time by setting AA. This means that the AA bit may be used to temporarily isolate the I

2

C block from the I

2

C-bus.

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Chapter 15: LPC111x/LPC11Cxx I2C-bus controller

Table 240. Slave Receiver mode

Status

Code

(STAT)

Status of the I

2

C-bus and hardware

Application software response

To/From DAT To CON

STA STO SI

0x60 Own SLA+W has been received; ACK has been returned.

No DAT action or

No DAT action

X

X

0

0

0

0

0x68

0x70

0x78

0x80

0x88

0x90

Arbitration lost in

SLA+R/W as master;

Own SLA+W has been received, ACK returned.

General call address

(0x00) has been received; ACK has been returned.

Arbitration lost in

SLA+R/W as master;

General call address has been received,

ACK has been returned.

No DAT action or

No DAT action

Previously addressed with own SLV address; DATA has been received; ACK has been returned.

Read data byte or

Read data byte

Previously addressed with own SLA; DATA byte has been received; NOT ACK has been returned.

Read data byte or

Read data byte or

X

X

X

X

0

0

Previously addressed with General Call;

DATA byte has been received; ACK has been returned.

No DAT action or

No DAT action

No DAT action or

No DAT action

Read data byte or

Read data byte

Read data byte or

Read data byte

X

X

X

X

1

1

X

X

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

AA

0

1

0

1

Data byte will be received and NOT ACK will be returned.

Data byte will be received and ACK will be returned.

Data byte will be received and NOT ACK will be returned.

Data byte will be received and ACK will be returned.

0

1

0

1

Data byte will be received and NOT ACK will be returned.

Data byte will be received and ACK will be returned.

Data byte will be received and NOT ACK will be returned.

Data byte will be received and ACK will be returned.

0

1

0

1

0

1

0

1

Next action taken by I

2

C hardware

Data byte will be received and NOT ACK will be returned.

Data byte will be received and ACK will be returned.

Switched to not addressed SLV mode; no recognition of own SLA or General call address.

Switched to not addressed SLV mode;

Own SLA will be recognized; General call address will be recognized if

ADR[0] = logic 1.

Switched to not addressed SLV mode; no recognition of own SLA or General call address. A START condition will be transmitted when the bus becomes free.

Switched to not addressed SLV mode;

Own SLA will be recognized; General call address will be recognized if

ADR[0] = logic 1. A START condition will be transmitted when the bus becomes free.

Data byte will be received and NOT ACK will be returned.

Data byte will be received and ACK will be returned.

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Chapter 15: LPC111x/LPC11Cxx I2C-bus controller

Table 240. Slave Receiver mode

…continued

Status

Code

(STAT)

Status of the I

2

C-bus and hardware

Application software response

To/From DAT To CON

STA STO SI

0x98 0 0 0 Previously addressed with General Call;

DATA byte has been received; NOT ACK has been returned.

Read data byte or

Read data byte or 0 0 0

0xA0 A STOP condition or

Repeated START condition has been received while still addressed as

SLV/REC or

SLV/TRX.

Read data byte or

Read data byte

No STDAT action or

No STDAT action or

No STDAT action or

No STDAT action

1

1

0

0

1

1

0

0

0

0

0

0

0

0

0

0

0

0

Next action taken by I

2

C hardware

AA

0

1

0

1

0

1

0

1

Switched to not addressed SLV mode; no recognition of own SLA or General call address.

Switched to not addressed SLV mode;

Own SLA will be recognized; General call address will be recognized if

ADR[0] = logic 1.

Switched to not addressed SLV mode; no recognition of own SLA or General call address. A START condition will be transmitted when the bus becomes free.

Switched to not addressed SLV mode;

Own SLA will be recognized; General call address will be recognized if

ADR[0] = logic 1. A START condition will be transmitted when the bus becomes free.

Switched to not addressed SLV mode; no recognition of own SLA or General call address.

Switched to not addressed SLV mode;

Own SLA will be recognized; General call address will be recognized if

ADR[0] = logic 1.

Switched to not addressed SLV mode; no recognition of own SLA or General call address. A START condition will be transmitted when the bus becomes free.

Switched to not addressed SLV mode;

Own SLA will be recognized; General call address will be recognized if

ADR[0] = logic 1. A START condition will be transmitted when the bus becomes free.

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Chapter 15: LPC111x/LPC11Cxx I2C-bus controller

reception of the own

Slave address and one or more Data bytes all are acknowledged

S SLA W A DATA

60H

A DATA

80H

A P OR S

80H A0H last data byte received is Not acknowledged arbitration lost as

Master and addressed as Slave reception of the

General Call address and one or more Data bytes

A

P OR S

88H

A

68H

GENERAL CALL A DATA

70h

A DATA

90h

A

P OR S

90h A0H last data byte is Not acknowledged arbitration lost as

Master and addressed as Slave by General

Call

A

78h from Master to Slave from Slave to Master

DATA A any number of data bytes and their associated Acknowledge bits n this number (contained in I2STA) corresponds to a defined state of the I

2

C bus

Fig 56. Format and states in the Slave Receiver mode

A

P OR S

98h

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Chapter 15: LPC111x/LPC11Cxx I2C-bus controller

15.10.4 Slave Transmitter mode

In the slave transmitter mode, a number of data bytes are transmitted to a master receiver

(see Figure 57

). Data transfer is initialized as in the slave receiver mode. When ADR and

CON have been initialized, the I

2

C block waits until it is addressed by its own slave address followed by the data direction bit which must be “1” (R) for the I

2

C block to operate in the slave transmitter mode. After its own slave address and the R bit have been received, the serial interrupt flag (SI) is set and a valid status code can be read from STAT.

This status code is used to vector to a state service routine, and the appropriate action to

be taken for each of these status codes is detailed in Table 241

. The slave transmitter mode may also be entered if arbitration is lost while the I

2

C block is in the master mode

(see state 0xB0).

If the AA bit is reset during a transfer, the I

2

C block will transmit the last byte of the transfer and enter state 0xC0 or 0xC8. The I

2

C block is switched to the not addressed slave mode and will ignore the master receiver if it continues the transfer. Thus the master receiver receives all 1s as serial data. While AA is reset, the I

2

C block does not respond to its own slave address or a General Call address. However, the I

2

C-bus is still monitored, and address recognition may be resumed at any time by setting AA. This means that the AA bit may be used to temporarily isolate the I

2

C block from the I

2

C-bus.

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Table 241. Slave Transmitter mode

Status

Code

(STAT)

Status of the I

2

C-bus and hardware

Application software response

To/From DAT To CON

STA STO SI

0xA8 Own SLA+R has been received; ACK has been returned.

Load data byte or

Load data byte

X

X

0

0

0

0

0xB0

0xB8

0xC0

0xC8

Arbitration lost in

SLA+R/W as master;

Own SLA+R has been received, ACK has been returned.

Load data byte or

Load data byte

Data byte in DAT has been transmitted;

ACK has been received.

Load data byte or

Load data byte

Data byte in DAT has been transmitted;

NOT ACK has been received.

Last data byte in DAT has been transmitted

(AA = 0); ACK has been received.

No DAT action or

No DAT action or

No DAT action or

No DAT action

No DAT action or

No DAT action or

No DAT action or

No DAT action

X

X

X

X

0

0

1

1

0

0

1

1

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

Next action taken by I

2

C hardware

AA

0

1

0

1

Last data byte will be transmitted and

ACK bit will be received.

Data byte will be transmitted; ACK will be received.

Last data byte will be transmitted and

ACK bit will be received.

Data byte will be transmitted; ACK bit will be received.

0

1

0

1

0

1

0

1

0

01

Last data byte will be transmitted and

ACK bit will be received.

Data byte will be transmitted; ACK bit will be received.

Switched to not addressed SLV mode; no recognition of own SLA or General call address.

Switched to not addressed SLV mode;

Own SLA will be recognized; General call address will be recognized if

ADR[0] = logic 1.

Switched to not addressed SLV mode; no recognition of own SLA or General call address. A START condition will be transmitted when the bus becomes free.

Switched to not addressed SLV mode;

Own SLA will be recognized; General call address will be recognized if

ADR[0] = logic 1. A START condition will be transmitted when the bus becomes free.

Switched to not addressed SLV mode; no recognition of own SLA or General call address.

Switched to not addressed SLV mode;

Own SLA will be recognized; General call address will be recognized if

ADR[0] = logic 1.

Switched to not addressed SLV mode; no recognition of own SLA or General call address. A START condition will be transmitted when the bus becomes free.

Switched to not addressed SLV mode;

Own SLA will be recognized; General call address will be recognized if

ADR.0 = logic 1. A START condition will be transmitted when the bus becomes free.

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reception of the own

Slave address and one or more Data bytes all are acknowledged

S SLA R A DATA A DATA

A

P OR S

A8H B8H C0H arbitration lost as

Master and addressed as Slave last data byte transmitted. Switched to Not Addressed

Slave (AA bit in

I2CON = “0”)

A

B0H

A ALL ONES P OR S

C8H from Master to Slave from Slave to Master

DATA A any number of data bytes and their associated

Acknowledge bits n this number (contained in I2STA) corresponds to a defined state of the I

2

C bus

Fig 57. Format and states in the Slave Transmitter mode

15.10.5 Miscellaneous states

There are two STAT codes that do not correspond to a defined I

2

C hardware state (see

Table 242 ). These are discussed below.

15.10.5.1 STAT = 0xF8

This status code indicates that no relevant information is available because the serial interrupt flag, SI, is not yet set. This occurs between other states and when the I

2

C block is not involved in a serial transfer.

15.10.5.2 STAT = 0x00

This status code indicates that a bus error has occurred during an I

2

C serial transfer. A bus error is caused when a START or STOP condition occurs at an illegal position in the format frame. Examples of such illegal positions are during the serial transfer of an address byte, a data byte, or an acknowledge bit. A bus error may also be caused when external interference disturbs the internal I

2

C block signals. When a bus error occurs, SI is set. To recover from a bus error, the STO flag must be set and SI must be cleared. This

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causes the I

2

C block to enter the “not addressed” slave mode (a defined state) and to clear the STO flag (no other bits in CON are affected). The SDA and SCL lines are released (a STOP condition is not transmitted).

Table 242. Miscellaneous States

Status

Code

(STAT)

Status of the I

2

C-bus and hardware

Application software response

To/From DAT To CON

0xF8

STA STO SI

No CON action

AA

0x00

No relevant state information available;

SI = 0.

No DAT action

Bus error during MST or selected slave modes, due to an illegal START or

STOP condition. State

0x00 can also occur when interference causes the I

2

C block to enter an undefined state.

No DAT action 0 1 0 X

Next action taken by I

2

C hardware

Wait or proceed current transfer.

Only the internal hardware is affected in the MST or addressed SLV modes. In all cases, the bus is released and the I

2

C block is switched to the not addressed

SLV mode. STO is reset.

15.10.6 Some special cases

The I

2

C hardware has facilities to handle the following special cases that may occur during a serial transfer:

Simultaneous Repeated START conditions from two masters

Data transfer after loss of arbitration

Forced access to the I

2

C-bus

I

2

C-bus obstructed by a LOW level on SCL or SDA

Bus error

15.10.6.1 Simultaneous Repeated START conditions from two masters

A Repeated START condition may be generated in the master transmitter or master receiver modes. A special case occurs if another master simultaneously generates a

Repeated START condition (see Figure 58 ). Until this occurs, arbitration is not lost by

either master since they were both transmitting the same data.

If the I

2

C hardware detects a Repeated START condition on the I

2

C-bus before generating a Repeated START condition itself, it will release the bus, and no interrupt request is generated. If another master frees the bus by generating a STOP condition, the I

2

C block will transmit a normal START condition (state 0x08), and a retry of the total serial data transfer can commence.

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S

08H

SLA W A

18H

DATA A S

28H

OTHER MASTER

CONTINUES

P S SLA

08H other Master sends repeated START earlier retry

Fig 58. Simultaneous Repeated START conditions from two masters

15.10.6.2 Data transfer after loss of arbitration

Arbitration may be lost in the master transmitter and master receiver modes (see

Figure 52

). Loss of arbitration is indicated by the following states in STAT; 0x38, 0x68,

0x78, and 0xB0 (see Figure 54 and

Figure 55

).

If the STA flag in CON is set by the routines which service these states, then, if the bus is free again, a START condition (state 0x08) is transmitted without intervention by the CPU, and a retry of the total serial transfer can commence.

15.10.6.3 Forced access to the I

2

C-bus

In some applications, it may be possible for an uncontrolled source to cause a bus hang-up. In such situations, the problem may be caused by interference, temporary interruption of the bus or a temporary short-circuit between SDA and SCL.

If an uncontrolled source generates a superfluous START or masks a STOP condition, then the I

2

C-bus stays busy indefinitely. If the STA flag is set and bus access is not obtained within a reasonable amount of time, then a forced access to the I

2

C-bus is possible. This is achieved by setting the STO flag while the STA flag is still set. No STOP condition is transmitted. The I

2

C hardware behaves as if a STOP condition was received and is able to transmit a START condition. The STO flag is cleared by hardware (see

Figure 59

).

time limit

STA flag

STO flag

SDA line

SCL line start condition

Fig 59. Forced access to a busy I

2

C-bus

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15.10.6.4 I

2

C-bus obstructed by a LOW level on SCL or SDA

An I

2

C-bus hang-up can occur if either the SDA or SCL line is held LOW by any device on the bus. If the SCL line is obstructed (pulled LOW) by a device on the bus, no further serial transfer is possible, and the problem must be resolved by the device that is pulling the

SCL bus line LOW.

Typically, the SDA line may be obstructed by another device on the bus that has become out of synchronization with the current bus master by either missing a clock, or by sensing a noise pulse as a clock. In this case, the problem can be solved by transmitting additional clock pulses on the SCL line (see

Figure 60 ). The I

2

C interface does not include a dedicated time-out timer to detect an obstructed bus, but this can be implemented using another timer in the system. When detected, software can force clocks (up to 9 may be required) on SCL until SDA is released by the offending device. At that point, the slave may still be out of synchronization, so a START should be generated to insure that all I

2

C peripherals are synchronized.

STA flag

(2) (3)

(1) (1)

SDA line

SCL line start condition

(1) Unsuccessful attempt to send a START condition.

(2) SDA line is released.

(3) Successful attempt to send a START condition. State 08H is entered.

Fig 60. Recovering from a bus obstruction caused by a LOW level on SDA

15.10.6.5 Bus error

A bus error occurs when a START or STOP condition is detected at an illegal position in the format frame. Examples of illegal positions are during the serial transfer of an address byte, a data bit, or an acknowledge bit.

The I

2

C hardware only reacts to a bus error when it is involved in a serial transfer either as a master or an addressed slave. When a bus error is detected, the I

2

C block immediately switches to the not addressed slave mode, releases the SDA and SCL lines, sets the interrupt flag, and loads the status register with 0x00. This status code may be used to vector to a state service routine which either attempts the aborted serial transfer again or simply recovers from the error condition as shown in

Table 242

.

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15.10.7 I

2

C state service routines

This section provides examples of operations that must be performed by various I

2

C state service routines. This includes:

Initialization of the I

2

C block after a Reset.

I

2

C Interrupt Service

The 26 state service routines providing support for all four I

2

C operating modes.

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15.10.8 Initialization

In the initialization example, the I

2

C block is enabled for both master and slave modes.

For each mode, a buffer is used for transmission and reception. The initialization routine performs the following functions:

ADR is loaded with the part’s own slave address and the General Call bit (GC)

The I

2

C interrupt enable and interrupt priority bits are set

The slave mode is enabled by simultaneously setting the I2EN and AA bits in CON and the serial clock frequency (for master modes) is defined by is defined by loading the

SCLH and SCLL registers

. The master routines must be started in the main program.

The I

2

C hardware now begins checking the I

2

C-bus for its own slave address and General

Call. If the General Call or the own slave address is detected, an interrupt is requested and STAT is loaded with the appropriate state information.

15.10.9 I

2

C interrupt service

When the I

2

C interrupt is entered, STAT contains a status code which identifies one of the

26 state services to be executed.

15.10.10 The state service routines

Each state routine is part of the I

2

C interrupt routine and handles one of the 26 states.

15.10.11 Adapting state services to an application

The state service examples show the typical actions that must be performed in response to the 26 I

2

C state codes. If one or more of the four I

2

C operating modes are not used, the associated state services can be omitted, as long as care is taken that the those states can never occur.

In an application, it may be desirable to implement some kind of time-out during I

2

C operations, in order to trap an inoperative bus or a lost service routine.

15.11 Software example

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15.11.1 Initialization routine

Example to initialize I

2

C Interface as a Slave and/or Master.

1. Load ADR with own Slave Address, enable General Call recognition if needed.

2. Enable I

2

C interrupt.

3. Write 0x44 to CONSET to set the I2EN and AA bits, enabling Slave functions. For

Master only functions, write 0x40 to CONSET.

15.11.2 Start Master Transmit function

Begin a Master Transmit operation by setting up the buffer, pointer, and data count, then initiating a START.

1. Initialize Master data counter.

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2. Set up the Slave Address to which data will be transmitted, and add the Write bit.

3. Write 0x20 to CONSET to set the STA bit.

4. Set up data to be transmitted in Master Transmit buffer.

5. Initialize the Master data counter to match the length of the message being sent.

6. Exit

15.11.3 Start Master Receive function

Begin a Master Receive operation by setting up the buffer, pointer, and data count, then initiating a START.

1. Initialize Master data counter.

2. Set up the Slave Address to which data will be transmitted, and add the Read bit.

3. Write 0x20 to CONSET to set the STA bit.

4. Set up the Master Receive buffer.

5. Initialize the Master data counter to match the length of the message to be received.

6. Exit

15.11.4 I

2

C interrupt routine

Determine the I

2

C state and which state routine will be used to handle it.

1. Read the I

2

C status from STA.

2. Use the status value to branch to one of 26 possible state routines.

15.11.5 Non mode specific states

15.11.5.1 State: 0x00

Bus Error. Enter not addressed Slave mode and release bus.

1. Write 0x14 to CONSET to set the STO and AA bits.

2. Write 0x08 to CONCLR to clear the SI flag.

3. Exit

15.11.5.2 Master States

State 08 and State 10 are for both Master Transmit and Master Receive modes. The R/W bit decides whether the next state is within Master Transmit mode or Master Receive mode.

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15.11.5.3 State: 0x08

A START condition has been transmitted. The Slave Address + R/W bit will be transmitted, an ACK bit will be received.

1. Write Slave Address with R/W bit to DAT.

2. Write 0x04 to CONSET to set the AA bit.

3. Write 0x08 to CONCLR to clear the SI flag.

4. Set up Master Transmit mode data buffer.

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5. Set up Master Receive mode data buffer.

6. Initialize Master data counter.

7. Exit

15.11.5.4 State: 0x10

A Repeated START condition has been transmitted. The Slave Address + R/W bit will be transmitted, an ACK bit will be received.

1. Write Slave Address with R/W bit to DAT.

2. Write 0x04 to CONSET to set the AA bit.

3. Write 0x08 to CONCLR to clear the SI flag.

4. Set up Master Transmit mode data buffer.

5. Set up Master Receive mode data buffer.

6. Initialize Master data counter.

7. Exit

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15.11.6 Master Transmitter states

15.11.6.1 State: 0x18

Previous state was State 8 or State 10, Slave Address + Write has been transmitted, ACK has been received. The first data byte will be transmitted, an ACK bit will be received.

1. Load DAT with first data byte from Master Transmit buffer.

2. Write 0x04 to CONSET to set the AA bit.

3. Write 0x08 to CONCLR to clear the SI flag.

4. Increment Master Transmit buffer pointer.

5. Exit

15.11.6.2 State: 0x20

Slave Address + Write has been transmitted, NOT ACK has been received. A STOP condition will be transmitted.

1. Write 0x14 to CONSET to set the STO and AA bits.

2. Write 0x08 to CONCLR to clear the SI flag.

3. Exit

15.11.6.3 State: 0x28

Data has been transmitted, ACK has been received. If the transmitted data was the last data byte then transmit a STOP condition, otherwise transmit the next data byte.

1. Decrement the Master data counter, skip to step 5 if not the last data byte.

2. Write 0x14 to CONSET to set the STO and AA bits.

3. Write 0x08 to CONCLR to clear the SI flag.

4. Exit

5. Load DAT with next data byte from Master Transmit buffer.

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6. Write 0x04 to CONSET to set the AA bit.

7. Write 0x08 to CONCLR to clear the SI flag.

8. Increment Master Transmit buffer pointer

9. Exit

15.11.6.4 State: 0x30

Data has been transmitted, NOT ACK received. A STOP condition will be transmitted.

1. Write 0x14 to CONSET to set the STO and AA bits.

2. Write 0x08 to CONCLR to clear the SI flag.

3. Exit

15.11.6.5 State: 0x38

Arbitration has been lost during Slave Address + Write or data. The bus has been released and not addressed Slave mode is entered. A new START condition will be transmitted when the bus is free again.

1. Write 0x24 to CONSET to set the STA and AA bits.

2. Write 0x08 to CONCLR to clear the SI flag.

3. Exit

15.11.7 Master Receive states

15.11.7.1 State: 0x40

Previous state was State 08 or State 10. Slave Address + Read has been transmitted,

ACK has been received. Data will be received and ACK returned.

1. Write 0x04 to CONSET to set the AA bit.

2. Write 0x08 to CONCLR to clear the SI flag.

3. Exit

15.11.7.2 State: 0x48

Slave Address + Read has been transmitted, NOT ACK has been received. A STOP condition will be transmitted.

1. Write 0x14 to CONSET to set the STO and AA bits.

2. Write 0x08 to CONCLR to clear the SI flag.

3. Exit

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15.11.7.3 State: 0x50

Data has been received, ACK has been returned. Data will be read from DAT. Additional data will be received. If this is the last data byte then NOT ACK will be returned, otherwise

ACK will be returned.

1. Read data byte from DAT into Master Receive buffer.

2. Decrement the Master data counter, skip to step 5 if not the last data byte.

3. Write 0x0C to CONCLR to clear the SI flag and the AA bit.

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4. Exit

5. Write 0x04 to CONSET to set the AA bit.

6. Write 0x08 to CONCLR to clear the SI flag.

7. Increment Master Receive buffer pointer

8. Exit

15.11.7.4 State: 0x58

Data has been received, NOT ACK has been returned. Data will be read from DAT. A

STOP condition will be transmitted.

1. Read data byte from DAT into Master Receive buffer.

2. Write 0x14 to CONSET to set the STO and AA bits.

3. Write 0x08 to CONCLR to clear the SI flag.

4. Exit

15.11.8 Slave Receiver states

15.11.8.1 State: 0x60

Own Slave Address + Write has been received, ACK has been returned. Data will be received and ACK returned.

1. Write 0x04 to CONSET to set the AA bit.

2. Write 0x08 to CONCLR to clear the SI flag.

3. Set up Slave Receive mode data buffer.

4. Initialize Slave data counter.

5. Exit

15.11.8.2 State: 0x68

Arbitration has been lost in Slave Address and R/W bit as bus Master. Own Slave Address

+ Write has been received, ACK has been returned. Data will be received and ACK will be returned. STA is set to restart Master mode after the bus is free again.

1. Write 0x24 to CONSET to set the STA and AA bits.

2. Write 0x08 to CONCLR to clear the SI flag.

3. Set up Slave Receive mode data buffer.

4. Initialize Slave data counter.

5. Exit.

15.11.8.3 State: 0x70

General call has been received, ACK has been returned. Data will be received and ACK returned.

1. Write 0x04 to CONSET to set the AA bit.

2. Write 0x08 to CONCLR to clear the SI flag.

3. Set up Slave Receive mode data buffer.

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Chapter 15: LPC111x/LPC11Cxx I2C-bus controller

4. Initialize Slave data counter.

5. Exit

15.11.8.4 State: 0x78

Arbitration has been lost in Slave Address + R/W bit as bus Master. General call has been received and ACK has been returned. Data will be received and ACK returned. STA is set to restart Master mode after the bus is free again.

1. Write 0x24 to CONSET to set the STA and AA bits.

2. Write 0x08 to CONCLR to clear the SI flag.

3. Set up Slave Receive mode data buffer.

4. Initialize Slave data counter.

5. Exit

15.11.8.5 State: 0x80

Previously addressed with own Slave Address. Data has been received and ACK has been returned. Additional data will be read.

1. Read data byte from DAT into the Slave Receive buffer.

2. Decrement the Slave data counter, skip to step 5 if not the last data byte.

3. Write 0x0C to CONCLR to clear the SI flag and the AA bit.

4. Exit.

5. Write 0x04 to CONSET to set the AA bit.

6. Write 0x08 to CONCLR to clear the SI flag.

7. Increment Slave Receive buffer pointer.

8. Exit

15.11.8.6 State: 0x88

Previously addressed with own Slave Address. Data has been received and NOT ACK has been returned. Received data will not be saved. Not addressed Slave mode is entered.

1. Write 0x04 to CONSET to set the AA bit.

2. Write 0x08 to CONCLR to clear the SI flag.

3. Exit

15.11.8.7 State: 0x90

Previously addressed with General Call. Data has been received, ACK has been returned.

Received data will be saved. Only the first data byte will be received with ACK. Additional data will be received with NOT ACK.

1. Read data byte from DAT into the Slave Receive buffer.

2. Write 0x0C to CONCLR to clear the SI flag and the AA bit.

3. Exit

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15.11.8.8 State: 0x98

Previously addressed with General Call. Data has been received, NOT ACK has been returned. Received data will not be saved. Not addressed Slave mode is entered.

1. Write 0x04 to CONSET to set the AA bit.

2. Write 0x08 to CONCLR to clear the SI flag.

3. Exit

15.11.8.9 State: 0xA0

A STOP condition or Repeated START has been received, while still addressed as a

Slave. Data will not be saved. Not addressed Slave mode is entered.

1. Write 0x04 to CONSET to set the AA bit.

2. Write 0x08 to CONCLR to clear the SI flag.

3. Exit

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15.11.9 Slave Transmitter states

15.11.9.1 State: 0xA8

Own Slave Address + Read has been received, ACK has been returned. Data will be transmitted, ACK bit will be received.

1. Load DAT from Slave Transmit buffer with first data byte.

2. Write 0x04 to CONSET to set the AA bit.

3. Write 0x08 to CONCLR to clear the SI flag.

4. Set up Slave Transmit mode data buffer.

5. Increment Slave Transmit buffer pointer.

6. Exit

15.11.9.2 State: 0xB0

Arbitration lost in Slave Address and R/W bit as bus Master. Own Slave Address + Read has been received, ACK has been returned. Data will be transmitted, ACK bit will be received. STA is set to restart Master mode after the bus is free again.

1. Load DAT from Slave Transmit buffer with first data byte.

2. Write 0x24 to CONSET to set the STA and AA bits.

3. Write 0x08 to CONCLR to clear the SI flag.

4. Set up Slave Transmit mode data buffer.

5. Increment Slave Transmit buffer pointer.

6. Exit

15.11.9.3 State: 0xB8

Data has been transmitted, ACK has been received. Data will be transmitted, ACK bit will be received.

1. Load DAT from Slave Transmit buffer with data byte.

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Chapter 15: LPC111x/LPC11Cxx I2C-bus controller

2. Write 0x04 to CONSET to set the AA bit.

3. Write 0x08 to CONCLR to clear the SI flag.

4. Increment Slave Transmit buffer pointer.

5. Exit

15.11.9.4 State: 0xC0

Data has been transmitted, NOT ACK has been received. Not addressed Slave mode is entered.

1. Write 0x04 to CONSET to set the AA bit.

2. Write 0x08 to CONCLR to clear the SI flag.

3. Exit.

15.11.9.5 State: 0xC8

The last data byte has been transmitted, ACK has been received. Not addressed Slave mode is entered.

1. Write 0x04 to CONSET to set the AA bit.

2. Write 0x08 to CONCLR to clear the SI flag.

3. Exit

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Chapter 16: LPC111x/LPC11Cxx C_CAN controller

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16.1 How to read this chapter

The C_CAN block is available in LPC11Cxx parts only (LPC11C00 series).

The LPC11C22 and LPC11C24 parts include an on-chip, high-speed transceiver. For these parts, the CAN_RXD and CAN_TXD signals are connected internally to the on-chip

transceiver and the transceiver signals are pinned out (see Table 244

).

16.2 Basic configuration

The C_CAN is configured using the following registers:

1. Power: In the SYSAHBCLKCTRL register, set bit 17 ( Table 21 ).

2. Clocking: For an accurate peripheral clock to the C_CAN block, select the system

oscillator either as the main clock ( Table 18 ) or as input to the system PLL (

Table 16

).

Do not select the IRC if C_CAN baud rates above 100 kbit/s are required.

3. Reset: Before accessing the C_CAN block, ensure that the CAN_RST_N bit (bit 3) in the PRESETCTRL register (

Table 9

) is set to 1. This de-asserts the reset signal to the

C_CAN block.

The peripheral clock to the C_CAN (the C_CAN system clock) and to the programmable

C_CAN clock divider (see

Table 275 ) is provided by the system clock (see

Table 21

). This clock can be disabled through bit 17 in the SYSAHBCLKCTRL register for power savings.

Remark:

If C_CAN baudrates above 100 kbit/s are required, the system oscillator must be selected as the clock source for the system clock. For lower baudrates, the IRC may also be used as clock source.

16.3 Features

Conforms to protocol version 2.0 parts A and B.

Supports bit rate of up to 1 Mbit/s.

Supports 32 Message Objects.

Each Message Object has its own identifier mask.

Provides programmable FIFO mode (concatenation of Message Objects).

Provides maskable interrupts.

Supports Disabled Automatic Retransmission (DAR) mode for time-triggered CAN applications.

Provides programmable loop-back mode for self-test operation.

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Chapter 16: LPC111x/LPC11Cxx C_CAN controller

16.4 General description

Controller Area Network (CAN) is the definition of a high performance communication protocol for serial data communication. The C_CAN controller is designed to provide a full implementation of the CAN protocol according to the CAN Specification Version 2.0B. The

C_CAN controller allows to build powerful local networks with low-cost multiplex wiring by supporting distributed real-time control with a very high level of security.

The CAN controller consists of a CAN core, message RAM, a message handler, control registers, and the APB interface.

For communication on a CAN network, individual Message Objects are configured. The

Message Objects and Identifier Masks for acceptance filtering of received messages are stored in the Message RAM.

All functions concerning the handling of messages are implemented in the Message

Handler. Those functions are the acceptance filtering, the transfer of messages between the CAN Core and the Message RAM, and the handling of transmission requests as well as the generation of the module interrupt.

The register set of the CAN controller can be accessed directly by an external CPU via the

APB bus. These registers are used to control/configure the CAN Core and the Message

Handler and to access the Message RAM.

CAN_TXD CAN_RXD

C_CAN

CAN CORE

APB bus

MESSAGE RAM

MESSAGE

HANDLER

APB

INTERFACE

REGISTER

INTERFACE

Fig 61. C_CAN block diagram

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Chapter 16: LPC111x/LPC11Cxx C_CAN controller

16.5 Pin description

Table 243. CAN pin description (LPC11C12/C14)

Pin Type Description

CAN_TXD

CAN_RXD I

O C_CAN transmit output

C_CAN receive input

Table 244. CAN pin description (LPC11C22/C24)

Pin Type Description

CANL

CANH

STB I

I/O

I/O

LOW-level CAN bus line.

HIGH-level CAN bus line.

Silent mode control input for CAN transceiver (LOW = Normal mode,

HIGH = silent mode).

VDD_CAN

V

CC

GND

-

-

-

Supply voltage for I/O level of CAN transceiver.

Supply voltage for CAN transceiver.

Ground for CAN transceiver.

16.6 Register description

The C_CAN registers are organized as 32-bit wide registers.

The two sets of interface registers (IF1 and IF2) control the CPU access to the Message

RAM. They buffer the data to be transferred to and from the RAM, avoiding conflicts between CPU accesses and message reception/transmission.

Table 245. Register overview: CCAN (base address 0x4005 0000)

Name Access Address offset

Description

CANCNTL R/W 0x000 CAN control

CANSTAT

CANEC

CANBT

CANINT

R/W

RO

R/W

RO

0x004

0x008

0x00C

0x010

Status register

Error counter

Bit timing register

Interrupt register

CANTEST

CANBRPE

-

CANIF1_CMDREQ

CANIF1_CMDMSK_W

CANIF1_CMDMSK_R

R/W

R/W

-

R/W

R/W

R/W

0x014

0x018

0x01C

0x020

0x024

0x024

Test register

Baud rate prescaler extension register

Reserved

Message interface 1 command request

Message interface 1 command mask (write direction)

Message interface 1 command mask (read direction)

CANIF1_MSK1

CANIF1_MSK2

CANIF1_ARB1

CANIF1_ARB2

CANIF1_MCTRL

R/W

R/W

R/W

R/W

R/W

0x028

0x02C

0x030

0x034

0x038

Message interface 1 mask 1

Message interface 1 mask 2

Message interface 1 arbitration 1

Message interface 1 arbitration 2

Message interface 1 message control

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0x0000

0xFFFF

0xFFFF

0x0000

0x0000

0x0000

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Reset value

0x0001

0x0000

0x0000

0x2301

0x0000

-

0x0000

-

0x0001

0x0000

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Chapter 16: LPC111x/LPC11Cxx C_CAN controller

Table 245. Register overview: CCAN (base address 0x4005 0000)

Name Access Address offset

Description

-

CANIF1_DA1

CANIF1_DA2

CANIF1_DB1

CANIF1_DB2

-

R/W

R/W

R/W

R/W

0x03C

0x040

0x044

0x048

0x04C -

0x07C

Message interface 1 data A1

Message interface 1 data A2

Message interface 1 data B1

Message interface 1 data B2

Reserved

CANIF2_CMDREQ

CANIF2_CMDMSK_W

R/W

R/W

0x080

0x084

-

-

CANIF2_CMDMSK_R

CANIF2_MSK1

CANIF2_MSK2

CANIF2_ARB1

CANIF2_ARB2

CANIF2_MCTRL

CANIF2_DA1

CANIF2_DA2

CANIF2_DB1

CANIF2_DB2

CANTXREQ1

CANTXREQ2

-

-

R/W

R/W

R/W

R/W

R/W

R/W

R/W

R/W

R/W

R/W

RO

RO

0x084

0x088

0x08C

0x090

0x094

0x098

0x09C

0x0A0

0x0A4

0x0A8

0x0AC -

0x0FC

0x100

0x104

0x108 -

0x11C

Message interface 2 command request

Message interface 2 command mask (write direction)

Message interface 2 command mask (read direction)

Message interface 2 mask 1

Message interface 2 mask 2

Message interface 2 arbitration 1

Message interface 2 arbitration 2

Message interface 2 message control

Message interface 2 data A1

Message interface 2 data A2

Message interface 2 data B1

Message interface 2 data B2

Reserved

Transmission request 1

Transmission request 2

Reserved

-

CANND1

CANND2

-

RO

RO

New data 1

New data 2

Reserved

-

-

CANIR1

CANIR2

CANMSGV1

CANMSGV2

CANCLKDIV

-

-

RO

RO

RO

RO

R/W

0x120

0x124

0x128 -

0x13C

0x140

0x144

0x148 -

0x15C

0x160

0x164

0x168 -

0x17C

0x180

Interrupt pending 1

Interrupt pending 2

Reserved

Message valid 1

Message valid 2

Reserved

Can clock divider register

-

0x0000

0x0000

-

0x0000

0x0000

-

0x0000

0x0000

-

0x0000

0x0000

0x0001

Reset value

0x0000

0x0000

-

0x0000

0x0000

0x0001

0x0000

0x0000

0xFFFF

0xFFFF

0x0000

0x0000

0x0000

0x0000

0x0000

-

0x0000

0x0000

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Chapter 16: LPC111x/LPC11Cxx C_CAN controller

16.6.1 CAN protocol registers

16.6.1.1 CAN control register

The reset value 0x0001 of the CANCTL register enables initialization by software (INIT =

1). The C_CAN does not influence the CAN bus until the CPU resets the INIT bit to 0.

Table 246. CAN control registers (CANCNTL, address 0x4005 0000) bit description

Bit Symbol Value Description Reset value

Access

0 INIT Initialization 1 R/W

1 IE

0

1

0

Normal operation.

Started. Initialization is started. On reset, software needs to initialize the CAN controller.

Module interrupt enable

Disable CAN interrupts. The interrupt line is always HIGH.

0 R/W

1

2 SIE

0

1

Enable CAN interrupts. The interrupt line is set to LOW and remains LOW until all pending interrupts are cleared.

Status change interrupt enable 0

Disable status change interrupts. No status change interrupt will be generated.

Enable status change interrupts. A status change interrupt will be generated when a message transfer is successfully completed or a CAN bus error is detected.

R/W

3 EIE R/W

4

5

6

7

31:8

-

-

DAR

CCE

TEST

-

0

1

0

1

0

1

0

1

Error interrupt enable

Disable error interrupt. No error status interrupt will be generated.

0

Enable error interrupt. A change in the bits

BOFF or EWARN in the CANSTAT registers will generate an interrupt.

reserved

Disable automatic retransmission

Enabled. Automatic retransmission of disturbed messages enabled.

0

0

Disabled. Automatic retransmission disabled.

Configuration change enable

No write access. The CPU has no write access to the bit timing register.

Write access. The CPU has write access to the

CANBT register while the INIT bit is one.

0

Test mode enable

Normal operation.

Test mode.

reserved -

0

-

-

R/W

R/W

R/W

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Chapter 16: LPC111x/LPC11Cxx C_CAN controller

Remark:

The busoff recovery sequence (see

CAN Specification Rev. 2.0

) cannot be shortened by setting or resetting the INIT bit. If the device goes into busoff state, it will set

INIT, stopping all bus activities. Once INIT has been cleared by the CPU, the device will then wait for 129 occurrences of Bus Idle (129

11 consecutive HIGH/recessive bits) before resuming normal operations. At the end of the busoff recovery sequence, the Error

Management Counters will be reset.

During the waiting time after the resetting of INIT, each time a sequence of 11

HIGH/recessive bits has been monitored, a Bit0Error code is written to the Status Register

CANSTAT, enabling the CPU to monitor the proceeding of the busoff recovery sequence and to determine whether the CAN bus is stuck at LOW/dominant or continuously disturbed.

16.6.1.2 CAN status register

A status interrupt is generated by bits BOFF, EWARN, RXOK, TXOK, or LEC. BOFF and

EWARN generate an error interrupt, and RXOK, TXOK, and LEC generate a status change interrupt if EIE and SIE respectively are set to enabled in the CANCTRL register.

A change of bit EPASS and a write to RXOK, TXOK, or LEC will never create a status interrupt.

Reading the CANSTAT register will clear the Status Interrupt value (0x8000) in the

CANINT register.

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Chapter 16: LPC111x/LPC11Cxx C_CAN controller

Table 247. CAN status register (CANSTAT, address 0x4005 0004) bit description

Bit

2:0

3

4

Symbol

LEC

TXOK

RXOK

Value

0x0

0x1

0x2

0x3

0x4

0x5

0x6

0x7

0

1

0

1

Description

Last error code

Type of the last error to occur on the CAN bus.The LEC field holds a code which indicates the type of the last error to occur on the CAN bus.

This field will be cleared to ‘0’ when a message has been transferred

(reception or transmission) without error. The unused code ‘111’ may be written by the CPU to check for updates.

000

No error

.

Reset value

Stuff error

. More than 5 equal bits in a sequence have occurred in a part of a received message where this is not allowed.

Form error

. A fixed format part of a received frame has the wrong format.

AckError

. The message this CAN core transmitted was not acknowledged.

Bit1Error

. During the transmission of a message (with the exception of the arbitration field), the device wanted to send a HIGH/recessive level

(bit of logical value ‘1’), but the monitored bus value was

LOW/dominant.

Bit0Error

. During the transmission of a message (or acknowledge bit, or active error flag, or overload flag), the device wanted to send a

LOW/dominant level (data or identifier bit logical value ‘0’), but the monitored Bus value was HIGH/recessive. During busoff recovery this status is set each time a sequence of 11 HIGH/recessive bits has been monitored. This enables the CPU to monitor the proceeding of the busoff recovery sequence (indicating the bus is not stuck at

LOW/dominant or continuously disturbed).

CRCError

. The CRC checksum was incorrect in the message received.

Unused.

No CAN bus event was detected (written by the CPU).

Transmitted a message successfully

This bit must be reset by the CPU. It is never reset by the CAN controller.

No transmit. Since this bit was last reset by the CPU, no message has been successfully transmitted.

Successful transmit. Since this bit was last reset by the CPU, a message has been successfully transmitted (error free and acknowledged by at least one other node).

Received a message successfully

This bit must be reset by the CPU. It is never reset by the CAN controller.

No receive. Since this bit was last reset by the CPU, no message has been successfully received.

Successful receive.Since this bit was last set to zero by the CPU, a message has been successfully received independent of the result of acceptance filtering.

0

0

Access

R/W

R/W

R/W

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Chapter 16: LPC111x/LPC11Cxx C_CAN controller

Table 247. CAN status register (CANSTAT, address 0x4005 0004) bit description

…continued

Bit Symbol Value Description

5

6

7

31:8 -

EPASS

EWARN

BOFF

-

0

1

0

1

0

1

Error passive

Active. The CAN controller is in the error active state.

Passive. The CAN controller is in the error passive state as defined in the

CAN 2.0 specification

.

Warning status

Below limit. Both error counters are below the error warning limit of 96.

At limit. At least one of the error counters in the EC has reached the error warning limit of 96.

Busoff status

The CAN module is not in busoff.

The CAN controller is in busoff state.

reserved

Reset value

0

0

0

Access

RO

RO

RO

16.6.1.3 CAN error counter

Table 248. CAN error counter (CANEC, address 0x4005 0008) bit description

Bit Symbol Value Description Reset value

7:0 TEC7_0 0

14:8

15

REC6_0

RP

Transmit error counter

Current value of the transmit error counter

(maximum value 255)

Receive error counter

Current value of the receive error counter

(maximum value 127).

Receive error passive -

-

0

31:16 -

1

-

Below error level. The receive counter is below the error passive level.

At error level. The receive counter has reached the error passive level as defined in the

CAN2.0 specification

.

Reserved -

Access

RO

RO

RO

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Chapter 16: LPC111x/LPC11Cxx C_CAN controller

16.6.1.4 CAN bit timing register

Table 249. CAN bit timing register (CANBT, address 0x4005 000C) bit description

Bit Symbol Description Reset value

5:0 BRP Baud rate prescaler

The value by which the oscillator frequency is divided for generating the bit time quanta. The bit time is built up from a multiple of this quanta. Valid values for the Baud Rate

Prescaler are 0 to 63.

[1]

000001

7:6 SJW 00

11:8

14:12

31:15 -

TSEG1

TSEG2

(Re)synchronization jump width

Valid programmed values are 0 to 3.

[1]

Time segment before the sample point including propagation segment.

Valid values are 1 to 15.

[1]

Time segment after the sample point

Valid values are 0 to 7.

[1]

Reserved -

0011

010

[1] Hardware interprets the value programmed into these bits as the bit value

1.

-

Access

R/W

R/W

R/W

R/W

For example, with a LPC11Cx system clock set to of 8 MHz, the reset value of 0x2301 configures the C_CAN for a bit rate of 500 kBit/s.

The registers are only writable if a configuration change is enabled in CANCTRL and the controller is initialized by software (bits CCE and INIT in the CAN Control Register are set).

For details on bit timing, see Section 16.7.5

and the

Bosch C_CAN user’s manual, revision 1.2

.

Baud rate prescaler

The bit time quanta t q

are determined by the BRP value: t q

= BRP / f sys

(f sys

is the LPC11Cx system clock to the C_CAN block).

Time segments 1 and 2

Time segments TSEG1 and TSEG2 determine the number of time quanta per bit time and the location of the sample point: t

TSEG1/2

= t q

(TSEG1/2 + 1)

Synchronization jump width

To compensate for phase shifts between clock oscillators of different bus controllers, any bus controller must re-synchronize on any relevant signal edge of the current transmission. The synchronization jump width t

SJW

defines the maximum number of clock cycles a certain bit period may be shortened or lengthened by one re-synchronization: t

SJW

= t q

(SJW + 1)

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Chapter 16: LPC111x/LPC11Cxx C_CAN controller

16.6.1.5 CAN interrupt register

Table 250. CAN interrupt register (CANINT, address 0x4005 0010) bit description

Bit Symbol Description Reset value

15:0 INTID

31:16 -

0x0000 = No interrupt is pending.

0x0001 - 0x0020 = Number of message object which caused the interrupt.

0x0021 - 0x7FFF = Unused

0x8000 = Status interrupt

0x8001 - 0xFFFF = Unused

0

Reserved -

Access

R

If several interrupts are pending, the CAN Interrupt Register will point to the pending interrupt with the highest priority, disregarding their chronological order. An interrupt remains pending until the CPU has cleared it. If INTID is different from 0x0000 and IE is set, the interrupt line to the CPU is active. The interrupt line remains active until INTID is back to value 0x0000 (the cause of the interrupt is reset) or until IE is reset.

The Status Interrupt has the highest priority. Among the message interrupts, the Message

Object’ s interrupt priority decreases with increasing message number.

A message interrupt is cleared by clearing the Message Object’s INTPND bit. The

StatusInterrupt is cleared by reading the Status Register.

16.6.1.6 CAN test register

Write access to the Test Register is enabled by setting bit Test in the CAN Control

Register.

The different test functions may be combined, but when TX[1:0]

“00” is selected, the message transfer is disturbed.

Table 251. CAN test register (CANTEST, address 0x4005 0014) bit description

Bit Symbol Value Description Reset value

1:0

2

3

-

BASIC

SILENT

-

0

1

Reserved

Basic mode 0

Disabled. Basic mode disabled.

Enabled. IF1 registers used as TX buffer, IF2 registers used as RX buffer.

Silent mode 0

4 LBACK

0

1

0

1

Normal operation.

Silent mode. The module is in silent mode.

Loop back mode

Disabled. Loop back mode is disabled.

Enabled. Loop back mode is enabled.

0

Access

-

R/W

R/W

R/W

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Chapter 16: LPC111x/LPC11Cxx C_CAN controller

Table 251. CAN test register (CANTEST, address 0x4005 0014) bit description

Bit Symbol Value Description Reset value

6:5 TX 00

0x0

0x1

Control of CAN_TXD pins

Controller. Level at the CAN_TXD pin is controlled by the CAN controller. This is the value at reset.

Sample point. The sample point can be monitored at the CAN_TXD pin.

7

31:8 -

RX

0x2

0x3

0

1

Low. CAN_TXD pin is driven LOW/dominant.

High. CAN_TXD pin is driven

HIGH/recessive.

Monitors the actual value of the CAN_RXD pin.

Dominant. The CAN bus is dominant

(CAN_RXD = 0).

Recessive. The CAN bus is recessive

(CAN_RXD = 1).

R/W

0

-

Access

R/W

R

16.6.1.7 CAN baud rate prescaler extension register

Table 252. CAN baud rate prescaler extension register (CANBRPE, address 0x4005 0018) bit description

Bit Symbol Description Reset value

Access

3:0 BRPE

31:4 -

Baud rate prescaler extension

By programming BRPE the Baud Rate Prescaler can be extended to values up to 1023. Hardware interprets the value as the value of BRPE (MSBs) and BRP (LSBs) plus one. Allowed values are 0 to 15.

0x0000 R/W

Reserved -

16.6.2 Message interface registers

There are two sets of interface registers which are used to control the CPU access to the

Message RAM. The interface registers avoid conflicts between CPU access to the

Message RAM and CAN message reception and transmission by buffering the data to be transferred. A complete Message Object (see

Section 16.6.2.1

) or parts of the Message

Object may be transferred between the Message RAM and the IFx Message Buffer registers in one single transfer.

The function of the two interface register sets is identical (except for test mode Basic).

One set of registers may be used for data transfer to the Message RAM while the other set of registers may be used for the data transfer from the Message RAM, allowing both processes to be interrupted by each other.

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Chapter 16: LPC111x/LPC11Cxx C_CAN controller

Each set of interface registers consists of message buffer registers controlled by their own command registers. The command mask register specifies the direction of the data transfer and which parts of a message object will be transferred. The command request register is used to select a message object in the message RAM as target or source for the transfer and to start the action specified in the command mask register.

Table 253. Message interface registers

IF1 register names

CANIF1_CMDREQ

IF1 register set

IF1 command request

CANIF1_CMDMASK

CANIF1_MASK1

CANIF1_MASK2

CANIF1_ARB1

IF1 command mask

IF1 mask 1

IF1 mask 2

IF1 arbitration 1

CANIF1_ARB2

CANIF1_MCTRL

CANIF1_DA1

CANIF1_DA2

CANIF1_DB1

CANIF1_DB2

IF1 arbitration 2

IF1 message control

IF1 data A1

IF1 data A2

IF1 data B1

IF1 data B2

IF2 register names

CANIF2_CMDREQ

CANIF2_CMDMASK

CANIF2_MSK1

CANIF2_MSK2

CANIF2_ARB1

CANIF2_ARB2

CANIF2_MCTRL

CANIF2_DA1

CANIF2_DA2

CANIF2_DB1

CANIF2_DB2

IF2 register set

IF2 command request

IF2 command mask

IF2 mask 1

IF2 mask 2

IF2 arbitration 1

IF2 arbitration 2

IF2 message control

IF2 data A1

IF2 data A2

IF2 data B1

IF2 data B2

There are 32 Message Objects in the Message RAM. To avoid conflicts between CPU access to the Message RAM and CAN message reception and transmission, the CPU cannot directly access the Message Objects. The message objects are accessed through the IFx Interface Registers.

For details of message handling, see

Section 16.7.3

.

16.6.2.1 Message objects

A message object contains the information from the various bits in the message interface registers.

Table 254 below shows a schematic representation of the structure of the

message object. The bits of a message object and the respective interface register where this bit is set or cleared are shown. For bit functions see the corresponding interface register.

Table 254. Structure of a message object in the message RAM

UMASK MSK[28:0] MXTD MDIR EOB NEWDAT

IF1/2_MCTRL

RMTEN TXRQST

IF1/2_MSK1/2

MSGVAL ID[28:0] XTD DIR

MSGLST RXIE

DLC3

IF1/2_MCTRL

DLC2

IF1/2_MCTRL

DATA0

IF1/2_DA1

DATA1 DATA2

IF1/2_ARB1/2

DATA3 DATA4

IF1/2_DA2

DATA5

IF1/2_DB1

TXIE

DLC1

DATA6

IF1/2_MCTRL

DATA7

IF1/2_DB2

INTPND

DLC0

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16.6.2.2 CAN message interface command request registers

A message transfer is started as soon as the CPU has written the message number to the

Command Request Register. With this write operation the BUSY bit is automatically set to

‘1’ and the signal CAN_WAIT_B is pulled LOW to notify the CPU that a transfer is in progress. After a wait time of 3 to 6 CAN_CLK periods, the transfer between the Interface

Register and the Message RAM has completed. The BUSY bit is set back to zero and the signal CAN_WAIT_B is set back.

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Table 255. CAN message interface command request registers (CANIF1_CMDREQ, address

0x4005 0020 and CANIF2_CMDREQ, address 0x4005 0080) bit description

Bit Symbol Value Description Access

5:0 MN

Reset

Value

0x00 R/W

14:6

15

-

BUSY

0

Message number

0x01 - 0x20 = Valid message numbers. The message object in the message RAM is selected for data transfer.

0x00 = Not a valid message number. This value is interpreted as 0x20.

[1]

0x21 - 0x3F = Not a valid message number. This

value is interpreted as 0x01 - 0x1F.

[1]

reserved

BUSY flag

Done. Set to zero by hardware when read/write action to this Command request register has finished.

-

0

-

RO

31:16 -

1 Busy. Set to one by hardware when writing to this

Command request register.

Reserved -

[1] When a message number that is not valid is written into the Command request registers, the message number will be transformed into a valid value and that message object will be transferred.

16.6.2.3 CAN message interface command mask registers

The control bits of the IFx Command Mask Register specify the transfer direction and select which of the IFx Message Buffer Registers are source or target of the data transfer.The functions of the register bits depend on the transfer direction (read or write) which is selected in the WR/RD bit (bit 7) of this Command mask register.

Select the WR/RD to

one

for the Write transfer direction (write to message RAM)

zero

for the Read transfer direction (read from message RAM)

Table 256. CAN message interface command mask registers (CANIF1_CMDMSK_W, address

0x4005 0024 and CANIF2_CMDMSK_W, address 0x4005 0084) bit description for write direction

Bit Symbol Value Description

0 DATA_B

0

1

Access data bytes 4-7

Unchanged. Data bytes 4-7 unchanged.

Transfer. Transfer data bytes 4-7 to message object.

Reset value

0

Access

R/W

1 DATA_A R/W

0

1

Access data bytes 0-3

Unchanged. Data bytes 0-3 unchanged.

Transfer. Transfer data bytes 0-3 to message object.

0

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Table 256. CAN message interface command mask registers (CANIF1_CMDMSK_W, address

0x4005 0024 and CANIF2_CMDMSK_W, address 0x4005 0084) bit description for write direction

…continued

Bit Symbol Value Description Reset value

Access

2 TXRQST R/W

3

4

CLRINTPND

CTRL

-

0

1

Access transmission request bit

No transmission request. TXRQST bit unchanged in IF1/2_MCTRL.

Remark:

If a transmission is requested by programming this bit, the TXRQST bit in the

CANIFn_MCTRL register is ignored.

0

Request a transmission. Set the TXRQST bit

IF1/2_MCTRL.

This bit is ignored in the write direction.

0

0

R/W

R/W

0

1

Access control bits

Unchanged. Control bits unchanged.

Transfer. Transfer control bits to message object

5 ARB

0

1

Access arbitration bits

Unchanged. Arbitration bits unchanged.

Transfer. Transfer Identifier, DIR, XTD, and

MSGVAL bits to message object.

0 R/W

6

7

31:8 -

MASK

WR_RD

-

0

1

1

Access mask bits

Unchanged. Mask bits unchanged.

Transfer. Transfer Identifier MSK + MDIR +

MXTD to message object.

Write transfer

Transfer data from the selected message buffer registers to the message object addressed by the command request register

CANIFn_CMDREQ.

reserved

0

0

0 -

R/W

R/W

Table 257. CAN message interface command mask registers (CANIF1_CMDMSK_R, address

0x4005 0024 and CANIF2_CMDMSK_R, address 0x4005 0084) bit description for read direction

Bit Symbol Value Description

0 DATA_B

0

1

Access data bytes 4-7

Unchanged. Data bytes 4-7 unchanged.

Transfer. Transfer data bytes 4-7 to IFx message buffer register.

Reset value

0

Access

R/W

1 DATA_A 0 R/W

0

1

Access data bytes 0-3

Unchanged. Data bytes 0-3 unchanged.

Transfer. Transfer data bytes 0-3 to IFx message buffer.

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Table 257. CAN message interface command mask registers (CANIF1_CMDMSK_R, address

0x4005 0024 and CANIF2_CMDMSK_R, address 0x4005 0084) bit description for read direction

…continued

Bit Symbol Value Description Reset value

Access

2 NEWDAT R/W

0

Access new data bit

Unchanged. NEWDAT bit remains unchanged.

Remark:

A read access to a message object can be combined with the reset of the control bits INTPND and NEWDAT in IF1/2_MCTRL.

The values of these bits transferred to the IFx

Message Control Register always reflect the status before resetting these bits.

0

1

3 CLRINTPND

0

1

Clear. Clear NEWDAT bit in the message object.

Clear interrupt pending bit.

Unchanged. INTPND bit remains unchanged.

0 R/W

4

5

CTRL

ARB

0

1

0

1

Clear. Clear INTPND bit in the message object.

Access control bits

Unchanged. Control bits unchanged.

Transfer. Transfer control bits to IFx message buffer.

0

0 Access arbitration bits

Unchanged. Arbitration bits unchanged.

Transfer. Transfer Identifier, DIR, XTD, and

MSGVAL bits to IFx message buffer register.

R/W

R/W

6

7

31:8 -

MASK

WR_RD

-

0

1

0

Access mask bits

Unchanged. Mask bits unchanged.

Transfer. Transfer Identifier MSK + MDIR +

MXTD to IFx message buffer register.

Read transfer

Transfer data from the message object addressed by the command request register to the selected message buffer registers

CANIFn_CMDREQ.

reserved

0

0

0 -

R/W

R/W

16.6.2.4 IF1 and IF2 message buffer registers

The bits of the Message Buffer registers mirror the Message Objects in the Message

RAM.

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16.6.2.4.1

CAN message interface mask 1 registers

Table 258. CAN message interface mask 1 registers (CANIF1_MSK1, address 0x4005 0028 and CANIF2_MASK1, address 0x4005 0088) bit description

Bit Symbol Value Description Reset value

Access

15:0 MSK15_0 R/W

31:16 -

0

1

Identifier mask [15:0]

Match. The corresponding bit in the identifier of the message cannot inhibit the match in the acceptance filtering.

0xFFFF

Mask. The corresponding identifier bit is used for acceptance filtering.

Reserved 0 -

16.6.2.4.2

CAN message interface mask 2 registers

Table 259. CAN message interface mask 2 registers (CANIF1_MSK2, address 0x4005 002C and CANIF2_MASK2, address 0x4005 008C) bit description

Bit

12:0

13

14

15

31:16 -

-

Symbol

MSK28_16

MDIR

MXTD

-

Value Description

0

1

Identifier mask [28:16]

Match. The corresponding bit in the identifier of the message cannot inhibit the match in the acceptance filtering.

Mask. The corresponding identifier bit is used for acceptance filtering.

Reserved 1

Reset value

0xFFF

1

0

1

Mask message direction

Without DIR bit. The message direction bit (DIR) has no effect on acceptance filtering.

With DIR bit. The message direction bit (DIR) is used for acceptance filtering.

Mask extend identifier 1

0

1

Without XTD. The extended identifier bit (XTD) has no effect on acceptance filtering.

With XTD. The extended identifier bit (XTD) is used for acceptance filtering.

Reserved 0 -

Access

R/W

-

R/W

R/W

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16.6.2.4.3

CAN message interface c arbitration 1 registers

Table 260. CAN message interface arbitration 1 registers (CANIF1_ARB1, address

0x4005 0030 and CANIF2_ARB1, address 0x4005 0090) bit description

Bit Symbol Description Reset value

Access

15:0 ID15_0 R/W

31:16 -

Message identifier [15:0]

29-bit identifier (extended frame)

11-bit identifier (standard frame). These bits are not used for 11-bit identifiers.

0x00

Reserved 0 -

[1]

16.6.2.4.4

CAN message interface arbitration 2 registers

Table 261. CAN message interface arbitration 2 registers (CANIF1_ARB2, address 0x4005 0034 and CANIF2_ARB2, address 0x4005 0094) bit description

Bit Symbol Value Description Access

12:0

Reset value

0x00 R/W

ID[28:16]

ID[28:18]

Message identifier

29-bit identifier (extended frame)

11-bit identifier (standard frame). ID[17:16] are not used for 11-bit identifiers.

13 DIR R/W

14 XTD

0

1

Message direction

Receive.

On TXRQST, a Remote Frame with the identifier of this Message Object is transmitted. On reception of a Data Frame with matching identifier, that message is stored in this Message Object.

0x00

Transmit.

On TXRQST, the respective Message Object is transmitted as a Data

Frame. On reception of a Remote Frame with matching identifier, the

TXRQST bit of this Message Object is set (if RMTEN = one).

Extend identifier 0x00 R/W

0

15

31:16 -

MSGVAL

-

1

0

1

Standard. The 11-bit standard identifier will be used for this message object.

Extended. The 29-bit extended identifier will be used for this message object.

Message valid

Remark:

The CPU must reset the MSGVAL bit of all unused Messages

Objects during the initialization before it resets bit INIT in the CAN Control

Register. This bit must also be reset before the identifier ID28:0, the control bits XTD, DIR, or the Data Length Code DLC3:0 are modified, or if the

Messages Object is no longer required.

0

Invalid. The message object is ignored by the message handler.

Valid. The message object is configured and should be considered by the message handler.

Reserved 0 -

R/W

[1]

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16.6.2.4.5

CAN message interface message control registers

Table 262. CAN message interface message control registers (CANIF1_MCTRL, address 0x4005 0038 and

CANIF2_MCTRL, address 0x4005 0098) bit description

Bit Symbol Value Description Reset value

Access

3:0 DLC3_0 R/W

6:4

7

-

EOB

Data length code 3:0

Remark:

The Data Length Code of a Message Object must be defined the same as in all the corresponding objects with the same identifier at other nodes. When the Message Handler stores a data frame, it will write the

DLC to the value given by the received message.

0000 - 1000 = Data frame has 0 - 8 data bytes.

1001 - 1111 = Data frame has 8 data bytes.

0000

Reserved

End of buffer

-

0

-

R/W

0

8 TXRQST

1

0

1

Not end of buffer. Message object belongs to a FIFO buffer and is not the last message object of that FIFO buffer.

End of buffer. Single message object or last message object of a FIFO buffer.

Transmit request

Not waiting. This message object is not waiting for transmission.

Waiting. The transmission of this message object is requested and is not yet done

0 R/W

9 RMTEN R/W

10

11

12

13

RXIE

TXIE

UMASK

INTPND

0

1

0

1

0

1

0

1

0

1

Remote enable

TXRQST unchanged. At the reception of a remote frame, TXRQST is left unchanged.

TXRQST set. At the reception of a remote frame, TXRQST is set.

Receive interrupt enable

INTPND unchanged. INTPND will be left unchanged after successful reception of a frame.

INTPND set. INTPND will be set after successful reception of a frame.

0

0

Transmit interrupt enable

INTPND unchanged. The INTPND bit will be left unchanged after a successful transmission of a frame.

0

INTPND set. INTPND will be set after a successful transmission of a frame.

Use acceptance mask

Remark:

If UMASK is set to 1, the message object’s mask bits have to be programmed during initialization of the message object before MAGVAL is set to 1.

0

Ignore. Mask ignored.

Use. Use mask (MSK[28:0], MXTD, and MDIR) for acceptance filtering.

Interrupt pending

Not pending. This message object is not the source of an interrupt.

Pending. This message object is the source of an interrupt. The Interrupt

Identifier in the Interrupt Register will point to this message object if there is no other interrupt source with higher priority.

0

R/W

R/W

R/W

R/W

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Table 262. CAN message interface message control registers (CANIF1_MCTRL, address 0x4005 0038 and

CANIF2_MCTRL, address 0x4005 0098) bit description

…continued

Bit Symbol Value Description Reset value

Access

14 MSGLST 0 R/W

15 NEWDAT

0

1

Message lost (only valid for message objects in the direction receive).

Not lost. No message lost since this bit was reset last by the CPU.

Lost. The Message Handler stored a new message into this object when

NEWDAT was still set, the CPU has lost a message.

New data 0 R/W

31:16 -

0

1

No new data. No new data has been written into the data portion of this message object by the message handler since this flag was cleared last by the CPU.

New data. The message handler or the CPU has written new data into the data portion of this message object.

Reserved 0 -

16.6.2.4.6

CAN message interface data A1 registers

In a CAN Data Frame, DATA0 is the first, DATA7 (in CAN_IF1B2 AND CAN_IF2B2) is the last byte to be transmitted or received. In CAN’s serial bit stream, the MSB of each byte will be transmitted first.

Remark:

Byte DATA0 is the first data byte shifted into the shift register of the CAN Core during a reception, byte DATA7 is the last. When the Message Handler stores a Data

Frame, it will write all the eight data bytes into a Message Object. If the Data Length Code is less than 8, the remaining bytes of the Message Object will be overwritten by non specified values.

Table 263. CAN message interface data A1 registers (CANIF1_DA1, address 0x4005 003C and CANIF2_DA1, address 0x4005 009C) bit description

Bit Symbol Description Reset value Access

7:0

15:8

31:16 -

DATA0

DATA1

Data byte 0

Data byte 1

Reserved -

0x00

0x00

-

R/W

R/W

16.6.2.4.7

CAN message interface data A2 registers

Table 264. CAN message interface data A2 registers (CANIF1_DA2, address 0x4005 0040 and CANIF2_DA2, address 0x4005 00A0) bit description

Bit

7:0

Symbol Description

DATA2 Data byte 2

Reset value

0x00

Access

R/W

15:8

31:16 -

DATA3 Data byte 3

Reserved -

0x00

-

R/W

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16.6.2.4.8

CAN message interface data B1 registers

Table 265. CAN message interface data B1 registers (CANIF1_DB1, address 0x4005 0044 and CANIF2_DB1, address 0x4005 00A4) bit description

Bit

7:0

Symbol Description

DATA4 Data byte 4

Reset value

0x00

Access

R/W

15:8

31:16 -

DATA5 Data byte 5

Reserved -

0x00

-

R/W

16.6.2.4.9

CAN message interface data B2 registers

Table 266. CAN message interface data B2 registers (CANIF1_DB2, address 0x4005 0048 and CANIF2_DB2, address 0x4005 00A8) bit description

Bit Symbol Description Reset value Access

7:0

15:8

31:16 -

DATA6

DATA7

Data byte 6

Data byte 7

Reserved -

0x00

0x00

-

R/W

R/W

16.6.3 Message handler registers

All Message Handler registers are read-only. Their contents (TXRQST, NEWDAT,

INTPND, and MSGVAL bits of each Message Object and the Interrupt Identifier) is status information provided by the Message Handler FSM.

16.6.3.1 CAN transmission request 1 register

This register contains the TXRQST bits of message objects 1 to 16. By reading out the

TXRQST bits, the CPU can check for which Message Object a Transmission Request is pending. The TXRQST bit of a specific Message Object can be set/reset by the CPU via the IFx Message Interface Registers or by the Message Handler after reception of a

Remote Frame or after a successful transmission.

Table 267. CAN transmission request 1 register (CANTXREQ1, address 0x4005 0100) bit description

Bit Symbol Description Access

15:0 TXRQST16_1

Reset value

0x00 R Transmission request bit of message objects 16 to 1.

0 = This message object is not waiting for transmission.

1 = The transmission of this message object is requested and not yet done.

31:16 Reserved -

16.6.3.2 CAN transmission request 2 register

This register contains the TXRQST bits of message objects 32 to 17. By reading out the

TXRQST bits, the CPU can check for which Message Object a Transmission Request is pending. The TXRQST bit of a specific Message Object can be set/reset by the CPU via the IFx Message Interface Registers or by the Message Handler after reception of a

Remote Frame or after a successful transmission.

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Table 268. CAN transmission request 2 register (CANTXREQ2, address 0x4005 0104) bit description

Bit Symbol

15:0 TXRQST32_17

Description Reset value

Access

Transmission request bit of message objects 32 to 17.

0 = This message object is not waiting for transmission.

1 = The transmission of this message object is requested and not yet done.

0x00 R

31:16 Reserved -

16.6.3.3 CAN new data 1 register

This register contains the NEWDAT bits of message objects 16 to 1. By reading out the

NEWDAT bits, the CPU can check for which Message Object the data portion was updated. The NEWDAT bit of a specific Message Object can be set/reset by the CPU via the IFx Message Interface Registers or by the Message Handler after reception of a Data

Frame or after a successful transmission.

Table 269. CAN new data 1 register (CANND1, address 0x4005 0120) bit description

Bit Symbol Description Reset value

Access

15:0 NEWDAT16_1 R

31:16 -

New data bits of message objects 16 to 1.

0 = No new data has been written into the data portion of this Message Object by the Message Handler since last time this flag was cleared by the CPU.

1 = The Message Handler or the CPU has written new data into the data portion of this Message Object.

0x00

Reserved -

16.6.3.4 CAN new data 2 register

This register contains the NEWDAT bits of message objects 32 to 17. By reading out the

NEWDAT bits, the CPU can check for which Message Object the data portion was updated. The NEWDAT bit of a specific Message Object can be set/reset by the CPU via the IFx Message Interface Registers or by the Message Handler after reception of a Data

Frame or after a successful transmission.

Table 270. CAN new data 2 register (CANND2, address 0x4005 0124) bit description

Bit Symbol Description Reset value

Access

15:0 NEWDAT32_17 0x00 R

31:16 -

New data bits of message objects 32 to 17.

0 = No new data has been written into the data portion of this Message Object by the Message

Handler since last time this flag was cleared by the

CPU.

1 = The Message Handler or the CPU has written new data into the data portion of this Message

Object.

Reserved -

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16.6.3.5 CAN interrupt pending 1 register

This register contains the INTPND bits of message objects 16 to 1. By reading out the

INTPND bits, the CPU can check for which Message Object an interrupt is pending. The

INTPND bit of a specific Message Object can be set/reset by the CPU via the IFx

Message Interface Registers or by the Message Handler after reception or after a successful transmission of a frame. This will also affect the value of INTPND in the

Interrupt Register.

Table 271. CAN interrupt pending 1 register (CANIR1, address 0x4005 0140) bit description

Bit Symbol Description Reset value

Access

15:0 INTPND16_1 0x00 R

31:16 -

Interrupt pending bits of message objects 16 to 1.

0 = This message object is ignored by the message handler.

1 = This message object is the source of an interrupt.

Reserved -

16.6.3.6 CAN interrupt pending 2 register

This register contains the INTPND bits of message objects 32 to 17. By reading out the

INTPND bits, the CPU can check for which Message Object an interrupt is pending. The

INTPND bit of a specific Message Object can be set/reset by the CPU via the IFx

Message Interface Registers or by the Message Handler after reception or after a successful transmission of a frame. This will also affect the value of INTPND in the

Interrupt Register.

Table 272. CAN interrupt pending 2 register (CANIR2, addresses 0x4005 0144) bit description

Bit Symbol Description

15:0 INTPND32_17

Reset value

0x00 Interrupt pending bits of message objects 32 to 17.

0 = This message object is ignored by the message handler.

1 = This message object is the source of an interrupt.

Access

R

31:16 Reserved -

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16.6.3.7 CAN message valid 1 register

This register contains the MSGVAL bits of message objects 16 to 1. By reading out the

MSGVAL bits, the CPU can check which Message Object is valid. The MSGVAL bit of a specific Message Object can be set/reset by the CPU via the IFx Message Interface

Registers.

Table 273. CAN message valid 1 register (CANMSGV1, addresses 0x4005 0160) bit description

Bit Symbol Description Reset value

Access

15:0 MSGVAL16_1 Message valid bits of message objects 16 to 1.

0 = This message object is ignored by the message handler.

1 = This message object is configured and should be considered by the message handler.

0x00 R

31:16 Reserved -

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16.6.3.8 CAN message valid 2 register

This register contains the MSGVAL bits of message objects 32 to 17. By reading out the

MSGVAL bits, the CPU can check which Message Object is valid. The MSGVAL bit of a specific Message Object can be set/reset by the CPU via the IFx Message Interface

Registers.

Table 274. CAN message valid 2 register (CANMSGV2, address 0x4005 0164) bit description

Bit Symbol Description Access Reset value

15:0 MSGVAL32_17 Message valid bits of message objects 32 to 17.

0 = This message object is ignored by the message handler.

1 = This message object is configured and should be considered by the message handler.

R 0x00

31:16 Reserved -

16.6.4 CAN timing register

16.6.4.1 CAN clock divider register

This register determines the CAN clock signal. The CAN_CLK is derived from the peripheral clock PCLK divided by the values in this register.

Table 275. CAN clock divider register (CANCLKDIV, address 0x4005 0180) bit description

Bit Symbol Description Reset value

Access

3:0 1 R/W

31:4 -

CLKDIVVAL Clock divider value. CAN_CLK =

PCLK/(CLKDIVVAL +1)

0000: CAN_CLK = PCLK divided by 1.

0001: CAN_CLK = PCLK divided by 2.

0010: CAN_CLK = PCLK divided by 3

0011: CAN_CLK = PCLK divided by 4.

...

1111: CAN_CLK = PCLK divided by 16.

reserved -

16.7 Functional description

16.7.1 C_CAN controller state after reset

After a hardware reset, the registers hold the values described in

Table 245 . Additionally,

the busoff state is reset and the output CAN_TXD is set to recessive (HIGH). The value

0x0001 (INIT = ‘1’) in the CAN Control Register enables the software initialization. The

CAN controller does not communicate with the CAN bus until the CPU resets INIT to ‘0’.

The data stored in the message RAM is not affected by a hardware reset. After power-on, the contents of the message RAM is undefined.

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Chapter 16: LPC111x/LPC11Cxx C_CAN controller

16.7.2 C_CAN operating modes

16.7.2.1 Software initialization

The software initialization is started by setting the bit INIT in the CAN Control Register, either by software or by a hardware reset, or by entering the busoff state.

During software initialization (INIT bit is set), the following conditions are present:

All message transfer from and to the CAN bus is stopped.

The status of the CAN output CAN_TXD is recessive (HIGH).

The EC counters are unchanged.

The configuration registers are unchanged.

Access to the bit timing register and the BRP extension register is enabled if the CCE bit in the CAN control register is also set.

To initialize the CAN controller, software has to set up the bit timing register and each message object. If a message object is not needed, it is sufficient to set its MSGVAL bit to not valid. Otherwise, the whole message object has to be initialized.

Resetting the INIT bit finishes the software initialization. Afterwards the Bit Stream

Processor BSP synchronizes itself to the data transfer on the CAN bus by waiting for the occurrence of a sequence of 11 consecutive recessive bits (Bus Idle) before it can take part in bus activities and starts the message transfer.

Remark:

The initialization of the Message Objects is independent of INIT and also can be done on the fly, but the Message Objects should all be configured to particular identifiers or set to not valid during software initialization before the BSP starts the message transfer.

To change the configuration of a Message Object during normal operation, the CPU has to start by setting the MSGVAL bit to not valid. When the configuration is completed,

MSAGVALis set to valid again.

16.7.2.2 CAN message transfer

Once the CAN controller is initialized and INIT is reset to zero, the CAN core synchronizes itself to the CAN bus and starts the message transfer.

Received messages are stored into their appropriate Message Objects if they pass the

Message Handler’s acceptance filtering. The whole message including all arbitration bits,

DLC and eight data bytes is stored into the Message Object. If the Identifier Mask is used, the arbitration bits which are masked to “don’t care” may be overwritten in the Message

Object.

The CPU may read or write each message any time via the Interface Registers. The

Message Handler guarantees data consistency in case of concurrent accesses.

Messages to be transmitted are updated by the CPU. If a permanent Message Object

(arbitration and control bits set up during configuration) exists for the message, only the data bytes are updated and then TXRQST bit with NEWDAT bit are set to start the transmission. If several transmit messages are assigned to the same Message Object

(when the number of Message Objects is not sufficient), the whole Message Object has to be configured before the transmission of this message is requested.

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The transmission of any number of Message Objects may be requested at the same time, and they are transmitted subsequently according to their internal priority. Messages may be updated or set to not valid any time, even when their requested transmission is still pending. The old data will be discarded when a message is updated before its pending transmission has started.

Depending on the configuration of the Message Object, the transmission of a message may be requested autonomously by the reception of a remote frame with a matching identifier.

16.7.2.3 Disabled Automatic Retransmission (DAR)

According to the

CAN Specification (ISO11898, 6.3.3 Recovery Management)

, the CAN controller provides means for automatic retransmission of frames that have lost arbitration or that have been disturbed by errors during transmission. The frame transmission service will not be confirmed to the user before the transmission is successfully completed. By default, the automatic retransmission on lost arbitration or error is enabled. It can be disabled to enable the CAN controller to work within a Time Triggered CAN (TTCAN, see

ISO11898-1) environment.

The Disable Automatic Retransmission mode is enabled by programming bit DAR in the

CAN Control Register to one. In this operation mode the programmer has to consider the different behavior of bits TXRQST and NEWDAT in the Control Registers of the Message

Buffers:

When a transmission starts, bit TXRQST of the respective Message Buffer is reset while bit NEWDAT remains set.

When the transmission completed successfully, bit NEWDAT is reset.

When a transmission failed (lost arbitration or error), bit NEWDAT remains set. To restart the transmission, the CPU has to set TXRQST back to one.

16.7.2.4 Test modes

The Test mode is entered by setting bit TEST in the CAN Control Register to one. In Test mode the bits TX[1:0], TX0, LBACK, SILENT, and BASIC in the Test Register are writable.

Bit RX monitors the state of pin CAN_RXD and therefore is only readable. All Test register functions are disabled when bit TEST is reset to zero.

16.7.2.4.1

Silent mode

The CAN core can be set in Silent mode by programming the Test register bit SILENT to one.

In Silent Mode, the CAN controller is able to receive valid data frames and valid remote frames, but it sends only recessive bits on the CAN bus, and it cannot start a transmission. If the CAN Core is required to send a dominant bit (ACK bit, overload flag, active error flag), the bit is rerouted internally so that the CAN Core monitors this dominant bit, although the CAN bus may remain in recessive state. The Silent mode can be used to analyze the traffic on a CAN bus without affecting it by the transmission of dominant bits

(Acknowledge Bits, Error Frames).

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C_CAN

CAN_TXD CAN_RXD

= 1

Rx Tx

CAN CORE

Fig 62. CAN core in Silent mode

16.7.2.4.2

Loop-back mode

The CAN Core can be set in Loop-back mode by programming the Test Register bit

LBACK to one. In Loop-back Mode, the CAN Core treats its own transmitted messages as received messages and stores them (if they pass acceptance filtering) into a Receive

Buffer.

This mode is provided for self-test functions. To be independent from external stimulation, the CAN Core ignores acknowledge errors (recessive bit sampled in the acknowledge slot of a data/remote frame) in Loop-back mode. In this mode the CAN core performs an internal feedback from its CAN_TXD output to its CAN_RXD input. The actual value of the

CAN_RXD input pin is disregarded by the CAN Core. The transmitted messages can be monitored at the CAN_TXD pin.

CAN_TXD CAN_RXD

C_CAN

Rx Tx

CAN CORE

Fig 63. CAN core in Loop-back mode

16.7.2.4.3

Loop-back mode combined with Silent mode

It is also possible to combine Loop-back mode and Silent mode by programming bits

LBACK and SILENT to one at the same time. This mode can be used for a “Hot Selftest”, meaning the C_CAN can be tested without affecting a running CAN system connected to the pins CAN_TXD and CAN_RXD. In this mode the CAN_RXD pin is disconnected from the CAN Core and the CAN_TXD pin is held recessive.

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CAN_TXD CAN_RXD

C_CAN

= 1

Rx Tx

CAN CORE

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Fig 64. CAN core in Loop-back mode combined with Silent mode

16.7.2.4.4

Basic mode

The CAN Core can be set in Basic mode by programming the Test Register bit BASIC to one. In this mode the CAN controller runs without the Message RAM.

The IF1 Registers are used as Transmit Buffer. The transmission of the contents of the

IF1 Registers is requested by writing the BUSY bit of the IF1 Command Request Register to ‘1’. The IF1 Registers are locked while the BUSY bit is set. The BUSY bit indicates that the transmission is pending.

As soon the CAN bus is idle, the IF1 Registers are loaded into the shift register of the CAN

Core and the transmission is started. When the transmission has completed, the BUSY bit is reset and the locked IF1 Registers are released.

A pending transmission can be aborted at any time by resetting the BUSY bit in the IF1

Command Request Register while the IF1 Registers are locked. If the CPU has reset the

BUSY bit, a possible retransmission in case of lost arbitration or in case of an error is disabled.

The IF2 Registers are used as Receive Buffer. After the reception of a message the contents of the shift register is stored into the IF2 Registers, without any acceptance filtering.

Additionally, the actual contents of the shift register can be monitored during the message transfer. Each time a read Message Object is initiated by writing the BUSY bit of the IF2

Command Request Register to ‘1’, the contents of the shift register is stored into the IF2

Registers.

In Basic mode the evaluation of all Message Object related control and status bits and of the control bits of the IFx Command Mask Registers is turned off. The message number of the Command request registers is not evaluated. The NEWDAT and MSGLST bits of the

IF2 Message Control Register retain their function, DLC3-0 will show the received DLC, the other control bits will be read as ‘0’.

In Basic mode the ready output CAN_WAIT_B is disabled (always ‘1’)

16.7.2.4.5

Software control of pin CAN_TXD

Four output functions are available for the CAN transmit pin CAN_TXD:

1. serial data output (default).

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2. drives CAN sample point signal to monitor the CAN controller’s timing.

3. drives recessive constant value.

4. drives dominant constant value.

The last two functions, combined with the readable CAN receive pin CAN_RXD, can be used to check the CAN bus’ physical layer.

The output mode of pin CAN_TXD is selected by programming the Test Register bits TX1 and TX0 as described

Section 16.6.1.6

.

Remark:

The three test functions for pin CAN_TXD interfere with all CAN protocol functions. The CAN_TXD pin must be left in its default function when CAN message transfer or any of the test modes Loo-back mode, Silent mode, or Basic mode are selected.

16.7.3 CAN message handler

The Message handler controls the data transfer between the Rx/Tx Shift Register of the

CAN Core, the Message RAM and the IFx Registers, see Figure 65

.

The message handler controls the following functions:

Data Transfer between IFx Registers and the Message RAM

Data Transfer from Shift Register to the Message RAM

Data Transfer from Message RAM to Shift Register

Data Transfer from Shift Register to the Acceptance Filtering unit

Scanning of Message RAM for a matching Message Object

Handling of TXRQST flags

Handling of interrupts

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transfer a message object

INTERFACE

COMMAND REGISTERS

IF1 COMMAND REQUEST

IF1 COMMAND MASK

IF2 COMMAND REQUEST

IF2 COMMAND MASK

MESSAGE BUFFER

REGISTERS

IF1 MASK1, 2

IF1 ARBITRATION 1/2

IF1 MESSAGE CTRL

IF1 DATA A1/2

IF1 DATA B1/2

IF2 MASK1, 2

IF2 ARBITRATION 1/2

IF2 MESSAGE CTRL

IF2 DATA A1/2

IF2 DATA B1/2 read transfer write transfer

MESSAGE RAM

MESSAGE OBJECT 1

MESSAGE OBJECT 2

.

.

.

MESSAGE OBJECT 32

MESSAGE HANDLER

TRANSMISSION REQUEST 1/2

NEW DATA 1/2

INTERRUPT PENDING1/2

MESSAGE VALID1/2 transfer a

CAN frame receive

CAN CORE/

SHIFT REGISTERS transmit

CAN bus

Fig 65. Block diagram of a message object transfer

16.7.3.1 Management of message objects

The configuration of the Message Objects in the Message RAM will (with the exception of the bits MSGVAL, NEWDAT, INTPND, and TXRQST) is not be affected by resetting the chip. All the Message Objects must be initialized by the CPU or they must be set to not valid (MSGVAL = ‘0’).The bit timing must be configured before the CPU clears the INIT bit in the CAN Control Register.

The configuration of a Message Object is done by programming Mask, Arbitration, Control and Data field of one of the two interface register sets to the desired values. By writing to the corresponding IFx Command Request Register, the IFx Message Buffer Registers are loaded into the addressed Message Object in the Message RAM.

When the INIT bit in the CAN Control Register is cleared, the CAN Protocol Controller state machine of the CAN core and the Message Handler State Machine control the CAN controller’s internal data flow. Received messages that pass the acceptance filtering are stored into the Message RAM, and messages with pending transmission request are loaded into the CAN core’s shift register and are transmitted via the CAN bus.

The CPU reads received messages and updates messages to be transmitted via the IFx

Interface Registers. Depending on the configuration, the CPU is interrupted on certain

CAN message and CAN error events.

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16.7.3.2 Data Transfer between IFx Registers and the Message RAM

When the CPU initiates a data transfer between the IFx Registers and Message RAM, the

Message Handler sets the BUSY bit in the respective Command Register to ‘1’. After the transfer has completed, the BUSY bit is set back to ‘0’.

The Command Mask Register specifies whether a complete Message Object or only parts of it will be transferred. Due to the structure of the Message RAM it is not possible to write single bits/bytes of one Message Object. Software must always write a complete Message

Object into the Message RAM. Therefore the data transfer from the IFx Registers to the

Message RAM requires a read-modify-write cycle:

1. Read the parts of the message object that are not to be changed from the message

RAM using the command mask register.

After the partial read of a Message Object, the Message Buffer Registers that are not selected in the Command Mask Register will be left unchanged.

2. Write the complete contents of the message buffer registers into the message object.

After the partial write of a Message Object, the Message Buffer Registers that are not selected in the Command Mask Register will set to the actual contents of the selected Message Object.

16.7.3.3 Transmission of messages between the shift registers in the CAN core and the Message buffer

If the shift register of the CAN Core cell is ready for loading and if there is no data transfer between the IFx Registers and Message RAM, the MSGVAL bits in the Message Valid

Register TXRQST bits in the Transmission Request Register are evaluated. The valid

Message Object with the highest priority pending transmission request is loaded into the shift register by the Message Handler and the transmission is started. The Message

Object’s NEWDAT bit is reset.

After a successful transmission and if no new data was written to the Message Object

(NEWDAT = ‘0’) since the start of the transmission, the TXRQST bit will be reset. If TXIE is set, INTPND will be set after a successful transmission. If the CAN controller has lost the arbitration or if an error occurred during the transmission, the message will be retransmitted as soon as the CAN bus is free again. If meanwhile the transmission of a message with higher priority has been requested, the messages will be transmitted in the order of their priority.

16.7.3.4 Acceptance filtering of received messages

When the arbitration and control field (Identifier + IDE + RTR + DLC) of an incoming message is completely shifted into the Rx/Tx Shift Register of the CAN Core, the

Message Handler state machine starts the scanning of the Message RAM for a matching valid Message Object.

To scan the Message RAM for a matching Message Object, the Acceptance Filtering unit is loaded with the arbitration bits from the CAN Core shift register. Then the arbitration and mask fields (including MSGVAL, UMASK, NEWDAT, and EOB) of Message Object 1 are loaded into the Acceptance Filtering unit and compared with the arbitration field from the shift register. This is repeated with each following Message Object until a matching

Message Object is found or until the end of the Message RAM is reached.

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If a match occurs, the scanning is stopped and the Message Handler state machine proceeds depending on the type of frame (Data Frame or Remote Frame) received.

16.7.3.4.1

Reception of a data frame

The Message Handler state machine stores the message from the CAN Core shift register into the respective Message Object in the Message RAM. The data bytes, all arbitration bits, and the Data Length Code are stored into the corresponding Message Object. This is implemented to keep the data bytes connected with the identifier even if arbitration mask registers are used.

The NEWDAT bit is set to indicate that new data (not yet seen by the CPU) has been received. The CPU/software should reset NEWDAT when it reads the Message Object. If at the time of the reception the NEWDAT bit was already set, MSGLST is set to indicate that the previous data (supposedly not seen by the CPU) is lost. If the RxIE bit is set, the

INTPND bit is also set, causing the Interrupt Register to point to this Message Object.

The TXRQST bit of this Message Object is reset to prevent the transmission of a Remote

Frame, while the requested Data Frame has just been received.

16.7.3.4.2

Reception of a remote frame

When a Remote Frame is received, three different configurations of the matching

Message Object have to be considered:

1. DIR = ‘1’ (direction = transmit), RMTEN = ‘1’, UMASK = ‘1’ or’0’

On the reception of a matching Remote Frame, the TXRQST bit of this Message

Object is set. The rest of the Message Object remains unchanged.

2. DIR = ‘1’ (direction = transmit), RMTEN = ‘0’, UMASK = ’0’

On the reception of a matching Remote Frame, the TXRQST bit of this Message

Object remains unchanged; the Remote Frame is ignored.

3. DIR = ‘1’ (direction = transmit), RMTEN = ‘0’, UMASK = ’1’

On the reception of a matching Remote Frame, the TXRQST bit of this Message

Object is reset. The arbitration and control field (Identifier + IDE + RTR + DLC) from the shift register is stored into the Message Object in the Message RAM, and the

NEWDAT bit of this Message Object is set. The data field of the Message Object remains unchanged; the Remote Frame is treated similar to a received Data Frame.

16.7.3.5 Receive/transmit priority

The receive/transmit priority for the Message Objects is attached to the message number.

Message Object 1 has the highest priority, while Message Object 32 has the lowest priority. If more than one transmission request is pending, they are serviced due to the priority of the corresponding Message Object.

16.7.3.6 Configuration of a transmit object

Table 276 shows how a transmit object should be initialized by software (see also

Table 254 ):

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Table 276. Initialization of a transmit object

MSGVAL Arbitration bits

Data bits Mask bits

1

MSGLST

0 application dependent

RXIE

0 application dependent

TXIE

application dependent application dependent

INTPND

0

EOB

1

RMTEN

application dependent

DIR

1

NEWDAT

TXRQST

0

0

The Arbitration Registers (ID28:0 and XTD bit) are given by the application. They define the identifier and the type of the outgoing message. If an 11-bit Identifier (“Standard

Frame”) is used, it is programmed to ID28. In this case ID18, ID17 to ID0 can be disregarded.

If the TXIE bit is set, the INTPND bit will be set after a successful transmission of the

Message Object.

If the RMTEN bit is set, a matching received Remote Frame will cause the TXRQST bit to be set, and the Remote Frame will autonomously be answered by a Data Frame.

The Data Registers (DLC3:0, Data0:7) are given by the application. TXRQST and RMTEN may not be set before the data is valid.

The Mask Registers (Msk28-0, UMASK, MXTD, and MDIR bits) may be used

(UMASK=’1’) to allow groups of Remote Frames with similar identifiers to set the TXRQST

bit. For details see Section 16.7.3.4.2

. The DIR bit should not be masked.

16.7.3.7 Updating a transmit object

The CPU may update the data bytes of a Transmit Object any time via the IFx Interface registers. Neither MSGVAL nor TXRQST have to be reset before the update.

Even if only a part of the data bytes are to be updated, all four bytes of the corresponding

IFx Data A Register or IFx Data B Register have to be valid before the content of that register is transferred to the Message Object. Either the CPU has to write all four bytes into the IFx Data Register or the Message Object is transferred to the IFx Data Register before the CPU writes the new data bytes.

When only the (eight) data bytes are updated, first 0x0087 is written to the Command

Mask Register. Then the number of the Message Object is written to the Command

Request Register, concurrently updating the data bytes and setting TXRQST.

To prevent the reset of TXRQST at the end of a transmission that may already be in progress while the data is updated, NEWDAT has to be set together with TXRQST. For

details see Section 16.7.3.3

.

When NEWDAT is set together with TXRQST, NEWDAT will be reset as soon as the new transmission has started.

16.7.3.8 Configuration of a receive object

Table 277 shows how a receive object should be initialized by software (see also

Table 254 )

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Table 277. Initialization of a receive object

MSGVAL Arbitration bits

Data bits Mask bits

1

MSGLST

0 application dependent

RXIE

application dependent application dependent

TXIE

0 application dependent

INTPND

0

EOB

1

RMTEN

0

DIR

0

NEWDAT

TXRQST

0

0

The Arbitration Registers (ID28-0 and XTD bit) are given by the application. They define the identifier and type of accepted received messages. If an 11-bit Identifier (“Standard

Frame”) is used, it is programmed to ID[28:18]. ID17 to ID0 can then be disregarded.

When a Data Frame with an 11-bit Identifier is received, ID17 to ID0 will be set to ‘0’.

If the RxIE bit is set, the INTPND bit will be set when a received Data Frame is accepted and stored in the Message Object.

The Data Length Code (DLC[3:0] is given by the application. When the Message Handler stores a Data Frame in the Message Object, it will store the received Data Length Code and eight data bytes. If the Data Length Code is less than 8, the remaining bytes of the

Message Object will be overwritten by non specified values.

The Mask Registers (Msk[28:0], UMASK, MXTD, and MDIR bits) may be used

(UMASK=’1’) to allow groups of Data Frames with similar identifiers to be accepted. For

details see section Section 16.7.3.4.1

. The DIR bit should not be masked in typical

applications.

16.7.3.9 Handling of received messages

The CPU may read a received message any time via the IFx Interface registers. The data consistency is guaranteed by the Message Handler state machine.

To transfer the entire received message from message RAM into the message buffer, software must write first 0x007F to the Command Mask Register and then the number of the Message Object to the Command Request Register. Additionally, the bits NEWDAT and INTPND are cleared in the Message RAM (not in the Message Buffer).

If the Message Object uses masks for acceptance filtering, the arbitration bits show which of the matching messages has been received.

The actual value of NEWDAT shows whether a new message has been received since last time this Message Object was read. The actual value of MSGLST shows whether more than one message has been received since last time this Message Object was read.

MSGLST will not be automatically reset.

Using a Remote Frame, the CPU may request another CAN node to provide new data for a receive object. Setting the TXRQST bit of a receive object will cause the transmission of a Remote Frame with the receive object’s identifier. This Remote Frame triggers the other

CAN node to start the transmission of the matching Data Frame. If the matching Data

Frame is received before the Remote Frame could be transmitted, the TXRQST bit is automatically reset.

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16.7.3.10 Configuration of a FIFO buffer

With the exception of the EOB bit, the configuration of Receive Objects belonging to a

FIFO Buffer is the same as the configuration of a (single) Receive Object, see section

Section 16.7.3.8

.

To concatenate two or more Message Objects into a FIFO Buffer, the identifiers and masks (if used) of these Message Objects have to be programmed to matching values.

Due to the implicit priority of the Message Objects, the Message Object with the lowest number will be the first Message Object of the FIFO Buffer. The EOB bit of all Message

Objects of a FIFO Buffer except the last have to be programmed to zero. The EOB bits of the last Message Object of a FIFO Buffer is set to one, configuring it as the End of the

Block.

16.7.3.10.1

Reception of messages with FIFO buffers

Received messages with identifiers matching to a FIFO Buffer are stored into a Message

Object of this FIFO Buffer starting with the Message Object with the lowest message number.

When a message is stored into a Message Object of a FIFO Buffer the NEWDAT bit of this

Message Object is set. By setting NEWDAT while EOB is zero the Message Object is locked for further write accesses by the Message Handler until the CPU has written the

NEWDAT bit back to zero.

Messages are stored into a FIFO Buffer until the last Message Object of this FIFO Buffer is reached. If none of the preceding Message Objects is released by writing NEWDAT to zero, all further messages for this FIFO Buffer will be written into the last Message Object of the FIFO Buffer and therefore overwrite previous messages.

16.7.3.10.2

Reading from a FIFO buffer

When the CPU transfers the contents of Message Object to the IFx Message Buffer registers by writing its number to the IFx Command Request Register, bits NEWDAT and

INTPND in the corresponding Command Mask Register should be reset to zero

(TXRQST/NEWDAT = ‘1’ and ClrINTPND = ‘1’). The values of these bits in the Message

Control Register always reflect the status before resetting the bits.

To assure the correct function of a FIFO Buffer, the CPU should read out the Message

Objects starting at the FIFO Object with the lowest message number.

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START read CANIR

INTID = 0x8000 ?

yes status change interrupt handling

INTID = 0x0001

to 0x0020 ?

yes

MessageNum = INTID

INTID = 0x0000 ?

END yes write MessageNum to CANIFx_CMDREQ read message to message buffer reset NEWDAT = 0 reset INTPND = 0 read CANIFx_MCTRL no

NEWDAT = 1 yes read data from CANIFx_DA/B yes

EOB = 1 no

MessageNum = MessageNum +1

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Fig 66. Reading a message from the FIFO buffer to the message buffer

16.7.4 Interrupt handling

If several interrupts are pending, the CAN Interrupt Register will point to the pending interrupt with the highest priority, disregarding their chronological order. An interrupt remains pending until the CPU has cleared it.

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The Status Interrupt has the highest priority. Among the message interrupts, the Message

Object’s interrupt priority decreases with increasing message number.

A message interrupt is cleared by clearing the Message Object’s INTPND bit. The Status

Interrupt is cleared by reading the Status Register.

The interrupt identifier INTID in the Interrupt Register indicates the cause of the interrupt.

When no interrupt is pending, the register will hold the value zero. If the value of the

Interrupt Register is different from zero, then there is an interrupt pending and, if IE is set, the interrupt line to the CPU, IRQ_B, is active. The interrupt line remains active until the

Interrupt Register is back to value zero (the cause of the interrupt is reset) or until IE is reset.

The value 0x8000 indicates that an interrupt is pending because the CAN Core has updated (not necessarily changed) the Status Register (Error Interrupt or Status Interrupt).

This interrupt has the highest priority. The CPU can update (reset) the status bits RXOK,

TXOK and LEC, but a write access of the CPU to the Status Register can never generate or reset an interrupt.

All other values indicate that the source of the interrupt is one of the Message Objects where INTID points to the pending message interrupt with the highest interrupt priority.

The CPU controls whether a change of the Status Register may cause an interrupt (bits

EIE and SIE in the CAN Control Register) and whether the interrupt line becomes active when the Interrupt Register is different from zero (bit IE in the CAN Control Register). The

Interrupt Register will be updated even when IE is reset.

The CPU has two possibilities to follow the source of a message interrupt:

Software can follow the INTID in the Interrupt Register.

Software can poll the interrupt pending register, see Section 16.6.3.5

.

An interrupt service routine reading the message that is the source of the interrupt may read the message and reset the Message Object’s INTPND at the same time (bit

ClrINTPND in the Command Mask Register). When INTPND is cleared, the Interrupt

Register will point to the next Message Object with a pending interrupt.

16.7.5 Bit timing

Even if minor errors in the configuration of the CAN bit timing do not result in immediate failure, the performance of a CAN network can be reduced significantly. In many cases, the CAN bit synchronization will amend a faulty configuration of the CAN bit timing to such a degree that only occasionally an error frame is generated. In the case of arbitration however, when two or more CAN nodes simultaneously try to transmit a frame, a misplaced sample point may cause one of the transmitters to become error passive.

The analysis of such sporadic errors requires a detailed knowledge of the CAN bit synchronization inside a CAN node and of the CAN nodes’ interaction on the CAN bus.

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16.7.5.1 Bit time and bit rate

CAN supports bit rates in the range of lower than 1 kBit/s up to 1000 kBit/s. Each member of the CAN network has its own clock generator, usually a quartz oscillator. The timing parameter of the bit time (i.e. the reciprocal of the bit rate) can be configured individually for each CAN node, creating a common bit rate even though the CAN nodes’ oscillator periods (f osc

) may be different.

The frequencies of these oscillators are not absolutely stable, as small variations are caused by changes in temperature or voltage and by deteriorating components. As long as the variations remain inside a specific oscillator tolerance range (df), the CAN nodes are able to compensate for the different bit rates by re-synchronizing to the bit stream.

According to the CAN specification, the bit time is divided into four segments ( Figure 67 ).

The Synchronization Segment, the Propagation Time Segment, the Phase Buffer

Segment 1, and the Phase Buffer Segment 2. Each segment consists of a specific, programmable number of time quanta (see

Table 278 ). The length of the time quantum

(t q

), which is the basic time unit of the bit time, is defined by the CAN controller’s system clock f and the Baud Rate Prescaler (BRP): t q

= BRP / f sys

. The C_CAN’s system clock f sys is the frequency of the LPC11Cx system clock (see

Section 16.2

).

The Synchronization Segment Sync_Seg is the part of the bit time where edges of the

CAN bus level are expected to occur; the distance between an edge that occurs outside of

Sync_Seg and the Sync_Seg is called the phase error of that edge. The Propagation

Time Segment Prop_Seg is intended to compensate for the physical delay times within the CAN network. The Phase Buffer Segments Phase_Seg1 and Phase_Seg2 surround the Sample Point. The (Re-)Synchronization Jump Width (SJW) defines how far a re-synchronization may move the Sample Point inside the limits defined by the Phase

Buffer Segments to compensate for edge phase errors.

Table 278 describes the minimum programmable ranges required by the CAN protocol.

Bit time parameters are programmed through the CANBT register, Table 249

. For details on bit timing and examples, see the

C_CAN user’s manual, revision 1.2

.

Table 278. Parameters of the C_CAN bit time

Parameter Range Function

BRP

SYNC_SEG

PROP_SEG

(1...32)

1t q

(1...8)

t q

Defines the length of the time quantum t

Synchronization segment. Fixed length. Synchronization of bus input to system clock.

q

.

Propagation time segment. Compensates for physical delay times. This parameter is determined by the system delay times in the C_CAN network.

PHASE_SEG1 (1...8)

t q

PHASE_SEG2

(TSEG2)

SJW

(1...8)

(1...4)

t

t q q

Phase buffer segment 1. May be lengthened temporarily by synchronization.

Phase buffer segment 2. May be shortened temporarily by synchronization.

(Re-) synchronization jump width. May not be longer than either phase buffer segment.

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TSEG1

PHASE_SEG1

TSEG2

PHASE_SEG2

Fig 67. Bit timing

16.7.5.2 Calculating the C_CAN bit rate

The C_CAN clock is derived from the system clock. The C_CAN clock can be divided by

the C_CAN clock divider ( Table 275

): CAN_CLK = system clock/ (DIVVAL +1).

Using Figure 67

and

Table 278 , the bit rate and sample point can be expressed as follows

using t q

= BRP / CAN_CLK:

Bit rate = 1/(t q

x total number of quantas) = 1 / (t q

x (1 + PROP_SEG+TSEG1+TSEG2)) =

CAN_CLK / (BRP x (1 + PROP_SEG+TSEG1+TSEG2))

Sample point = (1 + PROP_SEG+TSEG1) / (1 + PROP_SEG+TSEG1+TSEG2) x 100

The CAN BT register (see

Table 249 ) stores the bit timing information for parameters BRP

(bits 5:0), PROP_SEG +TSEG1 (bits 11:8, named TSEG1), and TSEG2. Note that the register content are +1 encoded.

Using the contents of the BT register for BRP, TSEG1, and TSEG2, the bit rate can be calculated as follows:

Bit rate = CAN_CLK/((BRP + 1) x (TSEG1+2+TSEG2+1))

Sample point = (TSEG1+2) / (TSEG1+2+TSEG2+1) x 100

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17.1 How to read this chapter

The C_CAN block is available in LPC11Cxx parts only (LPC11C00 series).

17.2 Features

The on-chip drivers are stored in boot ROM and offer CAN and CANopen initialization and communication features to user applications via a defined API. The following functions are included in the API:

CAN set-up and initialization

CAN send and receive messages

CAN status

CANopen Object Dictionary

CANopen SDO expedited communication

CANopen SDO segmented communication primitives

CANopen SDO fall-back handler

17.3 General description

In addition to the CAN ISP, the boot ROM provides a CAN and CANopen API to simplify

CAN application development. It covers initialization, configuration, basic CAN send/receive as well as a CANopen SDO interface. Callback functions are available to process receive events.

17.3.1 Differences to fully-compliant CANopen

While the bootloader uses the SDO communication protocol and the Object Dictionary data organization method, it is not a fully CiA 301 standard compliant CANopen node. In particular, the following features are not available or different to the standard:

No Network Management (NMT) message processing.

No Heartbeat Message, no entry 0x1017.

Uses proprietary SDO Abort Codes to indicate device errors

“Empty” SDO responses during SDO segmented download/write to the node are shortened to one data byte, rather than full eight data bytes as the standard describes. This to speed up the communication.

Entry [1018h,1] Vendor ID reads 0x0000 0000 rather than an official CiA-assigned unique Vendor ID. This in particular because the chip will be incorporated into designs of customers who will become the “vendor” of the whole device. The host will have to use a different method to identify the CAN ISP devices.

The maximum OD entries allowed is 255.

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17.4 API description

17.4.1 Calling the C_CAN API

A fixed location in ROM contains a pointer to the ROM driver table i.e. 0x1FFF 1FF8. This location is the same for all LPC11Cxx parts. The ROM driver table contains pointer to the

CAN API table. Pointers to the various CAN API functions are stored in this table. CAN

API functions can be called by using a C structure.

Figure 68

illustrates the pointer mechanism used to access the on-chip CAN API. On-chip

RAM from address 0x1000 0050 to 0x1000 00B8 is used by the CAN API. This address range should not be used by the application. For applications using the on-chip CAN API, the linker control file should be modified appropriately to prevent usage of this area for application’s variable storage.

0x1FFF 1FF8

0x1FFF 1FFC

0x1FFF 2000

ROM Driver Table

Ptr to Device Table 0

Ptr to Device Table 1

Ptr to C_CAN API Table

Ptr to Device Table n

C_CAN API

Device n isr config_rxmsgobj can_receive can_transmit config_canopen canopen_handler config_calb init_can

Ptr to Function 0

Ptr to Function 1

Ptr to Function 2

Ptr to Function n

Fig 68. CAN API pointer structure

In C, the structure with the function list that is referenced to call the API functions looks as follows: typedef struct _CAND {

void (*init_can) (uint32_t * can_cfg, uint8_t isr_ena);

void (*isr) (void);

void (*config_rxmsgobj) (CAN_MSG_OBJ * msg_obj);

uint8_t (*can_receive) (CAN_MSG_OBJ * msg_obj);

void (*can_transmit) (CAN_MSG_OBJ * msg_obj);

void (*config_canopen) (CAN_CANOPENCFG * canopen_cfg);

void (*canopen_handler) (void);

void (*config_calb) (CAN_CALLBACKS * callback_cfg);

} CAND;

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17.4.2 CAN initialization

The CAN controller clock divider, the CAN bit rate is set, and the CAN controller is initialized based on an array of register values that are passed on via a pointer.

void init_can (uint32_t * can_cfg, uint8_t isr_ena)

The first 32-bit value in the array is applied to the CANCLKDIV register, the second value is applied to the CAN_BTR register.

The second parameter enables interrupts on the CAN controller level. Set to FALSE for polled communication.

Example call:

ROM **rom = (ROM **)(0x1fff1ff8); uint32_t CanApiClkInitTable[2] = {

0x00000000UL, // CANCLKDIV

0x00004DC5UL // CAN_BTR

};

(*rom)->pCAND->init_can(&CanApiCanInitTable[0], 1);

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17.4.3 CAN interrupt handler

When the user application is active, the interrupt handlers are mapped in the user flash space. The user application must provide an interrupt handler for the CAN interrupt. In order to process CAN events and call the callback functions the application must call the

CAN API interrupt handler directly from the interrupt handler routine. The CAN API interrupt handler takes appropriate action according to the data received and the status detected on the CAN bus.

void isr (void)

The CAN interrupt handler does not process CANopen messages.

Example call:

(*rom)->pCAND->isr();

For polled communication, the interrupt handler may be called manually as often as required. The callback functions for receive, transmit, and error will be executed as described and on the same level the interrupt handler was called from.

17.4.4 CAN Rx message object configuration

The CAN API supports and uses the full CAN model with 32 message objects. Any of the message objects can be used for receive or transmit of either 11-bit or 29-bit CAN messages. CAN messages that have their RTR-bit set (remote transmit) are also supported. For receive objects, a mask pattern for the message identifier allows to receive ranges of messages, up to receiving all CAN messages on the bus in a single message object. See also

Section 16.7.3.4

.

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Transmit message objects are automatically configured when used.

// control bits for CAN_MSG_OBJ.mode_id

#define CAN_MSGOBJ_STD 0x00000000UL // CAN 2.0a 11-bit ID

#define CAN_MSGOBJ_EXT 0x20000000UL // CAN 2.0b 29-bit ID

#define CAN_MSGOBJ_DAT 0x00000000UL // data frame

#define CAN_MSGOBJ_RTR 0x40000000UL // rtr frame typedef struct _CAN_MSG_OBJ {

uint32_t mode_id;

uint32_t mask;

uint8_t data[8];

uint8_t dlc;

uint8_t msgobj;

} CAN_MSG_OBJ; void config_rxmsgobj (CAN_MSG_OBJ * msg_obj)

Example call:

// Configure message object 1 to receive all 11-bit messages 0x000-0x00F msg_obj.msgobj = 1; msg_obj.mode_id = 0x000; msg_obj.mask = 0x7F0;

(*rom)->pCAND-> config_rxmsgobj(&msg_obj);

17.4.5 CAN receive

The CAN receive function allows reading messages that have been received by an Rx message object. A pointer to a message object structure is passed to the receive function.

Before calling, the number of the message object that is to be read has to be set in the structure.

void config_rxmsgobj (CAN_MSG_OBJ * msg_obj)

Example call:

// Read out received message msg_obj.msgobj = 5;

(*rom)->pCAND->can_receive(&msg_obj);

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17.4.6 CAN transmit

The CAN transmit function allows setting up a message object and triggering the transmission of a CAN message on the bus. 11-bit standard and 29-bit extended messages are supported as well as both standard data and remote-transmit (RTR) messages.

void config_txmsgobj (CAN_MSG_OBJ * msg_obj)

Example call: msg_obj.msgobj = 3; msg_obj.mode_id = 0x123UL;

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msg_obj.mask = 0x0UL; msg_obj.dlc = 1; msg_obj.data[0] = 0x00;

(*rom)->pCAND->can_transmit(&msg_obj);

17.4.7 CANopen configuration

The CAN API supports an Object Dictionary interface and the SDO protocol. In order to activate it, the CANopen configuration function has to be called with a pointer to a structure with the CANopen Node ID (1...127), the message object numbers to use for receive and transmit SDOs, a flag to decide whether the CANopen SDO handling should happen in the interrupt serving function automatically or via the dedicated API function, and two pointers to Object Dictionary configuration tables and their sizes. One table contains all read-only, constant entries of four bytes or less. The second table contains all variable and writable entries as well as SDO segmented entries.

typedef struct _CAN_ODCONSTENTRY {

uint16_t index;

uint8_t subindex;

uint8_t len;

uint32_t val;

} CAN_ODCONSTENTRY;

// upper-nibble values for CAN_ODENTRY.entrytype_len

#define OD_NONE 0x00 // Object Dictionary entry doesn't exist

#define OD_EXP_RO 0x10 // Object Dictionary entry expedited, read-only

#define OD_EXP_WO 0x20 // Object Dictionary entry expedited, write-only

#define OD_EXP_RW 0x30 // Object Dictionary entry expedited, read-write

#define OD_SEG_RO 0x40 // Object Dictionary entry segmented, read-only

#define OD_SEG_WO 0x50 // Object Dictionary entry segmented, write-only

#define OD_SEG_RW 0x60 // Object Dictionary entry segmented, read-write typedef struct _CAN_ODENTRY { uint16_t index; uint8_t subindex; uint8_t entrytype_len; unint8_t isr_handled; uint8_t *val;

} CAN_ODENTRY; typedef struct _CAN_CANOPENCFG { uint8_t node_id; uint8_t msgobj_rx; uint8_t msgobj_tx;

uint8_t isr_handled; uint32_t od_const_num;

CAN_ODCONSTENTRY *od_const_table; uint32_t od_num;

CAN_ODENTRY *od_table;

} CAN_CANOPENCFG;

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Example OD tables and CANopen configuration structure:

// List of fixed, read-only Object Dictionary (OD) entries

// Expedited SDO only, length=1/2/4 bytes const CAN_ODCONSTENTRY myConstOD [] = {

// index subindex length value

{ 0x1000, 0x00, 4, 0x54534554UL }, // "TEST"

{ 0x1018, 0x00, 1, 0x00000003UL },

{ 0x1018, 0x01, 4, 0x00000003UL },

{ 0x2000, 0x00, 1, (uint32_t)'M' },

};

// List of variable OD entries

// Expedited SDO with length=1/2/4 bytes

// Segmented SDO application-handled with length and value_pointer don't care const CAN_ODENTRY myOD [] = {

// index subindex access_type|length value_pointer

{ 0x1001, 0x00, OD_EXP_RO | 1, (uint8_t *)&error_register },

{ 0x1018, 0x02, OD_EXP_RO | 4, (uint8_t *)&device_id },

{ 0x1018, 0x03, OD_EXP_RO | 4, (uint8_t *)&fw_ver },

{ 0x2001, 0x00, OD_EXP_RW | 2, (uint8_t *)&param },

{ 0x2200, 0x00, OD_SEG_RW, (uint8_t *)NULL },

};

// CANopen configuration structure const CAN_CANOPENCFG myCANopen = {

20, // node_id

5, // msgobj_rx

6, // msgobj_tx

TRUE, // isr_handled

sizeof(myConstOD)/sizeof(myConstOD[0]), // od_const_num

(CAN_ODCONSTENTRY *)myConstOD, // od_const_table

sizeof(myOD)/sizeof(myOD[0]), // od_num

(CAN_ODENTRY *)myOD, // od_table

};

Example call:

// Initialize CANopen handler

(*rom)->pCAND->config_canopen((CAN_CANOPENCFG *)&myCANopen[0]);

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17.4.8 CANopen handler

The CANopen handler processes the CANopen SDO messages to access the Object

Dictionary and calls the CANopen callback functions when initialized. It can either be called by the interrupt handler automatically (isr_handled == TRUE in CANopen initialization structure) or manually via the CANopen handler API function. If called manually, the CANopen handler has to be called cyclically as often as needed for the application.

In a typical CANopen application, SDO handling has the lowest priority and is done in the foreground rather than through interrupt processing.

Example call:

// Call CANopen handler

(*rom)->pCAND->canopen_handler();

17.4.9 CAN/CANopen callback functions

The CAN API supports callback functions for various events. The callback functions are published via an API function.

typedef struct _CAN_CALLBACKS {

void (*CAN_rx)(uint8_t msg_obj);

void (*CAN_tx)(uint8_t msg_obj);

void (*CAN_error)(uint32_t error_info);

uint32_t (*CANOPEN_sdo_read)(uint16_t index, uint8_t subindex);

uint32_t (*CANOPEN_sdo_write)(

uint16_t index, uint8_t subindex, uint8_t *dat_ptr);

uint32_t (*CANOPEN_sdo_seg_read)(

uint16_t index, uint8_t subindex, uint8_t openclose,

uint8_t *length, uint8_t *data, uint8_t *last);

uint32_t (*CANOPEN_sdo_seg_write)(

uint16_t index, uint8_t subindex, uint8_t openclose,

uint8_t length, uint8_t *data, uint8_t *fast_resp);

uint8_t (*CANOPEN_sdo_req)(

uint8_t length_req, uint8_t *req_ptr, uint8_t *length_resp,

uint8_t *resp_ptr);

} CAN_CALLBACKS;

Example callback table definition:

// List of callback function pointers const CAN_CALLBACKS callbacks = {

CAN_rx,

CAN_tx,

CAN_error,

CANOPEN_sdo_exp_read,

CANOPEN_sdo_exp_write,

CANOPEN_sdo_seg_read,

CANOPEN_sdo_seg_write,

CANOPEN_sdo_req,

};

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/* Callback function prototypes */ void CAN_rx(uint8_t msg_obj_num); void CAN_tx(uint8_t msg_obj_num); void CAN_error(uint32_t error_info);

/* CANopen Callback function prototypes */ uint32_t CANOPEN_sdo_exp_read (uint16_t index, uint8_t subindex); uint32_t CANOPEN_sdo_exp_write(uint16_t index, uint8_t subindex, uint8_t *dat_ptr); uint32_t CANOPEN_sdo_seg_read(uint16_t index, uint8_t subindex, uint8_t openclose, uint8_t *length, uint8_t *data, uint8_t *last); uint32_t CANOPEN_sdo_seg_write(uint16_t index, uint8_t subindex, uint8_t openclose, uint8_t length, uint8_t *data, uint8_t *fast_resp); uint8_t CANOPEN_sdo_req(uint8_t length_req, uint8_t *req_ptr, uint8_t *length_resp, uint8_t *resp_ptr);

Example call:

// Publish callbacks

(*rom)->pCAND->config_calb(&callbacks);

17.4.10 CAN message received callback

The CAN message received callback function is called on the interrupt level by the CAN interrupt handler.

Example call:

// CAN receive handler void CAN_rx(uint8_t msgobj_num)

{

// Read out received message

msg_obj.msgobj = msgobj_num;

(*rom)->pCAND->can_receive(&msg_obj);

return;

}

Remark:

The callback is not called if the user CANopen handler is activated for the message object that is used for SDO receive.

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17.4.11 CAN message transmit callback

Called on the interrupt level by the CAN interrupt handler after a message has been successfully transmitted on the bus.

Example call:

// CAN transmit handler void CAN_tx(uint8_t msgobj_num)

{

// Reset flag used by application to wait for transmission finished if (wait_for_tx_finished == msgobj_num) wait_for_tx_finished = 0;

return;

}

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Remark:

The callback is not called after the user CANopen handler has used a message object to transmit an SDO response.

17.4.12 CAN error callback

The CAN error callback function is called on the interrupt level by the CAN interrupt handler.

// error status bits

#define CAN_ERROR_NONE 0x00000000UL

#define CAN_ERROR_PASS 0x00000001UL

#define CAN_ERROR_WARN 0x00000002UL

#define CAN_ERROR_BOFF 0x00000004UL

#define CAN_ERROR_STUF 0x00000008UL

#define CAN_ERROR_FORM 0x00000010UL

#define CAN_ERROR_ACK 0x00000020UL

#define CAN_ERROR_BIT1 0x00000040UL

#define CAN_ERROR_BIT0 0x00000080UL

#define CAN_ERROR_CRC 0x00000100UL

Example call:

// CAN error handler void CAN_error(uint32_t error_info)

// If we went into bus off state, tell the application to

// re-initialize the CAN controller

if (error_info & CAN_ERROR_BOFF) reset_can = TRUE;

return;

}

17.4.13 CANopen SDO expedited read callback

The CANopen SDO expedited read callback function is called by the CANopen handler.

The callback function is called before the SDO response is generated, allowing to modify or update the data.

Example call:

// CANopen callback for expedited read accesses uint32_t CANOPEN_sdo_exp_read(uint16_t index, uint8_t subindex)

{

// Every read of [2001h,0] increases param by one

if ((index == 0x2001) && (subindex==0)) param++;

return 0;

}

Remark:

If the flag isr_handled was set to TRUE when initializing CANopen, this callback function will be called by the CAN API interrupt handler and therefore will execute on the interrupt level.

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17.4.14 CANopen SDO expedited write callback

The CANopen SDO expedited write callback function is called by the CANopen handler.

The callback passes on the new data and is called before the new data has been written, allowing to reject or condition the data.

Example call:

// CANopen callback for expedited write accesses uint32_t CANOPEN_sdo_exp_write(uint16_t index, uint8_t subindex, uint8_t

*dat_ptr)

{

// Writing 0xAA55 to entry [2001h,0] unlocks writing the config table

if ((index == 0x2001) && (subindex == 0))

if (*(uint16_t *)dat_ptr == 0xAA55)

{ write_config_ena = TRUE; return(TRUE);

} else return(FALSE); // Reject any other value

}

Remark:

If the flag isr_handled was set TRUE when initializing CANopen, this callback function will be called by the CAN API interrupt handler and therefore will execute on the interrupt level.

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17.4.15 CANopen SDO segmented read callback

The CANopen SDO segmented read callback function is called by the CANopen handler.

The callback function allows the following actions:

inform about the opening of the read channel.

provide data segments of up to seven bytes to the reading host.

close the channel when all data has been read.

abort the transmission at any time.

// Values for CANOPEN_sdo_seg_read/write() callback 'openclose' parameter

#define CAN_SDOSEG_SEGMENT 0 // segment read/write

#define CAN_SDOSEG_OPEN 1 // channel is opened

#define CAN_SDOSEG_CLOSE 2 // channel is closed

Example call (reading a buffer): uint8_t read_buffer[0x123];

// CANopen callback for segmented read accesses uint32_t CANOPEN_sdo_seg_read(

uint16_t index, uint8_t subindex, uint8_t openclose,

uint8_t *length, uint8_t *data, uint8_t *last)

{

static uint16_t read_ofs;

uint16_t i;

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if ((index == 0x2200) && (subindex==0))

{

if (openclose == CAN_SDOSEG_OPEN)

{

// Initialize the read buffer with "something"

for (i=0; i<sizeof(read_buffer); i++)

{

read_buffer[i] = (i+5) + (i<<2);

}

read_ofs = 0;

}

else if (openclose == CAN_SDOSEG_SEGMENT)

{

i = 7;

while (i && (read_ofs < sizeof(read_buffer)))

{

*data++ = read_buffer[read_ofs++];

i--;

}

*length = 7-i;

if (read_ofs == sizeof(read_buffer)) // The whole buffer read:

// this is last segment

{

*last = TRUE;

}

}

return 0;

}

else

{

return SDO_ABORT_NOT_EXISTS;

}

}

Remark:

If the flag isr_handled was set TRUE when initializing CANopen, this callback function will be called by the CAN API interrupt handler and therefore will execute on the interrupt level.

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17.4.16 CANopen SDO segmented write callback

The CANopen SDO segmented write callback function is called by the CANopen handler.

The callback function allows the following actions:

inform about the opening and closing of the write channel.

pass on data segments of up to seven bytes from the writing host.

abort the transmission at any time, for example when there is a buffer overflow.

Responses can be selected to be 8-byte (CANopen standard compliant) or 1-byte (faster but not supported by all SDO clients).

// Values for CANOPEN_sdo_seg_read/write() callback 'openclose' parameter

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#define CAN_SDOSEG_SEGMENT 0 // segment read/write

#define CAN_SDOSEG_OPEN 1 // channel is opened

#define CAN_SDOSEG_CLOSE 2 // channel is closed

Example call (writing a buffer): uint8_t write_buffer[0x321];

// CANopen callback for segmented write accesses uint32_t CANOPEN_sdo_seg_write(

uint16_t index, uint8_t subindex, uint8_t openclose,

uint8_t length, uint8_t *data, uint8_t *fast_resp)

{

static uint16_t write_ofs;

uint16_t i;

if ((index == 0x2200) && (subindex==0))

{

if (openclose == CAN_SDOSEG_OPEN)

{

// Initialize the write buffer

for (i=0; i<sizeof(write_buffer); i++)

{

write_buffer[i] = 0;

}

write_ofs = 0;

}

else if (openclose == CAN_SDOSEG_SEGMENT)

{

*fast_resp = TRUE; // Use fast 1-byte segment write response

i = length;

while (i && (write_ofs < sizeof(write_buffer)))

{

write_buffer[write_ofs++] = *data++;

i--;

}

if (i && (write_ofs >= sizeof(write_buffer))) // Too much data to write

{

return SDO_ABORT_TRANSFER; // Data could not be written

}

}

else if (openclose == CAN_SDOSEG_CLOSE)

{

// Write has successfully finished: mark the buffer valid etc.

}

return 0;

}

else

{

return SDO_ABORT_NOT_EXISTS;

}

}

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Chapter 17: LPC11Cxx C_CAN on-chip drivers

Remark:

If the flag isr_handled was set TRUE when initializing CANopen, this callback function will be called by the CAN API interrupt handler and therefore will execute on the interrupt level.

17.4.17 CANopen fall-back SDO handler callback

The CANopen fall-back SDO handler callback function is called by the CANopen handler.

This function is called whenever an SDO request could not be processed or would end in an SDO abort response. It is called with the full data buffer of the request and allows to generate any type of SDO response. This can be used to implement custom SDO handlers, for example to implement the SDO block transfer method.

// Return values for CANOPEN_sdo_req() callback

#define CAN_SDOREQ_NOTHANDLED 0 // process regularly, no impact

#define CAN_SDOREQ_HANDLED_SEND 1 // processed in callback, auto-send

// returned msg

#define CAN_SDOREQ_HANDLED_NOSEND 2 // processed in callback, don't send

// response

Example call (not implementing custom processing):

// CANopen callback for custom SDO request handler uint8_t CANOPEN_sdo_req ( uint8_t length, uint8_t *req_ptr, uint8_t *length_resp, uint8_t *resp_ptr)

{ return CAN_SDOREQ_NOTHANDLED;

}

Remark:

If the flag isr_handled was set TRUE when initializing CANopen, this callback function will be called by the CAN API interrupt handler and therefore will execute on the interrupt level.

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Chapter 18: LPC1100/LPC1100C/LPC1100L series: 16-bit counter/timer CT16B0/1

Rev. 12.4 — 22 December 2016 User manual

18.1 How to read this chapter

The 16-bit timer blocks are identical for all LPC111x, LPC11D14, and LPC11Cxx parts in the LPC1100, LPC1100C, and LPC1100L series.

Pin-out variations

The match output MAT0 of timer 1 (CT16B1_MAT0) is not pinned out on parts LPC11C22 and LPC11C24.

18.2 Basic configuration

The CT16B0/1 are configured using the following registers:

1. Pins: The CT16B0/1 pins must be configured in the IOCONFIG register block

(

Section 7.4

).

2. Power and peripheral clock: In the SYSAHBCLKCTRL register, set bit 7 and bit 8

(

Table 21

). The peripheral clock is provided by the system clock (see

Table 20

).

18.3 Features

Two 16-bit counter/timers with a programmable 16-bit prescaler.

Counter or timer operation.

One 16-bit capture channel that can take a snapshot of the timer value when an input signal transitions. A capture event may also optionally generate an interrupt.

Four 16-bit match registers that allow:

Continuous operation with optional interrupt generation on match.

Stop timer on match with optional interrupt generation.

Reset timer on match with optional interrupt generation.

Up to three (CT16B0) or two (CT16B1) external outputs corresponding to match registers with the following capabilities:

Set LOW on match.

Set HIGH on match.

Toggle on match.

Do nothing on match.

For each timer, up to four match registers can be configured as PWM allowing to use up to three match outputs as single edge controlled PWM outputs.

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Chapter 18: LPC1100/LPC1100C/LPC1100L series: 16-bit counter/timer

18.4 Applications

Interval timer for counting internal events

Pulse Width Demodulator via capture input

Free-running timer

Pulse Width Modulator via match outputs

18.5 Description

Each Counter/timer is designed to count cycles of the peripheral clock (PCLK) or an externally supplied clock and can optionally generate interrupts or perform other actions at specified timer values based on four match registers. The peripheral clock is provided by the system clock (see

Figure 8

). Each counter/timer also includes one capture input to trap the timer value when an input signal transitions, optionally generating an interrupt.

In PWM mode, three match registers on CT16B0 and two match registers on CT16B1 can be used to provide a single-edge controlled PWM output on the match output pins. It is recommended to use the match registers that are not pinned out to control the PWM cycle length.

Remark:

The 16-bit counter/timer0 (CT16B0) and the 16-bit counter/timer1 (CT16B1) are functionally identical except for the peripheral base address.

18.6 Pin description

Table 279 gives a brief summary of each of the counter/timer related pins.

Table 279. Counter/timer pin description

Pin

CT16B0_CAP0

CT16B1_CAP0

CT16B0_MAT[2:0]

CT16B1_MAT[1:0]

Type

Input

Output

Description

Capture Signal:

A transition on a capture pin can be configured to load the Capture Register with the value in the counter/timer and optionally generate an interrupt.

Counter/Timer block can select a capture signal as a clock source instead of the PCLK

derived clock. For more details see Section 18.7.11

.

External Match Outputs of CT16B0/1:

When a match register of CT16B0/1 (MR3:0) equals the timer counter (TC), this output can either toggle, go LOW, go HIGH, or do nothing. The External Match Register

(EMR) and the PWM Control Register (PWMCON) control the functionality of this output.

18.7 Register description

The 16-bit counter/timer0 contains the registers shown in Table 280

and the 16-bit

counter/timer1 contains the registers shown in Table 281 . More detailed descriptions

follow.

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Chapter 18: LPC1100/LPC1100C/LPC1100L series: 16-bit counter/timer

Table 280. Register overview: 16-bit counter/timer 0 CT16B0 (base address 0x4000 C000)

Name

TMR16B0IR

TMR16B0TCR

Access

R/W

R/W

Address offset

0x000

0x004

Description

Interrupt Register (IR). The IR can be written to clear interrupts. The IR can be read to identify which of five possible interrupt sources are pending.

Timer Control Register (TCR). The TCR is used to control the Timer

Counter functions. The Timer Counter can be disabled or reset through the TCR.

TMR16B0TC R/W 0x008

TMR16B0PR R/W 0x00C

0

Timer Counter (TC). The 16-bit TC is incremented every PR+1 cycles of

PCLK. The TC is controlled through the TCR.

0

Prescale Register (PR). When the Prescale Counter (below) is equal to this value, the next clock increments the TC and clears the PC.

0

Reset

value

[1]

0

TMR16B0PC R/W 0x010

-

TMR16B0MCR

TMR16B0MR0

TMR16B0MR1

TMR16B0MR2

TMR16B0MR3

TMR16B0CCR

TMR16B0CR0

TMR16B0EMR

TMR16B0CTCR

-

R/W

R/W

R/W

R/W

R/W

R/W

RO

R/W

R/W

0x014

0x018

0x01C

0x020

0x024

0x028

0x02C

0x03C

0x040 -

0x06C

0x070

Prescale Counter (PC). The 16-bit PC is a counter which is incremented to the value stored in PR. When the value in PR is reached, the TC is incremented and the PC is cleared. The PC is observable and controllable through the bus interface.

0

Match Control Register (MCR). The MCR is used to control if an interrupt is generated and if the TC is reset when a Match occurs.

0

Match Register 0 (MR0). MR0 can be enabled through the MCR to reset the TC, stop both the TC and PC, and/or generate an interrupt every time

MR0 matches the TC.

Match Register 1 (MR1). See MR0 description.

0

0

Match Register 2 (MR2). See MR0 description.

Match Register 3 (MR3). See MR0 description.

0

0

Capture Control Register (CCR). The CCR controls which edges of the capture inputs are used to load the Capture Registers and whether or not an interrupt is generated when a capture takes place.

0

Capture Register 0 (CR0). CR0 is loaded with the value of TC when there is an event on the CT16B0_CAP0 input.

External Match Register (EMR). The EMR controls the match function and the external match pins CT16B0_MAT[2:0].

reserved -

0

0

TMR16B0PWMC R/W 0x074

Count Control Register (CTCR). The CTCR selects between Timer and

Counter mode, and in Counter mode selects the signal and edge(s) for counting.

0

PWM Control Register (PWMCON). The PWMCON enables PWM mode for the external match pins CT16B0_MAT[2:0].

0

[1] Reset value reflects the data stored in used bits only. It does not include reserved bits content.

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Chapter 18: LPC1100/LPC1100C/LPC1100L series: 16-bit counter/timer

Table 281. Register overview: 16-bit counter/timer 1 CT16B1 (base address 0x4001 0000)

Name

TMR16B1IR

TMR16B1TCR

Access

R/W

R/W

Address offset

0x000

0x004

Description

Interrupt Register (IR). The IR can be written to clear interrupts. The IR can be read to identify which of five possible interrupt sources are pending.

Timer Control Register (TCR). The TCR is used to control the Timer

Counter functions. The Timer Counter can be disabled or reset through the TCR.

TMR16B1TC R/W 0x008

TMR16B1PR R/W 0x00C

0

Timer Counter (TC). The 16-bit TC is incremented every PR+1 cycles of

PCLK. The TC is controlled through the TCR.

0

Prescale Register (PR). When the Prescale Counter (below) is equal to this value, the next clock increments the TC and clears the PC.

0

Reset value

[1]

0

TMR16B1PC R/W 0x010

-

TMR16B1MCR

TMR16B1MR0

TMR16B1MR1

TMR16B1MR2

TMR16B1MR3

TMR16B1CCR

TMR16B1CR0

TMR16B1EMR

TMR16B1CTCR

-

R/W

R/W

R/W

R/W

R/W

R/W

RO

R/W

R/W

TMR16B1PWMC R/W

0x014

0x018

0x01C

0x020

0x024

0x028

0x02C

0x03C

0x040 -

0x06C

0x070

0x074

Prescale Counter (PC). The 16-bit PC is a counter which is incremented to the value stored in PR. When the value in PR is reached, the TC is incremented and the PC is cleared. The PC is observable and controllable through the bus interface.

0

Match Control Register (MCR). The MCR is used to control if an interrupt is generated and if the TC is reset when a Match occurs.

0

Match Register 0 (MR0). MR0 can be enabled through the MCR to reset the TC, stop both the TC and PC, and/or generate an interrupt every time MR0 matches the TC.

Match Register 1 (MR1). See MR0 description.

0

0

Match Register 2 (MR2). See MR0 description.

Match Register 3 (MR3). See MR0 description.

0

0

Capture Control Register (CCR). The CCR controls which edges of the capture inputs are used to load the Capture Registers and whether or not an interrupt is generated when a capture takes place.

0

0 Capture Register 0 (CR0). CR0 is loaded with the value of TC when there is an event on the CT16B1_CAP0 input.

External Match Register (EMR). The EMR controls the match function and the external match pins CT16B1_MAT[1:0].

reserved -

0

Count Control Register (CTCR). The CTCR selects between Timer and

Counter mode, and in Counter mode selects the signal and edge(s) for counting.

0

PWM Control Register (PWMCON). The PWMCON enables PWM mode for the external match pins CT16B1_MAT[1:0].

0

[1] Reset value reflects the data stored in used bits only. It does not include reserved bits content.

18.7.1 Interrupt Register (TMR16B0IR and TMR16B1IR)

The Interrupt Register (IR) consists of four bits for the match interrupts and one bit for the capture interrupt. If an interrupt is generated then the corresponding bit in the IR will be

HIGH. Otherwise, the bit will be LOW. Writing a logic one to the corresponding IR bit will reset the interrupt. Writing a zero has no effect.

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Chapter 18: LPC1100/LPC1100C/LPC1100L series: 16-bit counter/timer

2

3

0

1

Table 282. Interrupt Register (TMR16B0IR - address 0x4000 C000 and TMR16B1IR - address 0x4001 0000) bit description

Bit Symbol Description Reset value

4

31:5 -

MR0 Interrupt

MR1 Interrupt

MR2 Interrupt

MR3 Interrupt

CR0 Interrupt

Interrupt flag for match channel 0.

Interrupt flag for match channel 1.

Interrupt flag for match channel 2.

Interrupt flag for match channel 3.

Interrupt flag for capture channel 0 event.

Reserved -

0

0

0

0

0

18.7.2 Timer Control Register (TMR16B0TCR and TMR16B1TCR)

The Timer Control Register (TCR) is used to control the operation of the counter/timer.

Table 283. Timer Control Register (TMR16B0TCR - address 0x4000 C004 and TMR16B1TCR - address 0x4001 0004) bit description

Bit

0

Symbol

CEn

Description

Counter Enable. When one, the Timer Counter and

Prescale Counter are enabled for counting. When zero, the counters are disabled.

Reset value

0

1

31:2 -

CRst Counter Reset. When one, the Timer Counter and the

Prescale Counter are synchronously reset on the next positive edge of PCLK. The counters remain reset until

TCR[1] is returned to zero.

Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined.

0

NA

18.7.3 Timer Counter (TMR16B0TC - address 0x4000 C008 and

TMR16B1TC - address 0x4001 0008)

The 16-bit Timer Counter is incremented when the Prescale Counter reaches its terminal count. Unless it is reset before reaching its upper limit, the TC will count up through the value 0x0000 FFFF and then wrap back to the value 0x0000 0000. This event does not cause an interrupt, but a Match register can be used to detect an overflow if needed.

Table 284: Timer counter registers (TMR16B0TC, address 0x4000 C008 and TMR16B1TC

0x4001 0008) bit description

Bit Symbol Description Reset value

15:0

31:16 -

TC Timer counter value.

Reserved.

-

0

18.7.4 Prescale Register (TMR16B0PR - address 0x4000 C00C and

TMR16B1PR - address 0x4001 000C)

The 16-bit Prescale Register specifies the maximum value for the Prescale Counter.

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Chapter 18: LPC1100/LPC1100C/LPC1100L series: 16-bit counter/timer

Table 285: Prescale registers (TMR16B0PR, address 0x4000 C00C and TMR16B1PR

0x4001 000C) bit description

Bit Symbol Description

15:0

31:16 -

PR Prescale max value.

Reserved.

-

Reset value

0

18.7.5 Prescale Counter register (TMR16B0PC - address 0x4000 C010 and

TMR16B1PC - address 0x4001 0010)

The 16-bit Prescale Counter controls division of PCLK by some constant value before it is applied to the Timer Counter. This allows control of the relationship between the resolution of the timer and the maximum time before the timer overflows. The Prescale Counter is incremented on every PCLK. When it reaches the value stored in the Prescale Register, the Timer Counter is incremented, and the Prescale Counter is reset on the next PCLK.

This causes the TC to increment on every PCLK when PR = 0, every 2 PCLKs when

PR = 1, etc.

Table 286: Prescale counter registers (TMR16B0PC, address 0x4001 C010 and TMR16B1PC

0x4000 0010) bit description

Bit Symbol Description Reset value

15:0

31:16 -

PC Prescale counter value.

Reserved.

-

0

18.7.6 Match Control Register (TMR16B0MCR and TMR16B1MCR)

The Match Control Register is used to control what operations are performed when one of the Match Registers matches the Timer Counter. The function of each of the bits is shown in

Table 287 .

Table 287. Match Control Register (TMR16B0MCR - address 0x4000 C014 and TMR16B1MCR - address 0x4001 0014) bit description

Bit Symbol Value Description

0

1

MR0I

MR0R

1

0

Interrupt on MR0: an interrupt is generated when MR0 matches the value in the TC.

Enabled

Disabled

Reset on MR0: the TC will be reset if MR0 matches it.

Reset value

0

0

2 MR0S

1

0

Enabled

Disabled

Stop on MR0: the TC and PC will be stopped and TCR[0] will be set to 0 if MR0 matches the TC.

0

3 MR1I

1

0

1

0

Enabled

Disabled

Interrupt on MR1: an interrupt is generated when MR1 matches the value in the TC.

Enabled

Disabled

0

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Chapter 18: LPC1100/LPC1100C/LPC1100L series: 16-bit counter/timer

Table 287. Match Control Register (TMR16B0MCR - address 0x4000 C014 and TMR16B1MCR - address 0x4001 0014) bit description

…continued

Bit Symbol Value Description Reset value

4 MR1R

5 MR1S

1

0

Reset on MR1: the TC will be reset if MR1 matches it.

Enabled

Disabled

0

Stop on MR1: the TC and PC will be stopped and TCR[0] will be set to 0 if MR1 matches the TC.

0

1

0

6

7

8

MR2I

MR2R

MR2S

1

0

1

0

Enabled

Disabled

Interrupt on MR2: an interrupt is generated when MR2 matches the value in the TC.

Enabled

0

Disabled

Reset on MR2: the TC will be reset if MR2 matches it.

Enabled

Disabled

0

Stop on MR2: the TC and PC will be stopped and TCR[0] will be set to 0 if MR2 matches the TC.

0

1

0

9

10

11

31:12 -

MR3I

MR3R

MR3S

1

0

1

0

1

0

Enabled

Disabled

Interrupt on MR3: an interrupt is generated when MR3 matches the value in the TC.

Enabled

0

Disabled

Reset on MR3: the TC will be reset if MR3 matches it.

Enabled

Disabled

0

Stop on MR3: the TC and PC will be stopped and TCR[0] will be set to 0 if MR3 matches the TC.

0

Enabled

Disabled

Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined.

NA

18.7.7 Match Registers (TMR16B0MR0/1/2/3 - addresses 0x4000

C018/1C/20/24 and TMR16B1MR0/1/2/3 - addresses 0x4001

0018/1C/20/24)

The Match register values are continuously compared to the Timer Counter value. When the two values are equal, actions can be triggered automatically. The action possibilities are to generate an interrupt, reset the Timer Counter, or stop the timer. Actions are controlled by the settings in the MCR register.

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Chapter 18: LPC1100/LPC1100C/LPC1100L series: 16-bit counter/timer

Table 288: Match registers (TMR16B0MR0 to 3, addresses 0x4000 C018 to 24 and

TMR16B1MR0 to 3, addresses 0x4001 0018 to 24) bit description

Bit Symbol Description

15:0

31:16 -

MATCH Timer counter match value.

Reserved.

-

Reset value

0

18.7.8 Capture Control Register (TMR16B0CCR and TMR16B1CCR)

The Capture Control Register is used to control whether the Capture Register is loaded with the value in the Counter/timer when the capture event occurs, and whether an interrupt is generated by the capture event. Setting both the rising and falling bits at the same time is a valid configuration, resulting in a capture event for both edges. In the description below, n represents the Timer number, 0 or 1.

Table 289. Capture Control Register (TMR16B0CCR - address 0x4000 C028 and TMR16B1CCR - address

0x4001 0028) bit description

Bit Symbol Value Description

0 CAP0RE

1

Capture on CT16Bn_CAP0 rising edge: a sequence of 0 then 1 on CT16Bn_CAP0 will cause CR0 to be loaded with the contents of TC.

Enabled

Reset value

0

1 CAP0FE

0

1

0

Disabled

Capture on CT16Bn_CAP0 falling edge: a sequence of 1 then 0 on CT16Bn_CAP0 will cause CR0 to be loaded with the contents of TC.

0

Enabled

2

31:3 -

CAP0I

-

1

0

Disabled

Interrupt on CT16Bn_CAP0 event: a CR0 load due to a CT16Bn_CAP0 event will generate an interrupt.

Enabled

Disabled

Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined.

0

NA

18.7.9 Capture Register (CT16B0CR0 - address 0x4000 C02C and

CT16B1CR0 - address 0x4001 002C)

Each Capture register is associated with a device pin and may be loaded with the counter/timer value when a specified event occurs on that pin. The settings in the Capture

Control Register register determine whether the capture function is enabled, and whether a capture event happens on the rising edge of the associated pin, the falling edge, or on both edges.

Table 290: Capture registers (TMR16B0CR0, address 0x4000 C02C and TMR16B1CR0, address 0x4001 002C) bit description

Bit Symbol Description Reset value

15:0

31:16 -

CAP Timer counter capture value.

Reserved.

-

0

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Chapter 18: LPC1100/LPC1100C/LPC1100L series: 16-bit counter/timer

18.7.10 External Match Register (TMR16B0EMR and TMR16B1EMR)

The External Match Register provides both control and status of the external match channels and external match pins CT16B0_MAT[2:0] and CT16B1_MAT[1:0].

If the match outputs are configured as PWM output in the PWMCON registers

(

Section 18.7.12

), the function of the external match registers is determined by the PWM

rules ( Section 18.7.13 “Rules for single edge controlled PWM outputs” on page 345 ).

Table 291. External Match Register (TMR16B0EMR - address 0x4000 C03C and TMR16B1EMR - address

0x4001 003C) bit description

Bit Symbol Value Description

0 EM0 External Match 0. This bit reflects the state of output CT16B0_MAT0/CT16B1_MAT0, whether or not this output is connected to its pin. When a match occurs between the TC and MR0, this bit can either toggle, go LOW, go HIGH, or do nothing. Bits EMR[5:4] control the functionality of this output. This bit is driven to the

CT16B0_MAT0/CT16B1_MAT0 pins if the match function is selected in the IOCON registers (0 = LOW, 1 = HIGH).

0

Reset value

1 EM1

2 EM2

External Match 1. This bit reflects the state of output CT16B0_MAT1/CT16B1_MAT1, whether or not this output is connected to its pin. When a match occurs between the TC and MR1, this bit can either toggle, go LOW, go HIGH, or do nothing. Bits EMR[7:6] control the functionality of this output. This bit is driven to the

CT16B0_MAT1/CT16B1_MAT1 pins if the match function is selected in the IOCON registers (0 = LOW, 1 = HIGH).

0

External Match 2. This bit reflects the state of output match channel 2, whether or not this output is connected to its pin. When a match occurs between the TC and MR2, this bit can either toggle, go LOW, go HIGH, or do nothing. Bits EMR[9:8] control the functionality of this output. Note that on counter/timer 0 this match channel is not pinned out. This bit is driven to the CT16B1_MAT2 pin if the match function is selected in the

IOCON registers (0 = LOW, 1 = HIGH).

0

3

5:4

EM3

EMC0

External Match 3. This bit reflects the state of output of match channel 3. When a match occurs between the TC and MR3, this bit can either toggle, go LOW, go HIGH, or do nothing. Bits EMR[11:10] control the functionality of this output. There is no output pin available for this channel on either of the 16-bit timers.

0

External Match Control 0. Determines the functionality of External Match 0. 00

0x0

0x1

7:6 EMC1

0x2

0x3

0x0

0x1

Do Nothing.

Clear the corresponding External Match bit/output to 0 (CT16Bn_MATm pin is LOW if pinned out).

Set the corresponding External Match bit/output to 1 (CT16Bn_MATm pin is HIGH if pinned out).

Toggle the corresponding External Match bit/output.

External Match Control 1. Determines the functionality of External Match 1.

Do Nothing.

00

0x2

0x3

Clear the corresponding External Match bit/output to 0 (CT16Bn_MATm pin is LOW if pinned out).

Set the corresponding External Match bit/output to 1 (CT16Bn_MATm pin is HIGH if pinned out).

Toggle the corresponding External Match bit/output.

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Table 291. External Match Register (TMR16B0EMR - address 0x4000 C03C and TMR16B1EMR - address

0x4001 003C) bit description

Bit Symbol Value Description

9:8

11:10

31:12 -

EMC2

EMC3

0x0

0x1

0x2

0x3

0x0

0x1

0x2

0x3

External Match Control 2. Determines the functionality of External Match 2.

Do Nothing.

Clear the corresponding External Match bit/output to 0 (CT16Bn_MATm pin is LOW if pinned out).

Set the corresponding External Match bit/output to 1 (CT16Bn_MATm pin is HIGH if pinned out).

Toggle the corresponding External Match bit/output.

External Match Control 3. Determines the functionality of External Match 3.

Do Nothing.

Clear the corresponding External Match bit/output to 0 (CT16Bn_MATm pin is LOW if pinned out).

Set the corresponding External Match bit/output to 1 (CT16Bn_MATm pin is HIGH if pinned out).

Toggle the corresponding External Match bit/output.

Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined.

Reset value

00

00

NA

Table 292. External match control

EMR[11:10], EMR[9:8],

EMR[7:6], or EMR[5:4]

Function

00

01

10

11

Do Nothing.

Clear the corresponding External Match bit/output to 0 (CT16Bn_MATm pin is LOW if pinned out).

Set the corresponding External Match bit/output to 1 (CT16Bn_MATm pin is HIGH if pinned out).

Toggle the corresponding External Match bit/output.

18.7.11 Count Control Register (TMR16B0CTCR and TMR16B1CTCR)

The Count Control Register (CTCR) is used to select between Timer and Counter mode, and in Counter mode to select the pin and edges for counting.

When Counter Mode is chosen as a mode of operation, the CAP input (selected by the

CTCR bits 3:2) is sampled on every rising edge of the PCLK clock. After comparing two consecutive samples of this CAP input, one of the following four events is recognized: rising edge, falling edge, either of edges or no changes in the level of the selected CAP input. Only if the identified event occurs, and the event corresponds to the one selected by bits 1:0 in the CTCR register, will the Timer Counter register be incremented.

Effective processing of the externally supplied clock to the counter has some limitations.

Since two successive rising edges of the PCLK clock are used to identify only one edge on the CAP selected input, the frequency of the CAP input can not exceed one half of the

PCLK clock. Consequently, duration of the HIGH/LOW levels on the same CAP input in this case can not be shorter than 1/(2

PCLK).

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Chapter 18: LPC1100/LPC1100C/LPC1100L series: 16-bit counter/timer

Table 293. Count Control Register (TMR16B0CTCR - address 0x4000 C070 and

TMR16B1CTCR - address 0x4001 0070) bit description

Bit Symbol Value

1:0 CTM

Description Reset value

Counter/Timer Mode. This field selects which rising PCLK edges can increment Timer’s Prescale Counter (PC), or clear

PC and increment Timer Counter (TC).

00

3:2 CIS

31:4 -

0x0

0x1

0x2

0x3

-

0x0

0x1

0x2

0x3

Timer Mode: every rising PCLK edge

Counter Mode: TC is incremented on rising edges on the

CAP input selected by bits 3:2.

Counter Mode: TC is incremented on falling edges on the

CAP input selected by bits 3:2.

Counter Mode: TC is incremented on both edges on the CAP input selected by bits 3:2.

Count Input Select. In counter mode (when bits 1:0 in this register are not 00), these bits select which CAP pin is sampled for clocking.

Note:

If Counter mode is selected in the CTCR register, bits 2:0 in the Capture Control Register

(CCR) must be programmed as 000.

00

CT16Bn_CAP0

CT16Bn_CAP1

Reserved.

Reserved.

Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined.

-

18.7.12 PWM Control register (TMR16B0PWMC and TMR16B1PWMC)

The PWM Control Register is used to configure the match outputs as PWM outputs. Each match output can be independently set to perform either as PWM output or as match output whose function is controlled by the External Match Register (EMR).

For timer 0, three single-edge controlled PWM outputs can be selected on the

CT16B0_MAT[2:0] outputs. For timer 1, two single-edged PWM outputs can be selected on the CT16B1_Mat[1:0] outputs. One additional match register determines the PWM cycle length. When a match occurs in any of the other match registers, the PWM output is set to HIGH. The timer is reset by the match register that is configured to set the PWM cycle length. When the timer is reset to zero, all currently HIGH match outputs configured as PWM outputs are cleared.

Table 294. PWM Control Register (TMR16B0PWMC - address 0x4000 C074 and

TMR16B1PWMC- address 0x4001 0074) bit description

Bit Symbol Value Description

0 PWMEN0

Reset value

0

0

1

PWM channel0 enable

CT16Bn_MAT0 is controlled by EM0.

PWM mode is enabled for CT16Bn_MAT0.

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Chapter 18: LPC1100/LPC1100C/LPC1100L series: 16-bit counter/timer

Table 294. PWM Control Register (TMR16B0PWMC - address 0x4000 C074 and

TMR16B1PWMC- address 0x4001 0074) bit description

Bit Symbol Value Description

1

2

3

31:4 -

PWMEN1

PWMEN2

PWMEN3

0

1

0

1

0

1

PWM channel1 enable

CT16Bn_MAT1 is controlled by EM1.

PWM mode is enabled for CT16Bn_MAT1.

PWM channel2 enable

Match channel 2 or pin CT16B0_MAT2 is controlled by

EM2. Match channel 2 is not pinned out on timer 1.

PWM mode is enabled for match channel 2 or pin

CT16B0_MAT2.

PWM channel3 enable

Note:

It is recommended to use match channel 3 to set the PWM cycle because it is not pinned out.

Match channel 3 match channel 3 is controlled by EM3.

PWM mode is enabled for match channel 3match channel 3.

Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined.

Reset value

0

0

0

NA

18.7.13 Rules for single edge controlled PWM outputs

1. All single edge controlled PWM outputs go LOW at the beginning of each PWM cycle

(timer is set to zero) unless their match value is equal to zero.

2. Each PWM output will go HIGH when its match value is reached. If no match occurs

(i.e. the match value is greater than the PWM cycle length), the PWM output remains continuously LOW.

3. If a match value larger than the PWM cycle length is written to the match register, and the PWM signal is HIGH already, then the PWM signal will be cleared on the next start of the next PWM cycle.

4. If a match register contains the same value as the timer reset value (the PWM cycle length), then the PWM output will be reset to LOW on the next clock tick. Therefore, the PWM output will always consist of a one clock tick wide positive pulse with a period determined by the PWM cycle length (i.e. the timer reload value).

5. If a match register is set to zero, then the PWM output will go to HIGH the first time the timer goes back to zero and will stay HIGH continuously.

Note:

When the match outputs are selected to serve as PWM outputs, the timer reset

(MRnR) and timer stop (MRnS) bits in the Match Control Register MCR must be set to 0 except for the match register setting the PWM cycle length. For this register, set the

MRnR bit to 1 to enable the timer reset when the timer value matches the value of the corresponding match register.

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Chapter 18: LPC1100/LPC1100C/LPC1100L series: 16-bit counter/timer

PWM2/MAT2

PWM1/MAT1

PWM0/MAT0

MR2 = 100

MR1 = 41

MR0 = 65

0 41 65 100

(counter is reset)

Fig 69. Sample PWM waveforms with a PWM cycle length of 100 (selected by MR2) and

MAT2:0 enabled as PWM outputs by the PWCM register.

18.8 Example timer operation

Figure 70

shows a timer configured to reset the count and generate an interrupt on match.

The prescaler is set to 2 and the match register set to 6. At the end of the timer cycle where the match occurs, the timer count is reset. This gives a full length cycle to the match value. The interrupt indicating that a match occurred is generated in the next clock after the timer reached the match value.

Figure 71

shows a timer configured to stop and generate an interrupt on match. The prescaler is again set to 2 and the match register set to 6. In the next clock after the timer reaches the match value, the timer enable bit in TCR is cleared, and the interrupt indicating that a match occurred is generated.

PCLK prescale counter timer counter timer counter reset interrupt

2

4

0 1

5

2 0 1

6

2 0 1

0

2 0

1

Fig 70. A timer cycle in which PR=2, MRx=6, and both interrupt and reset on match are enabled

1

PCLK prescale counter timer counter

TCR[0]

(counter enable) interrupt

2

4

0 1

5

1

2 0

6

0

Fig 71. A timer cycle in which PR=2, MRx=6, and both interrupt and stop on match are enabled

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Chapter 18: LPC1100/LPC1100C/LPC1100L series: 16-bit counter/timer

18.9 Architecture

The block diagram for counter/timer0 and counter/timer1 is shown in Figure 72 .

MATCH REGISTER 0

MATCH REGISTER 1

MATCH REGISTER 2

MATCH REGISTER 3

MATCH CONTROL REGISTER

EXTERNAL MATCH REGISTER

INTERRUPT REGISTER

CONTROL

MATn[2:0]

INTERRUPT

CAP0

STOP ON MATCH

RESET ON MATCH

LOAD[3:0]

CAPTURE CONTROL REGISTER

=

=

=

=

CSN

TIMER COUNTER

CE

CAPTURE REGISTER 0

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reset

TIMER CONTROL REGISTER enable

Fig 72. 16-bit counter/timer block diagram

TCI

PRESCALE COUNTER

PCLK

MAXVAL

PRESCALE REGISTER

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Chapter 19: LPC1100XL series: 16-bit counter/timer CT16B0/1

Rev. 12.4 — 22 December 2016 User manual

19.1 How to read this chapter

The 16-bit timer blocks are identical for all LPC1100XL parts.

Compared to the timer block for the LPC1100/LPC1100L/LPC1100C series, the following features have been added:

One additional capture input for each timer.

Capture-clear function for easy pulse-width measurement (see

Section 19.7.11

).

19.2 Basic configuration

The CT16B0/1 are configured using the following registers:

1. Pins: The CT16B0/1 pins must be configured in the IOCONFIG register block

(

Section 7.4

).

2. Power and peripheral clock: In the SYSAHBCLKCTRL register, set bit 7 and bit 8

(

Table 21

). The peripheral clock is provided by the system clock (see

Table 20

).

19.3 Features

Two 16-bit counter/timers with a programmable 16-bit prescaler.

Counter or timer operation.

The timer and prescaler may be configured to be cleared on a designated capture event. This feature permits easy pulse-width measurement by clearing the timer on the leading edge of an input pulse and capturing the timer value on the trailing edge.

Two 16-bit capture channels that can take a snapshot of the timer value when an input signal transitions. A capture event may also optionally generate an interrupt.

Four 16-bit match registers that allow:

Continuous operation with optional interrupt generation on match.

Stop timer on match with optional interrupt generation.

Reset timer on match with optional interrupt generation.

Up to three (CT16B0) or two (CT16B1) external outputs corresponding to match registers with the following capabilities:

Set LOW on match.

Set HIGH on match.

Toggle on match.

Do nothing on match.

For each timer, up to four match registers can be configured as PWM allowing to use up to three match outputs as single edge controlled PWM outputs.

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Chapter 19: LPC1100XL series: 16-bit counter/timer CT16B0/1

19.4 Applications

Interval timer for counting internal events

Pulse Width Demodulator via capture input

Free-running timer

Pulse Width Modulator via match outputs

19.5 Description

Each Counter/timer is designed to count cycles of the peripheral clock (PCLK) or an externally supplied clock and can optionally generate interrupts or perform other actions at specified timer values based on four match registers. The peripheral clock is provided by the system clock (see

Figure 8

). Each counter/timer also includes one capture input to trap the timer value when an input signal transitions, optionally generating an interrupt.

In PWM mode, three match registers on CT16B0 and two match registers on CT16B1 can be used to provide a single-edge controlled PWM output on the match output pins. It is recommended to use the match registers that are not pinned out to control the PWM cycle length.

Remark:

The 16-bit counter/timer0 (CT16B0) and the 16-bit counter/timer1 (CT16B1) are functionally identical except for the peripheral base address.

19.6 Pin description

Table 295 gives a brief summary of each of the counter/timer related pins.

Table 295. Counter/timer pin description

Pin

CT16B0_CAP[1:0]

CT16B1_CAP0[1:0]

CT16B0_MAT[2:0]

CT16B1_MAT[1:0]

Type

Input

Output

Description

Capture Signal:

A transition on a capture pin can be configured to load the Capture Register with the value in the counter/timer and optionally generate an interrupt.

Counter/Timer block can select a capture signal as a clock source instead of the PCLK

derived clock. For more details see Section 19.7.11

.

External Match Outputs of CT16B0/1:

When a match register of CT16B0/1 (MR3:0) equals the timer counter (TC), this output can either toggle, go LOW, go HIGH, or do nothing. The External Match Register

(EMR) and the PWM Control Register (PWMCON) control the functionality of this output.

19.7 Register description

The 16-bit counter/timer0 contains the registers shown in Table 296

and the 16-bit

counter/timer1 contains the registers shown in Table 297 . More detailed descriptions

follow.

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Chapter 19: LPC1100XL series: 16-bit counter/timer CT16B0/1

Table 296. Register overview: 16-bit counter/timer 0 CT16B0 (base address 0x4000 C000)

Name

TMR16B0IR

TMR16B0TCR

Access

R/W

R/W

Address offset

0x000

0x004

Description

Interrupt Register (IR). The IR can be written to clear interrupts. The IR can be read to identify which of five possible interrupt sources are pending.

Timer Control Register (TCR). The TCR is used to control the Timer

Counter functions. The Timer Counter can be disabled or reset through the TCR.

TMR16B0TC R/W 0x008

TMR16B0PR R/W 0x00C

0

Timer Counter (TC). The 16-bit TC is incremented every PR+1 cycles of

PCLK. The TC is controlled through the TCR.

0

Prescale Register (PR). When the Prescale Counter (below) is equal to this value, the next clock increments the TC and clears the PC.

0

Reset

value

[1]

0

TMR16B0PC R/W 0x010

-

-

TMR16B0MCR

TMR16B0MR0

TMR16B0MR1

TMR16B0MR2

TMR16B0MR3

TMR16B0CCR

TMR16B0CR0

TMR16B0CR1

TMR16B0EMR

TMR16B0CTCR

-

-

R/W

R/W

R/W

R/W

R/W

R/W

RO

RO

R/W

R/W

0x014

0x018

0x01C

0x020

0x024

0x028

0x02C

0x030

0x034 -

0x038

0x03C

0x040 -

0x06C

0x070

Prescale Counter (PC). The 16-bit PC is a counter which is incremented to the value stored in PR. When the value in PR is reached, the TC is incremented and the PC is cleared. The PC is observable and controllable through the bus interface.

0

Match Control Register (MCR). The MCR is used to control if an interrupt is generated and if the TC is reset when a Match occurs.

0

Match Register 0 (MR0). MR0 can be enabled through the MCR to reset the TC, stop both the TC and PC, and/or generate an interrupt every time

MR0 matches the TC.

Match Register 1 (MR1). See MR0 description.

0

0

Match Register 2 (MR2). See MR0 description.

Match Register 3 (MR3). See MR0 description.

0

0

Capture Control Register (CCR). The CCR controls which edges of the capture inputs are used to load the Capture Registers and whether or not an interrupt is generated when a capture takes place.

0

Capture Register 0 (CR0). CR0 is loaded with the value of TC when there is an event on the CT16B0_CAP0 input.

Capture Register 1 (CR1). CR1 is loaded with the value of TC when there is an event on the CT16B0_CAP1 input.

Reserved -

0

0

External Match Register (EMR). The EMR controls the match function and the external match pins CT16B0_MAT[2:0].

Reserved -

0

TMR16B0PWMC R/W 0x074

Count Control Register (CTCR). The CTCR selects between Timer and

Counter mode, and in Counter mode selects the signal and edge(s) for counting.

0

PWM Control Register (PWMCON). The PWMCON enables PWM mode for the external match pins CT16B0_MAT[2:0].

0

[1] Reset value reflects the data stored in used bits only. It does not include reserved bits content.

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Chapter 19: LPC1100XL series: 16-bit counter/timer CT16B0/1

Table 297. Register overview: 16-bit counter/timer 1 CT16B1 (base address 0x4001 0000)

Name

TMR16B1IR

TMR16B1TCR

Access

R/W

R/W

Address offset

0x000

0x004

Description

Interrupt Register (IR). The IR can be written to clear interrupts. The IR can be read to identify which of five possible interrupt sources are pending.

Timer Control Register (TCR). The TCR is used to control the Timer

Counter functions. The Timer Counter can be disabled or reset through the TCR.

TMR16B1TC R/W 0x008

TMR16B1PR R/W 0x00C

0

Timer Counter (TC). The 16-bit TC is incremented every PR+1 cycles of

PCLK. The TC is controlled through the TCR.

0

Prescale Register (PR). When the Prescale Counter (below) is equal to this value, the next clock increments the TC and clears the PC.

0

Reset value

[1]

0

TMR16B1PC R/W 0x010

-

-

TMR16B1MCR

TMR16B1MR0

TMR16B1MR1

TMR16B1MR2

TMR16B1MR3

TMR16B1CCR

TMR16B1CR0

TMR16B1CR1

TMR16B1EMR

TMR16B1CTCR

-

-

R/W

R/W

R/W

R/W

R/W

R/W

RO

RO

R/W

R/W

0x014

0x018

0x01C

0x020

0x024

0x028

0x02C

0x030

0x034 -

0x038

0x03C

0x040 -

0x06C

0x070

Prescale Counter (PC). The 16-bit PC is a counter which is incremented to the value stored in PR. When the value in PR is reached, the TC is incremented and the PC is cleared. The PC is observable and controllable through the bus interface.

0

Match Control Register (MCR). The MCR is used to control if an interrupt is generated and if the TC is reset when a Match occurs.

0

Match Register 0 (MR0). MR0 can be enabled through the MCR to reset the TC, stop both the TC and PC, and/or generate an interrupt every time MR0 matches the TC.

Match Register 1 (MR1). See MR0 description.

0

0

Match Register 2 (MR2). See MR0 description.

Match Register 3 (MR3). See MR0 description.

0

0

Capture Control Register (CCR). The CCR controls which edges of the capture inputs are used to load the Capture Registers and whether or not an interrupt is generated when a capture takes place.

0

0 Capture Register 0 (CR0). CR0 is loaded with the value of TC when there is an event on the CT16B1_CAP0 input.

Capture Register 1 (CR1). CR1 is loaded with the value of TC when there is an event on the CT16B1_CAP1 input.

Reserved -

0

External Match Register (EMR). The EMR controls the match function and the external match pins CT16B1_MAT[1:0].

Reserved -

0

TMR16B1PWMC R/W 0x074

Count Control Register (CTCR). The CTCR selects between Timer and

Counter mode, and in Counter mode selects the signal and edge(s) for counting.

0

PWM Control Register (PWMCON). The PWMCON enables PWM mode for the external match pins CT16B1_MAT[1:0].

0

[1] Reset value reflects the data stored in used bits only. It does not include reserved bits content.

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Chapter 19: LPC1100XL series: 16-bit counter/timer CT16B0/1

19.7.1 Interrupt Register (TMR16B0IR and TMR16B1IR)

The Interrupt Register (IR) consists of four bits for the match interrupts and one bit for the capture interrupt. If an interrupt is generated then the corresponding bit in the IR will be

HIGH. Otherwise, the bit will be LOW. Writing a logic one to the corresponding IR bit will reset the interrupt. Writing a zero has no effect.

2

3

0

1

Table 298. Interrupt Register (TMR16B0IR - address 0x4000 C000 and TMR16B1IR - address 0x4001 0000) bit description

Bit Symbol Description Reset value

MR0INT

MR1INT

MR2INT

MR3INT

Interrupt flag for match channel 0.

Interrupt flag for match channel 1.

Interrupt flag for match channel 2.

Interrupt flag for match channel 3.

0

0

0

0

4

5

31:6 -

CR0INT

CR1INT

Interrupt flag for capture channel 0 event.

Interrupt flag for capture channel 1 event.

Reserved -

0

0

19.7.2 Timer Control Register (TMR16B0TCR and TMR16B1TCR)

The Timer Control Register (TCR) is used to control the operation of the counter/timer.

Table 299. Timer Control Register (TMR16B0TCR - address 0x4000 C004 and TMR16B1TCR - address 0x4001 0004) bit description

Bit Symbol Description Reset value

0 CEN

1

31:2 -

CRST

Counter Enable. When one, the Timer Counter and

Prescale Counter are enabled for counting. When zero, the counters are disabled.

0

0 Counter Reset. When one, the Timer Counter and the

Prescale Counter are synchronously reset on the next positive edge of PCLK. The counters remain reset until

TCR[1] is returned to zero.

Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined.

NA

19.7.3 Timer Counter (TMR16B0TC - address 0x4000 C008 and

TMR16B1TC - address 0x4001 0008)

The 16-bit Timer Counter is incremented when the Prescale Counter reaches its terminal count. Unless it is reset before reaching its upper limit, the TC will count up through the value 0x0000 FFFF and then wrap back to the value 0x0000 0000. This event does not cause an interrupt, but a Match register can be used to detect an overflow if needed.

Table 300: Timer counter registers (TMR16B0TC, address 0x4000 C008 and TMR16B1TC

0x4001 0008) bit description

Bit Symbol Description

15:0 TC Timer counter value.

Reset value

0

31:16 Reserved.

-

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Chapter 19: LPC1100XL series: 16-bit counter/timer CT16B0/1

19.7.4 Prescale Register (TMR16B0PR - address 0x4000 C00C and

TMR16B1PR - address 0x4001 000C)

The 16-bit Prescal