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CONTENTS
Console Theory of Operation .............................................................................................................. 4-19
6.1 Main PCB Interface ......................................................................................................................... 14
6.3 FM Tuner .......................................................................................................................................... 16
Console Procedures ........................................................................................................................ 27-33
Bass Module Procedures ................................................................................................................ 34-35
Satellite Array Procedures .................................................................................................................... 36
Appendix ............................................................................................................................................. 37-51
Figure 1. 3•2•1 Series II Console Test Setup Diagram ............................................................................ 37
Figure 2. 3•2•1 Series II Bass Module Test Setup Diagram .................................................................... 38
Obtaining System Information from the Media Center Display ........................................................ 39
Computer Setup Procedure ............................................................................................................ 40-41
IC Diagrams ........................................................................................................................................52-61
Service Manual Revision History ........................................................................................................... 62
1
SAFETY INFORMATION
1. Parts that have special safety characteristics are identified by the symbol on schematics or by special notes on the parts list. Use only replacement parts that have critical characteristics recommended by the manufacturer.
2. Make leakage current or resistance measurements to determine that exposed parts are acceptably insulated from the supply circuit before returning the unit to the customer.
Use the following checks to perform these measurements:
A. Leakage Current Hot Check-With the unit completely reassembled, plug the AC line cord directly into a 120V AC outlet. (Do not use an isolation transformer during this test.) Use a leakage current tester or a metering system that complies with American National Standards
Institute (ANSI) C101.1 "Leakage Current for Appliances" and Underwriters Laboratories (UL)
6500 / IEC 60056 paragraph 9.1.1. With the unit AC switch first in the ON position and then in
OFF position, measure from a known earth ground (metal waterpipe, conduit, etc.) to all exposed metal parts of the unit (antennas, handle bracket, metal cabinet, screwheads, metallic overlays, control shafts, etc.), especially any exposed metal parts that offer an electrical return path to the chassis. Any current measured must not exceed 0.5 milliamp. Reverse the unit power cord plug in the outlet and repeat test. ANY MEASUREMENTS NOT WITHIN THE
LIMITS SPECIFIED HEREIN INDICATE A POTENTIAL SHOCK HAZARD THAT MUST BE
ELIMINATED BEFORE RETURNING THE UNIT TO THE CUSTOMER.
B. Insulation Resistance Test Cold Check-(1) Unplug the power supply and connect a jumper wire between the two prongs of the plug. (2) Turn on the power switch of the unit. (3) Measure the resistance with an ohmmeter between the jumpered AC plug and each exposed metallic cabinet part on the unit. When testing 3 wire products, the resistance measured to the product enclosure should be between 2 and infinite MOhms. Also, the resistance measured to exposed input/output connectors should be between 4 and infinite MOhms. When testing 2 wire products, the resistance measured to exposed input/output connectors should be between 4 and infinite MOhms. If it is not within the limits specified, there is the possibility of a shock hazard, and the unit must be repaired and rechecked before it is returned to the customer.
CAUTION: The Bose
®
3
•
2
•
1 Series II Home Entertainment System contains no user-serviceable parts. To prevent warranty infractions, refer servicing to warranty service stations or factory service.
PROPRIETARY INFORMATION
THIS DOCUMENT CONTAINS PROPRIETARY INFORMATION OF
BOSE CORPORATION WHICH IS BEING FURNISHED ONLY FOR
THE PURPOSE OF SERVICING THE IDENTIFIED BOSE PRODUCT
BY AN AUTHORIZED BOSE SERVICE CENTER OR OWNER OF
THE BOSE PRODUCT, AND SHALL NOT BE REPRODUCED OR
USED FOR ANY OTHER PURPOSE.
2
ELECTROSTATIC DISCHARGE SENSITIVE (ESDS)
DEVICE HANDLING
This unit contains ESDS devices. We recommend the following precautions when repairing, replacing or transporting ESDS devices:
• Perform work at an electrically grounded work station.
• Wear wrist straps that connect to the station or heel straps that connect to conductive
floor mats.
• Avoid touching the leads or contacts of ESDS devices or PC boards even if properly
grounded. Handle boards by the edges only.
• Transport or store ESDS devices in ESD protective bags, bins, or totes. Do not insert
unprotected devices into materials such as plastic, polystyrene foam, clear plastic bags,
bubble wrap or plastic trays.
3
THEORY OF OPERATION
System Overview
The 3
•
2
•
1 Series II is a single-zone home entertainment system. It has two configurations:
(1) basic/standard system with no Ethernet interface and no hard drive or uMusic TM function.
This system will be available with either the standard 3
•
2
•
1 speaker arrays or the Gemstone
TM speaker arrays. (2) A premium system including the Ethernet interface and hard drive and uMusic. This system will also incorporate the array speakers developed in the Gemstone project.
The 3
•
2
•
1 Series II system consists of the following major components:
1. Console with Display, Main board, Tuner board, button board and IR remote receiver,
CD/DVD driver, Hard disk driver (premium version only).
2. Bass module Unit with Woofer, DSP board, I/O board and system power supply.
3. Two two-element speaker arrays.
4. IR remote control.
Console Theory of Operation
The basic elements of the console are:
1. Main board.
2. Tuner board.
3. VFD display.
4. DVD ROM driver.
5. Button board.
6. IR receiver.
7. Hard disk driver (premium only)
8. Ethernet interface (premium only)
1. Power Supply
Note: Refer to the 3
•
2
•
1 II console schematic sheets, 270593, for the following information.
The bass module provides un-regulated power V_UNREG to console via connector J100 pins 1 and 2 [sheet 10, B2]. The power supply electronics are comprised of 4 main sections; switching power supplies, linear power supplies, power supply synchronization, and power fail detection.
The console’s input voltage, V_UNREG, comes from the bass module and is nominally 26VDC.
This voltage varies with load and line levels, but is limited to 31.5V maximum (assuming line voltage of 140V AC). This voltage is always present whenever the bass module is plugged into the wall and so the console’s power supplies are likewise active. All the voltage level source are listed in following table:
Node Name Output
Voltage
Type Input from
V_UNREG +26 Full Bass module rectifier at line of
120VAC
+12V +12 Switching V_UNREG
Outputs to
+12V and +5V switching power supply
+9V
+5V
+3.3V
+1.8V
+9
+5
+3.3
+1.8
Linear +12V
Switching V_UNREG
Linear
Linear
+5V
+3.3V
DVD drive, Tuner board, VFD display, Video control relay.
Analog MUX, DAC output filter op-amps, Summing op-amps and Zone speaker differential input opamps.
+3.3V and +1.8V switching power supply; DVD drive, Hard disk driver, IR receiver, DAC, SPDIF receiver.
Processor CS98200’s I/O power, Flash, SDRAM
IC’s, Ethernet controller, SPDIF receiver,
Processor CS98200’s core and PLL circuit power; power on/monitor reset chip.
Note: The 1.8V and 3.3V linear regulators are derived from the +5V switching power supply.
The 9V linear regulator is derived from the +12V switching power supply.
4
THEORY OF OPERATION
1.1. Switching Power Supplies
The +12V and +5V switching power supplies use ST L4973D3.3 regulator ICs (U17 [sheet 14,
B5] and U2 [A6]). The power supplies are designed as step-down Buck converters. The voltage fed back to the chip on pin 13 determines the output voltage; the chip’s control circuitry will work to keep this voltage at +3.3V. The +5.1V and +12V supplies use resistor divide-down networks to obtain the +3.3V feedback voltage.
The reference designators listed below correspond to the +12V switching power supply; the designs of the +5V regulator is nearly identical.
IC Pin
1
10
Components Connected Function
R17, C50
C25
11 R33
Sets free running switching frequency
(when not controlled externally)
Bootstrap to drive internal D-MOS
12
13
18
19
20
R36 C22 C24
R30 R37
C51
C58
Q5
Lead-lag filter for compensation loop
Voltage feedback for control
+5.1V for external reference
Sets supply soft-start time constant
Supply frequency switching synchronization
(see section 2.4 below)
A number of additional series inductors and parallel capacitors exist to provide filtering functions.
The compensation networks used for these switching power supplies have been chosen to provide stability under all conditions and to provide minimal RF interference to the tuner.
The supplies function in both continuous and discontinuous mode depending on the load.
1.2. Linear Power Supplies
U18 [C3] is the +9V linear regulator. VR1 [A3] and VR2 [A2] are the 3.3V and 1.8V linear regulator, respectively.
1.3. Supply Synchronization
In order to control the noise interference to the AM tuner, a variable frequency to alternate switching synchronization scheme was implemented. When the console is in the Tuner mode, the SPDIF receiver (U8001 [sheet 12, B4]) delivers a 2.8224MHz clock signal (SPDIFIN_BCK) from the 11.2896MHz crystal oscillator. SPDIFIN_BCK drives the binary count (U3 [sheet 14,
C4]) and generates a required synchronizing pulse (F_SYNCH) and feed to pin 20 of U17 [C5] and pin 20 of U2 [B6]. Q4 [D3] and Q5 [D3] are for buffering and level shifting of the synchronizing pulse. The synchronization pulse alternation is controlled by tuner board based on the AM station to be tuned.
5
THEORY OF OPERATION
1.4. Power Failure Detection
It is important to detect a power failure and alert the mircoprocessor to save any relevant information and mute the power amplifiers so that no audio “pops” will be heard. The power failure detection circuit (Q2, Q3, R11, R35, R40 and R15 [sheet 14, C7]) that we employ controls an edge-triggered interrupt to the CS98200 microprocessor (U7003, pin 146 [sheet 5, C5]) to do just that. If the voltage on V_UNREG falls below roughly 13.2V, the microprocessor will be alerted that there is a power failure occuring. The interrupt will be unasserted (go high) when
V_UNREG goes above roughly 16.1V. This large hytsterisis is set so that dips in V_UNREG caused by loud volumes will not inadvertantly trip a power fail interrupt. In a brownout condition, the system will mute with the power dip and then recover gracefully when the normal line level is restored (V_UNREG goes above 15.39V).
2. Processor and Its Peripherals
2.1 Processor
The CS98200 (U7003) from Cirrus Logic is the DVD decoder IC that functions as the console's main processor. The CS98200 is a highly-integrated processor that provides all of the audio and video processing functions needed for the next generation of feature-rich DVD players, DVD receivers and Internet DVD applications such as MP3, Dolby Digital™, Dolby ProLogic II™, and
DTS Digital Surround™ decoding. It supports most popular CD formats, disk control, video decoding and up to eight channels of audio output. The CS98200 also integrates six 10-bit video digital-to-analog converters (DACs) and TV encoding with progressive scan functionality.
Progressive scan video provides high resolution and eliminates the "flickering" effect present in traditional video playback.
The CS98200 contains two embedded 32-bit RISC processors, one of which is used as the main processor in the 3
•
2
•
1 Series II system. This processor controls all GPIO, sub-circuits and interfaces, with the exception of those offloaded to the ST micro on the Tuner Board. All of the
Main Board software runs on this processor. The second embedded CS98200 processor is responsible for overseeing ATAPI, Memory and Host interfaces, DVD ROM Drive disc playback,
Hard Disk Drive store/playback and audio/video decode and generation. Software for this processor is provided by Cirrus. An external FLASH and SDRAM are shared between the two
RISC processors.
2.1.1 Processor clock
Y7000 [sheet 2, B6] is the 27.0 MHz crystal for processor CS98200 (U7003) to derivate all the internal system clock signals. C7001 and C7002 are the load capacitors. The crystal’s frequency accuracy should be within ±50ppm for color video operation.
2.1.2 Processor reset
U7002 [sheet 2, B6] generates a 140ms power-on pulse any time the +1.8V supply dips below
1.58 volts (including initial power-on). The pulse goes through RC network (R7015 and C7003) to U7003’s reset input pin 2. This same pulse also goes through another RC network (R7013 and C6219) to flash chip U6203’s [sheet 6, C3] reset input pin 12. Those two RC networks have a different time constant to ensure flash chip is out of reset before processor C98200.
6
THEORY OF OPERATION
2.2 SDRAM
U6200 [sheet 6, B/C7] is a 128Mbit with 32-bit bus wide synchronous dynamic random access memory (SDRAM) IC. For SDRAM accesses, a memory clock of up to 166 MHz that synchronizes data access is sent to the chip at pin 68. Data commands for accesses are coded in the
M_RAS_L and M_CAS_L signals (pins 18 and 19), and data read/write selection is done by the
M_WE_L signal (pin 17). The address to be written or read is given on the address bus
MA[10:0]. The 32-bit data bus MD[31:0] contains the word to be written or read after the pipeline delay of the memory chip.
2.3 FLASH
U6203 [sheet 6, C3] is a 32Mbit with 16-bit bus wide Flash memory IC but only 8-bit wide data bus is used in the system due to the limitation of CS98200. U6203 shares the memory address with SDRAM (U6200) but the data is a dedicated one from CS98200. Flash access is asynchronous and does not use a memory clock.
U6204 and U6205 [sheet 6, 4A-D] are buffers between the SDRAM and FLASH, and they have their Output Enable pins tied to common pull-down resistors, with test points, allowing the manufacturing plant to disable these buffers (thus releasing the FLASH address/data bus) during programming. Half of buffer U6204 (2A/B[1..8]) is used to condition the 8 memory control signals, and is given its own enable and direction-control signals (with independent test points). This allows the manufacturing plant to maintain control of the SDRAM during both write and read-back phases of In-circuit test.
2.4 ROMULATOR
J6200 [sheet 6, B/C2] is the ROMULATOR connector for the debug purposes of software development. The console Main board provides a footprint for the required 60-pin ROMULATOR connector but not populated in production. This connector will allow access to the FLASH address and data busses, as per the Cirrus reference design. Pin 59 shall be tied into the console reset circuitry, allowing it to access the CS98200 and keep the console FLASH in reset while running off the ROMULATOR.
U6203 can be programmed not only from the ROMULATOR connector during development but also from CD/DVD driver in the field. During re-programming in the field via CD/DVD driver, the operating and new program are held in SDRAM. Power failures during field Flash update could result in the console being made completely inoperable.
7
THEORY OF OPERATION
3. Communications Busses and Interface Blocks
3.1 Communications Busses
3.1.1 I
2
C Bus
There are two I 2 C buses: (1) the I 2 C Debug bus for software development, the connector is J7000-NV which is not populated in production; (2) the I 2 C configuration bus which configures the devices in audio path. The devices connecting to the I
2
C configuration bus and its protocol are listed in following table.
Reference
Designator
Vendor
Number
Protocol Address
Byte
U4000 TEA6422 I
2
Description
6-input stereo analog audio input MUX chip (ST). No
CS pin is available on this part. ADDR pin has an internal 50K pull-up: logic high.
S/PDIF receiver. Uses the AKM_CS chip select signal to differentiate its messages from I
2
C. The AKM
U9200 AK4382A AKM 011xxxxxb mix-down DAC. “w” is the write bit. The 8 data bits of the 16-bit protocol are driven by the AK4112B when w is 0.
Stereo DAC for the CS98200 Mix-down path. Uses the AKM_CS chip select signal to differentiate its messages from I
2
C. The AKM address separates its messages from those for the S/PDIF receiver.
*Note: "w" bit can be either 1 or 0 depending on read/write.
3.1.2 SPI Bus
The CS98200's (U7003) built-in SPI interface is used to control two subsystems in the console, the VFD (interface connector is J6500 [sheet 13, B8]) and the Tuner Assembly
(interface connector is J6000 [D8]). U6802 [A-C6] is the buffer between CS98200 and the two subsystems. These subsystems must timeshare the SPI resource.
For the outbound data (data stream from CS98200 to subsystems), both subsystems have a signal which uniquely identifies when the SPI data sent from the CS98200 is valid for them.
For the VFD module, the VFD_STROBE indicates it is the target. For the Tuner Assembly, it is SPI_SEL (which becomes TNRBD_SEL once buffered). These signals are the key to timesharing the SPI bus. Note the differing polarities associated with the signals.
For the outbound data (data stream from subsystems to CS98200), each subsystem interacts with the CS98200 differently, as follows:
• The VFD module allows for bi-directional communication, but timeshares a single wire in half-duplex mode to accomplish this. To receive SPI data from the VFD, the CS98200 must therefore use the SPI configuration option which allows receiving on the same pin used for transmission (pin 196). See the CS98200 register spec for details.
• The Tuner Assembly will use SPI in true bi-directional, full duplex mode, although the
CS9200 will be the master of all transfers. The TNRBD_DATAIN signal, which ties to the
CS98200's SPI receiver, is used for receiving. Again, see the CS98200 register spec for
SPI configuration details.
8
THEORY OF OPERATION
3.2 Interface Blocks
3.2.1 Vacuum Fluorescent Display (VFD)
This vacuum fluorescent display is a custom, stand-alone VFD module manufactured by
Futaba. It includes the VFD glass assembly, as well as all power supply and control/refresh electronics, and a ribbon cable interconnect to the console main board.
The console VFD module interface with the Main board is by a flexible cable via connector
J6500 [sheet 13, B8] which has 5-pin as listed in following table:
J6500
Pin
1
2
3
4
5
Signal Function
+12V
Strobe/
Ground
Clock
Data
+12V supply for the module.
Strobe for serial protocol (low when sending VFD data).
Power supply/signal ground.
Clock for serial protocol. Normally high here at the connector.
Data for serial protocol. Normally high here at the connector.
Note: (1) There is a buffer, U6802 with open collector between VFD and the CS98200. The buffer is required to level-shift the 3.3V logic levels associated with the SPI interface to the 5V logic levels required by the VFD module.
(2) The VFD module has built-in 1.5K Ohm pull-up resistors on the Clock, Data and Strobe signals. There are no such pull-ups on the console Main Board; therefore, these signals will not be measurable at connector J6500 unless the VFD is attached.
3.2.2 Button Board
The console has 6 buttons on the top leading edge. The buttons are physically located on a small assembly which connects to the Main Board via ribbon cable into J6700 [sheet 8, D8].
Software continually monitors these buttons to detect and de-bounce a key press. Pull-down resistors are provided to hold KEY inputs to logical 0 (ground) when no buttons are pressed.
Interconnections to the buttons are in the form of a 2x3 row/column matrix of key closures.
Each button is therefore identified by its unique row/column position.
The arrangement of buttons on the front of the console is as follows. Each circular button represents a key closure which shorts a given KEYOUT row signal to a given KEYIN column signal when a button is pressed. For example, ON/OFF shorts the KEYOUT0 signal to KEYIN0 when pressed:
KEYOUT0 KEYOUT1 KEYOUT2
ON/OFF SOUR
VOLUME
+
ENTER
EJECT
KEYIN0
KEYIN1
9
KEYOUT
2
THEORY OF OPERATION
Row Signal
KEYOUT
1
KEYOUT
0
Column Signal
KEYIN
1
KEYIN
0
Button Name
Button
Position
4
2
(labeled 5
STORE on premium console)
3
3.2.3 IR Receiver
The 321 Series II console includes a narrow-band IR receiver module. The IR receiver gets the
IR signal from the remote control and passes it to the Main board via the Button board. The IR signal information enters the Main board at J6700 pin7.
The console is capable of being controlled by the universal IR remote controls (basic and premium) developed specifically for the 3
•
2
•
1 Series II, as well as 3rd party remote controls which either include the 3
•
2
•
1 II codes or can learn them (such as a Crestron universal remote). A narrow-band IR receiver module is provided on a printed circuit sub-assembly to permit mounting in the front of the console. This module amplifies the incoming IR data stream and removes its 37.9 kHz AM sub-carrier. The CS98200 handles the decoding of inbound control commands from IR receiver module. Hardware assistance/noise filtering is provided in the chip for this.
3.2.4 DVD Driver
J3200 [sheet 7, B/C5] is the connector for the DVD ROM driver which connects to the ATAPI bus on Main board. The DVD ROM provides video source and one of the internal audio sources.
It can be configured either master or slave mode and share same ATAPI bus and reset signal with HDD but with separate select signal.
3.2.5 Hard Disk Driver
J9341 [sheet 7, B/C4] is the connector for the hard disk driver (HDD) which connects to the
ATAPI bus on Main board. The DVD ROM provides one of the internal audio sources. It can be configured either master or slave mode and share same ATAPI bus and reset signal with DVD
ROM but with separate select signal. HDD is only populated on premium product.
3.3 Ethernet
The 3
•
2
•
1 Series II premium console includes an Ethernet connector J9640 [sheet 9, B/C2] and a Cirrus CS8900A 10baseT Ethernet Controller IC U9641 [sheet 9, B/C6] which interfaces to the
CS98200 via the parallel Host bus. Since this bus is timeshared with the ATAPI drives, RISC0 is expected to handle all interactions with the chip, providing essentially a transmit and receive
FIFO for RISC1 to use for sending/receiving Ethernet packets, as well as a software API for high-level control of the chip (power up/down, etc.).
The LINK LED, LAN LED and isolation transformer are included inside the Ethernet connector,
J9640, visible from the back of the console. The green LED (D9640) is connected directly to the LINK LED output of the CS8900A Ethernet Controller IC (U9641) via R9656. The yellow
LED is directly connected to the LAN LED output via R9657.
10
THEORY OF OPERATION
4. Audio Path
The audio path block diagram is as follows:
11
THEORY OF OPERATION
4.1 Analog Audio Path
4.1.1 Analog Input
There are total of 7 analog input sources: 6 external analog inputs and one internal analog input. Those 6 external analog inputs are: 1 tuner from Tuner board via J6000 [sheet 13, D8],
3 external (AUX, CAB/SAT and TV) from connector J201 [sheet 10, B-D8], 2 network speaker
(Zone1 and Zone2) from J202 [sheet 11, C3] via differential input buffer U8406 [B/C1]. The internal analog input is from the mix-down DAC U9200 [C8] which convert I2S audio stream from the CS98200 to an analog signal which is one of the two inputs to the summing circuit
U9100 [C5].
The 6 external analog sources are selected by the TEA6422 (U4000 [sheet 10, B5]) analog audio MUX. The MUX is controlled via the CS98200's I2C bus. The MUX has the ability to direct any one of the 6 input sources to any one of the 3 output.
4.1.2 Analog Output
Only the 3rd output of the TEA6422 (U4000) analog audio MUX is used (the 1st and 2nd output channels are unused) and the 3rd output of the TEA6422 is summed into the NJM4556 buffer amplifiers (U9100 [sheet 11, C5]). The mix-down DAC outputs are also summed into these buffer amplifiers. When one of the 6 external analog audio sources is selected as the console analog output, the 3rd output of the TEA6422 is active and the output of the mix-down DAC is placed into reset through the reset bit in the I2C registers in order to reduce the noise level to minimum. In a similar way, when the CS98200-generated down-mix is selected as the console analog output, the 3rd output of the TEA6422 is muted and the output of the mix-down DAC takes active.
The analog output goes to the bass module via the connector J100 [sheet 10, B2]. The
TEA6422 analog input MUX supports 2Vrms signal levels. The maximum amplitude of the differential outputs of the AK4382 DAC is approximately 2Vrms. External analog input signals may be up to 2Vrms without experiencing distortion or clipping-- absolute maximum allowable input levels are about 3dB higher.
4.2 Digital Audio Path
4.2.1 Digital Input
There are total of 6 digital input sources: 4 external digital inputs and 2 internal digital input.
Those 4 external digital inputs are: AUX, CABSAT and TV from connector J201 [sheet 12, C8] and optical signal from J8000 [B8]. The 2 internal digital input sources are from the DVD ROM driver via connector J3200 [sheet 7, B/C5] and hard disk driver (HDD installed on premium product only) via connector J9341 [B/C4].
The 4 external digital sources are directed to the AK4112 U8001 [sheet 12, B/C5] SPDIF receiver. The SPDIF receiver is controlled via the CS98200's I2C bus. The 2 internal digital input sources (both DVD ROM driver and HDD) feed the audio data streams to CS98200 via the
ATAPI bus for decoding and processing.
12
THEORY OF OPERATION
4.2.2 Digital Output
The AK4112 (U8001) SPDIF receiver has two output options for all the 4 external digital input sources: (1) bypass one of the 4 external SPDIF input steams to the digital MUX U8002, and
(2) recover the SPDIF input stream, convert to I2S and feed to CS98200. Those two output options can be selected independently. The audio streams from both DVD ROM driver and HDD are decoded and processed by CS98200 and then output to the digital MUX U8002 [sheet 12,
C3]. The digital MUX U8002 selects one of its two inputs and feeds the output to the bass module via isolation pulse transformer T8600 [sheet 12, C1] and connector J100 [sheet 10, B2].
The 3
•
2
•
1 Series II console provides a digital output stream for the Smart Speaker compatible speaker system. This output is capable of sending up to 192 kHz S/PDIF streams when driven by the CS98200. The outbound S/PDIF signal is roughly 2 Vpp, allowing diode-termination techniques in the Smart Speaker. When external analog sources (or the AM/FM tuner) are played, the required data is not available on the digital audio output. When CD/DVD discs are played, the frame rate will be generated by the CS98200 to be compatible with the disc. When external digital inputs are played, the AK4112B receiver will phase-lock to the inbound SPDIF stream, derive bit/frame clocks from it, and provide these clocks to the CS98200 for use in clocking the S/PDIF output stream.
4.3 Interaction Between the Digital and Analog Inputs
The CS98200 has some ways to decide which input type should be played for each source.
When playing the external inputs, the external digital inputs have preference, and shall be played whenever an input stream is found to be present. If none is available, the associated analog inputs shall be selected, thought the digital inputs shall continue to be monitored for streams that might appear later. Digital signals are routed through the CS98200, which examines them for available data in any of the supported formats (PCM, MP3, AC3, MPEG2 or DTS).
As for the selection between optical and electrical digital input, the console external optical input is assigned through the on-screen display (OSD) to a particular input source. To allow this, the hardware has provided the optical signal a unique input into the AK4112B S/PDIF MUX/receiver.
When playing the source assigned to the optical input, the software should first check for the presence of an optical input signal-if none is present, the coax digital input (S/PDIF) should be examined. If, again, no signal is present, the external analog inputs should be played. The external analog inputs may be played while detection of a valid digital stream is in process.
5. Video Path
The video DAC’s inside CS98200 may be configured for either S-video and CVBS outputs or
Component Video (YPrPb or RGB) output. The component output can be configured either interlaced or progressive scan (the console's video low-pass filters have been designed to support both standard and progressive-scan video outputs). A separate set of Component Video output jacks is provided. The “Y” jack includes a switch normally closed to ground that is opened when a cable is inserted into the jack. The resulting signal “COMP_SENSE” is monitored by the CS98200.
13
THEORY OF OPERATION
A pair of signal relays, K5000 [sheet 13, C2] and K5001 [B2], permit selection of internally generated Composite and S-Video signals or pass-through of external Composite and S-Video signal inputs to the output Composite and S-Video connector J201. When VIDEO_SEL is low, the console is configured as video pass-through mode which plays external video signals.
When VIDEO_SEL is high, the console is configured as playing video signals from CS98200.
The Component Video (YPrPb) output should be selected whenever the COMP_SENSE signal is high. Also, when Component Video is selected, the VIDEO_SEL line shall remain low at all times. This prevents attenuation of the video signal if both sets of outputs (Composite, S-Video and YPrPb) are connected to other equipment.
6. Tuner Electronics
The tuner function is implemented on a dedicated PCB which has no other essential functions or hardware. This has the advantage of the console working without needing the tuner board in circuit. The topology of the tuner circuit itself is very similar to the 321 Series I tuner. There are three variations of the final assembly. See SD270575 for details.
Note: Refer to the Tuner PCB schematic sheets, 270575, for the following information.
6.1 Main PCB Interface
Interfacing the Tuner PCB to the Main is accomplished through a 13 connection flat-flex cable to connector J1 [sheet 2, C8]. Below is a table describing the pin functionality…
Pin
Number
1 +12V
2
3
4
5
Supply_Freq_Sel
Gnd
Name Direction
Tuner_L
Tuner_R
6 Gnd
7 Tnrbd_Sel
Supply
Function/Notes
Sole supply voltage for the tuner board, in normal operation it draws <100mA. Local 10V(U18) and 5V(U19) is derived from this
Output Logic Level output setting the main board switching power supply frequency determined by a lookup table in the ST micro (ST72324) for interference avoidance. AM only.
Low, Fsync=97.324kHz
High, Fsync=100.800kHz
Supply Return for all signals. No differentiation in grounding is implemented on the tuner board.
Output Left channel analog audio output.
Output Right channel analog audio output.
8
9
Tnrbd_Clk
Tnrbd_Datain
Input Buffered SPI select line for communicating with the
ST72324 from the CS98200 on the main board. Note, this comm bus is shared with the display so this line allows for the differentiation of commands between systems.
Input Buffered SPI clock line for communicating with the
ST72324 from the CS98200 on the main board.
Output SPI data from the ST72324 to the CS98200. +5V logic levels.
10 Gnd
11 Tnrbd_Dataout Input
12
13
Tnrbd_Reset
Tnrbd_Flash
Input
Input
Buffered SPI data output from the CS98200 to the
ST72324.
Hard Resets the ST72324
Control Signal to apply programming voltage to ST72324 in order to reprogram internal flash.
14
THEORY OF OPERATION
Detailed control of the tuner is implemented by the ST72324 (U7001 [sheet 3, C6]) microprocessor upon instructions from the CS98200 SPI bus on the main board. U7001 is responsible for:
•
Handling all control commands from the main board.
•
Communicating with the PLL IC (U2074 [sheet 2, C/D3]) via the CCB bus to set it’s various
•
I/O pins as well as setting the desired local oscillator frequency.
•
Querying the RDS chip (U2200 [sheet 2, D6]), if present, for relevant messages.
•
Processing the seek algorithms based on S-Meter and audio levels, as well as IF-count.
•
Storing the seek/stop and stereo levels during tuner alignment for use in the field.
The general purpose input and output ports on the PLL IC (U2074) are set up as follows:
U2074 Pin
Number
7
8
9
14
Name Direction
FM/AM
IF/MUTE
AM/FM
10 FORCE-
MONO
11 Supply_Freq_
13
Sel
IF/MUTE
ST-LED
Output
Function/Notes
O.C. Output Enables the audio output of the detector when low.
See pin 13.
Output Switches the mode of detector IC U2000 and sets which output (FM : pin 23, AM : pin 24) is active.
Inactive => high impedance.
Output
Output
Input
Input
Controls Q2000 which switches power to the FM front-end and the IF amplifier. In AM mode these are both switched off.
Forces the detector IC to decode FM into monoaural audio.
See above table
When pin 8 is high impedance R2013 pulls the DC level of the IF/MUTE line high (>3.5v), audio is muted and the output of the FM IF buffer appears on this line. This is fed to the IF counter on pin 13.
This is used during seek to determine if a valid broadcast signal is present. Note that this output is dependent on having TU-LED (Pin 6) low indicating a sufficient input IF level.
Used to monitor the stereo indicator coming from pin 7 of U2000. The state of this pin is shown on the stereo icon display or in the OSD FM status window
15
THEORY OF OPERATION
6.3 FM Tuner
6.3.1 FM Tuner Front End Circuitry
The FM RF signal from the antenna is input via the F or PAL-type input connector J2001 [sheet
1, B8] and goes to the FM front-end module. The antenna supplied with the console is the standard quarter-wavelength dipole antenna.
The FM front-end [sheet 1, B/C8] contains a tuned RF amplifier, FM local oscillator and a mixer.
The 10.7 MHz IF output signal (pin 7 of the module) passes through a 10.7 MHz ceramic filter,
CF2000 [C7], an FM IF amplifier Q2001 [C6] and then through a second ceramic filter, CF2001
[C6]. Transistor Q2001 and related circuitry form the FM IF amplifier produces about 15 dB of voltage gain and provides the proper impedance matching for the ceramic filters. These FM IF filter stages reject unwanted FM stations and noise.
The software that controls the FM tuner has provisions for an IF offset to optimize tuner performance for a given range of IF filters. The possible values of IF offset are -25kHz, 0, and
+25kHz, with the available offsets determined by twice the reference frequency (2 x 12.5kHz).
The software measures (“counts”) the IF frequency, and this offset is added to the count. In tuner alignment, the value that minimizes THD at 98.1 MHz for an un-modulated signal is chosen and stored before other stop levels are set.
6.3.2 FM Tuner Output Circuitry
The output signal from CF2001 is fed to the LA1837 AM/FM detector IC, U2000 [C4] at pin1.
This device contains the FM IF limiter, FM detector, FM stereo MPX decoder, and the S-meter circuitry used for seek processing. The FM IF input signal to the LA1837 goes through several gain/limiter stages and then to a single-tuned, coil-based discriminator circuit. The discriminator coil, T2001 [C5], is adjusted for minimum second harmonic audio distortion. The recovered FM composite signal appears on pin 23 of U2000.
The composite audio signal is filtered by C2018 [C2] and fed back into pin 22 of U2000. The value of C2018 is chosen to optimize FM stereo separation. The stereo MPX decoding is also performed by U2000 and the decoded left and right signals are output on pins 20 and 21. The pilot PLL VCO is completely internal to the LA1837 detector IC, not requiring an external 456 kHz ceramic resonator as in older designs. The pilot PLL loop filter is formed by C2014, R2016, and C2016 on pin 14.
FM de-emphasis for the left audio channel is set by C2026, R2022 and the output impedance of pin 21 of U2000 (3.3k). FM de-emphasis for the right audio channel is set by C2027, R2023 and the output impedance of pin 20 of U2000 (3.3k). For a US unit the capacitor values are set to produce 75µS de-emphasis, and for Europe/Japan they are set to produce 50µS de-emphasis.
The resultant de-emphasized and amplified audio signal appears on pins 16 and 17. Signals above the audio band, including the 38 kHz sub-channel demodulation components are cut off at the bass module by the input filters in A/D converters and the audio DSP is used to create a notch filter at 19 kHz to reject the 19 kHz pilot tone, thus removing the need for external MPX filters.
16
THEORY OF OPERATION
6.3.3 FM and AM S-Meter and Stop, and Stereo Levels
The FM and AM S-meter signals, pin 11 and 12 of the LA1837 respectively, are analog voltage levels that indicate the FM IF and AM RF input signal levels. These signals are connected to the
A/D inputs of the ST72324. During factory tuner alignment the appropriate test signal levels are injected into the UUT and the resultant ADC values for FM stop level, FM mono/stereo level and
AM stop level are stored in the EEPROM U7000 [sheet 3, D3].
The stop level is the voltage level above which the signal strength is deemed strong enough to warrant stopping on a channel during seek. This does not mean that the unit will always stop on a station if the S-meter level is high enough since an IF count is also performed during to ensure that the correct IF frequency has been obtained.
The stereo level is the level above which a channel that has been automatically forced into mono will return to being decoded as stereo (if stereo material is present).
When first tuning to a station the unit defaults into mono for one half second to prevent a mono station from coming through as noisy stereo. If the initial S-meter read is greater than the stereo level the unit switches into stereo. After the initial S-meter read the unit switches between stereo and mono in the following way. Every 500ms the S-meter is read and the unit switches from stereo to mono if it reads one S-meter level below the force-mono level. The unit switches from mono to stereo after ten consecutive readings of S-meter level above the stereo level. The reasoning for using one sample to force-mono but ten consecutive samples for stereo is to ensure that a unit with S-meter reading levels close to the threshold do not switch between noisy stereo and clear mono too often. The set voltage between the force-mono and stereo thresholds also helps to prevent unnecessary switching between mono and stereo, mainly due to modulation noise on the S-meter capacitor.
Note: Switching stereo “on” via the On Screen Display will enable the above automatic forcemono function while switching it “off” disables this automatic function and ALWAYS forces the unit into monaural decoding. Also note that the stereo icon on the front display and the stereo status flag on the OSD indicate the state of the ST-LED line, which indicates detection of the
19 kHz pilot tone present in stereo broadcasts. In force-mono (automatic or otherwise) this will always be low even if the actual broadcast is in stereo.
The nominal FM stop and stereo levels are:
FM stop : 30 dBf @ 98.1 MHz
FM stereo : 42 dBf @ 98.1 MHz (force-mono approx 2dB lower)
17
THEORY OF OPERATION
6.4 AM Tuner
The signal from the external AM loop antenna enters through the 2.5 mm AM jack, J2000 [sheet
1, D8], and is fed to the AM front end module, T2000 [D6]. The antenna input is balanced by placing C2000 [D7] between one side of the input and ground, reducing electric field interference. The front end module contains the varactor-tuned RF and Local Oscillator (LO) tracking circuits. This part is pre-tuned by the manufacturer for proper alignment with AM antenna
PT199824-002, and is further adjusted during factory alignment, if necessary. The RF tuned output is fed to the AM buffer FET transistor Q2002 [D6] and the buffered output is sent to pin
27 of U2000 [C3] which contains the AM RF amplifier, mixer, IF amplifier, AM detector, and AM
S-meter circuitry. The 450 kHz AM IF output signal that appears on pin 2 is filtered by the IF filter, T2001 [C5], and fed back into the IC on pin 4. The AM IF signal is demodulated by U2000 and the audio output is sent to pins 20 and 21, to pass through the low pass filter used in FM for de-emphasis.
In order to avoid having harmonics of the main board switching power supplies interfere with the
AM tuner the switching frequency is controlled by F_SYNCH, a clock output from U3 [console schematic sheet 14, C4] on the main board. The signal Supply_Freq_Sel (via lookup table based on AM station) is used to vary the output of F_SYNCH between two frequencies that will avoid the selected channel frequency and its image the best.
The AM seek stop processing and factory alignment is performed in a similar fashion to FM mode processing. The nominal AM stop level is 56 dBµV/m @ 1080 kHz.
6.5 Phase-locked Loop Tuning
The AM and FM local oscillators are controlled by the PLL IC, U2074 [sheet 2, C3]. The microprocessor selects the AM or FM band and the particular frequency. The 7.2 MHz clock reference is generated by the microprocessor which is the stable crystal oscillator frequency divided by 2. The 7.2 MHz oscillator is divided down to produce a 12.5 kHz reference frequency in FM mode and a 10 kHz (9 kHz for European and Japan units) reference frequency in AM mode.
U2074 [sheet 2, C/D3] divides down the AM or FM LO input, compares it to the appropriate reference frequency and generates an error signal that is output on pin 19.
This error signal is integrated and amplified by an active lead-lag filter formed using an internal
FET inside U2074 and associated components connected to pins 19, 20 and 21. C2096, C2097,
R2079, R2080 and R2081 control the gain and pole-zero locations of the filter. The values of these components are chosen to ensure stability of the PLL while providing sufficient speed, moderate overshoot, and symmetric up/down settling time. The resulting signal output at pin 21 is used as a tuning voltage and is fed back to the AM and FM front-ends.
The AM tuning voltage is further filtered by R2078 and C2095 and is fed back to the common node of the varactors inside the AM front end, T2004. The tuning voltage varies the capacitance of the varactor diodes, which in turn simultaneously tunes both the AM antenna and the
AM LO. In FM mode, the tuning voltage is filtered by R2077 [sheet 2, D1] and the input capacitance of pin 5 of the FM front-end (0.047uF) [sheet 1, B/C8]. As in the AM case, the tuning voltage is fed to varactors which tune the LO frequency and RF filtering.
18
THEORY OF OPERATION
6.6 RDS
European tuners contain additional components for the decoding of Radio Data System (RDS) information. The LC72722 Radio Data System (RDS) decoder IC, U2200 [sheet 2, D6], is a single-chip system IC that implements the signal processing required by both the European
RDS standard and US RDBS system. RDS/RDBS systems can send digital information over the airwaves along with the standard FM signal by adding a digitally modulated 57 kHz subcarrier to the normal FM composite signal. The LC72722 includes a bandpass filter, demodulator, synchronization, and error correction circuits. The input (pin 2) to the RDS IC comes from
Q2003 [sheet 1, C1], which buffers the FM composite signal at pin 23 of the LA1837. The time base for the decoder is a crystal oscillator formed by the 4.332 MHz crystal, Y2200, the inverter internal to the IC across pins 12 and 13, and the two shunt capacitors, C2205 and C2206.
Control of the RDS IC is achieved by using the same bus interface used for the PLL IC.
PS3
•
2
•
1 Series II Speaker System Theory of Operation
The following information describes the operation of the PS3
•
2
•
1 Series II bass module.
Note: Refer to the bass module amp and DSP schematic diagrams, 270921, for the following information.
1. Components
The PS3
•
2
•
1 Series II Speaker System consists of:
•
The PS3
•
2
•
1 Series II Bass Module, 273031-*
•
Qty 2 Array Speakers, 255198-* or (Series II GS) 269990-*
•
Array Speaker Cable, 255123-* or (Series II GS) 269984-*
•
Line Cord 260082-*
•
Bass Module Interface Cable Assembly 269997-*
* Dash variants may vary.
The components above permit connection to the AV3
•
2
•
1 Series II console.
2. Bass Module Interface
Control and audio input to the bass module is by means of a 13-pin interface connector and associated bass module to console cable. This interface provides up to 15 watts (average) of unregulated DC power for operation of the connected console. The bass module is controlled through a single-wire serial connection which utilizes the Smart Speaker protocol on a 4800
Baud, half-duplex, bi-directional connection. Audio from the console is transported to the bass module via stereo analog and/or S/PDIF input. The analog and digital audio inputs may be used in conjunction to allow the transport of multi-channel audio information. A separate MUTE line is also provided to allow the console to immediately mute the audio output. Additionally, there is a control line which completely powers down the DSP section of the bass module to reduce power consumption, but it is not implemented in production.
19
THEORY OF OPERATION
2.1 Interface connector and cable descriptions
The 13-pin interface connector is wired in a one-to-one fashion with the console connector.
The pins/signals are as follows:
Pin Number Signal Description Wire Type/Gauge
1 Vunreg #20AWG
2 GND #20AWG
3,11 SPDIF +/- #28AWG twisted pair
4 Mute #28AWG
6
7
9,8
12,10
AGND
DGND
Audio Left +/-
Audio Right +/-
#28AWG Drain/shield over Audio Right & Left
#28AWG Drain/ shield for SPDIF+/-
#28AWG twisted pair
#28AWG twisted pair
Shell SGND Overall tin-copper braid shield
2.1.1 Smart Speaker
This is a single-wire 4800 baud, half duplex connection. It operates on an open-collector principle and follows the hardware and software protocol defined by the SmartSpeaker interface specifications. It operates similar to RS-232, but with a 0-3.3/5V level and positive logic.
2.1.2 MUTE Control
This is a positive logic control input to the Powered Speaker. Asserting this line (+3.3V) forces a hardware mute of the power amplifiers. This input is internally pulled logic high in the Powered
Speaker and the input must be pulled to logic low by the console to allow audio to be heard.
2.1.3 S/PDIF
The S/PDIF input is a fully differential input which is terminated by a pair of back-to-back diodes only. Supported sample rates are 44.1 kHz and 48 kHz.
2.1.4 Analog Audio Input
The analog audio inputs are fully differential with an input impedance of approximately 10k ohms. The full scale input is 2.0Vrms.
2.1.5 DSP_SHUTDOWN
This is a positive logic control input which, when asserted logic high, shuts down the SMPS feeding the entire DSP and signal processing path. It is not implemented (via depopulated components) in the production design.
2.1.6 Vunreg
This is a DC supply which provides unregulated power for use by the console. Approx. 30W peak is available from this supply. It is internally fused at 4A.
20
THEORY OF OPERATION
2.2 3
•
2
•
1 Series II Bass Module Details
The bass module contains all the active audio processing and amplification electronics of the
3
•
2
•
1 Series II System. The rear end cap of the bass module provides access to the following components:
•
Line cord socket
•
Power Switch (European only)
•
System Connector (13-pin)
•
Array Speaker Connector (DB9-S)
All the above components are mounted on the I/O Printed Circuit Assembly, part number
270926-001, which is, in turn, secured to the end cap via a metal bracket. The dash suffix is used to denote the various AC voltage variants.
All other electronics reside on the DSP/Amplifier PCB Assembly. The DSP/Amp PCB is secured to the extruded aluminum heat sink (which is glued to the back baffle of the module enclosure) with a metal bracket. This bracket provides sufficient compression force to the PCB to maintain good thermal contact to the heat sink of the audio power amplifiers, rectifier diodes, and preregulator FET.
The power transformer for the system is directly mounted to the end baffle of the module above the heat sink.
2.2.1 I/O Printed Circuit Assembly
Note: Refer to the Input/Output (I/O) PCB schematic diagram, 270926, for the following information.
The I/O printed circuit assembly contains the AC input connector J1 [C4], the line switch S1 [D3] and line fuse F1 [C3]. Connector J2/J5 [D2], depending on the dash (-xxx) variation, provides the primary power connection to the power transformer. A location for a MOV (VR1 [C3]) is provided, but is not populated in production.
Connectors J6 [B7] and J7 [D8] connect the I/O PCB to the DSP PCB. J6 connects to a 16position ribbon cable which carries the S/PDIF and audio inputs and control signals to/from the
DSP board. J7 connects to a 10-position cable that brings the array speaker amplifier outputs and Vunreg/GND onto the I/O PCB. C7-9 provide RF ground coupling between the various ground pins and structures on the board. C1, C3, C4, C5, and C10 are DC blocking caps on the differential audio inputs and associated GND. C6 is the bulk storage capacitor for the
Vunreg supply. All of the signals described in section 3.1 are connected to the 13-pin system connector J3 [B2] on this board.
2.2.2 DSP/Amplifier Printed Circuit Assembly
This board provides the following major functions:
Note: Refer to the DSP/Amplifier PCB schematic diagrams, 270921, for the following information.
21
THEORY OF OPERATION
2.2.2.1 Power rectification, pre-regulation and filtering
J5 [sheet 4, D6] connects the secondary winding of the power transformer to the circuit rectifiers
D7-10 [C/D 5/6], which form a full-bridge rectifier. The DC output of the rectifier charges capacitor C22 [D2] to a controlled peak voltage, via FET Q4 [D4]. The controlled peak voltage is
15.75V (± 0.75V). The pre-regulator circuit formed by ZR1 [D5], Q2-3 [C4/5], R7-13, and C21,
24-5 cause Q1 to switch off once the limit voltage has been attained.
The diodes D7-10 and Q1 are required to have good thermal contact to the heat sink. This requires a deflection of 0.5 to 1mm of the thermal material applied in the interface. Q5 and associated components provide a soft-switching function
2.2.2.2 Control Power generation
Both a 5 volt and a 3.3 volt power rails are generated for the DSP and audio source control circuits.
U100 [sheet 4, B5], L70 [B4], D11, and C30, C31 form a buck switching regulator for the 5 volt supply. The nominal switching frequency is established by components R16 and C33 [B6]. A modulating signal derived from the transformer secondary is coupled to the oscillator circuit via
C37. R18 and R19 establish the magnitude of the modulating signal. C38 filters unwanted harmonics and line noise from the signal. Q6 [A6] allows the Inhibit pin to be pulled low from the console, which disables the power supply, forming the DSP_SHUTDOWN function.
U101 [A3] generates the 3.3 volt supply from the 5 volt supply. C42 prevents oscillation of the output of U502 as well as assisting to manage voltage ripple due to load fluctuations. U6000
[sheet 1, D5] monitors the 3.3V and issues a reset of the DSP if this supply ever drops below a regulation threshold of 3.08V.
2.2.2.3 Audio Power amplification
Dual Audio Amplifier IC’s, U150 [sheet 5, C/D3] and U250 [A/B3] provide the power amplification for the external speaker arrays. The array outputs are available on J150 [B/C1]. A similar amplifier, U350 [B/C6], provides power amplification to the bass module woofer via connector
J350 [C4]. Both inputs of U350 are wired in parallel and both amp outputs are provided to the woofer connector J350. Each output of the amplifiers have an RF de-coupling capacitor of
.01uF, C152 and similar, shunting the high-frequency components of the signal through a series resistor of 3.32 Ohms, R162 and similar. The series resistor creates a lead in the pass characteristic at approximately 4.7MHz in order to maintain stability of the power amplifier.
The differential inputs of the power amplifiers are coupled to the output of the Audio DAC via
1uF aluminum electrolytic capacitors, C156, C157 and similar. A shunt resistor and capacitor,
R151 and C156 and similar, form the termination of a second-order low-pass filter described later.
2.2.2.4 Power Amplifier control, monitoring
The MODE signal is a three-level signal generated by Q450 [sheet 5, A8], Q451 [B8], Q452
[B8], D450, R450, and R451. IF the /STDBYout signal is asserted low, the internal bias of the
MODE pins of the amplifiers will cause the signal to drive to ground. This causes the amplifiers to enter the “Stand-by” low-power state. The internal bias to the amplifier signal inputs is turned off causing the inputs to drift to ground. Stand-by should not be entered while the DAC driving the signal inputs is out of the reset state.
22
THEORY OF OPERATION
When the /STDBYout signal is high, the MODE pin will be either within the 3.3-6.4 volt range
(mute), or near VRAW (active), as controlled by the MUTE signal and Q450, D450. When
MUTE is high, Q450 saturates, causing the MODE voltage to be driven to approximately 5.4
volts. R450 assures the MUTE signal is active any time the DSP (U7000) is not driving it.
The open-collector diagnostic outputs of the three amplifier IC’s are summed into the /DIAG signal to the DSP (U7000 [sheet 1, B/C 4/5]). R453 [sheet 5, C7] pulls the signal to logic false
(high) when none of the amplifiers is asserting the signal. Currently /DIAG is unused by the
DSP.
The Clip signals of the amplifier IC’s driving the array speakers (U150, U250) are summed into the /ARRAYCLIP signal. R454 [sheet 5, D2] holds the signal false (high) if neither amplifier IC is asserting the clip signal. A similar arrangement is used for the bass amplifier with the /
BASSCLIP signal.
2.2.2.5 Digital-to Analog Signal conversion and conditioning
Processed audio signals are converted to amplifier drive signals by the DAC portion of the
Codec (CS4228), U4000 [sheet 2, C/D2]. The single-ended outputs of U4000 have a full-scale output of nominally 1.31 Vrms. They also have significant out-of-band noise as well as the expected sigma-delta conversion noise due the IC’s location in the digital portion of the circuit.
Resistor arrays R4300, R4301, R4302 [B2] serve to terminate the negative signal of the power amplifier differential inputs and provides the source impedance for the first stage of the secondorder low-pass filter. The Capacitors C4300-11 provide both the switching noise suppression on the individual signal and one of the two poles for the second-order lowpass filter.
Resistor arrays R150 [sheet 5, C4], R250 [B4], R350 [B8] increase the source impedance of the second portion of the filter. The shunt resistance of R151 and similar and the shunt capacitance of C158 and similar form the second pole.
Analog output gain for a 0dbFS digital signal…
•
DAC output
•
Filter Gain
•
Amplifier Gain
•
Total Gain
1.3Vrms
-8dB
26dB
18dB (8x)
•
Max amplitude 10.4 volts RMS or 14.7 volts peak
Note that DSP gain managers limit the signals to avoid clipping, which is likely to occur beyond
11 volts peak.
2.2.2.6 Analog-to Digital Conversion
The analog inputs (J7100, pins 2, 3, 5, 6 [sheet 3, C7]) are coupled to the ADC differential input of U4000 [sheet 2, C/D2] through a RC t-network which utilizes the inherent element matched values of quad resistor packs R1001 and R1005. This provides good common-mode rejection on the inputs as well as providing a lowpass filter function.
The A/D conversion sample rate is determined by the SHARC_CLK providing a 128Fs master clock to the converter (33.333MHz/6 = 5.56MHz) rate which ultimately yields a sample rate of
43.4kHz.
23
THEORY OF OPERATION
2.2.2.7 S/PDIF Receiver
U4400 [sheet 1, B7] provides the S/PDIF digital audio receiver function. The incoming differential S/PDIF signal is fed to U4400’s differential inputs RXP0 and RXN0 through a filter and termination network. T1 is a common-mode transformer which rejects unwanted commonmode noise, particularly important since U4400 has little or no common-mode rejection inherent to the IC design. D4502 [sheet 3, C6] clamps the signal to +/- one diode drop. This is the only
“termination” of the input signal. The assumption is that while there is a termination mismatch on the end of the twisted pair, all reflections and standing waves are eliminated by the clamping action of the diodes, i.e., the reflections never reach into the +/- one diode drop region. The subsequent resistors and capacitors form a low pass network that limits the bandwidth to just above the fundamental bit rate of the S/PDIF signal (128Fs).
U4400 provides the system MCLK at 128Fs when the S/PDIF input is active. When the ADC path is selected, the MCLK is provided by the DSP (U7000) SHRAC_CLK output [sheet 1, C3], which is routed through U4400s MCLK output (pin 10) by setting the IC into “Stop” mode via an
I2C command from the DSP.
2.2.2.8 Internal audio path
External analog and S/PDIF input signals are converted to serial digital samples that are clocked at the bit rate established by BITCLK. Each sample is 32-bits long alternate between left and right channels as indicated by the LRCLK signal. The Codec, U4000, generates
BITCLK and LRCLK in all operating modes based on its MCLK input. MCLK is programmed to be 128 times the LRCLK rate and, thus, 4 times the BITCLK rate.
The S/PDIF decoder, U4400, either generates MCLK from the bit-rate detected on the selected digital audio input, or passes through the SHARC_CLK signal when no valid digital audio input is detected or when the part is not running. The SHARC_CLK signal clocks the audio path when analog audio inputs are selected.
The analog data converted by U4000 is presented to the DSP controller U7000 on A/DOUT.
The received digital data from either S/PDIF input is transmitted to U7000 on a separate signal using the DR0A input of U7000. Both signals share the same LRCLK and BITCLK as do the audio outputs D/ADATA1-3.
2.2.2.9 Communications
Smart Speaker Interface
Smart Speaker commands from the console are received by the circuit comprised of Q6100 and
Q6101 [sheet 1, C7]. The input is level shifted to a 3.3V signal by Q6100 and is then “gainedup” with hysteresis before being presented to the PWM0 input of the DSP. This is accomplished with 3 inverters of U6100 and C6105 and is necessary as the PWM0 input uses a fast counter to determine the commands and any noise/glitching of the input destroys the message.
TAP Interface
The components used to access TAP directly onto the bass module DSP/Amplifier PCB are not populated on the production versions of this board. Any testing or troubleshooting will be performed using the Smart Speaker commands as listed in the test procedures in this troubleshooting guide. The following is for informational purposes only.
The TAP interface uses the serial ports (signals TAPIN and TAPOUT) on the Sharc microprocessor (U7000 [sheet 1, C4]). The connection is made through J6200 [sheet 3, A8]. Q6200,
R6200 and similar convert RS-232 level input communication signals to logic level. Q6201 drives the output line to 0 and 3.3V. These parts are not used, and are shown as NV (no value) on the schematic sheets.
24
THEORY OF OPERATION
DSP/Amplifier PCB LED’s
There are 2 LED’s in the system, located on the DSP/Amplifier board, a green LED (DS6500
[sheet 3, D7]) and an amber LED (DS6501). The amber LED is not populated in production.
When the main board is installed and rear cover is in place, the light produced is visible (with practice) through the rear grille as it reflects off the heat sink as well as goes through drilled holes in the PC board. R6500 and R6501 limit the current through the LED’s (as well as the
DSP controlling them). The table below explains the uses of these LED’s in production mode
(CB = Counter Blink: when one LED is on, the other LED is off!):
Green
LED
Amber
LED
Description
Off
Off
Off
On
This should never happen. If it does, it likely means
1) That there is no power –OR-
2) There is a problem with the hardware (or, perhaps, software!)
When power is first supplied, BEFORE the DSP boots, the hardware will put the LED’s into this state. If the board stays in this state there is a problem with the DSP hardware (or software).
CB, 5 Hz CB, 5 Hz Immediately after powering up AND if the LED’s remain in this mode, there is a problem with the Power On Self Test (POST): either the
FLASH did not checksum or the SDRAM memory test failed or
Once every 5 sec
1 Hz
Off
Off there was a problem initializing one or more or the audio peripherals
(U4000, U4400).
Board is powered, initialized, and waiting for a Smart Speaker command to turn on the board. The LED will be on for only 0.010 seconds!
Board is powered, initialized, has been turned on by the console (or in
ASCII TAP mode) and S/PDIF is present. When on, the LED will be on for 0.5 seconds.
CB, 1 Hz CB, 1 Hz Board is powered, initialized, has been turned on by the console (or in
ASCII TAP mode), S/PDIF NOT present. When on the LED will be on for 0.5 seconds.
Toggle Don’t care
The green LED will toggle whenever a byte is received from the
RS-232 input. This toggling will modulate the current state of the green LED, i.e. the normal 1 Hz rate may be “chopped” by incoming
RS-232 data.
CB, 5 Hz CB, 5 Hz If the board passed the POST and generally seemed to be OK, this state indicates that a catastrophic software error has occurred. The production code will stay in this mode for 1 second then do a
X ON software reset; development code will remain in this state, allowing the developer to isolate the source of the problem.
When the system is operating normally, the orange LED may remain on when the amplifier mute is on.
1 Hz
5 Hz
10 Hz
1 Hz LED’s will blink together when reading FLASH update data.
5 Hz LED’s will blink together when FLASH is being written with update
OFF information
The green LED will blink when in the quasi-standby state
25
THEORY OF OPERATION
2.2.2.10 DSP
The DSP system comprises of the SHARC microprocessor (21065L, U7000), the FLASH memory (U7200 [sheet 2, B5]), and the SDRAM (U7300 [B/C3]). The software can essentially be broken up into two segments: The framework and the DSP functions. The framework comprises all of the micro-controller type functions for the 3
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2
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1 Series II such as the communications, controlling/monitoring the power amplifiers, and power-up/down. The DSP functions are the digital audio signal processing functions that exist “inside” the framework, such as the equalization, array processing, volume control, etc. The following discussion relates only to the interactive and hardware information about the DSP system.
Booting - On a cold start, the supplies come up with the 3.3V supply being the last to achieve regulation. This supply is monitored with the reset IC, MAX823 (U6000 [sheet 1, D5]) such that when a threshold is reached, about 3.1V, the IC brings the DSP system out of RESET. When this occurs, the DSP boots from the FLASH IC and enters the Standby mode.
Standby - After a cold start or an off signal, the DSP puts the system into a standby mode where the system draws about 3-4 W off the primary AC. Mainly, the amplifiers are put into standby mode (low quiescent draw), the CS8415A (U4400 [sheet 1, A7]) and CS4228 (U4000
[C2]) are reset, and the DSP enters the “IDLE16” mode (NOT reset) as this is the lowest power drain mode for the DSP. In this mode, the TAP input works as described above and the PWM input looks for any communication via Smart Speaker. On any edge on the COMM line, the
DSP enters its quasi-power-down (quasi-standby) mode and sees if a valid command was received, if not, then the unit enters the standby mode again. LED action shows what is going on during this time. Also once a second, the system must “come alive” briefly to toggle the watchdog timer to prevent a RESET to occur.
Also, on entering standby, the volume parameter is set to the last value, but is bounded in the range of 20 to 80.
Oscillator - The system clock is derived from the oscillator formed by Y7000 [sheet 1, A6] and an inverter of U6100. There is an onboard inverter on the SHARC but it was determined to not have enough gain to reliably start-up the oscillator. R7000 was empirically determined to keep the power dissipation in the crystal to less than .5mW. C7008, 7009 make up the loading capacitance to set the correct frequency, 33.333MHz. The SHARC doubles this clock to
66.666MHz which sets the maximums MIPS load of the software.
Reprogramming - Software updating is accomplished via the S/PDIF input. The “file” is a converted binary image into a stereo PCM format that comprises a header followed by the image to be flashed (the length of this file is about 2 seconds). This allows the software to be upgraded from a CD-ROM inserted into the console. When the appropriate Smart Speaker commands are sent, the DSP reboots into ERC then looks again for an update header before reading in the actual update image. When the image is read in, the code takes a few seconds to determine the validity with a checksum. If the checksum fails, then no update occurs. (If there are still “updates” being presented, then the process will begin again.) If the checksum passes, the unit then writes the image to the FLASH, a process which takes about 45 seconds and the LED’s blink very rapidly (10 Hz, see above). The update disc/file can then be stopped during this time safely. When this has completed, the system then reboots into the new code as if it were a cold start (into standby).
The ERC (Emergency Recovery Code) has been written to a protected area of the FLASH such that in case a software update crashed or anything else that causes the FLASH to be corrupted, the ERC will always be available, and therefore rewriting the FLASH is always possible using the same update procedure.
26
Troubleshooting Guide
3
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2
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1 and 3
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2
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1GS Series II
Home Entertainment System
(US/Canada, European, UK, Australia, Japan and Dual Voltage Standard Versions)
3
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2
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1 Series II System
©2005 Bose Corporation
3
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2
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1GS Series II System
Troubleshooting Guide
Reference Number 273029-TG Rev. 00
Electronic Copy Only
SPECIFICATIONS AND FEATURES SUBJECT TO CHANGE WITHOUT NOTICE
Bose Corporation
The Mountain
Framingham Massachusetts USA 01701
P/N: 273029-TG Rev. 00 3/2005 (H) http://serviceops.bose.com
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