OWL Instruction Manual OWL Digital Camera

OWL Instruction Manual OWL Digital Camera
OWL Instruction Manual
Document number
Revision
File name
Date
Page
2011-05-23-01
V1.8
OWL_Digital_IM.doc
29/03/13
1 of 28
Project designation
OWL Digital Camera
Document title
Instructions and manual of use
This document is the property of Raptor Photonics and must not be
copied, shown or in any way be communicated to persons other than
those requiring the inf ormation f or the execution of their duty .
OWL Instruction Manual
Document number
Revision
File name
Date
Page
2011-05-23-01
V1.8
OWL_Digital_IM.doc
29/03/13
2 of 28
DOCUMENT VALIDATION
Prepared
Name
Title
SH
Raptor Photonics
Date
th
29 March 2013
Review ed
Review ed
Review ed
Review ed
Review ed
Approved
Authorized
DOCUMENT CHANGE RECORD
Issue
Change order
Date
1.0
23/05/11
1.4
10/06/11
1.5
20/06/11
1.6
1.7
1.8
05/07/11
14/07/11
29/03/13
Pages affected
Comment
Page 6
Page 6
Original
Up rev to 1.4 to capture all recent
functionality additions
Added Samtec connector and changed
some order
Removed Samtec connector.
Added Power Connector Pinout
Trigger In and Out fixed
OWL Instruction Manual
Document number
Revision
File name
Date
Page
2011-05-23-01
V1.8
OWL_Digital_IM.doc
29/03/13
3 of 28
TABLE OF CONTENTS
1
SCOPE......................................................................................................................................5
2
DESIGN OVERVIEW..............................................................................................................6
2.1
Physical Interfaces ..........................................................................................................6
2.1.1
4 pin Hirose ..............................................................................................................6
2.1.2
SMA Connectors .....................................................................................................6
2.1.3
Camera Link Connector .........................................................................................7
2.2
Electrical Block Diagram ................................................................................................8
2.3
Mechanical Profile ...........................................................................................................9
3
DESIGN DETAILS ............................................................................................................... 10
3.1
Electrical Design ........................................................................................................... 10
3.1.1
Power supplies and TEC..................................................................................... 10
3.1.2
ROIC and set point Temperature Calibration .................................................. 10
3.1.3
Digital Video out ................................................................................................... 12
3.1.4
Internal Frame Synchronisation ......................................................................... 13
3.1.5
External Frame synchronisation ........................................................................ 13
3.1.6
Automatic Light Control ....................................................................................... 14
3.1.7
ROI.......................................................................................................................... 14
3.1.8
Average Video level detection............................................................................ 15
3.1.9
Peak Video level detection ................................................................................. 15
3.1.10 Bad Pixel................................................................................................................ 15
3.1.11 ROIC Control Registers....................................................................................... 15
3.1.12 Unit Serial number ............................................................................................... 16
4
SERIAL COMMUNICATION (LVDS INTERFACE USING CAMERALINK ).............. 17
4.1
Overview ........................................................................................................................ 17
4.2
Set Commands ............................................................................................................. 18
4.3
Query Commands ........................................................................................................ 20
4.4
Examples ....................................................................................................................... 23
4.4.1
Set System Status................................................................................................ 23
4.4.2
Get System Status ............................................................................................... 23
4.4.3
Get Micro version ................................................................................................. 23
4.4.4
Get FPGA version ................................................................................................ 23
4.4.5
Get Unit Serial Number ....................................................................................... 23
4.4.6
Reset camera........................................................................................................ 23
4.4.7
Read Sensor PCB temperature ......................................................................... 23
4.4.8
Enable Auto exposure ......................................................................................... 24
4.4.9
Switch TEC off ...................................................................................................... 24
4.4.10 Command acknowledge...................................................................................... 24
APPENDIX A - FPGA FIRMWARE UPLOAD................................................. 25
OWL Instruction Manual
Document number
Revision
File name
Date
Page
2011-05-23-01
V1.8
OWL_Digital_IM.doc
29/03/13
4 of 28
Figure 1: Test Unit with Camera module (Photograph) ............................................................5
Figure 2: Un NUCed Image taken with Camera .........................................................................5
Figure 3: Electrical block diagram ................................................................................................8
Figure 4: Mechanical profile drawings .........................................................................................9
Figure 5: Digital Video Timing (TO BE UPDATED) ................................................................ 12
Figure 6: External Trigger timing (TO BE UPDATED) ........................................................... 13
Figure 7: ROI size and offset...................................................................................................... 14
OWL Instruction Manual
Document number
Revision
File name
Date
Page
2011-05-23-01
V1.8
OWL_Digital_IM.doc
29/03/13
5 of 28
1 SCOPE
This document details the design for the OWL Digital Short Wave Infrared (SWIR) camera.
Details of the camera electrical interfaces and communication protocols are also provided.
A photograph of the complete Camera module is shown below with a raw uncorrected image.
Image was taken in Daylight, TEC off.
Figure 1: Test Unit with Camera module (Photograph)
Figure 2: Un NUCed Image taken with Camera
OWL Instruction Manual
Document number
Revision
File name
Date
Page
2011-05-23-01
V1.8
OWL_Digital_IM.doc
29/03/13
6 of 28
2 DESIGN OVERVIEW
2.1
Physical Interfaces
1
2
3
1.
4 Pin Hirose connector
2.
SMA connector
3.
SMA connector
4.
3M CameraLink connector
4
Part #: HR10A-7R-4PB(73)
50Ω, Trigger In
50Ω, Trigger Out
Part #: 10226-6212PC
2.1.1 4 pin Hirose
The OWL Digital has a 4-pin Hirose multi-connector for power input and signal integration.
The pin-out table is shown below (Image seen from rear of camera).
The Associated male connector part # is: HR10-7P-4S(73)
1
2
4
3
Pin Number
1
2
3
4
I/O
-
Signal Name
12V
12V
GND
GND
2.1.2 SMA Connectors
The OWL Digital has 2 SMA connectors on the rear panel. One is for trigger out to allow the user
to trigger other equipment such as a laser and the other is a trigger in. The trigger is used when a
laser, for example, is in control of the timings and wishes to trigger the camera.
OWL Instruction Manual
Document number
Revision
File name
Date
Page
2011-05-23-01
V1.8
OWL_Digital_IM.doc
29/03/13
7 of 28
2.1.3 Camera Link Connector
Camera link connector is compliant with the Camera Link® Version 1.2 standard Ref.
http://www.machinevisiononline.org/public/articles/articlesdetails.cfm?id=2028
OWL Instruction Manual
Document number
Revision
File name
Date
Page
2011-05-23-01
V1.8
OWL_Digital_IM.doc
29/03/13
8 of 28
2.2
`
Electrical Block Diagram
T EMP
Cactus
Sensor
TEC
Cameralink
Video/Serial
Ambient
TEMP
AMP
Buff/
AMP
SDRAM
RS232
QUAD
ADC
FPGA
Trig i/o
EPROM
Power
Supply
Figure 3: Electrical block diagram
OWL Instruction Manual
Document number
Revision
File name
Date
Page
2011-05-23-01
V1.8
OWL_Digital_IM.doc
29/03/13
9 of 28
2.3
Mechanical Profile
`
Figure 4: Mechanical profile drawings
Notes:
- Drawing shown with C mount ring fitted to camera
- C-mount has a flange focal distance of 17.52mm.
- From the above drawing the estimated focal plane of the sensor can be found at 17.52mm
from the front of the C ring and 10.52mm from the front face of the camera.
- Note that the C ring is on can be adjusted to enable back focus of the camera if required.
OWL Instruction Manual
Document number
Revision
File name
Date
Page
2011-05-23-01
V1.8
OWL_Digital_IM.doc
29/03/13
10 of 28
3 DESIGN DETAILS
3.1
Electrical Design
3.1.1 Power supplies and TEC
Unit input power specification is 12V +/- 0.5V with a maximum of 5Watts power dissipation with
the TEC cooler switched off. Additional inrush current (peakpower) is required when the cooler
power is switched from low to high. Peak Power < 18Watts. The total, maximum steady state,
unit power dissipation is 15Watts
The set point for the TEC cooling is +15degC. The TEC power is automatically adjusted to try and
achieve the set point temperature, with a limit of approx. 10W drive. For low ambient
temperatures or with additional heat sinking less than 10Watt may be applied to the TEC to
achieve the set point.
3.1.2 ROIC and set point Temperature Calibration
The temperature of the ROIC is determined from a diode voltage on the ROIC. The diode voltage
varies linearly with temperature. This voltage is read via an Analogue to Digital(ADC) converter.
For calibration two ADC count values for the ROIC temperature are determined during
qualification testing for each camera i.e. at 0degC and at +40degC. These two points are stored in
the cameras EPROM. A straight line graph can then be used to determine temperature for any
given ADC count value.
Straight line eqn.
Y = M*X+C , becomes
where the slope,
Constant offset,
M = (Y1-Y2)/(X1-X2) -- two known points from calibration
C = Y2 - M*(X2)
For any ADC value,
ADC temp(degC) = M*(ADC counts) + C
Likewise a Digital to Analogue converter is used to produce a voltage for the set point of the TEC
control loop. Two values are determined for 0degC and +40degC for each camera during
qualification testing and stored in the cameras EPROM.
OWL Instruction Manual
Document number
Revision
File name
Date
Page
2011-05-23-01
V1.8
OWL_Digital_IM.doc
29/03/13
11 of 28
The relationship of DAC counts to setpoint temperature is linear and therefore a straight line graph
can be used to determine the setpoint temperature from the DAC count value.
OWL Instruction Manual
Document number
Revision
File name
Date
Page
2011-05-23-01
V1.8
OWL_Digital_IM.doc
29/03/13
12 of 28
3.1.3 Digital Video out
The Owl_OEM1 camera produces mono, progressive scan, digital video output as per Cameralink
standard.
A continuous 40MHz clock is broadcast on to the external interface along with FRAME VALID,
LINE VALID and 14 bit digital pixel data. This is embedded within the Cameralink signals.
The OWL_OEM1 SWIR Sensor has 640 x 512 active pixels.
FVPERIOD
FVLOW
LL_FV
LL_LV
LVPERIOD
1
FVHIGH-LVHIGH
2
3
495
496
LVLOW
Figure 5: Digital Video Timing (TO BE UPDATED)
FVPERIO D = Frame Valid period
60.00Hz
= 83333 5MHz clock periods
59.94Hz
= 83417 5MHz clock periods
50.00Hz
= 100,000 5MHz clock periods
25.00Hz
= 200,000 5MHz clock periods
29.97Hz
= 166,834 5MHz clock periods
30.00Hz
= 166,667 5MHz clock periods
EXT TRIG
= USER DEFINED
FVLO W = Frame Valid low
60.00Hz
= (TBD) = TBD pixel clock periods (TBD line periods)
59.94Hz
= (TBD) = TBD pixel clock periods (TBD line periods)
50.00Hz
= (TBD) = TBD pixel clock periods (TBD line periods)
25.00Hz
= (TBD) = TBD pixel clock periods (TBD line periods)
29.97Hz
= (TBD) = TBD pixel clock periods (TBD line periods)
30.00Hz
= (TBD) = TBD pixel clock periods (TBD line periods)
EXT TRIG
= (X – TBD) , where X is the USER DEFINED FVPERIOD
LVPERIO D
LVLO W
FVHIGH -LVHIGH
Video Latency
= Line Valid period
= TBD pixel clock periods
= Line Valid low
= (TBD) = TBD pixel clock periods
= Rising edge of Frame valid to rising edge of line 1 Line Valid
= TBD pixel clock periods
= TBD
OWL Instruction Manual
Document number
Revision
File name
Date
Page
2011-05-23-01
V1.8
OWL_Digital_IM.doc
29/03/13
13 of 28
3.1.4 Internal Frame Synchronisation
When internal trigger is selected the frame rate is determined for a set of 4 8-bit internal registers
that make up a 32 bit number. each count in the 32bit register equates to a 1*5MHz clock period
i.e. 200ns.
Example frame rates are given below.
Frame Rate
25
29.97
30
50
59.94
60
Period
40 ms
33 ms
33 ms
20 ms
16 ms
16 ms
Count value
200,000
166,834
166,667
100,000
83417
83333
3.1.5 External Frame synchronisation
When external trigger is selected the camera may be triggered from an external source via the
differential input pins TRIG_TC_P and TRIG_TC_N (see 32 pin SAMTEC connector pin out).
A programmable delay may also be used to delay the start of exposure of the camera.
T fp
T pw
EXT .
T RIG
T dly
T. Dly
T exp
T dly
Exposure N
Read out N-1
T. Dly
Read out N
T rd
Tfp = Frame period
Tpw = Trigger pulse width, min width > one 5MHz clock period
Tdly = Delay from falling edge of trigger to start of exposure
Trd = readout time for 1 progressive frame
Texp = exposure time of sensor
Jitter performance = +/- TBD
Figure 6: External Trigger timing (TO BE UPDATED)
Notes;
- External trigger, triggers the start of a new exposure
E. N+1.
OWL Instruction Manual
Document number
Revision
File name
Date
Page
2011-05-23-01
V1.8
OWL_Digital_IM.doc
29/03/13
14 of 28
- A programmable delay may be inserted between the external trigger and the start of exposure
3.1.6 Automatic Light Control
Exposure of the Sensor may be automatically controlled by using the " Set FPGA CTRL reg "
command and setting bit 1 = 1.
Exposure will automatically be adjusted until the set point is reached. If the Exposure reaches its
maximum value the camera will automatically increase the Digital gain applied to the image until
the set point is reached.
During Auto, exposure is limited to a minimum value of 500nsec and a maximum value
determined by the frame rate of the camera.
Digital Gain is limited to a min of 466counts= gain of 1.82 so that the full well on the sensor may
saturate the 14bit digital output. Maximum digital gain count = 65535 = gain of 256.
3.1.7 ROI
A region of interest within the main active region of 640*512 may be defined. This region may be
used to calculate Peak and Average settings for the Automatic Light control function of the
camera.
ROI offset and size are outlined below.
640 pixels
X
W
X = ROI X Offset
Y = ROI Y Offset
Y
W = ROI width
H = ROI height
512 lines
H
ROI
Figure 7: ROI size and offset
8bit values are used to store X,Y,W and H.
The 8-bit values sent to the camera for X, Y, W and H will be multiplied by 4 in the camera, to
give the required number pixels for the offset/size for the ROI. i.e. the ROI can be moved to
within a resolution of 4 pixels in the X and Y, and the ROI size will have a resolution of 4 pixels
OWL Instruction Manual
Document number
Revision
File name
Date
Page
2011-05-23-01
V1.8
OWL_Digital_IM.doc
29/03/13
15 of 28
Note that the ROI may only be moved within a region 632*504 region, with a min offset of 4,4.
If (X+W)>632 then X will be internally limited to make sure (X+W)=632
If (Y+H)>504 then Y will be internally limited to make sure (Y+H)=504
ROI highlighting is also provided. When selected the pixels within the ROI will have a gain of
unity, Those pixels outside the ROI may either have 0.75 gain applied.
An optional ROI outline feature is also included that if enabled will draw a 1pixel wide box
around the ROI
3.1.8 Average Video level detection
An average video level is calculated for active ROI. This value will be calculated in real time, i.e.
as pixel data in the ROI is captured from the sensor it is fed directly to an accumulator. At the end
of frame the Accumulator is divided to give a true average. This average can be read from internal
registers in the camera.
3.1.9 Peak Video level detection
Peak video is determined from a rolling average of 4 pixels. current pixel + 3 previous pixels are
used to derive peak value. This peak value is monitored for the ROI and latched at the end of
frame. The peak value may be read from internal registers in the camera.
3.1.10 Bad Pixel
Will be determined from NUC values that are stored for each pixel. For gain and offset values
outside a given threshold will determine that the pixel is BAD.
During the calculation of the NUC values any pixels identified as bad will have their gain and
offset values set to zero.
Bad pixels may be highlighted during live video by selecting the appropriate NUC state.
3.1.11 ROIC Control Registers
The ROIC is controlled from a single 31bit register. This register is mapped to four internal 8bit
registers in the FPGA.
Default register state =0x2FFC0004 -- High gain mode
A low gain mode is available that will provide a greater dynamic range at the expense of a higher
noise floor.
to switch to Low gain(High dynamic range) set the ROIC control register to, 0x3FFC0004
i.e. send commands
0x53 0xE0 0x02 0xE4 0x3F 0x50
0x53 0xE0 0x02 0xE5 0xFC 0x50
0x53 0xE0 0x02 0xE6 0x00 0x50
OWL Instruction Manual
Document number
Revision
File name
Date
Page
2011-05-23-01
V1.8
OWL_Digital_IM.doc
29/03/13
16 of 28
0x53 0xE0 0x02 0xE7 0x04 0x50
3.1.12 Unit Serial number
Can be read from the camera’s EPROM. When Comms is enabled to the EPROM.
OWL Instruction Manual
Document number
Revision
File name
Date
Page
2011-05-23-01
V1.8
OWL_Digital_IM.doc
29/03/13
17 of 28
4 SERIAL COMMUNICATION (LVDS INTERFACE USING CAMERALINK )
4.1 Overview
Serial communications performed over a standard Cameralink LVDS interface. The device used
for this is DS90LV019TMTC from National Semiconductor.
For version 1.4 of the Micro firmware, the Power on default settings for camera serial port are;
- 115200 baud
- 1 start bit
- 8 data bits
- 1 stop bit
These settings are fixed and can’t be altered.
UART message format
Command
Data1 ¦ data2 ---Data n
End command
The message format used for the UART is kept simple. The first Byte is the command to the
Microcontroller in the camera, following bytes contain data required by the command, the last
byte terminates the message. 0x50 is always used to terminate the message.
It is intended that the camera be operated from a higher level perspective whereby complete
UART messages or groups of UART messages are used to achieve required camera functionality
as laid out in document 66823-.doc dated 23 FEB 2011.
Bits in registers that have not been identified in the documentation should be ignored.
Once a command has been received by the camera all sub sequent commands from the host will be
ignored until the command has been processed.
The time taken for the camera to process the command once it has been fully received will be
shorter that the total time for the transmission of the command from the host.
It is recommended that command acknowledge be enabled for all communication with he camera.
The camera will return a hex code of 0x50 when it has finished processing the last command and
is ready to receive a new command.
If command acknowledge bit is set = 1 and the camera transmits data as a response to a command
from the host, the ACK packet of 0x50 will be added to the end of the transmission.
OWL Instruction Manual
Document number
Revision
File name
Date
Page
2011-05-23-01
V1.8
OWL_Digital_IM.doc
29/03/13
18 of 28
4.2 Set Commands
Set Command
Serial Packet
Set system state
0x4F 0xYY 0x50
Micro RESET
0x55 0x50
Set exposure
0x53
0x53
0x53
0x53
0xE0
0xE0
0xE0
0xE0
0x02
0x02
0x02
0x02
0xEE 0xY1 0x50
0xEF 0xY2 0x50
0xF0 0xY3 0x50
0xF1 0xY4 0x50
Set digital video gain
0x53 0xE0 0x02 0xC6 0xMM 0x50
0x53 0xE0 0x02 0xC7 0xLL 0x50
Set trig delay
0x53
0x53
0x53
0x53
0xE2
0xE2
0xE2
0xE2
0x02
0x02
0x02
0x02
0xE9 0xY1 0x50
0xEA 0xY2 0x50
0xEB 0xY3 0x50
0xEC 0xY4 0x50
Set External Trig
0x53 0xE0 0x02 0xF2 0xYY 0x50
Set frame rate
(Internal trig)
0x53
0x53
0x53
0x53
0xE0
0xE0
0xE0
0xE0
0x02
0x02
0x02
0x02
0xDD 0xY1 0x50
0xDE 0xY2 0x50
0xDF 0xY3 0x50
0xE0 0xY4 0x50
0x53
0x53
0x53
0x53
0xE0
0xE0
0xE0
0xE0
0x02
0x02
0x02
0x02
0xE4
0xE5
0xE6
0xE7
Write to ROIC
0xYY
0xYY
0xYY
0xYY
0x50
0x50
0x50
0x50
Comments
YY Bit 7..5= Reserve
YY Bit 4 = 1 to enable command ack
YY Bit 1 = 0 to Hold FPGA in RESET
YY Bit 0 = 1 to enable comms to FPGA
EPROM
Will trap Micro causing watchdog and
reset of firmware
32 bit value, 4 separate commands,
1 count = 1*160MHz period = 6.25nsecs
Y1 = MSB of 4 byte word
::
Y4 = LSB of 4 byte word
Exposure updated on LSB write
Min Exposure = 500nsec = 80counts
16bit value = gain*256
MM bits 7..0 = gain bits 15..8
LL bits 7..0 = level bits 7..0
Data updated on write to LSBs
32 bit value, 4 separate commands,
1 count = 1*160MHz period = 6.25nsecs
Y1 = MSB of 4 byte word
Y4 = LSB of 4 byte word;
Trig Delay updated on LSB write
YY Bit 6 = 1 to enable Ext trig
(Default=0)
YY Bit 5 = 0 for –ve edge trig(Default=0)
32 bit value, 4 separate commands,
1 count = 1*5MHz period = 200nsecs
Y1 = MSB of 4 byte word
Y4 = LSB of 4 byte word;
Frame rate updated on LSB write
MSB of 4 byte word
LSB of 4 byte word;
ROIC updated on LSB write
OWL Instruction Manual
Document number
Revision
File name
Date
Page
2011-05-23-01
V1.8
OWL_Digital_IM.doc
29/03/13
19 of 28
Set FPGA CTRL reg
0x53 0xE0 0x02 0x00 0xYY 0x50
YY Bit 0 = 1 to enable TEC (Default=0)
YY Bit 1 = 1 to enable Auto Exp
(Default=1)
12 bit DAC value, MSB = MSB of MM
byte, upper nibble of LL = LSBs
12 bit value to be converted to
temperature from DAC calibration values
(see " Get manufacturers Data")
Bit 7 Bit 6 Bit5 (of YY)
0
0
0 offset corrected
0
0
1 offset +gain corrected
0
1
0 Normal(Default)
0
1
1 offset +gain + Dark
1
0
0 8bit offset /32
1
0
1 8bit Dark *2^19
1
1
0 8bit gain /128
1
1
1 offset +gain + Dark
+Bad PIXEL show
14 bit value – max 0x3FFF = White
MM bits 7..0 = level bits 13..6
LL bits 7..2 = level bits 5..0
YY 8-bit value
0 = Full Peak
255 = Full Average
YY Bits 7..4 = GAIN speed(Default=7)
YY Bits 3..0 = EXP speed(Default=7)
Pixels within ROI always gain = 1
Bit 7 Bit 6
0
0 gain=1 outside ROI (Default)
1
0 gain=0.75 outside ROI
0
1 gain=1 + ROI BOX
Set TEC set point
0x53 0x98 0x03 0x22 0xMM 0xLL
0x50
Set NUC state
0x53 0xE0 0x02 0xF9 0xYY 0x50
Set Auto level
0x53 0xE0 0x02 0x23 0xMM 0x50
0x53 0xE0 0x02 0x24 0xLL 0x50
Set PEAK/Average
0x53 0xE0 0x02 0x2D 0xYY 0x50
Set AGC speed
0x53 0xE0 0x02 0x2F 0xYY 0x50
Set ROI appearance
0x53 0xE0 0x02 0x31 0xYY 0x50
Set ROI X offset
0x53 0xE0 0x02 0x32 0xYY 0x50
YY 8-bit value = 1/4 of X pixel offset
Set ROI Y offset
0x53 0xE0 0x02 0x33 0xYY 0x50
YY 8-bit value = 1/4 of Y pixel offset
Set ROI X Size
0x53 0xE0 0x02 0x35 0xYY 0x50
YY 8-bit value = 1/4 of X pixel offset
Set ROI Y Size
0x53 0xE0 0x02 0x36 0xYY 0x50
YY 8-bit value = 1/4 of Y pixel offset
OWL Instruction Manual
Document number
Revision
File name
Date
Page
2011-05-23-01
V1.8
OWL_Digital_IM.doc
29/03/13
20 of 28
4.3 Query Commands
Query Command
Send Serial Packet
Get system status
Get exposure value
( May also be read
during Auto Exposure)
Get Digital Gain
Get trig delay
0x49 0x50
0x53
0x53
0x53
0x53
0x53
0x53
0x53
0x53
0xE0
0xE1
0xE0
0xE1
0xE0
0xE1
0xE0
0xE1
0x01
0x01
0x01
0x01
0x01
0x01
0x01
0x01
0xEE 0x50
0x50
0xEF 0x50
0x50
0xF0 0x50
0x50
0xF1 0x50
0x50
0x53
0x53
0x53
0x53
0x53
0x53
0x53
0x53
0x53
0x53
0x53
0x53
0xE0
0xE1
0xE0
0xE1
0xE0
0xE1
0xE0
0xE1
0xE0
0xE1
0xE0
0xE1
0x01
0x01
0x01
0x01
0x01
0x01
0x01
0x01
0x01
0x01
0x01
0x01
0xC6 0x50
0x50
0xC7 0x50
0x50
0xE9 0x50
0x50
0xEA 0x50
0x50
0xEB 0x50
0x50
0xEC 0x50
0x50
Get Ext. Trig Status
0x53 0xE0 0x01 0xF2 0x50
0x53 0xE1 0x01 0x50
Get frame rate
(Internal trig)
0x53
0x53
0x53
0x53
0x53
0x53
0x53
0x53
Get TEC/AEXP Status
0xE0
0xE1
0xE0
0xE1
0xE0
0xE1
0xE0
0xE1
0x01
0x01
0x01
0x01
0x01
0x01
0x01
0x01
0xDD 0x50
0x50
0xDE 0x50
0x50
0xDF 0x50
0x50
0xE0 0x50
0x50
0x53 0xE0 0x01 0x00 0x50
0x53 0xE1 0x01 0x50
Comments
Single byte will be transmitted from
camera when command received.
YY Bit 7..5= Reserved
YY Bit 4 = 1 Command ack Enabled
YY Bit 1 = 0 FPGA Held in RESET
YY Bit 0 = 1 Comms to FPGA EPROM
Enabled
Set address EE
Read address EE ,(MSB) 1 byte
Set address EF
Read address EF ,(MIDU) 1 byte
Set address F0
Read address F0, (MIDL)1 byte
Set address F1
Read address F1 (LSB) , 1 byte
32 bit value, 4 bytes,
1 count = 1*160MHz period = 6.25nsecs
Min Exposure = 500nsec = 80counts
2 bytes returned MM,LL
16bit value = gain*256
Reg. C6 bits 7..0 = gain bits 15..8
Reg. C7 bits 7..0 = level bits 7..0
32 bit value, 4 separate Registers,
1 count = 1*160MHz period = 6.25nsecs
E9 = MSB of 4 byte word
EC = LSB of 4 byte word;
1 byte returned
Bit 6 = 1, Ext trig enabled (Default=0)
Bit 5 = 0 for –ve edge trig(Default=0)
32 bit value, 4 separate Registers,
1 count = 1*5MHz period = 200nsecs
DD = MSB of 4 byte word
E0 = LSB of 4 byte word;
Set address 00 (MSB)
Read address 00 (MSB), 1 byte
OWL Instruction Manual
Document number
Revision
File name
Date
Page
2011-05-23-01
V1.8
OWL_Digital_IM.doc
29/03/13
21 of 28
Get TEC Setpoint
0x53 0x98 0x01 0x20 0x50
0x53 0x99 0x02 0x50
Get NUC state
0x53 0xE0 0x01 0xF9 0x50
0x53 0xE1 0x01 0x50
Get Auto level
(Set point)
0x53
0x53
0x53
0x53
Get PEAK/Average
setting
0x53 0xE0 0x01 0x2D 0x50
0x53 0xE1 0x01 0x50
Get AGC speed
0x53 0xE0 0x01 0x2F 0x50
0x53 0xE1 0x01 0x50
Get ROI appearance
0x53 0xE0 0x01 0x31 0x50
0x53 0xE1 0x01 0x50
Get ROI X offset
Get ROI Y offset
Get ROI X Size
Get ROI Y Size
Get Video Peak value
Get Video Average
0xE0
0xE1
0xE0
0xE1
0x01
0x01
0x01
0x01
0x23 0x50
0x50
0x24 0x50
0x50
0x53
0x53
0x53
0x53
0x53
0x53
0x53
0x53
0xE0
0xE1
0xE0
0xE1
0xE0
0xE1
0xE0
0xE1
0x01
0x01
0x01
0x01
0x01
0x01
0x01
0x01
0x32 0x50
0x50
0x33 0x50
0x50
0x35 0x50
0x50
0x36 0x50
0x50
0x53
0x53
0x53
0x53
0xE0
0xE1
0xE0
0xE1
0x01
0x01
0x01
0x01
0x5E 0x50
0x50
0x5F 0x50
0x50
Bit 0 = 1 if TEC is enabled
Bit 1 = 1 if AEXP is enabled
Read 12 bit EM word;
2 bytes returned MM,LL
MM = 8 MSBs
LL = 4 LSBs (Upper nibble)
12 bit value to be converted to temperature
from DAC calibration values (see " Get
manufacturers Data")
1 byte returned
Bit 7 Bit 6 Bit5
0
0
0 offset corrected
0
0
1 offset +gain corrected
0
1
0 Normal(Default)
0
1
1 offset +gain + Dark
1
0
0 8bit offset /32
1
0
1 8bit Dark *2^19
1
1
0 8bit gain /128
1
1
1 offset +gain + Dark
+Bad PIXEL show
2 bytes returned MM,LL
14 bit value – max 0x3FFF = White
Reg 23, bits 7..0 = level bits 13..6
Reg 24, bits 7..2 = level bits 5..0
8-bit value
0 = Full Peak
255 = Full Average
Bits 7..4 = GAIN speed(Default=7)
Bits 3..0 = EXP speed(Default=7)
Pixels within ROI always gain = 1
Bit 7 Bit 6
0
0 gain=1 outside ROI (Default)
1
0 gain=0.75 outside ROI
0
1 gain=1 + ROI BOX
YY 8-bit value = 1/4 of X pixel offset
YY 8-bit value = 1/4 of Y pixel offset
YY 8-bit value = 1/4 of X pixel offset
YY 8-bit value = 1/4 of Y pixel offset
14 bit value, 2 bytes returned
Set address 5E
Add 5E, bits 5..0 = Pk. level bits 13..8
Set address 5F
Read Add 5F = Pk level bits 7..0
14 bit value, 2 bytes returned
OWL Instruction Manual
Document number
Revision
File name
Date
Page
2011-05-23-01
V1.8
OWL_Digital_IM.doc
29/03/13
22 of 28
value
0x53
0x53
0x53
0x53
0xE0
0xE1
0xE0
0xE1
0x01
0x01
0x01
0x01
0x60 0x50
0x50
0x61 0x50
0x50
Get sensor PCB
temperature
0x53 0x97 0x02 0x50
Get Sensor Temp
temperature
0x53 0x91 0x02 0x50
Get Micro version
0x56 0x50
Get FPGA version
Get Unit Serial Number
Get manufacturers Data
0x53
0x53
0x53
0x53
0x53
0x00
0x53
0xE0 0x01 0x7E 0x50
0xE1 0x01 0x50
0xE0 0x01 0x7F 0x50
0xE1 0x01 0x50
0xAE 0x05 0x01 0x00
0x02 0x00 0x50
0xAF 0x02 0x50
0x53 0xAE 0x05 0x01 0x00
0x00 0x02 0x00 0x50
0x53 0xAF 0x12 0x50
Set address 60
Add 60, bits 5..0 = Avg. bits 13..8
Set address 61
Read Add 61 = Avg. bits 7..0
2 bytes returned
1st byte = temp in deg C (integer value)
2nd byte bit 7 = 1 for additional 0.5degC
2 bytes returned, MSB followed by LSB
MSB bits 3..0 = Temp cnt bits 11..8
LSB bits 7..0 = Temp cnt bits 7..0
12 bit value to be converted to temperature
from ADC calibration values (see " Get
manufacturers Data")
Two bytes transmitted from camera when
command received. 1st byte Major version
2nd byte Minor version.
Set address 7E (Major Version Byte)
Read address 7E, 1 byte
Set address 7F (Minor Version Byte)
Read address 7F, 1 byte
2 bytes returned 1st byte is the LSB 2nd is
the MSB
Get 18 bytes from cameras EPROM.
For 2 byte values 1st byte returned is the
LSB.
Starting at address 0x000002
2 bytes Serial number
3 bytes Build Date (DD/MM/YY)
5 bytes Build code (5 ASCII chars)
2 bytes ADC cal 0degC point
2 bytes ADC cal+4 0degC point
2 bytes DAC cal 0degC point
2 bytes DAC cal+4 0degC point
NOTES:
- Command 0x4F writes to the system status register, 0x49 reads from the system status
register.
OWL Instruction Manual
Document number
Revision
File name
Date
Page
2011-05-23-01
V1.8
OWL_Digital_IM.doc
29/03/13
23 of 28
4.4
Examples
Note: Command acknowledge has been enabled for each of these examples meaning that
each command will provoke a 0x50 packet to be returned when complete.
4.4.1 Set System Status
From power up
Command
TX bytes (to camera)
Set system status
0x4F 0x12 0x50
- ACK enabled (bit 4)
- FPGA enabled(bit1)
- EPROM comms disabled(bit0)
RX’d bytes (From camera)
0x50 (ACK)
4.4.2 Get System Status
Command
TX bytes (to camera)
Get system status
0x49 0x50
RX’d bytes (From camera)
0x12 0x50
4.4.3 Get Micro version
Command
TX bytes (to camera)
Get Micro version
0x56 0x50
RX’d bytes (From camera)
0x01 0x04 0x50 (V1.4)
4.4.4 Get FPGA version
Command
TX bytes (to camera)
0x53 0xE0 0x01 0x7E 0x50
0x53 0xE1 0x01 0x50
Get FPGA version
0x53 0xE0 0x01 0x7F 0x50
0x53 0xE1 0x01 0x50
RX’d bytes (From camera)
0x50
0x02 0x50
0x50
0x01 0x50 (V2.1)
4.4.5 Get Unit Serial Number
Command
TX bytes (to camera)
RX’d bytes (From camera)
Get system status
0x49 0x50
0x12 0x50
Binary OR status byte with
none
none
0x01
Enable EPROM Comms
0x4F 0x13 0x50
0x50
0x53 0xAE 0x05 0x01 0x00
0x50
Get Unit Serial Number
0x00 0x02 0x00 0x50
0x53 0xAF 0x02 0x50
0xEA 0x03 0x50 (S. no. 1002)
Disable EPROM Comms
0x4F 0x12 0x50
0x50
Note that serial number along with other data may be read as part of the " Get manufacturers Data"
4.4.6 Reset camera
Command
TX bytes (to camera)
RX’d bytes (From camera)
System RESET
0x4F 0x00 0x50
0x50
System Enable
0x4F 0x12 0x50
0x50
4.4.7 Read Sensor PCB temperature
OWL Instruction Manual
Document number
Revision
File name
Date
Page
2011-05-23-01
V1.8
OWL_Digital_IM.doc
29/03/13
24 of 28
Command
Get Sensor PCB temperature
TX bytes (to camera)
0x53 0x97 0x02 0x50
4.4.8 Enable Auto exposure
Command
TX bytes (to camera)
0x53 0xE0 0x01 0x00 0x50
Get TEC/ AEXP Status byte
0x53 0xE1 0x01 0x50
Binary OR status byte with
none
0x02
Send byte i.e. Enable Auto
0x53 0xE0 0x02 0x00 0x03
EXP
0x50
4.4.9 Switch TEC off
Command
RX’d bytes (From camera)
0x23 0x70 0x50 (35 deg C)
RX’d bytes (From camera)
0x50
0x01 0x50
none
0x50
TX bytes (to camera)
0x53 0xE0 0x01 0x00 0x50
0x53 0xE1 0x01 0x50
RX’d bytes (From camera)
0x50
0x01 0x50
Binary AND status byte
with 0xFE
none
none
Send byte i.e. Disable TEC
0x53 0xE0 0x02 0x00 0x00
0x50
0x50
Get TEC /AEXP Status byte
4.4.10 Command acknowledge
Assume cmd ack = 0 to start
Command
TX bytes (to camera)
Get system status
0x49 0x50
Binary OR status byte with
none
0x10
Enable Command
0x47 0x12 0x50
Acknowledge
After ack is set
Command
Get Micro version
TX bytes (to camera)
0x56 0x50
RX’d bytes (From camera)
0x02
none
0x50 (ack)
RX’d bytes (From camera)
0x01 0x04 0x50 (v1.4+ack)
OWL Instruction Manual
Document number
Revision
File name
Date
Page
2011-05-23-01
V1.8
OWL_Digital_IM.doc
29/03/13
25 of 28
APPENDIX A - FPGA FIRMWARE UPLOAD
OWL Instruction Manual
Document number
Revision
File name
Date
Page
2011-05-23-01
V1.8
OWL_Digital_IM.doc
29/03/13
26 of 28
CAMERA EPROM
The cameraEPROM is divided into15 sectors with address spaces as outlined below. Note that
each address points to a 16bit word.
/* Sector Structure...
Sector Kwords words
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
4
4
4
4
4
4
4
4
32
32
32
32
32
32
32
4096
4096
4096
4096
4096
4096
4096
4096
32768
32768
32768
32768
32768
32768
32768
start end
start
end
0
4095
000000 000FFF
4096
8191
001000 001FFF
8192
12287 002000 002FFF
12288 16383 003000 003FFF
16384 20479 004000 004FFF
20480 24575 005000 005FFF
24576 28671 006000 006FFF
28672 32767 007000 007FFF
32768 65535 008000 00FFFF
65536 98303 010000 017FFF
98304 131071 018000 01FFFF
131072 163839 020000 027FFF
163840 196607 028000 02FFFF
196608 229375 030000 037FFF
229376 262143 038000 03FFFF
SECTOR 1 - is used for Manufacture specific data i.e. serial number etc.
SECTORS 2-15 are used to hold the FPGA configuration information.
To program a new FPGA configuration
1. Sectors 2-15 must be erased
2. a new bit file must be uploaded to Sectors 2-15
Note that SECTOR 1 must not be ERASED as this contains detailed data about the camera.
SECTOR ERASE
The following command is used to erase a sector.
SECTOR xx ERASE - 0x53 0xAE 0x05 0x04 0xAA 0xBB 0xCC 0x00 0x50
Where the Hex Number AABBCC represents an address in the sector to be erased. After the
SECTOR erase command has been issued a small delay is required for the ERASE to take place.
Successful erase can be determined by polling the sector with the following command.
0x53 0xAF 0x01 0x50
If a value of 0xFF is returned the sector erase is complete.
Example Sector ERASEs
SECTOR 2 ERASE - 0x53 0xAE 0x05 0x04 0x00 0x10 0x00 0x00 0x50
OWL Instruction Manual
Document number
Revision
File name
Date
Page
2011-05-23-01
V1.8
OWL_Digital_IM.doc
29/03/13
27 of 28
0x53 0xAF 0x01 0x50 (Continue to poll until 0xFF received)
SECTOR 3 ERASE - 0x53 0xAE 0x05 0x04 0x00 0x20 0x00 0x00 0x50
0x53 0xAF 0x01 0x50 (Continue to poll until 0xFF received)
SECTOR 4 ERASE - 0x53 0xAE 0x05 0x04 0x00 0x30 0x00 0x00 0x50
0x53 0xAF 0x01 0x50 (Continue to poll until 0xFF received)
SECTOR 5 ERASE - 0x53 0xAE 0x05 0x04 0x00 0x40 0x00 0x00 0x50
0x53 0xAF 0x01 0x50 (Continue to poll until 0xFF received)
SECTOR 6 ERASE - 0x53 0xAE 0x05 0x04 0x00 0x50 0x00 0x00 0x50
0x53 0xAF 0x01 0x50 (Continue to poll until 0xFF received)
SECTOR 7 ERASE - 0x53 0xAE 0x05 0x04 0x00 0x60 0x00 0x00 0x50
0x53 0xAF 0x01 0x50 (Continue to poll until 0xFF received)
SECTOR 8 ERASE - 0x53 0xAE 0x05 0x04 0x00 0x70 0x00 0x00 0x50
0x53 0xAF 0x01 0x50 (Continue to poll until 0xFF received)
SECTOR 9 ERASE - 0x53 0xAE 0x05 0x04 0x00 0x80 0x00 0x00 0x50
0x53 0xAF 0x01 0x50 (Continue to poll until 0xFF received)
SECTOR 10 ERASE - 0x53 0xAE 0x05 0x04 0x01 0x00 0x00 0x00 0x50
0x53 0xAF 0x01 0x50 (Continue to poll until 0xFF received)
SECTOR 11 ERASE - 0x53 0xAE 0x05 0x04 0x01 0x80 0x00 0x00 0x50
0x53 0xAF 0x01 0x50 (Continue to poll until 0xFF received)
SECTOR 12 ERASE - 0x53 0xAE 0x05 0x04 0x02 0x00 0x00 0x00 0x50
0x53 0xAF 0x01 0x50 (Continue to poll until 0xFF received)
SECTOR 13 ERASE - 0x53 0xAE 0x05 0x04 0x02 0x80 0x00 0x00 0x50
0x53 0xAF 0x01 0x50 (Continue to poll until 0xFF received)
SECTOR 14 ERASE - 0x53 0xAE 0x05 0x04 0x03 0x00 0x00 0x00 0x50
0x53 0xAF 0x01 0x50 (Continue to poll until 0xFF received)
SECTOR 15 ERASE - 0x53 0xAE 0x05 0x04 0x03 0x80 0x00 0x00 0x50
0x53 0xAF 0x01 0x50 (Continue to poll until 0xFF received)
SECTOR PROGRAMMING
Bursts of 32 DATA bytes (sixteen 16bit words) should be sent to the EPROM using a single
command, the EPROM will auto increment the addresses.
Burst write command
0x53 0xAE 0x25 0x02 0xAA 0xBB 0xCC 0xN1 0xN2 0xN3 ............0xN32 0x00 0x50
The address of the burst write is given by AABBCC, 32 DATA bytes as read from bit file are sent
N1-N32
Address AABBCC should start at the base address of sector 2 i.e. 0x001000 and increment by 16
for every burst command until the end of file.
At the end of file the last burst may not require 32bytes due to the file size, if this is the case the
last 32 should be padded out to 32. Data in padding ignored.
Notes :
- It is recommended to operate the camera with Command Ack. Waiting for a command Ack will
ensure burst writes have taken place before moving to the next burst write.
OWL Instruction Manual
Document number
Revision
File name
Date
Page
2011-05-23-01
V1.8
OWL_Digital_IM.doc
29/03/13
28 of 28
- The bit stream contains a check sum that is used by the FPGA during power up. If data is
corrupted during upload the FPGA will not boot.
- Verification that FPGA has successfully booted can be done by reading the FPGA version
number.
Example command list
TX bytes (to camera)
RX’d
bytes
(from
camera)
0x4F 0x11 0x50
0x50
0x53 0xAE 0x05 0x04 0x00
0x10 0x00 0x00 0x50
0x50
0x53 0xAF 0x01 0x50
0xFF
0x50
Poll until 0xFF is returned
As above with relevant sector
address
As above
Poll after each sector is erased
until 0xFF is returned
Burst write 32
bytes of bit file
0x53 0xAE 0x25 0x02 0x00
0x10 0x00 0xN1 0xN2 0xN3
............0xN32 0x00 0x50
0x50
1st burst starting at Sector 2
address.
Multiple burst
writes of 32 bytes
of bit file
0x53 0xAE 0x25 0x02 0xAA
0xBB 0xCC 0xN1 0xN2 0xN3
............0xN32 0x00 0x50
0x50
Set System State
0x4F 0x12 0x50
0x50
0x53 0xE0 0x01 0x7E 0x50
0x50
0x02
0x50
0x50
0x01
0x50
Command
Enable Command
Acknowledge +
Enable EROM
comms + Hold
FPGA in reset
Erase EEPROM
sector 2
Confirm Sector 2
erase (by reading
LSByte)
Erase EEPROM
sectors 3-15 and
confirm erase after
each sector.
0x53 0xE1 0x01 0x50
Get FPGA version
0x53 0xE0 0x01 0x7F 0x50
0x53 0xE1 0x01 0x50
Comments
Address 0xAABBCC starts at
sector 2 base address and needs to
be incremented by 16 for each
successive burst until end of file.
FPGA will now boot with new
firmware, need to delay approx.
500msec
Version 2.1
Was this manual useful for you? yes no
Thank you for your participation!

* Your assessment is very important for improving the work of artificial intelligence, which forms the content of this project

Download PDF

advertisement