2016.08.11
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The MAX
®
10 devices consist of the following:
• Logic array blocks (LABs)
• Analog-to-digital converter (ADC)
• User flash memory (UFM)
• Embedded multiplier blocks
• Embedded memory blocks (M9K)
• Clocks and phase-locked loops (PLL)
• General purpose I/O
• High-speed LVDS I/O
• External memory interfaces
• Configuration flash memory (CFM)
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. Altera warrants performance of its semiconductor products to current specifications in accordance with Altera's standard warranty, but reserves the right to make changes to any products and services at any time without notice. Altera assumes no responsibility or liability arising out of the application or use of any information, product, or service described herein except as expressly agreed to in writing by Altera. Altera customers are advised to obtain the latest version of device specifications before relying on any published information and before placing orders for products or services.
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2
Logic Array Block
Figure 1: Typical Device Floorplan for MAX 10 Devices
• The amount and location of each block varies in each MAX 10 device.
• Certain MAX 10 devices may not contain a specific block.
Clocks Logic Array Blocks
PLL
I/O Banks
PLL
Internal Flash
UFM
CFM
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PLL
Embedded Memory
I/O Banks
Embedded Multipliers
PLL
•
•
Related Information
MAX 10 Device Datasheet
Provides more information about specification and performance for MAX 10 devices.
MAX 10 FPGA Device Overview
Provides more information about maximum resources in MAX 10 devices
The LABs are configurable logic blocks that consist of a group of logic resources.
Each LAB consists of the following:
• 16 logic elements (LEs)—smallest logic unit in MAX 10 devices
• LE carry chains—carry chains propagated serially through each LE within a LAB
• LAB control signals—dedicated logic for driving control signals to LEs within a LAB
• Local interconnect—transfers signals between LEs in the same LAB
• Register chains—transfers the output of one LE register to the adjacent LE register in a LAB
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Figure 2: LAB Structure of MAX 10 Devices
Row Interconnect
LAB Interconnects
3
Column
Interconnect
Direct link interconnect from adjacent block
Direct link interconnect from adjacent block
Direct link interconnect to adjacent block
Direct link interconnect to adjacent block
LAB Local Interconnect
The Quartus
®
Prime Compiler places associated logic in a LAB or adjacent LABs, allowing the use of local and register chain connections for performance and area efficiency.
The LAB local interconnect is driven by column and row interconnects and LE outputs in the same LAB.
The direct link connection minimizes the use of row and column interconnects to provide higher perform‐ ance and flexibility. The direct link connection enables the neighboring elements from left and right to drive the local interconnect of a LAB. The elements are:
• LABs
• PLLs
• M9K embedded memory blocks
• embedded multipliers
Each LE can drive up to 48 LEs through local and direct link interconnects.
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LAB Control Signals
Figure 3: LAB Local and Direct Link Interconnects for MAX 10 Devices
Direct link interconnect from left LAB, M9K memory block, embedded multiplier,
PLL, or IOE output
Direct link interconnect from right LAB, M9K memory block, embedded multiplier,
PLL, or IOE output
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LEs
Direct link interconnect to left
Local
Interconnect
LAB
Each LAB contains dedicated logic for driving control signals to its LEs.
The control signals include:
• Two clock signals
• Two clock enable signals
• Two asynchronous clear signals
• One synchronous clear signal
• One synchronous load signal
Direct link interconnect to right
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Figure 4: LAB-Wide Control Signals for MAX 10 Devices
Dedicated
LAB Row
Clocks
Local
Interconnect
Local
Interconnect
Local
Interconnect
Local
Interconnect
6 labclkena1 labclk1 labclk2 labclkena2 syncload
LAB Control Signals
labclr1 labclr2 synclr
5
Table 1: Control Signal Descriptions for MAX 10 Devices
Control Signal
labclk1 labclk2 labclkena1 labclkena2 labclr1 labclr2 syncload synclr
Description
• Each LAB can use two clocks signals. The clock and clock enable signals of each LAB are linked. For example, any LE in a particular LAB using the labclk1
signal also uses the labclkena1
signal.
• If the LAB uses both the rising and falling edges of a clock, it also uses both LAB-wide clock signals.
• The LAB row clocks
[5..0]
and LAB local interconnect generate the
LAB-wide clock signals. The MultiTrack interconnect inherent low skew allows clock and control signal distribution in addition to data distribu‐ tion.
• Each LAB can use two clock enable signals. The clock and clock enable signals of each LAB are linked. For example, any LE in a particular LAB using the labclk1
signal also uses the labclkena1
signal.
• Deasserting the clock enable signal turns off the LAB-wide clock signal.
Asynchronous clear signals:
• LAB-wide control signals that control the logic for the clear signal of the register.
• The LE directly supports an asynchronous clear function.
Synchronous load and synchronous clear signals:
• Can be used for implementing counters and other functions
• LAB-wide control signals that affect all registers in the LAB
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Logic Elements
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You can use up to eight control signals at a time. Register packing and synchronous load cannot be used simultaneously.
Each LAB can have up to four non-global control signals. You can use additional LAB control signals as long as they are global signals.
A LAB-wide asynchronous load signal to control the logic for the preset signal of the register is not available. The register preset is achieved with a NOT gate push-back technique. MAX 10 devices only support either a preset or asynchronous clear signal.
In addition to the clear port, MAX 10 devices provide a chip-wide reset pin (
DEV_CLRn
) to reset all registers in the device. An option set before compilation in the Quartus Prime software controls this pin.
This chip-wide reset overrides all other control signals.
LE is the smallest unit of logic in the MAX 10 device family architecture. LEs are compact and provide advanced features with efficient logic usage.
Each LE has the following features:
• A four-input look-up table (LUT), which can implement any function of four variables
• A programmable register
• A carry chain connection
• A register chain connection
• The ability to drive the following interconnects:
• local
• row
• column
• register chain
• direct link
• Register packing support
• Register feedback support
LEs contain inputs, outputs and registers to enable several features.
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Figure 5: LE High-Level Block Diagram for MAX 10 Devices.
LE Carry-In
Register Chain
Routing from previous LE
LAB-Wide
Synchronous
Load
LAB-Wide
Synchronous
Clear
Register Bypass
Programmable
Register
LE Features
data 1 data 2 data 3 data 4
Look-Up Table
(LUT)
Carry
Chain
Synchronous
Load and
Clear Logic
D
ENA
CLRN
Q
Register Feedback
labclr1 labclr2
Chip-Wide
Reset
(DEV_CLRn)
Asynchronous
Clear Logic
Clock &
Clock Enable
Select
LE Carry-Out labclk1 labclk2 labclkena1 labclkena2
7
Row, Column,
And Direct Link
Routing
Row, Column,
And Direct Link
Routing
Local
Routing
Register Chain
Output
LE Inputs
There are six available inputs to the LE in both mode LE operating modes, Normal Mode and Arithmetic
Mode. Each input is directed to different destinations to implement the desired logic function. The LE inputs are:
• four data inputs from the LAB local interconnect
• an LE carry-in from the previous LE carry-chain
• a register chain connection
LE Outputs
Each LE has three outputs which are:
• Two LE outputs drive the column or row and direct link routing connections
• One LE output drives the local interconnect resources
The register packing feature is supported in MAX 10 devices. With register packing, the LUT or register output drives the three outputs independently. This feature improves device utilization by using the register and the LUT for unrelated functions.
The LAB-wide synchronous load control signal is not available when using register packing.
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LE Operating Modes
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Register Chain Output
Each LE has a register chain output which allows registers in the same LAB to cascade together. This feature speed up connections between LABs and optimize local interconnect resources by allowing the following:
• LUTs to be used for combinational functions
• registers to be used for an unrelated shift register implementation
Programmable Register
You can configure the programmable register of each LE for D, T, JK, or SR flipflop operation. Each register has the following inputs:
• clock—can be driven by signals that use the global clock network, general-purpose I/O pins or the internal logic
• clear—can be driven by signals that use the global clock network, general-purpose I/O pins or the internal logic
• clock enable—can be driven by general-purpose I/O pins or the internal logic
For combinational functions, the LUT output bypasses the register and drives directly to the LE outputs.
Register Feedback
The register feedback mode allows the register output to feed back into the LUT of the same LE. This is to ensure that the register is packed with its own fan-out LUT which provides another mechanism for improved fitting. The LE can also drive out registered and unregistered versions of the LUT output.
The LEs in MAX 10 devices operate in two modes.
• Normal mode
• Arithmetic mode
These operating modes use LE resources differently. Both LE modes have six available inputs and LABwide signals.
The Quartus Prime software automatically chooses the appropriate mode for common functions, such as counters, adders, subtractors, and arithmetic functions, in conjunction with parameterized functions such as the library of parameterized modules (LPM) functions.
You can also create special-purpose functions that specify which LE operating mode to use for optimal performance.
Normal Mode
Normal mode is suitable for general logic applications and combinational functions.
In normal mode, four data inputs from the LAB local interconnect are inputs to a four-input LUT. The
Quartus Prime Compiler automatically selects the carry-in (cin) or the data3 signal as one of the inputs to the LUT. LEs in normal mode support packed registers and register feedback.
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Figure 6: LE Operating in Normal Mode for MAX 10 devices
Packed Register Input
Register Chain
Connection sload
(LAB Wide) sclear
(LAB Wide)
Arithmetic Mode
9
data1 data2 data3 cin (from cout of previous LE) data4
Four-Input
LUT
D
ENA
CLRN
Q
Row, Column, and
Direct Link Routing
Row, Column, and
Direct Link Routing
Local Routing clock (LAB Wide) ena (LAB Wide) aclr (LAB Wide)
Register Bypass Register Feedback
Register
Chain Output
Arithmetic Mode
Arithmetic mode is ideal for implementing adders, counters, accumulators, and comparators.
The LE in arithmetic mode implements a 2-bit full adder and basic carry chain. LEs in arithmetic mode can drive out registered and unregistered versions of the LUT output. Register feedback and register packing are supported when LEs are used in arithmetic mode.
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Embedded Memory
Figure 7: LE Operating in Arithmetic Mode for MAX 10 devices
Packed Register Input
Register Chain
Connection sload
(LAB Wide) sclear
(LAB Wide)
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data4 data1 data2 data3 cin (from cout of previous LE)
Three-Input
LUT
Three-Input
LUT clock (LAB Wide) ena (LAB Wide) aclr (LAB Wide)
D
ENA
CLRN
Q
Row, Column, and
Direct link routing
Row, Column, and
Direct link routing
Local Routing cout
Register
Chain Output
Register Bypass Register Feedback
Carry Chain
The Quartus Prime Compiler automatically creates carry chain logic during design processing. You can also manually create the carry chain logic during design entry. Parameterized functions, such as LPM functions, automatically take advantage of carry chains for the appropriate functions. The Quartus Prime
Compiler creates carry chains longer than 16 LEs by automatically linking LABs in the same column.
To enhanced fitting, a long carry chain runs vertically, which allows fast horizontal connections to M9K memory blocks or embedded multipliers through direct link interconnects. For example, if a design has a long carry chain in a LAB column next to a column of M9K memory blocks, any LE output can feed an adjacent M9K memory block through the direct link interconnect.
If the carry chains run horizontally, any LAB which is not next to the column of M9K memory blocks uses other row or column interconnects to drive a M9K memory block.
A carry chain continues as far as a full column.
The MAX 10 embedded memory block is optimized for applications such as high throughput packet processing, embedded processor program, and embedded data storage.
The MAX 10 embedded memory structure consists of 9,216-bit (including parity bits) blocks. You can use each M9K block in different widths and configuration to provide various memory functions such as RAM,
ROM, shift registers, and FIFO.
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MAX 10 embedded memory supports the following general features:
Embedded Multiplier
• 8,192 memory bits per block (9,216 bits per block including parity).
• Independent read-enable ( rden
) and write-enable ( wren
) signals for each port.
• Packed mode in which the M9K memory block is split into two 4.5 K single-port RAMs.
• Variable port configurations.
• Single-port and simple dual-port modes support for all port widths.
• True dual-port (one read and one write, two reads, or two writes) operation.
• Byte enables for data input masking during writes.
• Two clock-enable control signals for each port (port A and port B).
• Initialization file to preload memory content in RAM and ROM modes.
Related Information
MAX 10 Embedded Memory User Guide
11
You can use an embedded multiplier block in one of two operational modes, depending on the application needs:
• One 18-bit x 18-bit multiplier
• Up to two 9-bit x 9-bit independent multipliers
You can also use embedded multipliers of the MAX 10 devices to implement multiplier adder and multiplier accumulator functions. The multiplier portion of the function is implemented using embedded multipliers. The adder or accumulator function is implemented in logic elements (LEs).
Related Information
MAX 10 Embedded Multiplier User Guide
You can configure each embedded multiplier to support a single 18 x 18 multiplier for input widths of 10 to 18 bits.
The following figure shows the embedded multiplier configured to support an 18-bit multiplier.
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9-Bit Multipliers
Figure 8: 18-Bit Multiplier Mode
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signa signb aclr clock ena
Data A [17..0]
Data B [17..0]
D
ENA
Q
CLRN
D
ENA
Q
CLRN
D
ENA
Q
CLRN
Data Out [35..0]
18 x 18 Multiplier
Embedded Multiplier
All 18-bit multiplier inputs and results are independently sent through registers. The multiplier inputs can accept signed integers, unsigned integers, or a combination of both. Also, you can dynamically change the signa
and signb
signals and send these signals through dedicated input registers.
You can configure each embedded multiplier to support two 9 × 9 independent multipliers for input widths of up to 9 bits.
The following figure shows the embedded multiplier configured to support two 9-bit multipliers.
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Figure 9: 9-Bit Multiplier Mode
Data A 0 [8..0]
Data B 0 [8..0]
D
ENA
Q
CLRN
D
ENA
Q
CLRN signa signb aclr clock ena
D
ENA
Q
CLRN
Clocking and PLL
13
Data Out 0 [17..0]
9 x 9 Multiplier
Data A 1 [8..0]
Data B 1 [8..0]
D
ENA
Q
CLRN
D
ENA
Q
CLRN
D
ENA
Q
CLRN
Data Out 1 [17..0]
9 x 9 Multiplier
Embedded Multiplier
All 9-bit multiplier inputs and results are independently sent through registers. The multiplier inputs can accept signed integers, unsigned integers, or a combination of both.
Each embedded multiplier block has only one signa
and one signb
signal to control the sign representa‐ tion of the input data to the block. If the embedded multiplier block has two 9 × 9 multipliers the following applies:
• The
Data A
input of both multipliers share the same signa
signal
• The
Data B
input of both multipliers share the same signb
signal
MAX 10 devices support global clock network (GCLK) and phase-locked loop (PLL).
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Global Clock Networks
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Clock networks provide clock sources for the core. You can use clock networks in high fan out global signal network such as reset and clear.
PLLs provide robust clock management and synthesis for device clock management, external system clock management, and I/O interface clocking.
Related Information
MAX 10 Clock Networks and PLLs User Guide
GCLKs drive throughout the entire device, feeding all device quadrants. All resources in the device, such as the I/O elements, logic array blocks (LABs), dedicated multiplier blocks, and M9K memory blocks can use GCLKs as clock sources. Use these clock network resources for control signals, such as clock enables and clears fed by an external pin. Internal logic can also drive GCLKs for internally-generated GCLKs and asynchronous clears, clock enables, or other control signals with high fan-out.
Figure 10: GCLK Network Sources for 10M02, 10M04, and 10M08 Devices
GCLK[5..9]
DPCLK2
DPCLK3
CLK[2,3][p,n] CLK[0,1][p,n]
DPCLK0
DPCLK1
GCLK[0..4]
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Internal Oscillator
Figure 11: GCLK Network Sources for 10M16, 10M25, 10M40, and 10M50 Devices
CLK[4,5][p,n]
15
GCLK[10..14]
GCLK[5..9]
DPCLK2
DPCLK3
CLK[2,3][p,n] CLK[0,1][p,n]
DPCLK0
DPCLK1
GCLK[0..4]
GCLK[15..19]
CLK[6,7][p,n]
MAX 10 devices have built-in internal ring oscillator with clock multiplexers and dividers. The internal ring oscillator operates up to 232 MHz which is not accessible. This operating frequency further divides down to slower frequencies.
When the oscena
input signal is asserted, the oscillator is enabled and the output can be routed to the logic array through the clkout
output signal. When the oscena
signal is set low, the clkout
signal is constant high. You can analyze this delay using the TimeQuest timing analyzer.
The main purpose of a PLL is to synchronize the phase and frequency of the voltage-controlled oscillator
(VCO) to an input reference clock.
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PLL Block and Locations
Figure 12: MAX 10 PLL High-Level Block Diagram
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Each clock source can come from any of the two or four clock pins located on the same side of the device as the PLL.
PLL lock
LOCK circuit
CLKIN
4:1
Multiplexer pfdena
4:1
Multiplexer inclk0 inclk1
Clock
Switchover
Block
÷n clkswitch clkbad0 clkbad1 activeclock
PFD CP LF
VCO
Range
Detector
VCO
8
÷2
(1)
8
÷C0
÷C1
÷C2
÷C3
÷C4
÷M
PLL output mux
GCLKs
ADC clock
(2)
External clock output
No Compensation; ZDB Mode
Source-Synchronous; Normal Mode
GCLK networks
Notes:
(1) This is the VCO post-scale counter K.
(2) Only counter C0 of PLL1 and PLL3 can drive the ADC clock.
The following figures show the physical locations of the PLLs. Every index represents one PLL in the device. The physical locations of the PLLs correspond to the coordinates in the Quartus Prime Chip
Planner.
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Figure 13: PLL Locations for 10M02 Device
Bank 8
PLL Block and Locations
17
PLL 2
(2)
PLL 1
(1)
Bank 3
Notes:
(1) Available on all packages except V36 package.
(2) Available on U324 and V36packages only.
Figure 14: PLL Locations for 10M04 and 10M08 Devices
Bank 8 Bank 7 PLL 2
(2)
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PLL 1
(1)
Bank 3 Bank 4
Notes:
(1) Available on all packages except V81 package.
(2) Available on F256, F484, U324, and V81 packages only.
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General Purpose I/O
Figure 15: PLL Locations for 10M16, 10M25, 10M40 and 10M50 Devices
PLL 3
(1)
Bank 8 Bank 7 PLL 2
(1)
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PLL 1 Bank 3 Bank 4
OCT
PLL 4
(1)
Note:
(1) Available on all packages except E144 and U169 packages.
The I/O system of MAX 10 devices support various I/O standards. In the MAX 10 devices, the I/O pins are located in I/O banks at the periphery of the devices. The I/O pins and I/O buffers have several programmable features.
Related Information
MAX 10 General Purpose I/O User Guide
The I/O elements are located in a group of four modules per I/O bank:
• High speed DDR3 I/O banks—supports various I/O standards and protocols including DDR3. These
I/O banks are available only on the right side of the device.
• High speed I/O banks—supports various I/O standards and protocols except DDR3. These I/O banks are available on the top, left, and bottom sides of the device.
• Low speed I/O banks—lower speeds I/O banks that are located at the top left side of the device.
For more information about I/O pins support, refer to the pinout files for your device.
The I/O banks are located at the periphery of the device.
For more details about the modular I/O banks available in each device package, refer to the relevant device pin-out file.
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Figure 16: I/O Banks for MAX 10 02 Devices—Preliminary
VREF8 VCCIO8
8
VREF1
VCCIO1
1
VREF2
VCCIO2
2
3
VCCIO3 VREF3
MAX 10 I/O Banks Locations
19
6
VREF6
VCCIO6
5
VREF5
VCCIO5
Low Speed I/O
High Speed I/O
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MAX 10 I/O Banks Locations
Figure 17: I/O Banks for MAX 10 04 and 08 Devices—Preliminary
VREF8 VCCIO8 VREF7 VCCIO7
8 7
VCCIO1A
VREF1
VCCIO1B
VREF2
1A
1B
2
VCCIO2
6
VREF6
VCCIO6
5
VREF5
VCCIO5
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3
VCCIO3 VREF3
4
VCCIO4 VREF4
Low Speed I/O
High Speed I/O
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Figure 18: I/O Banks for MAX 10 16, 25, 40, and 50 Devices—Preliminary
High-Speed LVDS I/O
VREF8 VCCIO8 VREF7 VCCIO7
8 7
21
VCCIO1A
VREF1
VCCIO1B
VREF2
1A
1B
2
VCCIO2
6
VREF6
VCCIO6
5
VREF5
VCCIO5
OCT
3
VCCIO3 VREF3
4
VCCIO4 VREF4
Low Speed I/O
High Speed I/O
High Speed DDR3 I/O
The MAX 10 device family supports high-speed LVDS protocols through the LVDS I/O banks and the
Altera Soft LVDS IP core.
The MAX 10 devices use registers and logic in the core fabric to implement LVDS input and output interfaces.
• For LVDS transmitters and receivers, MAX 10 devices use the the double data rate I/O (DDIO) registers that reside in the I/O elements (IOE). This architecture improves performance with regards to the receiver input skew margin (RSKM) or transmitter channel-to-channel skew (TCCS).
• For the LVDS serializer/deserializer (SERDES), MAX 10 devices use logic elements (LE) registers.
Related Information
MAX 10 High-Speed LVDS I/O User Guide
The LVDS solution uses the I/O elements and registers in the MAX 10 devices. The Altera Soft LVDS IP core implements the serializer and deserializer as soft SERDES blocks in the core logic.
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MAX 10 High-Speed LVDS I/O Location
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The MAX 10 devices do not contain dedicated serialization or deserialization circuitry:
• You can use I/O pins and core fabric to implement a high-speed differential interface in the device.
• The MAX 10 solution uses shift registers, internal PLLs, and I/O elements to perform the serial-toparallel and parallel-to-serial conversions of incoming and outgoing data.
• The Quartus Prime software uses the parameter settings of the Altera Soft LVDS IP core to automati‐ cally construct the differential SERDES in the core fabric.
Figure 19: Soft LVDS SERDES
This figure shows a transmitter and receiver block diagram for the soft LVDS SERDES circuitry with the interface signals of the transmitter and receiver data paths.
10 tx_in
ALTERA_SOFT_LVDS
tx_out inclock
C0
C1
LVDS Transmitter
tx_out tx_in
10 bits maximum data width tx_coreclock
FPGA
Fabric
rx_out rx_outclock
10 rx_out
ALTERA_SOFT_LVDS
rx_in inclock
C0
C1
LVDS Receiver
–
+ rx_in
C0
ALTPLL
C1 inclock areset rx_inclock / tx_inclock pll_areset
The I/O banks in MAX 10 devices support true LVDS input and emulated LVDS output on all I/O banks.
Only the bottom I/O banks support true LVDS output.
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Figure 20: LVDS Support in I/O Banks of 10M02 Devices
MAX 10 High-Speed LVDS I/O Location
23
This figure shows a top view of the silicon die. Each bank is labeled with the actual bank number. LVPECL support only in banks 2 and 6.
8
1
2
3
6
5
LVDS
Emulated LVDS
RSDS
Emulated RSDS
Mini-LVDS
Emulated Mini-LVDS
PPDS
Emulated PPDS
BLVDS
LVPECL
TMDS
Sub-LVDS
SLVS
HiSpi
TX RX
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MAX 10 High-Speed LVDS I/O Location
Figure 21: LVDS Support in I/O Banks of 10M04 and 10M08 Devices
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This figure shows a top view of the silicon die. Each bank is labeled with the actual bank number. LVPECL support only in banks 2 and 6.
8 7
1A
1B
2
3 4
6
5
LVDS
Emulated LVDS
RSDS
Emulated RSDS
Mini-LVDS
Emulated Mini-LVDS
PPDS
Emulated PPDS
BLVDS
LVPECL
TMDS
Sub-LVDS
SLVS
HiSpi
TX RX
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External Memory Interface
Figure 22: LVDS Support in I/O Banks of 10M16, 10M25, 10M40, and 10M50 Devices
25
This figure shows a top view of the silicon die. Each bank is labeled with the actual bank number. LVPECL support only in banks 2, 3, 6, and 8.
8 7
1A
1B
2
3 4
6
5
OCT
LVDS
Emulated LVDS
RSDS
Emulated RSDS
Mini-LVDS
Emulated Mini-LVDS
PPDS
Emulated PPDS
BLVDS
LVPECL
TMDS
Sub-LVDS
SLVS
HiSpi
TX RX
The MAX 10 devices are capable of interfacing with a broad range of external memory standards.
This capability allows you to use the MAX 10 devices in a wide range of applications such as image processing, storage, communications, and general embedded systems.
The external memory interface solution in MAX 10 devices consist of:
• The I/O elements that support external memory interfaces.
• The UniPHY IP core that allows you to configure the memory interfaces to support different external memory interface standards.
Related Information
MAX 10 External Memory Interface User Guide
In MAX 10 devices, external memory interfaces are supported only on the I/O banks on the right side of the device. You must place all external memory I/O pins on the I/O banks on the right side of the device.
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Analog-to-Digital Converter
Figure 23: I/O Banks for External Memory Interfaces
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This figure represents the top view of the silicon die that corresponds to a reverse view of the device package.
PLL 8 7 PLL
Only the top right PLL is usable for external memory interfaces
1A
1B
6
External memory interface support only available on
I/O banks on the right side of the device.
2
5
PLL 3 4
OCT
PLL
External memory interfaces support is available only for 10M16, 10M25, 10M40, and 10M50 devices.
MAX 10 devices feature up to two analog-to-digital converters (ADC). The ADCs provide the MAX 10 devices with built-in capability for on-die temperature monitoring and external analog signal conversion.
The ADC solution consists of hard IP blocks in the MAX 10 device periphery and soft logic through the
Altera Modular ADC IP core.
The ADC solution provides you with built-in capability to translate analog quantities to digital data for information processing, computing, data transmission, and control systems. The basic function is to provide a 12 bit digital representation of the analog signal being observed.
The ADC solution works in two modes:
• Normal mode—monitors up to 18 single-ended external inputs with a cumulative sampling rate of one megasymbols per second (Msps).
• Temperature sensing mode—monitors internal temperature data input with a sampling rate of up to 50 kilosymbols per second (ksps).
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Figure 24: ADC Hard IP Block in MAX 10 Devices
ADC Block Locations
27
Dedicated
Analog Input
ADC Hard IP Block
Sampling and Hold
DOUT [11:0]
ADC Analog Input
(Dual Function) [16:1]
Mux
12 bit 1 Mbps ADC
Control/Status
Temperature Sensor
ADC V
REF
Internal V
REF
Related Information
MAX 10 Analog to Digital Converter User Guide
The ADC blocks are located at the top left corner of the MAX 10 device periphery.
Figure 25: ADC Block Location in MAX 10 04 and 08 Devices
Altera Modular ADC IP Core
8 7
ADC1
PLL Clock In
Sequencer [4:0]
1A
1B
6
2 5
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I/O Bank
ADC Block
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ADC Block Locations
Figure 26: ADC Block Location in MAX 10 16 Devices
ADC1
8 7
1A
1B
2
3 4
6
5
OCT
I/O Bank
ADC Block
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Figure 27: ADC Block Location in MAX 10 25, 40, and 50 Devices
Package E144 of these devices have only one ADC block.
8 7
ADC1
ADC2
1A
1B
6
Configuration Schemes
29
2
5
3 4
OCT
I/O Bank
ADC Block
Figure 28: High-Level Overview of JTAG Configuration and Internal Configuration for MAX 10 Devices
JTAG Configuration
Configuration Data
.sof
.pof
MAX 10 Device
CRAM
Internal
Configuration
CFM
JTAG In-System Programming
Related Information
MAX 10 FPGA Configuration User Guide
In MAX 10 devices, JTAG instructions take precedence over the internal configuration scheme.
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Internal Configuration
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Using the JTAG configuration scheme, you can directly configure the device CRAM through the JTAG interface—
TDI
,
TDO
,
TMS
, and
TCK
pins. The Quartus Prime software automatically generates an SRAM
Object File (.sof). You can program the .sof using a download cable with the Quartus Prime software programmer.
You need to program the configuration data into the configuration flash memory (CFM) before internal configuration can take place. The configuration data to be written to CFM will be part of the programmer object file (
.pof
). Using JTAG In-System Programming (ISP), you can program the
.pof
into the internal flash.
During internal configuration, MAX 10 devices load the CRAM with configuration data from the CFM.
Altera MAX 10 devices feature a user flash memory (UFM) block that stores non-volatile information.
The UFM is part of the internal flash available in MAX 10 devices.
The UFM architecture of MAX 10 devices is a combination of soft and hard IPs. You can only access the
UFM using the Altera On-Chip Flash IP core in the Quartus II software.
Figure 29: Altera On-Chip Flash IP Block Diagram
Avalon-MM Avalon-MM Avalon-MM
Avalon-MM Slave
Parallel Controller
(Data)
Parallel Serial
Avalon-MM Slave
Serial Controller
(Data)
UFM Block Interface
Control Register
Status Register
Avalon-MM Slave Controller
(Control)
altera_onchip_flash
This IP block has two Avalon-MM slave controllers:
• Data—a wrapper of the UFM block that provides read and write accesses to the flash.
• Control—the CSR and status register for the flash, that is required only for write operations.
Related Information
MAX 10 User Flash Memory (UFM) User Guide
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Power Management
31
MAX 10 power optimization features are as follows:
• Single-supply or dual-supply device options
• Power-on reset (POR) circuitry
• Power management controller scheme
• Hot socketing
Related Information
Power Management User Guide
MAX 10 single-supply devices only need either a 3.0- or 3.3-V external power supply. The external power supply serves as an input to the MAX 10 device
VCC_ONE
and
VCCA
power pins. This external power supply is then regulated by an internal voltage regulator in the MAX 10 single-supply device to 1.2 V. The 1.2-V voltage level is required by core logic operation.
Figure 30: MAX 10 Single-Supply Device
VCC_ONE/VCCA
Max 10 Single-Supply Device
3.3 V/3.0 V
Voltage
Regulator
1.2 V
MAX 10 dual-supply devices require 1.2 V and 2.5 V for the device core logics and periphery operations.
Figure 31: MAX 10 Dual-Supply Device
VCCA, VCCA_ADC
(2.5 V)
MAX 10
Dual-Supply Device
VCC, VCCD_PLL, VCCINT
(1.2 V)
The power management controller scheme allows you to allocate some applications in sleep mode during runtime. This enables you to to turn off portions of the design, thus reducing dynamic power consump‐ tion. You can re-enable your application with a fast wake-up time of less than 1 ms.
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Hot Socketing
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The MAX 10 device offers hot socketing, which is also known as hot plug-in or hot swap, and power sequencing support without the use of any external devices. You can insert or remove the MAX 10 device on a board in a system during system operation. This does not affect the running system bus or the board that is inserted into the system.
The hot-socketing feature removes some encountered difficulties when using the MAX 10 device on a PCB that contains a mixture of devices with different voltage levels.
With the MAX 10 device hot-socketing feature, you no longer need to ensure a proper power-up sequence for each device on the board. MAX 10 device hot-socketing feature provides:
• Board or device insertion and removal without external components or board manipulation
• Support for any power-up sequence
• Non-intrusive I/O buffers to system buses during hot insertion
Date
August 2016
May 2016
May 2015
December 2014
September 2014
Version Changes
2016.08.11 Removed content duplication in
Embedded Multiplier
.
2016.05.13 • Added internal oscillator architectural information.
• Updated section name from
Clock Networks and PLL
to
Clocking and PLL
.
• Added high-speed LVDS circuity information.
• Added power management controller scheme and hot socketing information.
2015.05.04 • Removed 'Internal Configuration' figure.
• Added 'Overview of of JTAG Configuration and Internal Configu‐ ration for MAX 10 Devices' figure in 'Configuration'.
2014.12.15 • Updated Altera On Chip Flash IP core block diagram for user flash memory.
• Updated links.
2014.09.22 Initial release.
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TOC-2
Contents
MAX 10 Embedded Memory Overview..............................................................1-1
MAX 10 Embedded Memory Architecture and Features................................... 2-1
MAX 10 Embedded Memory Design Consideration..........................................3-1
Altera Corporation
TOC-3
Shift Register (RAM-based) IP Core References................................................ 8-1
ALTMEMMULT IP Core References.................................................................10-1
Additional Information for MAX 10 Embedded Memory User Guide.............A-1
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MAX
®
10 embedded memory block is optimized for applications such as high throughput packet processing, embedded processor program, and embedded data storage.
1
©
2016 Intel Corporation. All rights reserved. Intel, the Intel logo, Altera, Arria, Cyclone, Enpirion, MAX, Megacore, NIOS, Quartus and Stratix words and logos are trademarks of Intel Corporation in the US and/or other countries. Other marks and brands may be claimed as the property of others. Intel warrants performance of its FPGA and semiconductor products to current specifications in accordance with Intel's standard warranty, but reserves the right to make changes to any products and services at any time without notice. Intel assumes no responsibility or liability arising out of the application or use of any information, product, or service described herein except as expressly agreed to in writing by Intel. Intel customers are advised to obtain the latest version of device specifications before relying on any published information and before placing orders for products or services.
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The MAX 10 embedded memory structure consists of 9,216-bit (including parity bits) blocks. You can use each M9K block in different widths and configuration to provide various memory functions such as RAM,
ROM, shift registers, and FIFO.
The following list summarizes the MAX 10 embedded memory features:
• Embedded memory general features
• Embedded memory operation modes
• Embedded memory clock modes
Related Information
MAX 10 Device Overview
For information about MAX 10 devices embedded memory capacity and distribution
2
MAX 10 embedded memory supports the following general features:
• 8,192 memory bits per block (9,216 bits per block including parity).
• Independent read-enable ( rden
) and write-enable ( wren
) signals for each port.
• Packed mode in which the M9K memory block is split into two 4.5 K single-port RAMs.
• Variable port configurations.
• Single-port and simple dual-port modes support for all port widths.
• True dual-port (one read and one write, two reads, or two writes) operation.
• Byte enables for data input masking during writes.
• Two clock-enable control signals for each port (port A and port B).
• Initialization file to preload memory content in RAM and ROM modes.
The clock-enable control signal controls the clock entering the input and output registers and the entire
M9K memory block. This signal disables the clock so that the M9K memory block does not see any clock edges and does not perform any operations.
©
2016 Intel Corporation. All rights reserved. Intel, the Intel logo, Altera, Arria, Cyclone, Enpirion, MAX, Megacore, NIOS, Quartus and Stratix words and logos are trademarks of Intel Corporation in the US and/or other countries. Other marks and brands may be claimed as the property of others. Intel warrants performance of its FPGA and semiconductor products to current specifications in accordance with Intel's standard warranty, but reserves the right to make changes to any products and services at any time without notice. Intel assumes no responsibility or liability arising out of the application or use of any information, product, or service described herein except as expressly agreed to in writing by Intel. Intel customers are advised to obtain the latest version of device specifications before relying on any published information and before placing orders for products or services.
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Parity Bit
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The rden
and wren
control signals control the read and write operations for each port of the M9K memory blocks. You can disable the rden
or wren
signals independently to save power whenever the operation is not required.
Figure 2-1: Register Clock, Clear, and Control Signals Implementation in M9K Embedded Memory Block
Dedicated
Row LAB
Clocks
6
Local
Interconnect clock_a clock_b clocken_b clocken_a rden_a rden_b wren_a wren_b aclr_a aclr_b addressstall_b addressstall_a byteena_b byteena_a
You can perform parity checking for error detection with the parity bit along with internal logic resources.
The M9K memory blocks support a parity bit for each storage byte. You can use this bit as either a parity bit or as an additional data bit. No parity function is actually performed on this bit. If error detection is not desired, you can use the parity bit as an additional data bit.
M9K memory blocks support the read enable feature for all memory modes.
If you...
Create the read-enable port and perform a write operation with the read enable port deasserted
...Then
The data output port retains the previous values that are held during the most recent active read enable.
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If you...
• Activate the read enable during a write operation, or
• Do not create a read-enable signal
Read-During-Write
...Then
The output port shows:
• the new data being written,
• the old data at that address, or
• a “Don't Care” value when read-during-write occurs at the same address location.
2-3
The read-during-write operation occurs when a read operation and a write operation target the same memory location at the same time.
The read-during-write operation operates in the following ways:
• Same-port
• Mixed-port
Related Information
Customize Read-During-Write Behavior
• Memory block that are implemented as RAMs support byte enables.
• The byte enable controls mask the input data, so that only specific bytes of data are written. The unwritten bytes retain the values written previously.
• The write enable ( wren
) signal, together with the byte enable ( byteena
) signal, control the write operations on the RAM blocks. By default, the byteena
signal is high (enabled) and only the wren signal controls the writing.
• The byte enable registers do not have a clear
port.
• M9K blocks support byte enables when the write port has a data width of ×16, ×18, ×32, or ×36 bits.
• Byte enables operate in a one-hot fashion. The LSB of the byteena
signal corresponds to the LSB of the data bus. For example, if byteena = 01
and you are using a RAM block in ×18 mode, data[8:0]
is enabled and data[17:9]
is disabled. Similarly, if byteena = 11
, both data[8:0]
and data[17:9]
are enabled.
• Byte enables are active high.
Table 2-1: M9K Blocks Byte Enable Selections byteena[3:0]
[0] = 1
[1] = 1
[2] = 1
Affected Bytes. Any Combination of Byte Enables is Possible.
datain x 16
[7:0]
[15:8]
—
datain x 18
[8:0]
[17:9]
—
datain x 32
[7:0]
[15:8]
[23:16]
datain x 36
[8:0]
[17:9]
[26:18]
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Data Byte Output byteena[3:0]
[3] = 1
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Affected Bytes. Any Combination of Byte Enables is Possible.
datain x 16
—
datain x 18
—
datain x 32
[31:24]
datain x 36
[35:27]
If you...
Deassert a byte-enable bit during a write cycle
Assert a byte-enable bit during a write cycle
...Then
The old data in the memory appears in the corresponding data-byte output.
The corresponding data-byte output depends on the
Quartus
®
Prime software setting. The setting can be either the newly written data or the old data at that location.
This figure shows how the wren
and byteena
signals control the RAM operations.
Figure 2-2: Byte Enable Functional Waveform
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Packed Mode Support
You can implement two single-port memory blocks in a single block under the following conditions:
• Each of the two independent block sizes is less than or equal to half of the M9K block size. The maximum data width for each independent block is 18 bits wide.
• Each of the single-port memory blocks is configured in single-clock mode.
2-5
Related Information
MAX 10 Embedded Memory Clock Modes
on page 2-10
• The address clock enable feature holds the previous address value for as long as the address clock enable signal ( addressstall
) is enabled ( addressstall = 1
).
• When you configure M9K memory blocks in dual-port mode, each port has its own independent address clock enable.
• Use the address clock enable feature to improve the effectiveness of cache memory applications during a cache-miss.
• The default value for the addressstall
signal is low.
• The address register output feeds back to its input using a multiplexer. The addressstall
signal selects the multiplexer output.
Figure 2-3: Address Clock Enable Block Diagram
address[0] address[0] register address[0] address[N] addressstall clock address[N] register address[N]
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Address Clock Enable During Read Cycle Waveform
Figure 2-4: Address Clock Enable Waveform During Read Cycle
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Figure 2-5: Address Clock Enable Waveform During Write Cycle
You can selectively enable asynchronous clear per logical memory using the RAM: 1-PORT and RAM: 2-
PORT IP cores.
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Resetting Registers in M9K Blocks
2-7
The M9k block supports asynchronous clear for:
• Read address registers: Asserting asynchronous clear to the read address register during a read operation might corrupt the memory content.
• Output registers: When applied to output registers, the asynchronous clear signal clears the output registers and the effects are immediately seen. If your RAM does not use output registers, you can still clear the RAM outputs using the output latch asynchronous clear feature.
• Output latches
Note: Input registers other than read address registers are not supported.
Figure 2-6: Output Latch Asynchronous Clear Waveform
Related Information
Internal Memory (RAM and ROM) User Guide.
There are three ways to reset registers in the M9K blocks:
• Power up the device
• Use the aclr
signal for output register only
• Assert the device-wide reset signal using the DEV_CLRn option
The M9K memory blocks allow you to implement fully-synchronous SRAM memory in multiple operation modes. The M9K memory blocks do not support asynchronous (unregistered) memory inputs.
Note: Violating the setup or hold time on the M9K memory block input registers may corrupt memory contents. This applies to both read and write operations.
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Supported Memory Operation Modes
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Table 2-2: Supported Memory Operation Modes in the M9K Embedded Memory Blocks
Memory Operation Mode
Single-port RAM
Related IP Core
RAM: 1-PORT IP Core
Description
Single-port mode supports non-simultaneous read and write operations from a single address.
Use the read enable port to control the RAM output ports behavior during a write operation:
• To show either the new data being written or the old data at that address, activate the read enable during a write operation.
• To retain the previous values that are held during the most recent active read enable, perform the write operation with the read enable port deasserted.
Simple dual-port RAM RAM: 2-PORT IP Core
You can simultaneously perform one read and one write operations to different locations where the write operation happens on port A and the read operation happens on port B.
True dual-port RAM RAM: 2-PORT IP Core
Single-port ROM ROM: 1-PORT IP Core
You can perform any combination of two port operations:
• two reads, two writes, or,
• one read and one write at two different clock frequencies.
Only one address port is available for read operation.
You can use the memory blocks as a ROM.
• Initialize the ROM contents of the memory blocks using a .mif or .hex file.
• The address lines of the ROM are registered.
• The outputs can be registered or unregistered.
• The ROM read operation is identical to the read operation in the single-port RAM configuration.
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Memory Operation Mode
Dual-port ROM
Shift-register
FIFO
Memory-based multiplier
Supported Memory Operation Modes
2-9
Related IP Core
ROM: 2-PORT IP Core
Description
The dual-port ROM has almost similar functional ports as single-port ROM. The difference is dualport ROM has an additional address port for read operation.
You can use the memory blocks as a ROM.
• Initialize the ROM contents of the memory blocks using a .mif or .hex file.
• The address lines of the ROM are registered.
• The outputs can be registered or unregistered.
• The ROM read operation is identical to the read operation in the single-port RAM configuration.
Shift Register (RAMbased) IP Core
You can use the memory blocks as a shift-register block to save logic cells and routing resources.
The input data width (w), the length of the taps (m), and the number of taps (n) determine the size of a shift register (w × m × n).
You can cascade memory blocks to implement larger shift registers.
FIFO IP Core
You can use the memory blocks as FIFO buffers.
• Use the FIFO IP core in single clock FIFO
(SCFIFO) mode and dual clock FIFO (DCFIFO) mode to implement single- and dual-clock FIFO buffers in your design.
• Use dual clock FIFO buffers when transferring data from one clock domain to another clock domain.
• The M9K memory blocks do not support simultaneous read and write from an empty
FIFO buffer.
ALTMEMMULT IP Core You can use the memory blocks as a memory-based multiplier.
Related Information
MAX 10 Embedded Memory Related IPs
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Clock Mode Description
Independent
Clock Mode
A separate clock is available for the following ports:
• Port A—Clock A controls all registers on the port A side.
• Port B—Clock B controls all registers on the port B side.
Input/Output
Clock Mode
• M9K memory blocks can implement input or output clock mode for single-port, true dual-port, and simple dual-port memory modes.
• An input clock controls all input registers to the memory block, including data
, address
, byteena
, wren
, and rden
registers.
• An output clock controls the data-output registers.
Read or Write
Clock Mode
• M9K memory blocks support independent clock enables for both the read and write clocks.
• A read clock controls the data outputs, read address, and read enable registers.
• A write clock controls the data inputs, write address, and write enable registers.
Single-Clock
Mode
A single clock, together with a clock enable, controls all registers of the memory block.
True
Dual-
Port
Yes
Yes
—
Yes
Simple
Dual-
Port
—
Modes
Single-
Port
—
ROM
Yes
Yes
Yes
Yes
Yes
—
Yes
Yes
—
Yes
FIFO
—
—
Yes
Yes
•
•
•
Related Information
on page 2-5
Control Clocking to Reduce Power Consumption
Output Read Data in Simultaneous Read and Write
In all clock modes, asynchronous clear is available only for output latches and output registers. For independent clock mode, this is applicable on port A and port B.
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Output Read Data in Simultaneous Read and Write
2-11
If you perform a simultaneous read/write to the same address location using the read or write clock mode, the output read data is unknown. If you want the output read data to be a known value, use single-clock or input/output clock mode and then select the appropriate read-during-write behavior in the RAM: 1-PORT and RAM: 2-PORT IP cores.
Related Information
MAX 10 Embedded Memory Clock Modes
on page 2-10
Table 2-3: Supported Clock Modes for Independent Clock Enables
Clock Mode
Read/write
Independent
Description
Supported for both the read and write clocks.
Supported for the registers of both ports.
Table 2-4: Single-port Memory Configurations for M9K Blocks
Configuration
Depth × width
M9K Block
8192 × 1
4096 × 2
2048 × 4
1024 × 8
1024 × 9
512 × 16
512 × 18
256 × 32
256 × 36
The following equation defines the port width configuration: Memory depth (number of words) × Width of the data input bus.
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Memory Configurations for Dual-Port Modes
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• If your port width configuration (either the depth or the width) is more than the amount an internal memory block can support, additional memory blocks (of the same type) are used. For example, if you configure your M9K as 512 × 36, which exceeds the supported port width of 512 × 18, two M9Ks are used to implement your RAM.
• In addition to the supported configuration provided, you can set the memory depth to a non-power of two, but the actual memory depth allocated can vary. The variation depends on the type of resource implemented.
• If the memory is implemented in dedicated memory blocks, setting a non-power of two for the memory depth reflects the actual memory depth.
• When you implement your memory using dedicated memory blocks, refer to the Fitter report to check the actual memory depth.
Table 2-5: Simple Dual-port Memory Configurations
Read
Port
Write Port
8192 × 1 4096 × 2 2048 × 4 1024 × 8 512 × 16 256 × 32 1024 × 9 512 × 18
Yes Yes Yes Yes Yes Yes — —
1024
× 8
512 ×
16
256 ×
32
8192
× 1
4096
× 2
2048
× 4
1024
× 9
512 ×
18
256 ×
36
Yes
Yes
Yes
Yes
Yes
—
—
—
Yes
Yes
Yes
Yes
Yes
—
—
—
Yes
Yes
Yes
Yes
Yes
—
—
—
Yes
Yes
Yes
Yes
Yes
—
—
—
Yes
Yes
Yes
Yes
Yes
—
—
—
Yes
Yes
Yes
Yes
Yes
—
—
—
—
—
—
—
—
Yes
Yes
Yes
—
—
—
—
—
Yes
Yes
Yes
—
—
—
—
—
—
Yes
Yes
Yes
256 × 36
Table 2-6: True Dual-port Memory Configurations
Read Port
8192 × 1
8192 × 1
Yes
4096 × 2
Yes
2048 × 4
Yes
Write Port
1024 × 8
Yes
512 × 16
Yes
1024 × 9
—
512 × 18
—
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Read Port
4096 × 2
2048 × 4
1024 × 8
512 × 16
1024 × 9
512 × 18
8192 × 1
Yes
Yes
Yes
Yes
—
—
4096 × 2
Yes
Yes
Yes
Yes
—
—
2048 × 4
Yes
Yes
Yes
Yes
—
—
Maximum Block Depth Configuration
Write Port
1024 × 8 512 × 16
Yes
Yes
Yes
Yes
—
—
Yes
Yes
Yes
Yes
—
—
1024 × 9
—
—
—
—
Yes
Yes
512 × 18
—
—
—
—
Yes
Yes
2-13
The Set the maximum block depth parameter allows you to set the maximum block depth of the dedicated memory block you use. You can slice the memory block to your desired maximum block depth.
For example, the capacity of an M9K block is 9,216 bits, and the default memory depth is 8K, in which each address is capable of storing 1 bit (8K × 1). If you set the maximum block depth to 512, the M9K block is sliced to a depth of 512 and each address is capable of storing up to 18 bits (512 × 18).
Use this parameter to save power usage in your devices and to reduce the total number of memory blocks used. However, this parameter might increase the number of LEs and affects the design performance.
When the RAM is sliced shallower, the dynamic power usage decreases. However, for a RAM block with a depth of 256, the power used by the extra LEs starts to outweigh the power gain achieved by shallower slices.
The maximum block depth must be in a power of two, and the valid values vary among different dedicated memory blocks.
This table lists the valid range of maximum block depth for M9K memory blocks.
Table 2-7: Valid Range of Maximum Block Depth for M9K Memory Blocks
M9K
Memory Block Valid Range
256 - 8K. The maximum block depth must be in a power of two.
The IP parameter editor prompts an error message if you enter an invalid value for the maximum block depth. Altera recommends that you set the value of the Set the maximum block depth parameter to Auto if you are unsure of the appropriate maximum block depth to set or the setting is not important for your design. The Auto setting enables the Compiler to select the maximum block depth with the appropriate port width configuration for the type of internal memory block of your memory.
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There are several considerations that require your attention to ensure the success of your designs.
In the true dual-port RAM mode, you can perform two write operations to the same memory location.
However, the memory blocks do not have internal conflict resolution circuitry.
To avoid unknown data being written to the address, implement external conflict resolution logic to the memory block.
Customize the read-during-write behavior of the memory blocks to suit your design requirements.
Figure 3-1: Difference Between the Two Types of Read-during-Write Operations —Same Port and Mixed
Port.
3
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2016 Intel Corporation. All rights reserved. Intel, the Intel logo, Altera, Arria, Cyclone, Enpirion, MAX, Megacore, NIOS, Quartus and Stratix words and logos are trademarks of Intel Corporation in the US and/or other countries. Other marks and brands may be claimed as the property of others. Intel warrants performance of its FPGA and semiconductor products to current specifications in accordance with Intel's standard warranty, but reserves the right to make changes to any products and services at any time without notice. Intel assumes no responsibility or liability arising out of the application or use of any information, product, or service described herein except as expressly agreed to in writing by Intel. Intel customers are advised to obtain the latest version of device specifications before relying on any published information and before placing orders for products or services.
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Same-Port Read-During-Write Mode
Related Information
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The same-port read-during-write mode applies to a single-port RAM or the same port of a true dual-port
RAM.
Table 3-1: Output Modes for Embedded Memory Blocks in Same-Port Read-During-Write Mode
This table lists the available output modes if you select the embedded memory blocks in the same-port read-during-write mode.
Output Mode Description
"new data"
(flow-through)
The new data is available on the rising edge of the same clock cycle on which the new data is written.
When using New Data mode together with byte enable, you can control the output of the RAM.
When byte enable is high, the data written into the memory passes to the output (flow-through).
When byte enable is low, the masked-off data is not written into the memory and the old data in the memory appears on the outputs. Therefore, the output can be a combination of new and old data determined by byteena.
"don't care" The RAM outputs reflect the old data at that address before the write operation proceeds.
Figure 3-2: Same-Port Read-During-Write: New Data Mode
clk_a wren_a rden_a address_a data_a q_a (asynch)
A
A a0
B
B
C
C
D
D a1
E
E
F
F
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Figure 3-3: Same Port Read-During-Write: Old Data Mode
clk_a wren_a rden_a address_a data_a q_a (asynch)
A
a0
B
A
C
B
Mixed-Port Read-During-Write Mode
3-3
D
a1
E
D
F
E
The mixed-port read-during-write mode applies to simple and true dual-port RAM modes where two ports perform read and write operations on the same memory address using the same clock—one port reading from the address, and the other port writing to it.
Table 3-2: Output Modes for RAM in Mixed-Port Read-During-Write Mode
Output Mode
"old data"
Description
A read-during-write operation to different ports causes the RAM output to reflect the “old data” value at the particular address.
"don't care"
The RAM outputs “don’t care” or “unknown” value.
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Mixed-Port Read-During-Write Operation with Dual Clocks
Figure 3-4: Mixed-Port Read-During-Write: Old Data Mode
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clk_a&b wren_a address_a data_a
A a
B C D E b
F rden_b address_b q_b (asynch) a b a (old data)
A
B b (old data)
In Don't Care mode, the old data is replaced with “Don't Care”.
D E
For mixed-port read-during-write operation with dual clocks, the relationship between the clocks determines the output behavior of the memory.
If You...
Use the same clock for the two clocks
Use different clocks
...Then
The output is the old data from the address location.
The output is unknown during the mixed-port readduring-write operation. This unknown value may be the old or new data at the address location, depending on whether the read happens before or after the write.
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Consider Power-Up State and Memory Initialization
Consider the power-up state of the different types of memory blocks if you are designing logic that evaluates the initial power-up values, as listed in the following table:
Table 3-3: Initial Power-Up Values of Embedded Memory Blocks
Memory Type
M9K
Output Registers
Used
Bypassed
Power Up Value
Zero (cleared)
Zero (cleared)
3-5
By default, the Quartus Prime software initializes the RAM cells to zero unless you specify a .mif.
All memory blocks support initialization with a .mif. You can create .mif files in the Quartus Prime software and specify their use with the RAM IP when you instantiate a memory in your design. Even if a memory is preinitialized (for example, using a .mif), it still powers up with its output cleared. Only the subsequent read after power up outputs the preinitialized values.
Only the following MAX 10 configuration modes support memory initialization:
• Single Compressed Image with Memory Initialization
• Single Uncompressed Image with Memory Initialization
Note: The memory initialization feature is supported in MAX 10 Flash and Analog feature options only
•
•
Related Information
Selecting Internal Configuration modes.
Provides more information about selecting MAX 10 internal configuration modes.
MAX 10 Device Feature Options
Provides information on devices that support memory initialization.
Reduce AC power consumption in your design by controlling the clocking of each memory block:
• Use the read-enable signal to ensure that read operations occur only when necessary. If your design does not require read-during-write, you can reduce your power consumption by deasserting the readenable signal during write operations, or during the period when no memory operations occur.
• Use the Quartus Prime software to automatically place any unused memory blocks in low-power mode to reduce static power.
• Create independent clock enable for different input and output registers to control the shut down of a particular register for power saving purposes. From the parameter editor, click More Options (beside the clock enable option) to set the available independent clock enable that you prefer.
Related Information
MAX 10 Embedded Memory Clock Modes
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Selecting Read-During-Write Output Choices
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• Single-port RAM only supports same-port read-during-write, and the clock mode must be either single clock mode, or input/output clock mode.
• Simple dual-port RAM only supports mixed-port read-during-write, and the clock mode must be either single clock mode, or input/output clock mode.
• True dual-port RAM supports same port read-during-write and mixed-port read-during-write.
• For same port read-during-write, the clock mode must be either single clock mode, input/output clock mode, or independent clock mode.
• For mixed port read-during-write, the clock mode must be either single clock mode, or input/ output clock mode.
Note: If you are not concerned about the output when read-during-write occurs and would like to improve performance, select Don't Care. Selecting Don't Care increases the flexibility in the type of memory block being used, provided you do not assign block type when you instantiate the memory block.
Table 3-4: Output Choices for the Same-Port and Mixed-Port Read-During-Write
Memory Block
Single-Port RAM
Same-Port
Read-During-
Write
Simple Dual-
Port RAM
Mixed-Port
Read-During-
Write
Same-Port
Read-During-
Write
True Dual-Port RAM
Mixed-Port Read-During-Write
M9K
Don’t Care
New Data
Old Data
Old Data
Don’t Care
New Data
Old Data
Old Data
Don’t Care
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The RAM: 1-Port IP core implements the single-port RAM memory mode.
Figure 4-1: RAM: 1-Port IP Core Signals with the Single Clock Option Enabled
q[] data[] wren address[] addressstall_a rden clock clken
Figure 4-2: RAM: 1-Port IP Core Signals with the Dual Clock Option Enabled
q[] data[] wren address[] addressstall_a rden inclock inclocken outclock outclocken
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2016 Intel Corporation. All rights reserved. Intel, the Intel logo, Altera, Arria, Cyclone, Enpirion, MAX, Megacore, NIOS, Quartus and Stratix words and logos are trademarks of Intel Corporation in the US and/or other countries. Other marks and brands may be claimed as the property of others. Intel warrants performance of its FPGA and semiconductor products to current specifications in accordance with Intel's standard warranty, but reserves the right to make changes to any products and services at any time without notice. Intel assumes no responsibility or liability arising out of the application or use of any information, product, or service described herein except as expressly agreed to in writing by Intel. Intel customers are advised to obtain the latest version of device specifications before relying on any published information and before placing orders for products or services.
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Table 4-1: RAM:1-Port IP Core Input Signals
Signal
data
Yes
Required
address wren addressstall_a
Yes
Yes
Optional clock clkena rden aclr
Yes
Optional
Optional
Optional
Description
Data input to the memory. The data
port is required and the width must be equal to the width of the q
port.
Address input to the memory.
Write enable input for the wraddress
port.
Address clock enable input to hold the previous address of address_a
port for as long as the addressstall_a port is high.
The following list describes which of your memory clock must be connected to the clock port, and port synchronization in different clocking modes:
• Single clock—Connect your single source clock to clock
port. All registered ports are synchronized by the same source clock.
• Read/Write—Connect your write clock to clock port. All registered ports related to write operation, such as data_a
port, address_a
port, wren_a
port, and byteena_a
port are synchronized by the write clock.
• Input/Output—Connect your input clock to clock port. All registered input ports are synchronized by the input clock.
• Independent clock—Connect your port A clock to clock
port. All registered input and output ports of port A are synchronized by the port A clock.
Clock enable input for clock
port.
Read enable input for rdaddress
port.
Asynchronously clear the registered input and output ports. The asynchronous clear effect on the registered ports can be controlled through their corresponding asynchronous clear parameter, such as indata_aclr, wraddress_aclr, and so on.
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inclock inclocken outclock outclocken
Signal Required
Optional
Optional
Optional
Optional
RAM: 1-Port IP Core Parameters For MAX 10 Devices
4-3
Description
The following list describes which of your memory clock must be connected to the inclock port, and port synchronization in different clock modes:
• Single clock—Connect your single source clock to inclock
port and outclock
port. All registered ports are synchronized by the same source clock.
• Read/Write—Connect your write clock to inclock port. All registered ports related to write operation, such as data
port, wraddress
port, wren
port, and byteena
port are synchronized by the write clock.
• Input/Output—Connect your input clock to inclock
port. All registered input ports are synchronized by the input clock.
Clock enable input for inclock
port.
The following list describes which of your memory clock must be connected to the outclock
port, and port synchronization in different clock modes:
• Single clock—Connect your single source clock to inclock
port and outclock
port. All registered ports are synchronized by the same source clock.
• Read/Write—Connect your read clock to outclock port. All registered ports related to read operation, such as rdaddress
port, rdren
port, and q
port are synchronized by the read clock.
• Input/Output—Connect your output clock to outclock
port. The registered q
port is synchronized by the output clock.
Clock enable input for outclock
port.
Table 4-2: RAM:1-Port IP Core Output Ports
Signal
q
Yes
Required Description
Data output from the memory. The q
port must be equal to the width data port.
Table 4-3: RAM: 1-Port IP Core Parameters for MAX 10 Devices
This table lists the IP core parameters applicable to MAX 10 devices.
Parameter Values
Parameter Settings: Widths/Blk Type/Clks
Description
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Specifies the width of the 'q' output bus in bits.
Description
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Parameter Values
How wide should the 'q' output bus be?
How many <X>-bit words of memory?
1, 2, 3, 4, 5, 6, 7, 8, 9,
10, 11, 12, 13, 14, 15,
16, 17, 18, 19, 20, 21,
22, 23, 24, 25, 26, 27,
28, 29, 30, 31, 32, 36,
40, 48, 64, 72, 108,
128, 144, and 256.
32, 64, 128, 256, 512,
1024, 2048, 4096,
8192, 16384, 32768, and 65536.
What should the memory block type be?
Auto
M9K
LC
Use default logic cell style
On/Off
On/Off
On/Off
On/Off
Options
Use Stratix
M512 emulation logic cell style
Set the maximum block depth to
On/Off
Auto, 32, 64, 128,
256, 512, 1024, 2048,
4096, and 8192
What clocking method would you like to use?
Single clock On/Off
Dual clock: use separate ‘input’ and
‘output’ clocks
On/Off
Specifies the number of <X>-bit words.
Specifies the memory block type. The types of memory block that are available for selection depends on your target device.
Specifies the logic cell implementation options. This option is enabled only when you choose LCs memory type.
Specifies the maximum block depth in words. This option is disabled only when you choose LCs memory type.
A single clock and a clock enable controls all registers of the memory block.
An input and an output clock controls all registers related to the data input and output to/from the memory block including data, address, byte enables, read enables, and write enables.
Parameter Settings: Regs/Clkens/Byte Enable/Aclrs
Which ports should be registered?
'data' and 'wren' input ports —
'address' input port
'q' output port
—
On/Off
This option is automatically enabled.
Specifies whether to register the read or write input and output ports.
This option is automatically enabled.
Specifies whether to register the read or write input and output ports.
Specifies whether to register the read or write input and output ports.
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clock signal.
More Options
More Options
Parameter
Create one clock enable signal for each
Use clock enable for port A input registers
Use clock enable for port A output registers
Create an
'addressstall_a' input port
On/Off
On/Off
On/Off
Create an ‘aclr’ asynchronous clear for the registered ports.
'q' port
Create a 'rden' read enable signal
On/Off
RAM: 1-Port IP Core Parameters For MAX 10 Devices
Values
4-5
Description
Specifies whether to turn on the option to create one clock enable signal for each clock signal.
Specify whether to use clock enable for port A input and output registers.
On/Off
On/Off
On/Off
Specify whether to use clock enable for port A input and output registers.
Specifies whether to create clock enables for address registers. You can create these ports to act as an extra active low clock enable input for the address registers.
Specifies whether to create an asynchronous clear port for the registered ports.
Specifies whether the q
port is cleared by the aclr
port.
Specifies whether to create a rden
read enable signal.
Parameter Settings: Read During Write Option
Single Port Read During Write Option
What should the q output be when reading from a memory location being written to?
• Don't Care
• New Data
• Old Data
Get x's for write masked bytes instead of old data when byte enable is used
No, leave it blank
On/Off
Parameter Settings: Mem Init
Do you want to specify the initial content of the memory?
On/Off
Specifies the output behavior when read-during-write occurs.
• Don't Care—The RAM outputs
"don't care" or "unknown" values for read-during-write operation.
• New Data—New data is available on the rising edge of the same clock cycle on which it was written.
• Old Data— The RAM outputs reflect the old data at that address before the write operation proceeds.
Turn on this option to obtain 'X' on the masked byte.
Specifies the initial content of the memory. Initialize the memory to zero.
Initialize memory content data to XX..X
on power-up in simulation
On/Off
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Parameter
Yes, use this file for the memory content data
On/Off
Values
Allow In-System Memory Content Editor to capture and update content independ‐ ently of the system clock
The 'Instance ID' of this RAM is
On/Off
—
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Description
Allows you to specify a memory initialization file (.mif) or a hexadec‐ imal (Intel-format) file (.hex).
Note: The configuration scheme of your device is Internal
Configuration. In order to use memory initialization, you must select a single image configuration mode with memory initialization, for example the Single
Compressed Image with
Memory Initialization option. You can set the configuration mode on the
Configuration page of the
Device and Pin Options
dialog box.
Specifies whether to allow In-System
Memory Content Editor to capture and update content independently of the system clock.
Specifies the RAM ID.
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The RAM: 2-PORT IP core implements the simple dual-port RAM and true dual-port RAM memory modes.
Figure 5-1: RAM: 2-Port IP Core Signals With the One Read Port and One Write Port, and Single Clock
Options Enabled
5
q[] data[] wraddress[] wren rdaddress[] rden byteena_a[] wr_addressstall rd_addressstall clock enable
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2016 Intel Corporation. All rights reserved. Intel, the Intel logo, Altera, Arria, Cyclone, Enpirion, MAX, Megacore, NIOS, Quartus and Stratix words and logos are trademarks of Intel Corporation in the US and/or other countries. Other marks and brands may be claimed as the property of others. Intel warrants performance of its FPGA and semiconductor products to current specifications in accordance with Intel's standard warranty, but reserves the right to make changes to any products and services at any time without notice. Intel assumes no responsibility or liability arising out of the application or use of any information, product, or service described herein except as expressly agreed to in writing by Intel. Intel customers are advised to obtain the latest version of device specifications before relying on any published information and before placing orders for products or services.
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Figure 5-2: RAM: 2-Port IP Core Signals with the One Read Port and One Write Port, and Dual Clock: Use
Separate 'Read' and 'Write' Clocks Options Enabled
q[] data[] wraddress[] wren rdaddress[] rden byteena_a[] wr_addressstall rd_addressstall wrclock wrclocken rdclock rdclocken rdinclocken rdoutclocken
Figure 5-3: RAM: 2-Port IP Core Signals with the One Read Port and One Write Port, and Dual Clock: Use
Separate 'Input' and 'Output' Clocks Options Enabled
q[] data[] wraddress[] wren rdaddress[] rden byteena_a[] wr_addressstall rd_addressstall inclock inclocken outclock outclocken
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RAM: 2-PORT IP Core References
5-3
Figure 5-4: RAM: 2-Port IP Core Signals with the Two Read/Write Ports and Single Clock Options Enabled
data_a[] address_a[] wren_a rden_a data_b[] address_b[] wren_b rden_b byteena_a[] addressstall_a addressstall_b clock enable q_a[] q_b[]
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Figure 5-5: RAM: 2-Port IP Core Signals with the Two Read/Write Ports and Dual Clock: Use Separate 'Input' and 'Output' Clocks Options Enabled
data_a[] address_a[] wren_a rden_a data_b[] address_b[] wren_b rden_b byteena_a[] addressstall_a addressstall_b inclock inclocken outclock outclocken q_a[] q_b[]
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RAM: 2-Ports IP Core Signals (Simple Dual-Port RAM) For MAX 10 Devices
5-5
Figure 5-6: RAM: 2-Port IP Core Signals with the Two Read/Write Ports and Dual Clock: Use Separate for A and B Ports Options Enabled
data_a[] address_a[] wren_a rden_a data_b[] address_b[] wren_b rden_b byteena_a[] addressstall_a addressstall_b clock_a enable_a clock_b enable_b q_a[] q_b[]
Table 5-1: RAM: 2-Ports IP Core Input Signals (Simple Dual-Port RAM)
data
Signal Required
Yes wraddress wren rdaddress
Yes
Yes
Yes
Description
Data input to the memory. The data
port is required and the width must be equal to the width of the q
port.
Write address input to the memory. The wraddress
port is required and must be equal to the width of the raddress
port.
Write enable input for wraddress
port. The wren
port is required.
Read address input to the memory. The rdaddress
port is required and must be equal to the width of wraddress
port.
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rden
RAM: 2-Ports IP Core Signals (Simple Dual-Port RAM) For MAX 10 Devices
clock inclock
Signal
outclock
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Required
Yes
Description
The following list describes which of your memory clock must be connected to the clock
port, and port synchronization in different clock modes:
• Single clock—Connect your single source clock to clock port. All registered ports are synchronized by the same source clock.
• Read/Write—Connect your write clock to clock
port. All registered ports related to write operation, such as data_a port, address_a
port, wren_a
port, and byteena_a
port are synchronized by the write clock.
• Input/Output—Connect your input clock to clock
port. All registered input ports are synchronized by the input clock.
• Independent clock—Connect your port A clock to clock port. All registered input and output ports of port A are synchronized by the port A clock.
Yes
Yes
The following list describes which of your memory clock must be connected to the inclock
port, and port synchronization in different clock modes:
• Single clock—Connect your single source clock to inclock port and outclock
port. All registered ports are synchron‐ ized by the same source clock.
• Read/Write—Connect your write clock to inclock
port. All registered ports related to write operation, such as data
port, wraddress
port, wren
port, and byteena
port are synchron‐ ized by the write clock.
• Input/Output—Connect your input clock to inclock
port.
All registered input ports are synchronized by the input clock.
The following list describes which of your memory clock must be connected to the outclock
port, and port synchronization in different clock modes:
• Single clock—Connect your single source clock to inclock port and outclock
port. All registered ports are synchron‐ ized by the same source clock.
• Read/Write—Connect your read clock to outclock
port. All registered ports related to read operation, such as rdaddress port, rdren
port, and q
port are synchronized by the read clock.
• Input/Output—Connect your output clock to outclock port. The registered q
port is synchronized by the output clock.
Optional Read enable input for rdaddress
port. The rden
port is supported when the use_eab
parameter is set to
OFF
. Instantiate the IP core if you want to use read enable feature with other memory blocks.
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Signal
byteena_a outclocken inclocken
RAM: 2-Port IP Core Signals (True Dual-Port RAM) for MAX 10 Devices
Required Description
Optional Byte enable input to mask the data_a
port so that only specific bytes, nibbles, or bits of the data are written. The byteena_a port is not supported in the following conditions:
• If the implement_in_les
parameter is set to
ON
.
• If the operation_mode
parameter is set to
ROM
.
Optional Clock enable input for outclock
port.
Optional Clock enable input for inclock
port.
5-7
Table 5-2: RAM: 2-Ports IP Core Output Signals (Simple Dual-Port RAM)
q
Signal Required
Yes
Description
Data output from the memory. The q
port is required, and must be equal to the width data port.
Table 5-3: RAM: 2-Port IP Core Input Signals (True Dual-Port RAM)
data_a
Signal Required
Optional
Description
•
•
•
Data input to port A of the memory. The data_a
port is required if the operation_mode
parameter is set to any of the following values:
SINGLE_PORT
DUAL_PORT
BIDIR_DUAL_PORT address_a
Yes wren_a data_b
Optional
Optional
•
•
•
Address input to port A of the memory. The address_a
port is required for all operation modes.
Write enable input for address_a
port. The wren_a
port is required if you set the operation_mode
parameter to any of the following values:
SINGLE_PORT
DUAL_PORT
BIDIR_DUAL_PORT
Data input to port B of the memory. The data_b
port is required if the operation_mode
parameter is set to
BIDIR_
DUAL_PORT
.
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Signal
address_b wren_b clock inclock
Required
Optional
Yes
Yes
Yes
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Description
•
•
Address input to port B of the memory. The address_b
port is required if the operation_mode
parameter is set to the following values:
DUAL_PORT
BIDIR_DUAL_PORT
Write enable input for address_b
port. The wren_b
port is required if you set the operation_mode
parameter to
BIDIR_
DUAL_PORT
.
The following list describes which of your memory clock must be connected to the clock
port, and port synchronization in different clock modes:
• Single clock—Connect your single source clock to clock port. All registered ports are synchronized by the same source clock.
• Read/Write—Connect your write clock to clock
port. All registered ports related to write operation, such as data_a port, address_a
port, wren_a
port, and byteena_a
port are synchronized by the write clock.
• Input/Output—Connect your input clock to clock
port. All registered input ports are synchronized by the input clock.
• Independent clock—Connect your port A clock to clock port. All registered input and output ports of port A are synchronized by the port A clock.
The following list describes which of your memory clock must be connected to the inclock
port, and port synchronization in different clock modes:
• Single clock—Connect your single source clock to inclock port and outclock
port. All registered ports are synchron‐ ized by the same source clock.
• Read/Write—Connect your write clock to inclock
port. All registered ports related to write operation, such as data
port, wraddress
port, wren
port, and byteena
port are synchron‐ ized by the write clock.
• Input/Output—Connect your input clock to inclock
port.
All registered input ports are synchronized by the input clock.
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Signal
outclock rden_a rden_b byteena_a addressstall_a addressstall_b
Required
Yes
Optional
Optional
Optional
Optional
RAM: 2-Port IP Core Signals (True Dual-Port RAM) for MAX 10 Devices
5-9
Description
The following list describes which of your memory clock must be connected to the outclock port, and port synchronization in different clock modes:
• Single clock—Connect your single source clock to inclock port and outclock
port. All registered ports are synchron‐ ized by the same source clock.
• Read/Write—Connect your read clock to outclock
port. All registered ports related to read operation, such as rdaddress port, rdren
port, and q
port are synchronized by the read clock.
• Input/Output—Connect your output clock to outclock port. The registered q
port is synchronized by the output clock.
Read enable input for address_a
port. The rden_a
port is supported depending on your selected memory mode and memory block.
Read enable input for address_b
port. The rden_b
port is supported depending on your selected memory mode and memory block.
Byte enable input to mask the data_a
port so that only specific bytes, nibbles, or bits of the data are written. The byteena_a port is not supported in the following conditions:
• If the implement_in_les
parameter is set to
ON
.
• If the operation_mode
parameter is set to
ROM
.
Address clock enable input to hold the previous address of address_a
port for as long as the addressstall_a
port is high.
Address clock enable input to hold the previous address of address_b
port for as long as the addressstall_b
port is high.
Table 5-4: RAM:2-Port IP Core Output Signals (True Dual-Port RAM)
q_a
Signal Required
Yes
Description
•
•
•
Data output from Port A of the memory. The q_a
port is required if the operation_mode
parameter is set to any of the following values:
SINGLE_PORT
BIDIR_DUAL_PORT
ROM
The width of q_a
port must be equal to the width of data_a port.
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Signal Required
Yes
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Description
Data output from Port B of the memory. The q_b
port is required if you set the operation_mode
to the following values:
•
•
DUAL_PORT
BIDIR_DUAL_PORT
The width of q_b
port must be equal to the width of data_b port.
Table 5-5: RAM: 2-Port IP Core Parameters for MAX 10 Devices
This table lists the IP core parameters applicable to MAX 10 devices.
Option Legal Values
Parameter Settings: General
How will you be using the dual port RAM? • With one read port and one write port
• With two read/write ports
How do you want to specify the memory size?
• As a number of words
• As a number of bits
Parameter Settings: Widths/ Blk Type
How many <X>-bit words of memory?
—
Use different data widths on different ports On/Off
Description
Specifies how you use the dual port RAM.
Determines whether to specify the memory size in words or bits.
Specifies the number of <X>
-bit words.
Specifies whether to use different data widths on different ports.
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RAM: 2-Port IP Core Parameters for MAX 10 Devices
Read/Write Ports
Option
When you select With
one read port and one
write port, the following options are available:
• How wide should the ‘data_a’ input bus be?
• How wide should the ‘q’ output bus be?
When you select
With two read/
write ports, the following options are available:
• How wide should the ‘q_a’ output bus be?
• How wide should the ‘q_b’ output bus be?
What should the memory block type be?
Legal Values
1, 2, 3, 4, 5, 6, 7, 8, 9, 16, 18,
32, 36, 64, 72, 108, 128, 144,
256, and 288
• Auto
• M9K
• LCs
Description
Specifies the width of the input and output ports.
5-11
The How wide should the ‘q’
output bus be? and the How
wide should the ‘q_b’
output bus be? options are only available when you turn on the Use different data
widths on different ports
parameter.
Option How should the memory be implemented?
• Use default logic cell style
• Use Stratix M512 emulation logic cell style
Specifies the memory block type. The types of memory block that are available for selection depends on your target device.
The LCs value is only available under the following conditions:
• Turn on the With one
read port and one write
port option
• Turn off Use different
data widths on different
ports option.
Specifies the logic cell implementation options.
This option is enabled only when you choose LCs memory type.
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RAM: 2-Port IP Core Parameters for MAX 10 Devices
Option
Set the maximum block depth to
• Auto
• 128
• 256
• 512
• 1024
• 2048
• 4096
• 8192
Legal Values
Parameter Settings: Clks/Rd, Byte En
What clocking method would you like to use?
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Description
Specifies the maximum block depth in words.
When you select With one
read port and one write port, the following values are available:
• Single clock
• Dual clock: use separate
‘input’ and ‘output’ clocks
• Dual clock: use separate
‘read’ and ‘write’ clocks
When you select With two
read/write ports, the following options are available:
• Single clock
• Dual clock: use separate
‘input’ and ‘output’ clocks
• Dual clock: use separate clocks for A and B ports
Specifies the clocking method to use.
• Single clock—A single clock and a clock enable controls all registers of the memory block.
• Dual Clock: use separate
‘input’ and ‘output’ clocks
—An input and an output clock controls all registers related to the data input and output to/from the memory block including data, address, byte enables, read enables, and write enables.
• Dual clock: use separate
‘read’ and ‘write’ clocks—
A write clock controls the data-input, write-address, and write-enable registers while the read clock controls the data-output, read-address, and readenable registers.
• Dual clock: use separate clocks for A and B ports
—Clock A controls all registers on the port A side; clock B controls all registers on the port B side. Each port also supports independent clock enables for both port A and port B registers, respectively.
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Option
Create a ‘rden’ read enable signal
Create a ‘rden_a’ and ‘rden_b’ read enable signal
Byte Enable Ports Create byte enable for port A
Parameter Settings: Regs/Clkens/Aclrs
Which ports should be registered?
When you select With
one read port and one
write port, the following options are available:
• Write input ports
‘data_a’,
‘wraddress_a’, and
‘wren_a’
• Read input ports
'rdaddress' and
'rden'
• Read output port(s)
‘q_a’ and 'q_b'
When you select With
two read/write ports, the following options are available:
• Write input ports
‘data_a’,
‘wraddress_a’, and
‘wren_a’ write input ports
• Read output port(s)
‘q’_a and ‘q_b’
RAM: 2-Port IP Core Parameters for MAX 10 Devices
Legal Values
On/Off
On/Off
On/Off
Description
5-13
Available when you select
With one read port and one
write port option.
• Available when you select
With two read/write
ports option.
• Specifies whether to create a read enable signal for Port A and B.
Specifies whether to create a byte enable for Port A and B.
Turn on these options if you want to mask the input data so that only specific bytes, nibbles, or bits of data are written.
On/Off Specifies whether to register the read or write input and output ports.
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More Option
Option
When you select With
one read port and one
write port, the following options are available:
• ‘q_b’ port
When you select With
two read/write ports, the following options are available:
• ‘q_a’ port
• ‘q_b’ port
Create one clock enable signal for each clock signal.
Legal Values
On/Off
On/Off
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Description
The read and write input ports are turned on by default. You only need to specify whether to register the Q output ports.
Specifies whether to turn on the option to create one clock enable signal for each clock signal.
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More Option
Option
When you select With
one read port and one
write port, the following option is available:
• Clock enable options
• Clock enable options: Use clock enable for write input registers
• Address options
• Create an ‘wr_ addressstall’ input port.
• Create an ‘rd_ addressstall’ input port.
When you select With
two read /write ports, the following options are available:
• Clock enable options
• Use clock enable for port A input registers
• Use clock enable for port A output registers
• Address options
• Create an
‘addressstall_a’ input port.
• Create an
‘addressstall_b’ input port.
Create an ‘aclr’ asynchronous clear for the registered ports.
RAM: 2-Port IP Core Parameters for MAX 10 Devices
Legal Values
On/Off
Description
5-15
• Clock enable options—
Clock enable for port B input and output registers are turned on by default.
You only need to specify whether to use clock enable for port A input and output registers.
• Address options—
Specifies whether to create clock enables for address registers. You can create these ports to act as an extra active low clock enable input for the address registers.
On/Off Specifies whether to create an asynchronous clear port for the registered ports.
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RAM: 2-Port IP Core Parameters for MAX 10 Devices
More Option
Option
When you select With
one read port and one
write port, the following options are available:
• ‘rdaddress’ port
• ‘q_b’ port
When you select With
two read /write ports, the following options are available:
• ‘q_a’ port
• ‘q_b’ port
Legal Values
On/Off
Parameter Settings: Output 1
Mixed Port Read-
During-Write for
Single Input Clock
RAM
When you select With
one read port and one
write port, the following option is available:
• How should the q output behave when reading a memory location that is being written from the other port?
When you select With
two read /write ports, the following option is available:
• How should the q_a and q_b outputs behave when reading a memory location that is being written from the other port?
• Old memory contents appear
• I do not care (the outputs will be undefined)
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Description
Specifies whether the raddress
, q_a
, and q_b ports are cleared by the aclr port.
Specifies the output behavior when read-during-write occurs.
• Old memory contents
appear— The RAM outputs reflect the old data at that address before the write operation proceeds.
• I do not care—This option functions differently when you turn it on depending on the following memory block type you select:
• When you set the memory block type to
Auto, or M9K, the
RAM outputs ‘don't care’ or “unknown” values for readduring-write operation without analyzing the timing path.
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Option Legal Values Description
Do not analyze the timing between write and read operation. Metastability issues are prevented by never writing and reading at the same address at the same time.
On/Off This option is automatically turned on when you turn on the I do not care (The
outputs will be undefined)
option. This option enables the RAM to output ‘don’t care’ or 'unknown' values for read-during-write operation without analyzing the timing path.
Parameter Settings: Output 2 (This tab is only available when you select two read/write ports)
Port A Read-
During-Write
Option
What should the ‘q_a’ output be when reading from a memory location being written to?
Specifies the output behavior when read-during-write occurs.
Port B Read-
During-Write
Option
What should the
‘q_b’ output be when reading from a memory location being written to?
• New data
• Old Data
• New Data—New data is available on the rising edge of the same clock cycle on which it was written.
• Old Data—The RAM outputs reflect the old data at that address before the write operation proceeds.
Get x’s for write masked bytes instead of old data when byte enable is used
On/Off This option is automatically turned on when you select the New Data value. This option obtains ‘X’ on the masked byte.
Parameter Settings: Mem Init
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RAM: 2-Port IP Core Parameters for MAX 10 Devices
Option
Do you want to specify the initial content of the memory?
Legal Values
• No, leave it blank
• Yes, use this file for the memory content data
The initial content file should conform to which port's dimension?
• PORT_A
• PORT_B
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Description
Specifies the initial content of the memory.
• To initialize the memory to zero, select No, leave it
blank.
• To use a Memory Initiali‐ zation File (.mif) or a
Hexadecimal (Intelformat) File (.hex), select
Yes, use this file for the
memory content data.
Note: The configuration scheme of your device is Internal
Configuration. In order to use memory initiali‐ zation, you must select a single image configura‐ tion mode with memory initiali‐ zation, for example the
Single
Compressed
Image with
Memory Initiali‐ zation option. You can set the configuration mode on the
Configuration page of the
Device and Pin
Options dialog box.
Specifies which port's dimension that the initial content file should conform to.
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The ROM: 1-PORT IP core implements the single-port ROM memory mode.
Figure 6-1: ROM: 1-PORT IP Core Signals with the Single Clock Option Enabled
q[] address[] addressstall_a rden clock clken
©
2016 Intel Corporation. All rights reserved. Intel, the Intel logo, Altera, Arria, Cyclone, Enpirion, MAX, Megacore, NIOS, Quartus and Stratix words and logos are trademarks of Intel Corporation in the US and/or other countries. Other marks and brands may be claimed as the property of others. Intel warrants performance of its FPGA and semiconductor products to current specifications in accordance with Intel's standard warranty, but reserves the right to make changes to any products and services at any time without notice. Intel assumes no responsibility or liability arising out of the application or use of any information, product, or service described herein except as expressly agreed to in writing by Intel. Intel customers are advised to obtain the latest version of device specifications before relying on any published information and before placing orders for products or services.
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ROM: 1-PORT IP Core Signals For MAX 10 Devices
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Figure 6-2: ROM: 1-PORT IP Core Signals with the Dual Clock: Use Separate 'Input' and 'Output' Clocks
Option Enabled
q[] address[] addressstall_a rden inclock inclocken outclock outclocken
Table 6-1: ROM: 1-PORT IP Core Input Signals
address
Signal
addressstall_a
Required
Yes
Optional rden
Optional
Description
Address input to the memory.
Address clock enable input to hold the previous address of address_a
port for as long as the addressstall_a port is high.
Read enable input for rdaddress
port. The rden
port is supported when the use_eab
parameter is set to
OFF
.
Instantiate the IP if you want to use read enable feature with other memory blocks.
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clock
Signal
clken inclock inclocken outclock
ROM: 1-PORT IP Core References
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Required
Yes
Optional
Yes
Optional
Yes
ROM: 1-PORT IP Core Signals For MAX 10 Devices
6-3
Description
The following list describes which of your memory clock must be connected to the clock
port, and port synchronization in different clock modes:
• Single clock—Connect your single source clock to clock
port. All registered ports are synchronized by the same source clock.
• Read/Write—Connect your write clock to clock port. All registered ports related to write operation, such as data_a
port, address_a
port, wren_a
port, and byteena_a
port are synchronized by the write clock.
• Input/Output—Connect your input clock to clock port. All registered input ports are synchronized by the input clock.
• Independent clock—Connect your port A clock to clock
port. All registered input and output ports of port A are synchronized by the port A clock.
Clock enable input for clock
port.
The following list describes which of your memory clock must be connected to the inclock
port, and port synchronization in different clock modes:
• Single clock—Connect your single source clock to inclock
port and outclock
port. All registered ports are synchronized by the same source clock.
• Read/Write—Connect your write clock to inclock port. All registered ports related to write operation, such as data
port, wraddress
port, wren
port, and byteena
port are synchronized by the write clock.
• Input/Output—Connect your input clock to inclock
port. All registered input ports are synchronized by the input clock.
Clock enable input for inclock
port.
The following list describes which of your memory clock must be connected to the outclock
port, and port synchronization in different clock modes:
• Single clock—Connect your single source clock to inclock
port and outclock
port. All registered ports are synchronized by the same source clock.
• Read/Write—Connect your read clock to outclock port. All registered ports related to read operation, such as rdaddress
port, rdren
port, and q
port are synchronized by the read clock.
• Input/Output—Connect your output clock to outclock
port. The registered q
port is synchronized by the output clock.
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ROM: 1-PORT IP Core Parameters for MAX 10 Devices
Signal
outclocken
Required
Optional
Description
Clock enable input for outclock
port.
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Table 6-2: ROM: 1-PORT IP Core Output Signals
q
Signal Required
Yes
Description
Data output from the memory. The q
port is required, and must be equal to the width data port.
Table 6-3: ROM: 1-Port IP Core Parameters for MAX 10 Devices
This table lists the IP core parameters applicable to MAX 10 devices.
Option Legal Values
Parameter Settings: General
How wide should the 'q' output bus be?
How many <X>-bit words of memory?
1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11,
12, 13, 14, 15, 16, 17, 18, 19,
20, 21, 22, 23, 24, 25, 26, 27,
28, 29, 30, 31, 32, 36, 40, 48,
64, 72, 108, 128, 144, and 256.
32, 64, 128, 256, 512, 1024,
2048, 4096, 8192, 16384,
32768, and 65536.
What should the memory block type be?
• Auto
• M9K
Set the maximum block depth to
Description
Specifies the width of the 'q' output bus in bits.
Specifies the number of <X>
-bit words.
Specifies the memory block type. The types of memory block that are available for selection depends on your target device.
Specifies the maximum block depth in words.
• Auto
• 32
• 64
• 128
• 256
• 512
• 1024
• 2048
• 4096
• 8192
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Option
What clocking method would you like to use?
ROM: 1-PORT IP Core Parameters for MAX 10 Devices
Legal Values
• Single clock
• Dual clock: use separate
‘input’ and ‘output’ clocks
6-5
Description
Specifies the clocking method to use.
• Single clock—A single clock and a clock enable controls all registers of the memory block.
• Dual clock: use separate
‘input’ and ‘output’ clocks
—An input and an output clock controls all registers related to the data input and output to/from the memory block including data, address, byte enables, read enables, and write enables.
Parameter Settings: Regs/Clkens/Aclrs
Which ports should be registered?
• 'address' input port
• 'q' output port
Create one clock enable signal for each clock signal.
On/Off
On/Off
More Options • Clock enable options
• Use clock enable for port A input registers
• Use clock enable for port A output registers
• Address options
• Create an 'address‐ stall_a' input port
Create an ‘aclr’ asynchronous clear for the registered ports.
More Options • 'address' port
• 'q' port
On/Off
On/Off
On/Off
Specifies whether to register the read or write input and output ports.
Specifies whether to turn on the option to create one clock enable signal for each clock signal.
• Clock enable options—
Clock enable for port B input and output registers are turned on by default.
You only need to specify whether to use clock enable for port A input and output registers.
• Address options—
Specifies whether to create clock enables for address registers. You can create these ports to act as an extra active low clock enable input for the address registers.
Specifies whether to create an asynchronous clear port for the registered ports.
Specifies whether the address
and q
ports are cleared by the aclr
port.
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Option
Create a 'rden' read enable signal
Parameter Settings: Mem Init
Do you want to specify the initial content of the memory?
Legal Values
On/Off
Yes, use this file for the memory content data.
Allow In-System Memory Content Editor to capture and update content independ‐ ently of the system clock
The 'Instance ID' of this RAM is
On/Off
—
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Description
Specifies whether to create a rden
read enable signal.
Specifies the initial content of the memory. In ROM mode you must specify a
Memory Initialization File
(.mif) or a Hexadecimal
(Intel-format) File (.hex).
The configuration scheme of your device is Internal
Configuration. In order to use memory initialization, you must select a single image configuration mode with memory initialization, for example the Single
Compressed Image with
Memory Initialization option. You can set the configuration mode on the
Configuration page of the
Device and Pin Options
dialog box.
Specifies whether to allow
In-System Memory Content
Editor to capture and update content independently of the system clock.
Specifies the RAM ID.
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This IP core implements the dual-port ROM memory mode. The dual-port ROM has almost similar functional ports as single-port ROM. The difference is dual-port ROM has an additional address port for read operation.
Figure 7-1: ROM: 2-PORT IP Core Signals with the Single Clock Option Enabled
7
q_a[] q_b[] address_a[] rden_a address_b[] rden_b addressstall_a addressstall_b clock enable
©
2016 Intel Corporation. All rights reserved. Intel, the Intel logo, Altera, Arria, Cyclone, Enpirion, MAX, Megacore, NIOS, Quartus and Stratix words and logos are trademarks of Intel Corporation in the US and/or other countries. Other marks and brands may be claimed as the property of others. Intel warrants performance of its FPGA and semiconductor products to current specifications in accordance with Intel's standard warranty, but reserves the right to make changes to any products and services at any time without notice. Intel assumes no responsibility or liability arising out of the application or use of any information, product, or service described herein except as expressly agreed to in writing by Intel. Intel customers are advised to obtain the latest version of device specifications before relying on any published information and before placing orders for products or services.
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Registered
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ROM: 2-PORT IP Core References
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Figure 7-2: ROM: 2-PORT IP Core Signals with the Dual Clock: Use Separate 'Input' and 'Output' Clocks
Option Enabled
q_a[] q_b[] address_a[] rden_a address_b[] rden_b addressstall_a addressstall_b inclock inclocken outclock outclocken
Figure 7-3: ROM: 2-PORT IP Core Signals with the Dual Clock: Use Separate Clocks for A and B Ports Option
Enabled
q_a[] q_b[] address_a[] rden_a address_b[] rden_b addressstall_a addressstall_b clock_a enable_a clock_b enable_b
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7-3
Table 7-1: ROM: 2-PORT IP Core Input Signals
address_a rden_a
Signal
address_b
Required Description
Yes Address input to port A of the memory. The address_a
port is required for all operation modes.
Optional Read enable input for address_a
port. The rden_a
port is supported depending on your selected memory mode and memory block.
Optional Address input to port B of the memory. The address_b
port is required if the operation_mode
parameter is set to the following values:
•
•
DUAL_PORT
BIDIR_DUAL_PORT rden_b clock addressstall_a addressstall_b
Optional Read enable input for address_b
port. The rden_b
port is supported depending on your selected memory mode and memory block.
Yes The following list describes which of your memory clock must be connected to the clock
port, and port synchronization in different clock modes:
• Single clock—Connect your single source clock to clock
port.
All registered ports are synchronized by the same source clock.
• Read/Write—Connect your write clock to clock
port. All registered ports related to write operation, such as data_a
port, address_a
port, wren_a
port, and byteena_a
port are synchronized by the write clock.
• Input/Output—Connect your input clock to clock
port. All registered input ports are synchronized by the input clock.
• Independent clock—Connect your port A clock to clock
port.
All registered input and output ports of port A are synchronized by the port A clock.
Optional Address clock enable input to hold the previous address of address_a
port for as long as the addressstall_a
port is high.
Optional Address clock enable input to hold the previous address of address_b
port for as long as the addressstall_b
port is high.
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aclr
ROM: 2-PORT IP Core Signals for MAX 10 Devices
Signal
inclock outclock inclocken outclocken
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Required
Yes
Yes
Description
The following list describes which of your memory clock must be connected to the inclock
port, and port synchronization in different clock modes:
• Single clock—Connect your single source clock to inclock
port and outclock
port. All registered ports are synchronized by the same source clock.
• Read/Write—Connect your write clock to inclock
port. The write clock synchronizes all registered ports related to write operation, such as data
port, wraddress
port, wren
port, and byteena
port.
• Input/Output—Connect your input clock to inclock
port. The input clock synchronizes all registered input ports.
The following list describes which of your memory clock must be connected to the outclock
port, and port synchronization in different clock modes:
• Single clock—Connect your single source clock to inclock port and outclock
port. All registered ports are synchronized by the same source clock.
• Read/Write—Connect your read clock to outclock
port. The read clock synchronizes all registered ports related to read operation, such as rdaddress
port, rdren
port, and q
port.
• Input/Output—Connect your output clock to outclock
port.
The output clock synchronizes the registered q
port.
Optional Clock enable input for inclock
port.
Optional Clock enable input for outclock
port.
Optional Asynchronously clear the registered input and output ports. The asynchronous clear effect on the registered ports can be controlled through their corresponding asynchronous clear parameter, such as indata_aclr
and wraddress_aclr
.
Table 7-2: ROM: 2-PORT IP Core Output Signals
q_a
Signal Required
Yes
Description
•
•
•
Data output from port A of the memory. The q_a
port is required if you set the operation_mode
parameter to any of the following values:
SINGLE_PORT
BIDIR_DUAL_PORT
ROM
The width of the q_a
port must be equal to the width of the data_a port.
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Signal
q_b
Required
Yes
ROM:2-Port IP Core Parameters For MAX 10 Devices
7-5
Description
Data output from port B of the memory. The q_b
port is required if you set the operation_mode
parameter to the following values:
•
•
DUAL_PORT
BIDIR_DUAL_PORT
The width of q_b
port must be equal to the width of data_b
port.
Table 7-3: ROM:2-Port IP Core Parameters for MAX 10 Devices
This table lists the IP core parameters applicable to MAX 10 devices.
Option Legal Values
Parameter Settings: Widths/Blk Type
How do you want to specify the memory size?
• As a number of words
• As a number of bits
Description
Determines whether to specify the memory size in words or bits.
How many <X>-bit words of memory?
—
Use different data widths on different ports On/Off
Read Ports
How wide should the
‘q_a’ output bus be?
How wide should the ‘q_b’ output bus be?
What should the memory block type be?
Set the maximum block depth to
1, 2, 3, 4, 5, 6, 7, 8, 9,
16, 18, 32, 36, 64, 72,
108, 128, 144, 256, and
288
Auto, M9K
Auto, 128, 256, 512,
1024, 2048, 4096, 8192
Specifies the number of <X>-bit words.
Specifies whether to use different data widths on different ports.
Specifies the width of the input and output ports.
The How wide should the ‘q_b’
output bus be? option is only available when you turn on the Use
different data widths on different
ports parameter.
Specifies the memory block type.
The types of memory block that are available for selection depends on your target device.
Specifies the maximum block depth in words.
Parameter Settings: Clks/Rd, Byte En
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ROM:2-Port IP Core Parameters For MAX 10 Devices
Option
What clocking method would you like to use?
Legal Values
• Single clock
• Dual clock: use separate ‘input’ and
‘output’ clocks
• Dual clock: use separate clocks for
A and B ports
On/Off
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Description
Specifies the clocking method to use.
• Single clock—A single clock and a clock enable controls all registers of the memory block.
• Dual Clock: use separate ‘input’
and ‘output’ clocks—An input and an output clock controls all registers related to the data input and output to/from the memory block including data, address, byte enables, read enables, and write enables.
• Dual clock: use separate clocks
for A and B ports—Clock A controls all registers on the port
A side; clock B controls all registers on the port B side. Each port also supports independent clock enables for both port A and port B registers, respectively.
Specifies whether to create read enable signals.
Create a ‘rden_a’ and 'rden_b' read enable signal
Parameter Settings: Regs/Clkens/Aclrs
Which ports should be registered?
• Write input ports
• Read output port(s)
More Options
• Input ports
• 'address_a' port
• 'address_b' port
• Q output ports
• ‘q_a’ port
• 'q_b' port
Create one clock enable signal for each clock signal.
On/Off
On/Off
On/Off
Specifies whether to register the read or write input and output ports.
The read and write input ports are turned on by default. You only need to specify whether to register the Q output ports.
Specifies whether to turn on the option to create one clock enable signal for each clock signal.
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Option
More Options
•
• Clock enable options
• Use clock enable for port A input registers
• Use clock enable for port A output registers
• Address options
• Create an
‘addressstall_a’ input port.
• Create an
‘addressstall_b’ input port.
Create an ‘aclr’ asynchronous clear for the registered ports.
Legal Values
On/Off
On/Off
More Options
• ‘q_a’ port
• ‘q_b’ port
Parameter Settings: Mem Init
On/Off
Description
• Clock enable options—Clock enable for port B input and output registers are turned on by default. You only need to specify whether to use clock enable for port A input and output registers.
• Address options—Specifies whether to create clock enables for address registers. You can create these ports to act as an extra active low clock enable input for the address registers.
Specifies whether to create an asynchronous clear port for the registered ports.
Specifies whether the ‘q_a’, and ‘q_b’ ports are cleared by the aclr port.
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ROM:2-Port IP Core Parameters For MAX 10 Devices
Option
Do you want to specify the initial content of the memory?
The initial content file should conform to which port's dimension?
Legal Values
Yes, use this file for the memory content data
• PORT_A
• PORT_B
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Description
Specifies the initial content of the memory.
• To initialize the memory to zero, select No, leave it blank.
• To use a Memory Initialization
File (.mif) or a Hexadecimal
(Intel-format) File (.hex), select
Yes, use this file for the memory
content data.
Note: The configuration scheme of your device is Internal
Configuration. In order to use memory initializa‐ tion, you must select a single image configura‐ tion mode with memory initialization, for example the Single Compressed
Image with Memory
Initialization option. You can set the configuration mode on the Configura‐ tion page of the Device
and Pin Options dialog box.
Specifies which port's dimension that the initial content file should conform to.
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The Shift Register (RAM-based) IP core contains additional features not found in a conventional shift register. You can use the memory blocks as a shift-register block to save logic cells and routing resources.
You can cascade memory blocks to implement larger shift registers.
Figure 8-1: Shift Register (RAM-based) IP Core Signals
8
shift_in[] clock clken aclr shiftout[] taps[]
Table 8-1: Shift Register (RAM-based) IP Core Input Signals
aclr
Signal
shiftin[] clock clken
Required
Yes
Yes
No
No
Description
Data input to the shifter. Input port
WIDTH
bits wide.
Positive-edge triggered clock.
Clock enable for the clock
port. clken
defaults to VCC.
Asynchronously clears the contents of the shift register chain. The shiftout outputs are cleared immediately upon the assertion of the aclr
signal.
Table 8-2: Shift Register (RAM-based) IP Core Output Signals
Signal
shiftout[]
Required
Yes
Description
Output from the end of the shift register. Output port
WIDTH
bits wide.
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Shift Register (RAM-based) IP Core Parameters for MAX 10 Devices
Signal
taps[]
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Required
Yes
Description
Output from the regularly spaced taps along the shift register. Output port
WIDTH * NUMBER_OF_TAPS
wide. This port is an aggregate of all the regularly spaced taps (each
WIDTH
bits) along the shift register.
Table 8-3: Shift Register (RAM-based) IP Core Parameters for MAX 10 Devices
This table lists the IP core parameters applicable to MAX 10 devices.
Option Values
How wide should the "shiftin" input and the "shiftout" output buses be?
How many taps would you like?
1, 2, 3, 4, 5, 6, 7, 8, 12, 16, 24,
32, 48, 64, 96, 128, 192, and
256.
1, 2, 3, 4, 5, 6, 7, 8, 12, 16, 24,
32, 48, 64, 96, and 128.
Description
Specifies the width of the input pattern.
Create groups for each tap output
How wide should the distance between taps be?
Create a clock enable port
Create an asynchronous clear port
What should the RAM block type be?
On/Off
3, 4, 5, 6, 7, 8, 16, 32, 64, and
128
On/Off
On/Off
Auto, M9K
Specifies the number of regularly spaced taps along the shift register.
Creates groups for each tap output.
Specifies the distance between the regularly spaced taps in clock cycles. This number translates to the number of RAM words that will be used. The value must be at least 3.
Creates the clken
port
Creates the aclr
port.
Specifies the RAM block type.
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The FIFO IP core implements the FIFO mode, enabling you to use the memory blocks as FIFO buffers.
• Use the FIFO IP core in single clock FIFO (SCFIFO) and dual clock FIFO (DCFIFO) modes to implement single- and dual-clock FIFO buffers in your design.
• Dual clock FIFO buffers are useful when transferring data from one clock domain to another clock domain.
• The M9K memory blocks do not support simultaneous read and write from an empty FIFO buffer.
Figure 9-1: FIFO IP Core: SCFIFO Mode Signals
9
data[] wrreq rdreq clock sclr aclr q[] full almost_full empty almost_empty usedw[]
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2016 Intel Corporation. All rights reserved. Intel, the Intel logo, Altera, Arria, Cyclone, Enpirion, MAX, Megacore, NIOS, Quartus and Stratix words and logos are trademarks of Intel Corporation in the US and/or other countries. Other marks and brands may be claimed as the property of others. Intel warrants performance of its FPGA and semiconductor products to current specifications in accordance with Intel's standard warranty, but reserves the right to make changes to any products and services at any time without notice. Intel assumes no responsibility or liability arising out of the application or use of any information, product, or service described herein except as expressly agreed to in writing by Intel. Intel customers are advised to obtain the latest version of device specifications before relying on any published information and before placing orders for products or services.
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FIFO IP Core Signals for MAX 10 Devices
Figure 9-2: FIFO IP Core: DCFIFO Mode Signals
data[] wrreq wrclk rdreq rdclk aclr wrfull wrempty wrusedw[] q[] rdfull rdempty rdusedw[]
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Table 9-1: FIFO IP Core Input Signals
clock wrclk
Signal Required
Yes
Yes rdclk data
Yes
Yes
Description
•
•
•
•
•
Positive-edge-triggered clock.
Positive-edge-triggered clock. Synchronizes the following ports: data wrreq wrfull wrempty wrusedw
•
•
•
•
•
Positive-edge-triggered clock. Synchronizes the following ports: q rdreq rdfull rdempty rdusedw
Holds the data to be written in the FIFO IP core when the wrreq signal is asserted.
If you manually instantiate the FIFO IP core, ensure that the port width is equal to the How wide should the FIFO be? parameter.
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wrreq
Signal
rdreq sclr aclr
Required
Yes
Yes
No
No
FIFO IP Core Signals for MAX 10 Devices
9-3
Description
Assert this signal to request for a write operation.
Ensure that the following conditions are met:
• Do not assert the wrreq
signal when the full
(for the FIFO IP core in SCFIFO mode) or wrfull
(for the FIFO IP core in
DCFIFO mode) port is high. Enable the overflow protection circuitry or turn on the Disable overflow checking. Writing to a
full FIFO will corrupt contents parameter so that the FIFO IP core can automatically disable the wrreq
signal when it is full.
• The wrreq
signal must meet the functional timing requirement based on the full
or wrfull
signal.
• Do not assert the wrreq
signal during the deassertion of the aclr signal. Violating this requirement creates a race condition between the falling edge of the aclr
signal and the rising edge of the write
clock if the wrreq
port is set to high.
Assert this signal to request for a read operation. The rdreq
signal acts differently in normal synchronous FIFO mode and show-ahead mode synchronous FIFO modes.
Ensure that the following conditions are met:
• Do not assert the rdreq
signal when the empty
(for the FIFO IP core in SCFIFO mode) or rdempty
(for the FIFO IP core in
DCFIFO mode) port is high. Enable the underflow protection circuitry or turn on the Disable underflow checking. Reading
from an empty FIFO will corrupt contents parameter so that the
FIFO IP core can automatically disable the rdreq
signal when it is empty.
The rdreq
signal must meet the functional timing requirement based on the empty
or rdempty
signal.
Assert this signal to clear all the output status ports, but the effect on the q
output may vary for different FIFO configurations. There are no minimum number of clock cycles for aclr
signals that must remain active.
Table 9-2: FIFO IP Core Output Signals
Signal Required
q
Description
Shows the data read from the read request operation. In SCFIFO and
DCFIFO modes, the width of the q
port must be equal to the width of the data
port. If you manually instantiate the IPs, ensure that the port width is equal to the How wide should the FIFO be? parameter.
In DCFIFO_MIXED_WIDTHS mode, the width of the q
port can be different from the width of the data
port. If you manually instantiate the IP, ensure that the width of the q
port is equal to the Use a
different output width parameter. The IP supports a wide write port with a narrow read port, and vice versa. However, the width ratio is restricted by the type of RAM block, and in general, are in the power of 2.
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full
FIFO IP Core Parameters for MAX 10 Devices
wrfull rdfull empty wrempty rdempty almost_full almost_empty usedw
Signal
wrusedw rdusedw
Required
No
No
No
No
No
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Description
When asserted, the FIFO IP core is considered full. Do not perform write request operation when the FIFO IP core is full. In general, the signal is a delayed version of the wrfull
signal. However, the rdfull signal functions as a combinational output instead of a derived version of the wrfull
signal. Therefore, you must always refer to the wrfull
port to ensure whether or not a valid write request operation can be performed, regardless of the target device.
When asserted, the FIFO IP core is considered empty. Do not perform read request operation when the FIFO IP core is empty. In general, the wrempty
signal is a delayed version of the rdempty
signal.
However, the wrempty
signal functions as a combinational output instead of a derived version of the rdempty
signal. Therefore, you must always refer to the rdempty
port to ensure whether or not a valid read request operation can be performed, regardless of the target device.
Asserted when the usedw
signal is greater than or equal to the
Almost full parameter. It is used as an early indication of the full signal.
Asserted when the usedw
signal is less than the Almost empty parameter. It is used as an early indication of the empty
signal.
Show the number of words stored in the FIFO. Ensure that the port width is equal to the usedw[] parameter if you manually instantiate the FIFO IP core in SCFIFO or DCFIFO modes. In DCFIFO_
MIXED_WIDTH mode, the width of the wrusedw
and rdusedw
ports must be equal to the usedw[] and Use a different output width parameters respectively.
Table 9-3: FIFO IP Core Parameters for MAX 10 Devices
This table lists the IP core parameters applicable to MAX 10 devices.
Parameter HDL Parameter Description
How wide should the
FIFO be?
Use a different output width
(1) lpm_width lpm_width_r
Specifies the width of the data
and q
ports for the FIFO IP core in SCFIFO mode and DCFIFO mode. For the FIFO IP core in DCFIFO_MIXED_WIDTHS mode, this parameter specifies only the width of the data
port.
Specifies the width of the q
port for the FIFO IP core in
DCFIFO_MIXED_WIDTHS mode.
(1) Applicable in DCFIFO_MIXED_WIDTHS mode only.
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Parameter
Usedw[]
How deep should the
FIFO be?
Which kind of read access do you want with the rdreq signal?
FIFO IP Core Parameters for MAX 10 Devices
9-5
HDL Parameter
lpm_widthu lpm_numwords lpm_showahead lpm_type
Description
Specifies the width of the usedw
port for the FIFO IP core in SCFIFO mode, or the width of the rdusedw
and wrusedw
ports for the FIFO IP core in DCFIFO mode. For the FIFO IP core in DCFIFO_MIXED_WIDTHS mode, it only represents the width of the wrusedw
port.
Specifies the depths of the FIFO you require. The value must be at least 4. The value assigned must comply with the
2
LPM_WIDTHU
equation.
Specifies whether the FIFO is in normal synchronous FIFO mode or show-ahead mode synchronous FIFO mode.
Fornormal synchronous FIFO mode, the FIFO IP core treats the rdreq
port as a normal read request that only performs read operation when the port is asserted. For show-ahead mode synchronous FIFO mode, the FIFO IP core treats the rdreq
port as a read-acknowledge that automatically outputs the first word of valid data in the
FIFO IP core (when the empty
or rdempty
port is low) without asserting the rdreq
signal. Asserting the rdreq signal causes the FIFO IP core to output the next data word, if available. If you turn on this parameter, you may reduce performance.
Identifies the library of parameterized modules (LPM) entity name. The values are SCFIFO and DCFIFO.
Do you want a common clock for reading and writing the FIFO?
Disable overflow checking. Writing to a full FIFO will corrupt contents
Disable underflow checking. Reading from an empty FIFO will corrupt contents.
Add an extra MSB to usedw
(2) overflow_ checking underflow_ checking add_usedw_msb_ bit
Specifies whether or not to enable the protection circuitry for overflow checking that disables the wrreq
port when the FIFO IP core is full. This parameter is enabled by default.
Specifies whether or not to enable the protection circuitry for underflow checking that disables the rdreq
port when the FIFO IP core is empty. This parameter is enabled by default. Note that reading from an empty SCFIFO mode gives unpredictable results.
Increases the width of the rdusedw
and wrusedw
ports by one bit. By increasing the width, it prevents the FIFO IP core from rolling over to zero when it is full. This parameter is disabled by default.
(2) Applicable in DCFIFO mode only.
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FIFO IP Core Parameters for MAX 10 Devices
Parameter
How many sync stages?
(2)
HDL Parameter
rdsync_ delaypipe
How many sync stages?
if the device contains memory blocks.
Add circuit to synchronize ‘aclr’ input with ‘wrclk’
(2)
Add circuit to synchronize ‘aclr’ input with ‘rdclk’
(2)
Implement FIFO storage with logic cells only, even
wrsync_ delaypipe use_eab write_aclr_ synch read_aclr_ synch
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Description
Specifies the number of synchronization stages in the cross clock domain. The value of the rdsync_delaypipe parameter relates the synchronization stages from the write control logic to the read control logic; the wrsync_ delaypipe parameter relates the synchronization stages from the read control logic to the write control logic. Use these parameters to set the number of synchronization stages if the clocks are not synchronized, and set the clocks_are_synchronized parameter to FALSE. The actual synchronization stage implemented relates variously to the parameter value assigned, depends on the target device.
Specifies the number of synchronization stages in the cross clock domain. The value of the rdsync_delaypipe parameter relates the synchronization stages from the write control logic to the read control logic; the wrsync_ delaypipe parameter relates the synchronization stages from the read control logic to the write control logic. Use these parameters to set the number of synchronization stages if the clocks are not synchronized, and set the clocks_are_synchronized parameter to FALSE. The actual synchronization stage implemented relates variously to the parameter value assigned, depends on the target device.
Specifies whether or not the FIFO IP core is constructed using RAM blocks. This parameter is disabled by default. If you turn off this parameter, the FIFO IP core is implemented in logic elements, regardless of the memory block type assigned to the What should the memory block
type be parameter.
Specifies whether or not to add a circuit that causes the aclr
port to be internally synchronized by the wrclk
clock.
Adding the circuit prevents the race condition between the wrreq
and aclr
ports that could corrupt the FIFO IP core.
This parameter is disabled by default.
Specifies whether or not to add a circuit that causes the aclr
port to be internally synchronized by the rdclk
clock.
Adding the circuit prevents the race condition between the rdreq
and aclr
ports that could corrupt the FIFO IP core.
This parameter is disabled by default.
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9-7
Parameter
Which type of optimiza‐ tion do you want?
(2)
What should the memory block type be
HDL Parameter
clocks_are_ synchronized ram_block_type add_ram_ output_ register
Description
Specifies whether or not the write and read clocks are synchronized, which in turn determines the number of internal synchronization stages added for stable operation of the FIFO. The values are TRUE and FALSE. If omitted, the default value is FALSE. You must only set the parameter to TRUE if the write clock and the read clock are always synchronized and they are multiples of each other. Otherwise, set this to FALSE to avoid metastability problems. If the clocks are not synchronized, set the parameter to FALSE, and use the rdsync_delaypipe and wrsync_delaypipe parameters to determine the number of synchronization stages required.
Specifies the target device’s memory block to be used. To get the proper implementation based on the RAM configu‐ ration that you set, allow the Quartus Prime software to automatically choose the memory type by ignoring this parameter and turn on the Implement FIFO storage with
logic cells only, even if the device contains memory
blocks. parameter. This gives the Compiler the flexibility to place the memory function in any available memory resource based on the FIFO depth required.
Specifies whether to register the q output. The values are
Yes (best speed) and No (smallest area). The default value is No (smallest area).
Would you like to register the output to maximize the perform‐ ance but use more area?
(3)
Becomes true when usedw[] is greater than or equal to:
(3)
Almost full
(3)
Almost empty
(3)
Becomes true when usedw[] is less than:
(3)
Currently selected device family
almost_full_ value almost_empty_ value intended_ device_family
Sets the threshold value for the almost_full port. When the number of words stored in the FIFO IP core is greater than or equal to this value, the almost_full port is asserted.
Sets the threshold value for the almost_empty port. When the number of words stored in the FIFO IP core is less than this value, the almost_empty port is asserted.
Specifies the intended device that matches the device set in your Quartus Prime project. Use this parameter only for functional simulation.
(3) Applicable in SCFIFO mode only.
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The ALTMEMMULT IP core creates only memory-based multipliers using on-chip memory blocks found in M9K memory blocks.
Figure 10-1: ALTMEMMULT IP Core Signals
data_in[] coeff_in[] sload_coeff sclr clock result[] load_done
Table 10-1: ALTMEMMULT IP Core Input Signals
Signal
clock coeff_in[]
Required
Yes
No data_in[] sclr sel[] sload_coeff
Yes
No
No
No
Description
Clock input to the multiplier.
Coefficient input port for the multiplier. The size of the input port depends on the
WIDTH_C
parameter value.
Data input port to the multiplier. The size of the input port depends on the
WIDTH_D
parameter value.
Synchronous clear input. If unused, the default value is active high.
Fixed coefficient selection. The size of the input port depends on the
WIDTH_S
parameter value.
Synchronous load coefficient input port. Replaces the current selected coefficient value with the value specified in the coeff_in
input.
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2016 Intel Corporation. All rights reserved. Intel, the Intel logo, Altera, Arria, Cyclone, Enpirion, MAX, Megacore, NIOS, Quartus and Stratix words and logos are trademarks of Intel Corporation in the US and/or other countries. Other marks and brands may be claimed as the property of others. Intel warrants performance of its FPGA and semiconductor products to current specifications in accordance with Intel's standard warranty, but reserves the right to make changes to any products and services at any time without notice. Intel assumes no responsibility or liability arising out of the application or use of any information, product, or service described herein except as expressly agreed to in writing by Intel. Intel customers are advised to obtain the latest version of device specifications before relying on any published information and before placing orders for products or services.
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ALTMEMMULT IP Core Parameters for MAX 10 Devices
Signal
sload_data
Required
No
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Description
Synchronous load data input port. Signal that specifies new multiplication operation and cancels any existing multiplication operation. If the
MAX_
CLOCK_CYCLES_PER_RESULT
parameter has a value of
1
, the sload_data input port is ignored.
Table 10-2: ALTMEMMULT IP Core Output Signals
Signal
result[]
Required
Yes result_valid load_done
Yes
No
Description
Multiplier output port. The size of the input port depends on the
WIDTH_R parameter value.
Indicates when the output is the valid result of a complete multiplication. If the
MAX_CLOCK_CYCLES_PER_RESULT
parameter has a value of
1
, the result_valid
output port is not used.
Indicates when the new coefficient has finished loading. The load_don e signal asserts when a new coefficient has finished loading. Unless the load_ done
signal is high, no other coefficient value can be loaded into the memory.
Table 10-3: ALTMEMMULT IP Core Parameters for MAX 10 Devices
This table lists the IP core parameters applicable to MAX 10 devices.
Option Values Description
Specifies the width of the data_in
port.
How wide should the 'data_ in' input bus be?
What is the representation of
'data_in'?
How wide should the coefficient be?
What is the representation of the coefficient?
What is the value of the initial coefficient?
Create ports to allow loading coefficients
Create a synchronous clear input
What should the RAM block type be?
2, 3, 4, 5, 6, 7, 8, 16,
24, and 32
SIGNED,
UNSIGNED
2, 3, 4, 5, 6, 7, 8, 16,
24
SIGNED,
UNSIGNED
0, 1, 2, 3, and 4
On/Off
On/Off
Auto, M9K
Specifies whether the or unsigned.
Specifies whether the coeff_in
input port and the pre-loaded coefficients are signed or unsigned.
Specifies value of the first fixed coefficient.
Creates the
Creates the coeff_in sclr
port.
data_in
Specifies the width of the
and
input port is signed coeff_in
port.
sload_coeff
Specifies the RAM block type.
port.
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Date
October 2016
November 2015
May 2015
September 2014
Version Changes
2016.10.31 • Added note stating that the memory initialization feature is supported in MAX 10 Analog and Flash feature options only.
2015.11.02 • Revised the title for the tables in the Embedded Memory Configu‐ ration topic.
• Added a link to the MAX 10 FPGA Device Overview in the
Consider Power-Up State and Memory Initialization topic.
• Changes instances of Quartus II to Quartus Prime.
2015.05.04 • Updated 'Yes, use this file for the memory content data' parameter note for RAM:1-Port, RAM:2-Port, ROM:1-Port, and ROM:2-Port.
• Added information about the internal configuration mode that supports memory initialization in 'Consider Power-Up State and
Memory Initialization'
2014.09.22 Initial release.
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TOC-2
Contents
Embedded Multipliers Features and Architecture............................................. 2-1
Embedded Multipliers Implementation Guides.................................................3-1
LPM_MULT (Multiplier) IP Core References....................................................4-1
ALTMULT_ACCUM (Multiply-Accumulate) IP Core References....................5-1
ALTMULT_ADD (Multiply-Adder) IP Core References...................................6-1
ALTMULT_COMPLEX (Complex Multiplier) IP Core References..................7-1
Additional Information for MAX 10 Embedded Multipliers User Guide........A-1
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The embedded multiplier is configured as either one 18 x 18 multiplier or two 9 x 9 multipliers. For multiplications greater than 18 x 18, the Quartus
®
Prime software cascades multiple embedded multiplier blocks together. There are no restrictions on the data width of the multiplier but the greater the data width, the slower the multiplication process.
Figure 1-1: Embedded Multipliers Arranged in Columns with Adjacent LABS
Embedded
Multiplier
Column
1
1 LAB
Row
Embedded
Multiplier
Table 1-1: Number of Embedded Multipliers in the MAX 10 Devices
10M02
10M04
10M08
10M16
Device Embedded
Multipliers
16
20
24
45
9 x 9 Multipliers
(1)
32
40
48
90
18 x 18 Multipliers
(1)
16
20
24
45
(1)
These columns show the number of 9 x 9 or 18 x 18 multipliers for each device. The total number of multipliers for each device is not the sum of all the multipliers.
©
2015 Altera Corporation. All rights reserved. ALTERA, ARRIA, CYCLONE, ENPIRION, MAX, MEGACORE, NIOS, QUARTUS and STRATIX words and logos are trademarks of Altera Corporation and registered in the U.S. Patent and Trademark Office and in other countries. All other words and logos identified as trademarks or service marks are the property of their respective holders as described at www.altera.com/common/legal.html
. Altera warrants performance of its semiconductor products to current specifications in accordance with Altera's standard warranty, but reserves the right to make changes to any products and services at any time without notice. Altera assumes no responsibility or liability arising out of the application or use of any information, product, or service described herein except as expressly agreed to in writing by Altera. Altera customers are advised to obtain the latest version of device specifications before relying on any published information and before placing orders for products or services.
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Embedded Multiplier Block Overview
10M25
10M40
10M50
Device Embedded
Multipliers
55
125
144
9 x 9 Multipliers
(1)
110
250
288
18 x 18 Multipliers
(1)
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55
125
144
You can implement soft multipliers by using the M9K memory blocks as look-up tables (LUTs). The
LUTs contain partial results from multiplying input data with coefficients implementing variable depth and width high-performance soft multipliers for low-cost, high-volume DSP applications. The availability of soft multipliers increases the number of available multipliers in the device.
Table 1-2: Number of Multipliers in the MAX 10 Devices
Device Total Multipliers
(3)
10M02
10M04
10M08
10M16
10M25
10M40
10M50
Embedded
Multipliers
16
20
24
45
55
125
144
Soft Multipliers
(16 x 16)
(2)
12
21
42
61
75
140
182
28
41
66
106
130
265
326
(1)
(2)
(3)
These columns show the number of 9 x 9 or 18 x 18 multipliers for each device. The total number of multipliers for each device is not the sum of all the multipliers.
Soft multipliers are implemented in sum of multiplication mode. M9K memory blocks are configured with
18-bit data widths to support 16-bit coefficients. The sum of the coefficients requires 18-bits of resolution to account for overflow.
The total number of multipliers may vary, depending on the multiplier mode you use.
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Each embedded multiplier consists of three elements. Depending on the application needs, you can use an embedded multiplier block in one of two operational modes.
2
Each embedded multiplier consists of the following elements:
• Multiplier stage
• Input and output registers
• Input and output interfaces
Figure 2-1: Multiplier Block Architecture
signa signb aclr clock ena
Data A
Data B
D
ENA
Q
CLRN
D
ENA
Q
CLRN
D
ENA
Q
CLRN
Input
Register
Output
Register
Embedded Multiplier Block
Data Out
Depending on the operational mode of the multiplier, you can send each multiplier input signal into either one of the following:
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. Altera warrants performance of its semiconductor products to current specifications in accordance with Altera's standard warranty, but reserves the right to make changes to any products and services at any time without notice. Altera assumes no responsibility or liability arising out of the application or use of any information, product, or service described herein except as expressly agreed to in writing by Altera. Altera customers are advised to obtain the latest version of device specifications before relying on any published information and before placing orders for products or services.
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Multiplier Stage
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• An input register
• The multiplier in 9- or 18-bit sections
Each multiplier input signal can be sent through a register independently of other input signals. For example, you can send the multiplier
Data A
signal through a register and send the
Data B
signal directly to the multiplier.
The following control signals are available to each input register in the embedded multiplier:
• Clock
• Clock enable
• Asynchronous clear
All input and output registers in a single embedded multiplier are fed by the same clock, clock enable, and asynchronous clear signals.
The multiplier stage of an embedded multiplier block supports 9 × 9 or 18 × 18 multipliers and other multipliers in between these configurations. Depending on the data width or operational mode of the multiplier, a single embedded multiplier can perform one or two multiplications in parallel.
Each multiplier operand is a unique signed or unsigned number. Two signals, signa
and signb
, control an input of a multiplier and determine if the value is signed or unsigned. If the signa
signal is high, the
Data A
operand is a signed number. If the signa
signal is low, the
Data A
operand is an unsigned number.
The following table lists the sign of the multiplication results for the various operand sign representations.
The results of the multiplication are signed if any one of the operands is a signed value.
signa
Value
Unsigned
Unsigned
Signed
Signed
Data A
Logic Level
Low
Low
High
High
signb
Value
Unsigned
Signed
Unsigned
Signed
Data B
Logic Level
Low
High
Low
High
Result
Unsigned
Signed
Signed
Signed
You can dynamically change the signa
and signb
signals to modify the sign representation of the input operands at run time. You can send the signa
and signb
signals through a dedicated input register. The multiplier offers full precision, regardless of the sign representation.
When the signa
and signb
signals are unused, the Quartus Prime software sets the multiplier to perform unsigned multiplication by default.
You can register the embedded multiplier output using output registers in either 18- or 36-bit sections.
This depends on the operational mode of the multiplier. The following control signals are available for each output register in the embedded multiplier:
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Embedded Multipliers Operational Modes
2-3
• Clock
• Clock enable
• Asynchronous clear
All input and output registers in a single embedded multiplier are fed by the same clock, clock enable, and asynchronous clear signals.
You can use an embedded multiplier block in one of two operational modes, depending on the applica‐ tion needs:
• One 18-bit x 18-bit multiplier
• Up to two 9-bit x 9-bit independent multipliers
You can also use embedded multipliers of the MAX
®
10 devices to implement multiplier adder and multiplier accumulator functions. The multiplier portion of the function is implemented using embedded multipliers. The adder or accumulator function is implemented in logic elements (LEs).
You can configure each embedded multiplier to support a single 18 x 18 multiplier for input widths of 10 to 18 bits.
The following figure shows the embedded multiplier configured to support an 18-bit multiplier.
Figure 2-2: 18-Bit Multiplier Mode
signa signb aclr clock ena
Data A [17..0]
Data B [17..0]
D
ENA
Q
CLRN
D
ENA
Q
CLRN
D
ENA
Q
CLRN
Data Out [35..0]
18 x 18 Multiplier
Embedded Multiplier
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9-Bit Multipliers
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All 18-bit multiplier inputs and results are independently sent through registers. The multiplier inputs can accept signed integers, unsigned integers, or a combination of both. Also, you can dynamically change the signa
and signb
signals and send these signals through dedicated input registers.
You can configure each embedded multiplier to support two 9 × 9 independent multipliers for input widths of up to 9 bits.
The following figure shows the embedded multiplier configured to support two 9-bit multipliers.
Figure 2-3: 9-Bit Multiplier Mode
signa signb aclr clock ena
Data A 0 [8..0]
Data B 0 [8..0]
D
ENA
Q
CLRN
D
ENA
Q
CLRN
D
ENA
Q
CLRN
9 x 9 Multiplier
Data Out 0 [17..0]
Data A 1 [8..0]
Data B 1 [8..0]
D
ENA
Q
CLRN
D
ENA
Q
CLRN
D
ENA
Q
CLRN
Data Out 1 [17..0]
9 x 9 Multiplier
Embedded Multiplier
All 9-bit multiplier inputs and results are independently sent through registers. The multiplier inputs can accept signed integers, unsigned integers, or a combination of both.
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9-Bit Multipliers
2-5
Each embedded multiplier block has only one signa
and one signb
signal to control the sign representa‐ tion of the input data to the block. If the embedded multiplier block has two 9 × 9 multipliers the following applies:
• The
Data A
input of both multipliers share the same signa
signal
• The
Data B
input of both multipliers share the same signb
signal
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The Quartus Prime software contains tools for you to create and compile your design, and configure your device.
You can prepare for device migration, set pin assignments, define placement restrictions, setup timing constraints, and customize IP cores using the Quartus Prime software.
•
•
•
Related Information
Introduction to Altera IP Cores
Provides general information about all Altera IP cores, including parameterizing, generating, upgrading, and simulating IP.
Creating Version-Independent IP and Qsys Simulation Scripts
Create simulation scripts that do not require manual updates for software or IP version upgrades.
Project Management Best Practices
Guidelines for efficient management and portability of your project and IP files.
3
The following integer arithmetic IP cores use the MAX 10 device embedded multipliers block:
• LPM_MULT
• ALTMULT_ACCUM (MAC)
• ALTMULT_ADD
• ALTMULT_COMPLEX
You can view the Verilog HDL prototype for the IP cores in the following Verilog Design Files (.v):
Table 3-1: Verilog HDL Prototype Location
Integer Arithmetic Megafunctions
LPM_MULT
Directory
<Quartus Prime installation directory>\eda\synthesis lpm.v
Verilog Design File (.v)
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2015 Altera Corporation. All rights reserved. ALTERA, ARRIA, CYCLONE, ENPIRION, MAX, MEGACORE, NIOS, QUARTUS and STRATIX words and logos are trademarks of Altera Corporation and registered in the U.S. Patent and Trademark Office and in other countries. All other words and logos identified as trademarks or service marks are the property of their respective holders as described at www.altera.com/common/legal.html
. Altera warrants performance of its semiconductor products to current specifications in accordance with Altera's standard warranty, but reserves the right to make changes to any products and services at any time without notice. Altera assumes no responsibility or liability arising out of the application or use of any information, product, or service described herein except as expressly agreed to in writing by Altera. Altera customers are advised to obtain the latest version of device specifications before relying on any published information and before placing orders for products or services.
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VHDL Component Declaration Location
Integer Arithmetic Megafunctions
• ALTMULT_ACCUM
• ALTMULT_ADD
• ALTMULT_COMPLEX
Directory
<Quartus Prime installation directory>\eda\synthesis
Verilog Design File (.v) altera_mf.v
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You can view the VHDL component declaration for the IP cores in the following VHDL Design Files
(.vhd):
Integer Arithmetic Megafunctions
LPM_MULT
• ALTMULT_ACCUM
• ALTMULT_ADD
• ALTMULT_COMPLEX
Directory
<Quartus Prime installation directory>\libraries\vhdl\lpm
<Quartus Prime installation directory>\libraries\vhdl\altera_ mf
VHDL Design File (.vhd)
LPM_PACK.vhd
altera_mf_components.vhd
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There are three groups of options: General, General2, and Pipeling.
Table 4-1: LPM_MULT Parameters - General
This table lists the IP core parameters applicable to MAX 10 devices.
GUI Parameter Parameter Condition
Multiplier configuration — —
Value
• Multiply
‘ dataa
’ input by ‘datab’ input
• Multiply
‘ dataa
’ input by itself
(squaring operation)
How wide should the
‘ dataa
’ input be?
How wide should the
‘ datab
’ input be?
How should the width of the ‘ result
’ output be determined?
How should the width of the ‘ result
’ output be determined? >
Restrict the width to [] bits
LPM_
WIDTHA
LPM_
WIDTHB
LPM_
WIDTHP
LPM_
WIDTHP
‘
—
—
—
How should the width of the result
’ output be determined? >
Restrict the width to [] bits = On
1–256
1–256
• Automatically calculate the width
• Restrict the width to [] bits
1–256
Description
Specifies the multiplier configuration.
Specifies the width of the dataa[]
port.
Specifies the width of the datab[] port.
Specifies how the result width is determined.
You can set the result width.
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2015 Altera Corporation. All rights reserved. ALTERA, ARRIA, CYCLONE, ENPIRION, MAX, MEGACORE, NIOS, QUARTUS and STRATIX words and logos are trademarks of Altera Corporation and registered in the U.S. Patent and Trademark Office and in other countries. All other words and logos identified as trademarks or service marks are the property of their respective holders as described at www.altera.com/common/legal.html
. Altera warrants performance of its semiconductor products to current specifications in accordance with Altera's standard warranty, but reserves the right to make changes to any products and services at any time without notice. Altera assumes no responsibility or liability arising out of the application or use of any information, product, or service described herein except as expressly agreed to in writing by Altera. Altera customers are advised to obtain the latest version of device specifications before relying on any published information and before placing orders for products or services.
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4-2
LPM_MULT Parameter Settings
Table 4-2: LPM_MULT Parameters - General2
This table lists the IP core parameters applicable to MAX 10 devices.
GUI Parameter Parameter Condition
Does the ‘ datab
’ input bus have a constant value?
— —
• No
Value
• Yes, the value is []
Which type of multipli‐ cation do you want?
Which multiplier implementation should be used?
LPM_
REPRESENTATI
ON
DEDICATED_
MULTIPLIER_
CIRCUITRY
—
—
• Unsigned
• Signed
• Use default implementa‐ tion
• Use the dedicated multiplier circuitry (Not available for all families)
• Use logic elements
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Description
You can specify the constant value of the
‘ datab
’ input bus, if any.
Specifies the type of multiplication performed.
Specifies the multiplier implementation.
Table 4-3: LPM_MULT Parameters - Pipeling
This table lists the IP core parameters applicable to MAX 10 devices.
GUI Parameter Parameter Condition
Do you want to pipeline the function?
LPM_PIPELINE —
Value
• No
• Yes, I want output latency of [] clock cycles
Create an ‘ aclr
’ asynchronous clear port
Create a ‘ clken enable clock
’ clock
What type of optimiza‐ tion do you want?
—
—
MAXIMIZE_
SPEED
Do you want to pipeline the function? = Yes,
I want output latency of [] clock cycles
Do you want to pipeline the function? = Yes,
I want output latency of [] clock cycles
—
On or off
On or off
• Default
• Speed
• Area
Description
You can add extra latency to the outputs, if any.
Specifies asynchronous clear for the complex multiplier. Clears the function asynchro‐ nously when aclr port is asserted high.
Specifies active high clock enable for the clock port of the complex multiplier
You can specify if the type of optimization is determined by Quartus
Prime, speed, or area.
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Ports
4-3
Table 4-4: LPM_MULT Input Ports
Port Name
dataa[] datab[] clock clken aclr
Required
Yes
Yes
No
No
No
Table 4-5: LPM_MULT Output Ports
Port Name
result[]
Required
Yes
Description
Data input. The size of the input port depends on the
LPM_WIDTHA parameter value.
Data input. The size of the input port depends on the
LPM_WIDTHB parameter value.
Clock input for pipelined usage. For
LPM_PIPELINE
values other than
0
(default), the clock port must be enabled.
Clock enable for pipelined usage. When the clken
port is asserted high, the adder/subtractor operation takes place. When the signal is low, no operation occurs. If omitted, the default value is
1
.
Asynchronous clear port used at any time to reset the pipeline to all
0 s, asynchronously to the clock signal. The pipeline initializes to an undefined (X) logic level. The outputs are a consistent, but non-zero value.
Description
Data output. The size of the output port depends on the
LPM_WIDTHP
parameter value. If
LPM_WIDTHP
< max (
LPM_
WIDTHA
+
LPM_WIDTHB
,
LPM_WIDTHS
) or (
LPM_WIDTHA
+
LPM_
WIDTHS
), only the
LPM_WIDTHP
MSBs are present.
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There are four groups of options: General, Extra Modes, Multipliers, and Accumulator.
Table 5-1: ALTMULT_ACCUM Parameters - General
This table lists the IP core parameters applicable to MAX 10 devices.
GUI Parameter Parameter Condition
What is the number of multipliers?
All multipliers have similar configurations
NUMBER_OF_
MULTIPLIERS
—
—
—
1
On
Value
How wide should the A input buses be?
How wide should the B input buses be?
How wide should the
‘ result
’ output bus be?
Create a 4 th
asynchro‐ nous clear input option
WIDTH_A
WIDTH_B
WIDTH_
RESULT
—
Create an associated clock enable for each clock
—
What is the representa‐ tion format for A inputs?
REPRESENTATI
ON_A
—
—
—
—
—
—
1–256
1–256
1–256
On or Off
On or Off
• Signed
• Unsigned
• Variable
Description
By default, only 1 multiplier is supported.
By default all multipliers have similar configurations
Specifies the width of A input buses.
Specifies the width of B input buses.
Specifies the width of
‘ result
’ output bus.
Turn on this option if you want to create a 4 th asynchronous clear input option.
Turn on this option if you want to create an associated clock enable for each clock.
Specifies the represen‐ tation format for A inputs.
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. Altera warrants performance of its semiconductor products to current specifications in accordance with Altera's standard warranty, but reserves the right to make changes to any products and services at any time without notice. Altera assumes no responsibility or liability arising out of the application or use of any information, product, or service described herein except as expressly agreed to in writing by Altera. Altera customers are advised to obtain the latest version of device specifications before relying on any published information and before placing orders for products or services.
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5-2
ALTMULT_ACCUM Parameter Settings
GUI Parameter
‘ signa
’ input controls the sign (1 signed/0 unsigned)
Parameter
PORT_SIGNA
Description
High ‘ signa
’ input indicates signed and low ‘ signa
’ input indicates unsigned.
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Condition
Input
Representation >
What is the representation format for A inputs? =
Variable
Input
Representation >
More Options
Value
More Options
On or Off Register ‘ signa
’ input —
‘
Add an extra pipeline register
Input Register > What is the source for clock input?
Input Register > What is the source for asynchronous clear input?
Pipeline Register >
What is the source for clock input?
Pipeline Register >
What is the source for asynchronous clear input?
What is the representa‐ tion format for B inputs?
— Input
Representation >
More Options
SIGN_REG_A Input
Representation >
More Options
SIGN_ACLR_A Input
Representation >
More Options
SIGN_
PIPELINE_
REG_A
SIGN_
PIPELINE_
ACLR_A
REPRESENTATI
ONS_B
Input
Representation >
More Options
Input
Representation >
More Options
— signb
’ input controls the sign (1 signed/0 unsigned)
Register ‘ signb
’ input
PORT_SIGNB
—
On or Off
Clock0–Clock3
• Aclr0–Aclr2
• None
Clock0–Clock3
• Aclr0–Aclr2
• None
• Signed
• Unsigned
• Variable
More Options Input
Representation >
What is the representation format for B inputs? =
Variable
Input
Representation >
More Options
On or Off
Add an extra pipeline register
— Input
Representation >
More Options
On or Off
Turn on this option if you want to enable the register of ‘ signa
’ input
Turn on this option if you want to enable the extra pipeline register
Specifies the source for clock input.
Specifies the source for asynchronous clear input.
Specifies the source for clock input.
Specifies the source for asynchronous clear input.
Specifies the represen‐ tation format for B inputs.
High ‘ signb
’ input indicates signed and low ‘ signb
’ input indicates unsigned.
Turn on this option if you want to enable the register of ‘ signb
’ input
Turn on this option if you want to enable the extra pipeline register
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GUI Parameter
Input Register > What is the source for clock input?
Input Register > What is the source for asynchronous clear input?
Pipeline Register >
What is the source for clock input?
Pipeline Register >
What is the source for asynchronous clear input?
Parameter Condition
SIGN_REG_B Input
Representation >
More Options
SIGN_ACLR_B Input
Representation >
More Options
SIGN_
PIPELINE_
REG_B
SIGN_
PIPELINE_
ACLR_B
Input
Representation >
More Options
Input
Representation >
More Options
Table 5-2: ALTMULT_ACCUM Parameters - Extra Modes
GUI Parameter
Create a shiftout output from A input of the last multiplier
Parameter
—
Condition
—
ALTMULT_ACCUM Parameter Settings
Value
Clock0–Clock3
• Aclr0–Aclr2
• None
Clock0–Clock3
• Aclr0–Aclr2
• None
Value
On or Off
Specifies the source for asynchronous clear input.
Specifies the source for clock input.
Specifies the source for asynchronous clear input.
5-3
Description
Specifies the source for clock input.
Create a shiftout output from B input of the last multiplier
Add extra register(s) at the output
What is the source for clock input?
What is the source for asynchronous clear input?
Add [] extra latency to the output
—
—
OUTPUT_REG Outputs
—
Configuration >
More Options
OUTPUT_ACLR Outputs
Configuration >
More Options
Outputs
—
—
Configuration >
More Options
On or Off
On
Clock0–Clock3
• Aclr0–Aclr2
• None
0, 1, 2, 3, 4, 5, 6,
7, 8, or 12
Description
Turn on this option to create a shiftout output from A input of the last multiplier.
Turn on this option to create a shiftout output from B input of the last multiplier.
By default, output register must be enabled for accumulator.
Specifies the clock signal for the registers on the outputs.
Specifies the asynchro‐ nous clear signal for the registers on the outputs.
Specifies the extra latency to add to the output.
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ALTMULT_ACCUM Parameter Settings
GUI Parameter
Which multiplieradder implementation should be used?
Parameter
DEDICATED_
MULTIPLIER_
CIRCUITRY
Condition
—
Value
• Use the default implementa‐ tion
• Use dedicated multiplier circuitry (Not available for all families)
• Use logic elements
Description
Specifies the multiplier-adder implementation.
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Table 5-3: ALTMULT_ACCUM Parameters - Multipliers
This table lists the IP core parameters applicable to MAX 10 devices.
GUI Parameter
Register input A of the multiplier
Parameter
—
Condition
—
Value
On or Off
What is the source for clock input?
What is the source for asynchronous clear input?
Register input B of the multiplier
INPUT_REG_A • Input
Configuration
> Register input A of the multiplier =
On
• Input
Configuration
> More
Options
INPUT_ACLR_
A
Clock0–Clock3
• Aclr0–Aclr2
• None
• Input
Configuration
> Register input A of the multiplier =
On
• Input
Configuration
> More
Options
— — On or Off
Description
Turn on to enable register input A of the multiplier.
Specifies the clock port for the dataa[]
port.
Specifies the asynchro‐ nous clear port for the dataa[]
port.
Turn on to enable register input B of the multiplier.
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GUI Parameter
What is the source for clock input?
What is the source for asynchronous clear input?
What is the input A of the multiplier connected to?
What is the input B of the multiplier connected to?
Register output of the multiplier
What is the source for clock input?
ALTMULT_ACCUM Parameter Settings
5-5
Parameter Condition
INPUT_REG_B • Input
Configuration
> Register input B of the multiplier =
On
• Input
Configuration
> More
Options
INPUT_ACLR_
B
Value
Clock0–Clock3
—
—
—
MULTIPLIER_
REG
Description
Specifies the clock port for the datab[] port.
• Input
Configuration
> Register input B of the multiplier =
On
• Input
Configuration
> More
Options
—
• Aclr0–Aclr2
• None
—
—
• Output
Configuration
> Register output of the multiplier =
On
• Output
Configuration
> More
Options
Specifies the asynchro‐ nous clear port for the datab[]
port.
Multiplier input By default, input A of the multiplier is always connected to the multiplier’s input.
Multiplier input By default, input B of the multiplier is always connected to the multiplier’s input.
On or Off
Clock0–Clock3
Turn on to enable register output of the multiplier.
Specifies the clock signal for the register that immediately follows the multiplier.
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ALTMULT_ACCUM Parameter Settings
GUI Parameter
What is the source for asynchronous clear input?
Parameter
MULTIPLIER_
ACLR
Register ‘ input accum_sload
’ —
Condition Value
• Output
Configuration
> Register output of the multiplier =
On
• Output
Configuration
> More
Options
• Aclr0–Aclr2
• None
Table 5-4: ALTMULT_ACCUM Parameters - Accumulator
This table lists the IP core parameters applicable to MAX 10 devices.
GUI Parameter Parameter Condition
Create an ‘ sload accum_
’ input port
— —
Value
On or off
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Description
Specifies the asynchro‐ nous clear signal of the register that follows the corresponding multiplier.
Description
Dynamically specifies whether the accumulator value is constant. If the accum_ sload
port is high, then the multiplier output is loaded into the accumulator.
Turn on to enable register ‘ accum_sload
’ input.
Add an extra pipeline register
—
• Accumulator
> Create an
‘accum_sload’ input port =
On
• Accumulator
> More
Options
On or off
On or off
• Accumulator
> Create an
‘ accum_ sload
’ input port = On
• Accumulator
> More
Options
Turn on this option if you want to enable the extra pipeline register
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GUI Parameter
Input Register > What is the source for clock input?
Input Register > What is the source for asynchronous clear input?
Pipeline Register >
What is the source for clock input?
Pipeline Register >
What is the source for asynchronous clear input?
ALTMULT_ACCUM Parameter Settings
Parameter
ACCUM_
SLOAD_REG
ACCUM_
SLOAD_ACLR
ACCUM_
SLOAD_
PIPELINE_REG
ACCUM_
SLOAD_
PIPELINE_
ACLR
—
Condition
• Accumulator
> Create an
‘accum_sload’ input port =
On
• Accumulator
> More
Options
Value
Clock0–Clock3
• Accumulator
> Create an
‘ accum_ sload
’ input port = On
• Accumulator
> More
Options
• •
Accumulator
> Create an
‘ accum_ sload
’ input port = On
• Accumulator
> More
Options
• Aclr0–Aclr2
• None
Clock0–Clock3
• Accumulator
> Create an
‘ accum_soad
’ input port =
On
• Accumulator
> More
Options
—
• Aclr0–Aclr2
• None
On or Off Create an ‘ overflow
’ output port
Add [] extra latency to the multiplier output
EXTRA_
MULTIPLIER_
LATENCY
— 0, 1, 2, 3, 4, 5, 6,
7, 8, or 12
Description
Specifies the clock signal for the accum_ sload
port.
Specifies the asynchro‐ nous clear source for the first register on the accum_sload
input.
Specifies the source for asynchronous clear input.
Overflow
port for the accumulator
Specifies the number of clock cycles of latency for the multiplier portion of the DSP block. If the
MULTIPLIER_REG parameter is specified, then the specified clock port is used to add the latency.
5-7
Specifies the source for clock input.
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ALTMULT_ACCUM Ports
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Table 5-5: ALTMULT_ACCUM IP Core Input Ports
Port Name
accum_sload aclr0 aclr1 aclr2 aclr3 addnsub clock0 clock1 clock2 clock3 dataa[] datab[] ena0 ena1 ena2 ena3
Required
No
No
No
No
No
No
No
No
No
No
Yes
Yes
No
No
No
No
Description
Causes the value on the accumulator feedback path to go to zero (0) or to accum_sload_upper_data
when concatenated with 0. If the accumulator is adding and the accum_sload
port is high, then the multiplier output is loaded into the accumulator. If the accumulator is subtracting, then the opposite (negative value) of the multiplier output is loaded into the accumulator.
The first asynchronous clear input. The aclr0
port is active high.
The second asynchronous clear input. The aclr1
port is active high.
The third asynchronous clear input. The
aclr2
port is active high.
The fourth asynchronous clear input. The aclr3
port is active high.
Controls the functionality of the adder. If the addnsub
port is high, the adder performs an add function; if the addnsub
port is low, the adder performs a subtract function.
Specifies the first clock input, usable by any register in the IP core.
Specifies the second clock input, usable by any register in the
IP core.
Specifies the third clock input, usable by any register in the IP core.
Specifies the fourth clock input, usable by any register in the
IP core.
Data input to the multiplier. The size of the input port depends on the
WIDTH_A
parameter value.
Data input to the multiplier. The size of the input port depends on the
WIDTH_B
parameter value.
Clock enable for the clock0
port.
Clock enable for the clock1
port.
Clock enable for the clock2
port.
Clock enable for the clock3
port.
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signa signb
Port Name Required
No
No
ALTMULT_ACCUM Ports
Description
Specifies the numerical representation of the dataa[]
port. If the signa
port is high, the multiplier treats the dataa[]
port as signed two's complement. If the signa
port is low, the multiplier treats the dataa[]
port as an unsigned number.
Specifies the numerical representation of the datab[]
port. If the signb
port is high, the multiplier treats the datab[]
port as signed two's complement. If the signb
port is low, the multiplier treats the datab[] port as an unsigned number.
Table 5-6: ALTMULT_ACCUM IP Core Output Ports
5-9
Port Name
overflow result[] scanouta[] scanoutb[]
Required
No
Yes
No
No
Description
Overflow port for the accumulator.
Accumulator output port. The size of the output port depends on the
WIDTH_RESULT
parameter value.
Output of the first shift register. The size of the output port depends on the
WIDTH_A
parameter value. When instantiating the ALTMULT_ACCUM IP core with the MegaWizard Plug-
In Manager, the MegaWizard Plug-In Manager renames the scanouta[]
port to shiftouta
port.
Output of the second shift register. The size of the input port depends on the
WIDTH_B
parameter value. When instantiating the ALTMULT_ACCUM IP core with the MegaWizard Plug-
In Manager, the MegaWizard Plug-In Manager renames the scanoutb[]
port to shiftoutb
port.
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There are three groups of options: General, Extra Modes, and Multipliers.
Table 6-1: ALTMULT_ADD Parameters - General
This table lists the IP core parameters applicable to MAX 10 devices.
GUI Parameter Parameter Condition
What is the number of multipliers?
NUMBER_OF_
MULTIPLIERS
—
Value
1, 2, 3, or 4
All multipliers have similar configurations
Create an associated clock enable for each clock
—
How wide should the A input buses be?
How wide should the B input buses be?
How wide should the
‘ result
’ output bus be?
Create a 4 th asynchro‐ nous clear input option
WIDTH_A
WIDTH_B
WIDTH_
RESULT
—
—
—
—
—
—
—
—
On or Off
1–256
1–256
1–256
On or Off
On or Off
Description
Specifies the number of multipliers. You can specify up to four multipliers.
Turn on this option if you want all multipliers to have similar configurations.
Specifies the width of A input buses.
Specifies the width of B input buses.
Specifies the width of
‘ result
’ output bus.
Turn on this option if you want to create a 4 th asynchronous clear input option.
Turn on this option if you want to create an associated clock enable for each clock.
©
2015 Altera Corporation. All rights reserved. ALTERA, ARRIA, CYCLONE, ENPIRION, MAX, MEGACORE, NIOS, QUARTUS and STRATIX words and logos are trademarks of Altera Corporation and registered in the U.S. Patent and Trademark Office and in other countries. All other words and logos identified as trademarks or service marks are the property of their respective holders as described at www.altera.com/common/legal.html
. Altera warrants performance of its semiconductor products to current specifications in accordance with Altera's standard warranty, but reserves the right to make changes to any products and services at any time without notice. Altera assumes no responsibility or liability arising out of the application or use of any information, product, or service described herein except as expressly agreed to in writing by Altera. Altera customers are advised to obtain the latest version of device specifications before relying on any published information and before placing orders for products or services.
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ISO
9001:2008
Registered
6-2
ALTMULT_ADD Parameter Settings
‘
GUI Parameter
What is the representa‐ tion format for A inputs?
Parameter
REPRESENTATI
ON_A signa
’ input controls the sign (1 signed/0 unsigned)
Register ‘ signa
’ input
PORT_SIGNA
—
Condition
—
Value
• Signed
• Unsigned
• Variable
More Options Input
Representation >
What is the representation format for A inputs? =
Variable
Input
Representation >
More Options
On or Off
Description
Specifies the represen‐ tation format for A inputs.
High ‘ signa
’ input indicates signed and low ‘ signa
’ input indicates unsigned.
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‘
Add an extra pipeline register
—
Input Register > What is the source for clock input?
Input Register > What is the source for asynchronous clear input?
Pipeline Register >
What is the source for clock input?
Pipeline Register >
What is the source for asynchronous clear input?
What is the representa‐ tion format for B inputs?
SIGNED_
REGISTER_A
SIGNED_
ACLR_A
SIGNED_
PIPELINE_
REGISTER_A
SIGNED_
PIPELINE_
ACLR_A
REPRESENTATI
ONS_B
Input
Representation >
More Options
Input
Representation >
More Options
Input
Representation >
More Options
Input
Representation >
More Options
Input
Representation >
More Options
— signb
’ input controls the sign (1 signed/0 unsigned)
PORT_SIGNB
On or Off
Clock0–Clock3
• Aclr0–Aclr2
• None
Clock0–Clock3
• Aclr0–Aclr2
• None
Input
Representation >
What is the representation format for B inputs? =
Variable
• Signed
• Unsigned
• Variable
More Options
Turn on this option if you want to enable the register of ‘ signa
’ input
Turn on this option if you want to enable the extra pipeline register
Specifies the source for clock input.
Specifies the source for asynchronous clear input.
Specifies the source for clock input.
Specifies the source for asynchronous clear input.
Specifies the represen‐ tation format for B inputs.
High ‘ signb
’ input indicates signed and low ‘ signb
’ input indicates unsigned.
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GUI Parameter
Register ‘ signb
’ input
Add an extra pipeline register
Input Register > What is the source for clock input?
Input Register > What is the source for asynchronous clear input?
Pipeline Register >
What is the source for clock input?
Pipeline Register >
What is the source for asynchronous clear input?
Parameter
—
—
SIGNED_
REGISTER_B
SIGNED_
ACLR_B
SIGNED_
PIPELINE_
REGISTER_B
SIGNED_
PIPELINE_
ACLR_B
Condition
Input
Representation >
More Options
Input
Representation >
More Options
Input
Representation >
More Options
Input
Representation >
More Options
Input
Representation >
More Options
Input
Representation >
More Options
ALTMULT_ADD Parameter Settings
Value
On or Off
On or Off
Clock0–Clock3
• Aclr0–Aclr2
• None
Clock0–Clock3
• Aclr0–Aclr2
• None
Table 6-2: ALTMULT_ADD Parameters - Extra Modes
This table lists the IP core parameters applicable to MAX 10 devices.
GUI Parameter Parameter Condition
Create a shiftout output from A input of the last multiplier
Create a shiftout output from B input of the last multiplier
Register output of the adder unit
—
—
—
—
—
—
Value
On or Off
On or Off
On or Off
What is the source for clock input?
OUTPUT_
REGISTER
• Outputs
Configuration
> Register output of the adder unit =
On
• Outputs
Configuration
> More
Options
Clock0–Clock3
Specifies the source for asynchronous clear input.
Specifies the source for clock input.
Specifies the source for asynchronous clear input.
Description
Turn on to create a signal from A input.
Turn on to create a signal from B input.
Turn on to create a register output of the adder unit.
Specifies the clock signal for the output register.
6-3
Description
Turn on this option if you want to enable the register of ‘ signb
’ input
Turn on this option if you want to enable the extra pipeline register
Specifies the source for clock input.
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ALTMULT_ADD Parameter Settings
GUI Parameter
What is the source for asynchronous clear input?
What operation should be performed on outputs of the first pair of multipliers?
Parameter Condition
OUTPUT_ACLR • Outputs
Configuration
> Register output of the adder unit =
On
• Outputs
Configuration
> More
Options
MUTIPLIER1_
DIRECTION
General > What is the number of multipliers? = 2,
3, or 4
Value
• Aclr0–Aclr2
• None
• Add
• Subtract
• Variable
‘ addnsub1 controls the operation
(1 add/0 sub)
Register ‘ input
’ input addnsub1
'
—
—
Adder Operation
> What operation should be performed on outputs of the first pair of multipliers? =
Variable
—
More Options
On or Off
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Description
Specifies the source for asynchronous clear input.
Specifies whether the second multiplier adds or subtracts its value from the sum. Values are add and subtract. If
Variable is selected the addnsub1
port is used.
High ‘ addnsub1
’ input indicates add and low
‘ addnsub1
’ input indicates subtract.
Add an extra pipeline register
— —
Adder Operation
> More Options
On or Off
Clock0–Clock3
Turn on this option if you want to enable the register of ‘ addnsub1
’ input
Turn on this option if you want to enable the extra pipeline register
Specifies the source for clock input.
Input Register > What is the source for clock input?
Input Register > What is the source for asynchronous clear input?
Pipeline Register >
What is the source for clock input?
ADDNSUB_
MULTIPLIER_
REGISTER[1]
ADDSUB_
MULTIPLIER_
ACLR[1]
ADDNSUB_
MULTIPLIER_
PIPELINE_
REGISTER[1]
Adder Operation
> More Options
Adder Operation
> More Options
• Aclr0–Aclr2
• None
Clock0–Clock3
Specifies the source for asynchronous clear input.
Specifies the source for clock input.
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GUI Parameter
Pipeline Register >
What is the source for asynchronous clear input?
What operation should be performed on outputs of the second pair of multipliers?
Parameter
ADDNSUB_
MULTIPLIER_
PIPELINE_
ACLR[1]
MUTIPLIER3_
DIRECTION
‘ addnsub3 register
’ input controls the sign (1 add/0 sub) - More
Options
Register ‘ input addnsub3
’
Add an extra pipeline
—
—
—
Condition
Adder Operation
> More Options
General > What is the number of multipliers? = 4
—
—
—
Adder Operation
> More Options
ALTMULT_ADD Parameter Settings
Value
• Aclr0–Aclr2
• None
—
—
On or Off
On or Off
Clock0–Clock3
Description
Specifies the source for asynchronous clear input.
Specifies whether the fourth and all subsequent oddnumbered multipliers add or subtract their results from the total.
Values are add and subtract. If Variable is selected, the addnsub3 port is used.
High ‘ addnsub3
’ input indicates add and low
‘ addnsub3
’ input indicates subtract.
6-5
Turn on this option if you want to enable the register of ‘ addnsub3
’ input.
Turn on this option if you want to enable the extra pipeline register.
Specifies the source for clock input.
Input Register > What is the source for clock input?
Input Register > What is the source for asynchronous clear input?
Pipeline Register >
What is the source for clock input?
Pipeline Register >
What is the source for asynchronous clear input?
ADDNSUB_
MULTIPLIER_
REGISTER[3]
ADDSUB_
MULTIPLIER_
ACLR[3]
ADDNSUB_
MULTIPLIER_
PIPELINE_
REGISTER[3]
ADDNSUB_
MULTIPLIER_
PIPELINE_
ACLR[3]
Adder Operation
> More Options
Adder Operation
> More Options
Adder Operation
> More Options
• Aclr0–Aclr2
• None
Clock0–Clock3
• Aclr0–Aclr2
• None
Specifies the source for asynchronous clear input.
Specifies the source for clock input.
Specifies the source for asynchronous clear input.
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ALTMULT_ADD Parameter Settings
GUI Parameter
Which multiplieradder implementation should be used?
Parameter
DEDICATED_
MULTIPLIER_
CIRCUITRY
Condition
—
Value
• Use the default implementa‐ tion
• Use dedicated multiplier circuitry (Not available for all families)
• Use logic elements
Description
Specifies the multiplier-adder implementation.
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Table 6-3: ALTMULT_ADD Parameters - Multipliers
This table lists the IP core parameters applicable to MAX 10 devices.
GUI Parameter
Register input A of the multiplier
Parameter
—
Condition
—
Value
On or Off
What is the source for clock input?
What is the source for asynchronous clear input?
Register input B of the multiplier
INPUT_
REGISTER_
A[0..3]
INPUT_ACLR_
A[0..3]
—
• Input
Configuration
> Register input A of the multiplier =
On
• • Input
Configuration
> More
Options
Clock0–Clock3
• Input
Configuration
> Register input A of the multiplier =
On
• Input
Configuration
> More
Options
—
• Aclr0–Aclr2
• None
On or Off
Description
Turn on to enable register input A of the multiplier.
Specifies the source for clock input.
Specifies the source for asynchronous clear input.
Turn on to enable register input B of the multiplier.
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GUI Parameter
What is the source for clock input?
What is the source for asynchronous clear input?
What is the input A of the multiplier connected to?
What is the input B of the multiplier connected to?
Register output of the multiplier
What is the source for clock input?
Parameter
INPUT_
REGISTER_
B[0..3]
INPUT_ACLR_
B[0..3]
INPUT_
SOURCE_
A[0..3]
INPUT_
SOURCE_B[0..3]
—
MULTIPLIER_
REGISTER[]
Condition
• Input
Configuration
> Register input B of the multiplier =
On
• Input
Configuration
> More
Options
ALTMULT_ADD Parameter Settings
Value
Clock0–Clock3
• Input
Configuration
> Register input B of the multiplier =
On
• Input
Configuration
> More
Options
—
• Aclr0–Aclr2
• None
• Multiplier input
• Shiftin input
Specifies the source for asynchronous clear input.
6-7
Description
Specifies the source for clock input.
—
—
• Multiplier input
• Shiftin input
On or Off
Specifies the input A of the multiplier is connected to either multiplier input or shiftin input.
Specifies the input B of the multiplier is connected to either multiplier input or shiftin input.
Turn on to enable the register for output of the multiplier.
Specifies the source for clock input.
• Output
Configuration
> Register output of the multiplier =
On
• Output
Configuration
> More
Options
Clock0–Clock3
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ALTMULT_ADD Ports
GUI Parameter
What is the source for asynchronous clear input?
Parameter
MULTIPLIER_
ACLR[]
Condition Value
• Output
Configuration
> Register output of the multiplier =
On
• Output
Configuration
> More
Options
• Aclr0–Aclr2
• None
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Description
Specifies the source for asynchronous clear input.
Table 6-4: ALTMULT_ADD IP Core Input Ports
Port Name
dataa[] datab[] clock[] aclr[] ena[] signa signb
Required
Yes
Yes
No
No
No
No
No
Description
Data input to the multiplier. Input port
[NUMBER_OF_MULTIPLIERS *
WIDTH_A - 1..0]
wide.
Data input to the multiplier. Input port
[NUMBER_OF_MULTIPLIERS *
WIDTH_B - 1..0]
wide.
Clock input port
[0..3]
to the corresponding register. This port can be used by any register in the IP core.
Input port
[0..3]
. Asynchronous clear input to the corresponding register.
Input port
[0..3]
. Clock enable for the corresponding clock[] port.
Specifies the numerical representation of the dataa[]
port. If the signa port is high, the multiplier treats the dataa[]
port as a signed two's complement number. If the signa
port is low, the multiplier treats the dataa[] port as an unsigned number.
Specifies the numerical representation of the datab[]
port. If the signb port is high, the multiplier treats the datab[]
port as a signed two's complement number. If the signb
port is low, the multiplier treats the datab[] port as an unsigned number.
Table 6-5: ALTMULT_ADD IP Core Output Ports
Port Name
result[] overflow scanouta[] scanoutb[]
Required
Yes
No
No
No
Description
Multiplier output port. Output port
[WIDTH_RESULT - 1..0]
wide.
Overflow flag. If output_saturation
is enabled, overflow flag is set.
Output of scan chain A. Output port
[WIDTH_A - 1..0]
wide.
Output of scan chain B. Output port
[WIDTH_B - 1..0]
wide.
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There are two groups of options: General and Implementation Style/Pipelining.
Table 7-1: ALTMULT_COMPLEX Parameters - General
This table lists the IP core parameters applicable to MAX 10 devices.
GUI Parameter Parameter Condition
How wide should the A input buses be?
How wide should the B input buses be?
How wide should the
‘ result
’ output bus be?
What is the representa‐ tion format for A inputs?
What is the representa‐ tion format for B inputs?
WIDTH_A
WIDTH_B
WIDTH_
RESULT
REPRESENTATI
ON_A
REPRESENTATI
ONS_B
—
—
—
—
—
1–256
Value
1–256
1–256
• Signed
• Unsigned
• Signed
• Unsigned
Description
Specifies the width of A input buses.
Specifies the width of B input buses.
Specifies the width of
‘ result
’ output bus.
Specifies the represen‐ tation format for A inputs.
Specifies the represen‐ tation format for B inputs.
©
2015 Altera Corporation. All rights reserved. ALTERA, ARRIA, CYCLONE, ENPIRION, MAX, MEGACORE, NIOS, QUARTUS and STRATIX words and logos are trademarks of Altera Corporation and registered in the U.S. Patent and Trademark Office and in other countries. All other words and logos identified as trademarks or service marks are the property of their respective holders as described at www.altera.com/common/legal.html
. Altera warrants performance of its semiconductor products to current specifications in accordance with Altera's standard warranty, but reserves the right to make changes to any products and services at any time without notice. Altera assumes no responsibility or liability arising out of the application or use of any information, product, or service described herein except as expressly agreed to in writing by Altera. Altera customers are advised to obtain the latest version of device specifications before relying on any published information and before placing orders for products or services.
www.altera.com
101 Innovation Drive, San Jose, CA 95134
ISO
9001:2008
Registered
7-2
Ports
Table 7-2: ALTMULT_COMPLEX Parameters - Implementation Style/Pipelining
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This table lists the IP core parameters applicable to MAX 10 devices.
GUI Parameter Parameter Condition
Which implementa‐ tion style should be used?
IMPLEMENTATIO
N_STYLE
—
Value
Automatically select a style for best trade-off for the current settings
Output latency [] clock cycles
Create an asynchro‐ nous Clear input
Create clock enable input
PIPELINE
—
—
—
—
—
0–14
On or off
On or off
Description
By default automatic selection for MAX 10 device is selected.
Quartus Prime software will determine the best implementation based on the selected device family and input width.
Specifies the number of clock cycles for output latency.
Specifies synchronous clear for the complex multiplier. Clears the function asynchro‐ nously when the aclr port is asserted high.
Specifies active high clock enable for the clock port of the complex multiplier.
Table 7-3: ALTMULT_COMPLEX Input Ports
aclr
Port Name Required
No clock dataa_imag[] dataa_real[] datab_imag[]
Yes
Yes
Yes
Yes
Description
Asynchronous clear for the complex multiplier. When the aclr port is asserted high, the function is asynchronously cleared.
Clock input to the ALTMULT_COMPLEX function.
Imaginary input value for the data
A
port of the complex multiplier. The size of the input port depends on the
WIDTH_A parameter value.
Real input value for the data
A
port of the complex multiplier.
The size of the input port depends on the
WIDTH_A
parameter value.
Imaginary input value for the data
B
port of the complex multiplier. The size of the input port depends on the
WIDTH_B parameter value.
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Port Name
datab_real[] ena
Required
Yes
No
Description
Real input value for the data
B
port of the complex multiplier.
The size of the input port depends on the
WIDTH_B
parameter value.
Active high clock enable for the clock port of the complex multiplier.
Table 7-4: ALTMULT_COMPLEX Output Ports
Ports
7-3
Port Name
result_imag result_real
Required
Yes
Yes
Description
Imaginary output value of the multiplier. The size of the output port depends on the
WIDTH_RESULT
parameter value.
Real output value of the multiplier. The size of the output port depends on the
WIDTH_RESULT
parameter value.
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Date
November
2015
September
2014
Version Changes
2015.11.02 • Changed instances of
Quartus II
to
Quartus Prime
.
• Removed topics on generating IP cores and added links to Introduc‐ tion to Altera IP Cores, Creating Version-Independent IP and Qsys
Simulation Scripts, and Project Management Best Practices.
2014.09.22 Initial release.
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2015 Altera Corporation. All rights reserved. ALTERA, ARRIA, CYCLONE, ENPIRION, MAX, MEGACORE, NIOS, QUARTUS and STRATIX words and logos are trademarks of Altera Corporation and registered in the U.S. Patent and Trademark Office and in other countries. All other words and logos identified as trademarks or service marks are the property of their respective holders as described at www.altera.com/common/legal.html
. Altera warrants performance of its semiconductor products to current specifications in accordance with Altera's standard warranty, but reserves the right to make changes to any products and services at any time without notice. Altera assumes no responsibility or liability arising out of the application or use of any information, product, or service described herein except as expressly agreed to in writing by Altera. Altera customers are advised to obtain the latest version of device specifications before relying on any published information and before placing orders for products or services.
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TOC-2
Contents
MAX 10 Clocking and PLL Architecture and Features......................................2-1
MAX 10 Clocking and PLL Design Considerations........................................... 3-1
Altera Corporation
TOC-3
MAX 10 Clocking and PLL Implementation Guides......................................... 4-1
ALTPLL_RECONFIG IP Core References......................................................... 7-1
Additional Information for MAX 10 Clocking and PLL User Guide............... A-1
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MAX
®
10 devices support global clock (GCLK) networks.
Clock networks provide clock sources for the core. You can use clock networks in high fan-out global signal network such as reset and clear.
MAX 10 devices offer built-in internal oscillator up to 116 MHz.
You can enable or disable the internal oscillator.
Phase-locked loops (PLLs) provide robust clock management and synthesis for device clock management, external system clock management, and I/O interface clocking.
You can use the PLLs as follows:
• Zero-delay buffer
• Jitter attenuator
• Low-skew fan-out buffer
• Frequency synthesizer
• Reduce the number of oscillators required on the board
• Reduce the clock pins used in the device by synthesizing multiple clock frequencies from a single reference clock source
• On-chip clock de-skew
• Dynamic phase shift
• Counters reconfiguration
• Bandwidth reconfiguration
• Programmable output duty cycle
1
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2015 Altera Corporation. All rights reserved. ALTERA, ARRIA, CYCLONE, ENPIRION, MAX, MEGACORE, NIOS, QUARTUS and STRATIX words and logos are trademarks of Altera Corporation and registered in the U.S. Patent and Trademark Office and in other countries. All other words and logos identified as trademarks or service marks are the property of their respective holders as described at www.altera.com/common/legal.html
. Altera warrants performance of its semiconductor products to current specifications in accordance with Altera's standard warranty, but reserves the right to make changes to any products and services at any time without notice. Altera assumes no responsibility or liability arising out of the application or use of any information, product, or service described herein except as expressly agreed to in writing by Altera. Altera customers are advised to obtain the latest version of device specifications before relying on any published information and before placing orders for products or services.
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1-2
PLLs Overview
• PLL cascading
• Reference clock switchover
• Drive the analog-to-digital converter (ADC) clock
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GCLKs drive throughout the entire device, feeding all device quadrants. All resources in the device, such as the I/O elements, logic array blocks (LABs), dedicated multiplier blocks, and M9K memory blocks can use GCLKs as clock sources. Use these clock network resources for control signals, such as clock enables and clears fed by an external pin. Internal logic can also drive GCLKs for internally-generated GCLKs and asynchronous clears, clock enables, or other control signals with high fan-out.
There are two types of external clock pins that can drive the GCLK networks.
Dedicated Clock Input Pins
You can use the dedicated clock input pins (
CLK<#>[p,n]
) to drive clock and global signals, such as asynchronous clears, presets, and clock enables for GCLK networks.
If you do not use the dedicated clock input pins for clock input, you can also use them as general-purpose input or output pins.
The
CLK
pins can be single-ended or differential inputs. When you use the
CLK
pins as single-ended clock inputs, both the
CLK<#>p
and
CLK<#>n
pins have dedicated connection to the GCLK networks. When you use the
CLK
pins as differential inputs, pair two clock pins of the same number to receive differential signaling.
Dual-Purpose Clock Pins
You can use the dual-purpose clock (
DPCLK
) pins for high fan-out control signals, such as protocol signals,
TRDY
and
IRDY
signals for PCI via GCLK networks.
The
DPCLK
pins are only available on the left and right of the I/O banks.
2
©
2015 Altera Corporation. All rights reserved. ALTERA, ARRIA, CYCLONE, ENPIRION, MAX, MEGACORE, NIOS, QUARTUS and STRATIX words and logos are trademarks of Altera Corporation and registered in the U.S. Patent and Trademark Office and in other countries. All other words and logos identified as trademarks or service marks are the property of their respective holders as described at www.altera.com/common/legal.html
. Altera warrants performance of its semiconductor products to current specifications in accordance with Altera's standard warranty, but reserves the right to make changes to any products and services at any time without notice. Altera assumes no responsibility or liability arising out of the application or use of any information, product, or service described herein except as expressly agreed to in writing by Altera. Altera customers are advised to obtain the latest version of device specifications before relying on any published information and before placing orders for products or services.
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CLK0p
CLK0n
CLK1p
CLK1n
CLK2p
CLK2n
CLK3p
CLK3n
CLK4p
(1)
CLK4n
(1)
CLK5p
(1)
CLK5n
(1)
CLK6p
(1)
2-2
Clock Resources
Table 2-1: MAX 10 Clock Resources
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Clock Resource Device Number of Resources
Available
Source of Clock Resource
Dedicated clock input pins
• 10M02
• 10M04
• 10M08
• 10M16
• 10M25
• 10M40
• 10M50
8 single-ended or 4 differential
CLK[3..0][p,n]
pins on the left and right of the I/O banks
16 single-ended or 8 differential
CLK[7..0][p,n]
pins on the top, left, bottom, and right of the I/O banks
DPCLK
pins All 4
DPCLK[3..0]
pins on the left and right of the I/O banks
For more information about the clock input pins connections, refer to the pin connection guidelines.
Related Information
MAX 10 FPGA Device Family Pin Connection Guidelines
Table 2-2: MAX 10 Clock Pins Connectivity to the GCLK Networks
CLK
Pin GCLK
GCLK[0,2,4]
GCLK[1,2]
GCLK[1,3,4]
GCLK[0,3]
GCLK[5,7,9]
GCLK[6,7]
GCLK[6,8,9]
GCLK[5,8]
GCLK[10,12,14]
GCLK[11,12]
GCLK[11,13,14]
GCLK[10,13]
GCLK[15,17,19]
(1) This only applies to 10M16, 10M25, 10M40, and 10M50 devices.
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CLK6n
(1)
CLK7p
(1)
CLK7n
(1)
DPCLK0
DPCLK1
DPCLK2
DPCLK3
CLK
Pin
GCLK[16,17]
GCLK[16,18,19]
GCLK[15,18]
GCLK[0,2]
GCLK[1,3,4]
GCLK[5,7]
GCLK[6,8,9]
Global Clock Network Sources
GCLK
Figure 2-1: GCLK Network Sources for 10M02, 10M04, and 10M08 Devices
2-3
CLK[0,1][p,n]
DPCLK0
DPCLK1
GCLK[0..4] GCLK[5..9]
DPCLK2
DPCLK3
CLK[2,3][p,n]
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Global Clock Control Block
Figure 2-2: GCLK Network Sources for 10M16, 10M25, 10M40, and 10M50 Devices
CLK[4,5][p,n]
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GCLK[10..14]
GCLK[5..9]
DPCLK2
DPCLK3
CLK[2,3][p,n] CLK[0,1][p,n]
DPCLK0
DPCLK1
GCLK[0..4]
GCLK[15..19]
CLK[6,7][p,n]
The clock control block drives GCLKs. The clock control blocks are located on each side of the device, close to the dedicated clock input pins. GCLKs are optimized for minimum clock skew and delay.
The clock control block has the following functions:
• Dynamic GCLK clock source selection (not applicable for
DPCLK
pins and internal logic input)
• GCLK multiplexing
• GCLK network power down (dynamic enable and disable)
Table 2-3: Clock Control Block Inputs
Input
Dedicated clock input pins
Description
Dedicated clock input pins can drive clocks or global signals, such as synchronous and asynchro‐ nous clears, presets, or clock enables onto given
GCLKs.
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DPCLK
pins
PLL counter outputs
Internal logic
Input
Global Clock Control Block
2-5
Description
DPCLK
pins are bidirectional dual function pins that are used for high fan-out control signals, such as protocol signals,
TRDY
and
IRDY
signals for PCI via the GCLK. Clock control blocks that have inputs driven by
DPCLK
pins cannot drive PLL inputs.
PLL counter outputs can drive the GCLK.
You can drive the GCLK through logic array routing to enable the internal logic elements (LEs) to drive a high fan-out, low-skew signal path. Clock control blocks that have inputs driven by internal logic cannot drive PLL inputs.
Figure 2-3: Clock Control Block
Clock Control Block
Static Clock Select (3)
Internal Logic
DPCLK
Enable/
Disable
Global
Clock
C0
C1
C2
Static Clock
Select
(3)
CLK[n + 3]
CLK[n + 2]
CLK[n + 1]
CLK[n] inclk1 inclk0 fIN
PLL
C3
C4 clkswitch
(1)
clkselect[1..0]
(2)
Internal Logic
(4)
inclk1 inclk0 fIN
PLL
C0
C1
C2
C3
C4 clkswitch
(1)
Notes:
(1) The clkswitch signal can either be set through the configuration file or dynamically set when using the manual PLL switchover
feature. The output of the multiplexer is the input clock (fIN) for the PLL.
(2) The clkselect[1..0] signals are fed by internal logic. You can use the clkselect[1..0] signals to dynamically select the clock source for
the GCLK when the device is in user mode. Only one PLL (applicable to PLLs on the same side) can be selected as the clock source to
the GCLK.
(3) The static clock select signals are set in the configuration file. Therefore, dynamic control when the device is in user mode is not
feasible.
(4) You can use internal logic to enable or disable the GCLK in user mode.
Each MAX 10 device has a maximum of 20 clock control blocks. There are five clock control blocks on each side of the device.
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Each PLL generates five clock outputs through the c[4..0]
counters. Two of these clocks can drive the
GCLK through a clock control block.
From the Clock Control Block Inputs table, only the following inputs can drive into any given clock control block:
• Two dedicated clock input pins
• Two PLL counter outputs
• One
DPCLK
pin
• One source from internal logic
The output from the clock control block in turn feeds the corresponding GCLK. The GCLK can drive the
PLL input if the clock control block inputs are outputs of another PLL or dedicated clock input pins.
Normal I/O pins cannot drive the PLL input clock port.
Figure 2-4: Clock Control Block on Each Side of the Device
Clock Input Pins
PLL Outputs
DPCLK
Internal Logic
4
5
4
5
Clock
Control
Block
5
GCLK
Five Clock Control
Blocks on Each Side of the Device
Out of these five inputs to any clock control block, the two clock input pins and two PLL outputs are dynamically selected to feed a GCLK. The clock control block supports static selection of the signal from internal logic.
•
•
Related Information
on page 5-2
You can disable the MAX 10 GCLK (power down) by using both static and dynamic approaches. In the static approach, configuration bits are set in the configuration file generated by the Quartus
®
Prime software, which automatically disables unused GCLKs. The dynamic clock enable or disable feature allows internal logic to control clock enable or disable of the GCLKs.
When a clock network is disabled, all the logic fed by the clock network is in an off-state, reducing the overall power consumption of the device. This function is independent of the PLL and is applied directly on the clock network.
You can set the input clock sources and the clkena
signals for the GCLK multiplexers through the
ALTCLKCTRL IP core parameter editor in the Quartus Prime software.
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Clock Enable Signals
2-7
•
•
Related Information
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The MAX 10 devices support clkena
signals at the GCLK network level. This allows you to gate off the clock even when a PLL is used. After reenabling the output clock, the PLL does not need a resynchroniza‐ tion or relock period because the circuit gates off the clock at the clock network level. In addition, the PLL can remain locked independent of the clkena
signals because the loop-related counters are not affected.
Figure 2-5: clkena Implementation
clkena clkin
D Q clkena_out clk_out
Note: The clkena
circuitry controlling the
C0
output of the PLL to an output pin is implemented with two registers instead of a single register.
Figure 2-6: Example Waveform of clkena Implementation with Output Enable
The clkena
signal is sampled on the falling edge of the clock ( clkin
). This feature is useful for applications that require low power or sleep mode.
clkin clkena clk_out
The clkena
signal can also disable clock outputs if the system is not tolerant to frequency overshoot during PLL resynchronization.
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Internal Oscillator Architecture and Features
•
•
•
Related Information
Guideline: Clock Enable Signals
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MAX 10 devices have built-in internal ring oscillator with clock multiplexers and dividers. The internal ring oscillator operates up to 232 MHz which is not accessible. This operating frequency further divides down to slower frequencies.
By default internal oscillator is turned off in user mode. You can turn on the oscillator by asserting the oscena
signal in the Internal Oscillator IP core.
When the oscena
input signal is asserted, the oscillator is enabled and the output can be routed to the logic array through the clkout
output signal. When the oscena
signal is set low, the clkout
signal is constant high. You can analyze this delay using the TimeQuest timing analyzer.
The main purpose of a PLL is to synchronize the phase and frequency of the voltage-controlled oscillator
(VCO) to an input reference clock.
Figure 2-7: MAX 10 PLL High-Level Block Diagram
Each clock source can come from any of the two or four clock pins located on the same side of the device as the PLL.
PLL lock
LOCK circuit
CLKIN
4:1
Multiplexer pfdena
4:1
Multiplexer inclk0 inclk1
Clock
Switchover
Block
÷n clkswitch clkbad0 clkbad1 activeclock
PFD CP
LF
VCO
Range
Detector
VCO
8
÷2
(1)
8
÷C0
÷C1
÷C2
÷C3
÷C4
÷M
PLL output mux
GCLKs
ADC clock
(2)
External clock output
No Compensation; ZDB Mode
Source-Synchronous; Normal Mode
GCLK networks
Notes:
(1) This is the VCO post-scale counter K.
(2) Only counter C0 of PLL1 and PLL3 can drive the ADC clock.
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PLL Architecture
2-9
Phase-Frequency Detector (PFD)
The PFD has inputs from the feedback clock, f
FB
, and the input reference clock, f
REF
. The PLL compares down signal that determines whether the VCO needs to operate at a higher or lower frequency.
Charge Pump (CP)
If the charge pump receives a logic high on the up signal, current is driven into the loop filter. If the charge pump receives a logic high on the down signal, current is drawn from the loop filter.
Loop Filter (LF)
The loop filter converts the up and down signals from the PFD to a voltage that is used to bias the VCO.
The loop filter filters out glitches from the charge pump and prevents voltage overshoot, which minimizes jitter on the VCO.
Voltage-Controlled Oscillator (VCO)
The voltage from the charge pump determines how fast the VCO operates. The VCO is implemented as a four-stage differential ring oscillator. A divide counter,
M
, is inserted in the feedback loop to increase the
VCO frequency, f
VCO
, above the input reference frequency, f
REF
.
The VCO frequency is determined using the following equation: f
VCO
= f
REF
×
M
= f
IN
×
M
/
N
, where f
IN
is the input clock frequency to the PLL and
N
is the pre-scale counter.
The VCO frequency is a critical parameter that must be between 600 and 1,300 MHz to ensure proper operation of the PLL. The Quartus Prime software automatically sets the VCO frequency within the recommended range based on the clock output and phase shift requirements in your design.
Post-Scale Counters (
C
)
The VCO output can feed up to five post-scale counters (
C0
,
C1
,
C2
,
C3
, and
C4
). These post-scale counters allow the PLL to produce a number of harmonically-related frequencies.
Internal Delay Elements
The MAX 10 PLLs have internal delay elements to compensate for routing on the GCLK networks and
I/O buffers. These internal delays are fixed.
PLL Outputs
The MAX 10 PLL supports up to 5 GCLK outputs and 1 dedicated external clock output. The output frequency, f
OUT
, to the GCLK network or dedicated external clock output is determined using the following equation: f
REF
= f
IN
/
N
and f
OUT
= f
VCO
/
C
= (f
REF
×
M
)/
C
= (f
IN
×
M
)/(
N
×
C
), where
C
is the setting on the
C0
,
C1
,
C2
,
C3
, or
C4
counter.
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PLL Features
Table 2-4: MAX 10 PLL Features
Feature
C
output counters
M
,
N
,
C
counter sizes
Dedicated clock outputs
Dedicated clock input pins
Spread-spectrum input clock tracking
PLL cascading
Source synchronous compensation
No compensation mode
Normal compensation
Zero-delay buffer compensation
Phase shift resolution
Programmable duty cycle
Output counter cascading
Input clock switchover
User mode reconfiguration
Loss of lock detection
4:1 multiplexer
CLK
input selection
Support
5
1 to 512
(2)
1 single-ended or 1 differential
4 single-ended or 2 differential
Yes (3)
Through GCLK
Yes
Yes
Yes
Yes
Down to 96 ps increments
(4)
Yes
Yes
Yes
Yes
Yes
Yes
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The following figures show the physical locations of the PLLs. Every index represents one PLL in the device. The physical locations of the PLLs correspond to the coordinates in the Quartus Prime Chip
Planner.
(2)
(3)
(4)
C
counters range from 1 through 512 if the output clock uses a 50% duty cycle. For any output clocks using a non-50% duty cycle, the post-scale counters range from 1 through 256.
Only applicable if the input clock jitter is in the input jitter tolerance specifications.
The smallest phase shift is determined by the VCO period divided by eight. For degree increments, the
MAX 10 device family can shift all output frequencies in increments of at least 45°. Smaller degree increments are possible depending on the frequency and divide parameters.
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Figure 2-8: PLL Locations for 10M02 Device
Bank 8 PLL 2
(2)
PLL Locations
2-11
PLL 1
(1)
Bank 3
Notes:
(1) Available on all packages except V36 package.
(2) Available on U324 and V36packages only.
Figure 2-9: PLL Locations for 10M04 and 10M08 Devices
Bank 8 Bank 7 PLL 2
(2)
PLL 1
(1)
Bank 3 Bank 4
Notes:
(1) Available on all packages except V81 package.
(2) Available on F256, F484, U324, and V81 packages only.
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Clock Pin to PLL Connections
Figure 2-10: PLL Locations for 10M16, 10M25, 10M40 and 10M50 Devices
PLL 3
(1)
Bank 8 Bank 7 PLL 2
(1)
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PLL 1 Bank 3 Bank 4
OCT
PLL 4
(1)
Note:
(1) Available on all packages except E144 and U169 packages.
Table 2-5: MAX 10 Dedicated Clock Input Pin Connectivity to PLL
Dedicated Clock Pin
CLK[0,1][p,n]
CLK[2,3][p,n]
CLK[4,5][p,n]
CLK[6,7][p,n]
Table 2-6: MAX 10 PLL Counter Connectivity to the GCLK Networks
PLL Counter Output
PLL1_C0
PLL1_C1
PLL1_C2
PLL1_C3
PLL1_C4
PLL2_C0
PLL
PLL1
,
PLL3
PLL2
,
PLL4
PLL2
,
PLL3
PLL1
,
PLL4
GCLK
GCLK[0,3,15,18]
GCLK[1,4,16,19]
GCLK[0,2,15,17]
GCLK[1,3,16,18]
GCLK[2,4,17,19]
GCLK[5,8,10,13]
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PLL Counter Output
PLL2_C1
PLL2_C2
PLL2_C3
PLL2_C4
PLL3_C0
(5)
PLL3_C1
(5)
PLL3_C2
(5)
PLL3_C3
(5)
PLL3_C4
(5)
PLL4_C0
(5)
PLL4_C1
(5)
PLL4_C2
(5)
PLL4_C3
(5)
PLL4_C4
(5)
PLL Control Signals
GCLK
GCLK[6,9,11,14]
GCLK[5,7,10,12]
GCLK[6,8,11,13]
GCLK[7,9,12,14]
GCLK[0,3,10,13]
GCLK[1,4,11,14]
GCLK[0,2,10,12]
GCLK[1,3,11,13]
GCLK[2,4,12,14]
GCLK[5,8,15,18]
GCLK[6,9,16,19]
GCLK[5,7,15,17]
GCLK[6,8,16,18]
GCLK[7,9,17,19]
2-13
You can use the following three signals to observe and control the PLL operation and resynchronization.
pfdena
Use the pfdena
signal to maintain the last locked frequency so that your system has time to store its current settings before shutting down.
The pfdena
signal controls the PFD output with a programmable gate. The PFD circuit is enabled by default. When the PFD circuit is disabled, the PLL output does not depend on the input clock, and tends to drift outside of the lock window.
areset
The areset
signal is the reset or resynchronization input for each PLL. The device input pins or internal logic can drive these input signals.
When you assert the areset
signal, the PLL counters reset, clearing the PLL output and placing the PLL out of lock. The VCO is then set back to its nominal setting. When the areset
signal is deasserted, the
PLL resynchronizes to its input as it relocks.
The assertion of the areset
signal does not disable the VCO, but instead resets the VCO to its nominal value. The only time that the VCO is completely disabled is when you do not have a PLL instantiated in your design.
(5) This only applies to 10M16, 10M25, 10M40, and 10M50 devices.
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locked
The locked
output indicates that the PLL has locked onto the reference clock and the PLL clock outputs are operating at the desired phase and frequency set in the ALTPLL IP core parameter editor.
Altera recommends using the areset
and locked
signals in your designs to control and observe the status of your PLL. This implementation is illustrated in the following figure.
Figure 2-11: locked Signal Implementation
locked
PLL locked
VCC
D
DFF
Q areset
Note: If you use the SignalTap
®
II tool to probe the locked
signal before the D flip-flop, the locked signal goes low only when areset
is deasserted. If the areset
signal is not enabled, the extra logic is not implemented in the ALTPLL IP core.
•
•
•
Related Information
Guideline: PLL Control Signals
on page 3-2
PLL Control Signals Parameter Settings
on page 6-2
The MAX 10 PLLs support up to four different clock feedback modes. Each mode allows clock multiplica‐ tion and division, phase shifting, and programmable duty cycle.
The PLL fully compensates input and output delays only when you use the dedicated clock input pins associated with a given PLL as the clock sources.
•
•
•
•
For example, when using
PLL1
in normal mode, the clock delays from one of the following clock input pins to the PLL and the PLL clock output-to-destination register are fully compensated:
CLK0
CLK1
CLK2
CLK3
When driving the PLL using the GCLK network, the input and output delays might not be fully compensated in the Quartus Prime software.
Related Information
Operation Modes Parameter Settings
on page 6-1
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Source Synchronous Mode
2-15
If the data and clock arrive at the same time at the input pins, the phase relationship between the data and clock remains the same at the data and clock ports of any I/O element input register.
You can use this mode for source synchronous data transfers. Data and clock signals at the I/O element experience similar buffer delays as long as both signals use the same I/O standard.
Figure 2-12: Example of Phase Relationship Between Clock and Data in Source Synchronous Mode
Data pin
PLL reference
clock at input pin
Data at register
Clock at register
Source synchronous mode compensates for clock network delay, including any difference in delay between the following two paths:
• Data pin to I/O element register input
• Clock input pin to the PLL PFD input
For all data pins clocked by a source synchronous mode PLL, set the input pin to the register delay chain in the I/O element to zero in the Quartus Prime software. All data pins must use the PLL
COMPENSATED logic option in the Quartus Prime software.
In no compensation mode, the PLL does not compensate for any clock networks. This mode provides better jitter performance because clock feedback into the PFD does not pass through as much circuitry.
Both the PLL internal and external clock outputs are phase-shifted with respect to the PLL clock input.
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Figure 2-13: Example of Phase Relationship Between the PLL Clocks in No Compensation Mode
Phase Aligned
PLL Reference
Clock at the Input Pin
PLL Clock at the
Register Clock Port
(1)
,
(2)
External PLL Clock
Outputs
(2)
Notes:
(1) Internal clocks fed by the PLL are phase-aligned to each other.
(2) The PLL clock outputs can lead or lag the PLL input clocks. The PLL clock outputs lag the
PLL input clocks depending on the routine delays.
In normal mode, the PLL fully compensates the delay introduced by the GCLK network. An internal clock in normal mode is phase-aligned to the input clock pin. In this mode, the external clock output pin has a phase delay relative to the input clock pin. The Quartus Prime software timing analyzer reports any phase difference between the two.
Figure 2-14: Example of Phase Relationship Between the PLL Clocks in Normal Compensation Mode
Phase Aligned
PLL Reference
Clock at the Input pin
PLL Clock at the
Register Clock Port
External PLL Clock
Outputs
(1)
Note:
(1) The external clock output can lead or lag the PLL internal clock signals.
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Zero-Delay Buffer Mode
2-17
In zero-delay buffer (ZDB) mode, the external clock output pin is phase-aligned with the clock input pin for zero delay through the device. When using this mode, use the same I/O standard for the input clock and output clocks to ensure clock alignment at the input and output pins.
Figure 2-15: Example of Phase Relationship Between the PLL Clocks in ZDB Mode
Phase Aligned
PLL Reference Clock
at the Input Pin
PLL Clock at the Register Clock Port
External PLL Clock Output at the Output Pin
Each PLL in the MAX 10 devices supports one single-ended clock output or one differential clock output.
Only the
C0
output counter can feed the dedicated external clock outputs without going through the
GCLK. Other output counters can feed other I/O pins through the GCLK.
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PLL External Clock Output
Figure 2-16: PLL External Clock Output
PLL #
C0
C3
C4
C1
C2
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clkena 0
(1)
clkena 1
(1)
PLL #_CLKOUTp
(2)
PLL #_CLKOUTn
(2)
Notes:
(1) These external clock enable signals are available only when using the ALTCLKCTRL IP core.
(2) PLL#_CLKOUTp and PLL#_CLKOUTn pins are dual-purpose I/O pins that you can use as one single-ended
or one differential clock output.
Each pin of a differential output pair is 180° out of phase. To implement the 180° out-of-phase pin in a pin pair, the Quartus Prime software places a NOT gate in the design into the I/O element.
The clock output pin pairs support the following I/O standards:
• Same I/O standard as the standard output pins (in the top and bottom banks)
• LVDS
• LVPECL
• Differential high-speed transceiver logic (HSTL)
• Differential SSTL
The MAX 10 PLLs can drive out to any regular I/O pin through the GCLK. You can also use the external clock output pins as general-purpose I/O pins if you do not require any external PLL clocking.
Related Information
MAX 10 General Purpose I/O User Guide
Provides more information about the I/O standards supported by the PLL clock output pins.
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ADC Clock Input from PLL
Only the
C0
output counter from
PLL1
and
PLL3
can drive the ADC clock.
Counter
C0
has dedicated path to the ADC clock input.
2-19
The MAX 10 devices allow a spread-spectrum input with typical modulation frequencies. However, the device cannot automatically detect that the input is a spread-spectrum signal. Instead, the input signal looks like deterministic jitter at the input of the PLL.
The MAX 10 PLLs can track a spread-spectrum input clock if the input signal meets the following conditions:
• The input signal is within the input jitter tolerance specifications.
• The modulation frequency of the input clock is below the PLL bandwidth as specified in the Fitter report.
MAX 10 devices cannot generate spread-spectrum signals internally.
The programmable duty cycle allows PLLs to generate clock outputs with a variable duty cycle. This feature is supported on the PLL post-scale counters.
The duty cycle setting is achieved by a low and high time-count setting for the post-scale counters. To determine the duty cycle choices, the Quartus Prime software uses the frequency input and the required multiply or divide rate.
The post-scale counter value determines the precision of the duty cycle. The precision is defined as 50% divided by the post-scale counter value. For example, if the
C0
counter is 10, steps of 5% are possible for duty cycle choices between 5 to 90%.
Combining the programmable duty cycle with programmable phase shift allows the generation of precise nonoverlapping clocks.
Related Information
Post-Scale Counters (C0 to C4)
Provides more information about configuring the duty cycle of the post-scale counters in real time.
The PLL bandwidth is the measure of the PLL’s ability to track the input clock and its associated jitter.
The MAX 10 PLLs provide advanced control of the PLL bandwidth using the programmable characteris‐ tics of the PLL loop, including loop filter and charge pump. The 3-dB frequency of the closed-loop gain in the PLL determines the PLL bandwidth. The bandwidth is approximately the unity gain point for open loop PLL response.
•
Related Information
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•
•
Programmable Phase Shift
on page 4-6
Provides more information about the PLL components to update PLL bandwidth in real time.
Programmable Bandwidth Parameter Settings
on page 6-2
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The MAX 10 devices use phase shift to implement clock delays. You can phase shift the output clocks from the MAX 10 PLLs using one of the following methods:
• Fine resolution using VCO phase taps
• Coarse resolution using counter starting time
The VCO phase output and counter starting time are the most accurate methods of inserting delays.
These methods are purely based on counter settings, which are independent of process, voltage, and temperature.
The MAX 10 devices support dynamic phase shifting of VCO phase taps only. The phase shift is configu‐ rable for any number of times. Each phase shift takes about one scanclk
cycle, allowing you to implement large phase shifts quickly.
Fine Resolution Phase Shift
Fine resolution phase shifts are implemented by allowing any of the output counters (
C[4..0]
) or the
M counter to use any of the eight phases of the VCO as the reference clock. This allows you to adjust the delay time with a fine resolution. The following equation shows the minimum delay time that you can insert using this method.
Figure 2-17: Fine Resolution Phase Shift Equation
f
REF
in this equation is the input reference clock frequency
For example, if f counter settings.
REF
is 100 MHz,
N
= 1, and
M
= 8, then f
VCO
= 800 MHz, and Φ fine
= 156.25 ps. The PLL operating frequency defines this phase shift, a value that depends on the reference clock frequency and
The following figure shows an example of phase shift insertion using the fine resolution through VCO phase taps method. The eight phases from the VCO are shown and labeled for reference.
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Programmable Phase Shift
Figure 2-18: Example of Delay Insertion Using VCO Phase Output and Counter Delay Time
2-21
•
•
•
The observations in this example are as follows:
CLK0
CLK1
is based on 0° phase from the VCO and has the
C
value for the counter set to one.
signal is divided by four, two VCO clocks for high time and two VCO clocks for low time. based on the 135° phase tap from the VCO and has the
C
value for the counter set to one.
CLK1
is
CLK2
Φ
signal is also divided by four. In this case, the two clocks are offset by 3 Φ coarse
(two complete VCO periods).
fine
.
CLK2
is based on the
0° phase from the VCO but has the
C
value for the counter set to three. This creates a delay of two
1/8 t
VCO t
VCO
135
180
225
270
0
45
90
315
CLK0
CLK1
CLK2 t d0-1 t d0-2
Coarse Resolution Phase Shift
Coarse resolution phase shifts are implemented by delaying the start of the counters for a predetermined number of counter clocks.
Figure 2-19: Coarse Resolution Phase Shift Equation
C
in this equation is the count value set for the counter delay time—the initial setting in the PLL usage section of the compilation report in the Quartus Prime software. If the initial value is 1, C – 1 = 0° phase shift.
•
•
•
Related Information
Dynamic Phase Configuration Implementation
Dynamic Phase Configuration Counter Selection
Dynamic Phase Configuration with Advanced Parameters
on page 4-9
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•
•
Clock Switchover
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Dynamic Phase Configuration Parameter Settings
on page 6-4
Provides more information about the ALTPLL IP core parameter settings in the Quartus Prime software.
on page 7-1
Provides more information about the ALTPLL_RECONFIG IP core parameter settings in the Quartus
Prime software.
The clock switchover feature allows the PLL to switch between two reference input clocks. Use this feature for clock redundancy or for a dual-clock domain application where a system turns on the redundant clock if the previous clock stops running. The design can perform clock switchover automatically when the clock is no longer toggling or based on a user-controlled signal, clkswitch.
The following clock switchover modes are supported in MAX 10 PLLs:
• Automatic switchover—The clock sense circuit monitors the current reference clock. If the current reference clock stops toggling, the reference clock automatically switches to inclk0
or inclk1
clock.
• Manual clock switchover—The clkswitch
signal controls the clock switchover. When the clkswitch signal goes from logic low to high, and stays high for at least three clock cycles, the reference clock to the PLL switches from inclk0
to inclk1
, or vice-versa.
• Automatic switchover with manual override—This mode combines automatic switchover and manual clock switchover. When the clkswitch
signal goes high, it overrides the automatic clock switchover function. As long as the clkswitch
signal is high, any further switchover action is blocked.
•
•
Related Information
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Clock Switchover Parameter Settings
on page 6-3
The MAX 10 PLLs support a fully configurable clock switchover capability.
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Figure 2-20: Automatic Clock Switchover Circuit Block Diagram
Automatic Clock Switchover
This figure shows a block diagram of the automatic switchover circuit built into the PLL.
clkbad0 clkbad1 activeclock
clksw
Clock
Sense
Switchover
State
Machine clkswitch
(Provides Manual
Switchover Support) inclk0 inclk1
N
Counter
PFD muxout refclk fbclk
2-23
When the current reference clock is not present, the clock sense block automatically switches to the backup clock for PLL reference. You can select a clock source at the backup clock by connecting it to the inclk1
port of the PLL in your design.
The clock switchover circuit also sends out three status signals— clkbad[0]
, clkbad[1]
, and activeclock
—from the PLL to implement a custom switchover circuit in the logic array.
In automatic switchover mode, the clkbad[0]
and clkbad[1]
signals indicate the status of the two clock inputs. When the clkbad[0]
and clkbad[1]
signals are asserted, the clock sense block detects that the corresponding clock input has stopped toggling. These two signals are not valid if the frequency difference between inclk0
and inclk1
is greater than 20%.
The activeclock
signal indicates which of the two clock inputs ( inclk0
or inclk1
) is selected as the reference clock to the PLL. When the frequency difference between the two clock inputs is more than
20%, the activeclock
signal is the only valid status signal.
Note: Glitches in the input clock may cause the frequency difference between the input clocks to be more than 20%.
When the current reference clock to the PLL stops toggling, use the switchover circuitry to automatically switch from inclk0
to inclk1
that runs at the same frequency. This automatic switchover can switch back and forth between the inclk0
and inclk1
clocks any number of times when one of the two clocks fails and the other clock is available.
For example, in applications that require a redundant clock with the same frequency as the reference clock, the switchover state machine generates a signal ( clksw
) that controls the multiplexer select input.
In this case, inclk1
becomes the reference clock for the PLL.
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When using automatic clock switchover mode, the following requirements must be satisfied:
• Both clock inputs must be running when the FPGA is configured.
• The period of the two clock inputs differ by no more than 20%.
If the current clock input stops toggling while the other clock is also not toggling, switchover is not initiated and the clkbad[0..1]
signals are not valid. If both clock inputs do not have the same frequency, but their period difference is within 20%, the clock sense block detects when a clock stops toggling.
However, the PLL might lose lock after the switchover completes and needs time to relock.
Note: Altera recommends resetting the PLL using the areset
signal to maintain the phase relationships between the PLL input and output clocks when using clock switchover.
Figure 2-21: Example of Automatic Switchover After Loss of Clock Detection
This figure shows an example waveform of the switchover feature in automatic switchover mode. In this example, the inclk0
signal remains low. After the inclk0
signal remains low for approximately two clock cycles, the clock sense circuitry drives the clkbad[0]
signal high. Since the reference clock signal is not toggling, the switchover state machine controls the multiplexer through the clksw
signal to switch to the backup clock, inclk1
.
inclk0 inclk1
(1)
muxout clkbad0 clkbad1 activeclock
Note:
(1) Switchover is enabled on the falling edge of inclk0 or inclk1, depending on which clock is available. In this figure,
switchover is enabled on the falling edge of inclk1.
In automatic switchover with manual override mode, you can use the clkswitch
signal for user- or system-controlled switch conditions. You can use this mode for same-frequency switchover, or to switch between inputs of different frequencies.
For example, if inclk0
is 66 MHz and inclk1
is 200 MHz, you must control the switchover using the clkswitch
signal. The automatic clock sense circuitry cannot monitor clock input ( inclk0
and inclk1
) frequencies with a frequency difference of more than 20%.
This feature is useful when clock sources originate from multiple cards on the backplane, requiring a system-controlled switchover between frequencies of operation.
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Manual Clock Switchover
2-25
You must choose the backup clock frequency and set the
M
,
N
, and
C
counters so that the VCO operates within the recommended frequency range.
The following figure shows a clock switchover waveform controlled by the clkswitch
signal. In this case, both clock sources are functional and inclk0
is selected as the reference clock. The clkswitch
signal goes high, which starts the switchover sequence. On the falling edge of inclk0
, the counter’s reference clock, muxout
, is gated off to prevent clock glitching. On the falling edge of inclk1
, the reference clock multiplexer switches from inclk0
to inclk1
as the PLL reference. The activeclock
signal is asserted to indicate the clock that is currently feeding the PLL, which is inclk1
.
In automatic override with manual switchover mode, the activeclock
signal mirrors the clkswitch signal. Since both clocks are still functional during the manual switch, neither clkbad
signal goes high.
Because the switchover circuit is positive-edge sensitive, the falling edge of the clkswitch
signal does not cause the circuit to switch back from inclk1
to inclk0
. When the clkswitch
signal goes high again, the process repeats.
Figure 2-22: Example of Clock Switchover Using the clkswitch
(Manual) Control
inclk0 inclk1 muxout clkswitch activeclock clkbad0 clkbad1
To initiate a manual clock switchover event, both inclk0 and inclk1 must be running when the clkswitch signal goes high.
The clkswitch
signal and automatic switch work only if the clock being switched to is available. If the clock is not available, the state machine waits until the clock is available.
In manual clock switchover mode, the clkswitch
signal controls whether inclk0
or inclk1
is selected as the input clock to the PLL. By default, inclk0
is selected.
A clock switchover event is initiated when the clkswitch
signal transitions from logic low to logic high, and is being held high for at least three inclk
cycles. You must bring the clkswitch
signal back to low again to perform another switchover event. If you do not require another switchover event, you can leave the clkswitch
signal in a logic high state after the initial switch. Pulsing the clkswitch
signal high for at least three inclk
cycles performs another switchover event.
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If inclk0
and inclk1
have different frequencies and are always running, the minimum amount of time for which clkswitch
signal is high must be greater than or equal to three of the slower-frequency inclk0 and inclk1
cycles.
Related Information
Two PLLs are cascaded to each other through the clock network. If your design cascades PLLs, the source
(upstream) PLL must have a low-bandwidth setting and the destination (downstream) PLL must have a high-bandwidth setting.
The MAX 10 PLLs support post-scale counter cascading to create counters larger than 512. This is implemented by feeding the output of one
C
counter into the input of the next
C
counter.
Figure 2-23: Counter-to-Counter Cascading
VCO Output
C0
VCO Output
VCO Output
VCO Output
VCO Output
VCO Output
C1
C2
C3
C4
When cascading counters to implement a larger division of the high-frequency VCO clock, the cascaded counters behave as one counter with the product of the individual counter settings.
For example, if
C0
= 4 and
C1
= 2, the cascaded value is
C0
x
C1
= 8.
The Quartus Prime software automatically sets all the post-scale counter values for cascading in the configuration file. Post-scale counter cascading cannot be performed using PLL reconfiguration.
The PLLs use several divide counters and different VCO phase taps to perform frequency synthesis and phase shifts. In MAX 10 PLLs, you can reconfigure both counter settings and phase shift the PLL output clock in real time. You can also change the charge pump and loop filter components, which dynamically affects the PLL bandwidth.
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PLL Reconfiguration
2-27
The following PLL components are configurable in real time:
• Pre-scale counter (
N
)
• Feedback counter (
M
)
• Post-scale output counters (
C0
-
C4
)
• Charge pump current (I
CP
)
• Loop filter components (R, C)
You can use these PLL components to update the following settings in real time without reconfiguring the entire FPGA:
• Output clock frequency
• PLL bandwidth
• Phase shift
The ability to reconfigure the PLL in real time is useful in applications that may operate in multiple frequencies. It is also useful in prototyping environments, allowing you to sweep PLL output frequencies and dynamically adjust the output clock phase.
For instance, a system generating test patterns is required to generate and send patterns at 75 or 150 MHz, depending on the requirements of the device under test. Reconfiguring the PLL components in real time allows you to switch between two such output frequencies in a few microseconds.
You can also use this feature to adjust clock-to-out (t settings.
CO
) delays in real time by changing the PLL output clock phase shift. This approach eliminates the need to regenerate a configuration file with the new PLL
Figure 2-24: PLL Reconfiguration Scan Chain
This figure shows the dynamic adjustment of the PLL counter settings by shifting their new settings into a serial shift register chain or scan chain. Serial data shifts to the scan chain via the scandata
port, and shift registers are clocked by scanclk
. The maximum scanclk
frequency is 100 MHz. After shifting the last bit of data, asserting the configupdate
signal for at least one scanclk
clock cycle synchronously updates the
PLL configuration bits with the data in the scan registers.
FVCO from M counter from N counter
PFD LF/K/CP VCO scandata scanclkena configupdate inclk scandataout scandone scanclk
/C4 /C3
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The counter settings are updated synchronously to the clock frequency of the individual counters.
Therefore, not all counters update simultaneously.
The dynamic reconfiguration scheme uses configuration files, such as the Hexadecimal-format file (.hex) or the Memory Initialization file (.mif). These files are used together with the ALTPLL_RECONFIG IP core to perform the dynamic reconfiguration.
•
•
•
•
Related Information
Guideline: .mif Streaming in PLL Reconfiguration
PLL Dynamic Reconfiguration Implementation
PLL Dynamic Reconfiguration Parameter Settings
on page 6-4
Provides more information about the ALTPLL IP core parameter settings in the Quartus Prime software.
on page 7-1
Provides more information about the ALTPLL_RECONFIG IP core parameter settings in the Quartus
Prime software.
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Altera recommends using the clkena
signals when switching the clock source to the PLLs or GCLK. The recommended sequence is as follows:
1. Disable the primary output clock by deasserting the clkena
signal.
2. Switch to the secondary clock using the dynamic select signals of the clock control block.
3. Allow some clock cycles of the secondary clock to pass before reasserting the clkena
signal. The exact number of clock cycles to wait before enabling the secondary clock depends on your design. You can build a custom logic to ensure a glitch-free transition when switching between different clock sources.
•
•
•
Related Information
on page 5-2
The following guidelines describe the restrictions associated with the signal sources that can drive the inclk
input:
• You must use the inclk
ports that are consistent with the clkselect
ports.
• When you are using multiple input sources, the inclk
ports can only be driven by the dedicated clock input pins and the PLL clock outputs.
• If the clock control block feeds any inclk
port of another clock control block, both clock control blocks must be able to be reduced to a single clock control block of equivalent functionality.
• When you are using the glitch-free switchover feature, the clock you are switching from must be active.
If the clock is not active, the switchover circuit cannot transition from the clock you originally selected.
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2015 Altera Corporation. All rights reserved. ALTERA, ARRIA, CYCLONE, ENPIRION, MAX, MEGACORE, NIOS, QUARTUS and STRATIX words and logos are trademarks of Altera Corporation and registered in the U.S. Patent and Trademark Office and in other countries. All other words and logos identified as trademarks or service marks are the property of their respective holders as described at www.altera.com/common/legal.html
. Altera warrants performance of its semiconductor products to current specifications in accordance with Altera's standard warranty, but reserves the right to make changes to any products and services at any time without notice. Altera assumes no responsibility or liability arising out of the application or use of any information, product, or service described herein except as expressly agreed to in writing by Altera. Altera customers are advised to obtain the latest version of device specifications before relying on any published information and before placing orders for products or services.
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3-2
Internal Oscillator Design Considerations
You cannot drive the PLLs with internal oscillator.
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You must include the areset
signal in your designs if one of the following conditions is true:
• PLL reconfiguration or clock switchover is enabled in your design.
• Phase relationships between the PLL input clock and output clocks must be maintained after a loss-oflock condition.
• The input clock to the PLL is toggling or unstable at power-up.
• The areset
signal is asserted after the input clock is stable and within specifications.
Related Information
on page 2-13
To comply with simultaneous switching noise (SSN) design guideline, Altera recommends that you do not use unterminated I/O in the same bank as the input clock signal to the PLL.
Related Information
Guidelines: Clock and Asynchronous Control Input Signal
Provides more information about using I/O connectivity restrictions.
The lock time of a PLL is the amount of time required by the PLL to attain the target frequency and phase relationship after device power-up, after a change in the PLL output frequency, or after resetting the PLL.
A PLL might lose lock for a number of reasons, such as the following causes:
• Excessive jitter on the input clock.
• Excessive switching noise on the clock inputs of the PLL.
• Excessive noise from the power supply, causing high output jitter and possible loss of lock.
• A glitch or stopping of the input clock to the PLL.
• Resetting the PLL by asserting the areset
port of the PLL.
• An attempt to reconfigure the PLL might cause the
M
counter,
N
counter, or phase shift to change, causing the PLL to lose lock. However, changes to the post-scale counters do not affect the PLL locked signal.
• PLL input clock frequency drifts outside the lock range specification.
• The PFD is disabled using the pfdena
port. When this happens, the PLL output phase and frequency tend to drift outside of the lock window.
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Guideline: Output Clocks
3-3
The ALTPLL IP core allows you to monitor the PLL locking process using a lock signal named locked and also allows you to set the PLL to self-reset on loss of lock.
Each MAX 10 PLL supports up to five output clocks. You can use the output clock port as a core output clock or an external output clock port. The core output clock feeds the FPGA core and the external output clock feeds the dedicated pins on the FPGA.
The ALTPLL IP core does not have a dedicated output enable port. You can disable the PLL output using the areset
signal to disable the PLL output counters.
Consider the following guidelines when cascading PLLs:
• Set the primary PLL to low bandwidth to help filter jitter. Set the secondary PLL to high bandwidth to track the jitter from the primary PLL. You can view the Quartus Prime software compilation report file to ensure the PLL bandwidth ranges do not overlap. If the bandwidth ranges overlap, jitter peaking can occur in the cascaded PLL scheme.
Note: You can get an estimate of the PLL deterministic jitter and static phase error (SPE) by using the
TimeQuest Timing Analyzer in the Quartus Prime software. Use the SDC command derive_clock_uncertainty
to generate a report titled
PLLJ_PLLSPE_INFO.txt
in your project directory. Then, use set_clock_uncertainty
command to add jitter and SPE values to your clock constraints.
• Keep the secondary PLL in a reset state until the primary PLL has locked to ensure the phase settings are correct on the secondary PLL.
• You cannot connect any of the inclk
ports of any PLLs in a cascaded scheme to the clock outputs from PLLs in the cascaded scheme.
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Use the following guidelines to design with clock switchover in PLLs:
• Clock loss detection and automatic clock switchover requires that the frequency difference between inclk0
and inclk1
is within 20% range. Failing to meet this requirement causes the clkbad[0]
and clkbad[1]
signals to function improperly.
• When using manual clock switchover, the frequency difference between inclk0
and inclk1
can be more than 20%. However, differences between the two clock sources (frequency, phase, or both) can cause the PLL to lose lock. Resetting the PLL ensures that the correct phase relationships are maintained between the input and output clocks.
• Both inclk0
and inclk1
must be running when the clkswitch
signal goes high to start the manual clock switchover event. Failing to meet this requirement causes the clock switchover to malfunction.
• Applications that require a clock switchover feature and a small frequency drift must use a lowbandwidth PLL. When referencing input clock changes, the low-bandwidth PLL reacts slower than a high-bandwidth PLL. When the switchover happens, the low-bandwidth PLL propagates the stoppage of the clock to the output at a slower speed than the high-bandwidth PLL. The low-bandwidth PLL filters out jitter on the reference clock. However, be aware that the low-bandwidth PLL also increases lock time.
• After a switchover occurs, there might be a finite resynchronization period for the PLL to lock onto a new clock. The exact amount of time it takes for the PLL to relock depends on the PLL configuration.
• The phase relationship between the input clock to the PLL and output clock from the PLL is important in your design. Assert areset
for 10 ns after performing a clock switchover. Wait for the locked signal
(or gated lock) to go high before reenabling the output clocks from the PLL.
• Disable the system during switchover if the system is not tolerant of frequency variations during the
PLL resynchronization period. You can use the clkbad[0]
and clkbad[1]
status signals to turn off the
PFD ( pfdena
= 0) so that the VCO maintains its last frequency. You can also use the switchover state machine to switch over to the secondary clock. After enabling the PFD, the output clock enable signals
( clkena
) can disable clock outputs during the switchover and resynchronization period. After the lock indication is stable, the system can reenable the output clock or clocks.
• The VCO frequency gradually decreases when the primary clock is lost and then increases as the VCO locks onto the secondary clock, as shown in the following figure. After the VCO locks onto the secondary clock, some overshoot can occur (an over-frequency condition) in the VCO frequency.
Figure 3-1: VCO Switchover Operating Frequency
Primary Clock Stops Running
Frequency Overshoot
Switchover Occurs
VCO Tracks Secondary Clock
ΔFvco
•
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•
Guideline: .mif Streaming in PLL Reconfiguration
Clock Switchover Parameter Settings
on page 6-3
3-5
Consider the following guidelines when using
.mif
streaming in PLL reconfiguration:
• 10M02 devices do not support
.mif
streaming in PLL reconfiguration due to flash size limitation. Altera recommends using an external flash.
• 10M04, 10M08, 10M16, 10M25, 10M40, and 10M50 devices only support
.mif
streaming in single image mode. Altera recommends using an external flash for dual image mode. The MAX 10 devices do not support using both dual image mode and PLL reconfiguration with
.mif
simultaneously.
Related Information
on page 2-26
scandone
signal must be low before the second PLL reconfiguration. For scandone
signal to go low, PLL areset
signal must be asserted.
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The clock control block (ALTCLKCTRL) IP core is a clock control function for configuring the clock control block.
The common applications of the ALTCLKCTRL IP core are as follows:
• Dynamic clock source selection—When using the clock control block, you can select the dynamic clock source that drives the global clock network.
• Dynamic power-down of a clock network—The dynamic clock enable or disable feature allows internal logic to power down the clock network. When a clock network is powered down, all the logic fed by that clock network is not toggling, thus reducing the overall power consumption of the device.
The ALTCLKCTRL IP core provides the following features:
• Supports clock control block operation mode specifications
• Supports specification of the number of input clock sources
• Provides an active high clock enable control input
•
•
•
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The ALTPLL IP core specifies the PLL circuitry. You can use this IP core to configure the PLL types, operation modes, and advanced features of the PLL.
4
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Expanding the PLL Lock Range
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•
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The PLL lock range is between the minimum (Freq min lock parameter) and maximum (Freq min lock parameter) input frequency values for which the PLL can achieve lock. Changing the input frequency might cause the PLL to lose lock, but if the input clock remains within the minimum and maximum frequency specifications, the PLL is able to achieve lock. The Quartus Prime software shows these input frequency values in the PLL Summary report located under the Resource Section of the Fitter folder in the
Compilation Report.
The Quartus Prime software does not necessarily pick values for the PLL parameters to maximize the lock range. For example, when you specify a 75 MHz input clock in the ALTPLL parameter editor, the actual
PLL lock range might be between 70 MHz to 90 MHz. If your application requires a lock range of 50 MHz to 100 MHz, the default lock range of this PLL is insufficient.
For devices that support clock switchover in PLLs, you can use the ALTPLL IP core parameter editor to maximize the lock range.
To extract valid parameter values to maximize your PLL lock range, perform the following steps:
1. In the schematic editor, double-click the ALTPLL instance in your design to open the ALTPLL parameter editor.
2. On the General/Modes page, for What is the frequency of the inclk0 input?, type the value of the low end of your desired PLL lock range.
For example, if your application requires a lock range of 50 MHz to 100 MHz, type
50
MHz.
3. On the Inputs/Lock page, turn on Create output file(s) using the 'Advanced' PLL parameters.
4. On the Clock switchover page, turn on Create an 'inclk1' input for a second input clock and enter the high end of your lock range as the frequency for inclk1
.
For example, if your application requires a lock range of 50 MHz to 100 MHz, type
100
MHz.
5. Set the rest of the parameters in the remaining pages of the ALTPLL IP core parameter editor.
6. Compile your project and note the lock range shown in the PLL Summary report. If it is satisfactory, note all of the values for the PLL from this report, such as the
M
value,
N
value, charge pump current, loop filter resistance, and loop filter capacitance.
7. In the schematic editor, double-click the ALTPLL instance in your design to open the ALTPLL parameter editor.
8. On the Clock switchover page, turn off Create an 'inclk1' input for a second input clock.
9. Click Finish to update the PLL wrapper file.
10.In a text editor, open the PLL wrapper file. Modify all of the values for the parameters listed in step 6.
Save the changes.
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• If the wrapper file is in Verilog format, go to the defparam section.
• If the wrapper file is in VHDL HDL, go to the Generic Map section.
11.Compile your project.
12.Check the PLL Summary report to confirm that the PLL lock range meets your requirements. The modified PLL should have the desired lock range.
If your input clock frequency is too close to the end of the desired PLL lock range—for example the low end of the desired lock range is 50 MHz and the input clock frequency is 50 MHz, the PLL might not maintain lock when the input clock has jitter or the frequency drifts below 50 MHz. You may choose to expand your PLL lock range to ensure your expected input clock frequency is further from the end of the range. For this example, you can enter 45 MHz and 105 MHz to ensure that your target lock range of
50 MHz to 100 MHz is within the PLL lock range.
The Quartus Prime software prompts an error message if it is unable to implement your preferred lock range using this procedure. Therefore, you have to look into other options, such as PLL reconfiguration to support your input frequency range.
An advanced level of control is also possible for precise control of the PLL loop filter characteristics. This level allows you to explicitly select the following advanced parameters:
• Charge pump current ( charge_pump_current
)
• Loop filter resistance ( loop_filter_r
)
• Loop filter capacitance( loop_filter_c
)
This option is intended for advanced users who know the exact details of their PLL configuration. You can use this option if you understand the parameters well enough to set them optimally. The files generated are not intended to be reused by the ALTPLL IP core parameter editor. After the ALTPLL IP core output files are specified using the advanced parameters, the Quartus Prime compiler cannot change them. For example, the compiler cannot perform optimization. Thus, your design cannot benefit from improved algorithms of the compiler. The Quartus Prime compiler cannot select better settings or change some settings that the ALTPLL IP core parameter editor finds to be incompatible with your design.
The parameter settings to generate output files using advanced PLL parameters are located on the Inputs/
Lock page of the ALTPLL IP core parameter editor.
Turn on Create output file(s) using the 'Advanced' PLL parameters to enable the feature.
When you turn on this option, the generated output files contain all of the initial counter values used in the PLL. You can use these values for functional simulation in a third-party simulator.
These parameter settings create no additional top-level ports.
•
•
•
Related Information
on page 2-19
on page 4-6
Provides more information about the PLL components to update PLL bandwidth in real time.
Programmable Bandwidth Parameter Settings
on page 6-2
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To reconfigure the PLL counters, perform the following steps:
1. Assert the scanclkena
signal at least one scanclk
cycle prior to shifting in the first bit of scandata
(
Dn
).
2. Shift the serial data ( scandata
) into the scan chain on the second rising edge of scanclk
.
3. After all 144 bits have been scanned into the scan chain, deassert the scanclkena
signal to prevent inadvertent shifting of bits in the scan chain.
4. Assert the configupdate
signal for one scanclk
cycle to update the PLL counters with the contents of the scan chain.
The scandone
signal goes high indicating that the PLL is being reconfigured. A falling edge indicates that the PLL counters have been updated with new settings.
5. Reset the PLL using the areset
signal if you make any changes to the
M
,
N
, post-scale output
C counters, or the I
CP
, R, and C settings.
6. You can repeat steps 1 through 5 to reconfigure the PLL any number of times.
Figure 4-1: PLL Reconfiguration Scan Chain Functional Simulation
scandata Dn
D0
LSB scanclk scanclkena scandataout
Dn_old
D0_old Dn configupdate scandone areset
When reconfiguring the counter clock frequency, you cannot reconfigure the corresponding counter phase shift settings using the same interface. You can reconfigure phase shifts in real time using the dynamic phase shift reconfiguration interface. If you wish to keep the same nonzero phase shift setting
(for example, 90°) on the clock output, you must reconfigure the phase shift after reconfiguring the counter clock frequency.
Related Information
on page 2-26
You can configure the multiply or divide values and duty cycle of the post-scale counters in real time.
Each counter has an 8-bit high time setting and an 8-bit low time setting. The duty cycle is the ratio of output high or low time to the total cycle time, which is the sum of the two.
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Scan Chain
4-5
The post-scale counters have two control bits:
•
• rbypass
—For bypassing the counter rselodd
—For selecting the output clock duty cycle
When the rbypass
bit is set to 1, it bypasses the counter, resulting in a division by one. When this bit is set to 0, the PLL computes the effective division of the VCO output frequency based on the high and low time counters. The PLL implements this duty cycle by transitioning the output clock from high-to-low on the rising edge of the VCO output clock.
For example, if the post-scale divide factor is 10, the high and low count values are set to 5 and 5 respectively, to achieve a 50–50% duty cycle. However, a 4 and 6 setting for the high and low count values, respectively, would produce an output clock with 40–60% duty cycle.
The rselodd
bit indicates an odd divide factor for the VCO output frequency with a 50% duty cycle. The
PLL implements this duty cycle by transitioning the output clock from high-to-low on a falling edge of the
VCO output clock.
For example, if the post-scale divide factor is 3, the high and low time count values are 2 and 1 respectively, to achieve this division. This implies a 67%–33% duty cycle. If you need a 50%–50% duty cycle, you must set the rselodd
control bit to 1 to achieve this duty cycle despite an odd division factor.
When you set rselodd
= 1, subtract 0.5 cycles from the high time and add 0.5 cycles to the low time.
The calculation for the example is shown as follows:
•
• High time count = 2 cycles
• Low time count = 1 cycle rselodd
= 1 effectively equals:
• High time count = 1.5 cycles
• Low time count = 1.5 cycles
• Duty cycle = (1.5/3)% high time count and (1.5/3)% low time count
Related Information
The MAX 10 PLLs have a 144-bit scan chain.
Table 4-1: PLL Component Reprogramming Bits
C4
(6)
C3
C2
C1
C0
Block Name
Counter
16
16
16
16
16
Number of Bits
Control Bit
2 (7)
2
(7)
2
(7)
2 (7)
2 (7)
Total
18
18
18
18
18
(6)
(7)
LSB bit for
C4
low-count value is the first bit shifted into the scan chain.
These two control bits include rbypass
, for bypassing the counter, and rselodd
, for selecting the output clock duty cycle.
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Charge Pump and Loop Filter
Block Name
M
N
Charge Pump
Loop Filter
(8)
Total number of bits
Counter
16
16
9
9
Figure 4-2: PLL Component Scan Chain Order
DATAIN
MSB
LF CP
LSB
Number of Bits
Control Bit
2 (7)
2 (7)
0
0
N M C0
Total
18
18
9
9
144
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DATAOUT C4 C3 C2 C1
Figure 4-3: PLL Post-Scale Counter Scan Chain Bit Order
HB
0
HB
1
HB
2
HB
3
HB
4
HB
5
HB
6
DATAOUT
LB
0
LB
1
LB
2
LB
3
LB
4
LB
5
LB
6
LB
7
HB
7
LB
8
HB
8
LB
9
HB
9 rbypass rselodd
You can reconfigure the following settings to update the PLL bandwidth in real time:
• Charge pump (I
CP
)
• Loop filter resistor (R)
• Loop filter capacitor (C)
Table 4-2: Charge Pump Bit Control
CP[2]
0
0
0
CP[1]
0
0
1
CP[0]
0
1
1
Setting (Decimal)
0
1
3
DATAIN
(8) MSB bit for loop filter is the last bit shifted into the scan chain.
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CP[2]
1
CP[1]
1
Table 4-3: Loop Filter Resistor Value Control
CP[0]
LFR[4]
0
1
1
1
0
0
0
1
1
1
1
LFR[3]
1
0
0
0
0
0
0
1
1
1
1
Table 4-4: Loop Filter High Frequency Capacitor Control
LFR[2]
0
0
0
1
0
0
1
0
0
1
1
LFR[1]
0
0
1
0
0
1
0
0
1
0
1
1
LFR[0]
0
0
1
0
0
1
0
0
1
0
0
Bypassing PLL Counter
Setting (Decimal)
7
4-7
Setting (Decimal)
8
16
19
20
0
3
4
24
27
28
30
LFC[1]
0
0
1
LFC[0]
0
1
1
Setting (Decimal)
0
1
3
•
•
•
Related Information
on page 2-19
Programmable Bandwidth with Advanced Parameters
Programmable Bandwidth Parameter Settings
on page 6-2
Bypassing a PLL counter results in a multiplification (
M
counter) or a division (
N
,
C0
to
C4
counters) factor of one.
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Dynamic Phase Configuration Implementation
Table 4-5: PLL Counter Settings
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Description
PLL counter bypassed
PLL counter not bypassed
X
X
X
X
X
X
PLL Scan Chain Bits [0..8] Settings
LSB
X X X X
X X X X
X
X
MSB
1 (9)
0 (9)
To bypass any of the PLL counters, set the bypass bit to 1. The values on the other bits are ignored.
To perform one dynamic phase shift step, perform the following steps:
1. Set
PHASEUPDOWN
and
PHASECOUNTERSELECT
as required.
2. Assert
PHASESTEP
for at least two
SCANCLK
cycles. Each
PHASESTEP
pulse allows one phase shift.
3. Deassert
PHASESTEP
after
PHASEDONE
goes low.
4. Wait for
PHASEDONE
to go high.
5. Repeat steps 1 through 4 as many times as required to perform multiple phase shifts.
PHASEUPDOWN
and
PHASECOUNTERSELECT
signals are synchronous to
SCANCLK
and must meet the t requirements with respect to the
SCANCLK
edges.
su
and t h
You can repeat dynamic phase-shifting indefinitely. For example, in a design where the VCO frequency is set to 1,000 MHz and the output clock frequency is set to 100 MHz, performing 40 dynamic phase shifts
(each one yields 125 ps phase shift) results in shifting the output clock by 180º, which is a phase shift of 5 ns.
Figure 4-4: Dynamic Phase Shift Timing Diagram
SCANCLK
PHASESTEP
PHASEUPDOWN
PHASECOUNTERSELECT
PHASEDONE a b c d
PHASEDONE goes low synchronous with SCANCLK
The
PHASESTEP
signal is latched on the negative edge of
SCANCLK
(a,c) and must remain asserted for at least two
SCANCLK
cycles. Deassert
PHASESTEP
after
PHASEDONE
goes low.
(9) Bypass bit
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On the second
SCANCLK
rising edge (b,d) after
PHASESTEP
is latched, the values of
PHASEUPDOWN
and
PHASECOUNTERSELECT
are latched. The PLL starts dynamic phase-shifting for the specified counters and in the indicated direction.
The
PHASEDONE
signal is deasserted synchronous to
SCANCLK
at the second rising edge (b,d) and remains low until the PLL finishes dynamic phase-shifting. Depending on the VCO and
SCANCLK
frequencies,
PHASEDONE
low time may be greater than or less than one
SCANCLK
cycle.
You can perform another dynamic phase-shift after the
PHASEDONE
signal goes from low to high. Each
PHASESTEP
pulse enables one phase shift. The
PHASESTEP
pulses must be at least one
SCANCLK
cycle apart.
•
•
•
•
•
Related Information
Dynamic Phase Configuration Parameter Settings
on page 6-4
Provides more information about the ALTPLL IP core parameter settings in the Quartus Prime software.
on page 7-1
Provides more information about the ALTPLL_RECONFIG IP core parameter settings in the Quartus
Prime software.
PLL Dynamic Reconfiguration Parameter Settings
on page 6-4
Provides more information about the ALTPLL IP core parameter settings in the Quartus Prime software.
on page 7-1
Provides more information about the ALTPLL_RECONFIG IP core parameter settings in the Quartus
Prime software.
Table 4-6: Phase Counter Select Mapping
PLL Counter Selection
All output counters
M
counter
C0
counter
C1
counter
C2
counter
C3
counter
C4
counter
PHASECOUNTERSELECT [2]
1
1
1
0
0
0
0
[1]
0
0
1
0
0
1
1
[0]
0
1
0
0
1
0
1
Related Information
on page 2-20
The finest phase shift step resolution you can get in the ALTPLL IP core is 1/8 of the VCO period. If the
VCO frequency is at the lower end of the supported VCO range, the phase shift step resolution might be larger than preferred for your design.
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You can modify your phase shift resolution using the dynamic phase reconfiguration feature of the PLL. If you want to modify the phase shift resolution without the dynamic phase reconfiguration feature enabled, perform the following steps:
1. Create an ALTPLL instance. Make sure you specify the speed grade of your target device and the PLL type.
2. On the PLL Reconfiguration page, turn on Create optional inputs for dynamic phase reconfigura‐
tion and Enable phase shift step resolution.
3. On the Output Clocks page, set your desired phase shift for each required output clock. Note all the internal PLL settings shown.
4. On the Bandwidth/SS page, click More Details to see the internal PLL settings. Note all of the settings shown.
5. On the Inputs/Lock page, turn on Create output file(s) using the ‘Advanced’ PLL Parameters.
6. Return to the PLL Reconfiguration page and turn off Create Optional Inputs for Dynamic Phase
Reconfiguration.
7. Click Finish to generate the PLL instantiation file(s).
When using Advanced Parameters, the PLL wrapper file (<
ALTPLL_instantiation_name
>
.v
or
<
ALTPLL_instantiation_name
>
.vhd
) is written in a format that allows you to identify the PLL parameters. The parameters are listed in the Generic Map section of the VHDL file, or in the defparam
section of the Verilog file.
8. Open your PLL instantiation wrapper file and locate either the Generic Map or the defparam
section.
9. Modify the settings to match the settings that you noted in steps 3 and 4.
10.Save the PLL instantiation wrapper file and compile your design.
11.Verify that the output clock frequencies and phases are correct in the PLL Usage report located under the Resource section of the Fitter folder in the Compilation Report.
By using this technique, you can apply valid PLL parameters as provided by the ALTPLL IP core parameter editor to optimize the settings for your design.
Alternatively, you can leave the dynamic phase reconfiguration option enabled and tie the relevant input ports— phasecounterselect[3..0]
, phaseupdown
, phasestep
, and scanclk
—to constants, if you prefer not to manually edit the PLL wrapper file using the Advanced PLL Parameters option.
Related Information
on page 2-20
The ALTPLL_RECONFIG IP core implements reconfiguration logic to facilitate dynamic real-time reconfiguration of PLLs. You can use the IP core to update the output clock frequency, PLL bandwidth, and phase shifts in real time, without reconfiguring the entire FPGA.
Use the ALTPLL_RECONFIG IP core in designs that must support dynamic changes in the frequency and phase shift of clocks and other frequency signals. The IP core is also useful in prototyping environments because it allows you to sweep PLL output frequencies and dynamically adjust the output clock phase.
You can also adjust the clock-to-output (t
CO operation requires dynamic phase-shifting.
) delays in real-time by changing the output clock phase shift.
This approach eliminates the need to regenerate a configuration file with the new PLL settings. This
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Project Management Best Practices
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4-11
For details about the resource usage and performance of the ALTPLL_RECONFIG IP core, refer to the compilation reports in the Quartus Prime software.
To view the compilation reports for the ALTPLL_RECONFIG IP core in the Quartus Prime software, follow these steps:
1. On the Processing menu, click Start Compilation to run a full compilation.
2. After compiling the design, on the Processing menu, click Compilation Report.
3. In the Table of Contents browser, expand the Fitter folder by clicking the “+” icon.
4. Under Fitter, expand Resource section, and select Resource Usage Summary to view the resource usage information.
5. Under Fitter, expand Resource section, and select Resource Utilization by Entity to view the resource utilization information.
The Internal Oscillator IP core specifies the internal oscillator frequencies for the devices.
•
•
•
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Creating Version-Independent IP and Qsys Simulation Scripts
Create simulation scripts that do not require manual updates for software or IP version upgrades.
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Guidelines for efficient management and portability of your project and IP files.
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Table 5-1: ALTCLKCTRL IP Core Parameters for MAX 10 Devices
This table lists the IP core parameters applicable to MAX 10 devices.
Parameter Value
How do you want to use the ALTCLKCTRL
For global clock, or
For external path
Decription
Specify the ALTCLKCTRL buffering mode. You can select from the following modes:
• For global clock—Allows a clock signal to reach all parts of the chip with the same amount of skew; you can select input port clkselect
to switch between the four clock inputs.
• For external path—Represents the clock path from the outputs of the PLL to the dedicated clock output pins; only one clock output is accepted.
How many clock inputs would you like?
1, 2, 3, or 4
Specify the number of input clock sources for the clock control block. You can specify up to four clock inputs.
You can change the number of clock inputs only if you choose For global clock option.
Create ‘ena’ port to enable or disable the clock network driven by this buffer
On or Off Turn on this option if you want to create an active high clock enable signal to enable or disable the clock network.
5
©
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. Altera warrants performance of its semiconductor products to current specifications in accordance with Altera's standard warranty, but reserves the right to make changes to any products and services at any time without notice. Altera assumes no responsibility or liability arising out of the application or use of any information, product, or service described herein except as expressly agreed to in writing by Altera. Altera customers are advised to obtain the latest version of device specifications before relying on any published information and before placing orders for products or services.
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ALTCLKCTRL Ports and Signals
Parameter
Ensure glitch-free switchover implementa‐ tion
Value
On or Off
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2015.11.02
Decription
Turn on this option to implement a glitch-free switchover when you use multiple clock inputs.
You must ensure the currently selected clock is running before switching to another source. If the selected clock is not running, the glitch-free switchover implementa‐ tion will not be able to switch to the new clock source.
By default, the clkselect
port is set to
00
. A clock must be applied to inclk0x
for the values on the clkselect
ports to be read.
•
•
•
•
Related Information
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Global Clock Network Power Down
Guideline: Clock Enable Signals
on page 2-6
Table 5-2: ALTCLKCTRL Input Ports for MAX 10 Devices
Port Name
clkselect[] ena
Condition
Optional
Optional
Description
Input that dynamically selects the clock source to drive the clock network that is driven by the clock buffer.
Input port
[1 DOWNTO 0]
wide.
If omitted, the default is GND.
•
•
If this signal is connected, only the global clock network can be driven by this clock control block.
The following list shows the signal selection for the binary value:
00
— inclk[0]
01
— inclk[1]
Clock enable of the clock buffer.
If omitted, the default value is V
CC
.
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Port Name
inclk[]
Condition
Required
ALTCLKCTRL Ports and Signals
5-3
Description
Clock input of the clock buffer.
Input port
[1 DOWNTO 0]
wide.
You can specify up to two clock inputs, inclk[1..0]
.
Clock pins, clock outputs from the PLL, and core signals can drive the inclk[]
port.
Multiple clock inputs are only supported for the global clock networks.
Table 5-3: ALTCLKCTRL Output Ports for MAX 10 Devices
outclk
Port Name Condition
Required Output of the clock buffer.
•
•
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Guideline: Clock Enable Signals
Description
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The following tables list the IP core parameters applicable to MAX 10 devices.
You can set the operation mode for PLL in the General/Modes page of the ALTPLL IP core parameter editor.
Table 6-1: Operation Mode Parameter Editor Settings
Parameter
Which device speed grade will you be using?
Value
Any, 7, or 8
Description
Specify the speed grade if you are not already using a device with the fastest speed. The lower the number, the faster the speed grade.
Specify the frequency of the input clock signal.
What is the frequency of the inclock0 input?
Use the feedback path inside the PLL
Which output clock will be compensated for?
—
In normal mode, In
source-synchronous compensation
mode, In zero-delay
buffer mode, or
With no compensation
Specify which operation mode to use.
For source-synchronous mode and zero-delay buffer mode, you must make PLL Compensation assignments using the Assignment Editor in addition to setting the appropriate mode in the IP core. The assignment allows you to specify an output pin as a compensation target for a PLL in zero-delay buffer mode, or to specify an input pin or group of input pins as compensation targets for a PLL in source-synchronous mode.
C0
,
C1
,
C2
,
C3
, or
C4
Specify which PLL output port to compensate.
The drop down list contains all output clock ports for the selected device. The correct output clock selection depends on the operation mode that you select.
For example, for normal mode, select the core output clock. For zero-delay buffer mode, select the external output clock.
6
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2015 Altera Corporation. All rights reserved. ALTERA, ARRIA, CYCLONE, ENPIRION, MAX, MEGACORE, NIOS, QUARTUS and STRATIX words and logos are trademarks of Altera Corporation and registered in the U.S. Patent and Trademark Office and in other countries. All other words and logos identified as trademarks or service marks are the property of their respective holders as described at www.altera.com/common/legal.html
. Altera warrants performance of its semiconductor products to current specifications in accordance with Altera's standard warranty, but reserves the right to make changes to any products and services at any time without notice. Altera assumes no responsibility or liability arising out of the application or use of any information, product, or service described herein except as expressly agreed to in writing by Altera. Altera customers are advised to obtain the latest version of device specifications before relying on any published information and before placing orders for products or services.
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6-2
PLL Control Signals Parameter Settings
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The parameter settings for the control signals are located on the Inputs/Lock page of the ALTPLL IP core parameter editor.
Turn on the control signal you want to create from the options available.
Related Information
on page 2-13
You can configure the bandwidth of the ALTPLL IP core on the Bandwidth/SS page of the ALTPLL IP core parameter editor.
Table 6-2: Bandwidth Configuration Parameter Editor Settings
Parameter
Auto
Preset
Value
—
Low
Medium
High
Description
The ALTPLL parameter editor chooses the best possible bandwidth values to achieve the desired PLL settings. In some cases, you can get a bandwidth value outside the Low and High preset range.
You can use the programmable bandwidth feature with the clock switchover feature to get the PLL output settings that you desire.
You must set the bandwidth to Auto if you want to enable the spread-spectrum feature.
PLL with a low bandwidth has better jitter rejection but a slower lock time.
PLL with a medium bandwidth has a balance between lock time and jitter rejection.
PLL with a high bandwidth has a faster lock time but tracks more jitter.
The table on the right in the Bandwidth/SS page shows the values of the following components:
•
• Charge pump current
• Loop filter resistance
• Loop filter capacitance
M
counter
These parameter settings create no additional top-level ports.
•
•
•
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Programmable Bandwidth with Advanced Parameters
on page 4-6
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Clock Switchover Parameter Settings
The parameter settings for clock switchover feature are located on the Clock switchover page of the
ALTPLL IP core parameter editor.
6-3
Table 6-3: Clock Switchover Parameter Editor Settings
Parameter
Create an 'inclk1' input for a second input clock
Value
On or Off
—
Description
Turn on this option to enable the switchover feature.
The inclk0
signal is by default the primary input clock signal of the ALTPLL IP core.
Select this option for manual clock switchover mode.
Create a 'clkswitch' input to manually select between the input clocks
Allow PLL to automati‐ cally control the switching between input clocks
Create a 'clkswitch' input to dynamically control the switching between input clocks
Perform the input clock switchover after
(number) input clock cycles
Create an 'activeclock' output to indicate the input clock being used
Create a 'clkbad' output for each input clock
—
On or Off
On or Off
On or Off
On or Off
Select this option for automatic clock switchover mode.
The automatic switchover is initiated during loss of lock or when the inclk0
signal stops toggling.
Turn on this option for automatic clock switchover with manual override mode.
The automatic switchover is initiated during loss of lock or when the clkswitch
signal is asserted.
Turn on this option to specify the number of clock cycles to wait before the PLL performs the clock switchover.
The allowed number of clock cycles to wait is devicedependent.
Turn on this option to monitor which input clock signal is driving the PLL.
When the current clock signal is inclk0
, the activeclock
signal is low. When the current clock signal is inclk1
, the activeclock
signal is high.
Turn on this option to monitor when the input clock signal has stopped toggling.
The clkbad0
signal monitors the inclk0
signal. The clkbad1
signal monitors the inclk1
signal.
The clkbad0
signal goes high when the inclk0
signal stops toggling. The clkbad1
signal goes high when the inclk1
signal stops toggling. The clkbad
signals remain low when the input clock signals are toggling.
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PLL Dynamic Reconfiguration Parameter Settings
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The parameter settings for the normal dynamic reconfiguration scheme are located on the PLL Reconfi‐
guration page of the ALTPLL IP core parameter editor.
Table 6-4: PLL Dynamic Reconfiguration Parameter Editor Settings
Parameter
Create optional inputs for dynamic reconfigu‐ ration
Initial Configuration
File
Additional Configura‐ tion File(s)
Value
On or Off
—
—
•
•
Related Information
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Dynamic Phase Configuration Implementation
The parameter settings to enable the dynamic phase configuration feature are located on the PLL
Reconfiguration page of the ALTPLL IP core parameter editor.
Table 6-5: Dynamic Phase Configuration Parameter Editor Settings
Parameter
Create optional inputs for dynamic phase reconfiguration
Value
On or Off
Description
Turn on this option to enable all the PLL reconfigura‐ tion ports for this instantiation— scanclk
, scanclkena
, scandata
, scandone
, scandataout
, and configupdate
.
Specify the location of the configuration file that is used to initialize the ALTPLL_RECONFIG IP core.
Specify additional configuration file. This file might contain additional settings for the PLL, or might be used to initialize the ALTPLL_RECONFIG IP core.
Enable phase shift step resolution edit
On or Off
Description
•
•
•
•
•
Turn on this option to enable the dynamic phase configuration feature. The following ports are created: phasecounterselect[2..0] phaseupdown phasestep scanclk phasedone
Turn on this option to modify the value for Phase shift
step resolution(ps) for each individual PLL output clock on the Output Clocks page.
By default, the finest phase shift resolution value is 1/8 of the VCO period. If the VCO frequency is at the lower end of the supported VCO range, the phase shift resolution might be larger than preferred for your design. Use this option to fine tune the phase shift step resolution.
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Related Information
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Output Clocks Parameter Settings
6-5
The Output Clocks page of the ALTPLL parameter editor contains the parameter settings of the clock output signals. You can configure the c0
, c1
, c2
, c3
, and c4
clock output signals of the ALTPLL IP core.
Each option has the following two columns:
• Requested settings—The settings that you want to implement.
• Actual settings—The settings closest values that can be implemented in the PLL circuit to best approxi‐ mate the requested settings.
Use the values in the actual settings column as a guide to adjust the requested settings. If the requested settings for one of the output clocks cannot be approximated, the ALTPLL IP core parameter editor produces a warning message at the top of every page.
Table 6-6: Output Clocks Parameter Editor Settings
Parameter
Use this clock
Value
On or Off
—
Description
Turn on this option to generate an output clock port in your ALTPLL instance.
The output clock port that is to be compensated for is enabled by default. It cannot be disabled, unless you select a different output clock port to be compensated for.
Specify the frequency of the output clock signal.
Enter output clock frequency
Enter output clock parameters
Clock multiplication factor
Clock division factor
Clock phase shift
—
—
—
—
Specify the the output clock parameters instead of the frequency.
Specify the clock multiplication factor of the signal.
Specify the clock division factor of the signal.
Set the programmable phase shift for an output clock signals.
The smallest phase shift is 1/8 of VCO period. For degree increments, the maximum step size is 45 degrees. You can set smaller steps using the Clock
multiplication factor and Clock division factor options.
For example, if the post-scale counter is 32, the smallest phase shift step is 0.1°. The up and down buttons let you cycle through phase shift values. Alternatively, you can enter a number in the phase shift field manually instead of using the buttons.
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ALTPLL Ports and Signals
Parameter
Clock duty cycle (%)
Per Clock Feasibility
Indicators
Value
—
—
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Set the duty cycle of the output clock signal.
Indicate output clocks that contain unachievable settings.
The output clock name in red is the name of the clock with unachievable settings. The clock listed in green has no settings issues, and the grayed-out names are the unselected output clocks. You must adjust the requested settings for the affected output clocks to resolve the warning messages.
The ALTPLL IP core parameter editor calculates the simplest fraction, and displays it in the actual settings column. You can use the copy button to copy values from the actual settings to the requested settings.
Figure 6-1: PLL Output Clock Frequency
For example, if the input clock frequency is 100 MHz, and the requested multiplication and division factors are 205 and 1025 respectively, the output clock frequency is calculated as 100 × 205/1025=20 MHz.
The actual settings reflect the simplest fraction—the actual multiplication factor is 1, and the actual division factor is 5.
Table 6-7: ALTPLL Input Ports for MAX 10 Devices
areset
Port Name
(10)
Condition
Optional clkswitch configupdate
Optional
Optional
Description
Resets all counters to initial values, including the
GATE_LOCK_COUNTER
parameter.
The control input port to dynamically toggle between clock input ports ( inclk0
and inclk1 ports), or to manually override the automatic clock switchover.
You should create the clkswitch
port if only the inclk1
port is created.
Dynamic full PLL reconfiguration.
(10) Replace brackets, [], in the port name with integer to get the exact name. For example, inclk0
and inclk1
.
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inclk[]
Port Name
(10)
pfdena phasecounterselect[] phasestep phaseupdown scanclk scanclkena scandata
Condition
Required
Optional
Optional
Optional
Optional
Optional
Optional
Optional
ALTPLL Ports and Signals
6-7
Description
The clock inputs that drive the clock network.
If more than one inclk[]
port is created, you must use the clkselect
port to specify which clock is used. The inclk0
port must always be connected; connect other clock inputs if switching is necessary.
A dedicated clock pin or PLL output clock can drive this port.
Enables the phase frequency detector (PFD).
When the PFD is disabled, the PLL continues to operate regardless of the input clock. Because the
PLL output clock frequency does not change for some time, you can use the pfdena
port as a shutdown or cleanup function when a reliable input clock is no longer available.
Specifies counter select. You can use the phasecounterselect[2..0]
bits to select either the
M
or one of the
C
counters for phase adjustment.
One address map to select all
C
counters. This signal is registered in the PLL on the rising edge of
SCANCLK
.
Specifies dynamic phase shifting. Logic high enables dynamic phase shifting.
Specifies dynamic phase shift direction.
1
= UP,
0
=
DOWN. Signal is registered in the PLL on the rising edge of
SCANCLK
.
Input clock port for the serial scan chain.
Free-running clock from core used in combination with
PHASESTEP
to enable or disable dynamic phase shifting. Shared with
SCANCLK
for dynamic reconfi‐ guration.
Clock enable port for the serial scan chain.
Contains the data for the serial scan chain.
(10) Replace brackets, [], in the port name with integer to get the exact name. For example, inclk0
and inclk1
.
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ALTPLL Ports and Signals
Table 6-8: ALTPLL Output Ports for MAX 10 Devices
Port Name
(11)
activeclock
Condition
Optional c[] clkbad[]
Required
Optional
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Description
Specifies which clock is the primary reference clock when the clock switchover circuit initiates.
If the inclk0
is in use, the activeclock
port goes low. If the inclk1
is in use, the activeclock
port goes high.
You can set the PLL to automatically initiate the clock switchover when the primary reference clock is not toggling correctly, or you can manually initiate the clock switchover using the clkswitch input port.
The clock output of the PLL.
clkbad1
and clkbad0
ports check for input clock toggling.
If the inclk0
port stops toggling, the clkbad0
port goes high. If the inclk1
port stops toggling, the clkbad1
port goes high.
(11) Replace the brackets,
[]
, in the port name with an integer to get the exact name (for example, c0
and c1
).
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locked
Port Name
(11)
phasedone scandataout scandone
Condition
Optional
Optional
Optional
Optional
ALTPLL Ports and Signals
6-9
Description
This output port acts as an indicator when the PLL has reached phase-locked. The locked
port stays high as long as the PLL is locked, and stays low when the PLL is out-of-lock.
The number of cycles needed to gate the locked signal is based on the PLL input clock. The gatedlock circuitry is clocked by the PLL input clock. The maximum lock time for the PLL is provided in the
MAX 10 Device Datasheet
.
Take the maximum lock time of the PLL and divide it by the period of the PLL input clock. The result is the number of clock cycles needed to gate the locked
signal.
The lock signal is an asynchronous output of the
PLL. The PLL lock signal is derived from the reference clock and feedback clock feeding the phase frequency detector (PFD) as follows:
• Reference clock = Input Clock/
N
• Feedback clock = VCO/
M
The PLL asserts the locked
port when the phases and frequencies of the reference clock and feedback clock are the same or within the lock circuit tolerance. When the difference between the two clock signals goes beyond the lock circuit tolerance, the PLL loses lock.
This output port indicates that dynamic phase reconfiguration is completed.
When phasedone
signal is asserted, it indicates to core logic that the phase adjustment is complete and
PLL is ready to act on a possible second adjustment pulse. This signal asserts based on internal PLL timing and deasserts on rising edge of
SCANCLK
.
The data output for the serial scan chain.
You can use the scandataout
port to determine when PLL reconfiguration completes. The last output is cleared when reconfiguration completes.
This output port indicates that the scan chain write operation is initiated.
The scandone
port goes high when the scan chain write operation initiates, and goes low when the scan chain write operation completes.
(11) Replace the brackets,
[]
, in the port name with an integer to get the exact name (for example, c0
and c1
).
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Table 7-1: ALTPLL_RECONFIG IP Core Parameters for MAX 10 Devices
This table lists the IP core parameters applicable to MAX 10 devices.
Page Parameter
Currently Selected
Device Family
Which scan chain type will you be using?
Value
—
—
Description
Specifies the chosen device family.
The scan chain is a serial shift register chain that is used to store settings. It acts like a cache. When you assert the reconfig
signal, the PLL is reconfigured with the values in the cache. The type of scan chain must follow the type of PLL to be reconfigured. The scan chain type has a default value of Top/
Bottom.
Parameter
Settings
Do you want to specify the initial value of the scan chain?
No, leave it
blank,
Yes, use this file for the content data
Specifies the initial value of the scan chain.
Select No, leave it blank to not specify a file or select Yes, use this file for the content
data to browse for a
.hex
or
.mif
file.
The option to initialize from a ROM is not available. However, you can choose to add ports to write to the scan chain from an external ROM during runtime by turning on
Add ports to write to the scan chain from
external ROM during run time.
Add ports to write to the scan chain from external ROM during run time
On, Off Turn on this option to take advantage of cycling multiple configuration files, which are stored in external ROMs during user mode.
7
©
2015 Altera Corporation. All rights reserved. ALTERA, ARRIA, CYCLONE, ENPIRION, MAX, MEGACORE, NIOS, QUARTUS and STRATIX words and logos are trademarks of Altera Corporation and registered in the U.S. Patent and Trademark Office and in other countries. All other words and logos identified as trademarks or service marks are the property of their respective holders as described at www.altera.com/common/legal.html
. Altera warrants performance of its semiconductor products to current specifications in accordance with Altera's standard warranty, but reserves the right to make changes to any products and services at any time without notice. Altera assumes no responsibility or liability arising out of the application or use of any information, product, or service described herein except as expressly agreed to in writing by Altera. Altera customers are advised to obtain the latest version of device specifications before relying on any published information and before placing orders for products or services.
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101 Innovation Drive, San Jose, CA 95134
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7-2
ALTPLL_RECONFIG Ports and Signals
Page
EDA
Summary
Parameter
Simulation Libraries
Generate netlist
—
Value
—
On, Off
—
UG-M10CLKPLL
2015.11.02
Description
Specifies the libraries for functional simulation.
Turn on this option to generate synthesis area and timing estimation netlist.
Specifies the types of files to be generated. A gray checkmark indicates a file that is automatically generated; an unchecked check box indicates an optional file. Choose from the following types of files:
• AHDL Include file (<
function name
>
.inc
)
• VHDL component declaration file
(<
function name
>
.cmp
)
• Quartus Prime symbol file (<
function name
>
.bsf
)
• Instantiation template file (<
function name
>_
inst.v
or <
function name
>_
inst.vhd
)
• Verilog HDL black box file (<
function name
>_
bb.v
)
If the Generate netlist option is turned on, the file for that netlist is also available
(<
function name
>_
syn.v
).
•
•
•
•
Related Information
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Dynamic Phase Configuration Implementation
Table 7-2: ALTPLL_RECONFIG Input Ports for MAX 10 Devices
clock
Port Name Condition
Required
Description
Clock input for loading individual parameters. This signal also clocks the PLL during reconfiguration.
The clock input port must be connected to a valid clock.
Refer to the
MAX 10 Device Datasheet
for the clock f
MAX
.
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reset
Port Name
data_in[] counter_type[] counter_param[]
Condition
Required
Optional
Optional
Optional
ALTPLL_RECONFIG Ports and Signals
7-3
Description
Asynchronous reset input to the IP core.
Altera recommends that you reset this IP core before first use to guarantee that it is in a valid state. However, it does power up in the reset state. This port must be connected.
Data input that provides parameter value when writing parameters.
This 9-bit input port provides the data to be written to the scan cache during a write operation. The bit width of the counter parameter to be written determines the number of bits of data_in[]
that are read into the cache.
For example, the low bit count of the
C0
counter is 8-bit wide, so data_in[7..0]
is read to the correct cache location. The bypass mode for the
C0
counter is 1-bit wide, so data_in[0]
is read for the value of this parameter.
If omitted, the default value is 0.
Specifies the counter type.
An input port in the form of a 4-bit bus that selects which counter type should be selected for the corresponding operation (read, write, or reconfig).
Refer to the counter_type[3..0]
settings table for the mapping between the counter_type
value and the physical counter to be set.
Specifies the parameter for the value specified in the counter_type
port.
An input port in the form of a 3-bit bus that selects which parameter for the given counter type should be updated.
The mapping to each parameter type and the corresponding parameter bit-width are defined in the counter_param[3..0]
settings table.
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ALTPLL_RECONFIG Ports and Signals
Port Name
read_param
Condition
Optional write_param
Optional
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Description
Reads the parameter specified with the counter_type
and counter_param
ports from cache and fed to the data_ out[]
port.
When asserted, the read_param
signal indicates that the scan cache should be read and fed to data_out[]
. The bit location of the scan cache and the number of bits read and sent to data_out[]
depend on the counter_type and counter_param
values. The read_param
signal is sampled at the rising clock edge. If the read_param
signal is asserted, the parameter value is read from the cache.
Assert the read_param
signal for 1 clock cycle only to prevent the parameter from being read twice.
The busy
signal is asserted on the rising clock edge following the assertion of the read_param
signal. While the parameter is read, the busy
signal remains asserted.
After the busy
signal is deasserted, the value on data_ out[]
is valid and the next parameter can be loaded.
While the busy
signal is asserted, the value on data_ out[]
is not valid.
When the read_param
signal is asserted, the busy
signal is only asserted on the following rising edge of the clock and not on the same clock cycle as the read_param
signal.
Writes the parameter specified with the
counter_type and counter_param
ports to the cache with the value specified on the data_in[]
port.
When asserted, the write_param
signal indicates that the value on data_in[]
should be written to the parameter specified by counter_type[]
and counter_param[]
. The number of bits read from the data_in[]
port depends on the parameter. The write_param
signal is sampled at the rising clock edge. If the write_param
signal is asserted, the parameter value is written to the cache. Assert the write_param
signal for 1 clock cycle only to prevent the parameter from being written twice.
The busy
signal is asserted on the rising clock edge following the assertion of the write_param
signal. While the parameter is being written, the busy
signal remains asserted and input to data_in[]
is ignored. After the busy
signal is deasserted, the next parameter can be written.
When the write_param
signal is asserted, the busy
signal is only asserted on the following rising edge of the clock.
The busy
signal is not asserted on the same clock cycle as the write_param
signal.
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Port Name
reconfig pll_areset_in pll_scandone pll_scandataout
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Condition
Required
Optional
Optional
Required
ALTPLL_RECONFIG Ports and Signals
7-5
Description
Specifies that the PLL should be reconfigured with the
PLL settings specified in the current cache.
When asserted, the reconfig
signal indicates that the PLL should be reconfigured with the values in the cache. The reconfig
signal is sampled at the rising clock edge. If the reconfig
signal is asserted, the cached settings are loaded in the PLL. Assert the reconfig
signal for 1 clock cycle only to prevent reloading the PLL configuration. The busy
signal is asserted on the rising clock edge following the assertion of the reconfig
signal. While the PLL is being loaded, the busy
signal remains asserted. After the busy
signal is deasserted, the parameter values can be modified again.
During and after reconfiguration, the scan chain data cache remains unchanged. This allows you to easily create a new set of reconfiguration settings using only one parameter.
If write_param
has not been asserted since the previous assertion of reconfig
, the entire scan chain is shifted in to the PLL again.
When the reconfig
signal is asserted, the busy
signal is only asserted on the following rising edge of the clock.
The busy
signal is not asserted on the same clock cycle as the reconfig
signal.
Input signal indicating that the PLL should be reset.
When asserted, the pll_areset_in
signal indicates the
PLL IP core should be reset. This port defaults to 0 if left unconnected. When using the ALTPLL_RECONFIG IP core in a design, you cannot reset the PLL in any other way. You must use this IP core port to manually reset the
PLL.
Input port for the ALTPLL_RECONFIG IP core. This port is driven by the PLL's scandone
output signal and determines when the PLL is reconfigured.
Input port driven by the scandataout
signal from the
ALTPLL IP core. Use this port to read the current configuration of the ALTPLL IP core. This input port holds the ALTPLL scan data output from the dynamically reconfigurable bits. The pll_scandataout
port must be connected to the scandataout
port of the PLL. The activity on this port can only be observed when the reconfig
signal is asserted.
Altera Corporation
7-6
ALTPLL_RECONFIG Ports and Signals
Table 7-3: ALTPLL_RECONFIG Output Ports for MAX 10 Devices
Port Name
data_out[]
Condition
Optional busy pll_areset pll_configupdate pll_scanclk
Optional
Required
Optional
Required
Description
UG-M10CLKPLL
2015.11.02
Data read from the cache when read_param
is asserted.
This 9-bit output bus provides the parameter data to the user. When the read_param
signal is asserted, the values on counter_type[]
and counter_param[]
determine the parameter value that is loaded from cache and driven on the data_out[]
bus. When the IP core deasserts the busy signal, the appropriate bits of the bus (for example,
[0]
or
[3..0]
) hold a valid value.
Indicates that the PLL is reading or writing a parameter to the cache, or is configuring the PLL.
While the busy
signal is asserted, no parameters can be read or written, and no reconfiguration can be initiated.
Changes to the IP core can be made only when the busy signal is not asserted. The signal goes high when the read_param
, write_param
, or reconfig
input port is asserted, and remains high until the specified operation is complete. In the case of a reconfiguration operation, the busy
signal remains high until the pll_areset
signal is asserted and then deasserted.
Drives the areset
port on the PLL to be reconfigured.
The pll_areset
port must be connected to the areset port of the ALTPLL IP core for the reconfiguration to function correctly. This signal is active high. The pll_ areset
is asserted when pll_areset_in
is asserted, or, after reconfiguration, at the next rising clock edge after the scandone
signal goes high. If you use the ALTPLL_
RECONFIG IP core, use the pll_areset
output port to drive the PLL areset
port.
Drives the configupdate
port on the PLL to be reconfig‐ ured. When asserted, the pll_configupdate
port loads selected data to PLL configuration latches. The signal is asserted after the final data bit is sent out.
Drives the scanclk
port on the PLL to be reconfigured.
For information about the maximum scanclk
frequency for the various devices, refer to the respective device handbook.
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Port Name
pll_scanclkena pll_scandata
Condition
Optional
Required
ALTPLL_RECONFIG Counter Settings
Description
This port acts as a clock enable for the scanclk
port on the PLL to be reconfigured.
Reconfiguration begins on the first rising edge of pll_ scanclk
after pll_scanclkena
assertion. On the first falling edge of pll_scanclk
, after the deassertion of the pll_scanclkena
signal, the IP core stops scanning data to the PLL.
Drives the scandata
port on the PLL to be reconfigured.
This output port from the IP core holds the scan data input to the PLL for the dynamically reconfigurable bits.
The pll_scandata
port sends scandata
to the PLL. Any activity on this port can only be observed when the reconfig
signal is asserted.
7-7
Table 7-4: counter_type[3..0]
Settings for MAX 10 Devices
Counter Selection
N
M
CP/LF
VCO
C0
C1
C2
C3
C4
Illegal value
Illegal value
Illegal value
Illegal value
Illegal value
Illegal value
Illegal value
Binary
0111
1000
1001
1010
1011
1100
1101
1110
1111
0000
0001
0010
0011
0100
0101
0110
Decimal
11
12
13
14
15
7
8
9
10
3
4
5
6
0
1
2
ALTPLL_RECONFIG IP Core References
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7-8
ALTPLL_RECONFIG Counter Settings
Table 7-5: counter_param[2..0]
Settings for MAX 10 Devices
Regular counters (
C4
CP/LF
VCO
M
)
Counter Type
/
N
counters
C0
-
Counter Param
High count
Low count
Bypass
Mode (odd/even division)
Charge pump unused
Charge pump current
Loop filter unused
Loop filter resistor
Loop filter capacitance
VCO post scale
High count
Low count
Bypass
Mode (odd/even division)
Nominal count
•
•
For even nominal count, the counter bits are automatically set as follows: high_count low_count
=
Nominalcount
/2
=
Nominalcount
/2
For odd nominal count, the counter bits are automatically set as follows:
•
• high_count
= (
Nominalcount
+ 1)/2 low_count
=
Nominalcount
- high_count
• odd/even division bit = 1
For nominal count = 1, bypass bit = 1.
Binary
000
000
001
100
000
100
001
010
101
111
000
001
100
101
101
Decimal
0
0
1
4
5
7
0
4
1
2
4
5
5
0
1
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Width (bits)
1
8
8
1
1
9
3
1
5
2
1
1
5
8
8
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Table 8-1: Internal Oscillator IP Core Parameters for MAX 10 Devices
This table lists the IP core parameters applicable to MAX 10 devices.
Parameter
Clock Frequency
Value
55, 116
Decription
Specify the clock frequency for simulation. If not specified, the default value is 55 MHz.
Table 8-2: Internal Oscillator Input Port for MAX 10 Devices
oscena
Port Name Condition
Required
Description
Input control signal to turn on or turn off the internal oscillator.
Table 8-3: Internal Oscillator Output Port for MAX 10 Devices
clkout
Port Name Condition
Optional
Description
Output clock from the internal oscillator.
8
©
2015 Altera Corporation. All rights reserved. ALTERA, ARRIA, CYCLONE, ENPIRION, MAX, MEGACORE, NIOS, QUARTUS and STRATIX words and logos are trademarks of Altera Corporation and registered in the U.S. Patent and Trademark Office and in other countries. All other words and logos identified as trademarks or service marks are the property of their respective holders as described at www.altera.com/common/legal.html
. Altera warrants performance of its semiconductor products to current specifications in accordance with Altera's standard warranty, but reserves the right to make changes to any products and services at any time without notice. Altera assumes no responsibility or liability arising out of the application or use of any information, product, or service described herein except as expressly agreed to in writing by Altera. Altera customers are advised to obtain the latest version of device specifications before relying on any published information and before placing orders for products or services.
www.altera.com
101 Innovation Drive, San Jose, CA 95134
ISO
9001:2008
Registered
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A
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Date
November 2015
June 2015
May 2015
December 2014
September 2014
Version Changes
2015.11.02 • Removed the topics about the IP catalog and parameter editor, generating IP cores, and the files generated by the IP core, and added a link to
Introduction to Altera IP Cores
.
• Changed instances of
Quartus II
to
Quartus Prime
.
2015.06.12 Added connectivity restriction guideline to the PLL design considera‐ tions.
2015.05.04 Rearranged the fine resolution phase shift equation.
2014.12.15 • Corrected the statement that if you do not use the dedicated clock input pins for clock input, you can also use them as generalpurpose input or output pins.
• Added description in Internal Oscillator Architecture and Features to state that the internal ring oscillator operates up to 232 MHz and this frequency is not accessible.
• Added connectivity restrictions guideline for internal oscillator.
• Added Internal Oscillator IP Core parameter: Clock Frequency.
• Moved Internal Oscillator Frequencies table from Internal
Oscillator Architecture and Features chapter to MAX 10 FPGA
Device Datasheet.
2014.09.22 Initial release.
©
2015 Altera Corporation. All rights reserved. ALTERA, ARRIA, CYCLONE, ENPIRION, MAX, MEGACORE, NIOS, QUARTUS and STRATIX words and logos are trademarks of Altera Corporation and registered in the U.S. Patent and Trademark Office and in other countries. All other words and logos identified as trademarks or service marks are the property of their respective holders as described at www.altera.com/common/legal.html
. Altera warrants performance of its semiconductor products to current specifications in accordance with Altera's standard warranty, but reserves the right to make changes to any products and services at any time without notice. Altera assumes no responsibility or liability arising out of the application or use of any information, product, or service described herein except as expressly agreed to in writing by Altera. Altera customers are advised to obtain the latest version of device specifications before relying on any published information and before placing orders for products or services.
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9001:2008
Registered
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TOC-2
Contents
MAX 10 General Purpose I/O User Guide Archives......................................... A-1
Altera Corporation
Document Revision History for MAX 10 General Purpose I/O User Guide...
TOC-3
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1
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The MAX
®
10 general purpose I/O (GPIO) system consists of the I/O elements (IOE) and the Altera
GPIO Lite IP core.
• The IOEs contain bidirectional I/O buffers and I/O registers located in I/O banks around the periphery of the device.
• The Altera GPIO Lite IP core supports the GPIO components and features, including double data rate
I/O (DDIO), delay chains, I/O buffers, control signals, and clocking.
•
•
•
•
•
Related Information
MAX 10 I/O Architecture and Features
on page 2-1
Provides information about the architecture and features of the I/Os in MAX 10 devices.
MAX 10 I/O Design Considerations
on page 3-1
Provides I/O design guidelines for MAX 10 Devices.
MAX 10 I/O Implementation Guides
Provides guides to implement I/Os in MAX 10 Devices.
Altera GPIO Lite IP Core References
on page 5-1
Lists the parameters and signals of Altera GPIO Lite IP core for MAX 10 Devices.
MAX 10 General Purpose I/O User Guide Archives
on page 6-1
Provides a list of user guides for previous versions of the Altera GPIO Lite IP core.
Table 1-1: Package Plan for MAX 10 Single Power Supply Devices
Device
10M02
10M04
Type
Size
Ball Pitch
M153
153-pin MBGA
8 mm × 8 mm
0.5 mm
112
112
Package
U169
169-pin UBGA
11 mm × 11 mm
0.8 mm
130
130
E144
144-pin EQFP
22 mm × 22 mm
0.5 mm
101
101
©
2016 Altera Corporation. All rights reserved. ALTERA, ARRIA, CYCLONE, ENPIRION, MAX, MEGACORE, NIOS, QUARTUS and STRATIX words and logos are trademarks of Altera Corporation and registered in the U.S. Patent and Trademark Office and in other countries. All other words and logos identified as trademarks or service marks are the property of their respective holders as described at www.altera.com/common/legal.html
. Altera warrants performance of its semiconductor products to current specifications in accordance with Altera's standard warranty, but reserves the right to make changes to any products and services at any time without notice. Altera assumes no responsibility or liability arising out of the application or use of any information, product, or service described herein except as expressly agreed to in writing by Altera. Altera customers are advised to obtain the latest version of device specifications before relying on any published information and before placing orders for products or services.
www.altera.com
101 Innovation Drive, San Jose, CA 95134
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1-2
MAX 10 Devices I/O Resources Per Package
Device
10M08
10M16
10M25
10M40
10M50
Type
Size
Ball Pitch
M153
153-pin MBGA
8 mm × 8 mm
0.5 mm
112
—
—
—
—
Package
U169
169-pin UBGA
11 mm × 11 mm
0.8 mm
130
130
—
—
—
Table 1-2: Package Plan for MAX 10 Dual Power Supply Devices—Preliminary
Device
Type
Size
Ball
Pitch
V36
36-pin
WLCSP
3 mm × 3 mm
0.4 mm
V81
81-pin
WLCSP
4 mm × 4 mm
0.4 mm
Package
U324
324-pin
UBGA
F256
256-pin
FBGA
15 mm × 15 mm
0.8 mm
17 mm × 17 mm
1.0 mm
F484
484-pin
FBGA
23 mm × 23 mm
1.0 mm
E144
144-pin EQFP
22 mm × 22 mm
0.5 mm
101
101
101
101
101
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F672
672-pin FBGA
27 mm × 27 mm
1.0 mm
10M02
10M04
10M08
10M16
10M25
10M40
10M50
—
—
—
—
27
—
—
—
—
—
—
—
—
56
160
246
246
246
—
—
—
—
178
178
178
178
178
178
—
—
250
320
360
360
360
—
—
500
500
—
—
—
Altera Corporation
MAX 10 I/O Overview
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MAX 10 I/O Vertical Migration Support
1-3
Figure 1-1: Migration Capability Across MAX 10 Devices
• The arrows indicate the migration paths. The devices included in each vertical migration path are shaded. Some packages have several migration paths. Devices with lesser I/O resources in the same path have lighter shades.
• To achieve the full I/O migration across product lines in the same migration path, restrict I/Os usage to match the product line with the lowest I/O count.
V36 V81 M153 U169
Package
U324 F256 E144 F484 F672
Device
10M02
10M04
10M08
10M16
10M25
10M40
10M50
Note: To verify the pin migration compatibility, use the Pin Migration View window in the Quartus
®
Prime software Pin Planner.
Related Information
Verifying Pin Migration Compatibility
MAX 10 I/O Overview
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The I/O system of MAX 10 devices support various I/O standards. In the MAX 10 devices, the I/O pins are located in I/O banks at the periphery of the devices. The I/O pins and I/O buffers have several programmable features.
Related Information
on page 1-1
2
MAX 10 devices support a wide range of I/O standards, including single-ended, voltage-referenced singleended, and differential I/O standards.
Table 2-1: Supported I/O Standards in MAX 10 Devices
The voltage-referenced I/O standards are not supported in the following I/O banks of these device packages:
• All I/O banks of V36 package of 10M02.
• All I/O banks of V81 package of 10M08.
• Banks 1A and 1B of E144 package of 10M50.
I/O Standard Type
Device
Support
All
Direction
Input
Yes
Output
Yes
Application
General purpose
Standard Support
JESD8-B 3.3 V LVTTL/3.3 V
LVCMOS
3.0 V LVTTL/3.0 V
LVCMOS
2.5 V LVCMOS
1.8 V LVCMOS
1.5 V LVCMOS
Singleended
Singleended
Singleended
Singleended
Singleended
All
All
All
All
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
General purpose
General purpose
General purpose
General purpose
JESD8-B
JESD8-5
JESD8-7
JESD8-11
©
2016 Altera Corporation. All rights reserved. ALTERA, ARRIA, CYCLONE, ENPIRION, MAX, MEGACORE, NIOS, QUARTUS and STRATIX words and logos are trademarks of Altera Corporation and registered in the U.S. Patent and Trademark Office and in other countries. All other words and logos identified as trademarks or service marks are the property of their respective holders as described at www.altera.com/common/legal.html
. Altera warrants performance of its semiconductor products to current specifications in accordance with Altera's standard warranty, but reserves the right to make changes to any products and services at any time without notice. Altera assumes no responsibility or liability arising out of the application or use of any information, product, or service described herein except as expressly agreed to in writing by Altera. Altera customers are advised to obtain the latest version of device specifications before relying on any published information and before placing orders for products or services.
www.altera.com
101 Innovation Drive, San Jose, CA 95134
ISO
9001:2008
Registered
2-2
MAX 10 I/O Standards Support
I/O Standard Type
1.2 V LVCMOS
3.0 V PCI
3.3 V Schmitt
Trigger
2.5 V Schmitt
Trigger
1.8 V Schmitt
Trigger
1.5 V Schmitt
Trigger
SSTL-2 Class I
SSTL-2 Class II
SSTL-18 Class I
SSTL-18 Class II
SSTL-15 Class I
SSTL-15 Class II
SSTL-15 (1)
SSTL-135
(1)
1.8 V HSTL Class I
1.8 V HSTL Class II
1.5 V HSTL Class I
Voltagereferenced
Voltagereferenced
Voltagereferenced
Voltagereferenced
Voltagereferenced
Voltagereferenced
Voltagereferenced
Voltagereferenced
Voltagereferenced
Voltagereferenced
Voltagereferenced
Singleended
Singleended
Singleended
Singleended
Singleended
Singleended
Device
Support
All
All
All
All
All
All
All
All
All
All
All
All
All
All
All
All
All
Direction
Input Output
Yes Yes
Yes Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
—
Yes
Yes
—
—
—
Yes
Yes
Yes
Application
General purpose
General purpose
General purpose
General purpose
General purpose
General purpose
DDR1
DDR1
DDR2
DDR2
DDR3
DDR3
DDR3
DDR3L
DDR II+, QDR II+, and RLDRAM 2
DDR II+, QDR II+, and RLDRAM 2
DDR II+, QDR II+,
QDR II, and
RLDRAM 2
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Standard Support
JESD8-12
PCI Rev. 2.2
—
—
—
—
JESD8-9B
JESD8-9B
JESD8-15
JESD8-15
—
—
JESD79-3D
—
JESD8-6
JESD8-6
JESD8-6
(1) Available in MAX 10 16, 25, 40, and 50 devices only.
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I/O Standard Type
1.5 V HSTL Class II Voltagereferenced
Device
Support
All
1.2 V HSTL Class I
1.2 V HSTL Class II
HSUL-12 (1)
Voltagereferenced
Voltagereferenced
Voltagereferenced
Differential Differential SSTL-2
Class I and II
Differential SSTL-
18 Class I and Class
II
Differential SSTL-
15 Class I and Class
II
Differential SSTL-
15
Differential SSTL-
135
Differential 1.8 V
HSTL Class I and
Class II
Differential 1.5 V
HSTL Class I and
Class II
Differential 1.2 V
HSTL Class I and
Class II
Differential HSUL-
12
LVDS (dedicated)
(4)
Differential
Differential
Differential
Differential
Differential
Differential
Differential
Differential
Differential
All
All
All
All
All
All
All
All
All
All
All
All
All
Yes
Yes (2)
Yes
(2)
Yes (2)
Yes (2)
Yes (2)
Yes
(2)
Yes (2)
Yes (2)
Yes (2)
Yes
MAX 10 I/O Standards Support
Direction
Input Output
Yes Yes
Yes Yes
Application
DDR II+, QDR II+,
QDR II, and
RLDRAM 2
General purpose
2-3
Standard Support
JESD8-6
JESD8-16A
Yes Yes General purpose JESD8-16A
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
(3)
(3)
(3)
(3)
(3)
(3)
(3)
(3)
(3)
Yes
LPDDR2
DDR1
DDR2
DDR3
DDR3
DDR3L
DDR II+, QDR II+, and RLDRAM 2
DDR II+, QDR II+,
QDR II, and
RLDRAM 2
General purpose
LPDDR2
—
—
JESD8-9B
JESD8-15
—
JESD79-3D
—
JESD8-6
JESD8-6
JESD8-16A
—
ANSI/TIA/EIA-644
(2)
(3)
(4)
The inputs treat differential inputs as two single-ended inputs and decode only one of them.
The outputs use two single-ended output buffers with the second output buffer programmed as inverted.
You can use dedicated LVDS transmitters only on the bottom I/O banks. You can use LVDS receivers on all
I/O banks.
MAX 10 I/O Architecture and Features
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MAX 10 I/O Standards Support
I/O Standard Type
LVDS (emulated, external resistors)
Mini-LVDS
(dedicated) (4)
Mini-LVDS
(emulated, external resistor)
RSDS (dedicated) (4)
RSDS (emulated, external resistor,
1R)
RSDS (emulated, external resistors,
3R)
PPDS (dedicated) (4)
Differential
Differential
Differential
Differential
Differential
Differential
Differential
Device
Support
All
All
PPDS (emulated, external resistor)
LVPECL
Bus LVDS
TMDS
Sub-LVDS
SLVS
Differential
Differential
Differential
Differential
Differential
Differential
Dual supply devices
All
Dual supply devices
All
Dual supply devices
Dual supply devices
All
All
Dual supply devices
Dual supply devices
Dual supply devices
Direction
Input Output
— Yes
— Yes
—
—
—
—
—
—
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
—
Yes
—
Yes
Yes
(5)
(6)
(7)
Application
—
—
—
Standard Support
ANSI/TIA/EIA-644
—
—
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—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
(5)
(6)
(7)
The outputs use two single-ended output buffers with the second output buffer programmed as inverted. A single series resistor is required.
Requires external termination resistors.
The outputs uses two single-ended output buffers as emulated differential outputs. Requires external termination resistors.
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I/O Standard
HiSpi
Type
Differential
Device
Support
Dual supply devices
MAX 10 I/O Standards Voltage and Pin Support
Direction
Input Output
Yes —
Application
—
2-5
Standard Support
—
•
•
Related Information
on page 2-13
Provides more information about available I/O buffer types and supported I/O standards.
LVDS Transmitter I/O Termination Schemes, MAX 10 High-Speed LVDS I/O User Guide
Table 2-2: MAX 10 I/O Standards Voltage Levels and Pin Support
Note: The I/O standards that each pin type supports depends on the I/O standards that the pin's I/O bank supports. For example, only the bottom I/O banks support the LVDS (dedicated) I/O standard. You can use the LVDS (dedicated) I/O standard for the
PLL_CLKOUT
pin only if the pin is available in your device's bottom I/O banks. To determine the pin's I/O bank locations for your device, check your device's pin out file.
I/O Standard
Input
V
CCIO
(V)
Output
V
REF
(V)
Pin Type Support
MEM_CLK CLK DQS
User I/O
3.3/3.0/
2.5
3.0/2.5
3.3
3.0
—
—
PLL_
CLKOUT
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
3.3 V LVTTL/
3.3 V LVCMOS
3.0 V LVTTL/
3.0 V LVCMOS
2.5 V LVCMOS
1.8 V LVCMOS
1.5 V LVCMOS
1.2 V LVCMOS
3.0 V PCI
3.3 V Schmitt
Trigger
2.5 V Schmitt
Trigger
1.8 V Schmitt
Trigger
3.0/2.5
1.8/1.5
1.8/1.5
1.2
3.0
3.3
2.5
1.8
2.5
1.8
1.5
1.2
3.0
—
—
—
—
—
—
—
—
—
—
—
Yes
Yes
Yes
Yes
Yes
—
—
—
Yes
Yes
Yes
Yes
Yes
—
—
—
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
(8)
(8)
(8)
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
(8) Bidirectional— use Schmitt Trigger input with LVTTL output.
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2-6
MAX 10 I/O Standards Voltage and Pin Support
I/O Standard
Input
V
CCIO
(V)
Output
V
REF
(V)
1.5
— —
PLL_
CLKOUT
— 1.5 V Schmitt
Trigger
SSTL-2 Class I
SSTL-2 Class II
SSTL-18 Class I
SSTL-18 Class II
SSTL-15 Class I
SSTL-15 Class II
SSTL-15
SSTL-135
I
1.8 V HSTL Class
1.8 V HSTL Class
II
I
1.5 V HSTL Class
1.5 V HSTL Class
II
I
1.2 V HSTL Class
1.2 V HSTL Class
II
HSUL-12
Differential SSTL-
2 Class I and II
Differential SSTL-
18 Class I and
Class II
Differential SSTL-
15 Class I and
Class II
Differential SSTL-
15
2.5
2.5
1.8
1.8
1.5
1.5
1.5
1.35
1.8
1.8
1.5
1.5
1.2
1.2
1.2
—
2.5
—
1.8
—
1.5
—
1.5
2.5
2.5
1.8
1.8
1.5
1.5
1.5
1.35
1.8
1.8
1.5
1.5
1.2
1.2
1.2
2.5
—
1.8
—
1.5
—
1.5
—
1.25
1.25
0.9
0.9
0.75
0.75
0.75
0.675
0.9
0.9
0.75
0.75
0.6
0.6
0.6
—
1.25
—
0.9
—
0.75
—
0.75
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
—
Yes
—
Yes
—
Yes
—
Pin Type Support
MEM_CLK CLK DQS
—
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
—
Yes
—
Yes
—
Yes
—
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
—
Yes
—
Yes
—
Yes
—
Yes
Yes (8)
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
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User I/O
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
—
—
—
—
—
—
—
—
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I/O Standard
Differential SSTL-
135
Differential 1.8 V
HSTL Class I and
Class II
Differential 1.5 V
HSTL Class I and
Class II
Differential 1.2 V
HSTL Class I and
Class II
Differential
HSUL-12
LVDS (dedicated)
LVDS (emulated, external resistors)
Mini-LVDS
(dedicated)
Mini-LVDS
(emulated, external resistor)
RSDS (dedicated)
RSDS (emulated, external resistor,
1R)
RSDS (emulated, external resistors,
3R)
PPDS (dedicated)
PPDS (emulated, external resistor)
LVPECL
Bus LVDS
TMDS
Sub-LVDS
Input
V
CCIO
(V)
Output
V
REF
(V)
—
1.5
—
1.2
—
1.2
2.5
—
—
1.35
—
1.8
1.5
—
1.2
—
1.2
—
2.5
2.5
1.35
—
1.8
—
—
0.675
—
0.9
—
0.75
—
0.6
—
0.6
—
—
Yes
—
Yes
—
Yes
—
Yes
Yes
MAX 10 I/O Standards Voltage and Pin Support
Pin Type Support
MEM_CLK CLK DQS PLL_
CLKOUT
Yes
—
Yes
—
Yes
—
Yes
—
—
Yes
—
Yes
Yes
Yes
Yes
Yes
2-7
User I/O
—
—
—
—
Yes
—
Yes
—
Yes
—
Yes
Yes
—
Yes
—
Yes
—
Yes
Yes
—
Yes
Yes
Yes
Yes
Yes
Yes
—
—
—
—
—
—
—
—
Yes
Yes
— 2.5
— Yes Yes — — Yes
— 2.5
— Yes Yes — — Yes
—
—
—
—
—
2.5
2.5
2.5
2.5
2.5
2.5
2.5
2.5
2.5
—
2.5
—
1.8
—
—
—
—
—
—
—
—
—
Yes
Yes
Yes
Yes
Yes
—
—
—
Yes
Yes
Yes
Yes
Yes
Yes
—
—
—
Yes
—
—
—
—
—
Yes
—
Yes
Yes
—
—
—
—
—
—
—
—
—
Yes
Yes
Yes
Yes
Yes
—
Yes
Yes
Yes
MAX 10 I/O Architecture and Features
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MAX 10 I/O Elements
I/O Standard
Input
V
CCIO
(V)
Output
V
REF
(V)
SLVS
HiSpi
2.5
2.5
2.5
—
—
—
•
•
•
•
•
Related Information
MAX 10 Device Pin-Out Files
on page 2-1
MAX 10 LVDS SERDES I/O Standards Support
MAX 10 High-Speed LVDS I/O Location
PLL_
CLKOUT
Yes
—
Pin Type Support
MEM_CLK CLK DQS
Yes
—
Yes
Yes
—
—
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User I/O
Yes
Yes
The MAX 10 I/O elements (IOEs) contain a bidirectional I/O buffer and five registers for registering input, output, output-enable signals, and complete embedded bidirectional single data rate (SDR) and double data rate (DDR) transfer.
The I/O buffers are grouped into groups of four I/O modules per I/O bank:
• The MAX 10 devices share the user I/O pins with the
VREF
,
RUP
,
RDN
,
CLKPIN
,
PLLCLKOUT
, configura‐ tion, and test pins.
• Schmitt Trigger input buffer is available in all I/O buffers.
Each IOE contains one input register, two output registers, and two output-enable (OE) registers:
• The two output registers and two OE registers are used for DDR applications.
• You can use the input registers for fast setup times and output registers for fast clock-to-output times.
• You can use the OE registers for fast clock-to-output enable times.
You can use the IOEs for input, output, or bidirectional data paths. The I/O pins support various singleended and differential I/O standards.
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Figure 2-1: IOE Structure in Bidirectional Configuration
io_clk[5..0]
Column or Row
Interconnect
OE clkout oe_out
OE Register
D Q
ENA
ACLR/PRN aclr/prn
Chip-Wide Reset data_in1 data_in0 sclr/ preset
Output Register
D Q
ENA
ACLR/PRN
MAX 10 I/O Banks Architecture
Output
Pin Delay
Current Strength Control
Open-Drain Out
Slew Rate Control
VCCIO
Optional
PCI Clamp
VCCIO
Programmable
Pull-Up
Resistor
Bus Hold
2-9
clkin oe_in
D Q
ENA
ACLR/PRN
Input Register
Input Pin to
Input Register
Delay or Input Pin to
Logic Array
Delay
Related Information
MAX 10 Power Management User Guide
Provides more information about the I/O buffers in different power cycles and hot socketing.
The I/O elements are located in a group of four modules per I/O bank:
• High speed DDR3 I/O banks—supports various I/O standards and protocols including DDR3. These
I/O banks are available only on the right side of the device.
• High speed I/O banks—supports various I/O standards and protocols except DDR3. These I/O banks are available on the top, left, and bottom sides of the device.
• Low speed I/O banks—lower speeds I/O banks that are located at the top left side of the device.
For more information about I/O pins support, refer to the pinout files for your device.
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MAX 10 I/O Banks Locations
Related Information
MAX 10 Device Pin-Out Files
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The I/O banks are located at the periphery of the device.
For more details about the modular I/O banks available in each device package, refer to the relevant device pin-out file.
Figure 2-2: I/O Banks for MAX 10 02 Devices—Preliminary
VREF8 VCCIO8
8
VREF1
VCCIO1
1
VREF2
VCCIO2
2
6
VREF6
VCCIO6
5
VREF5
VCCIO5
3
VCCIO3 VREF3
Low Speed I/O
High Speed I/O
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Figure 2-3: I/O Banks for MAX 10 04 and 08 Devices—Preliminary
VREF8 VCCIO8 VREF7 VCCIO7
MAX 10 I/O Banks Locations
8 7
2-11
VCCIO1A
VREF1
VCCIO1B
VREF2
1A
1B
2
VCCIO2
6
VREF6
VCCIO6
5
VREF5
VCCIO5
3
VCCIO3 VREF3
4
VCCIO4 VREF4
Low Speed I/O
High Speed I/O
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MAX 10 I/O Banks Locations
Figure 2-4: I/O Banks for MAX 10 16, 25, 40, and 50 Devices—Preliminary
VREF8 VCCIO8 VREF7 VCCIO7
8 7
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VCCIO1A
VREF1
VCCIO1B
1A
1B
6
VREF6
VCCIO6
VREF2 VREF5
2 5
VCCIO2 VCCIO5
3
VCCIO3 VREF3
4
VCCIO4 VREF4
OCT
Low Speed I/O
High Speed I/O
High Speed DDR3 I/O
•
•
Related Information
MAX 10 Device Pin-Out Files
High-Speed I/O Specifications
Provides the performance information for different I/O standards in the low-speed and high-speed I/O banks.
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MAX 10 I/O Buffers
2-13
The general purpose I/Os (GPIOs) in MAX 10 devices consist of LVDS I/O and DDR I/O buffers.
Table 2-3: Types of GPIO Buffers in MAX 10 Devices
LVDS I/O Buffers
• Support differential and single-ended I/O standards.
• Available only on I/O banks at the bottom side of the device.
• For LVDS, the bottom I/O banks support LVDS transmitter, emulated LVDS transmitter, and
LVDS receiver buffers.
DDR I/O Buffers
• Support differential and single-ended I/O standards.
• Available on I/O banks at the left, right, and top sides of the device.
• For LVDS, the DDR I/O buffers support only
LVDS receiver and emulated LVDS transmitter buffers.
• For DDR, only the DDR I/O buffers on the right side of the device supports DDR3 external memory interfaces. DDR3 support is only available for MAX 10 16, 25, 40, and 50 devices.
•
•
Related Information
on page 2-1
LVDS Transmitter I/O Termination Schemes, MAX 10 High-Speed LVDS I/O User Guide
The MAX 10 devices feature selectable Schmitt trigger input buffer on all I/O banks.
The Schmitt trigger input buffer has similar V
IL
and V
IH
as the LVTTL I/O standard but with better noise immunity. The Schmitt trigger input buffers are used as default input buffers during configuration mode.
Related Information
MAX 10 Device Datasheet
The MAX 10 I/O buffers support a range of programmable features. These features increase the flexibility of I/O utilization and provide an alternative to reduce the usage of external discrete components such as a pull-up resistor and a diode.
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Programmable I/O Buffer Features
Table 2-4: Summary of Supported MAX 10 Programmable I/O Buffer Features and Settings
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Feature
Open
Drain
Bus-Hold
Pull-up
Resistor
Slew Rate
Control
Setting
Condition
On, Off (default)
On, Off (default)
On, Off (default)
0 (Slow), 1 (Medium),
2 (Fast). Default is 2.
To enable this feature, use the
OPNDRN primitive.
Disabled if you use the weak pull-up resistor feature.
Disabled if you use the bus-hold feature.
Disabled if you use OCT.
Assignment Name
—
Enable Bus-
Hold Circuitry
Weak Pull-Up
Resistor
Slew Rate
Supported I/O Standards
• 3.0 V and 3.3 V LVTTL
• 1.2 V, 1.5 V, 1.8 V, 2.5 V,
3.0 V, and 3.3 V LVCMOS
• SSTL-2, SSTL-18, SSTL-15, and SSTL-135
• 1.2 V, 1.5 V, and 1.8 V
HSTL
• HSUL-12
• 3.0 V PCI
• 3.0 V LVTTL
• 1.2 V, 1.5 V, 1.8 V, 2.5 V, and 3.0 V LVCMOS
• SSTL-2, SSTL-18, and
SSTL-15
• 1.2 V, 1.5 V, and 1.8 V
HSTL
• Differential SSTL-2,
Differential SSTL-18, and
Differential SSTL-15
• Differential 1.2 V, 1.5 V, and 1.8 V HSTL
PCI Clamp
Diode
On (default for input pins),
Off (default for output pins, except 3.0 V PCI)
— PCI I/O
• 3.0 V and 3.3 V LVTTL
• 2.5 V, 3.0 V, and 3.3 V
LVCMOS
• 3.0 V PCI
• 2.5 V, 3.0 V, and 3.3 V
Schmitt Trigger
Pre-
Emphasis
Differen‐ tial Output
Voltage
0 (disabled), 1
(enabled). Default is 1.
0 (low), 1 (medium), 2
(high). Default is 2.
—
—
Programmable
Pre-emphasis
Programmable
Differential
Output
Voltage (V
OD
)
• LVDS
• RSDS
• PPDS
• Mini-LVDS
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Programmable Open Drain
The optional open-drain output for each I/O pin is equivalent to an open collector output. If it is configured as an open drain, the logic value of the output is either high-Z or logic low.
Use an external resistor to pull the signal to a logic high.
2-15
Each I/O pin provides an optional bus-hold feature that is active only after configuration. When the device enters user mode, the bus-hold circuit captures the value that is present on the pin by the end of the configuration.
The bus-hold circuitry holds this pin state until the next input signal is present. Because of this, you do not require an external pull-up or pull-down resistor to hold a signal level when the bus is tri-stated.
For each I/O pin, you can individually specify that the bus-hold circuitry pulls non-driven pins away from the input threshold voltage—where noise can cause unintended high-frequency switching. To prevent over-driving signals, the bus-hold circuitry drives the voltage level of the I/O pin lower than the V
CCIO level.
If you enable the bus-hold feature, you cannot use the programmable pull-up option. To configure the
I/O pin for differential signals, disable the bus-hold feature.
Each I/O pin provides an optional programmable pull-up resistor during user mode. The pull-up resistor weakly holds the I/O to the V
CCIO
level.
If you enable the weak pull-up resistor, you cannot use the bus-hold feature.
You can use the programmable current strength to mitigate the effects of high signal attenuation that is caused by a long transmission line or a legacy backplane.
Table 2-5: Programmable Current Strength Settings for MAX 10 Devices
The output buffer for each MAX 10 device I/O pin has a programmable current strength control for the I/O standards listed in this table.
I/O Standard
I
OH
/ I
OL
Current Strength Setting (mA)
(Default setting in bold)
3.3 V LVCMOS
3.3 V LVTTL
3.0 V LVTTL/3.0 V LVCMOS
2.5 V LVTTL/2.5 V LVCMOS
1.8 V LVTTL/1.8 V LVCMOS
1.5 V LVCMOS
1.2 V LVCMOS
SSTL-2 Class I
SSTL-2 Class II
2
8, 4
16, 12, 8, 4
16, 12, 8, 4
16, 12, 10, 8, 6, 4, 2
16, 12, 10, 8, 6, 4, 2
12, 10, 8, 6, 4, 2
12, 8
16
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Programmable Output Slew Rate Control
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I/O Standard
SSTL-18 Class I
SSTL-18 Class II
SSTL-15 Class I
SSTL-15 Class II
1.8 V HSTL Class I
1.8 V HSTL Class II
1.5 V HSTL Class I
1.5 V HSTL Class II
1.2 V HSTL Class I
1.2 V HSTL Class II
BLVDS
SLVS
Sub-LVDS
I
OH
/ I
OL
Current Strength Setting (mA)
(Default setting in bold)
12, 10, 8
16, 12
12, 10, 8
16
12, 10, 8
16
12, 10, 8
16
12, 10, 8
14
16, 12, 8
16, 12, 8
12, 8, 4
Note: Altera recommends that you perform IBIS or SPICE simulations to determine the best current strength setting for your specific application.
You have the option of three settings for programmable slew rate control—0, 1, and 2 with 2 as the default setting. Setting 0 is the slow slew rate and 2 is the fast slew rate.
• Fast slew rate—provides high-speed transitions for high-performance systems.
• Slow slew rate—reduces system noise and crosstalk but adds a nominal delay to the rising and falling edges.
Table 2-6: Programmable Output Slew Rate Control for MAX 10 Devices
This table lists the single-ended I/O standards and current strength settings that support programmable output slew rate control. For I/O standards and current strength settings that do not support programmable slew rate control, the default slew rate setting is 2 (fast slew rate).
I/O Standard
I
OH
/ I
OL
Current Strength Supporting Slew Rate Control
3.0 V LVTTL/3.0 V LVCMOS
2.5 V LVTTL/2.5 V LVCMOS
1.8 V LVTTL/1.8 V LVCMOS
1.5 V LVCMOS
1.2 V LVCMOS
SSTL-2 Class I
16, 12, 8
16, 12, 8
16, 12, 8
16, 12, 10, 8
12, 10, 8
12, 8
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I/O Standard
SSTL-2 Class II
SSTL-18 Class I
SSTL-18 Class II
SSTL-15 Class I
SSTL-15 Class II
1.8 V HSTL Class I
1.8 V HSTL Class II
1.5 V HSTL Class I
1.5 V HSTL Class II
1.2 V HSTL Class I
1.2 V HSTL Class II
Programmable IOE Delay
2-17
I
OH
/ I
OL
Current Strength Supporting Slew Rate Control
16
12, 10, 8
16, 12
12, 10, 8
16
12, 10, 8
16
12, 10, 8
16
12, 10, 8
14
You can specify the slew rate on a pin-by-pin basis because each I/O pin contains a slew rate control. The slew rate control affects both the rising and falling edges.
Note: Altera recommends that you perform IBIS or SPICE simulations to determine the best slew rate setting for your specific application.
You can activate the programmable IOE delays to ensure zero hold times, minimize setup times, increase clock-to-output times, or delay the clock input signal. This feature helps read and write timing margins because it minimizes the uncertainties between signals in the bus.
Each pin can have a different input delay from pin-to-input register or a delay from output register-to-output pin values to ensure that the signals within a bus have the same delay going into or out of the device.
Table 2-7: Programmable Delay Chain
Programmable Delays
Input pin-to-logic array delay
Input pin-to-input register delay
Output pin delay
Dual-purpose clock input pin delay
Quartus Prime Logic Option
Input delay from pin to internal cells
Input delay from pin to input register
Delay from output register to output pin
Input delay from dual-purpose clock pin to fan-out destina‐ tions
There are two paths in the IOE for an input to reach the logic array. Each of the two paths can have a different delay. This allows you to adjust delays from the pin to the internal logic element (LE) registers that reside in two different areas of the device. You must set the two combinational input delays with the input delay from pin to internal cells logic option in the Quartus Prime software for each path. If the pin
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PCI Clamp Diode
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uses the input register, one of the delays is disregarded and the delay is set with the input delay from pin to input register logic option in the Quartus Prime software.
The IOE registers in each I/O block share the same source for the preset or clear features. You can program preset or clear for each individual IOE, but you cannot use both features simultaneously. You can also program the registers to power-up high or low after configuration is complete. If programmed to power-up low, an asynchronous clear can control the registers. If programmed to power-up high, an asynchronous preset can control the registers. This feature prevents the inadvertent activation of the active-low input of another device upon power up. If one register in an IOE uses a preset or clear signal, all registers in the IOE must use that same signal if they require preset or clear. Additionally, a synchro‐ nous reset signal is available for the IOE registers.
•
•
Related Information
MAX 10 Device Datasheet
Timing Closure and Optimization chapter, Volume 2: Design Implementation and Optimization,
Quartus Prime Handbook
Provides more information about the input and output pin delay settings.
The MAX 10 devices are equipped with optional PCI clamp diode that you can enable for the input and output of each I/O pin.
The PCI clamp diode is available in the Quartus Prime software for the following I/O standards:
• 3.3 V LVTTL/3.3 V LVCMOS
• 3.0 V LVTTL/3.0 V LVCMOS
• 2.5 V LVTTL/2.5 V LVCMOS
• 3.0 V PCI
• 3.3 V Schmitt Trigger
• 2.5 V Schmitt Trigger
The differential output voltage (V
OD
) setting and the output impedance of the driver set the output current limit of a high-speed transmission signal. At a high frequency, the slew rate may not be fast enough to reach the full V
OD
level before the next edge, producing pattern-dependent jitter. Pre-emphasis momentarily boosts the output current during switching to increase the output slew rate.
Pre-emphasis increases the amplitude of the high-frequency component of the output signal. This increase compensates for the frequency-dependent attenuation along the transmission line.
The overshoot introduced by the extra current occurs only during change of state switching. This overshoot increases the output slew rate but does not ring, unlike the overshoot caused by signal reflection. The amount of pre-emphasis required depends on the attenuation of the high-frequency component along the transmission line.
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Programmable Differential Output Voltage
Figure 2-5: LVDS Output with Programmable Pre-Emphasis
2-19
Voltage boost from pre-emphasis
V
P
OUT
V
OD
OUT
V
P
Differential output voltage (peak–peak)
Table 2-8: Quartus Prime Software Assignment for Programmable Pre-Emphasis
To
Assignment name
Allowed values
Field Assignment
tx_out
Programmable Pre-emphasis
0 (disabled), 1 (enabled). Default is 1.
The programmable V
OD
settings allow you to adjust the output eye opening to optimize the trace length and power consumption. A higher V
V
OD
OD
swing reduces power consumption.
swing improves voltage margins at the receiver end, and a smaller
Figure 2-6: Differential V
OD
This figure shows the V
OD
of the differential LVDS output.
Single-Ended Waveform
Positive Channel (p)
V
OD
Negative Channel (n)
V
CM
Ground
Differential Waveform
V
OD
V
OD
(diff peak - peak) = 2 x V
OD
(single-ended)
V
OD p - n = 0 V
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Programmable Emulated Differential Output
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You can statically adjust the V of the differential signal by changing the V
Prime software Assignment Editor.
OD
settings in the Quartus
Table 2-9: Quartus Prime Software Assignment Editor—Programmable V
OD
Field
To
Assignment name
Allowed values
Assignment
tx_out
Programmable Differential Output Voltage (V
OD
)
0 (low), 1 (medium), 2 (high). Default is 2.
The MAX 10 devices support emulated differential output where a pair of IOEs drives bidirectional I/O pins.
The emulated differential output feature is supported for the following I/O standards:
• Differential SSTL-2 Class I and II
• Differential SSTL-18 Class I and II
• Differential SSTL-15 Class I and II
• Differential SSTL-15
• Differential SSTL-135
• Differential 1.8 V HSTL Class I and II
• Differential 1.5 V HSTL Class I and II
• Differential 1.2 V HSTL Class I and II
• Differential HSUL-12
• LVDS 3R
• Mini-LVDS 3R
• PPDS 3R
• RSDS 1R and 3R
• BLVDS
• SLVS
• Sub-LVDS
The MAX 10 16, 25, 40, and 50 devices feature programmable dynamic power down for several I/O standards to reduce the static power consumption.
In these devices, you can apply the programmable dynamic power down feature to the I/O buffers for the following I/O standards:
• Input buffer—SSTL, HSTL, HSUL, LVDS
• Output buffer—LVDS
Related Information
MAX 10 Power Management User Guide
Provides more information about using the programmable dynamic power down feature.
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I/O Standards Termination
2-21
Voltage-referenced and differential I/O standards requires different termination schemes.
The 3.3-V LVTTL, 3.0-V LVTTL and LVCMOS, 2.5-V LVTTL and LVCMOS, 1.8-V LVTTL and
LVCMOS, 1.5-V LVCMOS, 1.2-V LVCMOS, and 3.0-V PCI I/O standards do not specify a recommended termination scheme per the JEDEC standard.
Voltage-referenced I/O standards require an input reference voltage (V
REF
(V
TT device.
) and a termination voltage
). The reference voltage of the receiving device tracks the termination voltage of the transmitting
Figure 2-7: HSTL I/O Standard Termination
Termination
External
On-Board
Termination
OCT with and without
Calibration
Transmitter
Series OCT
50 Ω
HSTL Class I
50 Ω
50 Ω
VREF
VTT
50 Ω
50 Ω
VREF
VTT
Transmitter
Receiver
Receiver
HSTL Class II
VTT
50 Ω 50 Ω
50 Ω
VREF
VTT
Transmitter
Series OCT
25 Ω
VTT
50 Ω 50 Ω
VTT
50 Ω
VREF
Transmitter
Receiver
Receiver
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Differential I/O Standards Termination
Figure 2-8: SSTL I/O Standard Termination
Termination
External
On-Board
Termination
SSTL Class I
25 Ω
50 Ω
50 Ω
VREF
VTT
Transmitter
Series OCT
50 Ω
OCT with and without
Calibration
50 Ω
50 Ω
VREF
VTT
Receiver
Transmitter Receiver
SSTL Class II
50 Ω
25 Ω
VTT VTT
50 Ω
50 Ω
VREF
Transmitter
Series OCT
25 Ω
50 Ω
VTT VTT
50 Ω
50 Ω
VREF
Transmitter
Receiver
Receiver
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Differential I/O standards typically require a termination resistor between the two signals at the receiver.
The termination resistor must match the differential load impedance of the bus.
Figure 2-9: Differential HSTL I/O Standard Termination
Termination
External
On-Board
Termination
Differential HSTL
V
TT
V
TT
50 Ω
50 Ω
50 Ω
50 Ω
Transmitter Receiver
OCT
Series OCT
50 Ω
50 Ω
50 Ω
V
TT
50 Ω
V
TT
50 Ω
Transmitter Receiver
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Figure 2-10: Differential SSTL I/O Standard Termination
Termination
External
On-Board
Termination
Differential SSTL Class I
25 Ω
50 Ω
50 Ω
V
TT
50 Ω
V
TT
25 Ω
50 Ω
Transmitter Receiver Transmitter
MAX 10 On-Chip I/O Termination
Differential SSTL Class II
50 Ω
25 Ω
V
TT
V
TT
50 Ω 50 Ω
50 Ω
V
TT
V
TT
50 Ω
25 Ω
50 Ω
OCT
Series OCT
50 Ω
50 Ω
50 Ω
V
TT
50 Ω
V
TT
50 Ω
Series OCT
25 Ω
V
TT
V
TT
50 Ω 50 Ω 50 Ω
50 Ω
V
TT
50 Ω
V
TT
50 Ω
Transmitter Receiver Transmitter
2-23
Receiver
Receiver
Related Information
MAX 10 High-Speed LVDS I/O User Guide
Provides more information about differential I/O external termination.
The on-chip termination (OCT) block in MAX 10 devices provides I/O impedance matching and termination capabilities. OCT maintains signal quality, saves board space, and reduces external component costs.
The MAX 10 devices support serial (R
S
) OCT for single-ended output pins and bidirectional pins. For bidirectional pins, OCT is active for output only.
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OCT Calibration
Figure 2-11: Single-ended I/O Termination (R
S
)
This figure shows the single-ended termination scheme supported in MAX 10 device.
Driver
Series Termination
Receiving
Device
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R
S
Z
0
= 50 Ω
V
REF
Table 2-10: OCT Schemes Supported in MAX 10 Devices
Direction OCT Schemes
R
S
OCT with calibration
Output
R
S
OCT without calibration
Device Support
MAX 10 16, 25,
40, and 50 devices
All MAX 10 devices
I/O Bank Support
Right bank only
All I/O banks
The OCT calibration circuit compares the total impedance of the output buffer to the external resistors connected to the
RUP
and
RDN
pins. The circuit dynamically adjusts the output buffer impedance until it matches the external resisters.
Each calibration block comes with a pair of
RUP
and
RDN
pins.
During calibration, the
RUP
and
RDN
pins are each connected through an external 25 Ω, 34 Ω, 40 Ω, 48 Ω, or 50 Ω resistor for respective on-chip series termination value of 25 Ω, 34 Ω, 40 Ω, 48 Ω, and 50 Ω:
•
•
RUP
RDN
—connected to
VCCIO
.
—connected to
GND
.
The OCT calibration circuit compares the external resistors to the internal resistance using comparators.
The OCT calibration block uses the comparators' output to dynamically adjust buffer impedance.
During calibration, the resistance of the
RUP
and
RDN
pins varies. To estimate of the maximum possible current through the external calibration resistors, assume a minimum resistance of 0 Ω on the
RUP
and
RDN
pins.
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S
RS OCT in MAX 10 Devices
2-25
Table 2-11: Selectable I/O Standards for R
S
OCT
This table lists the output termination settings for R
S standards.
OCT with and without calibration on different I/O
• R
• R
S
OCT with calibration—supported only on the right side I/O banks of the MAX 10 16, 25, 40, and 50 devices.
S
OCT without calibration—supported on all I/O banks of all MAX 10 devices.
Calibrated OCT (Output) Uncalibrated OCT (Output)
I/O Standard
3.0 V LVTTL/3.0V LVCMOS
2.5 V LVTTL/2.5 V LVCMOS
1.8 V LVTTL/1.8 V LVCMOS
1.5 V LVCMOS
1.2 V LVCMOS
SSTL-2 Class I
SSTL-2 Class II
SSTL-18 Class I
SSTL-18 Class II
SSTL-15 Class I
SSTL-15 Class II
SSTL-15
SSTL-135
1.8 V HSTL Class I
1.8 V HSTL Class II
1.5 V HSTL Class I
1.5 V HSTL Class II
1.2 V HSTL Class I
1.2 V HSTL Class II
HSUL-12
Differential SSTL-2 Class I
Differential SSTL-2 Class I
Differential SSTL-18 Class I
Differential SSTL-18 Class II
Differential SSTL-15 Class I
50
25
50
25
34, 40
34, 40
50
25
34, 40, 48
50
25
50
25
50
25, 50
50
25
50
25
50
25
R
S
(Ω)
25, 50
25, 50
25, 50
25, 50
34, 40, 48
50
25
50
25
50
50
25
50
25
34, 40
34, 40
50
25
25, 50
50
25
50
25
50
25
R
S
(Ω)
25, 50
25, 50
25, 50
25, 50
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RS OCT in MAX 10 Devices
I/O Standard
Differential SSTL-15 Class II
Differential SSTL-15
Differential SSTL-135
Differential 1.8 V HSTL Class I
Differential 1.8 V HSTL Class II
Differential 1.5 V HSTL Class I
Differential 1.5 V HSTL Class II
Differential 1.2 V HSTL Class I
Differential 1.2 V HSTL Class II
Differential HSUL-12
Calibrated OCT (Output)
R
S
(Ω)
25
34, 40
34, 40
50
25
50
25
50
25
34, 40, 48
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Uncalibrated OCT (Output)
R
S
(Ω)
25
34, 40
34, 40
50
25
50
25
50
25
34, 40, 48
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There are several considerations that require your attention to ensure the success of your designs. Unless noted otherwise, these design guidelines apply to all variants of this device family.
Related Information
on page 1-1
3
There are several V
CCIO location.
range considerations because of I/O pin configuration function and I/O bank
• The shared I/O pins can only support a V
CCIO
range of 1.5 V to 3.3 V when you access the configura‐ tion function in user mode. The configuration function of the I/O pins can only support 1.5 V to 3.3 V.
If you need to access, for example, JTAG pins during user mode, the bank where the pin resides will be constrained by this V
CCIO
range. If you want to use I/O standards within the 1.2 V to 1.35 V range, you must not use the configuration function of any of the I/O pins during user mode. This only affects bank 1 and bank 8 because only these banks have I/O pins with configuration function.
• For devices with banks 1A and 1B:
• If you use the
VREF
pin or the ADC, you must supply a common V
CCIO
• If you do not use the
VREF
pin or the ADC, you can supply separate V
voltage to banks 1A and 1B.
CCIO
voltages to banks 1A and
1B.
• If you plan to migrate from devices that has banks 1A and 1B to devices that has only bank 1, ensure that the V
CCIO
of bank 1A and 1B are the same.
• For the V36 package of the 10M02 device, the V
CCIO
of these groups of I/O banks must be the same:
• Group 1—banks 1, 2 and 8
• Group 2—banks 3, 5, and 6
• For the V81 package of the 10M08 device, the V
CCIO
of these groups of I/O banks must be the same:
• Group 1—banks 1A, 1B, and 2
• Group 2—banks 5 and 6
These restrictions apply if you use the V
REF
pin.
©
2016 Altera Corporation. All rights reserved. ALTERA, ARRIA, CYCLONE, ENPIRION, MAX, MEGACORE, NIOS, QUARTUS and STRATIX words and logos are trademarks of Altera Corporation and registered in the U.S. Patent and Trademark Office and in other countries. All other words and logos identified as trademarks or service marks are the property of their respective holders as described at www.altera.com/common/legal.html
. Altera warrants performance of its semiconductor products to current specifications in accordance with Altera's standard warranty, but reserves the right to make changes to any products and services at any time without notice. Altera assumes no responsibility or liability arising out of the application or use of any information, product, or service described herein except as expressly agreed to in writing by Altera. Altera customers are advised to obtain the latest version of device specifications before relying on any published information and before placing orders for products or services.
www.altera.com
101 Innovation Drive, San Jose, CA 95134
ISO
9001:2008
Registered
3-2
Guidelines: Enable Clamp Diode for LVTTL/LVCMOS Input Buffers
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• If you use a shared
VREF
pin as an I/O, all voltage-reference input buffers (SSTL, HSTL, and HSUL) are disabled.
• If you use a shared
VREF
pin as a voltage reference, you must enable the input buffer of specific I/O pin to use the voltage-reference I/O standards.
• The voltage-referenced I/O standards are not supported in the following I/O banks of these device packages:
• All I/O banks of V36 package of 10M02.
• All I/O banks of V81 package of 10M08.
• Banks 1A and 1B of E144 package of 10M50.
• For devices with banks 1A and 1B, if you use the
VREF
pin, you must supply a common V
1A and 1B.
CCIO
to banks
• Maximum number of voltage-referenced inputs for each
VREF
pin is 75% of total number of I/O pads.
The Quartus Prime software will provide a warning if you exceed the maximum number.
• Except for I/O pins that you used for static signals, all non-voltage-referenced output must be placed two pads away from a
VREF
pin. The Quartus Prime software will output an error message if this rule is violated.
Related Information
If the V
CCIO
of the I/O bank is lower than the voltage of the LVTTL/LVCMOS input buffers, Altera recommends that you enable the clamp diode.
• 3.3 V LVCMOS/LVTTL input buffers—enable clamp diode if V
CCIO
of the I/O bank is 3.0 V.
• 3.3 V or 3.0 V LVCMOS/LVTTL input buffers—enable clamp diode if V
CCIO
of the I/O bank is 2.5 V.
By enabling the clamp diode under these conditions, you will be able to limit overshoot or undershoot.
However, this does not comply with hot socket current specification.
If you do not enable the clamp diode under these conditions, the signal integrity for the I/O pin will be impacted and there will be overshoot or undershoot problem. In this situation, you must ensure that your board design conforms to the overshoot/undershoot specifications.
Table 3-1: Voltage Tolerance Maximum Ratings for 3.3 V or 3.0 V
This table lists the voltage tolerance specifications. Ensure that your board design conforms to these specifications if you do not want to follow the clamp diode recommendation.
Voltage Minimum (V) Maximum (V)
V
CCIO
= 3.3 V
V
CCIO
= 3.0 V
V
IH
(AC)
V
IH
(DC)
V
IL
(DC)
3.135
2.85
—
—
–0.3
3.45
3.15
4.1
3.6
0.8
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Guidelines: Adhere to the LVDS I/O Restrictions Rules
3-3
For LVDS applications, adhere to the I/O restriction pin connection guidelines to avoid excessive jitter on the LVDS transmitter output pins. The Quartus Prime software generates a critical warning if these rules are violated.
Related Information
MAX 10 FPGA Device Family Pin Connection Guidelines
For different I/O standards and conditions, you must limit the number of I/O pins. This I/O restriction rule is applicable if you use LVDS transmitters or receivers.
Table 3-2: Maximum Percentage of I/O Pins Allowed for Specific I/O Standards in an I/O Bank
This table lists the maximum number of general purpose output pins recommended in a bank in terms of percentage to the total number of I/O pins available in an I/O bank if you use these combinations of I/O standards and conditions.
I/O Standard Condition Max Pins Per Bank (%)
25
2.5 V LVTTL/
LVCMOS
2.5 V SSTL
16 mA current strength and 25 Ω OCT (fast and slow slew rate)
12 mA current strength (fast and slow slew rate)
8 mA current strength (fast and slow slew rate) and 50
Ω OCT (fast slew rate)
4 mA current strength (fast and slow slew rate)
—
30
45
65
100
These restrictions are applicable if you use the analog-to-digital converter (ADC) block.
The Quartus Prime software uses physics-based rules to define the number of I/Os allowed in a particular bank based on the I/O's drive strength. These rules are based on noise calculation to analyze accurately the impact of I/O placement on the ADC performance.
The physics-based rules are available for the following devices starting from these Quartus Prime software versions:
• From Quartus Prime version 14.1—MAX 10 10M04, 10M08, 10M40, and 10M50 devices.
• From Quartus Prime version 15.0.1—MAX 10 10M02, 10M16, and 10M25 devices.
Altera highly recommends that you adhere to these guidelines to ensure ADC performance. Furthermore, following these guidelines prevents additional critical warning from future versions of the Quartus Prime software when the physics-based rules are implemented.
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Guidelines: Analog-to-Digital Converter I/O Restriction
Table 3-3: I/O Restrictions Related to ADC Usage—Preliminary
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This table lists the I/O restrictions by MAX 10 device package if you use the dedicated analog input (
ANAIN1
or
ANAIN2
) or any dual function ADC I/O pins as ADC channel inputs.
Package Restriction/Guideline
All Disable all JTAG operation during ADC sampling. The ADC signal-to-noise and distortion ratio (SINAD) is not guaranteed during JTAG operation.
M153
U169
U324
F256
F484
F672
• Banks 1A and 1B—you cannot use GPIO pins in these banks.
• Banks 2, 3, 4, 5, 6, and 7—you can use GPIO pins located in these banks.
• Bank 8—you can use a percentage of the GPIO pins in this bank based on drive strength:
• For an example listing the percentage of GPIO pins allowed in bank 8 for the
(9) .
• Use low drive strength (8 mA and below) and differential I/O standards.
• Do not place transmitter pins in this bank. Use banks 2, 3, 4, 5, 6, or 7 instead.
• You can use static pins such as
RESET
or
CONTROL
.
• GPIO pins in this bank are governed by physics-based rules. The Quartus Prime software will issue a critical warning I/O settings violates any of the I/O physicbased rule.
E144 • Bank 1A, 1B, 2, and 8—you cannot use GPIO pins in these banks.
• Banks 4 and 6—you can use GPIO pins located in these banks.
• Banks 3, 5, and 7—you can use a percentage of the GPIO pins in this bank based on drive strength:
• For the percentage of GPIO pins allowed, refer to
• Use low drive strength (8 mA and below) and differential I/O standards.
• GPIO pins in these banks are governed by physics-based rules. The Quartus
Prime software will issue a critical warning I/O settings violates any of the I/O physic-based rule.
Table 3-4: I/O Usage Restriction for Bank 8 in MAX 10 F484 Package
This table lists the percentage of I/O pins available in I/O bank 8 if you use the dedicated analog input (
ANAIN1
or
ANAIN2
) or any dual function ADC I/O pins as ADC channel. Refer to
for the list of I/O standards in each group.
I/O Standards TX RX Total Availability (%)
Group 1
Group 2
Group 3
Group 4
18
16
7
5
18
16
11
7
36
32
18
12
100
89
50
33
(9) For all device packages, the software displays a warning message if the number of GPIO pins in bank 8 is more than the allowed percentage.
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I/O Standards
Group 5
Group 6
Group 7
I/O Standard Group
Group 1
TX
4
4
0
RX
6
4
8
Guidelines: Analog-to-Digital Converter I/O Restriction
Total
10
8
8
Availability (%)
28
22
22
3-5
Table 3-5: I/O Usage Restriction for Banks 3, 5, and 7 in MAX 10 E144 Package
This table lists the percentage of I/O pins available in banks 3, 5, and 7 if you use the dedicated analog input
(
ANAIN1
or
ANAIN2
) or any dual function ADC I/O pins as ADC channel inputs. Refer to
for the list of
I/O standards in each group.
Bank 3 Bank 5 Bank 7
I/O Standards
TX RX Availability
(%)
TX RX Availability
(%)
TX RX Availability
(%)
Device I/O
Availability (%)
Group 1
Group 2
Group 3
Group 4
Group 5
Group 6
Group 7
7
7
4
3
2
1
0
8
8
5
4
3
2
0
88
88
50
39
28
17
0
6
6
6
5
5
5
5
6
6
6
5
5
5
5
100
100
100
83
83
83
83
4
4
2
0
0
0
0
3
3
0
0
0
0
0
100
100
29
0
0
0
0
37
35
32
54
54
45
39
Table 3-6: I/O Standards Groups Categorized According to Drive Strengths
I/O Standards Name and Drive Strength
• 2.5 V LVDS
• 2.5 V RSDS
• BLVDS at 4 mA
• SLVS at 4 mA
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Guidelines: Analog-to-Digital Converter I/O Restriction
I/O Standard Group
Group 2
I/O Standards Name and Drive Strength
• BLVDS at 8 mA
• SLVS at 8 mA
• Sub-LVDS at 8 mA
• 1.8 V, 1.5 V, and 1.2 V HSTL Class I at 8 mA
• SSTL-15 at 34 Ω or 40 Ω
• SSTL-135 at 34 Ω or 40 Ω
• HSUL-12 at 34 Ω or 40 Ω
• SSTL-2 Class I at 8 mA
• SSTL-18 Class I at 8 mA
• SSTL-15 Class I at 8 mA
• 2.5 V and 1.8 V LVTTL at 4 mA
• 2.5 V, 1.8 V, 1.5 V, and 1.2 V LVCMOS at 4 mA
• 1.8 V LVTTL at 2 mA
• 1.8 V, 1.5 V, and 1.2 V LVCMOS at 2 mA
Group 3
Group 4
• BLVDS at 12 mA
• SLVS at 12 mA
• Sub-LVDS at 12 mA
• SSTL-2 Class I at 10 mA or 12 mA
• SSTL-18 Class I at 10 mA or 12 mA
• SSTL-15 Class I at 10 mA or 12 mA
• 1.8 V, 1.5 V, and 1.2 V HSTL Class I at 10 mA or 12 mA
• SSTL-2 at 50 Ω
• SSTL-18 at 50 Ω
• SSTL-15 at 50 Ω
• 1.8 V, 1.5 V and 1.2 V HSTL at 50 Ω
• HSUL-12 at 48 Ω
• 2.5 V and 1.8 V LVTTL at 50 Ω
• 2.5 V, 1.8 V, 1.5 V, and 1.2 V LVCMOS at 50 Ω
• 1.8 V LVTTL at 6 mA or 8 mA
• 1.8 V, 1.5 V, and 1.2 V LVCMOS at 6 mA or 8 mA
• 3.0 V LVTTL at 4 mA
• 3.0 V LVCMOS at 4 mA
• SSTL-18 Class II at 12 mA
• 3.0 V LVTTL at 50 Ω
• 3.0 V LVCMOS at 50 Ω
• 2.5 V LVTTL at 8 mA
• 2.5 V LVCMOS at 8 mA
• 1.8 V LVTTL at 10 mA or 12 mA
• 1.8 V, 1.5 V, and 1.2 V LVCMOS at 10 mA or 12 mA
• 3.3 V LVCMOS at 2 mA
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I/O Standard Group
Group 5
Group 6
Group 7
Guidelines: External Memory Interface I/O Restrictions
I/O Standards Name and Drive Strength
• SSTL-2 Class II at 16 mA
• SSTL-18 Class II at 16 mA
• SSTL-15 Class II at 16 mA
• 1.8 V and 1.5 V HSTL Class II at 16 mA
• 1.2 V HSTL Class II at 14 mA
• SSTL-18 at 25 Ω
• SSTL-15 at 25 Ω
• SSTL-2 at 25 Ω
• 1.8 V, 1.5 V, and 1.2 V HSTL at 25 Ω
• 2.5 V and 1.8 V LVTTL at 25 Ω
• 2.5 V, 1.8 V, 1.5 V, and 1.2 LVCMOS at 25 Ω
• 1.8 V LVTTL at 16 mA
• 1.8 V and 1.5 V LVCMOS at 16 mA
• 2.5 V LVCMOS at 12 mA
• 2.5 V LVTTL at 12 mA
• 3.0 V LVCMOS at 8 mA
• 3.0 V LVTTL at 8 mA
• 3.3 V LVTTL at 4 mA or 8 mA
• 2.5 V LVTTL at 16 mA
• 2.5 V LVCMOS at 16 mA
• 3.0 V LVTTL at 12 mA
• 3.0 V LVCMOS at 12 mA
• 3.0 V LVTTL at 25 Ω
• 3.0 V LVCMOS at 25 Ω
• 3.0 V LVTTL at 16 mA
• 3.0 V LVCMOS at 16 mA
3-7
These I/O rules are applicable if you use external memory interfaces in your design.
Two GPIOs Adjacent to DQ Pin Is Disabled
This limitation is applicable to MAX 10 10M16, 10M25, 10M40, and 10M50 devices, and only if you use
DDR3 and LPDDR2 SDRAM memory standards.
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Guidelines: Dual-Purpose Configuration Pin
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Table 3-7: DDR3 and LPDDR2 Memory Interface Widths and Device Packages Where Two GPIOs Adjacent to DQ Pins Are Disabled
This table lists the combination of MAX 10 10M16, 10M25, 10M40, and 10M50 device packages, and DDR3 and
LPDDR2 memory interface widths where you cannot use two GPIO pins that are adjacent to the DQ pins.
Device Package Memory Interface Width (DDR3 and LPPDR2 only)
U324
F484
F672 x8 x8, x16, x24 x8, x16, x24
Total I/O Utilization in Bank Must Be 75 Percent or Less in Some Devices
If you use DDR3 or LPDDR2 SDRAM memory interface standards, you can generally use a maximum of
75 percent of the total number of I/O pins available in a bank. This restriction differs from device to device. In some devices packages you can use all 100 percent of the I/Os. The Quartus Prime software will output an error message if the I/O usage per bank of that device is affected by this rule.
If you use DDR2 memory interface standards, you can assign 25 percent of the I/O pins as input pins only.
To use configuration pins as user I/O pins in user mode, you have to adhere to the following guidelines.
Table 3-8: Dual-Purpose Configuration Pin Guidelines for MAX 10 Devices
Guidelines
Configuration pins during initialization:
• Tri-state the external I/O driver and drive an external pull-up resistor
(10)
or
• Use the external I/O driver to drive the pins to the state same as the external weak pull-up resistor
Pins
•
•
• nCONFIG nSTATUS
CONF_DONE
(10) If you intend to remove the external weak pull-up resistor, Altera recommends that you remove it after the device enters user mode.
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Guidelines: Clock and Data Input Signal for MAX 10 E144 Package
Guidelines
JTAG pins:
• If you intend to switch back and forth between user I/O pins and JTAG pin functions using the
JTAGEN
pin, all JTAG pins must be assigned as single-ended
I/O pins or voltage-referenced I/O pins. Schmitt trigger input is the recommended input buffer.
• JTAG pins cannot perform as JTAG pins in user mode if you assign any of the
JTAG pin as a differential I/O pin.
• You must use the JTAG pins as dedicated pins and not as user I/O pins during
JTAG programming.
• Do not toggle JTAG pin during the initialization stage.
• Put the test access port (TAP) controller in reset state by driving the
TDI
and
TMS
pins high and
TCK
pin low for at least 5 clock cycles before the initialization.
•
•
•
•
TDO
TMS
TCK
TDI
Pins
3-9
Attention: Assign all JTAG pins as single-ended I/O pins or voltage-referenced I/O pins if you enable
JTAG pin sharing feature.
Related Information
MAX 10 FPGA Configuration User Guide
Provides more information about the dual-purpose I/O pins in configuration and user modes.
There is strong inductive coupling on the MAX 10 E144 lead frame package. Glitch may occur on an input pin when an aggressor pin with strong drive strength toggles directly adjacent to it.
PLL Clock Input Pins
The PLL clock input pins are sensitive to SSN jitter. To avoid the PLL from losing lock, do not use the output pins directly on the left and right of the PLL clock input pins.
Data Input Pins
Potential glitch on the data input pin, leading to input read signal failure, can occur in the following conditions:
• The output pin directly adjacent to the data input pin is assigned an unterminated I/O standard, such as LVTTL and LVCMOS, with drive strength of 8 mA or higher.
• The output pin directly adjacent to the data input pin is assigned a terminated I/O standard, such as
SSTL, with drive strength of 8 mA or higher.
MAX 10 I/O Design Considerations
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Guidelines: Clock and Data Input Signal for MAX 10 E144 Package
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To reduce jitter on data input pin, Altera recommends the following guidelines:
• Reduce the drive strength of the directly adjacent output pin for the different unterminated I/O standards as follows:
• 4 mA or below—2.5 V, 3.0 V, and 3.3 V unterminated I/O standards
• 6 mA or below—1.2 V, 1.5 V, and 1.8 V unterminated I/O standards
• For unterminated I/O standard, assign the pins directly on the left and right of the data input pin to a non-toggling signal.
• For terminated I/O standard, you can use only one pin directly on the left or right of the data input pin as toggling signal, provided that you set the slew rate setting of this pin to “0” (slow slew rate).
Otherwise, assign the pins directly on the left and right of the data input pin to a non-toggling signal.
• Change the unterminated I/O standard data input pin to a Schmitt Trigger input buffer for better noise immunity. If you are using Schmitt Trigger input buffer on the data input pin, you can use the directly adjacent output pin with unterminated I/O standard at a maximum drive strength of 8 mA.
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You can implement your I/O design in the Quartus Prime software. The software contains tools for you to create and compile your design, and configure your device.
The Quartus Prime software allows you to prepare for device migration, set pin assignments, define placement restrictions, setup timing constraints, and customize IP cores. For more information about using the Quartus Prime software, refer to the related information.
Related Information
on page 1-1
4
The Altera GPIO Lite IP core supports the MAX 10 GPIO components. To implement the GPIOs in your design, you can customize the Altera GPIO Lite IP core to suit your requirements and instantiate it in your design.
GPIOs are I/Os used in general applications not specific to transceivers, memory-like interfaces or LVDS.
The Altera GPIO Lite IP core features the following components:
• Double data rate input/output (DDIO)—A digital component that doubles the data-rate of a communication channel.
• I/O buffers—connect the pads to the FPGA.
Figure 4-1: High Level View of Single-Ended GPIO
Core
OEIN[1:0]
DATAIN[3:0]
DATAOUT[3:0]
GPIO
OE
Path
Output
Path
Input
Path
Buffer
©
2016 Altera Corporation. All rights reserved. ALTERA, ARRIA, CYCLONE, ENPIRION, MAX, MEGACORE, NIOS, QUARTUS and STRATIX words and logos are trademarks of Altera Corporation and registered in the U.S. Patent and Trademark Office and in other countries. All other words and logos identified as trademarks or service marks are the property of their respective holders as described at www.altera.com/common/legal.html
. Altera warrants performance of its semiconductor products to current specifications in accordance with Altera's standard warranty, but reserves the right to make changes to any products and services at any time without notice. Altera assumes no responsibility or liability arising out of the application or use of any information, product, or service described herein except as expressly agreed to in writing by Altera. Altera customers are advised to obtain the latest version of device specifications before relying on any published information and before placing orders for products or services.
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Registered
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Altera GPIO Lite IP Core Data Paths
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•
•
•
Related Information
Introduction to Altera IP Cores
Provides general information about all Altera IP cores, including parameterizing, generating, upgrading, and simulating IP.
Creating Version-Independent IP and Qsys Simulation Scripts
Create simulation scripts that do not require manual updates for software or IP version upgrades.
Project Management Best Practices
Guidelines for efficient management and portability of your project and IP files.
Table 4-1: Altera GPIO Lite Data Path Modes
Data Path
Input
Output
Bidirectional
Bypass
Data goes from the delay element to the core, bypassing all double data rate I/Os (DDIOs).
Data goes from the core straight to the delay element, bypassing all DDIOs.
The output buffer drives both an output pin and an input buffer.
Mode
Single Register
The full-rate DDIO operates as a single register.
The full-rate DDIO operates as a single register.
The full-rate DDIO operates as a single register. The output buffer drives both an output pin and an input buffer.
DDR
The full-rate DDIO operates as a regular
DDIO.
The full-rate DDIO operates as a regular
DDIO.
The full-rate DDIO operates as a regular
DDIO. The output buffer drives both an output pin and an input buffer. The input buffer drives a set of three flip-flops.
If you use asynchronous clear and preset signals, all DDIOs share these same signals.
•
•
•
The pad sends data to the input buffer and the input buffer feeds the delay element. From the delay element, the data is fed to the DDIO stage, which consists of three registers:
RegAi
RegBi
RegCi
samples the data from pad_in
at the positive clock edge.
samples the data from pad_in
at the negative clock edge.
samples the data from
RegAi
at the negative clock edge.
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DDR Output Path with Output Enable
Figure 4-2: Simplified View of Altera GPIO Lite DDR Input Path
pad_in
Input
Buffer
Delay
Element inclk
DDIO_IN
D
RegAi
Q D
RegCi
Q IO_DATAIN0
D
RegBi
Q
IO_DATAIN1
4-3
Figure 4-3: Altera GPIO Lite Input Path Timing Diagram
High Z
D0 D1 D2 D3 D4 D5 D6 D7 pad_in inclk
Output from RegAi
Output from RegBi
Output from RegCi
D0
D1
D0
D2
D3
D2
D4
D5
D4
D6
D7
D6
High Z
•
•
•
RegCo
samples the data from
IO_DATAOUT0
at the positive clock edge.
RegDo
samples the data from
IO_DATAOUT1
when outclock
value is 0.
Output DDR
samples the data from
RegCo
at the positive clock edge, and from
RegDo
at the negative clock edge.
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Verifying Pin Migration Compatibility
Figure 4-4: Simplified View of Altera GPIO Lite DDR Output Path with Output Enable
IO_DATAOUT0
DDIO_OUT
RegCo
D Q
OE
Delay
Element
Output DDR
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IO_DATAOUT1 outclock
D
RegDo
Q
QB
Figure 4-5: Altera GPIO Lite Output Path Timing Diagram
OE
IO_DATAOUT1
IO_DATAOUT0 outclock
RegCo
RegD0
Output DDR
D0
D1
D2
D3
D4
D5
D6
D7
D0
D0
D1
D1
D2
D2
D3
D3
D4
D4
D5
D5
D6
D6
D7
D7
You can use the Pin Migration View window in the Quartus Prime software Pin Planner to assist you in verifying whether your pin assignments migrate to a different device successfully.
You can vertically migrate to a device with a different density while using the same device package, or migrate between packages with different densities and ball counts.
1. Open Assignments > Pin Planner and create pin assignments.
2. If necessary, perform one of the following options to populate the Pin Planner with the node names in the design:
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4-5
• Analysis & Elaboration
• Analysis & Synthesis
• Fully compile the design
3. Then, on the menu, click View > Pin Migration View.
4. To select or change migration devices:
a. Click Device to open the Device dialog box.
b. Under Migration compatibility click Migration Devices.
5. To show more information about the pins:
a. Right-click anywhere in the Pin Migration View window and select Show Columns.
b. Then, click the pin feature you want to display.
6. If you want to view only the pins, in at least one migration device, that have a different feature than the corresponding pin in the migration result, turn on Show migration differences.
7. Click Pin Finder to open the Pin Finder dialog box and find and highlight pins with specific function‐ ality.
If you want to view only the pins found and highlighted by the most recent query in the Pin Finder dialog box, turn on Show only highlighted pins.
8. To export the pin migration information to a Comma-Separated Value File (.csv), click Export.
Related Information
MAX 10 I/O Vertical Migration Support
MAX 10 I/O Implementation Guides
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You can set various parameter settings for the Altera GPIO Lite IP core to customize its behaviors, ports, and signals.
The Quartus Prime software generates your customized Altera GPIO Lite IP core according to the parameter options that you set in the parameter editor.
Related Information
on page 1-1
5
You can set the parameter settings for the Altera GPIO Lite IP core in the Quartus Prime software. There are three groups of options: General, Buffer, and Registers.
Table 5-1: Altera GPIO Lite Parameters - General
Parameter Condition Description
Data direction
Data width
—
—
Allowed
Values
• input
• output
• bidir
1 to 128
Specifies the data direction for the
GPIO.
Specifies the data width.
Table 5-2: Altera GPIO Lite Parameters - Buffer
Parameter Condition Description
Use true differential buffer Data direction = input or output
Allowed
Values
• On
• Off
If turned on, enables true differential I/O buffers and disables pseudo differential I/O buffers.
©
2016 Altera Corporation. All rights reserved. ALTERA, ARRIA, CYCLONE, ENPIRION, MAX, MEGACORE, NIOS, QUARTUS and STRATIX words and logos are trademarks of Altera Corporation and registered in the U.S. Patent and Trademark Office and in other countries. All other words and logos identified as trademarks or service marks are the property of their respective holders as described at www.altera.com/common/legal.html
. Altera warrants performance of its semiconductor products to current specifications in accordance with Altera's standard warranty, but reserves the right to make changes to any products and services at any time without notice. Altera assumes no responsibility or liability arising out of the application or use of any information, product, or service described herein except as expressly agreed to in writing by Altera. Altera customers are advised to obtain the latest version of device specifications before relying on any published information and before placing orders for products or services.
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Altera GPIO Lite Parameter Settings
Parameter Condition
Use pseudo differential buffer Data direction = output or bidir
Use bus-hold circuitry
Use open drain output
Enable oe port
Data direction = input or output
Data direction = output or bidir
Data direction = output
Enable nsleep port (only available in selected devices)
Data direction = input or bidir
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Allowed
Values
• On
• Off
• On
• Off
• On
• Off
• On
• Off
• On
• Off
Description
• If turned on in output mode— enables pseudo differential output buffers and disables true differential I/O buffers.
• If turned on in bidir mode— enables true differential input buffer and pseudo differential output buffer.
If turned on, the bus hold circuitry can weakly hold the signal on an I/O pin at its lastdriven state where the output buffer state will be 1 or 0 but not high-impedance.
If turned on, the open drain output enables the device to provide system-level control signals such as interrupt and write enable signals that can be asserted by multiple devices in your system.
If turned on, enables user input to the OE port. This option is automatically turned on for bidirectional mode.
If turned on, enables the nsleep port.
This option is available for the
10M16, 10M25, 10M40, and
10M50 devices.
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Table 5-3: Altera GPIO Lite Parameters - Registers
Parameter Condition
Register mode —
Enable aclr port
• Register mode = ddr
• On
• Off
Enable aset port
• Data direction = output or bidir
• Register mode = ddr
• Set registers to power up high
(when aclr and aset ports are not used) = off
• On
• Off
Set registers to power up high
(when aclr and aset ports are not used)
• Register mode = ddr
• Enable aclr port = off
• Enable aset port = off
• Enable sclr port = off
• On
• Off
Altera GPIO Lite Parameter Settings
5-3
Allowed
Values
• bypass
• singleregister
• ddr
Description
Specifies the register mode for the
Altera GPIO Lite IP core:
• bypass—specifies a simple wire connection from/to the buffer.
• single-register—specifies that the DDIO is used as a simple register in single data-rate mode (SDR). The Fitter may pack this register in the I/O.
• ddr— specifies that the IP core uses the DDIO.
If turned on, enables the
ACLR port for asynchronous clears.
If turned on, enables the
ASET port for asynchronous preset.
If you are not using the
ASET
ports:
ACLR
and
• On—specifies that registers power up HIGH.
• Off—specifies that registers power up LOW.
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Enable inclocken/outclocken ports
Altera GPIO Lite Parameter Settings
Parameter Condition Allowed
Values
Register mode = ddr • On
• Off
Invert din
Description
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• On—exposes the clock enable port to allow you to control when data is clocked in or out.
This signal prevents data from being passed through without your control.
• Off—clock enable port is not exposed and data always pass through the register automati‐ cally.
If turned on, inverts the data out output port.
Invert DDIO inclock
• Data direction = output
• Register mode = ddr
• Data direction = input or bidir
• Register mode = ddr
• On
• Off
• On
• Off
• On—captures the first data bit on the falling edge of the input clock.
• Off—captures the first data bit on the rising edge of the input clock.
If turned on, specifies that a single register drives the
OE
signal at the output buffer.
Use a single register to drive the output enable (oe) signal at the I/O buffer
Use DDIO registers to drive the output enable (oe) signal at the I/O buffer
• Data direction = output or bidir
• Register mode = single-register or ddr
• Use DDIO registers to drive the output enable
(oe) signal at the I/
O buffer = off
• On
• Off
• Data direction = output or bidir
• Register mode = ddr
• Use a single register to drive the output enable
(oe) signal at the I/
O buffer = off
• On
• Off
If turned on, specifies that the
DDR I/O registers drive the signal at the output buffer. The output pin is held at high impedance for an extra half clock cycle after the
OE
OE
port goes high.
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Parameter Condition
Implement DDIO input registers in hard implementa‐ tion (Only available in certain devices)
• Data direction = input or bidir
• Register mode = ddr
Allowed
Values
• On
• Off
Altera GPIO Lite Interface Signals
Description
• On—implements the DDIO input registers using hard block at the I/O edge.
• Off—implements the DDIO
5-5
input registers as soft implementation using registers in the FPGA core fabric.
This option is applicable only for
MAX 10 16, 25, 40, and 50 devices because the DDIO input registers hard block is available only in these devices. To avoid Fitter error, turn this option off for other MAX 10 devices.
Depending on parameter settings you specify, different interface signals are available for the Altera GPIO
Lite IP core.
Table 5-4: Pad Interface Signals
The pad interface connects the Altera GPIO Lite IP core to the pads.
Signal Name Direction
pad_in
Input
Description
Input pad port if you use the input path.
pad_in_b
Input
Input negative pad port if you use the input path and enable the true or pseudo differential buffers.
pad_out pad_out_b pad_io pad_io_b
Output
Output pad port if you use the output path.
Output
Output negative pad port if you use the output path and enable the true of pseudo differential buffers.
Bidirectional Bidirectional pad port if you use bidirectional paths.
Bidirectional Bidirectional negative pad port if you use bidirectional paths and enable true or pseudo differential buffers.
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Altera GPIO Lite Interface Signals
Table 5-5: Data Interface Signals
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The data interface is an input or output interface from the Altera GPIO Lite IP core to the FPGA core.
Signal Name Direction Description
din
Input
Data received from the input pin.
Signal width for each input pin:
• DDR mode—2
• Other modes—1 dout
Output
Data to send out through the output pin.
Signal width for each output pin:
• DDR mode—2
• Other modes—1 oe
Input
Control signal that enables the output buffer. This signal is active HIGH.
nsleep
Input
Control signal that enables the input buffer. This signal is active LOW.
This signal is available for the 10M16, 10M25, 10M40, and
10M50 devices.
Table 5-6: Clock Interface Signals
The clock interface is an input clock interface. It consists of different signals, depending on the configuration. The
Altera GPIO Lite IP core can have zero, one, two, or four clock inputs. Clock ports appear differently in different configurations to reflect the actual function performed by the clock signal.
Signal Name Direction Description
inclock
Input
Input clock that clocks the registers in the input path.
inclocken
Input
Control signal that controls when data is clocked in. This signal is active HIGH.
outclock
Input
Input clock that clocks the registers in the output path.
ouctlocken
Input
Control signal that controls when data is clocked out. This signal is active HIGH.
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Table 5-7: Reset Interface Signals
Altera GPIO Lite Interface Signals
The reset interface connects the Altera GPIO Lite IP core to the DDIOs.
Signal Name Direction
aclr
Input
Description
Control signal for asynchronous clear that sets the register output state to 0. This signal is active HIGH.
aset
Input
Control signal for asynchronous preset that sets the register output state to 1. This signal is active HIGH.
sclr
Input
Control signal for synchronous clear that sets the register output to 0. This signal is active HIGH.
5-7
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If an IP core version is not listed, the user guide for the previous IP core version applies.
IP Core Version User Guide
15.1
15.0
14.1
MAX 10 General Purpose I/O User Guide
MAX 10 General Purpose I/O User Guide
MAX 10 General Purpose I/O User Guide
A
©
2016 Altera Corporation. All rights reserved. ALTERA, ARRIA, CYCLONE, ENPIRION, MAX, MEGACORE, NIOS, QUARTUS and STRATIX words and logos are trademarks of Altera Corporation and registered in the U.S. Patent and Trademark Office and in other countries. All other words and logos identified as trademarks or service marks are the property of their respective holders as described at www.altera.com/common/legal.html
. Altera warrants performance of its semiconductor products to current specifications in accordance with Altera's standard warranty, but reserves the right to make changes to any products and services at any time without notice. Altera assumes no responsibility or liability arising out of the application or use of any information, product, or service described herein except as expressly agreed to in writing by Altera. Altera customers are advised to obtain the latest version of device specifications before relying on any published information and before placing orders for products or services.
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101 Innovation Drive, San Jose, CA 95134
ISO
9001:2008
Registered
2016.05.02
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Version Changes
2016.05.02 • Updated the list of supported I/O standards to specify I/O standards that are supported only in dual power supply MAX 10 devices.
• Updated the names of emulated differential I/O standards to improve clarity.
• Updated the topic about the I/O standards voltage and pin support to clarify that the I/O standards that a pin type supports depends on pin's I/O bank.
• Updated the setting information for PCI clamp diode:
• On by default for input pins for all supported I/O standards
• Off by default for output pins for all supported I/O standards, except 3.0 V PCI
• Updated the topic about the ADC I/O restriction:
• Added the list of devices with physics-based rules support from
Quartus Prime version 15.0.1.
• Clarified that the table listing the percentage of GPIOs allowed in bank 8 is an example for the F484 package. For all packages, the Quartus Prime software displays a warning message if you exceed the allowed GPIO percentage.
B
©
2016 Altera Corporation. All rights reserved. ALTERA, ARRIA, CYCLONE, ENPIRION, MAX, MEGACORE, NIOS, QUARTUS and STRATIX words and logos are trademarks of Altera Corporation and registered in the U.S. Patent and Trademark Office and in other countries. All other words and logos identified as trademarks or service marks are the property of their respective holders as described at www.altera.com/common/legal.html
. Altera warrants performance of its semiconductor products to current specifications in accordance with Altera's standard warranty, but reserves the right to make changes to any products and services at any time without notice. Altera assumes no responsibility or liability arising out of the application or use of any information, product, or service described herein except as expressly agreed to in writing by Altera. Altera customers are advised to obtain the latest version of device specifications before relying on any published information and before placing orders for products or services.
www.altera.com
101 Innovation Drive, San Jose, CA 95134
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9001:2008
Registered
B-2
Document Revision History for MAX 10 General Purpose I/O User Guide
Date
November 2015
June 2015
May 2015
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Version Changes
2015.11.02 • Added PCI clamp diode support for the 3.3 V and 2.5 V Schmitt
Trigger I/O standards.
• Added a table that summarizes the programmable I/O buffer features and settings.
• Updated the topics about V
CCIO
range consideration and VREF I/O standards restriction with guidelines for using different V
CCIO supplies in bank 1A and bank 1B.
• Added guidelines topic about using the clock and input pins in the
E144 package.
• Added the Enable nsleep port parameter option.
• Removed the topics about the IP catalog and parameter editor, generating IP cores, and the files generated by the IP core, and added a link to
Introduction to Altera IP Cores
.
• Changed instances of
Quartus II
to
Quartus Prime
.
2015.06.10 • Added related link to the MAX 10 device pin-outs in topic about I/
O banks locations. The device pin-out files provide more informa‐ tion about available I/O pins in each I/O bank.
• Updated the ADC I/O restriction guidelines topic.
2015.05.04 • Removed the F672 package of the MAX 10 10M25 device.
• Updated footnote for LVDS (dedicated) in the table listing the supported I/O standards to clarify that you can use LVDS receivers on all I/O banks.
• Added missing footnote number for the DQS column of the 3.3 V
Schmitt Trigger row in the table that lists the I/O standards voltage levels and pin support.
• Added a table listing the I/O standards and current strength settings that support programmable output slew rate control.
• Updated the topic about external memory interface I/O restrictions to add x24 memory interface width to the F484 package.
• Added topic about the programmable differential output voltage.
• Updated the guidelines for voltage-referenced I/O standards to add a list of device packages that do not support voltage-referenced I/O standards.
• Updated the topic about the I/O restriction rules to remove statements about the differential pad placement rules.
• Renamed the input_ena
signal name to nsleep
and updated the relevant description.
• Updated the description for the Invert DDIO inclock parameter of the Altera GPIO Lite IP core.
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December 2014
September 2014
Document Revision History for MAX 10 General Purpose I/O User Guide
B-3
Version Changes
2014.12.15 Updated the topic about the ADC I/O restriction:
• Added information about implementation of physics-based rules in the Quartus Prime software.
• Updated the list of I/O standards groups for the ADC I/O restric‐ tion.
2014.09.22 Initial release.
Document Revision History for MAX 10 General Purpose I/O User Guide
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TOC-2
Contents
MAX 10 High-Speed LVDS I/O Overview..........................................................1-1
MAX 10 High-Speed LVDS Architecture and Features......................................2-1
Emulated RSDS, Emulated Mini-LVDS, and Emulated PPDS Transmitter External
Altera Corporation
TOC-3
MAX 10 LVDS Transmitter and Receiver Design...............................................5-1
MAX 10 High-Speed LVDS Board Design Considerations................................6-1
MAX 10 High-Speed LVDS I/O User Guide Archives....................................... A-1
Document Revision History for MAX 10 High-Speed LVDS I/O User Guide..
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The MAX
®
10 device family supports high-speed LVDS protocols through the LVDS I/O banks and the
Altera Soft LVDS IP core.
Table 1-1: Summary of LVDS I/O Buffers Support in MAX 10 I/O Banks
I/O Buffer Type
True LVDS input buffer
True LVDS output buffer
Emulated LVDS output buffer
I/O Bank Support
All I/O banks
Only bottom I/O banks
All I/O banks
1
The LVDS I/O standards support differs between MAX 10 D and S variants. Refer to related information for more details.
•
•
•
•
•
•
•
Related Information
MAX 10 High-Speed LVDS Architecture and Features
Provides information about the high-speed LVDS architecture and the features supported by the device.
MAX 10 LVDS Transmitter Design
on page 3-1
Provides information and guidelines for implementing LVDS transmitter in MAX 10 devices using the
Altera Soft LVDS IP core.
on page 4-1
Provides information and guidelines for implementing LVDS receiver in MAX 10 devices using the
Altera Soft LVDS IP core.
MAX 10 LVDS Transmitter and Receiver Design
Provides design guidelines for implementing both LVDS transmitters and receivers in the same MAX
10 device.
Altera Soft LVDS IP Core References
on page 7-1
Lists the parameters and signals of Altera Soft LVDS IP core for MAX 10 devices.
MAX 10 LVDS SERDES I/O Standards Support
on page 2-7
Lists the supported LVDS I/O standards and the support in different MAX 10 device variants.
MAX 10 High-Speed LVDS I/O User Guide Archives
on page 8-1
Provides a list of user guides for previous versions of the Altera Soft LVDS IP core.
©
2016 Intel Corporation. All rights reserved. Intel, the Intel logo, Altera, Arria, Cyclone, Enpirion, MAX, Megacore, NIOS, Quartus and Stratix words and logos are trademarks of Intel Corporation in the US and/or other countries. Other marks and brands may be claimed as the property of others. Intel warrants performance of its FPGA and semiconductor products to current specifications in accordance with Intel's standard warranty, but reserves the right to make changes to any products and services at any time without notice. Intel assumes no responsibility or liability arising out of the application or use of any information, product, or service described herein except as expressly agreed to in writing by Intel. Intel customers are advised to obtain the latest version of device specifications before relying on any published information and before placing orders for products or services.
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1-2
Altera Soft LVDS Implementation Overview
You can implement LVDS applications in MAX 10 devices as transmitter-only, receiver-only, or a combination of transmitters and receivers.
Figure 1-1: MAX 10 LVDS Implementation Overview
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Altera Soft LVDS
LVDS Transmitter
Implementation
LVDS Receiver
Implementation
LVDS Transmitter and Receiver
Implementation
Altera Corporation
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The MAX 10 devices use registers and logic in the core fabric to implement LVDS input and output interfaces.
• For LVDS transmitters and receivers, MAX 10 devices use the the double data rate I/O (DDIO) registers that reside in the I/O elements (IOE). This architecture improves performance with regards to the receiver input skew margin (RSKM) or transmitter channel-to-channel skew (TCCS).
• For the LVDS serializer/deserializer (SERDES), MAX 10 devices use logic elements (LE) registers.
•
•
Related Information
MAX 10 High-Speed LVDS I/O Overview
on page 1-1
MAX 10 LVDS SERDES I/O Standards Support
on page 2-7
Lists the supported LVDS I/O standards and the support in different MAX 10 device variants.
2
The LVDS channels available vary among MAX 10 devices. All I/O banks in MAX 10 devices support true
LVDS input buffers and emulated LVDS output buffers. However, only the bottom I/O banks support true
LVDS output buffers.
Table 2-1: LVDS Buffers in MAX 10 Devices
This table lists the LVDS buffer support for I/O banks on each side of the devices.
©
2016 Intel Corporation. All rights reserved. Intel, the Intel logo, Altera, Arria, Cyclone, Enpirion, MAX, Megacore, NIOS, Quartus and Stratix words and logos are trademarks of Intel Corporation in the US and/or other countries. Other marks and brands may be claimed as the property of others. Intel warrants performance of its FPGA and semiconductor products to current specifications in accordance with Intel's standard warranty, but reserves the right to make changes to any products and services at any time without notice. Intel assumes no responsibility or liability arising out of the application or use of any information, product, or service described herein except as expressly agreed to in writing by Intel. Intel customers are advised to obtain the latest version of device specifications before relying on any published information and before placing orders for products or services.
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9001:2008
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2-2
MAX 10 LVDS Channels Support
Product Line Package
10M02
V36
M153
U169
U324
E144
Side
Right
Left
Bottom
Top
Right
Left
Bottom
Top
Right
Left
Bottom
Top
Right
Left
Bottom
Top
Right
Left
Bottom
Top
0
0
0
9
0
7
9
0
0
0
0
9
0
0
0
0
3
0
0
0
TX
True LVDS Pairs
RX
20
16
10
12
17
15
14
13
24
11
12
12
12
13
12
3
3
1
3
12
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Emulated LVDS Pairs
20
16
10
12
17
15
14
13
24
11
12
12
12
13
12
3
3
1
3
12
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Product Line Package
10M04
M153
U169
U324
F256
E144
Side
Right
Left
Bottom
Top
Right
Left
Bottom
Top
Right
Left
Bottom
Top
Right
Left
Bottom
Top
Right
Left
Bottom
Top
MAX 10 LVDS Channels Support
TX
True LVDS Pairs
RX
0
0
0
13
15
0
0
0
0
0
10
9
0
0
0
0
9
0
0
0
19
20
8
12
31
28
28
19
22
11
10
17
15
14
27
12
12
12
13
12
2-3
Emulated LVDS Pairs
19
20
8
12
31
28
28
19
22
11
10
17
15
14
27
12
12
12
13
12
MAX 10 High-Speed LVDS Architecture and Features
Send Feedback
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2-4
MAX 10 LVDS Channels Support
Product Line Package
10M08
V81
M153
U169
U324
F256
E144
F484
Side
Left
Bottom
Top
Right
Left
Bottom
Top
Right
Left
Bottom
Right
Left
Bottom
Top
Right
Left
Bottom
Top
Right
Top
Right
Left
Bottom
Top
Right
Left
Bottom
Top
TX
True LVDS Pairs
RX
0
10
0
0
0
0
13
0
0
15
0
0
0
15
9
0
0
0
0
9
0
0
0
0
7
0
0
0
11
10
27
19
20
8
12
33
28
28
28
28
19
22
17
15
14
27
31
12
12
13
12
6
7
5
7
12
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Emulated LVDS Pairs
11
10
27
19
20
8
12
33
28
28
28
28
19
22
17
15
14
27
31
12
12
13
12
6
7
5
7
12
Altera Corporation
MAX 10 High-Speed LVDS Architecture and Features
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Product Line Package
10M16
U169
U324
F256
E144
F484
Side
Right
Left
Bottom
Top
Right
Left
Bottom
Top
Right
Left
Bottom
Top
Right
Left
Bottom
Top
Right
Left
Bottom
Top
MAX 10 LVDS Channels Support
TX
True LVDS Pairs
RX
0
0
0
10
13
0
0
0
0
0
22
15
0
0
0
0
9
0
0
0
11
10
39
38
22
19
20
8
12
32
42
31
28
28
19
12
17
15
14
27
2-5
Emulated LVDS Pairs
11
10
39
38
22
19
20
8
12
32
42
31
28
28
19
12
17
15
14
27
MAX 10 High-Speed LVDS Architecture and Features
Send Feedback
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2-6
MAX 10 LVDS Channels Support
Product Line Package
10M25
10M40
F256
E144
F484
F256
E144
F484
F672
Side
Left
Bottom
Top
Right
Left
Bottom
Top
Right
Left
Bottom
Right
Left
Bottom
Top
Right
Left
Bottom
Top
Right
Top
Right
Left
Bottom
Top
Right
Left
Bottom
Top
TX
True LVDS Pairs
RX
0
24
0
0
0
0
10
0
0
30
0
0
0
13
24
0
0
0
0
10
0
0
0
0
13
0
0
0
36
46
53
11
10
41
48
70
60
58
19
20
9
12
48
36
46
19
22
12
11
10
41
19
22
19
20
8
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Emulated LVDS Pairs
36
46
53
11
10
41
48
70
60
58
19
20
9
12
48
36
46
19
22
12
11
10
41
19
22
19
20
8
Altera Corporation
MAX 10 High-Speed LVDS Architecture and Features
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Product Line
10M50
Package
F256
E144
F484
F672
Side
Right
Left
Bottom
Top
Right
Left
Bottom
Top
Right
Left
Bottom
Top
Right
Left
Bottom
Top
MAX 10 LVDS SERDES I/O Standards Support
TX
True LVDS Pairs
RX
24
0
0
0
0
0
30
10
0
0
0
0
13
0
0
0
48
36
46
53
70
60
58
12
11
10
41
19
22
19
20
9
2-7
Emulated LVDS Pairs
48
36
46
53
70
60
58
12
11
10
41
19
22
19
20
9
•
•
Related Information
MAX 10 Device Pin-Out Files
Provides pin-out files for each MAX 10 device.
MAX 10 High-Speed LVDS I/O Location
on page 2-11
The MAX 10 D and S device variants support different LVDS I/O standards. All I/O banks in MAX 10 devices support true LVDS input buffers and emulated LVDS output buffers. However, only the bottom
I/O banks support true LVDS output buffers.
Table 2-2: MAX 10 LVDS I/O Standards Support
Single and dual supply MAX 10 devices support different I/O standards. For more information about single and dual supply devices, refer to the device overview.
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MAX 10 LVDS SERDES I/O Standards Support
I/O Standard
True LVDS
Emulated LVDS
(three resistors)
All
True RSDS
Emulated RSDS
(single resistor)
Bottom
All
Emulated RSDS
(three resistors)
All
True Mini-LVDS
Emulated Mini-
LVDS (three resistors)
PPDS
Emulated PPDS
(three resistors)
Bus LVDS
Bottom
All
Bottom
All
All
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
LVPECL
I/O Bank TX
All
All
Bottom banks only
—
RX
Yes
—
—
—
—
—
—
—
—
Yes
Yes
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MAX 10 Device
Support
Dual
Supply
Device
Yes
Single
Supply
Device
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
—
Yes
—
—
—
—
Notes
• All I/O banks support true LVDS input buffers.
• Only the bottom I/O banks support true LVDS output buffers.
All I/O banks support emulated LVDS output buffers.
—
All I/O banks support emulated RSDS output buffers.
All I/O banks support emulated RSDS output buffers.
—
All I/O banks support emulated Mini-LVDS output buffers.
—
—
Yes Yes
Yes Yes
• Bus LVDS (BLVDS) output uses two singleended outputs with the second output programmed as inverted.
• BLVDS input uses LVDS input buffer.
• You can tristate BLVDS output.
Supported only on dual function clock input pins.
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I/O Standard I/O Bank TX
TMDS
Sub-LVDS
SLVS
All
All
All
—
Yes
Yes
RX
Yes
Yes
Yes
MAX 10 LVDS SERDES I/O Standards Support
MAX 10 Device
Support
Dual
Supply
Device
Yes
Single
Supply
Device
—
Notes
Yes —
2-9
• Requires external termination but does not require V
REF
.
• Requires external level shifter to support 3.3 V
TMDS input. This level shifter must convert the
TMDS signal from ACcoupled to DC-coupled before you connect it to the MAX 10 input buffer.
• TMDS receiver support uses dedicated 2.5 V
LVDS input buffer.
• Transmitter supports only emulated Sub-LVDS using emulated 1.8 V differential signal as output.
• Requires external output termination.
• Does not require V
REF
.
• Sub-LVDS receiver support uses dedicated
2.5 V LVDS input buffer.
Yes —
• SLVS transmitter support uses emulated LVDS output.
• Requires external termination but does not require V
REF
.
• SLVS receiver support uses dedicated 2.5 V
LVDS input buffer.
MAX 10 High-Speed LVDS Architecture and Features
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MAX 10 High-Speed LVDS Circuitry
I/O Standard
HiSpi
I/O Bank
All
TX
—
RX
Yes
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MAX 10 Device
Support
Dual
Supply
Device
Yes
Single
Supply
Device
—
Notes
• Only input is supported because HiSpi is a unidirectional I/O standard.
• Requires external termination but does not require V
REF
.
• HiSpi receiver support uses dedicated 2.5 V
LVDS input buffer.
•
•
•
•
•
•
•
•
•
Related Information
MAX 10 FPGA Device Overview
Emulated LVDS External Termination
Emulated RSDS, Emulated Mini-LVDS, and Emulated PPDS Transmitter External Termination
page 3-4
TMDS Receiver External Termination
Sub-LVDS Transmitter External Termination
on page 3-3
Sub-LVDS Receiver External Termination
on page 4-3
SLVS Transmitter External Termination
on page 3-4
SLVS Receiver External Termination
HiSpi Receiver External Termination
on page 4-4
The LVDS solution uses the I/O elements and registers in the MAX 10 devices. The Altera Soft LVDS IP core implements the serializer and deserializer as soft SERDES blocks in the core logic.
The MAX 10 devices do not contain dedicated serialization or deserialization circuitry:
• You can use I/O pins and core fabric to implement a high-speed differential interface in the device.
• The MAX 10 solution uses shift registers, internal PLLs, and I/O elements to perform the serial-toparallel and parallel-to-serial conversions of incoming and outgoing data.
• The Quartus
®
Prime software uses the parameter settings of the Altera Soft LVDS IP core to automati‐ cally construct the differential SERDES in the core fabric.
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MAX 10 High-Speed LVDS Architecture and Features
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MAX 10 High-Speed LVDS I/O Location
2-11
Figure 2-1: Soft LVDS SERDES
This figure shows a transmitter and receiver block diagram for the soft LVDS SERDES circuitry with the interface signals of the transmitter and receiver data paths.
tx_in
10 bits maximum data width tx_coreclock
FPGA
Fabric
rx_out rx_outclock
10
10 tx_in
ALTERA_SOFT_LVDS
tx_out inclock
C0
C1 rx_out
ALTERA_SOFT_LVDS
rx_in inclock
C0
C1
LVDS Transmitter
LVDS Receiver
tx_out
–
+ rx_in
C0
C1
ALTPLL inclock areset rx_inclock / tx_inclock pll_areset
Related Information
MAX 10 Clocking and PLL User Guide
Provides more information about the PLL and the PLL output counters.
The I/O banks in MAX 10 devices support true LVDS input and emulated LVDS output on all I/O banks.
Only the bottom I/O banks support true LVDS output.
MAX 10 High-Speed LVDS Architecture and Features
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2-12
MAX 10 High-Speed LVDS I/O Location
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Figure 2-2: LVDS Support in I/O Banks of 10M02 Devices
This figure shows a top view of the silicon die. Each bank is labeled with the actual bank number. LVPECL support only in banks 2 and 6.
8
1
2
3
6
5
LVDS
Emulated LVDS
RSDS
Emulated RSDS
Mini-LVDS
Emulated Mini-LVDS
PPDS
Emulated PPDS
BLVDS
LVPECL
TMDS
Sub-LVDS
SLVS
HiSpi
TX RX
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MAX 10 High-Speed LVDS I/O Location
2-13
Figure 2-3: LVDS Support in I/O Banks of 10M04 and 10M08 Devices
This figure shows a top view of the silicon die. Each bank is labeled with the actual bank number. LVPECL support only in banks 2 and 6.
8 7
1A
1B
2
3 4
6
5
LVDS
Emulated LVDS
RSDS
Emulated RSDS
Mini-LVDS
Emulated Mini-LVDS
PPDS
Emulated PPDS
BLVDS
LVPECL
TMDS
Sub-LVDS
SLVS
HiSpi
TX RX
MAX 10 High-Speed LVDS Architecture and Features
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2-14
Differential I/O Pins in Low Speed Region
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Figure 2-4: LVDS Support in I/O Banks of 10M16, 10M25, 10M40, and 10M50 Devices
This figure shows a top view of the silicon die. Each bank is labeled with the actual bank number. LVPECL support only in banks 2, 3, 6, and 8.
8 7
1A
6
1B
2
3 4
5
OCT
LVDS
Emulated LVDS
RSDS
Emulated RSDS
Mini-LVDS
Emulated Mini-LVDS
PPDS
Emulated PPDS
BLVDS
LVPECL
TMDS
Sub-LVDS
SLVS
HiSpi
TX RX
•
•
Related Information
PLL Specifications
Provides PLL performance information for MAX 10 devices.
High-Speed I/O Specifications
Provides minimum and maximum data rates for different data widths in MAX 10 devices.
Some of the differential I/O pins are located in the low speed region of the MAX 10 device.
• For each user I/O pin (excluding configuration pin) that you place in the low speed region, the Quartus
Prime software generates an informational warning message.
• Refer to the device pinout to identify the low speed I/O pins.
• Refer to the device datasheet for the performance information of these I/O pins.
•
•
Related Information
MAX 10 Device Pin-Out Files
Provides pin-out files for each MAX 10 device.
MAX 10 Device Datasheet
Altera Corporation
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•
Differential I/O Pins in Low Speed Region
MAX 10 I/O Banks Locations, MAX 10 General Purpose I/O User Guide
Shows the locations of the high speed and low speed I/O banks.
2-15
MAX 10 High-Speed LVDS Architecture and Features
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2016.10.31
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You can implement transmitter-only applications using the MAX 10 LVDS solution. You can use the
Altera Soft LVDS IP core to instantiate soft SERDES circuitry. The soft SERDES circuitry works with the clocks and differential I/O pins to create a high-speed differential transmitter circuit.
•
•
Related Information
MAX 10 High-Speed LVDS I/O Overview
on page 1-1
MAX 10 LVDS SERDES I/O Standards Support
on page 2-7
Lists the supported LVDS I/O standards and the support in different MAX 10 device variants.
3
The LVDS transmitter circuitry uses the I/O elements and registers in the MAX 10 devices. The Altera Soft
LVDS IP core implements the serializer as a soft SERDES block in the core logic.
Related Information
MAX 10 High-Speed LVDS Circuitry
You can program some features of the I/O buffers and pins in MAX 10 devices according to your design requirements. For high-speed LVDS transmitter applications, you can program the pre-emphasis setting.
The differential output voltage (V
OD
) setting and the output impedance of the driver set the output current limit of a high-speed transmission signal. At a high frequency, the slew rate may not be fast enough to reach the full V
OD
level before the next edge, producing pattern-dependent jitter. Pre-emphasis momentarily boosts the output current during switching to increase the output slew rate.
Pre-emphasis increases the amplitude of the high-frequency component of the output signal. This increase compensates for the frequency-dependent attenuation along the transmission line.
The overshoot introduced by the extra current occurs only during change of state switching. This overshoot increases the output slew rate but does not ring, unlike the overshoot caused by signal reflection. The amount of pre-emphasis required depends on the attenuation of the high-frequency component along the transmission line.
©
2016 Intel Corporation. All rights reserved. Intel, the Intel logo, Altera, Arria, Cyclone, Enpirion, MAX, Megacore, NIOS, Quartus and Stratix words and logos are trademarks of Intel Corporation in the US and/or other countries. Other marks and brands may be claimed as the property of others. Intel warrants performance of its FPGA and semiconductor products to current specifications in accordance with Intel's standard warranty, but reserves the right to make changes to any products and services at any time without notice. Intel assumes no responsibility or liability arising out of the application or use of any information, product, or service described herein except as expressly agreed to in writing by Intel. Intel customers are advised to obtain the latest version of device specifications before relying on any published information and before placing orders for products or services.
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3-2
Programmable Differential Output Voltage
Figure 3-1: LVDS Output with Programmable Pre-Emphasis
Voltage boost from pre-emphasis
V
P
OUT
V
OD
OUT
V
P
Differential output voltage (peak–peak)
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Table 3-1: Quartus Prime Software Assignment for Programmable Pre-Emphasis
Field Assignment
To
Assignment name
Allowed values tx_out
Programmable Pre-emphasis
0 (disabled), 1 (enabled). Default is 1.
The programmable V
V
OD
OD
settings allow you to adjust the output eye opening to optimize the trace length and power consumption. A higher V
OD
swing reduces power consumption.
swing improves voltage margins at the receiver end, and a smaller
Figure 3-2: Differential V
OD
This figure shows the V
OD
of the differential LVDS output.
Single-Ended Waveform
Positive Channel (p)
V
OD
Negative Channel (n)
V
CM
Ground
Differential Waveform
V
OD
V
OD
(diff peak - peak) = 2 x V
OD
(single-ended)
V
OD p - n = 0 V
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LVDS Transmitter I/O Termination Schemes
3-3
You can statically adjust the V of the differential signal by changing the V
Prime software Assignment Editor.
OD
settings in the Quartus
Table 3-2: Quartus Prime Software Assignment Editor—Programmable V
OD
Field Assignment
To
Assignment name
Allowed values tx_out
Programmable Differential Output Voltage (V
OD
)
0 (low), 1 (medium), 2 (high). Default is 2.
For transmitter applications in MAX 10 devices, you must implement external termination for some I/O standards.
The emulated LVDS transmitter requires a three-resistor external termination scheme.
Figure 3-3: External Termination for Emulated LVDS Transmitter
In this figure, R
S
= 120 Ω and R
P
= 170 Ω.
RS
50 Ω
RP
100 Ω
50 Ω
RS
Emulated LVDS on FPGA
The Sub-LVDS transmitter requires a three-resistor external termination scheme.
LVDS peer
MAX 10 LVDS Transmitter Design
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3-4
SLVS Transmitter External Termination
Figure 3-4: External Termination for Sub-LVDS Transmitter
1.8 V
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Z
0
= 50 Ω
267 Ω
TX 121 Ω 100 Ω RX
Z
0
= 50 Ω
267 Ω
Sub-LVDS on FPGA Sub-LVDS peer
The SLVS transmitter requires a three-resistor external termination scheme.
Figure 3-5: External Termination for SLVS Transmitter
2.5 V
Z
0
= 50 Ω
221 Ω
2.5 V
48.7 Ω
15 Ω
TX 100 Ω
Z
0
= 50 Ω
221 Ω
48.7 Ω
15 Ω
SLVS on FPGA
2.5 V
RX
SLVS peer
The emulated RSDS, emulated mini-LVDS, or emulated PPDS transmitter requires a three-resistor external termination scheme. You can also use a single-resistor external termination for the emulated
RSDS transmitter.
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LVDS Transmitter FPGA Design Implementation
Figure 3-6: External Termination for Emulated RSDS, Mini-LVDS, or PPDS Transmitter
In this figure, R
S
is 120 Ω and R
P
is 170 Ω.
3-5
RS
50 Ω
RP 100 Ω
50 Ω
RS
Emulated RSDS,
Mini-LVDS, or PPDS on FPGA
Figure 3-7: Single-Resistor External Termination for Emulated RSDS Transmitter
RSDS, Mini-LVDS, or
PPDS peer
100 Ω
50 Ω
50 Ω
100 Ω
Emulated RSDS on FPGA
RSDS peer
MAX 10 devices use a soft SERDES architecture to support high-speed I/O interfaces. The Quartus Prime software creates the SERDES circuits in the core fabric by using the Altera Soft LVDS IP core. To improve the timing performance and support the SERDES, MAX 10 devices use the I/O registers and LE registers in the core fabric.
MAX 10 LVDS Transmitter Design
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Altera Soft LVDS IP Core in Transmitter Mode
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In the Quartus Prime software, you can design your high-speed transmitter interfaces using the Altera Soft
LVDS IP core. This IP core uses the resources optimally in the MAX 10 devices to create the high-speed
I/O interfaces.
• You can use the Altera Soft LVDS parameter editor to customize your serializer based on your design requirements.
• The high-speed I/O interface created using the Altera Soft LVDS IP core always sends the most signifi‐ cant bit (MSB) of your parallel data first.
•
•
•
•
Related Information
Altera Soft LVDS Parameter Settings
Introduction to Altera IP Cores
on page 7-1
Provides general information about all Altera FPGA IP cores, including parameterizing, generating, upgrading, and simulating IP cores.
Creating Version-Independent IP and Qsys Simulation Scripts
Create simulation scripts that do not require manual updates for software or IP version upgrades.
Project Management Best Practices
Guidelines for efficient management and portability of your project and IP files.
You can create the LVDS interface components by instantiating the Altera Soft LVDS IP core with an internal or external PLL.
Instantiate Altera Soft LVDS IP Core with Internal PLL
You can set the Altera Soft LVDS IP core to build the SERDES components and instantiate the PLL internally.
• To use this method, turn off the Use external PLL option in the PLL Settings tab and set the necessary settings in the PLL Settings and Transmitter Settings tab.
• The Altera Soft LVDS IP core integrates the PLL into the LVDS block.
• The drawback of this method is that you can use the PLL only for the particular LVDS instance.
Instantiate Altera Soft LVDS IP Core with External PLL
You can set the Altera Soft LVDS IP core to build only the SERDES components but use an external PLL source.
• To use this method, turn on the Use external PLL option in the PLL Settings tab.
• Follow the required clock setting to the input ports as listed in the notification panel.
• You can create your own clocking source using the ALTPLL IP core.
• Use this method to optimize PLL usage with other functions in the core.
•
•
Related Information
MAX 10 Clocking and PLL User Guide
Provides more information about the PLL and the PLL output counters.
MAX 10 Clocking and PLL User Guide
Provides more information about the PLL and the PLL output counters.
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Guidelines: LVDS TX Interface Using External PLL
3-7
You can instantiate the Altera Soft LVDS IP core with the Use External PLL option. Using external PLL, you can control the PLL settings. For example, you can dynamically reconfigure the PLL to support different data rates and dynamic phase shifts. To use this option, you must instantiate the ALTPLL IP core to generate the various clock signals.
If you turn on the Use External PLL option for the Altera Soft LVDS transmitter, you require the following signals from the ALTPLL IP core:
• Serial clock input to the tx_inclock
port of the Altera Soft LVDS transmitter.
• Parallel clock used to clock the transmitter FPGA fabric logic and connected to the tx_syncclock port.
Related Information
MAX 10 Clocking and PLL User Guide
Provides more information about the PLL and the PLL output counters.
ALTPLL Signal Interface with Altera Soft LVDS Transmitter
You can choose any of the PLL output clock ports to generate the LVDS interface clocks.
If you use the ALTPLL IP core as the external PLL source of the Altera Soft LVDS transmitter, use the source-synchronous compensation mode.
Table 3-3: Example: Signal Interface between ALTPLL and Altera Soft LVDS Transmitter
From the ALTPLL IP Core To the Altera Soft LVDS Transmitter
Fast clock output ( c0
)
The fast clock output ( c0
) can only drive tx_inclock
on the Altera Soft LVDS transmitter.
tx_inclock
Slow clock output ( c1
) tx_syncclock
Determining External PLL Clock Parameters for Altera Soft LVDS Transmitter
To determine the ALTPLL IP core clock parameter for the Altera Soft LVDS IP core transmitter, follow these steps in your design:
1. Instantiate the Altera Soft LVDS IP core transmitter using internal PLL.
2. Compile the design up to TimeQuest timing analysis.
3. In the Table of Contents section of the Compilation Report window, navigate to TimeQuest Timing
Analyzer > Clocks.
4. Note the clock parameters used by the internal PLL for the Altera Soft LVDS IP core transmitter.
In the list of clocks, clk0
is the fast clock.
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Initializing the Altera Soft LVDS IP Core
Figure 3-8: Clock Parameters Example for Altera Soft LVDS Transmitter
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Configure the ALTPLL output clocks with the parameters you noted in this procedure and connect the clock outputs to the correct Altera Soft LVDS clock input ports.
The PLL locks to the reference clock before the Altera Soft LVDS IP core implements the SERDES blocks for data transfer.
During device initialization the PLL starts to lock to the reference clock and becomes operational when it achieves lock during user mode. If the clock reference is not stable, it corrupts the phase shifts of the PLL output clock. This phase shifts corruption can cause failure and corrupt data transfer between the highspeed LVDS domain and the low-speed parallel domain.
To avoid data corruption, follow these steps when initializing the Altera Soft LVDS IP core:
1. Assert the pll_areset
signal for at least 10 ns.
2. After at least 10 ns, deassert the pll_areset
signal.
3. Wait until the PLL lock becomes stable.
After the PLL lock port asserts and is stable, the SERDES blocks are ready for operation.
The LVDS I/O standard enables high-speed transmission of data that results in better overall system performance. To take advantage of fast system performance, you must analyze the timing for high-speed signals. Timing analysis for the differential block is different than traditional synchronous timing analysis techniques.
The basis of the source synchronous timing analysis is the skew between the data and the clock signals instead of the clock-to-output setup times. High-speed differential data transmission requires the use of timing parameters provided by IC vendors and is strongly influenced by board skew, cable skew, and clock jitter.
The receiver input skew margin (RSKM) calculation uses the transmitter channel-to-channel skew (TCCS)
—an important parameter based on the MAX 10 transmitter in a source-synchronous differential interface. You can get the TCCS value from the device datasheet.
Related Information
MAX 10 Device Datasheet
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Guidelines: LVDS Transmitter Channels Placement
3-9
To maintain an acceptable noise level on the V
CCIO ended I/O pins in relation to differential pads.
supply, observe the placement restrictions for single-
Altera recommends that you create a Quartus Prime design, specify your device I/O assignments, and compile your design to validate your pin placement. The Quartus Prime software verifies your pin connections against the I/O assignment and placement rules to ensure that the device will operate properly.
You can use the Quartus Prime Pin Planner Package view to ease differential I/O assignment planning:
• On the View menu, click Show Differential Pin Pair Connections to highlight the differential pin pairing. The differential pin pairs are connected with red lines.
• For differential pins, you only need to assign the signal to a positive pin. The Quartus Prime software automatically assigns the negative pin if the positive pin is assigned with a differential I/O standard.
In MAX 10 devices, the routing of each differential pin pair is matched. Consequently, the skew between the positive and the negative pins is minimal. The internal routes of both pins in a differential pair are matched even if the pins are non-adjacent.
The Altera Soft LVDS IP core for MAX 10 devices supports a maximum of 18 channels per IP instantia‐ tion. Each channel can support deserialization factor (parallel data width) from one to ten bits. When you are grouping channels for an application, you must consider the channel to channel skew during Fitter placement. To minimize skew, place all LVDS channels in the group side by side. For your PCB design,
Altera recommends that you perform package skew compensation to minimize skew and maximize performance.
Note: For MAX 10 devices, the Quartus Prime software does not provide a package skew compensation report.
Each PLL in the MAX 10 device can drive only the LVDS channels in I/O banks on the same edge as the
PLL.
Table 3-4: Examples of Usable PLL to Drive I/O Banks in MAX 10 Devices
I/O Bank Edge
Left
Bottom
Right
Top
Input refclk
Left
Bottom
Right
Top
GCLK
mux
Left
Bottom
Right
Top
Usable PLL
Top left or bottom left
Bottom left or bottom right
Top right or bottom right
Top left or top right
The Quartus Prime software automatically optimizes the SERDES logic placement to meet the timing requirements. Therefore, you do not have to perform placement constraints on the Altera Soft LVDS IP core logic.
To improve the performance of the Quartus Prime Fitter, you can create LogicLock
™ floorplan to confine the transmitter SERDES logic placement.
regions in the device
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Guidelines: Enable LVDS Pre-Emphasis for E144 Package
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• The TCCS parameter is guaranteed per datasheet specification to the entire bank of differential I/Os that are located in the same side. This guarantee applies if the transmitter SERDES logic is placed within the LAB adjacent to the output pins.
• Constrain the transmitter SERDES logic to the LAB adjacent to the data output pins and clock output pins to improve the TCCS performance.
Related Information
Quartus Prime Incremental Compilation for Hierarchical and Team-Based Design chapter, Volume 1:
Design and Synthesis, Quartus Prime Handbook
Provides step by step instructions about creating a design floorplan with LogicLock location assignments.
For MAX 10 devices in the E144 package, Altera recommends that you enable LVDS pre-emphasis to achieve optimum signal integrity (SI) performance. If you do not enable pre-emphasis, undesirable SI condition may be induced in the device resulting in LVDS eye height sensitivity.
You can obtain useful information about the LVDS interface performance with board-level verification using the FPGA prototype.
Although the focus of the board-level verification is to verify the FPGA functionality in your end system, you can take additional steps to examine the margins. Using oscilloscopes, you can examine the margins to verify the predicted size of the data-valid window, and the setup and hold margins at the I/O interface.
You can also use the Altera SignalTap
® the system against your design targets.
II Logic Analyzer to perform system level verification to correlate
Related Information
In-System Debugging Using External Logic Analyzers chapter, Volume 3: Verification, Quartus Prime
Handbook
Before you debug on hardware, Altera recommends that you perform an RTL simulation. Using the RTL simulation, you can check the code functionality before testing in real hardware.
For example, you can use the RTL simulation to verify that when you send a training pattern from a remote transmitter, the bitslipping mechanism in your LVDS receiver works.
You need to consider the I/O placement rules related to LVDS. The Quartus Prime software generates critical warning or error messages if the I/O placements rules are violated.
For more information, refer to the related information.
Related Information
MAX 10 General Purpose I/O User Guide
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You can implement receiver-only applications using the MAX 10 LVDS solution. You can use the Altera
Soft LVDS IP core to instantiate soft SERDES circuitry. The soft SERDES circuitry works with the clocks and differential I/O pins to create a high-speed differential receiver circuit.
•
•
Related Information
MAX 10 High-Speed LVDS I/O Overview
on page 1-1
MAX 10 LVDS SERDES I/O Standards Support
on page 2-7
Lists the supported LVDS I/O standards and the support in different MAX 10 device variants.
4
The LVDS receiver circuitry uses the I/O elements and registers in the MAX 10 devices. The deserializer is implemented in the core logic as a soft SERDES blocks.
In the receiver mode, the following blocks are available in the differential receiver datapath:
• Deserializer
• Data realignment block (bit slip)
Related Information
MAX 10 High-Speed LVDS Circuitry
The soft deserializer converts a 1-bit serial data stream into a parallel data stream based on the deserialization factor.
Figure 4-1: LVDS x8 Deserializer Waveform
RX_IN 7 6 5 4 3 2 1 0 a b c d e f g h A B C D E F G H X X X X X X X X
FCLK
RX_OUT[9:0] XXXXXXXX 76543210 abcdefgh ABCDEFGH
©
2016 Intel Corporation. All rights reserved. Intel, the Intel logo, Altera, Arria, Cyclone, Enpirion, MAX, Megacore, NIOS, Quartus and Stratix words and logos are trademarks of Intel Corporation in the US and/or other countries. Other marks and brands may be claimed as the property of others. Intel warrants performance of its FPGA and semiconductor products to current specifications in accordance with Intel's standard warranty, but reserves the right to make changes to any products and services at any time without notice. Intel assumes no responsibility or liability arising out of the application or use of any information, product, or service described herein except as expressly agreed to in writing by Intel. Intel customers are advised to obtain the latest version of device specifications before relying on any published information and before placing orders for products or services.
www.altera.com
101 Innovation Drive, San Jose, CA 95134
ISO
9001:2008
Registered
4-2
Data Realignment Block (Bit Slip)
rx_in fclk loaden
Signal
rx_out[9:0]
Description
LVDS data stream, input to the Altera Soft LVDS channel.
Clock used for receiver.
Enable signal for deserialization generated by the Altera Soft LVDS IP core.
Deserialized data.
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Skew in the transmitted data and skew added by the transmision link cause channel-to-channel skew on the received serial data streams. To compensate for channel-to-channel skew and establish the correct received word boundary at each channel, each receiver channel contains a data realignment circuit. The data realignment circuit realigns the data by inserting bit latencies into the serial stream.
To align the data manually, use the data realignment circuit to insert a latency of one
RxFCLK
cycle . The data realignment circuit slips the data one bit for every
RX_DATA_ALIGN
pulse. You must wait at least two core clock cycles before checking to see if the data is aligned. This wait is necessary because it takes at least two core clock cycles to purge the corrupted data.
An optional
RX_CHANNEL_DATA_ALIGN
port controls the bit insertion of each receiver independently of the internal logic. The data slips one bit on the rising edge of
RX_CHANNEL_DATA_ALIGN
.
The
RX_CHANNEL_DATA_ALIGN
signal has these requirements:
• The minimum pulse width is one period of the parallel clock in the logic array.
• The minimum low time between pulses is one period of the parallel clock.
• The signal is edge-triggered.
• The valid data is available two parallel clock cycles after the rising edge of
RX_CHANNEL_DATA_ALIGN
.
Figure 4-2: Data Realignment Timing
This figure shows receiver output (
RX_OUT
) after one bit slip pulse with the deserialization factor set to 4.
rx_inclock rx_in rx_outclock rx_channel_data_align rx_out
3 2 1 0 3 2 1 0 3 2 1 0
3210 321x xx21 0321
All LVDS receiver channels require termination to achieve better signal quality and ensure impedance matching with the transmission line and driver.
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LVDS, Mini-LVDS, and RSDS Receiver External Termination
The LVDS, mini-LVDS, or RSDS receiver requires a single resistor external termination scheme.
Figure 4-3: External Termination for LVDS I/O Standard
4-3
TX
50 Ω
50 Ω
100 Ω
Differential Outputs
The SLVS receiver requires a single-resistor external termination scheme.
Figure 4-4: External Termination for SLVS Receiver
RX
Differential Inputs
2.5 V
TX
Z
0
= 50 Ω
Z
0
= 50 Ω
100 Ω
SLVS peer
The Sub-LVDS receiver requires a single-resistor external termination scheme.
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RX
SLVS on FPGA
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TMDS Receiver External Termination
Figure 4-5: External Termination for Sub-LVDS Receiver
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2.5 V
TX
Z
0
= 50 Ω
Z
0
= 50 Ω
100 Ω RX
Sub-LVDS peer Sub-LVDS on FPGA
Figure 4-6: External Termination for TMDS Receiver
This diagram shows the external level shifter that is required for the TMDS input standards support in
MAX 10 devices.
1.8 V
2.5 V
50 Ω 50 Ω
0.1 µF
Z
0
= 50 Ω
TX RX
0.1 µF
Z
0
= 50 Ω
TMDS on FPGA TMDS peer
The HiSpi receiver requires a single-resistor external termination scheme.
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Figure 4-7: External Termination for HiSpi Receiver
LVPECL External Termination
4-5
2.5 V
TX
Z
0
= 50 Ω
Z
0
= 50 Ω
100 Ω RX
HiSpi peer HiSpi on FPGA
The MAX 10 devices support the LVPECL I/O standard on input clock pins only.
• LVDS input buffers support LVPECL input operation.
• LVPECL output operation is not supported.
Use AC coupling if the LVPECL common-mode voltage of the output buffer does not match the LVPECL input common-mode voltage.
Note: Altera recommends that you use IBIS models to verify your LVPECL AC/DC-coupled termination.
Figure 4-8: LVPECL AC-Coupled Termination
0.1 µF
Z
0
= 50 Ω
V
ICM
50 Ω
Z
0
= 50 Ω
50 Ω
0.1 µF
LVPECL Output Buffer LVPECL Input Buffer
Support for DC-coupled LVPECL is available if the LVPECL output common mode voltage is within the
MAX 10 LVPECL input buffer specification.
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LVDS Receiver FPGA Design Implementation
Figure 4-9: LVPECL DC-Coupled Termination
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Z
0
= 50 Ω
Z
0
= 50 Ω
100 Ω
LVPECL Output Buffer LVPECL Input Buffer
For information about the V
ICM
specification, refer to the device datasheet.
Related Information
MAX 10 Device Datasheet
MAX 10 devices use a soft SERDES architecture to support high-speed I/O interfaces. The Quartus Prime software creates the SERDES circuits in the core fabric by using the Altera Soft LVDS IP core. To improve the timing performance and support the SERDES, MAX 10 devices use the I/O registers and LE registers in the core fabric.
In the Quartus Prime software, you can design your high-speed receiver interfaces using the Altera Soft
LVDS IP core. This IP core uses the resources in the MAX 10 devices optimally to create the high-speed
I/O interfaces.
• You can use the Altera Soft LVDS parameter editor to customize your deserializer based on your design requirements.
• The Altera Soft LVDS IP core implements the high-speed deserializer in the core fabric.
•
•
•
Related Information
Altera Soft LVDS Parameter Settings
Introduction to Altera IP Cores
on page 7-1
Provides general information about all Altera FPGA IP cores, including parameterizing, generating, upgrading, and simulating IP cores.
Creating Version-Independent IP and Qsys Simulation Scripts
Create simulation scripts that do not require manual updates for software or IP version upgrades.
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•
PLL Source Selection for Altera Soft LVDS IP Core
Project Management Best Practices
Guidelines for efficient management and portability of your project and IP files.
You can create the LVDS interface components by instantiating the Altera Soft LVDS IP core with an internal or external PLL.
4-7
Instantiate Altera Soft LVDS IP Core with Internal PLL
You can set the Altera Soft LVDS IP core to build the SERDES components and instantiate the PLL internally.
• To use this method, turn off the Use external PLL option in the PLL Settings tab.
• The Altera Soft LVDS IP core integrates the PLL into the LVDS block.
• The drawback of this method is that you can use the PLL only for the particular LVDS instance.
Instantiate Altera Soft LVDS IP Core with External PLL
You can set the Altera Soft LVDS IP core to build only the SERDES components but use an external PLL source.
• To use this method, turn on the Use external PLL option in the PLL Settings tab.
• Follow the required clock setting to the input ports as listed in the notification panel.
• You can create your own clocking source using the ALTPLL IP core.
• Use this method to optimize PLL usage with other functions in the core.
•
•
Related Information
MAX 10 Clocking and PLL User Guide
Provides more information about the PLL and the PLL output counters.
MAX 10 Clocking and PLL User Guide
Provides more information about the PLL and the PLL output counters.
You can instantiate the Altera Soft LVDS IP core with the Use External PLL option. Using external PLL, you can control the PLL settings. For example, you can dynamically reconfigure the PLL to support different data rates and dynamic phase shifts. To use this option, you must instantiate the ALTPLL IP core to generate the various clock signals.
If you turn on the Use External PLL option for the Altera Soft LVDS receiver, you require the following signals from the ALTPLL IP core:
• Serial clock input to the rx_inclock
port of the Altera Soft LVDS receiver.
• Parallel clock used to clock the receiver FPGA fabric logic.
• The locked
signal for Altera Soft LVDS PLL reset port.
Related Information
MAX 10 Clocking and PLL User Guide
Provides more information about the PLL and the PLL output counters.
ALTPLL Signal Interface with Altera Soft LVDS Receiver
You can choose any of the PLL output clock ports to generate the LVDS interface clocks.
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Determining External PLL Clock Parameters for Altera Soft LVDS Receiver
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If you use the ALTPLL IP core as the external PLL source of the Altera Soft LVDS receiver, use the sourcesynchronous compensation mode.
Table 4-1: Example: Signal Interface Between ALTPLL and Altera Soft LVDS Receiver with Even
Deserialization Factor
From the ALTPLL IP Core To the Altera Soft LVDS Receiver
Fast clock output ( c0
)
The serial clock output ( c0
) can only drive rx_inclock
on the Altera Soft
LVDS receiver.
rx_inclock
Slow clock output ( c1
) rx_syncclock
Table 4-2: Example: Signal Interface Between ALTPLL and Altera Soft LVDS Receiver with Odd
Deserialization Factor
From the ALTPLL IP Core To the Altera Soft LVDS Receiver
Fast clock output ( c0
)
The serial clock output ( c0
) can only drive rx_inclock
on the Altera Soft
LVDS receiver.
rx_inclock
Slow clock output ( c1
)
Read clock ( c2
) output from the PLL rx_syncclock rx_readclock
(clock input port for reading operation from RAM buffer and read counter)
Determining External PLL Clock Parameters for Altera Soft LVDS Receiver
To determine the ALTPLL IP core clock parameter for the Altera Soft LVDS IP core receiver, follow these steps in your design:
1. Instantiate the Altera Soft LVDS IP core receiver using internal PLL.
2. Compile the design up to TimeQuest timing analysis.
3. In the Table of Contents section of the Compilation Report window, navigate to TimeQuest Timing
Analyzer > Clocks.
4. Note the clock parameters used by the internal PLL for the Altera Soft LVDS IP core receiver.
In the list of clocks, clk[0]
is the fast clock, clk[1]
is the slow clock, and clk[2]
is the read clock.
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Initializing the Altera Soft LVDS IP Core
Figure 4-10: Clock Parameters Example for Altera Soft LVDS Receiver
4-9
Configure the ALTPLL output clocks with the parameters you noted in this procedure and connect the clock outputs to the correct Altera Soft LVDS clock input ports.
The PLL locks to the reference clock before the Altera Soft LVDS IP core implements the SERDES blocks for data transfer.
During device initialization the PLL starts to lock to the reference clock and becomes operational when it achieves lock during user mode. If the clock reference is not stable, it corrupts the phase shifts of the PLL output clock. This phase shifts corruption can cause failure and corrupt data transfer between the highspeed LVDS domain and the low-speed parallel domain.
To avoid data corruption, follow these steps when initializing the Altera Soft LVDS IP core:
1. Assert the pll_areset
signal for at least 10 ns.
2. After at least 10 ns, deassert the pll_areset
signal.
3. Wait until the PLL lock becomes stable.
After the PLL lock port asserts and is stable, the SERDES blocks are ready for operation.
The LVDS I/O standard enables high-speed transmission of data that results in better overall system performance. To take advantage of fast system performance, you must analyze the timing for high-speed signals. Timing analysis for the differential block is different than traditional synchronous timing analysis techniques.
The basis of the source synchronous timing analysis is the skew between the data and the clock signals instead of the clock-to-output setup times. High-speed differential data transmission requires the use of timing parameters provided by IC vendors and is strongly influenced by board skew, cable skew, and clock jitter.
Use RSKM, TCCS, and sampling window (SW) specifications for high-speed source-synchronous differential signals in the receiver data path.
Related Information
Guidelines: Control Channel-to-Channel Skew
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RSKM Equation
RSKM Equation
The RSKM equation expresses the relationship between RSKM, TCCS, and SW.
Figure 4-11: RSKM Equation
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Conventions used for the equation:
• RSKM—the timing margin between the clock input of the receiver and the data input sampling window, and the jitter induced from core noise and I/O switching noise.
• Time unit interval (TUI)—time period of the serial data.
• SW—the period of time that the input data must be stable to ensure that the LVDS receiver samples the data successfully. The SW is a device property and varies according to device speed grade.
• TCCS—the timing difference between the fastest and the slowest output edges across channels driven by the same PLL. The TCCS measurement includes the t
CO
variation, clock, and clock skew.
Note: If there is additional board channel-to-channel skew, consider the total receiver channel-to-channel skew (RCCS) instead of TCCS. Total RCCS = TCCS + board channel-to-channel skew.
You must calculate the RSKM value, based on the data rate and device, to determine if the LVDS receiver can sample the data:
• A positive RSKM value, after deducting transmitter jitter, indicates that the LVDS receiver can sample the data properly.
• A negative RSKM value, after deducting transmitter jitter, indicates that the LVDS receiver cannot sample the data properly.
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RSKM Report for LVDS Receiver
Figure 4-12: Differential High-Speed Timing Diagram and Timing Budget
This figure shows the relationship between the RSKM, TCCS, and the SW of the receiver.
Timing Diagram
External
Input Clock
Time Unit Interval (TUI)
Internal
Clock
Receiver
Input Data
TCCS
RSKM SW
TCCS
RSKM t
SW
(min)
Bit n
Internal
Clock
Falling Edge
TUI t
SW
(max)
Bit n
Timing Budget
External
Clock
Internal
Clock
Synchronization
Transmitter
Output Data
Receiver
Input Data
TCCS
RSKM
Clock Placement
RSKM
TCCS
2
SW
4-11
Related Information
Guidelines: Control Channel-to-Channel Skew
RSKM Report for LVDS Receiver
For LVDS receivers, the Quartus Prime software provides an RSKM report showing the SW, TUI, and
RSKM values.
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Assigning Input Delay to LVDS Receiver Using TimeQuest Timing Analyzer
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• To generate the RSKM report, run the report_RSKM
command in the TimeQuest Timing Analyzer.
The RSKM report is available in the TimeQuest Timing Analyzer section of the Quartus Prime compilation report.
• To obtain a more realistic RSKM value, assign the input delay to the LVDS receiver through the constraints menu of the TimeQuest Timing Analyzer. The input delay is determined according to the data arrival time at the LVDS receiver port, with respect to the reference clock.
• If you set the input delay in the settings parameters for the Set Input Delay option, set the clock name to the clock that references the source-synchronous clock that feeds the LVDS receiver.
• If you do not set any input delay in the TimeQuest Timing Analyzer, the receiver channel-to-channel skew defaults to zero.
• You can also directly set the input delay in a Synopsys Design Constraint file (.sdc) by using the set_input_delay
command.
Related Information
Guidelines: Control Channel-to-Channel Skew
Assigning Input Delay to LVDS Receiver Using TimeQuest Timing Analyzer
To obtain the RSKM value, assign an appropriate input delay to the LVDS receiver from the TimeQuest
Timing Analyzer constraints menu.
1. On the menu in the TimeQuest Timing Analyzer, select Constraints > Set Input Delay.
2. In the Set Input Delay window, select the desired clock using the pull-down menu. The clock name must reference the source synchronous clock that feeds the LVDS receiver.
3. Click the Browse button (next to the Targets field).
4. In the Name Finder window, click List to view a list of all available ports. Select the LVDS receiver serial input ports according to the input delay you set, and click OK.
5. In the Set Input Delay window, set the appropriate values in the Input delay options and Delay value fields.
6. Click Run to incorporate these values in the TimeQuest Timing Analyzer.
7. Repeat from
to assign the appropriate delay for all the LVDS receiver input ports. If you have
already assigned Input Delay and you need to add more delay to that input port, turn on the Add
Delay option.
Related Information
Guidelines: Control Channel-to-Channel Skew
Example: RSKM Calculation
This example shows the RSKM calculation for FPGA devices at 1 Gbps data rate with a 200 ps board channel-to-channel skew.
• TCCS = 100 ps
• SW = 300 ps
• TUI = 1000 ps
• Total RCCS = TCCS + Board channel-to-channel skew = 100 ps + 200 ps = 300 ps
• RSKM = (TUI – SW – RCCS) / 2 = (1000 ps – 300 ps – 300 ps) / 2 = 200 ps
If the RSKM is greater than 0 ps after deducting transmitter jitter, the receiver will work correctly.
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Guidelines: Floating LVDS Input Pins
4-13
Related Information
Guidelines: Control Channel-to-Channel Skew
You can implement floating LVDS input pins in MAX 10 devices.
For floating LVDS input pins, apply a 100 Ω differential resistance across the P and N legs of the LVDS receiver. You can use external termination.
If you use floating LVDS input pins, Altera recommends that you use external biasing schemes to reduce noise injection and current consumption.
To maintain an acceptable noise level on the V
CCIO ended I/O pins in relation to differential pads.
supply, observe the placement restrictions for single-
Altera recommends that you create a Quartus Prime design, specify your device I/O assignments, and compile your design to validate your pin placement. The Quartus Prime software verifies your pin connections against the I/O assignment and placement rules to ensure that the device will operate properly.
You can use the Quartus Prime Pin Planner Package view to ease differential I/O assignment planning:
• On the View menu, click Show Differential Pin Pair Connections to highlight the differential pin pairing. The differential pin pairs are connected with red lines.
• For differential pins, you only need to assign the signal to a positive pin. The Quartus Prime software automatically assigns the negative pin if the positive pin is assigned with a differential I/O standard.
In MAX 10 devices, the routing of each differential pin pair is matched. Consequently, the skew between the positive and the negative pins is minimal. The internal routes of both pins in a differential pair are matched even if the pins are non-adjacent.
The Altera Soft LVDS IP core for MAX 10 devices supports a maximum of 18 channels per IP instantia‐ tion. Each channel can support deserialization factor (parallel data width) from one to ten bits. When you are grouping channels for an application, you must consider the channel to channel skew during Fitter placement. To minimize skew, place all LVDS channels in the group side by side. For your PCB design,
Altera recommends that you perform package skew compensation to minimize skew and maximize performance.
Note: For MAX 10 devices, the Quartus Prime software does not provide a package skew compensation report.
Each PLL in the MAX 10 device can drive only the LVDS channels in I/O banks on the same edge as the
PLL.
Table 4-3: Examples of Usable PLL to Drive I/O Banks in MAX 10 Devices
I/O Bank Edge
Left
Bottom
Right
Input refclk
Left
Bottom
Right
GCLK
mux
Left
Bottom
Right
Usable PLL
Top left or bottom left
Bottom left or bottom right
Top right or bottom right
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Guidelines: LVDS Receiver Logic Placement
I/O Bank Edge
Top
Input refclk
Top
GCLK
mux
Top
Usable PLL
Top left or top right
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The Quartus Prime software automatically optimizes the SERDES logic placement to meet the timing requirements. Therefore, you do not have to perform placement constraints on the Altera Soft LVDS IP core logic.
To improve the performance of the Quartus Prime Fitter, you can create LogicLock regions in the device floorplan to confine the transmitter SERDES logic placement.
• The TCCS parameter is guaranteed per datasheet specification to the entire bank of differential I/Os that are located in the same side. This guarantee applies if the transmitter SERDES logic is placed within the LAB adjacent to the output pins.
• Constrain the transmitter SERDES logic to the LAB adjacent to the data output pins and clock output pins to improve the TCCS performance.
For receiver designs that uses the core logic to implement the SERDES circuits, you must set proper timing constraints.
For LVDS receiver data paths where the PLL operation is in source-synchronous compensation mode, the
Quartus Prime compiler automatically ensures that the associated delay chain settings are set correctly.
However, if the input clock and data at the receiver are not edge- or center-aligned, it may be necessary for you to set the timing constraints in the Quartus Prime TimeQuest Timing Analyzer. The timing constraints specify the timing requirements necessary to ensure reliable data capture.
You can obtain useful information about the LVDS interface performance with board-level verification using the FPGA prototype.
Although the focus of the board-level verification is to verify the FPGA functionality in your end system, you can take additional steps to examine the margins. Using oscilloscopes, you can examine the margins to verify the predicted size of the data-valid window, and the setup and hold margins at the I/O interface.
You can also use the Altera SignalTap II Logic Analyzer to perform system level verification to correlate the system against your design targets.
Before you debug on hardware, Altera recommends that you perform an RTL simulation. Using the RTL simulation, you can check the code functionality before testing in real hardware.
For example, you can use the RTL simulation to verify that when you send a training pattern from a remote transmitter, the bitslipping mechanism in your LVDS receiver works.
You need to consider the I/O placement rules related to LVDS. The Quartus Prime software generates critical warning or error messages if the I/O placements rules are violated.
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For more information, refer to the related information.
Geometry-Based and Physics-Based I/O Rules
Related Information
MAX 10 General Purpose I/O User Guide
4-15
MAX 10 LVDS Receiver Design
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You can implement mixed transmitter and receiver applications using the MAX 10 LVDS solution. You can use the Altera Soft LVDS IP core to instantiate soft SERDES circuitry. The soft SERDES circuitry works with the clocks and differential I/O pins to create high-speed differential transmitter and receiver circuits.
In a mixed transmitter and receiver implementation, the transmitter and receiver can share some FPGA resources.
•
•
Related Information
MAX 10 High-Speed LVDS I/O Overview
on page 1-1
MAX 10 LVDS SERDES I/O Standards Support
on page 2-7
Lists the supported LVDS I/O standards and the support in different MAX 10 device variants.
5
You can instantiate the components for the Altera Soft LVDS interfaces by using internal or external PLLs.
Figure 5-1: Typical Altera Soft LVDS Interfaces with Internal PLL
LVDS Source
Device
CLOCK and
DATA
FPGA Device
SERDES logic and DDIO
LVDS Receiver IP Core
PLL
LVDS Transmitter IP Core
PLL
SERDES logic and DDIO
CLOCK and
DATA
LVDS Destination
Device
©
2016 Intel Corporation. All rights reserved. Intel, the Intel logo, Altera, Arria, Cyclone, Enpirion, MAX, Megacore, NIOS, Quartus and Stratix words and logos are trademarks of Intel Corporation in the US and/or other countries. Other marks and brands may be claimed as the property of others. Intel warrants performance of its FPGA and semiconductor products to current specifications in accordance with Intel's standard warranty, but reserves the right to make changes to any products and services at any time without notice. Intel assumes no responsibility or liability arising out of the application or use of any information, product, or service described herein except as expressly agreed to in writing by Intel. Intel customers are advised to obtain the latest version of device specifications before relying on any published information and before placing orders for products or services.
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LVDS Transmitter and Receiver FPGA Design Implementation
Figure 5-2: Typical Altera Soft LVDS Interfaces with External PLL
FPGA Device
LVDS Source
Device
DATA
CLOCK
PLL
IP Core
LVDS Receiver IP Core
SERDES logic and DDIO
PLL
IP Core
LVDS Transmitter IP Core
SERDES logic and DDIO
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DATA
CLOCK
LVDS Destination
Device
•
•
Related Information
MAX 10 LVDS Transmitter Design
on page 3-1
Provides more information about specific features and support of the LVDS transmitters.
on page 4-1
Provides more information about specific features and support of the LVDS receivers.
MAX 10 devices use a soft SERDES architecture to support high-speed I/O interfaces. The Quartus Prime software creates the SERDES circuits in the core fabric by using the Altera Soft LVDS IP core. To improve the timing performance and support the SERDES, MAX 10 devices use the I/O registers and LE registers in the core fabric.
In applications where an LVDS transmitter and receiver are required, you typically need two PLLs—one for each interface. Using the Altera Soft LVDS IP core, you can reduce PLL usage by sharing one PLL between the transmitter and receiver.
• Turn on the Use common PLL(s) for receivers and transmitters option to allow the Quartus Prime compiler to share the same PLL.
• To share a PLL, several PLLs must have the same PLL settings, such as PLL feedback mode, clock frequency, and phase settings. The LVDS transmitters and receivers must use the same input clock frequency and reset input.
• If you are sharing a PLL, you can use more counters to enable different deserialization factor and data rates for the transmitters and receivers. However, because you are using more PLL counters, the PLL input clock frequency and the PLL counter resolution cause limitations in clocking the transmitters and receivers.
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Initializing the Altera Soft LVDS IP Core
5-3
Note: The number of PLLs available differs among MAX 10 packages. Altera recommends that you select a MAX 10 device package that provides sufficient number of PLL clockouts for your design.
The PLL locks to the reference clock before the Altera Soft LVDS IP core implements the SERDES blocks for data transfer.
During device initialization the PLL starts to lock to the reference clock and becomes operational when it achieves lock during user mode. If the clock reference is not stable, it corrupts the phase shifts of the PLL output clock. This phase shifts corruption can cause failure and corrupt data transfer between the highspeed LVDS domain and the low-speed parallel domain.
To avoid data corruption, follow these steps when initializing the Altera Soft LVDS IP core:
1. Assert the pll_areset
signal for at least 10 ns.
2. After at least 10 ns, deassert the pll_areset
signal.
3. Wait until the PLL lock becomes stable.
After the PLL lock port asserts and is stable, the SERDES blocks are ready for operation.
You can obtain useful information about the LVDS interface performance with board-level verification using the FPGA prototype.
Although the focus of the board-level verification is to verify the FPGA functionality in your end system, you can take additional steps to examine the margins. Using oscilloscopes, you can examine the margins to verify the predicted size of the data-valid window, and the setup and hold margins at the I/O interface.
You can also use the Altera SignalTap II Logic Analyzer to perform system level verification to correlate the system against your design targets.
Before you debug on hardware, Altera recommends that you perform an RTL simulation. Using the RTL simulation, you can check the code functionality before testing in real hardware.
For example, you can use the RTL simulation to verify that when you send a training pattern from a remote transmitter, the bitslipping mechanism in your LVDS receiver works.
You need to consider the I/O placement rules related to LVDS. The Quartus Prime software generates critical warning or error messages if the I/O placements rules are violated.
For more information, refer to the related information.
Related Information
MAX 10 General Purpose I/O User Guide
MAX 10 LVDS Transmitter and Receiver Design
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To achieve optimal performance from the MAX 10 device, you must consider critical issues such as impedance of traces and connectors, differential routing, and termination techniques.
6
To improve signal quality, follow these board design guidelines:
• Base your board designs on controlled differential impedance. Calculate and compare all parameters such as trace width, trace thickness, and the distance between two differential traces.
• Maintain equal distance between traces in differential I/O standard pairs as much as possible. Routing the pair of traces close to each other maximizes the common-mode rejection ratio (CMRR).
• Keep the traces as short as possible to limit signal integrity issues. Longer traces have more inductance and capacitance.
• Place termination resistors as close to receiver input pins as possible.
• Use surface mount components.
• Avoid 90° corners on board traces.
• Use high-performance connectors.
• Design backplane and card traces so that trace impedance matches the impedance of the connector and termination.
• Keep an equal number of vias for both signal traces.
• Create equal trace lengths to avoid skew between signals. Unequal trace lengths result in misplaced crossing points and decrease system margins as the transmitter-channel-to-channel skew (TCCS) value increases.
• Limit vias because they cause discontinuities.
• Keep toggling single-ended I/O signals away from differential signals to avoid possible noise coupling.
• Do not route single-ended I/O clock signals to layers adjacent to differential signals.
• Analyze system-level signals.
For the MAX 10 devices, perform PCB trace compensation to adjust the trace length of each LVDS channel. Adjusting the trace length improves the channel-to-channel skew when interfacing with receivers.
©
2016 Intel Corporation. All rights reserved. Intel, the Intel logo, Altera, Arria, Cyclone, Enpirion, MAX, Megacore, NIOS, Quartus and Stratix words and logos are trademarks of Intel Corporation in the US and/or other countries. Other marks and brands may be claimed as the property of others. Intel warrants performance of its FPGA and semiconductor products to current specifications in accordance with Intel's standard warranty, but reserves the right to make changes to any products and services at any time without notice. Intel assumes no responsibility or liability arising out of the application or use of any information, product, or service described herein except as expressly agreed to in writing by Intel. Intel customers are advised to obtain the latest version of device specifications before relying on any published information and before placing orders for products or services.
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Guidelines: Determine Board Design Constraints
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At the package level, you must control the LVDS I/O skew for each I/O bank and each side of the device. If you plan to vertically migrate from one device to another using the same board design, you must control the package migration skew for each migratable LVDS I/O pin.
For information about controlling the LVDS I/O and package skew, refer to the related information.
•
•
•
•
•
Related Information
on page 4-9
Explains the relationship between the RSKM, TCCS, and SW.
Provides guidelines to generate RSKM report with realistic RSKM value.
Assigning Input Delay to LVDS Receiver Using TimeQuest Timing Analyzer
on page 4-12
Provides the procedure to assign input delay in TimeQuest Timing Analyzer to obtain RSKM value.
After you have closed timing for your FPGA design, examine your board design to determine the different factors that can impact signal integrity. These factors affect overall timing at the receiving device in the
LVDS interface.
The time margin for the LVDS receiver (indicated by the RSKM value) is the timing budget allocation for board level effects such as:
• Skew—these factors cause board-level skew:
• Board trace lengths
• Connectors usage
• Parasitic circuits variations
• Jitter—jitter effects are derived from factors such as crosstalk.
• Noise—on board resources with imperfect power supplies and reference planes may also cause noise.
To ensure successful operation of the Altera Soft LVDS IP core receiver, do not exceed the timing budget.
Related Information
Board Design Guidelines Solution Center
Provides resources related to board design for Altera devices.
After you determined the system requirements and finalized the board design constraints, use an electronic design automation (EDA) simulation tool to perform board-level simulations. Use the IBIS or
HSPICE models of the FPGA and the target LVDS device for the simulation.
The board-level simulation ensures optimum board setup where you can determine if the data window conforms to the input specification (electrical and timing) of the LVDS receiver.
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Guidelines: Perform Board Level Simulations
6-3
You can use the programmable pre-emphasis feature on the true LVDS output buffers, for example, to compensate for the frequency-dependent attenuation of the transmission line. With this feature, you can maximize the data eye opening at the far end receiver especially on long transmission lines.
•
•
•
Related Information
Altera IBIS Models
Provides IBIS models of Altera devices for download.
Altera HSPICE Models
Provides SPICE models of Altera devices for download.
IBIS Model Generation
Provides video that demonstrates how to generate IBIS file using the Quartus Prime software.
MAX 10 High-Speed LVDS Board Design Considerations
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You can set various parameter settings for the Altera Soft LVDS IP core to customize its behaviors, ports, and signals.
The Quartus Prime software generates your customized Altera Soft LVDS IP core according to the parameter options that you set in the parameter editor.
•
•
Related Information
MAX 10 High-Speed LVDS I/O Overview
on page 1-1
MAX 10 LVDS SERDES I/O Standards Support
on page 2-7
Lists the supported LVDS I/O standards and the support in different MAX 10 device variants.
7
There are four groups of options: General , PLL Settings , Receiver Settings , and Transmitter Settings
Table 7-1: Altera Soft LVDS Parameters - General
Parameter Condition Allowed
Values
Power Supply
Mode
—
• Dual
Supply
• Single
Supply
Functional mode —
• RX
• TX
Description
Specifies whether the target device is a single or dual supply device.
Number of channels
— 1–18
Specifies the functional mode for the Altera
Soft LVDS IP core:
• RX—specifies the IP is an LVDS receiver.
• TX—specifies the IP is an LVDS transmitter.
Specifies the number of LVDS channels.
©
2016 Intel Corporation. All rights reserved. Intel, the Intel logo, Altera, Arria, Cyclone, Enpirion, MAX, Megacore, NIOS, Quartus and Stratix words and logos are trademarks of Intel Corporation in the US and/or other countries. Other marks and brands may be claimed as the property of others. Intel warrants performance of its FPGA and semiconductor products to current specifications in accordance with Intel's standard warranty, but reserves the right to make changes to any products and services at any time without notice. Intel assumes no responsibility or liability arising out of the application or use of any information, product, or service described herein except as expressly agreed to in writing by Intel. Intel customers are advised to obtain the latest version of device specifications before relying on any published information and before placing orders for products or services.
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Altera Soft LVDS Parameter Settings
Parameter Condition
SERDES factor —
Allowed
Values
1, 2, 4, 5, 6, 7,
8, 9, 10
Description
Specifies the number of bits per channel.
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Table 7-2: Altera Soft LVDS Parameters - PLL Settings
Parameter Condition Allowed
Values
Use external PLL
Data rate
Not applicable for x1 and x2 modes.
—
• On
• Off
Refer to the device datasheet.
Inclock frequency
Enable rx_locked port
Enable tx_locked port
Enable pll_areset port
— Depends on
Data rate.
• General,
Functional mode =
RX
• Use external PLL =
Off
• On
• Off
• General,
Functional mode =
TX
• Use external PLL =
Off
Always on
• On
• Off
• On
• Off
Enable tx_data_ reset port
• General,
Functional mode =
TX
• Use external PLL =
On
• On
• Off
Description
Specifies whether the Altera Soft LVDS IP core generates a PLL or connects to a userspecified PLL.
Specifies the data rate going out of the PLL.
The multiplication value for the PLL is
OUTPUT_DATA_RATE divided by
INCLOCK_ PERIOD.
Specifies the input clock frequency to the
PLL in MHz.
If turned on, enables the rx_locked
port.
If turned on, enables the tx_locked
port.
If turned on, enables the pll_areset
port in internal PLL mode.
In external PLL mode, the pll_areset
port is always on.
If turned on, enables the tx_data_reset port.
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Parameter Condition Allowed
Values
Enable rx_data_ reset port
• General,
Functional mode =
RX
• Use external PLL =
On
• On
• Off
Use common
PLL(s) for receivers and transmitters
Use external PLL = Off • On
• Off
Altera Soft LVDS Parameter Settings
Description
If turned on, enables the port.
rx_data_reset
7-3
Enable self-reset on loss lock in PLL
Use external PLL = Off • On
• Off
Desired transmitter inclock phase shift
• General,
Functional mode =
TX
• Use external PLL =
Off
Depends on
Data rate.
Desired receiver inclock phase shift
• General,
Functional mode =
RX
• Use external PLL =
Off
Depends on
Data rate.
• On—specifies that the compiler uses the same PLL for the LVDS receiver and transmitter.
• Off—specifies that the compiler uses different PLLs for LVDS receivers and transmitters.
You can use common PLLs if you use the same input clock source, deserialization factor, pll_areset
source, and data rates.
If turned on, the PLL is reset when it loses lock.
Specifies the phase shift parameter used by the PLL for the transmitter.
Specifies the phase shift parameter used by the PLL for the receiver.
Table 7-3: Altera Soft LVDS Parameters - Receiver Settings
Parameter Condition Allowed
Values
Enable bitslip mode
General, Functional mode = RX
• On
• Off
Description
If turned on, enables the rx_data_align port.
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Altera Soft LVDS Parameter Settings
Parameter Condition
Enable independent bitslip controls for each channel
General, Functional mode = RX
Allowed
Values
• On
• Off
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Description
If turned on, enables the rx_channel_ data_align
port.
The rx_channel_data_align
is an edgesensitive bit slip control signal:
• Each rising edge on this signal causes the data realignment circuitry to shift the word boundary by one bit.
• The minimum pulse width requirement is one parallel clock cycle.
If turned on, enables the rx_data_align_ reset
port.
Enable rx_data_ align_reset port
Add extra register for rx_data_align port
Bitslip rollover value
Use RAM buffer
• General,
Functional mode =
RX
• Enable bitslip mode
= On
• Enable independent bitslip controls for each channel = Off
• On
• Off
• General,
Functional mode =
RX
• Enable bitslip mode
= On
• On
• Off
• General,
Functional mode =
RX
• Enable bitslip mode
= On
1–11
—
• On
• Off
If turned on, registers the port.
rx_data_align
If you turn this option off, you must preregister the rx_data_align[]
port in the logic that feeds the receiver.
Specifies the number of pulses before the circuitry restores the serial data latency to 0.
Use a multiplexer and synchroniza‐ tion register
—
• On
• Off
If turned on, the Altera Soft LVDS IP core implements the output synchronization buffer in the embedded memory blocks.
This implementation option uses more logic than Use a multiplexer and synchroniza‐
tion register option but results in the correct word alignment.
If turned on, the Altera Soft LVDS IP core implements a multiplexer instead of a buffer for output synchronization.
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Parameter
Use logic element based RAM
Register outputs
Condition
—
General, Functional mode = RX
Allowed
Values
• On
• Off
• On
• Off
Altera Soft LVDS Parameter Settings
Description
7-5
If turned on, the Altera Soft LVDS IP core implements the output synchronization buffer in the logic elements.
This implementation option uses more logic than Use a multiplexer and synchroniza‐
tion register option but results in the correct word alignment.
If turned on, registers the rx_out[]
port.
If you turn this option off, you must preregister the rx_out[]
port in the logic that feeds the receiver.
Table 7-4: Altera Soft LVDS Parameters - Transmitter Settings
Parameter Condition Allowed
Values
Enable 'tx_ outclock' output port
• General,
Functional mode =
TX
• PLL Settings, Use external PLL = Off
• On
• Off
Description
If turned on, enables the tx_outclock
port.
Every tx_outclock
signal goes through the shift register logic, except in the following parameter configurations:
• When the outclock_divide_by
signal =
1
• When the outclock_divide_by
signal is equal to the deserialization_ factor
signal (for odd factors only), and the outclock_duty_cycle
signal is 50
Tx_outclock division factor
• General,
Functional mode =
TX
• PLL Settings, Use external PLL = Off
• Enable 'tx_ outclock' output port = On
Depends on
SERDES
factor.
Specifies that the frequency of the outclock
signal is equal to the the transmitter output data rate divided by the selected division factor.
tx_
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Parameter Condition
Outclock duty cycle
• General,
Functional mode =
TX
• PLL Settings, Use external PLL = Off
• Enable 'tx_ outclock' output port = On
Desired transmitter outclock phase shift
• General,
Functional mode =
TX
• PLL Settings, Use external PLL = Off
• Enable 'tx_ outclock' output port = On
Register 'tx_in' input port
General, Functional mode = TX
Allowed
Values
Depends on
SERDES
factor and
Tx_outclock division
factor.
Depends on
Data rate.
• On
• Off
Clock resource
Enable 'tx_ coreclock' output port
Clock source for
'tx_coreclock' constraints.
Description
Specifies the external clock timing
Specifies the phase shift of the output clock relative to the input clock.
If turned on, registers the tx_in[]
port.
If you turn this option off, you must preregister the tx_in[]
port in the logic that feeds the transmitter.
Specifies which clock resource registers the tx_in
input port.
• General,
Functional mode =
TX
• Register 'tx_in' input port = On
General, Functional mode = TX
• tx_inclock
• tx_ coreclock
• On
• Off
If turned on, enables the tx_coreclock output port.
Specifies which clock resource drives the tx_coreclock
output port.
• General,
Functional mode =
TX
• Enable 'tx_ coreclock' output port = On
• Auto selection
• Global clock
• Regional clock
• Dual-
Regional clock
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•
Related Information
Altera Soft LVDS IP Core in Transmitter Mode
Altera Soft LVDS IP Core in Receiver Mode
Altera Soft LVDS Interface Signals
7-7
Depending on parameter settings you specify, different signals are available for the Altera Soft LVDS IP core.
Table 7-5: Transmitter Interface Signals
Signal Name Direction
pll_areset
Input tx_data_reset tx_in[] tx_inclock tx_coreclock
Input
Input
Input
Output
Width (Bit)
1
<n>
<m>
1
1
Description
Asynchronously resets all counters to the initial values.
Asynchronous reset for the shift registers, capture registers, and synchronization registers for all channels.
• This signal is used if Use external PLL parameter setting is turned on.
• This signal does not affect the data realignment block or the PLL.
This signal is parallel data that Altera Soft
LVDS IP core transmits serially.
Input data is synchronous to the tx_ coreclock
signal. The data bus width per channel is the same as the serialization factor (SF).
Reference clock input for the transmitter
PLL.
The parameter editor automatically selects the appropriate PLL multiplication factor based on the data and reference clock frequency.
Output clock that feeds non-peripheral logic.
FPGA fabric–transmitter interface clock— the parallel transmitter data generated in the FPGA fabric is clocked with this clock.
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Altera Soft LVDS Interface Signals
Signal Name
tx_locked
Direction
Output tx_out[] tx_outclock
Output
Output
Width (Bit)
1
<n>
1
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Description
Provides the LVDS PLL status:
• Remains high when the PLL is locked to the input reference clock.
• Remains low when the PLL fails to lock.
Serialized LVDS data output signal of
<n>
channels.
tx_out[(<n>-1)..0]
drives parallel data from tx_in[(<J> × <n>)-1 ..0]
where
<J>
is the serialization factor and
<n>
is the number of channels. tx_out[0]
drives data from tx_in[(<J>-1)..0]
. tx_out[1] drives data from the next
<J>
number of bits on tx_in
.
External reference clock.
The frequency of this clock is program‐ mable to be the same as the data rate.
Table 7-6: Receiver Interface Signals signal Name
rx_data_reset
Direction
Input rx_in[]
Input
Width (Bit)
<n>
<n>
Description
Asynchronous reset for all channels, excluding the PLL.
• This signal is available if Use external
PLL parameter setting is turned on.
• You must externally synchronize this signal with the fast clock.
LVDS serial data input signal of
<n>
channels.
rx_in[(<n>-1)..0]
is deserialized and driven on rx_out[(<J> × <n>)-1 ..0] where
<J>
is the deserialization factor and
<n>
is the number of channels. rx_in[0] drives data to rx_out[(<J>-1)..0]
. rx_ in[1]
drives data to the next
<J>
number of bits on rx_out
.
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signal Name
rx_inclock rx_coreclk rx_locked rx_out rx_outclock rx_data_align rx_data_align_reset rx_channel_data_align
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Direction
Input
Input
Output
Output
Output
Input
Input
Input
Width (Bit)
1
<n>
1
<m>
1
1
1
<n>
Altera Soft LVDS Interface Signals
7-9
Description
LVDS reference input clock.
The parameter editor automatically selects the appropriate PLL multiplication factor based on the data rate and reference clock frequency selection.
LVDS reference input clock.
• Replaces the non-peripheral clock from the PLL.
• One clock for each channel.
Provides the LVDS PLL status:
• Stays high when the PLL is locked to the input reference clock.
• Stays low when the PLL fails to lock.
Receiver parallel data output.
The data bus width per channel is the same as the deserialization factor (DF).
Parallel output clock from the receiver PLL.
• This signal is not available if you turn on the Use external PLL parameter setting.
• The FPGA fabric–receiver interface clock must be driven by the PLL instantiated through the ALTPLL parameter editor.
Controls the byte alignment circuitry.
You can register this signal using the rx_ outclock
signal.
Resets the byte alignment circuitry.
Use the rx_data_align_reset
input signal if:
• You need to reset the PLL during device operation.
• You need to re-establish the word alignment.
Controls byte alignment circuitry.
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Altera Soft LVDS Interface Signals signal Name
rx_cda_reset
Direction
Input
Width (Bit)
<n>
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Description
Asynchronous reset to the data realignment circuitry. This signal resets the data realign‐ ment block.
The minimum pulse width requirement for this reset is one parallel clock cycle.
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If an IP core version is not listed, the user guide for the previous IP core version applies.
IP Core Version User Guide
16.0
15.1
15.0
14.1
MAX 10 High-Speed LVDS I/O User Guide
MAX 10 High-Speed LVDS I/O User Guide
MAX 10 High-Speed LVDS I/O User Guide
MAX 10 High-Speed LVDS I/O User Guide
A
©
2016 Intel Corporation. All rights reserved. Intel, the Intel logo, Altera, Arria, Cyclone, Enpirion, MAX, Megacore, NIOS, Quartus and Stratix words and logos are trademarks of Intel Corporation in the US and/or other countries. Other marks and brands may be claimed as the property of others. Intel warrants performance of its FPGA and semiconductor products to current specifications in accordance with Intel's standard warranty, but reserves the right to make changes to any products and services at any time without notice. Intel assumes no responsibility or liability arising out of the application or use of any information, product, or service described herein except as expressly agreed to in writing by Intel. Intel customers are advised to obtain the latest version of device specifications before relying on any published information and before placing orders for products or services.
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May 2016
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Version Changes
2016.10.31 • Added related information links in the topic about LVDS channels support.
• Restructured and updated the topic about the RSKM.
• Added a topic that describes how to assign input delay to the LVDS receiver using the TimeQuest Timing Analyzer.
2016.05.02 • Added true RSDS and emulated RSDS (three resistors) transmitter support for single supply MAX 10 devices.
• Updated the transmitter and receiver channels placement topics to describe about minimizing skew when you group LVDS channels for an application.
• Updated the description of the rx_data_reset
interface signal to specify that you must externally synchronize it with the fast clock.
• Updated the General tab of the Altera Soft LVDS parameter settings:
• Added the Power Supply Mode option.
• Updated the allowed values of the SERDES factor parameter.
B
©
2016 Intel Corporation. All rights reserved. Intel, the Intel logo, Altera, Arria, Cyclone, Enpirion, MAX, Megacore, NIOS, Quartus and Stratix words and logos are trademarks of Intel Corporation in the US and/or other countries. Other marks and brands may be claimed as the property of others. Intel warrants performance of its FPGA and semiconductor products to current specifications in accordance with Intel's standard warranty, but reserves the right to make changes to any products and services at any time without notice. Intel assumes no responsibility or liability arising out of the application or use of any information, product, or service described herein except as expressly agreed to in writing by Intel. Intel customers are advised to obtain the latest version of device specifications before relying on any published information and before placing orders for products or services.
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Document Revision History for MAX 10 High-Speed LVDS I/O User Guide
Date
November 2015
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Version Changes
2015.11.02 • Updated the high-speed LVDS circuitry figure to correct the flow from
C1
in ALTPLL to inclock
of ALTERA_SOFT_LVDS.
Previously, the figure shows a bidirectional flow.
• Updated the steps for determining the external PLL clock parameters for the receiver to clarify the clock names listed by the
Quartus Prime compilation report.
• Updated the topic about Altera Soft LVDS parameter settings:
• Added links to topics about PLL and high-speed I/O perform‐ ance in the device datasheet.
• Corrected the conditions required to use the Enable tx_data_
reset port and Enable rx_data_reset port parameters. You must turn on the Use external PLL option first.
• Updated the allowed values for the Tx_outclock division factor and Outclock duty cycle parameters.
• Updated the condition for the Desired transmitter outclock
phase shift parameter.
• Removed the topics about generating IP cores and the files generated by the IP core, and added a link to
Introduction to Altera
IP Cores
.
• Removed the statement about getting TCCS value from the Quartus
Prime compilation report. You can get TCCS value from the device datasheet.
• Added guidelines topic about enabling LVDS pre-emphasis for
MAX 10 devices in the E144 package.
• Updated the guidelines to control channel-to-channel skew to remove statements about getting the trace delay amount from the
Fitter Report panel.
• Added link to video that demonstrates how to generate IBIS file using the Quartus Prime software.
• Changed instances of
Quartus II
to
Quartus Prime
.
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May 2015
December 2014
September 2014
Document Revision History for MAX 10 High-Speed LVDS I/O User Guide
B-3
Version Changes
2015.05.04 • Removed the F672 package from the 10M25 device.
• Updated the number of bottom true receiver channels for package
M153 of the 10M02 device from 49 to 13.
• Added BLVDS output support in single-supply MAX 10 devices.
Previously, BLVDS support for single-supply devices was input only.
• Updated the RSKM definition in the topic about receiver input skew margin to include jitter induced from core noise and I/O switching noise.
• Updated topics related to using the Altera Soft LVDS IP core
(transmitter or receiver) in external PLL mode:
• Added rx_readclock
, rx_syncclock
, and tx_synclock
ports.
• Removed pll_areset
port.
• Added examples for odd and even serialization factors.
• Added procedures to obtain the external PLL clock parameters.
• Removed similar guidelines in the chapter for the transmitter and receiver design. The updated guidelines for the receiver only and transmitter only designs can apply for designs that use both transmitters and receivers.
• Updated parameter settings of the Altera Soft LVDS IP core:
• Removed allowed values "6" and "9" from the SERDES factor parameter.
• Added allowed value "Off" to the Enable pll_areset port parameter.
• Updated the parameter label Register_rx_bitslip_ctrl port to
Add extra register for rx_data_align port and specified that you must pre-register the port if you turn it on.
2014.12.15 • Updated table listing LVDS channels to include LVDS channel counts for each device package.
• Added information in the topics about channels placement that
MAX 10 devices support x18 bundling mode.
• Updated the examples in topics about channels PLL placement to provide more details.
• Added link to the
MAX 10 Clocking and PLL User Guide
that provides more information about the PLL and the PLL output counters used to clock the soft SERDES.
2014.09.22 Initial release.
Document Revision History for MAX 10 High-Speed LVDS I/O User Guide
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TOC-2
Contents
MAX 10 External Memory Interface Overview.................................................. 1-1
MAX 10 External Memory Interface Architecture and Features....................... 2-1
MAX 10 External Memory Interface Design Considerations............................ 3-1
DDR2/DDR3 Recommended Termination Schemes for MAX 10 Devices.............................3-3
LPDDR2 Recommended Termination Schemes for MAX 10 Devices.....................................3-6
Guidelines: MAX 10 DDR3, DDR2, and LPDDR2 External Memory Interface I/O Limitation......3-6
Guidelines: MAX 10 Board Design Requirement for DDR2, DDR3, and LPDDR2.......................... 3-8
MAX 10 External Memory Interface Implementation Guides...........................4-1
UniPHY IP Core References for MAX 10........................................................... 5-1
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TOC-3
MAX 10 External Memory Interface User Guide Archives................................A-1
Additional Information for MAX 10 External Memory Interface User Guide
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The MAX
®
10 devices are capable of interfacing with a broad range of external memory standards. With this capability, you can utilize MAX 10 devices in a wide range of applications such as image processing, storage, communications, and general embedded systems.
The external memory interface solution in MAX 10 devices consist of:
• The I/O elements that support external memory interfaces.
• The UniPHY IP core that allows you to configure the memory interfaces to support different external memory interface standards.
Note: Altera recommends that you construct all DDR2, DDR3, and LPDDR2 SDRAM external memory interfaces using the UniPHY IP core.
(1)
•
•
•
•
•
•
•
•
•
Related Information
MAX 10 External Memory Interface Architecture and Features
MAX 10 External Memory Interface Design Considerations
on page 3-1
MAX 10 External Memory Interface Implementation Guides
UniPHY IP Core References for MAX 10
Documentation: External Memory Interfaces
Provides more information about external memory system performance specification, board design guidelines, timing analysis, simulation, and debugging.
External Memory Interface Handbook Volume 1: Altera Memory Solution Overview and Design
Flow
Provides more information about using Altera devices for external memory interfaces including Altera memory solution and design flow.
External Memory Interface Handbook Volume 2: Design Guidelines
Provides more information about using Altera devices for external memory interfaces including memory selection, board design, implementing memory IP cores, timing, optimization, and debugging.
Functional Description—MAX 10 EMIF
Provides more information about implementing memory IP cores for MAX 10 devices.
MAX 10 DDR3 Reference Design
Provides DDR3 UniPHY IP core reference design for MAX 10 devices.
1
(1)
Licensing terms and costs for UniPHY IP core apply.
©
2016 Intel Corporation. All rights reserved. Intel, the Intel logo, Altera, Arria, Cyclone, Enpirion, MAX, Megacore, NIOS, Quartus and Stratix words and logos are trademarks of Intel Corporation in the US and/or other countries. Other marks and brands may be claimed as the property of others. Intel warrants performance of its FPGA and semiconductor products to current specifications in accordance with Intel's standard warranty, but reserves the right to make changes to any products and services at any time without notice. Intel assumes no responsibility or liability arising out of the application or use of any information, product, or service described herein except as expressly agreed to in writing by Intel. Intel customers are advised to obtain the latest version of device specifications before relying on any published information and before placing orders for products or services.
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•
MAX 10 External Memory Interface Support and Performance
MAX 10 External Memory Interface User Guide Archives
on page 6-1
Provides a list of user guides for previous versions of the UniPHY IP core.
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The MAX 10 devices contain circuitry that supports several external memory interface standards.
Table 1-1: Memory Standards Supported by the Soft Memory Controller for MAX 10 Devices
Contact your local sales representatives for access to the -I6 or -A6 speed grade devices in the Quartus
Prime Software.
External Memory
Interface Standard
Rate Support Speed Grade Voltage (V) Max Frequency (MHz)
DDR3 SDRAM
DDR3L SDRAM
DDR2 SDRAM
LPDDR2
(2)
Half
Half
Half
Half
-I6
-I6
-I6
-I7 and -C7
-I6
1.5
1.35
1.8
1.2
303
303
200
167
200
(3)
•
•
•
Related Information
External Memory Interface Spec Estimator
Provides a parametric tool that allows you to find and compare the performance of the supported external memory interfaces in Altera devices.
Planning Pin and FPGA Resources chapter, External Memory Interface Handbook
Provides the maximum number of interfaces supported by MAX 10 devices for each memory standards, pin counts for various external memory interface implementation examples, and informa‐ tion about the clock, address/command, data, data strobe, DM, and optional ECC signals.
MAX 10 Device Datasheet
(2)
(3)
MAX 10 devices support only single-die LPDDR2.
To achieve the specified performance, constrain the memory device I/O and core power supply variation to within ±3%. By default, the frequency is 167 MHz.
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MAX 10 External Memory Interface Overview
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The external memory interface architecture of MAX 10 devices is a combination of soft and hard IPs.
Figure 2-1: High Level Overview of MAX 10 External Memory Interface System
This figure shows a high level overview of the main building blocks of the external memory interface system in MAX 10 devices.
User
Design
Memory
Controller
Physical
Layer (PHY)
External
Memory SDRAM
2
• The full rate data capture and write registers use the DDIO registers inside the I/O elements.
• PHY logic is implemented as soft logic in the core fabric.
• The memory controller is the intermediary between the user logic and the rest of the external memory interface system. The Altera
®
memory controller IP is a soft memory controller that operates at half rate. You can also use your own soft memory controller or a soft memory controller IP from Altera's third-party partners.
• The physical layer (PHY) serves as the bridge between the memory controller and the external memory
DRAM device.
•
•
•
Related Information
MAX 10 External Memory Interface Overview
Documentation: External Memory Interfaces
Provides more information about external memory system performance specification, board design guidelines, timing analysis, simulation, and debugging.
Intellectual Properties: Memories & Controllers
Provides a list of memory controller IP solutions from Altera and partners.
In MAX 10 devices, external memory interfaces are supported only on the I/O banks on the right side of the device. You must place all external memory I/O pins on the I/O banks on the right side of the device.
©
2016 Intel Corporation. All rights reserved. Intel, the Intel logo, Altera, Arria, Cyclone, Enpirion, MAX, Megacore, NIOS, Quartus and Stratix words and logos are trademarks of Intel Corporation in the US and/or other countries. Other marks and brands may be claimed as the property of others. Intel warrants performance of its FPGA and semiconductor products to current specifications in accordance with Intel's standard warranty, but reserves the right to make changes to any products and services at any time without notice. Intel assumes no responsibility or liability arising out of the application or use of any information, product, or service described herein except as expressly agreed to in writing by Intel. Intel customers are advised to obtain the latest version of device specifications before relying on any published information and before placing orders for products or services.
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MAX 10 DQ/DQS Groups
Figure 2-2: I/O Banks for External Memory Interfaces
This figure represents the top view of the silicon die that corresponds to a reverse view of the device package.
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PLL 8 7 PLL
Only the top right PLL is usable for external memory interfaces
1A
6
1B
External memory interface support only available on
I/O banks on the right side of the device.
2
5
PLL 3 4
OCT
PLL
External memory interfaces support is available only for 10M16, 10M25, 10M40, and 10M50 devices.
Different MAX 10 devices and packages support different numbers of DQ/DQS groups for external memory interfaces.
Table 2-1: Supported DQ/DQS Group Sizes in MAX 10 Devices and Packages
This table lists the number of DQ/DQS groups supported on different MAX 10 devices and packages. Only the I/O banks on the right side of the devices support external memory interfaces.
Number of DQ Groups
Device Package
I/O Bank
(Right Side) x8
10M16
F256, U324, and
F484
B5
B6
1
1
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10M25
10M40
10M50
Device
F256
F484
F256
F484
F672
F256
F484
F672
Package
I/O Bank
(Right Side)
B5
B6
B5
B6
B5
B6
B5
B6
B5
B6
B5
B6
B5
B6
B5
B6
MAX 10 External Memory Interfaces Maximum Width
Number of DQ Groups x8
2
2
1
2
1
1
2
2
1
2
1
1
1
1
1
2
2-3
Related Information
Planning Pin and FPGA Resources chapter, External Memory Interface Handbook
Provides the maximum number of interfaces supported by MAX 10 devices for each memory standards, pin counts for various external memory interface implementation examples, and information about the clock, address/command, data, data strobe, DM, and optional ECC signals.
Different MAX 10 device packages support different maximum width for external memory interfaces.
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MAX 10 External Memory Interfaces Maximum Width
Table 2-2: Supported Maximum External Memory Interface Width in MAX 10 Device Packages
Product Line
10M16
F256 U324
Package
F484 F672
—
• x8 DDR2,
DDR3/3L, and
LPDDR2 without ECC
• x16 LPDDR2 without ECC
• x8 DDR2,
DDR3/3L, and
LPDDR2 without ECC
• x16 DDR2, and
DDR3/3L with or without ECC
• x16 LPDDR2 without ECC
• x8 DDR2,
DDR3/3L, and
LPDDR2 without ECC
• x16 DDR2, and
DDR3/3L with or without ECC
• x16 LPDDR2 without ECC
10M25 —
• x8 DDR2,
DDR3/3L, and
LPDDR2 without ECC
• x16 LPDDR2 without ECC
• x8 DDR2,
DDR3/3L and
LPDDR2 without ECC
• x16 DDR2, and
DDR3/3L with or without ECC
• x24 DDR2, and
DDR3/3L with
ECC
• x16 LPDDR2 without ECC
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• x8 DDR2, DDR3/3L, and LPDDR2 without
ECC
• x16 DDR2, and DDR3/
3L with or without ECC
• x24 DDR2, and DDR3/
3L with ECC
• x16 LPDDR2 without
ECC
10M40 —
• x8 DDR2,
DDR3/3L and
LPDDR2 without ECC
• x16 LPDDR2 without ECC
• x8 DDR2,
DDR3/3L, and
LPDDR2 without ECC
• x16 DDR2, and
DDR3/3L with or without ECC
• x24 DDR2, and
DDR3/3L with
ECC
• x16 LPDDR2 without ECC
• x8 DDR2, DDR3/3L, and LPDDR2 without
ECC
• x16 DDR2, and DDR3/
3L with or without ECC
• x24 DDR2, and DDR3/
3L with ECC
• x16 LPDDR2 without
ECC
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Product Line
10M50
F256
• x8 DDR2,
DDR3/3L, and
LPDDR2 without ECC
• x16 LPDDR2 without ECC
U324
—
MAX 10 Memory Controller
Package
F484
• x8 DDR2,
DDR3/3L, and
LPDDR2 without ECC
• x16 DDR2, and
DDR3/3L with or without ECC
• x24 DDR2, and
DDR3/3L with
ECC
• x16 LPDDR2 without ECC
F672
• x8 DDR2, DDR3/3L, and LPDDR2 without
ECC
• x16 DDR2, and DDR3/
3L with or without ECC
• x24 DDR2, and DDR3/
3L with ECC
• x16 LPDDR2 without
ECC
2-5
MAX 10 devices use the HPC II external memory controller.
Table 2-3: Features of the MAX 10 Memory Controller
Feature
Half-Rate Operation
Description
The controller and user logic can run at half the memory clock rate.
Controller Latency
The controller has a low best-case time between a read request or a write request on the local interface, and the memory command being sent to the AFI interface.
Data Reordering
The memory controller will reorder read and write requests as necessary to achieve the most efficient throughput of data.
Starvation Control
The controller implements a starvation counter to limit the length of time that a command can go unserved. This counter ensures that lower-priority requests are not overlooked indefinitely due to data reordering. You can set a starvation limit, to ensure that a waiting command is served immediately, when the starvation counter reaches the specified limit.
Priority Bypass
The memory controller accepts user requests to bypass the priority established by data reordering. When the controller detects a highpriority request, it allows that request to bypass the current queue. The high-priority request is then processed immediate, reducing latency.
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MAX 10 External Memory Read Datapath
Feature
Standard Interface
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Description
The memory controller uses Avalon-ST as its native interface, allowing the flexibility to extend to Avalon-MM, AXI, or a proprietary protocol with an adapter.
Avalon-MM Data Slave Local
Interface
Bank Management
The controller supports the Altera Avalon memory-mapped protocol.
The memory controller will intelligently keep a page open based on incoming traffic, improving efficiency, especially for random traffic.
Streaming Reads and Writes
The memory controller has the ability to issue reads or writes continu‐ ously to sequential addresses each clock cycle, if the bank is open. This feature allows for the passage of large amounts of data, with high efficiency.
Bank Interleaving
The memory controller has the ability to issue reads or writes continu‐ ously to random addresses. The bank addresses must be correctly cycled by user logic.
Predictive Bank Management
The memory controller has the ability to issue bank management commands early, so that the correct row is already open when a read or write request occurs. This feature allows for increased efficiency.
Quasi-1T Address/Command
Half-Rate
One controller clock cycle equals two memory clock cycles in a halfrate interface. To maximize command bandwidth, the memory controller provides the option to allow two memory commands on every controller clock cycle. The controller is constrained to issue a row command on the first clock phase and a column command on the second clock phase, or vice versa. Row commands include activate and precharge commands; column commands include read and write commands.
Built-In Burst Adaptor
The memory controller has the ability to accept bursts of arbitrary size on the local interface, and map these to efficient memory commands.
Self-Refresh Controls and User
Auto-Refresh Controls
The memory controller has the ability to issue self-refresh commands and allow user auto-refresh through a sideband interface.
Enable Auto Power-Down
The memory controller has the ability to power-down if no commands are received.
In MAX 10 devices, instead of using DQS strobes, the memory interface solution uses internal read capture clock to capture data directly in the double data rate I/O (DDIO) registers in the I/O elements.
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DDR Input Registers
2-7
• The PLL supplies memory clock to the DRAM device and generates read capture clock that is frequency-locked to the incoming data stream. The read capture clock and the incoming read data stream have an arbitrary phase relationship.
• For maximum timing margin, calibration sequence is used to position the read capture clock within the optimum sampling position in the read data eye.
• Data is captured directly in the DDIO registers implemented in the I/O periphery.
The DDR input capture registers in MAX 10 devices are implemented in the I/O periphery.
Figure 2-3: External Memory Interface Read Datapath
FPGA Core FPGA Periphery
afi_rdata_en read_increment_vfifo
(from Sequencer) read_latency_counter
(from Sequencer) afi_rdata afi_rdata_valid
Latency Shifter
D
CLK latency_counter
Q
FIFO Shifter
D
INCR
CLK
Q
RDATA_LFIFO rdreq
Q wrreq
D
CLK
From Other DQ within DQS Group
Q
RDATA_FIFO
D
RD CLK WR CLK
Q
Q
Input HR Register
Input HR Register
D Q D
Q
Q D Q D
Q Q dataout
DDIO_IN pad fr_clk hr_clk inclock
DQ
PLL
GCLK AFI_CLK (HR)
PHYCLK MEM_CLK (FR)
PHYCLK DQ_WRITE_CLK (FR)
PHYCLK READ_CAPTURE_CLK0
TRACKING_CLK clkin[0] clkin[1] clkin[2] clkin[3]
PHYCLK clkout[0] clkout[1] clkout[2] clkout[3]
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MAX 10 External Memory Write Datapath
Figure 2-4: External Memory Interface Read Datapath Timing
afi clock afi_rdata_en write_enable for LFIFO
(afi_rdata_valid) data transferred marked as valid soft
VFIFO pipe read_enable for LFIFO data transferred marked as valid afi_clk captured data
(after rdata _fifo) capture clock /2
HR register output
(clocked by div /2 clock)
2 nd
flopped data first ddio data captured on soft hard capture clock read mem _dq ddio output ba ba dc dcba dc fe a b c d e f g h ba dc fe hg dcba fe hg hgfe hg dcba hgfe dcba hgfe hgfe
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In MAX 10 external memory interfaces, post-amble is not a concern because the read data strobe signal,
DQS, is not used during read operation.
For all DDR applications supported by MAX 10 devices, the DQS strobe is sent to the external DRAM as center-aligned to the write DQ data.
The clock that clocks DDIO registers of the DQ output is phase-shifted –90º from the clock that drives the
DDIO registers of the DQS strobe. This create a DQS strobe that is center-aligned to the DQ data.
The external memory write datapath is not calibrated.
A dedicated DDIO write block is implemented in the DDR output and output enable paths.
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Figure 2-5: External Memory Interface Write Datapath
DDR Output Registers
afi_wdata_valid
PLL
4
FPGA Core
Full Rate Cycle
Shifter for WL
Adjustment
D fr_cycle_shifter
Q
4 afi_wdata
4
D fr_cycle_shifter
Q
4
GCLK AFI_CLK (HR)
PHYCLK MEM_CLK (FR)
PHYCLK DQ_WRITE_CLK (FR)
PHYCLK READ_CAPTURE_CLK0
TRACKING_CLK
Multiplexer Generator datain muxsel fr_clk afi_dqs_burst
4
D fr_cycle_shifter
Q
4
Multiplexer Generator datain muxsel fr_clk
FPGA Periphery
Simple DDIO datain hr_clk fr_clk muxsel dataout
2
Transfer Register
D Q
2
Q
D Q
Q
Simple DDIO datain hr_clk fr_clk muxsel dataout
2
Transfer Register
D Q
2
Simple DDIO datain hr_clk fr_clk muxsel dataout
2
Q
Transfer Register
D Q
2 dqs/dqs#
2
Q
Transfer Register
D Q
2
DDIO OUT
D Q
D
Q
Q
Q
DDIO OUT
D Q
Q Q clkin[0] clkin[1] clkin[2] clkin[3]
PHYCLK clkout[0] clkout[1] clkout[2] clkout[3]
2-9
DQ
DQS
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MAX 10 Address/Command Path
Figure 2-6: External Memory Interface Write Datapath Timing
afi Clock soft
Write Data afi_wdata phy_ddio_dq
(after fr_cycle_shifter)
Multiplexer Select
WR DATA Hi
WR DATA Lo
Write Data Valid afi_wdata_valid[0] afi_wdata_valid[1] phy_ddio_wrdata_en[0]
(after fr_cycle_shifter) phy_ddio_wrdata_en[1]
(after fr_cycle_shifter) afi_dqs_burst[0]
DQS Enable abcd cd xx afi_dqs_burst[1] phy_ddio_dqs_en[0]
(after fr_cycle_shifter) phy_ddio_dqs_en[1]
(after fr_cycle_shifter)
Multiplexer Select
DQS_OE
DQ_OE
Memory Clock
Transferred DQS_OE
Transferred DQ_OE adc Clock mem_dq mem_dqs mem_dqs_n hard efgh ghab xx ef x x d c b a g h f e x x d c b a h g f e
Altera's soft memory controller IP and PHY IP operate at half rate and issue address/command instructions at half-rate.
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MAX 10 PHY Clock (PHYCLK) Network
2-11
• You must send the address/command instructions to the external DRAM center-aligned with respect to the external memory clock (CK/CK#).
• For LPDDR2 applications, the address/command path is double data rate (DDR). Dedicated DDIO output registers in the I/O periphery clocks out the address/command instructions to the external
DRAM.
• For DDR2/3 applications, the address/command path is single data rate (SDR). Instead of dedicated
DDIO output registers, simple output I/O registers in the I/O periphery clocks out the address/ command instructions to the external DRAM device.
The PHYCLK network is a dedicated high-speed and low skew balanced clock tree that provides better clock skew for external memory interface applications.
In MAX 10 devices, only the top right PLL is routed to the PHYCLK tree. Therefore, the PHYCLK tree is available only for the I/O banks on the right side of the MAX 10 10M16, 10M25, 10M40, and 10M50 devices.
Figure 2-7: I/O Banks for External Memory Interfaces
This figure represents the top view of the silicon die that corresponds to a reverse view of the device package.
PLL 8 7 PLL
Only the top right PLL is usable for external memory interfaces
1A
1B
6
External memory interface support only available on
I/O banks on the right side of the device.
2
5
PLL 3 4
OCT
PLL
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Phase Detector for VT Tracking
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There may be variations in the read and write paths caused by voltage and temperature changes. The phase detector keeps track of the variation of the mimic clock to optimize the system timing.
Figure 2-8: VT Tracking System Overview
CK/CK# 2
I/O Register
DDIO
Out
CK/CK#
DRAM
RESET
ACK
PD_UP
PD_DOWN
Phase Detector
Phase alignment
MIMIC_CLK_P/N
Dynamic Phase
Shift Control
PLL
GCLK SYS_CLK (HR)
PHYCLK MEM_CLK (FR)
PHYCLK DQ_WRITE_CLK (FR)
PHYCLK READ_CAPTURE_CLK (FR)
TRACKING_CLK (FR)
In the MAX 10 external memory interface solution, the memory clocks are used to mimic the read and write paths. The memory clock pins loop back to the phase detector as a mimic clock. The phase detector provides any variation of the mimic clock to the sequencer. The sequencer adjusts the read capture clock to match the clock phase change.
The MAX 10 devices support calibrated on-chip series termination (R
S
OCT) on the right side I/O banks.
• To use the calibrated OCT, use the
RUP
and
RDN
pins for each R
S
OCT control block.
• You can use each OCT calibration block to calibrate one type of termination with the same V
CCIO
.
You must set the
RUP
and
RDN
resistor values according to the R value is 34 Ω, then the set both
RUP
and
RDN
value to 34 Ω.
S
OCT value. For example, if the R
S
OCT
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Phase-Locked Loop
2-13
Related Information
MAX 10 On-Chip I/O Termination
Provides more information about OCT.
For the external memory interface, the PLL generates the memory clock, write clock, capture clock, and the logic–core clock.
• The memory clock provides clock for DQS write strobe, and address and command signals.
• The write clock that is shifted –90° from the memory clock provides clock for DQ signals during memory writes.
You can use the PLL reconfiguration feature to calibrate the read–capture phase shift to balance the setup and hold margins. At startup, the sequencer calibrates the capture clock.
For external memory interfaces in MAX 10 devices, you must use the top right PLL (PLL 2).
Related Information
PLL Locations
Provides more information about PLL location and availability in different MAX 10 packages.
The MAX 10 low power feature is automatically activated when the self refresh or low power down modes are activated. The low power feature sends the afi_mem_clk_disable
signal to stop the clock used by the controller.
To conserve power, the MAX 10 UniPHY IP core performs the following functions:
• Tri-states the address and command signals except
CKE
and
RESET_N
signals
• Disables the input buffer of DDR input
Note: The MAX 10 low power feature is available from version 15.0 of the Quartus version 15.0 or later.
®
Prime software. To enable this feature, regenerate your MAX 10 UniPHY IP core using the Quartus Prime software
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There are several considerations that require your attention to ensure the success of your designs. Unless noted otherwise, these design guidelines apply to all variants of this device family.
•
•
Related Information
MAX 10 External Memory Interface Overview
Planning Pin and FPGA Resources chapter, External Memory Interface Handbook
Provides pin planning guidelines for implementing external memory interfaces with Altera devices.
3
In DDR2/DDR3 interfaces, the MAX 10 devices use data (DQ), data strobe (DQS), clock, address, and command pins to interface with external memory devices. The devices also use the data mask (DM) pins to enable data masking.
Related Information
DDR2/DDR3 Recommended Termination Schemes for MAX 10 Devices
on page 3-3
For the MAX 10 external memory interfaces, the DQ pins are the data pins for bidirectional read and write, and the DQS pins are the data strobe pins used only during write operations.
The MAX 10 devices support bidirectional data strobes. Connect the bidirectional DQ data signals to the same MAX 10 device DQ pins. The DQS pin is used only during write mode. In read mode, the MAX 10
PHY generates the read capture clock internally and ignores the DQS signal. However, you must still connect DQS signal to the MAX 10 DQS pin.
Related Information
Guidelines: Reading the MAX 10 Pin-Out Files
on page 3-8
MAX 10 I/O Bank DQ/DQS Support for DDR2/DDR3
For DDR2/DDR3 SDRAM, I/O banks 5 and 6 in MAX 10 devices can support DQ and DQS signals with
DQ-bus widths of 8, 16 and 24 bits.
©
2016 Intel Corporation. All rights reserved. Intel, the Intel logo, Altera, Arria, Cyclone, Enpirion, MAX, Megacore, NIOS, Quartus and Stratix words and logos are trademarks of Intel Corporation in the US and/or other countries. Other marks and brands may be claimed as the property of others. Intel warrants performance of its FPGA and semiconductor products to current specifications in accordance with Intel's standard warranty, but reserves the right to make changes to any products and services at any time without notice. Intel assumes no responsibility or liability arising out of the application or use of any information, product, or service described herein except as expressly agreed to in writing by Intel. Intel customers are advised to obtain the latest version of device specifications before relying on any published information and before placing orders for products or services.
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Data Mask Pins
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• For DDR2 and DDR3 SDRAM interfaces, the devices use ×8 mode DQS group regardless of the interface width.
• If you need to support wider interfaces, use multiple ×8 DQ groups.
• You can use any unused DQ pins as regular user I/O pins if they are not used as memory interface signals.
• The x24 interface is implemented through x16 + ECC.
Related Information
on page 2-2
Provides the supported DQ/DQS groups for each device.
In MAX 10 devices, the data mask (
DM
) pins are pre-assigned in the device pinouts. Although the Quartus
Prime Fitter treats the
DQ
and
DM
pins in a DQS group equally for placement purposes, the pre-assigned
DQ and
DM
pins are the preferred pins.
Each group of
DQS
and
DQ
signals has one
DM
pin:
• You require data mask (
DM
) pins only while writing to the external memory devices.
• A low signal on the
DM
pin indicates that the write is valid.
• Driving the
DM
pin high causes the memory to mask the
DQ
signals.
• Similar to the DQ output signals, the DM signals are clocked by the –90º shifted clock.
Some DDR2 and DDR3 SDRAM devices support error correction coding (ECC). ECC is a method of detecting and automatically correcting errors in data transmission.
• In 24-bit DDR2 or DDR3 SDRAM, there are eight ECC data pins and 16 data pins.
• Connect the DDR2 and DDR3 SDRAM ECC pins to a separate DQS or DQ group in the MAX 10 device.
• The memory controller needs additional logic to encode and decode the ECC data.
Related Information
ALTECC (Error Correction Code: Encoder/Decoder) chapter, Integer Arithmetic Megafunctions User
Guide
Provides more information about ALTECC_ENCODER and ALTECC_DECODER IP cores that implement ECC functionality.
For DDR2/DDR3 interfaces, the address signals and the control or command signals are sent at a single data rate.
You can use any of the user I/O pins on banks 5 & 6 of MAX 10 devices to generate the address and control or command signals to the external memory device.
At the external memory device, the memory clock signals (CK and CK#) are used to capture the address signals, and the control or command signals.
In MAX 10 devices, the double data rate I/O (DDIO) registers are used to generate the CK/CK# signals.
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DDR2/DDR3 Recommended Termination Schemes for MAX 10 Devices
3-3
The memory clock pins are predefined and are listed in the device pinout files. Refer to the the relevant device pinout files to determine the locations of the memory clock pins.
•
•
Related Information
Pin Connection Guidelines Tables, Planning Pin and FPGA Resources chapter, External Memory
Interface Handbook
Provides more information about CK/CK# pins placement.
MAX 10 Device Pin-Out Files
If you are creating interfaces with multiple DDR2 or DDR3 components where the address, command, and memory clock pins are connected to more than one load, follow these steps:
1. Simulate the system to get the new slew-rate for the DQ/DQS, DM, address and command, and clock signals.
2. Use the derated t
IS
and t
IH
specifications from the DDR2 or DDR3 datasheet based on the simulation results.
3. If timing deration causes your interface to fail timing requirements, consider duplication of these signals to lower their loading, and hence improve timing.
Note: Class I and Class II termination schemes in the following tables refer to drive strength and not physical termination.
Table 3-1: Termination Recommendations for MAX 10 DDR2 Component
Signal Type
DQ/DQS
DM
Address and command
Clock
SSTL 18 I/O
Standard
FPGA–End Discrete
Termination
Class I 12 mA 50 Ω parallel to V discrete
TT
Class I 12 mA
Class I with maximum drive strength
—
—
Class I 12 mA —
Memory–End Termination 1
ODT75
(4)
56 Ω parallel to V
TT
discrete
• x1 = 100 Ω differential (6)
• x2 = 200 Ω differential.
(7)
Memory I/O Standard
HALF
(5)
—
—
—
Table 3-2: On Board Termination Recommendation for MAX 10 DDR3 Component
For MAX 10 devices, on board termination is required for DDR3 component.
(5)
(6)
(7)
(4)
ODT75 vs. ODT50 on the memory has the effect of opening the eye more, with a limited increase in overshoot/undershoot.
HALF is reduced drive strength.
x1 is a single-device load.
x2 is a two-device load.
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LPDDR2 Design Considerations
I/O Standard
SSTL 15 Class 1
R
S
OCT
50 Ω without calibration
FPGA–End
80 Ω resistor
On Board Termination
Memory-End
40 Ω resistor
Table 3-3: Supported External Memory Interface Termination Scheme for DDR3 and DDR2
Memory Interface
Standard
I/O Standard R
S
OCT R
UP
, R
DN
(Ω)
DDR3
DDR3L
DDR2
SSTL-15
SSTL-135
SSTL-18
25
34
40
50
34
40
25
50
25
34
40
50
34
40
25
50
Related Information
Planning Pin and FPGA Resources
Provides more information about termination and signal duplication.
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Note: MAX 10 devices support single-die LPDDR2 only.
In LPDDR2 interfaces, the MAX 10 devices use data (DQ), data strobe (DQS), clock, command, and address pins to interface with external memory devices. The devices also use the data mask (DM) pins to enable data masking.
For the MAX 10 external memory interfaces, the DQ pins are the data pins for bidirectional read and write, and the DQS pins are the data strobe pins used only during write operations.
The MAX 10 devices support bidirectional data strobes. Connect the bidirectional DQ data signals to the same MAX 10 device DQ pins. The DQS pin is used only during write mode. In read mode, the MAX 10
PHY generates the read capture clock internally and ignores the DQS signal. However, you must still connect DQS signal to the MAX 10 DQS pin.
Related Information
Guidelines: Reading the MAX 10 Pin-Out Files
on page 3-8
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MAX 10 I/O Bank DQ/DQS Support for LPDDR2
3-5
MAX 10 I/O Bank DQ/DQS Support for LPDDR2
For LPDDR2 SDRAM, I/O banks 5 and 6 in MAX 10 devices can support DQ and DQS signals with DQbus widths of 8 and 16 bits.
• For LPDDR2 SDRAM interfaces, the devices use ×8 mode DQS group regardless of the interface width.
• If you need to support wider interfaces, use multiple ×8 DQ groups.
• You can use any unused DQ pins as regular user I/O pins if they are not used as memory interface signal.
Related Information
on page 2-2
Provides the supported DQ/DQS groups for each device.
In MAX 10 devices, the data mask (
DM
) pins are pre-assigned in the device pinouts. Although the Quartus
Prime Fitter treats the
DQ
and
DM
pins in a DQS group equally for placement purposes, the pre-assigned
DQ and
DM
pins are the preferred pins.
Each group of
DQS
and
DQ
signals has one
DM
pin:
• You require data mask (
DM
) pins only while writing to the external memory devices.
• A low signal on the
DM
pin indicates that the write is valid.
• Driving the
DM
pin high causes the memory to mask the
DQ
signals.
• Similar to the DQ output signals, the DM signals are clocked by the –90º shifted clock.
For LPDDR2 interfaces, the address signals and the control or command signals are sent at double data rate.
You can use any of the user I/O pins on banks 5 & 6 of MAX 10 devices to generate the address and control or command signals to the external memory device.
At the external memory device, the memory clock signals (CK and CK#) are used to capture the address signals, and the control or command signals.
In MAX 10 devices, the double data rate I/O (DDIO) registers are used to generate the CK/CK# signals.
The memory clock pins are predefined and are listed in the device pinout files. Refer to the the relevant device pinout files to determine the locations of the memory clock pins.
•
•
Related Information
Pin Connection Guidelines Tables, Planning Pin and FPGA Resources chapter, External Memory
Interface Handbook
Provides more information about CK/CK# pins placement.
MAX 10 Device Pin-Out Files
For an LPDDR2 interface that targets 200 MHz, constrain the memory device I/O and core power supply variation to within ±3%.
MAX 10 External Memory Interface Design Considerations
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LPDDR2 Recommended Termination Schemes for MAX 10 Devices
• Memory I/O power supply pin is
VDDQ
• Memory core power supply pin is
VDD
Related Information
MAX 10 Power Management User Guide
Table 3-4: Supported External Memory Interface Termination Scheme for LPDDR2
Memory Interface
Standard
LPDDR2
I/O Standard
HSUL-12
R
S
OCT
34, 40, 48
R
UP
, R
DN
(Ω)
34, 40, 48
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While implementing certain external memory interface standards, the number of I/O pins available is limited.
• While implementing DDR2—for 25 percent of the remaining I/O pins available in I/O banks 5 and 6, you can assign them only as input pins.
• While implementing DDR3 or LPDDR2—the I/O pins listed in the following table are not available for use. Of the remaining I/O pins, you can assign only 75 percent of the available I/O pins in I/O banks 5 and 6 for normal I/O operation.
Table 3-5: Unavailable I/O Pins While Implementing DDR3 or LPDDR2 External Memory Interfaces in
Certain Device Packages—Preliminary
Device
F256 U324
Package
F484 F672
10M16 N16
P16
R15
P15
R18
P18
E16
D16
F21
F20
E19
F18
U21
U22
M21
L22
—
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Device
10M25
10M40
10M50
Guidelines: MAX 10 DDR3, DDR2, and LPDDR2 External Memory Interface I/O
Limitation
Package
F256 U324 F484 F672
N16
P16
— U21
U22
M21
L22
F21
F20
E19
F18
F17
E17
—
N16
P16
— U21
U22
M21
L22
F21
F20
E19
F18
F17
E17
W23
W24
U25
U24
T24
R25
R24
P25
K23
K24
J23
H23
G23
F23
G21
G22
3-7
MAX 10 External Memory Interface Design Considerations
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Guidelines: MAX 10 Board Design Requirement for DDR2, DDR3, and LPDDR2
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• For DDR2, DDR3, and LPDDR2 interfaces, the maximum board skew between pins must be lower than 40 ps. This guideline applies to all pins (address, command, clock, and data).
• To minimize unwanted inductance from the board via, Altera recommends that you keep the PCB via depth for V
CCIO
banks below 49.5 mil.
• For devices with DDR3 interface implementation, onboard termination is required for the DQ, DQS, and address signals. Altera recommends that you use termination resistor value of 80 Ω to V
TT
.
• For the DQ, address, and command pins, keep the PCB trace routing length less than six inches for
DDR3, or less than three inches for LPDDR2.
•
•
•
•
Related Information
External Memory Interface Handbook Volume 1: Altera Memory Solution Overview and Design
Flow
Provides more information about using Altera devices for external memory interfaces including Altera memory solution and design flow.
External Memory Interface Handbook Volume 2: Design Guidelines
Provides more information about using Altera devices for external memory interfaces including memory selection, board design, implementing memory IP cores, timing, optimization, and debugging.
Functional Description—MAX 10 EMIF
Provides more information about implementing memory IP cores for MAX 10 devices.
MAX 10 FPGA Signal Integrity Design Guidelines
Provides design guidelines related to signal integrity for MAX 10 devices.
•
•
For the maximum number of DQ pins and the exact number per group for a particular MAX 10 device, refer to the relevant device pin-out files.
In the pin-out files, the
DQS
and
DQSn
pins denote the differential data strobe/clock pin pairs. The
DQS
and
DQSn
pins are listed in the MAX 10 pin-out files as
DQSXR
and
DQSnXR
:
X
indicates the DQ/DQS grouping number.
R
indicates the location of the group which is always on the right side of the device.
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You can implement your external memory interface design in the Quartus Prime software. The software contains tools for you to create and compile you design, and configure your device.
In the Quartus Prime software, you can instantiate and configure the UniPHY IP core to suit your memory interface requirement.
•
•
•
•
•
Related Information
MAX 10 External Memory Interface Overview
External Memory Interface Handbook Volume 1: Altera Memory Solution Overview and Design
Flow
Provides more information about using Altera devices for external memory interfaces including Altera memory solution and design flow.
External Memory Interface Handbook Volume 2: Design Guidelines
Provides more information about using Altera devices for external memory interfaces including memory selection, board design, implementing memory IP cores, timing, optimization, and debugging.
Functional Description—MAX 10 EMIF
Provides more information about implementing memory IP cores for MAX 10 devices.
MAX 10 DDR3 Reference Design
Provides DDR3 UniPHY IP core reference design for MAX 10 devices.
4
The UniPHY IP core allows you to control the soft IP of the MAX 10 external memory interface solution.
©
2016 Intel Corporation. All rights reserved. Intel, the Intel logo, Altera, Arria, Cyclone, Enpirion, MAX, Megacore, NIOS, Quartus and Stratix words and logos are trademarks of Intel Corporation in the US and/or other countries. Other marks and brands may be claimed as the property of others. Intel warrants performance of its FPGA and semiconductor products to current specifications in accordance with Intel's standard warranty, but reserves the right to make changes to any products and services at any time without notice. Intel assumes no responsibility or liability arising out of the application or use of any information, product, or service described herein except as expressly agreed to in writing by Intel. Intel customers are advised to obtain the latest version of device specifications before relying on any published information and before placing orders for products or services.
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UniPHY IP Core
Figure 4-1: MAX 10 UniPHY IP Core Block Diagram
External Memory Interface IP
PLL
I/O Structure
Reference Clock
External
Memory
Device
DQ I/O
I/O Block
PHY
Calibration
Sequencer
Write Path
Read Path
Address/Command
Path
Memory
Controller
•
•
•
Related Information
Introduction to Altera IP Cores
Provides general information about all FPGA IP cores, including parameterizing, generating, upgrading, and simulating IP cores.
Creating Version-Independent IP and Qsys Simulation Scripts
Create simulation scripts that do not require manual updates for software or IP version upgrades.
Project Management Best Practices
Guidelines for efficient management and portability of your project and IP files.
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LPDDR2 External Memory Interface Implementation
Figure 4-2: Top Level View of LPDDR2 Architecture in MAX 10 Devices
Off FPGA Core
Soft Memory
Controller
PLL clk[0] clk[1] clk[2] clk[3]
DQ x8 group
(soft)
8 fr_resync_clk hr_resync_clk
DQ x8 group
(soft)
8 fr_resync_clk hr_resync_clk
GCLK sys_clk phy_mem_clk dq_write_clk read_capture_clk dqs_tracking_clk
Periphery
Memory PHY
DQ x8 group
DQ x8 group
PHYCLK
External Memory
Device
4-3
Related Information
Planning Pin and FPGA Resources chapter, External Memory Interface Handbook
Provides the maximum number of interfaces supported by MAX 10 devices for each memory standards, pin counts for various external memory interface implementation examples, and information about the clock, address/command, data, data strobe, DM, and optional ECC signals.
For LPDDR2, the external memory interface IP for MAX 10 devices uses one capture clock and one tracking clock with one discrete device.
Figure 4-3: Supported Topology for LPDDR2 Memory Interfaces
This figure shows the supported LPDDR2 topology. Only one discrete LPDDR2 device is supported with a
16 bit maximum interface width. The memory interface IP in MAX 10 devices generates LPDDR2 IPs targeted for this configuration only.
FPGA
16
LPDDR2
CS
MAX 10 External Memory Interface Implementation Guides
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DDR2 and DDR3 External Memory Interface Implementation
Figure 4-4: Top Level View of DDR2, DDR3, or DDR3L Architecture in MAX 10 Devices
Soft Memory
Controller
PLL clk[0] clk[1] clk[2] clk[3]
Core
DQ x8 group
(soft)
8 fr_resync_clk hr_resync_clk
DQ x8 group
(soft)
8 fr_resync_clk hr_resync_clk
DQ x8 group
(soft)
8 fr_resync_clk hr_resync_clk
GCLK sys_clk
Periphery
Memory PHY
DQ x8 group
DQ x8 group
DQ x8 group phy_mem_clk dq_write_clk read_capture_clk read_capture_ecc_clk
PHYCLK
Off FPGA
External Memory
Device
External Memory
Device
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Related Information
Planning Pin and FPGA Resources chapter, External Memory Interface Handbook
Provides the maximum number of interfaces supported by MAX 10 devices for each memory standards, pin counts for various external memory interface implementation examples, and information about the clock, address/command, data, data strobe, DM, and optional ECC signals.
For DDR2 or DDR3/DDR3L, the external memory interface IP for MAX 10 devices uses two capture clocks with two discrete devices.
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MAX 10 Supported DDR2 or DDR3 Topology
4-5
Figure 4-5: Supported Topology for DDR2 or DDR3 Memory Interfaces
This figure shows the supported DDR2/DDR3 topology. One clock captures the lower 16 bit of data and the other clock captures the top 8 bit of data. The memory interface IP in MAX 10 devices generates
DDR2 or DDR3/DDR3L IPs targeted for this configuration only.
FPGA
16
DDR3
CS
8
DDR3
MAX 10 External Memory Interface Implementation Guides
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For MAX 10 devices, there are three variations of the UniPHY IP core:
• DDR2 SDRAM Controller
• DDR3 SDRAM Controller
• LPDDR2 SDRAM Controller
•
•
•
•
Related Information
MAX 10 External Memory Interface Overview
External Memory Interface Handbook Volume 1: Altera Memory Solution Overview and Design
Flow
Provides more information about using Altera devices for external memory interfaces including Altera memory solution and design flow.
External Memory Interface Handbook Volume 2: Design Guidelines
Provides more information about using Altera devices for external memory interfaces including memory selection, board design, implementing memory IP cores, timing, optimization, and debugging.
Functional Description—MAX 10 EMIF
Provides more information about implementing memory IP cores for MAX 10 devices.
You can set the parameter settings for the UniPHY IP core in the Quartus Prime software. There are six groups of options: PHY Settings, Memory Parameters, Memory Timing, Board Settings, Controller
Settings, and Diagnostics.
Note: MAX 10 devices are not supported in the EMIF Debug Toolkit.
There are three groups of options: General Settings, Clocks, and Advanced PHY Settings.
5
©
2016 Intel Corporation. All rights reserved. Intel, the Intel logo, Altera, Arria, Cyclone, Enpirion, MAX, Megacore, NIOS, Quartus and Stratix words and logos are trademarks of Intel Corporation in the US and/or other countries. Other marks and brands may be claimed as the property of others. Intel warrants performance of its FPGA and semiconductor products to current specifications in accordance with Intel's standard warranty, but reserves the right to make changes to any products and services at any time without notice. Intel assumes no responsibility or liability arising out of the application or use of any information, product, or service described herein except as expressly agreed to in writing by Intel. Intel customers are advised to obtain the latest version of device specifications before relying on any published information and before placing orders for products or services.
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Registered
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UniPHY Parameters—PHY Settings
Table 5-1: PHY Settings - General Settings
Parameter
Speed Grade
Description
Specifies the speed grade of the targeted FPGA device that affects the generated timing constraints and timing reporting.
Note: For MAX 10 devices, DDR3 and LPDDR2 is supported only for speed grade –6, and DDR2 for speed grades –6 and –7.
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Generate PHY only
Turn on this option to generate the UniPHY IP core without a memory controller.
When you turn on this option, the AFI interface is exported so that you can easily connect your own memory controller.
Table 5-2: PHY Settings - Clocks
Parameter
Memory clock frequency
Description
The frequency of the clock that drives the memory device. Use up to 4 decimal places of precision.
To obtain the maximum supported frequency for your target memory configuration, refer to the External Memory Spec Estimator page on the Altera website.
Achieved memory clock frequency
The actual frequency the PLL generates to drive the external memory interface (memory clock).
PLL reference clock frequency
The frequency of the input clock that feeds the PLL. Use up to 4 decimal places of precision.
Rate on Avalon-MM interface
The width of data bus on the Avalon-MM interface.
The MAX 10 supports only Half rate, which results in a width of 4× the memory data width.
Achieved local clock frequency The actual frequency the PLL generates to drive the local interface for the memory controller (AFI clock).
Table 5-3: DDR3 SDRAM PHY Settings - Advanced PHY Settings
Parameter
Supply voltage
Description
The supply voltage and sub-family type of memory.
This option is available for DDR3 SDRAM only.
I/O standard
The I/O standard voltage.
Set the I/O standard according to your design’s memory standard.
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Parameter
Reconfigurable PLL location
UniPHY Parameters—Memory Parameters
Description
If you set the PLL used in the UniPHY IP core memory interface to be reconfigurable at run time, you must specify the location of the PLL.
This assignment generates a PLL that can only be placed in the given sides.
5-3
Related Information
External Memory Interface Spec Estimator
Provides a parametric tool that allows you to find and compare the performance of the supported external memory interfaces in Altera devices.
There are three groups of options: Memory Parameters, Memory Topology, and Memory Initialization
Options.
Table 5-4: Memory Parameters
Use the Memory Parameters options group to apply the memory parameters from your memory manufacturer’s data sheet.
Parameter Description
Memory vendor
The vendor of the memory device. Select the memory vendor according to the memory vendor you use. For memory vendors that are not listed in the setting, select JEDEC with the nearest memory parameters and edit the parameter values according to the values of the memory vendor that you use. However, if you select a configuration from the list of memory presets, the default memory vendor for that preset setting is automatically selected.
Memory format
The format of the memory device.
This parameter is automatically set to Discrete Device.
Memory device speed grade
Total interface width
The maximum frequency at which the memory device can run.
The total number of DQ pins of the memory device. Limited to 8 to 24 bits.
DQ/DQS group size
The number of DQ bits per DQS group.
Number of DQS groups
The number of DQS groups is calculated automatically from the Total interface
width and the DQ/DQS group size parameters.
Number of chip selects The number of chip-selects the IP core uses for the current device configuration.
Specify the total number of chip-selects according to the number of memory device.
Number of clocks
The width of the clock bus on the memory interface.
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UniPHY Parameters—Memory Parameters
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Parameter
Row address width
Description
The width of the row address on the memory interface.
Column address width The width of the column address on the memory interface.
Bank-address width
The width of the bank address bus on the memory interface.
Enable DM pins
Specifies whether the DM pins of the memory device are driven by the FPGA.
You can turn off this option to avoid overusing FPGA device pins when using x4 mode memory devices.
When you are using x4 mode memory devices, turn off this option for DDR3
SDRAM.
You must turn on this option if you are using Avalon byte enable.
DQS# Enable
Turn on differential DQS signaling to improve signal integrity and system performance.
This option is available for DDR2 SDRAM only.
Table 5-5: Memory Parameters - Memory Initialization Options (DDR3 SDRAM)
This table lists the memory initialization options for DDR3 SDRAM.
Parameter Description
Read burst type
Specifies accesses within a given burst in sequential or interleaved order.
Specify sequential ordering for use with the Altera memory controller. Specify interleaved ordering only for use with an interleaved-capable custom controller, when the Generate PHY
only parameter is enabled on the PHY Settings tab.
Mode Register 0
DLL precharge power down
Specifies whether the DLL in the memory device is off or on during precharge power-down.
Memory CAS latency setting
The number of clock cycles between the read command and the availability of the first bit of output data at the memory device and also interface frequency. Refer to memory vendor data sheet speed bin table.
Set this parameter according to the target memory speed grade and memory clock frequency.
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UniPHY Parameters—Memory Parameters
5-5
Parameter
Mode Register 1
Mode Register 2
Output drive strength setting
Description
The output driver impedance setting at the memory device.
To obtain the optimum signal integrity performance, select the optimum setting based on the board simulation results.
Memory additive
CAS latency setting
The posted CAS additive latency of the memory device.
Enable this feature to improve command and bus efficiency, and increase system bandwidth. For more information about optimizing the memory controller, refer to related information.
ODT Rtt nominal value
The on-die termination resistance at the memory device.
To obtain the optimum signal integrity performance, select the optimum setting based on the board simulation results.
Auto selfrefresh method
Selfrefresh temperature
Memory write CAS latency setting
Disable or enable auto selfrefresh.
Specifies the selfrefresh temperature as Normal or Extended.
The number of clock cycles from the releasing of the internal write to the latching of the first data in, at the memory device and also interface frequency. Refer to memory vendor data sheet speed bin table and set according to the target memory speed grade and memory clock frequency.
Dynamic ODT (Rtt_
WR) value
The mode of the dynamic ODT feature of the memory device.
This is used for multi-rank configurations. For more guidelines about DDR2 and DDR3 SDRAM board layout, refer to the related information.
To obtain the optimum signal integrity performance, select the optimum setting based on the board simulation results.
Table 5-6: Memory Parameters - Memory Initialization Options (DDR2 SDRAM)
This table lists the memory initialization options for DDR2 SDRAM.
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UniPHY Parameters—Memory Parameters
Parameter
Mode Register 0
Burst length
Read burst type
DLL precharge power down
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Description
Specifies the burst length.
Specifies accesses within a given burst in sequential or interleaved order.
Specify sequential ordering for use with the Altera memory controller. Specify interleaved ordering only for use with an interleaved-capable custom controller, when the Generate PHY
only parameter is enabled on the PHY Settings tab.
Determines whether the DLL in the memory device is in slow exit mode or in fast exit mode during precharge power down.
For more information, refer to memory vendor data sheet.
Memory CAS latency setting
Determines the number of clock cycles between the READ command and the availability of the first bit of output data at the memory device. For more information, refer to memory vendor data sheet speed bin table.
Set this parameter according to the target memory speed grade and memory clock frequency.
Output drive strength setting
Mode Register 1
Memory additive
CAS latency setting
Determines the output driver impedance setting at the memory device.
To obtain the optimum signal integrity performance, select the optimum setting based on the board simulation results.
Determines the posted CAS additive latency of the memory device.
Enable this feature to improve command and bus efficiency, and increase system bandwidth.
Memory on-die termination (ODT) setting
Mode Register 2 SRT Enable
Determines the on-die termination resistance at the memory device.
To obtain the optimum signal integrity performance, select the optimum setting based on the board simulation results.
Determines the selfrefresh temperature (SRT). Select 1x refresh
rate for normal temperature (0-85C)or select 2x refresh rate for high temperature (>85C).
Table 5-7: Memory Parameters - Memory Initialization Options (LPDDR2 SDRAM)
This table lists the memory initialization options for LPDDR2 SDRAM.
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UniPHY Parameters—Memory Timing
5-7
Parameter
Burst Length
Specifies the burst length.
Description
Mode Register 1
Read Burst Type
Specifies accesses within a given burst in sequential or interleaved order.
Specify sequential ordering for use with the Altera memory controller. Specify interleaved ordering only for use with an interleaved-capable custom controller, when the Generate PHY
only parameter is enabled on the PHY Settings tab.
Mode Register 2 Read latency setting Determines the number of clock cycles between the READ command and the availability of the first bit of output data at the memory device.
Set this parameter according to the target memory interface frequency. Refer to memory data sheet and also target memory speed grade.
Mode Register 3 Output drive strength settings
Determines the output driver impedance setting at the memory device.
To obtain the optimum signal integrity performance, select the optimum setting based on the board simulation results.
•
•
•
Related Information
External Memory Interface Handbook Volume 1: Altera Memory Solution Overview and Design
Flow
Provides more information about using Altera devices for external memory interfaces including Altera memory solution and design flow.
External Memory Interface Handbook Volume 2: Design Guidelines
Provides more information about using Altera devices for external memory interfaces including memory selection, board design, implementing memory IP cores, timing, optimization, and debugging.
Functional Description—MAX 10 EMIF
Provides more information about implementing memory IP cores for MAX 10 devices.
Use the Memory Timing options to apply the memory timings from your memory manufacturer’s data sheet.
Table 5-8: Memory Timing
For each parameter, refer to the memory vendor data sheet.
Parameter Applies To Description tIS (base)
DDR2, DDR3,
LPDDR2
Address and control setup to CK clock rise.
Set According To
Memory speed grade
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Parameter tIH (base) tQH
UniPHY Parameters—Memory Timing tDS (base) tDH (base) tDQSQ tQHS tDQSCK tDQSCK (max) tDQSCK Delta
Short tDQSCK Delta
Medium tDQSCK Delta
Long tDQSS tDQSH tQSH tDSH tDSS tINIT
Applies To
DDR2, DDR3,
LPDDR2
DDR2, DDR3,
LPDDR2
DDR2, DDR3,
LPDDR2
DDR2, DDR3,
LPDDR2
DDR2,
LPDDR2
Description
Address and control hold after CK clock rise.
Data setup to clock (DQS) rise.
Data hold after clock (DQS) rise.
DQS, DQS# to DQ skew, per access.
DQ output hold time from DQS, DQS#
(absolute time value).
DDR3
DQ output hold time from DQS, DQS#
(percentage of tCK).
DDR2, DDR3
LPDDR2
LPDDR2
DQS output access time from CK/CK#.
Absolute value of the difference between any two tDQSCK measurements (within a byte lane) within a contiguous sequence of bursts within a 160 ns rolling window.
LPDDR2
Absolute value of the difference between any two tDQSCK measurements (within a byte lane) within a contiguous sequence of bursts within a 1.6 µs rolling window.
LPDDR2
DDR2,
LPDDR2
DDR3
Absolute value of the difference between any two tDQSCK measurements (within a byte lane) within a contiguous sequence of bursts within a 32ms rolling window.
DDR2, DDR3,
LPDDR2
First latching edge of DQS to associated clock edge (percentage of tCK).
DQS Differential High Pulse Width
(percentage of tCK). Specifies the minimum high time of the DQS signal received by the memory.
DDR2, DDR3,
LPDDR2
DQS falling edge hold time from CK
(percentage of tCK).
DDR2, DDR3,
LPDDR2
DQS falling edge to CK setup time (percentage of tCK).
DDR2, DDR3,
LPDDR2
Memory initialization time at power-up.
Memory speed grade
Memory speed grade
Memory speed grade
Memory speed grade
Memory speed grade
Memory speed grade
Memory speed grade
Memory speed grade
Memory speed grade
Memory speed grade
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Set According To
Memory speed grade
Memory speed grade
Memory speed grade
Memory speed grade
Memory speed grade
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Parameter tMRD tMRW tRAS tRCD tRP tREFI tREFIab tRFC tRFCab tWR tWTR tFAW tRRD tRTP
UniPHY Parameters—Board Settings
5-9
Applies To Description
DDR2, DDR3
LPDDR2
Load mode register command period.
DDR2, DDR3,
LPDDR2
DDR2, DDR3,
LPDDR2
DDR2, DDR3,
LPDDR2
Active to precharge time.
Active to read or write time.
Precharge command period.
DDR2, DDR3 Refresh command interval.
LPDDR2
DDR2, DDR3 Auto-refresh command interval.
LPDDR2
Refresh command interval (all banks).
Auto-refresh command interval (all banks).
DDR2, DDR3,
LPDDR2
DDR2, DDR3,
LPDDR2
Write recovery time.
Write to read period.
Calculate the value based on the memory clock frequency.
DDR2, DDR3,
LPDDR2
DDR2, DDR3,
LPDDR2
Four active window time.
RAS to RAS delay time.
Calculate the value based on the memory clock frequency.
DDR2, DDR3,
LPDDR2
Read to precharge time.
Calculate the value based on the memory clock frequency.
Set According To
Memory speed grade
Memory speed grade
Memory speed grade
Memory speed grade
Memory speed grade and tempera‐ ture range
Memory speed grade
Memory device capacity
Memory device capacity
Memory speed grade
Memory speed grade and memory clock frequency
Memory speed grade and page size
Memory speed grade, page size and memory clock frequency
Memory speed grade and memory clock frequency
There are three groups of options: Setup and Hold Derating, Channel Signal Integrity, and Board
Skews.
Table 5-9: Board Settings - Setup and Hold Derating
The slew rate of the output signals affects the setup and hold times of the memory device, and thus the write margin. You can specify the slew rate of the output signals to see their effect on the setup and hold times of both the address and command signals and the DQ signals, or alternatively, you may want to
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specify the setup and hold times directly. You should enter information derived during your PCB development process of prelayout (line) and postlayout (board) simulation.
Parameter Description
Derating method
Derating method. The default settings are based on Altera internal board simulation data. To obtain accurate timing analysis according to the condition of your board, Altera recommends that you perform board simulation and enter the slew rate in the Quartus Prime software to calculate the derated setup and hold time automatically or enter the derated setup and hold time directly.
CK/CK# slew rate (differential) CK/CK# slew rate (differential).
Address/Command slew rate
Address and command slew rate.
DQS/DQS# slew rate (Differen‐ tial)
DQ slew rate
DQS and DQS# slew rate (differential).
DQ slew rate.
tIS
Address/command setup time to CK.
tIH
Address/command hold time from CK.
tDS
Data setup time to DQS.
tDH
Data hold time from DQS.
Table 5-10: Board Settings - Channel Signal Integrity
Channel signal integrity is a measure of the distortion of the eye due to intersymbol interference, crosstalk, or other effects. Typically, when going from a single-rank configuration to a multi-rank configuration there is an increase in the channel loss, because there are multiple stubs causing reflections. Although the
Quartus Prime timing models include some channel uncertainty, you must perform your own channel signal integrity simulations and enter the additional channel uncertainty, relative to the reference eye, into the parameter editor.
Parameter Description
Derating method
Choose between default Altera settings (with specific Altera boards) or manually enter board simulation numbers obtained for your specific board.
Address and command eye reduction (setup)
The reduction in the eye diagram on the setup side (or left side of the eye) due to ISI on the address and command signals compared to a case when there is no ISI. (For single rank designs, ISI can be zero; in multirank designs, ISI is necessary for accurate timing analysis.)
Address and command eye reduction (hold)
The reduction in the eye diagram on the hold side (or right side of the eye) due to ISI on the address and command signals compared to a case when there is no ISI.
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Parameter
Write DQ eye reduction
Read DQ eye reduction
Write Delta DQS arrival time
Read Delta DQS arrival time
UniPHY Parameters—Board Settings
Description
The total reduction in the eye diagram due to ISI on DQ signals compared to a case when there is no ISI. Altera assumes that the ISI reduces the eye width symmetrically on the left and right side of the eye.
The increase in variation on the range of arrival times of DQS compared to a case when there is no ISI. Altera assumes that the ISI causes DQS to further vary symmetrically to the left and to the right.
5-11
Table 5-11: Board Settings - Board Skews
PCB traces can have skews between them that can reduce timing margins. Furthermore, skews between different chip selects can further reduce the timing margin in multiple chip-select topologies. This section allows you to enter parameters to compensate for these variations.
Note: Altera recommends that you use the Board Skew Parameter Tool to help you calculate the board skews. For more information, refer to the related information section.
Parameter
Maximum CK delay to DIMM/device
Description
The delay of the longest CK trace from the FPGA to the memory device is expressed by the following equation:
Maximum DQS delay to DIMM/ device
Where
n
is the number of memory clock and
r
is number rank of device.
The delay of the longest DQS trace from the FPGA to the memory device, whether on a DIMM or the same PCB as the FPGA is expressed by the following equation:
Where
n
is the number of DQS and
r
is number of rank of DIMM/device. For example in dual-rank DIMM implementation, if there are 2 DQS in each rank
DIMM, the maximum DQS delay is expressed by the following equation:
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UniPHY Parameters—Board Settings
Parameter
Minimum delay difference between
CK and DQS
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Description
The minimum skew or smallest positive skew (or largest negative skew) between the CK signal and any DQS signal when arriving at the same DIMM/device over all
DIMMs/devices is expressed by the following equation:
Where
n
is the number of memory clock,
m
is the number of DQS, and
r
is the number of rank of DIMM/device. For example in dual-rank DIMM implementa‐ tion, if there are 2 pairs of memory clock and 4 DQS signals (two for each clock) for each rank DIMM, the minimum delay difference between CK and DQS is expressed by the following equation:
This parameter value affects the write leveling margin for DDR3 interfaces with leveling in multi-rank configurations. This parameter value also applies to nonleveling configurations of any number of ranks with the requirement that DQS must have positive margins in Timequest Report DDR.
For multiple boards, the minimum skew between the CK signal and any DQS signal when arriving at the same DIMM over all DIMMs is expressed by the following equation, if you want to use the same design for several different boards:
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Parameter
Maximum delay difference between
CK and DQS
UniPHY Parameters—Board Settings
5-13
Description
The maximum skew or smallest negative skew (or largest positive skew) between the CK signal and any DQS signal when arriving at the same DIMM/device over all
DIMMs/devices is expressed by the following equation:
Where
n
is the number of memory clock,
m
is the number of DQS, and
r
is the number of rank of DIMM/device. For example in dual-rank DIMM implementa‐ tion, if there are 2 pairs of memory clock and 4 DQS signals (two for each clock) for each rank DIMM, the maximum delay difference between CK and DQS is expressed by the following equation:
This value affects the write Leveling margin for DDR3 interfaces with leveling in multi-rank configurations. This parameter value also applies to non-leveling configurations of any number of ranks with the requirement that DQS must have positive margins in Timequest Report DDR.
For multiple boards, the maximum skew (or largest positive skew) between the CK signal and any DQS signal when arriving at the same DIMM over all DIMMs is expressed by the following equation, if you want to use the same design for several different boards:
Maximum skew within DQS group
The largest skew among DQ and DM signals in a DQS group. This value affects the read capture and write margins for DDR2 and DDR3 SDRAM interfaces in all configurations (single or multiple chip-select, DIMM or component).
For multiple boards, the largest skew between DQ and DM signals in a DQS group is expressed by the following equation:
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UniPHY Parameters—Board Settings
Parameter
Maximum skew between DQS groups
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Description
The largest skew between DQS signals in different DQS groups. This value affects the resynchronization margin in memory interfaces without leveling such as DDR2
SDRAM and discrete-device DDR3 SDRAM in both single- or multiple chip-select configurations.
For multiple boards, the largest skew between DQS signals in different DQS groups is expressed by the following equation, if you want to use the same design for several different boards:
Average delay difference between
DQ and DQS
The average delay difference between each DQ signal and the DQS signal, calculated by averaging the longest and smallest DQ signal delay values minus the delay of DQS. The average delay difference between DQ and DQS is expressed by the following equation: where
n
is the number of DQS groups. For multi-rank or multiple CS configura‐ tion, the equation is:
Maximum skew within address and command bus
The largest skew between the address and command signals for a single board is expressed by the following equation:
For multiple boards, the largest skew between the address and command signals is expressed by the following equation, if you want to use the same design for several different boards:
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Parameter
Average delay difference between address and command and CK
UniPHY Parameters—Controller Settings
Description
A value equal to the average of the longest and smallest address and command signal delay values, minus the delay of the CK signal. The value can be positive or negative. Positive values represent address and command signals that are longer than CK signals; negative values represent address and command signals that are shorter than CK signals. The average delay difference between address and command and CK is expressed by the following equation:
5-15
where
n
is the number of memory clocks. For multi-rank or multiple CS configura‐ tion, the equation is:
The Quartus Prime software uses this skew to optimize the delay of the address and command signals to have appropriate setup and hold margins for DDR2 and DDR3
SDRAM interfaces. You should derive this value through board simulation.
For multiple boards, the average delay difference between address and command and CK is expressed by the following equation, if you want to use the same design for several different boards:
•
•
Related Information
Analizing Timing of Memory IP chapter, External Memory Interface Handbook
Provides more information about derating method and measuring eye reduction.
Board Skew Parameter Tool
There are four groups of options: Avalon Interface, Low Power Mode, Efficiency, and Configuration,
Status and Error Handling.
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Table 5-12: Controller Settings - Avalon Interface
Parameter
Generate power-of-2 data bus widths for Qsys or SOPC
Builder
Descriptions
Rounds down the Avalon-MM side data bus to the nearest power of 2.
You must enable this option for Qsys systems.
If this option is enabled, the Avalon data buses are truncated to 256 bits wide. One Avalon read-write transaction of 256 bit width maps to four memory beat transactions, each of 72 bits (8 MSB bits are zero, while
64 LSB bits carry useful content). The four memory beats may comprise an entire burst length-of-4 transaction, or part of a burst-length-of-8 transaction.
Generate SOPC Builder compatible resets
This option is not required when using the MegaWizard Plug-in
Manager or Qsys.
Maximum Avalon-MM burst length
Specifies the maximum burst length on the Avalon-MM bus. Affects the
AVL_SIZE_WIDTH
parameter.
Enable Avalon-MM byte-enable signal
When you turn on this option, the controller adds the byte enable signal (avl_be) for the Avalon-MM bus to control the data mask (mem_ dm) pins going to the memory interface. You must also turn on Enable
DM pins if you are turning on this option.
When you turn off this option, the byte enable signal (avl_be) is not enabled for the Avalon-MM bus, and by default all bytes are enabled.
However, if you turn on Enable DM pins with this option turned off, all write words are written.
Avalon interface address width The address width on the Avalon-MM interface.
Avalon interface data width
The data width on the Avalon-MM interface.
Table 5-13: Controller Settings - Low Power Mode
Parameter
Enable Self-Refresh Controls
Description
Enables the self-refresh signals on the controller top-level design. These controls allow you to control when the memory is placed into selfrefresh mode.
Enable Deep Power-Down
Controls
Enables the Deep-Powerdown signals on the controller top level. These controls allow you to control when the memory is placed in Deep-
Powerdown mode.
This option is available only for LPDDR2 SDRAM.
Enable Auto Power-Down
Allows the controller to automatically place the memory into powerdown mode after a specified number of idle cycles. Specifies the number of idle cycles after which the controller powers down the memory in the auto-power down cycles parameter.
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Parameter
Auto Power-Down Cycles
UniPHY Parameters—Controller Settings
Description
The number of idle controller clock cycles after which the controller automatically powers down the memory. The legal range is from 1 to
65,535 controller clock cycles.
5-17
Table 5-14: Controller Settings - Efficiency
Parameter
Enable User Auto-Refresh
Controls
Description
Enables the user auto-refresh control signals on the controller top level.
These controller signals allow you to control when the controller issues memory autorefresh commands.
Enable Auto-Precharge Control Enables the autoprecharge control on the controller top level. Asserting the autoprecharge control signal while requesting a read or write burst allows you to specify whether the controller should close (autopre‐ charge) the currently open page at the end of the read or write burst.
Local-to-Memory Address
Mapping
Allows you to control the mapping between the address bits on the
Avalon-MM interface and the chip, row, bank, and column bits on the memory:
• Chip-Row-Bank-Col—improves efficiency with sequential traffic.
• Chip-Bank-Row-Col—improves efficiency with random traffic.
• Row-Chip-Bank-Col—improves efficiency with multiple chip select and sequential traffic.
Command Queue Look-Ahead
Depth
Selects a look-ahead depth value to control how many read or writes requests the look-ahead bank management logic examines. Larger numbers are likely to increase the efficiency of the bank management, but at the cost of higher resource usage. Smaller values may be less efficient, but also use fewer resources. The valid range is from 1 to 16.
Enable Reordering
Allows the controller to perform command and data reordering that reduces bus turnaround time and row/bank switching time to improve controller efficiency.
Starvation limit for each command
Specifies the number of commands that can be served before a waiting command is served. The valid range is from 1 to 63.
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Table 5-15: Controller Settings - Configuration, Status and Error Handling
Parameter
Enable Configuration and
Status Register Interface
Description
Enables run-time configuration and status interface for the memory controller. This option adds an additional Avalon-MM slave port to the memory controller top level, which you can use to change or read out the memory timing parameters, memory address sizes, mode register settings and controller status. If Error Detection and Correction Logic is enabled, the same slave port also allows you to control and retrieve the status of this logic.
CSR port host interface
Specifies the type of connection to the CSR port. The port can be exported, internally connected to a JTAG Avalon Master, or both:
• Internal (JTAG)—connects the CSR port to a JTAG Avalon Master.
• Avalon-MM Slave —exports the CSR port.
• Shared—exports and connects the CSR port to a JTAG Avalon
Master.
Enable Error Detection and
Correction Logic
Enables ECC for single-bit error correction and double-bit error detection. MAX 10 devices supports ECC only for 16 bits + 8 bits ECC memory configuration.
Enable Auto Error Correction
Allows the controller to perform auto correction when a single-bit error is detected by the ECC logic.
To turn this on, you must first turn on Enable Error Detection and
Correction Logic.
There is one option group supported for MAX 10 devices: Simulation Options.
Table 5-16: Diagnostics - Simulation Options
Parameter Description
Enable verbose memory model output Turn on this option to display more detailed information about each memory access during simulation.
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If an IP core version is not listed, the user guide for the previous IP core version applies.
IP Core Version User Guide
16.0
15.1
15.0
14.1
MAX 10 Exteral Memory Interface User Guide
MAX 10 Exteral Memory Interface User Guide
MAX 10 Exteral Memory Interface User Guide
MAX 10 Exteral Memory Interface User Guide
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2016 Intel Corporation. All rights reserved. Intel, the Intel logo, Altera, Arria, Cyclone, Enpirion, MAX, Megacore, NIOS, Quartus and Stratix words and logos are trademarks of Intel Corporation in the US and/or other countries. Other marks and brands may be claimed as the property of others. Intel warrants performance of its FPGA and semiconductor products to current specifications in accordance with Intel's standard warranty, but reserves the right to make changes to any products and services at any time without notice. Intel assumes no responsibility or liability arising out of the application or use of any information, product, or service described herein except as expressly agreed to in writing by Intel. Intel customers are advised to obtain the latest version of device specifications before relying on any published information and before placing orders for products or services.
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Date
October 2016
May 2016
November 2015
May 2015
Version
2016.10.28
2016.05.02
2015.11.02
2015.05.11
Changes
• Updated Memory Standards Supported by the Soft
Memory Controller for MAX 10 devices table.
• Updated UniPHY IP core parameter settings for
LPDDR2, DDR2 and DDR3.
• Updated Supported Maximum External Memory
Interface Width in MAX 10 Device Packages table.
• Added MAX 10 External Memory Interface User
Guide Archives table.
• Updated DDR2, DDR3 and LPDDR2 can use only user I/O pins from banks 5 and 6 of MAX 10 devices to generate address and control or command signals..
• Added links to MAX 10 DDR3 UniPHY IP core reference design.
• Added topic that lists the maximum external memory interface widths supported for different
MAX 10 device packages.
• Removed the topics about the IP catalog and parameter editor, generating IP cores, and the files generated by the IP core, and added a link to
Introduction to Altera IP Cores
.
• Changed instances of
Quartus II
to
Quartus Prime
.
Added on board termination recommendation for
DDR3 component.
B
©
2016 Intel Corporation. All rights reserved. Intel, the Intel logo, Altera, Arria, Cyclone, Enpirion, MAX, Megacore, NIOS, Quartus and Stratix words and logos are trademarks of Intel Corporation in the US and/or other countries. Other marks and brands may be claimed as the property of others. Intel warrants performance of its FPGA and semiconductor products to current specifications in accordance with Intel's standard warranty, but reserves the right to make changes to any products and services at any time without notice. Intel assumes no responsibility or liability arising out of the application or use of any information, product, or service described herein except as expressly agreed to in writing by Intel. Intel customers are advised to obtain the latest version of device specifications before relying on any published information and before placing orders for products or services.
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Document Revision History for MAX 10 External Memory Interface User Guide
Date
May 2015
Version
2015.05.04
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Changes
• Updated the footnote in the topic about external memoy interface support and performance to specify that the default maximum frequency for
LPDDR2 is 167 MHz.
• Removed the F672 package from the 10M25 device.
• Removed the note about contacting Altera for
DDR3, DDR3L, DDR2, and LPDDR2 external memory interface support. The Quartus Prime software supports these external memory interfaces from version 15.0.
• Added a topic about the PHYCLK network.
• Moved information about recommended LPDDR2 termination scheme into a new topic under
LPDDR2 design considerations section. The information was previously in the topic about recommended DDR2/DDR3 termination schemes.
• Updated the guidelines about board design require‐ ment to improve clarity.
• Updated and added related information links to relevant information.
• Added a topic about the low power feature available from version 15.0 of the Quartus Prime software.
• Updated the topic about the phase detector to add a figure showing the VT tracking system overview.
December 2014 2014.12.15
• Changed Altera MAX 10 EMIF IP core to UniPHY
IP core.
• Removed reference to DIMM in a footnote under the table that lists the termination recommenda‐ tions for DDR2 component. The UniPHY IP core for MAX 10 does not support DIMM.
• Added a list of the MAX 10 memory controller features.
• Added "Preliminary" tag to the table that lists the I/
Os unavailable in certain MAX 10 packages while implementing DDR3 or LPDDR2 external memory interfaces.
• Updated the board design requirement with additional guidelines.
• Added information for the MAX 10 external memory interface UniPHY IP core. This addition includes the chapters about external memory interface implementation and IP core references.
• Edited texts and added related information links to improve clarity.
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Document Revision History for MAX 10 External Memory Interface User Guide
Version
2014.09.22
Initial release.
Changes
B-3
Additional Information for MAX 10 External Memory Interface User Guide
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TOC-2
Contents
MAX 10 Analog to Digital Converter Overview................................................ 1-1
MAX 10 ADC Architecture and Features........................................................... 2-1
Altera Modular ADC and Altera Modular Dual ADC IP Cores Architecture......................2-17
MAX 10 ADC Design Considerations................................................................ 3-1
Guidelines: Board Design for Power Supply Pin and ADC Ground (
)....................................3-1
MAX 10 ADC Implementation Guides...............................................................4-1
Parameters Settings for Generating Altera Modular ADC or Altera Modular Dual ADC IP
Altera Corporation
TOC-3
Altera Modular ADC and Altera Modular Dual ADC IP Cores References..... 5-1
Altera Modular ADC IP Core Channel Name to MAX 10 Device Pin Name Mapping........5-6
Altera Modular Dual ADC IP Core Channel Name to MAX 10 Device Pin Name
Command Interface of Altera Modular ADC and Altera Modular Dual ADC.................... 5-13
Response Interface of Altera Modular ADC and Altera Modular Dual ADC.......................5-14
Threshold Interface of Altera Modular ADC and Altera Modular Dual ADC......................5-15
CSR Interface of Altera Modular ADC and Altera Modular Dual ADC................................5-16
IRQ Interface of Altera Modular ADC and Altera Modular Dual ADC................................5-16
Peripheral Clock Interface of Altera Modular ADC and Altera Modular Dual ADC..........5-17
Peripheral Reset Interface of Altera Modular ADC and Altera Modular Dual ADC...........5-17
ADC PLL Clock Interface of Altera Modular ADC and Altera Modular Dual ADC.......... 5-17
ADC PLL Locked Interface of Altera Modular ADC and Altera Modular Dual ADC........5-18
MAX 10 Analog to Digital Converter User Guide Archives..............................A-1
Document Revision History for MAX 10 Analog to Digital Converter User
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MAX
®
10 devices feature up to two analog-to-digital converters (ADC). The ADCs provide the MAX 10 devices with built-in capability for on-die temperature monitoring and external analog signal conversion.
The ADC solution consists of hard IP blocks in the MAX 10 device periphery and soft logic through the
Altera Modular ADC IP core.
The ADC solution provides you with built-in capability to translate analog quantities to digital data for information processing, computing, data transmission, and control systems. The basic function is to provide a 12 bit digital representation of the analog signal being observed.
The ADC solution works in two modes:
• Normal mode—monitors single-ended external inputs with a cumulative sampling rate of up to 1 million samples per second (MSPS):
• Single ADC devices—up to 17 single-ended external inputs (one dedicated analog and 16 dual function input pins)
• Dual ADC devices—up to 18 single-ended external inputs (one dedicated analog and eight dual function input pins in each ADC block)
• Temperature sensing mode—monitors external temperature data input with a sampling rate of up to 50 kilosamples per second. In dual ADC devices, only the first ADC block supports this mode.
•
•
•
•
•
•
•
•
Related Information
MAX 10 ADC Architecture and Features
on page 2-1
MAX 10 ADC Design Considerations
MAX 10 ADC Implementation Guides
on page 4-1
Altera Modular ADC and Altera Modular Dual ADC IP Cores References
MAX 10 Getting Started
MAX 10 Online Training
MAX 10 How-to Videos
How to Create ADC Design in MAX 10 Device Using Qsys Tool
Provides video instruction that demonstrates how to create the ADC design in MAX 10 devices using the Qsys system integration tool within the Quartus to view the measured analog signal.
®
Prime software and how to use the ADC toolkit
1
©
2016 Intel Corporation. All rights reserved. Intel, the Intel logo, Altera, Arria, Cyclone, Enpirion, MAX, Megacore, NIOS, Quartus and Stratix words and logos are trademarks of Intel Corporation in the US and/or other countries. Other marks and brands may be claimed as the property of others. Intel warrants performance of its FPGA and semiconductor products to current specifications in accordance with Intel's standard warranty, but reserves the right to make changes to any products and services at any time without notice. Intel assumes no responsibility or liability arising out of the application or use of any information, product, or service described herein except as expressly agreed to in writing by Intel. Intel customers are advised to obtain the latest version of device specifications before relying on any published information and before placing orders for products or services.
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•
•
ADC Block Counts in MAX 10 Devices
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How to Create Simultaneous Measurement with MAX 10 ADC, Part 1
Provides the first part of video instruction series that explains the differences between the MAX 10
Altera Modular ADC and Altera Modular Dual ADC IP cores. The video also demonstrates how to create a simple simultaneous ADC measurement and how to place signal taps to measure the digital code output for analog signal.
How to Create Simultaneous Measurement with MAX 10 ADC, Part 2
Provides the second part of video instruction series that explains the differences between the MAX 10
Altera Modular ADC and Altera Modular Dual ADC IP cores. The video also demonstrates how to create a simple simultaneous ADC measurement and how to place signal taps to measure the digital code output for analog signal.
The ADC block is available in single and dual supply MAX 10 devices.
Table 1-1: Number of ADC Blocks in MAX 10 Devices and Packages
For more information about the device part numbers that feature ADC blocks, refer to the device overview.
Package
Power
Supply
10M04 10M08 10M16
Device
10M25 10M40 10M50
M153
U169
U324
F256
E144
F484
F672
Single
Single
Dual
Dual
Single
Dual
Dual
1
1
1
1
1
—
—
1
1
1
1
1
1
—
—
1
1
1
1
1
—
—
—
—
2
1
2
—
—
—
—
2
1
2
2
—
—
—
2
1
2
2
Related Information
MAX 10 FPGA Device Overview
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MAX 10 Analog to Digital Converter Overview
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ADC Channel Counts in MAX 10 Devices
1-3
Different MAX 10 devices support different number of ADC channels.
Table 1-2: ADC Channel Counts in MAX 10 Devices
• Devices with two ADC blocks have two dedicated analog inputs and each ADC block has 8 dual function pins. You can use the dual function pins in an ADC block as general purpose I/O (GPIO) pins if you do not use the ADC.
• For more information about the device part numbers that feature ADC blocks, refer to the device overview.
Package
M153
U169
U324
F256
E144
F484
F672
Pin Type
Dual function
Dedicated
Dual function
Dedicated
Dual function
Dedicated
Dual function
Dedicated
Dual function
Dedicated
Dual function
Dedicated
Dual function
Dedicated
10M04
1
8
1
8
1
16
1
16
1
8
—
—
—
—
10M08
1
8
1
8
1
16
1
16
1
8
1
16
—
—
ADC Channel Counts Per Device
10M16
—
—
10M25
—
—
10M40
—
—
1
8
1
16
1
16
1
8
1
16
—
—
—
—
—
—
2
16
1
8
2
16
—
—
—
—
—
—
2
16
1
8
2
16
2
16
10M50
—
—
—
—
—
—
2
16
1
8
2
16
2
16
•
•
Related Information
MAX 10 FPGA Device Overview
MAX 10 ADC Vertical Migration Support
MAX 10 Analog to Digital Converter Overview
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1-4
MAX 10 ADC Vertical Migration Support
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Figure 1-1: ADC Vertical Migration Across MAX 10 Devices
The arrows indicate the ADC migration paths. The devices included in each vertical migration path are shaded.
Device
M153 U169 U324
Package
F256 E144 F484
10M04
10M08
10M16
10M25
10M40
10M50
Dual ADC Device:
Each ADC (ADC1 and ADC2) supports 1 dedicated analog input pin and 8 dual function pins.
Single ADC Device:
Single ADC that supports 1 dedicated analog input pin and 16 dual function pins.
Single ADC Device:
Single ADC that supports 1 dedicated analog input pin and 8 dual function pins.
F672
Table 1-3: Pin Migration Conditions for ADC Migration
Source
Single ADC device
Dual ADC device
Single ADC device
Dual ADC device
Target
Single ADC device
Dual ADC device
Dual ADC device
Single ADC device
Migratable Pins
You can migrate all ADC input pins
• One dedicated analog input pin.
• Eight dual function pins from the ADC1 block of the source device to the ADC1 block of the target device.
Related Information
ADC Channel Counts in MAX 10 Devices
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MAX 10 Single or Dual Supply Devices
1-5
MAX 10 devices are available in single or dual supply packages.
• For devices with single power supply:
• Use on chip regulator to power up the digital supply.
• Use V
CCA
to power up the ADC analog.
• For dual power supply devices, you must provide external power supplies of 1.2 V and 2.5 V to power up the ADC.
To choose the correct device, refer to the MAX 10 device overview.
For more information about the ADC parameter, refer to the device datasheet.
•
•
Related Information
MAX 10 Device Datasheet
MAX 10 FPGA Device Overview
The ADC in dual supply MAX 10 devices can measure from 0 V to 2.5 V. In single supply MAX 10 devices, it can measure up to 3.0 V or 3.3 V, depending on your power supply voltage.
• In prescaler mode, the analog input can measure up to 3.0 V in dual supply MAX 10 devices and up to
3.6 V in single supply MAX 10 devices.
• The analog input scale has full scale code from
000h
to
FFFh
. However, the measurement can only display up to
full scale – 1 LSB
.
• For the 12 bits corresponding value calculation, use unipolar straight binary coding scheme.
MAX 10 Analog to Digital Converter Overview
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MAX 10 ADC Conversion
Figure 1-2: ADC Measurement Display for 2.5 V
Output Code
FFF
FFE
FFD
Full Scale
Transition
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Full scale input = 2.5 V
Resolution = 2
12
= 4096
1 LSB = 2.5V / 4096 =
610.35µ V
003
002
001
000
610.35µ 1220.70µ 2.4993896
Input Voltage (V)
The MAX 10 ADC is a 1 MHz successive approximation register (SAR) ADC. If you set up the PLL and
Altera Modular ADC IP core correctly, the ADC operates at up to 1 MHz during normal sampling and 50 kHz during temperature sensing.
Note: The analog value represented by the all-ones code is not full scale but
full scale – 1 LSB
. This is a common convention in data conversion notation and applies to ADCs.
•
•
•
Related Information
on page 4-2
Altera Modular ADC Parameters Settings
on page 5-2
Altera Modular Dual ADC Parameters Settings
on page 5-8
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In MAX 10 devices, the ADC is a 12-bit SAR ADC that provides the following features:
• Sampling rate of up to 1 MSPS
• Up to 18 channels for analog measurement: 16 dual function channels and two dedicated analog input channels in dual ADC devices
• Single-ended measurement capability
• Simultaneous measurement capability at the dedicated analog input pins for dual ADC devices
• Soft logic sequencer
• On-chip temperature sensor with sampling rate of 50 kilosamples per second
• Internal or external voltage references usage. The source of the internal voltage reference is the ADC analog supply; the ADC conversion result is ratiometric.
•
•
Related Information
MAX 10 Analog to Digital Converter Overview
on page 1-1
MAX 10 Analog to Digital Converter User Guide Archives
on page 6-1
Provides a list of user guides for previous versions of the Altera Modular ADC and Altera Modular
Dual ADC IP cores.
The MAX 10 ADC is a successive approximation register (SAR) ADC that converts one analog sample in one clock cycle.
Each ADC block supports one dedicated analog input pin and up to 16 channels of dual function pins.
You can use the built-in temperature sensing diode (TSD) to perform on-chip temperature measurement.
2
©
2016 Intel Corporation. All rights reserved. Intel, the Intel logo, Altera, Arria, Cyclone, Enpirion, MAX, Megacore, NIOS, Quartus and Stratix words and logos are trademarks of Intel Corporation in the US and/or other countries. Other marks and brands may be claimed as the property of others. Intel warrants performance of its FPGA and semiconductor products to current specifications in accordance with Intel's standard warranty, but reserves the right to make changes to any products and services at any time without notice. Intel assumes no responsibility or liability arising out of the application or use of any information, product, or service described herein except as expressly agreed to in writing by Intel. Intel customers are advised to obtain the latest version of device specifications before relying on any published information and before placing orders for products or services.
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ADC Block Locations
Figure 2-1: ADC Hard IP Block in MAX 10 Devices
Note: In dual ADC devices, the temperature sensor is available only in ADC1.
PLL Clock In
Dedicated
Analog Input
ADC Hard IP Block
Sequencer [4:0]
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DOUT [11:0]
ADC Analog Input
(Dual Function) [16:1]
Mux
Sampling and Hold
12 bit 1 Mbps ADC
Control/Status
Temperature Sensor
ADC V
REF
Internal V
REF
Altera Modular ADC IP Core
Related Information
on page 2-19
Provides mode information about the sequencer conversion modes.
The ADC blocks are located at the top left corner of the MAX 10 device periphery.
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MAX 10 ADC Architecture and Features
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Figure 2-2: ADC Block Location in MAX 10 04 and 08 Devices
ADC1
8 7
1A
1B
2
6
5
ADC Block Locations
2-3
3 4
I/O Bank
ADC Block
MAX 10 ADC Architecture and Features
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ADC Block Locations
Figure 2-3: ADC Block Location in MAX 10 16 Devices
ADC1
8 7
1A
1B
2
3 4
6
5
OCT
I/O Bank
ADC Block
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Figure 2-4: ADC Block Location in MAX 10 25, 40, and 50 Devices
Package E144 of these devices have only one ADC block.
8 7
ADC1
ADC2
1A
1B
Single or Dual ADC Devices
2-5
6
2
5
3 4
OCT
I/O Bank
ADC Block
MAX 10 devices are available with single or dual ADC blocks.
For devices with one ADC block, you can use up to 17 ADC channels:
• These channels include one dedicated analog input and up to 16 dual function pins.
• You can use the dual function pins as GPIO pins when you do not use the ADC.
Note: MAX 10 devices in the E144 package have only 8 dual function ADC pins.
For devices with two ADC blocks, you can use up to 18 ADC channels:
• For dual ADC devices, each ADC block can support one dedicated analog input pin and up to 8 dual function pins.
• If you use both ADC blocks in dual ADC devices, you can use up to two dedicated analog input pins and 16 dual function pins.
• For simultaneous measurement, you can use only dedicated analog input pins in both ADC blocks because the package routing of both dedicated analog pins are matched. For dual function pins, the routing latency between two ADC blocks may cause data mismatch in simultaneous measurement.
• For simultaneous measurement, use the Altera Modular Dual ADC IP core.
To choose the correct device, refer to the MAX 10 device overview.
MAX 10 ADC Architecture and Features
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ADC Analog Input Pins
•
•
Related Information
MAX 10 FPGA Device Overview
ADC Channel Counts in MAX 10 Devices
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The analog input pins support single-ended and unipolar measurements.
The ADC block in MAX 10 devices contains two types of ADC analog input pins:
• Dedicated ADC analog input pin—pins with dedicated routing that ensures both dedicated analog input pins in a dual ADC device has the same trace length.
• Dual function ADC analog input pin—pins that share the pad with GPIO pins.
If you use bank 1A for ADC, you cannot use the bank for GPIO.
Each analog input pin in the ADC block is protected by electrostatic discharge (ESD) cell.
The ADC block in MAX 10 devices contains a prescaler function.
The prescaler function divides the analog input voltage by half. Using this function, you can measure analog input greater than 2.5 V. In prescaler mode, the analog input can handle up to 3 V input for the dual supply MAX 10 devices and 3.6 V for the single supply MAX 10 devices.
Figure 2-5: ADC Prescaler Block Diagram
3.6 kΩ
ADC
Analog
Input
3.6 kΩ
Mux
REFGND
The prescaler feature is available on these channels in each ADC block:
• Single ADC device—channels 8 and 16 (if available)
• Dual ADC device:
• Using Altera Modular ADC IP core—channel 8 of first or second ADC
• Using Altera Modular Dual ADC IP core—channel 8 of ADC1 and channel 17 of ADC2
The ADC block uses the device PLL as the clock source. The ADC clock path is a dedicated clock path.
You cannot change this clock path.
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ADC Voltage Reference
2-7
Depending on the device package, the MAX 10 devices support one or two PLLs—PLL1 only, or PLL1 and
PLL3.
For devices that support two PLLs, you can select which PLL to connect to the ADC. You can configure the ADC blocks with one of the following schemes:
• Both ADC blocks share the same clock source for synchronization.
• Both ADC blocks use different PLLs for redundancy.
If each ADC block in your design uses its own PLL, the Quartus
® clock source scheme based on the PLL clock input source:
Prime Fitter automatically selects the
• If each PLL that clocks its respective ADC block uses different PLL input clock source, the Quartus
Prime Fitter follows your design (two PLLs).
• If both PLLs that clock their respective ADC block uses the same PLL input clock source, the Quartus
Prime Fitter merges both PLLs as one.
In dual ADC mode, both ADC instance must share the same ADC clock setting.
Related Information
PLL Locations, MAX 10 Clocking and PLL User Guide
Provides more information about the availability of PLL3 in different MAX 10 devices and packages.
Each ADC block in MAX 10 devices can independently use an internal or external voltage reference. In dual ADC devices, you can assign an internal voltage reference to one ADC block and an external voltage reference to the other ADC block.
There is only one external
VREF
pin in each MAX 10 device. Therefore, if you want to assign external voltage reference for both ADC blocks in dual ADC devices, share the same external voltage reference for both ADC blocks.
Altera recommends that you use a clean external voltage reference with a maximum resistance of 100 Ω for the ADC blocks. If the ADC block uses an internal voltage reference, the ADC block is tied to its analog voltage and the conversion result is ratiometric.
The ADC block in MAX 10 devices has built-in TSD. You can use the built-in TSD to monitor the internal temperature of the MAX 10 device.
MAX 10 ADC Architecture and Features
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ADC Temperature Sensing Diode
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• While using the temperature sensing mode, the ADC sampling rate is 50 kilosamples per second during temperature measurement.
• After the temperature measurement completes, if the next conversion in the sequence is normal sampling mode, the Altera Modular ADC IP core automatically switches the ADC back to normal sampling mode. The maximum cumulative sampling rate in normal sampling mode is 1 MSPS.
• When the ADC switches from normal sensing mode to temperature sensing mode, and vice versa, calibration is run automatically for the changed clock frequency. The calibration incurs at least six clock calibration cycles from the new sampling rate.
• The ADC TSD measurement uses a 64-samples running average method. For example:
• The first measured temperature value is the average of samples 1 to 64.
• The second measured temperature value is the average of samples 2 to 65.
• The third measured temperature value is the average of samples 3 to 66.
• The subsequent temperature measurements follow the same method.
For dual ADC devices, the temperature sensor is available in ADC1 only.
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Temperature Measurement Code Conversion
2-9
Use the temperature measurement code conversion table to convert the values measured by the ADC TSD to actual temperature.
Table 2-1: Temperature Code Conversion Table
Temp (C) Code
-24 3771
-23 3770
-22 3768
-21 3766
-20 3765
-19 3764
-18 3762
-17 3759
-16 3756
-15 3754
-14 3752
-13 3751
-12 3750
-32 3785
-31 3782
-30 3781
-29 3780
-28 3779
-27 3777
-26 3775
-25 3773
-40 3798
-39 3796
-38 3795
-37 3793
-36 3792
-35 3790
-34 3788
-33 3786
Temp (C) Code
10 3707
11 3704
12 3703
13 3702
14 3700
15 3699
16 3698
17 3697
18 3696
19 3695
20 3688
21 3684
22 3682
2 3721
3 3720
4 3719
5 3717
6 3715
7 3713
8 3711
9 3709
-6 3738
-5 3736
-4 3733
-3 3732
-2 3731
-1 3730
0 3727
1 3725
Temp (C) Code
44 3638
45 3636
46 3634
47 3632
48 3630
49 3628
50 3625
51 3622
52 3619
53 3616
54 3613
55 3610
56 3607
36 3654
37 3651
38 3648
39 3645
40 3643
41 3642
42 3641
43 3640
28 3670
29 3667
30 3666
31 3664
32 3662
33 3660
34 3658
35 3656
Temp (C) Code
78 3552
79 3551
80 3550
81 3549
82 3548
83 3547
84 3546
85 3542
86 3538
87 3534
88 3530
89 3526
90 3525
70 3576
71 3573
72 3570
73 3567
74 3564
75 3561
76 3558
77 3555
62 3593
63 3592
64 3591
65 3590
66 3589
67 3585
68 3582
69 3579
Temp (C)
112 3471
113 3468
114 3465
115 3461
116 3460
117 3459
118 3456
119 3451
120 3450
121 3449
122 3445
123 3440
124 3432
96 3510
97 3507
98 3504
99 3501
100 3500
101 3498
102 3496
103 3494
104 3492
105 3490
106 3489
107 3486
108 3483
109 3480
110 3477
111 3474
Code
MAX 10 ADC Architecture and Features
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2-10
ADC Sequencer
Temp (C) Code
-11 3748
-10 3746
-9 3744
-8 3742
-7 3740
Temp (C) Code
23 3680
24 3678
25 3677
26 3676
27 3673
Temp (C) Code
57 3604
58 3601
59 3598
60 3595
61 3594
Temp (C) Code
91 3524
92 3522
93 3519
94 3516
95 3513
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Temp (C)
125 3431
— —
— —
— —
— —
Code
The Altera Modular ADC and Altera Modular Dual ADC IP cores implement the sequencer. Use the
Altera Modular ADC or Altera Modular Dual ADC parameter editor to define the ADC channel acquisition sequence and generate the HDL code.
The sequencer can support sequences of up to 64 ADC measurement slots. While configuring the Altera
Modular ADC or Altera Modular Dual ADC IP core, you can select which channel, including the TSD channel, to sample in each sequencer slot. During runtime, you cannot change the channel sequence but you can configure the sequencer conversion mode using the Nios
®
II HAL driver API.
You can specify up to 64 slots and assign the channel for each slot. You can repeat the same channel number several times if required.
Related Information
Guidelines: ADC Sequencer in Altera Modular Dual ADC IP Core
on page 2-10
Follow these sequencer guidelines if you use dual ADC blocks with the Altera Modular Dual ADC IP core.
• The conversion sequence length of both ADC blocks must be the same.
• You can configure independent patterns for the conversion sequence of each ADC blocks.
• You can set a sequencer slot in ADC2 to NULL. If you set the slot to NULL, ADC2 will perform a dummy conversion for the slot with output of "0". The NULL option is available only for ADC2.
• The temperature sensor is available only in ADC1. If you configure a sequencer slot in ADC1 for temperature sensing, you must set the same sequencer slot number in ADC2 to NULL.
Related Information
on page 2-10
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Figure 2-6: MAX 10 ADC Timing Diagram
ADC Timing
2-11
• This figure shows the timing diagram for the command and response interface of the Altera Modular
ADC control core.
• The timing diagram shows the latency of the first valid response data, and the latency between the first acknowledgment of the first command request and the back-to-back response data.
clock reset_n command_valid commandd_channel[4:0] command_starofpacket command_endofpacket command_ready response_valid response_channel[4:0] response_data[11:0] response_startofpacket response_endofpacket
0x00 0x10
0x00
0x000
0x01
0x10
0x008
0x02
0x00
0x000
0x01
0x001
3 ADC soft IP clock + 2 μs
3 ADC soft IP clock + 3 μs
1 μs
The timing diagram shows an example where:
• The conversion sequence is channel 16 → channel 1 → channel 2
• The response data for channel 16 is 8
• The response data for channel 1 is 1
You can use the Altera Modular ADC and Altera Modular Dual ADC IP cores to generate soft IP controllers for the ADC hard IP blocks in MAX 10 devices.
There are two ADC IP cores:
• Altera Modular ADC IP core—each instance can control one ADC hard IP block. In a dual ADC device, you can instantiate one Altera Modular ADC IP core instance for each ADC block. However, both instances will be asynchronous to each other.
• Altera Modular Dual ADC IP core—you can control both ADC hard IP block with a single IP instance.
• For the analog input pins (ANAIN1 and ANAIN2) in both ADC hard IP blocks, the measurement is synchronous.
• For the dual function input pins, there are some measurement timing differences caused by the routing latency.
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Altera Modular ADC IP Core Configuration Variants
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You can perform the following functions with the Altera Modular ADC or Altera Modular Dual ADC IP core parameter editor:
• Configure the ADC clock, sampling rate, and reference voltage.
• Select which analog input channels that the ADC block samples.
• Configure the threshold value to trigger a threshold violation notification.
• Set up a conversion sequence to determine which channel requires more frequent attention.
•
•
•
•
Related Information
Altera Modular ADC and Altera Modular Dual ADC IP Cores References
Introduction to Altera IP Cores
Provides general information about all Altera FPGA IP cores, including parameterizing, generating, upgrading, and simulating IP cores.
Creating Version-Independent IP and Qsys Simulation Scripts
Create simulation scripts that do not require manual updates for software or IP version upgrades.
Project Management Best Practices
Guidelines for efficient management and portability of your project and IP files.
The Altera Modular ADC IP core provides four configuration variants that target different ADC use cases.
These configuration variants support usages from basic system monitoring to high performance ADC data streaming.
Configuration 1: Standard Sequencer with Avalon-MM Sample Storage
In this configuration variant, you can use the standard sequencer micro core with internal on-chip RAM for storing ADC samples.
Configuration 2: Standard Sequencer with Avalon-MM Sample Storage and Threshold Violation
on page 2-13
In this configuration variant, you can use the standard sequencer micro core with internal on-chip RAM for storing ADC samples with the additional capability of detecting threshold violation.
Configuration 3: Standard Sequencer with External Sample Storage
In this configuration variant, you can use the standard sequencer micro core and store the ADC samples in external storage.
Configuration 4: ADC Control Core Only
In this configuration variant, the Altera Modular ADC generates only the ADC control core.
Related Information
Altera Modular ADC and Altera Modular Dual ADC IP Cores References
In this configuration variant, you can use the standard sequencer micro core with internal on-chip RAM for storing ADC samples. This configuration is useful for basic system monitoring application.
In a system monitoring application, the ADC captures a block of samples data and stores them in the onchip RAM. The host processor retrieves the data before triggering another block of ADC data sample request. The speed of the host processor in servicing the interrupt determines the interval between each block sample request.
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Configuration 2: Standard Sequencer with Avalon-MM Sample Storage and
Threshold Violation Detection
Figure 2-7: Standard Sequencer with Avalon-MM Sample Storage (Altera Modular ADC IP Core)
peripheral clock peripheral reset
CSR altera_adc altera_adc_sequencer
S SRC command altera_adc_control
SNK
SRC
2-13
adc_pll_clock
(clock from dedicated PLL) adc_pll_locked
(locked signal from dedicated PLL)
CSR
IRQ altera_adc_sample_store
S SNK response
Figure 2-8: Standard Sequencer with Avalon-MM Sample Storage (Altera Modular Dual ADC IP Core)
peripheral clock peripheral reset
CSR altera_dual_adc altera_adc_sequencer
SRC
S
SRC command altera_adc_control
SNK SRC response
SRC sync handshake
SNK altera_dual_adc_synchronizer
SNK sync handshake
SRC command
SNK SRC response altera_adc_control altera_adc_response_merge
SNK
SRC
SNK altera_adc_sample_store response
SNK S adc_pll_clock
(clock from dedicated PLL) adc_pll_locked
(locked signal from dedicated PLL)
CSR
IRQ
•
•
Related Information
Customizing and Generating Altera Modular ADC IP Core
on page 4-3
In this configuration variant, you can use the standard sequencer micro core with internal on-chip RAM for storing ADC samples with the additional capability of detecting threshold violation. This configuration is useful for system monitoring application where you want to know whether the ADC samples value fall outside the maximum or minimum threshold value.
When the threshold value is violated, the Altera Modular ADC or Altera Modular Dual ADC IP core notifies the discrete logic component. The discrete component then triggers system recovery action. For example, the system can increase the fan speed in a temperature control system.
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Configuration 2: Standard Sequencer with Avalon-MM Sample Storage and
Threshold Violation Detection
Figure 2-9: Standard Sequencer with Avalon-MM Sample Storage and Threshold Violation Detection
(Altera Modular ADC IP Core)
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peripheral clock peripheral reset
CSR altera_adc altera_adc_sequencer
S SRC command altera_adc_control
SNK
SRC adc_pll_clock
(clock from dedicated PLL) adc_pll_locked
(locked signal from dedicated PLL) response
CSR
IRQ altera_adc_sample_store
S SNK response
Avalon ST Splitter
Core
SRC
SNK
SRC threshold altera_adc_threshold_detect
SRC SNK response
In dual ADC mode, you can configure the threshold detection of each ADC instance independently of each other. This capability is available because each ADC instance measures different analog metrics.
Figure 2-10: Standard Sequencer with Avalon-MM Sample Storage and Threshold Violation Detection
(Altera Modular Dual ADC IP Core)
peripheral clock peripheral reset
CSR threshold altera_dual_adc
S altera_adc_sequencer
SRC
SRC command altera_adc_control
SNK SRC response
SRC sync handshake
SNK altera_dual_adc_synchronizer command
SNK sync handshake
SRC
SNK SRC response altera_adc_control
SRC altera_adc_threshold_detect
SNK response
SRC
SNK
SRC
Avalon ST Splitter
Core response altera_adc_response_merge
SNK
SRC
SNK
Avalon ST Splitter
Core
SNK SRC
SRC
SNK response response altera_adc_threshold_detect
SRC response altera_adc_sample_store
SNK S threshold adc_pll_clock
(clock from dedicated PLL) adc_pll_locked
(locked signal from dedicated PLL)
CSR
IRQ
•
•
Related Information
Customizing and Generating Altera Modular ADC IP Core
on page 4-3
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Configuration 3: Standard Sequencer with External Sample Storage
2-15
In this configuration variant, you can use the standard sequencer micro core and store the ADC samples in external storage.
You need to design your own logic to interface with the external storage.
Figure 2-11: Standard Sequencer with External Sample Storage (Altera Modular ADC IP Core)
peripheral clock peripheral reset
CSR altera_adc
S altera_adc_sequencer
SRC command altera_adc_control
SNK
SRC adc_pll_clock
(clock from dedicated PLL) adc_pll_locked
(locked signal from dedicated PLL) response
Figure 2-12: Standard Sequencer with External Sample Storage (Altera Modular Dual ADC IP Core)
peripheral clock peripheral reset
CSR altera_dual_adc altera_adc_sequencer
SRC
S
SRC altera_adc_control command
SNK SRC
SRC sync handshake
SNK altera_dual_adc_synchronizer
SNK sync handshake
SRC command
SNK SRC altera_adc_control response adc_pll_clock
(clock from dedicated PLL) adc_pll_locked
(locked signal from dedicated PLL) response
•
•
Related Information
Customizing and Generating Altera Modular ADC IP Core
on page 4-3
In this configuration variant, the Altera Modular ADC generates only the ADC control core. You have full flexibility to design your own application-specific sequencer and use your own way to manage the ADC samples.
MAX 10 ADC Architecture and Features
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Configuration 4: ADC Control Core Only
Figure 2-13: ADC Control Core Only (Altera Modular ADC IP Core)
peripheral clock peripheral reset command altera_adc altera_adc_control
SNK
SRC adc_pll_clock
(clock from dedicated PLL) adc_pll_locked
(locked signal from dedicated PLL) response
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Figure 2-14: ADC Control Core Only (Altera Modular Dual ADC IP Core)
command peripheral clock peripheral reset command altera_dual_adc altera_adc_control
SNK SRC
SRC sync handshake
SNK altera_dual_adc_synchronizer
SNK sync handshake
SRC
SNK SRC altera_adc_control response adc_pll_clock
(clock from dedicated PLL) adc_pll_locked
(locked signal from dedicated PLL) response
•
•
Related Information
Customizing and Generating Altera Modular ADC IP Core
on page 4-3
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Altera Modular ADC and Altera Modular Dual ADC IP Cores Architecture
The Altera Modular ADC IP core consists of six micro cores.
2-17
Table 2-2: Altera Modular ADC Micro Cores
Micro Core
ADC control
Description
This core interacts with the ADC hard IP block. The ADC control core uses
Avalon ST interface to receive commands from upstream cores, decodes, and drives the ADC hard IP block accordingly.
Sequencer
This core contains command register and static conversion sequence data. The sequencer core issues commands for downstream cores to execute.
• You can use the command register to configure the intended conversion mode.
• You can configure the length and content of the conversion sequence data only when generating the IP core.
• You can access the register of the sequencer core through the Avalon-MM slave interface.
• The command information to the downstream core goes through the
Avalon ST interface.
Sample storage
This core stores the ADC samples that are received through the Avalon ST interface.
• The samples are stored in the on-chip RAM. You can retrieve the samples through the Avalon-MM slave interface.
• With this core, you have the option to generate interrupt when the ADC receives a block of ADC samples (one full round of conversion sequence).
Response merge
This core merges simultaneous responses from two ADC control cores into a single response packet to send to the sample storage core. This core is available only if you use the Altera Modular Dual ADC IP core in the following configurations:
• Standard Sequencer with Avalon-MM Sample Storage
• Standard Sequencer with Avalon-MM Sample Storage and Threshold
Violation Detection
Dual ADC synchronizer core
This core performs synchronization handshakes between two ADC control cores. This core is available only if you use the Altera Modular Dual ADC IP core.
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ADC Control Core
Micro Core
Threshold detection
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Description
• This core supports fault detection. The threshold detection core receives
ADC samples through the Avalon ST interface and checks whether the samples value exceeds the maximum or falls below the minimum threshold value.
• The threshold detection core conveys threshold value violation information through the Avalon ST interface.
• You can configure which channel to enable for maximum and minimum threshold detection and the threshold values only during IP core generation.
The ADC control core drives the ADC hard IP according to the command it receives. The control core also maps the channels from the Altera Modular ADC IP core to the channels in the ADC hard IP block.
The ADC control core of the Altera Modular ADC IP core implements only the functions that are related to ADC hard IP block operations. For example:
• Power up
• Power down
• Analog to digital conversion on analog pins
• Analog to digital conversion on on-chip temperature sensor
The ADC control core has two clock domains:
• One clock domain for clocking the ADC control core soft logic
• Another clock domain for the ADC hard IP block
The ADC control core does not have run-time configurable options.
Figure 2-15: ADC Control Core High-Level Block Diagram
peripheral clock peripheral reset command altera_adc_control
SNK
ADC
Controller
FSM
ADC
Hard IP
Wrapper
SRC
SRC adc_pll_clock
(clock from dedicated PLL) adc_pll_locked
(locked signal from dedicated PLL) response sync handshake (dual ADC only)
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Table 2-3: ADC Control Core Backpressure Behavior
Interface
Command
Backpressure Behavior
Sequencer Core
2-19
The ADC control core asserts ready when it is ready to perform a sample conversion.
The ADC control core only accepts one command at a time. The control core releases ready when it completes processing current command and prepares to perform the next command.
Once the ADC control core asserts "cmd_ready=1" to acknowledge the current command, the Sequencer core provides the next valid request within two clock cycles.
If the next valid request comes after two clock cycles, the ADC control core perform non-continuous sampling.
Response
The ADC control core does not support backpressure in the response interface. The fastest back-to-back assertion of valid request is 1 µs.
The sequencer core controls the type of conversion sequence performed by the ADC hard IP. You can configure the conversion mode during run time using the sequencer core registers.
During Altera Modular ADC or Altera Modular Dual ADC IP core configuration, the sequencer core provides up to 64 configurable slots. You can define the sequence that the ADC channels are sampled by selecting the ADC channel for each sequencer slot.
The sequencer core has a single clock domain.
Figure 2-16: Sequencer Core High-Level Block Diagram
peripheral clock peripheral reset
CSR altera_adc_sequencer
Command Register
S
Static Conversion
Sequence Data Array
(up to 64 slots)
Sequencer
Controller
Sequencer
Controller
SRC
SRC command command
(dual ADC only)
Table 2-4: Sequencer Core Conversion Modes
Conversion Mode
Single cycle ADC conversion
Description
• In this mode, when the run bit is set, ADC conversion starts from the channel that you specify in the first slot.
• The conversion continues onwards with the channel that you specify in each sequencer slot.
• Once the conversion finishes with the last sequencer slot, the conversion cycle stops and the ADC hard IP block clears the run bit.
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Sample Storage Core
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Conversion Mode
Continuous ADC conversion
Description
• In this mode, when the run bit is set, ADC conversion starts from the channel that you specify in the first slot.
• The conversion continues onwards with the channel that you specify in each sequencer slot.
• Once the conversion finishes with the last sequencer slot, the conversion begins again from the first slot of the sequence.
• To stop the continuous conversion, clear the run bit. The sequencer core continues the conversion sequence until it reaches the last slot and then stops the conversion cycle.
•
•
•
Related Information
Altera Modular ADC Parameters Settings
on page 5-2
Lists the parameters available during Altera Modular ADC IP core configuration.
Altera Modular Dual ADC Parameters Settings
on page 5-8
Lists the parameters available during Altera Modular Dual ADC IP core configuration.
on page 5-18
Lists the registers for run-time control of the sequencer core.
The sample storage core stores the ADC sampling data in the on-chip RAM. The sample storage core stores the ADC samples data based on conversion sequence slots instead of ADC channels.
For example, if you sample a sequence of CH1, CH2, CH1, CH3, CH1, and then CH4, the ADC sample storage core stores the channel sample data in the same RAM entry sequence. This means that CH1 sample data will be in the first, third, and fifth RAM entries; one for each sequence slot.
The sample storage core asserts IRQ when it completes receipt of a sample block. You can disable the IRQ assertion during run time using the interrupt enable register (IER) of the sample storage core. If you disable IRQ assertion, you must create polling methods in your design to determine the complete receipt of a sample block.
The sample storage core has a single clock domain.
Figure 2-17: Sample Storage Core High-Level Block Diagram
peripheral clock peripheral reset
CSR
IRQ altera_adc_sample_store
S
64 RAM Entries for
ADC Sample Storage
IER Register
ISR Register
RAM
Control
Interrupt
Control
SNK response
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Response Merge Core
2-21
Related Information
on page 5-19
The response merge core merges simultaneous responses from two ADC control cores in the Altera
Modular Dual ADC IP core.
The Altera Modular Dual ADC IP core uses the response merge core if you use the following configura‐ tions:
• Standard Sequencer with Avalon-MM Sample Storage
• Standard Sequencer with Avalon-MM Sample Storage and Threshold Violation Detection
Figure 2-18: Response Merge Core High-Level Block Diagram
altera_adc_response_merge peripheral clock peripheral reset response response
SNK
SNK
Response merge logic
SRC response
The dual ADC synchronizer core performs synchronization handshakes between two ADC control cores in the Altera Modular Dual ADC IP core.
The peripheral clock domain is asynchronous to the ADC PLL clock domain in the ADC control core.
Control event from the ADC hard IP block can appear at the peripheral clock domain at the same time, or by a difference of one peripheral clock between ADC1 and ADC2 control cores. Both ADC hard IP cores communicate with the dual ADC synchronizer core through the Avalon-ST interface.
For example, although a new command valid event from the sequencer arrives at both ADC control cores at the same peripheral clock cycle, the end of conversion signals arrive at one peripheral clock cycle difference between ADC1 and ADC2. To avoid the condition where ADC1 begins conversion earlier or later than ADC2, the ADC control core performs synchronization handshake using the dual ADC synchronizer core.
An ADC control core asserts a sync_valid
signal when it detects an ADC PLL clock domain event. The dual ADC synchronizer core asserts the sync_ready
signal after it receives sync_valid
signals from both
ADC control cores. After the sync_ready
signal is asserted, both ADC control cores proceed to their next internal state.
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Threshold Detection Core
Figure 2-19: Dual ADC Synchronizer Core High-Level Block Diagram
altera_dual_adc_synchronizer peripheral clock peripheral reset sync handshake sync handshake
SNK
SNK
Synchronizer logic
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The threshold detection core compares the sample value that the ADC block receives to the threshold value that you define during Altera Modular ADC IP core configuration. This core does not have run-time configurable options.
If the ADC sample value is beyond the maximum or minimum threshold limit, the threshold detection core issues a violation notification through the Avalon-ST interface.
The threshold detection core has a single clock domain.
Figure 2-20: Threshold Detection Core High-Level Block Diagram
altera_adc_threshold_detect peripheral clock peripheral reset threshold SRC
Comparator
Logic
SNK response
The Altera ADC HAL driver supports the following features:
• Read ADC channel data.
• Enable maximum or minimum threshold and return a user callback when the interrupt is triggered.
• Command the control of the ADC (run, stop, and recalibrate).
•
•
Related Information
HAL API Reference, Nios II Gen 2 Software Developer's Handbook
Provides more information about the HAL API.
ADC HAL Device Driver for Nios II Gen 2
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ADC Toolkit for Testing ADC Performance
2-23
You can use the ADC Toolkit provided with the Quartus Prime software to understand the performance of the analog signal chain as seen by the MAX 10 ADC blocks.
The ADC Toolkit supports monitoring the ADC whether you use the Altera Modular ADC or Altera
Modular Dual ADC IP core. However, the ADC Toolkit can only monitor one ADC block at a time. If you are using the Altera Modular Dual ADC IP core, configure the Debug Path parameter in the IP core to select which ADC block you want to hook up to the ADC Toolkit.
Related Information
ADC Toolkit
Provides more information about the ADC Toolkit.
By default, the ADC logic simulation outputs a fixed unique value for each ADC channel. However, you can enable an option to specify your own output values for each ADC channel other than the TSD.
The ADC simulation model for MAX 10 devices supports the standard digital logic simulators that the
Quartus Prime software supports.
Related Information
Quartus Prime Simulator Support
By default, the Enable user created expected output file option in the Altera Modular ADC or Altera
Modular Dual ADC IP core is disabled. The ADC simulation always output a fixed value for each ADC channel, including the analog and TSD channels. The values are different for single and dual ADC devices.
Table 2-5: Fixed Expected Output Data for Single ADC Device Simulation
Channel
CH0
CH1
CH2
CH3
CH4
CH5
CH6
CH7
CH8
CH9
Expected Output Data (Decimal Value)
5
6
3
4
0
1
2
7
8
9
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User-Specified ADC Logic Simulation Output
Channel
CH10
CH11
CH12
CH13
CH14
CH15
CH16
TSD
Expected Output Data (Decimal Value)
14
15
16
3615
10
11
12
13
Table 2-6: Fixed Expected Output Data for Dual ADC Device Simulation
Channel
CH0
CH1
CH2
CH3
CH4
CH5
CH6
CH7
CH8
TSD
ADC1
13
14
15
16
17
10
11
12
18
3615
Expected Output Data (Decimal Value)
ADC2
23
24
25
26
20
21
22
27
28
—
(No TSD in ADC2)
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You can configure the Altera Modular ADC or Altera Modular Dual ADC IP core to output user-specified values in the logic simulation for each ADC channel except the TSD channel.
If you enable this feature, you must provide a simulation stimulus input file for each ADC channel that you enable. The logic simulation reads the input file for each channel and outputs the value of the current sequence. Once the simulation reaches the end of the file, it repeats from the beginning of the sequence.
The stimulus input file is a plain text file that contains two columns of numbers:
• The first column of numbers is ignored by the simulation model. You can use any values that you want such as time or sequence. The actual data sequencing is based on the text rows.
• The second column contains the voltage values.
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User-Specified ADC Logic Simulation Output
2-25
The ADC IP core automatically converts each voltage value to a 12-bit digital value based on the reference voltage you specify in the IP core parameter settings.
Figure 2-21: Simulation Output Example, One Channel Enabled
SIM_FILE_CH0
1 0.2
2 0.5
3 0.8
4 1.1
5 1.4
V
IN
Sequence pattern:
CH0, CH0, CH0...
V
IN
V
REF
× 2
12
Pattern repeats
V
REF
= 2.5 V
Observed Simulator Output
Voltage values (Hexadecimal)
0x148
0x333
0x51F
0x70A
0x8F6
0x148
0x333
.
.
.
Simulation time flow
Figure 2-22: Simulation Output Example, Two Channels Enabled
SIM_FILE_CH0
1 0.2
2 0.5
3 0.8
4 1.1
5 1.4
V
IN
SIM_FILE_CH1
1 0.4
2 0.9
3 1.3
4 1.5
5 2.2
Sequence pattern:
CH0, CH1, CH0, CH1...
V
IN
V
REF
× 2
12
Pattern repeats
V
REF
= 2.3 V
Observed Simulator Output
Voltage values (Hexadecimal)
.
.
.
0x9BD
0xF4E
0x164
0x2C8
0x164
0x2C8
0x37A
0x643
0x591
0x90B
0x7A7
0xA6F
Simulation time flow
V
IN
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There are several considerations that require your attention to ensure the success of your designs. Unless noted otherwise, these design guidelines apply to all variants of this device family.
Related Information
MAX 10 Analog to Digital Converter Overview
on page 1-1
3
For the ADC and V
REF
pins, use the
REFGND
pin as the analog ground plane connection.
Related Information
MAX 10 FPGA Device Family Pin Connection Guidelines
Provides more information about pin connections including pin names and connection guidelines.
REFGND
The crosstalk requirement for analog to digital signal is -100 dB up to 2 GHz. There must be no parallel routing between power, ground, and surrounding general purpose I/O traces. If a power plane is not possible, route the power and ground traces as wide as possible.
• To reduce IR drop and switching noise, keep the impedance as low as possible for the ADC power and ground. The maximum DC resistance for power is 1.5 Ω.
• The power supplies connected to the ADC should have ferrite beads in series followed by a 10 µF capacitor to the ground. This setup ensures that no external noise goes into the device power supply pins.
• Decouple each of the device power supply pin with a 0.1 µF capacitor. Place the capacitor as close as possible to the device pin.
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2016 Intel Corporation. All rights reserved. Intel, the Intel logo, Altera, Arria, Cyclone, Enpirion, MAX, Megacore, NIOS, Quartus and Stratix words and logos are trademarks of Intel Corporation in the US and/or other countries. Other marks and brands may be claimed as the property of others. Intel warrants performance of its FPGA and semiconductor products to current specifications in accordance with Intel's standard warranty, but reserves the right to make changes to any products and services at any time without notice. Intel assumes no responsibility or liability arising out of the application or use of any information, product, or service described herein except as expressly agreed to in writing by Intel. Intel customers are advised to obtain the latest version of device specifications before relying on any published information and before placing orders for products or services.
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101 Innovation Drive, San Jose, CA 95134
ISO
9001:2008
Registered
3-2
Guidelines: Board Design for Analog Input
Figure 3-1: Recommended RC Filter for Power Traces
Ferrite Beads
Power
Supply
10 µF
Power
Supply
Ferrite Beads
GND
10 µF
GND
VCCADC_2P5
0.1 µF
Place this cap close to the pin
GND
0.1 µF
Place this cap close to the pin
GND
VCCADC_1P2
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There is no impedance requirement for the
REFGND
. Altera recommends that you use the lowest impedance with the most minimum DC resistance possible. Typical resistance is less than 1 Ω.
Altera recommends that you set a
REFGND
plane that extends as close as possible to the corresponding decoupling capacitor and FPGA:
• If possible, define a complete
REFGND
plane in the layout.
• Otherwise, route the
REFGND
using a trace that is as wide as possible from the island to the FPGA pins and decoupling capacitor.
• The
REFGND
ground is the analog ground plane for the ADC V
REF
and analog input.
• Connect
REFGND
ground to the system digital ground through ferrite beads. You can also evaluate the ferrite bead option by comparing the impedance with the frequency specifications.
The crosstalk requirement for analog to digital signal is -100 dB up to 2 GHz. There must be no parallel routing between analog input signals and I/O traces, and between analog input signals and FPGA I/O signal traces.
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Guidelines: Board Design for Analog Input
3-3
• The ADC presents a switch capacitor load to the driving circuit. Therefore, the total RC constant, including package, trace, and parasitic driver must be less than 42.4 ns. This consideration is to ensure that the input signal is fully settled during the sampling phase.
• If you reduce the total sampling rate, you can calculate the required settling time as
0.45 ÷ F
S
> 10.62 × RC constant
.
• To gain more total RC margin, Altera recommends that you make the driver source impedance as low as possible:
• For non-prescaler channel—less than 1 kΩ
• For prescaler channel—less than 11 Ω
Note: Not adhering to the source impedance recommendation may impact parameters such as total harmonic distortion (THD), signal-to-noise and distortion ratio (SINAD), differential nonlinearity (DNL), and integral non-linearity (INL).
Trace Routing
• If possible, route the switching I/O traces on different layers.
• There is no specific requirement for input signal trace impedance. However, the DC resistance for the input trace must be as low as possible.
• Route the analog input signal traces as adjacent as possible to
REFGND
if there is no
REFGND
plane.
• Use
REFGND
as ground reference for the ADC input signal.
• For prescaler-enabled input signal, set the ground reference to
REFGND
. Performance degrades if the ground reference of prescaler-enabled input signal is set to common ground (
GND
).
Input Low Pass Filter Selection
• Altera recommends that you place a low pass filter to filter out high frequency noise being aliased back onto the input signal.
• Place the low pass filter as close as possible to the analog input signals.
• The cut off frequency depends on the analog input frequency. Altera recommends that the F cutoff @ -3dB is at least two times the input frequency.
• You can download the ADC input SPICE model for ADC front end board design simulation from the
Altera website.
Table 3-1: RC Constant and Filter Value
This table is an example of the method to quantify the RC constant and identify the RC filter value.
Total RC Constant = (R
DRIVER
C
FILTER
+ C
PIN
)
+ R
BOARD
+ R
PACKAGE
+ R
FILTER
) × (C
DRIVER
+ C
BOARD
+ C
PACKAGE
+
Driver
R (Ω)
5
10
C
(pF)
2
2
Board
R (Ω)
5
5
C
(pF)
17
17
Package
R (Ω)
3
3
C
(pF)
5
5
Pin
Capacitance
(pF)
6
6
RC Filter
R (Ω)
60
50
C
(pF)
550
580
F cutoff @ -3dB
(MHz)
4.82
5.49
Total RC
Constant
(ns)
42.34
41.48
Settling Time
(ns)
42.4
42.4
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Guidelines: Board Design for ADC Reference Voltage Pin
Figure 3-2: Passive Low Pass Filter Example
Driver RC
Board RC
R
FILTER
Place this cap close to the pin
C
FILTER
ADC Analog Input
Altera
Device
REFGND
Figure 3-3: First Order Active Low Pass Filter Example
This figure is an example. You can design
n
th order active low pass filter.
C1
Board RC
Driver RC
R1 R2
C2
+
-
Cut-off frequency:
ƒ c
=
1
2π R1C1R2C2
REFGND
ADC Analog Input
Altera
Device
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Parameters Settings for Generating Altera Modular ADC or Altera Modular Dual ADC IP Core
on page 4-5
Altera Modular ADC Parameters Settings
on page 5-2
Altera Modular Dual ADC Parameters Settings
on page 5-8
SPICE Models for Altera Devices
Provides the MAX 10 ADC spice model download.
The crosstalk requirement for analog to digital signal is -100 dB up to 2 GHz. There is no parallel routing between analog input signals and I/O traces. Route the V
REF
traces as adjacent as possible to
REFGND
.
If a
REFGND
plane is not possible, route the analog input signal as adjacent as possible to
REFGND
.
There is one ADC reference voltage pin in each MAX 10 device. This pin uses
REFGND
as ground reference.
Keep the trace resistance less than 0.8 Ω.
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Guidelines: Board Design for ADC Reference Voltage Pin
Figure 3-4: RC Filter Design Example for Reference Voltage Pin
Place the RC filter as close as possible to the analog input pin.
V
REF
3-5
1.0 Ω
10.0 µF 1 µF Altera device
REFGND REFGND
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You can implement your ADC design in the Quartus Prime software. The software contains tools for you to create and compile your design, and configure your device.
The Quartus Prime software allows you to set up the parameters and generate your Altera Modular ADC
IP core. To understand the ADC signal performance, you can use the Quartus Prime ADC Toolkit. For more information about using the Quartus Prime software and the ADC toolkit, refer to the related information.
Figure 4-1: High Level Block Diagram of the MAX 10 ADC Solution
4
Altera FPGA
User Design
Avalon-MM
Master
ADC soft IP clock
Avalon-MM interface
RAM Block
Bidirectional dual port
Altera Modular ADC IP Core
Avalon MM Slave
RAM read/write CSR and ADC digital output
Sequencer state machine
ADC hard IP clock
Altera PLL
IP Core
ADC hard IP block
Control, status, and data signals to sample analog input pin, one pin at a time
External voltage reference pin
Analog input pins
•
Related Information
MAX 10 Analog to Digital Converter Overview
on page 1-1
©
2016 Intel Corporation. All rights reserved. Intel, the Intel logo, Altera, Arria, Cyclone, Enpirion, MAX, Megacore, NIOS, Quartus and Stratix words and logos are trademarks of Intel Corporation in the US and/or other countries. Other marks and brands may be claimed as the property of others. Intel warrants performance of its FPGA and semiconductor products to current specifications in accordance with Intel's standard warranty, but reserves the right to make changes to any products and services at any time without notice. Intel assumes no responsibility or liability arising out of the application or use of any information, product, or service described herein except as expressly agreed to in writing by Intel. Intel customers are advised to obtain the latest version of device specifications before relying on any published information and before placing orders for products or services.
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Quartus II Handbook, Volume 1: Design and Synthesis
Provides more information about using IP cores in the Quartus II software.
Introduction to Altera IP Cores
Provides general information about all Altera FPGA IP cores, including parameterizing, generating, upgrading, and simulating IP cores.
Creating Version-Independent IP and Qsys Simulation Scripts
Create simulation scripts that do not require manual updates for software or IP version upgrades.
Project Management Best Practices
Guidelines for efficient management and portability of your project and IP files.
ADC Toolkit
Provides more information about the ADC Toolkit.
ADC Toolkit for Testing ADC Performance
To create your ADC design, you must customize and generate the ALTPLL and Altera Modular ADC IP cores.
The ALTPLL IP core provides the clock for the Altera Modular ADC IP core.
1. Customize and generate the ALTPLL IP core.
2. Customize and generate the Altera Modular ADC IP core.
3. Connect the ALTPLL IP core to the Altera Modular ADC IP core.
4. Create ADC Avalon slave interface to start the ADC.
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Related Information
Customizing and Generating Altera Modular ADC IP Core
on page 4-3
Parameters Settings for Generating Altera Modular ADC or Altera Modular Dual ADC IP Core
on page 4-5
Parameters Settings for Generating ALTPLL IP Core
MAX 10 Getting Started
MAX 10 Online Training
MAX 10 How-to Videos
How to Create ADC Design in MAX 10 Device Using Qsys Tool
Provides video instruction that demonstrates how to create the ADC design in MAX 10 devices using the Qsys system integration tool within the Quartus Prime software and how to use the ADC toolkit to view the measured analog signal.
How to Create Simultaneous Measurement with MAX 10 ADC, Part 1
Provides the first part of video instruction series that explains the differences between the MAX 10
Altera Modular ADC and Altera Modular Dual ADC IP cores. The video also demonstrates how to create a simple simultaneous ADC measurement and how to place signal taps to measure the digital code output for analog signal.
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How to Create Simultaneous Measurement with MAX 10 ADC, Part 2
Provides the second part of video instruction series that explains the differences between the MAX 10
Altera Modular ADC and Altera Modular Dual ADC IP cores. The video also demonstrates how to create a simple simultaneous ADC measurement and how to place signal taps to measure the digital code output for analog signal.
Altera recommends that you use the Altera Modular ADC IP core with a Nios II processor, which supports the ADC HAL driver.
1. Create a new project in the Quartus Prime software.
While creating the project, select a device that has one or two ADC blocks.
2. In the Quartus Prime software, select Tools > Qsys.
3. In the Qsys window, select File > New System.
A clock source block is automatically added under the System Contents tab.
4. In the System Contents tab, double click the clock name.
5. In the Parameters tab for the clock source, set the Clock frequency.
6. In the IP Catalog tab in the Qsys window, double click Processors and Peripherals > Peripherals >
Altera Modular ADC.
The Altera Modular ADC appears in the System Contents tab and the Altera Modular ADC parameter editor opens.
7. In the Altera Modular ADC parameter editor, specify the parameter settings and channel sampling sequence for your application.
8. In the System Contents tab in the Qsys window, double click the Export column of the adc_pll_clock
and adc_pll_locked
interfaces to export them.
9. Connect the clock
, reset_sink
, sample_store_csr
, and sample_store_irq
signals. Optionally, you can use the Nios II Processor, On-Chip Memory, and JTAG UART IP cores to form a working ADC system that uses the Altera ADC HAL drivers.
10.In the Qsys window, select File > Save.
You can copy an example HDL code to declare an instance of your ADC system. In the Qsys window, select Generate > HDL Example.
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Related Information
on page 4-2
Parameters Settings for Generating ALTPLL IP Core
Parameters Settings for Generating Altera Modular ADC or Altera Modular Dual ADC IP Core
on page 4-5
Configuration 1: Standard Sequencer with Avalon-MM Sample Storage
on page 2-12
Configuration 2: Standard Sequencer with Avalon-MM Sample Storage and Threshold Violation
on page 2-13
Configuration 3: Standard Sequencer with External Sample Storage
on page 2-15
Configuration 4: ADC Control Core Only
ADC PLL Clock Interface of Altera Modular ADC and Altera Modular Dual ADC
ADC PLL Locked Interface of Altera Modular ADC and Altera Modular Dual ADC
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Navigate through the ALTPLL IP core parameter editor and specify the settings required for your design.
After you have specified all options as listed in the following table, you can generate the HDL files and the optional simulation files.
For more information about all ALTPLL parameters, refer to the related information.
Table 4-1: ALTPLL Parameters Settings
To generate the PLL for the ADC, use the following settings.
Tab Parameter
Parameter Settings > General/
Modes
Parameter Settings > Inputs/
Lock
What is the frequency of the inclk0 input?
Create an 'areset' input to asynchronously reset the PLL
Create 'locked' output
Specify the input frequency to the PLL.
Turn off this option.
Setting
Turn on this option. You need to connect this signal to the adc_pll_locked
port of the
Altera Modular ADC or Altera Modular Dual
ADC IP core.
Use this clock
Turn on this option.
Enter output clock frequency
Output Clocks > clk c0
Specify an output frequency of 2, 10, 20, 40, or 80 MHz. You can specify any of these frequencies. The ADC block runs at 1 MHz internally but it contains a clock divider that can further divide the clock by a factor of 2,
10, 20, 40, and 80.
Use this same frequency value in your Altera
Modular ADC or Altera Modular Dual ADC
IP core. You need to connect this signal to the adc_pll_clock
port of the Altera Modular
ADC or Altera Modular Dual ADC IP core.
Different ADC sampling rates support different clock frequencies. For a valid sampling rate and clock frequency combina‐ tion, refer to the related information.
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Related Information
on page 4-2
Customizing and Generating Altera Modular ADC IP Core
on page 4-3
MAX 10 Clock Networks and PLLs User Guide
ADC PLL Clock Interface of Altera Modular ADC and Altera Modular Dual ADC
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IP Core
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ADC PLL Locked Interface of Altera Modular ADC and Altera Modular Dual ADC
Valid ADC Sample Rate and Input Clock Combination
on page 5-13
Navigate through the Altera Modular ADC IP core parameter editor and specify the settings required for your design. After you have specified all options as listed in the following tables, you can generate the HDL files and the optional simulation files.
Altera recommends that you save the generated files in the design file directory (default setting).
For more information about each Altera Modular ADC or Altera Modular Dual ADC parameter, refer to the related information section.
Table 4-2: Parameter Settings in General Group
Parameter
Core Variant
Setting
There are four configuration variants of the Altera Modular ADC IP core. Select the core variant that meets your requirement. For more information, refer to the related information.
Debug Path
Turn this on to enable the debug path for the selected core variant. You can use the ADC Toolkit to monitor the ADC performance.
Generate IP for which ADCs of this device?
For devices with two ADC blocks, select the ADC block for which you are generating the IP core. There are feature differences between the two ADC blocks. The temperature sensor is available only in the first
ADC block. There are also different channel counts in both ADC blocks.
ADC Sample Rate
Select the predefined sampling rate for the ADC from 25 kHz to
1 MHz. A lower sampling rate allows you greater flexibility in designing your ADC front end driver circuit. For example, using a lower sampling rate gives you a wider settling time margin for your filter design.
The sampling rate you select affects which ADC input clock frequencies are available.
Refer to the related information for more details about the sampling rate and the required settling time.
ADC Input Clock
Select the same frequency that you set for the ALTPLL IP core that clocks the Altera Modular ADC IP core. When configuring the
ALTPLL IP core, specify a clock frequency that is supported by the
ADC sampling rate. For more details, refer to the related information.
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Parameters Settings for Generating Altera Modular ADC or Altera Modular Dual ADC
IP Core
Parameter Setting
Reference Voltage Source
Select whether you want to use external or internal reference voltage.
There is only one
VREF
pin. For dual ADC blocks, you can use one external V
REF
source for both ADC blocks, or external V
ADC block and internal V
REF
for the other ADC block.
REF
for one
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External Reference Voltage
Enable user created expected output file
If you use external V
REF
source in your design, specify the V
REF
level.
If you want to use your own stimulus input file to simulate the ADC output data, enable this function and specify the file for the specific
ADC channel. For more information about user-specified ADC logic simulation output, refer to the related information.
Table 4-3: Parameters Settings in Channels Group
You can navigate through the tabs for all the available channels and turn on the channel you want to use.
In each channel (and TSD) tab, you can specify the settings in this table.
Parameter Setting
Use Channel 0 (Dedicated analog input pin - ANAIN)
This option is available in the CH0 tab.
CH0 is the dedicated analog input channel. If you want to use the dedicated analog input, turn on this option.
User created expected output file If you enabled the option to use your own stimulus input file to simulate the output data, click Browse and select the file for each enabled channel.
This option is available in all channel tabs except the TSD tab.
Use Channel
N
You can select which dual-function ADC channels to turn on or off.
There are 16 channels (CH1 to CH16) for single ADC devices and 8 channels (CH1 to CH8) for each ADC block in dual ADC devices.
Use on-chip TSD
This option is available in the TSD tab. The TSD channel is the temperature sensing channel.
Turn on this option if you want the IP core to read the built-in temperature sensor in the ADC block.
The sampling rate of the ADC block reduces to 50 kHz when it reads the temperature measurement. After it completes the temperature reading, the ADC sampling rate returns to 1 MHz.
For the Altera Modular Dual ADC IP core, if you specify the TSD in a sequencer slot for ADC1, specify NULL in the same sequencer slot number for ADC2.
Enable Maximum threshold for
Channel
N
Turn on this option if you want to set a maximum threshold value for the channel.
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Parameter
Parameters Settings for Generating Altera Modular ADC or Altera Modular Dual ADC
IP Core
Setting
Enter Maximum Threshold for
Channel
N
Enter the maximum threshold voltage for the channel. The IP core will generate a threshold violation notification signal to indicate that the sampled data is over the threshold value that you specify.
4-7
Enable Maximum threshold for on-chip TSD (TSD tab)
Enter the maximum threshold temperature for the temperature sensor in Celsius. The IP core will generate a threshold violation notification signal to indicate that the sampled temperature is over the temperature that you specify.
Enable Minimum threshold for
Channel
N
Turn on this option if you want to set a minimum threshold value for the channel.
Enter Minimum Threshold for
Channel
N
Enter the minimum threshold voltage for the channel. The IP core will generate a threshold violation notification signal to indicate that the sampled data is below the threshold value that you specify.
Enter Minimum Threshold for on-chip TSD (TSD tab)
Enter the maximum threshold temperature for the temperature sensor in Celsius. The IP core will generate a threshold violation notification signal to indicate that the sampled temperature is below the tempera‐ ture that you specify.
Table 4-4: Parameters Settings in Sequencer Group
Parameter
Number of slot used
Setting
Select the number of channels to use for conversion. The parameter editor displays the number of slots available in the Conversion
Sequence Channels based on your selection.
Slot
N
For each available slot, select the channel to sample in the sequence.
The available channels depend on the channels that you turned on in the Channels parameters group.
If you turned on a channel but do not select the channel in any of the sequencer slots, the unselected channel is not measured during the
ADC sampling sequence.
The ADC block samples the measurements in the sequence you specify.
After it reaches the last slot in the sequence, it repeats the sampling from the first slot.
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Related Information
on page 4-2
Customizing and Generating Altera Modular ADC IP Core
on page 4-3
Altera Modular ADC Parameters Settings
on page 5-2
Altera Modular Dual ADC Parameters Settings
on page 5-8
Altera Modular ADC IP Core Channel Name to MAX 10 Device Pin Name Mapping
MAX 10 ADC Implementation Guides
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5-12
Valid ADC Sample Rate and Input Clock Combination
on page 5-13
User-Specified ADC Logic Simulation Output
Provides more information about using your own stimulus input file to simulate the ADC output data.
Guidelines: Board Design for Analog Input
on page 3-2
Provides more information about the sampling rate and settling time.
The ADC design requires that the ALTPLL IP core clocks the Altera Modular ADC IP core.
Before you begin
Generate the ALTPLL and Altera Modular ADC IP cores with the settings in the related information.
Figure 4-2: Basic MAX 10 ADC Design
PLL
inclk0 inclk0 frequency: 100.000 MHz
Operation Mode: Normal
Clk Ratio Ph (dg) DC (%) c0 1/10 0.00
50.00
c0 locked
Altera Modular ADC
clock_clk clock clk reset_sink_reset_n adc_pll_clock_clk reset_sink adc_pll_clock reset_n clk adc_pll_locked adc_pll_locked_export export sequencer_csr_address sequencer_csr sequencer_csr_read sequencer_csr_write sequencer_csr_writedata[31..0] sequencer_csr_readdata[31..0] sample_store_csr sample_store_csr_address[6..0] sample_store_csr_read sample_store_csr_write sample_store_csr_writedata[31..0] sample_store_csr_readdata[31..0] address read write address read write writedata readdata irq writedata readdata sample_store_irq sample_store_irq_irq
1. Create the design as shown in the preceding figure.
2. Connect the c0
signal from the ALTPLL IP core to the adc_pll_clock_clk
port of the Altera Modular
ADC IP core.
3. Connect the locked
signal from the ALTPLL IP core to the adc_pll_locked_export
port of the
Altera Modular ADC IP core.
4. Create the ADC Avalon slave interface to start the ADC.
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Parameters Settings for Generating ALTPLL IP Core
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Parameters Settings for Generating Altera Modular ADC or Altera Modular Dual ADC IP Core
on page 4-5
Configuration 1: Standard Sequencer with Avalon-MM Sample Storage
on page 2-12
Configuration 2: Standard Sequencer with Avalon-MM Sample Storage and Threshold Violation
on page 2-13
Configuration 3: Standard Sequencer with External Sample Storage
on page 2-15
Configuration 4: ADC Control Core Only
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The Altera Modular ADC or Altera Modular Dual ADC IP core is a soft controller for the ADC hard IP blocks. You can generate soft IPs to instantiate the on-chip ADC blocks. With this IP core, you can configure the ADCs and abstract the low level handshake with the ADC hard IP blocks.
The Quartus Prime software generates your customized Altera Modular ADC or Altera Modular Dual
ADC IP core according to the parameter options that you set in the parameter editor.
•
•
•
Related Information
MAX 10 Analog to Digital Converter Overview
on page 1-1
Altera Modular ADC and Altera Modular Dual ADC IP Cores
Altera Modular ADC IP Core Configuration Variants
on page 2-11
on page 2-12
5
©
2016 Intel Corporation. All rights reserved. Intel, the Intel logo, Altera, Arria, Cyclone, Enpirion, MAX, Megacore, NIOS, Quartus and Stratix words and logos are trademarks of Intel Corporation in the US and/or other countries. Other marks and brands may be claimed as the property of others. Intel warrants performance of its FPGA and semiconductor products to current specifications in accordance with Intel's standard warranty, but reserves the right to make changes to any products and services at any time without notice. Intel assumes no responsibility or liability arising out of the application or use of any information, product, or service described herein except as expressly agreed to in writing by Intel. Intel customers are advised to obtain the latest version of device specifications before relying on any published information and before placing orders for products or services.
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Altera Modular ADC Parameters Settings
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There are three groups of options: General, Channels, and Sequencer.
Table 5-1: Altera Modular ADC Parameters - General
Parameter
Core Variant
Allowed Values
• Standard sequencer with
Avalon-MM sample storage
• Standard sequencer with
Avalon-MM sample storage and threshold violation detection
• Standard sequencer with external sample storage
• ADC control core only
Description
Selects the core configuration for the Altera Modular
ADC IP core.
Debug Path
• Disabled
• Enabled
Enables the debug path.
Generate IP for which
ADCs of this device?
ADC Sample Rate
• 1st ADC
• 2nd ADC
25 kHz, 50 kHz,
100 kHz, 200 kHz,
250 kHz, 500 kHz, and 1 MHz
For devices that have two ADC blocks, specifies which
ADC block you want to instantiate using the IP core.
Specifies the ADC sampling rate. The sampling rate you select affects which ADC input clock frequencies are available.
Refer to the related information for more details about the sampling rate and the required settling time.
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Parameter
ADC Input Clock
External Reference
Voltage
Allowed Values
2 MHz, 10 MHz,
20 MHz, 40 MHz, and 80 MHz
Reference Voltage Source • External
• Internal
Altera Modular ADC Parameters Settings
5-3
Description
Specifies the frequency of the PLL clock counter zero ( c0
) clock supply for the ADC core clock.
• You must configure the c0
of the first ALTPLL IP core that you instantiate to output one of the frequencies in the allowed values list.
• Connect the ALTPLL c0
output signal to the Altera
Modular ADC clk_in_pll_c0 input signal.
For valid ADC sampling rate and input clock frequencies combinations, refer to the related information.
Specifies the source of voltage reference for the ADC:
• External—uses
ADC_VREF
pin as the voltage reference source.
• Internal—uses the on-chip 2.5 V (3.0/3.3V on voltageregulated devices) as the voltage reference source.
Specifies the voltage of
ADC_VREF
pin if you use it as reference voltage to the ADC.
Enable user created expected output file
• Dual supply devices: up to
2.5 V
• Single supply devices: up to
3.63 V
• Enabled
• Disabled
Specifies the source of output data for ADC logic simulation:
• Enabled—uses the stimulus input file you provide for each ADC channel, except the TSD channel, to simulate the output data.
• Disabled—uses fixed expected output data for all
ADC channels. This is the default setting.
For more information about user-specified ADC logic simulation output, refer to the related information.
Table 5-2: Altera Modular ADC Parameters - Channels
This group of parameters is divided into several tabs—one for each channel, and one tab for the TSD.
Parameter Allowed Values Description
Enables the dedicated analog input pin.
Use Channel 0 (Dedicated analog input pin -
ANAIN)
(CH0 tab)
• On
• Off
Altera Modular ADC and Altera Modular Dual ADC IP Cores References
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Altera Modular ADC Parameters Settings
Parameter
User created expected output file
Allowed Values
—
Use Channel tab)
(TSD tab)
N
(Each channel in its own
Use on-chip TSD
Enable Maximum threshold for Channel
N
(Each channel in its own tab)
Enable Maximum threshold for on-chip
TSD
(TSD tab)
Enter Maximum
Threshold for Channel
N
(Each channel in its own tab, including channel 0)
Enter Maximum
Threshold for on-chip
TSD
(TSD tab)
Enable Minimum threshold for Channel
N
(Each channel in its own tab, including channel 0)
• On
• Off
• On
• Off
• On
• Off
• On
• Off
Depends on reference voltage
• On
• Off
—
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Description
Specifies user-created stimulus input file to simulate the output data for the channel.
This option is available for each enabled channel except the TSD if you select Enable user created expected
output file.
Enables the dual-function analog input, where
N
is:
• 1 to 16 channels for single ADC devices
• 1 to 8 channels for dual ADC devices
Specifies that the IP core reads the built-in temperature sensor in the ADC.
If you turn on this option, the ADC sampling rate is up to
50 kHz when it reads the temperature measurement.
After it completes the temperature reading, the ADC sampling rate is up to 1 MHz.
Enables the maximum threshold feature for the channel.
This option is available only if you select the Standard
sequencer with Avalon-MM sample storage and
threshold violation detection core variant.
Enables the maximum threshold feature for the TSD.
This option is available only if you select the Standard
sequencer with Avalon-MM sample storage and
threshold violation detection core variant.
Specifies the maximum threshold value in Volts.
This setting is available only if you select the Standard
sequencer with Avalon-MM sample storage and
threshold violation detection core variant.
Specifies the maximum threshold value in Celsius.
This setting is available only if you select the Standard
sequencer with Avalon-MM sample storage and
threshold violation detection core variant.
Enables the minimum threshold feature for the channel.
This option is available only if you select the Standard
sequencer with Avalon-MM sample storage and
threshold violation detection core variant.
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Parameter
Enable Minimum threshold for on-chip
TSD
(TSD tab)
Enter Minimum
Threshold for Channel
N
(Each channel in its own tab, including channel 0)
Enter Minimum
Threshold for on-chip
TSD
(TSD tab)
Enable Prescaler for
Channel
N
•
•
Allowed Values
• On
• Off
Depends on reference voltage
—
On
Off
Altera Modular ADC Parameters Settings
Description
Enables the minimum threshold feature for the TSD.
This option is available only if you select the Standard
sequencer with Avalon-MM sample storage and
threshold violation detection core variant.
Specifies the minimum threshold value in Volts.
This setting is available only if you select the Standard
sequencer with Avalon-MM sample storage and
threshold violation detection core variant.
5-5
Specifies the minimum threshold value in Celsius.
This setting is available only if you select the Standard
sequencer with Avalon-MM sample storage and
threshold violation detection core variant.
Enables the prescaler function, where
N
is:
• Channels 8 and 16 (if available) for single ADC devices.
• Channel 8 of ADC1 or ADC2 for dual ADC devices.
Table 5-3: Altera Modular ADC Parameters - Sequencer
Parameter
Number of slot used
Allowed Values
1 to 64
Description
Specifies the number of conversion sequence slots to use.
The Conversion Sequence Channels section displays the slots available according to the number of slots you select here.
Slot
N
Enabled channel number (CH
N
)
Specifies which enabled ADC channel to use for the slot in the sequence.
The selection option lists the ADC channels that you turned on in the Channels parameter group.
•
•
•
•
•
Related Information
Configuration 1: Standard Sequencer with Avalon-MM Sample Storage
on page 2-12
Configuration 2: Standard Sequencer with Avalon-MM Sample Storage and Threshold Violation
on page 2-13
Configuration 3: Standard Sequencer with External Sample Storage
on page 2-15
Configuration 4: ADC Control Core Only
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•
•
•
•
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Altera Modular ADC IP Core Channel Name to MAX 10 Device Pin Name Mapping
Altera Modular Dual ADC IP Core Channel Name to MAX 10 Device Pin Name Mapping
5-12
Valid ADC Sample Rate and Input Clock Combination
on page 5-13
User-Specified ADC Logic Simulation Output
Provides more information about using your own stimulus input file to simulate the ADC output data.
Guidelines: Board Design for Analog Input
on page 3-2
Provides more information about the sampling rate and settling time.
Each ADC channel in the Altera Modular ADC IP core corresponds to different device pin name for single and dual ADC devices.
Table 5-4: Altera Modular ADC IP Core Channel to Pin Mapping for Single ADC Devices
Channel Name
CH8
CH9
CH10
CH11
CH12
CH13
CH14
CH15
CH16
CH0
CH1
CH2
CH3
CH4
CH5
CH6
CH7
Pin Name
ANAIN1
ADC1IN1
ADC1IN2
ADC1IN3
ADC1IN4
ADC1IN5
ADC1IN6
ADC1IN7
ADC1IN8
ADC1IN9
ADC1IN10
ADC1IN11
ADC1IN12
ADC1IN13
ADC1IN14
ADC1IN15
ADC1IN16
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Altera Modular ADC IP Core Channel Name to MAX 10 Device Pin Name Mapping
Table 5-5: Altera Modular ADC IP Core Channel to Pin Mapping for Dual ADC Devices
ADC Block
First ADC
Second ADC
Channel Name
CH7
CH8
CH0
CH1
CH2
CH3
CH4
CH5
CH0
CH1
CH2
CH3
CH4
CH5
CH6
CH6
CH7
CH8
Pin Name
ANAIN1
ADC1IN1
ADC1IN2
ADC1IN3
ADC1IN4
ADC1IN5
ADC1IN6
ADC1IN7
ADC1IN8
ANAIN2
ADC2IN1
ADC2IN2
ADC2IN3
ADC2IN4
ADC2IN5
ADC2IN6
ADC2IN7
ADC2IN8
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Altera Modular Dual ADC Parameters Settings
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There are three groups of options: General, Channels, and Sequencer.
Table 5-6: Altera Modular Dual ADC Parameters - General
Parameter
Core Variant
Allowed Values
• Standard sequencer with
Avalon-MM sample storage
• Standard sequencer with
Avalon-MM sample storage and threshold violation detection
• Standard sequencer with external sample storage
• ADC control core only
Description
Selects the core configuration for the Altera Modular
Dual ADC IP core.
ADC Sample Rate 25 kHz, 50 kHz,
100 kHz, 200 kHz,
250 kHz, 500 kHz, and 1 MHz
Specifies the ADC sampling rate. The sampling rate you select affects which ADC input clock frequencies are available.
Refer to the related information for more details about the sampling rate and the required settling time.
ADC Input Clock 2 MHz, 10 MHz,
20 MHz, 40 MHz, and 80 MHz
Specifies the frequency of the PLL clock counter zero ( c0
) clock supply for the ADC core clock.
• You must configure the c0
of the first ALTPLL IP core that you instantiate to output one of the frequencies in the allowed values list.
• Connect the ALTPLL c0
output signal to the Altera
Modular Dual ADC clk_in_pll_c0 input signal.
For valid ADC sampling rate and input clock frequencies combinations, refer to the related information.
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Parameter
Reference Voltage (ADC1 or ADC2)
Allowed Values
• External
• Internal
External Reference
Voltage
Altera Modular Dual ADC Parameters Settings
5-9
Description
Specifies the source of voltage reference for the ADC:
• External—uses
ADC_VREF
pin as the voltage reference source.
• Internal—uses the on-chip 2.5 V (3.0/3.3V on voltageregulated devices) as the voltage reference source.
Specifies the voltage of
ADC_VREF
pin if you use it as reference voltage to the ADC.
Enable user created expected output file
• Dual supply devices: up to
2.5 V
• Single supply devices: up to
3.63 V
• Enabled
• Disabled
Specifies the source of output data for ADC logic simulation:
• Enabled—uses the stimulus input file you provide for each ADC channel, except the TSD channel, to simulate the output data.
• Disabled—uses fixed expected output data for all
ADC channels. This is the default setting.
For more information about user-specified ADC logic simulation output, refer to the related information.
Table 5-7: Altera Modular Dual ADC Parameters - Channels
This group of parameters is divided into two main tabs for ADC1 and ADC2. For each tab, there are several channel tabs—one for each channel, and one tab for the TSD in ADC1.
Parameter Allowed Values Description
• On
• Off
Enables the dedicated analog input pin for ADC1 or
ADC2.
Use Channel 0 or 9
(Dedicated analog input pin - ANAIN)
(CH0 tab for ADC1 or
CH9 tab for ADC2)
User created expected output file
—
Specifies user-created stimulus input file to simulate the output data for the channel.
This option is available for each enabled channel except the TSD if you select Enable user created expected
output file.
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Altera Modular Dual ADC Parameters Settings
Parameter
Use Channel
N
(Each channel in its own tab)
Allowed Values
• On
• Off
Use on-chip TSD
(TSD tab in ADC1 only)
• On
• Off
Enable Maximum threshold for Channel
N
(Each channel in its own tab)
Enable Maximum threshold for on-chip
TSD
(TSD tab)
Enter Maximum
Threshold for Channel
N
(Each channel in its own tab, including channel 0)
Enter Maximum
Threshold for on-chip
TSD
(TSD tab)
Enable Minimum threshold for Channel
N
(Each channel in its own tab, including channel 0)
• On
• Off
• On
• Off
Depends on reference voltage
• On
• Off
—
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Description
Enables the dual-function analog input, where
N
is:
• Channels 1 to 8 for ADC1
• Channels 10 to 17 for ADC2
Specifies that the IP core reads the built-in temperature sensor in ADC1.
If you turn on this option, the ADC sampling rate is up to
50 kHz when it reads the temperature measurement.
After it completes the temperature reading, the ADC sampling rate is up to 1 MHz.
Note: If you select the TSD for a sequencer slot in
ADC1, select NULL for the same sequencer slot number in ADC2.
Enables the maximum threshold feature for the channel.
This option is available only if you select the Standard
sequencer with Avalon-MM sample storage and
threshold violation detection core variant.
Enables the maximum threshold feature for the TSD.
This option is available only if you select the Standard
sequencer with Avalon-MM sample storage and
threshold violation detection core variant.
Specifies the maximum threshold value in Volts.
This setting is available only if you select the Standard
sequencer with Avalon-MM sample storage and
threshold violation detection core variant.
Specifies the maximum threshold value in Celsius.
This setting is available only if you select the Standard
sequencer with Avalon-MM sample storage and
threshold violation detection core variant.
Enables the minimum threshold feature for the channel.
This option is available only if you select the Standard
sequencer with Avalon-MM sample storage and
threshold violation detection core variant.
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Parameter
Enable Minimum threshold for on-chip
TSD
(TSD tab)
Enter Minimum
Threshold for Channel
N
(Each channel in its own tab, including channel 0)
Enter Minimum
Threshold for on-chip
TSD
(TSD tab)
Enable Prescaler for
Channel
N
•
•
Allowed Values
• On
• Off
Depends on reference voltage
—
On
Off
Altera Modular Dual ADC Parameters Settings
Description
Enables the minimum threshold feature for the TSD.
This option is available only if you select the Standard
sequencer with Avalon-MM sample storage and
threshold violation detection core variant.
Specifies the minimum threshold value in Volts.
This setting is available only if you select the Standard
sequencer with Avalon-MM sample storage and
threshold violation detection core variant.
5-11
Specifies the minimum threshold value in Celsius.
This setting is available only if you select the Standard
sequencer with Avalon-MM sample storage and
threshold violation detection core variant.
Enables the prescaler function, where
N
is:
• Channel 8 in ADC1
• Channel 17 in ADC2
Table 5-8: Altera Modular Dual ADC Parameters - Sequencer
Parameter
Number of slot used
Allowed Values
1 to 64
Description
Specifies the number of conversion sequence slots to use for both ADC1 and ADC2.
The Conversion Sequence Channels section displays the slots available for ADC1 and ADC2 according to the number of slots you select here.
Slot
N
Enabled channel number (CH
N
)
Specifies which enabled ADC channel to use for the slot in the sequence.
The selection option lists the ADC channels that you turned on in the Channels parameter group for ADC1 and ADC2.
Note: If you select the TSD for a sequencer slot in
ADC1, select NULL for the same sequencer slot number in ADC2.
•
•
Related Information
Configuration 1: Standard Sequencer with Avalon-MM Sample Storage
on page 2-12
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•
•
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•
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Mapping
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Configuration 2: Standard Sequencer with Avalon-MM Sample Storage and Threshold Violation
on page 2-13
Configuration 3: Standard Sequencer with External Sample Storage
on page 2-15
Configuration 4: ADC Control Core Only
Altera Modular ADC IP Core Channel Name to MAX 10 Device Pin Name Mapping
Altera Modular Dual ADC IP Core Channel Name to MAX 10 Device Pin Name Mapping
5-12
Valid ADC Sample Rate and Input Clock Combination
on page 5-13
User-Specified ADC Logic Simulation Output
Provides more information about using your own stimulus input file to simulate the ADC output data.
Guidelines: Board Design for Analog Input
on page 3-2
Provides more information about the sampling rate and settling time.
Each ADC channel in the Altera Modular Dual ADC IP core corresponds to different device pin name.
Table 5-9: Altera Modular Dual ADC IP Core Channel to Pin Mapping
ADC Block
ADC1
ADC2
Channel Name
CH5
CH6
CH7
CH8
CH9
CH10
CH11
CH12
CH0
CH1
CH2
CH3
CH4
CH13
CH14
CH15
CH16
CH17
Pin Name
ANAIN1
ADC1IN1
ADC1IN2
ADC1IN3
ADC1IN4
ADC1IN5
ADC1IN6
ADC1IN7
ADC1IN8
ANAIN2
ADC2IN1
ADC2IN2
ADC2IN3
ADC2IN4
ADC2IN5
ADC2IN6
ADC2IN7
ADC2IN8
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Valid ADC Sample Rate and Input Clock Combination
5-13
Each predefined ADC sampling rate supports a list of input clock frequencies. When you configure the
ALTPLL IP core to clock the ADC, use an ADC input clock frequency supported by your ADC sampling rate.
The ability to specify the ADC sampling rate allows you more design flexibility. If you are not using the maximum MAX 10 ADC sampling rate, you get a wider settling time margin.
Table 5-10: Valid Combination of ADC Sampling Rate and Input Clock
Total ADC Sampling Rate
(kHz)
1000
500
250
200
125
100
50
25
2
—
Yes
Yes
Yes
Yes
—
—
Yes
10
Yes
—
—
—
Yes
Yes
Yes
—
ADC Input Clock Frequency (MHz)
20
—
—
—
—
Yes
Yes
Yes
—
40
—
—
—
—
Yes
Yes
—
—
80
—
—
—
—
Yes
—
—
—
•
•
•
•
Related Information
Parameters Settings for Generating ALTPLL IP Core
Parameters Settings for Generating Altera Modular ADC or Altera Modular Dual ADC IP Core
on page 4-5
Altera Modular ADC Parameters Settings
on page 5-2
Altera Modular Dual ADC Parameters Settings
on page 5-8
Depending on parameter settings you specify, different signals are available for the Altera Modular ADC or Altera Modular Dual ADC IP core.
The command interface is an Avalon-ST type interface that supports a ready latency of 0.
Table 5-11: Command Interface Signals
valid
Signal Width
(Bit)
1
Description
Indication from the source port that current transfer is valid.
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Response Interface of Altera Modular ADC and Altera Modular Dual ADC
ready channel
Signal Width
(Bit)
1
5
Description
Indication from the sink port that it is ready for current transfer.
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Indicates the channel that the ADC hard block samples from for current command.
• 31—recalibration request
• 30:18—not used
• 17—temperature sensor
• 16:0—channels 16 to 0; where channel 0 is the dedicated analog input pin and channels 1 to 16 are the dual purpose analog input pins startofpacket
1
Indication from the source port that current transfer is the start of packet.
• For altera_adc_sequencer core implementation, the IP core asserts this signal during the first slot of conversion sequence data array.
• For altera_adc_control core implementation, this signal is ignored. The IP core just passes the received information back to the corresponding response interface.
endofpacket
1
Indication from the source port that current transfer is the end of packet.
• For altera_adc_sequencer core implementation, IP core asserts this signal during the final slot of conversion sequence data array.
• For altera_adc_control core implementation, this signal is ignored. The IP core just passes the received information back to the corresponding response interface.
•
•
Related Information
Altera Modular ADC IP Core Channel Name to MAX 10 Device Pin Name Mapping
5-12
Altera Modular Dual ADC IP Core Channel Name to MAX 10 Device Pin Name Mapping
The response interface is an Avalon-ST type interface that does not support backpressure. To avoid overflow condition at the source port, implement sink ports with response data process time that is fast enough, or with enough buffers storage.
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Threshold Interface of Altera Modular ADC and Altera Modular Dual ADC
Table 5-12: Response Interface Signals
Signal Description
valid channel
Width
(Bit)
1
5
Indication from the source port that current transfer is valid.
5-15
Indicates the ADC channel to which the ADC sampling data corresponds for the current response.
• 31:18—not used
• 17—temperature sensor
• 16:0—channels 16 to 0; where channel 0 is the dedicated analog input pin and channels 1 to 16 are the dual purpose analog input pins data startofpacket endofpacket
12 or 24 ADC sampling data:
• 12 bit width for Altera Modular ADC
• 24 bit width for Altera Modular Dual ADC
1
Indication from the source port that current transfer is the start of packet.
For altera_adc_control core implementation, the source of this signal is from the corresponding command interface.
1
Indication from the source port that current transfer is the end of packet.
For altera_adc_control core implementation, the source of this signal is from the corresponding command interface.
The threshold interface is an Avalon-ST type interface that does not support backpressure.
Table 5-13: Threshold Interface Signals
valid channel
Signal Width
(Bit)
1
5
Description
Indication from the source port that current transfer is valid.
Indicates the ADC channel for which the threshold value has been violated.
• 31:18—not used
• 17—temperature sensor
• 16:0—channels 16 to 0; where channel 0 is the dedicated analog input pin and channels 1 to 16 are the dual purpose analog input pins
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data
CSR Interface of Altera Modular ADC and Altera Modular Dual ADC
Signal Width
(Bit)
1
Description
Indicates the type of threshold violation:
• 1—Exceeds maximum threshold value
• 0—Below minimum threshold value
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•
•
Related Information
Altera Modular ADC IP Core Channel Name to MAX 10 Device Pin Name Mapping
Altera Modular Dual ADC IP Core Channel Name to MAX 10 Device Pin Name Mapping
5-12
The CSR interface is an Avalon-MM slave interface.
Table 5-14: CSR Interface Signals
Signal
address
Width
(Bit)
Description
1 or 7 Avalon-MM address bus. The address bus width is in the unit of word addressing:
• altera_adc_sample_store core—address width is seven
• altera_adc_sequencer core—address width is one read
1
Avalon-MM read request.
write
1
Avalon-MM write request.
writedata
32
Avalon-MM write data bus.
readdata
32
Avalon-MM read data bus.
The IRQ interface is an interrupt interface type.
Table 5-15: IRQ Interface Signals
Signal
irq
Width
(Bit)
1 Interrupt request.
Description
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Peripheral Clock Interface of Altera Modular ADC and Altera Modular Dual ADC
The peripheral clock interface is a clock sink interface type.
5-17
Table 5-16: Peripheral Clock Interface Signals
clock
Signal Width
(Bit)
1
Description
Single clock that clocks all Altera Modular ADC or Altera Modular
Dual ADC micro cores.
The peripheral reset interface is a reset sink interface type.
Table 5-17: Peripheral Reset Interface Signals
reset_n
Signal Width
(Bit)
1
Description
Single reset source that that resets all Altera Modular ADC or Altera
Modular Dual ADC micro cores.
The ADC PLL clock interface is a clock sink interface type.
Table 5-18: ADC PLL Clock Interface Signals
clock
Signal Width
(Bit)
1
Description
ADC hard IP clock source from
C0
output of dedicated PLL1 or
PLL3.
Export this interface from the Qsys system.
•
•
•
•
Related Information
Customizing and Generating Altera Modular ADC IP Core
on page 4-3
Parameters Settings for Generating ALTPLL IP Core
PLL Locations, MAX 10 Clocking and PLL User Guide
Provides more information about the availability of PLL3 in different MAX 10 devices and packages.
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ADC PLL Locked Interface of Altera Modular ADC and Altera Modular Dual ADC
The ADC PLL locked interface is a conduit end interface type.
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Table 5-19: ADC PLL Locked Interface Signals
conduit
Signal Width
(Bit)
1
Description
ADC hard IP locked signal output of dedicated PLL1 or PLL3.
Export this interface from the Qsys system.
•
•
•
•
Related Information
Customizing and Generating Altera Modular ADC IP Core
Parameters Settings for Generating ALTPLL IP Core
PLL Locations, MAX 10 Clocking and PLL User Guide
on page 4-3
Provides more information about the availability of PLL3 in different MAX 10 devices and packages.
The registers in the generated Altera Modular ADC IP core provide the IP core with the control and settings during operation.
Table 5-20: Command Register (CMD)
Address Offset:
0x0
Bit
31:4
3:1
Name
Reserved
Mode
Attribute Description
Read Reserved
Read-Write Indicates the operation mode of the sequencer core.
These bits are ignored when the run bit (bit 0) is set.
In continuous conversion, the data will be overwritten after a complete sampling sequence.
Value
—
• 7—Recalibrate the
ADC
• 6 to 2—Reserved
• 1—Single cycle ADC conversion
• 0—Continuous ADC conversion
Default
0
0
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Bit
0
Name
Run
Attribute Description
Read-Write Use this control bit to trigger the sequencer core operation.
The Altera Modular ADC IP core waits until the sequencer core completes its current operation before writing to this register bit.
Sample Storage Core Registers
Value
• 1—Run
• 0—Stop
5-19
Default
0
Related Information
on page 2-19
Table 5-21: ADC Sample Register (ADC_SAMPLE) of Altera Modular ADC
Address Offset:
0x3F
(slot 63)—
0x0
(slot 0)
Bit
31:12
Name
Reserved
Attribute
Read
Description
11:0 Sample Read
Reserved
The data sampled by the ADC for the corresponding slot.
Value
—
Sampled data
Table 5-22: ADC Sample Register (ADC_SAMPLE) of Altera Modular Dual ADC
Address Offset:
0x3F
(slot 63)—
0x0
(slot 0)
Bit
31:28
27:16
15:12
11:0
Name
Reserved
Sample
Reserved
Sample
Attribute
Read
Read
Read
Read
Description
Reserved
The data sampled by ADC2 for the corresponding slot.
Reserved
The data sampled by ADC1 for the corresponding slot.
Value
—
Sampled data
—
Sampled data
Default
0
0
Default
0
0
0
0
Table 5-23: Interrupt Enable Register (IER)
Address Offset:
0x40
Clear the enable bit to prevent the corresponding interrupt status bit from causing interrupt output assertion (IRQ). The enable bit does not stop the interrupt status bit value from showing in the interrupt status register (ISR).
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Bit
31:1
0
ADC HAL Device Driver for Nios II Gen 2
Name
Reserved
M_EOP
Attribute Description
Read Reserved
Read-Write The enable bit for the end of packet
(EOP) interrupt.
Value
—
• 1—Enables the corresponding interrupt
• 0—Disables the corresponding interrupt
Table 5-24: Interrupt Status Register (ISR)
Address Offset:
0x41
Bit
31:1
0
Name
Reserved
EOP
Attribute
Read
Read-Write
(one cycle)
Description
Reserved
EOP interrupt.
Value
—
• 1—Indicates complete receipt of a sample block
• 0—Automatically clears to 0 after indication of complete receipt
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Default
0
1
Default
0
0
Related Information
•
•
•
•
The Altera Modular ADC IP core provides a HAL device driver. You can integrate the device driver into the HAL system library for Nios II Gen 2 systems.
The Altera Modular ADC IP core provides software files that define low-level access to the hardware. You can use the macros definition and functions in the software files to initialize the Altera Modular ADC core.
altera_modular_adc_sequencer_regs.h
—this file defines the register map for the sequencer core. It provides symbolic constants to access the low-level hardware.
altera_modular_adc_sample_store_regs.h
—this file defines the register for sample storage core. It provides symbolic constants to access the low-level hardware.
altera_modular_adc.h
—include this file into your application. It automatically includes the other header files and defines additional functions.
altera_modular_adc.c
—this file implements helper functions that are defined in the header file.
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ADC HAL Device Driver for Nios II Gen 2
Related Information
HAL API Reference, Nios II Gen 2 Software Developer's Handbook
Provides more information about the HAL API.
5-21
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If an IP core version is not listed, the user guide for the previous IP core version applies.
IP Core Version User Guide
16.0
15.1
15.0
MAX 10 Analog to Digital Converter User Guide
MAX 10 Analog to Digital Converter User Guide
MAX 10 Analog to Digital Converter User Guide
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2016 Intel Corporation. All rights reserved. Intel, the Intel logo, Altera, Arria, Cyclone, Enpirion, MAX, Megacore, NIOS, Quartus and Stratix words and logos are trademarks of Intel Corporation in the US and/or other countries. Other marks and brands may be claimed as the property of others. Intel warrants performance of its FPGA and semiconductor products to current specifications in accordance with Intel's standard warranty, but reserves the right to make changes to any products and services at any time without notice. Intel assumes no responsibility or liability arising out of the application or use of any information, product, or service described herein except as expressly agreed to in writing by Intel. Intel customers are advised to obtain the latest version of device specifications before relying on any published information and before placing orders for products or services.
www.altera.com
101 Innovation Drive, San Jose, CA 95134
ISO
9001:2008
Registered
2016.10.31
UG-M10ADC
Date
October 2016
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Version Changes
2016.10.31 • Updated the topic about the ADC voltage reference to specify that you must use clean external voltage reference with a maximum resistance of 100 Ω.
• Updated the topic about the ADC sequencer to clarify that
"conversion mode" refers to the sequencer conversion mode, namely the single-cycle and continuous ADC conversion modes.
• Added a related information link to a topic in the
MAX 10 Clocking and PLL User Guide
that lists the availability of PLL1 and PLL3 in different MAX 10 devices and packages.
• Updated various topics throughout the user guide to improve the clarity of descriptions related to the user-specified ADC logic simulation output feature.
• Updated the
VCCVREF
pin name to
ADC_VREF
.
• Edited the board design guidelines for analog input:
• Updated text to improve clarity.
• Updated the F cutoff @ -3dB
recommendation from "five times" to
"at least two times" the input frequency.
• Updated the figure showing the first order active low pass filter example.
B
©
2016 Intel Corporation. All rights reserved. Intel, the Intel logo, Altera, Arria, Cyclone, Enpirion, MAX, Megacore, NIOS, Quartus and Stratix words and logos are trademarks of Intel Corporation in the US and/or other countries. Other marks and brands may be claimed as the property of others. Intel warrants performance of its FPGA and semiconductor products to current specifications in accordance with Intel's standard warranty, but reserves the right to make changes to any products and services at any time without notice. Intel assumes no responsibility or liability arising out of the application or use of any information, product, or service described herein except as expressly agreed to in writing by Intel. Intel customers are advised to obtain the latest version of device specifications before relying on any published information and before placing orders for products or services.
www.altera.com
101 Innovation Drive, San Jose, CA 95134
ISO
9001:2008
Registered
B-2
Document Revision History for MAX 10 Analog to Digital Converter User Guide
Date
May 2016
November 2015
June 2015
May 2015
UG-M10ADC
2016.10.31
Version Changes
2016.05.02 • Removed all preliminary marks.
• Added new function to specify