TSync Time Code Processors

TSync Time Code Processors
product brief
TSync Time Code Processors
Form Factors
Available References
Timing Functions
• PCIe, cPCI, PCI-104, PMC, VPX
• Others available upon request
• Rugged design
• Conduction-cooled ready
• Conformal coating available
• GNSS synchronization
(multi-constellation)
• SAASM GPS option
• IRIG timecode
• 1PPS
• Internal clock
• IRIG timecode generator
• 1PPS and programmable
periodic output
• 10 MHz output
• Event time-tagging
• Time-match/alarm signal
Spectracom TSync time code processors are complete synchronization systems on circuit cards ready for easy integration into
mission critical applications.
Each board has an onboard clock/oscillator that can phase-lock
to a wide variety of external timing references and provides
5 ns resolution to the time-keeping hardware. The user can
prioritize multiple references so if one is lost the unit will
automatically switch to the next. The oscillator can
be its own reference when it “freewheels” in the
absence of a valid external synchronization source.
For applications where accuracy in this “holdover”
conditional is essential, an upgrade to a higher
precision ovenized crystal oscillator (OCXO) is available.
Spectracom TSync boards offer a high degree of ruggedness,
customization and field upgradeability. If a new application
or change in deployment requires a different feature set,
we can usually accommodate it.
Four user-programmable time tag inputs may be used for multiple event capture at 10,000 events per second. Additionally,
four programmable time match outputs are provided. Key to the
TSync functionality is the ability to generate interrupts. Using a
Spectracom driver package available for the latest versions of
popular operating systems, you may configure your board using
interrupt-driven algorithms to support your unique applications.
spectracom.com
Some models are conduction-cooled
ready with a thermal frame option
TSync Time Code Processors Technical Specifications
Internal Time-Keeping
Disciplined On-board Clock
•Frequency: 200 MHz
•Resolution: 5 ns
•Sync Sources: GNSS, IRIG, 1 PPS inputs
Reference Inputs
GNSS Reference
•Frequency: GPS L1 (1575.42 MHz),
GLONASS L1 (1602 MHz); contact the
factory for compatibility with QZSS
(1572.42 MHz), BeiDou (1561.1 MHz)
and Galileo (1575.42 MHz)
Internal GNSS Receiver Option
•Front Panel Connector: SMA jack
(+5 V at 30 mA max supplied to
power antenna pre-amp)
•Antenna sold separately
•SMA to Type N adapter cable included
External GNSS Receiver/Antenna Option
(PCIe and cPCI Only)
•Size: 45 mm dia., 72.55 mm H
(3.74” dia., 2.85” H)
•Pole mount included
•Operating Temperature: -40°C
to 85°C (-40°F to +185°F)
•Cable: 30.5 M (100’) included, 92 M
(300’) max., 9 mm (0.35”dia.);
Connectors: 20 mm (0.79”) at
antenna end, DB15 at board end,
with adapter cable
SAASM GPS Receiver Option (cPCI and
VPX Only)
•Antenna sold separately
•SMA to Type N adapter cable included
with convection cooled models
•See table for specs
IRIG
Code Format (AM or DCLS)
IRIG A, IRIG B, IRIG G, NASA36 (autodetect), IEEE 1344/C37.118 (selectable)
AM
•Amplitude: 500 mV p-p min,10 V p-p max
•Modulation Ratio: 2:1 min, 6:1 max
•Input Impedance: >10 K Ohms
•Common Mode Voltage: ±150 V DC max
•Input Stability: Better than 100 ppm
DCLS (Differential or Single Ended)
•Differential Amplitude: 200 mV p-p min,
5 V p-p max - 7V to +12 V DC max
common mode voltage (RS-485
compatible)
•Single Ended Amplitude: +1.3V VIL min,
+2 V VIH max (TTL compatible)
1PPS Input
•Amplitude: 0 V to +5.5 V, +0.8 V VIL,
+2.0 V VIH
•1 Hz Pulse, Rising Edge or Falling
Edge Active (selectable)
•100 ns minimum pulse width
•Input Impedence: <150 pF capacitive
Internal SAASM GPS Reference (cPCI and VPX Only):
Value
SAASM GPS
Receiver
MPE-S Type II GB-GRAM
Frequency
L1 (1575.42 MHz) and L2
(1227.6 MHz) simultaneous
L1- C/A, P(Y)
L2 - P(Y)
Satellite Tracking
1 to 12
TTFF - Time to First
Fix (Synchronization
Time)
Cold Start (with almanac download):
15 minutes
Cold Start (no almanac download):
5 minutes
Warm Start: 90 seconds
Hot Start: 10 seconds
TTSF - Time to
Subsequent Fix
(Reacquisition Time)
< 20 seconds, Off or Stby < 15 minutes
< 25 seconds, Off or Stby < 60 minutes
< 70 seconds, Off < 60 minutes
Antenna Connector
Convection Cooled: SMA Jack
(+3.3 V @ 9 mA to 60 mA)
Conduction Cooled: MMCX Jack
(+3.3 V @ 9 mA to 60 mA)
1 PPS Accuracy
±100 ns
Key Fill
DS102 standard, DS101 optional
Backup Battery
SAASM I/O connector or P1-VBAT, VPX
P1 connector
General Inputs (x4)
Event Time-Tag Input
•Amplitude: 0 V to +5.5 V, +0.8 V VIL,
+2.0 V VIH
•Polarity (selectable): Positive or negative
•Pulse Width: 50 ns min
•Repetition Rate: More than 10,000
events per second
•Resolution: 5 ns
Outputs
IRIG
Code Format (AM or DCLS)
IRIG A, IRIG B, IRIG E, IRIG G, NASA36,
IEEE 1344
AM
•Amplitude (adjustable): 500 mV
p-p min, 6 V p-p max into 50 ohms
•Modulation Ratio: 3:1
•Output Impedance: 50 Ohms
DCLS
•Differential Amplitude: 1.5 V p-p min,
3.3V p-p max, ±1.5 V min,1.8 V max
common mode voltage (RS-485 compatible)
•Single Ended Amplitude: (100 Ohm Load)
+0.5V VOL max, +2.5 V VOH min (TTL
compatible)
1PPS
•Signal Level: TTL compatible, 4.3 V
minimum, base-to-peak into 50 (for PCIe
only: TTL compatible, 2.2 V minimum,
base-to-peak into high impedance)
•Pulse Width: Configurable Pulse width
(200 ms by default)
•Rise Time:< 10 ns
•Accuracy: See table
1 PPS Output:
Accuracy to UTC
(1-sigma locked to GPS)
TCXO
OCXO
OCXO
Rugged Option
(cPCI & VPX only)
±50 ns
±50 ns
±25 ns
Holdover (constant temp after 2 weeks of GPS lock)
After 4 hours
12 μs
3 μs
1 μs
After 24 hours
450 μs
100 μs
25 μs
TCXO
OCXO
OCXO
Rugged Option
(cPCI & VPX only)
Accuracy
(average over 24 hours
when GPS locked)
1x10-11
5x10-12
2x10-12
Medium Term
Stability
(without GPS after
2 weeks of GPS lock)
1x10-8/
day
2x10-9/
day
5x10-10/day
@1 Hz
—
-90
—
@10 Hz
—
-113
-120
@100 Hz
-110
-120
-135
@1 KHz
-135
-140
-135
@10 KHz
-140
-150
-145
10 MHz Frequency Output:
General Outputs (x4)
Periodic Output
•Amplitude: TTL compatible, 4.3 V
minimum, base-to-peak into 50 (for PCIe
only: TTL compatible, 2.2 V minimum,
base-to-peak into high impedance)
•Period: 100 ns min, 60 s max in 20 ns
steps (10 MHz – 0.17 Hz)
•Pulse Width: 20 ns min, 999 ms max
in 20 ns steps
•Polarity (selectable): Positive or negative
Phase Noise (dBc/Hz)
Signal Waveform & Levels: +13 dBm ±3 dB into 50 ohm, BNC
TSync Time Code Processors Technical Specifications
Technical Specifications: TSync
PCI-104 Specifications
Time-Match/Alarm Output
•Amplitude: TTL compatible, 4.3
•Compliant to PCI-104
PCI-104Specifi
spec,cations
rev 1.1
• Amplitude: TTL compatible, 4.3 V
• Compliant to PCI-104 spec, rev 1.1
minimum, base-to-peak into Time-Match/Alarm
50
Output
PCI-104
Specifi
cations
•Compliant
PCI
spec,
rev
2.2
minimum, base-to-peak
into 50  to •
Compliant to PCI spec, rev 2.2
• 2.2
Amplitude:
4.3
V
•
Compliant
to
PCI-104
spec,
rev 1.1
•2.2 V minimum, base-to-peakTime-Match/Alarm
intoV minimum,
highTTL compatible,
base-to-peak
into
Output
•
DIP
switch
selectable
PCI-104
PCI-104
Specifi
cations
•DIP
PCI-104
stack
level
minimum,
base-to-peak
intoswitch
50
V selectable
•
Compliant
PCI spec,
revrev
2.21.1
high
impedance)
•
Amplitude:
TTL
compatible,
4.3
level
Time-Match/Alarm Output
• stack
Compliant
totoPCI-104
spec,
impedance)
PCI-104
Specifi
cations
2.2 V minimum,
base-to-peak
into •
•Universal
DIP
switch selectable
PCI-104
•
Signaling
Voltage
•
100
days
inB5us
ns Interface:
steps
minimum,
base-to-peak
into
50
Bus
Interface:
Universal
Signaling
• Range:
Amplitude:
TTL
compatible,
4.3V
Compliant
toPCI-104
PCI
spec,
revrev
2.21.1
•
Compliant
to
spec,
•Range: 100 days in 5 ns steps minimum,
highVimpedance)
stack
level
2.2
base-to-peak
into
3.3
V
3.3selectable
V/5
base-to-peak
intoV/5
50 
DIP switch
PCI-104
• Voltage
Compliant
to
PCIV spec,
rev 2.2
10
MHzminimum,
Output
(Sine
Wave)
• high
Range:
100
days
in
5
ns
steps
•
Bus
Interface:
Universal
Signaling
•
Speed:
32bit
address
@
stack
level selectable
minimum,
into 32bit
2.2 Vimpedance)
• Bus
DIP
switch
PCI-104
•Bus
Speed:
address
@ V33/66
MHz
10 MHz Output (Sine Wave) •• Harmonics:
< -40base-to-peak
dBc
Voltage
3.3 V/5
Range:
100 days
in 5Wave)
ns steps
MHz
• 33/66
Bus Interface:
Universal Signaling
high
impedance)
10Spurious:
MHz
Output
(Sine
stack
level
•
< -70 dBc
•Harmonics: < -40 dBc
•
Bus
Speed:
32bit
address
@
• Range:
100 <days
in 5 ns steps
Voltage
3.3 V/5
V VPX
Harmonics:
-40
dBc
• Bus
Interface:
Universal
Signaling
Conduction
(cPCI
and
only)
•
cations:
See table Cooling
10Other
MHzspecifi
Output
(Sine
Wave)
33/66
MHz
Conduction
Cooling
(cPCI and
• Voltage
Bus Speed:
32bit
address
@
•Spurious: < -70 dBc
•
Spurious:
<
-70
dBc
3.3
V/5
V
• Harmonics:
< -40
dBcWave)
•Per
ANSI/VITA 30.1-2002 (cPCI)
10
MHz LVDS
Output
(Sine
10
MHz
Clocks
viaSee
P2
33/66
MHz32bit address @
VPX
only)
Other
specifi
cations:
table
•
Bus
Speed:
Spurious:
< -70
dBc
•Other specifications: See table•• Harmonics:
Conduction
Cooling
(cPCI
and
< -40
dBc
•Per VITA 46/IEEE
1101.2
33/66
MHz(VPX)
Connector
(VPX
only)
• Per
30.1-2002 (cPCI)
Other
cations:
See
•
< -70
dBc via
10Spurious:
MHzspecifi
LVDS
Clocks
P2table
VPX ANSI/VITA
only) Cooling
(cPCI and
•
Four
(4)specifi
LVDScations:
differential
pairs
Per
VITA 46/IEEE
1101.2
(VPX)
•Thermal
frame•Conduction
available
by request
10 MHz LVDS Clocks via P2 Connector
•
Other
See
table
Connector
(VPX
only)
•
Per
ANSI/VITA
30.1-2002
(cPCI)
10
MHz LVDS
Clocks
via P2
Conduction
Cooling
(cPCIbyand
VPX
only)
•
Impedance:
100
ohm
• Thermal frame available
request
(VPX only)
•
C
omponent
elevations
available
for
•
Four
(4)
LVDS
differential
pairs
•
Per
VITA
46/IEEE
1101.2
(VPX)
10
MHz
LVDS
Clocks
via
P2
•
Duty
Cycle:
50%
Connector (VPX only)
VPX
•
Component
elevations
available
Per only)
ANSI/VITA
30.1-2002
(cPCI)
•Four (4) LVDS differential pairs•• Rise
Impedance:
• Thermal
available
bydesign
request
custom
frame
design
<100
10
nsohm
Four Time:
(4) LVDS
differential
pairsthermal
thermal
frame
VITAframe
46/IEEE
1101.2
(VPX)
Connector
(VPX
only)
• for
Per custom
ANSI/VITA
30.1-2002
(cPCI)
•
Duty
Cycle:
50%
•
Component
elevations
available
Impedance:
ohm
•Impedance: 100 ohm
Thermal
available
by request
• Four
(4) LVDS100
differential
pairs
• Per
VITAframe
46/IEEE
1101.2
(VPX)
Power
• Rise
10 nsPower
for
custom thermal
frame design
General
Duty Time:
Cycle:<100
50%
Component
elevations
• Impedance:
ohm
• Thermal
frame
available available
by request
•Duty Cycle: 50%
See
table
below.
See
table
below.
PCIe
cations
10 ns
RiseSpecifi
Time:
<50%
for custom thermal
frame
design
•
Duty
Cycle:
•
Component
elevations
available
Power
General
•Rise Time: < 10 ns
• Rise
Full-height
Time: mounting
< 10 ns bracket
fortable
custom
thermal frame design
See
below.
Power
Environmental
PCIe
Specifi
cations
Environmental
General
provided
Temperature
•
Full-height
mounting
bracket
Power
See table below.
General
General
•
Bus
Interface:
Low-profi
le PCIe
PCIe
Specifi
cations
Environmental
Temperature
•
Operating:
-40°C to 80°C (-40°F
provided
See
table below.
• x1,
Full-height
mounting bracket
Rev 1.1
PCIe
Specifi
cations
Temperature
PCIe Specifications
to to
+176°F)
card edge
with
•
O
perating:
80°Cat(-40°F
to +176°F)
• provided
Bus Interface: Low-profi
le PCIe -40°C
Environmental
• Full-height mounting bracket
•
Operating:
-40°C to
80°C (-40°F
conduction
cooled
frame
cations
Temperature
x1,
Rev
1.1
Environmental
•Full-height mounting bracketPMC
at card
edge with
conduction
cooled
frame
•provided
BusSpecifi
Interface:
Low-profi
le PCIe
provided
to
+176°F)
at
card
edge
with
•
Storage:
-40°C
to 85°C
(-40°F
to
• Single Size CMC (Common mezOperating:
-40°C
to 80°C
(-40°F
Temperature
x1,
Rev
1.1
•
Bus
Interface:
Low-profile PCIe -40°C
•Bus Interface: Low-profi le PCIe
x1,Specifi
Rev
1.1
conduction
cooled
frame
PMC
cations
to
85°C
(-40°F
to
+185°F)
+185°F)
mm x 74 mm
zanine
Card)
149•Storage:
to
+176°F)
at
card
edge
with
• Operating: -40°C to 80°C (-40°F
x1,
Rev
1.1
• conduction
Storage: -40°C
to 85°C (-40°F to
•
Single
Sizecations
CMC
(Common
mez•
Bus
Interface:
Universal
Signaling
cooled
PMC
Specifi
to +176°F) at
card frame
edge with
Humidity
PMC Specifications
Humidity
+185°F) -40°C to 85°C (-40°F to
mm x 74 mm
zanine Size
Card)
149
• Operating
Storage:
3.3cations
V/5
V (Common
• Voltage
Single
CMC
mezconduction
frame
PMC
Specifi
•
&cooled
Storage:
95% RH at
• Bus
Bus
Interface:
Universal
Signaling
•Single Size CMC (Common mezzanine
•
O
perating
&
Storage:
95%
RH
athours/
60°C
Humidity
+185°F)
•
Speed:
32bit
address
@
mm
x
74
mm
zanine
Card)
149
• 60°C
Storage:
(-40°F
to
Single Size CMC (Common mezfor 5-40°C
cycles to
of 85°C
48
cycle
Voltage
3.3 V/5
V for Signaling
•
Operating
&
Storage:
95% RH at
Card) 149 mm x 74 mm
MHz
• 33/66
Bus
Interface:
Universal
5
cycles
of
48
hours/
cycle
+185°F)
zanine Card) 149 mm x 74 mm
Humidity
Physical
• Voltage
Bus Speed:
32bit
address
@
60°C
for
5
cycles
of
48
hours/
cycle
3.3 V/5
V
• Bus Interface:
Universal
Signaling
• Operating
& Storage:
95% RH at
Humidity
Weight
(base
configurations)
•Bus Interface: Universal Signaling
Voltage
cPCI
Specifi
cations
33/66
MHz
Physical
• Voltage
Bus Speed:
32bit
address @
Physical
3.3 V/5
60°C for
cycles
ofg48 hours/
cycle
Operating
& Storage:
95% RH
at
•
PCIe:
4.35oz/122
• 3U
Compact
PCI V(cPCI) Compliant
3.3 V/5 V
33/66
MHz
Weight
(base
•
Bus
Speed:
32bit Weight
address @
cPCI
Specifi
cations
60°C for
5 oz/88
cyclesconfi
ofg 48gurations)
hours/ cycle
•
PMC:
3.1
Physical
to PICMG
2.0
r3.0 100 mm x(base configurations)
• cPCI:
PCIe: 6.1
4.3
oz/122
•Bus Speed: 32bit address @ 33/66
MHz
33/66
MHz PCI (cPCI) Compliant
•
3U Specifi
Compact
•
oz/173
gg (without
Weight
(base
confi
gurations)
Physical
mm (3U
card •PCIe:
size)
160
cPCI
cations
4.3 oz/122
g 3.1
• thermo
PMC:
oz/88 gg oz/323 g
to
2.0PCI
r3.0
100Compliant
mm x
frame),11.4
•
PCIe:
4.3
oz/122
Weight
(base
configurations)
•
Bus
Interface:
Universal
Signaling
3UPICMG
Compact
(cPCI)
cPCI
Specifi
cations
cPCI Specifications
• (with
cPCI:
6.1
(without
•PMC:
oz/88
g thermo
160
mm3.3
(3U
card
size)
frame)
•
PMC:
3.1oz/173
oz/88
gg
PCIe:
4.3
oz/122
g
V/5
V(cPCI)
to
PICMG
2.0
r3.0
100Compliant
mm 3.1
x
• Voltage
3U
Compact
PCI
thermo
frame),11.4
oz/323
•3U Compact PCI (cPCI) Compliant
to 32bit
• Bus
Bus Speed:
Interface:
Universal
Signaling
•
6.3
cPCI:
6.1
oz/173
(without g
• VPX:
PMC:
3.1oz/179
oz/88thermo
ggg(without
•
address
160
mm (3U
size)
cPCI:
6.1
g
(without
to
PICMG
2.0card
r3.0•
100
mm@
x oz/173
(with thermo
frame)oz/329
V
Voltage
3.3 V/5
thermo
frame),1.6
gg
frame),11.4
oz/323
PICMG 2.0 r3.0 100 mm x 160
mm
(3U
•
cPCI:
6.1
oz/173
g
(without
• 33/66
Bus
Interface:
Universal
Signaling
160
mmMHz
(3U card
size)
frame),11.4
oz/323
g (with
thermo
frame)
• (with
VPX: thermo
6.3
oz/179
g (without
• Bus
Speed:
32bitV address
@
frame)
thermo
frame),11.4
oz/323 g
Voltage
3.3 V/5
card size)
• Bus
Interface:
Universal Signaling
thermo
frame),1.6
g
VPX
Specifi
cations
• PCI-104:
3.4frame)
oz/96
g
33/66
MHz
•VPX: 6.3
g (without
thermo
VPX:
6.3
oz/179
goz/329
(without
(with
thermo
• Voltage
Bus Speed:
32bit
@ oz/179
3.3 V/5
V address
(with thermo
frame)oz/329 g
•Bus Interface: Universal Signaling
Voltage
• 3U
VPX
form-factor
Compliant to
thermo
frame),1.6
•
VPX:
6.3
oz/179
g
(without
frame),11.6
oz/329
g
(with
thermo
frame)
33/66
MHz
•
Bus
Speed:
32bit
address
@
Safety
&
EMI
VPX
Specifications
• PCI-104:
3.4frame)
oz/96 g
VITA-46
(with thermo
3.3 V/5 V
thermo
frame),1.6
g
MHz
33/66
Certifi
cations:
RoHS,oz/329
CE, FCC
•
3U VPX
form-factor
Compliant
•PCI-104:
g
•
3.9”
x 6.3”
(100 mm
x 160 mm)to 3.4 oz/96
VPX
Specifi
cations
•
PCI-104:
3.4frame)
oz/96 g
(with
thermo
Safety
&
EMI
Class
A
•Bus Speed: 32bit address @ 33/66
MHz
VITA-46
•Connectors
to
VITA
46.0
for
P0,
•
3U
VPX
form-factor
Compliant
to
VPX Specifications
•
PCI-104:
3.4RoHS,
oz/96CE,
g FCC
Certifi
cations:
• VITA-46
3.9”and
x 6.3”
x 160 mm)
Safety
& EMI
Safety
& EMI Drivers
P2 (100 mm
• P1,
3U VPX
form-factor
Compliant to
Class
A
VPX Specifications
•Connectors
to PCIe
VITA
46.0
for
P0,
Certifications:
RoHS,
CE,A
FCC
Safety
&
EMI
•
Bus
Interface:
x1,
Rev
1.1
Certifications:
RoHS,
CE,
FCC
Class
3.9”
x
6.3”
(100
mm
x
160
mm)
VITA-46
Linux* 64/32 bit, Windows 7
P1,
and P2 to VITA 46.0 for P0,
Class
A
•3U VPX form-factor Compliant
to VITA-46
Certifi
cations:
RoHS, Embedded
CE, FCC
Drivers
•Connectors
64/32
bit, Windows
•
3.9” x 6.3” (100
mm x 160 mm)
• P1,
Bus and
Interface:
PCIe
x1, Rev 1.1
Class
A64/32 bit, Windows 7
Drivers
Linux*
P2 to VITA
•Connectors
46.0 for P0,
•3.9” x 6.3” (100 mm x 160 mm)
Drivers
*Contact
sales for specific kernel versions
64/32
bit, Windows
Embedded
• P1,
Bus and
Interface:
x1, Rev64/32
1.1 bit,
Linux*
Windows
7 64/32
bit,
P2 PCIe
Linux*
64/32
bit,
Windows
7
Drivers
•Connectors to VITA 46.0 for P0, P1, and P2
*Contact
sales
for bit,
specifi
c kernel
versions
• Bus Interface: PCIe
x1, Rev 1.1
64/3264/32
bit, Windows
Embedded
Windows
Embedded
Linux*
Windows
7
Power:
•Bus Interface: PCIe x1, Rev 1.1
*Contact
sales
for specific kernel
versions
64/32
bit,versions
Windows
Embedded
*Contact sales for specific
kernel
Time-Match/Alarm Output
*Contact sales for specific kernel versions
+5 VDC
Power:
Power:
Power:
PCIe
Power:
PMC
PCIe
+5 VDC
PCIe
cPCI
PCIe
PMC
PCIe
PCI-104
PMC
—
cPCI
PMC
VPX
cPCI
PCI-104
PMC
cPCI
±5% @
1.4A typ
PCI-104
VPX
cPCI
±5% @
1.4A typ
VPX
PCI-104
VPX
PCI-104
VPX
±5% @ 1.4A typ
+5—
VDC
VDC typ
±5%+5
@—
1.4A
+3.3 VDC
+5 VDC
±5%
1.4A
±5% @
@—
1.4A typ
typ
—
±5%
±5% @
@ 1.4A
1.4A typ
typ±5% @ 0.7A typ
±5% @ 1.4A typ
Vs3: +5%/-2.5%
±5% @ 1.4A typ
@ 0.4A typical TCXO, OCXO options
±5%
1.4A
±5% @ 0.7A
±5% @
@OCXO
1.4A typ
typ
Vs3: +5%/-2.5%
@ 0.6A typical
rugged
option
0.4A maximum
typical TCXO,
OCXO
options
@ 1.4A
rugged
OCXO
option warm-up
±5%
@
1.4A
typ
Vs3: +5%/-2.5%
@ 0.6A typical rugged OCXO option
@ 0.4A typical
TCXO, OCXO options
0.7A
Vs3: +5%/-2.5%
@ 1.4A maximum
rugged OCXO±5%
option @
warm-up
@ 0.4A
0.6A typical
typical TCXO,
rugged OCXO
OCXO options
option
@
@ 0.6A
1.4A typical
maximum
rugged
OCXO
option warm-up
@
rugged
OCXO
option
@ 1.4A maximum rugged OCXO±5%
option @
warm-up
0.7A
Vs3: +5%/-2.5%
@ 0.4A typical TCXO, OCXO options
@ 0.6A typical rugged OCXO option
@ 1.4A maximum rugged OCXO option warm-up
Technical Specifications: TSync
Timing Board Use Cases
Timing Board Use Cases Technical Specifications: TSync
Timing Board Use Cases Technical Specifications: TSync
Timing Board Use Cases
Timing Board Use Cases
NTP Server
NTP Server
NTP Server
NTP Server
GPS
SERV
NTPd
SERV
NTPd
NTP
NTPd
NTPd
NTP
SERV
SERV
GPS
GPS
GPS
NTP
NTP
IRIG Timecode
IRIG Timecode
IRIG Timecode
IRIG Timecode
Time-Sensitive Application Server
Time-Sensitive Application Server
GPS
User Server
Software
Time-Sensitive Application
Time-Sensitive Application Server
SERV
GPS
User Software
Precise Timestamps
and Interrupts
User Software
Precise Timestamps
User Software
and Interrupts
Precise Timestamps
and Interrupts
Precise
Timestamps
Embedded Master Clock
and Interrupts
SERV
GPS
GPS
SERV
SERV
IRIG Timecode
IRIG Timecode
IRIG Timecode
IRIG Timecode
Embedded Master Clock
Embedded Master Clock
Embedded Master Clock
Software Control
GPS
Software Control
GPS
Software Control
Software Control
Timestamping External Data
Timestamping External Data
Timestamping External Data
Timestamping External Data
Physical Synchronization
Signals
Physical Synchronization
Signals
Physical Synchronization
Signals
Physical Synchronization
Signals
GPS
GPS
User Software
GPS
User Software
GPS
User Software
User Software
External Events
IRIG Timecode
IRIG Timecode
IRIG Timecode
IRIG Timecode
IRIG Timecode
GPS
GPS
External Events
+3.3 VDC
External Events
External Events
+12 VDC
+3.3
VDCtyp
±5%
@ 0.7A
+12
VDCtyp
±8%
@ 0.2A
+3.30.7A
VDC
±5%
±5% @
@ 0.7A typ
typ
+3.3 VDC
±5%
±5% @
@ 0.7A
0.7A typ
typ
+120.2A
VDC
±8%
±8% @
@ 0.2A typ
typ
+12 VDC
±8%
±8% @
@ 0.2A
0.2A typ
typ
+12 VDC
±5% @
@ 0.7A typ
typ
±5%
±8%
±5% @ 0.7A
0.7A typ
±5% @ 0.7A typ
±5% @ 0.7A typ
0.85A
typ
±5%
0.7A
typ
typVs2: +5%/-2%
±8%
±5% @
@@
0.7A
typ
±5% @ @
0.7A
typ typ
Vs2: +5%/-2%
0.85A
IRIG Timecode
IRIG Timecode
IRIG Timecode
-12 VDC
-12—VDC
VDC typ
±5%-12
@—
0.2A
-12 VDC
-12 VDC
±5%
0.2A
±5% @
@—
0.2A typ
typ
—
±5%
—@
±5%
@ 0.2A
0.2A typ
typ
±8% @
@ 0.2A typ
typ
±8%
@ 0.2A typ
±8% @ 0.2A
0.2A typ
±8% @ 0.2A typ
±8% @ 0.2A typ
±5% @ 0.2A typ
±5% @ 0.2A typ
±5%
0.2A
±8%
@
0.2A
typ
@ 0.2AVs1:
typ
±8%
@@
0.2A
typtyp
12V_AUX:
-±5%
@ 0.2A
±5%
@
typ
±5%
@
0.2A
typ
±5%
@ 0.2A
0.2A
typ typ
±8%
@ 0.2A
typtyp
Vs1:
±5%
@ 0.2A
±5%-±5%
@ 0.2A
typ typ
12V_AUX:
@ 0.2A
typVs2: +5%/-2% @ 0.85A±8%
typ ±5% @ 0.2A typ
typ @ 0.2AVs1:
±5%
@ 0.2A
12V_AUX:
-±5% typ
@ 0.2A typ
Vs2: +5%/-2% @ 0.85A typ
typ
Vs2: +5%/-2% @ 0.85A typ
Vs1: ±5% @ 0.2A typ
12V_AUX: -±5% @ 0.2A typ
±8% @ 0.2A typ
±5% @ 0.2A typ
Vs1: ±5% @ 0.2A typ
12V_AUX: -±5% @ 0.2A typ
TSync Time Code Processors Technical Specifications
TSync-PCIe
TSync-PMC
Ordering Information*
Spectracom’s TSync timing boards come in
several configurations depending on the
bus-type/form factor. Variations include
the precision of internal timekeeping,
synchronization to external references and
interconnections to external devices.
Form Factor/Bus Type
(AAAA)
TSync-cPCI
1=TF
TSync-PCI-104
Model Number
Options
TSync-AAAA-X-Y-Z
Premium Breakout Cable Upgrade:
AAAA = Form Factor
X= Custom Options
Y=Internal Oscillator
Z=External Reference
Replaces basic breakout cable for all available
inputs and outputs.
Custom Options (X)
0=NONE
TSync-VPX
*For more information about external connections (adapters,
breakout cables, antennas, etc.) please see the TSync Configurations
& Ordering Information datasheet.
Internal Options (Y)
External Reference (Z)
0=IRIG or
Other
1=Internal
GPS/GNSS
2=External
GPS/GNSS
x
x
x
x
x
x
3=CC
0=TCXO
1=OCXO
x
x
2=Rugged
OCXO
PCIe
(PCI Express)
x
PMC
(PCI mezzanine card)
x
x
x
x
x
cPCI
(compact PCI)
x
x
x
x
x
x
x
x
VPX
x
x
x
x
x
x
x
PCI-104
x
x
x
x
x
x
TF = Thermal Frame
CC = Conformal Coating
spectracom.com
November 30, 2016 - TSync (B1). Specifications subject to change or improvement without notice.
Spectracom is a business of the Orolia Group. ©2015-2016 Orolia USA, Inc.
x
3=SAASM
GPS
x
x
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