Toshiba T3200 - Maintenance Manual

1.1 GENERAL

Toshiba Personal Computer T3200 (hereinafter referred to as

T3200) is a portable personal computer which is compatible with

IBM PC/AT si tuated at higher rank of portable computer than

Toshiba T3l00. Hardware of the T3200, a lot of IC chips are

C-MOS type so that the power consumption is very little and Gate

Array chips are applied so that it is very compact and light weight.

The T3200 is composed of as follows:

System PCB (Printed curcuit board)

Hard disk control PCB

3.5-inch floppy disk drive

3.5-inch hard disk drive

Plasma display

Keyboard

Power supply unit

FIGURE 1-1 T3200 Personal Computer

1-1

A 3.5-inch Floppy disk drive (FDD) is double-sided, double-density, double-track with storage capacity of 720 kilobytes (formatted). A 3.5-inch hard disk drive (HDD) with storage capacity of 40 megabytes (formatted) is the second external storage device. The plasma display with pixels of 720 in columns and 400 in rows.

The keyboard has 85 keys. For most applications it can be used exactly like a standard typewriter keyboard.

The power supply unit provides +5 Vdc and +12 Vdc power to every component in the system unit, including the option cards. For the plasma display, this unit regulates +205 Vdc power. This unit has a ventilation fan, driven by +12 Vdc. The fan enhances the reliability and durability of the T3200 system unit.

The T3200 provided connecting to the optional devices at the rear panel of the system. There are three connectors such as a parallel printer (or an external floppy disk drive), an RGB direct drive CRT display and an RS-232C device.

The connector for a parallel printer can be used to connect an external FDD unit by changing the A-B-PRT switch setting.

1-2

1.2 SYSTEM PCB

System PCB is composed of the following devices: o Central processor: CPU (80286-12) (12 MHz/6 MHz» o Numeric data processor: NPU (80287, optional) o Memory

RAM

ROM (Main BIOS) . . . . .

(AGS BIOS) . . . . . .

Video RAM . . . . . . . . . . •

1 Mbyte standard

3 Mbytes (option card)

--- "LIM" standard

64 Kbytes (16 bits)

32 Kbytes (8 bits)

256 Kbytes o System suP?ort elements

Direct memory access: DMA (82C37)

Programmable interrupt controller: PIC (82C59)

Programmable interval timer: PIT (82C54)

Real time clock: RTC (MC1468l8) o Floppy disk controller: FDC (TC8565F) o Keyboard controller: KBC (u8042) x 2 o Display controller: PEGA2, AGS G.A. o Gate array

Bus driver

Memory mapper

DMA driver

I/O controller

LIM

AGS (Advanced graphics subsystem)

1-3

1.2.1 DIP switches

The system has DIP switches which are located at the rear panel.

The following table shows function of the DIP switches.

TABLE 1-1 DIP Switch Functions

DIP

Switch

Setting Description

1

2

3

4

5

ON

OFF

ON

OFF

ON

OFF

ON

OFF

ON

OFF

Auto-Switched display mode

IBM EGA full compatible

PRT port used both for input and output

PRT port only for output

Communications port as CH2

Communications port as CH 1

Double font in plasma for TEXT

Single font in plasma for TEXT

Disable CRTC for EXT.CRTC

Enable internal CRTC (normal)

6

ON

OFF

North European Font to display

Other Fonts (Normal)

7to 10 (Defined as follows)

Monitor in use 7 8 9 10

Monochrome OFF OFF OFF OFF

Standard RGB

(40 column mode is default)

ON OFF OFF ON

Standard RGB

(80 column mode is default)

Enhanced RGB

(200 line or emulation of standard RGB is default)

OFF

ON

OFF

ON

OFF

ON

ON

OFF

Enhanced RGB

(350 line, true enhanced operation is default) OFF ON ON OFF

1-4

1.2.2 Jumper straps

The system has six jumper straps (PJ 2) which are located on the keyboard control PCB.

Usually the six jumper straps are all open.

The following figure shows location of the jumper straps.

MiwtfU

PJ 2

I I

FIGURE 1-2 Jumper Strap Locations

The following table shows function of the jumper straps.

TABLE 1-2 Jumper Strap Functions

Name Function

1-2 Not used

3-4 2HD FDD type Open ... 1.6 Mbytes

Short ... 2.0 Mbytes

5-6 Internal FDD numbers Open ... OneFDD

Short ... Two FDD/s

7-8 FDD type Open ... 2DD

Short ... 2HD (1.6 Mbytes/2.0 Mbytes)

9-10 Standard memory size Open ... 640 kbytes

Short ... 512 kbytes

11-12 Used 3M B memory card Open ... Used as the extended memory and mode (Option) the expanded memory.

Short ... Used as the only expanded memory.

1-5

1.3 3.5-INCB FLOPPY DISK DRIVE

The floppy disk drive (FDD) used in the T3200 is high performance, high reliable, slim sized FDD for 3.5-inch floppy disks with recording capacity of 720 kbytes (formatted) in double-sided, double density and 135 tracks per inch operation.

The specifications are as following table.

FIGURE 1-3 3.5-inch FDD

TABLE 1-3 3.5-inch Floppy Disk Drive Specifications

Item

Storage Capacity (kilobytes)

Number of Heads

Number of Track per Side

Track to Track Access (milliseconds)

Head Settling Time (milliseconds)

Track Density (tracks per inch)

Motor Start-up Time (milliseconds)

Data Transfer Rate (kilobits per second)

Rotational Speed (revolutions per minute)

Recording Method

Specifications

1000 (unformatted)

720 (formatted)

2

80

3

15

135

500

250

300

MFM (Modified frequency modulation)

1-6

1.4 3.5-IRCH HARD DISK DRIVE

The hard disk drive (HDD) is random access storage, having recording capacity of 40 Mbytes (formatted). This is equipped with the storage media of non-removable 3.5-inch magnetic disks and mini-winchester type magnetic heads.


FIGURE 1-4 3.5-inch Hard Disk Drive

TABLE 1-4 3.5-inch Hard Disk Drive Specifications

Item

Storage Capacity (megabytes)

Number of Heads

Number of Cylinders

Number of Tracks (tracks per cylinder)

Access Time (milliseconds) (minimum)

(average)

(maximum)

Recording Density (bits per inch)

Track Density (tracks per inch)

Rotational Speed (revolutions per minute)

Recording Method

Specifications

51.24 (unformatted)

40.30 (formatted)

8

615

8

8

38

85

14845

834

3600

MFM (Modefied Frequency

Modulation)

1-7

1.5 HARD DISK CONTROL PCB

Hard disk control PCB (HOC) is accompanied by hard disk drive

(HOD) and connects to the system PCB through a cable. This HOC can interface the HDD to the system PCB.


FIGURE 1-5 Hard Disk Control PCB

TABLE 1-5 Hard Disk Control PCB Specifications

Item

Encoding method

Data Transfer Rate (megabits per second) maximum

Write Precompensation time (nanoseconds)

Sectoring

Specifications

MFM (Modefied Frequency

Modulation)

5

12

Soft

1-8

1.5.1 Jumper straps

The Hard disk control PCB has jumper straps which are PJ 3, PJ 4 and PJ 5.

Functions of the jumper straps are as follows.

(1)

PJ 3

Not used.

(2) PJ 4

This jumper straps select recording method of the hard disk control PCB.

The following table shows function.

TABLE 1-6 PJ 4 Jumper Strap Functions

No. Status

1-2 Short

3-4 Open

Function

MFM method

( 3) PJ 5

This jumper straps select the delay time of the hard disk control PCB.

Usually delay time is selected as 20 ns.

The following table shows function of the jumper straps.

TABLE 1-7 PJ 5 Jumper Strap Functions

No.

1-2

3-4

5-6

7-8

9-10

Delay time select

10 ns

15 ns

20 ns

25 ns

30 ns

1-9

1 .6 KEYBOARD

The keyboard is mounted on the system and has 85 keys. These consist of 54 standard keys, 10 function keys, 17 cursor keys,

14 functional keypads, and Fn key.

The keyboard is just a key matrix built up by the above keys.

The keyboard is connected to the keyboard controller on the system PCB through a 22-pin flat cable.

FIGURE 1-6 Keyboard

1-10

1. 7 PLASMA DISPLAY

The plasma display is a graphics type display unit composed of the display panel and driver circui ts. This receives vertical and horizontal sync signals, four bit data signals, and shift clock for data transmission. All these signals are TTL level compatible. The specifications are as following table.

The plasma display has 4-level of gray display.

The plasma display be adjusted by contrast/brightness control volume.

FIGURE 1-7 Plasma Display

TABLE 1-8 Plasma Display Specifications

Item

Dot Number (dots)

Dot Dimension (mm)

Dot Pitch (mm)

Display Area (mm)

Contrast

Color

Power Requirement

MTBF

Specification

720 x 400

0.18 (V) x 0.16 (H)

0.36 (V) x 0.30 (H)

144(V)x216(H)

1 : 10

Neon - orange

+ 5V

+ 205

+ SV

± 0.5V, 0.6A

± 5V, 170mA

± O.SV, 60mA

20000 hours

1-11

1.8 POWER SUPPLY UNIT

The power supply unit supplies dc 5, 12, -12 and 205 volts to all the components in the system.

The power supply unit is housed in the system and is designed to support the following:

1) System PCB

2) 3.5-inch Floppy disk drive

3) 3.5-inch Hard disk drive

4) Hard disk control PCB

5) Keyboard unit

6) Plasma display

7) Option PCB's

The power supply unit includes the input line filter, line fuse, cooling fan, power conversion circuitry and connectors.

Input rating is as follows.

AC 100, 115/220, 240 Volts, 60W (lOOW max.)

Output rating is as following table.

FIGURE 1-8 Power Supply Unit

TABLE 1-9 Power Supply Unit Output Rating

FUNCTION

SYSTEM PCB

SYSTEM PCB

SYSTEM PCB

PLASMA DISPLAY

PLASMA DISPLAY

DC VOLTAGE

5V

12 V

-12 V

205 V

SV

1-12

REGULATION

TOLERANCE

:t5%

±5%

+ 10 %, 20 %

200 to 210 V

±10%

MAX.

CURRENT

6.5A

2.6A

0.3A

170mA

60mA

2.1 GENERAL

These problem isolation procedures are used to isolate defective

FRUs (field replaceable units) to be replaced. FRUs consist of the following:

1. Power supply unit

2. System PCB

3. FDD

4 . HDD and HOC

5. Keyboard

6. Plasma display

See PART 4 for detailed replacement procedures instructions.

Test program operations are described in PART 3.

The following items are necessary for carrying out the problem isolation procedures.

1. T3200 Diagnostics disk

2. Flatbladed screwdriver

3. Work disk (for FDD testing)

4. Cleaning disk kit (for FDD testing)

5. Multimeter

6. Printer port LED

The problem isolation flowchart described in part 2.2 can be used to determine the necessary isolation procedures to be followed when there is a problem with the T3200.

2.2 PROBLEM ISOLATION FLOWCHART

This flowchart is used as a guide for determining which FRU is defecti ve. Please conf irm the following before performing the flowchart procedures.

1. No disk is in the FDD.

2. All optional equipment is disconnected.

See next page.

2-1

Turn the POWER switch off.

Perform power supply problem

">-;,.;.No"--___

I isolation procedures in part 2.3.

Yes Perform system PCB problem

=>-----l.1 isolation procedures in part 2.4.

No

~

Perform Plasma Display problem isolation procedures in part 2.8.

No

:>-.:..;.::....---1.1

Perform system PCB problem isolation procedures in part 2.4.

Is the C> displayed on the screen ?

No

~":':'="'---l.1

Perform HOD problem isolation procedures 1 n part 2.4.

FIGURE 2-1 Problem Isolation Flowchart

2-2

Insert the diagnostics disk into the FDD.

~_N...,;.o_

Perform FDD problem isolation

... , procedures in part 2.5.

Yes

After confirming which diagnostic test caused an error to be

--:>-----l., genera ted. Perform the re 1 evant problem isolation procedures, as indicated below.

System normal

1. If an error is generated on the system test, memory test, display test and real timer test, go to system PCB isolation procedures in part 2.4.

2. If an error is generated on the hard disk test, go to HDD isolation procedures in part 2.6.

3. If an error is generated on the keyboard test, go to keyboard isolation procedures in part 2.8.

4. If an error is generated on the floppy disk test, go to FDD isolation procedures in part 2.5.

2-3

2.3 POWER SUPPLY UNIT ISOLATION PROCEDURES

This section describes how to determine whether the power supply

PCB is defective or not. The procedures below are outlined in the following pages. They should be performed in the order indicated.

PROCEDURE 1: Power Indicator Check

PROCEDURE 2: Connector Check

PROCEDURE 3: Output Voltage Check

PROCEDURE 4: Power Supply Unit Voltage Adjustment

PROCEDURE 5: Power Supply Unit Replacement

2-4

PROCEDURE 1

Power Indicator Check

1. Turn the POWER switch on.

2. If the POWER indicator lights, go to PROCEDURE 3.

If the indicator doesn't light, replace the ac cord; if i t lights, the previous ac cord was defective. If the indicator doesn't light yet, go to PROCEDURE 2.

Disk in Use

D O 0

Left Right CRT

D O D

Caps Num Scroll

Lock Lock Lock

FIGURE 2-2 POWER Indicator Check

2-5

PROCEDURE 2

Connector Check

1. Turn the POWER switch off and unplug the ac cord.

2. Remove the top cover. (Refer to part 4.2.)

3. If the two system PCB connectors (PJ 7 and 8) are connected properly, go to PROCEDURE 3; if they are not connected properly, reconnect them.

FIGURE 2-3 Power Supply Unit Connectors

2-6

PROCEDURE 3

Output Voltage Check

1. Disconnect the three power cables (for plasma display and system PCB) from the system PCB.

2. Plug the ac cord, then turn the POWER switch on.

3. Use a multimeter to confirm that the output voltages for the three power supply PCB connectors conform to the values given in the following table.

4. If the voltages conform to the values given in the table, the power supply PCB is normal. System PCB is probably defecti ve, go to system PCB isolation procedures in part

2.4.

5. If the voltages do not conform to those given in the table, ao to PROCEDURE 4.

TABLE 2-1 Power Supply Unit Output Voltages

CONNECTOR

PJ 003

PJ 004

PJ 005

PIN NUMBER VOLTAGE (Vdc)

+ lead -lead Normal Min Max

1 3,4 + 5 + 4.75 + 5.25

2 3,4 + 5 + 4.75 + 5.25

1

3

2,4

2,4

+ 12

- 12

+ 11.4 + 12.6

- 13.2 - 9.6

1

3

2

2

+

+

205

5

+

+

200

4.5

+ 210

+ 5.5

2-7

PROCEDURE 4

Power Supply Unit Voltage Adjustment


2. Remove the power supply unit. (Refer to part 4.9.)

3. Remove the power supply uni t cover from the power supply unit.

4. Set the dummy load resister (1.3 kiloohm, 35 W) to the plasma display power connector (l-pin to 2-pin).

5. Plug the ac cord to the power supply uni t, then turn the

POWER switch on.

6. Use a multimeter to confirm that the output voltages for the plasma display power connector conform to the volues given in the following table.

TABLE 2-2 VRl Adjustment

CONNECTOR

PJ 005

PIN NUMBER

+ lead -lead

1 2

VOLTAGE (Vdc)

Min Max

+ 201 + 202

7. If the voltage does not conform to that given in the table, after turn the VR2 to the right, then adjust the VRl on the power supply PCB by Phillips screwdriver.

8. Turn the POWER switch off, then remove the dummy load resister (1.3 kiloohm, 35 W).

9. Set the dummy load resister (21 kiloohm, 2.5 W) to the prasma display power connector (l-pin to 2-pin).

10. Adjust the VR2 on the systen PCB that the output voltages for the plasma display power connector conform to the values given in the following table.

TABLE 2-3 VR2 Adjustment

CONNECTOR

PJ 005

PIN NUMBER

+ lead -lead

1 2

VOLTAGE (Vdc)

Min Max

+ 208 + 209

2-8

PROCEDURE 5

Power Supply unit Replacement


2. Replace the power supply unit. (Refer to part 4.9.)

3. If normal operation is restored after replacing the power supply unit, the previous power supply unit was defective.

4. If normal operation is not restored, another FRU is probably defective. replaced.

The defective unit must be isolated and

2-9

2.4 SYSTEM PCB ISOLATION PROCEDURES

This section describes how to determine whether the system PCB is defective or not. The procedures below are outlined in the fol1owinq pages. They should be performed in the order indicated.

PROCEDURE 1: Message Check

PROCEDURE 2: Printer Port LED Check

PROCEDURE 3: Test Program Execution

PROCEDURE 4: System PCB Replacement

NOTE: Before ca rrying out any of these procedures, make sure that there is not a floppy disk in the FDD.

2-10

PROCEDURE 1

Message Check


2. If the system is loaded, go to PROCEDURE 3.

3. If the following message is displayed on the screen, press the Fl key. Execute the setup. (Refer to OWNER'S MANUAL in

PART 6.)

***

Error in CMOS. Bad battery

***

Check system Then. press [Fl]

key ......

***

Error in CMOS. Bad check sum

***

Check system Then. press [Fl] key .•••.•

**

Error in CMOS. Bad configuration

**


key ..•.• a

***

Error in CMOS. Bad memory size

***


key .•••••

**

Error in CMOS. Bad time function

**


key ......

4. If the following message is displayed on the screen, go to

HOD isolation procedures in part 2.6.

**

HOD Load error or Bad system disk

**

Insert system disk in drive

Press any key when ready ..•..

5. If none of the messages are displayed and you have a printer port LED, go to PROCEDURE 3.

If none the messages are displayed and you don't have a printer port LED, go to PROCEDURE 2.

2-11

PROCEDURE 2

Beep Sound Check

1. Turn the POWER switch off.


3. If the system occurs an error, the system informs you of an error code with the beep sound. (That is the bit information of DL register.)

The system repeats the buzzer message three times. A hexadecimal number is configured by the combination of two groups of the beep sounds, each of which is composed of either short sounds or long sounds.

The status of an error code is as following table.

4. If the error code conforms to the values given in the table, go to PROCEDURE 5.

5. If the error code doesn't conform to the values given in the table, another FRU is probably defective.

TABLE 2-4 Beep Sound Error Code

5H

6H

7H

BH

OH lH

2H

3H

4H

9H

AH

BH

CH

DH

EH

FH

2-12

PROCEDURE 3

Printer Port LED Check


2. Plug the printer port LED into the PRT/FDD connector on the back of the unit.

3. Turn the POWER switch on while watching the printer port

LED.

The printer port LED will light at the same time that the

POWER switch is turned on.

4. Read the final LED status as a hexadecimal value from left to right.

5. If the final LED status matches any of the error code values

1n the table 2-6 (See the next page.), go to PROCEDURE 5.

6. If the final LED status is 19B, go to PROCEDURE 4 and continue.

TABLE 2-5 Printer Port LED Normal Status

Status Messages

01 (H)

02 (H)

Initial setup of LSI start

Initial setup of RTC end

03 (H)

04 (H)

Initial setup of PIT end

Initial setup of DMAC(#1) end

05(H) Initial setup of DMAC(#2) end

06 (H) Initial setup of PIC (#1) end

07 (H)

08 (H)

Initial setup of PIC (#2) end

Initial setup of DMA page register end

09 (H) Initial setup of KB controller end

OA (H) Initial setup of memory (0 - 64 KB) end

OB (H)

OC (H)

Initial setup of memory (64 - 640 KB) end

Initial setup of memory (more than 1 MB) Protect mode end

OD (H) Initial setup of memory (more than 1 MB) Real mode end

OE(H) Check a checksum of CMOS end

OF (H) Check ciassfication of CRT end

10 (H) Check item of CMOS end

11 (H)

12 (H)

Initial setup of CRT end

Initial setup of keyboard end

13 (H)

14 (H)

15 (H) Initial setup of HDD end

16(H) Initial setup of option ROM end

17 (H)

18 (H)

19 (H)

Initial setup of Timer end

Initial setup of FDD end

Initial setup of printer end

Initial setup of RS232C end

Prepare the boot end

2-13

TABLE 2-6 Printer Port LED Error Status

Status Error Messages

81 (H)

82 (H)

83 (H)

84(H)

85(H)

86 (H)

87(H)

88(H)

89 (H)

Exception (size proc)

Faded PM (size proc)

ADR 20 failed (size proc)

KBC Self test error

KBC not ready I (KBC init)

KBC not ready

o

(KBC init)

KBC not ready I (size ret)

KBC not ready I (ex. ret size)

KBC not ready I (mono set)

8A(H) KBC not ready I (KB init)

8B (H)

8C(H)

91 (H)

92 (H)

93 (H)

94(H)

KBC not ready I (PRT init)

KBC not ready

PE

=

1 (start)

PE

=

0 (size proc)

PE

=

0 (mem test)

o

(PRT init)

ROM check sum error

A1 (H) RTC data bus error

A2(H) RTC into error

A3 (H) RTC clock error

A4(H) PIT data bus error

A5(H)

A6(H)

A7 (H)

PIT ch.2 output error

PIT clock error

PIT ch. 1 output error

A8(H)

A9 (H)

PIT ch.O output error

DMAC # 1 data bus error

AA(H) DMAC #2 data bus error

AB (H) PIC # 1 data bus error

AC(H) PIC #1 data bus error

AD(H) PIC #2 data bus error

AE (H) PIC #2 data bus error

AF (H)

B 1 (H)

MAPPER data bus error

MAPPER address error

B2 (H) Word/byte error (110)

B3 (H) Exception (mem test)

B4 (H) Failed PM (mem test)

B5(H)

B6(H)

B7(H)

KBC not ready I (ex. ret mem test)

ADR 20 failed (mem test)

KBC NOT ready I (mem test)

2-14

Process

HALT

HALT

HALT

HALT

HALT

HALT

HALT

HALT

HALT

HALT

HALT

HALT

HALT

HALT

HALT

HALT

HALT

HALT

HALT

HALT

HALT

HALT

HALT

HALT

HALT

HALT

HALT

HALT

HALT

HALT

HALT

HALT

HALT

HALT

HALT

HALT

HALT

HALT

Status Error Messages

B8(H)

C1 (H)

C2 (H)

KBC not ready o

(FDD int)

Mem (base 64KB) data bus error

C3 (H)

C4(H)

C8(H)

Mem (base 64KB) word/byte error

Mem (base 64KB) fixed data error

Mem (base 64KB) address error

Mem (base 64KB) parity circuit error

C9(H)

CA(H)

CB (H)

CC(H)

Mem (base 64KB) parity circuit error i Mem (base 64KB) parity circuit error



DO(H)

01 (H)

D2 (H)

D3 (H)

04 (H)

Mem (64 KB-

Mem (64 KB-

Mem (64 KB-

Mem (64 KB-

) data bus error

) word/byte error

) fixed error

) address error

DS (H) Mem address error

D8(H) Mem (64 KB) parity circuit error

09 (H) Mem (64 KB-

OA(H) Mem (64 KB-

DB (H)

E1 (H)

Mem (64 KB-

DC(H) Mem (64 KB-

) parity circuit error




Video RAM error (mono)

E2 (H)

E3 (H)

Video RAM error (plasma/color)

Video RAM error (plasma)

E4(H)

ES(H)

E6(H)

CRTC error (mono)

CRTC error (plasma/color)

FDC error

Process

HALT

HALT

HALT

HALT

HALT

HALT

HALT

HALT

HALT

HALT

HALT

HALT

HALT

HALT

HALT

HALT

HALT

HALT

HALT

HALT

HALT

HALT

HALT

HALT

HALT

HALT

2-15

PROCEDURE 4

Test Program Execution

1. Execute the following test program. (See PART 3 TEST AND

DIAGNOSTICS. )

1. System test

2. Memory test

3. Keyboard test

4. Display test

S. Floppy disk test

6. Hard disk test

7. Real timer test

2. If an error is generated on the system test, memory test, display test and real timer test, go to PROCEDURE S.

3. If an error is generated on the floppy disk test, go to FDD isolation procedures in part 2.S.

4. If an error is generated on the hard disk test, go to HDD isolation procedures in part 2.6.

S. If an er.ror is generated on the keyboard test, go to keyboard isolation procedures in part 2.7.

2-16

PROCEDURE 5

System PCB Replacement

1. Replace the system PCB. (Refer to part 4.14)

2. If normal operation is restored after replacing the PCB, the previous PCB was defective.

3. If normal operation is not restored, another FRU is probably defective. The defective unit must be isolated and replaced.

2-17

2.5 FLOPPY DISK DRIVE ISOLATION PROCEDURES

This section describes how to determine whether the floppy disk drive is defective or not. The procedures below are outlined in the following pages. They should be performed in the order indicated.

PROCEDURE 1: Test and Diagnostic Program Loading Check

PROCEDURE 2 : Message Check

PROCEDURE 3 : Head Cleaning

PROCEDURE 4 : FDD Test Execution

PROCEDURE 5 : FDD Connector Check

PROCEDURE 6 : New FDD connection

2-18

PROCEDURE 1

Test and Diagnostic Programs Loading Check


2. Insert the diagnostics disk into the FDD.


4. If loading occurs normally, go to PROCEDURE 3. (See PART 3 to determine if loading has occurred normally.)

5. If loading has not occurred normally, go to PROCEDURE 2.

2-19

PROCEDURE 2

Messaqe Check

1. When the diagnostics disk is inserted into the FDD and the

POWER switch is turned on, message (a), message (b), message

(c) or message (d) should appear.

(a) (**** FDD A in not installed ****

)

(b) Non-System disk or disk error

Replace and press any key when ready

** FDD load error or Bad system disk **

(c) Insert system disk in drive

Press any key when ready •.•••

(d)

** HOD Load error or Bad system disk **


Press any key when ready •••••

2. If (a) of the above message is displayed, confirm that the

A-B-PRT switch is set to the PRT side. If i t is not seted to the PRT side, set the PRT side; if i t is seted to the PRT side, go to PROCEDURE 5.

3. If (b),

(c) or (d) of the above messages is displayed, the contents of the floppy disk are damaged, or some other disk than the diagnostics disk has been inserted into the FDD.

Change the diagnostics disk. If loading then occurs, go to

PROCEDURE 4; if loading does not occur, go to PROCEDURE 3.

4. If none of the above messages appears, go to PROCEDURE 5.

2-20

PROCEDURE 3

Head Cleaning


2. Insert the cleaning disk to the FDD.


4. If normal operation is restored after cleaning the head, go to PROCEDURE 4.

5. If normal operation is not restored, go to PROCEDURE 5.

2-21

PROCEDURE 4

FDD Test Execution

1. Run the floppy disk test which is indicated in the

Diagnostic Test Menu.

2. If an error is generated during the floppy disk test, error code and status will be displayed as indicated in following table. Follow the directions provided in an the the table.

3. If no error is generated, the FDD is normal.

TABLE 2-7 FDD Error Status

CODE

01

02

40

60

80

EE

03

04

06

08

09

10

20

STATUS

Bad Command

Address Mark Not Found

Write Protected

Recod Not Found

Media removed on dual attach card

DMA Overrun Error

DMA Boundary Error

CRC Error

FDC Error

SEEK ERROR

FDD not drive

Time Out Error (Not Ready)

Write buffer error

2-22

PROCEDURE 5

FDD Connector Check

1. Turn the POWER switch off and disconnect the ac cord.

2. Remove the top cover. (Refer to part 4.2.>

3. If the FDD cable is connected to the system PCB securely, go to PROCEDURE 6.

4. If the above connections are not secure, reconnect them.

FIGURE 2-4 FDD Connector Check

2-23

PROCEDURE 6

New FDD Connection


2. Remove the FDD. (Refer to part 4.10.>

3. Connect the new FDD to the FDD connector, then other connectors too.


5. If normal operation is restored after connect the new FDD, the previous FDD was defective. Assemble the system.

6. If normal operation is not restored, system PCB is probably defective. Refer to part 2.4.

2-24

2.6 BARD DISK DRIVE ISOLATION PROCEDURES

This section describes how to determine whether the Hard Disk

Drive is defective or not. The procedures below are outlined in the following pages. They should be performed in the order indicated.

PROCEDURE 1: HDD Indicator Check

PROCEDURE 2: Message Check

PROCEDURE 3: Format Execution

PROCEDURE 4: Hard Disk Test Execution


PROCEDURE 6 : New HDC Connection

PROCEDURE 7: New HDD Connection

2-25

PROCEDURE 1

HOD Indicator Check


2. If there is a floppy disk in the FDD, take it out.


4. If the HDD indicator (Disk In Use - Left) blinks briefly and goes out, go to PROCEDURE 2: if it continues blinking, go to

PROCEDURE 4.

5. If the indicator does not light at all, go to PROCEDURE 5.

Disk in Use

_ 0 0 0 0 0

Left Right CRT Caps Num Scroll

Lock Lock Lock

FIGURE 2-5 HDD Indicator Check

2-26

PROCEDURE 2

Message Check

1. If the system is loaded, go to PROCEDURE 4.

2. If the following message is displayed on the screen, go to

PROCEDURE 3.

**

HOD Load error or Bad system disk

**


Press any key when ready ..•••

2-27

PROCEDURE 3

Format Execution

CAUTION: The contents of the hard disk will be erased when the

FORMAT command is run. Before running the test, transfer the contents of the hard disk on the floppy disk. This can be done with the MS-DOS BACKUP command.

(See the MS-DOS manual for details.)

1. Remove the diagnostics disk, and then insert the MS-DOS system disk to the FDD.

2. To set the parti tion of the hard disk, enter the FDISK command. (See the MS-DOS manual for details.)

3. To format the hard disk, enter the FORMAT command. (See the

MS-DOS manual for details.)

4. If normal operation is restored, the HDD is normal.

5. If normal operation is not restored, go to PROCEDURE 6.

2-28

PROCEDURE 4

Hard Disk Test Execution

CAUTION: The contents of the hard disk will be erased when the test program is run. Before running the test, transfer the contents of the hard disk on the floppy disk. This can be done wi th the MS -DOS BACKUP command. (See the

MS-DOS manual for details.>

1. Insert the diagnostics disk into the FDD and load the test and diagnostic programs.

2. Run the hard disk test which is indicated in the diagnostics test menu.

3. If an error is generated during the hard disk test, an error code and status will be displayed as indicated in the following table. Go to PROCEDURE 6.

4. If no error is generated, the HDD is normal. Enter the

MS-DOS FDISK command which will set the parti tion. Then enter the MS-DOS FORMAT command. (See the MS-DOS manual for details. )

TABLE 2-8 HDD Error Status

CODE

OA

OB

10

11

20

40

80

AA

01

02

04

05

07

09

BB

CC

EO

FO

STATUS

Bad command error

Bad address mark

Record not found

HDC NOT RESET

Drive not initialize

DMA Boundary error

Bad sector error

Bad track error

ECC error

ECC recover enable

HDC error

Seek error

Time out error

Drive not ready

Undefined

Write fault

Status error

Not sense error (HW.code

=

FF)

2-29

PROCEDURE 5

Connector Check


2. Remove the top cover. (Refer to part 4.2>

J .

If the HDD, HDC, and system PCB are connected securely, go to PROCEDURE 6.

4. If they are not connected securely, reconnect them.

FIGURE 2-6 HDC and HDD Connector Check

2-30

PROCEDURE 6

New HOC Connection


2. Remove the HDC. (Refer to part 4.13.>

3. Connect the new HOC to the system PCB and HDO, then other connectors too.

4. If normal operation is restored, the previous HOC was defective. Assemble the system.

5. If normal operation is not restored, HOD is probably defective. Go to PROCEDURE 7.

2-31

PROCEDURE 7

New HOD Connection


2. Remove the HOD. (Refer to part 4.11.)

3. Connect the new HDD to the HDC, then other connectors too.

4. If normal operation is restored, the previous HDD was defective. Assemble the system.

5. If normal operation is not restored, system PCB is probably defective. System PCB is probably defective. Refer to part

2.4.

2-32

2.7 KEYBOARD ISOLATION PROCEDURES

This section describes how to determine whether the keyboard is defective or not. The procedures below are outlined in the following pages. indicated.

They should be performed in the order

PROCEDURE 1: Input Check

PROCEDURE 2: Keyboard Test Execution


PROCEDURE 4: New Keyboared Connection

2-33

PROCEDURE 1

Input Check

1. Load either the diagnostics disk or the MS-DOS system disk.

2. When a prompt (A, B, C, etc.) appears on the screen, hit any of the whi te keys on the keyboard (any character or the space bar). If the character you hit appears on the screen, go to PROCEDURE 2.

3. If the character does not appear, go to PROCEDURE 3.

Toshiba Personal Computer MS-DOS Version 3.20 / (RXXXXX)

(C) Copyright Toshiba

(C) Copyright Microsoft

Corporation 1983,1986

Corporation 1981,1986

Current date is XXX X-XX-19XX

Enter new date (mm-dd-yy) :

Current time is X:XX:XX,XX

Enter new time :

COMMAND Version 3.20

A> abcdefghijklmnopqrst ••••••••••••••••

2-34

PROCEDURE 2

Keyboard Test Execution

1. Insert the diagnostics disk into the PDD and load the test and diagnostics programs. (Refer to PART 3.>

2. Run the keyboard test which is indicated in the diagnostics test menu.

3. If an error is generated during the test, go to PROCEDURE 3.

4. If no error is generated during the test, the keyboard is normal.

2-35

PROCBDURE 3

Connector Check


2. Remove the top cover. (Refer to part 4.2)

3. Lift the keyboard up and check that the keyboard cable is connected securely to the system PCB. If it is connected securely, go to PROCEDURE 4.

4. If it is not connected securely, reconnect it.

FIGURE 2-7 Keyboard Connector Check

2-36

PROCEDURE 4

New Keyboard Connection


2. Remove the keyboard unit. (Refer to part 4.7.>

3. Connect the new keyboard to the system PCB.

4. If normal operation is restored after connect the keyboard, the previous keyboard was defective. Assemble the system.

5. If normal operation is not restored, system PCB is probably defective. Refer to part 2.4.

2-37

2.8 PLASMA DISPLAY ISOLATION PROCBDURES

This section describes

DISPLAY is defective or in the following pages. indicated. how to determine whether the PLASMA not. The procedures below are outlined

They should be performed in the order

PROCEDURE 1: Display Check

PROCEDURE 2: Plasma Display Contrast and

Brightness Check

PROCEDURE 3 : Display Test Execution

PROCEDURE 4: Plasma Display Connector Check

PROCEDURE 5: New PDP Connection

2-38

PROCEDURE 1

Display Check


2. After turning the POWER switch on again, the following message should appear in the upper left-hand corner of the screen:

MEMORY TEST XXXKB

3. If the message appears, go to PROCEDURE 2.

4. If the message does not appear, first do the following:

(a) Confirm that the contrast and brightness volume is adjusted correctly.

(b) Confirm that the display is not on an external CRT.

(The CRT indicator lamp will be l i t if the display is on an external CRT.)

(C) Confirm that the DIP switch is OFF.

After confirming (a), (b) and (c) above, perform steps 1 and

2 again. If the message still fails to appear, go to

PROCEDURE 3.

2-39

PROCEDURE 2

Plasma Display Contrast and Brightness Check

1. Turn the contrast and brightness volume, then confirm that the screen becomes changed darker or brighter.

2. If the screen is changed darker or brighter, power supply inputs voltage to the PDP. Go to PROCEDURE 7.

3. If the screen is not changed, go to PROCEDURE 4.

FIGURE 2-8 Plasma Display Contrast and Brightness Check

2-40

PROCEDURE 3

Display Test Execution

1. Insert the diagnostics disk into the FDD and run the test and diagnostics programs.

2. If an error is generated dur ing the display test from the diagnostics test menu, the system PCB is probably defective.

Refer to part 2.4.

3. If no error is generated, the plasma display is normal.

2-41

PROCEDURE 4

PDP Connector Check


2. Take out the PDP (Refer to part 4.4.) and confirm that the plasma display cable is connected securely to the module.

3. If the cable is connected securely, go to PROCEDURE 6.

4. If the cable is not connected securely, reconnect it.

FIGURE 2-9 PDP Connector Check

2-42

PROCEDURE 5

New PDP Connection

1. Connect a new PDP and plasma display cable to the PDP.

2. If normal operation is restored after replacing the PDP, the previous PDP was defective. Assemble the system.

3. If normal operation is not restored, system PCB is probably defective. System PCB is probably defective. Refer to part

2.4.

2-43

3.1 GENERAL

This part explains test and diagnostic programs. The purpose of the test and diagnostic programs is to check the functions of all hardware modules of the T3200 Personal Computer.

There are 19 programs ~ they are composed of two modules: the service program module (DIAGNOSTICS MENU) and test program module (DIAGNOSTIC TEST MENU).

The service program module is composed of 8 tasks:

1. HARD DISK FORMAT

2. SEEK TO LANDING ZONE (HOD)

3. HEAD CLEANING

4. LOG UTILITIES

5. RUNNING TEST

6. FDD UTILITIES

7. SYSTEM CONFIGURATION

8. SETUP

The test program module is composed of 11 tests as follows:

1. SYSTEM TEST

2. MEMORY TEST

3. KEYBOARD TEST

4. DISPLAY TEST

5. FLOPPY DISK TEST

6. PRINTER TEST

7. ASYNC TEST

8. HARD DISK TEST

9. REAL TIMER TEST

10. NDP TEST

11. EXPANSION TEST

The following items are necessary for carrying out the test and diagnostic programs.

1. T3200 Diagnostics disk

2. MS-DOS system disk

3. Work disk (formatted)

4. Cleaning disk kit

5. Printer wraparound connector

6. RS232C wraparound connector

The service engineer utilizes these programs to isolate problems by selecting the appropriate program and operation procedures described in the part 3.2 OPERATIONS.

3-1

3.2 OPERATIONS

1. Insert the diagnostics disk in the floppy disk drive and turn the POWER switch on.

2. Input TESTCB3 for the A> prompt and press Enter.

3. The following display will appear.

TOSHIBA personal computer T3200 DIAGNOSTICS

Version X.XX (C) copyright TOSHIBA Corp. 1987

DIAGNOSTIC MENU:

1 - DIAGNOSTIC TEST

2 - HARD DISK FORMAT

3 - SEEK TO LANDING ZONE (HOD)

4 - HEAD CLEANING

5 - LOG UTILITIES

6 - RUNNING TEST

7 - FDD UTILITIES

8 - SYSTEM CONFIGURATION

9 - EXIT TO MS-DOS o SETUP

PRESS [0] - [9] KEY

Detailed explanations of the service programs and the operations are given in parts 3.16 to 3.23.

4. Press 1 key then Enter. The following display will appear.

TOSHIBA personal computer T3200 DIAGNOSTICS version X.XX (C) copyright TOSHIBA Corp. 1987

DIAGNOSTIC TEST MENU :

1 - SYSTEM TEST

2 - MEMORY TEST

3 - KEYBOARD TEST

4 - DISPLAY TEST

5 - FLOPPY DISK TEST

6 - PRINTER TEST

7 - ASYNC TEST

8 - HARD DISK TEST

9 - REAL TIME TEST

10 - NDP TEST

11 - EXPANSION TEST

88 - FDD & HOD ERROR RETRY COUNT SET

99 - EXIT TO DIAGNOSTICS MENU

PRESS [1] - [9] KEY

3-2

If you want to set the FDD and HDD retry count, type 88 then press Enter. The following message will appear.

When don't operate, error retry count number is onece.

FOO & HOD Error retry count ?

You can set the error retry count of the floppy disk test and hard disk test.

Type 99 then press Enter. Return to the DIAGNOSTICS MENU.

When select the FLOPPY DISK TEST, the following messages will appear.

Test drive number select (1:F001.2:FOD2.0:F001&2) ?

Media in drivell mode (l:360k.2:360k-l.2M/720k.3:1.2M.4:720k) ?

Test start track (Enter:0/dd:OO-79) ?

In the case of type the test start track, test start track number of the floppy disk is one digit or two digits.

When press Enter only, test start track number is zero track.

When select the HARD DISK TEST, the following message will appear.

Test drive number select (I:H001.2:H002.0:H001&2) ?

5. After pressing the test number (1 to 11) of the DIAGNOSTIC

TEST MENU, the following display (sample) will appear.

TEST NAME

SUB TEST

PASS COUNT

WRITE DATA

ADDRESS

SUB-TEST MENU :

01 - ROM CHECKSUM

xx

XXXXX

XX

XXX XX

ERROR COUNT

READ DATA

STATUS

99 - Exit to DIAGNOSTIC TEST MENU

SELECT SUB-TEST NUMBER?

TEST LOOP (1:YES/2:NO) ?

ERRR STOP (1:YES/2:NO) ?

XXXXXXX

XXXXX

XX

xxx

3-3

6. Select the subtest number. Type the subtest number then press the Enter. The following message will appear.

When select the KEYBOARD TEST, the following message will not appear.

TEST LOOP (1:YES/2:NO) ?

When select the (YES)1

Each time a test cycle ends, i t increments the pass counter by one and repeats the test cycle ••

When select the (NO)1

At the end of a test cycle, it terminares the test execution and exits to the subtest menu.

7. Type the 1 or 2 then press Enter. The following message will appear.

ERROR STOP (1:YES/2:NO) ?

When select the (YES)1

When an error occurs, it displays the error status and stops the execution of the test program. The operation guide displays on the right side of the display screen.

When select the (NO)1

When an error occurs, it displays the error status then it increments the error counter by one and goes to the next test.

8. Type the 1 or 2 then press the Enter. The test program will run. Each subtest names described in the part 3.3.

9. When stop the test program, press Ctrl return to the DIAGNOSTICS MENU.

+ Break keys then

10. When error occurs on the test program, the following message will appear.

ERROR STATUS NAME (( HALT OPERATION ]]

1: Test End

2:

3:

Continue

Retry

1: Terminates the test program execution and exits to the subtest menu.

2: Continues the test.

3: Retry the test.

The error code and error status names described in part

3.15.

3-4

3.3 SUBTEST NAMES

The following table shows subtest name of the test program.

TABLE 3-1 Subtest Names

# TEST NAME SUBTEST#

1

2

3

4

5

6

7

8

9

10

11

SYSTEM

MEMORY

KEYBOARD

DISPLAY

FDD

PRINTER

ASYNC

HOD

REAL TIMER

NDP

EXPANSION

UNIT

06

07

01

02

03

04

OS

06

07

08

09

01

02

03

01

01

02

03

02

03

01

02

03

04

OS

01

03

04

OS

02

03

04

05

06

07

08

09

10

01

02

01

02

01

02

03

04

05

06

01

02

01

TEST ITEMS

ROM checksum

HW status

RAM constant data

RAM address pattern data

RAM refresh

Protected mode

Protected mode (3MB)

LIM (Expansion memory)

Pressed key display

Pressed key code display

VRAM read/write

Character attributes

Character set

80*25 Character display

Graphics display (color set 0/1)

640*200 Graphics display

640*200 Graphics display

Display page

·W pattern display

Special attribute test

Sequential read

Sequential read/write

Random address/data

Write specified address

Read specified address

Ripple pattern

Function

Wrapa around

Wrap around (channel· 1)

Wrap around (channel - 2)

Point to point (send)

Point to point (receive)

Card modem loopback

Card modem on-line test

Dial tester test

Sequential read

Address uniquence

Random address/data

Cross talk & peek shift

Write/read/compare(CE)

Write specified address

Read specified address

ECC circuit (CE cylinder)

Sequential write

Real time test

Backup memory test

Real ti me carry test

NDPtest

Box wrap around test

Box mono video ram test

Wrap around test ( 16bit bus)

3-5

3.4 SYSTEM TEST

Subtest 01 ROM checksum (Execution time: 1 second)

This test performs the ROM checksum test on the system PCB.

(Test extent : FOOOOH - FFFFFH 64KB)

Subtest 02 H/W status

This test reads hardware status of the system, then displays the status as shown below.

76543210

H/W status = 10011101

Bit7 --- Display mode

Bit6 --- CPU clock

BitS --- Ten key PAD

Bit4 --- 2MB FDD

Bit3 --- Internal FDDs

Bit2 --- Drive A/B

Bit1 --- External FDD

BitO --- Internal FDD

= Plasma

= 12MHz

= OFF

= 1.6MB

= 1

= Normal

= OFF

= 2DD type

[DIP]

SW1 --- Auto SW = Disable

SW4 --- Font Mode = Single

SW6 --- European Font= Other

SW7-10 --- Monitor Type = RGB 350

3-6

3.5 MEMORY TEST

Subtest 01 RAM constant data (Execution time: 30 seconds)

This test writes constant data to Memory, and then reads and compares them with the original data.

The constant data are "FFFFH", "AAAAH", "5555H",

"OlOlH" and "OOOOH".

Subtest 02 RAM address seconds) pattern data <Execution time: 10

This test makes the segment address and offset address by XORing, and then writes the address pat tern data and reads and compares them wi th the original data.

Subtest 03 RAM refresh (Execution time: 20 seconds)

This test wr i tes constant data in 256 bytes length to Memory, and then reads and compares it with the original data. The constant data are "AAAAH" and

"5555H". A certain interval time will be taken between the write and the read operations.

Subtest 04 Protected mode (Execution time: 78 seconds)

This test writes fixed data and address data to memory (256 kbytes to MAX 640 kbytes or 1 Mbytes to

MAX. Mbytes ) in protect mode, and then reads and compares it with the original data.

Subtest 05 Protected mode (3MB) (Execution time: 74 seconds)

This test writes fixed data and address data to memory

(1

Mbytes to 4 Mbyts) in protect mode, and then reads and compares it with the original data.

Subtest 06 LIM (Expansion memory) (Execution time: 84 seconds)

Run the same test as subtest 04 for the expansion memory page' frame address (DO OOOH) and the block select register (208H/2l8H) and memory size (3

Mbytes + 384 kbytes). This performed for every 64 kbytes.

3-7

3.6 KEYBOARD TEST

Subtest 01 Pressed key display

Hote: Execute the test when Num-lock key is off. If this key is on, the test cannot be carried out.

When the keyboard layout (as shown on the display, press a certain whether the corresponding key on changed to the character

"*".

below) is drawn key and check the screen is

When the same key again, i t becomes to be the original state so that it is able to confirm the self-repeat function.

The following three keys are exceptions, and each key is changed to the character

"*"

only when it is pressed, and if released, it gets back to the original state.

Ctrl key, Shift key, Alt key

KEYBOARD TEST IN PROGRESS 30100

IF TEST OK, PRESS [DEL] THEN [ENTER] KEY

3-8

Subtest 02 Pressed key code display

Scan code, character code, and key top name are displayed on the screen by pressing a certain key as shown below.

Some keys such as Ins, Caps lock, Num lock, Scroll lock, Alt, Ctrl, and shift key blink on the screen when each one is pressed.

Each scan code, character code and key top name described in the TABLE 3-2.(Next page)

KEYBOARD TEST IN PROGRESS 302000

Scan code = XX

Character code = XX

Key top = XXXX

Ins Lock Caps Lock Num Lock Scroll Lock

Alt Ctrl Left Shift Right Shift

PRESS [ENTER] KEY

3-9

TABLE 3-2 Scan Code, Character Code, and Key Top Names

KEY TOP

,

Y u i

0

P

[

1 a s d f

9 h

J k

I

~-

-~ q w e r t

1

2

7

8

9

3

4

5

6

0

-

=

\

SCAN CODE

15

16

17

18

19

11

12

13

14

OC

00

2B

OE

OF

10

1A

18

1 E

1F

20

21

22

23

24

25

26

27

29

02

07

08

09

OA

OB

03

04

05

06

CHARACTER

CODE

60

31

32

33

34

35

36

37

38

39

30

20

3D

5C

08

09

71

77

65

72

74

79

75

69

6F

70

58

50

61

73

64

66

67

68

6A

68

6C

3B

3-10

TABLE 3-2 Scan Code, Character Code, and Key Top Name

/

Space

F2

F4

F6

F8

FlO

Fl

F3

F5

F7

F9

Esc

Home

E-

End

Uper

Lower

Pg Up

~

Pg Dn

Del

Sys Req

Prt Sc

-

+

KEY TOP v b n m

,

, z x c

SCAN CODE

35

39

3C

3E

40

42

44

3B

3D

30

31

32

33

34

28

2C

2D

2E

2F

3F

41

43

01

47

4B

4F

48

50

49

4D

51

53

85

37

4A

4E

CHARACTER

CODE

20

00

00

00

00

00

00

00

00

00

00 lB

00

00

00

00

00

00

00

00

00

00

2A

2D

2B

27

7A

78

63

76

62

6E

6D

2C

2E

2F

3-11

3.7 DISPLAY TEST

Subtest 01 VRAM read/write (Execution time: 1 second)

This test writes constant data (FFFFH, AAAAH, 5555H,

OOOOH) and address data to the video RAM (256 kbytes) and SRAM (2 kbytes); it then reads the data out and compares it the original data.

Subtest 02 Character attributes (Execution time: 1 second)

This test is for checking the various types of displays:

Normal Display

Intensified Display

Reverse Display

Blinking Display

In the case of color displays, all seven colors used

(blue, red, magenta, green, cyan, yellow, white) are displayed. The background and foreground colors can then be checked for br ightness. The display below appears on the screen when this test is run.

CHARACTER ATTRIBUTES

NEXT LINE SHOWS NORMAL DISPLAY.

NNNNNNNNNNNNNNNNNNNNNNNN

NEXT LINE SHOWS INTENSIFIED DISPLAY.

I I I I I I I I I I I I I I I I

NEXT LINE SHOWS REVERSE DISPLAY.

RRRRRRRRRRRRRRRRRRRRRRRRRRRRRRR

NEXT LINE SHOWS BRINKING DISPLAY.

BBBBBBBBBBBBBBBBBBBBBBBBBBBBBBB

BLUE

RED

MAGENTA

GREEN

CYAN

YELLOW

WHITE

PRESS [ENTER] KEY

3-12

Subtest 03 Character set (Execution time: 1 second)

In this test the character code (OOH to FFH) characters are displayed in the 40 x 25 pixel mode as shown below.

CHARACTER SET IN 40X25

I J .

~

, - . / 0 1 2 3 4 5 6 T B ' : :

< >

!@lA a

C 0 E F 0 HI J i l L " NO

PO R STU V W x Y Z ' "

J " _ ' • ~ c _ • , , • I

I k I . A . ,

~ r

I I • • •

I J •

I : J ~

A

~ a , a a ~ • ~ a

I , i f 1 llE.~; • ~ G • YO 0 C ~k~ r

.i i 4 ,; ;; H 9 ! , r -.

I,~ I.~ i . . . ill .;i

-8 -.. "'3 I,.J

J d , ~1--1 r

II

I .• :-~...I.---'YT'· b. f'

.--a +J

I . . . . . . . .

~ r

n 1:

II .. r

I • n , _ • E n

.. ± ?: 5. rJ +

=:: • • , . . A I •

PRESS [ENTER] KEY

Subtest 04 80*25 Character display (Execution time: 1 second)

In this test the shift caracters are displayed in the 80 x 25 pixel mode as shown below.

80*25 CHARACTER DISPLAY

012345678901234567890123u 678901234567890123456789

!U;$~Lj()*~,-,/01234S67 JXYZC¥]A_"abcdet9hij~lmno

!u=S~&j()*+,-./01234567f XYZC¥]A "abcdet9hijklmno~

.. !;$:".&. ' ( ) *+, -,/012345678' {YZC¥]" _ -: abcde t 9h i jk I mncpq

~$~~I()*+,-,/01234Sb787 YZC.JA_"abcdeT9hijkimncpq~

$~&.' ()*+,-./0123456789 ZC.]"_ "abcdet9hijklmncpqrs

~L' ()*+,-./0123456789: :C¥]A_ "abcdet9hijklmno~~~st

&

J ( )

*

T" , ,

10 123456789 : j . • ] A _

"a bed e t 9 h i j kim n

0

~

'1

~

5 t u

'()*+,-./0123456789:j(: ]A_"abcdet9hijklmnc~~rstuv

()*+,-,/012345b789:j(=> \_"abcdet9hijklmnc~~rStuvw

)*+,-./012345b789: j(=>?Q "abc~et9hijklmnop~r5tuvwx

*+.-,10123456789: j(=>?CiA

~ocdet9hijklmnop~r5tuvwxy

T,

-.10 :23456789: j

(=> ?CiA8C. cde t 9h i jk I mnOpqr s t:..:vwxy::

PRESS [ENTER] KEY

3-13

Subtest 05 320*200 Graphics display (Execution time: 3 seconds)

This test displays two sets of color blocks for the color display in the 320 x 200 dots graphics mode

(Mode 4 and D) as shown below.

Color set 0: Green, red, yellow

Color set 1: Cyan, Magenta, White

320*200 GRAPHICS DISPLAY [X]

PRESS [ENTER] KEY

Subtest 06 640*200 Graphics display (Execution time: 3 seconds)

This test displays the color blocks for the black and white display in the 640 x 200 dot graphics mode

(Mode 6 and E) as shown below.

640*200 GRAPHICS DISPLAY [X]

EVEN DOTS

DRIVEN

ODD DOTS

DRIVEN

ALL DOTS

DRIVEN

PRESS [ENTER] KEY

3-14

Subtest 07 640 x 400 Graphics display (Execution time: 5 seconds)

This test displays the color blocks for the black and white display in the 640 x 350 and 640 x 400 dot graphics mode (Mode 10/ 74) as shown below.

Note: Mode 74 is not applicable when the external display is selected.

640*XXX GRAPHICS DISPLAY : [XX]

EVEN DOTS

DRIVEN

ODD DOTS

DRIVEN

ALL DOTS

DRIVEN

PRESS [ENTER] KEY

Subtest 08 Display page (Execution time: 15 seconds)

This test confirms that the pages can be changed in order (page 0 to page 7) in the 40 x 25 pixel mode.

DISPLAY PAGE a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a

3-15

Subtest 09 "H" pattern display

This test displays H characters on the entire screen, as shown below.

HHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHH














~HHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHH

Subtest 10 Special attribute test

This test displays the following display.

CRT/Caps/Num/Scroll LED test 1

(1) Press [ Caps Lock 1 key! ••• Caps (on/off)

(2) Press [ Num lock] key! •.. Num (on/off)

(3) Press [Scroll lock 1 key! •.• Scroll (on/off)

(4) Press [ Fn + End] key! .•. CRT (on)

(5) Press [ Fn + Home] key! ••. CRT (off)

Press [ENTER] KEY

3-16

3.8 FLOPPY DISK TEST

CAUTION: Before running the floppy disk test prepare a formatted work disk and remove the diagnostics disk then insert the work disk to the FDD.

Subtest 01 Sequential read (Execution time: 50 seconds)

This test performs a cyclic redundancy check with a continuous read operation of all track on a floppy disk.

2D (Double-sided, double density): Track 0 to 39

2DD (Double-sided, double density, double track):

Track 0 to 79

Subtest 02 Sequential read/write (Execution time: 115 seconds)

This test writes data to all tracks (as defined above) continuously and then reads the data out and compares it to original data.

(The data pattern is B5ADADH repeated.)

Subtest 03 Random address/data (Execution time: 12 seconds)

This test writes random data to random address on all tracks (as defined in subtest 01) and then reads the data out and compares it with the original data.

Subtest 04 Write specified address (Execution time: 1 second)

This test writes data specified by keyboard to tracks, heads, and address specified by the keyboard.

Subtest 05 Read specified address (Execution time: 1 second)

This test reads data from tracks, heads, and address specified by keyboard.

3-17

3.9 PRINTER TEST

CAUTION: A printer (IBM compatible) must be looked up to the system in order to execute the test.

Subtest 01 Ripple pattern (Execution time: 110 seconds)

This test prints character for code 20H through 7EH line by line while shifting one character to the right at the beginning of each new line.

! "#$%&' ( ) '"+, -. /0123456789: ; l

¥] - _' abcde

!"#$%&' ('''+,-./01234:;ti'jd~:;''=>'?ICIIABl:DEI!'GHIJKLMNOPQRSTUVWXYZl'tj_·abcder

"#$%&' ( ) "+, - ./0123456789: ; <=>?:glABCDEFGHIJKLMNOPQRSTUVWXYZ [¥ J - _ abcdefg.

#$%&' ( ) *+, - ./0123456789: ; [¥] - _' abcdefgh

$%&' ()*+,-./012345678 Q · '<=>?@ABCDEFGHIJKLMNOPQRSTUVWXYZ[¥]-_'abcdef-

%&' ()*+,-./Ol?~· -or,HIJKLMNOPQRSTUVWXYZ[¥]-_-abc~

&'()*+

,

'

-··..,OPQRSTUVWXYZ(¥)-_·""

Subtest 02 Function (Execution time: 15 seconds)

This test prints out various print type as shown below.

Normal Print

Compressed Print

Double Strike Print

Double Width Print

Emphasized Print

All Characters Print

PRINTER TEST

1. THIS LINES SHOWS NORMAL PRINT.

2 . T H I S L I N E SHOWS DOUBLE WIDTH P R I N T .

3. THIS LINE SHOWS COMPRESSED PRINT.

4. THIS LINE SHOWS EMPASIZED PRINT.

5. THIS LINE SHOWS DOUBLE STRIKE PRINT.

ALL CHARACTERS PRINT

!"#S%&' ()0+,-./0123456789: ;<=>?~ABCDEFGHIJKLMNOPQRSTUVWXYZ(Yl'_ abcdefgn~J~lmn opqrstuvwxyz{j )-

Subtest 03 Wrap around (Execution time: 1 second)

Note: A printer wraparound connector is necessary for executing this test. Wiring diagram of the printer wrap around connector described in the part 3.24.

Checks the data, control, and status lines with the printer wrap around connector.

Operations for the test is as follows.

1. After type the channel number, the following message will appear.

[[[ Change DIPSW-2

ON J JJ ?

2. Turn the DIP switch-2 on, then press Enter.

3. After f innished the test, turn the DIP swi tch-2 off.

3-18

3.10 ASYNC TEST

For subtest 01 to subtest 05, transmission is done as follows in the communication.

Speed: 9600 BPS

Data: 8 bits + parity (EVEN)

1 stop bit

20H to 7EH

Subtest 01 Wrap around (channell) (Execution time: 1 second)

Note: An RS232C wrap around connector must be connected to channell to execute this test. RS232C wrap around connector wiring diagram described in part 3.24.

Performs a data send/receive test with the wrap around connector for the channell.

Subtest 02 Wrap around (channel 2) (Execution time: 1 second)

Performs the same test as subtest 01 for the channel

2.

Subtest 03 Point to point (send) (Execution time: 1 second)

Note: This test can be executed on condition that the both send and receive sides are set in the same condition, and also connected together by RS232C direct cable (Wiring diagram described in part

3.22. ). Subtest 03 must be executed together wi th subtest 04 and vice versa.

In this test, the data (20H to 7EH) are sent as one block from one side to the other, and then returned from the later one to the first side again.

This test is used to check wheter the returned data are same as the original ones.

Subtest 04 Point to point (receive) (Execution time: 1 second)

This test is exactly the same as subtest 03 except that the data flow is completely opposite.

3-19

Subtest 05 300/1200 BPS card modem loopback (Execution time: 5 seconds)

Note: If there is no modem card in the system, this test can not be executed.

This test is used to check whether the data, which is from the modem to the RS232C inside the system, is same as the original data which had first been sent to the modem card.

Subtest 06 Card modem on-line test (Execution time: 10 seconds)

Note: After the system is connected to the PBX, unless the receive side is in the same status as the send side, the test cannot be executed.

In this test, first some data are sent to the modem card from the RS232C inside the system, then the data is again sent to the other system through the

PBX (Private Branch Exchange).

This test is used whether the returned data from the other system are same as the original data.

Subtest 07 Dial tester test (Execution time: 60 seconds)

Note: To execute this test, a dial tester must be connected to the system.

This test is carried out by sending the pulse dial and tone dial twice automatically.

[Pulse dial]: "1-2-3-4-5-6-7-8-9-0-1-2"

[Tone dial]: "1-2-3-4-5-6-7-8-9-*-0-#"

3-20

3.11 BARD DISK TEST

CAUTION: The contents of the hard disk will be erased when subtest 02, 03, 04, 06, 08 and 09 is run. Before running the test, transfer the contents of the hard disk on the floppy disk. This can be done with the

MS-DOS BACKUP command. After the test, enter the MS-DOS

FDISK command, which will set the partition. Then enter the MS-DOS FORMAT command. (See the MS-DOS manual for details.)

Subtest 01 Sequential read (CYL.0-614,CYL.614-0) time: 8.5 minutes)

(Execution

This test performs forward reading of contents from track 0 to track 610 and then performs reverse reading of the contents from track 610 to track O.

Subtest 02 Address uniquence (Execution time: 13 minutes)

This test writes the address data(sector by sector) track by track, then reads the data and compares i t to the original data.

Following three kinds of read operations are performed.

(Forward sequential, Reverse sequential, Random)

Subtest 03 Random address/data (Execution time 30 seconds)

This test write random data in random units to random address (cylinder, head, sector) and then reads the data out and compares it to the original data.

Subtest 04 Cross talk & peak shift (Execution time: 13 minutes)

This test writes the eight types of worst pattern data (shown below) to cylinders then reads the data while shifting cylinder by cylinder.

Worst pattern data

1. B5ADAD . . . . . . .

2. 4A5252 . . . . . . .

3. EB6DB6 . . . . . . .

4. 149249 . . . . . . .

5. 63B63B . . . . . . .

6. 9C49C4 . . . . . . .

7. 2DB6DB . . • . . . .

8. D24924 . . . . • . .

3-21

Subtest 05 Write/Read/Compare (CE) (Execution time: 2 seconds)

This test writes B5ADAD worst pattern data to the CE cylinder and then reads the data out and compares it to the original data.

Subtest 06 Write specified address (Execution time: I second)

This test writes specified data to a specified cylinder and head.

Subtest 07 Read specified address (Execution time: I second)

Subtest 08

This test reads data which has been written to a specified cylinder and head.

ECC circuit seconds)

(CE cyl inder) (Execution time: 2

This test checks correction) circuit cylinder and head. the ECC functions

(Error to a check and specified

Subtest 09 Sequential write

This test writes specified data of the two bytes to all cylinder.

3-22

3.12 REAL TIMER TEST

Subtest 01 Real time

A new data and time can be input during this test when the current data and time are displayed.

Operations for the test is as follows.

1. After executing the test, the following message will appear.

901000 REAL TIME TEST

Current date:

Current time:

xx-xx-xxxx

XX:XX:XX

Enter new date:

PRESS [ENTER] KEY TO EXIT TEST

2. If current date is not correct, input the current new date. Press the Enter, the Enter new tiae: message will appear.

3. If current time is not correct, input the current new time. Press the Enter, return to the subtest menu of the REAL TIME TEST.

Subtest 02 Backup memory (Execution time: 1 second)

This test writes data (FFH, AAH, bytes of the backup memory, and compares it with the original data.

55H, OOH) to 64 then reads and

Subtest 03 Real time carry

CAUTION: When this test is executed, the current data and time is erased.

This test checks whether the real-time clock increments the time displayed correctly (month, day, year, hour, minute, second).

3-23

3.13 NDP TEST

Note: This test cannot be run if there is no NDP mounted on the system PCB.

Subtest 01 NDP test (Execution time: 1 second)

This test checks the control word, status word, bus, and addition/multiplication functions.

3.14 EXPARSION UNIT TEST

Note: If there is no expansion box connected to the system, this test cannot be executed.

Subtest 01 Box wrap around seconds)

(8 bits bus) (Execution time: 3

Note: As this test required a special tool to be executed, it can not be carried out here.

Subtest 02 Box mono video ram (Execution time: 1 second)

Note: If there is no monochrome display card in the expansion box, this test cannot be executed.

This test writes data (FF, AA, 55, OOH) into the monochrome display memory (BOOOOH to BOF9FH), then reads the data out and compares it to the original data.

Subtest 03 Wrap around test (16 bit bus)

Note: As this test required a special tool to be executed, it can not be carried out here.

3-24

3.15 ERROR CODE AND ERROR STATUS HAMES

The following table shows the error code and error status names.

TABLE 3-3 Error Code and Error Status Names

DEVICE NAME ERROR CODE

EVERYTHING FF

ERROR STATUS NAME

Compare error

SYSTEM

MEMORY

FDD

RS232C

PRINTER

01

01

02

01

02

04

08

10

20

40

80

88

33

34

36

01

08

10

20

40

80

01

08

09

10

20

40

02

03

04

06

60

80

EE

ROM Checksum Error

Parity Error

PROTECTED MODE NOT CHANGE ERROR

Bad Command

Address Mark Not Found

Write Protected

Record Not Found

Media removed on dual attach card

DMA Overrun Error

DMA Boundary Error

CRC Error

FDC Error

SEEK ERROR

FDD not drive

Time Out Error (Not Ready)

Write buffer error

DSR Off Time Out

CTS Off Time Out

RX EMPTY Time Out

TX BUFFER FULL Time Out

Parity Error

Framing Error

Overrun Error

Line Status Error

Modem Status Error

NO CARRIER (CARD MODEM)

ERROR (CARD MODEM)

NO DIAL TONE (CARD MODEM)

Time Out

Fault

Select Line

Out Of Paper

Power off

Busy Line

3-25

TABLE 3-3 Error Code and Error Status Names

DEVICE NAME ERROR CODE

HDD

OA

OB

10

11

20

40

80

AA

01

02

04

05

07

09

BB

CC

EO

FO

NDP 01

02

03

04

05

06

ERROR STATUS NAME

Bad command error

Bad address mark

Record not found

HDC NOT RESET

Drive not initialize

DMA Boundary error

Bad sector error

Bad track error

ECC error

ECC recover enable

HDC error

Seek error

Ti me out error

Drive not ready

Undefined

Write fault

Status error

Not sense error (HW.code

=

FF)

No NDP

Control word error

Status word error

Bus error

Addition error

Multiplication error

3-26

3.16 HARD DISK FORMAT

There are two types of hard disk formatting:

1. Physical formatting

2. Logical formatting

This orogram is for physical formatting of the hard disk; i t can execute the following items.

1. All track FORMAT

2. Good track FORMAT

3. Bad track FORMAT

4. Bad track CHECK

Note: Execution of the program cannot be performed unless the

HDD switch is on.

CAUTION: The contents of the hard disk will be erased when this program is run. Before running the program, transfer the contents of the hard disk on to a floppy disk. This can be done with the MS-DOS BACKUP command. (See the


3.16.1 proqram description

1. All track FORMAT

Performs physical shown below.

(Execution time: 15 minutes) formatting of hard disk in the manner

Sector sequences: 3

Cylinders: o to 614

Heads: o to 7

Sectors: 1 to 17

Sector length:

Bad track:

512 bytes per sector

MAX. 51 tracks

2. Good track FORMAT (Execution time: 1 second)

Executes the formatting of a specified cylinder and track as a good track.

3. Bad track FORMAT (Execution time: 1 second)

Executes the formatting of a specified cylinder and track as a bad track.

4. Bad track CHECK

Checks for bad tracks on the displayed.

(Execution time: 1 and 1/2 minutes) tracks by performing a read operation for all hard disk; a list of bad tracks is then

3-27

3.16.2 Operations

CAUTION: After physical formatting is finished, enter the MS-DOS

FDISK command, which will set the partition. Then enter the MS-DOS FORMAT command. (See the MS-DOS manual for details.)

1. After pressing 2 and Enter to select from the DIAGNOSTICS

MENU, the following display will appear.

DIAGNOSTIC - HARD DISK FORMAT: VI.O

I - All track FORMAT

2 Good track FORMAT

3 Bad track FORMAT

4 Bad track CHECK

9 Exit to DIAGNOSTICS MENU

Press [NUMBER] key?

2. All track FORMAT Selection

(1) When All track FORMAT (1) is selected, the following message will appear.

Interleave number (3/1-9)

?

(2) Select an interleave number. (Usually select 3.) Type the number and press Enter. The following message will appear.

Drive number select

(1:11. 2:12) ?

(3) Select a drive number. Type the drive number and press

Enter. The following display will appear.

[HOD TYPE]

[HOD TYPE]

[HOD TYPE]

CYLINDER

HEAD

SECTOR

= XXX

= X

= XX

[WARNING: Current DISK data will be completely destroyed]

[[cylinder,head = XXX X]]

3-28

(4) After checking all cylinders of following message will appear. If the following message will appear. the hard disk, the found the bad track,

Press [Bad track number (CCCH) key

?

(5) If the hard disk has the bad track except the displayed number, type a bad-track number (four digits) and press

Enter. (The first three digits are the cylinder number and the last digit is the head number.) If there is a bad track on the hard disk, press the Enter only. This executes the formatting of all tracks.

(6) After formatting the hard disk, the [[cylinder r head = xxx

X)) message wi 11 appear; then all cyl inders of the hard disk are checked. If there is a bad track on the hard disk, the bad track number will be displayed on the screen.

(7) Format complete message will then appear.

(8) Press the Enter to return to the HARD DISK FORMAT menu.

3-29

3. Good track FORMAT or Bad track FORMAT Selection

(1) When Good track FORMAT or Bad track FO~ is selected, the following message will appear.

Interleave number (3/1-9)

?

(2) Select an interleave number. (Usually select 3.) Type the number and press Enter. The following message will appear.

Drive number select

(1:11, 2:12) ?

(3) Select a drive number. Type the drive number and press

Enter. The following message will appear.

[HOD TYPE]

[HOD TYPE]

[HOD TYPE]

CYLINDER

HEAD

SECTOR

= XXX

= X

= XX

Press [Track Number (CCCH)] key?

(4) Type a track number (four digits) and press Enter.

(The first three digits are the cylinder number and the last digit is the head number.) This executes the formatting of good tracks or bad tracks.

Rote: This program can format only one track per operation. If it is desired to format several good tracks or bad tracks, repeat the operation as many times as nessary.

(5) After formatting the track of the hard disk, the Format complete message will appear.


3-30

4. Bad track CHECK Selection

(l) When Bad track CHECK is selected, the following message will appear.

Drive number select (l:ll, 2:12)

?

( 2) Sel ect a dr i ve number. Type the dr i ve number and press

Enter. When the following message appears, and bad tracks of the hard disk are checked.

[HOD TYPE]

[HOD TYPE]

[HOD TYPE]

CYLINDER

HEAD

SECTOR

= XXX

= X

= XX

[[cylinder,head

=

XXX X]]

(3) After checking the bad tracks of the hard disk are checked, the Format complete message will appear.


3-31

3. 17 SEEK TO LANDIRG ZONE (BDD)

3.17.1 Program description

When moving the uni t, if an HDD head touches a da ta area, the data wi 11 be lost. In order to protect the data, this program moves HDD heads to safe areas. Theese areas called .. landing zones."

Note: When the built-in T3200 hard disk does not issue a command to the HDD for an interval of 5 seconds, the HDD heads move to a landing zone automatically.

3.17.2 Operations

1. After pressing .. 3" and Enter to select from the DIAGNOSTICS

MENU. The program is then automatically executed and the following message will appear.

Landing seek completed. (HOO#!)

Press [enter] key.

2. After pressing Enter, return to the DIAGNOSTICS MENU.

3-32

3.18 BEAD CLEANING


This program executes head loading and seek/read operations for head cleaning. A cleaning kit is necessary for cleaning the FDD head.

3.18.2 Operations


MENU, the following message will appear.

HEAD CLEANING

Mount cleaning disk(s) on drive(s).

Press any key when ready.

2. After above message appears, remove the Diagnostics disk, insert the cleaning disk, and press any key.

3. When the following message appears, FDD head cleaning will begin.

HEAD CLEANING

Mount cleaning disk(s) on drive(s).


Cleaning start

4. When cleaning is finished, the display automatically returns to the DIAGNOSTICS MENU.

3-33

3.19 LOG UTILITIES


This program logs error information generated, while a test is in progress; the information is stored in the RAM.

However if the POWER switch is turned off the error information will be lost. The error information itself is displayed as the following.

1. Error count (eNT)

2. Test name (TEST)

3. Subtest number (NAME)

4G Pass count (PASS)

5. Error status (STS)

6. Address (FDD, HDD 1 or memory; ADDR)

7. Write data (WD)

8. Read data (RD)

9. Error status name

This program can store data on a floppy disk or output information to a printer.

3-34

3.19.2 Operations


MENU, the error information logged in the RAM or on the floppy disk is displayed as shown below.

XXXXX ERRORS

CNT TEST NAME PASS STS ADDR WD RD ERROR STATUS NAME

001

FDD

02 0000 103 00001 00 00

FDD - WRITE PROTECTED

001

FDD

01 0000 180 00001 00 00

FDD - TIME OUT ERROR

1

Read data

Error status

Pass count Write data

Error status name

Sub test number

Test name

Error count

[[1:Next,2:Prev,3:Exit,4:Clear,5:Print,6:FD LogRead,7:FD LogWrite II

2. Error information to be displayed on the screen can be manupulated with the following key operation.

The 1 key scrolls the display to the next page.

The 2 key scrolls the display to the previous page.

The 3 key returns the display to the DIAGNOSTIC MENU.

The 4 key erases all error log information in RAM.

The 5 key outputs error log information to a printer.

The 6 key reads log information from a floppy disk.

The 7 key writes log information to a floppy disk.

3-35

3.20 RUNNING TEST

3.20.1 Program descripti~n

This program automatically runs the following tests in sequence.

1. System test (subtest number 01)

2. Memory test (subtest number 01, 02, 03, 04, 06)

3. Display test (subtest number 01 to 08)

4. FDD test (subtest number 02)

S. Printer test (subtest number 03)

6. Async test (subtest number 01)

7. HDD test (subtest number 01, OS)

8. Real timer (subtest number 02)

When running an FDD test, this system automatically decides whether there are one or two FDDs.

3.20.2 Operations

CAUTION: Do not forget to load a work disk. If a work disk is not loaded, an error will be generated during FDD testing.

1. Remove the diagnostics disk and insert the work disk into the floppy disk drive.

2. After pressing 6 and Enter to select from the DIAGNOSTIC

MENU, the following message will appear.

Printer wrap around test (YIN) 1

3. Select whether to execute the printer wraparound test (Yes) or not (No). Type the desired Y or N and press Enter key.

(If Y is selected, a wraparound connector must be connected to the pr inter connector on the back of the unit.) The following message will appear.

Async wrap around test (YIN) 1

4. Select whether to execute the test (Yes) the desired Y or N and press Enter Key. an RS232C wraparound connector must be

COMMS connector on the back of the unit.) or not (No). Type

(If Y is selected, connected to the

5. This program is repeated continuously. To stop the program, press Ctrl + Break key.

3-36

3.21 FDD UTILITIES


These programs format and copy floppy disks, and display dump list for both the FDD and the HDD.

1. FORMAT

This program can format floppy disk (5.25"/3.5") as follows.

(a) 20: Two-sided, double-density, 48 TPI, MFM mode, 512 bytes,

9 sectors/track.

(b) 200: Two-sided, double-density, double-track, 96 TPI, MFM mode, 512 bytes, 15 sectors/track.

(c) 2HD: Two-sided,high-density, double-track, 96/135 TPI, MFM mode, 512 bytes, 15 sectors/track.

2. COpy

This program copies floppy disks.

Copy with one FDD (Drive A)

Copy with two FDDs (Drive A to Drive B)

3. DUMP

This program display the contents of floppy disks (both 3.5" and

5.25") and hard disks (designated sectors).

3.21.2 Operations

1. After pressing 7 and Enter key to select from the

DIAGNOSTICS MENU, the following display will appear before program execution.

[FDD UTILITIES]

1 FORMAT

2 COPY

3 DUMP

9 EXIT TO DIAGNOSTICS MENU

PRESS [I] - [9] KEY

3-37

2. FORMAT Selection

(1) When FORMAT is selected, the following message appears.

DIAGNOSTICS - FORMAT

Drive number select (l:A, 2:8) ?

(2) Select a drive number. Type the number and the following message will then appear.

Type select (O:2DD-2DD,1:2D-04DE,2:2D-08DE,3:2HD-08DE)

(3) Select a media-drive type number. Type the number and the following message will appear.

Warning: Disk data will be destroyed.

Insert work disk in to drive A :


( 4 ) Remove the diagnostics disk from the FDD and insert the work disk; press any key.

The Format start message will appear; formatting is then executed. After the floppy disk is formatted, the following message will appear.

Format complete

Another format (1:Yes/2:No) ?

(5) If you type 1 and press Enter key, the display will return to the message in (3) above. If you type 2 the display will return to the DIAGNOSTICS MENU.

3-38

3. COpy Selection

(1) When COpy is selected, the following message will appear.

DIAGNOSTICS - COPY

Type select (O:2DD-2DD,1:2D-04D,2:2D-08DE,3:2HD-08DE) ?

(2) Select a media/dr i ve type number. Type the number. The following message will then appear.

Insert source disk into drive A


(3) Remove the diagnostics disk from the FDD and insert the source disk; press any key. The Copy started message will then appear. After that, the following message will appear.

Insert target disk into drive A


(4) Remove the source disk from the FDD and insert the work disk (formatted); press any key. When coping can not be done with one operation, message (2) is displayed again.

Repeat the operation. After the floppy disk has been copied, the following message will appear.

Copy complete

Another copy (1:Yes/2:No)

?

(5) If you type 1 the display will return to the message in

(1) above. If you type 2 the display will return to the

DIAGNOSTICS MENU.

3-39

4. DUMP Selection

(1) When DUMP is selected, the following message will appear.

[HDD&FLOPPY DISK DATA DUMP] format type select (O:2DD,1:2D,2:2HD,3:HDD) ?

(2) Select a format type number. Type the number. If 3 is selected, the dump lists for the hard disk are displayed automatically.

0: Display a dump list for a floppy disk (2DD)

1: Display a dump list for a floppy disk (2D).

2: Display a dump list for a floppy disk (2HD).

3: Displays a dump list for a hard disk.

(3) If 0, 1, or 2 is selected, the following message will appear.

Select

FDD number (1:A/2:B)

?

( 4) Select an FDD drive number; the following message wi 11 then appear.

Insert source disk into drive A


(5) Remove the diagnostics disk from the FDD and insert a source disk; press any key. The Track number 11 message will then appear. Type the track number and press Enter.

(6) The Head number? message will then appear. Type the head number and press Enter.

(7) The sector number ?1 message will then appear. Type the sector number and press Enter. The dump list for the floppy disk will be displayed.

(8) After a dump list appears on the screen, the Press number

key (1:up,2:down,3:end) 1 message will appear.

1. Displays the next sector dump.

2. Displays a previous sector dump.

3. Displays the following message.

Another dump (1:Yes/2:No)

?

(9) If you type 1 the display will return to the message shown after (4) above. If you type 2 the display will return to the DIAGNOSTICS MENU.

3-40

3.22 SYSTEM CONFIGURATION


This program displays the following system configuration.

1. Memory size

2. Display type

3. Floppy disk drive number

4. Async port number

5. Hard disk drive number

6. Printer port number

7. Co-processor number

8. Extended memory size

3.22.2 Operations

After pressing 8 and Enter key to select from the DIAGNOSTICS

MENU, the following display will appear.

SYSTEM CONFIGURATION

* 640KB MEMORY

* PLASMA DISPLAY

* 1 FLOPPY DISK DRIVE(S)

* 1 ASYNC ADAPTOR

* 1 HARD DISK DRIVE(S)

* 1 PRINTER ADAPTOR

* 0 MATH CO-PROCESSOR

* XXXXKB EXTENDED MEMORY

PRESS [ENTER] KEY

Press Enter key to return to the DIAGNOSTICS MENU.

3-41

3.23 SETUP


This program displays the following items, and then can change i t by automatically or manual.

1. Floppy disk drive number and type

2. Hard disk drive number and type

3. System memory size

4. Extended memory size

5. Expanded memory size

6. External display card status

3.23.2 Operations

1. After pressing a and Enter to select the DIAGNOSTICS MENU, the following display will appear.

[[ System setup ]]

1. Floppy disk drives = 1 drive#! type driveN2 type

= 2

= 0

720KB/l.2MB

No drive

2. Hard disk drives driveNl type

= 1

= 4- Cyl=614,h=8,S/T=17

3. Memory size

System memory

Extended memory

Expanded memory

= 640KB

= OMB

= 384KB + OMB

4. External display card = None

Select setup change (l:no/2:yes) ?

2. Select the (yes) or (no). Type the number and press Enter.

If select (yes), the following message will appear.

If select (no), load the system again.

3-42

3. Select the (auto) or (manual). Type the number and press

En ter. If select the (manual), the following message wi 11 appear.

Floppy disk setup

0: No drive

1: 360KB

2: 720KB/1. 2MB

(1) Floppy disk driveR1 type

=

2 ?

4. Select the floppy disk drive#l type. Type the number and press Enter. (In the case of the floppy disk drivr type is

720KB or 1.2MB, press Enter only.)

The following message will appear.

0: No drive

1: 360KB

2: 720KB/1. 2MB

(2) Floppy disk driveR1 type

=

0 ?

5. Select the floppy disk drive#2 type. Type the number and press Enter. (In the case of the floppy disk drive#2 is no drive, press Enter only.) The following message will appear.

Hard disk setup

1

(3) Is hard disk available? (YIN)

3-43

6. Select the (YES) or (NO). Type "Y" or "N" and press the

Enter. Return to the SETUP menu.

Note: If the system has a optional following message will appear. memory card, the

Extended memory setup ]

0: No memory

1: 0.5MB

2: 1MB

3: 1.5MB

4: 2MB

5: 2.5MB

6: 3MB

(4) Extended memory size

=

06

? [

3MB]

(Expanded memory size [384KB+ OMB])

7. Select the expanded memory size. Type the number and press the Enter. Return to the SETUP menu.

Note: If the DIP switch 5 is ON and the system has a optional display board to the expansion slot, the following message will appear.

[External display card type setup]

1: Color display card (40*25 column)

2: Color display card (80*25 column)

3: Monochrome display card

0: Others

(5) External display type

=

0

?

8. Select the external display card type. Type the number and press the Enter. Return to the SETUP menu.

3-44

3 • 24 WIRING DIAGRAM

1 . Printer wrap around connector

(9) + PD7

(8) + PD6

(7) + PD5

(6) + PD4

(5) + PD3

(4) + PD2

(3) + PD1

(2) + PD~

- ERROR

- AUTFD

+ SELECT

- PINIT

- STROBE

-ACK

+ PE

- SLiN

+ BUSY

( 15)

( 14)

(13)

(16)

(1)

(10)

(12)

(17)

(11 )

FIGURE 3-1 Printer Wrap Around Connector

2 . RS232C Wrap around connector

(3) TRANSMIT DATA

(7) REQU EST TO SEN D

(4) DATA TERMINAL

READY

RECEIVE DATA (2)

CLEAR TO SEND (8)

L

CARRIER DETECT (1)

L

DATA SET READY

(6)

(9)

RING INDICATE

FIGURE 3-2 RS232C Wrap Around Connector

3-45

3 . RS232C direct cable (9-pin to 9-pin)

(3) TO

(4) OTR

(7) RTS

.-

RO

.-

OSR :

CTS

(8)

(6)

RI (9)

(1) CO

(2)

(5) GNO

(2) RO

I(

GNO

TO

(5)

(3)

(1) CO

(6) OSR

(8) CTS

(9) RI

I(

:

RTS

OTR

(7)

(4)

FIGURE 3-3 RS232C Direct Cable (9-pin to 9-pin)

4. RS232C direct cable (9-pin to 25-pin)

(1) CO

(2) RO

(3) TO

(4) OTR

(5) GNO

(7) RTS

(6) OSR

(8) CTS

(9) RI

...

...

RTS

.-

.-

: CTS

OSR

RI

GNO

RO

TO

CO

(8)

(2)

(3)

(5)

(6)

(22)

(7)

(4)

(20) OTR

:

FIGURE 3-4 RS232C Direct Cable (9-pin to 25-pin)

3-46

4.1 GENERAL

This section gives a detailed description of the procedures used to replace FRUs (field replaceable units).

FRUs consist of the following:

1. Top Cover

2. PDP (Plasma Display Panel) Mask

3. PDP

4. Indicator PCB

5. Cable Guide

6. PDP Cover Assembly

7. Keyboard Unit

8. Speaker

9. Lithium Battery

10. Power Supply Unit

11. FDD (Floppy Disk Drive)

12. HDD (Hard Disk Drive)

13. Expansion Bus PCB

14. Fan

15. HDC (Hard Disk Control PCB)

16. Syatem PCB

The following points must be kept in mind:

1. The system should never be disassembled unless there is a problem (abnormal operation, etc.)

2. Only approved tools may be used.

3. After deciding the purpose of replacing the unit, and the procedures required, do not carry out any other procedures which are not absolutely necessary.

4. Be sure to turn the POWER switch off before beginning.

5. Be sure to disconnect the ac cord and all external cables from the system.

6. Follow only the fixed, standard procedures.

7. After replacing a unit, confirm that the system is operating normally.

Tools needed for unit replacement:

1. Phillips Screwdriver

2. Bladehead Screwdriver

3. Tweezers

4-1

4. 2 REMOVING/REPLACING THE TOP COVER

1. Confirm that the POWER switch is off and unplug the ac cord.

2. Turn the unit upside down and pull the handle (A) forward.

3. Remove the five screws (B) from the base assembly (C).

(B)

(A)

FIGURE 4-1 Removing the Screws from the Base Assembly

4-2

6. Open the plasma display, then remove the PDP, the indicator

PCB and cable guide as directed in part 4.3, 4.4 and 4.5.

7. Remove the keyboard unit as directed in part 4.7.

8. To remove the top cover (H), pass the four cable (1) through a slit (J) of the top cover.

At this time, remove the connector panel (K) from the top cover.

(K)

~

(J)

FIGURE 4-3 Removing the Top Cover

9. To install a top cover, follow the above procedures in reverse.

4-4

4.3 REMOVING/REPLACING THE PDP MASK


2. Open the plasma display.

3. Using tweezers or fine-pointed instruments, peel off the function label (A) and keep it in a clean place.

4. Remove the two screws (B) from the PDP mask (C), then remove the PDP mask pulling it up.

([»)

(E)

FIGURE 4-4 Removing the PDP Mask

5. To install a new PDP mask, follow the above procedures in reverse.

Note: Confirm that the eight latches (D) of the PDP cover assembly (E) are inserted into the PDP mask.

4-5

4.4 REMOVING/REPLACING THE PDP


2. Remove the PDP mask as directed in part 4.3.

3. Remove the four screws (A) on the PDP (B).

4. Lift up the PDP, then put it on the keyboard (C).

5. Disconnect the three cable (D) from the rear of the PDP.

FIGURE 4-5 Removing the PDP

6. To install a PDP, follow the above procedures in reverse.

4-6

4.5 REMOVING/REPLACING THE INDICATOR PCB, THE CABLE GUIDE AND

THE PLASMA PCB


2. Remove the PDP as directed in part 4.4.

3. Pull the ground cable (A) from the PDP cover assembly (B).

4. Lift the indicator PCB (C), then disconnect an indicator cable (D) from the indicator PCB.

4. Take off the indicator cable, ground cable, plasma display power cable (E) and plasma display signal cable (F) from the cable guide (G), then remove the cable guide.

5. To remove the volume PCB (H), remove the single screw (I) from the PDP cover assembly.

(8)

-I.-J'--II'f--(H)

(G)

(F)

- - - , t . , . ,

FIGURE 4-6 Removing the Indicator PCB and the Cable Guide

4-7

6. To install an indicator PCB and cable guide, follow the previous page procedures in reverse.

Note: When put the four cables through cable guide, be careful as following items.

(1) Put plasma display power cable (J) to your right, and plasma ground cable (K), indicator cable (L) and plasma display signal cable (M) to your left as shown in the figure 4-7.

(2) position the cable guide so that thicker part (N) comes to the upper side as shown in the figure 4-8.

(3) Put the cable guide in the top cover, then place each cable in the two ditches (0) of the PDP cover assembly as shown in the figure 4-7.

«(»

(~) (K)

(U

FIGURE 4-7 Cable position

FIGURE 4-8 Cable Guide

4-8

4. 6 REMOVING/REPLACING THE PDP COVER ASSEMBLY

1. Confirm that the POWER switch is off and unplug the ac coad.

2. Remove the indicator PCB and cable guide as directed in part

4 • 5 •

3. Remove the two screws (A) from the two hinges (B).

4. To remove the PDP cover assembly (C), shift the two hinges to inside, then turn the PDP cover assembly down and lift i t up.

FIGURE 4-9 Removing the PDP Cover Assembly

5. To install a new PDP cover assembly, follow the above procedures in reverse.

4-9

4. 7 REMOVING/REPLACING THE KEYBOARD UNIT


2. Open the plasma display, then remove the two mask panels (A) by using bladehead screwdriver.

3. Remove the two screws (B) located beneath the two mask panels and l i f t up the keyboard unit (C).

4. Release the pressure plate (0) of connector PJ 3 to disconnect the keyboard cable (E) from the system PCB (F).

FIGURE 4-10 Removing the Keyboard unit

5. To install a keyboard unit, follow the above procedures in reverse.

4-10

4.8 REMOVING/REPLACING THE SPEAKER AND THE LITHIUM BATTERY


2. Remove the top cover as directed in part 4.2.

3. To remove the lithium battery (A), disconnect the lithium battery cable (B) from the system PCB (C) and lift it up.

4. Disconnect the speaker cable (D) from the system PCB.

5. Remove the speaker (E) by pushing the plastic latch (F) outward until the speaker can be pulled out.

\.1ir--+--

(8)

(C)

FIGURE 4-11 Removing the Lithium Battery and the Speaker

6. To install a new lithium battery and speaker, follow the above procedures in reverse.

4-11

4.9 REMOVDIG/RBPLACIHG THE POWER SUPPLY UNIT


2. Remove the top cover as directed in part 4.2.

3. Disconnect the two power supply cable (A) from the system

PCB (B).

4. To remove the power supply unit (C), remove the three screws

(D) from the power supply unit.

FIGURE 4-12 Removing the Power Supply Unit

5. To install a power supply unit, follow the above procedures in reverse.

4-12

4.10 REMOVING/REPLACING THE POD


2. Remove the top cover as directed in part 4.2.

3. Remove the lithum battery (A) from the FDD base (B).

4. Disconnect the FDD cable (C) from the system PCB (D).

5. Remove the five screws (E) and ground cable (F) from the FDD base.

(A)

FIGURE 4-13 Removing the FDD Base

4-13

6. Remove the three screws (G) from the bottom of the FDD base.

(G)

FIGURE 4-14 Removing the FDD

7. To install a new FDD, follow the above procedures in reverse.

4-14

4.11 REMOVING/REPLACING THE BOD

CAUTION: The hard disk contents will remain in the old hard disk. If desired, transfer the contents of the old hard disk onto a floppy disk before replacing the hard disk.

This can be done with the MS-DOS BACKUP command. (See the MS-DOS manual for details.)


2. Remove the top cover and FDD base as directed in part 4.2 and 4.10.

3. Disconnect the HOD power cable (A) and HOC cable (B) from the HOD (C).

4. To remove the HOD, hold the HOD and remove the four screws

(D) from the bottom of the base assembly (E).

(E)

(8)

FIGURE 4-15 Removing the HOD

5. To install a new HOD, follow the above procedures in reverse.

6. Enter the MS-DOS FDISK command, which will set the partition. Then enter the MS-DOS FORMAT command. (See the


4-15

4.12 RBMOVING/RBPLACING THE EXPANSION BUS PCB AND THE FAN


2. Remove the top cover and the FDD base as directed in part

4.2 and 4.10.

3. Disconnect the fan and HOD power cable (A) from the HOD (B) and the system PCB (C).

4. Remove the two screws (D), then lift it up.

5. To remove the fan on the expansion bus PCB (E), remove the two screws (F).

(C)

(8)

FIGURE 4-16 Removing the Expansion Bus PCB and the Fan

6. To install a new expansion bus PCB and a new fan, follow the above procedures in reverse.

4-16

4.13 REMOVING/REPLACING THE BARD DISK CONTROL PCB


2. Remove the expansion bus PCB as directed in part 4.12.

3. Disconnect the HDC cable (A) from the HDD (B), then remove the two screws (C) from the HDC (D).

4. To remove the HDC from the system PCB (E) lift it up.

(C)

(8) - _ _ _

(E)

FIGURE 4-17 Removing the HDC

5. To install a new HDC, follow the above procedures in reverse.

4-17

4.14 REMOVING/REPLACING THE SYSTEM PCB


2. Remove the power supply unit, the FOO base and the expansion bus PCB as directed in part 4.9, 4.10 and 4.12.

3. Disconnect the speaker cable (A) from the system PCB (B).

4. Remove the thirteen screws (C) and three spacer (D) on the system PCB.

If the system has optional memory card, remove the optional memory card from the system PCB after removing the system

PCB. (Refer to part 4.15.)

(D)

FIGURE 4-18 Removing the System PCB

5. To install a new system PCB, follow the above procedures in reverse.

4-18

4.15 REMOVING/REPLACING THE OPTIONAL MEMORY CARD


2. Remove the keyboard unit as directed in part 4.7.

3. Remove the single screw (A) from the optional memory card

(B).

4. To remove the optional memory card, lift up a part of the system PCB and optional memory card, then disconnect the optional memory card connector (C) from the system PCB.

(8)

FIGURE 4-19 Removing the Optional Memory Card

5. To install a new optional memory card, follow the above procedures in reverse.

4-19

5.1 PCB LAYOUT

(N)

(L)

(D)

I

N :

~ ~~

11.

~

~

::t:=l.

, 1 •

D~

D,

D, a~

a~

a~

8; t~J':

~

~-

.

"'0'

•

D

· !

EJ

D§;8 q=-D=D= i l

[~t

~-

'"

~

=

:

.

·

•

11'1

I&.

N

>-

1/1

N

[~)8~

13l

0

!:! j;j

0

"-

ID

1'1

•

•

•

•

D

~!

•

; i

..

(J)

(F)

5 -1 System

PCB Connectors

5-1

(A)

(A) PJ 1 CRT connector

( B) PJ 2 PRT/FDD connector

(C) PJ 3 COMMS connector

(D) PJ 4 Expansion connector

(E) PJ 5 Speaker connector

(F) PJ 6 HDD power connector

(G)

(H)

PJ 7 Power supply connector (+ 12 V)

PJ 8 Power supply connector (+ 5 V)

(1) PJ 9 HDC connector

(J) PJ 10 PDP connector

(K) PJ 11 FDD connector

(L) PJ 12 Lithium battery connector

(M) PJ 14 Sensor connector

(N) PJ 15 External keyboard connector

5-2

5.1. 2 System PCB ICs

(G)

(E)

~ b~

-c:J;

,0, .. -

(F) - - - r l

itY

~

:::cJ.

CJ-

EJi

~

;;

;~ c

Q

•

• . +00· rill!

~

-

~r=J

EJ~

Eli

+

•

~+u.

L--=-.J

~---~

I

!

I r-:J

L::.J ~

.', d

-

~

+

~

(Q) a

;;

(C)

;;§I

-

.!.....of c """_

(J)

1'1

0

"-

I-

ID

1'1

~

+

(1

I

EJEJE]

~

""J

IL EJE)EJ

+ + _

+1 0 __

_

·;EI ..,

" I

D· 0. •

'01.1

".' ..,

L:J c=..J

!

b

•

y "

(P)

-

!~~:

:·~·----II

-..

, - . - - - -

~ e~;Q[]

D. c.J' U

(I) • c-;l=

IQ~

-

I ·

.. c-;l~

L.J c...=J

_ _

~

EJ~ ~)

:r=J

EJg: EJ

,. P..J2 ~I---·

I j

1, •

.I"

(L)

(A)

(M)

(R)

FIGURE 5-2 System PCB ICs

5-3

(B)

(A) CPU: Central processing unit (80286-12)

(B) NDP: Numeric data processor socket (option)

(C) FDC: Floppy disk controller (TC8565)

(D) PIC: Programmable interrupt controller (82C59)

(E) DMA: Direct memory access controller (82C37)

(F) PIT: Programmable interval timer (82C54)

(G) RTC: Rial time clock (46818)

(H) SIO: Serial input/output controller (T8570)

(I) VFO: Variable frequency oscillator (4108A)

(J) AGS ROM

(K) AGS RAM

(L) V-RAM (256 kbytes)

(M) Gate array (bus driver)

(N) Gate array (memory mapper)

(0) Gate array (DMA)

(P) Gate array (AGS)

(Q) Gate array (I/O controller)

(R) PEGA2

5-4

5.1.3 Keyboard control PCB

(A)

(G)

+

., II

I . , I .~

De

... a

.. ..

,~

I.'

112

•

I [ I !

. . . . . . . .

(E)

(F)

(C)

~[j

N

M u..

+ :

-

.. c:J: l:J;

FIGURE 5-3 Keyboard Control PCB

5-5

(D)

(A) PJ 1 Memory card connector

(B) PJ 2 Jumper straps

(C) PJ 3 Keyboard connector

(D) Keyboard controller (8742)

(E) System RAM

(F) BIOS ROM

(G) Gate array (EMS)

5-6

5.2 CONNECTORS

5.2.1 PRT/EXT FDD connector

13 o

0 0 0 0 0 0 0 0 0 0 0 0 0

o

0 0 0 0 0 0 0 0 0 0 0 0

14 25

FIGURE 5-4 PRT/EXT FDD Connector

TABLE 5-1 PRT/EXT FDD Connector Signal Names

2

3

4

12

13

14

15

16

5

6

7

8

9

10

11

17

18-

25

PIN

1

PD~; 110

PD1; 11 0

PD2; 110

PD3;110

PD4;110

PD5;110

PD6; 110

PD7;110

ACK;OOO

BUSY; 100

PE; 100

SELECT; 100

AUTFD;OOO

ERROR;OOO

PINIT;OOO

SLlN;OOO

SIGNAL I/O DESCRIPTION

STROBE;OOO 0 - STROBE

SIGNAL

READY;OOO

0 + DATA BIT 0

0 + DATA BIT 1

0 + DATA BIT 2

0 + DATA BIT 3

0 + DATA BIT 4

0 + DATA BIT 5

0 + DATA BIT 6

0 + DATA BIT 7

I - ACKNOWLEDGE

I + BUSY

I + PAPER END

I + SELECT

0 -AUTO FEED

I - ERROR (FAULT)

INDEX;OOO

TRACKO;OOO

WPROTC;OOO

RDDA;OOO

DSKCHG;OOO

-

-

-

SWFDP;100

SWMONB;OOO

WRDATA;100

EXFWE; 100

XRATEO;100

SIDE;100

0 - PRINTER INITIALIZE FDCDRC; 100

0 - SELECT INPUT STEP;100

1/0 DESCRIPTION

I

- EXTERNAL DRIVE

READY

I -INDEX

I - TRACK ZERO

I - WRITE PROTECTED

I - READ DATA

I - DISK CHANGE

(NOT USED)

(NOT USED)

(NOT USED)

0 + DRIVE SELECT

0 + MOTOR ON

0 + WRITE DATA

0 + WRITE ENABLE

0 + LOW DENSITY

0 + SIDE SELECT

0 + DIRECTION

0 + STEP

GND

(FOR PRT)

GROUND (0 V) GND

(FOR EXT FDD)

GROUND (0 V)

5-7

5.2.2 RGB connector

5 o o

0 0 0 0

9 6

FIGURE 5-5 RGB Connector

TABLE 5-2 RGB Connector Signal Names

PIN 1/0 SIGNAL MONOCHROME STANDARD RGB ENHANCED RGB

1 GND

2 0 PESR; 100

3 0 PERE; 100

4 0 PEGR; 100

5 0 PEBL;100

6 0 PESG;100

7 0 PESB; 100

8 0 PEHS; 100

9 0 PEVS'100

Ground

Ground

Not connected

Video

H.Sync

V.Svnc

Ground

Ground

Red

Not connected Green

Not connected Blue

Intensity Intensity

Ground

S.Red

Red

Green

Blue

Intensity/ S.Green

Not connected S.Blue

H.Sync H.Sync

V.Svnc V.Svnc

5.2.3 COMMS connector

5 o o

0 0 0 0

6 9

FIGURE 5-6 COMMS Connector

TABLE 5-3 COMMS Connector Signal Names

PIN

1

2

3

4

5

6

7

8

9

SIGNAL

MDCD; 100

MDRD; 100

MDTD; 100

MDDTR; 100

GND

MDDSR;100

MDRTS;100

MDCTS; 100

MDRI'100

1/0

0

0

I

I

I

0

I

I

DESCRIPTION

+ DATA CARRIER DETECT

+ RECEIVE DATA

+ SEND DATA

+ DATA TERMINAL READY

GROUND (OV)

+ DATA SET READY

+ REQUEST TO SEND

+ CLEAR TO SEND

+ RING INDICATOR

5-8

5.2.4 Expansion bus connector (in the system unit)

There are two typs of expansion bus connectors: one is 8-bit bus type, and the other is l6-bi t bus type. 8 bi t bus-type has signal names only at A side and B side.

TABLE 5-4 Expansion Bus Connector (A side/B side)

Signal Names

PIN

An

A14

A15

A16

A17

A18

A19

A20

Al

A2

A3

A4

AS

A6

A7

A8

A9

Ala

All

A12

A21

A22

A23

A24

A25

A26

A27

A28

A29

A30

A31

SIGNAL

10CHCK; 000

507; 1 00

506; 100

505; 100

5D4; 100

503;100

,SD2; 100

501;100

500; 1 00

10RDY; 100

AEN;100

5A19;100

SA 18; 100

SA17; 100

SA 16; 100

SA 15; 1 00

SA 14; 100

SA 13; 100

SA12;100

SA 11; 1 00

SA10;100

SA9; 100

SA8; 100

SA7; 100

SA6; 100

5A5; 100

SA4; 100

5A3; 100

SA2; 1 00

SA 1; 100

SAO; 100

PIN

B20

B21

B22

B23

B24

B25

B26

B27

B28

B29

B30

B31

Bl

B2

B3

B4

85

B6

B7

B8

B9

Bl0

B 11

B12

B13

B14

B15

B16

B17

B18

B19

I/O

/0

/0

/0

/0

/0

/0

/0

/0

/0

/0

/0

/0

/0

/0

/0

/0

/0

I

I/O

I/O

I/O

I/O

I/O

I/O

I/O

I/O

I

0

/0

/0

/0

SIGNAL

GNO

RE5ET;100 vee

IRQ9; 100

M5V

OREQ2;100

M12V

OWAIT;OOO

P12V

GND

SMEMW;OOO

5MEMR;000

10W;000

10R;000

DACK3; 000

OREQ3; 100

OACK1;000

OREQ1;100

REFR5H;000

CLK;100

IRQ7;100

IRQ6; 100

IRQ5;100

IRQ4; 100

IRQ3;100

OACK2;000

TC; 100

ALE;100 vce

CLKCRT; 100

GND

I/O

0

I

I

I

I

0

0

0

I/O

0

I

I

I

I

0

I

0

I

0

0

I/O

I/O

0

5-9

TABLE 5-5 Expansion Bus Connector (C side/D side)

Signal Names

PIN

Cl

C2

(3

C4

(5

(6

C7

(8

(9

(10

Cll

(12

(13

(14

C1S

(16

C17

(18

SIGNAL

5BHE;000

A23; 100

A22; 100

A21;100

A20; 100

A19;100

A 18; 100

A 17; 100

MEMR;OOO

MEMW;OOO

5D8; 100

509; 100

5Dl0;100

5Dl1;100

5D12; 100

5D13;100

5D14;100

5Dls'100

I/O

I/O

I/O

I/O

I/O

I/O

I/O

I/O

I/O

I/O

I/O

I/O

I/O

I/O

I/O

I/O

I/O

I/O

I/O

5.2.5 External keyboard connector

PIN

Dl

D2

D3

D4

Ds

D6

D7

D8

D9

Dl0

Dl1

012

013

D14

Dls

D16

D17

D18

SIGNAL

MEM16;000

1016;000

IRQ10;100

IRQll;100

IRQ12; 100

IRQls;100

IRQ14;100

DA(KO;OOO

DREQO; 100

DA(KS;OOO

DREQS; 100

OA(K6;OOO

DREQ6; 100

DACK7;000

DREQ7; 100

V((

MA5TER;000

GND

I/O

I

I

I

I

I

0

I

I

I

0

I

0

I

0

I

I

3

2

FIGURE 5-7 External Keyboard Connector

TABLE 5-6 External Keyboard Connector Signal Names

Pin

1

2

3

4

5

1/0

1/0

I/O

5-10

Signal Name

KBCLK (clock)

KBDAT (data)

N.C.

Vee

GND

5.3 KEYBOARD LAYOUT

5.3.1 USA version

FIGURE 5-8 USA Version

5-11

5.3.2 England version

FIGURE 5-9 England Version

5-12

5.3.3 German version

FIGURE 5-10 German Version

5-13

5.3.4 France version

FIGURE 5-11 France Version

5-14

5.3.5 Spain version

FIGURE 5-12 Spain Version

5-15

5.3.6 Italy version

FIGURE 5-13 Italy Version

5-16

5.3.7 Scandinavia version

FIGURE 5-14 Scandinavia Version

5-17

5.3.8 Switzerland version

FIGURE 5-15 Switzerland Version

5-18

5.3.9 Keycap number

FIGURE 5-16 Keycap Number

5-19

5.4 DISPLAY CODE

TABLE 5-7 Display Code

~

0

I(~

I

2

3

4

5

6

7

!

+--

--. -

-

•

I

~

2 3 4 5 6 7 8 9 A

, 0 @ p

,

P y

,

E

, a

~

~ rr

4§

+

•

•

•

Ell

9

A

B

C

0

E

F

0

[+] c3

•

-

rr

--+

9 L

}

J.)

~

-

..

!

.. f r

"

#

$

0/0

&

(

•

,

)

*

1

2

3

4

5

6

7

8

9 a

Q i.i

00

, b r e IE

0 x e y

(,

1=

6

' 0

U

£

¥

'" r

-,

.

> N /\ n ~, A Pf

«

/ ?

•

A Q

B

C

0

E

R

S

T

U

H X

I

K

< L

M

0 -

'"

Y

]

C 5 d e

F V f h i

J Z j

[ k

I m

0 t u v

Y z

I

I

{

6-

}

A

a

a

.. e

, e

A

..

"

..

,

,

,

A

A f

0 f

,

0

, a

0 u

0

, , a

G W g w C(

A

0

0

A u

, u o.

--

N

-

0

B C 0 E F

...

ex --

n t-r--a

¢ 1/2

»

,

H

Jt~

F= t=TI

WI

III

Dl

~

~

II

1=

1 l l - I -

1=

II

"I

I lL b

F r-

~

~ ~

/3 r

11 -

-

+

>

<

L

(1

).J

T

2 a n

co

cf>

E n

I) r

.

,.....,..

~

0

2

•

•

() -./ n

•

I~I

5-20

APPENDIX A

BUS DRIVER GA (Gate Array)

A.l GENERAL

The Bus Driver Gate Array is a flat package typed chip with

100 lead pins, and i t controls the busses between the CPU and Memory, or the CPU and I/O devices.

The Bus Driver Gate Array has the following functions.

Input/ Output control of the 16-bit data bus

- Generation of the system address

- Generation of the Memory refresh address

80 51

50

100

1 30

31

A-l

A. 2 BLOCK DIAGRTAM

< n1" nil

DIRC

DBHEN

XCVR

<-r)7-nn

CNVAO

LATDEN

LCH

DIRC

-:>

XVCR K

DBlEN

BCHGD~ I

BCHGE~I

V

XCVR

(

I

<;D1S-C;DR

SDl-SDD ;> r

A16-A9

SEL ~16.:-:~'> ALE

CPHLDA

LCH

I xn7-XD

-:>

ADSTB?,

AEN2 ~

LCH r - -

>

r-->

-

AENl

SEL r-f - -

ADSTBl

..

AENl

..

PGA16

LCH

REFADO

..

CTR

AENl +AEN2 t

SADREN

REFQ1..,

DRVR

XA8

C;A8-SAO

>

I Alq-A 1

I

ALE

~

CPHlD~

LCH

>

='.J REFAD~

SEL

CPHlDA

+DMACK

SA19· ·SAiL />

XCVR: Transceiver

DRVR: Driver

SEL: Selector

LCH; Latch

CTR : Counter

FIGURE A-I Bus Driver GA Block Diagram

A-2

A.3 SIGNAL DESCRIPTION AND PIN ASSIGNMENT

TABLE A-I Pin Description

8

9

10

11

12

13

14

15

16

2

3

4

Pin liD Signal Name

1

5

6

7

17

18

19

20

21

I

I

I

I

I

I

I

I

I

I

I

I

I

I

I

I

I

I

I

Description

CPU hold acknowledge signal.

CPHLDA When this signal is high, the system bus is used by anyother controller than the CPU.

ALE

Vcc

CPU address latch signal.

This signal is active high.

+ 5V

This signal is a part of DMA address from the

PGA16

DIRC page register of the Memory Mapper GA.

Data transfer direction signal in the CPU access mode. When this signal is low, the data goes to the CPU (read cycle), and when it is high, the data comes from the CPU (write cycle).

Data bus enable signal.

BUSEN

This signal controls data enable timing during the CPU readl write operation.


XD7-XDO are data bus from the liD controllers.

The DMAC outputs DMA address on the data bus

XDO during the DMA operation.

Data bus bit o.

Data bus bit 1.

Data bus bit 2.

XD1

XD2

XD3

XD4

XD5

XD6

XD7

GND

AEN1

Data bus bit 3.

Data bus bit 4.

Data bus bit 5.

Data bus bit 6.

Data bus bit 7.

Ground

Address enable signal for the slave DMA.

This signal is active low.

Address enable signal for the master DMA.

AEN2

A9

A10

A 11

A15


A 19-A9 are the CPU address lines. These lines also come from the Memory Mapper GA for the

DMA address transfer.

CPU address line bit 9.




A-3

33 I/O

34 I/O

35 I/O

36 I/O

37 I/O

38 I/O

39 I/O

40

41 I/O

42 I/O

43 I/O

44 I/O

45 I/O

46 I/O

47 I/O

48 I/O

Pin I/O Signal Name

26

27

28

29

22

23

24

25

30

31

I

I

I

I

I

I

I

I

0

32 I/O

49

50

I

I

A12

A13

A17

Descri ption

A19

A14

A16

Vcc

A18



+5V


This signal is generated by CPHLDA signal.

DMACK When this signal is low, CPU mode is activated,

XA8

SD15

SD14

SD13

SD12

SD11

SD10

SD9

SD8

GND

SD7

SD6

SD5

SD4

SD3

SD2

SD1

SDO




CPU address line bit 19. and when it is high, DMA mode is activated.

DMA address

Each of SD15-SDO is the system data bus.

The lines SD15-SD8 are in the high bank, while

SD7-SDO are in the low bank.

System data bus bit 15.








Ground








System data bus bit o.

This is an enable signal to transfer the 2nd byte

BCHGEN during 16/8 bit conversion.

It is also enabled while DMA byte is transferred.


This signal controls the direction of the 2nd byte

BCHGDR transfer during 16/8 bit conversion or DMA byte transfer.

A-4

52

53

54

67

68

69

70

63

64

65

66

59

60

61

62

55

56

57

58

71

72

73

74

Pin 1/0 Signal Name

51

75

76

77

78

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

I

I

I

I

SA6

Vcc

SA9

SA7

SA8

SA10

SAB

SA 11

SA 12

SA5

SA3

SA4

SA2

GND

SA1

SA14

SA15

SA16

SA17

SA18

SAO

SA19

DBHEN

DBLEN

LATDEN

CNVAO

Vcc

Description

System address lines.

SA8-SAO are used during the memory refresh cycle, and SA 15-SA9 are used during the

CPU/DMA mode as a part of the system address.

System address line bit 6.

Not used

+ 5V












Ground




System address ne bit 16.

System address nebit17.

System address ne bit 18.

System address ne bit o.

System address I ne bit 19.

High bank data bus (SD15-SD8) enable signal.

This is active high.

Low bank data bus (SD7-SDO) enable signal.


This signal is to read the 1st byte stored in the internal buffer during 16/8 bit conversion.

The 1st byte is read out when starting the 2nd byte reading if this signal is active.

This signal is dummy address for the 2nd byte during 16/8 bit conversion.

This signal stores the 1st byte in the internal buffrer while read operation is being executed.

+ 5V

A-5

Pin I/O Signal Name

79

80

81

I

I

I

82 I/O

83 I/O

84 I/O

85 I/O

86 I/O

87 I/O

88 I/O

89 I/O

90

91 I

92 I/O

93 I/O

94 I/O

95 I/O

96 I/O

97 I/O

98 I/O

99 I/O

100

REFADO

REFQ1

ADSTB1

D15

D14

D13

D12

D11

D10

D9

D8

GND

ADSTB2

D7

D6

D5

D4

D3

D2

D1

DO

Description

This signal is a refresh address (the lowest bit).

It is output as SAO.

This signal is also used as a clock signal for the internal refresh address counter.

This signal is to output the refresh address to the system bus.

This signal outputs the content of the refresh address counter, when it is low.

Slave DMAC address strobe signal.

This signal is used to latch the DMA address which has been output on the data bus,.

CPU data bus from Ito the CPU.

(D15-D8 are in the high bank, and D7-DO are in the low bank)

CPU data bus bit 15.






CPU data bus bit 9.

CPU data bus bit 8.

Ground

Master DMAC address strobe signal.

This signal generates DMA address.

It is active high.

CPU data bus bit 7.

CPU data bus bit 6.

CPU data bus bit 5.

CPU data bus bit 4.

CPU data bus bit 3.

CPU data bus bit 2.

CPU data bus bit 1.

CPU data bus bit o.

Not used.

A-6

A.4 DATA BUS CONTROL

This circuit controls the data bus between the CPU and I/O port or the CPU and Memory. 8/16 bit conversion is performed by this circuit.

<;[) 1 S-SDR

D

B

<

[)lS -08

A

<

[)7-00

2

DIRC

DBHEN

> XCVR

CNVAO lATDEN..

LCH r<

3

BCHGO~'I

BCHGEN .. lJ

XCVR r

J

4

DIRC

>

XVCR r<

1

DBlEN

<;[)7.<:.nn

C

FIGURE A-2 Data Flow among the CPU, I/O Port, and Memory

A.4.1 Word access

When the I/O port connected to the data bus is word oriented, no data conversion is performed.

Low bank

High bank

B l1li(

(refer to Figure A-2)

In this case, read/ write cycle is completed in three CPU cycles. (No wait cycle request is included.)

A-7

A.4.2 Byte access

Following are the cases of byte access.

The I/O port is connected to the low bank of the data bus.

- Word Read Operation

The 1st data byte (even address data) transferred from C is latched in the buffer 3 temporarily.

The following second byte data (odd address data) is transferred to the DIS-D8 ( B ) through the trsansceiver 4.

At this time, the 1st data byte in the buffer 3 is enabled to be output to the data bus D7-DO ( is transferred to the

A ), thus, l6-bit data cpu.

The transceiver 1 is disabled while the 2nd data byte is being transferred.

1st data byte

C--~-'~3 -.A

2nd data byte

C - 4

.. B


- Word Write Operation l6-bit write data from the the data bus DIS-DO. cpu is output to

The low bank data D8-DO is transferred to transceiver 1 as the 1st data byte.

C

The high bank data DlS-19 is transferred to

A and B through through the

C through the transceiver 2 and trnasceiver 4 as the 2nd byte.

1st data byte

A--~-~1 "C

2nd data byte

B -'2 -'4

-.C


The transceiver 1 is disabled during the 2nd byte transfer.

The buffer 3 is disabled while write operation is being executed.

This word/ byte conversion occupies 12 system clock cycle time.

A-8

A.4.3 DMA operation

Byte DMA operation

DMA data transfer between I/O port connected to the low bank data bus and memory location of odd address is as follows.

Case of I/O to Memory

Case of Memory to I/O

"D

.. c


- Word DMA operation

The GA is not concerned with the word DMA operation.

~.5 Address Generation

System address busses SA19-SAO are generated in this GA, and each of these lines are used for the following purposes.

- CPU address output SA19 SA9

- DMA address output SA19 SA9, XA8

- Refresh address output : SA8 - SAO

To generate the system address, following three functional blocks are applied.

A.5.1 SA19 -SA17

SA19 - 17 come from the CPU and from the Memory Mapper GA.

They are wired ORed.

I Alq-A17 r

;:; L.CH

>

\=:J

>

REFADO

SEL

ALE .-

CPHLD~

CPHLDA

+DMACK

<:lI.1Q"':'<;A17

">

FIGURE A-3 System Address Bus 19 - 17

A-9

A.S.2 SA16 - SA9, XA8

These lines are used to output the CPU address A16-A9 to

SA16 - SA9 or output the DMA address PGA16, XD7 - XDO to

SA16 - SA9, XA8.

LA 16 A9

ALE

(PHLDA

LCH

I XD7-XDI

>

ADSTB?.

AEN2 •

LCH

ADSTBl

•

AENl •

PGA16

LCH

----

>

- > -

AEN1

SEL r--f - - -

AEN1 +AEN2 t

SADREN

SEL

XA8

SAlfi-SAQ

>

FIGURE A-4 System Address Bus SA16 9, XA8

A.S.3 SA8 - SAO

These address lines are used to output memory refresh address. The address is generated by refresh address counter and it is output at every 15 micro seconds.

CTR

REFQ1,..

DRVR S~B s~o

>

FIGURE A-5 System Address Bus SA8 0

A-IO

APPENDIX B

MEMORY MAPPER GA (Gate Array)

B.l GENERAL

The Memory Mapper Gate Array is a flat package typed chip with 100 lead pins, and i t contains the following functions.

- Generation of the DMA memory address.

I/O address decoding.

- Other various functions such as;

*

ROM control signal

*

Timer clock

*

Parity error detection control

*

NMI (Non Maskable Interrupt) signal

80

51

..w. _ _ _ _ 50

100

1

30

31

B-1

B • 2 BLOCK DIAGRAM

Xn7-Xnn

CPU commands

CPU

Interface

Latch

<---

(SA9)

I

XA8 XAO

I

DACK7-DACKO

>

Address

>

Select

I - - -

I - - -

>

8bitx 16

Register

>

A23-A16 >

10CONT

10CS

1/0

Command

Decoder

1/0 control Lines /

FIGURE B-1 Memory Mapper GA Block Diagram

B-2

B.3 SIGNAL DESCRIPTION AND PIN ASSIGNMENT

TABLE B-1 Pin Description

Pin

1

2

3

4

S

6

7

8

9

10

11

1/0

I

I

0

0

0

0

0

I

I

I

12 0

Signal Name Description

CPHLDA

MIO

VCC

SPK

KBCCS


When this signal is high, the system bus is used by any other controller than the CPU.

If this signal is low, the system bus is used by the

CPU.

Memory I/O select signal.

When this signal is high, memory cycle is being executed, and when low, I/O cycle.

+SV

Buzzer signal from the external circuit.

Keyboard controller select signal.

This signal becomes low when the I/O port address is 062H/ 068H and also KBSEL = 0, or when the address is 8062"H/ 8068H.

Chip select signal to the BIOS ROM.


LROMCS The address ranges are:

OEOOOOH-OFFFFFH

ROMOE

FEOOOOH-FFFFFFH

Output enable signal to the BIOS ROM.

This signal is generated by the ROM chip select signal and memory read command.


System bus high enable signal.

SBHE

MEMR

LATAO

CNVALE

PGA16

This signal generates the data bus high enable signal. This signal is active low.

Memory read command.

This signal comes from the DMA controller GA and it is generated by SAO.

When this signal is high, the low bank of the data bus is selected.

Dummy address latch enable signal for the 2nd byte transfer in 16/8 bit conversion.

This signal also generates output enable signal of the 1st byte which has been latched.

Address line from the Memory Mapper register during the DMA cycle or memory refresh cycle.

This signal is used as the system address SA 16 durinQ the slave DMA oQeration.

B-3

Pin I/O Signal Name

13

14

15

16

17

18

19

20

21

22

23

24

25

0

I

I

0

0

0

0

0

0

0

I

0

NDPCS

DIRC

GND

HCS1

DBlEN

DBHEN lATDEN

NMI

BSYCPU

10RDY

ROMCS

RAM16

PPICS

Description

This signal defines that the NDP (80287) has been selected. If this signal is low, the system data bus is disabled. When OF8H*SMI0*INTA 1 is made, this signal is activated.

Direction signal for CPU data transfer.

When this signal is low, read data is on the data bus, and when it is high, write data is on the data bus.

Ground

HDD address decode signal 1 (not used).

Data (low bank) enable signal.

This signal is generated from lATAO signal. This signal is active high.

Data bus (high bank) enable signal.

This signal is generated from SHBE signal.

This signal is active high. each data bus is controlled inside the GA.

This signal is read enable signal for the 1st byte transfer in 16/8 bit conversion.

The 1st byte has been stored in a buffer of the

Bus Controller GA during the 1st read cycle.

NMI interrupt signal. It is active high.

This signal is output when memory parity error or any error from the expansion unit occurs.

CPU busy signal to NDP.


I/O channel ready signal:

This signal is used to expand the NDP reset signal in order to meet the timing specification of the

NDP.

ROM chip select signal. This signal is active low.

The address ranges are:

OFOOOOH-OFFFFFH

FEOOOOH-FFFFFFH

This signal becomes low when the system memory (0-640 Kbytes) is accessed. This signal enables internal parity error detection flag.

PeripheralI/O select signal.

This signal becomes active when the I/O port address is 06*H-07*H.


B-4

Pin 1/0 Signal Name

26

27

28

29

30

31

32

33

34

35

36

37

38

39

40

I

0

0

0

0

I

I

I

I

I

I

I

I

Description

PUCLR

10CHK

Vcc

Power on reset signal. This signal is active low.

This signal inhibits real timer write command during the reset period.

Error signal from an external expansion unit. If this signal is low, the NMI flag becomes effective.

+5V

INTA

REFRSH

TM20UT

RESET lOR lOW

ALE

This signal is to read the interrupt vector address.

This signal comes from the interrupt controller

(U8259A).

DMA refresh enable signal. This signal is active high. The Memory Mapper address A23-A 17 and PGA 16 are output during the memory refresh operation.

Buzzer sound signal used in the system.

This signal comes from the timer (U8254).

System reset signal.


1/0 read command. This signal is active low.

It is used to write memory address register in the

GA, system status, and also to generate command.

1/0 write command. This signal is active low.

It is used to write memory address sregister in the

GA, or to generate various commands.

Address latch enable signal from the cpu.


TMCLK Clock signal (1.19 MHz) to the timer (U8254).

Count control signal to the timer.

TMGATE When this signal is low, it disables from counting, and when it is high, counting is enabled.

PITCS

PIC1CS

GND

Timer (U8254) chip select signal.

This signal is active low, and becomes active when the 1/0 port address is 04*H-05*H.

Chip select signal to the master interrupt controller (U8259A). This signal is active low, and becomes active when 1/0 port address is

02*H-03*H.

Ground

B-5

42

43

44

45

46

47

48

49

50

52

53

54

55

Pin

41

51

56

57

58

59

60

61

62

63

I

I

I

I

I

I

I

I

0

110

0

I

I

I

0

I

0

0

0

0

0

I


DSTRB

Data read strobe signal to the real timer.

This signal becomes active when read operation to the 1/0 port address 071 H is executed.


SA14

SA15

DACK6

DACK2

DACK4

DACKO

DACK7

Address line bit 14.


DMA acknowledge signal from channel 6.

DMA acknowledge signal from channel 2.

DMA acknowledge signal from channel4.

DMA acknowledge signal from channel O.

DMA acknowledge signal from channel7.

DMA acknowledge signal from channel 3. DACK3

IRQ13

KBCCS2

Interrup_t request signal when NDP error occurs.

System occupation request signal from the

MASTER external processor.


Chip select signal forthe external 101 keyboard controller.

Vcc

NDPER

NDPBS

KBSEL2

SA9

+5V

NDP error signal.

NDP busy signal.

This signal indicates which of the two keyboard controllers (the internal one or excternal one) is selected.

When this signal is "1"

I it shows that the external controller is selected.

Address line bit 9.

This signal is ORed signal of CPHLDA and

DMACK

NDPRST

MASTER signals. This signal is low except in the

DMA mode.

Reset command to the NDP.


Chip select signal to the slave interrupt controller

(U8259A). This signal is active when the 1/0 port

PIC2CS address is OA*H-OB*H.

This is active low.

Chip select signal to the master DMAC (U8237).

DMA2CS This signal is active when the 1/0 port address is

HCS0

MDSPK

OC*H-OD*H. This is active low.

HDD address decode signal 0 (not used).

Buzzer sound siqnal from the MODEM card.

B-6

Pin I/O Signal Name

64

65

66

67

68

69

70

71

72

73

74

75

76

77

78

79

80

81

I

I

0

0

I

I

0

0

0

0

0

0

0

0

0

I

I

Description

PDINL

GND

PDINH

RETIMW

Parity error signal from the system memory (low bank).

Ground

Parity error signal from the system memory (high bank). This signal is active low.

It makes an NMI interrupt signal at the rising edge of the memory read if an error occurs.

Data write command to the real timer.

This signal becomes active when write operation to the 1/0 port address 071 H is executed. This signal is active low.

STEP

RWSEK

FDSTEP

Step signal to the FDD.


Seek enable signal to the FDD.

When this signal is low, FD seek operation is enabled, and when it is high, FDD read orwrite operation is enabled.

Step signal from the FDC.


Chip select signal to the DMAC (U8237A).

DMA1CS This signal becomes active when the 1/0 port address is OO*H. This signal is active low.

A23--A 17 are used as page address during the

DMA operation. The page address from the

A23 internal register is output when the DMA acknowledge signal is low.

A22

A21

A20

A19

A18







Vcc

A17

+5V


$14MHZ Clock signal (14.31818 MHz) to the timer (U8254).

Each of XA9--XAO is X address which is same as

XAO the system address. They are used to decode the

1/0 port address or to specify the DMA page register for readl write operation to the page address reqister

B-7

Pin I/O Signal Name

82

83

84

85

86

87

88

89

90

91

92

93

94

95

I/O

I/O

I/O

96 I/O

97 I/O

98 I/O

99 I/O

100

I

I

I

I

I

I

I

I

0

I/O

I

XA7

XA6

XA5

XA4

XA3

XA2

XA1

XA8

GND

Description

XDREAD connected to the X data bus.


Each of XD7 - XDO is X data bus. Read or write operation to the DMA page register and read

XDO

XD1

XD2

XD3

XD4

XD5

XD6

XD7

PDPEN

X address line bit 7.








Ground

Read enable signal to the peripheralI/O which is operation to the system status are performed through this bus.

X data bus bit O.

X data bus bit 1.

X data bus bit 2.

X data bus bit 3.

X data bus bit 4.

X data bus bit 5.

X data bus bit 6.

X data bus bit 7.

This signal indicates whether the plasma display panel is open or closed.

When this signal is" 1", it means that the panel is open, and therefore the plasma display can be used.

B-8

B • 4 DNA MEMORY ADDRESS

DMA page address is stored in the DMA page address register in the Memory Mapper GA before it is used in the DMA cycle.

The DMA page address register has 8 bit length and it is output to the address lines A23 - Al7 and PGAl6 during the

DMA cycle.

Each DMA channel has a DMA page address register and address is assigned as follows.

TABLE B-2 Address Assignment of DMA Address Register

Adress

081H

082H

087H

089H

08AH

08FH

Channel

Channel 2

Channel 3

Channel 0

Channel 6

Channel7

* Refresh

DMA

Slave DMA

II

II

Master DMA

II

II

To store the DMA page address, the address lines XA are decoded and the data on the XD lines are stored in the selected register.

< XD7 .l(nn

CPu commands

CPU

Interface

Latch

I<=-

>

8bit x 16

Register

A23 A16

>

(SA9)

I XA8 XAO

I DACK7 DACKO

>

Address

>

Select

I - - f - -

>

FIGURE B-2 DMA Page Address Register

B-9

B.5 I/O Decode Control

Address lines SA9 and SA8-SAS are used to generate the I/O port select signal.

Address on the XA lines are decoded for I/O port chip select if it is not in the DMA cycle.

The following table shows the address assignment to each I/O port chip.

TABLE B-3 Address Assignment to the I/O Port

Address Signal Name

OO*H-01*H DMA1CS

02*H-03*H PIC1CS

04*H-05*H PITCS

06*H-07*H PPICS

08*H-09*H PREGCS

OA*H-OB*H PIC2CS

OC*H-OD*H DMA2CS

OE*H-OF*H C287

Descri ption

Slave DMAC select

Master Interrupt Controller Select

Timer Chip Select

Peripheral 1/0 Select

Reqister Select within the GA

Slave Interrupt Controller Select

Master DMAC Select

NDP reset

B-10

APPENDIX C

OMA GA (Gate Array)

C.l GENERAL

The DMA Gate Array is a flat package typed chip with 100 lead pins.

The DMA Controller Gate Array has the following functions.

- Clock generator

CPU clock

DMA clock

- Keyboard clock

- System timing control

- Memory control (ROM, RAM)

- DMA control

- Memory refresh control

- DMA ready control

- Command generation

80 51

~--------~~-50

100

~m________

1 30

C-l

C. 2 BLOCK DIAGRAM

Command

16MHz

DMAMRD

51,50

R5T CMD

MIO

DMHRQ

FREQ2

CPHLDA

~,3-AlZ

>

Counter

&

Latch

Ready

.. Gen.

I

..

..

Shutdown

•

Gen .

~

I BUS

Control

..

..

DMAI

Refresh •

&

Latch

>

Memory

Decoder

&

Latch

FIGURE C-I DMA GA Block Diagram

CPUCLK

SYSCLK

DMACLCK

CPRDY

Commands

(MEMRIW, IORIW, etc.)

DMARDY

•

SHUTDOWN

BCHGEN

BCHGDR :

BCHFEN

BCHGDR

DMAACK

REFQ1 REFAQO

RASH, L

CASO, 1,2

VRAMCS

ROM~~

..

•

•

•

C-2

C.3 SIGNAL DESCRIPTION AND PIN ASSIGNMENT

TABLE C-l Pin Description

Pin 1/0 Signal Name Descri ption

1

2

3

4

S

I

0

I

1/0

6 1/0

CPHLDA

ALE

VCC

AEN1 lOR lOW


When this signal is high, the system bus is used by any other controller than the CPU.

If this signal is low, the system is used by the CPU.

CPU address latch signal.

The address data is latched at falling edge of this signal.

+5V

Address enable signal during the slave DMA operation. The DMA address is enabled when this signal is low.

1/0 read command.

1/0 read operation is executed when this signal is low. In the master mode, this becomes an input signal.

1/0 write command.

1/0 write operation is executed when this signal is low. This signal is output from the DMAC

(U8237) during the DMA operation. In the master mode, this becomes an input signal.

Memory I/O select signal.

When this Signal is high, memory cycle is being

7

8

11

I

0

I

MIO

CLK4

SEL4M executed, and when this signal is low, it is 1/0 cycle.

12MHz clock (not used).

Memory read command. This signal is also

9 1/0 output during the memory refresh operation.

MEMR* Memory read operation is done when this signal is low. In the master mode, this becomes an input signal.

Memory write command. The write operation is

10 I/O MEMW* done when this signal is low. In the master mode, this becomes an input signal.

Clock rate select sig nal.

This signal is generated by the keyboard controller to select CPU clock rate.

When this signal is low, the CPU clock rate is 12

MHz, and when it is high, the CPU clock rate is 6

MHz.

C-3

17

18

19

14

15

16

Pin I/O Signal Name

12

13

20

21

22

23

25

26

27

28

29

0

0

0

0

I

I

I

I

I

I

I

I

I

I

I

I

24 liD

Description

Output address line from the CPU.

CPUA20

This signal is controlled inside the GA, depending on the CPU mode {Reali Protect}.

In the real mode, A20 is fixed to low, and in the

BALE protect mode, CPUA2 is output to A20.

CPU reset command.

RSTCMD This signal is effective when it is low, and it outputs the CPU reset signal.

CPU address line bit O.

AO

This signal generates SAO inside the GA.

GND Ground

This signal shows the direction of data transfer.

DIR

FREQ

When reading, this becomes low.

Refresh timing signal {not used}.

In the CPU mode, this signal functions exactly like

ALE. Apart from the CPU mode, it is always high.

NPCK

A01

A17

A18

A19

A20

A21

A22

A23

Vcc

PAKI

Clock signal8MHz forthe NDP {80287}.

CPU address line bit 1 :

This signal is used to generate the "shut down" signal.

CPUI Memory mapper address.

Memory Mapper address is input during the

DMA operation. This signal is used to decode each memory size.

CPUI Memory Mapper Address line bit 17.




This signal is output during the CPU operation, and when used in the real mode, it is fixed to low, while in the protect mode, CPUA2 signal is output. When the CPU is inactivated, this becomes an input signal.




+ 5V

Input PEACK siqnal from the CPU.

C-4

Pin I/O Signal Name

30

31

32

33

34

35

36

37

38

39

40

41

42

43

44

45

46

47

48

49

50

0

0

I

I

0

I

I

I

I

0

0

I

I

I

I

I

0

0

I

I

Description

RealI Protect mode select signal.

When this signal is low, the CPU is in the real

REAL mode, and when it is high, the CPU is in the protect mode.

Keyboard controller clock signal (6MHz). CLK42

Address strobe signal to the real timer

AS18

(MC146818). This signal is active low.

$24MHz System clock signal (24 MHz)

CPRDY

CPUCLK

CPU ready signal.

This signal is active low, and is sampled by the

CPU at the leading edge of the Tc cycle.

CPU clock signal.

Either 24 MHz or 12 MHz is output by the clock selection control.

S1

SO

NDPCS

CPU bus status bit 1.

CPU bus status bit o.

NDP(80287) chip select signal.

TMIOUT Memory refresh request signal

GND

TEST

DMARDY

Ground

Test signal for the GA. This signal is active high.

Peripheral 1/0 select signal. This signal generates

PPICS real timer address strobe signal. When 1/0 address is 06*h/07*h, this signal becomes low.

PUCLR Power on reset signal. This signal is acitive low.

DMACLK DMA clock signal.(4MHz or 2MHz)

Ready signal to the DMAC One wait cycle is given in the DMA operation.

When this signal is low, it gives the wait cycle, and when it is high, DMA operation is is enabled.

Ack hold signal to the external DMAC

DMHLDA When this signal is high, it allows the DMA operation.

DMHRQ

CPU hold request signal from the external DMAC

This signal is acitve high.

Memory read command from the DMAC

DMAMRD

DACK4

XA4


Slave DMAC cycle signal. This signal is active low.

The master DMAC can not output addressl command signal while this signal is active.

Address sianal. CPUI DMA address bit 4.

C-5

Pin 1/0 Signal Name

51

52

53

54

55

56

57

58

59

60

61

62

63

64

65

1/0

0

0

I

66 0

67 I

I

0

0

I

0

I/O

I

I

0

XAO

BUSE N

Vcc

PAKO

SMEMR*

SMEMW *

10RDY

DMAAEN

SBHE

1016

MEM16

SYSCLK

DM1HLD

TEST2

GND

AMEMR

TEST1

Description

Address signal. This signal is from SAO.

It is input during the slave DMAC operation.

Data Enable Signal:

This signal is used to enable data bus.

+5V

PEAK output signal to the NDP:

The expanded PAKI (29 pins) signal with one more CPU clock in order to meet the timing specifications of the NDP.

Memory read command. This signal is output to the 8-bit expansion bus.

It is not output to any address of more than 1 M byte. This signal is active low.

Memory write command. The output condition of this signal is same as that of the SMEMR signal.

CPU ready control signal from outside the GA.

When this signal is low, a wait cycle can be qiven.

Address enable signal during the DMA operation. This signal is acive low.

System bus high enable signal.

This signal enables the high bank of the data when it is active. In the master mode, this signal becomes an input signal.

This signal defines that 16-bit type of I/O device is serviced in 110 command execution.

16-bit memory access signal.

This signal is to indicate that 16-bit type memory is accessed.

System clock.

One-third of the CPU clock frequency is output.

This signal is output when DMA request signal comes from the slave DMAC. When DACK4 is low, this signal becomes active (high).

The slave DMAC starts DMA operation by this.

GA test signal: This signal is active high.

Ground

Memory read signal to the T3200 system memory

(including expansion memory).

GA test sianal: This sianal is active low.

C-6

0

I

I

0

I

0

I

0

0

0

0

0

C-7

Pin I/O Signal Name Description

88

89

90

91

--

92

-- --.-------= ---- ---

93

94

95

96

97

98

0

0

CNVAO

BCHGDR

This signal is dummy address for 2nd byte transfer in 16/8 bit conversion.

The 1 st byte is latched at raising point of this signal while read operation is being executed.

This signal specifies the direction of the 2nd byte transfer in 16/8 bit conversion.

When this signal is low;

High bank ~

When this signal is high;

Low bank ~

GND Ground

This signal is an enable signal for the 2nd byte

O~ .... BC-HG-EN· ... tr.;:n~'fer- in·~1£/3 hih:-oniieG~oj')·.--·..... - -.--.-..~--.---

_0

0

0

0

0

0

0

C:PVHRO

CHK2

RAM16

CNVALE

LlMSL

ROMCS

LATAO


CPU hold request signal. This signal is generated

when the DfVIHRQ signai ishlcih. ~ - - - ~-

Internal monitor signal inside the GA.

System memory (0-640 Kbytes) access signal.

This signal is active low. It enables the parity error detection.

This signal is to latch the dummy address of the

2nd byte transfer in 16/8 bit conversion. This siqnal is active high.

Output signal from the EMS GA:

This signal indicates that the memory to be accessed is the system memory, and that neither

VRAM nor the memory connected to the extended bus is accessed.

BIOS ROM chip select signal. This signal is active low. The decode ranges of the address are:

OEOOOOH-OFFFFH

FEOOOOH-FFFFFH

System address inverted signal during the CPU cycle. When this signal is high (SAO is low), low data bus enable sianal is aenerated.

C-8

Pin I/O Signal Name

99

100

I

0

BHE

SMMW

Description

High data bus enable signal.

When this signal is low, high bank of the data bus is accessed.

Memory write signal supplied to the EGA GA:

This signal is active when write access to the memory space between 0-1 Megabyte is executed.

In the CPU mode, signals with the mark * are output, only when VRAM or the memory connected to the expanded bus is accessed.

C-9

C • 3 CLOCK GENERATOR

This circuitry is to generate the following cloks.

The original clock signal is a 24 MHz clock.

CPU Clock

System clock

DMA clock

Fast

24 MHz

8 MHz

4 MHz

Slow

12 MHz

4 MHz

2 MHz

Following are the timing chart of the clocks.

$24MHZ; 100

CPUCLK; 100

6 min.--.

SYSCLK; 100

13min.~

DMACLK; 100

16min.~ ~

FIGURE C-2 Clock Timing Chart

C-IO

C • 4 DNA CONTROL

CPU

"

/\

<:1\ l'

·<;AI

/\

>

ODD

~

Memory

EVEN

/I

\,

"

0

<:r1.l5. -

C; A P.

<;D7-SD

XD7-XDO lIE CPUHRQ

CPHLDA

DCHGEN t

DCHGDF

DMA

GA

DMHRO

DMHLDA

~

DMAC

XA7-XAO lIE

DRQX

DACKX

I/O

Port

~ t I t lOR lOW

FIGURE C-3 DMA Controller

This circuitry controls the DMA operation.

The DMA GA receives DMHRQ signal from the DMAC, then the GA responds to the CPU with CPUHRQ signal.

After receiving CPHLDA signal from the CPU, the GA responds to the DMAC with DMHLDA signal.

The DMAC starts DMA operation when i t receives the DMHLDA.

The DMAC prepares the DMA address on the system address bus and lOR/lOW signal to the DMA GA for the bus control. If the I/O port is byte oriented device, the bus controller GA is used for data bus switching (low bank to high bank or vice versa).

C-ll

APPENDIX 0

I/O CONTROLLER GA (Gate Array)

D.l GENERAL

The I/O Controller Gate Array is a flat package type chip with 100 lead pins.

This Gate Array has the following functions.

- FDD control

- Printer control

80 51

50

100

1 30

31

D-l

D.2 BLOCK DIAGGRAM

SD7-SDO r

SA1 SAO

I lOR lOW

;; CPU

~

Interface

~

.>

FDD

Command

Register

FDD Command >

FDD

>

Command

Register

PRT Inmm .. nn >

Printer

">

Bus

Driver

Pf)7_Pf)(l >

SA9-SAO

--,-~S:"';L~-'-'

1110

>

Decoder

--.!::

I

PreCompo

I

SIOCS

HDDCS

CRTCS

~D~RQ~F~D~(

_ _ _ _

~.~ID_el_a_Y

__

~----------------D-L-D-RQ--'-_~.~

$16MHz

.1

FOC

Clock

Switch

$HIFRQ

#CKFDC

:

FIGURE D-l I/O Controller GA Block Diagram

D-2

D.3 SIGNAL DESCRIPTION ADN PIN ASSIGNMENT

TABLE D-l Pin Description

Pin liD Signal Name

1 liD

10

11

12

13

14

15

16

17

18

19

20

21

2 liD

3

4 liD

5 liD

6 liD

7 liD

8 liD

9 liD

22

0

I

I

I

I

I

I

I

I

I

I

0

SDO

SA3

SA4

SAS

GND

SA6

SA7

SA8

SA9

SA1

PDSOO

SD1

Vcc

SD2

SD3

SD4

SD5

SD6

SD7

CRTCS

SA2

DRQ2

Description

Each of SD7-SDO is system data bus.

For printer control, this signal is used;

- to output printer data.

- to read pri nter status.

- to decode printer command.

For FDD control, it is used;

- to decode FDD control command.



+ 5v

System data bus bit 2





System data bus bit 7 liD port select signal to the color graphics controller. This signal is active (low) when the liD

~ort address is 3D*H. *=O-F

SA9-SAO is system address. They are used to decode the liD port addresses such as;

Printer/ FDDI Color Graphics port!

HDD port! RS232C





Ground






Write precompensation control.

This signal is fixed to low in this system.

DMA cycle request signal from the FDe.

This siqnal is active hiqh.

D-3

Pin

23

24

25

26

27

28

29

30

31

32

33

34

35

I/O

0

I

0

0

I

I

0

I

I

I

I

I


TC

This signal is a terminal count signal that indicates the end of the DMA data transfer.


It comes from the DMAC (U8237).

Terminal count signal to the FDC

FDAKTC This signal is active high. It is generated from the

TC signal.

FDACK

DRQFDC This signal generates DRQ2 to be sent to the

DMAC This signal is active high.

PDS01

Write precompensation ON/ OFF signal.

This signal is fixed to high in this system.

Vec

DMA acknowledge signal to the FDC


DMA cycle request signal from the FDC

IRQ6

+ 5V

Interrupt request signal which the FDC outputs at the end of command execution.

This signal is active high, and goes to the

DMACK

DACK2

EXTFDD

U8259A.

This signal inhibits output of the I/O port address during the DMA operation.

When this signal is low, decoding the address is enabled, and when high, it is disabled.

This is acknowledge signal to DRQ2 which is DMA data transfer request signal.


This signal is to switch the printer port connector to the external FDD.

When this signal is low, the connector is for the printer port, and when it is high, the connector is

$16MHZ

$19MHZ

$CKFDC for FDD port.

Basic clock to the FDC and VFO.

16 M Hz (cycle time is 62.5 ns.)

Basic clock to the FDC and VFO.

19.2 MHz (cycle time is 52.08 ns.)

FDC clock. Frequency of the clock depends on the data transfer rate.

250 kbps; 8 MHz, 16 MHz

300 kbps; 4.8 MHz, 19.2 MHz

500 kbps' 4 MHz 16 MHz

D-4

Pin 1/0 Signal Name

36

37

38

39

40

41

42

43

44

45

46

47

48

49

0

0

0

0

I

I

0

I

I

0

I

I

I

$HIFRQ

WINDOW

WCLK

FDCCS

GND lOR lOW

FDSRST

FDCWD

FDCINT

XF7RD

PS1

PSO

SYNC

Description

VFO clock. The clock frequency depends on the data transfer rate.

250 kbps; 8 MHz

300 kbps; 9.6 MHz

500 kbps; 8 MHz

Window signal generated from the internal circuit. This signal is active high.

FDD data write clock to the FDC

The cycle time of this signal is one-eighth of

CKFDC

Chip select signal to the FDC (U765).

This signal is active (low) when the 1/0 port address is 3F4HI 3F5H.

Ground

1/0 read command.


1/0 write command.


FDC reset command. This signal is active high, and is issued by the command to 3F2H (data is

D2).

Write data from the FDC


Interrupt signal from the FDC

This signal is active high, and generates IRQ6 signal.

This signal is to read the status of FDD disk change. This signal is active (low) when read address is 3F7H.

PS 1 and PSO are precompensation control signals.

These signals are output from the FDC

PSO PS1 Time

Low

Low

Low

High

No delay

225-250 nsdelayed

High Low 225-250 nsquickened

Precompensation control siqnal.

This signal is to control the VFO operation mode.

When this signal is low, it inhibits the read operation, and when it is high, the read operation isenabled.

D-5

Pin I/O Signal Name

50

51

52

53

54

55

56

57

58

59

60

61

62

63

I

0

0

0

0

0

0

0

I

I

0

I

I

Description

FDCWE

IRQEN

CCMICS

Data write enable signal to the FDD.


Printer interrupt enable signal.

This signal is active low. This signal is issued by the command to 372H.

RS232C (Primary) select signal.

This signal is active (low) when the I/O port address is 3F8H-3FFH.

Vcc +5V

FDD motor on signal to the 1st FDD.

SWMONA This signal is active high. ON/OFF is controlled by the command to 3F2H.

FDD motor on signal to the 2nd FDD.

SWMONB This signal is active high. ON/OFF is controlled by

INDRVB the command to 3F2H.

Internal FDD (2nd FD) select signal.

This siqnal is active hiqh.

SWFDA

Internal FDD (1st FDD) select signal.


This signal defines the FDD transfer rate.

XRATEO

SELECT

BUSY

CBDIR

STROBE

AUTFD


500 kbps-250 kbps


300 kbps

This signal is issued by the command to 3F7H.

Printer select command. This signal is active low.

It can be read from address 3F7H. This signal becomes write gate signal when it is in the external FFD mode.

Printer busy status. This signal is active high.

It can be read from the address 371 H.

This signal becomes motor ON/OFF signal when it is in the external FDD mode.

Read enable signal to the I/O peripheral which is connected to the external bus. This type of bus does not exist in this system.

Printer strobe signal. This signal is active high.

It can be read from address 371 H.

Printer auto-feed command. This signal becomes low density signal when it is in the external FDD mode.

D-6

Pin I/O Signal Name

64

65

66

67

68

69

70

71

72

73

74

75

76

I

0

I

I

I

I

I

0

0

0

0

0

Description

PDS10

FDD precompensation ON/OFF signal.

This signal is not used in this system.

Ground GND

RS232C (Secondary) select signal.

CCM2CS This signal is active (low) when the 1/0 port address is 2F7H-2FFH.

PE

Paper end status from the printer.

This signal is active high. It can be read from the address 371 H. This signal becomes write data signal when it is in the external FDD mode.

PINIT

SUN

ACK

Printer initial command. This signal is active high.

It can be read from address 372H. This signal becomes direction signal when It is in the external FDD mode.

Printer select command. This signal is active high. It can be read from address 372H.

This signal becomes step signal when it is in the external FDD mode.

Printer ACK status. This signal is active high.

It can be read from address 371 H.

Select signal is input when it is in the external

FDD mode,.

EROR

Printer error status. This signal is active high.

It can be read from the address 371 H. This signal becomes SIDE signal when it is in the external

FDD mode.

EXFDWE Write gate signal in the external FDD mode.

System FDD (2nd FDD) select signal.

SWFDB

This signal is active high ..

Read control signal to the VFO.

DTAREA When this signal is low, read operation is disabled, and when high, it is enabled.

This signal is to change the value of resistance in the VFO circuit when the data transfer rate is 300

EN96M kbps.


WN

Window signal from the VFO.

This sianal is active hiah.

D-7

Pin I/O Signal Name

77

78

79

80

81

0

0

0

0

82 I/O

83 I/O

84 I/O

85 I/O

86 I/O

87 I/O

88 I/O

89 I/O

90

91

92

0

0

MINI

Vcc

WRDATA

HDDCS

PRTDIR

PD7

PD6

PDS

PD4

PD3

PD2

PD1

PDO

GND

SLCTIN

AUTFD

Description

This signal defines the formatting mode of the disk.


9 sectors/ track


15 sectors/ track

+ 5V

Write data to the FDD. This signal is active high.

The precompensation is given to this write data.

Select signal to the external HDC.

This signal is active (low) when the I/O address is

170H-177H.

This signal controls the direction of printer data port.


External ~


Internal ~

This function is ignored when it is in the external

FDD mode.

Each of PD7-PDO is a printer or parallel data IN bus. When it is in the external FDD mode, each bus is in the high impedance state.

When printer is connected, they are in the output mode.

Printer data bus bit 7.


Printer data bus bit s.





Printer data bus bit o.

Ground

Printer select command. This signal is active high. This signal is issued by the command to address 372H.

Printer auto-feed command. This signal is active high, and is issued by the command to address

372H.

D-8

Pin 1/0 Signal Name

93

94

95

96

97

98

99

100

0

0

I

0

I

I

I

INIT

STROBE

DIREN

FDSLSEN

SAO

RST

FSELSW

GND

Description

Printer initial command. This signal is active low, and is issued by the command to address 372H.

Printer strobe command. This signal is active high, and is issued by the command to address

372H.

This signal is to control the direction of the printer data bus.

When this signal is low, it is in the parallel IN mode, and when it is high, it is in the printer output mode.

This signal is to read the FDD interface signal as below, when it is in the external FDD mode.

INDEX/TRAWCK O/WRITE PROTECTI

READ DATAl DISK CHANGEI READY


Address line. This signal is used to generate printerl FDD control command.

Initial reset signal. This signal is active low.

Internal counters and F/Fs are reset by this signal.

This signal is to change the drive number of the internal FDD. When this signal is low, the drive number is changed to B, and when high, it is changed to A (Normal).

Ground.

D-9

APPENDIX E

EMS GA (Gate Array)

E.l GENERAL

This chip allows application programs to access a vast memory space by the bank switching operation, through a certain memory address which is used as a window .

This Gate Array is used for address conversion, and i t stores page control registers, map registers, CPU/ DMA address decoder and so on.

The EMS Gate Array is a flat package typed chip, and is composed of 80 lead pins.

57

56

......................... -

41

40

80

1

......................... -

16

17

E-l

E.3 SIGNAL DESCRIPTION AND PIN ASSIGNMENT

TABLE E-1 Pin Description

Pin I/O Signal Name

RSET

GND

EXTND

M512K

SBHE

BALE

REFRSH

DMACK

MEMR

XIOR

XIOW

GND

EA20

EA21

SA16

SA15

SA14

SA13

SA12

SA 11

SA10

SA09

GND

SA08

SA07

SA06

SAOs

SA04

SA03

SA02

SA01

SAOO

Vcc

SDO

SD1

SD2

1

2

3

4

I

9

10

11

5

6

7

8

20

21

22

23

24

25

16

17

18

19

26

27

28

29

30

31

12

13 0

14

15

0

I

I

I

I

I

I

I

I

I

I

I

I

I

I

I

I

32 I

33

34 I/O

35

36 liD liD

I

I

I

I

I

I

I

I

I

Descri pti 0 n

Reset signal. This signal is active high.

Ground

Extended memory access disable select.

Conventional memory 512 Kbytes/640 kbytes select

Bus hiqh enable siqnal.

Address latch enable signal.

Refresh signal.

DMA acknowledge signal.

Memory read command

I/O read command liD write command

Ground

Unlatched MA20

Unlatched MA21

Address bus 16

Address bus 15

Address bus 14

Address bus 13

Address bus 12

Address bus 11

Address bus 10

Address bus 09

Ground

Address bus 08

Address bus 07

Address bus 06

Address bus 05

Address bus 04

Address bus 03

Address bus 02

Address bus 01

Address bus 00

+5v

Data bus 0

Data bus 1

Data bus 2

E-3

Pin I/O Signal Name

68

69

70

71

64

65

66

67

60

61

62

63

55

56

57

58

59

51

52

53

54

47

48

49

50

43

44

45

46

37 I/O

38 I/O

39 I/O

40 I/O

41

42

I/O

0

0

0

0

0

0

0

I

I

0

0

0

0

0

0

0

I

I

I

I

I

I

I

I

I

I

I

Description

SD3

SD4

SD5

SD6

SD7

GND

MA20

MA19

MA18

MA17

MA16

MA15

Data bus 3

Data bus 4

Data bus 5

Data bus 6

Data bus 7

Ground

RAM address 20

RAM address 19

RAM address 18

RAM address 17

RAM address 16

RAM address 15

MA14

PDINH

PDINL

GND

CASLSL

CASHSL

RAS4SL

RAS3SL

RAS2SL

RAS1SL

RASOSL

RAS4EN

RAM address 14

RAM parity set H

RAM parity set L

Ground

RAM CAS enable L

RAM CAS enable H

RAM RAS enable signal4

RAM RAS enable signal 3




RAS4 enable signal

RAS3EN

RAS2EN

RAS3 enable signal

RAS2 enable signal

GND Ground

MEMWE Memory write command

A23

A22

A21

A20

A19

A18

A17

Unlatched address bus 23







E-4

Pin 1/0 Signal Name

72

73

74

75

I

I

I

76 0

77 0

78 0

79 0

80 I

A16

Vcc

A15

A14

ERAS

MEM16

DRMRD

10CHK

CPHLDA

Description


+

Sv



Unlatched OR of MA22, 23

Memory word transfer signal

RAM data enable

RAM parity error

CPU hold siQnal

E-5

APPENDIX F

AGS.GA (Gate Array)

F.I GENERAL

AGS stands for Advanced Graphics Subsystem, and is used together with the PEGA2 chip to realize the function of 640 x 400 mode graphics in the CRT or Plasma display.

AGS Gate Array is a flat package typed chip with 100 lead pins in total.

80 51

50

100

1 30

31

F-l

F.2 BLOCK DIAGRAM

<

SYSTEM BUS

(iOCHi<)

SDO-7

MXA

>

Sl TZ

(PDP

(n(K P'HW

PD2,3,4

;:-

--::,

DRV

' - - -

1----"[:]

r--_V"'----.-_V~_,

SEl

I

SEl

MXB J;

~PE**

___

I

SDO r - -

--::, DRV

~----~~

FT1Z

AUT

PDP

DISZ

~-2

I - -

SDOO-19 AGS - GA

REF, DMA,IORZ,

MERZ,IOWZ,

MEWZ,RESZ

UNlZ

MIO

BlK

MESZ

IOSZ

RDP elK

PO* {\ ~

I - -

I - -

I - -

ROMZ

RWEZ l=l

ROM

32 Kbytes

IRO

ESAZ

">.r SRAM

L-wE es

PEGA- 2

(M2BO-7)

" 1\

(M1BO

-7) fI 1\

(MOBO

-7)

DRV t--

~

DRAM

~

'-------' (M3B3 -7)

L - -_ _ _ _ _ _ _

-

FIGURE F-I AGS.GA Block Diagram

F-2

F.3

SIGNAL DESCRIPTION AND PIN ASSIGNMENT

TABLE F-l Pin Description

2

3

4

5

6

7

8

9

10

Pin I/O Signal Name

1

11

12

13

14

15

16

17

18

19

20

21

22

23

24

25

26

27

0

0

I

I

I

I

I

I

I

I

I

I

I

I

I

I

0

0

I

I

I

I

I

I

I

Description

MUXB

MUXA

Multiplex Select A

External Clock/ Dip switch select signal

Multiplex Select B

External Clock/ Dip switch select signal

Vcc

RAMCS

+5V

SRAM chiQselect signal

RAMWE SRAM write enable signal

DMACK System bus address enable signal

SMEMW Memory write command

SMEMR Memory read command lOW I/O write command lOR I/O read commad

This signal is ued to power on the Auto-switch

AUTOSW (DIP-SW1) concernig bit 70f the PEGA2 status read port.

This signal is used to select double or single FONT

FONT

DSPDIS

(DIP-SW4) concernig bit 5 of the PEGA2 status read

port.

This signal is used to disable the system

This signal is used to select Sacandinavian or

CGFONT Normal FONT (DIP-SW6) concernig bit 4 of the

PEGA2 status read port.

GND

REFRSH

SWTCH

RESET

IRQ9

BLANK

MIOSl

POVS

POHS

POSB

POSG

POBl

POGR

Ground

System bus memory refresh signal. When this is low, memory access is enabled.

Status signal from the external4-bit Display type select switch.

System bus reset signal

CRT interrupt signal. This signal is output from the PEGA2, and can be read at the bit 7 of 3C2 port.

This is the signal to indicate that blanking is being executed.

This is the si9nal to select Memory or I/O.

CRT display signal from the PEGA2.


CRT disglay signal from the PEGA2.



CRT displav siqnal from the PEGA2.

F-3

Pin 1/0 Signal Name

28

29

30

31

32

0

0

33 0

34 0

35 I

36 I

I

I

37

38

39

40

41

42

43 0

44 0

45 0

46 0

47

48

49

50

51

I

0

I

0

I

I

0

0

0

Vcc

PORE

POSR

Description

READ

10SEl

MEMSl

I/O select signal

PEGA memory select signal

ROMSl ROM chip select signal

ClKMUX Basic clock for CRT display

PDPSl

UNl

ClK

ClKPDP

GND

GND

SRON

SlT

M3DA2

M3DA1

M3DAO

XA8

ESA

TRP

PEPD4

PEGR

+ 5V



PEGA read I write select signal

Plasmal CRT select signal

This signal is to indicate that the content of the port 3D8 has already been read twice.

This is cleared by the next read or write signal.

Basic clock for display. This is output to the PEGA.

Basic clock for Plasma display

Ground

Ground

This signal is to enable the SR signal.

When this is high, CRT output pin No.2 is grounded.

NMI generate timing signal

Address data bit 2 of the DRAM plane 3. In this

GA, system address bus is output to the PEGA.

Address data bit 1 of the DRAM plane 3.

Address data bit 0 of the DRAM plane 3.

I/O port address bit 8 for display

When XA8 = SA8, the port 3XX is accessed.

" XA8 = SA8, the port 2XX is accessed.

PEGA system address input enable signal.

When this is low, system address is output to M3 bus.

Trap (NMI) generate signal

Plasma display signal. This signal is active low.

Pins 51,54,55,57,58,59,60,61 are used for selection of CRT or Plasma display as follows, depending on their combinations.

CRT

PEVS (Pin 58) 9Pin

PDP

VS

PEHS (Pin 59)

PESB (Pin 54)

PESG (pin 55)

8pin

7pin

6pin

HS

PD1

PS4

PEBl (pin 61)

PEGR (pin 51)

PERE (pin 57)

PESR (pin 60)

Spin

4pin

3pin

2pin

PS3

PS2

PS1

SCK

F-4

Pin I/O Signal Name

56

57

58

59

60

61

52

53

54

55

0

0

0

0

62

63

64

65

66

67

I

I

68

69

70

71

I

I

I

I

72 I/O

73 I/O

74 I/O

75 I/O

76 I/O

77 I/O

78

79 I/O

I

I

I

87

88

89

90

80 I/O

81 I

82 I

83

84

85

86

I

I

I

I

I

I

I

0

0

0

0

0

PEPD2

Vcc

PESB

PESG

PEPD3

PERE

PEVS

PEHS

PESR

PEBL

SA3

SA2

SA1

SAO

SDO

SD1

SD2

SD3

SA8

SA7

SA6

GND

SA5

SA4

SD4

SD5

Vee

SD6

SD7

SA19

SA18

SA17

SA16

SA15

SA14

SA 13

SA12

SA 11

GND

Description

Plasma display signal. This siBnal is active low.

+ 5V

Refer to the descriQtion of the Qin 51.

Refer to the description of the pin 51.

Plasma display signal. This signal is active low.

Refer to the description of the pin 51.

Refer to the description of the ~in 51.

Refer to the descriQtion of the ~in 51.

Refer to the description of theQin 51.

Refer to the descrif>tion of the pin 51. system address bus bit 8. system address bus bit 7. system address bus bit 6.

Ground system address bus bit 5. system address bus bit 4. system address bus bit 3. system address bus bit 2. system address bus bit 1. system address bus bit o.







+ 5V


System data bus bit 7. system address bus bit 19. system add ress bus bit 18. system address bus bit 17. system address bus bit 16. system address bus bit 15. system address bus bit 14. system address bus bit 13. system address bus bit 12. system address bus bit 11.

Ground

F-5

Pin I/O Signal Name

91

92

93

94

95

96 liD

97 liD

98

99

100

I

I liD liD liD liD liD liD

SA10

SA9

LD7

LD6

LD5

LD4

LD3

LD2

LD1

LDO

Description system address bus bit 10. system address bus bit 9.

Local data bus 7 among PEGA, ROM, and SRAM.

Local data bus 6 amonq PEGA, ROM, and SRAM.

Local data bus 5 amonq PEGA, ROM, and SRAM.





Local data bus 0 amona PEGA ROM. and SRAM.

F-6

APPENDIX G

PEGA2

G.l GENERAL

The PEGA2 is a single solution for design of a video controller.

This chip is composed of 84 pins with 40 multiplexed bidirectional signals for handling RAM address and data, CPU address and data, as well as various I/O bits.

Four busses of 8 bits each connect to the four banks of

DRAM, and the fifth 8 bits is used for CPU address and data.

54

53

75

74

84

1

12

32

G-l

G. 2 BLOCK DIAGRAM

RAM PLAN EO

RAM PLAN El

RAM PLAN E2

RAM PLAN E3

CPU

ADDRES S

CPU DAT A

~

PEGA 2

,..

AGS-GA

~

CPUINTFC

SEQUENCER

~

CRT CONTROL

VIDEO CONTROL

RD/W R

CLOC K

RES ET lOS EL

MEM SL

-.-

FIGURE G-I PEGA2 Block Diagram

POVS

POHS

VIDEO OUT

VDISP

(VIDEO DISPLAY

ENABLE)

IRQ

(INTERRUPT

REQUEST)

CPU

ADDRESS MUX

CONTROL

RAM CONTROL

10RDY

G-2

The PEGA2 uses 64Kx4 DRAMs with one RAM bank consisting of 2 chips. Within a bank, one chip connects 4 data lines to the low 4 bus signals and the other chip connects 5 data lines to the high 4 bus signals.

The RAS, CAS, and OE signals are common to all 4 banks, but each bank uses a separate WE signal.

The signals required for controlling the external bus multiplexers are generated with a minimum of additional logic. External logic as also required for PC bus interface functions, including address decoding, bus direction control and interrupt handling.

The eight video outputs of the PEGA2 are designed to drive a 9-pin monitor cable directly. Switching logic inside the

PEGA 2 correctly configures the video data signals (RrGgBb,

IRGB or Video/ Intensity) for the particular monitor being driven.

A TTG-compatib1e clock, up to 26 MHz drives the PEGA2.

A reset pin initializes the chip and a total of 12 pins are used for power and ground connections.

G-3

F.3 SIGNAL DESCRIPTION AND PIN ASSIGNMENT

TABLE G-l Pin Description

7 I/O

8 I/O

9 I/O

10

11

0

12 I/O

13 I/O

14 I/O

15

16 I/O

17 I/O

18 I/O

19 I/O

20 I/O

21

22

23 I/O

24 I/O

25 I/O

26 I/O

Pin I/O Signal Name

1

2 I/O

3

4

5

6

27

I/O

I/O

I/O

I/O

I/O

Description

GND

M3DA-4

M3DA-5

M3DA-6

M3DA-7

M2DA-0

M2DA-l

M2DA-2

Ground

Memory data and address bit 4, plane 3.

CPU add ress bit 10 at ESAN.


CPU address bit 11 at ESAN.


CPU add ress bit 12 at ESAN.






LIGHT PEN Switch at ESAN.


SD1

SD2

SD3

Vcc

GND

SD4

SDS

SD6

SD7

M2DA-3 Memory data and address bit 3, plane 2.

Active low, bits DO and Dlof Figure Control

FCVO

Register at I/O port 3XA; supplied to Feature

FCV1

Connector.




GND

M2DA-7

SDO

Ground


CPU data bit 1

IRQ9

CPU data bit 2

CPU data bit 3

CPU data bit 4

+5V

Ground

CPU data bit S

CPU data bit 6

CPU data bit 7

CPU data bit 8

Active high, indicates that an interrupt has been generated. Can be set to high impedance under program control (3XS-11 H, bitS).

Gets read as STATUS 0 bit 7.

G-4

Pin I/O Signal Name

28

29

30

31

32

33

41

42

43

44

45

34 0

35

36

37

38

39

40

0

I

I

I

I

46

0

0

0

0

0

I

47

48 0

49 0

50

51

52

53

0

0

0

0

10RDY

GND

COE

ESA

CCAS

MIOSL

GRAPH

RAS

CWO

CW1

CW2

CW3

RESET

CLOCK

READ

GND

Vcc

10SEL

MEMSL

Vcc

POHS

POVS

POSR

POSG

BLANK

ATRSLN

Description

Active high, indicates that memory access has been completed. When it is low,it is used to cause wait states to be inserted into the memory access cycles. It is high impedance when memory is not selected.

Ground

Active low, output enable for video planes

Active low enable for system address bits

(6-13, 14) and LPSW multiplexed with memory datal address bits (see above).

Active low, column address strobe

Active high, Memory or I/O selected. Controls external data bus driver.

Active high, indicates that a graphics mode is active; low indicates alphanumeric mode.

Active low, row address strobe.

Active low, write signal for video plane 0




Active low, master reset supplied by external power on circuitry.

26.0 MHz max.

Active high while reading PEGA I/O port or video memory.

Gound

+5V

Active low. I/O select indicates accessing any

PEGA I/O port.

Active low. memory select indicates accessing video memory.

+ 5V

Horizontal Sync Signal

Vertical Sync Signal (active low for monochrome monitors and IBM Enhanced Color Display).

Secondary Red Output

Secondary green output or intensity

Active high, Horizontal or Vertical blanking for use with feature connector.

Active low, Attribute/ shift load for use with feature connector.

G-S

Pin I/O Signal Name

54 0

55

56

0

0

57 0

58 0

59 I/O

60 I/O

61 I/O

62 I/O

63 I/O

64

65

66 I/O

67 I/O

68 I/O

69 I/O

70 I/O

71

72 I/O

73

74

75

VDISP

POSB

PORE

POGR

POBL

M1DAO

M1DAl

M1DA2

M1DA3

M1DA4

GND

Vcc

M1DA5

M1DA6

M1DA7

MODAO

MODAl

GND

MODA2

MODA3

MODA4

Vcc

Description

Active high, Video display enable, indicates active video (un blanked, not border).

Secondary blue output or monochrome video.

Primary red output

Primary green output

Primary blue output


Memory data and address bit " plane 1.



Memory data and add ress bit 4, plane 1.

Ground

+5V

Memorydata and address bit 5, plane 1.


Memory data and address bit 7, planel.

Memory data and add ress bit 0, plane O.

Memory data and address bit 1, plane O.

Ground

Memory data and address bit 2, plane o.

Memory data and add ress bit 3, plane O.


76 0

77 I/O

78 I/O

79 I/O

80 I/O

81 I/O

82 I/O

83 I/O

84

UNLOCK

MODA5

MODA6

MODA7

M3DAO

M3DAl

M3DA2

M3DA3

Vcc

Active low, goes active after two successive reads of the old mode register(3D8 or 3B8). Goes inactive at the end of of the next /0 read or write cycle.



Memory data and address bit 7, plane o.


CPU address bit 6 at ESAN







+ 5V

G-6

Toshiba T3200 - Maintenance Manual

Error in CMOS. Bad battery

Check system Then. press [Fl]

Error in CMOS. Bad check sum

Check system Then. press [Fl] key .•••.•

Error in CMOS. Bad configuration

Check system Then. press [Fl]

Error in CMOS. Bad memory size

Check system Then. press [Fl]

Error in CMOS. Bad time function

Check system Then. press [Fl]

HOD Load error or Bad system disk

Insert system disk in drive

Press any key when ready ..•..

o

o

2.5 FLOPPY DISK DRIVE ISOLATION PROCEDURES

HOD Load error or Bad system disk

Insert system disk in drive

Press any key when ready ..•••

PROCEDURE 7

Toshiba Personal Computer MS-DOS Version 3.20 / (RXXXXX)

(C) Copyright Toshiba

(C) Copyright Microsoft

Corporation 1983,1986

Corporation 1981,1986

Current date is XXX X-XX-19XX

Enter new date (mm-dd-yy) :

Current time is X:XX:XX,XX

Enter new time :

COMMAND Version 3.20

PROCBDURE 3

PROCEDURE 4

xx

xxx

3-3

"*".

"*"

xx-xx-xxxx

Interleave number (3/1-9)

Drive number select

Press [Bad track number (CCCH) key

Interleave number (3/1-9)

Drive number select

Drive number select (l:ll, 2:12)

Landing seek completed. (HOO#!)

Press [enter] key.

001

02 0000 103 00001 00 00

001

01 0000 180 00001 00 00

Printer wrap around test (YIN) 1

Async wrap around test (YIN) 1

Copy complete

Another copy (1:Yes/2:No)

FDD number (1:A/2:B)

Another dump (1:Yes/2:No)

Floppy disk setup

0: No drive

(1) Floppy disk driveR1 type

2 ?

0: No drive

(2) Floppy disk driveR1 type

0 ?

Hard disk setup

(3) Is hard disk available? (YIN)

Extended memory setup ]

0: No memory

1: 0.5MB

2: 1MB

3: 1.5MB

4: 2MB

5: 2.5MB

6: 3MB

(4) Extended memory size

06

3MB]

(Expanded memory size [384KB+ OMB])

[External display card type setup]

1: Color display card (40*25 column)