RT8171C - Richtek Technology

RT8171C - Richtek Technology
®
RT8171C
Single-Phase Controller with Integrated Driver for VR12.1
Mobile CPU Core Power Supply
General Description
Features
The RT8171C is a VR12.1 compliant CPU power controller
which includes one voltage rails : a 1 phase synchronous
buck controller, the CORE VR. The RT8171C has zero
load-line function to support zero load-line application. The
RT8171C adopts G-NAVPTM (Green Native AVP), which is
Richtek's proprietary topology derived from finite DC gain
compensator with current mode control, making it an easy
to set the PWM controller, meeting all Intel CPU
requirements of AVP (Active Voltage Positioning). Based
on the G-NAVPTM topology, the RT8171C also features a
quick response mechanism for optimized AVP performance
during load transient. The RT8171C supports mode
transition function with various operating states. A Serial
VID (SVID) interface is built in the RT8171C to
communicate with Intel VR12.1 compliant CPU. The
RT8171C supports VID on-the-fly function with three
different slew rates : Fast, Slow and Decay. By utilizing
the G-NAVPTM topology, the operating frequency of the
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RT8171C varies with VID, load and input voltage to further
enhance the efficiency even in CCM. The built-in high
accuracy DAC converts the SVID code ranging from 0.25V
to 1.52V with 5mV per step, as shown in Table 1. The
RT8171C integrates a high accuracy ADC for platform
setting functions, such as quick response or over current
level. The RT8171C provides VR ready output signals. It
also features complete fault protection functions including
Over Voltage (OV), Under Voltage (UV), Negative Voltage
(NV), Over Current (OC) and Under Voltage Lockout
(UVLO). The RT8171C is available in a WQFN-32L 4x4
small foot print package.
VR12.1 Compatible Power Management States
Switching Frequency up to 1MHz
Serial VID Interface
Signal Phase PWM Controller
G-NAVPTM Topology
0.5% DAC Accuracy
Differential Remote Voltage Sensing
Built-in ADC for Platform Programming
System Thermal Compensated AVP
Diode Emulation Mode at Light Load Condition
Fast transient Response
VR Ready Indicator
Thermal Throttling
Current Monitor Output
Low Quiescent Power at PS3 and PS4
OVP, UVP, OCP, UVLO, NVP
Address Flip Function
DVID Improvement
Applications



VR12.1 Intel Core Supply
Notebook CPU Core Supply
AVP Step-Down Converter
Marking Information
3L= : Product Code
3L=YM
DNN
YMDNN : Date Code
Simplified Application Circuit
VIN
To PCH
To CPU
RT8171C
VR_READY
VR_HOT
UGATE
VCLK
PHASE
VDIO
VCORE
LGATE
ALERT
Copyright © 2015 Richtek Technology Corporation. All rights reserved.
DS8171C-02
September 2015
is a registered trademark of Richtek Technology Corporation.
www.richtek.com
1
RT8171C
Pin Configurations
Ordering Information
RT8171C
NC
IMON
SETGND
VBOOTSEL
ISENP
ISENN
EN
UGATE
(TOP VIEW)
Package Type
QW : WQFN-32L 4x4 (W-Type)
Lead Plating System
G : Green (Halogen Free and Pb Free)
Note :
Richtek products are :

RoHS compliant and compatible with the current requirements of IPC/JEDEC J-STD-020.
Suitable for use in SnPb or Pb-free soldering processes.
1
24
2
23
3
22
4
21
GND
5
6
20
33
7
8
19
18
17
DRV_EN
PHASE
BOOT
PVCC
LGATE
PGND
DRV_EN
VR_READY
9 10 11 12 13 14 15 16
SET3
IBIAS
TSEN
VR_HOT
VDIO
ALERT
VCLK
TONSET

32 31 30 29 28 27 26 25
VREF
COMP
FB
VSEN
RGND
VCC
SET1
SET2
WQFN-32L 4x4
Functional Pin Description
Pin No.
Pin Name
Pin Function
1
VREF
Fixed 0.6V Output Reference Voltage. This voltage is only used to offset the
output voltage of the IMON pin. Between this pin and GND must be placed a
exact 0.47F decoupling capacitor.
2
COMP
CORE VR Compensation Node. This pin is the output node of the error
amplifier.
3
FB
CORE VR Feedback Voltage Input. This pin is the negative input node of the
error amplifier.
4
VSEN
CORE VR Voltage Sense Input. This pin is connected to the terminal of CORE
VR output voltage.
5
RGND
Return Ground for CORE VR. This pin is the negative node of the differential
remote voltage sensing.
6
VCC
Supply Voltage Input. Connect this pin to GND via a ceramic capacitor larger
than 2.2F. The decoupling capacitor should be placed as close to the
controller as possible. If the ripple of voltage source is large, RC low pass filter
is recommended. (R = 20, C = 2.2F)
7
SET1
1st Platform Setting. Platform can use this to set DVID compensation time,
RSET, DVID compensation width and OCS.
8
SET2
2nd Platform Setting. Platform can use this to set ICCMAX, QRTH and
QRWIDTH.
9
SET3
3rd Platform Setting. Platform can use this to set zero load-line, anti-overshoot,
ADDR, switching frequency range, shrink TON at PS2 and PS3 and ZCD
threshold voltage.
10
IBIAS
Internal Bias Current Setting. Connecting this pin to GND by a 100k resistor
can set the internal current. Do not connect this pin to GND by a bypass
capacitor.
11
TSEN
Thermal Sense Input of CORE VR.
Copyright © 2015 Richtek Technology Corporation. All rights reserved.
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is a registered trademark of Richtek Technology Corporation.
DS8171C-02
September 2015
RT8171C
Pin No.
Pin Name
Pin Function
12
VR_HOT
Thermal Monitor Output. (Active Low).
13
VDIO
VR and CPU Data Transmission Interface.
14
ALERT
SVID Alert. (Active Low).
15
VCLK
Synchronous Clock from the CPU.
16
TONSET
CORE VR On-Time Setting. Connect this pin to input voltage with one resistor.
By this resistor value, ripple size in PWM-mode can be set.
17
VR_READY
VR Ready Indicator of CORE VR.
DRV_EN
Internal Driv er Enable Control. These two pins should be floating and be
connected together.
19
PGND
Driver Power Ground.
20
LGATE
Low-Side Gate Driver Output. This pin drives the Gate of low-side MOSFET.
21
PVCC
Driver Power. Connect this pin to GND by a ceramic capacitor 2.2F at least.
22
BOOT
Bootstrap Supply for High-Side MOSFET.
23
PHASE
Switch Node. This Pin is Return Node of The Core VR high-side driver. Connect
this pin to the high-side MOSFET Source together with the low-side MOSFET
Drain and the inductor.
25
UGATE
High-Side Gate Driv er Output. This pin drives the Gate of high-side MOSFET.
26
EN
VR Enable Control Input.
27
ISENN
Negative Current Sense Input.
28
ISENP
Positive Current Sense Input.
29
VBOOTSEL
Boot Voltage Setting. Connect to a resistor divider between VCC and SETGND
pins. By using this pin, BOOT voltage can be set to 0.9V, 1V or 1.1V.
30
SETGND
Ground Return for the Platform Setting Pins : SET1, SET2, SET3, VBOOTSEL
and TSEN. The SETGND pin is connected to ground except at PS3 and PS4.
31
IMON
CPU Core Current Monitor Output. This pin outputs a voltage proportional to the
inductor current. Do not connect a bypass capacitor from this pin to GND or the
VREF pin.
32
NC
No Internal Connection.
GND
Ground. The exposed pad must be soldered to a large PCB and connected to
GND for maximum power dissipation.
18, 24
33
(Exposed Pad)
Copyright © 2015 Richtek Technology Corporation. All rights reserved.
DS8171C-02
September 2015
is a registered trademark of Richtek Technology Corporation.
www.richtek.com
3
RT8171C
SETGND
VR_READY
VCC
EN
VSEN
VR_HOT
ALERT
VDIO
IMONI
VCLK
TSEN
SET3
SET2
SET1
VBOOTSEL
Function Block Diagram
x4
UVLO
MUX
GND
IBIAS
ADC
Loop Control
Protection Logic
SVID Interface Configuration
Registers Control Logic
TZ <7:0>
DIMON <7:0>
ZCD <2:0>
EN_0LL
EN_ANTI_OVS
From Control Logic
RGND
DAC
Soft-Start & Slew
Rate Control
ERROR
AMP
VSET
+
FB
-
ISENN
-
BOOT
+
+
CMP
PWM
UGATE
TON
GEN
PWM
Driver
QR
PGND
QRWIDTH
-
IMONI
OCP_SUM,
OCP_SPIKE
DRV_EN
TON
+
PHASE
LGATE
-
Current Mirror
Current Mirror
+
PVCC
Offset
Cancellation
COMP
ISENP
TONSET
DVID_TH <2:0>
DVID_WTH <2:0>
OCS <2:0>
RSET <2:0>
ICCMAX <7:0>
QR_TH <2:0>
QR_WIDTH <2:0>
RSET
+
OC
To Protection Logic
-
VSEN
OV/UV/NV
IMON VREF
Copyright © 2015 Richtek Technology Corporation. All rights reserved.
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is a registered trademark of Richtek Technology Corporation.
DS8171C-02
September 2015
RT8171C
Operation
The RT8171C adopts G-NAVPTM (Green Native AVP) which
is Richtek's proprietary topology derived from finite DC
gain of EA amplifier with current mode control, making it
easy to set the droop to meet all Intel CPU requirements
of AVP (Adaptive Voltage Positioning).
Loop Control Protection Logic
The RT8171C adopts the G-NAVPTM controller, which is
one type of current mode constant on-time control with
DC offset cancellation. The approach can not only improve
DC offset problem for increasing system accuracy but also
has fast transient response. When current feedback signal
reaches COMP signal, the RT8171C generates an ontime width to achieve PWM modulation.
Cancel the current/voltage ripple issue to get the accurate
VSEN.
Besides, RT8171C also can support zero load-line
application.
Generate an analog signal according to the digital code
generated by Control Logic.
TON GEN
Soft-Start & Slew Rate Control
Generate the PWM signal sequentially according to the
phase control signal from the Loop Control Protection
Logic.
Control the Dynamic VID slew rate of VSET according to
the SetVID fast or SetVID slow. And the soft-start slew
rate is the slow slew rate.
It controls the power on sequence and the protection
behavior.
Offset Cancellation
UVLO
Detect the PVCC and VCC voltage and issue POR signal
as they are high enough.
DAC
SVID Interface/Configuration Registers/Control
Logic
The interface that receives the SVID signal from CPU and
sends the relative signals to Loop Control Protection Logic
to execute the action by CPU.
The registers save the pin setting data from ADC output.
The Control Logic controls the ADC timing and generates
the digital code of the VID that is relative to VSEN.
Copyright © 2015 Richtek Technology Corporation. All rights reserved.
DS8171C-02
September 2015
is a registered trademark of Richtek Technology Corporation.
www.richtek.com
5
RT8171C
Table 1. VR12.1 VID Code Table
VID7
VID6
VID5
VID4
VID3
VID2
VID1
VID0
HEX
Voltage (V)
0
0
0
0
0
0
0
1
01
0.250
0
0
0
0
0
0
1
0
02
0.255
0
0
0
0
0
0
1
1
03
0.260
0
0
0
0
0
1
0
0
04
0.265
0
0
0
0
0
1
0
1
05
0.270
0
0
0
0
0
1
1
0
06
0.275
0
0
0
0
0
1
1
1
07
0.280
0
0
0
0
1
0
0
0
08
0.285
0
0
0
0
1
0
0
1
09
0.290
0
0
0
0
1
0
1
0
0A
0.295
0
0
0
0
1
0
1
1
0B
0.300
0
0
0
0
1
1
0
0
0C
0.305
0
0
0
0
1
1
0
1
0D
0.310
0
0
0
0
1
1
1
0
0E
0.315
0
0
0
0
1
1
1
1
0F
0.320
0
0
0
1
0
0
0
0
10
0.325
0
0
0
1
0
0
0
1
11
0.330
0
0
0
1
0
0
1
0
12
0.335
0
0
0
1
0
0
1
1
13
0.340
0
0
0
1
0
1
0
0
14
0.345
0
0
0
1
0
1
0
1
15
0.350
0
0
0
1
0
1
1
0
16
0.355
0
0
0
1
0
1
1
1
17
0.360
0
0
0
1
1
0
0
0
18
0.365
0
0
0
1
1
0
0
1
19
0.370
0
0
0
1
1
0
1
0
1A
0.375
0
0
0
1
1
0
1
1
1B
0.380
0
0
0
1
1
1
0
0
1C
0.385
0
0
0
1
1
1
0
1
1D
0.390
0
0
0
1
1
1
1
0
1E
0.395
0
0
0
1
1
1
1
1
1F
0.400
0
0
1
0
0
0
0
0
20
0.405
0
0
1
0
0
0
0
1
21
0.410
0
0
1
0
0
0
1
0
22
0.415
0
0
1
0
0
0
1
1
23
0.420
0
0
1
0
0
1
0
0
24
0.425
0
0
1
0
0
1
0
1
25
0.430
0
0
1
0
0
1
1
0
26
0.435
0
0
1
0
0
1
1
1
27
0.440
0
0
1
0
1
0
0
0
28
0.445
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is a registered trademark of Richtek Technology Corporation.
DS8171C-02
September 2015
RT8171C
VID7
VID6
VID5
VID4
VID3
VID2
VID1
VID0
HEX
Voltage (V)
0
0
1
0
1
0
0
1
29
0.450
0
0
1
0
1
0
1
0
2A
0.455
0
0
1
0
1
0
1
1
2B
0.460
0
0
1
0
1
1
0
0
2C
0.465
0
0
1
0
1
1
0
1
2D
0.470
0
0
1
0
1
1
1
0
2E
0.475
0
0
1
0
1
1
1
1
2F
0.480
0
0
1
1
0
0
0
0
30
0.485
0
0
1
1
0
0
0
1
31
0.490
0
0
1
1
0
0
1
0
32
0.495
0
0
1
1
0
0
1
1
33
0.500
0
0
1
1
0
1
0
0
34
0.505
0
0
1
1
0
1
0
1
35
0.510
0
0
1
1
0
1
1
0
36
0.515
0
0
1
1
0
1
1
1
37
0.520
0
0
1
1
1
0
0
0
38
0.525
0
0
1
1
1
0
0
1
39
0.530
0
0
1
1
1
0
1
0
3A
0.535
0
0
1
1
1
0
1
1
3B
0.540
0
0
1
1
1
1
0
0
3C
0.545
0
0
1
1
1
1
0
1
3D
0.550
0
0
1
1
1
1
1
0
3E
0.555
0
0
1
1
1
1
1
1
3F
0.560
0
1
0
0
0
0
0
0
40
0.565
0
1
0
0
0
0
0
1
41
0.570
0
1
0
0
0
0
1
0
42
0.575
0
1
0
0
0
0
1
1
43
0.580
0
1
0
0
0
1
0
0
44
0.585
0
1
0
0
0
1
0
1
45
0.590
0
1
0
0
0
1
1
0
46
0.595
0
1
0
0
0
1
1
1
47
0.600
0
1
0
0
1
0
0
0
48
0.605
0
1
0
0
1
0
0
1
49
0.610
0
1
0
0
1
0
1
0
4A
0.615
0
1
0
0
1
0
1
1
4B
0.620
0
1
0
0
1
1
0
0
4C
0.625
0
1
0
0
1
1
0
1
4D
0.630
0
1
0
0
1
1
1
0
4E
0.635
0
1
0
0
1
1
1
1
4F
0.640
0
1
0
1
0
0
0
0
50
0.645
0
1
0
1
0
0
0
1
51
0.650
Copyright © 2015 Richtek Technology Corporation. All rights reserved.
DS8171C-02
September 2015
is a registered trademark of Richtek Technology Corporation.
www.richtek.com
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RT8171C
VID7
VID6
VID5
VID4
VID3
VID2
VID1
VID0
HEX
Voltage (V)
0
1
0
1
0
0
1
0
52
0.655
0
1
0
1
0
0
1
1
53
0.660
0
1
0
1
0
1
0
0
54
0.665
0
1
0
1
0
1
0
1
55
0.670
0
1
0
1
0
1
1
0
56
0.675
0
1
0
1
0
1
1
1
57
0.680
0
1
0
1
1
0
0
0
58
0.685
0
1
0
1
1
0
0
1
59
0.690
0
1
0
1
1
0
1
0
5A
0.695
0
1
0
1
1
0
1
1
5B
0.700
0
1
0
1
1
1
0
0
5C
0.705
0
1
0
1
1
1
0
1
5D
0.710
0
1
0
1
1
1
1
0
5E
0.715
0
1
0
1
1
1
1
1
5F
0.720
0
1
1
0
0
0
0
0
60
0.725
0
1
1
0
0
0
0
1
61
0.730
0
1
1
0
0
0
1
0
62
0.735
0
1
1
0
0
0
1
1
63
0.740
0
1
1
0
0
1
0
0
64
0.745
0
1
1
0
0
1
0
1
65
0.750
0
1
1
0
0
1
1
0
66
0.755
0
1
1
0
0
1
1
1
67
0.760
0
1
1
0
1
0
0
0
68
0.765
0
1
1
0
1
0
0
1
69
0.770
0
1
1
0
1
0
1
0
6A
0.775
0
1
1
0
1
0
1
1
6B
0.780
0
1
1
0
1
1
0
0
6C
0.785
0
1
1
0
1
1
0
1
6D
0.790
0
1
1
0
1
1
1
0
6E
0.795
0
1
1
0
1
1
1
1
6F
0.800
0
1
1
1
0
0
0
0
70
0.805
0
1
1
1
0
0
0
1
71
0.810
0
1
1
1
0
0
1
0
72
0.815
0
1
1
1
0
0
1
1
73
0.820
0
1
1
1
0
1
0
0
74
0.825
0
1
1
1
0
1
0
1
75
0.830
0
1
1
1
0
1
1
0
76
0.835
0
1
1
1
0
1
1
1
77
0.840
0
1
1
1
1
0
0
0
78
0.845
0
1
1
1
1
0
0
1
79
0.850
0
1
1
1
1
0
1
0
7A
0.855
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is a registered trademark of Richtek Technology Corporation.
DS8171C-02
September 2015
RT8171C
VID7
VID6
VID5
VID4
VID3
VID2
VID1
VID0
HEX
Voltage (V)
0
1
1
1
1
0
1
1
7B
0.860
0
1
1
1
1
1
0
0
7C
0.865
0
1
1
1
1
1
0
1
7D
0.870
0
1
1
1
1
1
1
0
7E
0.875
0
1
1
1
1
1
1
1
7F
0.880
1
0
0
0
0
0
0
0
80
0.885
1
0
0
0
0
0
0
1
81
0.890
1
0
0
0
0
0
1
0
82
0.895
1
0
0
0
0
0
1
1
83
0.900
1
0
0
0
0
1
0
0
84
0.905
1
0
0
0
0
1
0
1
85
0.910
1
0
0
0
0
1
1
0
86
0.915
1
0
0
0
0
1
1
1
87
0.920
1
0
0
0
1
0
0
0
88
0.925
1
0
0
0
1
0
0
1
89
0.930
1
0
0
0
1
0
1
0
8A
0.935
1
0
0
0
1
0
1
1
8B
0.940
1
0
0
0
1
1
0
0
8C
0.945
1
0
0
0
1
1
0
1
8D
0.950
1
0
0
0
1
1
1
0
8E
0.955
1
0
0
0
1
1
1
1
8F
0.960
1
0
0
1
0
0
0
0
90
0.965
1
0
0
1
0
0
0
1
91
0.970
1
0
0
1
0
0
1
0
92
0.975
1
0
0
1
0
0
1
1
93
0.980
1
0
0
1
0
1
0
0
94
0.985
1
0
0
1
0
1
0
1
95
0.990
1
0
0
1
0
1
1
0
96
0.995
1
0
0
1
0
1
1
1
97
1.000
1
0
0
1
1
0
0
0
98
1.005
1
0
0
1
1
0
0
1
99
1.010
1
0
0
1
1
0
1
0
9A
1.015
1
0
0
1
1
0
1
1
9B
1.020
1
0
0
1
1
1
0
0
9C
1.025
1
0
0
1
1
1
0
1
9D
1.030
1
0
0
1
1
1
1
0
9E
1.035
1
0
0
1
1
1
1
1
9F
1.040
1
0
1
0
0
0
0
0
A0
1.045
1
0
1
0
0
0
0
1
A1
1.050
1
0
1
0
0
0
1
0
A2
1.055
1
0
1
0
0
0
1
1
A3
1.060
Copyright © 2015 Richtek Technology Corporation. All rights reserved.
DS8171C-02
September 2015
is a registered trademark of Richtek Technology Corporation.
www.richtek.com
9
RT8171C
VID7
VID6
VID5
VID4
VID3
VID2
VID1
VID0
HEX
Voltage (V)
1
0
1
0
0
1
0
0
A4
1.065
1
0
1
0
0
1
0
1
A5
1.070
1
0
1
0
0
1
1
0
A6
1.075
1
0
1
0
0
1
1
1
A7
1.080
1
0
1
0
1
0
0
0
A8
1.085
1
0
1
0
1
0
0
1
A9
1.090
1
0
1
0
1
0
1
0
AA
1.095
1
0
1
0
1
0
1
1
AB
1.100
1
0
1
0
1
1
0
0
AC
1.105
1
0
1
0
1
1
0
1
AD
1.110
1
0
1
0
1
1
1
0
AE
1.115
1
0
1
0
1
1
1
1
AF
1.120
1
0
1
1
0
0
0
0
B0
1.125
1
0
1
1
0
0
0
1
B1
1.130
1
0
1
1
0
0
1
0
B2
1.135
1
0
1
1
0
0
1
1
B3
1.140
1
0
1
1
0
1
0
0
B4
1.145
1
0
1
1
0
1
0
1
B5
1.150
1
0
1
1
0
1
1
0
B6
1.155
1
0
1
1
0
1
1
1
B7
1.160
1
0
1
1
1
0
0
0
B8
1.165
1
0
1
1
1
0
0
1
B9
1.170
1
0
1
1
1
0
1
0
BA
1.175
1
0
1
1
1
0
1
1
BB
1.180
1
0
1
1
1
1
0
0
BC
1.185
1
0
1
1
1
1
0
1
BD
1.190
1
0
1
1
1
1
1
0
BE
1.195
1
0
1
1
1
1
1
1
BF
1.200
1
1
0
0
0
0
0
0
C0
1.205
1
1
0
0
0
0
0
1
C1
1.210
1
1
0
0
0
0
1
0
C2
1.215
1
1
0
0
0
0
1
1
C3
1.220
1
1
0
0
0
1
0
0
C4
1.225
1
1
0
0
0
1
0
1
C5
1.230
1
1
0
0
0
1
1
0
C6
1.235
1
1
0
0
0
1
1
1
C7
1.240
1
1
0
0
1
0
0
0
C8
1.245
1
1
0
0
1
0
0
1
C9
1.250
1
1
0
0
1
0
1
0
CA
1.255
1
1
0
0
1
0
1
1
CB
1.260
1
1
0
0
1
1
0
0
CC
1.265
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10
is a registered trademark of Richtek Technology Corporation.
DS8171C-02
September 2015
RT8171C
VID7
VID6
VID5
VID4
VID3
VID2
VID1
VID0
HEX
Voltage (V)
1
1
0
0
1
1
0
1
CD
1.270
1
1
0
0
1
1
1
0
CE
1.275
1
1
0
0
1
1
1
1
CF
1.280
1
1
0
1
0
0
0
0
D0
1.285
1
1
0
1
0
0
0
1
D1
1.290
1
1
0
1
0
0
1
0
D2
1.295
1
1
0
1
0
0
1
1
D3
1.300
1
1
0
1
0
1
0
0
D4
1.305
1
1
0
1
0
1
0
1
D5
1.310
1
1
0
1
0
1
1
0
D6
1.315
1
1
0
1
0
1
1
1
D7
1.320
1
1
0
1
1
0
0
0
D8
1.325
1
1
0
1
1
0
0
1
D9
1.330
1
1
0
1
1
0
1
0
DA
1.335
1
1
0
1
1
0
1
1
DB
1.340
1
1
0
1
1
1
0
0
DC
1.345
1
1
0
1
1
1
0
1
DD
1.350
1
1
0
1
1
1
1
0
DE
1.355
1
1
0
1
1
1
1
1
DF
1.360
1
1
1
0
0
0
0
0
E0
1.365
1
1
1
0
0
0
0
1
E1
1.370
1
1
1
0
0
0
1
0
E2
1.375
1
1
1
0
0
0
1
1
E3
1.380
1
1
1
0
0
1
0
0
E4
1.385
1
1
1
0
0
1
0
1
E5
1.390
1
1
1
0
0
1
1
0
E6
1.395
1
1
1
0
0
1
1
1
E7
1.400
1
1
1
0
1
0
0
0
E8
1.405
1
1
1
0
1
0
0
1
E9
1.410
1
1
1
0
1
0
1
0
EA
1.415
1
1
1
0
1
0
1
1
EB
1.420
1
1
1
0
1
1
0
0
EC
1.425
1
1
1
0
1
1
0
1
ED
1.430
1
1
1
0
1
1
1
0
EE
1.435
1
1
1
0
1
1
1
1
EF
1.440
1
1
1
1
0
0
0
0
F0
1.445
1
1
1
1
0
0
0
1
F1
1.450
1
1
1
1
0
0
1
0
F2
1.455
1
1
1
1
0
0
1
1
F3
1.460
1
1
1
1
0
1
0
0
F4
1.465
1
1
1
1
0
1
0
1
F5
1.470
Copyright © 2015 Richtek Technology Corporation. All rights reserved.
DS8171C-02
September 2015
is a registered trademark of Richtek Technology Corporation.
www.richtek.com
11
RT8171C
VID7
VID6
VID5
VID4
VID3
VID2
VID1
VID0
HEX
Voltage (V)
1
1
1
1
0
1
1
0
F6
1.475
1
1
1
1
0
1
1
1
F7
1.480
1
1
1
1
1
0
0
0
F8
1.485
1
1
1
1
1
0
0
1
F9
1.490
1
1
1
1
1
0
1
0
FA
1.495
1
1
1
1
1
0
1
1
FB
1.500
1
1
1
1
1
1
0
0
FC
1.505
1
1
1
1
1
1
0
1
FD
1.510
1
1
1
1
1
1
1
0
FE
1.515
1
1
1
1
1
1
1
1
FF
1.520
Table 2. Standard Serial VID Commands
Code
Commands
Master
Payload
Contents
Slave
Payload
Contents
00h
not supported
N/A
N/A
N/A
01h
SetVID_Fast
VID code
N/A
1. Set new target VID code, VR jumps to new VID target
with controlled default "fast" slew rate 13.2mV/s.
2. Set VR_Settled when VR reaches target VID voltage.
02h
SetVID_Slow
VID code
N/A
1. Set new target VID code, VR jumps to new VID target
with controlled default "slow" slew rate 3.3mV/s.
2. Set VR_Settled when VR reaches target VID voltage.
N/A
1. Set new target VID code, VR jumps to new VID target, but
does not control the slew rate. The output voltage decays
at a rate proportional to the load current.
2. Low-side MOSFET is not allowed to sync current.
3. ACK 11b when target higher than current VOUT voltage.
4. ACK 10b when target lower than current VOUT voltage.
03h
SetVID_Decay
VID code
Description
04h
SetPS
Byte
indicating
power states
N/A
1. Set power state.
2. ACK 11b when not support.
3. ACK 10b even slave not change configuration.
4. ACK 11b for still running SetVID command.
5. VR remains in lower state when receiving SetVID
(decay).
05h
SetRegADR
Pointer of
registers in
data table
N/A
1. Set the pointer of the data register.
2. ACK 11b for address outside of support.
3. NAK 01b for SetADR (all call).
06h
SetReg DAT
New data
register
content
N/A
1. Write the contents to the data register.
2. NAK 01b for SetReg (all call).
07h
GetReg
08h to
1Fh
not supported
Specified
Register
Contents
N/A
N/A
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12
1. Slave returns the contents of the specified register as the
payload.
2. ACK 11b for non support address.
3. NAK 01b for GetReg (all call).
N/A
is a registered trademark of Richtek Technology Corporation.
DS8171C-02
September 2015
RT8171C
Table3. SVID Data and Configuration Register
Index
Register Name
Description
Access
Default
00h
Vendor ID
Vendor ID
RO, Vendor
1Eh
01h
Product ID
Product ID
RO, Vendor
76h
02h
Product Revision
Product Revision
RO, Vendor
00h
05h
Protocol ID
SVID Protocol ID
RO, Vendor
06h
06h
Capability
Bit mapped register, identifies the SVID VR Capabilities
and which of the optional telemetry register is supported.
RO, Vendor
81h
10h
Status_1
Data register containing the status of VR.
R-M, W-PWM
00h
11h
Status_2
Data register containing the status of transmission.
R-M, W-PWM
00h
12h
Temperature
Zone
Data register showing temperature zone that has been
R-M, W-PWM
entered.
00h
15h
IOUT
At PS0 to PS2, IOUT report data from ADC sense IMON
voltage. When power state at PS3, the IOUT report data is R-M, W-PWM
fix to 04h.
00h
1Ch
Status_2_lastread
The register contains a copy of the status_2.
R-M, W-PWM
00h
21h
ICC Max
Data register containing the ICC max the platform
supports. Binary format in A IE 64h = 100A.
RO, Platform
7Dh
22h
Temp Max
Data register containing the temperature max the platform
supports.
Binary format in C IE 64h = 100C.
RO, Platform
64h
24h
SR-fast
Data register containing the capability of fast slew rate the
platform can sustain. Binary format in mV/S IE 0Ch =
12mV/s.
RO
0Ch
25h
SR-slow
Data register containing the capability of slow slew rate.
Binary format in mV/S IE 03h = 3mV/S.
RO
03h
2Ah
Slow Slew Rate
Selector
The register is programmed by master and set the slow
slew rate.
RW, Master
02h
2Bh
PS4 Exit Latency
Data register containing the latency of exiting PS4.
RO
77h
2Ch
PS3 Exit Latency
Data register containing the latency of exiting PS3.
RO
3Fh
2Dh
Enable to Ready
for SVID
Data register containing the latency from Enable assertion
to the VR being ready to accept an SVID command.
RO
BAh
30h
VOUT Max
The register is programmed by master and sets the
maximum VID.
RW, Master
D5h
31h
VID Setting
Data register containing currently programmed VID.
RW, Master
00h
32h
Power State
Register containing the current programmed power state.
RW, Master
00h
33h
Offset
Set offset in VID steps.
RW, Master
00h
34h
Multi VR
Configuration
Bit mapped data register which configures multiple VRs
behavior on the same bus.
RW, Master
01h
35h
Pointer
Scratch pad register for temporary storage of the
SetRegADR pointer register.
RW, Master
30h
Notes :
W-PWM = Write by PWM Only
RO = Read Only
Vendor = Hard Coded by VR Vendor
RW = Read/Write
Platform = Programmed by the Master
R-M = Read by Master
PWM = Programmed by the VR Control IC
Copyright © 2015 Richtek Technology Corporation. All rights reserved.
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September 2015
is a registered trademark of Richtek Technology Corporation.
www.richtek.com
13
RT8171C
Absolute Maximum Ratings














(Note 1)
VCC, PVCC to GND ---------------------------------------------------------------------------------------------- −0.3V to 6V
RGND to GND ------------------------------------------------------------------------------------------------------ −0.3V to 0.3V
TONSET to GND --------------------------------------------------------------------------------------------------- −0.3V to 7.5V
BOOT to PHASE -------------------------------------------------------------------------------------------------- −0.3V to 6V
PHASE to GND
DC --------------------------------------------------------------------------------------------------------------------- −0.3V to 32V
< 20ns --------------------------------------------------------------------------------------------------------------- −8V to 38V
LGATE to GND
DC --------------------------------------------------------------------------------------------------------------------- (GND − 0.3V) to 6V
< 20ns --------------------------------------------------------------------------------------------------------------- (GND − 5V) to 7.5V
UGATE to PHASE
DC --------------------------------------------------------------------------------------------------------------------- (GND − 0.3V) to 6V
< 20ns --------------------------------------------------------------------------------------------------------------- (GND − 5V) to 7.5V
Other Pins ----------------------------------------------------------------------------------------------------------- −0.3V to (VCC + 0.3V)
Power Dissipation, PD @ TA = 25°C
WQFN-32L 4x4 ---------------------------------------------------------------------------------------------------- 3.59W
Package Thermal Resistance (Note 2)
WQFN-32L 4x4, θJA ----------------------------------------------------------------------------------------------- 27.8°C/W
WQFN-32L 4x4, θJC ---------------------------------------------------------------------------------------------- 7°C/W
Junction Temperature --------------------------------------------------------------------------------------------- 150°C
Lead Temperature (Soldering, 10 sec.) ----------------------------------------------------------------------- 260°C
Storage Temperature Range ------------------------------------------------------------------------------------ −65°C to 150°C
ESD Susceptibility (Note 3)
HBM (Human Body Model) -------------------------------------------------------------------------------------- 2kV
Recommended Operating Conditions



(Note 4)
Supply Voltage, PVCC ------------------------------------------------------------------------------------------- 4.5V to 5.5V
Junction Temperature Range ------------------------------------------------------------------------------------ −40°C to 125°C
Ambient Temperature Range ------------------------------------------------------------------------------------ −40°C to 85°C
Electrical Characteristics
(VCC = 5V, TA = 25°C, unless otherwise specified)
Parameter
Symbol
Test Conditions
Min
Typ
Max
Unit
4.5
5
5.5
V
Supply Input
Supply Voltage
VCC
Supply Current
IVCC
VEN = H, No switching
--
3.6
--
mA
Supply Current at PS3
IVCC_PS3
VEN = H, No switching
--
1.2
--
mA
Supply Current at PS4
IVCC_PS4
VEN = H, No switching
--
--
200
A
Power Supply Voltage
PVCC
4.5
--
5.5
V
Power Supply Current
IPVCC
No Switching
--
80
--
A
Shutdown Current
ISHDN
VEN = 0V
--
--
5
A
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is a registered trademark of Richtek Technology Corporation.
DS8171C-02
September 2015
RT8171C
Parameter
Symbol
Test Conditions
Min
Typ
Max
Unit
VDAC = 0.8V 1.52V
0.5
0
0.5
% of
VID
VDAC = 0.5V 0.795V
8
0
8
VDAC = 0.25V 0.495V
10
0
10
Reference and DAC
DAC Accuracy
VFB
mV
PVCC Power On Reset (POR)
POR Threshold
POR Hysteresis
VPOR_r
PVCC Rising
--
4.2
4.5
VPOR_f
PVCC Falling
3.4
3.84
--
--
360
--
SetVID Slow
2.5
3.3
3.6
SetVID Fast
12.5
13.2
14.4
VPOR_HYS
V
mV
Slew Rate
Dynamic VID Slew
Rate
SR
mV/s
EA Amplifier
DC Gain
Gain-Bandwidth
Product
ADC
RL = 47k
70
--
--
dB
GBW
CLOAD = 5pF
--
5
--
MHz
Slew Rate
SREA
CLOAD = 10pF (Gain = 4, RF = 47k,
VOUT = 0.5V to 3V)
5
--
--
V/s
0.5
--
3.6
V
Output Voltage Range
VCOMP
Maximum Source/Sink
IOUTEA
Current
Load-Line Current Gain Amplifier
RL = 47k
VCOMP = 2V
--
5
--
mA
Input Offset Voltage
VILOFS
VIMON = 1V
5
--
5
mV
Current Gain
AILGAIN
VIMON VVREF = 1V,
VFB = VCOMP = 1V
--
1/3
--
A/A
Current Sensing Amplifier
Input Offset Voltage
VOSCS
0.8
--
0.8
mV
Impedance at Positive
Input
RISENP
1
--
--
M
Current Mirror Gain
AMIRROR
IIMON / ISENN
0.97
1
1.03
A/A
TONSET Pin Voltage
VTON
IRTON = 20 A, VDAC = 1V,
3
SET3 = fSW > 500kHz
--
1
--
V
On-Time Setting
TON
IRTON = 20 A, VDAC = 1V,
3
SET3 = fSW > 500kHz
256
285
314
ns
Input Current Range
IRTON
VDAC = 1V, SET3 = fSW > 500kHz
2
--
24
A
Minimum Off-time
TOFF
IRTON = 20 A, VDAC = 1V,
3
SET3 = fSW > 500kHz
--
150
--
ns
TON Setting
Copyright © 2015 Richtek Technology Corporation. All rights reserved.
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September 2015
is a registered trademark of Richtek Technology Corporation.
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15
RT8171C
Parameter
Symbol
Test Conditions
Min
Typ
Max
Unit
1.95
2
2.05
V
4.1
4.3
4.45
V
--
200
--
mV
VID higher than 1.2V
VID
+ 300
VID
+ 350
VID
+ 400
mV
VID lower than 1.2V
1500
1550
1600
Respect to VID voltage
400
350
300
mV
mV
IBIAS
IBIAS Pin Voltage
VIBIAS
RIBIAS = 100k
Protections
Under Voltage Lockout
Threshold
VUVLO
VUVLO
Falling edge hysteresis
Over Voltage Protection
Threshold
VOV
Under Voltage Protection
Threshold
VUV
Negative Voltage Protection
Threshold
VNV
100
50
--
Logic-High
VIH
0.7
--
--
Logic-Low
VIL
--
--
0.3
1
--
1
A
EN and VR_READY
EN Input
Voltage
Leakage Current of EN
V
VR_READY Delay
TVR_READY VSEN = VBoot to VR_READY High
3
5
6
s
VR_READY Pull Low
Voltage
VPGOOD
IVR_READY = 10mA
--
--
0.13
V
VIH
Respect to INTEL Spec. with
50mV hysteresis
0.65
--
--
--
--
0.45
1
--
1
A
--
--
0.13
V
0.55
0.6
0.65
V
VBOOT Voltage set to 1V
0.995
1
1.005
V
VIMON VIMON_INI = 0.4V
--
255
--
VIMON VIMON_INI = 0.2V
--
128
--
VIMON VIMON_INI = 0V
--
0
--
--
400
--
s
Serial VID and VR_HOT
VCLK, VDIO
Leakage Current of VCLK,
VDIO, ALERT and VR_HOT
VIL
ILEAK_IN
V
IVDIO = 10mA
VDIO, ALERT and VR_HOT
Pull Low Voltage
IALERT = 10mA
IVR_HOT = 10mA
VREF and VBOOT
VREF Voltage
VREF
VBOOT Voltage
VBOOT
ADC
Digital IMON Set
VIMON
Decimal
Update Period of IMON
TIMON
TSEN Threshold for
Tmp_Zone [7] transition
VTSEN
100C
--
1.887
--
V
TSEN Threshold for
Tmp_Zone [6] transition
VTSEN
97C
--
1.837
--
V
TSEN Threshold for
Tmp_Zone [5] transition
VTSEN
94C
--
1.784
--
V
Copyright © 2015 Richtek Technology Corporation. All rights reserved.
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is a registered trademark of Richtek Technology Corporation.
DS8171C-02
September 2015
RT8171C
Parameter
Symbol
Test Conditions
Min
Typ
Max
Unit
TSEN Threshold for
Tmp_Zone [4] transition
VTSEN
91C
--
1.729
--
V
TSEN Threshold for
Tmp_Zone [3] transition
VTSEN
88C
--
1.672
--
V
TSEN Threshold for
Tmp_Zone [2] transition
VTSEN
85C
--
1.612
--
V
TSEN Threshold for
Tmp_Zone [1] transition
VTSEN
82C
--
1.551
--
V
TSEN Threshold for
Tmp_Zone [0] transition
VTSEN
75C
--
1.402
--
V
Update Period of TSEN
tTSEN
--
50
--
s
CICCMAX1
VICCMAX = 0.7V
58
64
70
CICCMAX2
VICCMAX = 0.8V
122
128
134
CICCMAX3
VICCMAX = 1V
248
256
260
UGATE Rise Time
tUGATEr
3nF load
--
8
--
UGATE Fall Time
tUGATEf
3nF load
--
8
--
ns
LGATE Rise Time
tLGATEr
3nF load
--
8
--
ns
LGATE Fall Time
UGATE Turn-Off
Propagation Delay
LGATE Turn-Off
Propagation Delay
UGATE Turn-On
Propagation Delay
LGATE Turn-On
Propagation Delay
UGATE/LGATE Tri-State
Propagation Delay
Output
UGATE Driver Source
Resistance
UGATE Driver Source
Current
UGATE Driver Sink
Resistance
UGATE Driver Sink Current
LGATE Driver Source
Resistance
LGATE Driver Source
Current
LGATE Driver Sink
Resistance
LGATE Driver Sink Current
tLGATEf
3nF load
--
4
--
ns
tPDLU
Outputs Unloaded
--
35
--
ns
tPDLL
Outputs Unloaded
--
35
--
ns
tPDHU
Outputs Unloaded
--
20
--
ns
tPDHL
Outputs Unloaded
--
20
--
ns
tPTS
Outputs Unloaded
--
35
--
ns
RUGATEsr
100mA Source Current
--
1
--

IUGATEsr
VUGATE VPHASE = 2.5V
--
2
--
A
RUGATEsk
100mA Sink Current
--
1
--

IUGATEsk
VUGATE  VPHASE = 2.5V
--
2
--
A
RLGATEsr
100mA Source Current
--
1
--

ILGATEsr
VLGATE = 2.5V
--
2
--
A
RLGATEsk
100mA Sink Current
--
0.5
--

ILGATEsk
VLGATE = 2.5V
--
4
--
A
Digital Code of ICCMAX
Decimal
Switching Time
Copyright © 2015 Richtek Technology Corporation. All rights reserved.
DS8171C-02
September 2015
ns
is a registered trademark of Richtek Technology Corporation.
www.richtek.com
17
RT8171C
Note 1. Stresses beyond those listed “Absolute Maximum Ratings” may cause permanent damage to the device. These are
stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated in
the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions may
affect device reliability.
Note 2. θJA is measured at TA = 25°C on a high effective thermal conductivity four-layer test board per JEDEC 51-7. θJC is
measured at the exposed pad of the package.
Note 3. Devices are ESD sensitive. Handling precaution is recommended.
Note 4. The device is not guaranteed to function outside its operating conditions.
Copyright © 2015 Richtek Technology Corporation. All rights reserved.
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is a registered trademark of Richtek Technology Corporation.
DS8171C-02
September 2015
DS8171C-02
September 2015
R3 39.63k
RNTC1
100k
ß = 4485
Copyright © 2015 Richtek Technology Corporation. All rights reserved.
VIN
R13
6.2k
To CPU
R12
5.6k
R9 10k
R7 81.75k
R5 16.0634k
R11
100k
VCC
R19
75
R14
1
R10
10k
R4
13.92k
C1
2.2µF
R22
130
SETGND
TSEN
13
15
12
17
10
VDIO
VCLK
VR_HOT
VR_READY
IBIAS
GND
16 TONSET
30
11
29 VBOOTSEL
7 SET1
8 SET2
21
PGND
IMON
VREF
R32
68k
C11
47pF
R25
0
19
C9
R28
5.44k
47k
ß = 4050
C14
Optional
C13
Optional
R29
475
R30
475
C10
0.47µF
C4
0.47µF
VSS_SENSE
VCC_SENSE
VCC_SENSE
R17
R16
8.83k
R33
10k
C6
22µF
L1
Optional 330nH / 2.95m
R31 680
Q2
Q1
VIN
5V
C12
390pF
C5
R24 0.1µF
2.2
C2
2.2µF
R2
2.2
R18
31 6.63k RNTC2
1
RGND 5
FB 3
COMP 2
ISENP 28
27
ISENN
4
VSEN
LGATE 20
PHASE 23
25
BOOT 22
PVCC
UGATE
RT8171C
14
ALERT
26 EN
18, 24 DRV_EN
R23
150
R34
100k
VCC
9 SET3
6
33 (Exposed Pad)
R6
1.15k
VCC
Enable
R20 R21
10k 130
VCCIO
C3
0.1µF
R15
604k
R8
24.0698k
5V
R1
20
0.1µF
x3
270μF/6m
C7
C8
22µFx6
R26
100
VCC_SENSE
LOAD
VCORE_OUT
R27
100
VSS_SENSE
RT8171C
Typical Application Circuit
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19
RT8171C
Typical Operating Characteristics
CORE VR Power Off from EN
CORE VR Power On from EN
V CORE
(500mV/Div)
V CORE
(500mV/Div)
EN
(900mV/Div)
EN
(900mV/Div)
VR_READY
(800mV/Div)
UGATE
(20V/Div)
VR_READY
(800mV/Div)
UGATE
(20V/Div)
VIN = 7.4V, No Load, Boot VID 0.9V
Time (200μs/Div)
Time (200μs/Div)
CORE VR OCP
CORE VR OVP
V CORE
(1V/Div)
V CORE
(700mV/Div)
VR_READY
(2V/Div)
UGATE
(20V/Div)
I LOAD
(30A/Div)
VR_READY
(800mV/Div)
UGATE
(20V/Div)
VIN = 7.4V, Boot VID 0.9V
LGATE
(8V/Div)
VIN = 7.4V, Boot VID 0.9V, PS2
Time (200μs/Div)
Time (100μs/Div)
CORE VR Dynamic VID Up
CORE VR Dynamic VID Down
V CORE
V CORE
VCLK
(1V/Div)
V CORE
(300mV/Div)
V CORE
(300mV/Div)
VDIO
(1V/Div)
VDIO
(1V/Div)
ALERT
(1V/Div)
VIN = 7.4V, No Load, Boot VID 0.9V
VCLK
(1V/Div)
VIN = 7.4V, VID = 0.7V to 1.15V, Slew Rate = Slow
Time (20μs/Div)
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20
ALERT
(1V/Div)
VIN = 7.4V, VID = 1.15V to 0.7V, Slew Rate = Slow
Time (20μs/Div)
is a registered trademark of Richtek Technology Corporation.
DS8171C-02
September 2015
RT8171C
CORE VR Dynamic VID Down
CORE VR Dynamic VID Up
V CORE
V CORE
VCLK
(1V/Div)
V CORE
(300mV/Div)
V CORE
(500mV/Div)
VDIO
(1V/Div)
VDIO
(1V/Div)
ALERT
(2V/Div)
VCLK
(1V/Div)
VIN = 7.4V, VID = 0.7V to 1.15V, Slew Rate = Fast
ALERT
(2V/Div)
VIN = 7.4V, VID = 1.15V to 0.7V, Slew Rate = Fast
Time (10μs/Div)
Time (10μs/Div)
CORE VR Mode Transient
CORE VR Mode Transient
V CORE
(10mV/Div)
V CORE
(10mV/Div)
VCLK
(1V/Div)
VCLK
(1V/Div)
UGATE
(20V/Div)
UGATE
(20V/Div)
LGATE
(8V/Div)
LGATE
(8V/Div)
VIN = 7.4V, VID = 0.7V, PS0 to PS2, ILOAD = 1A
VIN = 7.4V, VID = 0.7V, PS2 to PS0, ILOAD = 1A
Time (50μs/Div)
Time (50μs/Div)
VVIMON
Current
vs. Load Current
IMON vs.
CORE VR Thermal Monitoring
1.2
1.0
0.8
VIMON (V)
TSEN
(1V/Div)
0.6
0.4
VR_HOT
(500mV/Div)
0.2
VIN = 12V, TSEN Sweep from 1.7V to 2.1V
Time (10ms/Div)
0.0
0
1
2
3
4
5
6
7
8
9
10 11 12 13
Load Current (A)
Copyright © 2015 Richtek Technology Corporation. All rights reserved.
DS8171C-02
September 2015
is a registered trademark of Richtek Technology Corporation.
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21
RT8171C
Applications Information
The RT8171C is a single phase synchronous Buck
controller designed to meet Intel VR12.1 compatible CPU
specification with a serial SVID control interface. The
controller uses an ADC to implement all kinds of settings
to save a total number of pins for easily using and
increasing PCB space utilization.
G-NAVPTM Control Mode
The RT8171C adopts the G-NAVPTM controller, which is a
current mode constant on-time control with DC offset
cancellation. The approach can not only improve DC offset
problem for increasing system accuracy but also provide
fast transient response. For the RT8171C, when current
feedback signal reaches comp signal to generate an ontime width to achieve PWM modulation. Figure 1 shows
the basic G-NAVPTM behavior waveforms in Continuous
Conduct Mode (CCM).
Current feedback signal
Comp signal
PWM1
Diode Emulation Mode (DEM)
As well-known, the dominate power loss is switching
related loss during light load, hence VR needs to be
operated in asynchronous mode (or called discontinuous
conduct mode, DCM) to reduce switching related loss
since switching frequency is dependent on loading in the
asynchronous mode. RT8171C can operate in Diode
Emulation Mode (DEM) in order to improve light load
efficiency. In DEM operation, the behavior of the low-side
MOSFET needs to work like a diode, that is, the low-side
MOSFET will be turned on when the DCR network voltage
is higher than the ZCD_TH, i.e. the inductor current follows
from source to drain of low-side MOSFET. The low-side
MOSFET will be turned off when DCR network is lower
than the ZCD_TH, i.e. reversed current is not allowed.
The positive voltage threshold (ZCD threshold) of low-side
MOSFET turn off is set by the SET3 pin in Table 9. Figure
2 shows the control behavior in DEM. Figure 3 shows the
G-NAVPTM operation in DEM to illustrate the control
behaviors. When the load decreases, the discharge time
of output capacitors increases during UGATE and LGATE
are turned off. Hence, the switching frequency and
switching losses will be reduced to improve efficiency in
light load condition.
PWM2
Inductor current
PWM3
TM
Figure 1 (a). G-NAVP Behavior Waveforms in CCM in
Steady State
Phase node
Current feedback signal
UGATE
Comp signal
LGATE
PWM1
Figure 2. Diode Emulation Mode (DEM) in Steady State
PWM2
PWM3
Figure 1 (b). G-NAVPTM Behavior Waveforms in CCM in
Load Transient
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is a registered trademark of Richtek Technology Corporation.
DS8171C-02
September 2015
RT8171C
Inductor
current signal
Output capacitor
discharge slope
COMP signal
UGATE
LGATE
(a) Lighter Load Condition in DEM.
Capacitor discharge slope is lower than Figure 3 (b).
Inductor
current signal
Output capacitor
discharge slope
COMP signal
UGATE
LGATE
(b) Load Increased Condition in DEM.
Capacitor discharge slope is Higher than Figure 3 (a).
Figure 3. G-NAVPTM Operation in DEM.
Switching Frequency (TON) Setting
RT8171C is one kind of constant on-time control. The
patented CCRCOT (Constant Current Ripple COT)
technology can generate an adaptive on-time with input
voltage and VID code to obtain a constant current ripple.
So that the output voltage ripple can be controlled nearly
like a constant as different input and output voltage change.
Connect a resistor RTON between input voltage terminal
and TONSET pin to set the on-time width.
In order to meet Intel VR12.1 quiescent power specification
at PS3 and PS4, RT8171C provides two different
coefficients for TON. And these coefficients can be setting
by SET3 pin, as shown in Tablet 9. So, RT8171C can
pass quiescent power for all range switching frequency at
PS3 and PS4 under battery mode condition.
For SET3 pin fSW ≤ 500kHz,
TON
R
 C  0.22
= TON
VIN  VDAC
TON =
 VDAC
RTON  C  VDAC / 5.45
VIN  1.2
< 1.2V 
 VDAC  1.2V 
Copyright © 2015 Richtek Technology Corporation. All rights reserved.
DS8171C-02
September 2015
For SET3 pin fSW > 500kHz
R
 C  0.11
TON = TON
 VDAC < 1.2V 
VIN  VDAC
TON =
RTON  C  VDAC / 10.9
VIN  1.2
 VDAC  1.2V 
Where C = 18.2pF. By using the relationship between
TON and fSW, the switching frequency fSW is :

1
fSW(MAX) = 
T
ON(MAX)

  VDAC(MAX) 
   VIN(MAX) 
 

Where
fSW(MAX) is the maximum switching frequency.
VDAC(MAX) is the maximum VDAC of application.
VIN(MAX) is the maximum application input voltage.
TON(MAX) is the on-time width.
When load increases, on-time keeps constant. The
off-time width will be reduced so that loading can load
more power from input terminal to regulate output voltage.
Hence, the loading current increases in case the switching
frequency also increases. Higher switching frequency
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RT8171C
operation can reduce power component's size and PCB
space, trading off the whole efficiency since switching
related loss increases, vice versa.
Please note that the actual switching frequency is also
dependent on the losses in the main power stage and the
driver characteristic. So, in order to get more accuracy
switching frequency the form of the switching frequency
can be rewrote as below :
fSW(MAX) 
VDAC(MAX)  ICC(MAX)  (DCR  RONLS  RLL )
VIN(MAX)  ICC(MAX)  (RONLS  RONHS )  (TON  TD  TON,VAR )  ICC(MAX)  RONLS  TD
Where fSW(MAX) is the maximum switching frequency,
VDAC(MAX) is the maximum application VID, VIN(MAX) is the
maximum input voltage, ICC(MAX) is the maximum load
current, DCR is the inductor DC resistance, RON-HS is the
equivalent high-side RDS(ON), RON-LS is the equivalent lowside RDS(ON), TD is the driver dead time , RLL is the loadline
value, TON,VAR is the TON variation value.
Above method can keep the constant current ripple,
whether VIN and VID are variation. But this method will
generate large power consumption on TONSET pin. In
order to reduce the power consumption on TONSET pin,
here can connect a resister RTON between VCC and
TONSET pin to set the on-time width.
When inductance and DCRx time constant is equal to RXCX
filter network time constant, a voltage ILX x DCRx will drop
on CX to generate inductor current signal. According to
the Figure 4, the ISENN is as follows :
I  DCR x
ISENN = Lx
RCSx
Where LX / DCRx = RXCX is held. The method can get high
efficiency performance, but DCRx value will be drifted by
temperature, a NTC resistor should add in the resistor
network in the IMON pin to achieve DCR x thermal
compensation.
It's noted that, in order to avoid current amplifier being
saturated. When (ILx x DCRx) is larger than 140mV, the
current sense method should be adopted method II as
illustrated in Figure 5. According to Figure 5, the RX is as
follows :
Rx = Rx1 // RX2
The resistance accuracy of RCSx is recommended to be
1% or higher. And in order to get impedance matching,
the RCSx must be placed 680Ω resistor.
The on-time width equation can be rewritten as below.
For SET3 pin fSW ≤ 500kHz,
RTON  C  0.22
 VDAC  1.2V 
VCC  VDAC
R
 C  VDAC / 5.45
 TON
 VDAC  1.2V 
VCC  1.2
ISENN
+
-
TON 
TON
Lx
DCRx
Rx
Cx
ISENP
ISENN
RCSx
Figure 4. Lossless Current Sense Method I
For SET3 pin fSW > 500kHz,
RTON  C  0.11
 VDAC  1.2V 
VCC  VDAC
R
 C  VDAC / 10.9
 TON
 VDAC  1.2V 
VCC  1.2
ILx
TON 
TON
This method can saving power dissipation on TONSET
pin but it will loss the constant current ripple merit. So,
this method can be used under VIN is fixed application.
Current Sense
In the RT8171C, the current signal is used for load-line
setting and OC (Over Current) protection. The inductor
current sense method adopts the lossless current sensing
for allowing high efficiency as illustrated in the Figure 4.
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24
VCORE
ILx
ISENN
+
-
VCORE
Lx
DCRx
Rx1
Cx
ISENP
ISENN
RCSx
Rx2
Figure 5. Lossless Current Sense Method II
Thermal Compensation for Current Sense
Thermal Compensation for Current Sense is a patented
topology, unlike conventional current sense method
requiring a NTC resistor in per phase current loop for
is a registered trademark of Richtek Technology Corporation.
DS8171C-02
September 2015
RT8171C
thermal compensation. That is to say, this current sense
of thermal compensation method can be applied to multiphase condition and it only needs one NTC resistor. So,
the NTC resistor cost can be saved by using the method.
Figure 6 and Figure 7 show the current sense method
which connecting the resistor network between the IMON
and VREF pins to set a part of current loop gain for loadline (droop) setting and set accurate over current
protection.
The method I current sense network equation is as follows :
DCR x
 REQ  ILx
RCSx
The G-NAVPTM topology can set load-line (droop) via the
current loop and the voltage loop, the load-line is a slope
between load current ICC and output voltage VCORE as
shown in Figure 8. Figure 9 shows the voltage control and
current loop. By using both loops, the load-line (droop)
can easily be set. The load-line set equation is :
1 DCR x

 REQ
3 RCSx
AI
RLL =
=
(m )
R2
AV
R1
The load-line can be set to zero by SET3 pin.
VCORE
The method II current sense network equation is as follows :
VIMON  VREF =
DCR x
R x2
 REQ  ILx 
RCSx
R x1 + R x2
Load-line slope = -RLL
REQ includes a NTC resistor to compensate DCRx thermal
drifting for high accuracy load-line (droop).
ILx
IMON
VIMON
RNTC
ISENN
REQ
+
-
VCORE
Lx
DCRx
Rx
Cx
ISENP
ISENN
RLL x ICC
ICC
Figure 8. Load-Line (Droop)
VCORE
R2
Voltage Loop
RCSx
TON Generator
R1
ILx
DCRx
Cx
-
VID
ISENP
+
Figure 6. Total Current Sense Method I Network
RCS
+
+
Lx
Rx
VREF
-
ISENN
-
1/3
+
-
VIMON  VREF =
Load-Line (Droop) Setting
RNTC
ISENN
IMON
VREF
REQ
Figure 9. Voltage Loop and Current Loop
ILx
IMON
VIMON
RNTC
ISENN
REQ
+
-
VCORE
Lx
DCRx
Rx1
Cx1
ISENP
ISENN
RCSx
Rx2
VREF
Figure 7. Total Current Sense Method II Network
Copyright © 2015 Richtek Technology Corporation. All rights reserved.
DS8171C-02
September 2015
Compensator Design
The compensator of RT8171C doesn't need a complex
type II or type III compensator to optimize control loop
performance. It can adopt a simple type I compensator
(one pole, one zero) in G-NAVPTM topology to achieve
constant output impedance design for Intel VR12.1 ACLL
specification. The one pole one zero compensator is
shown as Figure 10, the transfer function of compensator
should be designed as the following transfer function to
achieve constant output impedance, i.e. Zo(s) = load-line
slope in the entire frequency range :
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25
RT8171C
s
  fSW
AI
(s) 

s
RLL
1+
Function 2 Function 1
<5:0>
<5:0>
1+
GCON
ADC
ESR
Where AI is current loop gain, RLL is load-line, fSW is
switching frequency and ωESR is a pole that should be
located at 1 / (COUT x ESR). Then, the C1 and C2 should
be designed as follows :
C1 =
COUT  ESR
R2
It is noted that, the values of C1 and C2 may fine tune for
better experimental performance.
C2 =
Function 2
Register
Function 2 Function 1
<5:0>
<5:0>
For reducing total pin number of package, the SET[1:3]
pins adopt the multi-function pin setting mechanism in
RT8171C. Figure 11 illustrates this operating mechanism.
First, external voltage divider is to set the Function 1 and
then internal current source 80μA is to set the Function
2. The setting voltage of Function 1 and Function 2 can
be represented as follows :
R2
VFunction 1 =
 VCC
R1 + R2
R1 R2
VFunction 2 = 80 A 
R1 + R2
All function setting will be done within 500μs after power
ready (POR).
If VFunction 1 and VFunction 2 are determined, R1 and R2 can
be calculated as follows :
V V
R1 = CC Function 2
80 A  VFunction 1
R2 =
R1 VFunction1
VCC  VFunction1
VCC
R1
SET[1:3]
Function 2
Register
+
Multi-Function Pin Setting Mechanism
80µA
Function 1
Register
-
VID
R2
SetGND
ADC
R2
Figure 10. Type I Compensator
R1
SET[1:3]
C2
R1
VCC
Function 1
Register
1
R1   fSW
C1
80µA
R2
SetGND
Figure 11. Multi-Function Pin Setting Mechanism
Connecting a R3 resistor from the SET[1:3] pin to the
middle node of voltage divider can help to fine tune the set
voltage of Function 2, which does not affect the set voltage
of Function 1. The Figure 12 shows the setting method
and the set voltage of Function 1 and Function 2 can be
represented as :
R2
VFunction 1 =
 VCC
R1 + R2
R1 R2 

VFunction 2 = 80 A   R3 +

R1 + R2 

Function 2 Function 1
<5:0>
<5:0>
80µA
ADC
VCC
Function 1
Register
R1
SET[1:3]
Function 2
Register
R3
R2
SetGND
In addition, Richtek provides a Microsoft Excel-based
spreadsheet to help design the SETx resistor network for
RT8171C.
Copyright © 2015 Richtek Technology Corporation. All rights reserved.
www.richtek.com
26
is a registered trademark of Richtek Technology Corporation.
DS8171C-02
September 2015
RT8171C
Function 2 Function 1
<5:0>
<5:0>
80µA
ADC
VCC
Function 1
Register
R1
SET[1:3]
R3
R2
Function 2
Register
SetGND
Figure 12. Multi-Function Pin Setting Mechanism with a
R3 resistor to fine tune the set voltage of function 2
Quick Response (QR) Mechanism
When the transient load step-up becomes quite large, it
is difficult for loop response to meet the energy transfer.
Hence, that output voltage generate undershoot to fail
specification. The RT8171C has Quick Response (QR)
mechanism being able to help improve this issue. It adopts
a nonlinear control mechanism which can enlarge the on
time of PWM signal at instantaneous step-up transient
load to restrain the output voltage drooping, Figure 13
shows the QR behavior.
QR Width
VCORE
The output voltage signal behavior needs to be detected
so that QR mechanism can be trigged. The output voltage
signal is via a remote sense line to connect at VSEN pin
that is shown in Figure 14. The QR mechanism needs to
set QR width and QR threshold. Both definitions are shown
in Figure 13. A proper QR mechanism set can meet different
applications. The SET2 pin is a multi-function pin which
can set QR threshold, QR width and ICCMAX.
QR Threshold
Current Mirror
QR trigger
IMirror
VID
VCC_SENSE
+
-
RQR VSEN
Figure 14. Simplified QR Trigger Schematic
An internal current source 80μA is used in multi-function
pin setting mechanism. For example, 25mV QR threshold
and 1.3 x TON QR width are set according to the Table 4,
the set voltage should be between 0.6506V and 0.6725V.
Please note that a high accuracy resistor is needed for
this setting accuracy, <1% error tolerance is
recommended.
In the Table 4, there are some “No Use” marks at QR
Width section. It means that user should not use it to
avoid the possibility of shift digital code due to tolerance
concern.
PWM
Load
Figure 13. Quick Response Mechanism
Copyright © 2015 Richtek Technology Corporation. All rights reserved.
DS8171C-02
September 2015
is a registered trademark of Richtek Technology Corporation.
www.richtek.com
27
RT8171C
Table 4. SET2 Pin Setting for QR Threshold and QR Width
VQR_SET = 80  A 
R1 R2
R1 R2
QR_TH
<2:0>
QR
Threshold
QR Width
(%TON)
0.000
10.948
21.896
mV
QRWIDTH
<2:0>
000
25.024
50.049
75.073
35.973
60.997
86.022
46.921
71.945
96.970
mV
mV
mV
001
010
011
100.098
125.122
150.147
175.171
111.046
136.070
161.095
186.119
121.994
147.019
172.043
197.067
mV
mV
mV
mV
200.196
225.220
250.244
211.144
236.168
261.193
222.092
247.116
272.141
mV
mV
mV
275.269
300.293
325.318
350.342
286.217
311.241
336.266
361.290
297.165
322.190
347.214
372.239
mV
mV
mV
mV
375.367
400.391
425.415
450.440
386.315
411.339
436.364
461.388
397.263
422.287
447.312
472.336
mV
mV
mV
mV
475.464
500.489
525.513
486.413
511.437
536.461
497.361
522.385
547.410
mV
mV
mV
550.538
575.562
600.587
625.611
561.486
586.510
611.535
636.559
572.434
597.458
622.483
647.507
mV
mV
mV
mV
110
111
000
001
44%
No Use
No Use
155%
650.635
675.660
700.684
725.709
661.584
686.608
711.632
736.657
672.532
697.556
722.581
747.605
mV
mV
mV
mV
010
011
100
101
133%
111%
89%
67%
750.733
775.758
800.782
761.681
786.706
811.730
772.630
797.654
822.678
mV
mV
mV
110
111
000
44%
No Use
No Use
825.806
850.831
875.855
900.880
836.755
861.779
886.804
911.828
847.703
872.727
897.752
922.776
mV
mV
mV
mV
001
010
011
100
155%
133%
111%
89%
925.904
950.929
975.953
936.852
961.877
986.901
947.801
972.825
997.849
mV
mV
mV
Min
Typical
Max
unit
Copyright © 2015 Richtek Technology Corporation. All rights reserved.
www.richtek.com
28
000
100
101
110
111
No Use
Disable
000
001
010
001
011
100
101
110
011
100
011
100
101
89%
67%
44%
No Use
No Use
155%
133%
15mV
111
000
001
010
010
155%
133%
111%
111%
89%
67%
44%
No Use
No Use
155%
133%
20mV
25mV
30mV
101
110
111
111%
89%
67%
67%
44%
No Use
is a registered trademark of Richtek Technology Corporation.
DS8171C-02
September 2015
RT8171C
VQR_SET = 80  A 
R1 R2
R1  R2
Min
Typical
Max
unit
1000.978
1011.926
1022.874
mV
QRWIDTH
<2:0>
000
1026.002
1051.026
1076.051
1036.950
1061.975
1086.999
1047.898
1072.923
1097.947
mV
mV
mV
001
010
011
1101.075
1126.100
1151.124
1176.149
1112.023
1137.048
1162.072
1187.097
1122.972
1147.996
1173.021
1198.045
mV
mV
mV
mV
1201.173
1226.197
1251.222
1212.121
1237.146
1262.170
1223.069
1248.094
1273.118
mV
mV
mV
1276.246
1301.271
1326.295
1351.320
1287.195
1312.219
1337.243
1362.268
1298.143
1323.167
1348.192
1373.216
mV
mV
mV
mV
1376.344
1401.369
1426.393
1451.417
1387.292
1412.317
1437.341
1462.366
1398.240
1423.265
1448.289
1473.314
mV
mV
mV
mV
1476.442
1501.466
1526.491
1487.390
1512.414
1537.439
1498.338
1523.363
1548.387
mV
mV
mV
1551.515
1576.540
1562.463
1587.488
1573.412
1598.436
mV
mV
Dynamic VID (DVID) Compensation
When VID transition event occurs, a charge current will
be generated in the loop to cause that DVID performance
is deteriorated by this induced charge current, the
phenomenon is called droop effect. The droop effect is
shown in Figure 15. When VID up transition occurs, the
output capacitor will be charged by inductor current. Since
current signal is sensed in inductor, an induced charge
current will appear in control loop. The induced charge
current will produce a voltage drop in R1 to cause output
voltage to have a droop effect. Due to this, VID transition
performance will be deteriorated.
Copyright © 2015 Richtek Technology Corporation. All rights reserved.
DS8171C-02
September 2015
QR_TH
<2:0>
101
100
101
110
111
QR
Threshold
No Use
35mV
000
001
010
110
011
100
101
110
011
100
101
110
111
155%
133%
111%
89%
67%
44%
No Use
No Use
155%
133%
40mV
111
000
001
010
111
QR Width
(%TON)
111%
89%
67%
44%
No Use
No Use
155%
133%
45mV
111%
89%
67%
44%
No Use
The RT8171C provides a DVID compensation function. A
virtual charge current signal can be established by the
SET1 pin to cancel the real induced charge current signal
and the virtual charge current signal is defined in Figure
17. Figure 16 shows the operation of canceling droop
effect. A virtual charge current signal is established first
and then VID signal plus virtual charge current signal is
generated in FB pin. Hence, an induced charge current
signal flows to R1 and is cancelled to reduce droop effect.
As mention before, the charge current will be generated
when VID transition event occurs. This charge current will
not only deteriorated DVID performance but also may
damage power switches. Due to this, user should consider
the power rating current of power switches when choosing
the power switches.
is a registered trademark of Richtek Technology Corporation.
www.richtek.com
29
RT8171C
Charge current
L
VIN
Q1
CO1
Q2
Gate
Driver
CO2
RESR
CPU
Ai
Induced charge
current signal
C2
C1
R2
CCRCOT
COMP -
VIN
VID
Output voltage
R1
EA
+
+
tON
IDROOP
VID
VID Transition
Table 5 and Table 6 show the DVID_Threshold and
DVID_Width settings in SET1 pin, respectively. For
example, 25mV DVID_Threshold and 72μs DVID_Width
are designed (OCP sets as 110% ICCMAX, and RSET
sets as 100% Ramp current). The DVID_Threshold is set
by an external voltage divider to set and the DVID_Width
is set by an internal current source 80μA by the multifunction pin setting mechanism. According to the Table 5
and Table 6, the DVID_Threshold set voltage should be
between 1.226V and 1.248V and the DVID_Width set
voltage should be between 0.125V and 0.147V. Please
note that a high accuracy resistor is needed for this setting,
<1% error tolerance is recommended.
Figure 15. Droop Effect in VID Transition
Charge current
VIN
L
Q1
Gate
Driver
CO1
Q2
CO2
RESR
Ai
Induced charge
current signal
Output voltage
CPU
C2
R2
C1
CCRCOT
COMP -
VIN
VID
+
tON
IDROOP
EA
+
R1
Virtual Charge Current
+
DVID Event
Slew Rate
Control
VID
Virtual Charge
Current
Generator
VID
Transition
SET1
Figure 16. DVID Compensation
DVID_Width
DVID_Threshold
Figure 17. Definition of Virtual Charge Current Signal
Copyright © 2015 Richtek Technology Corporation. All rights reserved.
www.richtek.com
30
is a registered trademark of Richtek Technology Corporation.
DS8171C-02
September 2015
RT8171C
Min
0.000
Table 5. SET1 Pin Setting for DVID_Threshold
R1 R2
VDVID_Threshold = 80  A 
R1  R2
DVID_Threshold
DVID_TH
OCS
Typical
Max
unit
<2:0>
<2:0>
10.948
21.896
mV
000
No Use
25.024
50.049
75.073
100.098
125.122
150.147
35.973
60.997
86.022
111.046
136.070
161.095
46.921
71.945
96.970
121.994
147.019
172.043
mV
mV
mV
mV
mV
mV
175.171
200.196
225.220
250.244
186.119
211.144
236.168
261.193
197.067
222.092
247.116
272.141
mV
mV
mV
mV
275.269
300.293
325.318
350.342
286.217
311.241
336.266
361.290
297.165
322.190
347.214
372.239
mV
mV
mV
mV
375.367
400.391
425.415
450.440
475.464
500.489
386.315
411.339
436.364
461.388
486.413
511.437
397.263
422.287
447.312
472.336
497.361
522.385
mV
mV
mV
mV
mV
mV
525.513
550.538
575.562
600.587
536.461
561.486
586.510
611.535
547.410
572.434
597.458
622.483
mV
mV
mV
mV
101
110
111
000
147%
156%
No Use
No Use
625.611
650.635
675.660
700.684
636.559
661.584
686.608
711.632
647.507
672.532
697.556
722.581
mV
mV
mV
mV
001
010
011
100
110%
119%
128%
138%
725.709
750.733
775.758
800.782
825.806
850.831
736.657
761.681
786.706
811.730
836.755
861.779
747.605
772.630
797.654
822.678
847.703
872.727
mV
mV
mV
mV
mV
mV
875.855
900.880
925.904
950.929
886.804
911.828
936.852
961.877
897.752
922.776
947.801
972.825
mV
mV
mV
mV
975.953
986.901
997.849
mV
Copyright © 2015 Richtek Technology Corporation. All rights reserved.
DS8171C-02
September 2015
111
001
010
011
100
101
110
OCP = %ICCMAX
85mV
111
000
001
010
110
101
100
011
100
101
110
111
000
001
010
011
100
No Use
No Use
110%
119%
75mV
65mV
55mV
101
110
111
000
001
010
011
011
100
101
110
111
110%
119%
128%
138%
147%
156%
128%
138%
147%
156%
No Use
No Use
110%
119%
128%
138%
147%
156%
No Use
No Use
110%
119%
45mV
128%
138%
147%
156%
No Use
is a registered trademark of Richtek Technology Corporation.
www.richtek.com
31
RT8171C
Min
Typical
Max
1000.978
1011.926
1022.874
R1 R2
R1  R2
DVID_TH
unit
<2:0>
mV
1026.002
1051.026
1076.051
1101.075
1126.100
1151.124
1036.950
1061.975
1086.999
1112.023
1137.048
1162.072
1047.898
1072.923
1097.947
1122.972
1147.996
1173.021
mV
mV
mV
mV
mV
mV
1176.149
1201.173
1226.197
1251.222
1187.097
1212.121
1237.146
1262.170
1198.045
1223.069
1248.094
1273.118
mV
mV
mV
mV
1276.246
1301.271
1326.295
1351.320
1287.195
1312.219
1337.243
1362.268
1298.143
1323.167
1348.192
1373.216
mV
mV
mV
mV
1376.344
1401.369
1426.393
1451.417
1476.442
1501.466
1387.292
1412.317
1437.341
1462.366
1487.390
1512.414
1398.240
1423.265
1448.289
1473.314
1498.338
1523.363
mV
mV
mV
mV
mV
mV
1526.491
1551.515
1576.540
1537.439
1562.463
1587.488
1548.387
1573.412
1598.436
mV
mV
mV
VDVID_Threshold = 80 A 
Copyright © 2015 Richtek Technology Corporation. All rights reserved.
www.richtek.com
32
010
OCS
<2:0>
000
001
010
011
100
101
110
DVID_Threshold OCP = %ICCMAX
No Use
35mV
111
000
001
010
001
000
011
100
101
110
111
000
001
010
011
100
110%
119%
128%
138%
147%
156%
No Use
No Use
110%
119%
25mV
15mV
101
110
111
128%
138%
147%
156%
No Use
No Use
110%
119%
128%
138%
147%
156%
No Use
is a registered trademark of Richtek Technology Corporation.
DS8171C-02
September 2015
RT8171C
Table 6. SET1 Pin Setting for DVID_Width
VDVID_Width =
R2
 5V
R1  R2
Min
Typical
Max
unit
0.000
25.024
50.049
10.948
35.973
60.997
21.896
46.921
71.945
mV
mV
mV
75.073
100.098
125.122
150.147
86.022
111.046
136.070
161.095
96.970
121.994
147.019
172.043
mV
mV
mV
mV
175.171
200.196
225.220
250.244
275.269
186.119
211.144
236.168
261.193
286.217
197.067
222.092
247.116
272.141
297.165
mV
mV
mV
mV
mV
300.293
325.318
350.342
375.367
400.391
311.241
336.266
361.290
386.315
411.339
322.190
347.214
372.239
397.263
422.287
mV
mV
mV
mV
mV
425.415
450.440
475.464
500.489
436.364
461.388
486.413
511.437
447.312
472.336
497.361
522.385
mV
mV
mV
mV
525.513
550.538
575.562
600.587
625.611
536.461
561.486
586.510
611.535
636.559
547.410
572.434
597.458
622.483
647.507
mV
mV
mV
mV
mV
650.635
675.660
700.684
725.709
750.733
661.584
686.608
711.632
736.657
761.681
672.532
697.556
722.581
747.605
772.630
mV
mV
mV
mV
mV
775.758
800.782
825.806
850.831
786.706
811.730
836.755
861.779
797.654
822.678
847.703
872.727
mV
mV
mV
mV
875.855
900.880
925.904
950.929
975.953
886.804
911.828
936.852
961.877
986.901
897.752
922.776
947.801
972.825
997.849
mV
mV
mV
mV
mV
Copyright © 2015 Richtek Technology Corporation. All rights reserved.
DS8171C-02
September 2015
RSET
<3:0>
0000
0001
0010
0011
0100
0101
0110
0111
1000
1001
DVID_WTH
<1:0>
00
01
10
11
00
01
10
11
00
01
10
11
00
01
10
11
00
01
10
11
00
01
10
11
00
01
10
11
00
01
10
11
00
01
10
11
00
01
10
11
RSET % 300kHz
83%
100%
117%
133%
150%
167%
183%
200%
217%
233%
DVID_Width
No Use
72s
96s
No Use
No Use
72s
96s
No Use
No Use
72s
96s
No Use
No Use
72s
96s
No Use
No Use
72s
96s
No Use
No Use
72s
96s
No Use
No Use
72s
96s
No Use
No Use
72s
96s
No Use
No Use
72s
96s
No Use
No Use
72s
96s
No Use
is a registered trademark of Richtek Technology Corporation.
www.richtek.com
33
RT8171C
VDVID_Width =
R2
 5V
R1  R2
Min
Typical
Max
unit
1000.978
1026.002
1011.926
1036.950
1022.874
1047.898
mV
mV
1051.026
1076.051
1101.075
1126.100
1151.124
1061.975
1086.999
1112.023
1137.048
1162.072
1072.923
1097.947
1122.972
1147.996
1173.021
mV
mV
mV
mV
mV
1176.149
1201.173
1226.197
1251.222
1187.097
1212.121
1237.146
1262.170
1198.045
1223.069
1248.094
1273.118
mV
mV
mV
mV
1276.246
1301.271
1326.295
1351.320
1376.344
1287.195
1312.219
1337.243
1362.268
1387.292
1298.143
1323.167
1348.192
1373.216
1398.240
mV
mV
mV
mV
mV
1401.369
1426.393
1451.417
1476.442
1501.466
1412.317
1437.341
1462.366
1487.390
1512.414
1423.265
1448.289
1473.314
1498.338
1523.363
mV
mV
mV
mV
mV
1526.491
1551.515
1576.540
1537.439
1562.463
1587.488
1548.387
1573.412
1598.436
mV
mV
mV
Copyright © 2015 Richtek Technology Corporation. All rights reserved.
www.richtek.com
34
RSET
<3:0>
1010
1011
1100
1101
1110
1111
DVID_WTH
<1:0>
00
01
10
11
00
01
10
11
00
01
10
11
00
01
10
11
00
01
10
11
00
01
10
11
RSET % 300kHz
250%
267%
283%
300%
317%
333%
DVID_Width
No Use
72s
96s
No Use
No Use
72s
96s
No Use
No Use
72s
96s
No Use
No Use
72s
96s
No Use
No Use
72s
96s
No Use
No Use
72s
96s
No Use
is a registered trademark of Richtek Technology Corporation.
DS8171C-02
September 2015
RT8171C
Ramp Compensation
Current Monitor, IMON
G-NAVPTM topology is one type of ripple based control
that has fast transient response, no beat frequency issue
in high repetitive load frequency operation and low BOM
cost. But ripple based control usually has no good noise
immunity. The RT8171C provides a ramp compensation
to increase noise immunity and reduce jitter at the
switching node. Figure 18 shows the ramp compensation.
RT8171C includes a current monitor (IMON) function which
can be used to detect over current protection and the
maximum processor current ICCMAX, and also sets a
part of current gain in the load-line setting. It produces an
analog voltage proportional to output current between the
IMON and VREF pins.
Noise Margin
w/o ramp compensation
IMON-VREF
VCOMP
The calculation of current sense method I for IMON − VREF
voltage is shown as below :
DCR x
VIMON  VREF =
 REQ  ILx
RCSx
Where ILx is output current and the definitions of DCRx,
RCS and REQ can refer to Figure 6.
Maximum Processor Current Setting, ICCMAX
Noise Margin
w/ ramp compensation
IMON-VREF
VCOMP
Figure 18. Ramp Compensation
The maximum processor current ICCMAX can be set by
the SET2 pin. ICCMAX register is set by an external voltage
divider by the multi-function mechanism. The Table 7
shows the ICCMAX setting in SET2 pin. For example,
ICCMAX = 25A, the VICCMAX needs to be set as 0.635V
typically. Additionally, VIMON − VREF needs to be set as
0.4V when ILx = 25A. The ICCMAX alert signal will be
pulled to low level if VIMON − VREF = 0.4V.
For the RT8171C, the ramp compensation also needs to
be considered during mode transition from PS0/1 to PS2.
For achieving smooth mode transition into PS2, a proper
ramp compensation design is necessary. Since the ramp
compensation needs to be proportional to the switching
frequency, in others words, ramp compensation is
dependent on switching frequency. The Table 6 shows
the relationship between switching frequency and ramp
compensation. For example, when designed switching
frequency is 400kHz, the RAMP is set as 400kHz  100% .
300kHz
Copyright © 2015 Richtek Technology Corporation. All rights reserved.
DS8171C-02
September 2015
is a registered trademark of Richtek Technology Corporation.
www.richtek.com
35
RT8171C
Table 7. SET2 Pin Setting for ICCMAX
VICCMAX =
R2
 5V
R1 R2
ICCMAX
Unit
Min
0.000
Typical
9.384
Max
18.768
Unit
mV
0
A
25.024
50.049
75.073
100.098
125.122
34.409
59.433
84.457
109.482
134.506
43.793
68.817
93.842
118.866
143.891
mV
mV
mV
mV
mV
1
2
3
4
5
A
A
A
A
A
150.147
175.171
200.196
225.220
250.244
159.531
184.555
209.580
234.604
259.629
168.915
193.939
218.964
243.988
269.013
mV
mV
mV
mV
mV
6
7
8
9
10
A
A
A
A
A
275.269
300.293
325.318
350.342
375.367
284.653
309.677
334.702
359.726
384.751
294.037
319.062
344.086
369.110
394.135
mV
mV
mV
mV
mV
11
12
13
14
15
A
A
A
A
A
400.391
425.415
450.440
475.464
409.775
434.800
459.824
484.848
419.159
444.184
469.208
494.233
mV
mV
mV
mV
16
17
18
19
A
A
A
A
500.489
525.513
550.538
575.562
600.587
509.873
534.897
559.922
584.946
609.971
519.257
544.282
569.306
594.330
619.355
mV
mV
mV
mV
mV
20
21
22
23
24
A
A
A
A
A
625.611
650.635
675.660
700.684
725.709
634.995
660.020
685.044
710.068
735.093
644.379
669.404
694.428
719.453
744.477
mV
mV
mV
mV
mV
25
26
27
28
29
A
A
A
A
A
750.733
760.117
769.501
mV
30
A
Anti-Overshoot Function
When DVID slew rate increases, loop response is difficult
to meet energy transfer so that output voltage generates
overshoot to fail specification. The RT8171C has AntiOvershoot function being able to help improve this issue.
The VR will turn off low-side MOSFET when output voltage
ramps up to the target VID (ALERT signal be pulled low).
This function also can improve the overshoot during the
Copyright © 2015 Richtek Technology Corporation. All rights reserved.
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36
load transient condition. When Anti-overshoot function is
triggered, the UGATE and LGATE signal will be masked
to reduce the overshoot. The Table 8 shows the AntiOvershoot setting in SET3 pin and this function can be
enabled/disabled by SET3 pin under load transient
condition. Please note that, this function is always enabled
under DVID condition.
is a registered trademark of Richtek Technology Corporation.
DS8171C-02
September 2015
RT8171C
Zero Load-Line
VR Address Setting
The RT8171C adopts G-NAVPTM (Green Native AVP),
which is Richtek's proprietary topology derived from finite
DC gain compensator with current mode control, making
it an easy to set the PWM controller, meeting all Intel
CPU requirements of AVP (Active Voltage Positioning).
The RT8171C also can support zero load-line application.
This function can be enabled/disabled by SET3 pin, as
shown in Table 8.
In VR 12.1 Intel SVID protocol, the data packet will contain
a 4 bit addressing code for future platform flexibility. The
RT8171C provides a VR address setting function that can
be set by SET3 pin. The VR will react according to the
SVID command when VR addressing setting bit is the
same with the CPU addressing code. When VR addressing
setting bit and the CPU addressing code are different, the
VR will skip the SVID command.
Shrink TON
In order to reduce ripple at PS2 and PS3. RT8171C support
shrink on-time function. If this function is enabled, the ontime at PS2 and PS3 will be 65% on-time of PS0. But the
switching frequency will be faster at PS2 and PS3.
The Table 8 and Table 9 show the VR Address setting in
SET3 pin. It is noted that VR Address constructs from
MSB and LSB. The Table 10 shows the more clearly
relation about the real VR Address.
Table 8. SET3 Pin Setting for Function 1
VSET3_1 
Min
0.000
25.024
50.049
75.073
100.098
125.122
150.147
175.171
200.196
225.220
250.244
275.269
300.293
325.318
350.342
375.367
400.391
425.415
450.440
475.464
500.489
525.513
550.538
575.562
Typical
10.948
35.973
60.997
86.022
111.046
136.070
161.095
186.119
211.144
236.168
261.193
286.217
311.241
336.266
361.290
386.315
411.339
436.364
461.388
486.413
511.437
536.461
561.486
586.510
R2
 5V
R1 R2
Max
21.896
46.921
71.945
96.970
121.994
147.019
172.043
197.067
222.092
247.116
272.141
297.165
322.190
347.214
372.239
397.263
422.287
447.312
472.336
497.361
522.385
547.410
572.434
597.458
Anti-Overshoot
Unit
mV
mV
mV
mV
mV
mV
mV
mV
mV
mV
mV
mV
mV
mV
mV
mV
mV
mV
mV
mV
mV
mV
mV
mV
Copyright © 2015 Richtek Technology Corporation. All rights reserved.
DS8171C-02
September 2015
Zero Load-Line
VR Address
MSB
0
Disable
1
Disable
Enable
0
is a registered trademark of Richtek Technology Corporation.
www.richtek.com
37
RT8171C
Min
600.587
R2
 5V
R1 R2
Typical
Max
611.535
622.483
Unit
mV
625.611
650.635
675.660
700.684
725.709
636.559
661.584
686.608
711.632
736.657
647.507
672.532
697.556
722.581
747.605
mV
mV
mV
mV
mV
750.733
775.758
800.782
825.806
850.831
761.681
786.706
811.730
836.755
861.779
772.630
797.654
822.678
847.703
872.727
mV
mV
mV
mV
mV
875.855
900.880
925.904
950.929
886.804
911.828
936.852
961.877
897.752
922.776
947.801
972.825
mV
mV
mV
mV
975.953
1000.978
1026.002
1051.026
1076.051
986.901
1011.926
1036.950
1061.975
1086.999
997.849
1022.874
1047.898
1072.923
1097.947
mV
mV
mV
mV
mV
1101.075
1126.100
1151.124
1176.149
1201.173
1112.023
1137.048
1162.072
1187.097
1212.121
1122.972
1147.996
1173.021
1198.045
1223.069
mV
mV
mV
mV
mV
1226.197
1251.222
1276.246
1301.271
1237.146
1262.170
1287.195
1312.219
1248.094
1273.118
1298.143
1323.167
mV
mV
mV
mV
1326.295
1351.320
1376.344
1401.369
1337.243
1362.268
1387.292
1412.317
1348.192
1373.216
1398.240
1423.265
mV
mV
mV
mV
1426.393
1451.417
1476.442
1501.466
1526.491
1551.515
1437.341
1462.366
1487.390
1512.414
1537.439
1562.463
1448.289
1473.314
1498.338
1523.363
1548.387
1573.412
mV
mV
mV
mV
mV
mV
1576.540
1587.488
1598.436
mV
VSET3_1 
Copyright © 2015 Richtek Technology Corporation. All rights reserved.
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38
Anti-Overshoot
Zero Load-Line
VR Address
MSB
Disable
Enable
1
0
Disable
1
Enable
0
Enable
1
is a registered trademark of Richtek Technology Corporation.
DS8171C-02
September 2015
RT8171C
Table 9. SET3 Pin Setting for Function 2
VR
Address
LSB
Switching
Frequency
Min
Typical
Max
unit
0.000
23.46041
46.921
mV
50.049
73.48485
96.921
mV
100.098
123.5093
146.921
mV
150.147
173.5337
196.921
mV
200.196
223.5582
246.921
mV
250.244
273.5826
296.921
mV
300.293
323.607
346.921
mV
350.342
373.6315
396.921
mV
400.391
423.6559
446.921
mV
450.440
473.6804
496.921
mV
500.489
523.7048
546.921
mV
550.538
573.7292
596.921
mV
600.587
623.7537
646.921
mV
650.635
673.7781
696.921
mV
700.684
723.8025
746.921
mV
750.733
773.827
796.921
mV
3mV
800.782
823.8514
846.921
mV
0.75mV
850.831
873.8759
896.921
mV
900.880
923.9003
946.921
mV
950.929
973.9247
996.921
mV
1000.978
1023.949
1046.921
mV
1051.026
1073.974
1096.921
mV
1101.075
1123.998
1146.921
mV
1151.124
1174.022
1196.921
mV
1201.173
1224.047
1246.921
mV
1251.222
1274.071
1296.921
mV
1301.271
1324.096
1346.921
mV
1351.320
1374.12
1396.921
mV
1401.369
1424.145
1446.921
mV
1451.417
1474.169
1496.921
mV
1501.466
1524.194
1546.921
mV
1551.515
1574.218
1596.921
mV
Copyright © 2015 Richtek Technology Corporation. All rights reserved.
DS8171C-02
September 2015
Shrink T ON
ZCD_TH<1:0>
0.75mV
Disable
1.5mV
2.25mV
3mV
FSW > 500kHz
0.75mV
Enable
1.5mV
2.25mV
3mV
1
0.75mV
Disable
1.5mV
2.25mV
3mV
FSW ≦ 500kHz
0.75mV
Enable
Disable
1.5mV
2.25mV
1.5mV
2.25mV
3mV
FSW > 500kHz
0.75mV
Enable
1.5mV
2.25mV
3mV
0
0.75mV
Disable
1.5mV
2.25mV
3mV
FSW ≦ 500kHz
0.75mV
Enable
1.5mV
2.25mV
3mV
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39
RT8171C
Table 10. Composing about Real VR Address
VR Address
MSB/LSB
Real VR Address
0
0
0
0
1
1
1
0
4
1
1
5
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40
is a registered trademark of Richtek Technology Corporation.
DS8171C-02
September 2015
RT8171C
Over Current Protection
The RT8171C has dual OCP mechanism. One is named
OCP-SUM, the other is called OCP-SPIKE. The over
current protection (OCP) forces high-side MOSFET and
low-side MOSFET off by shutting down internal PWM logic
drivers. RT8171C provides OCP-SUM which is set by SET1
pin. The OCP-SUM threshold setting can refer to ICCMAX
current in the Table 7. For example, if ICCMAX is set as
25A, user can set voltage by using the external voltage
divider in SET1 pin as 1.262V typically if DVID_Threshold
= 25mV, then 30A OCP-SUM (120% x ICCMAX) threshold
will be set. When output current is higher than the OCPSUM threshold, OCP-SUM is latched with a 40μs delay
time to prevent false trigger. Besides, the OCP-SUM
function is masked when dynamic VID transient occurs
and after dynamic VID transition, OCP-SUM is masked
for 80μs. The other one is per phase OCP which should
trip when the output current exceeds quintuple ICCMAX
during soft-start. When output current is higher than the
per phase OCP threshold, per phase OCP is latched with
a 1μs delay time to prevent false trigger. Please note that,
here is no OCP at PS3.
Over Output Voltage Protection
There are two conditions for OVP. One is when VSEN is
higher than 1.2V. The other is when VSEN is smaller than
1.2V. For VSEN is higher than 1.2V, OVP condition is
detected when the VSEN pin is 350mV more than VID.
For VSEN is smaller than 1.2V, OVP is occurred when
VSEN is higher than 1.55V. When OVP condition is
detected, the upper gate voltage UGATE is pulled-low and
lower gate voltage LGATE is pulled-high. OVP is latched
with a 0.5us delay time to prevent false trigger.
Negative Voltage Protection
Since the OVP latch continuously turns on low-side
MOSFET of the VR, the VR will suffer negative output
voltage. When the VSEN detects a voltage below −0.05V
after triggering OVP, the VR will trigger NVP to turn off
low-side MOSFET of the VR while the high-side MOSFET
remains off. After triggering NVP, if the output voltage rises
above 0V, the OVP latch will restart to turn on low-side
MOSFET. Therefore, the output voltage may bounce
between 0V and −0.05V due to OVP latch and NVP
triggering. The NVP function will be active only after OVP
is triggered.
Under Voltage Protection
When the VSEN pin voltage is 350mV less than VID, a
UVP will be latched. When UVP latched, both the UGATE
and LGATE will be pulled-low. A 3.5μs delay is used in
UVP detection circuit to prevent false trigger. Besides,
the UVP function is masked when dynamic VID transient
occurs and after dynamic VID transition, UVP is masked
for 80μs.
Under Voltage Lock Out (UVLO)
During normal operation, if the voltage at the VCC pin
drops below POR threshold 4.1V (min), the VR will trigger
UVLO. The UVLO protection forces high-side MOSFET
and low-side MOSFET off by shutting down internal PWM
logic drivers.
Power Ready (POR) Detection
During start-up, the RT8171C will detect the voltage at
the voltage input pins : VCC, EN and PVCC. When VCC >
4.1V and PVCC > 4V the RT8171C will recognize the
power state of system to be ready (POR = high) and wait
for enable command at the EN pin. After POR = high and
VEN > 0.7V, the RT8171C will enter start-up sequence. If
the voltage at any voltage pin drops below low threshold
(POR = low), the RT8171C will enter power down
sequence and all the functions will be disabled. Normally,
connecting system voltage VTT (1.05V) to the EN pin is
recommended.1ms (max) after the chip has been enabled,
the SVID circuitry will be ready. All the protection latches
(OVP, OCP, UVP) will be cleared only by VCC. The
condition of VEN = low will not clear these latches. Figure
19 and Figure 20 show the POR detection and the timing
chart for POR process, respectively.
5V
VCC
4.1V
PVCC
VTT
1.05V
PVCC
+
CP
-
POR
DRIVER
Enable
EN
+
0.7V
CP
-
Figure 19. POR Detection
Copyright © 2015 Richtek Technology Corporation. All rights reserved.
DS8171C-02
September 2015
is a registered trademark of Richtek Technology Corporation.
www.richtek.com
41
RT8171C
divider elements (R1, R2 and NTC) so that VTSEN = 1.887V
at 100°C. The resistance accuracy of TSEN network is
recommended to be 1% or higher.
R2
VTSEN = VCC 
= 1.887V
R2 + R1//RNTC(100C) 
VCC
PVCC
POR
EN
1ms
VDDIO
SVID Invalid
Invalid
Valid
VR_HOT
VCC
Figure 20. Timing Chart for POR Process
R1
Precise Reference Current Generation, IBIAS
Analog circuits need very precise reference voltage/current
to drive/set these analog devices. The RT8171C provides
a 2V voltage source at the IBIAS pin, and a 100kΩ resistor
is required to be connected between IBIAS pin and analog
ground to generate a very precise reference current.
Through this connection, the RT8171C will generate a
20μA current from the IBIAS pin to analog ground, and
this 20μA current will be mirrored inside the RT8171C for
internal use. The IBIAS pin can only be connected with a
100kΩ resistor to GND for internal analog circuit use. The
resistance accuracy of this resistor is recommended to
be 1% or higher. Figure 21 shows the IBIAS setting circuit.
Current Mirror
+
NTC
TSEN
-
R2
1.887V
SetGND
Figure 22. VR_HOT Circuit
VBOOT
The RT8171C provides controllable VBOOT function as
shown in Figure 23. The VBOOT voltage can be set by
the VBOOTSEL pin. Table 11 shows the VBOOT voltage
setting in VBOOTSEL pin. For example, when VBOOT =
1V, the VBOOTSEL set voltage will be between 1.3V and
3.7V. It's noted that, if floating VBOOTSEL pin that the
VBOOT voltage will not be defined.
VCC
2V
+
20µA
R1
-
VBOOTSEL
IBIAS
100k
R2
SetGND
Figure 21. IBIAS Setting Circuit
TSEN and VR_HOT
The VR_HOT signal is an open-drain signal which is used
for VR thermal protection. When the sensed voltage in
TSEN pin is over 1.887V under VCC is exact 5V condition,
the VR_HOT signal will be pulled-low to notify CPU that
the thermal protection needs to work. Please note that,
the VR thermal protection is only valid under PS0, PS1
and PS2 condition. According to Intel VR definition,
VR_HOT signal needs acting if VR power chain
temperature exceeds 100°C. Placing an NTC thermistor
at the hottest area in the VR power chain and its
connection is shown in Figure 22, to design the voltage
Copyright © 2015 Richtek Technology Corporation. All rights reserved.
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42
Figure 23. VBOOTSEL Circuit.
Table 11. VBOOTSEL Pin setting for VBOOT
R2
 5V
R1  R2
Typical
Max
Unit
VBOOTSEL 
Min
VBOOT
0
0.6
1.2
V
0.9
1.3
2.5
3.7
V
1.0
3.8
4.4
5
V
1.1
Differential Remote Sense Setting
The VR provides differential remote-sense inputs to
eliminate the effects of voltage drops along the PC board
traces as signified as Figure 24. CPU internal power routes
is a registered trademark of Richtek Technology Corporation.
DS8171C-02
September 2015
RT8171C
and socket contacts. The CPU contains on-die sense pins,
VCC_SENSE and VSS_SENSE. Connecting RGND to VSS_SENSE
and connect FB to VCC_SENSE with a resistor to build the
negative input path of the error amplifier. The VDAC and the
precision voltage reference are referred to RGND for
accurate remote sensing.
R x  Cx =
VCORE
IOUT x RLL
IOUT
IOUT
CPU VCC_SENSE
Expected load transient waveform
VOUT
R1
FB
EA
+
COUT
+
VID
Lx
DCR x
VCORE
R2
RGND
R x  Cx <
Lx
DCR x
IOUT x RLL
CPU VSS_SENSE
IOUT
Figure 24. Remote Sensing Circuit
IOUT
Current Loop Design in Details
VREF
REQ
RNTC
IMON
ISENN
+
-
Lx
DCRx
Rx
Cx
Lx
DCR x
IOUT x RLL
680
2/3
IOUT
+
0.6V
R x  Cx >
VCORE
ISENP
ISENN
Undershoot created in VCORE
VCORE
ILx
IOUT
Sluggish droop
COMP +
+
Figure 25. Current Loop Structure
Figure 25 shows the whole current loop structure. The
current loop plays an important role in RT8171C that can
decide ACLL performance (for load-line is required
condition), DCLL accuracy and ICCMAX accuracy. For
ACLL performance, the correct compensator design is
assumed, if RC network time constant matches inductor
time constant LX / DCRX, an expected load transient
waveform can be designed. If RXCX network time constant
is larger than inductor time constant LX / DCRX, VCORE
waveform has a sluggish droop during load transient. If
RXCX network is smaller than inductor time constant
LX / DCRX, a worst VCORE waveform will sag to create an
undershoot to fail the specification. Figure 26 shows the
variety of RXCX constant corresponding to the output
waveforms.
Copyright © 2015 Richtek Technology Corporation. All rights reserved.
DS8171C-02
September 2015
Figure 26. All Kind of RXCX Constants
For DCLL performance and ICCMAX accuracy, since the
copper wire of inductor has a positive temperature
coefficient, when temperature goes high in the heavy load
condition then DCR value goes large simultaneously. A
resistor network with NTC thermistor compensation
connecting between IMON pin and REF pin is necessary,
to compensate the positive temperature coefficient of
inductor DCR. The design flow is as follows :
Step1 : Given the three system temperature TL, TR and
TH, at which are compensated.
Step2 : Three equations can be listed as
DCR (TL )

680
1
 iLi  REQ (TL ) = 0.4
i=1
1
DCR (TR )

680
 iLi  REQ (TR ) = 0.4
i=1
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RT8171C
DCR (TH )

680
1

Design Step
iLi  REQ (TH ) = 0.4
i=1
Where :
(1) The relationship between DCR and temperature is as
follows :
DCR (T) = DCR (25C)  1+ 0.00393 (T - 25)
RT8171C Excel based design tool is available. Users can
contact your Richtek representative to get the
spreadsheet. Three main design procedures of RT8171C
design, first step is initial settings, second step is loop
design and last step is protection settings. The following
design example is to explain RT8171C design procedure:
(2) REQ(T) is the equivalent resistor of the resistor network
with a NTC thermistor

VCORE Specification
Input Voltage
7.4
No. of Phase
1
VBoot
1
ICCMAX
13
ICC-Dyn
8
MAX Switching Frequency
800kHz

REQ (T) = RIMON1 + RIMON2 / / RIMON3 + RNTC (T)
And the relationship between NTC and temperature is as
follows :
RNTC (T) = RNTC (25C)  e
β(
1
1
)

T+273 298
β is in the NTC thermistor datasheet.
Step3 : Three equations and three unknowns, RIMON1,
RIMON2 and RIMON3 can be found out unique solution.
RIMON1 = K TR 
RIMON2 =
RIMON2  (RNTCTR +RIMON3 )
RIMON2 +RNTCTR +RIMON3
2
[KR3
+KR3 (RNTCTL +RNTCTR )
+RNTCTLRNTCTR ]α TL
RIMON3 = -RIMON2 +KR3
The output filter requirements of VRTB specification are
as follows :
Output Inductor : 330nH/2.95mΩ
Output Bulk Capacitor : 270μF/2V.6mΩ (3pcs)
Output Ceramic Capacitor : 22μF/0603 (6pcs max sites
on top side)
(1) Initial Settings

Where :
R2
=2.5V, R1 can be selected by user and here
R1+R2
R1 is equal to 10kΩ so R2 is equal to 10kΩ.
5
K TH  K TR
α TH =
RNTCTH  RNTCTR
α TL =
K TL  K TR
RNTCTL  RNTCTR
KR3 =
(α TH / α TL )RNTCTH  RNTCTL
1  (α TH / α TL )
K TL =
0.4
GCS(TL)  ICC-MAX
K TR =
0.4
GCS(TR)  ICC-MAX
K TH =
0.4
GCS(TH)  ICC-MAX
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RT8171C initial VBoot voltage is 1V

IBIAS needs to connect a 100kΩ resistor to ground.
(2) Loop Design

On time setting :
VIN(MAX) = 7.4V, VDAC(MAX) = 1V, FSW(MAX) = 800kHz, ICC(MAX)
= 13A, DCR = 2.95mΩ, RLL = 0Ω, RON-HS = 6mΩ, RON-LS
= 6mΩ, TD = 30ns, TON,VAR = 15ns.
Using the Microsoft Excel-based spreadsheet from
RICHTEK.
The RTON resistance can be calculated after the switching
frequency and the on-time are decided.
(V  VDAC )  TON
RTON  IN
 652k
18.2p  0.11
Choosing the nearest on-time setting resistor RTON =
649kΩ
is a registered trademark of Richtek Technology Corporation.
DS8171C-02
September 2015
RT8171C

Current sensor adopts lossless RC filter to sense current
signal in DCR. For getting an expected load transient
waveform RXCX time constant needs to match LX / DCRX.
CX = 0.47μF is set, then
LX
 240
RX 
0.47μF  DCR X
Where RLL is load-line, COUT is total output capacitance
and dVID/dt is DVID fast slew rate. Here the load-line is
equal to zero. Thus the DVID compensation isn't work
under the zero load-line application. So, DVID_TH and
DVID_Width can be set to any value. Here DVID_TH
and DVID_Width are chosen as 15mV and 72μs,
respectively. Next, OCP threshold I is designed as 1.28
x ICCMAX. Last, RAMP = 800kHz / 300kHz = 267%,
267% is set. By using above information, the two
equations can be listed by using multi-function pin
setting mechanism :
But RX = 240Ω will let REQ is too small, so here the current
sense method 2 should be selected. By using the design
tool, Rx1 and Rx2 can be determined, both are equal to
475Ω.


IMON resistor network design : TL = 25°C, TR = 50°C
and TH = 100°C are decided, NTC thermistor = 100kΩ
@ 25°C, β = 4050 and ICCMAX = 13A. According to the
sub-section “Current Loop Design in Details”, RIMON1
= 6.63kΩ, RIMON2 = 8.83kΩ and RIMON3 = 5.44kΩ can
be decided. The REQ (25°C) = 14.187kΩ.
Load-line design : If load-line is required, the load-line
can be determined by below equation and the voltage
loop AV gain is also decided by the following equation :
RLL
1  DCR  R
EQ
A V 3 RCS


AI
R2
R1
R2  1137.3mV
R1 R2
80μ  R1 R2  1487.6mV
R1 R2
5
R1 = 81.757kΩ and R2 = 24.065kΩ.

(m)
Here the load-line isn't required. The suggestion AV gain
is 5 to 10 for the zero load-line application. R1 = 10kΩ is
usually decided and here R2 is chosen to 68kΩ.

1
 39.7pF
R1  fSW
C
 ESR
C2  OUT
 28pF
R2
For Intel platform, in order to induce the band width to
enhance transient performance to meet Intel's criterion,
the zero location can be designed close to 1/10 of the
switching frequency or less than the 1/10 of switching
frequency.

R2  334.7mV
R1  R2
80μ  R1 R2  86.02mV
R1  R2
5
Typical compensator design can use the following
equations to design C1 and C2 values
C1 
SET1 resistor network design : First, the DVID
compensation parameters need to be decided. The
DVID_TH can be calculated as the following equation :
VDVID_TH  RLL  COUT  dVID
dt
Copyright © 2015 Richtek Technology Corporation. All rights reserved.
DS8171C-02
September 2015
SET2 resistor network design : The QR mechanism
parameters need to be designed at first. Due to the load
current step is small and output capacitance is large,
the QR mechanism isn't necessary. The QR_TH is set
to disable and QR Width is designed as 1.11 x TON. The
ICCMAX is designed as 13A. By using the information,
the two equation can be listed by using multi-function
pin setting mechanism :
R1 = 16.063kΩ and R2 = 1.1524kΩ.

SET3 resistor network design: The zero load-line function
and anti-overshoot function are decided to enable at first.
Then, the ZCD threshold is chosen as 0.75mV, shrink
TON is disabled, switching frequency is chosen fSW >
500kHz and VR address is usually set to 0. By using
the information, the two equations can be listed by using
multi-function pin setting mechanism:
5  R2  1299.7mV
R1  R2
80μ  R1 R2  824.24mV
R1  R2
R1 = 39.64kΩ and R2 = 13.92kΩ.
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RT8171C


Maximum Power Dissipation (W)1
(3) Protection Settings
OVP/UVP protections: When the VSEN pin voltage is
350mV higher than VID, the OVP will be latched. When
the VSEN pin voltage is 350mV lower than VID, the
UVP will be latched.
TSEN and VR_HOT design : Using the following equation
to calculate related resistances for VR_HOT setting.
R2
VTSEN  VCC 
 1.887V
R2  RNTC(100oC) //R1


Choosing R1 = 100kΩ and an NTC thermistor RNTC (25°C)
= 100kΩ and its β = 4485. When temperature is 100°C,
the RNTC(100°C) = 4.85kΩ. Then R2 = 2.8kΩ can be
calculated.
PD(MAX) = (TJ(MAX) − TA) / θJA
where TJ(MAX) is the maximum junction temperature, TA is
the ambient temperature, and θJA is the junction to ambient
thermal resistance.
For recommended operating condition specifications, the
maximum junction temperature is 125°C. The junction to
ambient thermal resistance, θJA, is layout dependent. For
WQFN-32L 4x4 package, the thermal resistance, θJA, is
27.8°C/W on a standard JEDEC 51-7 four-layer thermal
test board. The maximum power dissipation at TA = 25°C
can be calculated by the following formula :
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3.0
2.5
2.0
1.5
1.0
0.5
0
25
50
75
100
125
Ambient Temperature (°C)
Figure 27. Derating Curve of Maximum Power
Dissipation
Layout Considerations
PCB layout is critical to achieve low switching losses and
stable operation. The switching power stage requires
particular attention. If possible, mount all of the power
components on the top side of the board with their ground
terminals flushed against one another. Follow these
guidelines for the optimum PCB layout :

Keep the high current paths short, especially at the
ground terminals.

Keep the power traces and load connections short. This
is essential for high efficiency.

When trade-offs in trace lengths must be made, it's
preferable to let the inductor charging path be longer
than the discharging path.

Place the current sense component close to the
controller. ISENP and ISENN connections for current
limit and voltage positioning must be made using Kelvin
sense connections to guarantee current sense accuracy.
The PCB trace from the sense nodes should be
paralleled back to the controller.

Route high speed switching nodes away from sensitive
analog areas (COMP, FB, ISENP, ISENN, etc...)

Connect the exposed pad to the ground plane through
low impedance path. Recommend use of at least 5 vias
to connect to ground planes in PCB internal layers.
PD(MAX) = (125°C − 25°C) / (27.8°C/W) = 3.59W for
WQFN-32L 4x4 package
The maximum power dissipation depends on the operating
ambient temperature for fixed T J(MAX) and thermal
resistance, θJA. The derating curve in Figure 27 allows
the designer to see the effect of rising ambient temperature
on the maximum power dissipation.
Four-Layer PCB
3.5
0.0
Thermal Considerations
For continuous operation, do not exceed absolute
maximum junction temperature. The maximum power
dissipation depends on the thermal resistance of the IC
package, PCB layout, rate of surrounding airflow, and
difference between junction and ambient temperature. The
maximum power dissipation can be calculated by the
following formula :
4.0
is a registered trademark of Richtek Technology Corporation.
DS8171C-02
September 2015
RT8171C
Outline Dimension
1
1
2
2
DETAIL A
Pin #1 ID and Tie Bar Mark Options
Note : The configuration of the Pin #1 identifier is optional,
but must be located within the zone indicated.
Dimensions In Millimeters
Symbol
Dimensions In Inches
Min.
Max.
Min.
Max.
A
0.700
0.800
0.028
0.031
A1
0.000
0.050
0.000
0.002
A3
0.175
0.250
0.007
0.010
b
0.150
0.250
0.006
0.010
D
3.900
4.100
0.154
0.161
D2
2.650
2.750
0.104
0.108
E
3.900
4.100
0.154
0.161
E2
2.650
2.750
0.104
0.108
e
L
0.400
0.300
0.016
0.400
0.012
0.016
W-Type 32L QFN 4x4 Package
Richtek Technology Corporation
14F, No. 8, Tai Yuen 1st Street, Chupei City
Hsinchu, Taiwan, R.O.C.
Tel: (8863)5526789
Richtek products are sold by description only. Richtek reserves the right to change the circuitry and/or specifications without notice at any time. Customers should
obtain the latest relevant information and data sheets before placing orders and should verify that such information is current and complete. Richtek cannot
assume responsibility for use of any circuitry other than circuitry entirely embodied in a Richtek product. Information furnished by Richtek is believed to be
accurate and reliable. However, no responsibility is assumed by Richtek or its subsidiaries for its use; nor for any infringements of patents or other rights of third
parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Richtek or its subsidiaries.
DS8171C-02
September 2015
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