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HDMI Input/Output FMC Module with Camera Interface
Hardware Guide
Table of Contents
Figures
Tables
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1.0 Introduction
The purpose of this manual is to describe the functionality and contents of the HDMI Input/Output FMC Module with Camera Interface from Avnet Electronics Marketing. This document includes descriptions of the hardware features.
1.1 Description
The HDMI Input/Output FMC Module with Camera Interface is not a stand-alone module, but rather a plug-in module designed to interface with FMC compatible baseboards. In that role, the FMC adapter provides a number of video interfaces to its host
via a LPC FMC connector. The FMC Module is shown in Figure 1.
1.2 Features
The HDMI Input/Output FMC Module provides the following features.
Video Input
— HDMI input interface
— Camera interface
Video Output
— HDMI output interface
Clock Source
— Video clock synthesizer
I2C Configuration
— IPMI Identification EEPROM
— Peripheral configuration
Figure 1
– FMC-HDMI-CAM – Top/Bottom View
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1.3 Ordering Information
The following table lists the evaluation kit part numbers and available software options.
Part Number
AES-FMC-HDMI-CAM-G
( http://www.em.avnet.com/fmc-hdmi-cam )
AES-CAM-TOSH-1080P-G
AES-CAM-ON-P1300C-G
Hardware
HDMI Input/output FMC Module
(camera module not included)
Optional camera modules
Toshiba Industrial 1080P60 Camera Module
ON Semiconductor PYTHON-1300-C Camera Module
Table 1 - Ordering Information
Figure 2
– FMC-HDMI-CAM – Angle View
1.4 References
Analog Devices Engineering Zone : ADV7611 HDMI Receiver resources http://ez.analog.com/docs/DOC-1745
Analog Devices Engineering Zone : ADV7511 HDMI Receiver resources http://ez.analog.com/docs/DOC-1740
Texas Instruments CDCE913 datasheet: Programmable 2-PLL VCXO Clock Synthesizer http://focus.ti.com/docs/prod/folders/print/cdce913.html
FMC Specification http://www.vita.com/fmc.html
Platform Management FRU Information Storage Definition V1.0 http://download.intel.com/design/servers/ipmi/FRU1011.pdf
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2.0 Functional Description
The FMC-HDMI-CAM is a low pin count (LPC) FMC module containing interfaces intended for video processing. This module contains no processing intelligence and requires that it be plugged into a compatible baseboard for power, control and data processing. The FMC module has a camera interface that allows optional camera modules to be populated..
Figure 3 depicts the architecture of the FMC-HDMI-CAM FMC module.
Optional
Camera Modules
HDMI
Output
HDMI
Input
Camera Interface
Connector
HDMI
Connector
HDMI
Connector
FMC-HDMI-CAM
5V
5V supply
12V
Video Clock
Synthesizer
ADV7511 ADV7611
FMC LPC
(72 I/O, 36 differential)
Figure 3
– FMC-HDMI-CAM - Block Diagram
Figure 4
– FMC-HDMI-CAM – Shown with Toshiba camera module
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Figure 5
– FMC-HDMI-CAM – Shown with PYTHON-1300-C camera module
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2.1 FMC Connector
The FMC LPC connector provides 68 single-ended I/O or 34 differential I/O as defined in Table 2.
Table 2
– FMC LPC Connector Pinout
Note: For the FMC LPC, the connector columns K, J, F, E, B, and A are not used and not shown in the above table.
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34
35
36
37
38
39
40
26
27
28
29
30
31
32
33
5
6
7
8
9
10
11
The FMC pin allocation for the FMC-HDMI-CAM FMC Module is defined in Table 3.
H G D
1
2
3
4
-
PRSNT_M2C_L
GND
VCLK1
GND
HDMII_CLK (in)
HDMIO_CLK (out)
GND
1
2
3
4
PG_C2M
GND
GND
-
CAM_RESET_N
GND
CAM_D[0]_P
CAM_D[0]_N
GND
CAM_D[3]_P
CAM_D[3]_N
GND
CLK_OUT_P (in)
CLK_OUT_N (in)
GND
CAM_D[1]_P
CAM_D[1]_N
GND
5
6
7
8
10
11
-
GND
GND
HDMIIO_INT#
9 I2C_MUX_RESET_N
GND
CAM_D[4]_P
12
13
14
15
16
17
18
GND
CAM_D[5]_P
CAM_D[5]_N
GND
CAM_SPI_MOSI
CAM_SPI_MISO
GND
19 CAM_MONITOR[1]
20 CAM_MONITOR[0]
21 GND
22
23
24
25
HDMIO_CBCR[4]
HDMIO_CBCR[1]
GND
HDMIO_Y[4]
CAM_D[6]_P
CAM_D[6]_N
GND
CAM_SPI_CLK
CAM_SPI_SSEL_N
GND
I2C_MUX_SCL
I2C_MUX_SDA
GND
HDMIO_CBCR[7]
HDMIO_CBCR[5]
GND
HDMIO_CBCR[0]
HDMII_Y[5]
12
13
14
15
16
17
18
19
20
21
22
23
24
25
CAM_D[4]_N
GND
CAM_D[7]_P
CAM_D[7]_N
GND
CAM_CLK_PLL
CAM_TRIGGER[2]
GND
HDMIO_CBCR[6]
HDMIO_CBCR[3]
GND
HDMIO_Y[7]
HDMIO_Y[3]
GND
HDMIO_Y[2]
GND
HDMIO_SPDIF
HDMII_SPDIF
GND
HDMII_Y[1]
HDMII_Y[0]
GND
HDMII_CBCR[5]
HDMII_CBCR[4]
GND
HDMII_CBCR[1]
HDMII_CBCR[0]
GND
VADJ
GND
HDMIO_Y[1]
HDMIO_Y[0]
GND
HDMII_Y[5]
HDMII_Y[2]
GND
HDMII_CBCR[7]
HDMII_CBCR[6]
GND
HDMII_CBCR[3]
HDMII_CBCR[2]
GND
VADJ
GND
34
35
36
37
38
39
40
26
27
28
29
30
31
32
33
HDMII_Y[7]
HDMII_Y[4]
GND
-
TDI
TDO
1
3P3VAUX
-
-
GA1
3P3V
GND
3P3V
GND
3P3V
Table 3
– FMC-HDMI-CAM - LPC Pinout
C
GND
-
-
GND
GND
-
-
GND
GND
CAM_D[2]_P
CAM_D[2]_N
GND
GND
CAM_SYNC_P
12
13
14
CAM_SYNC_N
GND
15
16
GND 17
CAM_TRIGGER[1] 18
CAM_TRIGGER[0] 19
GND 20
GND 21
HDMIO_CBCR[2] 22
HDMIO_Y[6] 23
GND
GND
24
25
5
6
7
8
9
10
11
1
2
3
4
HDMII_Y[6]
HDMII_Y[3]
GND
GND
SCL
SDA
GND
GND
GA0
12P0V
GND
12P0V
GND
3P3V
GND
34
35
36
37
38
39
40
26
27
28
29
30
31
32
33
1
TDO is connected to TDI in order not to break the JTAG chain
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2.2 Voltage Sources
The following table lists all the voltage sources available on the FMC-HDMI-CAM module.
Voltage Name
3V3AUX
3V3
VADJ
12V
REG_5V
REG_1V8
Voltage
3.3 V
3.3 V
2.5 V or 3.3 V
12.0 V
5V
1.8V
Current Description
supplied by FMC connector
Used by IPMI Identification prior to module power-up.
Used by ADV7611, ADV7511, CDCE913, and level translators
Used for all single-ended signals connected to FMC connector. supplied by the FMC-HDMI-CAM FMC module
1A
TBD
Over-designed for VITA-5000 image sensor module
Used by ADV7611, ADV7511, CDCE913
Table 4
–Voltage Sources
2.3 I2C Chain 1
– IPMI Identification EEPROM
The following I2C section implements the IPMI identification for the FMC module.
3.3V
GA1
GA0
SCL
SDA
FMC LPC connector
PRSTN_M2C_L
EEPROM
PG_C2M
VADJ
VREF_A_M2C
Figure 6
– IPMI Identification, Block Diagram
When the VADJ voltage is valid, the PG_C2M (ie. power good) will be asserted high. An inverted version of this signal is used to enable all the voltage level translators connected to VADJ.
The address of the I2C EEPROM will be determined by the GA[0:1] signals driven by the carrier.
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Table 5 describes the EEPROM address for the FMC module.
GA[0:1]
FMC-HDMI-CAM
I2C EEPROM Address
00
01
10
11
0xA0
0xA2
0xA4
0xA6
Table 5
– IPMI Identification, I2C EEPROM Address
The EEPROM content is defined by the Platform Management FRU Information Storage Definition V1.0. http://download.intel.com/design/servers/ipmi/FRU1011.pdf
For the FMC-HDMI-CAM module, the content is described in Table 6.
Content FMC-HDMI-CAM
Board Information
- Manufacturer Date/Time
- Manufacturer
- Product
- Serial
- Part Number
- FRU File ID
-
Avnet
FMC-HDMI-CAM
{programmed during factory testing}
AES-FMC-HDMI-CAM-G
-
Table 6
– IPMI Identification, EEPROM Content
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2.4 I2C Chain 2
– Peripheral Configuration
The FMC-HDMI-CAM Module implements two I2C chains. The second I2C chain is used to configure the FMC-HDMI-CAM module’s peripherals.
VADJ
FMC LPC
Connector
I2C_MUX_SCL
I2C_MUX_SDA
VADJ
VADJ
I2C_MUX_RST
5
CAM_SCL
CAM_SDA
VADJ
Camera
Connector
3P3V
I2C I/O
Expander
4
PLL_IO_SCL
PLL_IO_SDA
Clock
Synth.
3P3V
3
HDMII_SCL
HDMII_SDA
HDMI Rx
ADV7611
3P3V
2
HDMIO_SCL
HDMIO_SDA
HDMI Tx
ADV7511
REG_5P0V
1
HDMIO_DDC_SCL
HDMIO_DDC_SDA
HDMI Tx
EDID on-board devices off-board devices
I2C
Multiplexer
(PCA9548A)
Figure 7
– I2C Peripheral Configuration, Block Diagram
The Texas Instruments PCA9546A I2C Multiplexer performs two purposes:
Voltage level translation (2.5 V, 3.3 V, 5.0 V)
I2C address conflict resolution
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The following table lists the I2C addresses that may be present on each of the I2C Multiplexer’s ports. Notice that the I2C
Multiplexer’s address is always visible regardless of which port is enabled.
Device I2C Address
0xE0 (PCA9546) I2C Multiplexer
HDMI Output DDC EDID
Mux Port 1
Mux Port 2
0xA0
HDMI Output
HDMI Input
Video Clock Synth.
I2C I/O Expander
Camera unused
0x72 (ADV7511)
Mux Port 3
0x98 (ADV7611)
Mux Port 4
0xCA (CDCE913)
0x40 (PCA9555)
Mux Port 5 specific to camera module
Mux Port 6
Mux Port 7 unused
Mux Port 8 unused
Table 7
– I2C Peripheral Configuration, Device Summary
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2.5 I2C I/O Expander
The FMC module implements many features that require additional I/Os outside the available I/Os provided via the FMC connector. To accomplish the requirement for the additional I/Os, an I2C I/O Expander was implemented to handle various controls signals attached to peripherals.
The I2C I/O Expander is implemented with the Texas Instruments PCA9534. The I2C I/O Expander takes an I2C interface from the I2C MUX and decodes that to provide 8 USER GPIO on its outputs. This is an ideal device for the control signal support that was required by the peripherals.
The figure below shows a high level diagram of the I2C I/O Expander circuit on the FMC module.
3P3V
VCLK_SCL
VCLK_SDA
I2C MUX
HDMII_RESET#
P5
P6
P7
P0
P1
P2
P3
P4
HDMII_HPD
HDMIO_HPD
HDMIO_PD
CAM_PWDN
CAM_USER_IO1
CAM_USER_IO2
I2C IO
Expander
(PCA9534)
Figure 8
– I2C I/O Expander, Block Diagram
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2.6 Video Clock Synthesizer
A Video Clock Generator is included on the FMC module in order to provide a clock for all video applications.
The following block diagram illustrates the connections for the Video Clock Generator.
+1.8V
+1.8V
+3.3V
S0
3P3V
VDDout
VADJ
PLL_IO_SCL
PLL_IO_SDA
Y1
Voltage Level
Translator
(LMK00804B)
27 MHz
Y2
Y3
FMC LPC
Connector
Video Clock
Synthesizer
(CDCE913)
Figure 9
– Video Clock Synthesizer, Block Diagram
The Texas Instruments CDCE913 clock synthesizer has three clock outputs which are used as follows.
Clock PLL Description
Y1
Y2
Y3
PLL1
PLL1
PLL1
Can be used for any application
Unused
Unused
Table 8
– Video Clock Generator, Clock Output Usage
The Y1 clock output can be used for any application. One of these applications could be the 62MHz reference clock for the camera interface, another could be the clock source for the HDMI output. The Y2 and Y3 clock outputs are not used.
The default mode of the CDCE913 is to output a 27 MHz clock on all of its outputs.
Configuration is performed via I2C. The SDA/SCL pins of the CDCE913 device are 3.3 V tolerant.
The settings of the CDCE913 video clock synthesizer can be calculated automatically using the TI Pro-
Clock™ software.
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2.7 HDMI Input
The HDMI input interface is implemented using the Analog Devices ADV7611 device. This device
’s output video interface supports YCbCr mode with embedded syncs, which significantly reduce the number of I/O required for the FMC side interface.
By using the YCbCr 4:2:2 mode, the pixels are 16 bits instead of 24 bits. This is acceptable since the Xilinx video reference designs use YCbCr 4:2:2 video format.
The following block diagram illustrates the connections between the FMC connector and the HDMI Receiver.
+5V
+3.3V
VADJ
CLK0_M2C_P
HDMII_LLC
HDMII_D[15:0]
HDMII_SPDIF
VADJ
Voltage Level
Translator
HMDIIO_INT#
28.6363MHz
+3.3V
HMDI_SCL
HDMI_SDA
+5V
HDMII_RXC+
HDMII_RXC-
HDMII_RX[2:0]+
HDMII_RX[2:0]-
HDMII_DDC_SCL
HDMII_DDC_SDA
HDMII_CEC
HDMII_HPD
HDMI
Connector
HDMII_RESET#
FMC LPC
Connector
HDMI
Receiver
(ADV7611)
I2C I/O
Expander
(PCA9555)
Figure 10
– HDMI Input, Block Diagram
The HDMII_SCL/SDA signals are connected to the I2C MUX device. The HDMII_RST# and HPD signals are connected to an
I2C IO Expander device. See the relevant sections for the I2C MUX and I2C IO Expander for details on asserting the signals connected to these devices.
More detailed information on the ADV7611, including a hardware user guide and recommended schematic/layout/bom, can be found on the Analog Devices EngineerZone: http://ez.analog.com/docs/DOC-1745
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2.8 HDMI Output
The HDMI output interface is implemented using the Analog Devices ADV7511 device. This device’s input video interface supports YCbCr mode with embedded syncs, which significantly reduce the number of I/O required for the FMC side interface.
By using the YCbCr 4:2:2 mode, the pixels are 16 bits instead of 24 bits. This is acceptable since the Xilinx video reference designs use YCbCr 4:2:2 video format.
The following block diagram illustrates the connections between the FMC connector and the HDMI Transmitter.
3P3V
3P3V
VADJ
HDMI_SCL
HDMI_SDA
HDMI_5P0V
HDMIO_VCLK
HDMIO_D[15:0]
HDMIO_TXC+
HDMIO_TXC-
HDMIO_TX[2:0]+
HDMIO_TX[2:0]-
HDMIO_SPDIF
HDMIO_DDC_SCL
HDMIO_DDC_SDA
HDMIO_CEC
HDMIO_HPD
HDMI
Connector
VADJ
HDMIO_PD
HMDIIO_INT#
FMC LPC
Connector
HDMI
Transmitter
(ADV7511)
I2C I/O
Expander
(PCA9555)
Figure 11
– HDMI Output, Block Diagram
The HDMIO_SCL/SDA and HDMIO_DDC_SCL/SDA signals are connected to an I2C MUX device. The HDMIO_PD and
HDMIO_HPD signals connected to an I2C IO Expander device. See the relevant sections for the I2C MUX and I2C IO
Expander for details on asserting the signals connected to these devices.
More detailed information on the ADV7511, including a hardware user guide and example schematics/layout, can be found on the Analog Devices EngineerZone: http://ez.analog.com/docs/DOC-1740
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2.9 Camera Interface
The Embedded Vision Carrier Card can accommodate a variety of camera modules with its camera interface, which defines pins for the following functions:
Configuration & Control (single-ended signals) o
I2C o
SPI o
Reset/Reference Clock o
Trigger o
Monitor o
LED control
Video (differential signals) o
CLK o
SYNC o
DATA[7:0]
Power o
5V, used by camera modules to create on-board voltages o
VIO, same as VCCO used for single-ended I/O
2.10 Camera Connector
The connector used to house the Camera Modules is a standard PCI Express connector. The x4 connector is chosen in order to support all the signals required by the camera interface (10 differential pairs, 16 single-ended signals).
The connector chosen for the PCI Express connector is a thru-hole (TH) version depicted in the image below, PCIE-064-02-F-
D-TH. The thru-hole (TH) connector is used with vertical PCB guides to hold the camera board at right-angle to the carrier card.
More information is availa ble for the PCI Express connectors at Samtec’s website: http://www.samtec.com/documents/webfiles/pdf/pcie.pdf
.
Figure 12
– PCIEx4 Camera Connector
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The following table describes the proprietary camera interface pin assignment on the thru-hole (TH) PCIe x4 Lane Connector
(Samtec: PCIE-064-02-F-D-TH).
Mapping for Camera Interface
Side B Side A
PCI Express x1
GND
+5V
GND
CAM_REFCLK
+5V
+5V
+5V
CAM_I2C_SCL
GND
CAM_CLK_P
CAM_CLK_N
GND
CAM_DATA0_P
+2.5V
+2.5V
CAM_I2C_SDA
+2.5V
CAM_DATA0_N
GND
CAM_DATA1_P
CAM_DATA1_N
+2.5V
GND
Key Notch
CAM_SPI_CLK
GND
CAM_DATA2_P
CAM_SPI_CS CAM_DATA2_N
CAM_SPI_MISO
GND
GND
GND
CAM_SPI_MOSI
CAM_DATA3_P
CAM_DATA3_N
PCI Express x4
GND
GND
CAM_RST#
CAM_DATA4_P
CAM_DATA4_N
CAM_PWDN
GND
GND
CAM_DATA5_P
CAM_TRIGGER0 CAM_DATA5_N
CAM_MONITOR0
GND
CAM_TRIGGER1
CAM_DATA6_P
CAM_TRIGGER2 CAM_DATA6_N
CAM_MONITOR1
GND
GND
CAM_DATA7_P
CAM_USER_IO1
CAM_DATA7_N
CAM_USER_IO2
GND
GND
CAM_SYNC_N
GND
CAM_SYNC_P
Table 9
– Camera Interface Pin Assignments
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3.0 Known Issues & Limitations
This section describes the known issues and limitations for the FMC Module.
There currently are no known issues and limitations for the FMC module.
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4.0 Revisions
V0.1 First Version (AES-FMC-HDMI-CAM-G) September 14, 2015
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