HT68FB540/HT68FB550/HT68FB560

HT68FB540/HT68FB550/HT68FB560

I/O Flash USB MCU with SPI

HT68FB540/HT68FB550/HT68FB560

HT68FB540/HT68FB550/HT68FB560

I/O Flash USB MCU with SPI

Table of Contents

Features ............................................................................................................ 6

CPU Featu�es ......................................................................................................................... �

Pe�iphe�al Featu�es ................................................................................................................. �

General Description ......................................................................................... 7

Selection Table ................................................................................................. 8

Block Diagram .................................................................................................. 8

Pin Assignment ................................................................................................ 9

Pin Description .............................................................................................. 12

Absolute Maximum Ratings .......................................................................... 18

D.C. Characteristics ....................................................................................... 18

A.C. Characteristics ....................................................................................... 20

LVD & LVR Electrical Characteristics .......................................................... 21

Power on Reset (AC+DC) Electrical Characteristics .................................. 21

System Architecture ...................................................................................... 22

Clo�king and Pipelining ......................................................................................................... ��

P�og�a� Counte� ................................................................................................................... �3

Sta�k ..................................................................................................................................... �4

A�ith�eti� and Logi� Unit – ALU ........................................................................................... �4

Flash Program Memory ................................................................................. 25

St�u�tu�e ................................................................................................................................ �5

Spe�ial Ve�to�s ..................................................................................................................... �5

Look-up Ta�le ........................................................................................................................ ��

Ta�le P�og�a� Exa�ple ........................................................................................................ ��

In Syste� P�og�a��ing – ISP .............................................................................................. �7

Flash Me�o�y Read/W�ite Page Size ................................................................................... �7

ISP Bootloade� ...................................................................................................................... �9

Flash P�og�a� Me�o�y Registe�s ........................................................................................ �9

In Appli�ation P�og�a� – IAP ............................................................................................... 33

In Ci��uit P�og�a��ing – ICP ............................................................................................... 37

On-Chip De�ug Suppo�t – OCDS ......................................................................................... 37

RAM Data Memory ......................................................................................... 38

St�u�tu�e ................................................................................................................................ 38

Special Function Register Description ........................................................ 42

Indi�e�t Add�essing Registe�s – IAR0� IAR1 ......................................................................... 4�

Me�o�y Pointe�s – MP0� MP1 .............................................................................................. 4�

Bank Pointe� – BP ................................................................................................................. 43

A��u�ulato� – ACC ............................................................................................................... 44

P�og�a� Counte� Low Registe� – PCL .................................................................................. 44

Rev. 1.40

� De�e��e� 01� �01�

HT68FB540/HT68FB550/HT68FB560

I/O Flash USB MCU with SPI

Rev. 1.40 3 De�e��e� 01� �01�

HT68FB540/HT68FB550/HT68FB560

I/O Flash USB MCU with SPI

Rev. 1.40

� De�e��e� 01� �01�

HT68FB540/HT68FB550/HT68FB560

I/O Flash USB MCU with SPI

Look-up Ta�le Registe�s – TBLP� TBHP� TBLH ..................................................................... 44

Status Registe� – STATUS .................................................................................................... 45

Oscillator ........................................................................................................ 46

Os�illato� Ove�view ............................................................................................................... 4�

System Clock Configurations

................................................................................................ 4�

Exte�nal C�ystal Os�illato� – HXT .......................................................................................... 47

Inte�nal PLL F�equen�y Gene�ato� ........................................................................................ 48

Inte�nal RC Os�illato� – HIRC ............................................................................................... 50

Inte�nal 3�kHz Os�illato� – LIRC ........................................................................................... 50

Supple�enta�y Inte�nal Clo�ks ............................................................................................. 50

Operating Modes and System Clocks ......................................................... 50

Syste� Clo�ks ...................................................................................................................... 51

Syste� Ope�ation Modes ...................................................................................................... 51

Cont�ol Registe� .................................................................................................................... 53

Fast Wake-up ........................................................................................................................ 54

Ope�ating Mode Swit�hing and Wake-up .............................................................................. 55

Stand�y Cu��ent Conside�ations ........................................................................................... 58

Wake-up ................................................................................................................................ 59

P�og�a��ing Conside�ations ................................................................................................ 59

Watchdog Timer ............................................................................................. 60

Wat�hdog Ti�e� Clo�k Sou��e .............................................................................................. �0

Wat�hdog Ti�e� Cont�ol Registe� ......................................................................................... �0

Wat�hdog Ti�e� Ope�ation ................................................................................................... �1

Reset and Initialisation .................................................................................. 62

Reset Ove�view ..................................................................................................................... ��

Reset Fun�tions .................................................................................................................... �3

Reset Initial Conditions ......................................................................................................... �7

Input/Output Ports ......................................................................................... 77

Pull-high Resisto�s ................................................................................................................ 79

Po�t Wake-up ........................................................................................................................ 81

Po�t A Wake-up Pola�ity Cont�ol Registe� ............................................................................ 8�

I/O Po�t Cont�ol Registe�s ..................................................................................................... 83

Po�t A � Po�t D Powe� Sou��e Cont�ol Registe�s ................................................................... 84

I/O Pin St�u�tu�es .................................................................................................................. 8�

P�og�a��ing Conside�ations ................................................................................................ 8�

Timer Modules – TM ...................................................................................... 87

Int�odu�tion ........................................................................................................................... 87

TM Ope�ation ........................................................................................................................ 87

TM Clo�k Sou��e ................................................................................................................... 88

TM Inte��upts ......................................................................................................................... 88

TM Exte�nal Pins ................................................................................................................... 88

TM Input/Output Pin Cont�ol Registe�s ................................................................................. 89

P�og�a��ing Conside�ations ................................................................................................ 9�

Rev. 1.40 3 De�e��e� 01� �01�

HT68FB540/HT68FB550/HT68FB560

I/O Flash USB MCU with SPI

Compact Type TM – CTM .............................................................................. 93

Co�pa�t TM Ope�ation ......................................................................................................... 94

Co�pa�t Type TM Registe� Des��iption................................................................................ 94

Co�pa�t Type TM Ope�ating Modes .................................................................................... 98

Co�pa�e Mat�h Output Mode ............................................................................................... 98

Ti�e�/Counte� Mode ........................................................................................................... 100

PWM Output Mode .............................................................................................................. 101

Standard Type TM – STM ............................................................................ 104

Standa�d TM Ope�ation ....................................................................................................... 104

Standa�d Type TM Registe� Des��iption ............................................................................. 105

Standa�d Type TM Ope�ating Modes ...................................................................................11�

Co�pa�e Output Mode .........................................................................................................11�

Ti�e�/Counte� Mode ............................................................................................................113

Ti�e�/Counte� Mode ............................................................................................................114

PWM Output Mode ...............................................................................................................114

Single Pulse Mode ...............................................................................................................117

Captu�e Input Mode .............................................................................................................119

Serial Interface Module – SIM ..................................................................... 121

SPI Inte�fa�e ....................................................................................................................... 1�1

SPI Inte�fa�e Ope�ation ....................................................................................................... 1�1

SPI Registe�s ...................................................................................................................... 1��

SPI Co��uni�ation ............................................................................................................ 1�5

SPI Bus Ena�le/Disa�le ...................................................................................................... 1�7

SPI Ope�ation ...................................................................................................................... 1�8

E��o� Dete�tion .................................................................................................................... 1�9

I � C Inte�fa�e ........................................................................................................................ 1�9

I

C Bus Co��uni�ation ...................................................................................................... 134

I

C Bus Sta�t Signal ............................................................................................................. 135

I

C Bus Slave Add�ess ........................................................................................................ 135

I � C Bus Read/W�ite Signal .................................................................................................. 13�

I

C Bus Slave Add�ess A�knowledge Signal ....................................................................... 13�

I

C Bus Data and A�knowledge Signal ............................................................................... 13�

I

C Ti�e Out Fun�tion ......................................................................................................... 138

Serial Interface – SPIA ................................................................................. 138

SPIA Inte�fa�e Ope�ation .................................................................................................... 139

SPIA Registe�s .................................................................................................................... 140

SPIA Co��uni�ation .......................................................................................................... 14�

SPIA Bus Ena�le/Disa�le .................................................................................................... 144

SPIA Ope�ation ................................................................................................................... 145

E��o� Dete�tion .................................................................................................................... 14�

Peripheral Clock Output .............................................................................. 147

Pe�iphe�al Clo�k Ope�ation ................................................................................................. 147

Rev. 1.40

4 De�e��e� 01� �01�

HT68FB540/HT68FB550/HT68FB560

I/O Flash USB MCU with SPI

Rev. 1.40 5 De�e��e� 01� �01�

HT68FB540/HT68FB550/HT68FB560

I/O Flash USB MCU with SPI

Rev. 1.40

4 De�e��e� 01� �01�

HT68FB540/HT68FB550/HT68FB560

I/O Flash USB MCU with SPI

Interrupts ...................................................................................................... 148

Inte��upt Registe�s ............................................................................................................... 148

Inte��upt Ope�ation .............................................................................................................. 15�

Exte�nal Inte��upt ................................................................................................................. 153

USB Inte��upt ...................................................................................................................... 154

Se�ial Inte�fa�e Module Inte��upts – SIM Inte��upt .............................................................. 154

Se�ial Pe�iphe�al Inte�fa�e Inte��upt – SPIA Inte��upt .......................................................... 154

LVD Inte��upt ....................................................................................................................... 154

Multi-fun�tion Inte��upt ........................................................................................................ 154

TM Inte��upts ....................................................................................................................... 155

Inte��upt Wake-up Fun�tion ................................................................................................. 155

P�og�a��ing Conside�ations .............................................................................................. 155

Low Voltage Detector – LVD ....................................................................... 156

LVD Registe� ....................................................................................................................... 15�

LVD Ope�ation ..................................................................................................................... 157

USB Interface ............................................................................................... 157

Powe� Plane ........................................................................................................................ 158

USB Suspend Wake-Up Re�ote Wake-Up ........................................................................ 158

USB Inte�fa�e Ope�ation ..................................................................................................... 159

USB Inte�fa�e Registe�s ...................................................................................................... 1�0

Configuration Options

................................................................................. 177

Application Circuits ..................................................................................... 178

Instruction Set .............................................................................................. 179

Int�odu�tion ......................................................................................................................... 179

Inst�u�tion Ti�ing ................................................................................................................ 179

Moving and T�ansfe��ing Data ............................................................................................. 179

A�ith�eti� Ope�ations .......................................................................................................... 179

Logi�al and Rotate Ope�ations ............................................................................................ 180

B�an�hes and Cont�ol T�ansfe� ........................................................................................... 180

Bit Ope�ations ..................................................................................................................... 180

Ta�le Read Ope�ations ....................................................................................................... 180

Othe� Ope�ations ................................................................................................................. 180

Inst�u�tion Set Su��a�y ..................................................................................................... 181

Instruction Definition

................................................................................... 183

Package Information ................................................................................... 192

�0-pin SSOP (150�il) Outline Di�ensions ......................................................................... 193

�4-pin SSOP (150�il) Outline Di�ensions ......................................................................... 194

�8-pin SSOP (150�il) Outline Di�ensions ......................................................................... 195

SAW Type �0-pin (4��

×4

��) QFN Outline Di�ensions .................................................. 19�

48-pin LQFP (7��

×

7��) Outline Di�ensions .................................................................. 197

Rev. 1.40 5 De�e��e� 01� �01�

HT68FB540/HT68FB550/HT68FB560

I/O Flash USB MCU with SPI

Features

CPU Features

• Operating voltage :

V

DD

(MCU)

– f

SYS

= 4MHz/6MHz: 2.2V~5.5V

– f

SYS

= 12MHz: 2.7V~5.5V

V

DD

(USB mode)

– f

SYS

= 6MHz/12MHz: 3.3V~5.5V

– f

SYS

= 16MHz: 4.5V~5.5V

• Up to 0.25µs instruction cycle with 16MHz system clock at V

DD

= 5V

• Power down and wake-up functions to reduce power consumption

• Three oscillators:

External Crystal - HXT

Internal RC - HIRC

Internal 32kHz RC - LIRC

• Multi-mode operation: NORMAL, SLOW, IDLE and SLEEP

• 2 Compact type 10-bit Timer Module - CTM

• 1 Standard type 10-bit Timer Module - STM

• 1 Standard type 16-bit Timer Module - STM

• All instructions executed in one or two instruction cycles

• Table read instructions

• 62 powerful instructions

• Up to 12-level subroutine nesting

• Bit manipulation instruction

Peripheral Features

• Flash Program Memory: 4K×16~16K×16

• RAM Data Memory: 256×8~768×8

• USB 2.0 Full Speed compatible

• Up to 8 endpoints supported including endpoint 0

• All endpoints except endpoint 0 can support interrupt and bulk transfer

• All endpoints except endpoint 0 can be configured as 8, 16, 32, 64 bytes FIFO size

• Endpoint 0 support control transfer

• Endpoint 0 has 8 byte FIFO

• Support 3.3V LDO and internal UDP 1.5K ohm pull-up resistor

• Internal 12MHz RC OSC with 0.25% accuracy for all USB modes

• Watchdog Timer function

• Up to 37 bidirectional I/O lines

• Dual pin-shared external interrupts

• Multiple Timer Modules for time measurement, input capture, compare match output or PWM output or single pulse output function

• Serial Interface Modules with Dual SPI and I

2

C interfaces

• Single Serial SPI interface

• Low voltage reset function

Rev. 1.40

� De�e��e� 01� �01�

HT68FB540/HT68FB550/HT68FB560

I/O Flash USB MCU with SPI

Rev. 1.40 7 De�e��e� 01� �01�

HT68FB540/HT68FB550/HT68FB560

I/O Flash USB MCU with SPI

HT68FB540/HT68FB550/HT68FB560

I/O Flash USB MCU with SPI

• Low voltage detect function

• Wide range of available package types

• Flash program memory can be re-programmed up to 1,000,000 times

• Flash program memory data retenton > 10 years

• Support In System Programming function - ISP

General Description

The HT68FB540, HT68FB550 and HT68FB560 are Flash Memory I/O with USB type 8-bit high performance RISC architecture microcontrollers, designed for applications that interface directly to which require an USB interface. Offering users the convenience of Flash Memory multiprogramming features, these devices also include a wide range of functions and features. Other memory includes an area of RAM Data Memory.

Multiple and extremely flexible Timer Modules provide timing, pulse generation and PWM generation functions. Communication with the outside world is catered for by including fully integrated SPI, I

2

C and USB interface functions, three popular interfaces which provide designers with a means of easy communication with external peripheral hardware. Protective features such as an internal Watchdog

Timer, Low Voltage Reset and Low Voltage Detector coupled with excellent noise immunity and ESD protection ensure that reliable operation is maintained in hostile electrical environments. The external interrupt can be triggered with falling edges or both falling and rising edges.

A full choice of three oscillator functions are provided including two fully integrated system oscillators which requires no external components for their implementation. The ability to operate and switch dynamically between a range of operating modes using different clock sources gives users the ability to optimize microcontroller operation and minimize power consumption.

The inclusion of flexible I/O programming features along with many other features ensure that the devices will find specific excellent use in a wide range of application possibilities such as motor driving, industrial control, consumer products, subsystem controllers, etc.

The devices are fully supported by the Holtek range of fully functional development and programming tools, providing a means for fast and efficient product development cycles.

Rev. 1.40

� De�e��e� 01� �01� Rev. 1.40 7 De�e��e� 01� �01�

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HT68FB540/HT68FB550/HT68FB560

I/O Flash USB MCU with SPI

Selection Table

Part No.

Most features are common to all devices, the main feature distinguishing them are Program Memory capacity, I/O count, stack capacity and package types. The following table summarises the main features of each device.

4K

8K

1�K

×

1�

×

1�

×

1�

Data

Memory I/O

�5�

51�

7�8

×

8

×

8

×

8

17

�5

37

Ext.

Interrupt

Timer

Module

10-�it CTM

×

10-�it STM

×

1

1�-�it STM

×

1

10-�it CTM

×

10-�it STM

×

1

1�-�it STM

×

1

10-�it CTM

×

10-�it STM

×

1

1�-�it STM

×

1

SIM

(SPI/I

2

C) SPI Stack

8

8

1�

Package

�0QFN

�0/�4SSOP

�4/�8SSOP

48LQFP

�4/�8SSOP

48LQFP

Block Diagram

 ƒ

„

€

 

 ƒ

„

­

€









 







†  ‚ …

Rev. 1.40

8 De�e��e� 01� �01�

HT68FB540/HT68FB550/HT68FB560

I/O Flash USB MCU with SPI

Rev. 1.40 9 De�e��e� 01� �01�

HT68FB540/HT68FB550/HT68FB560

I/O Flash USB MCU with SPI

HT68FB540/HT68FB550/HT68FB560

I/O Flash USB MCU with SPI

Pin Assignment

HT68FB540

UDP/GPIO1

V33O

UBUS/PE1/VDD

HVDD

PE�

3

4

1

5

�0 19 18 17 1�

15

14

HT68FB540

20 QFN-A

13

1�

11

� 7 8 9 10

PA3/TCK�

PA�/TP3_1/OSC�

PA1/TP�_1/OSC1

PA0/TCK1/OCDSDA

PE0/VDDIO

PA7/INT0/SCSA

PA4/SDOA/TP0_0

UDN/GPIO0

UDP/GPIO1

V33O

UBUS/PE1/VDD

HVDD

PE�

VSS

RES/OCDSCK

1

3

4

7

8

5

9

10

�0

19

18

17

1�

15

14

13

1�

11

HT68FB540

20 SSOP-A

PA�/TCK0/SCKA

PA5/SDIA/TP1_0

PA3/TCK�

PA�/TP3_1/OSC�

PA1/TP�_1/OSC1

PA0/TCK1/OCDSDA

PE0/VDDIO

PB�/TCK3/SCK

PB1/SDI/SCL

PB0/SDO/SDA

PA4/SDOA/TP0_0

PE0/VDDIO

UDN/GPIO0

UDP/GPIO1

V33O

UBUS/PE1/VDD

HVDD

PE�

VSS

RES/OCDSCK

PB0/SDO/SDA

PB�/INT1/TP�_0

�1

�0

19

18

17

�4

�3

��

1�

15

14

13

HT68FB540

24 SSOP-A

10

11

1�

7

8

9

1

3

4

5

PA7/INT0/SCSA

PA�/TCK0/SCKA

PA5/SDIA/TP1_0

PA3/TCK�

PA�/TP3_1/OSC�

PA1/TP�_1/OSC1

PA0/TCK1/OCDSDA

PB5/PCK/TP3_0

PB4/TP0_1

PB3/SCS/TP1_1

PB�/TCK3/SCK

PB1/SDI/SCL

Rev. 1.40

8 De�e��e� 01� �01� Rev. 1.40 9 De�e��e� 01� �01�

HT68FB550

PA�/TCK0/SCKA

PA7/INT0/SCSA

UDN/GPIO0

UDP/GPIO1

V33O

UBUS/PE1/VDD

HVDD

PE�

VSS

RES/OCDSCK

PB0/SDO/SDA

PB1/SDI/SCL

�1

�0

19

18

17

�4

�3

��

1�

15

14

13

HT68FB550

24 SSOP-A

7

8

9

5

3

4

1

10

11

1�

PA5/SDIA/TP1_0

PA4/SDOA/TP0_0

PA3/TCK�

PA�/TP3_1/OSC�

PA1/TP�_1/OSC1

PA0/TCK1/OCDSDA

PE0/VDDIO

PB�/INT1/TP�_0

PB5/PCK/TP3_0

PB4/TP0_1

PB3/SCS/TP1_1

PB�/TCK3/SCK

HT68FB540/HT68FB550/HT68FB560

I/O Flash USB MCU with SPI

PA�/TCK0/SCKA

PA7/INT0/SCSA

UDN/GPIO0

UDP/GPIO1

V33O

UBUS/PE1/VDD

HVDD

PE�

VSS

RES/OCDSCK

PD0

PD1

PB0/SDO/SDA

PB1/SDI/SCL

7

8

5

9

10

11

1�

13

14

1

3

4

HT68FB550

28 SSOP-A

�8

�7

��

�5

�4

�3

��

�1

�0

19

18

17

1�

15

PA5/SDIA/TP1_0

PA4/SDOA/TP0_0

PA3/TCK�

PA�/TP3_1/OSC�

PA1/TP�_1/OSC1

PA0/TCK1/OCDSDA

PE0/VDDIO

PD3

PD�

PB�/INT1/TP�_0

PB5/PCK/TP3_0

PB4/TP0_1

PB3/SCS/TP1_1

PB�/TCK3/SCK

NC

UDN/GPIO0

UDP/GPIO1

V33O

UBUS/PE1/VDD

HVDD

PE�

VSS

RES/OCDSCK

NC

NC

NC

3

4

1

5

48 47 4� 45 44 43 4� 41

HT68FB550

48 LQFP-A

40 39 38 37

3�

35

34

33

8

9

7

10

11

1�

13 14 151� 17 18 19 �0 �1 �� �3 �4

3�

31

30

�9

�8

�7

��

�5

PA�/TP3_1/OSC�

PA1/TP�_1/OSC1

PA0/TCK1/OCDSDA

PE0/VDDIO

PD7

PD�

PD5

PD4

PD3

PD�

NC

PB�/INT1/TP�_0

HT68FB540/HT68FB550/HT68FB560

I/O Flash USB MCU with SPI

Rev. 1.40

10 De�e��e� 01� �01� Rev. 1.40 11 De�e��e� 01� �01�

HT68FB540/HT68FB550/HT68FB560

I/O Flash USB MCU with SPI

HT68FB540/HT68FB550/HT68FB560

I/O Flash USB MCU with SPI

HT68FB560

PA�/TCK0/SCKA

PA7/INT0/SCSA

UDN/GPIO0

UDP/GPIO1

V33O

UBUS/PE1/VDD

HVDD

PE�

VSS

RES/OCDSCK

PB0/SDO/SDA

PB1/SDI/SCL

�0

19

18

17

1�

�4

�3

��

�1

15

14

13

HT68FB560

24 SSOP-A

7

4

5

1

3

8

9

10

11

1�

PA5/SDIA/TP1_0

PA4/SDOA/TP0_0

PA3/TCK�

PA�/TP3_1/OSC�

PA1/TP�_1/OSC1

PA0/TCK1/OCDSDA

PE0/VDDIO

PB�/INT1/TP�_0

PB5/PCK/TP3_0

PB4/TP0_1

PB3/SCS/TP1_1

PB�/TCK3/SCK

PA�/TCK0/SCKA

PA7/INT0/SCSA

UDN/GPIO0

UDP/GPIO1

V33O

UBUS/PE1/VDD

HVDD

PE�

VSS

RES/OCDSCK

PD0

PD1

PB0/SDO/SDA

PB1/SDI/SCL

9

10

11

1�

7

8

5

13

14

1

3

4

HT68FB560

28 SSOP-A

�8

�7

��

�5

�4

�3

��

�1

17

1�

15

�0

19

18

PA5/SDIA/TP1_0

PA4/SDOA/TP0_0

PA3/TCK�

PA�/TP3_1/OSC�

PA1/TP�_1/OSC1

PA0/TCK1/OCDSDA

PE0/VDDIO

PD3

PD�

PB�/INT1/TP�_0

PB5/PCK/TP3_0

PB4/TP0_1

PB3/SCS/TP1_1

PB�/TCK3/SCK

PC7

UDN/GPIO0

UDP/GPIO1

V33O

UBUS/PE1/VDD

HVDD

PE�

VSS

RES/OCDSCK

PE3

PE4

PE5

7

8

5

3

4

1

48 47 4� 45 44 43 4� 41

HT68FB560

48 LQFP-A

40 39 38 37

3�

35

34

33

3�

31

30

�9

�8

9

10

11

1�

�7

��

13 14 151� 17 18 19 �0 �1 �� �3 �4

�5

PA�/TP3_1/OSC�

PA1/TP�_1/OSC1

PA0/TCK1/OCDSDA

PE0/VDDIO

PD7

PD�

PD5

PD4

PD3

PD�

PB7

PB�/INT1/TP�_0

Rev. 1.40

10 De�e��e� 01� �01� Rev. 1.40 11 De�e��e� 01� �01�

HT68FB540/HT68FB550/HT68FB560

I/O Flash USB MCU with SPI

Pin Description

The pins on these devices can be referenced by their Port name, e.g. PA.0, PA.1 etc, which refer to the digital I/O function of the pins. However these Port pins are also shared with other function such as the Serial Port pins etc. The function of each pin is listed in the following table, however the details behind how each pin is configured is contained in other sections of the datasheet.

HT68FB540

Pin Name Function

PA0

PA0/TCK1/

OCDSDA

TCK1

OCDSDA

PA1/TP�_1/

OSC1

PA�/TP3_1/

OSC�

PA3/TCK�

PA4/SDOA/

TP0_0

PA5/SDIA/

TP1_0

PA�/TCK0/

SCKA

PA7/INT0/SCSA

PB0/SDO/SDA

PB1/SDI/SCL

PA1

TP�_1

OSC1

PA�

TP3_1

OSC�

PA3

TCK�

PA4

SDOA

TP0_0

PA5

SDIA

TP1_0

PA�

TCK0

SCKA

PA7

INT0

SCSA

PB0

SDO

SDA

PB1

SDI

SCL

OPT

PAPU

PAWU

PAPU

PAWU

TMPC1

PAPU

PAWU

TMPC1

PAPU

PAWU

PAPU

PAWU

TMPC0

PAPU

PAWU

TMPC0

PAPU

PAWU

PAPU

PAWU

PXPU

PXWU

PXPU

PXWU

I/T O/T Description

ST CMOS Gene�al pu�pose I/O. Registe� ena�led pull-up and wake-up.

ST — TM1 input

ST CMOS Gene�al pu�pose I/O. Registe� ena�led pull-up and wake-up.

ST CMOS TM� I/O

HXT — HXT pin

ST CMOS Gene�al pu�pose I/O. Registe� ena�led pull-up and wake-up.

ST CMOS TM3 I/O

— HXT HXT pin

ST CMOS Gene�al pu�pose I/O. Registe� ena�led pull-up and wake-up.

ST — TM� input

ST CMOS Gene�al pu�pose I/O. Registe� ena�led pull-up and wake-up.

— CMOS SPIA Data output

ST CMOS TM0 I/O

ST CMOS Gene�al pu�pose I/O. Registe� ena�led pull-up and wake-up.

ST — SPIA Data input

ST CMOS TM1 I/O

ST CMOS Gene�al pu�pose I/O. Registe� ena�led pull-up and wake-up.

ST — TM0 input

ST NMOS SPIA Se�ial Clo�k

ST CMOS Gene�al pu�pose I/O. Registe� ena�led pull-up and wake-up.

ST — Exte�nal inte��upt 0

ST CMOS SPIA Slave sele�t

ST CMOS Gene�al pu�pose I/O. Registe� ena�led pull-up and wake-up.

— CMOS SPI Data output

ST NMOS I � C Data

ST CMOS Gene�al pu�pose I/O. Registe� ena�led pull-up and wake-up.

ST — SPI Data input

ST NMOS I

C Clo�k

Rev. 1.40

1� De�e��e� 01� �01�

HT68FB540/HT68FB550/HT68FB560

I/O Flash USB MCU with SPI

Rev. 1.40 13 De�e��e� 01� �01�

HT68FB540/HT68FB550/HT68FB560

I/O Flash USB MCU with SPI

Rev. 1.40

1� De�e��e� 01� �01�

HT68FB540/HT68FB550/HT68FB560

I/O Flash USB MCU with SPI

Pin Name

PB�/TCK3/SCK

PB3/SCS/TP1_1

PB4/TP0_1

PB5/PCK/TP3_0

PB�/INT1/TP�_0

PE0/VDDIO

VDD/PE1/UBUS

PE�

Function

PB�

TCK3

SCK

PB3

SCS

TP1_1

PB4

TP0_1

PB5

PCK

TP3_0

PB�

INT1

TP�_0

PE0

VDDIO

VDD

PE1

UBUS

PE�

RES

PXPU

PXWU

TMPC1

PXPU

PXWU

TMPC1

PXPU

PXWU

OPT

PXPU

PXWU

TMPC1

PXPU

PXWU

TMPC0

PXPU

PXWU

TMPC0

PXPU

PXWU

RES/OCDSCK

OCDSCK —

I/T O/T Description

ST CMOS Gene�al pu�pose I/O. Registe� ena�led pull-up and wake-up.

ST — TM3 input

ST CMOS SPI Se�ial Clo�k

ST CMOS Gene�al pu�pose I/O. Registe� ena�led pull-up and wake-up.

ST CMOS SPI Slave sele�t

ST CMOS TM1 I/O

ST CMOS Gene�al pu�pose I/O. Registe� ena�led pull-up and wake-up.

ST CMOS TM0 I/O

ST CMOS Gene�al pu�pose I/O. Registe� ena�led pull-up and wake-up.

— CMOS Pe�iphe�al output �lo�k

ST CMOS TM3 I/O

ST CMOS Gene�al pu�pose I/O. Registe� ena�led pull-up and wake-up.

ST — Exte�nal inte��upt 1

ST CMOS TM� I/O

ST CMOS Gene�al pu�pose I/O. Registe� ena�led pull-up and wake-up.

PWR

PWR

ST

PWR

PA exte�nal powe� input

Powe� supply

Gene�al pu�pose I/O� Input pin

USB SIE VDD

ST CMOS Gene�al pu�pose I/O. Registe� ena�led pull-up and wake-up.

UDN/GPIO0

UDP/GPIO1

VSS

V33O

HVDD

UDN

GPIO0

UDP

GPIO1

VSS

V33O

HVDD

ST — Reset input

ST —

De�ug �lo�k input in On-Chip De�ug Suppo�t �ode fo� OCDS

EV only

ST CMOS USB UDN line

ST CMOS Gene�al pu�pose I/O

ST CMOS USB UDP line

ST CMOS Gene�al pu�pose I/O

PWR

PWR

— G�ound

PWR 3.3V �egulato� output

— HIRC os�illato� Positive Powe� supply.

Note: I/T: Input type O/T: Output type

OPT: Optional by configuration option (CO) or register option

PWR: Power

ST: Schmitt Trigger input

CO: Configuration option

CMOS: CMOS output

HXT: High frequency crystal oscillator

Where devices exist in more than one package type the table reflects the situation for the package with the largest number of pins. For this reason not all pins described in the table may exist on all package types.

Rev. 1.40 13 De�e��e� 01� �01�

HT68FB540/HT68FB550/HT68FB560

I/O Flash USB MCU with SPI

TCK0

SCKA

PA7

INT0

SCSA

PB0

SDO

SDA

PB1

SDI

SCL

PB�

TCK3

SCK

SDOA

TP0_0

PA5

SDIA

TP1_0

PA�

PA1

TP�_1

OSC1

PA�

TP3_1

OSC�

PA3

TCK�

PA4

HT68FB550

Pin Name Function

PA0

PA0/TCK1/

OCDSDA

TCK1

OCDSDA

PA1/TP�_1/

OSC1

PA�/TP3_1/

OSC�

PA3/TCK�

PA4/SDOA/

TP0_0

PA5/SDIA/

TP1_0

PA�/TCK0/

SCKA

PA7/INT0/

SCSA

PB0/SDO/

SDA

PB1/SDI/SCL

PB�/TCK3/

SCK

OPT

PAPU

PAWU

PXPU

PXWU

PXPU

PXWU

TMPC0

PAPU

PAWU

PAPU

PAWU

PAPU

PAWU

TMPC1

PAPU

PAWU

TMPC1

PAPU

PAWU

PAPU

PAWU

TMPC0

PAPU

PAWU

PXPU

PXWU

TMPC1

I/T

ST

ST

ST

ST

ST

ST

ST

ST

ST

ST

ST

ST

ST

ST

ST

ST

ST

ST

ST

ST

ST

ST

ST

ST

O/T

CMOS Gene�al pu�pose I/O. Registe� ena�led pull-up and wake-up.

CMOS TM3 I/O

HXT HXT pin

CMOS Gene�al pu�pose I/O. Registe� ena�led pull-up and wake-up.

— TM� input

CMOS Gene�al pu�pose I/O. Registe� ena�led pull-up and wake-up.

CMOS SPIA Data output

CMOS TM0 I/O

CMOS Gene�al pu�pose I/O. Registe� ena�led pull-up and wake-up.

— SPIA Data input

CMOS TM1 I/O

CMOS Gene�al pu�pose I/O. Registe� ena�led pull-up and wake-up.

TM1 input

TM0 input

NMOS SPIA Se�ial Clo�k

CMOS Gene�al pu�pose I/O. Registe� ena�led pull-up and wake-up.

Exte�nal inte��upt 0

CMOS SPIA Slave sele�t

CMOS Gene�al pu�pose I/O. Registe� ena�led pull-up and wake-up.

— SPI Data input

NMOS I � C Clo�k

CMOS Gene�al pu�pose I/O. Registe� ena�led pull-up and wake-up.

— TM3 input

CMOS SPI Se�ial Clo�k

Description

CMOS Gene�al pu�pose I/O. Registe� ena�led pull-up and wake-up.

ST

ST

HXT

CMOS Gene�al pu�pose I/O. Registe� ena�led pull-up and wake-up

CMOS TM� I/O

— HXT pin

ST

ST

CMOS Gene�al pu�pose I/O. Registe� ena�led pull-up and wake-up.

CMOS SPI Data output

NMOS I

C Data

Rev. 1.40

14 De�e��e� 01� �01�

HT68FB540/HT68FB550/HT68FB560

I/O Flash USB MCU with SPI

Rev. 1.40 15 De�e��e� 01� �01�

HT68FB540/HT68FB550/HT68FB560

I/O Flash USB MCU with SPI

Rev. 1.40

14 De�e��e� 01� �01�

HT68FB540/HT68FB550/HT68FB560

I/O Flash USB MCU with SPI

Pin Name

PB3/SCS/

TP1_1

PB4/TP0_1

PB5/PCK/

TP3_0

Function

PB3

SCS

TP1_1

PB4

TP0_1

PB5

PCK

TP3_0

PB�

INT1

TP�_0

OPT

PXPU

PXWU

TMPC0

PXPU

PXWU

TMPC0

PXPU

PXWU

TMPC1

PXPU

PXWU

TMPC1

I/T

ST

ST

ST

ST

ST

ST

ST

ST

O/T Description

CMOS Gene�al pu�pose I/O. Registe� ena�led pull-up and wake-up.

CMOS SPI Slave sele�t

CMOS TM1 I/O

CMOS Gene�al pu�pose I/O. Registe� ena�led pull-up and wake-up.

CMOS TM0 I/O

CMOS Gene�al pu�pose I/O. Registe� ena�led pull-up and wake-up.

CMOS Pe�iphe�al output �lo�k.

CMOS TM3 I/O

CMOS Gene�al pu�pose I/O. Registe� ena�led pull-up and wake-up.

PB�/ INT1/

TP�_0 ST

ST

ST

— Exte�nal inte��upt 1

CMOS TM� I/O

CMOS Gene�al pu�pose I/O. Registe� ena�led pull-up and wake-up.

PD0~PD7

PE0/VDDIO

VDD/PE1/

UBUS

PE�

PE0

VDDIO

VDD

PE1

UBUS

PE�

PXPU

PXWU

PXPU

PXWU

ST

PWR

PWR

ST

PWR

ST

CMOS Gene�al pu�pose I/O. Registe� ena�led pull-up and wake-up.

PA� PD4~PD7 exte�nal powe� input.

Powe� supply

Gene�al pu�pose I/O� Input pin

USB SIE VDD

CMOS Gene�al pu�pose I/O. Registe� ena�led pull-up and wake-up.

RES/OCDSCK

UDN/GPIO0

UDP/GPIO1

VSS

V33O

HVDD

RES

OCDSCK

UDN

GPIO0

UDP

GPIO1

VSS

V33O

HVDD

ST

ST

ST

ST

ST

ST

PWR

PWR

— Reset input

De�ug �lo�k input in On-Chip De�ug Suppo�t �ode fo� OCDS

EV only

CMOS USB UDN line.

CMOS Gene�al pu�pose I/O

CMOS USB UDP line

CMOS Gene�al pu�pose I/O

— G�ound

PWR 3.3V �egulato� output

— HIRC os�illato� Positive Powe� supply.

Note: I/T: Input type O/T: Output type

OPT: Optional by configuration option (CO) or register option

PWR: Power

ST: Schmitt Trigger input

CO: Configuration option

CMOS: CMOS output

HXT: High frequency crystal oscillator

Where devices exist in more than one package type the table reflects the situation for the package with the largest number of pins. For this reason not all pins described in the table may exist on all package types.

Rev. 1.40 15 De�e��e� 01� �01�

HT68FB540/HT68FB550/HT68FB560

I/O Flash USB MCU with SPI

TCK0

SCKA

PA7

INT0

SCSA

PB0

SDO

SDA

PB1

SDI

SCL

PB�

TCK3

SCK

SDOA

TP0_0

PA5

SDIA

TP1_0

PA�

PA1

TP�_1

OSC1

PA�

TP3_1

OSC�

PA3

TCK�

PA4

HT68FB560

Pin Name Function

PA0

PA0/TCK1/

OCDSDA

TCK1

OCDSDA

PA1/TP�_1/

OSC1

PA�/TP3_1/

OSC�

PA3/TCK�

PA4/SDOA/

TP0_0

PA5/SDIA/

TP1_0

PA�/TCK0/

SCKA

PA7/INT0/

SCSA

PB0/SDO/SDA

PB1/SDI/SCL

PB�/TCK3/

SCK

OPT

PAPU

PAWU

PXPU

PXWU

PXPU

PXWU

TMPC0

PAPU

PAWU

PAPU

PAWU

PAPU

PAWU

TMPC1

PAPU

PAWU

TMPC1

PAPU

PAWU

PAPU

PAWU

TMPC0

PAPU

PAWU

PXPU

PXWU

TMPC1

I/T

ST

ST

ST

ST

ST

ST

ST

ST

ST

ST

ST

ST

ST

ST

ST

ST

ST

ST

ST

ST

ST

ST

ST

ST

O/T

CMOS Gene�al pu�pose I/O. Registe� ena�led pull-up and wake-up.

CMOS TM3 I/O

HXT HXT pin

CMOS Gene�al pu�pose I/O. Registe� ena�led pull-up and wake-up.

— TM� input

CMOS Gene�al pu�pose I/O. Registe� ena�led pull-up and wake-up.

CMOS SPIA Data output

CMOS TM0 I/O

CMOS Gene�al pu�pose I/O. Registe� ena�led pull-up and wake-up.

— SPIA Data input

CMOS TM1 I/O

CMOS Gene�al pu�pose I/O. Registe� ena�led pull-up and wake-up.

TM0 input

NMOS SPIA Se�ial Clo�k

CMOS Gene�al pu�pose I/O. Registe� ena�led pull-up and wake-up.

Exte�nal inte��upt 0

CMOS SPIA Slave sele�t

CMOS Gene�al pu�pose I/O. Registe� ena�led pull-up and wake-up.

— SPI Data input

NMOS I � C Clo�k

CMOS Gene�al pu�pose I/O. Registe� ena�led pull-up and wake-up.

— TM3 input

CMOS SPI Se�ial Clo�k

Description

CMOS Gene�al pu�pose I/O. Registe� ena�led pull-up and wake-up.

— TM1 input

fo� OCDS

ST

ST

HXT

CMOS Gene�al pu�pose I/O. Registe� ena�led pull-up and wake-up.

CMOS TM� I/O

— HXT pin

ST

ST

CMOS Gene�al pu�pose I/O. Registe� ena�led pull-up and wake-up.

CMOS SPI Data output

NMOS I

C Data

Rev. 1.40

1� De�e��e� 01� �01�

HT68FB540/HT68FB550/HT68FB560

I/O Flash USB MCU with SPI

Rev. 1.40 17 De�e��e� 01� �01�

HT68FB540/HT68FB550/HT68FB560

I/O Flash USB MCU with SPI

Rev. 1.40

1� De�e��e� 01� �01�

HT68FB540/HT68FB550/HT68FB560

I/O Flash USB MCU with SPI

Pin Name

PB3/SCS/

TP1_1

PB4/TP0_1

PB5/PCK/

TP3_0

PB�/INT1/

TP�_0

PB7

PC0~PC7

Function

PB3

SCS

TP1_1

PB4

TP0_1

PB5

PCK

TP3_0

PB�

INT1

TP�_0

PB7

OPT

PXPU

PXWU

TMPC0

PXPU

PXWU

TMPC0

PXPU

PXWU

TMPC1

PXPU

PXWU

TMPC1

PXPU

PXWU

ST

ST

ST

I/T

ST

ST

ST

ST

ST

ST

ST

ST

ST

O/T Description

CMOS Gene�al pu�pose I/O. Registe� ena�led pull-up and wake-up.

CMOS SPI Slave sele�t

CMOS TM1 I/O

CMOS Gene�al pu�pose I/O. Registe� ena�led pull-up and wake-up.

CMOS TM0 I/O

CMOS Gene�al pu�pose I/O. Registe� ena�led pull-up and wake-up.

CMOS Pe�iphe�al output �lo�k

CMOS TM3 I/O

CMOS Gene�al pu�pose I/O. Registe� ena�led pull-up and wake-up.

— Exte�nal inte��upt 1

CMOS TM� I/O

CMOS Gene�al pu�pose I/O. Registe� ena�led pull-up and wake-up.

CMOS Gene�al pu�pose I/O. Registe� ena�led pull-up and wake-up.

PD0~PD7 ST CMOS Gene�al pu�pose I/O. Registe� ena�led pull-up and wake-up.

PE0/VDDIO

VDD/PE1/

UBUS

PE0

VDDIO

VDD

PE1

UBUS

PXPU

PXWU

ST

PWR

PWR

ST

PWR

CMOS Gene�al pu�pose I/O. Registe� ena�led pull-up and wake-up.

PA� PD4~PD7 exte�nal powe� input

Powe� supply.

Gene�al pu�pose I/O� Input pin

USB SIE VDD

PE�~PE5 ST CMOS Gene�al pu�pose I/O. Registe� ena�led pull-up and wake-up.

RES/OCDSCK

UDN/GPIO0

UDP/GPIO1

VSS

V33O

HVDD

RES

OCDSCK

UDN

GPIO0

UDP

GPIO1

VSS

V33O

HVDD

ST

ST

ST

ST

ST

ST

PWR

PWR

— Reset input

De�ug �lo�k input in On-Chip De�ug Suppo�t �ode fo� OCDS

EV only

CMOS USB UDN line

CMOS Gene�al pu�pose I/O.

CMOS USB UDP line

CMOS Gene�al pu�pose I/O.

— G�ound

PWR 3.3V �egulato� output

— HIRC os�illato� Positive Powe� supply.

Note: I/T: Input type O/T: Output type

OPT: Optional by configuration option (CO) or register option

PWR: Power

ST: Schmitt Trigger input

CO: Configuration option

CMOS: CMOS output

HXT: High frequency crystal oscillator

Where devices exist in more than one package type the table reflects the situation for the package with the largest number of pins. For this reason not all pins described in the table may exist on all package types.

Rev. 1.40 17 De�e��e� 01� �01�

HT68FB540/HT68FB550/HT68FB560

I/O Flash USB MCU with SPI

Absolute Maximum Ratings

Supply Voltage ........................

V

SS

-0.3V to V

SS

+6.0V

Input Voltage ...........................

V

SS

-0.3V to V

DD

+0.3V

I

OL

Total .............................................................150mA

Total Power Dissipation ....................................500mV

Storage Temperature .......................... -50°C to 125°C

Operating Temperature ........................ -40°C to 85°C

I

OH

Total ........................................................... -100mA

Note: These are stress ratings only. Stresses exceeding the range specified under "Absolute Maximum Ratings" may cause substantial damage to the device. Functional operation of this device at other conditions beyond those listed in the specification is not implied and prolonged exposure to extreme conditions may affect device reliability.

D.C. Characteristics

I

I

I

I

I

Symbol

V

V

DD1

DD�

DD1

DD�

DD3

DD4

DD5

Parameter

Ope�ating Voltage

(C�ystal OSC)

Ope�ating Voltage (High

F�equen�y Inte�nal RC OSC)

Ope�ating Cu��ent

(C�ystal OSC� f

(HIRC OSC� f

SYS

Ope�ating Cu��ent

SYS

=f

Ope�ating Cu��ent

(C�ystal OSC� f

SYS

=f

H

H

� f

=f

H

� f

S

S

=f

� f

S

=f

LIRC

=f

LIRC

)

LIRC

)

)

Ope�ating Cu��ent

(HIRC OSC� f

SYS

=f

H

� f

S

=f

LIRC

)

Ope�ating Cu��ent

(LIRC OSC� f

SYS

=f

L

=f

LIRC

� f

S

=f

LIRC

)

V

DD

Test Conditions

Conditions

f

SYS

=4MHz f

SYS

=�MHz f

SYS

=8MHz f

SYS

=1�MHz f

SYS

=1�MHz

— f

SYS

=1�MHz

3V No load� f

5V

H

=4MHz�

WDT ena�le

3V No load� f

5V

H

=�MHz�

WDT ena�le

3V No load� f

5V

H

=8MHz�

WDT ena�le

3V No load� f

5V

H

=1�MHz�

WDT ena�le

3V No load� f

5V

H

=1�MHz�

WDT ena�le

3V No load� ADC off� f

5V

LIRC

=3�kHz�

WDT ena�le� LVR ena�le

3V No load� f

H

=1�MHz� WDT ena�le� USB ena�le� PLL on�

5V

V33O on

5V No load� f

H

=�MHz� WDT ena�le�

USB ena�le� PLL on� V33O on

5V

No load� f

H

=1�MHz� WDT ena�le� USB ena�le� PLL on�

V33O on

5V

No load� f

V33O on

H

=1�MHz� WDT ena�le� USB ena�le� PLL on�

Min.

�.�

�.�

�.�

�.7

4.5

�.7

Ta= 25°C

Unit

V

V

V

V

V

V

�A

�A

�A

�A

�A

�A

�A

�A

�A

�A

μA

μA

�A

�A

�A

Max.

5.5

5.5

5.5

5.5

5.5

5.5

1.5

4.0

�.0

5.0

3.0

5.5

4.0

7.0

4.0

7.0

80

150

10.0

1�

15

Typ.

0.8

1.8

1.0

�.5

1.3

3.0

�.0

4.0

�.0

4.0

40

70

5.5

11

10

11

1�

1�

17

�A

�A

Rev. 1.40

18 De�e��e� 01� �01�

HT68FB540/HT68FB550/HT68FB560

I/O Flash USB MCU with SPI

Rev. 1.40 19 De�e��e� 01� �01�

HT68FB540/HT68FB550/HT68FB560

I/O Flash USB MCU with SPI

Rev. 1.40

18 De�e��e� 01� �01�

HT68FB540/HT68FB550/HT68FB560

I/O Flash USB MCU with SPI

I

I

I

I

I

I

I

I

I

Symbol

STB1

STB�

STB3

STB4

STB5

SUS1

SUS�

V

V

V

V

OL

OH

V

R

R

R

IL1

IH1

IL�

IH�

V33O

UDP

PH

PL f f

Parameter

Stand�y Cu��ent (Idle 1)

(C�ystal o� HIRC OSC� f

SYS

=f

H

� f

S

=f

LIRC

)

Stand�y Cu��ent (Idle 0)

(C�ystal o� HIRC OSC� f

SYS

=off� f

S

=f

LIRC

)

Stand�y Cu��ent (Idle 0)

(LIRC OSC� f

=f

SYS

LIRC

)

=off� f

S

=f

LIRC

)

Stand�y Cu��ent (Sleep 0)

(C�ystal o� HIRC OSC�

SYS

=off� f

S

=f

LIRC

)

Stand�y Cu��ent (Sleep 0)

(C�ystal o� HIRC OSC� f

SYS

=off� f

S

=f

LIRC

)

Suspend Cu��ent (Sleep 0)

(C�ystal o� HIRC OSC�

SYS

=off� f

S f

Suspend Cu��ent (Sleep 0)

(C�ystal o� HIRC OSC�

SYS

=off� f

S

=f

LIRC

)

Input Low Voltage fo� I/O Po�ts�

TCK and INT

Input High Voltage fo� I/O Po�ts�

TCK and INT

Input Low Voltage (RES)

Input High Voltage (RES)

I/O Po�t Sink Cu��ent

I/O Po�t� Sou��e Cu��ent

V

DD

Test Conditions

Conditions

3V No load� syste� HALT�

WDT ena�le� os�illato� on

5V

(FSYSON=1)

3V No load� syste� HALT�

WDT ena�le� os�illato� off

5V

(FSYSON=0)

3V No load� syste� HALT�

5V

WDT ena�le

3V No load� syste� HALT�

5V

WDT disa�le

5V

5V

No load� syste� HALT� WDT disa�le� LVR ena�le and

LVDEN=1

No load� syste� HALT� WDT disa�le� USB t�ans�eive�� 3.3V

Regulato� on and �l� suspend�

(UCC.4)

No load� syste� HALT� WDT disa�le� USB t�ans�eive�� 3.3V

Regulato� on and set suspend�

(UCC.4)

3V V

OL

=0.1V

DD

5V V

OL

=0.1V

DD

3V V

OH

=0.9V

DD

5V V

OH

=0.9V

DD

5V I

V33O

=70�A

3.3V Regulato� Output

Pull-high Resistan�e of UDP to

V33O

Pull-high Resistan�e of I/O

Po�ts

Pull-low Resistan�e of UBUS

Pin

3.3V

3V

5V

5V SUSP�=1� RUBUS=0

Min.

0

0.8V

DD

0

0.9V

DD

4

10

-�

-5

3.0

-5%

�0

10

0.5

Typ.

�0

3�0

�40

0.8

1.5

1.5

3.0

1.5

3.0

0.1

0.3

-4

-10

3.3

8

�0

1.5

�0

30

1

Max.

90

4�0

3�0

0.�V

DD

V

DD

0.4V

DD

V

DD

3.�

+5%

100

50

1.5

1.5

3.0

3.0

�.0

3.0

�.0

1.0

�.0

Unit

μA

μA

μA

V

�A

�A

μA

μA

μA

μA

μA

μA

V

V

V

�A

�A

�A

�A

V kΩ kΩ kΩ

Rev. 1.40 19 De�e��e� 01� �01�

HT68FB540/HT68FB550/HT68FB560

I/O Flash USB MCU with SPI

A.C. Characteristics

Ta= 25°C t f f f t t t t t f

Symbol

SYS1

SYS�

LIRC

TIMER

BGS

TIMER

RES

INT

SST

RSTD

Parameter

Syste� Clo�k (C�ystal OSC)

Syste� Clo�k (HIRC OSC)

Syste� Clo�k (3�K RC)

�.�~5.5V Non-USB �ode� Ta=�5°C

3.0~5.5V Non-USB �ode� Ta= -40~85°C

-3%

-�%

1�

1�

+3%

+�%

MHz

MHz

�.�~5.5V Non-USB �ode� Ta=-40~85°C -10%

3.3~5.5V USB �ode

1� +10% MHz

-0.�5% 1� +0.�5% MHz

5V Ta= �5°C

�.�~5.5V Ta= -40°C to 85°C

�.�~5.5V

�.7~5.5V

-10%

-50%

3�

3�

+10%

+�0%

8

1� kHz kHz

MHz

MHz Ti�e� I/P F�equen�y (TMR)

VBG Tu�n on Sta�le Ti�e

TCKn Input Pin Mini�u� Pulse

Width

Exte�nal Reset Mini�u� Low

Pulse Width

Inte��upt Mini�u� Pulse Width

4.5~5.5V

10

0.3

10

10

1�

MHz

�s

μs

μs

μs

Syste� Sta�t-up Ti�e� Pe�iod

(Wake-up f�o� HALT� f

SYS

off at HALT state� Slow Mode

No��al Mode)

— f

SYS

=HXT (Slow Mode → No�-

�al Mode (HXT)) f

SYS

=HXT (Wake-up f�o�

HALT� f

SYS

off at HALT state) f

SYS

=HIRC f

SYS

=LIRC

10�4

10�4

10�4

— t t t t

SYS

SYS

SYS

SYS

Syste� Sta�t-up Ti�e� Pe�iod

(Wake-up f�o� HALT� f

SYS

on at

HALT state)

Syste� Sta�t-up Ti�e� Pe�iod

(Reset)

Syste� Reset Delay Ti�e

(Powe� On Reset)

Syste� Reset Delay Ti�e

(Any Reset ex�ept Powe� On

Reset)

V

DD

�.�~5.5V

�.�~5.5V

�.�~5.5V

�.7~5.5V

4.5~5.5V

Condition

Min.

10�4

�5

8.3

Typ. Max.

— 4

1�

1�

8

50

1�.7

100

33.3

Unit

MHz

MHz

MHz

MHz

MHz t t

SYS

SYS

�s

�s

Rev. 1.40

�0 De�e��e� 01� �01�

HT68FB540/HT68FB550/HT68FB560

I/O Flash USB MCU with SPI

Rev. 1.40 �1 De�e��e� 01� �01�

HT68FB540/HT68FB550/HT68FB560

I/O Flash USB MCU with SPI

Rev. 1.40

�0 De�e��e� 01� �01�

HT68FB540/HT68FB550/HT68FB560

I/O Flash USB MCU with SPI

LVD & LVR Electrical Characteristics

t t t t

I

Symbol

V

LVD3

V

LVD4

V

LVD5

V

LVD�

V

LVD7

V

LVD8

V

LVR1

V

LVR�

V

LVR3

V

LVR4

V

LVD1

V

LVD�

Parameter

Low Voltage Reset Voltage

Low Voltage Dete�to� Voltage

LVD

LVR

LVD

SRESET

LVDS

Additional Powe� Consu�ption if LVD/LVR is Used

Low Voltage Width to Reset

Low Voltage Width to Inte��upt

Softwa�e Reset Width to Reset

LVDO Sta�le Ti�e

V

DD

3V

5V

Test Conditions

Conditions

LVR Ena�le� �.1V option

LVR Ena�le� �.55V option

LVR Ena�le� 3.15V option

LVR Ena�le� 3.8V option

LVDEN=1� V

LVD

=�.0V

LVDEN=1� V

LVD

=�.�V

LVDEN=1� V

LVD

=�.4V

LVDEN=1� V

LVD

=�.7V

LVDEN=1� V

LVD

=3.0V

LVDEN=1� V

LVD

=3.3V

LVDEN=1� V

LVD

=3.�V

LVDEN=1� V

LVD

=4.0V

LVD disa�le

LVD ena�le

(LVR ena�le)

Fo� LVR ena�le� LVD off → on

Ta= 25°C

Min.

1�0

�0

45

15

-5%

×Typ.

-5%

×Typ.

3.�

4.0

30

�0

�.4

�.7

3.0

3.3

�40

45

90

�.1

�.55

3.15

3.8

�.0

�.�

Typ. Max. Unit

+5%

×Typ.

+5%

×Typ.

45

90

480

90

1�0

V

V

μA

μA

V

V

V

V

μs

μs

μs

μs

V

V

V

V

V

V

Power on Reset (AC+DC) Electrical Characteristics

t

Symbol

V

POR

RR

POR

VDD

Parameter

V

DD

Sta�t Voltage to ensu�e

Powe�-on Reset

V

DD

Rise Rate to ensu�e

Powe�-on Reset

Mini�u� Ti�e fo� V

DD

Stays at

V

POR

to Ensu�e Powe�-on Reset

VDD

Condition

Min.

0.035

1

Typ.

Max.

Ta= 25°C

Unit

100 �V

V/�s

�s

Rev. 1.40 �1 De�e��e� 01� �01�

HT68FB540/HT68FB550/HT68FB560

I/O Flash USB MCU with SPI

System Architecture

A key factor in the high-performance features of the Holtek range of microcontrollers is attributed to their internal system architecture. The range of devices take advantage of the usual features found within RISC microcontrollers providing increased speed of operation and enhanced performance.

The pipelining scheme is implemented in such a way that instruction fetching and instruction execution are overlapped, hence instructions are effectively executed in one cycle, with the exception of branch or call instructions. An 8-bit wide ALU is used in practically all instruction set operations, which carries out arithmetic operations, logic operations, rotation, increment, decrement, branch decisions, etc. The internal data path is simplified by moving data through the Accumulator and the ALU. Certain internal registers are implemented in the Data Memory and can be directly or indirectly addressed. The simple addressing methods of these registers along with additional architectural features ensure that a minimum of external components is required to provide a functional I/O control system with maximum reliability and flexibility. This makes the device suitable for low-cost, high-volume production for controller applications.

Clocking and Pipelining

The main system clock, derived from either a HXT, HIRC or LIRC oscillator is subdivided into four internally generated non-overlapping clocks, T1~T4. The Program Counter is incremented at the beginning of the T1 clock during which time a new instruction is fetched. The remaining T2~T4 clocks carry out the decoding and execution functions. In this way, one T1~T4 clock cycle forms one instruction cycle. Although the fetching and execution of instructions takes place in consecutive instruction cycles, the pipelining structure of the microcontroller ensures that instructions are effectively executed in one instruction cycle. The exception to this are instructions where the contents of the Program Counter are changed, such as subroutine calls or jumps, in which case the instruction will take one more instruction cycle to execute.

For instructions involving branches, such as jump or call instructions, two machine cycles are required to complete instruction execution. An extra cycle is required as the program takes one cycle to first obtain the actual jump or call address and then another cycle to actually execute the branch. The requirement for this extra cycle should be taken into account by programmers in timing sensitive applications.





   

    

System Clocking and Pipelining

Rev. 1.40

�� De�e��e� 01� �01�

HT68FB540/HT68FB550/HT68FB560

I/O Flash USB MCU with SPI

Rev. 1.40 �3 De�e��e� 01� �01�

HT68FB540/HT68FB550/HT68FB560

I/O Flash USB MCU with SPI

HT68FB540/HT68FB550/HT68FB560

I/O Flash USB MCU with SPI

   



   

 



Instruction Fetching

Program Counter

During program execution, the Program Counter is used to keep track of the address of the next instruction to be executed. It is automatically incremented by one each time an instruction is executed except for instructions, such as "JMP" or "CALL" that demand a jump to a nonconsecutive Program Memory address. Only the lower 8 bits, known as the Program Counter Low

Register, are directly addressable by the application program.

When executing instructions requiring jumps to non-consecutive addresses such as a jump instruction, a subroutine call, interrupt or reset, etc., the microcontroller manages program control by loading the required address into the Program Counter. For conditional skip instructions, once the condition has been met, the next instruction, which has already been fetched during the present instruction execution, is discarded and a dummy cycle takes its place while the correct instruction is obtained.

Device

HT�8FB540

HT�8FB550

HT�8FB5�0

Program Counter

Program Counter High Byte

PC11~PC8

PCL Register

PC1�~PC8

PC13~PC8

PCL7~PCL0

Program Counter

The lower byte of the Program Counter, known as the Program Counter Low register or PCL, is available for program control and is a readable and writeable register. By transferring data directly into this register, a short program jump can be executed directly; however, as only this low byte is available for manipulation, the jumps are limited to the present page of memory, which is 256 locations.

When such program jumps are executed it should also be noted that a dummy cycle will be inserted.

Manipulating the PCL register may cause program branching, so an extra cycle is needed to pre-fetch.

Rev. 1.40

�� De�e��e� 01� �01� Rev. 1.40 �3 De�e��e� 01� �01�

HT68FB540/HT68FB550/HT68FB560

I/O Flash USB MCU with SPI

Stack

This is a special part of the memory which is used to save the contents of the Program Counter only.

The stack has multiple levels depending upon the device and is neither part of the data nor part of the program space, and is neither readable nor writeable. The activated level is indexed by the Stack

Pointer, and is neither readable nor writeable. At a subroutine call or interrupt acknowledge signal, the contents of the Program Counter are pushed onto the stack. At the end of a subroutine or an interrupt routine, signaled by a return instruction, RET or RETI, the Program Counter is restored to its previous value from the stack. After a device reset, the Stack Pointer will point to the top of the stack.

If the stack is full and an enabled interrupt takes place, the interrupt request flag will be recorded but the acknowledge signal will be inhibited. When the Stack Pointer is decremented, by RET or RETI, the interrupt will be serviced. This feature prevents stack overflow allowing the programmer to use the structure more easily. However, when the stack is full, a CALL subroutine instruction can still be executed which will result in a stack overflow. Precautions should be taken to avoid such cases which might cause unpredictable program branching.

If the stack is overflow, the first Program Counter save in the stack will be lost.

P r o g r a m C o u n t e r

T o p o f S t a c k

S t a c k

P o i n t e r

S t a c k L e v e l 1

S t a c k L e v e l 2

S t a c k L e v e l 3

P r o g r a m

M e m o r y

B o t t o m o f S t a c k S t a c k L e v e l N

Device

HT�8FB540/HT�8FB550

HT�8FB5�0

Stack Levels

8

1�

Arithmetic and Logic Unit – ALU

The arithmetic-logic unit or ALU is a critical area of the microcontroller that carries out arithmetic and logic operations of the instruction set. Connected to the main microcontroller data bus, the ALU receives related instruction codes and performs the required arithmetic or logical operations after which the result will be placed in the specified register. As these ALU calculation or operations may result in carry, borrow or other status changes, the status register will be correspondingly updated to reflect these changes. The ALU supports the following functions:

• Arithmetic operations: ADD, ADDM, ADC, ADCM, SUB, SUBM, SBC, SBCM, DAA

• Logic operations: AND, OR, XOR, ANDM, ORM, XORM, CPL, CPLA

• Rotation RRA, RR, RRCA, RRC, RLA, RL, RLCA, RLC

• Increment and Decrement INCA, INC, DECA, DEC

• Branch decision JMP, SZ, SZA, SNZ, SIZ, SDZ, SIZA, SDZA, CALL, RET, RETI

Rev. 1.40

�4 De�e��e� 01� �01�

HT68FB540/HT68FB550/HT68FB560

I/O Flash USB MCU with SPI

Rev. 1.40 �5 De�e��e� 01� �01�

HT68FB540/HT68FB550/HT68FB560

I/O Flash USB MCU with SPI

Rev. 1.40

�4 De�e��e� 01� �01�

HT68FB540/HT68FB550/HT68FB560

I/O Flash USB MCU with SPI

Flash Program Memory

The Program Memory is the location where the user code or program is stored. For this device series the Program Memory is Flash type, which means it can be programmed and re-programmed a large number of times, allowing the user the convenience of code modification on the same device. By using the appropriate programming tools, this Flash device offers users the flexibility to conveniently debug and develop their applications while also offering a means of field programming and updating.

Structure

The Program Memory has a capacity of 4Kx16 bits to 16Kx16 bits. The Program Memory is addressed by the Program Counter and also contains data, table information and interrupt entries.

Table data, which can be setup in any location within the Program Memory, is addressed by a separate table pointer register.

Device

HT�8FB540

HT�8FB550

HT�8FB5�0

Capacity

4K × 1�

8K × 1�

1�K

×

1�

Banks

0

0

0�1

The HT68FB560 has its Program Memory divided into two Banks, Bank 0 and Bank 1. The required

Bank is selected using Bit 5 of the BP Register.

Special Vectors

Within the Program Memory, certain locations are reserved for the reset and interrupts. The location

000H is reserved for use by the device reset for program initialisation. After a device reset is initiated, the program will jump to this location and begin execution.

0 0 0 0 H

0 0 0 4 H

0 0 2 8 H

R e s e t

I n t e r r u p t

V e c t o r

R e s e t R e s e t

I n t e r r u p t

V e c t o r

I n t e r r u p t

V e c t o r

0 F F F H

1 6 b i t s

1 F F F H

1 6 b i t s 1 6 b i t s

2 0 0 0 H

B a n k 1

3 F F F H

Program Memory Structure

Rev. 1.40 �5 De�e��e� 01� �01�

HT68FB540/HT68FB550/HT68FB560

I/O Flash USB MCU with SPI

Look-up Table

Any location within the Program Memory can be defined as a look-up table where programmers can store fixed data. To use the look-up table, the table pointer must first be setup by placing the address of the look up data to be retrieved in the table pointer register, TBLP and TBHP. These registers define the total address of the look-up table.

After setting up the table pointer, the table data can be retrieved from the Program Memory using the "TABRD[m]" instructions, respectively. When the instruction is executed, the lower order table byte from the Program Memory will be transferred to the user defined Data Memory register [m] as specified in the instruction. The higher order table data byte from the Program Memory will be transferred to the TBLH special register. Any unused bits in this transferred higher order byte will be read as "0".

The accompanying diagram illustrates the addressing data flow of the look-up table.

T B H P R e g i s t e r

T B L P R e g i s t e r

D a t a

1 6 b i t s

R e g i s t e r T B L H

H i g h B y t e

U s e r S e l e c t e d

R e g i s t e r

L o w B y t e

Table Program Example

The following example shows how the table pointer and table data is defined and retrieved from the microcontroller. This example uses raw table data located in the Program Memory which is stored there using the ORG statement. The value at this ORG statement is"1F00H" which refers to the start address of the last page within the 8K Program Memory of the HT68FB550. The table pointer is setup here to have an initial value of "06H". This will ensure that the first data read from the data table will be at the Program Memory address "1F06H" or 6 locations after the start of the last page.

Note that the value for the table pointer is referenced to the first address of the present page if the

"TABRD [m]" instruction is being used. The high byte of the table data which in this case is equal to zero will be transferred to the TBLH register automatically when the "TABRD [m]" instruction is executed.

Because the TBLH register is a read-only register and cannot be restored, care should be taken to ensure its protection if both the main routine and Interrupt Service Routine use table read instructions. If using the table read instructions, the Interrupt Service Routines may change the value of the TBLH and subsequently cause errors if used again by the main routine. As a rule it is recommended that simultaneous use of the table read instructions should be avoided. However, in situations where simultaneous use cannot be avoided, the interrupts should be disabled prior to the execution of any main routine table-read instructions. Note that all table related instructions require two instruction cycles to complete their operation.

Rev. 1.40

�� De�e��e� 01� �01�

HT68FB540/HT68FB550/HT68FB560

I/O Flash USB MCU with SPI

Rev. 1.40 �7 De�e��e� 01� �01�

HT68FB540/HT68FB550/HT68FB560

I/O Flash USB MCU with SPI

HT68FB540/HT68FB550/HT68FB560

I/O Flash USB MCU with SPI

In System Programming – ISP

The provision of Flash type Program Memory provides the user with a means of convenient and easy upgrades and modifications to their programs on the same device.

As an additional convenience, Holtek has provided a means of programming the microcontroller in-system using a two-line USB interface. This provides manufacturers with the possibility of manufacturing their circuit boards complete with a programmed or un-programmed microcontroller, and then programming or upgrading the program at a later stage. This enables product manufacturers to easily keep their manufactured products supplied with the latest program releases without removal and re-insertion of the device.

The Program Memory can be programmed serially in-system using the USB interface, namely using the UDN and UDP pins. The power is supplied by the UBUS pin. The technical details regarding the in-system programming of the devices are beyond the scope of this document and will be supplied in supplementary literature. The Flash Program Memory Read/ Write function is implemented using a series of registers.

Flash Memory Read/Write Page Size

There are two page sizes, 32 words or 64 words, assigned for various Flash memory size. When the Flash memory, larger than 8K bytes, is selected, the 64 word page size is assigned per page and buffer. Otherwise, the page and buffer size are assigned as 32 words.

The following diagram illustrates the Read/Write page and buffer assignment. The write buffer is controlled by the CLWB bit in the FRCR register. The CLWB bit can be set high to enable the Clear

Write Buffer procedure, as the procedure is finished, this bit will be cleared to low by hardware.

The Write Buffer is filled when the FWEN bit is set to high, when this bit is set high, the data in the

Write buffer will be written to the Flash ROM, the FWT bit is used to indicate the writing procedure.

Setting this bit high and check if the write procedure is finished, this bit will be cleared by hardware.

The Read Byte can be assigned by the address. The FRDEN is used to enable the read function and the FRD is used to indicate the reading procedure. When the reading procedure is finished, this bit will be cleared by hardware.

Device

HT�8FB540 (4K × 1�)

HT�8FB550 (8K × 1�)

HT�8FB5�0 (1�K × 1�)

Page Size (Words)

3�

3�

�4

Write Buffer (Words)

3�

3�

�4

Rev. 1.40

�� De�e��e� 01� �01� Rev. 1.40 �7 De�e��e� 01� �01�

HT68FB540/HT68FB550/HT68FB560

I/O Flash USB MCU with SPI

Flash Me�o�y

W�ite Buffe�

CLWB

FARH

FD0H

FARL

FD0L

Write one word to FD0L/FD0H

Flash Me�o�y

FARH

FD0H

FARL

FD0L

Read one word to FD0L/FD0H

Note:1. Writing a data into high byte, which means the H/L Data is written into Write Buffer, will cause the Flash memory address increased by one automatically and the new address will be loaded to the FARH and FARL registers. However, the user can also fill the new address by filling the data into FARH and FARL registers in the same page, then the data will be written into the corresponding address.

2. If the address already reached the boundary of the flash memory, such as 11111b of the 32 words or 111111b of the 64 words. At this moment, the address will not be increased and the address will stop at the last address of that page and the writing data is invalid.

3. At this point, the user has to set a new address again to fill a new data.

4. If the data is writing using the write buffer, the write buffer will be cleared by hardware automatically after the write procedure is ready in 2ms.

5. First time use the Write buffer or renew the data in the Write buffer, the user can use to Clear buffer bit (CLWB) to clear write buffer.

HT68FB540/HT68FB550/HT68FB560

I/O Flash USB MCU with SPI

Rev. 1.40

�8 De�e��e� 01� �01� Rev. 1.40 �9 De�e��e� 01� �01�

HT68FB540/HT68FB550/HT68FB560

I/O Flash USB MCU with SPI

Rev. 1.40

�8 De�e��e� 01� �01�

HT68FB540/HT68FB550/HT68FB560

I/O Flash USB MCU with SPI

ISP Bootloader

The devices provide the ISP Bootloader function to upgrade the software in the Flash memory.

The user can select to use the ISP Bootloader application software provided by Holtek IDE tool or to create his own Bootloader software. When the Holtek Bootloader software is selected, that will occupy 0.5K words area in the Flash memory. The accopanying diagram illustrates the Flash memory structure with Holtek Bootloader software.

HT68FB540

Bootloade�

HT68FB550

Bootloade�

HT68FB560

Bootloade�

0000H

0000H 0000H

0D00H

0DFFH

Last Page

Bank 0

1D00H

1DFFH

Last Page

1FFFH

Bank 1

3D00H

3DFFH

Last Page

Flash Program Memory Registers

There are two address registers, four 16-bit data registers and two control register. The control register is located in Bank1 and the other registers are located in Bank0. Read and Write operations to the Flash memory are carried out in 16-bit data operations using the address and data registers and the control register. Several registers control the overall operation of the internal Flash Program

Memory. T he address registers are named FARL and FARH, the data registers are named FDnL and FDnH, and the control registers are named FCR and FRCR. As the FARL and FDnL registers are located in Bank 0, they can be directly accessed in the same was as any other Special Function

Register. The FARH, FDnH, FCR and FRCR registers however, being located in Bank1, cannot be addressed directly and can only be read from or written to indirectly using the MP1 Memory Pointer and Indirect Addressing Register, IAR1.

Rev. 1.40 �9 De�e��e� 01� �01�

Rev. 1.40

HT68FB540/HT68FB550/HT68FB560

I/O Flash USB MCU with SPI

Program Memory Register List

• HT68FB540

Name

FARL

FARH

FD0L

FD0H

FD1L

FD1H

FD�L

FD�H

FD3L

FD3H

FCR

FRCR

• HT68FB550

7

D7

D7

D15

D7

D15

D7

D15

D7

D15

CFWEN

6

D�

D�

D14

D�

D14

D�

D14

D�

D14

FMOD�

Name

FD�L

FD�H

FD3L

FD3H

FCR

FRCR

FARL

FARH

FD0L

FD0H

FD1L

FD1H

Name

FARL

FARH

FD0L

FD0H

FD1L

FD1H

FD�L

FD�H

FD3L

FD3H

FCR

FRCR

7

D7

D7

D15

D7

D15

D7

D15

D7

D15

CFWEN

• HT68FB560

7

D7

D7

D15

D7

D15

D7

D15

D7

D15

CFWEN

6

D�

D�

D14

D�

D14

D�

D14

D�

D14

FMOD�

D�

D14

D�

D14

FMOD�

6

D�

D�

D14

D�

D14

5

D5

D5

D13

D5

D13

D5

D13

D5

D13

FMOD1

4

D4

D4

D1�

D4

D1�

D4

D1�

D4

D1�

FMOD0

FSWRST

Bit

D3

D11

D3

D11

D3

D11

BWT

3

D3

D11

D3

D11

5

D5

D5

D13

D5

D13

D5

D13

D5

D13

FMOD1

4

D4

D1�

D4

D1�

D4

D1�

D4

D1�

D4

D1�

FMOD0

FSWRST

Bit

3

D3

D11

D3

D11

D3

D11

D3

D11

D3

D11

BWT

D5

D13

D5

D13

FMOD1

5

D5

D13

D5

D13

D5

D13

4

D4

D1�

D4

D1�

D4

D1�

D4

D1�

D4

D1�

FMOD0

FSWRST

Bit

D3

D11

D3

D11

BWT

3

D3

D11

D3

D11

D3

D11

D�

D10

D�

D10

D�

D10

FWT

2

D�

D10

D�

D10

1

D1

D9

D1

D9

D1

D9

D1

D9

D1

D9

FRDEN

D0

D8

D0

D8

D0

D8

FRD

0

D0

D8

D0

D8

CLWB

2

D�

D10

D�

D10

D�

D10

D�

D10

D�

D10

FWT

1

D1

D9

D1

D9

D9

D1

D9

D1

D1

D9

FRDEN

0

D0

D8

D0

D8

D8

D0

D8

D0

D0

D8

FRD

CLWB

D�

D10

D�

D10

FWT

2

D�

D10

D�

D10

D�

D10

D1

D9

D1

D9

FRDEN

—-

D9

D1

D9

1

D1

D9

D1

D0

D8

D0

D8

FRD

CLWB

D8

D0

D8

0

D0

D8

D0

30 De�e��e� 01� �01�

HT68FB540/HT68FB550/HT68FB560

I/O Flash USB MCU with SPI

Rev. 1.40 31 De�e��e� 01� �01�

HT68FB540/HT68FB550/HT68FB560

I/O Flash USB MCU with SPI

Rev. 1.40

30 De�e��e� 01� �01�

HT68FB540/HT68FB550/HT68FB560

I/O Flash USB MCU with SPI

FARL Register

Bit

Na�e

R/W

POR

7

D7

R/W x

6

D�

R/W x

5

D5

R/W x

4

D4

R/W x

Bit 7~0

D7~D0

: Flash Program Memory address

Flash Program Memory address bit 7~bit 0

FARH Register

• HT68FB540

Bit

Na�e

R/W

POR

7

6

5

4

3

D11

R/W x

3

D3

R/W x

Bit 7~4 Reserved, cannot be used

Bit 3~0

D11~D8

: Flash Program Memory address

Flash Program Memory address bit 11~bit 8

• HT68FB550

Bit

Na�e

R/W

POR

7

6

5

4

D1�

R/W x

3

D11

R/W x

Bit 7~5 Reserved, cannot be used

Bit 4~0

D12~D8

: Flash Program Memory address

Flash Program Memory address bit 12~bit 8

• HT68FB560

Bit

Na�e

R/W

POR

7

6

5

D13

R/W x

4

D1�

R/W x

3

D11

R/W x

Bit 7~6 Reserved, cannot be used

Bit 5~0

D13~D8

: Flash Program Memory address

Flash Program Memory address bit 13~bit 8

2

D�

R/W x

1

D1

R/W x

0

D0

R/W x

"x" unknown

2

D10

R/W x

1

D9

R/W x

0

D8

R/W x

"x" unknown

2

D10

R/W x

1

D9

R/W x

0

D8

R/W x

"x" unknown

2

D10

R/W x

1

D9

R/W x

0

D8

R/W x

"x" unknown

Rev. 1.40 31 De�e��e� 01� �01�

Rev. 1.40

HT68FB540/HT68FB550/HT68FB560

I/O Flash USB MCU with SPI

FCR Register

Bit

Na�e

R/W

POR

Bit 7

Bit 6~4

Bit 3

Bit 2

Bit 1

Bit 0

7

CFWEN

R/W

0

6

FMOD�

R/W

0

5

FMOD1

R/W

0

4

FMOD0

R/W

0

3

BWT

R/W

0

2

FWT

R/W

0

1

FRDEN

R/W

0

0

FRD

R/W

0

CFWEN

: Flash ROM Write Enable bit, FWEN, control bit

0: disable

1: unimplemented

This bit is used to control the FWEN bit enable or disable. When this bit is cleared to low by software, the Flash memory write enable control bit, FWEN will be cleared to low as well. It’s ineffective to set this bit to high. The user can check this bit to confirm the FWEN status.

FMOD2~FMOD0

: Flash Program memory, Configuration option memory operating mode control bits

000: write memory mode

001: page erase mode

010: reserved

011: read memory mode

100: reserved

101: reserved

110: FWEN (flash memory write enable) bit control mode

111: reserved

BWT

: Mode change control

0: mode change cycle has finished

1: activate a mode change cycle

This bit will be automatically reset to zero by the hardware after the mode change cycle has finished.

FWT

: Flash memory Write Control

0: write cycle has finished

1: activate a write cycle

This is the Flash memory Write Control Bit and when set high by the application program will activate a write cycle. This bit will be automatically reset to zero by the hardware after the write cycle has finished.

FRDEN

: Flash Memory Read Enable

0: disable

1: enable

This is the Flash memory Read Enable Bit which must be set high before Flash memory read operations are carried out. Clearing this bit to zero will inhibit Flash memory read operations.

FRD

: Flash memory Read Control

0: read cycle has finished

1: activate a read cycle

This is the Flash memory Read Control Bit and when set high by the application program will activate a read cycle. This bit will be automatically reset to zero by the hardware after the read cycle has finished. Setting this bit high will have no effect if the RDEN has not first been set high.

Note: The FWT, FRDEN and FRD registers can not be set to "1" at the same time with a single instruction.

3� De�e��e� 01� �01�

HT68FB540/HT68FB550/HT68FB560

I/O Flash USB MCU with SPI

Rev. 1.40 33 De�e��e� 01� �01�

HT68FB540/HT68FB550/HT68FB560

I/O Flash USB MCU with SPI

Rev. 1.40

3� De�e��e� 01� �01�

HT68FB540/HT68FB550/HT68FB560

I/O Flash USB MCU with SPI

FRCR Register

Bit

Na�e

R/W

POR

Bit 7~5

Bit 4

Bit 3~1

Bit 0

7

6

5

4

FSWRST

R/W

0

3

2

1

0

CLWB

R/W

0

"—": unimplemented, read as "0"

FSWRST

: control bit

Must be to 0

"—": unimplemented, read as "0"

CLWB

: Flash Program memory Write buffer clear control bit

0: do not initiate clear Write Buffer or clear process

1: initiate clear Write Buffer process

This bit is used to control the Flash Program memory clear Write buffer process. It will be set by software and cleared by hardware.

In Application Program – IAP

Offering users the convenience of Flash Memory multi-programming features, the HT68FB5x0 series of devices not only provide an ISP function, but also an additional IAP function. The convenience of the IAP function is that it can execute the updated program procedure using its internal firmware, without requiring an external Program Writer or PC. In addition, the IAP interface can also be any type of communication protocol, such as UART or CAN, using I/O pins. D esigners can assign I/O pins to communicate with the external memory device, including the updated program. Regarding the internal firmware, the user can select versions provided by HOLTEK or create their own. The following section illustrates the procedures regarding how to implement IAP firmware.

Enable Flash Write Control Procedure

The first procedure to implement the IAP firmware is to enable the Flash Write control which includes the following steps.

• Write data "110" to the Fmod [2:0] bits in the FCR register to enable the Flash write control bit,

FWEN.

• Set the BWT bit in the FCR register to "1".

• The device will start a 1ms counter. The user should write the correct data pattern into the Flash data registers, namely FD1L~FD3L and FD1H~FD3H, during this period of time.

• Once the 1ms counter has overflowed or if the written pattern is incorrect, the enable Flash write control procedure will be invalid and the user should repeat the above procedure.

• No matter whether the procedure is valid or not, the devices will clear the BWT bit automatically.

• The enable Flash write pattern data is (00H 04H 0DH 09H C3H 40H) and it should be written into the Flash data registers.

• Once the Flash write operation is enabled, the user can update the Flash memory using the Flash control registers.

• To disable the Flash write procedure, the user can only clear the CFWEN bit in the FCR register.

There is no need to execute the above procedure.

Rev. 1.40 33 De�e��e� 01� �01�

Rev. 1.40

HT68FB540/HT68FB550/HT68FB560

I/O Flash USB MCU with SPI

Set FWEN

Fmod2~0 = 110 : Set FWEN bit

BWT = 1,Hardware set a counter

Wrtie the following pattern to Flash Data register

FD 1L= 00h , FD 1H = 04h

FD 2L = 0dh , FD 2H = 09h

FD 3L =C 3h , FD 3H = 40h

No

Is counter overflow?

BWT = 0 ?

Yes

Is pattern is correct ?

Yes

No

CFWEN = 1

Set FWEN bit success

.

CFWEN = 0

Set FWEN bit fail

END

34 De�e��e� 01� �01�

HT68FB540/HT68FB550/HT68FB560

I/O Flash USB MCU with SPI

Rev. 1.40 35 De�e��e� 01� �01�

HT68FB540/HT68FB550/HT68FB560

I/O Flash USB MCU with SPI

Rev. 1.40

34 De�e��e� 01� �01�

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I/O Flash USB MCU with SPI

Flash Memory Write and Read Procedures

The following flow charts illustrate the Write and Read Flash memory procedures.

Write Flash

ROM

Set FWEN procedure

Page Erase

FAH=xxh, FAL=xxh

Fmod2~0=001

FWT=1

Rev. 1.40

No

FWT=0 ?

Yes

Write

Fmod2~0=000

Write data to Write Buffer

[(ROM ≤ 8K 1~32 Words data) or

(ROM > 8K 1~64 Words data)]:

Flash address register: FAH=xxh, FAL=xxh

Write the following data to register:

FD0L=xxh, FD0H=xxh

Write next data

No

Write Buffer

Finish?

Yes

FWT=1

No

FWT=0 ?

Yes

Write Finish ?

No

Write next Page

Yes

Clear CFWEN bit

END

Write Flash Program ROM Procedure

35 De�e��e� 01� �01�

Rev. 1.40

HT68FB540/HT68FB550/HT68FB560

I/O Flash USB MCU with SPI

Read Flash

Fmod2~0 = 011

FRDEN = 1 flash address register:

FAH = xxh, FAL = xxh

FRD = 1

No

FRD = 0 ?

Yes

Read value:

FD 0L = xxh, FD 0H = xxh

No

Read Finish ?

Yes

FRDEN = 0

Clear CFWEN bit

END

3� De�e��e� 01� �01�

HT68FB540/HT68FB550/HT68FB560

I/O Flash USB MCU with SPI

Rev. 1.40 37 De�e��e� 01� �01�

HT68FB540/HT68FB550/HT68FB560

I/O Flash USB MCU with SPI

Rev. 1.40

3� De�e��e� 01� �01�

HT68FB540/HT68FB550/HT68FB560

I/O Flash USB MCU with SPI

In Circuit Programming – ICP

The provision of Flash type Program Memory provides the user with a means of convenient and easy upgrades and modifications to their programs on the same device.

As an additional convenience, Holtek has provided a means of programming the microcontroller incircuit using a 4-pin interface. This provides manufacturers with the possibility of manufacturing their circuit boards complete with a programmed or un-programmed microcontroller, and then programming or upgrading the program at a later stage. This enables product manufacturers to easily keep their manufactured products supplied with the latest program releases without removal and reinsertion of the device.

Holtek Writer Pins

ICPDA

ICPCK

VDD

VSS

MCU Programming Pins

UDN

RES

VDD/HVDD

VSS

Pin Description

P�og�a��ing Se�ial Data

P�og�a��ing Clo�k

Powe� Supply

G�ound

The Program Memory can be programmed serially in-circuit using this 4-wire interface. Data is downloaded and uploaded serially on a single pin with an additional line for the clock. Two additional lines are required for the power supply and one line for the reset. The technical details regarding the in-circuit programming of the devices are beyond the scope of this document and will be supplied in supplementary literature.

During the programming process, taking control of the UDN and RES pins for data and clock programming purposes. The user must there take care to ensure that no other outputs are connected to these two pins.



  



Note: * may be resistor or capacitor. The resistance of * must be greater than 300 W or the capacitance of * must be less than 1nF.

On-Chip Debug Support – OCDS

There is an EV chip named HT68VB540/HT68VB550/HT68VB560 which is used to emulate the

HT68FB540/HT68FB550/HT68FB560 device. The HT68VB540/HT68VB550/HT68VB560 device also provides the “On-Chip Debug” function to debug the HT68FB540/HT68FB550/HT68FB560 device during development process. The two devices, HT68FB540/HT68FB550/HT68FB560 and

HT68VB540/HT68VB550/HT68VB560, are almost functional compatible except the “On-Chip

Debug” function. Users can use the HT68VB540/HT68VB550/HT68VB560 device to emulate the

HT68FB540/HT68FB550/HT68FB560 device behaviors by connecting the OCDSDA and OCDSCK

Rev. 1.40 37 De�e��e� 01� �01�

HT68FB540/HT68FB550/HT68FB560

I/O Flash USB MCU with SPI

pins to the Holtek HT-IDE development tools. The OCDSDA pin is the OCDS Data/Address input/ output pin while the OCDSCK pin is the OCDS clock input pin. When users use the HT68VB540/

HT68VB550/HT68VB560 EV chip for debugging, the corresponding pin functions shared with the

OCDSDA and OCDSCK pins in the HT68FB540/HT68FB550/HT68FB560 device will have no effect in the HT68VB540/HT68VB550/HT68VB560 EV chip. For more detailed OCDS information, refer to the corresponding document named “Holtek e-Link for 8-bit MCU OCDS User’s Guide”.

Holtek e-Link Pins

OCDSDA

OCDSCK

VDD

GND

EV Chip Pins

OCDSDA

OCDSCK

VDD/HVDD

VSS

Pin Description

On-Chip De�ug Suppo�t Data/Add�ess input/output

On-Chip De�ug Suppo�t Clo�k input

Powe� Supply

G�ound

RAM Data Memory

The Data Memory is a volatile area of 8-bit wide RAM internal memory and is the location where temporary information is stored.

Structure

Divided into two sections, the first of these is an area of RAM, known as the Special Function Data

Memory. Here are located registers which are necessary for correct operation of the device. Many of these registers can be read from and written to directly under program control, however, some remain protected from user manipulation.

Device Capacity

HT�8FB540

HT�8FB550

HT�8FB5�0

�5� × 8

51� × 8

7�8 × 8

Banks

0: 80H~FFH

1: 80H~FFH

0: 80H~FFH

1: 80H~FFH

�: 80H~FFH

3: 80H~FFH

0: 80H~FFH

1: 80H~FFH

�: 80H~FFH

3: 80H~FFH

4: 80H~FFH

5: 80H~FFH

The second area of Data Memory is known as the General Purpose Data Memory, which is reserved for general purpose use. All locations within this area are read and write accessible under program control.

The overall Data Memory is subdivided into several banks, the structure of which depends upon the device chosen. The Special Purpose Data Memory registers are accessible in all banks, with the exception of the FRCR, FCR, FARH and FDnH registers at address from 40H to 46H, which are only accessible in Bank 1. Switching between the different Data Memory banks is achieved by setting the Bank Pointer to the correct value. The start address of the Data Memory for all devices is the address 00H.

Rev. 1.40

38 De�e��e� 01� �01�

HT68FB540/HT68FB550/HT68FB560

I/O Flash USB MCU with SPI

Rev. 1.40 39 De�e��e� 01� �01�

HT68FB540/HT68FB550/HT68FB560

I/O Flash USB MCU with SPI

Rev. 1.40

38 De�e��e� 01� �01�

HT68FB540/HT68FB550/HT68FB560

I/O Flash USB MCU with SPI

HT68FB540 Special Purpose Data Memory

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Rev. 1.40

HT68FB540/HT68FB550/HT68FB560

I/O Flash USB MCU with SPI

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40 De�e��e� 01� �01�

HT68FB540/HT68FB550/HT68FB560

I/O Flash USB MCU with SPI

Rev. 1.40 41 De�e��e� 01� �01�

HT68FB540/HT68FB550/HT68FB560

I/O Flash USB MCU with SPI

Rev. 1.40

40 De�e��e� 01� �01�

HT68FB540/HT68FB550/HT68FB560

I/O Flash USB MCU with SPI

HT68FB560 Special Purpose Data Memory

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Rev. 1.40 41 De�e��e� 01� �01�

HT68FB540/HT68FB550/HT68FB560

I/O Flash USB MCU with SPI

Special Function Register Description

Most of the Special Function Register details will be described in the relevant functional section; however several registers require a separate description in this section.

Indirect Addressing Registers – IAR0, IAR1

The Indirect Addressing Registers, IAR0 and IAR1, although having their locations in normal RAM register space, do not actually physically exist as normal registers. The method of indirect addressing for RAM data manipulation uses these Indirect Addressing Registers and Memory Pointers, in contrast to direct memory addressing, where the actual memory address is specified. Actions on the

IAR0 and IAR1 registers will result in no actual read or write operation to these registers but rather to the memory location specified by their corresponding Memory Pointers, MP0 or MP1. Acting as a pair, IAR0 and MP0 can together access data from Bank 0 while the IAR1 and MP1 register pair can access data from any bank. As the Indirect Addressing Registers are not physically implemented, reading the Indirect Addressing Registers indirectly will return a result of "00H" and writing to the registers indirectly will result in no operation.

Memory Pointers – MP0, MP1

Two Memory Pointers, known as MP0 and MP1 are provided. These Memory Pointers are physically implemented in the Data Memory and can be manipulated in the same way as normal registers providing a convenient way with which to address and track data. When any operation to the relevant Indirect Addressing Registers is carried out, the actual address that the microcontroller is directed to, is the address specified by the related Memory Pointer. MP0, together with Indirect

Addressing Register, IAR0, are used to access data from Bank 0, while MP1 and IAR1 are used to access data from all banks according to BP register. Direct Addressing can only be used with Bank 0, all other Banks must be addressed indirectly using MP1 and IAR1.

The following example shows how to clear a section of four Data Memory locations already defined as locations adres1 to adres4.

Indirect Addressing Program Example

data .section data adres1 db ? adres2 db ? adres3 db ? adres4 db ? block db ? code .section at 0 code org 00h

start:

mov

mov block,a

mov a,offset adres1 ; Accumulator loaded with first RAM address

mov mp0,a ; setup memory pointer with first RAM address

loop:

clr IAR0 ; clear the data at address defined by MP0

inc ;

sdz block ; check if last memory location has been cleared

jmp loop

continue:

The important point to note here is that in the example shown above, no reference is made to specific

RAM addresses.

Rev. 1.40

4� De�e��e� 01� �01�

HT68FB540/HT68FB550/HT68FB560

I/O Flash USB MCU with SPI

Rev. 1.40 43 De�e��e� 01� �01�

HT68FB540/HT68FB550/HT68FB560

I/O Flash USB MCU with SPI

Rev. 1.40

4� De�e��e� 01� �01�

HT68FB540/HT68FB550/HT68FB560

I/O Flash USB MCU with SPI

Bank Pointer – BP

Depending upon which device is used, the Program and Data Memory are divided into several banks. Selecting the required Program and Data Memory area is achieved using the Bank Pointer.

Bit 5 of the Bank Pointer is used to select Program Memory Bank 0 or 1, while bits 0~2 are used to select Data Memory Banks 0 ~ 5.

The Data Memory is initialised to Bank 0 after a reset, except for a WDT time-out reset in the Power

Down Mode, in which case, the Data Memory bank remains unaffected. It should be noted that the

Special Function Data Memory is not affected by the bank selection, which means that the Special

Function Registers can be accessed from within any bank. Directly addressing the Data Memory will always result in Bank 0 being accessed irrespective of the value of the Bank Pointer. Accessing data from banks other than Bank 0 must be implemented using Indirect addressing.

As both the Program Memory and Data Memory share the same Bank Pointer Register, care must be taken during programming.

Device

HT�8FB540

HT�8FB550

HT�8FB5�0

7

6

Bit

5

PMBP0

4

BP Registers List

3

2

1

0

DMBP0

DMBP1 DMBP0

DMBP� DMBP1 DMBP0

BP Register

• HT68FB540

Bit

Na�e

R/W

POR

R

0

7

R

0

6

R

0

5

R

0

4

Bit 7~1

Bit 0

• HT68FB550

Bit

Na�e

R/W

POR

Bit 7~2

Bit 1~0

"—": unimplemented, read as "0"

DMBP0

: Select Data Memory Banks

0: bank 0

1: bank 1

R

0

7

R

0

6

R

0

5

R

0

4

"—": unimplemented, read as "0"

DMBP1, DMBP0

: Select Data Memory Banks

00: bank 0

01: bank 1

10: bank 2

11: bank 3

R

0

3

R

0

3

R

0

2

R

0

2

R

0

1

1

DMBP1

R/W

0

0

DMBP0

R/W

0

0

DMBP0

R/W

0

Rev. 1.40 43 De�e��e� 01� �01�

HT68FB540/HT68FB550/HT68FB560

I/O Flash USB MCU with SPI

• HT68FB560

Bit

Na�e

R/W

POR

R

0

7

Bit 7~6

Bit 5

Bit 4~3

Bit 2~0

R

0

6

5

PMBP0

R/W

0

R

0

4

R

0

3

2

DMBP�

R/W

0

"—": unimplemented, read as "0"

PMBP0

: Select Program Memory Banks

0: bank 0, program memory address is from 0000H ~ 1FFFH

1: bank 1, program memory address is from 2000H ~ 3FFFH

"—": unimplemented, read as "0"

DMBP2 ~ DMBP0

: Select Data Memory Banks

000: bank 0

001: bank 1

010: bank 2

011: bank 3

100: bank 4

101: bank 5

110~111: unimplemented

1

DMBP1

R/W

0

0

DMBP0

R/W

0

Accumulator – ACC

The Accumulator is central to the operation of any microcontroller and is closely related with operations carried out by the ALU. The Accumulator is the place where all intermediate results from the ALU are stored. Without the Accumulator it would be necessary to write the result of each calculation or logical operation such as addition, subtraction, shift, etc., to the Data Memory resulting in higher programming and timing overheads. Data transfer operations usually involve the temporary storage function of the Accumulator; for example, when transferring data between one user defined register and another, it is necessary to do this by passing the data through the

Accumulator as no direct transfer between two registers is permitted.

Program Counter Low Register – PCL

To provide additional program control functions, the low byte of the Program Counter is made accessible to programmers by locating it within the Special Purpose area of the Data Memory. By manipulating this register, direct jumps to other program locations are easily implemented. Loading a value directly into this PCL register will cause a jump to the specified Program Memory location, however, as the register is only 8-bit wide, only jumps within the current Program Memory page are permitted. When such operations are used, note that a dummy cycle will be inserted.

Look-up Table Registers – TBLP, TBHP, TBLH

These three special function registers are used to control operation of the look-up table which is stored in the Program Memory. TBLP and TBHP are the table pointer and indicates the location where the table data is located. Their value must be setup before any table read commands are executed. Their value can be changed, for example using the "INC" or "DEC" instructions, allowing for easy table data pointing and reading. TBLH is the location where the high order byte of the table data is stored after a table read data instruction has been executed. Note that the lower order table data byte is transferred to a user defined location.

Rev. 1.40

44 De�e��e� 01� �01�

HT68FB540/HT68FB550/HT68FB560

I/O Flash USB MCU with SPI

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HT68FB540/HT68FB550/HT68FB560

I/O Flash USB MCU with SPI

Rev. 1.40

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I/O Flash USB MCU with SPI

Status Register – STATUS

This 8-bit register contains the zero flag (Z), carry flag (C), auxiliary carry flag (AC), overflow flag

(OV), power down flag (PDF), and watchdog time-out flag (TO). These arithmetic/logical operation and system management flags are used to record the status and operation of the microcontroller.

With the exception of the TO and PDF flags, bits in the status register can be altered by instructions like most other registers. Any data written into the status register will not change the TO or PDF flag.

In addition, operations related to the status register may give different results due to the different instruction operations. The TO flag can be affected only by a system power-up, a WDT time-out or by executing the "CLR WDT" or "HALT" instruction. The PDF flag is affected only by executing the "HALT" or "CLR WDT" instruction or during a system power-up.

The Z, OV, AC and C flags generally reflect the status of the latest operations.

• C is set if an operation results in a carry during an addition operation or if a borrow does not take place during a subtraction operation; otherwise C is cleared. C is also affected by a rotate through carry instruction.

• AC is set if an operation results in a carry out of the low nibbles in addition, or no borrow from the high nibble into the low nibble in subtraction; otherwise AC is cleared.

• Z is set if the result of an arithmetic or logical operation is zero; otherwise Z is cleared.

• OV is set if an operation results in a carry into the highest-order bit but not a carry out of the highest-order bit, or vice versa; otherwise OV is cleared.

• PDF is cleared by a system power-up or executing the "CLR WDT" instruction. PDF is set by executing the "HALT" instruction.

• TO is cleared by a system power-up or executing the "CLR WDT" or "HALT" instruction. TO is set by a WDT time-out.

In addition, on entering an interrupt sequence or executing a subroutine call, the status register will not be pushed onto the stack automatically. If the contents of the status registers are important and if the subroutine can corrupt the status register, precautions must be taken to correctly save it.

STATUS Register

Bit 7

Na�e

R/W

POR

R

0

Bit 7~6

Bit 5

Bit 4

Bit 3

Bit 2

R

0

6

5

TO

R

0

4

PDF

R

0

3

OV

R/W x

2

Z

R/W x

1

AC

R/W x

0

C

R/W x

"x" unknown

"—": unimplemented, read as "0"

TO

: Watchdog Time-Out flag

0: after power up or executing the "CLR WDT" or "HALT" instruction

1: a watchdog time-out occurred.

PDF

: Power down flag

0: after power up or executing the "CLR WDT" instruction

1: by executing the "HALT" instruction

OV

: Overflow flag

0: no overflow

1: an operation results in a carry into the highest-order bit but not a carry out of the

highest-order bit or vice versa.

Z

: Zero flag

0: the result of an arithmetic or logical operation is not zero

1: the result of an arithmetic or logical operation is zero

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I/O Flash USB MCU with SPI

Bit 1

Bit 0

AC

: Auxiliary flag

0: no auxiliary carry

1: an operation results in a carry out of the low nibbles in addition, or no borrow

from the high nibble into the low nibble in subtraction

C

: Carry flag

0: no carry-out

1: an operation results in a carry during an addition operation or if a borrow does not

take place during a subtraction operation

C is also affected by a rotate through carry instruction.

Oscillator

Various oscillator options offer the user a wide range of functions according to their various application requirements. The flexible features of the oscillator functions ensure that the best optimisation can be achieved in terms of speed and power saving. Oscillator selections and operation are selected through a combination of configuration options and registers.

Oscillator Overview

In addition to being the source of the main system clock the oscillators also provide clock sources for the Watchdog Timer Interrupt. External oscillators requiring some external components as well as fully integrated internal oscillators, requiring no external components, are provided to form a wide range of both fast and slow system oscillators. The high speed oscillator, HXT or HIRC, option is selected through the configuration option. The higher frequency oscillators provide higher performance but carry with it the disadvantage of higher power requirements, while the opposite is of course true for the lower frequency oscillator. With the capability of dynamically switching between fast and slow system clock, the device has the flexibility to optimize the performance/ power ratio, a feature especially important in power sensitive portable applications.

Type

Exte�nal C�ystal

Inte�nal High Speed RC

Inte�nal Low Speed RC

Name

HXT

HIRC

LIRC

Freq.

�MHz o� 1�MHz

1�MHz

3�kHz

Pins

OSC1/OSC�

Oscillator Types

Note: For USB applications, HXT must be connected an 6MHz or 12MHz crystal.

System Clock Configurations

There are several oscillator sources, two high speed oscillators and one low speed oscillator.

The high speed system clocks are sourced from the external crystal/ ceramic oscillator, the PLL frequency generator and the internal 12MHz RC oscillator. The low speed oscillator is the internal

32kHz RC oscillator. Selecting whether the low or high speed oscillator is used as the system oscillator is implemented using the HLCLK bit and CKS2~CKS0 bits in the SMOD register and as the system clock can be dynamically selected. The actual source clock used for each of the high speed oscillators is chosen via configuration options. The frequency of the slow speed or high speed system clock is also determined using the HLCLK bit and CKS2~CKS0 bits in the SMOD register.

Note that two oscillator selections must be made namely one high speed and one low speed system oscillators. It is not possible to choose a no-oscillator selection for either the high or low speed oscillator. In addition, the internal PLL frequency generator, whose clock source is supplied by an external crystal oscillator, can be enabled by a software control bit to generate various frequencies for the USB interface and system clock.

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I/O Flash USB MCU with SPI

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I/O Flash USB MCU with SPI

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I/O Flash USB MCU with SPI

USBCKEN �it

Config.Option

Sele�ts

� o� 1�MHz XTAL

HXT

OSC

HOSC

÷�

HIRC

OSC

High speed

Os�illato�

Configu�ation

Option

SYSCLK

Bit

�MHz

PLL

PLL �it

48MHz

1�MHz

�MHz

1�MHz

HOSC

SYSCLK

�it

To USBCK

�i��uits

USBCKEN

�it

HOSC

PLL �lo�k

FSYS1�MHz

�it

PLL �it

LIRC

OSC f

H

P�es�ale�

HCLK �it

CKS0-CKS� �it f f

H

H

/�

/4 f

H

/8 f f

H

H

/1�

/3� f

H

/�4 f f

H

L f

SYS f

L

Fast Wake-Up f�o�

SLEEP o� IDLE �ode

Cont�ol (fo� HXT only) f

SUB

WDT

System Clock Configurations

External Crystal Oscillator – HXT

The External Crystal System Oscillator is one of the high frequency oscillator.

  

 

Crystal/Ceramic System Oscillator – HXT

Crystal Frequency

1�MHz

1�MHz

8MHz

�MHz

Crystal Oscillator C1 and C2 Values

C1

0pF

0pF

0pF

0pF

4MHz

1MHz

Note: 1. C1 and C� values a�e fo� guidan�e only.

0pF

100pF

Crystal Recommended Capacitor Values

Note: For USB applications, HXT must be connected a 6MHz or 12MHz crystal.

C2

0pF

0pF

0pF

0pF

0pF

100pF

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I/O Flash USB MCU with SPI

Internal PLL Frequency Generator

The internal PLL frequency generator is used to generate the frequency for the USB interface and the system clock. This PLL generator can be enabled or disabled by the PLL control bit in the USC register. After a power on reset, the PLL control bit will be set to "0" to turn on the PLL generator.

The PLL generator will provide the fixed 48MHz frequency for the USB operating frequency and another frequency for the system clock source which can be either 6MHz, 12MHz or 16MHz. The selection of this system frequency is implemented using the SYSCLK, Fsys16MHZ, and USBCKEN bits in the UCC register. In addition, the system clock can be selected as the HXT via these control bits. The CLK_ADJ bit is used to adjust the PLL clock automatically.

SYSC Register

Bit

Na�e

R/W

POR

Bit 7

Bit 6

Bit 5

Bit 4~3

Bit 2

Bit 1~0

7 6

CLK_ADJ USBdis

R/W

0

R/W

0

5

RUBUS

R/W

0

4

3

2

HFV

R/W

0

1

0

CLK_ADJ

: PLL Clock Automatic Adjustment function:

0: disable

1: enable

Note that if the user selects the HIRC as the system clock, the CLK_ADJ bit must be set to "1" to adjust the PLL frequency automatically.

USBdis

: USB SIE control bit

USB related control bit, described elsewhere

RUBUS

: UBUS pin pull low resistor

USB related control bit, described elsewhere

"—": unimplemented, read as "0"

HFV

: High frequency voltage control

This bit must be set to high.

"—": unimplemented, read as "0"

HT68FB540/HT68FB550/HT68FB560

I/O Flash USB MCU with SPI

Rev. 1.40

48 De�e��e� 01� �01� Rev. 1.40 49 De�e��e� 01� �01�

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I/O Flash USB MCU with SPI

Rev. 1.40

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I/O Flash USB MCU with SPI

UCC Register

• HT68FB540

Bit

Na�e

R/W

POR

7

R�t�l

R/W

0

B it 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1~0

6 5 4 3

SYSCLK Fsys1�MHZ SUSP� USBCKEN

R/W

0

R/W

0

R/W

0

R/W

0

2

R

0

1

EPS1

R/W

0

0

EPS0

R/W

0

Rctrl

: 7.5kΩ resistor between UDP and UBUS control bit

USB related control bit, described elsewhere

SYSCLK

: System clock frequency select bit

0: 12MHz

1: 6MHz

Note:

If a 6 MHz crystal or resonator is used for the MCU, this bit should be set to "1".

If a 12 MHz crystal or resonator is used, then this bit should be set to "0".

If the 12MHz HIRC is selected, then this bit must be set to "0".

Fsys16MHZ

: PLL 16MHz output control bit

0: HXT

1: PLL 16MHz

SUSP2

: Reduce power consumption in suspend mode control bit

USB related control bit, described elsewhere

USBCKEN

: USB clock control bit

0: disable

1: enable

"—": unimplemented, read as "0"

EPS1, EPS0

: Accessing endpoint FIFO selection

USB related control bit, described elsewhere

USC Register

Bit

Na�e

R/W

POR

B it 7

1

RMWK

R/W

0

0

SUSP

R

0

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

7

URD

R/W

1

6

SELPS�

R/W

0

5

PLL

R/W

0

4 3

SELUSB RESUME

R/W R

0 0

URD

: USB reset signal control function definition

USB related control bit, described elsewhere

SELPS2

: the chip works under PS2 mode indicator bit

USB related control bit, described elsewhere

PLL

: PLL control bit

0: Turn-on PLL

1: Turn-off PLL

SELUSB

: the chip works under USB mode indicator bit

USB related control bit, described elsewhere

RESUME

: USB resume indication bit

USB related control bit, described elsewhere

URST

: USB reset indication bit

USB related control bit, described elsewhere

RMWK

: USB remote wake-up command

USB related control bit, described elsewhere

SUSP

: USB suspend indication

USB related control bit, described els ewhere

2

URST

R/W

0

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I/O Flash USB MCU with SPI

The following table illustrates the PLL output frequency selected by the related control bits.

PLL

0

0

0

0

1

USBCKEN

0

0

1

1 x

Fsys16MHZ

0

1

0

1 x

f

H

HOSC (HXT o� HIRC) f

PLL

– 1�MHz f

PLL

– �MHz o� 1�MHz� depending on the

"SYSCLK" �it in the UCC �egiste� sele�tion f

PLL

– 1�MHz

HOSC (HXT o� HIRC) x: stand fo� "don’t �a�e"

High Frequency System Clock f

H

Selection Table

Internal RC Oscillator – HIRC

The internal RC oscillator is a fully integrated system oscillator requiring no external components.

The internal RC oscillator has a fixed frequency of 12MHz. Device trimming during the manufacturing process and the inclusion of internal frequency compensation circuits are used to ensure that the influence of the power supply voltage, temperature and process variations on the oscillation frequency are minimised. As a result, at a power supply of either 3.3V or 5V and at a temperature of 25 degrees, the fixed oscillation frequency of 12MHz will have a tolerance within 3%

(Non-USB mode). Note that if this internal system clock option is selected, as it requires no external pins for its operation, I/O pi ns PA1 and PA2 are free for use as normal I/O pins. The H I RC has its own power supply pin, HVDD. The HVDD pin must be connected to VDD and an 0.1

m F capacitor to ground.

Internal 32kHz Oscillator – LIRC

The Internal 32kHz System Oscillator is a fully integrated RC oscillator with a typical frequency of 32kHz at 5V, requiring no external components for its implementation. Device trimming during the manufacturing process and the inclusion of internal frequency compensation circuits are used to ensure that the influence of the power supply voltage, temperature and process variations on the oscillation frequency are minimised. As a result, at a power supply of 5V and at a temperature of 25 degrees, the fixed oscillation frequency of 32kHz will have a tolerance within 10%.

Supplementary Internal Clocks

The low speed oscillator, in addition to providing a system clock source is also used to provide a clock source, namely f

SUB

, to the Watchdog Timer Interrupt.

Operating Modes and System Clocks

Present day applications require that their microcontrollers have high performance but often still demand that they consume as little power as possible, conflicting requirements that are especially true in battery powered portable applications. The fast clocks required for high performance will by their nature increase current consumption and of course vice versa, lower speed clocks reduce current consumption. As Holtek has provided these devices with both high and low speed clock sources and the means to switch between them dynamically, the user can optimise the operation of their microcontroller to achieve the best performance/power ratio.

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I/O Flash USB MCU with SPI

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I/O Flash USB MCU with SPI

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I/O Flash USB MCU with SPI

System Clocks

The device has many different clock sources for both the CPU and peripheral function operation.

By providing the user with a wide range of clock options using configuration options and register programming, a clock system can be configured to obtain maximum application performance.

The main system clock, can come from either a high frequency, f

H

, or low frequency, f

L

, source, and is selected using the HLCLK bit and CKS2~CKS0 bits in the SMOD register. The high speed system clock can be sourced from either a HXT or HIRC oscillator, selected via a configuration option. The low speed system clock source can be provided by internal clock f

L

, sourced by the

LIRC oscillator. The other choice, which is a divided version of the high speed system oscillator has a range of f

H

/2~f

H

/64. The f

SUB

clock is used as the clock source for the Watchdog timer.

USBCKEN �it

Config.Option

Sele�ts

� o� 1�MHz XTAL

HXT

OSC

HOSC

÷�

HIRC

OSC

High speed

Os�illato�

Configu�ation

Option

SYSCLK

Bit

�MHz

PLL

PLL �it

48MHz

1�MHz

�MHz

1�MHz

HOSC

SYSCLK

�it

To USBCK

�i��uits

USBCKEN

�it

HOSC

PLL �lo�k

FSYS1�MHz

�it

PLL �it

LIRC

OSC f

H

P�es�ale� f f

H

H

/�

/4 f

H

/8 f f

H

H

/1�

/3� f

H

/�4 f f

H

L f

SYS

HCLK �it

CKS0-CKS� �it f

L f

SUB

WDT

Fast Wake-Up f�o�

SLEEP o� IDLE �ode

Cont�ol (fo� HXT only)

System Clock Configurations

Note: when the system clock source f

SYS

is switched to f

L

from f

H

, the high speed oscillation will stop to conserve the power. Thus there is no f

H

~f

H

/64 for peripheral circuit to use.

System Operation Modes

There are six different modes of operation for the microcontroller, each one with its own special characteristics and which can be chosen according to the specific performance and power requirements of the application. There are two modes allowing normal operation of the microcontroller, the NORMAL Mode and SLOW Mode. The remaining four modes, the SLEEP0,

SLEEP1, IDLE0 and IDLE1 Mode are used when the microcontroller CPU is switched off to conserve power.

Operation Mode

NORMAL Mode

SLOW Mode

IDLE0 Mode

IDLE1 Mode

SLEEP0 Mode

SLEEP1 Mode

CPU

On

On

Off

Off

Off

Off

Description f

SYS

f

H

~ f

H/�4 f

L

Off

On

Off

Off

f

SUB

On

On

On

On

Off

On

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I/O Flash USB MCU with SPI

NORMAL Mode

As the name suggests this is one of the main operating modes where the microcontroller has all of its functions operational and where the system clock is provided by one of the high speed oscillators.

This mode operates allowing the microcontroller to operate normally with a clock source will come from one of the high speed oscillators, either the HXT or HIRC oscillators. The high speed oscillator will however first be divided by a ratio ranging from 1 to 64, the actual ratio being selected by the

CKS2~CKS0 and HLCLK bits in the SMOD register. Although a high speed oscillator is used, running the microcontroller at a divided clock ratio reduces the operating current.

SLOW Mode

This is also a mode where the microcontroller operates normally although now with a slower speed clock source. The clock source is provided by the LIRC. Running the microcontroller in this mode allows it to run with much lower operating currents. In the SLOW Mode, the f

H

is off.

IDLE0 Mode

The IDLE0 Mode is entered when a HALT instruction is executed and when the IDLEN bit in the

SMOD register is high and the FSYSON bit in the CTRL register is low. In the IDLE0 Mode the system oscillator will be inhibited from driving the CPU but some peripheral functions will remain operational such as the Watchdog Timer, TMs and SIM. In the IDLE0 Mode, the system oscillator will be stopped. In the IDLE0 Mode the Watchdog Timer clock, f

SUB

, will be on.

IDLE1 Mode

The IDLE1 Mode is entered when an HALT instruction is executed and when the IDLEN bit in the SMOD register is high and the FSYSON bit in the CTRL register is high. In the IDLE1 Mode the system oscillator will be inhibited from driving the CPU but may continue to provide a clock source to keep some peripheral functions operational such as the Watchdog Timer, TMs and SIM. In the IDLE1 Mode, the system oscillator will continue to run, and this system oscillator may be high speed or low speed system oscillator. In the IDLE1 Mode the Watchdog Timer clock, f

SUB

, will be on.

SLEEP0 Mode

The SLEEP0 Mode is entered when an HALT instruction is executed and when the IDLEN bit in the SMOD register is low. In the SLEEP0 mode the CPU will be stopped, and the f

L

clock will be stopped too, and the Watchdog Timer function is disabled. In this mode, the LVDEN is must set to

"0". If the LVDEN is set to "1", it won’t enter the SLEEP0 Mode.

SLEEP1 Mode

The SLEEP1 Mode is entered when an HALT instruction is executed and when the IDLEN bit in the

SMOD register is low. In the SLEEP1 mode the CPU will be stopped. However, the f

SUB clock will continue to operate if the LVDEN is "1" or the Watchdog Timer function is enabled

.

5� De�e��e� 01� �01�

HT68FB540/HT68FB550/HT68FB560

I/O Flash USB MCU with SPI

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HT68FB540/HT68FB550/HT68FB560

I/O Flash USB MCU with SPI

Rev. 1.40

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I/O Flash USB MCU with SPI

Control Register

A single register, SMOD is used for overall control of the internal clocks within the device.

SMOD Register

Bit

Na�e

R/W

POR

Bit 7~5

Bit 4

Bit 3

Bit 2

Bit 1

7

CKS�

R/W

0

6

CKS1

R/W

0

5

CKS0

R/W

0

4

FSTEN

R/W

0

3

LTO

R

0

2

HTO

R

0

1

IDLEN

R/W

1

0

HLCLK

R/W

1

CKS2~CKS0

: The system clock selection when HLCLK is "0".

000: f

001: f

L

( f

L

(f

LIRC

LIRC

010: f

H

/64

011: f

H

/32

100: f

H

/16

H

/8

)

)

101: f

110: f

H

/4

111: f

H

/2

These three bits are used to select which clock is used as the system clock source. In addition to the system clock source, which can be the LIRC, a divided version of the high speed system oscillator can also be chosen as the system clock source.

FSTEN

: Fast Wake-up Control (only for HXT )

0: disable

1: enable

This is the Fast Wake-up Control bit which determines if the f

L

clock source is initially used after the device wakes up. When the bit is high, the f

L

clock source can be used as a temporary system clock to provide a faster wake up time as the f

L

clock is available.

LTO

: Low speed system oscillator ready flag

0: not ready

1: ready

This is the low speed system oscillator ready flag which indicates when the low speed system oscillator is stable after power on reset or a wake-up has occurred. The flag will be low when in the SLEEP0 Mode but after a wake-up has occurred, the flag will change to a high level after 1~2 clock cycles if the LIRC oscillator is used.

HTO

: High speed system oscillator ready flag

0: not ready

1: ready

This is the high speed system oscillator ready flag which indicates when the high speed system oscillator is stable. This flag is cleared to "0" by hardware when the device is powered on and then changes to a high level after the high speed system oscillator is stable. Therefore this flag will always be read as "1" by the application program after device power-on. The flag will be low when in the SLEEP or IDLE0 Mode but after a wake-up has occurred, the flag will change to a high level after 1024 clock cycles if the HXT oscillator is used and after 1024 clock cycles if the HIRC oscillator is used.

IDLEN

: IDLE Mode control

0: disable

1: enable

This is the IDLE Mode Control bit and determines what happens when the HALT instruction is executed. If this bit is high, when a HALT instruction is executed the device will enter the IDLE Mode. In the IDLE1 Mode the CPU will stop running but the system clock will continue to keep the peripheral functions operational, if

FSYSON bit is high. If FSYSON bit is low, the CPU and the system clock will all stop in IDLE0 mode. If the bit is low the device will enter the SLEEP Mode when a HALT instruction is executed.

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I/O Flash USB MCU with SPI

Bit 0

HLCLK

: system clock selection

0: f

H

/2~f

H

/64 or f

L

1: f

H

This bit is used to select if the f

H

clock or the f

H

/2~f

H

/64 or f

L

clock is used as the system clock. When the bit is high the f

H

clock will be selected and if low the f

H

/2~f

H

/64 or f

L

clock will be selected. When system clock switches from the f

H

clock to the f

L

clock and the f

H

clock will be automatically switched off to conserve power.

Fast Wake-up

To minimise power consumption the device can enter the SLEEP or IDLE0 Mode, where the system clock source to the device will be stopped. However when the device is woken up again, it can take a considerable time for the original system oscillator to restart, stabilise and allow normal operation to resume. To ensure the device is up and running as fast as possible a Fast Wake-up function is provided, which allows f

L

, namely the LIRC oscillator, to act as a temporary clock to first drive the system until the original system oscillator has stabilised. As the clock source for the Fast Wake-up function is f

L

, the Fast Wake-up function is only available in the SLEEP1 and IDLE0 modes. When the device is woken up from the SLEEP0 mode, the Fast Wake-up function has no effect because the f

L

clock is stopped. The Fast Wake-up enable/disable function is controlled using the FSTEN bit in the SMOD register.

If the HXT oscillator is selected as the NORMAL Mode system clock, and if the Fast Wake-up function is enabled, then it will take one to two t

L

clock cycles of the LIRC oscillator for the system to wake-up. The system will then initially run under the f

L

clock source until 1024 HXT clock cycles have elapsed, at which point the HTO flag will switch high and the system will switch over to operating from the HXT oscillator.

If the HIRC oscillator or LIRC oscillator is used as the system oscillator then it will take 1024 clock cycles of the HIRC or 1~2 cycles of the LIRC to wake up the system from the SLEEP or IDLE0

Mode. The Fast Wake-up bit, FSTEN will have no effect in these cases.

System

Oscillator

HXT

HIRC

LIRC

FSTEN

Bit

0

1 x x

Wake-up Time

(SLEEP0 Mode)

Wake-up Time

(SLEEP1 Mode)

10�4 HXT �y�les 10�4 HXT �y�les

Wake-up Time

(IDLE0 Mode)

10�4 HXT �y�les

1~� f

L

�y�les (Syste� �uns with f ove� to �un with the HXT �lo�k)

L

first fo� 10�4 HXT �y�les and then swit�hes

10�4 HIRC �y�les 10�4 HIRC �y�les

1~� LIRC �y�les 1~� LIRC �y�les

Wake-up Time

(IDLE1 Mode)

1~� HXT �y�les

1~� HXT �y�les

1~� HIRC �y�les

1~� LIRC �y�les

Wake-Up Times

Note that if the Watchdog Timer is disabled, which means that the LIRC is off, then there will be no

Fast Wake-up function available when the device wakes-up from the SLEEP0 Mode.

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HT68FB540/HT68FB550/HT68FB560

I/O Flash USB MCU with SPI

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I/O Flash USB MCU with SPI

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I/O Flash USB MCU with SPI

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Operating Mode Switching and Wake-up

The device can switch between operating modes dynamically allowing the user to select the best performance/power ratio for the present task in hand. In this way microcontroller operations that do not require high performance can be executed using slower clocks thus requiring less operating current and prolonging battery life in portable applications.

In simple terms, Mode Switching between the NORMAL Mode and SLOW Mode is executed using the HLCLK bit and CKS2~CKS0 bits in the SMOD register while Mode Switching from the

NORMAL/SLOW Modes to the SLEEP/IDLE Modes is executed via the HALT instruction. When a HALT instruction is executed, whether the device enters the IDLE Mode or the SLEEP Mode is determined by the condition of the IDLEN bit in the SMOD register and FSYSON in the CTRL register.

When the HLCLK bit switches to a low level, which implies that clock source is switched from the high speed clock source, f

H, to the clock source, f

H

/2~f

H

/64 or f

L

. If the clock is from the f

L

, the high speed clock source will stop running to conserve power. When this happens it must be noted that the f

H

/16 and f

H

/64 internal clock sources will also stop running, which may affect the operation of other internal functions such as the TMs and the SIM. The accompanying flowchart shows what happens when the device moves between the various operating modes.

NORMAL Mode to SLOW Mode Switching

When running in the NORMAL Mode, which uses the high speed system oscillator, and therefore consumes more power, the system clock can switch to run in the SLOW Mode by set the HLCLK bit to "0" and set the CKS2~CKS0 bits to "000" or "001" in the SMOD register. This will then use the low speed system oscillator which will consume less power. Users may decide to do this for certain operations which do not require high performance and can subsequently reduce power consumption.

The SLOW Mode is sourced from the LIRC oscillator and therefore requires these oscillators to be stable before full mode switching occurs. This is monitored using the LTO bit in the SMOD register.

Rev. 1.40 55 De�e��e� 01� �01�

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I/O Flash USB MCU with SPI

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I/O Flash USB MCU with SPI

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I/O Flash USB MCU with SPI

SLOW Mode to NORMAL Mode Switching

In SLOW Mode the system uses the LIRC low speed system oscillator. To switch back to the

NORMAL Mode, where the high speed system oscillator is used, the HLCLK bit should be set to "1" or HLCLK bit is "0", but CKS2~CKS0 is set to "010", "011", "100", "101", "110"or "111".

As a certain amount of time will be required for the high frequency clock to stabilise, the status of the HTO bit is checked. The amount of time required for high speed system oscillator stabilization depends upon which high speed system oscillator type is used.

Entering the SLEEP0 Mode

There is only one way for the device to enter the SLEEP0 Mode and that is to execute the "HALT" instruction in the application program with the IDLEN bit in SMOD register equal to "0" and the

WDT and LVD both off. When this instruction is executed under the conditions described above, the following will occur:

• The system clock and WDT clock will be stopped and the application program will stop at the

"HALT" instruction.

• The Data Memory contents and registers will maintain their present condition.

• The WDT will be cleared and stopped.

• The I/O ports will maintain their present conditions.

• In the status register, the Power Down flag, PDF, will be set and the Watchdog time-out flag, TO, will be cleared.

Entering the SLEEP1 Mode

There is only one way for the device to enter the SLEEP1 Mode and that is to execute the "HALT" instruction in the application program with the IDLEN bit in SMOD register equal to "0"and the

WDT or LVD on. When this instruction is executed under the conditions described above, the following will occur:

• The system clock will be stopped and the application program will stop at the "HALT" instruction, but the WDT or LVD will remain with the clock source coming from the f

SUB

clock.

• The Data Memory contents and registers will maintain their present condition.

• The WDT will be cleared and resume counting if the WDT is enabled.

• The I/O ports will maintain their present conditions.

• In the status register, the Power Down flag, PDF, will be set and the Watchdog time-out flag, TO, will be cleared.

Rev. 1.40

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HT68FB540/HT68FB550/HT68FB560

I/O Flash USB MCU with SPI

Entering the IDLE0 Mode

There is only one way for the device to enter the IDLE0 Mode and that is to execute the "HALT" instruction in the application program with the IDLEN bit in SMOD register equal to "1" and the

FSYSON bit in CTRL register equal to "0". When this instruction is executed under the conditions described above, the following will occur:

• The system clock will be stopped and the application program will stop at the "HALT" instruction, but the f

SUB clock will be on.

• The Data Memory contents and registers will maintain their present condition.

• The WDT will be cleared and resume counting if the WDT is enabled.

• The I/O ports will maintain their present conditions.

• In the status register, the Power Down flag, PDF, will be set and the Watchdog time-out flag, TO, will be cleared.

Entering the IDLE1 Mode

There is only one way for the device to enter the IDLE1 Mode and that is to execute the "HALT" instruction in the application program with the IDLEN bit in SMOD register equal to "1" and the

FSYSON bit in CTRL register equal to "1". When this instruction is executed under the conditions described above, the following will occur:

• The system clock and f

SUB clock will be on and the application program will stop at the"HALT" instruction.

• The Data Memory contents and registers will maintain their present condition.

• The WDT will be cleared and resume counting if the WDT is enabled.

• The I/O ports will maintain their present conditions.

• In the status register, the Power Down flag, PDF, will be set and the Watchdog time-out flag, TO, will be cleared.

Standby Current Considerations

As the main reason for entering the SLEEP or IDLE Mode is to keep the current consumption of the device to as low a value as possible, perhaps only in the order of several micro-amps except in the

IDLE1 Mode, there are other considerations which must also be taken into account by the circuit designer if the power consumption is to be minimised. Special attention must be made to the I/O pins on the device. All high-impedance input pins must be connected to either a fixed high or low level as any floating input pins could create internal oscillations and result in increased current consumption.

This also applies to devices which have different package types, as there may be unbonded pins.

These must either be setup as outputs or if setup as inputs must have pull-high resistors connected.

Care must also be taken with the loads, which are connected to I/O pins, which are setup as outputs.

These should be placed in a condition in which minimum current is drawn or connected only to external circuits that do not draw current, such as other CMOS inputs. Also note that additional standby current will also be required if the LIRC oscillator is enabled.

In the IDLE1 Mode the system oscillator is on, if the system oscillator is from the high speed system oscillator, the additional standby current will also be perhaps in the order of several hundred microamps

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58 De�e��e� 01� �01�

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I/O Flash USB MCU with SPI

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I/O Flash USB MCU with SPI

Rev. 1.40

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I/O Flash USB MCU with SPI

Wake-up

After the system enters the SLEEP or IDLE Mode, it can be woken up from one of various sources listed as follows:

• An external or USB reset

• An external rising or falling edge on PA and a falling edge on PB~PE, except for PE1

• A system interrupt

• A WDT overflow

If the system is woken up by an external or USB reset, the device will experience a full system reset, however, if the device is woken up by a WDT overflow, a Watchdog Timer reset will be initiated.

Although both of these wake-up methods will initiate a reset operation, the actual source of the wake-up can be determined by examining the TO and PDF flags. The PDF flag is cleared by a system power-up or executing the clear Watchdog Timer instructions and is set when executing the

"HALT" instruction. The TO flag is set if a WDT time-out occurs, and causes a wake-up that only resets the Program Counter and Stack Pointer, the other flags remain in their original status.

Each pin on Ports can be setup using the PAWU and PXWU registers to permit a negative transition on the pin to wake-up the system. When a Port pin wake-up occurs, the program will resume execution at the instruction following the "HALT" instruction. If the system is woken up by an interrupt, then two possible situations may occur. The first is where the related interrupt is disabled or the interrupt is enabled but the stack is full, in which case the program will resume execution at the instruction following the "HALT" instruction. In this situation, the interrupt which woke-up the device will not be immediately serviced, but will rather be serviced later when the related interrupt is finally enabled or when a stack level becomes free. The other situation is where the related interrupt is enabled and the stack is not full, in which case the regular interrupt response takes place. If an interrupt request flag is set high before entering the SLEEP or IDLE Mode, the wake-up function of the related interrupt will be disabled.

Programming Considerations

• If the device is woken up from the SLEEP0 Mode to the NORMAL Mode, the high speed system oscillator needs an SST period. The device will execute first instruction after HTO is "1".

• If the device is woken up from the SLEEP1 Mode to NORMAL Mode, and the system clock source is from HXT oscillator and FSTEN is "1", the system clock can be switched to the LIRC oscillator after wake up.

• There are peripheral functions, such as WDT, TMs and SIM, for which the f

SYS is used. If the system clock source is switched from f

H

to f

L

, the clock source to the peripheral functions mentioned above will change accordingly.

• The on/off condition of f

L

depends upon whether the WDT is enabled or disabled as the WDT clock source is generated from f

L

.

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I/O Flash USB MCU with SPI

Watchdog Timer

The Watchdog Timer is provided to prevent program malfunctions or sequences from jumping to unknown locations, due to certain uncontrollable external events such as electrical noise.

Watchdog Timer Clock Source

The Watchdog Timer clock source is provided by the internal clock, f

SUB, which is sourced from the

LIRC oscillator. The Watchdog Timer source clock is then subdivided by a ratio of 2

8

to 2

18 to give longer timeouts, the actual value being chosen using the WS2~WS0 bits in the WDTC register. The

LIRC internal oscillator has an approximate period of 32kHz at a supply voltage of 5V.

However, it should be noted that this specified internal clock period can vary with VDD, temperature and process variations. The WDT function is allowed to enable or disable by setting the WDTC register data.

Watchdog Timer Control Register

A single register, WDTC, controls the required timeout period as well as the enable/disable operation. The WRF software reset flag will be indicated in the CTRL register.

WDTC Register

Bit

Na�e

R/W

7

WE4

R/W

POR 0

Bit 7~3

Bit 2~0

6

WE3

R/W

1

5

WE�

R/W

0

4

WE1

R/W

1

3

WE0

R/W

0

2

WS�

R/W

0

1

WS1

R/W

1

0

WS0

R/W

1

WE4~WE0

: WDT function software control

10101: WDT disabled

01010: WDT enabled

Other values: Reset MCU

When these bits are changed to any other values due to environmental noise the microcontroller will be reset; this reset operation will be activated after 2~3 LIRC clock cycles and the WRF bit in the CTRL register will be set to 1 to indicate the reset source.

WS2, WS1, WS0

: WDT time-out period selection

000: 2

8

/f

SUB

001: 2 10 /f

SUB

010: 2

12

/f

SUB

011: 2

14

/f

SUB

100: 2

15

/f

SUB

101: 2

16

110: 2 17

/f

SUB

/f

SUB

111: 2

18

/f

SUB

These three bits determine the division ratio of the Watchdog Timer source clock, which in turn determines the time-out period.

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�0 De�e��e� 01� �01�

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I/O Flash USB MCU with SPI

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I/O Flash USB MCU with SPI

Rev. 1.40

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I/O Flash USB MCU with SPI

CTRL Register

Bit

Na�e

R/W

POR

Bit 7

Bit 6~3

Bit 2

Bit 1

Bit 0

7

FSYSON

R/W

0

6

5

4

3

2

LVRF

R/W x

1

LRF

R/W

0

0

WRF

R/W

0

FSYSON

: f

SYS

control in IDLE Mode

Described elsewhere.

"—": unimplemented, read as "0"

LVRF

: LVR function reset flag

Described elsewhere.

LRF

: LVR control register software reset flag

Described elsewhere.

WRF

: WDT control register software reset flag

0: not occurred

1: occurred

This bit is set to 1 by the WDT Control register software reset and cleared by the application program. Note that this bit can only be cleared to 0 by the application program.

Watchdog Timer Operation

The Watchdog Timer operates by providing a device reset when its timer overflows. This means that in the application program and during normal operation the user has to strategically clear the

Watchdog Timer before it overflows to prevent the Watchdog Timer from executing a reset. This is done using the clear watchdog instructions. If the program malfunctions for whatever reason, jumps to an unknown location, or enters an endless loop, these clear instructions will not be executed in the correct manner, in which case the Watchdog Timer will overflow and reset the device. With regard to the Watchdog Timer enable/disable function, there are also five bits, WE4~WE0, in the WDTC register to offer additional enable/disable and reset control of the Watchdog Timer.

WDT Enable/Disabled using the WDT Control Register

The WDT is enabled/disabled using the WDT control register, the WE4~WE0 values can determine which mode the WDT operates in. The WDT will be disabled when the WE4~WE0 bits are set to a value of 10101B. The WDT function will be enabled if the WE4~WE0 bit value is equal to 01010B.

If the WE4~WE0 bits are set to any other values other than 01010B and 10101B, it will reset the device after 2~3 LIRC clock cycles. After power on these bits will have the value of 01010B.

WDT

Cont�olled �y WDT Cont�ol Registe�

WE4~WE0 Bits

10101B

01010B

Any othe� value

WDT Function

Disa�le

Ena�le

Reset MCU

Watchdog Timer Enable/Disable Control

Under normal program operation, a Watchdog Timer time-out will initialise a device reset and set the status bit TO. However, if the system is in the SLEEP or IDLE Mode, when a Watchdog Timer time-out occurs, the TO bit in the status register will be set and only the Program Counter and Stack

Pointer will be reset. Three methods can be adopted to clear the Watchdog Timer contents. The first is a WDT reset, which means a value other than 01010B or 10101B is written into the WE4~WE0 bit locations, the second is to use the Watchdog Timer software clear instructions and the third is via a HALT instruction. There is only one method of using software instruction to clear the Watchdog

Timer and that is to use the single "CLR WDT" instruction to clear the WDT.

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I/O Flash USB MCU with SPI

The maximum time out period is when the 2

18

division ratio is selected. As an example, with a

32kHz LIRC oscillator as its source clock, this will give a maximum watchdog period of around 8 seconds for the 2

18

division ratio, and a minimum timeout of 7.8ms for the 2

8

division ration.

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Watchdog Timer

 

Reset and Initialisation

A reset function is a fundamental part of any microcontroller ensuring that the device can be set to some predetermined condition irrespective of outside parameters. A hardware reset will of course be automatically implemented after the device is powered-on, however there are a number of other hardware and software reset sources that can be implemented dynamically when the device is running.

Reset Overview

The most important reset condition is after power is first applied to the microcontroller. In this case, internal circuitry will ensure that the microcontroller, after a short delay, will be in a well defined state and ready to execute the first program instruction. After this power-on reset, certain important internal registers will be set to defined states before the program instructions commence execution.

One of these registers is the Program Counter, which will be reset to zero forcing the microcontroller to begin program execution from the lowest Program Memory address.

The devices provide several reset sources to generate the internal reset signal, providing extended

MCU protection. The different types of resets are listed in the accompanying table.

Reset Name

Powe�-on �eset

Reset pin

Low voltage �eset

Wat�hdog �eset

WDTC �egiste� setting softwa�e �eset

LVRC �egiste� setting sof�wa�e �eset

Abbreviation Indication Bit Register

POR — —

RES

LVR

WDT

LVRF

TO

CTRL

STATUS

WRF

LRF

CTRL

CTRL

Notes

Auto gene�ated at powe� on

Ha�dwa�e �eset

Low VDD voltage

W�ite to WDTC �egiste�

W�ite to LVRC �egiste�

Reset Source Summary

In addition to the power-on reset, situations may arise where it is necessary to forcefully apply a reset condition when the microcontroller is running. One example of this is where after power has been applied and the microcontroller is already running, the RES line is forcefully pulled low. In such a case, known as a normal operation reset, some of the registers remain unchanged allowing the microcontroller to proceed with normal operation after the reset line is allowed to return high.

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I/O Flash USB MCU with SPI

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I/O Flash USB MCU with SPI

Another type of reset is when the Watchdog Timer overflows and resets the microcontroller. All types of reset operations result in different register conditions being setup. Another reset exists in the form of a Low Voltage Reset, LVR, where a full reset, similar to the RES reset is implemented in situations where the power supply voltage falls below a certain threshold.

Reset Functions

There are several ways in which a microcontroller reset can occur, through events occurring both internally and externally:

Power-on Reset

The most fundamental and unavoidable reset is the one that occurs after power is first applied to the microcontroller. As well as ensuring that the Program Memory begins execution from the first memory address, a power-on reset also ensures that certain other registers are preset to known conditions. All the I/O port and port control registers will power up in a high condition ensuring that all pins will be first set to inputs.

Note: t

RSTD

is power-on delay, typical time= 50ms

Power-on Reset Timing Chart

RES Pin

Although the microcontroller has an internal RC reset function, if the VDD power supply rise time is not fast enough or does not stabilise quickly at power-on, the internal reset function may be incapable of providing proper reset operation. For this reason it is recommended that an external

RC network is connected to the RES pin, whose additional time delay will ensure that the RES pin remains low for an extended period to allow the power supply to stabilise. During this time delay, normal operation of the microcontroller will be inhibited. After the RES line reaches a certain voltage value, the reset delay time t

RSTD

is invoked to provide an extra delay time after which the microcontroller will begin normal operation. The abbreviation SST in the figures stands for System

Start-up Timer.

For most applications a resistor connected between VDD and the RES pin and a capacitor connected between VSS and the RES pin will provide a suitable external reset circuit. Any wiring connected to the RES pin should be kept as short as possible to minimise any stray noise interference.

Rev. 1.40 �3 De�e��e� 01� �01�

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I/O Flash USB MCU with SPI

For applications that operate within an environment where more noise is present the Enhanced Reset

Circuit shown is recommended.

Note: "*" it is recommended that this component is added for added ESD protection

"**" It is recommended that this component is added in environments where power line noise is significant.

External RES Circuit

More information regarding external reset circuits is located in Application Note HA0075E on the

Holtek website.

Pulling the RES Pin low using external hardware will also execute a device reset. In this case, as in the case of other resets, the Program Counter will reset to zero and program execution initiated from this point.

Note: t

RSTD

is power-on delay, typical time= 16.7ms

RES Reset Timing Chart

Low Voltage Reset – LVR

The microcontroller contains a low voltage reset circuit in order to monitor the supply voltage of the device and provide an MCU reset should the value fall below a certain predefined level.

• LVR Operation

The LVR function is always enabled with a specific LVR voltage V

LVR

. If the supply voltage of the device drops to within a range of 0.9V~V

LVR

such as might occur when changing the battery in battery powered applications, the LVR will automatically reset the device internally and the LVRF bit in the CTRL register will also be set to 1. For a valid LVR signal, a low supply voltage, i.e., a voltage in the range between 0.9V~V

LVR

must exist for a time greater than that specified by t

LVR

in the A.C. characteristics. If the low supply voltage state does not exceed this value, the LVR will ignore the low supply voltage and will not perform a reset function. The actual V

LVR

value can be selected by the LVS bits in the LVRC register. If the LVS7~LVS0 bits are changed to some different values by environmental noise, the LVR will reset the device after 2~3 LIRC clock cycles. When this happens, the LRF bit in the CTRL register will be set to 1. After power on the register will have the value of 01010101B. Note that the LVR function will be automatically disabled when the device enters the power down mode.

�4 De�e��e� 01� �01�

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Rev. 1.40

�4 De�e��e� 01� �01�

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Note: t

RSTD

is power-on delay, typical time= 16.7ms

Low Voltage Reset Timing Chart

• LVRC Register

Bit

Na�e

R/W

POR

Bit 7

Bit 6~3

Bit 2

Bit 1

Bit 0

7

LVS7

R/W

0

6

LVS�

R/W

1

5

LVS5

R/W

0

4

LVS4

R/W

1

3

LVS3

R/W

0

2

LVS�

R/W

1

1

LVS1

R/W

0

0

LVS0

R/W

1

Bit 7~0

LVS7~LVS0

: LVR Voltage Select control

01010101: 2.1V

00110011: 2.55V

10011001: 3.15V

10101010: 3.8V

Any other value: Generates MCU reset–register is reset to POR value When an actual low voltage condition occurs, as specified by one of the four defined LVR voltage values above, an MCU reset will be generated. The reset operation will be activated after 2~3 LIRC clock cycles. In this situation the register contents will remain the same after such a reset occurs. Any register value, other than the four defined LVR values above, will also result in the generation of an MCU reset. The reset operation will be activated after 2~3 LIRC clock cycles. However in this situation the register contents will be reset to the POR value.

CTRL Register

Bit

Na�e

R/W

POR

7

FSYSON

R/W

0

6

5

4

3

2

LVRF

R/W x

1

LRF

R/W

0

0

WRF

R/W

0

FSYSON

: f

SYS

Control in IDLE Mode

Describe elsewhere.

"—": unimplemented, read as "0"

LVRF

: LVR function reset flag

0: not occur

1: occurred

This bit is set to 1 when a specific Low Voltage Reset situation condition occurs. This bit can only be cleared to 0 by the application program.

LRF

: LVR Control register software reset flag

0: not occur

1: occurred

This bit is set to 1 if the LVRC register contains any non defined LVR voltage register values. This in effect acts like a software reset function. This bit can only be cleared to

0 by the application program.

WRF

: WDT Control register software reset flag

Describe elsewhere.

Rev. 1.40 �5 De�e��e� 01� �01�

Rev. 1.40

HT68FB540/HT68FB550/HT68FB560

I/O Flash USB MCU with SPI

Watchdog Time-out Reset during Normal Operation

The Watchdog time-out Reset during normal operation is the same as a hardware RES pin reset except that the Watchdog time-out flag TO will be set to "1".

Note: t

RSTD

is power-on delay, typical time= 16.7ms

WDT Time-out Reset during Normal Operation Timing Chart

Watchdog Time-out Reset during SLEEP or IDLE Mode

The Watchdog time-out Reset during SLEEP or IDLE Mode is a little different from other kinds of reset. Most of the conditions remain unchanged except that the Program Counter and the Stack

Pointer will be cleared to "0" and the TO flag will be set to "1". Refer to the A.C. Characteristics for t

SST

details.

Note:The t

SST

is 15~16 clock cycles if the system clock source is provided by HIRC. The t

SST

is

1024 clock for HXT. The t

SST

is 1~2 clock for LIRC.

WDT Time-out Reset during SLEEP or IDLE Timing Chart

• WDTC Register Software Reset

A WDTC software reset will be generated when a value other than "10101" or "01010", exist in the highest five bits of the WDTC register. The WRF bit in the CTRL register will be set high when this occurs, thus indicating the generation of a WDTC software reset.

• WDTC Register

Bit

Na�e

R/W

7

WE4

R/W

POR 0

Bit 7~3

Bit 2~0

6

WE3

R/W

1

5

WE�

R/W

0

4

WE1

R/W

1

3

WE0

R/W

0

WE4, WE3, WE2, WE1, WE0

: WDT Software Control

10101: WDT disable

01010: WDT enable (default)

Other: MCU reset

WS2, WS1, WS0

: WDT time-out period selection.

Described elsewhere

2

WS�

R/W

0

1

WS1

R/W

1

0

WS0

R/W

1

�� De�e��e� 01� �01�

HT68FB540/HT68FB550/HT68FB560

I/O Flash USB MCU with SPI

Rev. 1.40 �7 De�e��e� 01� �01�

HT68FB540/HT68FB550/HT68FB560

I/O Flash USB MCU with SPI

HT68FB540/HT68FB550/HT68FB560

I/O Flash USB MCU with SPI

Reset Initial Conditions

The different types of reset described affect the reset flags in different ways. These flags, known as PDF and TO are located in the status register and are controlled by various microcontroller operations, such as the SLEEP or IDLE Mode function or Watchdog Timer. The reset flags are shown in the table:

TO

0 u

1

1

PDF

0 u u

1

RESET Conditions

Powe�-on �eset

RES� LVR o� USB �eset du�ing NORMAL o� SLOW Mode ope�ation

WDT ti�e-out �eset du�ing NORMAL o� SLOW Mode ope�ation

WDT ti�e-out �eset du�ing IDLE o� SLEEP Mode ope�ation

"u"stands fo� un�hanged

The following table indicates the way in which the various components of the microcontroller are affected after a power-on reset occurs.

Item

P�og�a� Counte�

Inte��upts

WDT

Ti�e�/Event Counte�

Input/Output Po�ts

Sta�k Pointe�

Condition After RESET

Reset to ze�o

All inte��upts will �e disa�led

Clea� afte� �eset� WDT �egins �ounting

Ti�e� Counte� will �e tu�ned off

I/O po�ts will �e setup as inputs

Sta�k Pointe� will point to the top of the sta�k

The different kinds of resets all affect the internal registers of the microcontroller in different ways.

To ensure reliable continuation of normal program execution after a reset occurs, it is important to know what condition the microcontroller is in after a particular reset occurs. The following table describes how each type of reset affects each of the microcontroller internal registers. Note that where more than one package type exists the table will reflect the situation for the larger package type.

Rev. 1.40

�� De�e��e� 01� �01� Rev. 1.40 �7 De�e��e� 01� �01�

HT68FB540/HT68FB550/HT68FB560

I/O Flash USB MCU with SPI

WDTC

FRCR

FCR

FARL

FARH

FD0L

FD0H

FD1L

MFI1

PA

PAC

PB

PBC

PE

PEC

FD1H

FD�L

FD�H

FD3L

FD3H

I�CTOC

SIMC0

SIMC1

BP

SMOD

INTEG

LVDC

INTC0

INTC1

INTC�

MFI0

MP0

MP1

ACC

PCL

TBLP

TBLH

TBHP

STATUS

Register

0000 0000

1111 1111

1111 1111

-111 1111

-111 1111

---- -101

---- -111

0101 0011

- - - 0 - - - 0

0000 0000 xxxx xxxx

---- xxxx xxxx xxxx xxxx xxxx xxxx xxxx

• The HT68FB540 register states are summarized below:

Reset

(Power On)

xxxx xxxx

WDT Timeout/WDTC

Software

Reset (Normal

Operation)

xxxx xxxx

RES

Reset/LVRC

Software

Reset (Normal

Operation)

xxxx xxxx

RES

Reset

(HALT)

xxxx xxxx

WDT

Time-out

(HALT)*

uuuu uuuu xxxx xxxx xxxx xxxx

0000 0000 xxxx xxxx uuuu uuuu

0000 0000 xxxx xxxx uuuu uuuu

0000 0000 xxxx xxxx uuuu uuuu

0000 0000 uuuu uuuu uuuu uuuu

0000 0000 xxxx xxxx xxxx xxxx

---- xxxx

--00 xxxx uuuu uuuu uuuu uuuu

---- uuuu

--1u uuuu uuuu uuuu uuuu uuuu

---- uuuu

--uu uuuu uuuu uuuu uuuu uuuu

---- uuuu

--01 uuuu uuuu uuuu uuuu uuuu

---- uuuu

--11 uuuu

- - - - - - - 0

0000 0011

0000 0000

--00 -000

-000 0000

00-0 00-0

0000 0000

0000 0000

- - - - - - - 0

0000 0011

0000 0000

--00 -000

-000 0000

00-0 00-0

0000 0000

0000 0000

- - - - - - - 0

0000 0011

0000 0000

--00 -000

-000 0000

00-0 00-0

0000 0000

0000 0000

- - - - - - - 0

0000 0011

0000 0000

--00 -000

-000 0000

00-0 00-0

0000 0000

0000 0000

- - - - - - - u uuuu uuuu uuuu uuuu

--uu -uuu

-uuu uuuu uu-u uu-u uuuu uuuu uuuu uuuu xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx

0000 0000

1110 000-

1000 0001

0000 0000

1111 1111

1111 1111

-111 1111

-111 1111

---- -101

---- -111

0101 0011

- - - 0 - - - 0

0000 0000 xxxx xxxx

---- xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx

0000 0000

1110 000-

1000 0001

0000 0000

1111 1111

1111 1111

-111 1111

-111 1111

---- -101

---- -111

0101 0011

- - - 0 - - - 0

0000 0000 xxxx xxxx

---- xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx

0000 0000

1110 000-

1000 0001

0000 0000

1111 1111

1111 1111

-111 1111

-111 1111

---- -101

---- -111

0101 0011

- - - 0 - - - 0

0000 0000 xxxx xxxx

---- xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx

0000 0000

1110 000-

1000 0001 uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuuuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu

-uuu uuuu

-uuu uuuu

---- -uuu

---- -uuu uuuu uuuu

- - - u - - - u uuuu uuuu uuuu uuuu

---- uuuu uuuu uuuu uuuu uuuu uuuu uuuu

USB-reset

(Normal)

USB-reset

(HALT)

0000 0000

1111 1111

1111 1111

-111 1111

-111 1111

---- -101

---- -111

0101 0011

- - - 0 - - - 0

0000 0000 xxxx xxxx

---- xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx uuuu uuuu

0000 0000 uuuu uuuu uuuu uuuu

---- uuuu

--uu uuuu

- - - - - - - 0

0000 0011

0000 0000

--00 -000

-000 0000

00-0 00-0

0000 0000

0000 0000 xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx

0000 0000

1110 000-

1000 0001

0000 0000

1111 1111

1111 1111

-111 1111

-111 1111

---- -101

---- -111

0101 0011

- - - 0 - - - 0

0000 0000 xxxx xxxx

---- xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx uuuu uuuu

0000 0000 uuuu uuuu uuuu uuuu

---- uuuu

--uu uuuu

- - - - - - - 0

0000 0011

0000 0000

--00 -000

-000 0000

00-0 00-0

0000 0000

0000 0000 xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx

0000 0000

1110 000-

1000 0001

Rev. 1.40

�8 De�e��e� 01� �01�

HT68FB540/HT68FB550/HT68FB560

I/O Flash USB MCU with SPI

Rev. 1.40 �9 De�e��e� 01� �01�

HT68FB540/HT68FB550/HT68FB560

I/O Flash USB MCU with SPI

Rev. 1.40

�8 De�e��e� 01� �01�

HT68FB540/HT68FB550/HT68FB560

I/O Flash USB MCU with SPI

0000 0000

0000 0000

0000 0000

0000 0000

0000 0000

0000 0000

- - - - - - 0 0

0000 0000

- - - - - - 0 0

0000 0000

0000 0000

0000 0000

- - - - - - 0 0

0000 0000

- - - - - - 0 0

0000 0000

111- --0-

--00 0000 xxxx xxxx

0000 ---0

0000 0000

0000 0000

0000 0000

-0-- --00

-0-- --00

--01 --01

--01 --01

0000 0---

0000 0000

0000 0000

0000 0000

0000 0000

0000 0000

- - - - - - 0 0

0000 0000

- - - - - - 0 0

11xx 000-

Register

Reset

(Power On)

xxxx xxxx

WDT Timeout/WDTC

Software

Reset (Normal

Operation)

xxxx xxxx

RES

Reset/LVRC

Software

Reset (Normal

Operation)

xxxx xxxx

TM1C1

TM1DL

TM1DH

TM1AL

TM1AH

TM�C0

TM�C1

TM�DL

TM0C1

TM0DL

TM0DH

TM0AL

TM0AH

TM0RP

TM1C0

TM�DH

TM�AL

TM�AH

TM3C0

TM3C1

TM3DL

TM3DH

TM3AL

TM3AH

USB_

STAT

SIMD

SIMA/

SIMC�

SPIAC0

SPIAC1

SPIAD

SBSC

PAWU

PADIR

PAPU

PXPU

PXWU

TMPC0

TMPC1

TM0C0

0000 0000 0000 0000 0000 0000

0000 0000

0000 0000

0000 0000

0000 0000

0000 0000

0000 0000

- - - - - - 0 0

0000 0000

- - - - - - 0 0

0000 0000

0000 0000

0000 0000

- - - - - - 0 0

0000 0000

- - - - - - 0 0

0000 0000

111- --0-

--00 0000 xxxx xxxx

0000 ---0

0000 0000

0000 0000

0000 0000

-0-- --00

-0-- --00

--01 --01

--01 --01

0000 0---

0000 0000

0000 0000

0000 0000

0000 0000

0000 0000

- - - - - - 0 0

0000 0000

- - - - - - 0 0

11xx 000-

0000 0000

0000 0000

0000 0000

0000 0000

0000 0000

0000 0000

- - - - - - 0 0

0000 0000

- - - - - - 0 0

0000 0000

0000 0000

0000 0000

- - - - - - 0 0

0000 0000

- - - - - - 0 0

0000 0000

111- --0-

--00 0000 xxxx xxxx

0000 ---0

0000 0000

0000 0000

0000 0000

-0-- --00

-0-- --00

--01 --01

--01 --01

0000 0---

0000 0000

0000 0000

0000 0000

0000 0000

0000 0000

- - - - - - 0 0

0000 0000

- - - - - - 0 0

11xx 000-

RES

Reset

(HALT)

xxxx xxxx

0000 0000

0000 0000

0000 0000

0000 0000

0000 0000

0000 0000

0000 0000

- - - - - - 0 0

0000 0000

- - - - - - 0 0

0000 0000

0000 0000

0000 0000

- - - - - - 0 0

0000 0000

- - - - - - 0 0

0000 0000

111- --0-

--00 0000 xxxx xxxx

0000 ---0

0000 0000

0000 0000

0000 0000

-0-- --00

-0-- --00

--01 --01

--01 --01

0000 0---

0000 0000

0000 0000

0000 0000

0000 0000

0000 0000

- - - - - - 0 0

0000 0000

- - - - - - 0 0

11xx 000-

WDT

Time-out

(HALT)*

uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu

- - - - - - u u uuuu uuuu

- - - - - - u u uuuu uuuu uuuu uuuu uuuu uuuu

- - - - - - u u uuuu uuuu

- - - - - - u u uuuu uuuu uuu- --u-

--uu uuuu uuuu uuuu uuuu ---u uuuu uuuu uuuu uuuu uuuu uuuu

-u-- --uu

-u-- --uu

--uu --uu

--uu --uu uuuu u--uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu

- - - - - - u u uuuu uuuu

- - - - - - u u

11xx 000-

USB-reset

(Normal)

USB-reset

(HALT)

xxxx xxxx

0000 0000

0000 0000

0000 0000

0000 0000

0000 0000

0000 0000

0000 0000

- - - - - - 0 0

0000 0000

- - - - - - 0 0

0000 0000

0000 0000

0000 0000

- - - - - - 0 0

0000 0000

- - - - - - 0 0

0000 0000

111- --0-

--00 0000 xxxx xxxx

0000 ---0

0000 0000

0000 0000

0000 0000

-0-- --00

-0-- --00

--01 --01

--01 --01

0000 0---

0000 0000

0000 0000

0000 0000

0000 0000

0000 0000

- - - - - - 0 0

0000 0000

- - - - - - 0 0

11xx 000xxxx xxxx

0000 0000

0000 0000

0000 0000

0000 0000

0000 0000

0000 0000

- - - - - - 0 0

0000 0000

- - - - - - 0 0

0000 0000

0000 0000

0000 0000

- - - - - - 0 0

0000 0000

- - - - - - 0 0

0000 0000

111- --0-

--00 0000 xxxx xxxx

0000 ---0

0000 0000

0000 0000

0000 0000

-0-- --00

-0-- --00

--01 --01

--01 --01

0000 0---

0000 0000

0000 0000

0000 0000

0000 0000

0000 0000

0000 0000

- - - - - - 0 0

0000 0000

- - - - - - 0 0

11xx 000-

Rev. 1.40 �9 De�e��e� 01� �01�

HT68FB540/HT68FB550/HT68FB560

I/O Flash USB MCU with SPI

Register

UINT

USC

USR

UCC

AWR

STLI

STLO

SIES

MISC

UFIEN

FIFO0

FIFO1

FIFO�

FIFO3

UFOEN

UFC0

PAPS0

PAPS1

SYSC

CTRL

LVRC

Note: " * " stands for "warm reset"

" - " not implement

" u " stands for "unchanged"

" x " stands for "unknown"

---- 0000

1000 0000

---- 0000

0000 0-00

0000 0000

---- 0000

---- 0000

00-0 0000

000- 0000

---- 0000 xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx

---- 0000

0000 00--

0000 0000

0000 0000

000- -0--

0--- -x00

0101 0101

Reset

(Power On)

WDT Timeout/WDTC

Software

Reset (Normal

Operation)

---- uuuu uuuu xuux

---- uuuu uuuu u-uu uuuu uuuu

---- uuuu

---- uuuu uu-x xuuu xxu- uuuu

---- uuuu xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx

---- uuuu uuuu uu--

0000 0000

0000 0000

000- -0--

0--- -x00

0101 0101

RES

Reset/LVRC

Software

Reset (Normal

Operation)

---- 0000

1000 0000

---- 0000

0000 0-00

0000 0000

---- 0000

---- 0000

00-0 0000

000- 0000

---- 0000 xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx

---- 0000

0000 00--

0000 0000

0000 0000

000- -0--

0--- -x00

0101 0101

RES

Reset

(HALT)

WDT

Time-out

(HALT)*

---- 0000

1000 0000

---- 0000

0000 0-00

0000 0000

---- uuuu uuuu xuux

---- uuuu uuuu u-uu uuuu uuuu

---- 0000 ---- uuuu

---- 0000 ---- uuuu

00-0 0000

000- 0000 uu-x xuuu xxu- uuuu

---- 0000 xxxx xxxx xxxx xxxx xxxx xxxx

---- uuuu xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx

---- 0000

0000 00--

0000 0000

0000 0000

000- -0--

0--- -x00

0101 0101 xxxx xxxx

---- uuuu uuuu uu-uuuu uuuu uuuu uuuu uuu- -u-u--- -xuu uuuu uuuu

USB-reset

(Normal)

USB-reset

(HALT)

---- 0000

1uuu 0100

---- 0000

0uu0 u-00

0000 0000

---- 0000

---- 0000

00-0 0000

000- 0000

---- 0000 xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx

---- 0000

0000 00--

0000 0000

0000 0000

000- -0--

0--- -x00

0101 0101

---- 0000

1uuu 0100

---- 0000

0uu0 u-00

0000 0000

---- 0000

---- 0000

00-0 0000

000- 0000

---- 0000 xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx

---- 0000

0000 00--

0000 0000

0000 0000

000- -0--

0--- -x00

0101 0101

HT68FB540/HT68FB550/HT68FB560

I/O Flash USB MCU with SPI

Rev. 1.40

70 De�e��e� 01� �01� Rev. 1.40 71 De�e��e� 01� �01�

HT68FB540/HT68FB550/HT68FB560

I/O Flash USB MCU with SPI

Rev. 1.40

70 De�e��e� 01� �01�

HT68FB540/HT68FB550/HT68FB560

I/O Flash USB MCU with SPI

PDC

PE

PEC

WDTC

FRCR

FCR

FARL

INTC�

MFI0

MFI1

PA

PAC

PB

PBC

PD

FARH

FD0L

FD0H

FD1L

FD1H

FD�L

FD�H

FD3L

FD3H

MP0

MP1

ACC

PCL

TBLP

TBLH

TBHP

STATUS

BP

SMOD

INTEG

LVDC

INTC0

INTC1

Register

• The HT68FB550 register states are summarized below:

Reset

(Power On)

xxxx xxxx xxxx xxxx xxxx xxxx

WDT Timeout/WDTC

Software Reset

(Normal

Operation)

xxxx xxxx xxxx xxxx uuuu uuuu

RES

Reset/LVRC

Software Reset

(Normal

Operation)

xxxx xxxx xxxx xxxx uuuu uuuu

RES

Reset

(HALT)

xxxx xxxx xxxx xxxx uuuu uuuu

0000 0000 xxxx xxxx xxxx xxxx

---x xxxx

--00 xxxx

- - - - - - 0 0

0000 0011

0000 0000

--00 -000

-000 0000

00-0 00-0

0000 0000

0000 0000

0000 0000

1111 1111

1111 1111

-111 1111

-111 1111

1111 1111

1111 1111

---- -101

---- -111

0101 0011

- - - 0 - - - 0

0000 0000 xxxx xxxx

---x xxxx xxxx xxxx xxxx xxxx xxxx xxxx

0000 0000 uuuu uuuu uuuu uuuu

---u uuuu

--1u uuuu

---- ---00

0000 0011

0000 0000

--00 -000

-000 0000

00-0 00-0

0000 0000

0000 0000

0000 0000

1111 1111

1111 1111

-111 1111

-111 1111

1111 1111

1111 1111

---- -101

---- -111

0101 0011

- - - 0 - - - 0

0000 0000 xxxx xxxx

---x xxxx xxxx xxxx xxxx xxxx xxxx xxxx

0000 0000 uuuu uuuu uuuu uuuu

---u uuuu

--uu uuuu

- - - - - - 0 0

0000 0011

0000 0000

--00 -000

-000 0000

00-0 00-0

0000 0000

0000 0000

0000 0000

1111 1111

1111 1111

-111 1111

-111 1111

1111 1111

1111 1111

---- -101

---- -111

0101 0011

- - - 0 - - - 0

0000 0000 xxxx xxxx

---x xxxx xxxx xxxx xxxx xxxx xxxx xxxx

0000 0000 uuuu uuuu uuuu uuuu

---u uuuu

--01 uuuu

- - - - - - 0 0

0000 0011

0000 0000

--00 -000

-000 0000

00-0 00-0

0000 0000

0000 0000

0000 0000

1111 1111

1111 1111

-111 1111

-111 1111

1111 1111

1111 1111

---- -101

---- -111

0101 0011

- - - 0 - - - 0

0000 0000 xxxx xxxx

---x xxxx xxxx xxxx xxxx xxxx xxxx xxxx

WDT

Time-out

(HALT)*

uuuu uuuu uuuu uuuu uuuu uuuu

0000 0000 uuuu uuuu uuuu uuuu

---u uuuu

--11 uuuu

- - - - - - u u uuuu uuuu uuuu uuuu

--uu -uuu

-uuu uuuu uu-u uu-u uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu

-uuu uuuu

-uuu uuuu uuuu uuuu uuuu uuuu

---- -uuu

---- -uuu uuuu uuuu

- - - u - - - u uuuu uuuu uuuu uuuu xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx

---u uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu

USB-reset

(Normal)

USB-reset

(HALT)

0000 0000

0000 0000

0000 0000

1111 1111

1111 1111

-111 1111

-111 1111

1111 1111

1111 1111

---- -101

---- -111

0101 0011

- - - 0 - - - 0

0000 0000 xxxx xxxx

---x xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx uuuu uuuu

0000 0000 uuuu uuuu uuuu uuuu

---u uuuu

--uu uuuu

- - - - - - 0 0

0000 0011

0000 0000

--00 -000

-000 0000

00-0 00-0

0000 0000

0000 0000

0000 0000

1111 1111

1111 1111

-111 1111

-111 1111

1111 1111

1111 1111

---- -101

---- -111

0101 0011

- - - 0 - - - 0

0000 0000 xxxx xxxx

---x xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx uuuu uuuu

0000 0000 uuuu uuuu uuuu uuuu

---u uuuu

--uu uuuu

- - - - - - 0 0

0000 0011

0000 0000

--00 -000

-000 0000

00-0 00-0

Rev. 1.40 71 De�e��e� 01� �01�

HT68FB540/HT68FB550/HT68FB560

I/O Flash USB MCU with SPI

0000 0000

0000 0000

0000 0000

0000 0000

0000 0000

0000 0000

- - - - - - 0 0

0000 0000

- - - - - - 0 0

0000 0000

0000 0000

0000 0000

- - - - - - 0 0

0000 0000

- - - - - - 0 0

0000 0000

0000 0000

0000 0000

- - - - - - 0 0

111- --0-

--00 0000 xxxx xxxx

0000 ---0

0000 0000

0000 0000

0000 0000

-000 --00

-000 --00

--01 --01

--01 --01

0000 0---

0000 0000

0000 0000

0000 0000

TM1C1

TM1DL

TM1DH

TM1AL

TM1AH

TM�C0

TM�C1

TM0C0

TM0C1

TM0DL

TM0DH

TM0AL

TM0AH

TM0RP

TM1C0

TM�DL

TM�DH

TM�AL

TM�AH

TM3C0

TM3C1

TM3DL

TM3DH

SBSC

PAWU

PADIR

PAPU

PXPU

PXWU

TMPC0

TMPC1

I�CTOC

SIMC0

SIMC1

SIMD

SIMA/

SIMC�

SPIAC0

SPIAC1

SPIAD

Register

Reset

(Power On)

WDT Timeout/WDTC

Software Reset

(Normal

Operation)

0000 0000

1110 000-

1000 0001 xxxx xxxx

0000 0000

1110 000-

1000 0001 xxxx xxxx

RES

Reset/LVRC

Software Reset

(Normal

Operation)

0000 0000

1110 000-

1000 0001 xxxx xxxx

0000 0000 0000 0000 0000 0000

0000 0000

0000 0000

0000 0000

0000 0000

0000 0000

0000 0000

- - - - - - 0 0

0000 0000

- - - - - - 0 0

0000 0000

0000 0000

0000 0000

- - - - - - 0 0

0000 0000

- - - - - - 0 0

0000 0000

0000 0000

0000 0000

- - - - - - 0 0

111- --0-

--00 0000 xxxx xxxx

0000 ---0

0000 0000

0000 0000

0000 0000

-000 --00

-000 --00

--01 --01

--01 --01

0000 0---

0000 0000

0000 0000

0000 0000

0000 0000

0000 0000

0000 0000

0000 0000

0000 0000

0000 0000

- - - - - - 0 0

0000 0000

- - - - - - 0 0

0000 0000

0000 0000

0000 0000

- - - - - - 0 0

0000 0000

- - - - - - 0 0

0000 0000

0000 0000

0000 0000

- - - - - - 0 0

111- --0-

--00 0000 xxxx xxxx

0000 ---0

0000 0000

0000 0000

0000 0000

-000 --00

-000 --00

--01 --01

--01 --01

0000 0---

0000 0000

0000 0000

0000 0000

RES

Reset

(HALT)

0000 0000

1110 000-

1000 0001 xxxx xxxx

0000 0000

0000 0000

0000 0000

0000 0000

0000 0000

0000 0000

0000 0000

- - - - - - 0 0

0000 0000

- - - - - - 0 0

0000 0000

0000 0000

0000 0000

- - - - - - 0 0

0000 0000

- - - - - - 0 0

0000 0000

0000 0000

0000 0000

- - - - - - 0 0

111- --0-

--00 0000 xxxx xxxx

0000 ---0

0000 0000

0000 0000

0000 0000

-000 --00

-000 --00

--01 --01

--01 --01

0000 0---

0000 0000

0000 0000

0000 0000

WDT

Time-out

(HALT)*

uuuu uuuu uuuu uuuuuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu

- - - - - - u u uuuu uuuu

- - - - - - u u uuuu uuuu uuuu uuuu uuuu uuuu

- - - - - - u u uuuu uuuu

- - - - - - u u uuuu uuuu uuuu uuuu uuuu uuuu

- - - - - - u u uuu- --u-

--uu uuuu uuuu uuuu uuuu ---u uuuu uuuu uuuu uuuu uuuu uuuu

-uuu --uu

-uuu --uu

--uu --uu

--uu --uu uuuu u--uuuu uuuu uuuu uuuu uuuu uuuu

USB-reset

(Normal)

USB-reset

(HALT)

0000 0000

1110 000-

1000 0001 xxxx xxxx

0000 0000

0000 0000

0000 0000

0000 0000

0000 0000

0000 0000

0000 0000

- - - - - - 0 0

0000 0000

- - - - - - 0 0

0000 0000

0000 0000

0000 0000

- - - - - - 0 0

0000 0000

- - - - - - 0 0

0000 0000

0000 0000

0000 0000

- - - - - - 0 0

111- --0-

--00 0000 xxxx xxxx

0000 ---0

0000 0000

0000 0000

0000 0000

-000 --00

-000 --00

--01 --01

--01 --01

0000 0---

0000 0000

0000 0000

0000 0000

0000 0000

1110 000-

1000 0001 xxxx xxxx

0000 0000

0000 0000

0000 0000

0000 0000

0000 0000

0000 0000

0000 0000

- - - - - - 0 0

0000 0000

- - - - - - 0 0

0000 0000

0000 0000

0000 0000

- - - - - - 0 0

0000 0000

- - - - - - 0 0

0000 0000

0000 0000

0000 0000

- - - - - - 0 0

111- --0-

--00 0000 xxxx xxxx

0000 ---0

0000 0000

0000 0000

0000 0000

-000 --00

-000 --00

--01 --01

--01 --01

0000 0---

0000 0000

0000 0000

0000 0000

Rev. 1.40

7� De�e��e� 01� �01�

HT68FB540/HT68FB550/HT68FB560

I/O Flash USB MCU with SPI

Rev. 1.40 73 De�e��e� 01� �01�

HT68FB540/HT68FB550/HT68FB560

I/O Flash USB MCU with SPI

Rev. 1.40

7� De�e��e� 01� �01�

HT68FB540/HT68FB550/HT68FB560

I/O Flash USB MCU with SPI

Register

FIFO3

FIFO4

FIFO5

UFOEN

UFC0

UFC1

PDPS

PAPS0

PAPS1

SYSC

CTRL

LVRC

STLI

STLO

SIES

MISC

UFIEN

FIFO0

FIFO1

FIFO�

TM3AL

TM3AH

USB_

STAT

UINT

USC

USR

UCC

AWR

Reset

(Power On)

WDT Timeout/WDTC

Software Reset

(Normal

Operation)

0000 0000

- - - - - - 0 0

0000 0000

- - - - - - 0 0

RES

Reset/LVRC

Software Reset

(Normal

Operation)

0000 0000

- - - - - - 0 0

11xx 000xxxx xxxx xxxx xxxx xxxx xxxx

--00 0000

0000 00--

---- 0000

0000 0000

0000 0000

0000 0000

000- -0--

0--- -x00

0101 0101

--00 0000

1000 0000

--00 0000

0000 0000

0000 0000

--00 0000

--00 0000

00-0 0000

0000 0000

--00 0000 xxxx xxxx xxxx xxxx xxxx xxxx

11xx 000xxxx xxxx xxxx xxxx xxxx xxxx

--uu uuuu uuuu uu--

---- uuuu

0000 0000

0000 0000

0000 0000

000- -0--

0--- -x00

0101 0101

--uu uuuu uuuu xuux

--uu uuuu uuuu uuuu uuuu uuuu

--uu uuuu

--uu uuuu uu-x xuuu xxuu uuuu

--uu uuuu xxxx xxxx xxxx xxxx xxxx xxxx

Note: " * " stands for "warm reset"

" - " not implement

" u " stands for "unchanged"

" x " stands for "unknown"

11xx 000xxxx xxxx xxxx xxxx xxxx xxxx

--00 0000

0000 00--

---- 0000

0000 0000

0000 0000

0000 0000

000- -0--

0--- -x00

0101 0101

--00 0000

1000 0000

--00 0000

0000 0000

0000 0000

--00 0000

--00 0000

00-0 0000

0000 0000

--00 0000 xxxx xxxx xxxx xxxx xxxx xxxx

RES

Reset

(HALT)

0000 0000

- - - - - - 0 0

11xx 000xxxx xxxx xxxx xxxx xxxx xxxx

--00 0000

0000 00--

---- 0000

0000 0000

0000 0000

0000 0000

000- -0--

0--- -x00

0101 0101

--00 0000

1000 0000

--00 0000

0000 0000

0000 0000

--00 0000

--00 0000

00-0 0000

0000 0000

--00 0000 xxxx xxxx xxxx xxxx xxxx xxxx

WDT

Time-out

(HALT)*

uuuu uuuu

- - - - - - u u

11xx 000xxxx xxxx xxxx xxxx xxxx xxxx

--uu uuuu uuuu uu--

---- uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuu- -u-u--- -xuu uuuu uuuu

--uu uuuu uuuu xuux

--uu uuuu uuuu uuuu uuuu uuuu

--uu uuuu

--uu uuuu uu-x xuuu xxuu uuuu

--uu uuuu xxxx xxxx xxxx xxxx xxxx xxxx

USB-reset

(Normal)

USB-reset

(HALT)

0000 0000

- - - - - - 0 0

11xx 000xxxx xxxx xxxx xxxx xxxx xxxx

--00 0000

0000 00--

---- 0000

0000 0000

0000 0000

0000 0000

000- -0--

0--- -x00

0101 0101

--00 0000

1uuu 0100

--00 0000

0uu0 u000

0000 0000

--00 0000

--00 0000

00-0 0000

0000 0000

--00 0000 xxxx xxxx xxxx xxxx xxxx xxxx

0000 0000

- - - - - - 0 0

11xx 000xxxx xxxx xxxx xxxx xxxx xxxx

--00 0000

0000 00--

---- 0000

0000 0000

0000 0000

0000 0000

000- -0--

0--- -x00

0101 0101

--00 0000

1uuu 0100

--00 0000

0uu0 u000

0000 0000

--00 0000

--00 0000

00-0 0000

0000 0000

--00 0000 xxxx xxxx xxxx xxxx xxxx xxxx

Rev. 1.40 73 De�e��e� 01� �01�

HT68FB540/HT68FB550/HT68FB560

I/O Flash USB MCU with SPI

PCC

PD

PDC

PE

PEC

WDTC

FRCR

INTC�

MFI0

MFI1

PA

PAC

PB

PBC

PC

FCR

FARL

FARH

FD0L

FD0H

FD1L

FD1H

FD�L

FD�H

MP0

MP1

ACC

PCL

TBLP

TBLH

TBHP

STATUS

BP

SMOD

INTEG

LVDC

INTC0

INTC1

Register

• The HT68FB560 register states are summarized below:

Reset

(Power On)

WDT Timeout/WDTC

Software Reset

(Normal

Operation)

RES

Reset/LVRC

Software Reset

(Normal

Operation)

0000 0000

0000 0000

0000 0000

1111 1111

1111 1111

1111 1111

1111 1111

1111 1111

1111 1111

1111 1111

1111 1111

--11 1101

--11 1111

0101 0011

- - - 0 - - - 0

0000 0000 xxxx xxxx

--xx xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx

0000 0000 xxxx xxxx xxxx xxxx

--xx xxxx

--00 xxxx

--0- -000

0000 0011

0000 0000

--00 -000

-000 0000

00-0 00-0

0000 0000

0000 0000

0000 0000

1111 1111

1111 1111

1111 1111

1111 1111

1111 1111

1111 1111

1111 1111

1111 1111

--11 1101

--11 1111

0101 0011

- - - 0 - - - 0

0000 0000 xxxx xxxx

--xx xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx uuuu uuuu

0000 0000 uuuu uuuu uuuu uuuu

--uu uuuu

--1u uuuu

--0- --000

0000 0011

0000 0000

--00 -000

-000 0000

00-0 00-0

0000 0000

0000 0000

0000 0000

1111 1111

1111 1111

1111 1111

1111 1111

1111 1111

1111 1111

1111 1111

1111 1111

--11 1101

--11 1111

0101 0011

- - - 0 - - - 0

0000 0000 xxxx xxxx

--xx xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx uuuu uuuu

0000 0000 uuuu uuuu uuuu uuuu

--uu uuuu

--uu uuuu

--0- -000

0000 0011

0000 0000

--00 -000

-000 0000

00-0 00-0

RES

Reset

(HALT)

0000 0000

0000 0000

0000 0000

1111 1111

1111 1111

1111 1111

1111 1111

1111 1111

1111 1111

1111 1111

1111 1111

--11 1101

--11 1111

0101 0011

- - - 0 - - - 0

0000 0000 xxxx xxxx

--xx xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx uuuu uuuu

0000 0000 uuuu uuuu uuuu uuuu

--uu uuuu

--01 uuuu

--0- -000

0000 0011

0000 0000

--00 -000

-000 0000

00-0 00-0

WDT

Time-out

(HALT)*

uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu

--uu uuuu

--uu uuuu uuuu uuuu

- - - u - - - u uuuu uuuu uuuu uuuu

--uu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu

0000 0000 uuuu uuuu uuuu uuuu

--uu uuuu

--11 uuuu

--u- -uuu uuuu uuuu uuuu uuuu

--uu -uuu

-uuu uuuu uu-u uu-u

USB-reset

(Normal)

USB-reset

(HALT)

0000 0000

0000 0000

0000 0000

1111 1111

1111 1111

1111 1111

1111 1111

1111 1111

1111 1111

1111 1111

1111 1111

--11 1101

--11 1111

0101 0011

- - - 0 - - - 0

0000 0000 xxxx xxxx

--xx xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx uuuu uuuu

0000 0000 uuuu uuuu uuuu uuuu

--uu uuuu

--uu uuuu

--0- -000

0000 0011

0000 0000

--00 -000

-000 0000

00-0 00-0

0000 0000

0000 0000

0000 0000

1111 1111

1111 1111

1111 1111

1111 1111

1111 1111

1111 1111

1111 1111

1111 1111

--11 1101

--11 1111

0101 0011

- - - 0 - - - 0

0000 0000 xxxx xxxx

--xx xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx uuuu uuuu

0000 0000 uuuu uuuu uuuu uuuu

--uu uuuu

--uu uuuu

--0- -000

0000 0011

0000 0000

--00 -000

-000 0000

00-0 00-0

Rev. 1.40

74 De�e��e� 01� �01�

HT68FB540/HT68FB550/HT68FB560

I/O Flash USB MCU with SPI

Rev. 1.40 75 De�e��e� 01� �01�

HT68FB540/HT68FB550/HT68FB560

I/O Flash USB MCU with SPI

Rev. 1.40

74 De�e��e� 01� �01�

HT68FB540/HT68FB550/HT68FB560

I/O Flash USB MCU with SPI

0000 0000

0000 0000

0000 0000

0000 0000

0000 0000

0000 0000

0000 0000

0000 0000

0000 0000

- - - - - - 0 0

0000 0000

- - - - - - 0 0

0000 0000

0000 0000

0000 0000

- - - - - - 0 0

0000 0000

- - - - - - 0 0

0000 0000

111- --0-

--00 0000 xxxx xxxx

0000 ---0

0000 0000

0000 0000

0000 0000

0000 0000

0000 0000

--01 --01

--01 --01

0000 0---

0000 0000

TM0RP

TM1C0

TM1C1

TM1DL

TM1DH

TM1AL

TM1AH

TMPC0

TMPC1

TM0C0

TM0C1

TM0DL

TM0DH

TM0AL

TM0AH

TM�C0

TM�C1

TM�DL

TM�DH

TM�AL

TM�AH

TM3C0

SPIAC1

SPIAD

SBSC

PAWU

PADIR

PAPU

PXPU

PXWU

FD3L

FD3H

I�CTOC

SIMC0

SIMC1

SIMD

SIMA/

SIMC�

SPIAC0

Register

Reset

(Power On)

WDT Timeout/WDTC

Software Reset

(Normal

Operation)

RES

Reset/LVRC

Software Reset

(Normal

Operation)

xxxx xxxx xxxx xxxx

0000 0000

1110 000-

1000 0001 xxxx xxxx xxxx xxxx xxxx xxxx

0000 0000

1110 000-

1000 0001 xxxx xxxx xxxx xxxx xxxx xxxx

0000 0000

1110 000-

1000 0001 xxxx xxxx

0000 0000

0000 0000

0000 0000

0000 0000

0000 0000

0000 0000

0000 0000

0000 0000

0000 0000

- - - - - - 0 0

0000 0000

- - - - - - 0 0

0000 0000

0000 0000

0000 0000

- - - - - - 0 0

0000 0000

- - - - - - 0 0

0000 0000

111- --0-

--00 0000 xxxx xxxx

0000 ---0

0000 0000

0000 0000

0000 0000

0000 0000

0000 0000

--01 --01

--01 --01

0000 0---

0000 0000

0000 0000

0000 0000

0000 0000

0000 0000

0000 0000

0000 0000

0000 0000

0000 0000

0000 0000

- - - - - - 0 0

0000 0000

- - - - - - 0 0

0000 0000

0000 0000

0000 0000

- - - - - - 0 0

0000 0000

- - - - - - 0 0

0000 0000

111- --0-

--00 0000 xxxx xxxx

0000 ---0

0000 0000

0000 0000

0000 0000

0000 0000

0000 0000

--01 --01

--01 --01

0000 0---

0000 0000

RES

Reset

(HALT)

xxxx xxxx xxxx xxxx

0000 0000

1110 000-

1000 0001 xxxx xxxx

0000 0000

0000 0000

0000 0000

0000 0000

0000 0000

0000 0000

0000 0000

0000 0000

0000 0000

- - - - - - 0 0

0000 0000

- - - - - - 0 0

0000 0000

0000 0000

0000 0000

- - - - - - 0 0

0000 0000

- - - - - - 0 0

0000 0000

111- --0-

--00 0000 xxxx xxxx

0000 ---0

0000 0000

0000 0000

0000 0000

0000 0000

0000 0000

--01 --01

--01 --01

0000 0---

0000 0000

WDT

Time-out

(HALT)*

USB-reset

(Normal)

xxxx xxxx xxxx xxxx

0000 0000

1110 000-

1000 0001 xxxx xxxx

0000 0000

0000 0000

0000 0000

0000 0000

0000 0000

0000 0000

0000 0000

0000 0000

0000 0000

- - - - - - 0 0

0000 0000

- - - - - - 0 0

0000 0000

0000 0000

0000 0000

- - - - - - 0 0

0000 0000

- - - - - - 0 0

0000 0000

111- --0-

--00 0000 xxxx xxxx

0000 ---0

0000 0000

0000 0000

0000 0000

0000 0000

0000 0000

--01 --01

--01 --01

0000 0---

0000 0000 uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuuuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu

- - - - - - u u uuuu uuuu

- - - - - - u u uuuu uuuu uuuu uuuu uuuu uuuu

- - - - - - u u uuuu uuuu

- - - - - - u u uuuu uuuu uuu- --u-

--uu uuuu uuuu uuuu uuuu ---u uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu

--uu --uu

--uu --uu uuuu u--uuuu uuuu

USB-reset

(HALT)

xxxx xxxx xxxx xxxx

0000 0000

1110 000-

1000 0001 xxxx xxxx

0000 0000

0000 0000

0000 0000

0000 0000

0000 0000

0000 0000

0000 0000

0000 0000

0000 0000

- - - - - - 0 0

0000 0000

- - - - - - 0 0

0000 0000

0000 0000

0000 0000

- - - - - - 0 0

0000 0000

- - - - - - 0 0

0000 0000

111- --0-

--00 0000 xxxx xxxx

0000 ---0

0000 0000

0000 0000

0000 0000

0000 0000

0000 0000

--01 --01

--01 --01

0000 0---

0000 0000

Rev. 1.40 75 De�e��e� 01� �01�

HT68FB540/HT68FB550/HT68FB560

I/O Flash USB MCU with SPI

Register

Reset

(Power On)

WDT Timeout/WDTC

Software Reset

(Normal

Operation)

RES

Reset/LVRC

Software Reset

(Normal

Operation)

UFOEN

UFC0

UFC1

PDPS

PAPS0

PAPS1

SYSC

CTRL

LVRC

FIFO0

FIFO1

FIFO�

FIFO3

FIFO4

FIFO5

FIFO�

FIFO7

USR

UCC

AWR

STLI

STLO

SIES

MISC

UFIEN

TM3C1

TM3DL

TM3DH

TM3AL

TM3AH

USB_

STAT

UINT

USC

0000 0000

0000 0000

- - - - - - 0 0

0000 0000

- - - - - - 0 0

11xx 000xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx

0000 0000

0000 00--

0000 0000

0000 0000

0000 0000

0000 0000

000- -0--

0--- -x00

0101 0101

0000 0000

1000 0000

0000 0000

0000 0000

0000 0000

0000 0000

0000 0000

00-0 0000

0000 0000

0000 0000 xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx

0000 0000

0000 0000

- - - - - - 0 0

0000 0000

- - - - - - 0 0

11xx 000xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx

00uu uuuu uuuu uu-uuuu uuuu

0000 0000

0000 0000

0000 0000

000- -0--

0--- -x00

0101 0101 uuuu uuuu uuuu xuux uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uu-x xuuu xxuu uuuu

00uu uuuu xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx

Note: " * " stands for "warm reset"

" - " not implement

" u " stands for "unchanged"

" x " stands for "unknown"

0000 0000

0000 0000

- - - - - - 0 0

0000 0000

- - - - - - 0 0

11xx 000xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx

-0000 0000

0000 00--

0000 0000

0000 0000

0000 0000

0000 0000

000- -0--

0--- -x00

0101 0101

0000 0000

1000 0000

0000 0000

0000 0000

0000 0000

0000 0000

0000 0000

00-0 0000

0000 0000

0000 0000 xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx

RES

Reset

(HALT)

0000 0000

0000 0000

- - - - - - 0 0

0000 0000

- - - - - - 0 0

11xx 000xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx

0000 0000

0000 00--

0000 0000

0000 0000

0000 0000

0000 0000

000- -0--

0--- -x00

0101 0101

0000 0000

1000 0000

0000 0000

0000 0000

0000 0000

0000 0000

0000 0000

00-0 0000

0000 0000

0000 0000 xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx

WDT

Time-out

(HALT)*

uuuu uuuu uuuu uuuu

- - - - - - u u uuuu uuuu

- - - - - - u u

11xx 000xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx uuuu uuuu uuuu uu-uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuu- -u-u--- -xuu uuuu uuuu uuuu uuuu uuuu xuux uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uu-x xuuu xxuu uuuu uuuu uuuu xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx

USB-reset

(Normal)

USB-reset

(HALT)

0000 0000

0000 0000

- - - - - - 0 0

0000 0000

- - - - - - 0 0

11xx 000-

0000 0000

0000 0000

- - - - - - 0 0

0000 0000

- - - - - - 0 0

11xx 000xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx

0000 0000

0000 00--

0000 0000

0000 0000

0000 0000

0000 0000

000- -0--

0--- -x00

0101 0101

0000 0000 0000 0000

1uuu 0100 1uuu 0100

0000 0000 0000 0000

0uu0 u000 0uu0 u000

0000 0000 0000 0000

0000 0000 0000 0000

0000 0000 0000 0000

00-0 0000 00-0 0000

0000 0000

0000 0000

0000 0000

0000 0000 xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx

0000 0000

0000 00--

0000 0000

0000 0000

0000 0000

0000 0000

000- -0--

0--- -x00

0101 0101

Rev. 1.40

7� De�e��e� 01� �01�

HT68FB540/HT68FB550/HT68FB560

I/O Flash USB MCU with SPI

Rev. 1.40 77 De�e��e� 01� �01�

HT68FB540/HT68FB550/HT68FB560

I/O Flash USB MCU with SPI

HT68FB540/HT68FB550/HT68FB560

I/O Flash USB MCU with SPI

Input/Output Ports

Holtek microcontrollers offer considerable flexibility on their I/O ports. With the input or output designation of every pin fully under user program control, pull-high selections for all ports and wake-up selections on certain pins, the user is provided with an I/O structure to meet the needs of a wide range of application possibilities.

The devices provide bidirectional input/output lines labeled with port names PA~PE.

These I/O ports are mapped to the RAM Data Memory with specific addresses as shown in the Special Purpose

Data Memory table. All of these I/O ports can be used for input and output operations. For input operation, these ports are non-latching, which means the inputs must be ready at the T2 rising edge of instruction "MOV A, [m]", where m denotes the port address. For output operation, all the data is latched and remains unchanged until the output latch is rewritten.

I/O Register List

• HT68FB540

Register

Name

PAWU

PAPU

PA

PAC

PADIR

PXWU

PXPU

PAPS0

PAPS1

PB

PBC

PE

PEC

PA3S1

PA7S1

D7

D7

7

D7

D7

D7

6

D�

D�

D�

D�

D�

PELWU

PELPU

PA3S0

PA7S0

D�

D�

PA�S1

PA�S1

D5

D5

D5

D5

5

D5

D5

D5

PA�S0

PA�S0

D4

D4

D4

D4

4

D4

D4

D4

Bit

PA1S1

PA5S1

D3

D3

D3

D3

3

D3

D3

D3

PA1S0

PA5S0

D�

D�

D�

D�

D�

D�

2

D�

D�

D�

1

D1

D1

D1

D1

D1

PBHWU

PBHPU

PA0S1

PA4S1

D1

D1

D1

D1

0

D0

D0

D0

D0

D0

PBLWU

PBLPU

PA0S0

PA4S0

D0

D0

D0

D0

Rev. 1.40

7� De�e��e� 01� �01� Rev. 1.40 77 De�e��e� 01� �01�

Rev. 1.40

HT68FB540/HT68FB550/HT68FB560

I/O Flash USB MCU with SPI

PAPS0

PAPS1

PB

PBC

PD

PDC

PE

PEC

PAWU

PAPU

PA

PAC

PADIR

PXWU

PXPU

• HT68FB550

Register

Name

PA3S1

PA7S1

D7

D7

D7

7

D7

D7

D7

D7

• HT68FB560

Register

Name

PAWU

PAPU

PA

PAC

PADIR

PXWU

PXPU

PAPS0

PAPS1

PB

PBC

PC

PCC

PD

PDC

PE

PEC

7

D7

D7

D7

D7

D7

PEHWU

PEHPU

PA3S1

PA7S1

D7

D7

D7

D7

D7

D7

6

D�

D�

D�

D�

D�

PELWU

PELPU

PA3S0

PA7S0

D�

D�

D�

D�

6

D�

D�

D�

D�

D�

PELWU

PELPU

PA3S0

PA7S0

D�

D�

D�

D�

D�

D�

5

D5

D5

D5

D5

D5

PDHWU

PDHPU

PA�S1

PA�S1

D5

D5

D5

D5

D5

D5

D5

D5

PA�S1

D5

D5

D5

D5

5

D5

D5

D5

D5

D5

PDHWU

PDHPU

PA�S1

PA�S0

D4

D4

D4

D4

4

D4

D4

D4

D4

D4

PDLWU

PDLPU

PA�S0

Bit

D3

PA1S1

3

D3

D3

D3

D3

PA5S1

D3

D3

D3

D3

2

D�

D�

D�

D�

D�

PA1S0

PA5S0

D�

D�

D�

D�

D�

D�

1

D1

D1

D1

D1

D1

PBHWU

PBHPU

PA0S1

PA4S1

D1

D1

D1

D1

D1

D1

PA�S0

D4

D4

D4

D4

D4

D4

D4

D4

4

D4

D4

D4

D4

D4

PDLWU

PDLPU

PA�S0

Bit

3

D3

D3

D3

D3

D3

PCHWU

PCHPU

PA1S1

PA5S1

D3

D3

D3

D3

D3

D3

D3

D3

2

D�

D�

D�

D�

D�

PCLWU

PCLPU

PA1S0

PA5S0

D�

D�

D�

D�

D�

D�

D�

D�

1

D1

D1

D1

D1

D1

PBHWU

PBHPU

PA0S1

PA4S1

D1

D1

D1

D1

D1

D1

D1

D1

0

D0

D0

D0

D0

D0

PBLWU

PBLPU

PA0S0

PA4S0

D0

D0

D0

D0

D0

D0

D0

D0

PA4S0

D0

D0

D0

D0

D0

D0

0

D0

D0

D0

D0

D0

PBLWU

PBLPU

PA0S0

78 De�e��e� 01� �01�

HT68FB540/HT68FB550/HT68FB560

I/O Flash USB MCU with SPI

Rev. 1.40 79 De�e��e� 01� �01�

HT68FB540/HT68FB550/HT68FB560

I/O Flash USB MCU with SPI

Rev. 1.40

78 De�e��e� 01� �01�

HT68FB540/HT68FB550/HT68FB560

I/O Flash USB MCU with SPI

Pull-high Resistors

Many product applications require pull-high resistors for their switch inputs usually requiring the use of an external resistor. To eliminate the need for these external resistors, all I/O pins, when configured as an input have the capability of being connected to an internal pull-high resistor. These pull-high resistors are selected using registers, namely PAPU and PXPU, and are implemented using weak PMOS transistors. Note that the PA pull-high resistors are controlled by bits in the PAPU register, other than the PB, PC, PD, PE pull-high resistors are controlled by nibble in the PXPU register.

PAPU Register

Bit

Na�e

R/W

POR

Bit 7~0

7

D7

R/W

0

6

D�

R/W

0

5

D5

R/W

0

4

D4

R/W

0

PAPU

: I/O PA bit 7~bit 0 Pull-High Control

0: disable

1: enable

3

D3

R/W

0

PXPU Register

• HT68FB540

Bit

Na�e

R/W

POR

R

0

7

6

PELPU

R/W

0

R

0

5

R

0

4

Bit 7

Bit 6

"—": unimplemented, read as "0"

PELPU

: PE2, PE0 pins Pull-High control

0: disable

1: enable

Note that the PE1 pin has no pull-up resistor.

Bit 5~2 "—": unimplemented, read as "0"

Bit 1

Bit 0

PBHPU

: PB6~PB4 pins Pull-High control

0: disable

1: enable

PBLPU

: PB3~PB0 pins Pull-High control

0: disable

1: enable

• HT68FB550

Bit

Na�e

R/W

POR

7

R

0

6

PELPU

R/W

0

5

PDHPU

R/W

0

4

PDLPU

R/W

0

Bit 7

Bit 6

"—": unimplemented, read as "0"

PELPU

: PE2, PE0 pins Pull-High control

0: disable

1: enable

Note that the PE1 pin has no pull-up resistor.

3

R

0

R

0

3

2

R

0

R

0

2

2

D�

R/W

0

1

D1

R/W

0

1

PBHPU

R/W

0

1

PBHPU

R/W

0

0

D0

R/W

0

0

PBLPU

R/W

0

0

PBLPU

R/W

0

Rev. 1.40 79 De�e��e� 01� �01�

Rev. 1.40

HT68FB540/HT68FB550/HT68FB560

I/O Flash USB MCU with SPI

Bit 5

Bit 4

PDHPU

: PD7~PD4 pins Pull-High control

0: disable

1: enable

PDLPU

: PD3~PD0 pins Pull-High control

0: disable

1: enable

Bit 3~2 "—": unimplemented, read as "0"

Bit 1

PBHPU

: PB6~PB4 pins Pull-High control

0: disable

1: enable

Bit 0

PBLPU

: PB3~PB0 pins Pull-High control

0: disable

1: enable

• HT68FB560

Bit

Na�e

7

PEHPU

R/W

POR

R/W

0

6

PELPU

R/W

0

5

PDHPU

R/W

0

4

PDLPU

R/W

0

3

PCHPU

R/W

0

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

PEHPU

: PE5~PE4 pins Pull-High control

0: disable

1: enable

PELPU

: PE3~PE2, PE0 pins Pull-High control

0: disable

1: enable

Note that the PE1 pin has no pull-up resistor.

PDHPU

: PD7~PD4 pins Pull-High control

0: disable

1: enable

PDLPU

: PD3~PD0 pins Pull-High control

0: disable

1: enable

PCHPU

: PC7~PC4 pins Pull-High control

0: disable

1: enable

PCLPU

: PC3~PC0 pins Pull-High control

0: disable

1: enable

PBHPU

: PB7~PB4 pins Pull-High control

0: disable

1: enable

PBLPU

: PB3~PB0 pins Pull-High control

0: disable

1: enable

2

PCLPU

R/W

0

1

PBHPU

R/W

0

0

PBLPU

R/W

0

80 De�e��e� 01� �01�

HT68FB540/HT68FB550/HT68FB560

I/O Flash USB MCU with SPI

Rev. 1.40 81 De�e��e� 01� �01�

HT68FB540/HT68FB550/HT68FB560

I/O Flash USB MCU with SPI

Rev. 1.40

80 De�e��e� 01� �01�

HT68FB540/HT68FB550/HT68FB560

I/O Flash USB MCU with SPI

Port Wake-up

The HALT instruction forces the microcontroller into the SLEEP or IDLE Mode which preserves power, a feature that is important for battery and other low-power applications. Various methods exist to wake-up the microcontroller, one of which is to change the logic condition on one of the

Port A~Port E pins from high to low. This function is especially suitable for applications that can be woken up via external switches. Each pin on Port A~Port E can be selected by bits or nibble to have this wake-up feature using the PAWU and PXWU registers.

PAWU Register

Bit

Na�e

R/W

POR

7

D7

R/W

0

Bit 7~0

6

D�

R/W

0

5

D5

R/W

0

4

D4

R/W

0

PAWU

: Port A bit 7~bit 0 Wake-up Control

0: disable

1: enable

3

D3

R/W

0

PXWU Register

• HT68FB540

Bit

Na�e

R/W

POR

R

0

7

6

PELWU

R/W

0

R

0

5

R

0

4

Bit 7

Bit 6

Bit 5~2

Bit 1

Bit 0

• HT68FB550

Bit

Na�e

R/W

POR

7

R

0

"—": unimplemented, read as "0"

PELWU

: PE2, PE0 pins Wake-up control

0: disable

1: enable

Note that the PE1 pin has no wake-up function.

"—": unimplemented, read as "0"

PBHWU

: PB6~PB4 pins Wake-up control

0: disable

1: enable

PBLWU

: PB3~PB0 pins Wake-up control

0: disable

1: enable

6

PELWU

R/W

0

5

PDHWU

R/W

0

4

PDLWU

R/W

0

3

R

0

Bit 7

Bit 6

"—": unimplemented, read as "0"

PELWU

: PE2, PE0 pins Wake-up control

0: disable

1: enable

Note that the PE1 pin has no wake-up function.

R

0

3

2

R

0

2

D�

R/W

0

R

0

2

1

D1

R/W

0

1

PBHWU

R/W

0

1

PBHWU

R/W

0

0

D0

R/W

0

0

PBLWU

R/W

0

0

PBLWU

R/W

0

Rev. 1.40 81 De�e��e� 01� �01�

HT68FB540/HT68FB550/HT68FB560

I/O Flash USB MCU with SPI

Bit 5

Bit 4

Bit 3~2

Bit 1

Bit 0

PDHWU

: PD7~PD4 pins Wake-up control

0: disable

1: enable

PDLWU

: PD3~PD0 pins Wake-up control

0: disable

1: enable

"—": unimplemented, read as "0"

PBHWU

: PB6~PB4 pins Wake-up control

0: disable

1: enable

PBLWU

: PB3~PB0 pins Wake-up control

0: disable

1: enable

• HT68FB560

Bit

Na�e

7

PEHWU

R/W

POR

R/W

0

6

PELWU

R/W

0

5

PDHWU

R/W

0

4

PDLWU

R/W

0

3

PCHWU

R/W

0

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

PEHWU

: PE5~PE4 pins Wake-up control

0: disable

1: enable

PELWU

: PE3~PE2, PE0 pins Wake-up control

0: disable

1: enable

Note that the PE1 pin has no wake-up function.

PDHWU

: PD7~PD4 pins Wake-up control

0: disable

1: enable

PDLWU

: PD3~PD0 pins Wake-up control

0: disable

1: enable

PCHWU

: PC7~PC4 pins Wake-up control

0: disable

1: enable

PCLWU

: PC3~PC0 pins Wake-up control

0: disable

1: enable

PBHWU

: PB7~PB4 pins Wake-up control

0: disable

1: enable

PBLWU

: PB3~PB0 pins Wake-up control

0: disable

1: enable

2

PCLWU

R/W

0

1

PBHWU

R/W

0

0

PBLWU

R/W

0

Port A Wake-up Polarity Control Register

The I/O port, PA, can be setup to have a choice of wake-up polarity using specific register.

Ea�h pin on Po�t A �an �e sele�ted individually to have this Wake-up pola�ity featu�e using the PADIR �egiste�.

Rev. 1.40

8� De�e��e� 01� �01�

HT68FB540/HT68FB550/HT68FB560

I/O Flash USB MCU with SPI

Rev. 1.40 83 De�e��e� 01� �01�

HT68FB540/HT68FB550/HT68FB560

I/O Flash USB MCU with SPI

Rev. 1.40

8� De�e��e� 01� �01�

HT68FB540/HT68FB550/HT68FB560

I/O Flash USB MCU with SPI

PADIR Register

Bit

Na�e

R/W

POR

7

D7

R/W

0

Bit 7~0

6

D�

R/W

0

5

D5

R/W

0

4

D4

R/W

0

PADIR

: PA7~PA0 pins Wake-up edge control

0: rising edge

1: falling edge

3

D3

R/W

0

2

D�

R/W

0

1

D1

R/W

0

0

D0

R/W

0

I/O Port Control Registers

Each I/O port has its own control register known as PAC~PEC, to control the input/output configuration. With this control register, each CMOS output or input can be reconfigured dynamically under software control. Each pin of the I/O ports is directly mapped to a bit in its associated port control register. For the I/O pin to function as an input, the corresponding bit of the control register must be written as a "1". This will then allow the logic state of the input pin to be directly read by instructions. When the corresponding bit of the control register is written as a "0", the I/O pin will be setup as a CMOS output. If the pin is currently setup as an output, instructions can still be used to read the output register. However, it should be noted that the program will in fact only read the status of the output data latch and not the actual logic status of the output pin.

PAC Register

Bit

Na�e

R/W

POR

7

D7

R/W

1

6

D�

R/W

1

5

D5

R/W

1

4

D4

R/W

1

3

D3

R/W

1

2

D�

R/W

1

1

D1

R/W

1

0

D0

R/W

1

PBC Register

• HT68FB540/HT68FB550

Bit 7 6

Na�e

R/W

POR

D�

R/W

1

• HT68FB560

Bit

Na�e

R/W

POR

7

D7

R/W

1

6

D�

R/W

1

PCC Register

• HT68FB560

Bit

Na�e

R/W

POR

7

D7

R/W

1

6

D�

R/W

1

5

D5

R/W

1

5

D5

R/W

1

5

D5

R/W

1

4

D4

R/W

1

4

D4

R/W

1

4

D4

R/W

1

3

D3

R/W

1

3

D3

R/W

1

3

D3

R/W

1

2

D�

R/W

1

2

D�

R/W

1

2

D�

R/W

1

1

D1

R/W

1

1

D1

R/W

1

1

D1

R/W

1

0

D0

R/W

1

0

D0

R/W

1

0

D0

R/W

1

Rev. 1.40 83 De�e��e� 01� �01�

HT68FB540/HT68FB550/HT68FB560

I/O Flash USB MCU with SPI

PDC Register

• HT68FB550/HT68FB560

Bit

Na�e

R/W

POR

7

D7

R/W

1

6

D�

R/W

1

PEC Register

• HT68FB540/HT68FB550

Bit

Na�e

7

6

R/W

POR

5

D5

R/W

1

5

4

D4

R/W

1

4

3

D3

R/W

1

3

2

D�

R/W

1

2

D�

R/W

1

1

D1

R/W

1

1

D1

R/W

1

0

D0

R/W

1

0

D0

R/W

1

• HT68FB560

Bit

Na�e

R/W

POR

Bit 7~6

Bit 5~0

7

6

5

D5

R/W

1

4

D4

R/W

1

"—": unimplemented, read as "0"

PEC

: I/O Port bit 5~bit 0 Input/Output Control

0: Output

1: Input

3

D3

R/W

1

2

D�

R/W

1

1

D1

R/W

1

0

D0

R/W

1

Port A , Port D Power Source Control Registers

Port A and Port D can be setup to have a choice of various power source using specific registers.

Each pin on Port A and Port D [7:4] can be selected individually to have various power sources using the PAPS0, PAPS1 and PDPS registers.

PAPS0 Register

Bit

Na�e

R/W

POR

Bit 7~6

Bit 5~4

Bit 3~2

Bit 1~0

7

PA3S1

R/W

0

6

PA3S0

R/W

0

5

PA�S1

R/W

0

4

PA�S0

R/W

0

PA3S1, PA3S0

: PA3 power supply control

00: VDD

01: VDD

10: VDDIO

11: V33O, 3.3V regulator output

PA2S1, PA2S0

: PA2 power supply control

00: VDD

01: VDD

10: VDDIO

11: V33O, 3.3V regulator output

PA1S1, PA1S0

: PA1 power supply control

00: VDD

01: VDD

10: VDDIO

11: V33O, 3.3V regulator output

PA0S1, PA0S0

: PA0 power supply control

00: VDD

01: VDD

10: VDDIO

11: V33O, 3.3V regulator output

3

PA1S1

R/W

0

2

PA1S0

R/W

0

1

PA0S1

R/W

0

0

PA0S0

R/W

0

Rev. 1.40

84 De�e��e� 01� �01�

HT68FB540/HT68FB550/HT68FB560

I/O Flash USB MCU with SPI

Rev. 1.40 85 De�e��e� 01� �01�

HT68FB540/HT68FB550/HT68FB560

I/O Flash USB MCU with SPI

Rev. 1.40

84 De�e��e� 01� �01�

HT68FB540/HT68FB550/HT68FB560

I/O Flash USB MCU with SPI

PAPS1 Register

Bit

Na�e

R/W

POR

Bit 7~6

Bit 5~4

Bit 3~2

Bit 1~0

7

PA7S1

R/W

0

6

PA7S0

R/W

0

5

PA�S1

R/W

0

4

PA�S0

R/W

0

PA7S1, PA7S0

: PA7 power supply control

00: VDD

01: VDD

10: VDDIO

11: V33O, 3.3V regulator output

PA6S1, PA6S0

: PA6 power supply control

00: VDD

01: VDD

10: VDDIO

11: V33O, 3.3V regulator output

PA5S1, PA5S0

: PA5 power supply control

00: VDD

01: VDD

10: VDDIO

11: V33O, 3.3V regulator output

PA4S1, PA4S0

: PA4 power supply control

00: VDD

01: VDD

10: VDDIO

11: V33O, 3.3V regulator output

3

PA5S1

R/W

0

PDPS Register

• HT68FB550/HT68FB560

Bit

Na�e

7

PD7S1

6

PD7S0

R/W

POR

R/W

0

R/W

0

Bit 7~6

Bit 5~4

Bit 3~2

Bit 1~0

5

PD�S1

R/W

0

4

PD�S0

R/W

0

PD7S1, PD7S0

: PD7 power supply control

00: VDD

01: VDD

10: VDDIO

11: V33O, 3.3V regulator output

PD6S1, PD6S0

: PD6 power supply control

00: VDD

01: VDD

10: VDDIO

11: V33O, 3.3V regulator output

PD5S1, PD5S0

: PD5 power supply control

00: VDD

01: VDD

10: VDDIO

11: V33O, 3.3V regulator output

PD4S1, PD4S0

: PD4 power supply control

00: VDD

01: VDD

10: VDDIO

11: V33O, 3.3V regulator output

3

PD5S1

R/W

0

Rev. 1.40 85

2

PA5S0

R/W

0

1

PA4S1

R/W

0

0

PA4S0

R/W

0

2

PD5S0

R/W

0

1

PD4S1

R/W

0

0

PD4S0

R/W

0

De�e��e� 01� �01�

HT68FB540/HT68FB550/HT68FB560

I/O Flash USB MCU with SPI

I/O Pin Structures

The accompanying diagrams illustrate the internal structures of some generic I/O pin types. As the exact logical construction of the I/O pin will differ from these drawings, they are supplied as a guide only to assist with the functional understanding of the I/O pins. The wide range of pin-shared structures does not permit all types to be shown.

Programming Considerations

Within the user program, one of the first things to consider is port initialisation. After a reset, all of the I/O data and port control registers will be set high. This means that all I/O pins will default to an input state, the level of which depends on the other connected circuitry and whether pull-high selections have been chosen. If the port control registers, PAC~PEC, are then programmed to setup some pins as outputs, these output pins will have an initial high output value unless the associated port data registers, PA~PE, are first programmed. Selecting which pins are inputs and which are outputs can be achieved byte-wide by loading the correct values into the appropriate port control register or by programming individual bits in the port control register using the "SET [m].i" and

"CLR [m].i" instructions. Note that when using these bit control instructions, a read-modify-write operation takes place. The microcontroller must first read in the data on the entire port, modify it to the required new bit values and then rewrite this data back to the output ports.

All Ports provide the wake-up function which can be set by individual pin in the Port A while it has to be set by nibble pins in the Port B, Port C, Port D and Port E. When the device is in the SLEEP or IDLE Mode, various methods are available to wake the device up. One of these is a voltage level transition on any of the Port pins. Single or multiple pins on Ports can be setup to have this function.

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Generic Input/Output Structure

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Timer Modules – TM

One of the most fundamental functions in any microcontroller device is the ability to control and measure time. To implement time related functions each device includes several Timer Modules, abbreviated to the name TM. The TMs are multi-purpose timing units and serve to provide operations such as Timer/Counter, Input Capture, Compare Match Output and Single Pulse Output as well as being the functional unit for the generation of PWM signals. Each of the TMs has two individual interrupts. The addition of input and output pins for each TM ensures that users are provided with timing units with a wide and flexible range of features.

The common features of the different TM types are described here with more detailed information provided in the individual Compact and Standard TM sections.

Introduction

The devices conta in four TMs h aving a reference name of TM0, TM1, TM2 and TM3. Each individual TM can be categorised as a certain type, namely Compact Type TM or Standard Type

TM. Although similar in nature, the different TM types vary in their feature complexity. The common features to all of the Compact and Standard TMs will be described in this section. The detailed operation regarding each of the TM types will be described in separate sections. The main features and differences between the two types of TMs are summarised in the accompanying table.

Function

Ti�e�/Counte�

I/P Captu�e

Co�pa�e Mat�h Output

PWM Channels

Single Pulse Output

PWM Align�ent

PWM Adjust�ent Pe�iod & Duty

CTM

1

Edge

Duty o� Pe�iod

STM

1

1

Edge

Duty o� Pe�iod

TM Function Summary

Each device in the series contains a specific number of either Compact Type and Standard Type TM units which are shown in the table together with their individual reference name, TM0~TM3.

Device

HT�8FB540/HT�8FB550/HT�8FB5�0

TM0

1�-�it STM

TM1

10-�it STM

TM Name/Type Reference

TM2

10-�it CTM

TM3

10-�it CTM

TM Operation

The different types of TM offer a diverse range of functions, from simple timing operations to

PWM signal generation. The key to understanding how the TM operates is to see it in terms of a free running counter whose value is then compared with the value of pre-programmed internal comparators. When the free running counter has the same value as the pre-programmed comparator, known as a compare match situation, a TM interrupt signal will be generated which can clear the counter and perhaps also change the condition of the TM output pin. The internal TM counter is driven by a user selectable clock source, which can be an internal clock or an external pin.

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TM Clock Source

The clock source which drives the main counter in each TM can originate from various sources.

The selection of the required clock source is implemented using the TnCK2~TnCK0 bits in the TM control registers. The clock source can be a ratio of either the system clock f

SYS

or the internal high clock f

H

, the f

L

clock source or the external TCKn pin. Note that setting these bits to the value 101 will select an undefined clock input, in effect disconnecting the TM clock source. The TCKn pin clock source is used to allow an external signal to drive the TM as an external clock source or for event counting.

TM Interrupts

The Compact and Standard type TMs each have two internal interrupts, one for each of the internal comparator A or comparator P, which generate a TM interrupt when a compare match condition occurs. When a TM interrupt is generated it can be used to clear the counter and also to change the state of the TM output pin.

TM External Pins

Each of the TMs, irrespective of what type, has one TM input pin, with the label TCKn. The TM input pin, is essentially a clock source for the TM and is selected using the TnCK2~TnCK0 bits in the TMnC0 register. This external TM input pin allows an external clock source to drive the internal

TM. This external TM input pin is shared with other functions but will be connected to the internal

TM if selected using the TnCK2~TnCK0 bits. The TM input pin can be chosen to have either a rising or falling active edge.

The TMs each have two output pins with the label TPn. When the TM is in the Compare Match

Output Mode, these pins can be controlled by the TM to switch to a high or low level or to toggle when a compare match situation occurs. The external TPn output pin is also the pin where the TM generates the PWM output waveform. As the TM output pins are pin-shared with other function, the

TM output function must first be setup using registers. A single bit in one of the registers determines if its associated pin is to be used as an external TM output pin or if it is to have another function.

The number of output pins for each TM type and device is different, the details are provided in the accompanying table.

All TM output pin names have a "_n" suffix. Pin names that include a "_0" or "_1" suffix indicate that they are from a TM with multiple output pins. This allows the TM to generate a complimentary output pair, selected using the I/O register data bits.

Device

HT�8FB540

HT�8FB550

HT�8FB5�0

CTM

TP�_0� TP�_1

TP3_0� TP3_1

STM

TP0_0� TP0_1

TP1_0� TP1_1

Registers

TMPC0�

TMPC1

TM Output Pins

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TM Input/Output Pin Control Registers

Selecting to have a TM input/output or whether to retain its other shared function, is implemented using one or two registers, with a single bit in each register corresponding to a TM input/output pin.

Setting the bit high will setup the corresponding pin as a TM input/output, if reset to zero the pin will retain its original other function.

Registers Device

7 6 5 4

Bit

3 2 1 0

TMPC0

TMPC1

HT�8FB540

HT�8FB550

HT�8FB5�0

HT�8FB540

HT�8FB550

HT�8FB5�0

T1CP1 T1CP0

T3CP1 T3CP0

T0CP1 T0CP0

T�CP1 T�CP0

TM Input/Output Pin Control Registers List

TM0 Function Pin Control Block Diagram

Note: 1. The I/O register data bits shown are used for TM output inversion control.

2. In the Capture Input Mode, the TM pin control register must never enable more than one TM input.

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TM1 Function Pin Control Block Diagram

Note: 1. The I/O register data bits shown are used for TM output inversion control.

2. In the Capture Input Mode, the TM pin control register must never enable more than one TM input.

TM2 Function Pin Control Block Diagram

Note: The I/O register data bits shown are used for TM output inversion control.

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TM3 Function Pin Control Block Diagram

Note: The I/O register data bits shown are used for TM output inversion control.

TMPC0 Register

Bit

Na�e

R/W

POR

R

0

7

R

0

6

5

T1CP1

R/W

0

Bit 7~6 "—": unimplemented, read as "0"

Bit 5

T1CP1

: TP1_1 pin Control

0: disable

1: enable

Bit 4

T1CP0

: TP1_0 pin Control

0: disable

1: enable

Bit 3~2

Bit 1

Bit 0

"—": unimplemented, read as "0"

T0CP1

: TP0_1 pin Control

0: disable

1: enable

T0CP0

: TP0_0 pin Control

0: disable

1: enable

4

T1CP0

R/W

1

R

0

3

R

0

2

1

T0CP1

R/W

0

0

T0CP0

R/W

1

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TMPC1 Register

Bit

Na�e

R/W

POR

R

0

7

R

0

6

5

T3CP1

R/W

0

Bit 7~6 "—": unimplemented, read as "0"

Bit 5

T3CP1

: TP3_1 pin Control

0: disable

1: enable

Bit 4

T3CP0

: TP3_0 pin Control

0: disable

1: enable

Bit 3~2

Bit 1

Bit 0

"—": unimplemented, read as "0"

T2CP1

: TP2_1 pin Control

0: disable

1: enable

T2CP0

: TP2_0 pin Control

0: disable

1: enable

4

T3CP0

R/W

1

R

0

3

R

0

2

1

T�CP1

R/W

0

0

T�CP0

R/W

1

Programming Considerations

The TM Counter Registers and the Capture/Compare CCRA register, being either 10-bit or 16bit, all have a low and high byte structure. The high bytes can be directly accessed, but as the low bytes can only be accessed via an internal 8-bit buffer, reading or writing to these register pairs must be carried out in a specific way. The important point to note is that data transfer to and from the 8-bit buffer and its related low byte only takes place when a write or read operation to its corresponding high byte is executed.



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The following steps show the read and write procedures:

• Writing Data to CCRA

Step 1. Write data to Low Byte TMxAL

– note that here data is only written to the 8-bit buffer.

Step 2. Write data to High Byte TMxAH

– here data is written directly to the high byte registers and simultaneously data is latched from

the 8-bit buffer to the Low Byte registers.

• Reading Data from the Counter Registers and CCRA

Step 1. Read data from the High Byte TMxDH or TMxAH

– here data is read directly from the high byte registers and simultaneously data is latched from

the Low Byte register into the 8-bit buffer.

Step 2. Read data from the Low Byte TMxDL or TMxAL

– this step reads data from the 8-bit buffer.

As the CCRA register implemented in the way shown in the following diagram and accessing these register pairs is carried out in a specific way described above, it is recommended to use the "MOV" instruction to access the CCRA low byte register, named TMxAL, using the following access procedures. Accessing the CCRA low byte register without following these access procedures will result in unpredictable values.

Compact Type TM – CTM

Although the simplest form of the two TM types, the Compact TM type still contains three operating modes, which are Compare Match Output, Timer/Event Counter and PWM Output modes. The

Compact TM can also be controlled with an external input pin and can drive two external output pins. These two external output pins can be the same signal or the inverse signal.

CTM

HT�8FB540

HT�8FB550

HT�8FB5�0

Name

10-�it CTM

TM No.

��3

TM Input Pin

TCK�� TCK3

TM Output Pin

TP�_0� TP�_1�

TP3_0� TP3_1�

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Compact Type TM Block Diagram

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Compact TM Operation

At its core is a 10-bit count-up counter which is driven by a user selectable internal or external clock source. There are also two internal comparators with the names, Comparator A and Comparator

P. These comparators will compare the value in the counter with CCRP and CCRA registers. The

CCRP is three bits wide whose value is compared with the highest three bits in the counter while the

CCRA is the ten bits and therefore compares with all counter bits.

The only way of changing the value of the 10-bit counter using the application program, is to clear the counter by changing the TnON bit from low to high. The counter will also be cleared automatically by a counter overflow or a compare match with one of its associated comparators.

When these conditions occur, a TM interrupt signal will also usually be generated. The Compact

Type TM can operate in a number of different operational modes, can be driven by different clock sources including an input pin and can also control an output pin. All operating setup conditions are selected using relevant internal registers.

Compact Type TM Register Description

Overall operation of the Compact TM is controlled using six registers. A read only register pair exists to store the internal counter 10-bit value, while a read/write register pair exists to store the internal 10-bit CCRA value. The remaining two registers are control registers which setup the different operating and control modes as well as the three CCRP bits.

Name

TMnC0

TMnC1

TMnDL

TMnDH

Bit7

TnPAU

TnM1

D7

Bit6

TnCK�

TnM0

D�

Bit5

TnCK1

TnIO1

D5

Bit4

TnCK0

TnIO0

D4

Bit3

TnON

TnOC

D3

Bit2

TnRP�

TnPOL

D�

Bit1

TnRP1

TnDPX

D1

D9

Bit0

TnRP0

TnCCLR

D0

D8

TMnAL

TMnAH

D7

D�

D5

D4

D3

D�

D1

D9

D0

D8

Compact TM Register List (n=2,3)

TMnDL Register

Bit

Na�e

R/W

POR

7

D7

R

0

Bit 7~0

6

D�

R

0

5

D5

R

0

4

D4

R

0

3

D3

R

0

TMnDL

: TMn Counter Low Byte Register bit 7 ~ bit 0

TMn 10-bit Counter bit 7 ~ bit 0

2

D�

R

0

TMnDH Register

Bit

Na�e

R/W

7

POR —

Bit 7~2

Bit 1~0

6

5

4

3

"—": unimplemented, read as "0"

TMnDH

: TMn Counter High Byte Register bit 1~bit 0

TMn 10-bit Counter bit 9~bit 8

2

1

D9

R

0

1

D1

R

0

0

D8

R

0

0

D0

R

0

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TMnAL Register

Bit

Na�e

R/W

POR

7

D7

R/W

0

Bit 7~0

6

D�

R/W

0

5

D5

R/W

0

4

D4

R/W

0

3

D3

R/W

0

TMnAL

: TMn CCRA Low Byte Register bit 7 ~ bit 0

TMn 10-bit CCRA bit 7 ~ bit 0

2

D�

R/W

0

1

D1

R/W

0

0

D0

R/W

0

TMnAH Register

Bit

Na�e

R/W

POR

7

Bit 7~2

Bit 1~0

6

5

4

3

"—": unimplemented, read as "0"

TMnAH

: TMn CCRA High Byte Register bit 1~bit 0

TMn 10-bit CCRA bit 9~bit 8

2

1

D9

R/W

0

0

D8

R/W

0

TMnC0 Register

Bit

Na�e

R/W

POR

Bit 7

Bit 6~4

7

TnPAU

R/W

0

6

TnCK�

R/W

0

5

TnCK1

R/W

0

4

TnCK0

R/W

0

3

TnON

R/W

0

2

TnRP�

R/W

0

1

TnRP1

R/W

0

0

TnRP0

R/W

0

TnPAU

: TMn Counter Pause Control

0: run

1: pause

The counter can be paused by setting this bit high. Clearing the bit to zero restores normal counter operation. When in a Pause condition the TM will remain powered up and continue to consume power. The counter will retain its residual value when this bit changes from low to high and resume counting from this value when the bit changes to a low value again.

TnCK2~TnCK0

: Select TMn Counter clock

000: f

SYS

/4

001: f

SYS

010: f

H

/16

011: f

H

/64

100: f

L

101: Undefined

110: TCKn rising edge clock

111: TCKn falling edge clock

These three bits are used to select the clock source for the TMn. Selecting the

Reserved clock input will effectively disable the internal counter. The external pin clock source can be chosen to be active on the rising or falling edge. The clock source f

SYS

is the system clock, while f

H

and f

L

are other internal c locks, the details of which can be found in the oscillator section.

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Bit 3

Bit 2~0

TnON

: TMn Counter On/Off Control

0: Off

1: On

This bit controls the overall on/off function of the TMn. Setting the bit high enables the counter to run, clearing the bit disables the TMn. Clearing this bit to zero will stop the counter from counting and turn off the TMn which will reduce its power consumption. When the bit changes state from low to high the internal counter value will be reset to zero, however when the bit changes from high to low, the internal counter will retain its residual value. If the TMn is in the Compare Match Output

Mode then the TMn output pin will be reset to its initial condition, as specified by the

TnOC bit, when the TnON bit changes from low to high.

TnRP2~TnRP0

: TMn CCRP 3-bit register, compared with the TMn Counter bit 9~bit

7 Comparator P Match Period

000: 1024 TMn clocks

001: 128 TMn clocks

010: 256 TMn clocks

011: 384 TMn clocks

100: 512 TMn clocks

101: 640 TMn clocks

110: 768 TMn clocks

111: 896 TMn clocks

These three bits are used to setup the value on the internal CCRP 3-bit register, which are then compared with the internal counter’s highest three bits. The result of this comparison can be selected to clear the internal counter if the TnCCLR bit is set to zero.

Setting the TnCCLR bit to zero ensures that a compare match with the CCRP values will reset the internal counter. As the CCRP bits are only compared with the highest three counter bits, the compare values exist in 128 clock cycle multiples. Clearing all three bits to zero is in effect allowing the counter to overflow at its maximum value.

TMnC1 Register

Bit

Na�e

R/W

POR

Bit 7~6

Bit 5~4

7

TnM1

R/W

0

6

TnM0

R/W

0

5

TnIO1

R/W

0

4

TnIO0

R/W

0

3

TnOC

R/W

0

2

TnPOL

R/W

0

1

TnDPX

R/W

0

0

TnCCLR

R/W

0

TnM1 ~ TnM0

: Select TMn Operating Mode

00: Compare Match Output Mode

01: Undefined

10: PWM Mode

11: Timer/Counter Mode

These bits setup the required operating mode for the TM. To ensure reliable operation the TM should be switched off before any changes are made to the TnM1 and TnM0 bits. In the Timer/Counter Mode, the TM output pin control must be disabled.

TnIO1~TnIO0

: Select TPn_0, TPn_1 output function

Compare Match Output Mode

00: No change

01: Output low

10: Output high

11: Toggle output

PWM Mode

00: PWM Output inactive state

01: PWM Output active state

10: PWM output

11: Undefined

Timer/counter Mode

unused

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Bit 3

Bit 2

Bit 1

Bit 0

These two bits are used to determine how the TMn output pin changes state when a certain condition is reached. The function that these bits select depends upon in which mode the TMn is running. In the Compare Match Output Mode, the TnIO1 and TnIO0 bits determine how the TMn output pin changes state when a compare match occurs from the Comparator A. The TMn output pin can be setup to switch high, switch low or to toggle its present state when a compare match occurs from the Comparator A. When the bits are both zero, then no change will take place on the output. The initial value of the TMn output pin should be setup using the TnOC bit in the TMnC1 register. Note that the output level requested by the TnIO1 and TnIO0 bits must be different from the initial value setup using the TnOC bit otherwise no change will occur on the TMn output pin when a compare match occurs. After the TMn output pin changes state it can be reset to its initial level by changing the level of the TnON bit from low to high.

In the PWM Mode, the TnIO1 and TnIO0 bits determine how the TM output pin changes state when a certain compare match condition occurs. The PWM output function is modified by changing these two bits. It is necessary to only change the values of the TnIO1 and TnIO0 bits only after the TMn has been switched off.

Un predictable PWM outputs will occur if the TnIO1 and TnIO0 bits are changed when the TM is running.

TnOC

: TPn_0, TPn_1 Output control bit

Compare Match Output Mode

0: Initial low

1: Initial high

PWM Mode

0: Active low

1: Active high

This is the output control bit for the TMn output pin. Its operation depends upon whether TMn is being used in the Compare Match Output Mode or in the PWM Mode.

It has no effect if the TMn is in the Timer/Counter Mode. In the Compare Match

Output Mode it determines the logic level of the TMn output pin before a compare match occurs. In the PWM Mode it determines if the PWM signal is active high or active low.

TnPOL

: TPn_0, TPn_1 Output polarity Control

0: Non-invert

1: Invert

This bit controls the polarity of the TPn_0 or TPn_1 output pin. When the bit is set high the TMn output pin will be inverted and not inverted when the bit is zero. It has no effect if the TMn is in the Timer/Counter Mode.

TnDPX

: TMn PWM period/duty Control

0: CCRP - period; CCRA - duty

1: CCRP - duty; CCRA - period

This bit determines which of the CCRA and CCRP registers are used for period and duty control of the PWM waveform.

TnCCLR

: Select TMn Counter clear condition

0: TMn Comparator P match

1: TMn Comparator A match

This bit is used to select the method which clears the counter. Remember that the

Compact TMn contains two comparators, Comparator A and Comparator P, either of which can be selected to clear the internal counter. With the TnCCLR bit set high, the counter will be cleared when a compare match occurs from the Comparator A.

When the bit is low, the counter will be cleared when a compare match occurs from the Comparator P or with a counter overflow. A counter overflow clearing method can only be implemented if the CCRP bits are all cleared to zero. The TnCCLR bit is not used in the PWM Mode.

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Compact Type TM Operating Modes

The Compact Type TM can operate in one of three operating modes, Compare Match Output Mode,

PWM Mode or Timer/Counter Mode. The operating mode is selected using the TnM1 and TnM0 bits in the TMnC1 register.

Compare Match Output Mode

To select this mode, bits TnM1 and TnM0 in the TMnC1 register, should be set to "00" respectively.

In this mode once the counter is enabled and running it can be cleared by three methods. These are a counter overflow, a compare match from Comparator A and a compare match from Comparator P.

When the TnCCLR bit is low, there are two ways in which the counter can be cleared. One is when a compare match occurs from Comparator P, the other is when the CCRP bits are all zero which allows the counter to overflow. Here both TnAF and TnPF interrupt request flags for the Comparator

A and Comparator P respectively, will both be generated.

If the TnCCLR bit in the TMnC1 register is high then the counter will be cleared when a compare match occurs from Comparator A. However, here only the TnAF interrupt request flag will be generated even if the value of the CCRP bits is less than that of the CCRA registers. Therefore when

TnCCLR is high no TnPF interrupt request flag will be generated. If the CCRA bits are all zero, the counter will overflow when its reaches its maximum 10-bit, 3FF Hex, value, however here the TnAF interrupt request flag will not be generated.

As the name of the mode suggests, after a comparison is made, the TM output pin will change state. The TM output pin condition however only changes state when a TnAF interrupt request flag is generated after a compare match occurs from Comparator A. The TnPF interrupt request flag, generated from a compare match occurs from Comparator P, will have no effect on the TM output pin. The way in which the TM output pin changes state are determined by the condition of the

TnIO1 and TnIO0 bits in the TMnC1 register. The TM output pin can be selected using the TnIO1 and TnIO0 bits to go high, to go low or to toggle from its present condition when a compare match occurs from Comparator A. The initial condition of the TM output pin, which is setup after the

TnON bit changes from low to high, is setup using the TnOC bit. Note that if the TnIO1 and TnIO0 bits are zero then no pin change will take place.

HT68FB540/HT68FB550/HT68FB560

I/O Flash USB MCU with SPI

Rev. 1.40

98 De�e��e� 01� �01� Rev. 1.40 99 De�e��e� 01� �01�

HT68FB540/HT68FB550/HT68FB560

I/O Flash USB MCU with SPI

HT68FB540/HT68FB550/HT68FB560

I/O Flash USB MCU with SPI

TnON

TnPAU

TnPOL

CCRP Int.

Flag TnPF

CCRA Int.

Flag TnAF

Counte� Value

0x3FF

Counte� ove�flow

CCRP=0

CCRP > 0

CCRP > 0

TnCCLR = 0; TnM [1:0] = 00

Counte� �lea�ed �y CCRP value

Resu�e

CCRP

CCRA

Pause Stop

Ti�e

TM O/P Pin

Output pin set to initial Level Low if TnOC=0

Output Toggle with

TnAF flag

He�e TnIO [1:0] = 11

Toggle Output sele�t

Note TnIO [1:0] = 10

Output not affe�ted �y TnAF flag. Re�ains High until �eset

�y TnON �it

A�tive High Output sele�t

Output Inve�ts when TnPOL is high

Output Pin

Reset to Initial value

Output �ont�olled �y othe� pin-sha�ed fun�tion

Compare Match Output Mode – TnCCLR= 0

Note: 1. With TnCCLR= 0, a Comparator P match will clear the counter

2. The TM output pin is controlled only by the TnAF flag

3. The output pin is reset to its initial state by a TnON bit rising edge

Rev. 1.40

98 De�e��e� 01� �01� Rev. 1.40 99 De�e��e� 01� �01�

HT68FB540/HT68FB550/HT68FB560

I/O Flash USB MCU with SPI

Counte� Value

0x3FF

CCRA

CCRP

TnCCLR = 1; TnM [1:0] = 00

CCRA > 0 Counte� �lea�ed �y CCRA value

CCRA = 0

Counte� ove�flow

Resu�e

Pause

CCRA=0

Stop Counte� Resta�t

Ti�e

TnON

TnPAU

TnPOL

CCRA Int.

Flag TnAF

CCRP Int.

Flag TnPF

No TnAF flag gene�ated on

CCRA ove�flow

TM O/P Pin

TnPF not gene�ated

Output pin set to initial Level Low if TnOC=0

Output Toggle with

TnAF flag

He�e TnIO [1:0] = 11

Toggle Output sele�t

Output does not �hange

Note TnIO [1:0] = 10

Output not affe�ted �y

TnAF flag. Re�ains High until �eset �y TnON �it

A�tive High Output sele�t

Output Inve�ts when TnPOL is high

Output Pin

Reset to Initial value

Output �ont�olled �y othe� pin-sha�ed fun�tion

Compare Match Output Mode – TnCCLR= 1

Note: 1. With TnCCLR= 1, a Comparator A match will clear the counter

2. The TM output pin is controlled only by the TnAF flag

3. The output pin is reset to its initial state by a TnON bit rising edge

4. The TnPF flag is not generated when TnCCLR= 1

Timer/Counter Mode

To select this mode, bits TnM1 and TnM0 in the TMnC1 register should be set to 11 respectively.

The Timer/Counter Mode operates in an identical way to the Compare Match Output Mode generating the same interrupt flags. The exception is that in the Timer/Counter Mode the TM output pin is not used. Therefore the above description and Timing Diagrams for the Compare Match

Output Mode can be used to understand its function. As the TM output pin is not used in this mode, the pin can be used as a normal I/O pin or other pin-shared function.

Rev. 1.40

100 De�e��e� 01� �01�

HT68FB540/HT68FB550/HT68FB560

I/O Flash USB MCU with SPI

Rev. 1.40 101 De�e��e� 01� �01�

HT68FB540/HT68FB550/HT68FB560

I/O Flash USB MCU with SPI

Rev. 1.40

100 De�e��e� 01� �01�

HT68FB540/HT68FB550/HT68FB560

I/O Flash USB MCU with SPI

PWM Output Mode

To select this mode, bits TnM1 and TnM0 in the TMnC1 register should be set to 10 respectively.

The PWM function within the TM is useful for applications which require functions such as motor control, heating control, illumination control etc. By providing a signal of fixed frequency but of varying duty cycle on the TM output pin, a square wave AC waveform can be generated with varying equivalent DC RMS values.

As both the period and duty cycle of the PWM waveform can be controlled, the choice of generated waveform is extremely flexible. In the PWM mode, the TnCCLR bit has no effect on the PWM operation. Both of the CCRA and CCRP registers are used to generate the PWM waveform, one register is used to clear the internal counter and thus control the PWM waveform frequency, while the other one is used to control the duty cycle. Which register is used to control either frequency or duty cycle is determined using the TnDPX bit in the TMnC1 register. The PWM waveform frequency and duty cycle can therefore be controlled by the values in the CCRA and CCRP registers.

An interrupt flag, one for each of the CCRA and CCRP, will be generated when a compare match occurs from either Comparator A or Comparator P. The TnOC bit in the TMnC1 register is used to select the required polarity of the PWM waveform while the two TnIO1 and TnIO0 bits are used to enable the PWM output or to force the TM output pin to a fixed high or low level. The TnPOL bit is used to reverse the polarity of the PWM output waveform.

CTM, PWM Mode, Edge-aligned Mode, TnDPX= 0

CCRP 001b 010b 011b 100b

Pe�iod

Duty

1�8 �5� 384 51�

CCRA

101b

�40

110b

7�8

111b

89�

000b

10�4

If f

SYS

= 16MHz, TM clock source is f

SYS

/4, CCRP = 100b and CCRA = 128,

The CTM PWM output frequency = (f

SYS

/4)/512 = f

SYS

/2048 = 7.8125kHz, duty = 128/512 = 25%.

If the Duty value defined by the CCRA register is equal to or greater than the Period value, then the

PWM output duty is 100%.

CTM, PWM Mode, Edge-aligned Mode, TnDPX= 1

CCRP 001b 010b 011b 100b

Pe�iod

Duty 1�8 �5� 384 51�

CCRA

101b

�40

110b 111b 000b

7�8 89�

10�4

The PWM output period is determined by the CCRA register value together with the TM clock while the PWM duty cycle is defined by the CCRP register value.

Rev. 1.40 101 De�e��e� 01� �01�

HT68FB540/HT68FB550/HT68FB560

I/O Flash USB MCU with SPI

Counte� Value

CCRP

CCRA

Counte� �lea�ed

�y CCRP

Pause Resu�e

TnDPX = 0; TnM [1:0] = 10

Counte� Reset when

TnON �etu�ns high

Counte� Stop if

TnON �it low

TnON

TnPAU

TnPOL

CCRA Int.

Flag TnAF

CCRP Int.

Flag TnPF

TM O/P Pin

(TnOC=1)

TM O/P Pin

(TnOC=0)

PWM Duty Cy�le set �y CCRA

PWM �esu�es ope�ation

Output �ont�olled �y othe� pin-sha�ed fun�tion

Output Inve�ts when TnPOL = 1

PWM Pe�iod set �y CCRP

PWM Mode – TnDPX= 0

Note: 1. Here TnDPX= 0 – Counter cleared by CCRP

2. A counter clear sets the PWM Period

3. The internal PWM function continues even when TnIO [1:0] = 00 or 01

4. The TnCCLR bit has no influence on PWM operation

Ti�e

HT68FB540/HT68FB550/HT68FB560

I/O Flash USB MCU with SPI

Rev. 1.40

10� De�e��e� 01� �01� Rev. 1.40 103 De�e��e� 01� �01�

HT68FB540/HT68FB550/HT68FB560

I/O Flash USB MCU with SPI

HT68FB540/HT68FB550/HT68FB560

I/O Flash USB MCU with SPI

Counte� Value

Counte� �lea�ed

�y CCRA

TnDPX = 1; TnM [1:0] = 10

CCRA

CCRP

Pause Resu�e

Counte� Stop if

TnON �it low

TnON

TnPAU

TnPOL

CCRP Int.

Flag TnPF

CCRA Int.

Flag TnAF

TM O/P Pin

(TnOC=1)

TM O/P Pin

(TnOC=0)

PWM Duty Cy�le set �y CCRP

PWM �esu�es ope�ation

Output �ont�olled �y othe� pin-sha�ed fun�tion

Output Inve�ts when TnPOL = 1

PWM Pe�iod set �y CCRA

PWM Mode – TnDPX= 1

Note: 1. Here TnDPX = 1 – Counter cleared by CCRA

2. A counter clear sets the PWM Period

3. The internal PWM function continues even when TnIO [1:0] = 00 or 01

4. The TnCCLR bit has no influence on PWM operation

Ti�e

Rev. 1.40

10� De�e��e� 01� �01� Rev. 1.40 103 De�e��e� 01� �01�

HT68FB540/HT68FB550/HT68FB560

I/O Flash USB MCU with SPI

Standard Type TM – STM

The Standard Type TM contains five operating modes, which are Compare Match Output, Timer/

Event Counter, Capture Input, Single Pulse Output and PWM Output modes. The Standard TM can also be controlled with an external input pin and can drive one or two external output pins.

Name TM No.

TM Input Pin TM Output Pin STM

HT�8FB540

HT�8FB550

HT�8FB5�0

1�-�it STM

10-�it STM

0�

1

TCK0�

TCK1

TP0_0� TP0_1

TP1_0� TP1_1

Standard TM Operation

There are two sizes of Standard TMs, one is 10-bit wide and the other is 16-bit wide. At the core is a

10 or 16-bit count-up counter which is driven by a user selectable internal or external clock source.

There are also two internal comparators with the names, Comparator A and Comparator P. These comparators will compare the value in the counter with CCRP and CCRA registers. The CCRP comparator is 3 or 8-bits wide whose value is compared the with highest 3 or 8 bits in the counter while the CCRA is the ten or sixteen bits and therefore compares all counter bits.

The only way of changing the value of the 10 or 16-bit counter using the application program, is to clear the counter by changing the TnON bit from low to high. The counter will also be cleared automatically by a counter overflow or a compare match with one of its associated comparators.

When these conditions occur, a TM interrupt signal will also usually be generated. The Standard

Type TM can operate in a number of different operational modes, can be driven by different clock sources including an input pin and can also control an output pin. All operating setup conditions are selected using relevant internal registers.

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Standard Type TM Block Diagram

†

­ † ­

  ­  

ˆ

ˆ

Rev. 1.40

104 De�e��e� 01� �01�

HT68FB540/HT68FB550/HT68FB560

I/O Flash USB MCU with SPI

Rev. 1.40 105 De�e��e� 01� �01�

HT68FB540/HT68FB550/HT68FB560

I/O Flash USB MCU with SPI

Rev. 1.40

104 De�e��e� 01� �01�

HT68FB540/HT68FB550/HT68FB560

I/O Flash USB MCU with SPI

Standard Type TM Register Description

Overall operation of the Standard TM is controlled using a series of registers. A read only register pair exists to store the internal counter 10 or 16-bit value, while a read/write register pair exists to store the internal 10 or 16-bit CCRA value. The remaining two registers are control registers which setup the different operating and control modes as well as the three or eight CCRP bits.

16-bit Standard TM Register List

Name

TM0C0

Bit7

T0PAU

Bit6

T0CK�

TM0C1

TM0DL

TM0DH

TM0AL

TM0AH

TM0RP

T0M1

D7

D15

D7

D15

D7

T0M0

D�

D14

D�

D14

D�

Bit5

T0CK1

T0IO1

D5

D13

D5

D13

D5

Bit4

T0CK0

T0IO0

D4

D1�

D4

D1�

D4

Bit3

T0ON

T0OC

D3

D11

D3

D11

D3

Bit2

T0POL

D�

D10

D�

D10

D�

Bit1

T0PX

D1

D9

D1

D9

D1

Bit0

T0CLR

D0

D8

D0

D8

D0

• TM0C0 Register

Bit

Na�e

7

T0PAU

R/W

POR

R/W

0

Bit 7

Bit 6~4

6

T0CK�

R/W

0

5

T0CK1

R/W

0

4

T0CK0

R/W

0

3

T0ON

R/W

0

R

0

2

R

0

1

R

0

0

T0PAU

: TM0 Counter Pause Control

0: Run

1: Pause

The counter can be paused by setting this bit high. Clearing the bit to zero restores normal counter operation. When in a Pause condition the TM will remain powered up and continue to consume power. The counter will retain its residual value when this bit changes from low to high and resume counting from this value when the bit changes to a low value again.

T0CK2, T0CK1, T0CK0

: Select TM0 Counter clock

000: f

SYS/

4

001: f

SYS

010: f

H

/16

011: f

H

/64

100: f

L

101: Reserved

110: TCK0 rising edge clock

111: TCK0 falling edge clock

These three bits are used to select the clock source for the TM. Selecting the Reserved clock input will effectively disable the internal counter. The external pin clock source can be chosen to be active on the rising or falling edge. The clock source f

SYS

is the system clock, while f

H

and f

L

are other internal clocks, the details of which can be found in the oscillator section.

Rev. 1.40 105 De�e��e� 01� �01�

HT68FB540/HT68FB550/HT68FB560

I/O Flash USB MCU with SPI

Rev. 1.40

Bit 3

Bit 2~0

T0ON

: TM0 Counter On/Off Control

0: Off

1: On

This bit controls the overall on/off function of the TM. Setting the bit high enables the counter to run, clearing the bit disables the TM. Clearing this bit to zero will stop the counter from counting and turn off the TM which will reduce its power consumption.

When the bit changes state from low to high the internal counter value will be reset to zero, however when the bit changes from high to low, the internal counter will retain its residual value until the bit returns high again. If the TM is in the Compare Match

Output Mode then the TM output pin will be reset to its initial condition, as specified by the T0OC bit, when the T0ON bit changes from low to high.

"—": unimplemented, read as "0"

• TM0C1 Register

Bit

Na�e

7

T0M1

R/W

POR

R/W

0

Bit 7~6

Bit 5~4

6

T0M0

R/W

0

5

T0IO1

R/W

0

4

T0IO0

R/W

0

3

T0OC

R/W

0

2

T0POL

R/W

0

1

T0DPX

R/W

0

0

T0CCLR

R/W

0

T0M1~T0M0

: Select TM0 Operating Mode

00: Compare Match Output Mode

01: Capture Input Mode

10: PWM Mode or Single Pulse Output Mode

11: Timer/Counter Mode

These bits setup the required operating mode for the TM. To ensure reliable operation the TM should be switched off before any changes are made to the T0M1 and T0M0 bits. In the Timer/Counter Mode, the TM output pin control must be disabled.

T0IO1~T0IO0

: Select TP0_0, TP0_1 output function

Compare Match Output Mode

00: No change

01: Output low

10: Output high

11: Toggle output

PWM Mode/ Single Pulse Output Mode

00: Force inactive state

01: Force active state

10: PWM output

11: Single pulse output

Capture Input Mode

00: Input capture at rising edge of TP0_0, TP0_1

01: Input capture at falling edge of TP0_0, TP0_1

10: Input capture at falling/rising edge of TP0_0, TP0_1

11: Input capture disabled

Timer/counter Mode:

Unused

These two bits are used to determine how the TM output pin changes state when a certain condition is reached. The function that these bits select depends upon in which mode the

TM is running.

In the Compare Match Output Mode, the T0IO1 and T0IO0 bits determine how the TM output pin changes state when a compare match occurs from the Comparator A. The TM output pin can be setup to switch high, switch low or to toggle its present state when a compare match occurs from the Comparator A. When the bits are both zero, then no change will take place on the output. The initial value of the TM output pin should be setup using the T0OC bit in the

TM0C1 register. Note that the output level requested by the T0IO1 and T0IO0 bits must be different from the initial value setup using the T0OC bit otherwise no change will occur on the

TM output pin when a compare match occurs. After the TM output pin changes state it can be reset to its initial level by changing the level of the T0ON bit from low to high.

10� De�e��e� 01� �01�

HT68FB540/HT68FB550/HT68FB560

I/O Flash USB MCU with SPI

Rev. 1.40 107 De�e��e� 01� �01�

HT68FB540/HT68FB550/HT68FB560

I/O Flash USB MCU with SPI

Rev. 1.40

10� De�e��e� 01� �01�

HT68FB540/HT68FB550/HT68FB560

I/O Flash USB MCU with SPI

Bit 3

Bit 2

Bit 1

Bit 0

• TM0DL Register

Bit 7

Na�e

R/W

POR

D7

R

0

In the PWM Mode, the T0IO1 and T0IO0 bits determine how the TM output pin changes state when a certain compare match condition occurs. The PWM output function is modified by changing these two bits. It is necessary to only change the values of the T0IO1 and T0IO0 bits only after the TM has been switched off.

U npredictable PWM outputs will occur if the T0IO1 and T0IO0 bits are changed when the TM is running.

T0OC

: TP0_0, TP0_1 Output control bit

Compare Match Output Mode

0: Initial low

1: Initial high

PWM Mode/ Single Pulse Output Mode

0: Active low

1: Active high

This is the output control bit for the TM output pin. Its operation depends upon whether TM is being used in the Compare Match Output Mode or in the PWM Mode/

Single Pulse Output Mode. It has no effect if the TM is in the Timer/Counter Mode. In the Compare Match Output Mode it determines the logic level of the TM output pin before a compare match occurs. In the PWM Mode it determines if the PWM signal is active high or active low.

T0POL

: TP0_0, TP0_1 Output polarity Control

0: Non-invert

1: Invert

This bit controls the polarity of the TP0_0 or TP0_1 output pin. When the bit is set high the TM output pin will be inverted and not inverted when the bit is zero. It has no effect if the TM is in the Timer/Counter Mode.

T0DPX

: TM0 PWM period/duty Control

0: CCRP - period; CCRA - duty

1: CCRP - duty; CCRA - period

This bit, determines which of the CCRA and CCRP registers are used for period and duty control of the PWM waveform.

T0CCLR

: Select TM0 Counter clear condition

0: TM0 Comparator P match

1: TM0 Comparator A match

This bit is used to select the method which clears the counter. Remember that the

Standard TM contains two comparators, Comparator A and Comparator P, either of which can be selected to clear the internal counter. With the T0CCLR bit set high, the counter will be cleared when a compare match occurs from the Comparator A.

When the bit is low, the counter will be cleared when a compare match occurs from the Comparator P or with a counter overflow. A counter overflow clearing method can only be implemented if the CCRP bits are all cleared to zero. The T0CCLR bit is not used in the PWM, Single Pulse or Input Capture Mode.

6

D�

R

0

5

D5

R

0

4

D4

R

0

3

D3

R

0

2

D�

R

0

1

D1

R

0

0

D0

R

0

Bit 7~0

TM0DL

: TM0 Counter Low Byte Register bit 7~bit 0

TM0 16-bit Counter bit 7~bit 0

Rev. 1.40 107 De�e��e� 01� �01�

Rev. 1.40

HT68FB540/HT68FB550/HT68FB560

I/O Flash USB MCU with SPI

• TM0DH Register

Bit

Na�e

R/W

POR

7

D15

R

0

6

D14

R

0

5

D13

R

0

4

D1�

R

0

3

D11

R

0

Bit 7~0

TM0AL

: TM0 CCRA Low Byte Register bit 7~bit 0

TM0 16-bit CCRA bit 7~bit 0

• TM0AH Register

Bit 7

Na�e

R/W

POR

D15

R/W

0

6

D14

R/W

0

5

D13

R/W

0

4

D1�

R/W

0

3

D11

R/W

0

2

D10

R

0

Bit 7~0

TM0DH

: TM0 Counter High Byte Register bit 7~bit 0

TM0 16-bit Counter bit 15~bit 8

• TM0AL Register

Bit

Na�e

R/W

POR

7

D7

R/W

0

6

D�

R/W

0

5

D5

R/W

0

4

D4

R/W

0

3

D3

R/W

0

2

D�

R/W

0

2

D10

R/W

0

1

D1

R/W

0

1

D9

R

0

0

D0

R/W

0

0

D8

R

0

1

D9

R/W

0

0

D8

R/W

0

Bit 7~0

Bit 7~0

TM0AH

: TM0 CCRA High Byte Register bit 7~bit 0

TM0 16-bit CCRA bit 15~bit 8

• TM0RP Register

Bit

Na�e

R/W

POR

7

D7

R/W

0

6

D�

R/W

0

5

D5

R/W

0

4

D4

R/W

0

3

D3

R/W

0

2

D�

R/W

0

1

D1

R/W

0

0

D0

R/W

0

TM0RP

: TM0 CCRP Register bit 7~bit 0

TM0 CCRP 8-bit register, compared with the TM0 Counter bit 15~bit 8. Comparator P

Match Period

0: 65536 TM0 clocks

1~255: 256 x (1~255) TM0 clocks

These eight bits are used to setup the value on the internal CCRP 8-bit register, which are then compared with the internal counter’s highest eight bits. The result of this comparison can be selected to clear the internal counter if the T0CCLR bit is set to zero. Setting the T0CCLR bit to zero ensures that a compare match with the CCRP values will reset the internal counter. As the CCRP bits are only compared with the highest eight counter bits, the compare values exist in 256 clock cycle multiples.

Clearing all eight bits to zero is in effect allowing the counter to overflow at its maximum value.

10-bit Standard TM Register List

Name

TM1C0

TM1C1

TM1DL

TM1DH

TM1AL

TM1AH

Bit7

T1PAU

T1M1

D7

D7

Bit6

T1CK�

T1M0

D�

D�

Bit5

T1CK1

T1IO1

D5

D5

Bit4

T1CK0

T1IO0

D4

D4

Bit3

T1ON

T1OC

D3

D3

Bit2

T1RP�

T1POL

D�

D�

Bit1

T1RP1

T1DPX

D1

D9

D1

D9

Bit0

T1RP0

T1CCLR

D0

D8

D0

D8

108 De�e��e� 01� �01�

HT68FB540/HT68FB550/HT68FB560

I/O Flash USB MCU with SPI

Rev. 1.40 109 De�e��e� 01� �01�

HT68FB540/HT68FB550/HT68FB560

I/O Flash USB MCU with SPI

Rev. 1.40

108 De�e��e� 01� �01�

HT68FB540/HT68FB550/HT68FB560

I/O Flash USB MCU with SPI

Rev. 1.40

• TM1C0 Register

Bit

Na�e

R/W

POR

7

T1PAU

R/W

0

Bit 7

Bit 6~4

Bit 3

Bit 2~0

6

T1CK�

R/W

0

5

T1CK1

R/W

0

4

T1CK0

R/W

0

3

T1ON

R/W

0

2

T1RP�

R/W

0

1

T1RP1

R/W

0

0

T1RP0

R/W

0

T1PAU

: TM1 Counter Pause Control

0: run

1: pause

The counter can be paused by setting this bit high. Clearing the bit to zero restores normal counter operation. When in a Pause condition the TM will remain powered up and continue to consume power. The counter will retain its residual value when this bit changes from low to high and resume counting from this value when the bit changes to a low value again.

T1CK2~T1CK0

: Select TM1 Counter clock

000: f

SYS

/4

001: f

SYS

010: f

H

/16

011: f

H

/64

100: f

L

101: Undefined

110: TCK1 rising edge clock

111: TCK1 falling edge clock

These three bits are used to select the clock source for the TM. Selecting the Reserved clock input will effectively disable the internal counter. The external pin clock source can be chosen to be active on the rising or falling edge. The clock source f

SYS

is the system clock, while f

H

and f

L

are other internal clocks, the details of which can be found in the oscillator section.

T1ON

: TM1 Counter On/Off Control

0: Off

1: On

This bit controls the overall on/off function of the TM. Setting the bit high enables the counter to run, clearing the bit disables the TM. Clearing this bit to zero will stop the counter from counting and turn off the TM which will reduce its power consumption. When the bit changes state from low to high the internal counter value will be reset to zero, however when the bit changes from high to low, the internal counter will retain its residual value until the bit returns high again.

If the TM is in the Compare Match Output Mode then the TM output pin will be reset to its initial condition, as specified by the T1OC bit, when the T1ON bit changes from low to high.

T1RP2~T1RP0

: TMn CCRP 3-bit register, compared with the TMn Counter bit 9~bit 7

Comparator P Match Period

000: 1024 TM1 clocks

001: 128 TM1 clocks

010: 256 TM1 clocks

011: 384 TM1 clocks

100: 512 TM1 clocks

101: 640 TM1 clocks

110: 768 TM1 clocks

111: 896 TM1 clocks

These three bits are used to setup the value on the internal CCRP 3-bit register, which are then compared with the internal counter’s highest three bits. The result of this comparison can be selected to clear the internal counter if the T1CCLR bit is set to zero.

Setting the T1CCLR bit to zero ensures that a compare match with the CCRP values will reset the internal counter. As the CCRP bits are only compared with the highest three counter bits, the compare values exist in 128 clock cycle multiples. Clearing all three bits to zero is in effect allowing the counter to overflow at its maximum value.

109 De�e��e� 01� �01�

Rev. 1.40

HT68FB540/HT68FB550/HT68FB560

I/O Flash USB MCU with SPI

• TM1C1 Register

Bit

Na�e

7

T1M1

R/W

POR

R/W

0

Bit 7~6

Bit 5~4

6

T1M0

R/W

0

5

T1IO1

R/W

0

4

T1IO0

R/W

0

3

T1OC

R/W

0

2

T1POL

R/W

0

1

T1DPX

R/W

0

0

T1CCLR

R/W

0

T1M1~T1M0

: Select TM1 Operating Mode

00: Compare Match Output Mode

01: Capture Input Mode

10: PWM Mode or Single Pulse Output Mode

11: Timer/Counter Mode

These bits setup the required operating mode for the TM. To ensure reliable operation the TM should be switched off before any changes are made to the T1M1 and T1M0 bits. In the Timer/Counter Mode, the TM output pin control must be disabled.

T1IO1~T1IO0

: Select TP1_0, TP1_1 output function

Compare Match Output Mode

00: No change

01: Output low

10: Output high

11: Toggle output

PWM Mode/Single Pulse Output Mode

00: PWM Output inactive state

01: PWM Output active state

10: PWM output

11: Single pulse output

Capture Input Mode

00: Input capture at rising edge of TP1_0, TP1_1

01: Input capture at falling edge of TP1_0, TP1_1

10: Input capture at falling/rising edge of TP1_0, TP1_1

11: Input capture disabled

Timer/counter Mode:

Unused

These two bits are used to determine how the TM output pin changes state when a certain condition is reached. The function that these bits select depends upon in which mode the TM is running.

In the Compare Match Output Mode, the T1IO1 and T1IO0 bits determine how the

TM output pin changes state when a compare match occurs from the Comparator A.

The TM output pin can be setup to switch high, switch low or to toggle its present state when a compare match occurs from the Comparator A. When the bits are both zero, then no change will take place on the output. The initial value of the TM output pin should be setup using the T1OC bit in the TM1C1 register. Note that the output level requested by the T1IO1 and T1IO0 bits must be different from the initial value setup using the T1OC bit otherwise no change will occur on the TM output pin when a compare match occurs. After the TM output pin changes state it can be reset to its initial level by changing the level of the T1ON bit from low to high.

In the PWM Mode, the T1IO1 and T1IO0 bits determine how the TM output pin changes state when a certain compare match condition occurs. The PWM output function is modified by changing these two bits. It is necessary to only change the values of the T1IO1 and T1IO0 bits only after the TM has been switched off.

U npredictable PWM outputs will occur if the T1IO1 and T1IO0 bits are changed when the TM is running

110 De�e��e� 01� �01�

HT68FB540/HT68FB550/HT68FB560

I/O Flash USB MCU with SPI

Rev. 1.40 111 De�e��e� 01� �01�

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I/O Flash USB MCU with SPI

Rev. 1.40

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HT68FB540/HT68FB550/HT68FB560

I/O Flash USB MCU with SPI

Bit 3

Bit 2

Bit 1

Bit 0

T1OC

: TP1_0, TP1_1 Output control bit

Compare Match Output Mode

0: initial low

1: initial high

PWM Mode/ Single Pulse Output Mode

0: Active low

1: Active high

This is the output control bit for the TM output pin. Its operation depends upon whether TM is being used in the Compare Match Output Mode or in the PWM Mode/

Single Pulse Output Mode. It has no effect if the TM is in the Timer/Counter Mode. In the Compare Match Output Mode it determines the logic level of the TM output pin before a compare match occurs. In the PWM Mode it determines if the PWM signal is active high or active low.

T1POL

: TP1_0, TP1_1 Output polarity Control

0: non-invert

1: invert

This bit controls the polarity of the TP1_0 or TP1_1 output pin. When the bit is set high the TM output pin will be inverted and not inverted when the bit is zero. It has no effect if the TM is in the Timer/Counter Mode.

T1DPX

: TMn PWM period/duty Control

0: CCRP - period; CCRA - duty

1: CCRP - duty; CCRA - period

This bit, determines which of the CCRA and CCRP registers are used for period and duty control of the PWM waveform.

T1CCLR

: Select TM1 Counter clear condition

0: TM1 Comparator P match

1: TM1 Comparator A match

This bit is used to select the method which clears the counter. Remember that the

Standard TM contains two comparators, Comparator A and Comparator P, either of which can be selected to clear the internal counter. With the T1CCLR bit set high, the counter will be cleared when a compare match occurs from the Comparator A.

When the bit is low, the counter will be cleared when a compare match occurs from the Comparator P or with a counter overflow. A counter overflow clearing method can only be implemented if the CCRP bits are all cleared to zero. The T1CCLR bit is not used in the PWM, Single Pulse or Input Capture Mode.

• TM1DL Register

Bit

Na�e

R/W

7

D7

R

POR 0

6

D�

R

0

5

D5

R

0

4

D4

R

0

3

D3

R

0

2

D�

R

0

1

D1

R

0

0

D0

R

0

Bit 7~0

TM1DL

: TM1 Counter Low Byte Register bit 7~bit 0

TM1 10-bit Counter bit 7~bit 0

• TM1DH Register

Bit

Na�e

7

R/W

POR

6

5

4

3

Bit 7~2

Bit 1~0

"—": unimplemented, read as "0"

TM1DH

: TM1 Counter High Byte Register bit 1~bit 0

TM1 10-bit Counter bit 9~bit 8

2

1

D9

R

0

0

D8

R

0

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HT68FB540/HT68FB550/HT68FB560

I/O Flash USB MCU with SPI

• TM1AL Register

Bit

Na�e

R/W

POR

7

D7

R/W

0

6

D�

R/W

0

5

D5

R/W

0

4

D4

R/W

0

3

D3

R/W

0

Bit 7~0

TM1AL

: TM1 CCRA Low Byte Register bit 7~bit 0

TM1 10-bit CCRA bit 7~bit 0

• TM1AH Register

Bit 7

Na�e

R/W

POR

6

5

4

3

Bit 7~2

Bit 1~0

"—": unimplemented, read as "0"

T

M1AH

: TM1 CCRA High Byte Register bit 1~bit 0

TM1 10-bit CCRA bit 9~bit 8

2

2

D�

R/W

0

1

D1

R/W

0

1

D9

R/W

0

0

D0

R/W

0

0

D8

R/W

0

Standard Type TM Operating Modes

The Standard Type TM can operate in one of five operating modes, Compare Match Output Mode,

PWM Output Mode, Single Pulse Output Mode, Capture Input Mode or Timer/Counter Mode. The operating mode is selected using the TnM1 and TnM0 bits in the TMnC1 register.

Compare Output Mode

To select this mode, bits TnM1 and TnM0 in the TMnC1 register, should be set to 00 respectively.

In this mode once the counter is enabled and running it can be cleared by three methods. These are a counter overflow, a compare match from Comparator A and a compare match from Comparator P.

When the TnCCLR bit is low, there are two ways in which the counter can be cleared. One is when a compare match from Comparator P, the other is when the CCRP bits are all zero which allows the counter to overflow. Here both TnAF and TnPF interrupt request flags for Comparator A and

Comparator P respectively, will both be generated.

If the TnCCLR bit in the TMnC1 register is high then the counter will be cleared when a compare match occurs from Comparator A. However, here only the TnAF interrupt request flag will be generated even if the value of the CCRP bits is less than that of the CCRA registers. Therefore when

TnCCLR is high no TnPF interrupt request flag will be generated. In the Compare Match Output

Mode, the CCRA can not be set to "0".

As the name of the mode suggests, after a comparison is made, the TM output pin, will change state. The TM output pin condition however only changes state when a TnAF interrupt request flag is generated after a compare match occurs from Comparator A. The TnPF interrupt request flag, generated from a compare match occurs from Comparator P, will have no effect on the TM output pin. The way in which the TM output pin changes state are determined by the condition of the

TnIO1 and TnIO0 bits in the TMnC1 register. The TM output pin can be selected using the TnIO1 and TnIO0 bits to go high, to go low or to toggle from its present condition when a compare match occurs from Comparator A. The initial condition of the TM output pin, which is setup after the

TnON bit changes from low to high, is setup using the TnOC bit. Note that if the TnIO1 and TnIO0 bits are zero then no pin change will take place.

Rev. 1.40

11� De�e��e� 01� �01�

HT68FB540/HT68FB550/HT68FB560

I/O Flash USB MCU with SPI

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I/O Flash USB MCU with SPI

Rev. 1.40

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I/O Flash USB MCU with SPI

TnON

TnPAU

TnPOL

CCRP Int.

Flag TnPF

CCRA Int.

Flag TnAF

Timer/Counter Mode

To select this mode, bits TnM1 and TnM0 in the TMnC1 register should be set to 11 respectively.

The Timer/Counter Mode operates in an identical way to the Compare Match Output Mode generating the same interrupt flags. The exception is that in the Timer/Counter Mode the TM output pin is not used. Therefore the above description and Timing Diagrams for the Compare Match

Output Mode can be used to understand its function. As the TM output pin is not used in this mode, the pin can be used as a normal I/O pin or other pin-shared function.

Counte� Value

0x3FF

Counte� ove�flow

CCRP=0

CCRP > 0

TnCCLR = 0; TnM [1:0] = 00

CCRP > 0

Counte� �lea�ed �y CCRP value

Resu�e

Counte�

Resta�t

CCRP

CCRA

Pause Stop

Ti�e

TM O/P Pin

Output pin set to initial Level Low if TnOC=0

Output Toggle with

TnAF flag

He�e TnIO [1:0] = 11

Toggle Output sele�t

Note TnIO [1:0] = 10

Output not affe�ted �y TnAF flag. Re�ains High until �eset

�y TnON �it

A�tive High Output sele�t

Output Inve�ts when TnPOL is high

Output Pin

Reset to Initial value

Output �ont�olled �y othe� pin-sha�ed fun�tion

Compare Match Output Mode – TnCCLR= 0

Note: 1. With TnCCLR= 0 a Comparator P match will clear the counter

2. The TM output pin is controlled only by the TnAF flag

3. The output pin is reset to its initial state by a TnON bit rising edge

Rev. 1.40 113 De�e��e� 01� �01�

HT68FB540/HT68FB550/HT68FB560

I/O Flash USB MCU with SPI

Counte� Value

0x3FF

CCRA

CCRP

TnCCLR = 1; TnM [1:0] = 00

CCRA > 0 Counte� �lea�ed �y CCRA value

CCRA = 0

Counte� ove�flow

Resu�e

Pause

CCRA=0

Stop Counte� Resta�t

Ti�e

TnON

TnPAU

TnPOL

CCRA Int.

Flag TnAF

CCRP Int.

Flag TnPF

No TnAF flag gene�ated on

CCRA ove�flow

TM O/P Pin

TnPF not gene�ated

Output pin set to initial Level Low if TnOC=0

Output Toggle with

TnAF flag

He�e TnIO [1:0] = 11

Toggle Output sele�t

Output does not �hange

Note TnIO [1:0] = 10

Output not affe�ted �y

TnAF flag. Re�ains High until �eset �y TnON �it

A�tive High Output sele�t

Output Inve�ts when TnPOL is high

Output Pin

Reset to Initial value

Output �ont�olled �y othe� pin-sha�ed fun�tion

Compare Match Output Mode – TnCCLR= 1

Note: 1. With TnCCLR= 1 a Comparator A match will clear the counter

2. The TM output pin is controlled only by the TnAF flag

3. The output pin is reset to its initial state by a TnON bit rising edge

4. A TnPF flag is not generated when TnCCLR= 1

Timer/Counter Mode

To select this mode, bits TnM1 and TnM0 in the TMnC1 register should be set to 11 respectively.

The Timer/Counter Mode operates in an identical way to the Compare Match Output Mode generating the same interrupt flags. The exception is that in the Timer/Counter Mode the TM output pin is not used. Therefore the above description and Timing Diagrams for the Compare Match

Output Mode can be used to understand its function. As the TM output pin is not used in this mode, the pin can be used as a normal I/O pin or other pin-shared function.

PWM Output Mode

To select this mode, bits TnM1 and TnM0 in the TMnC1 register should be set to 10 respectively and also the TnIO1 and TnIO0 bits should be set to 10 respectively. The PWM function within the TM is useful for applications which require functions such as motor control, heating control, illumination control etc. By providing a signal of fixed frequency but of varying duty cycle on the

TM output pin, a square wave AC waveform can be generated with varying equivalent DC RMS values.

Rev. 1.40

114 De�e��e� 01� �01�

HT68FB540/HT68FB550/HT68FB560

I/O Flash USB MCU with SPI

Rev. 1.40 115 De�e��e� 01� �01�

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I/O Flash USB MCU with SPI

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As both the period and duty cycle of the PWM waveform can be controlled, the choice of generated waveform is extremely flexible. In the PWM mode, the TnCCLR bit has no effect as the PWM period. Both of the CCRA and CCRP registers are used to generate the PWM waveform, one register is used to clear the internal counter and thus control the PWM waveform frequency, while the other one is used to control the duty cycle. Which register is used to control either frequency or duty cycle is determined using the TnDPX bit in the TMnC1 register. The PWM waveform frequency and duty cycle can therefore be controlled by the values in the CCRA and CCRP registers.

An interrupt flag, one for each of the CCRA and CCRP, will be generated when a compare match occurs from either Comparator A or Comparator P. The TnOC bit in the TMnC1 register is used to select the required polarity of the PWM waveform while the two TnIO1 and TnIO0 bits are used to enable the PWM output or to force the TM output pin to a fixed high or low level. The TnPOL bit is used to reverse the polarity of the PWM output waveform.

16-bit STM, PWM Mode, Edge-aligned Mode, T0DPX= 0

CCRP 1~255 000b

Pe�iod

Duty

CCRP x �5�

CCRA

�553�

If f

SYS

= 16MHz, TM clock source select f

SYS

/4, CCRP = 2 and CCRA = 128,

The STM PWM output frequency = (f

SYS

/4)/(2x256)= f

SYS

/2048 = 7.8125kHz, duty= 128/512= 25%

If the Duty value defined by the CCRA register is equal to or greater than the Period value, then the

PWM output duty is 100%.

16-bit STM, PWM Mode, Edge-aligned Mode, T0DPX= 1

CCRP 1~255 000b

Pe�iod

Duty CCRP x �5�

CCRA

�553�

The PWM output period is determined by the CCRA register value together with the TM clock while the PWM duty cycle is defined by the (CCRP x 256) except when CCRP value is equal to 000b.

10-bit STM, PWM Mode, Edge-aligned Mode, T1DPX= 0

CCRP

Pe�iod

Duty

001b

1�8

010b

�5�

011b

384

100b

51�

CCRA

101b

�40

110b

7�8

111b

89�

000b

10�4

If f

SYS

= 16MHz, TM clock source select f

SYS

/4, CCRP = 100b and CCRA = 128,

The STM PWM output frequency = (f

SYS

/4)/512 = f

SYS

/2048 = 7.8125kHz, duty = 128/512 = 25%

If the Duty value defined by the CCRA register is equal to or greater than the Period value, then the

PWM output duty is 100%.

10-bit STM, PWM Mode, Edge-aligned Mode, T1DPX= 1

CCRP 001b 010b 011b 100b 101b

Pe�iod

Duty 1�8 �5� 384 51�

CCRA

�40

110b 111b 000b

7�8 89�

10�4

The PWM output period is determined by the CCRA register value together with the TM clock while the PWM duty cycle is defined by the CCRP register value.

Rev. 1.40 115 De�e��e� 01� �01�

HT68FB540/HT68FB550/HT68FB560

I/O Flash USB MCU with SPI

Counte� Value

CCRP

CCRA

Counte� �lea�ed

�y CCRP

Pause Resu�e

TnDPX = 0; TnM [1:0] = 10

Counte� Reset when

TnON �etu�ns high

Counte� Stop if

TnON �it low

TnON

TnPAU

TnPOL

CCRA Int.

Flag TnAF

CCRP Int.

Flag TnPF

TM O/P Pin

(TnOC=1)

TM O/P Pin

(TnOC=0)

PWM Duty Cy�le set �y CCRA

PWM �esu�es ope�ation

Output �ont�olled �y othe� pin-sha�ed fun�tion

Output Inve�ts when TnPOL = 1

PWM Pe�iod set �y CCRP

PWM Mode – TnDPX= 0

Note: 1. Here TnDPX= 0 – Counter cleared by CCRP

2. A counter clear sets the PWM Period

3. The internal PWM function continues running even when TnIO [1:0]= 00 or 01

4. The TnCCLR bit has no influence on PWM operation

Ti�e

HT68FB540/HT68FB550/HT68FB560

I/O Flash USB MCU with SPI

Rev. 1.40

11� De�e��e� 01� �01� Rev. 1.40 117 De�e��e� 01� �01�

HT68FB540/HT68FB550/HT68FB560

I/O Flash USB MCU with SPI

Rev. 1.40

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I/O Flash USB MCU with SPI

Counte� Value

Counte� �lea�ed

�y CCRA

TnDPX = 1; TnM [1:0] = 10

CCRA

CCRP

Pause Resu�e

Counte� Stop if

TnON �it low

Ti�e

TnON

TnPAU

TnPOL

CCRP Int.

Flag TnPF

CCRA Int.

Flag TnAF

TM O/P Pin

(TnOC=1)

TM O/P Pin

(TnOC=0)

PWM Duty Cy�le set �y CCRP

PWM �esu�es ope�ation

Output �ont�olled �y othe� pin-sha�ed fun�tion

Output Inve�ts when TnPOL = 1

PWM Pe�iod set �y CCRA

PWM Mode – TnDPX= 1

Note: 1. Here TnDPX= 1 – Counter cleared by CCRA

2. A counter clear sets the PWM Period

3. The internal PWM function continues even when TnIO [1:0]= 00 or 01

4. The TnCCLR bit has no influence on PWM operation

Single Pulse Mode

To select this mode, bits TnM1 and TnM0 in the TMnC1 register should be set to 10 respectively and also the TnIO1 and TnIO0 bits should be set to 11 respectively. The Single Pulse Output Mode, as the name suggests, will generate a single shot pulse on the TM output pin.

The trigger for the pulse output leading edge is a low to high transition of the TnON bit, which can be implemented using the application program. However in the Single Pulse Mode, the TnON bit can also be made to automatically change from low to high using the external TCKn pin, which will in turn initiate the Single Pulse output. When the TnON bit transitions to a high level, the counter will start running and the pulse leading edge will be generated. The TnON bit should remain high when the pulse is in its active state. The generated pulse trailing edge will be generated when the

TnON bit is cleared to zero, which can be implemented using the application program or when a compare match occurs from Comparator A.

However a compare match from Comparator A will also automatically clear the TnON bit and thus generate the Single Pulse output trailing edge. In this way the CCRA value can be used to control

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I/O Flash USB MCU with SPI

the pulse width. A compare match from Comparator A will also generate a TM interrupt. The counter can only be reset back to zero when the TnON bit changes from low to high when the counter restarts. In the Single Pulse Mode CCRP is not used. The TnCCLR and TnDPX bits are not used in this Mode.



 

  

      

Single Pulse Generation

Counte� Value

CCRA

CCRP

Counte� stopped

�y CCRA

Pause

Resu�e

TnM [1:0] = 10 ; TnIO [1:0] = 11

Counte� Stops

�y softwa�e

TnON

TCKn pin

TnPAU

TnPOL

CCRP Int.

Flag TnPF

CCRA Int.

Flag TnAF

Softwa�e

T�igge�

Clea�ed �y

CCRA �at�h

No CCRP Inte��upts gene�ated

Auto. set �y

TCKn pin

Softwa�e

T�igge�

TCKn pin

T�igge�

Softwa�e

T�igge�

Softwa�e

Clea�

Softwa�e

T�igge�

TM O/P Pin

(TnOC=1)

TM O/P Pin

(TnOC=0)

Pulse Width set �y CCRA

Output Inve�ts when TnPOL = 1

Single Pulse Mode

Note: 1. Counter stopped by CCRA

2. CCRP is not used

3. The pulse is triggered by the TCKn pin or by setting the TnON bit high

4. A TCKn pin active edge will automatically set the TnON bit hight

5. In the Single Pulse Mode, TnIO [1:0] must be set to "11" and can not be changed.

Ti�e

Rev. 1.40

118 De�e��e� 01� �01�

HT68FB540/HT68FB550/HT68FB560

I/O Flash USB MCU with SPI

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I/O Flash USB MCU with SPI

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I/O Flash USB MCU with SPI

Capture Input Mode

To select this mode bits TnM1 and TnM0 in the TMnC1 register should be set to 01 respectively.

This mode enables external signals to capture and store the present value of the internal counter and can therefore be used for applications such as pulse width measurements. The external signal is supplied on the TPn_0 or TPn_1 pin, whose active edge can be either a rising edge, a falling edge or both rising and falling edges; the active edge transition type is selected using the TnIO1 and TnIO0 bits in the TMnC1 register. The counter is started when the TnON bit changes from low to high which is initiated using the application program.

When the required edge transition appears on the TPn_0 or TPn_1 pin the present value in the counter will be latched into the CCRA registers and a TM interrupt generated. Irrespective of what events occur on the TPn_0 or TPn_1 pin the counter will continue to free run until the TnON bit changes from high to low. When a CCRP compare match occurs the counter will reset back to zero; in this way the CCRP value can be used to control the maximum counter value. When a CCRP compare match occurs from Comparator P, a TM interrupt will also be generated. Counting the number of overflow interrupt signals from the CCRP can be a useful method in measuring long pulse widths. The TnIO1 and TnIO0 bits can select the active trigger edge on the TPn_0 or TPn_1 pin to be a rising edge, falling edge or both edge types. If the TnIO1 and TnIO0 bits are both set high, then no capture operation will take place irrespective of what happens on the TPn_0 or TPn_1 pin, however it must be noted that the counter will continue to run.

As the TPn_0 or TPn_1 pin is pin shared with other functions, care must be taken if the TM is in the

Input Capture Mode. This is because if the pin is setup as an output, then any transitions on this pin may cause an input capture operation to be executed. The TnCCLR and TnDPX bits are not used in this Mode.

Rev. 1.40

118 De�e��e� 01� �01� Rev. 1.40 119 De�e��e� 01� �01�

HT68FB540/HT68FB550/HT68FB560

I/O Flash USB MCU with SPI

Counte� Value

Counte� �lea�ed

�y CCRP

TnM [1:0] = 01

CCRP

YY

XX

Pause

Resu�e

Ti�e

TnON

TnPAU

TM �aptu�e pin TPn_x

A�tive edge

CCRA Int.

Flag TnAF

CCRP Int.

Flag TnPF

A�tive edge

A�tive edge

CCRA

Value

TnIO [1:0]

Value

00

Rising edge

XX YY XX

01

Falling edge 10

Both edges

YY

11

Disa�le Captu�e

Capture Input Mode

Note: 1. TnM [1:0] = 01 and active edge set by the TnIO [1:0] bits

2. A TM Capture input pin active edge transfers the counter value to CCRA

3. TnCCLR bit not used

4. No output function – TnOC and TnPOL bits are not used

5. CCRP determines the counter value and the counter has a maximum count value when CCRP is equal to zero.

HT68FB540/HT68FB550/HT68FB560

I/O Flash USB MCU with SPI

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I/O Flash USB MCU with SPI

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I/O Flash USB MCU with SPI

Serial Interface Module – SIM

The devices contain a Serial Interface Module, which includes both the four line SPI interface and the two line I

2

C interface types, to allow an easy method of communication with external peripheral hardware. Having relatively simple communication protocols, these serial interface types allow the microcontroller to interface to external SPI or I

2

C based hardware such as sensors, Flash or

EEPROM memory, etc. The SIM interface pins are pin-shared with other I/O pins therefore the SIM interface function must first be selected by software control. As both interface types share the same pins and registers, the choice of whether the SPI or I

2

C type is used is made using the SIM operating mode control bits, named SIM2~SIM0, in the SIMC0 register. These pull-high resistors of the SIM pin-shared I/O are selected using pull-high control registers, and also if the SIM function is enabled.

There is one control register associated with the serial interface control, namely SBSC. This is used to enable the SIM_WCOL bit function, SA_WCOL bit function and I

2

C debounce selection.

The devices provide two kinds of SPI function, namely SPI and SPIA, each of them has the corresponding WCOL control bits to enable the SIM WCOL and SPIA WCOL control bits, namely

SIM_WCOL and SA_WCOL respectively. In addition, the I2CDB1 and I2CDB0 bits are used to select the I

2

C debounce time.

SPI Interface

This SPI interface function, which is part of the Serial Interface Module, should not be confused with the other independent SPI function, known as SPIA, which is described in another section of this datasheet.

The SPI interface is often used to communicate with external peripheral devices such as sensors,

Flash or EEPROM memory devices etc. Originally developed by Motorola, the four line SPI interface is a synchronous serial data interface that has a relatively simple communication protocol simplifying the programming requirements when communicating with external hardware devices.

The communication is full duplex and operates as a slave/master type, where the device can be either master or slave. Although the SPI interface specification can control multiple slave devices from a single master, but this device provided only one SCS pin. If the master needs to control multiple slave devices from a single master, the master can use I/O pin to select the slave devices.

SPI Interface Operation

The SPI interface is a full duplex synchronous serial data link. It is a four line interface with pin names SDI, SDO, SCK and SCS . Pins SDI and SDO are the Serial Data Input and Serial Data Output lines, SCK is the Serial Clock line and SCS is the Slave Select line. As the SPI interface pins are pinshared with other functions and with the I

2

C function pins, the SPI interface must first be selected by the correct bits in the SIMC0 and SIMC2 registers. After the SPI option has been selected, it can also be additionally disabled or enabled using the SIMEN bit in the SIMC0 register.

SPI Master/Slave Connection

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HT68FB540/HT68FB550/HT68FB560

I/O Flash USB MCU with SPI

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SPI Block Diagram

The SPI function in these devices offer the following features:

• Full duplex synchronous data transfer

• Both Master and Slave modes

• LSB first or MSB first data transmission modes

• Transmission complete flag

• Rising or falling active clock edge

• WCOL bit enabled or disable select

The status of the SPI interface pins is determined by a number of factors such as whether the device is in the master or slave mode and upon the condition of certain control bits such as CSEN and

SIMEN.

SPI Registers

There are four internal registers which control the overall operation of the SPI interface. These are the SIMD data register and three registers SIMC0, SIMC2 and SBSC. Note that the SIMC1 register is only used by the I

2

C interface.

Register

Name

SIMC0

SIMD

SIMC�

SBSC

7

SIM�

D7

D7

SIM_WCOL

6

SIM1

D�

D�

5

SIM0

D5

CKPOLB

I�CDB1

Bit

4

PCKEN

D4

CKEG

I�CDB0

3 2 1

PCKP1 PCKP0 SIMEN

D3

MLS

D�

CSEN

D1

WCOL

0

D0

TRF

SA_WCOL

SIM Registers List

The SIMD register is used to store the data being transmitted and received. The same register is used by both the SPI and I

2

C functions. Before the device writes data to the SPI bus, the actual data to be transmitted must be placed in the SIMD register. After the data is received from the SPI bus, the device can read it from the SIMD register. Any transmission or reception of data from the SPI bus must be made via the SIMD register.

The SIM_WCOL bit in the SBSC register is used to control the SPI WCOL function.

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I/O Flash USB MCU with SPI

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I/O Flash USB MCU with SPI

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I/O Flash USB MCU with SPI

SIMD Register

Bit

Na�e

R/W

POR

7

D7

R/W x

6

D�

R/W x

5

D5

R/W x

4

D4

R/W x

3

D3

R/W x

2

D�

R/W x

1

D1

R/W x

0

D0

R/W x

"x" unknown

There are also three control registers for the SPI interface, SIMC0 SIMC2 and SBSC. Note that the

SIMC2 register also has the name SIMA which is used by the I

2

C function. The SIMC1 register is not used by the SPI function, only by the I

2

C function. Register SIMC0 is used to control the enable/ disable function and to set the data transmission clock frequency. Although not connected with the

SPI function, the SIMC0 register is also used to control the Peripheral Clock Prescaler. Register

SIMC2 is used for other control functions such as LSB/MSB selection, write collision flag etc.

SIMC0 Register

Bit

Na�e

R/W

7

SIM�

R/W

POR 1

Bit 7~5

Bit 4

Bit 3~2

6

SIM1

R/W

1

5

SIM0

R/W

1

4

PCKEN

R/W

0

3

PCKP1

R/W

0

2

PCKP0

R/W

0

1

SIMEN

R/W

0

0

R

0

SIM2, SIM1, SIM0

: SIM Operating Mode Control

000: SPI master mode; SPI clock is f

SYS

/4

001: SPI master mode; SPI clock is f

SYS

/16

010: SPI master mode; SPI clock is f

SYS

/64

011: SPI master mode; SPI clock is f

L

100: SPI master mode; SPI clock is TM0 CCRP match frequency/2

101: SPI slave mode

110: I

2

C slave mode

111: Non SIM function

These bits setup the overall operating mode of the SIM function. As well as selecting if the I

2

C or SPI function, they are used to control the SPI Master/Slave selection and the SPI Master clock frequency. The SPI clock is a function of the system clock but can also be chosen to be sourced from f

L

or TM0. If the SPI Slave Mode is selected then the clock will be supplied by an external Master device.

PCKEN

: PCK Output Pin Control

0: disable

1: enable

PCKP1, PCKP0

: Select PCK output pin frequency

00: f

SYS

01: f

SYS

/4

10: f

SYS

/8

11: TM0 CCRP match frequency/2

Rev. 1.40 1�3 De�e��e� 01� �01�

Rev. 1.40

HT68FB540/HT68FB550/HT68FB560

I/O Flash USB MCU with SPI

Bit 1

Bit 0

SIMEN

: SIM Control

0: disable

1: enable

The bit is the overall on/off control for the SIM interface. When the SIMEN bit is cleared to zero to disable the SIM interface, the SDI, SDO, SCK and SCS, or SDA and SCL lines will lose their SPI or I

2

C function and the SIM operating current will be reduced to a minimum value. When the bit is high the SIM interface is enabled. If the

SIM is configured to operate as an SPI interface via the SIM2~SIM0 bits, the contents of the SPI control registers will remain at the previous settings when the SIMEN bit changes from low to high and should therefore be first initialised by the application program. If the SIM is configured to operate as an I

2

C interface via the SIM2~SIM0 bits and the SIMEN bit changes from low to high, the contents of the I

2

C control bits such as HTX and TXAK will remain at the previous settings and should therefore be first initialised by the application program while the relevant I

2

C flags such as HCF,

HAAS, HBB, SRW and RXAK will be set to their default states.

"—": unimplemented, read as "0"

SIMC2 Register

Bit

Na�e

R/W

POR

7

D7

R/W

0

Bit 7~6

Bit 5

Bit 4

Bit 3

6

D�

R/W

0

5

CKPOLB

R/W

0

4

CKEG

R/W

0

3

MLS

R/W

0

2

CSEN

R/W

0

1

WCOL

R/W

0

0

TRF

R/W

0

Undefined bit

This bit can be read or written by the application program.

CKPOLB

: Determines the base condition of the clock line

0: the SCK line will be high when the clock is inactive

1: the SCK line will be low when the clock is inactive

The CKPOLB bit determines the base condition of the clock line, if the bit is high, then the SCK line will be low when the clock is inactive. When the CKPOLB bit is low, then the SCK line will be high when the clock is inactive.

CKEG

: Determines SPI SCK active clock edge type

CKPOLB=0

0: SCK is high base level and data capture at SCK rising edge

1: SCK is high base level and data capture at SCK falling edge

CKPOLB=1

0: SCK is low base level and data capture at SCK falling edge

1: SCK is low base level and data capture at SCK rising edge

The CKEG and CKPOLB bits are used to setup the way that the clock signal outputs and inputs data on the SPI bus. These two bits must be configured before data transfer is executed otherwise an erroneous clock edge may be generated. The CKPOLB bit determines the base condition of the clock line, if the bit is high, then the SCK line will be low when the clock is inactive. When the CKPOLB bit is low, then the SCK line will be high when the clock is inactive. The CKEG bit determines active clock edge type which depends upon the condition of CKPOLB bit.

MLS

: SPI Data shift order

0: LSB

1: MSB

This is the data shift select bit and is used to select how the data is transferred, either

MSB or LSB first. Setting the bit high will select MSB first and low for LSB first.

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I/O Flash USB MCU with SPI

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I/O Flash USB MCU with SPI

Rev. 1.40

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HT68FB540/HT68FB550/HT68FB560

I/O Flash USB MCU with SPI

Bit 2

Bit 1

Bit 0

CSEN

: SPI SCS pin Control

0: disable

1: enable

The CSEN bit is used as an enable/disable for the SCS pin. If this bit is low, then the

SCS pin will be disabled and placed into I/O pin or the other functions. If the bit is high the SCS pin will be enabled and used as a select pin.

WCOL

: SPI Write Collision flag

0: No collision

1: Collision

The WCOL flag is used to detect if a data collision has occurred. If this bit is high it means that data has been attempted to be written to the SIMD register during a data transfer operation. This writing operation will be ignored if data is being transferred.

The bit can be cleared by the application program. Note that using the WCOL bit can be disabled or enabled via the SIM_WCOL bit in the SBSC register.

TRF

: SPI Transmit/Receive Complete flag

0: Data is being transferred

1: SPI data transmission is completed

The TRF bit is the Transmit/Receive Complete flag and is set "1" automatically when an SPI data transmission is completed, but must set to "0" by the application program.

It can be used to generate an interrupt.

SBSC Register

Bit

Na�e

R/W

POR

Bit 7

Bit 6

Bit 5~4

Bit 3~1

Bit 0

7

SIM_WCOL

R/W

0

6

5 4

I�CDB1 I�CDB0

R/W

0

R/W

0

SIM_WCOL

: SIM WCOL control bit

0: disable

1: enable

"—": unimplemented, read as "0"

I2CDB1, I2CDB0

: I

2

C debounce selection bits

Related to I

2

C function, described elsewhere

"—": unimplemented, read as "0"

SA_WCOL

: SPIA WCOL function control

Related to SPIA function, described elsewhere

3

2

1

0

SA_WCOL

R/W

0

SPI Communication

After the SPI interface is enabled by setting the SIMEN bit high, then in the Master Mode, when data is written to the SIMD register, transmission/reception will begin simultaneously. When the data transfer is complete, the TRF flag will be set automatically, but must be cleared using the application program. In the Slave Mode, when the clock signal from the master has been received, any data in the SIMD register will be transmitted and any data on the SDI pin will be shifted into the SIMD register. The master should output an SCS signal to enable the slave device before a clock signal is provided. The slave data to be transferred should be well prepared at the appropriate moment relative to the SCS signal depending upon the configurations of the CKPOLB bit and CKEG bit. The accompanying timing diagram shows the relationship between the slave data and SCS signal for various configurations of the CKPOLB and CKEG bits.

The SPI will continue to function even in the IDLE Mode.

Rev. 1.40 1�5 De�e��e� 01� �01�

Rev. 1.40

HT68FB540/HT68FB550/HT68FB560

I/O Flash USB MCU with SPI

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SPI Master Mode Timing



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SPI Slave Mode Timing – CKEG=0



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SPI Slave Mode Timing – CKEG=1

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I/O Flash USB MCU with SPI

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I/O Flash USB MCU with SPI

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I/O Flash USB MCU with SPI

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SPI Transfer Control Flowchart

SPI Bus Enable/Disable

To enable the SPI bus, set CSEN= 1 and SCS = 0, then wait for data to be written into the SIMD

(TXRX buffer) register. For the Master Mode, after data has been written to the SIMD (TXRX buffer) register, then transmission or reception will start automatically. When all the data has been transferred, the TRF bit should be set. For the Slave Mode, when clock pulses are received on SCK, data in the TXRX buffer will be shifted out or data on SDI will be shifted in.To disable the SPI bus, the SCK, SDI, SDO and SCS will become I/O pins or the other functions.

Rev. 1.40 1�7 De�e��e� 01� �01�

HT68FB540/HT68FB550/HT68FB560

I/O Flash USB MCU with SPI

SPI Operation

All communication is carried out using the 4-line interface for either Master or Slave Mode.The

CSEN bit in the SIMC2 register controls the overall function of the SPI interface. Setting this bit high will enable the SPI interface by allowing the SCS line to be active, which can then be used to control the SPI interface. If the CSEN bit is low, the SPI interface will be disabled and the SCS line will be an I/O pin or the other functions and can therefore not be used for control of the SPI interface. If the CSEN bit and the SIMEN bit in the SIMC0 are set high, this will place the SDI line in a floating condition and the SDO line high. If in Master Mode the SCK line will be either high or low depending upon the clock polarity selection bit CKPOLB in the SIMC2 register. If in Slave

Mode the SCK line will be in a floating condition. If the SIMEN bit is low, then the bus will be disabled and SCS , SDI, SDO and SCK will all become I/O pins or the other functions. In the Master

Mode the Master will always generate the clock signal. The clock and data transmission will be initiated after data has been written into the SIMD register. In the Slave Mode, the clock signal will be received from an external master device for both data transmission and reception. The following sequences show the order to be followed for data transfer in both Master and Slave Mode:

Master Mode

• Step 1

Select the SPI Master mode and clock source using the SIM2~SIM0 bits in the SIMC0 control register

• Step 2

Setup the CSEN bit and setup the MLS bit to choose if the data is MSB or LSB first, this setting must be the same with the Slave device.

• Step 3

Setup the SIMEN bit in the SIMC0 control register to enable the SPI interface.

• Step 4

For write operations: write the data to the SIMD register, which will actually place the data into the TXRX buffer. Then use the SCK and SCS lines to output the data. After this, go to step5.

For read operations: the data transferred in on the SDI line will be stored in the TXRX buffer until all the data has been received at which point it will be latched into the SIMD register.

• Step 5

Check the WCOL bit if set high then a collision error has occurred so return to step 4. If equal to zero then go to the following step.

• Step 6

Check the TRF bit or wait for a SPI serial bus interrupt.

• Step 7

Read data from the SIMD register.

• Step 8

Clear TRF.

• Step 9

Go to step 4.

Rev. 1.40

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HT68FB540/HT68FB550/HT68FB560

I/O Flash USB MCU with SPI

Rev. 1.40 1�9 De�e��e� 01� �01�

HT68FB540/HT68FB550/HT68FB560

I/O Flash USB MCU with SPI

Rev. 1.40

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HT68FB540/HT68FB550/HT68FB560

I/O Flash USB MCU with SPI

Slave Mode

• Step 1

Select the SPI Slave mode using the SIM2~SIM0 bits in the SIMC0 control register

• Step 2

Setup the CSEN bit and setup the MLS bit to choose if the data is MSB or LSB first, this setting must be the same with the Master device.

• Step 3

Setup the SIMEN bit in the SIMC0 control register to enable the SPI interface.

• Step 4

For write operations: write the data to the SIMD register, which will actually place the data into the TXRX buffer. Then wait for the master clock SCK and SCS signal. After this, go to step5.

For read operations: the data transferred in on the SDI line will be stored in the TXRX buffer until all the data has been received at which point it will be latched into the SIMD register.

• Step 5

Check the WCOL bit if set high then a collision error has occurred so return to step 4. If equal to zero then go to the following step.

• Step 6

Check the TRF bit or wait for a SPI serial bus interrupt.

• Step 7

Read data from the SIMD register.

• Step 8

Clear TRF.

• Step 9

Go to step 4.

Error Detection

The WCOL bit in the SIMC2 register is provided to indicate errors during data transfer. The bit is set by the SPI serial Interface but must be cleared by the application program. This bit indicates a data collision has occurred which happens if a write to the SIMD register takes place during a data transfer operation and will prevent the write operation from continuing. The overall function of the

WCOL bit can be disabled or enabled by the SIM_WCOL bit in the SBSC register. .

I

2

C Interface

The I

2

C interface is used to communicate with external peripheral devices such as sensors,

EEPROM memory etc. Originally developed by Philips, it is a two line low speed serial interface for synchronous serial data transfer. The advantage of only two lines for communication, relatively simple communication protocol and the ability to accommodate multiple devices on the same bus has made it an extremely popular interface type for many applications.

I

2

C Master Slave Bus Connection

Rev. 1.40 1�9 De�e��e� 01� �01�

Rev. 1.40

HT68FB540/HT68FB550/HT68FB560

I/O Flash USB MCU with SPI

I

2

C Interface Operation

The I

2

C serial interface is a two line interface, a serial data line, SDA, and serial clock line, SCL. As many devices may be connected together on the same bus, their outputs are both open drain types.

For this reason it is necessary that external pull-high resistors are connected to these outputs. Note that no chip select line exists, as each device on the I 2 C bus is identified by a unique address which will be transmitted and received on the I

2

C bus.

When two devices communicate with each other on the bidirectional I

2

C bus, one is known as the master device and one as the slave device. Both master and slave can transmit and receive data, however, it is the master device that has overall control of the bus. For these devices, which only operate in slave mode, there are two methods of transferring data on the I

2

C bus, the slave transmit mode and the slave receive mode.

The debounce time of the I

2

C interface can be determined by the I2CDB1 and I2CDB0 bits in the

SBSC register. This uses the internal clock to in effect add a debounce time to the external clock to reduce the possibility of glitches on the clock line causing erroneous operation. The debounce time, if selected, can be chosen to be either 1 or 2 system clocks.

S T A R T s i g n a l f r o m M a s t e r

S e n d s l a v e a d d r e s s a n d R / W b i t f r o m M a s t e r

A c k n o w l e d g e f r o m s l a v e

S e n d d a t a b y t e f r o m M a s t e r

A c k n o w l e d g e f r o m s l a v e

S T O P s i g n a l f r o m M a s t e r

I

2

C Registers

There are three control registers associated with the I

2

C bus, SIMC0, SIMC1 and SBSC, one address register SIMA and one data register, SIMD. The SIMD register, which is shown in the above SPI section, is used to store the data being transmitted and received on the I

2

C bus. Before the microcontroller writes data to the I

2

C bus, the actual data to be transmitted must be placed in the

SIMD register. After the data is received from the I

2

C bus, the microcontroller can read it from the

SIMD register. Any transmission or reception of data from the I

2

C bus must be made via the SIMD register.

Note that the SIMA register also has the name SIMC2 which is used by the SPI function. Bit SIMEN and bits SIM2~SIM0 in register SIMC0 are used by the I

2

C interface. The I2CDB0 and I2CDB1 in the

SBSC register are used to select the I

2

C debounce time.

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HT68FB540/HT68FB550/HT68FB560

I/O Flash USB MCU with SPI

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HT68FB540/HT68FB550/HT68FB560

I/O Flash USB MCU with SPI

Rev. 1.40

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HT68FB540/HT68FB550/HT68FB560

I/O Flash USB MCU with SPI

Rev. 1.40

Register

Name

SIMC0

SIMC1

SIMD

SIMA

SBSC

7

SIM�

HCF

D7

IICA�

SIM_WCOL

6

SIM1

HAAS

D�

IICA5

5

SIM0

4

PCKEN

Bit

3

PCKP1

HBB

D5

HTX

D4

IICA4 IICA3

I�CDB1 I�CDB0

TXAK

D3

IICA�

I

2

C Registers List

2

PCKP0

SRW

D�

IICA1

1

SIMEN

IAMWU

D1

IICA0

0

RXAK

D0

D0

SA_WCOL

• SIMC0 Register

Bit 7

Na�e

R/W

POR

SIM�

R/W

1

Bit 7~5

Bit 4

Bit 3~2

Bit 1

Bit 0

6

SIM1

R/W

1

5

SIM0

R/W

1

4

PCKEN

R/W

0

3

PCKP1

R/W

0

2

PCKP0

R/W

0

1

SIMEN

R/W

0

R

0

0

SIM2, SIM1, SIM0

: SIM Operating Mode Control

000: SPI master mode; SPI clock is f

SYS

/4

001: SPI master mode; SPI clock is f

SYS

/16

010: SPI master mode; SPI clock is f

011: SPI master mode; SPI clock is f

L

SYS

/64

100: SPI master mode; SPI clock is TM0 CCRP match frequency/2

101: SPI slave mode

110: I

2

C slave mode

111: Non SIM function

These bits setup the overall operating mode of the SIM function. As well as selecting if the I

2

C or SPI function, they are used to control the SPI Master/Slave selection and the SPI Master clock frequency. The SPI clock is a function of the system clock but can also be chosen to be sourced from the f

L

or TM0. If the SPI Slave Mode is selected then the clock will be supplied by an external Master device.

PCKEN

: PCK Output Pin Control

0: disable

1: enable

PCKP1, PCKP0

: Select PCK output pin frequency

00: f

SYS

01: f

SYS

/4

10: f

SYS

/8

11: TM0 CCRP match frequency/2

SIMEN

: SIM Control

0: disable

1: enable

The bit is the overall on/off control for the SIM interface. When the SIMEN bit is cleared to zero to disable the SIM interface, the SDI, SDO, SCK and SCS, or SDA and SCL lines will be in a floating condition and the SIM operating current will be reduced to a minimum value. When the bit is high the SIM interface is enabled. If the

SIM is configured to operate as an SPI interface via SIM2~SIM0 bits, the contents of the SPI control registers will remain at the previous settings when the SIMEN bit changes from low to high and should therefore be first initialised by the application program. If the SIM is configured to operate as an I

2

C interface via the SIM2~SIM0 bits and the SIMEN bit changes from low to high, the contents of the I

2

C control bits such as HTXand TXAK will remain at the previous settings and should therefore be first initialised by the application program while the relevant I

2

C flags such as HCF,

HAAS, HBB, SRW and RXAK will be set to their default states.

"—": unimplemented, read as "0".

131 De�e��e� 01� �01�

Rev. 1.40

HT68FB540/HT68FB550/HT68FB560

I/O Flash USB MCU with SPI

• SIMC1 Register

Bit

Na�e

7

HCF

R/W

POR

R

1

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

6

HAAS

R

0

5

HBB

R

0

4

HTX

R/W

0

3

TXAK

R/W

0

2

SRW

R

0

1

IAMWU

R/W

0

0

RXAK

R

1

HCF

: I

2

C Bus data transfer completion flag

0: Data is being transferred

1: Completion of an 8-bit data transfer

The HCF flag is the data transfer flag. This flag will be zero when data is being transferred. Upon completion of an 8-bit data transfer the flag will go high and an interrupt will be generated.

HAAS

: I

2

C Bus address match flag

0: Not address match

1: Address match

The HASS flag is the address match flag. This flag is used to determine if the slave device address is the same as the master transmit address. If the addresses match then this bit will be high, if there is no match then the flag will be low.

HBB

: I

2

C Bus busy flag

0: I

2

C Bus is not busy

1: I

2

C Bus is busy

The HBB flag is the I

2

C busy flag. This flag will be "1" when the I

2

C bus is busy which will occur when a START signal is detected. The flag will be set to "0" when the bus is free which will occur when a STOP signal is detected.

HTX

: Select I

2

C slave device is transmitter or receiver

0: Slave device is the receiver

1: Slave device is the transmitter

TXAK

: I

2

C Bus transmit acknowledge flag

0: Slave send acknowledge flag

1: Slave do not send acknowledge flag

The TXAK bit is the transmit acknowledge flag. After the slave device receipt of 8-bits of data,this bit will be transmitted to the bus on the 9th clock from the slave device.

The slave device must always set TXAK bit to "0" before further data is received.

SRW

: I

2

C Slave Read/Write flag

0: Slave device should be in receive mode

1: Slave device should be in transmit mode

The SRW flag is the I

2

C Slave Read/Write flag. This flag determines whether the master device wishes to transmit or receive data from the I

2

C bus. When the transmitted address and slave address is match, that is when the HAAS flag is set high, the slave device will check the SRW flag to determine whether it should be in transmit mode or receive mode. If the SRW flag is high, the master is requesting to read data from the bus, so the slave device should be in transmit mode. When the SRW flag is zero, the master will write data to the bus, therefore the slave device should be in receive mode to read this data.

IAMWU

: I

2

C Address Match Wake-up Control

0: disable

1: enable

This bit should be set to "1" to enable I

2

C address match wake up from SLEEP or

IDLE Mode.

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I/O Flash USB MCU with SPI

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I/O Flash USB MCU with SPI

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Bit 0

RXAK

: I

2

C Bus Receive acknowledge flag

0: Slave receive acknowledge flag

1: Slave does not receive acknowledge flag

The RXAK flag is the receiver acknowledge flag. When the RXAK flag is "0", it means that a acknowledge signal has been received at the 9th clock, after 8 bits of data have been transmitted. When the slave device in the transmit mode, the slave device checks the RXAK flag to determine if the master receiver wishes to receive the next byte. The slave transmitter will therefore continue sending out data until the RXAK flag is "1". When this occurs, the slave transmitter will release the SDA line to allow the master to send a STOP signal to release the I

2

C Bus.

The SIMD register is used to store the data being transmitted and received. The same register is used by both the SPI and I

2

C functions. Before the device writes data to the

SPI bus, the actual data to be transmitted must be placed in the SIMD register. After the data is received from the SPI bus, the device can read it from the SIMD register.

Any transmission or reception of data from the SPI bus must be made via the SIMD register.

• SIMD Register

Bit 7

Na�e

R/W

POR

D7

R/W x

6

D�

R/W x

5

D5

R/W x

4

D4

R/W x

3

D3

R/W x

2

D�

R/W x

1

D1

R/W x

0

D0

R/W x

"x" unknown

• SIMA Register

Bit 7

Na�e

R/W

POR

IICA�

R/W x

Bit 7~1

Bit 0

6

IICA5

R/W x

5

IICA4

R/W x

4

IICA3

R/W x

3

IICA�

R/W x

2

IICA1

R/W x

1

IICA0

R/W x

0

R/W

0

"x" unknown

IICA6~ IICA0

: I

2

C slave address

IICA6~ IICA0 is the I

2

C slave address bit 6~bit 0.

The SIMA register is also used by the SPI interface but has the name SIMC2. The

SIMA register is the location where the 7-bit slave address of the slave device is stored. Bits 7~1 of the SIMA register define the device slave address. Bit 0 is not defined.

When a master device, which is connected to the I

2

C bus, sends out an address, which matches the slave address in the SIMA register, the slave device will be selected. Note that the SIMA register is the same register address as SIMC2 which is used by the SPI interface.

Undefined bit

This bit can be read or written by user software program.

• SBSC Register

Bit

Na�e

7

SIM_WCOL

R/W

POR

R/W

0

Bit 7

Bit 6

6

5 4

I�CDB1 I�CDB0

R/W

0

R/W

0

SIM_WCOL

: SIM WCOL control bit

Related to SPI, described elsewhere.

"—": unimplemented, read as "0"

3

2

1

0

SA_WCOL

R/W

0

133 De�e��e� 01� �01�

HT68FB540/HT68FB550/HT68FB560

I/O Flash USB MCU with SPI

Bit 5~4

Bit 3~1

Bit 0

I2CDB1, I2CDB0

: I

2

C debounce selection bits

00: No debounce (default)

01: 1 system clock debounce

10, 11: 2 system clocks debounce

"—": unimplemented, read as "0"

SA_WCOL

: SPIA WCOL function control

Related to SPIA, described elsewhere.

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I

2

C Block Diagram

I

2

C Bus Communication

Communication on the I

2

C bus requires four separate steps, a START signal, a slave device address transmission, a data transmission and finally a STOP signal. When a START signal is placed on the I

2

C bus, all devices on the bus will receive this signal and be notified of the imminent arrival of data on the bus. The first seven bits of the data will be the slave address with the first bit being the

MSB. If the address of the slave device matches that of the transmitted address, the HAAS bit in the

SIMC1 register will be set and an I

2

C interrupt will be generated. After entering the interrupt service routine, the slave device must first check the condition of the HAAS bit to determine whether the interrupt source originates from an address match or from the completion of an 8-bit data transfer.

During a data transfer, note that after the 7-bit slave address has been transmitted, the following bit, which is the 8th bit, is the read/write bit whose value will be placed in the SRW bit. This bit will be checked by the slave device to determine whether to go into transmit or receive mode. Before any transfer of data to or from the I

2

C bus, the microcontroller must initialise the bus, the following are steps to achieve this:

• Step 1

Set the SIM2~SIM0 and SIMEN bits in the SIMC0 register to "1" to enable the I

2

C bus.

• Step 2

Write the slave address of the device to the I

2

C bus address register SIMA

.

• Step 3

Set the SIME interrupt enable bit of the interrupt control register to enable the SIM interrupt.

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HT68FB540/HT68FB550/HT68FB560

I/O Flash USB MCU with SPI

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I/O Flash USB MCU with SPI

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I/O Flash USB MCU with SPI

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I

2

C Bus Initialisation Flow Chart

I

2

C Bus Start Signal

The START signal can only be generated by the master device connected to the I

2

C bus and not by the slave device. This START signal will be detected by all devices connected to the I

2

C bus. When detected, this indicates that the I

2

C bus is busy and therefore the HBB bit will be set. A START condition occurs when a high to low transition on the SDA line takes place when the SCL line remains high.

I

2

C Bus Slave Address

The transmission of a START signal by the master will be detected by all devices on the I

2

C bus.

To determine which slave device the master wishes to communicate with, the address of the slave device will be sent out immediately following the START signal. All slave devices, after receiving this 7-bit address data, will compare it with their own 7-bit slave address. If the address sent out by the master matches the internal address of the microcontroller slave device, then an internal I

2

C bus interrupt signal will be generated. The next bit following the address, which is the 8th bit, defines the read/write status and will be saved to the SRW bit of the SIMC1 register. The slave device will then transmit an acknowledge bit, which is a low level, as the 9th bit. The slave device will also set the status flag HAAS when the addresses match.

As an I

2

C bus interrupt can come from two sources, when the program enters the interrupt subroutine, the HAAS bit should be examined to see whether the interrupt source has come from a matching slave address or from the completion of a data byte transfer. When a slave address is matched, the device must be placed in either the transmit mode and then write data to the SIMD register, or in the receive mode where it must implement a dummy read from the SIMD register to release the SCL line.

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I/O Flash USB MCU with SPI

I

2

C Bus Read/Write Signal

The SRW bit in the SIMC1 register defines whether the slave device wishes to read data from the

I

2

C bus or write data to the I

2

C bus. The slave device should examine this bit to determine if it is to be a transmitter or a receiver. If the SRW flag is "1" then this indicates that the master device wishes to read data from the I

2

C bus, therefore the slave device must be setup to send data to the I

2

C bus as a transmitter. If the SRW flag is "0" then this indicates that the master wishes to send data to the I

2

C bus, therefore the slave device must be setup to read data from the I

2

C bus as a receiver.

I

2

C Bus Slave Address Acknowledge Signal

After the master has transmitted a calling address, any slave device on the I

2

C bus, whose own internal address matches the calling address, must generate an acknowledge signal. The acknowledge signal will inform the master that a slave device has accepted its calling address. If no acknowledge signal is received by the master then a STOP signal must be transmitted by the master to end the communication. When the HAAS flag is high, the addresses have matched and the slave device must check the SRW flag to determine if it is to be a transmitter or a receiver. If the SRW flag is high, the slave device should be setup to be a transmitter so the HTX bit in the SIMC1 register should be set to "1" . If the SRW flag is low, then the microcontroller slave device should be setup as a receiver and the HTX bit in the SIMC1 register should be set to "0" .

I

2

C Bus Data and Acknowledge Signal

The transmitted data is 8-bits wide and is transmitted after the slave device has acknowledged receipt of its slave address. The order of serial bit transmission is the MSB first and the LSB last.

After receipt of 8-bits of data, the receiver must transmit an acknowledge signal, level "0"., before it can receive the next data byte. If the slave transmitter does not receive an acknowledge bit signal from the master receiver, then the slave transmitter will release the SDA line to allow the master to send a STOP signal to release the I

2

C Bus. The corresponding data will be stored in the SIMD register. If setup as a transmitter, the slave device must first write the data to be transmitted into the

SIMD register. If setup as a receiver, the slave device must read the transmitted data from the SIMD register.

When the slave receiver receives the data byte, it must generate an acknowledge bit, known as

TXAK, on the 9th clock. The slave device, which is setup as a transmitter will check the RXAK bit in the SIMC1 register to determine if it is to send another data byte, if not then it will release the

SDA line and await the receipt of a STOP signal from the master.

HT68FB540/HT68FB550/HT68FB560

I/O Flash USB MCU with SPI

Rev. 1.40

13� De�e��e� 01� �01� Rev. 1.40 137 De�e��e� 01� �01�

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I/O Flash USB MCU with SPI

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I/O Flash USB MCU with SPI

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I

2

C Communication Timing Diagram

Note: *When a slave address is matched, the device must be placed in either the transmit mode and then write data to the SIMD register, or in the receive mode where it must implement a dummy read from the SIMD register to release the SCL line.

Rev. 1.40



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I

2

C Bus ISR Flow Chart

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HT68FB540/HT68FB550/HT68FB560

I/O Flash USB MCU with SPI

I

2

C Time Out Function

The I

2

C interface provides a time-out scheme to prevent a locked situation which might take place by an unexpected clock timing generated by a noise input signal. When the I

2

C interface has been locked for a period of time, the I 2 C hardware and the register, SIMC1, will be initialized automatically and the I2CTOF bit in the I2CTOC register will be set high. The Time Out function enable/disable and the time-out period are managed by the I2CTOC register.

I

2

C Time Out Operation

The time-out counter will start counting when the I

2

C interface received the START bit and address match. After that the counter will be cleared on each falling edge of the SCL pin. If the time counter is larger than the selected time-out time, then the anti-locked protection scheme will take place and the time-out counter will be stopped by hardware automatically, the I2CTOF bit will be set high and an I

2

C interrupt will also take place. Note that this scheme can also be stopped when the I

2

C received the STOP bit. There are several time-out periods can be selected by the I2CTOS0~I2CTOS5 bits in the I2CTOC register.

• I2CTOC Register

Bit

Na�e

R/W

7

R/W

6

I�CTOEN I�CTOF I�CTOS5 I�CTOS4 I�CTOS3 I�CTOS� I�CTOS1 I�CTOS0

R/W

5

R/W

4

R/W

3

R/W

2

R/W

1

R/W

0

R/W

POR 0 0 0 0 0 0 0 0

Bit 7

Bit 6

Bit 5~0

I2CTOEN

: I

2

C Time Out function control bit

0: disable

1: enable

I2CTOF

: I

2

C Time Out indication bit

0: Not occurred

1: Occurred

I2CTOS5~I2CTOS0

: I

2

C Time out time period select

The I

2

C Time out clock is provided by the f

L

/32. The time out time period can be calculated from the accompanying equation.

([I2CTOS5:I2CTOS0]+1) x (32/f

L

)

Serial Interface – SPIA

The devices contain an independent SPI function. It is important not to confuse this independent SPI function with the additional one contained within the combined SIM function, which is described in another section of this datasheet. This independent SPI function will carry the name SPIA to distinguish it from the other one in the SIM.

The SPI interface is often used to communicate with external peripheral devices such as sensors,

Flash or EEPROM memory devices etc. Originally developed by Motorola, the four line SPI interface is a synchronous serial data interface that has a relatively simple communication protocol simplifying the programming requirements when communicating with external hardware devices.

The communication is full duplex and operates as a slave/master type, where the device can be either master or slave. Although the SPIA interface specification can control multiple slave devices from a single master, however this device is provided with only one SCSA pin. If the master needs to control multiple slave devices from a single master, the master can use I/O pins to select the slave devices.

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138 De�e��e� 01� �01�

HT68FB540/HT68FB550/HT68FB560

I/O Flash USB MCU with SPI

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I/O Flash USB MCU with SPI

Rev. 1.40

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I/O Flash USB MCU with SPI

SPIA Interface Operation

The SPIA interface is a full duplex synchronous serial data link. It is a four line interface with pin names SDIA, SDOA, SCKA and SCSA. Pins SDIA and SDOA are the Serial Data Input and Serial

Data Output lines, SCKA is the Serial Clock line and SCSA is the Slave Select line. As the SPIA interface pins are pin-shared with normal I/O pins, the SPIA interface must first be enabled by setting the correct bits in the SPIAC0 and SPIAC1 registers. the SPIA can be disabled or enabled using the SPIAEN bit in the SPIAC0 register. Communication between devices connected to the SPIA interface is carried out in a slave/master mode with all data transfer initiations being implemented by the master. The Master also controls the clock signal. As the device only contains a single SCSA pin only one slave device can be utilized.

The SCSA pin is controlled by the application program, set the SACSEN bit to "1" to enable the

SCSA pin function and clear the SACSEN bit to "0" to place the SCSA pin into a floating state.

SPIA Master/Slave Connection

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SPIA Block Diagram

The SPIA function in this device offers the following features:

• Full duplex synchronous data transfer

• Both Master and Slave modes

• LSB first or MSB first data transmission modes

• Transmission complete flag

• Rising or falling active clock edge

• SAWCOL bit enabled or disable select

The status of the SPIA interface pins is determined by a number of factors such as whether the device is in the master or slave mode and upon the condition of certain control bits such as SACSEN and SPIAEN.

Rev. 1.40 139 De�e��e� 01� �01�

HT68FB540/HT68FB550/HT68FB560

I/O Flash USB MCU with SPI

SPIA Registers

There are four internal registers which control the overall operation of the SPIA interface. These are the SPIAD data register and three registers SPIAC0, SPIAC1 and SBSC. The SA_WCOL bit in the

SBSC register is used to control the SPIA WCOL function.

Register

Name

SPIAC0

SPIAC1

SPIAD

7

SASPI�

D7

Bit

6 5

SASPI1 SASPI0

D�

4

3

2

1

SPIAEN

SACKPOL SACKEG SAMLS SACSEN SAWCOL

D5 D4 D3 D� D1

0

SATRF

D0

SBSC SIM_WCOL — I�CDB1 I�CDB0 — — — SA_WCOL

SPIA Registers List

The SPIAD register is used to store the data being transmitted and received. Before the device writes data to the SPIA bus, the actual data to be transmitted must be placed in the SPIAD register.

After the data is received from the SPIA bus, the device can read it from the SPIAD register. Any transmission or reception of data from the SPIA bus must be made via the SPIAD register.

SPIAD Register

Bit

Na�e

R/W

7

D7

R/W

6

D�

R/W

5

D5

R/W

4

D4

R/W

3

D3

R/W

2

D�

R/W

1

D1

R/W

0

D0

R/W

POR x x x x x x x x

"x" unknown

There are also three control registers for the SPIA interface, SPIAC0, SPIAC1 and SBSC. Register

SPIAC0 is used to control the enable/disable function and to set the data transmission clock frequency. Register SPIAC1 is used for other control functions such as LSB/MSB selection, write collision flag etc.

SPIAC0 Register

Bit

Na�e

R/W

POR

Bit 7~5

Bit 4~2

7

SASPI�

R/W

1

6

SASPI1

R/W

1

5

SASPI0

R/W

1

4

0

3

0

2

0

1

SPIAEN

R/W

0

0

0

SASPI2 ~ SASPI0

: Master/Slave Clock Select

000 : SPIA master, f

SYS

/4

001 : SPIA master, f

SYS

/16

010 : SPIA master, f

SYS

/64

011 : SPIA master, f

L

100 : SPIA master, TM0 CCRP match frequency/2

101 : SPIA slave

110: unimplemented

111: unimplemented

These bits are used to control the SPIA Master/Slave selection and the SPIA Master clock frequency. The SPIA clock is a function of the system clock but can also be chosen to be sourced from TM0. If the SPIA Slave Mode is selected then the clock will be supplied by an external Master device

"—": unimplemented, read as "0"

Rev. 1.40

140 De�e��e� 01� �01�

HT68FB540/HT68FB550/HT68FB560

I/O Flash USB MCU with SPI

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I/O Flash USB MCU with SPI

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HT68FB540/HT68FB550/HT68FB560

I/O Flash USB MCU with SPI

Bit 1

Bit 0

SPIAEN

: SPIA enable or disable

0: disable

1: enable

The bit is the overall on/off control for the SIMA interface. When the SPIAEN bit is cleared to zero to disable the SPIA interface, the SDIA, SDOA, SCKA and SCSA lines will lose their SPI function and the SPIA operating current will be reduced to a minimum value. When the bit is high the SPIA interface is enabled.

"—": unimplemented, read as "0"

SPIAC1 Register

Bit

Na�e

7

R/W

POR

Bit 7~6

Bit 5

Bit 4

Bit 3

Bit 2

6

5 4 3 2 1 0

SACKPOL SACKEG SAMLS SACSEN SAWCOL SATRF

R/W

0

R/W

0

R/W

0

R/W

0

R/W

0

R/W

0

"—": unimplemented, read as "0".

This bit can be read or written by user software program.

SACKPOL

: Determines the base condition of the clock line

0: SCKA line will be high when the clock is inactive

1: SCKA line will be low when the clock is inactive

The SACKPOL bit determines the base condition of the clock line, if the bit is high, then the SCKA line will be low when the clock is inactive. When the SACKPOL bit is low, then the SCKA line will be high when the clock is inactive.

SACKEG

: Determines the SPIA SCKA active clock edge type

SACKPOL= 0:

0: SCKA has high base level with data capture on SCKA rising edge

1: SCKA has high base level with data capture on SCKA falling edge

SACKPOL= 1:

0: SCKA has low base level with data capture on SCKA falling edge

1: SCKA has low base level with data capture on SCKA rising edge

The SACKEG and SACKPOL bits are used to setup the way that the clock signal outputs and inputs data on the SPI bus. These two bits must be configured before a data transfer is executed otherwise an erroneous clock edge may be generated. The

SACKPOL bit determines the base condition of the clock line, if the bit is high, then the SCKA line will be low when the clock is inactive. When the SACKPOL bit is low, then the SCKA line will be high when the clock is inactive. The SACKEG bit determines active clock edge type which depends upon the condition of the SACKPOL bit.

SAMLS

: MSB/LSB First Bit

0: LSB shift first

1: MSB shift first

This is the data shift select bit and is used to select how the data is transferred, either

MSB or LSB first. Setting the bit high will select MSB first and low for LSB first.

SACSEN

: Select Signal Enable/Disable Bit

0: disable, other functions

1: Enable

The SACSEN bit is used as an enable/disable for the SCSA pin. If this bit is low, then the SCSA pin will be disabled and placed into other functions. If the bit is high the

SCSA pin will be enabled and used as a select pin.

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I/O Flash USB MCU with SPI

Bit 1

Bit 0

SAWCOL

: Write Collision Bit

0: Collision free

1: Collision detected

The SAWCOL flag is used to detect if a data collision has occurred. If this bit is high it means that data has been attempted to be written to the SPIAD register during a data transfer operation. This writing operation will be ignored if data is being transferred.

The bit can be cleared by the application program. Note that this function can be disabled or enabled via the SA_WCOL bit in the SBSC register.

SATRF

: Transmit/Receive Flag

0: Not complete

1: Transmission/reception complete

The SATRF bit is the Transmit/Receive Complete flag and is set "1" automatically when an SPIA data transmission is completed, but must set to zero by the application program. It can be used to generate an interrupt.

SBSC Register

Bit

Na�e

R/W

POR

Bit 7

Bit 6

Bit 5~4

Bit 3~1

Bit 0

7

SIM_WCOL

R/W

0

6

5 4

I�CDB1 I�CDB0

R/W R/W

0 0

SIM_WCOL

: SIM WCOL control bit

Related to SPI, described elsewhere.

"—": unimplemented, read as "0"

I2CDB1, I2CDB0

: I

2

C debounce selection bits

Related to I

2

C, described elsewhere.

"—": unimplemented, read as "0"

SA_WCOL

: SPIA WCOL function control

0: disable

1: enable.

3

2

1

0

SA_WCOL

R/W

0

SPIA Communication

After the SPIA interface is enabled by setting the SPIAEN bit high, then in the Master Mode, when data is written to the SPIAD register, transmission/reception will begin simultaneously. When the data transfer is complete, the SATRF flag will be set automatically, but must be cleared using the application program. In the Slave Mode, when the clock signal from the master has been received, any data in the SPIAD register will be transmitted and any data on the SDIA pin will be shifted into the SPIAD register.

The master should output an SCSA signal to enable the slave device before a clock signal is provided.

The slave data to be transferred should be well prepared at the appropriate moment relative to the SCSA signal depending upon the configurations of the SACKPOL bit and SACKEG bit. The accompanying timing diagram shows the relationship between the slave data and SCS signal for various configurations of the SACKPOL and SACKEG bits.

The SPIA will continue to function even in the IDLE Mode.

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I/O Flash USB MCU with SPI

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I/O Flash USB MCU with SPI





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SPIA Master Mode Timing

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SPIA Slave Mode Timing – SACKEG= 0

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SPIA Slave Mode Timing – SACKEG= 1

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I/O Flash USB MCU with SPI

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SPIA Transfer Control Flowchart

SPIA Bus Enable/Disable

To enable the SPIA bus, set SACSEN= 1 and SCSA=0, then wait for data to be written into the

SPIAD (TXRX buffer) register. For the Master Mode, after data has been written to the SPIAD

(TXRX buffer) register, then transmission or reception will start automatically. When all the data has been transferred the SATRF bit should be set. For the Slave Mode, when clock pulses are received on SCKA, data in the TXRX buffer will be shifted out or data on SDIA will be shifted in.

To disable the SPIA bus SCKA, SDIA, SDOA, SCSA will become I/O pins or the other functions.

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SPIA Operation

All communication is carried out using the 4-line interface for either Master or Slave Mode.

The SACSEN bit in the SPIAC1 register controls the overall function of the SPIA interface. Setting this bit high will enable the SPIA interface by allowing the SCSA line to be active, which can then be used to control the SPIA interface. If the SACSEN bit is low, the SPIA interface will be disabled and the SCSA line will be an I/O pin or the other functions and can therefore not be used for control of the SPIA interface. If the SACSEN bit and the SPIAEN bit in the SPIAC0 register are set high, this will place the SDIA line in a floating condition and the SDOA line high. If in Master Mode the

SCKA line will be either high or low depending upon the clock polarity selection bit SACKPOLB in the SPIAC1 register. If in Slave Mode the SCKA line will be in a floating condition. If SPIAEN is low then the bus will be disabled and SCSA, SDIA, SDOA and SCKA will all become I/O pins or the other functions. In the Master Mode the Master will always generate the clock signal. The clock and data transmission will be initiated after data has been written into the SPIAD register. In the Slave

Mode, the clock signal will be received from an external master device for both data transmission and reception. The following sequences show the order to be followed for data transfer in both

Master and Slave Mode:

Master Mode

• Step 1

Select the clock source and Master mode using the SASPI2~SASPI0 bits in the SPIAC0 control register

• Step 2

Setup the SACSEN bit and setup the SAMLS bit to choose if the data is MSB or LSB first, this must be same as the Slave device.

• Step 3

Setup the SPIAEN bit in the SPIAC0 control register to enable the SPIA interface.

• Step 4

For write operations: write the data to the SPIAD register, which will actually place the data into the TXRX buffer. Then use the SCKA and SCSA lines to output the data. After this go to step 5.

For read operations: the data transferred in on the SDIA line will be stored in the TXRX buffer until all the data has been received at which point it will be latched into the SPIAD register.

• Step 5

Check the SAWCOL bit if set high then a collision error has occurred so return to step 4. If equal to zero then go to the following step.

• Step 6

Check the SATRF bit or wait for a SPIA serial bus interrupt.

• Step 7

Read data from the SPIAD register.

• Step 8

Clear SATRF.

• Step 9

Go to step 4.

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I/O Flash USB MCU with SPI

Slave Mode

• Step 1

Select the SPI Slave mode using the SASPI2~SASPI0 bits in the SPIAC0 control register

• Step 2

Setup the SACSEN bit and setup the SAMLS bit to choose if the data is MSB or LSB first, this setting must be the same with the Master device.

• Step 3

Setup the SPIAEN bit in the SPIAC0 control register to enable the SPIA interface.

• Step 4

For write operations: write the data to the SPIAD register, which will actually place the data into the TXRX buffer. Then wait for the master clock SCKA and SCSA signal. After this, go to step 5.

For read operations: the data transferred in on the SDIA line will be stored in the TXRX buffer until all the data has been received at which point it will be latched into the SPIAD register.

• Step 5

Check the SAWCOL bit if set high then a collision error has occurred so return to step 4. If equal to zero then go to the following step.

• Step 6

Check the SATRF bit or wait for a SPIA serial bus interrupt.

• Step 7

Read data from the SPIAD register.

• Step 8

Clear SATRF.

• Step 9

Go to step 4.

Error Detection

The SAWCOL bit in the SPIAC register is provided to indicate errors during data transfer. The bit is set by the SPIA serial Interface but must be cleared by the application program. This bit indicates a data collision has occurred which happens if a write to the SPIAD register takes place during a data transfer operation and will prevent the write operation from continuing. The overall function of the

SAWCOL bit can be disabled or enabled by the SA_WCOL bit in the SBSC register.

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I/O Flash USB MCU with SPI

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I/O Flash USB MCU with SPI

Peripheral Clock Output

The Peripheral Clock Output allows the device to supply external hardware with a clock signal synchronised to the microcontroller clock.

Peripheral Clock Operation

As the peripheral clock output pin, PCK, is shared with I/O line, the required pin function is chosen via

PCKEN in the SIMC0 register. The Peripheral Clock function is controlled using the SIMC0 register.

The clock source for the Peripheral Clock Output can originate from either the TM0 CCRP match frequency/2 or a divided ratio of the internal f

SYS

clock. The PCKEN bit in the SIMC0 register is the overall on/off control, setting PCKEN bit to "1" enables the Peripheral Clock, setting PCKEN bit to "0" disables it. The required division ratio of the system clock is selected using the PCKP1 and PCKP0 bits in the same register. If the device enters the SLEEP Mode this will disable the Peripheral Clock output.

SIMC0 Register

Bit

Na�e

R/W

POR

Bit 7~5

Bit 4

Bit 3~2

Bit 1

Bit 0

7

SIM�

R/W

1

6

SIM1

R/W

1

5

SIM0

R/W

1

4

PCKEN

R/W

0

3

PCKP1

R/W

0

2

PCKP0

R/W

0

1

SIMEN

R/W

0

0

SIM2, SIM1, SIM0

: SIM operating mode control

000: SPI master mode; SPI clock is f

SYS

/4

001: SPI master mode; SPI clock is f

SYS

/16

010: SPI master mode; SPI clock is f

SYS

/64

011: SPI master mode; SPI clock is f

L

100: SPI master mode; SPI clock is TM0 CCRP match frequency/2

101: SPI slave mode

110: I

2

C slave mode

111: non SIM function

These bits setup the overall operating mode of the SIM function. As well as selecting if the I

2

C or SPI function, they are used to control the SPI Master/Slave selection and the SPI Master clock frequency. The SPI clock is a function of the system clock but can also be chosen to be sourced from the TM0. If the SPI Slave Mode is selected then the clock will be supplied by an external Master device.

PCKEN

: PCK output pin control

0: disable

1: enable

PCKP1, PCKP0

: select PCK output pin frequency

00: f

SYS

01: f

SYS

/4

10: f

SYS

/8

11: TM0 CCRP match frequency/2

SIMEN

: SIM control

0: disable

1: enable

The bit is the overall on/off control for the SIM interface. When the SIMEN bit is cleared to zero to disable the SIM interface, the SDI, SDO, SCK and SCS , or SDA and

SCL lines will be in a floating condition and the SIM operating current will be reduced to a minimum value. When the bit is high the SIM interface is enabled. Note that when the SIMEN bit changes from low to high the contents of the SPI control registers will be in an unknown condition and should therefore be first initialised by the application program.

"—": unimplemented, read as "0"

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Interrupts

Interrupts are an important part of any microcontroller system. When an external event or an internal function such as a Timer Module requires microcontroller attention, their corresponding interrupt will enforce a temporary suspension of the main program allowing the microcontroller to direct attention to their respective needs. The device contains several external interrupt and internal interrupts functions. The external interrupts are generated by the action of the external INT0 and

INT1 pins, while the internal interrupts are generated by various internal functions such as the TMs,

LVD, SIM, SPIA and USB.

Interrupt Registers

Overall interrupt control, which basically means the setting of request flags when certain microcontroller conditions occur and the setting of interrupt enable bits by the application program, is controlled by a series of registers, located in the Special Purpose Data Memory, as shown in the accompanying table. The number of registers depends upon the device chosen but fall into three categories. The first is the INTC0~INTC2 registers which setup the primary interrupts, the second is the MFI0~MFI1 registers which setup the Multi-function interrupts. Finally there is an INTEG register to setup the external interrupt trigger edge type.

Each register contains a number of enable bits to enable or disable individual registers as well as interrupt flags to indicate the presence of an interrupt request. The naming convention of these follows a specific pattern. First is listed an abbreviated interrupt type, then the (optional) number of that interrupt followed by either an "E" for enable/disable bit or "F" for request flag.

Function

Glo�al

INTn Pin

Multi-fun�tion

SIM

SPIA

LVD

TM

USB

Enable Bit

EMI

INTnE

MFnE

SIME

SPIAE

LVE

TnPE

TnAE

USBE

Request Flag

INTnF

MFnF

SIMF

SPIAF

LVF

TnPF

TnAF

USBF

Interrupt Register Bit Naming Conventions

Notes

— n=0 o� 1 n=0~3

— n=0~3

Interrupt Register Contents

Name

INTEG

INTC0

INTC1

INTC�

MFI0

MFI1

7

MF1F

SPIAF

T1AF

T3AF

6

USBF

MF0F

SIMF

T1PF

T3PF

5

INT1F

MF3F

T0AF

T�AF

4

INT0F

LVF

Bit

3

INT1S1

USBE

MF1E

MF�F

T0PF

T�PF

SPIAE

T1AE

T3AE

2

INT1S0

INT1E

MF0E

SIME

T1PE

T3PE

1

INT0S1

INT0E

MF3E

T0AE

T�AE

0

INT0S0

EMI

LVE

MF�E

T0PE

T�PE

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• INTEG Register

Bit

Na�e

7

R/W

POR

R

0

R

0

6

R

0

5

R

0

4

3

INT1S1

R/W

0

2

INT1S0

R/W

0

Bit 7~4

Bit 3~2

Bit 1~0

• INTC0 Register

Bit

Na�e

7

R/W

POR

R

0

"—": unimplemented, read as "0"

INT1S1, INT1S0

: interrupt edge control for INT1 pin

00: disable

01: rising edge

10: falling edge

11: rising and falling edges

INT0S1, INT0S0

: interrupt edge control for INT0 pin

00: disable

01: rising edge

10: falling edge

11: rising and falling edges

6

USBF

R/W

0

5

INT1F

R/W

0

4

INT0F

R/W

0

3

USBE

R/W

0

2

INT1E

R/W

0

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

"—": unimplemented, read as "0"

USBF

: USB Interrupt Request Flag

0: no request

1: interrupt request

INT1F

: INT1 interrupt request flag

0: no request

1: interrupt request

INT0F

: INT0 interrupt request flag

0: no request

1: interrupt request

USBE

: USB Interrupt Control

0: disable

1: enable

INT1E

: INT1 interrupt control

0: disable

1: enable

INT0E

: INT0 interrupt control

0: disable

1: enable

EMI

: Global interrupt control

0: disable

1: enable

1

INT0S1

R/W

0

0

INT0S0

R/W

0

1

INT0E

R/W

0

0

EMI

R/W

0

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I/O Flash USB MCU with SPI

• INTC1 Register

Bit

Na�e

7

MF1F

R/W

POR

R/W

0

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

6

MF0F

R/W

0

R

0

5

4

LVF

R/W

0

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

MF1F

: Multi-function Interrupt 1 Request Flag

0: no request

1: interrupt request

MF0F

: Multi-function Interrupt 0 Request Flag

0: no request

1: interrupt request

"—": unimplemented, read as "0"

LVF

: LVD interrupt request flag

0: No request

1: Interrupt request

MF1E

: Multi-function Interrupt 1 Interrupt Control

0: disable

1: enable

MF0E

: Multi-function Interrupt 0 Interrupt Control

0: disable

1: enable

"—": unimplemented, read as "0"

LVE

: LVD Interrupt Control

0: disable

1: enable

• INTC2 Register

Bit

Na�e

R/W

7

SPIAF

R/W

POR 0

6

SIMF

R/W

0

5

MF3F

R/W

0

4

MF�F

R/W

0

3

SPIAE

R/W

0

Bit 7

SPIAF

: SPIA interrupt request flag

0: no request

1: interrupt request

SIMF

: SIM interrupt request flag

0: no request

1: interrupt request

MF3F

: Multi-function Interrupt 3 Request Flag

0: no request

1: interrupt request

MF2F

: Multi-function Interrupt 2 Request Flag

0: no request

1: interrupt request

SPIAE

: SPIA Interrupt Control

0: disable

1: enable

SIME

: SIM Interrupt Control

0: disable

1: enable

3

MF1E

R/W

0

2

MF0E

R/W

0

2

SIME

R/W

0

R

0

1

0

LVE

R/W

0

1

MF3E

R/W

0

0

MF�E

R/W

0

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Rev. 1.40

Bit 1

Bit 0

MF3E

: Multi-function Interrupt 3 Control

0: disable

1: enable

MF2E

: Multi-function Interrupt 2 Control

0: disable

1: enable

• MFI0 Register

Bit 7

Na�e

R/W

POR

T1AF

R/W

0

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

6

T1PF

R/W

0

5

T0AF

R/W

0

4

T0PF

R/W

0

3

T1AE

R/W

0

T1AF

: TM1 Comparator A match interrupt request flag

0: no request

1: interrupt request

T1PF

: TM1 Comparator P match interrupt request flag

0: no request

1: interrupt request

T0AF

: TM0 Comparator A match interrupt request flag

0: no request

1: interrupt request

T0PF

: TM0 Comparator P match interrupt request flag

0: no request

1: interrupt request

T1AE

: TM1 Comparator A match interrupt control

0: disable

1: enable

T1PE

: TM1 Comparator P match interrupt control

0: disable

1: enable

T0AE

: TM0 Comparator A match interrupt control

0: disable

1: enable

T0PE

: TM0 Comparator P match interrupt control

0: disable

1: enable

2

T1PE

R/W

0

• MFI1 Register

Bit

Na�e

R/W

7

T3AF

R/W

POR 0

Bit 7

Bit 6

Bit 5

6

T3PF

R/W

0

5

T�AF

R/W

0

4

T�PF

R/W

0

3

T3AE

R/W

0

T3AF

: TM3 Comparator A match interrupt request flag

0: no request

1: interrupt request

T3PF

: TM3 Comparator P match interrupt request flag

0: no request

1: interrupt request

T2AF

: TM2 Comparator A match interrupt request flag

0: no request

1: interrupt request

2

T3PE

R/W

0

1

T0AE

R/W

0

0

T0PE

R/W

0

1

T�AE

R/W

0

0

T�PE

R/W

0

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Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

T2PF

: TM2 Comparator P match interrupt request flag

0: no request

1: interrupt request

T3AE

: TM3 Comparator A match interrupt control

0: disable

1: enable

T3PE

: TM3 Comparator P match interrupt control

0: disable

1: enable

T2AE

: TM2 Comparator A match interrupt control

0: disable

1: enable

T2PE

: TM2 Comparator P match interrupt control

0: disable

1: enable

Interrupt Operation

When the conditions for an interrupt event occur, such as a TM Compare P, Compare A or Compare

B match etc, the relevant interrupt request flag will be set. Whether the request flag actually generates a program jump to the relevant interrupt vector is determined by the condition of the interrupt enable bit. If the enable bit is set high then the program will jump to its relevant vector; if the enable bit is zero then although the interrupt request flag is set an actual interrupt will not be generated and the program will not jump to the relevant interrupt vector. The global interrupt enable bit, if cleared to zero, will disable all interrupts.

When an interrupt is generated, the Program Counter, which stores the address of the next instruction to be executed, will be transferred onto the stack. The Program Counter will then be loaded with a new address which will be the value of the corresponding interrupt vector. The microcontroller will then fetch its next instruction from this interrupt vector. The instruction at this vector will usually be a "JMP" which will jump to another section of program which is known as the interrupt service routine. Here is located the code to control the appropriate interrupt. The interrupt service routine must be terminated with a "RETI" , which retrieves the original Program Counter address from the stack and allows the microcontroller to continue with normal execution at the point where the interrupt occurred.

The various interrupt enable bits, together with their associated request flags, are shown in the accompanying diagrams with their order of priority. Some interrupt sources have their own individual vector while others share the same multi-function interrupt vector. Once an interrupt subroutine is serviced, all the other interrupts will be blocked, as the global interrupt enable bit,

EMI bit will be cleared automatically. This will prevent any further interrupt nesting from occurring.

However, if other interrupt requests occur during this interval, although the interrupt will not be immediately serviced, the request flag will still be recorded.

If an interrupt requires immediate servicing while the program is already in another interrupt service routine, the EMI bit should be set after entering the routine, to allow interrupt nesting. If the stack is full, the interrupt request will not be acknowledged, even if the related interrupt is enabled, until the Stack Pointer is decremented. If immediate service is desired, the stack must be prevented from becoming full. In case of simultaneous requests, the accompanying diagram shows the priority that is applied. All of the interrupt request flags when set will wake-up the device if it is in SLEEP or

IDLE Mode, however to prevent a wake-up from occurring the corresponding flag should be set before the device is in SLEEP or IDLE Mode.

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I/O Flash USB MCU with SPI

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I/O Flash USB MCU with SPI

Legend

xxF

Request Flag - no auto reset in ISR xxF

Request Flag - auto reset in ISR xxE

Enable Bit

Interrupt

Name

Request

Flags

Enable

Bits

TM 0 P

TM 0 A

T0PF

T0AF

T0PE

T0AE

EMI auto disabled in ISR

Interrupt

Name

INT0 Pin

Request

Flags

INT0F

INT1 Pin INT1F

USB USBF

M. Funct.0

MF0F

Enable

Bits

INT0E

INT1E

USBE

MF0E

Master

Enable

EM I

EM I

EM I

EM I

Vector

04H

Priority

High

08H

0CH

10H

TM 1 P

TM 1 A

TM 2 P

TM 2 A

T1PF

T1AF

T2PF

T2AF

T1PE

T1AE

T2PE

T2AE

M.Funct.1

M.Funct.2

MF1F

MF2F

MF1E

MF2E

EM I

EM I

14H

18H

TM 3 P

TM 3 A

T3PF

T3AF

T3PE

T3AE

M.Funct.3

MF3F MF3E EM I

1CH

SIM SIMF SIME EM I 20H

Interrupt contained with in

Multi-Function Interrupts

SPIA SPIAF

SPIAE

EM I

24H

LVD

LVF LVE EM I

28H

Low

External Interrupt

The external interrupts are controlled by signal transitions on the pins INT0 and INT1. An external interrupt request will take place when the external interrupt request flags, INT0F, INT1F, are set, which will occur when a transition, whose type is chosen by the edge select bits, appears on the external interrupt pins. To allow the program to branch to its respective interrupt vector address, the global interrupt enable bit, EMI, and respective external interrupt enable bit, INT0E, INT1E, must first be set. Additionally the correct interrupt edge type must be selected using the INTEG register to enable the external interrupt function and to choose the trigger edge type. As the external interrupt pins are pin-shared with I/O pins, they can only be configured as external interrupt pins if their external interrupt enable bit in the corresponding interrupt register has been set. The pin must also be setup as an input by setting the corresponding bit in the port control register. When the interrupt is enabled, the stack is not full and the correct transition type appears on the external interrupt pin, a subroutine call to the external interrupt vector, will take place. When the interrupt is serviced, the external interrupt request flags, INT0F, INT1F, will be automatically reset and the EMI bit will be automatically cleared to disable other interrupts. Note that any pull-high resistor selections on the external interrupt pins will remain valid even if the pin is used as an external interrupt input.

The INTEG register is used to select the type of active edge that will trigger the external interrupt.

A choice of either rising or falling or both edge types can be chosen to trigger an external interrupt.

Note that the INTEG register can also be used to disable the external interrupt function.

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I/O Flash USB MCU with SPI

USB Interrupt

A USB interrupt request will take place when the USB interrupt request flags, USBF, is set, a situation that will occur when an endpoint is accessed. To allow the program to branch to its respective interrupt vector address, the global interrupt enable bit, EMI, and USB interrupt enable bit, USBE, must first be set. When the interrupt is enabled, the stack is not full and an endpoint is accessed, a subroutine call to the USB interrupt vector, will take place. When the interrupt is serviced, the USB interrupt request flag, USBF, will be automatically reset and the EMI bit will be automatically cleared to disable other interrupts.

Serial Interface Module Interrupts – SIM Interrupt

The Serial Interface Module interrupt, known as the SIM interrupt, will take place when the

SIM Interrupt request flag, SIMF, is set, which occurs when a byte of data has been received or transmitted by the SIM interface. To allow the program to branch to its respective interrupt vector address, the global interrupt enable bit, EMI, and the Serial Interface Interrupt enable bit, SIME, must first be set. When the interrupt is enabled, the stack is not full and a byte of data has been transmitted or received by the SIM interface, a subroutine call to the respective Interrupt vector, will take place. When the Serial Interface Interrupt is serviced, the EMI bit will be automatically cleared to disable other interrupts and the SIMF flag will be automatically cleared as well.

Serial Peripheral Interface Interrupt – SPIA Interrupt

The Serial Peripheral Interface Interrupt, also known as the SPIA interrupt, will take place when the

SPIA Interrupt request flag, SPIAF, is set, which occurs when a byte of data has been received or transmitted by the SPIA interface. To allow the program to branch to its respective interrupt vector address, the global interrupt enable bit, EMI, and the Serial Interface Interrupt enable bit, SPIAE, must first be set. When the interrupt is enabled, the stack is not full and a byte of data has been transmitted or received by the SPIA interface, a subroutine call to the respective Interrupt vector, will take place. When the interrupt is serviced, the Serial Interface Interrupt flag, SPIAF, will be automatically cleared. The EMI bit will also be automatically cleared to disable other interrupts.

LVD Interrupt

The Low Voltage Detector interrupt, known as the LVD interrupt, will take place when the LVD

Interrupt request flag, LVF, is set, which occurs when the Low Voltage Detector function detects a low power supply voltage. To allow the program to branch to its respective interrupt vector address, the global interrupt enable bit, EMI and Low Voltage Interrupt enable bit, LVE, must first be set.

When the interrupt is enabled, the stack is not full and a low voltage condition occurs, a subroutine call to the LVD Interrupt vector, will take place. When the Low Voltage Interrupt is serviced, the EMI bit will be automatically cleared to disable other interrupts and the LVF flag will be automatically cleared as well.

Multi-function Interrupt

Within this device there is various Multi-function interrupts. Unlike the other independent interrupts, these interrupts have no independent source, but rather are formed from other existing interrupt sources, namely the TM Interrupts.

A Multi-function interrupt request will take place when any of the Multi-function interrupt request flags, MF0F~MF3F are set. The Multi-function interrupt flags will be set when any of their included functions generate an interrupt request flag. To allow the program to branch to its respective interrupt vector address, when the Multi-function interrupt is enabled and the stack is not full, and either one of the interrupts contained within each of Multi-function interrupt occurs, a subroutine call to one of

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the Multi-function interrupt vectors will take place. When the interrupt is serviced, the related Multi-

Function request flag will be automatically reset and the EMI bit will be automatically cleared to disable other interrupts.

However, it must be noted that, although the Multi-function Interrupt flags will be automatically reset when the interrupt is serviced, the request flags from the original source of the Multi-function interrupts, namely the TM Interrupts, interrupt will not be automatically reset and must be manually reset by the application program.

TM Interrupts

The Compact and Standard Type TMs have two interrupts each. All of the TM interrupts are contained within the Multi-function Interrupts. For each of the Compact and Standard Type TMs there are two interrupt request flags TnPF and TnAF and two enable bits TnPE and TnAE. A TM interrupt request will take place when any of the TM request flags are set, a situation which occurs when a TM comparator P or A match situation happens.

To allow the program to branch to its respective interrupt vector address, the global interrupt enable bit, EMI, respective TM Interrupt enable bit, and relevant Multi-function Interrupt enable bit, MFnE, must first be set. When the interrupt is enabled, the stack is not full and a TM comparator match situation occurs, a subroutine call to the relevant Multi-function Interrupt vector locations, will take place. When the TM interrupt is serviced, the EMI bit will be automatically cleared to disable other interrupts, however only the related MFnF flag will be automatically cleared. As the TM interrupt request flags will not be automatically cleared, they have to be cleared by the application program.

Interrupt Wake-up Function

Each of the interrupt functions has the capability of waking up the microcontroller when in the

SLEEP or IDLE Mode. A wake-up is generated when an interrupt request flag changes from low to high and is independent of whether the interrupt is enabled or not. Therefore, even though the device is in the SLEEP or IDLE Mode and its system oscillator stopped, situations such as external edge transitions on the external interrupt pins, a low power supply voltage or comparator input change may cause their respective interrupt flag to be set high and consequently generate an interrupt. Care must therefore be taken if spurious wake-up situations are to be avoided. If an interrupt wake-up function is to be disabled then the corresponding interrupt request flag should be set high before the device enters the SLEEP or IDLE Mode. The interrupt enable bits have no effect on the interrupt wake-up function.

Programming Considerations

By disabling the relevant interrupt enable bits, a requested interrupt can be prevented from being serviced, however, once an interrupt request flag is set, it will remain in this condition in the interrupt register until the corresponding interrupt is serviced or until the request flag is cleared by the application program.

Where a certain interrupt is contained within a Multi-function interrupt, then when the interrupt service routine is executed, as only the Multi-function interrupt request flags, MF0F~MF3F, will be automatically cleared, the individual request flag for the function needs to be cleared by the application program.

It is recommended that programs do not use the "CALL" instruction within the interrupt service subroutine. Interrupts often occur in an unpredictable manner or need to be serviced immediately.

If only one stack is left and the interrupt is not well controlled, the original control sequence will be damaged once a CALL subroutine is executed in the interrupt subroutine.

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Every interrupt has the capability of waking up the microcontroller when it is in the SLEEP or IDLE

Mode, the wake up being generated when the interrupt request flag changes from low to high. If it is required to prevent a certain interrupt from waking up the microcontroller then its respective request flag should be first set high before enter SLEEP or IDLE Mode.

As only the Program Counter is pushed onto the stack, then when the interrupt is serviced, if the contents of the accumulator, status register or other registers are altered by the interrupt service program, their contents should be saved to the memory at the beginning of the interrupt service routine.

To return from an interrupt subroutine, either a RET or RETI instruction may be executed. The RETI instruction in addition to executing a return to the main program also automatically sets the EMI bit high to allow further interrupts. The RET instruction however only executes a return to the main program leaving the EMI bit in its present zero state and therefore disabling the execution of further interrupts.

Low Voltage Detector – LVD

Each device has a Low Voltage Detector function, also known as LVD. This enabled the device to monitor the power supply voltage, V

DD

, and provide a warning signal should it fall below a certain level. This function may be especially useful in battery applications where the supply voltage will gradually reduce as the battery ages, as it allows an early warning battery low signal to be generated.

The Low Voltage Detector also has the capability of generating an interrupt signal.

LVD Register

The Low Voltage Detector function is controlled using a single register with the name LVDC. Three bits in this register, VLVD2~VLVD0, are used to select one of eight fixed voltages below which a low voltage condition will be determined. A low voltage condition is indicated when the LVDO bit is set. If the LVDO bit is low, this indicates that the V

DD

voltage is above the preset low voltage value. The LVDEN bit is used to control the overall on/off function of the low voltage detector.

Setting the bit high will enable the low voltage detector. Clearing the bit to zero will switch off the internal low voltage detector circuits. As the low voltage detector will consume a certain amount of power, it may be desirable to switch off the circuit when not in use, an important consideration in power sensitive battery powered applications.

LVDC Register

Bit

Na�e

R/W

POR

Bit 7 ~ 6

Bit 5

Bit 4

Bit 3

R

0

7

R

0

6

5

LVDO

R

0

4

LVDEN

R/W

0

"—": unimplemented, read as "0"

LVDO

: LVD Output Flag

0: No Low Voltage Detect

1: Low Voltage Detect

LVDEN

: Low Voltage Detector Control

0: disable

1: enable

"—": unimplemented, read as "0"

R

0

3

2

VLVD�

R/W

0

1

VLVD1

R/W

0

0

VLVD0

R/W

0

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Bit 2~0

VLVD2~VLVD0

: Select LVD Voltage

000: 2.0V

001: 2.2V

010: 2.4V

011: 2.7V

100: 3.0V

101: 3.3V

110: 3.6V

111: 4.0V

LVD Operation

The Low Voltage Detector function operates by comparing the power supply voltage, V

DD

, with a pre-specified voltage level stored in the LVDC register. This has a range of between 2.0V and 4.0V.

When the power supply voltage, V

DD

, falls below this pre-determined value, the LVDO bit will be set high indicating a low power supply voltage condition. The Low Voltage Detector function is supplied by a reference voltage which will be automatically enabled. When the device is powered down the low voltage detector will remain active if the LVDEN bit is high. After enabling the Low

Voltage Detector, a time delay t

LVDS

should be allowed for the circuitry to stabilise before reading the

LVDO bit. Note also that as the VDD voltage may rise and fall rather slowly, at the voltage nears that of VLVD, there may be multiple bit LVDO transitions

.

The Low Voltage Detector also has its own interrupt, providing an alternative means of low voltage detection, in addition to polling the LVDO bit. The interrupt will only be generated after a delay of t

LVD

after the LVDO bit has been set high by a low voltage condition. When the device is powered down the Low Voltage Detector will remain active if the LVDEN bit is high. In this case, the LVF interrupt request flag will be set, causing an interrupt to be generated if V

DD

falls below the preset

LVD voltage. This will cause the device to wake-up from the SLEEP or IDLE Mode, however if the Low Voltage Detector wake up function is not required then the LVF flag should be first set high before the device enters the SLEEP or IDLE Mode.

USB Interface

The USB interface is a 4-wire serial bus that allows communication between a host device and up to 127 max peripheral devices on the same bus. A token based protocol method is used by the host device for communication control. Other advantages of the USB bus include live plugging and unplugging and dynamic device configuration. As the complexity of USB data protocol does not permit comprehensive USB operation information to be provided in this datasheet, the reader should therefore consult other external information for a detailed USB understanding.

The device includes a USB interface function allowing for the convenient design of USB peripheral products.

The USB disable/enable control bit "USBdis" is in the SYSC Register. If the USB is disabled, then

V33O will be floating, the UDP/UDN lines will become I/O functions, and the USB SIE will be disabled.

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Power Plane

There are three power planes for HT68FB540/HT68FB550/HT68FB560: USB SIE VDD, VDDIO and the MCU VDD.

For the USB SIE VDD will supply all circuits related to USB SIE and be sourced from pin "UBUS".

Once the USB is removed from the USB and there is no power in the USB BUS, the USB SIE circuit is no longer operational.

For the PA and PD ports, it can be configured using the PAPS1, PAPS0 and PDPS registers to define the pins PA0~PA7, PD4~PD7 are supplied by the MCU VDD, the V33O or the power pin VDDIO.

For the MCU VDD, it supplies all the HT68FB540/HT68FB550/HT68FB560 circuits except the

USB SIE which is supply by UBUS.

The PE1 is pin shared with UBUS pin and it’s "input" only.

USB Suspend Wake-Up Remote Wake-Up

If there is no signal on the USB bus for over 3ms, the devices will go into a suspend mode. The

Suspend flag, SUSP, in the USC register, will then be set high and an USB interrupt will be generated to indicate that the devices should jump to the suspend state to meet the requirements of the USB suspend current spec. In order to meet the requirements of the suspend current, the firmware should disable the USB clock by clearing the US BCKEN bit to "0 " .

The suspend current can be further decreased by setting the SUSP2 bit in the UCC register. When the resume signal is sent out by the host, the device will be woken up the by the USB interrupt and the Resume bit in the USC register will be set. To ensure correct device operation, the program must set the USBCKEN bit in the UCC register high and clear the SUSP2 bit in the UCC register. The

Resume signal will be cleared before the Idle signal is sent out by the host and the Suspend line in the USC register will change to zero. So when the MCU detects the Suspend bit in the USC register, the condition of the Resume line should be noted and taken into consideration.

SUSPEND

USB Resume Signal

USB_INT

The device has a remote wake up function which can wake-up the USB Host by sending a wake-up pulse through RMWK in the USC register. Once the USB Host receives a wake-up signal from the device it will send a Resume signal to the device.

SUSPEND

Min. 1 USB CLK

RMWK

USB Resume Signal

Min.2.5ms

USB_INT

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USB Interface Operation

The HT68FB540, HT68FB550 and HT68FB560 have 4 Endpoints (EP0~EP3), 6 Endpoints

(EP0~EP5), and 8 Endpoints (EP0~EP7) respectively. The EP0 supports Control transfer. All

EP1~EP7 support Interrupt or Bulk transfer.

All endpoints except EP0 can be configure as 8, 16, 32, 64 FIFO size by the register UFC0 and

UFC1. EP0 has 8-byte FIFO size.

The Total FIFO size is 256 +8 bytes for the HT68FB540, 512 +8 bytes for the HT68FB550 and 768

+8 bytes for the HT68FB560.

As the USB FIFO is assigned from the last bank of the Data RAM and has a start address of 0FFH to the upper address, dependent on the FIFO size, if the corresponding data RAM bank is used for both general purpose RAM and the USB FIFO, special care should be taken that the RAM EQU definition should not overlap with the USB FIFO RAM address.

The URD in the USC register is the USB reset signal control function definition bit.

The USB FIFO size definition for IN/OUT control depends on the UFC, UFIEN and UFOEN registers. If OUT 1 not used, then the OUT 1 FIFO will not be defined and IN 2 will be defined as

IN 1 afterwards.

n80H

HT68FB540

Gene�al Pu�pose

Data Me�o�y nBFH nC0H nC7H nC8H

OUT 3 (8 �ytes)

IN 3 (8 �ytes)

OUT � (1� �ytes) nDFH nE0H

IN � (1� �ytes) nEFH nF0H nF7H nF8H nFFH

OUT 1 (8 �ytes)

IN 1 (8 �ytes)

"n"=Bank 1~0� last �ank fi�st defined

USB FIFO Size Define

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USB Interface Registers

The USB interface has a series of registers associated with its operation.

SYSC Register

Bit

Na�e

R/W

POR

Bit 7

Bit 6

Bit 5

Bit 4~3

Bit 2

Bit 1~0

7 6

CLK_ADJ USBdis

R/W

0

R/W

0

5

RUBUS

R/W

0

4

0

3

0

CLK_ADJ

: PLL Clock Automatic Adjustment function:

PLL related control bit, described elsewhere

USBdis

: USB SIE control bit

0: enable

1: disable

RUBUS

: UBUS pin pull low resistor

0: enable

1: disable

"—": unimplemented, read as "0"

HFV

: High frequency voltage control

This bit must be set to high.

"—": unimplemented, read as "0"

2

HFV

R/W

0

1

0

0

0

USB_STAT Register

Bit

Na�e

R/W

POR

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

7 6 5 4

PS�_CKO PS�_DAO PS�_CKI PS�_DAI

W

1

W

1

R

0

R

0

3

SE1

R/W

0

2

SE0

R/W

0

1

PU

R/W

0

0

ESD

R/W

0

PS2_CKO

: Output for driving UDP/GPIO1 pin, when work under GPIO mode function. Default value is "1".

PS2_DAO

: Output for driving UDN/GPIO0 pin, when work under GPIO mode function. Default value is "1".

PS2_CKI

: UDP/GPIO1 input.

PS2_DAI

: UDN/GPIO0 input.

SE1

: This bit is used to indicate the SIE has detected a SE1 noise in the USB bus. This bit is set by SIE and clear by F/W.

SE0

: This bit is used to indicate the SIE has detected a SE0 noise in the USB bus. This bit is set by SIE and clear by F/W.

PU

: Bit1=1, UDP, and UDN have a 600kΩ pull-high Bit1=0, no pull-high (default on

MCU reset)

ESD

: This bit will set to "1" when there is ESD issue.

This bit is set by SIE and cleared by F/W.

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UINT Register

• HT68FB540

Bit

Na�e

R/W

POR

7

R

0

Bit 7~4 :

Bit 3

Bit 2

Bit 1

Bit 0

R

0

6

5

R

0

4

R

0

"—": unimplemented, read as "0"

EP3EN

: USB endpoint3 interrupt control bit.

0: disable

1: enable

EP2EN

: USB endpoint2 interrupt control bit.

0: disable

1: enable

EP1EN

: USB endpoint1 interrupt control bit.

0: disable

1: enable

EP0EN

: USB endpoint0 interrupt control bit.

0: disable

1: enable

3

EP3EN

R/W

0

• HT68FB550

Bit

Na�e

R/W

POR

7

R

0

R

0

6

5

EP5EN

R/W

0

4

EP4EN

R/W

0

Bit 7 ~ 6 : "—": unimplemented, read as "0"

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

EP5EN

: USB endpoint5 interrupt control bit.

0: disable

1: enable

EP4EN

: USB endpoint4 interrupt control bit.

0: disable

1: enable

EP3EN

: USB endpoint3 interrupt control bit.

0: disable

1: enable

EP2EN

: USB endpoint2 interrupt control bit.

0: disable

1: enable

EP1EN

: USB endpoint1 interrupt control bit.

0: disable

1: enable

EP0EN

: USB endpoint0 interrupt control bit.

0: disable

1: enable

3

EP3EN

R/W

0

2

EP�EN

R/W

0

1

EP1EN

R/W

0

0

EP0EN

R/W

0

2

EP�EN

R/W

0

1

EP1EN

R/W

0

0

EP0EN

R/W

0

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• HT68FB560

Bit

Na�e

7

EP7EN

R/W

POR

R/W

0

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

6

EP�EN

R/W

0

5

EP5EN

R/W

0

4

EP4EN

R/W

0

EP7EN

: USB endpoint7 interrupt control bit.

0: disable

1: enable

EP6EN

: USB endpoint6 interrupt control bit.

0: disable

1: enable

EP5EN

: USB endpoint5 interrupt control bit.

0: disable

1: enable

EP4EN

: USB endpoint4 interrupt control bit.

0: disable

1: enable

EP3EN

: USB endpoint3 interrupt control bit.

0: disable

1: enable

EP2EN

: USB endpoint2 interrupt control bit.

0: disable

1: enable

EP1EN

: USB endpoint1 interrupt control bit.

0: disable

1: enable

EP0EN

: USB endpoint0 interrupt control bit.

0: disable

1: enable

3

EP3EN

R/W

0

USC Register

Bit

Na�e

R/W

POR

Bit 7

Bit 6

Bit 5

7

URD

R/W

1

6

SELPS�

R/W

0

5

PLL

R/W

0

4 3

SELUSB RESUME

R/W R

0 0

2

EP�EN

R/W

0

2

URST

R/W

0

1

EP1EN

R/W

0

1

RMWK

R/W

0

0

EP0EN

R/W

0

0

SUSP

R

0

URD

: USB reset signal control function definition

0: USB reset signal cannot MCU

1: USB reset signal will reset MCU

SELPS2

: PS2 mode select bit

0: not PS2 mode

1: PS2 mode

When the SELPS2 bit is set high, the PS2 function is selected and the pin-shared pins,

UDN/GPIO0 and UDP/ GPIO1, will become the GPIO0 and GPIO1 general purpose

I/O functions which can be used to be the DATA and CLK pins for the PS2.

PLL

: PLL control bit

0: Turn-on PLL

1: Turn-off PLL

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Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

SELUSB

: USB mode and V33O on/off select bit

0: not USB mode, turn-off V33O

1: USB mode, turn-on V33O

When the SELUSB bit is set high, the USB and V33O functions is selected and the pin-shared pins, UDN/GPIO0 and UDP/GPIO1, will become the UDN and UDP pins for the USB.

SELUSB SELPS2

0

0

1

0

1 x

USB and PS2 mode description

1.No �ode suppo�ted

2.V33O pin not output and it will floating

3.UDN/GPIO0 and UDP/GPIO1 pins �ann’t output

1.PS� �ode

�.V33O pin output VDD

3.UDN/GPIO0 and UDP/GPIO1 pins will �e�o�e the GPIO0 and

GPIO1 pins, which can output by firmware

1.USB mode

2.V33O output 3.3V

3.UDN/GPIO0 and UDP/GPIO1 pins will become the UDN and UDP pins x: don’t �a�e

RESUME

: USB resume indication bit

0: SUSP bit goes to "0"

1: leave the suspend mode

When the USB leaves the suspend mode, this bit is set to "1" (set by SIE). When the

RESUME is set by SIE, an interrupt will be generated to wake-up the MCU. In order to detect the suspend state, the MCU should set USBCKEN and clear SUSP2 (in the

UCC register) to enable the SIE detect function. RESUME will be cleared when the

SUSP goes to "0". When the MCU is detecting the SUSP, the condition of RESUME

(causes the MCU to wake-up) should be noted and taken into consideration.

URST

: USB reset indication bit

0: no USB reset

1: USB reset occurred

This bit is set/cleared by the USB SIE. This bit is used to detect a USB reset event on the USB bus. When this bit is set to "1", this indicates that a USB reset has occurred and that a USB interrupt will be initialized.

RMWK

: USB remote wake-up command

0: no remote wake-up

1: remote wake-up

It is set by MCU to leave the USB host leaving the suspend mode. This bit is set to produce a high pulse width of 4 m s to indicate that the USB host has left the suspend mode.

SUSP

: USB suspend indication

0: not in the suspend mode

1: enter the suspend mode

When this bit is set to 1 (set by SIE), it indicates that the USB bus has entered the suspend mode. The USB interrupt is also triggered when this bit changes from low to high.

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USR Register

• HT68FB540

Bit

Na�e

R/W

POR

7

R

0

6

R

0

5

R

0

Bit 7~4 :

Bit 3

Bit 2

Bit 1

Bit 0

"—": unimplemented, read as "0"

EP3F

: Endpoint 3 accessed detection

0: not accessed

1: accessed

EP2F

: Endpoint 2 accessed detection

0: not accessed

1: accessed

EP1F

: Endpoint 1 accessed detection

0: not accessed

1: accessed

EP0F

: Endpoint 0 accessed detection

0: not accessed

1: accessed

• HT68FB550

Bit

Na�e

R/W

POR

Bit 7~6 :

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

7

R

0

R

0

6

5

EP5F

R/W

0

4

EP4F

R/W

0

"—": unimplemented, read as "0"

EP5F

: Endpoint 5 accessed detection

0: not accessed

1: accessed

EP4F

: Endpoint 4 accessed detection

0: not accessed

1: accessed

EP3F

: Endpoint 3 accessed detection

0: not accessed

1: accessed

EP2F

: Endpoint 2 accessed detection

0: not accessed

1: accessed

EP1F

: Endpoint 1 accessed detection

0: not accessed

1: accessed

EP0F

: Endpoint 0 accessed detection

0: not accessed

1: accessed

4

R

0

3

EP3F

R/W

0

2

EP�F

R/W

0

1

EP1F

R/W

0

0

EP0F

R/W

0

3

EP3F

R/W

0

2

EP�F

R/W

0

1

EP1F

R/W

0

0

EP0F

R/W

0

1�4 De�e��e� 01� �01�

HT68FB540/HT68FB550/HT68FB560

I/O Flash USB MCU with SPI

Rev. 1.40 1�5 De�e��e� 01� �01�

HT68FB540/HT68FB550/HT68FB560

I/O Flash USB MCU with SPI

Rev. 1.40

1�4 De�e��e� 01� �01�

HT68FB540/HT68FB550/HT68FB560

I/O Flash USB MCU with SPI

• HT68FB560

Bit

Na�e

R/W

POR

7

EP7F

R/W

0

6

EP�F

R/W

0

5

EP5F

R/W

0

4

EP4F

R/W

0

3

EP3F

R/W

0

2

EP�F

R/W

0

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

EP7F

: Endpoint 7 accessed detection

0: not accessed

1: accessed

EP6F

: Endpoint 6 accessed detection

0: not accessed

1: accessed

EP5F

: Endpoint 5 accessed detection

0: not accessed

1: accessed

EP4F

: Endpoint 4 accessed detection

0: not accessed

1: accessed

EP3F

: Endpoint 3 accessed detection

0: not accessed

1: accessed

EP2F

: Endpoint 2 accessed detection Bit 2

Bit 1

Bit 0

UCC Register

• HT68FB540

0: not accessed

1: accessed

EP1F

: Endpoint 1 accessed detection

0: not accessed

1: accessed

EP0F

: Endpoint 0 accessed detection

0: not accessed

1: accessed

Bit

Na�e

R/W

POR

7

R�t�l

R/W

0

6 5 4 3

SYSCLK Fsys1�MHZ SUSP� USBCKEN

R/W

0

R/W

0

R/W

0

R/W

0

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1~0

2

R

0

Rctrl

: 7.5kΩ resistor between UDP and Ubus control bit

0: no 7.5kΩ resistor between UDP and Ubus

1: has 7.5kΩ resistor between UDP and Ubus

SYSCLK

: Specify MCU oscillator frequency indication bit

0: 12MHz crystal oscillator or resonator, clear this bit to "0".

1: 6MHz crystal oscillator or resonator, set this bit to "1".

Fsys16MHZ

: MCU system clock source control bit

0: from OSC.

1: from PLL output 16MHz.

SUSP2

: Reduce power consumption in suspend mode control bit

0: in normal mode

1: in halt mode, set this bit to "1" for reducing power consumption

USBCKEN

: USB clock control bit

0: disable

1: enable

"—": unimplemented, read as "0"

EPS1, EPS0

: Accessing endpoint FIFO selection

00: select endpoint 0 FIFO (control)

01: select endpoint 1 FIFO

10: select endpoint 2 FIFO

11: select endpoint 3 FIFO

1

EP1F

R/W

0

1

EPS1

R/W

0

Rev. 1.40 1�5

0

EP0F

R/W

0

0

EPS0

R/W

0

De�e��e� 01� �01�

HT68FB540/HT68FB550/HT68FB560

I/O Flash USB MCU with SPI

Rev. 1.40

• HT68FB550

Bit

Na�e

R/W

POR

7

R�t�l

R/W

0

R/W

POR

Bit 7

6 5

SYSCLK Fsys1�MHZ

R/W

0

R/W

0

4 3

SUSP� USBCKEN

R/W

0

R/W

0

2

EPS�

R/W

0

1

EPS1

R/W

0

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2~0

Rctrl

: 7.5kΩ resistor between UDP and Ubus control bit

0: no 7.5kΩ resistor between UDP and Ubus

1: has 7.5kΩ resistor between UDP and Ubus

SYSCLK

: Specify MCU oscillator frequency indication bit

0: 12MHz crystal oscillator or resonator, clear this bit to "0".

1: 6MHz crystal oscillator or resonator, set this bit to "1".

Fsys16MHZ

: MCU system clock source control bit

0: from OSC.

1: from PLL output 16MHz.

SUSP2

: Reduce power consumption in suspend mode control bit

0: In normal mode

1: In halt mode, set this bit to "1" for reducing power consumption

USBCKEN

: USB clock control bit

0: disable

1: enable

EPS2, EPS1, EPS0

: Accessing endpoint FIFO selection

000: Select endpoint 0 FIFO (control)

001: Select endpoint 1 FIFO

010: Select endpoint 2 FIFO

011: Select endpoint 3 FIFO

100: Select endpoint 4 FIFO

101~111: Select endpoint 5 FIFO

HT68FB560

Bit

Na�e

7

R�t�l

6 5 4 3

SYSCLK Fsys1�MHZ SUSP� USBCKEN

2

EPS�

1

EPS1

R/W

0

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2~0

R/W

0

R/W

0

R/W

0

R/W

0

R/W

0

R/W

0

Rctrl

: 7.5kΩ resistor between UDP and Ubus control bit

0: no 7.5kΩ resistor between UDP and Ubus

1: has 7.5kΩ resistor between UDP and Ubus

SYSCLK

: Specify MCU oscillator frequency indication bit

0: 12MHz crystal oscillator or resonator, clear this bit to "0".

1: 6MHz crystal oscillator or resonator, set this bit to "1".

Fsys16MHZ

: MCU system clock source control bit

0: from OSC.

1: from PLL output 16MHz.

SUSP2

: Reduce power consumption in suspend mode control bit

0: In normal mode

1: In halt mode, set this bit to "1" for reducing power consumption

USBCKEN

: USB clock control bit

0: disable

1: enable

EPS2, EPS1, EPS0

: Accessing endpoint FIFO selection

000: Select endpoint 0 FIFO (control)

001: Select endpoint 1 FIFO

010: Select endpoint 2 FIFO

011: Select endpoint 3 FIFO

100: Select endpoint 4 FIFO

101: Select endpoint 5 FIFO

110: Select endpoint 6 FIFO

111: Select endpoint 7 FIFO

0

EPS0

R/W

0

0

EPS0

R/W

0

1�� De�e��e� 01� �01�

HT68FB540/HT68FB550/HT68FB560

I/O Flash USB MCU with SPI

Rev. 1.40 1�7 De�e��e� 01� �01�

HT68FB540/HT68FB550/HT68FB560

I/O Flash USB MCU with SPI

Rev. 1.40

1�� De�e��e� 01� �01�

HT68FB540/HT68FB550/HT68FB560

I/O Flash USB MCU with SPI

AWR Register

Bit

Na�e

R/W

POR

Bit 7~1

Bit 0

7

AD�

R/W

0

6

AD5

R/W

0

5

AD4

R/W

0

4

AD3

R/W

0

3

AD�

R/W

0

2

AD1

R/W

0

1

AD0

R/W

0

0

WKEN

R/W

0

AD6~AD0

: USB device address

WKEN

: USB remote-wake-up control bit

0: disable

1: enable

The AWR register contains the current address and a remote wake up function control bit. The initial value of AWR is "00H". The address value extracted from the USB command has not to be loaded into this register until the SETUP stage has finished.

STLO Register

• HT68FB540

Bit

Na�e

R/W

POR

7

6

5

4

3

STLO3

R/W

0

2

STLO�

R/W

0

1

STLO1

R/W

0

0

STLO0

R/W

0

Bit 7~4

Bit 3~0

• HT68FB550

Bit

Na�e

R/W

POR

7

"—": unimplemented, read as "0"

STLO3~STLO0

: FIFO OUT stall endpoints indication bits

0: not stall

1: stall

The STLO register shows if the corresponding endpoint has worked properly or not.

As soon as endpoint improper operation occurs, the related bit in the STLO register has to be set high. The STLO register bits will be cleared by a USB reset signal and a setup token event.

6

5

STLO5

R/W

0

4

STLO4

R/W

0

3

STLO3

R/W

0

2

STLO�

R/W

0

1

STLO1

R/W

0

0

STLO0

R/W

0

Bit 7~6

Bit 5~0

"—": unimplemented, read as "0"

STLO5~STLO0

: FIFO OUT stall endpoints indication bits

0: not stall

1: stall

The STLO register shows if the corresponding endpoint has worked properly or not.

As soon as endpoint improper operation occurs, the related bit in the STLO register has to be set high. The STLO register bits will be cleared by a USB reset signal and a setup token event.

Rev. 1.40 1�7 De�e��e� 01� �01�

Rev. 1.40

HT68FB540/HT68FB550/HT68FB560

I/O Flash USB MCU with SPI

• HT68FB560

Bit

Na�e

7

STLO7

R/W

POR

R/W

0

Bit 7~0

6

STLO�

R/W

0

5

STLO5

R/W

0

4

STLO4

R/W

0

3

STLO3

R/W

0

2

STLO�

R/W

0

1

STLO1

R/W

0

0

STLO0

R/W

0

STLO7~STLO0

: FIFO OUT stall endpoints indication bits

0: not stall

1: stall

The STLO register shows if the corresponding endpoint has worked properly or not.

As soon as endpoint improper operation occurs, the related bit in the STLO register has to be set high. The STLO register bits will be cleared by a USB reset signal and a setup token event.

STLI Register

• HT68FB540

Bit

Na�e

R/W

POR

7

6

5

4

3

STLI3

R/W

0

2

STLI�

R/W

0

1

STLI1

R/W

0

0

STLI0

R/W

0

Bit 7~4 :

Bit 3~0

• HT68FB550

Bit

Na�e

R/W

POR

7

"—": unimplemented, read as "0"

STLI3~STLI0

: FIFO IN stall endpoints indication bits

0: not stall

1: stall

The STLI register shows if the corresponding endpoint has worked properly or not. As soon as endpoint improper operation occurs, the related bit in the STLI register has to be set high. The STLI register bits will be cleared by a USB reset signal and a setup token event.

6

5

STLI5

R/W

0

4

STLI4

R/W

0

3

STLI3

R/W

0

2

STLI�

R/W

0

1

STLI1

R/W

0

0

STLI0

R/W

0

Bit 7~6 :

Bit 5~0

"—": unimplemented, read as "0"

STLI5~STLI0

: FIFO IN stall endpoints indication bits

0: not stall

1: stall

The STLI register shows if the corresponding endpoint has worked properly or not. As soon as endpoint improper operation occurs, the related bit in the STLI register has to be set high. The STLI register bits will be cleared by a USB reset signal and a setup token event.

1�8 De�e��e� 01� �01�

HT68FB540/HT68FB550/HT68FB560

I/O Flash USB MCU with SPI

Rev. 1.40 1�9 De�e��e� 01� �01�

HT68FB540/HT68FB550/HT68FB560

I/O Flash USB MCU with SPI

Rev. 1.40

1�8 De�e��e� 01� �01�

HT68FB540/HT68FB550/HT68FB560

I/O Flash USB MCU with SPI

• HT68FB560

Bit

Na�e

7

STLI7

R/W

POR

R/W

0

Bit 7~0

6

STLI�

R/W

0

5

STLI5

R/W

0

4

STLI4

R/W

0

3

STLI3

R/W

0

2

STLI�

R/W

0

1

STLI1

R/W

0

0

STLI0

R/W

0

STLI7 ~ STLI0

: FIFO IN stall endpoints indication bits

0: not stall

1: stall

The STLI register shows if the corresponding endpoint has worked properly or not. As soon as endpoint improper operation occurs, the related bit in the STLI register has to be set high. The STLI register bits will be cleared by a USB reset signal and a setup token event.

SIES Register

Bit

Na�e

R/W

POR

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

7

NMI

R/W

0

6

CRCF

R/W

0

R

0

5

4

NAK

R

0

R

0

3

IN

2

OUT

R/W

0

1

ERR

R/W

0

0

ASET

R/W

0

NMI

: NAK token interrupt mask flag

0: interrupt enable

1: interrupt disable

If this bit set, when the device sent a NAK token to the host, an interrupt will be disabled. Otherwise if this bit is cleared, when the device sends a NAK token to the host, it will enter the interrupt sub-routine. This bit is used for all endpoint.

CRCF

: CRC error detection flag

0: no error

1: error

This bit will be set to "1" when there are the following three conditions happened:

CRC error, PID error, Bit stuffing error. This bit is set by SIE and cleared by F/W.

"—": unimplemented, read as "0"

NAK

: ACK error detection flag

0: no error

1: error

This bit will set to "1" once SIE discover there are some error condition so the SIE is not response (NAK or ACK or DATA) for the USB token. This bit is set by SIE and cleared by F/W.

IN

: Current USB receiving signal indicator

0: low

1: high

This bit is used to indicate the current USB receiving signal from PC host is IN token.

OUT

: USB OUT token indicator

0: low

1: high

This bit is used to indicate the OUT token (except the OUT zero length token) has been received. The firmware clears this bit after the OUT data has been read. Also, this bit will be cleared by SIE after the next valid SETUP token is received.

Rev. 1.40 1�9 De�e��e� 01� �01�

Rev. 1.40

HT68FB540/HT68FB550/HT68FB560

I/O Flash USB MCU with SPI

Bit 1

Bit 0

ERR

: FIFO accessed error indicator

0: no error

1: error

This bit is used to indicate that some errors have occurred when the FIFO is accessed.

This bit is set by SIE and should be cleared by firmware. This bit is used for all endpoint.

ASET

: device address updated method control bit

0: update address after an written address to the AWR register

1: update address after PC host read out data

This bit is used to configure the SIE to automatically change the device address by the value stored in the AWR register. When this bit is set to "1" by firmware, the SIE will update the device address by the value stored in the AWR register after the PC host has successfully read the data from he device by an IN operation. Otherwise, when this bit is cleared to"0", the SIE will update the device address immediately after an address is written to the AWR register. So, in order to work properly, the firmware has to clear this bit after a next valid SETUP token is received.

MISC Register

• HT68FB540

Bit

Na�e

7

LEN0

R/W

POR

R

0

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

6 5

READY SETCMD

R

0

R/W

0

R

0

4

3

E3IDF

R/W

0

2

CLEAR

R/W

0

1

TX

R/W

0

0

REQUEST

R/W

0

LEN0

: 0-sized packet indication flag

0: not 0-sized packet

1: 0-sized packet

This bit is used to show that the host sent a 0-sized packet to the MCU. This bit must be cleared by a read action to the corresponding FIFO.

READY

: Desired FIFO ready indication flag

0: not ready

1: ready

SETCMD

: Setup command indication flag

0: not setup command

1: setup command

This bit is used to show that the data in the FIFO is a setup command. This bit is set by

Hardware and cleared by Firmware.

"—": unimplemented, read as "0"

E3IDF

: endpoint 3 input FIFO selection

0: single buffer

1: double buffer

CLEAR

: Clear FIFO function control bit

0: disable

1: enable

MCU requests to clear the FIFO, even if the FIFO is not ready. After clearing the

FIFO, the USB interface will send force_tx_err to tell the Host that data under-run if the Host wants to read data.

170 De�e��e� 01� �01�

HT68FB540/HT68FB550/HT68FB560

I/O Flash USB MCU with SPI

Rev. 1.40 171 De�e��e� 01� �01�

HT68FB540/HT68FB550/HT68FB560

I/O Flash USB MCU with SPI

Rev. 1.40

170 De�e��e� 01� �01�

HT68FB540/HT68FB550/HT68FB560

I/O Flash USB MCU with SPI

Rev. 1.40

Bit 1

Bit 0

TX

: data writing to FIFO status indication flag

0: data writing finished

1: data writing to FIFO

To represent the direction and transition end MCU access. When set to logic 1, the

MCU desires to write data to the FIFO. After finishing, this bit must be set to logic 0 before terminating request to represent transition end. For an MCU read operation, this bit must be set to logic 0 and set to logic 1 after finishing.

REQUEST

: Desired FIFO request status indication flag

0: no request

1: request

After setting the status of the desired one, FIFO can be requested by setting this bit high.After finishing, this bit must be set low.

• HT68FB550/HT68FB560

Bit

Na�e

7

LEN0

6 5 4

READY SETCMD E4ODF

R/W

POR

R

0

R

0

R/W

0

R/W

0

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

3

E3IDF

R/W

0

2

CLEAR

R/W

0

1

TX

R/W

0

0

REQUEST

R/W

0

LEN0

: 0-sized packet indication flag

0: not 0-sized packet

1: 0-sized packet

This bit is used to show that the host sent a 0-sized packet to the MCU. This bit must be cleared by a read action to the corresponding FIFO.

READY

: Desired FIFO ready indication flag

0: not ready

1: ready

SETCMD

: Setup command indication flag

0: not setup command

1: setup command

This bit is used to show that the data in the FIFO is a setup command. This bit is set by

Hardware and cleared by Firmware.

E4ODF

: endpoint 4 output FIFO selection

0: single buffer

1: double buffer

E3IDF

: endpoint 3 input FIFO selection

0: single buffer

1: double buffer

CLEAR

: Clear FIFO function control bit

0: disable

1: enable

MCU requests to clear the FIFO, even if the FIFO is not ready. After clearing the

FIFO, the USB interface will send force_tx_err to tell the Host that data under-run if the Host wants to read data.

TX

: data writing to FIFO status indication flag

0: data writing finished

1: data writing to FIFO

To represent the direction and transition end MCU access. When set to logic 1, the

MCU desires to write data to the FIFO. After finishing, this bit must be set to logic 0 before terminating request to represent transition end. For an MCU read operation, this bit must be set to logic 0 and set to logic 1 after finishing.

REQUEST

: Desired FIFO request status indication flag

0: no request

1: request

After setting the status of the desired one, FIFO can be requested by setting this bit high.After finishing, this bit must be set low.

171 De�e��e� 01� �01�

Rev. 1.40

HT68FB540/HT68FB550/HT68FB560

I/O Flash USB MCU with SPI

UFOEN Register

• HT68FB540

Bit

Na�e

R/W

POR

7

R

0

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

6

R

0

5

R

0

Bit 7~4

Bit 3

Bit 2

Bit 1

Bit 0

• HT68FB550

Bit

Na�e

R/W

POR

R

0

7

"—": unimplemented, read as "0"

SETO3

: EP3 output FIFO control bit

0: disable

1: enable

SETO2

: EP2 output FIFO control bit

0: disable

1: enable

SETO1

: EP1 output FIFO control bit

0: disable

1: enable

DATATG

: DATA token toggle bit

0: low

1: high

R

0

6

5

SETO5

R/W

0

4

SETO4

R/W

0

Bit 7 ~ 6

Bit 5

"—": unimplemented, read as "0"

SETO5

: EP5 output FIFO control bit

0: disable

1: enable

SETO4

: EP4 output FIFO control bit

0: disable

1: enable

SETO3

: EP3 output FIFO control bit

0: disable

1: enable

SETO2

: EP2 output FIFO control bit

0: disable

1: enable

SETO1

: EP1 output FIFO control bit

0: disable

1: enable

DATATG

: DATA token toggle bit

0: low

1: high

4

R

0

3

SETO3

R/W

0

2

SETO�

R/W

0

1

SETO1

R/W

0

0

DATATG

R/W

0

3

SETO3

R/W

0

2

SETO�

R/W

0

1

SETO1

R/W

0

0

DATATG

R/W

0

17� De�e��e� 01� �01�

HT68FB540/HT68FB550/HT68FB560

I/O Flash USB MCU with SPI

Rev. 1.40 173 De�e��e� 01� �01�

HT68FB540/HT68FB550/HT68FB560

I/O Flash USB MCU with SPI

Rev. 1.40

17� De�e��e� 01� �01�

HT68FB540/HT68FB550/HT68FB560

I/O Flash USB MCU with SPI

• HT68FB560

Bit

Na�e

7

SETO7

R/W

POR

R/W

0

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

6

SETO�

R/W

0

5

SETO5

R/W

0

4

SETO4

R/W

0

SETO7

: EP7 output FIFO control bit

0: disable

1: enable

SETO6

: EP6 output FIFO control bit

0: disable

1: enable

SETO5

: EP5 output FIFO control bit

0: disable

1: enable

SETO4

: EP4 output FIFO control bit

0: disable

1: enable

SETO3

: EP3 output FIFO control bit

0: disable

1: enable

SETO2

: EP2 output FIFO control bit

0: disable

1: enable

SETO1

: EP1 output FIFO control bit

0: disable

1: enable

DATATG

: DATA token toggle bit

0: low

1: high

3

SETO3

R/W

0

2

SETO�

R/W

0

1

SETO1

R/W

0

0

DATATG

R/W

0

UFIEN Register

• HT68FB540

Bit

Na�e

R/W

POR

7

R

0

Bit 7~4

Bit 3

Bit 2

Bit 1

Bit 0

6

R

0

5

R

0

4

R

0

3

SETI3

R/W

0

2

SETI�

R/W

0

1

SETI1

R/W

0

0

FIFO_def

R/W

0

"—": unimplemented, read as "0"

SETI3

: EP3 input FIFO control bit

0: disable

1: enable

SETI2

: EP2 input FIFO control bit

0: disable

1: enable

SETI1

: EP1 input FIFO control bit

0: disable

1: enable

FIFO_def

: FIFO configuration redefined control bit

0: disable

1: enable

If this bit is set to "1", the SIE should redefine the FIFO configuration. This bit will be automatically cleared by SIE.

Rev. 1.40 173 De�e��e� 01� �01�

Rev. 1.40

HT68FB540/HT68FB550/HT68FB560

I/O Flash USB MCU with SPI

• HT68FB550

Bit

Na�e

R/W

POR

R

0

7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

R

0

6

5

SETI5

R/W

0

Bit 7~6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

"—": unimplemented, read as "0"

SETI5

: EP5 input FIFO control bit

0: disable

1: enable

SETI4

: EP4 input FIFO control bit

0: disable

1: enable

SETI3

: EP3 input FIFO control bit

0: disable

1: enable

SETI2

: EP2 input FIFO control bit

0: disable

1: enable

SETI1

: EP1 input FIFO control bit

0: disable

1: enable

FIFO_def

: FIFO configuration redefined control bit

0: disable

1: enable

If this bit is set to "1", the SIE should redefine the FIFO configuration. This bit will be automatically cleared by SIE.

• HT68FB560

Bit

Na�e

R/W

7

SETI7

R/W

POR 0

6

SETI�

R/W

0

5

SETI5

R/W

0

4

SETI4

R/W

0

3

SETI3

R/W

0

2

SETI�

R/W

0

1

SETI1

R/W

0

0

FIFO_def

R/W

0

Bit 7

SETI7

: EP7 input FIFO control bit

0: disable

1: enable

SETI6

: EP6 input FIFO control bit

0: disable

1: enable

SETI5

: EP5 input FIFO control bit

0: disable

1: enable

SETI4

: EP4 input FIFO control bit

0: disable

1: enable

SETI3

: EP3 input FIFO control bit

0: disable

1: enable

SETI2

: EP2 input FIFO control bit

0: disable

1: enable

4

SETI4

R/W

0

3

SETI3

R/W

0

2

SETI�

R/W

0

1

SETI1

R/W

0

0

FIFO_def

R/W

0

174 De�e��e� 01� �01�

HT68FB540/HT68FB550/HT68FB560

I/O Flash USB MCU with SPI

Rev. 1.40 175 De�e��e� 01� �01�

HT68FB540/HT68FB550/HT68FB560

I/O Flash USB MCU with SPI

Rev. 1.40

174 De�e��e� 01� �01�

HT68FB540/HT68FB550/HT68FB560

I/O Flash USB MCU with SPI

Bit 1

Bit 0

SETI1

: EP1 input FIFO control bit

0: disable

1: enable

FIFO_def

: FIFO configuration redefined control bit

0: disable

1: enable

If this bit is set to "1", the SIE should redefine the FIFO configuration. This bit will be automatically cleared by SIE.

UFC0 Register

Bit

Na�e

R/W

POR

Bit 7~6

Bit 5~4

Bit 3~2

Bit 1~0:

7

E3FS1

R/W

0

6

E3FS0

R/W

0

5

E�FS1

R/W

0

4

E�FS0

R/W

0

E3FS1, E3SF0

: endpoint 3 FIFO size selection

00: 8-byte

01: 16-byte

10: 32-byte

11: 64-byte

E2FS1, E2SF0

: endpoint 2 FIFO size selection

00: 8-byte

01: 16-byte

10: 32-byte

11: 64-byte

E1FS1, E1SF0

: endpoint 1 FIFO size selection

00: 8-byte

01: 16-byte

10: 32-byte

11: 64-byte

"—": unimplemented, read as "0"

3

E1FS1

R/W

0

2

E1FS0

R/W

0

R

0

1

R

0

0

UFC1 Register

• HT68FB550

Bit

Na�e

R/W

POR

R

0

7

Bit 7~4 :

Bit 3~2

Bit 1~0

R

0

6

R

0

5

R

0

4

"—": unimplemented, read as "0"

E5FS1, E5SF0

: endpoint 5 FIFO size selection

00: 8-byte

01: 16-byte

10: 32-byte

11: 64-byte

E4FS1, E4SF0

: endpoint 4 FIFO size selection

00: 8-byte

01: 16-byte

10: 32-byte

11: 64-byte

3

E5FS1

R/W

0

2

E5FS0

R/W

0

1

E4FS1

R/W

0

0

E4FS0

R/W

0

Rev. 1.40 175 De�e��e� 01� �01�

Rev. 1.40

HT68FB540/HT68FB550/HT68FB560

I/O Flash USB MCU with SPI

• HT68FB560

Bit

Na�e

7

E7FS1

R/W

POR

R/W

0

Bit 7~6

Bit 5~4

Bit 3~2

Bit 1~0

6

E7FS0

R/W

0

5

E�FS1

R/W

0

4

E�FS0

R/W

0

E7FS1, E7SF0

: endpoint 7 FIFO size selection

00: 8-byte

01: 16-byte

10: 32-byte

11: 64-byte

E6FS1, E6SF0

: endpoint 6 FIFO size selection

00: 8-byte

01: 16-byte

10: 32-byte

11: 64-byte

E5FS1, E5SF0

: endpoint 5 FIFO size selection

00: 8-byte

01: 16-byte

10: 32-byte

11: 64-byte

E4FS1, E4SF0

: endpoint 4 FIFO size selection

00: 8-byte

01: 16-byte

10: 32-byte

11: 64-byte

3

E5FS1

R/W

0

USB endpoint accessing registers

• HT68FB540

Register

Name

FIFO0

FIFO1

FIFO�

FIFO3

7

D7

D7

D7

D7

6

D�

D�

D�

D�

5

D5

D5

D5

D5

4

D4

D4

D4

D4

Bit

3

D3

D3

D3

D3

• HT68FB550

Register

Name

FIFO0

FIFO1

FIFO�

FIFO3

FIFO4

FIFO5

7

D7

D7

D7

D7

D7

D7

6

D�

D�

D�

D�

D�

D�

5

D5

D5

D5

D5

D5

D5

4

D4

D4

D4

D4

D4

D4

Bit

3

D3

D3

D3

D3

D3

D3

2

E5FS0

R/W

0

2

D�

D�

D�

D�

2

D�

D�

D�

D�

D�

D�

1

E4FS1

R/W

0

0

E4FS0

R/W

0

1

D1

D1

D1

D1

D1

D1

1

D1

D1

D1

D1

0

D0

D0

D0

D0

0

D0

D0

D0

D0

D0

D0

17� De�e��e� 01� �01�

HT68FB540/HT68FB550/HT68FB560

I/O Flash USB MCU with SPI

Rev. 1.40 177 De�e��e� 01� �01�

HT68FB540/HT68FB550/HT68FB560

I/O Flash USB MCU with SPI

HT68FB540/HT68FB550/HT68FB560

I/O Flash USB MCU with SPI

FIFO0

FIFO1

FIFO�

FIFO3

FIFO4

FIFO5

FIFO�

FIFO7

• HT68FB560

Register

Name

D7

D7

D7

D7

7

D7

D7

D7

D7

D�

D�

D�

D�

6

D�

D�

D�

D�

D5

D5

D5

D5

5

D5

D5

D5

D5

D4

D4

D4

D4

4

D4

D4

D4

D4

Bit

D3

D3

D3

D3

3

D3

D3

D3

D3

D�

D�

D�

D�

2

D�

D�

D�

D�

D1

D1

D1

D1

1

D1

D1

D1

D1

Configuration Options

Configuration options refer to certain options within the MCU that are programmed into the device during the programming process. During the development process, these options are selected using the HT-IDE software development tools. As these options are programmed into the device using the hardware programming tools, once they are selected they cannot be changed later using the application program. All options must be defined for proper system function, the details of which are shown in the table.

No.

Options

Oscillator Options

1

High Speed Syste� Os�illato� Sele�tion - f

1. HIRC (Default)

�. HXT

H:

Crystal Mode Frequency Option

Clo�k Mode f�equen�y:

1. 1�MHz

�. �MHz

I/O or VDDIO Option

3

I/O o� VDDIO pin �ont�ol �it:

1. VDDIO (Default)

�. I/O (PE0)

D0

D0

D0

D0

0

D0

D0

D0

D0

Rev. 1.40

17� De�e��e� 01� �01� Rev. 1.40 177 De�e��e� 01� �01�

Application Circuits

VDD

0.1µF

VBUS

D-

D+

VSS

HVDD

VDD/UBUS

10µF

0.1µF

100k W

300 W

0.1µF

RES

VSS

33 W

UDN

UDP

33 W

47pF

47pF

V33O

0.1µF

I/O

Key Matrix Input

HT68FB540/HT68FB550/HT68FB560

I/O Flash USB MCU with SPI

VDD

SIM

SPI / I

2

C

Device

B G R

TP0

TP1

TP2

1k W

1k W

1k W

120 W

Q1

3904

65 W

Q2

3904

56 W

Q3

3904

HT68FB540/HT68FB550/HT68FB560

I/O Flash USB MCU with SPI

Rev. 1.40

178 De�e��e� 01� �01� Rev. 1.40 179 De�e��e� 01� �01�

HT68FB540/HT68FB550/HT68FB560

I/O Flash USB MCU with SPI

Rev. 1.40

178 De�e��e� 01� �01�

HT68FB540/HT68FB550/HT68FB560

I/O Flash USB MCU with SPI

Instruction Set

Introduction

Central to the successful operation of any microcontroller is its instruction set, which is a set of program instruction codes that directs the microcontroller to perform certain operations. In the case of Holtek microcontrollers, a comprehensive and flexible set of over 60 instructions is provided to enable programmers to implement their application with the minimum of programming overheads.

For easier understanding of the various instruction codes, they have been subdivided into several functional groupings.

Instruction Timing

Most instructions are implemented within one instruction cycle. The exceptions to this are branch, call, or table read instructions where two instruction cycles are required. One instruction cycle is equal to 4 system clock cycles, therefore in the case of an 8MHz system oscillator, most instructions would be implemented within 0.5µs and branch or call instructions would be implemented within

1µs. Although instructions which require one more cycle to implement are generally limited to the JMP, CALL, RET, RETI and table read instructions, it is important to realize that any other instructions which involve manipulation of the Program Counter Low register or PCL will also take one more cycle to implement. As instructions which change the contents of the PCL will imply a direct jump to that new address, one more cycle will be required. Examples of such instructions would be ″CLR PCL″ or ″MOV PCL, A″. For the case of skip instructions, it must be noted that if the result of the comparison involves a skip operation then this will also take one more cycle, if no skip is involved then only one cycle is required.

Moving and Transferring Data

The transfer of data within the microcontroller program is one of the most frequently used operations. Making use of three kinds of MOV instructions, data can be transferred from registers to the Accumulator and vice-versa as well as being able to move specific immediate data directly into the Accumulator. One of the most important data transfer applications is to receive data from the input ports and transfer data to the output ports.

Arithmetic Operations

The ability to perform certain arithmetic operations and data manipulation is a necessary feature of most microcontroller applications. Within the Holtek microcontroller instruction set are a range of add and subtract instruction mnemonics to enable the necessary arithmetic to be carried out. Care must be taken to ensure correct handling of carry and borrow data when results exceed 255 for addition and less than 0 for subtraction. The increment and decrement instructions INC, INCA, DEC and DECA provide a simple means of increasing or decreasing by a value of one of the values in the destination specified.

Rev. 1.40 179 De�e��e� 01� �01�

HT68FB540/HT68FB550/HT68FB560

I/O Flash USB MCU with SPI

Logical and Rotate Operations

The standard logical operations such as AND, OR, XOR and CPL all have their own instruction within the Holtek microcontroller instruction set. As with the case of most instructions involving data manipulation, data must pass through the Accumulator which may involve additional programming steps. In all logical data operations, the zero flag may be set if the result of the operation is zero. Another form of logical data manipulation comes from the rotate instructions such as RR, RL, RRC and RLC which provide a simple means of rotating one bit right or left. Different rotate instructions exist depending on program requirements. Rotate instructions are useful for serial port programming applications where data can be rotated from an internal register into the Carry bit from where it can be examined and the necessary serial bit set high or low. Another application where rotate data operations are used is to implement multiplication and division calculations.

Branches and Control Transfer

Program branching takes the form of either jumps to specified locations using the JMP instruction or to a subroutine using the CALL instruction. They differ in the sense that in the case of a subroutine call, the program must return to the instruction immediately when the subroutine has been carried out. This is done by placing a return instruction RET in the subroutine which will cause the program to jump back to the address right after the CALL instruction. In the case of a JMP instruction, the program simply jumps to the desired location. There is no requirement to jump back to the original jumping off point as in the case of the CALL instruction. One special and extremely useful set of branch instructions are the conditional branches. Here a decision is first made regarding the condition of a certain data memory or individual bits. Depending upon the conditions, the program will continue with the next instruction or skip over it and jump to the following instruction. These instructions are the key to decision making and branching within the program perhaps determined by the condition of certain input switches or by the condition of internal data bits.

Bit Operations

The ability to provide single bit operations on Data Memory is an extremely flexible feature of all

Holtek microcontrollers. This feature is especially useful for output port bit programming where individual bits or port pins can be directly set high or low using either the ″SET [m].i″ or ″CLR [m].i″ instructions respectively. The feature removes the need for programmers to first read the 8-bit output port, manipulate the input data to ensure that other bits are not changed and then output the port with the correct new data. This read-modify-write process is taken care of automatically when these bit operation instructions are used.

Table Read Operations

Data storage is normally implemented by using registers. However, when working with large amounts of fixed data, the volume involved often makes it inconvenient to store the fixed data in the Data Memory. To overcome this problem, Holtek microcontrollers allow an area of Program

Memory to be setup as a table where data can be directly stored. A set of easy to use instructions provides the means by which this fixed data can be referenced and retrieved from the Program

Memory.

Other Operations

In addition to the above functional instructions, a range of other instructions also exist such as the ″HALT″ instruction for Power-down operations and instructions to control the operation of the Watchdog Timer for reliable program operations under extreme electric or electromagnetic environments. For their relevant operations, refer to the functional related sections.

Rev. 1.40

180 De�e��e� 01� �01�

HT68FB540/HT68FB550/HT68FB560

I/O Flash USB MCU with SPI

Rev. 1.40 181 De�e��e� 01� �01�

HT68FB540/HT68FB550/HT68FB560

I/O Flash USB MCU with SPI

Rev. 1.40

180 De�e��e� 01� �01�

HT68FB540/HT68FB550/HT68FB560

I/O Flash USB MCU with SPI

Instruction Set Summary

The following table depicts a summary of the instruction set categorised according to function and can be consulted as a basic instruction reference using the following listed conventions.

Table conventions: x: Bits immediate data m: Data Memory address

A: Accumulator i: 0~7 number of bits addr: Program memory address

Mnemonic

Arithmetic

ADD A�[�]

ADDM A�[�]

ADD A�x

ADC A�[�]

ADCM A�[�]

SUB A�x

SUB A�[�]

SUBM A�[�]

SBC A�[�]

SBCM A�[�]

DAA [�]

Logic Operation

Description

Add Data Me�o�y to ACC

Add ACC to Data Me�o�y

Add i��ediate data to ACC

Add Data Me�o�y to ACC with Ca��y

Add ACC to Data �e�o�y with Ca��y

Su�t�a�t i��ediate data f�o� the ACC

Su�t�a�t Data Me�o�y f�o� ACC

Su�t�a�t Data Me�o�y f�o� ACC with �esult in Data Me�o�y

Su�t�a�t Data Me�o�y f�o� ACC with Ca��y

Su�t�a�t Data Me�o�y f�o� ACC with Ca��y� �esult in Data Me�o�y

De�i�al adjust ACC fo� Addition with �esult in Data Me�o�y

AND A�[�]

OR A�[�]

XOR A�[�]

ANDM A�[�]

ORM A�[�]

XORM A�[�]

AND A�x

OR A�x

XOR A�x

CPL [�]

CPLA [�]

Logi�al AND Data Me�o�y to ACC

Logi�al OR Data Me�o�y to ACC

Logi�al XOR Data Me�o�y to ACC

Logi�al AND ACC to Data Me�o�y

Logi�al OR ACC to Data Me�o�y

Logi�al XOR ACC to Data Me�o�y

Logi�al AND i��ediate Data to ACC

Logi�al OR i��ediate Data to ACC

Logi�al XOR i��ediate Data to ACC

Co�ple�ent Data Me�o�y

Co�ple�ent Data Me�o�y with �esult in ACC

Increment & Decrement

INCA [�]

INC [�]

DECA [�]

DEC [�]

In��e�ent Data Me�o�y with �esult in ACC

In��e�ent Data Me�o�y

De��e�ent Data Me�o�y with �esult in ACC

De��e�ent Data Me�o�y

Rotate

RRA [�]

RR [�]

RRCA [�]

RRC [�]

RLA [�]

RL [�]

RLCA [�]

RLC [�]

Data Move

MOV A�[�]

MOV [�]�A

MOV A�x

Bit Operation

CLR [�].i

SET [�].i

Rotate Data Me�o�y �ight with �esult in ACC

Rotate Data Me�o�y �ight

Rotate Data Me�o�y �ight th�ough Ca��y with �esult in ACC

Rotate Data Me�o�y �ight th�ough Ca��y

Rotate Data Me�o�y left with �esult in ACC

Rotate Data Me�o�y left

Rotate Data Me�o�y left th�ough Ca��y with �esult in ACC

Rotate Data Me�o�y left th�ough Ca��y

Move Data Me�o�y to ACC

Move ACC to Data Me�o�y

Move i��ediate data to ACC

Clea� �it of Data Me�o�y

Set �it of Data Me�o�y

Cycles

1

1

1

1

Note

1Note

1Note

1

1

1

1Note

1

1

1

Note

1

1

1

Note

1

1

1

Note

1

1

Note

1

Note

1

1

Note

1

1Note

1

1

Note

1

1

Note

1

1

Note

1

1

Note

1

1

Note

1

1 Note

1

Note

Flag Affected

Z

Z

Z

Z

Z

Z

Z

Z

Z

Z

Z

Z� C� AC� OV

Z� C� AC� OV

Z� C� AC� OV

Z� C� AC� OV

Z� C� AC� OV

Z� C� AC� OV

Z� C� AC� OV

Z� C� AC� OV

Z� C� AC� OV

Z� C� AC� OV

C

Z

Z

Z

Z

None

None

C

C

None

None

C

C

None

None

None

None

None

Rev. 1.40 181 De�e��e� 01� �01�

HT68FB540/HT68FB550/HT68FB560

I/O Flash USB MCU with SPI

Mnemonic

Branch

JMP add�

SZ [�]

SZA [�]

SZ [�].i

SNZ [�].i

SIZ [�]

SDZ [�]

SIZA [�]

SDZA [�]

CALL add�

RET

RET A�x

RETI

Table Read

TABRD [�]

Miscellaneous

NOP

CLR [�]

SET [�]

CLR WDT

CLR WDT1

CLR WDT�

SWAP [�]

SWAPA [�]

HALT

Description

Ju�p un�onditionally

Skip if Data Me�o�y is ze�o

Skip if Data Me�o�y is ze�o with data �ove�ent to ACC

Skip if �it i of Data Me�o�y is ze�o

Skip if �it i of Data Me�o�y is not ze�o

Skip if in��e�ent Data Me�o�y is ze�o

Skip if de��e�ent Data Me�o�y is ze�o

Skip if in��e�ent Data Me�o�y is ze�o with �esult in ACC

Skip if de��e�ent Data Me�o�y is ze�o with �esult in ACC

Su��outine �all

Retu�n f�o� su��outine

Retu�n f�o� su��outine and load i��ediate data to ACC

Retu�n f�o� inte��upt

Read ta�le (�u��ent page) to TBLH and Data Me�o�y

No ope�ation

Clea� Data Me�o�y

Set Data Me�o�y

Clea� Wat�hdog Ti�e�

P�e-�lea� Wat�hdog Ti�e�

P�e-�lea� Wat�hdog Ti�e�

Swap ni��les of Data Me�o�y

Swap ni��les of Data Me�o�y with �esult in ACC

Ente� powe� down �ode

Cycles

1

Note

1 Note

1

Note

1

Note

1 note

1

Note

1

Note

1

Note

Note

1

1

Note

1 Note

1

1

1

1

Note

1

1

Flag Affected

None

None

None

None

TO� PDF

TO� PDF

TO� PDF

None

None

TO� PDF

Note: 1. For skip instructions, if the result of the comparison involves a skip then two cycles are required, if no skip takes place only one cycle is required.

2. Any instruction which changes the contents of the PCL will also require 2 cycles for execution.

3. For the ″CLR WDT1″ and ″CLR WDT2″ instructions the TO and PDF flags may be affected by the execution status. The TO and PDF flags are cleared after both ″CLR WDT1″ and ″CLR WDT2″ instructions are consecutively executed. Otherwise the TO and PDF flags remain unchanged.

None

None

None

None

None

None

None

None

None

None

None

None

None

HT68FB540/HT68FB550/HT68FB560

I/O Flash USB MCU with SPI

Rev. 1.40

18� De�e��e� 01� �01� Rev. 1.40 183 De�e��e� 01� �01�

HT68FB540/HT68FB550/HT68FB560

I/O Flash USB MCU with SPI

Rev. 1.40

18� De�e��e� 01� �01�

HT68FB540/HT68FB550/HT68FB560

I/O Flash USB MCU with SPI

Instruction Definition

ADDM A,[m]

Description

Operation

Affected flag(s)

AND A,[m]

Description

Operation

Affected flag(s)

AND A,x

Description

Operation

Affected flag(s)

ANDM A,[m]

Description

Operation

Affected flag(s)

ADC A,[m]

Description

Operation

Affected flag(s)

ADCM A,[m]

Description

Operation

Affected flag(s)

ADD A,[m]

Description

Operation

Affected flag(s)

ADD A,x

Description

Operation

Affected flag(s)

Add Data Memory to ACC with Carry

The contents of the specified Data Memory, Accumulator and the carry flag are added.

The result is stored in the Accumulator.

ACC ← ACC + [m] + C

OV, Z, AC, C

Add ACC to Data Memory with Carry

The contents of the specified Data Memory, Accumulator and the carry flag are added.

The result is stored in the specified Data Memory.

[m] ← ACC + [m] + C

OV, Z, AC, C

Add Data Memory to ACC

The contents of the specified Data Memory and the Accumulator are added.

The result is stored in the Accumulator.

ACC ← ACC + [m]

OV, Z, AC, C

Add immediate data to ACC

The contents of the Accumulator and the specified immediate data are added.

The result is stored in the Accumulator.

ACC ← ACC + x

OV, Z, AC, C

Add ACC to Data Memory

The contents of the specified Data Memory and the Accumulator are added.

The result is stored in the specified Data Memory.

[m] ← ACC + [m]

OV, Z, AC, C

Logical AND Data Memory to ACC

Data in the Accumulator and the specified Data Memory perform a bitwise logical AND operation. The result is stored in the Accumulator.

ACC ← ACC ″AND″ [m]

Z

Logical AND immediate data to ACC

Data in the Accumulator and the specified immediate data perform a bit wise logical AND operation. The result is stored in the Accumulator.

ACC ← ACC ″AND″ x

Z

Logical AND ACC to Data Memory

Data in the specified Data Memory and the Accumulator perform a bitwise logical AND operation. The result is stored in the Data Memory.

[m] ← ACC ″AND″ [m]

Z

Rev. 1.40 183 De�e��e� 01� �01�

HT68FB540/HT68FB550/HT68FB560

I/O Flash USB MCU with SPI

CLR WDT

Description

Operation

Affected flag(s)

CLR WDT1

Description

Operation

Affected flag(s)

CLR WDT2

Description

Operation

Affected flag(s)

CPL [m]

Description

Operation

Affected flag(s)

CALL addr

Description

Operation

Affected flag(s)

CLR [m]

Description

Operation

Affected flag(s)

CLR [m].i

Description

Operation

Affected flag(s)

Subroutine call

Unconditionally calls a subroutine at the specified address. The Program Counter then increments by 1 to obtain the address of the next instruction which is then pushed onto the stack. The specified address is then loaded and the program continues execution from this new address. As this instruction requires an additional operation, it is a two cycle instruction.

Stack ← Program Counter + 1

Program Counter ← addr

None

Clear Data Memory

Each bit of the specified Data Memory is cleared to 0.

[m] ← 00H

None

Clear bit of Data Memory

Bit i of the specified Data Memory is cleared to 0.

[m].i ← 0

None

Clear Watchdog Timer

The TO, PDF flags and the WDT are all cleared.

WDT cleared

TO ← 0

PDF ← 0

TO, PDF

Pre-clear Watchdog Timer

The TO, PDF flags and the WDT are all cleared. Note that this instruction works in conjunction with CLR WDT2 and must be executed alternately with CLR WDT2 to have effect. Repetitively executing this instruction without alternately executing CLR WDT2 will have no effect.

WDT cleared

TO ← 0

PDF ← 0

TO, PDF

Pre-clear Watchdog Timer

The TO, PDF flags and the WDT are all cleared. Note that this instruction works in conjunction with CLR WDT1 and must be executed alternately with CLR WDT1 to have effect.

Repetitively executing this instruction without alternately executing CLR WDT1 will have no effect.

WDT cleared

TO ← 0

PDF ← 0

TO, PDF

Complement Data Memory

Each bit of the specified Data Memory is logically complemented (1′s complement). Bits which previously contained a 1 are changed to 0 and vice versa.

[m] ← [m]

Z

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HT68FB540/HT68FB550/HT68FB560

I/O Flash USB MCU with SPI

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I/O Flash USB MCU with SPI

CPLA [m]

Description

Operation

Affected flag(s)

DAA [m]

Description

Operation

Affected flag(s)

DEC [m]

Description

Operation

Affected flag(s)

DECA [m]

Description

Operation

Affected flag(s)

HALT

Description

Operation

Affected flag(s)

INC [m]

Description

Operation

Affected flag(s)

INCA [m]

Description

Operation

Affected flag(s)

Complement Data Memory with result in ACC

Each bit of the specified Data Memory is logically complemented (1′s complement). Bits which previously contained a 1 are changed to 0 and vice versa. The complemented result is stored in the Accumulator and the contents of the Data Memory remain unchanged.

ACC ← [m]

Z

Decimal-Adjust ACC for addition with result in Data Memory

Convert the contents of the Accumulator value to a BCD (Binary Coded Decimal) value resulting from the previous addition of two BCD variables. If the low nibble is greater than 9 or if AC flag is set, then a value of 6 will be added to the low nibble. Otherwise the low nibble remains unchanged. If the high nibble is greater than 9 or if the C flag is set, then a value of 6 will be added to the high nibble. Essentially, the decimal conversion is performed by adding

00H, 06H, 60H or 66H depending on the Accumulator and flag conditions. Only the C flag may be affected by this instruction which indicates that if the original BCD sum is greater than

100, it allows multiple precision decimal addition.

[m] ← ACC + 00H or

[m] ← ACC + 06H or

[m] ← ACC + 60H or

[m] ← ACC + 66H

C

Decrement Data Memory

Data in the specified Data Memory is decremented by 1.

[m] ← [m] − 1

Z

Decrement Data Memory with result in ACC

Data in the specified Data Memory is decremented by 1. The result is stored in the

Accumulator. The contents of the Data Memory remain unchanged.

ACC ← [m] − 1

Z

Enter power down mode

This instruction stops the program execution and turns off the system clock. The contents of the Data Memory and registers are retained. The WDT and prescaler are cleared. The power down flag PDF is set and the WDT time-out flag TO is cleared.

TO ← 0

PDF ← 1

TO, PDF

Increment Data Memory

Data in the specified Data Memory is incremented by 1.

[m] ← [m] + 1

Z

Increment Data Memory with result in ACC

Data in the specified Data Memory is incremented by 1. The result is stored in the Accumulator.

The contents of the Data Memory remain unchanged.

ACC ← [m] + 1

Z

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HT68FB540/HT68FB550/HT68FB560

I/O Flash USB MCU with SPI

MOV [m],A

Description

Operation

Affected flag(s)

NOP

Description

Operation

Affected flag(s)

OR A,[m]

Description

Operation

Affected flag(s)

OR A,x

Description

Operation

Affected flag(s)

ORM A,[m]

Description

Operation

Affected flag(s)

RET

Description

Operation

Affected flag(s)

JMP addr

Description

Operation

Affected flag(s)

MOV A,[m]

Description

Operation

Affected flag(s)

MOV A,x

Description

Operation

Affected flag(s)

Jump unconditionally

The contents of the Program Counter are replaced with the specified address. Program execution then continues from this new address. As this requires the insertion of a dummy instruction while the new address is loaded, it is a two cycle instruction.

Program Counter ← addr

None

Move Data Memory to ACC

The contents of the specified Data Memory are copied to the Accumulator.

ACC ← [m]

None

Move immediate data to ACC

The immediate data specified is loaded into the Accumulator.

ACC ← x

None

Move ACC to Data Memory

The contents of the Accumulator are copied to the specified Data Memory.

[m] ← ACC

None

No operation

No operation is performed. Execution continues with the next instruction.

No operation

None

Logical OR Data Memory to ACC

Data in the Accumulator and the specified Data Memory perform a bitwise logical OR operation. The result is stored in the Accumulator.

ACC ← ACC ″OR″ [m]

Z

Logical OR immediate data to ACC

Data in the Accumulator and the specified immediate data perform a bitwise logical OR operation. The result is stored in the Accumulator.

ACC ← ACC ″OR″ x

Z

Logical OR ACC to Data Memory

Data in the specified Data Memory and the Accumulator perform a bitwise logical OR operation. The result is stored in the Data Memory.

[m] ← ACC ″OR″ [m]

Z

Return from subroutine

The Program Counter is restored from the stack. Program execution continues at the restored address.

Program Counter ← Stack

None

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HT68FB540/HT68FB550/HT68FB560

I/O Flash USB MCU with SPI

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I/O Flash USB MCU with SPI

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I/O Flash USB MCU with SPI

RET A,x

Description

Operation

Affected flag(s)

RETI

Description

Operation

Affected flag(s)

RL [m]

Description

Operation

Affected flag(s)

RLA [m]

Description

Operation

Affected flag(s)

RLC [m]

Description

Operation

Affected flag(s)

RLCA [m]

Description

Operation

Affected flag(s)

RR [m]

Description

Operation

Affected flag(s)

Return from subroutine and load immediate data to ACC

The Program Counter is restored from the stack and the Accumulator loaded with the specified immediate data. Program execution continues at the restored address.

Program Counter ← Stack

ACC ← x

None

Return from interrupt

The Program Counter is restored from the stack and the interrupts are re-enabled by setting the

EMI bit. EMI is the master interrupt global enable bit. If an interrupt was pending when the

RETI instruction is executed, the pending Interrupt routine will be processed before returning to the main program.

Program Counter ← Stack

EMI ← 1

None

Rotate Data Memory left

The contents of the specified Data Memory are rotated left by 1 bit with bit 7 rotated into bit 0.

[m].(i+1) ← [m].i; (i = 0~6)

[m].0 ← [m].7

None

Rotate Data Memory left with result in ACC

The contents of the specified Data Memory are rotated left by 1 bit with bit 7 rotated into bit 0.

The rotated result is stored in the Accumulator and the contents of the Data Memory remain unchanged.

ACC.(i+1) ← [m].i; (i = 0~6)

ACC.0 ← [m].7

None

Rotate Data Memory left through Carry

The contents of the specified Data Memory and the carry flag are rotated left by 1 bit. Bit 7 replaces the Carry bit and the original carry flag is rotated into bit 0.

[m].(i+1) ← [m].i; (i = 0~6)

[m].0 ← C

C ← [m].7

C

Rotate Data Memory left through Carry with result in ACC

Data in the specified Data Memory and the carry flag are rotated left by 1 bit. Bit 7 replaces the

Carry bit and the original carry flag is rotated into the bit 0. The rotated result is stored in the

Accumulator and the contents of the Data Memory remain unchanged.

ACC.(i+1) ← [m].i; (i = 0~6)

ACC.0 ← C

C ← [m].7

C

Rotate Data Memory right

The contents of the specified Data Memory are rotated right by 1 bit with bit 0 rotated into bit 7.

[m].i ← [m].(i+1); (i = 0~6)

[m].7 ← [m].0

None

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HT68FB540/HT68FB550/HT68FB560

I/O Flash USB MCU with SPI

RRA [m]

Description

Operation

Affected flag(s)

RRC [m]

Description

Operation

Affected flag(s)

RRCA [m]

Description

Operation

Affected flag(s)

SBC A,[m]

Description

Operation

Affected flag(s)

SBCM A,[m]

Description

Operation

Affected flag(s)

SDZ [m]

Description

Operation

Affected flag(s)

Rotate Data Memory right with result in ACC

Data in the specified Data Memory and the carry flag are rotated right by 1 bit with bit 0 rotated into bit 7. The rotated result is stored in the Accumulator and the contents of the

Data Memory remain unchanged.

ACC.i ← [m].(i+1); (i = 0~6)

ACC.7 ← [m].0

None

Rotate Data Memory right through Carry

The contents of the specified Data Memory and the carry flag are rotated right by 1 bit. Bit 0 replaces the Carry bit and the original carry flag is rotated into bit 7.

[m].i ← [m].(i+1); (i = 0~6)

[m].7 ← C

C ← [m].0

C

Rotate Data Memory right through Carry with result in ACC

Data in the specified Data Memory and the carry flag are rotated right by 1 bit. Bit 0 replaces the Carry bit and the original carry flag is rotated into bit 7. The rotated result is stored in the

Accumulator and the contents of the Data Memory remain unchanged.

ACC.i ← [m].(i+1); (i = 0~6)

ACC.7 ← C

C ← [m].0

C

Subtract Data Memory from ACC with Carry

The contents of the specified Data Memory and the complement of the carry flag are subtracted from the Accumulator. The result is stored in the Accumulator. Note that if the result of subtraction is negative, the C flag will be cleared to 0, otherwise if the result is positive or zero, the C flag will be set to 1.

ACC ← ACC − [m] − C

OV, Z, AC, C

Subtract Data Memory from ACC with Carry and result in Data Memory

The contents of the specified Data Memory and the complement of the carry flag are subtracted from the Accumulator. The result is stored in the Data Memory. Note that if the result of subtraction is negative, the C flag will be cleared to 0, otherwise if the result is positive or zero, the C flag will be set to 1.

[m] ← ACC − [m] − C

OV, Z, AC, C

Skip if decrement Data Memory is 0

The contents of the specified Data Memory are first decremented by 1. If the result is 0 the following instruction is skipped. As this requires the insertion of a dummy instruction while the next instruction is fetched, it is a two cycle instruction. If the result is not 0 the program proceeds with the following instruction.

[m] ← [m] − 1

Skip if [m] = 0

None

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I/O Flash USB MCU with SPI

SDZA [m]

Description

Operation

Affected flag(s)

SET [m]

Description

Operation

Affected flag(s)

SET [m].i

Description

Operation

Affected flag(s)

SIZ [m]

Description

Operation

Affected flag(s)

SIZA [m]

Description

Operation

Affected flag(s)

SNZ [m].i

Description

Operation

Affected flag(s)

SUB A,[m]

Description

Operation

Affected flag(s)

Skip if decrement Data Memory is zero with result in ACC

The contents of the specified Data Memory are first decremented by 1. If the result is 0, the following instruction is skipped. The result is stored in the Accumulator but the specified

Data Memory contents remain unchanged. As this requires the insertion of a dummy instruction while the next instruction is fetched, it is a two cycle instruction. If the result is not 0, the program proceeds with the following instruction.

ACC ← [m] − 1

Skip if ACC = 0

None

Set Data Memory

Each bit of the specified Data Memory is set to 1.

[m] ← FFH

None

Set bit of Data Memory

Bit i of the specified Data Memory is set to 1.

[m].i ← 1

None

Skip if increment Data Memory is 0

The contents of the specified Data Memory are first incremented by 1. If the result is 0, the following instruction is skipped. As this requires the insertion of a dummy instruction while the next instruction is fetched, it is a two cycle instruction. If the result is not 0 the program proceeds with the following instruction.

[m] ← [m] + 1

Skip if [m] = 0

None

Skip if increment Data Memory is zero with result in ACC

The contents of the specified Data Memory are first incremented by 1. If the result is 0, the following instruction is skipped. The result is stored in the Accumulator but the specified

Data Memory contents remain unchanged. As this requires the insertion of a dummy instruction while the next instruction is fetched, it is a two cycle instruction. If the result is not

0 the program proceeds with the following instruction.

ACC ← [m] + 1

Skip if ACC = 0

None

Skip if bit i of Data Memory is not 0

If bit i of the specified Data Memory is not 0, the following instruction is skipped. As this requires the insertion of a dummy instruction while the next instruction is fetched, it is a two cycle instruction. If the result is 0 the program proceeds with the following instruction.

Skip if [m].i ≠ 0

None

Subtract Data Memory from ACC

The specified Data Memory is subtracted from the contents of the Accumulator. The result is stored in the Accumulator. Note that if the result of subtraction is negative, the C flag will be cleared to 0, otherwise if the result is positive or zero, the C flag will be set to 1.

ACC ← ACC − [m]

OV, Z, AC, C

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I/O Flash USB MCU with SPI

SUBM A,[m]

Description

Operation

Affected flag(s)

SUB A,x

Description

Operation

Affected flag(s)

SWAP [m]

Description

Operation

Affected flag(s)

SWAPA [m]

Description

Operation

Affected flag(s)

SZ [m]

Description

Operation

Affected flag(s)

SZA [m]

Description

Operation

Affected flag(s)

SZ [m].i

Description

Operation

Affected flag(s)

Subtract Data Memory from ACC with result in Data Memory

The specified Data Memory is subtracted from the contents of the Accumulator. The result is stored in the Data Memory. Note that if the result of subtraction is negative, the C flag will be cleared to 0, otherwise if the result is positive or zero, the C flag will be set to 1.

[m] ← ACC − [m]

OV, Z, AC, C

Subtract immediate data from ACC

The immediate data specified by the code is subtracted from the contents of the Accumulator.

The result is stored in the Accumulator. Note that if the result of subtraction is negative, the C flag will be cleared to 0, otherwise if the result is positive or zero, the C flag will be set to 1.

ACC ← ACC − x

OV, Z, AC, C

Swap nibbles of Data Memory

The low-order and high-order nibbles of the specified Data Memory are interchanged.

[m].3~[m].0 ↔ [m].7 ~ [m].4

None

Swap nibbles of Data Memory with result in ACC

The low-order and high-order nibbles of the specified Data Memory are interchanged. The result is stored in the Accumulator. The contents of the Data Memory remain unchanged.

ACC.3 ~ ACC.0 ← [m].7 ~ [m].4

ACC.7 ~ ACC.4 ← [m].3 ~ [m].0

None

Skip if Data Memory is 0

If the contents of the specified Data Memory is 0, the following instruction is skipped. As this requires the insertion of a dummy instruction while the next instruction is fetched, it is a two cycle instruction. If the result is not 0 the program proceeds with the following instruction.

Skip if [m] = 0

None

Skip if Data Memory is 0 with data movement to ACC

The contents of the specified Data Memory are copied to the Accumulator. If the value is zero, the following instruction is skipped. As this requires the insertion of a dummy instruction while the next instruction is fetched, it is a two cycle instruction. If the result is not 0 the program proceeds with the following instruction.

ACC ← [m]

Skip if [m] = 0

None

Skip if bit i of Data Memory is 0

If bit i of the specified Data Memory is 0, the following instruction is skipped. As this requires the insertion of a dummy instruction while the next instruction is fetched, it is a two cycle instruction. If the result is not 0, the program proceeds with the following instruction.

Skip if [m].i = 0

None

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I/O Flash USB MCU with SPI

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I/O Flash USB MCU with SPI

HT68FB540/HT68FB550/HT68FB560

I/O Flash USB MCU with SPI

TABRD [m]

Description

Operation

Affected flag(s)

XOR A,[m]

Description

Operation

Affected flag(s)

XORM A,[m]

Description

Operation

Affected flag(s)

XOR A,x

Description

Operation

Affected flag(s)

Read table to TBLH and Data Memory

The low byte of the program code addressed by the table pointer (TBLP/TBHP) is moved to the specified Data Memory and the high byte moved to TBLH.

[m] ← program code (low byte)

TBLH ← program code (high byte)

None

Logical XOR Data Memory to ACC

Data in the Accumulator and the specified Data Memory perform a bitwise logical XOR operation. The result is stored in the Accumulator.

ACC ← ACC ″XOR″ [m]

Z

Logical XOR ACC to Data Memory

Data in the specified Data Memory and the Accumulator perform a bitwise logical XOR operation. The result is stored in the Data Memory.

[m] ← ACC ″XOR″ [m]

Z

Logical XOR immediate data to ACC

Data in the Accumulator and the specified immediate data perform a bitwise logical XOR operation. The result is stored in the Accumulator.

ACC ← ACC ″XOR″ x

Z

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HT68FB540/HT68FB550/HT68FB560

I/O Flash USB MCU with SPI

Package Information

Note that the package information provided here is for consultation purposes only. As this information may be updated at regular intervals users are reminded to consult the Holtek website for the latest version of the package/carton information .

Additional supplementary information with regard to packaging is listed below. Click on the relevant section to be transferred to the relevant website page.

• Further Package Information (include Outline Dimensions, Product Tape and Reel Specifications)

• Packing Meterials Information

• Carton information

HT68FB540/HT68FB550/HT68FB560

I/O Flash USB MCU with SPI

Rev. 1.40

19� De�e��e� 01� �01� Rev. 1.40 193 De�e��e� 01� �01�

HT68FB540/HT68FB550/HT68FB560

I/O Flash USB MCU with SPI

Rev. 1.40

19� De�e��e� 01� �01�

Symbol

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F

G

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α

A

B

C

C’

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Symbol

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C

C’

HT68FB540/HT68FB550/HT68FB560

I/O Flash USB MCU with SPI

20-pin SSOP (150mil) Outline Dimensions

Min.

0.�0

0.10

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0.004

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Dimensions in inch

Nom.

0.�3� BSC

0.155 BSC

0.341 BSC

0.0�5 BSC

Dimensions in mm

Nom.

�.0 BSC

3.9 BSC

8.�� BSC

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Max.

0.30

1.75

0.�5

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0.�5

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Rev. 1.40 193 De�e��e� 01� �01�

Symbol

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G

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A

B

C

C’

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Symbol

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G

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C’

24-pin SSOP (150mil) Outline Dimensions

HT68FB540/HT68FB550/HT68FB560

I/O Flash USB MCU with SPI

Min.

0.�0

0.10

0.41

0.10

Min.

0.008

0.004

0.01�

0.004

Dimensions in inch

Nom.

0.�3� BSC

0.154 BSC

0.341 BSC

0.0�5 BSC

Dimensions in mm

Nom.

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3.900 BSC

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Max.

0.30

1.75

0.�5

1.�7

0.�5

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0.01�

0.0�9

0.010

0.050

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Rev. 1.40

194 De�e��e� 01� �01�

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I/O Flash USB MCU with SPI

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HT68FB540/HT68FB550/HT68FB560

I/O Flash USB MCU with SPI

Rev. 1.40

194 De�e��e� 01� �01�

Symbol

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HT68FB540/HT68FB550/HT68FB560

I/O Flash USB MCU with SPI

28-pin SSOP (150mil) Outline Dimensions

Min.

0.�0

0.10

0.41

0.10

Min.

0.008

0.004

0.01�

0.004

Dimensions in inch

Nom.

0.�3� BSC

0.154 BSC

0.390 BSC

0.0�5 BSC

Dimensions in mm

Nom.

�.000 BSC

3.900 BSC

9.900 BSC

0.�35 BSC

Max.

0.30

1.75

0.�5

1.�7

0.�5

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0.01�

0.0�9

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Rev. 1.40 195 De�e��e� 01� �01�

Symbol

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A3

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L

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Symbol

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A3

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HT68FB540/HT68FB550/HT68FB560

I/O Flash USB MCU with SPI

SAW Type 20-pin (4mm

×4

mm) QFN Outline Dimensions

Min.

0.800

0.000

0.180

1.90

1.90

0.30

0.�0

Min.

0.031

0.000

0.007

0.075

0.075

0.01�

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Dimensions in inch

Nom.

0.033

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0.008 REF

0.010

0.157 BSC

0.157 BSC

0.0�0 BSC

0.079

0.079

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Dimensions in mm

Nom.

0.850

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0.�03 REF

0.�50

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4.000 BSC

0.500 BSC

�.00

�.00

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0.300

�.05

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0.01�

0.081

0.081

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Rev. 1.40

19� De�e��e� 01� �01�

HT68FB540/HT68FB550/HT68FB560

I/O Flash USB MCU with SPI

Rev. 1.40 197 De�e��e� 01� �01�

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I/O Flash USB MCU with SPI

Rev. 1.40

19� De�e��e� 01� �01�

HT68FB540/HT68FB550/HT68FB560

I/O Flash USB MCU with SPI

48-pin LQFP (7mm

×

7mm) Outline Dimensions

Rev. 1.40

Symbol

G

H

I

E

F

A

B

C

D

J

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Symbol

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J

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Min.

0.17

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0.007

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0.018

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Dimensions in inch

Nom.

0.354 BSC

0.�7� BSC

0.354 BSC

0.�7� BSC

0.0�0 BSC

0.009

0.055

0.0�4

Dimensions in mm

Nom.

9.00 BSC

7.00 BSC

9.00 BSC

7.00 BSC

0.50 BSC

0.��

1.40

0.�0

Max.

0.�7

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0.030

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HT68FB540/HT68FB550/HT68FB560

I/O Flash USB MCU with SPI

HT68FB540/HT68FB550/HT68FB560

I/O Flash USB MCU with SPI

Copy�ight

©

�01� �y HOLTEK SEMICONDUCTOR INC.

The info��ation appea�ing in this Data Sheet is �elieved to �e a��u�ate at the ti�e of pu�li�ation. Howeve�� Holtek assu�es no �esponsi�ility a�ising f�o� the use of the specifications described. The applications mentioned herein are used solely fo� the pu�pose of illust�ation and Holtek �akes no wa��anty o� �ep�esentation that su�h appli�ations will �e suita�le without fu�the� �odifi�ation� no� �e�o��ends the use of its p�odu�ts fo� appli�ation that �ay p�esent a �isk to hu�an life due to

�alfun�tion o� othe�wise. Holtek's p�odu�ts a�e not autho�ized fo� use as ��iti�al

�o�ponents in life suppo�t devi�es o� syste�s. Holtek �ese�ves the �ight to alte� its products without prior notification. For the most up-to-date information, please visit ou� we� site at http://www.holtek.�o�.

Rev. 1.40

198 De�e��e� 01� �01� Rev. 1.40 PB De�e��e� 01� �01�

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