78K0R/Kx3-L User`s Manual for Hardware

78K0R/Kx3-L User`s Manual for Hardware
User’s Manual
16
78K0R/Kx3-L
User’s Manual: Hardware
16-Bit Single-Chip Microcontrollers
All information contained in these materials, including products and product specifications,
represents information on the product at the time of publication and is subject to change by
Renesas Electronics Corp. without notice. Please review the latest information published by
Renesas Electronics Corp. through various means, including the Renesas Electronics Corp.
website (http://www.renesas.com).
www.renesas.com
Rev.4.00
Mar 2011
Notice
1.
2.
3.
4.
5.
6.
7.
All information included in this document is current as of the date this document is issued. Such information, however, is
subject to change without any prior notice. Before purchasing or using any Renesas Electronics products listed herein, please
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Descriptions of circuits, software and other related information in this document are provided only to illustrate the operation of
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NOTES FOR CMOS DEVICES
(1) VOLTAGE APPLICATION WAVEFORM AT INPUT PIN: Waveform distortion due to input noise or a
reflected wave may cause malfunction. If the input of the CMOS device stays in the area between VIL
(MAX) and VIH (MIN) due to noise, etc., the device may malfunction. Take care to prevent chattering noise
from entering the device when the input level is fixed, and also in the transition period when the input level
passes through the area between VIL (MAX) and VIH (MIN).
(2) HANDLING OF UNUSED INPUT PINS: Unconnected CMOS device inputs can be cause of malfunction.
If an input pin is unconnected, it is possible that an internal input level may be generated due to noise, etc.,
causing malfunction. CMOS devices behave differently than Bipolar or NMOS devices. Input levels of
CMOS devices must be fixed high or low by using pull-up or pull-down circuitry. Each unused pin should be
connected to VDD or GND via a resistor if there is a possibility that it will be an output pin. All handling
related to unused pins must be judged separately for each device and according to related specifications
governing the device.
(3) PRECAUTION AGAINST ESD: A strong electric field, when exposed to a MOS device, can cause
destruction of the gate oxide and ultimately degrade the device operation. Steps must be taken to stop
generation of static electricity as much as possible, and quickly dissipate it when it has occurred.
Environmental control must be adequate. When it is dry, a humidifier should be used. It is recommended
to avoid using insulators that easily build up static electricity. Semiconductor devices must be stored and
transported in an anti-static container, static shielding bag or conductive material. All test and measurement
tools including work benches and floors should be grounded. The operator should be grounded using a
wrist strap. Semiconductor devices must not be touched with bare hands. Similar precautions need to be
taken for PW boards with mounted semiconductor devices.
(4) STATUS BEFORE INITIALIZATION: Power-on does not necessarily define the initial status of a MOS
device. Immediately after the power source is turned ON, devices with reset functions have not yet been
initialized. Hence, power-on does not guarantee output pin levels, I/O settings or contents of registers. A
device is not initialized until the reset signal is received. A reset operation must be executed immediately
after power-on for devices with reset functions.
(5) POWER ON/OFF SEQUENCE: In the case of a device that uses different power supplies for the internal
operation and external interface, as a rule, switch on the external power supply after switching on the internal
power supply. When switching the power supply off, as a rule, switch off the external power supply and then
the internal power supply. Use of the reverse power on/off sequences may result in the application of an
overvoltage to the internal elements of the device, causing malfunction and degradation of internal elements
due to the passage of an abnormal current. The correct power on/off sequence must be judged separately
for each device and according to related specifications governing the device.
(6) INPUT OF SIGNAL DURING POWER OFF STATE : Do not input signals or an I/O pull-up power supply
while the device is not powered. The current injection that results from input of such a signal or I/O pull-up
power supply may cause malfunction and the abnormal current that passes in the device at this time may
cause degradation of internal elements. Input of signals during the power off state must be judged
separately for each device and according to related specifications governing the device.
How to Use This Manual
Readers
This manual is intended for user engineers who wish to understand the functions of the
78K0R/Kx3-L and design and develop application systems and programs for these devices.
The target products are as follows.
• 78K0R/KC3-L: μPD78F1000, 78F1001, 78F1002, 78F1003
• 78K0R/KD3-L: μPD78F1004, 78F1005, 78F1006
• 78K0R/KE3-L: μPD78F1007, 78F1008, 78F1009
• 78K0R/KF3-L: μPD78F1010, 78F1011, 78F1012, 78F1027, 78F1028
• 78K0R/KG3-L: μPD78F1013, 78F1014, 78F1029, 78F1030
Purpose
This manual is intended to give users an understanding of the functions described in the
Organization below.
Organization
The 78K0R/Kx3-L manual is separated into two parts: this manual and the instructions
edition (common to the 78K0R Microcontroller).
78K0R/Kx3-L
78K0R Microcontroller
User’s Manual
User’s Manual
(This Manual)
Instructions
• Pin functions
• CPU functions
• Internal block functions
• Instruction set
• Interrupts
• Explanation of each instruction
• Other on-chip peripheral functions
• Electrical specifications
How to Read This Manual
It is assumed that the readers of this manual have general knowledge of electrical
engineering, logic circuits, and microcontrollers.
• To gain a general understanding of functions:
→ Read this manual in the order of the CONTENTS. The mark “<R>” shows major
revised points. The revised points can be easily searched by copying an “<R>” in the
PDF file and specifying it in the “Find what:” field.
• How to interpret the register format:
→ For a bit number enclosed in angle brackets, the bit name is defined as a reserved
word in the RA78K0R, and is defined as an sfr variable using the #pragma sfr
directive in the CC78K0R.
• To know details of the 78K0R Microcontroller instructions:
→ Refer to the separate document 78K0R Microcontroller Instructions User’s Manual
(U17792E).
Conventions
Data significance:
Higher digits on the left and lower digits on the right
Active low representations: ××× (overscore over pin and signal name)
Note:
Footnote for item marked with Note in the text
Caution:
Information requiring particular attention
Remark:
Supplementary information
...×××× or ××××B
Numerical representations: Binary
...××××
Decimal
Hexadecimal
Related Documents
...××××H
The related documents indicated in this publication may include preliminary versions.
However, preliminary versions are not marked as such.
Documents Related to Devices
Document Name
Document No.
78K0R/Kx3-L User’s Manual
This manual
78K0R Microcontroller Instructions User’s Manual
78K0R Microcontroller Self Programming Library Type02 User’s Manual
U17792E
Note
U19193E
Note This document is classified under engineering management. Contact an Renesas Electronics sales representative.
Documents Related to Development Tools (Software) (User’s Manuals)
Document Name
CC78K0R Ver. 2.00 C Compiler
RA78K0R Ver. 1.20 Assembler Package
SM+ System Simulator
Document No.
Operation
U18549E
Language
U18548E
Operation
U18547E
Language
U18546E
Operation
U18010E
PM+ Ver. 6.30
U18416E
ID78K0R-QB Ver. 3.20 Integrated Debugger
Operation
U17839E
Documents Related to Development Tools (Hardware) (User’s Manuals)
Document Name
Document No.
QB-MINI2 On-Chip Debug Emulator with Programming Function
U18371E
QB-78K0RIX3 In-Circuit Emulator (compatible with 78K0R/KC3-L, 78K0R/KD3-L, and 78K0R/KE3-L)
U19228E
QB-78K0RKX3C In-Circuit Emulator (compatible with 78K0R/KF3-L and 78K0R/KG3-L (μ PD78F1010,
U19324E
78F1011, 78F1012, 78F1013, and 78F1014))
QB-78F1030 In-Circuit Emulator (compatible with 78K0R/KF3-L and 78K0R/KG3-L (μ PD78F1027, 78F1028,
Under development
78F1029, and 78F1030))
Documents Related to Flash Memory Programming
Document Name
PG-FP5 Flash Memory Programmer User’s Manual
Document No.
R02UT0008E
Caution The related documents listed above are subject to change without notice. Be sure to use the latest
version of each document when designing.
Other Documents
Document Name
RENESAS MICROCOMPUTER GENERAL CATALOG
Document No.
R01CS0001E
Semiconductor Device Mount Manual
Note
Quality Grades on NEC Semiconductor Devices
C11531E
NEC Semiconductor Device Reliability/Quality Control System
C10983E
Guide to Prevent Damage for Semiconductor Devices by Electrostatic Discharge (ESD)
C11892E
Note See the “Semiconductor Device Mount Manual” website (http://www.renesas.com/prod/package/manual/index.html).
Caution The related documents listed above are subject to change without notice. Be sure to use the latest
version of each document when designing.
All trademarks and registered trademarks are the property of their respective owners.
Windows and Windows NT are registered trademarks or trademarks of Microsoft Corporation in the United States
and/or other countries.
PC/AT is a trademark of International Business Machines Corporation.
EEPROM is a trademark of Renesas Electronics Corporation.
SuperFlash is a registered trademark of Silicon Storage Technology, Inc. in several countries including the United
States and Japan.
Caution: This product uses SuperFlash® technology licensed from Silicon Storage Technology, Inc.
CONTENTS
CHAPTER 1 OUTLINE............................................................................................................................. 22
1.1 Features......................................................................................................................................... 22
1.2 Applications .................................................................................................................................. 24
1.3 Ordering Information.................................................................................................................... 24
1.4 Pin Configuration (Top View) ...................................................................................................... 25
1.4.1 78K0R/KC3-L ................................................................................................................................... 25
1.4.2 78K0R/KD3-L ................................................................................................................................... 28
1.4.3 78K0R/KE3-L ................................................................................................................................... 29
1.4.4 78K0R/KF3-L.................................................................................................................................... 31
1.4.5 78K0R/KG3-L ................................................................................................................................... 32
1.5 Pin Identification........................................................................................................................... 35
1.6 Block Diagram .............................................................................................................................. 36
1.6.1 78K0R/KC3-L ................................................................................................................................... 36
1.6.2 78K0R/KD3-L ................................................................................................................................... 39
1.6.3 78K0R/KE3-L ................................................................................................................................... 40
1.6.4 78K0R/KF3-L.................................................................................................................................... 41
1.6.5 78K0R/KG3-L ................................................................................................................................... 42
1.7 Outline of Functions..................................................................................................................... 43
1. 7. 1 78K0R/KC3-L, 78K0R/KD3-L, 78K0R/KE3-L ................................................................................. 43
1. 7. 2 78K0R/KF3-L, 78K0R/KG3-L ......................................................................................................... 45
CHAPTER 2 PIN FUNCTIONS (78K0R/KC3-L, 78K0R/KD3-L, 78K0R/KE3-L) ................................... 47
2.1 Pin Function List .......................................................................................................................... 47
2.1.1 78K0R/KC3-L (40-pin products) ....................................................................................................... 48
2.1.2 78K0R/KC3-L (44-pin and 48-pin products) ..................................................................................... 52
2.1.3 78K0R/KD3-L ................................................................................................................................... 57
2.1.4 78K0R/KE3-L ................................................................................................................................... 62
2.2 Description of Pin Functions ...................................................................................................... 67
2.2.1 P00, P01 (port 0) .............................................................................................................................. 67
2.2.2 P10 to P17 (port 1) ........................................................................................................................... 68
2.2.3 P20 to P27 (port 2) ........................................................................................................................... 69
2.2.4 P30 to P33 (port 3) ........................................................................................................................... 70
2.2.5 P40 to P43 (port 4) ........................................................................................................................... 71
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2.2.6 P50 to P53 (port 5) ........................................................................................................................... 72
2.2.7 P60 and P61 (port 6) ........................................................................................................................ 73
2.2.8 P70 to P77 (port 7) ........................................................................................................................... 73
2.2.9 P80 to P83 (port 8) ........................................................................................................................... 75
2.2.10 P120 to P124 (port 12) ................................................................................................................... 76
2.2.11 P140, P141 (port 14) ...................................................................................................................... 77
2.2.12 P150 to P153 (port 15) ................................................................................................................... 78
2.2.13 AVREF, AVSS, VDD, EVDD, VSS, EVSS ................................................................................................ 78
2.2.14 RESET ........................................................................................................................................... 79
2.2.15 REGC ............................................................................................................................................. 79
2.2.16 FLMD0............................................................................................................................................ 80
2.3 Pin I/O Circuits and Recommended Connection of Unused Pins ........................................... 81
CHAPTER 3 PIN FUNCTIONS (78K0R/KF3-L, 78K0R/KG3-L) ............................................................ 87
3.1 Pin Function List .......................................................................................................................... 87
3.1.1 78K0R/KF3-L.................................................................................................................................... 88
3.1.2 78K0R/KG3-L ................................................................................................................................... 93
3.2 Description of Pin Functions ...................................................................................................... 99
3.2.1 P00 to P06 (port 0) ........................................................................................................................... 99
3.2.2 P10 to P17 (port 1) ......................................................................................................................... 100
3.2.3 P20 to P27 (port 2) ......................................................................................................................... 102
3.2.4 P30, P31 (port 3) ............................................................................................................................ 102
3.2.5 P40 to P47 (port 4) ......................................................................................................................... 103
3.2.6 P50 to P57 (port 5) ......................................................................................................................... 105
3.2.7 P60 to P67 (port 6) ......................................................................................................................... 107
3.2.8 P70 to P77 (port 7) ......................................................................................................................... 108
3.2.9 P80 to P87 (port 8) ......................................................................................................................... 109
3.2.10 P90, P91 (port 9) .......................................................................................................................... 110
3.2.11 P110, P111 (port 11) .................................................................................................................... 110
3.2.12 P120 to P124 (port 12) ................................................................................................................. 110
3.2.13 P130, P131 (port 13) .................................................................................................................... 111
3.2.14 P140 to P145 (port 14) ................................................................................................................. 112
3.2.15 P150 to P157 (port 15) ................................................................................................................. 113
3.2.16 AVREF, AVSS, VDD, EVDD0, EVDD1, VSS, EVSS0, EVSS1 ..................................................................... 114
3.2.17 RESET ......................................................................................................................................... 115
3.2.18 REGC ........................................................................................................................................... 115
3.2.19 FLMD0.......................................................................................................................................... 115
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3.3 Pin I/O Circuits and Recommended Connection of Unused Pins ......................................... 116
3.3.1 78K0R/KF3-L.................................................................................................................................. 116
3.3.2 78K0R/KG3-L ................................................................................................................................. 119
CHAPTER 4 CPU ARCHITECTURE .................................................................................................... 124
4.1 Memory Space ............................................................................................................................ 124
4.1.1 Internal program memory space..................................................................................................... 137
4.1.2 Mirror area...................................................................................................................................... 141
4.1.3 Internal data memory space ........................................................................................................... 143
4.1.4 Special function register (SFR) area .............................................................................................. 144
4.1.5 Extended special function register (2nd SFR: 2nd Special Function Register) area ..................... 144
4.1.6 Data memory addressing ............................................................................................................... 145
4.2 Processor Registers................................................................................................................... 154
4.2.1 Control registers ............................................................................................................................. 154
4.2.2 General-purpose registers.............................................................................................................. 156
4.2.3 ES and CS registers....................................................................................................................... 158
4.2.4 Special function registers (SFRs) ................................................................................................... 159
4.2.5 Extended special function registers (2nd SFRs: 2nd Special Function Registers) ......................... 166
4.3 Instruction Address Addressing............................................................................................... 175
4.3.1 Relative addressing........................................................................................................................ 175
4.3.2 Immediate addressing .................................................................................................................... 175
4.3.3 Table indirect addressing ............................................................................................................... 176
4.3.4 Register direct addressing.............................................................................................................. 177
4.4 Addressing for Processing Data Addresses ........................................................................... 178
4.4.1 Implied addressing ......................................................................................................................... 178
4.4.2 Register addressing ....................................................................................................................... 178
4.4.3 Direct addressing ........................................................................................................................... 179
4.4.4 Short direct addressing .................................................................................................................. 180
4.4.5 SFR addressing.............................................................................................................................. 181
4.4.6 Register indirect addressing ........................................................................................................... 182
4.4.7 Based addressing........................................................................................................................... 183
4.4.8 Based indexed addressing ............................................................................................................. 186
4.4.9 Stack addressing............................................................................................................................ 187
CHAPTER 5 PORT FUNCTIONS (78K0R/KC3-L, 78K0R/KD3-L, 78K0R/KE3-L) ............................. 188
5.1 Port Functions ............................................................................................................................ 188
5.2 Port Configuration...................................................................................................................... 191
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5.2.1 Port 0.............................................................................................................................................. 192
5.2.2 Port 1.............................................................................................................................................. 194
5.2.3 Port 2.............................................................................................................................................. 197
5.2.4 Port 3.............................................................................................................................................. 199
5.2.5 Port 4.............................................................................................................................................. 203
5.2.6 Port 5.............................................................................................................................................. 206
5.2.7 Port 6.............................................................................................................................................. 210
5.2.8 Port 7.............................................................................................................................................. 211
5.2.9 Port 8.............................................................................................................................................. 216
5.2.10 Port 12.......................................................................................................................................... 220
5.2.11 Port 14.......................................................................................................................................... 224
5.2.12 Port 15.......................................................................................................................................... 226
5.3 Registers Controlling Port Function ........................................................................................ 228
5.4 Port Function Operations .......................................................................................................... 243
5.4.1 Writing to I/O port ........................................................................................................................... 243
5.4.2 Reading from I/O port ..................................................................................................................... 243
5.4.3 Operations on I/O port .................................................................................................................... 243
5.4.4 Connecting to external device with different power potential (2.5 V, 3 V)....................................... 244
5.5 Settings of Port Mode Register and Output Latch When Using Alternate Function........... 246
5.6 Cautions on 1-bit Manipulation Instruction for Port Register n (Pn) .................................... 249
CHAPTER 6 PORT FUNCTIONS (78K0R/KF3-L, 78K0R/KG3-L) ...................................................... 250
6.1 Port Functions ............................................................................................................................ 250
6.2 Port Configuration...................................................................................................................... 255
6.2.1 Port 0.............................................................................................................................................. 256
6.2.2 Port 1.............................................................................................................................................. 262
6.2.3 Port 2.............................................................................................................................................. 270
6.2.4 Port 3.............................................................................................................................................. 272
6.2.5 Port 4.............................................................................................................................................. 274
6.2.6 Port 5 (μ PD78F1010, 78F1011, 78F1012, 78F1013, 78F1014) .................................................... 283
6.2.7 Port 5 (μ PD78F1027, 78F1028, 78F1029, 78F1030) .................................................................... 288
6.2.8 Port 6.............................................................................................................................................. 295
6.2.9 Port 7.............................................................................................................................................. 300
6.2.10 Port 8............................................................................................................................................ 302
6.2.11 Port 9............................................................................................................................................ 304
6.2.12 Port 11.......................................................................................................................................... 305
6.2.13 Port 12.......................................................................................................................................... 307
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6.2.14 Port 13.......................................................................................................................................... 311
6.2.15 Port 14.......................................................................................................................................... 313
6.2.16 Port 15.......................................................................................................................................... 318
6.3 Registers Controlling Port Function ........................................................................................ 320
6.4 Port Function Operations .......................................................................................................... 330
6.4.1 Writing to I/O port ........................................................................................................................... 330
6.4.2 Reading from I/O port ..................................................................................................................... 330
6.4.3 Operations on I/O port .................................................................................................................... 330
6.4.4 Connecting to external device with different potential (2.5 V, 3 V) ................................................. 331
6.5 Settings of Port Mode Register, and Output Latch When Using Alternate Function.......... 333
6.6 Cautions on 1-Bit Manipulation Instruction for Port Register n (Pn).................................... 337
CHAPTER 7 CLOCK GENERATOR .................................................................................................... 338
7.1 Functions of Clock Generator................................................................................................... 338
7.2 Configuration of Clock Generator ............................................................................................ 339
7.3 Registers Controlling Clock Generator.................................................................................... 343
7.4 System Clock Oscillator ............................................................................................................ 361
7.4.1 X1 oscillator.................................................................................................................................... 361
7.4.2 XT1 oscillator (products other than 78K0R/KC3-L (40-pin)) ........................................................... 361
7.4.3 Internal high-speed oscillator.......................................................................................................... 365
7.4.4 Internal low-speed oscillator ........................................................................................................... 365
7.4.5 Prescaler ........................................................................................................................................ 365
7.5 Clock Generator Operation ....................................................................................................... 366
7.6 Controlling Clock........................................................................................................................ 371
7.6.1 Example of setting 8 MHz internal high-speed oscillator ................................................................ 371
7.6.2 Example of setting 1 MHz internal high-speed oscillator ................................................................ 371
7.6.3 Example of setting 20 MHz internal high-speed oscillator .............................................................. 372
7.6.4 Example of setting X1 oscillation clock........................................................................................... 373
7.6.5 Example of setting XT1 oscillation clock (products other than 78K0R/KC3-L (40-pin)) ................. 374
7.6.6 CPU clock status transition diagram............................................................................................... 376
7.6.7 Condition before changing CPU clock and processing after changing CPU clock ......................... 384
7.6.8 Time required for switchover of CPU clock and main system clock ............................................... 386
7.6.9 Conditions before clock oscillation is stopped ................................................................................ 387
CHAPTER 8 TIMER ARRAY UNIT...................................................................................................... 388
8.1 Functions of Timer Array Unit................................................................................................... 389
8.1.1 Independent channel operation function ........................................................................................ 389
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8.1.2 Simultaneous channel operation function....................................................................................... 390
8.1.3 LIN-bus supporting function (channel 7 only) ................................................................................. 392
8.2 Configuration of Timer Array Unit ............................................................................................ 393
8.3 Registers Controlling Timer Array Unit.................................................................................... 402
8.4 Basic Rules of Simultaneous Channel Operation Function .................................................. 432
8.5 Channel Output (TOmn pin) Control ........................................................................................ 434
8.5.1 TOmn pin output circuit configuration............................................................................................. 434
8.5.2 TOmn Pin Output Setting ............................................................................................................... 436
8.5.3 Cautions on Channel Output Operation ......................................................................................... 437
8.5.4 Collective manipulation of TOmn bit............................................................................................... 442
8.5.5 Timer Interrupt and TOmn Pin Output at Operation Start ............................................................... 443
8.6 Channel Input (TImn Pin) Control ............................................................................................. 444
8.6.1 TImn edge detection circuit ............................................................................................................ 444
8.7 Independent Channel Operation Function of Timer Array Unit............................................. 445
8.7.1 Operation as interval timer/square wave output ............................................................................. 445
8.7.2 Operation as external event counter .............................................................................................. 452
8.7.3 Operation as frequency divider (channel 0 of 78K0R/KD3-L, KE3-L, KF3-L. KG3-L only) ............. 456
8.7.4 Operation as input pulse interval measurement ............................................................................. 460
8.7.5 Operation as input signal high-/low-level width measurement........................................................ 464
8.8 Simultaneous Channel Operation Function of Timer Array Unit .......................................... 468
8.8.1 Operation as one-shot pulse output function .................................................................................. 468
8.8.2 Operation as PWM function............................................................................................................ 475
8.8.3 Operation as multiple PWM output function ................................................................................... 482
CHAPTER 9 REAL-TIME COUNTER................................................................................................... 492
9.1 Functions of Real-Time Counter............................................................................................... 492
9.2 Configuration of Real-Time Counter ........................................................................................ 492
9.3 Registers Controlling Real-Time Counter................................................................................ 494
9.4 Real-Time Counter Operation ................................................................................................... 509
9.4.1 Starting operation of real-time counter ........................................................................................... 509
9.4.2 Shifting to STOP mode after starting operation .............................................................................. 510
9.4.3 Reading/writing real-time counter................................................................................................... 511
9.4.4 Setting alarm of real-time counter .................................................................................................. 513
9.4.5 1 Hz output of real-time counter ..................................................................................................... 514
9.4.6 32.768 kHz output of real-time counter .......................................................................................... 514
9.4.7 512 Hz, 16.384 kHz output of real-time counter ............................................................................. 514
9.4.8 Example of watch error correction of real-time counter .................................................................. 515
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CHAPTER 10 COMPARATORS/PROGRAMMABLE GAIN AMPLIFIERS (78K0R/KC3-L, 78K0R/KD3-L,
78K0R/KE3-L only) ........................................................................................................ 520
10.1 Features of Comparator and Programmable Gain Amplifier ............................................... 520
10.2 Configurations of Comparator and Programmable Gain Amplifier .................................... 523
10.3 Registers Controlling Comparators and Programmable Gain Amplifiers.......................... 523
10.4 Operations of Comparator and Programmable Gain Amplifier ........................................... 530
10.4.1 Starting comparator and programmable gain amplifier operation................................................. 530
10.4.2 Stopping comparator and programmable gain amplifier operation ............................................... 535
CHAPTER 11 CLOCK OUTPUT/BUZZER OUTPUT CONTROLLER............................................... 537
11.1 Functions of Clock Output/Buzzer Output Controller .......................................................... 537
11.2 Configuration of Clock Output/Buzzer Output Controller.................................................... 540
11.3 Registers Controlling Clock Output/Buzzer Output Controller ........................................... 540
11.4 Operations of Clock Output/Buzzer Output Controller ........................................................ 543
11.4.1 Operation as output pin ................................................................................................................ 543
CHAPTER 12 WATCHDOG TIMER ..................................................................................................... 544
12.1 Functions of Watchdog Timer................................................................................................. 544
12.2 Configuration of Watchdog Timer .......................................................................................... 545
12.3 Register Controlling Watchdog Timer.................................................................................... 546
12.4 Operation of Watchdog Timer................................................................................................. 547
12.4.1 Controlling operation of watchdog timer ....................................................................................... 547
12.4.2 Setting overflow time of watchdog timer ....................................................................................... 548
12.4.3 Setting window open period of watchdog timer ............................................................................ 549
12.4.4 Setting watchdog timer interval interrupt ...................................................................................... 550
CHAPTER 13 A/D CONVERTER .......................................................................................................... 551
13.1 Function of A/D Converter....................................................................................................... 551
13.2 Configuration of A/D Converter .............................................................................................. 552
13.3 Registers Used in A/D Converter............................................................................................ 554
13.4 A/D Converter Operations ....................................................................................................... 568
13.4.1 Basic operations of A/D converter ................................................................................................ 568
13.4.2 Input voltage and conversion results ............................................................................................ 570
13.4.3 A/D converter operation modes.................................................................................................... 571
13.5 How to Read A/D Converter Characteristics Table............................................................... 574
13.6 Cautions for A/D Converter ..................................................................................................... 576
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CHAPTER 14 SERIAL ARRAY UNIT.................................................................................................. 580
14.1 Functions of Serial Array Unit................................................................................................. 581
14.1.1 3-wire serial I/O (CSI00, CSI01, CSI10, CSI20, CSI40, CSI41) ................................................... 581
14.1.2 UART (UART0 to UART4)............................................................................................................ 582
14.1.3 Simplified I2C (IIC10, IIC20).......................................................................................................... 583
14.2 Configuration of Serial Array Unit .......................................................................................... 584
14.3 Registers Controlling Serial Array Unit.................................................................................. 591
14.4 Operation stop mode ............................................................................................................... 622
14.4.1 Stopping the operation by units .................................................................................................... 623
14.4.2 Stopping the operation by channels ............................................................................................. 625
14.5 Operation of 3-Wire Serial I/O (CSI00, CSI01, CSI10, CSI20, CSI40, CSI41) Communication..... 627
14.5.1 Master transmission ..................................................................................................................... 629
14.5.2 Master reception........................................................................................................................... 639
14.5.3 Master transmission/reception...................................................................................................... 648
14.5.4 Slave transmission ....................................................................................................................... 658
14.5.5 Slave reception............................................................................................................................. 668
14.5.6 Slave transmission/reception........................................................................................................ 675
14.5.7 Calculating transfer clock frequency............................................................................................. 685
14.5.8 Procedure for processing errors that occurred during 3-wire serial I/O (CSI00, CSI01, CSI10, CSI20,
CSI40, CSI41) communication..................................................................................................... 687
14.6 Operation of UART (UART0 to UART4) Communication...................................................... 688
14.6.1 UART transmission ...................................................................................................................... 690
14.6.2 UART reception............................................................................................................................ 700
14.6.3 Calculating baud rate ................................................................................................................... 707
14.6.4 Procedure for processing errors that occurred during UART (UART0 to UART4) communication...... 711
14.7 LIN Communication Operation ............................................................................................... 712
14.7.1 LIN transmission........................................................................................................................... 712
14.7.2 LIN reception ................................................................................................................................ 715
14.8 Operation of Simplified I2C (IIC10, IIC20) Communication ................................................... 721
14.8.1 Address field transmission............................................................................................................ 723
14.8.2 Data transmission......................................................................................................................... 729
14.8.3 Data reception .............................................................................................................................. 733
14.8.4 Stop condition generation............................................................................................................. 738
14.8.5 Calculating transfer rate ............................................................................................................... 739
14.8.6 Procedure for processing errors that occurred during simplified I2C (IIC10, IIC20) communication......742
14.9 Relationship Between Register Settings and Pins ............................................................... 743
14.9.1 78K0R/KC3-L, 78K0R/KD3-L, 78K0R/KE3-L ............................................................................... 743
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14.9.2 78K0R/KF3-L, 78K0R/KG3-L ....................................................................................................... 747
CHAPTER 15 SERIAL INTERFACE IICA ........................................................................................... 756
15.1 Functions of Serial Interface IICA........................................................................................... 756
15.2 Configuration of Serial Interface IICA .................................................................................... 759
15.3 Registers Controlling Serial Interface IICA............................................................................ 762
15.4 I2C Bus Mode Functions........................................................................................................... 776
15.4.1 Pin configuration........................................................................................................................... 776
15.4.2 Setting transfer clock by using IICWL and IICWH registers.......................................................... 777
2
15.5 I C Bus Definitions and Control Methods .............................................................................. 778
15.5.1 Start conditions............................................................................................................................. 778
15.5.2 Addresses .................................................................................................................................... 779
15.5.3 Transfer direction specification..................................................................................................... 779
15.5.4 Acknowledge (ACK) ..................................................................................................................... 780
15.5.5 Stop condition............................................................................................................................... 781
15.5.6 Wait .............................................................................................................................................. 782
15.5.7 Canceling wait .............................................................................................................................. 784
15.5.8 Interrupt request (INTIICA) generation timing and wait control..................................................... 785
15.5.9 Address match detection method ................................................................................................. 786
15.5.10 Error detection............................................................................................................................ 786
15.5.11 Extension code........................................................................................................................... 786
15.5.12 Arbitration ................................................................................................................................... 787
15.5.13 Wakeup function......................................................................................................................... 789
15.5.14 Communication reservation........................................................................................................ 792
15.5.15 Cautions ..................................................................................................................................... 796
15.5.16 Communication operations......................................................................................................... 797
15.5.17 Timing of I2C interrupt request (INTIICA) occurrence ................................................................. 804
15.6 Timing Charts ........................................................................................................................... 825
CHAPTER 16 MULTIPLIER/DIVIDER ................................................................................................... 840
16.1 Functions of Multiplier/Divider................................................................................................ 840
16.2 Configuration of Multiplier/Divider ......................................................................................... 840
16.3 Register Controlling Multiplier/Divider................................................................................... 845
16.4 Operations of Multiplier/Divider.............................................................................................. 846
16.4.1 Multiplication operation................................................................................................................. 846
16.4.2 Division operation......................................................................................................................... 847
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CHAPTER 17 DMA CONTROLLER ..................................................................................................... 849
17.1 Functions of DMA Controller .................................................................................................. 849
17.2 Configuration of DMA Controller ............................................................................................ 850
17.3 Registers Controlling DMA Controller ................................................................................... 853
17.4 Operation of DMA Controller................................................................................................... 857
17.4.1 Operation procedure .................................................................................................................... 857
17.4.2 Transfer mode .............................................................................................................................. 858
17.4.3 Termination of DMA transfer ........................................................................................................ 858
17.5 Example of Setting of DMA Controller ................................................................................... 859
17.5.1 CSI consecutive transmission ...................................................................................................... 859
17.5.2 Consecutive capturing of A/D conversion results ......................................................................... 861
17.5.3 UART consecutive reception + ACK transmission........................................................................ 863
17.5.4 Holding DMA transfer pending by DWAITn bit ............................................................................. 865
17.5.5 Forced termination by software .................................................................................................... 866
17.6 Cautions on Using DMA Controller ........................................................................................ 868
CHAPTER 18 INTERRUPT FUNCTIONS............................................................................................. 870
18.1 Interrupt Function Types ......................................................................................................... 870
18.2 Interrupt Sources and Configuration ..................................................................................... 870
18.3 Registers Controlling Interrupt Functions (78K0R/KC3-L, 78K0R/KD3-L, 78K0R/KE3-L). 876
18.4 Registers Controlling Interrupt Functions (78K0R/KF3-L, 78K0R/KG3-L).......................... 886
18.5 Interrupt Servicing Operations ............................................................................................... 897
18.5.1 Maskable interrupt request acknowledgment ............................................................................... 897
18.5.2 Software interrupt request acknowledgment ................................................................................ 900
18.5.3 Multiple interrupt servicing............................................................................................................ 900
18.5.4 Interrupt request hold ................................................................................................................... 904
CHAPTER 19 KEY INTERRUPT FUNCTION ..................................................................................... 905
19.1 Functions of Key Interrupt ...................................................................................................... 905
19.2 Configuration of Key Interrupt ................................................................................................ 905
19.3 Register Controlling Key Interrupt ......................................................................................... 907
CHAPTER 20 STANDBY FUNCTION .................................................................................................. 908
20.1 Standby Function and Configuration ..................................................................................... 908
20.1.1 Standby function........................................................................................................................... 908
20.1.2 Registers controlling standby function.......................................................................................... 909
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20.2 Standby Function Operation ................................................................................................... 912
20.2.1 HALT mode .................................................................................................................................. 912
20.2.2 STOP mode.................................................................................................................................. 917
CHAPTER 21 RESET FUNCTION........................................................................................................ 922
21.1 Register for Confirming Reset Source ................................................................................... 931
CHAPTER 22 POWER-ON-CLEAR CIRCUIT...................................................................................... 933
22.1 Functions of Power-on-Clear Circuit...................................................................................... 933
22.2 Configuration of Power-on-Clear Circuit ............................................................................... 934
22.3 Operation of Power-on-Clear Circuit ...................................................................................... 934
22.4 Cautions for Power-on-Clear Circuit ...................................................................................... 937
CHAPTER 23 LOW-VOLTAGE DETECTOR ....................................................................................... 939
23.1 Functions of Low-Voltage Detector........................................................................................ 939
23.2 Configuration of Low-Voltage Detector ................................................................................. 940
23.3 Registers Controlling Low-Voltage Detector......................................................................... 940
23.4 Operation of Low-Voltage Detector ........................................................................................ 945
23.4.1 When used as reset ..................................................................................................................... 946
23.4.2 When used as interrupt ................................................................................................................ 952
23.5 Cautions for Low-Voltage Detector ........................................................................................ 958
CHAPTER 24 REGULATOR ................................................................................................................. 962
24.1 Regulator Overview.................................................................................................................. 962
24.2 Registers Controlling Regulator ............................................................................................. 962
CHAPTER 25 OPTION BYTE............................................................................................................... 964
25.1 Functions of Option Bytes ...................................................................................................... 964
25.1.1 User option byte (000C0H to 000C2H/010C0H to 010C2H)......................................................... 964
25.1.2 On-chip debug option byte (000C3H/ 010C3H)............................................................................ 965
25.2 Format of User Option Byte .................................................................................................... 965
25.3 Format of On-chip Debug Option Byte................................................................................... 967
25.4 Setting of Option Byte.............................................................................................................. 968
CHAPTER 26 FLASH MEMORY .......................................................................................................... 969
26.1 Writing with Flash Memory Programmer ............................................................................... 969
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26.2 Programming Environment ..................................................................................................... 979
26.3 Communication Mode .............................................................................................................. 979
26.4 Connection of Pins on Board.................................................................................................. 980
26.4.1 FLMD0 pin.................................................................................................................................... 980
26.4.2 TOOL0 pin.................................................................................................................................... 981
26.4.3 RESET pin.................................................................................................................................... 981
26.4.4 Port pins ....................................................................................................................................... 982
26.4.5 REGC pin ..................................................................................................................................... 982
26.4.6 X1 and X2 pins ............................................................................................................................. 982
26.4.7 Power supply................................................................................................................................ 982
26.5 Registers Controlling Flash Memory...................................................................................... 983
26.6 Programming Method .............................................................................................................. 983
26.6.1 Controlling flash memory.............................................................................................................. 983
26.6.2 Flash memory programming mode............................................................................................... 984
26.6.3 Selecting communication mode.................................................................................................... 985
26.6.4 Communication commands .......................................................................................................... 985
26.7 Security Settings ...................................................................................................................... 987
26.8 Processing Time of Each Command When Using PG-FP5 (Reference Values) ................ 989
26.9 Flash Memory Programming by Self-Programming ............................................................. 990
26.9.1 Boot swap function ....................................................................................................................... 992
26.9.2 Flash shield window function........................................................................................................ 994
CHAPTER 27 ON-CHIP DEBUG FUNCTION ..................................................................................... 995
27.1 Connecting QB-MINI2 to 78K0R/Kx3-L................................................................................... 995
27.2 On-Chip Debug Security ID ..................................................................................................... 996
27.3 Securing of User Resources ................................................................................................... 996
CHAPTER 28 BCD CORRECTION CIRCUIT ..................................................................................... 998
28.1 BCD Correction Circuit Function............................................................................................ 998
28.2 Registers Used by BCD Correction Circuit ........................................................................... 998
28.3 BCD Correction Circuit Operation .......................................................................................... 999
CHAPTER 29 INSTRUCTION SET...................................................................................................... 1001
29.1 Conventions Used in Operation List .................................................................................... 1002
29.1.1 Operand identifiers and specification methods........................................................................... 1002
29.1.2 Description of operation column ................................................................................................. 1003
29.1.3 Description of flag operation column .......................................................................................... 1004
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29.1.4 PREFIX instruction ..................................................................................................................... 1004
29.2 Operation List ......................................................................................................................... 1005
CHAPTER 30 ELECTRICAL SPECIFICATIONS (78K0R/KC3-L, 78K0R/KD3-L, 78K0R/KE3-L) ... 1022
30.1 Pins Mounted According to Product .................................................................................... 1022
30.1.1 Port functions ............................................................................................................................. 1022
30.1.2 Non-port functions ...................................................................................................................... 1023
30.2 Absolute Maximum Ratings .................................................................................................. 1024
30.3 Oscillator Characteristics...................................................................................................... 1026
30.3.1 Main system clock oscillator characteristics ............................................................................... 1026
30.3.2 Internal oscillator characteristics ................................................................................................ 1027
30.3.3 Sub system clock oscillator characteristics................................................................................. 1027
30.3.4 Recommended oscillator circuit constants ................................................................................. 1028
30.4 DC Characteristics ................................................................................................................. 1031
30.4.1 Pin characteristics ...................................................................................................................... 1031
30.4.2 Supply current characteristics .................................................................................................... 1038
30.5 AC Characteristics ................................................................................................................. 1043
30.5.1 Basic operation........................................................................................................................... 1043
30.5.2 Measurement conditions ............................................................................................................ 1048
30.6 Peripheral Functions Characteristics................................................................................... 1049
30.6.1 Serial array unit .......................................................................................................................... 1049
30.6.2 Serial interface IICA ................................................................................................................... 1067
30.6.3 On-chip debug (UART)............................................................................................................... 1067
30.6.4 A/D converter characteristics...................................................................................................... 1068
30.6.5 Programmable gain amplifier characteristics.............................................................................. 1068
30.6.6 Comparator characteristics......................................................................................................... 1069
30.6.7 POC circuit characteristics ......................................................................................................... 1070
30.6.8 Supply voltage rise time ............................................................................................................. 1071
30.6.9 LVI circuit characteristics............................................................................................................ 1072
30.7 Data Memory STOP Mode Low Supply Voltage Data Retention Characteristics............. 1073
30.8 Flash Memory Programming Characteristics...................................................................... 1073
CHAPTER 31 ELECTRICAL SPECIFICATIONS (78K0R/KF3-L, 78K0R/KG3-L) ............................ 1074
31.1 Pins Mounted According to Product .................................................................................... 1074
31.1.1 Port functions ............................................................................................................................. 1074
31.1.2 Non-port functions ...................................................................................................................... 1075
31.2 Absolute Maximum Ratings .................................................................................................. 1076
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31.3 Oscillator Characteristics...................................................................................................... 1078
31.3.1 Main system clock oscillator characteristics ............................................................................... 1078
31.3.2 Internal oscillator characteristics ................................................................................................ 1079
31.3.3 Sub system clock oscillator characteristics................................................................................. 1079
31.3.4 Recommended oscillator circuit constants ................................................................................. 1080
31.4 DC Characteristics ................................................................................................................. 1084
31.4.1 Pin characteristics ...................................................................................................................... 1084
31.4.2 Supply current characteristics .................................................................................................... 1091
31.5 AC Characteristics ................................................................................................................. 1096
31.5.1 Basic operation........................................................................................................................... 1096
31.5.2 Measurement conditions ............................................................................................................ 1101
31.6 Peripheral Functions Characteristics................................................................................... 1102
31.6.1 Serial array unit .......................................................................................................................... 1102
31.6.2 Serial interface IICA ................................................................................................................... 1120
31.6.3 On-chip debug (UART)............................................................................................................... 1120
31.6.4 A/D converter characteristics...................................................................................................... 1121
31.6.5 POC circuit characteristics ......................................................................................................... 1122
31.6.6 Supply voltage rise time ............................................................................................................. 1123
31.6.7 LVI circuit characteristics............................................................................................................ 1124
31.7 Data Memory STOP Mode Low Supply Voltage Data Retention Characteristics............. 1125
31.8 Flash Memory Programming Characteristics...................................................................... 1125
CHAPTER 32 PACKAGE DRAWINGS ............................................................................................... 1126
32.1 78K0R/KC3-L (40-pin products) ............................................................................................ 1126
32.2 78K0R/KC3-L (44-pin products) ............................................................................................ 1127
32.3 78K0R/KC3-L (48-pin products) ............................................................................................ 1128
32.4 78K0R/KD3-L........................................................................................................................... 1130
32.5 78K0R/KE3-L ........................................................................................................................... 1131
32.6 78K0R/KF3-L ........................................................................................................................... 1136
32.7 78K0R/KG3-L........................................................................................................................... 1138
CHAPTER 33 RECOMMENDED SOLDERING CONDITIONS......................................................... 1141
APPENDIX A DEVELOPMENT TOOLS............................................................................................. 1143
A.1 Software Package .................................................................................................................... 1147
A.2 Language Processing Software ............................................................................................. 1147
A.3 Control Software ...................................................................................................................... 1148
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A.4 Flash Memory Programming Tools........................................................................................ 1149
A.4.1 When using flash memory programmer PG-FP5 and FL-PR5 ..................................................... 1149
A.4.2 When using on-chip debug emulator with programming function QB-MINI2................................ 1149
A.5 Debugging Tools (Hardware).................................................................................................. 1150
A.5.1 When using in-circuit emulator..................................................................................................... 1150
A.5.2 When using on-chip debug emulator with programming function QB-MINI2................................ 1154
A.6 Debugging Tools (Software)................................................................................................... 1154
APPENDIX B REVISION HISTORY ................................................................................................... 1155
B.1 Major Revisions in This Edition ............................................................................................. 1155
B.2 Revision History of Preceding Editions ................................................................................ 1156
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78K0R/Kx3-L
RENESAS MCU
CHAPTER 1 OUTLINE
1.1 Features
{ Minimum instruction execution time can be changed from high speed (0.05 μs: @ 20 MHz operation with high-speed
system clock) to ultra low-speed (61 μs: @ 32.768 kHz operation with subsystem clock)
{ General-purpose register: 8 bits × 32 registers (8 bits × 8 registers × 4 banks)
{ ROM, RAM capacities
Flash ROM
RAM
78K0R/KC3-L
40 pins
256 KB
192 KB
128 KB
12 KB
44 pins
Note 1
10 KB
8 KB
Note 2
78K0R/KD3-L
48 pins
78K0R/KE3-L 78K0R/KF3-L 78K0R/KG3-L
52 pins
64 pins
80 pins
100 pins
−
−
−
μPD78F1028
μPD78F1030
−
−
−
μPD78F1027
μPD78F1029
−
−
−
μPD78F1012
μPD78F1014
96 KB
6 KB
−
−
−
μPD78F1011
μPD78F1013
64 KB
4 KB
−
−
−
μPD78F1010
−
μPD78F1003
μPD78F1006
μPD78F1009
−
−
48 KB
2 KB
μPD78F1002
μPD78F1005
μPD78F1008
−
−
32 KB
1.5 KB
μPD78F1001
μPD78F1004
μPD78F1007
−
−
16 KB
1 KB
−
−
−
−
3 KB
Note 3
μPD78F1000
−
Notes 1. This is 11 KB when the self-programming function is used.
2. This is 7 KB when the self-programming function is used.
3. This is 2 KB when the self-programming function is used.
{ On-chip internal high-speed oscillation clocks
• 20 MHz Internal high-speed oscillation clock: 20 MHz (TYP.)
• 8 MHz Internal high-speed oscillation clock: 8 MHz (TYP.)
• 1 MHz Internal high-speed oscillation clock: 1 MHz (TYP.)
{ On-chip single-power-supply flash memory (with prohibition of chip erase/block erase/writing function)
{ Self-programming (with boot swap function/flash shield window function)
{ On-chip debug function
{ On-chip power-on-clear (POC) circuit and low-voltage detector (LVI)
{ On-chip watchdog timer (operable with the dedicated internal low-speed oscillation clock)
{ On-chip multiplier/divider (16 bits × 16 bits, 32 bits ÷ 32 bits)
{ On-chip key interrupt function
{ On-chip clock output/buzzer output controller Note 1
{ On-chip BCD adjustment
{ I/O ports: 33 to 89 (N-ch open drain: 2/4Note 1)
{ Timer: 10/14 channels
• 16-bit timer:
8/12 channels
• Watchdog timer:
1 channel
• Real-time counter: 1 channelNote 2
Notes1. Those are not mounted onto 40-pin and 44-pin products of the 78K0R/KC3-L.
2. This is not mounted onto 40-pin product of the 78K0R/KC3-L.
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78K0R/Kx3-L
CHAPTER 1 OUTLINE
{ On-chip comparator/programmable gain amplifier function
Note 1
{ Serial interface
• CSI
• UART/UART (LIN-bus supported)
• I2C Note 2/simplified I2C
{ 10-bit resolution A/D converter (AVREF = 1.8 to 5.5 V): 10 to 16 channels
{ Power supply voltage: VDD = 1.8 to 5.5 V
{ Operating ambient temperature: TA = −40 to +85°C
Notes 1.
2.
Remark
78K0R/KC3-L, 78K0R/KD3-L, 78K0R/KE3-L only.
This is not mounted onto 40-pin and 44-pin products of the 78K0R/KC3-L
The pins mounted depend on the product. See 1.6 Block Diagram and 1.7 Outline of Functions.
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78K0R/Kx3-L
CHAPTER 1 OUTLINE
1.2 Applications
{ Audio visual equipment
{ Home appliances
{ Industrial equipment
1.3 Ordering Information
• Flash memory version (lead-free product)
78K0R/Kx3-L
Package
Part Number
Microcontroller
78K0R/KC3-L
78K0R/KD3-L
78K0R/KE3-L
78K0R/KF3-L
40-pin plastic WQFN (6 × 6)
μ PD78F1000K8-4B4-AXNote 1, 78F1001K8-4B4-AX Note 1,
44-pin plastic LQFP (10 × 10)
μ PD78F1000GB-GAF-AX, 78F1001GB-GAF-AX,
48-pin plastic TQFP (fine pitch) (7 × 7)
μ PD78F1001GA-HAA-AX, 78F1002GA-HAA-AX,
48-pin plastic WQFN (7 × 7)
μ PD78F1001K8-5B4-AX Note 1, 78F1002K8-5B4-AX Note 1,
52-pin plastic LQFP (10 × 10)
μ PD78F1004GB-GAG-AX, 78F1005GB-GAG-AX,
64-pin plastic LQFP (12 × 12)
μ PD78F1007GK-GAJ-AX, 78F1008GK-GAJ-AX,
64-pin plastic LQFP (fine pitch) (10 × 10)
μ PD78F1007GB-GAH-AX, 78F1008GB-GAH-AX,
64-pin plastic TQFP (fine pitch) (7 × 7)
μ PD78F1007GA-HAB-AX, 78F1008GA-HAB-AX,
64-pin plastic FBGA (5 × 5)
μ PD78F1007F1-AN1-A, 78F1008F1-AN1-A,
64-pin plastic FBGA (4 × 4)
μ PD78F1007F1-AA2-A, 78F1008F1- AA2-A,
64-pin plastic WQFN (9 × 9)
μ PD78F1007K8-6B4-AX Note 2, 78F1008K8- 6B4-AX Note 2,
80-pin plastic LQFP (14 × 14)
78F1002K8-4B4-AX Note 1, 78F1003K8-4B4-AX Note 1
78F1002GB-GAF-AX, 78F1003GB-GAF-AX
78F1003GA-HAA-AX
78F1003K8-5B4-AX Note 1
78F1006GB-GAG-AX
78F1009GK-GAJ-AX
78F1009GB-GAH-AX
78F1009GA-HAB-AX
78F1009F1-AN1-A
78F1009F1- AA2-A
78F1009K8- 6B4-AX Note 2
μ PD78F1010GC-GAD-AX, 78F1011GC-GAD-AX,
78F1012GC-GAD-AX, 78F1027GC-GAD-AX,
78F1028GC-GAD-AX
80-pin plastic LQFP (fine pitch) (12 × 12)
μ PD78F1010GK-GAK-AX, 78F1011GK-GAK-AX,
78F1012GK-GAK-AX, 78F1027GK-GAK-AX, 78F1028GKGAK-AX
78K0R/KG3-L
100-pin plastic LQFP (14 × 20)
100-pin plastic LQFP (fine pitch) (14 × 14)
100-pin plastic FBGA (6 × 6) Note 3
μ PD78F1013GF-GAS-AX, 78F1014GF-GAS-AX,
78F1029GF-GAS-AX, 78F1030GF-GAS-AX
μ PD78F1013GC-UEU-AX, 78F1014GC-UEU-AX,
78F1029GC-UEU-AX, 78F1030GC-UEU-AX
μ PD78F1013F1-BAK-A, 78F1014F1- BAK-A
Notes 1. Under development
2. Development cancellation
2. The μPD78F1029 and μPD78F1030 don’t have the FBGA package.
Caution The 78K0R/Kx3-L has an on-chip debug function, which is provided for development and evaluation.
Do not use the on-chip debug function in products designated for mass production, because the
guaranteed number of rewritable times of the flash memory may be exceeded when this function is
used, and product reliability therefore cannot be guaranteed. Renesas Electronics is not liable for
problems occurring when the on-chip debug function is used.
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24
78K0R/Kx3-L
CHAPTER 1 OUTLINE
1.4 Pin Configuration (Top View)
1.4.1 78K0R/KC3-L
P20/ANI0
P21/ANI1
P22/ANI2
P23/ANI3
P24/ANI4
P25/ANI5
P26/ANI6
P27/ANI7
P150/ANI8
P151/ANI9
• 40-pin plastic WQFN (6 × 6) (Under development)
40 39 38 37 36 35 34 33 32 31
P120/INTP0/EXLVI
P41/TOOL1
P40/TOOL0
RESET
FLMD0
P122/X2/EXCLK
P121/X1
REGC
VSS
VDD
30
29
28
27
26
25
24
23
22
21
1
2
3
4
5
6
7
8
9
10
AVSS
AVREF
P80/CMP0P/INTP3/PGAI
P81/CMP0M
P83/CMP1M
P10/TI02/TO02
P11/TI03/TO03
P12/TI04/TO04
P13/TI05/TO05
P50/TI06/TO06
P30/SO10/TxD1
P31/SI10/RxD1/SDA10/INTP1
P32/SCK10/SCL10/INTP2
P75/KR5/SCK00
P74/KR4/SI00/RxD0
P73/KR3/SO00/TxD0
P72/KR2/SCK01/INTP6
P71/KR1/SI01/INTP5
P70/KR0/SO01/INTP4
P51/TI07/TO07
11 12 13 14 15 16 17 18 19 20
Cautions 1. Make AVSS the same potential as VSS.
2. Connect the REGC pin to Vss via a capacitor (0.47 to 1 μF).
3. P20/ANI0 to P27/ANI7 and P151/ANI9 are set as analog inputs in the order of P151/ANI9, …,
P27/ANI7, …, P20/ANI0 by the A/D port configuration register (ADPC). When using P20/ANI0 to
P27/ANI7 and P151/ANI9 as analog inputs, start designing from P151/ANI9 (see 13.3 (6) A/D port
configuration register (ADPC) for details).
Remark
For pin identification, see 1.5 Pin Identification.
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78K0R/Kx3-L
CHAPTER 1 OUTLINE
P120/INTP0/EXLVI
P20/ANI0
P21/ANI1
P22/ANI2
P23/ANI3
P24/ANI4
P25/ANI5
P26/ANI6
P27/ANI7
P150/ANI8
P151/ANI9
• 44-pin plastic LQFP (10 × 10)
44 43 42 41 40 39 38 37 36 35 34
1
33
2
32
3
31
4
30
5
29
6
28
7
27
8
26
9
25
10
24
11
23
12 13 14 15 16 17 18 19 20 21 22
AVSS
AVREF
P80/CMP0P/INTP3/PGAI
P81/CMP0M
P82/CMP1P/INTP7
P83/CMP1M
P10/TI02/TO02
P11/TI03/TO03
P12/TI04/TO04/RTCDIV/RTCCL
P13/TI05/TO05
P50/TI06/TO06
P30/SO10/TxD1
P31/SI10/RxD1/SDA10/INTP1
P32/SCK10/SCL10/INTP2
P75/KR5/SCK00
P74/KR4/SI00/RxD0
P73/KR3/SO00/TxD0
P72/KR2/SCK01/INTP6
P71/KR1/SI01/INTP5
P70/KR0/SO01/INTP4
P52/RTC1HZ/SLTI/SLTO
P51/TI07/TO07
P41/TOOL1
P40/TOOL0
RESET
P124/XT2
P123/XT1
FLMD0
P122/X2/EXCLK
P121/X1
REGC
VSS
VDD
Cautions 1. Make AVSS the same potential as VSS.
2. Connect the REGC pin to Vss via a capacitor (0.47 to 1 μF).
3. P20/ANI0 to P27/ANI7 and P151/ANI9 are set as analog inputs in the order of P151/ANI9, …,
P27/ANI7, …, P20/ANI0 by the A/D port configuration register (ADPC). When using P20/ANI0 to
P27/ANI7 and P151/ANI9 as analog inputs, start designing from P151/ANI9 (see 13.3 (6) A/D port
configuration register (ADPC) for details).
Remark
For pin identification, see 1.5 Pin Identification.
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78K0R/Kx3-L
CHAPTER 1 OUTLINE
• 48-pin plastic TQFP (fine pitch) (7 × 7)
VDD
VSS
REGC
P121/X1
P122/X2/EXCLK
FLMD0
P123/XT1
P124/XT2
RESET
P40/TOOL0
P41/TOOL1
P120/INTP0/EXLVI
• 48-pin plastic WQFN (7 × 7) (Under development)
48 47 46 45 44 43 42 41 40 39 38 37
1
36
2
35
3
34
4
33
5
32
6
31
7
30
8
29
9
28
10
27
11
26
12
25
13 14 15 16 17 18 19 20 21 22 23 24
P140/PCLBUZ0
P20/ANI0
P21/ANI1
P22/ANI2
P23/ANI3
P24/ANI4
P25/ANI5
P26/ANI6
P27/ANI7
P150/ANI8
P151/ANI9
P152/ANI10
P51/TI07/TO07
P50/TI06/TO06
P13/TI05/TO05
P12/TI04/TO04/RTCDIV/RTCCL
P11/TI03/TO03
P10/TI02/TO02
P83/CMP1M
P82/CMP1P/INTP7
P81/CMP0M
P80/CMP0P/INTP3/PGAI
AVREF
AVSS
P60/SCL0
P61/SDA0
P30/SO10/TxD1
P31/SI10/RxD1/SDA10/INTP1
P32/SCK10/SCL10/INTP2
P75/KR5/SCK00
P74/KR4/SI00/RxD0
P73/KR3/SO00/TxD0
P72/KR2/SCK01/INTP6
P71/KR1/SI01/INTP5
P70/KR0/SO01/INTP4
P52/RTC1HZ/SLTI/SLTO
Cautions 1. Make AVSS the same potential as VSS.
2. Connect the REGC pin to Vss via a capacitor (0.47 to 1 μF).
3. P20/ANI0 to P27/ANI7 and P150/ANI8 to P152/ANI10 are set as analog inputs in the order of
P152/ANI10, …, P150/ANI8, P27/ANI7, …, P20/ANI0 by the A/D port configuration register (ADPC).
When using P20/ANI0 to P27/ANI7 and P150/ANI8 to P152/ANI10 as analog inputs, start designing
from P152/ANI10 (see 13.3 (6) A/D port configuration register (ADPC) for details).
Remark
For pin identification, see 1.5 Pin Identification.
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78K0R/Kx3-L
CHAPTER 1 OUTLINE
1.4.2 78K0R/KD3-L
P152/ANI10
P151/ANI9
P150/ANI8
P27/ANI7
P26/ANI6
P25/ANI5
P24/ANI4
P23/ANI3
P22/ANI2
P21/ANI1
P20/ANI0
P01/TO00
P00/TI00
• 52-pin plastic LQFP (10 × 10)
52 51 50 49 48 47 46 45 44 43 42 41 40
P140/PCLBUZ0
1
39
AVSS
P120/INTP0/EXLVI
2
38
AVREF
P41/TOOL1
3
37
P80/CMP0P/INTP3/PGAI
P40/TOOL0
4
36
P81/CMP0M
RESET
5
35
P82/CMP1P/INTP7
P124/XT2
6
34
P83/CMP1M
P123/XT1
7
33
P10/TI02/TO02
FLMD0
8
32
P11/TI03/TO03
P122/X2/EXCLK
9
31
P12/TI04/TO04/RTCDIV/RTCCL
P121/X1
10
30
P13/TI05/TO05
REGC
11
29
P50/TI06/TO06
VSS
12
28
P51/TI07/TO07
VDD
13
27
P52/RTC1HZ/SLTI/SLTO
P70/KR0/SO01/INTP4
P71/KR1/SI01/INTP5
P73/KR3/SO00/TxD0
P72/KR2/SCK01/INTP6
P74/KR4/SI00/RxD0
P75/KR5/SCK00
P76/KR6
P77/KR7
P32/SCK10/SCL10/INTP2
P31/SI10/RxD1/SDA10/INTP1
P61/SDA0
P30/SO10/TxD1
P60/SCL0
14 15 16 17 18 19 20 21 22 23 24 25 26
Cautions 1. Make AVSS the same potential as VSS.
2. Connect the REGC pin to Vss via a capacitor (0.47 to 1 μF).
3. P20/ANI0 to P27/ANI7 and P150/ANI8 to P152/ANI10 are set as analog inputs in the order of
P152/ANI10, …, P150/ANI8, P27/ANI7, …, P20/ANI0 by the A/D port configuration register (ADPC).
When using P20/ANI0 to P27/ANI7 and P150/ANI8 to P152/ANI10 as analog inputs, start designing
from P152/ANI10 (see 13.3 (6) A/D port configuration register (ADPC) for details).
Remark
For pin identification, see 1.5 Pin Identification.
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78K0R/Kx3-L
CHAPTER 1 OUTLINE
1.4.3 78K0R/KE3-L
• 64-pin plastic LQFP (12 × 12)
• 64-pin plastic LQFP (fine pitch) (10 × 10)
P140/PCLBUZ0
P141/PCLBUZ1
P00/TI00
P01/TO00
P20/ANI0
P21/ANI1
P22/ANI2
P23/ANI3
P24/ANI4
P25/ANI5
P26/ANI6
P27/ANI7
P150/ANI8
P151/ANI9
P152/ANI10
P153/ANI11
• 64-pin plastic TQFP (fine pitch) (7 × 7)
64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49
P120/INTP0/EXLVI
P43
P42
P41/TOOL1
P40/TOOL0
RESET
P124/XT2
P123/XT1
FLMD0
P122/X2/EXCLK
P121/X1
REGC
VSS
EVSS
VDD
EVDD
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
AVSS
AVREF
P80/CMP0P/INTP3/PGAI
P81/CMP0M
P82/CMP1P/INTP7
P83/CMP1M
P10/TI02/TO02
P11/TI03/TO03
P12/TI04/TO04/RTCDIV/RTCCL
P13/TI05/TO05
P14/TI06/TO06
P15/TI07/TO07
P16
P17
P50
P51
P60/SCL0
P61/SDA0
P30/SO10/TxD1
P31/SI10/RxD1/SDA10/INTP1
P32/SCK10/SCL10/INTP2
P33
P77/KR7
P76/KR6
P75/KR5/SCK00
P74/KR4/SI00/RxD0
P73/KR3/SO00/TxD0
P72/KR2/SCK01/INTP6
P71/KR1/SI01/INTP5
P70/KR0/SO01/INTP4
P53
P52/RTC1HZ/SLTI/SLTO
17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32
Cautions 1.
2.
3.
4.
Make AVSS and EVSS the same potential as VSS.
Make EVDD the same potential as VDD.
Connect the REGC pin to Vss via a capacitor (0.47 to 1 μF).
P20/ANI0 to P27/ANI7 and P150/ANI8 to P153/ANI11 are set as analog inputs in the order of
P153/ANI11, …, P150/ANI8, P27/ANI7, …, P20/ANI0 by the A/D port configuration register (ADPC).
When using P20/ANI0 to P27/ANI7 and P150/ANI8 to P153/ANI11 as analog inputs, start designing
from P153/ANI11 (see 13.3 (6) A/D port configuration register (ADPC) for details).
Remarks 1. For pin identification, see 1.5 Pin Identification.
2. When using the microcontroller for an application where the noise generated inside the microcontroller
must be reduced, it is recommended to supply separate powers to the VDD and EVDD pins and connect the
VSS and EVSS pins to separate ground lines.
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78K0R/Kx3-L
CHAPTER 1 OUTLINE
• 64-pin plastic FBGA (5 × 5)
• 64-pin plastic FBGA (4 × 4)
Top View
Bottom View
8
7
6
5
4
3
2
1
A
B
C D E
F
G H
H
G
F
E D
C
B A
Index mark
Pin No.
Name
Pin No.
Name
Pin No.
Name
Pin No.
Name
A1
P53
C1
P50
E1
P83/CMP1M
G1
AVREF
A2
P52/RTC1HZ/SLTI
/SLTO
C2
P71/KR1/SI01/INTP5
E2
P12/TI04/TO04
/RTCDIV/RTCCL
G2
P151/ANI9
A3
P72/KR2/SCK01
/INTP6
C3
P74/KR4/SI00/RxD0
E3
P11/TI03/TO03
G3
P150/ANI8
A4
P75/KR5/SCK00
C4
P17
E4
P10/TI02/TO02
G4
P26/ANI6
A5
P77/KR7
C5
P33
E5
P21/ANI1
G5
P23/ANI3
A6
P61/SDA0
C6
P31/SI10/RxD1
/SDA10/INTP1
E6
P41/TOOL1
G6
P20/ANI0
A7
P60/SCL0
C7
VSS
E7
RESET
G7
P00/TI00
A8
EVDD
C8
P121/X1
E8
FLMD0
G8
P124/XT2
B1
P51
D1
P15/TI07/TO07
F1
P80/CMP0P
H1
AVSS
B2
P70/KR0/SO01
/INTP4
D2
P14/TI06/TO06
F2
P81/CMP0M
H2
P153/ANI11
B3
P73/KR3/SO00/TxD0
D3
P13/TI05/TO05
F3
P82/CMP1P/INTP7
H3
P152/ANI10
B4
P76/KR6
D4
P16
F4
P25/ANI5
H4
P27/ANI7
B5
P32/SCK10/SCL10
/INTP2
D5
P42
F5
P22/ANI2
H5
P24/ANI4
B6
P30/SO10/TxD1
D6
P40/TOOL0
F6
P43
H6
P141/PCLBUZ1
B7
VDD
D7
REGC
F7
P01/TO00
H7
P140/PCLBUZ0
B8
EVSS
D8
P122/X2/EXCLK
F8
P123/XT1
H8
P120/INTP0/EXLVI
/INTP3/PGAI
Cautions 1. Make AVSS and EVSS the same potential as VSS.
2. Make EVDD the same potential as VDD.
3. Connect the REGC pin to VSS via a capacitor (0.47 to 1 μF).
Remarks 1. For pin identification, see 1.5 Pin Identification.
2. When using the microcontroller for an application where the noise generated inside the microcontroller
must be reduced, it is recommended to supply separate powers to the VDD and EVDD pins and connect
the VSS and EVSS pins to separate ground lines.
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CHAPTER 1 OUTLINE
1.4.4 78K0R/KF3-L
• 80-pin plastic LQFP (14 × 14)
P140/PCLBUZ0/INTP6
P142/SCK20/SCL20
P143/SI20/RxD2/SDA20
P144/SO20/TxD2
P02/SO10/TxD1
P03/SI10/RxD1/SDA10
P04/SCK10/SCL10
P130
P20/ANI0
P21/ANI1
P22/ANI2
P23/ANI3
P24/ANI4
P25/ANI5
P26/ANI6
P27/ANI7
P150/ANI8
P151/ANI9
P152/ANI10
P153/ANI11
• 80-pin plastic LQFP (fine pitch) (12 × 12)
80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61
P120/INTP0/EXLVI
P47
P46
P45/SO01
P44/SI01
P43/SCK01
P42/TI04/TO04
P41/TOOL1
P40/TOOL0
RESET
P124/XT2
P123/XT1
FLMD0
P122/X2/EXCLK
P121/X1
REGC
VSS
EVSS0
VDD
EVDD0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
60
59
58
57
56
55
54
53
52
51
50
49
48
47
46
45
44
43
42
41
AVSS
AVREF
P111
P110
P91
P90
P10/SCK00
P11/SI00/RxD0
P12/SO00/TxD0
P13/TxD3
P14/RxD3
P15/RTCDIV/RTCCL
P16/TI01/TO01/INTP5
P17/TI02/TO02
P55/PCLBUZ1/SO41Note/INTP7
P54/SI41Note/TI07/TO07
P53/SCK41Note/TI00
P52/SO40Note/TO00/TxD4Note
P51/SI40Note/RxD4Note/INTP2
P50/SCK40Note/INTP1
P60/SCL0
P61/SDA0
P62
P63
P31/TI03/TO03/INTP4
P64/TI10/TO10
P65/TI11/TO11
P66/TI12/TO12
P67/TI13/TO13
P77/KR7/INTP11
P76/KR6/INTP10
P75/KR5/INTP9
P74/KR4/INTP8
P73/KR3
P72/KR2
P71/KR1
P70/KR0
P06/TI06/TO06
P05/TI05/TO05
P30/INTP3/RTC1HZ
21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40
Note
SCK40, SCK41, SI40, SI41, SO40, SO41, TxD4, RxD4 pins are only mounted in the μ PD78F1027 and
78F1028.
Cautions 1.
2.
3.
4.
Make AVSS and EVSS0 the same potential as VSS.
Make EVDD0 the same potential as VDD.
Connect the REGC pin to Vss via a capacitor (0.47 to 1 μF: target).
P20/ANI0 to P27/ANI7 and P150/ANI8 to P153/ANI11 are set as analog inputs in the order of
P153/ANI11, …, P150/ANI8, P27/ANI7, …, P20/ANI0 by the A/D port configuration register (ADPC).
When using P20/ANI0 to P27/ANI7 and P150/ANI8 to P153/ANI11 as analog inputs, start designing
from P153/ANI11 (see 13.3 (6) A/D port configuration register (ADPC) for details).
Remarks 1. When using the microcontroller for an application where the noise generated inside the microcontroller
must be reduced, it is recommended to supply separate powers to the VDD and EVDD0 pins and connect
the VSS and EVSS0 pins to separate ground lines.
2. For pin identification, see 1.5 Pin Identification.
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78K0R/Kx3-L
CHAPTER 1 OUTLINE
1.4.5 78K0R/KG3-L
EVDD0
VDD
EVSS0
VSS
REGC
P121/X1
P122/X2/EXCLK
FLMD0
P123/XT1
P124/XT2
RESET
P40/TOOL0
P41/TOOL1
P42/TI04/TO04
P43/SCK01
P44/SI01
P45/SO01
P46/INTP1/TI05/TO05
P47/INTP2
P120/INTP0/EXLVI
• 100-pin plastic LQFP (14 × 20)
P140/PCLBUZ0/INTP6
P141/PCLBUZ1/INTP7
P142/SCK20/SCL20
P143/SI20/RxD2/SDA20
P144/SO20/TxD2
P145/TI07/TO07
P00/TI00
P01/TO00
P02/SO10/TxD1
P03/SI10/RxD1/SDA10
P04/SCK10/SCL10
P131/TI06/TO06
P130
P20/ANI0
P21/ANI1
P22/ANI2
P23/ANI3
P24/ANI4
P25/ANI5
P26/ANI6
P27/ANI7
P150/ANI8
P151/ANI9
P152/ANI10
P153/ANI11
P154/ANI12
P155/ANI13
P156/ANI14
P157/ANI15
AVSS
Note
100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81
1
80
2
79
3
78
4
77
5
76
6
75
7
74
8
73
9
72
10
71
11
70
12
69
13
68
14
67
15
66
16
65
17
64
18
63
19
62
20
61
21
60
22
59
23
58
24
57
25
56
26
55
27
54
28
53
29
52
30
51
31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50
P50/SCK40
P51/SI40Note/RxD4Note
P52/SO40Note/TxD4Note
P53/SCK41Note
P54/SI41Note
P55/SO41Note
P56
P57
P17/TI02/TO02
P16/TI01/TO01/INTP
P15/RTCDIV/RTCCL
P14/RxD3
P13/TxD3
P12/SO00/TxD0
P11/SI00/RxD0
P10/SCK00
P91
P110
P111
AVREF
P60/SCL0
P61/SDA0
P62
P63
P31/TI03/TO03/INTP4
P64/TI10/TO10
P65/TI11/TO11
P66/TI12/TO12
P67/TI13/TO13
P77/KR7/INTP11
P76/KR6/INTP10
P75/KR5/INTP9
P74/KR4/INTP8
P73/KR3
P72/KR2
P71/KR1
P70/KR0
P06
P05
EVSS1
P80
P81
P82
P83
P84
P85
P86
P87
P30/INTP3/RTC1HZ
EVDD1
Note
SCK40, SCK41, SI40, SI41, SO40, SO41, TxD4, RxD4 pins are only mounted in the μ PD78F1029 and
78F1030.
Cautions 1.
2.
3.
4.
Make AVSS, EVSS0, and EVSS1 the same potential as VSS.
Make EVDD0 and EVDD1 the same potential as VDD.
Connect the REGC pin to Vss via a capacitor (0.47 to 1 μF: target).
P20/ANI0 to P27/ANI7 and P150/ANI8 to P157/ANI15 are set as analog inputs in the order of
P157/ANI15, …, P150/ANI8, P27/ANI7, …, P20/ANI0 by the A/D port configuration register (ADPC).
When using P20/ANI0 to P27/ANI7 and P150/ANI8 to P157/ANI15 as analog inputs, start designing
from P157/ANI15 (see 13.3 (6) A/D port configuration register (ADPC) for details).
Remarks 1. When using the microcontroller for an application where the noise generated inside the microcontroller
must be reduced, it is recommended to supply separate powers to the VDD and two EVDD pins and
connect the VSS and two EVSS pins to separate ground lines.
2. For pin identification, see 1.5 Pin Identification.
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Mar 31, 2011
32
78K0R/Kx3-L
CHAPTER 1 OUTLINE
P143/SI20/RxD2/SDA20
P144/SO20/TxD2
P145/TI07/TO07
P00/TI00
P01/TO00
P02/SO10/TxD1
P03/SI10/RxD1/SDA10
P04/SCK10/SCL10
P131/TI06/TO06
P130
P20/ANI0
P21/ANI1
P22/ANI2
P23/ANI3
P24/ANI4
P25/ANI5
P26/ANI6
P27/ANI7
P150/ANI8
P151/ANI9
P152/ANI10
P153/ANI11
P154/ANI12
P155/ANI13
P156/ANI14
• 100-pin plastic LQFP (fine pitch) (14 × 14)
100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 80 79 78 77 76
75
1
2
74
3
73
4
72
5
71
6
70
7
69
8
68
9
67
10
66
11
65
12
64
13
63
14
62
15
61
16
60
17
59
18
58
19
57
20
56
21
55
22
54
23
53
52
24
51
25
26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50
P157/ANI15
AVSS
AVREF
P111
P110
P91
P10/SCK00
P11/SI00/RxD0
P12/SO00/TxD0
P13/TxD3
P14/RxD3
P15/RTCDIV/RTCCL
P16/TI01/TO01/INTP5
P17/TI02/TO02
P57
P56
P55/SO41Note
P54/SI41Note
P53/SCK41Note
P52/SO40Note/TxD4Note
P51/SI40Note/RxD4Note
Note
P50/SCK40
EVDD1
P30/INTP3/RTC1HZ
P87
P62
P63
P31/TI03/TO03/INTP4
P64/TI10/TO10
P65/TI11/TO11
P66/TI12/TO12
P67/TI13/TO13
P77/KR7/INTP11
P76/KR6/INTP10
P75/KR5/INTP9
P74/KR4/INTP8
P73/KR3
P72/KR2
P71/KR1
P70/KR0
P06
P05
EVSS1
P80
P81
P82
P83
P84
P85
P86
P142/SCK20/SCL20
P141/PCLBUZ1/INTP7
P140/PCLBUZ0/INTP6
P120/INTP0/EXLVI
P47/INTP2
P46/INTP1/TI05/TO05
P45/SO01
P44/SI01
P43/SCK01
P42/TI04/TO04
P41/TOOL1
P40/TOOL0
RESET
P124/XT2
P123/XT1
FLMD0
P122/X2/EXCLK
P121/X1
REGC
VSS
EVSS0
VDD
EVDD0
P60/SCL0
P61/SDA0
Note
SCK40, SCK41, SI40, SI41, SO40, SO41, TxD4, RxD4 pins are only mounted in the 48-pin products of the μ
PD78F1029 and 78F1030.
Cautions 1.
2.
3.
4.
Make AVSS, EVSS0, and EVSS1 the same potential as VSS.
Make EVDD0 and EVDD1 the same potential as VDD.
Connect the REGC pin to Vss via a capacitor (0.47 to 1 μF: target).
P20/ANI0 to P27/ANI7 and P150/ANI8 to P157/ANI15 are set as analog inputs in the order of
P157/ANI15, …, P150/ANI8, P27/ANI7, …, P20/ANI0 by the A/D port configuration register (ADPC).
When using P20/ANI0 to P27/ANI7 and P150/ANI8 to P157/ANI15 as analog inputs, start designing
from P157/ANI15 (see 13.3 (6) A/D port configuration register (ADPC) for details).
Remarks 1. When using the microcontroller for an application where the noise generated inside the microcontroller
must be reduced, it is recommended to supply separate powers to the VDD and two EVDD pins and
connect the VSS and two EVSS pins to separate ground lines.
2. For pin identification, see 1.5 Pin Identification.
R01UH0106EJ0400 Rev.4.00
Mar 31, 2011
33
78K0R/Kx3-L
CHAPTER 1 OUTLINE
• 100-pin plastic FBGA (6 × 6)
Note
Top View
Bottom View
10
9
8
7
6
5
4
3
2
1
A
B
C D E
F
G H
I
J
A
B
C D E
F
G H
I
J
Index mark
Pin No.
Name
Pin No.
Name
Pin No.
Name
Pin No.
Name
A1
P86
C6
P72/KR2
F1
P15/RTCDIV/RTCCL
H6
P20/ANI0
A2
P84
C7
P75/KR5/INTP9
F2
P14/RxD3
H7
P00/TI00
A3
EVSS1
C8
P77/KR7/INTP11
F3
P13/TxD3
H8
P142/SCK20/SCL20
A4
P05
C9
VDD
F4
P12/SO00/TxD0
H9
P42/TI04/TO04
A5
P63
C10
EVDD0
F5
P11/SI00/RxD0
H10
P124/XT2
A6
P62
D1
P50
F6
P04/SCK10/SCL10
J1
P156/ANI14
A7
P61/SDA0
D2
P51
F7
P44/SI01
J2
P157/ANI15
A8
P60/SCL0
D3
P52
F8
P45/SO01
J3
P152/ANI10
A9
P65/TI11/TO11
D4
P53
F9
FLMD0
J4
P27/ANI7
A10
P64/TI10/TO10
D5
P54
F10
VSS
J5
P24/ANI4
B1
P87
D6
P73/KR3
G1
P130
J6
P21/ANI1
B2
P85
D7
P76/KR6/INTP10
G2
P91
J7
P01/TO00
B3
P83
D8
P40/TOOL0
G3
P110
J8
P144/SO20/TxD2
B4
P81
D9
EVSS0
G4
P111
J9
P47/INTP2
B5
P06
D10
P121/X1
G5
P10/SCK00
J10
B6
P71/KR1
E1
P55
G6
P03/SI10/RxD1/SDA10 K1
P155/ANI13
B7
P74/KR4/INTP8
E2
P56
G7
P02/SO10/TxD1
K2
P154/ANI12
B8
P67/TI13/TO13
E3
P57
G8
P46/TI05/TO05/INTP1 K3
P153/ANI11
B9
P66/TI12/TO12
E4
P17/TI02/TO02
G9
RESET
K4
P150/ANI8
B10
P31/TI03/TO03/INTP4 E5
P16/TI01/TO01/INTP5 G10
P123/XT1
K5
P25/ANI5
C1
EVDD1
E6
P13/TI06/TO06
H1
AVREF
K6
P22/ANI2
C2
P30/RTC1HZ/INTP3
E7
P41/TOOL1
H2
AVSS
K7
P145/TI07/TO07
P120/INTP0/EXLVI
C3
P82
E8
P43/SCK01
H3
P151/ANI9
K8
P143/SI20/RxD2/SDA20
C4
P80
E9
REGC
H4
P26/ANI6
K9
P141/PCLBUZ1/INTP7
C5
P70/KR0
E10
P122/X2/EXCLK
H5
P23/ANI3
K10
P140/PCLBUZ0/INTP6
Note μPD78F1013 and μPD78F1014 only
Cautions 1. Make AVSS, EVSS0, and EVSS1 the same potential as VSS.
2. Make EVDD0 and EVDD1 the same potential as VDD.
3. Connect the REGC pin to Vss via a capacitor (0.47 to 1 μF: target).
Remarks 1. When using the microcontroller for an application where the noise generated inside the microcontroller
must be reduced, it is recommended to supply separate powers to the VDD and two EVDD pins and
connect the VSS and two EVSS pins to separate ground lines.
2. For pin identification, see 1.5 Pin Identification.
R01UH0106EJ0400 Rev.4.00
Mar 31, 2011
34
78K0R/Kx3-L
CHAPTER 1 OUTLINE
1.5 Pin Identification
ANI0-ANI15:
Analog Input
AVREF:
Analog Reference Voltage
AVSS :
Analog Ground
CMP0M, CMP1M:
Comparator Input (Minus)
CMP0P, CMP1P:
Comparator Input (Plus)
Buzzer Output
PGAI:
Programmable Gain Amplifier
REGC:
Regulator Capacitance
Input
RESET:
Reset
RTC1HZ:
Real-time Counter Correction Clock
Ground for Port
RTCCL:
(1 Hz) Output
EVSS, EVSS0,
EVSS1:
EXCLK:
Real-time Counter Clock (32 kHz
Original Oscillation) Output
External Clock Input
(Main System Clock)
EXLVI:
Programmable Clock Output/
Power Supply for Port
EVDD, EVDD0,
EVDD1:
PCLBUZ0, PCLBUZ1:
RTCDIV:
Real-time Counter Clock (32 kHz
Divided Frequency) Output
External Potential Input
for Low-voltage Detector
RxD0 to RxD4:
FLMD0:
Flash Programming Mode
SCK00, SCK01, SCK10,
INTP0 to INTP11:
External Interrupt Input
SCK20, SCK40, SCK41:
KR0 to KR7:
Key Return
SCL0, SCL10, SCL20:
Serial Clock Input/Output
P00 to P06:
Port 0
SDA0, SDA10, SDA20:
Serial Data Input/Output
P10 to P17:
Port 1
SI00, SI01, SI10, SI20,
P20 to P27:
Port 2
SI40, SI41:
Serial Data Input
P30 to P33:
Port 3
SLTI:
Selectable Timer Input
P40 to P47:
Port 4
SLTO:
Selectable Timer Output
P50 to P57:
Port 5
SO00, SO01, SO10,
Serial Data Output
P60 to P67:
Port 6
SO20, SO40, SO41:
Serial Data Output
P70 to P77:
Port 7
TI00 to TI07, TI10 to TI13: Timer Input
P80 to P87:
Port 8
TO00 to TO07,
P90, P91:
Port 9
TO10 to TO13:
Timer Output
P110, P111:
Port 11
TOOL0:
Data Input/Output for Tool
P120 to P124:
Port 12
TOOL1:
Clock Output for Tool
P130, P131:
Port 13
TxD0 to TxD4:
Transmit Data
P140 to P145:
Port 14
VDD:
Power Supply
P150 to P157:
Port 15
VSS:
Ground
R01UH0106EJ0400 Rev.4.00
Mar 31, 2011
Receive Data
Serial Clock Input/Output
X1, X2:
Crystal Oscillator (Main System Clock)
XT1, XT2:
Crystal Oscillator (Subsystem Clock)
35
78K0R/Kx3-L
CHAPTER 1 OUTLINE
1.6 Block Diagram
1.6.1 78K0R/KC3-L
• 40-pin products
TIMER ARRAY
UNIT (8ch)
ch0
PORT 1
4
P10 to P13
PORT 2
8
P20 to P27
PORT 3
3
P30 to P32
PORT 4
2
P40, P41
PORT 5
2
P50, P51
PORT 7
6
P70 to P75
PORT 8
3
P80, P81, P83
2
P121, P122
2
P150, P151
ch1
TI02/TO02/P10
ch2
TI03/TO03/P11
ch3
TI04/TO04/P12
ch4
TI05/TO05/P13
ch5
TI06/TO06/P50
ch6
TI07/TO07/P51
RxD0/P74 (LINSEL)
ch7
PORT 12
PORT 15
LOW-SPEED
INTERNAL
OSCILLATOR
WINDOW
WATCHDOG
TIMER
A/D CONVERTER
P120
8
ANI0/P20 to
ANI7/P27
2
ANI8/P150,
ANI9/P151
AVREF
AVSS
CMP0M/P81,
CMP1M/P83
2
COMPARATOR
PROGRAMMABLE
GAIN AMPLIFIER
CMP0P/P80
KEY RETURN
SERIAL ARRAY
UNIT (4ch)
RxD0/P74
TxD0/P73
UART0
LINSEL
RxD1/P31
TxD1/P30
UART1
78K0R
CPU
CORE
FLASH
MEMORY
POWER ON CLEAR/
LOW VOLTAGE
INDICATOR
PGAI/P80
KR0/P70 to
KR5/P75
6
POC/LVI
CONTROL
EXLVI/P120
RESET CONTROL
SCK00/P75
SI00/P74
SO00/P73
SCK01/P72
SI01/P71
SO01/P70
CSI00
TOOL0/P40
TOOL1/P41
ON-CHIP DEBUG
CSI01
RAM
SCK10/P32
SI10/P31
SO10/P30
CSI10
SCL10/P32
SDA10/P31
IIC10
SYSTEM
CONTROL
VOLTAGE
REGULATOR
MULTIPLIER&
DIVIDER
DIRECT MEMORY
ACCESS CONTROL
BCD
ADJUSTMENT
RESET
X1/P121
X2/EXCLK/P122
HIGH-SPEED
INTERNAL
OSCILLATOR
VDD
VSS
REGC
FLMD0
2
INTERRUPT
CONTROL
INTP3/P80
3
R01UH0106EJ0400 Rev.4.00
Mar 31, 2011
RxD0/P74 (LINSEL)
INTP0/P120
INTP1/P31,
INTP2/P32
INTP4/P70,
INTP5/P71,
INTP6/P72
36
78K0R/Kx3-L
CHAPTER 1 OUTLINE
• 44-pin products
TIMER ARRAY
UNIT (8ch)
PORT 1
4
P10 to P13
PORT 2
8
P20 to P27
PORT 3
3
P30 to P32
PORT 4
2
P40, P41
PORT 5
3
P50 to P52
PORT 7
6
P70 to P75
PORT 8
4
P80 to P83
4
P121 to P124
2
P150, P151
8
ANI0/P20 to
ANI7/P27
2
ANI8/P150,
ANI9/P151
ch0
SLTI/SLTO/P52
ch1
TI02/TO02/P10
ch2
TI03/TO03/P11
ch3
TI04/TO04/P12
ch4
TI05/TO05/P13
ch5
TI06/TO06/P50
ch6
TI07/TO07/P51
RxD0/P74 (LINSEL)
ch7
PORT 12
LOW-SPEED
INTERNAL
OSCILLATOR
PORT 15
WINDOW
WATCHDOG
TIMER
RTCDIV/RTCCL/P12
A/D CONVERTER
P120
REALTIME COUNTER
RTC1HZ/P52
CMP0M/P81,
CMP1M/P83
2
CMP0P/P80,
CMP1P/P82
2
AVREF
AVSS
PROGRAMMABLE
GAIN AMPLIFIER
COMPARATOR
78K0R
CPU
CORE
FLASH
MEMORY
SERIAL ARRAY
UNIT (4ch)
RxD0/P74
TxD0/P73
UART0
LINSEL
RxD1/P31
TxD1/P30
UART1
KEY RETURN
POWER ON CLEAR/
LOW VOLTAGE
INDICATOR
PGAI/P80
KR0/P70 to
KR5/P75
6
POC/LVI
CONTROL
EXLVI/P120
RESET CONTROL
RAM
SCK00/P75
SI00/P74
SO00/P73
SCK01/P72
SI01/P71
SO01/P70
CSI00
TOOL0/P40
TOOL1/P41
ON-CHIP DEBUG
CSI01
SYSTEM
CONTROL
SCK10/P32
SI10/P31
SO10/P30
CSI10
SCL10/P32
SDA10/P31
IIC10
RESET
X1/P121
X2/EXCLK/P122
HIGH-SPEED
INTERNAL
OSCILLATOR
XT1/P123
XT2/P124
VOLTAGE
REGULATOR
REGC
MULTIPLIER&
DIVIDER
VDD
DIRECT MEMORY
ACCESS CONTROL
BCD
ADJUSTMENT
R01UH0106EJ0400 Rev.4.00
Mar 31, 2011
VSS
FLMD0
2
INTERRUPT
CONTROL
2
3
RxD0/P74 (LINSEL)
INTP0/P120
INTP1/P31,
INTP2/P32
INTP3/P80,
INTP7/P82
INTP4/P70,
INTP5/P71,
INTP6/P72
37
78K0R/Kx3-L
CHAPTER 1 OUTLINE
• 48-pin products
TIMER ARRAY
UNIT (8ch)
PORT 1
4
P10 to P13
PORT 2
8
P20 to P27
PORT 3
3
P30 to P32
PORT 4
2
P40, P41
PORT 5
3
P50 to P52
ch0
SLTI/SLTO/P52
ch1
TI02/TO02/P10
ch2
TI03/TO03/P11
ch3
TI04/TO04/P12
ch4
TI05/TO05/P13
ch5
PORT 6
2
P60, P61
TI06/TO06/P50
ch6
PORT 7
6
P70 to P75
TI07/TO07/P51
RxD0/P74 (LINSEL)
ch7
PORT 8
4
P80 to P83
4
P121 to P124
LOW-SPEED
INTERNAL
OSCILLATOR
PORT 12
PORT 14
WINDOW
WATCHDOG
TIMER
PORT 15
RTCDIV/RTCCL/P12
CMP0P/P80,
CMP1P/P82
2
A/D CONVERTER
2
78K0R
CPU
CORE
P150-P152
8
ANI0/P20 to
ANI7/P27
3
ANI8/P150 to
ANI10/P152
AVREF
AVSS
FLASH
MEMORY
PROGRAMMABLE
GAIN AMPLIFIER
RxD0/P74
TxD0/P73
UART0
LINSEL
KEY RETURN
RxD1/P31
TxD1/P30
UART1
POWER ON CLEAR/
LOW VOLTAGE
INDICATOR
RAM
CSI00
CSI01
RESET CONTROL
SCK10/P32
SI10/P31
SO10/P30
CSI10
ON-CHIP DEBUG
SCL10/P32
SDA10/P31
IIC10
SYSTEM
CONTROL
SDA0/P61
SCL0/P60
3
COMPARATOR
SERIAL ARRAY
UNIT (4ch)
SCK00/P75
SI00/P74
SO00/P73
SCK01/P72
SI01/P71
SO01/P70
P140
REALTIME COUNTER
RTC1HZ/P52
CMP0M/P81,
CMP1M/P83
P120
SERIAL
INTERFACE IICA
BUZZER OUTPUT
PGAI/P80
KR0/P70 to
KR5/P75
6
POC/LVI
CONTROL
TOOL0/P40
TOOL1/P41
RESET
X1/P121
X2/EXCLK/P122
HIGH-SPEED
INTERNAL
OSCILLATOR
VDD
VSS
XT1/P123
XT2/P124
FLMD0
VOLTAGE
REGULATOR
REGC
PCLBUZ0/P140
CLOCK OUTPUT
CONTROL
2
MULTIPLIER&
DIVIDER
DIRECT MEMORY
ACCESS CONTROL
EXLVI/P120
INTERRUPT
CONTROL
2
3
RxD0/P74 (LINSEL)
INTP0/P120
INTP1/P31,
INTP2/P32
INTP3/P80,
INTP7/P82
INTP4/P70,
INTP5/P71,
INTP6/P72
BCD
ADJUSTMENT
R01UH0106EJ0400 Rev.4.00
Mar 31, 2011
38
78K0R/Kx3-L
CHAPTER 1 OUTLINE
1.6.2 78K0R/KD3-L
TIMER ARRAY
UNIT (8ch)
PORT 0
2
P00, P01
TI00/P00
TO00/P01
ch0
PORT 1
4
P10 to P13
SLTI/SLTO/P52
ch1
PORT 2
8
P20 to P27
TI02/TO02/P10
ch2
PORT 3
3
P30 to P32
TI03/TO03/P11
ch3
PORT 4
2
P40, P41
TI04/TO04/P12
ch4
TI05/TO05/P13
ch5
PORT 5
3
P50 to P52
TI06/TO06/P50
ch6
PORT 6
2
P60, P61
TI07/TO07/P51
RxD0/P74 (LINSEL)
ch7
PORT 7
8
P70 to P77
PORT 8
4
P80 to P83
4
P121 to P124
LOW-SPEED
INTERNAL
OSCILLATOR
PORT 12
WINDOW
WATCHDOG
TIMER
RTCDIV/RTCCL/P12
CMP0M/P81,
CMP1M/P83
CMP0P/P80,
CMP1P/P82
PORT 14
REALTIME COUNTER
RTC1HZ/P52
P120
PORT 15
2
P140
3
P150 to P152
8
ANI0/P20 to
ANI7/P27
3
ANI8/P150 to
ANI10/P152
COMPARATOR
2
78K0R
CPU
CORE
FLASH
MEMORY
A/D CONVERTER
AVREF
AVSS
SERIAL ARRAY
UNIT (4ch)
RxD0/P74
TxD0/P73
UART0
LINSEL
RxD1/P31
TxD1/P30
UART1
SCK00/P75
SI00/P74
SO00/P73
SCK01/P72
SI01/P71
SO01/P70
SCK10/P32
SI10/P31
SO10/P30
SCL10/P32
SDA10/P31
PROGRAMMABLE
GAIN AMPLIFIER
KEY RETURN
PGAI/P80
KR0/P70 to
KR7/P77
8
RAM
POWER ON CLEAR/
LOW VOLTAGE
INDICATOR
CSI00
POC/LVI
CONTROL
CSI01
RESET CONTROL
CSI10
TOOL0/P40
TOOL1/P41
ON-CHIP DEBUG
IIC10
SYSTEM
CONTROL
SDA0/P61
SCL0/P60
EXLVI/P120
SERIAL
INTERFACE IICA
VDD
VSS
FLMD0
RESET
X1/P121
X2/EXCLK/P122
HIGH-SPEED
INTERNAL
OSCILLATOR
XT1/P123
XT2/P124
BUZZER OUTPUT
PCLBUZ0/P140
CLOCK OUTPUT
CONTROL
VOLTAGE
REGULATOR
MULTIPLIER&
DIVIDER
DIRECT MEMORY
ACCESS CONTROL
REGC
2
INTERRUPT
CONTROL
2
3
BCD
ADJUSTMENT
R01UH0106EJ0400 Rev.4.00
Mar 31, 2011
RxD0/P74 (LINSEL)
INTP0/P120
INTP1/P31,
INTP2/P32
INTP3/P80,
INTP7/P82
INTP4/P70,
INTP5/P71,
INTP6/P72
39
78K0R/Kx3-L
CHAPTER 1 OUTLINE
1.6.3 78K0R/KE3-L
TIMER ARRAY
UNIT (8ch)
PORT 0
2
P00, P01
TI00/P00
TO00/P01
ch0
PORT 1
8
P10 to P17
SLTI/SLTO/P52
ch1
PORT 2
8
P20 to P27
TI02/TO02/P10
ch2
PORT 3
4
P30 to P33
TI03/TO03/P11
ch3
PORT 4
4
P40 to P43
TI04/TO04/P12
ch4
TI05/TO05/P13
ch5
PORT 5
4
P50 to P53
TI06/TO06/P14
ch6
PORT 6
2
P60, P61
TI07/TO07/P15
RxD0/P74 (LINSEL)
ch7
PORT 7
8
P70 to P77
PORT 8
4
P80 to P83
4
P121 to P124
LOW-SPEED
INTERNAL
OSCILLATOR
PORT 12
WINDOW
WATCHDOG
TIMER
RTCDIV/RTCCL/P12
CMP0M/P81,
CMP1M/P83
CMP0P/P80,
CMP1P/P82
P140
P141
PORT 14
REALTIME COUNTER
RTC1HZ/P52
P120
PORT 15
2
4
P150 to P153
8
ANI0/P20 to
ANI7/P27
4
ANI8/P150 to
ANI11/P153
COMPARATOR
2
78K0R
CPU
CORE
FLASH
MEMORY
A/D CONVERTER
AVREF
AVSS
SERIAL ARRAY
UNIT (4ch)
RxD0/P74
TxD0/P73
UART0
LINSEL
RxD1/P31
TxD1/P30
UART1
PROGRAMMABLE
GAIN AMPLIFIER
KEY RETURN
PGAI/P80
KR0/P70 to
KR7/P77
8
RAM
SCK00/P75
SI00/P74
SO00/P73
SCK01/P72
SI01/P71
SO01/P70
POWER ON CLEAR/
LOW VOLTAGE
INDICATOR
CSI00
POC/LVI
CONTROL
EXLVI/P120
CSI01
RESET CONTROL
SCK10/P32
SI10/P31
SO10/P30
CSI10
TOOL0/P40
TOOL1/P41
ON-CHIP DEBUG
SCL10/P32
SDA10/P31
IIC10
SYSTEM
CONTROL
SDA0/P61
SCL0/P60
SERIAL
INTERFACE IICA
VDD,
EVDD
VSS, FLMD0
EVSS
RESET
X1/P121
X2/EXCLK/P122
HIGH-SPEED
INTERNAL
OSCILLATOR
XT1/P123
XT2/P124
BUZZER OUTPUT
PCLBUZ0/P140,
PCLBUZ1/P141
2
CLOCK OUTPUT
CONTROL
VOLTAGE
REGULATOR
MULTIPLIER&
DIVIDER
DIRECT MEMORY
ACCESS CONTROL
REGC
2
INTERRUPT
CONTROL
2
2
BCD
ADJUSTMENT
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RxD0/P74 (LINSEL)
INTP0/P120
INTP1/P31,
INTP2/P32
INTP3/P80,
INTP7/P82
INTP4/P70,
INTP5/P71
INTP6/P72
40
78K0R/Kx3-L
CHAPTER 1 OUTLINE
1.6.4 78K0R/KF3-L
TIMER ARRAY
UNIT0 (8 ch)
TI00/P53
TO00/P52
ch0
TI01/TO01/P16
ch1
TI02/TO02/P17
ch2
TI03/TO03/P31
ch3
TI04/TO04/P42
ch4
TI05/TO05/P05
ch5
TI06/TO06/P06
ch6
TI07/TO07/P54
RxD3/P14 (LINSEL)
ch7
TIMER ARRAY
UNIT1 (4 ch)
TI10/TO10/P64
ch0
TI11/TO11/P65
ch1
TI12/TO12/P66
ch2
TI13/TO13/P67
ch3
PORT 0
5
P02 to P06
PORT 1
8
P10 to P17
PORT 2
8
P20 to P27
PORT 3
2
P30, P31
PORT 4
8
P40 to P47
PORT 5
6
P50 to P55
PORT 6
8
P60 to P67
PORT 7
8
P70 to P77
PORT 9
2
P90, P91
PORT 11
2
PORT 12
WINDOW
WATCHDOG
TIMER
78K0R
CPU
CORE
PORT 14
4
P140, P142 to P144
PORT 15
4
P150 to P153
SERIAL ARRAY
UNIT0 (4 ch)
UART1
SCK00/P10
SI00/P11
SO00/P12
CSI00
SCK01/P43
SI01/P44
SO01/P45
CSI01
PCLBUZ0/P140
PCLBUZ1/P55
CLOCK OUTPUT
CONTROL
RTC1HZ/P30
RxD1/P03
TxD1/P02
P130
BUZZER OUTPUT
REALTIME COUNTER
UART0
P121 to P124
FLASH
MEMORY
RTCDIV/RTCCL/P15
RxD0/P11
TxD0/P12
4
PORT 13
LOW-SPEED
INTERNAL
OSCILLATOR
P110, P111
P120
A/D CONVERTER
RAM
8
ANI0/P20 to
ANI7/P27
4
ANI8/P150 to
ANI11/P153
AVREF
AVSS
KEY RETURN
8
KR0/P70 to
KR7/P77
DIRECT MEMORY
ACCESS CONTROL
SCK10/P04
SI10/P03
SO10/P02
SCL10/P04
SDA10/P03
SERIAL ARRAY
UNIT2 (2 ch)Note
IIC10
CSI40
SCK40/P50
SI40/RxD4/P51
SO40/TxD4/P52
CSI41
SCK41/P53
SI41/P54
SO41/P55
MULTIPLIER&
DIVIDER
UART4
RxD4/P51
TxD4/P52
ON-CHIP DEBUG
SERIAL ARRAY
UNIT1 (4 ch)
SCK20/P142
SI20/P143
SO20/P144
CSI20
SCL20/P142
SDA20/P143
IIC20
RxD2/P143
TxD2/P144
UART2
UART3
RxD3/P14
TxD3/P13
LINSEL
SCL0/P60
SDA0/P61
POWER ON CLEAR/
LOW VOLTAGE
INDICATOR
CSI10
SERIAL
INTERFACE IICA
POC/LVI
CONTROL
EXLVI/P120
RESET CONTROL
TOOL0/P40
TOOL1/P41
BCD
ADJUSTMENT
VDD,
VSS, FLMD0
EVDD0 EVSS0
SYSTEM
CONTROL
HIGH-SPEED
INTERNAL
OSCILLATOR
RESET
X1/P121
X2/EXCLK/P122
XT1/P123
XT2/P124
RxD3/P14 (LINSEL)
INTP0/P120
INTP1/P50,
INTP2/P51
2
INTP3/P30,
INTP4/P31
2
INTP5/P16
VOLTAGE
REGULATOR
REGC
INTERRUPT
CONTROL
INTP6/P140
INTP7/P55
INTP8/P74 to
INTP11/P77
Note
4
Serial array unit 2 is only mounted in the μ PD78F1027 and 78F1028.
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78K0R/Kx3-L
CHAPTER 1 OUTLINE
1.6.5 78K0R/KG3-L
TIMER ARRAY
UNIT0 (8 ch)
TI00/P00
TO00/P01
ch0
TI01/TO01/P16
ch1
TI02/TO02/P17
ch2
TI03/TO03/P31
ch3
TI04/TO04/P42
ch4
TI05/TO05/P46
ch5
TI06/TO06/P131
ch6
TI07/TO07/P145
RxD3/P14 (LINSEL)
ch7
TIMER ARRAY
UNIT1 (4 ch)
TI10/TO10/P64
ch0
TI11/TO11/P65
ch1
TI12/TO12/P66
ch2
TI13/TO13/P67
ch3
PORT 0
7
P00 to P06
PORT 1
8
P10 to P17
PORT 2
8
P20 to P27
PORT 3
2
P30, P31
PORT 4
8
P40 to P47
PORT 5
8
P50 to P57
PORT 6
8
P60 to P67
PORT 7
8
P70 to P77
PORT 8
8
P80 to P87
PORT 9
PORT 11
PORT 12
2
78K0R
CPU
CORE
P110, P111
P120
4
P121 to P124
P130
P131
PORT 13
LOW-SPEED
INTERNAL
OSCILLATOR
WINDOW
WATCHDOG
TIMER
P91
PORT 14
6
P140 to P145
PORT 15
8
P150 to P157
2
PCLBUZ0/P140, PCLBUZ1/P141
FLASH
MEMORY
RTCDIV/RTCCL/P15
REALTIME COUNTER
BUZZER OUTPUT
RTC1HZ/P30
CLOCK OUTPUT
CONTROL
SERIAL ARRAY
UNIT0 (4 ch)
RxD0/P11
TxD0/P12
UART0
RxD1/P03
TxD1/P02
UART1
SCK00/P10
SI00/P11
SO00/P12
CSI00
SCK01/P43
SI01/P44
SO01/P45
CSI01
A/D CONVERTER
8
ANI0/P20 to
ANI7/P27
8
ANI8/P150 to
ANI15/P157
AVREF
AVSS
KEY RETURN
8
KR0/P70 to
KR7/P77
DIRECT MEMORY
ACCESS CONTROL
SCK10/P04
SI10/P03
SO10/P02
SCL10/P04
SDA10/P03
CSI10
SERIAL ARRAY
UNIT2 (2 ch) Note
IIC10
CSI40
SCK40/P50
SI40/RxD4/P51
SO40/TxD4/P52
SERIAL ARRAY
UNIT1 (4 ch)
CSI41
SCK41/P53
SI41/P54
SO41/P55
UART4
RxD4/P51
TxD4/P52
SCK20/P142
SI20/P143
SO20/P144
CSI20
SCL20/P142
SDA20/P143
IIC20
POWER ON CLEAR/
LOW VOLTAGE
INDICATOR
POC/LVI
CONTROL
EXLVI/P120
RESET CONTROL
MULTIPLIER&
DIVIDER
ON-CHIP DEBUG
RxD2/P143
TxD2/P144
TOOL0/P40
TOOL1/P41
UART2
UART3
RxD3/P14
TxD3/P13
LINSEL
SCL0/P60
SDA0/P61
VDD,
VSS, FLMD0
EVDD0, EVSS0,
EVDD1 EVSS1
BCD
ADJUSTMENT
SYSTEM
CONTROL
SERIAL
INTERFACE IICA
HIGH-SPEED
INTERNAL
OSCILLATOR
RxD3/P14 (LINSEL)
INTP0/P120
INTP1/P46,
INTP2/P47
2
INTP3/P30,
INTP4/P31
2
INTP5/P16
Note
RAM
INTP6/P140,
INTP7/P141
2
INTP8/P74 to
INTP11/P77
4
INTERRUPT
CONTROL
VOLTAGE
REGULATOR
RESET
X1/P121
X2/EXCLK/P122
XT1/P123
XT2/P124
REGC
Serial array unit 2 is only mounted in the μ PD78F1029 and 78F1030.
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78K0R/Kx3-L
CHAPTER 1 OUTLINE
1.7 Outline of Functions
1. 7. 1 78K0R/KC3-L, 78K0R/KD3-L, 78K0R/KE3-L
(1/2)
Item
40-pin
3/2
1
1.5
2
3/2
1.5
2
Note 1
48
64
32
3/2
1.5
2
Note 1
μ PD78F1009
2
32
μ PD78F1008
1.5
64
μ PD78F1007
1
48
μ PD78F1006
32
μ PD78F1005
16
μ PD78F1004
64
μ PD78F1003
48
μ PD78F1002
RAM (KB)
μ PD78F1001
μ PD78F1001
32
μ PD78F1003
μ PD78F1000
16
48
64
32
48
64
3/2
1.5
2
Note 1
Note 1
Memory space
1 MB
Main system High-speed system
clock
clock
X1 (crystal/ceramic) oscillation, external main system clock input (EXCLK)
2 to 20 MHz: VDD = 2.7 to 5.5 V, 2 to 5 MHz: VDD = 1.8 to 5.5 V
Internal high-speed
oscillation clock
78K0R/KE3-L
48-pin
μ PD78F1002
μ PD78F1003
μ PD78F1001
Flash memory
(KB)
44-pin
μ PD78F1002
μ PD78F1000
Internal
memory
78K0R/KD3-L
78K0R/KC3-L
3/2
Note 1
Internal oscillation
1 MHz (TYP.), 8 MHz (TYP.): VDD = 1.8 to 5.5 V
20 MHz internal high- Internal oscillation
speed oscillation
20 MHz (TYP.): VDD = 2.7 to 5.5 V
clock
Subsystem clock
−
XT1 (crystal) oscillation
32.768 kHz (TYP.): VDD = 1.8 to 5.5 V
Internal low-speed oscillation clock
(dedicated to WDT)
Internal oscillation
30 kHz (TYP.): VDD = 1.8 to 5.5 V
General-purpose register
8 bits × 32 registers (8 bits × 8 registers × 4 banks)
Minimum instruction execution time
0.05 μs (High-speed system clock: fMX = 20 MHz operation)
Instruction set
• 8-bit operation, 16-bit operation
• Multiplication (8 bits × 8 bits)
• Bit manipulation (Set, reset, test, and Boolean operation), etc.
−
I/O port
Timer
Total
33
37
41
45
55
CMOS I/O
31
33
34
38
48
CMOS input
2
4
4
4
4
CMOS output
−
−
1
1
1
N-ch open-drain I/O
(6 V tolerance)
−
−
2
2
2
16-bit timer
8 channels
Watchdog timer
1 channel
Real-time counter (RTC)
Timer output
RTC output
Notes 1.
2.
61 μs (Subsystem clock: fSUB = 32.768 kHz operation)
−
6
Note 2
)
(PWM outputs: 6
−
1 channel
8
Note 2
(PWM outputs: 7
)
2
• 1 Hz (subsystem clock: fSUB = 32.768 kHz)
• 512 Hz, 16.384 kHz, or 32.768 kHz (subsystem clock: fSUB = 32.768 kHz)
This is 2 KB when the self-programming function is used.
The number of outputs varies, depending on the setting.
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78K0R/Kx3-L
CHAPTER 1 OUTLINE
(2/2)
Item
78K0R/KD3-L
78K0R/KC3-L
40-pin
44-pin
μ PD78F1009
μ PD78F1008
•
1
μ PD78F1007
1
μ PD78F1006
μ PD78F1005
μ PD78F1004
μ PD78F1003
μ PD78F1002
μ PD78F1001
μ PD78F1003
μ PD78F1002
μ PD78F1001
μ PD78F1000
μ PD78F1003
μ PD78F1002
μ PD78F1001
μ PD78F1000
−
Clock output/buzzer output
78K0R/KE3-L
48-pin
2
2.44 kHz, 4.88 kHz, 9.76 kHz, 1.25 MHz, 2.5
MHz, 5 MHz, 10 MHz
(peripheral hardware clock: fMAIN = 20 MHz
operation)
•
256 Hz, 512 Hz, 1.024 kHz, 2.048 kHz, 4.096
kHz, 8.192 kHz, 16.384 kHz, 32.768 kHz
(Subsystem clock: fSUB = 32.768 kHz operation)
10-bit resolution A/D converter
10 channels
11 channels
11 channels
12 channels
(AVREF = 1.8 to 5.5 V)
Comparators
2 channels (reference voltage: 12 combinations)
Programmable gain amplifiers
1 channel (5 amplification factors)
• CSI: 2 channels/UART (LIN-bus supported): 1 channel
Serial interface
• CSI: 1 channel/UART: 1 channel/simplified I C: 1 channel
2
−
2
I C bus
Multiplier/divider
1 channel
1 channel
1 channel
25
25
25
• 16 bits × 16 bits = 32 bits (multiplication)
• 32 bits ÷ 32 bits = 32 bits (division)
DMA controller
2 channels
Vectored interrupt Internal
sources
External
22
24
8
9
Key interrupt
6 channels (KR0 to KR5)
Reset
• Reset by RESET pin
8 channels (KR0 to KR7)
• Internal reset by watchdog timer
• Internal reset by power-on-clear
• Internal reset by low-voltage detector
• Internal reset by illegal instruction execution
Note
• Internal reset by a reset processing check error
Power-on-clear circuit
• Power-on-reset:
1.61 ±0.09 V
• Power-down-reset: 1.59 ±0.09 V
Low-voltage detector
1.91 V to 4.22 V (16 stages)
On-chip debug function
Provided
Power supply voltage
VDD = 1.8 to 5.5 V
Operating ambient temperature
TA = −40 to +85 °C
Note
The illegal instruction is generated when instruction code FFH is executed.
Reset by the illegal instruction execution not issued by emulation with the in-circuit emulator or on-chip debug
emulator.
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78K0R/Kx3-L
CHAPTER 1 OUTLINE
1. 7. 2 78K0R/KF3-L, 78K0R/KG3-L
(1/2)
Item
96
RAM (KB)
4
6
8/7
10
12/11
6
Note 1
Note 2
128
192
256
8/7
10
12/11
Note 1
Memory space
1 MB
Main system High-speed system
clock
clock
X1 (crystal/ceramic) oscillation, external main system clock input (EXCLK)
2 to 20 MHz: VDD = 2.7 to 5.5 V, 2 to 5 MHz: VDD = 1.8 to 5.5 V
Internal high-speed
oscillation clock
Note 4
256
μ PD78F1030
192
Note 4
128
μ PD78F1029
μ PD78F1028
96
μ PD78F1014
μ PD78F1027
64
μ PD78F1013
μ PD78F1012
Flash memory
(KB)
78K0R/KG3-L
μ PD78F1011
μ PD78F1010
Internal
memory
78K0R/KF3-L
Note 2
Internal oscillation
1 MHz (TYP.), 8 MHz (TYP.): VDD = 1.8 to 5.5 V
20 MHz internal high- Internal oscillation
speed oscillation
20 MHz (TYP.): VDD = 2.7 to 5.5 V
clock
Subsystem clock
XT1 (crystal) oscillation
32.768 kHz (TYP.): VDD = 1.8 to 5.5 V
Internal low-speed oscillation clock
(dedicated to WDT)
Internal oscillation
30 kHz (TYP.): VDD = 1.8 to 5.5 V
General-purpose register
8 bits × 32 registers (8 bits × 8 registers × 4 banks)
Minimum instruction execution time
0.05 μs (High-speed system clock: fMX = 20 MHz operation)
61 μs (Subsystem clock: fSUB = 32.768 kHz operation)
• 8-bit operation, 16-bit operation
• Multiplication (8 bits × 8 bits)
• Bit manipulation (Set, reset, test, and Boolean operation), etc.
Instruction set
I/O port
Timer
Notes 1.
2.
Total
71
89
CMOS I/O
62
80
CMOS input
4
4
CMOS output
1
1
N-ch open-drain I/O
(6 V tolerance)
4
4
16-bit timer
12 channels (unit 0: 8 channels, unit 1: 4 channels)
Watchdog timer
1 channel
Real-time counter
(RTC)
1 channel
Note 3
Timer output
12 channels (PWM outputs unit 0: 7, unit 1: 3
)
RTC output
2
• 1 Hz (subsystem clock: fSUB = 32.768 kHz)
• 512 Hz, 16.384 kHz, or 32.768 kHz (subsystem clock: fSUB = 32.768 kHz)
This is 7 KB when the self-programming function is used.
This is 11 KB when the self-programming function is used.
3.
The number of outputs varies, depending on the setting.
4.
The μPD78F1029 and μPD78F1030 don’t have the FBGA package.
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78K0R/Kx3-L
CHAPTER 1 OUTLINE
(2/2)
Item
78K0R/KF3-L
78K0R/KG3-L
μ PD78F1030
μ PD78F1029
μ PD78F1014
μ PD78F1013
μ PD78F1028
μ PD78F1027
μ PD78F1012
μ PD78F1011
μ PD78F1010
Note 1
Note 1
Clock output/buzzer output
2
• 2.44 kHz, 4.88 kHz, 9.76 kHz, 1.25 MHz, 2.5 MHz, 5 MHz, 10 MHz
(peripheral hardware clock: fMAIN = 20 MHz operation)
• 256 Hz, 512 Hz, 1.024 kHz, 2.048 kHz, 4.096 kHz, 8.192 kHz, 16.384 kHz, 32.768 kHz
(Subsystem clock: fSUB = 32.768 kHz operation)
10-bit resolution A/D converter
12 channels
16 channels
(AVREF = 1.8 to 5.5 V)
Comparators
−
Programmable gain amplifiers
−
• CSI: 2 channels/UART: 1 channel
Serial interface
• CSI: 1 channel/UART: 1 channel/simplified I C: 1 channel
2
• CSI: 1 channel/UART: 1 channel/simplified I C: 1 channel
2
• UART supporting LIN-bus: 1 channel
• CSI: 2 channels/UART: 1 channel (μ PD78F1027, 78F1028, 78F1029, 78F1030)
2
I C bus
1 channel
Multiplier/divider
• 16 bits × 16 bits = 32 bits (multiplication)
DMA controller
2 channels
• 32 bits ÷ 32 bits = 32 bits (division)
Vectored interrupt Internal
sources
External
33
35
33
35
13
Key interrupt
8 channels (KR0 to KR7)
Reset
• Reset by RESET pin
• Internal reset by watchdog timer
• Internal reset by power-on-clear
• Internal reset by low-voltage detector
• Internal reset by illegal instruction execution
Note 2
• Internal reset by a reset processing check error
Power-on-clear circuit
• Power-on-reset:
1.61 ±0.09 V
• Power-down-reset: 1.59 ±0.09 V
Low-voltage detector
1.91 V to 4.22 V (16 stages)
On-chip debug function
Provided
Power supply voltage
VDD = 1.8 to 5.5 V
Operating ambient temperature
TA = −40 to +85 °C
Notes 1. The μPD78F1029 and μPD78F1030 don’t have the FBGA package.
2. The illegal instruction is generated when instruction code FFH is executed.
Reset by the illegal instruction execution not issued by emulation with the in-circuit emulator or on-chip
debug emulator.
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78K0R/Kx3-L
CHAPTER 2 PIN FUNCTIONS (78K0R/KC3-L, 78K0R/KD3-L, 78K0R/KE3-L)
CHAPTER 2 PIN FUNCTIONS (78K0R/KC3-L, 78K0R/KD3-L, 78K0R/KE3-L)
Caution For the functions of the pins in the 78K0R/KF3-L and 78K0R/KG3-L, see CHAPTER 3 PIN FUNCTIONS
(78K0R/KF3-L and 78K0R/KG3-L).
2.1 Pin Function List
Pin I/O buffer power supplies depend on the product. The relationship between these power supplies and the pins is
shown below.
Table 2-1. Pin I/O Buffer Power Supplies (AVREF, VDD)
• 78K0R/KC3-L: 40-pin plastic WQFN (6x6)
Note 1
44-pin plastic LQFP (10x10)
48-pin plastic TQFP (fine pitch) (7x7)
48-pin plastic WQFN (7x7) Note 1
• 78K0R/KD3-L: 52-pin plastic LQFP (10x10)
Power Supply
Corresponding Pins
Note 2
, P80 to P83
Note 3
AVREF
P20 to P27, P150 to P152
EVDD
• Port pins other than P20 to P27, P150 to P152
Note 2
, P80 to P83
Note 3
• Pins other than port pins
Notes 1. Under development
2. 40-pin and 44-pin products of the 78K0R/KC3-L do not have a P152 pin.
3. 40-pin product of the 78K0R/KC3-L does not have a P82 pin.
Table 2-2. Pin I/O Buffer Power Supplies (AVREF, EVDD, VDD)
• 78K0R/KE3-L: 64-pin plastic FBGA (5x5)
64-pin plastic FBGA (4x4)
64-pin plastic TQFP (fine pitch) (7x7)
64-pin plastic LQFP (fine pitch) (10x10)
64-pin plastic LQFP (12x12)
Power Supply
Corresponding Pins
AVREF
P20 to P27, P150 to P153, P80 to P83
EVDD
• Port pins other than P20 to P27, P150 to P153, P80 to P83, and P121 to P124
• RESET pin and FLMD0 pin
VDD
• P121 to P124
• Pins other than port pins (other than RESET pin and FLMD0 pin)
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78K0R/Kx3-L
CHAPTER 2 PIN FUNCTIONS (78K0R/KC3-L, 78K0R/KD3-L, 78K0R/KE3-L)
2.1.1 78K0R/KC3-L (40-pin products)
(1) Port functions (1/2): 78K0R/KC3-L (40-pin)
Function Name
P10
I/O
I/O
Function
Port 1.
After Reset
Input port
4-bit I/O port.
P11
TI04/TO04
Use of an on-chip pull-up resistor can be specified by a software
P13
TI05/TO05
setting.
P20 to P27
I/O
TI02/TO02
TI03/TO03
Input/output can be specified in 1-bit units.
P12
Alternate Function
Port 2.
Digital input
8-bit I/O port.
port
ANI0 to ANI7
Input/output can be specified in 1-bit units.
P30
I/O
Port 3.
Input port
SO10/TxD1
3-bit I/O port.
Input of P31 and P32 can be set to TTL buffer.
P31
Output of P30 to P32 can be set to N-ch open-drain output (VDD
SI10/RxD1/SDA10/
tolerance).
INTP1
Input/output can be specified in 1-bit units.
P32
SCK10/SCL10/
Use of an on-chip pull-up resistor can be specified by a software
INTP2
setting.
P40
Note
I/O
Port 4.
Input port
TOOL0
2-bit I/O port.
Input/output can be specified in 1-bit units.
P41
TOOL1
Use of an on-chip pull-up resistor can be specified by a software
setting.
P50
I/O
Port 5.
Input port
2-bit I/O port.
P51
TI06/TO06
TI07/TO07
Input/output can be specified in 1-bit units.
Use of an on-chip pull-up resistor can be specified by a software
setting.
P70
P71
I/O
Port 7.
6-bit I/O port.
Input of P71, P72, P74, and P75 can be set to TTL buffer.
Input port
KR0/SO01/INTP4
KR1/SI01/INTP5
P72
Output of P70, P72, P73, and P75 can be set to N-ch open-drain
KR2/SCK01/INTP6
P73
output (VDD tolerance).
KR3/SO00/TxD0
P74
P75
Note
Input/output can be specified in 1-bit units.
Use of an on-chip pull-up resistor can be specified by a software
setting.
KR4/SI00/RxD0
KR5/SCK00
If on-chip debugging is enabled by using an option byte, be sure to pull up the P40/TOOL0 pin externally.
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CHAPTER 2 PIN FUNCTIONS (78K0R/KC3-L, 78K0R/KD3-L, 78K0R/KE3-L)
(1) Port functions (2/2): 78K0R/KC3-L (40-pin)
Function Name
P80
I/O
I/O
P81
P121
Port 8.
After Reset
Analog input CMP0P/INTP3/
PGAI
Inputs/output can be specified in 1-bit units.
CMP0M
CMP1M
programmable gain amplifier inputs.
I/O
Port 12.
Input
1-bit I/O port and 2-bit input port.
Input port
INTP0/EXLVI
X1
For only P120, input/output can be specified in 1-bit units.
P122
Alternate Function
3-bit I/O port.
Inputs of P80, P81, and P83 can be set as comparator inputs or
P83
P120
Function
X2/EXCLK
For only P120, use of an on-chip pull-up resistor can be specified
by a software setting.
P150, P151
I/O
Port 15.
Digital input
2-bit I/O port.
port
ANI8, ANI9
Input/output can be specified in 1-bit units.
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CHAPTER 2 PIN FUNCTIONS (78K0R/KC3-L, 78K0R/KD3-L, 78K0R/KE3-L)
(2) Non-port functions (1/2): 78K0R/KC3-L (40-pin)
Function Name
ANI0 to ANI7
I/O
Input
Function
A/D converter analog input
After Reset
Digital input
Alternate Function
P20 to P27
port
ANI8, ANI9
Input
A/D converter analog input
Digital input
P150, P151
port
CMP0M
Input
Input voltage on the (−) side of comparator 0
CMP0P
Input
Input voltage on the (+) side of comparator 0
P80/INTP3/PGAI
CMP1M
Input
Input voltage on the (−) side of comparator 1
P83
EXLVI
Input
Potential input for external low-voltage detection
Input port
P120/INTP0
INTP0
Input
External interrupt request input for which the valid edge (rising
Input port
P120/EXLVI
INTP1
Analog input P81
edge, falling edge, or both rising and falling edges) can be
P31/SI10/RxD1/
specified
SDA10
INTP2
P32/SCK10/SCL10
INTP3
Analog input P80/CMP0P/PGAI
INTP4
Input port
P70/KR0/SO01
INTP5
P71/KR1/SI01
INTP6
P72/KR2/SCK01
KR0
Input
Key interrupt input
Input port
P70/SO01/INTP4
KR1
P71/SI01/INTP5
KR2
P72/SCK01/INTP6
KR3
P73/SO00/TxD0
KR4
P74/SI00/RxD0
KR5
P75/SCK00
PGAI
Input
−
REGC
Programmable gain amplifier input
Connecting regulator output (2.4 V) stabilization capacitance for
Analog input P80/CMP0P/INTP3
−
−
−
−
internal operation.
Connect to VSS via a capacitor (0.47 to 1 μF).
RESET
Input
RxD0
Input
RxD1
SCK00
System reset input
Serial data input to UART0
Input port
Serial data input to UART1
I/O
Clock input/output for CSI00
P74/KR4/SI00
P31/SI10/SDA10/
INTP1
Input port
P75/KR5
SCK01
Clock input/output for CSI01
P72/KR2/INTP6
SCK10
Clock input/output for CSI10
P32/SCL10/INTP2
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CHAPTER 2 PIN FUNCTIONS (78K0R/KC3-L, 78K0R/KD3-L, 78K0R/KE3-L)
(2) Non-port functions (2/2): 78K0R/KC3-L (40-pin)
Function Name
SCL10
I/O
Function
2
I/O
Clock input/output for simplified I C
2
After Reset
Alternate Function
Input port
P32/SCK10/INTP2
SDA10
I/O
Serial data I/O for simplified I C
Input port
P31/SI10/RxD1/
INTP1
SI00
Input
Serial data input to CSI00
Input port
P74/KR4/RxD0
SI01
Serial data input to CSI01
P71/KR1/INTP5
SI10
Serial data input to CSI10
P31/RxD1/SDA10/
INTP1
SO00
Output
Serial data output from CSI00
Input port
P73/KR3/TxD0
SO01
Serial data output from CSI01
P70/KR0/INTP4
SO10
Serial data output from CSI10
P30/TxD1
TI02
Input
External count clock input to 16-bit timer 02
Input port
P10/TO02
TI03
External count clock input to 16-bit timer 03
P11/TO03
TI04
External count clock input to 16-bit timer 04
P12/TO04
TI05
External count clock input to 16-bit timer 05
P13/TO05
TI06
External count clock input to 16-bit timer 06
P50/TO06
TI07
External count clock input to 16-bit timer 07
P51/TO07
TO02
Output
16-bit timer 02 output
Input port
P10/TI02
TO03
16-bit timer 03 output
P11/TI03
TO04
16-bit timer 04 output
P12/TI04
TO05
16-bit timer 05 output
P13/TI05
TO06
16-bit timer 06 output
P50/TI06
TO07
TxD0
16-bit timer 07 output
Output
TxD1
P51/TI07
Input port
Serial data output from UART1
X1
−
X2
−
EXCLK
Serial data output from UART0
Input
−
VDD
Resonator connection for main system clock
External clock input for main system clock
Positive power supply (Port pins other than P20 to P27, P80, P81,
P73/KR3/SO00
P30/SO10
Input port
P121
Input port
P122/EXCLK
Input port
P122/X2
−
−
−
−
−
−
−
−
−
−
P83, P150, P151, and other than ports)
−
AVREF
• A/D converter and comparator reference voltage input
• Positive power supply for P20 to P27, P80, P81, P83, P150,
P151, A/D converter, programmable gain amplifier, and
comparator
−
VSS
Ground potential (Port pins other than P20 to P27, P80, P81, P83,
P150, P151, and other than ports)
−
AVSS
Ground potential for A/D converter, programmable gain amplifier,
comparator, P20 to P27, P80, P81, P83, P150, P151
−
FLMD0
Flash memory programming mode setting
TOOL0
I/O
Data I/O for flash memory programmer/debugger
Input port
P40
TOOL1
Output
Clock output for debugger
Input port
P41
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CHAPTER 2 PIN FUNCTIONS (78K0R/KC3-L, 78K0R/KD3-L, 78K0R/KE3-L)
2.1.2 78K0R/KC3-L (44-pin and 48-pin products)
(1) Port functions (1/2): 78K0R/KC3-L (44-pin and 48-pin products)
Function Name
P10
I/O
I/O
Function
Port 1.
After Reset
Input port
4-bit I/O port.
P11
TI02/TO02
TI03/TO03
Input/output can be specified in 1-bit units.
P12
Alternate Function
TI04/TO04/
Use of an on-chip pull-up resistor can be specified by a software
RTCDIV/RTCCL
setting.
P13
TI05/TO05
P20 to P27
I/O
Port 2.
Digital input
8-bit I/O port.
port
ANI0 to ANI7
Input/output can be specified in 1-bit units.
P30
I/O
Port 3.
Input port
SO10/TxD1
3-bit I/O port.
Input of P31 and P32 can be set to TTL buffer.
P31
Output of P30 to P32 can be set to N-ch open-drain output (VDD
SI10/RxD1/SDA10/
tolerance).
INTP1
Input/output can be specified in 1-bit units.
P32
SCK10/SCL10/
Use of an on-chip pull-up resistor can be specified by a software
INTP2
setting.
P40
Note 1
I/O
Port 4.
Input port
TOOL0
2-bit I/O port.
Input/output can be specified in 1-bit units.
P41
TOOL1
Use of an on-chip pull-up resistor can be specified by a software
setting.
P50
I/O
Port 5.
Input port
3-bit I/O port.
P51
TI07/TO07
Input/output can be specified in 1-bit units.
P52
RTC1HZ/SLTI/
Use of an on-chip pull-up resistor can be specified by a software
SLTO
setting.
P60
Note 2
P61
Note 2
I/O
Port 6.
TI06/TO06
Input port
SCL0
Note 2
2-bit I/O port.
Output of P60 and P61 is N-ch open-drain output (6 V tolerance).
SDA0
Note 2
Input/output can be specified in 1-bit units.
P70
P71
I/O
Port 7.
6-bit I/O port.
Input of P71, P72, P74, and P75 can be set to TTL buffer.
Input port
KR0/SO01/INTP4
KR1/SI01/INTP5
P72
Output of P70, P72, P73, and P75 can be set to N-ch open-drain
KR2/SCK01/INTP6
P73
output (VDD tolerance).
KR3/SO00/TxD0
P74
P75
Input/output can be specified in 1-bit units.
Use of an on-chip pull-up resistor can be specified by a software
setting.
KR4/SI00/RxD0
KR5/SCK00
Notes 1. If on-chip debugging is enabled by using an option byte, be sure to pull up the P40/TOOL0 pin externally.
2. 48-pin products only.
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CHAPTER 2 PIN FUNCTIONS (78K0R/KC3-L, 78K0R/KD3-L, 78K0R/KE3-L)
(1) Port functions (2/2): 78K0R/KC3-L (44-pin and 48-pin products)
Function Name
I/O
I/O
P80
P81
Function
Port 8.
After Reset
Analog input CMP0P/INTP3/
4-bit I/O port.
PGAI
Inputs/output can be specified in 1-bit units.
CMP0M
Inputs of P80 to P83 can be set as comparator inputs or
P82
CMP1P/INTP7
programmable gain amplifier inputs.
P83
CMP1M
P120
P121
I/O
Port 12.
Input
1-bit I/O port and 4-bit input port.
Input port
X2/EXCLK
For only P120, use of an on-chip pull-up resistor can be specified
P123
INTP0/EXLVI
X1
For only P120, input/output can be specified in 1-bit units.
P122
XT1
by a software setting.
P124
P140
Alternate Function
XT2
Note
Output
Port 14.
Note
Output port
PCLBUZ0
Port 15.
Digital input
ANI8, ANI9,
3-bit I/O port.
port
ANI10
1-bit output port.
P150, P151,
P152
Note
I/O
Note
Input/output can be specified in 1-bit units.
Note 48-pin products only.
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CHAPTER 2 PIN FUNCTIONS (78K0R/KC3-L, 78K0R/KD3-L, 78K0R/KE3-L)
(2) Non-port functions (1/3): 78K0R/KC3-L (44-pin and 48-pin products)
Function Name
ANI0 to ANI7
ANI8, ANI9,
ANI10
I/O
Input
Function
A/D converter analog input
Input
After Reset
Alternate Function
Digital input
P20 to P27
port
P150, P151, P152
Note
Note
CMP0M
Input
Input voltage on the (−) side of comparator 0
CMP0P
Input
Input voltage on the (+) side of comparator 0
P80/INTP3/PGAI
CMP1M
Input
Input voltage on the (−) side of comparator 1
P83
CMP1P
Input
Input voltage on the (+) side of comparator 1
P82/INTP7
EXLVI
Input
Potential input for external low-voltage detection
Input port
P120/INTP0
INTP0
Input
External interrupt request input for which the valid edge (rising
Input port
P120/EXLVI
INTP1
Analog input P81
edge, falling edge, or both rising and falling edges) can be
P31/SI10/RxD1/
specified
SDA10
INTP2
P32/SCK10/SCL10
INTP3
Analog input P80/CMP0P/PGAI
INTP4
Input port
P70/KR0/SO01
INTP5
P71/KR1/SI01
INTP6
P72/KR2/SCK01
Analog input P82/CMP1P
INTP7
Input
KR0
Key interrupt input
Input port
P70/SO01/INTP4
KR1
P71/SI01/INTP5
KR2
P72/SCK01/INTP6
KR3
P73/SO00/TxD0
KR4
P74/SI00/RxD0
KR5
PCLBUZ0
PGAI
P75/SCK00
Note
Clock output/buzzer output
Output port
Input
Programmable gain amplifier input
Analog input P80/CMP0P/INTP3
−
REGC
Connecting regulator output (2.4 V) stabilization capacitance for
P140
Note
Output
−
−
internal operation.
Connect to VSS via a capacitor (0.47 to 1 μF).
RTCDIV
Output
Real-time counter clock (32 kHz division) output
Input port
P12/TI04/TO04/
RTCCL
RTCCL
Output
Real-time counter clock (32 kHz original oscillation) output
Input port
P12/TI04/TO04/
RTCDIV
RTC1HZ
Output
Real-time counter correction clock (1 Hz) output
RESET
Input
System reset input
RxD0
Input
Serial data input to UART0
RxD1
SCK00
Input port
−
Input port
Serial data input to UART1
I/O
Clock input/output for CSI00
P52/SLTI/SLTO
−
P74/KR4/SI00
P31/SI10/SDA10/
INTP1
Input port
P75/KR5
SCK01
Clock input/output for CSI01
P72/KR2/INTP6
SCK10
Clock input/output for CSI10
P32/SCL10/INTP2
Note 48-pin products only.
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CHAPTER 2 PIN FUNCTIONS (78K0R/KC3-L, 78K0R/KD3-L, 78K0R/KE3-L)
(2) Non-port functions (2/3): 78K0R/KC3-L (44-pin and 48-pin products)
Function Name
SCL0
Note
SCL10
SDA0
Note
I/O
Function
After Reset
2
I/O
Clock input/output for I C
I/O
Clock input/output for simplified I C
2
2
Alternate Function
Note
Input port
P60
Input port
P32/SCK10/INTP2
Input port
P61
Note
I/O
Serial data I/O for I C
SDA10
I/O
Serial data I/O for simplified I C
Input port
P31/SI10/RxD1/
INTP1
SI00
Input
Serial data input to CSI00
Input port
P74/KR4/RxD0
2
SI01
Serial data input to CSI01
P71/KR1/INTP5
SI10
Serial data input to CSI10
P31/RxD1/SDA10/
INTP1
SLTI
Input
16-bit timer 00, 01 input
Input port
P52/RTC1HZ/SLTO
SLTO
Output
16-bit timer 00, 01 output
Input port
P52/RTC1HZ/SLTI
SO00
Output
Serial data output from CSI00
Input port
P73/KR3/TxD0
SO01
Serial data output from CSI01
P70/KR0/INTP4
SO10
Serial data output from CSI10
P30/TxD1
TI02
Input
External count clock input to 16-bit timer 02
Input port
P10/TO02
TI03
External count clock input to 16-bit timer 03
P11/TO03
TI04
External count clock input to 16-bit timer 04
P12/TO04/
RTCDIV/RTCCL
TI05
External count clock input to 16-bit timer 05
P13/TO05
TI06
External count clock input to 16-bit timer 06
P50/TO06
TI07
External count clock input to 16-bit timer 07
P51/TO07
TO02
Output
16-bit timer 02 output
Input port
P10/TI02
TO03
16-bit timer 03 output
P11/TI03
TO04
16-bit timer 04 output
P12/TI04/
RTCDIV/RTCCL
TO05
16-bit timer 05 output
P13/TI05
TO06
16-bit timer 06 output
P50/TI06
TO07
16-bit timer 07 output
P51/TI07
TxD0
Output
TxD1
X1
−
X2
−
XT1
−
XT2
EXCLK
VDD
Input port
P121
Input port
P122/EXCLK
Resonator connection for subsystem clock
Input port
P123
Input port
P124
External clock input for main system clock
Input port
P122/X2
−
Input
−
−
P73/KR3/SO00
P30/SO10
Resonator connection for main system clock
Positive power supply (Port pins other than P20 to P27, P80 to
P83, P150, P151, P152
AVREF
Input port
Serial data output from UART0
Serial data output from UART1
−
−
−
−
−
−
Note
, and other than ports)
• A/D converter and comparator reference voltage input
• Positive power supply for P20 to P27, P150, P151, P152
Note
,
P80 to P83, A/D converter, programmable gain amplifier, and
comparator
VSS
−
Ground potential (Port pins other than P20 to P27, P80 to P83,
P150, P151, P152
Note
, and other than ports)
Note 48-pin products only.
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CHAPTER 2 PIN FUNCTIONS (78K0R/KC3-L, 78K0R/KD3-L, 78K0R/KE3-L)
(2) Non-port functions (3/3): 78K0R/KC3-L (44-pin and 48-pin products)
Function Name
I/O
Function
−
Ground potential for A/D converter, programmable gain amplifier,
AVSS
comparator, P20 to P27, P150, P151, P152
−
FLMD0
Note
After Reset
Alternate Function
−
−
−
−
and P80 to P83
Flash memory programming mode setting
TOOL0
I/O
Data I/O for flash memory programmer/debugger
Input port
P40
TOOL1
Output
Clock output for debugger
Input port
P41
Note 48-pin products only.
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2.1.3 78K0R/KD3-L
(1) Port functions (1/2): 78K0R/KD3-L
Function Name
I/O
I/O
P00
Function
Port 0.
After Reset
Input port
2-bit I/O port.
P01
Alternate Function
TI00
TO00
Input/output can be specified in 1-bit units.
Use of an on-chip pull-up resistor can be specified by a software
setting.
I/O
P10
Port 1.
Input port
4-bit I/O port.
P11
TI03/TO03
Input/output can be specified in 1-bit units.
P12
TI02/TO02
TI04/TO04/
Use of an on-chip pull-up resistor can be specified by a software
RTCDIV/RTCCL
setting.
P13
TI05/TO05
P20 to P27
I/O
Port 2.
Digital input
8-bit I/O port.
port
ANI0 to ANI7
Input/output can be specified in 1-bit units.
P30
I/O
Port 3.
Input port
SO10/TxD1
3-bit I/O port.
Input of P31 and P32 can be set to TTL buffer.
P31
Output of P30 to P32 can be set to N-ch open-drain output (VDD
SI10/RxD1/SDA10/
tolerance).
INTP1
Input/output can be specified in 1-bit units.
P32
SCK10/SCL10/
Use of an on-chip pull-up resistor can be specified by a software
INTP2
setting.
P40
Note
I/O
Port 4.
Input port
TOOL0
2-bit I/O port.
Input/output can be specified in 1-bit units.
P41
TOOL1
Use of an on-chip pull-up resistor can be specified by a software
setting.
P50
I/O
Port 5.
Input port
3-bit I/O port.
P51
TI07/TO07
Input/output can be specified in 1-bit units.
P52
RTC1HZ/SLTI/
Use of an on-chip pull-up resistor can be specified by a software
SLTO
setting.
P60
P61
I/O
Port 6.
2-bit I/O port.
TI06/TO06
Input port
SCL0
SDA0
Output of P60 and P61 is N-ch open-drain output (6 V tolerance).
Input/output can be specified in 1-bit units.
Note If on-chip debugging is enabled by using an option byte, be sure to pull up the P40/TOOL0 pin externally.
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(1) Port functions (2/2): 78K0R/KD3-L
Function Name
P70
I/O
I/O
Function
Port 7.
After Reset
Input port
8-bit I/O port.
P71
KR0/SO01/INTP4
KR1/SI01/INTP5
Input of P71, P72, P74, and P75 can be set to TTL buffer.
P72
Alternate Function
KR2/SCK01/INTP6
Output of P70, P72, P73, and P75 can be set to N-ch open-drain
P73
output (VDD tolerance).
KR3/SO00/TxD0
P74
Input/output can be specified in 1-bit units.
KR4/SI00/RxD0
Use of an on-chip pull-up resistor can be specified by a software
P75
KR5/SCK00
setting.
P76
KR6
P77
P80
KR7
I/O
P81
Port 8.
Analog input CMP0P/INTP3/
4-bit I/O port.
PGAI
Inputs/output can be specified in 1-bit units.
CMP0M
Inputs of P80 to P83 can be set as comparator inputs or
P82
CMP1P/INTP7
programmable gain amplifier inputs.
P83
P120
P121
CMP1M
I/O
Port 12.
Input
1-bit I/O port and 4-bit input port.
Input port
X1
For only P120, input/output can be specified in 1-bit units.
P122
X2/EXCLK
For only P120, use of an on-chip pull-up resistor can be specified
P123
XT1
by a software setting.
P124
P140
INTP0/EXLVI
XT2
Output
Port 14.
Output port
PCLBUZ0
Port 15.
Digital input
ANI8 to ANI10
3-bit I/O port.
port
1-bit output port.
P150 to P152
I/O
Input/output can be specified in 1-bit units.
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(2) Non-port functions (1/3): 78K0R/KD3-L
Function Name
ANI0 to ANI7
I/O
Input
Function
A/D converter analog input
After Reset
Alternate Function
Digital input
P20 to P27
port
P150 to P152
ANI8 to ANI10
Input
CMP0M
Input
Input voltage on the (−) side of comparator 0
CMP0P
Input
Input voltage on the (+) side of comparator 0
P80/INTP3/PGAI
CMP1M
Input
Input voltage on the (−) side of comparator 1
P83
CMP1P
Input
Input voltage on the (+) side of comparator 1
P82/INTP7
EXLVI
Input
Potential input for external low-voltage detection
Input port
P120/INTP0
INTP0
Input
External interrupt request input for which the valid edge (rising
Input port
P120/EXLVI
INTP1
Analog input P81
edge, falling edge, or both rising and falling edges) can be
P31/SI10/RxD1/
specified
SDA10
INTP2
P32/SCK10/SCL10
INTP3
Analog input P80/CMP0P/PGAI
INTP4
Input port
P70/KR0/SO01
INTP5
P71/KR1/SI01
INTP6
P72/KR2/SCK01
Analog input P82/CMP1P
INTP7
KR0
Input
Key interrupt input
Input port
P70/SO01/INTP4
KR1
P71/SI01/INTP5
KR2
P72/SCK01/INTP6
KR3
P73/SO00/TxD0
KR4
P74/SI00/RxD0
KR5
P75/SCK00
KR6
P76
KR7
P77
PCLBUZ0
Output
Clock output/buzzer output
Output port
PGAI
Input
Programmable gain amplifier input
Analog input P80/CMP0P/INTP3
REGC
−
Connecting regulator output (2.4 V) stabilization capacitance for
P140
−
−
internal operation.
Connect to VSS via a capacitor (0.47 to 1 μF).
RTCDIV
Output
Real-time counter clock (32 kHz division) output
Input port
P12/TI04/TO04/
RTCCL
RTCCL
Output
Real-time counter clock (32 kHz original oscillation) output
Input port
P12/TI04/TO04/
RTCDIV
RTC1HZ
Output
Real-time counter correction clock (1 Hz) output
RESET
Input
System reset input
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Input port
−
P52/SLTI/SLTO
−
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CHAPTER 2 PIN FUNCTIONS (78K0R/KC3-L, 78K0R/KD3-L, 78K0R/KE3-L)
(2) Non-port functions (2/3): 78K0R/KD3-L
Function Name
RxD0
I/O
Input
RxD1
SCK00
Function
After Reset
Input port
Serial data input to UART0
Serial data input to UART1
P74/KR4/SI00
P31/SI10/SDA10/
INTP1
Clock input/output for CSI00
I/O
Alternate Function
Input port
P75/KR5
SCK01
Clock input/output for CSI01
P72/KR2/INTP6
SCK10
Clock input/output for CSI10
P32/SCL10/INTP2
SCL0
SCL10
SDA0
2
I/O
Clock input/output for I C
2
I/O
Clock input/output for simplified I C
2
I/O
Serial data I/O for I C
2
Input port
P60
Input port
P32/SCK10/INTP2
Input port
P61
SDA10
I/O
Serial data I/O for simplified I C
Input port
P31/SI10/RxD1/
INTP1
SI00
Input
Serial data input to CSI00
Input port
P74/KR4/RxD0
SI01
Serial data input to CSI01
P71/KR1/INTP5
SI10
Serial data input to CSI10
P31/RxD1/SDA10/
INTP1
SLTI
Input
16-bit timer 00, 01 input
Input port
P52/RTC1HZ/SLTO
SLTO
Output
16-bit timer 00, 01 output
Input port
P52/RTC1HZ/SLTI
SO00
Output
Serial data output from CSI00
Input port
P73/KR3/TxD0
SO01
Serial data output from CSI01
P70/KR0/INTP4
SO10
Serial data output from CSI10
P30/TxD1
TI00
Input
External count clock input to 16-bit timer 00
Input port
P00
TI02
External count clock input to 16-bit timer 02
P10/TO02
TI03
External count clock input to 16-bit timer 03
P11/TO03
TI04
External count clock input to 16-bit timer 04
P12/TO04/
RTCDIV/RTCCL
TI05
External count clock input to 16-bit timer 05
P13/TO05
TI06
External count clock input to 16-bit timer 06
P50/TO06
TI07
External count clock input to 16-bit timer 07
P51/TO07
TO00
Output
16-bit timer 00 output
Input port
P01
TO02
16-bit timer 02 output
P10/TI02
TO03
16-bit timer 03 output
P11/TI03
TO04
16-bit timer 04 output
P12/TI04/
RTCDIV/RTCCL
TO05
16-bit timer 05 output
P13/TI05
TO06
16-bit timer 06 output
P50/TI06
TO07
16-bit timer 07 output
P51/TI07
TxD0
Output
TxD1
Input port
Serial data output from UART1
X1
−
X2
−
XT1
−
XT2
−
EXCLK
Serial data output from UART0
Input
Resonator connection for main system clock
Resonator connection for subsystem clock
External clock input for main system clock
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P73/KR3/SO00
P30/SO10
Input port
P121
Input port
P122/EXCLK
Input port
P123
Input port
P124
Input port
P122/X2
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CHAPTER 2 PIN FUNCTIONS (78K0R/KC3-L, 78K0R/KD3-L, 78K0R/KE3-L)
(2) Non-port functions (3/3): 78K0R/KD3-L
Function Name
I/O
−
VDD
Function
Positive power supply (Port pins other than P20 to P27, P80 to
After Reset
Alternate Function
−
−
−
−
−
−
−
−
−
−
P83, P150 to P152, and other than ports)
−
AVREF
• A/D converter and comparator reference voltage input
• Positive power supply for P20 to P27, P150 to P152, P80 to
P83, A/D converter, programmable gain amplifier, and
comparator
−
VSS
Ground potential (Port pins other than P20 to P27, P80 to P83,
P150 to P152, and other than ports)
−
AVSS
Ground potential for A/D converter, programmable gain amplifier,
comparator, P20 to P27, P150 to P152 and P80 to P83
−
FLMD0
Flash memory programming mode setting
TOOL0
I/O
Data I/O for flash memory programmer/debugger
Input port
P40
TOOL1
Output
Clock output for debugger
Input port
P41
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2.1.4 78K0R/KE3-L
(1) Port functions (1/2): 78K0R/KE3-L
Function Name
I/O
I/O
P00
Function
Port 0.
After Reset
Input port
2-bit I/O port.
P01
Alternate Function
TI00
TO00
Input/output can be specified in 1-bit units.
Use of an on-chip pull-up resistor can be specified by a software
setting.
I/O
P10
Port 1.
Input port
8-bit I/O port.
P11
TI03/TO03
Input/output can be specified in 1-bit units.
P12
TI02/TO02
TI04/TO04/
Use of an on-chip pull-up resistor can be specified by a software
RTCDIV/RTCCL
setting.
P13
TI05/TO05
P14
TI06/TO06
P15
TI07/TO07
P16
−
P17
−
P20 to P27
I/O
Port 2.
Digital input
8-bit I/O port.
port
ANI0 to ANI7
Input/output can be specified in 1-bit units.
I/O
P30
P31
Port 3.
Input port
SI10/RxD1/SDA10/
Input of P31 and P32 can be set to TTL buffer.
INTP1
Output of P30 to P32 can be set to N-ch open-drain output (VDD
P32
SCK10/SCL10/
tolerance).
INTP2
Input/output can be specified in 1-bit units.
P33
SO10/TxD1
4-bit I/O port.
−
Use of an on-chip pull-up resistor can be specified by a software
setting.
P40
Note
I/O
Input port
4-bit I/O port.
P41
TOOL0
TOOL1
Input/output can be specified in 1-bit units.
P42
P43
P50
Port 4.
I/O
Use of an on-chip pull-up resistor can be specified by a software
−
setting.
−
Port 5.
−
Input port
4-bit I/O port.
P51
−
Input/output can be specified in 1-bit units.
P52
RTC1HZ/SLTI/
Use of an on-chip pull-up resistor can be specified by a software
SLTO
setting.
−
P53
P60
P61
I/O
Port 6.
2-bit I/O port.
Input port
SCL0
SDA0
Output of P60 and P61 is N-ch open-drain output (6 V tolerance).
Input/output can be specified in 1-bit units.
Note If on-chip debugging is enabled by using an option byte, be sure to pull up the P40/TOOL0 pin externally.
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CHAPTER 2 PIN FUNCTIONS (78K0R/KC3-L, 78K0R/KD3-L, 78K0R/KE3-L)
(1) Port functions (2/2): 78K0R/KE3-L
Function Name
P70
I/O
I/O
Function
Port 7.
After Reset
Input port
8-bit I/O port.
P71
KR0/SO01/INTP4
KR1/SI01/INTP5
Input of P71, P72, P74, and P75 can be set to TTL buffer.
P72
Alternate Function
KR2/SCK01/INTP6
Output of P70, P72, P73, and P75 can be set to N-ch open-drain
P73
output (VDD tolerance).
KR3/SO00/TxD0
P74
Input/output can be specified in 1-bit units.
KR4/SI00/RxD0
Use of an on-chip pull-up resistor can be specified by a software
P75
KR5/SCK00
setting.
P76
KR6
P77
P80
KR7
I/O
P81
Port 8.
Analog input CMP0P/INTP3/
4-bit I/O port.
PGAI
Inputs/output can be specified in 1-bit units.
CMP0M
Inputs of P80 to P83 can be set as comparator inputs or
P82
CMP1P/INTP7
programmable gain amplifier inputs.
P83
P120
P121
CMP1M
I/O
Port 12.
Input
1-bit I/O port and 4-bit input port.
Input port
X1
For only P120, input/output can be specified in 1-bit units.
P122
X2/EXCLK
For only P120, use of an on-chip pull-up resistor can be specified
P123
XT1
by a software setting.
P124
P140
P141
INTP0/EXLVI
XT2
Output
Port 14.
Output port
PCLBUZ0
I/O
1-bit output port and 1-bit I/O port.
Input port
PCLBUZ1
Port 15.
Digital input
ANI8 to ANI11
4-bit I/O port.
port
For only P141, input/output can be specified.
For only P141, use of an on-chip pull-up resistor can be specified
by a software setting.
P150 to P153
I/O
Input/output can be specified in 1-bit units.
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CHAPTER 2 PIN FUNCTIONS (78K0R/KC3-L, 78K0R/KD3-L, 78K0R/KE3-L)
(2) Non-port functions (1/3): 78K0R/KE3-L
Function Name
ANI0 to ANI7
I/O
Input
Function
A/D converter analog input
After Reset
Alternate Function
Digital input
P20 to P27
port
P150 to P153
ANI8 to ANI11
Input
CMP0M
Input
Input voltage on the (−) side of comparator 0
CMP0P
Input
Input voltage on the (+) side of comparator 0
P80/INTP3/PGAI
CMP1M
Input
Input voltage on the (−) side of comparator 1
P83
CMP1P
Input
Input voltage on the (+) side of comparator 1
P82/INTP7
EXLVI
Input
Potential input for external low-voltage detection
Input port
P120/INTP0
INTP0
Input
External interrupt request input for which the valid edge (rising
Input port
P120/EXLVI
INTP1
Analog input P81
edge, falling edge, or both rising and falling edges) can be
P31/SI10/RxD1/
specified
SDA10
INTP2
P32/SCK10/SCL10
INTP3
Analog input P80/CMP0P/PGAI
INTP4
Input port
P70/KR0/SO01
INTP5
P71/KR1/SI01
INTP6
P72/KR2/SCK01
Analog input P82/CMP1P
INTP7
KR0
Input
Key interrupt input
Input port
P70/SO01/INTP4
KR1
P71/SI01/INTP5
KR2
P72/SCK01/INTP6
KR3
P73/SO00/TxD0
KR4
P74/SI00/RxD0
KR5
P75/SCK00
KR6
P76
KR7
P77
PCLBUZ0
Output
Clock output/buzzer output
PCLBUZ1
PGAI
REGC
Input
−
Programmable gain amplifier input
Connecting regulator output (2.4 V) stabilization capacitance for
Output port
P140
Input port
P141
Analog input P80/CMP0P/INTP3
−
−
internal operation.
Connect to VSS via a capacitor (0.47 to 1 μF).
RTCDIV
Output
Real-time counter clock (32 kHz division) output
Input port
P12/TI04/TO04/
RTCCL
RTCCL
Output
Real-time counter clock (32 kHz original oscillation) output
Input port
P12/TI04/TO04/
RTCDIV
RTC1HZ
Output
Real-time counter correction clock (1 Hz) output
RESET
Input
System reset input
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Input port
−
P52/SLTI/SLTO
−
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CHAPTER 2 PIN FUNCTIONS (78K0R/KC3-L, 78K0R/KD3-L, 78K0R/KE3-L)
(2) Non-port functions (2/3): 78K0R/KE3-L
Function Name
RxD0
I/O
Input
RxD1
SCK00
Function
After Reset
Input port
Serial data input to UART0
Serial data input to UART1
P74/KR4/SI00
P31/SI10/SDA10/
INTP1
Clock input/output for CSI00
I/O
Alternate Function
Input port
P75/KR5
SCK01
Clock input/output for CSI01
P72/KR2/INTP6
SCK10
Clock input/output for CSI10
P32/SCL10/INTP2
SCL0
SCL10
SDA0
2
I/O
Clock input/output for I C
2
I/O
Clock input/output for simplified I C
2
I/O
Serial data I/O for I C
2
Input port
P60
Input port
P32/SCK10/INTP2
Input port
P61
SDA10
I/O
Serial data I/O for simplified I C
Input port
P31/SI10/RxD1/
INTP1
SI00
Input
Serial data input to CSI00
Input port
P74/KR4/RxD0
SI01
Serial data input to CSI01
P71/KR1/INTP5
SI10
Serial data input to CSI10
P31/RxD1/SDA10/
INTP1
SLTI
Input
16-bit timer 00, 01 input
Input port
P52/RTC1HZ/SLTO
SLTO
Output
16-bit timer 00, 01 output
Input port
P52/RTC1HZ/SLTI
SO00
Output
Serial data output from CSI00
Input port
P73/KR3/TxD0
SO01
Serial data output from CSI01
P70/KR0/INTP4
SO10
Serial data output from CSI10
P30/TxD1
TI00
Input
External count clock input to 16-bit timer 00
Input port
P00
TI02
External count clock input to 16-bit timer 02
P10/TO02
TI03
External count clock input to 16-bit timer 03
P11/TO03
TI04
External count clock input to 16-bit timer 04
P12/TO04/
RTCDIV/RTCCL
TI05
External count clock input to 16-bit timer 05
P13/TO05
TI06
External count clock input to 16-bit timer 06
P14/TO06
TI07
External count clock input to 16-bit timer 07
P15/TO07
TO00
Output
16-bit timer 00 output
Input port
P01
TO02
16-bit timer 02 output
P10/TI02
TO03
16-bit timer 03 output
P11/TI03
TO04
16-bit timer 04 output
P12/TI04/
RTCDIV/RTCCL
TO05
16-bit timer 05 output
P13/TI05
TO06
16-bit timer 06 output
P14/TI06
TO07
16-bit timer 07 output
P15/TI07
TxD0
Output
TxD1
Input port
Serial data output from UART1
X1
−
X2
−
XT1
−
XT2
−
EXCLK
Serial data output from UART0
Input
Resonator connection for main system clock
Resonator connection for subsystem clock
External clock input for main system clock
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P73/KR3/SO00
P30/SO10
Input port
P121
Input port
P122/EXCLK
Input port
P123
Input port
P124
Input port
P122/X2
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CHAPTER 2 PIN FUNCTIONS (78K0R/KC3-L, 78K0R/KD3-L, 78K0R/KE3-L)
(2) Non-port functions (3/3): 78K0R/KE3-L
Function Name
I/O
−
VDD
Function
Positive power supply (P121 to P124 and other than ports (other
After Reset
Alternate Function
−
−
−
−
−
−
−
−
−
−
−
−
−
−
than RESET pin and FLMD0 pin))
−
EVDD
Positive power supply for ports (other than P20 to P27, P150 to
P153, P80 to P83, and P121 to P124), and RESET and FLMD0
pin
−
AVREF
• A/D converter and comparator reference voltage input
• Positive power supply for P20 to P27, P150 to P153, P80 to
P83, A/D converter, programmable gain amplifier, and
comparator
−
VSS
Ground potential (P121 to P124 and other than ports (other than
RESET pin and FLMD0 pin))
−
EVSS
Ground potential for ports (other than P20 to P27, P150 to P153,
and P121 to P124), and RESET and FLMD0 pin
−
AVSS
Ground potential for A/D converter, programmable gain amplifier,
comparator, P20 to P27, P150 to P153 and P80 to P83
−
FLMD0
Flash memory programming mode setting
TOOL0
I/O
Data I/O for flash memory programmer/debugger
Input port
P40
TOOL1
Output
Clock output for debugger
Input port
P41
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CHAPTER 2 PIN FUNCTIONS (78K0R/KC3-L, 78K0R/KD3-L, 78K0R/KE3-L)
2.2 Description of Pin Functions
Remark
The pins mounted depend on the product. See 1.4 Pin Configuration (Top View) and 2.1 Pin Function
List.
2.2.1 P00, P01 (port 0)
P00 and P01 function as an I/O port. These pins also function as timer I/O.
78K0R/KC3-L
78K0R/KC3-L (48-pin)
78K0R/KD3-L
78K0R/KE3-L
(μPD78F100y: y = 0 to 3)
(μPD78F100y: y = 1 to 3)
(μPD78F100y: y = 4 to 6)
(μPD78F100y: y = 7 to 9)
40-pin
44-pin
P00/ TI00
−
−
√
√
P11/TO00
−
−
√
√
Remark √: Mounted
The following operation modes can be specified in 1-bit units.
(1) Port mode
P00 and P01 function as an I/O port. P00 and P01 can be set to input or output port in 1-bit units using port mode
register 0 (PM0). Use of an on-chip pull-up resistor can be specified by pull-up resistor option register 0 (PU0).
(2) Control mode
P00 and P01 function as timer I/O.
(a) TI00
This is the pin for inputting an external count clock/capture trigger to 16-bit timer 00.
(b) TO00
This is the timer output pin of 16-bit timer 00.
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CHAPTER 2 PIN FUNCTIONS (78K0R/KC3-L, 78K0R/KD3-L, 78K0R/KE3-L)
2.2.2 P10 to P17 (port 1)
P10 to P17 function as an I/O port. These pins also function as timer I/O and real-time counter clock output.
78K0R/KC3-L
78K0R/KC3-L (48-pin)
78K0R/KD3-L
78K0R/KE3-L
(μPD78F100y: y = 0 to 3)
(μPD78F100y: y = 1 to 3)
(μPD78F100y: y = 4 to 6)
(μPD78F100y: y = 7 to 9)
40-pin
44-pin
P10/TI02/TO02
√
√
√
√
P11/TO00/TI03/
√
√
√
√
√
√
√
TO03
P12/TI04/TO04/
P12/TI04/
RTCDIV/RTCCL
TO04
√
Note 1
√
√
P14/TI06/TO06
−
Note 2
√
−
Note 2
−
Note 2
√
P15/TI07/TO07
−
Note 2
−
Note 2
−
Note 2
√
P13/TI05/TO05
√
P16
−
−
−
√
P17
−
−
−
√
Notes 1.
2.
40-pin product of the 78K0R/KC3-L does not have a RTCDIV/RTCCL pin.
TI06/TO06 and TI07/TO07 are shared with P50 and P51, respectively, in products other than the 78K0R/KE3L.
Remark √: Mounted
The following operation modes can be specified in 1-bit units.
(1) Port mode
P10 to P17 function as an I/O port. P10 to P17 can be set to input or output port in 1-bit units using port mode
register 1 (PM1). Use of an on-chip pull-up resistor can be specified by pull-up resistor option register 1 (PU1).
(2) Control mode
P10 to P17 function as timer I/O and real-time counter clock output.
(a) TI02 to TI07
These are the pins for inputting an external count clock/capture trigger to 16-bit timers 02 to 07.
(b) TO02 to TO07
These are the timer output pins of 16-bit timers 02 to 07.
(c) RTCDIV
This is the real-time counter clock (32 kHz division) output pin.
(d) RTCCL
This is the real-time counter clock (32 kHz original oscillation) output pin.
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2.2.3 P20 to P27 (port 2)
P20 to P27 function as an I/O port. These pins also function as A/D converter analog input.
78K0R/KC3-L
78K0R/KC3-L (48-pin)
78K0R/KD3-L
78K0R/KE3-L
(μPD78F100y: y = 0 to 3)
(μPD78F100y: y = 1 to 3)
(μPD78F100y: y = 4 to 6)
(μPD78F100y: y = 7 to 9)
40-pin
44-pin
P20/ANI0
√
√
√
√
P21/ANI1
√
√
√
√
P22/ANI2
√
√
√
√
P23/ANI3
√
√
√
√
P24/ANI4
√
√
√
√
P25/ANI5
√
√
√
√
P26/ANI6
√
√
√
√
P27/ANI7
√
√
√
√
Remark √: Mounted
The following operation modes can be specified in 1-bit units.
(1) Port mode
P20 to P27 function as an I/O port. P20 to P27 can be set to input or output port in 1-bit units using port mode
register 2 (PM2).
(2) Control mode
P20 to P27 function as the A/D converter analog input pins (ANI0 to ANI7). When using these pins as the analog
input pins, see 13.6 (5) ANI0/P20 to ANI7/P27, ANI8/P150 to ANI15/P157.
Caution ANI0/P20 to ANI7/P27 are set in the digital input (general-purpose port) mode after release of reset.
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2.2.4 P30 to P33 (port 3)
P30 to P33 function as an I/O port. These pins also function as serial interface data I/O, clock I/O, and external
interrupt request input.
Input to the P30 and P31 pins can be specified through a normal input buffer or a TTL input buffer in 1-bit units, using
port input mode register 3 (PIM3).
Output from the P30 to P32 pins can be specified as normal CMOS output or N-ch open-drain output (VDD tolerance) in
1-bit units, using port output mode register 3 (POM3).
78K0R/KC3-L
78K0R/KC3-L (48-pin)
78K0R/KD3-L
78K0R/KE3-L
(μPD78F100y: y = 0 to 3)
(μPD78F100y: y = 1 to 3)
(μPD78F100y: y = 4 to 6)
(μPD78F100y: y = 7 to 9)
40-pin
44-pin
P30/SO10/TxD1
√
√
√
√
P31/SI10/RxD1/
√
√
√
√
√
√
√
√
−
−
−
√
SDA10/INTP1
P32/SCK10/
SCL10/INTP2
P33
Remark √: Mounted
The following operation modes can be specified in 1-bit units.
(1) Port mode
P30 to P33 function as an I/O port. P30 to P33 can be set to input or output port in 1-bit units using port mode
register 3 (PM3). Use of an on-chip pull-up resistor can be specified by pull-up resistor option register 3 (PU3).
(2) Control mode
P30 to P33 function as serial interface data I/O, clock I/O, and external interrupt request input.
(a) SI10
This is a serial data input pin of serial interface CSI10.
(b) SO10
This is a serial data output pin of serial interface CSI10.
(c) SCK10
This is a serial clock I/O pin of serial interface CSI10.
(d) TxD1
This is a serial data output pin of serial interface UART1.
(e) RxD1
This is a serial data input pin of serial interface UART1.
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(f) SDA10
This is a serial data I/O pin of serial interface for simplified I2C.
(g) SCL10
This is a serial clock I/O pin of serial interface for simplified I2C.
(h) INTP1, INTP2
These are the external interrupt request input pins for which the valid edge (rising edge, falling edge, or both
rising and falling edges) can be specified.
Caution To use P30/SO10/TxD1 and P32/SCK10/SCL10/INTP2 as general-purpose ports, set serial
communication operation setting register 02 (SCR02) to the default status (0087H). In addition,
clear port output mode register 3 (POM3) to 00H.
2.2.5 P40 to P43 (port 4)
P40 to P43 function as an I/O port. These pins also function as data I/O for a flash memory programmer/debugger and
clock output.
78K0R/KC3-L
78K0R/KC3-L (48-pin)
78K0R/KD3-L
78K0R/KE3-L
(μPD78F100y: y = 0 to 3)
(μPD78F100y: y = 1 to 3)
(μPD78F100y: y = 4 to 6)
(μPD78F100y: y = 7 to 9)
40-pin
44-pin
P40/TOOL0
√
√
√
√
P41/TOOL1
√
√
√
√
P42
−
−
−
√
P43
−
−
−
√
Remark √: Mounted
The following operation modes can be specified in 1-bit units.
(1) Port mode
P40 to P43 function as an I/O port. P40 to P43 can be set to input or output port in 1-bit units using port mode
register 4 (PM4). Use of an on-chip pull-up resistor can be specified by pull-up resistor option register 4 (PU4).
Be sure to connect an external pull-up resistor to P40 when on-chip debugging is enabled (by using an option byte).
(2) Control mode
P40 to P43 function as data I/O for a flash memory programmer/debugger and clock output.
(a) TOOL0
This is a data I/O pin for a flash memory programmer/debugger.
Be sure to pull up this pin externally when on-chip debugging is enabled (pulling it down is prohibited).
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(b) TOOL1
This is a clock output pin for a debugger.
When the on-chip debug function is used, the P41/TOOL1 pin can be used as follows by the mode setting on the
debugger.
1-line mode: can be used as a port (P41).
2-line mode: used as a TOOL1 pin and cannot be used as a port (P41).
Caution The function of the P40/TOOL0 pin varies as described in (a) to (c) below.
In the case of (b) or (c), make the specified connection.
(a) In normal operation mode and when on-chip debugging is disabled (OCDENSET = 0) by an
option byte (000C3H)
=> Use this pin as a port pin (P40).
(b) In normal operation mode and when on-chip debugging is enabled (OCDENSET = 1) by an
option byte (000C3H)
=> Connect this pin to VDD via an external resistor, and always input a high level to the pin
before reset release.
(c) When on-chip debug function is used, or in write mode of flash memory programmer
=> Use this pin as TOOL0.
Directly connect this pin to the on-chip debug emulator or a flash memory programmer,
or pull it up by connecting it to VDD via an external resistor.
2.2.6 P50 to P53 (port 5)
P50 to P53 function as an I/O port. These pins also function as real-time counter correction clock output and timer I/O.
78K0R/KC3-L
78K0R/KC3-L (48-pin)
78K0R/KD3-L
78K0R/KE3-L
(μPD78F100y: y = 0 to 3)
(μPD78F100y: y = 1 to 3)
(μPD78F100y: y = 4 to 6)
(μPD78F100y: y = 7 to 9)
40-pin
44-pin
P50/TI06/TO06
√
√
√
P50
Note
P51/TI07/TO07
√
√
√
P51
Note
√
√
√
−
−
√
P52/RTC1HZ/
−
√
SLTI/SLTO
−
P53
Note
TI06/TO06 and TI07/TO07 are shared only in the 78K0R/KC3-L and 78K0R/KD3-L. The 78K0R/KE3-L does not
have a sharing function.
Remark √: Mounted
The following operation modes can be specified in 1-bit units.
(1) Port mode
P50 to P53 function as an I/O port. P50 to P53 can be set to input or output port in 1-bit units using port mode
register 5 (PM5). Use of an on-chip pull-up resistor can be specified by pull-up resistor option register 5 (PU5).
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(2) Control mode
P50 to P53 function as real-time counter correction clock output and timer I/O.
(a) RTC1HZ
This is the real-time counter correction clock (1 Hz) output pin.
(b) SLTI
This is used as a pin for inputting an external count clock or a capture trigger to 16-bit timers 00 and 01, by
setting the input switching control register (ISC).
(c) SLTO
This is used as a timer output pin of 16-bit timers 00 and 01, by setting the input switching control register (ISC).
(d) TI06, TI07
These are the pins for inputting an external count clock/capture trigger to 16-bit timers 06 and 07.
(e) TO06, TO07
These are the timer output pins of 16-bit timers 06 and 07.
2.2.7 P60 and P61 (port 6)
P60 and P61 function as an I/O port. These pins also function as serial interface IICA data I/O and clock I/O.
78K0R/KC3-L
78K0R/KC3-L (48-pin)
78K0R/KD3-L
78K0R/KE3-L
(μPD78F100y: y = 0 to 3)
(μPD78F100y: y = 1 to 3)
(μPD78F100y: y = 4 to 6)
(μPD78F100y: y = 7 to 9)
40-pin
44-pin
P60/SCL0
−
√
√
√
P61/SDA0
−
√
√
√
Remark √: Mounted
The following operation modes can be specified in 1-bit units.
(1) Port mode
P60 and P61 function as an I/O port. P60 and P61 can be set to input port or output port in 1-bit units using port
mode register 6 (PM6).
Output of P60 and P61 is N-ch open-drain output (6 V tolerance).
(2) Control mode
P60 and P61 function as serial interface IICA data I/O and clock I/O.
(a) SDA0
This is a serial data I/O pin of serial interface IICA.
(b) SCL0
This is a serial clock I/O pin of serial interface IICA.
2.2.8 P70 to P77 (port 7)
P70 to P77 function as an I/O port. These pins also function as key interrupt input, serial interface data I/O, clock I/O,
and external interrupt request input.
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Input to the P71, P72, P74, and P75 pins can be specified through a normal input buffer or a TTL input buffer in 1-bit
units, using port input mode register 7 (PIM7).
Output from the P70, P72, P73, and P75 pins can be specified as normal CMOS output or N-ch open-drain output (VDD
tolerance) in 1-bit units, using port output mode register 7 (POM7).
78K0R/KC3-L
78K0R/KC3-L (48-pin)
78K0R/KD3-L
78K0R/KE3-L
(μPD78F100y: y = 0 to 3)
(μPD78F100y: y = 1 to 3)
(μPD78F100y: y = 4 to 6)
(μPD78F100y: y = 7 to 9)
√
√
√
√
√
√
√
√
√
√
√
√
√
√
√
√
√
√
√
√
P75/KR5/SCK00
√
√
√
√
P76/KR6
−
−
√
√
P77/KR7
−
−
√
√
40-pin
P70/KR0/SO01/
44-pin
INTP4
P71/KR1/SI01/
INTP5
P72/KR2/
SCK01/INTP6
P73/KR3/SO00/
TxD0
P74/KR4/SI00/
RxD0
Remark √: Mounted
The following operation modes can be specified in 1-bit units.
(1) Port mode
P70 to P77 function as an I/O port. P70 to P77 can be set to input or output port in 1-bit units using port mode
register 7 (PM7). Use of an on-chip pull-up resistor can be specified by pull-up resistor option register 7 (PU7).
(2) Control mode
P70 to P77 function as key interrupt input, serial interface data I/O, clock I/O, and external interrupt request input.
(a) KR0 to KR7
These are the key interrupt input pins.
(b) SI00, SI01
These are the serial data input pin of serial interface CSI00 and CSI01.
(c) SO00, SO01
These are the serial data output pin of serial interface CSI00 and CSI01.
(d) SCK00, SCK01
These are the serial clock I/O pins of serial interface CSI00 and CSI01.
(e) RxD0
This is a serial data input pin of serial interface UART0.
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(f) TxD0
This is a serial data output pin of serial interface UART0.
(g) INTP4 to INTP6
These are the external interrupt request input pin for which the valid edge (rising edge, falling edge, or both rising
and falling edges) can be specified.
Caution
To use P70/KR0/SO01/INTP4, P72/KR2/SCK01/INTP6, P73/KR3/SO00/TxD0, and P75/KR5/SCK00 as
general-purpose ports, set serial communication operation setting registers 00 and 01 (SCR00
and SCR01) to the default status (0087H). In addition, clear port output mode register 7 (POM7)
to 00H.
2.2.9 P80 to P83 (port 8)
P80 to P83 function as an I/O port. These pins also function as input voltages on the (+) side of comparators 0 and 1,
input voltages on the (−) side of comparators 0 and 1, external interrupt request inputs, and programmable gain amplifier
inputs.
Inputs to the P80 to P83 pins must be enabled or disabled in 1-bit units using port input mode register 8 (PIM8).
78K0R/KC3-L
78K0R/KC3-L (48-pin)
78K0R/KD3-L
78K0R/KE3-L
(μPD78F100y: y = 0 to 3)
(μPD78F100y: y = 1 to 3)
(μPD78F100y: y = 4 to 6)
(μPD78F100y: y = 7 to 9)
√
√
√
√
√
√
√
√
√
√
√
√
√
√
40-pin
P80/CMP0P/
44-pin
INTP3/PGAI
P81/CMP0M
P82/CMP1P/
−
√
INTP7
P83/CMP1M
√
Remark √: Mounted
The following operation modes can be specified in 1-bit units.
(1) Port mode
P80 to P83 function as an I/O port. P80 to P83 can be set to input port or output port in 1-bit units using port mode
register 8 (PM8).
(2) Control mode
P80 to P83 function as input voltages on the (+) side of comparators 0 and 1, input voltages on the (−) side of
comparators 0 and 1, external interrupt request inputs, and programmable gain amplifier inputs.
(a) CMP0P, CMP1P
These are the input voltage pins on the (+) sides of comparators 0 and 1.
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(b) CMP0M, CMP1M
These are the input voltage pins on the (−) sides of comparators 0 and 1.
(c) INTP3, INTP7
These are the external interrupt request input pin for which the valid edge (rising edge, falling edge, or both rising
and falling edges) can be specified.
(d) PGAI
This is a programmable gain amplifier input pin.
2.2.10 P120 to P124 (port 12)
P120 functions as an I/O port. P121 to P124 function as ant input port. These pins also function as external interrupt
request input, potential input for external low-voltage detection, connecting resonator for main system clock, connecting
resonator for subsystem clock, and external clock input for main system clock.
78K0R/KC3-L
78K0R/KC3-L (48-pin)
78K0R/KD3-L
78K0R/KE3-L
(μPD78F100y: y = 0 to 3)
(μPD78F100y: y = 1 to 3)
(μPD78F100y: y = 4 to 6)
(μPD78F100y: y = 7 to 9)
√
√
√
√
P121/X1
√
√
√
√
P122/X2/
√
√
√
√
40-pin
P120/INTP0/
44-pin
EXLVI
EXCLK
P123/XT1
−
√
√
√
√
P124/XT2
−
√
√
√
√
Remark √: Mounted
The following operation modes can be specified in 1-bit units.
(1) Port mode
P120 functions as an I/O port. P120 can be set to input or output port using port mode register 12 (PM12). Use of an
on-chip pull-up resistor can be specified by pull-up resistor option register 12 (PU12).
P121 to P124 function as an input port.
(2) Control mode
P120 to P124 function as external interrupt request input, potential input for external low-voltage detection, connecting
resonator for main system clock, connecting resonator for subsystem clock, and external clock input for main system
clock.
(a) INTP0
This is an external interrupt request input pin for which the valid edge (rising edge, falling edge, or both rising and
falling edges) can be specified.
(b) EXLVI
This is a potential input pin for external low-voltage detection.
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(c) X1, X2
These are the pins for connecting a resonator for main system clock.
(d) EXCLK
This is an external clock input pin for main system clock.
(e) XT1, XT2
These are the pins for connecting a resonator for subsystem clock.
2.2.11 P140, P141 (port 14)
P140 functions as a 1-bit output port. P141 functions as a 1-bit I/O port. These pins also function as clock/buzzer
output.
78K0R/KC3-L
78K0R/KC3-L (48-pin)
78K0R/KD3-L
78K0R/KE3-L
(μPD78F100y: y = 0 to 3)
(μPD78F100y: y = 1 to 3)
(μPD78F100y: y = 4 to 6)
(μPD78F100y: y = 7 to 9)
40-pin
44-pin
P140/PCLBUZ0
−
√
√
√
P141/PCLBUZ1
−
−
−
√
Remark √: Mounted
The following operation modes can be specified in 1-bit units.
(1) Port mode
P140 functions as a 1-bit output port.
P141 functions as a 1-bit I/O port. P141 can be set to input or output port in 1-bit units using port mode register 14
(PM14). Use of an on-chip pull-up resistor can be specified by pull-up resistor option register 14 (PU14).
(2) Control mode
P140 and P141 function as clock/buzzer output.
(a) PCLBUZ0, PCLBUZ1
These are the clock/buzzer output pins.
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2.2.12 P150 to P153 (port 15)
P150 to P153 function as an I/O port. These pins also function as A/D converter analog input.
78K0R/KC3-L
78K0R/KC3-L (48-pin)
78K0R/KD3-L
78K0R/KE3-L
(μPD78F100y: y = 0 to 3)
(μPD78F100y: y = 1 to 3)
(μPD78F100y: y = 4 to 6)
(μPD78F100y: y = 7 to 9)
40-pin
44-pin
P150/ANI8
√
√
√
√
P151/ANI9
√
√
√
√
P152/ANI10
−
√
√
√
P153/ANI11
−
−
−
√
Remark √: Mounted
The following operation modes can be specified in 1-bit units.
(1) Port mode
P150 to P153 function as an I/O port. P150 to P153 can be set to input or output port in 1-bit units using port mode
register 15 (PM15).
(2) Control mode
P150 to P153 function as the A/D converter analog input pins (ANI8 to ANI11). When using these pins as the analog
input pins, see 13.6 (5) ANI0/P20 to ANI7/P27 and ANI8/P150 to ANI15/P157.
Caution ANI8/P150 to ANI11/P153 are set in the digital input (general-purpose port) mode after release of
reset.
2.2.13 AVREF, AVSS, VDD, EVDD, VSS, EVSS
78K0R/KC3-L
78K0R/KC3-L (48-pin)
78K0R/KD3-L
78K0R/KE3-L
(μPD78F100y: y = 0 to 3)
(μPD78F100y: y = 1 to 3)
(μPD78F100y: y = 4 to 6)
(μPD78F100y: y = 7 to 9)
40-pin
44-pin
AVREF
√
√
√
√
AVSS
√
√
√
√
VDD
√
√
√
√
EVDD
−
−
−
√
VSS
√
√
√
√
EVSS
−
−
−
√
(1) AVREF
This is the A/D converter and comparator reference voltage input pin and the positive power supply pin of P20 to P27,
P150 to P153, P80 to P83, A/D converter, programmable gain amplifier, and comparator.
When all pins of port 2, port 15, and port 8 are used as the analog port pins, make the potential of AVREF be such that
1.8 V ≤ AVREF ≤ VDD. When one or more of the pins of port 2, port 15, and port 8 are used as the digital port pins or
when the A/D converter, programmable gain amplifier, and comparator are not used, make AVREF the same potential
as EVDD or VDD.
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(2) AVSS
This is the ground potential pin of A/D converter, programmable gain amplifier, comparator, P20 to P27, P150 to P153,
and P80 to P83. Even when the A/D converter, programmable gain amplifier, and comparator are not used, always
use this pin with the same potential as EVSS or VSS.
(3) VDD, EVDD
VDD is the positive power supply pin for P121 to P124 and other than ports (other than the RESET pin and FLMD0
pin) Note.
EVDD is the positive power supply pin for ports other than those of P20 to P27, P150 to P153, P80 to P83, and P121
to P124, as well as for the RESET pin and FLMD0 pin.
Note With products not provided with an EVDD pin, use VDD as the positive power supply pin for port pins other than
P20 to P27, P150 to P153, and P80 to P83, as well as for pins other than those of ports.
(4) VSS, EVSS
VSS is the ground potential pin for P121 to P124 and other than ports (other than the RESET pin and FLMD0 pin) Note.
EVSS is the ground potential pin for ports other than those of P20 to P27, P150 to P153, P80 to P83, and P121 to
P124, as well as for the RESET pin and FLMD0 pin.
Note With products not provided with an EVSS pin, use VSS as the ground potential pin for port pins other than P20
to P27, P150 to P153, P80 to P83, as well as for pins other than those of ports.
2.2.14 RESET
This is the active-low system reset input pin.
When the external reset pin is not used, connect this pin directly to EVDD or via a resistor.
When the external reset pin is used, design the circuit based on VDD.
2.2.15 REGC
This is the pin for connecting regulator output (2.4 V) stabilization capacitance for internal operation. Connect this pin
to VSS via a capacitor (0.47 to 1 μF).
Also, use a capacitor with good characteristics, since it is used to stabilize internal voltage.
REGC
VSS
Caution Keep the wiring length as short as possible for the broken-line part in the above figure.
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2.2.16 FLMD0
This is a pin for setting flash memory programming mode.
Perform either of the following processing.
(a) In normal operation mode
It is recommended to leave this pin open during normal operation.
The FLMD0 pin must always be kept at the VSS level before reset release but does not have to be pulled down
externally because it is internally pulled down by reset. However, pulling it down must be kept selected (i.e.,
FLMDPUP = “0”, default value) by using bit 7 (FLMDPUP) of the background event control register (BECTL) (see
26.5 (1) Back ground event control register). To pull it down externally, use a resistor of 200 kΩ or smaller.
Self programming and the rewriting of flash memory with the programmer can be prohibited using hardware, by
directly connecting this pin to the VSS pin.
(b) In self programming mode
It is recommended to leave this pin open when using the self programming function. To pull it down externally,
use a resistor of 100 kΩ to 200 kΩ.
In the self programming mode, the setting is switched to pull up in the self programming library.
(c) In flash memory programming mode
Directly connect this pin to a flash memory programmer when data is written by the flash memory programmer.
This supplies a writing voltage of the VDD level to the FLMD0 pin.
The FLMD0 pin does not have to be pulled down externally because it is internally pulled down by reset. To pull
it down externally, use a resistor of 1 kΩ to 200 kΩ.
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2.3 Pin I/O Circuits and Recommended Connection of Unused Pins
Table 2-3 shows the types of pin I/O circuits and the recommended connections of unused pins.
Table 2-3. Connection of Unused Pins (1/3)
Pin Name
I/O Circuit Type
P00/TI00
8-R
P01/TO00
5-AG
P10/TI02/TO02
8-R
I/O
I/O
Recommended Connection of Unused Pins
Input:
Independently connect to EVDD or EVSS via a resistor.
Output:
Leave open.
Input:
Independently connect to AVREF or AVSS via a resistor.
Output:
Leave open.
Input:
Independently connect to EVDD or EVSS via a resistor.
Output:
Leave open.
P11/TI03/TO03
P12/TI04/TO04/RTCDIV/
RTCCL
P13/TI05/TO05
P14/TI06/TO06
Note 1
P15/TI07/TO07
Note 1
P16
P17
P20/ANI0 to P27/ANI7
Note 2
P30/SO10/TxD1
P31/SI10/RxD1/SDA10/
11-G
5-AG
5-AN
INTP1
<When N-ch open-drain>
Set the port output latch to 0 and leave open with low level out put.
P32/SCK10/SCL10/INTP2
P33
5-AG
Input:
Independently connect to EVDD or EVSS via a resistor.
Output: Leave open.
8-R
P40/TOOL0
<When on-chip debugging is enabled>
Pull this pin up (pulling it down is prohibited).
<When on-chip debugging is disabled>
Input:
Independently connect to EVDD or EVSS via a resistor.
Output:
Leave open.
P41/TOOL1
Input:
Independently connect to EVDD or EVSS via a resistor.
P42
Output: Leave open.
5-AG
P43
P50/TI06/TO06
Note 3
P51/TI07/TO07
Note 3
8-R
P52/RTC1HZ/SLTI/SLTO
P53
5-AG
Notes 1. TI06/TO06 and TI07/TO07 are shared with P50 and P51, respectively, in products other than the 78K0R/KE3-L.
2. P20/ANI0 to P27/ANI7 are set in the digital input port mode after release of reset.
3. TI06/TO06 and TI07/TO07 are shared with P14 and P15, respectively, in the 78K0R/KE3-L.
Remark
With products not provided with an EVDD or EVSS pin, replace EVDD with VDD, or replace EVSS with VSS.
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Table 2-3. Connection of Unused Pins (2/3)
Pin Name
I/O Circuit Type
13-R
P60/SCL0
I/O
I/O
Recommended Connection of Unused Pins
Input:
Independently connect to EVDD or EVSS via a resistor, or
connect directly to EVSS.
P61/SDA0
Output: Set the port output latch to 0 and leave open with low level
out put.
P70/KR0/SO01/INTP4
8-R
Input:
Independently connect to EVDD or EVSS via a resistor.
Output:
Leave open.
<When N-ch open-drain>
Set the port output latch to 0 and leave open with low level out put.
P71/KR1/SI01/INTP5
5-AN
Input:
Independently connect to EVDD or EVSS via a resistor.
Output: Leave open.
Independently connect to EVDD or EVSS via a resistor.
P72/KR2/SCK01/INTP6
Input:
P73/KR3/SO00/TxD0
Output: Leave open.
8-R
<When N-ch open-drain>
Set the port output latch to 0 and leave open with low level out put.
P74/KR4/SI00/RxD0
5-AN
P75/KR5/SCK00
Input:
Independently connect to EVDD or EVSS via a resistor.
Output:
Leave open.
Input:
Independently connect to EVDD or EVSS via a resistor.
Output:
Leave open.
<When N-ch open-drain>
Set the port output latch to 0 and leave open with low level out put.
8-R
P76/KR6
P77/KR7
Input:
Independently connect to EVDD or EVSS via a resistor.
Output:
Leave open.
11-J
Input:
P81/CMP0M
11-H
Output: Leave open.
P82/CMP1P/INTP7
11-I
P83/CMP1M
11-H
P120/INTP0/EXLVI
8-R
P80/CMP0P/INTP3/PGAI
Input:
Independently connect to AVREF or AVSS via a resistor.
Independently connect to EVDD or EVSS via a resistor.
Output: Leave open.
Remark
With products not provided with an EVDD or EVSS pin, replace EVDD with VDD, or replace EVSS with VSS.
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Table 2-2. Connection of Unused Pins (3/3)
Pin Name
Note 1
I/O Circuit Type
37-C
P121/X1
P122/X2/EXCLK
P123/XT1
Note 1
P124/XT2
Note 1
I/O
Recommended Connection of Unused Pins
Input
Independently connect to VDD or VSS via a resistor.
Leave open.
Note 1
37-B
P140/PCLBUZ0
3-C
Output
P141/PCLBUZ1
5-AG
I/O
Input:
Independently connect to EVDD or EVSS via a resistor.
Output: Leave open.
P150/ANI8 to
P153/ANI11
11-G
Note 2
−
AVREF
−
Input:
Independently connect to AVREF or AVSS via a resistor.
Output:
Leave open.
<When one or more of P20 to P27, P150 to P153, or P80 to P83
are set as a digital port>
Make this pin the same potential as EVDD or VDD.
<When all of P20 to P27, P150 to P153, and P80 to P83 are set as
analog ports>
Make this pin to have a potential where 1.8 V ≤ AVREF ≤ VDD.
−
AVSS
FLMD0
2-W
RESET
2
Make this pin the same potential as EVSS or VSS.
−
Leave open or connect to VSS via a resistor of 100 kΩ or more.
Input
−
REGC
−
−
Connect directly to EVDD or via a resistor.
Connect to VSS via capacitor (0.47 to 1 μF).
Notes 1. Use recommended connection above in input port mode (see Figure 7-3 Format of Clock Operation Mode
Control Register (CMC)) when these pins are not used.
2. P150/ANI8 to P153/ANI11 are set in the digital input port mode after release of reset.
Remark
With products not provided with an EVDD or EVSS pin, replace EVDD with VDD, or replace EVSS with VSS.
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Figure 2-1. Pin I/O Circuit List (1/3)
Type 2
Type 2-W
EVDD
IN
P-ch
Pull-up
enable
N-ch
Pll-down
enable
EVSS
Schmitt-triggered input with hysteresis characteristics
IN
Schmitt-triggered input with hysteresis characteristics
Type 3-C
Type 5-AG
EVDD
EVDD
Pull-up
enable
P-ch
P-ch
EVDD
Data
OUT
Data
P-ch
IN/OUT
N-ch
Output
disable
N-ch
EVSS
EVSS
Input
enable
Type 5-AN
Type 8-R
EVDD
EVDD
Pull-up
enable
P-ch
Pull-up
enable
P-ch
EVDD
Data
P-ch
Output
disable
N-ch
EVDD
IN/OUT
Data
P-ch
IN/OUT
EVSS
CMOS
Output
disable
N-ch
EVSS
TTL
Input
characteristic
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Figure 2-1. Pin I/O Circuit List (2/3)
Type 11-G
Type 11-H
AVREF
data
P-ch
IN/OUT
AVREF
output
disable
Data
N-ch
P-ch
IN/OUT
Output
disable
Voltage generated by internal amplifier or
CMP0P (pin level)
AVSS
N-ch
Comparator
+
AVSS
P-ch
_
P-ch
N-ch
Comparator
+
_
N-ch
P-ch
Series resistor string voltage
AVSS
N-ch
Internally
generated
reference
voltage
Input enable
input enable
Type 11-I
Type 11-J
AVREF
data
P-ch
AVREF
data
P-ch
output
disable
N-ch
IN/OUT
AVSS
output
disable
N-ch
_
P-ch
N-ch
Voltage generated
by internal amplifier
P-ch
P-ch
N-ch
N-ch
+
AVSS
OP
AMP
AVSS
VREF
(threshold voltage)
P-ch
+
N-ch
_
Comparator
P-ch
+
_
N-ch
Internally generated voltage
or CMP0M (pin level)
P-ch
+
Voltage generated by internal amplifier or
CMP1M (pin level)
_
N-ch
CMP1P
(pin level)
Internally generated voltage
or CMP1M (pin level)
input enable
input enable
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Figure 2-1. Pin I/O Circuit List (3/3)
Type 13-R
Type 37-B
IN/OUT
data
output disable
XT2
input
enable
N-ch
EVSS
amp
enable
P-ch
N-ch
XT1
input
enable
Type 37-C
X2
input
enable
amp
enable
P-ch
N-ch
X1
input
enable
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CHAPTER 3 PIN FUNCTIONS (78K0R/KF3-L, 78K0R/KG3-L)
CHAPTER 3 PIN FUNCTIONS (78K0R/KF3-L, 78K0R/KG3-L)
Caution For the functions of the pins in the 78K0R/KC3-L, 78K0R/KD3-L, 78K0R/KE3-L, see CHAPTER 2 PIN
FUNCTIONS (78K0R/KC3-L, 78K0R/KD3-L, 78K0R/KE3-L).
3.1 Pin Function List
Pin I/O buffer power supplies depend on the product. The relationship between these power supplies and the pins is
shown below.
Table 3-1. Pin I/O Buffer Power Supplies (AVREF, EVDD0, VDD)
• 78K0R/KF3-L: 80-pin plastic LQFP (14x14)
80-pin plastic LQFP (fine pitch) (12x12)
Power Supply
Corresponding Pins
AVREF
P20 to P27, P150 to P153
EVDD0
• Port pins other than P20 to P27, P121 to P124, and P150 to P153
• RESET and FLMD0 pins
• P121 to P124
VDD
• Pins other than port pins (excluding RESET and FLMD0 pins)
Table 3-2. Pin I/O Buffer Power Supplies (AVREF, EVDD0, EVDD1, VDD)
• 78K0R/KG3-L: 100-pin plastic LQFP (14x20)
100-pin plastic LQFP (fine pitch) (14x14)
100-pin plastic FBGA (6x6) Note
Power Supply
Corresponding Pins
AVREF
P20 to P27, P150 to P157
EVDD0, EVDD1
• Port pins other than P20 to P27, P121 to P124, and P150 to P157
• RESET and FLMD0 pins
• P121 to P124
VDD
• Pins other than port pins (excluding RESET and FLMD0 pins)
Note
μPD78F1013 and μPD78F1014 only
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3.1.1 78K0R/KF3-L
(1) Port functions (1/2): 78K0R/KF3-L
Function Name
P02
I/O
I/O
Function
Port 0.
After Reset
Input port
5-bit I/O port.
P03
SO10/TxD1
SI10/RxD1/SDA10
Input of P03 and P04 can be set to TTL input buffer.
P04
Alternate Function
SCK10/SCL10
Output of P02 to P04 can be set to N-ch open-drain output
P05
(VDD tolerance).
TI05/TO05
P06
Input/output can be specified in 1-bit units.
TI06/TO06
Use of an on-chip pull-up resistor can be specified by a
software setting.
I/O
P10
Port 1.
Input port
8-bit I/O port.
P11
SI00/RxD0
Input of P10 and P11 can be set to TTL input buffer.
P12
SCK00
SO00/TxD0
Output of P10 and P12 can be set to N-ch open-drain output
P13
TxD3
(VDD tolerance).
P14
Input/output can be specified in 1-bit units.
RxD3
P15
Use of an on-chip pull-up resistor can be specified by a
RTCDIV/RTCCL
software setting.
P16
TI01/TO01/INTP5
P17
TI02/TO02
P20 to P27
I/O
Port 2.
Digital input
8-bit I/O port.
port
ANI0 to ANI7
Input/output can be specified in 1-bit units.
I/O
P30
Port 3.
Input port
2-bit I/O port.
P31
RTC1HZ/INTP3
TI03/TO03/INTP4
Input/output can be specified in 1-bit units.
Use of an on-chip pull-up resistor can be specified by a
software setting.
P40
Note 1
I/O
Port 4.
Input port
8-bit I/O port.
P41
TOOL1
Input/output can be specified in 1-bit units.
P42
TI04/TO04
Use of an on-chip pull-up resistor can be specified by a
P43
TOOL0
SCK01
software setting.
P44
SI01
P45
SO01
−
P46, P47
P50
P51
P52
P53
I/O
Port 5.
6-bit I/O port.
Input/output can be specified in 1-bit units.
Use of an on-chip pull-up resistor can be specified by a
software setting.
Input port
INTP1/SCK40
Note 2
Note 2
INTP2/SI40/RxD4
Note 2
TO00/SO40/TxD4
TI00/SCK41
Note 2
Note 2
P54
TI07/TO07/SI41
P55
PCLBUZ1/INTP7/
SO41
Note 2
Notes 1. If on-chip debugging is enabled by using an option byte, be sure to pull up the P40/TOOL0 pin externally
(see Caution in 3.2.5 P40 to P47 (port 4)).
2. SCK40, SCK41, SI40, SI41, SO40, SO41, TxD4, RxD4 are only mounted in the μ PD78F1027 and 78F1028.
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(1) Port functions (2/2): 78K0R/KF3-L
Function Name
P60
I/O
I/O
Function
Port 6.
After Reset
Input port
8-bit I/O port.
P61
Alternate Function
SCL0
SDA0
Output of P60 to P63 can be set to N-ch open-drain output (6
P62, P63
−
V tolerance).
P64 to P67
Input/output can be specified in 1-bit units.
TI10/TO10 to
For only P64 to P67, use of an on-chip pull-up resistor can be
TI13/TO13
specified by a software setting.
P70 to P73
I/O
Port 7.
Input port
8-bit I/O port.
P74 to P77
KR0 to KR3
KR4/INTP8 to
Input/output can be specified in 1-bit units.
KR7/INTP11
Use of an on-chip pull-up resistor can be specified by a
software setting.
P90, P91
I/O
Port 9.
Input port
−
Input port
−
2-bit I/O port.
Input/output can be specified in 1-bit units.
Use of an on-chip pull-up resistor can be specified by a
software setting.
P110, P111
I/O
Port 11.
2-bit I/O port.
Input/output can be specified in 1-bit units.
Use of an on-chip pull-up resistor can be specified by a
software setting.
P120
P121
I/O
Port 12.
Input
1-bit I/O port and 4-bit input port.
Input port
X1
For only P120, use of an on-chip pull-up resistor can be
P122
INTP0/EXLVI
X2/EXCLK
specified by a software setting.
P123
XT1
P124
XT2
P130
Output
Port 13.
Output port
−
1-bit output port.
P140
I/O
Port 14.
Input port
4-bit I/O port.
P142
SCK20/SCL20
Input of P142 and P143 can be set to TTL input buffer.
P143
SI20/RxD2/SDA20
Output of P142 to P144 can be set to the N-ch open-drain
P144
PCLBUZ0/INTP6
SO20/TxD2
output (VDD tolerance).
Input/output can be specified in 1-bit units.
Use of an on-chip pull-up resistor can be specified by a
software setting.
P150 to P153
I/O
Port 15.
Digital input
4-bit I/O port.
port
ANI8 to ANI11
Input/output can be specified in 1-bit units.
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(2) Non-port functions (1/3): 78K0R/KF3-L
Function Name
ANI0 to ANI7
I/O
Input
Function
After Reset
Alternate Function
Digital input P20 to P27
A/D converter analog input
ANI8 to ANI11
port
P150 to P153
EXLVI
Input
Potential input for external low-voltage detection
Input port
P120/INTP0
INTP0
Input
External interrupt request input for which the valid edge (rising
Input port
P120/EXLVI
edge, falling edge, or both rising and falling edges) can be
INTP1
Note
P50/SCK40
specified
Note
INTP2
P51/SI40
INTP3
P30/RTC1HZ
INTP4
P31/TI03/TO03
INTP5
P16/TI01/TO01
INTP6
P140/PCLBUZ0
INTP7
P55/PCLBUZ1/
SO41
INTP8 to
/RxD4
Note
Note
P74/KR4 to P77/KR7
INTP11
KR0 to KR3
Input
Key interrupt input
Input port
P70 to P73
P74/INTP8 to
KR4 to KR7
P77/INTP11
PCLBUZ0
Output
Clock output/buzzer output
Input port
PCLBUZ1
P140/INTP6
P55/INTP7
−
REGC
Connecting regulator output (2.4 V) stabilization capacitance for
−
−
internal operation.
Connect to VSS via a capacitor (0.47 to 1 μF: target).
RTCDIV
Output
Real-time counter clock (32 kHz divided frequency) output
Input port
P15/RTCCL
RTCCL
Output
Real-time counter clock (32 kHz original oscillation) output
Input port
P15/RTCDIV
RTC1HZ
Output
Real-time counter correction clock (1 Hz) output
Input port
P30/INTP3
RESET
Input
System reset input
RxD0
Input
Serial data input to UART0
Input port
P11/SI00
RxD1
Input
Serial data input to UART1
Input port
P03/SI10/SDA10
RxD2
Input
Serial data input to UART2
Input port
P143/SI20/SDA20
RxD3
Input
Serial data input to UART3
Input port
P14
RxD4
Input
Serial data input to UART4
Input port
P51/INTP2/SI40
SCK00
I/O
Clock input/output for CSI00, CSI01, CSI10, CSI20, CSI40, and
Input port
P10
Note
−
CSI41
SCK01
−
P43
SCK10
P04/SCL10
SCK20
P142/SCL20
SCK40
P50/INTP1
P53/TI00
SCK41
SCL0
SCL10
I/O
I/O
2
Clock input/output for I C
2
Clock input/output for simplified I C
SCL20
Note
Note
Input port
P60
Input port
P04/SCK10
P142/SCK20
SCK40, SCK41, SI40, SI41, SO40, SO41, TxD4, RxD4 are only mounted in the μ PD78F1027 and 78F1028.
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(2) Non-port functions (2/3): 78K0R/KF3-L
Function Name
SDA0
SDA10
I/O
I/O
I/O
Function
2
Serial data I/O for I C
2
Serial data I/O for simplified I C
After Reset
Input port
P61
Input port
P03/SI10/RxD1
SDA20
P143/SI20/RxD2
Input
SI00
Alternate Function
Serial data input to CSI00, CSI01, CSI10, CSI20, CSI40, and
Input port
CSi41
SI01
P11/RxD0
P44
SI10
P03/RxD1/SDA10
SI20
P143/RxD2/SDA20
SI40
Note
P51/RxD4
SI41
Note
P54/TI07/TO07
SO00
Output
SO01
Serial data output from CSI00, CSI01, CSI10, CSI20, CSI40, and Input port
CSI41
Note
/INTP2
P12/TxD0
P45
SO10
P02/TxD1
SO20
P144/TxD2
SO40
P52/TO00/TxD4
SO41
P55/PCLBUZ1/INTP7
TI00
Input
External count clock input to 16-bit timer 00
Input port
P53/SCK41
Note
Note
TI01
External count clock input to 16-bit timer 01
P16/TO01/INTP5
TI02
External count clock input to 16-bit timer 02
P17/TO02
TI03
External count clock input to 16-bit timer 03
P31/TO03/INTP4
TI04
External count clock input to 16-bit timer 04
P42/TO04
TI05
External count clock input to 16-bit timer 05
P05/TO05
TI06
External count clock input to 16-bit timer 06
P06/TO06
TI07
External count clock input to 16-bit timer 07
P54/TO07/SI41
TI10
External count clock input to 16-bit timer 10
P64/TO10
TI11
External count clock input to 16-bit timer 11
P65/TO11
TI12
External count clock input to 16-bit timer 12
P66/TO12
TI13
External count clock input to 16-bit timer 13
P67/TO13
TO00
Output
16-bit timer 00 output
Input port
P52/SO40
Note
Note
/TxD4
TO01
16-bit timer 01 output
P16/TI01/INTP5
TO02
16-bit timer 02 output
P17/TI02
TO03
16-bit timer 03 output
P31/TI03/INTP4
TO04
16-bit timer 04 output
P42/TI04
TO05
16-bit timer 05 output
P05/TI05
TO06
16-bit timer 06 output
P06/TI06
TO07
16-bit timer 07 output
P54/TI07/SI41
TO10
16-bit timer 10 output
P64/TI10
TO11
16-bit timer 11 output
P65/TI11
TO12
16-bit timer 12 output
P66/TI12
TO13
16-bit timer 13 output
P67/TI13
Note
Note
Note
SCK41, SI40, SI41, SO40, SO41, TxD4, and RxD4 are only mounted in the μ PD78F1027 and 78F1028.
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(2) Non-port functions (3/3) : 78K0R/KF3-L
Function Name
I/O
Output
TxD0
Function
Serial data output from UART0
After Reset
Input port
Alternate Function
P12/SO00
TxD1
Serial data output from UART1
P02/SO10
TxD2
Serial data output from UART2
P144/SO20
TxD3
Serial data output from UART3
P13
Serial data output from UART4
P52/SO40
TxD4
Note
X1
−
X2
−
EXCLK
Resonator connection for main system clock
/TO00
Input port
P121
Input port
P122/EXCLK
Input
External clock input for main system clock
Input port
P122/X2
XT1
−
Resonator connection for subsystem clock
Input port
P123
XT2
−
Input port
P124
VDD
−
Positive power supply (P121 to P124 and other than ports
Note
−
−
−
−
−
−
−
−
−
−
−
−
−
−
(excluding RESET and FLMD0 pins))
−
EVDD0
Positive power supply for ports (other than P20 to P27, P121 to
P124, P150 to P153), and RESET and FLMD0 pins
−
AVREF
• A/D converter reference voltage input
• Positive power supply for P20 to P27, P150 to P153, and A/D
converter
−
VSS
Ground potential (P121 to P124 and other than ports (excluding
RESET and FLMD0 pins))
−
EVSS0
Ground potential for ports (other than P20 to P27, P121 to P124,
and P150 to P153), and RESET and FLMD0 pins
−
AVSS
Ground potential for A/D converter, P20 to P27, and P150 to
P153. Use this pin with the same potential as EVSS0 and VSS.
−
FLMD0
Flash memory programming mode setting
TOOL0
I/O
Data I/O for flash memory programmer/debugger
Input port
P40
TOOL1
Output
Clock output for debugger
Input port
P41
Note
SO40 and RxD4 are only mounted in the μ PD78F1027 and 78F1028.
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3.1.2 78K0R/KG3-L
(1) Port functions (1/3): 78K0R/KG3-L
Function Name
I/O
I/O
P00
Function
Port 0.
After Reset
Input port
7-bit I/O port.
P01
TI00
TO00
Input of P03 and P04 can be set to TTL input buffer.
P02
Alternate Function
SO10/TxD1
Output of P02 to P04 can be set to N-ch open-drain output
P03
(VDD tolerance).
SI10/RxD1/SDA10
P04
Input/output can be specified in 1-bit units.
SCK10/SCL10
Use of an on-chip pull-up resistor can be specified by a
P05, P06
−
software setting.
I/O
P10
Port 1.
Input port
8-bit I/O port.
P11
SI00/RxD0
Input of P10 and P11 can be set to TTL input buffer.
P12
SCK00
SO00/TxD0
Output of P10 and P12 can be set to N-ch open-drain output
P13
TxD3
(VDD tolerance).
P14
Input/output can be specified in 1-bit units.
RxD3
P15
Use of an on-chip pull-up resistor can be specified by a
RTCDIV/RTCCL
software setting.
P16
TI01/TO01/INTP5
P17
TI02/TO02
P20 to P27
I/O
Port 2.
Digital input
8-bit I/O port.
port
ANI0 to ANI7
Input/output can be specified in 1-bit units.
I/O
P30
Port 3.
Input port
2-bit I/O port.
P31
RTC1HZ/INTP3
TI03/TO03/INTP4
Input/output can be specified in 1-bit units.
Use of an on-chip pull-up resistor can be specified by a
software setting.
P40
Note
P41
P42
P43
I/O
Port 4.
8-bit I/O port.
Input/output can be specified in 1-bit units.
Use of an on-chip pull-up resistor can be specified by a
software setting.
Input port
TOOL0
TOOL1
TI04/TO04
SCK01
P44
SI01
P45
SO01
P46
INTP1/TI05/TO05
P47
INTP2
Note
If on-chip debugging is enabled by using an option byte, be sure to pull up the P40/TOOL0 pin externally (see
Caution in 3.2.5 P40 to P47 (port 4)).
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(1) Port functions (2/3): 78K0R/KG3-L
Function Name
I/O
I/O
P50
Function
Port 5.
After Reset
Input port
8-bit I/O port.
P51
Note
Note
SO40/TxD4
Use of an on-chip pull-up resistor can be specified by a
P53
SCK40
SI40/RxD4
Input/output can be specified in 1-bit units.
P52
Alternate Function
SCK41
software setting.
Note
Note
Note
P54
SI41
P55
SO41
Note
−
P56
−
P57
P60
I/O
Port 6.
Input port
8-bit I/O port.
P61
SCL0
SDA0
Output of P60 to P63 can be set to N-ch open-drain output
P62, P63
−
(6 V tolerance).
P64 to P67
Input/output can be specified in 1-bit units.
TI10/TO10 to
For only P64 to P67, use of an on-chip pull-up resistor can be
TI13/TO13
specified by a software setting.
P70 to P73
I/O
Port 7.
Input port
8-bit I/O port.
P74 to P77
KR0 to KR3
KR4/INTP8 to
Input/output can be specified in 1-bit units.
KR7/INTP11
Use of an on-chip pull-up resistor can be specified by a
software setting.
P80 to P87
I/O
Port 8.
Input port
−
Input port
−
Input port
−
8-bit I/O port.
Input/output can be specified in 1-bit units.
Use of an on-chip pull-up resistor can be specified by a
software setting.
P91
I/O
Port 9.
1-bit I/O port.
Input/output can be specified in 1-bit units.
Use of an on-chip pull-up resistor can be specified by a
software setting.
P110, P111
I/O
Port 11.
2-bit I/O port.
Input/output can be specified in 1-bit units.
Use of an on-chip pull-up resistor can be specified by a
software setting.
P120
P121
I/O
Port 12.
Input
1-bit I/O port and 4-bit input port.
Input port
X1
For only P120, use of an on-chip pull-up resistor can be
P122
INTP0/EXLVI
X2/EXCLK
specified by a software setting.
P123
XT1
P124
XT2
P130
Output
Port 13.
Output port
−
1-bit output port and 1-bit I/O port.
P131
I/O
For only P131, use of an on-chip pull-up resistor can be
Input port
TI06/TO06
specified by a software setting.
Note
SCK40, SCK41, SI40, SI41, SO40, SO41, TxD4, RxD4 are only mounted in the μ PD78F1027 and 78F1028.
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Function Name
P140
I/O
I/O
Function
Port 14.
After Reset
Input port
6-bit I/O port.
P141
PCLBUZ0/INTP6
PCLBUZ1/INTP7
Input of P142 and P143 can be set to TTL input buffer.
P142
Alternate Function
SCK20/SCL20
Output of P142 to P144 can be set to the N-ch open-drain
P143
output (VDD tolerance).
SI20/RxD2/SDA20
P144
Input/output can be specified in 1-bit units.
SO20/TxD2
Use of an on-chip pull-up resistor can be specified by a
P145
P150 to P157
TI07/TO07
software setting.
I/O
Port 15.
Digital input
8-bit I/O port.
port
ANI8 to ANI15
Input/output can be specified in 1-bit units.
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(2) Non-port functions (1/3): 78K0R/KG3-L
Function Name
ANI0 to ANI7
I/O
Input
Function
After Reset
Alternate Function
Digital input P20 to P27
A/D converter analog input
ANI8 to ANI15
port
P150 to P157
EXLVI
Input
Potential input for external low-voltage detection
Input port
P120/INTP0
INTP0
Input
External interrupt request input for which the valid edge (rising
Input port
P120/EXLVI
edge, falling edge, or both rising and falling edges) can be
INTP1
P46/TI05/TO05
specified
INTP2
P47
INTP3
P30/RTC1HZ
INTP4
P31/TI03/TO03
INTP5
P16/TI01/TO01
INTP6
P140/PCLBUZ0
INTP7
P141/PCLBUZ1
INTP8 to
P74/KR4 to P77/KR7
INTP11
KR0 to KR3
Input
Key interrupt input
Input port
P70 to P73
P74/INTP8 to
KR4 to KR7
P77/INTP11
PCLBUZ0
Output
Clock output/buzzer output
Input port
PCLBUZ1
P140/INTP6
P141/INTP7
−
REGC
Connecting regulator output (2.4 V) stabilization capacitance for
−
−
internal operation.
Connect to VSS via a capacitor (0.47 to 1 μF: target).
RTCDIV
Output
Real-time counter clock (32 kHz divided frequency) output
Input port
P15/RTCCL
RTCCL
Output
Real-time counter clock (32 kHz original oscillation) output
Input port
P15/RTCDIV
RTC1HZ
Output
Real-time counter correction clock (1 Hz) output
Input port
P30/INTP3
RESET
Input
System reset input
RxD0
Input
Serial data input to UART0
Input port
P11/SI00
RxD1
Input
Serial data input to UART1
Input port
P03/SI10/SDA10
RxD2
Input
Serial data input to UART2
Input port
P143/SI20/SDA20
RxD3
Input
Serial data input to UART3
Input port
P14
RxD4
Input
Serial data input to UART4
Input port
P51/SI40
SCK00
I/O
Clock input/output for CSI00, CSI01, CSI10, CSI20, CSI40, and
Input port
P10
Note
−
CSI41
SCK01
−
P43
SCK10
P04/SCL10
SCK20
P142/SCL20
SCK40
Note
P50
SCK41
Note
P53
SCL0
SCL10
SCL20
Note
Note
I/O
I/O
I/O
2
Clock input/output for I C
Input port
P60
2
Input port
P04/SCK10
2
Input port
P142/SCK20
Clock input/output for simplified I C
Clock input/output for simplified I C
SCK40, SCK41, SI40, RxD4 are only mounted in the μ PD78F1029 and 78F1030.
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Function Name
SDA0
SDA10
I/O
I/O
I/O
Function
2
Serial data I/O for I C
After Reset
Alternate Function
Input port
P61
2
Input port
P03/SI10/RxD1
2
Serial data I/O for simplified I C
SDA20
I/O
Serial data I/O for simplified I C
Input port
P143/SI20/RxD2
SI00
Input
Serial data input to CSI00, CSI01, CSI10, CSI20, CSI40, and
Input port
P11/RxD0
CSI41
SI01
P44
SI10
P03/RxD1/SDA10
SI20
P143/RxD2/SDA20
SI40
Note
P51/RxD4
SI41
Note
P54
SO00
Output
SO01
Serial data output from CSI00, CSI01, CSI10, CSI20, CSI40, and Input port
CSI41
Note
P12/TxD0
P45
SO10
P02/TxD1
SO20
P144/TxD2
SO40
Note
P52/TxD4
SO41
Note
P55
TI00
Input
External count clock input to 16-bit timer 00
Input port
Note
P00
TI01
External count clock input to 16-bit timer 01
P16/TO01/INTP5
TI02
External count clock input to 16-bit timer 02
P17/TO02
TI03
External count clock input to 16-bit timer 03
P31/TO03/INTP4
TI04
External count clock input to 16-bit timer 04
P42/TO04
TI05
External count clock input to 16-bit timer 05
P46/INTP1/TO05
TI06
External count clock input to 16-bit timer 06
P131/TO06
TI07
External count clock input to 16-bit timer 07
P145/TO07
TI10
External count clock input to 16-bit timer 10
P64/TO10
TI11
External count clock input to 16-bit timer 11
P65/TO11
TI12
External count clock input to 16-bit timer 12
P66/TO12
TI13
External count clock input to 16-bit timer 13
P67/TO13
TO00
Output
16-bit timer 00 output
Input port
P01
TO01
16-bit timer 01 output
P16/TI01/INTP5
TO02
16-bit timer 02 output
P17/TI02
TO03
16-bit timer 03 output
P31/TI03/INTP4
TO04
16-bit timer 04 output
P42/TI04
TO05
16-bit timer 05 output
P46/INTP1/TI05
TO06
16-bit timer 06 output
P131/TI06
TO07
16-bit timer 07 output
P145/TI07
TO10
16-bit timer 10 output
P64/TI10
TO11
16-bit timer 11 output
P65/TI11
TO12
16-bit timer 12 output
P66/TI12
TO13
16-bit timer 13 output
P67/TI13
Note
SI40, SI41, SO40, SO41, TxD4, and RxD4 are only mounted in the μ PD78F1029 and 78F1030.
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Function Name
I/O
Output
TxD0
Function
Serial data output from UART0
After Reset
Input port
Alternate Function
P12/SO00
TxD1
Serial data output from UART1
P02/SO10
TxD2
Serial data output from UART2
P144/SO20
TxD3
Serial data output from UART3
P13
Serial data output from UART4
P52/SO40
TxD4
Note
X1
−
X2
−
EXCLK
Resonator connection for main system clock
Input port
P121
Input port
P122/EXCLK
Input
External clock input for main system clock
Input port
P122/X2
XT1
−
Resonator connection for subsystem clock
Input port
P123
XT2
−
Input port
P124
VDD
−
Positive power supply (P121 to P124 and other than ports
Note
−
−
−
−
−
−
−
−
−
−
−
−
−
−
(excluding RESET and FLMD0 pins))
−
EVDD0, EVDD1
Positive power supply for ports (other than P20 to P27, P121 to
P124, P150 to P157), and RESET and FLMD0 pins
−
AVREF
• A/D converter reference voltage input
• Positive power supply for P20 to P27, P150 to P157, and A/D
converter
−
VSS
Ground potential (P121 to P124 and other than ports (excluding
RESET and FLMD0 pins))
−
EVSS0, EVSS1
Ground potential for ports (other than P20 to P27, P121 to P124,
and P150 to P157), and RESET and FLMD0 pins
−
AVSS
Ground potential for A/D converter, P20 to P27, and P150 to
P157. Use this pin with the same potential as EVSS0, EVSS1, and
VSS.
−
FLMD0
Flash memory programming mode setting
TOOL0
I/O
Data I/O for flash memory programmer/debugger
Input port
P40
TOOL1
Output
Clock output for debugger
Input port
P41
Note
SO40 and TxD4 are only mounted in the μ PD78F1029 and 78F1030.
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3.2 Description of Pin Functions
Remark
The pins mounted depend on the product. See 1.4 Pin Configuration (Top View) and 3.1 Pin Function
List.
3.2.1 P00 to P06 (port 0)
P00 to P06 function as an I/O port. These pins also function as timer I/O, serial interface data I/O, and clock I/O.
Input to the P03 and P04 pins can be specified through a normal input buffer or a TTL input buffer in 1-bit units, using
port input mode register 0 (PIM0).
Output from the P02 to P04 pins can be specified as normal CMOS output or N-ch open-drain output (VDD tolerance) in
1-bit units, using port output mode register 0 (POM0).
78K0R/KF3-L
78K0R/KG3-L
(μ PD78F10xx: xx = 10, 11, 12,
(μ PD78F10xx: xx = 13, 14,
27, 28)
29, 30)
P00/TI00
−
Note 1
P01/TO00
−
Note 1
√
P02/SO10/TxD1
√
√
P03/SI10/RxD1/SDA10
√
√
P04/SCK10/SCL10
√
√
P05/TI05/TO05
√
P05
Note 2
P06/TI06/TO06
√
P06
Note 2
√
Notes 1. TI00 and TO00 are shared with P53 and P52, respectively, in the 78K0R/KF3-L.
2. TI05/TO05 and TI06/TO06 are shared with P46 and P131, respectively, in the 78K0R/KG3-L.
The following operation modes can be specified in 1-bit units.
(1) Port mode
P00 to P06 function as an I/O port. P00 to P06 can be set to input or output port in 1-bit units using port mode
register 0 (PM0). Use of an on-chip pull-up resistor can be specified by pull-up resistor option register 0 (PU0).
(2) Control mode
P00 to P04 function as timer I/O, serial interface data I/O, and clock I/O.
(a) TI00, TI05, and TI06
There are the pins for inputting an external count clock/capture trigger to 16-bit timers 00, 05, and 06.
(b) TO00, TO05, and TO06
These are the timer output pins of 16-bit timers 00, 05, and 06.
(c) SI10
This is a serial data input pin of serial interface CSI10.
(d) SO10
This is a serial data output pin of serial interface CSI10.
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(e) SCK10
This is a serial clock I/O pin of serial interface CSI10.
(f) TxD1
This is a serial data output pin of serial interface UART1.
(g) RxD1
This is a serial data input pin of serial interface UART1.
(h) SDA10
This is a serial data I/O pin of serial interface for simplified I2C.
(i)
SCL10
This is a serial clock I/O pin of serial interface for simplified I2C.
Caution To use P02/SO10/TxD1
and P04/SCK10/SCL10
as
general-purpose ports, set serial
communication operation setting register 02 (SCR02) to the default status (0087H). In addition,
clear port output mode register 0 (POM0) to 00H.
3.2.2 P10 to P17 (port 1)
P10 to P17 function as an I/O port. These pins also function as external interrupt request input, serial interface data I/O,
clock I/O, timer I/O, and real-time counter clock output.
Input to the P10 and P11 pins can be specified through a normal input buffer or a TTL input buffer in 1-bit units, using
port input mode register 1 (PIM1).
Output from the P10 and P12 pins can be specified as normal CMOS output or N-ch open-drain output (VDD tolerance)
in 1-bit units, using port output mode register 1 (POM1).
78K0R/KF3-L
78K0R/KG3-L
(μ PD78F10xx: xx = 10, 11, 12,
(μ PD78F10xx: xx = 13, 14,
27, 28)
29, 30)
P10/SCK00
√
√
P11/SI00/RxD0
√
√
P12/SO00/TxD0
√
√
P13/TxD3
√
√
P14/RxD3
√
√
P15/RTCDIV/RTCCL
√
√
P16/TI01/TO01/INTP5
√
√
P17/TI02/TO02
√
√
The following operation modes can be specified in 1-bit units.
(1) Port mode
P10 to P17 function as an I/O port. P10 to P17 can be set to input or output port in 1-bit units using port mode
register 1 (PM1). Use of an on-chip pull-up resistor can be specified by pull-up resistor option register 1 (PU1).
(2) Control mode
P10 to P17 function as external interrupt request input, serial interface data I/O, clock I/O, timer I/O, and real-time
counter clock output.
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(a) SI00
This is a serial data input pin of serial interface CSI00.
(b) SO00
This is a serial data output pin of serial interface CSI00.
(c) SCK00
This is a serial clock I/O pin of serial interface CSI00.
(d) RxD0, RxD3
These are the serial data input pins of serial interface UART0 and UART3.
(e) TxD0, TxD3
These are the serial data output pins of serial interface UART0 and UART3.
(f)
TI01, TI02
These are the pins for inputting an external count clock/capture trigger to 16-bit timers 01 and 02.
(g) TO01, TO02
These are the timer output pins of 16-bit timers 01 and 02.
(h) INTP5
This is an external interrupt request input pin for which the valid edge (rising edge, falling edge, or both rising and
falling edges) can be specified.
(i)
RTCDIV
This is a real-time counter clock (32 kHz, divided) output pin.
(j)
RTCCL
This is a real-time counter clock (32 kHz, original oscillation) output pin.
Cautions 1. To use P10/SCK00 and P12/SO00/TxD0 as general-purpose ports, set serial communication
operation setting register 00 (SCR00) to the default status (0087H).
2. Do not enable outputting RTCCL and RTCDIV at the same time.
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3.2.3 P20 to P27 (port 2)
P20 to P27 function as an I/O port. These pins also function as A/D converter analog input.
78K0R/KF3-L
78K0R/KG3-L
(μ PD78F10xx: xx = 10, 11, 12,
(μ PD78F10xx: xx = 13, 14,
27, 28)
29, 30)
P20/ANI0
√
√
P21/ANI1
√
√
P22/ANI2
√
√
P23/ANI3
√
√
P24/ANI4
√
√
P25/ANI5
√
√
P26/ANI6
√
√
P27/ANI7
√
√
The following operation modes can be specified in 1-bit units.
(1) Port mode
P20 to P27 function as an I/O port. P20 to P27 can be set to input or output port in 1-bit units using port mode
register 2 (PM2).
(2) Control mode
P20 to P27 function as the A/D converter analog input pins (ANI0 to ANI7). When using these pins as the analog
input pins, see 13.6 (5) ANI0/P20 to ANI7/P27 and ANI8/P150 to ANI15/P157.
Caution ANI0/P20 to ANI7/P27 are set in the digital input (general-purpose port) mode after release of reset.
3.2.4 P30, P31 (port 3)
P30 and P31 function as an I/O port. These pins also function as external interrupt request input, timer I/O, and realtime counter correction clock output.
78K0R/KF3-L
78K0R/KG3-L
(μ PD78F10xx: xx = 10, 11, 12,
(μ PD78F10xx: xx = 13, 14,
27, 28)
29, 30)
P30/RTC1HZ/INTP3
√
√
P31/TI03/TO03/INTP4
√
√
The following operation modes can be specified in 1-bit units.
(1) Port mode
P30 and P31 function as an I/O port. P30 and P31 can be set to input or output port in 1-bit units using port mode
register 3 (PM3). Use of an on-chip pull-up resistor can be specified by pull-up resistor option register 3 (PU3).
(2) Control mode
P30 and P31 function as external interrupt request input, timer I/O, and real-time counter correction clock output.
(a) INTP3, INTP4
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These are the external interrupt request input pins for which the valid edge (rising edge, falling edge, or both
rising and falling edges) can be specified.
(b) TI03
This is a pin for inputting an external count clock/capture trigger to 16-bit timer 03.
(c) TO03
This is a timer output pin from 16-bit timer 03.
(d) RTC1HZ
This is a real-time counter correction clock (1 Hz) output pin.
3.2.5 P40 to P47 (port 4)
P40 to P47 function as an I/O port. These pins also function as external interrupt request input, serial interface data I/O,
clock I/O, data I/O for a flash memory programmer/debugger, clock output, and timer I/O.
78K0R/KF3-L
78K0R/KG3-L
(μ PD78F10xx: xx = 10, 11, 12,
(μ PD78F10xx: xx = 13, 14,
27, 28)
29, 30)
P40/TOOL0
√
√
P41/TOOL1
√
√
P42/TI04/TO04
√
√
P43/SCK01
√
√
P44/SI01
√
√
P45/SO01
√
√
P46/INTP1/TI05/TO05
P47/INTP2
P46
Note 1
√
P47
Note 2
√
Notes 1. INTP1 and TI05/TO05 are shared with P50 and P05, respectively, in the 78K0R/KF3-L.
2. INTP2 is shared with P51, in the 78K0R/KF3-L.
The following operation modes can be specified in 1-bit units.
(1) Port mode
P40 to P47 function as an I/O port. P40 to P47 can be set to input or output port in 1-bit units using port mode
register 4 (PM4). Use of an on-chip pull-up resistor can be specified by pull-up resistor option register 4 (PU4).
Be sure to connect an external pull-up resistor to P40 when on-chip debugging is enabled (by using an option byte).
(2) Control mode
P40 to P47 function as serial interface data I/O, clock I/O, external interrupt request input, data I/O for a flash memory
programmer/debugger, clock output, and timer I/O.
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(a) INTP1, INTP2
These are the external interrupt request input pins for which the valid edge (rising edge, falling edge, or both
rising and falling edges) can be specified.
(b) TOOL0
This is a data I/O pin for a flash memory programmer/debugger.
Be sure to pull up this pin externally when on-chip debugging is enabled (pulling it down is prohibited).
(c) TOOL1
This is a clock output pin for a debugger.
When the on-chip debug function is used, the P41/TOOL1 pin can be used as follows by the mode setting on the
debugger.
1-line mode: can be used as a port (P41).
2-line mode: used as a TOOL1 pin and cannot be used as a port (P41).
(d) TI04, TI05
These are the pins for inputting an external count clock/capture trigger to 16-bit timers 04 and 05.
(e) TO04, TO05
These are the timer output pins from 16-bit timers 04 and 05.
(f) SCK01
This is a serial clock I/O pin of serial interface CSI01.
(g) SI01
This is a serial data input pin of serial interface CSI01.
(h) SO01
This is a serial data output pin of serial interface CSI01.
Caution The function of the P40/TOOL0 pin varies as described in (a) to (c) below.
In the case of (b) or (c), make the specified connection.
(a) In normal operation mode and when on-chip debugging is disabled (OCDENSET = 0) by an
option byte (000C3H)
=> Use this pin as a port pin (P40).
(b) In normal operation mode and when on-chip debugging is enabled (OCDENSET = 1) by an
option byte (000C3H)
=> Connect this pin to EVDD0 or EVDD1 via an external resistor, and always input a high level
to the pin before reset release.
(c) When on-chip debug function is used, or in write mode of flash memory programmer
=> Use this pin as TOOL0.
Directly connect this pin to the on-chip debug emulator or a flash memory programmer,
or pull it up by connecting it to EVDD0 or EVDD1 via an external resistor.
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3.2.6 P50 to P57 (port 5)
P50 to P57 function as an I/O port. These pins also function as serial interface data I/O, clock I/O, external interrupt
request input, timer I/O, and clock/buzzer output.
<In case of the μ PD78F1010, 78F1011, 78F1012, 78F1013, 78F1014>
78K0R/KF3-L
78K0R/KG3-L
(μ PD78F10xx: xx = 10, 11, 12)
(μ PD78F10xx: xx = 13, 14)
P50/INTP1
√
P50
Note
P51/INTP2
√
P51
Note
P52/TO00
√
P52
Note
P53/TI00
√
P53
Note
P54/TI07/TO07
√
P54
Note
P55/PCLBUZ1/INTP7
√
P55
Note
P56
−
√
P57
−
√
Note
The following pins are shared in the 78K0R/KG3-L.
• P46/INTP1
• P47/INTP2
• P01/TO00
• P00/TI00
• P145/TI07/TO07
• P141/PCLBUZ1/INTP7
<In case of the μ PD78F1027, 78F1028, 78F1029, 78F1030>
78K0R/KF3-L
78K0R/KG3-L
(μ PD78F10xx: xx = 27, 28)
(μ PD78F10xx: xx = 29, 30)
P50/SCK40/INTP1
√
P50/SCK40
P51/SI40/RxD4/INTP2
√
P51/SI40/RxD4
P52/SO40/TO00/TxD4
√
P52/SO40/TxD4
P53/SCK41/TI00
√
P53/SCK41
P54/SI41/TI07/TO07
√
P54/SI41
P55/PCLBUZ1/SO41/
√
P55/SO41
Note
Note
Note
Note
Note
Note
INTP7
P56
−
√
P57
−
√
Note
The following pins are shared in the 78K0R/KG3-L.
• P46/INTP1
• P47/INTP2
• P01/TO00
• P00/TI00
• P145/TI07/TO07
• P141/PCLBUZ1/INTP7
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The following operation modes can be specified in 1-bit units.
(1) Port mode
P50 to P57 function as an I/O port. P50 to P57 can be set to input or output port in 1-bit units using port mode
register 5 (PM5). Use of an on-chip pull-up resistor can be specified by pull-up resistor option register 5 (PU5).
(2) Control mode
P50 to P57 function as serial interface data I/O, clock I/O, external interrupt request input, timer I/O, and clock/buzzer
output.
(a) INTP1, INTP2, INTP7
These are the external interrupt request input pins for which the valid edge (rising edge, falling edge, or both
rising and falling edges) can be specified.
(b) TI00, TI07
These are the pins for inputting an external count clock/capture trigger to 16-bit timers 00 and 07.
(c) TO00, TO07
These are the timer output pins of 16-bit timers 00 and 07.
(d) PCLBUZ1
This is a clock/buzzer output pin.
(e) SI40, SI41
These are the serial data input pins of serial interface CSI40 and CSI41.
(f) SO40, SO41
These are the serial data output pin of serial interface CSI40 and CSI41.
(g) SCK40, SCK41
These are the serial clock I/O pins of serial interface CSI40 and CSI41.
(h) RxD4
This is a serial data input pin of serial interface UART4.
(i)
TxD4
This is a serial data output pins of serial interface UART4.
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3.2.7 P60 to P67 (port 6)
P60 to P67 function as an I/O port. These pins also function as serial interface data I/O, clock I/O, and timer I/O.
78K0R/KF3-L
78K0R/KG3-L
(μ PD78F10xx: xx = 10, 11, 12,
(μ PD78F10xx: xx = 13, 14,
27, 28)
29, 30)
P60/SCL0
√
√
P61/SDA0
√
√
P62
√
√
P63
√
√
P64/TI10/TO10
√
√
P65/TI11/TO11
√
√
P66/TI12/TO12
√
√
P67/TI13/TO13
√
√
The following operation modes can be specified in 1-bit units.
(1) Port mode
P60 to P67 function as an I/O port. P60 to P67 can be set to input port or output port in 1-bit units using port mode
register 6 (PM6). Only for P64 to P67, use of an on-chip pull-up resistor can be specified by pull-up resistor option
register 6 (PU6).
Output of P60 to P63 is N-ch open-drain output (6 V tolerance).
(2) Control mode
P60 and P61 and P64 to P67 function as serial interface data I/O, clock I/O, and timer I/O.
(a) SDA0
This is a serial data I/O pin of serial interface IICA.
(b) SCL0
This is a serial clock I/O pin of serial interface IICA.
(c) TI10 to TI13
These are the pins for inputting an external count clock/capture trigger to 16-bit timers 10 to 13.
(d) TO10 to TO13
These are the timer output pins of 16-bit timers 10 to 13.
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3.2.8 P70 to P77 (port 7)
P70 to P77 function as an I/O port. These pins also function as key interrupt input and external interrupt request input.
78K0R/KF3-L
78K0R/KG3-L
(μ PD78F10xx: xx = 10, 11, 12,
(μ PD78F10xx: xx = 13, 14,
27, 28)
29, 30)
P70/KR0
√
√
P71/KR1
√
√
P72/KR2
√
√
P73/KR3
√
√
P74/KR4/INTP8
√
√
P75/KR5/INTP9
√
√
P76/KR6/INTP10
√
√
P77/KR7/INTP11
√
√
The following operation modes can be specified in 1-bit units.
(1) Port mode
P70 to P77 function as an I/O port. P70 to P77 can be set to input or output port in 1-bit units using port mode
register 7 (PM7). Use of an on-chip pull-up resistor can be specified by pull-up resistor option register 7 (PU7).
(2) Control mode
P70 to P77 function as key interrupt input, and external interrupt request input.
(a) KR0 to KR7
These are the key interrupt input pins.
(b) INTP8 to INTP11
These are the external interrupt request input pins for which the valid edge (rising edge, falling edge, or both
rising and falling edges) can be specified.
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3.2.9 P80 to P87 (port 8)
P80 to P87 function as an I/O port.
P80 to P87 can be set to input or output port in 1-bit units using port mode register 8 (PM8). Use of an on-chip pull-up
resistor can be specified by pull-up resistor option register 8 (PU8).
78K0R/KF3-L
78K0R/KG3-L
(μ PD78F10xx: xx = 10, 11, 12,
(μ PD78F10xx: xx = 13, 14,
27, 28)
29, 30)
P80
−
√
P81
−
√
P82
−
√
P83
−
√
P84
−
√
P85
−
√
P86
−
√
P87
−
√
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3.2.10 P90, P91 (port 9)
P90 and P91 function as an I/O port.
P90 and P91 can be set to input or output port in 1-bit units using port mode register 9 (PM9). Use of an on-chip pullup resistor can be specified by pull-up resistor option register 9 (PU9).
78K0R/KF3-L
78K0R/KG3-L
(μ PD78F10xx: xx = 10, 11, 12,
(μ PD78F10xx: xx = 13, 14,
27, 28)
29, 30)
P90
√
−
P91
√
√
3.2.11 P110, P111 (port 11)
P110 and P111 function as an I/O port.
P110 and P111 can be set to input or output port in 1-bit units using port mode register 11 (PM11). Use of an on-chip
pull-up resistor can be specified by pull-up resistor option register 11 (PU11).
78K0R/KF3-L
78K0R/KG3-L
(μ PD78F10xx: xx = 10, 11, 12,
(μ PD78F10xx: xx = 13, 14,
27, 28)
29, 30)
P110
√
√
P111
√
√
3.2.12 P120 to P124 (port 12)
P120 function as a 1-bit I/O port. P121 to P124 functions as a 4-bit input port. These pins also function as external
interrupt request input, potential input for external low-voltage detection, connecting resonator for main system clock,
connecting resonator for subsystem clock, and external clock input for main system clock.
78K0R/KF3-L
78K0R/KG3-L
(μ PD78F10xx: xx = 10, 11, 12,
(μ PD78F10xx: xx = 13, 14,
27, 28)
29, 30)
P120/INTP0/EXLVI
√
√
P121/X1
√
√
P122/X2/EXCLK
√
√
P123/XT1
√
√
P124/XT2
√
√
The following operation modes can be specified in 1-bit units.
(1) Port mode
P120 functions as a 1-bit I/O port. P120 can be set to input or output port using port mode register 12 (PM12). Use
of an on-chip pull-up resistor can be specified by pull-up resistor option register 12 (PU12).
P121 to P124 functions as a 4-bit input port.
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(2) Control mode
P120 to P124 function as external interrupt request input, potential input for external low-voltage detection, connecting
resonator for main system clock, connecting resonator for subsystem clock, and external clock input for main system
clock.
(a) INTP0
This is an external interrupt request input pin for which the valid edge (rising edge, falling edge, or both rising and
falling edges) can be specified.
(b) EXLVI
This is a potential input pin for external low-voltage detection.
(c) X1, X2
These are the pins for connecting a resonator for main system clock.
(d) EXCLK
This is an external clock input pin for main system clock.
(e) XT1, XT2
These are the pins for connecting a resonator for subsystem clock.
3.2.13 P130, P131 (port 13)
P130 functions as a 1-bit output port. P131 functions as a 1-bit I/O port. These pins also function as timer I/O.
Remark
When the device is reset, P130 outputs a low level. Therefore, to output a high level from P130 before the
device is reset, the output signal of P130 can be used as a pseudo reset signal of the CPU (see the figure for
Remark in 6.2.13 Port 13).
78K0R/KF3-L
78K0R/KG3-L
(μ PD78F10xx: xx = 10, 11, 12,
(μ PD78F10xx: xx = 13, 14,
27, 28)
29, 30)
√
√
Note
√
P130/INTP1
P131/TI06/TO06
Note
−
TI06/TO06 is shared with P06, in the 78K0R/KF3-L.
(1) Port mode
P130 functions as a 1-bit output port.
P131 functions as a 1-bit I/O port. P131 can be set to input or output port using port mode register 13 (PM13). Use
of an on-chip pull-up resistor can be specified by pull-up resistor option register 13 (PU13).
(2) Control mode
P131 functions as timer I/O.
(a) TI06
This is a pin for inputting an external count clock/capture trigger to 16-bit timer 06.
(b) TO06
This is a timer output pin from 16-bit timer 06.
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3.2.14 P140 to P145 (port 14)
P140 to P145 function as an I/O port.
These pins also function as timer I/O, external interrupt request input,
clock/buzzer output, serial interface data I/O, and clock I/O.
Input to the P142 and P143 pins can be specified through a normal input buffer or a TTL input buffer in 1-bit units using
port input mode register 14 (PIM14).
Output from the P142 to P144 pins can be specified as normal CMOS output or N-ch open-drain output (VDD tolerance)
in 1-bit units using port output mode register 14 (POM14).
78K0R/KF3-L
78K0R/KG3-L
(μ PD78F10xx: xx = 10, 11, 12,
(μ PD78F10xx: xx = 13, 14,
27, 28)
29, 30)
√
√
Note 1
√
P142/SCK20/SCL20
√
√
P143/SI20/RxD2/SDA20
√
√
√
√
P140/PCLBUZ0/INTP6
P141/PCLBUZ1/INTP7
−
P144/SO20/TxD2
P145/TI07/TO07
−
Note 2
√
Notes 1. PCLBUZ/INTP7 is shared with P55, in the 78K0R/KF3-L.
2. TI07/TO07 is shared with P54, in the 78K0R/KF3-L.
The following operation modes can be specified in 1-bit units.
(1) Port mode
P140 to P145 function as an I/O port. P140 to P145 can be set to input or output port in 1-bit units using port mode
register 14 (PM14). Use of an on-chip pull-up resistor can be specified by pull-up resistor option register 14 (PU14).
(2) Control mode
P140 to P145 function as timer I/O, external interrupt request input, clock/buzzer output, serial interface data I/O, and
clock I/O.
(a) INTP6, INTP7
These are the external interrupt request input pins for which the valid edge (rising edge, falling edge, or both
rising and falling edges) can be specified.
(b) PCLBUZ0, PCLBUZ1
These are the clock/buzzer output pins.
(c) TI07
This is a pin for inputting an external count clock/capture trigger to 16-bit timer 07.
(d) TO07
This is a timer output pin of 16-bit timer 07.
(e) SI20
This is a serial data input pin of serial interface CSI20.
(f) SO20
This is a serial data output pin of serial interface CSI20.
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(g) SCK20
This is a serial clock I/O pin of serial interface CSI20.
(h) TxD2
This is a serial data output pin of serial interface UART2.
(i)
RxD2
This is a serial data input pin of serial interface UART2.
(j)
SDA20
This is a serial data I/O pin of serial interface for simplified I2C.
(k) SCL20
This is a serial clock I/O pin of serial interface for simplified I2C.
3.2.15 P150 to P157 (port 15)
P150 to P157 function as an I/O port. These pins also function as A/D converter analog input.
78K0R/KF3-L
78K0R/KG3-L
(μ PD78F10xx: xx = 10, 11, 12,
(μ PD78F10xx: xx = 13, 14,
27, 28)
29, 30)
P150/ANI8
√
√
P151/ANI9
√
√
P152/ANI10
√
√
P153/ANI11
√
√
P154/ANI12
−
√
P155/ANI13
−
√
P156/ANI14
−
√
P157/ANI15
−
√
The following operation modes can be specified in 1-bit units.
(1) Port mode
P150 to P157 function as an I/O port. P150 to P157 can be set to input or output port in 1-bit units using port mode
register 15 (PM15).
(2) Control mode
P150 to P157 function as the A/D converter analog input pins (ANI8 to ANI15). When using these pins as the analog
input pins, see 13.6 (5) ANI0/P20 to ANI7/P27 and ANI8/P150 to ANI15/P157.
Caution ANI8/P150 to ANI15/P157 are set in the digital input (general-purpose port) mode after release of
reset.
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3.2.16 AVREF, AVSS, VDD, EVDD0, EVDD1, VSS, EVSS0, EVSS1
78K0R/KF3-L
78K0R/KG3-L
(μ PD78F10xx: xx = 10, 11, 12,
(μ PD78F10xx: xx = 13, 14,
27, 28)
29, 30)
AVREF
√
√
AVSS
√
√
VDD
√
√
EVDD0
√
√
EVDD1
−
√
VSS
√
√
EVSS0
√
√
EVSS1
−
√
(1) AVREF
This is the A/D converter reference voltage input pin and the positive power supply pin of P20 to P27, P150 to P157,
and A/D converter.
When all pins of ports 2 and 15 are used as the analog port pins, make the potential of AVREF be such that 1.8 V ≤
AVREF ≤ VDD. When one or more of the pins of ports 2 and 15 are used as the digital port pins or when the A/D
converter is not used, make AVREF the same potential as EVDD0, EVDD1, and VDD.
(2) AVSS
This is the ground potential pin of A/D converter, P20 to P27, and P150 to P157. Even when the A/D converter is not
used, always use this pin with the same potential as EVSS0, EVSS1, and VSS.
(3) VDD, EVDD0, EVDD1
VDD is the positive power supply pin for P121 to P124 and pins other than ports (excluding the RESET and FLMD0
pins).
EVDD0 and EVDD1 are the positive power supply pins for ports other than P20 to P27, P121 to P124, and P150 to P157
as well as for the RESET and FLMD0 pins.
(4) VSS, EVSS0, EVSS1
VSS is the ground potential pin for P121 to P124 and pins other than ports (excluding the RESET and FLMD0 pins).
EVSS0 and EVSS1 are the ground potential pins for ports other than P20 to P27, P121 to P124, and P150 to P157 as
well as for the RESET and FLMD0 pins.
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3.2.17 RESET
This is the active-low system reset input pin.
When the external reset pin is not used, connect this pin directly or via a resistor to EVDD0 or EVDD1.
When the external reset pin is used, design the circuit based on VDD.
3.2.18 REGC
This is the pin for connecting regulator output (2.4 V) stabilization capacitance for internal operation. Connect this pin
to VSS via a capacitor (0.47 to 1 μF: target).
Also, use a capacitor with good characteristics, since it is used to stabilize internal voltage.
REGC
VSS
Caution Keep the wiring length as short as possible for the broken-line part in the above figure.
3.2.19 FLMD0
This is a pin for setting flash memory programming mode.
Perform either of the following processing.
(a) In normal operation mode
It is recommended to leave this pin open during normal operation.
The FLMD0 pin must always be kept at the VSS level before reset release but does not have to be pulled down
externally because it is internally pulled down by reset. However, pulling it down must be kept selected (i.e.,
FLMDPUP = “0”, default value) by using bit 7 (FLMDPUP) of the background event control register (BECTL) (see
26.5 (1) Back ground event control register). To pull it down externally, use a resistor of 200 kΩ or smaller.
Self programming and the rewriting of flash memory with the programmer can be prohibited using hardware, by
directly connecting this pin to the VSS pin.
(b) In self programming mode
It is recommended to leave this pin open when using the self programming function. To pull it down externally,
use a resistor of 100 kΩ to 200 kΩ.
In the self programming mode, the setting is switched to pull up in the self programming library.
(c) In flash memory programming mode
Directly connect this pin to a flash memory programmer when data is written by the flash memory programmer.
This supplies a writing voltage of the VDD level to the FLMD0 pin.
The FLMD0 pin does not have to be pulled down externally because it is internally pulled down by reset. To pull
it down externally, use a resistor of 1 kΩ to 200 kΩ.
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3.3 Pin I/O Circuits and Recommended Connection of Unused Pins
3.3.1 78K0R/KF3-L
Table 3-3 shows the types of pin I/O circuits and the recommended connections of unused pins. For I/O Circuit Type,
see Figure 3-1. Pin I/O Circuit List.
Table 3-3. Connection of Unused Pins (1/3)
Pin Name
I/O Circuit Type
P02/SO10/TxD1
5-AG
P03/SI10/RxD1/SDA10
5-AN
I/O
I/O
Recommended Connection of Unused Pins
Input:
Independently connect to EVDD0 or EVSS0 via a resistor.
Output: Leave open.
<When N-ch open-drain>
P04/SCK10/SCL10
Set the port output latch to 0 and leave open with low level out put.
P05/TI05/TO05
8-R
Input:
Independently connect to EVDD0 or EVSS0 via a resistor.
Output: Leave open.
P06/TI06/TO06
P10/SCK00
5-AN
Input:
Independently connect to EVDD0 or EVSS0 via a resistor.
Output: Leave open.
<When N-ch open-drain>
Set the port output latch to 0 and leave open with low level out put.
Input:
P11/SI00/RxD0
Independently connect to EVDD0 or EVSS0 via a resistor.
Output: Leave open.
P12/SO00/TxD0
5-AG
Input:
Independently connect to EVDD0 or EVSS0 via a resistor.
Output: Leave open.
<When N-ch open-drain>
Set the port output latch to 0 and leave open with low level out put.
Input:
P13/TxD3
Independently connect to EVDD0 or EVSS0 via a resistor.
Output: Leave open.
Independently connect to EVDD0 or EVSS0 via a resistor.
P14/RxD3
8-R
Input:
P15/RTCDIV/RTCCL
5-AG
Output: Leave open.
P16/TI01/TO01/INTP5
8-R
P17/TI02/TO02
P20/ANI0 to P27/ANI7
Note
11-G
Input:
Independently connect to AVREF or AVSS via a resistor.
Output: Leave open.
P30/RTC1HZ/INTP3
8-R
Input:
Independently connect to EVDD0 or EVSS0 via a resistor.
Output: Leave open.
P31/TI03/TO03/INTP4
P40/TOOL0
<When on-chip debugging is enabled>
Pull this pin up (pulling it down is prohibited).
<When on-chip debugging is disabled>
Input:
Independently connect to EVDD0 or EVSS0 via a resistor.
Output: Leave open.
Note P20/ANI0 to P27/ANI7 are set in the digital input port mode after release of reset.
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Table 3-3. Connection of Unused Pins (2/3)
Pin Name
I/O Circuit Type
P41/TOOL1
5-AG
P42/TI04/TO04
8-R
I/O
I/O
Recommended Connection of Unused Pins
Input:
Independently connect to EVDD0 or EVSS0 via a resistor.
Output: Leave open.
P43/SCK01
P44/SI01
P45/SO01
5-AG
Input:
Independently connect to EVDD0 or EVSS0 via a resistor.
Output: Leave open.
<When N-ch open-drain>
Set the port output latch to 0 and leave open with low level out put.
P46, P47
8-R
Input:
Independently connect to EVDD0 or EVSS0 via a resistor.
Output: Leave open.
P50/SCK40/INTP1
P51/SI40/RxD4/INTP2
P52/SO40/TO00/TxD4
5-AG
P53/SCK41/TI00
8-R
P54/SI41/TI07/TO07
P55/PCLBUZ1/SO41/INTP7
P60/SCL0
13-R
Input:
Independently connect to EVDD0 or EVSS0 via a resistor, or
connect directly to EVSS0.
P61/SDA0
Output: Set the port output latch to 0 and leave open with low
P62
level out put.
P63
13-P
P64/TI10/TO10
8-R
Input:
Independently connect to EVDD0 or EVSS0 via a resistor.
Output: Leave open.
P65/TI11/TO11
P66/TI12/TO12
P67/TI13/TO13
P70/KR0 to P73//KR3
P74/KR4/INTP8 to
P77/KR7/INTP11
P90, P91
5-AG
P110
8-R
P111
5-AG
P120/INTP0/EXLVI
8-R
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Table 3-3. Connection of Unused Pins (3/3)
Pin Name
I/O Circuit Type
Note 1
37-C
P121/X1
P122/X2/EXCLK
P123/XT1
Note 1
P124/XT2
Note 1
I/O
Recommended Connection of Unused Pins
Input
Independently connect to VDD or VSS via a resistor.
Leave open.
Note 1
37-B
P130
3-C
Output
P140/PCLBUZ0/ITNP6
8-R
I/O
Input:
Independently connect to EVDD0 or EVSS0 via a resistor.
Output: Leave open.
Input:
5-AN
P142/SCK20/SCL20
Independently connect to EVDD0 or EVSS0 via a resistor.
Output: Leave open.
P143/SI20/RxD2/SDA20
P144/SO20/TxD2
<When N-ch open-drain>
5-AG
Set the port output latch to 0 and leave open with low level out put.
P150/ANI8 to P153/ANI11
Note 2
Input:
11-G
Independently connect to AVREF or AVSS via a resistor.
Output: Leave open.
−
AVREF
−
<When one or more of P20 to P27 and P150 to P153 are set as a
digital port>
Make this pin the same potential as EVDD0 or VDD.
<When all of P20 to P27 and P150 to P153 are set as analog
ports>
Make this pin to have a potential where 1.8 V ≤ AVREF ≤ VDD.
−
AVSS
FLMD0
2-W
RESET
2
Make this pin the same potential as EVSS0 or VSS.
Leave open or connect to VSS via a resistor of 100 kΩ or more.
Input
−
REGC
−
−
−
Connect directly or via a resistor to EVDD0.
Connect to VSS via capacitor (0.47 to 1 μF).
Notes 1. Use recommended connection above in input port mode (see Figure 7-3 Format of Clock Operation
Mode Control Register (CMC)) when these pins are not used.
2. P150/ANI8 to P153/ANI11 are set in the digital input port mode after release of reset.
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3.3.2 78K0R/KG3-L
Table 3-4 shows the types of pin I/O circuits and the recommended connections of unused pins. For I/O Circuit Type,
see Figure 3-1. Pin I/O Circuit List.
Table 3-4. Connection of Unused Pins (1/3)
Pin Name
I/O Circuit Type
P00/TI00
8-R
P01/TO00
5-AG
I/O
I/O
Recommended Connection of Unused Pins
Input:
Independently connect to EVDD0, EVDD1, EVSS0, or EVSS1
via a resistor.
Output: Leave open.
Input:
P02/SO10/TxD1
P03/SI10/RxD1/SDA10
Independently connect to EVDD0, EVDD1, EVSS0, or EVSS1
via a resistor.
5-AN
Output: Leave open.
P04/SCK10/SCL10
<When N-ch open-drain>
Set the port output latch to 0 and leave open with low level out put.
P05
8-R
Input:
Independently connect to EVDD0, EVDD1, EVSS0, or EVSS1
via a resistor.
P06
Output: Leave open.
5-AN
P10/SCK00
Input:
Independently connect to EVDD0, EVDD1, EVSS0, or EVSS1
via a resistor.
Output: Leave open.
<When N-ch open-drain>
Set the port output latch to 0 and leave open with low level out put.
Input:
P11/SI00/RxD0
Independently connect to EVDD0, EVDD1, EVSS0, or EVSS1
via a resistor.
Output: Leave open.
P12/SO00/TxD0
5-AG
Input:
Independently connect to EVDD0, EVDD1, EVSS0, or EVSS1
via a resistor.
Output: Leave open.
<When N-ch open-drain>
Set the port output latch to 0 and leave open with low level out put.
Input:
P13/TxD3
Independently connect to EVDD0, EVDD1, EVSS0, or EVSS1
via a resistor.
Output: Leave open.
P14/RxD3
8-R
P15/RTCDIV/RTCCL
5-AG
P16/TI01/TO01/INTP5
8-R
Input:
Independently connect to EVDD0, EVDD1, EVSS0, or EVSS1
via a resistor.
Output: Leave open.
P17/TI02/TO02
P20/ANI0 to P27/ANI7
Note
11-G
Input:
Independently connect to AVREF or AVSS via a resistor.
Output: Leave open.
P30/RTC1HZ/INTP3
8-R
Input:
Independently connect to EVDD0, EVDD1, EVSS0, or EVSS1
via a resistor.
P31/TI03/TO03/INTP4
Output: Leave open.
Note P20/ANI0 to P27/ANI7 are set in the digital input port mode after release of reset.
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Table 3-4. Connection of Unused Pins (2/3)
Pin Name
P40/TOOL0
I/O Circuit Type
8-R
I/O
I/O
Recommended Connection of Unused Pins
<When on-chip debugging is enabled>
Pull this pin up (pulling it down is prohibited).
<When on-chip debugging is disabled>
Input:
Independently connect to EVDD0, EVDD1, EVSS0, or EVSS1
via a resistor.
Output: Leave open.
P41/TOOL1
5-AG
P42/TI04/TO04
8-R
Input:
Independently connect to EVDD0, EVDD1, EVSS0, or EVSS1
via a resistor.
Output: Leave open.
P43/SCK01
P44/SI01
P45/SO01
5-AG
Input:
Independently connect to EVDD0, EVDD1, EVSS0, or EVSS1
via a resistor.
Output: Leave open.
<When N-ch open-drain>
Set the port output latch to 0 and leave open with low level out put.
P46/TI05/TO05/INTP1
8-R
Input:
Independently connect to EVDD0, EVDD1, EVSS0, or EVSS1
via a resistor.
P47/INTP2
Output: Leave open.
P50, P51, P53 to P55
P50/SCK40
P51/SI40/RxD4
P52/SO40/TxD4
5-AG
P53/SCK41
8-R
P54/SI41
P55/SO41
P56
5-AG
P57
P60/SCL0
13-R
Input:
Independently connect to EVDD0, EVDD1 or EVSS0, EVSS1 via
a resistor, or connect directly to EVSS0, EVSS1.
P61/SDA0
Output: Set the port output latch to 0 and leave open with low
P62
level out put.
P63
13-P
P64/TI10/TO10
8-R
P65/TI11/TO11
P66/TI12/TO12
Input:
Independently connect to EVDD0, EVDD1, EVSS0, or EVSS1
via a resistor.
Output: Leave open.
P67/TI13/TO13
P70/KR0 to P73//KR3
P74/KR4/INTP8 to
P77/KR7/INTP11
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Table 3-4. Connection of Unused Pins (3/3)
Pin Name
I/O Circuit Type
5-AG
P80 to P87
I/O
Recommended Connection of Unused Pins
Input:
I/O
Independently connect to EVDD0, EVDD1, EVSS0, or EVSS1
via a resistor.
P91
P110
8-R
P111
5-AG
P120/INTP0/EXLVI
8-R
Note 1
37-C
P121/X1
P122/X2/EXCLK
P123/XT1
Note 1
P124/XT2
Note 1
Output: Leave open.
Input
Independently connect to VDD or VSS via a resistor.
Note 1
37-B
P130
3-C
Output
Leave open.
P131/TI06/TO06
8-R
I/O
Input:
Independently connect to EVDD0, EVDD1, EVSS0, or EVSS1
via a resistor.
P140/PCLBUZ0/ITNP6
Output: Leave open.
P141/PCLBUZ1/INTP7
P142/SCK20/SCL20
Input:
5-AN
Independently connect to EVDD0, EVDD1, EVSS0, or EVSS1
via a resistor.
P143/SI20/RxD2/SDA20
P144/SO20/TxD2
Output: Leave open.
5-AG
<When N-ch open-drain>
Set the port output latch to 0 and leave open with low level out put.
P145/TI07/TO07
Input:
8-R
Independently connect to EVDD0, EVDD1, EVSS0, or EVSS1
via a resistor.
Output: Leave open.
Note 2
P150/ANI8 to P157/ANI15
Input:
11-G
Independently connect to AVREF or AVSS via a resistor.
Output: Leave open.
−
AVREF
−
<When one or more of P20 to P27 and P150 to P157 are set as a
digital port>
Make this pin the same potential as EVDD0, EVDD1, or VDD.
<When all of P20 to P27 and P150 to P157 are set as analog
ports>
Make this pin to have a potential where 1.8 V ≤ AVREF ≤ VDD.
−
AVSS
FLMD0
2-W
RESET
2
Make this pin the same potential as EVSS0, EVSS1, or VSS.
−
Leave open or connect to VSS via a resistor of 100 kΩ or more.
Input
−
REGC
−
−
Connect directly or via a resistor to EVDD0 or EVDD1.
Connect to VSS via capacitor (0.47 to 1 μF: target).
Notes 1. Use recommended connection above in input port mode (see Figure 7-3 Format of Clock Operation
Mode Control Register (CMC)) when these pins are not used.
2. P150/ANI8 to P157/ANI15 are set in the digital input port mode after release of reset.
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Figure 3-1. Pin I/O Circuit List (1/2)
Type 2
Type 5-AG
EVDD0, EVDD1
Pull-up
enable
P-ch
EVDD0, EVDD1
IN
Data
P-ch
IN/OUT
Schmitt-triggered input with hysteresis characteristics
Output
disable
N-ch
EVSS0, EVSS1
Input
enable
Type 2-W
Type 5-AN
EVDD0, EVDD1
EVDD0, EVDD1
Pull-up
enable
P-ch
Pull-up
enable
P-ch
EVDD0, EVDD1
Data
P-ch
Output
disable
N-ch
IN/OUT
Pull-down
enable
N-ch
EVSS0, EVSS1
EVSS0, EVSS1
CMOS
IN
TTL
Schmitt-triggered input with hysteresis characteristics
Input
characteristic
Type 3-C
Type 8-R
EVDD0, EVDD1
EVDD0, EVDD1
Pull-up
enable
P-ch
P-ch
EVDD0, EVDD1
Data
OUT
Data
P-ch
IN/OUT
N-ch
Output
disable
N-ch
EVSS0, EVSS1
EVSS0, EVSS1
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Figure 3-1. Pin I/O Circuit List (2/2)
Type 11-G
Type 37-B
AVREF
Data
P-ch
XT2
IN/OUT
Output
disable
Input
enable
N-ch
AVSS
amp
enable
P-ch
+
_
P-ch
N-ch
Comparator
N-ch
Series resistor string voltage
XT1
AVSS
Input
enable
Input enable
Type 13-P
Type 37-C
Output
disable
X2
IN/OUT
Data
input
enable
N-ch
P-ch
N-ch
EVSS0, EVSS1
amp
enable
Input
enable
X1
input
enable
Type 13-R
IN/OUT
Data
Output disable
N-ch
EVSS0, EVSS1
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CHAPTER 4 CPU ARCHITECTURE
CHAPTER 4 CPU ARCHITECTURE
4.1 Memory Space
Products in the 78K0R/Kx3-L can access a 1 MB memory space. Figures 4-1 to 4-9 show the memory maps.
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Figure 4-1. Memory Map (μPD78F1000)
03FFFH
FFFFFH
Special function register (SFR)
256 bytes
FFF00H
FFEFFH
FFEE0H
FFEDFH
General-purpose register
32 bytes
RAMNotes 1, 2
1 KB
FFB00H
FFAFFH
Program area
Reserved
01FFFH
F4000H
F3FFFH
010CEH
010CDH
Mirror
12 KB
F1000H
F0FFFH
Reserved
010C4H
010C3H
F0800H
F07FFH
Special function register (2nd SFR)
2 KB
Data memory
space
010C0H
010BFH
01080H
0107FH
F0000H
EFFFFH
On-chip debug security
ID setting areaNote 3
10 bytes
Option byte areaNote 3
4 bytes
Boot cluster 1
CALLT table area
64 bytes
Vector table area
128 bytes
01000H
00FFFH
Program area
Reserved
000CEH
000CDH
000C4H
000C3H
000C0H
000BFH
00080H
0007FH
Program
memory
space
04000H
03FFFH
00000H
On-chip debug security
ID setting areaNote 3
10 bytes
Option byte areaNote 3
4 bytes
Boot cluster 0Note 4
CALLT table area
64 bytes
Vector table area
128 bytes
Flash memory
16 KB
00000H
Notes 1. While using the self-programming function, the area FFE20H to FFEFFH cannot be used as stack memory.
2. Instructions can be executed from the RAM area excluding the general-purpose register area.
3. When boot swap is not used: Set the option bytes to 000C0H to 000C3H, and the on-chip debug security
IDs to 000C4H to 000CDH.
When boot swap is used:
Set the option bytes to 000C0H to 000C3H and 010C0H to 010C3H, and the
on-chip debug security IDs to 000C4H to 000CDH and 010C4H to 010CDH.
4. Writing boot cluster 0 can be prohibited depending on the setting of security (see 26.7 Security Setting).
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Figure 4-2. Memory Map (μPD78F1001, 78F1004, 78F1007)
07FFFH
FFFFFH
Special function register (SFR)
256 bytes
FFF00H
FFEFFH
FFEE0H
FFEDFH
General-purpose register
32 bytes
RAMNotes 1, 2
1.5 KB
FF900H
FF8FFH
Program area
Reserved
01FFFH
F8000H
F7FFFH
F1000H
F0FFFH
Mirror
28 KB
010CEH
010CDH
Reserved
010C4H
010C3H
F0800H
F07FFH
Special function register (2nd SFR)
2 KB
Data memory
space
010C0H
010BFH
01080H
0107FH
F0000H
EFFFFH
On-chip debug security
ID setting areaNote 3
10 bytes
Option byte areaNote 3
4 bytes
Boot cluster 1
CALLT table area
64 bytes
Vector table area
128 bytes
01000H
00FFFH
Program area
Reserved
000CEH
000CDH
000C4H
000C3H
000C0H
000BFH
00080H
0007FH
08000H
07FFFH
Program
memory
space
On-chip debug security
ID setting areaNote 3
10 bytes
Option byte areaNote 3
4 bytes
Boot cluster 0Note 4
CALLT table area
64 bytes
Vector table area
128 bytes
Flash memory
32 KB
00000H
00000H
Notes 1. While using the self-programming function, the area FFE20H to FFEFFH cannot be used as stack memory.
2. Instructions can be executed from the RAM area excluding the general-purpose register area.
3. When boot swap is not used: Set the option bytes to 000C0H to 000C3H, and the on-chip debug security
IDs to 000C4H to 000CDH.
When boot swap is used:
Set the option bytes to 000C0H to 000C3H and 010C0H to 010C3H, and the
on-chip debug security IDs to 000C4H to 000CDH and 010C4H to 010CDH.
4. Writing boot cluster 0 can be prohibited depending on the setting of security (see 26.7 Security Setting).
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Figure 4-3. Memory Map (μPD78F1002, 78F1005, 78F1008)
0BFFFH
FFFFFH
Special function register (SFR)
256 bytes
FFF00H
FFEFFH
FFEE0H
FFEDFH
General-purpose register
32 bytes
RAMNotes 1, 2
2 KB
FF700H
FF6FFH
Program area
Reserved
01FFFH
FC000H
FBFFFH
F1000H
F0FFFH
Mirror
44 KB
010CEH
010CDH
Reserved
010C4H
010C3H
F0800H
F07FFH
Special function register (2nd SFR)
2 KB
Data memory
space
F0000H
EFFFFH
010C0H
010BFH
01080H
0107FH
On-chip debug security
ID setting areaNote 3
10 bytes
Option byte areaNote 3
4 bytes
Boot cluster 1
CALLT table area
64 bytes
Vector table area
128 bytes
01000H
00FFFH
Reserved
Program area
000CEH
000CDH
000C4H
000C3H
000C0H
000BFH
00080H
0007FH
0C000H
0BFFFH
Program
memory
space
Option byte areaNote 3
4 bytes
Boot cluster 0Note 4
CALLT table area
64 bytes
Vector table area
128 bytes
Flash memory
48 KB
00000H
On-chip debug security
ID setting areaNote 3
10 bytes
00000H
Notes 1. While using the self-programming function, the area FFE20H to FFEFFH cannot be used as stack memory.
2. Instructions can be executed from the RAM area excluding the general-purpose register area.
3. When boot swap is not used: Set the option bytes to 000C0H to 000C3H, and the on-chip debug security
IDs to 000C4H to 000CDH.
When boot swap is used:
Set the option bytes to 000C0H to 000C3H and 010C0H to 010C3H, and the
on-chip debug security IDs to 000C4H to 000CDH and 010C4H to 010CDH.
4. Writing boot cluster 0 can be prohibited depending on the setting of security (see 26.7 Security Setting).
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Figure 4-4. Memory Map (μPD78F1003, 78F1006, 78F1009)
0FFFFH
FFFFFH
Special function register (SFR)
256 bytes
FFF00H
FFEFFH
FFEE0H
FFEDFH
General-purpose register
32 bytes
RAMNotes 1, 2
3 KB
Program area
FF300H
FF2FFH
Mirror
56.75 KB
01FFFH
010CEH
010CDH
F1000H
F0FFFH
Reserved
010C4H
010C3H
F0800H
F07FFH
Special function register (2nd SFR)
2 KB
Data memory
space
F0000H
EFFFFH
010C0H
010BFH
01080H
0107FH
On-chip debug security
ID setting areaNote 3
10 bytes
Option byte areaNote 3
4 bytes
Boot cluster 1
CALLT table area
64 bytes
Vector table area
128 bytes
01000H
00FFFH
Reserved
Program area
000CEH
000CDH
000C4H
000C3H
000C0H
000BFH
00080H
0007FH
10000H
0FFFFH
Program
memory
space
Notes 1.
Option byte areaNote 3
4 bytes
Boot cluster 0Note 4
CALLT table area
64 bytes
Vector table area
128 bytes
Flash memory
64 KB
00000H
On-chip debug security
ID setting areaNote 3
10 bytes
00000H
While using the self-programming function, the area FFE20H to FFEFFH cannot be used as stack memory.
Furthermore, the areas of FF300H to FF6FFH also cannot be used with the μPD78F1003, 78F1006 and
78F1009.
2. Instructions can be executed from the RAM area excluding the general-purpose register area.
3. When boot swap is not used: Set the option bytes to 000C0H to 000C3H, and the on-chip debug security
IDs to 000C4H to 000CDH.
When boot swap is used:
Set the option bytes to 000C0H to 000C3H and 010C0H to 010C3H, and the
on-chip debug security IDs to 000C4H to 000CDH and 010C4H to 010CDH.
4. Writing boot cluster 0 can be prohibited depending on the setting of security (see 26.7 Security Setting).
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Figure 4-5. Memory Map (μPD78F1010)
0FFFFH
FFFFFH
Special function register (SFR)
256 bytes
FFF00H
FFEFFH
FFEE0H
FFEDFH
General-purpose register
32 bytes
RAMNotes 1, 2
4 KB
Program area
FEF00H
FEEFFH
Mirror
55.75 KB
01FFFH
010CEH
010CDH
F1000H
F0FFFH
Reserved
010C4H
010C3H
F0800H
F07FFH
Special function register (2nd SFR)
2 KB
F0000H
EFFFFH
Data memory
space
010C0H
010BFH
01080H
0107FH
On-chip debug security
ID setting areaNote 3
10 bytes
Option byte areaNote 3
4 bytes
Boot cluster 1
CALLT table area
64 bytes
Vector table area
128 bytes
01000H
00FFFH
Reserved
Program area
000CEH
000CDH
000C4H
000C3H
000C0H
000BFH
00080H
0007FH
10000H
0FFFFH
Program
memory
space
Option byte areaNote 3
4 bytes
Boot cluster 0Note 4
CALLT table area
64 bytes
Vector table area
128 bytes
Flash memory
64 KB
00000H
On-chip debug security
ID setting areaNote 3
10 bytes
00000H
Notes 1. While using the self-programming function, the area FFE20H to FFEFFH cannot be used as stack memory.
2. Instructions can be executed from the RAM area excluding the general-purpose register area.
3. When boot swap is not used: Set the option bytes to 000C0H to 000C3H, and the on-chip debug security
IDs to 000C4H to 000CDH.
When boot swap is used:
Set the option bytes to 000C0H to 000C3H and 010C0H to 010C3H, and the
on-chip debug security IDs to 000C4H to 000CDH and 010C4H to 010CDH.
4. Writing boot cluster 0 can be prohibited depending on the setting of security (see 26.7 Security Setting).
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Figure 4-6. Memory Map (μPD78F1011, 78F1013)
17FFFH
FFFFFH
Special function register (SFR)
256 bytes
FFF00H
FFEFFH
FFEE0H
FFEDFH
General-purpose register
32 bytes
Program area
Notes 1, 2
RAM
6 KB
FE700H
FE6FFH
Mirror
53.75 KB
01FFFH
010CEH
010CDH
F1000H
F0FFFH
Reserved
010C4H
010C3H
F0800H
F07FFH
Special function register (2nd SFR)
2 KB
Data memory
space
F0000H
EFFFFH
010C0H
010BFH
01080H
0107FH
On-chip debug security
ID setting areaNote 3
10 bytes
Option byte areaNote 3
4 bytes
CALLT table area
64 bytes
Boot cluster 1
Vector table area
128 bytes
01000H
00FFFH
Reserved
Program area
000CEH
000CDH
000C4H
000C3H
000C0H
000BFH
18000H
17FFFH
00080H
0007FH
Flash memory
96 KB
Program
memory
space
00000H
On-chip debug security
ID setting areaNote 3
10 bytes
Option byte areaNote 3
4 bytes
Boot cluster 0Note 4
CALLT table area
64 bytes
Vector table area
128 bytes
00000H
Notes 1. While using the self-programming function, the area FFE20H to FFEFFH cannot be used as stack memory.
2. Instructions can be executed from the RAM area excluding the general-purpose register area.
3. When boot swap is not used: Set the option bytes to 000C0H to 000C3H, and the on-chip debug security
IDs to 000C4H to 000CDH.
When boot swap is used:
Set the option bytes to 000C0H to 000C3H and 010C0H to 010C3H, and the
on-chip debug security IDs to 000C4H to 000CDH and 010C4H to 010CDH.
4. Writing boot cluster 0 can be prohibited depending on the setting of security (see 26.7 Security Setting).
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Figure 4-7. Memory Map (μPD78F1012, 78F1014)
FFFFFH
1FFFFH
Special function register (SFR)
256 bytes
FFF00H
FFEFFH
FFEE0H
FFEDFH
General-purpose register
32 bytes
Program area
Notes 1, 2
RAM
8 KB
FDF00H
FDEFFH
01FFFH
Mirror
51.75 KB
010CEH
010CDH
F1000H
F0FFFH
Reserved
010C4H
010C3H
F0800H
F07FFH
Special function register (2nd SFR)
2 KB
Data memory
space
F0000H
EFFFFH
010C0H
010BFH
On-chip debug security
ID setting areaNote 3
10 bytes
Option byte areaNote 3
4 bytes
CALLT table area
64 bytes
Boot cluster 1
01080H
0107FH
Vector table area
128 bytes
01000H
00FFFH
Reserved
Program area
000CEH
000CDH
000C4H
000C3H
000C0H
000BFH
20000H
1FFFFH
Program
memory
space
On-chip debug security
ID setting areaNote 3
10 bytes
Option byte areaNote 3
4 bytes
Boot cluster 0 Note 4
CALLT table area
64 bytes
00080H
0007FH
Flash memory
128 KB
00000H
Vector table area
128 bytes
00000H
Notes 1. While using the self-programming function, the area FFE20H to FFEFFH cannot be used as stack memory.
Furthermore, the areas of FDF00H to FE2FFH also cannot be used with the μPD78F1012 and 78F1014.
2. Instructions can be executed from the RAM area excluding the general-purpose register area.
3. When boot swap is not used: Set the option bytes to 000C0H to 000C3H, and the on-chip debug security
IDs to 000C4H to 000CDH.
When boot swap is used:
Set the option bytes to 000C0H to 000C3H and 010C0H to 010C3H, and the
on-chip debug security IDs to 000C4H to 000CDH and 010C4H to 010CDH.
4. Writing boot cluster 0 can be prohibited depending on the setting of security (see 26.7 Security Setting).
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Figure 4-8. Memory Map (μPD78F1027, 78F1029)
FFFFFH
2FFFFH
Special function register (SFR)
256 bytes
FFF00H
FFEFFH
FFEE0H
FFEDFH
General-purpose register
32 bytes
Program area
RAMNotes 1, 2
10 KB
FD700H
FD6FFH
Mirror
49.75 KB
01FFFH
F1000H
F0FFFH
Reserved
F0800H
F07FFH
Special function register (2nd SFR)
2 KB
F0000H
EFFFFH
010CEH
010CDH
010C4H
010C3H
010C0H
010BFH
On-chip debug security
ID setting areaNote 3
10 bytes
Option byte areaNote 3
4 bytes
CALLT table area
64 bytes
Boot cluster 1
01080H
0107FH
Data memory
space
Vector table area
128 bytes
Reserved
01000H
00FFFH
Program area
000CEH
000CDH
000C4H
000C3H
30000H
2FFFFH
000C0H
000BFH
On-chip debug security
ID setting areaNote 3
10 bytes
Option byte areaNote 3
4 bytes
Boot cluster 0Note 4
CALLT table area
64 bytes
Program
memory
space
Flash memory
192 KB
00080H
0007FH
Vector table area
128 bytes
00000H
00000H
Notes 1. While using the self-programming function, the area FFE20H to FFEFFH cannot be used as stack memory.
2. Instructions can be executed from the RAM area excluding the general-purpose register area.
3. When boot swap is not used: Set the option bytes to 000C0H to 000C3H, and the on-chip debug security
IDs to 000C4H to 000CDH.
When boot swap is used:
Set the option bytes to 000C0H to 000C3H and 010C0H to 010C3H, and the
on-chip debug security IDs to 000C4H to 000CDH and 010C4H to 010CDH.
4. Writing boot cluster 0 can be prohibited depending on the setting of security (see 26.7 Security Setting).
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Figure 4-9. Memory Map (μPD78F1028, 78F1030)
FFFFFH
3FFFFH
Special function register (SFR)
256 bytes
FFF00H
FFEFFH
FFEE0H
FFEDFH
General-purpose register
32 bytes
Program area
RAMNotes 1, 2
12 KB
FCF00H
FCEFFH
Mirror
47.75 KB
01FFFH
F1000H
F0FFFH
Reserved
F0800H
F07FFH
Special function register (2nd SFR)
2 KB
F0000H
EFFFFH
010CEH
010CDH
010C4H
010C3H
010C0H
010BFH
On-chip debug security
ID setting areaNote 3
10 bytes
Option byte areaNote 3
4 bytes
CALLT table area
64 bytes
Boot cluster 1
01080H
0107FH
Data memory
space
Vector table area
128 bytes
Reserved
01000H
00FFFH
Program area
000CEH
000CDH
40000H
3FFFFH
000C4H
000C3H
000C0H
000BFH
Program
memory
space
Flash memory
256 KB
On-chip debug security
ID setting areaNote 3
10 bytes
Option byte areaNote 3
4 bytes
Boot cluster 0Note 4
CALLT table area
64 bytes
00080H
0007FH
Vector table area
128 bytes
00000H
00000H
Notes 1. While using the self-programming function, the area FFE20H to FFEFFH cannot be used as stack memory.
Furthermore, the areas of FCF00H to FD2FFH also cannot be used with the μPD78F1029 and 78F1030.
2. Instructions can be executed from the RAM area excluding the general-purpose register area.
3. When boot swap is not used: Set the option bytes to 000C0H to 000C3H, and the on-chip debug security
IDs to 000C4H to 000CDH.
When boot swap is used:
Set the option bytes to 000C0H to 000C3H and 010C0H to 010C3H, and the
on-chip debug security IDs to 000C4H to 000CDH and 010C4H to 010CDH.
4. Writing boot cluster 0 can be prohibited depending on the setting of security (see 26.7 Security Setting).
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Remark
CHAPTER 4 CPU ARCHITECTURE
The flash memory is divided into blocks (one block = 1 KB). For the address values and block numbers, see
Table 4-1 Correspondence Between Address Values and Block Numbers in Flash Memory.
1FFFFH
Block 7FH
1FC00H
1FBFFH
007FFH
00400H
003FFH
Block 01H
Block 00H
1 KB
00000H
(μPD78F1012, 78F1014)
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Correspondence between the address values and block numbers in the flash memory are shown below.
Table 4-1. Correspondence Between Address Values and Block Numbers in Flash Memory (1/2)
Address Value
Block
Address Value
00000H to 003FFH
00H
Block
Address Value
08000H to 083FFH
20H
Block
Address Value
10000H to 103FFH
40H
Block
Number
Number
Number
Number
18000H to 183FFH
60H
00400H to 007FFH
01H
08400H to 087FFH
21H
10400H to 107FFH
41H
18400H to 187FFH
61H
00800H to 00BFFH
02H
08800H to 08BFFH
22H
10800H to 10BFFH
42H
18800H to 18BFFH
62H
00C00H to 00FFFH
03H
08C00H to 08FFFH
23H
10C00H to 10FFFH
43H
18C00H to 18FFFH
63H
01000H to 013FFH
04H
09000H to 093FFH
24H
11000H to 113FFH
44H
19000H to 193FFH
64H
01400H to 017FFH
05H
09400H to 097FFH
25H
11400H to 117FFH
45H
19400H to 197FFH
65H
01800H to 01BFFH
06H
09800H to 09BFFH
26H
11800H to 11BFFH
46H
19800H to 19BFFH
66H
01C00H to 01FFFH
07H
09C00H to 09FFFH
27H
11C00H to 11FFFH
47H
19C00H to 19FFFH
67H
02000H to 023FFH
08H
0A000H to 0A3FFH
28H
12000H to 123FFH
48H
1A000H to 1A3FFH
68H
02400H to 027FFH
09H
0A400H to 0A7FFH
29H
12400H to 127FFH
49H
1A400H to 1A7FFH
69H
02800H to 02BFFH
0AH
0A800H to 0ABFFH
2AH
12800H to 12BFFH
4AH
1A800H to 1ABFFH
6AH
02C00H to 02FFFH
0BH
0AC00H to 0AFFFH
2BH
12C00H to 12FFFH
4BH
1AC00H to 1AFFFH
6BH
03000H to 033FFH
0CH
0B000H to 0B3FFH
2CH
13000H to 133FFH
4CH
1B000H to 1B3FFH
6CH
03400H to 037FFH
0DH
0B400H to 0B7FFH
2DH
13400H to 137FFH
4DH
1B400H to 1B7FFH
6DH
03800H to 03BFFH
0EH
0B800H to 0BBFFH
2EH
13800H to 13BFFH
4EH
1B800H to 1BBFFH
6EH
03C00H to 03FFFH
0FH
0BC00H to 0BFFFH
2FH
13C00H to 13FFFH
4FH
1BC00H to 1BFFFH
6FH
04000H to 043FFH
10H
0C000H to 0C3FFH
30H
14000H to 143FFH
50H
1C000H to 1C3FFH
70H
04400H to 047FFH
11H
0C400H to 0C7FFH
31H
14400H to 147FFH
51H
1C400H to 1C7FFH
71H
04800H to 04BFFH
12H
0C800H to 0CBFFH
32H
14800H to 14BFFH
52H
1C800H to 1CBFFH
72H
04C00H to 04FFFH
13H
0CC00H to 0CFFFH
33H
14C00H to 14FFFH
53H
1CC00H to 1CFFFH
73H
05000H to 053FFH
14H
0D000H to 0D3FFH
34H
15000H to 153FFH
54H
1D000H to 1D3FFH
74H
05400H to 057FFH
15H
0D400H to 0D7FFH
35H
15400H to 157FFH
55H
1D400H to 1D7FFH
75H
05800H to 05BFFH
16H
0D800H to 0DBFFH
36H
15800H to 15BFFH
56H
1D800H to 1DBFFH
76H
05C00H to 05FFFH
17H
0DC00H to 0DFFFH
37H
15C00H to 15FFFH
57H
1DC00H to 1DFFFH
77H
06000H to 063FFH
18H
0E000H to 0E3FFH
38H
16000H to 163FFH
58H
1E000H to 1E3FFH
78H
06400H to 067FFH
19H
0E400H to 0E7FFH
39H
16400H to 167FFH
59H
1E400H to 1E7FFH
79H
06800H to 06BFFH
1AH
0E800H to 0EBFFH
3AH
16800H to 16BFFH
5AH
1E800H to 1EBFFH
7AH
06C00H to 06FFFH
1BH
0EC00H to 0EFFFH
3BH
16C00H to 16FFFH
5BH
1EC00H to 1EFFFH
7BH
07000H to 073FFH
1CH
0F000H to 0F3FFH
3CH
17000H to 173FFH
5CH
1F000H to 1F3FFH
7CH
07400H to 077FFH
1DH
0F400H to 0F7FFH
3DH
17400H to 177FFH
5DH
1F400H to 1F7FFH
7DH
07800H to 07BFFH
1EH
0F800H to 0FBFFH
3EH
17800H to 17BFFH
5EH
1F800H to 1FBFFH
7EH
07C00H to 07FFFH
1FH
0FC00H to 0FFFFH
3FH
17C00H to 17FFFH
5FH
1FC00H to 1FFFFH
7FH
Remark
μPD78F1000:
Block numbers 00H to 0FH
μPD78F1001, 78F1004, 78F1007:
Block numbers 00H to 1FH
μPD78F1002, 78F1005, 78F1008:
Block numbers 00H to 2FH
μPD78F1003, 78F1006, 78F1009, 78F1010: Block numbers 00H to 3FH
μPD78F1011, 78F1013:
Block numbers 00H to 5FH
μPD78F1012, 78F1014:
Block numbers 00H to 7FH
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Table 4-1. Correspondence Between Address Values and Block Numbers in Flash Memory (2/2)
Address Value
Block
Address Value
Number
Block
Address Value
Number
Block
Address Value
Number
Block
Number
20000H to 203FFH
80H
28000H to 283FFH
A0H
30000H to 303FFH C0H
38000H to 383FFH
E0H
20400H to 207FFH
81H
28400H to 287FFH
A1H
30400H to 307FFH C1H
38400H to 387FFH
E1H
20800H to 20BFFH
82H
28800H to 28BFFH
A2H
30800H to 30BFFH C2H
38800H to 38BFFH E2H
20C00H to 20FFFH
83H
28C00H to 28FFFH
A3H
30C00H to 30FFFH C3H
38C00H to 38FFFH E3H
21000H to 213FFH
84H
29000H to 293FFH
A4H
31000H to 313FFH C4H
39000H to 393FFH
E4H
21400H to 217FFH
85H
29400H to 297FFH
A5H
31400H to 317FFH C5H
39400H to 397FFH
E5H
21800H to 21BFFH
86H
29800H to 29BFFH
A6H
31800H to 31BFFH C6H
39800H to 39BFFH E6H
21C00H to 21FFFH
87H
29C00H to 29FFFH
A7H
31C00H to 31FFFH C7H
39C00H to 39FFFH E7H
22000H to 223FFH
88H
2A000H to 2A3FFH
A8H
32000H to 323FFH C8H
3A000H to 3A3FFH E8H
22400H to 227FFH
89H
2A400H to 2A7FFH
A9H
32400H to 327FFH C9H
3A400H to 3A7FFH E9H
22800H to 22BFFH
8AH
2A800H to 2ABFFH AAH
32800H to 32BFFH CAH
3A800H to 3ABFFH EAH
22C00H to 22FFFH
8BH
2AC00H to 2AFFFH ABH
32C00H to 32FFFH CBH
3AC00H to 3AFFFH EBH
23000H to 233FFH
8CH
2B000H to 2B3FFH
ACH
33000H to 333FFH CCH
3B000H to 3B3FFH ECH
23400H to 237FFH
8DH
2B400H to 2B7FFH
ADH
33400H to 337FFH CDH
3B400H to 3B7FFH EDH
23800H to 23BFFH
8EH
2B800H to 2BBFFH AEH
33800H to 33BFFH CEH
3B800H to 3BBFFH EEH
23C00H to 23FFFH
8FH
2BC00H to 2BFFFH AFH
33C00H to 33FFFH CFH
3BC00H to 3BFFFH EFH
24000H to 243FFH
90H
2C000H to 2C3FFH B0H
34000H to 343FFH D0H
3C000H to 3C3FFH F0H
24400H to 247FFH
91H
2C400H to 2C7FFH B1H
34400H to 347FFH D1H
3C400H to 3C7FFH F1H
24800H to 24BFFH
92H
2C800H to 2CBFFH B2H
34800H to 34BFFH D2H
3C800H to 3CBFFH F2H
24C00H to 24FFFH
93H
2CC00H to 2CFFFH B3H
34C00H to 34FFFH D3H
3CC00H to 3CFFFH F3H
25000H to 253FFH
94H
2D000H to 2D3FFH B4H
35000H to 353FFH D4H
3D000H to 3D3FFH F4H
25400H to 257FFH
95H
2D400H to 2D7FFH B5H
35400H to 357FFH D5H
3D400H to 3D7FFH F5H
25800H to 25BFFH
96H
2D800H to 2DBFFH B6H
35800H to 35BFFH D6H
3D800H to 3DBFFH F6H
25C00H to 25FFFH
97H
2DC00H to 2DFFFH B7H
35C00H to 35FFFH D7H
3DC00H to 3DFFFH 77H
26000H to 263FFH
98H
2E000H to 2E3FFH
B8H
36000H to 363FFH D8H
3E000H to 3E3FFH F8H
26400H to 267FFH
99H
2E400H to 2E7FFH
B9H
36400H to 367FFH D9H
3E400H to 3E7FFH F9H
26800H to 26BFFH
9AH
2E800H to 2EBFFH BAH
36800H to 36BFFH DAH
3E800H to 3EBFFH FAH
26C00H to 26FFFH
9BH
2EC00H to 2EFFFH BBH
36C00H to 36FFFH DBH
3EC00H to 3EFFFH FBH
27000H to 273FFH
9CH
2F000H to 2F3FFH
BCH
37000H to 373FFH DCH
3F000H to 3F3FFH FCH
27400H to 277FFH
9DH
2F400H to 2F7FFH
BDH
37400H to 377FFH DDH
3F400H to 3F7FFH FDH
27800H to 27BFFH
9EH
2F800H to 2FBFFH
BEH
37800H to 37BFFH DEH
3F800H to 3FBFFH FEH
27C00H to 27FFFH
9FH
2FC00H to 2FFFFH BFH
37C00H to 37FFFH DFH
3FC00H to 3FFFFH FFH
Remark
μPD78F1027, 78F1029:
μPD78F1028, 78F1030:
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Block numbers 00H to FFH
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4.1.1 Internal program memory space
The internal program memory space stores the program and table data.
The 78K0R/Kx3-L products incorporate internal ROM (flash memory), as shown below.
Table 4-2. Internal ROM Capacity
Part Number
Internal ROM
Structure
μPD78F1000
Flash memory
Capacity
16384 × 8 bits (00000H to 03FFFH)
μPD78F1001, 78F1004, 78F1007
32768 × 8 bits (00000H to 07FFFH)
μPD78F1002, 78F1005, 78F1008
49152 × 8 bits (00000H to 0BFFFH)
μPD78F1003, 78F1006, 78F1009, 78F1010
65536 × 8 bits (00000H to 0FFFFH)
μPD78F1011, 78F1013
98304 × 8 bits (00000H to 17FFFH)
μPD78F1012, 78F1014
131072 × 8 bits (00000H to 1FFFFH)
μPD78F1027, 78F1029
196608 × 8 bits (00000H to 2FFFFH)
μPD78F1028, 78F1030
262144 × 8 bits (00000H to 3FFFFH)
The internal program memory space is divided into the following areas.
(1) Vector table area
The 128-byte area 00000H to 0007FH is reserved as a vector table area. The program start addresses for branch
upon reset or generation of each interrupt request are stored in the vector table area. Furthermore, the interrupt jump
address is a 64 K address of 00000H to 0FFFFH, because the vector code is assumed to be 2 bytes.
Of the 16-bit address, the lower 8 bits are stored at even addresses and the higher 8 bits are stored at odd addresses.
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Table 4-3. Vector Table (1/2)
Vector Table Address
Interrupt Source
KC3-L (40pin)
KC3-L (44-pin)
KC3-L (48-pin)
KD3-L
KE3-L
KF3-L
KG3-L
00000H
RESET input, POC, LVI, WDT, TRAP
√
√
√
√
√
√
√
00004H
INTWDTI
√
√
√
√
√
√
√
00006H
INTLVI
√
√
√
√
√
√
√
00008H
INTP0
√
√
√
√
√
√
√
0000AH
INTP1
√
√
√
√
√
√
√
0000CH
INTP2
√
√
√
√
√
√
√
0000EH
INTP3
√
√
√
√
√
√
√
00010H
INTP4
√
√
√
√
√
√
√
00012H
INTP5
√
√
√
√
√
√
√
00014H
INTST3
−
−
−
−
−
√
√
00016H
INTSR3
−
−
−
−
−
√
√
INTCMP0
√
√
√
√
√
−
−
INTSRE3
−
−
−
−
−
√
√
INTCMP1
√
√
√
√
√
−
−
0001AH
INTDMA0
√
√
√
√
√
√
√
0001CH
INTDMA1
√
√
√
√
√
√
√
0001EH
INTST0/INTCSI00
√
√
√
√
√
√
√
00020H
INTSR0/INTCSI01
√
√
√
√
√
√
√
00022H
INTSRE0
√
√
√
√
√
√
√
00024H
INTST1/INTCSI10/INTIIC10
√
√
√
√
√
√
√
00026H
INTSR1
√
√
√
√
√
√
√
00028H
INTSRE1
√
√
√
√
√
√
√
0002AH
INTIICA
−
−
√
√
√
√
√
0002CH
INTTM00
√
√
√
√
√
√
√
0002EH
INTTM01
√
√
√
√
√
√
√
00030H
INTTM02
√
√
√
√
√
√
√
00032H
INTTM03
√
√
√
√
√
√
√
00018H
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Table 4-3. Vector Table (2/2)
KC3-L (40-pin)
KC3-L (44-pin)
KC3-L (48-pin)
KD3-L
KE3-L
KF3-L
KG3-L
00034H
INTAD
√
√
√
√
√
√
√
00036H
INTRTC
−
√
√
√
√
√
√
00038H
INTRTCI
−
√
√
√
√
√
√
0003AH
INTKR
√
√
√
√
√
√
√
0003CH
INTST2/INTCSI20/INTIIC20
−
−
−
−
−
√
√
0003EH
INTP6
−
−
−
−
−
√
√
00040H
INTTM13
−
−
−
−
−
√
√
INTMD
√
√
√
√
√
−
−
00042H
INTTM04
√
√
√
√
√
√
√
00044H
INTTM05
√
√
√
√
√
√
√
00046H
INTTM06
√
√
√
√
√
√
√
00048H
INTTM07
√
√
√
√
√
√
√
0004AH
INTSR2
−
−
−
−
−
√
√
INTP6
√
√
√
√
√
−
−
0004CH
INTP7
−
√
√
√
√
√
√
0004EH
INTP8
−
−
−
−
−
√
√
00050H
INTP9
−
−
−
−
−
√
√
00052H
INTP10
−
−
−
−
−
√
√
00054H
INTP11
−
−
−
−
−
√
√
INTSRE4
−
−
−
−
−
00056H
INTTM10
−
−
−
−
−
√
√
00058H
INTTM11
−
−
−
−
−
√
√
0005AH
INTTM12
−
−
−
−
−
√
√
0005CH
INTSRE2
−
−
−
−
−
√
√
0005EH
INTMD
−
−
−
−
−
√
√
00060H
INTST4
−
−
−
−
−
Note Note
INTCSI40
−
−
−
−
−
Note Note
INTSR4
−
−
−
−
−
Note Note
INTCSI41
−
−
−
−
−
Note Note
BRK
√
√
√
√
√
Vector Table Address
00062H
0007EH
Interrupt Source
Note Note
√
√
Note Those are only mounted in the 78K0R/KF3-L (μ PD78F1027 and 78F1028) and the 78K0R/KG3-L (μ
PD78F1029 and 78F1030).
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(2) CALLT instruction table area
The 64-byte area 00080H to 000BFH can store the subroutine entry address of a 2-byte call instruction (CALLT). Set
the subroutine entry address to a value in a range of 00000H to 0FFFFH (because an address code is of 2 bytes).
To use the boot swap function, set a CALLT instruction table also at 01080H to 010BFH.
(3) Option byte area
A 4-byte area of 000C0H to 000C3H can be used as an option byte area. Set the option byte at 010C0H to 010C3H
when the boot swap is used. For details, see CHAPTER 25 OPTION BYTE.
(4) On-chip debug security ID setting area
A 10-byte area of 000C4H to 000CDH and 010C4H to 010CDH can be used as an on-chip debug security ID setting
area. Set the on-chip debug security ID of 10 bytes at 000C4H to 000CDH when the boot swap is not used and at
000C4H to 000CDH and 010C4H to 010CDH when the boot swap is used. For details, see CHAPTER 27 ON-CHIP
DEBUG FUNCTION.
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4.1.2 Mirror area
The 78K0R/Kx3-L mirrors the data flash area of 00000H to 0FFFFH, to F0000H to FFFFFH. The μPD78F1011 to
78F1014, 78F1027, 78F1028, 78F1029, and 78F1030 mirror the data flash area of 00000H to 0FFFFH or 10000H to
1FFFFH, to F0000H to FFFFFH (the data flash area to be mirrored is set by the processor mode control register (PMC)).
By reading data from F0000H to FFFFFH, an instruction that does not have the ES register as an operand can be used,
and thus the contents of the data flash can be read with the shorter code. However, the data flash area is not mirrored to
the SFR, extended SFR, RAM, and use prohibited areas.
See 4.1 Memory Space for the mirror area of each product.
The mirror area can only be read and no instruction can be fetched from this area.
The following show examples.
Example 1 μPD8F1011, 78F1013
Example 2 μPD78F1012, 78F1014
(Flash memory: 96 KB, RAM: 6 KB)
(Flash memory: 128 KB, RAM: 8 KB)
Setting MAA = 0
Setting MAA = 1
FFFFFH
FFFFFH
Special-function register (SFR)
256 bytes
FFF00H
FFEFFH
FFEE0H
FFEDFH
FE700H
FE6FFH
Special-function register (SFR)
256 bytes
FFF00H
FFEFFH
General-purpose register
32 bytes
FFEE0H
FFEDFH
RAM
6 KB
General-purpose register
32 bytes
RAM
8 KB
FDF00H
FDEFFH
Flash memory
(same data as 01000H to 0E6FFH)
Flash memory
(same data as 11000H to 1DEFFH)
F1000H
F0FFFH
F1000H
F0FFFH
Reserved
Reserved
F0800H
F07FFH
F0800H
F07FFH
Special-function register (2nd SFR)
2 KB
Special-function register (2nd SFR)
2 KB
F0000H
EFFFFH
F0000H
EFFFFH
Mirror
Mirror
Reserved
For example, 15432H is mirrored to
Reserved For example, 02345H is mirrored to
F5432H. Data can therefore be read by
MOV A, !5432H, instead of MOV ES,
F2345H. Data can therefore be read by
#01H and MOV A, ES:!5432H.
MOV A, !2345H, instead of MOV ES,
#00H and MOV A, ES:!2345H.
20000H
1FFFFH
Flash memory
1DF00H
1DEFFH
Flash memory
18000H
17FFFH
Flash memory
11000H
10FFFH
0E700H
0E6FFH
Flash memory
Flash memory
01000H
00FFFH
Flash memory
00000H
Remark
00000H
MAA: Bit 0 of the processor mode control register (PMC)
The PMC register is described below.
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• Processor mode control register (PMC)
This register sets the flash memory space for mirroring to area from F0000H to FFFFFH.
The PMC register can be set by a 1-bit or 8-bit memory manipulation instruction.
Reset signal generation sets this register to 00H.
Figure 4-10. Format of Configuration of Processor Mode Control Register (PMC)
Address: FFFFEH After reset: 00H R/W
Symbol
7
6
5
4
3
2
1
<0>
PMC
0
0
0
0
0
0
0
MAA
MAA
Selection of flash memory space for mirroring to area from F0000H to FFFFFH
0
00000H to 0FFFFH is mirrored to F0000H to FFFFFH
1
10000H to 1FFFFH is mirrored to F0000H to FFFFFH Note
Note This setting is prohibited in products other than the μ PD78F1011 to 78F1014, 78F1027, 78F1028, 78F1029,
and 78F1030.
Cautions 1. In products other than the μ PD78F1011 to 78F1014, 78F1027, 78F1028, 78F1029, and 78F1030, be
sure to set bit 0 (MAA) to 0 (default value).
2. Set the PMC register only once during the initial settings prior to operating the DMA controller.
Rewriting the PMC register other than during the initial settings is prohibited.
3. After setting the PMC register, wait for at least one instruction and access the mirror area.
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4.1.3 Internal data memory space
The 78K0R/Kx3-L products incorporate the following RAMs.
Table 4-4. Internal RAM Capacity
Part Number
Internal RAM
μPD78F1000
1024 × 8 bits (FFB00H to FFEFFH)
μPD78F1001, 78F1004, 78F1007
1536 × 8 bits (FF900H to FFEFFH)
μPD78F1002, 78F1005, 78F1008
2048 × 8 bits (FF700H to FFEFFH)
μPD78F1003, 78F1006, 78F1009
3072 × 8 bits (FF300H to FFEFFH)
μPD78F1010
4096 × 8 bits (FEF00H to FFEFFH)
μPD78F1011, 78F1013
6144 × 8 bits (FE700H to FFEFFH)
μPD78F1012, 78F1014
8192 × 8 bits (FDF00H to FFEFFH)
μPD78F1027, 78F1029
10240 × 8 bits (FD700H to FFEFFH)
μPD78F1028, 78F1030
12288 × 8 bits (FCF00H to FFEFFH)
The internal RAM can be used as a data area and a program area where instructions are written and executed. Four
general-purpose register banks consisting of eight 8-bit registers per bank are assigned to the 32-byte area of FFEE0H to
FFEFFH of the internal RAM area. However, instructions cannot be executed by using the general-purpose registers.
The internal RAM is used as a stack memory.
Cautions 1. It is prohibited to use the general-purpose register (FFEE0H to FFEFFH) space for fetching
instructions or as a stack area.
2. While using the self-programming function, the area FFE20H to FFEFFH cannot be used as stack
memory. Furthermore, the areas of FF300H to FF6FFH and FDF00H to FE2FFH also cannot be
used with the μPD78F1003, 78F1006 and 78F1009, and μ PD78F1011 to 78F1014, 78F1027, 78F1028,
78F1029, and 78F1030, respectively.
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4.1.4 Special function register (SFR) area
On-chip peripheral hardware special function registers (SFRs) are allocated in the area FFF00H to FFFFFH (see Table
4-5 in 4.2.4 Special function registers (SFRs)).
Caution Do not access addresses to which SFRs are not assigned.
4.1.5 Extended special function register (2nd SFR: 2nd Special Function Register) area
On-chip peripheral hardware special function registers (2nd SFRs) are allocated in the area F0000H to F07FFH (see
Table 4-6 in 4.2.5 Extended Special function registers (2nd SFRs: 2nd Special Function Registers)).
SFRs other than those in the SFR area (FFF00H to FFFFFH) are allocated to this area. An instruction that accesses
the extended SFR area, however, is 1 byte longer than an instruction that accesses the SFR area.
Caution Do not access addresses to which extended SFRs are not assigned.
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4.1.6 Data memory addressing
Addressing refers to the method of specifying the address of the instruction to be executed next or the address of the
register or memory relevant to the execution of instructions.
Several addressing modes are provided for addressing the memory relevant to the execution of instructions for the
78K0R/Kx3-L, based on operability and other considerations. For areas containing data memory in particular, special
addressing methods designed for the functions of the special function registers (SFR) and general-purpose registers are
available for use. Figures 4-11 to 4-19 show correspondence between data memory and addressing.
Figure 4-11. Correspondence Between Data Memory and Addressing (μPD78F1000)
FFFFFH
FFF20H
FFF1FH
FFF00H
FFEFFH
FFEE0H
FFEDFH
FFE20H
FFE1FH
FFB00H
FFAFFH
Special function register (SFR)
256 bytes
General-purpose register
32 bytes
SFR addressing
Register addressing
Short direct
addressing
RAMNote
1 KB
Reserved
F4000H
F3FFFH
F1000H
F0FFFH
Mirror
12 KB
Reserved
F0800H
F07FFH
Special function register (2nd SFR)
2 KB
F0000H
EFFFFH
Direct addressing
Register indirect addressing
Based addressing
Based indexed addressing
Reserved
04000H
03FFFH
Flash memory
16 KB
00000H
Note
While using the self-programming function, the area FFE20H to FFEFFH cannot be used as stack memory.
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Figure 4-12. Correspondence Between Data Memory and Addressing (μPD78F1001, 78F1004, 78F1007)
FFFFFH
FFF20H
FFF1FH
FFF00H
FFEFFH
FFEE0H
FFEDFH
FFE20H
FFE1FH
FF900H
FF8FFH
Special function register (SFR)
256 bytes
General-purpose register
32 bytes
SFR addressing
Register addressing
Short direct
addressing
RAMNote
1.5 KB
Reserved
F8000H
F7FFFH
Mirror
28 KB
F1000H
F0FFFH
Reserved
F0800H
F07FFH
Special function register (2nd SFR)
2 KB
F0000H
EFFFFH
Direct addressing
Register indirect addressing
Based addressing
Based indexed addressing
Reserved
08000H
07FFFH
Flash memory
32 KB
00000H
Note
While using the self-programming function, the area FFE20H to FFEFFH cannot be used as stack memory.
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Figure 4-13. Correspondence Between Data Memory and Addressing (μPD78F1002, 78F1005, 78F1008)
FFFFFH
FFF20H
FFF1FH
FFF00H
FFEFFH
FFEE0H
FFEDFH
FFE20H
FFE1FH
FF700H
FF6FFH
Special function register (SFR)
256 bytes
General-purpose register
32 bytes
SFR addressing
Register addressing
Short direct
addressing
RAMNote
2 KB
Reserved
FC000H
FBFFFH
Mirror
44 KB
F1000H
F0FFFH
Reserved
F0800H
F07FFH
Special function register (2nd SFR)
2 KB
Direct addressing
Register indirect addressing
F0000H
EFFFFH
Based addressing
Based indexed addressing
Reserved
0C000H
0BFFFH
Flash memory
48 KB
00000H
Note
While using the self-programming function, the area FFE20H to FFEFFH cannot be used as stack memory.
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Figure 4-14. Correspondence Between Data Memory and Addressing (μPD78F1003, 78F1006, 78F1009)
FFFFFH
FFF20H
FFF1FH
FFF00H
FFEFFH
FFEE0H
FFEDFH
Special function register (SFR)
256 bytes
General-purpose register
32 bytes
SFR addressing
Register addressing
Short direct
addressing
RAMNote
3 KB
FFE20H
FFE1FH
FF300H
FF2FFH
Mirror
56.75 KB
F1000H
F0FFFH
Reserved
F0800H
F07FFH
Special function register (2nd SFR)
2 KB
Direct addressing
Register indirect addressing
F0000H
EFFFFH
Based addressing
Based indexed addressing
Reserved
10000H
0FFFFH
Flash memory
64 KB
00000H
Note
While using the self-programming function, the area FFE20H to FFEFFH cannot be used as stack memory.
Furthermore, the areas of FF300H to FF6FFH also cannot be used with the μPD78F1003, 78F1006 and
78F1009.
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Figure 4-15. Correspondence Between Data Memory and Addressing (μPD78F1010)
FFFFFH
FFF20H
FFF1FH
FFF00H
FFEFFH
FFEE0H
FFEDFH
FFE20H
FFE1FH
Special function register (SFR)
SFR addressing
256 bytes
General-purpose register
32 bytes
Register addressing
Short direct
addressing
RAMNote
4 KB
FEF00H
FEEFFH
Mirror
55.75 KB
F1000H
F0FFFH
Reserved
F0800H
F07FFH
Special function register (2nd SFR)
2 KB
Direct addressing
Register indirect addressing
F0000H
EFFFFH
Based addressing
Based indexed addressing
Reserved
10000H
0FFFFH
Flash memory
64 KB
00000H
Note
While using the self-programming function, the area FFE20H to FFEFFH cannot be used as stack memory.
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Figure 4-16. Correspondence Between Data Memory and Addressing (μPD78F1011, 78F1013)
FFFFFH
FFF20H
FFF1FH
FFF00H
FFEFFH
FFEE0H
FFEDFH
FFE20H
FFE1FH
Special function register (SFR)
256 bytes
General-purpose register
32 bytes
SFR addressing
Register addressing
Short direct
addressing
RAMNote
6 KB
FE700H
FE6FFH
Mirror
53.75 KB
F1000H
F0FFFH
F0800H
F07FFH
Reserved
Special function register (2nd SFR)
2 KB
Direct addressing
Register indirect addressing
F0000H
EFFFFH
Based addressing
Based indexed addressing
Reserved
18000H
17FFFH
Flash memory
96 KB
00000H
Note
While using the self-programming function, the area FFE20H to FFEFFH cannot be used as stack memory.
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Figure 4-17. Correspondence Between Data Memory and Addressing (μPD78F1012, 78F1014)
FFFFFH
FFF20H
FFF1FH
FFF00H
FFEFFH
FFEE0H
FFEDFH
FFE20H
FFE1FH
Special function register (SFR)
256 bytes
General-purpose register
32 bytes
SFR addressing
Register addressing
Short direct
addressing
RAMNote
8 KB
FDF00H
FDEFFH
Mirror
51.75 KB
F1000H
F0FFFH
F0800H
F07FFH
Reserved
Special function register (2nd SFR)
2 KB
Direct addressing
Register indirect addressing
F0000H
EFFFFH
Based addressing
Based indexed addressing
Reserved
20000H
1FFFFH
Flash memory
128 KB
00000H
Note
While using the self-programming function, the area FFE20H to FFEFFH cannot be used as stack memory.
Furthermore, the areas of FDF00H to FE2FFH also cannot be used with the μPD78F1012 and 78F1014.
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Figure 4-18. Correspondence Between Data Memory and Addressing (μPD78F1027, 78F1029)
FFFFFH
FFF20H
FFF1FH
FFF00H
FFEFFH
FFEE0H
FFEDFH
FFE20H
FFE1FH
Special function register (SFR)
256 bytes
General-purpose register
32 bytes
SFR addressing
Register addressing
Short direct
addressing
RAMNote
10 KB
FD700H
FD6FFH
Mirror area
49.75 KB
F1000H
F0FFFH
Reserved
F0800H
F07FFH
Special function register (2nd SFR)
2 KB
Direct addressing
F0000H
EFFFFH
Register indirect addressing
Based addressing
Based indexed addressing
Reserved
30000H
2FFFFH
Flash memory 192 KB
00000H
Note While using the self-programming function, the area FFE20H to FFEFFH cannot be used as stack memory.
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Figure 4-19. Correspondence Between Data Memory and Addressing (μPD78F1028, 78F1030)
FFFFFH
FFF20H
FFF1FH
FFF00H
FFEFFH
FFEE0H
FFEDFH
FFE20H
FFE1FH
FCF00H
FCEFFH
Special function register (SFR)
256 bytes
General-purpose register
32 bytes
SFR addressing
Register addressing
Short direct
addressing
RAMNote
12 KB
Mirror area
47.75 KB
F1000H
F0FFFH
Reserved
F0800H
F07FFH
Special function register (2nd SFR)
2 KB
F0000H
EFFFFH
Direct addressing
Register indirect addressing
Based addressing
Based indexed addressing
Reserved
40000H
3FFFFH
Flash memory
256 KB
00000H
Note
While using the self-programming function, the area FFE20H to FFEFFH cannot be used as stack memory.
Furthermore, the areas of FCF00H to FD2FFH also cannot be used with the μPD78F1028 and 78F1030.
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4.2 Processor Registers
The 78K0R/Kx3-L products incorporate the following processor registers.
4.2.1 Control registers
The control registers control the program sequence, statuses and stack memory. The control registers consist of a
program counter (PC), a program status word (PSW) and a stack pointer (SP).
(1) Program counter (PC)
The program counter is a 20-bit register that holds the address information of the next program to be executed.
In normal operation, PC is automatically incremented according to the number of bytes of the instruction to be fetched.
When a branch instruction is executed, immediate data and register contents are set.
Reset signal generation sets the reset vector table values at addresses 0000H and 0001H to the program counter.
Figure 4-20. Format of Program Counter
19
0
PC
(2) Program status word (PSW)
The program status word is an 8-bit register consisting of various flags set/reset by instruction execution.
Program status word contents are stored in the stack area upon vectored interrupt request is acknowledged or PUSH
PSW instruction execution and are restored upon execution of the RETB, RETI and POP PSW instructions. Reset
signal generation sets the PSW register to 06H.
Figure 4-21. Format of Program Status Word
7
PSW
IE
0
Z
RBS1
AC
RBS0
ISP1
ISP0
CY
(a) Interrupt enable flag (IE)
This flag controls the interrupt request acknowledge operations of the CPU.
When 0, the IE flag is set to the interrupt disabled (DI) state, and all maskable interrupt requests are disabled.
When 1, the IE flag is set to the interrupt enabled (EI) state and interrupt request acknowledgment is controlled
with an in-service priority flag (ISP1, ISP0), an interrupt mask flag for various interrupt sources, and a priority
specification flag.
The IE flag is reset (0) upon DI instruction execution or interrupt acknowledgment and is set (1) upon EI
instruction execution.
(b) Zero flag (Z)
When the operation result is zero, this flag is set (1). It is reset (0) in all other cases.
(c) Register bank select flags (RBS0, RBS1)
These are 2-bit flags to select one of the four register banks.
In these flags, the 2-bit information that indicates the register bank selected by SEL RBn instruction execution is
stored.
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(d) Auxiliary carry flag (AC)
If the operation result has a carry from bit 3 or a borrow at bit 3, this flag is set (1). It is reset (0) in all other cases.
(e) In-service priority flags (ISP1, ISP0)
This flag manages the priority of acknowledgeable maskable vectored interrupts. Vectored interrupt requests
specified lower than the value of ISP0 and ISP1 flags by the priority specification flag registers (PRn0L, PRn0H,
PRn1L, PRn1H, PRn2L, PRn2H) (see 18.3 (3)) can not be acknowledged. Actual request acknowledgment is
controlled by the interrupt enable flag (IE).
Remark n = 0, 1
(f) Carry flag (CY)
This flag stores overflow and underflow upon add/subtract instruction execution. It stores the shift-out value upon
rotate instruction execution and functions as a bit accumulator during bit operation instruction execution.
(3) Stack pointer (SP)
This is a 16-bit register to hold the start address of the memory stack area. Only the internal RAM area can be set as
the stack area.
Figure 4-22. Format of Stack Pointer
15
0
SP SP15 SP14 SP13 SP12 SP11 SP10 SP9 SP8 SP7 SP6 SP5 SP4 SP3 SP2 SP1 SP0
The SP is decremented ahead of write (save) to the stack memory and is incremented after read (restored) from the
stack memory.
Each stack operation saves data as shown in Figure 4-19.
Caution 1. Since reset signal generation makes the SP contents undefined, be sure to initialize the SP before
using the stack.
2. It is prohibited to use the general-purpose register (FFEE0H to FFEFFH) space as a stack area.
3. While using the self-programming function, the area FFE20H to FFEFFH cannot be used as stack
memory. Furthermore, the areas of FF300H to FF6FFH and FDF00H to FE2FFH also cannot be
used with the μPD78F1003, 78F1006 and 78F1009, and μPD78F1012 and 78F1014, 78F1027,
78F1028, 78F1029, and 78F1030, respectively.
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Figure 4-23. Data to Be Saved to Stack Memory
PUSH PSW instruction
PUSH rp instruction
SP←SP−2
↑
SP−2
↑
SP−1
↑
SP →
Register pair lower
Register pair higher
CALL, CALLT instructions
(4-byte stack)
SP←SP−4
↑
SP−4
↑
SP−3
↑
SP−2
↑
SP−1
↑
SP →
PC7 to PC0
PC15 to PC8
PC19 to PC16
00H
SP←SP−2
↑
SP−2
↑
SP−1
↑
SP →
00H
PSW
Interrupt, BRK instruction
(4-byte stack)
SP←SP−4
↑
SP−4
↑
SP−3
↑
SP−2
↑
SP−1
↑
SP →
PC7 to PC0
PC15 to PC8
PC19 to PC16
PSW
4.2.2 General-purpose registers
General-purpose registers are mapped at particular addresses (FFEE0H to FFEFFH) of the data memory. The generalpurpose registers consists of 4 banks, each bank consisting of eight 8-bit registers (X, A, C, B, E, D, L, and H).
Each register can be used as an 8-bit register, and two 8-bit registers can also be used in a pair as a 16-bit register (AX,
BC, DE, and HL).
These registers can be described in terms of function names (X, A, C, B, E, D, L, H, AX, BC, DE, and HL) and absolute
names (R0 to R7 and RP0 to RP3).
Register banks to be used for instruction execution are set by the CPU control instruction (SEL RBn). Because of the 4register bank configuration, an efficient program can be created by switching between a register for normal processing and
a register for interrupts for each bank.
Cautions 1. It is prohibited to use the general-purpose register (FFEE0H to FFEFFH) space for fetching
instructions or as a stack area.
2. While using the self-programming function, the area FFE20H to FFEFFH cannot be used as stack
memory. Furthermore, the areas of FF300H to FF6FFH and FDF00H to FE2FFH also cannot be
used with the μPD78F1003, 78F1006 and 78F1009, and μPD78F1012, 78F1014, 78F1027, 78F1028,
78F1029, and 78F1030, respectively.
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Figure 4-24. Configuration of General-Purpose Registers
(a) Function name
16-bit processing
8-bit processing
FFEFFH
H
Register bank 0
HL
L
FFEF8H
D
Register bank 1
DE
E
FFEF0H
B
BC
Register bank 2
C
FFEE8H
A
AX
Register bank 3
X
FFEE0H
15
0
7
0
(b) Absolute name
16-bit processing
8-bit processing
FFEFFH
R7
Register bank 0
RP3
R6
FFEF8H
R5
Register bank 1
RP2
R4
FFEF0H
R3
RP1
Register bank 2
R2
FFEE8H
R1
RP0
Register bank 3
R0
FFEE0H
15
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4.2.3 ES and CS registers
The ES register is used for data access and the CS register is used to specify the higher address when a branch
instruction is executed.
The default value of the ES register after reset is 0FH, and that of the CS register is 00H.
Figure 4-25. Configuration of ES and CS Registers
ES
CS
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6
5
4
3
2
1
0
0
0
0
0
ES3
ES2
ES1
ES0
7
6
5
4
3
2
1
0
0
0
0
0
CS3
CP2
CP1
CP0
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4.2.4 Special function registers (SFRs)
Unlike a general-purpose register, each SFR has a special function.
SFRs are allocated to the FFF00H to FFFFFH area.
SFRs can be manipulated like general-purpose registers, using operation, transfer, and bit manipulation instructions.
The manipulable bit units, 1, 8, and 16, depend on the SFR type.
Each manipulation bit unit can be specified as follows.
• 1-bit manipulation
Describe the symbol reserved by the assembler for the 1-bit manipulation instruction operand (sfr.bit).
This
manipulation can also be specified with an address.
• 8-bit manipulation
Describe the symbol reserved by the assembler for the 8-bit manipulation instruction operand (sfr).
This
manipulation can also be specified with an address.
• 16-bit manipulation
Describe the symbol reserved by the assembler for the 16-bit manipulation instruction operand (sfrp).
When
specifying an address, describe an even address.
Table 4-5 gives a list of the SFRs. The meanings of items in the table are as follows.
• Symbol
Symbol indicating the address of a special function register. It is a reserved word in the RA78K0R, and is defined as
an sfr variable using the #pragma sfr directive in the CC78K0R. When using the RA78K0R, ID78K0R-QB, and SM+
for 78K0R, symbols can be written as an instruction operand.
• R/W
Indicates whether the corresponding SFR can be read or written.
R/W: Read/write enable
R: Read only
W: Write only
• Manipulable bit units
“√” indicates the manipulable bit unit (1, 8, or 16). “−” indicates a bit unit for which manipulation is not possible.
• After reset
Indicates each register status upon reset signal generation.
Caution Do not access addresses to which extended SFRs are not assigned.
Remark
For extended SFRs (2nd SFRs), see 4.2.5 Extended special function registers (2nd SFRs: 2nd Special
Function Registers).
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Table 4-5. SFR List (1/6)
KE3-L
KF3-L
KG3-L
After Reset
KD3-L
Manipulable Bit Range
KC3-L (48-pin)
R/W
KC3-L (44-pin)
Symbol
KC3-L (40-pin)
Address Special Function Register (SFR) Name
FFF00H Port register 0
P0
R/W
√
√
−
00H
−
−
−
√
√
√
√
FFF01H Port register 1
P1
R/W
√
√
−
00H
√
√
√
√
√
√
√
FFF02H Port register 2
P2
R/W
√
√
−
00H
√
√
√
√
√
√
√
FFF03H Port register 3
P3
R/W
√
√
−
00H
√
√
√
√
√
√
√
FFF04H Port register 4
P4
R/W
√
√
−
00H
√
√
√
√
√
√
√
FFF05H Port register 5
P5
R/W
√
√
−
00H
√
√
√
√
√
√
√
FFF06H Port register 6
P6
R/W
√
√
−
00H
−
−
√
√
√
√
√
FFF07H Port register 7
P7
R/W
√
√
−
00H
√
√
√
√
√
√
√
FFF08H Port register 8
P8
R/W
√
√
−
00H
√
√
√
√
√
−
√
FFF09H Port register 9
P9
R/W
√
√
−
00H
−
−
−
−
−
√
√
FFF0BH Port register 11
P11
R/W
√
√
−
00H
−
−
−
−
−
√
√
FFF0CH Port register 12
P12
R/W
√
√
−
Undefined
√
√
√
√
√
√
√
FFF0DH Port register 13
P13
R/W
√
√
−
00H
−
−
−
−
−
√
√
FFF0EH Port register 14
P14
R/W
√
√
−
00H
−
−
√
√
√
√
√
FFF0FH Port register 15
P15
R/W
√
√
−
00H
√
√
√
√
√
√
√
FFF10H Serial data register 00
TXD0/ SDR00
SIO00
R/W
−
√
√
0000H
√
√
√
√
√
√
√
−
−
√
√
√
√
√
√
√
−
√
√
√
√
√
√
√
√
−
−
√
√
√
√
√
√
√
−
√
−
−
−
−
−
√
√
−
−
−
−
−
−
−
√
√
−
√
−
−
−
−
−
√
√
−
−
−
−
−
−
−
√
√
−
FFF11H
FFF12H Serial data register 01
RXD0/ SDR01
SIO01
R/W
−
FFF13H
FFF14H Serial data register 12
TXD3 SDR12
R/W
−
FFF15H
FFF16H Serial data register 13
RXD3 SDR13
R/W
−
FFF17H
1-bit
8-bit
16-bit
√
√
√
0000H
0000H
0000H
TDR00
R/W
−
−
√
0000H
√
√
√
√
√
√
√
TDR01
R/W
−
−
√
0000H
√
√
√
√
√
√
√
FFF1EH 10-bit A/D conversion result
register
ADCR
R
−
−
√
0000H
√
√
√
√
√
√
√
FFF1FH
ADCRH
R
−
√
−
00H
√
√
√
√
√
√
√
FFF18H Timer data register 00
FFF19H
FFF1AH Timer data register 01
FFF1BH
8-bit A/D conversion
result register
FFF20H Port mode register 0
PM0
R/W
√
√
−
FFH
−
−
−
√
√
√
√
FFF21H Port mode register 1
PM1
R/W
√
√
−
FFH
√
√
√
√
√
√
√
FFF22H Port mode register 2
PM2
R/W
√
√
−
FFH
√
√
√
√
√
√
√
FFF23H Port mode register 3
PM3
R/W
√
√
−
FFH
√
√
√
√
√
√
√
FFF24H Port mode register 4
PM4
R/W
√
√
−
FFH
√
√
√
√
√
√
√
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Table 4-5. SFR List (2/6)
KE3-L
KF3-L
KG3-L
After Reset
KD3-L
Manipulable Bit Range
KC3-L (48-pin)
R/W
KC3-L (44-pin)
Symbol
KC3-L (40-pin)
Address Special Function Register (SFR) Name
FFF25H Port mode register 5
PM5
R/W
√
√
−
FFH
√
√
√
√
√
√
√
FFF26H Port mode register 6
PM6
R/W
√
√
−
FFH
−
−
√
√
√
√
√
FFF27H Port mode register 7
PM7
R/W
√
√
−
FFH
√
√
√
√
√
√
√
FFF28H Port mode register 8
PM8
R/W
√
√
−
FFH
√
√
√
√
√
−
√
FFF29H Port mode register 9
PM9
R/W
√
√
−
FFH
−
−
−
−
−
√
√
FFF2BH Port mode register 11
PM11
R/W
√
√
−
FFH
−
−
−
−
−
√
√
FFF2CH Port mode register 12
PM12
R/W
√
√
−
FFH
√
√
√
√
√
√
√
1-bit
8-bit
16-bit
FFF2DH Port mode register 13
PM13
R/W
√
√
−
FEH
−
−
−
−
−
−
√
FFF2EH Port mode register 14
PM14
R/W
√
√
−
FFH
−
−
−
−
√
√
√
FFF2FH Port mode register 15
PM15
R/W
√
√
−
FFH
√
√
√
√
√
√
√
FFF30H A/D converter mode register
ADM
R/W
√
√
−
00H
√
√
√
√
√
√
√
FFF31H Analog input channel
specification register
ADS
R/W
√
√
−
√
√
√
√
√
√
√
FFF37H Key return mode register
KRM
R/W
√
√
−
00H
√
√
√
√
√
√
√
FFF38H External interrupt rising edge
EGP0
R/W
√
√
−
00H
√
√
√
√
√
√
√
EGN0
R/W
√
√
−
00H
√
√
√
√
√
√
√
EGP1
R/W
√
√
−
00H
−
−
−
−
−
√
√
EGN1
R/W
√
√
−
00H
−
−
−
−
−
√
√
FFF3CH Input switch control register
ISC
R/W
√
√
−
00H
√
√
√
√
√
√
√
FFF3EH Timer input select register 0
TIS0
R/W
√
√
−
00H
√
√
√
√
√
√
√
−
−
−
−
√
√
√
√
√
√
√
√
00H
enable register 0
FFF39H External interrupt falling edge
enable register 0
FFF3AH External interrupt rising edge
enable register 1
FFF3BH External interrupt falling edge
enable register 1
FFF3FH Timer input select register 1
FFF44H Serial data register 02
TIS1
R/W
√
√
−
00H
−
TXD1/ SDR02
R/W
−
√
√
0000H
√
−
−
√
√
√
√
√
√
√
−
√
0000H
√
√
√
√
√
√
√
−
−
√
√
√
√
√
√
√
−
√
−
−
−
−
−
√
√
−
−
−
−
−
−
−
√
√
−
√
−
−
−
−
−
√
√
−
−
−
−
−
−
−
√
√
−
√
−
−
−
−
−
Note Note
−
−
−
−
−
−
−
Note Note
SIO10
FFF45H
FFF46H Serial data register 03
FFF47H
FFF48H Serial data register 10
−
RXD1 SDR03
R/W
−
TXD2/ SDR10
R/W
√
√
0000H
SIO20
FFF49H
FFF4AH Serial data register 11
FFF4BH
FFF4CH Serial data register 20
−
RXD2 SDR11
R/W
−
SIO40/ SDR20
R/W
√
√
0000H
0000H
TxD4
FFF4DH
−
Note Those are only mounted in the 78K0R/KF3-L (μ PD78F1027 and 78F1028) and the 78K0R/KG3-L (μ PD78F1029 and
78F1030).
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Table 4-5. SFR List (3/6)
−
√
√
0000H
−
−
−
−
−
−
FFF4FH
Note Note
1
RxD4
−
KG3-L
16-bit
KF3-L
8-bit
KE3-L
1-bit
After Reset
KD3-L
SIO41/ SDR21 R/W
Manipulable Bit Range
KC3-L (48-pin)
R/W
KC3-L (44-pin)
FFF4EH Serial data register 21
Symbol
KC3-L (40 pin)
Address Special Function Register (SFR) Name
1
−
−
−
−
−
−
1
1
−
√
√
√
√
√
Note Note
FFF50H IICA shift register
IICA
R/W
−
√
−
00H
−
FFF51H IICA status register
IICS
R
√
√
−
00H
−
−
√
√
√
√
√
FFF52H IICA flag register
IICF
R/W
√
√
−
00H
−
−
√
√
√
√
√
√
√
√
√
√
√
FFF64H Timer data register 02
TDR02
R/W
−
−
√
0000H
√
TDR03
R/W
−
−
√
0000H
√
√
√
√
√
√
√
TDR04
R/W
−
−
√
0000H
√
√
√
√
√
√
√
TDR05
R/W
−
−
√
0000H
√
√
√
√
√
√
√
TDR06
R/W
−
−
√
0000H
√
√
√
√
√
√
√
TDR07
R/W
−
−
√
0000H
√
√
√
√
√
√
√
TDR10
R/W
−
−
√
0000H
−
−
−
−
−
√
√
TDR11
R/W
−
−
√
0000H
−
−
−
−
−
√
√
TDR12
R/W
−
−
√
0000H
−
−
−
−
−
√
√
TDR13
R/W
−
−
√
0000H
−
−
−
−
−
√
√
RSUBC
R
−
−
√
0000H
−
√
√
√
√
√
√
FFF65H
FFF66H Timer data register 03
FFF67H
FFF68H Timer data register 04
FFF69H
FFF6AH Timer data register 05
FFF6BH
FFF6CH Timer data register 06
FFF6DH
FFF6EH Timer data register 07
FFF6FH
FFF70H Timer data register 10
FFF71H
FFF72H Timer data register 11
FFF73H
FFF74H Timer data register 12
FFF75H
FFF76H Timer data register 13
FFF77H
FFF90H Sub-count register
FFF91H
FFF92H Second count register
SEC
R/W
−
√
−
00H
−
√
√
√
√
√
√
FFF93H Minute count register
MIN
R/W
−
√
−
00H
−
√
√
√
√
√
√
−
√
√
√
√
√
√
FFF94H Hour count register
HOUR
R/W
−
√
−
FFF95H Week count register
WEEK
R/W
−
√
−
00H
−
√
√
√
√
√
√
FFF96H Day count register
DAY
R/W
−
√
−
01H
−
√
√
√
√
√
√
01H
−
√
√
√
√
√
√
FFF97H Month count register
Notes 1.
MONTH
R/W
−
√
−
Note 2
12H
Those are only mounted in the 78K0R/KF3-L (μ PD78F1027 and 78F1028) and the 78K0R/KG3-L (μ
PD78F1029 and 78F1030).
2.
The value of this register is 00H if the AMPM bit (bit 3 of real-time counter control register 0 (RTCC0)) is set to
1 after reset.
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CHAPTER 4 CPU ARCHITECTURE
Table 4-5. SFR List (4/6)
KE3-L
KF3-L
KG3-L
After Reset
KD3-L
Manipulable Bit Range
KC3-L (48-pin)
R/W
KC3-L (44-pin)
Symbol
KC3-L (40-pin)
Address Special Function Register (SFR) Name
FFF98H Year count register
YEAR
R/W
−
√
−
00H
−
√
√
√
√
√
√
FFF99H Watch error correction register
SUBCUD
R/W
−
√
−
00H
−
√
√
√
√
√
√
FFF9AH Alarm minute register
ALARMWM
R/W
−
√
−
00H
−
√
√
√
√
√
√
FFF9BH Alarm hour register
ALARMWH
R/W
−
√
−
12H
−
√
√
√
√
√
√
√
√
√
√
√
√
1-bit
8-bit
16-bit
FFF9CH Alarm week register
ALARMWW
R/W
−
√
−
00H
−
FFF9DH Real-time counter control
RTCC0
R/W
√
√
−
00H
−
√
√
√
√
√
√
RTCC1
R/W
√
√
−
00H
−
√
√
√
√
√
√
RTCC2
R/W
√
√
−
00H
−
√
√
√
√
√
√
CMC
R/W
−
√
−
00H
√
√
√
√
√
√
√
CSC
R/W
√
√
−
C0H
√
√
√
√
√
√
√
OSTC
R
√
√
−
00H
√
√
√
√
√
√
√
OSTS
R/W
−
√
−
07H
√
√
√
√
√
√
√
CKC
R/W
√
√
−
09H
√
√
√
√
√
√
√
−
−
√
√
√
√
√
−
−
−
−
√
√
√
√
√
√
√
√
√
√
register 0
FFF9EH Real-time counter control
register 1
FFF9FH Real-time counter control
register 2
FFFA0H Clock operation mode control
register
FFFA1H Clock operation status control
register
FFFA2H Oscillation stabilization time
counter status register
FFFA3H Oscillation stabilization time
select register
FFFA4H System clock control register
FFFA5H Clock output select register 0
CKS0
R/W
√
√
−
00H
FFFA6H Clock output select register 1
CKS1
R/W
√
√
−
00H
R
−
√
−
FFFA8H Reset control flag register
RESF
Undefined
Note 1
Note 2
√
√
√
√
√
√
√
Note 3
√
√
√
√
√
√
√
√
√
√
√
√
√
√
FFFA9H Low-voltage detection register
LVIM
R/W
√
√
−
00H
FFFAAH Low-voltage detection level
LVIS
R/W
√
√
−
0EH
WDTE
R/W
−
√
−
1A/9A
select register
FFFABH Watchdog timer enable register
Note 4
Notes 1. The reset value of the RESF register varies depending on the reset source.
2. The reset value of the LVIM register varies depending on the reset source and the setting of the option byte.
3. The reset value of the LVIS register varies depending on the reset source.
4. The reset value of the WDTE register is determined by the setting of the option byte.
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CHAPTER 4 CPU ARCHITECTURE
Table 4-5. SFR List (5/6)
KE3-L
KF3-L
KG3-L
After Reset
KD3-L
Manipulable Bit Range
KC3-L (48-pin)
R/W
KC3-L (44-pin)
Symbol
KC3-L (40-pin)
Address Special Function Register (SFR) Name
FFFB0H DMA SFR address register 0
DSA0
R/W
−
√
−
00H
√
√
√
√
√
√
√
FFFB1H DMA SFR address register 1
DSA1
R/W
−
√
−
00H
√
√
√
√
√
√
√
R/W
−
√
√
00H
√
√
√
√
√
√
√
FFFB3H DMA RAM address register 0H DRA0H
R/W
−
√
00H
√
√
√
√
√
√
√
FFFB4H DMA RAM address register 1L
R/W
−
√
00H
√
√
√
√
√
√
√
FFFB5H DMA RAM address register 1H DRA1H
R/W
−
√
00H
√
√
√
√
√
√
√
FFFB6H DMA byte count register 0L
DBC0L DBC0
R/W
−
√
00H
√
√
√
√
√
√
√
FFFB7H DMA byte count register 0H
DBC0H
R/W
−
√
00H
√
√
√
√
√
√
√
FFFB8H DMA byte count register 1L
DBC1L DBC1
R/W
−
√
00H
√
√
√
√
√
√
√
FFFB9H DMA byte count register 1H
DBC1H
R/W
−
√
00H
√
√
√
√
√
√
√
FFFBAH DMA mode control register 0
DMC0
R/W
√
√
00H
√
√
√
√
√
√
√
√
√
√
√
√
√
√
√
√
√
√
√
FFFB2H DMA RAM address register 0L
DRA0L DRA0
DRA1L DRA1
1-bit
8-bit
16-bit
√
√
√
−
FFFBBH DMA mode control register 1
DMC1
R/W
√
√
−
00H
√
FFFBCH DMA operation control register 0
DRC0
R/W
√
√
−
00H
√
FFFBDH DMA operation control register 1
DRC1
R/W
√
√
−
00H
√
√
√
√
√
√
√
√
√
√
√
√
√
√
√
√
√
√
√
FFFBEH Back ground event control
BECTL
R/W
√
√
−
00H
√
−
−
−
−
Undefined
√
−
−
−
−
Undefined
√
√
√
√
√
√
√
√
√
√
√
√
√
register
FFFC0H
−
FFFC2H
−
FFFC4H
−
PFCMD
PFS
Note
Note
FLPMC
FFFD0H Interrupt request flag register 2L IF2L
Note
IF2
FFFD1H Interrupt request flag register 2H IF2H
FFFD4H Interrupt mask flag register 2L
MK2L
FFFD5H Interrupt mask flag register 2H
MK2H
MK2
FFFD8H Priority specification flag register PR02L PR02
−
−
−
−
Undefined
√
R/W
√
√
√
00H
√
√
√
√
√
√
√
R/W
√
√
00H
−
−
−
−
−
√
√
R/W
√
√
R/W
√
√
R/W
√
√
R/W
√
√
R/W
√
√
R/W
√
√
R/W
√
√
√
√
FFH
√
√
√
√
√
√
√
FFH
−
−
−
−
−
√
√
FFH
√
√
√
√
√
√
√
FFH
−
−
−
−
−
√
√
FFH
√
√
√
√
√
√
√
FFH
−
−
−
−
−
√
√
02L
FFFD9H Priority specification flag register PR02H
02H
FFFDCH Priority specification flag register PR12L PR12
√
12L
FFFDDH Priority specification flag register PR12H
12H
FFFE0H Interrupt request flag register 0L IF0L
IF0
FFFE1H Interrupt request flag register 0H IF0H
FFFE2H Interrupt request flag register 1L IF1L
IF1
FFFE3H Interrupt request flag register 1H IF1H
FFFE4H Interrupt mask flag register 0L
MK0L
FFFE5H Interrupt mask flag register 0H
MK0H
Note
MK0
R/W
√
√
R/W
√
√
R/W
√
√
R/W
√
√
R/W
√
√
√
√
√
00H
√
√
√
√
√
√
√
00H
√
√
√
√
√
√
√
00H
√
√
√
√
√
√
√
00H
√
√
√
√
√
√
√
FFH
√
√
√
√
√
√
√
FFH
√
√
√
√
√
√
√
Do not directly operate this SFR, because it is to be used in the self programming library.
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CHAPTER 4 CPU ARCHITECTURE
Table 4-5. SFR List (6/6)
16-bit
R/W
√
√
√
R/W
√
√
R/W
√
√
R/W
√
√
R/W
√
√
R/W
√
√
R/W
√
√
R/W
√
√
R/W
√
√
R/W
√
√
√
KG3-L
FFFE8H Priority specification flag register PR00L PR00
8-bit
KF3-L
MK1H
1-bit
After Reset
KE3-L
MK1
Manipulable Bit Range
KD3-L
FFFE7H Interrupt mask flag register 1H
MK1L
R/W
KC3-L (48-pin)
FFFE6H Interrupt mask flag register 1L
Symbol
KC3-L (44-pin)
Address Special Function Register (SFR) Name
FFH
√
√
√
√
√
√
FFH
√
√
√
√
√
√
FFH
√
√
√
√
√
√
FFH
√
√
√
√
√
√
FFH
√
√
√
√
√
√
FFH
√
√
√
√
√
√
FFH
√
√
√
√
√
√
FFH
√
√
√
√
√
√
FFH
√
√
√
√
√
√
FFH
√
√
√
√
√
√
00L
FFFE9H Priority specification flag register PR00H
00H
FFFEAH Priority specification flag register PR01L PR01
√
01L
FFFEBH Priority specification flag register PR01H
01H
FFFECH Priority specification flag register PR10L PR10
√
10L
FFFEDH Priority specification flag register PR10H
10H
FFFEEH Priority specification flag register PR11L PR11
√
11L
FFFEFH Priority specification flag register PR11H
11H
FFFF0H Multiplication/division data register
FFFF1H A (L)
MDAL/MULA
R/W
−
−
√
0000H
√
√
√
√
√
√
FFFF2H Multiplication/division data register
FFFF3H A (H)
MDAH/MULB
R/W
−
−
√
0000H
√
√
√
√
√
√
FFFF4H Multiplication/division data register
FFFF5H B (H)
MDBH/MULOH R/W
−
−
√
0000H
√
√
√
√
√
√
FFFF6H Multiplication/division data register
FFFF7H B (L)
MDBL/MULOL
R/W
−
−
√
0000H
√
√
√
√
√
√
R/W
√
√
−
00H
√
√
√
√
√
√
FFFFEH Processor mode control register PMC
Remark For extended SFRs (2nd SFRs), see Table 4-6 Extended SFR (2nd SFR) List.
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CHAPTER 4 CPU ARCHITECTURE
4.2.5 Extended special function registers (2nd SFRs: 2nd Special Function Registers)
Unlike a general-purpose register, each extended SFR (2nd SFR) has a special function.
Extended SFRs are allocated to the F0000H to F07FFH area. SFRs other than those in the SFR area (FFF00H to
FFFFFH) are allocated to this area. An instruction that accesses the extended SFR area, however, is 1 byte longer than
an instruction that accesses the SFR area.
Extended SFRs can be manipulated like general-purpose registers, using operation, transfer, and bit manipulation
instructions. The manipulable bit units, 1, 8, and 16, depend on the SFR type.
Each manipulation bit unit can be specified as follows.
• 1-bit manipulation
Describe the symbol reserved by the assembler for the 1-bit manipulation instruction operand (!addr16.bit). This
manipulation can also be specified with an address.
• 8-bit manipulation
Describe the symbol reserved by the assembler for the 8-bit manipulation instruction operand (!addr16). This
manipulation can also be specified with an address.
• 16-bit manipulation
Describe the symbol reserved by the assembler for the 16-bit manipulation instruction operand (!addr16). When
specifying an address, describe an even address.
Table 4-6 gives a list of the extended SFRs. The meanings of items in the table are as follows.
• Symbol
Symbol indicating the address of an extended SFR. It is a reserved word in the RA78K0R, and is defined as an sfr
variable using the #pragma sfr directive in the CC78K0R. When using the RA78K0R, ID78K0R-QB, and SM+ for
78K0R, symbols can be written as an instruction operand.
• R/W
Indicates whether the corresponding extended SFR can be read or written.
R/W: Read/write enable
R:
Read only
W:
Write only
• Manipulable bit units
“√” indicates the manipulable bit unit (1, 8, or 16). “−” indicates a bit unit for which manipulation is not possible.
• After reset
Indicates each register status upon reset signal generation.
Caution Do not access addresses to which extended SFRs are not assigned.
Remark
For SFRs in the SFR area, see 4.2.4 Special function registers (SFRs).
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CHAPTER 4 CPU ARCHITECTURE
Table 4-6. Extended SFR (2nd SFR) List (1/8)
KE3-L
KF3-L
KG3-L
After Reset
KD3-L
Manipulable Bit Range
KC3-L (48-pin)
R/W
KC3-L (44-pin)
Symbol
KC3-L (40-pin)
Address Special Function Register (SFR) Name
F0017H
A/D port configuration register
R/W
−
√
−
10H
√
√
√
√
√
√
√
F0030H
Pull-up resistor option register 0 PU0
R/W
√
√
−
00H
−
−
−
√
√
√
√
F0031H
Pull-up resistor option register 1 PU1
R/W
√
√
−
00H
√
√
√
√
√
√
√
F0033H
Pull-up resistor option register 3 PU3
R/W
√
√
−
00H
√
√
√
√
√
√
√
F0034H
Pull-up resistor option register 4 PU4
R/W
√
√
−
00H
√
√
√
√
√
√
√
F0035H
Pull-up resistor option register 5 PU5
R/W
√
√
−
00H
√
√
√
√
√
√
√
F0036H
Pull-up resistor option register 6 PU6
R/W
√
√
−
00H
−
−
−
−
−
√
√
F0037H
Pull-up resistor option register 7 PU7
R/W
√
√
−
00H
√
√
√
√
√
√
√
F0038H
Pull-up resistor option register 8 PU8
R/W
√
√
−
00H
−
−
−
−
−
−
√
F0039H
Pull-up resistor option register 9 PU9
R/W
√
√
−
00H
−
−
−
−
−
√
√
ADPC
1-bit
8-bit
16-bit
F003BH Pull-up resistor option register
11
PU11
R/W
√
√
−
00H
−
−
−
−
−
√
√
F003CH Pull-up resistor option register
12
PU12
R/W
√
√
−
00H
√
√
√
√
√
√
√
F003DH Pull-up resistor option register
13
PU13
R/W
√
√
−
00H
−
−
−
−
−
−
√
F003EH Pull-up resistor option register
14
PU14
R/W
√
√
−
00H
−
−
−
−
√
√
√
F0040H
Port input mode register 0
PIM0
R/W
√
√
−
00H
−
−
−
−
−
√
√
F0041H
Port input mode register 1
PIM1
R/W
√
√
−
00H
−
−
−
−
−
√
√
F0043H
Port input mode register 3
PIM3
R/W
√
√
−
00H
√
√
√
√
√
−
−
F0047H
Port input mode register 7
PIM7
R/W
√
√
−
00H
√
√
√
√
√
−
−
F0048H
Port input mode register 8
PIM8
R/W
√
√
−
00H
√
√
√
√
√
−
−
F004EH Port input mode register 14
PIM14
R/W
√
√
−
00H
−
−
−
−
−
√
√
F0050H
Port output mode register 0
POM0
R/W
√
√
−
00H
−
−
−
−
−
√
√
F0051H
Port output mode register 1
POM1
R/W
√
√
−
00H
−
−
−
−
−
√
√
F0053H
Port output mode register 0
POM3
R/W
√
√
−
00H
√
√
√
√
√
−
−
F0057H
Port output mode register 1
POM7
R/W
√
√
−
00H
√
√
√
√
√
−
−
F005EH Port output mode register 14
POM14
R/W
√
√
−
00H
−
−
−
−
−
√
√
F0060H
Noise filter enable register 0
NFEN0
R/W
√
√
−
00H
√
√
√
√
√
√
√
F0061H
Noise filter enable register 1
NFEN1
R/W
√
√
−
00H
√
√
√
√
√
√
√
F0062H
Noise filter enable register 2
NFEN2
R/W
√
√
−
00H
√
√
√
√
√
√
√
F00E0H Multiplication/division data
register C (L)
MDCL
R
−
−
√
0000H
√
√
√
√
√
√
√
F00E2H Multiplication/division data
register C (H)
MDCH
R
−
−
√
0000H
√
√
√
√
√
√
√
F00E8H Multiplication/division control
register
MDUC
R/W
√
√
−
00H
√
√
√
√
√
√
√
F00F0H Peripheral enable register 0
PER0
R/W
√
√
−
00H
√
√
√
√
√
√
√
F00F1H Peripheral enable register 1
PER1
R/W
√
√
−
00H
√
√
√
√
√
F00F2H Peripheral enable register 2
PER2
R/W
√
√
−
00H
√
√
√
√
√
Note Note
−
−
Note Those are only mounted in the 78K0R/KF3-L (μ PD78F1027 and 78F1028) and the 78K0R/KG3-L (μ PD78F1029 and
78F1030).
R01UH0106EJ0400 Rev.4.00
Mar 31, 2011
167
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CHAPTER 4 CPU ARCHITECTURE
Table 4-6. Extended SFR (2nd SFR) List (2/8)
R/W
−
√
−
KG3-L
16-bit
KF3-L
8-bit
KE3-L
1-bit
After Reset
KD3-L
Manipulable Bit Range
KC3-L (48-pin)
OSMC
R/W
KC3-L (44-pin)
F00F3H Operation speed mode control
register
Symbol
KC3-L (40-pin)
Address Special Function Register (SFR) Name
00H
√
√
√
√
√
√
√
F00F4H Regulator mode control register
RMC
R/W
−
√
−
00H
√
√
√
√
√
√
√
F00F6H
DSCCTL
R/W
√
√
−
00H
√
√
√
√
√
√
√
BCDADJ
R
−
√
−
Undefined
√
√
√
√
√
√
√
√
0000H
√
√
√
√
√
√
√
√
√
√
√
√
√
√
√
√
√
√
√
√
√
√
√
√
√
√
√
√
√
√
√
√
√
√
√
√
√
√
√
√
√
√
√
√
√
√
√
√
√
√
√
√
√
√
√
√
√
√
√
√
√
√
√
√
√
√
√
√
√
√
√
√
√
√
√
√
20 MHz internal high-speed
oscillation control register
F00FEH BCD adjust result register
F0100H
Serial status register 00
F0102H
Serial status register 01
Serial status register 02
SSR01L SSR01
R
SSR02L SSR02
R
−
F0105H
F0106H
R
−
F0103H
F0104H
SSR00L SSR00
−
F0101H
Serial status register 03
SSR03L SSR03
R
−
F0107H
Serial flag clear trigger register
00
SIR00L SIR00 R/W
F010AH Serial flag clear trigger register
F010BH 01
SIR01L SIR01 R/W
F010CH Serial flag clear trigger register
F010DH 02
SIR02L SIR02 R/W
F010EH Serial flag clear trigger register
F010FH 03
SIR03L SIR03 R/W
F0108H
F0109H
−
−
−
−
√
−
−
−
√
−
−
−
√
−
−
−
√
−
−
−
√
−
−
−
√
−
−
−
√
−
−
−
√
√
√
√
√
0000H
0000H
0000H
0000H
√
0000H
√
√
√
√
√
√
√
√
√
0000H
√
√
√
√
√
√
√
√
√
√
√
√
√
√
√
0000H
√
√
√
√
√
√
√
−
−
√
√
√
√
√
√
√
Serial mode register 00
SMR00
R/W
−
−
√
0020H
√
√
√
√
√
√
√
Serial mode register 01
SMR01
R/W
−
−
√
0020H
√
√
√
√
√
√
√
Serial mode register 02
SMR02
R/W
−
−
√
0020H
√
√
√
√
√
√
√
Serial mode register 03
SMR03
R/W
−
−
√
0020H
√
√
√
√
√
√
√
Serial communication operation
setting register 00
SCR00
R/W
−
−
√
0087H
√
√
√
√
√
√
√
F011AH Serial communication operation
F011BH setting register 01
SCR01
R/W
−
−
√
0087H
√
√
√
√
√
√
√
F011CH Serial communication operation
F011DH setting register 02
SCR02
R/W
−
−
√
0087H
√
√
√
√
√
√
√
F011EH Serial communication operation
F011FH setting register 03
SCR03
R/W
−
−
√
0087H
√
√
√
√
√
√
√
F0110H
−
F0111H
F0112H
F0113H
F0114H
F0115H
F0116H
F0117H
F0118H
F0119H
R01UH0106EJ0400 Rev.4.00
Mar 31, 2011
168
78K0R/Kx3-L
CHAPTER 4 CPU ARCHITECTURE
Table 4-6. Extended SFR (2nd SFR) List (3/8)
√
−
√
√
−
−
√
√
−
−
−
√
Serial channel start register 0
SS0L
Serial channel stop register 0
ST0L
Serial clock select register 0
SPS0L SPS0
−
−
Serial output register 0
SO0
R/W
−
SOE0L SOE0
R/W
ST0
R/W
−
F0125H
R/W
−
F0127H
F0128H
R/W
−
F0123H
F0126H
SS0
KG3-L
√
−
F0122H
−
KF3-L
√
SE0L
KE3-L
16-bit
KD3-L
8-bit
After Reset
KC3-L (48-pin)
1-bit
Serial channel enable status
register 0
F0124H
R
Manipulable Bit Range
F0121H
F0120H
SE0
R/W
KC3-L (44-pin)
Symbol
KC3-L (40-pin)
Address Special Function Register (SFR) Name
0000H
√
√
√
√
√
√
√
√
√
√
√
√
√
√
√
√
√
√
√
√
√
0000H
√
√
√
√
√
√
√
√
√
0000H
√
√
√
√
√
√
√
√
√
√
√
√
√
√
√
0000H
√
√
√
√
√
√
√
√
√
√
√
√
√
√
−
√
0F0FH
√
√
√
√
√
√
√
√
√
√
0000H
√
√
√
√
√
√
√
−
−
√
√
√
√
√
√
√
−
√
√
√
√
√
√
√
√
−
−
√
√
√
√
√
√
√
−
−
−
−
−
√
√
−
−
−
−
−
√
√
−
−
−
−
−
√
√
−
−
−
−
−
√
√
−
−
−
−
√
√
F0129H
F012AH Serial output enable register 0
−
F012BH
F0134H
Serial output level register 0
F0140H
Serial status register 10
Serial status register 11
SSR10L SSR10
R
SSR11L SSR11
R
−
F0143H
F0144H
R/W
−
F0141H
F0142H
SOL0L SOL0
−
F0135H
Serial status register 12
SSR12L SSR12
Serial status register 13
SSR13L SSR13
Serial flag clear trigger register
10
SIR10L SIR10 R/W
F014AH Serial flag clear trigger register
F014BH 11
SIR11L SIR11 R/W
F014CH Serial flag clear trigger register
F014DH 12
SIR12L SIR12 R/W
F014EH Serial flag clear trigger register
F014FH 13
SIR13L SIR13 R/W
−
F0145H
F0146H
F0149H
F0150H
R
−
F0147H
F0148H
R
−
−
−
−
−
√
−
−
−
√
−
−
−
√
−
−
−
√
−
−
−
√
−
−
−
√
−
−
−
√
−
−
−
√
−
−
√
√
√
0000H
0000H
0000H
√
0000H
−
−
−
−
−
−
√
√
√
0000H
−
−
−
−
−
√
√
−
−
−
−
−
√
√
√
0000H
−
−
−
−
−
√
√
−
−
−
−
−
√
√
√
0000H
−
−
−
−
−
√
√
−
−
−
−
−
√
√
−
−
−
−
−
√
√
−
−
−
−
−
√
√
−
−
−
−
−
√
√
−
−
−
−
−
√
√
√
√
0000H
0000H
Serial mode register 10
SMR10
R/W
−
−
√
0020H
−
−
−
−
−
√
√
Serial mode register 11
SMR11
R/W
−
−
√
0020H
−
−
−
−
−
√
√
Serial mode register 12
SMR12
R/W
−
−
√
0020H
−
−
−
−
−
√
√
Serial mode register 13
SMR13
R/W
−
−
√
0020H
−
−
−
−
−
√
√
F0151H
F0152H
F0153H
F0154H
F0155H
F0156H
F0157H
R01UH0106EJ0400 Rev.4.00
Mar 31, 2011
169
78K0R/Kx3-L
CHAPTER 4 CPU ARCHITECTURE
Table 4-6. Extended SFR (2nd SFR) List (4/8)
KE3-L
KF3-L
KG3-L
After Reset
KD3-L
Manipulable Bit Range
KC3-L (48-pin)
R/W
KC3-L (44-pin)
Symbol
KC3-L (40-pin)
Address Special Function Register (SFR) Name
Serial communication operation SCR10
setting register 10
R/W
−
−
√
0087H
−
−
−
−
−
√
√
F015AH Serial communication operation SCR11
F015BH setting register 11
R/W
−
−
√
0087H
−
−
−
−
−
√
√
F015CH Serial communication operation SCR12
F015DH setting register 12
R/W
−
−
√
0087H
−
−
−
−
−
√
√
F015EH Serial communication operation SCR13
F015FH setting register 13
R/W
−
−
√
0087H
−
−
−
−
−
√
√
SE1
R
√
√
√
0000H
−
−
−
−
−
√
√
−
−
−
−
−
√
√
SS1
R/W
√
0000H
−
−
−
−
−
√
√
−
−
−
−
−
√
√
ST1
R/W
√
0000H
−
−
−
−
−
√
√
−
−
−
−
−
√
√
−
−
−
−
−
√
√
−
−
−
−
−
√
√
F0158H
F0159H
F0160H
SE1L
F0161H
Serial channel enable status
register 1
F0162H
Serial channel start register 1
SS1L
Serial channel stop register 1
ST1L
−
F0163H
F0164H
−
F0165H
F0166H
Serial clock select register 1
SPS1L SPS1
R/W
−
F0167H
F0168H
−
Serial output register 1
1-bit
8-bit
16-bit
−
−
√
√
−
−
√
√
−
−
−
√
−
−
√
0000H
SO1
R/W
−
−
√
0F0FH
−
−
−
−
−
√
√
SOE1L SOE1
R/W
√
√
√
0000H
−
−
−
−
−
√
√
−
−
−
−
−
−
−
√
√
−
√
−
−
−
−
−
√
√
−
−
−
−
−
−
−
√
√
F0169H
F016AH Serial output enable register 1
−
F016BH
F0174H
Serial output level register 1
SOL1L SOL1
R/W
−
F0175H
√
0000H
Timer counter register 00
TCR00
R
−
−
√
FFFFH
√
√
√
√
√
√
√
Timer counter register 01
TCR01
R
−
−
√
FFFFH
√
√
√
√
√
√
√
Timer counter register 02
TCR02
R
−
−
√
FFFFH
√
√
√
√
√
√
√
Timer counter register 03
TCR03
R
−
−
√
FFFFH
√
√
√
√
√
√
√
Timer counter register 04
TCR04
R
−
−
√
FFFFH
√
√
√
√
√
√
√
F018AH Timer counter register 05
TCR05
R
−
−
√
FFFFH
√
√
√
√
√
√
√
TCR06
R
−
−
√
FFFFH
√
√
√
√
√
√
√
TCR07
R
−
−
√
FFFFH
√
√
√
√
√
√
√
F0180H
F0181H
F0182H
F0183H
F0184H
F0185H
F0186H
F0187H
F0188H
F0189H
F018BH
F018CH Timer counter register 06
F018DH
F018EH Timer counter register 07
F018FH
R01UH0106EJ0400 Rev.4.00
Mar 31, 2011
170
78K0R/Kx3-L
CHAPTER 4 CPU ARCHITECTURE
Table 4-6. Extended SFR (2nd SFR) List (5/8)
KE3-L
KF3-L
KG3-L
After Reset
KD3-L
Manipulable Bit Range
KC3-L (48-pin)
R/W
KC3-L (44-pin)
Symbol
KC3-L (40-pin)
Address Special Function Register (SFR) Name
Timer mode register 00
TMR00
R/W
−
−
√
0000H
√
√
√
√
√
√
√
Timer mode register 01
TMR01
R/W
−
−
√
0000H
√
√
√
√
√
√
√
Timer mode register 02
TMR02
R/W
−
−
√
0000H
√
√
√
√
√
√
√
Timer mode register 03
TMR03
R/W
−
−
√
0000H
√
√
√
√
√
√
√
Timer mode register 04
TMR04
R/W
−
−
√
0000H
√
√
√
√
√
√
√
F019AH Timer mode register 05
TMR05
R/W
−
−
√
0000H
√
√
√
√
√
√
√
TMR06
R/W
−
−
√
0000H
√
√
√
√
√
√
√
TMR07
R/W
−
−
√
0000H
√
√
√
√
√
√
√
R
−
√
√
0000H
√
√
√
√
√
√
√
−
−
√
√
√
√
√
√
√
R
−
√
√
√
√
√
√
√
−
−
R
−
√
−
−
R
−
√
−
−
R
−
√
−
−
−
√
−
−
−
√
−
−
−
√
−
−
√
√
−
−
F0190H
1-bit
8-bit
16-bit
F0191H
F0192H
F0193H
F0194H
F0195H
F0196H
F0197H
F0198H
F0199H
F019BH
F019CH Timer mode register 06
F019DH
F019EH Timer mode register 07
F019FH
F01A0H Timer status register 00
F01A1H
F01A2H Timer status register 01
F01A3H
F01A4H Timer status register 02
F01A5H
F01A6H Timer status register 03
F01A7H
F01A8H Timer status register 04
F01A9H
F01AAH Timer status register 05
F01ABH
F01ACH Timer status register 06
F01ADH
F01AEH Timer status register 07
F01AFH
TSR00L TSR00
−
TSR01L TSR01
−
TSR02L TSR02
−
TSR03L TSR03
−
TSR04L TSR04
−
TSR05L TSR05
TSR06L TSR06
TSR07L TSR07
F01B2H Timer channel start register 0
TS0L
F01B5H
R01UH0106EJ0400 Rev.4.00
Mar 31, 2011
R
−
TE0L
F01B4H Timer channel stop register 0
R
−
F01B0H Timer channel enable status
F01B1H register 0
F01B3H
R
−
TE0
R
−
TS0
R/W
√
√
−
−
TT0
R/W
√
√
−
−
−
TT0L
−
√
0000H
√
√
√
√
√
√
√
√
√
0000H
√
√
√
√
√
√
√
√
√
√
√
√
√
√
√
0000H
√
√
√
√
√
√
√
√
√
√
√
√
√
√
√
0000H
√
√
√
√
√
√
√
√
√
√
√
√
√
√
√
√
√
√
√
√
√
√
√
√
√
√
√
√
√
√
√
√
√
√
√
√
√
√
√
√
√
√
√
√
√
√
√
√
√
√
√
√
√
√
√
√
√
√
√
√
√
√
√
√
√
√
√
√
√
√
√
√
√
√
√
√
√
√
√
√
0000H
0000H
0000H
0000H
√
0000H
√
√
√
√
√
√
√
√
√
0000H
√
√
√
√
√
√
√
√
√
√
√
√
√
√
171
78K0R/Kx3-L
CHAPTER 4 CPU ARCHITECTURE
Table 4-6. Extended SFR (2nd SFR) List (6/8)
F01BCH Timer output level register 0
F01BDH
F01BEH Timer output mode register 0
F01BFH
F01C0H Timer counter register 10
−
√
√
−
−
R/W
−
√
−
−
R/W
√
√
−
−
R/W
−
√
−
−
TOM0L TOM0 R/W
−
√
−
−
TPS0L TPS0
R/W
−
TO0L
TO0
−
TOE0L TOE0
−
TOL0L TOL0
−
−
KG3-L
F01BBH
16-bit
KF3-L
F01BAH Timer output enable register 0
8-bit
KE3-L
F01B9H
1-bit
After Reset
KD3-L
F01B8H Timer output register 0
Manipulable Bit Range
KC3-L (48-pin)
F01B7H
R/W
KC3-L (44-pin)
F01B6H Timer clock select register 0
Symbol
KC3-L (40-pin)
Address Special Function Register (SFR) Name
0000H
√
√
√
√
√
√
√
√
√
√
√
√
√
√
√
√
√
√
√
√
√
0000H
√
√
√
√
√
√
√
√
√
0000H
√
√
√
√
√
√
√
√
√
√
√
√
√
√
√
0000H
√
√
√
√
√
√
√
√
√
√
√
√
√
√
√
0000H
√
√
√
√
√
√
√
√
√
√
√
√
√
√
TCR10
R
−
−
√
FFFFH
−
−
−
−
−
√
√
TCR11
R
−
−
√
FFFFH
−
−
−
−
−
√
√
TCR12
R
−
−
√
FFFFH
−
−
−
−
−
√
√
TCR13
R
−
−
√
FFFFH
−
−
−
−
−
√
√
TMR10
R/W
−
−
√
0000H
−
−
−
−
−
√
√
TMR11
R/W
−
−
√
0000H
−
−
−
−
−
√
√
TMR12
R/W
−
−
√
0000H
−
−
−
−
−
√
√
TMR13
R/W
−
−
√
0000H
−
−
−
−
−
√
√
R
−
√
√
0000H
−
−
−
−
−
√
√
−
−
−
−
−
−
−
√
√
−
√
−
−
−
−
−
√
√
−
−
−
−
−
−
−
√
√
−
√
−
−
−
−
−
√
√
−
−
−
−
−
−
−
√
√
−
√
−
−
−
−
−
√
√
−
−
−
−
−
−
−
√
√
√
−
−
−
−
√
√
F01C1H
F01C2H Timer counter register 11
F01C3H
F01C4H Timer counter register 12
F01C5H
F01C6H Timer counter register 13
F01C7H
F01C8H Timer mode register 10
F01C9H
F01CAH Timer mode register 11
F01CBH
F01CCH Timer mode register 12
F01CDH
F01CEH Timer mode register 13
F01CFH
F01D0H Timer status register 10
F01D1H
F01D2H Timer status register 11
F01D3H
F01D4H Timer status register 12
F01D5H
F01D6H Timer status register 13
F01D7H
TSR10L TSR10
−
TSR11L TSR11
TSR12L TSR12
TSR13L TSR13
R
−
TE1L
F01DAH Timer channel start register 1
TS1L
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−
F01D8H Timer channel enable status
F01D9H register 1
F01DBH
R
−
TE1
R
√
−
−
TS1
R/W
√
√
−
−
−
−
√
√
√
0000H
0000H
0000H
√
0000H
−
−
−
−
−
−
√
√
√
0000H
−
−
−
−
−
√
√
−
−
−
−
−
√
√
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Table 4-6. Extended SFR (2nd SFR) List (7/8)
F01E1H
F01E2H Timer output enable register 1
F01E3H
F01E4H Timer output level register 1
F01E5H
F01E6H Timer output mode register 1
F01B7H
F0200H Serial status register 20
F0201H
F0202H Serial status register 21
F0203H
16-bit
√
√
√
−
−
R/W
−
√
−
−
R/W
−
√
−
−
R/W
√
√
−
−
−
√
−
−
−
√
−
−
−
√
−
−
−
√
−
−
−
√
−
−
R/W
−
√
R/W
−
TPS1L TPS1
−
TO1L
TO1
−
TOE1L TOE1
−
TOL1L TOL1
R/W
−
TOM1L TOM1
R/W
−
SSR20L SSR20 R/W
−
SSR21L SSR21 R/W
−
F0204H Serial flag clear trigger register
F0205H 20
SIR20L SIR20
R/W
F0206H Serial flag clear trigger register
F0207H 21
SIR21L SIR21
−
−
F0208H Serial mode register 20
SMR20
R/W
−
SMR21
R/W
F020CH Serial communication operation SCR20
F020DH setting register 20
F020EH Serial communication operation SCR21
F020FH setting register 21
−
0000H
√
0000H
√
0000H
√
0000H
√
0000H
√
√
√
√
0000H
0000H
0000H
0000H
KG3-L
F01E0H Timer output register 1
8-bit
KF3-L
F01DFH
1-bit
After Reset
KE3-L
F01DEH Timer clock select register 1
TT1
Manipulable Bit Range
KD3-L
F01DDH
TT1L
R/W
KC3-L (48-pin)
F01DCH Timer channel stop register 1
Symbol
KC3-L (44-pin)
Address Special Function Register (SFR) Name
−
−
−
−
√
√
−
−
−
−
√
√
−
−
−
−
√
√
−
−
−
−
√
√
−
−
−
−
√
√
−
−
−
−
√
√
−
−
−
−
√
√
−
−
−
−
√
√
−
−
−
−
√
√
−
−
−
−
√
√
−
−
−
−
√
√
−
−
−
−
√
√
−
−
−
−
Note Note
−
−
−
−
Note Note
−
−
−
−
Note Note
−
−
−
−
Note Note
−
−
−
−
Note Note
−
−
−
−
Note Note
−
−
−
−
Note Note
√
0000H
−
−
−
−
Note Note
−
√
0020H
−
−
−
−
Note Note
−
−
√
0020H
−
−
−
−
Note Note
R/W
−
−
√
0087H
−
−
−
−
Note Note
R/W
−
−
√
0087H
−
−
−
−
Note Note
R
√
√
√
0000H
−
−
−
−
Note Note
−
−
−
−
−
−
Note Note
√
√
−
−
−
−
Note Note
−
−
−
−
−
−
Note Note
−
−
−
−
Note Note
−
−
−
−
Note Note
−
−
−
−
Note Note
−
−
−
−
Note Note
−
F0209H
F020AH Serial mode register 21
F020BH
F0210H Serial channel enable status
F0211H register 2
SE2L
F0212H Serial channel start register 2
SS2L
F0213H
F0214H Serial channel stop register 2
F0215H
F0216H Serial clock select register2
F0217H
SE2
−
SS2
R/W
−
ST2L
ST2
R/W
−
SPS2L SPS2
−
R/W
√
√
−
−
√
√
−
−
√
√
√
0000H
0000H
0000H
Note Those are only mounted in the 78K0R/KF3-L (μ PD78F1027 and 78F1028) and the 78K0R/KG3-L (μ PD78F1029 and
78F1030).
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Table 4-6. Extended SFR (2nd SFR) List (8/8)
−
−
√
0303H
−
−
−
−
−
Note Note
−
−
−
−
−
Note Note
−
−
−
−
−
Note Note
−
−
−
−
−
Note Note
−
−
−
−
Note Note
Note Note
F0219H
F021AH Serial output enable register 2
√
√
−
−
R/W
√
√
−
−
R/W
√
√
SOE2L SOE2 R/W
−
F021BH
F0220H Serial output level register 2
SOL2L SOL2
−
F0221H
0000H
√
0000H
−
−
−
−
−
−
−
00H
−
−
√
√
√
√
√
F0230H
IICA control register 0
F0231H
IICA control register 1
IICCTL1
R/W
√
√
−
00H
−
−
√
√
√
√
√
F0232H
IICA low-level width setting
register
IICWL
R/W
−
√
−
FFH
−
−
√
√
√
√
√
F0233H
IICA high-level width setting
register
IICWH
R/W
−
√
−
FFH
−
−
√
√
√
√
√
F0234H
Slave address register
SVA
R/W
−
√
−
00H
−
√
√
√
√
√
√
F0240H
Programmable gain amplifier
control register
OAM
R/W
√
√
−
00H
√
√
√
√
√
−
−
F0241H
Comparator 0 control register
C0CTL
R/W
√
√
−
00H
√
√
√
√
√
−
−
F0242H
Comparator 0 internal reference C0RVM
voltage setting register
R/W
√
√
−
00H
√
√
√
√
√
−
−
F0243H
Comparator 1 control register
R/W
√
√
−
00H
√
√
√
√
√
−
−
F0244H
Comparator 1 internal reference C1RVM
voltage setting register
R/W
√
√
−
00H
√
√
√
√
√
−
−
Note
IICCTL0
√
KG3-L
16-bit
KF3-L
8-bit
KE3-L
1-bit
After Reset
KD3-L
R/W
Manipulable Bit Range
KC3-L (48-pin)
SO2
R/W
KC3-L (44-pin)
F0218H Serial output register 2
Symbol
KC3-L (40-pin)
Address Special Function Register (SFR) Name
C1CTL
Those are only mounted in the 78K0R/KF3-L (μ PD78F1027 and 78F1028) and the 78K0R/KG3-L (μ PD78F1029
and 78F1030).
Remark
For SFRs in the SFR area, see Table 4-5 SFR List.
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4.3 Instruction Address Addressing
4.3.1 Relative addressing
[Function]
Relative addressing stores in the program counter (PC) the result of adding a displacement value included in the
instruction word (signed complement data: −128 to +127 or −32768 to +32767) to the program counter (PC)’s value
(the start address of the next instruction), and specifies the program address to be used as the branch destination.
Relative addressing is applied only to branch instructions.
Figure 4-26. Outline of Relative Addressing
PC
OP code
DISPLACE
8/16 bits
4.3.2 Immediate addressing
[Function]
Immediate addressing stores immediate data of the instruction word in the program counter, and specifies the
program address to be used as the branch destination.
For immediate addressing, CALL !!addr20 or BR !!addr20 is used to specify 20-bit addresses and CALL !addr16 or
BR !addr16 is used to specify 16-bit addresses. 0000 is set to the higher 4 bits when specifying 16-bit addresses.
Figure 4-27. Example of CALL !!addr20/BR !!addr20
PC
OP code
Low Addr.
High Addr.
Seg Addr.
Figure 4-28. Example of CALL !addr16/BR !addr16
PC
PCS
PCH
PCL
OP code
0000
Low Addr.
High Addr.
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4.3.3 Table indirect addressing
[Function]
Table indirect addressing specifies a table address in the CALLT table area (0080H to 00BFH) with the 5-bit
immediate data in the instruction word, stores the contents at that table address and the next address in the program
counter (PC) as 16-bit data, and specifies the program address. Table indirect addressing is applied only for CALLT
instructions.
In the 78K0R microcontrollers, branching is enabled only to the 64 KB space from 00000H to 0FFFFH.
Figure 4-29. Outline of Table Indirect Addressing
OP code
Low Addr.
00000000
10
0
High Addr.
Table address
Memory
0000
PC
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PCH
PCL
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4.3.4 Register direct addressing
[Function]
Register direct addressing stores in the program counter (PC) the contents of a general-purpose register pair
(AX/BC/DE/HL) and CS register of the current register bank specified with the instruction word as 20-bit data, and
specifies the program address. Register direct addressing can be applied only to the CALL AX, BC, DE, HL, and BR
AX instructions.
Figure 4-30. Outline of Register Direct Addressing
OP code
rp
CS
PC
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PCH
PCL
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4.4 Addressing for Processing Data Addresses
4.4.1 Implied addressing
[Function]
Instructions for accessing registers (such as accumulators) that have special functions are directly specified with the
instruction word, without using any register specification field in the instruction word.
[Operand format]
Because implied addressing can be automatically employed with an instruction, no particular operand format
is necessary.
Implied addressing can be applied only to MULU X.
Figure 4-31. Outline of Implied Addressing
OP code
A register
Memory
4.4.2 Register addressing
[Function]
Register addressing accesses a general-purpose register as an operand. The instruction word of 3-bit long is used
to select an 8-bit register and the instruction word of 2-bit long is used to select a 16-bit register.
[Operand format]
Identifier
Description
r
X, A, C, B, E, D, L, H
rp
AX, BC, DE, HL
Figure 4-32. Outline of Register Addressing
OP code
Register
Memory
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4.4.3 Direct addressing
[Function]
Direct addressing uses immediate data in the instruction word as an operand address to directly specify the target
address.
[Operand format]
Identifier
Description
ADDR16
Label or 16-bit immediate data (only the space from F0000H to FFFFFH is specifiable)
ES: ADDR16
Label or 16-bit immediate data (higher 4-bit addresses are specified by the ES register)
Figure 4-33. Example of ADDR16
FFFFFH
OP code
Low Addr.
Target memory
High Addr.
F0000H
Memory
Figure 4-34. Example of ES:ADDR16
FFFFFH
ES
OP code
Low Addr.
Target memory
High Addr.
00000H
Memory
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4.4.4 Short direct addressing
[Function]
Short direct addressing directly specifies the target addresses using 8-bit data in the instruction word. This type of
addressing is applied only to the space from FFE20H to FFF1FH.
[Operand format]
Identifier
SADDR
Description
Label, FFE20H to FFF1FH immediate data, or 0FE20H to 0FF1FH immediate data
(only the space from FFE20H to FFF1FH is specifiable)
SADDRP
Label, FFE20H to FFF1FH immediate data, or 0FE20H to 0FF1FH immediate data (even address only)
(only the space from FFE20H to FFF1FH is specifiable)
Figure 4-35. Outline of Short Direct Addressing
OP code
FFF1FH
saddr
saddr
FFE20H
Memory
Remark SADDR and SADDRP are used to describe the values of addresses FE20H to FF1FH with 16-bit immediate
data (higher 4 bits of actual address are omitted), and the values of addresses FFE20H to FFF1FH with 20bit immediate data.
Regardless of whether SADDR or SADDRP is used, addresses within the space from FFE20H to FFF1FH
are specified for the memory.
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4.4.5 SFR addressing
[Function]
SFR addressing directly specifies the target SFR addresses using 8-bit data in the instruction word. This type of
addressing is applied only to the space from FFF00H to FFFFFH.
[Operand format]
Identifier
SFR
SFRP
Description
SFR name
16-bit-manipulatable SFR name (even address only)
Figure 4-36. Outline of SFR Addressing
FFFFFH
OP code
SFR
FFF00H
SFR
Memory
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CHAPTER 4 CPU ARCHITECTURE
4.4.6 Register indirect addressing
[Function]
Register indirect addressing directly specifies the target addresses using the contents of the register pair specified
with the instruction word as an operand address.
[Operand format]
Identifier
Description
−
[DE], [HL] (only the space from F0000H to FFFFFH is specifiable)
−
ES:[DE], ES:[HL] (higher 4-bit addresses are specified by the ES register)
Figure 4-37. Example of [DE], [HL]
FFFFFH
OP code
rp
Target memory
F0000H
Memory
Figure 4-38. Example of ES:[DE], ES:[HL]
FFFFFH
ES
OP code
rp
Target memory
00000H
Memory
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4.4.7 Based addressing
[Function]
Based addressing uses the contents of a register pair specified with the instruction word as a base address, and 8bit immediate data or 16-bit immediate data as offset data. The sum of these values is used to specify the target
address.
[Operand format]
Identifier
Description
−
[HL + byte], [DE + byte], [SP + byte] (only the space from F0000H to FFFFFH is specifiable)
−
word[B], word[C] (only the space from F0000H to FFFFFH is specifiable)
−
word[BC] (only the space from F0000H to FFFFFH is specifiable)
−
ES:[HL + byte], ES:[DE + byte] (higher 4-bit addresses are specified by the ES register)
−
ES:word[B], ES:word[C] (higher 4-bit addresses are specified by the ES register)
−
ES:word[BC] (higher 4-bit addresses are specified by the ES register)
Figure 4-39. Example of [SP+byte]
FFFFFH
SP
Target memory
F0000H
OP code
byte
Memory
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Figure 4-40. Example of [HL + byte], [DE + byte]
FFFFFH
rp (HL/DE)
Target memory
F0000H
OP code
byte
Memory
Figure 4-41. Example of word[B], word[C]
FFFFFH
r (B/C)
Target memory
F0000H
OP code
Low Addr.
High Addr.
Memory
Figure 4-42. Example of word[BC]
FFFFFH
rp (BC)
Target memory
F0000H
OP code
Low Addr.
High Addr.
Memory
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Figure 4-43. Example of ES:[HL + byte], ES:[DE + byte]
FFFFFH
ES
rp (HL/DE)
Target memory
OP code
00000H
byte
Memory
Figure 4-44. Example of ES:word[B], ES:word[C]
FFFFFH
ES
r (B/C)
Target memory
OP code
00000H
Low Addr.
Memory
High Addr.
Figure 4-45. Example of ES:word[BC]
FFFFFH
ES
rp (BC)
Target memory
OP code
00000H
Low Addr.
Memory
High Addr.
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4.4.8 Based indexed addressing
[Function]
Based indexed addressing uses the contents of a register pair specified with the instruction word as the base
address, and the content of the B register or C register similarly specified with the instruction word as offset address.
The sum of these values is used to specify the target address.
[Operand format]
Identifier
Description
−
[HL+B], [HL+C] (only the space from F0000H to FFFFFH is specifiable)
−
ES:[HL+B], ES:[HL+C] (higher 4-bit addresses are specified by the ES register)
Figure 4-46. Example of [HL+B], [HL+C]
FFFFFH
OP code
rp (HL)
Target memory
F0000H
r (B/C)
Memory
Figure 4-47. Example of ES:[HL+B], ES:[HL+C]
FFFFFH
OP code
ES
rp (HL)
Target memory
00000H
r (B/C)
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4.4.9 Stack addressing
[Function]
The stack area is indirectly addressed with the stack pointer (SP) contents.
This addressing is automatically
employed when the PUSH, POP, subroutine call, and return instructions are executed or the register is
saved/restored upon generation of an interrupt request.
Stack addressing is applied only to the internal RAM area.
[Operand format]
Identifier
−
Description
PUSH AX/BC/DE/HL
POP AX/BC/DE/HL
CALL/CALLT
RET
BRK
RETB
(Interrupt request generated)
RETI
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CHAPTER 5 PORT FUNCTIONS (78K0R/KC3-L, 78K0R/KD3-L, 78K0R/KE3-L)
CHAPTER 5 PORT FUNCTIONS (78K0R/KC3-L, 78K0R/KD3-L, 78K0R/KE3-L)
Caution For the functions of the port in the 78K0R/KF3-L and 78K0R/KG3-L, see CHAPTER 6
PORT
FUNCTIONS (78K0R/KF3-L and 78K0R/KG3-L).
5.1 Port Functions
Pin I/O buffer power supplies depend on the product. The relationship between these power supplies and the pins is
shown below.
Table 5-1. Pin I/O Buffer Power Supplies (AVREF, VDD)
• 78K0R/KC3-L: 40-pin plastic WQFN (6x6)
Note 1
44-pin plastic LQFP (10x10)
48-pin plastic TQFP (fine pitch) (7x7)
48-pin plastic WQFN (7x7) Note 1
• 78K0R/KD3-L: 52-pin plastic LQFP (10x10)
Power Supply
Corresponding Pins
Note 2
, P80 to P83
Note 3
AVREF
P20 to P27, P150 to P152
EVDD
• Port pins other than P20 to P27, P150 to P152
Note 2
, P80 to P83
Note 3
• Pins other than port pins
Notes 1. Under development
2. 40-pin and 44-pin products of the 78K0R/KC3-L do not have a P152 pin.
3. 40-pin product of the 78K0R/KC3-L does not have a P82 pin.
Table 5-2. Pin I/O Buffer Power Supplies (AVREF, EVDD, VDD)
• 78K0R/KE3-L: 64-pin plastic FBGA (5x5)
64-pin plastic FBGA (4x4)
64-pin plastic TQFP (fine pitch) (7x7)
64-pin plastic LQFP (fine pitch) (10x10)
64-pin plastic LQFP (12x12)
Power Supply
Corresponding Pins
AVREF
P20 to P27, P150 to P153, P80 to P83
EVDD
• Port pins other than P20 to P27, P150 to P153, P80 to P83, and P121 to P124
• RESET pin and FLMD0 pin
VDD
• P121 to P124
• Pins other than port pins (other than RESET pin and FLMD0 pin)
The 78K0R/KC3-L, 78K0R/KD3-L, 78K0R/KE3-L microcontrollers are provided with digital I/O ports, which enable
variety of control operations. The functions of each port are shown in Table 5-3.
In addition to the function as digital I/O ports, these ports have several alternate functions. For details of the alternate
functions, see CHAPTER 2 PIN FUNCTIONS (78K0R/KC3-L, 78K0R/KD3-L, 78K0R/KE3-L).
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Table 5-3. Port Functions (1/2)
KC3-L (40-pin)
KC3-L (44-pin)
KC3-L (48-pin)
KD3-L
KE3-L
−
−
−
√
√
Function Name
P00
I/O
I/O
Function
Port 0.
After Reset
Input port
Alternate Function
TI00
I/O port.
Input/output can be specified in 1-bit units.
−
−
−
√
√
P01
TO00
Use of an on-chip pull-up resistor can be
specified by a software setting.
√
√
√
√
√
P10
√
√
√
√
√
P11
√
√
√
√
√
I/O
Port 1.
Input port
I/O port.
TI03/TO03
Input/output can be specified in 1-bit units.
P12
TI02/TO02
TI04/TO04/
Use of an on-chip pull-up resistor can be
Note 1
RTCDIV/RTCCL
specified by a software setting.
√
√
√
√
√
P13
TI05/TO05
−
−
−
−
√
P14
TI06/TO06
−
−
−
−
√
P15
TI07/TO07
−
−
−
−
√
P16
−
−
−
−
−
√
P17
−
√
√
√
√
√
√
√
√
√
√
P20 to P27
I/O
Port 2.
Digital input
I/O port.
port
ANI0 to ANI7
Input/output can be specified in 1-bit units.
√
√
√
√
√
√
√
√
√
√
P30
I/O
P31
Port 3.
Input port
SI10/RxD1/SDA10
Input of P31 and P32 can be set to TTL buffer.
/INTP1
Output of P30 to P32 can be set to N-ch open-
P32
SCK10/SCL10/
drain output (VDD tolerance).
INTP2
Input/output can be specified in 1-bit units.
−
−
−
−
√
√
√
√
√
√
√
√
√
√
√
P33
Note 2
P40
−
−
√
P42
−
−
−
−
√
P43
√
√
√
√
√
P50
√
√
√
√
√
P51
√
√
√
I/O
P52
Port 4.
−
−
−
√
TOOL0
TOOL1
Input/output can be specified in 1-bit units.
I/O
Use of an on-chip pull-up resistor can be
−
specified by a software setting.
−
Port 5.
I/O port.
Input/output can be specified in 1-bit units.
Use of an on-chip pull-up resistor can be
specified by a software setting.
−
Input port
I/O port.
P41
−
√
−
Use of an on-chip pull-up resistor can be
specified by a software setting.
−
−
SO10/TxD1
I/O port.
P53
Input port
TI06/TO06
Note 3
TI07/TO07
Note 3
RTC1HZ/SLTI/
SLTO
−
Notes 1. 40-pin product of the 78K0R/KC3-L does not have a RTCDIV/RTCCL pin.
2. If on-chip debugging is enabled by using an option byte, be sure to pull up the P40/TOOL0 pin externally
(see Caution in 2.2.5 P40 to P43 (port 4)).
3. TI06/TO06 and TI07/TO07 are shared only in the 78K0R/KC3-L and 78K0R/KD3-L. The 78K0R/KE3-L does
not have a sharing function.
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Table 5-3. Port Functions (2/2)
KC3-L (40-pin)
KC3-L (44-pin)
KC3-L (48-pin)
KD3-L
KE3-L
−
−
√
√
√
Function Name
P60
I/O
I/O
Function
Port 6.
After Reset
Input port
Alternate Function
SCL0
I/O port.
Output of P60 and P61 is N-ch open-drain output
−
−
√
√
√
P61
SDA0
(6 V tolerance).
Input/output can be specified in 1-bit units.
√
√
√
√
√
P70
√
√
√
√
√
P71
√
√
√
√
√
I/O
Port 7.
Input port
I/O port.
KR1/SI01/INTP5
Input of P71, P72, P74, and P75 can be set to
P72
KR0/SO01/INTP4
KR2/SCK01/
TTL buffer.
INTP6
Output of P70, P72, P73, and P75 can be set to
√
√
√
√
√
P73
N-ch open-drain output (VDD tolerance).
KR3/SO00/TxD0
√
√
√
√
√
P74
Input/output can be specified in 1-bit units.
KR4/SI00/RxD0
Use of an on-chip pull-up resistor can be
√
√
√
√
√
P75
−
−
−
√
√
P76
KR6
−
−
−
√
√
P77
KR7
√
√
√
√
√
√
√
√
√
√
P81
P80
−
√
√
√
√
P82
√
√
√
√
√
P83
√
√
√
√
√
P120
√
√
√
√
√
P121
I/O
Port 8.
PGAI
CMP0M
Inputs of P80 to P83 can be set as comparator
CMP1M
I/O
Port 12.
Input
I/O port and input port.
√
P122
−
√
√
√
√
P123
For only P120, use of an on-chip pull-up resistor
−
√
√
√
√
P124
can be specified by a software setting.
−
−
√
√
√
P140
−
Input port
X2/EXCLK
bit units.
Output Port 14.
I/O
INTP0/EXLVI
X1
For only P120, input/output can be specified in 1-
√
−
CMP1P/INTP7
inputs or programmable gain amplifier inputs.
√
−
CMP0P/INTP3/
Inputs/output can be specified in 1-bit units.
√
−
Analog input
I/O port.
√
P141
KR5/SCK00
specified by a software setting.
XT1
XT2
Output port
PCLBUZ0
Input port
PCLBUZ1
Port 15.
Digital input
ANI8
I/O port.
port
ANI9
Output port and I/O port.
For only P141, input/output can be specified.
√
For only P141, use of an on-chip pull-up resistor
can be specified by a software setting.
√
√
√
√
√
√
√
√
√
P150
√
P151
−
−
√
√
√
P152
−
−
−
−
√
P153
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Input/output can be specified in 1-bit units.
ANI10
ANI11
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5.2 Port Configuration
Ports include the following hardware.
Table 5-4. Port Configuration
Item
Control registers
Configuration
• 78K0R/KC3-L (40-pin and 44-pin products)
Port mode registers (PM1 to PM5, PM7, PM8, PM12, PM15)
Port registers (P1 to P5, P7, P8, P12, P15)
Pull-up resistor option registers (PU1, PU3 to PU5, PU7, PU12)
Port input mode registers (PIM3, PIM7, PIM8)
Port output mode registers (POM3, POM7)
A/D port configuration register (ADPC)
• 78K0R/KC3-L (48-pin products)
Port mode registers (PM1 to PM8, PM12, PM15)
Port registers (P1 to P8, P12, P14, P15)
Pull-up resistor option registers (PU1, PU3 to PU5, PU7, PU12)
Port input mode registers (PIM3, PIM7, PIM8)
Port output mode registers (POM3, POM7)
A/D port configuration register (ADPC)
• 78K0R/KD3-L
Port mode registers (PM0 to PM8, PM12, PM15)
Port registers (P0 to P8, P12, P14, P15)
Pull-up resistor option registers (PU0, PU1, PU3 to PU5, PU7, PU12)
Port input mode registers (PIM3, PIM7, PIM8)
Port output mode registers (POM3, POM7)
A/D port configuration register (ADPC)
• 78K0R/KE3-L
Port mode registers (PM0 to PM8, PM12, PM14, PM15)
Port registers (P0 to P8, P12, P14, P15)
Pull-up resistor option registers (PU0, PU1, PU3 to PU5, PU7, PU12, PU14)
Port input mode registers (PIM3, PIM7, PIM8)
Port output mode registers (POM3, POM7)
A/D port configuration register (ADPC)
Port
• 78K0R/KC3-L (40-pin products)
Total: 33 (CMOS I/O: 31, CMOS input: 2)
• 78K0R/KC3-L (44-pin products)
Total: 37 (CMOS I/O: 33, CMOS input: 4)
• 78K0R/KC3-L (48-pin products)
Total: 41 (CMOS I/O: 34, CMOS input: 4, CMOS output: 1, N-ch open drain I/O: 2)
• 78K0R/KD3-L
Total: 45 (CMOS I/O: 38, CMOS input: 4, CMOS output: 1, N-ch open drain I/O: 2)
• 78K0R/KE3-L
Total: 55 (CMOS I/O: 48, CMOS input: 4, CMOS output: 1, N-ch open drain I/O: 2)
Pull-up resistor
• 78K0R/KC3-L (40-pin products) Total: 18
• 78K0R/KC3-L (44-pin products) Total: 19
• 78K0R/KC3-L (48-pin products) Total: 19
• 78K0R/KD3-L Total: 23
• 78K0R/KE3-L Total: 32
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5.2.1 Port 0
78K0R/KC3-L
78K0R/KC3-L (48-pin)
78K0R/KD3-L
78K0R/KE3-L
(μPD78F100y: y = 0 to 3)
(μPD78F100y: y = 1 to 3)
(μPD78F100y: y = 4 to 6)
(μPD78F100y: y = 7 to 9)
40-pin
44-pin
P00/TI00
−
−
√
√
P11/TO00
−
−
√
√
Port 0 is an I/O port with an output latch. Port 0 can be set to the input mode or output mode in 1-bit units using port
mode register 0 (PM0). When the P00 and P01 pins are used as an input port, use of an on-chip pull-up resistor can be
specified in 1-bit units by pull-up resistor option register 0 (PU0).
This port can also be used for timer I/O.
Reset signal generation sets port 0 to input mode.
Figures 5-1 and 5-2 show block diagrams of port 0.
Caution To use P01/TO00 as a general-purpose port, set bit 0 (TO00) of timer output register 0 (TO0) and bit 0
(TOE00) of timer output enable register 0 (TOE0) to “0”, which is the same as their default status
setting.
Figure 5-1. Block Diagram of P00
EVDD
WRPU
PU0
PU00
P-ch
Alternate
function
Selector
Internal bus
RD
WRPORT
P0
Output latch
(P00)
P00/TI00
WRPM
PM0
PM00
P0:
PU0:
PM0:
RD:
WRxx:
Port register 0
Pull-up resistor option register 0
Port mode register 0
Read signal
Write signal
Remark With products not provided with an EVDD or EVSS pin, replace EVDD with VDD, or replace EVSS with VSS.
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Figure 5-2. Block Diagram of P01
EVDD
WRPU
PU0
PU01
P-ch
Selector
Internal bus
RD
WRPORT
P0
Output latch
(P01)
P01/TO00
WRPM
PM0
PM01
Alternate
function
P0:
Port register 0
PU0:
Pull-up resistor option register 0
PM0:
Port mode register 0
RD:
Read signal
WRxx:
Write signal
Remark With products not provided with an EVDD or EVSS pin, replace EVDD with VDD, or replace EVSS with VSS.
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5.2.2 Port 1
78K0R/KC3-L
78K0R/KC3-L (48-pin)
78K0R/KD3-L
78K0R/KE3-L
(μPD78F100y: y = 0 to 3)
(μPD78F100y: y = 1 to 3)
(μPD78F100y: y = 4 to 6)
(μPD78F100y: y = 7 to 9)
40-pin
44-pin
P10/TI02/TO02
√
√
√
√
P11/TO00/TI03/
√
√
√
√
√
√
√
TO03
P12/TI04/TO04/
P12/TI04/
RTCDIV/RTCCL
TO04
√
Note 1
√
P13/TI05/TO05
P14/TI06/TO06
−
Note 2
P15/TI07/TO07
−
Note 2
√
−
Note 2
−
Note 2
√
√
−
Note 2
√
−
Note 2
√
P16
−
−
−
√
P17
−
−
−
√
Notes 1.
2.
40-pin product of the 78K0R/KC3-L does not have a RTCDIV/RTCCL pin.
TI06/TO06 and TI07/TO07 are shared with P50 and P51, respectively, in products other than the 78K0R/KE3L.
Remark √: Mounted
Port 1 is an I/O port with an output latch. Port 1 can be set to the input mode or output mode in 1-bit units using port
mode register 1 (PM1). When the P10 to P17 pins are used as an input port, use of an on-chip pull-up resistor can be
specified in 1-bit units by pull-up resistor option register 1 (PU1).
This port can also be used for timer I/O and real-time counter clock output.
Reset signal generation sets port 1 to input mode.
Figures 5-3 and 5-4 show block diagrams of port 1.
Caution
To use P10/TI02/TO02, P11/TI03/TO03, P12/TI04/TO04/RTCDIV/RTCCL, P13/TI05/TO05, P14/TI06/TO06, or
P15/TI07/TO07 as a general-purpose port, set bits 2 to 7 (TO02 to TO07) of timer output register 0
(TO0) and bits 2 to 7 (TOE02 to TOE07) of timer output enable register 0 (TOE0) to “0”, which is the
same as their default status setting.
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Figure 5-3. Block Diagram of P10 to P15
EVDD
WRPU
PU1
PU10 to PU15
P-ch
Alternate
function
Selector
Internal bus
RD
WRPORT
P1
Output latch
(P10 to P15)
WRPM
PM1
PM10 to PM15
P10/TI02/TO02,
P11/TI03/TO03,
P12/TI04/TO04/RTCDIVNote/RTCCLNote,
P13/TI05/TO05,
P14/TI06/TO06,
P15/TI07/TO07
Alternate
function
Note
40-pin product of the 78K0R/KC3-L does not have a RTCDIV/RTCCL pin.
P1:
Port register 1
PU1:
Pull-up resistor option register 1
PM1:
Port mode register 1
RD:
Read signal
WR××: Write signal
Remark With products not provided with an EVDD or EVSS pin, replace EVDD with VDD, or replace EVSS with VSS.
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Figure 5-4. Block Diagram of P16 and P17
EVDD
WRPU
PU1
PU16, PU17
P-ch
Selector
Internal bus
RD
WRPORT
P1
Output latch
(P16, P17)
P16, P17
WRPM
PM1
PM16, PM17
P1:
Port register 1
PU1:
Pull-up resistor option register 1
PM1:
Port mode register 1
RD:
Read signal
WR××: Write signal
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5.2.3 Port 2
78K0R/KC3-L
78K0R/KC3-L (48-pin)
78K0R/KD3-L
78K0R/KE3-L
(μPD78F100y: y = 0 to 3)
(μPD78F100y: y = 1 to 3)
(μPD78F100y: y = 4 to 6)
(μPD78F100y: y = 7 to 9)
40-pin
44-pin
P20/ANI0
√
√
√
√
P21/ANI1
√
√
√
√
P22/ANI2
√
√
√
√
P23/ANI3
√
√
√
√
P24/ANI4
√
√
√
√
P25/ANI5
√
√
√
√
P26/ANI6
√
√
√
√
P27/ANI7
√
√
√
√
Remark √: Mounted
Port 2 is an I/O port with an output latch. Port 2 can be set to the input mode or output mode in 1-bit units using port
mode register 2 (PM2).
This port can also be used for A/D converter analog input.
To use P20/ANI0 to P27/ANI7 as digital input pins, set them in the digital I/O mode by using the A/D port configuration
register (ADPC) and in the input mode by using the PM2 register. Use these pins starting from the lower bit.
To use P20/ANI0 to P27/ANI7 as digital output pins, set them in the digital I/O mode by using the ADPC register and in
the output mode by using the PM2 register.
To use P20/ANI0 to P27/ANI7 as analog input pins, set them in the analog input mode by using the ADPC register and
in the input mode by using the PM2 register. Use these pins starting from the upper bit.
Table 5-5. Setting Functions of P20/ANI0 to P27/ANI7 Pins
ADPC Register
Digital I/O selection
Analog input selection
PM2 Register
ADS Register
P20/ANI0 to P27/ANI7 Pins
Input mode
−
Digital input
Output mode
−
Digital output
Input mode
Output mode
Selects ANI.
Analog input (to be converted)
Does not select ANI.
Analog input (not to be converted)
Selects ANI.
Setting prohibited
Does not select ANI.
All P20/ANI0 to P27/ANI7 are set in the digital input mode when the reset signal is generated.
Figure 5-5 shows a block diagram of port 2.
Caution Make the AVREF pin the same potential as the VDD pin when port 2 is used as a digital port.
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Figure 5-5. Block Diagram of P20 to P27
Selector
Internal bus
RD
WRPORT
P2
Output latch
(P20 to P27)
P20/ANI0 to
P27/ANI7
WRPM
PM2
PM20 to PM27
A/D converter
P2:
Port register 2
PM2:
Port mode register 2
RD:
Read signal
WR××: Write signal
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5.2.4 Port 3
78K0R/KC3-L
78K0R/KC3-L (48-pin)
78K0R/KD3-L
78K0R/KE3-L
(μPD78F100y: y = 0 to 3)
(μPD78F100y: y = 1 to 3)
(μPD78F100y: y = 4 to 6)
(μPD78F100y: y = 7 to 9)
40-pin
44-pin
P30/SO10/TxD1
√
√
√
√
P31/SI10/RxD1/
√
√
√
√
√
√
√
√
−
−
−
√
SDA10/INTP1
P32/SCK10/
SCL10/INTP2
P33
Remark √: Mounted
Port 3 is an I/O port with an output latch. Port 3 can be set to the input mode or output mode in 1-bit units using port
mode register 3 (PM3). When the P30 to P33 pins are used as an input port, use of an on-chip pull-up resistor can be
specified in 1-bit units by pull-up resistor option register 3 (PU3).
Input to the P31 and P32 pins can be specified through a normal input buffer or a TTL input buffer in 1-bit units using
port input mode register 3 (PIM3).
Output from the P30 to P32 pins can be specified as N-ch open-drain output (VDD tolerance) in 1-bit units using port
output mode register 3 (POM3).
This port can also be used for serial interface data I/O, clock I/O, and external interrupt request input.
Reset signal generation sets port 3 to input mode.
Figures 5-6 to 5-8 show block diagrams of port 3.
Caution To use P30/SO10/TxD1, P31/SI10/RxD1/SDA10/INTP1, P32/SCK10/SCL10/INTP2 as a general-purpose
port, note the serial array unit setting. For details, refer to Table 14-7 Relationship Between Register
Settings and Pins (Channel 2: CSI10, UART1 Transmission, IIC10) and Table 14-8 Relationship
Between Register Settings and Pins (Channel 3: UART1 Reception).
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Figure 5-6. Block Diagram of P30
EVDD
WRPU
PU3
PU30
P-ch
Selector
RD
Internal bus
WRPORT
P3
Output latch
(P30)
P30/SO10/TxD1
WRPOM
POM3
POM30
WRPM
PM3
PM30
Alternate
function
P3:
Port register 3
PU3:
Pull-up resistor option register 3
POM3: Port output mode register 3
PM3:
Port mode register 3
RD:
Read signal
WR××: Write signal
Remark With products not provided with an EVDD or EVSS pin, replace EVDD with VDD, or replace EVSS with VSS.
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Figure 5-7. Block Diagram of P31 and P32
WRPIM
PIM3
PIM31, PIM32
EVDD
WRPU
PU3
PU31, PU32
P-ch
Alternate
function
CMOS
Selector
Internal bus
RD
TTL
WRPORT
P3
Output latch
(P31, P32)
P31/SI10/RxD1/SDA10/INTP1,
P32/SCK10/SCL10/INTP2
WRPOM
POM3
POM31, POM32
WRPM
PM3
PM31, PM32
Alternate
function
P3:
Port register 3
PU3:
Pull-up resistor option register 3
PIM3:
Port input mode register 3
POM3: Port output mode register 3
PM3:
Port mode register 3
RD:
Read signal
WR××: Write signal
Remark With products not provided with an EVDD or EVSS pin, replace EVDD with VDD, or replace EVSS with VSS.
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Figure 5-8. Block Diagram of P33
EVDD
WRPU
PU3
PU33
P-ch
Selector
Internal bus
RD
WRPORT
P3
Output latch
(P33)
P33
WRPM
PM3
PM33
P3:
Port register 3
PU3:
Pull-up resistor option register 3
PM3:
Port mode register 3
RD:
Read signal
WR××: Write signal
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5.2.5 Port 4
78K0R/KC3-L
78K0R/KC3-L (48-pin)
78K0R/KD3-L
78K0R/KE3-L
(μPD78F100y: y = 0 to 3)
(μPD78F100y: y = 1 to 3)
(μPD78F100y: y = 4 to 6)
(μPD78F100y: y = 7 to 9)
40-pin
44-pin
P40/TOOL0
√
√
√
√
P41/TOOL1
√
√
√
√
P42
−
−
−
√
P43
−
−
−
√
Remark √: Mounted
Port 4 is an I/O port with an output latch. Port 4 can be set to the input mode or output mode in 1-bit units using port
mode register 4 (PM4). When the P40 to P43 pins are used as an input port, use of an on-chip pull-up resistor can be
specified in 1-bit units by pull-up resistor option register 4 (PU4)Note.
This port can also be used for flash memory programmer/debugger data I/O and clock output.
Reset signal generation sets port 4 to input mode.
Figures 5-9 and 5-10 show block diagrams of port 4.
Note When a tool is connected, the P40 and P41 pins cannot be connected to a pull-up resistor.
Caution When a tool is connected, the P40 pin cannot be used as a port pin.
When the on-chip debug function is used, the P41 pin can be used as follows by the mode setting on
the debugger.
1-line mode: can be used as a port (P41).
2-line mode: used as a TOOL1 pin and cannot be used as a port (P41).
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Figure 5-9. Block Diagram of P40 and P41
EVDD
WRPU
PU4
PU40, PU41
P-ch
Alternate
function
Selector
Internal bus
RD
WRPORT
Output latch
(P40, P41)
WRPM
Selector
P4
P40/TOOL0,
P41/TOOL1
PM4
PM40, PM41
Alternate
function
P4:
Port register 4
PU4:
Pull-up resistor option register 4
PM4:
Port mode register 4
RD:
Read signal
WR××: Write signal
Remark With products not provided with an EVDD or EVSS pin, replace EVDD with VDD, or replace EVSS with VSS.
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Figure 5-10. Block Diagram of P42 and P43
EVDD
WRPU
PU4
PU42, PU43
P-ch
Selector
Internal bus
RD
WRPORT
P4
Output latch
(P42, P43)
P42, P43
WRPM
PM4
PM42, PM43
P4:
Port register 4
PU4:
Pull-up resistor option register 4
PM4:
Port mode register 4
RD:
Read signal
WR××: Write signal
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5.2.6 Port 5
78K0R/KC3-L
78K0R/KC3-L (48-pin)
78K0R/KD3-L
78K0R/KE3-L
(μPD78F100y: y = 0 to 3)
(μPD78F100y: y = 1 to 3)
(μPD78F100y: y = 4 to 6)
(μPD78F100y: y = 7 to 9)
40-pin
44-pin
P50/TI06/TO06
√
√
√
P50
Note
P51/TI07/TO07
√
√
√
P51
Note
√
√
√
−
−
√
−
P52/RTC1HZ/
√
SLTI/SLTO
−
P53
Note TI06/TO06 and TI07/TO07 are shared only in the 78K0R/KC3-L and 78K0R/KD3-L. The 78K0R/KE3-L does not
have a sharing function.
Remark √: Mounted
Port 5 is an I/O port with an output latch. Port 5 can be set to the input mode or output mode in 1-bit units using port
mode register 5 (PM5). When the P50 to P53 pins are used as an input port, use of an on-chip pull-up resistor can be
specified in 1-bit units by pull-up resistor option register 5 (PU5).
This port can also be used for real-time counter correction clock output and timer I/O.
Reset signal generation sets port 5 to input mode.
Figures 5-11 to 5-13 show block diagrams of port 5.
Caution 1. To use P50/TI06/TO06 and P51/TI07/TO07 as a general-purpose port, set bits 6 and 7 (TO06 and
TO07) of timer output register 0 (TO0) and bits 6 and 7 (TOE06 and TOE07) of timer output enable
register 0 (TOE0) to “0”, which is the same as their default status setting.
2. To use P52/RTC1HZ/SLTI/SLTO as a general-purpose port, check which timer I/O pin of which
channel n is selected in the input switching control register (ISC) setting. Also, set bit n (TO0n) of
timer output register 0 (TO0) and bit n (TOE0n) of timer output enable register 0 (TOE0) to “0”,
which is the same setting as in the initial state of each.
3. In the case of the 78K0R/KC3-L (40-pin), be sure to clear bit2 of the PM5 register to “0” after the
reset release.
Remark
n = 0, 1
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Figure 5-11. Block Diagram of P50 and P51
(1) 78K0R/KE3-L
EVDD
WRPU
PU5
PU50, PU51
P-ch
Selector
Internal bus
RD
WRPORT
P5
Output latch
(P50, P51)
P50, P51
WRPM
PM5
PM50, PM51
(2) Products other than 78K0R/KE3-L
VDD
WRPU
PU5
PU50 and PU51
P-ch
Alternate
function
Selector
Internal bus
RD
WRPORT
P5
Output latch
(P50 and P51)
WRPM
P50/TI06/TO06,
P51/TI07/TO07
PM5
PM50 and PM51
Alternate
function
P5:
Port register 5
PU5:
Pull-up resistor option register 5
PM5:
Port mode register 5
RD:
Read signal
WR××: Write signal
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Figure 5-12. Block Diagram of P52
EVDD
WRPU
PU5
PU52
P-ch
ISC2
Selector
Channel 0 of TAUS
RD
Selector
Internal bus
Channel 1 of TAUS
ISC
ISC2
WRPORT
P5
Selector
Output latch
(P52)
WRPM
PM5
P52/RTC1HZ/SLTI/SLTO
PM52
Alternate
function
Channel 0 of TAUS
Channel 1 of TAUS
P5:
Port register 5
PU5:
Pull-up resistor option register 5
PM5:
Port mode register 5
RD:
Read signal
WR××: Write signal
ISC:
Input switch control register
Remark With products not provided with an EVDD or EVSS pin, replace EVDD with VDD, or replace EVSS with VSS.
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Figure 5-13. Block Diagram of P53
EVDD
WRPU
PU5
PU53
P-ch
Selector
Internal bus
RD
WRPORT
P5
Output latch
(P53)
P53
WRPM
PM5
PM53
P5:
Port register 5
PU5:
Pull-up resistor option register 5
PM5:
Port mode register 5
RD:
Read signal
WR××: Write signal
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5.2.7 Port 6
78K0R/KC3-L
78K0R/KC3-L (48-pin)
78K0R/KD3-L
78K0R/KE3-L
(μPD78F100y: y = 0 to 3)
(μPD78F100y: y = 1 to 3)
(μPD78F100y: y = 4 to 6)
(μPD78F100y: y = 7 to 9)
40-pin
44-pin
P60/SCL0
−
√
√
√
P61/SDA0
−
√
√
√
Remark √: Mounted
Port 6 is an I/O port with an output latch. Port 6 can be set to the input mode or output mode in 1-bit units using port
mode register 6 (PM6).
The output of the P60 and P61 pins is N-ch open-drain output (6 V tolerance).
This port can also be used for serial interface data I/O and clock I/O.
Reset signal generation sets port 6 to input mode.
Figure 5-14 shows block diagram of port 6.
Caution When using P60/SCL0 or P61/SDA0 as a general-purpose port, stop the operation of serial interface
IICA.
Figure 5-14. Block Diagram of P60 and P61
Alternate
function
Internal bus
Selector
RD
WRPORT
P6
Output latch
(P60, P61)
P60/SCL0,
P61/SDA0
WRPM
PM6
PM60, PM61
Alternate
function
P6:
Port register 6
PM6:
Port mode register 6
RD:
Read signal
WR××: Write signal
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5.2.8 Port 7
78K0R/KC3-L
78K0R/KC3-L (48-pin)
78K0R/KD3-L
78K0R/KE3-L
(μPD78F100y: y = 0 to 3)
(μPD78F100y: y = 1 to 3)
(μPD78F100y: y = 4 to 6)
(μPD78F100y: y = 7 to 9)
√
√
√
√
√
√
√
√
√
√
√
√
√
√
√
√
√
√
√
√
P75/KR5/SCK00
√
√
√
√
P76/KR6
−
−
√
√
P77/KR7
−
−
√
√
40-pin
P70/KR0/SO01/
44-pin
INTP4
P71/KR1/SI01/
INTP5
P72/KR2/
SCK01/INTP6
P73/KR3/SO00/
TxD0
P74/KR4/SI00/
RxD0
Remark √: Mounted
Port 7 is an I/O port with an output latch. Port 7 can be set to the input mode or output mode in 1-bit units using port
mode register 7 (PM7). When the P70 to P77 pins are used as an input port, use of an on-chip pull-up resistor can be
specified in 1-bit units by pull-up resistor option register 7 (PU7).
Input to the P71, P72, P74, and P75 pins can be specified through a normal input buffer or a TTL input buffer in 1-bit
units using port input mode register 7 (PIM7).
Output from the P70, P72, P73, and P75 pins can be specified as N-ch open-drain output (VDD tolerance) in 1-bit units
using port output mode register 7 (POM7).
This port can also be used for key return input, serial interface data I/O, clock I/O, and external interrupt request input.
Reset signal generation sets port 7 to input mode.
Figures 5-15 to 5-18 show block diagrams of port 7.
Caution To use P70/KR0/SO01/INTP4, P71/KR1/SI01/INTP5, P72/KR2/SCK01/INTP6, P73/KR3/SO00/TxD0,
P74/KR4/SI00/RxD0, P75/KR5/SCK00 as a general-purpose port, note the serial array unit setting. For
details, refer to Table 14-5 Relationship Between Register Settings and Pins (Channel 0: CSI00,
UART0 Transmission) and Table 14-6 Relationship Between Register Settings and Pins (Channel 1:
CSI01, UART0 Reception).
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Figure 5-15. Block Diagram of P70 and P73
EVDD
WRPU
PU7
PU70, PU73
P-ch
Alternate
function
Internal bus
Selector
RD
WRPORT
P7
Output latch
(P70, P73)
P70/KR0/SO01/INTP4,
P73/KR3/SO00/TxD0
WRPOM
POM7
POM70, POM73
WRPM
PM7
PM70, PM73
Alternate
function
P7:
Port register 7
PU7:
Pull-up resistor option register 7
POM7: Port output mode register 7
PM7:
Port mode register 7
RD:
Read signal
WR××: Write signal
Remark With products not provided with an EVDD or EVSS pin, replace EVDD with VDD, or replace EVSS with VSS.
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Figure 5-16. Block Diagram of P71 and P74
WRPIM
PIM7
PIM71, PIM74
EVDD
WRPU
PU7
P-ch
Alternate
function
CMOS
RD
Selector
Internal bus
PU71, PU74
TTL
WRPORT
P7
Output latch
(P71, P74)
WRPM
P71/KR1/SI01/INTP5,
P74/KR4/SI00/RxD0
PM7
PM71, PM74
P7:
Port register 7
PU7:
Pull-up resistor option register 7
PM7:
Port mode register 7
PIM7:
Port input mode register 7
RD:
Read signal
WR××: Write signal
Remark With products not provided with an EVDD or EVSS pin, replace EVDD with VDD, or replace EVSS with VSS.
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Figure 5-17. Block Diagram of P72 and P75
WRPIM
PIM7
PIM72, PIM75
EVDD
WRPU
PU7
PU72, PU75
P-ch
Alternate
function
CMOS
Selector
Internal bus
RD
TTL
WRPORT
P7
Output latch
(P72, P75)
WRPOM
P72/KR2/SCK01/INTP6,
P75/KR5/SCK00
POM7
POM72, POM75
WRPM
PM7
PM72, PM75
Alternate
function
P7:
Port register 7
PU7:
Pull-up resistor option register 7
PM7:
Port mode register 7
PIM7:
Port input mode register 7
POM7: Port output mode register 7
RD:
Read signal
WR××: Write signal
Remark With products not provided with an EVDD or EVSS pin, replace EVDD with VDD, or replace EVSS with VSS.
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Figure 5-18. Block Diagram of P76 and P77
EVDD
WRPU
PU7
PU76, PU77
P-ch
Alternate
function
Selector
Internal bus
RD
WRPORT
P7
Output latch
(P76, P77)
P76/KR6, P77/KR7
WRPM
PM7
PM76, PM77
P7:
Port register 7
PU7:
Pull-up resistor option register 7
PM7:
Port mode register 7
RD:
Read signal
WR××: Write signal
Remark With products not provided with an EVDD or EVSS pin, replace EVDD with VDD, or replace EVSS with VSS.
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5.2.9 Port 8
78K0R/KC3-L
78K0R/KC3-L (48-pin)
78K0R/KD3-L
78K0R/KE3-L
(μPD78F100y: y = 0 to 3)
(μPD78F100y: y = 1 to 3)
(μPD78F100y: y = 4 to 6)
(μPD78F100y: y = 7 to 9)
√
√
√
√
√
√
√
√
√
√
√
√
√
√
40-pin
P80/CMP0P/
44-pin
INTP3/PGAI
P81/CMP0M
P82/CMP1P/
−
√
INTP7
P83/CMP1M
√
Remark √: Mounted
Port 8 is an I/O port with an output latch. Port 8 can be set to the input mode or output mode in 1-bit units using port
mode register 8 (PM8).
Inputs to the P80 to P83 pins must be enabled or disabled in 1-bit units using port input mode register 8 (PIM8).
This port can also be used for an input voltage on the (+) sides of comparators 0 and 1, an input voltage on the (−)
sides of comparators 0 and 1, an external interrupt request input, and a programmable gain amplifier input.
Reset signal generation sets port 8 to analog input mode.
Figures 5-19 to 5-21 show block diagrams of port 8.
Caution
In the case of the 78K0R/KC3-L (40-pin), be sure to clear bit2 of the PM8 register to “0” after the reset
release.
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Figure 5-19. Block Diagram of P80
WRPIM
PIM8
PIM80
Alternate
function
Selector
Internal bus
RD
WRPORT
P8
Output latch
(P80)
P80/CMP0P/INTP3/PGAI
WRPM
PM8
PM80
Comparator,
programmable gain amplifier
P8:
Port register 8
PM8:
Port mode register 8
PIM8:
Port input mode register 8
RD:
Read signal
WR××: Write signal
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Figure 5-20. Block Diagram of P81 and P83
WRPIM
PIM8
PIM81, PIM83
Selector
Internal bus
RD
WRPORT
P8
Output latch
(P81, P83)
P81/CMP0M,
P83/CMP1M
WRPM
PM8
PM81, PM83
Comparator
P8:
Port register 8
PM8:
Port mode register 8
PIM8:
Port input mode register 8
RD:
Read signal
WR××: Write signal
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Figure 5-21. Block Diagram of P82
WRPIM
PIM8
PIM82
Alternate
function
Internal bus
Selector
RD
WRPORT
P8
Output latch
(P82)
P82/CMP1P/INTP7
WRPM
PM8
PM82
Comparator
P8:
Port register 8
PM8:
Port mode register 8
PIM8:
Port input mode register 8
RD:
Read signal
WR××: Write signal
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5.2.10 Port 12
78K0R/KC3-L
78K0R/KC3-L (48-pin)
78K0R/KD3-L
78K0R/KE3-L
(μPD78F100y: y = 0 to 3)
(μPD78F100y: y = 1 to 3)
(μPD78F100y: y = 4 to 6)
(μPD78F100y: y = 7 to 9)
√
√
√
√
P121/X1
√
√
√
√
P122/X2/
√
√
√
√
40-pin
P120/INTP0/
44-pin
EXLVI
EXCLK
P123/XT1
−
√
√
√
√
P124/XT2
−
√
√
√
√
Remark √: Mounted
P120 is an I/O port with an output latch. Port 12 can be set to the input mode or output mode in 1-bit units using port
mode register 12 (PM12). When used as an input port, use of an on-chip pull-up resistor can be specified by pull-up
resistor option register 12 (PU12).
P121 to P124 are input ports.
This port can also be used for external interrupt request input, potential input for external low-voltage detection,
connecting resonator for main system clock, connecting resonator for subsystem clock, and external clock input for main
system clock.
Reset signal generation sets port 12 to input mode.
Figures 5-22 to 5-24 show block diagrams of port 12.
Caution
The function setting on P121 to P124 is available only once after the reset release. The port once set
for connection to an oscillator cannot be used as an input port unless the reset is performed.
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Figure 5-22. Block Diagram of P120
EVDD
WRPU
PU12
PU120
P-ch
Alternate
function
Selector
Internal bus
RD
WRPORT
P12
Output latch
(P120)
P120/INTP0/EXLVI
WRPM
PM12
PM120
P12:
Port register 12
PU12:
Pull-up resistor option register 12
PM12:
Port mode register 12
RD:
Read signal
WR××: Write signal
Remark With products not provided with an EVDD or EVSS pin, replace EVDD with VDD, or replace EVSS with VSS.
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Figure 5-23. Block Diagram of P121 and P122
Clock generator
CMC
OSCSEL
RD
Internal bus
P122/X2/EXCLK
CMC
EXCLK, OSCSEL
RD
P121/X1
CMC:
Clock operation mode control register
RD:
Read signal
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Figure 5-24. Block Diagram of P123 and P124
Clock generator
CMC
OSCSELS
RD
Internal bus
P124/XT2
CMC
OSCSELS
RD
P123/XT1
CMC:
Clock operation mode control register
RD:
Read signal
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5.2.11 Port 14
78K0R/KC3-L
78K0R/KC3-L (48-pin)
78K0R/KD3-L
78K0R/KE3-L
(μPD78F100y: y = 0 to 3)
(μPD78F100y: y = 1 to 3)
(μPD78F100y: y = 4 to 6)
(μPD78F100y: y = 7 to 9)
40-pin
44-pin
P140/PCLBUZ0
−
√
√
√
P141/PCLBUZ1
−
−
−
√
Remark √: Mounted
P140 is a port dedicated to output and is provided with an output latch.
P141 is an I/O port with an output latch. P141 can be set to the input mode or output mode in 1-bit units using port
mode register 14 (PM14). When the P141 pin is used as an input port, use of an on-chip pull-up resistor can be specified
in 1-bit units by pull-up resistor option register 14 (PU14).
This port can also be used for clock/buzzer output.
Reset signal generation sets P141 to input mode.
Figures 5-25 and 5-26 show block diagrams of port 14.
Caution To use P140/PCLBUZ0 and P141/PCLBUZ1 as general-purpose ports, set bit 7 of clock output select
registers 0 and 1 (CKS0, CKS1) to “0”, which is the same as their default status setting.
Figure 5-25. Block Diagram of P140
Internal bus
RD
WRPORT
P140
Output latch
(P140)
P140/PCLBUZ0
Alternate
function
P14:
Port register 14
RD:
Read signal
WR××: Write signal
Remark
The P140 pin outputs a low level when it is used as a port function pin and a reset is effected. If P140 is set
to output a high level, the output signal of P140 can be dummy-output as the CPU reset signal.
Reset signal
P140
Set by software
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Figure 5-26. Block Diagram of P141
EVDD
WRPU
PU14
PU141
P-ch
RD
Internal bus
Selector
WRPORT
P14
Output latch
(P141)
WRPM
P141/PCLBUZ1
PM14
PM141
Alternate
function
P14:
Port register 14
PU14:
Pull-up resistor option register 14
PM14:
Port mode register 14
RD:
Read signal
WR××: Write signal
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5.2.12 Port 15
78K0R/KC3-L
78K0R/KC3-L (48-pin)
78K0R/KD3-L
78K0R/KE3-L
(μPD78F100y: y = 0 to 3)
(μPD78F100y: y = 1 to 3)
(μPD78F100y: y = 4 to 6)
(μPD78F100y: y = 7 to 9)
40-pin
44-pin
P150/ANI8
√
√
√
√
P151/ANI9
√
√
√
√
P152/ANI10
−
√
√
√
P153/ANI11
−
−
−
√
Remark √: Mounted
Port 15 is an I/O port with an output latch. Port 15 can be set to the input mode or output mode in 1-bit units using port
mode register 15 (PM15).
This port can also be used for A/D converter analog input.
To use P150/ANI8 to P153/ANI11 as digital input pins, set them in the digital I/O mode by using the A/D port
configuration register (ADPC) and in the input mode by using the PM15 register. Use these pins starting from the lower bit.
To use P150/ANI8 to P153/ANI11 as digital output pins, set them in the digital I/O mode by using the ADPC register
and in the output mode by using the PM15 register.
Table 5-6. Setting Functions of P150/ANI8 to P153/ANI11 Pins
ADPC Register
Digital I/O selection
Analog input selection
PM15 Register
ADS Register
P150/ANI8 to P153/ANI11 Pins
Input mode
−
Digital input
Output mode
−
Digital output
Input mode
Selects ANI.
Analog input (to be converted)
Does not select ANI.
Analog input (not to be converted)
Output mode
Selects ANI.
Setting prohibited
Does not select ANI.
All P150/ANI8 to P153/ANI11 are set in the digital input mode when the reset signal is generated.
Figure 5-27 shows block diagram of port 15.
Caution Make the AVREF pin the same potential as the VDD pin when port 15 is used as a digital port.
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Figure 5-27. Block Diagram of P150 to P153
Selector
Internal bus
RD
WRPORT
P15
Output latch
(P150 to P153)
P150/ANI8 to
P153/ANI11
WRPM
PM15
PM150 to PM153
A/D converter
P15:
Port register 15
PM15:
Port mode register 15
RD:
Read signal
WR××: Write signal
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5.3 Registers Controlling Port Function
Port functions are controlled by the following six types of registers.
• Port mode registers (PMxx)
• Port registers (Pxx)
• Pull-up resistor option registers (PUxx)
• Port input mode registers (PIM3, PIM7, PIM8)
• Port output mode registers (POM3, POM7)
• A/D port configuration register (ADPC)
(1) Port mode registers (PMxx)
These registers specify input or output mode for the port in 1-bit units.
These registers can be set by a 1-bit or 8-bit memory manipulation instruction.
Reset signal generation sets these registers to FFH (PM13 is set to FEH).
When port pins are used as alternate-function pins, set the port mode register by referencing 5.5 Settings of Port
Mode Register and Output Latch When Using Alternate Function.
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Figure 5-28. Format of Port Mode Register (78K0R/KC3-L (40-pin))
Symbol
7
6
5
4
3
2
1
0
Address
After reset
R/W
PM1
1
1
1
1
PM13
PM12
PM11
PM10
FFF21H
FFH
R/W
PM2
PM27
PM26
PM25
PM24
PM23
PM22
PM21
PM20
FFF22H
FFH
R/W
PM3
1
1
1
1
1
PM32
PM31
PM30
FFF23H
FFH
R/W
PM4
1
1
1
1
1
1
PM41
PM40
FFF24H
FFH
R/W
PM5
1
1
1
1
1
0
PM51
PM50
FFF25H
FFH
R/W
PM7
1
1
PM75
PM74
PM73
PM72
PM71
PM70
FFF27H
FFH
R/W
PM8
1
1
1
1
PM83
0
PM81
PM80
FFF28H
FFH
R/W
PM12
1
1
1
1
1
1
1
PM120
FFF2CH
FFH
R/W
PM15
1
1
1
1
1
1
PM151
PM150
FFF2FH
FFH
R/W
Pmn pin I/O mode selection
PMmn
(m = 1 to 5, 7, 8, 12, 15; n = 0 to 7)
0
Output mode (output buffer on)
1
Input mode (output buffer off)
Cautions 1.
Be sure to set bits 4 to 7 of the PM1 register, bits 3 to 7 of the PM3 register, bits 2 to 7 of
the PM4 register, bits 3 to 7 of the PM5 register, bits 6 and 7 of the PM7 register, bits 4 to 7
of the PM8 register, bits 1 to 7 of the PM12 register, and bits 2 to 7 of the PM15 register to 1.
2.
Be sure to clear bit2 of the PM5 register and bit 2 of the PM8 register to “0” after the reset
release.
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Figure 5-29. Format of Port Mode Register (78K0R/KC3-L (44-pin and 48-pin))
Symbol
7
6
5
4
3
2
1
0
Address
After reset
R/W
PM1
1
1
1
1
PM13
PM12
PM11
PM10
FFF21H
FFH
R/W
PM2
PM27
PM26
PM25
PM24
PM23
PM22
PM21
PM20
FFF22H
FFH
R/W
PM3
1
1
1
1
1
PM32
PM31
PM30
FFF23H
FFH
R/W
PM4
1
1
1
1
1
1
PM41
PM40
FFF24H
FFH
R/W
PM5
1
1
1
1
1
PM52
PM51
PM50
FFF25H
FFH
R/W
1
1
1
1
1
1
FFF26H
FFH
R/W
PM7
1
1
PM75
PM74
PM73
PM72
PM71
PM70
FFF27H
FFH
R/W
PM8
1
1
1
1
PM83
PM82
PM81
PM80
FFF28H
FFH
R/W
PM12
1
1
1
1
1
1
1
PM120
FFF2CH
FFH
R/W
PM15
1
1
1
1
1
PM151
PM150
FFF2FH
FFH
R/W
PM6
Note
PM152
Note
PM61
Note
Note
PM60
Pmn pin I/O mode selection
PMmn
(m = 1 to 8, 12, 15; n = 0 to 7)
0
Output mode (output buffer on)
1
Input mode (output buffer off)
Note 48-pin products only.
Caution Be sure to set bits 4 to 7 of the PM1 register, bits 3 to 7 of the PM3 register, bits 2 to 7 of the
PM4 register, bits 3 to 7 of the PM5 register, bits 2 to 7 of the PM6 register, bits 6 and 7 of the
PM7 register, bits 4 to 7 of the PM8 register, bits 1 to 7 of the PM12 register, and bits 3 to 7 of
the PM15 register to 1.
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Figure 5-30. Format of Port Mode Register (78K0R/KD3-L)
Symbol
7
6
5
4
3
2
1
0
Address
After reset
R/W
PM0
1
1
1
1
1
1
PM01
PM00
FFF20H
FFH
R/W
PM1
1
1
1
1
PM13
PM12
PM11
PM10
FFF21H
FFH
R/W
PM2
PM27
PM26
PM25
PM24
PM23
PM22
PM21
PM20
FFF22H
FFH
R/W
PM3
1
1
1
1
1
PM32
PM31
PM30
FFF23H
FFH
R/W
PM4
1
1
1
1
1
1
PM41
PM40
FFF24H
FFH
R/W
PM5
1
1
1
1
1
PM52
PM51
PM50
FFF25H
FFH
R/W
PM6
1
1
1
1
1
1
PM61
PM60
FFF26H
FFH
R/W
PM7
PM77
PM76
PM75
PM74
PM73
PM72
PM71
PM70
FFF27H
FFH
R/W
PM8
1
1
1
1
PM83
PM82
PM81
PM80
FFF28H
FFH
R/W
PM12
1
1
1
1
1
1
1
PM120
FFF2CH
FFH
R/W
PM15
1
1
1
1
1
PM152
PM151
PM150
FFF2FH
FFH
R/W
Pmn pin I/O mode selection
PMmn
(m = 0 to 8, 12, 15; n = 0 to 7)
0
Output mode (output buffer on)
1
Input mode (output buffer off)
Caution Be sure to set bits 2 to 7 of the PM0 register, bits 4 to 7 of the PM1 register, bits 3 to 7 of the
PM3 register, bits 2 to 7 of the PM4 register, bits 3 to 7 of the PM5 register, bits 2 to 7 of the
PM6 register, bits 4 to 7 of the PM8 register, bits 1 to 7 of the PM12 register, and bits 3 to 7 of
the PM15 register to 1.
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Figure 5-31. Format of Port Mode Register (78K0R/KE3-L)
Symbol
7
6
5
4
3
2
1
0
Address
After reset
R/W
PM0
1
1
1
1
1
1
PM01
PM00
FFF20H
FFH
R/W
PM1
PM17
PM16
PM15
PM14
PM13
PM12
PM11
PM10
FFF21H
FFH
R/W
PM2
PM27
PM26
PM25
PM24
PM23
PM22
PM21
PM20
FFF22H
FFH
R/W
PM3
1
1
1
1
PM33
PM32
PM31
PM30
FFF23H
FFH
R/W
PM4
1
1
1
1
PM43
PM42
PM41
PM40
FFF24H
FFH
R/W
PM5
1
1
1
1
PM53
PM52
PM51
PM50
FFF25H
FFH
R/W
PM6
1
1
1
1
1
1
PM61
PM60
FFF26H
FFH
R/W
PM7
PM77
PM76
PM75
PM74
PM73
PM72
PM71
PM70
FFF27H
FFH
R/W
PM8
1
1
1
1
PM83
PM82
PM81
PM80
FFF28H
FFH
R/W
PM12
1
1
1
1
1
1
1
PM120
FFF2CH
FFH
R/W
PM14
1
1
1
1
1
1
PM141
0
FFF2EH
FEH
R/W
PM15
1
1
1
1
PM153
PM152
PM151
PM150
FFF2FH
FFH
R/W
Pmn pin I/O mode selection
PMmn
(m = 0 to 8, 12, 14, 15; n = 0 to 7)
0
Output mode (output buffer on)
1
Input mode (output buffer off)
Caution Be sure to set bits 2 to 7 of the PM0 register, bits 4 to 7 of the PM3 register, bits 4 to 7 of the
PM4 register, bits 4 to 7 of the PM5 register, bits 2 to 7 of the PM6 register, bits 4 to 7 of the
PM8 register, bits 1 to 7 of the PM12 register, bits 2 to 7 of the PM14 register, and bits 4 to 7 of
the PM15 register to 1. Also, be sure to set bit 0 of the PM14 register to 0.
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(2) Port registers (Pxx)
These registers set the output latch value of a port.
If the data is read in the input mode, the pin level is read. If it is read in the output mode, the output latch value is
readNote.
These registers can be set by a 1-bit or 8-bit memory manipulation instruction.
Reset signal generation clears these registers to 00H.
Note It is always 0 and never a pin level that is read out if a port is read during the input mode when P2 and P15 are
set to function as an analog input for a A/D converter.
Figure 5-32. Format of Port Register (78K0R/KC3-L (40-pin))
Symbol
7
6
5
4
3
2
1
0
Address
P1
0
0
0
0
P13
P12
P11
P10
FFF01H
00H (output latch) R/W
P2
P27
P26
P25
P24
P23
P22
P21
P20
FFF02H
00H (output latch) R/W
P3
0
0
0
0
0
P32
P31
P30
FFF03H
00H (output latch) R/W
P4
0
0
0
0
0
0
P41
P40
FFF04H
00H (output latch) R/W
P5
0
0
0
0
0
0
P51
P50
FFF05H
00H (output latch) R/W
P7
0
0
P75
P74
P73
P72
P71
P70
FFF07H
00H (output latch) R/W
P8
0
0
0
0
P83
0
P81
P80
FFF08H
00H (output latch) R/W
P12
0
0
0
0
0
P122
P121
P120
FFF0CH
P15
0
0
0
0
0
0
P151
P150
FFF0FH
Pmn
After reset
Undefined
R/W
Note2
R/W
00H (output latch) R/W
m = 1 to 8, 12, 14, 15 ; n = 0 to 7
Output data control (in output mode)
Input data read (in input mode)
0
Output 0
Input low level
1
Output 1
Input high level
Note P121 and P122 are read-only.
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Figure 5-33. Format of Port Register (78K0R/KC3-L (44-pin and 48-pin))
Symbol
7
6
5
4
3
2
1
0
Address
P1
0
0
0
0
P13
P12
P11
P10
FFF01H
00H (output latch) R/W
P2
P27
P26
P25
P24
P23
P22
P21
P20
FFF02H
00H (output latch) R/W
P3
0
0
0
0
0
P32
P31
P30
FFF03H
00H (output latch) R/W
P4
0
0
0
0
0
0
P41
P40
FFF04H
00H (output latch) R/W
P5
0
0
0
0
0
P52
P51
P50
FFF05H
00H (output latch) R/W
0
0
0
0
0
0
FFF06H
00H (output latch) R/W
P7
0
0
P75
P74
P73
P72
P71
P70
FFF07H
00H (output latch) R/W
P8
0
0
0
0
P83
P82
P81
P80
FFF08H
00H (output latch) R/W
P12
0
0
0
P124
P123
P122
P121
P120
FFF0CH
0
0
0
0
0
0
0
0
0
0
0
0
P152
P6
Note1
P14
Note1
P15
Pmn
P61
Note1
Note1
P151
P60
Note1
P140
Note1
P150
After reset
Undefined
R/W
Note2
R/W
FFF0EH
00H (output latch) R/W
FFF0FH
00H (output latch) R/W
m = 1 to 8, 12, 14, 15 ; n = 0 to 7
Output data control (in output mode)
Input data read (in input mode)
0
Output 0
Input low level
1
Output 1
Input high level
Notes 1. P121 to P124 are read-only.
2. 48-pin products only.
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Figure 5-34. Format of Port Register (78K0R/KD3-L)
Symbol
7
6
5
4
3
2
1
0
Address
P0
0
0
0
0
0
0
P01
P00
FFF00H
00H (output latch) R/W
P1
0
0
0
0
P13
P12
P11
P10
FFF01H
00H (output latch) R/W
P2
P27
P26
P25
P24
P23
P22
P21
P20
FFF02H
00H (output latch) R/W
P3
0
0
0
0
0
P32
P31
P30
FFF03H
00H (output latch) R/W
P4
0
0
0
0
0
0
P41
P40
FFF04H
00H (output latch) R/W
P5
0
0
0
0
0
P52
P51
P50
FFF05H
00H (output latch) R/W
P6
0
0
0
0
0
0
P61
P60
FFF06H
00H (output latch) R/W
P7
P77
P76
P75
P74
P73
P72
P71
P70
FFF07H
00H (output latch) R/W
P8
0
0
0
0
P83
P82
P81
P80
FFF08H
00H (output latch) R/W
P12
0
0
0
P124
P123
P122
P121
P120
FFF0CH
P14
0
0
0
0
0
0
0
P140
FFF0EH
00H (output latch) R/W
P15
0
0
0
0
0
P152
P151
P150
FFF0FH
00H (output latch) R/W
Pmn
After reset
Undefined
R/W
R/W
Note
m = 0 to 8, 12, 14, 15 ; n = 0 to 7
Output data control (in output mode)
Input data read (in input mode)
0
Output 0
Input low level
1
Output 1
Input high level
Note P121 to P124 are read-only.
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Figure 5-35. Format of Port Register (78K0R/KE3-L)
Symbol
7
6
5
4
3
2
1
0
Address
P0
0
0
0
0
0
0
P01
P00
FFF00H
00H (output latch) R/W
P1
P17
P16
P15
P14
P13
P12
P11
P10
FFF01H
00H (output latch) R/W
P2
P27
P26
P25
P24
P23
P22
P21
P20
FFF02H
00H (output latch) R/W
P3
0
0
0
0
P33
P32
P31
P30
FFF03H
00H (output latch) R/W
P4
0
0
0
0
P43
P42
P41
P40
FFF04H
00H (output latch) R/W
P5
0
0
0
0
P53
P52
P51
P50
FFF05H
00H (output latch) R/W
P6
0
0
0
0
0
0
P61
P60
FFF06H
00H (output latch) R/W
P7
P77
P76
P75
P74
P73
P72
P71
P70
FFF07H
00H (output latch) R/W
P8
0
0
0
0
P83
P82
P81
P80
FFF08H
00H (output latch) R/W
P12
0
0
0
P124
P123
P122
P121
P120
FFF0CH
P14
0
0
0
0
0
0
P141
P140
FFF0EH
00H (output latch) R/W
P15
0
0
0
0
P153
P152
P151
P150
FFF0FH
00H (output latch) R/W
Pmn
After reset
Undefined
R/W
R/W
Note
m = 0 to 8, 12, 14, 15 ; n = 0 to 7
Output data control (in output mode)
Input data read (in input mode)
0
Output 0
Input low level
1
Output 1
Input high level
Note P121 to P124 are read-only.
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(3) Pull-up resistor option registers (PUxx)
These registers specify whether the on-chip pull-up resistors are to be used or not. On-chip pull-up resistors can be
used in 1-bit units only for the bits set to input mode of the pins to which the use of an on-chip pull-up resistor has
been specified in these registers. On-chip pull-up resistors cannot be connected to bits set to output mode and bits
used as alternate-function output pins, regardless of the settings of these registers.
These registers can be set by a 1-bit or 8-bit memory manipulation instruction.
Reset signal generation clears these registers to 00H.
Figure 5-36. Format of Pull-up Resistor Option Register (78K0R/KC3-L)
Symbol
7
6
5
4
3
2
1
0
Address
After reset
R/W
PU1
0
0
0
0
PU13
PU12
PU11
PU10
F0031H
00H
R/W
PU3
0
0
0
0
0
PU32
PU31
PU30
F0033H
00H
R/W
PU4
0
0
0
0
0
0
PU41
PU40
F0034H
00H
R/W
PU5
0
0
0
0
0
PU52
PU51
PU50
F0035H
00H
R/W
PU7
0
0
PU75
PU74
PU73
PU72
PU71
PU70
F0037H
00H
R/W
PU12
0
0
0
0
0
0
0
PU120
F003CH
00H
R/W
Note
Pmn pin on-chip pull-up resistor selection
PUmn
(m = 1, 3 to 5, 7, 12 ; n = 0 to 5)
0
On-chip pull-up resistor not connected
1
On-chip pull-up resistor connected
Note In the case of the 40-pin product, be sure to clear PU52 bit of the PU5 register to “0”.
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Figure 5-37. Format of Pull-up Resistor Option Register (78K0R/KD3-L)
Symbol
7
6
5
4
3
2
1
0
Address
After reset
R/W
PU0
0
0
0
0
0
0
PU01
PU00
F0030H
00H
R/W
PU1
0
0
0
0
PU13
PU12
PU11
PU10
F0031H
00H
R/W
PU3
0
0
0
0
0
PU32
PU31
PU30
F0033H
00H
R/W
PU4
0
0
0
0
0
0
PU41
PU40
F0034H
00H
R/W
PU5
0
0
0
0
0
PU52
PU51
PU50
F0035H
00H
R/W
PU7
PU77
PU76
PU75
PU74
PU73
PU72
PU71
PU70
F0037H
00H
R/W
PU12
0
0
0
0
0
0
0
PU120
F003CH
00H
R/W
Pmn pin on-chip pull-up resistor selection
PUmn
(m = 0, 1, 3 to 5, 7, 12 ; n = 0 to 7)
0
On-chip pull-up resistor not connected
1
On-chip pull-up resistor connected
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Figure 5-38. Format of Pull-up Resistor Option Register (78K0R/KE3-L)
Symbol
7
6
5
4
3
2
1
0
Address
After reset
R/W
PU0
0
0
0
0
0
0
PU01
PU00
F0030H
00H
R/W
PU1
PU17
PU16
PU15
PU14
PU13
PU12
PU11
PU10
F0031H
00H
R/W
PU3
0
0
0
0
PU33
PU32
PU31
PU30
F0033H
00H
R/W
PU4
0
0
0
0
PU43
PU42
PU41
PU40
F0034H
00H
R/W
PU5
0
0
0
0
PU53
PU52
PU51
PU50
F0035H
00H
R/W
PU7
PU77
PU76
PU75
PU74
PU73
PU72
PU71
PU70
F0037H
00H
R/W
PU12
0
0
0
0
0
0
0
PU120
F003CH
00H
R/W
PU14
0
0
0
0
0
0
PU141
0
F003EH
00H
R/W
Pmn pin on-chip pull-up resistor selection
PUmn
(m = 0, 1, 3 to 5, 7, 12, 14 ; n = 0 to 7)
0
On-chip pull-up resistor not connected
1
On-chip pull-up resistor connected
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(4) Port input mode registers (PIM3, PIM7, PIM8)
The PIM3 and PIM7 registers set the input buffer of P31, P32, P71, P72, P74, or P75 in 1-bit units.
TTL input buffer can be selected during serial communication with an external device of the different potential.
The PIM8 register is used to enable or disable the digital inputs to P80 to P83 in 1-bit units.
When using a
comparator or a programmable gain amplifier, the digital inputs are disabled (used as analog input) by software
processing. To use port functions and alternative functions, the digital inputs must be enabled, because they are
disabled (used as analog input) by default.
These registers can be set by a 1-bit or 8-bit memory manipulation instruction.
Reset signal generation clears these registers to 00H.
Figure 5-39. Format of Port Input Mode Register
Symbol
7
6
5
4
3
2
1
0
Address
After reset
R/W
PIM3
0
0
0
0
0
PIM32
PIM31
0
F0043H
00H
R/W
PIM7
0
0
PIM75
PIM74
0
PIM72
PIM71
0
F0047H
00H
R/W
PIM8
0
0
0
0
PIM83
PIM81
PIM80
F0048H
00H
R/W
PIM82
Note
Pmn pin input buffer selection
PIMmn
(m = 3 and 7; n = 1, 2, 4, 5)
0
Normal input buffer
1
TTL input buffer
P8n pin digital input buffer selection
PIM8n
(n = 0 to 3)
0
Disables digital input (used as analog input)
1
Enables digital input
Note In the case of the 40-pin product, be sure to clear PIM82 bit of the PIM8 register to “0”.
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(5) Port output mode registers (POM3, POM7)
These registers set the output mode of P30 to P32, P70, P72, P73, or P75 in 1-bit units.
N-ch open drain output (VDD tolerance) mode can be selected during serial communication with an external device of
2
the different potential, and for the SDA10 pin during simplified I C communication with an external device of the same
potential.
These registers can be set by a 1-bit or 8-bit memory manipulation instruction.
Reset signal generation clears these registers to 00H.
Figure 5-40. Format of Port Output Mode Register
Symbol
7
6
5
4
3
2
1
0
Address
After reset
R/W
POM3
0
0
0
0
0
POM32
POM31
POM30
F0053H
00H
R/W
POM7
0
0
POM75
0
POM73
POM72
0
POM70
F0057H
00H
R/W
Pmn pin output mode selection
POMmn
(m = 3 and 7; n = 0 to 3 and 5)
0
Normal output mode
1
N-ch open-drain output (VDD tolerance) mode
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(6) A/D port configuration register (ADPC)
This register switches the ANI0/P20 to ANI7/P27 and ANI8/P150 to ANI11/P153 pins to digital I/O of port or analog
input of A/D converter.
The ADPC register can be set by an 8-bit memory manipulation instruction.
Reset signal generation sets this register to 10H.
Figure 5-41. Format of A/D Port Configuration Register (ADPC)
Address: F0017H
After reset: 10H
R/W
Symbol
7
6
5
4
3
2
1
0
ADPC
0
0
0
ADPC4
ADPC3
ADPC2
ADPC1
ADPC0
ADPC4 ADPC3 ADPC2 ADPC1 ADPC0
Analog input (A)/digital I/O (D) switching
Port 15
Port 2
ANI11 ANI10 ANI9 ANI8 ANI7 ANI6 ANI5 ANI4 ANI3 ANI2 ANI1 ANI0
/P153 /P152 /P151 /P150 /P27 /P26 /P25 /P24 /P23 /P22 /P21 /P20
0
0
0
0
0
A
A
A
A
A
A
A
A
A
A
A
A
0
0
0
0
1
A
A
A
A
A
A
A
A
A
A
A
D
0
0
0
1
0
A
A
A
A
A
A
A
A
A
A
D
D
0
0
0
1
1
A
A
A
A
A
A
A
A
A
D
D
D
0
0
1
0
0
A
A
A
A
A
A
A
A
D
D
D
D
0
0
1
0
1
A
A
A
A
A
A
A
D
D
D
D
D
0
0
1
1
0
A
A
A
A
A
A
D
D
D
D
D
D
0
0
1
1
1
A
A
A
A
A
D
D
D
D
D
D
D
0
1
0
0
0
A
A
A
A
D
D
D
D
D
D
D
D
0
1
0
0
1
A
A
A
D
D
D
D
D
D
D
D
D
0
1
0
1
0
A
A
D
D
D
D
D
D
D
D
D
D
0
1
0
1
1
A
D
D
D
D
D
D
D
D
D
D
D
1
0
0
0
0
D
D
D
D
D
D
D
D
D
D
D
D
Other than the above
Setting prohibited
Cautions 1. Set a channel to be used for A/D conversion in the input mode by using port mode register 2
and 15 (PM2, PM15).
2. Do not set the pin that is set by the ADPC register as digital I/O by the analog input channel
specification register (ADS).
3. Be sure to first set the ADCEN bit of peripheral enable register 0 (PER0) to 1 when setting up
the ADPC register. If ADCEN = 0, writing to the ADPC register is ignored and specified
values are returned to the initial values.
Remark P20/ANI0 to P27/ANI7, P150/ANI8, and P151/ANI9: 78K0R/KC3-L (40-pin, 44-pin)
P20/ANI0 to P27/ANI7, P150/ANI8 to P152/ANI10: 78K0R/KC3-L (48-pin), 78K0R/KD3-L
P20/ANI0 to P27/ANI7, P150/ANI8 to P153/ANI11: 78K0R/KE3-L
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5.4 Port Function Operations
Port operations differ depending on whether the input or output mode is set, as shown below.
5.4.1 Writing to I/O port
(1) Output mode
A value is written to the output latch by a transfer instruction, and the output latch contents are output from the pin.
Once data is written to the output latch, it is retained until data is written to the output latch again.
The data of the output latch is cleared when a reset signal is generated.
(2) Input mode
A value is written to the output latch by a transfer instruction, but since the output buffer is off, the pin status does not
change.
Once data is written to the output latch, it is retained until data is written to the output latch again.
The data of the output latch is cleared when a reset signal is generated.
5.4.2 Reading from I/O port
(1) Output mode
The output latch contents are read by a transfer instruction. The output latch contents do not change.
(2) Input mode
The pin status is read by a transfer instruction. The output latch contents do not change.
5.4.3 Operations on I/O port
(1) Output mode
An operation is performed on the output latch contents, and the result is written to the output latch. The output latch
contents are output from the pins.
Once data is written to the output latch, it is retained until data is written to the output latch again.
The data of the output latch is cleared when a reset signal is generated.
(2) Input mode
The pin level is read and an operation is performed on its contents. The result of the operation is written to the output
latch, but since the output buffer is off, the pin status does not change.
The data of the output latch is cleared when a reset signal is generated.
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5.4.4 Connecting to external device with different power potential (2.5 V, 3 V)
When ports 3 and 7 operate with VDD = 4.0 V to 5.5 V, I/O connections with an external device that operates on a 2.5V
or 3 V power supply voltage are possible.
Regarding inputs, normal input (CMOS)/TTL switching is possible on a bit-by-bit basis by port input mode registers 3
and 7 (PIM3 and PIM7).
Moreover, regarding outputs, different power potentials can be supported by switching the output buffer to the N-ch
open drain (VDD withstand voltage) by port output mode registers 3 and 7 (POM3 and POM7).
(1) Setting procedure when using I/O pins of UART0, UART1 CSI00, CSI01, and CSI10 functions
(a) Use as 2.5V or 3 V input port
<1> After reset release, the port mode is the input mode (Hi-Z).
<2> If pull-up is needed, externally pull up the pin to be used (on-chip pull-up resistor cannot be used).
In case of UART0:
P74
In case of UART1:
P31
In case of CSI00:
P74, P75
In case of CSI01:
P71, P72
In case of CSI10:
P31, P32
<3> Set the corresponding bit of the PIM3 and PIM7 registers to 1 to switch to the TTL input buffer.
<4> VIH/VIL operates on a 2.5V or 3 V operating voltage.
(b) Use as 2.5V or 3 V output port
<1> After reset release, the port mode changes to the input mode (Hi-Z).
<2> Pull up externally the pin to be used (on-chip pull-up resistor cannot be used).
In case of UART0:
P73
In case of UART1:
P30
In case of CSI00:
P73, P75
In case of CSI01:
P70, P72
In case of CSI10:
P30, P32
<3> Set the output latch of the corresponding port to 1.
<4> Set the corresponding bit of the POM3 and POM7 registers to 1 to set the N-ch open drain output (VDD
withstand voltage) mode.
<5> Set the output mode by manipulating the PM3 and PM7 registers.
At this time, the output data is high level, so the pin is in the Hi-Z state.
<6> Communication is started by setting the serial array unit.
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(2) Setting procedure when using I/O pins of simplified IIC10 functions
<1> After reset release, the port mode is the input mode (Hi-Z).
<2> Externally pull up the pin to be used (on-chip pull-up resistor cannot be used).
In case of simplified IIC10:
P31, P32
<3> Set the output latch of the corresponding port to 1.
<4> Set the corresponding bit of the POM3 register to 1 to set the N-ch open drain output (VDD withstand
voltage) mode.
<5> Set the corresponding bit of the PM3 register to the output mode (data I/O is possible in the output mode).
At this time, the output data is high level, so the pin is in the Hi-Z state.
2
<6> Enable the operation of the serial array unit and set the mode to the simplified I C mode.
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5.5 Settings of Port Mode Register and Output Latch When Using Alternate Function
To use the alternate function of a port pin, set the port mode register and output latch as shown in Table 5-7.
Table 5-7. Settings of Port Mode Register and Output Latch When Using Alternate Function (1/2)
Pin Name
Alternate Function
Function Name
PIM8
PM××
P××
I/O
P00
TI00
Input
−
1
×
P01
TO00
Output
−
0
0
P10
TI02
Input
−
1
×
TO02
Output
−
0
0
TI03
Input
−
1
×
TO03
Output
−
0
0
TI04
Input
−
1
×
TO04
Output
−
0
0
RTCDIV
Output
−
0
0
RTCCL
Output
−
0
0
TI05
Input
−
1
×
Output
−
0
0
Input
−
1
×
P11
P12
P13
TO05
P14
Note 1
TI06
Note 1
TO06
P15
Note 1
TI07
Note 1
TO07
P20 to P27
Note 2
P30
P31
P32
P40
P41
P50
Note 1
−
0
0
−
1
×
Output
−
0
0
Input
−
1
×
SO10
Output
−
0
1
Output
−
0
1
SI10
Input
−
1
×
RxD1
Input
−
1
×
SDA10
I/O
−
0
1
INTP1
Input
−
1
×
SCK10
Input
−
1
×
Output
−
0
1
SCL10
I/O
−
0
1
INTP2
Input
−
1
×
TOOL0
I/O
−
×
×
TOOL1
Output
−
×
×
Input
−
1
×
Output
−
0
0
Input
−
1
×
Output
−
0
0
Note 1
TI07
×:
Note 1
Note 1
TO07
Remark
Note 2
Output
Input
TxD1
TI06
Note 1
Note 1
ANI0 to ANI7
TO06
P51
Note 1
Note 1
don’t care
PM××: Port mode register
P××:
Port output latch
(Note is listed on the next page after next.)
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Table 5-7. Settings of Port Mode Register and Output Latch When Using Alternate Function (2/2)
Pin Name
Alternate Function
Function Name
P52
PIM8
PM××
P××
I/O
RTC1HZ
Output
−
0
0
SLTI
Input
−
1
×
SLTO
Output
−
0
0
P60
SCL0
I/O
−
0
0
P61
SDA0
I/O
−
0
0
P70
KR0
Input
−
1
×
SO01
Output
−
0
1
INTP4
Input
−
1
×
KR1
Input
−
1
×
SI01
Input
−
1
×
P71
P72
P73
P74
P75
INTP5
Input
−
1
×
KR2
Input
−
1
×
SCK01
Input
−
1
×
Output
−
0
1
INTP6
Input
−
1
×
KR3
Input
−
1
×
SO00
Output
−
0
1
TxD0
Output
−
0
1
KR4
Input
−
1
×
SI00
Input
−
1
×
RxD0
Input
−
1
×
KR5
Input
−
1
×
SCK00
Input
−
1
×
Output
−
0
1
P76
KR6
Input
−
1
×
P77
KR7
Input
−
1
×
CMP0P
Input
PIM80 = 0
1
×
INTP3
Input
PIM80 = 1
1
×
Input
PIM80 = 0
1
×
P80
Note 2
PGAI
Note 2
P81
CMP0M
Input
PIM81 = 0
1
×
P82
CMP1P
Input
PIM82 = 0
1
×
INTP7
Input
PIM82 = 1
1
×
P83
CMP1M
Input
PIM83 = 0
1
×
P120
INTP0
Input
−
1
×
EXLVI
Input
−
1
×
P140
PCLBUZ0
Output
−
0
0
Output
−
0
0
Input
−
1
×
P141
PCLBUZ1
Note 2
P150 to P153
Remark
ANI8 to ANI11
×:
Note 2
don’t care
PM××: Port mode register
P××:
Port output latch
(Note is listed on the next page.)
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Notes 1. The ports with which the TI06/TO06 and TI07/TO07 pins are shared differ depending on the product.
78K0R/KC3-L, 78K0R/KD3-L: P50/TI06/TO06, P51/TI07/TO07
78K0R/KE3-L:
P14/TI06/TO06, P15/TI07/TO07
2. The function of the ANI0/P20 to ANI7/P27 and ANI8/P150 to ANI11/P153 pins can be selected by using the
A/D port configuration register (ADPC), analog input channel specification register (ADS), and port mode
registers 2, 15 (PM2, PM15).
Table 5-8. Setting Functions of ANI0/P20 to ANI7/P27 and ANI8/P150 to ANI11/P153 Pins
ADPC Register
PM2 and PM15
ADS Register
Registers
Digital I/O selection
Analog input selection
ANI0/P20 to ANI7/P27 and
ANI8/P150 to ANI11/P153 Pins
Input mode
−
Digital input
Output mode
−
Digital output
Input mode
Selects ANI.
Analog input (to be converted)
Does not select ANI.
Analog input (not to be converted)
Output mode
Selects ANI.
Setting prohibited
Does not select ANI.
Remark P20/ANI0 to P27/ANI7, P150/ANI8, and P151/ANI9: 78K0R/KC3-L (40pin, 44-pin)
P20/ANI0 to P27/ANI7, P150/ANI8 to P152/ANI10: 78K0R/KC3-L (48-pin), 78K0R/KD3-L
P20/ANI0 to P27/ANI7, P150/ANI8 to P153/ANI11: 78K0R/KE3-L
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5.6 Cautions on 1-bit Manipulation Instruction for Port Register n (Pn)
When a 1-bit manipulation instruction is executed on a port that provides both input and output functions, the output
latch value of an input port that is not subject to manipulation may be written in addition to the targeted bit.
Therefore, it is recommended to rewrite the output latch when switching a port from input mode to output mode.
<Example>
When P10 is an output port, P11 to P17 are input ports (all pin statuses are high level), and the port
latch value of port 1 is 00H, if the output of output port P10 is changed from low level to high level via a
1-bit manipulation instruction, the output latch value of port 1 is FFH.
Explanation:
The targets of writing to and reading from the Pn register of a port whose PMnm bit is 1 are the output
latch and pin status, respectively.
A 1-bit manipulation instruction is executed in the following order in the 78K0R/KC3-L, 78K0R/KD3-L,
78K0R/KE3-L.
<1> The Pn register is read in 8-bit units.
<2> The targeted one bit is manipulated.
<3> The Pn register is written in 8-bit units.
In step <1>, the output latch value (0) of P10, which is an output port, is read, while the pin statuses of
P11 to P17, which are input ports, are read. If the pin statuses of P11 to P17 are high level at this time,
the read value is FEH.
The value is changed to FFH by the manipulation in <2>.
FFH is written to the output latch by the manipulation in <3>.
Figure 5-42. Bit Manipulation Instruction (P10)
1-bit manipulation
instruction
(set1 P1.0)
is executed for P10
bit.
P10
Low-level output
P11 to P17
P10
High-level output
P11 to P17
Pin status: High-level
Port 1 output latch
0
0
0
Pin status: High-level
Port 1 output latch
0
0
0
0
0
1
1
1
1
1
1
1
1
1-bit manipulation instruction for P10 bit
<1> Port register 1 (P1) is read in 8-bit units.
• In the case of P10, an output port, the value of the port output latch (0) is read.
• In the case of P11 to P17, input ports, the pin status (1) is read.
<2> Set the P10 bit to 1.
<3> Write the results of <2> to the output latch of port register 1 (P1)
in 8-bit units.
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CHAPTER 6 PORT FUNCTIONS (78K0R/KF3-L, 78K0R/KG3-L)
Caution For the functions of the port in the 78K0R/KC3-L, 78K0R/KD3-L, 78K0R/KE3-L, see CHAPTER 5 PORT
FUNCTIONS (78K0R/KC3-L, 78K0R/KD3-L, 78K0R/KE3-L).
6.1 Port Functions
Pin I/O buffer power supplies depend on the product. The relationship between these power supplies and the pins is
shown below.
Table 6-1. Pin I/O Buffer Power Supplies (AVREF, EVDD0, VDD)
• 78K0R/KF3-L: 80-pin plastic LQFP (14x14)
80-pin plastic LQFP (fine pitch) (12x12)
Power Supply
Corresponding Pins
AVREF
P20 to P27, P150 to P153
EVDD0
• Port pins other than P20 to P27, P121 to P124, and P150 to P153
• RESET and FLMD0 pins
• P121 to P124
VDD
• Pins other than port pins (excluding RESET and FLMD0 pins)
Table 6-2. Pin I/O Buffer Power Supplies (AVREF, EVDD0, EVDD1, VDD)
• 78K0R/KG3-L: 100-pin plastic LQFP (14x20)
100-pin plastic LQFP (fine pitch) (14x14)
100-pin plastic FBGA (6x6) Note
Power Supply
Corresponding Pins
AVREF
P20 to P27, P150 to P157
EVDD0, EVDD1
• Port pins other than P20 to P27, P121 to P124, and P150 to P157
• RESET and FLMD0 pins
VDD
• P121 to P124
• Pins other than port pins (excluding RESET and FLMD0 pins)
The 78K0R/KF3-L, 78K0R/KG3-L microcontrollers are provided with digital I/O ports, which enable variety of control
operations. The functions of each port are shown in Table 6-3.
In addition to the function as digital I/O ports, these ports have several alternate functions. For details of the alternate
functions, see CHAPTER 3 PIN FUNCTIONS (78K0R/KF3-L, 78K0R/KG3-L).
Note μPD78F1013 and μPD78F1014 only
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Table 6-3. Port Functions (1/4)
KF3-L
KG3-L
Function Name
−
√
P00
−
√
P01
√
√
P02
√
√
P03
Output of P02 to P04 can be set to N-ch open-
SI10/RxD1/SDA10
√
√
P04
drain output (VDD tolerance).
SCK10/SCL10
Input/output can be specified in 1-bit units.
[KF3-L]
√
√
I/O
I/O
Function
Port 0.
After Reset
Input port
I/O port.
TI00
TO00
Input of P03 and P04 can be set to TTL input
SO10/TxD1
buffer.
P05
Alternate Function
Use of an on-chip pull-up resistor can be specified
TI05/TO05
by a software setting.
[KG3-L]
−
√
√
[KF3-L]
P06
TI06/TO06
[KG3-L]
−
Port 1.
I/O port.
√
√
P10
√
√
P11
√
√
P12
√
√
P13
√
√
P14
√
√
P15
√
√
P16
TI01/TO01/INTP5
√
√
P17
TI02/TO02
√
√
P20 to P27
I/O
Input port
SI00/RxD0
Input of P10 and P11 can be set to TTL input
buffer.
Output of P10 and P12 can be set to N-ch opendrain output (VDD tolerance).
Input/output can be specified in 1-bit units.
Use of an on-chip pull-up resistor can be specified
by a software setting.
I/O
SCK00
SO00/TxD0
TxD3
RxD3
RTCDIV/RTCCL
Port 2.
I/O port.
Input/output can be specified in 1-bit units.
Digital input
Port 3.
I/O port.
Input/output can be specified in 1-bit units.
Use of an on-chip pull-up resistor can be specified
by a software setting.
Input port
Port 4.
I/O port.
Input/output can be specified in 1-bit units.
Use of an on-chip pull-up resistor can be specified
by a software setting.
Input port
ANI0 to ANI7
port
√
√
P30
√
√
P31
√
√
P40
√
√
P41
√
√
P42
√
√
P43
SCK01
√
√
P44
SI01
√
√
P45
SO01
√
√
P46
[KF3-L]
I/O
Note
I/O
RTC1HZ/INTP3
TI03/TO03/INTP4
TOOL0
TOOL1
TI04/TO04
−
[KG3-L]
INTP1/TI05/TO05
√
√
P47
[KF3-L]
−
[KG3-L]
INTP2
Note
If on-chip debugging is enabled by using an option byte, be sure to pull up the P40/TOOL0 pin externally (see
Caution in 3.2.5 P40 to P47 (port 4)).
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Table 6-3. Port Functions (2/4)
KF3-L
KG3-L
Function Name
√
√
P50
I/O
I/O
Function
Port 5.
After Reset
Input port
Alternate Function
[KF3-L (μ PD78F1010,
I/O port.
78F1011, 78F1012)]
Input/output can be specified in 1-bit units.
INTP1
Use of an on-chip pull-up resistor can be specified
[KG3-L (μ PD78F1013,
by a software setting.
78F1014)]
−
[KF3-L(μ PD78F1027,
78F1028)]
INTP1/SCK40
[KG3-L(μ PD78F1029,
78F1030)]
SCK40
√
√
P51
[KF3-L (μ PD78F1010,
78F1011, 78F1012)]
INTP2
[KG3-L (μ PD78F1013,
78F1014)]
−
[KF3-L(μ PD78F1027,
78F1028)]
INTP2/SI40/RxD4
[KG3-L(μ PD78F1029,
78F1030)]
SI40/RxD4
√
√
P52
[KF3-L (μ PD78F1010,
78F1011, 78F1012)]
TO00
[KG3-L (μ PD78F1013,
78F1014)]
−
[KF3-L(μ PD78F1027,
78F1028)]
TO00/SO40/TxD4
[KG3-L(μ PD78F1029,
78F1030)]
SO40/TxD4
√
√
P53
[KF3-L (μ PD78F1010,
78F1011, 78F1012)]
TI00
[KG3-L (μ PD78F1013,
78F1014)]
−
[KF3-L (μ PD78F1027,
78F1028)]
TI00/SCK41
[KG3-L(μ PD78F1029,
78F1030)]
SCK41
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Table 6-3. Port Functions (3/4)
KF3-L
KG3-L
Function Name
√
√
P54
I/O
I/O
Function
Port 5.
After Reset
Input port
Alternate Function
[KF3-L (μ PD78F1010,
I/O port.
78F1011, 78F1012)]
Input/output can be specified in 1-bit units.
TI07/TO07
Use of an on-chip pull-up resistor can be specified
[KG3-L (μ PD78F1013,
by a software setting.
78F1014)]
−
[KF3-L(μ PD78F1027,
78F1028)]
TI00/TO07/SI41
[KG3-L(μ PD78F1029,
78F1030)]
SI41
√
√
KF3-L (μ PD78F1010,
P55
78F1011, 78F1012)]
PCLBUZ1/INTP7
[KG3-L (μ PD78F1013,
78F1014)]
−
[KF3-L (μ PD78F1027,
78F1028)]
PCLBUZ1/INTP7/SO41
[KG3-L(μ PD78F1029,
78F1030)]
SO41
−
√
P56
−
−
√
P57
−
√
√
P60
√
√
P61
√
√
P62, P63
√
√
P64 to P67
I/O
Port 6.
Input port
I/O port.
SCL0
SDA0
Output of P60 to P63 is N-ch open-drain output (6
−
V tolerance).
Input/output can be specified in 1-bit units.
TI10/TO10 to
For only P64 to P67, use of an on-chip pull-up
TI13/TO13
resistor can be specified by a software setting.
√
√
√
√
P70 to P73
I/O
Port 7.
Input port
I/O port.
P74 to P77
KR0 to KR3
KR4/INTP8 to
Input/output can be specified in 1-bit units.
KR7/INTP11
Use of an on-chip pull-up resistor can be specified
by a software setting.
−
√
P80 to P87
I/O
Port 8.
Input port
−
I/O port.
Input/output can be specified in 1-bit units.
Use of an on-chip pull-up resistor can be specified
by a software setting.
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Table 6-3. Port Functions (4/4)
KF3-L
KG3-L
Function Name
√
−
P90
√
√
I/O
I/O
Function
Port 9.
After Reset
Alternate Function
Input port
−
Input port
−
I/O port.
P91
Use of an on-chip pull-up resistor can be specified
by a software setting.
√
√
P110, P111
I/O
Port 11.
I/O port.
Input/output can be specified in 1-bit units.
Use of an on-chip pull-up resistor can be specified
by a software setting.
√
√
P120
√
√
P121
√
√
P122
√
√
P123
√
√
P124
√
√
P130
−
√
P131
I/O
Port 12.
Input
1-bit I/O port and 4-bit input port.
Input port
INTP0/EXLVI
X1
For only P120, use of an on-chip pull-up resistor
X2/EXCLK
can be specified by a software setting.
XT1
XT2
−
Output
Port 13.
Output port
I/O
1-bit output port and 1-bit I/O port.
Input port
TI06/TO06
Input port
PCLBUZ0/INTP6
For only P131, use of an on-chip pull-up resistor
can be specified by a software setting.
√
√
P140
I/O
Port 14.
I/O port.
−
√
P141
√
√
P142
√
√
P143
Output of P142 to P144 can be set to the N-ch
SI20/RxD2/SDA20
P144
open-drain output (VDD tolerance).
SO20/TxD2
√
−
√
√
PCLBUZ1/INTP7
Input of P142 and P143 can be set to TTL input
SCK20/SCL20
buffer.
Input/output can be specified in 1-bit units.
P145
TI07/TO07
Use of an on-chip pull-up resistor can be specified
by a software setting.
√
√
P150
I/O
Port 15.
Digital input
ANI8
I/O port.
port
ANI9
√
√
P151
√
√
P152
√
√
P153
ANI11
−
√
P154
ANI12
−
√
P155
ANI13
−
√
P156
ANI14
−
√
P157
ANI15
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ANI10
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CHAPTER 6 PORT FUNCTIONS (78K0R/KF3-L, 78K0R/KG3-L)
6.2 Port Configuration
Ports include the following hardware.
Table 6-4. Port Configuration
Item
Control registers
Configuration
• 78K0R/KF3-L
Port mode registers (PM0 to PM7, PM9, PM11, PM12, PM14, PM15)
Port registers (P0 to P7, P9, P11 to P15)
Pull-up resistor option registers (PU0, PU1, PU3 to PU7, PU9, PU11, PU12, PU14)
Port input mode registers (PIM0, PIM1, PIM14)
Port output mode registers (POM0, POM1, POM14)
A/D port configuration register (ADPC)
• 78K0R/KG3-L
Port mode registers (PM0 to PM9, PM11 to PM15)
Port registers (P0 to P9, P11 to P15)
Pull-up resistor option registers (PU0, PU1, PU3 to PU9, PU11 to PU14)
Port input mode registers (PIM0, PIM1, PIM14)
Port output mode registers (POM0, POM1, POM14)
A/D port configuration register (ADPC)
Port
• 78K0R/KF3-L
Total: 71 (CMOS I/O: 62, CMOS input: 4, CMOS output: 1, N-ch open drain I/O: 4)
• 78K0R/KG3-L
Total: 89 (CMOS I/O: 80, CMOS input: 4, CMOS output: 1, N-ch open drain I/O: 4)
Pull-up resistor
• 78K0R/KF3-L
Total: 50
• 78K0R/KG3-L
Total: 64
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6.2.1 Port 0
78K0R/KF3-L
78K0R/KG3-L
(μ PD78F10xx: xx = 10, 11, 12,
(μ PD78F10xx: xx = 13, 14,
27, 28)
29, 30)
P00/TI00
−
Note 1
P01/TO00
−
Note 1
√
P02/SO10/TxD1
√
√
P03/SI10/RxD1/SDA10
√
√
P04/SCK10/SCL10
√
√
P05/TI05/TO05
√
P05
Note 2
P06/TI06/TO06
√
P06
Note 2
√
Notes 1. TI00 and TO00 are shared with P53 and P52, respectively, in the 78K0R/KF3-L.
2. TI05/TO05 and TI06/TO06 are shared with P46 and P131, respectively, in the 78K0R/KG3-L.
Port 0 is an I/O port with an output latch. Port 0 can be set to the input mode or output mode in 1-bit units using port
mode register 0 (PM0). When the P00 to P06 pins are used as an input port, use of an on-chip pull-up resistor can be
specified in 1-bit units by pull-up resistor option register 0 (PU0).
Input to the P03 and P04 pins can be specified through a normal input buffer or a TTL input buffer in 1-bit units using
port input mode register 0 (PIM0).
Output from the P02 to P04 pins can be specified as N-ch open-drain output (VDD tolerance) in 1-bit units using port
output mode register 0 (POM0).
This port can also be used for timer I/O, serial interface data I/O, and clock I/O.
Reset signal generation sets port 0 to input mode.
Figures 6-1 to 6-5 show block diagrams of port 0.
Cautions 1. To use P01/TO00 as a general-purpose port, set bit 0 (TO00) of timer output register 0 (TO0) and
bit 0 (TOE00) of timer output enable register 0 (TOE0) to “0”, which is the same as their default
status setting.
2. To use P02/SO10/TxD1, P03/SI10/RxD1/SDA10, or P04/SCK10/SCL10 as a general-purpose port,
note the serial array unit 0 setting. For details, refer to the following tables.
• Table 14-11 Relationship Between Register Settings and Pins (Channel 2 of Unit 0: CSI10,
UART1 Transmission, IIC10)
• Table 14-12 Relationship Between Register Settings and Pins (Channel 3 of Unit 0: UART1
Reception)
3. To use P05/TI05/TO05 or P06/TI06/TO06 as a general-purpose port, set bits 5 and 6 (TO05, TO06)
of timer output register 0 (TO0) and bits 5 and 6 (TOE05, TOE06) of timer output enable register 0
(TOE0) to “0”, which is the same as their default status setting.
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Figure 6-1. Block Diagram of P00
EVDD0, EVDD1
WRPU
PU0
PU00
P-ch
Alternate
function
Selector
Internal bus
RD
WRPORT
P0
Output latch
(P00)
P00/TI00
WRPM
PM0
PM00
P0:
Port register 0
PU0:
Pull-up resistor option register 0
PM0:
Port mode register 0
RD:
Read signal
WR××: Write signal
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Figure 6-2. Block Diagram of P01
EVDD0, EVDD1
WRPU
PU0
PU01
P-ch
Selector
Internal bus
RD
WRPORT
P0
Output latch
(P01)
P01/TO00
WRPM
PM0
PM01
Alternate
function
P0:
Port register 0
PU0:
Pull-up resistor option register 0
PM0:
Port mode register 0
RD:
Read signal
WR××: Write signal
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Figure 6-3. Block Diagram of P02
EVDD0, EVDD1
WRPU
PU0
PU02
P-ch
Selector
Internal bus
RD
WRPORT
P0
Output latch
(P02)
P02/SO10/TxD1
WRPOM
POM0
POM02
WRPM
PM0
PM02
Alternate
function
P0:
Port register 0
PU0:
Pull-up resistor option register 0
PM0:
Port mode register 0
POM0: Port output mode register 0
RD:
Read signal
WR××: Write signal
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Figure 6-4. Block Diagram of P03 and P04
WRPIM
PIM0
EVDD0, EVDD1
PIM03, PIM04
WRPU
PU0
PU03, PU04
P-ch
Alternate
function
CMOS
Selector
Internal bus
RD
TTL
WRPORT
P0
Output latch
(P03, P04)
P03/SI10/RxD1/SDA10,
P04/SCK10/SCL10
WRPOM
POM0
POM03, POM04
WRPM
PM0
PM03, PM04
Alternate
function
P0:
Port register 0
PU0:
Pull-up resistor option register 0
PM0:
Port mode register 0
PIM0:
Port input mode register 0
POM0: Port output mode register 0
RD:
Read signal
WR××: Write signal
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Figure 6-5. Block Diagram of P05 and P06
[78K0R/KF3-L]
EVDD0
WRPU
PU0
PU05, PU06
P-ch
Alternate
function
Selector
Internal bus
RD
WRPORT
P0
Output latch
(P05, P06)
P05/TI05/TO05,
P06/TI06/TO06
WRPM
PM0
PM05, PM06
Alternate
function
[78K0R/KG3-L]
EVDD0, EVDD1
WRPU
PU0
P-ch
RD
Selector
Internal bus
PU05, PU06
WRPORT
P0
Output latch
(P05, P06)
P05, P06
WRPM
PM0
PM05, PM06
P0:
Port register 0
PU0:
Pull-up resistor option register 0
PM0:
Port mode register 0
RD:
Read signal
WR××: Write signal
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6.2.2 Port 1
78K0R/KF3-L
78K0R/KG3-L
(μ PD78F10xx: xx = 10, 11, 12,
(μ PD78F10xx: xx = 13, 14,
27, 28)
29, 30)
P10/SCK00
√
√
P11/SI00/RxD0
√
√
P12/SO00/TxD0
√
√
P13/TxD3
√
√
P14/RxD3
√
√
P15/RTCDIV/RTCCL
√
√
P16/TI01/TO01/INTP5
√
√
P17/TI02/TO02
√
√
Port 1 is an I/O port with an output latch. Port 1 can be set to the input mode or output mode in 1-bit units using port
mode register 1 (PM1). When the P10 to P17 pins are used as an input port, use of an on-chip pull-up resistor can be
specified in 1-bit units by pull-up resistor option register 1 (PU1).
Input to the P10 and P11 pins can be specified through a normal input buffer or a TTL input buffer in 1-bit units using
port input mode register 1 (PIM1).
Output from the P10 and P12 pins can be specified as N-ch open-drain output (VDD tolerance) in 1-bit units using port
output mode register 1 (POM1).
This port can also be used for external interrupt request input, serial interface data I/O, clock I/O, timer I/O, and realtime counter clock output.
Reset signal generation sets port 1 to input mode.
Figures 6-6 to 6-12 show block diagrams of port 1.
Cautions 1. To use P10/SCK00, P11/SI00/RxD0, or P12/SO00/TxD0, P13/TxD3, P14/RxD3 as a general-purpose
port, note the serial array unit setting. For details, refer to the following tables.
• Table 14-9 Relationship Between Register Settings and Pins (Channel 0 of Unit 0: CSI00,
UART0 Transmission)
• Table 14-10 Relationship Between Register Settings and Pins (Channel 1 of Unit 0: CSI01,
UART0 Reception)
• Table 14-15 Relationship Between Register Settings and Pins (Channel 2 of Unit 1: UART3
Transmission)
• Table 14-16 Relationship Between Register Settings and Pins (Channel 3 of Unit 1: UART3
Reception)
2. To use P16/TI01/TO01/INTP5 or P17/TI02/TO02 as a general-purpose port, set bits 1 and 2 (TO01,
TO02) of timer output register 0 (TO0) and bits 1 and 2 (TOE01, TOE02) of timer output enable
register 0 (TOE0) to “0”, which is the same as their default status setting.
3. To use P15/RTCDIV/RTCCL as a general-purpose port, set bit 4 (RCLOE0) of real-time counter
control register 0 (RTCC0) and bit 6 (RCLOE2) of real-time counter control register 2 (RTCC2) to
“0”, which is the same as their default status settings.
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Figure 6-6. Block Diagram of P10
WRPIM
PIM1
PIM10
EVDD0, EVDD1
WRPU
PU1
PU10
P-ch
Alternate
function
CMOS
Selector
Internal bus
RD
TTL
WRPORT
P1
Output latch
(P10)
P10/SCK00
WRPOM
POM1
POM10
WRPM
PM1
PM10
Alternate
function
P1:
Port register 1
PU1:
Pull-up resistor option register 1
PM1:
Port mode register 1
PIM1:
Port input mode register 1
POM1: Port output mode register 1
RD:
Read signal
WR××: Write signal
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Figure 6-7. Block Diagram of P11
WRPIM
PIM1
PIM11
EVDD0, EVDD1
WRPU
PU1
PU11
P-ch
Internal bus
Alternate
function
CMOS
Selector
RD
TTL
WRPORT
P1
Output latch
(P11)
P11/SI00/RxD0
WRPM
PM1
PM11
P1:
Port register 1
PU1:
Pull-up resistor option register 1
PM1:
Port mode register 1
PIM1:
Port input mode register 1
RD:
Read signal
WR××: Write signal
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Figure 6-8. Block Diagram of P12
EVDD0, EVDD1
WRPU
PU1
PU12
P-ch
Selector
Internal bus
RD
WRPORT
P1
Output latch
(P12)
P12/SO00/TxD0
WRPOM
POM1
POM12
WRPM
PM1
PM12
Alternate
function
P1:
Port register 1
PU1:
Pull-up resistor option register 1
PM1:
Port mode register 1
POM1: Port output mode register 1
RD:
Read signal
WR××: Write signal
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Figure 6-9. Block Diagram of P13
EVDD0, EVDD1
WRPU
PU1
PU13
P-ch
Selector
Internal bus
RD
WRPORT
P1
Output latch
(P13)
P13/TxD3
WRPM
PM1
PM13
Alternate
function
P1:
Port register 1
PU1:
Pull-up resistor option register 1
PM1:
Port mode register 1
RD:
Read signal
WR××: Write signal
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Figure 6-10. Block Diagram of P14
EVDD0, EVDD1
WRPU
PU1
PU14
P-ch
Alternate
function
Selector
Internal bus
RD
WRPORT
P1
Output latch
(P14)
P14/RxD3
WRPM
PM1
PM14
P1:
Port register 1
PU1:
Pull-up resistor option register 1
PM1:
Port mode register 1
RD:
Read signal
WR××: Write signal
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Figure 6-11. Block Diagram of P15
EVDD0, EVDD1
WRPU
PU1
PU15
P-ch
Selector
Internal bus
RD
WRPORT
P1
Output latch
(P15)
P15/RTCDIV/RTCCL
WRPM
PM1
PM15
Alternate
function
P1:
Port register 1
PU1:
Pull-up resistor option register 1
PM1:
Port mode register 1
RD:
Read signal
WR××: Write signal
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Figure 6-12. Block Diagram of P16 and P17
EVDD0, EVDD1
WRPU
PU1
PU16, PU17
P-ch
Alternate
function
Selector
Internal bus
RD
WRPORT
P1
Output latch
(P16, P17)
P16/TI01/TO01/INTP5,
P17/TI02/TO02
WRPM
PM1
PM16, PM17
Alternate
function
P1:
Port register 1
PU1:
Pull-up resistor option register 1
PM1:
Port mode register 1
RD:
Read signal
WR××: Write signal
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6.2.3 Port 2
78K0R/KF3-L
78K0R/KG3-L
(μ PD78F10xx: xx = 10, 11, 12,
(μ PD78F10xx: xx = 13, 14,
27, 28)
29, 30)
P20/ANI0
√
√
P21/ANI1
√
√
P22/ANI2
√
√
P23/ANI3
√
√
P24/ANI4
√
√
P25/ANI5
√
√
P26/ANI6
√
√
P27/ANI7
√
√
Port 2 is an I/O port with an output latch. Port 2 can be set to the input mode or output mode in 1-bit units using port
mode register 2 (PM2).
This port can also be used for A/D converter analog input.
To use P20/ANI0 to P27/ANI7 as digital input pins, set them in the digital I/O mode by using the A/D port configuration
register (ADPC) and in the input mode by using the PM2 register. Use these pins starting from the lower bit.
To use P20/ANI0 to P27/ANI7 as digital output pins, set them in the digital I/O mode by using the ADPC register and in
the output mode by using the PM2 register.
To use P20/ANI0 to P27/ANI7 as analog input pins, set them in the analog input mode by using the A/D port
configuration register (ADPC) and in the input mode by using the PM2 register. Use these pins starting from the upper bit.
Table 6-5. Setting Functions of P20/ANI0 to P27/ANI7 Pins
ADPC Register
Digital I/O selection
Analog input selection
PM2 Register
ADS Register
P20/ANI0 to P27/ANI7 Pins
Input mode
−
Digital input
Output mode
−
Digital output
Input mode
Output mode
Selects ANI.
Analog input (to be converted)
Does not select ANI.
Analog input (not to be converted)
Selects ANI.
Setting prohibited
Does not select ANI.
All P20/ANI0 to P27/ANI7 are set in the digital input mode when the reset signal is generated.
Figure 6-13 shows a block diagram of port 2.
Caution See 3.2.16 AVREF, AVSS, VDD, EVDD0, EVDD1, VSS, EVSS0, EVSS1 for the voltage to be applied to the AVREF
pin when using port 2 as a digital I/O.
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Figure 6-13. Block Diagram of P20 to P27
Selector
Internal bus
RD
WRPORT
P2
Output latch
(P20 to P27)
P20/ANI0 to
P27/ANI7
WRPM
PM2
PM20 to PM27
A/D converter
P2:
Port register 2
PM2:
Port mode register 2
RD:
Read signal
WR××: Write signal
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6.2.4 Port 3
78K0R/KF3-L
78K0R/KG3-L
(μ PD78F10xx: xx = 10, 11, 12,
(μ PD78F10xx: xx = 13, 14,
27, 28)
29, 30)
P30/RTC1HZ/INTP3
√
√
P31/TI03/TO03/INTP4
√
√
Port 3 is an I/O port with an output latch. Port 3 can be set to the input mode or output mode in 1-bit units using port
mode register 3 (PM3). When the P30 and P31 pins are used as an input port, use of an on-chip pull-up resistor can be
specified in 1-bit units by pull-up resistor option register 3 (PU3).
This port can also be used for external interrupt request input, timer I/O, and real-time counter correction clock output.
Reset signal generation sets port 3 to input mode.
Figure 6-14 shows block a diagram of port 3.
Cautions 1. To use P31/TI03/TO03/INTP4 as a general-purpose port, set bit 3 (TO03) of timer output register 0
(TO0) and bit 3 (TOE03) of timer output enable register 0 (TOE0) to “0”, which is the same as their
default status setting.
2. To use P30/RTC1HZ/INTP3 as a general-purpose port, set bit 5 (RCLOE1) of real-time counter
control register 0 (RTCC0) to “0”, which is the same as its default status setting.
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Figure 6-14. Block Diagram of P30 and P31
EVDD0, EVDD1
WRPU
PU3
PU30, PU31
P-ch
Alternate
function
Selector
Internal bus
RD
WRPORT
P3
Output latch
(P30, P31)
P30/RTC1HZ/INTP3,
P31/TI03/TO03/INTP4
WRPM
PM3
PM30, PM31
Alternate
function
P3:
Port register 3
PU3:
Pull-up resistor option register 3
PM3:
Port mode register 3
RD:
Read signal
WR××: Write signal
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6.2.5 Port 4
78K0R/KF3-L
78K0R/KG3-L
(μ PD78F10xx: xx = 10, 11, 12,
(μ PD78F10xx: xx = 13, 14,
27, 28)
29, 30)
P40/TOOL0
√
√
P41/TOOL1
√
√
P42/TI04/TO04
√
√
P43/SCK01
√
√
P44/SI01
√
√
P45/SO01
√
√
P46/INTP1/TI05/TO05
P47/INTP2
P46
Note 1
√
P47
Note 2
√
Notes 1. INTP1 and TI05/TO05 are shared with P50 and P05, respectively, in the 78K0R/KF3-L.
2. INTP2 is shared with P51, in the 78K0R/KF3-L.
Port 4 is an I/O port with an output latch. Port 4 can be set to the input mode or output mode in 1-bit units using port
mode register 4 (PM4). When the P40 to P47 pins are used as an input port, use of an on-chip pull-up resistor can be
specified in 1-bit units by pull-up resistor option register 4 (PU4)Note.
This port can also be used for external interrupt request input, serial interface data I/O, clock I/O, flash memory
programmer/debugger data I/O, clock output, and timer I/O.
Reset signal generation sets port 4 to input mode.
Figures 6-15 to 6-22 show block diagrams of port 4.
Note When a tool is connected, the P40 and P41 pins cannot be connected to a pull-up resistor.
Cautions 1. When a tool is connected, the P40 pin cannot be used as a port pin.
When the on-chip debug function is used, the P41 pin can be used as follows by the mode setting
on the debugger.
1-line mode: can be used as a port (P41).
2-line mode: used as a TOOL1 pin and cannot be used as a port (P41).
2. To use P43/SCK01, P44/SI01, or P45/SO01 as a general-purpose port, note the serial array unit 0
setting.
For details, refer to Table 14-10 Relationship Between Register Settings and Pins
(Channel 1 of Unit 0: CSI01, UART0 reception).
3. To use P42/TI04/TO04 or P46/INTP1/TI05/TO05 as a general-purpose port, set bits 4 and 5 (TO04,
TO05) of timer output register 0 (TO0) and bits 4 and 5 (TOE04, TOE05) of timer output enable
register 0 (TOE0) to “0”, which is the same as their default status setting.
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Figure 6-15. Block Diagram of P40
EVDD0, EVDD1
WRPU
PU4
PU40
P-ch
Alternate
function
Selector
WRPORT
P4
Output latch
(P40)
WRPM
Selector
Internal bus
RD
P40/TOOL0
PM4
PM40
Alternate
function
P4:
Port register 4
PU4:
Pull-up resistor option register 4
PM4:
Port mode register 4
RD:
Read signal
WR××: Write signal
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Figure 6-16. Block Diagram of P41
EVDD0, EVDD1
WRPU
PU4
PU41
P-ch
Internal bus
Selector
RD
WRPORT
Output latch
(P41)
WRPM
PM4
Selector
P4
P41/TOOL1
PM41
Alternate
function
P4:
Port register 4
PU4:
Pull-up resistor option register 4
PM4:
Port mode register 4
RD:
Read signal
WR××: Write signal
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Figure 6-17. Block Diagram of P42
EVDD0, EVDD1
WRPU
PU4
PU42
P-ch
Alternate
function
Selector
Internal bus
RD
WRPORT
P4
Output latch
(P42)
P42/TI04/TO04
WRPM
PM4
PM42
Alternate
function
P4:
Port register 4
PU4:
Pull-up resistor option register 4
PM4:
Port mode register 4
RD:
Read signal
WR××: Write signal
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Figure 6-18. Block Diagram of P43
EVDD0, EVDD1
WRPU
PU4
PU43
P-ch
Alternate
function
Internal bus
Selector
RD
WRPORT
P4
Output latch
(P43)
P43/SCK01
WRPM
PM4
PM43
Alternate
function
P4:
Port register 4
PU4:
Pull-up resistor option register 4
PM4:
Port mode register 4
RD:
Read signal
WR××: Write signal
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Figure 6-19. Block Diagram of P44
EVDD0, EVDD1
WRPU
PU4
PU44
P-ch
Alternate
function
Selector
Internal bus
RD
WRPORT
P4
Output latch
(P44)
P44/SI01
WRPM
PM4
PM44
P4:
Port register 4
PU4:
Pull-up resistor option register 4
PM4:
Port mode register 4
RD:
Read signal
WR××: Write signal
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Figure 6-20. Block Diagram of P45
EVDD0, EVDD1
WRPU
PU4
PU45
P-ch
Selector
Internal bus
RD
WRPORT
P4
Output latch
(P45)
P45/SO01
WRPM
PM4
PM45
Alternate
function
P4:
Port register 4
PU4:
Pull-up resistor option register 4
PM4:
Port mode register 4
RD:
Read signal
WR××: Write signal
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Figure 6-21. Block Diagram of P46
[78K0R/KF3-L]
EVDD0
WRPU
PU4
PU46
P-ch
Selector
Internal bus
RD
WRPORT
P4
Output latch
P46
(P46)
WRPM
PM4
PM46
[78K0R/KG3-L]
EVDD0, EVDD1
WRPU
PU4
PU46
P-ch
Alternate
function
Selector
Internal bus
RD
WRPORT
P4
Output latch
(P46)
P46/TI05/TO05/INTP1
WRPM
PM4
PM46
Alternate
function
P4:
Port register 4
PU4:
Pull-up resistor option register 4
PM4:
Port mode register 4
RD:
Read signal
WR××: Write signal
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Figure 6-22. Block Diagram of P47
[78K0R/KF3-L]
EVDD0
WRPU
PU4
PU47
P-ch
Selector
Internal bus
RD
WRPORT
P4
Output latch
P47
(P47)
WRPM
PM4
PM47
[78K0R/KG3-L]
EVDD0, EVDD1
WRPU
PU4
PU47
P-ch
Alternate
function
Selector
Internal bus
RD
WRPORT
P4
Output latch
(P47)
P47/INTP2
WRPM
PM4
PM47
P4:
Port register 4
PU4:
Pull-up resistor option register 4
PM4:
Port mode register 4
RD:
Read signal
WR××: Write signal
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6.2.6 Port 5 (μ PD78F1010, 78F1011, 78F1012, 78F1013, 78F1014)
78K0R/KF3-L
78K0R/KG3-L
(μPD78F101y: y = 0 to 2)
(μPD78F101y: y = 3, 4)
P50/INTP1
√
P50
Note
P51/INTP2
√
P51
Note
P52/TO00
√
P52
Note
P53/TI00
√
P53
Note
P54/TI07/TO07
√
P54
Note
P55/PCLBUZ1/INTP7
√
P55
Note
P56
−
√
P57
−
√
Note
The following pins are shared in the 78K0R/KG3-L.
• P46/INTP1
• P47/INTP2
• P01/TO00
• P00/TI00
• P145/TI07/TO07
• P141/PCLBUZ1/INTP7
Port 5 is an I/O port with an output latch. Port 5 can be set to the input mode or output mode in 1-bit units using port
mode register 5 (PM5). When the P50 to P57 pins are used as an input port, use of an on-chip pull-up resistor can be
specified in 1-bit units by pull-up resistor option register 5 (PU5).
This port can also be used for external interrupt request input, timer I/O, and clock/buzzer output.
Reset signal generation sets port 5 to input mode.
Figures 6-23 to 6-26 show block diagrams of port 5.
Cautions 1. To use P52/TO00 or P54/TI07/TO07 as a general-purpose port, set bits 0 and 7 (TO00, TO07) of
timer output register 0 (TO0) and bits 0 and 7 (TOE00, TOE07) of timer output enable register 0
(TOE0) to “0”, which is the same as their default status setting.
2. To use P55/PCLBUZ1/INTP7 as a general-purpose port, set bit 7 of clock output select register 1
(CKS1) to “0”, which is the same as their default status settings.
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Figure 6-23. Block Diagram of P50, P51, and P53
[78K0R/KF3-L (μ PD78F1010, 78F1011, 78F1012)]
EVDD0
WRPU
PU5
PU50, PU51, PU53
P-ch
Alternate
function
Selector
Internal bus
RD
WRPORT
P5
P50/INTP1,
P51/INTP2,
P53/TI00
Output latch
(P50, P51, P53)
WRPM
PM5
PM50, PM51, PM53
[78K0R/KG3-L (μ PD78F1013, 78F1014)]
EVDD0, EVDD1
WRPU
PU5
PU50, PU51, PU53
P-ch
Selector
Internal bus
RD
WRPORT
P5
Output latch
(P50, P51, P53)
P50, P51, P53
WRPM
PM5
PM50, PM51, PM53
P5:
Port register 5
PU5:
Pull-up resistor option register 5
PM5:
Port mode register 5
RD:
Read signal
WR××: Write signal
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Figure 6-24. Block Diagram of P52
[78K0R/KF3-L (μ PD78F1010, 78F1011, 78F1012)]
EVDD0
WRPU
PU5
PU52
P-ch
Selector
Internal bus
RD
WRPORT
P5
Output latch
(P52)
P52/TO00
WRPM
PM5
PM52
Alternate
function
[78K0R/KG3-L (μ PD78F1013, 78F1014)]
EVDD0, EVDD1
WRPU
PU5
PU52
P-ch
Selector
Internal bus
RD
WRPORT
P5
Output latch
(P52)
P52
WRPM
PM5
PM52
P5:
Port register 5
PU5:
Pull-up resistor option register 5
PM5:
Port mode register 5
RD:
Read signal
WR××: Write signal
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Figure 6-25. Block Diagram of P54 and P55
[78K0R/KF3-L (μ PD78F1010, 78F1011, 78F1012)]
EVDD0
WRPU
PU5
PU54, PU55
P-ch
Alternate
function
Selector
Internal bus
RD
WRPORT
P5
Output latch
(P54, P55)
P54/TI07/TO07,
P55/PCLBUZ1/INTP7
WRPM
PM5
PM54, PM55
Alternate
function
[78K0R/KG3-L (μ PD78F1013, 78F1014)]
EVDD0, EVDD1
WRPU
PU5
PU54, PU55
P-ch
Selector
Internal bus
RD
WRPORT
P5
Output latch
(P54, P55)
P54, P55
WRPM
PM5
PM54, PM55
P5:
Port register 5
PU5:
Pull-up resistor option register 5
PM5:
Port mode register 5
RD:
Read signal
WR××: Write signal
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Figure 6-26. Block Diagram of P56 and P57
EVDD0, EVDD1
WRPU
PU5
PU56, PU57
P-ch
Selector
Internal bus
RD
WRPORT
P5
Output latch
(P56, P57)
P56, P57
WRPM
PM5
PM56, PM57
P5:
Port register 5
PU5:
Pull-up resistor option register 5
PM5:
Port mode register 5
RD:
Read signal
WR××: Write signal
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6.2.7 Port 5 (μ PD78F1027, 78F1028, 78F1029, 78F1030)
78K0R/KF3-L
78K0R/KG3-L
(μ PD78F10xx: xx = 27, 28)
(μ PD78F10xx: xx = 29, 30)
P50/SCK40/INTP1
√
P50/SCK40
P51/SI40/RxD4/INTP2
√
P51/SI40/RxD4
P52/SO40/TO00/TxD4
√
P52/SO40/TxD4
P53/SCK41/TI00
√
Note
P53/SCK41
P54/SI41/TI07/TO07
√
P54/SI41
P55/PCLBUZ1/SO41/
√
P55/SO41
Note
Note
Note
Note
Note
INTP7
P56
−
√
P57
−
√
Note
The following pins are shared in the 78K0R/KG3-L.
• P46/INTP1
• P47/INTP2
• P01/TO00
• P00/TI00
• P145/TI07/TO07
• P141/PCLBUZ1/INTP7
Port 5 is an I/O port with an output latch. Port 5 can be set to the input mode or output mode in 1-bit units using port
mode register 5 (PM5). When the P50 to P57 pins are used as an input port, use of an on-chip pull-up resistor can be
specified in 1-bit units by pull-up resistor option register 5 (PU5).
This port can also be used for serial interface data I/O, clock I/O, external interrupt request input, timer I/O, and
clock/buzzer output.
Reset signal generation sets port 5 to input mode.
Figures 6-27 to 6-32 show block diagrams of port 5.
Cautions 1. To use P52/SO40/TO00/TxD4(P52/SO40/TO00, in case of KG3-L) or P54/SI41/TI07/TO07(P54/SI41,
in case of KG3-L) as a general-purpose port, set bits 0 and 7 (TO00, TO07) of timer output register
0 (TO0) and bits 0 and 7 (TOE00, TOE07) of timer output enable register 0 (TOE0) to “0”, which is
the same as their default status setting.
2. To use P55/PCLBUZ1/SO41/INTP7(P55/SO41, in case of KG3-L) as a general-purpose port, set bit
7 of clock output select register 1 (CKS1) to “0”, which is the same as their default status settings.
3. To
use
P50/SCK40/INTP1,
P51/SI40/RxD4/INTP2,
P52/SO40/TO00/TxD4,
P53/SCK41/TI00,
P54/SI41/TI07/TO07, and P55/PCLBUZ1/SO41/INTP7 as a general-purpose port, note the serial
array unit setting.
For details, refer to Table 1 Table 14-17.
Relationship between register
settings and pins (Channel 0 of unit 2: CSI40, UART4 transmission) (μPD78F1027, 78F1028,
78F1029, 78F1030 only) and Table 14-18.
Relationship between register settings and pins
(Channel 1 of unit 2: CSI41, UART4 reception) (μPD78F1027, 78F1028, 78F1029, 78F1030 only).
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Figure 6-27. Block Diagram of P50 and P53
EVDD0, EVDD1
WRPU
PU5
PU50, PU53
P-ch
Alternate
function
Selector
Internal bus
RD
WRPORT
P5
[In case of μPD78F1027, 78F1028]
Output latch
(P50, P53)
P50/SCK40/INTP1
P53/SCK41/TI00
[In case of μPD78F1029, 78F1030]
WRPM
PM5
P50/SCK40
P53/SCK41
PM50, PM53
Alternate
function
P5:
Port register 5
PU5:
Pull-up resistor option register 5
PM5:
Port mode register 5
RD:
Read signal
WR××: Write signal
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Figure 6-28. Block Diagram of P51
EVDD0, EVDD1
WRPU
PU5
PU51
P-ch
Alternate
function
Selector
Internal bus
RD
WRPORT
P5
Output latch
(P51)
WRPM
PM5
[In case of μPD78F1027, 78F1028]
P51/SI40/RxD4/INTP2
[In case of μPD78F1029, 78F1030]
P51/SI40/RxD4
PM51
P5:
Port register 5
PU5:
Pull-up resistor option register 5
PM5:
Port mode register 5
RD:
Read signal
WR××: Write signal
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Figure 6-29. Block Diagram of P52
[78K0R/KF3-L (μ PD78F1027, 78F1028)]
EVDD0
WRPU
PU5
PU52
P-ch
Internal bus
Selector
RD
WRPORT
P5
Output latch
(P52)
P52/SO40/TO00/TxD4
WRPM
PM5
PM52
Alternate
function
Alternate
function
[78K0R/KG3-L (μ PD78F1029, 78F1030)]
EVDD0, EVDD1
WRPU
PU5
PU52
P-ch
Selector
Internal bus
RD
WRPORT
P5
Output latch
(P52)
P52/SO40/TxD4
WRPM
PM5
PM52
Alternate
function
P5:
Port register 5
PU5:
Pull-up resistor option register 5
PM5:
Port mode register 5
RD:
Read signal
WR××: Write signal
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Figure 6-30. Block Diagram of P54
[78K0R/KF3-L (μ PD78F1027, 78F1028)]
EVDD0
WRPU
PU5
PU54
P-ch
Alternate
function
Internal bus
Selector
RD
WRPORT
P5
Output latch
(P54)
P54/SI41/TI07/TO07
WRPM
PM5
PM54
Alternate
function
[78K0R/KG3-L (μ PD78F1029, 78F1030)]
EVDD0, EVDD1
WRPU
PU5
PU54
P-ch
Alternate
function
Selector
Internal bus
RD
WRPORT
P5
Output latch
(P54)
P54/SI41
WRPM
PM5
PM54
P5:
Port register 5
PU5:
Pull-up resistor option register 5
PM5:
Port mode register 5
RD:
Read signal
WR××: Write signal
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Figure 6-31. Block Diagram of P55
[78K0R/KF3-L (μ PD78F1027, 78F1028)]
EVDD0
WRPU
PU5
PU55
Alternate
function
Selector
Internal bus
RD
P-ch
WRPORT
P5
Output latch
(P55)
P55/PCLBUZ1/SO41/INTP7
WRPM
PM5
PM55
Alternate
function
Alternate
function
[78K0R/KG3-L (μ PD78F1029, 78F1030)]
EVDD0, EVDD1
WRPU
PU5
PU55
P-ch
Selector
Internal bus
RD
WRPORT
P5
Output latch
(P55)
P55/SO41
WRPM
PM5
PM55
Alternate
function
P5:
PU5:
PM5:
RD:
WR××:
Port register 5
Pull-up resistor option register 5
Port mode register 5
Read signal
Write signal
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Figure 6-32. Block Diagram of P56 and P57
EVDD0, EVDD1
WRPU
PU5
PU56, PU57
P-ch
Selector
Internal bus
RD
WRPORT
P5
Output latch
(P56, P57)
P56, P57
WRPM
PM5
PM56, PM57
P5:
Port register 5
PU5:
Pull-up resistor option register 5
PM5:
Port mode register 5
RD:
Read signal
WR××: Write signal
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6.2.8 Port 6
78K0R/KF3-L
78K0R/KG3-L
(μ PD78F10xx: xx = 10, 11, 12,
(μ PD78F10xx: xx = 13, 14,
27, 28)
29, 30)
P60/SCL0
√
√
P61/SDA0
√
√
P62
√
√
P63
√
√
P64/TI10/TO10
√
√
P65/TI11/TO11
√
√
P66/TI12/TO12
√
√
P67/TI13/TO13
√
√
Port 6 is an I/O port with an output latch. Port 6 can be set to the input mode or output mode in 1-bit units using port
mode register 6 (PM6). When the P64 to P67 pins are used as an input port, use of an on-chip pull-up resistor can be
specified in 1-bit units by pull-up resistor option register 6 (PU6).
The output of the P60 to P63 pins is N-ch open-drain output (6 V tolerance).
This port can also be used for serial interface data I/O, clock I/O, and timer I/O.
Reset signal generation sets port 6 to input mode.
Figures 6-33 to 6-36 show block diagrams of port 6.
Cautions 1. Stop the operation of serial interface IICA when using P60/SCL0 and P61/SDA0 as generalpurpose ports.
2. To use P64/TI10/TO10 to P67/TI13/TO13 as a general-purpose port, set bits 0 to 3 (TO10 to TO13)
of timer output register 1 (TO1) and bits 0 to 3 (TOE10 to TOE13) of timer output enable register 1
(TOE1) to “0”, which is the same as their default status setting.
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Figure 6-33. Block Diagram of P60 and P61
Alternate
function
Selector
RD
Internal bus
WRPORT
P6
Output latch
(P60, P61)
P60/SCL0,
P61/SDA0
WRPM
PM6
PM60, PM61
Alternate
function
P6:
Port register 6
PM6:
Port mode register 6
RD:
Read signal
WR××: Write signal
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Figure 6-34. Block Diagram of P62
Selector
RD
Internal bus
WRPORT
P6
Output latch
(P62)
P62
WRPM
PM6
PM62
P6:
Port register 6
PM6:
Port mode register 6
RD:
Read signal
WR××: Write signal
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Figure 6-35. Block Diagram of P63
Internal bus
Selector
RD
WRPORT
P6
Output latch
(P63)
P63
WRPM
PM6
PM63
P6:
Port register 6
PM6:
Port mode register 6
RD:
Read signal
WR××: Write signal
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Figure 6-36. Block Diagram of P64 to P67
EVDD0, EVDD1
WRPU
PU6
PU64 to PU67
P-ch
Alternate
function
Selector
Internal bus
RD
WRPORT
P6
Output latch
(P64 to P67)
P64/TI10/TO10 to P67/TI13/TO13
WRPM
PM6
PM64 to PM67
Alternate
function
P6:
Port register 6
PU6:
Pull-up resistor option register 6
PM6:
Port mode register 6
RD:
Read signal
WR××: Write signal
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6.2.9 Port 7
78K0R/KF3-L
78K0R/KG3-L
(μPD78F10xx: xx = 10 to 12, 27,28)
(μPD78F10xx: xx = 13, 14, 29, 30)
P70/KR0
√
√
P71/KR1
√
√
P72/KR2
√
√
P73/KR3
√
√
P74/KR4/INTP8
√
√
P75/KR5/INTP9
√
√
P76/KR6/INTP10
√
√
P77/KR7/INTP11
√
√
Port 7 is an I/O port with an output latch. Port 7 can be set to the input mode or output mode in 1-bit units using port
mode register 7 (PM7). When used as an input port, use of an on-chip pull-up resistor can be specified in 1-bit units by
pull-up resistor option register 7 (PU7).
This port can also be used for key return input and interrupt request input.
Reset signal generation sets port 7 to input mode.
Figure 6-37 shows a block diagram of port 7.
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Figure 6-37. Block Diagram of P70 to P77
EVDD0, EVDD1
WRPU
PU7
PU70 to PU77
P-ch
Alternate
function
Selector
Internal bus
RD
WRPORT
P7
Output latch
(P70 to P77)
WRPM
PM7
P70/KR0
to
P73/KR3,
P74/KR4/INTP8
to
P77/KR7/INTP11
PM70 to PM77
P7:
Port register 7
PU7:
Pull-up resistor option register 7
PM7:
Port mode register 7
RD:
Read signal
WR××: Write signal
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6.2.10 Port 8
78K0R/KF3-L
78K0R/KG3-L
(μPD78F10xx: xx = 10 to 12, 27,28)
(μPD78F10xx: xx = 13, 14, 29, 30)
P80
−
√
P81
−
√
P82
−
√
P83
−
√
P84
−
√
P85
−
√
P86
−
√
P87
−
√
Port 8 is an I/O port with an output latch. Port 8 can be set to the input mode or output mode in 1-bit units using port
mode register 8 (PM8). When the P80 to P87 pins are used as an input port, use of an on-chip pull-up resistor can be
specified in 1-bit units by pull-up resistor option register 8 (PU8).
Reset signal generation sets port 8 to input mode.
Figure 6-38 shows a block diagram of port 8.
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Figure 6-38. Block Diagram of P80 to P87
EVDD0, EVDD1
WRPU
PU8
PU80 to PU87
P-ch
Selector
Internal bus
RD
WRPORT
P8
Output latch
(P80 to P87)
P80 to P87
WRPM
PM8
PM80 to PM87
P8:
Port register 8
PU8:
Pull-up resistor option register 8
PM8:
Port mode register 8
RD:
Read signal
WR××: Write signal
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6.2.11 Port 9
78K0R/KF3-L
78K0R/KG3-L
(μPD78F10xx: xx = 10 to 12, 27,28)
(μPD78F10xx: xx = 13, 14, 29, 30)
P90
√
−
P91
√
√
P91 is an I/O port with an output latch. Port 9 can be set to the input mode or output mode in 1-bit units using port
mode register 9 (PM9). When the P90 and P91 pins are used as an input port, use of an on-chip pull-up resistor can be
specified in 1-bit units by pull-up resistor option register 9 (PU9).
Reset signal generation sets port 9 to input mode.
Figure 6-39 shows a block diagram of port 9.
Figure 6-39. Block Diagram of P90 and P91
EVDD0, EVDD1
WRPU
PU9
PU90, PU91
P-ch
Selector
Internal bus
RD
WRPORT
P9
Output latch
(P90, P91)
P90, P91
WRPM
PM9
PM90, PM91
P9:
Port register 9
PU9:
Pull-up resistor option register 9
PM9:
Port mode register 9
RD:
Read signal
WR××: Write signal
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6.2.12 Port 11
78K0R/KF3-L
78K0R/KG3-L
(μPD78F10xx: xx = 10 to 12, 27,28)
(μPD78F10xx: xx = 13, 14, 29, 30)
P110
√
√
P111
√
√
Port 11 is an I/O port with an output latch. Port 11 can be set to the input mode or output mode in 1-bit units using port
mode register 11 (PM11). When the P110 and P111 pins are used as an input port, use of an on-chip pull-up resistor can
be specified in 1-bit units by pull-up resistor option register 11 (PU11).
Reset signal generation sets port 11 to input mode.
Figures 6-40 and 6-41 show a block diagram of port 11.
Figure 6-40. Block Diagram of P110
EVDD0, EVDD1
WRPU
PU11
PU110
P-ch
Selector
Internal bus
RD
WRPORT
P11
Output latch
(P110)
P110
WRPM
PM11
PM110
P11:
Port register 11
PU11:
Pull-up resistor option register 11
PM11:
Port mode register 11
RD:
Read signal
WR××: Write signal
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Figure 6-41. Block Diagram of P111
EVDD0, EVDD1
WRPU
PU11
PU111
P-ch
Selector
Internal bus
RD
WRPORT
P11
Output latch
(P111)
P111
WRPM
PM11
PM111
P11:
Port register 11
PU11:
Pull-up resistor option register 11
PM11:
Port mode register 11
RD:
Read signal
WR××: Write signal
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6.2.13 Port 12
78K0R/KF3-L
78K0R/KG3-L
(μPD78F10xx: xx = 10 to 12, 27,28)
(μPD78F10xx: xx = 13, 14, 29, 30)
P120/INTP0/EXLVI
√
√
P121/X1
√
√
P122/X2/EXCLK
√
√
P123/XT1
√
√
P124/XT2
√
√
P120 is an I/O port with an output latch. Port 12 can be set to the input mode or output mode in 1-bit units using port
mode register 12 (PM12). When used as an input port, use of an on-chip pull-up resistor can be specified by pull-up
resistor option register 12 (PU12).
P121 to P124 are 4-bit input ports.
This port can also be used for external interrupt request input, potential input for external low-voltage detection,
connecting resonator for main system clock, connecting resonator for subsystem clock, and external clock input for main
system clock.
Reset signal generation sets port 12 to input mode.
Figures 6-42 to 6-44 show block diagrams of port 12.
Caution The function setting on P121 to P124 is available only once after the reset release. The port once set
for connection to an oscillator cannot be used as an input port unless the reset is performed.
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Figure 6-42. Block Diagram of P120
EVDD0, EVDD1
WRPU
PU12
PU120
P-ch
Alternate
function
Selector
Internal bus
RD
WRPORT
P12
Output latch
(P120)
P120/INTP0/EXLVI
WRPM
PM12
PM120
P12:
Port register 12
PU12:
Pull-up resistor option register 12
PM12:
Port mode register 12
RD:
Read signal
WR××: Write signal
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Figure 6-43. Block Diagram of P121 and P122
Clock generator
CMC
OSCSEL
RD
Internal bus
P122/X2/EXCLK
CMC
EXCLK, OSCSEL
RD
P121/X1
CMC:
Clock operation mode control register
RD:
Read signal
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Figure 6-44. Block Diagram of P123 and P124
Clock generator
CMC
OSCSELS
RD
Internal bus
P124/XT2
CMC
OSCSELS
RD
P123/XT1
CMC:
Clock operation mode control register
RD:
Read signal
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6.2.14 Port 13
78K0R/KF3-L
78K0R/KG3-L
(μPD78F10xx: xx = 10 to 12, 27,28)
(μPD78F10xx: xx = 13, 14, 29, 30)
√
√
Note
√
P130/INTP1
−
P131/TI06/TO06
Note
TI06/TO06 is shared with P06, in the 78K0R/KF3-L.
P130 is a 1-bit output-only port with an output latch.
P131 is a 1-bit I/O port with an output latch. When used as an input port, use of an on-chip pull-up resistor can be
specified by pull-up resistor option register 13 (PU13).
Reset signal generation sets port 13 to input mode.
This port can also be used for timer I/O.
Figures 6-45 and 6-46 show block diagrams of port 13.
Caution To use P131/TI06/TO06 as a general-purpose port, set bit 6 (TO06) of timer output register 0 (TO0) and
bit 6 (TOE06) of timer output enable register 0 (TOE0) to “0”, which is the same as their default status
setting.
Figure 6-45. Block Diagram of P130
Internal bus
RD
WRPORT
P13
Output latch
(P130)
P13:
Port register 13
RD:
Read signal
P130
WR××: Write signal
Remark When reset is effected, P130 outputs a low level. If P130 is set to output a high level before reset is effected,
the output signal of P130 can be dummy-output as the CPU reset signal.
Reset signal
P130
Set by software
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Figure 6-46. Block Diagram of P131
EVDD0, EVDD1
WRPU
PU13
PU131
P-ch
Alternate
function
Selector
Internal bus
RD
WRPORT
P13
Output latch
(P131)
P131/TI06/TO06
WRPM
PM13
PM131
Alternate
function
P13:
Port register 13
PU13:
Pull-up resistor option register 13
PM13:
Port mode register 13
RD:
Read signal
WR××: Write signal
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6.2.15 Port 14
78K0R/KF3-L
78K0R/KG3-L
(μPD78F10xx: xx = 10 to 12, 27,28)
(μPD78F10xx: xx = 13, 14, 29, 30)
√
√
Note 1
√
P142/SCK20/SCL20
√
√
P143/SI20/RxD2/SDA20
√
√
P140/PCLBUZ0/INTP6
P141/PCLBUZ1/INTP7
−
√
P144/SO20/TxD2
−
P145/TI07/TO07
Note 2
√
√
Notes 1. PCLBUZ/INTP7 is shared with P55, in the 78K0R/KF3-L.
2. TI07/TO07 is shared with P54, in the 78K0R/KF3-L.
Port 14 is an I/O port with an output latch. Port 14 can be set to the input mode or output mode in 1-bit units using port
mode register 14 (PM14). When the P140 to P145 pins are used as an input port, use of an on-chip pull-up resistor can
be specified in 1-bit units by pull-up resistor option register 14 (PU14).
Input to the P142 and P143 pins can be specified through a normal input buffer or a TTL input buffer in 1-bit units using
port input mode register 14 (PIM14).
Output from the P142 to P144 pins can be specified as N-ch open-drain output (VDD tolerance) in 1-bit units using port
output mode register 14 (POM14).
This port can also be used for timer I/O, external interrupt request input, clock/buzzer output, serial interface data I/O,
and clock I/O.
Reset signal generation sets port 14 to input mode.
Figures 6-47 to 6-50 show block diagrams of port 14.
Cautions 1. To use P142/SCK20/SCL20, P143/SI20/RxD2/SDA20, or P144/SO20/TxD2 as a general-purpose
port, note the serial array unit 1 setting. For details, refer to the following tables.
• Table 14-13 Relationship Between Register Settings and Pins (Channel 0 of Unit 1: CSI20,
UART2 Transmission, IIC20)
• Table 14-14 Relationship Between Register Settings and Pins (Channel 1 of Unit 1: UART2
Reception)
2. To use P145/TI07/TO07 as a general-purpose port, set bit 7 (TO07) of timer output register 0 (TO0)
and bit 7 (TOE07) of timer output enable register 0 (TOE0) to “0”, which is the same as their
default status setting.
3. To use P140/PCLBUZ0/INTP6 or P141/PCLBUZ1/INTP7 as a general-purpose port, set bit 7 of
clock output select registers 0 and 1 (CKS0, CKS1) to “0”, which is the same as their default
status settings.
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Figure 6-47. Block Diagram of P140
EVDD0, EVDD1
WRPU
PU14
PU140
P-ch
Alternate
function
Selector
Internal bus
RD
WRPORT
P14
Output latch
(P140)
P140/PCLBUZ0/INTP6
WRPM
PM14
PM140
Alternate
function
P14:
Port register 14
PU14:
Pull-up resistor option register 14
PM14:
Port mode register 14
RD:
Read signal
WR××: Write signal
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Figure 6-48. Block Diagram of P141 and P145
EVDD0, EVDD1
WRPU
PU14
PU141, PU145
P-ch
Alternate
function
Selector
Internal bus
RD
WRPORT
P14
Output latch
(P141, P145)
P141/PCLBUZ1/INTP7,
P145/TI07/TO07
WRPM
PM14
PM141, PM145
Alternate
function
P14:
Port register 14
PU14:
Pull-up resistor option register 14
PM14:
Port mode register 14
RD:
Read signal
WR××: Write signal
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Figure 6-49. Block Diagram of P142 and P143
WRPIM
PIM14
PIM142, PIM143
EVDD0, EVDD1
WRPU
PU14
PU142, PU143
P-ch
Alternate
function
CMOS
Selector
Internal bus
RD
TTL
WRPORT
P14
Output latch
(P142, P143)
WRPOM
P142/SCK20/SCL20,
P143/SI20/RxD2/SDA20
POM14
POM142, POM143
WRPM
PM14
PM142, PM143
Alternate
function
P14:
Port register 14
PU14:
Pull-up resistor option register 14
PM14:
Port mode register 14
PIM14: Port input mode register 14
POM14: Port output mode register 14
RD:
Read signal
WR××: Write signal
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Figure 6-50. Block Diagram of P144
EVDD0, EVDD1
WRPU
PU14
PU144
P-ch
Selector
Internal bus
RD
WRPORT
P14
Output latch
(P144)
P144/SO20/TxD2
WRPOM
POM14
POM144
WRPM
PM14
PM144
Alternate
function
P14:
Port register 14
PU14:
Pull-up resistor option register 14
PM14:
Port mode register 14
POM14: Port output mode register 14
RD:
Read signal
WR××: Write signal
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6.2.16 Port 15
78K0R/KF3-L
78K0R/KG3-L
(μPD78F10xx: xx = 10 to 12, 27,28)
(μPD78F10xx: xx = 13, 14, 29, 30)
P150/ANI8
√
√
P151/ANI9
√
√
P152/ANI10
√
√
P153/ANI11
√
√
P154/ANI12
−
√
P155/ANI13
−
√
P156/ANI14
−
√
P157/ANI15
−
√
Port 15 is an I/O port with an output latch. Port 15 can be set to the input mode or output mode in 1-bit units using port
mode register 15 (PM15).
This port can also be used for A/D converter analog input.
To use P150/ANI8 to P157/ANI15 as digital input pins, set them in the digital I/O mode by using the A/D port
configuration register (ADPC) and in the input mode by using the PM15 register. Use these pins starting from the lower bit.
To use P150/ANI8 to P157/ANI15 as digital output pins, set them in the digital I/O mode by using the ADPC register
and in the output mode by using the PM15 register.
Table 6-6. Setting Functions of P150/ANI8 to P157/ANI15 Pins
ADPC Register
PM15 Register
Digital I/O selection
Input mode
Analog input selection
Input mode
ADS Register
−
−
Output mode
Output mode
P150/ANI8 to P157/ANI15 Pins
Digital input
Digital output
Selects ANI.
Analog input (to be converted)
Does not select ANI.
Analog input (not to be converted)
Selects ANI.
Setting prohibited
Does not select ANI.
All P150/ANI8 to P157/ANI15 are set in the digital input mode when the reset signal is generated.
Figure 6-51 shows a block diagram of port 15.
Caution See 3.2.16 AVREF, AVSS, VDD, EVDD0, EVDD1, VSS, EVSS0, EVSS1 for the voltage to be applied to the AVREF
pin when using port 15 as a digital I/O.
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Figure 6-51. Block Diagram of P150 to P157
Selector
Internal bus
RD
WRPORT
P15
Output latch
(P150 to P157)
P150/ANI8 to
P157/ANI15
WRPM
PM15
PM150 to PM157
A/D converter
P15:
Port register 15
PM15:
Port mode register 15
RD:
Read signal
WR××: Write signal
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6.3 Registers Controlling Port Function
Port functions are controlled by the following six types of registers.
• Port mode registers (PMxx)
• Port registers (Pxx)
• Pull-up resistor option registers (PUxx)
• Port input mode registers (PIM0, PIM1, PIM14)
• Port output mode registers (POM0, POM1, POM14)
• A/D port configuration register (ADPC)
(1) Port mode registers (PMxx)
These registers specify input or output mode for the port in 1-bit units.
These registers can be set by a 1-bit or 8-bit memory manipulation instruction.
Reset signal generation sets these registers to FFH (FEH for PM13).
When port pins are used as alternate-function pins, set the port mode register by referencing 6.5 Settings of Port
Mode Register, and Output Latch When Using Alternate Function.
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Figure 6-52. Format of Port Mode Register (78K0R/KF3-L)
Symbol
7
6
5
4
3
2
1
0
Address
After reset
R/W
PM0
1
PM06
PM05
PM04
PM03
PM02
1
1
FFF20H
FFH
R/W
PM1
PM17
PM16
PM15
PM14
PM13
PM12
PM11
PM10
FFF21H
FFH
R/W
PM2
PM27
PM26
PM25
PM24
PM23
PM22
PM21
PM20
FFF22H
FFH
R/W
PM3
1
1
1
1
1
1
PM31
PM30
FFF23H
FFH
R/W
PM4
PM47
PM46
PM45
PM44
PM43
PM42
PM41
PM40
FFF24H
FFH
R/W
PM5
1
1
PM55
PM54
PM53
PM52
PM51
PM50
FFF25H
FFH
R/W
PM6
PM67
PM66
PM65
PM64
PM63
PM62
PM61
PM60
FFF26H
FFH
R/W
PM7
PM77
PM76
PM75
PM74
PM73
PM72
PM71
PM70
FFF27H
FFH
R/W
PM9
1
1
1
1
1
1
PM91
PM90
FFF29H
FFH
R/W
PM11
1
1
1
1
1
1
PM111
PM110
FFF2BH
FFH
R/W
PM12
1
1
1
1
1
1
1
PM120
FFF2CH
FFH
R/W
PM14
1
1
1
PM144
PM143
PM142
1
PM140
FFF2EH
FFH
R/W
PM15
1
1
1
1
PM153
PM152
PM151
PM150
FFF2FH
FFH
R/W
Pmn pin I/O mode selection
PMmn
(m = 0 to 7, 9, 11, 12, 14, 15; n = 0 to 7)
Caution
0
Output mode (output buffer on)
1
Input mode (output buffer off)
Be sure to set bits 0, 1 and 7 of the PM0 register, bits 2 to 7 of the PM3 register, bits 6 and 7 of the
PM5 register, bits 2 to 7 of the PM9 register, bits 2 to 7 of the PM11 register, bits 1 to 7 of the PM12
register, bits 1 and 5 to 7 of the PM14 register, and bits 4 to 7 of the PM15 register to “1”.
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Figure 6-53. Format of Port Mode Register (78K0R/KG3-L)
Symbol
7
6
5
4
3
2
1
0
Address
After reset
R/W
PM0
1
PM06
PM05
PM04
PM03
PM02
PM01
PM00
FFF20H
FFH
R/W
PM1
PM17
PM16
PM15
PM14
PM13
PM12
PM11
PM10
FFF21H
FFH
R/W
PM2
PM27
PM26
PM25
PM24
PM23
PM22
PM21
PM20
FFF22H
FFH
R/W
PM3
1
1
1
1
1
1
PM31
PM30
FFF23H
FFH
R/W
PM4
PM47
PM46
PM45
PM44
PM43
PM42
PM41
PM40
FFF24H
FFH
R/W
PM5
PM57
PM56
PM55
PM54
PM53
PM52
PM51
PM50
FFF25H
FFH
R/W
PM6
PM67
PM66
PM65
PM64
PM63
PM62
PM61
PM60
FFF26H
FFH
R/W
PM7
PM77
PM76
PM75
PM74
PM73
PM72
PM71
PM70
FFF27H
FFH
R/W
PM8
PM87
PM86
PM85
PM84
PM83
PM82
PM81
PM80
FFF28H
FFH
R/W
PM9
1
1
1
1
1
1
PM91
1
FFF29H
FFH
R/W
PM11
1
1
1
1
1
1
PM111
PM110
FFF2BH
FFH
R/W
PM12
1
1
1
1
1
1
1
PM120
FFF2CH
FFH
R/W
PM13
1
1
1
1
1
1
PM131
0
FFF2DH
FEH
R/W
PM14
1
1
PM145
PM144
PM143
PM142
PM141
PM140
FFF2EH
FFH
R/W
PM15
PM157
PM156
PM155
PM154
PM153
PM152
PM151
PM150
FFF2FH
FFH
R/W
Pmn pin I/O mode selection
PMmn
(m = 0 to 9, 11 to 15; n = 0 to 7)
Caution
0
Output mode (output buffer on)
1
Input mode (output buffer off)
Be sure to set bit 7 of the PM0 register, bits 2 to 7 of the PM3 register, bits 0 and 2 to 7 of the PM9
register, bits 2 to 7 of the PM11 register, bits 1 to 7 of the PM12 register, bits 2 to 7 of the PM13
register, and bits 6 and 7 of the PM14 register to “1”. And be sure to set bit 0 of the PM13 register to
“0”.
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(2) Port registers (Pxx)
These registers set the output latch value of a port.
If the data is read in the input mode, the pin level is read. If it is read in the output mode, the output latch value is
readNote.
These registers can be set by a 1-bit or 8-bit memory manipulation instruction.
Reset signal generation clears these registers to 00H.
Note It is always 0 and never a pin level that is read out if a port is read during the input mode when P2 and P15 are
set to function as an analog input for a A/D converter.
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Figure 6-54. Format of Port Register (78K0R/KF3-L)
Symbol
7
6
5
4
3
2
1
0
Address
P0
0
P06
P05
P04
P03
P02
0
0
FFF00H
00H (output latch) R/W
P1
P17
P16
P15
P14
P13
P12
P11
P10
FFF01H
00H (output latch) R/W
P2
P27
P26
P25
P24
P23
P22
P21
P20
FFF02H
00H (output latch) R/W
P3
0
0
0
0
0
0
P31
P30
FFF03H
00H (output latch) R/W
P4
P47
P46
P45
P44
P43
P42
P41
P40
FFF04H
00H (output latch) R/W
P5
0
0
P55
P54
P53
P52
P51
P50
FFF05H
00H (output latch) R/W
P6
P67
P66
P65
P64
P63
P62
P61
P60
FFF06H
00H (output latch) R/W
P7
P77
P76
P75
P74
P73
P72
P71
P70
FFF07H
00H (output latch) R/W
P9
0
0
0
0
0
0
P91
P90
FFF09H
00H (output latch) R/W
P11
0
0
0
0
0
0
P111
P110
FFF0BH
00H (output latch) R/W
P12
0
0
0
P124
P123
P122
P121
P120
FFF0CH
P13
0
0
0
0
0
0
0
P130
FFF0DH
00H (output latch) R/W
P14
0
0
0
P144
P143
P142
0
P140
FFF0EH
00H (output latch) R/W
P15
0
0
0
0
P153
P152
P151
P150
FFF0FH
00H (output latch) R/W
Pmn
After reset
Undefined
R/W
R/W
Note
m = 0 to 7, 9, 11 to 15; n = 0 to 7
Output data control (in output mode)
Input data read (in input mode)
0
Output 0
Input low level
1
Output 1
Input high level
Note P121 to P124 are read-only.
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Figure 6-55. Format of Port Register (78K0R/KG3-L)
Symbol
7
6
5
4
3
2
1
0
Address
P0
0
P06
P05
P04
P03
P02
P01
P00
FFF00H
00H (output latch) R/W
P1
P17
P16
P15
P14
P13
P12
P11
P10
FFF01H
00H (output latch) R/W
P2
P27
P26
P25
P24
P23
P22
P21
P20
FFF02H
00H (output latch) R/W
P3
0
0
0
0
0
0
P31
P30
FFF03H
00H (output latch) R/W
P4
P47
P46
P45
P44
P43
P42
P41
P40
FFF04H
00H (output latch) R/W
P5
P57
P56
P55
P54
P53
P52
P51
P50
FFF05H
00H (output latch) R/W
P6
P67
P66
P65
P64
P63
P62
P61
P60
FFF06H
00H (output latch) R/W
P7
P77
P76
P75
P74
P73
P72
P71
P70
FFF07H
00H (output latch) R/W
P8
P87
P86
P85
P84
P83
P82
P81
P80
FFF08H
00H (output latch) R/W
P9
0
0
0
0
0
0
P91
0
FFF09H
00H (output latch) R/W
P11
0
0
0
0
0
0
P111
P110
FFF0BH
00H (output latch) R/W
P12
0
0
0
P124
P123
P122
P121
P120
FFF0CH
P13
0
0
0
0
0
0
P131
P130
FFF0DH
00H (output latch) R/W
P14
0
0
P145
P144
P143
P142
P141
P140
FFF0EH
00H (output latch) R/W
P15
P157
P156
P155
P154
P153
P152
P151
P150
FFF0FH
00H (output latch) R/W
Pmn
After reset
Undefined
R/W
R/W
Note
m = 0 to 9, 11 to 15; n = 0 to 7
Output data control (in output mode)
Input data read (in input mode)
0
Output 0
Input low level
1
Output 1
Input high level
Note P121 to P124 are read-only.
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(3) Pull-up resistor option registers (PUxx)
These registers specify whether the on-chip pull-up resistors are to be used or not. On-chip pull-up resistors can be
used in 1-bit units only for the bits set to input mode of the pins to which the use of an on-chip pull-up resistor has
been specified in these registers. On-chip pull-up resistors cannot be connected to bits set to output mode and bits
used as alternate-function output pins, regardless of the settings of these registers.
These registers can be set by a 1-bit or 8-bit memory manipulation instruction.
Reset signal generation clears these registers to 00H.
Figure 6-56. Format of Pull-up Resistor Option Register (78K0R/KF3-L)
Symbol
7
6
5
4
3
2
1
0
Address
After reset
R/W
PU0
0
PU06
PU05
PU04
PU03
PU02
0
0
F0030H
00H
R/W
PU1
PU17
PU16
PU15
PU14
PU13
PU12
PU11
PU10
F0031H
00H
R/W
PU3
0
0
0
0
0
0
PU31
PU30
F0033H
00H
R/W
PU4
PU47
PU46
PU45
PU44
PU43
PU42
PU41
PU40
F0034H
00H
R/W
PU5
0
0
PU55
PU54
PU53
PU52
PU51
PU50
F0035H
00H
R/W
PU6
PU67
PU66
PU65
PU64
0
0
0
0
F0036H
00H
R/W
PU7
PU77
PU76
PU75
PU74
PU73
PU72
PU71
PU70
F0037H
00H
R/W
PU9
0
0
0
0
0
0
PU91
PU90
F0039H
00H
R/W
PU11
0
0
0
0
0
0
PU111
PU110
F003BH
00H
R/W
PU12
0
0
0
0
0
0
0
PU120
F003CH
00H
R/W
PU14
0
0
0
PU144
PU143
PU142
0
PU140
F003EH
00H
R/W
Pmn pin on-chip pull-up resistor selection
PUmn
(m = 0, 1, 3 to 7, 9, 11, 12, 14; n = 0 to 7)
0
On-chip pull-up resistor not connected
1
On-chip pull-up resistor connected
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Figure 6-57. Format of Pull-up Resistor Option Register (78K0R/KG3-L)
Symbol
7
6
5
4
3
2
1
0
Address
After reset
R/W
PU0
0
PU06
PU05
PU04
PU03
PU02
PU01
PU00
F0030H
00H
R/W
PU1
PU17
PU16
PU15
PU14
PU13
PU12
PU11
PU10
F0031H
00H
R/W
PU3
0
0
0
0
0
0
PU31
PU30
F0033H
00H
R/W
PU4
PU47
PU46
PU45
PU44
PU43
PU42
PU41
PU40
F0034H
00H
R/W
PU5
PU57
PU56
PU55
PU54
PU53
PU52
PU51
PU50
F0035H
00H
R/W
PU6
PU67
PU66
PU65
PU64
0
0
0
0
F0036H
00H
R/W
PU7
PU77
PU76
PU75
PU74
PU73
PU72
PU71
PU70
F0037H
00H
R/W
PU8
PU87
PU86
PU85
PU84
PU83
PU82
PU81
PU80
F0038H
00H
R/W
PU9
0
0
0
0
0
0
PU91
0
F0039H
00H
R/W
PU11
0
0
0
0
0
0
PU111
PU110
F003BH
00H
R/W
PU12
0
0
0
0
0
0
0
PU120
F003CH
00H
R/W
PU13
0
0
0
0
0
0
PU131
0
F003DH
00H
R/W
PU14
0
0
PU145
PU144
PU143
PU142
PU141
PU140
F003EH
00H
R/W
Pmn pin on-chip pull-up resistor selection
PUmn
(m = 0, 1, 3 to 9, 11 to 14; n = 0 to 7)
0
On-chip pull-up resistor not connected
1
On-chip pull-up resistor connected
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(4) Port input mode registers (PIM0, PIM1, PIM14)
These registers set the input buffer of P03, P04, P10, P11, P142, or P143 in 1-bit units.
TTL input buffer can be selected during serial communication with an external device of the different potential.
These registers can be set by a 1-bit or 8-bit memory manipulation instruction.
Reset signal generation clears these registers to 00H.
Figure 6-58. Format of Port Input Mode Register
Symbol
7
6
5
4
3
2
1
0
Address
After reset
R/W
PIM0
0
0
0
PIM04
PIM03
0
0
0
F0040H
00H
R/W
PIM1
0
0
0
0
0
0
PIM11
PIM10
F0044H
00H
R/W
PIM14
0
0
0
0
PIM143
PIM142
0
0
F004EH
00H
R/W
Pmn pin input buffer selection
PIMmn
(m = 0, 1, 14; n = 0 to 4)
0
Normal input buffer
1
TTL input buffer
(5) Port output mode registers (POM0, POM1, POM14)
These registers set the output mode of P02 to P04, P10, P12, or P142 to P144 in 1-bit units.
N-ch open drain output (VDD tolerance) mode can be selected during serial communication with an external device of
2
the different potential, and for the SDA10 and SDA20 pins during simplified I C communication with an external device
of the same potential.
These registers can be set by a 1-bit or 8-bit memory manipulation instruction.
Reset signal generation clears these registers to 00H.
Figure 6-59. Format of Port Input Mode Register
Symbol
7
6
5
4
3
2
1
0
Address
After reset
R/W
POM0
0
0
0
POM04
POM03
POM02
0
0
F0050H
00H
R/W
POM1
0
0
0
0
0
POM12
0
POM10
F0051H
00H
R/W
POM14
0
0
0
POM144 POM143 POM142
0
0
F005EH
00H
R/W
Pmn pin output mode selection
POMmn
(m = 0, 1, 14; n = 0, 2 to 4)
0
Normal output mode
1
N-ch open-drain output (VDD tolerance) mode
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(6) A/D port configuration register (ADPC)
This register switches the P20/ANI0 to P27/ANI7 and P150/ANI8 to P157/ANI15 pins to digital I/O of port or analog
input of A/D converter.
The ADPC register can be set by a 1-bit or 8-bit memory manipulation instruction.
Reset signal generation sets this register to 10H.
Figure 6-60. Format of A/D Port Configuration Register (ADPC)
Address: F0017H
After reset: 10H
R/W
Symbol
7
6
5
4
3
2
1
0
ADPC
0
0
0
ADPC4
ADPC3
ADPC2
ADPC1
ADPC0
ADP ADP ADP ADP ADP
C4 C3 C2 C1 C0
Analog input (A)/digital I/O (D) switching
Port 15
Port 2
ANI15/ ANI14/ ANI13/ ANI12/ ANI11/ ANI10/ ANI9/ ANI8/ ANI7/ ANI6/ ANI5/ ANI4/ ANI3/ ANI2/ ANI1/ ANI0/
P157 P156 P155 P154 P153 P152 P151 P150 P27
P26
P25
P24
P23
P22
P21
P20
0
0
0
0
0
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
0
0
0
0
1
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
D
0
0
0
1
0
A
A
A
A
A
A
A
A
A
A
A
A
A
A
D
D
0
0
0
1
1
A
A
A
A
A
A
A
A
A
A
A
A
A
D
D
D
0
0
1
0
0
A
A
A
A
A
A
A
A
A
A
A
A
D
D
D
D
0
0
1
0
1
A
A
A
A
A
A
A
A
A
A
A
D
D
D
D
D
0
0
1
1
0
A
A
A
A
A
A
A
A
A
A
D
D
D
D
D
D
0
0
1
1
1
A
A
A
A
A
A
A
A
A
D
D
D
D
D
D
D
0
1
0
0
0
A
A
A
A
A
A
A
A
D
D
D
D
D
D
D
D
0
1
0
0
1
A
A
A
A
A
A
A
D
D
D
D
D
D
D
D
D
0
1
0
1
0
A
A
A
A
A
A
D
D
D
D
D
D
D
D
D
D
0
1
0
1
1
A
A
A
A
A
D
D
D
D
D
D
D
D
D
D
D
0
1
1
0
0
A
A
A
A
D
D
D
D
D
D
D
D
D
D
D
D
0
1
1
0
1
A
A
A
D
D
D
D
D
D
D
D
D
D
D
D
D
0
1
1
1
0
A
A
D
D
D
D
D
D
D
D
D
D
D
D
D
D
0
1
1
1
1
A
D
D
D
D
D
D
D
D
D
D
D
D
D
D
D
1
0
0
0
0
D
D
D
D
D
D
D
D
D
D
D
D
D
D
D
D
Other than above
Setting prohibited
Cautions 1. Set the channel used for A/D conversion to the input mode by using port mode registers 2 and
15 (PM2, PM15).
2. Do not set the pin set by the ADPC register as digital I/O by the analog input channel
specification register (ADS).
3. P20/ANI0 to P27/ANI7 and P150/ANI8 to P157/ANI15 are set as analog inputs in the order of
P157/ANI15, …, P150/ANI8, P27/ANI7, …, P20/ANI0 by the A/D port configuration register (ADPC).
When using P20/ANI0 to P27/ANI7 and P150/ANI8 to P157/ANI15 as analog inputs, start
designing from P157/ANI15.
4. Be sure to first set the ADCEN bit of peripheral enable register 0 (PER0) to 1 when setting up the
ADPC register. If ADCEN = 0, writing to the ADPC register is ignored and specified values are
returned to the initial values.
Remark P20/ANI0 to P27/ANI7, P150/ANI8 to P153/ANI11: 78K0R/KF3-L
P20/ANI0 to P27/ANI7, P150/ANI8 to P157/ANI15: 78K0R/KG3-L
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6.4 Port Function Operations
Port operations differ depending on whether the input or output mode is set, as shown below.
6.4.1 Writing to I/O port
(1) Output mode
A value is written to the output latch by a transfer instruction, and the output latch contents are output from the pin.
Once data is written to the output latch, it is retained until data is written to the output latch again.
The data of the output latch is cleared when a reset signal is generated.
(2) Input mode
A value is written to the output latch by a transfer instruction, but since the output buffer is off, the pin status does not
change.
Once data is written to the output latch, it is retained until data is written to the output latch again.
The data of the output latch is cleared when a reset signal is generated.
6.4.2 Reading from I/O port
(1) Output mode
The output latch contents are read by a transfer instruction. The output latch contents do not change.
(2) Input mode
The pin status is read by a transfer instruction. The output latch contents do not change.
6.4.3 Operations on I/O port
(1) Output mode
An operation is performed on the output latch contents, and the result is written to the output latch. The output latch
contents are output from the pins.
Once data is written to the output latch, it is retained until data is written to the output latch again.
The data of the output latch is cleared when a reset signal is generated.
(2) Input mode
The pin level is read and an operation is performed on its contents. The result of the operation is written to the output
latch, but since the output buffer is off, the pin status does not change.
The data of the output latch is cleared when a reset signal is generated.
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6.4.4 Connecting to external device with different potential (2.5 V, 3 V)
When parts of ports 0, 1, 14 operate with VDD = 4.0 to 5.5 V, I/O connections with an external device that operates on
2.5 V, 3 V power supply voltage are possible.
Regarding inputs, CMOS/TTL switching is possible on a bit-by-bit basis by the port input mode registers (PIM0, PIM1,
PIM14).
Moreover, regarding outputs, different potentials can be supported by switching the output buffer to the N-ch open drain
(VDD withstand voltage) by the port output mode registers (POM0, POM1, POM14).
(1) Setting procedure when using I/O pins of UART0 to UART2, CSI00, CSI10, and CSI20 functions
(a) Use as 2.5 V, 3 V input port
<1> After reset release, the port mode is the input mode (Hi-Z).
<2> If pull-up is needed, externally pull up the pin to be used (on-chip pull-up resistor cannot be used).
In case of UART0:
P11
In case of UART1:
P03
In case of UART2:
P143
In case of CSI00:
P10, P11
In case of CSI10:
P03, P04
In case of CSI20:
P142, P143
<3> Set the corresponding bit of the PIMn register to 1 to switch to the TTL input buffer.
<4> VIH/VIL operates on 2.5 V, 3 V operating voltage.
(b) Use as 2.5 V, 3 V output port
<1> After reset release, the port mode changes to the input mode (Hi-Z).
<2> Pull up externally the pin to be used (on-chip pull-up resistor cannot be used).
In case of UART1:
P12
In case of UART1:
P02
In case of UART2:
P144
In case of CSI00:
P10, P12
In case of CSI10:
P02, P04
In case of CSI20:
P142, P144
<3> Set the output latch of the corresponding port to 1.
<4> Set the corresponding bit of the POMn register to 1 to set the N-ch open drain output (VDD withstand
voltage) mode.
<5> Set the output mode by manipulating the PMn register.
At this time, the output data is high level, so the pin is in the Hi-Z state.
<6> Communication is started by setting the serial array unit.
Remark n = 0, 1, 14
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(2) Setting procedure when using I/O pins of simplified IIC10 and IIC20 functions
<1> After reset release, the port mode is the input mode (Hi-Z).
<2> Externally pull up the pin to be used (on-chip pull-up resistor cannot be used).
In case of simplified IIC10:
P03, P04
In case of simplified IIC20:
P142, P143
<3> Set the output latch of the corresponding port to 1.
<4> Set the corresponding bit of the POMn register to 1 to set the N-ch open drain output (VDD withstand
voltage) mode.
<5> Set the corresponding bit of the PMn register to the output mode (data I/O is possible in the output mode).
At this time, the output data is high level, so the pin is in the Hi-Z state.
<6> Enable the operation of the serial array unit and set the mode to the simplified IIC mode.
Remark n = 0, 14
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6.5 Settings of Port Mode Register, and Output Latch When Using Alternate Function
To use the alternate function of a port pin, set the port mode register, and output latch as shown in Table 6-7 or Table
6-8.
Table 6-7. Settings of Port Mode Register, and Output Latch When Using Alternate Function (78K0R/KF3-L) (1/2)
Pin Name
Alternate Function
Function Name
P02
P03
P04
P10
P11
P12
P××
Pin Name
Alternate Function
Function Name
PM××
P××
I/O
SO10
Output
0
1
P40
TOOL0
I/O
×
×
TxD1
Output
0
1
P41
TOOL1
Output
×
×
SI10
Input
1
×
P42
TI04
Input
1
×
RxD1
Input
1
×
TO04
Output
0
0
SDA10
I/O
0
1
SCK01
Input
1
×
SCK10
Input
1
×
Output
0
1
Output
0
1
P44
SI01
Input
1
×
I/O
0
1
P45
SO01
Output
0
1
×
P50
SCK40
Input
1
×
Output
0
1
INTP1
Input
1
×
SI40
Input
1
×
SCL10
P05, P06
PM××
I/O
P43
TI05, TI06
Input
1
TO05, TO06
Output
0
0
SCK00
Input
1
×
Output
0
1
SI00
Input
1
×
RxD4
Input
1
×
RxD0
Input
1
×
INTP2
Input
1
×
SO00
Output
0
1
SO40
Output
0
1
Output
0
1
TxD4
Output
0
1
1
TO00
Output
0
0
SCK41
Input
1
×
Output
0
1
TI00
Input
1
×
SI41
Input
1
×
TxD0
P51
P52
P13
TxD3
Output
0
P14
RxD3
Input
1
×
P15
RTCDIV
Output
0
0
RTCCL
Output
0
0
TI01
Input
1
×
TO01
Output
0
0
TI07
Input
1
×
INTP5
Input
1
×
TO07
Output
0
0
Input
1
×
SO41
Output
0
1
Output
0
0
PCLBUZ1
Output
0
0
Input
1
×
INTP7
Input
1
×
RTC1HZ
Output
0
0
P60
SCL0
I/O
0
0
INTP3
Input
1
×
P61
SDA0
I/O
0
0
TI03
Input
1
×
P64 to P67
TI10 to TI13
Input
1
×
TO03
Output
0
0
TO10 to TO13
Output
0
0
INTP4
Input
1
×
KR0 to KR3
Input
1
×
P16
P17
TI02
TO02
P20 to P27
Note
P30
P31
Remark
Note
ANI0 to ANI7
×:
P53
P54
P55
P70 to P73
don’t care
PM××: Port mode register
P××:
Port output latch
(Note is listed on the next page.)
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Table 6-7. Settings of Port Mode Register, and Output Latch When Using Alternate Function (78K0R/KF3-L) (2/2)
Pin Name
Alternate Function
PM××
P××
INTP8 to INTP11 Input
1
×
KR4 to KR7
Input
1
×
INTP0
Input
1
×
EXLVI
Input
1
×
PCLBUZ0
Output
0
0
INTP6
Input
1
×
SCK20
Input
1
×
Output
0
1
Function Name
P74 to P77
P120
P140
P142
P143
P144
P153
Note
Note
SCL20
I/O
0
1
SI20
Input
1
×
RxD2
Input
1
×
SDA20
I/O
0
1
SO20
Output
0
1
TxD2
Output
0
1
Input
1
×
ANI8 to
P150 to
I/O
Note
ANI11
The functions of the ANI0/P20 to ANI7/P27 and ANI8/P150 to ANI11/P153 pins can be selected by using the
A/D port configuration register (ADPC), analog input channel specification register (ADS), and port mode
registers 2, 15 (PM2, PM15).
ADPC Register
Digital I/O selection
PM2 and PM15
Registers
ADS Register
Input mode
Output mode
Analog input selection
ANI0/P20 to ANI7/P27,
ANI8/P150 to ANI11/P153 Pins
−
Digital input
−
Digital output
Input mode
Selects ANI.
Analog input (to be converted)
Does not select ANI.
Analog input (not to be converted)
Output mode
Selects ANI.
Setting prohibited
Does not select ANI.
Remark
×:
don’t care
PM××: Port mode register
P××:
Port output latch
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Table 6-8. Settings of Port Mode Register, and Output Latch When Using Alternate Function (78K0R/KG3-L)
Pin Name
Alternate Function
Function Name
PM××
P××
Pin Name
I/O
Alternate Function
Function Name
P××
I/O
P00
TI00
Input
1
×
P01
TO00
Output
0
0
P02
SO10
Output
0
1
TxD1
Output
0
1
P47
SI10
Input
1
×
P50
SCK40
RxD1
Input
1
×
SDA10
I/O
0
1
SCK10
Input
1
×
Output
0
1
SCL10
I/O
0
1
SCK00
Input
1
×
Output
0
1
SI00
Input
1
RxD0
Input
1
SO00
Output
TxD0
Output
P13
TxD3
Output
0
1
P14
RxD3
Input
1
×
P70 to P73
P15
RTCDIV
Output
0
0
P74 to P77
INTP8 to INTP11 Input
1
×
RTCCL
Output
0
0
KR4 to KR7
Input
1
×
TI01
Input
1
×
INTP0
Input
1
×
TO01
Output
0
0
EXLVI
Input
1
×
×
P03
P04
P10
P11
P12
P16
P17
P30
P31
P51
TI05
Input
1
×
TO05
Output
0
0
INTP1
Input
1
×
INTP2
Input
1
×
×
SI40
Input
1
Output
0
1
Input
1
×
×
RxD4
Input
1
SO40
Output
0
1
TxD4
Output
0
1
P53
SCK41
Input
1
×
P54
SI41
Input
1
×
×
P55
SO41
Output
0
1
×
P60
SCL0
I/O
0
0
0
1
P61
SDA0
I/O
0
0
0
1
P64 to P67
TI10 to TI13
Input
1
×
TO10 to TO13
Output
0
0
KR0 to KR3
Input
1
×
INTP5
Input
1
×
TI02
Input
1
×
TO02
Output
0
0
1
×
P20 to P27Note ANI0 to ANI7Note Input
P46
PM××
RTC1HZ
Output
0
0
INTP3
Input
1
×
TI03
Input
1
×
TO03
Output
0
0
INTP4
Input
1
×
P52
P120
P131
P140
P141
P142
Input
1
Output
0
0
PCLBUZ0
Output
0
0
INTP6
Input
1
×
PCLBUZ1
Output
0
0
INTP7
Input
1
×
SCK20
Input
1
×
Output
0
1
SCL20
I/O
0
1
P40
TOOL0
I/O
×
×
SI20
Input
1
×
P41
TOOL1
Output
×
×
RxD2
Input
1
×
P42
TI04
Input
1
×
SDA20
I/O
0
1
TO04
Output
0
0
P43
SCK01
Input
1
×
Output
0
1
P44
SI01
Input
1
×
P45
SO01
Output
0
1
Remark
×:
P143
TI06
TO06
P144
P145
SO20
Output
0
1
TxD2
Output
0
1
×
TI07
Input
1
TO07
Output
0
0
P150 to
ANI8 to
Input
1
×
P157Note
ANI15Note
don’t care
PM××: Port mode register
P××:
Port output latch
(Note is listed on the next page.)
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Note
CHAPTER 6 PORT FUNCTIONS (78K0R/KF3-L, 78K0R/KG3-L)
The functions of the ANI0/P20 to ANI7/P27 and ANI8/P150 to ANI15/P157 pins can be selected by using the
A/D port configuration register (ADPC), analog input channel specification register (ADS), and port mode
registers 2, 15 (PM2, PM15).
ADPC Register
Digital I/O selection
Analog input selection
PM2 and PM15
Registers
ADS Register
ANI0/P20 to ANI7/P27,
ANI8/P150 to ANI15/P157 Pins
Input mode
−
Digital input
Output mode
−
Digital output
Input mode
Output mode
Selects ANI.
Analog input (to be converted)
Does not select ANI.
Analog input (not to be converted)
Selects ANI.
Setting prohibited
Does not select ANI.
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CHAPTER 6 PORT FUNCTIONS (78K0R/KF3-L, 78K0R/KG3-L)
6.6 Cautions on 1-Bit Manipulation Instruction for Port Register n (Pn)
When a 1-bit manipulation instruction is executed on a port that provides both input and output functions, the output
latch value of an input port that is not subject to manipulation may be written in addition to the targeted bit.
Therefore, it is recommended to rewrite the output latch when switching a port from input mode to output mode.
<Example>
When P10 is an output port, P11 to P17 are input ports (all pin statuses are high level), and the port
latch value of port 1 is 00H, if the output of output port P10 is changed from low level to high level via a
1-bit manipulation instruction, the output latch value of port 1 is FFH.
Explanation:
The targets of writing to and reading from the Pn register of a port whose PMnm bit is 1 are the output
latch and pin status, respectively.
A 1-bit manipulation instruction is executed in the following order in the 78K0R/KF3-L and 78K0R/KG3-L.
<1> The Pn register is read in 8-bit units.
<2> The targeted one bit is manipulated.
<3> The Pn register is written in 8-bit units.
In step <1>, the output latch value (0) of P10, which is an output port, is read, while the pin statuses of
P11 to P17, which are input ports, are read. If the pin statuses of P11 to P17 are high level at this time,
the read value is FEH.
The value is changed to FFH by the manipulation in <2>.
FFH is written to the output latch by the manipulation in <3>.
Figure 6-61. Bit Manipulation Instruction (P10)
1-bit manipulation
instruction
(set1 P1.0)
is executed for P10
bit.
P10
Low-level output
P11 to P17
P10
High-level output
P11 to P17
Pin status: High level
Port 1 output latch
0
0
0
Pin status: High level
Port 1 output latch
0
0
0
0
0
1
1
1
1
1
1
1
1
1-bit manipulation instruction for P10 bit
<1> Port register 1 (P1) is read in 8-bit units.
• In the case of P10, an output port, the value of the port output latch (0) is read.
• In the case of P11 to P17, input ports, the pin status (1) is read.
<2> Set the P10 bit to 1.
<3> Write the results of <2> to the output latch of port register 1 (P1)
in 8-bit units.
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CHAPTER 7 CLOCK GENERATOR
CHAPTER 7 CLOCK GENERATOR
7.1 Functions of Clock Generator
The clock generator generates the clock to be supplied to the CPU and peripheral hardware.
The following three kinds of system clocks and clock oscillators are selectable.
(1) Main system clock
<1> X1 oscillator
This circuit oscillates a clock of fX = 2 to 20 MHz by connecting a resonator to X1 and X2.
Oscillation can be stopped by executing the STOP instruction or setting of the MSTOP bit (bit 7 of the clock
operation status control register (CSC)).
<2> Internal high-speed oscillatorNote
This circuit oscillates clocks of fIH = 1 and 8 MHz (TYP.). After a reset release, the CPU always starts
operating with this internal high-speed oscillation clock. Oscillation can be stopped by executing the STOP
instruction or setting the HIOSTOP bit (bit 0 of the CSC register).
<3> 20 MHz internal high-speed oscillation clock oscillatorNote
This circuit oscillates a clock of fIH20 = 20 MHz (TYP.). Oscillation can be started by setting bit 0 (DSCON) of
the 20 MHz internal high-speed oscillation control register (DSCCTL) to 1 with VDD ≥ 2.7 V. Oscillation can
be stopped by setting the DSCON bit to 0.
Note To use the 1, 8, or 20 MHz internal high-speed oscillation clock, use the option byte to set the
frequency in advance (for details, see CHAPTER 25 OPTION BYTE). Also, the internal high-speed
oscillator automatically starts oscillating after reset release. To use the 20 MHz internal high-speed
oscillator to operate the microcontroller, oscillation is started by setting bit 0 (DSCON) of the 20 MHz
internal high-speed oscillation control register (DSCCTL) to 1.
An external main system clock (fEX = 2 to 20 MHz) can also be supplied from the EXCLK/X2/P122 pin. An external
main system clock input can be disabled by executing the STOP instruction or setting of the MSTOP bit.
As the main system clock, a high-speed system clock (X1 clock or external main system clock) or internal highspeed oscillation clock can be selected by setting of the MCM0 bit (bit 4 of the system clock control register (CKC)).
Note
(2) Subsystem clock
• XT1 clock oscillator
This circuit oscillates a clock of fSUB = 32.768 kHz by connecting a 32.768 kHz resonator to XT1 and XT2.
Oscillation can be stopped by setting the XTSTOP bit (bit 6 of the clock operation status control register (CSC)).
Note
The 78K0R/KC3-L (40-pin) doesn’t have the subsystem clock.
Remark
f X:
X1 clock oscillation frequency
fIH:
Internal high-speed oscillation clock frequency
fIH20: 20 MHz internal high-speed oscillation clock frequency
fEX:
External main system clock frequency
fSUB: Subsystem clock frequency
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(3) Internal low-speed oscillation clock (clock dedicated to watchdog timer)
• Internal low-speed oscillator
This circuit oscillates a clock of fIL = 30 kHz (TYP.).
The internal low-speed oscillation clock cannot be used as the CPU clock. The only hardware that operates with
the internal low-speed oscillation clock is the watchdog timer.
Oscillation is stopped when the watchdog timer stops.
Remarks 1. fIL: Internal low-speed oscillation clock frequency
2. The watchdog timer stops in the following cases.
• When bit 4 (WDTON) of an option byte (000C0H) = 0
• If the HALT or STOP instruction is executed when bit 4 (WDTON) of an option byte (000C0H) = 1 and
bit 0 (WDSTBYON) = 0
7.2 Configuration of Clock Generator
The clock generator includes the following hardware.
Table 7-1. Configuration of Clock Generator
Item
Configuration
Control registers
Clock operation mode control register (CMC)
System clock control register (CKC)
Clock operation status control register (CSC)
Oscillation stabilization time counter status register (OSTC)
Oscillation stabilization time select register (OSTS)
20 MHz internal high-speed oscillation control register (DSCCTL)
Note 1
Note 1
(PER0, PER1, PER2
)
Peripheral enable registers 0, 1, 2
Operation speed mode control register (OSMC)
Oscillators
X1 oscillator
Note 2
XT1 oscillator
Internal high-speed oscillator
Internal low-speed oscillator
Notes 1.
2.
The PER2 register is only mounted in the 78K0R/KC3-L, 78K0R/KD3-L, and 78K0R/KE3-L.
The 78K0R/KC3-L (40-pin) doesn’t have the XT1 oscillator (subsystem clock).
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Internal bus
Clock operation status
control register
(CSC)
Clock operation mode
control register
(CMC)
AMPH EXCLK OSCSEL
Oscillation stabilization
time select register (OSTS)
System clock control
register (CKC)
0
OSTS2 OSTS1 OSTS0
MSTOP
CSS MCS MCM0
1
MD
IV2
MD
IV1
MD
IV0
Standby controller
3
4
STOP mode
signal
X2/EXCLK
/P122
Option byte (000C1H)
FRQSEL2,
FRQSEL1
Normal
operation mode
Crystal/ceramic
oscillation
fX
External input
clock
fEX
Oscillation stabilization
time counter status
register (OSTC)
fMX
Internal high-speed
oscillator
Internal high-speed
oscillation (1 MHz (TYP.))
fMAIN/25
fIH1
fMAIN
fIH
Internal high-speed
oscillation (8 MHz (TYP.))
Main system clock
source selector
fIH8
fMAIN/24
fMAIN/23
fMAIN/22
CPU clock
and peripheral fCLK
hardware
clock source
selection
Selector
X1/P121
HALT mode
MOST MOST MOST MOST MOST MOST MOST MOST
8
9
10
11 13 15 17 18
High-speed system
clock oscillator
STOP mode
X1 oscillation
stabilization time counter
Prescaler
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Figure 7-1. Block Diagram of Clock Generator (78K0R/KC3-L (40-pin))
CPU
Timer array unit 0
fMAIN/2
Internal high-speed
oscillation (20 MHz (TYP.))
fIH20
fIH20
Option byte (000C0H)
WDTON
WDSTBYON
Internal low-speed
oscillator
fIL
Internal low-speed
A/D converter
Watchdog timer
DSCS SELDSC DSCON
20 MHz internal high-speed
oscillation control register
(DSCCTL)
Internal bus
TAU0
EN
Peripheral enable
register 2 (PER2)
OACMP
EN
Peripheral enable
register 1 (PER1)
SAU0
EN
ADC
EN
Peripheral enable
register 0 (PER0)
340
CHAPTER 7 CLOCK GENERATOR
HIOSTOP
Clock operation status
control register
(CSC)
Serial array unit 0
Programmable gain
amplifier/comparator
HALT/STOP mode signal
oscillation (30 kHz (TYP.))
(Remark is listed on p.343 .)
Controller
20 MHz internal
high-speed oscillator
fMAIN
78K0R/Kx3-L
Internal bus
Clock operation status
control register
(CSC)
Clock operation mode
control register
(CMC)
AMPH EXCLK OSCSEL
Oscillation stabilization
time select register (OSTS)
System clock control
register (CKC)
CLS
OSTS2 OSTS1 OSTS0
MSTOP
CSS MCS MCM0
1
MD
IV2
MD
IV1
MD
IV0
Standby controller
3
STOP mode
4
X1 oscillation
stabilization time counter
STOP mode
signal
Option byte (000C1H)
FRQSEL2,
FRQSEL1
Crystal/ceramic
oscillation
fX
External input
clock
fEX
Oscillation stabilization
time counter status
register (OSTC)
fMX
Clock output/
buzzer outputNote
Internal high-speed
oscillator
Internal high-speed
oscillation (1 MHz (TYP.))
fMAIN/25
fIH1
fMAIN
fIH
Internal high-speed
oscillation (8 MHz (TYP.))
Main system clock
source selector
fIH8
fMAIN/24
fMAIN/23
fMAIN/22
CPU clock
and peripheral fCLK
hardware
clock source
selection
Selector
X2/EXCLK
/P122
Normal
operation mode
MOST MOST MOST MOST MOST MOST MOST MOST
8
9
10
11 13 15 17 18
High-speed system
clock oscillator
X1/P121
HALT mode
Prescaler
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Figure 7-2. Block Diagram of Clock Generator (78K0R/KC3-L (44-pin and 48-pin), 78K0R/KD3-L, 78K0R/KE3-L)
CPU
Timer array unit 0
fMAIN/2
Internal high-speed
oscillation (20 MHz (TYP.))
fIH20
fIH20
Option byte (000C0H)
WDTON
WDSTBYON
Internal low-speed
oscillator
fIL
Internal low-speed
fSUB/2
XT2//P124
Crystal
oscillation
HALT/STOP mode signal
Programmable gain
amplifier/comparator
Watchdog timer
fSUB
Real-time counter,
clock output/buzzer outputNote
fXT
CLS
AMPHS1AMPHS0 OSCSELS
Clock operation mode
control register
(CMC)
XTSTOP HIOSTOP
DSCS SELDSC DSCON
Clock operation status
control register
(CSC)
20 MHz internal high-speed
oscillation control register
(DSCCTL)
Internal bus
Note
This is not mounted onto 44-pin product of the 78K0R/KC3-L.
(Remark is listed on the next page after next.)
A/D converter
TAU0
EN
Peripheral enable
register 2 (PER2)
OACMP
EN
Peripheral enable
register 1 (PER1)
SAU0
EN
IICA
ENNote
ADC
EN
RTC
EN
Peripheral enable
register 0 (PER0)
341
CHAPTER 7 CLOCK GENERATOR
Subsystem clock
oscillator
Serial interface IICANote
Real-time counter
oscillation (30 kHz (TYP.))
XT1/P123
Serial array unit 0
Controller
20 MHz internal
high-speed oscillator
fMAIN
78K0R/Kx3-L
Internal bus
Clock operation mode
control register
(CMC)
Clock operation status
control register
(CSC)
AMPH EXCLK OSCSEL
System clock control
register (CKC)
Oscillation stabilization
time select register (OSTS)
CLS
OSTS2 OSTS1 OSTS0
MSTOP
CSS MCS MCM0
1
MD
IV2
MD
IV1
MD
IV0
Standby controller
3
STOP mode
4
X1 oscillation
stabilization time counter
STOP mode
signal
High-speed system
clock oscillator
Crystal/ceramic
oscillation
fX
External input
clock
fEX
Option byte (000C1H)
FRQSEL2,
FRQSEL1
Oscillation stabilization
time counter status
register (OSTC)
fMX
Clock output/
buzzer output
Internal high-speed
oscillator
Internal high-speed
oscillation (1 MHz (TYP.))
fMAIN/25
fIH1
fMAIN
fIH
Internal high-speed
oscillation (8 MHz (TYP.))
fIH8
20 MHz internal
high-speed oscillator
Internal high-speed
oscillation (20 MHz (TYP.))
fMAIN/24
Main system clock
source selector
fMAIN/23
fMAIN/22
XT2//P124
Crystal
oscillation
Timer array unit 1
fMAIN
fIH20
Option byte (000C0H)
WDTON
WDSTBYON
fIH20
Internal low-speed
oscillator
fIL
Internal low-speed
Serial array unit 0
fSUB/2
HALT/STOP mode signal
Watchdog timer
Serial array unit 1
Serial array unit 2Note
Serial interface IICA
A/D converter
Real-time counter
Real-time counter,
clock output/buzzer output
fSUB
fXT
CLS
AMPHS1 AMPHS0 OSCSELS
Clock operation mode
control register
(CMC)
XTSTOP HIOSTOP
Clock operation status
control register
(CSC)
DSCS SELDSC DSCON
SAU
2EN
20 MHz internal high-speed
oscillation control register
(DSCCTL)
Internal bus
Note
Timer array unit 0
Those are are only mounted in the μ PD78F1027, 78F1028, 78F1029, and 78F1030.
(Remark is listed on the next page.)
RTC
EN
Peripheral enable
register 1Note (PER1)
ADC
EN
IICA
EN
SAU1
EN
SAU0
EN
TAU1
EN
Peripheral enable
register 0 (PER0)
TAU0
EN
342
CHAPTER 7 CLOCK GENERATOR
XT1/P123
CPU
fMAIN/2
oscillation (30 kHz (TYP.))
Subsystem clock
oscillator
CPU clock
and peripheral fCLK
hardware
clock source
selection
Controller
X2/EXCLK
/P122
Normal
operation mode
Selector
X1/P121
HALT mode
MOST MOST MOST MOST MOST MOST MOST MOST
8
9
10
11 13 15 17 18
Prescaler
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Figure 7-3. Block Diagram of Clock Generator (78K0R/KF3-L, 78K0R/KG3-L)
78K0R/Kx3-L
Remark
CHAPTER 7 CLOCK GENERATOR
fX:
X1 clock oscillation frequency
fIH:
Internal high-speed oscillation clock frequency
fIH20: 20 MHz internal high-speed oscillation clock frequency
fEX:
External main system clock frequency
fMX:
High-speed system clock frequency
fMAIN: Main system clock frequency
fXT:
XT1 clock oscillation frequency
fSUB:
Subsystem clock frequency
fCLK:
CPU/peripheral hardware clock frequency
fIL:
Internal low-speed oscillation clock frequency
7.3 Registers Controlling Clock Generator
The following eight registers are used to control the clock generator.
• Clock operation mode control register (CMC)
• System clock control register (CKC)
• Clock operation status control register (CSC)
• Oscillation stabilization time counter status register (OSTC)
• Oscillation stabilization time select register (OSTS)
• 20 MHz internal high-speed oscillation control register (DSCCTL)
• Peripheral enable registers 0, 1, 2Note (PER0, PER1, PER2 Note)
• Operation speed mode control register (OSMC)
Note
The PER2 register is only mounted in the 78K0R/KC3-L, 78K0R/KD3-L, and 78K0R/KE3-L.
(1) Clock operation mode control register (CMC)
This register is used to set the operation mode of the X1/P121, X2/EXCLK/P122, XT1/P123, and XT2/P124 Note pins,
and to select a gain of the oscillator.
The CMC register can be written only once by an 8-bit memory manipulation instruction after reset release. This
register can be read by a 1-bit or 8-bit memory manipulation instruction.
Reset signal generation clears this register to 00H.
Note
The 78K0R/KC3-L (40-pin) doesn’t have the XT1 and XT2 oscillator.
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Figure 7-4. Format of Clock Operation Mode Control Register (CMC)
Address: FFFA0H
After reset: 00H
R/W
Symbol
7
6
5
4
3
2
1
0
CMC
EXCLK
OSCSEL
0
OSCSELS
0
AMPHS1
AMPHS0
AMPH
Note
EXCLK
OSCSEL
0
0
Input port mode
Input port
0
1
X1 oscillation mode
Crystal/ceramic resonator connection
1
0
Input port mode
Input port
1
External clock input mode
Input port
1
OSCSELS
High-speed system clock
pin operation mode
Subsystem clock pin operation mode
X1/P121 pin
X2/EXCLK/P122 pin
External clock input
XT1/P123 pin
XT2/P124 pin
Note
0
Input port mode
Input port
1
XT1 oscillation mode
Crystal resonator connection
AMPHS1
AMPHS0
0
0
Low power consumption oscillation (default)
XT1 oscillator oscillation mode selection
0
1
Normal oscillation
1
0
Ultra-low power consumption oscillation
1
1
AMPH
Control of X1 clock oscillation frequency
0
2 MHz ≤ fX ≤ 10 MHz
1
10 MHz < fX ≤ 20 MHz
Note
OSCSELS bit is not provided in the 78K0R/KC3-L (40-pin). In the 78K0R/KC3-L (40-pin), bit 4 is
fixed to 0.
Cautions 1. The CMC register can be written only once after reset release, by an 8-bit memory
manipulation instruction.
2. After reset release, set the CMC register before X1 or XT1 oscillation is started as set
by the clock operation status control register (CSC).
3. Be sure to set the AMPH bit to 1 if the X1 clock oscillation frequency exceeds 10 MHz.
4. When the CMC register is used at the default value (00H), be sure to set 00H to this
register after reset release in order to prevent malfunctioning during a program loop.
5. The XT1 oscillator is a circuit with low amplification in order to achieve low-power
consumption. Note the following points when designing the circuit.
• Pins and circuit boards include parasitic capacitance. Therefore, perform
oscillation evaluation using a circuit board to be actually used and confirm that
there are no problems.
• When using the ultra-low power consumption oscillation (AMPHS1 = 1) as the
mode of the XT1 oscillator, use the recommended resonators described in
CHAPTER 30 ELECTRICAL SPECIFICATIONS (78K0R/KC3-L, 78K0R/KD3-L,
78K0R/KE3-L) or CHAPTER 31 ELECTRICAL SPECIFICATIONS (78K0R/KF3-L,
78K0R/KG3-L).
(Cautions and Remark are given on the next page.)
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• Make the wiring between the XT1 and XT2 pins and the resonators as short as
possible, and minimize the parasitic capacitance and wiring resistance. Note this
particularly when the ultra-low power consumption oscillation (AMPHS1 = 1) is
selected.
• Configure the circuit of the circuit board, using material with little wiring
resistance.
• Place a ground pattern that has the same potential as VSS as much as possible
near the XT1 oscillator.
• Be sure that the signal lines between the XT1 and XT2 pins, and the resonators
do not cross with the other signal lines. Do not route the wiring near a signal
line through which a high fluctuating current flows.
• The impedance between the XT1 and XT2 pins may drop and oscillation may be
disturbed due to moisture absorption of the circuit board in a high-humidity
environment or dew condensation on the board. When using the circuit board in
such an environment, take measures to damp-proof the circuit board, such as by
coating.
• When coating the circuit board, use material that does not cause capacitance or
leakage between the XT1 and XT2 pins.
Remark fX: X1 clock frequency
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(2) System clock control register (CKC)
This register is used to select a CPU/peripheral hardware clock and a division ratio.
The CKC register can be set by a 1-bit or 8-bit memory manipulation instruction.
Reset signal generation sets this register to 09H.
Figure 7-5. Format of System Clock Control Register (CKC)
Address: FFFA4H
Symbol
CKC
After reset: 09H
<7>
CLS
CLS
Note 2
R/W
Note 1
<6>
<5>
<4>
3
2
1
0
CSS
MCS
MCM0
1
MDIV2
MDIV1
MDIV0
Note 2
Status of CPU/peripheral hardware clock (fCLK)
0
Main system clock (fMAIN)
1
Subsystem clock divided by 2 (fSUB/2)
MCS
Status of Main system clock (fMAIN)
Internal high-speed oscillation clock (fIH) or 20 MHz internal high-speed oscillation clock
0
(fIH20)
1
High-speed system clock (fMX)
MCM0
Main system clock (fMAIN) operation control
Selects the internal high-speed oscillation clock (fIH) or 20 MHz internal high-speed
0
oscillation clock (fIH20) as the main system clock (fMAIN)
1
Selects the high-speed system clock (fMX) as the main system clock (fMAIN)
CSS
MDIV2
MDIV1
Selection of CPU/peripheral
MDIV0
hardware clock (fCLK)
0
1
Note 5
0
0
0
fMAIN
0
0
1
fMAIN/2 (This is the default setting if MCM0 = 0.)
0
1
0
fMAIN/2
2
0
1
1
fMAIN/2
3 Note 3
1
0
0
fMAIN/2
4 Note 3
1
0
1
fMAIN/2
5 Notes 3, 4
×
×
×
fSUB/2
Other than above
Setting prohibited
Notes 1. Bits 7 and 5 are read-only.
2. CLS bit is not provided in the 78K0R/KC3-L (40-pin). In the 78K0R/KC3-L (40-pin), bit 7 is fixed
to 0.
3. Setting is prohibited if the 1 MHz Internal high-speed oscillation clock frequency (fIH1) is
selected as the main system clock (fMAIN).
4. Setting is prohibited if the high-speed system clock (fMX) is selected as the main system clock
(fMAIN) and if fMX < 4 MHz.
5. Changing the value of the MCM0 bit is prohibited while the CSS bit is set to 1.
(Remarks and Cautions are listed on the next page.)
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Remarks 1. fIH:
Internal high-speed oscillation clock frequency
fIH20: 20 MHz Internal high-speed oscillation clock frequency
fIH1: 1 MHz Internal high-speed oscillation clock frequency
fMX: High-speed system clock frequency
fSUB: Subsystem clock frequency
2. ×:
don’t care
Cautions 1. Be sure to set bit 3 to 1.
2. The clock set by the CSS, MCM0, and MDIV2 bits to MDIV0 is supplied to the CPU
and peripheral hardware. If the CPU clock is changed, therefore, the clock supplied
to peripheral hardware (except the real-time counter, clock output/buzzer output, and
watchdog timer) is also changed at the same time.
Consequently, stop each
peripheral function when changing the CPU/peripheral hardware clock.
3. If the subsystem clock is used as the peripheral hardware clock, the operations of
the A/D converter and IICA are not guaranteed. For the operating characteristics of
the peripheral hardware, refer to the chapters describing the various peripheral
hardware as well as CHAPTER 30 ELECTRICAL SPECIFICATIONS (78K0R/KC3-L,
78K0R/KD3-L, 78K0R/KE3-L) or CHAPTER 31 ELECTRICAL SPECIFICATIONS
(78K0R/KF3-L, 78K0R/KG3-L).
The fastest instruction can be executed in 1 clock of the CPU clock in the 78K0R/Kx3-L. Therefore, the relationship
between the CPU clock (fCLK) and the minimum instruction execution time is as shown in Table 7-2.
Table 7-2. Relationship Between CPU Clock and Minimum Instruction Execution Time
CPU Clock
Minimum Instruction Execution Time: 1/fCLK
(Value set by the
MDIV2 to MDIV0
bits)
Subsystem Clock
Main System Clock (CSS = 0)
High-Speed System Clock
Internal High-Speed Oscillation
(MCM0 = 1)
Clock (MCM0 = 0)
At 10 MHz
At 20 MHz
At 8 MHz (TYP.)
At 20 MHz (TYP.)
Operation
Operation
Operation
Operation
Note
(CSS = 1)
At 32.768 kHz Operation
fMAIN
0.1 μs
0.05 μs
0.125 μs (TYP.)
0.05 μs (TYP.)
−
fMAIN/2
0.2 μs
0.1 μs
0.25 μs (TYP.)
0.1 μs (TYP.)
−
(default)
fMAIN/2
2
0.4 μs
0.2 μs
0.5 μs (TYP.)
0.2 μs (TYP.)
−
fMAIN/2
3
0.8 μs
0.4 μs
1.0 μs (TYP.)
0.4 μs (TYP.)
−
fMAIN/2
4
1.6 μs
0.8 μs
2.0 μs (TYP.)
0.8 μs (TYP.)
−
fMAIN/2
5
3.2 μs
1.6 μs
4.0 μs (TYP.)
1.6 μs (TYP.)
−
−
fSUB/2
Note
−
61 μs
The 78K0R/KC3-L (40-pin) doesn’t have the subsystem clock.
Remark
fMAIN: Main system clock frequency (fIH ,fIH20, or fMX)
fSUB:
Subsystem clock frequency
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(3) Clock operation status control register (CSC)
This register is used to control the operations of the high-speed system clock, internal high-speed oscillation clock,
and subsystem clockNote (except the 20 MHz internal high-speed oscillation clock and internal low-speed oscillation
clock).
The CSC register can be set by a 1-bit or 8-bit memory manipulation instruction.
Reset signal generation sets this register to C0H.
Note
The 78K0R/KC3-L (40-pin) doesn’t have the subsystem clock.
Figure 7-5. Format of Clock Operation Status Control Register (CSC)
Address: FFFA1H
Symbol
CSC
After reset: C0H
<7>
<6>
MSTOP
XTSTOP
Note 1
R/W
5
4
3
2
1
<0>
0
0
0
0
0
HIOSTOP
MSTOP
High-speed system clock operation control
X1 oscillation mode
External clock input mode
0
X1 oscillator operating
External clock from EXCLK
pin is valid
1
X1 oscillator stopped
External clock from EXCLK
pin is invalid
Note 1
XTSTOP
0
XT1 oscillator operating
1
XT1 oscillator stopped
Input port mode
Input port
Internal high-speed oscillation clock operation control
0
Internal high-speed oscillator operating
1
Internal high-speed oscillator stopped
Notes 1.
2.
Input port
Subsystem clock operation control
XT1 oscillation mode
HIOSTOP
Input port mode
Note 2
XTSTOP bit is not provided in the 78K0R/KC3-L (40-pin). In the 78K0R/KC3-L (40-pin), bit 6 is
fixed to 0.
The 1 MHz or 8 MHz (TYP.) internal high-speed oscillation clock stops. Stopping the internal
high-speed oscillator (HIOSTOP = 1) is prohibited while the 20 MHz internal high-speed
oscillation clock is operating (DSCON = 1). Stop the 20 MHz internal high-speed oscillation
clock by using the 20 MHz internal high-speed oscillation control register (DSCCTL) and not
the HIOSTOP bit.
Cautions 1. After reset release, set the clock operation mode control register (CMC) before
setting the CSC register.
2. To start X1 oscillation as set by the MSTOP bit, check the oscillation stabilization
time of the X1 clock by using the oscillation stabilization time counter status register
(OSTC).
3. When starting XT1 oscillation by setting the XSTOP bit, wait for oscillation of the
subsystem clock to stabilize by setting a wait time using software.
4. Do not stop the clock selected for the CPU peripheral hardware clock (fCLK) with the
OSC register.
5. The setting of the flags of the register to stop clock oscillation (invalidate the external
clock input) and the condition before clock oscillation is to be stopped are as Table
7-3.
6. Set the oscillation stabilization time select register (OSTS) before setting the MSTOP
bit to 0 after releasing reset. Note that if the OSTS register is being used with its
default settings, the OSTS register is not required to be set here.
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Table 7-3. Condition Before Stopping Clock Oscillation and Flag Setting
Clock
Condition Before Stopping Clock
(Invalidating External Clock Input)
X1 clock
External main system
clock
Subsystem clock
Note
CPU and peripheral hardware clocks operate with a clock
other than the high-speed system clock.
Setting of CSC
Register Flags
MSTOP = 1
(CLS = 0 and MCS = 0, or CLS = 1)
CPU and peripheral hardware clocks operate with a clock
other than the subsystem clock.
XTSTOP = 1
(CLS = 0)
Internal high-speed
oscillation clock
CPU and peripheral hardware clocks operate with a clock
other than the internal high-speed oscillator clock and 20
MHz internal high-speed oscillation clock.
HIOSTOP = 1
(CLS = 0 and MCS = 1, or CLS = 1)
Note The 78K0R/KC3-L (40-pin) doesn’t have the subsystem clock.
(4) Oscillation stabilization time counter status register (OSTC)
This is the register that indicates the count status of the X1 clock oscillation stabilization time counter.
The X1 clock oscillation stabilization time can be checked in the following case,
• If the X1 clock starts oscillation while the internal high-speed oscillation clock or subsystem clock is being used
as the CPU clock.
• If the STOP mode is entered and then released while the internal high-speed oscillation clock is being used as
the CPU clock with the X1 clock oscillating.
The OSTC register can be read by a 1-bit or 8-bit memory manipulation instruction.
When reset signal is generated, the STOP instruction and MSTOP (bit 7 of clock operation status control register
(CSC)) = 1 clear the OSTC register to 00H.
Remark The oscillation stabilization time counter starts counting in the following cases.
• When oscillation of the X1 clock starts (EXCLK, OSCSEL = 0, 1 → MSTOP = 0)
• When the STOP mode is released
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Figure 7-7. Format of Oscillation Stabilization Time Counter Status Register (OSTC)
Address: FFFA2H
Symbol
OSTC
After reset: 00H
7
6
5
R
4
3
2
1
0
MOST MOST MOST MOST MOST MOST MOST MOST
8
9
10
11
13
15
17
18
MOST MOST MOST MOST MOST MOST MOST MOST
8
9
10
11
13
15
17
18
Oscillation stabilization time status
fX = 10 MHz
fX = 20 MHz
8
25.6 μs max. 12.8 μs max.
8
25.6 μs min.
12.8 μs min.
9
51.2 μs min.
25.6 μs min.
10
102.4 μs min. 51.2 μs min.
11
204.8 μs min. 102.4 μs min.
0
0
0
0
0
0
0
0
2 /fX max.
1
0
0
0
0
0
0
0
2 /fX min.
1
1
0
0
0
0
0
0
2 /fX min.
1
1
1
0
0
0
0
0
2 /fX min.
1
1
1
1
0
0
0
0
2 /fX min.
13
819.2 μs min. 409.6 μs min.
15
3.27 ms min. 1.64 ms min.
17
13.11 ms min. 6.55 ms min.
18
26.21 ms min. 13.11 ms min.
1
1
1
1
1
0
0
0
2 /fX min.
1
1
1
1
1
1
0
0
2 /fX min.
1
1
1
1
1
1
1
0
2 /fX min.
1
1
1
1
1
1
1
1
2 /fX min.
Cautions 1. After the above time has elapsed, the bits are set to 1 in order from the MOST8 bit
and remain 1.
2. The oscillation stabilization time counter counts up to the oscillation stabilization
time set by the oscillation stabilization time select register (OSTS).
In the following cases, set the oscillation stabilization time of the OSTS register to
the value greater than the count value which is to be checked by the OSTC register
after the oscillation starts.
• If the X1 clock starts oscillation while the internal high-speed oscillation clock or
subsystem clock is being used as the CPU clock.
• If the STOP mode is entered and then released while the internal high-speed
oscillation clock is being used as the CPU clock with the X1 clock oscillating.
(Note, therefore, that only the status up to the oscillation stabilization time set by
the OSTS register is set to the OSTC register after the STOP mode is released.)
3. The X1 clock oscillation stabilization wait time does not include the time until clock
oscillation starts (“a” below).
STOP mode release
X1 pin voltage
waveform
a
Remark
fX: X1 clock oscillation frequency
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(5) Oscillation stabilization time select register (OSTS)
This register is used to select the X1 clock oscillation stabilization wait time when the STOP mode is released.
When the X1 clock is selected as the CPU clock, the operation automatically waits for the time set using the OSTS
register after the STOP mode is released.
When the internal high-speed oscillation clock is selected as the CPU clock, confirm with the oscillation stabilization
time counter status register (OSTC) that the desired oscillation stabilization time has elapsed after the STOP mode is
released. The oscillation stabilization time can be checked up to the time set using the OSTC register.
The OSTS register can be set by an 8-bit memory manipulation instruction.
Reset signal generation sets the OSTS register to 07H.
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Figure 7-8. Format of Oscillation Stabilization Time Select Register (OSTS)
Address: FFFA3H
After reset: 07H
R/W
Symbol
7
6
5
4
3
2
1
0
OSTS
0
0
0
0
0
OSTS2
OSTS1
OSTS0
OSTS2
OSTS1
OSTS0
Oscillation stabilization time selection
fX = 10 MHz
25.6 μs
Setting prohibited
9
51.2 μs
25.6 μs
10
102.4 μs
51.2 μs
11
204.8 μs
102.4 μs
0
0
0
2 /fX
0
0
1
2 /fX
0
1
0
2 /fX
0
1
1
2 /fX
13
819.2 μs
409.6 μs
15
3.27 ms
1.64 ms
17
13.11 ms
6.55 ms
18
26.21 ms
13.11 ms
1
0
0
2 /fX
1
0
1
2 /fX
1
1
0
2 /fX
1
1
1
fX = 20 MHz
8
2 /fX
Cautions 1. To set the STOP mode when the X1 clock is used as the CPU clock, set the OSTS
register before executing the STOP instruction.
2. Setting the oscillation stabilization time to 20 μs or less is prohibited.
3. Change the setting of the OSTS register before setting the MSTOP bit of the clock
operation status control register (CSC) to 0.
4. Do not change the value of the OSTS register during the X1 clock oscillation
stabilization time.
5. The oscillation stabilization time counter counts up to the oscillation stabilization
time set by the OSTS register.
In the following cases, set the oscillation stabilization time of the OSTS register to
the value greater than the count value which is to be checked by the OSTC register
after the oscillation starts.
• If the X1 clock starts oscillation while the internal high-speed oscillation clock or
subsystem clock is being used as the CPU clock.
• If the STOP mode is entered and then released while the internal high-speed
oscillation clock is being used as the CPU clock with the X1 clock oscillating.
(Note, therefore, that only the status up to the oscillation stabilization time set by
the OSTS register is set to the OSTC register after the STOP mode is released.)
6. The X1 clock oscillation stabilization wait time does not include the time until clock
oscillation starts (“a” below).
STOP mode release
X1 pin voltage
waveform
a
Remark fX: X1 clock oscillation frequency
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(6) 20 MHz internal high-speed oscillation control register (DSCCTL)
This register controls the 20 MHz internal high-speed oscillation clock (DSC) function.
This register can be used to control oscillation of the 20 MHz internal high-speed oscillation clock (fIH20) and select the
20 MHz internal high-speed oscillation clock (fIH20) as the CPU/peripheral hardware clock.
The DSCCTL register can be set by a 1-bit or 8-bit memory manipulation instruction.
Reset signal generation clears this register to 00H.
Figure 7-9. Format of 20 MHz Internal High-Speed Oscillation Control Register (DSCCTL)
Address: F00F6H
After reset: 00H
R/W
Note
Symbol
7
6
5
4
<3>
<2>
1
<0>
DSCCTL
0
0
0
0
DSCS
SELDSC
0
DSCON
DSCS
0
1
20 MHz internal high-speed oscillation supply status flag
Not supplied
Supplied (The CPU/peripheral hardware clock (fCLK) operates on the 20 MHz internal highspeed oscillation clock.)
SELDSC
0
Selection of 20 MHz internal high-speed oscillation for CPU/peripheral hardware clock (fCLK)
Does not select 20 MHz internal high-speed oscillation (clock selected by the system clock
control register (CKC) is supplied to fCLK)
1
Selects 20 MHz internal high-speed oscillation (20 MHz internal high-speed oscillation is
supplied to fCLK)
DSCON
Operating or stopping 20 MHz internal high-speed oscillation clock (fIH20)
0
Stopped
1
Operated
Note Bit 3 is read-only.
Cautions 1. 20 MHz internal oscillation can only be used if VDD ≥ 2.7 V.
2. Set the SELDSC bit when 100 μ s have elapsed after the DSCON bit has been set with VDD ≥ 2.7 V.
3. The internal high-speed oscillator must be operated (HIOSTOP = 0) when DSCON = 1.
4. If 1 MHz internal oscillation is selected by using the option byte, 20 MHz internal high-speed
oscillation cannot be used. Do not set (1) the DSCON bit.
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(7) Peripheral enable registers 0, 1, 2 (PER0, PER1, PER2)
These registers are used to enable or disable supplying the clock to the peripheral hardware. Clock supply to the
hardware that is not used is also stopped so as to decrease the power consumption and noise.
The 78K0R/KC3-L, 78K0R/KD3-L, and 78K0R/KE3-L include the PER0, PER1, and PER2 registers.
The
78K0R/KF3-L and 78K0R/KG3-L, however, only include the PER0 and PER1Note 1 registers. Note also that the bits
incorporated in the PER0 register differ depending on the product.
To use the peripheral functions below, which are controlled by this register, set (1) the bit corresponding to each
function before specifying the initial settings of the peripheral functions.
• Real-time counterNote 2
• A/D converter
• Serial interface IICANote 3
• Serial array unit 0
• Serial array unit 1 Note 4
• Serial array unit 2 Note 1
• Timer array unit 0
• Timer array unit 1 Note 4
• Comparators/programmable gain amplifiers Note 5
The PER0, PER1, and PER2 registers can be set by a 1-bit or 8-bit memory manipulation instruction.
Reset signal generation clears these registers to 00H.
Notes 1.
2.
3.
4.
5.
PER1 register is only mounted in the μ PD78F1027 to 78F1030.
This is not mounted onto 40-pin product of the 78K0R/KC3-L.
This is not mounted onto 44-pin and 48-pin products of the 78K0R/KC3-L.
78K0R/KF3-L, 78K0R/KG3-L only.
78K0R/KC3-L, 78K0R/KD3-L, 78K0R/KE3-L only.
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Figure 7-10. Format of Peripheral Enable Registers 0, 1, 2 (PER0, PER1, PER2)
(78K0R/KC3-L, 78K0R/KD3-L, 78K0R/KE3-L) (1/2)
Address: F00F0H
Symbol
PER0
After reset: 00H
<7>
6
Note 1
RTCEN
Address: F00F1H
0
After reset: 00H
R/W
<5>
<4>
ADCEN
IICAEN
Note 2
3
<2>
1
0
0
SAU0EN
0
0
R/W
Symbol
7
6
5
4
<3>
2
1
0
PER1
0
0
0
0
OACMPEN
0
0
0
Address: F00F2H
After reset: 00H
R/W
Symbol
7
6
5
4
3
2
1
<0>
PER2
0
0
0
0
0
0
0
TAU0EN
Bit 7
(PER0)
RTCEN
Note 1
Control of real-time counter (RTC) input clock supply
Note 3
Stops input clock supply.
0
• SFR used by the real-time counter (RTC) cannot be written.
• The real-time counter (RTC) is in the reset status.
Enables input clock supply.
1
• SFR used by the real-time counter (RTC) can be read and written.
Bit 5
ADCEN
(PER0)
0
Control of A/D converter input clock supply
Stops input clock supply.
• SFR used by the A/D converter cannot be written.
• The A/D converter is in the reset status.
Enables input clock supply.
1
• SFR used by the A/D converter can be read and written.
Bit 4
(PER0)
IICAEN
Note 2
Control of serial interface IICA input clock supply
Stops input clock supply.
0
• SFR used by the serial interface IICA cannot be written.
• The serial interface IICA is in the reset status.
Enables input clock supply.
1
• SFR used by the serial interface IICA can be read and written.
Notes 1. This is not mounted onto 40-pin product of the 78K0R/KC3-L.
2. This is not mounted onto 40-pin and 44-pin products of the 78K0R/KC3-L.
3. The input clock that can be controlled by the RTCEN bit is used when the register that is used
by the real-time counter (RTC) is accessed from the CPU. The RTCEN bit cannot control
supply of the operating clock (fSUB) to RTC.
Caution Be sure to clear bits 0, 1, 3, and 6 (40-pin product of the 78K0R/KC3-L: bits 0, 1, 3, 4, 6,
and 7, 44-pin product of the 78K0R/KC3-L: bits 0, 1, 3, 4, and 6) of the PER0 register, bits
0 to 2 and 4 to 7 of the PER1 register, and bits 1 to 7 of the PER2 register to 0.
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Figure 7-10. Format of Peripheral Enable Registers 0, 1, 2 (PER0, PER1, PER2)
(78K0R/KC3-L, 78K0R/KD3-L, 78K0R/KE3-L) (2/2)
Address: F00F0H
Symbol
PER0
After reset: 00H
<7>
RTCEN
Address: F00F1H
6
Note 1
R/W
<5>
0
<4>
ADCEN
After reset: 00H
IICAEN
Note 2
3
<2>
1
0
0
SAU0EN
0
0
R/W
Symbol
7
6
5
4
<3>
2
1
0
PER1
0
0
0
0
OACMPEN
0
0
0
Address: F00F2H
After reset: 00H
R/W
Symbol
7
6
5
4
3
2
1
<0>
PER2
0
0
0
0
0
0
0
TAU0EN
Bit 2
SAU0EN
(PER0)
0
Control of serial array unit 0 input clock supply
Stops input clock supply.
• SFR used by the serial array unit 0 cannot be written.
• The serial array unit 0 is in the reset status.
Enables input clock supply.
1
• SFR used by the serial array unit 0 can be read and written.
Bit 3
OACMPEN
(PER1)
0
Control of comparator and programmable gain amplifier input clock supply
Stops input clock supply.
• SFR used by the comparator and programmable gain amplifier cannot be written.
• The comparator and programmable gain amplifier is in the reset status.
Enables input clock supply.
1
• SFR used by the comparator and programmable gain amplifier can be read and written.
Bit 0
TAU0EN
(PER2)
0
Control of timer array unit 0 input clock supply
Stops input clock supply.
• SFR used by timer array unit 0 cannot be written.
• Timer array unit 0 is in the reset status.
Enables input clock supply.
1
• SFR used by timer array unit 0 can be read and written.
Notes 1. This is not mounted onto 40-pin product of the 78K0R/KC3-L.
2. This is not mounted onto 40-pin and 44-pin products of the 78K0R/KC3-L.
Caution Be sure to clear bits 0, 1, 3, and 6 (40-pin product of the 78K0R/KC3-L: bits 0, 1, 3, 4, 6,
and 7, 44-pin product of the 78K0R/KC3-L: bits 0, 1, 3, 4, and 6) of the PER0 register, bits
0 to 2 and 4 to 7 of the PER1 register, and bits 1 to 7 of the PER2 register to 0.
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Figure 7-11. Format of Peripheral Enable Registers 0 and 1 (PER0, PER1) (78K0R/KF3-L, 78K0R/KG3-L) (1/2)
Address: F00F0H
After reset: 00H
R/W
Symbol
<7>
6
<5>
<4>
<3>
<2>
<1>
<0>
PER0
RTCEN
0
ADCEN
IICAEN
SAU1EN
SAU0EN
TAU1EN
TAU0EN
4
3
2
<1>
0
Address: F00F1H
Symbol
PER1
After reset: 00H
7
Note 1
6
0
0
RTCEN
R/W
5
0
0
0
0
Note 1
SAU2EN
Control of real-time counter (RTC) input clock supply
0
Note 2
Stops input clock supply.
0
• SFR used by the real-time counter (RTC) cannot be written.
• The real-time counter (RTC) is in the reset status.
Supplies input clock.
1
• SFR used by the real-time counter (RTC) can be read and written.
ADCEN
Control of A/D converter input clock supply
Stops input clock supply.
0
• SFR used by the A/D converter cannot be written.
• The A/D converter is in the reset status.
Supplies input clock.
1
• SFR used by the A/D converter can be read and written.
IICAEN
Control of serial interface IICA input clock supply
Stops input clock supply.
0
• SFR used by the serial interface IICA cannot be written.
• The serial interface IICA is in the reset status.
Supplies input clock.
1
• SFR used by the serial interface IICA can be read and written.
Note 1
SAU1EN
Control of serial array unit 1 input clock supply
Stops input clock supply.
0
• SFR used by the serial array unit 1 cannot be written.
• The serial array unit 1 is in the reset status.
Supplies input clock.
1
• SFR used by the serial array unit 1 can be read and written.
Notes 1. PER1 register and SAU2EN bit are only mounted in the μ PD78F1027, 78F1028, 78F1029,
and 78F1030.
2. The input clock that can be controlled by the RTCEN bit is used when the register that is used
by the real-time counter (RTC) is accessed from the CPU. The RTCEN bit cannot control
supply of the operating clock (fSUB) to RTC.
Caution Be sure to clear bit 6 of the PER0 register and bits 0, and 2 to 7 of the PER1 register to 0.
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Figure 7-11. Format of Peripheral Enable Registers 0 and 1 (PER0, PER1) (78K0R/KF3-L, 78K0R/KG3-L) (2/2)
Address: F00F0H
After reset: 00H
R/W
Symbol
<7>
6
<5>
<4>
<3>
<2>
<1>
<0>
PER0
RTCEN
0
ADCEN
IICAEN
SAU1EN
SAU0EN
TAU1EN
TAU0EN
4
3
2
<1>
0
Address: F00F1H
Symbol
PER1
After reset: 00H
7
Note
6
0
0
R/W
5
0
SAU0EN
0
0
0
Note
SAU2EN
0
Control of serial array unit 0 input clock supply
Stops input clock supply.
0
• SFR used by the serial array unit 0 cannot be written.
• The serial array unit 0 is in the reset status.
Supplies input clock.
1
• SFR used by the serial array unit 0 can be read and written.
TAU1EN
Control of timer array unit 1 input clock supply
Stops input clock supply.
0
• SFR used by timer array unit 1 cannot be written.
• Timer array unit 1 is in the reset status.
Supplies input clock.
1
• SFR used by timer array unit 1 can be read and written.
TAU0EN
Control of timer array unit 0 input clock supply
Stops input clock supply.
0
• SFR used by timer array unit 0 cannot be written.
• Timer array unit 0 is in the reset status.
Supplies input clock.
1
• SFR used by timer array unit 0 can be read and written.
Note
SAU2EN
0
Control of serial array unit 2 input clock supply
Stops input clock supply.
• SFR used by the serial array unit 2 cannot be written.
• The serial array unit 2 is in the reset status.
1
Supplies input clock.
• SFR used by the serial array unit 2 can be read and written.
Note
PER1 register is only mounted in the μ PD78F1027, 78F1028, 78F1029, and 78F1030.
Caution Be sure to clear bit 6 of the PER0 register and bits 0, and 2 to 7 of the PER1 register to 0.
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(8) Operation speed mode control register (OSMC)
This register is used to reduce power consumption by stopping as many unnecessary clock functions as possible.
The FLPC and FSEL bits can be used to control the step-up circuit of the flash memory for high-speed operation.
If the microcontroller operates on a system clock of 10 MHz or more, set this register to 01B.
If the microcontroller operates at low speed on a system clock of 10 MHz or less, power consumption can be reduced,
because the voltage booster can be stopped by setting this register to its initial value, 00B. Furthermore, when CPU
operates with the system clock of 1 MHz, the power consumption can be further reduced by setting the FLPC bit to 1.
If the RTCLPC bit is set to 1 and real-time counter is operating, current consumption can be reduced, because the
circuit that synchronizes the clock to the peripheral functions, except the real-time counterNote 1, is stopped in STOP
mode and in HALT mode while subsystem clockNote 2 is selected as CPU clock.
The OSMC register can be set by an 8-bit memory manipulation instruction.
Reset signal generation clears this register to 00H.
Notes 1. 40-pin product of the 78K0R/KC3-L does not have real-time counter.
2. 40-pin product of the 78K0R/KC3-L does not have subsystem clock.
Figure 7-12. Format of Operation Speed Mode Control Register (OSMC)
Address: F00F3H
After reset: 00H
R/W
Symbol
7
6
5
4
3
2
1
0
OSMC
RTCLPC
0
0
0
0
0
FLPC
FSEL
FLPC
FSEL
0
0
Operates at a frequency of 10 MHz or less (default).
0
1
Operates at a frequency higher than 10 MHz.
1
0
Operates at a frequency of 1 MHz.
1
1
Setting prohibited
Note
RTCLPC
0
fCLK frequency selection
Setting in STOP mode and in HALT mode while subsystem clock is selected as CPU clock
Enables supply of subsystem clock to peripheral functions
(See Table 20-1 for peripheral functions whose operations are enabled.)
1
Note
Stops supply of subsystem clock to peripheral functions other than real-time counter
40-pin product of the 78K0R/KC3-L does not have RTCLPC bit. Be sure to clear RTCLPC bit to 0.
Cautions 1. Write “1” to the FSEL bit before the following two operations.
• Changing the clock prior to dividing fCLK to a clock other than fIH.
• Operating the DMA controller.
2. The CPU waits (140.5 clock (fCLK)) when “1” is written to the FSEL bit.
Interrupt requests issued during a wait will be suspended.
However, counting the oscillation stabilization time of fX can continue even while the
CPU is waiting.
3. To increase fCLK to 10 MHz or higher, set the FSEL bit to “1”, then change fCLK after
three or more clocks have elapsed.
4. To set the FSEL bit to 0, set fCLK to 10 MHz or less in advance.
5. Set FSEL = 0 to shift to STOP mode while VDD ≤ 2.7 V.
(Cautions are given on the next page.)
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6. The HALT mode current when STOP mode and when the subsystem clock is used
can be reduced by setting the RTCLPC bit to 1. However, no clock can be supplied
to the peripheral functions other than the real-time counter during HALT mode while
subsystem clock is selected as CPU clock. Set bit 7 (RTCEN) of peripheral enable
registers 0 (PER0), to 1, and all of bits 0 to 6 of the PER0 register, bits 0 to 7 of
peripheral enable register 1 (PER1), and bits 0 to 7 of peripheral enable register 2
(PER2) to 0 before setting subsystem clock HALT mode.
7. If the FLPC bit is set to a frequency of 1 MHz or less and then set (1), it cannot be
cleared (0) or set to a frequency of more than 1 MHz.
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7.4 System Clock Oscillator
7.4.1 X1 oscillator
The X1 oscillator oscillates with a crystal resonator or ceramic resonator (2 to 20 MHz) connected to the X1 and X2
pins.
An external clock can also be input. In this case, input the clock signal to the EXCLK pin.
To use the X1 oscillator, set bits 7 and 6 (EXCLK, OSCSEL) of the clock operation mode control register (CMC) as
follows.
• Crystal or ceramic oscillation: EXCLK, OSCSEL = 0, 1
• External clock input:
EXCLK, OSCSEL = 1, 1
When the X1 oscillator is not used, set the input port mode (EXCLK, OSCSEL = 0, 0).
When the pins are not used as input port pins, either, see Table 2-3 Connection of Unused Pins (78K0R/KC3-L,
78K0R/KD3-L, 78K0R/KE3-L) or Table 3-3 Connection of Unused Pins (78K0R/KF3-L, 78K0R/KG3-L).
Figure 7-13 shows an example of the external circuit of the X1 oscillator.
Figure 7-13. Example of External Circuit of X1 Oscillator
(a) Crystal or ceramic oscillation
(b) External clock
VSS
X1
X2
External clock
EXCLK
Crystal resonator
or
ceramic resonator
Cautions are listed on the next page.
7.4.2 XT1 oscillator (products other than 78K0R/KC3-L (40-pin))
The XT1 oscillator oscillates with a crystal resonator (standard: 32.768 kHz) connected to the XT1 and XT2 pins.
To use the XT1 oscillator, set bit 4 (OSCSELS) of the clock operation mode control register (CMC) to 1.
When the XT1 oscillator is not used, set the input port mode (OSCSELS = 0).
When the pins are not used as input port pins, either, see Table 2-3 Connection of Unused Pins (78K0R/KC3-L,
78K0R/KD3-L, 78K0R/KE3-L) or Table 3-3 Connection of Unused Pins (78K0R/KF3-L, 78K0R/KG3-L).
Figure 7-14 shows an example of the external circuit of the XT1 oscillator.
Figure 7-14. Example of External Circuit of XT1 Oscillator (Crystal Oscillation)
VSS
XT1
32.768
kHz
XT2
(Cautions are listed on the next page.)
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Caution 1. When using the X1 oscillator and XT1 oscillator, wire as follows in the area enclosed by the
broken lines in the Figures 7-13 and 7-14 to avoid an adverse effect from wiring capacitance.
• Keep the wiring length as short as possible.
• Do not cross the wiring with the other signal lines. Do not route the wiring near a signal line
through which a high fluctuating current flows.
• Always make the ground point of the oscillator capacitor the same potential as VSS. Do not
ground the capacitor to a ground pattern through which a high current flows.
• Do not fetch signals from the oscillator.
The XT1 oscillator is a circuit with low amplification in order to achieve low-power consumption.
Note the following points when designing the circuit.
• Pins and circuit boards include parasitic capacitance. Therefore, perform oscillation evaluation
using a circuit board to be actually used and confirm that there are no problems.
• When using the ultra-low power consumption oscillation (AMPHS1 = 1) as the mode of the XT1
oscillator, use the recommended resonators described in CHAPTER 30 ELECTRICAL
SPECIFICATIONS (78K0R/KC3-L, 78K0R/KD3-L, 78K0R/KE3-L) or CHAPTER 31 ELECTRICAL
SPECIFICATIONS (78K0R/KF3-L, 78K0R/KG3-L).
• Make the wiring between the XT1 and XT2 pins and the resonators as short as possible, and
minimize the parasitic capacitance and wiring resistance. Note this particularly when the ultralow power consumption oscillation (AMPHS1 = 1) is selected.
• Configure the circuit of the circuit board, using material with little wiring resistance.
• Place a ground pattern that has the same potential as VSS as much as possible near the XT1
oscillator.
• Be sure that the signal lines between the XT1 and XT2 pins, and the resonators do not cross
with the other signal lines. Do not route the wiring near a signal line through which a high
fluctuating current flows.
• The impedance between the XT1 and XT2 pins may drop and oscillation may be disturbed due
to moisture absorption of the circuit board in a high-humidity environment or dew
condensation on the board.
When using the circuit board in such an environment, take
measures to damp-proof the circuit board, such as by coating.
• When coating the circuit board, use material that does not cause capacitance or leakage
between the XT1 and XT2 pins.
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Figure 7-15 shows examples of incorrect resonator connection.
Figure 7-15. Examples of Incorrect Resonator Connection (1/2)
(a) Too long wiring
(b) Crossed signal line
PORT
VSS
X1
X2
VSS
X1
X2
NG
NG
NG
(c) The X1 and X2 signal line wires cross.
(d) A power supply/GND pattern exists
under the X1 and X2 wires.
VSS
VSS
X1
X1
X2
X2
Note
Power supply/GND pattern
Note
Do not place a power supply/GND pattern under the wiring section (section indicated by a broken line in the
figure) of the X1 and X2 pins and the resonators in a multi-layer board or double-sided board.
Do not configure a layout that will cause capacitance elements and affect the oscillation characteristics.
Remark
When using the subsystem clock, replace X1 and X2 with XT1 and XT2, respectively. Also, insert resistors
in series on the XT2 side.
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Figure 7-15. Examples of Incorrect Resonator Connection (2/2)
(e) Wiring near high alternating current
(f) Current flowing through ground line of oscillator
(potential at points A, B, and C fluctuates)
VDD
Pmn
X1
X2
High current
VSS
VSS
A
X1
B
X2
C
High current
(g) Signals are fetched
VSS
Caution
X1
X2
When X2 and XT1 are wired in parallel, the crosstalk noise of X2 may increase with XT1, resulting in
malfunctioning.
Remark
When using the subsystem clock, replace X1 and X2 with XT1 and XT2, respectively. Also, insert resistors
in series on the XT2 side.
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7.4.3 Internal high-speed oscillator
The internal high-speed oscillator is incorporated in the 78K0R/Kx3-L (1, 8 and 20 MHz (TYP.)). Oscillation can be
controlled by bit 0 (HIOSTOP) of the clock operation status control register (CSC) and bit 0 (DSCON) of the 20 MHz
internal high-speed oscillation control register (DSCCTL).
Caution To use the 1, 8, or 20 MHz internal high-speed oscillation clock, use the option byte to set the frequency
in advance (for details, see CHAPTER 25 OPTION BYTE).
Also, the internal high-speed oscillator
automatically starts oscillating after reset release. (If 8 MHz or 20 MHz is selected by using the option
byte, the microcontroller operates using the 8 MHz internal high-speed oscillator.) To use the 20 MHz
internal high-speed oscillator to operate the microcontroller, oscillation is started by setting bit 0
(DSCON) of the DSCCTL register to 1 with VDD ≥ 2.7 V.
7.4.4 Internal low-speed oscillator
The internal low-speed oscillator is incorporated in the 78K0R/Kx3-L.
The internal low-speed oscillation clock is used only as the watchdog timer clock. The internal low-speed oscillation
clock cannot be used as the CPU clock.
After a reset release, the internal low-speed oscillator automatically starts oscillation, and the watchdog timer is driven
(30 kHz (TYP.)) if the watchdog timer operation is enabled by the option byte.
The internal low-speed oscillator continues oscillation except when the watchdog timer stops. When the watchdog
timer operates, the internal low-speed oscillation clock does not stop, even in case of a program loop.
7.4.5 Prescaler
The prescaler generates a CPU/peripheral hardware clock by dividing the main system clock and subsystem clock.
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7.5 Clock Generator Operation
The clock generator generates the following clocks and controls the operation modes of the CPU, such as standby
mode (see Figure 7-1 and 7-2).
• Main system clock fMAIN
• High-speed system clock fMX
X1 clock fX
External main system clock fEX
• Internal high-speed oscillation clock fIH
• 20 MHz internal high-speed oscillation clock fIH20
• Subsystem clock fSUBNote
• Internal low-speed oscillation clock fIL
• CPU/peripheral hardware clock fCLK
Note
The 78K0R/KC3-L(40-pin) doesn’t have the XT1 oscillator (subsystem clock).
The CPU starts operation when the internal high-speed oscillator starts outputting after a reset release in the
78K0R/Kx3-L.
When the power supply voltage is turned on, the clock generator operation is shown in Figure 7-16 and Figure 7-17.
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Figure 7-16. Clock Generator Operation When Power Supply Voltage Is Turned On
(When LVI Default Start Function Stopped Is Set (Option Byte: LVIOFF = 1))
Power supply
voltage (VDD)
1.8 V
1.61 V
(TYP.)
0.5 V/ms
(MIN.)
0V
<1>
Internal reset signal
<3>
Switched by
software
Reset processing
(2.12 to 5.84 ms)
SELDSC = 1
<5>
1 or 8 MHz internal highspeed oscillation clock
CPU clock
<5>
20 MHz internal highspeed oscillation clock
1 or 8 MHz internal highspeed oscillation clock
High-speed
system clock
<5>
Subsystem
clock
<2>
Internal high-speed
oscillation clock (fIH)
Note 1
High-speed
system clock (fMX)
(when X1 oscillation
selected)
<4>
<4>
20 MHz internal
high-speed
oscillation clock (fIH20)
DSCON = 1
is set by software.
Subsystem clock (fSUB)
(when XT1 oscillation
selected)
X1 clock
oscillation stabilization timeNote 2
Starting X1 oscillation
is specified by software.
20 MHz internal high-speed oscillation clock
oscillation stabilization time : 100 μ s
<4>
Starting XT1 oscillation
is specified by software.
<1> When the power is turned on, an internal reset signal is generated by the power-on-clear (POC) circuit.
<2> When the power supply voltage exceeds 1.61 V (TYP.), the reset is released and the internal high-speed
oscillator
Note 3
automatically starts oscillation.
<3> The CPU starts operation on the internal high-speed oscillation clock
Note 3
after a reset processing such as waiting
for the voltage of the power supply or regulator to stabilize has been performed after reset release.
<4> Set the start of oscillation of the X1 or XT1 clock
Note 4
via software (see 7.6.4 Example of setting X1 oscillation
clock and 7.6.5 Example of setting XT1 oscillation clock).
Switch to oscillation using the 20 MHz internal high-speed oscillation clock after confirming that the power supply
voltage is at least 2.7 V and setting the DSCON bit to 1 by using software.
<5> When switching the CPU clock to the X1 or XT1 clock, wait for the clock oscillation to stabilize, and then set
switching via software (see 7.6.4 Example of setting X1 oscillation clock and 7.6.5 Example of setting XT1
oscillation clock).
Switch to the 20 MHz internal high-speed oscillation clock by setting the DSCON bit (bit 0 of the 20 MHz internal
high-speed oscillation control register (DSCCTL)), waiting for 100 μs, and then setting the SELDSC bit to 1 by
using software Note 5.
(Notes and Cautions are listed on the next page.)
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Notes 1.
The internal reset processing time includes the oscillation accuracy stabilization time of the internal high-
2.
When releasing a reset, confirm the oscillation stabilization time for the X1 clock using the oscillation
speed oscillation clock.
stabilization time counter status register (OSTC).
3.
The microcontroller operates on the 8 MHz internal high-speed oscillation clock if 8 MHz or 20 MHz is
selected for the internal high-speed oscillator by using the option byte or on the 1 MHz internal high-speed
oscillation clock if 1 MHz is selected.
4.
The 78K0R/KC3-L (40-pin) doesn’t have the subsystem clock.
5.
If the internal high-speed oscillator is set to 1 MHz by using the option byte, the 20 MHz internal high-speed
oscillation clock cannot be used.
Cautions 1. If the voltage rises with a slope of less than 0.5 V/ms (MIN.) from power application until the
voltage reaches 1.8 V, input a low level to the RESET pin from power application until the voltage
reaches 1.8 V, or set the LVI default start function stopped by using the option byte (LVIOFF = 0)
(see Figure 7-17). By doing so, the CPU operates with the same timing as <2> and thereafter in
Figure 7-16 after reset release by the RESET pin.
2. It is not necessary to wait for the oscillation stabilization time when an external clock input from
the EXCLK pin is used.
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Figure 7-17. Clock Generator Operation When Power Supply Voltage Is Turned On
(When LVI Default Start Function Enabled Is Set (Option Byte: LVIOFF = 0))
Power supply
voltage (VDD)
2.07 V
0V
<1>
Internal reset signal
Switched by
software
Reset processing
(195 to 341 μs)
<3>
CPU clock
SELDSC = 1
<5>
1 or 8 MHz internal highspeed oscillation clock
<5>
20 MHz internal highspeed oscillation clock
1 or 8 MHz internal highspeed oscillation clock
High-speed
system clock
<5>
Subsystem
clock
<2>
Internal high-speed
oscillation clock (fIH)
Note 1
High-speed
system clock (fMX)
(when X1 oscillation
selected)
<4>
Starting X1 oscillation
is specified by software.
<4>
20 MHz internal
high-speed
oscillation clock (fIH20)
DSCON = 1
is set by software.
Subsystem clock (fSUB)
(when XT1 oscillation
selected)
X1 clock
oscillation stabilization timeNote 2
20 MHz internal high-speed oscillation clock
oscillation stabilization time : 100 μ s
<4>
Starting XT1 oscillation
is specified by software.
<1> When the power is turned on, an internal reset signal is generated by the low-voltage detector (LVI) circuit.
<2> When the power supply voltage exceeds 2.07 V (TYP.), the reset is released and the internal high-speed
oscillator
Note 3
automatically starts oscillation.
<3> After the reset is released and reset processing is performed, the CPU starts operation on the internal high-speed
oscillation clock
Note 3
.
<4> Set the start of oscillation of the X1 or XT1 clock
Note 4
via software (see 7.6.4 Example of setting X1 oscillation
clock and 7.6.5 Example of setting XT1 oscillation clock).
Switch to oscillation using the 20 MHz internal high-speed oscillation clock after setting the DSCON bit to 1 by
using software.
<5> When switching the CPU clock to the X1 or XT1 clock
Note 4
, wait for the clock oscillation to stabilize, and then set
switching via software (see 7.6.4 Example of setting X1 oscillation clock and 7.6.5 Example of setting XT1
oscillation clock).
Switch to the 20 MHz internal high-speed oscillation clock after confirming that the power supply voltage is at
least 2.7 V, setting the DSCON bit (bit 0 of the 20 MHz internal high-speed oscillation control register (DSCCTL)),
waiting for 100 μs, and then setting the SELDSC bit to 1 by using software Note 5.
(Notes and Cautions are listed on the next page.)
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Notes 1.
CHAPTER 7 CLOCK GENERATOR
The internal reset processing time includes the oscillation accuracy stabilization time of the internal highspeed oscillation clock.
2.
When releasing a reset, confirm the oscillation stabilization time for the X1 clock using the oscillation
stabilization time counter status register (OSTC).
3.
The microcontroller operates on the 8 MHz internal high-speed oscillation clock if 8 MHz or 20 MHz is
selected for the internal high-speed oscillator by using the option byte or on the 1 MHz internal high-speed
oscillation clock if 1 MHz is selected.
4.
The 78K0R/KC3-L (40-pin) doesn’t have the subsystem clock.
5.
If the internal high-speed oscillator is set to 1 MHz by using the option byte, the 20 MHz internal high-speed
oscillation clock cannot be used.
Cautions 1. A voltage stabilization time (about 2.12 to 5.84 ms) is required after the supply voltage reaches
1.61 V (TYP.). If the time for the supply voltage to rise from 1.61 V (TYP.) to 2.07 V (TYP.) is
shorter than the voltage stabilization time, reset processing is entered after the voltage
stabilization time elapses.
2. It is not necessary to wait for the oscillation stabilization time when an external clock input from
the EXCLK pin is used.
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7.6 Controlling Clock
7.6.1 Example of setting 8 MHz internal high-speed oscillator
To use the 8 MHz internal high-speed oscillation clock as the CPU/peripheral hardware clock (fCLK), set 000C1H of the
option byte to FBH. Use the system clock control register (CKC) to specify the division ratio for the clock to be supplied to
the CPU/peripheral hardware clock after releasing reset. When using the default division setting (fIH/2 = 4 MHz), the CKC
register is not required to be set.
[Option byte setting]
Set address 000C1H to FBH.
Option
byte
7
(000C1H)
1
6
1
5
1
4
1
3
1
2
1
0
FRQSEL2
FRQSEL1
LVIOFF
0
1
1
LVIOFF bit: Set this bit to 0 to turn on the LVI by default when releasing the power-on-reset.
[Register settings]
<1> Use the MDIV2 to MDIV0 bits of the CKC register to specify the division ratio for the CPU/peripheral hardware
clock.
7
CLS
CKC
Note
Note
0
6
5
4
CSS
MCS
MCM0
0
0
0
3
1
2
1
0
MDIV2
MDIV1
MDIV0
0/1
0/1
0/1
CLS bit is not provided in the 78K0R/KC3-L (40-pin). In the 78K0R/KC3-L (40-pin), be sure to clear CLS bit
to 0.
7.6.2 Example of setting 1 MHz internal high-speed oscillator
To use the 1 MHz internal high-speed oscillation clock as the CPU/peripheral hardware clock (fCLK), set 000C1H of the
option byte to FDH. Use the system clock control register (CKC) to specify the division ratio for the clock to be supplied to
the CPU/peripheral hardware clock after releasing reset. When using the default division setting (fIH/2 = 0.5 MHz), the
CKC register is not required to be set.
[Option byte setting]
Set address 000C1H to FDH.
Option
byte
7
(000C1H)
1
6
1
5
1
4
1
3
1
2
1
0
FRQSEL2
FRQSEL1
LVIOFF
1
0
1
LVIOFF bit: Set this bit to 0 to turn on the LVI by default when releasing the power-on-reset.
[Register settings]
<1> Use the MDIV2 to MDIV0 bits of the CKC register to specify the division ratio for the CPU/peripheral hardware
clock.
7
CLS
CKC
Note
Note
0
6
5
4
CSS
MCS
MCM0
0
0
0
3
1
2
1
0
MDIV2
MDIV1
MDIV0
0/1
0/1
0/1
CLS bit is not provided in the 78K0R/KC3-L (40-pin). In the 78K0R/KC3-L (40-pin), be sure to clear CLS bit
to 0.
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7.6.3 Example of setting 20 MHz internal high-speed oscillator
To use the 20 MHz internal high-speed oscillation clock as the CPU/peripheral hardware clock (fCLK), set 000C1H of the
option byte to FBH. After releasing reset, set the operation speed mode control register (OSMC) and then the 20 MHz
internal high-speed oscillation control register (DSCCTL).
[Option byte setting]
Set address 000C1H to FBH.
Option
byte
7
6
5
4
3
(000C1H)
1
1
1
1
1
2
1
0
FRQSEL2
FRQSEL1
LVIOFF
0
1
1
LVIOFF bit: Set this bit to 0 to turn on the LVI by default when releasing the power-on-reset.
[Register settings] Set the register in the order of <1> to <5> below.
<1> Set the OSMC register so that the microcontroller operates at a frequency exceeding 10 MHz.
7
6
5
4
3
2
Note
RTCLPC
OSMC
0
0
RTCLPC bit
Note
0
0
0
0
1
0
FLPC
FSEL
0
1
: Set this bit to 1 to operate only the watch in sub-HALT mode (ultra-low current
consumption).
Note
RTCLPC bit is not provided in the 78K0R/KC3-L (40-pin). In the 78K0R/KC3-L (40-pin), be sure to clear
RTCLPC bit to 0.
<2> Set (1) the DSCON bit of the DSCCTL register to operate the 20 MHz internal high-speed oscillator.
DSCCTL
7
6
5
4
0
0
0
0
3
2
DSCS
SELDSC
0
0
1
0
DSCON
0
1
<3> Set (1) the DSCON bit and then wait for 100 μ s.
<4> Set (1) the SELDSC bit of the DSCCTL register to switch the internal high-speed oscillation clock from 8 MHz to 20
MHz.
DSCCTL
7
6
5
4
0
0
0
0
3
2
DSCS
SELDSC
0
1
1
0
DSCON
0
1
<5> Use the MDIV2 to MDIV0 bits of the CKC register to specify the division ratio for the CPU/peripheral hardware
clock.
7
CLS
CKC
Note
Note
0
6
5
4
CSS
MCS
MCM0
0
0
0
3
1
2
1
0
MDIV2
MDIV1
MDIV0
0/1
0/1
0/1
CLS bit is not provided in the 78K0R/KC3-L (40-pin). In the 78K0R/KC3-L (40-pin), be sure to clear CLS bit
to 0.
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7.6.4 Example of setting X1 oscillation clock
After a reset release, the CPU/peripheral hardware clock (fCLK) always starts operating with the internal high-speed
oscillation clock. To subsequently change the clock to the X1 oscillation clock, set the oscillator and start oscillation by
using the operation speed mode control register (OSMC), clock operation mode control register (CMC), and clock
operation status control register (CSC) and wait for oscillation to stabilize by using the oscillation stabilization time counter
status register (OSTC). After the oscillation stabilizes, set the X1 oscillation clock to fCLK by using the system clock control
register (CKC).
Set the frequency of the internal oscillation clock to be supplied immediately after releasing reset by using the option
byte.
[Option byte setting]
Set address 000C1H to FBH.
Option
byte
7
(000C1H)
1
6
5
1
1
4
3
1
2
1
0
FRQSEL2
FRQSEL1
LVIOFF
0
1
1
1
LVIOFF bit: Set this bit to 0 to turn on the LVI by default when releasing the power-on-reset.
FRQSEL2 and FRQSEL1 bits: Set the FRQSEL2 and FRQSEL1 bits to 1 and 0, respectively, to set the
internal oscillation clock frequency to 1 MHz.
[Register settings] Set the register in the order of <1> to <5> below.
<1> Use the OSMC register to set the frequency of the CPU/peripheral hardware.
7
6
5
4
3
2
0
0
0
0
0
Note
RTCLPC
OSMC
0
1
0
FLPC
FSEL
0
1
FSEL bit: Set this bit to 0 if the CPU/peripheral hardware clock is 10 MHz or less.
RTCLPC bitNote: Set this bit to 1 to operate only the watch in sub-HALT mode (ultra-low current
consumption).
Note
RTCLPC bit is not provided in the 78K0R/KC3-L (40-pin). In the 78K0R/KC3-L (40-pin), be sure to clear
RTCLPC bit to 0.
<2> Set (1) the OSCSEL bit of the CMC register to operate the X1 oscillator.
7
CMC
6
5
EXCLK
OSCSEL
0
1
4
3
Note
OSCSELS
0
0
0
2
1
0
AMPHS1
AMPHS0
AMPH
0
0
1
AMPH bit: Set this bit to 0 if the X1 oscillation clock is 10 MHz or less.
OSCSELS bitNote: Set this bit to 1 to set P122 and P123 to XT1 oscillation mode.
AMPHS0 and AMPHS1 bits: These bits are used to specify the oscillation mode of the XT1 oscillator.
Note
OSCSELS bit is not provided in the 78K0R/KC3-L (40-pin).
<3> Clear (0) the MSTOP bit of the CSC register to start oscillating the X1 oscillator.
7
CSC
6
XTSTOP
MSTOP
0
1
Note
XTSTOP bit
Note
5
4
3
2
1
Note
0
HIOSTOP
0
0
0
0
0
0
: Set this bit to 0 to oscillate the XT1 oscillator.
XTSTOP bit is not provided in the 78K0R/KC3-L (40-pin).
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<4> Use the OSTC register to wait for oscillation of the X1 oscillator to stabilize.
Example: Wait until the bits reach the following values when a wait of at least 102.4 μs is set based on a 10 MHz
resonator.
OSTC
7
6
5
4
3
2
1
0
MOST8
MOST9
MOST10
MOST11
MOST13
MOST15
MOST17
MOST18
1
1
1
0
0
0
0
0
<5> Use the MCM0 bit of the CKC register to specify the X1 oscillation clock as the CPU/peripheral hardware clock.
Use the MDIV2 to MDIV0 bits to specify the division ratio.
7
CLS
CKC
Note
Note
0
6
5
4
CSS
MCS
MCM0
0
0
1
3
1
2
1
0
MDIV2
MDIV1
MDIV0
0/1
0/1
0/1
CLS bit is not provided in the 78K0R/KC3-L (40-pin). In the 78K0R/KC3-L (40-pin), bit 7 is fixed to 0.
7.6.5 Example of setting XT1 oscillation clock (products other than 78K0R/KC3-L (40-pin))
After a reset release, the CPU/peripheral hardware clock (fCLK) always starts operating with the internal high-speed
oscillation clock. To subsequently change the clock to the XT1 oscillation clock, set the oscillator and start oscillation by
using the operation speed mode control register (OSMC), clock operation mode control register (CMC), and clock
operation status control register (CSC), set the XT1 oscillation clock to fCLK by using the system clock control register
(CKC).
Set the frequency of the internal oscillation clock to be supplied immediately after releasing reset by using the option
byte.
[Option byte setting]
Set address 000C1H to FBH.
Option
byte
7
6
5
4
3
(000C1H)
1
1
1
1
1
2
1
0
FRQSEL2
FRQSEL1
LVIOFF
0
1
1
LVIOFF bit: Set this bit to 0 to turn on the LVI by default when releasing the power-on-reset.
FRQSEL2 and FRQSEL1 bits: Set the FRQSEL2 and FRQSEL1 bits to 1 and 0, respectively, to set the
internal oscillation clock frequency to 1 MHz.
[Register settings] Set the register in the order of <1> to <5> below.
<1> Use the OSMC register to set the frequency of the CPU/peripheral hardware.
7
OSMC
6
5
4
3
2
RTCLPC
0
0
0
0
0
0
1
0
FLPC
FSEL
0
0
RTCLPC bit: Set this bit to 1 to operate only the watch in sub-HALT mode (ultra-low current consumption).
<2> Set (1) the OSCSELS bit of the CMC register to operate the XT1 oscillator.
CMC
7
6
EXCLK
OSCSEL
0
0
5
4
3
OSCSELS
0
1
0
2
1
0
AMPHS1
AMPHS0
AMPH
0/1
0/1
0
AMPHS0 and AMPHS1 bits: These bits are used to specify the oscillation mode of the XT1 oscillator.
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<3> Clear (0) the XTSTOP bit of the CSC register to start oscillating the XT1 oscillator.
CSC
7
6
MSTOP
XTSTOP
1
0
5
4
3
2
1
0
0
0
0
0
0
HIOSTOP
0
<4> Use the timer function or another function to wait for oscillation of the subsystem clock to stabilize by using
software.
<5> Use the CSS bit of the CKC register to specify the XT1 oscillation clock as the CPU/peripheral hardware clock.
CKC
7
6
5
4
CLS
CSS
MCS
MCM0
0
1
0
0
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2
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MDIV2
MDIV1
MDIV0
0
0
0
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7.6.6 CPU clock status transition diagram
Figure 7-18 and Figure 7-19 show the CPU clock status transition diagram of this product.
Figure 7-18. CPU Clock Status Transition Diagram (78K0R/KC3-L (40-pin))
Internal high-speed oscillation: Woken up
X1 oscillation/EXCLK input: Stops (input port mode)
DSC oscillation: Stops
Power ON
VDD < 1.61 V±0.09
(A)
Internal high-speed oscillation: Operating
X1 oscillation/EXCLK input:
Selectable by CPU
DSC oscillation: Selectable by CPU
Internal high-speed oscillation:
Selectable by CPU
X1 oscillation/EXCLK input:
Cannot be selected by CPU
DSC oscillation: Operating
Notes 2, 3
Reset release
VDD ≥ 1.61 V±0.09
Internal high-speed oscillation: Operating
X1 oscillation/EXCLK input: Stops (input port mode)
DSC oscillation: Stops
VDD ≥ 1.8 V
Note 1
(B)
CPU: Operating
with internal highspeed oscillation
(H)
CPU: Internal highspeed oscillation
→ STOP
(J)
CPU:
Operating with
DSC oscillation
(E)
CPU: Internal highspeed oscillation
→ HALT
(C)
(K)
CPU:
DSC oscillation
→ HALT
CPU: Operating
with X1 oscillation or
EXCLK input
Notes 1.
Internal high-speed oscillation:
Operating
X1 oscillation/EXCLK input:
Oscillatable
DSC oscillation: Stops
(I)
CPU: X1
oscillation/EXCLK
input → STOP
(F)
Internal high-speed
oscillation: Selectable by CPU
X1 oscillation/EXCLK input:
Operating
DSC oscillation: Stops
Internal high-speed
oscillation: Stops
X1 oscillation/EXCLK
input: Stops
DSC oscillation: Stops
Internal high-speed
oscillation: Selectable by CPU
X1 oscillation/EXCLK input:
Operating
DSC oscillation: Stops
CPU: X1
oscillation/EXCLK
input → HALT
Internal high-speed
oscillation: Oscillatable
X1 oscillation/EXCLK input:
Operating
DSC oscillation: Stops
Internal high-speed oscillation:
Stops
X1 oscillation/EXCLK input:
Stops
DSC oscillation: Stops
After reset release, an operation at one of the following operating frequencies is started, because fCLK = fIH/2
has been selected by setting the system clock control register (CKC) to 09H.
• When 1 MHz has been selected by using the option byte: 500 kHz (1 MHz/2)
• When 8 MHz or 20 MHz has been selected by using the option byte: 4 MHz (8 MHz/2)
2.
Specify 20 MHz internal oscillation after checking that VDD is at least 2.7 V.
3.
20 MHz internal oscillation cannot be used if 1 MHz internal oscillation is selected by using the option byte.
Remarks 1. If the low-power-supply detector (LVI) is set to ON by default by the option bytes, the reset will not be
released until the power supply voltage (VDD) exceeds 2.07 V±0.2 V.
After the reset operation, the status will shift to (B) in the above figure.
2. DSC: 20 MHz internal high-speed oscillation clock
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Figure 7-19. CPU Clock Status Transition Diagram (78K0R/KC3-L (44-pin, 48-pin), KD3-L, KE3-L, KF3-L, KG3-L)
Internal high-speed oscillation: Woken up
X1 oscillation/EXCLK input: Stops (input port mode)
XT1 oscillation: Stops (input port mode)
DSC oscillation: Stops
Power ON
VDD < 1.61 V±0.09
(A)
Internal high-speed oscillation:
Selectable by CPU
X1 oscillation/EXCLK input:
Cannot be selected by CPU
XT1 oscillation:
Cannot be selected by CPU
DSC oscillation: Operating
Internal high-speed oscillation:
Oscillatable
X1 oscillation/EXCLK input:
Oscillatable
XT1 oscillation: Oscillatable
DSC oscillation: Operating
Internal high-speed oscillation: Operating
X1 oscillation/EXCLK input:
Selectable by CPU
XT1 oscillation: Selectable by CPU
DSC oscillation: Selectable by CPU
Notes 2, 3
VDD ≥ 1.8 V
Note 1
(B)
CPU: Operating
with internal highspeed oscillation
(H)
CPU: Internal highspeed oscillation
→ STOP
(J)
(D)
(K)
CPU:
XT1 oscillation
→ HALT
(E)
CPU:
Operating with
XT1 oscillation
CPU: Internal highspeed oscillation
→ HALT
(C)
CPU: Operating
with X1 oscillation or
EXCLK input
Internal high-speed oscillation:
Selectable by CPU
X1 oscillation/EXCLK input:
Selectable by CPU
XT1 oscillation: Operating
DSC oscillation: Stops
Internal high-speed oscillation:
Oscillatable
X1 oscillation/EXCLK input:
Oscillatable
XT1 oscillation: Operating
DSC oscillation: Stops
Notes 1.
VDD ≥ 1.61 V±0.09
Internal high-speed oscillation: Operating
X1 oscillation/EXCLK input: Stops (input port mode)
XT1 oscillation: Stops (input port mode)
DSC oscillation: Stops
CPU:
Operating with
DSC oscillation
CPU:
DSC oscillation
→ HALT
(G)
Reset release
(I)
Internal high-speed oscillation:
Operating
X1 oscillation/EXCLK input:
Oscillatable
XT1 oscillation: Oscillatable
DSC oscillation: Stops
CPU: X1
oscillation/EXCLK
input → STOP
(F)
CPU: X1
oscillation/EXCLK
input → HALT
Internal high-speed
oscillation: Selectable by CPU
X1 oscillation/EXCLK input:
Operating
XT1 oscillation:
Selectable by CPU
DSC oscillation: Stops
Internal high-speed
oscillation: Stops
X1 oscillation/EXCLK
input: Stops
XT1 oscillation: Oscillatable
DSC oscillation: Stops
Internal high-speed
oscillation: Oscillatable
X1 oscillation/EXCLK input:
Operating
XT1 oscillation: Oscillatable
DSC oscillation: Stops
Internal high-speed oscillation:
Stops
X1 oscillation/EXCLK input:
Stops
XT1 oscillation: Oscillatable
DSC oscillation: Stops
After reset release, an operation at one of the following operating frequencies is started, because fCLK = fIH/2
has been selected by setting the system clock control register (CKC) to 09H.
• When 1 MHz has been selected by using the option byte: 500 kHz (1 MHz/2)
• When 8 MHz or 20 MHz has been selected by using the option byte: 4 MHz (8 MHz/2)
2.
Specify 20 MHz internal oscillation after checking that VDD is at least 2.7 V.
3.
20 MHz internal oscillation cannot be used if 1 MHz internal oscillation is selected by using the option byte.
Remarks 1. If the low-power-supply detector (LVI) is set to ON by default by the option bytes, the reset will not be
released until the power supply voltage (VDD) exceeds 2.07 V±0.2 V.
After the reset operation, the status will shift to (B) in the above figure.
2. DSC: 20 MHz internal high-speed oscillation clock
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Table 7-4 shows transition of the CPU clock and examples of setting the SFR registers.
Table 7-4. CPU Clock Transition and SFR Register Setting Examples (1/6)
(1) CPU operating with internal high-speed oscillation clock (B) after reset release (A)
Status Transition
(A) → (B)
SFR Register Setting
SFR registers do not have to be set (default status after reset release).
(2) CPU operating with high-speed system clock (C) after reset release (A)
(The CPU operates with the internal high-speed oscillation clock immediately after a reset release (B).)
(Setting sequence of SFR registers)
Setting Flag of SFR Register
CMC Register
Note 1
CSC
OSMC
OSTC
CKC
Register
Register
Register
Register
Status Transition
EXCLK
OSCSEL
AMPH
MSTOP
FSEL
(A) → (B) → (C)
0
1
0
0
0
MCM0
Must be
(X1 clock: 2 MHz ≤ fX ≤ 10 MHz)
(A) → (B) → (C)
0
1
1
0
1
Note 2
Must be
(X1 clock: 10 MHz < fX ≤ 20 MHz)
(A) → (B) → (C)
1
checked
1
checked
1
×
1
0
0/1
Note 2
Must not
1
be
(external main clock)
checked
Notes 1. The clock operation mode control register (CMC) can be written only once by an 8-bit memory
manipulation instruction after reset release.
2. FSEL = 1 when fCLK > 10 MHz
If a divided clock is selected and fCLK ≤ 10 MHz, use with FSEL = 0 is possible even if fX > 10 MHz.
Caution Set the clock after the supply voltage has reached the operable voltage of the clock to be set (see
CHAPTER 30 ELECTRICAL SPECIFICATIONS (78K0R/KC3-L, 78K0R/KD3-L, 78K0R/KE3-L) or
CHAPTER 31 ELECTRICAL SPECIFICATIONS (78K0R/KF3-L, 78K0R/KG3-L)).
Remark ×: don’t care
(3) CPU operating with subsystem clock (D) after reset release (A) (products other than 78K0R/KC3-L (40-pin))
(The CPU operates with the internal high-speed oscillation clock immediately after a reset release (B).)
(Setting sequence of SFR registers)
Setting Flag of SFR Register
CMC Register
Note
CSC
Waiting for
CKC
Register
Oscillation
Register
Status Transition
OSCSELS
AMPHS1
AMPHS0
XTSTOP
Stabilization
CSS
(A) → (B) → (D)
1
0/1
0/1
0
Necessary
1
Note The clock operation mode control register (CMC) can be written only once by an 8-bit memory manipulation
instruction after reset release.
Remark (A) to (K) in Table 7-4 correspond to (A) to (K) in Figure 7-19.
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Table 7-4. CPU Clock Transition and SFR Register Setting Examples (2/6)
(4) CPU operating with 20 MHz internal high-speed oscillation clock (J) after reset release (A)
(The CPU operates with the internal high-speed oscillation clock immediately after a reset release (B).)
(Setting sequence of SFR registers)
Setting Flag of SFR Register
Status Transition
Note
Waiting for Oscillation
DSCCTL Register
DSCON
Stabilization
SELDSC
1
Necessary
1
DSCCTL Register
(A) → (B) → (J)
(100 μs)
Note
Check that VDD ≥ 2.7 V and set DSCON = 1.
(5) CPU clock changing from internal high-speed oscillation clock (B) to high-speed system clock (C)
(Setting sequence of SFR registers)
CMC Register
Setting Flag of SFR Register
Status Transition
(B) → (C)
Note 1
EXCLK
OSCSEL
AMPH
0
1
0
OSTS
CSC
OSMC
OSTC
CKC
Register
Register
Register
Register
Register
MSTOP
FSEL
0
0
Note 2
0
1
1
Note 2
0
1
Note 3
1
Must be
1
checked
(X1 clock: 10 MHz < fX ≤ 20 MHz)
(B) → (C)
Must be
checked
(X1 clock: 2 MHz ≤ fX ≤ 10 MHz)
(B) → (C)
MCM0
1
1
×
Note 2
0
0/1
Must not
1
be
(external main clock)
checked
Unnecessary if these registers Unnecessary if the CPU is operating with
are already set
the high-speed system clock
Notes 1. The clock operation mode control register (CMC) can be changed only once after reset release. This
setting is not necessary if it has already been set.
2. Set the oscillation stabilization time as follows.
• Desired the oscillation stabilization time counter status register (OSTC) oscillation stabilization time ≤
Oscillation stabilization time set by the oscillation stabilization time select register (OSTS)
3. FSEL = 1 when fCLK > 10 MHz
If a divided clock is selected and fCLK ≤ 10 MHz, use with FSEL = 0 is possible even if fX > 10 MHz.
Caution Set the clock after the supply voltage has reached the operable voltage of the clock to be set (see
CHAPTER 30 ELECTRICAL SPECIFICATIONS (78K0R/KC3-L, 78K0R/KD3-L, 78K0R/KE3-L) or
CHAPTER 31 ELECTRICAL SPECIFICATIONS (78K0R/KF3-L, 78K0R/KG3-L)).
Remarks 1. ×: don’t care
2. (A) to (K) in Table 7-4 correspond to (A) to (K) in Figure 7-19.
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Table 7-4. CPU Clock Transition and SFR Register Setting Examples (3/6)
(6) CPU clock changing from internal high-speed oscillation clock (B) to subsystem clock (D) (products other
than 78K0R/KC3-L (40-pin))
(Setting sequence of SFR registers)
Setting Flag of SFR Register
CMC Register
Note
CSC Register
Waiting for
CKC Register
XTSTOP
Oscillation
CSS
OSCSELS
Status Transition
Stabilization
(B) → (D)
1
0
Necessary
1
Unnecessary if the CPU is operating
with the subsystem clock
Note The clock operation mode control register (CMC) can be written only once by an 8-bit memory manipulation
instruction after reset release.
(7) CPU clock changing from internal high-speed oscillation clock (B) to 20 MHz internal high-speed oscillation
clock (J)
(Setting sequence of SFR registers)
Setting Flag of SFR Register
Status Transition
Note
Waiting for Oscillation
DSCCTL Register
DSCON
Stabilization
SELDSC
1
Necessary (100 μs)
1
DSCCTL Register
(B) → (J)
Unnecessary if the CPU is operating with the 20 MHz
internal high-speed oscillation clock
Note
Check that VDD ≥ 2.7 V and set DSCON = 1.
(8) CPU clock changing from high-speed system clock (C) to internal high-speed oscillation clock (B)
(Setting sequence of SFR registers)
Setting Flag of SFR Register
Status Transition
(C) → (B)
CSC Register
Oscillation accuracy
CKC Register
HIOSTOP
stabilization time
MCM0
0
10 μ s
0
Unnecessary if the
CPU is operating with
the internal highspeed oscillation
clock
Remark (A) to (K) in Table 7-4 correspond to (A) to (K) in Figure 7-19.
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Table 7-4. CPU Clock Transition and SFR Register Setting Examples (4/6)
(9) CPU clock changing from high-speed system clock (C) to subsystem clock (D) (products other than
78K0R/KC3-L (40-pin))
(Setting sequence of SFR registers)
Setting Flag of SFR Register
CSC Register
Waiting for Oscillation
CKC Register
XTSTOP
Stabilization
CSS
0
Necessary
1
Status Transition
(C) → (D)
Unnecessary if the CPU is operating with the
subsystem clock
(10) CPU clock changing from subsystem clock (D) to internal high-speed oscillation clock (B) (products other
than 78K0R/KC3-L (40-pin))
(Setting sequence of SFR registers)
Setting Flag of SFR Register
Status Transition
(D) → (B)
CSC Register
CKC Register
HIOSTOP
MCM0
CSS
0
0
0
Unnecessary if the CPU
Unnecessary if this
is operating with the
register is already set
internal high-speed
oscillation clock
Remark (A) to (K) in Table 7-4 correspond to (A) to (K) in Figure 7-19.
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Table 7-4. CPU Clock Transition and SFR Register Setting Examples (5/6)
(11) CPU clock changing from subsystem clock (D) to high-speed system clock (C) (products other than
78K0R/KC3-L (40-pin))
(Setting sequence of SFR registers)
Setting Flag of SFR Register
OSTS
Status Transition
(D) → (C) (X1 clock: 2 MHz ≤
Note 1
OSMC
OSTC
Register
Register
CSC Register
Register
MSTOP
FSEL
0
0
Must be
fX ≤ 10 MHz)
CKC Register
MCM0
CSS
1
0
1
0
1
0
checked
(D) → (C) (X1 clock: 10 MHz <
Note 1
0
1
Note 2
Must be
fX ≤ 20 MHz)
checked
(D) → (C) (external main
Note 1
0
0/1
Must not be
clock)
checked
Unnecessary if the CPU is operating with the high-speed
system clock
Notes 1.
Unnecessary if these
registers are already set
Set the oscillation stabilization time as follows.
• Desired the oscillation stabilization time counter status register (OSTC) oscillation stabilization time ≤
Oscillation stabilization time set by the oscillation stabilization time select register (OSTS)
2. FSEL = 1 when fCLK > 10 MHz
If a divided clock is selected and fCLK ≤ 10 MHz, use with FSEL = 0 is possible even if fX > 10 MHz.
Caution Set the clock after the supply voltage has reached the operable voltage of the clock to be set (see
CHAPTER 30 ELECTRICAL SPECIFICATIONS (78K0R/KC3-L, 78K0R/KD3-L, 78K0R/KE3-L) or
CHAPTER 31 ELECTRICAL SPECIFICATIONS (78K0R/KF3-L, 78K0R/KG3-L)).
(12) CPU clock changing from 20 MHz internal high-speed oscillation clock (J) to internal high-speed oscillation
clock (B)
(Setting sequence of SFR registers)
Setting Flag of SFR Register
Status Transition
(J) → (B)
DSCCTL Register
SELDSC
DSCON
0
0
Remark (A) to (K) in Table 7-4 correspond to (A) to (K) in Figure 7-19.
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Table 7-4. CPU Clock Transition and SFR Register Setting Examples (6/6)
(13) • HALT mode (E) set while CPU is operating with internal high-speed oscillation clock (B)
• HALT mode (F) set while CPU is operating with high-speed system clock (C)
• HALT mode (G) set while CPU is operating with subsystem clock (D) (products other than 78K0R/KC3-L (40pin))
• HALT mode (K) set while CPU is operating with 20 MHz internal high-speed oscillation clock (J)
Status Transition
(B) → (E)
Setting
Executing HALT instruction
(C) → (F)
(D) → (G)
(J) → (K)
(14) • STOP mode (H) set while CPU is operating with internal high-speed oscillation clock (B)
• STOP mode (I) set while CPU is operating with high-speed system clock (C)
(Setting sequence)
Status Transition
(B) → (H)
Setting
−
Stopping peripheral
functions that cannot
(C) → (I)
In X1 oscillation
operate in STOP mode
Executing STOP
instruction
Sets the OSTS
register
External main
−
system clock
Remark (A) to (K) in Table 7-4 correspond to (A) to (K) in Figure 7-19.
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7.6.7 Condition before changing CPU clock and processing after changing CPU clock
Condition before changing the CPU clock and processing after changing the CPU clock are shown below.
Table 7-5. Changing CPU Clock (1/2)
CPU Clock
Before Change
Condition Before Change
Processing After Change
After Change
Stabilization of X1 oscillation
Operating current can be reduced by
speed oscillation
• OSCSEL = 1, EXCLK = 0, MSTOP = 0
stopping internal high-speed oscillator
clock
• After elapse of oscillation stabilization time
(HIOSTOP = 1).
Internal high-
X1 clock
External main
Enabling input of external clock from the
system clock
EXCLK pin
• OSCSEL = 1, EXCLK = 1, MSTOP = 0
Subsystem clock
Stabilization of XT1 oscillation
Note
• OSCSELS = 1, XTSTOP = 0
20 MHz internal
Stabilization of DSC oscillation with 20 MHz
high-speed
set by using the option byte
oscillation clock
• VDD ≥ 2.7 V
• After elapse of oscillation stabilization time
−
• After elapse of oscillation stabilization
time (100 μs) after setting to DSCON = 1
• SELDSC = 1
X1 clock
Internal high-
Oscillation of internal high-speed oscillator
speed oscillation
• HIOSTOP = 0
X1 oscillation can be stopped (MSTOP = 1).
clock
External main
Transition not possible
system clock
(To change the clock, set it again after
Subsystem clock
Stabilization of XT1 oscillation
Note
• OSCSELS = 1, XTSTOP = 0
−
executing reset once.)
X1 oscillation can be stopped (MSTOP = 1).
• After elapse of oscillation stabilization time
−
20 MHz internal
Transition cannot be performed unless the
high-speed
clock is changed to the internal high-speed
oscillation clock
oscillation clock once.
External main
Internal high-
Oscillation of internal high-speed oscillator
External main system clock input can be
system clock
speed oscillation
• HIOSTOP = 0
disabled (MSTOP = 1).
clock
X1 clock
Transition not possible
−
(To change the clock, set it again after
executing reset once.)
Subsystem clock
Stabilization of XT1 oscillation
External main system clock input can be
Note
• OSCSELS = 1, XTSTOP = 0
disabled (MSTOP = 1).
• After elapse of oscillation stabilization time
Note
20 MHz internal
Transition cannot be performed unless the
high-speed
clock is changed to the internal high-speed
oscillation clock
oscillation clock once.
−
The 78K0R/KC3-L (40-pin) doesn’t have the subsystem clock.
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Table 7-5. Changing CPU Clock (2/2)
CPU Clock
Before Change
Subsystem
Note
clock
Condition Before Change
Processing After Change
After Change
Internal high-
Oscillation of internal high-speed oscillator
XT1 oscillation can be stopped (XTSTOP =
speed oscillation
and selection of internal high-speed
1)
clock
oscillation clock as main system clock
• HIOSTOP = 0, MCS = 0
X1 clock
Stabilization of X1 oscillation and selection
of high-speed system clock as main system
clock
• OSCSEL = 1, EXCLK = 0, MSTOP = 0
• After elapse of oscillation stabilization time
• MCS = 1
External main
Enabling input of external clock from the
system clock
EXCLK pin and selection of high-speed
system clock as main system clock
• OSCSEL = 1, EXCLK = 1, MSTOP = 0
• MCS = 1
−
20 MHz internal
Transition cannot be performed unless the
high-speed
clock is changed to the internal high-speed
oscillation clock
oscillation clock once.
20 MHz internal
Internal high-
• SELDSC = 0
20 MHz internal high-speed oscillation clock
high-speed
speed oscillation
(Set when changing the clock.)
can be stopped (DSCON = 0)
oscillation clock
clock
X1 clock
Transition cannot be performed unless the
−
clock is changed to the internal high-speed
oscillation clock once.
External main
Transition cannot be performed unless the
system clock
clock is changed to the internal high-speed
−
oscillation clock once.
Subsystem
Note
clock
Transition cannot be performed unless the
−
clock is changed to the internal high-speed
oscillation clock once.
Note
The 78K0R/KC3-L (40-pin) doesn’t have the subsystem clock.
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7.6.8 Time required for switchover of CPU clock and main system clock
By setting bits 0 to 2, 4, and 6 (MDIV0 to MDIV2, MCM0, CSS) of the system clock control register (CKC), the CPU
clock can be switched (between the main system clock and the subsystem clock), main system clock can be switched
(between the internal high-speed oscillation clock and the high-speed system clock), and the division ratio of the main
system clock can be changed.
The actual switchover operation is not performed immediately after rewriting to the CKC register; operation continues
on the pre-switchover clock for several clocks (see Table 7-6 to Table 7-9).
Whether the CPU is operating on the main system clock or the subsystem clock can be ascertained using bit 7 (CLS) of
the CKC register. Whether the main system clock is operating on the high-speed system clock or internal high-speed
oscillation clock can be ascertained using bit 5 (MCS) of the CKC register.
When the CPU clock is switched, the peripheral hardware clock is also switched.
Table 7-6. Maximum Time Required for Main System Clock Switchover
Clock A
Switching directions
Clock B
fMAIN
Remark
fMAIN
See Table 7-7
fMX
See Table 7-8
(changing the division ratio)
fIH
fMAIN
fSUB
Note
See Table 7-9
Table 7-7. Maximum Number of Clocks Required for fMAIN ↔ fMAIN (Changing the Division Ratio)
Set Value Before Switchover
Set Value After Switchover
Clock A
Clock B
Clock A
1 + fA/fB clock
Clock B
1 + fB/fA clock
Table 7-8. Maximum Number of Clocks Required for fIH ↔ fMX
Set Value Before Switchover
Set Value After Switchover
MCM0
MCM0
0
1
(f MAIN = f IH )
(f MAIN = f MX )
0
f MX ≥f IH
1 + fIH/fMX clock
(f MAIN = f IH )
f MX <f IH
2fIH/fMX clock
1
f MX ≥f IH
2fMX/fIH clock
(f MAIN = f MX )
f MX <f IH
1 + fMX/fIH clock
Note The 78K0R/KC3-L (40-pin) doesn’t have the subsystem clock.
(Remarks 1 and 2 are listed on the next page.)
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Table 7-9. Maximum Number of Clocks Required for fMAIN ↔ fSUB
Note
Set Value Before Switchover
Set Value After Switchover
CSS
CSS
0
1
(f CLK = f MAIN )
(f CLK = f SUB )
0
1 + 2fMAIN/fSUB clock
(f CLK = f MAIN )
1
2 + fSUB/fMAIN clock
(f CLK = f SUB)
Remarks 1. The number of clocks listed in Table 7-7 to Table 7-9 is the number of CPU clocks before switchover.
2. Calculate the number of clocks in Table 7-7 to Table 7-9 by removing the decimal portion.
Example When switching the main system clock from the internal high-speed oscillation clock to the
high-speed system clock (@ oscillation with fIH = 8 MHz, fMX = 10 MHz)
1 + fIH/fMX = 1 + 8/10 = 1 + 0.8 = 1.8 → 2 clocks
Note The 78K0R/KC3-L (40-pin) doesn’t have the subsystem clock.
7.6.9 Conditions before clock oscillation is stopped
The following lists the register flag settings for stopping the clock oscillation (disabling external clock input) and
conditions before the clock oscillation is stopped.
Table 7-10. Conditions Before the Clock Oscillation Is Stopped and Flag Settings
Clock
Conditions Before Clock Oscillation Is Stopped
Flag Settings of SFR
(External Clock Input Disabled)
Register
Internal high-speed
MCS = 1 or CLS = 1
oscillation clock
(The CPU is operating on a clock other than the internal high-speed
HIOSTOP = 1
oscillation clock.)
X1 clock
MCS = 0 or CLS = 1
External main system clock
(The CPU is operating on a clock other than the high-speed system clock.)
Subsystem clock
Note
CLS = 0
MSTOP = 1
XTSTOP = 1
(The CPU is operating on a clock other than the subsystem clock.)
20 MHz internal high-speed
SELDSC = 0
oscillation clock
(The main system clock is operating on a clock other than the 20 MHz
DSCON = 0
internal high-speed oscillation clock.)
Note The 78K0R/KC3-L (40-pin) doesn’t have the subsystem clock.
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CHAPTER 8 TIMER ARRAY UNIT
The 78K0R/KC3-L, 78K0R/KD3-L, and 78K0R/KE3-L include a single timer array unit (timer array unit 0), whereas the
78K0R/KF3-L and 78K0R/KG3-L include two timer array units (timer array units 0 and 1).
The timer array unit 0 has eight 16-bit timers and the timer array unit 1 has four 16-bit timers.
Each 16-bit timer is called a channel and can be used as an independent timer. In addition, two or more “channels” can
be used to create a high-accuracy timer.
TIMER ARRAY UNIT 1 (KF3-L, KG3-L only)
TIMER ARRAY UNIT 0
channel 0
channel 0
channel 1
channel 1
channel 2
channel 2
channel 3
channel 6
channel 7
16-bit timers
For details about each function, see the table below.
Independent channel operation function
Simultaneous channel operation function
• Interval timer (→ refer to 8.7.1)
• One-shot pulse output(→ refer to 8.8.1)
• Square wave output (→ refer to 8.7.1)
• PWM output(→ refer to 8.8.2)
• Multiple PWM output(→ refer to 8.8.3)
• External event counter (→ refer to 8.7.2)
Note
(→ refer to 8.7.3)
• Divider function
• Input pulse interval measurement (→ refer to 8.7.4)
• Measurement of high-/low-level width of input signal
(→ refer to 8.7.5)
Note Only channel 0 of timer array unit 0 in the 78K0R/KD3-L, 78K0R/KE3-L, 78K0R/KF3-L, and 78K0R/KG3-L.
Channel 7 of the unit 0 can be used to realize LIN-bus reception processing in combination with UART of the serial
array unit.
The UART channel used for LIN-bus communication differs as follows depending on the product.
78K0R/KC3-L, 78K0R/KD3-L, 78K0R/KE3-L: UART0 of the serial array unit 0
78K0R/KF3-L, 78K0R/KG3-L:
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8.1 Functions of Timer Array Unit
Timer array unit has the following functions.
8.1.1 Independent channel operation function
By operating a channel independently, it can be used for the following purposes without being affected by the operation
mode of other channels.
(1) Interval timer
Each timer of a unit can be used as a reference timer that generates an interrupt (INTTMmn) at fixed intervals.
Operation clock
Compare operation
Channel n
Interrupt signal
(INTTMmn)
(2) Square wave output
A toggle operation is performed each time INTTMmn interrupt is generated and a square wave with a duty factor of
50% is output from a timer output pin (TOmn, SLTO).
Operation clock
Compare operation
Channel n
Timer output
(TOmn/SLTO)
(3) External event counter
Each timer of a unit can be used as an event counter that generates an interrupt when the number of the valid
edges of a signal input to the timer input pin (TImn, SLTI) has reached a specific value.
Timer input
(TImn/SLTI)
Edge detection
(4) Divider function
Compare operation
Interrupt signal
(INTTMmn)
Channel n
Note
A clock input from a timer input pin (TI00) is divided and output from an output pin (TO00).
Timer input
(TI00)
Capture operation
Channel 0
Timer output
(TO00)
(5) Input pulse interval measurement
Counting is started by the valid edge of a pulse signal input to a timer input pin (TImn, SLTI). The count value of
the timer is captured at the valid edge of the next pulse. In this way, the interval of the input pulse can be
measured.
Timer input
(TImn/SLTI)
Edge detection
Capture operation
Channel n
xxH
00H
Start Capture
(Note, Caution, and Remark are listed on the next page.)
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(6) Measurement of high-/low-level width of input signal
Counting is started by a single edge of the signal input to the timer input pin (TImn, SLTI), and the count value is
captured at the other edge. In this way, the high-level or low-level width of the input signal can be measured.
Edge detection
Capture operation
Timer input
(TImn/SLTI)
Channel n
00H xxH
Start Capture
Note Only channel 0 of timer array unit 0 in the 78K0R/KD3-L, 78K0R/KE3-L, 78K0R/KF3-L, and 78K0R/KG3-L.
Caution
Only the 78K0R/KC3-L (44-pin, 48-pin), 78K0R/KD3-L, and 78K0R/KE3-L include the SLTI and SLTO pins.
Remark
m: Unit number (m = 0, 1), n: Channel number (n = 0 to 7)
However, in case of the timer input pin (TImn) and the timer output pin (TOmn), mn changes as below.
78K0R/KC3-L (40-pin):
mn = 02 to 07
78K0R/KC3-L (44-pin, 48-pin):
mn = 00 to 07
78K0R/KD3-L, 78K0R/KE3-L:
mn = 00 to 07
78K0R/KF3-L, 78K0R/KG3-L:
mn = 00 to 07, 10 to 13
8.1.2 Simultaneous channel operation function
By using the combination of a master channel (a reference timer mainly controlling the cycle) and slave channels
(timers operating according to the master channel), channels can be used for the following purposes.
(1) One-shot pulse output
Two channels are used as a set to generate a one-shot pulse with a specified output timing and a specified pulse
width.
Compare operation
Timer input
(TImn/SLTI)
Edge detection
Interrupt signal (INTTMmn)
Channel n (master)
Compare operation
Channel p (slave)
Output
timing
Timer output
(TOmp)
Toggle
(Master)
Start
(Master)
Pulse width
Toggle
(Slave)
(2) PWM (Pulse Width Modulation) output
Two channels are used as a set to generate a pulse with a specified period and a specified duty factor.
Operation clock
Compare operation
Interrupt signal (INTTMmn)
Channel n (master)
Compare operation
Channel p (slave)
Timer output
(TOmp)
Duty
Period
(Cautions and Remark are listed on the next page.)
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(3) Multiple PWM (Pulse Width Modulation) output
By extending the PWM function and using one master channel and two or more slave channels, up to seven types
of PWM signals that have a specific period and a specified duty factor can be generated.
Operation clock
Compare operation
Interrupt signal (INTTMmn)
Channel n (master)
Compare operation
Channel p (slave)
Timer output
(TOmp)
Duty
Period
Compare operation
Channel q (slave)
Timer output
(TOmq)
Duty
Period
Cautions 1. The following rules apply when using multiple channels simultaneously.
• Only an even-numbered channel (channel 0, 2, 4, …) can be specified as the master channel.
• Only channels with lower channel numbers than the master channel can be specified as slave
channels (multiple slave channels can be set).
For details about the rules of simultaneous channel operation function, see 8.4 Basic Rules of
Simultaneous Channel Operation Function.
2. Only the 78K0R/KC3-L (44-pin, 48-pin), 78K0R/KD3-L, and 78K0R/KE3-L include the SLTI and SLTO
pins.
Remark
m: Unit number (m = 0, 1), n: Channel number (n = 0, 2, 4, 6)
78K0R/KC3-L, 78K0R/KD3-L, 78K0R/KE3-L: mn = 00, 02, 04, 06
78K0R/KF3-L, 78K0R/KG3-L:
mn = 00, 02, 04, 06, 10, 12
p: Slave channel number 1, q: Slave channel number 2Note
When m = 0: n < p < q ≤ 7
When m = 1: n < p < q ≤ 3
(Where p and q are a consecutive integer greater than n)
Note
Since there is no function of timer I/O, the channel 1 in the 78K0R/KC3-L (40-pin) can not be used as the
slave channel.
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8.1.3 LIN-bus supporting function (channel 7 only)
Timer array unit 0 is used to check whether signals received in LIN-bus communication match the LIN-bus
communication format.
(1) Detection of wakeup signal
The timer starts counting at the falling edge of a signal input to the serial data input pin (RxDk) of UARTk and the
count value of the timer is captured at the rising edge. In this way, a low-level width can be measured. If the lowlevel width is greater than a specific value, it is recognized as a wakeup signal.
(2) Detection of sync break field
The timer starts counting at the falling edge of a signal input to the serial data input pin (RxDk) of UARTk after a
wakeup signal is detected, and the count value of the timer is captured at the rising edge. In this way, a low-level
width is measured. If the low-level width is greater than a specific value, it is recognized as a sync break field.
(3) Measurement of pulse width of sync field
After a sync break field is detected, the low-level width and high-level width of the signal input to the serial data
input pin (RxDk) of UARTk are measured. From the bit interval of the sync field measured in this way, a baud rate
is calculated.
Remarks 1. The UART channel used for LIN-bus communication differs as follows depending on the product.
78K0R/KC3-L, 78K0R/KD3-L, 78K0R/KE3-L: k = 0 (UART0, RxD0 input pin)
78K0R/KF3-L, 78K0R/KG3-L:
k = 3 (UART3, RxD3 input pin)
2. For details about setting up the operations used to implement the LIN-bus, see 8.3 (13) Input switch
control register (ISC) and 8.7.5 Operation as input signal high-/low-level width measurement.
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8.2 Configuration of Timer Array Unit
Timer array unit includes the following hardware.
Table 8-1. Configuration of Timer Array Unit
Item
Configuration
78K0R/KC3-L, 78K0R/KD3-L, 78K0R/KE3-L
78K0R/KF3-L, 78K0R/KG3-L
Timer/counter
Timer/counter register mn (TCRmn)
Register
Timer data register mn (TDRmn)
Timer input
TI00 to TI07 (78K0R/KC3-L (40-pin) : TI02 to
Note 1
TI07), SLTI
pins, RxD0 pin (for LIN-bus)
TI00 to TI07, TI10 to TI13, RxD3 pin (for LINbus)
Timer output
TO00 to TO07(78K0R/KC3-L (40-pin) : TO02
Note 1
to TO07), SLTO
pins, output controller
TO00 to TO07, TO10 to TO13, output
controller
Control registers
<Registers of unit setting block>
Note 2
• Peripheral enable registers 0, 2 (PER0, PER2)
• Timer clock select register m (TPSm)
• Timer channel enable status register m (TEm)
• Timer channel start register m (TSm)
• Timer channel stop register m (TTm)
• Timer input select register m (TISm)
• Timer output enable register m (TOEm)
• Timer output register m (TOm)
• Timer output level register m (TOLm)
• Timer output mode register m (TOMm)
<Registers of each channel>
• Timer mode register mn (TMRmn)
• Timer status register mn (TSRmn)
• Input switch control register (ISC)
• Noise filter enable registers 1, 2 (NFEN1, NFEN2)
Note 3
• Port mode register (PMxx)
Note 3
• Port register (Pxx)
Notes 1. 40-pin product of the 78K0R/KC3-L does not have a SLTI and SLTO pins.
2. Set the PER2 register in the 78K0R/KC3-L, 78K0R/KD3-L, and 78K0R/KE3-L. Set the PER0 register in the
78K0R/KF3-L and 78K0R/KG3-L.
3. The port mode registers (PMxx) and port registers (Pxx) to be set differ depending on the product. for
details, see 8. 3 (15) Port mode registers 0, 1, 3 to 6, 13, 14 (PM0, PM1, PM3 to PM6, PM13, PM14).
Remark
m: Unit number (m = 0, 1), n: Channel number (n = 0 to 7)
78K0R/KC3-L, 78K0R/KD3-L, 78K0R/KE3-L: mn = 00 to 07
78K0R/KF3-L, 78K0R/KG3-L:
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The presence or absence of timer I/O pins in each timer array unit channel depends on the product.
Timer array
unit channels
I/O Pins of Each Product
KC3-L
KC3-L
KC3-L
(40-pin)
(44-pin)
(48-pin)
−
Channel 0
TAU1
TAU0
Channel 1
KD3-L
KE3-L
P00/TI00, P01/TO00
−
P52/SLTI/SLTO
Note
−
P52/SLTI/SLTO
Note
KF3-L
KG3-L
P52/TI00,
P00/TI00,
P01/TO00
P53/TO00
P16/TI01/TO01
Channel 2
P10/TI02/TO02
P17/TI02/TO02
Channel 3
P11/TI03/TO03
P31/TI03/TO03
Channel 4
P12/TI04/TO04
P42/TI04/TO04
Channel 5
P13/TI05/TO05
P05/TI05/TO05
P46/TI05/TO05
Channel 6
P50/TI06/TO06
P14/TI06/TO06
P06/TI06/TO06 P131/TI06/TO06
Channel 7
P51/TI07/TO07
P15/TI07/TO07
P54/TI07/TO07 P145/TI07/TO07
Channel 0
−
P64/TI10/TO10
Channel 1
−
P65/TI11/TO11
Channel 2
−
P66/TI12/TO12
Channel 3
−
P67/TI13/TO13
Note In the 78K0R/KC3-L (44-pin, 48-pin), 78K0R/KD3-L, and 78K0R/KE3-L, the P52/SLTI/SLTO pin can be used as the
timer I/O pin of channels 0 and 1. When using channel 0 in the 78K0R/KD3-L and 78K0R/KE3-L, the input switch
control register (ISC) can be used to select whether to use the P00/TI00, P01/TO00, and P52/SLTI/SLTO pins for
timer I/O. For details about the ISC register, see 8.3 (13) Input switch control register (ISC).
Caution Hereinafter, the timer I/O pins are described as TImn and TOmn (n = x), which also includes the selection
of the SLTI and SLTO pins.
Remarks 1. When timer input and timer output are shared by the same pin, either only timer input or only timer output
can be used.
2. The P52/SLTI/SLTO pin can only be assigned as the timer I/O pin for either channel 0 or channel 1. The
SLTI and SLTO pins cannot be selected as the timer I/O for channels 2 to 7.
Figures 8-1 to 8-5 show the block diagram.
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Figure 8-1. Entire Configuration of Timer Array Unit 0 (78K0R/KC3-L (40-pin))
Timer clock select register 0 (TPS0)
Peripheral enable
register 2 TAU0EN
(PER2)
PRS013 PRS012 PRS011 PRS010 PRS003 PRS002 PRS001 PRS000
4
4
fCLK
Prescaler
fCLK/20 to fCLK/215
Selector
fCLK/20 to fCLK/215
Selector
Slave/master controller
INTTM00
(Timer interrupt)
Channel 0
Channel 1
Slave/master controller
INTTM01
TO02
TI02
Channel 2
INTTM02
TO03
TI03
Channel 3
INTTM03
TO04
TI04
Channel 4
INTTM04
TO05
TI05
Channel 5
INTTM05
Channel 6
INTTM06
TO06
TI06
TO07
TI07
RxD0
(Serial input pin)
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INTTM07
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CHAPTER 8 TIMER ARRAY UNIT
Figure 8-2. Entire Configuration of Timer Array Unit 0 (78K0R/KC3-L (44-pin, 48-pin), 78K0R/KD3-L, 78K0R/KE3-L)
Timer clock select register 0 (TPS0)
Peripheral enable
register 2 TAU0EN
(PER2)
PRS013 PRS012 PRS011 PRS010 PRS003 PRS002 PRS001 PRS000
4
4
fCLK
Prescaler
fCLK/20 to fCLK/215
fCLK/20 to fCLK/215
Input switch control
register (ISC)
Selector
Selector
ISC2
Slave/master controller
Selector
Selector
Channel 0
Channel 1
ISC2 of ISC
register
INTTM00(Timer
interrupt)
TI00Note
SLTI
(Timer
input pin)
TO00Note
Slave/master controller
INTTM01
SLTO
(Timer
output pin)
TO02
TI02
Channel 2
INTTM02
TO03
TI03
Channel 3
INTTM03
TO04
TI04
Channel 4
INTTM04
TO05
TI05
Channel 5
INTTM05
Channel 6
INTTM06
TO06
TI06
TO07
TI07
RxD0
(Serial input pin)
Channel 7 (LIN-bus supported)
INTTM07
Note 78K0R/KD3-L and 78K0R/KE3-L only
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Figure 8-3. Entire Configuration of Timer Array Unit 0 (78K0R/KF3-L, 78K0R/KG3-L)
Timer clock select register 0 (TPS0)
Peripheral enable
register 0 TAU0EN
(PER0)
PRS013 PRS012 PRS011 PRS010 PRS003 PRS002 PRS001 PRS000
4
4
fCLK
Prescaler
fCLK/20 to fCLK/215
Selector
Slave/master controller
fCLK/20 to fCLK/215
Selector
TO00
INTTM00
(Timer interrupt)
TI00
Channel 0
TO01
TI01
Channel 1
Slave/master controller
INTTM01
TO02
TI02
Channel 2
INTTM02
TO03
TI03
Channel 3
INTTM03
TO04
TI04
Channel 4
INTTM04
TO05
TI05
Channel 5
INTTM05
TO06
TI06
Channel 6
INTTM06
TO07
TI07
RxD3
(Serial input pin)
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INTTM07
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CHAPTER 8 TIMER ARRAY UNIT
Figure 8-4. Entire Configuration of Timer Array Unit 1 (78K0R/KF3-L, 78K0R/KG3-L only)
Timer clock select register 1 (TPS1)
Peripheral enable
register 0 TAU1EN
(PER0)
PRS113 PRS112 PRS111 PRS110 PRS103 PRS102 PRS101 PRS100
4
4
fCLK
Prescaler
fCLK/20 to fCLK/215
fCLK/20 to fCLK/215
Selector
Selector
Slave/master controller
TO10
INTTM10
(Timer interrupt)
TI10
Channel 0
TO11
TI11
Channel 1
INTTM11
Slave/master controller
TO12
TI12
INTTM12
Channel 2
TO13
TI13
INTTM13
Channel 3
Figure 8-5. Internal Block Diagram of Channel of Timer Array Unit 0
Slave/master
controller
Operating
clock selection
CK01
Selector
fSUB/4
TI0n
fMCK
Edge
detection
fTCLK
Trigger
selection
CK00
Count clock
selection
Trigger signal to slave channel
Clock signal to slave channel
Interrupt signal to slave channel
Timer controller
Mode
selection
Output
controller
INTTM0n
(Timer interrupt)
Timer counter register 0n (TCR0n)
Timer status
register 0n (TSR0n)
Timer data register 0n (TDR0n)
Slave/master
controller
CKS0n CCS0n
Remark
PMxx
Interrupt
controller
TIS0n
Channel n
TO0n
Output latch
(Pxx)
Overflow
OVF
0n
MAS
STS0n2 STS0n1 STS0n0 CIS0n1 CIS0n0 MD0n3 MD0n2 MD0n1 MD0n0
TER0n
Timer mode register 0n (TMR0n)
n = 0 to 7
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CHAPTER 8 TIMER ARRAY UNIT
(1) Timer/counter register mn (TCRmn)
The TCRmn register is a 16-bit read-only register and is used to count clocks.
The value of this counter is incremented or decremented in synchronization with the rising edge of a count clock.
Whether the counter is incremented or decremented depends on the operation mode that is selected by the
MDmn3 to MDmn0 bits of timer mode register mn (TMRmn) (refer to 8.3 (3) Timer mode register mn (TMRmn)).
Figure 8-6. Format of Timer/Counter Register mn (TCRmn)
Address: F0180H, F0181H (TCR00) to F018EH, F018FH (TCR07)
After reset: FFFFH
R
F01C0H, F01C1H (TCR10) to F01C6H, F01C7H (TCR13)
F0181H (TCR00)
15
14
13
12
11
F0180H (TCR00)
10
9
8
7
6
5
4
3
2
1
0
TCRmn
Remark
m: Unit number (m = 0, 1), n: Channel number (n = 0 to 7)
78K0R/KC3-L, 78K0R/KD3-L, 78K0R/KE3-L: mn = 00 to 07
78K0R/KF3-L, 78K0R/KG3-L:
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The count value can be read by reading timer/counter register mn (TCRmn).
The count value is set to FFFFH in the following cases.
• When the reset signal is generated
• When the TAU0EN bit (in case of TAU0) or TAU1EN bit (in case of TAU1) of peripheral enable registers 0, 2
(PER0, PER2) are cleared
• When counting of the slave channel has been completed in the PWM output mode
• When counting of the master/slave channel has been completed in the one-shot pulse output mode
• When counting of the slave channel has been completed in the multiple PWM output mode
The count value is cleared to 0000H in the following cases.
• When the start trigger is input in the capture mode
• When capturing has been completed in the capture mode
Caution
The count value is not captured to timer data register mn (TDRmn) even when the TCRmn
register is read.
The TCRmn register read value differs as follows according to operation mode changes and the operating status.
Table 8-2. Timer/counter Register mn (TCRmn) Read Value in Various Operation Modes
Operation Mode
Count Mode
Timer/counter register mn (TCRmn) Read Value
Value if the
operation mode
was changed after
releasing reset
Interval timer
mode
Count down
Note
Value if the
operation mode was
changed after count
operation paused
(TTmn = 1)
Value if the
Operation was
restarted after count
operation paused
(TTmn = 1)
Value when waiting
for a start trigger
after one count
FFFFH
Undefined
Stop value
−
Capture mode
Count up
0000H
Undefined
Stop value
−
Event counter
mode
Count down
FFFFH
Undefined
Stop value
−
One-count mode
Count down
FFFFH
Undefined
Stop value
FFFFH
Capture & onecount mode
Count up
0000H
Undefined
Stop value
Capture value of
TDRmn register + 1
Note This indicates the value read from the TCRmn register when channel n has stopped operating as a timer (TEmn = 0)
and has been enabled to operate as a counter (TSmn = 1). The read value is held in the TCRmn register until the
count operation starts.
Remark
m: Unit number (m = 0, 1), n: Channel number (n = 0 to 7)
78K0R/KC3-L, 78K0R/KD3-L, 78K0R/KE3-L: mn = 00 to 07
78K0R/KF3-L, 78K0R/KG3-L:
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CHAPTER 8 TIMER ARRAY UNIT
(2) Timer data register mn (TDRmn)
This is a 16-bit register from which a capture function and a compare function can be selected.
The capture or compare function can be switched by selecting an operation mode by using the MDmn3 to MDmn0
bits of timer mode register mn (TMRmn).
The value of the TDRmn register can be changed at any time.
This register can be read or written in 16-bit units.
Reset signal generation clears this register to 0000H.
Figure 8-7. Format of Timer Data Register mn (TDRmn)
Address: FFF18H, FFF19H (TDR00), FFF1AH, FFF1BH (TDR01),
After reset: 0000H
R/W
FFF64H, FFF65H (TDR02) to FFF6EH, FFF6FH (TDR07)
FFF70H, FFF71H (TDR10) to FFF76H, FFF77H (TDR13)
FFF19H (TDR00)
15
14
13
12
11
FFF18H (TDR00)
10
9
8
7
6
5
4
3
2
1
0
TDRmn
(i) When timer data register mn (TDRmn) is used as compare register
Counting down is started from the value set to the TDRmn register. When the count value reaches 0000H, an
interrupt signal (INTTMmn) is generated. The TDRmn register holds its value until it is rewritten.
Caution
The TDRmn register does not perform a capture operation even if a capture trigger is input,
when it is set to the compare function.
(ii) When timer data register mn (TDRmn) is used as capture register
The count value of timer/counter register mn (TCRmn) is captured to the TDRmn register when the capture
trigger is input.
A valid edge of the TImn pin can be selected as the capture trigger. This selection is made by timer mode
register mn (TMRmn).
Remark
m: Unit number (m = 0, 1), n: Channel number (n = 0 to 7)
However, in case of the timer input pin (TImn), mn changes as below.
78K0R/KC3-L (40-pin):
mn = 02 to 07
78K0R/KC3-L (44-pin, 48-pin):
mn = 00 to 07
78K0R/KD3-L, 78K0R/KE3-L:
mn = 00 to 07
78K0R/KF3-L, 78K0R/KG3-L:
mn = 00 to 07, 10 to 13
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8.3 Registers Controlling Timer Array Unit
Timer array unit is controlled by the following registers.
• Peripheral enable registers 0, 2 (PER0, PER2)
Note 1
• Timer clock select register m (TPSm)
• Timer mode register mn (TMRmn)
• Timer status register mn (TSRmn)
• Timer channel enable status register m (TEm)
• Timer channel start register m (TSm)
• Timer channel stop register m (TTm)
• Timer input select register m (TISm)
• Timer output enable register m (TOEm)
• Timer output register m (TOm)
• Timer output level register m (TOLm)
• Timer output mode register m (TOMm)
• Input switch control register (ISC)
• Noise filter enable registers 1, 2 (NFEN1, NFEN2)
• Port mode register (PMxx)
• Port register (Pxx)
Note 2
Note 2
Notes 1. Set the PER2 register in the 78K0R/KC3-L, 78K0R/KD3-L, and 78K0R/KE3-L. Set the PER0 register in the
78K0R/KF3-L and 78K0R/KG3-L.
2. The port mode registers (PMxx) and port registers (Pxx) to be set differ depending on the product. for
details, see 8. 3 (15) Port mode registers 0, 1, 3 to 6, 13, 14 (PM0, PM1, PM3 to PM6, PM13, PM14).
Remark
m: Unit number (m = 0, 1), n: Channel number (n = 0 to 7)
78K0R/KC3-L, 78K0R/KD3-L, 78K0R/KE3-L: mn = 00 to 07
78K0R/KF3-L, 78K0R/KG3-L:
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(1) Peripheral enable registers 0, 2 (PER0, PER2)
These registers are used to enable or disable supplying the clock to the peripheral hardware. Clock supply to a
hardware macro that is not used is stopped in order to reduce the power consumption and noise.
When the timer array unit is used, be sure to set the following bits to 1.
• 78K0R/KC3-L, 78K0R/KD3-L, 78K0R/KE3-L
When timer array unit 0 is used → Bit 0 (TAU0EN) of the PER2 register
• 78K0R/KF3-L, 78K0R/KG3-L
When timer array unit 0 is used → Bit 0 (TAU0EN) of the PER0 register
When timer array unit 1 is used → Bit 1 (TAU1EN) of the PER0 register
The PER0 and PER2 registers can be set by a 1-bit or 8-bit memory manipulation instruction.
Reset signal generation clears these registers to 00H.
Figure 8-8. Format of Peripheral Enable Register 0 (PER0) (78K0R/KF3-L, 78K0R/KG3-L)
Address: F00F0H
After reset: 00H
R/W
Symbol
<7>
6
<5>
<4>
<3>
<2>
<1>
<0>
PER0
RTCEN
0
ADCEN
IICAEN
SAU1EN
SAU0EN
TAU1EN
TAU0EN
TAUmEN
0
Control of timer array unit m input clock (m = 0, 1)
Stops supply of input clock.
• SFR used by the timer array unit m cannot be written.
• The timer array unit m is in the reset status.
1
Supplies input clock.
• SFR used by the timer array unit m can be read/written.
Cautions 1. When setting the timer array unit m, be sure to set the TAU0EN and TAU1EN bits to 1
first. If TAU0EN, TAU1EN = 0, writing to a control register of timer array unit m is ignored,
and all read values are default values (except for the timer input select register m (TISm),
input switch control register (ISC), noise filter enable registers 1, 2 (NFEN1, NFEN2), port
mode registers 0, 1, 3, 4, 6, 13, 14 (PM0, PM1, PM3, PM4, PM6, PM13, PM14), and port
registers 0, 1, 3, 4, 6, 13, 14 (P0, P1, P3, P4, P6, P13, P14)).
2. Be sure to clear bit 6 to 0.
Remark m = 0, 1
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CHAPTER 8 TIMER ARRAY UNIT
Figure 8-9. Format of Peripheral Enable Register 2 (PER2) (78K0R/KC3-L, 78K0R/KD3-L, 78K0R/KE3-L)
Address: F00F2H
After reset: 00H
R/W
Symbol
7
6
5
4
3
2
1
<0>
PER2
0
0
0
0
0
0
0
TAU0EN
TAU0EN
0
Control of timer array unit 0 input clock supply
Stops input clock supply.
• SFR used by timer array unit 0 cannot be written.
• Timer array unit 0 is in the reset status.
1
Enables input clock supply.
• SFR used by timer array unit 0 can be read/written.
Cautions 1. When setting timer array unit 0, be sure to set TAU0EN to 1 first. If TAU0EN = 0, writing to a
control register of timer array unit 0 is ignored, and all read values are default values (except
for timer input select register 0 (TIS0), input switch control register (ISC), noise filter enable
registers 1, 2 (NFEN1, 2), port mode registers 0, 1, 5 (PM0, PM1, PM5), and port registers 0, 1, 5
(P0, P1, P5)).
2. Be sure to clear bits 1 to 7 of the PER2 register to 0.
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(2) Timer clock select register m (TPSm)
The TPSm register is a 16-bit register that is used to select two types of operation clocks (CKm0, CKm1) that are
commonly supplied to each channel. CKm1 is selected by bits 7 to 4 of the TPSm register, and CKm0 is selected
by bits 3 to 0.
Rewriting of the TPSm register during timer operation is possible only in the following cases.
If the PRSm00 to PRSm03 bits can be rewritten:
All channels for which CKm0 is selected as the operation clock (CKSmn = 0) are stopped (TEmn = 0).
If the PRSm10 to PRSm13 bits can be rewritten:
All channels for which CKm1 is selected as the operation clock (CKSmn = 1) are stopped (TEmn = 0).
The TPSm register can be set by a 16-bit memory manipulation instruction.
The lower 8 bits of the TPSm register can be set with an 8-bit memory manipulation instruction with TPSmL.
Reset signal generation clears this register to 0000H.
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CHAPTER 8 TIMER ARRAY UNIT
Figure 8-10. Format of Timer Clock Select register m (TPSm)
Address: F01B6H, F01B7H (TPS0)
After reset: 0000H
R/W
F01DEH, F01DFH (TPS1)
Symbol
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
TPSm
0
0
0
0
0
0
0
0
PRS
PRS
PRS
PRS
PRS
PRS
PRS
PRS
m13
m12
m11
m10
m03
m02
m01
m00
PRS
PRS
PRS
PRS
mk3
mk2
mk1
mk0
0
0
0
0
fCLK
0
0
0
1
fCLK/2
0
0
0
0
0
1
1
1
1
0
0
0
1
0
1
fCLK = 2 MHz
fCLK = 5 MHz
Note
fCLK = 10 MHz
fCLK = 20 MHz
2 MHz
5 MHz
10 MHz
20 MHz
1 MHz
2.5 MHz
5 MHz
10 MHz
fCLK/2
2
500 kHz
1.25 MHz
2.5 MHz
5 MHz
fCLK/2
3
250 kHz
625 kHz
1.25 MHz
2.5 MHz
fCLK/2
4
125 kHz
312.5 kHz
625 kHz
1.25 MHz
fCLK/2
5
62.5 kHz
156.2 kHz
312.5 kHz
625 kHz
0
1
1
0
fCLK/2
6
31.25 kHz
78.1 kHz
156.2 kHz
312.5 kHz
0
1
1
1
fCLK/2
7
15.62 kHz
39.1 kHz
78.1 kHz
156.2 kHz
fCLK/2
8
7.81 kHz
19.5 kHz
39.1 kHz
78.1 kHz
fCLK/2
9
3.91 kHz
9.76 kHz
19.5 kHz
39.1 kHz
fCLK/2
10
1.95 kHz
4.88 kHz
9.76 kHz
19.5 kHz
fCLK/2
11
976 Hz
2.44 kHz
4.88 kHz
9.76 kHz
fCLK/2
12
488 Hz
1.22 kHz
2.44 kHz
4.88 kHz
fCLK/2
13
244 Hz
610 Hz
1.22 kHz
2.44 kHz
122 Hz
305 Hz
610 Hz
1.22 kHz
61 Hz
153 Hz
305 Hz
610 Hz
1
1
1
1
1
1
Note
0
Selection of operation clock (CKmk)
0
0
0
0
1
1
0
0
1
1
0
0
0
1
0
1
0
1
1
1
1
0
fCLK/2
14
1
1
1
1
fCLK/2
15
When changing the clock selected for fCLK (by changing the system clock control register (CKC)
value), stop timer array unit (TTm = 00FFH).
The timer array unit must also be stopped if the operating clock specified by using the CKSmn bit
(fMCK), the valid edge of the signal input from the TImn pin, or the subsystem clock divided by 4
(fSUB/4) is selected as the count clock (fTCLK).
Caution
Be sure to clear bits 15 to 8 to “0”.
Remarks 1. fCLK: CPU/peripheral hardware clock frequency
2. m: Unit number (m = 0, 1), k = 0, 1
78K0R/KC3-L, 78K0R/KD3-L, 78K0R/KE3-L: m = 0
78K0R/KF3-L, 78K0R/KG3-L:
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CHAPTER 8 TIMER ARRAY UNIT
(3) Timer mode register mn (TMRmn)
The TMRmn register sets an operation mode of channel n. It is used to select an operation clock (fMCK), a count
clock, whether the timer operates as the master or a slave, a start trigger and a capture trigger, the valid edge of
the timer input, and an operation mode (interval, capture, event counter, one-count, or capture & one-count).
Rewriting the TMRmn register is prohibited when the register is in operation (when TEmn = 1). However, bits 7 and
6 (CISmn1, CISmn0) can be rewritten even while the register is operating with some functions (when TEmn = 1)
(for details, see 8.7 Independent Channel Operation Function of Timer Array Unit and 8.8 Simultaneous
Channel Operation Function of Timer Array Unit.
The TMRmn register can be set by a 16-bit memory manipulation instruction.
Reset signal generation clears this register to 0000H.
Figure 8-11. Format of Timer Mode Register mn (TMRmn) (1/3)
Address: F0190H, F0191H (TMR00) to F019EH, F019FH (TMR07)
After reset: 0000H
R/W
F01C8H, F01C9H (TMR10) to F01CEH, F01CFH (TMR13)
Symbol
15
14
13
12
11
10
9
8
TMRmn
CKS
0
0
CCS
MAST
STS
STS
STS
mn
ERmn
mn2
mn1
mn0
mn
CKS
7
6
5
4
CIS
CIS
0
0
mn1
mn0
3
2
1
0
MD
MD
MD
MD
mn3
mn2
mn1
mn0
Selection of operation clock (fMCK) of channel n
mn
0
Operation clock CKm0 set by timer clock select register m (TPSm)
1
Operation clock CKm1 set by timer clock select register m (TPSm)
Operation clock (fMCK ) is used by the edge detector. A count clock (fTCLK) and a sampling clock are generated
depending on the setting of the CCSmn bit.
CCS
Selection of count clock (fTCLK) of channel n
mn
0
Operation clock (fMCK) specified by the CKSmn bit
1
Valid edge of input signal input from the TImn pin/subsystem clock divided by 4 (fSUB/4)
Note
Count clock (fTCLK) is used for the timer/counter, output controller, and interrupt controller.
Note The 78K0R/KC3-L (40-pin) doesn’t have the subsystem clock.
Cautions 1. Be sure to clear bits 14, 13, 5, and 4 to “0”.
2. The timer array unit must be stopped (TTm = 00FFH) if the clock selected for fCLK is changed
(by changing the value of the system clock control register (CKC)), even if the operating clock
specified by using the CKSmn bit (fMCK), the valid edge of the signal input from the TImn pin,
or the subsystem clock divided by 4 (fSUB/4) is selected as the count clock (fTCLK).
Remark
m: Unit number (m = 0, 1), n: Channel number (n = 0 to 7)
However, in case of the timer input pin (TImn), mn changes as below.
78K0R/KC3-L (40-pin):
mn = 02 to 07
78K0R/KC3-L (44-pin, 48-pin):
mn = 00 to 07
78K0R/KD3-L, 78K0R/KE3-L:
mn = 00 to 07
78K0R/KF3-L, 78K0R/KG3-L:
mn = 00 to 07, 10 to 13
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Figure 8-11. Format of Timer Mode Register mn (TMRmn) (2/3)
Address: F0190H, F0191H (TMR00) to F019EH, F019FH (TMR07)
After reset: 0000H
R/W
F01C8H, F01C9H (TMR10) to F01CEH, F01CFH (TMR13)
Symbol
15
14
13
12
11
10
9
8
TMRmn
CKS
0
0
CCS
MAST
STS
STS
STS
mn
ERmn
mn2
mn1
mn0
mn
7
6
5
4
CIS
CIS
0
0
mn1
mn0
3
2
1
0
MD
MD
MD
MD
mn3
mn2
mn1
mn0
MAS
Selection between using channel n independently or
TER
simultaneously with another channel(as a slave or master)
mn
Operates in independent channel operation function or as slave channel in simultaneous channel operation
0
function.
1
Operates as master channel in simultaneous channel operation function.
Only the even channel can be set as a master channel (MASTERmn = 1).
Be sure to use odd-numbered channels as slave channels (MASTERmn = 0).
Clear the MASTERmn bit to 0 for a channel that is used with the independent channel operation function.
STS
STS
STS
mn2
mn1
mn0
0
0
0
Only software trigger start is valid (other trigger sources are unselected).
0
0
1
Valid edge of the TImn pin input is used as both the start trigger and capture trigger.
0
1
0
Both the edges of the TImn pin input are used as a start trigger and a capture trigger.
1
0
0
Interrupt signal of the master channel is used (when the channel is used as a slave channel
Setting of start trigger or capture trigger of channel n
with the simultaneous channel operation function).
Other than above
Setting prohibited
CIS
CIS
mn1
mn0
0
0
Falling edge
0
1
Rising edge
1
0
Both edges (when low-level width is measured)
Selection of TImn pin input valid edge
Start trigger: Falling edge, Capture trigger: Rising edge
1
1
Both edges (when high-level width is measured)
Start trigger: Rising edge, Capture trigger: Falling edge
If both the edges are specified when the value of the STSmn2 to STSmn0 bits is other than 010B, set the CISmn1
to CISmn0 bits to 10B.
Remark
m: Unit number (m = 0, 1), n: Channel number (n = 0 to 7)
However, in case of the timer input pin (TImn), mn changes as below.
78K0R/KC3-L (40-pin):
mn = 02 to 07
78K0R/KC3-L (44-pin, 48-pin):
mn = 00 to 07
78K0R/KD3-L, 78K0R/KE3-L:
mn = 00 to 07
78K0R/KF3-L, 78K0R/KG3-L:
mn = 00 to 07, 10 to 13
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Figure 8-11. Format of Timer Mode Register mn (TMRmn) (3/3)
Address: F0190H, F0191H (TMR00) to F019EH, F019FH (TMR07)
After reset: 0000H
R/W
F01C8H, F01C9H (TMR10) to F01CEH, F01CFH (TMR13)
Symbol
15
14
13
12
11
10
9
8
TMRmn
CKS
0
0
CCS
MAST
STS
STS
STS
mn
ERmn
mn2
mn1
mn0
mn
7
6
5
4
CIS
CIS
0
0
mn1
mn0
3
2
1
MD
MD
MD
MD
mn3
mn2
mn1
mn0
MD
MD
MD
MD
mn3
mn2
mn1
mn0
0
0
0
1/0
Interval timer mode
Counting down
Possible
0
1
0
1/0
Capture mode
Counting up
Possible
0
1
1
0
Event counter mode
Counting down
Possible
1
0
0
1/0
One-count mode
Counting down
Impossible
1
1
0
0
Capture & one-count mode
Counting up
Possible
Other than above
Operation mode of channel n
0
Count operation of TCR
Independent operation
Setting prohibited
The operation of the MDmn0 bit varies depending on each operation mode (see table below).
Operation mode
MD
(Value set by the MDmn3 to MDmn1 bits
mn0
Setting of starting counting and interrupt
(see table above))
• Interval timer mode
0
Timer interrupt is not generated when counting is started
(timer output does not change, either).
(0, 0, 0)
• Capture mode
1
(0, 1, 0)
Timer interrupt is generated when counting is started
(timer output also changes).
• Event counter mode
0
Timer interrupt is not generated when counting is started
0
Start trigger is invalid during counting operation.
(timer output does not change, either).
(0, 1, 1)
• One-count mode
Note 1
At that time, interrupt is not generated, either.
(1, 0, 0)
1
Note 2
Start trigger is valid during counting operation
.
At that time, interrupt is also generated.
• Capture & one-count mode
0
Timer interrupt is not generated when counting is started
(timer output does not change, either).
(1, 1, 0)
Start trigger is invalid during counting operation.
At that time interrupt is not generated, either.
Other than above
Setting prohibited
Notes 1. In one-count mode, interrupt output (INTTMmn) when starting a count operation and TOmn output are not
controlled.
2. If the start trigger (TSmn = 1) is issued during operation, the counter is cleared, an interrupt is generated,
and recounting is started.
Remark
m: Unit number (m = 0, 1), n: Channel number (n = 0 to 7)
However, in case of the timer output pin (TOmn), mn changes as below.
78K0R/KC3-L (40-pin):
mn = 02 to 07
78K0R/KC3-L (44-pin, 48-pin):
mn = 00 to 07
78K0R/KD3-L, 78K0R/KE3-L:
mn = 00 to 07
78K0R/KF3-L, 78K0R/KG3-L:
mn = 00 to 07, 10 to 13
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(4) Timer status register mn (TSRmn)
The TSRmn register indicates the overflow status of the counter of channel n.
The TSRmn register is valid only in the capture mode (MDmn3 to MDmn1 = 010B) and capture & one-count mode
(MDmn3 to MDmn1 = 110B). It will not be set in any other mode. See Table 8-3 for the operation of the OVF bit in
each operation mode and set/clear conditions.
The TSRmn register can be read by a 16-bit memory manipulation instruction.
The lower 8 bits of the TSRmn register can be set with an 8-bit memory manipulation instruction with TSRmnL.
Reset signal generation clears this register to 0000H.
Figure 8-12. Format of Timer Status Register mn (TSRmn)
Address: F01A0H, F01A1H (TSR00) to F01AEH, F01AFH (TSR07)
After reset: 0000H
R
F01D0H, F01D1H (TSR10) to F01D6H, F01D7H (TSR13)
Symbol
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
TSRmn
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
OVF
OVF
Counter overflow status of channel n
0
Overflow does not occur.
1
Overflow occurs.
When OVF = 1, this flag is cleared (OVF = 0) when the next value is captured without overflow.
Remark
m: Unit number (m = 0, 1), n: Channel number (n = 0 to 7)
78K0R/KC3-L, 78K0R/KD3-L, 78K0R/KE3-L: mn = 00 to 07
78K0R/KF3-L, 78K0R/KG3-L:
mn = 00 to 07, 10 to 13
Table 8-3. OVF Bit Operation and Set/Clear Conditions in Each Operation Mode
Timer operation mode
OVF bit
Set/clear conditions
• Capture mode
clear
When no overflow has occurred upon capturing
• Capture & one-count mode
set
When an overflow has occurred upon capturing
• Interval timer mode
clear
• Event counter mode
• One-count mode
Remark
set
−
(Use prohibited, not set and not cleared)
The OVF bit does not change immediately after the counter has overflowed, but changes upon the
subsequent capture.
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(5) Timer channel enable status register m (TEm)
The TEm register is used to enable or stop the timer operation of each channel.
When a bit of timer channel start register m (TSm) is set to 1, the corresponding bit of this register is set to 1.
When a bit of timer channel stop register m (TTm) is set to 1, the corresponding bit of this register is cleared to 0.
The TEm register can be read by a 16-bit memory manipulation instruction.
The lower 8 bits of the TEm register can be set with a 1-bit or 8-bit memory manipulation instruction with TEmL.
Reset signal generation clears this register to 0000H.
Figure 8-13. Format of Timer Channel Enable Status register m (TEm)
Address: F01B0H, F01B1H
After reset: 0000H
R
Symbol
15
14
13
12
11
10
9
8
TE0
0
0
0
0
0
0
0
0
Address: F01D8H, F01D9H
After reset: 0000H
7
6
5
4
1
0
R
15
14
13
12
11
10
9
8
7
6
5
4
TE1
0
0
0
0
0
0
0
0
0
0
0
0
3
2
1
0
TE13 TE12 TE11 TE10
Indication of operation enable/stop status of channel n
0
Operation is stopped.
1
Operation is enabled.
Remark
2
TE07 TE06 TE05 TE04 TE03 TE02 TE01 TE00
Symbol
TEmn
3
m: Unit number (m = 0, 1), n: Channel number (n = 0 to 7)
78K0R/KC3-L, 78K0R/KD3-L, 78K0R/KE3-L: mn = 00 to 07
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(6) Timer channel start register m (TSm)
The TSm register is a trigger register that is used to clear timer/counter register mn (TCRmn) and start the counting
operation of each channel.
When a bit (TSmn) of this register is set to 1, the corresponding bit (TEmn) of timer channel enable status register
m (TEm) is set to 1. The TSmn bit is immediately cleared when operation is enabled (TEmn = 1), because it is a
trigger bit.
The TSm register can be set by a 16-bit memory manipulation instruction.
The lower 8 bits of the TSm register can be set with a 1-bit or 8-bit memory manipulation instruction with TSmL.
Reset signal generation clears this register to 0000H.
Figure 8-14. Format of Timer Channel Start register m (TSm)
Address: F01B2H, F01B3H
After reset: 0000H
R/W
Symbol
15
14
13
12
11
10
9
8
TS0
0
0
0
0
0
0
0
0
Address: F01DAH, F01DBH
After reset: 0000H
R/W
7
6
5
4
2
1
0
TS07 TS06 TS05 TS04 TS03 TS02 TS01 TS00
Symbol
15
14
13
12
11
10
9
8
7
6
5
4
TS1
0
0
0
0
0
0
0
0
0
0
0
0
TSm
3
3
2
1
0
TS13 TS12 TS11 TS10
Operation enable (start) trigger of channel n
n
0
No trigger operation
1
The TEmn bit is set to 1 and the count operation becomes enabled.
The TCRmn register count operation start in the count operation enabled state varies depending on each
operation mode (see Table 8-4).
Caution
Be sure to clear bits 15 to 8 of the TS0 register and bits 15 to 4 of the TS1 register to “0”
Remarks 1. When the TSm register is read, 0 is always read.
2. m: Unit number (m = 0, 1), n: Channel number (n = 0 to 7)
78K0R/KC3-L, 78K0R/KD3-L, 78K0R/KE3-L: mn = 00 to 07
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Table 8-4. Operations from Count Operation Enabled State to Timer/counter Register mn (TCRmn) Count Start
Timer operation mode
• Interval timer mode
Operation when TSmn = 1 is set
No operation is carried out from start trigger detection (TSmn=1) until count clock
generation.
The first count clock loads the value of the TDRmn register to the TCRmn
register and the subsequent count clock performs count down operation (see 8.3
(6) (a) Start timing in interval timer mode).
• Event counter mode
Writing 1 to the TSmn bit loads the value of the TDRmn register to the TCRmn
register.
The subsequent count clock performs count down operation.
The external trigger detection selected by the STSmn2 to STSmn0 bits in the
TMRmn register does not start count operation (see 8.3 (6) (b) Start timing in
event counter mode).
• Capture mode
No operation is carried out from start trigger detection until count clock
generation.
The first count clock loads 0000H to the TCRmn register and the subsequent
count clock performs count up operation (see 8.3 (6) (c) Start timing in capture
mode).
• One-count mode
The waiting-for-start-trigger state is entered by writing 1 to the TSmn bit while the
timer is stopped (TEmn = 0).
No operation is carried out from start trigger detection until count clock
generation.
The first count clock loads the value of the TDRmn register to the TCRmn
register and the subsequent count clock performs count down operation (see 8.3
(6) (d) Start timing in one-count mode).
• Capture & one-count mode
The waiting-for-start-trigger state is entered by writing 1 to the TSmn bit while the
timer is stopped (TEmn = 0).
No operation is carried out from start trigger detection until count clock
generation.
The first count clock loads 0000H to the TCRmn register and the subsequent
count clock performs count up operation (see 8.3 (6) (e) Start timing in capture
& one-count mode).
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(a) Start timing in interval timer mode
<1> Operation is enabled (TEmn = 1) by writing 1 to the TSmn bit.
<2> The write data to the TSmn bit is held until count clock generation.
<3> Timer/counter register mn (TCRmn) holds the initial value until count clock generation.
<4> On generation of count clock, the value of timer data register mn (TDRmn) is loaded to the TCRmn
register and count starts.
Figure 8-15. Start Timing (In Interval Timer Mode)
fCLK
TSmn (write)
TEmn
<1>
Count clock
TSmn (write) hold signal
<2>
Start trigger detection signal
TCRmn
<3>
Initial value
<4>
TDRmn value
INTTMmn
When MDmn0 = 1 is set
Caution In the first cycle operation of count clock after writing the TSmn bit, an error at a maximum of one
clock is generated since count start delays until count clock has been generated. When the
information on count start timing is necessary, an interrupt can be generated at count start by
setting MDmn0 = 1.
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(b) Start timing in event counter mode
<1> Timer/counter register mn (TCRmn) holds its initial value while operation is stopped (TEmn = 0).
<2> Operation is enabled (TEmn = 1) by writing 1 to the TSmn bit.
<3> As soon as 1 has been written to the TSmn bit and 1 has been set to the TEmn bit, the value of timer data
register mn (TDRmn) is loaded to the TCRmn register to start counting.
<4> After that, the TCRmn register value is counted down according to the count clock.
Figure 8-16. Start Timing (In Event Counter Mode)
fCLK
TSmn (write)
TEmn
<1>
<2>
Count clock
TSmn (write) hold signal
Start trigger detection signal
TCRmn
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Initial value
<3>
TDRmn value
TDRmn value-1
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CHAPTER 8 TIMER ARRAY UNIT
(c) Start timing in capture mode
<1> Operation is enabled (TEmn = 1) by writing 1 to the TSmn bit.
<2> The write data to the TSmn bit is held until count clock generation.
<3> Timer/counter register mn (TCRmn) holds the initial value until count clock generation.
<4> On generation of count clock, 0000H is loaded to the TCRmn register and count starts.
Figure 8-17. Start Timing (In Capture Mode)
fCLK
TSmn (write)
TEmn
<1>
Count clock
TSmn (write) hold signal
<2>
Start trigger detection signal
TCRmn
<3>
Initial value
<4>
0000H
INTTMmn
When MDmn0 = 1 is set
Caution In the first cycle operation of count clock after writing the TSmn bit, an error at a maximum of one
clock is generated since count start delays until count clock has been generated. When the
information on count start timing is necessary, an interrupt can be generated at count start by
setting MDmn0 = 1.
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(d) Start timing in one-count mode
<1> Operation is enabled (TEmn = 1) by writing 1 to the TSmn bit.
<2> Enters the start trigger input wait status, and timer/counter register mn (TCRmn) holds the initial value.
<3> On start trigger detection, the value of timer data register mn (TDRmn) is loaded to the TCRmn register and
count starts.
Figure 8-18. Start Timing (In One-count Mode)
fCLK
TSmn (write)
<1>
TEmn
TImn edge detection signal
Count clock Note
TSmn (write) hold signal
Start trigger detection signal
TCRmn
<2>
Initial value
<3>
TDRmn value
Start trigger input wait status
Note When the one-count mode is set, the operation clock (fMCK) is selected as count clock (CCSmn = 0).
Caution An input signal sampling error is generated since operation starts upon start trigger detection (If
the TImn pin input signal is used as a start trigger, an error of one count clock occurs.).
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(e) Start timing in capture & one-count mode
<1> Operation is enabled (TEmn = 1) by writing 1 to the TSmn bit.
<2> Enters the start trigger input wait status, and timer/counter register mn (TCRmn) holds the initial value.
<3> On start trigger detection, 0000H is loaded to the TCRmn register and count starts.
Figure 8-19. Start Timing (In Capture & One-count Mode)
fCLK
TSmn (write)
<1>
TEmn
TImn edge detection signal
Count clock Note
TSmn (write) hold signal
Start trigger detection signal
TCRmn
<2>
Initial value
<3>
0000H
Start trigger input wait status
Note When the capture & one-count mode is set, the operation clock (fMCK) is selected as count clock (CCSmn =
0).
Caution An input signal sampling error is generated since operation starts upon start trigger detection (If
the TImn pin input signal is used as a start trigger, an error of one count clock occurs.)
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(7) Timer channel stop register m (TTm)
The TTm register is a trigger register that is used to clear timer/counter register mn (TCRmn) and start the counting
operation of each channel.
When a bit (TTmn) of this register is set to 1, the corresponding bit (TEmn) of timer channel enable status register
m (TEm) is cleared to 0. The TTmn bit is immediately cleared when operation is stopped (TEmn = 0), because it is
a trigger bit.
The TTm register can be set by a 16-bit memory manipulation instruction.
The lower 8 bits of the TTm register can be set with a 1-bit or 8-bit memory manipulation instruction with TTmL.
Reset signal generation clears this register to 0000H.
Figure 8-20. Format of Timer Channel Stop register m (TTm)
Address: F01B4H, F01B5H
After reset: 0000H
R/W
Symbol
15
14
13
12
11
10
9
8
TT0
0
0
0
0
0
0
0
0
Address: F01DCH, F01DDH
After reset: 0000H
R/W
7
6
5
4
2
1
0
TT07 TT06 TT05 TT04 TT03 TT02 TT01 TT00
Symbol
15
14
13
12
11
10
9
8
7
6
5
4
TT1
0
0
0
0
0
0
0
0
0
0
0
0
TTm
3
3
2
1
0
TT13 TT12 TT11 TT10
Operation stop trigger of channel n
n
0
No trigger operation
1
Operation is stopped (stop trigger is generated).
Caution
Be sure to clear bits 15 to 8 of the TT0 register and bits 15 to 4 of the TT1 register to “0”.
Remarks 1. When the TTm register is read, 0 is always read.
2. m: Unit number (m = 0, 1), n: Channel number (n = 0 to 7)
78K0R/KC3-L, 78K0R/KD3-L, 78K0R/KE3-L: mn = 00 to 07
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(8) Timer input select register m (TISm)
The TISm register is used to select whether a signal input to the timer input pin (TImn) or the subsystem clock
Note
divided by four (fSUB/4)
is valid for each channel.
The TISm register can be set by a 1-bit or 8-bit memory manipulation instruction.
Reset signal generation clears this register to 00H.
Note The 78K0R/KC3-L (40-pin) doesn’t have the subsystem clock.
Figure 8-21. Format of Timer Input Select register m (TISm)
Address: FFF3EH
After reset: 00H
R/W
Symbol
7
6
5
4
3
2
1
0
TIS0
TIS07
TIS06
TIS05
TIS04
TIS03
TIS02
TIS01
TIS00
Address: FFF3FH
After reset: 00H
R/W
Symbol
7
6
5
4
3
2
1
0
TIS1
0
0
0
0
TIS13
TIS12
TIS11
TIS10
TISmn
Selection of timer input/subsystem clock used with channel n
0
Input signal of timer input pin (TImn)
1
Subsystem clock divided by 4 (fSUB/4)
Note
Note
The 78K0R/KC3-L (40-pin) doesn’t have the subsystem clock.
Remark
m: Unit number (m = 0, 1), n: Channel number (n = 0 to 7)
However, in case of the timer input pin (TImn), mn changes as below.
78K0R/KC3-L (40-pin):
mn = 02 to 07
78K0R/KC3-L (44-pin, 48-pin):
mn = 00 to 07
78K0R/KD3-L, 78K0R/KE3-L:
mn = 00 to 07
78K0R/KF3-L, 78K0R/KG3-L:
mn = 00 to 07, 10 to 13
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(9) Timer output enable register m (TOEm)
The TOEm register is used to enable or disable timer output of each channel.
Channel n for which timer output has been enabled becomes unable to rewrite the value of the TOmn bit of timer
output register m (TOm) described later by software, and the value reflecting the setting of the timer output function
through the count operation is output from the timer output pin (TOmn).
The TOEm register can be set by a 16-bit memory manipulation instruction.
The lower 8 bits of the TOEm register can be set with a 1-bit or 8-bit memory manipulation instruction with TOEmL.
Reset signal generation clears this register to 0000H.
Figure 8-22. Format of Timer Output Enable register m (TOEm)
Address: F01BAH, F01BBH
After reset: 0000H
R/W
Symbol
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
TOE0
0
0
0
0
0
0
0
0
TOE
TOE
TOE
TOE
TOE
TOE
TOE
TOE
07
06
05
04
03
02
01
00
Address: F01E2H, F01E3H
After reset: 0000H
R/W
Symbol
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
TOE1
0
0
0
0
0
0
0
0
0
0
0
0
TOE
TOE
TOE
TOE
13
12
11
10
TOE
Timer output enable/disable of channel n
mn
0
The TOmn operation stopped by count operation (timer channel output bit).
Writing to the TOmn bit is enabled.
The TOmn pin functions as data output, and it outputs the level set to the TOmn bit.
The output level of the TOmn pin can be manipulated by software.
1
The TOmn operation enabled by count operation (timer channel output bit).
Writing to the TOmn bit is disabled (writing is ignored).
The TOmn pin functions as timer output, and the TOEmn bit is set or reset depending on the timer
operation.
The TOmn pin outputs the square-wave or PWM depending on the timer operation.
Caution
Be sure to clear bits 15 to 8 of the TOE0 register and bits 15 to 4 of the TOE1 register to “0”.
Remark
m: Unit number (m = 0, 1), n: Channel number (n = 0 to 7)
However, in case of the timer output pin (TOmn), mn changes as below.
78K0R/KC3-L (40-pin):
mn = 02 to 07
78K0R/KC3-L (44-pin, 48-pin):
mn = 00 to 07
78K0R/KD3-L, 78K0R/KE3-L:
mn = 00 to 07
78K0R/KF3-L, 78K0R/KG3-L:
mn = 00 to 07, 10 to 13
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(10) Timer output register m (TOm)
The TOm register is a buffer register of timer output of each channel.
The value of each bit in this register is output from the timer output pin (TOmn) of each channel.
The TOmn bit oh this register can be rewritten by software only when timer output is disabled (TOEmn = 0). When
timer output is enabled (TOEmn = 1), rewriting this register by software is ignored, and the value is changed only
by the timer operation.
When using the following timer output pins as port function pins, set the corresponding TOmn bit to 0.
Note
78K0R/KC3-L: P10/TO02, P11/TO03, P12/TO04, P13/TO05, P50/TO06, P51/TO07, P52/SLTO
78K0R/KD3-L: P01/TO00, P10/TO02, P11/TO03, P12/TO04, P13/TO05, P50/TO06, P51/TO07, P52/SLTO
78K0R/KE3-L: P01/TO00, P10/TO02, P11/TO03, P12/TO04, P13/TO05, P14/TO06, P15/TO07, P52/SLTO
78K0R/KF3-L: P53/TO00, P16/TO01, P17/TO02, P31/TO03, P42/TO04, P05/TO05, P06/TO06, P54/TO07,
P64/TO10, P65/TO11, P66/TO12, P67/TO13
78K0R/KG3-L: P01/TO00, P16/TO01, P17/TO02, P31/TO03, P42/TO04, P46/TO05, P131/TO06, P145/TO07,
P64/TO10, P65/TO11, P66/TO12, P67/TO13
Note The 78K0R/KC3-L (40-pin) doesn’t have the SLTI and SLTO pins .
The TOm register can be set by a 16-bit memory manipulation instruction.
The lower 8 bits of the TOm register can be set with an 8-bit memory manipulation instruction with TOmL.
Reset signal generation clears this register to 0000H.
Figure 8-23. Format of Timer Output register m (TOm)
Address: F01B8H, F01B9H
After reset: 0000H
R/W
Symbol
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
TO0
0
0
0
0
0
0
0
0
TO0
TO0
TO0
TO0
TO0
TO0
TO0
TO0
7
6
5
4
3
2
1
0
Address: F01E0H, F01E1H
After reset: 0000H
R/W
Symbol
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
TO1
0
0
0
0
0
0
0
0
0
0
0
0
TO1
TO1
TO1
TO1
3
2
1
0
TOm
Timer output of channel n
n
0
Timer output value is “0”.
1
Timer output value is “1”.
Caution
Be sure to clear bits 15 to 8 of the TO0 register and bits 15 to 4 of the TO1 register to “0”.
Remark
m: Unit number (m = 0, 1), n: Channel number (n = 0 to 7)
However, in case of the timer output pin (TOmn), mn changes as below.
78K0R/KC3-L (40-pin):
mn = 02 to 07
78K0R/KC3-L (44-pin, 48-pin):
mn = 00 to 07
78K0R/KD3-L, 78K0R/KE3-L:
mn = 00 to 07
78K0R/KF3-L, 78K0R/KG3-L:
mn = 00 to 07, 10 to 13
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CHAPTER 8 TIMER ARRAY UNIT
(11) Timer output level register m (TOLm)
The TOLm register is a register that controls the timer output level of each channel.
The setting of the inverted output of channel n by this register is reflected at the timing of set or reset of the timer
output signal while the timer output is enabled (TOEmn = 1) in the slave channel output mode (TOMmn = 1). In
the master channel output mode (TOMmn = 0), this register setting is invalid.
The TOLm register can be set by a 16-bit memory manipulation instruction.
The lower 8 bits of the TOLm register can be set with an 8-bit memory manipulation instruction with TOLmL.
Reset signal generation clears this register to 0000H.
Figure 8-24. Format of Timer Output Level register m (TOLm)
Address: F01BCH, F01BDH
After reset: 0000H
R/W
Symbol
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
TOL0
0
0
0
0
0
0
0
0
TOL
TOL
TOL
TOL
TOL
TOL
TOL
TOL
07
06
05
04
03
02
01
00
Address: F01E4H, F01E5H
After reset: 0000H
R/W
Symbol
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
TOL1
0
0
0
0
0
0
0
0
0
0
0
0
TOL
TOL
TOL
TOL
13
12
11
10
TOL
Control of timer output level of channel n
mn
0
Positive logic output (active-high)
1
Inverted output (active-low)
Caution
Be sure to clear bits 15 to 8 of the TOL0 register and bits 15 to 4 of the TOL1 register to “0”.
Remarks 1.
If the value of this register is rewritten during timer operation, the timer output is inverted when the
timer output signal changes next, instead of immediately after the register value is rewritten.
2.
m: Unit number (m = 0, 1), n: Channel number (n = 0 to 7)
78K0R/KC3-L, 78K0R/KD3-L, 78K0R/KE3-L: mn = 00 to 07
78K0R/KF3-L, 78K0R/KG3-L:
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CHAPTER 8 TIMER ARRAY UNIT
(12) Timer output mode register m (TOMm)
The TOMm register is used to control the timer output mode of each channel.
When a channel is used for the independent channel operation function, set the corresponding bit of the channel
to be used to 0.
When a channel is used for the simultaneous channel operation function (PWM output, one-shot pulse output, or
multiple PWM output), set the corresponding bit of the master channel to 0 and the corresponding bit of the slave
channel to 1.
The setting of each channel n by this register is reflected at the timing when the timer output signal is set or reset
while the timer output is enabled (TOEmn = 1).
The TOMm register can be set by a 16-bit memory manipulation instruction.
The lower 8 bits of the TOMm register can be set with an 8-bit memory manipulation instruction with TOMmL.
Reset signal generation clears this register to 0000H.
Figure 8-25. Format of Timer Output Mode register m (TOMm)
Address: F01BEH, F01BFH
After reset: 0000H
R/W
Symbol
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
TOM0
0
0
0
0
0
0
0
0
TOM
TOM
TOM
TOM
TOM
TOM
TOM
TOM
07
06
05
04
03
02
01
00
Address: F01E6, F01E7H
After reset: 0000H
R/W
Symbol
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
TOM1
0
0
0
0
0
0
0
0
0
0
0
0
TOM
TOM
TOM
TOM
13
12
11
10
TOM
Control of timer output mode of channel n
mn
0
Master channel output mode (to produce toggle output by timer interrupt request signal (INTTMmn))
1
Slave channel output mode (output is set by the timer interrupt request signal (INTTMmn) of the master
channel, and reset by the timer interrupt request signal (INTTMmp) of the slave channel)
Caution
Be sure to clear bits 15 to 8 of the TOM0 register and bits 15 to 4 of the TOM1 register to “0”.
Remark
m: Unit number (m = 0, 1), n: Channel number (n = 0 to 7)
78K0R/KC3-L, 78K0R/KD3-L, 78K0R/KE3-L: mn = 00 to 07
78K0R/KF3-L, 78K0R/KG3-L:
mn = 00 to 07, 10 to 13
p: Slave channel number Note
When m = 0: Master channel n = 0, 2, 4, 6, n < p ≤ 7
When m = 1: Master channel n = 0, 2, n < p ≤ 3
(where p is a consecutive integer greater than n)
Note
Since there is no function of timer I/O, the channel 1 in the 78K0R/KC3-L (40-pin) can not be used as
the slave channel.
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CHAPTER 8 TIMER ARRAY UNIT
(13) Input switch control register (ISC)
The ISC1 and ISC0 bits of the ISC register are used to implement LIN-bus communication operation by using
channel 7 in association with the serial array unit. When the ISC1 bit is set to 1, the input signal of the serial data
input pin (RxDk) is selected as a timer input signal.
The ISC2 bit is set to select the P52/SLTI/SLTO pin as the timer I/O pin of timer channels 0 and 1 (78K0R/KC3-L
(44-pin, 48-pin), 78K0R/KD3-L, 78K0R/KE3-L only).
The ISC register can be set by a 1-bit or 8-bit memory manipulation instruction.
Reset signal generation clears this register to 00H.
Figure 8-26. Format of Input Switch Control Register (ISC)
Address: FFF3CH
Symbol
After reset: 00H
7
ISC
0
ISC2
R/W
6
5
0
4
0
Note 1
3
0
2
0
ISC2
Note 1
1
0
ISC1
ISC0
Selecting P52/SLTI/SLTO Pin as Timer I/O Pin
Channel 0
Input Pin
0
P00/TI00
1
Note 2
P52/SLTI
ISC1
Channel 1
Output Pin
P01/TO00
Note 2
Input Pin
Output Pin
P52/SLTI
P52/SLTO
−
−
P52/SLTO
Switching channel 7 input of timer array unit 0
0
Uses the input signal of the TI07 pin as a timer input (normal operation).
1
Input signal of the RXDk pin is used as timer input (detects the wakeup signal and measures the low
width of the sync break field and the pulse width of the sync field).
ISC0
Switching external interrupt (INTP0) input
0
Uses the input signal of the INTP0 pin as an external interrupt (normal operation).
1
Uses the input signal of the RXDk pin as an external interrupt (wakeup signal detection).
Notes 1. 78K0R/KC3-L (44-pin, 48-pin), 78K0R/KD3-L, 78K0R/KE3-L only.
2. 78K0R/KD3-L and 78K0R/KE3-L only. Only the P52/SLTI/SLTO pin can be assigned to channels 0 and
1 in the 78K0R/KC3-L (44-pin, 48-pin).
Caution
Be sure to clear bits 7 to 3 to “0” in the 78K0R/KC3-L (44-pin, 48-pin), 78K0R/KD3-L, and
78K0R/KE3-L. Be sure to clear bits 7 to 2 to “0” in the 78K0R/KC3-L (40-pin).
Be sure to clear bits 7 to 2 to “0” in the 78K0R/KF3-L and 78K0R/KG3-L.
Remarks 1. When the LIN-bus communication function is used, select the input signal of the RxDk pin by setting
ISC1 to 1.
2. 78K0R/KC3-L, 78K0R/KD3-L, 78K0R/KE3-L: k = 0 (RxD0)
78K0R/KF3-L, 78K0R/KG3-L:
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CHAPTER 8 TIMER ARRAY UNIT
(14) Noise filter enable registers 1, 2 (NFEN1, NFEN2)
The NFEN1 and NFEN2 registers are used to set whether the noise filter can be used for the timer input signal to
each channel.
Enable the noise filter by setting the corresponding bits to 1 on the pins in need of noise removal.
When the noise filter is ON, match detection and synchronization of the 2 clocks is performed with the
CPU/peripheral hardware clock (fMCK). When the noise filter is OFF, only synchronization is performed with the
CPU/peripheral hardware clock (fMCK).
The NFEN1 and NFEN2 registers can be set by a 1-bit or 8-bit memory manipulation instruction.
Reset signal generation clears these registers to 00H.
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CHAPTER 8 TIMER ARRAY UNIT
Figure 8-27. Format of Noise Filter Enable Registers 1, 2 (NFEN1, NFEN2)
(78K0R/KC3-L, 78K0R/KD3-L, 78K0R/KE3-L)
Address: F0061H
After reset: 00H
R/W
Symbol
7
6
5
4
3
2
1
NFEN1
TNFEN07
TNFEN06
TNFEN05
TNFEN04
TNFEN03
TNFEN02
0
5
4
3
2
1
0
0
0
0
0
Address: F0062H
Symbol
NFEN2
After reset: 00H
7
0
TNFEN07
0
0
Noise filter OFF
1
Noise filter ON
Noise filter OFF
1
Noise filter ON
TNFEN05
Note 1
or RxD0/P74 pin input signal
Note 3
Note 3
input signal
Enable/disable using noise filter of TI05/TO05/P13 pin input signal
0
Noise filter OFF
1
Noise filter ON
TNFEN04
Enable/disable using noise filter of TI04/TO04/RTCDIV/RTCCL/P12 pin input signal
0
Noise filter OFF
1
Noise filter ON
TNFEN03
Enable/disable using noise filter of TI03/TO03/P11 pin input signal
0
Noise filter OFF
1
Noise filter ON
TNFEN02
Enable/disable using noise filter of TI02/TO02/P10 pin input signal
0
Noise filter OFF
1
Noise filter ON
Note 1
Enable/disable using noise filter of TI00/P00 pin input signal
0
Noise filter OFF
1
Noise filter ON
TNFENSL
Note 3
Enable/disable using noise filter of TI06/TO06/P14 (P50) pin
0
TNFEN00
TNFENSL
Note 2
Enable/disable using noise filter of TI07/TO07/P15 (P51) pin
TNFEN06
TNFEN00
R/W
6
0
0
Note 2
Enable/disable using noise filter of SLTI/SLTO/P52 pin input signal
0
Noise filter OFF
1
Noise filter ON
Notes 1. 78K0R/KD3-L and 78K0R/KE3-L only
2. TNFENSL bit is not provided in the 78K0R/KC3-L (40-pin).
3. TI06/TO06 and TI07/TO07 are shared with P50 and P51, respectively, in products other than the
78K0R/KE3-L.
4. The applicable pin can be switched by setting the ISC1 bit of the ISC register.
ISC1 = 0: Whether or not to use the noise filter of the TI07 pin can be selected.
ISC1 = 1: Whether or not to use the noise filter of the RxD0 pin can be selected.
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CHAPTER 8 TIMER ARRAY UNIT
Figure 8-28. Format of Noise Filter Enable Registers 1, 2 (NFEN1, NFEN2)
(78K0R/KF3-L, 78K0R/KG3-L) (1/2)
Address: F0061H
After reset: 00H
R/W
Symbol
7
6
5
4
3
2
1
0
NFEN1
TNFEN07
TNFEN06
TNFEN05
TNFEN04
TNFEN03
TNFEN02
TNFEN01
TNFEN00
Address: F0062H
After reset: 00H
R/W
Symbol
7
6
5
4
3
2
1
0
NFEN2
0
0
0
0
TNFEN13
TNFEN12
TNFEN11
TNFEN10
TNFEN07
Enable/disable using noise filter of the following pin input signal
78K0R/KF3-L: SI41
Note 1
78K0R/KG3-L: TI07/TO07/P145 pin or RxD3/P14 pin
0
Noise filter OFF
1
Noise filter ON
TNFEN06
Note 2
/TI07/TO07/P54 pin or RxD3/P14 pin
Note 2
Enable/disable using noise filter of the following pin input signal
78K0R/KF3-L: TI06/TO06/P06 pin
78K0R/KG3-L: TI06/TO06/P131 pin
0
Noise filter OFF
1
Noise filter ON
TNFEN05
Enable/disable using noise filter of the following pin input signal
78K0R/KF3-L: TI05/TO05/P05 pin
78K0R/KG3-L: TI05/TO05/P146 pin
0
Noise filter OFF
1
Noise filter ON
TNFEN04
Enable/disable using noise filter of TI04/TO04/P42 pin input signal
0
Noise filter OFF
1
Noise filter ON
TNFEN03
Enable/disable using noise filter of TI03/TO03/INTP4/P31 pin input signal
0
Noise filter OFF
1
Noise filter ON
Notes 1. SI41 pin is only mounted in the μ PD78F1027 and 78F1028.
2. The applicable pin can be switched by setting the ISC1 bit of the ISC register.
ISC1 = 0: Whether or not to use the noise filter of the TI07 pin can be selected.
ISC1 = 1: Whether or not to use the noise filter of the RxD3 pin can be selected.
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CHAPTER 8 TIMER ARRAY UNIT
Figure 8-28. Format of Noise Filter Enable Registers 1, 2 (NFEN1, NFEN2)
(78K0R/KF3-L, 78K0R/KG3-L) (2/2)
Address: F0061H
After reset: 00H
R/W
Symbol
7
6
5
4
3
2
1
0
NFEN1
TNFEN07
TNFEN06
TNFEN05
TNFEN04
TNFEN03
TNFEN02
TNFEN01
TNFEN00
Address: F0062H
After reset: 00H
R/W
Symbol
7
6
5
4
3
2
1
0
NFEN2
0
0
0
0
TNFEN13
TNFEN12
TNFEN11
TNFEN10
TNFEN02
Enable/disable using noise filter of TI02/TO02/P17 pin input signal
0
Noise filter OFF
1
Noise filter ON
TNFEN01
Enable/disable using noise filter of TI01/TO01/INTP5/P16 pin input signal
0
Noise filter OFF
1
Noise filter ON
TNFEN00
Enable/disable using noise filter of the following pin input signal
78K0R/KF3-L: SCK41
Note
/TI00/P53 pin
78K0R/KG3-L: TI00/P00 pin
0
Noise filter OFF
1
Noise filter ON
TNFEN13
Enable/disable using noise filter of TI13/TO13/P67 pin input signal
0
Noise filter OFF
1
Noise filter ON
TNFEN12
Enable/disable using noise filter of TI12/TO12/P66 pin input signal
0
Noise filter OFF
1
Noise filter ON
TNFEN11
Enable/disable using noise filter of TI11/TO11/P65 pin input signal
0
Noise filter OFF
1
Noise filter ON
TNFEN10
Enable/disable using noise filter of TI10/TO10/P64 pin input signal
0
Noise filter OFF
1
Noise filter ON
Note SCK41 pin is only mounted in the μ PD78F1027 and 78F1028.
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CHAPTER 8 TIMER ARRAY UNIT
(15) Port mode registers 0, 1, 3 to 6, 13, 14 (PM0, PM1, PM3 to PM6, PM13, PM14)
These registers set input/output of ports 0, 1, 3 to 6, 13, 14 in 1-bit units.
The port pins that are shared with the timer I/O pins differ depending on the product. When using the timer array
unit, set the following port mode registers according to the product used.
78K0R/KC3-L: PM1, PM5
78K0R/KD3-L: PM1, PM5
78K0R/KE3-L: PM0, PM1, PM5
78K0R/KF3-L: PM0, PM1, PM3-PM6
78K0R/KG3-L: PM0, PM1, PM3, PM4, PM6, PM13, PM14
When using the ports (such as P01/TO00 and P10/TO02/TI02) to be shared with the timer output pin for timer
output, set the port mode register (PMxx) bit and port register (Pxx) bit corresponding to each port to 0.
Example: When using P10/TO02/TI02 for timer output
Set the PM10 bit of port mode register 1 to 0.
Set the P10 bit of port register 1 to 0.
When using the ports (such as P00/TI00 and P10/TO02/TI02) to be shared with the timer output pin for timer input,
set the port mode register (PMxx) bit corresponding to each port to 1. At this time, the port register (Pxx) bit may
be 0 or 1.
Example: When using P10/TO02/TI02 for timer input
Set the PM10 bit of port mode register 1 to 1.
Set the P10 bit of port register 1 to 0 or 1.
The PM0, PM1, PM3 to PM6, PM13, PM14 registers can be set by a 1-bit or 8-bit memory manipulation
instruction.
Reset signal generation sets these registers to FFH.
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CHAPTER 8 TIMER ARRAY UNIT
Figure 8-29. Format of Port Mode Registers 0, 1, 5 (PM0, PM1, PM5) (78K0R/KE3-L)
Address: FFF20H
After reset: FFH
R/W
Symbol
7
6
5
4
3
2
1
0
PM0
1
1
1
1
1
1
PM01
PM00
Address: FFF21H
After reset: FFH
R/W
Symbol
7
6
5
4
3
2
1
0
PM1
PM17
PM16
PM15
PM14
PM13
PM12
PM11
PM10
Address: FFF25H
After reset: FFH
R/W
Symbol
7
6
5
4
3
2
1
0
PM5
1
1
1
1
PM53
PM52
PM51
PM50
PMmn
Remark
Pmn pin I/O mode selection (m = 0, 1, 5; n = 0 to 7)
0
Output mode (output buffer on)
1
Input mode (output buffer off)
The figure shown above presents the format of port mode registers 0, 1, and 5 of the 78K0R/KE3-L product.
See below for the format of the port mode register of other products.
78K0R/KC3-L, 78K0R/KD3-L, 78K0R/KE3-L: 5.3 (1) Port mode registers (PMxx).
78K0R/KF3-L, 78K0R/KG3-L:
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6.3 (1) Port mode registers (PMxx).
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CHAPTER 8 TIMER ARRAY UNIT
8.4 Basic Rules of Simultaneous Channel Operation Function
When simultaneously using multiple channels, namely, a combination of a master channel (a reference timer mainly
counting the cycle) and slave channels (timers operating according to the master channel), the following rules apply.
(1) Only an even channel (channel 0, 2, 4, etc.) can be set as a master channel.
(2) Any channel, except channel 0, can be set as a slave channel.
(3) The slave channel must be lower than the master channel.
Example: If channel 2 of the TAU0 is set as a master channel, channel 3 or those that follow (channels 3, 4, 5,
etc.) can be set as a slave channel.
If channel 0 of the TAU1 is set as a master channel, channel 1 or those that follow (channels 1, 2, 3)
can be set as a slave channel.
(4) Two or more slave channels can be set for one master channel.
(5) When two or more master channels are to be used, slave channels with a master channel between them may not
be set.
Example: If channels 0 and 4 are set as master channels, channels 1 to 3 can be set as the slave channels of
master channel 0. Channels 5 to 7 cannot be set as the slave channels of master channel 0.
(6) The operating clock for a slave channel in combination with a master channel must be the same as that of the
master channel. The CKS bit (bit 15 of timer mode register mn (TMRmn)) of the slave channel that operates in
combination with the master channel must be the same value as that of the master channel.
(7) A master channel can transmit INTTMmn (interrupt), start software trigger, and count clock to the lower channels.
(8) A slave channel can use INTTMmn (interrupt), a start software trigger, or the count clock of the master channel as
a source clock, but cannot transmit its own INTTMmn (interrupt), start software trigger, or count clock to channels
with lower channel numbers.
(9) A master channel cannot use INTTMmn (interrupt), a start software trigger, or the count clock from the other higher
master channel as a source clock.
(10) To simultaneously start channels that operate in combination, the channel start trigger bit (TSmn) of the channels
in combination must be set at the same time.
(11) To stop the channels in combination simultaneously, the channel stop trigger bit (TTmn) of the channels in
combination must be set at the same time.
The rules of the simultaneous channel operation function are applied in a channel group (a master channel and slave
channels forming one simultaneous channel operation function).
If two or more channel groups that do not operate in combination are specified, the basic rules of the simultaneous
channel operation function in 8.4 Basic Rules of Simultaneous Channel Operation Function do not apply to the
channel groups.
Remark
m: Unit number (m = 0, 1), n: Channel number (n = 0 to 7)
78K0R/KC3-L, 78K0R/KD3-L, 78K0R/KE3-L: mn = 00 to 07
78K0R/KF3-L, 78K0R/KG3-L:
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CHAPTER 8 TIMER ARRAY UNIT
Example
TAU0
CK00
Channel 0: Master
Channel group 1
(Simultaneous channel operation
function)
Channel 1: Slave
Channel 2: Slave
Channel group 2
(Simultaneous channel operation
function)
Channel 3: independent channel
operation function
CK01
CK00
Channel 4: Master
* The operating clock of channel group 1 may
be different from that of channel group 2.
Channel 5: independent
channel operation
function
* A channel that operates independent
channel operation function may be between
channel group 1 and channel group 2.
Channel 6: Slave
Channel 7: independent channel
operation function
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* A channel that operates independent
channel operation function may be between
a master and a slave of channel group 2.
Furthermore, the operating clock may be set
separately.
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CHAPTER 8 TIMER ARRAY UNIT
8.5 Channel Output (TOmn pin) Control
8.5.1 TOmn pin output circuit configuration
Figure 8-30. Output Circuit Configuration
<5>
TOmn register
Controller
Interrupt signal of the master channel
(INTTMmn)
Interrupt signal of the slave channel
(INTTMmp)
Set
TOmn pin
Reset/toggle
<1>
<2>
<3>
TOLmn
TOMmn
<4>
Internal bus
TOEmn
TOmn write signal
The following describes the TOmn pin output circuit.
<1> When TOMmn = 0 (master channel output mode), the set value of timer output level register m (TOLm) is
ignored and only INTTMmp (slave channel timer interrupt) is transmitted to timer output register m (TOm).
<2>
When TOMmn = 1 (slave channel output mode), both INTTMmn (master channel timer interrupt) and
INTTMmp (slave channel timer interrupt) are transmitted to the TOm register.
At this time, the TOLm register becomes valid and the signals are controlled as follows:
When TOLmn = 0:
Forward operation (INTTMmn → set, INTTMmp → reset)
When TOLmn = 1:
Reverse operation (INTTMmn → reset, INTTMmp → set)
When INTTMmn and INTTMmp are simultaneously generated, (0% output of PWM), INTTMmp (reset signal)
takes priority, and INTTMmn (set signal) is masked.
<3> While timer output is enabled (TOEmn = 1), INTTMmn (master channel timer interrupt) and INTTMmp (slave
channel timer interrupt) are transmitted to the TOm register. Writing to the TOm register (TOmn write signal)
becomes invalid.
When TOEmn = 1, the TOmn pin output never changes with signals other than interrupt signals.
To initialize the TOmn pin output level, it is necessary to set timer operation is stopeed (TOEmn = 0) and to
write a value to the TOm register.
<4> While timer output is disabeled (TOEmn = 0), writing to the TOmn bit to the target channel (TOmn write signal)
becomes valid. When timer output is disabeled (TOEmn = 0), neither INTTMmn (master channel timer
interrupt) nor INTTMmp (slave channel timer interrupt) is transmitted to the TOm register.
<5> The TOm register can always be read, and the TOmn pin output level can be checked.
(Remark is listed on the next page.)
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Remark
CHAPTER 8 TIMER ARRAY UNIT
m: Unit number (m = 0, 1), n: Channel number (n = 0 to 7)
However, in case of the timer output pin (TOmn), mn changes as below.
78K0R/KC3-L (40-pin):
mn = 02 to 07
78K0R/KC3-L (44-pin, 48-pin):
mn = 00 to 07
78K0R/KD3-L, 78K0R/KE3-L:
mn = 00 to07
78K0R/KF3-L, 78K0R/KG3-L:
mn = 00 to 07, 10 to 13
p: Slave channel number Note
When m = 0: Master channel n = 0, 2, 4, 6, n < p ≤ 7
When m = 1: Master channel n = 0, 2, n < p ≤ 3
(Where p is a consecutive integer greater than n)
Note
Since there is no function of timer I/O, the channel 1 in the 78K0R/KC3-L (40-pin) can not be used as
the slave channel.
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8.5.2 TOmn Pin Output Setting
The following figure shows the procedure and status transition of the TOmn output pin from initial setting to timer
operation start.
Figure 8-31. Status Transition from Timer Output Setting to Operation Start
TCRmn
Undefined value (FFFFH after reset)
(Counter)
Hi-Z
Timer alternate-function pin
Timer output signal
TOmn
TOEmn
Write operation enabled period to TOmn
<1> Set TOMmn
Set TOLmn
<2> Set TOmn
Write operation disabled period to TOmn
<3> Set TOEmn
<4> Set the port to <5> Timer operation start
output mode
<1> The operation mode of timer output is set.
• TOMmn bit (0: Master channel output mode, 1: Slave channel output mode)
• TOLmn bit (0: Forward output, 1: Reverse output)
<2> The timer output signal is set to the initial status by setting timer output register m (TOm).
<3> The timer output operation is enabled by writing 1 to the TOEmn bit (writing to the TOm register is disabled).
<4> The port I/O setting is set to output (see 8.3 (15) Port mode registers 0, 1, 3 to 6, 13, 14 (PM0, PM1, PM3 to
PM6, PM13, PM14)).
<5> The timer operation is enabled (TSmn = 1).
Remark
m: Unit number (m = 0, 1), n: Channel number (n = 0 to 7)
However, in case of the timer output pin (TOmn), mn changes as below.
78K0R/KC3-L (40-pin):
mn = 02 to 07
78K0R/KC3-L (44-pin, 48-pin):
mn = 00 to 07
78K0R/KD3-L, 78K0R/KE3-L:
mn = 00 to 07
78K0R/KF3-L, 78K0R/KG3-L:
mn = 00 to 07, 10 to 13
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8.5.3 Cautions on Channel Output Operation
(1) Changing values set in the registers TOm, TOEm, TOLm, and TOMm during timer operation
Since the timer operations (operations of timer/counter register mn (TCRmn) and timer data register mn (TDRmn)) are
independent of the TOmn output circuit and changing the values set in timer output register m (TOm), timer output
enable register m (TOEm), timer output level register m (TOLm), and timer output mode register m (TOMm) does not
affect the timer operation, the values can be changed during timer operation. To output an expected waveform from the
TOmn pin by timer operation, however, set the TOm, TOEm, TOLm, and TOMm registers to the values stated in the
register setting example of each operation.
When the values set to the TOEm, TOLm, and TOMm registers (but not the TOm register) are changed close to the
occurrence of the timer interrupt (INTTMmn) of each channel, the waveform output to the TOmn pin might differ,
depending on whether the values are changed immediately before or immediately after the timer interrupt (INTTMmn)
occurs.
Remark
m: Unit number (m = 0, 1), n: Channel number (n = 0 to 7)
However, in case of the timer output pin (TOmn), mn changes as below.
78K0R/KC3-L (40-pin):
mn = 02 to 07
78K0R/KC3-L (44-pin, 48-pin):
mn = 00 to 07
78K0R/KD3-L, 78K0R/KE3-L:
mn = 00 to 07
78K0R/KF3-L, 78K0R/KG3-L:
mn = 00 to 07, 10 to 13
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(2) Default level of TOmn pin and output level after timer operation start
The change in the output level of the TOmn pin when timer output register m (TOm) is written while timer output is
disabled (TOEmn = 0), the initial level is changed, and then timer output is enabled (TOEmn = 1) before port
output is enabled, is shown below.
(a) When operation starts with master channel output mode (TOMmn = 0) setting
The setting of timer output level register m (TOLm) is invalid when master channel output mode (TOMmn = 0).
When the timer operation starts after setting the default level, the toggle signal is generated and the output
level of the TOmn pin is reversed.
Figure 8-32. TOmn Pin Output Status at Toggle Output (TOMmn = 0)
TOEmn
Default level, TOLmn setting
TOmn = 0, TOLmn = 0
Hi-Z
TOmn = 1, TOLmn = 0
Hi-Z
TOmn = 0, TOLmn = 1
(Same output waveform as TOLmn = 0)
Hi-Z
TOmn = 1, TOLmn = 1
(Same output waveform as TOLmn = 0)
Hi-Z
Dependent on TOmn setting
Independent of TOLmn setting
Port output is enabled
Toggle
Toggle
Toggle
Toggle
Toggle
TOmn pin transition
Remarks 1. Toggle:
Reverse TOmn pin output status
2. m: Unit number (m = 0, 1), n: Channel number (n = 0 to 7)
However, in case of the timer output pin (TOmn), mn changes as below.
78K0R/KC3-L (40-pin):
mn = 02 to 07
78K0R/KC3-L (44-pin, 48-pin):
mn = 00 to 07
78K0R/KD3-L, 78K0R/KE3-L:
mn = 00 to 07
78K0R/KF3-L, 78K0R/KG3-L:
mn = 00 to 07, 10 to 13
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(b) When operation starts with slave channel output mode (TOMmn = 1) setting (PWM output))
When slave channel output mode (TOMmn = 1), the active level is determined by timer output level register m
(TOLm) setting.
Figure 8-33. TOmn Pin Output Status at PWM Output (TOMmn = 1)
TOEmn
Default level, TOLmn setting
TOmn = 0, TOLmn = 0
(Active high)
Hi-Z
TOmn = 1, TOLmn = 0
(Active high)
Hi-Z
TOmn = 0, TOLmn = 1
(Active low)
Hi-Z
TOmn = 1, TOLmn = 1
(Active low)
Hi-Z
No change
Dependent on TOLmn setting
Dependent on TOmn setting
Port output is enabled
Set
Reset
Set
Reset
Set
TOmn pin transition
Remarks 1. Set:
Reset:
The output signal of the TOmn pin changes from inactive level to active level.
The output signal of the TOmn pin changes from active level to inactive level.
2. m: Unit number (m = 0, 1), n: Channel number (n = 0 to 7)
However, in case of the timer output pin (TOmn), mn changes as below.
78K0R/KC3-L (40-pin):
mn = 02 to 07
78K0R/KC3-L (44-pin, 48-pin):
mn = 00 to 07
78K0R/KD3-L, 78K0R/KE3-L:
mn = 00 to 07
78K0R/KF3-L, 78K0R/KG3-L:
mn = 00 to 07, 10 to 13
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(3) Operation of TOmn pin in slave channel output mode (TOMmn = 1)
(a) When timer output level register m (TOLm) setting has been changed during timer operation
When the TOLm register setting has been changed during timer operation, the setting becomes valid at the
generation timing of the TOmn pin change condition. Rewriting the TOLm register does not change the output
level of the TOmn pin.
The operation when TOMmn is set to 1 and the value of the TOLm register is changed while the timer is
operating (TEmn = 1) is shown below.
Figure 8-34. Operation when TOLm Register Has Been Changed during Timer Operation
Output set signal
(Internal signal)
Output reset signal
(Internal signal)
TOLmn
TOmn pin
TOmn does not change
Remarks 1. Set:
Reset:
Set/reset signals are inverted
The output signal of the TOmn pin changes from inactive level to active level.
The output signal of the TOmn pin changes from active level to inactive level.
2. m: Unit number (m = 0, 1), n: Channel number (n = 0 to 7)
However, in case of the timer output pin (TOmn), mn changes as below.
78K0R/KC3-L (40-pin):
mn = 02 to 07
78K0R/KC3-L (44-pin, 48-pin):
mn = 00 to 07
78K0R/KD3-L, 78K0R/KE3-L:
mn = 00 to 07
78K0R/KF3-L, 78K0R/KG3-L:
mn = 00 to 07, 10 to 13
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(b) Set/reset timing
To realize 0%/100% output at PWM output, the TOmn pin/TOmn bit set timing at master channel timer interrupt
(INTTMmn) generation is delayed by 1 count clock by the slave channel.
If the set condition and reset condition are generated at the same time, a higher priority is given to the latter.
Figure 8-35 shows the set/reset operating statuses where the master/slave channels are set as follows.
Master channel:
Slave channel:
TOEmn = 1, TOMmn = 0, TOLmn = 0
TOEmp = 1, TOMmp = 1, TOLmp = 0
Figure 8-35. Set/Reset Timing Operating Statuses
fCLK
Count clock
Master channel
INTTMmn
Internal reset
signal
TOmn pin/
TOmn
Toggle
Internal set
signal
Delays to_reset by 1 count
clock with slave channel
Slave channel
INTTMmp
to_reset
(Internal signal)
TOmp pin/
TOmp
Set
Reset
Remarks 1. Internal reset signal: TOmn pin reset/toggle signal
Internal set signal: TOmn pin set signal
2. m: Unit number (m = 0, 1), n: Channel number (n = 0 to 7)
However, in case of the timer output pin (TOmn), mn changes as below.
78K0R/KC3-L (40-pin):
mn = 02 to 07
78K0R/KC3-L (44-pin, 48-pin): mn = 00 to 07
78K0R/KD3-L, 78K0R/KE3-L: mn = 00 to 07
78K0R/KF3-L, 78K0R/KG3-L: mn = 00 to 07, 10 to 13
p: Slave channel number Note
When m = 0: Master channel n = 0, 2, 4, 6, n < p ≤ 7
When m = 1: Master channel n = 0, 2, n < p ≤ 3
(Where p is a consecutive integer greater than n)
Note
Since there is no function of timer I/O, the channel 1 in the 78K0R/KC3-L (40-pin) can not be
used as the slave channel.
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CHAPTER 8 TIMER ARRAY UNIT
8.5.4 Collective manipulation of TOmn bit
In timer output register m (TOm), the setting bits for all the channels are located in one register in the same way as
timer channel start register m (TSm). Therefore, the TOmn bit of all the channels can be manipulated collectively.
Only the desired bits can also be manipulated by enabling writing only to the TOmn bits (TOEmn = 0) that correspond
to the relevant bits of the channel used to perform output (TOmn).
Figure 8-36. Example of TOmn Bit Collective Manipulation
Before writing
TO0
0
0
0
0
0
0
0
0
TO07 TO06 TO05 TO04 TO03 TO02 TO01 TO00
0
TOE0
0
0
0
0
0
0
0
0
0
1
0
0
0
1
0
TOE07 TOE06 TOE05 TOE04 TOE03 TOE02 TOE01 TOE00
0
0
1
0
1
1
1
1
1
1
0
0
0
0
1
1
O
O
× O ×
×
×
×
Data to be written
0
0
0
0
0
0
0
0
After writing
TO0
0
0
0
0
0
0
0
0
TO07 TO06 TO05 TO04 TO03 TO02 TO01 TO00
1
1
1
0
0
0
1
0
Writing is done only to the TOmn bit with TOEmn = 0, and writing to the TOmn bit with TOEmn = 1 is ignored.
TOmn (channel output) to which TOEmn = 1 is set is not affected by the write operation. Even if the write operation is
done to the TOmn bit, it is ignored and the output change by timer operation is normally done.
Figure 8-37. TOmn Pin Statuses by Collective Manipulation of TOmn Bit
Two or more TO0n output can
be changed simultaneously
TO07
Output does not change
when value does not
change
TO06
TO05
TO04
Writing to the TO0n bit is
ignored when TOE0n
=1
TO03
TO02
TO01
TO00
Before writing
Writing to the TO0n bit
(Caution and Remark are given on the next page.)
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Caution While timer output is enabled (TOEmn = 1), even if the output by timer interrupt of each timer
(INTTMmn) contends with writing to the TOmn bit, output is normally done to the TOmn pin.
Remark
m: Unit number (m = 0, 1), n: Channel number (n = 0 to 7)
However, in case of the timer output pin (TOmn), mn changes as below.
78K0R/KC3-L (40-pin):
mn = 02 to 07
78K0R/KC3-L (44-pin, 48-pin):
mn = 00 to 07
78K0R/KD3-L, 78K0R/KE3-L:
mn = 00 to 07
78K0R/KF3-L, 78K0R/KG3-L:
mn = 00 to 07, 10 to 13
8.5.5 Timer Interrupt and TOmn Pin Output at Operation Start
In the interval timer mode or capture mode, the MDmn0 bit in timer mode register mn (TMRmn) sets whether or not to
generate a timer interrupt at count start.
When MDmn0 is set to 1, the count operation start timing can be known by the timer interrupt (INTTMmn) generation.
In the other modes, neither timer interrupt at count operation start nor TOmn output is controlled.
Figures 8-37 and 8-38 show operation examples when the interval timer mode (TOEmn = 1, TOMmn = 0) is set.
Figure 8-38. When MDmn0 is set to 1
TCRmn
TEmn
INTTMmn
TOmn
Count operation start
When MDmn0 is set to 1, a timer interrupt (INTTMmn) is output at count operation start, and TOmn performs a toggle
operation.
Figure 8-39. When MDmn0 is set to 0
TCRmn
TEmn
INTTMmn
TOmn
Count operation start
When MDmn0 is set to 0, a timer interrupt (INTTMmn) is not output at count operation start, and TOmn does not
change either. After counting one cycle, INTTMmn is output and TOmn performs a toggle operation.
Remark
m: Unit number (m = 0, 1), n: Channel number (n = 0 to 7)
However, in case of the timer output pin (TOmn), mn changes as below.
78K0R/KC3-L (40-pin):
mn = 02 to 07
78K0R/KC3-L (44-pin, 48-pin):
mn = 00 to 07
78K0R/KD3-L, 78K0R/KE3-L:
mn = 00 to 07
78K0R/KF3-L, 78K0R/KG3-L:
mn = 00 to 07, 10 to 13
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8.6 Channel Input (TImn Pin) Control
8.6.1 TImn edge detection circuit
(1) Edge detection basic operation timing
Edge detection circuit sampling is done in accordance with the operation clock (fMCK).
Figure 8-40. Edge Detection Basic Operation Timing
fCLK
Operation clock (fMCK)
Synchronized (noise filter)
internal TImn signal
Rising edge detection internal trigger
Falling edge detection internal trigger
Remark
m: Unit number (m = 0, 1), n: Channel number (n = 0 to 7)
However, in case of the timer input pin (TImn) and the timer output pin (TOmn), mn changes as below.
78K0R/KC3-L (40-pin):
mn = 02 to 07
78K0R/KC3-L (44-pin, 48-pin):
mn = 00 to 07
78K0R/KD3-L, 78K0R/KE3-L:
mn = 00 to 07
78K0R/KF3-L, 78K0R/KG3-L:
mn = 00 to 07, 10 to 13
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8.7 Independent Channel Operation Function of Timer Array Unit
8.7.1 Operation as interval timer/square wave output
(1) Interval timer
The timer array unit can be used as a reference timer that generates INTTMmn (timer interrupt) at fixed intervals.
The interrupt generation period can be calculated by the following expression.
Generation period of INTTMmn (timer interrupt) = Period of count clock × (Set value of TDRmn + 1)
In products other than the 78K0R/KC3-L (40-pin), A subsystem clock divided by four (fSUB/4) can be selected as the
count clock, in addition to CKm0 and CKm1. Consequently, the interval timer can be operated with the count clock
fixed to fSUB/4, regardless of the fCLK frequency (main system clock, subsystem clock). However, be sure to change
the clock selected as fCLK (change the value of the system clock control register (CKC)) after stopping all channels
of timer array unit (timer channel stop register m (TTm) = 00FFH).
(2) Operation as square wave output
TOmn performs a toggle operation as soon as INTTMmn has been generated, and outputs a square wave with a
duty factor of 50%.
The period and frequency for outputting a square wave from TOmn can be calculated by the following expressions.
• Period of square wave output from TOmn = Period of count clock × (Set value of TDRmn + 1) × 2
• Frequency of square wave output from TOmn = Frequency of count clock/{(Set value of TDRmn + 1) × 2}
Timer/counter register mn (TCRmn) operates as a down counter in the interval timer mode.
The TCRmn register loads the value of timer data register mn (TDRmn) at the first count clock after the channel
start trigger bit (TSmn) of timer channel start register m (TSm) is set to 1. If the MDmn0 bit of timer mode register
mn (TMRmn) is 0 at this time, INTTMmn is not output and TOmn is not toggled. If the MDmn0 bit of the TMRmn
register is 1, INTTMmn is output and TOmn is toggled.
After that, the TCRmn register count down in synchronization with the count clock.
When TCRmn = 0000H, INTTMmn is output and TOmn is toggled at the next count clock. At the same time, the
TCRmn register loads the value of the TDRmn register again. After that, the same operation is repeated.
The TDRmn register can be rewritten at any time. The new value of the TDRmn register becomes valid from the
next period.
Remarks 1. m: Unit number (m = 0, 1), n: Channel number (n = 0 to 7)
However, in case of the operation of square wave output and the timer output pin (TOmn), mn
changes as below.
78K0R/KC3-L (40-pin):
mn = 02 to 07
78K0R/KC3-L (44-pin, 48-pin): mn = 00 to 07
2.
78K0R/KD3-L, 78K0R/KE3-L:
mn = 00 to 07
78K0R/KF3-L, 78K0R/KG3-L:
mn = 00 to 07, 10 to 13
fCLK: CPU/peripheral hardware clock frequency
fSUB: Subsystem clock oscillation frequency
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CKm1
CKm0
Trigger selection
fSUB/4
Edge
detection
Operation clock
Clock selection
Figure 8-41. Block Diagram of Operation as Interval Timer/Square Wave Output
TSmn
Timer counter
register mn (TCRmn)
Output
controller
Timer data
register mn(TDRmn)
Interrupt
controller
TOmn pin
Interrupt signal
(INTTMmn)
Figure 8-42. Example of Basic Timing of Operation as Interval Timer/Square Wave Output (MDmn0 = 1)
TSmn
TEmn
TCRmn
0000H
TDRmn
a
b
TOmn
INTTMmn
a+1
a+1
a+1
b+1
b+1
b+1
Remarks 1. m: Unit number (m = 0, 1), n: Channel number (n = 0 to 7)
However, in case of the operation of square wave output and the timer output pin (TOmn), mn
changes as below.
78K0R/KC3-L (40-pin):
mn = 02 to 07
78K0R/KC3-L (44-pin, 48-pin): mn = 00 to 07
78K0R/KD3-L, 78K0R/KE3-L:
mn = 00 to 07
78K0R/KF3-L, 78K0R/KG3-L:
mn = 00 to 07, 10 to 13
2. TSmn:
Bit n of timer channel start register m (TSm)
TEmn:
Bit n of timer channel enable status register m (TEm)
TCRmn:
Timer/counter register mn (TCRmn)
TDRmn:
Timer data register mn (TDRmn)
TOmn:
TOmn pin output signal
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Figure 8-43. Example of Set Contents of Registers During Operation as Interval Timer/Square Wave Output (1/3)
(1) When CKm0 or CKm1 is selected as count clock
(a) Timer mode register mn (TMRmn)
15
TMRmn
14
13
11
10
9
8
7
6
5
4
0
0
MAS
CCSmn
STSmn2 STSmn1 STSmn0 CISmn1 CISmn0
TERmn
CKSmn
1/0
12
0
0
0
0
0
0
0
0
3
2
1
0
MDmn3 MDmn2 MDmn1 MDmn0
0
0
0
0
1/0
Operation mode of channel n
000B: Interval timer
Setting of operation when counting is started
0: Neither generates INTTMmn nor inverts
timer output when counting is started.
1: Generates INTTMmn and inverts timer
output when counting is started.
Selection of TImn pin input edge
00B: Sets 00B because these are not used.
Start trigger selection
000B: Selects only software start.
Slave/master selection
0: Independent channel operation function.
Count clock selection
0: Selects the operation clock specified by using the CKSmn bit (fMCK) as the count clock.
Selecting the operation clock from two types of clocks (fMCK)
0: Selects CKm0 as operation clock of channel n.
1: Selects CKm1 as operation clock of channel n.
(b) Timer output register m (TOm)
Bit n
TOm
TOmn
0: Outputs 0 from TOmn.
1/0
1: Outputs 1 from TOmn.
(c) Timer output enable register m (TOEm)
Bit n
TOEm
TOEmn
1/0
0: Stops the TOmn output operation by counting operation.
1: Enables the TOmn output operation by counting operation.
(d) Timer output level register m (TOLm)
Bit n
TOLm
TOLmn
0: Cleared to 0 when TOMmn = 0 (master channel output mode)
0
(e) Timer output mode register m (TOMm)
Bit n
TOMm
TOMmn
0: Sets master channel output mode.
0
Remark m: Unit number (m = 0, 1), n: Channel number (n = 0 to 7)
However, in case of the operation of square wave output and the timer output pin (TOmn), mn changes as
below.
78K0R/KC3-L (40-pin):
mn = 02 to 07
78K0R/KC3-L (44-pin, 48-pin):
mn = 00 to 07
78K0R/KD3-L, 78K0R/KE3-L:
mn = 00 to 07
78K0R/KF3-L, 78K0R/KG3-L:
mn = 00 to 07, 10 to 13
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Figure 8-43. Example of Set Contents of Registers During Operation as Interval Timer/Square Wave Output (2/3)
(2) When fSUB/4 is selected as count clock (products other than 78K0R/KC3-L (40-pin))
(a) Timer mode register mn (TMRmn)
15
TMRmn
14
13
11
10
9
8
7
6
5
4
0
0
MAS
CCSmn
STSmn2 STSmn1 STSmn0 CISmn1 CISmn0
TERmn
CKSmn
1/0
12
0
0
1
0
0
0
0
1/0
3
2
1
0
MDmn3 MDmn2 MDmn1 MDmn0
1/0
0
0
0
1/0
Operation mode of channel n
000B: Interval timer
Setting of operation when counting is started
0: Neither generates INTTMmn nor inverts
timer output when counting is started.
1: Generates INTTMmn and inverts timer
output when counting is started.
fSUB/4 edge selection
00B: Detects falling edge (counts on fSUB/4 cycles).
01B: Detects rising edge (counts on fSUB/4 cycles).
10B: Detects both edges (counts on fSUB/2 cycles).
11B: Setting prohibited
Start trigger selection
000B: Selects only software start.
Slave/master selection
0: Independent channel operation function.
Count clock selection
1: Selects subsystem clock divided by four (fSUB/4).
Operation clock selection
0: Selects CKm0 as operation clock of channel n.
1: Selects CKm1 as operation clock of channel n.
fCLK (no division) is selected as selected operation clock by the TPSm register.
(b) Timer clock select register m (TPSm)
Bits 7 to 4, 3 to 0
TPSm
PRSmk3 to PRSmk0
0000
0000B: Selects fCLK (no division) as operation clock selected by the CKSmn bit of the TMRmn register.
k = 0 (bits 0 to 3) when CKm0 is selected and k = 1 (bits 4 to 7) when CKm1 is selected
(c) Timer input select register m (TISm)
Bit n
TISm
TISmn
1: Selects subsystem clock divided by four (fSUB/4).
1
(d) Timer output register m (TOm)
Bit n
TOm
TOmn
0: Outputs 0 from TOmn.
1/0
1: Outputs 1 from TOmn.
Remarks 1. m: Unit number (m = 0, 1), n: Channel number (n = 0 to 7)
However, in case of the operation of square wave output and the timer output pin (TOmn), mn changes
as below.
78K0R/KC3-L (40-pin):
mn = 02 to 07
78K0R/KC3-L (44-pin, 48-pin): mn = 00 to 07
78K0R/KD3-L, 78K0R/KE3-L: mn = 00 to 07
78K0R/KF3-L, 78K0R/KG3-L: mn = 00 to 07, 10 to 13
2. fSUB: Subsystem clock oscillation frequency
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CHAPTER 8 TIMER ARRAY UNIT
Figure 8-43. Example of Set Contents of Registers During Operation as Interval Timer/Square Wave Output (3/3)
(2) When fSUB/4 is selected as count clock (continued)
(e) Timer output enable register m (TOEm)
Bit n
TOEm
TOEmn
0: Stops the TOmn output operation by counting operation.
1: Enables the TOmn output operation by counting operation.
1/0
(f) Timer output level register m (TOLm)
Bit n
TOLm
TOLmn
0: Cleared to 0 when TOMmn = 0 (master channel output mode)
0
(g) Timer output mode register m (TOMm)
Bit n
TOMm
TOMmn
0: Sets master channel output mode.
0
Remark m: Unit number (m = 0, 1), n: Channel number (n = 0 to 7)
However, in case of the operation of square wave output and the timer output pin (TOmn), mn changes as
below.
78K0R/KC3-L (40-pin):
mn = 02 to 07
78K0R/KC3-L (44-pin, 48-pin):
mn = 00 to 07
78K0R/KD3-L, 78K0R/KE3-L:
mn = 00 to 07
78K0R/KF3-L, 78K0R/KG3-L:
mn = 00 to 07, 10 to 13
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CHAPTER 8 TIMER ARRAY UNIT
Figure 8-44. Operation Procedure of Interval Timer/Square Wave Output Function (1/2)
Software Operation
TAU
default
setting
Hardware Status
Power-off status
(Clock supply is stopped and writing to each register is
disabled.)
Sets the TAU0EN and TAU1EN bits of peripheral enable
Note
registers 0, 2 (PER0, PER2) to 1.
Power-on status. Each channel stops operating.
(Clock supply is started and writing to each register is
enabled.)
Sets timer clock select register m (TPSm).
Determines clock frequencies of CKm0 and CKm1.
Channel
default
setting
Operation is resumed.
Operation
start
Sets timer mode register mn (TMRmn) (determines
operation mode of channel).
Sets the TISmn bit to 1 (fSUB/4) when fSUB/4 is selected as
the count clock.
Sets interval (period) value to timer data register mn
(TDRmn).
Channel stops operating.
(Clock is supplied and some power is consumed.)
To use the TOmn output
Clears the TOMmn bit of timer output mode register m
(TOMm) to 0 (master channel output mode).
Clears the TOLmn bit to 0.
Sets the TOmn bit and determines default level of the
TOmn output.
The TOmn pin goes into Hi-Z output state.
Sets the TOEmn bit to 1 and enables operation of TOmn.
Clears the port register and port mode register to 0.
TOmn does not change because channel stops operating.
The TOmn pin outputs the TOmn set level.
(Sets the TOEmn bit to 1 only if using TOmn output and
resuming operation.).
Sets the TSmn bit to 1.
The TSmn bit automatically returns to 0 because it is a
trigger bit.
The TOmn default setting level is output when the port mode
register is in the output mode and the port register is 0.
TEmn = 1, and count operation starts.
Value of the TDRmn register is loaded to timer/counter
register mn (TCRmn) at the count clock input. INTTMmn is
generated and TOmn performs toggle operation if the
MDmn0 bit of the TMRmn register is 1.
During
operation
Set values of the TMRmn register, TOMmn, and TOLmn
bits cannot be changed.
Set value of the TDRmn register can be changed.
The TCRmn register can always be read.
The TSRmn register is not used.
Set values of the TOm and TOEm registers can be
changed.
Counter (TCRmn) counts down. When count value reaches
0000H, the value of the TDRmn register is loaded to the
TCRmn register again and the count operation is continued.
By detecting TCRmn = 0000H, INTTMmn is generated and
TOmn performs toggle operation.
After that, the above operation is repeated.
Operation
stop
The TTmn bit is set to 1.
The TTmn bit automatically returns to 0 because it is a
trigger bit.
TEmn = 0, and count operation stops.
The TCRmn register holds count value and stops.
The TOmn output is not initialized but holds current status.
The TOEmn bit is cleared to 0 and value is set to the TOmn bit.
The TOmn pin outputs the TOmn bit set level.
(Note and Remark are listed on the next page.)
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CHAPTER 8 TIMER ARRAY UNIT
Figure 8-44. Operation Procedure of Interval Timer/Square Wave Output Function (2/2)
Software Operation
Hardware Status
To hold the TOmn pin output level
Clears the TOmn bit to 0 after the value to
be held is set to the port register.
When holding the TOmn pin output level is not necessary
Switches the port mode register to input mode.
TAU
stop
The TAU0EN and TAU1EN bits of the PER0 and PER2
Note
registers are cleared to 0.
Note 78K0R/KC3-L, 78K0R/KD3-L, 78K0R/KE3-L:
78K0R/KF3-L, 78K0R/KG3-L:
Remark
The TOmn pin output level is held by port function.
The TOmn pin output level goes into Hi-Z output state.
Power-off status
All circuits are initialized and SFR of each channel is also
initialized.
(The TOmn bit is cleared to 0 and the TOmn pin is set to
port mode.)
TAU0EN bit of the PER2 register
TAU0EN or TAU1EN bit of the PER0 register
m: Unit number (m = 0, 1), n: Channel number (n = 0 to 7)
However, in case of the operation of square wave output and the timer output pin (TOmn), mn changes as
below.
78K0R/KC3-L (40-pin):
mn = 02 to 07
78K0R/KC3-L (44-pin, 48-pin):
mn = 00 to 07
78K0R/KD3-L, 78K0R/KE3-L:
mn = 00 to 07
78K0R/KF3-L, 78K0R/KG3-L:
mn = 00 to 07, 10 to 13
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CHAPTER 8 TIMER ARRAY UNIT
8.7.2 Operation as external event counter
The timer array unit can be used as an external event counter that counts the number of times the valid input edge
(external event) is detected in the TImn pin. When a specified count value is reached, the event counter generates an
interrupt. The specified number of counts can be calculated by the following expression.
Specified number of counts = Set value of TDRmn + 1
Timer/counter register mn (TCRmn) operates as a down counter in the event counter mode.
The TCRmn register loads the value of timer data register mn (TDRmn) by setting any channel start trigger bit (TSmn)
of timer channel start register m (TSm) to 1.
The TCRmn register counts down each time the valid input edge of the TImn pin has been detected. When TCRmn =
0000H, the TCRmn register loads the value of the TDRmn register again, and outputs INTTMmn.
After that, the above operation is repeated.
An irregular waveform that depends on external events is output from the TOmn pin. Stop the output by setting the
TOEmn bit of timer output enable register m (TOEm) to 0.
The TDRmn register can be rewritten at any time. The new value of the TDRmn register becomes valid during the next
count period.
TSmn
Trigger selection
Edge
detection
TImn pin
Clock selection
Figure 8-45. Block Diagram of Operation as External Event Counter
Timer counter
register mn (TCRmn)
Timer data
register mn (TDRmn)
Interrupt
controller
Interrupt signal
(INTTMmn)
Remark m: Unit number (m = 0, 1), n: Channel number (n = 0 to 7)
78K0R/KC3-L (40-pin):
mn = 02 to 07
78K0R/KC3-L (44-pin, 48-pin):
mn = 00 to 07
78K0R/KD3-L, 78K0R/KE3-L:
mn = 00 to 07
78K0R/KF3-L, 78K0R/KG3-L:
mn = 00 to 07, 10 to 13
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CHAPTER 8 TIMER ARRAY UNIT
Figure 8-46. Example of Basic Timing of Operation as External Event Counter
TSmn
TEmn
TImn
3
TCRmn
0000H
TDRmn
2
3
1
2
0
1
2
0
0003H
1
2
0
1
0002H
INTTMmn
4 events
4 events
3 events
Remarks 1. m: Unit number (m = 0, 1), n: Channel number (n = 0 to 7)
78K0R/KC3-L (40-pin):
mn = 02 to 07
78K0R/KC3-L (44-pin, 48-pin):
mn = 00 to 07
78K0R/KD3-L, 78K0R/KE3-L:
mn = 00 to 07
78K0R/KF3-L, 78K0R/KG3-L:
mn = 00 to 07, 10 to 13
2. TSmn:
TEmn:
Bit n of timer channel start register m (TSm)
Bit n of timer channel enable status register m (TEm)
TImn:
TImn pin input signal
TCRmn:
Timer/counter register mn (TCRmn)
TDRmn:
Timer data register mn (TDRmn)
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CHAPTER 8 TIMER ARRAY UNIT
Figure 8-47. Example of Set Contents of Registers in External Event Counter Mode
(a) Timer mode register mn (TMRmn)
15
TMRmn
14
13
CKSmn
1/0
12
CCSmn
0
0
1
11
10
9
8
7
6
5
4
MAS
STSmn2 STSmn1 STSmn0 CISmn1 CISmn0
TERmn
0
0
0
0
1/0
3
2
1
0
MDmn3 MDmn2 MDmn1 MDmn0
1/0
0
0
0
1
1
0
Operation mode of channel n
011B: Event count mode
Setting of operation when counting is started
0: Neither generates INTTMmn nor inverts
timer output when counting is started.
Selection of TImn pin input edge
00B: Detects falling edge.
01B: Detects rising edge.
10B: Detects both edges.
11B: Setting prohibited
Start trigger selection
000B: Selects only software start.
Slave/master selection
0: Independent channel operation function is selected.
Count clock selection
1: Selects the TImn pin input valid edge.
Operation clock selection
0: Selects CKm0 as operation clock of channel n.
1: Selects CKm1 as operation clock of channel n.
(b) Timer output register m (TOm)
Bit n
TOm
TOmn
0: Outputs 0 from TOmn.
0
(c) Timer output enable register m (TOEm)
Bit n
TOEm
TOEmn
0: Stops the TOmn output operation by counting operation.
0
(d) Timer output level register m (TOLm)
Bit n
TOLm
TOLmn
0: Cleared to 0 when TOMmn = 0 (master channel output mode).
0
(e) Timer output mode register m (TOMm)
Bit n
TOMm
TOMmn
0: Sets master channel output mode.
0
Remark m: Unit number (m = 0, 1), n: Channel number (n = 0 to 7)
78K0R/KC3-L (40-pin):
mn = 02 to 07
78K0R/KC3-L (44-pin, 48-pin):
mn = 00 to 07
78K0R/KD3-L, 78K0R/KE3-L:
mn = 00 to 07
78K0R/KF3-L, 78K0R/KG3-L:
mn = 00 to 07, 10 to 13
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Figure 8-48. Operation Procedure When External Event Counter Function Is Used
Software Operation
Hardware Status
Power-off status
TAU
default
(Clock supply is stopped and writing to each register is
setting
disabled.)
Sets the TAU0EN and TAU1EN bits of peripheral enable
Note
registers 0, 2 (PER0, PER2) to 1.
Power-on status. Each channel stops operating.
(Clock supply is started and writing to each register is
enabled.)
Sets timer clock select register m (TPSm).
Determines clock frequencies of CKm0 and CKm1.
Channel
Sets timer mode register mn (TMRmn) (determines
Channel stops operating.
default
operation mode of channel).
(Clock is supplied and some power is consumed.)
setting
Sets number of counts to timer data register mn
(TDRmn).
Clears the TOEmn bit of timer output enable register m
(TOEm) to 0.
Operation
Operation is resumed.
start
Sets the TSmn bit to 1.
TEmn = 1, and count operation starts.
The TSmn bit automatically returns to 0 because it is a
Value of the TDRmn register is loaded to timer/counter
trigger bit.
register mn (TCRmn) and detection of the TImn pin
input edge is awaited.
During
Set value of the TDRmn register can be changed.
Counter (TCRmn) counts down each time input edge of
operation
The TCRmn register can always be read.
the TImn pin has been detected. When count value
The TSRmn register is not used.
reaches 0000H, the value of the TDRmn register is loaded
Set values of the TMRmn register, TOMmn, TOLmn,
to the TCRmn register again, and the count operation is
TOmn, and TOEmn bits cannot be changed.
continued. By detecting TCRmn = 0000H, the INTTMmn
output is generated.
After that, the above operation is repeated.
Operation
stop
The TTmn bit is set to 1.
TEmn = 0, and count operation stops.
The TTmn bit automatically returns to 0 because it is a
The TCRmn register holds count value and stops.
trigger bit.
TAU
stop
The TAU0EN and TAU1EN bits of the PER0 and PER2
Note
registers are cleared to 0.
Power-off status
All circuits are initialized and SFR of each channel is
also initialized.
Note 78K0R/KC3-L, 78K0R/KD3-L, 78K0R/KE3-L:
78K0R/KF3-L, 78K0R/KG3-L:
TAU0EN bit of the PER2 register
TAU0EN or TAU1EN bit of the PER0 register
Remark m: Unit number (m = 0, 1), n: Channel number (n = 0 to 7)
78K0R/KC3-L (40-pin):
mn = 02 to 07
78K0R/KC3-L (44-pin, 48-pin):
mn = 00 to 07
78K0R/KD3-L, 78K0R/KE3-L:
mn = 00 to 07
78K0R/KF3-L, 78K0R/KG3-L:
mn = 00 to 07, 10 to 13
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CHAPTER 8 TIMER ARRAY UNIT
8.7.3 Operation as frequency divider (channel 0 of 78K0R/KD3-L, KE3-L, KF3-L. KG3-L only)
The timer array unit can be used as a frequency divider that divides a clock input to the TI00 pin and outputs the result
from the TO00 pin.
The divided clock frequency output from TO00 can be calculated by the following expression.
• When rising edge/falling edge is selected:
Divided clock frequency = Input clock frequency/{(Set value of TDR00 + 1) × 2}
• When both edges are selected:
Divided clock frequency ≅ Input clock frequency/(Set value of TDR00 + 1)
Timer/counter register 00 (TCR00) operates as a down counter in the interval timer mode.
After the channel start trigger bit (TS00) of timer channel start register 0 (TS0) is set to 1, the TCR00 register loads the
value of timer data register 00 (TDR00) when the TI00 valid edge is detected.
If the MD000 bit of timer mode register 00 (TMR00) is 0 at this time, INTTM00 is not output and TO00 is not toggled. If
the MD000 bit of timer mode register 00 (TMR00) is 1, INTTM00 is output and TO00 is toggled.
After that, the TCR00 register counts down at the valid edge of the TI00 pin. When TCR00 = 0000H, it toggles TO00.
At the same time, the TCR00 register loads the value of the TDR00 register again, and continues counting.
If detection of both the edges of the TI00 pin is selected, the duty factor error of the input clock affects the divided clock
period of the TO00 output.
The period of the TO00 output clock includes a sampling error of one period of the operation clock.
Clock period of TO00 output = Ideal TO00 output clock period ± Operation clock period (error)
The TDR00 register can be rewritten at any time. The new value of the TDR00 register becomes valid during the next
count period.
TS00
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Trigger selection
Edge
detection
TI00 pin
Clock selection
Figure 8-49. Block Diagram of Operation as Frequency Divider
Timer counter
register 00 (TCR00)
Output
controller
TO00 pin
Timer data
register 00 (TDR00)
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CHAPTER 8 TIMER ARRAY UNIT
Figure 8-50. Example of Basic Timing of Operation as Frequency Divider (MD000 = 1)
TS00
TE00
TI00
2
2
1
TCR00
0000H
TDR00
2
1
0
1
0
1
0
0002H
1
1
0
0
1
0
0
0001H
TO00
INTTM00
Divided
by 6
Remark TS00:
Divided
by 4
Bit n of timer channel start register 0 (TS0)
TE00:
Bit n of timer channel enable status register 0 (TE0)
TI00:
TI00 pin input signal
TCR00: Timer/counter register 00 (TCR00)
TDR00: Timer data register 00 (TDR00)
TO00:
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CHAPTER 8 TIMER ARRAY UNIT
Figure 8-51. Example of Set Contents of Registers During Operation as Frequency Divider
(a) Timer mode register 00 (TMR00)
15
TMR00
14
13
CKS00
1/0
0
0
12
11
CCS00
MAS
TER00
1
0
10
9
8
7
6
5
4
0
0
STS002 STS001 STS000 CIS001 CIS000
0
0
0
1/0
3
2
1
0
MD003 MD002 MD001 MD000
1/0
0
0
0
1/0
Operation mode of channel 0
000B: Interval timer
Setting of operation when counting is started
0: Neither generates INTTM00 nor inverts
timer output when counting is started.
1: Generates INTTM00 and inverts timer
output when counting is started.
Selection of TI00 pin input edge
00B: Detects falling edge.
01B: Detects rising edge.
10B: Detects both edges.
11B: Setting prohibited
Start trigger selection
000B: Selects only software start.
Slave/master selection
0: Independent channel operation function.
Count clock selection
1: Selects the TI00 pin input valid edge.
Operation clock selection
0: Selects CKm0 as operation clock of channel 0.
1: Selects CKm1 as operation clock of channel 0.
(b) Timer output register 0 (TO0)
Bit 0
TO0
TO00
0: Outputs 0 from TO00.
1/0
1: Outputs 1 from TO00.
(c) Timer output enable register 0 (TOE0)
Bit 0
TOE0
TOE00
1/0
0: Stops the TO00 output operation by counting operation.
1: Enables the TO00 output operation by counting operation.
(d) Timer output level register 0 (TOL0)
Bit 0
TOL0
TOL00
0: Cleared to 0 when TOM00 = 0 (master channel output mode)
0
(e) Timer output mode register 0 (TOM0)
Bit 0
TOM0
TOM00
0: Sets master channel output mode.
0
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CHAPTER 8 TIMER ARRAY UNIT
Figure 8-52. Operation Procedure When Frequency Divider Function Is Used
Software Operation
Hardware Status
TAU
default
setting
Power-off status
(Clock supply is stopped and writing to each register is
disabled.)
Sets the TAU0EN bit of peripheral enable registers 0, 2
Note
(PER0, PER2) to 1.
Power-on status. Each channel stops operating.
(Clock supply is started and writing to each register is
enabled.)
Sets timer clock select register 0 (TPS0).
Determines clock frequencies of CK00 and CK01.
Channel
default
setting
Sets timer mode register mn (TMRmn) (determines
operation mode of channel and selects the detection
edge).
Sets interval (period) value to timer data register 00
(TDR00).
Channel stops operating.
(Clock is supplied and some power is consumed.)
Clears the TOM00 bit of timer output mode register 0
(TOM0) to 0 (master channel output mode).
Clears the TOL00 bit to 0.
Sets the TO00 bit and determines default level of the
TO00 output.
The TO00 pin goes into Hi-Z output state.
Sets the TOE00 bit to 1 and enables operation of TO00.
Clears the port register and port mode register to 0.
Operation is resumed.
Operation
start
Sets the TOE00 bit to 1 (only when operation is
resumed).
Sets the TS00 bit to 1.
The TS00 bit automatically returns to 0 because it is a
trigger bit.
The TO00 default setting level is output when the port mode
register is in output mode and the port register is 0.
TO00 does not change because channel stops operating.
The TO00 pin outputs the TO00 set level.
TE00 = 1, and count operation starts.
Value of the TDR00 register is loaded to timer/counter
register 00 (TCR00) at the count clock input. INTTM00 is
generated and TO00 performs toggle operation if the MD000
bit of the TMR00 register is 1.
During
operation
Set value of the TDR00 register can be changed.
The TCR00 register can always be read.
The TSR00 register is not used.
Set values of the TO0 and TOE0 registers can be
changed.
Set values of the TMR00 register, TOM00, and TOL00
bits cannot be changed.
Counter (TCR00) counts down. When count value reaches
0000H, the value of the TDR00 register is loaded to the
TCR00 register again, and the count operation is continued.
By detecting TCR00 = 0000H, INTTM00 is generated and
TO00 performs toggle operation.
After that, the above operation is repeated.
Operation
stop
The TT00 bit is set to 1.
The TT00 bit automatically returns to 0 because it is a
trigger bit.
TE00 = 0, and count operation stops.
The TCR00 register holds count value and stops.
The TO00 output is not initialized but holds current status.
The TOE00 bit is cleared to 0 and value is set to the TO00 bit.
The TO00 pin outputs the TO00 set level.
TAU
stop
To hold the TO00 pin output level
Clears the TO00 bit to 0 after the value to be held is
set to the port register.
When holding the TO00 pin output level is not
necessary
Switches the port mode register to input mode.
The TAU0EN bit of the PER0 or PER2 register is cleared
Note
to 0.
Note 78K0R/KC3-L, 78K0R/KD3-L, 78K0R/KE3-L:
78K0R/KF3-L, 78K0R/KG3-L:
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The TO00 pin output level is held by port function.
The TO00 pin output level goes into Hi-Z output state.
Power-off status
All circuits are initialized and SFR of each channel is also
initialized.
(The TO00 bit is cleared to 0 and the TO00 pin is set to
port mode).
TAU0EN bit of the PER2 register
TAU0EN bit of the PER0 register
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CHAPTER 8 TIMER ARRAY UNIT
8.7.4 Operation as input pulse interval measurement
The count value can be captured at the TImn valid edge and the interval of the pulse input to TImn can be measured.
The pulse interval can be calculated by the following expression.
TImn input pulse interval = Period of count clock × ((10000H × TSRmn: OVF) + (Capture value of TDRmn + 1))
Caution The TImn pin input is sampled using the operating clock selected with the CKSmn bit of timer
mode register mn (TMRmn), so an error of up to one operating clock cycle occurs.
Timer/counter register mn (TCRmn) operates as an up counter in the capture mode.
When the channel start trigger bit (TSmn) of timer channel start register m (TSm) is set to 1, the TCRmn register counts
up from 0000H in synchronization with the count clock.
When the TImn pin input valid edge is detected, the count value of the TCRmn register is transferred (captured) to
timer data register mn (TDRmn) and, at the same time, the TCRmn register is cleared to 0000H, and the INTTMmn is
output. If the counter overflows at this time, the OVF bit of timer status register mn (TSRmn) is set to 1. If the counter
does not overflow, the OVF bit is cleared. After that, the above operation is repeated.
As soon as the count value has been captured to the TDRmn register, the OVF bit of the TSRmn register is updated
depending on whether the counter overflows during the measurement period. Therefore, the overflow status of the
captured value can be checked.
If the counter reaches a full count for two or more periods, it is judged to be an overflow occurrence, and the OVF bit of
the TSRmn register is set to 1. However, a normal interval value cannot be measured for the OVF bit, if two or more
overflows occur.
Set the STSmn2 to STSmn0 bits of the TMRmn register to 001B to use the valid edges of TImn as a start trigger and a
capture trigger.
When TEmn = 1, a software operation (TSmn = 1) can be used as a capture trigger, instead of using the TImn pin input.
CKm1
Operation clock
CKm0
Edge
detection
TImn pin
TSmn
Trigger selection
Clock selection
Figure 8-53. Block Diagram of Operation as Input Pulse Interval Measurement
Timer counter
register mn (TCRmn)
Timer data
register mn (TDRmn)
Interrupt
controller
Interrupt signal
(INTTMmn)
Remark m: Unit number (m = 0, 1), n: Channel number (n = 0 to 7)
78K0R/KC3-L (40-pin):
mn = 02 to 07
78K0R/KC3-L (44-pin, 48-pin):
mn = 00 to 07
78K0R/KD3-L, 78K0R/KE3-L:
mn = 00 to 07
78K0R/KF3-L, 78K0R/KG3-L:
mn = 00 to 07, 10 to 13
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Figure 8-54. Example of Basic Timing of Operation as Input Pulse Interval Measurement (MDmn0 = 0)
TSmn
TEmn
TImn
FFFFH
b
a
TCRmn
d
c
0000H
TDRmn
0000H
a
b
c
d
INTTMmn
OVF
Remarks 1. m: Unit number (m = 0, 1), n: Channel number (n = 0 to 7)
78K0R/KC3-L (40-pin):
mn = 02 to 07
78K0R/KC3-L (44-pin, 48-pin): mn = 00 to 07
78K0R/KD3-L, 78K0R/KE3-L:
mn = 00 to 07
78K0R/KF3-L, 78K0R/KG3-L:
mn = 00 to 07, 10 to 13
2. TSmn:
Bit n of timer channel start register m (TSm)
TEmn:
Bit n of timer channel enable status register m (TEm)
TImn:
TImn pin input signal
TCRmn:
Timer/counter register mn (TCRmn)
TDRmn:
Timer data register mn (TDRmn)
OVF:
Bit 0 of timer status register mn (TSRmn)
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Figure 8-55. Example of Set Contents of Registers to Measure Input Pulse Interval
(a) Timer mode register mn (TMRmn)
15
TMRmn
14
13
11
10
9
8
7
6
5
4
0
0
MAS
CCSmn
STSmn2 STSmn1 STSmn0 CISmn1 CISmn0
TERmn
CKSmn
1/0
12
0
0
0
0
0
0
1
1/0
3
2
1
0
MDmn3 MDmn2 MDmn1 MDmn0
1/0
0
1
0
1/0
Operation mode of channel n
010B: Capture mode
Setting of operation when counting is started
0: Does not generate INTTMmn when
counting is started.
1: Generates INTTMmn when counting is
started.
Selection of TImn pin input edge
00B: Detects falling edge.
01B: Detects rising edge.
10B: Detects both edges.
11B: Setting prohibited
Capture trigger selection
001B: Selects the TImn pin input valid edge.
Slave/master selection
0: Independent channel operation function.
Count clock selection
0: Selects operation clock.
Operation clock selection
0: Selects CKm0 as operation clock of channel n.
1: Selects CKm1 as operation clock of channel n.
(b) Timer output register m (TOm)
Bit n
TOm
TOmn
0: Outputs 0 from TOmn.
0
(c) Timer output enable register m (TOEm)
Bit n
TOEm
TOEmn
0: Stops TOmn output operation by counting operation.
0
(d) Timer output level register m (TOLm)
Bit n
TOLm
TOLmn
0: Cleared to 0 when TOMmn = 0 (master channel output mode).
0
(e) Timer output mode register m (TOMm)
Bit n
TOMm
TOMmn
0: Sets master channel output mode.
0
Remark m: Unit number (m = 0, 1), n: Channel number (n = 0 to 7)
78K0R/KC3-L (40-pin):
mn = 02 to 07
78K0R/KC3-L (44-pin, 48-pin):
mn = 00 to 07
78K0R/KD3-L, 78K0R/KE3-L:
mn = 00 to 07
78K0R/KF3-L, 78K0R/KG3-L:
mn = 00 to 07, 10 to 13
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Figure 8-56. Operation Procedure When Input Pulse Interval Measurement Function Is Used
Software Operation
Hardware Status
Power-off status
TAU
default
(Clock supply is stopped and writing to each register is
setting
disabled.)
Sets the TAU0EN and TAU1EN bits of peripheral enable
Note
registers 0, 2 (PER0, PER2) to 1.
Power-on status. Each channel stops operating.
(Clock supply is started and writing to each register is
enabled.)
Sets timer clock select register m (TPSm).
Determines clock frequencies of CKm0 and CKm1.
Channel
Sets timer mode register mn (TMRmn) (determines
Channel stops operating.
default
operation mode of channel).
(Clock is supplied and some power is consumed.)
Sets TSmn bit to 1.
TEmn = 1, and count operation starts.
setting
Operation
start
The TSmn bit automatically returns to 0 because it is a
Timer/counter register mn (TCRmn) is cleared to 0000H
trigger bit.
at the count clock input.
When the MDmn0 bit of the TMRmn register is 1,
Operation is resumed.
INTTMmn is generated.
During
Set values of only the CISmn1 and CISmn0 bits of the
Counter (TCRmn) counts up from 0000H. When the TImn
operation
TMRmn register can be changed.
pin input valid edge is detected, the count value is
The TDRmn register can always be read.
transferred (captured) to timer data register mn (TDRmn).
The TCRmn register can always be read.
At the same time, the TCRmn register is cleared to
The TSRmn register can always be read.
0000H, and the INTTMmn signal is generated.
Set values of the TOMmn, TOLmn, TOmn, and TOEmn
If an overflow occurs at this time, the OVF bit of timer
bits cannot be changed.
status register mn (TSRmn) is set; if an overflow does not
occur, the OVF bit is cleared.
After that, the above operation is repeated.
Operation
stop
TAU
stop
The TTmn bit is set to 1.
TEmn = 0, and count operation stops.
The TTmn bit automatically returns to 0 because it is a
The TCRmn register holds count value and stops.
trigger bit.
The OVF bit of the TSRmn register is also held.
The TAU0EN and TAU1EN bits of the PER0 and PER2
Note
registers are cleared to 0.
Power-off status
All circuits are initialized and SFR of each channel is
also initialized.
Note 78K0R/KC3-L, 78K0R/KD3-L, 78K0R/KE3-L:
78K0R/KF3-L, 78K0R/KG3-L:
TAU0EN bit of the PER2 register
TAU0EN or TAU1EN bit of the PER0 register
Remark m: Unit number (m = 0, 1), n: Channel number (n = 0 to 7)
78K0R/KC3-L (40-pin):
mn = 02 to 07
78K0R/KC3-L (44-pin, 48-pin): mn = 00 to 07
78K0R/KD3-L, 78K0R/KE3-L:
mn = 00 to 07
78K0R/KF3-L, 78K0R/KG3-L:
mn = 00 to 07, 10 to 13
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8.7.5 Operation as input signal high-/low-level width measurement
Caution When using a channel to implement the LIN-bus, set bit 1 (ISC1) of the input switch control
register (ISC) to 1. In the following descriptions, read TImn as RxD0 if using the 78K0R/KC3-L,
78K0R/KD3-L, or 78K0R/KE3-L, and as RxD3 if using the 78K0R/KF3-L or 78K0R/KG3-L.
By starting counting at one edge of the TImn pin input and capturing the number of counts at another edge, the signal
width (high-level width/low-level width) of TImn can be measured. The signal width of TImn can be calculated by the
following expression.
Signal width of TImn input = Period of count clock × ((10000H × TSRmn: OVF) + (Capture value of TDRmn + 1))
Caution The TImn pin input is sampled using the operating clock selected with the CKSmn bit of timer
mode register mn (TMRmn), so an error equivalent to one operation clock occurs.
Timer/counter register mn (TCRmn) operates as an up counter in the capture & one-count mode.
When the channel start trigger bit (TSmn) of timer channel start register m (TSm) is set to 1, the TEmn bit is set to 1
and the TImn pin start edge detection wait status is set.
When the TImn pin input start edge (rising edge of the TImn pin input when the high-level width is to be measured) is
detected, the counter counts up from 0000H in synchronization with the count clock. When the valid capture edge (falling
edge of the TImn pin input when the high-level width is to be measured) is detected later, the count value is transferred to
timer data register mn (TDRmn) and, at the same time, INTTMmn is output. If the counter overflows at this time, the OVF
bit of timer status register mn (TSRmn) is set to 1. If the counter does not overflow, the OVF bit is cleared. The TCRmn
register stops at the value “value transferred to the TDRmn register + 1”, and the TImn pin start edge detection wait status
is set. After that, the above operation is repeated.
As soon as the count value has been captured to the TDRmn register, the OVF bit of the TSRmn register is updated
depending on whether the counter overflows during the measurement period. Therefore, the overflow status of the
captured value can be checked.
If the counter reaches a full count for two or more periods, it is judged to be an overflow occurrence, and the OVF bit of
the TSRmn register is set to 1. However, a normal interval value cannot be measured for the OVF bit, if two or more
overflows occur.
Whether the high-level width or low-level width of the TImn pin is to be measured can be selected by using the CISmn1
and CISmn0 bits of the TMRmn register.
Because this function is used to measure the signal width of the TImn pin input, the TSmn bit cannot be set to 1 while
the TEmn bit is 1.
CISmn1, CISmn0 of TMRmn register = 10B: Low-level width is measured.
CISmn1, CISmn0 of TMRmn register = 11B: High-level width is measured.
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Operation clock
Clock selection
Figure 8-57. Block Diagram of Operation as Input Signal High-/Low-Level Width Measurement
CKm1
Edge
detection
TImn pin
Timer counter
register mn (TCRmn)
Trigger selection
CKm0
Timer data
register mn (TDRmn)
Interrupt
controller
Interrupt signal
(INTTMmn)
Figure 8-58. Example of Basic Timing of Operation as Input Signal High-/Low-Level Width Measurement
TSmn
TEmn
TImn
FFFFH
a
b
TCRmn
c
0000H
TDRmn
a
0000H
b
c
INTTMmn
OVF
Remarks 1. m: Unit number (m = 0, 1), n: Channel number (n = 0 to 7)
However, in case of the timer input pin (TImn) , mn changes as below.
78K0R/KC3-L (40-pin):
mn = 02 to 07
78K0R/KC3-L (44-pin, 48-pin): mn = 00 to 07
78K0R/KD3-L, 78K0R/KE3-L:
mn = 00 to 07
78K0R/KF3-L, 78K0R/KG3-L:
mn = 00 to 07, 10 to 13
2. TSmn:
TEmn:
Bit n of timer channel start register m (TSm)
Bit n of timer channel enable status register m (TEm)
TImn:
TImn pin input signal
TCRmn:
Timer/counter register mn (TCRmn)
TDRmn:
Timer data register mn (TDRmn)
OVF:
Bit 0 of timer status register mn (TSRmn)
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Figure 8-59. Example of Set Contents of Registers to Measure Input Signal High-/Low-Level Width
(a) Timer mode register mn (TMRmn)
15
TMRmn
14
13
11
10
9
8
7
6
5
4
0
0
MAS
CCSmn
STSmn2 STSmn1 STSmn0 CISmn1 CISmn0
TERmn
CKSmn
1/0
12
0
0
0
0
0
1
0
1
3
2
1
0
MDmn3 MDmn2 MDmn1 MDmn0
1/0
1
1
0
0
Operation mode of channel n
110B: Capture & one-count
Setting of operation when counting is started
0: Does not generate INTTMmn when
counting is started.
Selection of TImn pin input edge
10B: Both edges (to measure low-level width)
11B: Both edges (to measure high-level width)
Start trigger selection
010B: Selects the TImn pin input valid edge.
Slave/master selection
0: Independent channel operation function.
Count clock selection
0: Selects operation clock.
Operation clock selection
0: Selects CKm0 as operation clock of channel n.
1: Selects CKm1 as operation clock of channel n.
(b) Timer output register m (TOm)
Bit n
TOm
TOmn
0: Outputs 0 from TOmn.
0
(c) Timer output enable register m (TOEm)
Bit n
TOEm
TOEmn
0: Stops the TOmn output operation by counting operation.
0
(d) Timer output level register m (TOLm)
Bit n
TOLm
TOLmn
0: Cleared to 0 when TOMmn = 0 (master channel output mode).
0
(e) Timer output mode register m (TOMm)
Bit n
TOMm
TOMmn
0: Sets master channel output mode.
0
Remark
m: Unit number (m = 0, 1), n: Channel number (n = 0 to 7)
However, in case of the timer input pin (TImn) and the timer output pin (TOmn), mn changes as below.
78K0R/KC3-L (40-pin):
mn = 02 to 07
78K0R/KC3-L (44-pin, 48-pin):
mn = 00 to 07
78K0R/KD3-L, 78K0R/KE3-L:
mn = 00 to 07
78K0R/KF3-L, 78K0R/KG3-L:
mn = 00 to 07, 10 to 13
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Figure 8-60. Operation Procedure When Input Signal High-/Low-Level Width Measurement Function Is Used
Software Operation
Hardware Status
Power-off status
TAU
default
(Clock supply is stopped and writing to each register is
setting
disabled.)
Sets the TAU0EN and TAU1EN bits of peripheral enable
Note
registers 0, 2 (PER0, PER2) to 1.
Power-on status. Each channel stops operating.
(Clock supply is started and writing to each register is
enabled.)
Sets timer clock select register m (TPSm).
Determines clock frequencies of CKm0 and CKm1.
Channel
Sets timer mode register mn (TMRmn) (determines
Channel stops operating.
default
operation mode of channel).
(Clock is supplied and some power is consumed.)
setting
Clears the TOEmn bit to 0 and stops operation of TOmn.
Operation
Sets the TSmn bit to 1.
start
TEmn = 1, and the TImn pin start edge detection wait
The TSmn bit automatically returns to 0 because it is a
status is set.
trigger bit.
Operation is resumed.
Detects the TImn pin input count start valid edge.
Clears timer/counter register mn (TCRmn) to 0000H and
starts counting up.
During
Set value of the TDRmn register can be changed.
When the TImn pin start edge is detected, the counter
operation
The TCRmn register can always be read.
(TCRmn) counts up from 0000H. If a capture edge of the
The TSRmn register is not used.
TImn pin is detected, the count value is transferred to
Set values of the TMRmn register, TOMmn, TOLmn,
timer data register mn (TDRmn) and INTTMmn is
TOmn, and TOEmn bits cannot be changed.
generated.
If an overflow occurs at this time, the OVF bit of timer
status register mn (TSRmn) is set; if an overflow does not
occur, the OVF bit is cleared. The TCRmn register stops
the count operation until the next TImn pin start edge is
detected.
Operation
stop
TAU
The TTmn bit is set to 1.
TEmn = 0, and count operation stops.
The TTmn bit automatically returns to 0 because it is a
The TCRmn register holds count value and stops.
trigger bit.
The OVF bit of the TSRmn register is also held.
The TAU0EN and TAU1EN bits of the PER0 and PER2
Note
registers are cleared to 0.
stop
Power-off status
All circuits are initialized and SFR of each channel is
also initialized.
Note 78K0R/KC3-L, 78K0R/KD3-L, 78K0R/KE3-L:
78K0R/KF3-L, 78K0R/KG3-L:
Remark
TAU0EN bit of the PER2 register
TAU0EN or TAU1EN bit of the PER0 register
m: Unit number (m = 0, 1), n: Channel number (n = 0 to 7)
However, in case of the timer input pin (TImn) and the timer output pin (TOmn), mn changes as below.
78K0R/KC3-L (40-pin):
mn = 02 to 07
78K0R/KC3-L (44-pin, 48-pin):
mn = 00 to 07
78K0R/KD3-L, 78K0R/KE3-L:
mn = 00 to 07
78K0R/KF3-L, 78K0R/KG3-L:
mn = 00 to 07, 10 to 13
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8.8 Simultaneous Channel Operation Function of Timer Array Unit
8.8.1 Operation as one-shot pulse output function
By using two channels as a set, a one-shot pulse having any delay pulse width can be generated from the signal input
to the TImn pin.
The delay time and pulse width can be calculated by the following expressions.
Delay time = {Set value of TDRmn (master) + 2} × Count clock period
Pulse width = {Set value of TDRmp (slave)} × Count clock period
The master channel operates in the one-count mode and counts the delays. Timer/counter register mn (TCRmn) of the
master channel starts operating upon start trigger detection and loads the value of timer data register mn (TDRmn).
The TCRmn register counts down from the value of the TDRmn register it has loaded, in synchronization with the count
clock. When TCRmn = 0000H, it outputs INTTMmn and stops counting until the next start trigger is detected.
The slave channel operates in the one-count mode and counts the pulse width. The TCRmp register of the slave
channel starts operation using INTTMmn of the master channel as a start trigger, and loads the value of the TDRmp
register. The TCRmp register counts down from the value of The TDRmp register it has loaded, in synchronization with
the count value. When count value = 0000H, it outputs INTTMmp and stops counting until the next start trigger (INTTMmn
of the master channel) is detected.
The output level of TOmp becomes active one count clock after generation of
INTTMmn from the master channel, and inactive when TCRmp = 0000H.
Instead of using the TImn pin input, a one-shot pulse can also be output using the software operation (TSmn = 1) as a
start trigger.
Caution The timing of loading of timer data register mn (TDRmn) of the master channel is different from that of
the TDRmp register of the slave channel. If the TDRmn and TDRmp registers are rewritten during
operation, therefore, an illegal waveform is output. Rewrite the TDRmn register after INTTMmn is
generated and the TDRmp register after INTTMmp is generated.
Remark
m: Unit number (m = 0, 1), n: Channel number (n = 0, 2, 4, 6)
78K0R/KC3-L, 78K0R/KD3-L, 78K0R/KE3-L: mn = 00, 02, 04, 06
78K0R/KF3-L, 78K0R/KG3-L:
mn = 00, 02, 04, 06, 10, 12
Note
p: Slave channel number
When m = 0: n < p ≤ 7
When m = 1: n < p ≤ 3
Note
Since there is no function of timer I/O, the channel 1 in the 78K0R/KC3-L (40-pin) can not be used as the
slave channel.
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Figure 8-61. Block Diagram of Operation as One-Shot Pulse Output Function
Clock selection
Master channel
(one-count mode)
CKm1
Operation clock
Trigger selection
CKm0
TSmn
Edge
detection
TImn pin
Timer counter
register mn (TCRmn)
Timer data
register mn (TDRmn)
Interrupt
controller
Timer counter
register mp (TCRmp)
Output
controller
Timer data
register mp (TDRmp)
Interrupt
controller
Interrupt signal
(INTTMmn)
Clock selection
Slave channel
(one-count mode)
CKm1
Operation clock
Trigger selection
CKm0
Remark
TOmp pin
Interrupt signal
(INTTMmp)
m: Unit number (m = 0, 1), n: Channel number (n = 0, 2, 4, 6)
78K0R/KC3-L, 78K0R/KD3-L, 78K0R/KE3-L: mn = 00, 02, 04, 06
78K0R/KF3-L, 78K0R/KG3-L:
mn = 00, 02, 04, 06, 10, 12
Note
p: Slave channel number
When m = 0: n < p ≤ 7
When m = 1: n < p ≤ 3
Note
Since there is no function of timer I/O, the channel 1 in the 78K0R/KC3-L (40-pin) can not be used as the
slave channel.
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CHAPTER 8 TIMER ARRAY UNIT
Figure 8-62. Example of Basic Timing of Operation as One-Shot Pulse Output Function
TSmn
TEmn
TImn
Master
channel
FFFFH
TCRmn
0000H
TDRmn
a
TOmn
INTTMmn
TSmp
TEmp
FFFFH
TCRmp
Slave
channel
0000H
TDRmp
b
TOmp
INTTMmp
a+2
b
a+2
b
Remarks 1. m: Unit number (m = 0, 1), n: Channel number (n = 0, 2, 4, 6)
78K0R/KC3-L, 78K0R/KD3-L, 78K0R/KE3-L: mn = 00, 02, 04, 06
78K0R/KF3-L, 78K0R/KG3-L:
mn = 00, 02, 04, 06, 10, 12
p: Slave channel numberNote
When m = 0: n < p ≤ 7
When m = 1: n < p ≤3
Note Since there is no function of timer I/O, the channel 1 in the 78K0R/KC3-L (40-pin) can not be
used as the slave channel.
2. TSmn, TSmp:
Bit n, m of timer channel start register m (TSm)
TEmn, TEmp:
Bit n, m of timer channel enable status register m (TEm)
TImn, TImp:
TImn and TImp pins input signal
TCRmn, TCRmp: Timer/counter registers mn, mp (TCRmn, TCRmp)
TDRmn, TDRmp: Timer data registers mn, mp (TDRmn, TDRmp)
TOmn, TOmp:
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Figure 8-63. Example of Set Contents of Registers When One-Shot Pulse Output Function Is Used (Master Channel)
(a) Timer mode register mn (TMRmn)
15
TMRmn
14
13
CKSmn
1/0
12
CCSmn
0
0
0
11
10
9
8
7
6
5
4
MAS
STSmn2 STSmn1 STSmn0 CISmn1 CISmn0
TERmn
1
0
0
1
1/0
3
2
1
0
MDmn3 MDmn2 MDmn1 MDmn0
1/0
0
1
0
0
0
0
Operation mode of channel n
100B: One-count mode
Start trigger during operation
0: Trigger input is invalid.
Selection of TImn pin input edge
00B: Detects falling edge.
01B: Detects rising edge.
10B: Detects both edges.
11B: Setting prohibited
Start trigger selection
001B: Selects the TImn pin input valid edge.
Slave/master selection
1: Master channel.
Count clock selection
0: Selects operation clock.
Operation clock selection
0: Selects CKm0 as operation clock of channels n.
1: Selects CKm1 as operation clock of channels n.
(b) Timer output register m (TOm)
Bit n
TOm
TOmn
0: Outputs 0 from TOmn.
0
(c) Timer output enable register m (TOEm)
Bit n
TOEm
TOEmn
0: Stops the TOmn output operation by counting operation.
0
(d) Timer output level register m (TOLm)
Bit n
TOLm
TOLmn
0: Cleared to 0 when TOMmn = 0 (master channel output mode).
0
(e) Timer output mode register m (TOMm)
Bit n
TOMm
TOMmn
0: Sets master channel output mode.
0
Remark m: Unit number (m = 0, 1), n: Channel number (n = 0, 2, 4, 6)
78K0R/KC3-L, 78K0R/KD3-L, 78K0R/KE3-L: mn = 00, 02, 04, 06
78K0R/KF3-L, 78K0R/KG3-L:
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CHAPTER 8 TIMER ARRAY UNIT
Figure 8-64. Example of Set Contents of Registers When One-Shot Pulse Output Function Is Used (Slave Channel)
(a) Timer mode register mp (TMRmp)
15
TMRmp
14
13
CKSmp
1/0
12
CCSmp
0
0
0
11
10
9
8
7
6
5
4
MAS
STSmp2 STSmp1 STSmp0 CISmp1 CISmp0
TERmp
0
1
0
0
0
3
2
1
0
MDmp3 MDmp2 MDmp1 MDmp0
0
0
0
1
0
0
0
Operation mode of channel p
100B: One-count mode
Start trigger during operation
0: Trigger input is invalid.
Selection of TImp pin input edge
00B: Sets 00B because these are not used.
Start trigger selection
100B: Selects INTTMmn of master channel.
Slave/master selection
0: Slave channel.
Count clock selection
0: Selects operation clock.
Operation clock selection
0: Selects CKm0 as operation clock of channel p.
1: Selects CKm1 as operation clock of channel p.
* Make the same setting as master channel.
(b) Timer output register m (TOm)
Bit p
TOm
TOmp
0: Outputs 0 from TOmp.
1/0
1: Outputs 1 from TOmp.
(c) Timer output enable register m (TOEm)
Bit p
TOEm
TOEmp
1/0
0: Stops the TOmp output operation by counting operation.
1: Enables the TOmp output operation by counting operation.
(d) Timer output level register m (TOLm)
Bit p
TOLm
TOLmp
1/0
0: Positive logic output (active-high)
1: Inverted output (active-low)
(e) Timer output mode register m (TOMm)
Bit p
TOMm
TOMmp
1: Sets the slave channel output mode.
1
Remark
m: Unit number (m = 0, 1), n: Channel number (n = 0, 2, 4, 6)
78K0R/KC3-L, 78K0R/KD3-L, 78K0R/KE3-L: mn = 00, 02, 04, 06
78K0R/KF3-L, 78K0R/KG3-L:
mn = 00, 02, 04, 06, 10, 12
p: Slave channel numberNote
When m = 0: n < p ≤ 7
When m = 1: n < p ≤ 3
Note
Since there is no function of timer I/O, the channel 1 in the 78K0R/KC3-L (40-pin) can not be used
as the slave channel.
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Figure 8-65. Operation Procedure of One-Shot Pulse Output Function (1/2)
Software Operation
Hardware Status
Power-off status
TAU
default
(Clock supply is stopped and writing to each register is
setting
disabled.)
Sets the TAU0EN and TAU1EN bits of peripheral enable
Note
registers 0, 2 (PER0, PER2) to 1.
Power-on status. Each channel stops operating.
(Clock supply is started and writing to each register is
enabled.)
Sets timer clock select register m (TPSm).
Determines clock frequencies of CKm0 and CKm1.
Channel
Sets timer mode register mn, mp (TMRmn, TMRmp) of
Channel stops operating.
default
two channels to be used (determines operation mode of
(Clock is supplied and some power is consumed.)
setting
channels).
An output delay is set to timer data register mn (TDRmn)
of the master channel, and a pulse width is set to the
TDRmp register of the slave channel.
Sets slave channel.
The TOmp pin goes into Hi-Z output state.
The TOMmp bit of timer output mode register m
(TOMm) is set to 1 (slave channel output mode).
Sets the TOLmp bit.
Sets the TOmp bit and determines default level of the
TOmp output.
The TOmp default setting level is output when the port
mode register is in output mode and the port register is 0.
Sets the TOEmp bit to 1 and enables operation of TOmp.
TOmp does not change because channel stops operating.
Clears the port register and port mode register to 0.
The TOmp pin outputs the TOmp set level.
(Note and Remark are listed on the next page.)
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Figure 8-65. Operation Procedure of One-Shot Pulse Output Function (2/2)
Software Operation
Sets the TOEmp bit (slave) to 1 (only when operation is
resumed).
The TSmn (master) and TSmp (slave) bits of timer
channel start register m (TSm) are set to 1 at the same
time.
The TSmn and TSmp bits automatically return to 0
because they are trigger bits.
The TEmn and TEmp bits are set to 1 and the master
channel enters the TImn input edge detection wait status.
Counter stops operating.
Detects the TImn pin input valid edge of master channel.
Master channel starts counting.
During
operation
Set values of only the CISmn1 and CISmn0 bits of the
TMRmn register can be changed.
Set values of the TMRmp, TDRmn, TDRmp registers,
TOMmn, TOMmp, TOLmn, and TOLmp bits cannot be
changed.
The TCRmn and TCRmp registers can always be read.
The TSRmn and TSRmp registers are not used.
Set values of the TOm and TOEm registers can be
changed.
Master channel loads the value of the TDRmn register to
timer/counter register mn (TCRmn) when the TImn pin
valid input edge is detected, and the counter starts
counting down. When the count value reaches TCRmn =
0000H, the INTTMmn output is generated, and the counter
stops until the next valid edge is input to the TImn pin.
The slave channel, triggered by INTTMmn of the master
channel, loads the value of the TDRmp register to the
TCRmp register, and the counter starts counting down.
The output level of TOmp becomes active one count clock
after generation of INTTMmn from the master channel. It
becomes inactive when TCRmp = 0000H, and the
counting operation is stopped.
After that, the above operation is repeated.
Operation
stop
The TTmn (master) and TTmp (slave) bits are set to 1 at
the same time.
The TTmn and TTmp bits automatically return to 0
because they are trigger bits.
Operation is resumed.
Operation
start
Hardware Status
TAU
stop
TEmn, TEmp = 0, and count operation stops.
The TCRmn and TCRmp registers hold count value and
stop.
The TOmp output is not initialized but holds current
status.
The TOEmp bit of slave channel is cleared to 0 and
value is set to the TOmp bit.
The TOmp pin outputs the TOmp set level.
To hold the TOmp pin output level
Clears the TOmp bit to 0 after the value to
be held is set to the port register.
The TOmp pin output level is held by port function.
When holding the TOmp pin output level is not
necessary
Switches the port mode register to input mode.
The TOmp pin output level goes into Hi-Z output state.
The TAU0EN and TAU1EN bits of the PER0 and PER2
Note
registers are cleared to 0.
Power-off status
All circuits are initialized and SFR of each channel is
also initialized.
(The TOmp bit is cleared to 0 and the TOmp pin is set to
port mode.)
Note 78K0R/KC3-L, 78K0R/KD3-L, 78K0R/KE3-L: TAU0EN bit of the PER2 register
78K0R/KF3-L, 78K0R/KG3-L:
TAU0EN or TAU1EN bit of the PER0 register
Remark m: Unit number (m = 0, 1), n: Channel number (n = 0, 2, 4, 6)
78K0R/KC3-L, 78K0R/KD3-L, 78K0R/KE3-L: mn = 00, 02, 04, 06
78K0R/KF3-L, 78K0R/KG3-L:
mn = 00, 02, 04, 06, 10, 12
p: Slave channel numberNote
When m = 0: n < p ≤ 7
When m = 1: n < p ≤ 3
Note
Since there is no function of timer I/O, the channel 1 in the 78K0R/KC3-L (40-pin) can not be used as
the slave channel.
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8.8.2 Operation as PWM function
Two channels can be used as a set to generate a pulse of any period and duty factor.
The period and duty factor of the output pulse can be calculated by the following expressions.
Pulse period = {Set value of TDRmn (master) + 1} × Count clock period
Duty factor [%] = {Set value of TDRmp (slave)}/{Set value of TDRmn (master) + 1} × 100
0% output:
Set value of TDRmp (slave) = 0000H
100% output: Set value of TDRmp (slave) ≥ {Set value of TDRmn (master) + 1}
Remark
The duty factor exceeds 100% if the set value of TDRmp (slave) > (set value of TDRmn (master) + 1), it
summarizes to 100% output.
The master channel operates in the interval timer mode. If the channel start trigger bit (TSmn) of timer channel start
register m (TSm) is set to 1, an interrupt (INTTMmn) is output, the value set to timer data register mn (TDRmn) is loaded
to timer/counter register mn (TCRmn), and the counter counts down in synchronization with the count clock. When the
counter reaches 0000H, INTTMmn is output, the value of the TDRmn register is loaded again to the TCRmn register, and
the counter counts down. This operation is repeated until the channel stop trigger bit (TTmn) of timer channel stop
register m (TTm) is set to 1.
If two channels are used to output a PWM waveform, the period until the master channel counts down to 0000H is the
PWM output (TOmp) cycle.
The slave channel operates in one-count mode. By using INTTMmn from the master channel as a start trigger, the
TCRmp register loads the value of the TDRmp register and the counter counts down to 0000H. When the counter
reaches 0000H, it outputs INTTMmp and waits until the next start trigger (INTTMmn from the master channel) is generated.
If two channels are used to output a PWM waveform, the period until the slave channel counts down to 0000H is the
PWM output (TOmp) duty.
PWM output (TOmp) goes to the active level one clock after the master channel generates INTTMmn and goes to the
inactive level when the TCRmp register of the slave channel becomes 0000H.
Caution
To rewrite both timer data register mn (TDRmn) of the master channel and the TDRmp register of the
slave channel, a write access is necessary two times. The timing at which the values of the TDRmn
and TDRmp registers are loaded to the TCRmn and TCRmp registers is upon occurrence of INTTMmn
of the master channel.
Thus, when rewriting is performed split before and after occurrence of
INTTMmn of the master channel, the TOmp pin cannot output the expected waveform. To rewrite both
the TDRmn register of the master and the TDRmp register of the slave, therefore, be sure to rewrite
both the registers immediately after INTTMmn is generated from the master channel.
Remark
m: Unit number (m = 0, 1), n: Channel number (n = 0, 2, 4, 6)
78K0R/KC3-L, 78K0R/KD3-L, 78K0R/KE3-L: mn = 00, 02, 04, 06
78K0R/KF3-L, 78K0R/KG3-L:
mn = 00, 02, 04, 06, 10, 12
p: Slave channel numberNote
When m = 0: n < p ≤ 7
When m = 1: n < p ≤ 3
Note
Since there is no function of timer I/O, the channel 1 in the 78K0R/KC3-L (40-pin) can not be used as
the slave channel.
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CHAPTER 8 TIMER ARRAY UNIT
CKm1
Operation clock
CKm0
TSmn
Trigger selection
Master channel
(interval timer mode)
Clock selection
Figure 8-66. Block Diagram of Operation as PWM Function
Timer counter
register mn (TCRmn)
Timer data
register mn (TDRmn)
Interrupt
controller
Timer counter
register mp (TCRmp)
Output
controller
Timer data
register mp (TDRmp)
Interrupt
controller
Interrupt signal
(INTTMmn)
CKm1
Operation clock
Trigger selection
CKm0
Clock selection
Slave channel
(one-count mode)
Remark
TOmp pin
Interrupt signal
(INTTMmp)
m: Unit number (m = 0, 1), n: Channel number (n = 0, 2, 4, 6)
78K0R/KC3-L, 78K0R/KD3-L, 78K0R/KE3-L: mn = 00, 02, 04, 06
78K0R/KF3-L, 78K0R/KG3-L:
mn = 00, 02, 04, 06, 10, 12
p: Slave channel numberNote
When m = 0: n < p ≤ 7
When m = 1: n < p ≤ 3
Note
Since there is no function of timer I/O, the channel 1 in the 78K0R/KC3-L (40-pin) can not be used as
the slave channel.
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CHAPTER 8 TIMER ARRAY UNIT
Figure 8-67. Example of Basic Timing of Operation as PWM Function
TSmn
TEmn
FFFFH
Master
channel
TCRmn
0000H
TDRmn
a
b
TOmn
INTTMmn
TSmp
TEmp
FFFFH
Slave
channel
TCRmp
0000H
TDRmp
c
d
TOmp
INTTMmp
a+1
c
a+1
c
b+1
d
Remark 1. m: Unit number (m = 0, 1), n: Channel number (n = 0, 2, 4, 6)
78K0R/KC3-L, 78K0R/KD3-L, 78K0R/KE3-L: mn = 00, 02, 04, 06
78K0R/KF3-L, 78K0R/KG3-L:
p: Slave channel number
mn = 00, 02, 04, 06, 10, 12
Note
When m = 0: n < p ≤ 7
When m = 1: n < p ≤ 3
Note Since there is no function of timer I/O, the channel 1 in the 78K0R/KC3-L (40-pin) can not be
used as the slave channel.
2. TSmn, TSmp:
TEmn, TEmp:
Bit n, m of timer channel start register m (TSm)
Bit n, m of timer channel enable status register m (TEm)
TCRmn, TCRmp: Timer/counter registers mn, mp (TCRmn, TCRmp)
TDRmn, TDRmp: Timer data registers mn, mp (TDRmn, TDRmp)
TOmn, TOmp:
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CHAPTER 8 TIMER ARRAY UNIT
Figure 8-68. Example of Set Contents of Registers When PWM Function (Master Channel) Is Used
(a) Timer mode register mn (TMRmn)
15
TMRmn
14
13
11
10
9
8
7
6
5
4
0
0
MAS
CCSmn
STSmn2 STSmn1 STSmn0 CISmn1 CISmn0
TERmn
CKSmn
1/0
12
0
0
0
1
0
0
0
0
3
2
1
0
MDmn3 MDmn2 MDmn1 MDmn0
0
0
0
0
1
Operation mode of channel n
000B: Interval timer
Setting of operation when counting is started
1: Generates INTTMmn when counting is
started.
Selection of TImn pin input edge
00B: Sets 00B because these are not used.
Start trigger selection
000B: Selects only software start.
Slave/master selection
1: Master channel.
Count clock selection
0: Selects operation clock.
Operation clock selection
0: Selects CKm0 as operation clock of channel n.
1: Selects CKm1 as operation clock of channel n.
(b) Timer output register m (TOm)
Bit n
TOm
TOmn
0: Outputs 0 from TOmn.
0
(c) Timer output enable register m (TOEm)
Bit n
TOEm
TOEmn
0: Stops the TOmn output operation by counting operation.
0
(d) Timer output level register m (TOLm)
Bit n
TOLm
TOLmn
0: Cleared to 0 when TOMmn = 0 (master channel output mode).
0
(e) Timer output mode register m (TOMm)
Bit n
TOMm
TOMmn
0: Sets master channel output mode.
0
Remark
m: Unit number (m = 0, 1), n: Channel number (n = 0, 2, 4, 6)
78K0R/KC3-L, 78K0R/KD3-L, 78K0R/KE3-L: mn = 00, 02, 04, 06
78K0R/KF3-L, 78K0R/KG3-L:
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CHAPTER 8 TIMER ARRAY UNIT
Figure 8-69. Example of Set Contents of Registers When PWM Function (Slave Channel) Is Used
(a) Timer mode register mp (TMRmp)
15
TMRmp
14
13
CKSmp
1/0
12
CCSmp
0
0
0
11
10
9
8
7
6
5
4
MAS
STSmp2 STSmp1 STSmp0 CISmp1 CISmp0
TERmp
0
1
0
0
0
3
2
1
0
MDmp3 MDmp2 MDmp1 MDmp0
0
0
0
1
0
0
1
Operation mode of channel p
100B: One-count mode
Start trigger during operation
1: Trigger input is valid.
Selection of TImp pin input edge
00B: Sets 00B because these are not used.
Start trigger selection
100B: Selects INTTMmn of master channel.
Slave/master selection
0: Slave channel.
Count clock selection
0: Selects operation clock.
Operation clock selection
0: Selects CKm0 as operation clock of channel p.
1: Selects CKm1 as operation clock of channel p.
* Make the same setting as master channel.
(b) Timer output register m (TOm)
Bit p
TOm
TOmp
0: Outputs 0 from TOmp.
1/0
1: Outputs 1 from TOmp.
(c) Timer output enable register m (TOEm)
Bit p
TOEm
TOEmp
1/0
0: Stops the TOmp output operation by counting operation.
1: Enables the TOmp output operation by counting operation.
(d) Timer output level register m (TOLm)
Bit p
TOLm
TOLmp
1/0
0: Positive logic output (active-high)
1: Inverted output (active-low)
(e) Timer output mode register m (TOMm)
Bit p
TOMm
TOMmp
1: Sets the slave channel output mode.
1
Remark
m: Unit number (m = 0, 1), n: Channel number (n = 0, 2, 4, 6)
78K0R/KC3-L, 78K0R/KD3-L, 78K0R/KE3-L: mn = 00, 02, 04, 06
78K0R/KF3-L, 78K0R/KG3-L:
mn = 00, 02, 04, 06, 10, 12
p: Slave channel numberNote
When m = 0: n < p ≤ 7
When m = 1: n < p ≤ 3
Note
Since there is no function of timer I/O, the channel 1 in the 78K0R/KC3-L (40-pin) can not be used
as the slave channel.
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Figure 8-70. Operation Procedure When PWM Function Is Used (1/2)
Software Operation
Hardware Status
Power-off status
TAU
(Clock supply is stopped and writing to each register is
default
disabled.)
setting
Sets the TAU0EN and TAU1EN bits of peripheral enable
Note
registers 0, 2 (PER0, PER2) to 1.
Power-on status. Each channel stops operating.
(Clock supply is started and writing to each register is
enabled.)
Sets timer clock select register m (TPSm).
Determines clock frequencies of CKm0 and CKm1.
Channel
Sets timer mode registers mn, mp (TMRmn, TMRmp) of
Channel stops operating.
default
two channels to be used (determines operation mode of
(Clock is supplied and some power is consumed.)
setting
channels).
An interval (period) value is set to timer data register mn
(TDRmn) of the master channel, and a duty factor is set
to the TDRmp register of the slave channel.
Sets slave channel.
The TOmp pin goes into Hi-Z output state.
The TOMmp bit of timer output mode register m
(TOMm) is set to 1 (slave channel output mode).
Sets the TOLmp bit.
Sets the TOmp bit and determines default level of the
TOmp output.
The TOmp default setting level is output when the port
mode register is in output mode and the port register is 0.
Sets the TOEmp bit to 1 and enables operation of TOmp.
TOmp does not change because channel stops operating.
Clears the port register and port mode register to 0.
The TOmp pin outputs the TOmp set level.
(Note and Remark are listed on the next page.)
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Figure 8-70. Operation Procedure When PWM Function Is Used (2/2)
Software Operation
Operation
Sets the TOEmp bit (slave) to 1 (only when operation is
start
resumed).
Hardware Status
The TSmn (master) and TSmp (slave) bits of timer
channel start register m (TSm) are set to 1 at the same
When the master channel starts counting, INTTMmn is
time.
During
Operation is resumed.
operation
TEmn = 1, TEmp = 1
The TSmn and TSmp bits automatically return to 0
generated. Triggered by this interrupt, the slave
because they are trigger bits.
channel also starts counting.
Set values of the TMRmn and TMRmp registers,
TOMmn, TOMmp, TOLmn, and TOLmp bits cannot be
changed.
Set values of the TDRmn and TDRmp registers can be
changed after INTTMmn of the master channel is
generated.
The TCRmn and TCRmp registers can always be read.
The TSRmn and TSRmp registers are not used.
Set values of the TOm and TOEm registers can be
changed.
Operation
The TTmn (master) and TTmp (slave) bits are set to 1 at
stop
the same time.
The counter of the master channel loads the TDRmn
register value to timer/counter register mn (TCRmn), and
counts down. When the count value reaches TCRmn =
0000H, INTTMmn output is generated. At the same time,
the value of the TDRmn register is loaded to the TCRmn
register, and the counter starts counting down again.
At the slave channel, the value of the TDRmp register is
loaded to the TCRmp register, triggered by INTTMmn of
the master channel, and the counter starts counting down.
The output level of TOmp becomes active one count clock
after generation of the INTTMmn output from the master
channel. It becomes inactive when TCRmp = 0000H, and
the counting operation is stopped.
After that, the above operation is repeated.
TEmn, TEmp = 0, and count operation stops.
The TTmn and TTmp bits automatically return to 0
The TCRmn and TCRmp registers hold count value and
because they are trigger bits.
stop.
The TOmp output is not initialized but holds current
status.
The TOEmp bit of slave channel is cleared to 0 and value
is set to the TOmp bit.
TAU
stop
The TOmp pin outputs the TOmp set level.
To hold the TOmp pin output level
Clears the TOmp bit to 0 after the value to
The TOmp pin output level is held by port function.
be held is set to the port register.
When holding the TOmp pin output level is not
necessary
Switches the port mode register to input mode.
The TAU0EN and TAU1EN bits of the PER0 and PER2
Note
registers are cleared to 0.
The TOmp pin output level goes into Hi-Z output state.
Power-off status
All circuits are initialized and SFR of each channel is
also initialized.
(The TOmp bit is cleared to 0 and the TOmp pin is set
to port mode.)
Note 78K0R/KC3-L, 78K0R/KD3-L, 78K0R/KE3-L: TAU0EN bit of the PER2 register
78K0R/KF3-L, 78K0R/KG3-L:
TAU0EN or TAU1EN bit of the PER0 register
Remark m: Unit number (m = 0, 1), n: Channel number (n = 0, 2, 4, 6)
78K0R/KC3-L, 78K0R/KD3-L, 78K0R/KE3-L: mn = 00, 02, 04, 06
78K0R/KF3-L, 78K0R/KG3-L:
mn = 00, 02, 04, 06, 10, 12
p: Slave channel numberNote
When m = 0: n < p ≤ 7
When m = 1: n < p ≤ 3
Note
Since there is no function of timer I/O, the channel 1 in the 78K0R/KC3-L (40-pin) can not be used as
the slave channel.
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8.8.3 Operation as multiple PWM output function
By extending the PWM function and using multiple slave channels, many PWM waveforms with different duty values
can be output.
For example, when using two slave channels, the period and duty factor of an output pulse can be calculated by the
following expressions.
Pulse period = {Set value of TDRmn (master) + 1} × Count clock period
Duty factor 1 [%] = {Set value of TDRmp (slave 1)}/{Set value of TDRmn (master) + 1} × 100
Duty factor 2 [%] = {Set value of TDRmq (slave 2)}/{Set value of TDRmn (master) + 1} × 100
Remark
Although the duty factor exceeds 100% if the set value of TDRmp (slave 1) > {set value of TDRmn
(master) + 1} or if the {set value of TDRmq (slave 2)} > {set value of TDRmn (master) + 1}, it is
summarized into 100% output.
Timer/counter register mn (TCRmn) of the master channel operates in the interval timer mode and counts the periods.
The TCRmp register of the slave channel 1 operates in one-count mode, counts the duty factor, and outputs a PWM
waveform from the TOmp pin. The TCRmp register loads the value of timer data register mp (TDRmp), using INTTMmn of
the master channel as a start trigger, and starts counting down. When TCRmp = 0000H, TCRmp outputs INTTMmp and
stops counting until the next start trigger (INTTMmn of the master channel) has been input. The output level of TOmp
becomes active one count clock after generation of INTTMmn from the master channel, and inactive when TCRmp =
0000H.
In the same way as the TCRmp register of the slave channel 1, the TCRmq register of the slave channel 2 operates in
one-count mode, counts the duty factor, and outputs a PWM waveform from the TOmq pin. The TCRmq register loads the
value of the TDRmq register, using INTTMmn of the master channel as a start trigger, and starts counting down. When
TCRmq = 0000H, the TCRmq register outputs INTTMmq and stops counting until the next start trigger (INTTMmn of the
master channel) has been input. The output level of TOmq becomes active one count clock after generation of INTTMmn
from the master channel, and inactive when TCRmq = 0000H.
When channel 0 is used as the master channel as above, up to seven types of PWM signals can be output at the same
time.
Caution To rewrite both timer data register mn (TDRmn) of the master channel and the TDRmp register of the
slave channel 1, write access is necessary at least twice. Since the values of the TDRmn and TDRmp
registers are loaded to the TCRmn and TCRmp registers after INTTMmn is generated from the master
channel, if rewriting is performed separately before and after generation of INTTMmn from the master
channel, the TOmp pin cannot output the expected waveform. To rewrite both the TDRmn register of
the master and the TDRmp register of the slave, be sure to rewrite both the registers immediately
after INTTMmn is generated from the master channel (This applies also to the TDRmq register of the
slave channel 2).
Remark
m: Unit number (m = 0, 1), n: Channel number (n = 0, 2, 4)
78K0R/KC3-L, 78K0R/KD3-L, 78K0R/KE3-L: mn = 00, 02, 04
78K0R/KF3-L, 78K0R/KG3-L:
mn = 00, 02, 04, 10
p: Slave channel number 1, q: Slave channel number 2Note
When m = 0: n < p < q ≤ 7
When m = 1: n < p < q ≤ 3
(Where p and q are consecutive integers greater than n)
Note
Since there is no function of timer I/O, the channel 1 in the 78K0R/KC3-L (40-pin) can not be used as
the slave channel.
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CHAPTER 8 TIMER ARRAY UNIT
CKm1
Operation clock
CKm0
TSmn
Trigger selection
Master channel
(interval timer mode)
Clock selection
Figure 8-71. Block Diagram of Operation as Multiple PWM Output Function (output two types of PWMs)
Timer counter
register mn (TCRmn)
Timer data
register mn (TDRmn)
Interrupt
controller
Timer counter
register mp (TCRmp)
Output
controller
Timer data
register mp (TDRmp)
Interrupt
controller
Timer counter
register mq (TCRmq)
Output
controller
Timer data
register mq (TDRmq)
Interrupt
controller
Interrupt signal
(INTTMmn)
Operation clock
CKm1
Trigger selection
CKm0
Clock selection
Slave channel 1
(one-count mode)
TOmp pin
Interrupt signal
(INTTMmp)
CKm1
Operation clock
Trigger selection
CKm0
Clock selection
Slave channel 2
(one-count mode)
Remark
TOmq pin
Interrupt signal
(INTTMmq)
m: Unit number (m = 0, 1), n: Channel number (n = 0, 2, 4)
78K0R/KC3-L, 78K0R/KD3-L, 78K0R/KE3-L: mn = 00, 02, 04
78K0R/KF3-L, 78K0R/KG3-L:
mn = 00, 02, 04, 10
p: Slave channel number 1, q: Slave channel number 2Note
When m = 0: n < p < q ≤ 7
When m = 1: n < p < q ≤ 3
(Where p and q are consecutive integers greater than n)
Note
Since there is no function of timer I/O, the channel 1 in the 78K0R/KC3-L (40-pin) can not be used
as the slave channel.
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Figure 8-72. Example of Basic Timing of Operation as Multiple PWM Output Function
(output two types of PWMs) (1/2)
TSmn
TEmn
FFFFH
Master
channel
TCRmn
0000H
TDRmn
a
b
TOmn
INTTMmn
TSmp
TEmp
FFFFH
Slave
channel 1
TCRmp
0000H
TDRmp
c
d
TOmp
INTTMmp
a+1
a+1
c
c
b+1
d
d
TSmq
TEmq
FFFFH
Slave
channel 2
TCRmq
0000H
TDRmq
e
f
TOmq
INTTMmq
a+1
e
a+1
e
b+1
f
f
(Remark are listed on the next page.)
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Figure 8-72. Example of Basic Timing of Operation as Multiple PWM Output Function
(output two types of PWMs) (2/2)
Remarks 1. m: Unit number (m = 0, 1), n: Channel number (n = 0, 2, 4)
78K0R/KC3-L, 78K0R/KD3-L, 78K0R/KE3-L: mn = 00, 02, 04
78K0R/KF3-L, 78K0R/KG3-L:
mn = 00, 02, 04, 10
p: Slave channel number 1, q: Slave channel number 2Note
When m = 0: n < p < q ≤ 7
When m = 1: n < p < q ≤ 3
(Where p and q are consecutive integers greater than n)
Note
Since there is no function of timer I/O, channel 1 in the 78K0R/KC3-L (40-pin) can not used as
slave channel.
2. TSmn, TSmp, TSmq:
TEmn, TEmp, TEmq:
Bit n, p, q of timer channel start register m (TSm)
Bit n, p, q of timer channel enable status register m (TEm)
TCRmn, TCRmp, TCRmq: Timer/counter registers mn, mp, mq (TCRmn, TCRmp, TCRmq)
TDRmn, TDRmp, TDRmq: Timer data registers mn, mp, mq (TDRmn, TDRmp, TDRmq)
TOmn, TOmp, TOmq:
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CHAPTER 8 TIMER ARRAY UNIT
Figure 8-73. Example of Set Contents of Registers
When Multiple PWM Output Function (Master Channel) Is Used
(a) Timer mode register mn (TMRmn)
15
TMRmn
14
13
11
10
9
8
7
6
5
4
0
0
MAS
CCSmn
STSmn2 STSmn1 STSmn0 CISmn1 CISmn0
TERmn
CKSmn
1/0
12
0
0
0
1
0
0
0
0
3
2
1
0
MDmn3 MDmn2 MDmn1 MDmn0
0
0
0
0
1
Operation mode of channel n
000B: Interval timer
Setting of operation when counting is started
1: Generates INTTMmn when counting is
started.
Selection of TImn pin input edge
00B: Sets 00B because these are not used.
Start trigger selection
000B: Selects only software start.
Slave/master selection
1: Master channel.
Count clock selection
0: Selects operation clock.
Operation clock selection
0: Selects CKm0 as operation clock of channel n.
1: Selects CKm1 as operation clock of channel n.
(b) Timer output register m (TOm)
Bit n
TOm
TOmn
0: Outputs 0 from TOmn.
0
(c) Timer output enable register m (TOEm)
Bit n
TOEm
TOEmn
0: Stops the TOmn output operation by counting operation.
0
(d) Timer output level register m (TOLm)
Bit n
TOLm
TOLmn
0: Cleared to 0 when TOMmn = 0 (master channel output mode).
0
(e) Timer output mode register m (TOMm)
Bit n
TOMm
TOMmn
0: Sets master channel output mode.
0
Remark
m: Unit number (m = 0, 1), n: Channel number (n = 0, 2, 4)
78K0R/KC3-L, 78K0R/KD3-L, 78K0R/KE3-L: mn = 00, 02, 04
78K0R/KF3-L, 78K0R/KG3-L:
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CHAPTER 8 TIMER ARRAY UNIT
Figure 8-74. Example of Set Contents of Registers
When Multiple PWM Output Function (Slave Channel) Is Used (output two types of PWMs) (1/2)
(a) Timer mode register mp, mq (TMRmp, TMRmq)
15
TMRmp
TMRmq
14
13
12
11
10
9
8
7
6
5
4
MAS
CCSmp
STSmp2 STSmp1 STSmp0 CISmp1 CISmp0
TERmp
CKSmp
3
2
1
0
MDmp3 MDmp2 MDmp1 MDmp0
1/0
0
0
0
0
1
0
0
0
0
0
0
1
0
0
1
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
0
0
MAS
CCSmq
STSmq2 STSmq1 STSmq0 CISmq1 CISmq0
TERmq
CKSmq
1/0
0
0
0
0
1
0
0
0
0
MDmq3 MDmq2 MDmq1 MDmq0
1
0
0
1
Operation mode of channel p, q
100B: One-count mode
Start trigger during operation
1: Trigger input is valid.
Selection of TImp and TImq pins input edge
00B: Sets 00B because these are not used.
Start trigger selection
100B: Selects INTTMmn of master channel.
Slave/master selection
0: Slave channel.
Count clock selection
0: Selects operation clock.
Operation clock selection
0: Selects CKm0 as operation clock of channel p, q.
1: Selects CKm1 as operation clock of channel p, q.
* Make the same setting as master channel.
(b) Timer output register m (TOm)
TOm
Bit q
Bit p
TOmq
TOmp
1/0
1/0
0: Outputs 0 from TOmp or TOmq.
1: Outputs 1 from TOmp or TOmq.
(c) Timer output enable register m (TOEm)
Bit q
TOEm
Bit p
TOEmq TOEmp
1/0
1/0
0: Stops the TOmp or TOmq output operation by counting operation.
1: Enables the TOmp or TOmq output operation by counting operation.
(d) Timer output level register m (TOLm)
Bit q
TOLm
Bit p
TOLmq TOLmp
1/0
1/0
0: Positive logic output (active-high)
1: Inverted output (active-low)
(e) Timer output mode register m (TOMm)
Bit q
TOMm
Bit p
TOMmq TOMmp
1
1: Sets the slave channel output mode.
1
(Remark is listed on the next page.)
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CHAPTER 8 TIMER ARRAY UNIT
Figure 8-74. Example of Set Contents of Registers
When Multiple PWM Output Function (Slave Channel) Is Used (output two types of PWMs) (2/2)
Remark
m: Unit number (m = 0, 1), n: Channel number (n = 0, 2, 4)
78K0R/KC3-L, 78K0R/KD3-L, 78K0R/KE3-L: mn = 00, 02, 04
78K0R/KF3-L, 78K0R/KG3-L:
mn = 00, 02, 04, 10
p: Slave channel number 1, q: Slave channel number 2Note
When m = 0: n < p < q ≤ 7, When m = 1: n < p < q ≤ 3
(Where p and q are consecutive integers greater than n)
Note
Since there is no function of timer I/O, the channel 1 in the 78K0R/KC3-L (40-pin) can not be used as
the slave channel.
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CHAPTER 8 TIMER ARRAY UNIT
Figure 8-75. Operation Procedure When Multiple PWM Output Function Is Used (1/3)
Software Operation
Hardware Status
Power-off status
TAU
default
(Clock supply is stopped and writing to each register is
setting
disabled.)
Sets the TAU0EN and TAU1EN bits of peripheral enable
Note
registers 0, 2 (PER0, PER2) to 1.
Power-on status. Each channel stops operating.
(Clock supply is started and writing to each register is
enabled.)
Sets timer clock select register m (TPSm).
Determines clock frequencies of CKm0 and CKm1.
Channel
Sets timer mode registers mn, mp, mq (TMRmn,
Channel stops operating.
default
TMRmp, TMRmq) of each channel to be used
(Clock is supplied and some power is consumed.)
setting
(determines operation mode of channels).
An interval (period) value is set to timer data register mn
(TDRmn) of the master channel, and a duty factor is set
to the TDRmp and TDRmq registers of the slave
channels.
Sets slave channels.
The TOmp and TOmq pins go into Hi-Z output state.
The TOMmp and TOMmq bits of timer output mode
register m (TOMm) are set to 1 (slave channel output
mode).
Clears the TOLmp and TOLmq bits to 0.
Sets the TOmp and TOmq bits and determines default
level of the TOmp and TOmq outputs.
The TOmp and TOmq default setting levels are output
when the port mode register is in output mode and the port
register is 0.
Sets the TOEmp and TOEmq bits to 1 and enables
operation of TOmp and TOmq.
TOmp and TOmq do not change because channels stop
operating.
Clears the port register and port mode register to 0.
The TOmp and TOmq pins output the TOmp and TOmq
set levels.
(Note and Remark are listed on the next page.)
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CHAPTER 8 TIMER ARRAY UNIT
Figure 8-75. Operation Procedure When Multiple PWM Output Function Is Used (2/3)
Software Operation
Hardware Status
Operation (Sets the TOEmp and TOEmq (slave) bits to 1 only when
resuming operation.)
start
The TSmn bit (master), and TSmp and TSmq (slave) bits
of timer channel start register m (TSm) are set to 1 at the
same time.
The TSmn, TSmp, and TSmq bits automatically return
to 0 because they are trigger bits.
Set values of the TMRmn, TMRmp, TMRmq registers,
TOMmn, TOMmp, TOMmq, TOLmn, TOLmp, and TOLmq
bits cannot be changed.
Set values of the TDRmn, TDRmp, and TDRmq registers
can be changed after INTTMmn of the master channel is
generated.
The TCRmn, TCRmp, and TCRmq registers can always
be read.
The TSRmn, TSRmp, and TSRmq registers are not used.
Set values of the TOm and TOEm registers can be
changed.
Operation
stop
The TTmn bit (master), TTmp, and TTmq (slave) bits are
set to 1 at the same time.
The TTmn, TTmp, and TTmq bits automatically return
to 0 because they are trigger bits.
Operation is resumed.
During
operation
The TOEmp and TOEmq bits of slave channels are
cleared to 0 and value is set to the TOmp and TOmq bits.
TAU
stop
To hold the TOmp and TOmq pin output levels
Clears the TOmp and TOmq bits to 0 after
the value to be held is set to the port register.
When holding the TOmp and TOmq pin output levels are
not necessary
Switches the port mode register to input mode.
The TAU0EN and TAU1EN bits of the PER0 and PER2
Note
registers are cleared to 0.
Note 78K0R/KC3-L, 78K0R/KD3-L, 78K0R/KE3-L:
78K0R/KF3-L, 78K0R/KG3-L:
TEmn = 1, TEmp, TEmq = 1
When the master channel starts counting, INTTMmn is
generated. Triggered by this interrupt, the slave
channel also starts counting.
The counter of the master channel loads the TDRmn
register value to timer/counter register mn (TCRmn) and
counts down. When the count value reaches TCRmn =
0000H, INTTMmn output is generated. At the same time,
the value of the TDRmn register is loaded to the TCRmn
register, and the counter starts counting down again.
At the slave channel 1, the values of the TDRmp register
are transferred to the TCRmp register, triggered by
INTTMmn of the master channel, and the counter starts
counting down. The output levels of TOmp become active
one count clock after generation of the INTTMmn output
from the master channel. It becomes inactive when
TCRmp = 0000H, and the counting operation is stopped.
At the slave channel 2, the values of the TDRmq register
are transferred to TCRmq regster, triggered by INTTMmn
of the master channel, and the counter starts counting
down. The output levels of TOmq become active one count
clock after generation of the INTTMmn output from the
master channel. It becomes inactive when TCRmq =
0000H, and the counting operation is stopped.
After that, the above operation is repeated.
TEmn, TEmp, TEmq = 0, and count operation stops.
The TCRmn, TCRmp, and TCRmq registers hold count
value and stop.
The TOmp and TOmq output are not initialized but hold
current status.
The TOmp and TOmq pins output the TOmp and TOmq
set levels.
The TOmp and TOmq pin output levels are held by port
function.
The TOmp and TOmq pin output levels go into Hi-Z output
state.
Power-off status
All circuits are initialized and SFR of each channel is
also initialized.
(The TOmp and TOmq bits are cleared to 0 and the
TOmp and TOmq pins are set to port mode.)
TAU0EN bit of the PER2 register
TAU0EN or TAU1EN bit of the PER0 register
(Remark is listed on the next page.)
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Figure 8-75. Operation Procedure When Multiple PWM Output Function Is Used (3/3)
Remark
m: Unit number (m = 0, 1), n: Channel number (n = 0, 2, 4)
78K0R/KC3-L, 78K0R/KD3-L, 78K0R/KE3-L: mn = 00, 02, 04
78K0R/KF3-L, 78K0R/KG3-L:
mn = 00, 02, 04, 10
p: Slave channel number 1, q: Slave channel number 2Note
When m = 0: n < p < q ≤ 7, When m = 1: n < p < q ≤ 3
(Where p and q are a consecutive integer greater than n)
Note
Since there is no function of timer I/O, the channel 1 in the 78K0R/KC3-L (40-pin) can not be used
as the slave channel.
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CHAPTER 9 REAL-TIME COUNTER
CHAPTER 9 REAL-TIME COUNTER
Remark
The 78K0R/KC3-L (40-pin) doesn’t have the real-time counter.
9.1 Functions of Real-Time Counter
The real-time counter has the following features.
• Having counters of year, month, week, day, hour, minute, and second, and can count up to 99 years.
• Constant-period interrupt function (period: 1 month to 0.5 seconds)
• Alarm interrupt function (alarm: week, hour, minute)
• Interval interrupt function
• Pin output function of 1 Hz
• Pin output function of 512 Hz or 16.384 kHz or 32.768 kHz
9.2 Configuration of Real-Time Counter
The real-time counter includes the following hardware.
Table 9-1. Configuration of Real-Time Counter
Item
Control registers
Configuration
Peripheral enable register 0 (PER0)
Real-time counter control register 0 (RTCC0)
Real-time counter control register 1 (RTCC1)
Real-time counter control register 2 (RTCC2)
Sub-count register (RSUBC)
Second count register (SEC)
Minute count register (MIN)
Hour count register (HOUR)
Day count register (DAY)
Week count register (WEEK)
Month count register (MONTH)
Year count register (YEAR)
Watch error correction register (SUBCUD)
Alarm minute register (ALARMWM)
Alarm hour register (ALARMWH)
Alarm week register (ALARMWW)
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CHAPTER 9 REAL-TIME COUNTER
Figure 9-1. Block Diagram of Real-Time Counter
Real-time counter control register 1
WALE
WALIE WAFG
RIFG
Real-time counter control register 0
RWST RWAIT
RTCE RCLOE1 RCLOE0 AMPM
CT2
CT1
CT0
fSUB
Alarm week
register
(ALARMWW)
(7-bit)
Alarm hour
register
(ALARMWH)
(6-bit)
[KC3-L,KD3-L,KE3-L]
RTC1HZ/SLTI/SLTO/P52
[KF3-L,KG3-L]
RTC1HZ/INTP3/P30
Alarm minute
register
(ALARMWM)
(7-bit)
INTRTC
CT0 to CT2
Selector
RIFG
AMPM
RWST
1 day
1 month
Year count
register
(YEAR)
(8-bit)
Month count
register
(MONTH)
(5-bit)
Week count
register
(WEEK)
(3-bit)
Day count
register
(DAY)
(6-bit)
1 hour
Hour count
register
(HOUR)
(6-bit)
RWAIT
1 minute
Minute count
register
(MIN)
(7-bit)
Second
count
register
(SEC)
(7-bit)
0.5
seconds
Count clock
Sub-count = 32.768 kHz
register
(RSUBC)
fSUB
(16-bit)
Wait control
Count enable/
disable circuit
Buffer
Buffer
Buffer
Buffer
Buffer
Buffer
Buffer
RTCE
Watch error
correction
register
(SUBCUD)
(8-bit)
Internal bus
Real-time counter control register 2
RINTE RCLOE2 RCKDIV
ICT1
12-bit counter
ICT0
RINTE
Selector
fSUB
ICT2
INTRTCI
RCKDIV
Selector
RCLOE2
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[KF3-L,KG3-L]
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CHAPTER 9 REAL-TIME COUNTER
9.3 Registers Controlling Real-Time Counter
The real-time counter is controlled by the following 16 registers.
• Peripheral enable register 0 (PER0)
• Real-time counter control register 0 (RTCC0)
• Real-time counter control register 1 (RTCC1)
• Real-time counter control register 2 (RTCC2)
• Sub-count register (RSUBC)
• Second count register (SEC)
• Minute count register (MIN)
• Hour count register (HOUR)
• Day count register (DAY)
• Week count register (WEEK)
• Month count register (MONTH)
• Year count register (YEAR)
• Watch error correction register (SUBCUD)
• Alarm minute register (ALARMWM)
• Alarm hour register (ALARMWH)
• Alarm week register (ALARMWW)
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CHAPTER 9 REAL-TIME COUNTER
(1) Peripheral enable register 0 (PER0)
This register is used to enable or disable supplying the clock to the peripheral hardware. Clock supply to a
hardware macro that is not used is stopped in order to reduce the power consumption and noise.
When the real-time counter is used, be sure to set bit 7 (RTCEN) of this register to 1.
The PER0 register can be set by a 1-bit or 8-bit memory manipulation instruction.
Reset signal generation clears this register to 00H.
Figure 9-2. Format of Peripheral Enable Register 0 (PER0)
Address: F00F0H
Symbol
PER0
After reset: 00H
<7>
RTCEN
Note 1
RTCEN
Note 1
0
R/W
6
0
<5>
ADCEN
<4>
IICAEN
<3>
Note 2
SAU1EN
<2>
Note 3
SAU0EN
<1>
TAU1EN
Control of real-time counter (RTC) input clock supply
<0>
Note 3
TAU0EN
Note 3
Note 4
Stops input clock supply.
• SFR used by the real-time counter (RTC) cannot be written.
• The real-time counter (RTC) is in the reset status.
1
Enables input clock supply.
• SFR used by the real-time counter (RTC) can be read/written.
Notes 1. That is not provided in 40-pin product of the 78K0R/KC3-L.
2. That is not provided in 40-pin and 44-pin products of the 78K0R/KC3-L.
3. 78K0R/KF3-L and 78K0R/KG3-L only.
4. The RTCEN bit is used to supply or stop the clock used when accessing the real-time counter
(RTC) register from the CPU. The RTCEN bit cannot control supply of the operating clock
(fSUB) to RTC.
Cautions 1. When using the real-time counter, first set the RTCEN bit to 1, while oscillation of the
subsystem clock (fSUB) is stable. If RTCEN = 0, writing to a control register of the
real-time counter is ignored, and, even if the register is read, only the default value is
read.
2. Clock supply to peripheral functions other than the real-time counter can be stopped
in HALT mode when the subsystem clock is used, by setting the RTCLPC bit of the
operation speed mode control register (OSMC) to 1. In this case, set the RTCEN bit
of the PER0 register to 1 and the other bits (bits 0 to 6) to 0. If using the 78K0R/KC3L, 78K0R/KD3-L, or 78K0R/KE3-L, set bits 0 to 7 of the PER1 and PER2 registers to 0
also.
3. Be sure to clear the following bits to 0.
48-pin product of the 78K0R/KC3-L, 78K0R/KD3-L, 78K0R/KE3-L: bits 0, 1, 3, 6
44-pin product of the 78K0R/KC3-L: bits 0, 1, 3, 4, 6
40-pin product of the 78K0R/KC3-L: bits 0, 1, 3, 4, 6, 7
78K0R/KF3-L, 78K0R/KG3-L:
bit 6
(2) Real-time counter control register 0 (RTCC0)
The RTCC0 register is an 8-bit register that is used to start or stop the real-time counter operation, control the
RTCCL and RTC1HZ pins, and set a 12- or 24-hour system and the constant-period interrupt function.
The RTCC0 register can be set by a 1-bit or 8-bit memory manipulation instruction.
Reset signal generation clears this register to 00H.
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Figure 9-3. Format of Real-Time Counter Control Register 0 (RTCC0)
Address: FFF9DH
After reset: 00H
R/W
Symbol
<7>
6
<5>
<4>
3
2
1
0
RTCC0
RTCE
0
RCLOE1
RCLOE0
AMPM
CT2
CT1
CT0
RTCE
Real-time counter operation control
0
Stops counter operation.
1
Starts counter operation.
RCLOE1
RTC1HZ pin output control
0
Disables output of the RTC1HZ pin (1 Hz).
1
Enables output of the RTC1HZ pin (1 Hz).
RCLOE0
Note
RTCCL pin output control
0
Disables output of the RTCCL pin (32.768 kHz).
1
Enables output of the RTCCL pin (32.768 kHz).
AMPM
Selection of 12-/24-hour system
0
12-hour system (a.m. and p.m. are displayed.)
1
24-hour system
• Rewrite the AMPM bit value after setting the RWAIT bit (bit 0 of real-time counter control register 1 (RTCC1)) to 1.
If the AMPM bit value is changed, the values of the hour count register (HOUR) change according to the specified
time system.
• Table 9-2 shows the displayed time digits that are displayed.
CT2
CT1
CT0
Constant-period interrupt (INTRTC) selection
0
0
0
Does not use constant-period interrupt function.
0
0
1
Once per 0.5 s (synchronized with second count up)
0
1
0
Once per 1 s (same time as second count up)
0
1
1
Once per 1 m (second 00 of every minute)
1
0
0
Once per 1 hour (minute 00 and second 00 of every hour)
1
0
1
Once per 1 day (hour 00, minute 00, and second 00 of every day)
1
1
×
Once per 1 month (Day 1, hour 00 a.m., minute 00, and second 00 of
every month)
When changing the values of the CT2 to CT0 bits while the counter operates (RTCE = 1), rewrite the values of the
CT2 to CT0 bits after disabling interrupt servicing INTRTC by using the interrupt mask flag register. Furthermore,
after rewriting the values of the CT2 to CT0 bits, enable interrupt servicing after clearing the RIFG and RTCIF flags.
Note The RCLOE0 and RCLOE2 bits must not be enabled at the same time.
Caution If the RCLOE0 and RCLOE1 bits are changed when RTCE = 1, the last waveform of the 32.768 kHz
and 1 Hz output signals may become short.
Remark ×: don’t care
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(3) Real-time counter control register 1 (RTCC1)
The RTCC1 register is an 8-bit register that is used to control the alarm interrupt function and the wait time of the
counter.
The RTCC1 register can be set by a 1-bit or 8-bit memory manipulation instruction.
Reset signal generation clears this register to 00H.
Figure 9-4. Format of Real-Time Counter Control Register 1 (RTCC1) (1/2)
Address: FFF9EH
After reset: 00H
R/W
Symbol
<7>
<6>
5
<4>
<3>
2
<1>
<0>
RTCC1
WALE
WALIE
0
WAFG
RIFG
0
RWST
RWAIT
WALE
Alarm operation control
0
Match operation is invalid.
1
Match operation is valid.
When setting a value to the WALE bit while the counter operates (RTCE = 1) and WALIE = 1, rewrite the WALE bit
after disabling interrupt servicing INTRTC by using the interrupt mask flag register. Furthermore, clear the WAFG
and RTCIF flags after rewriting the WALE bit. When setting each alarm register (WALIE flag of real-time counter
control register 1 (RTCC1), the alarm minute register (ALARMWM), the alarm hour register (ALARMWH), and the
alarm week register (ALARMWW)), set match operation to be invalid (“0”) for the WALE bit.
WALIE
Control of alarm interrupt (INTRTC) function operation
0
Does not generate interrupt on matching of alarm.
1
Generates interrupt on matching of alarm.
WAFG
Alarm detection status flag
0
Alarm mismatch
1
Detection of matching of alarm
This is a status flag that indicates detection of matching with the alarm. It is valid only when WALE = 1 and is set to
“1” one clock (32.768 kHz) after matching of the alarm is detected. This flag is cleared when “0” is written to it.
Writing “1” to it is invalid.
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Figure 9-4. Format of Real-Time Counter Control Register 1 (RTCC1) (2/2)
RIFG
Constant-period interrupt status flag
0
Constant-period interrupt is not generated.
1
Constant-period interrupt is generated.
This flag indicates the status of generation of the constant-period interrupt. When the constant-period interrupt is
generated, it is set to “1”.
This flag is cleared when “0” is written to it. Writing “1” to it is invalid.
RWST
Wait status flag of real-time counter
0
Counter is operating.
1
Mode to read or write counter value
This status flag indicates whether the setting of the RWAIT bit is valid.
Before reading or writing the counter value, confirm that the value of this flag is 1.
RWAIT
Wait control of real-time counter
0
Sets counter operation.
1
Stops SEC to YEAR counters. Mode to read or write counter value
This bit controls the operation of the counter.
Be sure to write “1” to it to read or write the counter value.
Because the sub-count register (RSUBC) continues operation, complete reading or writing of it in 1 second, and
clear this bit back to 0.
When RWAIT = 1, it takes up to 1 clock (32.768 kHz) until the counter value can be read or written.
If the RSUBC register overflows when RWAIT = 1, the counter counts up after RWAIT = 0. If the second count
register is written, however, the RSUBC register is cleared.
Caution If writing is performed to the RTCC1 register with a 1-bit manipulation instruction, the RIFG flag
and WAFG flag may be cleared. Therefore, to perform writing to the RTCC1 register, be sure to
use an 8-bit manipulation instruction.
To prevent the RIFG flag and WAFG flag from being
cleared during writing, disable writing by setting 1 to the corresponding bit. If the RIFG flag and
WAFG flag are not used and the value may be changed, the RTCC1 register may be written by
using a 1-bit manipulation instruction.
Remark Fixed-cycle interrupts and alarm match interrupts use the same interrupt source (INTRTC). When using
these two types of interrupts at the same time, which interrupt occurred can be judged by checking the
fixed-cycle interrupt status flag (RIFG) and the alarm detection status flag (WAFG) upon INTRTC
occurrence.
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(4) Real-time counter control register 2 (RTCC2)
The RTCC2 register is an 8-bit register that is used to control the interval interrupt function and the RTCDIV pin.
The RTCC2 register can be set by a 1-bit or 8-bit memory manipulation instruction.
Reset signal generation clears this register to 00H.
Figure 9-5. Format of Real-Time Counter Control Register 2 (RTCC2)
Address: FFF9FH
After reset: 00H
R/W
Symbol
<7>
<6>
<5>
4
3
2
1
0
RTCC2
RINTE
RCLOE2
RCKDIV
0
0
ICT2
ICT1
ICT0
RINTE
ICT2
ICT1
ICT0
0
×
×
×
Interval interrupt is not generated.
1
0
0
0
2 /fXT (1.953125 ms)
1
0
0
1
2 /fXT (3.90625 ms)
1
0
1
0
2 /fXT (7.8125 ms)
1
0
1
1
2 /fXT (15.625 ms)
1
1
0
0
2 /fXT (31.25 ms)
1
1
0
1
2 /fXT (62.5 ms)
1
1
1
×
2 /fXT (125 ms)
RCLOE2
Note
Interval interrupt (INTRTCI) selection
6
7
8
9
10
11
12
RTCDIV pin output control
0
Output of the RTCDIV pin is disabled.
1
Output of the RTCDIV pin is enabled.
RCKDIV
Selection of RTCDIV pin output frequency
0
The RTCDIV pin outputs 512 Hz. (1.95 ms)
1
The RTCDIV pin outputs 16.384 kHz. (0.061 ms)
Notes The RCLOE0 and RCLOE2 bits must not be enabled at the same time.
Cautions 1. Change the ICT2, ICT1, and ICT0 bits when RINTE = 0.
2. When the output from the RTCDIV pin is stopped, the output continues after a maximum of
two clocks of fXT and enters the low level. While 512 Hz is output, and when the output is
stopped immediately after entering the high level, a pulse of at least one clock width of fXT may
be generated.
3. After the real-time counter starts operating, the output width of the RTCDIV pin may be shorter
than as set during the first interval period.
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(5) Sub-count register (RSUBC)
The RSUBC register is a 16-bit register that counts the reference time of 1 second of the real-time counter.
Normally, it takes a value of 0000H to 7FFFH and counts 1 second with a clock of 32.768 kHz.
The RSUBC register can be set by a 16-bit memory manipulation instruction.
Reset signal generation clears this register to 0000H.
Cautions 1. When a correction is made by using the watch error correction register (SUBCUD), the value
may become 8000H or more.
2. This register is also cleared by reset effected by writing the second count register.
3. The value read from this register is not guaranteed if it is read during operation, because a
value that is changing is read.
Figure 9-6. Format of Sub-Count Register (RSUBC)
Address: FFF90H
After reset: 0000H
R
Symbol
7
6
5
4
3
2
1
0
RSUBC
SUBC7
SUBC6
SUBC5
SUBC4
SUBC3
SUBC2
SUBC1
SUBC0
Address: FFF91H
After reset: 0000H
R
Symbol
7
6
5
4
3
2
1
0
RSUBC
SUBC15
SUBC14
SUBC13
SUBC12
SUBC11
SUBC10
SUBC9
SUBC8
(6) Second count register (SEC)
The SEC register is an 8-bit register that takes a value of 0 to 59 (decimal) and indicates the count value of
seconds.
It counts up when the sub-counter overflows.
When data is written to this register, it is written to a buffer and then to the counter up to 2 clocks (32.768 kHz) later.
Set a decimal value of 00 to 59 to this register in BCD code. If a value outside the range is set, the register value
returns to the normal value after 1 period.
The SEC register can be set by an 8-bit memory manipulation instruction.
Reset signal generation clears this register to 00H.
Figure 9-7. Format of Second Count Register (SEC)
Address: FFF92H
After reset: 00H
R/W
Symbol
7
6
5
4
3
2
1
0
SEC
0
SEC40
SEC20
SEC10
SEC8
SEC4
SEC2
SEC1
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(7) Minute count register (MIN)
The MIN register is an 8-bit register that takes a value of 0 to 59 (decimal) and indicates the count value of minutes.
It counts up when the second counter overflows.
When data is written to this register, it is written to a buffer and then to the counter up to 2 clocks (32.768 kHz) later.
Even if the second count register overflows while this register is being written, this register ignores the overflow and
is set to the value written. Set a decimal value of 00 to 59 to this register in BCD code. If a value outside the range
is set, the register value returns to the normal value after 1 period.
The MIN register can be set by an 8-bit memory manipulation instruction.
Reset signal generation clears this register to 00H.
Figure 9-8. Format of Minute Count Register (MIN)
Address: FFF93H
After reset: 00H
R/W
Symbol
7
6
5
4
3
2
1
0
MIN
0
MIN40
MIN20
MIN10
MIN8
MIN4
MIN2
MIN1
(8) Hour count register (HOUR)
The HOUR register is an 8-bit register that takes a value of 00 to 23 or 01 to 12 and 21 to 32 (decimal) and
indicates the count value of hours.
It counts up when the minute counter overflows.
When data is written to this register, it is written to a buffer and then to the counter up to 2 clocks (32.768 kHz) later.
Even if the minute count register overflows while this register is being written, this register ignores the overflow and
is set to the value written. Specify a decimal value of 00 to 23, 01 to 12, or 21 to 32 by using BCD code according
to the time system specified using bit 3 (AMPM) of real-time counter control register 0 (RTCC0).
If the AMPM bit value is changed, the values of the HOUR register change according to the specified time system.
If a value outside the range is set, the register value returns to the normal value after 1 period.
The HOUR register can be set by an 8-bit memory manipulation instruction.
Reset signal generation clears this register to 12H.
However, the value of this register is 00H if the AMPM bit (bit 3 of the RTCC0 register) is set to 1 after reset.
Figure 9-9. Format of Hour Count Register (HOUR)
Address: FFF94H
After reset: 12H
R/W
Symbol
7
6
5
4
3
2
1
0
HOUR
0
0
HOUR20
HOUR10
HOUR8
HOUR4
HOUR2
HOUR1
Caution Bit 5 (HOUR20) of the HOUR register indicates AM(0)/PM(1) if AMPM = 0 (if the 12-hour system is
selected).
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Table 9-2 shows the relationship between the setting value of the AMPM bit, the hour count register (HOUR) value, and
time.
Table 9-2. Displayed Time Digits
24-Hour Display (AMPM = 1)
12-Hour Display (AMPM = 0)
Time
HOUR Register
Time
HOUR Register
0
00H
0 a.m.
12H
1
01H
1 a.m.
01H
2
02H
2 a.m.
02H
3
03H
3 a.m.
03H
4
04H
4 a.m.
04H
5
05H
5 a.m.
05H
6
06H
6 a.m.
06H
7
07H
7 a.m.
07H
8
08H
8 a.m.
08H
9
09H
9 a.m.
09H
10
10H
10 a.m.
10H
11
11H
11 a.m.
11H
12
12H
0 p.m.
32H
13
13H
1 p.m.
21H
14
14H
2 p.m.
22H
15
15H
3 p.m.
23H
16
16H
4 p.m.
24H
17
17H
5 p.m.
25H
18
18H
6 p.m.
26H
19
19H
7 p.m.
27H
20
20H
8 p.m.
28H
21
21H
9 p.m.
29H
22
22H
10 p.m.
30H
23
23H
11 p.m.
31H
The HOUR register value is set to 12-hour display when the AMPM bit is “0” and to 24-hour display when the AMPM bit
is “1”.
In 12-hour display, the fifth bit of the HOUR register displays 0 for AM and 1 for PM.
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(9) Day count register (DAY)
The DAY register is an 8-bit register that takes a value of 1 to 31 (decimal) and indicates the count value of days.
It counts up when the hour counter overflows.
This counter counts as follows.
• 01 to 31 (January, March, May, July, August, October, December)
• 01 to 30 (April, June, September, November)
• 01 to 29 (February, leap year)
• 01 to 28 (February, normal year)
When data is written to this register, it is written to a buffer and then to the counter up to 2 clocks (32.768 kHz) later.
Even if the hour count register overflows while this register is being written, this register ignores the overflow and is
set to the value written. Set a decimal value of 01 to 31 to this register in BCD code. If a value outside the range is
set, the register value returns to the normal value after 1 period.
The DAY register can be set by an 8-bit memory manipulation instruction.
Reset signal generation clears this register to 01H.
Figure 9-10. Format of Day Count Register (DAY)
Address: FFF96H
After reset: 01H
R/W
Symbol
7
6
5
4
3
2
1
0
DAY
0
0
DAY20
DAY10
DAY8
DAY4
DAY2
DAY1
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(10) Week count register (WEEK)
The WEEK register is an 8-bit register that takes a value of 0 to 6 (decimal) and indicates the count value of
weekdays.
It counts up in synchronization with the day counter.
When data is written to this register, it is written to a buffer and then to the counter up to 2 clocks (32.768 kHz)
later. Set a decimal value of 00 to 06 to this register in BCD code. If a value outside the range is set, the register
value returns to the normal value after 1 period.
The WEEK register can be set by an 8-bit memory manipulation instruction.
Reset signal generation clears this register to 00H.
Figure 9-11. Format of Week Count Register (WEEK)
Address: FFF95H
After reset: 00H
R/W
Symbol
7
6
5
4
3
2
1
0
WEEK
0
0
0
0
0
WEEK4
WEEK2
WEEK1
Caution The value corresponding to the month count register (MONTH) or the day count register (DAY) is
not stored in the week count register (WEEK) automatically. After reset release, set the week
count register as follow.
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WEEK
Sunday
00H
Monday
01H
Tuesday
02H
Wednesday
03H
Thursday
04H
Friday
05H
Saturday
06H
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(11) Month count register (MONTH)
The MONTH register is an 8-bit register that takes a value of 1 to 12 (decimal) and indicates the count value of
months.
It counts up when the day counter overflows.
When data is written to this register, it is written to a buffer and then to the counter up to 2 clocks (32.768 kHz)
later. Even if the day count register overflows while this register is being written, this register ignores the overflow
and is set to the value written. Set a decimal value of 01 to 12 to this register in BCD code. If a value outside the
range is set, the register value returns to the normal value after 1 period.
The MONTH register can be set by an 8-bit memory manipulation instruction.
Reset signal generation clears this register to 01H.
Figure 9-12. Format of Month Count Register (MONTH)
Address: FFF97H
After reset: 01H
R/W
Symbol
7
6
5
4
3
2
1
0
MONTH
0
0
0
MONTH10
MONTH8
MONTH4
MONTH2
MONTH1
(12) Year count register (YEAR)
The YEAR register is an 8-bit register that takes a value of 0 to 99 (decimal) and indicates the count value of years.
It counts up when the month count register (MONTH) overflows.
Values 00, 04, 08, …, 92, and 96 indicate a leap year.
When data is written to this register, it is written to a buffer and then to the counter up to 2 clocks (32.768 kHz)
later. Even if the MONTH register overflows while this register is being written, this register ignores the overflow
and is set to the value written. Set a decimal value of 00 to 99 to this register in BCD code. If a value outside the
range is set, the register value returns to the normal value after 1 period.
The YEAR register can be set by an 8-bit memory manipulation instruction.
Reset signal generation clears this register to 00H.
Figure 9-13. Format of Year Count Register (YEAR)
Address: FFF98H
After reset: 00H
R/W
Symbol
7
6
5
4
3
2
1
0
YEAR
YEAR80
YEAR40
YEAR20
YEAR10
YEAR8
YEAR4
YEAR2
YEAR1
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(13) Watch error correction register (SUBCUD)
This register is used to correct the watch with high accuracy when it is slow or fast by changing the value that
overflows from the sub-count register (RSUBC) to the second count register (SEC) (reference value: 7FFFH).
The SUBCUD register can be set by an 8-bit memory manipulation instruction.
Reset signal generation clears this register to 00H.
Figure 9-14. Format of Watch Error Correction Register (SUBCUD)
Address: FFF99H
After reset: 00H
R/W
Symbol
7
6
5
4
3
2
1
0
SUBCUD
DEV
F6
F5
F4
F3
F2
F1
F0
DEV
Setting of watch error correction timing
0
Corrects watch error when the second digits are at 00, 20, or 40 (every 20 seconds).
1
Corrects watch error only when the second digits are at 00 (every 60 seconds).
Writing to the SUBCUD register at the following timing is prohibited.
• When DEV = 0 is set: For a period of SEC = 00H, 20H, 40H
• When DEV = 1 is set: For a period of SEC = 00H
F6
Setting of watch error correction value
0
Increases by {(F5, F4, F3, F2, F1, F0) – 1} × 2.
1
Decreases by {(/F5, /F4, /F3, /F2, /F1, /F0) + 1} × 2.
When (F6, F5, F4, F3, F2, F1, F0) = (*, 0, 0, 0, 0, 0, *), the watch error is not corrected. * is 0 or 1.
/F5 to /F0 are the inverted values of the corresponding bits (000011 when 111100).
Range of correction value: (when F6 = 0) 2, 4, 6, 8, … , 120, 122, 124
(when F6 = 1) –2, –4, –6, –8, … , –120, –122, –124
The range of value that can be corrected by using the watch error correction register (SUBCUD) is shown below.
DEV = 0 (correction every 20 seconds)
DEV = 1 (correction every 60 seconds)
Correctable range
–189.2 ppm to 189.2 ppm
–63.1 ppm to 63.1 ppm
Maximum excludes
± 1.53 ppm
± 0.51 ppm
± 3.05 ppm
± 1.02 ppm
quantization error
Minimum resolution
Remark If a correctable range is −63.1 ppm or lower and 63.1 ppm or higher, set 0 to DEV.
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(14) Alarm minute register (ALARMWM)
This register is used to set minutes of alarm.
The ALARMWM register can be set by an 8-bit memory manipulation instruction.
Reset signal generation clears this register to 00H.
Caution
Set a decimal value of 00 to 59 to this register in BCD code. If a value outside the range is set,
the alarm is not detected.
Figure 9-15. Format of Alarm Minute Register (ALARMWM)
Address: FFF9AH
After reset: 00H
R/W
Symbol
7
6
5
4
3
2
1
0
ALARMWM
0
WM40
WM20
WM10
WM8
WM4
WM2
WM1
(15) Alarm hour register (ALARMWH)
This register is used to set hours of alarm.
The ALARMWH register can be set by an 8-bit memory manipulation instruction.
Reset signal generation clears this register to 12H.
However, the value of this register is 00H if the AMPM bit (bit 3 of the RTCC0 register) is set to 1 after reset.
Caution
Set a decimal value of 00 to 23, 01 to 12, or 21 to 32 to this register in BCD code. If a value
outside the range is set, the alarm is not detected.
Figure 9-16. Format of Alarm Hour Register (ALARMWH)
Address: FFF9BH
After reset: 12H
R/W
Symbol
7
6
5
4
3
2
1
0
ALARMWH
0
0
WH20
WH10
WH8
WH4
WH2
WH1
Caution Bit 5 (WH20) of the ALARMWH register indicates AM(0)/PM(1) if AMPM = 0 (if the 12-hour system
is selected).
(16) Alarm week register (ALARMWW)
This register is used to set date of alarm.
The ALARMWW register can be set by an 8-bit memory manipulation instruction.
Reset signal generation clears this register to 00H.
Figure 9-17. Format of Alarm Week Register (ALARMWW)
Address: FFF9CH
After reset: 00H
R/W
Symbol
7
6
5
4
3
2
1
0
ALARMWW
0
WW6
WW5
WW4
WW3
WW2
WW1
WW0
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Here is an example of setting the alarm.
Time of Alarm
Day
12-Hour Display
Sunday Monday Tuesday Wednesday Thursday Friday Saturday Hour
Hour
24-Hour Display
Hour
Hour
10
1
Minute Minute
10
1
10
1
Minute Minute
10
1
W
W
W
W
W
W
W
W
W
W
W
W
W
W
0
1
2
3
4
5
6
Every day, 0:00 a.m.
1
1
1
1
1
1
1
1
2
0
0
0
0
0
0
Every day, 1:30 a.m.
1
1
1
1
1
1
1
0
1
3
0
0
1
3
0
Every day, 11:59 a.m.
1
1
1
1
1
1
1
1
1
5
9
1
1
5
9
Monday through
0
1
1
1
1
1
0
3
2
0
0
1
2
0
0
Sunday, 1:30 p.m.
1
0
0
0
0
0
0
2
1
3
0
1
3
3
0
Monday, Wednesday,
0
1
0
1
0
1
0
3
1
5
9
2
3
5
9
Friday, 0:00 p.m.
Friday, 11:59 p.m.
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9.4 Real-Time Counter Operation
9.4.1 Starting operation of real-time counter
Figure 9-18. Procedure for Starting Operation of Real-Time Counter
Start
RTCEN = 1Note 1
RTCE = 0
Setting AMPM, CT2 to CT0
Supplies input clock.
Stops counter operation.
Selects 12-/24-hour system and interrupt (INTRTC).
Setting SEC (clearing RSUBC)
Sets second count register.
Setting MIN
Sets minute count register.
Setting HOUR
Sets hour count register.
Setting WEEK
Sets week count register.
Setting DAY
Setting MONTH
Setting YEAR
Setting SUBCUDNote 2
Sets day count register.
Sets month count register.
Sets year count register.
Sets watch error correction register.
Clearing IF flags of interrupt
Clears interrupt request flags (RTCIF, RTCIIF).
Clearing MK flags of interrupt
Clears interrupt mask flags (RTCMK, RTCIMK).
RTCE = 1Note 3
Starts counter operation.
Yes
No
INTRTC = 1?
Reading counter
Notes 1. First set the RTCEN bit to 1, while oscillation of the subsystem clock (fSUB) is stable.
2. Set up the SUBCUD register only if the watch error must be corrected. For details about how to
calculate the correction value, see 9.4.8 Example of watch error correction of real-time counter.
3. Confirm the procedure described in 9.4.2 Shifting to STOP mode after starting operation when
shifting to STOP mode without waiting for INTRTC = 1 after RTCE = 1.
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9.4.2 Shifting to STOP mode after starting operation
Perform one of the following processing when shifting to STOP mode immediately after setting the RTCE bit to 1.
However, after setting the RTCE bit to 1, this processing is not required when shifting to STOP mode after the first
INTRTC interrupt has occurred.
• Shifting to STOP mode when at least two subsystem clocks (fSUB) have elapsed after setting the RTCE bit to 1 (see
Figure 9-19, Example 1).
• Checking by polling the RWST bit to become 1, after setting the RTCE bit to 1 and then setting the RWAIT bit to 1.
Afterward, setting the RWAIT bit to 0 and shifting to STOP mode after checking again by polling that the RWST bit
has become 0 (see Figure 9-19, Example 2).
Figure 9-19. Procedure for Shifting to STOP Mode After Setting RTCE bit to 1
Example 1
RTCE = 1
Example 2
RTCE = 1
Sets to counter operation
start
start
Sets to stop the SEC to YEAR
RWAIT = 1
Waiting at least for 2
counters, reads the counter
value, write mode
fSUB clocks
STOP mode
Sets to counter operation
Shifts to STOP mode
No
RWST = 1 ?
Checks the counter wait status
Yes
RWAIT = 0
No
Sets the counter operation
RWST = 0 ?
Yes
STOP mode
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CHAPTER 9 REAL-TIME COUNTER
9.4.3 Reading/writing real-time counter
Read or write the counter after setting 1 to RWAIT first.
Figure 9-20. Procedure for Reading Real-Time Counter
Start
No
RWAIT = 1
Stops SEC to YEAR counters.
Mode to read and write count values
RWST = 1?
Checks wait status of counter.
Yes
Reading SEC
Reads second count register.
Reading MIN
Reads minute count register.
Reading HOUR
Reads hour count register.
Reading WEEK
Reads week count register.
Reading DAY
Reading MONTH
Reading YEAR
RWAIT = 0
No
Reads day count register.
Reads month count register.
Reads year count register.
Sets counter operation.
RWST = 0?Note
Yes
End
Note Be sure to confirm that RWST = 0 before setting STOP mode.
Caution Complete the series of operations of setting the RWAIT bit to 1 to clearing the RWAIT bit to 0 within 1
second.
Remark
The second count register (SEC), minute count register (MIN), hour count register (HOUR), week count
register (WEEK), day count register (DAY), month count register (MONTH), and year count register (YEAR)
may be read in any sequence.
All the registers do not have to be set and only some registers may be read.
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Figure 9-21. Procedure for Writing Real-Time Counter
Start
No
RWAIT = 1
Stops SEC to YEAR counters.
Mode to read and write count values
RWST = 1?
Checks wait status of counter.
Yes
Writing SEC
Writes second count register.
Writing MIN
Writes minute count register.
Writing HOUR
Writes hour count register.
Writing WEEK
Writes week count register.
Writing DAY
Writing MONTH
No
Writes day count register.
Writes month count register.
Writing YEAR
Writes year count register.
RWAIT = 0
Sets counter operation.
RWST = 0?Note
Yes
End
Note Be sure to confirm that RWST = 0 before setting STOP mode.
Caution Complete the series of operations of setting the RWAIT bit to 1 to clearing the RWAIT bit to 0 within 1
second.
Remark
The second count register (SEC), minute count register (MIN), hour count register (HOUR), week count
register (WEEK), day count register (DAY), month count register (MONTH), and year count register (YEAR)
may be written in any sequence.
All the registers do not have to be set and only some registers may be written.
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9.4.4 Setting alarm of real-time counter
Set time of alarm after setting 0 to WALE first.
Figure 9-22. Alarm Setting Procedure
Start
WALE = 0
Match operation of alarm is invalid.
WALIE = 1
Interrupt is generated when alarm matches.
Setting ALARMWM
Sets alarm minute register.
Setting ALARMWH
Sets alarm hour register.
Setting ALARMWW
Sets alarm week register.
WALE = 1
No
Match operation of alarm is valid.
INTRTC = 1?
Yes
WAFG = 1?
No
Match detection of alarm Yes
Alarm processing
Constant-period interrupt servicing
Remarks 1. The alarm week register (ALARMWW), alarm hour register (ALARMWH), and alarm week register
(ALARMWW) may be written in any sequence.
2. Fixed-cycle interrupts and alarm match interrupts use the same interrupt source (INTRTC). When using
these two types of interrupts at the same time, which interrupt occurred can be judged by checking the
fixed-cycle interrupt status flag (RIFG) and the alarm detection status flag (WAFG) upon INTRTC
occurrence.
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9.4.5 1 Hz output of real-time counter
Figure 9-23. 1 Hz Output Setting Procedure
Start
Stops counter operation.
RTCE = 0
RCLOE1 = 1
Enables output of the RTC1HZ pin (1 Hz).
RTCE = 1
Starts counter operation.
Output start from RTC1HZ pin
Caution First set the RTCEN bit to 1, while oscillation of the subsystem clock (fSUB) is stable.
9.4.6 32.768 kHz output of real-time counter
Figure 9-24. 32.768 kHz Output Setting Procedure
Start
RCLOE0 = 1
Enables output of the RTCCL pin (32.768 kHz).
32.768 kHz output
start from RTCCL pin
Caution First set the RTCEN bit to 1, while oscillation of the subsystem clock (fSUB) is stable.
9.4.7 512 Hz, 16.384 kHz output of real-time counter
Figure 9-25. 512 Hz, 16.384 kHz output Setting Procedure
Start
512 Hz Output: RCKDIV = 0
16.384 kHz Output: RCKDIV = 1
RCLOE2 = 1
Selects output frequency of
the RTCDIV pin.
Output of the RTCDIV pin is enabled.
512 Hz or 16.384 kHz
output start from RTCDIV pin
Caution First set the RTCEN bit to 1, while oscillation of the subsystem clock (fSUB) is stable.
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9.4.8 Example of watch error correction of real-time counter
The watch can be corrected with high accuracy when it is slow or fast, by setting a value to the watch error correction
register.
Example of calculating the correction value
The correction value used when correcting the count value of the sub-count register (RSUBC) is calculated by
using the following expression.
Set the DEV bit to 0 when the correction range is −63.1 ppm or less, or 63.1 ppm or more.
(When DEV = 0)
Correction valueNote = Number of correction counts in 1 minute ÷ 3 = (Oscillation frequency ÷ Target frequency − 1)
¯ 32768 ¯ 60 ÷ 3
(When DEV = 1)
Correction valueNote = Number of correction counts in 1 minute = (Oscillation frequency ÷ Target frequency − 1) ¯
32768 ¯ 60
Note The correction value is the watch error correction value calculated by using bits 6 to 0 of the watch error
correction register (SUBCUD).
(When F6 = 0) Correction value = {(F5, F4, F3, F2, F1, F0) − 1} ¯ 2
(When F6 = 1) Correction value = − {(/F5, /F4, /F3, /F2, /F1, /F0) + 1} ¯ 2
When (F6, F5, F4, F3, F2, F1, F0) is (*, 0, 0, 0, 0, 0, *), watch error correction is not performed. “*” is 0 or 1.
/F5 to /F0 are bit-inverted values (000011 when 111100).
Remarks 1.
2.
The correction value is 2, 4, 6, 8, … 120, 122, 124 or −2, −4, −6, −8, … −120, −122, −124.
The oscillation frequency is the subsystem clock (fSUB).
It can be calculated from the 32 kHz output frequency of the RTCCL pin or the output frequency of the
RTC1HZ pin ¯ 32768 when the watch error correction register is set to its initial value (00H).
3.
The target frequency is the frequency resulting after correction performed by using the watch error
correction register.
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Correction example <1>
Example of correcting from 32772.3 Hz to 32768 Hz (32772.3 Hz − 131.2 ppm)
[Measuring the oscillation frequency]
The oscillation frequencyNote of each product is measured by outputting about 32.768 kHz from the RTCCL pin or
outputting about 1 Hz from the RTC1HZ pin when the watch error correction register (SUBCUD) is set to its initial value
(00H).
Note See 9.4.5 1 Hz output of real-time counter for the setting procedure of outputting about 1 Hz from the RTC1HZ
pin, and 9.4.6 32.768 kHz output of real-time counter for the setting procedure of outputting about 32 kHz from
the RTCCL pin.
[Calculating the correction value]
(When the output frequency from the RTCCL pin is 32772.3 Hz)
If the target frequency is assumed to be 32768 Hz (32772.3 Hz − 131.2 ppm), the correction range for −131.2 ppm is
−63.1 ppm or less, so assume DEV to be 0.
The expression for calculating the correction value when DEV is 0 is applied.
Correction value = Number of correction counts in 1 minute ÷ 3
= (Oscillation frequency ÷ Target frequency − 1) ¯ 32768 ¯ 60 ÷ 3
= (32772.3 ÷ 32768 − 1) ¯ 32768 ¯ 60 ÷ 3
= 86
[Calculating the values to be set to (F6 to F0)]
(When the correction value is 86)
If the correction value is 0 or more (when delaying), assume F6 to be 0.
Calculate (F5, F4, F3, F2, F1, F0) from the correction value.
{ (F5, F4, F3, F2, F1, F0) − 1} ¯ 2
= 86
(F5, F4, F3, F2, F1, F0)
= 44
(F5, F4, F3, F2, F1, F0)
= (1, 0, 1, 1, 0, 0)
Consequently, when correcting from 32772.3 Hz to 32768 Hz (32772.3 Hz − 131.2 ppm), setting the correction
register such that DEV is 0 and the correction value is 86 (bits 6 to 0 of SUBCUD register: 0101100) results in 32768
Hz (0 ppm).
Figure 9-26 shows the operation when (DEV, F6, F5, F4, F3, F2, F1, F0) is (0, 0, 1, 0, 1, 1, 0, 0).
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7FFFH + 56H (86)
7FFFH + 56H (86)
7FFFH + 56H (86)
7FFFH+56H (86)
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Figure 9-26. Operation when (DEV, F6, F5, F4, F3, F2, F1, F0) = (0, 0, 1, 0, 1, 1, 0, 0)
Count start
RSUBC
count value
SEC
0000H
8054H 8055H 0000H 0001H
00
01
7FFFH
0000H 0001H
19
7FFFH 0000H
8054H 8055H
20
0000H 0001H
39
7FFFH 0000H
8054H 8055H
40
0000H 0001H
59
7FFFH 0000H
8054H 8055H
00
CHAPTER 9 REAL-TIME COUNTER
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CHAPTER 9 REAL-TIME COUNTER
Correction example <2>
Example of correcting from 32767.4 Hz to 32768 Hz (32767.4 Hz + 18.3 ppm)
[Measuring the oscillation frequency]
The oscillation frequencyNote of each product is measured by outputting about 32.768 kHz from the RTCCL pin or
outputting about 1 Hz from the RTC1HZ pin when the watch error correction register (SUBCUD) is set to its initial value
(00H).
Note See 9.4.5 1 Hz output of real-time counter for the setting procedure of outputting about 1 Hz from the RTC1HZ
pin, and 9.4.6 32.768 kHz output of real-time counter for the setting procedure of outputting about 32 kHz from
the RTCCL pin.
[Calculating the correction value]
(When the output frequency from the RTCCL pin is 0.9999817 Hz)
Oscillation frequency = 32768 ¯ 0.9999817 ≈ 32767.4 Hz
Assume the target frequency to be 32768 Hz (32767.4 Hz + 18.3 ppm) and DEV to be 1.
The expression for calculating the correction value when DEV is 1 is applied.
Correction value = Number of correction counts in 1 minute
= (Oscillation frequency ÷ Target frequency − 1) ¯ 32768 ¯ 60
= (32767.4 ÷ 32768 − 1) ¯ 32768 ¯ 60
= −36
[Calculating the values to be set to (F6 to F0)]
(When the correction value is −36)
If the correction value is 0 or less (when quickening), assume F6 to be 1.
Calculate (F5, F4, F3, F2, F1, F0) from the correction value.
− {(/F5, /F4, /F3, /F2, /F1, /F0) − 1} ¯ 2
= −36
(/F5, /F4, /F3, /F2, /F1, /F0)
= 17
(/F5, /F4, /F3, /F2, /F1, /F0)
= (0, 1, 0, 0, 0, 1)
(F5, F4, F3, F2, F1, F0)
= (1, 0, 1, 1, 1, 0)
Consequently, when correcting from 32767.4 Hz to 32768 Hz (32767.4 Hz + 18.3 ppm), setting the correction
register such that DEV is 1 and the correction value is −36 (bits 6 to 0 of the SUBCUD register: 1101110) results in
32768 Hz (0 ppm).
Figure 9-27 shows the operation when (DEV, F6, F5, F4, F3, F2, F1, F0) is (1, 1, 1, 0, 1, 1, 1, 0).
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7FFFH − 24H (36)
7FFFH − 24H (36)
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Figure 9-27. Operation when (DEV, F6, F5, F4, F3, F2, F1, F0) = (1, 1, 1, 0, 1, 1, 1, 0)
Count start
RSUBC
count value
SEC
0000H
7FDAH 7FDBH 0000H 0001H
00
01
7FFFH
0000H 0001H
19
7FFFH 0000H 0001H
20
7FFFH
0000H 0001H
39
7FFFH 0000H 0001H
40
7FFFH
0000H 0001H
59
7FFFH 0000H
7FDAH 7FDBH
00
CHAPTER 9 REAL-TIME COUNTER
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CHAPTER 10 COMPARATORS/PROGRAMMABLE GAIN AMPLIFIERS
(78K0R/KC3-L, 78K0R/KD3-L, 78K0R/KE3-L only)
The number of input pins of the comparators differs, depending on the product.
Input pins of the
78K0R/KC3-L
78K0R/KC3-L
78K0R/KD3-L
78K0R/KE3-L
comparators
(40-pin)
(44, 48-pin)
CMP0P
√
√
√
√
CMP0M
√
√
√
√
CMP1P
−
√
√
√
CMP1M
√
√
√
√
10.1 Features of Comparator and Programmable Gain Amplifier
The features of the programmable gain amplifiers and comparators are described below.
{ Comparators
• A comparator is equipped with two channels (CMP0, CMP1).
• Negative-side input pins (CMP0M, CMP1M) and a positive-side input pin (CMP0P, CMP1P Note 1) can be connected.
• The output signal of a programmable gain amplifier can be used as the positive-side input signal of a comparator
Note 2
.
• The CMP0M and CMP1M pin inputs and the internal generation reference voltage (6 combinations for each
comparator) can be selected as the reference voltage.
• The elimination width of the noise elimination digital filter can be selected.
• An interrupt request is generated when the reference voltage is exceeded (INTCMP0, INTCMP1).
{ Programmable gain amplifiers
• A programmable gain amplifier amplifies and outputs an analog voltage that is input. One among five amplification
factors can be selected.
• The output signal of a programmable gain amplifier can be used as the positive-side input signal of a comparator
Note 2
.
• The output signal of a programmable gain amplifier can be selected as the analog input of an A/D converter.
Notes 1.
There is no positive-side input pin (CMP1P) for comparator 1 in the 78K0R/KC3-L (40-pin). Only the
2.
When using the output signals of the programmable gain amplifiers as the positive-side input signals
signal output from the programmable gain amplifier can be used for the input voltage.
of the comparators, the output signal is simultaneously input to both channels of comparators 0 and 1.
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Figure 10-1. Block Diagram of Comparator/Programmable Gain Amplifier (78K0R/KC3-L (40-pin))
Internal bus
Comparator 1 internal reference voltage
setting register (C1RVM)
Comparator 1 control register (C1CTL)
C1EN
C1VRE C1VRS2 C1VRS1 C1VRS0
Selector
+
C1INV C1DFS2 C1DFS1 C1DFS0
Output reversal
circuit
−
Noise filter
INTCMP1
AVREF
Controller
CMP1M/P83
C1OE
Programmable
gain amplifier
AVSS
Selector
Programmable gain amplifier output signal (PGAO)
Selector
PGAI/CMP0P/INTP3/P80
CMP0M/P81
A/D converter
+
Output reversal
circuit
−
Noise filter
INTCMP0
Controller
AVREF
AVSS
OAEN OAVG2 OAVG1 OAVG0
C0VRE C0VRS2 C0VRS1 C0VRS0
Programmable gain amplifier
control register (OAM)
C0EN
C0OE
Comparator 0 internal reference voltage
setting register (C0RVM)
C0INV C0DFS2 C0DFS1 C0DFS0
Comparator 0 control register (C0CTL)
Internal bus
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Figure 10-2. Block Diagram of Comparator/Programmable Gain Amplifier (78K0R/KC3-L (44-pin, 48-pin)),
78K0R/KD3-L, 78K0R/KE3-L
Internal bus
Comparator 1 internal reference voltage
setting register (C1RVM)
Comparator 1 control register (C1CTL)
C1EN
Selector
C1VRE C1VRS2 C1VRS1 C1VRS0
Selector
CMP1P/INTP7/P82
C1INV C1DFS2 C1DFS1 C1DFS0
Output reversal
circuit
−
Noise filter
INTCMP1
AVREF
Controller
CMP1M/P83
+
C1OE
Programmable
gain amplifier
AVSS
Selector
Programmable gain amplifier output signal (PGAO)
Selector
PGAI/CMP0P/INTP3/P80
CMP0M/P81
A/D converter
+
Output reversal
circuit
−
Noise filter
INTCMP0
Controller
AVREF
AVSS
OAEN OAVG2 OAVG1 OAVG0
C0VRE C0VRS2 C0VRS1 C0VRS0
Programmable gain amplifier
control register (OAM)
C0EN
C0OE
Comparator 0 internal reference voltage
setting register (C0RVM)
C0INV C0DFS2 C0DFS1 C0DFS0
Comparator 0 control register (C0CTL)
Internal bus
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10.2 Configurations of Comparator and Programmable Gain Amplifier
The comparators and programmable gain amplifiers consist of the following hardware.
Table 10-1. Configurations of Comparator and Programmable Gain Amplifier
Item
Control registers
Configuration
Peripheral enable register 1 (PER1)
Programmable gain amplifier control register (OAM)
Comparator 0 and 1 control registers (C0CTL, C1CTL)
Comparator 0 and 1 internal reference voltage setting registers
(C0RVM, C1RVM)
Port input mode register 8 (PIM8)
Port mode register 8 (PM8)
10.3 Registers Controlling Comparators and Programmable Gain Amplifiers
The comparators and programmable gain amplifiers use the following eight registers.
• Peripheral enable register 1 (PER1)
• Programmable gain amplifier control register (OAM)
• Comparator 0 and 1 control registers (C0CTL, C1CTL)
• Comparator 0 and 1 internal reference voltage setting registers (C0RVM, C1RVM)
• Port input mode register 8 (PIM8)
• Port mode register 8 (PM8)
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(1) Peripheral enable register 1 (PER1)
This register is used to enable or disable supplying the clock to the peripheral hardware. Power consumption and
noise are reduced by stopping the clock supply to unused hardware.
Make sure to set bit 3 (OACMPEN) to 1 to use a comparator or a programmable gain amplifier.
The PER1 register can be set by a 1-bit or 8-bit memory manipulation instruction.
Reset signal generation clears this register to 00H.
Cautions 1. Make sure to set the OACMPEN bit to 1 first, when setting the comparator or programmable
gain amplifier.
Writing to the control register of the comparator or programmable gain
amplifier will be ignored and all values read will be initialized when the OACMPEN bit is set to
0.
2. Make sure to set bits 0 to 2 and bits 4 to 7 of the PER1 register to “0”.
Figure 10-3. Format of Peripheral Enable Register 1 (PER1)
Address: F00F1H After reset: 00H R/W
Symbol
7
6
5
4
<3>
2
1
0
PER1
0
0
0
0
OACMPEN
0
0
0
OACMPEN
0
Control of comparator and programmable gain amplifier input clock supply
Stops input clock supply.
• SFR used by the comparator and programmable gain amplifier cannot be written.
• The comparator and programmable gain amplifier is in the reset status.
1
Enables input clock supply.
• SFR used by the comparator and programmable gain amplifier can be read and written.
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(2) Programmable gain amplifier control register (OAM)
This register is used to enable or disable the operation of a programmable gain amplifier and set the amplification
factor.
The OAM register can be set by a 1-bit or 8-bit memory manipulation instruction.
Reset signal generation clears this register to 00H.
Figure 10-4. Format of Programmable Gain Amplifier Control Register (OAM)
Address: F0240H After reset: 00H R/W
Symbol
<7>
6
5
4
3
2
1
0
OAM
OAEN
0
0
0
0
OAVG2
OAVG1
OAVG0
OAEN
Programmable gain amplifier operation control
0
Stops operation
1
Enables operation
Enables external input from the programmable gain amplifier input pin (PGAI)
Inputs the programmable gain amplifier output signal as the positive-side input voltage of comparators 0
and 1
OAVG2
OAVG1
OAVG0
0
0
1
×4
0
1
0
×6
0
1
1
×8
1
0
0
×10
1
0
1
×12
Other than the above
Input voltage amplification factor setting
Setting prohibited
Cautions 1. Set the amplification factor before enabling (OAEN = 1) the operation of the programmable
gain amplifier. Changing the amplification factor setting in the operation enabled state (OAEN
= 1) is prohibited.
2.
Set the comparator n control register (CnCTL) after setting the OAM register.
3.
To select a program gain amplifier output signal (PGAO) as an analog input of the A/D
converter, set OAEN = 1, wait for 3 μs by software, then start A/D conversion (ADCS = 1).
Remark
n = 0, 1
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(3) Comparator n control register (CnCTL)
This register is used to control the operation of comparator n, enable or disable comparator output, reverse the
output, and set the noise elimination width.
The CnCTL register can be set by a 1-bit or 8-bit memory manipulation instruction.
Reset signal generation clears this register to 00H.
Figure 10-5. Format of Comparator n Control Register (CnCTL)
Address: F0241H (C0CTL), F0242H (C1CTL) After reset: 00H R/W
Symbol
<7>
6
5
4
3
2
1
0
CnCTL
CnEN
0
0
CnOE
CnINV
CnDFS2
CnDFS1
CnDFS0
CnEN
Comparator operation control
0
Stops operation
1
Enables operation
Enables input to the external pins on the positive and negative sides of comparator n Notes 1, 2
CnOE
Enabling or disabling of comparator output
0
Disables output (output signal = fixed to low level)
1
Enables output
CnINV
Output reversal setting
0
Forward
1
Reverse Note 3
CnDFS2
CnDFS1
CnDFS0
Noise elimination width setting (fCLK = 20 MHz)
0
0
0
Noise filter unused
0
0
1
250 ns
0
1
0
500 ns
0
1
1
1 μs
0
0
2 μs
1
Other than the above
Setting prohibited
(Notes, Cautions, and Remarks are listed on the next page.)
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Notes 1. If OAEN = 1 (bit 7 of the programmable gain amplifier control register (OAM)) and the CnEN bit is set to
1, a programmable gain amplifier output signal will be input to the positive-side input of comparator n.
2. There is no positive-side input pin for comparator 1 in the 78K0R/KC3-L (40-pin). Only the signal output
from the programmable gain amplifier can be used for the input voltage.
3. An interrupt will occur if the CnINV bit is set (CnINV = 1) while operation is stopped (CnEN = 0) or when
output is prohibited (CnOE = 0). It is therefore necessary to mask the interrupt (CMPMKn = 1), and then
enable operation (CnEN = 1) and output (CnOE = 1). After operation and output have been enabled, se
t reverse output (CnINV = 1), clear the interrupt request flag (CMPIFn = 0), and then unmask the interru
pt (CMPMKn = 0). While reverse output is in progress, be sure to mask the interrupt (CMPMKn = 1) bef
ore stopping operation (CnEN = 0) or prohibiting output (CnOE = 0).
Cautions 1. Rewrite the CnINV and CnDFS2 to CnDFS0 bits after setting the comparator output to the
disabled state (CnOE = 0).
2. With the noise elimination width, an extra CPU clock (fCLK) may be eliminated from the setting
value.
(Example: When fCLK = 20 MHz, CnDFS2 to CnDFS0 = 001, noise elimination width = 250 to 300
ns)
3. To operate the comparator in combination with a programmable gain amplifier, set the
operation of the comparator after setting the operation of the programmable gain amplifier
(see Figure 10-10 and Figure 10-11).
4. The negative-side external pin input of the comparator will be cutoff when the CnVRE bit of
the comparator n internal reference voltage selection register (CnRVM) is set (1), regardless
of the value that enables or disables the comparator operation (CnEN bit).
5. Enable interrupt signals after setting CnEN = 1 and then waiting for 1 μs by software.
Remarks 1. fCLK: CPU or peripheral hardware clock frequency
2. n = 0, 1
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(4) Comparator n internal reference voltage selection register (CnRVM)
This register is used to set the internal reference voltage of comparator n. The internal reference voltage can be
selected from six voltages that use AVREF.
The CnRVM register can be set by a 1-bit or 8-bit memory manipulation instruction.
Reset signal generation clears this register to 00H.
Figure 10-6. Format of Comparator n Internal Reference Voltage Selection Register (CnRVM)
Address: F0243H (C0RVM), F0244H (C1RVM) After reset: 00H R/W
Symbol
<7>
6
5
4
3
2
1
0
CnRVM
CnVRE
0
0
0
0
CnVRS2
CnVRS1
CnVRS0
Internal reference voltage operation control
CnVRE
0
Stops operation
1
Enables operation
Connects the internal reference voltage to the negative-side input of comparator n
CnVRS2
CnVRS1
Reference voltage setting
CnVRS0
Reference voltage settable with
Reference voltage settable with
comparator 0 (n = 0)
comparator 1 (n = 1)
0
0
0
Setting prohibited
0
0
1
2AVREF/16
3AVREF/16
0
1
0
4AVREF/16
5AVREF/16
0
1
1
6AVREF/16
7AVREF/16
1
0
0
8AVREF/16
9AVREF/16
1
0
1
10AVREF/16
11AVREF/16
1
1
0
12AVREF/16
13AVREF/16
1
1
1
Setting prohibited
Cautions 1. The operation of the comparator is controlled by the CnEN bit when the operation of the
internal reference voltage is stopped (CnVRE = 0).
2. The negative-side external pin input of the comparator will be cutoff when the CnVRE bit is
set (1), regardless of the value that enables or disables the comparator operation (CnEN bit).
3. Set the reference voltage before enabling the operation of the internal reference voltage
(CnVRE = 1). Changing the reference voltage setting in the operation enabled state (CnVRE =
1) is prohibited.
4. Be sure to change the CnRVM register while CnEN = 0 (comparator operation stopped).
Remark
n = 0, 1
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(5) Port input mode register 8 (PIM8)
This register is used to enable or disable port 8 digital input in 1-bit units.
Set to digital input disable (used as analog input) to use a comparator or a programmable gain amplifier. Set to
digital input enable to use the port function or the external interrupt function, because digital input disable (used as
analog input) is set by default.
The PIM8 register can be set by a 1-bit or 8-bit memory manipulation instruction.
Reset signal generation clears this register to 00H.
Figure 10-7. Format of Port Input Mode Register 8 (PIM8)
Address: F0048H After reset: 00H R/W
Symbol
PIM8
7
6
0
0
4
0
0
3
PIM83
2
PIM82
Note
1
0
PIM81
PIM80
Selection of enabling or disabling P8n pin digital input (n = 0 to 3)
PIM8n
Note
5
0
Disables digital input (used as analog input)
1
Enables digital input
PIM82 bit is not provided in the 78K0R/KC3-L (40-pin).
(6) Port mode register 8 (PM8)
This register is used to set port 8 input or output in 1-bit units.
Set the PM80 to PM83 bits to 1 to use the P80/CMP0P/INTP3/PGAI, P81/CMP0M, P82/CMP1P/INTP7, or
P83/CMP1M pin as the positive-side or negative-side input function of the comparator, or the programmable gain
amplifier input function.
The output latches of P80 to P83 may be 0 or 1 at this time.
The PM80 to PM83 bits can be set by a 1-bit or 8-bit memory manipulation instruction.
Reset signal generation sets this register to FFH.
Figure 10-8. Format of Port Mode Register 8 (PM8)
Address: FFF28H After reset: FFH R/W
Symbol
PM8
7
1
6
1
5
1
1
3
PM83
2
PM82
Note
1
0
PM81
PM80
P8n pin I/O mode selection (n = 0 to 3)
PM8n
Note
4
0
Output mode (output buffer on)
1
Input mode (output buffer off)
PM82 bit is not provided in the 78K0R/KC3-L (40-pin).
Cautions 1. The port function that is alternatively used as the CMP0M, CMP1M pin can be used in the
input mode, when the CMP0P, CMP1P pin is selected as the positive-side input of the
comparator, and the internal reference voltage is used on the negative side. Using the output
mode, however, is prohibited.
2. 78K0R/KC3-L (40-pin) does not have a P82/CMP1P/INTP7 pin.
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10.4 Operations of Comparator and Programmable Gain Amplifier
10.4.1 Starting comparator and programmable gain amplifier operation
The procedures for starting the operation of a comparator and a programmable gain amplifier are described below,
separately for each use method.
{ Using only a comparator
Note
• Using the external pin input for the comparator reference voltage (Figure 10-9)
• Using the internal reference voltage for the comparator reference voltage (Figure 10-10)
{ Using a comparator and a programmable gain amplifier (using the programmable gain amplifier output voltage as the
comparator compare voltage input)
• Using the external pin input for the comparator reference voltage (Figure 10-11)
• Using the internal reference voltage for the comparator reference voltage (Figure 10-12)
{ Using the programmable gain amplifier output voltage as the A/D converter analog input (Figure 10-13)
Note
There is no positive-side input pin for comparator 1 in the 78K0R/KC3-L (40-pin). Only the signal output
from the programmable gain amplifier can be used for the input voltage.
Figure 10-9. Using the External Pin Input for the Comparator Reference Voltage (Using Only a Comparator)
Start
PM8 register setting
Set the PM8 register to the input mode.
PIM8 register setting
Set to the digital input disable state
(use port 8 as the analog input).
PER1 register setting
Cancel the reset state of the comparator or
programmable gain amplifier and start clock
supply.
CnCTL register setting
Use the CnINV bit of the CnCTL register to select
forwarding or reversing of the output. Use the
CnDFS0 to CnDFS2 bits to select the noise
elimination width.
CnEN bit setting
Enable the comparator operation by setting (1)
the CnEN bit of the CnCTL register. Input to the
positive side and negative side of the comparator
from the external pin will be enabled at the same
time.
Wait (1 μ s or more)
CnOE bit setting
Enable the comparator output signal by setting
(1) the CnOE bit of the CnCTL register.
Operation start
Remark
n = 0 and 1 (78K0R/KC3-L (40-pin): n = 0).
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Figure 10-10. Using the Internal Reference Voltage for the Comparator Reference Voltage
(Using Only a Comparator)
Start
PM8 register setting
Set the PM8 register to the input mode.
PIM8 register setting
Set to the digital input disable state
(use port 8 as the analog input).
PER1 register setting
Cancel the reset state of the comparator or
programmable gain amplifier and start clock
supply.
CnRVM register setting
CnVRE bit setting
Select the internal reference voltage by using the
CnVRS0 to CnVRS2 bits of the CnRVM regster.
Set to use the internal reference voltage by
setting (1) the CnVRE bit of the CnRVM
regster. The internal reference voltage will be
input to the negative side of the comparator at
the same time.
CnCTL register setting
Use the CnINV bit of the CnCTL register to select
forwarding or reversing of the output. Use the
CnDFS0 to CnDFS2 bits to select the noise
elimination width.
CnEN bit setting
Enable the comparator operation by setting (1) the
CnEN bit of the CnCTL regster. Input to the
positive side of the comparator from the external
pin will be enabled at the same time.
Wait (1.5 μ s or more)
CnOE bit setting
Enable the comparator output signal by setting
(1) the CnOE bit of the CnCTL regster.
Operation start
Remark
n = 0 and 1 (78K0R/KC3-L (40-pin): n = 0).
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Figure 10-11. Using the External Pin Input for the Comparator Reference Voltage (Using a Comparator and a
Programmable Gain Amplifier)
Start
PM8 register setting
Set the PM8 register to the input mode.
PIM8 register setting
Set to the digital input disable state
(use port 8 as the analog input).
PER1 register setting
Cancel the reset state of the comparator or
programmable gain amplifier and start clock
supply.
OAM register setting
OAEN bit setting
Set the amplification factor by using the OAVG0 to
OAVG2 bits of the OAM register.
Enable the programmable gain amplifier operation by setting
(1) the OAEN bit of the OAM register. At the same time,
enable the external input from the programmable gain
amplifier input pin (PGAI). The programmable gain amplifier
output signal will be input as the positive-side input voltage of
the comparator.
Wait (3 μ s or more)
CnCTL register setting
Use the CnINV bit of the CnCTL register to select
forwarding or reversing of the output. Use the
CnDFS0 to CnDFS2 bits to select the noise
elimination width.
CnEN bit setting
Enable the comparator operation by setting (1)
the CnEN bit of the CnCTL register. Input to the
negative side of the comparator from the external
pin will be enabled at the same time.
Wait (1 μ s or more)
CnOE bit setting
Enable the comparator output signal by setting
(1) the CnOE bit of the CnCTL register.
Operation start
Remark
n = 0 and 1 (78K0R/KC3-L (40-pin): n = 0).
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Figure 10-12. Using the Internal Reference Voltage for the Comparator Reference Voltage (Using a Comparator
and a Programmable Gain Amplifier)
Start
PM8 register setting
Set the PM8 register to the input mode.
PIM8 register setting
Set to the digital input disable state
(use port 8 as the analog input).
PER1 register setting
Cancel the reset state of the comparator or
programmable gain amplifier and start clock
supply.
OAM register setting
Set the amplification factor by using the OAVG0 to
OAVG2 bits of the OAM register.
OAEN bit setting
Enable the programmable gain amplifier operation by
setting (1) the OAEN bit of the OAM register. At the same
time, enable the external input from the programmable
gain amplifier input pin (PGAI). The programmable gain
amplifier output signal will be input as the positive-side
input voltage of the comparator.
Wait (3 μ s or more)
CnRVM register setting
CnVRE bit setting
CnCTL register setting
CnEN bit setting
Use the CnVRS0 to CnVRS2 bits of the CnRVM
register to select the internal reference voltage.
Set to use the internal reference voltage by setting
(1) the CnVRE bit of the CnRVM register. The
internal reference voltage will be input to the
negative side of the comparator at the same time.
Use the CnINV bit of the CnCTL register
to select forwarding or reversing of the
output. Use the CnDFS0 to CnDFS2 bits
to select the noise elimination width.
Enable the comparator operation by setting (1)
the CnEN bit of the CnCTL register.
Wait (1.5 μ s or more)
CnOE bit setting
Enable the comparator output signal by setting
(1) the CnOE bit of the CnCTL register.
Operation start
Remark
n = 0, 1
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Perform the following settings before selecting the programmable gain amplifier output signal as the analog input by
using the analog input channel specification register (ADS) of the A/D converter (refer to 13.4.1 Basic operations of A/D
converter).
Figure 10-13. Using the Programmable Gain Amplifier Output Voltage as the A/D Converter Analog Input
Start
PM8 register setting
Set the PM8 register to the input mode.
PIM8 register setting
Set to the digital input disable state
(use port 8 as the analog input).
PER1 register setting
Cancel the reset state of the comparator or
programmable gain amplifier and start clock
supply.
OAM register setting
Set the amplification factor by using the OAVG0 to
OAVG2 bits of the OAM register.
OAEN bit setting
Enable the programmable gain amplifier operation by
setting (1) the OAEN bit of the OAM register. At the
same time, enable the external input from the
programmable gain amplifier input pin (PGAI). The
programmable gain amplifier output signal will be input
as the positive-side input voltage of the comparator.
A/D converter register setting
Caution Ensure that 3 μs elapses before A/D conversion starts after setting the OAEN bit.
Remark
n = 0, 1
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10.4.2 Stopping comparator and programmable gain amplifier operation
The procedures for stopping the operation of a comparator and a programmable gain amplifier are described below,
separately for each use method.
{ Using only a comparator (Figure 10-14)
{ Using the programmable gain amplifier output voltage as the comparator compare voltage input (Figure 10-15)
{ Using the programmable gain amplifier output voltage as the A/D converter analog input (Figure 10-16)
Figure 10-14. Using Only a Comparator
Operation in progress
CnOE bit setting
Clear (0) the CnOE bit of the CnCTL register.
PER1 register setting
Stop the clock supply to the comparator or
programmable gain amplifier and initialize the
setting register.
Operation stop
Remark
n = 0 and 1 (78K0R/KC3-L (40-pin): n = 0).
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Figure 10-15. Using the Programmable Gain Amplifier Output Voltage as the
Comparator Compare Voltage Input
Operation in progress
CnOE bit setting
Clear (0) the CnOE bit of the CnCTL register.
OAEN bit setting
Clear (0) the OAEN bit of the OAM register and
prohibit the programmable gain amplifier input.
PER1 register setting
Stop the clock supply to the comparator or
programmable gain amplifier and initialize the
setting register.
Operation stop
Figure 10-16. Using the Programmable Gain Amplifier Output Voltage as the A/D Converter Analog Input
Operation in progress
ADCS bit setting
Clear (0) the ADCS bit of the A/D converter mode
register (ADM).
OAEN bit setting
Clear (0) the OAEN bit of the OAM register and
prohibit the programmable gain amplifier input.
PER1 register setting
Stop the clock supply to the comparator or
programmable gain amplifier and initialize the
setting register.
Operation stop
Remark
n = 0, 1
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CHAPTER 11 CLOCK OUTPUT/BUZZER OUTPUT CONTROLLER
CHAPTER 11 CLOCK OUTPUT/BUZZER OUTPUT CONTROLLER
The number of output pins of the clock output and buzzer output controllers differs, depending on the product.
Furthermore, 44-pin product of the 78K0R/KC3-L are not provided with clock output and buzzer output controllers.
KC3-L
KC3-L
KC3-L
(40-pin)
(44-pin)
(48-pin)
PCLBUZ0
−
−
PCLBUZ1
−
−
Output pin
KD3-L
KE3-L
KF3-L
KG3-L
√
√
√
√
√
−
−
√
√
√
11.1 Functions of Clock Output/Buzzer Output Controller
The clock output controller is intended for carrier output during remote controlled transmission and clock output for
supply to peripheral ICs.
Buzzer output is a function to output a square wave of buzzer frequency.
One pin can be used to output a clock or buzzer sound.
Two output pins, PCLBUZ0 and PCLBUZ1, are available.
The PCLBUZn pin outputs a clock selected by clock output select register n (CKSn).
Figure 11-1 shows the block diagram of clock output/buzzer output controller.
Remark n = 0:
78K0R/KC3-L (48-pin), 78K0R/KD3-L
n = 0, 1: 78K0R/KE3-L, 78K0R/KF3-L, 78K0R/KG3-L
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CHAPTER 11 CLOCK OUTPUT/BUZZER OUTPUT CONTROLLER
Figure 11-1. Block Diagram of Clock Output/Buzzer Output Controller (1/2)
• 78K0R/KC3-L (48-pin), 78K0R/KD3-L
fMAIN
Prescaler
5
3
fMAIN to fMAIN/24
fSUB to fSUB/27
Selector
fMAIN/211 to fMAIN/213
Clock/buzzer
controller
PCLBUZ0Note/P140
8
fSUB
PCLOE0
PCLOE0
Prescaler
0
0
0
Output latch
(P140)
CSEL0 CCS02 CCS01 CCS00
Clock output select register 0 (CKS0)
Internal bus
• 78K0R/KE3-L
Internal bus
Clock output select register 1 (CKS1)
PCLOE1
0
fMAIN
0
0
CSEL1 CCS12 CCS11 CCS10
Prescaler
PCLOE1
3
fMAIN/211 to fMAIN/213
fMAIN to fMAIN/24
Selector
5
Clock/buzzer
controller
PCLBUZ1Note/P141
fSUB to fSUB/27
Output latch
PM141
(P141)
fMAIN to fMAIN/24
fSUB to fSUB/27
8
fSUB
PCLOE0
Clock/buzzer
controller
PCLBUZ0Note/P140
8
PCLOE0
Prescaler
0
Selector
fMAIN/211 to fMAIN/213
0
0
Output latch
(P140)
CSEL0 CCS02 CCS01 CCS00
Clock output select register 0 (CKS0)
Internal bus
Note
The PCLBUZ0 and PCLBUZ1 pins can output a clock of up to 10 MHz at 2.7 V ≤ VDD. Setting a clock
exceeding 5 MHz at VDD < 2.7 V is prohibited.
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CHAPTER 11 CLOCK OUTPUT/BUZZER OUTPUT CONTROLLER
Figure 11-1. Block Diagram of Clock Output/Buzzer Output Controller (2/2)
• 78K0R/KF3-L, 78K0R/KG3-L
Internal bus
Clock output select register 1 (CKS1)
PCLOE1
0
fMAIN
0
0
CSEL1 CCS12 CCS11 CCS10
Prescaler
PCLOE1
3
fMAIN/211 to fMAIN/213
fMAIN to fMAIN/24
Selector
5
Clock/buzzer
controller
[KF3-L]
PCLBUZ1Note/INTP7/P55
[KG3-L]
PCLBUZ1Note/INTP7/P141
fSUB to fSUB/27
Output latch
(Pxx)
fMAIN to fMAIN/24
fSUB to fSUB/27
8
fSUB
PCLOE0
Selector
fMAIN/211 to fMAIN/213
Clock/buzzer
controller
[KF3-L, KG3-L]
PCLBUZ0Note/INTP6/P140
8
PCLOE0
Prescaler
0
PMxx
0
0
Output latch
(P140)
PM140
CSEL0 CCS02 CCS01 CCS00
Clock output select register 0 (CKS0)
Internal bus
Note
The PCLBUZ0 and PCLBUZ1 pins can output a clock of up to 10 MHz at 2.7 V ≤ VDD. Setting a clock
exceeding 5 MHz at VDD < 2.7 V is prohibited.
Remark 78K0R/KE3-L: PMxx, Pxx = PM55, P55
78K0R/KG3-L: PMxx, Pxx = PM141, P141
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CHAPTER 11 CLOCK OUTPUT/BUZZER OUTPUT CONTROLLER
11.2 Configuration of Clock Output/Buzzer Output Controller
The clock output/buzzer output controller includes the following hardware.
Table 11-1. Configuration of Clock Output/Buzzer Output Controller
Item
Control registers
Configuration
Clock output select registers n (CKSn)
Port mode registers 5, 14 (PM5, PM14)
Port registers 5, 14 (P5, P14)
Note
Note
Note The port mode register and port register to be set differ depending on the product.
78K0R/KC3-L (48-pin), 78K0R/KD3-L: P14
78K0R/KE3-L, 78K0R/KG3-L:
PM14, P14
78K0R/KF3-L:
PM5, P5, PM14, P14
Remark n = 0:
78K0R/KC3-L (48-pin), 78K0R/KD3-L
n = 0, 1: 78K0R/KE3-L, 78K0R/KF3-L, 78K0R/KG3-L
11.3 Registers Controlling Clock Output/Buzzer Output Controller
The following two registers are used to control the clock output/buzzer output controller.
• Clock output select registers n (CKSn)
• Port mode registers 5, 14 (PM5, PM14) Note
Note The port register to be set differ depending on the product.
78K0R/KC3-L (48-pin), 78K0R/KD3-L: None
78K0R/KE3-L, 78K0R/KG3-L:
PM14
78K0R/KF3-L:
PM5, PM14
(1) Clock output select registers n (CKSn)
These registers set output enable/disable for clock output or for the buzzer frequency output pin (PCLBUZn), and
set the output clock.
Select the clock to be output from the PCLBUZn pin by using the CKSn register.
The CKSn register are set by a 1-bit or 8-bit memory manipulation instruction.
Reset signal generation clears these registers to 00H.
Remark n = 0:
78K0R/KC3-L (48-pin), 78K0R/KD3-L
n = 0, 1: 78K0R/KE3-L, 78K0R/KF3-L, 78K0R/KG3-L
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CHAPTER 11 CLOCK OUTPUT/BUZZER OUTPUT CONTROLLER
Figure 11-2. Format of Clock Output Select Register n (CKSn)
Address: FFFA5H (CKS0), FFFA6H (CKS1)
Symbol
CKSn
After reset: 00H
R/W
<7>
6
5
4
3
2
1
0
PCLOEn
0
0
0
CSELn
CCSn2
CCSn1
CCSn0
PCLOEn
PCLBUZn pin output enable/disable specification
0
Output disable (default)
1
Output enable
CSELn
0
CCSn2
0
CCSn1
0
CCSn0
0
PCLBUZn pin output clock selection
fMAIN
fMAIN =
fMAIN =
fMAIN =
5 MHz
10 MHz
20 MHz
5 MHz
Note
10 MHz
Setting
prohibited
0
0
0
1
fMAIN/2
0
0
1
0
fMAIN/2
0
0
0
1
0
1
0
Note
2.5 MHz
5 MHz
10 MHz
2
1.25 MHz
2.5 MHz
5 MHz
fMAIN/2
3
625 kHz
1.25 MHz
2.5 MHz
fMAIN/2
4
312.5 kHz
625 kHz
1.25 MHz
0
1
0
1
fMAIN/2
11
2.44 kHz
4.88 kHz
9.76 kHz
0
1
1
0
fMAIN/2
12
1.22 kHz
2.44 kHz
4.88 kHz
13
610 Hz
1.22 kHz
2.44 kHz
0
1
1
1
fMAIN/2
1
0
0
0
fSUB
1
0
0
1
fSUB/2
1
0
1
0
1
1
1
1
0
0
1
0
32.768 kHz
16.384 kHz
fSUB/2
2
8.192 kHz
fSUB/2
3
4.096 kHz
fSUB/2
4
2.048 kHz
1.024 kHz
1
1
0
1
fSUB/2
5
1
1
1
0
fSUB/2
6
512 Hz
fSUB/2
7
256 Hz
1
Note
1
1
1
1
Note
Use the output clock within a range of 10 MHz. Furthermore, when using the output clock at VDD < 2.7 V, use
it within 5 MHz.
Cautions 1. Change the output clock after disabling clock output (PCLOEn = 0).
2. To shift to STOP mode when the main system clock is selected (CSELn = 0), set PCLOEn = 0
before executing the STOP instruction. When the subsystem clock is selected (CSELn = 1),
PCLOEn = 1 can be set because the clock can be output in STOP mode.
Remarks 1. n = 0:
78K0R/KC3-L (48-pin), 78K0R/KD3-L
n = 0, 1: 78K0R/KE3-L, 78K0R/KF3-L, 78K0R/KG3-L
2. fMAIN: Main system clock frequency
3. fSUB: Subsystem clock frequency
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CHAPTER 11 CLOCK OUTPUT/BUZZER OUTPUT CONTROLLER
(2) Port mode registers 5, 14 (PM5, PM14)
Note
These registers set input/output of ports 5 and 14 in 1-bit units.
When using the ports to be shared with the PCLBUZ0 and PCLBUZ1 pins for clock output and buzzer output, set
the port mode register (PMxx) bit and port register (Pxx) bit corresponding to each port to 0.
Example: When using P140/INTP6/PCLBUZ0 for clock output and buzzer output
Set the PM140 bit of port mode register 14 to 0.
Set the P140 bit of port register 14 to 0.
The PM5 and PM14 registers can be set by a 1-bit or 8-bit memory manipulation instruction.
Reset signal generation sets these registers to FFH (the PM14 register of the 78K0R/KE3-L is set to FEH).
Note The port mode register and port register to be set differ depending on the product.
78K0R/KC3-L (48-pin), 78K0R/KD3-L: P14
78K0R/KE3-L, 78K0R/KG3-L:
PM14, P14
78K0R/KF3-L:
PM5, P5, PM14, P14
Figure 11-3. Format of Port Mode Registers 5, 14 (PM5, PM14) (78K0R/KF3-L)
Address: FFF25H
After reset: FFH
R/W
Symbol
7
6
5
4
3
2
1
0
PM5
1
1
PM55
PM54
PM53
PM52
PM51
PM50
Address: FFF2EH
After reset: FFH
R/W
Symbol
7
6
5
4
3
2
1
0
PM14
1
1
1
PM144
PM143
PM142
1
PM140
PMmn
Pmn pin I/O mode selection (mn = 50 to 55, 140, 142 to 144)
0
Output mode (output buffer on)
1
Input mode (output buffer off)
Remarks 1. The figure shown above presents the format of port mode registers 5 and 14 of the
78K0R/KF3-L product. See below for the format of the port mode registers of other products.
78K0R/KE3-L:
5.3 (1) Port mode registers (PMxx).
78K0R/KF3-L, 78K0R/KG3-L:
6.3 (1) Port mode registers (PMxx).
2. There are no port mode registers in the 48-pin product of the 78K0R/KC3-L or in the 78K0R/
KD3-L.
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CHAPTER 11 CLOCK OUTPUT/BUZZER OUTPUT CONTROLLER
11.4 Operations of Clock Output/Buzzer Output Controller
One pin can be used to output a clock or buzzer sound.
The PCLBUZ0 pin outputs a clock/buzzer selected by the clock output select register 0 (CKS0).
The PCLBUZ1 pin outputs a clock/buzzer selected by the clock output select register 1 (CKS1).
11.4.1 Operation as output pin
The PCLBUZn pin is output as the following procedure.
<1> Select the output frequency with bits 0 to 3 (CCSn0 to CCSn2, CSELn) of the clock output select register (CKSn)
of the PCLBUZn pin (output in disabled status).
<2> Set bit 7 (PCLOEn) of the CKSn register to 1 to enable clock/buzzer output.
Remarks 1. The controller used for outputting the clock starts or stops outputting the clock one clock after enabling or
disabling clock output (PCLOEn bit) is switched. At this time, pulses with a narrow width are not output.
Figure 11-4 shows enabling or stopping output using the PCLOEn bit and the timing of outputting the clock.
2. n = 0:
78K0R/KC3-L (48-pin), 78K0R/KD3-L
n = 0, 1: 78K0R/KE3-L, 78K0R/KF3-L, 78K0R/KG3-L
Figure 11-4. Remote Control Output Application Example
PCLOEn
1 clock elapsed
Clock output
Narrow pulses are not recognized
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CHAPTER 12 WATCHDOG TIMER
CHAPTER 12 WATCHDOG TIMER
12.1 Functions of Watchdog Timer
The watchdog timer operates on the internal low-speed oscillation clock.
The watchdog timer is used to detect an inadvertent program loop. If a program loop is detected, an internal reset
signal is generated.
Program loop is detected in the following cases.
• If the watchdog timer counter overflows
• If a 1-bit manipulation instruction is executed on the watchdog timer enable register (WDTE)
• If data other than “ACH” is written to the WDTE register
• If data is written to the WDTE register during a window close period
When a reset occurs due to the watchdog timer, bit 4 (WDRF) of the reset control flag register (RESF) is set to 1. For
details of the RESF register, see CHAPTER 21 RESET FUNCTION.
When 75% of the overflow time is reached, an interval interrupt can be generated.
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CHAPTER 12 WATCHDOG TIMER
12.2 Configuration of Watchdog Timer
The watchdog timer includes the following hardware.
Table 12-1. Configuration of Watchdog Timer
Item
Configuration
Control register
Watchdog timer enable register (WDTE)
How the counter operation is controlled, overflow time, window open period, and interval interrupt are set by the option
byte.
Table 12-2. Setting of Option Bytes and Watchdog Timer
Setting of Watchdog Timer
Option Byte (000C0H)
Watchdog timer interval interrupt
Bit 7 (WDTINT)
Window open period
Bits 6 and 5 (WINDOW1, WINDOW0)
Controlling counter operation of watchdog timer
Bit 4 (WDTON)
Overflow time of watchdog timer
Bits 3 to 1 (WDCS2 to WDCS0)
Controlling counter operation of watchdog timer
Bit 0 (WDSTBYON)
(in HALT/STOP mode)
Remark For the option byte, see CHAPTER 25 OPTION BYTE.
Figure 12-1. Block Diagram of Watchdog Timer
WDTINT of option
byte (000C0H)
Interval time controller
(Count value overflow time × 3/4)
Interval time interrupt
WDCS2 to WDCS0 of
option byte (000C0H)
fIL
Clock
input
controller
20-bit
counter
fIL/27 to fIL/217
Selector
Reset
output
controller
Count clear
signal
WINDOW1 and
WINDOW0 of option
byte (000C0H)
WDTON of option
byte (000C0H)
Overflow signal
Internal reset signal
Window size
decision signal
Window size check
Watchdog timer enable
register (WDTE)
Write detector to
WDTE except ACH
Internal bus
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CHAPTER 12 WATCHDOG TIMER
12.3 Register Controlling Watchdog Timer
The watchdog timer is controlled by the watchdog timer enable register (WDTE).
(1) Watchdog timer enable register (WDTE)
Writing “ACH” to the WDTE register clears the watchdog timer counter and starts counting again.
This register can be set by an 8-bit memory manipulation instruction.
Reset signal generation sets this register to 9AH or 1AHNote.
Figure 12-2. Format of Watchdog Timer Enable Register (WDTE)
Address: FFFABH
Symbol
After reset: 9AH/1AHNote
7
6
R/W
5
4
3
2
1
0
WDTE
Note The WDTE register reset value differs depending on the WDTON bit setting value of the option byte
(000C0H). To operate watchdog timer, set the WDTON bit to 1.
WDTON Bit Setting Value
WDTE Register Reset Value
0 (watchdog timer count operation disabled)
1AH
1 (watchdog timer count operation enabled)
9AH
Cautions 1. If a value other than “ACH” is written to the WDTE register, an internal reset signal is
generated.
2. If a 1-bit memory manipulation instruction is executed for the WDTE register, an internal reset
signal is generated.
3. The value read from the WDTE register is 9AH/1AH (this differs from the written value (ACH)).
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CHAPTER 12 WATCHDOG TIMER
12.4 Operation of Watchdog Timer
12.4.1 Controlling operation of watchdog timer
1.
When the watchdog timer is used, its operation is specified by the option byte (000C0H).
• Enable counting operation of the watchdog timer by setting bit 4 (WDTON) of the option byte (000C0H) to 1 (the
counter starts operating after a reset release) (for details, see CHAPTER 25).
WDTON
Watchdog Timer Counter
0
Counter operation disabled (counting stopped after reset)
1
Counter operation enabled (counting started after reset)
• Set an overflow time by using bits 3 to 1 (WDCS2 to WDCS0) of the option byte (000C0H) (for details, see 12.4.2
and CHAPTER 25).
• Set a window open period by using bits 6 and 5 (WINDOW1 and WINDOW0) of the option byte (000C0H) (for
details, see 12.4.3 and CHAPTER 25).
2.
After a reset release, the watchdog timer starts counting.
3.
By writing “ACH” to the watchdog timer enable register (WDTE) after the watchdog timer starts counting and before
the overflow time set by the option byte, the watchdog timer is cleared and starts counting again.
4.
After that, write the WDTE register the second time or later after a reset release during the window open period. If
the WDTE register is written during a window close period, an internal reset signal is generated.
5.
If the overflow time expires without “ACH” written to the WDTE register, an internal reset signal is generated.
An internal reset signal is generated in the following cases.
• If a 1-bit manipulation instruction is executed on the WDTE register
• If data other than “ACH” is written to the WDTE register
Cautions 1. When data is written to the watchdog timer enable register (WDTE) for the first time after reset
release, the watchdog timer is cleared in any timing regardless of the window open time, as long
as the register is written before the overflow time, and the watchdog timer starts counting again.
2. If the watchdog timer is cleared by writing “ACH” to the WDTE register, the actual overflow time
may be different from the overflow time set by the option byte by up to 2/fIL seconds.
3. The watchdog timer can be cleared immediately before the count value overflows.
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CHAPTER 12 WATCHDOG TIMER
Cautions 4. The operation of the watchdog timer in the HALT and STOP modes differs as follows depending
on the set value of bit 0 (WDSTBYON) of the option byte (000C0H).
WDSTBYON = 0
WDSTBYON = 1
Watchdog timer operation stops.
In HALT mode
Watchdog timer operation continues.
In STOP mode
If WDSTBYON = 0, the watchdog timer resumes counting after the HALT or STOP mode is
released. At this time, the counter is cleared to 0 and counting starts.
When operating with the X1 oscillation clock after releasing the STOP mode, the CPU starts
operating after the oscillation stabilization time has elapsed.
Therefore, if the period between the STOP mode release and the watchdog timer overflow is short,
an overflow occurs during the oscillation stabilization time, causing a reset.
Consequently, set the overflow time in consideration of the oscillation stabilization time when
operating with the X1 oscillation clock and when the watchdog timer is to be cleared after the
STOP mode release by an interval interrupt.
5. The watchdog timer continues its operation during self-programming of the flash memory and
EEPROMTM emulation. During processing, the interrupt acknowledge time is delayed. Set the
overflow time and window size taking this delay into consideration.
12.4.2 Setting overflow time of watchdog timer
Set the overflow time of the watchdog timer by using bits 3 to 1 (WDCS2 to WDCS0) of the option byte (000C0H).
If an overflow occurs, an internal reset signal is generated. The present count is cleared and the watchdog timer starts
counting again by writing “ACH” to the watchdog timer enable register (WDTE) during the window open period before the
overflow time.
The following overflow times can be set.
Table 12-3. Setting of Overflow Time of Watchdog Timer
WDCS2
WDCS1
WDCS0
Overflow Time of Watchdog Timer
(fIL = 34.5 kHz (MAX.))
7
0
0
0
2 /fIL (3.71 ms)
0
0
1
2 /fIL (7.42 ms)
0
1
0
2 /fIL (14.84 ms)
0
1
1
2 /fIL (29.68 ms)
1
0
0
2 /fIL (118.72 ms)
1
0
1
2 /fIL (474.90 ms)
1
1
0
2 /fIL (949.80 ms)
1
1
1
2 /fIL (3799.19 ms)
8
9
10
12
14
15
17
Caution The watchdog timer continues its operation during self-programming of the flash memory and
EEPROM emulation. During processing, the interrupt acknowledge time is delayed. Set the overflow
time and window size taking this delay into consideration.
Remark
fIL: Internal low-speed oscillation clock frequency
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CHAPTER 12 WATCHDOG TIMER
12.4.3 Setting window open period of watchdog timer
Set the window open period of the watchdog timer by using bits 6 and 5 (WINDOW1, WINDOW0) of the option byte
(000C0H). The outline of the window is as follows.
• If “ACH” is written to the watchdog timer enable register (WDTE) during the window open period, the watchdog timer
is cleared and starts counting again.
• Even if “ACH” is written to the WDTE register during the window close period, an abnormality is detected and an
internal reset signal is generated.
Example: If the window open period is 50%
Counting
starts
Overflow
time
Window close period (50%)
Window close period (50%)
Internal reset signal is generated
if "ACH" is written to WDTE.
Counting starts again when
"ACH" is written to WDTE.
Caution When data is written to the WDTE register for the first time after reset release, the watchdog timer is
cleared in any timing regardless of the window open time, as long as the register is written before the
overflow time, and the watchdog timer starts counting again.
The window open period can be set is as follows.
Table 12-4. Setting Window Open Period of Watchdog Timer
WINDOW1
WINDOW0
Window Open Period of Watchdog Timer
0
0
Setting prohibited
0
1
50%
1
0
75%
1
1
100%
Cautions 1. The watchdog timer continues its operation during self-programming of the flash memory and
EEPROM emulation. During processing, the interrupt acknowledge time is delayed. Set the
overflow time and window size taking this delay into consideration.
2. When bit 0 (WDSTBYON) of the option byte (000C0H) = 0, the window open period is 100%
regardless of the values of the WINDOW1 and WINDOW0 bits.
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CHAPTER 12 WATCHDOG TIMER
10
Remark If the overflow time is set to 2 /fIL, the window close time and open time are as follows.
Setting of Window Open Period
50%
75%
100%
Window close time
0 to 20.08 ms
0 to 10.04 ms
None
Window open time
20.08 to 29.68 ms
10.04 to 29.68 ms
0 to 29.68 ms
<When window open period is 50%>
• Overflow time:
210/fIL (MAX.) = 210/34.5 kHz (MAX.) = 29.68 ms
• Window close time:
0 to 210/fIL (MIN.) × (1 − 0.5) = 0 to 210/25.5 kHz (MIN.) × 0.5 = 0 to 20.08 ms
• Window open time:
210/fIL (MIN.) × (1 − 0.5) to 210/fIL (MAX.) = 210/25.5 kHz (MIN.) × 0.5 to 210/34.5 kHz (MAX.)
= 20.08 to 29.68 ms
12.4.4 Setting watchdog timer interval interrupt
Depending on the setting of bit 7 (WDTINT) of an option byte (000C0H), an interval interrupt (INTWDTI) can be
generated when 75% of the overflow time is reached.
Table 12-5. Setting of Watchdog Timer Interval Interrupt
WDTINT
Use of Watchdog Timer Interval Interrupt
0
Interval interrupt is used.
1
Interval interrupt is generated when 75% of overflow time is reached.
Caution When operating with the X1 oscillation clock after releasing the STOP mode, the CPU starts
operating after the oscillation stabilization time has elapsed.
Therefore, if the period between the STOP mode release and the watchdog timer overflow is short, an
overflow occurs during the oscillation stabilization time, causing a reset.
Consequently, set the overflow time in consideration of the oscillation stabilization time when
operating with the X1 oscillation clock and when the watchdog timer is to be cleared after the STOP
mode release by an interval interrupt.
Remark
The watchdog timer continues counting even after INTWDTI is generated (until ACH is written to the
watchdog timer enable register (WDTE)). If ACH is not written to the WDTE register before the overflow time,
an internal reset signal is generated.
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CHAPTER 13 A/D CONVERTER
CHAPTER 13 A/D CONVERTER
The number of analog input channels of the A/D converter differs, depending on the product.
78K0R/KC3-L
78K0R/KC3-L
78K0R/KC3-L
(40-pin)
(44-pin)
(48-pin)
Analog
10 ch
10 ch
input
(ANI0 to
channels
ANI9)
78K0R/KD3-L
78K0R/KE3-L
78K0R/KF3-L
78K0R/KG3-L
11 ch
11 ch
12 ch
12 ch
16 ch
(ANI0 to
(ANI0 to
(ANI0 to
(ANI0 to
(ANI0 to
(ANI0 to
ANI9)
ANI10)
ANI10)
ANI11)
ANI11)
ANI15)
13.1 Function of A/D Converter
The A/D converter is a 10-bit resolution converter that converts analog input signals into digital values, and is
configured to control analog inputs, including up to sixteen channels of A/D converter analog inputs (ANI0 to ANI15) and a
programmable gain amplifier output (PGAO)
Note
.
The A/D converter has the following function.
• 10-bit resolution A/D conversion
10-bit resolution A/D conversion is carried out repeatedly for one analog input channel selected from ANI0 to ANI15.
Each time an A/D conversion operation ends, an interrupt request (INTAD) is generated.
Figure 13-1. Block Diagram of A/D Converter
AVREF
ANI0/P20
ANI1/P21
ANI2/P22
ANI3/P23
ANI4/P24
ANI5/P25
ANI6/P26
ANI7/P27
ANI8/P150
ANI9/P151
ANI10/P152
ANI11/P153
ANI12/P154
ANI13/P155
ANI14/P156
ANI15/P157
ADCS bit
Sample & hold circuit
A/D voltage comparator
Selector
Array
AVSS
Successive
approximation
register (SAR)
Selector
AVSS
Programmable gain amplifier
output signal (PGAO)
from PGAI pin Note
5
5
ADPC4 ADPC3 ADPC2 ADPC1 ADPC0
INTAD
Controller
ADOASNote ADS3
A/D port configuration
register (ADPC)
A/D conversion result
register (ADCR)
6
ADS2
ADS1
ADCS
ADS0
Analog input channel
specification register (ADS)
ADMD
FR2
FR1
FR0
LV1
LV0
ADCE
A/D converter mode
register (ADM)
Internal bus
Note 78K0R/KC3-L, 78K0R/KD3-L, 78K0R/KE3-L only.
Remark ANI0 to ANI9: 78K0R/KC3-L (40-pin, 44-pin)
ANI0 to ANI10: 78K0R/KC3-L (48-pin) and 78K0R/KD3-L
ANI0 to ANI11: 78K0R/KE3-L, 78K0R/KF3-L
ANI0 to ANI15: 78K0R/KG3-L
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CHAPTER 13 A/D CONVERTER
13.2 Configuration of A/D Converter
The A/D converter includes the following hardware.
(1) ANI0 to ANI15 pins
These are the analog input pins of the sixteen channels of the A/D converter. They input analog signals to be
converted into digital signals. Pins other than the one selected as the analog input pin can be used as I/O port pins.
Remark ANI0 to ANI9: 78K0R/KC3-L (40-pin, 44-pin)
ANI0 to ANI10: 78K0R/KC3-L (48-pin) and 78K0R/KD3-L
ANI0 to ANI11: 78K0R/KE3-L, 78K0R/KF3-L
ANI0 to ANI15: 78K0R/KG3-L
(2) PGAO (78K0R/KC3-L, 78K0R/KD3-L, 78K0R/KE3-L only)
This is the programmable gain amplifier output signal from the PGAI pin. The A/D converter can perform A/D
conversion by selecting the output signal of the programmable gain amplifier as the analog input.
(3) Sample & hold circuit
The sample & hold circuit samples each of the analog input voltages sequentially sent from the input circuit, and
sends them to the A/D voltage comparator. This circuit also holds the sampled analog input voltage during A/D
conversion.
(4) A/D voltage comparator
This A/D voltage comparator compares the voltage generated from the voltage tap of the array with the analog input
voltage. If the analog input voltage is found to be greater than the reference voltage (1/2 AVREF) as a result of the
comparison, the most significant bit (MSB) of the successive approximation register (SAR) is set. If the analog input
voltage is less than the reference voltage (1/2 AVREF), the MSB bit of the SAR is reset.
After that, bit 10 of the SAR register is automatically set, and the next comparison is made. The voltage tap of the
array is selected by the value of bit 11, to which the result has been already set.
Bit 11 = 0: (1/4 AVREF)
Bit 11 = 1: (3/4 AVREF)
The voltage tap of the array and the analog input voltage are compared and bit 10 of the SAR register is manipulated
according to the result of the comparison.
Analog input voltage ≥ Voltage tap of array: Bit 10 = 1
Analog input voltage ≤ Voltage tap of array: Bit 10 = 0
Comparison is continued like this to bit 0 of the SAR register.
(5) Array
The array generates the comparison voltage input from an analog input pin.
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CHAPTER 13 A/D CONVERTER
(6) Successive approximation register (SAR)
The SAR register is a 12-bit register that sets voltage tap data whose values from the array match the voltage values
of the analog input pins, 1 bit at a time starting from the most significant bit (MSB).
If data is set in the SAR register all the way to the least significant bit (LSB) (end of A/D conversion), the contents of
the SAR register (conversion results) are held in the A/D conversion result register (ADCR). When all the specified
A/D conversion operations have ended, an A/D conversion end interrupt request signal (INTAD) is generated.
(7) 10-bit A/D conversion result register (ADCR)
The A/D conversion result is loaded from the successive approximation register to this register each time A/D
conversion is completed, and the ADCR register holds the A/D conversion result in its higher 10 bits (the lower 6 bits
are fixed to 0).
(8) 8-bit A/D conversion result register (ADCRH)
The A/D conversion result is loaded from the successive approximation register to this register each time A/D
conversion is completed, and the ADCRH register stores the higher 8 bits of the A/D conversion result.
(9) Controller
This circuit controls the conversion time of an input analog signal that is to be converted into a digital signal, as well
as starting and stopping of the conversion operation. When A/D conversion has been completed, this controller
generates INTAD.
(10) AVREF pin
This pin inputs the reference voltage of the A/D converter, the programmable gain amplifier, the power supply pins
and A/D converter of the comparator, and the comparator. When all pins of ports 2, 15, and 8 are used as the analog
port pins, make the potential of AVREF be such that 1.8 V ≤ AVREF ≤ VDD. When one or more of the pins of ports 2, 15,
and 8 are used as the digital port pins, make AVREF the same potential as VDD.
The analog signal input to the ANI0 to ANI15 pins is converted into a digital signal, based on the voltage applied
across AVREF and AVSS.
(11) AVSS pin
This is the ground potential pin of the A/D converter. Always use this pin at the same potential as that of the VSS pin
even when the A/D converter is not used.
Remark ANI0 to ANI9: 78K0R/KC3-L (40-pin, 44-pin)
ANI0 to ANI10: 78K0R/KC3-L (48-pin) and 78K0R/KD3-L
ANI0 to ANI11: 78K0R/KE3-L, 78K0R/KF3-L
ANI0 to ANI15: 78K0R/KG3-L
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CHAPTER 13 A/D CONVERTER
13.3 Registers Used in A/D Converter
The A/D converter uses the following seven registers.
• Peripheral enable register 0 (PER0)
• A/D converter mode register (ADM)
• A/D port configuration register (ADPC)
• Analog input channel specification register (ADS)
• Port mode registers 2, 15, 8 Note (PM2, PM15, PM8 Note)
• 10-bit A/D conversion result register (ADCR)
• 8-bit A/D conversion result register (ADCRH)
Note Port mode register 8 is set only in the 78K0R/KC3-L, 78K0R/KD3-L, and 78K0R/KE3-L.
(1) Peripheral enable register 0 (PER0)
This register is used to enable or disable supplying the clock to the peripheral hardware. Clock supply to a hardware
macro that is not used is stopped in order to reduce the power consumption and noise.
When the A/D converter is used, be sure to set bit 5 (ADCEN) of this register to 1.
The PER0 register can be set by a 1-bit or 8-bit memory manipulation instruction.
Reset signal generation clears this register to 00H.
Figure 13-2. Format of Peripheral Enable Register 0 (PER0)
Address: F00F0H
Symbol
PER0
After reset: 00H
<7>
RTCEN
6
Note 1
0
R/W
<5>
ADCEN
ADCEN
0
<4>
IICAEN
<3>
Note 2
SAU1EN
<2>
Note 3
SAU0EN
<1>
TAU1EN
<0>
Note 3
TAU0EN
Note 3
Control of A/D converter input clock supply
Stops input clock supply.
• SFR used by the A/D converter cannot be written.
• The A/D converter is in the reset status.
1
Enables input clock supply.
• SFR used by the A/D converter can be read/written.
Notes 1. That is not provided in 40-pin product of the 78K0R/KC3-L.
2. That is not provided in 40-pin and 44-pin products of the 78K0R/KC3-L.
3. 78K0R/KF3-L and 78K0R/KG3-L only.
Cautions 1. When setting the A/D converter, be sure to set the ADCEN bit to 1 first. If ADCEN = 0, writing
to a control register of the A/D converter is ignored, and, even if the register is read, only the
default value is read (except for port mode registers 2, 15, and 8 (PM2, PM15, and PM8)).
2. Be sure to clear the following bits to 0.
48-pin product of the 78K0R/KC3-L, 78K0R/KD3-L, 78K0R/KE3-L: bits 0, 1, 3, 6
44-pin product of the 78K0R/KC3-L:
bits 0, 1, 3, 4, 6
40-pin product of the 78K0R/KC3-L:
bits 0, 1, 3, 4, 6, 7
78K0R/KF3-L, 78K0R/KG3-L:
bit 6
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CHAPTER 13 A/D CONVERTER
(2) A/D converter mode register (ADM)
This register sets the conversion time for analog input to be A/D converted, and starts/stops conversion.
The ADM register can be set by a 1-bit or 8-bit memory manipulation instruction.
Reset signal generation clears this register to 00H.
Figure 13-3. Format of A/D Converter Mode Register (ADM)
Address: FFF30H
Symbol
ADM
After reset: 00H
R/W
<7>
6
5
4
3
2
1
<0>
ADCS
ADMD
FR2Note 1
FR1Note 1
FR0Note 1
LV1Note 1
LV0Note 1
ADCE
ADCS
A/D conversion operation control
0
Stops conversion operation
1
Enables conversion operation
ADMD
A/D conversion operation mode specification
0
Select mode
1
Scan mode
A/D voltage comparator operation controlNote 2
ADCE
Notes 1.
0
Stops A/D voltage comparator operation
1
Enables A/D voltage comparator operation
For details of the FR2 to FR0, LV1, LV0 bits, and A/D conversion, see Table 13-2 A/D Conversion Time
Selection.
2.
The operation of the A/D voltage comparator is controlled by the ADCS and ADCE bits, and it takes 1 μs
from operation start to operation stabilization. Therefore, when the ADCS bit is set to 1 after 1 μs or more
has elapsed from the time ADCE bit is set to 1, the conversion result at that time has priority over the first
conversion result. Otherwise, ignore data of the first conversion.
Table 13-1. Settings of ADCS and ADCE bits
ADCS
ADCE
0
0
Stop status (DC power consumption path does not exist)
0
1
Conversion waiting mode (only A/D voltage comparator consumes power))
1
0
Setting prohibited
1
1
Conversion mode (A/D voltage comparator: enables operation)
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CHAPTER 13 A/D CONVERTER
Figure 13-4. Timing Chart When A/D Voltage Comparator Is Used
A/D voltage comparator: enables operation
ADCE
A/D voltage
comparator
Conversion
operation
Conversion
waiting
Conversion
operation
Conversion
stopped
ADCS
Note
Note To stabilize the internal circuit, the time from the rising of the ADCE bit to the falling of the ADCS bit must be 1
μs or longer.
Caution A/D conversion must be stopped before rewriting bits the FR0 to FR2, LV1, and LV0 bits to values
other than the identical data.
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CHAPTER 13 A/D CONVERTER
<R>
Table 13-2. A/D Conversion Time Selection (1/3)
(1) 4.0 V ≤ AVREF ≤ 5.5 V
A/D Converter Mode Register (ADM)
FR2
FR1
FR0
LV1
Mode
Conversion
Conversion Time Selection
fCLK = 2
LV0
fCLK = 5 MHz
fCLK = 10 MHz
fCLK = 20 MHz
Clock (fAD)
MHz
0
0
0
0
0
Normal
342/fCLK
Setting
Setting prohibited 34.2 μs
17.1 μs
fCLK/20
prohibited
34.4 μs
17.2 μs
8.6 μs
fCLK/10
27.6 μs
13.8 μs
6.9 μs
fCLK/8
fCLK/6
0
0
1
172/fCLK
0
1
0
138/fCLK
0
1
1
104/fCLK
52.0 μs
20.8 μs
10.4 μs
5.2 μs
1
0
0
70/fCLK
35.0 μs
14.0 μs
7.0 μs
Setting prohibited fCLK/4
1
0
1
53/fCLK
26.5 μs
10.6 μs
5.3 μs
fCLK/3
1
1
0
36/fCLK
18.0 μs
7.2 μs
Setting prohibited
fCLK/2
1
1
1
19/fCLK
9.5 μs
Setting prohibited
×
×
×
0
1
Low-
fCLK
−
Setting prohibited
voltage
0
0
0
1
0
High
speed 1
322/fCLK
Setting
64.4 μs
32.2 μs
16.1 μs
fCLK/20
162/fCLK
prohibited
32.4 μs
16.2 μs
8.1 μs
fCLK/10
0
0
1
0
1
0
130/fCLK
65.0 μs
26.0 μs
13.0 μs
6.5 μs
fCLK/8
0
1
1
98/fCLK
49.0 μs
19.6 μs
9.8 μs
4.9 μs
fCLK/6
1
0
0
66/fCLK
33.0 μs
13.2 μs
6.6 μs
3.3 μs
fCLK/4
1
0
1
50/fCLK
25.0 μs
10.0 μs
5.0 μs
2.5 μs
fCLK/3
1
1
0
34/fCLK
17.0 μs
6.8 μs
3.4 μs
Setting prohibited fCLK/2
1
1
1
18/fCLK
9.0 μs
3.6 μs
Setting prohibited
0
0
0
342/fCLK
Setting
Setting prohibited 34.2 μs
17.1 μs
fCLK/20
172/fCLK
prohibited
34.4 μs
17.2 μs
8.6 μs
fCLK/10
27.6 μs
13.8 μs
6.9 μs
fCLK/8
1
1
High
speed 2
fCLK
0
0
1
0
1
0
138/fCLK
0
1
1
104/fCLK
52.0 μs
20.8 μs
10.4 μs
5.2 μs
fCLK/6
1
0
0
70/fCLK
35.0 μs
14.0 μs
7.0 μs
3.5 μs
fCLK/4
1
0
1
53/fCLK
26.5 μs
10.6 μs
5.3 μs
Setting prohibited fCLK/3
1
1
0
36/fCLK
18.0 μs
7.2 μs
3.6 μs
fCLK/2
1
1
1
19/fCLK
9.5 μs
3.8 μs
Setting prohibited
fCLK
Cautions 1. When rewriting the FR2 to FR0, LV1, and LV0 bits to other than the same data, stop A/D conversion
once (ADCS = 0) beforehand.
2. The above conversion time does not include clock frequency errors. Select conversion time, taking
clock frequency errors into consideration.
Remark
fCLK: CPU/peripheral hardware clock frequency
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CHAPTER 13 A/D CONVERTER
<R>
Table 13-2. A/D Conversion Time Selection (2/3)
(2) 2.7 V ≤ AVREF ≤ 5.5 V
A/D Converter Mode Register (ADM)
Conversion Time Selection
Mode
FR2
FR1
FR0
LV1
LV0
fCLK = 2
MHz
0
0
0
0
0
0
0
1
172/fCLK
0
1
0
138/fCLK
0
1
1
104/fCLK
1
0
0
1
0
1
1
Normal
342/fCLK
fCLK = 5 MHz
fCLK = 10 MHz
Setting
Setting prohibited 34.2 μs
prohibited
34.4 μs
17.2 μs
fCLK = 20 MHz
Conversion
Clock (fAD)
17.1 μs
fCLK/20
8.6 μs
fCLK/10
27.6 μs
13.8 μs
Setting prohibited fCLK/8
52.0 μs
20.8 μs
10.4 μs
fCLK/6
70/fCLK
35.0 μs
14.0 μs
Setting prohibited
fCLK/4
1
53/fCLK
26.5 μs
10.6 μs
fCLK/3
1
0
36/fCLK
18.0 μs
Setting prohibited
fCLK/2
1
1
19/fCLK
9.5 μs
×
×
×
0
1
×
×
×
1
0
0
0
0
1
1
0
0
1
0
1
0
138/fCLK
0
1
1
104/fCLK
1
0
0
1
0
1
1
fCLK
Setting prohibited
−
High
speed 1
Setting prohibited
−
High
speed 2
342/fCLK
Lowvoltage
172/fCLK
Setting
Setting prohibited 34.2 μs
prohibited
34.4 μs
17.2 μs
17.1 μs
fCLK/20
8.6 μs
fCLK/10
27.6 μs
13.8 μs
6.9 μs
fCLK/8
52.0 μs
20.8 μs
10.4 μs
5.2 μs
fCLK/6
70/fCLK
35.0 μs
14.0 μs
7.0 μs
3.5 μs
fCLK/4
1
53/fCLK
26.5 μs
10.6 μs
5.3 μs
Setting prohibited fCLK/3
1
0
36/fCLK
18.0 μs
7.2 μs
3.6 μs
fCLK/2
1
1
19/fCLK
9.5 μs
3.8 μs
Setting prohibited
fCLK
Cautions 1. When rewriting the FR2 to FR0, LV1, and LV0 bits to other than the same data, stop A/D conversion
once (ADCS = 0) beforehand.
2. The above conversion time does not include clock frequency errors. Select conversion time, taking
clock frequency errors into consideration.
Remark
fCLK: CPU/peripheral hardware clock frequency
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CHAPTER 13 A/D CONVERTER
<R>
Table 13-2. A/D Conversion Time Selection (3/3)
(3) 1.8 V ≤ AVREF ≤ 4.0 V
A/D Converter Mode Register (ADM)
FR2
FR1
FR0
LV1
LV0
×
×
×
0
0
0
0
0
0
1
Conversion Time Selection
Mode
fCLK = 2
MHz
Normal
Low-
fCLK = 5 MHz
fCLK = 10 MHz
fCLK = 20 MHz
Conversion
Clock (fAD)
48.2 μs
24.1 μs
fCLK/20
Setting
prohibited
fCLK/10
Setting prohibited
482/fCLK
voltage
Setting
Setting
prohibited prohibited
0
0
1
242/fCLK
48.4 μs
24.2 μs
0
1
0
194/fCLK
38.8 μs
0
1
1
146/fCLK
29.2 μs
Setting
prohibited
1
0
0
98/fCLK
49.0 μs
1
0
1
74/fCLK
37.0 μs
1
1
0
50/fCLK
25.0 μs
fCLK/2
1
1
1
26/fCLK
Setting
prohibited
fCLK
×
×
×
1
0
High
speed 1
Setting prohibited
−
×
×
×
1
1
High
speed 2
Setting prohibited
−
Other than above
Setting
prohibited
fCLK/8
fCLK/6
fCLK/4
fCLK/3
Setting prohibited
Cautions 1. When rewriting the FR2 to FR0, LV1, and LV0 bits to other than the same data, stop A/D conversion
once (ADCS = 0) beforehand.
2. The above conversion time does not include clock frequency errors. Select conversion time, taking
clock frequency errors into consideration.
Remark
fCLK: CPU/peripheral hardware clock frequency
Figure 13-5. A/D Converter Sampling and A/D Conversion Timing
ADCS ← 1 or ADS rewrite
ADCS
Sampling
timing
INTAD
SAR
clear
Sampling
Successive conversion Transfer SAR
to ADCR, clear
INTAD
generation
Conversion time
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CHAPTER 13 A/D CONVERTER
(3) 10-bit A/D conversion result register (ADCR)
This register is a 16-bit register that stores the A/D conversion result in the select mode. The lower 6 bits are fixed to
0. Each time A/D conversion ends, the conversion result is loaded from the successive approximation register (SAR).
The higher 8 bits of the conversion result are stored in FFF1FH and the lower 2 bits are stored in the higher 2 bits of
FFF1EH.
The ADCR register can be read by a 16-bit memory manipulation instruction.
Reset signal generation clears this register to 0000H.
Figure 13-6. Format of 10-bit A/D Conversion Result Register (ADCR)
Address: FFF1FH, FFF1EH
After reset: 0000H
R
FFF1FH
Symbol
FFF1EH
ADCR
0
0
0
0
0
0
Caution When writing to the A/D converter mode register (ADM), analog input channel specification register
(ADS), and A/D port configuration register (ADPC), the contents of the ADCR register may become
undefined. Read the conversion result following conversion completion before writing to the ADM,
ADS, and ADPC registers. Using timing other than the above may cause an incorrect conversion
result to be read.
(4) 8-bit A/D conversion result register (ADCRH)
This register is an 8-bit register that stores the A/D conversion result. The higher 8 bits of 10-bit resolution are stored.
The ADCRH register can be read by an 8-bit memory manipulation instruction.
Reset signal generation clears this register to 00H.
Figure 13-7. Format of 8-bit A/D Conversion Result Register (ADCRH)
Address: FFF1FH
Symbol
7
After reset: 00H
6
5
R
4
3
2
1
0
ADCRH
Caution When writing to the A/D converter mode register (ADM), analog input channel specification register
(ADS), and A/D port configuration register (ADPC), the contents of the ADCRH register may become
undefined. Read the conversion result following conversion completion before writing to the ADM,
ADS, and ADPC registers. Using timing other than the above may cause an incorrect conversion
result to be read.
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CHAPTER 13 A/D CONVERTER
(5) Analog input channel specification register (ADS)
This register specifies the input channel of the analog voltage to be A/D converted.
The ADS register can be set by a 1-bit or 8-bit memory manipulation instruction.
Reset signal generation clears this register to 00H.
Figure 13-8. Format of Analog Input Channel Specification Register (ADS) (1/2)
Address: FFF31H
Symbol
ADS
0
KC3-L (40-pin)
KC3-L (44-pin)
KC3-L (48-pin)
KD3-L
KE3-L
KF3-L
KG3-L
Note 2 Note 2 Note 2 Note 2 Note 2
Note 3 Note 3 Note 3 Note 3
Note 3
After reset: 00H
7
Note 2 Note 2 Note 2
R/W
6
ADOAS
Note 1
5
4
3
2
1
0
0
0
ADS3
ADS2
ADS1
ADS0
{ Select mode (ADMD = 0)
ADOAS
ADS3
ADS2
ADS1
ADS0
Note 1
Analog input
Input source
channel
0
0
0
0
0
ANI0
P20/ANI0 pin
0
0
0
0
1
ANI1
P21/ANI1 pin
0
0
0
1
0
ANI2
P22/ANI2 pin
0
0
0
1
1
ANI3
P23/ANI3 pin
0
0
1
0
0
ANI4
P24/ANI4 pin
0
0
1
0
1
ANI5
P25/ANI5 pin
0
0
1
1
0
ANI6
P26/ANI6 pin
0
0
1
1
1
ANI7
P27/ANI7 pin
0
1
0
0
0
ANI8
P150/ANI8 pin
0
1
0
0
1
ANI9
P151/ANI9 pin
0
1
0
1
0
ANI10
P152/ANI10 pin
0
1
0
1
1
ANI11
P153/ANI11 pin
0
1
1
0
0
ANI12
P154/ANI12 pin
0
1
1
0
1
ANI13
P155/ANI13 pin
0
1
1
1
0
ANI14
P156/ANI14 pin
0
1
1
1
1
ANI15
P157/ANI15 pin
1
×
×
×
×
PGAO
Programmable gain
amplifier output signal
Other than the above
Notes 1.
Setting prohibited
78K0R/KC3-L, 78K0R/KD3-L, 78K0R/KE3-L only.
2.
Setting permitted
3.
Setting prohibited
(Cautions and Remarks are listed on the next page.)
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CHAPTER 13 A/D CONVERTER
Cautions 1. Be sure to clear the following bits to 0.
78K0R/KC3-L, 78K0R/KD3-L, 78K0R/KE3-L: bits 4, 5, 7
78K0R/KF3-L, 78K0R/KG3-L:
bits 4 to 7
2 Set a channel to be used for A/D conversion in the input mode by using port mode registers 2, 15,
and 8 (PM2, PM15, PM8).
3. Do not set the pin that is set by the A/D port configuration register (ADPC) as digital I/O by the
ADS register.
4. Select the output signal (PGAO) of the programmable gain amplifier from the PGAI pin as the
analog input after setting the operation of the programmable gain amplifier (refer to 13.4.1 Basic
operations of A/D converter).
Remarks 1.
2.
×: don’t care
P20/ANI0 to P27/ANI7, P150/ANI8, P151/ANI9:
78K0R/KC3-L (40-pin, 44-pin)
P20/ANI0 to P27/ANI7, P150/ANI8 to P152/ANI10: 78K0R/KC3-L (48-pin) and 78K0R/KD3-L
P20/ANI0 to P27/ANI7, P150/ANI8 to P153/ANI11: 78K0R/KE3-L, 78K0R/KF3-L
P20/ANI0 to P27/ANI7, P150/ANI8 to P157/ANI15: 78K0R/KG3-L
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Figure 13-8. Format of Analog Input Channel Specification Register (ADS) (2/2)
Address: FFF31H
Symbol
After reset: 00H
7
ADS
0
KC3-L (40-pin)
KC3-L (44-pin)
KC3-L (48-pin)
KD3-L
KE3-L
KF3-L, KG3-L
Note 2
Note 2
Note 2 Note 2
Note 3
Note 3
Note 2
R/W
6
ADOAS
Note 1
5
4
3
2
1
0
0
0
ADS3
ADS2
ADS1
ADS0
{ Scan mode (ADMD = 1)
ADOAS
ADS3
ADS2
ADS1
Analog input channel
Scan 0
Scan 1
Scan 2
Scan 3
0
0
0
0
0
ANI0
ANI1
ANI2
ANI3
0
0
0
0
1
ANI1
ANI2
ANI3
ANI4
0
0
0
1
0
ANI2
ANI3
ANI4
ANI5
0
0
0
1
1
ANI3
ANI4
ANI5
ANI6
0
0
1
0
0
ANI4
ANI5
ANI6
ANI7
0
0
1
0
1
ANI5
ANI6
ANI7
ANI8
0
0
1
1
0
ANI6
ANI7
ANI8
ANI9
0
0
1
1
1
ANI7
ANI8
ANI9
ANI10
1
0
0
0
0
PGAO
ANI0
ANI1
ANI2
1
0
0
0
1
PGAO
ANI1
ANI2
ANI3
1
0
0
1
0
PGAO
ANI2
ANI3
ANI4
1
0
0
1
1
PGAO
ANI3
ANI4
ANI5
1
0
1
0
0
PGAO
ANI4
ANI5
ANI6
1
0
1
0
1
PGAO
ANI5
ANI6
ANI7
1
0
1
1
0
PGAO
ANI6
ANI7
ANI8
1
0
1
1
1
PGAO
ANI7
ANI8
ANI9
Other than the above
Notes 1.
2.
3.
ADS0
Note 1
Setting prohibited
78K0R/KC3-L, 78K0R/KD3-L, 78K0R/KE3-L only.
Setting permitted
Setting prohibited
Cautions 1. Be sure to clear the following bits to 0.
78K0R/KC3-L, 78K0R/KD3-L, 78K0R/KE3-L: bits 4, 5, 7
78K0R/KF3-L, 78K0R/KG3-L:
bits 4 to 7
2 Set a channel to be used for A/D conversion in the input mode by using port mode registers 2, 15,
and 8 (PM2, PM15, PM8).
3. Do not set the pin that is set by the A/D port configuration register (ADPC) as digital I/O by the
ADS register.
4. Select the output signal (PGAO) of the programmable gain amplifier from the PGAI pin as the
analog input after setting the operation of the programmable gain amplifier (refer to 13.4.1 Basic
operations of A/D converter).
Remarks 1.
2.
×: don’t care
P20/ANI0 to P27/ANI7, P150/ANI8, P151/ANI9:
P20/ANI0 to P27/ANI7, P150/ANI8 to P152/ANI10:
P20/ANI0 to P27/ANI7, P150/ANI8 to P153/ANI11:
P20/ANI0 to P27/ANI7, P150/ANI8 to P157/ANI15:
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78K0R/KC3-L (40-pin, 44-pin)
78K0R/KC3-L (48-pin) and 78K0R/KD3-L
78K0R/KE3-L, 78K0R/KF3-L
78K0R/KG3-L
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CHAPTER 13 A/D CONVERTER
(6) A/D port configuration register (ADPC)
This register switches the ANI0/P20 to ANI7/P27 and ANI8/P150 to ANI15/P157 pins to analog input of A/D converter
or digital I/O of port.
The ADPC register can be set by an 8-bit memory manipulation instruction.
Reset signal generation sets this register to 10H.
Figure 13-9. Format of A/D Port Configuration Register (ADPC)
Address: F0017H
After reset: 10H
R/W
Symbol
7
6
5
4
3
2
1
0
ADPC
0
0
0
ADPC4
ADPC3
ADPC2
ADPC1
ADPC0
ADP ADP ADP ADP ADP
C4 C3 C2 C1 C0
Analog Input (A)/digital I/O (D) switching
Port 15
Port 2
ANI15 ANI14 ANI13 ANI12 ANI11 ANI10 ANI9 ANI8 ANI7 ANI6 ANI5 ANI4 ANI3 ANI2 ANI1 ANI0
/P157 /P156 /P155 /P154 /P153 /P152 /P151 /P150 /P27
0
0
0
0
0
A
A
A
A
A
A
A
A
A
/P26
/P25
/P24
/P23
/P22
/P21
/P20
A
A
A
A
A
A
A
0
0
0
0
1
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
D
0
0
0
1
0
A
A
A
A
A
A
A
A
A
A
A
A
A
A
D
D
0
0
0
1
1
A
A
A
A
A
A
A
A
A
A
A
A
A
D
D
D
0
0
1
0
0
A
A
A
A
A
A
A
A
A
A
A
A
D
D
D
D
0
0
1
0
1
A
A
A
A
A
A
A
A
A
A
A
D
D
D
D
D
0
0
1
1
0
A
A
A
A
A
A
A
A
A
A
D
D
D
D
D
D
0
0
1
1
1
A
A
A
A
A
A
A
A
A
D
D
D
D
D
D
D
0
1
0
0
0
A
A
A
A
A
A
A
A
D
D
D
D
D
D
D
D
0
1
0
0
1
A
A
A
A
A
A
A
D
D
D
D
D
D
D
D
D
0
1
0
1
0
A
A
A
A
A
A
D
D
D
D
D
D
D
D
D
D
0
1
0
1
1
A
A
A
A
A
D
D
D
D
D
D
D
D
D
D
D
0
1
1
0
0
A
A
A
A
D
D
D
D
D
D
D
D
D
D
D
D
0
1
1
0
1
A
A
A
D
D
D
D
D
D
D
D
D
D
D
D
D
0
1
1
1
0
A
A
D
D
D
D
D
D
D
D
D
D
D
D
D
D
0
1
1
1
1
A
D
D
D
D
D
D
D
D
D
D
D
D
D
D
D
1
0
0
0
0
D
D
D
D
D
D
D
D
D
D
D
D
D
D
D
D
Other than above
Setting prohibited
Cautions 1. Set a channel to be used for A/D conversion in the input mode by using port mode register 2 and
15 (PM2, PM15).
2. Do not set the pin that is set by the ADPC register as digital I/O by the analog input channel
specification register (ADS).
3. Be sure to first set the ADCEN bit of peripheral enable register 0 (PER0) to 1 when setting up the
ADPC register. If ADCEN = 0, writing to the ADPC register is ignored and specified values are
returned to the initial values.
Remark P20/ANI0 to P27/ANI7, P150/ANI8, P151/ANI9:
78K0R/KC3-L (40-pin, 44-pin)
P20/ANI0 to P27/ANI7, P150/ANI8 to P152/ANI10: 78K0R/KC3-L (48-pin) and 78K0R/KD3-L
P20/ANI0 to P27/ANI7, P150/ANI8 to P153/ANI11: 78K0R/KE3-L, 78K0R/KF3-L
P20/ANI0 to P27/ANI7, P150/ANI8 to P157/ANI15: 78K0R/KG3-L
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CHAPTER 13 A/D CONVERTER
(7) Port input mode register 8 (PIM8) (78K0R/KC3-L, 78K0R/KD3-L, 78K0R/KE3-L only)
This register enables or disables the digital input of port 8 in 1-bit units.
Disable the digital input (used as analog input) to use the PGAI pin as the analog input. Enable the digital input to use
the port function, or the external interrupt and timer Hi-Z control functions, because the digital input is disabled (used
as analog input) in the initial state.
The PIM8 register can be set by a 1-bit or 8-bit memory manipulation instruction.
Reset signal generation clears this register to 00H.
Figure 13-10. Format of Port Input Mode Register 8 (PIM8)
Address: F0048H
Symbol
PIM8
7
6
0
0
PIM8n
Note
After reset: 00H
R/W
5
0
4
0
3
PIM83
2
PIM82
Note
1
0
PIM81
PIM80
Selection of enabling or disabling P8n pin digital input (n = 0 to 3)
0
Disables digital input (used as analog input)
1
Enables digital input
PIM82 bit is not provided in the 78K0R/KC3-L (40-pin).
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CHAPTER 13 A/D CONVERTER
(8) Port mode registers 2, 15, and 8
Note
(PM2, PM15, PM8 Note)
When using the ANI0/P20 to ANI7/P27, ANI8/P150 to ANI15/P157, and PGAI/P80 pins for analog input port, set the
PM20 to PM27, PM150 to PM157, and PM80 bits to 1. The output latches of P20 to P27, P150 to P157, and P80 at
this time may be 0 or 1.
If the PM20 to PM27, PM150 to PM157, and PM80 bits are set to 0, they cannot be used as analog input port pins.
The PM2, PM15, and PM8 register can be set by a 1-bit or 8-bit memory manipulation instruction.
Reset signal generation sets these registers to FFH.
Note
Port mode register 8 is set only in the 78K0R/KC3-L, 78K0R/KD3-L, and 78K0R/KE3-L.
Caution If a pin is set as an analog input port, not the pin level but “0” is always read.
Remark P20/ANI0 to P27/ANI7, P150/ANI8, P151/ANI9:
78K0R/KC3-L (40-pin, 44-pin)
P20/ANI0 to P27/ANI7, P150/ANI8 to P152/ANI10: 78K0R/KC3-L (48-pin) and 78K0R/KD3-L
P20/ANI0 to P27/ANI7, P150/ANI8 to P153/ANI11: 78K0R/KE3-L, 78K0R/KF3-L
P20/ANI0 to P27/ANI7, P150/ANI8 to P157/ANI15: 78K0R/KG3-L
Figure 13-11. Formats of Port Mode Registers 2, 15, and 8 (PM2, PM15, PM8) (78K0R/KE3-L)
Address: FFF22H
After reset: FFH
R/W
Symbol
7
6
5
4
3
2
1
0
PM2
PM27
PM26
PM25
PM24
PM23
PM22
PM21
PM20
Address: FFF28H
After reset: FFH
R/W
Symbol
7
6
5
4
3
2
1
0
PM8
1
1
1
1
PM83
PM82
PM81
PM80
Address: FFF2FH
After reset: FFH
R/W
Symbol
7
6
5
4
3
2
1
0
PM15
1
1
1
1
PM153
PM152
PM151
PM150
PMmn
Pmn pin I/O mode selection (mn = 20 to 27, 150 to 153, 80 to 83)
0
Output mode (output buffer on)
1
Input mode (output buffer off)
Remark
The figure shown above presents the format of port mode registers 2, 8 and 15 of the 78K0R/KE3-L
product. See below for the format of the port mode registers of other products.
78K0R/KC3-L, 78K0R/KD3-L, 78K0R/KE3-L: 5.3 (1) Port mode registers (PMxx).
78K0R/KF3-L, 78K0R/KG3-L:
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CHAPTER 13 A/D CONVERTER
The ANI0/P20 to ANI7/P27, ANI8/P150 to ANI15/P157, and PGAI/P80 pins are as shown below depending on the
settings of the A/D port configuration register (ADPC), analog input channel specification register (ADS), PM2, PM15,
and PM8 registers.
Table 13-3. Setting Functions of ANI0/P20 to ANI7/P27, ANI8/P150 to ANI15/P157, and PGAI/P80 Pins
ADPC
PM2, PM15, and PM8
ADS
ANI0/P20 to ANI7/P27, ANI8/P150
to ANI15/P157, and PGAI/P80 Pins
Digital I/O selection
Analog input selection
Input mode
−
Digital input
Output mode
−
Digital output
Input mode
Output mode
Selects ANI.
Analog input (to be converted)
Does not select ANI.
Analog input (not to be converted)
Selects ANI.
Setting prohibited
Does not select ANI.
Remark P20/ANI0 to P27/ANI7, P150/ANI8, P151/ANI9:
78K0R/KC3-L (40-pin, 44-pin)
P20/ANI0 to P27/ANI7, P150/ANI8 to P152/ANI10: 78K0R/KC3-L (48-pin) and 78K0R/KD3-L
P20/ANI0 to P27/ANI7, P150/ANI8 to P153/ANI11: 78K0R/KE3-L, 78K0R/KF3-L
P20/ANI0 to P27/ANI7, P150/ANI8 to P157/ANI15: 78K0R/KG3-L
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CHAPTER 13 A/D CONVERTER
13.4 A/D Converter Operations
13.4.1 Basic operations of A/D converter
<1> Set bit 5 (ADCEN) of peripheral enable register 0 (PER0) to 1 to start the supply of the input clock to the A/D
converter.
<2> Set the A/D conversion time by using bits 5 to 1 (FR2 to FR0, LV1, and LV0) of the A/D converter mode register
(ADM), and set the operation mode by using bit 6 (ADMD) of the ADM register.
<3> Set bit 0 (ADCE) of the ADM register to 1 to start the operation of the A/D voltage comparator.
<4> Set the channels for A/D conversion to analog input by using the A/D port configuration register (ADPC) and set
to input mode by using the port mode registers (PM2, PM15, and PM8).
<5> Set the programmable gain amplifier operation to set the programmable gain amplifier output (PGAI pin) for the
analog input channel (refer to 10.4.1 Starting comparator and programmable gain amplifier operation).
<6> Select one channel for A/D conversion using the analog input channel specification register (ADS).
<7> Start the conversion operation by setting bit 7 (ADCS) of the ADM register to 1.
(<8> to <14> are operations performed by hardware.)
<8> The voltage input to the selected analog input channel is sampled by the sample & hold circuit.
<9> When sampling has been done for a certain time, the sample & hold circuit is placed in the hold state and the
sampled voltage is held until the A/D conversion operation has ended.
<10> Bit 9 of the successive approximation register (SAR) is set. The series resistor string voltage tap is set to (1/2)
AVREF by the tap selector.
<11> The voltage difference between the series resistor string voltage tap and sampled voltage is compared by the
voltage comparator. If the analog input is greater than (1/2) AVREF, the MSB bit of the SAR register remains set
to 1. If the analog input is smaller than (1/2) AVREF, the MSB bit is reset to 0.
<12> Next, bit 8 of the SAR register is automatically set to 1, and the operation proceeds to the next comparison. The
series resistor string voltage tap is selected according to the preset value of bit 9, as described below.
• Bit 9 = 1: (3/4) AVREF
• Bit 9 = 0: (1/4) AVREF
The voltage tap and sampled voltage are compared and bit 8 of the SAR register is manipulated as follows.
• Sampled voltage ≥ Voltage tap: Bit 8 = 1
• Sampled voltage < Voltage tap: Bit 8 = 0
<13> Comparison is continued in this way up to bit 0 of the SAR register.
<14> Upon completion of the comparison of 10 bits, an effective digital result value remains in the SAR register, and
the result value is transferred to the A/D conversion result register (ADCR, ADCRH) and then latched.
At the same time, the A/D conversion end interrupt request (INTAD) can also be generated.
<15> Repeat steps <8> to <14>, until the ADCS bit is cleared to 0.
To stop the A/D converter, clear the ADCS bit to 0.
To restart A/D conversion from the status of ADCE = 1, start from <7>. To start A/D conversion again when
ADCE = 0, set the ADCE bit to 1, wait for 1 μs or longer, and start <7>. To change a channel of A/D conversion,
start from <6>.
Caution Make sure the period of <3> to <7> is 1 μs or more.
Remark
Two types of the A/D conversion result registers are available.
• ADCR register (16 bits):
Store 10-bit A/D conversion value
• ADCRH register (8 bits):
Store 8-bit A/D conversion value
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CHAPTER 13 A/D CONVERTER
<R>
Figure 13-12. Basic Operation of A/D Converter
ADCS ← 1 or ADS rewrite
Conversion time
Sampling time
A/D converter
operation
SAR
SAR clear
Sampling
A/D conversion
Undefined
ADCR
Conversion
result
Conversion
result
INTAD
A/D conversion operations are performed continuously until bit 7 (ADCS) of the A/D converter mode register (ADM) is
reset (0) by software.
If a write operation is performed to the analog input channel specification register (ADS) during an A/D conversion
operation, the conversion operation is initialized, and if the ADCS bit is set (1), conversion starts again from the beginning.
Reset signal generation clears the A/D conversion result register (ADCR, ADCRH) to 0000H or 00H.
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CHAPTER 13 A/D CONVERTER
13.4.2 Input voltage and conversion results
The relationship between the analog input voltage input to the analog input pins (ANI0 to ANI15, PGAI) and the
theoretical A/D conversion result (stored in the 10-bit A/D conversion result register (ADCR)) is shown by the following
expression.
SAR = INT (
VAIN
AVREF
× 1024 + 0.5)
ADCR = SAR × 64
or
(
ADCR
64
− 0.5) ×
where, INT( ):
AVREF
1024
≤ VAIN < (
ADCR
64
+ 0.5) ×
AVREF
1024
Function which returns integer part of value in parentheses
VAIN:
Analog input voltage
AVREF:
AVREF pin voltage
ADCR: A/D conversion result register (ADCR) value
SAR:
Successive approximation register
Figure 13-13 shows the relationship between the analog input voltage and the A/D conversion result.
Figure 13-13. Relationship Between Analog Input Voltage and A/D Conversion Result
SAR
ADCR
1023
FFC0H
1022
FF80H
1021
FF40H
3
00C0H
2
0080H
1
0040H
A/D conversion result
0
0000H
1
1
3
2
5
3
2048 1024 2048 1024 2048 1024
2043 1022 2045 1023 2047 1
2048 1024 2048 1024 2048
Input voltage/AVREF
Remark ANI0 to ANI9: 78K0R/KC3-L (40-pin, 44-pin)
ANI0 to ANI10: 78K0R/KC3-L (48-pin) and 78K0R/KD3-L
ANI0 to ANI11: 78K0R/KE3-L, 78K0R/KF3-L
ANI0 to ANI15: 78K0R/KG3-L
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CHAPTER 13 A/D CONVERTER
13.4.3 A/D converter operation modes
The select mode and scan mode are provided as the A/D converter operation modes.
(1) Select mode
One analog input specified by the analog input channel specification register (ADS), while the ADMD bit of the A/D
converter mode register (ADM) is 0, is A/D converted.
When A/D conversion is complete, the conversion result is stored in the A/D conversion result register (ADCR) and
the A/D conversion end interrupt request signal (INTAD) is generated.
After A/D conversion has been completed, A/D conversion is repeated successively, unless the ADCS bit is set to 0.
If anything is written to the ADM or ADS register during conversion, A/D conversion is aborted. In this case, A/D
conversion is started again from the beginning.
Figure 13-14. Example of Select Mode Operation Timing
ANI1
Data 1
A/D conversion
operation
Data 1
(ANI1)
Data 2
Data 3
Data 4
Data 2
(ANI1)
Data 3
(ANI1)
Data 4
(ANI1)
Data 1
(ANI1)
ADCR,
ADCRH
Data 2
(ANI1)
Data 3
(ANI1)
Data 4
(ANI1)
INTAD
Conversion end
Conversion start
Set ADCS bit = 1
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Set ADCS bit = 0
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CHAPTER 13 A/D CONVERTER
(2) Scan mode
The four analog input channels of scans 0 to 3, which are specified by the analog input channel specification register
(ADS), while the ADMD bit of the A/D converter mode register (ADM) is 1, are A/D converted successively. A/D
conversion is performed in sequence, starting from the analog input channel specified by scan 0.
When A/D conversion of one analog input is complete, the conversion result is stored in the A/D conversion result
register (ADCR) and the A/D conversion end interrupt request signal (INTAD) is generated.
The A/D conversion results of all the analog input channels are stored in the ADCR register.
It is therefore
recommended to save the contents of the ADCR register to RAM, once A/D conversion of one analog input channel
has been completed.
After A/D conversion has been completed, A/D conversion is repeated successively, unless the ADCS bit is set to 0.
If anything is written to the ADM or ADS register during conversion, A/D conversion is aborted. In this case, A/D
conversion is started again from the analog input channel of scan 0.
Figure 13-15. Example of Scan Mode Operation Timing
ANI0
Data 5
Data 1
Data 6
ANI1
Data 2
Data 7
Data 3
ANI2
Data 8
ANI3
A/D conversion
operation
Data 4
Data 1
(ANI0)
ADCR,
ADCRH
Data 2
(ANI1)
Data 1
(ANI0)
Data 3
(ANI2)
Data 2
(ANI1)
Data 4
(ANI3)
Data 3
(ANI2)
Data 5
(ANI0)
Data 4
(ANI3)
Data 6
(ANI1)
Data 5
(ANI0)
Data 7
(ANI2)
Data 6
(ANI1)
Data 8
(ANI3)
Data 7
(ANI2)
Data 8
(ANI3)
INTAD
Conversion start
Set ADCS bit = 1
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Set ADCS bit = 0
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CHAPTER 13 A/D CONVERTER
The setting methods are described below.
<1> Set bit 5 (ADCEN) of peripheral enable register 0 (PER0) to 1.
<2> Select the conversion time by using bits 5 to 1 (FR2 to FR0, LV1, and LV0) of the A/D converter mode
register (ADM), and select the operation mode by using bit 6 (ADMD) of the ADM register.
<3> Set bit 0 (ADCE) of the ADM register to 1.
<4> Set the channel to be used in the analog input mode by using bits 4 to 0 (ADPC4 to ADPC0) of the A/D port
configuration register (ADPC), bits 7 to 0 (PM27 to PM20) of port mode register 2 (PM2), bits 7 to 0 (PM157
to PM150) of port mode register 15 (PM15), and bit 0 (PM80) of port mode register 8 (PM8).
<5> Set the programmable gain amplifier operation to set the programmable gain amplifier output (PGAI pin) for
the analog input channel (refer to 10.4.1 Starting comparator and programmable gain amplifier
operation).
<6> Select a channel to be used by using bits 6 and 3 to 0 (ADOAS, ADS3 to ADS0) of the analog input channel
specification register (ADS).
<7> Set bit 7 (ADCS) of the ADM register to 1 to start A/D conversion.
<8> When one A/D conversion has been completed, an interrupt request signal (INTAD) is generated.
<9> Transfer the A/D conversion data to the A/D conversion result register (ADCR, ADCRH).
<Change the channel>
<10> Change the channel using bits 6 and 3 to 0 (ADOAS, ADS3 to ADS0) of the ADS register to start A/D
conversion.
<11> When one A/D conversion has been completed, an interrupt request signal (INTAD) is generated.
<12> Transfer the A/D conversion data to the A/D conversion result register (ADCR, ADCRH).
<Complete A/D conversion>
<13> Clear the ADCS bit to 0.
<14> Clear the ADCE bit to 0.
<15> Clear bit 5 (ADCEN) of peripheral enable register 0 (PER0) to 0.
Cautions 1. Make sure the period of <3> to <7> is 1 μs or more.
2. <3> may be done between <4> and <6>.
3. <3> can be omitted. However, ignore data of the first conversion after <7> in this case.
4. The period from <8> to <11> differs from the conversion time set using bits 5 to 1 (FR2 to
FR0, LV1, LV0) of the ADM register. The period from <10> to <11> is the conversion time set
using the FR2 to FR0, LV1, and LV0 bits.
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13.5 How to Read A/D Converter Characteristics Table
Here, special terms unique to the A/D converter are explained.
(1) Resolution
This is the minimum analog input voltage that can be identified. That is, the percentage of the analog input voltage
per bit of digital output is called 1LSB (Least Significant Bit). The percentage of 1LSB with respect to the full scale is
expressed by %FSR (Full Scale Range).
1LSB is as follows when the resolution is 10 bits.
1LSB = 1/210 = 1/1024
= 0.098%FSR
Accuracy has no relation to resolution, but is determined by overall error.
(2) Overall error
This shows the maximum error value between the actual measured value and the theoretical value.
Zero-scale error, full-scale error, integral linearity error, and differential linearity errors that are combinations of these
express the overall error.
Note that the quantization error is not included in the overall error in the characteristics table.
(3) Quantization error
When analog values are converted to digital values, a ±1/2LSB error naturally occurs. In an A/D converter, an analog
input voltage in a range of ±1/2LSB is converted to the same digital code, so a quantization error cannot be avoided.
Note that the quantization error is not included in the overall error, zero-scale error, full-scale error, integral linearity
error, and differential linearity error in the characteristics table.
Figure 13-16. Overall Error
Figure 13-17. Quantization Error
1......1
1......1
Overall
error
Digital output
Digital output
Ideal line
1/2LSB
Quantization error
1/2LSB
0......0
AVREF
0
Analog input
0......0
0
Analog input
AVREF
(4) Zero-scale error
This shows the difference between the actual measurement value of the analog input voltage and the theoretical
value (1/2LSB) when the digital output changes from 0......000 to 0......001.
If the actual measurement value is greater than the theoretical value, it shows the difference between the actual
measurement value of the analog input voltage and the theoretical value (3/2LSB) when the digital output changes
from 0……001 to 0……010.
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(5) Full-scale error
This shows the difference between the actual measurement value of the analog input voltage and the theoretical
value (Full-scale − 3/2LSB) when the digital output changes from 1......110 to 1......111.
(6) Integral linearity error
This shows the degree to which the conversion characteristics deviate from the ideal linear relationship. It expresses
the maximum value of the difference between the actual measurement value and the ideal straight line when the zeroscale error and full-scale error are 0.
(7) Differential linearity error
While the ideal width of code output is 1LSB, this indicates the difference between the actual measurement value and
the ideal value.
Figure 13-18. Zero-Scale Error
Figure 13-19. Full-Scale Error
Full-scale error
Ideal line
011
010
001
Zero-scale error
Digital output (Lower 3 bits)
Digital output (Lower 3 bits)
111
000
111
110
101
Ideal line
000
0
1
2
3
AVREF
AVREF−3
0
Analog input (LSB)
AVREF−2
AVREF−1
AVREF
Analog input (LSB)
Figure 13-20. Integral Linearity Error
Figure 13-21. Differential Linearity Error
1......1
1......1
Ideal 1LSB width
Digital output
Digital output
Ideal line
Integral linearity
error
0......0
0
Analog input
Differential
linearity error
0......0
0
AVREF
Analog input
AVREF
(8) Conversion time
This expresses the time from the start of sampling to when the digital output is obtained.
The sampling time is included in the conversion time in the characteristics table.
(9) Sampling time
This is the time the analog switch is turned on for the analog voltage to be sampled by the sample & hold circuit.
Sampling
time
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CHAPTER 13 A/D CONVERTER
13.6 Cautions for A/D Converter
(1) Operating current in STOP mode
Shift to STOP mode after stopping the A/D converter (by setting bit 7 (ADCS) of the A/D converter mode register
(ADM) to 0). The operating current can be reduced by setting bit 0 (ADCE) of the ADM register to 0 at the same time.
To restart from the standby status, clear bit 0 (ADIF) of interrupt request flag register 1L (IF1L) to 0 and start
operation.
(2) Input range of ANI0 to ANI15 pins
Observe the rated range of the ANI0 to ANI15 pins input voltage. If a voltage of AVREF or higher and AVSS or lower
(even in the range of absolute maximum ratings) is input to an analog input channel, the converted value of that
channel becomes undefined. In addition, the converted values of the other channels may also be affected.
(3) Conflicting operations
<1> Conflict between the A/D conversion result register (ADCR, ADCRH) write and the ADCR or ADCRH register
read by instruction upon the end of conversion
The ADCR or ADCRH register read has priority. After the read operation, the new conversion result is written to
the ADCR or ADCRH registers.
<2> Conflict between the ADCR or ADCRH register write and the A/D converter mode register (ADM) write, the
analog input channel specification register (ADS), or A/D port configuration register (ADPC) write upon the end
of conversion
The ADM, ADS, or ADPC registers write has priority. The ADCR or ADCRH register write is not performed, nor
is the conversion end interrupt signal (INTAD) generated.
(4) Noise countermeasures
To maintain the 10-bit resolution, attention must be paid to noise input to the AVREF pin and ANI0 to ANI15 pins.
<1> Connect a capacitor with a low equivalent resistance and a good frequency response to the power supply.
<2> The higher the output impedance of the analog input source, the greater the influence. To reduce the noise,
connecting external C as shown in Figure 13-22 is recommended.
<3> Do not switch these pins with other pins during conversion.
<4> The accuracy is improved if the HALT mode is set immediately after the start of conversion.
Remark ANI0 to ANI9: 78K0R/KC3-L (40-pin, 44-pin)
ANI0 to ANI10: 78K0R/KC3-L (48-pin) and 78K0R/KD3-L
ANI0 to ANI11: 78K0R/KE3-L, 78K0R/KF3-L
ANI0 to ANI15: 78K0R/KG3-L
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Figure 13-22. Analog Input Pin Connection
If there is a possibility that noise equal to or higher than AVREF or
equal to or lower than AVSS may enter, clamp with a diode with a
small VF value (0.3 V or lower).
Reference
voltage
input
AVREF
ANI0 to ANI15
C = 100 to 1,000 pF
AVSS
VSS
(5) ANI0/P20 to ANI7/P27 and ANI8/P150 to ANI15/P157 pins
<1> The analog input pins (ANI0 to AN15) are also used as input port pins (P20 to P27, P150 to P157).
When A/D conversion is performed with any of the ANI0 to ANI15 pins selected, do not access P20 to P27 and
P150 to P157 while conversion is in progress; otherwise the conversion resolution may be degraded. It is
recommended to select pins used as P20 to P27 and P150 to P157 starting with the ANI0/P20 pin that is the
furthest from AVREF.
<2> If a digital pulse is applied to the pins adjacent to the pins currently used for A/D conversion, the expected value
of the A/D conversion may not be obtained due to coupling noise. Therefore, do not apply a pulse to the pins
adjacent to the pin undergoing A/D conversion.
(6) Input impedance of ANI0 to ANI15 pins
This A/D converter charges a sampling capacitor for sampling during sampling time.
Therefore, only a leakage current flows when sampling is not in progress, and a current that charges the capacitor
flows during sampling. Consequently, the input impedance fluctuates depending on whether sampling is in progress,
and on the other states.
To make sure that sampling is effective, however, it is recommended to keep the output impedance of the analog
input source to within 1 kΩ, and to connect a capacitor of about 100 pF to the ANI0 to ANI15 pins (see Figure 13-22).
(7) AVREF pin input impedance
A series resistor string of several tens of kΩ is connected between the AVREF and AVSS pins.
Therefore, if the output impedance of the reference voltage source is high, this will result in a series connection to the
series resistor string between the AVREF and AVSS pins, resulting in a large reference voltage error.
Remark P20/ANI0 to P27/ANI7, P150/ANI8, P151/ANI9:
78K0R/KC3-L (40-pin, 44-pin)
P20/ANI0 to P27/ANI7, P150/ANI8 to P152/ANI10: 78K0R/KC3-L (48-pin) and 78K0R/KD3-L
P20/ANI0 to P27/ANI7, P150/ANI8 to P153/ANI11: 78K0R/KE3-L, 78K0R/KF3-L
P20/ANI0 to P27/ANI7, P150/ANI8 to P157/ANI15: 78K0R/KG3-L
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CHAPTER 13 A/D CONVERTER
(8) Interrupt request flag (ADIF)
The interrupt request flag (ADIF) is not cleared even if the analog input channel specification register (ADS) is
changed.
Therefore, if an analog input pin is changed during A/D conversion, the A/D conversion result and ADIF flag for the
pre-change analog input may be set just before the ADS register rewrite. Caution is therefore required since, at this
time, when ADIF flag is read immediately after the ADS register rewrite, ADIF flag is set despite the fact A/D
conversion for the post-change analog input has not ended.
When A/D conversion is stopped and then resumed, clear ADIF flag before the A/D conversion operation is resumed.
Figure 13-23. Timing of A/D Conversion End Interrupt Request Generation
ADS rewrite
(start of ANIn conversion)
A/D conversion
ANIn
ADCR
ADS rewrite
(start of ANIm conversion)
ANIn
ANIn
ADIF is set but ANIm conversion
has not ended.
ANIm
ANIn
ANIm
ANIm
ANIm
ADIF
Remark n = 0 to 9, m = 0 to 9:
78K0R/KC3-L (40-pin, 44-pin), 78K0R/KC3-L (48-pin)
n = 0 to 10, m = 0 to 10: 78K0R/KD3-L
n = 0 to 11, m = 0 to 11: 78K0R/KE3-L, 78K0R/KF3-L
n = 0 to 11, m = 0 to 15: 78K0R/KG3-L
(9) Conversion results just after A/D conversion start
The first A/D conversion value immediately after A/D conversion starts may not fall within the rating range if the ADCS
bit is set to 1 within 1 μs after the ADCE bit was set to 1. Take measures such as polling the A/D conversion end
interrupt request (INTAD) and removing the first conversion result.
(10) A/D conversion result register (ADCR, ADCRH) read operation
When a write operation is performed to the A/D converter mode register (ADM), analog input channel specification
register (ADS), and A/D port configuration register (ADPC), the contents of the ADCR and ADCRH registers may
become undefined. Read the conversion result following conversion completion before writing to the ADM, ADS, or
ADPC register. Using a timing other than the above may cause an incorrect conversion result to be read.
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CHAPTER 13 A/D CONVERTER
(11) Internal equivalent circuit
The equivalent circuit of the analog input block is shown below.
Figure 13-24. Internal Equivalent Circuit of ANIn Pin
R1
ANIn
C1
C2
Table 13-4. Resistance and Capacitance Values of Equivalent Circuit (Reference Values)
AVREF
Mode
R1
C1
C2
4.0 V ≤ VDD ≤ 5.5 V
Normal
5.2 kΩ
8 pF
6.3 pF
High speed 1
5.2 kΩ
High speed 2
7.8 kΩ
Normal
18.6 kΩ
High speed 2
7.8 kΩ
Low-voltage
169.8 kΩ
2.7 V ≤ VDD < 4.0 V
1.8 V ≤ VDD < 4.0 V
Remarks 1. The resistance and capacitance values shown in Table 13-4 are not guaranteed values.
2. 78K0R/KC3-L (40-pin, 44-pin):
n = 0 to 9
78K0R/KC3-L (48-pin), 78K0R/KD3-L: n = 0 to 10
78K0R/KE3-L, 78K0R/KF3-L:
n = 0 to 11
78K0R/KG3-L:
n = 0 to 15
(12) Starting the A/D converter
Start the A/D converter after the AVREF voltage stabilize.
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CHAPTER 14 SERIAL ARRAY UNIT
CHAPTER 14 SERIAL ARRAY UNIT
Each serial array unit has four serial channels, each of which can be used for 3-wire serial (CSI), UART, and simplified
I2C communication.
Function assignment of each channel supported by the 78K0R/Kx3-L is as shown below.
• 78K0R/KC3-L, 78K0R/KD3-L, 78K0R/KE3-L
0
2
Used as CSI
Used as UART
Used as Simplified I C
0
CSI00
UART0 (supporting LIN-bus)
−
1
CSI01
2
CSI10
3
−
Unit
Channel
−
UART1
IIC10
−
• 78K0R/KF3-L, 78K0R/KG3-L
0
1
2
Note
Note
2
Used as CSI
Used as UART
Used as Simplified I C
0
CSI00
UART0
−
1
CSI01
2
CSI10
3
−
0
CSI20
1
−
2
−
3
−
Unit
Channel
0
CSI40
1
CSI41
−
UART1
IIC10
−
UART2
IIC20
−
UART3 (supporting LIN-bus)
−
−
UART4
−
−
Serial array unit 2 is only mounted in the μ PD78F1027, 78F1028, 78F1029, and 78F1030.
When “UART0” is used for channels 0 and 1 of the unit 0, CSI00 and CSI01 cannot be used, but CSI10, UART1, or
IIC10 can be used.
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CHAPTER 14 SERIAL ARRAY UNIT
14.1 Functions of Serial Array Unit
Each serial interface supported by the 78K0R/Kx3-L has the following features.
14.1.1 3-wire serial I/O (CSI00, CSI01, CSI10, CSI20, CSI40, CSI41)
Data is transmitted or received in synchronization with the serial clock (SCK) output from the master channel.
3-wire serial communication is clocked communication performed by using three communication lines: one for the serial
clock (SCK), one for transmitting serial data (SO), one for receiving serial data (SI).
For details about the settings, see 14.5 Operation of 3-Wire Serial I/O (CSI00, CSI01, CSI10, CSI20, CSI40, CSI41)
Communication.
[Data transmission/reception]
• Data length of 7 or 8 bits
• Phase control of transmit/receive data
• MSB/LSB first selectable
• Level setting of transmit/receive data
[Clock control]
• Master/slave selection
• Phase control of I/O clock
• Setting of transfer period by prescaler and internal counter of each channel
• Maximum transfer rate
During master communication: Max. fCLK/4, during slave communication: Max. fMCK/6 Note
[Interrupt function]
• Transfer end interrupt/buffer empty interrupt
[Error detection flag]
• Overrun error
Note
Use the clocks within a range satisfying the SCK cycle time (tKCY) characteristics (see CHAPTER 30
ELECTRICAL SPECIFICATIONS (78K0R/KC3-L, 78K0R/KD3-L, 78K0R/KE3-L) or CHAPTER 31
ELECTRICAL SPECIFICATIONS (78K0R/KF3-L, 78K0R/KG3-L)).
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CHAPTER 14 SERIAL ARRAY UNIT
14.1.2 UART (UART0 to UART4)
This is a start-stop synchronization function using two lines: serial data transmission (TXD) and serial data reception
(RXD) lines. By using these two communication lines, each data frame, which consist of a start bit, data, parity bit, and
stop bit, is transferred asynchronously (using the internal baud rate) between the microcontroller and the other
communication party. Full-duplex UART communication can be performed by using a channel dedicated to transmission
(even-numbered channel) and a channel dedicated to reception (odd-numbered channel).
The LIN-bus can be
implemented by using timer array unit 0 with an external interrupt (INTP0).
For details about the settings, see 14.6 Operation of UART (UART0 to UART4) Communication.
[Data transmission/reception]
• Data length of 5, 7, or 8 bits
• Select the MSB/LSB first
• Level setting of transmit/receive data and select of reverse
• Parity bit appending and parity check functions
• Stop bit appending
[Interrupt function]
• Transfer end interrupt/buffer empty interrupt
• Error interrupt in case of framing error, parity error, or overrun error
[Error detection flag]
• Framing error, parity error, or overrun error
The LIN-bus is accepted in UART0 (0 and 1 channels) of the 78K0R/KC3-L, 78K0R/KD3-L, 78K0R/KE3-L and UART3
(2 and 3 channels) of the 78K0R/KF3-L, 78K0R/KG3-L.
[LIN-bus functions]
• Wakeup signal detection
• Sync break field (SBF) detection
• Sync field measurement, baud rate calculation
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timer array unit 0
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CHAPTER 14 SERIAL ARRAY UNIT
2
14.1.3 Simplified I C (IIC10, IIC20)
This is a clocked communication function to communicate with two or more devices by using two lines: serial clock
(SCL) and serial data (SDA). This simplified I2C is designed for single communication with a device such as EEPROM,
flash memory, or A/D converter, and therefore, it functions only as a master.
Make sure by using software, as well as operating the control registers, that the AC specifications of the start and stop
conditions are observed.
For details about the settings, see 14.8 Operation of Simplified I2C (IIC10, IIC20)
[Data transmission/reception]
• Master transmission, master reception (only master function with a single master)
• ACK output functionNote and ACK detection function
• Data length of 8 bits (When an address is transmitted, the address is specified by the higher 7 bits, and the least
significant bit is used for R/W control.)
• Manual generation of start condition and stop condition
[Interrupt function]
• Transfer end interrupt
[Error detection flag]
• Parity error (ACK error)
* [Functions not supported by simplified I2C]
• Slave transmission, slave reception
• Arbitration loss detection function
• Wait detection functions
Note When receiving the last data, ACK will not be output if 0 is written to the SOEmn bit (serial output enable register
m (SOEm)) and serial communication data output is stopped. See the processing flow in 14.8.3 (2) for details.
Remark
To use an I2C bus of full function, see CHAPTER 15 SERIAL INTERFACE IICA.
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CHAPTER 14 SERIAL ARRAY UNIT
14.2 Configuration of Serial Array Unit
The serial array unit includes the following hardware.
Table 14-1. Configuration of Serial Array Unit (1/2) (78K0R/KC3-L, KD3-L, KE3-L)
Item
Configuration
78K0R/KC3-L, 78K0R/KD3-L, 78K0R/KE3-L
Shift register
8 bits
Buffer register
Lower 8 bits of serial data register mn (SDRmn)
Serial clock I/O
SCK00, SCK01, SCK10 pins (for 3-wire serial I/O), SCL10 pin (for simplified I C)
Serial data input
Note
2
SI00, SI01, SI10 pins (for 3-wire serial I/O), RXD0 pin (for UART supporting LIN-bus),
RXD1 pin (for UART)
Serial data output
SO00, SO01, SO10 pins (for 3-wire serial I/O), TXD0 pin (for UART supporting LIN-bus),
TXD1 pin (for UART), output controller
2
Serial data I/O
SDA10 pin (for simplified I C)
Control registers
<Registers of unit setting block>
• Peripheral enable register 0 (PER0)
• Serial clock select register 0 (SPS0)
• Serial channel enable status register 0 (SE0)
• Serial channel start register 0 (SS0)
• Serial channel stop register 0 (ST0)
• Serial output enable register 0 (SOE0)
• Serial output register 0 (SO0)
• Serial output level register 0 (SOL0)
• Input switch control register (ISC)
• Noise filter enable register 0 (NFEN0)
<Registers of each channel>
• Serial data register 0n (SDR0n)
• Serial mode register 0n (SMR0n)
• Serial communication operation setting register 0n (SCR0n)
• Serial status register 0n (SSR0n)
• Serial flag clear trigger register 0n (SIR0n)
• Port input mode registers 3, 7 (PIM3, PIM7)
• Port output mode registers 3, 7 (POM3, POM7)
• Port mode registers 3, 7 (PM3, PM7)
• Port registers 3, 7 (P3, P7)
Note The lower 8 bits of serial data register 0n (SDR0n) can be read or written as the following SFR, depending on
the communication mode.
• CSIp communication … SIOp (CSIp data register)
• UARTq reception … RXDq (UARTq receive data register)
• UARTq transmission … TXDq (UARTq transmit data register)
• IIC10 communication … SIO10 (IIC10 data register)
Remark
n: Channel number (n = 0 to 3), p: CSI number (p = 00, 01, 10),
q: UART number (q = 0, 1)
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CHAPTER 14 SERIAL ARRAY UNIT
Table 14-1. Configuration of Serial Array Unit (2/2) (78K0R/KF3-L, 78K0R/KG3-L)
Item
Configuration
μ PD78F1010, 78F1011, 78F1012, 78F1013,
μ PD78F1027, 78F1028, 78F1029, 78F1030
78F1014
Shift register
8 bits
Buffer register
Lower 8 bits of serial data register mn (SDRmn)
Serial clock I/O
SCK00, SCK01, SCK10, SCK20 pins (for 3-wire
SCK00, SCK01, SCK10, SCK20, SCK40, SCK41
serial I/O), SCL10, SCL20 pins (for simplified
2
I C)
pins (for 3-wire serial I/O), SCL10, SCL20 pins
2
(for simplified I C)
Serial data input
Serial data output
Note
SI00, SI01, SI10, SI20 pins (for 3-wire serial I/O), SI00, SI01, SI10, SI20, SI40, SI41 pins (for 3RXD0 to RxD2 pins (for UART), RXD3 pin (for
wire serial I/O), RXD0 to RxD2, RxD4 pins (for
UART supporting LIN-bus)
UART), RXD3 pin (for UART supporting LIN-bus)
SO00, SO01, SO10, SO20 pins (for 3-wire serial
SO00, SO01, SO10, SO20, SO40, SO41 pins
I/O), TXD0 to TxD2 pins (for UART),
(for 3-wire serial I/O), TXD0 to TxD2, TxD4 pins
TXD3 pin (for UART supporting LIN-bus), output
(for UART), TXD3 pin (for UART supporting LIN-
controller
bus), output controller
2
Serial data I/O
SDA10, SDA20 pins (for simplified I C)
Control registers
<Registers of unit setting block>
<Registers of unit setting block>
• Peripheral enable register 0 (PER0)
• Peripheral enable registers 0, 1 (PER0, PER1)
• Serial clock select register m (SPSm)
• Serial clock select register m (SPSm)
• Serial channel enable status register m (SEm)
• Serial channel enable status register m (SEm)
• Serial channel start register m (SSm)
• Serial channel start register m (SSm)
• Serial channel stop register m (STm)
• Serial channel stop register m (STm)
• Serial output enable register m (SOEm)
• Serial output enable register m (SOEm)
• Serial output register m (SOm)
• Serial output register m (SOm)
• Serial output level register m (SOLm)
• Serial output level register m (SOLm)
• Input switch control register (ISC)
• Input switch control register (ISC)
• Noise filter enable register 0 (NFEN0)
• Noise filter enable register 0 (NFEN0)
<Registers of each channel>
• Serial data register mn (SDRmn)
• Serial mode register mn (SMRmn)
• Serial communication operation setting register mn (SCRmn)
• Serial status register mn (SSRmn)
• Serial flag clear trigger register mn (SIRmn)
• Port input mode registers 0, 1, 14 (PIM0, PIM1, PIM14)
• Port output mode registers 0, 1, 14 (POM0, POM1, POM14)
• Port mode registers 0, 1, 4, 14 (PM0, PM1, PM4, PM14)
• Port registers 0, 1, 4, 14 (P0, P1, P4, P14
Note The lower 8 bits of serial data register mn (SDRmn) can be read or written as the following SFR, depending on
the communication mode.
• CSIp communication … SIOp (CSIp data register)
• UARTq reception … RXDq (UARTq receive data register)
• UARTq transmission … TXDq (UARTq transmit data register)
• IICr communication … SIOr (IICr data register)
Remark
m: Unit number (m = 0 to 2), n: Channel number (n = 0 to 3), p: CSI number (p = 00, 01, 10, 20, 40, 41),
q: UART number (q = 0 to 4), r: IIC number (r = 10, 20)
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CHAPTER 14 SERIAL ARRAY UNIT
Figure 14-1 shows the block diagram of the serial array unit 0.
Figure 14-1. Block Diagram of Serial Array Unit 0
Noise filter enable
register 0 (NFEN0)
Serial output register 0 (SO0)
0
Peripheral enable
register 0 (PER0)
0
0
1
0
CKO02 CKO01 CKO00
0
0
0
0
Serial clock select register 0 (SPS0)
PRS
013
SAU0EN
PRS
012
PRS
011
PRS
003
PRS
010
PRS
002
4
PRS
001
PRS
000
4
SO02 SO01
SO00
SE03
SE02 SE01
SE00
Serial channel enable
status register 0 (SE0)
SS03
SS02 SS01
SS00
Serial channel start
register 0 (SS0)
ST03
ST02
ST00
Serial channel stop
register 0 (ST0)
Prescaler
fCLK
0
0
11
11
fCLK/2 to fCLK/2
fCLK/2 to fCLK/2
SNFEN SNFEN
10
00
1
ST01
0
SOE02 SOE01 SOE00
0
SOL02
0
SOL00
INTTM02
Serial output enable
register 0 (SOE0)
Serial output level
register 0 (SOL0)
Selector
Selector
Serial data register 00 (SDR00)
CK00
fSCK
Edge
detection
Serial clock I/O pin
(when CSI00: SCK00)
Output latch
(Pyy)
(Buffer register block)
Serial data output pin
(when CSI00: SO00)
(when UART0: TXD0)
fTCLK
Shift register
Output
controller
Interrupt
controller
Communication controller
Output latch
(Pxx)
PMxx
Noise
elimination
enabled/
disabled
Edge/level
detection
SNFEN00
CKS00 CCS00 STS00 MD002 MD001
Serial mode register 00 (SMR00)
TXE
00
RXE
00
DAP
00
CKP
00
When UART0
EOC
00
Serial data input pin
(when CSI01: SI01)
Serial data input pin
(when CSI10: SI10)
(when IIC10: SDA10)
(when UART1: RXD1)
DIR
00
SLC
001
SLC
000
Selector
Error controller
DLS
002
DLS
001
DLS
000
TSF
00
BFF
00
FEF
00
PEF
00
OVF
00
Serial status register 00 (SSR00)
Serial data output pin
(when CSI01: SO01)
Communication controller
Mode selection
CSI01 or UART0
(for reception)
Edge/level
detection
Serial transfer end interrupt
(when CSI01: INTCSI01)
(when UART0: INTSR0)
Error controller
Serial transfer error interrupt
(INTSRE0)
CK00
Channel 2
Noise
elimination
enabled/
disabled
Clear
CK00
Channel 1
(LIN-bus supported) Note
CK01
Serial clock I/O pin
(when CSI10: SCK10)
(when IIC10: SCL10)
PTC
000
FECT PECT OVCT
00
00
00
Error
information
Serial communication operation setting register 00 (SCR00)
CK01
Serial clock I/O pin
(when CSI01: SCK01)
PTC
001
Serial transfer end interrupt
(when CSI00: INTCSI00)
(when UART0: INTST0)
Serial flag clear trigger
register 00 (SIR00)
Mode selection
CSI00 or UART0
(for transmission)
Communication
status
Serial data input pin
(when CSI00: SI00)
(when UART0: RxD0)
PMyy
fMCK
Clock controller
Selector
Channel 0
(LIN-bus supported) Note
(Clock division setting block)
Selector
CK01
Serial data output pin
(when CSI10: SO10)
(when IIC10: SDA10)
(when UART1: TXD1)
Communication controller
Mode selection
CSI10 or IIC10
or UART1
(for transmission)
Edge/level
detection
Serial transfer end interrupt
(when CSI10: INTCSI10)
(when IIC10: INTIIC10)
(when UART1: INTST1)
SNFEN10
CK01
CK00
Channel 3
Communication controller
When UART1
Edge/level
detection
Mode selection
UART1
(for reception)
Serial transfer end interrupt
(when UART1: INTSR1)
Error controller
Serial transfer error interrupt
(INTSRE1)
Note In the 78K0R/KF3-L and 78K0R/KG3-L, UART3 (unit 1, channels 2 and 3) is used for LIN-bus communication.
Remark
78K0R/KC3-L, 78K0R/KD3-L, 78K0R/KE3-L: PMxx, Pxx = PM75, P75 PMyy, Pyy = PM73, P73
78K0R/KF3-L, 78K0R/KG3-L:
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CHAPTER 14 SERIAL ARRAY UNIT
Figure 14-2 shows the block diagram of the serial array unit 1.
Figure 14-2. Block Diagram of Serial Array Unit 1 (78K0R/KF3-L, 78K0R/KG3-L only)
Noise filter enable
register 0 (NFEN0)
Serial output register 1 (SO1)
0
Peripheral enable
register 0 (PER0)
0
0
1
0
1
1
0
0
CKO10
0
1
0
Serial clock select register 1 (SPS1)
PRS
113
SAU1EN
PRS
112
PRS
111
PRS
110
PRS
101
PRS
102
PRS
103
4
SNFEN SNFEN
30
20
SO10
Serial channel enable
status register 1 (SE1)
SE13
SE12 SE11
SE10
SS13
SS12 SS11
SS10
Serial channel start
register 1 (SS1)
ST10
Serial channel stop
register 1 (ST1)
ST13
ST12
ST11
0
SOE12
0
Serial output enable
SOE10 register 1 (SOE1)
0
SOL12
0
SOL10
Prescaler
fCLK/20 to
fCLK/211
fCLK/20 to fCLK/211
1
PRS
100
4
fCLK
SO11
Serial output level
register 1 (SOL1)
Selector
Selector
Serial data register 10 (SDR10)
CK11
(Clock division setting block)
Selector
CK10
Selector
Serial clock I/O pin
(when CSI20: SCK20)
(when IIC20: SCL20)
fSCK
Edge
detection
Output latch
(P144 or P143)
(Buffer register block)
Serial data output pin
(when CSI20: SO20)
(when IIC20: SDA20)
(when UART2: TxD2)
fTCLK
Shift register
Output
controller
Interrupt
controller
Communication controller
Noise
elimination
enabled/
disabled
Edge/level
detection
SNFEN20
CKS10 CCS10 STS10 MD102 MD101
Serial mode register 10 (SMR10)
Serial transfer end interrupt
(when CSI20: INTCSI20)
(when IIC20: INTIIC20)
(when UART2: INTST2)
Serial flag clear trigger
register 10 (SIR10)
FECT PECT OVCT
10
10
10
Communication
status
Serial data input pin
(when CSI20: SI20)
(when IIC20: SDA20)
(when UART2: RxD2)
Mode selection
CSI20 or IIC20
or UART2
(for transmission)
Output latch
(P142)
PM142
PM144 or PM143
fMCK
Clock controller
Channel 0
Clear
Error controller
Error
information
TXE
10
RXE
10
DAP
10
CKP
10
EOC
10
PTC
101
PTC
100
DIR
10
SLC
101
SLC
100
Serial communication operation setting register 10 (SCR10)
CK11
DLS
100
TSF
10
BFF
10
FEF
10
PEF
10
OVF
10
Serial status register 10 (SSR10)
Communication controller
Mode selection
UART2
(for reception)
When UART2
Edge/level
detection
CK11
Serial transfer end interrupt
(when UART2: INTSR2)
Error controller
Serial transfer error interrupt
(INTSRE2)
CK10
Channel 2 (LIN-bus supported) Note
Serial data input pin
(when UART3: RxD3)
DLS
101
CK10
Channel 1
Noise
elimination
enabled/
disabled
DLS
102
Communication controller
Serial data output pin
(when UART3: TXD3)
Mode selection
UART3
(for transmission)
Edge/level
detection
Serial transfer end interrupt
(when UART3: INTST3)
SNFEN30
CK11
CK10
Channel 3 (LIN-bus supported) Note
When UART3
Edge/level
detection
Communication controller
Mode selection
UART3
(for reception)
Serial transfer end interrupt
(when UART3: INTSR3)
Error controller
Serial transfer error interrupt
(INTSRE3)
Note In the 78K0R/KC3-L, 78K0R/KD3-L, and 78K0R/KE3-L, UART0 (unit 0, channels 0 and 1) is used for LIN-bus
communication.
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CHAPTER 14 SERIAL ARRAY UNIT
Figure 14-3 shows the block diagram of the serial array unit 1.
Figure 14-3. Block Diagram of Serial Array Unit 1 (μ PD78F1027, 78F1028, 78F1029, 78F1030 only)
Noise filter enable
register 0 (NFEN0)
Serial output register 2 (SO2)
0
Peripheral enable
register 1 (PER1)
0
0
1
0
1
0
0
CKO21 CKO20
0
0
Serial clock select register 2 (SPS2)
PRS
213
SAU2EN
PRS
212
PRS
211
PRS
210
PRS
201
PRS
202
PRS
203
4
Prescaler
fCLK
fCLK/20 to
fCLK/211
fCLK/20 to fCLK/211
1
SO21
SO20
0
0
SE21
SE20
0
0
SS21
SS20
Serial channel start
register 2 (SS2)
ST20
Serial channel stop
register 2 (ST2)
Serial channel enable
status register 2 (SE2)
PRS
200
4
SNFEN
40
1
0
0
0
0
0
0
ST21
Serial output enable
SOE21 SOE20 register 2 (SOE2)
0
SOL20
Serial output level
register 2 (SOL2)
Selector
Selector
Serial data register 20 (SDR20)
CK21
(Clock division setting block)
Selector
CK20
Selector
Serial clock I/O pin
(when CSI40: SCK40)
fSCK
Edge
detection
Output latch
(P52)
(Buffer register block)
Serial data output pin
(when CSI40: SO40)
(when UART4: TxD4)
fTCLK
Shift register
Output
controller
Interrupt
controller
Communication controller
Noise
elimination
enabled/
disabled
Edge/level
detection
SNFEN40
CKS20 CCS20 STS20 MD202 MD201
Serial mode register 20 (SMR20)
Serial transfer end interrupt
(when CSI40: INTCSI40)
(when UART4: INTST4)
Serial flag clear trigger
register 20 (SIR20)
FECT PECT OVCT
20
20
20
Communication
status
Serial data input pin
(when CSI40: SI40)
(when UART4: RxD4)
Mode selection
CSI40 or UART4
(for transmission)
Output latch
(P50)
PM50
PM52
fMCK
Clock controller
Channel 0
Clear
Error controller
Error
information
TXE
20
RXE
20
DAP
20
CKP
20
EOC
20
PTC
201
PTC
200
DIR
20
SLC
201
SLC
200
Serial communication operation setting register 20 (SCR20)
CK21
Channel 1
DLS
201
DLS
200
TSF
20
BFF
20
FEF
20
PEF
20
OVF
20
Serial status register 20 (SSR20)
CK20
Communication controller
When UART4
Edge/level
detection
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DLS
202
Mode selection
UART4
(for reception)
Serial transfer end interrupt
(when UART4: INTSR4)
Error controller
Serial transfer error interrupt
(INTSRE4)
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CHAPTER 14 SERIAL ARRAY UNIT
(1) Shift register
This is an 8-bit register that converts parallel data into serial data or vice versa.
During reception, it converts data input to the serial pin into parallel data.
When data is transmitted, the value set to this register is output as serial data from the serial output pin.
The shift register cannot be directly manipulated by program.
To read or write the shift register, use the lower 8 bits of serial data register mn (SDRmn).
7
6
5
4
3
2
1
0
Shift register
(2) Lower 8 bits of the serial data register mn (SDRmn)
The SDRmn register is the transmit/receive data register (16 bits) of channel n.
Bits 7 to 0 function as a
transmit/receive buffer register, and bits 15 to 9 are used as a register that sets the division ratio of the operation
clock (fMCK).
When data is received, parallel data converted by the shift register is stored in the lower 8 bits. When data is to be
transmitted, set transmit to be transferred to the shift register to the lower 8 bits.
The data stored in the lower 8 bits of this register is as follows, depending on the setting of bits 0 to 2 (DLSmn0 to
DLSmn2) of serial communication operation setting register mn (SCRmn), regardless of the output sequence of
the data.
• 5-bit data length (stored in bits 0 to 4 of SDRmn register) (settable in UART mode only)
• 7-bit data length (stored in bits 0 to 6 of SDRmn register)
• 8-bit data length (stored in bits 0 to 7 of SDRmn register)
The SDRmn register can be read or written in 16-bit units.
The lower 8 bits of the SDRmn register can be read or writtenNote as the following SFR, depending on the
communication mode.
• CSIp communication … SIOp (CSIp data register)
• UARTq reception … RXDq (UARTq receive data register)
Note Writing in 8-bit units is prohibited
• UARTq transmission … TXDq (UARTq transmit data register)
when the operation is stopped
• IICr communication … SIOr (IICr data register)
(SEmn = 0).
Reset signal generation clears the SDRmn register to 0000H.
Remarks 1. After data is received, “0” is stored in bits 0 to 7 in bit portions that exceed the data length.
2. m: Unit number (m = 0 to 2), n: Channel number (n = 0 to 3), p: CSI number (p = 00, 01, 10, 20, 40,
41), q: UART number (q = 0 to 4), r: IIC number (r = 10, 20)
78K0R/KC3-L, 78K0R/KD3-L, 78K0R/KE3-L:
mn = 00 to 03, p = 00, 01, 10, q = 0, 1,
r = 10
78K0R/KF3-L μ PD78F1010, 78F1011, 78F1012 :
mn = 00 to 03, 10 to 13, p = 00, 01, 10,
20, q = 0 to 3, r = 10, 20
78K0R/KF3-L μ PD78F1027, 78F1028 :
mn = 00 to 03, 10 to 13, 20, 21, p = 00,
01, 10, 20, 40, 41, q = 0 to 4, r = 10, 20
78K0R/KG3-L μ PD78F1013, 78F1014 :
mn = 00 to 03, 10 to 13, p = 00, 01, 10,
20, q = 0 to 3, r = 10, 20
78K0R/KG3-L μ PD78F1029, 78F1030 :
mn = 00 to 03, 10 to 13, 20, 21, p = 00,
01, 10, 20, 40, 41, q = 0 to 4, r = 10, 20
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CHAPTER 14 SERIAL ARRAY UNIT
Figure 14-3. Format of Serial Data Register mn (SDRmn)
Address: FFF10H, FFF11H (SDR00), FFF12H, FFF13H (SDR01),
After reset: 0000H
R/W
FFF44H, FFF45H (SDR02), FFF46H, FFF47H (SDR03)
FFF48H, FFF49H (SDR10), FFF4AH, FFF4BH (SDR11),
FFF14H, FFF15H (SDR12), FFF16H, FFF17H (SDR13),
FFF4CH, FFF4DH (SDR20), FFF4EH, FFF4FH (SDR21)
FFF10H (SDR00)
FFF11H (SDR00)
15
14
13
12
11
10
9
SDRmn
8
7
6
5
4
3
2
1
0
7
6
5
4
3
2
1
0
0
Shift register
Caution
Be sure to clear bit 8 to “0”.
Remarks 1. For the function of the higher 7 bits of the SDRmn register, see 14.3 Registers Controlling Serial
Array Unit.
2. m: Unit number (m = 0 to 2), n: Channel number (n = 0 to 3)
78K0R/KC3-L, 78K0R/KD3-L, 78K0R/KE3-L:
mn = 00-03,
78K0R/KF3-L μ PD78F1010, 78F1011, 78F1012 :
mn = 00-03, 10-13
78K0R/KF3-L μ PD78F1027, 78F1028 :
mn = 00-03, 10-13, 20, 21
78K0R/KG3-L μ PD78F1013, 78F1014 :
mn = 00-03, 10-13
78K0R/KG3-L μ PD78F1029, 78F1030 :
mn = 00-03, 10-13, 20, 21
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CHAPTER 14 SERIAL ARRAY UNIT
14.3 Registers Controlling Serial Array Unit
Serial array unit is controlled by the following registers.
• Peripheral enable registers 0, 1 (PER0, PER1)
• Serial clock select register m (SPSm)
• Serial mode register mn (SMRmn)
• Serial communication operation setting register mn (SCRmn)
• Serial data register mn (SDRmn)
• Serial flag clear trigger register mn (SIRmn)
• Serial status register mn (SSRmn)
• Serial channel start register m (SSm)
• Serial channel stop register m (STm)
• Serial channel enable status register m (SEm)
• Serial output enable register m (SOEm)
• Serial output level register m (SOLm)
• Serial output register m (SOm)
• Input switch control register (ISC)
• Noise filter enable register 0 (NFEN0)
[78K0R/KC3-L, 78K0R/KD3-L, 78K0R/KE3-L]
• Port input mode registers 3, 7 (PIM3, PIM7)
• Port output mode registers 3, 7 (POM3, POM7)
• Port mode registers 3, 7 (PM3, PM7)
• Port registers 3, 7 (P3, P7)
[78K0R/KF3-L, 78K0R/KG3-L]
• Port input mode registers 0, 1, 14 (PIM0, PIM1, PIM14)
• Port output mode registers 0, 1, 14 (POM0, POM1, POM14)
• Port mode registers 0, 1, 4, 5Note, 14 (PM0, PM1, PM4, PM5Note, PM14)
• Port registers 0, 1, 4, 5
Note
Note
, 14 (P0, P1, P4, P5Note, P14)
Those are only mounted in the μ PD78F1027, 78F1028, 78F1029, and 78F1030.
Remark
m: Unit number (m = 0 to 2), n: Channel number (n = 0 to 3)
78K0R/KC3-L, 78K0R/KD3-L, 78K0R/KE3-L:
mn = 00 to 03
78K0R/KF3-L μ PD78F1010, 78F1011, 78F1012 :
mn = 00 to 03, 10 to 13
78K0R/KF3-L μ PD78F1027, 78F1028 :
mn = 00 to 03, 10 to 13, 20, 21
78K0R/KG3-L μ PD78F1013, 78F1014 :
mn = 00 to 03, 10 to 13
78K0R/KG3-L μ PD78F1029, 78F1030 :
mn = 00 to 03, 10 to 13, 20, 21
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CHAPTER 14 SERIAL ARRAY UNIT
(1) Peripheral enable registers 0, 1 (PER0, PER1)
PER0 and PER1 register are used to enable or disable supplying the clock to the peripheral hardware. Clock
supply to a hardware macro that is not used is stopped in order to reduce the power consumption and noise.
When serial array unit 0 is used, be sure to set bit 2 (SAU0EN) of PER0 register to 1.
In the 78K0R/KF3-L and 78K0R/KG3-L, be sure to set bit 3 (SAU1EN) of PER0 register to 1 when using serial
array unit 1, in the 78K0R/KF3-L (μ PD78F1027, 78F1028) and 78K0R/KG3-L (μ PD78F1029, 78F1030), be sure to
set bit 0 (SAU2EN) of PER1 register to 1 when using serial array unit 2.
The PER0 and PER1 registers can be set by a 1-bit or 8-bit memory manipulation instruction.
Reset signal generation clears the PER0 and PER1 register to 00H.
Figure 14-5. Format of Peripheral Enable Register 0, 1 (PER0, PER1)
Address: F00F0H
Symbol
PER0
<7>
RTCEN
Address: F00F1H
Symbol
PER1
After reset: 00H
Note
R/W
6
Note 1
<5>
0
After reset: 00H
<4>
IICAEN
ADCEN
<3>
Note 2
SAU1EN
<2>
Note 3
SAU0EN
<1>
TAU1EN
<0>
Note 3
TAU0EN
R/W
7
6
5
4
3
2
1
<0>
0
0
0
0
0
0
0
SAU2EN
SAUmEN
0
Note 3
Note 4
Control of serial array unit m input clock supply
Stops supply of input clock.
• SFR used by serial array unit m cannot be written.
• Serial array unit m is in the reset status.
1
Enables input clock supply.
• SFR used by serial array unit m can be read/written.
Notes 1.
That is not provided in 40-pin product of the 78K0R/KC3-L.
2.
That is not provided in 40-pin and 44-pin products of the 78K0R/KC3-L.
3.
78K0R/KF3-L and 78K0R/KG3-L only.
4.
78K0R/KF3-L (μ PD78F1027, 78F1028) and 78K0R/KG3-L (μ PD78F1029, 78F1030) only.
Cautions 1. When setting serial array unit m, be sure to set the SAUmEN bit to 1 first. If SAUmEN = 0,
writing to a control register of serial array unit m is ignored, and, even if the register is read,
only the default value is read.
Note that this does not apply to the following registers.
78K0R/KC3-L, 78K0R/KD3-L, 78K0R/KE3-L:
ISC, NFEN0, PIM3, PIM7, POM3, POM7, PM3, PM7, P3, and P7 registers.
78K0R/KF3-L (μ PD78F1010, 78F1011, 78F1012), 78K0R/KG3-L (μ PD78F1013, 78F1014):
ISC, NFEN0, PIM0, PIM1, PIM14, POM0, POM1, POM14, PM0, PM1, PM4, PM14, P0, P1, P4,
and P14 registers.
78K0R/KF3-L (μ PD78F1027, 78F1028), 78K0R/KG3-L (μ PD78F1029, 78F1030):
ISC, NFEN0, PIM0, PIM1, PIM14, POM0, POM1, POM14, PM0, PM1, PM4, PM5, PM14, P0, P1,
P4, P5, and P14 registers.
2. After setting the SAUmEN bit to 1, be sure to set serial clock select register m (SPSm) after 4
or more fCLK clocks have elapsed.
(Caution 3 and Remark are listed on the next page.)
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Cautions
CHAPTER 14 SERIAL ARRAY UNIT
3. Be sure to clear the following bits to 0.
48-pin product of the 78K0R/KC3-L, 78K0R/KD3-L, 78K0R/KE3-L:
bits 0, 1, 3, 6 of PER0
register
44-pin product of the 78K0R/KC3-L:
bits 0, 1, 3, 4, 6 of PER0
register
40-pin product of the 78K0R/KC3-L:
bits 0, 1, 3, 4, 6, 7 of PER0
register
78K0R/KF3-L (μ PD78F1010, 78F1011, 78F1012):
bit 6 of PER0 register
78K0R/KF3-L (μ PD78F1027, 78F1028):
bit 6 of PER0 register, bits
1 to 7 of PER1 register
78K0R/KG3-L (μ PD78F1013, 78F1014):
bit 6 of PER0 register
78K0R/KG3-L (μ PD78F1029, 78F1030):
bit 6 of PER0 register, bits
1 to 7 of PER1 register
Remark
78K0R/KC3-L, 78K0R/KD3-L, 78K0R/KE3-L:
m=0
78K0R/KF3-L μ PD78F1010, 78F1011, 78F1012 :
m = 0, 1
78K0R/KF3-L μ PD78F1027, 78F1028 :
m = 0 to 2
78K0R/KG3-L μ PD78F1013, 78F1014 :
m = 0, 1
78K0R/KG3-L μ PD78F1029, 78F1030 :
m = 0 to 2
(2) Serial clock select register m (SPSm)
The SPSm register is a 16-bit register that is used to select two types of operation clocks (CKm0, CKm1) that are
commonly supplied to each channel. CKm1 is selected by bits 7 to 4 of the SPSm register , and CKm0 is selected
by bits 3 to 0.
Rewriting the SPSm register is prohibited when the register is in operation (when SEmn = 1).
The SPSm register can be set by a 16-bit memory manipulation instruction.
The lower 8 bits of the SPSm register can be set with an 8-bit memory manipulation instruction with SPSmL.
Reset signal generation clears the SPSm register to 0000H.
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CHAPTER 14 SERIAL ARRAY UNIT
Figure 14-6. Format of Serial Clock Select Register m (SPSm) (1/2)
Address: F0126H, F0127H (SPS0), F0166H, F0167H (SPS1)
After reset: 0000H
R/W
F0216H, F0217H (SPS2)
Symbol
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
SPSm
0
0
0
0
0
0
0
0
PRS
PRS
PRS
PRS
PRS
PRS
PRS
PRS
m13
m12
m11
m10
m03
m02
m01
m00
PRS
PRS
PRS
PRS
mk3
mk2
mk1
mk0
0
0
0
0
fCLK
0
0
0
1
fCLK/2
0
0
0
0
0
0
1
1
1
1
0
0
0
1
0
1
Section of operation clock (CKmk)
fCLK = 2 MHz
fCLK = 5 MHz
Note 1
fCLK = 10 MHz
fCLK = 20 MHz
2 MHz
5 MHz
10 MHz
20 MHz
1 MHz
2.5 MHz
5 MHz
10 MHz
fCLK/2
2
500 kHz
1.25 MHz
2.5 MHz
5 MHz
fCLK/2
3
250 kHz
625 kHz
1.25 MHz
2.5 MHz
fCLK/2
4
125 kHz
313 kHz
625 kHz
1.25 MHz
fCLK/2
5
62.5 kHz
156 kHz
313 kHz
625 kHz
0
1
1
0
fCLK/2
6
31.3 kHz
78.1 kHz
156 kHz
313 kHz
0
1
1
1
fCLK/2
7
15.6 kHz
39.1 kHz
78.1 kHz
156 kHz
fCLK/2
8
7.81 kHz
19.5 kHz
39.1 kHz
78.1 kHz
fCLK/2
9
3.91 kHz
9.77 kHz
19.5 kHz
39.1 kHz
fCLK/2
10
1.95 kHz
4.88 kHz
9.77 kHz
19.5 kHz
fCLK/2
11
977 Hz
2.44 kHz
4.88 kHz
9.77 kHz
1
1
1
1
1
0
0
0
0
1
0
0
1
1
1
Other than above
0
1
0
1
1
INTTM02 if m = 0
Note 2
, setting prohibited if m = 1
Setting prohibited
Notes 1. When changing the clock selected for fCLK (by changing the system clock control register (CKC) value), do
so after having stopped (serial channel stop register m (STm) = 000FH) the operation of the serial array
unit (SAU). When selecting INTTM02 for the operation clock, also stop the timer array unit 0 (timer
channel stop register 0 (TT0) = 00FFH).
2.
SAU0 can be operated at a fixed division ratio of the subsystem clock, regardless of the fCLK frequency
(main system clock, sub system clock), by operating the interval timer for which fSUB/4Note 3 has been
selected as the count clock (setting the TIS02 bit of timer input select register 0 (TIS0) to 1) and
selecting INTTM02 by using the SPS0 register in channel 2 of TAU0. When changing fCLK, however,
SAU0 and TAU0 must be stopped as described in Note 1 above.
3.
The 78K0R/KC3-L (40-pin) doesn’t have the subsystem clock.
Cautions 1. Be sure to clear bits 15 to 8 to “0”.
2. After setting bit 2 (SAU0EN) of the PER0 register, bit 3 (SAU1EN) of the PER0 register, and bit
0 (SAU2EN) of the PER1 register to 1, be sure to set serial clock select register m (SPSm) after
4 or more fCLK clocks have elapsed.
Remarks 1. fCLK: CPU/peripheral hardware clock frequency
fSUB: Subsystem clock frequency
(Remarks 2 and 3 are listed on the next page.)
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Figure 14-6. Format of Serial Clock Select Register m (SPSm) (2/2)
Remarks 2.
3.
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m: Unit number (m = 0, 1)
78K0R/KC3-L, 78K0R/KD3-L, 78K0R/KE3-L:
m=0
78K0R/KF3-L (μ PD78F1010, 78F1011, 78F1012):
m = 0, 1
78K0R/KF3-L (μ PD78F1027, 78F1028):
m = 0 to 2
78K0R/KG3-L (μ PD78F1013, 78F1014):
m = 0, 1
78K0R/KG3-L(μ PD78F1029, 78F1030):
m = 0 to 2
k = 0, 1
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CHAPTER 14 SERIAL ARRAY UNIT
(3) Serial mode register mn (SMRmn)
The SMRmn register is a register that sets an operation mode of channel n. It is also used to select an operation
clock (fMCK), specify whether the serial clock (fSCK) may be input or not, set a start trigger, an operation mode (CSI,
UART, or I2C), and an interrupt source. This register is also used to invert the level of the receive data only in the
UART mode.
Rewriting the SMRmn register is prohibited when the register is in operation (when SEmn = 1). However, the
MDmn0 bit can be rewritten during operation.
The SMRmn register can be set by a 16-bit memory manipulation instruction.
Reset signal generation sets the SMRmn register to 0020H.
Figure 14-7. Format of Serial Mode Register mn (SMRmn) (1/3)
Address: F0110H, F0111H (SMR00) to F0116H, F0117H (SMR03),
After reset: 0020H
R/W
F0150H, F0151H (SMR10) to F0156H, F0157H (SMR13),
F0208H, F0209H (SMR20) , F020AH, F020BH (SMR21)
Symbol
15
14
13
12
11
10
9
8
7
SMRmn
CKS
CCS
0
0
0
0
0
STS
0
mn
mn
CKS
mn
6
5
4
3
SIS
1
0
0
mn0
2
1
0
MD
MD
MD
mn2
mn1
mn0
Selection of operation clock (fMCK) of channel n
mn
0
Operation clock CKm0 set by the SPSm register
1
Operation clock CKm1 set by the SPSm register
Operation clock (fMCK) is used by the edge detector. In addition, depending on the setting of the CCSmn bit and the
higher 7 bits of the SDRmn register, a transfer clock (fTCLK) is generated.
CCS
Selection of transfer clock (fTCLK) of channel n
mn
0
Divided operation clock fMCK specified by the CKSmn bit
1
Clock input fSCK from the SCKp pin (slave transfer in CSI mode)
Transfer clock fTCLK is used for the shift register, communication controller, output controller, interrupt controller, and
error controller. When CCSmn = 0, the division ratio of operation clock (fMCK) is set by the higher 7 bits of the
SDRmn register.
STS
Selection of start trigger source
mn
2
0
Only software trigger is valid (selected for CSI, UART transmission, and simplified I C).
1
Valid edge of the RXDq pin (selected for UART reception)
Transfer is started when the above source is satisfied after 1 is set to the SSm register.
Caution
Be sure to clear bits 13 to 9, 7, 4, and 3 to “0”. Be sure to set bit 5 to “1”.
(Remark is listed on the next page.)
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Figure 14-7. Format of Serial Mode Register mn (SMRmn) (2/3)
Remark
m: Unit number (m = 0 to 2), n: Channel number (n = 0 to 3), p: CSI number (p = 00, 01, 10, 20, 40, 41),
q: UART number (q = 0 to 4), r: IIC number (r = 10, 20)
78K0R/KC3-L, 78K0R/KD3-L, 78K0R/KE3-L:
mn = 00 to 03, p = 00, 01, 10, q = 0, 1,
78K0R/KF3-L μ PD78F1010, 78F1011, 78F1012 :
mn = 00 to 03, 10 to 13, p = 00, 01, 10,
78K0R/KF3-L μ PD78F1027, 78F1028 :
mn = 00 to 03, 10 to 13, 20, 21, p = 00,
78K0R/KG3-L μ PD78F1013, 78F1014 :
mn = 00 to 03, 10 to 13, p = 00, 01, 10,
78K0R/KG3-L μ PD78F1029, 78F1030 :
mn = 00 to 03, 10 to 13, 20, 21, p = 00,
r = 10
20, q = 0 to 3, r = 10, 20
01, 10, 20, 40, 41, q = 0 to 4, r = 10, 20
20, q = 0 to 3, r = 10, 20
01, 10, 20, 40, 41, q = 0 to 4, r = 10, 20
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Figure 14-7. Format of Serial Mode Register mn (SMRmn) (3/3)
Address: F0110H, F0111H (SMR00) to F0116H, F0117H (SMR03),
After reset: 0020H
R/W
F0150H, F0151H (SMR10) to F0156H, F0157H (SMR13),
F0208H, F0209H (SMR20), F020AH, F020BH (SMR21)
Symbol
15
14
13
12
11
10
9
8
7
SMRmn
CKS
CCS
0
0
0
0
0
STS
0
mn
mn
5
4
3
SIS
1
0
0
mn0
mn
SIS
6
2
1
0
MD
MD
MD
mn2
mn1
mn0
Controls inversion of level of receive data of channel n in UART mode
mn0
Falling edge is detected as the start bit.
0
The input communication data is captured as is.
Rising edge is detected as the start bit.
1
The input communication data is inverted and captured.
MD
MD
mn2
mn1
0
0
CSI mode
0
1
UART mode
1
0
Simplified I C mode
1
1
Setting prohibited
Setting of operation mode of channel n
2
MD
Selection of interrupt source of channel n
mn0
0
Transfer end interrupt
1
Buffer empty interrupt
(Occurs when data is transferred from the SDRmn register to the shift register.)
For successive transmission, the next transmit data is written by setting the MDmn0 bit to 1 when SDRmn data has
run out.
Caution
Be sure to clear bits 13 to 9, 7, 4, and 3 to “0”. Be sure to set bit 5 to “1”.
Remark m: Unit number (m = 0 to 2), n : Channel number (n = 0 to 3)
78K0R/KC3-L, 78K0R/KD3-L, 78K0R/KE3-L:
mn = 00 to 03
78K0R/KF3-L μ PD78F1010, 78F1011, 78F1012 : mn = 00 to 03, 10 to 13
78K0R/KF3-L μ PD78F1027, 78F1028 :
mn = 00 to 03, 10 to 13, 20, 21
78K0R/KG3-L μ PD78F1013, 78F1014 :
mn = 00 to 03, 10 to 13
78K0R/KG3-L μ PD78F1029, 78F1030 :
mn = 00 to 03, 10 to 13, 20, 21
(4) Serial communication operation setting register mn (SCRmn)
The SCRmn register is a communication operation setting register of channel n. It is used to set a data
transmission/reception mode, phase of data and clock, whether an error signal is to be masked or not, parity bit,
start bit, stop bit, and data length.
Rewriting the SCRmn register is prohibited when the register is in operation (when SEmn = 1).
The SCRmn register can be set by a 16-bit memory manipulation instruction.
Reset signal generation sets the SCRmn register to 0087H.
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CHAPTER 14 SERIAL ARRAY UNIT
Figure 14-8. Format of Serial Communication Operation Setting Register mn (SCRmn) (1/4)
Address: F0118H, F0119H (SCR00) to F011EH, F011FH (SCR03),
After reset: 0087H
R/W
F0158H, F0159H (SCR10) to F015EH, F015FH (SCR13),
F020CH, F020DH (SCR20), F020EH, F020FH (SCR21)
Symbol
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
SCRmn
TXE
RXE
DAP
CKP
0
EOC
PTC
PTC
DIR
0
SLC
SLC
0
DLS
DLS
DLS
mn
mn
mn
mn
mn
mn1
mn0
mn
mn1
mn0
mn2
mn1
mn0
TXE
RXE
mn
mn
0
0
Setting of operation mode of channel n
Disable communication.
0
1
Reception only
1
0
Transmission only
1
1
Transmission/reception
DAP
CKP
mn
mn
0
0
Selection of data and clock phase in CSI mode
Type
SCKp
1
SOp
D7
D6
D5
D4
D3
D2
D1
D0
D7
D6
D5
D4
D3
D2
D1
D0
SIp input timing
0
1
SCKp
2
SOp
SIp input timing
1
0
SCKp
3
SOp
D7
D6
D5
D4
D3
D2
D1
D0
D7
D6
D5
D4
D3
D2
D1
D0
SIp input timing
1
1
SCKp
4
SOp
SIp input timing
2
Be sure to set DAPmn, CKPmn = 0, 0 in the UART mode and simplified I C mode.
EOC
Selection of masking of error interrupt signal (INTSREx (x = 0 to 3))
mn
0
Masks error interrupt INTSREx (INTSRx is not masked).
1
Enables generation of error interrupt INTSREx (INTSRx is masked if an error occurs).
2
Set EOCmn = 0 in the CSI mode, simplified I C mode, and during UART transmission
Note
.
Set EOCmn = 1 during UART reception.
Note
When using CSI01 not with EOC01 = 0, error interrupt INTSRE0 may be generated.
Caution
Be sure to clear bits 3, 6, and 11 to “0”. Be sure to set bit 2 to “1”.
(Remark is listed on the next page.)
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Figure 14-8. Format of Serial Communication Operation Setting Register mn (SCRmn) (2/4)
Remark
m: Unit number (m = 0 to 2), n: Channel number (n = 0 to 3), p: CSI number (p = 00, 01, 10, 20, 40, 41)
78K0R/KC3-L, 78K0R/KD3-L, 78K0R/KE3-L:
mn = 00 to 03, p = 00, 01, 10
78K0R/KF3-L μ PD78F1010, 78F1011, 78F1012 :
mn = 00 to 03, 10 to 13, p = 00, 01, 10,
78K0R/KF3-L μ PD78F1027, 78F1028 :
mn = 00 to 03, 10 to 13, 20, 21, p = 00,
78K0R/KG3-L μ PD78F1013, 78F1014 :
mn = 00 to 03, 10 to 13, p = 00, 01, 10,
78K0R/KG3-L μ PD78F1029, 78F1030 :
mn = 00 to 03, 10 to 13, 20, 21, p = 00,
20
01, 10, 20, 40, 41
20
01, 10, 20, 40, 41
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CHAPTER 14 SERIAL ARRAY UNIT
Figure 14-8. Format of Serial Communication Operation Setting Register mn (SCRmn) (3/4)
Address: F0118H, F0119H (SCR00) to F011EH, F011FH (SCR03),
After reset: 0087H
R/W
F0158H, F0159H (SCR10) to F015EH, F015FH (SCR13),
F020CH, F020DH (SCR20), F020EH, F020FH (SCR21)
Symbol
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
SCRmn
TXE
RXE
DAP
CKP
0
EOC
PTC
PTC
DIR
0
SLC
SLC
0
DLS
DLS
DLS
mn
mn
mn
mn
mn
mn1
mn0
mn
mn1
mn0
mn2
mn1
mn0
PTC
PTC
mn1
mn0
Setting of parity bit in UART mode
Transmission
Reception
0
0
Does not output the parity bit.
0
1
Outputs 0 parity
Receives without parity
1
0
Outputs even parity.
Judged as even parity.
1
1
Outputs odd parity.
Judges as odd parity.
Note
.
No parity judgment
2
Be sure to set PTCmn1, PTCmn0 = 0, 0 in the CSI mode and simplified I C mode.
DIR
Selection of data transfer sequence in CSI and UART modes
mn
0
Inputs/outputs data with MSB first.
1
Inputs/outputs data with LSB first.
2
Be sure to clear DIRmn = 0 in the simplified I C mode.
SLC
SLC
mn1
mn0
0
0
No stop bit
0
1
Stop bit length = 1 bit
1
0
Stop bit length = 2 bits
1
1
Setting prohibited
Setting of stop bit in UART mode
When the transfer end interrupt is selected, the interrupt is generated when all stop bits have been completely
transferred.
2
Set 1 bit (SLCmn1, SLCmn0 = 0, 1) during UART reception and in the simplified I C mode.
Set no stop bit (SLCmn1, SLCmn0 = 0, 0) in the CSI mode.
Note 0 is always added regardless of the data contents.
Caution
Be sure to clear bits 3, 6, and 11 to “0”. Be sure to set bit 2 to “1”.
Remark
m: Unit number (m = 0 to 2), n: Channel number (n = 0 to 3)
78K0R/KC3-L, 78K0R/KD3-L, 78K0R/KE3-L:
mn = 00 to 03
78K0R/KF3-L μ PD78F1010, 78F1011, 78F1012 :
mn = 00 to 03, 10 to 13
78K0R/KF3-L μ PD78F1027, 78F1028 :
mn = 00 to 03, 10 to 13, 20, 21
78K0R/KG3-L μ PD78F1013, 78F1014 :
mn = 00 to 03, 10 to 13
78K0R/KG3-L μ PD78F1029, 78F1030 :
mn = 00 to 03, 10 to 13, 20, 21
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CHAPTER 14 SERIAL ARRAY UNIT
Figure 14-8. Format of Serial Communication Operation Setting Register mn (SCRmn) (4/4)
Address: F0118H, F0119H (SCR00) to F011EH, F011FH (SCR03),
After reset: 0087H
R/W
F0158H, F0159H (SCR10) to F015EH, F015FH (SCR13),
F020CH, F020DH (SCR20), F020EH, F020FH (SCR21)
Symbol
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
SCRmn
TXE
RXE
DAP
CKP
0
EOC
PTC
PTC
DIR
0
SLC
SLC
0
DLS
DLS
DLS
mn
mn
mn
mn
mn
mn1
mn0
mn
mn1
mn0
mn2
mn1
mn0
DLS
DLS
DLS
mn2
mn1
mn0
1
0
0
Setting of data length in CSI and UART modes
5-bit data length (stored in bits 0 to 4 of the SDRmn register)
(settable in UART mode only)
1
1
0
7-bit data length (stored in bits 0 to 6 of the SDRmn register)
1
1
1
8-bit data length (stored in bits 0 to 7 of the SDRmn register)
Other than above
Setting prohibited
2
Be sure to set DLSmn0 = 1 in the simplified I C mode.
Caution
Be sure to clear bits 3, 6, and 11 to “0”. Be sure to set bit 2 to “1”.
Remark
m: Unit number (m = 0 to 2), n: Channel number (n = 0 to 3)
78K0R/KC3-L, 78K0R/KD3-L, 78K0R/KE3-L:
mn = 00 to 03
78K0R/KF3-L μ PD78F1010, 78F1011, 78F1012 :
mn = 00 to 03, 10 to 13
78K0R/KF3-L μ PD78F1027, 78F1028 :
mn = 00 to 03, 10 to 13, 20, 21
78K0R/KG3-L μ PD78F1013, 78F1014 :
mn = 00 to 03, 10 to 13
78K0R/KG3-L μ PD78F1029, 78F1030 :
mn = 00 to 03, 10 to 13, 20, 21
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CHAPTER 14 SERIAL ARRAY UNIT
(5) Higher 7 bits of the serial data register mn (SDRmn)
The SDRmn register is the transmit/receive data register (16 bits) of channel n.
Bits 7 to 0 function as a
transmit/receive buffer register, and bits 15 to 9 are used as a register that sets the division ratio of the operation
clock (fMCK).
If the CCSmn bit of serial mode register mn (SMRmn) is cleared to 0, the clock set by dividing the operating clock
by the higher 7 bits of the SDRmn register is used as the transfer clock.
The lower 8 bits of the SDRmn register function as a transmit/receive buffer register. During reception, the parallel
data converted by the shift register is stored in the lower 8 bits, and during transmission, the data to be transmitted
to the shift register is set to the lower 8 bits.
The SDRmn register can be read or written in 16-bit units.
However, the higher 7 bits can be written or read only when the operation is stopped (SEmn = 0). During operation
(SEmn = 1), a value is written only to the lower 8 bits of the SDRmn register. When the SDRmn register is read
during operation, 0 is always read.
Reset signal generation clears the SDRmn register to 0000H.
Figure 14-9. Format of Serial Data Register mn (SDRmn) (1/2)
Address: FFF10H, FFF11H (SDR00), FFF12H, FFF13H (SDR01),
After reset: 0000H
R/W
FFF44H, FFF45H (SDR02), FFF46H, FFF47H (SDR03),
FFF48H, FFF49H (SDR10), FFF4AH, FFF4BH (SDR11),
FFF14H, FFF15H (SDR12), FFF16H, FFF17H (SDR13),
FFF4CH, FFF4DH (SDR20), FFF4EH, FFF4FH (SDR21)
FFF11H (SDR00)
Symbol
15
14
13
12
11
10
9
SDRmn
FFF10H (SDR00)
8
7
6
5
4
3
2
1
0
0
SDRmn[15:9]
Transfer clock setting by dividing the operating clock (fMCK)
0
0
0
0
0
0
0
fMCK/2
0
0
0
0
0
0
1
fMCK/4
0
0
0
0
0
1
0
fMCK/6
0
0
0
0
0
1
1
fMCK/8
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
1
1
1
1
1
1
0
fMCK/254
1
1
1
1
1
1
1
fMCK/256
Cautions 1. Be sure to clear bit 8 to “0”.
2. Setting SDRmn[15:9] = (0000000B, 0000001B) is prohibited when UART is used.
3. Setting SDRmn[15:9] = 0000000B is prohibited when simplified I2C is used. Set SDRmn[15:9]
to 0000001B or greater.
4. Do not write eight bits to the lower eight bits if operation is stopped (SEmn = 0). (If these bits
are written to, the higher seven bits are cleared to 0.)
(Remarks are listed on the next page.)
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Figure 14-9. Format of Serial Data Register mn (SDRmn) (2/2)
Remarks 1. For the function of the lower 8 bits of the SDRmn register, see 14.2 Configuration of Serial Array Unit.
2. m: Unit number (m = 0 to 2), n: Channel number (n = 0 to 3)
78K0R/KC3-L, 78K0R/KD3-L, 78K0R/KE3-L:
mn = 00 to 03
78K0R/KF3-L μ PD78F1010, 78F1011, 78F1012 :
mn = 00 to 03, 10 to 13
78K0R/KF3-L μ PD78F1027, 78F1028 :
mn = 00 to 03, 10 to 13, 20, 21
78K0R/KG3-L μ PD78F1013, 78F1014 :
mn = 00 to 03, 10 to 13
78K0R/KG3-L μ PD78F1029, 78F1030 :
mn = 00 to 03, 10 to 13, 20, 21
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CHAPTER 14 SERIAL ARRAY UNIT
(6) Serial flag clear trigger register mn (SIRmn)
The SIRmn register is a trigger register that is used to clear each error flag of channel n.
When each bit (FECTmn, PECTmn, OVCTmn) of this register is set to 1, the corresponding bit (FEFmn, PEFmn,
OVFmn) of serial status register mn is cleared to 0. Because the SIRmn register is a trigger register, it is cleared
immediately when the corresponding bit of the SSRmn register is cleared.
The SIRmn register can be set by a 16-bit memory manipulation instruction.
The lower 8 bits of the SIRmn register can be set with an 8-bit memory manipulation instruction with SIRmnL.
Reset signal generation clears the SIRmn register to 0000H.
Figure 14-10. Format of Serial Flag Clear Trigger Register mn (SIRmn)
Address: F0108H, F0109H (SIR00) to F010EH, F010FH (SIR03),
After reset: 0000H
R/W
F0148H, F0149H (SIR10) to F014EH, F014FH (SIR13),
F0204H, F0205H (SIR20) , F0206H, F0207H (SIR21)
Symbol
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
SIRmn
0
0
0
0
0
0
0
0
0
0
0
0
0
FEC
PEC
OVC
Tmn
Tmn
Tmn
FEC
Clear trigger of framing error of channel n
Tmn
0
Not cleared
1
Clears the FEFmn bit of the SSRmn register to 0.
PEC
Clear trigger of parity error flag of channel n
Tmn
0
Not cleared
1
Clears the PEFmn bit of the SSRmn register to 0.
OVC
Clear trigger of overrun error flag of channel n
Tmn
Caution
0
Not cleared
1
Clears the OVFmn bit of the SSRmn register to 0.
Be sure to clear bits 15 to 3 to “0”.
Remarks 1. m: Unit number (m = 0 to 2), n: Channel number (n = 0 to 3)
78K0R/KC3-L, 78K0R/KD3-L, 78K0R/KE3-L:
mn = 00 to 03
78K0R/KF3-L μ PD78F1010, 78F1011, 78F1012 :
mn = 00 to 03, 10 to 13
78K0R/KF3-L μ PD78F1027, 78F1028 :
mn = 00 to 03, 10 to 13, 20, 21
78K0R/KG3-L μ PD78F1013, 78F1014 :
mn = 00 to 03, 10 to 13
78K0R/KG3-L μ PD78F1029, 78F1030 :
mn = 00 to 03, 10 to 13, 20, 21
2. When the SIRmn register is read, 0000H is always read.
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CHAPTER 14 SERIAL ARRAY UNIT
(7) Serial status register mn (SSRmn)
The SSRmn register is a register that indicates the communication status and error occurrence status of channel n.
The errors indicated by this register are a framing error, parity error, and overrun error.
The SSRmn register can be read by a 16-bit memory manipulation instruction.
The lower 8 bits of the SSRmn register can be set with an 8-bit memory manipulation instruction with SSRmnL.
Reset signal generation clears the SSRmn register to 0000H.
Figure 14-11. Format of Serial Status Register mn (SSRmn) (1/2)
Address: F0100H, F0101H (SSR00) to F0106H, F0107H (SSR03),
F0140H, F0141H (SSR10) to F0146H, F0147H (SSR13),
F0200H, F0201H (SSR20), F0202H, F0203H (SSR21)
After reset: 0000H
R
Symbol
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
SSRmn
0
0
0
0
0
0
0
0
0
TSF
BFF
0
0
FEF
PEF
OVF
mn
mn
mn
mn
mn
TSF
Communication status indication flag of channel n
mn
0
Communication is stopped or suspended.
1
Communication is in progress.
<Clear conditions>
• The STmn bit of the STm register is set to 1 (communication is stopped) or the SSmn bit of the SSm register is
set to 1 (communication is suspended).
• Communication ends.
<Set condition>
• Communication starts.
BFF
Buffer register status indication flag of channel n
mn
0
Valid data is not stored in the SDRmn register.
1
Valid data is stored in the SDRmn register.
<Clear conditions>
• Transferring transmit data from the SDRmn register to the shift register ends during transmission.
• Reading receive data from the SDRmn register ends during reception.
• The STmn bit of the STm register is set to 1 (communication is stopped) or the SSmn bit of the SSm register is set
to 1 (communication is enabled).
<Set conditions>
• Transmit data is written to the SDRmn register while the TXEmn bit of the SCRmn register is set to 1
(transmission or transmission and reception mode in each communication mode).
• Receive data is stored in the SDRmn register while the RXEmn bit of the SCRmn register is set to 1 (reception or
transmission and reception mode in each communication mode).
• A reception error occurs.
Caution
If data is written to the SDRmn register when BFFmn = 1, the transmit/receive data stored in the
register is discarded and an overrun error (OVEmn = 1) is detected.
Remark m: Unit number (m = 0 to 2), n: Channel number (n = 0 to 3)
78K0R/KC3-L, 78K0R/KD3-L, 78K0R/KE3-L:
mn = 00 to 03
78K0R/KF3-L μ PD78F1010, 78F1011, 78F1012 :
mn = 00 to 03, 10 to 13
78K0R/KF3-L μ PD78F1027, 78F1028 :
mn = 00 to 03, 10 to 13, 20, 21
78K0R/KG3-L μ PD78F1013, 78F1014 :
mn = 00 to 03, 10 to 13
78K0R/KG3-L μ PD78F1029, 78F1030 :
mn = 00 to 03, 10 to 13, 20, 21
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CHAPTER 14 SERIAL ARRAY UNIT
Figure 14-11. Format of Serial Status Register mn (SSRmn) (2/2)
Address: F0100H, F0101H (SSR00) to F0106H, F0107H (SSR03),
After reset: 0000H
R
F0140H, F0141H (SSR10) to F0146H, F0147H (SSR13),
F0200H, F0201H (SSR20), F0202H, F0203H (SSR21)
Symbol
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
SSRmn
0
0
0
0
0
0
0
0
0
TSF
BFF
0
0
FEF
PEF
OVF
mn
mn
mn
mn
mn
FEF
Framing error detection flag of channel n
mn
0
No error occurs.
1
An error occurs (during UART reception).
<Clear condition>
• 1 is written to the FECTmn bit of the SIRmn register.
<Set condition>
• A stop bit is not detected when UART reception ends.
PEF
Parity error detection flag of channel n
mn
0
No error occurs.
1
An error occurs (during UART reception) or ACK is not detected (during I C transmission).
2
<Clear condition>
• 1 is written to the PECTmn bit of the SIRmn register.
<Set condition>
• The parity of the transmit data and the parity bit do not match when UART reception ends (parity error).
• No ACK signal is returned from the slave channel at the ACK reception timing during I C transmission (ACK is
2
not detected).
OVF
Overrun error detection flag of channel n
mn
0
No error occurs.
1
An error occurs
<Clear condition>
• 1 is written to the OVCTmn bit of the SIRmn register.
<Set condition>
• Even though receive data is stored in the SDRmn register, that data is not read and transmit data or the next
receive data is written while the RXEmn bit of the SCRmn register is set to 1 (reception or transmission and
reception mode in each communication mode).
• Transmit data is not ready for slave transmission or transmission and reception in CSI mode.
Remark m: Unit number (m = 0 to 2), n: Channel number (n = 0 to 3)
78K0R/KC3-L, 78K0R/KD3-L, 78K0R/KE3-L:
mn = 00 to 03
78K0R/KF3-L μ PD78F1010, 78F1011, 78F1012 :
mn = 00 to 03, 10 to 13
78K0R/KF3-L μ PD78F1027, 78F1028 :
mn = 00 to 03, 10 to 13, 20, 21
78K0R/KG3-L μ PD78F1013, 78F1014 :
mn = 00 to 03, 10 to 13
78K0R/KG3-L μ PD78F1029, 78F1030 :
mn = 00 to 03, 10 to 13, 20, 21
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CHAPTER 14 SERIAL ARRAY UNIT
(8) Serial channel start register m (SSm)
The SSm register is a trigger register that is used to enable starting communication/count by each channel.
When 1 is written a bit of this register (SSmn), the corresponding bit (SEmn) of serial channel enable status
register m (SEm) is set to 1 (Operation is enabled). Because the SSmn bit is a trigger bit, it is cleared immediately
when SEmn = 1.
The SSm register can be set by a 16-bit memory manipulation instruction.
The lower 8 bits of the SSm register can be set with an 1-bit or 8-bit memory manipulation instruction with SSmL.
Reset signal generation clears the SSm register to 0000H.
Figure 14-12. Format of Serial Channel Start Register m (SSm)
Address: F0122H, F0123H (SS0), F0162H, F0163H (SS1),
After reset: 0000H
R/W
F0212H, F0213H (SS2)
Symbol
15
14
13
12
11
10
9
8
7
6
5
4
SSm
0
0
0
0
0
0
0
0
0
0
0
0
3
SSm
3
SSmn
Note 1
2
1
0
SSm
SSm
SSm
1
0
2
Note 1
Operation start trigger of channel n
0
No trigger operation
1
Sets the SEmn bit to 1 and enters the communication wait status
Note 2
.
Notes 1. Those bits are invalid while operating serial allay unit 2.
2.
Caution
If a communication operation is already under execution, the operation is stopped.
Be sure to clear bits 15 to 4 to “0”.
Remarks 1. m: Unit number (m = 0 to 2), n: Channel number (n = 0 to 3)
78K0R/KC3-L, 78K0R/KD3-L, 78K0R/KE3-L:
mn = 00 to 03
78K0R/KF3-L μ PD78F1010, 78F1011, 78F1012 : mn = 00 to 03, 10 to 13
78K0R/KF3-L μ PD78F1027, 78F1028 :
mn = 00 to 03, 10 to 13, 20, 21
78K0R/KG3-L μ PD78F1013, 78F1014 :
mn = 00 to 03, 10 to 13
78K0R/KG3-L μ PD78F1029, 78F1030 :
mn = 00 to 03, 10 to 13, 20, 21
2. When the SSm register is read, 0000H is always read.
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CHAPTER 14 SERIAL ARRAY UNIT
(9) Serial channel stop register m (STm)
The STm register is a trigger register that is used to enable stopping communication/count by each channel.
When 1 is written a bit of this register (STmn), the corresponding bit (SEmn) of serial channel enable status
register m (SEm) is cleared to 0 (operation is stopped). Because the STmn bit is a trigger bit, it is cleared
immediately when SEmn = 0.
The STm register can set written by a 16-bit memory manipulation instruction.
The lower 8 bits of the STm register can be set with an 1-bit or 8-bit memory manipulation instruction with STmL.
Reset signal generation clears the STm register to 0000H.
Figure 14-13. Format of Serial Channel Stop Register m (STm)
Address: F0124H, F0125H (ST0), F0164H, F0165H (ST1)
After reset: 0000H
R/W
F0214H, F0215H (ST2)
Symbol
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
STm
0
0
0
0
0
0
0
0
0
0
0
0
STm
STm
STm
STm
1
0
3
STm
Note 1
Note 1
2
Operation stop trigger of channel n
n
0
No trigger operation
1
Clears the SEmn bit to 0 and stops the communication operation
Note 2
.
Notes 1. Those bits are invalid while operating serial allay unit 2.
2. Communication stops while holding the value of the control register and shift register, and the status of
the serial clock I/O pin, serial data output pin, and each error flag (FEFmn: framing error flag, PEFmn:
parity error flag, OVFmn: overrun error flag).
Caution
Be sure to clear bits 15 to 4 to “0”.
Remarks 1. m: Unit number (m = 0 to 2), n: Channel number (n = 0 to 3)
78K0R/KC3-L, 78K0R/KD3-L, 78K0R/KE3-L:
mn = 00 to 03
78K0R/KF3-L μ PD78F1010, 78F1011, 78F1012 : mn = 00 to 03, 10 to 13
78K0R/KF3-L μ PD78F1027, 78F1028 :
mn = 00 to 03, 10 to 13, 20, 21
78K0R/KG3-L μ PD78F1013, 78F1014 :
mn = 00 to 03, 10 to 13
78K0R/KG3-L μ PD78F1029, 78F1030 :
mn = 00 to 03, 10 to 13, 20, 21
2. When the STm register is read, 0000H is always read.
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CHAPTER 14 SERIAL ARRAY UNIT
(10) Serial channel enable status register m (SEm)
The SEm register indicates whether data transmission/reception operation of each channel is enabled or stopped.
When 1 is written a bit of serial channel start register m (SSm), the corresponding bit of this register is set to 1.
When 1 is written a bit of serial channel stop register m (STm), the corresponding bit is cleared to 0.
Channel n that is enabled to operate cannot rewrite by software the value of the CKOmn bit (serial clock output of
channel n) of serial output register m (SOm) to be described below, and a value reflected by a communication
operation is output from the serial clock pin.
Channel n that stops operation can set the value of the CKOmn bit of the SOm register by software and output its
value from the serial clock pin. In this way, any waveform, such as that of a start condition/stop condition, can be
created by software.
The SEm register can be read by a 16-bit memory manipulation instruction.
The lower 8 bits of the SEm register can be set with an 1-bit or 8-bit memory manipulation instruction with SEmL.
Reset signal generation clears the SEm register to 0000H.
Figure 14-14. Format of Serial Channel Enable Status Register m (SEm)
Address: F0120H, F0121H (SE0), F0160H, F0161H (SE1),
After reset: 0000H
R
F0210H, F0211H (SE2)
Symbol
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
SEm
0
0
0
0
0
0
0
0
0
0
0
0
SEm
SEm
SEm
SEm
1
0
3
SEm
Note
2
Note
Indication of operation enable/stop status of channel n
n
Note
0
Operation stops
1
Operation is enabled.
Those bits are invalid while operating serial allay unit 2.
Remark m: Unit number (m = 0 to 2), n: Channel number (n = 0 to 3)
78K0R/KC3-L, 78K0R/KD3-L, 78K0R/KE3-L:
mn = 00 to 03
78K0R/KF3-L μ PD78F1010, 78F1011, 78F1012 :
mn = 00 to 03, 10 to 13
78K0R/KF3-L μ PD78F1027, 78F1028 :
mn = 00 to 03, 10 to 13, 20, 21
78K0R/KG3-L μ PD78F1013, 78F1014 :
mn = 00 to 03, 10 to 13
78K0R/KG3-L μ PD78F1029, 78F1030 :
mn = 00 to 03, 10 to 13, 20, 21
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CHAPTER 14 SERIAL ARRAY UNIT
(11) Serial output enable register m (SOEm)
The SOEm register is a register that is used to enable or stop output of the serial communication operation of each
channel.
Channel n that enables serial output cannot rewrite by software the value of the SOmn bit of serial output register
m (SOm) to be described below, and a value reflected by a communication operation is output from the serial data
output pin.
For channel n, whose serial output is stopped, the SOmn bit value of the SOm register can be set by software, and
that value can be output from the serial data output pin. In this way, any waveform of the start condition and stop
condition can be created by software.
The SOEm register can be set by a 16-bit memory manipulation instruction.
The lower 8 bits of the SOEm register can be set with an 1-bit or 8-bit memory manipulation instruction with
SOEmL.
Reset signal generation clears the SOEm register to 0000H.
Figure 14-15. Format of Serial Output Enable Register m (SOEm)
Address: F012AH, F012BH
After reset: 0000H
R/W
Symbol
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
SOE0
0
0
0
0
0
0
0
0
0
0
0
0
0
SOE
SOE
SOE
02
01
00
Address: F016AH, F016BH
After reset: 0000H
R/W
Symbol
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
SOE1
0
0
0
0
0
0
0
0
0
0
0
0
0
SOE
0
SOE
12
Address: F021AH, F021BH
Symbol
SOE2
After reset: 0000H
10
R/W
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
SOE
SOE
21
20
Note
SOE
Serial output enable/stop of channel n
mn
Note
0
Stops output by serial communication operation.
1
Enables output by serial communication operation.
SOE2 register is only mounted in the 78K0R/KF3-L (μ PD78F1027, 78F1028) and 78K0R/KG3-L (μ
PD78F1029, 78F1030).
Caution
Be sure to clear bits 15 to 3 of the SOE0 register, bits 1 and 15 to 3 of the SOE1 register, and bits
15 to 2 of the SOE2 registers to “0”.
Remark m: Unit number (m = 0 to 2), n: Channel number (n = 0 to 2)
78K0R/KC3-L, 78K0R/KD3-L, 78K0R/KE3-L:
mn = 00 to 02
78K0R/KF3-L μ PD78F1010, 78F1011, 78F1012 :
mn = 00 to 02, 10, 12
78K0R/KF3-L μ PD78F1027, 78F1028 :
mn = 00 to 02, 10, 12, 20, 21
78K0R/KG3-L μ PD78F1013, 78F1014 :
mn = 00 to 02, 10, 12
78K0R/KG3-L μ PD78F1029, 78F1030 :
mn = 00 to 02, 10, 12, 20, 21
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CHAPTER 14 SERIAL ARRAY UNIT
(12) Serial output register m (SOm)
The SOm register is a buffer register for serial output of each channel.
The value of the SOmn bit of this register is output from the serial data output pin of channel n.
The value of the CKOmn bit of this register is output from the serial clock output pin of channel n.
The SOmn bit of this register can be rewritten by software only when serial output is disabled (SOEmn = 0). When
serial output is enabled (SOEmn = 1), rewriting by software is ignored, and the value of the register can be
changed only by a serial communication operation.
The CKOmn bit of this register can be rewritten by software only when the channel operation is stopped (SEmn =
0). While channel operation is enabled (SEmn = 1), rewriting by software is ignored, and the value of the CKOmn
bit can be changed only by a serial communication operation.
When using the following pins as port function pins, set the corresponding CKOmn and SOmn bits to “1”.
78K0R/KC3-L, 78K0R/KD3-L, 78K0R/KE3-L:
P30/SO10/TxD1,
P31/SI10/RxD1/SDA10/INTP1,
P32/SCK10/SCL10/INTP2,
P70/KR0/SO01/INTP4,
P72/KR2/SCK01/INTP6, P73/KR3/SO00/TxD0, P75/KR5/SCK00
78K0R/KF3-L, 78K0R/KG3-L:
P02/SO10/TxD1, P03/SI10/SDA10/RxD1, P04/SCK10/SCL10, P10/SCK00, P12/SO00/TxD0, P13/TxD3,
P43/SCK01, P45/SO01, P142/SCK20/SCL20, P143/SI20/SDA20/RxD2, P144/SO20/TxD2
μ PD78F1027, 78F1028:
P02/SO10/TxD1, P03/SI10/SDA10/RxD1, P04/SCK10/SCL10, P10/SCK00, P12/SO00/TxD0, P13/TxD3,
P43/SCK01, P45/SO01, P50/SCK40/INTP1, P52/SO40/TxD4/TO00, P53/SCK41/TI00,
P55/SO41/PCLBUZ1/INTP7, P142/SCK20/SCL20, P143/SI20/SDA20/RxD2, P144/SO20/TxD2
μ PD78F1029, 78F1030:
P02/SO10/TxD1, P03/SI10/SDA10/RxD1, P04/SCK10/SCL10, P10/SCK00, P12/SO00/TxD0, P13/TxD3,
P43/SCK01,
P45/SO01,
P50/SCK40,
P52/SO40/TxD4,
P53/SCK41,
P55/SO41,
P142/SCK20/SCL20,
P143/SI20/SDA20/RxD2, P144/SO20/TxD2
The SOm register can be set by a 16-bit memory manipulation instruction.
Reset signal generation clears the SOm register to 0F0FH.
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CHAPTER 14 SERIAL ARRAY UNIT
Figure 14-16. Format of Serial Output Register m (SOm)
Address: F0128H, F0129H
After reset: 0F0FH
R/W
Symbol
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
SO0
0
0
0
0
1
CKO
CKO
CKO
0
0
0
0
1
SO
SO
SO
02
01
00
02
01
00
Address: F0168H, F0169H
After reset: 0F0FH
R/W
Symbol
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
SO1
0
0
0
0
1
1
1
CKO
0
0
0
0
1
SO
1
SO
10
Address: F0218H, F0219H
Symbol
SO2
After reset: 0303H
12
10
R/W
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
0
0
0
0
1
1
CKO
CKO
0
0
0
0
1
1
SO
SO
21
20
21
20
Note
CKO
Serial clock output of channel n
mn
0
Serial clock output value is “0”.
1
Serial clock output value is “1”.
SO
Serial data output of channel n
mn
Note
0
Serial data output value is “0”.
1
Serial data output value is “1”.
SO2 register is only mounted in the 78K0R/KF3-L (μ PD78F1027, 78F1028) and 78K0R/KG3-L (μ
PD78F1029, 78F1030).
Caution
Be sure to set bits 11 and 3 of the SO0 register, bits 11 to 9, 3, and 1 of the SO1 register, and bits
11, 10, 3, and 2 of the SO2 register to “1”. And be sure to clear bits 15 to 12 and 7 to 4 of the
SOm register to “0”.
Remark m: Unit number (m = 0 to 2), n: Channel number (n = 0 to 2)
78K0R/KC3-L, 78K0R/KD3-L, 78K0R/KE3-L:
mn = 00 to 02
78K0R/KF3-L (μ PD78F1010, 78F1011, 78F1012) :
mn = 00 to 02, 10, 12
78K0R/KF3-L (μ PD78F1027, 78F1028) :
mn = 00 to 02, 10, 12, 20, 21
78K0R/KG3-L (μ PD78F1013, 78F1014) :
mn = 00 to 02, 10, 12
78K0R/KG3-L (μ PD78F1029, 78F1030) :
mn = 00 to 02, 10, 12, 20, 21
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CHAPTER 14 SERIAL ARRAY UNIT
(13) Serial output level register m (SOLm)
The SOLm register is a register that is used to set inversion of the data output level of each channel.
2
This register can be set only in the UART mode. Be sure to set 0000H in the CSI mode and simplifies I C mode.
Inverting channel n by using this register is reflected on pin output only when serial output is enabled (SOEmn =
1). When serial output is disabled (SOEmn = 0), the value of the SOmn bit is output as is.
Rewriting the SOLm register is prohibited when the register is in operation (when SEmn = 1).
The SOLm register can be set by a 16-bit memory manipulation instruction.
The lower 8 bits of the SOLm register can be set with an 8-bit memory manipulation instruction with SOLmL.
Reset signal generation clears the SOLm register to 0000H.
Figure 14-17. Format of Serial Output Level Register m (SOLm)
Address: F0134H, F0135H
After reset: 0000H
R/W
Symbol
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
SOL0
0
0
0
0
0
0
0
0
0
0
0
0
0
SOL
0
SOL
02
Address: F0174H, F0175H
After reset: 0000H
00
R/W
Symbol
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
SOL1
0
0
0
0
0
0
0
0
0
0
0
0
0
SOL
0
SOL
12
Address: F0220H, F0221H
Symbol
SOL2
After reset: 0000H
10
R/W
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
SOL
Note
20
SOL
Selects inversion of the level of the transmit data of channel n in UART mode
mn
Note
0
Communication data is output as is.
1
Communication data is inverted and output.
SOL2 register is only mounted in the 78K0R/KF3-L (μ PD78F1027, 78F1028) and 78K0R/KG3-L (μ
PD78F1029, 78F1030).
Caution
Be sure to clear bits 15 to 3, and 1 of the SOL0 and SOL1 registers, bits 15 to 1 of the SOL2
register to “0”.
Remark m: Unit number (m = 0 to 2), n: Channel number (n = 0 to 2)
78K0R/KC3-L, 78K0R/KD3-L, 78K0R/KE3-L:
mn = 00 to 02
78K0R/KF3-L (μ PD78F1010, 78F1011, 78F1012) :
mn = 00 to 02, 10, 12
78K0R/KF3-L (μ PD78F1027, 78F1028) :
mn = 00 to 02, 10, 12, 20
78K0R/KG3-L (μ PD78F1013, 78F1014) :
mn = 00 to 02, 10, 12
78K0R/KG3-L (μ PD78F1029, 78F1030) :
mn = 00 to 02, 10, 12, 20
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CHAPTER 14 SERIAL ARRAY UNIT
(14) Input switch control register (ISC)
The ISC1 and ISC0 bits of the ISC register are used to realize a LIN-bus communication operation by UARTk in
coordination with an external interrupt and the timer array unit 0.
When bit 0 is set to 1, the input signal of the serial data input (RXDk) pin is selected as an external interrupt
(INTP0) that can be used to detect a wakeup signal.
When bit 1 is set to 1, the input signal of the serial data input (RXDk) pin is selected as a timer input, so that wake
up signal can be detected, the low width of the sync break field, and the pulse width of the sync field can be
measured by the timer.
The ISC2 bit is set to select the P52/SLTI/SLTO pin as the timer I/O pin of timer channels 0 and 1 (78K0R/KC3-L
(44-pin, 48-pin), 78K0R/KD3-L, 78K0R/KE3-L only).
The ISC register can be set by a 1-bit or 8-bit memory manipulation instruction.
Reset signal generation clears the ISC register to 00H.
Figure 14-18. Format of Input Switch Control Register (ISC)
Address: FFF3CH
Symbol
After reset: 00H
7
ISC
0
ISC2
R/W
6
5
0
4
0
Note 1
3
0
0
2
ISC2
Note 1
0
ISC1
ISC0
Selecting P52/SLTI/SLTO Pin as Timer I/O Pin
Channel 0
Input pin
0
P00/TI00
1
Other than
1
Note 2
P52/SLTI
Channel 1
Output pin
P01/TO00
Note 2
P52/SLTO
Input pin
Output pin
P52/SLTI
P52/SLTO
−
−
Setting prohibited
the above
ISC1
Switching channel 7 input of timer array unit 0
0
Uses the input signal of the TI07 pin as a timer input (normal operation).
1
Input signal of the RXDk pin is used as timer input (detects the wakeup signal and measures the low
width of the sync break field and the pulse width of the sync field).
ISC0
Switching external interrupt (INTP0) input
0
Uses the input signal of the INTP0 pin as an external interrupt (normal operation).
1
Uses the input signal of the RXDk pin as an external interrupt (detects the wakeup signal).
Notes 1. 78K0R/KC3-L (44-pin, 48-pin), 78K0R/KD3-L, 78K0R/KE3-L only.
2. 78K0R/KD3-L and 78K0R/KE3-L only. Only the P52/SLTI/SLTO pin can be assigned to channels 0 and
1 in the 78K0R/KC3-L (44-pin, 48-pin).
Caution
Be sure to clear bits 7 to 3 to “0” in the 78K0R/KC3-L (44-pin, 48-pin), 78K0R/KD3-L, and
78K0R/KE3-L. Be sure to clear bits 7 to 2 to “0” in the 78K0R/KC3-L (40-pin).
Be sure to clear bits 7 to 2 to “0” in the 78K0R/KF3-L and 78K0R/KG3-L.
Remark 78K0R/KC3-L, 78K0R/KD3-L, 78K0R/KE3-L: k = 0 (RxD0)
78K0R/KF3-L, 78K0R/KG3-L:
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CHAPTER 14 SERIAL ARRAY UNIT
(15) Noise filter enable register 0 (NFEN0)
The NFEN0 register is used to set whether the noise filter can be used for the input signal from the serial data
input pin to each channel.
2
Disable the noise filter of the pin used for CSI or simplified I C communication, by clearing the corresponding bit of
this register to 0.
Enable the noise filter of the pin used for UART communication, by setting the corresponding bit of this register to
1.
When the noise filter is enabled, CPU/ peripheral hardware clock (fCLK) is synchronized with 2-clock match
detection.
The NFEN0 register can be set by a 1-bit or 8-bit memory manipulation instruction.
Reset signal generation clears the NFEN0 register to 00H.
Figure 14-19. Format of Noise Filter Enable Register 0 (NFEN0) (1/2)
Address: F0060H
Symbol
After reset: 00H
7
NFEN0
R/W
6
0
5
SNFEN30
Note 1
SNFEN40
4
0
SNFEN20
3
Note 1
0
2
SNFEN10
1
SNFEN40
Use of noise filter of RXD4 pin (RXD4/SI40/INTP2/P51
0
Noise filter OFF
1
Noise filter ON
0
Note 2
SNFEN00
Note 2
)
Set SNFEN40 to 1 to use the RXD4 pin.
Clear SNFEN40 to 0 to use the other than RxD4 pin.
SNFEN30
Note 1
Use of noise filter of RXD3 pin (RXD3/P14)
0
Noise filter OFF
1
Noise filter ON
Set SNFEN30 to 1 to use the RXD3 pin.
Clear SNFEN30 to 0 to use the other than RxD3 pin.
SNFEN20
Note 1
Use of noise filter of RXD2 pin (RXD2/SDA20/SI20/P143)
0
Noise filter OFF
1
Noise filter ON
Set SNFEN20 to 1 to use the RXD2 pin.
Clear SNFEN20 to 0 to use the other than RxD2 pin.
Use of noise filter of RXD1 pin
SNFEN10
78K0R/KC3-L, 78K0R/KD3-L, 78K0R/KE3-L: RxD1/SDA10/SI10/INTP1/P31 pin
78K0R/KF3-L, 78K0R/KG3-L:
0
Noise filter OFF
1
Noise filter ON
RxD1/SDA10/SI10/P03 pin
Set the SNFEN10 bit to 1 to use the RXD1 pin.
Clear the SNFEN10 bit to 0 to use the other than RxD1 pin.
Notes 1. 78K0R/KF3-L, 78K0R/KG3-L only.
2. 78K0R/KF3-L (μ PD78F1027, 78F1028), 78K0R/KG3-L (μ PD78F1029, 78F1030) only.
Caution
Be sure to clear bits 7 to 3, and 1 to “0” in the 78K0R/KC3-L, 78K0R/KD3-L, and 78K0R/KE3-L. Be
sure to clear bits 7, 5, 3, and 1 to “0” in the 78K0R/KF3-L (μ PD78F1010, 78F1011, 78F1012) and
78K0R/KG3-L (μ PD78F1013, 78F1014). Be sure to clear bits 7, 5, and 3 to “0” in the 78K0R/KF3-L
(μ PD78F1027, 78F1028) and 78K0R/KG3-L (μ PD78F1029, 78F1030).
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CHAPTER 14 SERIAL ARRAY UNIT
Figure 14-19. Format of Noise Filter Enable Register 0 (NFEN0) (1/2)
Address: F0060H
Symbol
After reset: 00H
7
NFEN0
0
R/W
6
5
SNFEN30
Note 1
0
4
SNFEN20
3
Note 1
0
2
SNFEN10
1
SNFEN40
0
Note 2
SNFEN00
Use of noise filter of RXD0 pin
SNFEN00
78K0R/KC3-L, 78K0R/KD3-L, 78K0R/KE3-L: RxD0/SI00/KR4/P74 pin
78K0R/KF3-L, 78K0R/KG3-L:
0
Noise filter OFF
1
Noise filter ON
RxD0/SI00/P11 pin
Set the SNFEN00 bit to 1 to use the RXD0 pin.
Clear the SNFEN00 bit to 0 to use the other than RxD0 pin.
Notes 1. 78K0R/KF3-L, 78K0R/KG3-L only.
2. 78K0R/KF3-L (μ PD78F1027, 78F1028), 78K0R/KG3-L (μ PD78F1029, 78F1030) only.
Caution
Be sure to clear bits 7 to 3, and 1 to “0” in the 78K0R/KC3-L, 78K0R/KD3-L, and 78K0R/KE3-L. Be
sure to clear bits 7, 5, 3, and 1 to “0” in the 78K0R/KF3-L (μ PD78F1010, 78F1011, 78F1012) and
78K0R/KG3-L (μ PD78F1013, 78F1014). Be sure to clear bits 7, 5, and 3 to “0” in the 78K0R/KF3-L
(μ PD78F1027, 78F1028) and 78K0R/KG3-L (μ PD78F1029, 78F1030).
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CHAPTER 14 SERIAL ARRAY UNIT
(16) Port input mode registers 0, 1, 3, 7, 14 (PIM0, PIM1, PIM3, PIM7, PIM14)
These registers set the input buffer of ports 0, 1, 3, 7, and 14 in 1-bit units.
The port input mode registers to be set differ depending on the product.
78K0R/KC3-L, 78K0R/KD3-L, 78K0R/KE3-L: PIM3, PIM7
78K0R/KF3-L, 78K0R/KG3-L:
PIM0, PIM1, PIM14
The PIM0, PIM1, PIM3, PIM7, and PIM14 registers can be set by a 1-bit or 8-bit memory manipulation instruction.
Reset signal generation clears the PIM0, PIM1, PIM3, PIM7, and PIM14 registers to 00H.
Figure 14-20. Format of Port Input Mode Registers 3 and 7 (PIM3 and PIM7)
(78K0R/KC3-L, 78K0R/KD3-L, 78K0R/KE3-L)
Address F0043H
After reset: 00H
R/W
Symbol
7
6
5
4
3
2
1
0
PIM3
0
0
0
0
0
PIM32
PIM31
0
Address F0047H
After reset: 00H
R/W
Symbol
7
6
5
4
3
2
1
0
PIM7
0
0
PIM75
PIM74
0
PIM72
PIM71
0
PIMmn
Pmn pin input buffer selection (m = 3, 7; n = 1, 2, 4, 5)
0
Normal input buffer
1
TTL input buffer
Figure 14-21. Format of Port Input Mode Registers 0, 1, and 14 (PIM0, PIM1, PIM14)
(78K0R/KF3-L, 78K0R/KG3-L)
Address F0040H
After reset: 00H
R/W
Symbol
7
6
5
4
3
2
1
0
PIM0
0
0
0
PIM04
PIM03
0
0
0
Address F0041H
After reset: 00H
R/W
Symbol
7
6
5
4
3
2
1
0
PIM1
0
0
0
0
0
0
PIM11
PIM10
Address F004EH
After reset: 00H
R/W
Symbol
7
6
5
4
3
2
1
0
PIM14
0
0
0
0
PIM143
PIM142
0
0
PIMmn
Pmn pin input buffer selection (m = 0, 1, 14; n = 0 to 4)
0
Normal input buffer
1
TTL input buffer
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(17) Port output mode registers 0, 1, 3, 7, 14 (POM0, POM1, POM3, POM7, POM14)
These registers set the output mode of ports 0, 1, 3, 7, and 14 in 1-bit units.
The port output mode registers to be set differ depending on the product.
78K0R/KC3-L, 78K0R/KD3-L, 78K0R/KE3-L: POM3, POM7
78K0R/KF3-L, 78K0R/KG3-L:
POM0, POM1, POM14
The POM0, POM1, POM3, POM7, and POM14 registers can be set by a 1-bit or 8-bit memory manipulation
instruction.
Reset signal generation clears the