L6728 - STMicroelectronics

L6728 - STMicroelectronics
L6728
Single phase PWM controller with Power Good
Features
■
Flexible power supply from 5 V to 12 V
■
Power conversion input as low as 1.5 V
■
0.8 V internal reference
■
0.8 % output voltage accuracy
■
High-current integrated drivers
■
Power Good output
■
Sensorless and programmable OCP across
low-side RDS(on)
DFN10
■
OV / UV protections
■
VSEN disconnection protection
■
Oscillator internally fixed at 300 kHz
■
LSless to manage pre-bias start-up
■
Adjustable output voltage
■
Disable function
■
Internal soft-start
■
DFN10 package
Applications
Description
L6728 is a single-phase step-down controller with
integrated high-current drivers that provides
complete control logic and protection to realize in
a simple way general DC-DC converters by using
a compact DFN10 package.
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L6728 provides simple control loop with voltage
mode EA. The integrated 0.8 V reference allows
regulating output voltages with ±0.8 % accuracy
over line and temperature variations. Oscillator is
internally fixed to 300 kHz.
Memory and termination supply
■
Subsystem power supply (MCH, IOCH, PCI...)
■
CPU and DSP power supply
■
Distributed power supply
■
General DC-DC converters
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Table 1.
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Device flexibility allows managing conversions
with power input VIN as low as 1.5 V and device
supply voltage ranging from 5 V to 12 V.
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L6728 provides programmable dual level over
current protection as well as over and under
voltage protection. Current information is
monitored across the low-side MOSFET RDS(on)
saving the use of expensive and spaceconsuming sense resistors.
PGOOD output easily provides real-time
information on output voltage status, through
VSEN dedicated output monitor.
Device summary
Order codes
Package
L6728
Packaging
Tube
DFN10
L6728TR
November 2008
Tape and reel
Rev 4
1/31
www.st.com
1
Content
L6728
Content
1
Typical application circuit and block diagram . . . . . . . . . . . . . . . . . . . . 4
2
1.1
Application circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
1.2
Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
Pin description and connection diagrams . . . . . . . . . . . . . . . . . . . . . . . 5
2.1
Pin descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
3
Thermal data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
4
Electrical specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
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4.1
Absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
4.2
Electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
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Device description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
6
Driver section . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
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6.1
7
Power dissipation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
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Soft-start . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
7.1
8
Low-side-less start up (LSLess) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
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Over current protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
8.1
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Over current threshold setting . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
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Output voltage setting and protections . . . . . . . . . . . . . . . . . . . . . . . . 14
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Application details . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
10.1
Compensation network . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
10.2
Layout guidelines . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
Application information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
11.1
Inductor design . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
11.2
Output capacitor(s) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
11.3
Input capacitors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
L6728
12
Content
20 A demonstration board . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
12.1
13
Board description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
12.1.1
Power input (Vin) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
12.1.2
Output (Vout) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
12.1.3
Signal input (Vcc) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
12.1.4
Test points . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
12.1.5
Board characterization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
5 A demonstration board . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
13.1
Board description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
13.1.1
Power input (Vin) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
13.1.2
Output (Vout) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
13.1.3
Signal input (Vcc) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
13.1.4
Test points . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
13.1.5
Board characterization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
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Package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
15
Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
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Typical application circuit and block diagram
L6728
1
Typical application circuit and block diagram
1.1
Application circuit
Figure 1.
Typical application circuit
VIN = 1.5V to 12V
VCC = 5V to 12V
CDEC
6
RPG
VCC
7
COMP
/ DIS
CF
CP
RF
ROS
8
RFB
BOOT
PGOOD
FB
VSEN
UGATE
L6728
10
PGOOD
PHASE
LGATE
/ OC
GND
9
HS
2
4
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Block diagram
VSEN
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VOCTH
OC
CONTROL LOGIC
&
PROTECTIONS
BOOT
ADAPTIVE ANTI
CROSS CONDUCTION
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VOUT MONITOR
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PGOOD
LOAD
VCC
Figure 2.
COUT
LS
RFB
Block diagram
Vout
L
L6728 Reference Schematic
1.2
CBULK
CHF
3
ROCSET
5
ROS
1
CLOCK
PWM
300 kHz
OSCILLATOR
HS
UGATE
PHASE
VCC
LS
ERROR AMPLIFIER
LGATE
/ OC
GND
+
-
L6728
FB
IOCSET
COMP
/ DIS
4/31
0.8V
L6728
2
Pin description and connection diagrams
Pin description and connection diagrams
Figure 3.
2.1
Pin connection (top view)
Pin descriptions
Table 2.
Pin #
Pins description
Name
Function
BOOT
HS driver supply.
Connect through a capacitor (100 nF) to the floating node (LS-Drain) pin
and provide necessary bootstrap diode from VCC.
2
PHASE
HS driver return path, current-reading and adaptive-dead-time monitor.
Connect to the LS drain to sense RDS(on) drop to measure the output
current. This pin is also used by the adaptive-dead-time control circuitry to
monitor when HS MOSFET is OFF.
3
UGATE
HS driver output. Connect directly to HS MOSFET gate.
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LGATE. LS driver output. Connect directly to LS MOSFET gate.
OC. Over Current threshold set. During a short period of time following
VCC rising over UVLO threshold, a 10 μA current is sourced from this pin.
resistor greater than 5 kΩ to program OC
LGATE / OC Connect to GND with an ROCSET
Threshold. The resulting voltage at this pin is sampled and held internally
as the OC set point. Maximum programmable OC threshold is 0.55 V. A
voltage greater than 0.6 V activates an internal clamp and causes OC
threshold to be set at the maximum value.
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GND
All internal references, logic and drivers are connected to this pin.
Connect to the PCB ground plane.
6
VCC
Device and drivers power supply.
Operative range from 5 V to 12 V. Filter with at least 1 nF MLCC to GND.
7
8
COMP. Error amplifier output. Connect with an RF - CF // CP to FB to
compensate the device control loop.
COMP / DIS
DIS. The device can be disabled by pushing this pin lower than 0.75 V (typ).
Setting free the pin, the device enables again.
FB
Error amplifier inverting input.
Connect with a resistor RFB to the output regulated voltage. Output resistor
divider may be used to regulate voltages higher than the reference.
5/31
Thermal data
L6728
Table 2.
3
Pins description (continued)
Pin #
Name
Function
9
VSEN
Regulated voltage sense pin for OVP and UVP protections and PGOOD.
Connect to the output regulated voltage, or to the output resistor divider if
the regulated voltage is higher than the reference.
10
PGOOD
Open drain output set free after SS has finished and pulled low when VSEN
is outside the relative window. Pull up to a voltage equal or lower than VCC.
If not used it can be left floating.
Thermal data
Table 3.
Thermal data
Symbol
Parameter
Rth(JA)
Thermal resistance junction to ambient
(Device soldered on 2s2p, 67 mm x 69 mm board)
Rth(JC)
Thermal resistance junction to case
TMAX
Maximum junction temperature
TSTG
Storage temperature range
TJ
Junction temperature range
PTOT
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Maximum power dissipation at TA = 25 °C
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Value
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Unit
°C/W
5
°C/W
150
°C
-40 to 150
°C
-40 to 125
°C
2.25
W
L6728
Electrical specifications
4
Electrical specifications
4.1
Absolute maximum ratings
Table 4.
Absolute maximum ratings
Symbol
Parameter
Value
Unit
-0.3 to 15
V
VBOOT, VUGATE
to PHASE
to GND
to GND; t < 200 ns
15
33
45
V
VPHASE
to GND
to GND; t < 200 ns
-5 to 18
-8 to 30
V
VLGATE
to GND
-0.3 to VCC+0.3
V
VCC
to GND
FB, COMP, VSEN to GND
-0.3 to 3.6
PGOOD to GND
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Table 5.
Electrical characteristics
(VCC = 5 V to 12 V; TJ = 0 to 70 °C unless otherwise specified)
Test conditions
Supply current and power-ON
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VCC supply current
UGATE and LGATE = OPEN
IBOOT
BOOT supply current
UGATE = OPEN; PHASE to GND
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VCC Turn-ON
Hysteresis
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Oscillator
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FSW
Main oscillator accuracy
ΔVOSC
PWM ramp amplitude
Typ
Max
mA
0.7
mA
0.2
300
V
V
330
1.4
Maximum duty cycle
Unit
6
4.1
270
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Min
VCC rising
UVLO
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Electrical characteristics
Parameter
V
-0.3 to VCC+0.3
4.2
Symbol
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kHz
V
80
%
Reference and error amplifier
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A0
GBWP
Output voltage accuracy
DC gain
-0.8
(1)
Gain-bandwidth product
(1)
(1)
SR
Slew-rate
DIS
Disable threshold
COMP falling
0.70
-
0.8
%
120
dB
15
MHz
8
V/μs
0.85
V
7/31
Electrical specifications
Table 5.
L6728
Electrical characteristics (continued)
(VCC = 5 V to 12 V; TJ = 0 to 70 °C unless otherwise specified)
Symbol
Parameter
Test conditions
Min
Typ
Max
Unit
Gate drivers
IUGATE
HS source current
BOOT - PHASE = 5 V
1.5
A
RUGATE
HS sink resistance
BOOT - PHASE = 5 V
1.1
Ω
ILGATE
LS source current
VCC = 5 V
1.5
A
RLGATE
LS sink resistance
VCC = 5 V
0.65
Ω
Over-current protection
IOCSET
OCSET current source
Sourced from LGATE pin, during OC
setting phase.
VOC_SW
OC switch-over threshold
VLGATE/OC rising
9
10
11
600
mV
Over and under-voltage protections
OVP
VSEN rising
0.970
1.000
un-latch, VSEN falling
0.35
0.40
0.570
OVP threshold
UVP
UVP threshold
VSEN falling
VSEN
VSEN bias current
Sourced from VSEN
Upper threshold
VSEN rising
Lower threshold
VSEN falling
PGOOD voltage low
IPGOOD = -4 mA
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PGOOD
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PGOOD
VPGOODL
1. Guaranteed by design, not subject to test.
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Pr
μA
uc
od
0.600
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1.030
V
0.45
V
0.630
V
100
nA
0.860
0.890
0.920
V
0.680
0.710
0.740
V
0.4
V
L6728
5
Device description
Device description
L6728 is a single-phase PWM controller with embedded high-current drivers that provides
complete control logic and protections to realize in an easy and simple way a general
DC-DC step-down converter. Designed to drive N-channel MOSFETs in a synchronous
buck topology, with its high level of integration this 10-pin device allows reducing cost and
size of the power supply solution also providing real-time PGOOD in a compact DFN10 3x3
mm.
L6728 is designed to operate from a 5 V or 12 V supply. The output voltage can be precisely
regulated to as low as 0.8 V with ±0.8 % accuracy over line and temperature variations. The
switching frequency is internally set to 300 kHz.
This device provides a simple control loop with a voltage-mode error-amplifier. The erroramplifier features a 15 MHz gain-bandwidth product and 8 V/µs slew rate, allowing high
regulator bandwidth for fast transient response.
To avoid load damages, L6728 provides over current protection as well as over voltage,
under voltage and feedback disconnection protection. The over current trip threshold is
programmable by a simple resistor connected from Lgate to GND. Output current is
monitored across low-side MOSFET RDS(on), saving the use of expensive and spaceconsuming sense resistor. Output voltage is monitored through dedicated VSEN pin.
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L6728 implements soft-start increasing the internal reference in closed loop regulation.
Low-side-less feature allows the device to perform soft-start over pre-biased output avoiding
high current return through the output inductor and dangerous negative spike at the load
side.
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L6728 is available in a compact DFN10 3x3 mm package with exposed pad.
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Driver section
6
L6728
Driver section
The integrated high-current drivers allow using different types of power MOSFET (also
multiple MOSFETs to reduce the equivalent RDS(on)), maintaining fast switching transition.
The driver for the high-side MOSFET uses BOOT pin for supply and PHASE pin for return.
The driver for low-side MOSFET uses the VCC pin for supply and GND pin for return.
The controller embodies an anti-shoot-through and adaptive dead-time control to minimize
low side body diode conduction time, maintaining good efficiency while saving the use of
Schottky diode:
●
to check high-side MOSFET turn off, PHASE pin is sensed. When the voltage at
PHASE pin drops down, the low-side MOSFET gate drive is suddenly applied;
●
to check low-side MOSFET turn off, LGATE pin is sensed. When the voltage at LGATE
has fallen, the high-side MOSFET gate drive is suddenly applied.
If the current flowing in the inductor is negative, voltage on PHASE pin will never drop. To
allow the low-side MOSFET to turn-on even in this case, a watchdog controller is enabled: if
the source of the high-side MOSFET doesn't drop, the low side MOSFET is switched on so
allowing the negative current of the inductor to recirculate. This mechanism allows the
system to regulate even if the current is negative.
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Power conversion input is flexible: 5 V, 12 V bus or any bus that allows the conversion (See
maximum duty cycle limitations) can be chosen freely.
6.1
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Power dissipation
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L6728 embeds high current MOSFET drivers for both high side and low side MOSFETs: it is
then important to consider the power that the device is going to dissipate in driving them in
order to avoid overcoming the maximum junction operative temperature.
Two main terms contribute in the device power dissipation: bias power and drivers' power.
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Device bias power (PDC) depends on the static consumption of the device through the
supply pins and it is simply quantifiable as follow (assuming to supply HS and LS
drivers with the same VCC of the device):
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P DC = V CC ⋅ ( I CC + I BOOT )
Drivers power is the power needed by the driver to continuously switch on and off the
external MOSFETs; it is a function of the switching frequency and total gate charge of
the selected MOSFETs. It can be quantified considering that the total power PSW
dissipated to switch the MOSFETs (easy calculable) is dissipated by three main
factors: external gate resistance (when present), intrinsic MOSFET resistance and
intrinsic driver resistance. This last term is the important one to be determined to
calculate the device power dissipation. The total power dissipated to switch the
MOSFETs results:
P SW = F SW ⋅ ( Q gHS ⋅ V BOOT + Q gLS ⋅ V CC )
External gate resistors helps the device to dissipate the switching power since the same
power PSW will be shared between the internal driver impedance and the external resistor
resulting in a general cooling of the device.
10/31
L6728
7
Soft-start
Soft-start
L6728 implements a soft-start to smoothly charge the output filter avoiding high in-rush
currents to be required from the input power supply. The device gradually increases the
internal reference from 0 V to 0.8 V in 4.5 ms (typ.), in closed loop regulation, linearly
charging the output capacitors to the final regulation voltage.
In the event of an over current triggering during soft start, the over current logic will override
the soft start sequence and will shut down the PWM logic and both the high side and low
side gates. This condition is latched, cycle VCC to recover.
The device begins soft start phase only when VCC power supply is above UVLO threshold
and over current threshold setting phase has been completed.
7.1
Low-side-less start up (LSLess)
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In order to avoid any kind of negative undershoot and dangerous return from the load during
start-up, L6728 performs a special sequence in enabling LS driver to switch: during the softstart phase, the LS driver results disabled (LS = OFF) until the HS starts to switch. This
avoid the dangerous negative spike on the output voltage that can happen if starting over a
pre-biased output.
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If the output voltage is pre-biased to a voltage higher than the final one, the HS would never
start to switch. In this case, at the end of soft start time, LS is enabled and discharge the
output to the final regulation value.
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This particular feature of the device masks the LS turn-on only from the control loop point of
view: protections by-pass this turning ON the LS MOSFET in case of need.
Figure 4.
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LSLess start up (left) vs non-LSLess start up (right)
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Over current protection
8
L6728
Over current protection
The over current function protects the converter from a shorted output or overload, by
sensing the output current information across the low side MOSFET drain-source onresistance, RDS(on). This method reduces cost and enhances converter efficiency by
avoiding the use of expensive and space-consuming sense resistors.
The low side RDS(on) current sense is implemented by comparing the voltage at the PHASE
node when LS MOSFET is turned on with the programmed OCP thresholds voltages,
internally held. If the monitored voltage is bigger than these thresholds, an over current
event is detected.
For maximum safety and load protection, L6728 implements a dual level over current
protection system:
●
1st level threshold: it is the user externally set threshold. If the monitored voltage on
PHASE exceeds this threshold, a 1st level over current is detected. If four 1st level OC
events are detected in four consecutive switching cycles, over current protection will be
triggered.
●
2nd level threshold: it is an internal threshold whose value is equal to 1st level
threshold multiplied by a factor 1.5. If the monitored voltage on PHASE exceeds this
threshold, over current protection will be triggered immediately.
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When over current protection is triggered, the device turns off both LS and HS MOSFETs in
a latched condition.
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To recover from over current protection triggered condition, VCC power supply must be
cycled.
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L6728
8.1
Over current protection
Over current threshold setting
L6728 allows to easily program a 1st level over current threshold ranging from 50 mV to
550 mV, simply by adding a resistor (ROCSET) between LGATE and GND. 2nd level threshold
will be automatically set accordingly.
During a short period of time (about 5 ms) following VCC rising over UVLO threshold, an
internal 10 µA current (IOCSET) is sourced from LGATE pin, determining a voltage drop
across ROCSET. This voltage drop will be sampled and internally held by the device as 1st
level over current threshold. The OC setting procedure overall time length is about 5 ms.
Connecting a ROCSET resistor between LGATE and GND, the programmed 1st level
threshold will be:
I OCSET ⋅ R OCSET
I OCth1 = ------------------------------------------R dsON
the programmed 2nd level threshold will be:
I OCth2
I OCSET ⋅ R OCSET
= 1.5 ⋅ -------------------------------------------R dsON
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ROCSET values range from 5 kΩ to 55 kΩ.
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In case ROCSET is not connected, the device sets the OCP thresholds to the maximum
values: an internal safety clamp on LGATE is triggered as soon as LGATE voltage reaches
600 mV, setting the maximum threshold and suddenly ending OC setting phase.
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13/31
Output voltage setting and protections
9
L6728
Output voltage setting and protections
L6728 is capable to precisely regulate an output voltage as low as 0.8 V. In fact, the device
comes with a fixed 0.8 V internal reference that guarantee the output regulated voltage to be
within ±0.8 % tolerance over line and temperature variations (excluding output resistor
divider tolerance, when present).
Output voltage higher than 0.8 V can be easily achieved by adding a resistor ROS between
FB pin and ground. Referring to Figure 1, the steady state DC output voltage will be:
R FB ⎞
V OUT = V REF ⋅ ⎛ 1 + ---------⎝
R ⎠
OS
where VREF is 0.8 V.
L6728 monitors the voltage at VSEN pin and compares it to internal reference voltage in
order to provide under voltage and over voltage protections as well as PGOOD signal.
According to the level of VSEN, different actions are performed from the controller:
●
PGOOD
)
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If the voltage monitored through VSEN exits from the PGOOD window limits, the device
de-asserts the PGOOD signal still continuing switching and regulating. PGOOD is
asserted at the end of the soft-start phase.
●
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Under voltage protection
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If the voltage at VSEN pin drops below UV threshold, the device turns off both HS and
LS MOSFETs, latching the condition. Cycle VCC to recover.
●
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Over voltage protection
If the voltage at VSEN pin rises over OV threshold (1 V typ), over voltage protection
turns off HS MOSFET and turns on LS MOSFET. The LS MOSFET will be turned off as
soon as VSEN goes below Vref/2 (0.4 V). The condition is latched, cycle VCC to
recover. Notice that, even if the device is latched, the device still controls the LS
MOSFET and can switch it on whenever VSEN rises above OV threshold.
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Feedback disconnection protection
In order to provide load protection even if VSEN pin is not connected, a 100 nA bias
current is always sourced from this pin. If VSEN pin is not connected, this current will
permanently pull it up causing the device to detect an OV: thus LS will be latched on
preventing output voltage from rising out of control.
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14/31
L6728
Application details
10
Application details
10.1
Compensation network
The control loop showed in Figure 5 is a voltage mode control loop. The output voltage is
regulated to the internal reference (when present, offset resistor between FB node and GND
can be neglected in control loop calculation).
Error Amplifier output is compared to oscillator saw-tooth waveform to provide PWM signal
to the driver section. PWM signal is then transferred to the switching node with VIN
amplitude. This waveform is filtered by the output filter.
The converter transfer function is the small signal transfer function between the output of the
EA and VOUT. This function has a double pole at frequency FLC depending on the L-COUT
resonance and a zero at FESR depending on the output capacitor ESR. The DC Gain of the
modulator is simply the input voltage VIN divided by the peak-to-peak oscillator voltage
ΔVOSC.
Figure 5.
PWM control loop
VIN
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OSC
ΔV OSC
_
L
PWM
COMPARATOR
(t s)
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ESR
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+
CF
V OUT
COUT
ERROR
AMPLIFIER
CP
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let
+
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VREF
_
RFB
RF
CS
RS
ZFB
ZF
The compensation network closes the loop joining VOUT and EA output with transfer
function ideally equal to -ZF/ZFB.
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Compensation goal is to close the control loop assuring high DC regulation accuracy, good
dynamic performances and stability. To achieve this, the overall loop needs high DC gain,
high bandwidth and good phase margin.
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High DC gain is achieved giving an integrator shape to compensation network transfer
function. Loop bandwidth (F0dB) can be fixed choosing the right RF/RFB ratio, however, for
stability, it should not exceed FSW/2π. To achieve a good phase margin, the control loop gain
has to cross 0 dB axis with -20 dB/decade slope.
As an example, Figure 6 shows an asymptotic bode plot of a type III compensation.
15/31
Application details
Figure 6.
L6728
Example of type III compensation
Gain
[dB]
open loop
EA gain
FZ1 FZ2
FP1
FP2
closed
loop gain
compensation
gain
20log (RF/RFB)
open loop
converter gain
20log (VIN/ΔVOSC )
0dB
FLC
●
Log (Freq)
F0dB
FESR
●
Open loop converter singularities:
a)
1
F LC = --------------------------------2π L ⋅ C OUT
b)
1
F ESR = ------------------------------------------2π ⋅ C OUT ⋅ ESR
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Compensation network singularities frequencies:
a)
1
F Z1 = -----------------------------2π ⋅ R F ⋅ C F
b)
1
F Z2 = ----------------------------------------------------2π ⋅ ( R FB + R S ) ⋅ C S
c)
1
F P1 = -------------------------------------------------CF ⋅ CP
2π ⋅ R F ⋅ ⎛⎝ ---------------------⎞⎠
CF + CP
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d)
1
F P2 = -----------------------------2π ⋅ R S ⋅ C S
To place the poles and zeroes of the compensation network, the following suggestions may
be followed:
a)
Set the gain RF/RFB in order to obtain the desired closed loop regulator bandwidth
according to the approximated formula (suggested values for RFB are in the range
of some kΩ):
F 0dB ΔV OSC
RF
= ------------ ⋅ ---------------------------F LC
V IN
R FB
16/31
L6728
Application details
b)
Place FZ1 below FLC (typically 0.5*FLC):
1
C F = ----------------------------π ⋅ R F ⋅ F LC
c)
Place FP1 at FESR:
CF
C P = ---------------------------------------------------------2π ⋅ R F ⋅ C F ⋅ F ESR – 1
d)
Place FZ2 at FLC and FP2 at half of the switching frequency:
R FB
R S = -------------------------F SW
------------------ – 1
2 ⋅ F LC
1
C S = -----------------------------π ⋅ R S ⋅ F SW
10.2
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Check that compensation network gain is lower than open loop EA gain before
F0dB;
f)
Check phase margin obtained (it should be greater than 45°) and repeat if
necessary.
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Layout guidelines
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L6728 provides control functions and high current integrated drivers to implement highcurrent step-down DC-DC converters. In this kind of application, a good layout is very
important.
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The first priority when placing components for these applications has to be reserved to the
power section, minimizing the length of each connection and loop as much as possible. To
minimize noise and voltage spikes (EMI and losses) power connections (highlighted in
Figure 7) must be a part of a power plane and anyway realized by wide and thick copper
traces: loop must be anyway minimized. The critical components, i.e. the power MOSFETs,
must be close one to the other. The use of multi-layer printed circuit board is recommended.
)
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The input capacitance (CIN), or at least a portion of the total capacitance needed, has to be
placed close to the power section in order to eliminate the stray inductance generated by the
copper traces. Low ESR and ESL capacitors are preferred, MLCC are suggested to be
connected near the HS drain.
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Use proper VIAs number when power traces have to move between different planes on the
PCB in order to reduce both parasitic resistance and inductance. Moreover, reproducing the
same high-current trace on more than one PCB layer will reduce the parasitic resistance
associated to that connection.
Connect output bulk capacitors (COUT) as near as possible to the load, minimizing parasitic
inductance and resistance associated to the copper trace, also adding extra decoupling
capacitors along the way to the load when this results in being far from the bulk capacitors
bank.
17/31
Application details
Figure 7.
L6728
Power connections (heavy lines)
VIN
CIN
UGATE
PHASE
L
L6728
COUT
LGATE
LOAD
GND
Gate traces and phase trace must be sized according to the driver RMS current delivered to
the power MOSFET. The device robustness allows managing applications with the power
section far from the controller without losing performances. Anyway, when possible, it is
recommended to minimize the distance between controller and power section.
Small signal components and connections to critical nodes of the application, as well as
bypass capacitors for the device supply, are also important. Locate bypass capacitor (VCC
and Bootstrap capacitor) and feedback compensation components as close to the device as
practical. For over current programmability, place ROCSET close to the device and avoid
leakage current paths on LGATE / OC pin, since the internal current source is only 10 μA.
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Systems that do not use Schottky diode in parallel to the low-side MOSFET might show big
negative spikes on the phase pin. This spike must be limited within the absolute maximum
ratings (for example, adding a gate resistor in series to HS MOSFET gate), as well as the
positive spike, but has an additional consequence: it causes the bootstrap capacitor to be
over-charged. This extra-charge can cause, in the worst case condition of maximum input
voltage and during particular transients, that boot-to-phase voltage overcomes the absolute
maximum ratings also causing device failures. It is then suggested in this cases to limit this
extra-charge by adding a small resistor in series to the bootstrap diode.
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Figure 8.
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Drivers turn-on and turn-off paths
LS DRIVER
(t s)
LS MOSFET
VCC
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RGATE
HS DRIVER
CGD
CGD
RINT
RGATE
LGATE
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18/31
GND
HS MOSFET
BOOT
RINT
UGATE
CGS
CDS
CGS
PHASE
CDS
L6728
Application information
11
Application information
11.1
Inductor design
The inductance value is defined by a compromise between the dynamic response time, the
efficiency, the cost and the size. The inductor has to be calculated to maintain the ripple
current (ΔIL) between 20 % and 30 % of the maximum output current (typ). The inductance
value can be calculated with the following relationship:
V IN – V OUT V OUT
L = ------------------------------ ⋅ -------------F SW ⋅ ΔI L
V IN
Where FSW is the switching frequency, VIN is the input voltage and VOUT is the output
voltage. Figure 9 shows the ripple current vs. the output voltage for different values of the
inductor, with VIN = 5 V and VIN = 12 V.
)
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Increasing the value of the inductance reduces the current ripple but, at the same time,
increases the converter response time to a dynamic load change. The response time is the
time required by the inductor to change its current from initial to final value. Until the inductor
has not finished its charging time, the output current is supplied by the output capacitors.
Minimizing the response time can minimize the output capacitance required. If the
compensation network is well designed, during a load variation the device is able to set a
duty cycle value very different (0 % or 80 %) from steady state one. When this condition is
reached, the response time is limited by the time required to change the inductor current.
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Figure 9.
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Inductor current ripple vs output voltage
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19/31
Application information
11.2
L6728
Output capacitor(s)
The output capacitors are basic components to define the ripple voltage across the output
and for the fast transient response of the power supply. They depend on the output voltage
ripple requirements, as well as any output voltage deviation requirement during a load
transient.
During steady-state conditions, the output voltage ripple is influenced by both the ESR and
capacitive value of the output capacitors as follow:
ΔV OUT_ESR = ΔI L ⋅ ESR
1
ΔV OUT_C = ΔI L ⋅ --------------------------------------8 ⋅ C OUT ⋅ F SW
Where ΔIL is the inductor current ripple. In particular, the expression that defines ΔVOUT_C
takes in consideration the output capacitor charge and discharge as a consequence of the
inductor current ripple.
)
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During a load variation, the output capacitors supplies the current to the load or absorb the
current stored into the inductor until the converter reacts. In fact, even if the controller
recognizes immediately the load transient and sets the duty cycle at 80 % or 0 %, the
current slope is limited by the inductor value. The output voltage has a drop that also in this
case depends on the ESR and capacitive charge/discharge as follow:
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ΔV OUT_ESR = ΔI OUT ⋅ ESR
ΔV OUT_C
L ⋅ ΔI OUT
= ΔI OUT ⋅ -------------------------------------2 ⋅ C OUT ⋅ ΔV L
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Where ΔVL is the voltage applied to the inductor during the transient response
( D MAX ⋅ VIN – VOUT for the load appliance or VOUT for the load removal).
)
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MLCC capacitors have typically low ESR to minimize the ripple but also have low
capacitance that do not minimize the voltage deviation during dynamic load variations. On
the contrary, electrolytic capacitors have big capacitance to minimize voltage deviation
during load transients while they does not show the same ESR values of the MLCC resulting
then in higher ripple voltages. For these reasons, a mix between electrolytic and MLCC
capacitor is suggested to minimize ripple as well as reducing voltage deviation in dynamic
mode.
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11.3 o Input capacitors
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The input capacitor bank is designed considering mainly the input rms current that depends
on the output deliverable current (IOUT) and the duty-cycle (D) for the regulation as follow:
I rms = I OUT ⋅ D ⋅ ( 1 – D )
The equation reaches its maximum value, IOUT/2, with D = 0.5. The losses depends on the
input capacitor ESR and, in worst case, are:
P = ESR ⋅ ( I OUT ⁄ 2 )
20/31
2
L6728
12
20 A demonstration board
20 A demonstration board
L6728 demonstration board realizes in a four-layer PCB a step-down DC/DC converter and
shows the operation of the device in a general purpose application. The input voltage can
range from 5 V to 12 V buses and the output voltage is fixed at 1.25 V. The application can
deliver an output current up to 30 A. The switching frequency is 300 kHz.
Figure 10. 20 A demonstration board (left) and components placement (right)
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Figure 11. L6728 - 20 A demonstration board top (left) and bottom (right) layers
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Figure 12. L6728 - 20 A demonstration board inner layers
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21/31
20 A demonstration board
L6728
Figure 13. 20 A demonstration board schematic
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L6728
20 A demonstration board
Table 6.
20 A demonstration board - bill of material
Qty
Reference
Description
Package
Capacitors
2
C1, C2
Electrolytic capacitor 1800 µF 16 V
Nippon chemi-con KZJ or KZG
1
C10
MLCC, 100 nF, 16V, X7R
SMD0603
3
C11 to C13
MLCC, 4.7 μF, 16V, X5R
Murata GRM31CR61C475MA01
SMD1206
2
C14, C38
MLCC, 1 μF, 16V, X7R
SMD0805
2
C15, C19
MLCC, 10 μF, 6.3 V, X7R
Murata GRM31CR70J106KA01L
SMD1206
2
C18, C20
Electrolytic capacitor 2200 μF 6.3 V
Nippon chemi-con KZJ or KZG
1
C23
MLCC, 6.8 nF, X7R
1
C24
MLCC, 33 nF, X7R
1
C35
MLCC, 68 pF, X7R
Resistors
Resistor, 3R3, 1/16W, 1 %
4
R3, R5, R11, R16
Resistor, 0R, 1/8W, 1 %
1
R4
Resistor, 1R8, 1/8W, 1 %
2
R6, R9
2
R8, R13
1
R7
1
R19
1
R18
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L1
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SMD0603
SMD0805
Resistor, 2K2, 1/16W, 1 %
Resistor, 3K9, 1/16W, 1 %
(s)
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1
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R1, R2, R20, R17
Inductor
Radial 10 x 20 mm
SMD0603
4
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Radial 10 x 25 mm
Resistor, 18K, 1/16W, 1 %
SMD0603
Resistor, 22K, 1/16W, 1 %
Resistor, 20K, 1/16W, 1 %
Inductor, 1.25 μH, T60-18, 6 turns
Easymagnet AP106019006P-1R1M
na
Active components
O
bs
1
D1
Diode, 1N4148 or BAT54
1
Q5
STD70N02L
1
Q7
STD95NH02LT4
1
U1
Controller, L6728
SOT23
DPACK
DFN10, 3x3 mm
23/31
20 A demonstration board
L6728
12.1
Board description
12.1.1
Power input (Vin)
This is the input voltage for the power conversion. The High-Side drain is connected to this
input. This voltage can range from 1.5 V to 12 V bus.
If the voltage is between 4.5 V and 12 V it can supply also the device (through the Vcc pin)
and in this case the R16 (0 Ω) resistor must be present.
12.1.2
Output (Vout)
The output voltage is fixed at 1.25 V but it can be changed by replacing the resistors R8
(sense partition lower resistor) and R13 (feedback partition lower resistor). R18 allows to
adjust OCP threshold.
12.1.3
Signal input (Vcc)
)
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t(
Using the input voltage Vin to supply the controller no power is required at this input.
However the controller can be supplied separately from the power stage through the Vcc
input (4.5-12 V) and, in this case, the R16 (0 Ω) resistor must be unsoldered.
12.1.4
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Test points
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Several test points are provided to have easy access at all important signal characterizing
the device:
12.1.5
COMP: the output of the error amplifier;
–
FB: the inverting input of the error amplifier;
–
PGOOD: signaling the regular functioning (active high);
–
VGDHS: the bootstrap diode anode;
–
PHASE: Phase node;
–
LGATE: Low-side gate pin of the device;
–
HGATE: High-side gate pin of the device.
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Board characterization
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Figure 14. 20 A demonstration board efficiency
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24/31
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–
L6728
13
5 A demonstration board
5 A demonstration board
L6728 demonstration board realizes in a two-layer PCB a step-down DC/DC converter and
shows the operation of the device in a general-purpose low-current application. The input
voltage can range from 5 V to 12 V buses and the output voltage is fixed at 1.25 V. The
application can deliver an output current in excess of 5 A. The switching frequency is
300 kHz.
Figure 15. L6728 - 5 A demonstration board (left) and components placement (right)
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Figure 16. L6728 - 5 A demonstration board top (left) and bottom (right) layers
)
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25/31
VIN1
R16
0
GND
ᤢ
1uF
U
H
O
O
N
UR
U
RW
Q
ZR
WF
H
1
H
QK
W
R
U
LD
W
DH
VQ
Q
HH
SF
PD
O
RS
&
220pF
68nF
4.7k
C35
C24
R13
3.9k
R9
VSEN
15
6.8nF
C36
Vsen
2.2k
R6
3
Q5a
5 /6
VIN_POWER
LSG1
2
1
0
Q5b
7 /8
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0
R8
3.9k
R14
2.2k
0
0
HSG1 4
HSD
0
L2
2.2uH
C23
6.8nF
R4
1.8
2
1
0
ᤡ
C12
10uF
ᤡ
ᤢ
330uF
C40
NC
0
22uF
0
ᤢ
C30
NC
OUT
C39
OUT
NC
0
C51
10uF
ᤢ
C29
0
ᤡ
ᤢ
C18
OUT
0
OUT
ᤡ
V
U
R
W
L
F
D
S
D
F
F
L
P
D
U
H
F
R7
FB
R1
VCC
3.3
R5
PHASE
R3
C10
100nF
BOOT
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COMP
7
VCC_PIN
FB
COMP
8
6
VSEN
R19
22k
9
10
LGATE
R17
3.3
3.3
W
Q
L
U
S
W
R
R
I
O
D
X
G
0
C14
VCC
COMP
FB
VSEN
PGOOD
LGATE
PHASE PIN
PHASE
UGATE
R2
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-
ᤡ
0
5
LGATE
UGATE
L6728
PGOOD
VCC_PIN
0
BAT54
V
U
R
W
L
F
D
S
D
F
P
X
O
D
W
Q
D
7
R18
10k
4
3
PHASE
BOOT
C38
1uF
D1
U
R
W
L
F
D
S
D
F
F
L
W
\
O
R
U
W
F
H
O
(
LGATE
UGATE
2
1
U1
GND
VCC
)
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(
ct
PHASE PIN
GND
GNDIN1
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/
/
+
1
'
6
7
6
W
H
I
V
R
0
O
D
X
'
BOOT
0
GNDCC
VCC
VCC
GND
0
GNDIN_POWER
V
U
R
W
L
F
D
S
D
F
F
L
P
D
U
H
F
W
Q
L
U
S
W
R
R
I
O
D
X
G
COMP
26/31
W
Q
L
U
S
W
R
R
I
O
D
X
G
FB
V
R
P
6
+
U
D
H
Q
H
F
D
O
S
OUT
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VIN_POWER
VOUT
0
GNDOUT1
GNDOUT
VOUT1
5 A demonstration board
L6728
Figure 17. 5 A demonstration board schematic
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L6728
5 A demonstration board
Table 7.
5 A demonstration board - bill of material
Qty
Reference
Description
Package
Capacitors
2
C12, C51
MLCC, 10 μF, 25 V, X5R
Murata GRM31CR61E106KA12
SMD1206
1
C10
MLCC, 100 nF, 16 V, X7R
SMD0603
2
C14, C38
MLCC, 1 μF, 16 V, X7R
SMD0805
1
C39
MLCC, 22 μF, 6.3 V, X5R
Murata GRM31CR60J226ME19L
SMD1206
1
C30
330 μF, 6.3 V, 9 mΩ
Sanyo 6TPF330M9L
SMD7343
2
C23, C36
MLCC, 6.8 nF, X7R
1
C24
MLCC, 68 nF, X7R
1
C35
MLCC, 220 pF, X7R
3
R1, R2, R17
Resistor, 3R3, 1/16 W, 1 %
3
R3, R5, R16
Resistor, 0R, 1/16 W, 1 %
1
R4
Resistor, 1R8, 1/8 W, 1 %
1
R14
Resistor, 15R, 1/16 W, 1 %
2
R6, R9
Resistor, 2K2, 1/16 W, 1 %
2
R8, R13
1
R7
1
R19
1
R18
SMD0603
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Resistors
Inductor
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1
L1
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-
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SMD0603
SMD0603
SMD0805
SMD0603
Resistor, 3K9, 1/16 W, 1 %
Resistor, 4K7, 1/16 W, 1 %
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(t s)
SMD0603
Resistor, 22K, 1/16 W, 1 %
Resistor, 10K, 1/16 W, 1 %
Inductor, 2.2 μH,
WURTH 744324220LF
na
Active Components
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1
D1
Diode, BAT54
1
Q5
STS9D8NH3LL
1
U1
Controller, L6728
13.1
Board description
13.1.1
Power input (Vin)
SOT23
SO8
DFN10, 3x3 mm
This is the input voltage for the power conversion. The high-side drain is connected to this
input. This voltage can range from 1.5 V to 12 V bus.
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5 A demonstration board
L6728
If the voltage is between 4.5 V and 12 V it can supply also the device (through the Vcc pin)
and in this case the R16 (0Ω) resistor must be present.
13.1.2
Output (Vout)
The output voltage is fixed at 1.25 V but it can be changed by replacing the resistors R8
(sense partition lower resistor) and R13 (feedback partition lower resistor). R18 allows to
adjust OCP threshold.
13.1.3
Signal input (Vcc)
Using the input voltage Vin to supply the controller no power is required at this input.
However the controller can be supplied separately from the power stage through the Vcc
input (4.5-12 V) and, in this case, the R16 (0 Ω) resistor must be unsoldered.
13.1.4
Test points
Several test points are provided to have easy access at all important signal characterizing
the device:
13.1.5
–
COMP: the output of the error amplifier;
–
FB: the inverting input of the error amplifier;
–
PGOOD: signaling the regular functioning (active high);
–
VGDHS: the bootstrap diode anode;
–
PHASE: Phase node;
–
LGATE: Low-side gate pin of the device;
–
HGATE: High-side gate pin of the device.
Board characterization
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Figure 18. 5 A demonstration board efficiency
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L6728
14
Package mechanical data
Package mechanical data
In order to meet environmental requirements, ST offers these devices in ECOPACK®
packages. These packages have a lead-free second level interconnect. The category of
second level interconnect is marked on the package and on the inner box label, in
compliance with JEDEC Standard JESD97. The maximum ratings related to soldering
conditions are also marked on the inner box label. ECOPACK is an ST trademark.
ECOPACK specifications are available at: www.st.com
Table 8.
DFN10 mechanical data
mm
mils
Dim.
Min
Typ
Max
Min
Typ
Max
0.80
0.90
1.00
31.5
35.4
39.4
A1
0.02
0.05
0.8
2.0
A2
0.70
27.6
A3
0.20
7.9
A
b
0.18
D
D2
2.21
c
u
d
7.1
9.1
2.26
1.49
1.64
0.50
0.3
M
0.4
0.75
m
(t s)
0.25
c
u
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o
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P
11.8
118.1
2.31
87.0
1.74
o
s
b
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0.5
89.0
e
t
le
3.00
e
L
0.30
3.00
E
E2
0.23
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s
t(
58.7
11.8
90.9
118.1
64.6
68.5
19.7
15.7
19.7
29.5
9.8
Figure 19. Package dimensions
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Revision history
15
L6728
Revision history
Table 9.
Document revision history
Date
Revision
Changes
29-Jun-2007
1
Initial release
17-Sep-2007
2
Updated TJ value in Table 3: Thermal data on page 6
05-Jun-2008
3
Added Figure 11 on page 21
Updated Section 14 on page 29, coverpage, Table 6 on page 23,
Figure 17 on page 26, Table 7 on page 27
18-Nov-2008
4
Updated Table 5 on page 7
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L6728
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