ASM2I9940L
ASM2I9940L
April 2007
rev 1.2
Low Voltage 1:18 Clock Distribution Chip
Features
With low output impedance (≈20Ω), in both the HIGH and
•
LVPECL or LVCMOS Clock Input
LOW logic states, the output buffers of the ASM2I9940L
•
2.5V LVCMOS Outputs for Pentium II
are ideal for driving series terminated transmission lines.
Microprocessor Support*
With 20Ω output impedance the ASM2I9940L has the
•
150pS Maximum Output-to-Output Skew
capability of driving two series terminated lines from each
•
Maximum Output Frequency of 250MHz
•
32 Lead LQFP & TQFP Packaging
The differential LVPECL inputs of the ASM2I9940L allow
•
Dual or Single Supply Device
the device to interface directly with a LVPECL fanout buffer
•
Dual VCC Supply Voltage, 3.3V Core and 2.5V
output. This gives the device an effective fanout of 1:36.
to build very wide clock fanout trees or to couple to a high
frequency clock source. The LVCMOS input provides a
Output
more standard interface for applications requiring only a
•
Single 3.3V VCC Supply Voltage for 3.3V Outputs
•
Single 2.5V VCC Supply Voltage for 2.5V I/O
addition, the two clock sources can be used to provide for a
•
Pin and Function compatible to MPC940L,
test clock interface as well as the primary system clock. A
MPC9109, CY29940 and CY29940-1
logic HIGH on the LVCMOS_CLK_Sel pin will select the
single clock distribution chip at relatively low frequencies. In
LVCMOS level clock input. All inputs of the ASM2I9940L
have internal
Functional Description
pullup/pulldown resistor, so they can be left
open if unused.
The ASM2I9940L is a 1:18 low Voltage Clock distribution
chip with 2.5V or 3.3V LVCMOS output capabilities. The
device features the capability to select either a differential
LVPECL or LVCMOS compatible input. The 18 outputs are
2.5V or 3.3V LVCMOS compatible and feature the drive
strength to drive 50Ω series or parallel terminated
transmission lines. With output-to-output skews of 150pS,
the ASM2I9940L is ideal as a clock distribution chip for the
most demanding of Synchronous systems. The 2.5V
outputs also make the device ideal for supplying clocks for
The ASM2I9940L is a single or dual supply device. The
device power supply offers a high degree of flexibility. The
device can operate with a 3.3V core and 3.3V output, a
3.3V core and 2.5V outputs as well as a 2.5V core and
2.5V outputs. The 32-lead LQFP and TQFP Packages
were chosen to optimize performance, board space and
cost of the device. The 32-lead LQFP and TQFP Packages
have a 7x7mm2 body size with conservative 0.8mm pin
spacing.
a high performance microprocessor based design.
* Pentium II is a trademark of Intel Corporation
PulseCore Semiconductor Corporation
1715 S. Bascom Ave Suite 200, Campbell, CA 95008 • Tel: 408-879-9077 • Fax: 408-879-9018
www.pulsecoresemi.com
Notice: The information in this document is subject to change without notice.
ASM2I9940L
April 2007
rev 1.2
Block Diagram
PECL_CLK
0
PECL_CLK
Q0
LVCMOS_CLK
1
16
LVCMOS_CLK_Sel
Q1-Q16
(Internal Pulldown)
Q17
Q7
Q8
VCCI
Q9
Q10
Q11
GNDO
GNDO
Q6
Pin Diagram
24
25
23
22
21
20
19
18
17
16
VCCO
Q5
26
15
Q12
Q4
27
14
Q13
Q3
28
13
Q14
VCC0
29
12
GNDO
Q2
30
11
Q15
Q1
31
10
Q16
Q0
32
9
Q17
Table 1. Function Table
4
GNDI
LVCMOS_CLK
LVCMOS_CLK_S
l
PECL_CLK
5
6
7
8
VCCO
3
VCCI
2
PECL_CLK
1
GNDO
ASM2I9940L
Table 2. Power Supply Voltages
LVCMOS_CLK_Sel
Input
0
1
PECL_CLK
LVCMOS_CLK
Supply Pin
Voltage Level
VCCI
VCCO
2.5V or 3.3V ± 5%
2.5V or 3.3V ± 5%
Low Voltage 1:18 Clock Distribution Chip
Notice: The information in this document is subject to change without notice.
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ASM2I9940L
April 2007
rev 1.2
Table 3. Pin Configuration
Pin #
Pin Name
5
PECL_CLK
6
PECL_CLK
3
LVCMOS_CLK
I/O
Type
Function
Input
LVPECL
Input
LVCMOS
LVCMOS Clock Input
LVPECL Clock Inputs
4
LVCMOS_CLK_Sel
Input
LVCMOS
Selects either LVPECL or
LVCMOS input as Clock Source
32,31,30,28,27,26,24,23,22,
20,19,18,15,14,13,11,10,9
Q0–Q17
Output
LVCMOS
Clock Outputs
2
GNDI
Supply
Core Negative Power Supply
1,12,17,25
GNDO
Supply
Output Negative Power Supply
7,21
VCCI
Supply
Core Positive Power Supply
8, 16,29
VCCO
Supply
Output Positive Power Supply
Table 4. Absolute Maximum Ratings1
Symbol
Min
Max
Unit
Supply Voltage
-0.3
3.6
V
VI
Input Voltage
-0.3
VCC + 0.3
V
IIN
Input Current
±20
mA
125
°C
260
°C
2
KV
VCC
TStor
Ts
TDV
Parameter
Storage Temperature Range
-40
Max. Soldering Temperature (10 sec)
Static Discharge Voltage
(As per JEDEC STD22- A114-B)
Note:1. These are stress ratings only and are not implied for functional use. Exposure to absolute maximum ratings for prolonged periods of time may affect
device reliability.
Low Voltage 1:18 Clock Distribution Chip
Notice: The information in this document is subject to change without notice.
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ASM2I9940L
April 2007
rev 1.2
Table 5. DC Characteristics (TA =-40° to +85°C, VCCI = 3.3V ± 5%, VCCO = 3.3V ± 5%)
Symbol
Characteristic
Min
Typ
2.0
Max
Unit
VCCI
V
0.8
V
VIH
Input HIGH Voltage
CMOS_CLK
VIL
Input LOW Voltage
CMOS_CLK
VPP
Peak–to–Peak Input
Voltage
PECL_CLK
500
1000
mV
VCMR
Common Mode Range
PECL_CLK
VCC-1.4
VCC-0.6
V
VOH
Output HIGH Voltage
VOL
Output LOW Voltage
2.4
V
IOH = –20mA
0.5
V
IOH = 20mA
±200
µA
IIN
Input Current
CIN
Input Capacitance
4.0
pF
Cpd
Power Dissipation Capacitance
10
pF
ZOUT
Output Impedance
ICC
18
Maximum Quiescent Supply Current
Condition
23
28
Ω
0.5
1.0
mA
per output
Table 6. AC Characteristics (TA = -40° to +85°C, VCCI = 3.3V ± 5%, VCCO = 3.3V ± 5%)
Symbol
Characteristic
Min
Typ
Max
Unit
250
MHz
Condition
Fmax
Maximum Input Frequency
tPLH
Propagation Delay
PECL_CLK < 150MHz
CMOS_CLK < 150MHz
2.0
1.7
2.7
2.5
3.4
3.0
nS
tPLH
Propagation Delay
PECL_CLK > 150MHz
CMOS_CLK > 150MHz
2.0
1.8
2.9
2.5
3.7
3.2
nS
tsk(o)
Output-to-output Skew
150
150
pS
1
Note .
tsk(pp)
Part-to-Part Skew
PECL_CLK < 150MHz
CMOS_CLK < 150MHz
1.5
1.3
nS
Notes1,2
tsk(pp)
Part-to-Part Skew
PECL_CLK > 150MHz
CMOS_CLK > 150MHz
1.8
1.5
nS
Notes
1,2
tsk(pp)
Part-to-Part Skew
PECL_CLK CMOS_CLK
850
750
pS
Notes
1,3
DC
Output Duty Cycle
fCLK < 134 MHz
fCLK <250 MHz
55
60
%
%
Input DC = 50%
Input DC = 50%
tr, tf
Output Rise/Fall Time
1.1
nS
0.5 – 2.4 V
PECL_CLK
CMOS_CLK
45
40
0.3
50
50
Note1.
Note: 1. Tested using standard input levels, Production tested @ 150MHz.
2. Across temperature and voltage ranges, includes output skew.
3. For a specific temperature and voltage, includes output skew.
Low Voltage 1:18 Clock Distribution Chip
Notice: The information in this document is subject to change without notice.
4 of 13
ASM2I9940L
April 2007
rev 1.2
Table 7. DC Characteristics (TA = -40° to +85°C, VCCI = 3.3V ± 5%, VCCO = 2.5V ± 5%)
Symbol
Characteristic
Min
Typ
2.0
Max
Unit
VCCI
V
0.8
V
VIH
Input HIGH Voltage
CMOS_CLK
VIL
Input LOW Voltage
CMOS_CLK
VPP
Peak–to–Peak Input
Voltage
PECL_CLK
500
1000
mV
VCMR
Common Mode Range
PECL_CLK
VCC-1.4
VCC-0.6
V
VOH
Output HIGH Voltage
VOL
Output LOW Voltage
1.8
V
IOH = -20mA
0.5
V
IOH = 20mA
±200
µA
IIN
Input Current
CIN
Input Capacitance
4.0
pF
Cpd
Power Dissipation Capacitance
10
pF
ZOUT
Output Impedance
23
Ω
Maximum Quiescent Supply Current
0.5
ICC
Condition
1.0
per output
mA
Table 8. AC Characteristics (TA =-40° to +85°C, VCCI = 3.3V ± 5%, VCCO = 2.5V ± 5%)
Symbol
Characteristic
Min
Typ
Max
Unit
250
MHz
Condition
Fmax
Maximum Input Frequency
tPLH
Propagation Delay
PECL_CLK < 150MHz
CMOS_CLK < 150MHz
2.0
1.7
2.8
2.5
3.5
3.0
nS
tPLH
Propagation Delay
PECL_CLK > 150MHz
CMOS_CLK > 150MHz
2.0
1.8
2.9
2.5
3.8
3.3
nS
tsk(o)
Output-to-output Skew
150
150
pS
Note1
tsk(pp)
Part–to–Part Skew
PECL_CLK < 150MHz
CMOS_CLK < 150MHz
1.5
1.3
nS
Notes1,2
tsk(pp)
Part–to–Part Skew
PECL_CLK > 150MHz
CMOS_CLK > 150MHz
1.8
1.5
nS
Notes1,2
tsk(pp)
Part–to–Part Skew
PECL_CLK CMOS_CLK
pS
Notes
DC
Output Duty Cycle
fCLK < 134 MHz
fCLK <250 MHz
tr, tf
Output Rise/Fall Time
PECL_CLK
CMOS_CLK
45
40
0.3
50
50
850
750
55
60
1.2
Note1.
1,3
%
%
Input DC = 50%
Input DC = 50%
nS
0.5 - 1.8 V
Note: 1.Tested using standard input levels, Production tested @ 150MHz.
2. Across temperature and voltage ranges, includes output skew.
3. For a specific temperature and voltage, includes output skew.
Low Voltage 1:18 Clock Distribution Chip
Notice: The information in this document is subject to change without notice.
5 of 13
ASM2I9940L
April 2007
rev 1.2
Table 9. DC Characteristics (TA = -40° to +85°C, VCCI = 2.5V ± 5%, VCCO = 2.5V ± 5%)
Symbol
Characteristic
Min
VIH
Input HIGH Voltage
CMOS_CLK
VIL
Input LOW Voltage
Peak–to–Peak Input
Voltage
CMOS_CLK
VPP
VCMR
Common Mode Range
VOH
Output HIGH Voltage
VOL
Output LOW Voltage
Typ
Max
Unit
VCCI
V
0.8
V
2.0
PECL_CLK
500
1000
mV
PECL_CLK
VCC-1.0
VCC-0.6
V
1.8
V
IOH = -20mA
0.5
V
IOH = 20mA
±200
µA
IIN
Input Current
CIN
Input Capacitance
4.0
pF
Cpd
Power Dissipation Capacitance
10
pF
ZOUT
ICC
Output Impedance
18
Maximum Quiescent Supply Current
Condition
23
28
Ω
0.5
1.0
mA
per output
Table 10. AC Characteristics (TA =-40° to +85°C, VCCI = 2.5V ± 5%, VCCO = 2.5V ± 5%)
Symbol
Characteristic
Fmax
Maximum Input Frequency
tPLH
Propagation Delay
tPLH
Propagation Delay
tsk(o)
Output-to-output Skew
Within one bank
tsk(pp)
Part–to–Part Skew
tsk(pp)
Part–to–Part Skew
tsk(pp)
Part–to–Part Skew
DC
Output Duty Cycle
tr, tf
Output Rise/Fall Time
PECL_CLK < 150MHz
CMOS_CLK < 150MHz
PECL_CLK > 150MHz
CMOS_CLK > 150MHz
PECL_CLK
CMOS_CLK
PECL_CLK < 150MHz
CMOS_CLK < 150MHz
PECL_CLK > 150MHz
CMOS_CLK > 150MHz
PECL_CLK
CMOS_CLK
fCLK < 134 MHz
fCLK <250 MHz
Min
2.6
2.3
2.8
2.3
45
40
0.3
Typ
4.0
3.1
3.8
3.1
50
50
Max
Unit
200
MHz
5.2
4.0
5.0
4.0
200
200
2.6
1.7
2.2
1.7
1.2
1.0
55
60
1.2
nS
Condition
Note1.
nS
pS
Note1.
nS
Notes1,2
nS
Notes1,2
nS
Notes1,3
%
%
nS
Input DC = 50%
Input DC = 50%
0.5 - 1.8 V
Note: 1. Tested using standard input levels, Production tested @ 150MHz.
2. Across temperature and voltage ranges, includes output skew.
3. For a specific temperature and voltage, includes output skew.
Low Voltage 1:18 Clock Distribution Chip
Notice: The information in this document is subject to change without notice.
6 of 13
ASM2I9940L
April 2007
rev 1.2
ASM2I9940L
Z0=50Ω
Pulse
Generator
Z=50Ω
Z0=50Ω
RT=50Ω
RT=50Ω
VTT
VTT
Figure 1. LVCMOS_CLK ASM2I9940L AC Test Reference for VCC = 3.3V and VCC = 2.5V
Differential
Pulse Generator
Z=50Ω
ASM2I9940L
Z0=50Ω
Z0=50Ω
RT = 50Ω
RT=50Ω
VTT
VTT
Figure 2. PECL_CLK ASM2I9940L AC Test Reference for VCC = 3.3V and VCC = 2.5V
PECL_CLK
VPP
PECL_CLK
VC
LVCMOS_CLK
VCMR
VCC ÷2
GND
VCC
Q
GND
tPD
Figure 3. Propagation Delay (tPD) Test Reference
VC
VCC ÷2
Q
VCC ÷2
GND
tPD
Figure 4. LVCMOS Propagation Delay (tPD) Test Reference
VCC
VCC
VCC ÷2
VCC ÷2
GND
GND
tP
VOH
VCC ÷2
T0
The time from the PLL controlled edge to the
non-controlled edge, divided by the time
between PLL controlled edges, expressed as a
percentage.
GND
tSK(O)
DC (tP ÷T0 Χ 100%)
The pin-to-pin skew is defined as the worst case
difference in propagation delay between any similar
delay path within a single device
Figure 5. Output Duty Cycle (DC)
Figure 6. Output–to–Output Skew tSK(O)
VCC = 3.3V VCC = 2.5V
tF
2.4
1.8V
0.55
0.6V
tR
VCC = 3.3V VCC = 2.5V
tF
Figure 7. Output Transition Time Test Reference
2.0
1.7V
0.8
0.7V
tR
Figure 8. Input Transition Time Test Reference
Low Voltage 1:18 Clock Distribution Chip
Notice: The information in this document is subject to change without notice.
7 of 13
ASM2I9940L
April 2007
rev 1.2
Power Consumption of the ASM2I9940L and
Thermal Management
Where ICCQ is the static current consumption of the
ASM2I9940L, CPD is the power dissipation capacitance
per output, (M)∑CL represents the external capacitive
output load, N is the number of active outputs (N is
always 12 in case of the ASM2I9940L). The ASM2I9940L
supports driving transmission lines to maintain high signal
integrity and tight timing parameters. Any transmission
line will hide the lumped capacitive load at the end of the
board trace, therefore, ∑CL is zero for controlled
transmission line systems and can be eliminated from
equation 1. Using parallel termination output termination
results in equation 2 for power dissipation.
The ASM2I9940L AC specification is guaranteed for the
entire operating frequency range up to 250MHz. The
ASM2I9940L power consumption and the associated
long-term reliability may decrease the maximum
frequency limit, depending on operating conditions such
as clock frequency, supply voltage, output loading,
ambient temperature, vertical convection and thermal
conductivity of package and board. This section
describes the impact of these parameters on the junction
temperature and gives a guideline to estimate the
ASM2I9940L die junction temperature and the associated
device reliability.
In equation 2, P stands for the number of outputs with a
parallel or thevenin termination, VOL, IOL, VOH and IOH are
a function of the output termination technique and DCQ is
the clock signal duty cycle. If transmission lines are used
∑CL is zero in equation 2 and can be eliminated. In
general, the use of controlled transmission line
techniques eliminates the impact of the lumped capacitive
loads at the end lines and greatly reduces the power
dissipation of the device. Equation 3 describes the die
junction temperature TJ as a function of the power
consumption.
Table 11. Die junction temperature and MTBF
Junction temperature
(°C)
MTBF (Years)
100
20.4
110
9.1
120
4.2
130
2.0
Increased power consumption will increase the die
junction temperature and impact the device reliability
(MTBF). According to the system-defined tolerable
MTBF, the die junction temperature of the ASM2I9940L
needs to be controlled and the thermal impedance of the
board/package should be optimized. The power
dissipated in the ASM2I9940L is represented in
equation 1.
Where Rthja is the thermal impedance of the package
(junction to ambient) and TA is the ambient temperature.
According to Table 11, the junction temperature can be
used to estimate the long-term device reliability. Further,
combining equation 1 and equation 2 results in a
maximum operating frequency for the ASM2I9940L in a
series terminated transmission line system, equation 4.



PTOT =  I CCQ + VCC ⋅ f CLOCK ⋅  N ⋅ C PD + ∑ C L  ⋅ VCC
M



Equation 1



PTOT = VCC ⋅  I CCQ + VCC ⋅ f CLOCK ⋅  N ⋅ C PD + ∑ C L  + ∑ DC Q ⋅ I OH (VCC − VOH ) + (1 − DC Q ) ⋅ I OL ⋅ VOL
M

 P

T J = T A + PTOT ⋅ Rthja
[
f CLOCKMAX =
C PD
1
2
⋅ N ⋅ VCC

T
− TA
⋅  JMAX
− (I CCQ ⋅ VCC )

 Rthja
Low Voltage 1:18 Clock Distribution Chip
Notice: The information in this document is subject to change without notice.
]
Equation 2
Equation 3
Equation 4
8 of 13
ASM2I9940L
April 2007
rev 1.2
TJ,MAX should be selected according to the MTBF
system requirements and Table 11. Rthja can be derived
from Table 12. The Rthja represent data based on 1S2P
boards, using 2S2P boards will result in a lower thermal
impedance than indicated below.
Table 12. Thermal package impedance of the
32LQFP
Convection,
Rthja (1P2S
Rthja (2P2S
board), °C/W
board), °C/W
LFPM
Still air
100 lfpm
200 lfpm
300 lfpm
400 lfpm
500 lfpm
86
76
71
68
66
60
61
56
54
53
52
49
If the calculated maximum frequency is below 250MHz, it
becomes the upper clock speed limit for the given
application conditions. The following eight derating charts
describe the safe frequency operation range for the
ASM2I9940L. The charts were calculated for a maximum
tolerable die junction temperature of 110°C (120°C),
corresponding to an estimated MTBF of 9.1 years
(4 years), a supply voltage of 3.3V and series terminated
transmission line or capacitive loading. Depending on a
given set of these operating conditions and the available
device convection a decision on the maximum operating
frequency can be made.
Low Voltage 1:18 Clock Distribution Chip
Notice: The information in this document is subject to change without notice.
9 of 13
ASM2I9940L
April 2007
rev 1.2
Package Information
32-lead TQFP
SECTION A-A
Dimensions
Symbol
Inches
Min
Max
Millimeters
Min
Max
A
….
0.0472
…
1.2
A1
0.0020
0.0059
0.05
0.15
A2
0.0374
0.0413
0.95
1.05
D
0.3465
0.3622
8.8
9.2
D1
0.2717
0.2795
6.9
7.1
E
0.3465
0.3622
8.8
9.2
E1
0.2717
0.2795
6.9
7.1
L
0.0177
0.0295
0.45
0.75
L1
0.03937 REF
1.00 REF
T
0.0035
0.0079
0.09
0.2
T1
0.0038
0.0062
0.097
0.157
b
0.0118
0.0177
0.30
0.45
b1
0.0118
0.0157
0.30
0.40
R0
0.0031
0.0079
0.08
0.2
a
0°
7°
0°
7°
e
0.031 BASE
0.8 BASE
Low Voltage 1:18 Clock Distribution Chip
Notice: The information in this document is subject to change without notice.
10 of 13
ASM2I9940L
April 2007
rev 1.2
32-lead LQFP
SECTION A-A
Dimensions
Symbol
Inches
Min
Max
Millimeters
Min
Max
A
….
0.0630
…
1.6
A1
0.0020
0.0059
0.05
0.15
A2
0.0531
0.0571
1.35
1.45
D
0.3465
0.3622
8.8
9.2
D1
0.2717
0.2795
6.9
7.1
E
0.3465
0.3622
8.8
9.2
E1
0.2717
0.2795
6.9
7.1
L
0.0177
0.0295
0.45
0.75
L1
0.03937 REF
1.00 REF
T
0.0035
0.0079
0.09
0.2
T1
0.0038
0.0062
0.097
0.157
b
0.0118
0.0177
0.30
0.45
b1
0.0118
0.0157
0.30
0.40
R0
0.0031
0.0079
0.08
0.20
e
a
0.031 BASE
0°
7°
0.8 BASE
0°
7°
Low Voltage 1:18 Clock Distribution Chip
Notice: The information in this document is subject to change without notice.
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ASM2I9940L
April 2007
rev 1.2
Ordering Information
Marking
Part Number
Package Type
Operating Range
ASM2P9940LG-32-LT
ASM2P9940LGL
32-pin LQFP, Tray, Green
Commercial
ASM2P9940LG-32-LR
ASM2P9940LGL
32-pin LQFP, Tape and Reel, Green
Commercial
ASM2P9940LG-32-ET
ASM2P9940LGE
32-pin TQFP, Tray, Green
Commercial
ASM2P9940LG-32-ER
ASM2P9940LGE
32-pin TQFP ,Tape and Reel, Green
Commercial
ASM2I9940LG-32-LT
ASM2I9940LGL
32-pin LQFP, Tray, Green
ASM2I9940LG-32-LR
ASM2I9940LGL
32-pin LQFP, Tape and Reel, Green
Industrial
ASM2I9940LG-32-ET
ASM2I9940LGE
32-pin TQFP, Tray, Green
Industrial
ASM2I9940LG-32-ER
ASM2I9940LGE
32-pin TQFP ,Tape and Reel, Green
Industrial
Industrial
Device Ordering Information
A S M 2 I 9 9 4 0 L G - 3 2 - L R
R = Tape & Reel, T = Tube or Tray
O = SOT
S = SOIC
T = TSSOP
A = SSOP
V = TVSOP
B = BGA
Q = QFN
U = MSOP
E = TQFP
L = LQFP
U = MSOP
P = PDIP
D = QSOP
X = SC-70
DEVICE PIN COUNT
G = GREEN PACKAGE, LEAD FREE, and RoHS
PART NUMBER
X= Automotive
I= Industrial
P or n/c = Commercial
(-40C to +125C) (-40C to +85C)
(0C to +70C)
1 = Reserved
2 = Non PLL based
3 = EMI Reduction
4 = DDR support products
5 = STD Zero Delay Buffer
6 = Power Management
7 = Power Management
8 = Power Management
9 = Hi Performance
0 = Reserved
PulseCore Semiconductor Mixed Signal Product
Licensed under US patent #5,488,627, #6,646,463 and #5,631,920.
Low Voltage 1:18 Clock Distribution Chip
Notice: The information in this document is subject to change without notice.
12 of 13
ASM2I9940L
April 2007
rev 1.2
PulseCore Semiconductor Corporation
1715 S. Bascom Ave Suite 200
Campbell, CA 95008
Tel: 408-879-9077
Fax: 408-879-9018
www.pulsecoresemi.com
Copyright © PulseCore Semiconductor
All Rights Reserved
Part Number: ASM2I9940L
Document Version: 1.2
Note: This product utilizes US Patent # 6,646,463 Impedance Emulator Patent issued to PulseCore Semiconductor, dated 11-11-2003
© Copyright 2007 PulseCore Semiconductor Corporation. All rights reserved. Our logo and name are trademarks or
registered trademarks of PulseCore Semiconductor. All other brand and product names may be the trademarks of their
respective companies. PulseCore reserves the right to make changes to this document and its products at any time without
notice. PulseCore assumes no responsibility for any errors that may appear in this document. The data contained herein
represents PulseCore’s best data and/or estimates at the time of issuance. PulseCore reserves the right to change or correct
this data at any time, without notice. If the product described herein is under development, significant changes to these
specifications are possible. The information in this product data sheet is intended to be general descriptive information for
potential customers and users, and is not intended to operate as, or provide, any guarantee or warrantee to any user or
customer. PulseCore does not assume any responsibility or liability arising out of the application or use of any product
described herein, and disclaims any express or implied warranties related to the sale and/or use of PulseCore products
including liability or warranties related to fitness for a particular purpose, merchantability, or infringement of any intellectual
property rights, except as express agreed to in PulseCore’s Terms and Conditions of Sale (which are available from
PulseCore). All sales of PulseCore products are made exclusively according to PulseCore’s Terms and Conditions of Sale.
The purchase of products from PulseCore does not convey a license under any patent rights, copyrights; mask works rights,
trademarks, or any other intellectual property rights of PulseCore or third parties. PulseCore does not authorize its products
for use as critical components in life-supporting systems where a malfunction or failure may reasonably be expected to result
in significant injury to the user, and the inclusion of PulseCore products in such life-supporting systems implies that the
manufacturer assumes all risk of such use and agrees to indemnify PulseCore against all claims arising from such use.
Low Voltage 1:18 Clock Distribution Chip
Notice: The information in this document is subject to change without notice.
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