COMIT Specification
COMIT
Computer On Module Interconnect TechnologyTM
SPECIFICATION
Revision 1.1
September 22, 2009
IMPORTANT INFORMATION AND DISCLAIMERS
The Small Form Factor Special Interest Group, Inc. (SFF-SIG) does not make any
warranties with regard to this Computer on Module Interconnect Technology (COMIT)
specification (“Specification”) and in particular, neither warrants nor represents that this
specification nor any products made in conformance with it will work in the intended
manner. Nor does the SFF-SIG assume responsibility for any errors that the
Specification may contain or have any liabilities or obligations for damages including, but
not limited to, special, incidental, indirect, punitive, or consequential damages whether
arising from or in connection with the use of this specification in any way.
No representation or warranties are made that any product based in whole or part on
this Specification will be free from defects or safe for use for its intended purposes. Any
person making, using, or selling such product does so at his or her own risk.
THE USER OF THIS SPECIFICATION HEREBY EXPRESSLY
ACKNOWLEDGES THAT THE SPECIFICATION IS PROVIDED “AS IS”, AND
THAT THE SFF-SIG MAKES NO REPRESENTATIONS, EXTENDS ANY
WARRANTIES OF ANY KIND, EITHER EXPRESS OR IMPLIED, ORAL, OR
WRITTEN, INCLUDING ANY WARRANTY OF MERCHANTABILITY OR
FITNESS FOR ANY PARTICULAR PURPOSE, OR WARRANTY OR
REPRESENTATION THAT THE SPECIFICATION OR ANY PRODUCT OR
TECHNOLOGY UTILIZING THE SPECIFICATION OR ANY SUBSET OF THE
SPECIFICATION WILL BE FREE FROM ANY CLAIMS OF INFRINGEMENT OF
ANY INTELLECTUAL PROPERTY, INCLUDING PATENTS, COPYRIGHT AND
TRADE SECRETS NOR DOES THE SFF-SIG ASSUME ANY
RESPONSIBILITIES WHATSOEVER WITH RESPECT TO THE
SPECIFICATION OR SUCH PRODUCTS. THE SFF-SIG DISCLAIMS ALL
LIABILITY, INCLUDING LIABILITY FOR INFRINGEMENT OF ANY
PROPRIETARY RIGHTS RELATING TO USE OF INFORMATION IN THIS
SPECIFICATION. NO LICENSE, EXPRESS OR IMPLIED BY ESTOPPEL, OR
OTHERWISE, TO ANY INTELLECTUAL PROPERTY RIGHTS IS GRANTED
HEREIN.
Designers must not rely upon the absence or characteristics of any features marked
“reserved”. The SFF-SIG reserves these for future definition and shall have no
responsibility whatsoever for conflicts or incompatibilities arising from future changes to
them.
COMIT and Computer On Module Interconnect Technology are trademarks and
Intellectual Property of the SFF-SIG. Other product names and trademarks,
registered trademarks, or service marks are property of their respective owners.
Please send comments via electronic mail to info@sff-sig.org.
Copyright 2009  Small Form Factor Special Interest Group, Inc.
COMIT Specification Revision 1.1
Copyright 2009, SFF-SIG
2
Revision History
Revision
1.0
1.1
Issue Date
Comments
March 2, 2009
Sept 22, 2009
Initial Release
Update pin definition for power architecture
COMIT Specification Revision 1.1
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3
Table of Contents
1.0
Introduction
5
1.1
General
5
1.2
Audience
5
1.3
Related Documents and Organizations
5
2.0
Acronyms and Terms
7
3.0
COMIT Connector
9
3.1
SEARAY™ Micro High Speed Series
9
3.1.1
Connector Stack Height
10
3.1.2
Connector Placement
10
3.2
4.0
5.0
Connector Pin Assignments
10
3.2.1
Connector Row A & B
12
3.2.2
Connector Row C & D
13
3.2.3
Connector Row E & F
14
3.3
COMIT Connector Signal Descriptions
15
3.4
COMIT Connector Physical Specifications
20
3.5
SEAF Connector Drawings
21
3.6
SEAM Connector Drawings
22
3.7
Auxiliary PATA connector
23
3.8
PATA Connector Pin Assignments
24
Recommended Design Practices
28
4.1
Implementing COMIT
28
4.2
COMIT General Layout Recommendations
28
4.3
COMIT USB Routing Recommendations
30
4.4
COMIT PCI Express Routing Recommendations
30
4.5
Power
31
4.5.1
COMIT Power Sequencing Requirements
31
4.5.2
COMIT Minimum Power
32
4.5.3
COMIT Maximum Power
32
4.5.4
COMIT Operating Power Modes
33
Name and Logo Use
COMIT Specification Revision 1.1
33
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4
1.0
Introduction
1.1
General
COMIT is an electromechanical connectorization specification for Computer On Module
(COM) processor products that integrate common high-speed and low-speed serial as
well as legacy expansion buses for next generation, small form factor products. It is a
modular, high-speed connector system composed of the most common high speed and
legacy interfaces available from modern low-power chipsets. The purpose is to provide
a compact, interoperable processor connection architecture for future embedded
systems designs.
COMIT supports different processors with a single baseboard, allowing easy migration to
future processors for performance/feature enhancement, and mitigating obsolescence
for either the processor or baseboard. COMIT is processor independent, focusing on
bus and interconnect technology rather than any single processor, DSP, or
microcontroller architecture.
The COMIT acronym stands for Computer On Module Interconnect Technology and is
pronounced “Com it”.
In a single connector, COMIT supports:












1.2
Three x1 (pronounced “by one”) PCI Express™ links
One x4 (“by four”) PCI Express link (optionally 4 divided into 4 additional x1 links)
Six high-speed USB 2.0 channels
VGA, digital video, and dual 18/24 bit LVDS video interfaces
Two SATA channels
One 10/100 or Gigabit Ethernet
One 8 bit SDIO
HD Audio
LPC (Low Pin Count) Bus
SPI/uWire, SMBus/I²C Bus
Power and ground
System clock and control signaling
Audience
This document is written for design engineers, technologists, and others that desire to
understand the basics of COMIT. It does not specify the connector mounting location or
application of the technology to any specific computer module or I/O board. That
information will be provided and explained in the specification that governs the
implementation of COMIT technology on the particular form-factor.
Since COMIT supports multiple high-speed differential serial buses, care must be
exercised with respect to best layout practice for high-speed signals. Please reference
the websites listed in the next section for their design recommendations. Also visit the
SFF-SIG website for any application notes or design guides that may be available.
COMIT Specification Revision 1.1
Copyright 2009, SFF-SIG
5
1.3
Related Documents and Organizations
I²C Specification
NXP Semiconductors Netherlands B.V. (formerly Philips Semiconductors)
Eindhoven, Netherlands
http://www.nxp.com/acrobat_download/literature/9398/39340011.pdf
Low Pin Count (LPC) Specification
Intel Corporation
Santa Clara, CA USA
http://www.intel.com/design/chipsets/industry/lpc.htm
MiniBlade Specification
Small Form Factor Special Interest Group
2784 Homestead Road #269
Santa Clara, CA 95051 USA
Phone: +1-650-961-2473
www.sff-sig.org
PCI Express Specification
PCI-SIG
3855 SW 153rd Drive
Beaverton, OR 97006 USA
Phone: +1-503-619-0569 Fax: +1-503-644-6708
www.pcisig.com
Samtec, Inc. (Connector data)
520 Park East Boulevard
New Albany, IN 47151-1147 USA
Phone: +1-812-944-6733 Fax: +1-812-948-5047
www.samtec.com
SFF-SIG
Small Form Factor Special Interest Group
2784 Homestead Road #269
Santa Clara, CA 95051 USA
Phone: +1-650-961-2473
www.sff-sig.org
SMBus Specification
System Management Interface Forum, Inc.
100 N. Central Expressway Suite 600
Richardson, Texas 75080-5323 USA
Fax: +1-972-238-1286
www.smbus.org
COMIT Specification Revision 1.1
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6
SPI
The SPI bus is a de facto standard, rather than one agreed by any international
committee. The reason for this is its essential simplicity. The best reference is
http://www.freescale.com/files/microcontrollers/doc/ref_manual/S12SPIV3.pdf
USB
USB Implementers Forum, Inc.
3855 SW 153rd Drive
Beaverton, OR 97006
www.usb.org
2.0
Acronyms and Terms
ATX-style
Refers to the power supply configuration that allows the computer to be
turned off via software. ATX power supplies have two separate five volt
signals, one that powers up and down with the system (+5V) and one that
stays powered all of the time unless the supply is disconnected from the
system power (+5VSB, standby) in order for the system to be capable of
waking up from network traffic, keyboard, etc.
FWH
Abbreviation for Firmware Hub.
I²C
The Inter-Integrated Circuit bus (I2C) is a patented interface developed by
Philips Semiconductors. The I2C bus is a half-duplex, synchronous, multimaster bus requiring only two signal wires: data and clock.
Lane
A PCI Express link is built around dedicated unidirectional couples of
serial (1-bit), point-to-point connections known as "lanes". PCI Express
lanes are full-duplex links, meaning that data can be transferred in both
directions simultaneously (Tx transmit and Rx receive lines are separate).
Link
A connection between any two PCI Express devices is known as a "link",
and is built up from a collection of one or more lanes. All devices must
minimally support single-lane (x1) link.
LPC Bus
Low Pin Count Bus –- It is used on embedded PCs to connect lowbandwidth devices to the CPU, such as the boot ROM and the "legacy"
I/O devices. The "legacy" I/O devices usually include serial ports, parallel
ports, keyboard, mouse, and floppy disk controller. Designers will benefit
from the reduced pin count because it uses less space and power, and is
more thermally efficient compared to ISA.
The LPC specification defines seven mandatory signals required for
bidirectional data transfer. Four of these signals carry the multiplexed
address and data. The other three are control signals (frame, reset, and
clock).
LVDS
Abbreviation for Low Voltage Differential Signaling which is used to
connect to flat panel displays.
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7
MiniBlade™
A removable Flash storage solution for embedded SBCs administered by
the SFF-SIG.
PCI Express It is a high-speed computer expansion card interface designed to replace
the general-purpose PCI expansion bus and is software compatible with
PCI in order to be transparent to system software. It is structured around
point-to-point full duplex serial links called lanes. In PCI Express version
1.1 (currently the most common version), each lane operates at a data
rate of 250 MB/s in each direction.
COMIT supports three single lanes and one quad lane of data between
the baseboard and expansion card. Lane counts are written with an “x”
prefix with “x1” designating a single-lane and ”x4” for a four-lane interface.
A x1 (pronounced “by one”) lane is very space efficient compared to the
parallel PCI bus that it replaces, with 2.5 times the bandwidth using only
five signals. Four lanes of 250 MB/s in a x4 link supports a maximum
transfer rate of 1 GB/s (250 MB/s x4) in each direction for PCIe 1.1.
PCIe
Abbreviation for PCI Express.
SATA
The Serial ATA computer bus is a high-speed serial interface for
connecting controllers to mass storage devices such as hard disks
SBC
Abbreviation for Single Board Computer.
SDVO
Serial Digital Video Out is a technology that allows additional video
signaling interfaces such as VGA and DVI monitor outputs, SDTV and
HDTV television outputs, or TV tuner inputs to a system board
SFF-SIG
The Small Form Factor Special Interest Group is an independent nonprofit industry group that develops, promotes, and supports small form
factor circuit board, I/O, and storage specifications with long-term stability
in mind.
SEARAY™
The name of a 0.50” [1.27mm] pitch high density, high–speed board-toboard interconnect system.
SMBus
System Management Bus – A simple two-wire bus, derived from I²C and
used in the x86 architecture for communication with low-bandwidth
devices such as memory sticks, clock generators, and temperature
sensors.
SPI
Serial Peripheral Interface Bus –- A synchronous serial data link standard
named by Motorola that operates in full duplex mode.
SUMIT™
Abbreviation for Stackable Unified Module Interconnect Technology
specification administered by the SFF-SIG.
COMIT Specification Revision 1.1
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8
USB
Universal Serial Bus –- It is a serial bus designed to allow peripherals to
be connected using a single standardized interface which replaces certain
legacy varieties of serial and parallel ports.
uWire
Microwire is a three-wire synchronous interface developed by National
Semiconductor. The Microwire protocol is essentially a subset of the SPI
interface. Microwire/Plus with alternate shift clock is compatible with SPI
mode 0. Microwire with standard shift clock is compatible with SPI mode
1.
3.0
COMIT Connector
3.1
SEARAY Series High Speed Board-to-Board Interconnect
Computer On Module connector requirements for modern chipsets used in rugged
environments represent a significant challenge for the connector vendor. For PCI
Express 2.0 and USB3 signaling requirements, connectors should be selected with
bandwidth well in excess of the 5GT/S requirements of both. Connectors must also be
very dense for these applications as both the module and chip scales shrink.
Connectors that combine the best speed and density often fall short as far as reliability in
rugged applications, or are very expensive.
The SEARAY connector from Samtec embodies all of the requirements- high speed,
high pin density, rugged and low cost. It is a 240-pin high-density (0.050-inch pitch)
SEAM/SEAF connector pair. The connector series is second sourced by Molex.
SEARAY is designed as an open pin field array configuration organized as six rows of
40 gold-plated pins to allow optimal routing and maximum design flexibility. The chosen
connector system is capable of a differential signaling rate of 9 GHz bandwidth (at -3dB
insertion loss) to support current and future high speed signaling for interfaces like PCI
Express Gen2 and USB3.
SEAM: ASP-140867-01
SEAF: ASP-140868-01
SEARAY Connectors from Samtec
The contacts in the SEARAY system are robust and allow for “zippering” when mating
and unmating the connectors. This contact design lowers the insertion and extraction
forces which is an important consideration with 240 pins. Each pin is rated for 2.7 Amps
and the connector will operate over the temperature range of -55°C to +125°C. The
COMIT Specification Revision 1.1
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9
rugged connector system is good for over 2000 mating cycles, is RoHS compliant, and is
ideal for industrial environments.
The SEARAY connector series are specified for use with or without standoffs. The
mated height of the connector pair is 8.5mm without standoffs, 8.65mm with standoffs.
The SEAF standard part number is ASP-140868-01 (Std. Part: SEAF-40-05.0-S-06-2-A,
processor board) and the SEAM standard part number is ASP-140867-01 (Std. Part:
SEAM-40-03.5-S-06-2-A, baseboard).
Detailed data sheets can be found at
http://www.samtec.com/search/comit.aspx.
3.1.1 Connector Stack Height
The stack height is measured from the top of the baseboard to the bottom of the
processor module (assuming the processor is on top). An 8.5mm mated connector
height has been chosen to allow for component height between processor and
baseboard while minimizing overall height.
For non-rugged applications, the SEAF/SEAM connector pair is specified to be used
without standoffs at an 8.5mm nominal height. For rugged configurations, the 8.5mm
version of the SEAF/SEAM connector pair is engineered to optimize manufacturing
tolerances of standoff hardware and their buildup in COM and mezzanine module
implementations using the same connectors.
Samtec manufactures a standoff
specifically for the 8.5mm SEAF/SEAM pair that is 8.65mm overall with male 4-40
threads on one end, female on the other. The use of this 8.65mm standoff height is
specifically tailored to the mechanical requirements of the SEAF/SEAM pair and
produces an extremely rugged connector solution. The 8.65mm standoff part number
from Samtec is ASP-144136-01.
Component maximum height is specified to be 5.4mm for the processor module (on the
COMIT connector side) and 3.0mm maximum height for the baseboard (again on the
COMIT connector side). These specifications apply for the entire area between the two
boards to prevent mechanical interference issues when modules are plugged into
baseboards.
3.1.2 Connector Placement
The SEAF is the connector on the COMIT processor module and the SEAM is the
baseboard connector. This specification does not address the location (placement)
requirements for any specific form factor. Please refer to the separate form factor
specifications for detailed COMIT connector placement information.
3.2
Connector Pin Assignments
COMIT was designed to support x86 architectures as well as any other processor or
DSP requiring the unique mix of interfaces available on the COMIT connector. As long
as the design guidelines for interfacing are followed, DSPs, micros, MIPS, RISC, and
COMIT Specification Revision 1.1
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10
other non-x86 processor architectures are all compatible. This enables the unique ability
to connect either an x86, DSP, or Xscale processor module to the same baseboard for a
diverse product offering if desired.
COMIT connector pin assignments are optimized for signal integrity, relative layout ease,
and optimal routing with small form factor chipset and processor solutions available from
Intel and VIA Technologies. Implementation of other chipsets and architectures are
supported as well.
COMIT is engineered to be completely complimentary to the SUMIT, MiniBlade, and
other architectures developed and published by the SFF-SIG.
COMIT Baseboard SEAM Connector Pin Locations
COMIT Specification Revision 1.1
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11
3.2.1 I/O Connector Row A and Row B Pin Assignments
Pin A1
Pin A2
Pin A3
Pin A4
Pin A5
Pin A6
Pin A7
Pin A8
Pin A9
Pin A10
Pin A11
Pin A12
Pin A13
Pin A14
Pin A15
Pin A16
Pin A17
Pin A18
Pin A19
Pin A20
Pin A21
Pin A22
Pin A23
Pin A24
Pin A25
Pin A26
Pin A27
Pin A28
Pin A29
Pin A30
Pin A31
Pin A32
Pin A33
Pin A34
Pin A35
Pin A36
Pin A37
Pin A38
Pin A39
Pin A40
C_PERn0
C_PERp0
GND
C_PETn0
C_PETp0
CPRSNT#/GND
C_CLKn
C_CLKp
GND
A_PERn0
A_PERp0
GND
A_PETn0
A_PETp0
APRSNT#/GND
A_CLKn
A_CLKp
GND
B_PERn0
B_PERp0
GND
B_PETn0
B_PETp0
BPRSNT#/GND
B_CLKn
B_CLKp
GND
D_PETn3
D_PETp3
GND
D_PETn2
D_PETp2
GND
D_PERn3
D_PERp3
GND
D_PERn1
D_PERp1
GND
PERST#
COMIT Specification Revision 1.1
Pin B1
Pin B2
Pin B3
Pin B4
Pin B5
Pin B6
Pin B7
Pin B8
Pin B9
Pin B10
Pin B11
Pin B12
Pin B13
Pin B14
Pin B15
Pin B16
Pin B17
Pin B18
Pin B19
Pin B20
Pin B21
Pin B22
Pin B23
Pin B24
Pin B25
Pin B26
Pin B27
Pin B28
Pin B29
Pin B30
Pin B31
Pin B32
Pin B33
Pin B34
Pin B35
Pin B36
Pin B37
Pin B38
Pin B39
Pin B40
GND
USB4+
USB4GND
USB2+
USB2GND
USB0+
USB0GND
SDVO_R+
SDVO_RGND
SDVO_G+
SDVO_GGND
SDVO_INT+
SDVO_INTGND
SDVO_B+
SDVO_BGND
SDVO_CLK+
SDVO_CLKGND
SDVO_CNTDAT
SDVO_CNTLCLK
BL_ENA
LVDS_DDCDAT
LVDS_DDCCLK
GND
D_PETn1
D_PETp1
GND
D_PERn2
D_PERp2
GND
D_PERn0
D_PERp0
GND
Copyright 2009, SFF-SIG
12
3.2.2 I/O Connector Row C and Row D Pin Assignments
Pin C1
Pin C2
Pin C3
Pin C4
Pin C5
Pin C6
Pin C7
Pin C8
Pin C9
Pin C10
Pin C11
Pin C12
Pin C13
Pin C14
Pin C15
Pin C16
Pin C17
Pin C18
Pin C19
Pin C20
Pin C21
Pin C22
Pin C23
Pin C24
Pin C25
Pin C26
Pin C27
Pin C28
Pin C29
Pin C30
Pin C31
Pin C32
Pin C33
Pin C34
Pin C35
Pin C36
Pin C37
Pin C38
Pin C39
Pin C40
USB5+
USB5GND
USB3+
USB3GND
USB1+
USB1GND
SATA1_A+
SATA1_AGND
SATA1_B+
SATA1_BSATA1_SPINUP
GND
SATA0_SPINUP
SATA0_A+
SATA0_AGND
SATA0_B+
SATA0_BGND
ENET_X0+
ENET_X0GND
ENET_X1+
ENET_X1GND
ENET_X2+
ENET_X2GND
ENET_X3+
ENET_X3GND
D_CLKn
D_CLKp
DPRSNT#/GND
D_PETn0
D_PETp0
COMIT Specification Revision 1.1
Pin D1
Pin D2
Pin D3
Pin D4
Pin D5
Pin D6
Pin D7
Pin D8
Pin D9
Pin D10
Pin D11
Pin D12
Pin D13
Pin D14
Pin D15
Pin D16
Pin D17
Pin D18
Pin D19
Pin D20
Pin D21
Pin D22
Pin D23
Pin D24
Pin D25
Pin D26
Pin D27
Pin D28
Pin D29
Pin D30
Pin D31
Pin D32
Pin D33
Pin D34
Pin D35
Pin D36
Pin D37
Pin D38
Pin D39
Pin D40
LPC_AD2
SERIRQ#
LPC_AD1
LPC_AD0
LPC_AD3
LPC_FRAME#
LPC_DRQ
CLK_33MHZ
LVDS_PWR_EN
GND
LVDS0_CLK+
LVDS0_CLK3.3V
LVDS0_Y3+
LVDS0_Y33.3V
LVDS0_Y2+
LVDS0_Y23.3V
LVDS0_Y1+
LVDS0_Y13.3V
LVDS0_Y0+
LVDS0_Y03.3V
LVDS1_CLK+
LVDS1_CLK+5V
LVDS1_Y3+
LVDS1_Y3+5V
LVDS1_Y2+
LVDS1_Y2+5V
LVDS1_Y1+
LVDS1_Y1+5V
LVDS1_Y0+
LVDS1_Y0GND
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13
3.2.3 I/O Connector Row E and Row F Pin Assignments
Pin E1
Pin E2
Pin E3
Pin E4
Pin E5
Pin E6
Pin E7
Pin E8
Pin E9
Pin E10
Pin E11
Pin E12
Pin E13
Pin E14
Pin E15
Pin E16
Pin E17
Pin E18
Pin E19
Pin E20
Pin E21
Pin E22
Pin E23
Pin E24
Pin E25
Pin E26
Pin E27
Pin E28
Pin E29
Pin E30
Pin E31
Pin E32
Pin E33
Pin E34
Pin E35
Pin E36
Pin E37
Pin E38
Pin E39
Pin E40
CLK14
RSTBTN#
PWRBTN#
SLP_S3#
SLP_S4/S5#
ALLSYS_PWRGOOD
SMI
WAKE#
VBAT
Reserved
+3.3VSB
SPI/uWire_DO
SPI/uWire_DI
SPI/uWire_CLK
SPI/uWire_CS0#
SPI/uWire_CS1#
USB_OC#
USB_EN
USB_CLIENTDET
RXD
TXD
LED0
LED1
GND
VGA_R
VGA_G
VGA_B
VGA_HS
VGA_VS
VGA_DDCDAT
VGA_DDCCLK
Reserved
+5VSB
+5VSB
+5V
+5V
+5V
+5V
+5V
+5V
COMIT Specification Revision 1.1
Pin F1
Pin F2
Pin F3
Pin F4
Pin F5
Pin F6
Pin F7
Pin F8
Pin F9
Pin F10
Pin F11
Pin F12
Pin F13
Pin F14
Pin F15
Pin F16
Pin F17
Pin F18
Pin F19
Pin F20
Pin F21
Pin F22
Pin F23
Pin F24
Pin F25
Pin F26
Pin F27
Pin F28
Pin F29
Pin F30
Pin F31
Pin F32
Pin F33
Pin F34
Pin F35
Pin F36
Pin F37
Pin F38
Pin F39
Pin F40
SDIO_D0
SDIO_D1
SDIO_D2
SDIO_D3
SDIO_D4
SDIO_D5
SDIO_D6
SDIO_D7
SDIO_CMD
SDIO_CLK
SDIO_WP
SDIO_CD#
SDIO_LED
SDIO_PWR
Reserved
Reserved
HAD_RST#
HDA_SYNC
HDA_SDO
HDA_SDI
HDA_CLK
HDA_SPKR
Reserved
SMB/I2C_DATA
SMB/I2C_CLK
SMB/I2C_ALERT#
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Copyright 2009, SFF-SIG
14
3.3
COMIT Connector Signal Descriptions
PCI Express
Signal Name
A_PETp0
A_PETn0
A_PERp0
A_PERn0
A_CLKp
A_CLKn
APRSNT#/GND
B_PETp0
B_PETn0
B_PERp0
B_PERn0
B_CLKp
B_CLKn
BPRSNT#/GND
C_PETp0
C_PETn0
C_PERp0
C_PERn0
C_CLKp
C_CLKn
CPRSNT#/GND
D_PETp0
D_PETn0
D_PERp0
D_PERn0
D_PETp1
D_PETn1
D_PERp1
D_PERn1
D_PETp2
D_PETn2
D_PERp2
D_PERn2
D_PETp3
D_PETn3
D_PERp3
D_PERn3
D_CLKp
D_CLKn
DPRSNT#/GND
PERST#
Pin #
A14
A13
A11
A10
A17
A16
A15
A23
A22
A20
A19
A26
A25
A24
A5
A4
A2
A1
A8
A7
A6
C40
C39
B39
B38
B33
B32
A38
A37
A32
A31
B36
B35
A29
A28
A35
A34
C37
C36
C38
A40
COMIT Specification Revision 1.1
Description
PCIe link A, lane 0, Diff Pair transmit positive pin
PCIe link A, lane 0, Diff Pair transmit negative pin
PCIe link A, lane 0, Diff Pair receive positive pin
PCIe link A, lane 0, Diff Pair receive negative pin
PCIe link A, clock Diff Pair positive pin
PCIe link A, clock Diff Pair negative pin
PCIe link A card present signal (driven by I/O card)
PCIe link B, lane 0, Diff Pair transmit positive pin
PCIe link B, lane 0, Diff Pair transmit negative pin
PCIe link B, lane 0, Diff Pair receive positive pin
PCIe link B, lane 0, Diff Pair receive negative pin
PCIe link B, clock Diff Pair positive pin
PCIe link B, clock Diff Pair negative pin
PCIe link C card present signal (driven by I/O card)
PCIe link C, lane 0, Diff Pair transmit positive pin
PCIe link C, lane 0, Diff Pair transmit negative pin
PCIe link C, lane 0, Diff Pair receive positive pin
PCIe link C, lane 0, Diff Pair receive negative pin
PCIe link C, clock Diff Pair positive pin
PCIe link C, clock Diff Pair negative pin
PCIe link C card present signal (driven by I/O card)
PCIe link D, lane 0, Diff Pair transmit positive pin
PCIe link D, lane 0, Diff Pair transmit negative pin
PCIe link D, lane 0, Diff Pair receive positive pin
PCIe link D, lane 0, Diff Pair receive negative pin
PCIe link D, lane 1, Diff Pair transmit positive pin
PCIe link D, lane 1, Diff Pair transmit negative pin
PCIe link D, lane 1, Diff Pair receive positive pin
PCIe link D, lane 1, Diff Pair receive negative pin
PCIe link D, lane 2, Diff Pair transmit positive pin
PCIe link D, lane 2, Diff Pair transmit negative pin
PCIe link D, lane 2, Diff Pair receive positive pin
PCIe link D, lane 2, Diff Pair receive negative pin
PCIe link D, lane 3, Diff Pair transmit positive pin
PCIe link D, lane 3, Diff Pair transmit negative pin
PCIe link D, lane 3, Diff Pair receive positive pin
PCIe link D, lane 3, Diff Pair receive negative pin
PCIe link D, clock Diff Pair positive pin
PCIe link D, clock Diff Pair negative pin
PCIe link D card present signal (driven by I/O card)
PCI Express reset signal
Copyright 2009, SFF-SIG
15
USB
Signal Name
USB0+
USB0USB1+
USB1USB2+
USB2USB3+
USB3USB4+
USB4USB5+
USB5USB_OC#
USB_EN#
USB_CLIENTDET
SATA Port 0
Signal Name
SATA0_A+
SATA0_ASATA0_B+
SATA0_BSATA0_SPINUP
SATA Port 1
Signal Name
SATA1_A+
SATA1_ASATA1_B+
SATA1_BSATA1_SPINUP
Pin #
B8
B9
C7
C8
B5
B6
C4
C5
B2
B3
C1
C2
E17
E18
E19
Pin #
C18
C19
C21
C22
C17
Pin #
C10
C11
C13
C14
C15
VGA
Signal Name
Pin #
VGA_R
VGA_G
VGA_B
VGA_HS
VGA_VS
VGA_DDCDAT
VGA_DDCCLK
E25
E26
E27
E28
E29
E30
E31
COMIT Specification Revision 1.1
Description
USB Channel 0 Diff Pair positive
USB Channel 0 Diff Pair negative
USB Channel 1 Diff Pair positive
USB Channel 1 Diff Pair negative
USB Channel 2 Diff Pair positive
USB Channel 2 Diff Pair negative
USB Channel 3 Diff Pair positive
USB Channel 3 Diff Pair negative
USB Channel 4 Diff Pair positive
USB Channel 4 Diff Pair negative
USB Channel 5 Diff Pair positive
USB Channel 5 Diff Pair negative
USB Channels Overcurrent flag (wire OR)
USB Channels Enable Output (wire OR)
USB Channel Client Detect Input
Description
SATA Data Diff Pair A Positive
SATA Data Diff Pair A Negative
SATA Data Diff Pair B Positive
SATA Data Diff Pair B Negative
SATA Spin Up Signal
Description
SATA Data Diff Pair A Positive
SATA Data Diff Pair A Negative
SATA Data Diff Pair B Positive
SATA Data Diff Pair B Negative
SATA Spin Up Signal
Description
VGA Red
VGA Green
VGA Blue
VGA Horizontal Sync
VGA Vertical Sync
VGA PnP Data
VGA PnP Clock
Copyright 2009, SFF-SIG
16
LVDS Port 0
Signal Name
Pin #
LVDS0_Y0+
LVDS0_Y0LVDS0_Y1+
LVDS0_Y1LVDS0_Y2+
LVDS0_Y2LVDS0_Y3+
LVDS0_Y3LVDS0_CLK+
LVDS0_CLK-
D23
D24
D20
D21
D17
D18
D14
D15
D11
D12
LVDS Port 1
Signal Name
Pin #
LVDS1_Y0+
LVDS1_Y0LVDS1_Y1+
LVDS1_Y1LVDS1_Y2+
LVDS1_Y2LVDS1_Y3+
LVDS1_Y3LVDS1_CLK+
LVDS1_CLK-
D38
D39
D35
D36
D32
D33
D29
D30
D26
D27
LVDS Control
Signal Name
Pin #
LVDS_DDCDAT
LVDS_DDCCLK
BL_ENA
LVDS_PWR_EN
B29
B30
B28
D9
Digital Video
Signal Name
SDVO_R+
SDVO_RSDVO_G+
SDVO_GSDVO_B+
SDVO_BSDVO_INT+
SDVO_INTSDVO_CLK+
SDVO_CLKSDVO_CNTDAT
SDVO_CNTCLK
Pin #
B11
B12
B14
B15
B20
B21
B17
B18
B23
B24
B26
B27
COMIT Specification Revision 1.1
Description
LVDS Data Diff Pair 0 Positive
LVDS Data Diff Pair 0 Negative
LVDS Data Diff Pair 1 Positive
LVDS Data Diff Pair 1 Negative
LVDS Data Diff Pair 2 Positive
LVDS Data Diff Pair 2 Negative
LVDS Data Diff Pair 3 Positive
LVDS Data Diff Pair 3 Negative
LVDS Clock Diff Pair 0 Positive
LVDS Clock Diff Pair 0 Negative
Description
LVDS Data Diff Pair 0 Positive
LVDS Data Diff Pair 0 Negative
LVDS Data Diff Pair 1 Positive
LVDS Data Diff Pair 1 Negative
LVDS Data Diff Pair 2 Positive
LVDS Data Diff Pair 2 Negative
LVDS Data Diff Pair 3 Positive
LVDS Data Diff Pair 3 Negative
LVDS Clock Diff Pair 0 Positive
LVDS Clock Diff Pair 0 Negative
Description
LVDS PnP Data
LVDS PnP Clock
LVDS Back Light Enable
LVDS Panel Power Enable
Description
SDVO Red Diff Pair Positive
SDVO Red Diff Pair Negative
SDVO Green Diff Pair Positive
SDVO Green Diff Pair Negative
SDVO Blue Diff Pair Positive
SDVO Blue Diff Pair Negative
SDVO Interrupt Diff Pair Positive
SDVO Interrupt Diff Pair Negative
SDVO Clock Diff Pair Positive
SDVO Clock Diff Pair Negative
SDVO Control Data
SDVO Control Clock
Copyright 2009, SFF-SIG
17
ETHERNET
Signal Name
Pin #
Description
ENET _X0+
ENET _X0ENET _X1+
ENET _X1ENET _X2+
ENET _X2ENET _X3+
ENET _X3LED0
LED1
C24
C25
C27
C28
C30
C31
C33
C34
E22
E23
ENET Data Diff Pair 0 Positive
ENET Data Diff Pair 0 Negative
ENET Data Diff Pair 1 Positive
ENET Data Diff Pair 1 Negative
ENET Data Diff Pair 2 Positive
ENET Data Diff Pair 2 Negative
ENET Data Diff Pair 3 Positive
ENET Data Diff Pair 3 Negative
ENET Link/Activity LED
ENET Speed LED
SDIO
Signal Name
Pin #
Description
SDIO_D0
SDIO_D1
SDIO_D2
SDIO_D3
SDIO_D4
SDIO_D5
SDIO_D6
SDIO_D7
SDIO_CMD
SDIO_CLK
SDIO_WP
SDIO_CD#
SDIO_LED
SDIO_PWR
HD Audio
Signal Name
HDA_SDO
HDA_SDI
HDA_CLK
HDA_RST#
HDA_SYNC
HDA_SPKR
SPI/uWire
Signal Name
SPI/uWire_DO
SPI/uWire_DI
SPI/uWire_CLK
SPI/uWire_CS0#
SPI/uWire_CS1#
F1
F2
F3
F4
F5
F6
F7
F8
F9
F10
F11
F12
F13
F14
Pin #
F19
F20
F21
F17
F18
F22
Pin #
E12
E13
E14
E15
E16
COMIT Specification Revision 1.1
SDIO Data 0
SDIO Data 1
SDIO Data 2
SDIO Data 3
SDIO Data 4
SDIO Data 5
SDIO Data 6
SDIO Data 7
SDIO Command
SDIO Clock
SDIO Write Protect
SDIO Card Detect
SDIO LED
SDIO Power enable Output
Description
HD Audio Serial Data Out
HD Audio Serial Data In
HD Audio Clock
HD Audio Reset
HD Audio Sync
Speaker out to CODEC
Description
Serial Data Out from Master, 3.3V
Serial Data In to Master, 3.3V
Serial Clock
Chip Select for Device 0
Chip Select for Device 1
Copyright 2009, SFF-SIG
18
SMBus/I²C
Signal Name
Pin #
SMB/I2C_DATA
SMB/I2C_CLK
SMB/I2C_ALERT#
F24
F25
F26
LPC
Signal Name
Pin #
LPC_AD0
LPC_AD1
LPC_AD2
LPC_AD3
LPC_FRAME#
SERIRQ#
LPC_DRQ
CLK_33MHz
D4
D3
D1
D5
D6
D2
D7
D8
System Control
Signal Name
ALLSYS_PWRGOOD
SLP_S3#
SLP_S4/S5#
PWRBTN#
SMI
CLK14
RSTBTN#
WAKE#
Serial
Signal Name
Pin #
E6
E4
E5
E3
E7
E1
E2
E8
Pin #
TXD
RXD
E21
E20
Power and Ground
Signal Name
+5V
+5VSB
+3VSB
+3.3V
VBAT
Ground
Description
SMBus Data
SMBus Clock
SMBus Interrupt Line In
Description
LPC Address, Data, and Control Line 0
LPC Address, Data, and Control Line 1
LPC Address, Data, and Control Line 2
LPC Address, Data, and Control Line 3
LPC Frame Signal to Start or Terminate Cycles
Serial IRQ for legacy interrupts
LPC DMA Request
33 MHz Clock Out
Description
S0 Power Good Signal
S3 Suspend to Ram Control
S4 Suspend to Disk / S5 Soft Off Control
Momentary - Power On Input
System Management Interrupt
14.31818 MHz Clock Output
Momentary - Reset Button Input
System Wake Signal
Description
Serial Data Out, 3.3V
Serial Data in, 3.3V
Pin #
D28, D31, D34, D37, E35, E36, E37, E38,
E39, E40
E33, E34
E11
D13, D16, D19, D22, D25
E9
E24, D10, D40, C3, C6, C9, C12, C16,
C20, C23, C26, C29, C32, C35, B1, B4,
B7, B10, B13, B16, B19, B22, B25, B31,
B34, B37, B40, A3, A9, A12, A18, A21,
A27, A30, A33, A36, A39
COMIT Specification Revision 1.1
Description
+5 volt power
Standby +5V (for ATX-style)
Standby +3V (for ATX-style)
+3.3 volt power
Battery Backup Supply 3.3V
Ground
Copyright 2009, SFF-SIG
19
Note: Ground is also present when the card present signal is asserted by I/O
cards that support PCI Express. This ground aids in preventing cross talk
on adjacent signal pairs.
Reserved Pins
Signal Name
Reserved
3.4
Pin #
E10, E32, F15, F16, F23, F27, F28,
F29, F30, F31, F32, F33, F34, F35,
F36, F37, F38, F39, F40
Description
Reserved for future use, Do Not
Connect
COMIT Connector Physical Specifications
Materials
Housing:
Contact:
RoHS Compliant:
Spec
LCP (Liquid Crystal Polymer)
Thermoplastic, UL Rated 94-V0
Copper Alloy
Yes
Contact Finish
Socket Interface:
Terminal Interface:
Underplate:
Spec
30 micro-inches Gold On Contact Area
30 micro-inches Gold On Contact Area
50 micro-inches Minimum of Nickel
Mechanical Performance
Insertion Force:
Withdrawal Force
Normal Force:
Durability:
Operating Temp:
Spec
14.7 lbs. maximum
18.9 lbs. minimum
63 gr. @ 0.009 Inches Deflection
500 mating/un-mating Cycles
-55°C to +125°C
Electrical Performance
Contact Resistance:
Contact Current Capacity:
Dielectric Strength:
Insulation Resistance:
Spec
6.9 milliohms max.
2.9 Amps @ 30°C Temp Rise
900 VAC
25,000 Meg Ohms Minimum
Solderability
Processing Temperature:
Spec
260°C Produces No Blistering, Distortion,
or Discoloration
High Frequency Performance
Single-Ended System
Impedance:
Differential Pair System
Impedance:
Differential Performance:
Spec
50 Ohms ±10%
COMIT Specification Revision 1.1
100 Ohms ±10%
9 GHz differential @ -3db insertion loss
Copyright 2009, SFF-SIG
20
3.5
SEAF Connector Drawings
COMIT Specification Revision 1.1
Copyright 2009, SFF-SIG
21
3.6
SEAM Connector Drawings
COMIT Specification Revision 1.1
Copyright 2009, SFF-SIG
22
3.7
Auxiliary PATA Connector
3.7.1 Rugged 2mm Board-to-Board Connectors
An auxiliary connector for PATA on COMIT has been defined that compliments the main
COMIT connector and provides for parallel ATA interface drives to be connected. This
connector is optional and may not be included on all implementations.
The TW (processor module) and SMM (baseboard) connector series from Samtec are
specified for use with or without standoffs. The mated height of the connector pair is
8.5mm without standoffs, 8.65mm with standoffs.
TW: ASP-140306-03
SMM: ASP-142677-02
The TW and SMM 2mm Connectors from Samtec
The TW standard part number is ASP-140306-03 (Std. Part: TW-22-XX-S-D-195-SM--A--P) and the SMM standard part number is ASP-142677-02 (Std. Part : SMM-122-02-SD-LC—P A) http://www.samtec.com/search/comit.aspx.
The 8.65mm standoff part number from Samtec is ASP-144136-01.
http://www.samtec.com/search/comit.aspx
3.7.2 Connector Placement
The TW series 2mm pin header is the PATA connector on the processor module and the
SMM rugged 2mm socket is the PATA baseboard connector for COMIT-based boards.
This specification does not address the location (placement) requirements for any
specific form factor. Please refer to the separate form factor specifications for detailed
COMIT connector placement information.
3.8
PATA Connector Pin Assignments
The PATA auxiliary connector for COMIT conforms to industry standard 2.5”, 2mm 44pin PATA connector pin out.
COMIT Specification Revision 1.1
Copyright 2009, SFF-SIG
23
3.8.1 PATA Connector Signal Descriptions
PCI Express
Signal Name
DD0
DD1
DD2
DD3
DD4
DD5
DD6
DD7
DD8
DD9
DD10
DD11
DD12
DD13
DD14
DD15
DA0
DA1
DA2
CS0#
CS1#
IRTRQ
IOR
IOW
IORDY
IOCS16
DMARQ
DMACK#
CSEL
DASP#
PDIAG#/CBLID#
RST#
+5V
GND
NC
RESERVED
Pin #
17
15
13
11
9
7
5
3
4
6
8
10
12
14
16
18
35
33
36
37
38
31
25
23
27
32
21
29
28
39
34
1
41,42
2, 19, 22, 24,
26, 30, 40, 43
20
44
COMIT Specification Revision 1.1
Description
PATA Data 0
PATA Data 1
PATA Data 2
PATA Data 3
PATA Data 4
PATA Data 5
PATA Data 6
PATA Data 7
PATA Data 8
PATA Data 9
PATA Data 10
PATA Data 11
PATA Data 12
PATA Data 13
PATA Data 14
PATA Data 15
PATA Address 0
PATA Address 1
PATA Address 2
PATA Chip Select 0
PATA Chip Select 1
Interrupt Request
IO Read
IO Write
IO Ready
(obsolete, now Reserved)
DMA Request
DMA Acknowledge
Cable Select
Device Active
Passed Diag/Cable Identifier
Reset
Power
Ground
No Connect
Reserved
Copyright 2009, SFF-SIG
24
3.8.2 PATA Connector Specifications
Materials
Housing:
Contact:
RoHS Compliant:
Spec
LCP (Liquid Crystal Polymer)
Thermoplastic, UL Rated 94-V0
Phosphor Bronze/ BeCu
Yes
Contact Finish
Socket Interface:
Terminal Interface:
Underplate:
Spec
30 micro-inches Gold On Contact Area
30 micro-inches Gold On Contact Area
50 micro-inches Minimum of Nickel
Mechanical Performance
Insertion Force
Withdrawal Force
Durability:
Operating Temp:
Spec
5.5 lbs. average
4.13 lbs. average
1000 mating/un-mating cycles
-55°C to +125°C
Electrical Performance
Contact Resistance:
Contact Current Capacity:
Dielectric Strength:
Insulation Resistance:
Spec
10 milliohms max.
3.0Amps @ 30°C Temp Rise
1000 VAC
5,000 Meg Ohms Minimum
Solderability
Processing Temperature:
Spec
260°C Produces No Blistering, Distortion,
or Discoloration
COMIT Specification Revision 1.1
Copyright 2009, SFF-SIG
25
3.8.3 PATA SMM Connector Drawings for use on a Baseboard
COMIT Specification Revision 1.1
Copyright 2009, SFF-SIG
26
3.8.4 PATA TW Connector Drawings for use on the COMIT
Processor Module
COMIT Specification Revision 1.1
Copyright 2009, SFF-SIG
27
4.0
Recommended Design Practices
4.1
Implementing COMIT
Products designed with COMIT technology can have multiple, diverse interconnect
buses in a single connector. Ultra-high speed, high speed, and moderate-to-low speed
interfaces can easily coexist on a single connector with a simple, conservative approach
to layout. Considerable effort has been made to ensure that routing on both processor
modules and baseboards are efficient. Consideration to design rules and limitations for
each respective interface has been given.
The following section is intended to help the designer identify areas for special
consideration and further research. This design guideline should by no means be
considered a complete reference, only a reasonable starting point. Following these
guidelines does not guarantee a successful design. There are many sources available
that discuss high-speed printed circuit board design, USB, or PCI Express specific
design guidelines. The following is no way an attempt to repeat this information or
instruct the designer in these areas. It merely touches on general guidelines that should
be observed, as well as some COMIT specific design rules.
Any designer building a processor module, SBC, or an expansion product with COMIT
technology should refer to the “Related Documents and Organizations” in Section 1.3 of
this Specification for links to applicable specifications and their governing bodies.
4.2
COMIT General Layout Recommendations
Component maximum height is specified to be 5.5mm for the processor module (on the
COMIT connector side) and 3.0mm maximum height for the baseboard (again on the
COMIT connector side). These specifications apply for the entire area between the two
boards to prevent mechanical interference issues when modules are plugged into
baseboards.
COMIT supports several common interfaces for low to moderate speed expansion
requirements. Industry standard serial interfaces include SMBus, I2C, SPI, Microwire,
and a UART. SMBus alert is included for power management alert functionality or
general SMBus interrupt usage. Two chip selects are included for SPI/uWire, which can
be expanded within the target device to any number needed. SPI and SMBus are
defined as 3.3V signaling. Five volt tolerant devices may be used as long as they do not
drive the SPI signals on the bus beyond the 3.3V nominal specification. The UART
signals are defined as 3.3V only. Level translators must be on the baseboard where
needed.
If more bandwidth is required, an LPC bus interface is also available that includes
SERIRQ signaling for interrupts and LDRQ for direct memory access transfers. The
LPC interface directly provides support for LPC and FWH devices, as well as is the only
remaining embedded interconnect solution for support of legacy ISA devices on new
processor products. A simple bridge chip on the baseboard or a transition board in a
SUMIT stack is all that is required for ISA. VGA, HD audio, digital video, LVDS, ENET,
COMIT Specification Revision 1.1
Copyright 2009, SFF-SIG
28
and SDIO interfaces are also included and must conform to industry standard routing
and layout guidelines.
Routing for all of these interfaces falls into “best design practice” for standard printed
circuit board layout. For more specific information, refer to the parent specification of
each interface referenced in Section 1.3, or to data available from the manufacturer for
the target device implemented.
COMIT General Layout and Routing considerations










Signal names on the connector are the context of the processor/chipset. (e.g. SPIDO
on the connector is the processor/chipset’s SPI Interface Data Out pin and should be
coupled to the final IO devices corresponding receive input pin)
The COMIT processor must include all input termination to the module. This includes
all control and interface input pull-up or pull-down termination.
The COMIT processor module must terminate all unused output signals at the
connector to ensure features not included on the baseboard are not left floating. (e.g.
LVDSEN, BLEN, and the LVDS data pairs must be terminated inactive if LVDS is not
supported on the processor; USB power enable must be terminated active if the
processor module does not include a bit for this function, inactive if unused; no
termination required on unused PCIe signals, etc).
The COMIT processor module must terminate all unused input signals at the
connector where necessary to ensure features not included on the base board do not
leave inputs floating at the connector to the processor module. (e.g. the baseboard
may not support over current on the USB channels, the processor must include a pull
up for this pin, no termination required on unused PCIe signals, etc).
All series termination must be on the processor module. This includes series
resistors for PATA, LVDS, etc. This is to minimize inter-compatibility issues when
mixing various combinations of processor modules and baseboards.
Ethernet interfaces on COMIT are specified to include magnetic on the processor
module. This mitigates issues with incompatibilities between various vendors and
speeds of interfaces and the large choice of magnetic configurations and packages.
For most applications, magnetics should be placed on the same side of the
processor module as the COMIT connector and adhere to the maximum 5.5mm
height specification.
If unused on the baseboard, 33MHz and 14.31818MHz clock signals should be
terminated into a resistor near the COMIT connector. Both of these signals are
specified to drive a maximum of two loads.
33MHz and 14.31818MHz clocks must be stable a minimum of 3 mS before PERST
goes inactive. This is to allow clock buffers on the base board to stabilize with
chipsets that gate these signals.
PWRGOOD, RSTBTN#, PWRBTN#, SMI, and WAKE# must be pulled up to +3.3V
on the processor module.
VBAT is battery backup for CMOS clock and low power non-volatile static RAM. It is
specified as 3.3V and must include diode-OR function on baseboard.
COMIT Specification Revision 1.1
Copyright 2009, SFF-SIG
29
4.3
COMIT USB Routing Recommendations
COMIT supports six USB signal pairs routed through the connector. Also, one
overcurrent and one enable signal for the six ports (wire OR) are included in the same
connector. Overcurrent is a 3.3V compatible signal and shall have termination included
on the processor module.
With a -3dB differential bandwidth specification at 9 GHz, COMIT is USB speed
independent. As of the release of this specification, all speeds of USB signaling are
compatible with the connectors used in COMIT. Both the manufacturer of the COMIT
connected USB host card and the baseboard or SUMIT connected USB target must
design to the respective specifications of the device used. USB OTG (On-The-Go)
compatible and USB slave devices may also be implemented with COMIT because a
USB client detect signal is included in the connector.
General routing recommendations and considerations for USB are commonly available.
COMIT specific implementations only need to ensure that these are met, and to observe
the recommendations below.
Recommended USB Implementation Guidelines:



COMIT specifies that USB power switches NOT be located on the COMIT processor
module unless the USB device connects directly to the processor module itself. Use
USB specific, active power switching devices located directly at the device or
connector leading off of the baseboard or SUMIT card. The use of polyfuse type
protection circuitry is acceptable but less desirable than active switches in embedded
systems because of the fast acting and in-rush limiting qualities of active devices.
Omitting protection for baseboard or SUMIT device connections is strongly
discouraged.
For designers of devices that consume more than 500 mA @5V continuous, refer to
Section 4.5 and to the specific COMIT enabled baseboard specifications for system
power considerations.
Ample bypassing and bulk decoupling at the switches on the baseboard is
mandatory to prevent system brown out or reset issues during USB hot swap device
insertion or power up.
4.4
COMIT PCI Express Routing Recommendations
COMIT supports PCI Express signaling. Three x1 and a single x4 links are supported in
the connector. Optionally, the x4 link can be divided into up to four additional x1 links for
a total of seven PCIe x1 links. One Card Present for each link, a separate clock pair for
each link (only 1 clock pair is provided for the x4 link whether used as a single link or as
four separate x1 links), and one common Wake signal is included in the pin definition for
COMIT.
PCI Express requires careful consideration when laying out a processor or I/O
expansion board. PCI Express Generation 1 is a 1.25 Gigabit per second differential
serial interface. With a maximum edge rate specified at 50 picoseconds, or 7 GHz,
routing is critical. Even at realized edge rates of ~100 picoseconds, attention to detail is
required for a successful design.
COMIT Specification Revision 1.1
Copyright 2009, SFF-SIG
30
When designing a printed circuit board for any extremely high-speed differential
signaling environment, the symmetry of the circuit is of utmost importance. Matching
each segment pair length, matching left hand and right hand turns for the pair, placing
vias or components symmetrically in the signal path, and routing the trace pair
symmetrically to these features are critical to minimize impedance, reflection, and flight
time mismatches that degrade signal quality at these frequencies.
Recommended PCI Express Implementation Guidelines:















Signal names on the connector are from the context of the processor/chipset. This is
consistent with the PCI Express specification. (e.g. PETp0 on the connector is the
processor board’s PCIe transmit positive pin and should be coupled to the I/O
device’s corresponding PCIe receive pin)
100 ohms ± 20% characteristic differential impedance
0.020” minimum space from differential pairs to adjacent conductors
Match signals of differential pair as closely as possible, 0.005” max per board
One via per card per signal plus one via each end for breakout
Vias placed symmetrically in the differential pair path
Capacitive coupling components placed as close as possible to transmitter and
placed symmetrically in the differential pair trace path
Match number of turns left and right, no sharp or 90 degree turns
Microstrip routing only over solid planes. (No routing over breaks in planes)
Stripline routing is not recommended unless using blind or back drilled vias to
eliminate the stub
Match lane to lane length within a link to ± 0.50” on COMIT processor module,
± 2.00” on baseboard and ± 0.50” on an expansion card
Maximum lane length on a processor module is 4.00” component to connector
(assumes FR4 type dielectric for loss and jitter budget)
Maximum lane length on a SBC is 10.00” connector to component or connector
(assumes FR4 type dielectric for loss and jitter budget)
Maximum lane length on an expansion card is 2.50” connector to component
(assumes FR4 type dielectric for loss and jitter budget)
Card present signals are grounded by the target device/card for the link(s) consumed
only.
4.5
COMIT Power
The COMIT Specification provides for ample power through the connector. Power is
supplied to the processor module through the COMIT connector on designated pins. It
is highly recommended that switching type power supplies be used to generate
processor module voltages necessary because of their excellent transient response and
their inherently high efficiency.
4.5.1 COMIT Power Sequencing
The COMIT Specification power sequencing requirements are defined to ensure module
reliability and cross-compatibility performance.
COMIT Specification Revision 1.1
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31
Start-up Power Sequence Requirements:
•
•
•
•
•
VBAT must come up at the same time or before +5VSB comes up
+5VSB must come up at the same time or before +3.3VSB comes up
+3.3VSB must come up at the same time or before +5V comes up
+5V must come up at the same time or before +3.3V comes up
ALLSYS_PWRGOOD must be active at the same time or after +3.3V comes up
Stop Power Sequence Requirements:
•
•
•
•
•
ALLSYS_PWRGOOD must be inactive at the same time or before +3.3V goes
down
+3.3V must go down at the same time or before +5V goes down
+5V must go down at the same time or before +3.3VSB goes down
+3.3VSB must go down at the same time or before +5VSB goes down
+5VSB must go down at the same time or before VBAT goes down
4.5.2 COMIT Minimum Power
The COMIT Specification does not specify the minimum power requirement a baseboard
must provide to processor modules. This will be specified within each standard formfactor mechanical specification to support the unique minimum requirements of each
size module. Please see the individual mechanical form-factor specification for more
information.
4.5.3 COMIT Maximum Power
Ample current carrying capacity is available from the COMIT connector for a wide variety
of applications and processors. The power available to the COMIT processor module
from the chosen baseboard solution must be specified by the vendor for the baseboard.
These limits may differ significantly from the total power available defined in the chart
below as a maximum of this specification. Power requirements in excess of the
baseboard available power specification, or greater than those listed below for the
COMIT connector capability, must be supplied by a secondary connector on the
processor module itself. Baseboard available power to the processor module will vary
from vendor to vendor, please consult the manufacturer’s documentation.
The following table describes the maximum continuous power available from the COMIT
connector for the processor module.
COMIT Connector Power Specifications
COMIT Connector Maximum Power:
+5V
+5VSB
+3VSB
+3.3V
VBAT
20 Amps continuous
4 Amps continuous
2 Amps continuous
10 Amps continuous
2 Amps continuous
COMIT Specification Revision 1.1
Copyright 2009, SFF-SIG
32
4.5.4 COMIT Operating Power Modes
The following table describes the various modes in which power to the module is
enabled.
COMIT Connector Baseboard Power Modes
Power
Rail
S0
S3
S4
S5
Notes:
+5V
ON
OFF
OFF
OFF Disable is SLP_S3# = 0
+3.3V
ON
OFF
OFF
OFF Disable is SLP_S3# = 0
+5VSB
ON
ON
ON
ON
Always on
+3VSB
ON
ON
ON
ON
Always on
Battery for CMOS and RTC
VBAT
ON
ON
ON
ON
backup
5.0
Name and Logo Use
The use of the COMIT logo is a privilege granted by the SFF-SIG to member companies
who believe their products comply with this Specification. Use of the logo by either
members or non-members implies such compliance. The SFF-SIG may revoke
permission to use logos if they are misused. The COMIT logo is as follows:
The CMYK colors are:
Green
Light Blue
Orange
Dark Blue
Black
C
55,
37,
0,
81,
0,
M
0,
7,
74,
61,
0,
Y
100,
3,
100,
0,
0,
K
0
0
0
0
100
The COMIT logo must be printed in black or color. The aspect ratio of the entire logo
must be maintained, but the size may be varied. Nothing may be added or deleted from
the COMIT logo. Permission is automatically granted to designated SFF-SIG members
only as stipulated on the most recent membership agreement during the period of time
for which their membership dues are paid.
The COMIT name and logo are trademarks of the Small Form Factor Special Interest
Group and must be acknowledged in all published literature and advertising material in
all media formats (i.e. print, electronic, web, etc.).
COMIT Specification Revision 1.1
Copyright 2009, SFF-SIG
33
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