DLP Design DLP-2232M datasheet

DLP Design DLP-2232M datasheet
DLP-2232M MODULE / EVALUATION KIT
1.0 Introduction
The DLP-2232M utilizes FTDI's third-generation USB UART/FIFO I.C., the FT2232C.
This low-cost development tool features two Multi-Purpose UART/FIFO controllers that
can be configured individually in several different modes. In addition to the UART
interface, FIFO interface, and Bit-Bang IO modes of the second-generation FT232BM
and FT245BM devices, the FT2232C offers a variety of additional modes of operation
including a Multi-Protocol Synchronous Serial Engine interface designed specifically for
synchronous serial protocols such as JTAG and SPI bus.
The DLP-2232M features a quality four-layer printed circuit board with a solid ground
plane, an integral 93C56 EEPROM on board for easy OEM customization and a standard
40-pin, 0.6in wide footprint. Integral power control and on-board MOSFET power
switch make the DLP-2232M a perfect choice for USB bus-powered, high-power designs
as well as self- and low-powered products.
Rev 1.4 (Nov 2005)
1
DLP-2232M
DLP Design, Inc.
1.1 Features Summary
• Single board, USB Dual Channel Serial / Parallel Ports with a variety of configurations
• Entire USB protocol handled on-board. No USB-specific firmware programming
required
• DLP-USB232M-style UART interface option with full Handshaking & Modem
interface signals
• UART Interface supports 7/8 bit data, 1/2 stop bits, and Odd/Even/Mark/Space/No
Parity
• Transfer Data Rate 300 to 1 Mega Baud (RS232)
• Transfer Data Rate 300 to 3 Mega Baud (TTL and RS422 / RS485)
• Auto Transmit Enable control for RS485 serial applications using TXDEN pin
• DLP-USB245M-style FIFO interface option with bi-directional data bus and simple 4wire handshake interface
• Transfer Data Rate up to 1 MegaByte / Second
• Enhanced Bit-Bang Mode interface option
• New Synchronous Bit-Bang Mode interface option
• New CPU-Style FIFO Interface Mode option
• New Multi-Protocol Synchronous Serial Engine (MPSSE) interface option
• New MCU Host Bus Emulation Mode option
• New Fast Opto-Isolated Serial Interface Mode option
• Interface mode and USB Description strings configurable in on-board EEPROM
• EEPROM Configurable in-circuit via USB
• Support for USB Suspend and Resume conditions via PWREN#, and SI/WUx pins
• Support for bus powered, self powered, and high-power bus powered USB
configurations
• Integrated Power-On-Reset circuit, with optional Reset input and Reset Output pins
• 5V and 3.3V logic IO Interfacing with independent level conversion on each channel
• USB Bulk or Isochronous data transfer modes
• 4.35V to 5.25V single supply operating voltage range
• UHCI / OHCI / EHCI host controller compatible
• USB 2.0 Full Speed (12 Mbits / Second) compatible
• Standard 40-pin, 0.6in wide footprint
VIRTUAL COM PORT (VCP) DRIVERS
• Windows 98 / 98 SE / 2000 / ME / XP
• Windows CE **
• MAC OS-8 and OS-9**
• MAC OS-X**
• Linux 2.40 and greater**
[ ** = In planning or under development ]
APPLICATION AREAS
• USB Dual Port RS232 Converters
• USB Dual Port RS422 / RS485
• Upgrading Legacy Peripheral Designs
• USB Instrumentation
• USB JTAG Programming
• USB to SPI Bus Interfaces
• USB Industrial Control
• Field Upgradeable USB Products
• Galvanically Isolated Products
With USB Interface
D2XX (Direct Drivers + DLL S/W
• Windows 98 / 98 SE / 2000 / ME / XP
Rev 1.4 (Nov 2005)
2
DLP-2232M
DLP Design, Inc.
1.2 General Description
The DLP-2232M module is a USB interface that incorporates the functionality of two
DLP-USB2xxM modules into a single 40-pin module. A single downstream USB port is
converted to two IO channels that can each be individually configured as a DLPUSB232M-style UART interface, or a DLP-USB245M-style FIFO interface, without the
need to add a USB hub.
There are also several new modes which can be enabled in the external EEPROM, or by
using DLL driver commands. These include Synchronous Bit-Bang Mode, a CPU-Style
FIFO Interface Mode, a Multi-Protocol Synchronous Serial Engine Interface Mode, MCU
Host Bus Emulation Mode, and Fast Opto-Isolated Serial Interface Mode. Additionally,
a new high output drive level option means that the device UART / FIFO IO pins will
drive out at around three times the normal power level, allowing the data bus to be shared
by several devices.
Classic BM-style Asynchronous Bit-Bang Mode is also supported, but has been enhanced
to give the user access to the device’s internal RD# and WR# strobes.
FTDI provides a royalty free Virtual Com Port (VCP) driver that makes the peripheral
ports look like a standard COM port to the PC. Most existing software applications
should be able interface with the Virtual Com Port simply by reconfiguring them to use
the new ports created by the driver. Using the VCP drivers, an application programmer
would communicate with the device in exactly the same way as they would a regular PC
COM port - using the Windows VCOMM API calls or a COM port library.
The FT2232C driver also incorporates the functions defined for FTDI’s D2XX drivers,
allowing applications programmers to interface software directly to the device using a
Windows DLL.
Rev 1.4 (Nov 2005)
3
DLP-2232M
DLP Design, Inc.
2.0 Features and Enhancements
The DLP-2232M incorporates all of the enhancements introduced for the second
generation DLP-USB232M and DLP-USB245M modules, summarized here:
• Two Individually Configurable IO Channels
Each of the DLP-2232M’s Channels (A and B) can be individually configured as a DLPUSB232M-style UART interface, or as a DL-USB245M-style FIFO interface.
Additionally, these channels can be configured in a number of special IO modes.
• Integrated Power-On-Reset (POR) circuit
The module incorporates an internal POR function. A RESET# pin is available to allow
external logic to reset the module where required, however for most applications this pin
can simply be left disconnected as the RESET input to the FT2232C is pulled to VCC
through a 47K resistor. A RSTOUT# pin is provided in order to allow the new POR
circuit to provide a stable reset to external MCU and other devices.
• Integrated level converter on UART / FIFO interface and control signals
Each channel of the DLP-2232M has its own independent VCCIO pin that can be
supplied by between 3V to 5V. This allows each channel’s output voltage drive level to
be individually configured. Thus allowing, for example, 3.3V logic to be interfaced to
the device without the need for external level converter I.C.’s.
• Improved power management control for high-power USB Bus Powered devices
The PWREN# pin of the FT2232C directly drives a P-Channel MOSFET for applications
where power switching of external circuitry is required. The BM pull down enable
feature (configured in the external EEPROM) is also retained. This will make the
module gently pull down on the FIFO / UART IO lines when the power is shut off
(PWREN# is high). In this mode, any residual voltage on external circuitry is bled to
GND when power is removed, thus ensuring that external circuitry controlled by
PWREN# resets reliably when power is restored.
• Support for Isochronous USB Transfers
Whilst USB Bulk transfer is usually the best choice for data transfer, the scheduling time
of the data is not guaranteed. For applications where scheduling latency takes priority
over data integrity such as transferring audio and low bandwidth video data, the DLP2232M offers the option of USB Isochronous transfer via configuration of bit in the
EEPROM.
• Send Immediate / Wake Up Signal Pin on each channel
There is a Send Immediate / Wake Up (SI/WU) signal pin on each of the two channels.
These combine two functions on one pin. If USB is in suspend mode (and remote
wakeup is enabled in the EEPROM), strobing this pin low will cause the device to
request a resume from suspend (WakeUp) on the USB Bus. Normally, this can be used
to wake up the Host PC. During normal operation, if this pin is strobed low any data in
the device RX buffer will be sent out over USB on the next Bulk-IN request from the
Rev 1.4 (Nov 2005)
4
DLP-2232M
DLP Design, Inc.
drivers regardless of the packet size. This can be used to optimize USB transfer speed for
applications that send small packets of data to the host PC.
• Programmable Receive Buffer Timeout
The TX buffer timeout is programmable over USB in 1ms increments from 1ms to
255ms, thus allowing the module to be better optimized for protocols requiring faster
response times from short data packets.
• Baud Rate Pre-Scaler Divisors
The DLP-2232M (UART mode) baud rate pre-scaler supports division by (n+0),
(n+0.125), (n+0.25), (n+0.375), (n+0.5), (n+0.625), (n+0.75) and (n+0.875) where n is an
integer between 2 and 16,384.
• USB 2.0 (full speed option)
An EEPROM based option allows the DLP-2232M to return a USB 2.0 device descriptor
as opposed to USB 1.1. Note: The device would be a USB 2.0 Full Speed device
(12Mb/s) as opposed to a USB 2.0 High Speed device (480Mb/s).
For more details on these features please see the FT232BM and FT245BM datasheets and
application notes.
In addition to the DLP-USB2xxM module features, the DLP-2232M incorporates the
following new features and interface modes:
• Enhanced Asynchronous Bit-Bang Interface
The DLP-2232M supports FTDI’s BM chip Bit Bang mode. In Bit Bang mode, the eight
FIFO data lines can be switched between FIFO interface mode and an 8-bit Parallel IO
port. Data packets can be sent to the device and they will be sequentially sent to the
interface at a rate controlled by an internal timer (equivalent to the baud rate prescaler).
With the DLP-2232M module, this mode has been enhanced so that the internal RD# and
WR# strobes are now brought out of the device which can be used to allow external logic
to be clocked by accesses to the Bit-Bang IO bus.
• Synchronous Bit-Bang Interface
With Synchronous Bit-Bang Mode, the device is only read when it is written to, as
opposed to asynchronously by the data rate generator. This makes it easier for the
controlling program to measure the response to an output stimulus, as the data returned is
synchronous to the output data.
• High Output Drive Level Capability
The IO interface pins can be made to drive out at 12 mA, instead of the normal 4 mA
allowing multiple devices to be interfaced to the bus.
Rev 1.4 (Nov 2005)
5
DLP-2232M
DLP Design, Inc.
• CPU-Style FIFO Interface
The CPU style FIFO interface is essentially the same function as the classic FT245
interface, however the bus signals have been redefined to make them easier to interface to
a CPU bus.
• Multi-Protocol Synchronous Serial Engine Interface (M.P.S.S.E.)
The Multi-Protocol Synchronous Serial Engine (MPSSE) interface is a new option
designed to interface efficiently with synchronous serial protocols such as JTAG and SPI
Bus. It is very flexible in that it can be configured for different industry standards, or
proprietary bus protocols. For instance, it is possible to connect one of the DLP-2232M’s
channels to an SRAM configurable FPGA as supplied by vendors such as Altera and
Xilinx. The FPGA device would normally be un-configured (i.e. have no defined
function) at power-up. Application software on the PC could use the MPSSE to
download configuration data to the FPGA over USB. This data would define the
hardware’s function and then, after the FPGA device is configured, the DLP-2232M can
switch back into FIFO interface mode to allow the programmed FPGA device to
communicate with the PC over USB. The other DLP-2232M channel would also be
available for other devices.
This approach would allow a customer to create a “generic” USB peripheral; who’s
hardware function can be defined under control of the application software. The FPGA
based hardware could be easily upgraded or totally changed simply by changing the
FPGA configuration data file. (See the FTDI MORPH-IC or DLP-Design DLP-2232PB
and DLP-2232SY development modules for practical examples)
• MCU Host Bus Emulation
This new mode combines the ‘A’ and ‘B’ bus interface to make the DLP-2232M
interface emulate a standard 8048 / 8051 style MCU bus. This allows peripheral devices
for these MCU families to be directly attached to the DLP-2232M with IO being
performed over USB with the help of MPSSE interface technology.
• Fast Opto-Isolated Serial Interface
A new proprietary FTDI protocol is designed to allow galvanically isolated devices to
communicate synchronously with the DLP-2232M using just 4 wires (two dual optoisolators). The peripheral circuitry controls the data transfer rate in both directions,
whilst maintaining full data integrity. Maximum USB full speed data rates can be
achieved. Both ‘A’ and ‘B’ channels can communicate over the same 4-wire interface if
desired.
Rev 1.4 (Nov 2005)
6
DLP-2232M
DLP Design, Inc.
3.0 DLP-2232M Module Simplified Block Diagram
MOSFET
Power
Switch
USB Type 'B'
connector to
Host PC/Mac
PWREN#
DP, DM
3.3 Volt LDO
FT2232C
Channel A
Multi-purpose UART /
FIFO Controller
40 Pin,
.6 inch
Header
Channel B
Multi-purpose UART /
FIFO Controller
6MHz Resonator
93C56
EEPROM
3.1 Functional Block Descriptions
• 6MHz Oscillator
The 6MHz Oscillator cell generates a 6MHz reference clock input to the x8 Clock
multiplier from an external 6MHz ceramic resonator.
• Multi-Purpose UART / FIFO Controllers
The Multi-purpose UART / FIFO controllers handle the transfer of data between the Dual
Port RX and TX buffers and the UART / FIFO transmit and receive registers. When
configured as a UART it performs asynchronous 7/8 bit parallel to serial and serial to
parallel conversion of the data on the RS232 (RS422 and RS485) interface. Control
signals supported by UART mode include RTS, CTS, DSR, DTR, DCD and RI. There
are also transmitter enable control signal pins (TXDEN) provided to assist with
interfacing to RS485 transceivers. RTS/CTS, DSR/DTR and X-On/X-Off handshaking
options are also supported. Handshaking, where required, is handled in hardware to
Rev 1.4 (Nov 2005)
7
DLP-2232M
DLP Design, Inc.
ensure fast response times. The UARTs also support the RS232 BREAK setting and
detection conditions.
• EEPROM Interface
The on-board 93C56 EEPROM allows each of the DLP-2232M module’s channels to be
independently configured as a serial UART (232 mode), or a parallel FIFO (245 mode).
The EEPROM is used to enable the CPU-style FIFO interface, and Fast Opto-Isolated
Serial interface modes. The EEPROM can also be used to customize the USB VID, PID,
Serial Number, Product Description Strings and Power Descriptor value of the DLP2232M for OEM applications. Other parameters controlled by the EEPROM include
Remote Wake Up, Isochronous Transfer Mode, Soft Pull Down on Power-Off and USB
2.0 descriptor modes.
The EEPROM is programmable in-circuit via USB using a utility program available from
both FTDI’s web site (www.ftdichip.com) and www.dlpdesign.com.
Rev 1.4 (Nov 2005)
8
DLP-2232M
DLP Design, Inc.
4.0 Module Pin-Out
40 Pin,
.6 inch
Header
40
C
32
22
T
F
1
6.000
20
USB 'B'
Type
Connector
21
Figure 2. Pin-Out (40 Pin DIP Header )
4.1 Pin Definitions
This section describes the operation of the DLP-2232M pins. Common pins are defined
in the first section and the I/O pins are defined by chip mode. More detailed descriptions
of the operation of the I/O pins are provided in section x. (was 9)
4.2 Common Pins
The operation of the following DLP-2232M pins stay the same, regardless of the
operating mode.
Pin# Signal
27
RSTIN#
Type
Input
26
RSTOUT#
Input
19
EXTVCC
PWR
Rev 1.4 (Nov 2005)
Description
Can be used by an external device to reset the FT2232C. If
not required, can be left disconnected.
Output of the internal Reset Generator. Stays high
impedance for ~5ms after VCC > 3.5V and the
internal clock starts up, then clamps it’s output to the 3.3V
output of the internal regulator.
Taking RESET# low will also force RSTOUT# to drive
low. RSTOUT# is NOT affected by a USB Bus Reset.
+4.35 to +5.25 volt VCC to the device core, LDO and nonUART / FIFO controller interface pins.
Device Analog Power Supply for the internal x8 clock
multiplier.
9
DLP-2232M
DLP Design, Inc.
18
VCCIOA
PWR
17
VCCIOB
PWR
20
PORTVCC PWR
16
VCCSW
PWR
21
VCCUSB
PWR
+3.0 to +5.25 volt VCC to the UART/FIFO Channel A
interface pins. When interfacing with 3.3V external logic
connect VCCIO to the 3.3V supply of the external logic,
otherwise connect to VCC to drive out at 5V CMOS level.
+3.0 volt to +5.25 volt VCC to the UART/FIFO Channel B
interface pins. When interfacing with 3.3V external logic
connect VCCIO to the 3.3V supply of the external logic,
otherwise connect to VCC to drive out at 5V CMOS level.
Power from USB port. Connect to EXTVCC if module is to
be powered by the USB port (typical configuration).
500mA maximum current available to USB adapter and
target electronics if USB device is configured for high
power.
Output of the MOSFET power switch, activated after
enumeration.
Filtered +3.0 volt to +5.25 volt EXTVCC from either the
host USB port or user supplied external power supply.
4.3 IO Pin Definitions by Chip Mode
The definition of the following pins vary according to the module’s mode:
Pin#
Generic
Pin
Name
232 UART
Mode
245
FIFO
Mode
40
39
38
37
36
35
34
33
32
31
30
29
28
ADBUS0
ADBUS1
ADBUS2
ADBUS3
ADBUS4
ADBUS5
ADBUS6
ADBUS7
ACBUS0
ACBUS1
ACBUS2
ACBUS3
SI/WUA
TXD
RXD
RTS#
CTS#
DTR#
DSR#
DCD#
RI#
TXDEN
SLEEP#
RXLED#
TXLED#
???
D0
D1
D2
D3
D4
D5
D6
D7
RXF#
TXE#
RD#
WR
SI/WUA
Rev 1.4 (Nov 2005)
Pin Definitions by Chip Mode *Note 2
Enhanced
CPU
Asynchronous MPSSE
FIFO
and
*Note 4
Interface Synchronous
Mode
Bit-Bang
Modes
D0
D0
TCK/SK
D1
D1
TDI/DU
D2
D2
TDO/D1
D3
D3
TMS/CS
D4
D4
GPIOL0
D5
D5
GPIOL1
D6
D6
GPIOL2
D7
D7
GPIOL3
CS#
WR# *Note 6 GPIOH0
A0
RD# *Note 6
GPIOH1
RD#
WR# *Note 7 GPIOH2
WR#
RD# *Note 7
GPIOH3
SI/WUA
SI/WUA
10
DLP-2232M
MCU Host
Bus
Enumeration
Mode
*Note 5
AD0
AD1
AD2
AD3
AD4
AD5
AD6
AD7
I/O0
I/O1
IORDY#
OSC
Fast
OptoIsolated
Serial
Mode
*Note 3
DLP Design, Inc.
Pin#
Generic
Pin
Name
232 UART
Mode
245
FIFO
Mode
13
12
11
10
9
8
7
6
5
4
3
2
1
BDBUS0
BDBUS1
BDBUS2
BDBUS3
BDBUS4
BDBUS5
BDBUS6
BDBUS7
BCBUS0
BCBUS1
BCBUS2
BCBUS3
SI/WUB
TXD
RXD
RTS#
CTS#
DTR#
DSR#
DCD#
RI#
TXDEN
SLEEP#
RXLED#
TXLED#
???
D0
D1
D2
D3
D4
D5
D6
D7
RXF#
TXE#
RD#
WR
SI/WUB
Pin Definitions by Chip Mode *Note 2
Enhanced
CPU
Asynchronous MPSSE
FIFO
and
*Note 4
Interface Synchronous
Mode
Bit-Bang
Modes
D0
D0
D1
D1
D2
D2
D3
D3
D4
D4
D5
D5
D6
D6
D7
D7
CS#
WR# *Note 8
A0
RD# *Note 8
RD#
WR# *Note 7
WR#
RD# *Note 7
SI/WUB
MCU Host
Bus
Enumeration
Mode
*Note 5
AD8
AD9
AD10
AD11
AD12
AD13
AD14
AD15
CS#
ALE
RD#
WR#
Fast
OptoIsolated
Serial
Mode
FSDI
FSCLK
FSDO
FSCTS
*Note 3
*Note 2 : 232 UART, 245 FIFO, CPU FIFO Interface, and Fast Opto-Isolated modes are
enabled in the external EEPROM. Enhanced Asynchronous and Synchronous Bit-Bang
modes, MPSSE, and MCU Host Bus Emulation modes are enabled using driver
commands.
*Note 3 : Channel A can be configured in another IO mode if channel B is in Fast OptoIsolated Serial Mode. If both Channel A and Channel B are in Fast Opto-Isolated Serial
Mode all of the IO will be on Channel B.
*Note 4 : MPSSE is Channel A only.
*Note 5 : MCU Host Bus Emulation requires both Channels.
*Note 6 : The Bit-Bang Mode (synchronous and asynchronous) WR# and RD# strobes
are on these pins when the main Channel mode is 245 FIFO, CPU FIFO interface, or Fast
Opto-Isolated Serial Modes.
*Note 7 : The Bit-Bang Mode (synchronous and asynchronous) WR# and RD# strobes
are on these pins when the main Channel mode is 232 UART Mode.
*Note 8 : The Bit-Bang Mode (synchronous and asynchronous) WR# and RD# strobes
are on these pins when the main Channel mode is 245 FIFO, CPU FIFO interface. BitBang mode is not available on Channel B when Fast Opto-Isolated Serial Mode is
enabled.
Rev 1.4 (Nov 2005)
11
DLP-2232M
DLP Design, Inc.
5.0 Mechanical Dimensions
Inches (mm)
0.05 typ.
( 1.3typ.)
2.2 typ.
(55.9 typ.)
0.1 typ.
(2.54 typ.)
0.25 typ.
(6.4 typ.)
0.65 typ.
(16.5 typ.)
0.25 typ.
(6.4typ.)
0.48 typ.
(12.2 typ.)
0.50 typ.
(12.7 typ.)
0.7 typ.
(17.8 typ.)
**
**Components on top and
bottom of PCB
0.6 typ.
(15.2 typ.)
0.36 typ.
(9.1 typ.)
0.7 typ.
(17.8 typ.)
Rev 1.4 (Nov 2005)
12
DLP-2232M
DLP Design, Inc.
6.0 Absolute Maximum Ratings
These are the absolute maximum ratings for the FT2232C device. Exceeding these may
cause permanent damage to the device.
• Storage Temperature …………………………………………..-65oC to + 150oC
• Ambient Temperature (Power Applied)……………………….. 0°C to 70°C
• VCC Supply Voltage …………………………………………..-0.5V to +6.00V
• DC Input Voltage - Inputs ……………………………………..-0.5V to VCC + 0.5V
• DC Input Voltage - High Impedance Bi-directional …………..-0.5V to VCC + 0.5V
• DC Output Current – Outputs…………………………………...24mA
• DC Output Current – Low Impedance Bi-directional ………….24mA
• Power Dissipation (VCC = 5.25V)……………………………..500mW
• Electrostatic Discharge Voltage (Human Body Model) (I < 1uA)…….+/- 3000V
• Latch Up Current (Vi = +/- 10V maximum, for 10 ms)………………+/-200mA
7.0 D.C. Characteristics
D.C. Characteristics (Ambient Temperature = 0 to 70°C)
Operating Voltage and Current
Parameter Description
Min Typ Max Units Conditions
Vcc1
VCC Operating Supply Voltage
4.35 5.0 5.25 V
Vcc2
VCCIO Operating Supply Voltage 3.0
5.25 V
Icc1
Operating Supply Current
25? mA
Normal Operation
Icc2
Operating Supply Current
??
200? uA
USB Suspend *Note 11
*Note 11 – Supply Current excludes the 200uA nominal drawn by the pull-up resistor on USBDP
IO Pin Characteristics (VCCIOx = 5.0V) *Note 12
Parameter
Voh
Vol
Vin
Vhys
Description
Output Voltage High
Output Voltage Low
Input Switching Threshold
Input Switching Hysteresis
Min
3.2
0.3
1.3
50
Typ
4.1
0.4
1.6
55
Max
4.9
0.6
1.9
60
Units
V
V
V
mV
Conditions
I source = 2mA
I sink = 2mA
*Note 13
IO Pin Characteristics (VCCIOx = 3.0 – 3.6V) *Note 12
Parameter Description
Min Typ Max Units Conditions
Voh
Output Voltage High
2.2
2.7 3.2
V
I source = 1mA
Vol
Output Voltage Low
0.3
0.4 0.5
V
I sink = 2mA
*Note 13
Vin
Input Switching Threshold
1.0
1.2 1.5
V
Vhys
Input Switching Hysteresis
20
25
30
mV
*Note 12 – Inputs have a 200K Ohm pull-up resistor to VCCIOx internal to the FT2232C.
*Note 13 – This is the standard output driver
RESET# and RSTOUT# Pin characteristics
Parameter
Vin
VHys
Voh
Vol
Description
Input Switching Threshold
Input Switching Hysteresis
Output Voltage High
Output Voltage Low
Rev 1.4 (Nov 2005)
Min
1.3
50
3.0
0.3
13
Typ
1.6
55
-
Max
1.9
60
3.6
0.6
Units
V
mV
V
V
Conditions
I source = 2mA
I sink = 2mA
DLP-2232M
DLP Design, Inc.
8.0 Standard Device Configuration Examples
8.1 USB Bus Powered and Self Powered Configuration
1
1
C
32
22
FT
40
C
32
22
T
F
40
6.000
6.000
External
5V
Supply
17
18
19
20
NC
21
Figure 8a - USB Bus Powered
Configuration
17
18
19
20
21
Figure 8b – Self Powered
Configuration
Figure 8a illustrates the DLP-2232M in a typical USB bus powered configuration. A
USB Bus Powered device gets its power from the USB bus. Basic rules for USB Bus
power devices are as follows –
a) On plug-in, the device must draw no more than 100mA
b) On USB Suspend the device must draw no more than 500uA.
c) A High Power USB Bus Powered Device (one that draws more than 100mA) should
use the on-board MOSFET to keep the current drawn by external circuitry to below
~70mA on plug-in and ~200uA on USB suspend.
d) A device that consumes more than 100mA cannot be plugged into a USB Bus Powered
Hub
e) No device can draw more that 500mA from the USB Bus. The power descriptor in the
EEPROM should be programmed to match the current draw required by the device.
A Ferrite Bead is connected in series with USB power to prevent noise from the device
and associated circuitry (EMI) being radiated down the USB cable to the host.
Figure 8b illustrates the DLP-2232M in a typical USB self powered configuration. A
USB Self Powered device gets its power from its own power supply and does not draw
current from the USB bus. The basic rules for USB Self power devices are as follows –
a) A Self-Powered device should not force current down the USB bus when the USB
Host or Hub Controller is powered down.
Rev 1.4 (Nov 2005)
14
DLP-2232M
DLP Design, Inc.
b) A Self-Powered device can take as much current as it likes during normal operation
and USB suspend as it has its own power source.
c) A Self-Powered device can be used with any USB Host and both Bus and Self
Powered USB Hubs.
The USB power descriptor option in the EEPROM should be programmed to a value of
zero (self powered).
To meet requirement a) the 1.5K pull-up resistor on USBDP is connected to RSTOUT#
as per the bus-power circuit. However, the USB Bus Power is used to control the
RESET# Pin of the FT2232C device. When the USB Host or Hub is powered up
RSTOUT# will pull the 1.5K resistor on USBDP to 3.3V, thus identifying the device as a
full speed device to USB. When the USB Host or Hub power is off, RESET# will go low
and the device will be held in reset. As RESET# is low, RSTOUT# will also be low, so
no current will be forced down USBDP via the 1.5K pull-up resistor when the host or hub
is powered down. Failure to do this may cause some USB host or hub controllers to
power up erratically.
When the DLP-2232M is in reset, the I/O interface pins all go tri-state. These pins
have 200K pull-up resistors to VCCIOx internal to the FT2232C, so they will gently pull
high unless driven by some external logic.
Note:
Rev 1.4 (Nov 2005)
15
DLP-2232M
DLP Design, Inc.
8.2 Interfacing to Microcontrollers
5V Microcontroller Systems
1
Microcontroller
40
1
40
VCC
External
5V
Supply
C
32
22
FT
C
32
22
FT
Microcontroller
6.000
6.000
External
5V
Supply
16
17
18
19
20
NC
21
16
17
18
19
20
Figure 10a - Bus Powered
1
21
Figure 10b - Self Powered
3.3 Volt Microcontroller Systems
3.3V
LDO
VCC
1
40
40
External
3.3V
Supply
Microcontroller
Microcontroller
VCC
External
5V
Supply
6.000
External
3.3V
Supply
3.3V
16
17
18
19
20
C
32
22
FT
C
32
22
FT
VCC
NC
21
Figure 10c - Bus Powered
6.000
16
17
18
19
20
21
Figure 10d - Self Powered
8.2.1 USB Bus-Powered, 5V Systems
Figure 10a shows how to configure the DLP-2232M to interface with a 5V
microcontroller. In this example, the USB port is the power source for VCCIOA and
VCCIOB, which in turn will cause the device interface IO pins on both channels to drive
out at the 5V level. In this configuration, the on-board MOSFET power switch controls
Rev 1.4 (Nov 2005)
16
DLP-2232M
DLP Design, Inc.
power to the microcontroller. Care must be taken to ensure all microcontroller circuitry,
when combined with the DLP-2232M circuitry, does not exceed the maximum available
current from the USB port of 500mA for a high-powered USB device.
8.2.2 USB Self-Powered, 5V Systems
Figure 10b is an example of a DLP-2232M USB self-powered design with 5V interface.
In this case, the VCCIOA and VCCIOB pins are supplied by an external 5V supply in
order to make both of the device’s IO channels drive out at 5V logic level, thus allowing
them to be connected to a 5V microcontroller or other external logic.
A USB self-powered design uses its own power supplies, and does not draw any of its
power from the USB bus. In such cases, no special care need be taken to meet the USB
suspend current (0.5 mA) as the device does not get it’s power from the USB port.
Note that if the SI/WUx pins are not being used they should be pulled up to the same
supply as their respective VCCIOx pin.
8.2.3 USB Bus-Powered, 3.3V Systems
Figure 10c shows how to configure the DLP-2232M to interface with a 3.3V
microcontroller. In this example, a discrete 3.3V regulator is used to supply the 3.3V
logic from the USB supply. VCCIOA and VCCIOB are connected to the output of the
3.3V regulator, which in turn will cause the device interface IO pins on both channels to
drive out at 3.3V level. It is also possible to have one IO interface channel driving out at
5V level, and the other at 3.3V level. In this case one of the VCCIOx pins would be
connected to 5V, and the other connected to 3.3V. For USB bus powered circuits, care
must be taken when selecting the regulator. The regulator must be capable of sustaining
its output voltage with an input voltage of 4.35 volts. A Low Drop Out (LDO) regulator
must be selected. An example of a regulator family that meets these requirements is the
MicroChip (Telcom) TC55 Series. These devices can supply up to 250mA current.
Note: It should be emphasized that the 3.3V supply, for VCCIOx in a bus powered design
with a 3.3V logic interface, should come from an LDO that is supplied by the USB bus,
not from any other source. Please also note that if the SI/WUx pins are not being used
they should be pulled up to the same supply as their respective VCCIOx pin.
8.2.4 USB Self-Powered, 3.3V Systems
Figure 10d is an example of a DLP-2232M USB self-powered design with 3.3V
interface. In this case, the VCCIOA and VCCIOB pins are supplied by an external 3.3V
supply in order to make both of the device’s IO channels drive out at 3.3V logic level,
thus allowing them to be connected to a 3.3V microcontroller or other external logic. It is
also possible to have one IO interface channel driving out at 5V level, and the other at
3.3V level. In this case one of the VCCIOx pins would be connected to 5V, and the other
connected to 3.3V.
Rev 1.4 (Nov 2005)
17
DLP-2232M
DLP Design, Inc.
A USB self-powered design uses its own power supplies, and does not draw any of its
power from the USB bus. In such cases, no special care need be taken to meet the USB
suspend current (0.5 mA) as the device does not get it’s power from the USB port.
Note that if the SI/WUx pins are not being used they should be pulled up to the same
supply as their respective VCCIOx pin.
9.0 Signal Descriptions By IO Mode and Interface Channel Configurations
9.1 232 UART Interface Mode Signal Descriptions and Interface
Configurations
When either Channel A or Channel B are in 232 UART mode the IO signal lines are
configured as follows:
Pin#
Signal
Type
Description
Channel A
40
39
38
37
Channel B
13
12
11
10
TXD
RXD
RTS#
CTS#
OUTPUT
INPUT
OUTPUT
INPUT
Transmit Asynchronous Data Output
Receive Asynchronous Data Input *Note 9
Request To Send Control Output / Handshake signal
Clear To Send Control Input / Handshake signal *Note
36
9
DTR#
OUTPUT
35
8
DSR#
INPUT
Data Terminal Ready Control Output / Handshake
signal
Data Set Ready Control Input / Handshake signal *Note
34
33
7
6
DCD#
RI#
INPUT
INPUT
9
9
Data Carrier Detect Control Input *Note 9
Ring Indicator Control Input. When the Remote Wake
up option is enabled in the EEPROM, taking RI# low
can be used to resume the PC USB Host controller
from suspend. *Note 9
*Note 9 : These pins are pulled to up VCCIO via 200K resistors in the FT2232C during
Reset and USB Suspend mode. These can be programmed to gently pull low during USB
suspend (PWREN# = “1”) by setting this option in the EEPROM.
Rev 1.4 (Nov 2005)
18
DLP-2232M
DLP Design, Inc.
9.2 245 FIFO Interface Mode Signal Descriptions and Configuration
When either Channel A or Channel B are in 245 FIFO mode, the IO signal lines are
configured as follows.
FIFO DATA BUS GROUP *Note 10
Pin#
Channel A
40
39
38
38
36
35
34
33
Channel B
13
12
11
10
9
8
7
6
Signal
Type
Description
D0
D1
D2
D3
D4
D5
D6
D7
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
FIFO Data Bus Bit 0
FIFO Data Bus Bit 1
FIFO Data Bus Bit 2
FIFO Data Bus Bit 3
FIFO Data Bus Bit 4
FIFO Data Bus Bit 5
FIFO Data Bus Bit 6
FIFO Data Bus Bit 7
FIFO CONTROL INTERFACE GROUP
Pin#
Signal
Type
Description
When high, do not read data from the FIFO. When
low, there is data available in the FIFO which can be
read by strobing RD# low then high again * Note 11
When high, do not write data into the FIFO. When
low, data can be written into the FIFO by transitioning
WR from high to low. * Note 11
Enables Current FIFO Data Byte on D0..D7 when low.
Fetches the next FIFO Data Byte (if available) from
the Receive FIFO Buffer when RD# goes from low to
high. * Note 10
Writes the Data Byte on the D0..D7 into the Transmit
FIFO Buffer on the falling edge of WR. * Note 10
The Send Immediate / WakeUp signal combines two
functions on a single pin. If USB is in suspend mode
(PWREN# = 1) and remote wakeup is enabled in the
EEPROM, strobing this pin low will cause the device
to request a resume on the USB Bus. Normally, this
can be used to wake up the Host PC.
During normal operation (PWREN# = 0), if this pin is
strobed low any data in the device TX buffer will be
sent out over USB on the next Bulk-IN request from
the drivers regardless of the pending packet size. This
can be used to optimize USB transfer speed for some
applications. Tie this pin to VCCIOx if not used.
Channel A
32
Channel B
5
RXF#
OUTPUT
31
4
TXE#
OUTPUT
30
3
RD#
INPUT
29
2
WR
INPUT
28
1
SI/WUx
INPUT
*Note 10: In Input Mode, these pins are pulled to VCCIOx via 200K resistors in the
FT2232C. These can be programmed to gently pull low during USB suspend
(PWREN# = “1”) by setting this option in the EEPROM.
*Note 11: During device reset, these pins are tri-state but pulled up to VCCIOx via 200K
resistors in the FT2232C.
Rev 1.4 (Nov 2005)
19
DLP-2232M
DLP Design, Inc.
9.3 245 FIFO Mode Timing Diagrams
9.3.1 FIFO Read Cycle Timing
T6
T5
RXF#
T2
T1
RD#
T4
T3
D[7...0]
Time
T1
T2
T3
T4
T5
T6
Valid Data
Min
50
50 + T6
20
0
0
80
Description
RD# Active Pulse Width
RD# to RD Pre-Charge Time
RD# Active to Valid Data ** Note 12
Valid Data Hold Time from RD# Inactive ** Note 12
RD# Inactive to RXF#
RXF# inactive after RD# cycle
Max
50
25
Unit
nS
nS
nS
nS
nS
nS
** Note 12: Load 30 pF
9.3.2 FIFO Write Cycle Timing
T12
T11
TXE#
WR
T9
D[7...0]
Time
T7
T8
T9
T10
T11
T12
T10
Valid Data
Min
50
50 + T12
20
0
5
80
Description
WR# Active Pulse Width
WR to WR Pre-Charge Time
Data Setup Time before WR inactive
Data Hold Time from WR Inactive
WR Inactive to TXE#
TXE# inactive after a read cycle
Rev 1.4 (Nov 2005)
T8
T7
20
DLP-2232M
Max
25
Unit
nS
nS
nS
nS
nS
nS
DLP Design, Inc.
9.4 Enhanced Asynchronous and Synchronous Bit-Bang Modes - Signal
Description and Interface Configuration
Bit-bang mode is a special DLP-2232M mode that changes the 8 IO lines on either or
both channels (A/B) into an 8 bit bi-directional bus. There are now two types of bit bang
modes - Enhanced Asynchronous, which is virtually the same as BM-style Bit-Bang
mode; and synchronous Bit-Bang mode, where data will only be read when the device is
written to. Bit-Bang mode is enabled by driver commands. When either Channel A or
Channel B are enabled in Enhanced Asynchronous Bit-Bang Mode, or Synchronous BitBang Mode the IO signal lines are configured as follows:
BIT-BANG DATA BUS GROUP *Note 10
Pin#
Channel A
40
39
38
38
36
35
34
33
Channel B
13
12
11
10
9
8
7
6
Signal
Type
Description
D0
D1
D2
D3
D4
D5
D6
D7
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
Bit-Bang Data Bus Bit 0
Bit-Bang Data Bus Bit 1
Bit-Bang Data Bus Bit 2
Bit-Bang Data Bus Bit 3
Bit-Bang Data Bus Bit 4
Bit-Bang Data Bus Bit 5
Bit-Bang Data Bus Bit 6
Bit-Bang Data Bus Bit 7
BIT-BANG CONTROL INTERFACE GROUP
Pin#
Channel A
32
31
30
29
Channel B
5
4
3
2
Signal
Type
Description
WR#
RD#
WR#
RD#
OUTPUT
OUTPUT
OUTPUT
OUTPUT
*Note 13
*Note 13
*Note 13
*Note 13
*Note 10: In Input Mode, these pins are pulled to VCCIOx via 200K resistors in the
FT2232C. These can be programmed to gently pull low during USB suspend (PWREN#
= “1”) by setting this option in the EEPROM.
*Note 13: The Bit-Bang Mode (synchronous and asynchronous) WR# and RD# strobes
are on these pins when the main Channel mode is 245 FIFO, CPU FIFO interface, or Fast
Opto-Isolated Serial Mode. Bit-Bang mode is not available on Channel B when Fast
Opto-Isolated Serial Mode is enabled.
*Note 14: The Bit-Bang Mode (synchronous and asynchronous) WR# and RD# strobes
are on these pins when the main Channel mode is set to 323 UART Mode.
Rev 1.4 (Nov 2005)
21
DLP-2232M
DLP Design, Inc.
9.5 Enhanced Asynchronous Bit-Bang Mode
Enhanced Asynchronous Bit-Bang mode is the same as BM-style Bit-Bang mode, except
that the internal RD# and WR# strobes are now brought out of the DLP-2232M to allow
external logic to be clocked by accesses to the bit-bang IO bus.
On either or both channels, any data written to the device in the normal manner will be
self clocked onto the data pins (those which have been configured as outputs). Each pin
can be independently set as an input or an output. The baud rate generator controls the
rate at which the data is clocked out.
For the data to change there has to be new data written, and the baud rate clock has to
tick. If no new data is written to the channel, the pins will hold the last value written.
To allow time for the data to be setup and held around the WR# strobe, the baud rate
should be less than 1 MegaBaud.
Enabling
Asynchronous Bit-Bang mode is enabled by the Set Bit Bang Mode command:
Set_USB_Device_BitMode($00,$01) ; to enable it
Set_USB_Device_BitMode($00,$00) ; to reset it
9.6 Synchronous Bit-Bang Mode
With Synchronous Bit-Bang enabled, data will only be sent out by the FT2232C if there
is space in the device for data to come in. This Synchronous Bit-Bang mode will read the
data bus pins first, before it sends out the byte that has just been transmitted. It is
therefore 1 byte behind the output, and so to read the inputs for the byte that you have
just sent, another byte must be sent.
For example:
(1)
Pins start at 0xFF
Send 0x55,0xAA
Pins go to 0x55 and then to 0xAA
DS2232C Version 1.0 © Future Technology Devices Intl. Ltd. 2004 Page 40 of 52FT2232C Dual
USB UART / FIFO I.C.
Data read = 0xFF,0x55
Rev 1.4 (Nov 2005)
22
DLP-2232M
DLP Design, Inc.
(2)
Pins start at 0xFF
Send 0x55,0xAA,0xAA
(repeat the last byte sent)
Pins go to 0x55 and then to 0xAA
Data read = 0xFF,0x55,0xAA
Figure 25 - Synchronous Bit Bang Mode Signal Timing
t1
t2
t3
t4
t5
t6
Clk Time
D7..0
Current Data
New Data
WR#
RD#
Time Description
t1
t2
t3
t4
t5
t6
Current pin state is read
RD# is set inactive
RD# is set active again, and any pins that are output will change to the new data.
Clock state for data setup
WR# goes active
WR# goes inactive
The internal RD# and WR# strobes are brought off-board to allow external logic to be
clocked by accesses to the bit-bang IO bus.
Enabling
Synchronous Bit-Bang mode is enabled by the Set Bit Bang Mode command:
Set_USB_Device_BitMode($00,$04) ; to enable it
Set_USB_Device_BitMode($00,$00) ; to reset it
Rev 1.4 (Nov 2005)
23
DLP-2232M
DLP Design, Inc.
9.7 Multi-Protocol Synchronous Serial Engine (MPSSE) Mode Signal
Descriptions and Interface Configurations
MPSSE Mode is designed to allow the DLP-2232M to interface efficiently with
synchronous serial protocols such as JTAG and SPI Bus. It can also be used to program
SRAM based FPGA’s over USB. The MPSSE interface is designed to be flexible so that
it can be configured to allow any synchronous serial protocol (industry standard or
proprietary) to be interfaced to the DLP-2232M. MPSSE is available on channel A only.
MPSSE is fully configurable, and is programmed by sending commands down the data
pipe. These can be sent individually, or more efficiently in packets. MPSSE is capable
of a maximum sustained data rate of 5.6 Mega bits / s.
When Channel A is configured in MPSSE mode the IO signal lines are configured as
follows:
Pin#
(Channel A Only)
Signal
40
39
38
37
36
35
34
33
32
31
30
29
28
TCK/SK
TDI/D0
TDO/D1
TMS/CS
GPIOL0
GPIOL1
GPIOL2
GPIOL3
GPIOH0
GPIOH1
GPIOH2
GPIOH3
SI/WU
Type
Description
Enabling
MPSSE mode is enabled using the Set Bit-Bang Mode command.
Set_USB_Device_BitMode($00,$02) ; to enable.
Set_USB_Device_BitMode($00,$00) ; to reset.
MPSSE is fully described in a separate FTDI application note.
Rev 1.4 (Nov 2005)
24
DLP-2232M
DLP Design, Inc.
9.8 MCU Host Bus Emulation Mode Signal Descriptions and Interface
Configuration
MCU host bus emulation mode uses both of the DLP2232M’s A and B channel interfaces
to make the chip emulate a standard 8048 / 8051 MCU host bus. This allows peripheral
devices for these MCU families to be directly connected to USB via the DLP2232M.
The lower 8 bits (AD7 to AD0) is a multiplexed Address / Data bus. A8 to A15 provide
upper (extended) addresses.
There are 4 basic operations:
1) Read (does not change A15 to A8)
2) Read Extended (changes A15 to A8)
3) Write (does not change A15 to A8)
4) Write Extended (changes A15 to A8)
Enabling
MCU Host Bus Emulation Mode enabled using the Set Bit-Bang Mode command.
Set_USB_Device_BitMode($00,$08) ; to enable it
Set_USB_Device_BitMode($00,$00) ; to reset it
Rev 1.4 (Nov 2005)
25
DLP-2232M
DLP Design, Inc.
When MCU Host Bus Emulation mode is enabled the IO signal lines on both channels
work together and the pins are configured as follows:
Pin#
40
39
38
37
36
35
34
33
32
Signal
AD0
AD1
AD2
AD3
AD4
AD5
AD6
AD7
I/O0
Type
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
Description
Address / Data Bus Bit 0
Address / Data Bus Bit 1
Address / Data Bus Bit 2
Address / Data Bus Bit 3
Address / Data Bus Bit 4
Address / Data Bus Bit 5
Address / Data Bus Bit 6
Address / Data Bus Bit 7
MPSSE mode instructions to set / clear or read the high
byte of data can be used with this pin. *Note
31
I/O1
MPSSE mode instructions to set, clear or read the high
byte of data can be used with this pin. Additionally, this
pin has instructions that will make the controller wait until
it is high, or wait until it is low. This can be used to
connect to an IRQ pin of a peripheral chip. The
DLP2232M will wait for the interrupt, and then read the
device, and pass the answer back to the host PC. I/O1 must
be held in input mode if this option is used. *Note
30
IORDY# INPUT
Extends the time taken to perform a Read or Write
operation if pulled low. Pull up to Vcc if not being used.
29
OSC
OUTPUT Shows the clock signal that the circuit is using.
13
A8
OUTPUT Extended Address Bus Bit 8
12
A9
OUTPUT Extended Address Bus Bit 9
11
A10
OUTPUT Extended Address Bus Bit 10
10
A11
OUTPUT Extended Address Bus Bit 11
9
A12
OUTPUT Extended Address Bus Bit 12
8
A13
OUTPUT Extended Address Bus Bit 13
7
A14
OUTPUT Extended Address Bus Bit 14
6
A15
OUTPUT Extended Address Bus Bit 15
5
CS#
OUTPUT Negative pulse to select device during Read or Write.
4
ALE
OUTPUT Positive pulse to latch the address.
3
RD#
OUTPUT Negative Read Output.
2
WR#
OUTPUT Negative Write Output. (Data is setup before WR# goes
low, and is held after WR# goes high)
1
NC
No Connect
*Note: These instructions are fully described in a separate FTDI, MPSSE mode
application note.
Rev 1.4 (Nov 2005)
26
DLP-2232M
DLP Design, Inc.
Figure 29 - MCU Host Bus Emulation Mode Signal Timing - Write Cycle
t1
t2
t3
t4
t5
t6
t7
t8
t9 t10
t11
OSC
A15..A8
High Address
AD7..0
Low Address
Data
ALE
CS#
WR#
IORDY
Time
t1
t2
t3
t4
t5
t6
t7
t8
t9
t10
t11
Description
High address byte is placed on the bus if the extended write is used.
Low address byte is put out.
1 clock period for address is set up.
ALE goes high to enable latch. This will extend to 2 clocks wide if IORDY# is low.
ALE goes low to latch address and CS# is set active low.
Data driven onto the bus.
1 clock period for data setup.
WR# is driven active low. This will extend to 6 clocks wide if IORDY# is low.
WR# is driven inactive high.
CS# is driven inactive, 1/2 a clock period after WR# goes inactive
Data is held until here and may now change
Rev 1.4 (Nov 2005)
27
DLP-2232M
DLP Design, Inc.
Figure 30 - MCU Host Bus Emulation Mode Signal Timing - Read Cycle
t1
t3
t2
t4
t5
t6
t7
t8 t9
OSC
A15..A8
High Address
AD7..0
Low Address
Hi-Z
ALE
CS#
RD#
IORDY
Time
t1
t2
t3
t4
t5
t6
t7
t8
t9
Description
High address byte is placed on the bus if the extended read is used - otherwise
t1 will not occur.
Low address byte is put out.
1 clock period for address set up.
ALE goes high to enable address latch. This will extend to 2 clocks wide if
IORDY# is low.
ALE goes low to latch address, and CS# is set active low. This will extend to 3
clocks if IORDY# is sam-pled low. CS# will always drop 1 clock after ALE has
gone high no matter the state of IORDY#.
Data is set as input (Hi-Z), and RD# is driven active low.
1 clock period for data setup. This will extend to 5 clocks wide if IORDY# is
sampled low.
RD# is driven inactive high.
CS# is driven inactive 1/2 a clock period after RD# goes inactive, and the data
bus is set back to output.
Figure 31 - MCU Host Bus Emulation Mode Signal Timing - Clock (OSC) Signal
thigh
OSC
tlow
tperiod
Time
Description
Typical
Value
Unit
tperiod
thigh
tlow
Clock Period
Clock signal high time
Clock signal low time
??
??
??
ns
ns
ns
Rev 1.4 (Nov 2005)
28
DLP-2232M
DLP Design, Inc.
9.9 Fast Opto-Isolated Serial Interface Mode Signal Description and
Configuration
Fast Opto-Isolated Serial Interface Mode provides a method of communicating with an
external device over USB using 4 wires that can have opto-isolators in their path, thus
providing galvanic isolation between systems. If either channel A or channel B are
enabled in fast opto-isolated serial mode then the pins on channel B are switched to the
fast serial interface configuration. The I/O interface for fast serial mode is always on
channel B, even if both channels are being used in this mode. An address bit is used to
determine the source or destination channel of the data. It therefore makes sense to
always use at least channel B or both for fast serial mode, but not A own its own.
When either Channel B or Both Channel A and B are configured in Fast Opto-Isolated
Serial Interface mode following IO signal lines are configured as follows:
Pin#
13
12
Signal
FSDI
FSCLK
11
FSDO
10
FSCTS
Type
INPUT
INPUT
Description
Fast serial data input
Clock input into the chip to clock data in or out. The
external device has to provide a clock signal or nothing
will change on the interface pins. This gives the
external device full control over the interface. It is
designed to be half duplex so that data is only
transferred in one direction at a time.
OUTPUT Fast serial data output. Driven low to indicate that the
chip is ready to send data.
OUTPUT Clear To Send control signal output
Fast Opto-Isolated serial interface mode is enabled in the external EEPROM.
Rev 1.4 (Nov 2005)
29
DLP-2232M
DLP Design, Inc.
Figure 33 - Fast Opto-Isolated Serial Signal Timing Diagram
FSCLK
t1
t6
t5
t2
FSDO / FSCTS
t7
FSDI
t3
Time
t1
t2
t3
t4
t5
t6
t7
t4
Description
FSDO / FSCTS hold time
FSDO / FSCTS setup time
FSDI hold time
FSDI setup time
FSCLK low
FSCLK high
FSCLK Period
Min
Max
5
10
10
10
20
Unit
ns
ns
ns
ns
ns
ns
ns
Outgoing Fast Serial Data
To send fast serial data out of the chip, the external device must clock. If the chip has
data ready to send, it will drive FSDO low to indicate the start bit. It will not do this if it
is currently receiving data from the external device.
Figure 34 - Fast Opto-Isolated Serial Data Format - Data output from the FT2232C
FSCLK
FSDO
0
Start
Bit
D0
D1
D2
D3
D4
D5
Data Bits - LSB first
D6
D7
SRCE
Source
Bit
Notes:
(i) Start Bit is always 0.
(ii) Data is sent LSB first.
(iii) The source bit (SRCE) indicates which channel the data has come from. A ‘0’ means
that it has come from Channel A, a ‘1’ means that it has come from Channel B.
(iv) If the target device is unable to accept the data when it detects the start bit, it should
stop the FSCLK until it can accept the data.
Rev 1.4 (Nov 2005)
30
DLP-2232M
DLP Design, Inc.
Incoming Fast Serial Data
The external device is allowed to send data into the chip if FSCTS is high. On receipt of
a Zero start bit on FSDI, the module will drop FSCTS on the next positive clock edge.
The data from bits 0 to 7 is then clocked in (LSB first). The next bit determines where
the data will be written. It can go to either channel A or to channel B. A ‘0’ will send it
to channel A, providing channel A is enabled for fast serial mode, otherwise it will go to
channel B. A ‘1’ will send it to channel B, providing channel B is enabled for fast serial
mode, otherwise it will go to channel A. Either channel A, or channel B, or both must be
enabled as fast serial mode or the circuit is disabled.
Figure 35 - Fast Opto-Isolated Serial Data Format - Data input to the DLP-2232M
FSCTS
FSCLK
FSDI
0
Start
Bit
D0
D1
D2
D3
D4
D5
Data Bits - LSB first
D6
D7
DEST
Destination
Bit
Notes:
(i) Start Bit is always 0.
(ii) Data is sent LSB first.
(iii) The destination bit (DEST) indicates which channel the data should go to. A ‘0’
means that it should go to channel A, a ‘1’ means that it should go to channel B.
(iv) The target device should check CTS is high before it sends data. CTS goes low after
data bit 0 (D0) and stays low until the chip can accept more data.
Contention
There is a possibility that contention may occur, where the interface goes from being
completely idle to both sending and receiving at the same clock instance. In this case the
chip backs off, and allow the data from the external device to be received.
Data Format
The data format for either direction is:
1) Zero Start Bit
2) Data bit 0
3) Data bit 1
4) Data bit 2
5) Data bit 3
6) Data bit 4
7) Data bit 5
8) Data bit 6
9) Data bit 7
10) Source/Destination (‘0’ indicates channel A; ‘1’ indicates channel B)
Rev 1.4 (Nov 2005)
31
DLP-2232M
DLP Design, Inc.
Enabling
Fast serial mode is enabled via EEPROM option bits. The device can be reset by setting
an enable value of $10 to the Set Bit Bang Mode command. While this bit is set, the
device is held reset.
Set_USB_Device_BitMode($00,$10) ; to reset it
Set_USB_Device_BitMode($00,$00) ; to enable it
Figure 36 - Fast Opto-Isolated Serial Interface Example
10.0 Disclaimer
© DLP Design, Inc., 2002 / 2004
Neither the whole nor any part of the information contained in, or the product described
in this manual, may be adapted or reproduced in any material or electronic form without
the prior written consent of the copyright holder.
This product and its documentation are supplied on an as-is basis and no warranty as to
their suitability for any particular purpose is either made or implied. DLP Design, Inc.
will not accept any claim for damages howsoever arising as a result of use or failure of
this product. Your statutory rights are not affected. This product or any variant of it is not
intended for use in any medical appliance, device or system in which the failure of the
product might reasonably be expected to result in personal injury.
This document provides information that may be subject to change without notice.
11.0 Contact Information
DLP Design, Inc.
1605 Roma Lane
Allen, TX 75013
Phone: 469-964-8027
Fax: 415-901-4859
E-Mail ( Sales ) : sales@dlpdesign.com
E-Mail ( Support ) : support@dlpdesign.com
Web Site URL : http://www.dlpdesign.com
Rev 1.4 (Nov 2005)
32
DLP-2232M
DLP Design, Inc.
C18
.1uF
EXTVCC
PORTVCC
FB1
Ferrite Bead
2
R2
27
C2
.1uF
C7
47pF
VCCUSB
C3
10uF
C5
.033uF
6
8
5
7
1.5K
Y1
6MHz
47
2
1
48
4
44
43
47pF
47pF
RSTOUT#
C16
C17
1
2
3
4
2.2K
2
FB2
Ferrite Bead
R1
470
C4
.1uF
TEST
EEDATA
EESK
EECS
RESET#
XTOUT
XTIN
RSTOUT#
USBDP
USBDM
3V3OUT
1
1
C1
.01uF
R4
U1
93C56
CS
SK
DIN
DOUT
R6
C12
C11
.01uF
.033uF
.1uF
AD0
AD1
AD2
AD3
AD4
AD5
AD6
AD7
AC0
AC1
AC2
AC3
PWREN
SI/WUB
BC0
BC1
BC2
BC3
BD0
BD1
BD2
BD3
BD4
BD5
BD6
BD7
SI/WUA
C13
14
31
CN1
CN-USB
R3
27
R8
47K
VCC
NC
NC
GND
10K
VCCIOA
VCCIOB
1
2
3
4
C6
47pF
VCCUSB
RSTIN#
8
7
6
5
VCCUSB
R5
3
42
GND
GND
GND
GND
VCC
VCC
9
18
25
34
46
AGND
AVCC
45
5
R7
2.2K
24
23
22
21
20
19
17
16
15
13
12
11
10
40
39
38
37
36
35
33
32
30
29
28
27
26
41
C8
.1uF
C9
.1uF
C10
10uF
VCCSW
DLP-2232M MODULE
SI/WUB
C14
.1uF
AD0
AD1
AD2
AD3
AD4
AD5
AD6
AD7
SI/WUB
AC0
BC3
AC1
BC2
AC2
BC1
AC3
BC0
BD7
SI/WUA
BD6
BD5
BD0
BD4
BD1
BD3
BD2
BD2
BD3
BD1
BD4
BD0
BD5
GND
BD6
GND
BD7
VCCSW
VCCIOB
VCCIOA
EXTVCC
PORTVCC
BC0
BC1
BC2
BC3
C15
.1uF
GND
VCCIOA
VCCIOB
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
24
23
22
21
JP5
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
24
23
22
21
CONN PCB 20x2
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
AD0
AD1
AD2
AD3
AD4
AD5
AD6
AD7
AC0
AC1
AC2
AC3
SI/WUA
RSTIN#
RSTOUT#
GND
GND
GND
GND
VCCUSB
>> PRELIMINARY <<
Q1
IRLML6402
U2
FT2232C
Was this manual useful for you? yes no
Thank you for your participation!

* Your assessment is very important for improving the work of artificial intelligence, which forms the content of this project

Download PDF

advertising