Wang 2200 Service Manual

Wang 2200 Service Manual
'I~BLE
OF CONTENTS
SECTION 1
l~
DESCRIPTION
1.1 GENERAL
1.2 MODEL INFORMATION
l~}
SPECIFICATIONS
1.3.1 2200 System; General Specifications
1.3.2 2200 CPU; Models A, B, C, S, T
1.3.3 Memory Sizes
1.3.4 Peripheral Capabilities
1.3.5 Dynamic Range
1.3.6 Subroutine Stacking'
1.3.7 Physical Parameters
1.4 PERIPHERAL CABLE LENGTHS
1-1
1-1
1-18
1-19
1-19
1-19
1-22
1-22
1-22
1-22
1-23
1-26
SECTION 2
2.
INSTALLATION
' •
2.1 INSTALLATION GUIDE FOR WANG SYSTEMS
.•'
2.1.1 Selecting A Location
2.1.2 Controlling The Environment
2.1.3 Electrical Environment
2.2 DEVICE ADDRESS ASSIGNMENTS
2.2.1 2200 Peripheral Default Addresses
2.2.2 Address Setting On 2200 r/o Controller Cards
2.3 RAM SIZE SELECTIONS
2,4 INCOMING INSPECTION
2.5 INSTALLATION PROCEDURE
2-1
2-1
2-1
2-1
2-3
2-4
2-6
2-7
2-11
2-12
2-13
SECTION 3
3.
OPERATION
3.1 GENERAL
3.2 PROGRAMMING OF OIlTl'UT DEVICES
3.2.1 The Select Statement
3.2.2 Device Type Codes
3.2.3 Print
3.2.4 List
3.2.5 Console Output
3.2.6 Line Length
3.2.7 Special Techniques
3.2.8 Summary Of Console And Non-console Device Output
From CPU
3-1
3-1
3-1
3-1
3-1
3-5
3-5
3-6
3-6
3-8
3-12
SECTION 4
4.
THEORY OF OPERATION
4.1 CPU GENERAL DESCRIPTION
4.1.1 Introduction
4.1.2 Hardware Versus Software
4.1.3 General Hardware Description
4.1.3.1 Register Structure
4.1.3.2 Memory Structure
4.1.3.3 Supporting Hardware
4.1.3.4 Input/Output Structure
ix
4-1
4-1
4-1
4-1
4-4
4-4
4-8
4-11
4-15
4.2 GENERAL INSTRUCTION SET DESCRIPTION
4. 3 CPU FIRMWARE DESCRIPTION
4.3.1 CPU Processing
4.3.1.1 Text Entry Phase
4.3.1.2 Variable and Line Number Resolution Phase
4.3.1.3 Text Atomizing
4.3.1.4 Execution Phase
4.3.1.5 Recursion
4.3.1.6 Expression Evaluation
4.3.1. 7 Looping (FOll/NEXT)
4.3.1.8 Subroutines (GOSUB/RETURN)
4.3.1.9 Device Selection
4.3.1.10 Output Device Switching
4.4 DETAILED THEORY OF CPU OPERATION (CENTRAL PROCESSOR AND
POWER &JPPLY
4.4.1 CPU Hardware
4.4.2 CPU Power Supply
4.4.3 2200 Mnemonics
~
4-16
4-22
4-23
4-23
4-23
4-25
4-27
4-21
4-28
4-31
4-32
4-32
4-34
4-35
4-35
4-88
4-90
SECTION 5
5._ USER TERMINAL AND POWER SUPPLY HARDWARE OPERATION
5.1 VIDEO DISPLAY
5.1.1 Video Display Principles
5.1. 2 Theory Of Operation
5.1.2.1 Video Amplifier
5.1.2.2 Sync Separator
5.1.2.3 Vertical Oscillator
5.1.2.4 Vertical Driver and Output
5.1.2.5 Horizontal APC Circuit
5.1.2.6 Horizontal Oscillator
5.1.2.1 Horizontal Pulse Shaper
5.1.2.8 Horizontal Driver
5.1.2.9 Horizontal Output
5.1.2.10 Retrace Blanking
5.1.2.11 Power Supply (13V Version)
5.1.2.12 Power Supply (12V Version)
5.2 THE TAPE DRIVE WIT
5.2.1 Theory Of Operation
3.2.1.1 Input Decoder
5.2.1.2 Signal Conditioner
5.2.1. 3 Take-up Motor Control
"""
5.2.1.4 Direction Control
5.2.1.5 Output Buffer
5.2.2 Detailed Theory Of Operation
5.2.2.1 Input Decoder (L558)
5.2.2.2 Tape Forward Operation (LOAD, SAVE, SKIP)
5.2.2.3 Tape Reverse Operation (BACKSPACE)
5.2.2.4 Rewind
5.2.2.5 Power Driver (L559)
5.2.2.6 Speed Control (L559)
5.2.2.1 Signal Conditioner (6115) and Output
Buffer (1558)
5-1
5-1
5-1
5-3
5-4
s-6
5-7
5-8
5-10
5-12
5-12
5-13
5-13
5-11
5-18
5-19
5-19
5-20
5-20
5-20
5-20
5-20
5-20
5-20
5-21
5-21
5-21
5-22
5-22
5-22
5-23
~
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SECTION 6
6. CPU INPUT/OUTPUT CONTROLLER CIRCUIT BOARDS HARDWARE OPERATION
"-
6.1 INPlIT/OrnUT DEVICE SELECTION
6.1.1 Introduction
6.1.2 Address Coeparator
6.1.3 Select Latch
6.1.4 Ready/Busy Decoder
6.2 VIDEO DISPLAY CONTROLLER
6.2.1 General Theory of Operation
6.2.1.1 Timing
6.2.1.2 Device Selection and Data Input
6.2.1.3 Clock Decoder
6.2.1.4 Horizontal Counter
6.2.1.5 Vertical Counter
6.2.1.6 Cursor Character and Row Counters
6.2.1.7 Cursor Character and Row Compare
6.~.1.8 Memory Address Selection
6.2.1.9 Character Generator Row Select Counter
6.2.1.10 Character Generator and Conversion
6.2.1.11 Output Gates
6.2.1.12 Roll Counter and Compare
6.2.1.13 Control Function Decoder
6.2.1.14 Control Functions
6.2.1.15 Read Cycle
6.2.1.16 Write Cycle
6.2.2 Detailed Theory Of Operation
6.2.2.1 Device Selection
6.2.2.2 ''D'' Clock and Clock Decode Logic
6.2.2.3 Vertical Counter
6.2.2.4 Horizontal Counter
6.2.2.5 Control Functions
6.2.2.6 Roll
6.2.2.7 Character Generstion
6.2.2.8 Cursor Generation
6.2.2.9 Writing a Character Into Memory
6.2.2.10 Lower To Upper Case Conversion
6.2.3 Differences In Video Display Controllers
6. 3 KEYBOARD CONTROLLER
6.3.1 General Theory Of Operation
6.3.1.1 Device Selection
6.3.1. 2 Scan Clock
6.3.1.3 Y Multiplexer
6.3.1.4 ROM and Output Latch
6.3.1.5 Function Decoder
6.3.2 Detailed Theory Of Operation
6.3.2.1 Device Selection
6.3.2.2 Keyboard Input Cycle
6.3.2.3 Function Key Detector
6.4 TAPE DRIVE CONTROLLER
6.4.1 General Theory Of Operation
6.4.1.1 Device Selection
6.4.1.2 Control Decoder
6.4.1.3 Output Buffer
xi
6-1
6-1
6-1
6-1
6-2
6-2
6-2
6-2
6-2
6-2
6-2
6-3
6-3
6-3
6-3
6-3
6-5
6-5
6-5
6-6
6-7
6-7
6-1
6-8
6-8
6-8
6-8
6-9
6-9
6-10
6-11
6-12
6-13
6-13
6-14
6-14
6-18
6-18
6-1.
6-18
6-19
6-19
6-19
6-19
6-19
6-19
6-22
6-22
6-23
6-23
6-23
6-23
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6.4.2 Detailed Theory Of Operation
6.4.2.1 Control Decoder
6.4.2.2 Output Suffer
0.5 1>1 SK OONTROI.I.ER
6.5.1 Gener,l1 TIleory or OperaL Ion
6.5.1.1 Device Selection
6.5.1.2 Input Buffer
6.5.1.3 Output Buffer
6.5.2 Detailed Theory Of Operation
6.5.2.1 Device Selection
6.5.2.2 Prime Circuit
6.5.2.3 Input Buffer
6.5.2.4 Output Buffer
6.6 DISK IllLTIPLEXER OONTROLLER (2230 IlXA/B)
6.6.1 Theory Of Operation
6.6.1.1 Device Selection
6.6.1.2 Scan Clock
6.6.1.3 Channel Scanner
6.6.1.4 cPU I/O Buffer
6.6.1.5 Hog Latch
6.6.2 Detailed Theory Of Operation
6.6.2.1 Scan Clock
6.6.2.2 Channel Scannlll
6.6.2.3 CPU 1/0 Buffer
6.6.2.4 Prime Circuit
6.&.2.5 Hog Latch
6.6.2.6 Drive #3 Latch
h
,
11<
.J.
6-23
6-24
6-24
6-24
6-24
6-24
&-25
6-25
6-25
&-25
6-26
6-26
6-26
6-2&
6-26
6-27
6-27
6-27
6-21
6-28
6-28
6-28
6-28
6-29
6-30
6-30
6-30
4
t'"'\
SECTION 7
7.
SYSTEM DIAGNOSTICS
7.1 MODEL 2200 A, B AND C CPU BASIC DIAGNOSTIC TESTS
7.1.1 Test 1 and 2
7.1.2 Model 2200B Basic D1agnostic Test
7.1.3 Model 2200C Basic Diagnostic Test
7.1.4 Model 2200S Basic Diagnostic Test
7.1.5 Model 2200T D18gnos tic Test
7.2 2200 MEMORY AND Ml\TR DIAGNOSTIC TESTS (HEM-I, MEM-2, and
MATR-3)
7.3 2200 B AND CMEMORY DIAGNOSTIC
7.4 OPTION DIAGNOSTICS
7.4.1 Matrix (Option 1 or Option 21) Diagnostic
7.4.2 General I/O (Option 2 or 23)
7.4.3 Edit (Option 3) Diagnostic
7.4.4 Audio Alarm (Options 4 and 31) Diagnostic
7.4.5 Sort (Option 5) Diagnostic
7.4:6 Advanced Programmable (Option 22) Diagnostic
7.4.7 Disk ROM (Option 24) Diagnostic
7.4.8 Keyboard Clicker (Option 32) Test
7.S PERIPHERAL WlICE DIAGNOSTICS
7.5.1 2200 Input System Diagnostic
7.5.2 Output System Diagnostic
7.5.3 Model 2207A/2227 ~iagnostics
7.5.4 Model 2221W D1agnostics
7.5.5 Model 2224 and 2230 MXA/MXB Diagnostics
xii
7-1
7-1
7-1
7-2
7-3
7-4
7-5
7-5
1-6
7-6
7-6
7-7
7-8
7-9
7-9
7-10
7-10
7-10
7-10
7-10
7-25
7-25
7-31
7-32
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7.5.6 2230/2260 Diagnostics
7.5.7 Model 2230 MXA and MXB Diagnostics
7.5.8 Model 2234/2244 Diagnostics
7.5.8.1 Electromechanical Tests
7.5.8.2 Data Tests
7.5.9 Model 2234A Or ~244A Diagnostics
7.5.9.1 See Paragraph 7.5.8.1
7.5.9.2 Data/Program Tests
7.5.10 Model 2240/2242/2243 Diagnostics
7.5.11 Model 2241 Diagnostic
7.5.12 Model 2250 Diagnostic
7.5.13 Model 2252 Diagnostic
:-,
7.5.14 Model 2261 Diagnostic
7.5.15 Model 2262 Diagnostic
7.5.16 Model 2209 Diagnostic
7.5.17 WCS 20/30 Diagnostic Programs
A
7-32
7-37
7-37
7-37
7-38
7-39
7-39
7-39
7-47
7-49
7-50
7-53
7-55
7-56
7-58
7-61
SECTION 8
8. MAINTENANCE INFORMATION FOR USER TERMINALS, POWER SUPPLIES AND
CPU'S
8.1 PREVENTIVE MAINTENANCE
8.1.1 Cleaning
8.1.1.1 Central Processing Unit
8.1.1.2 Video Display/Tape Drive Unit
8.1.1.3 Power Supply (2200 A, a, C SystelllS)
8.1.2 Lubrication
8.2 TROUBLESHOOTING
8.2.1 Video Display
8.2.2 The Tape Drive Unit
8.2.3 The Central Processing Unit
8.3 ADJUSTMENTS
8.3.1 Recommended Test Equipment/Tool List
8.3.2 CPU - Voltage Adjust Procedure
8.3.3 Video Display Unit
8.3.4 Tape Drive Unit
8.4 CHASSIS LAYOUT(S) AND SUPPLEMENTARY DATA
8.4.1 2200 CPU; Models A, B, C; 6 I/O Slots
8.4.2 2200 CPU; Models A, B, C; 11 I/O Slots
8.4.3 6222 Version; 2219 Chassis
8.4.4 2200 Models S, T
8.4.5 2200 SIT - 9 Slot (OP 20A)
8.4.6 2200 PS - Power Supply For CPU Models A, B, and C
8.4.7 2215 Basic Keyboard
8.4.8 2222 Alphanumeric Keyboard
8.4.9 2223 Upper/Lower Case Alphanumeric Keyword Keyboard
8.4.10 2216/2217 Video Display And Cassette Drive Console
8.4.11 2220 Integrated Video Display/Cassette Drive/Keyword
Keyboard Console
8.4.12 Integrated Video Display/Keyword Keyboard Console
8.4.13 2217 (TD-24) Cassette Drive
8.5 (X)MPONENT REPLACEMENTS
8.5.1 CPU
8.5.2 Video Display Unit
8.5.3 Tape Drive Unit
xiii
8-1
8-1
8-1
8-1
8-2
8-2
8-3
8-3
8-3
8-8
8-12
8-21
8-21
8-22
8-25
8-29
8-34
8-34
8-36
8-38
8-40
8-42
8-44
8-46
8-46
8-47
8-48
8-54
8-59
8-61
8-63
8-63
8-64
8-67
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SECTION 9
9. 2200 SYSTEM OPTION CONVERSIONS AND RETROfITS
9.1
9.2
9.3
9.4
9.5
9.6
9.7
~ ~.8
2200 A/B/C ROM AND SUPERPATCH OPTIONS
9.1.1 Super Patch Boards
9.1.2 Marking Of ROM and Superpatch PC Boards
MODELS 22005 AND 2200T ROM BOARDS
ROM AND SUPERPATCH CHART - 2200 A/B/C/S/T CPU'S
OPTION CONVERSIONS
9.4.1 Option 1 (Matrix Option) Conversion Procedure
9.4.2 Option 2 (General I/O) Conversion Procedure
9.4.3 Option 3 (Edit Option) Conversion Procedure
9.4.4 Option 4 and Option 31 (Audio Alarm) Conversion
Procedure
9.4.5 Option 5 (Sort ROM) Conversion Procedure
9.4.6 Option 20 (Three Extra I/O Slota For 2200S CPU)
Conversion Procedure
9.4.7 Option 20A (9 Slot I/O) Conversion Procedure
9.4.8 Option 21 ~atrix ROM) Conversion Procedure
9.4.9 Option 22 Advanced Programming And Matrix ROMs
9.4.10 Option 23 General I/O, Advanced Programming And
Matrix ROMs
9.4.11 Option 24 - Disk ROM
9.4.12 Option 30 (Upper/Lower Case Display) Conversion
Procedure
9.4.13 Option 32 (Keyboard Clicker) Conversion Procedure
2200 SYSTEM MEMORY OPTIONS
2200 SYSTEM RETROFITS
PERIPHERAL RETROFIT INSTRUCTIONS
9.7.1 600/700 Peripheral Conversions to 2200 Peripherals
9.7.2 601/701 to 2201
9.7.3 60Z/702 to 2202
9.7.4 612/712 to 2212
9.7.5 621/721 to 2221
9.7.6 630/730 to 2230
9.7. 7 63~/732 to 2232
9.7.8 640/740 to 2240
9.7.9 2234 to 2234A and 2244 to 2244A/Converaion
MISCELLANEOUS 2200 SYSTEM RETROFITS
9.8.1 Model 2201 ON/OFF Switch-Conversion Procedure
9.8.2 Conversion From 2201 to 2212 and 2232
9.8.3 Conversion Of 2215 and 2222 With 6367 PC Board
9-1
9-2
9-2
9-2
9-3
9-4
9-9
9-9
9-11
9-12
9-16
9-17
9-19
9-20
9-20
9-21
9-22
9-23
9-24
9-24
9-37
9-38
9-39
9-39
9-39
9-39
9-39
9-39
9-40
9-40
9-40
9-40
9-42
9-42
9-43
9-43
SECTION 10
10.
MECHANICAL ASSEMBLY DRAWINGS
10-1
SECTION 11
11. APPENDICES
APPENDIX
APPENDIX
APPENDIX
APPENDIX
11-1
A - ASCII roDE CHARACTER SET
11-1
B - LISTING OF ERROR MESSAGES
C - 2200 PERIPHERAL ADDRESS SETrINGS BY MODEL NUMBER
D - PRINTED CIRCUIT BOARD REVISION LISTING AND
ADDITIONAL REFERENCE NOTES
11-3
11-31
11-35
xiv
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SECTION 1
~
DESCRIPTION
1.1
GENERAL
The Wang Model 2200 Advanced Programmable Calculator combines simple
keyboard operation with the versatility of BASIC language programming, a
compiler language used by many larger scale computer systems.
The
Model 2200 is essentially a single-user, noninterrupt, microprogrammed
system.
The Wang BASIC compiler is interpretive, operating directly
on user text and saving in RAM where required.
A fundamental 2200 system incorporates the following:
a)
Central Processor Unit
tFIGURE 1-11
b)
IFIGURE 1-21
System Power Supply
)
IFIGURE 1-31
1-1
c)
User Terminals
FIGURE 1-4;
2216/2217/2223
FIGURE 1-6; 2226
FIGURE 1-5; 2220
The CPU a) is comprised of ROM (with or without software options),
Arithmetic/Logic circuitry, system control logic, I/O interface (expanded
in 2219 chassis), and approximately 3.4K bytes (expandable) of useravailable RAM (4K actual RAM space for smallest memory option).
The CPU
constitutes the 'heart' of a 2200 system.
The system power supply is either packaged within the CPU chassis
(2200 S,T)*, or is packaged separately (2200 PS for A, B, and C CPU
chassis; see figure 2).
The user terminal is comprised of a user input keyboard (2215, 2222,
2223), a 16 line/1024-character video display which is available in a
12 inch (diagonal measure) screen (2216/2226) or a 9 inch screen (2220
console), and a Model TD-24 digital tape cassette drive (2217) for
storage and retrieval of user programs and data.
1-2
The physical
packaging of the user terminal takes one of three console configurations.
The first console combines a video display and a TD-24 cassette drive
)
(2216/17 console) shown in figure 4; the keyboard is packaged separately
(2215, 2222, 2223; figure 4).
The second console combines the smaller
9 inch, (diagonal) video display, a TO-24 cassette drive, and an upper/
lower case Keyword Keyboard identical to the 2223 keyboard (2220 console;
figure 5).
The third console combines a 12 inch (diagonal) video
display and an upper/lower case Keyword Keyboard identical to the 2223
Keyboard; console storage/retrieval of bulk user data and programs is
accomplished via disk or via separate 2217 or 2218.
(2226 console;
Figure 6).
)
2200 A/B/C CPU - 6 I/O
FIGURE 1-7
2200 SIT CPU - 3/6 I/O
FIGURE 1-8
FIGURE 1-9
2219 A/B/C CPU - 11 I/O
FIGURE 1-10
2200 SIT CPU - 9 I/O
)
1-3
/\ number of special-purpose options are available:
.UCJO 01"1 JON ~
OJ'J ION IJfo:<;<.IU!,O!WN
ACCOMMODATING CPU - USAGE
nOOA
OP-I
2200B
nooc
22005
2200T
Matrix ROM Mutually
exclusive with OP-5
OP-2
General I/O ROM
OP-)
fo:dit ROM
OP-4
Audio Alarm
X
X
fOT
X
Standard
X
Standard
Standard
X
2216 DiRplay
OP-5
Coumercial Matrix/
X
Sort ROM(Hutually
exclusive with OP-I)
OP-20
) Extra I/O Slota
X
X
OP-20
9 I/O Slot Clmssis
X
X
OP-21
Mat rix ROM.
OP-22
Advanced ProgtallUllllble
Standard
X
Standard
X
Standard
X
Stand.. _-'I
ROM plus OP-21
OP-23
General I/O ROM
plus OP-22
OP-24
Disk Capability
plus OP-23
OP-30
Upper/Lower
X
X
X
Display (for 2220.
2216A, or 2226)
OP-li
Audio Alarm for
X
X
X
X
X
2220 and 2226
consoles
OP-)2
Keyboard Clicker
X
X
X .. Option available
- .. Option not available'
1-4
X
Option Descriptions
Options 1 or 21 (OP-l, OP-21) provide matrix statements designed
to reduce execution time and use less RAM than would be required using
standard 2200 statements to program matrix operations.
Options 2 or 23 (oP-2, OP-23) allows the user to custom-tailor
input/output operations to suit special peripheral devices.
This option
also facilitates high-speed character code translation and data packing/
unpacking.
Option 3 (OP-3) allows individual alphanumeric characters in a
line of program text, data values, or program text currently being
entered from a Keyboard, to be altered, deleted, or inserted without
inputting the entire program line again.
Options 4 or 31 (OP-4, OP31) cause an audible signal to alert
the system user when (for example) an error occurs under program control.
The alarm may be sounded by programming a predesignated HEX code wherever
desired.
)
Option 5 (OP-5) provides six matrix statements for flexible and
rapid searching, moving, and ordering data in System 2200B or C CPU's.
Option 5 is mutually exclusive with Option 1.
Options 20 and 20A (OP-20, OP-20A) provide 6-slot and 9-slot r/o
capabilities (respectively) with any 2200S or 2200T CPU.
Option 22 (OP-22) provides eleven bit and byte manipulation
statements and functions which greatly increase processing capability
by reducing programming requirements for such applications.
Option 22
includes Option 21.
Option 24 (OP-24) provides all disk I/O capabilities, and includes
Options 22 and 21.
Option 32 (OP-32) causes an audible "click" whenever a key is
)
depressed; thus an experienced programmer or typist (for example) need
1-5
not "bottom out" a key to ensure entry, thereby increasing input speed.
'The "click" sound also lessees the need to verify entry by checking
the video display.
A full compliment of peripheral devices interface with the 2200 CPU:
ACCOMMODATING CPU
PERIPHERAL!DESCRIPTION
2201
2202
2200A
2200B
2200C
22005
2200T
Output Writer
X
X
X
X
X
Plotting Output
-
X
X
OP-22
X
Min.
Writer
Req'd
2203
Punched Tape Reader
-
X
OP-22
X
X
Min.
Req'd
2207
RS-232-C Input!
limited
Output Interface
use
X
X
X
X
X
X
X
X
with Fixed BAUD
Rate
2207A
RS-232-C Input!
limited
Output Interface
use
with Selectable
BAUD rate
2209
Nine Track Mag.
Lire
2212
-
nr1v~
Analog Flatbed
-
OP-2
OP-2
"nd 12K
dnd
OP-2J
I ?K
'Jiltl
ilK
12K
j(AM
HAM
HAM
HAM
Mill.
MJII.
MI".
Mill.
Hp,,' ,1
Req'd
Req"d
Req'd
X
X
Plotter
OP-23
X
Min.
Req'd
2214
Mark Sense Card
limited
Reader
use
X
X
OP-22
Min.
Req'd
1-6
X
ACCOMMODATING CPU
PERIPHERAL/DESCR IPT ION
2200A
2215
2216
2200B
2200C
2200S
2200T
X
X
X
BASIC KeY"'ord
Requires
Requires
Keyboard
OP-3 for
OP-3 for
Keyboa'td
Keyboard
Edit
Edit
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
Executive Video
Display
2216A
Upper fLower Case
Executive Video
Display
2216/17
Combined 2216/2217
Console
22l6A/17 Combined 2216A/22l7
Console
)
2217
Single Cassette
Drive
2218
Dual Cassette
Drive
2220
2221
Integrated Console
Line Printer;
Requires
Requires
Requires
Requires
Requires
OP-3
OP-3
OP-30
OP-30
OP-30
for
for
for U/L
for U/L
for U/L
Keyboard
Keyboard
case
case
case
Edit and
Edit and
OP-30
OP-30
for U/L
for U/L
case
case
X
X
X
X
X
(132 Column)
)
1-7
ACCOMMODATING CPU
PERIPHERAL/DESCRIPTION
222111
Line Printer
2200A
2200B
2200C
2200S
2200T
X
X
X
X
X
X
X
X
X
X
X
X
OP-24
X
(132 column)
2222
2223
Alphanumeric
Requires
Requires
Typewriter
OP-3 for
OP-3 for
Keyboard
Keyboard
Keyboard
Edit
Edit
Alphanumeric/
Requires
Requires
BASIC Keyword
OP-3 for
OP-3 for
Keyboard
2224-2,
Disk Multiplexer
Keyboard
Keyboard
Edit
Edit
-
X
3,4
2226
Required
Comb inat ion Video
-
-
-
X
X
X
Display/U/L Case
Keyword Keyboard
for IICS.
Telecommunications
Limited
OP-2
OP-2
OP-23
Controller
Use
Recomm.
Recomm..
Recomm.
2227N
Null Modem
X
X
X
X
X
2230-1,
Fixed/Removable
-
X
X
OP-24
X
2,3
Disk Drive
2227
2230MXA, Daisy Chain
MXB
Disk Multiplexers
2231
Line Printer
Required
-
X
X
OP-24
X
Required
X
1-8
X
X
X
X
PERIPHERAL/DESCRIPTION
2232A
ACCOMMODATING CPU
Digital Flatbed
2200A
2200B
2200C
-
X
X
Plotter
22005
2200T
OP-22
X
Min.
Req'd
2234/34A Hopper Feed Punched
Limited
X
X
Use
Card Reader
OP-22
X
fun.
Req'd
2240-2
Dual Removable
-
X
X
Flexible Disk Drive
2241
Thermal Printer
OP-24
X
Required
X
X
X
X
X
-
X
X
OP-24
X
(80 ColUIJll1)
2242
Single Rc.novab Ie
Flexible DISk Drive
)
2243
Triple R( movable
Required
-
X
X
Flexible DISk f)r1ve
2244/44A Hopper Feed, Mark-
Sense/Punch Card
2252
X
Required
Limited
X
X
Use
OP-22
X
Min.
Reader
2250A
OP-24
Req'd
B Bit Parallel
Limited
OP-2
OP-2
OP-23
I/O Interface
Use
Recomm.
ReCODDD.
Recomm.
Scanning Input
X
X
X
X
X
X
X
X
X
X
X
Interface (BCD 10
digit parallel)
2252A
Scanning Input
Interface (Selec-
table
~ 10
digit
parallel input)
)
1-9
PERIPH[R,\L!DESCRIPTION
2260
F1xed!Removable
ACCOMMODATING CPU
2200A
2200B
2200C
2200S
2200T
-
X
X
OP-24
X
10 Meg Disk Drive
2261
High Speed 132
Required
X
X
X
X
X
L.l.m!ted
X
X
OP-22
X
Column Printer
2262-1,
Dl.g1.t.l.zer
2,3
2270
Use
Remov"lble Dl.,,>kette
-
Recomm.
X
X
Disk Dn.ve
2290
CPU/Perl.pheral
OP-24
X
Required
X
X
X
X
X
-
X
X
X
X
X
X
X
X
X
-
-
-
X
X
Stand
2291
D.gi"l Fl.:ltoed
Plotter Stand
2292
Auxill.ary Video
Display
2293
WCS Equipment
Stand
1-10
SYSTEM 2200 PERIPHERALS
)
2221/2261
2207
2218
~
FIGURE 1-11
Not shown
)
in-;·:~NOD-T~E~.----------Flgure 11· are the fo 11 owi ng
2207A
2209
2220
2221W
2222
2223
2226
2250
2252A
2260
2262
2270
2291
2292
2293
1-11
PERIPHERAL DESCRIPTIONS
The Model 2201 Output writer types numeric and upper and lower
case alphabetic output from the System 2200 with full format control.
In the Model 2202 Plotting Output writer, complete digital plotting
is combined with the alphanumeric capability of the Model 2201.
plots are easily titled and labeled.
Thus,
(Both the Model 2201 and the Model
2202 can be used as standard electric typewriters when not being used
with the System 2200.)
With the Model 2203 punched Tape Reader, paper tape data in
any code format is automatically read to the system, providing an
efficient "data reduction" system.
The reader supports,S, 6, 7 or
8 track paper tape.
The Model 2207 RS-232-C I/O Interface Controller is an earlier
version of the 2207A, and operates at a fixed baud rate.
The Model 2207A RS-232-C I/O Interface Controller allows attachment
R
of a Model 33 Teletype as a terminal for the system, generating hardcopy
and inputting programs and data stored un Teletype-punched paper tape .or
issued from the keyboard.
It also s·.pports interfacing of other Teletype-
compatible instrumentation or terminals at 110, 150, 300, 600 or 1,200 baud.
The Model 2209 Nine-Track Magnetic Tape Drive provides the
capability to store programs and data on half-inch IBM compatible
tapes.
A ten inch diameter reel can accommodate up to 20 megabytes
of information.
The Model 2212 Analog Flatbed Plotter (10" x 15") provides
continuous line or point plotting of curves and data, as well as
full alphanumeric labeling of plots with the System 2200.
With the Model 2214 Mark Sense Card Reader, data and programs
can be entered directly into the system via optical mark sense cards.
With this low cost reader cards can be prepared "off-line" without
tying up the keyboard (making the system more efficient) and are
manually fed into the Model 2214.
1-12
The Model 2215 BASIC Keyword Keyboard contains single keys for
most BASIC language verbs and commands.
The keyboard also contains all
alphabetic characters as well as all program execution keys needed to
)
run the System 2200.
The Model 2216 Executive Video Display provides sixteen lines
of 64 characters each, displayed on a 12" (diag. meas.) CRT screen.
The Model 22l6A Upper and Lower Case video Display provides 16
lines of 64 characters each, in either upper or lower case alphanumeric
characters.
The Model 2217 Single Tape Cassette Drive provides a bulk storage
system for both programs and data.
A ISO-foot tape has a capacity of
78,000 (8-bit) bytes, with an input/output transfer rate of 326 bytes
per second.
The Model 2216/2217 Combined CRT Executive Display/Single Tape
Cassette Drive Console is a video display and tape drive contained in
)
the same chassis.
The Model 22l6A/22l7 combined Upper and Lower Case CRT/Single
Tape Drive contains a video display and a tape drive in one chassis.
The display I/O controller provides upper/lower case character output
to the display (22l6A).
The Model 2218 Dual Tape Cassette Drive consists of two tape
drives contained in a single unit.
The tape drives are identical in
operation and performance to the Model 2217.
One CPU I/O Controller
operates both tape drives, but each tape drive operates independently,
with separate device addresses.
The Model 2219 Extended I/O Chassis is a 2200 A, B, or C CPU
option which provides an additional five I/O slots (for a total
capacity of 11 peripheral devices).
)
1-13
The Model 2220 Console contains a 9 inch video display, a cassette
drive, and an upper/lowercase Keyword Keyboard.
The 2220 is a self
contained user terminal and can be used in conjunction with a 2200A.
B, C, S, or T CPU.
On the Model 2221 L"ne Pr"nter (132 column), hardcopy output is
printed at 150 characters per second or 60 to 200 lines per minute,
depending upon line length.
The 2221W Dot Matrix Impact Printer (132-column), hardcopy output
is 200 characters per second and 65-300 lines per minute, depending on
line length.
The Model 2222 Alpha-Numeric TYpewriter Keyboard enables the user
to input upper and lower case alphanumeric characters and program control
and execution keys from a keyboard similar to a standard typewriter
Keyboard.
The 2223 Alphanumeric BASIC Keyword Keyboard enables the user
to input either upper/lowercase characters or most BASIC Programming
words with a single keystroke; an edit feature (std. with C, Sand T
CPU's) allows efficient program editting.
The Model 2224 Disk Mult"plexer allows the use of four System
2200 Central Processing Units with a single disk unit remotely located
up to 500' (152 m.) from each CPU, to maximize use of the disk unit.
The 2226 combines a 12" video display and an upper/lowercase
Keyword Keyboard into one console chassis.
The Model 2227 Telecommunications Controller allows local or
remote asynchronous communication between System 2200's or remote
telecommunications with "foreign" CPUs (IBM, Univac, Honeywell, et cetera).
Model 2200 software enables the system to become an "intelligent terminal"
with the Model 222 7.
The Model
2228 Binary Synchronous Telecommunications Controller t
when accompanied by a suitable modem (modulator/demodulator), and the
terminal emulator program, a System 2200 or a Wang Computer System can
transmit and receive data over dial-up communications lines linking the
1-14
system to another comparably
wh~ch
computer
)
equ~pped
commun~cate
can
The Model 2230-1,2,3
ma~nframe
Wang system or to any
with a IBM 2780
term~nal.
r~xed/Removable D~sk Dr~ves
provides bulk
storage for 1 25, 2.5 or 5 megabytes of information.
The Model 2230MXA Da~sy Cha~n Mult~plexer (1st CPU) and the
2230MXB (2nd, 3rd, or 4th CPU) allows up to 4 CPU's to access any dlSk
system at a maxlmum d~stance of 212' between each CPU.
The Model 2231
L~ne Pr~nter
(80 column) provides permanent hard-
copy output at 100 characters per second or 60 to 150
l~nes
per minute,
dependlng upon llne length.
The Model 2232A
or point
plott~ng
over the
ent~re
by 48
)
~nches
and Mylar.
D~g~tal
Flatbed Plotter provides
cont~nuous l~ne
~
of curves and data with an accuracy of up to
plotting surface.
The plotting surface
The plotter uses any type of paper
F~ber t~p, ballpo~nt,
or
draft~ng
~s
31
~nclud~ng
.005 in.
~nches
vellum,
l~nen
pens can be used.
The Model 2234 Hopper-Feed Punched Card Reader reads up to 250
cards per ~nute (max.) and can stack 550 cards (max.) ~n the ~nput
and output hoppers.
or
b~nary
An SO-column card can be punched
w~th Holler~th
code.
The 2234A Hopper-Feed Punched Card Reader
~s mechan~cally ~dent~cal
to the 2234; however, an expanded I/O controller fac~litates program
entry in Hollerith, as well as data entry
~n B~nary
or
Holler~th
from
punched cards.
The Model 2240-1 and 2240-2 Dual Removable
prov~de
)
Flex~ble D~sk Dr~ves
bulk storage of 262,144 bytes (2240-1) or 524,288 bytes (2240-2)
d~sk dr~ves
of data or programs.
Both
flex~ble
can be
disks,
wh~ch
eas~ly
accept the removable, compact
stored when not
~n
use.
The Model 2241 Thermal Pr~nter prov~des 80 columns of hardcopy (30
characters per second) on continuous form heat-sensitlve paper.
1-15
The Model 2242 Single Renvvable Flexible Disk Drive is similar to
the Model 2240, but contains one flexible disk drive and provides storage
for 262,144 bytes of information.
The Model 2243 Triple Renvvable Flexible Disk Drive contains
three flexible disk drives, and provides storage for a total of 786,432
bytes.
The removable, compact platters (used in the Model 2240, 2242,
and 2243) are interchangeable between the three disk drives of the unit
and any other 2240 series disk system.
The Model 2244 Hopper-Feed Mark Sense/Punched Card Reader
reads up to 250 cards per minute and can stack 550 cards in the input
or output hoppers.
The Model 2244 reads standard 80-column punch cards
(the same card used with the Model 2234); 80-column optical mark sense
cards without clock marks (either punched or marked in pencil); and
optical mark sense cards wi th timing marks and 80 columns or less of
data (punched or marked).
Data entry can be in Hollerith or binary
code.
The 2244A Hopper-Feed Mark Sense/punched-Card Reader is mechanically
identical to the 2244; however, an expanded I/O controller facilitates
program entry in Hollerith, Standard Educational Format and Wang Format,
as well as data entry in Binary or Hollerith.
The Mode1 2250A I/O Interface Controller (8-Bit-Parallel) enables
interfacing of 8-bit parallel I/O devices.
Parallel 8-bit data can be
transmitted or received by a 2250A/2200 system.
The Model 2252 Input Interface Controller (OCD lO-DigitParallel), an input-only interface, is directly compatible to most
digital meters for on-line applications.
It automatically converts
each BCD digit to an ASCII equivalent code. Optionally, it also can
be used to receive up to 40 discrete bits of parallel binary data.
The Model 2252A is a later version of the 2252, and allows manual
selection of 1 to 10 parallel BCD digits to be input to the 2200 CPU.
Groups of 4 discrete binary bits each may be entered by the same select
feature.
Generally speaking, selection of less than 10 digits input
allows faster input processing cycles.
1-16
The Model 2260 nxed/Removable
(10,027,00B total bytes) of
on-l~ne
D~sk Dn ve prov~des
storage.
ten megabytes
The un1t's total storage
capac1ty 1S d1v1ded equally between two separate hard-d1sk platters, one of
)
wh1ch 1S removable and can be conven1ently stored.
The Model 2261
H~gh-Speed Pr~nter
ut1l1zes two b1d1rect1onal
pr1nt1ng heads to pr1nt up to 330 characters per second, or 125 l1neq
per m1nute (132 characters per l1ne, max1mum).
The Model 2262 XY
D~g~t1zer
prov1des the capab1l1ty to d1g1t1ze
s1ngle p01nts or curves on a Cartesian plane at a resolut10n of + .005
inches over the ent1re dig1tiz1ng surface.
The Model 2270 Shugart Floppy
D~sk Chass~s
1S ava1lable 1n three
models (-1, -2, and -3) contain1ng one to three flex1ble d1sk dr1ves.
Th1S unit 1S an 1ntegral part of each WCS (Wang Computer
~ystem;
models
-20 and -30).
The Model 2290
)
CPU/Per~pheral
Stand stores the System 2200 CPU
(e1ther the standard CPU, SiT CPU's, 9-slot
Extended I/O Chass1s) and the Power Supply.
s/r CPU's or the Model 2219
The qtand includes four
electrical outlets and a master ON/OFF switch located on the front.
TI,e table top can accommodate a user terminal, or other perIphpral devIcc.
The Model 2291 Flatbed
Plotter/Per~pheral
Stand provides a qturdy
surface for the Model 2232A Flatbed Plotter.
The 2292 Aux1ll1ary V1deo D1splay 1S a 12" CRT d1splay un1t used
in conjunction w1th standard display capab1lities of the 2200 system.
The 2292 can display the same 1nformation as is presented on a 2216 or
2220 console d1splay.
Up to twelve 2292's may be cascaded.
The 2293 WCS Equ1pment Stand accommodates a 2200 S or T CPU, a
2270 Shugart d1sk drive (up to 3 drives), and a user Input/Output console.
It 1S standard w1th Wang Computer Systems (WCS) -20 and -30.
)
1-17
1.2
MODEL INFORMATION
A Wang serial tag attached to the rear panel of each product
identifies model number, memory size (if applicable), number of I/O
slots (if applicable), and line frequency/voltage/wattage ratings.
TYPICAL SERIAL TAG
PRODUCT LINE
Ll\nnRA10n'r"
(WANG)
MODEL:
2200 B 3
SERIAL#:
2649765
115 VAC / 60 HZ
LI NE VOLTAGE
TYPE CPU
RAM SIZE
LINE FREQUENCY
FIGURE 1-12
Some peripheral devices may be furthur identified by an O.E.M serial
tag (i.e., Diablo, Shugart, Documation, Wangco, etc.).
EXAMPLE:
CPU MODEL
noo
11-1
(MEMORY SIZES)
DESCRIPTION
2200 Advanct'd Pro~rnnuJlilbl(' C.llCtlJdloT
MEMORY SIZE
11K nYlt> Ml'mory
2200 11-2
HK
2200 11-3
12K
2200 B-4
16K
2200 B-5
20K
2200 B-6
24K
2200 B-7
28K
2200 B-8
32K
1-18
1.3
SPECIFICATIONS
115 VAC or 230 VAC + 10%; 50 or 60 Hz;
Power:
550 VA
Operating Temperature:
50°F to 90°F
Operating Humidity:
20% R.H.* to 80% R.H., non-condensing
(65°F to 75°F recommended)
(40% R.H. to 60% R.H. recommended)
*R.H.
1.3.2
2200 CPU;
MODrL~
Relative Humidity
A, n, C, S, T
*Average Execution Times
Add/Subtract
0.8
IDS.
Multiply .....•.....••..•.••....•..•. 3.8 ms.
)
Divide
7.4 ms.
Square Root
46.4
IDS.
ex ••...•.....•.•...•••...••.•....••. 25.3 ms.
logex .........•.....•.....••........ 23.2
IDS.
y
x ••••••••.••••••••••••••••••••••••• 45.4 ms.
Integer ............•..•......••..... 0.24 ms.
Absolute Value
O.02 ms.
Sign ................••.....••......• 0.25 ms.
Sin •..........•.•.........••....•... 38.3
IDS.
Cos ••..........•....•.•..••..•.•...• 38.9
IDS.
Tan
78.5 ms.
Arctan .......•...•..•.•...••..•••.•. 72.5 ms.
Read/Write Cycle .••.••.•...••...••.. 1.6~sec.
*Average execution times determined using Random Number Arguments
with 13 diglts of precision.
Speeds are faster in calculations
with arguments of less precision.
)
1-19
Average Execution Times within Expressions
Add
.80 ms
.80
fiS
7.40
fiS
Square Root
46.40 ms
Log (x)
23.20 ms
X+Y
Integer
.24 ms
Change Sign
.02 ms
Sine
38.30
Tangent
78.50 ms
Absolute value
3.80
Subtract
Divide
x
e
Multiply
fiS
Cosine
38.90 ms
Arctangent
72.50 ms
25.30 ms
45.40
fiS
.25 ms
fiS
2200 A/B INSTRUCTIONS
INSTRUCTION
OPTIMUM TIME
REM
0.384 ms
DEFFN'l:RETURN
3.360
SELECT PRINT 005
0.984 ms
SELECT PRINT 005(64)
1.200 ms
CONDITIONS/REMARKS
fiS
GOTO
2.640 ms
IF THEN (NUMERIC)
4.320 ms
CONDITION NOT MET
IF THEN (NUMERIC)
4.840 ms
CONDITION MET
IF Rl$=HEX THEN NNNN
2.640 ms
IF Rl$=A1$ THEN NNNN
3.120 ms
PRINTUSING, I, A
8.892 ms
DISPLAY 12 CHARACTERS
NEXT
4.380 ms
ON CRT
LET A=B
3.240 ms
LET B=A(l)
5.280 ms
LET B=A(255)
5.400 ms
LET B=123456
2.880 ms
LET X=l
2.880 ms
LET X=Y
3.190 ms
LET X=Y(3)
5.610 ms
Y IS DIMENSIONED
LET X=Y(J)
6.810 ms
J=3
TO 12
1-20
)
)
LET X=Y(3,4)
7.010
ms
DIM Y(6,8)
LET X=Y (J, K)
9.210
ms
J=3, K=4
LET X=Y(J+K)
9.310 ms
DIMYl2 J=3 K=4
LET X=Y(J*K)
10.810 ms
DIM Yl2 J=3 K=4
LET B$='0123456789ABCDEF'
2.460
ms
LET A$=B$
2.700
ms
LET A$=STR(B$,l,16)
5.376
ms
LET A$=STR(B$,8,1)
5.400
ms
LET A$='l'
2.635 ms
LET A$=B$
3.010
ms
DIM A$l,B$l
LET A$=B$
3.900
ms
DIM A$l,B$64
LET A$=B$
4.760
ms
DIM A$64,B$1
LET A$=B$
5.700
ms
DIM A$64,B$64
LET A$=STR(B$,l,l)
7.385
ms
LET STR(A$,l,l)=STR(B$,l,l)
8.310
ms
LET STR(A$,l,64)=STR(B$,l,64)
9.735
ms
LET STR(A$,1,30)=STR(B$,32)
8.160
ms
LET STR(A$,32,1)=STR(B$,32,1)
8.560
ms
LET STR(A$,64,1)=STR(B$,64,1)
8.535 ms
LET STR(A$,64)=STR(B$,64)
6.560
ms
LET STR(A$,l,64)=STR(B$,l,l)
8.435
ms
2200 B INSTRUCTIONS
)
B~LEN(A$)
4.140 ms
B=BAL(A$)
3.960 ms
ADD(A$,Ol)
2.970
ms
ADDC(A$,Ol)
3.000
ms
ADD(A$,B$)
3.696 ms
AND(A$,FF)
6.240
ms
BIN(A$)=64
2.760
ms
BIN(STR(A$,16,l»=64
5.232 ms
BOOL E(A$,55)
5.040 ms
BOOL &(A$,B$)
6.960
ms
CONVERT A TO A$, ( 1111111111)
4.896
ms
CONVERT X*2 TO A$, (+1111./111)
8.360 ms
1-21
CONVERT X TO STR(A$,3,8),(-#.#tttt)7.710 ms
CONVERT A$ TO Z
3.710 ms
CONVERT STR(A$,3,8) TO Z
6.235 ms
CONVERT X TO A$, (11111111.1111111111)
5.560 ms
INIT (80)A$
2.400
B=NUM(A$)
4.800 ms
A$=lO DIGITS
B=NUM(A$)
4.560 ms
A$=l DIGIT
ON B GOTO NNNN
4.800 ms
B=l GOTO CONDITION
ON B GOTO NNNN
2.520
B=5 FALL THROUGH
PACK(#II##)A$ FROM A
4.320 ms
IDS
IDS
CONDITION
PACK(#IIIIII.###II)A$ FROM A
4.704
ROTATE(A$,l)
2.970 ms
ROTATE(A$,n
3.816 ms
UNPACK(###II) A$ TO B
3.960 ms
1.3.3
IDS
MEMORY SIZES
2200 A, B, C Memory Sizes - 4,096 bytes (expandable to 32K in 4K
or 8K increments).
2200 S, T Memory Sizes - 4,096 bytes (expandable to 8K, 12K, 16K,
24K and 32K; 20K and 28K configurations are not possible).
1. 3.4
PERIPHERAL CAPABILITIES
2200 A, B, C - 6 I/O slots (expandable to a maximum of 11 with a
Model 2219 I/O Extended CPU Chassis).
2200 S - 3 I/O slots (6 with OP-20; 9 with OP-20A chassis).
2200 T - 3 I/O slots (6 with OP-20; 9 with OP-20A chassis.
1. 3. 5
DYNAMIC RANGE
2200 (all models)
1.3.6
SUBROUTINE STACKING
2200 (all models) approximately 40 levels
1-22
1.3.7
PHYSICAL PARAMETERS
2200 A, B, C
Dimensions:
CPU Chassis
Height
9 3/4 in.
Depth
16 in.
(40.6 em)
(24.8 em)
Width
17 in.
(43.2 em)
Weight
24 lb. (10.9 kg)
2200 PS (Power Supply for A, B, C CPU):
Chassis
in~
(19.7 em)
Depth
8 3f4 in.
(22.2 em)
Width
19 in.
Weight
34 lb. (15.4 kg)
Height
3f4
(48.3 em)
2200 S, T Dimensions:
CPU Chassis
)
Height
9.8 in.
Depth
21 in. (53.3 em)
(24.8 em)
Width
14.5 in.
Weight
40 lb. (18 kg)
06.8 em)
2200 SYSTEM KEYBOARDS:
Model 2215
Height
3 in. (7.62 em)
Depth
10 in.
Width
17 1/2 in. (44.5 em)
Weight
7 1bs. 0.2 kg)
(25.4 em)
Model 2222
Height
3 in.
Depth
10 in. (25.4 em)
Width
19 1/2 in.
Weight
7 1/2 1bs. 0.4 kg)
)
1-23
(7.62 em)
(49.5 em)
Model 2223
Height
3 in. (7.6 cm)
Depth
10 in. (25.4 cm)
Width
17 1/2 in. (44.5 cm)
Weight
7 lb. (3.2 kg)
2200 SYSTEM DISPLAY (2216):
Screen Size
Height
8 in. (20.3 cm)
Width
10.5 in. (26.7 cm)
Screen Capacity
16 lines, 64 characters/line (1024 Characters, total)
Character Size
Height
0.20 in. (0.51 cm)
Width
0.12 in. (0.30 cm)
CRT Housing Size
Height
Width
'Depth
14 in. (35.6 cm)
21. 5 in. (54.6 cm)
16 in. (40.6 cm)
CRT Housing Weight
36 lbs. (14.4 kg)
Cabling
Eight foot (2.44 m) coaxial cable with BNC connector to CPU
controller card.
2200 SYSTEM CASSETTE DRIVE:
Stop/Start Time
0.09/0.05 sec
1-24
Capacity
522 bytes/ft (1712 bytes/m)
)
Recording Speed
7.5 IPS (19.05 em/sec)
Search Speed
7.5 IPS (19.05 em/sec)
Transfer Rate
326 characters/sec (approx)
Inter-record Gap
0.6 in.
(1. 52 em)
(Capacity and transfer rate include gaps and
redundant recording.)
)
)
1-25
1.4
PERIPHERAL CARLE
MODEL
---ill-
LF,Nr.T"~
STANDARD LENGTH
(Feet/Meters)
01
12 '/3.66 m.
02
12'/3.66 m.
03
9'/2.74 m.
07A
50'/15.24 m.
09
8'/2.44 m.
12
12 '/3.66 m.
MAXIMUM
TESTED LENGTHS
(Feet/Meters)
14
8'/2.44 m.
15
12'/3.66 m.
200'/60.96 m.
16
8'/2.44 m.
1000'/304.80 m.
17
12'/3.66 m.
18
12'/3.66 m.
20
8'/2.44 m.
21
12'/3.66 m.
200 '/60. 96 m.
21W
12'/3.66 m.
22
12'/3.66 m.
200'/60.96 m.
23
12' /3.66 m.
200'/60.96 m.
24
12'/3.66 m.
*500' /152.40 m.
26
8'/2.44 m.
200' /60.96 m.
27
50'/15.24 m.
30
12'/3.66 m.
31
12'/3.66 m.
32,32A
12 '/3.66 m.
34,34A
8'/2.44 m.
40
12'/3.66 m.
41
12' /3. 66 m.
42
12 '/3.66 m.
**500'/152.40 m.
43
12'/3.66 m.
**500'/152.40 m.
**500'/152.40 m.
**500'/152.40 m.
44,44A
8'/2.44m.
50
100'/30.48 m.
52,52A
12' /3.66 m.
60
10'/3.05 m.
61
12'/3.66 m.
62
9'/2.74 m.
70
12'/3.66 m.
**500'/152.40 m.
92
25' /7.63 m.
1000'/304.80 m.
**500'/152.40 m.
*From any 2200; at least one of the 2200 to 2224 cables must be 12 feet.
**Using 2224 or 2230 MXA/MXB
1-26
SECTION 1
NOTES:
)
)
)
1-27
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SECTION 2
INSTALLATION
2.1
INSTALLATION GUIDE FOR WANG SYSTEMS
When a Wang System is delivered, it is not sufficient to merely find
floor space for the System and insert the plugs into an AC outlet.
Some
preparation is necessary to select a suitable location for the system and
to determine if the AC power lines the system will use are adequate.
The
following topics describe the ideal environment in which a System should
operate and the preparations necessary to meet these criteria.
2.1.1
SELECTING A LOCATION
The environment in which a system operates can greatly effect its
performance.
An ideal location would be one in which temperature and
humidity are controlled, airborne dirt and contaminants are reduced to
a minimum, AC power outlets are adequate, regulated, and noise free, and,
)
sufficient room exists for future expansion.
Such locations are difficult
to find; the System must often be installed in a less than favorable
environment.
The selected location should also be one that is easily accessible
by operating personnel, yet sufficiently removed from the main flow of
traffic so as not to interfere with the smooth operation of the 2200
System.
2.1.2
CONTROLLING THE ENVIRONMENT
Once a location is selected, three parameters to be considered
are environmental temperature, humidity, and cleanliness.
Temperature is the most important factor to consider because it
can vary greatly from day-to-day,
The recommended operating temperature
range is from 65°F to 75°F, but the allowable range is from 50°F to 90°F,
)
Low outside temperatures are usually not a problem because nearly all
2-1
locations are heated.
High temperatures can be a problem because many
locations do not have air conditioning.
If the system is used where
temperatures exceed the maximum specified, component failure rates will
drastically increase, resulting in costly downtime for the user.
High
temperatures can also cause warping and distortion of data storage
material, resulting in lost data.
If an air conditioning unit is already installed or if one is to be
installed, it is imperative that a separate power line be used.
If a
separate power line is not used, System errors can occur when the air
conditioner is in use.
While air conditioning is not only good for maintaining the proper
temperature, it also removes moisture and dust from the air, thereby
lowering the humidity.
If the system is installed in a carpeted room,
the lower humidity plus the static generating capability of carpets and
synthetic clothing impart a static electrical charge on operating
personnel.
When the operator comes in contact with the System, the
resultant static discharge is not only uncomfortable, but can cause
System malfunctions and the destruction of recorded data.
The recommended humidity range is from 40% to 60% R.H., but 20%
(In cold weather the humidity in heated buildings can be 10% or lower)
to 80% R.H. is allowable.
Low humidity not only increases the certainty
of static build-up, but also can cause oxide shed in data storage material.
Humidifiers and dehumidifiers should be installed to increase or decrease
the humidity as required.
-/
If carpeting is to be installed, be sure it is a non-static variety.
If carpeting already exists and is not a non-static carpet, it will
either have to be treated with a non-static spray or an electrically
conductive mat must be installed to prevent a static charge build-up.
Carpets treated with non-static spray should be thoroughly cleaned before
the first treatment, and retreated at least once every three months,
thereafter.
If an electrically conductive mat is used, it should be
installed under the system operating area and must be properly connected
to an earth ground.
2-2
Because there are no air filters in most Wang equipment, dirt can
accumulate rapidly on circuit boards and components.
Dirt and grease
form a film that prevents proper heat dissipation from components and
can also create a leakage path for signals.
Dirt also causes excessive
mechanical wear in tape and disc drives and causes scratches in the
oxide coating of storage material and on read/write heads.
To prevent unnecessary failures due to dirt, all air conditioning,
heating and ventilating units should have air filters installed; these
filters should be cleaned or replaced regularly.
In areas where filters
do not remove airborne dirt sufficiently, an electrostatic filter should
be installed.
2.1.3
ELECTRICAL ENVIRnNMENT
For most Wang Systems, a 20 ampere, 115 VAC power line is adequate.
Further System requirements dictate that this line must be regulated
to within + 10% and must be noise free.
)
Wherever feasible, the system
should have its own AC power line.
If the line is not sufficiently regulated to the limits indicated
above, a constant voltage transformer should be installed.
If the line
is 'noisy, however, a detailed analysis of the problem must be performed
to insure a correct solution.
Since computers and peripheral equipments are extremely susceptible
to Electromagnetic Interference (EMI), the source of the EMI must be
determined before a solution is proposed.
EMI can enter the System by
conduction along wiring and cabling or by direct radiation.
If sources
of EMI, which include office machines, air conditioning units, electric
motors~
machinery and arc welders, are in close proximity to the System,
EMI will enter by direct radiation.
The noise generating device should
be relocated, repaired or filtered to prevent it from interfering with
the System.
If the source of the noise cannot be found, an EMI filter
)
2-3
with a cut-off frequency near 10 kHz should be installed on the System's
AC power line.
In all cases, be sure that the AC power line has been
properly installed in steel conduit and that the conduit is properly connected
to junction boxes.
Also, insure that other devices including fluorescent
lighting, are not connected to the AC power line.
In extreme cases, such
as where arc welders are used in the vicinity, it may also be necessary
to shield the peripheral cables.
The ground pin of the AC line cord is connected to the chassis of
the 2200, as recommended by the National Electrical Manufacturer's
Association, and protects operating personnel from electrical shock.
Always connect the 2200 to a grounded outlet to insure safety from
electrical shock.
2.2
DEVICE ADDRESS ASSIGNMENTS
In order to interface each Wang peripheral device with the CPU,
an I/O controller circuit board is inserted in the CPU chassis, linking
CPU to peripheral via interconnecting cable.
Each peripheral device has a unique device address of the form
HEX XYlY ' where X is the device type (or class) and Y Y is a specific
Z
l 2
address manually set on the I/O controller circuit board with switches.
Device tYPe$ (classes) are categorized as follows:
1st HEX Digit (X)
o
Category
Used with console input/output devices
and with the 2209 Nine Track Magnetic
Tape Unit.
1
2
Tape Cassette Drives.
Used with printers which automatically
perform a line feed following a carriage
return; also used with digitizers and
certain telecommunications applications.
2-4
)
3
Disk Drives.
4
Used with plotters; also used with
printers to suppress automatic
carriage return/line feed, format
spaces, or Null Characters; also
used with the Teletype paper tape unit,
to turn the paper tape reader on.
5
Model 2214 Card Reader.
6
Models 2234A and 2244A Stack Card Readers.
The 3-digit HEXADECIMAL device address is printed on the mounting
bracket of the controller circuit board assigned to a particular
peripheral.
Hexadecimal device addresses are listed by I/O class below:
I/O Class
)
Device Addresses
Keyboards
001, 002, 003, 004
CRT Units
005, 006, 007, 008
Tape Cassette Units
IDA, lOB, 10C, 10D, IDE, lOF
Printers
215, 216
Output Writer
211, 212
Plotters
413, 414
Disk Units
310, 320, 330*
Card Reader
517 "628
Stack-Feed Card Readers
C)
Paper Tape Readers
618
Teletype
019, OlA, OIB Input
--.
~
DID, DIE, OIF Output>
Teletype Tape Units
Telecommunications
4lD, 4lE, 4lF
219, 2lA, 2lB Input 1
r
2lD, 2lE, 2lF Output
Parallel I/O Interface
23A, 23C, 23E Input
23B, 23D, 23F Output
)
2-5
v
~1c.
BCD Input Interface
25A, 25B, 25C, 25D, 25E, 25F
Digitizer
25A, 25B, 25C, 25D, 25E, 25F
Nine-Track Tape Unit
07B, 07D, 07F
WCS-lO Triple Controller
001 (keyboard) , 215 (printer),
WCS-20/30 Triple Controller
001 (keyboard) , 215 (printer) ,
lOA (tape cassette)
310 (diskette drive)
*For the Model 2243 (Triple Flexible Drive), the third
device address is 350, 360 or 370; for the WCS/30,
the Flexible Disk has device address 310, and the
Fixed/Removable Disk has device address 320.
*For the Model 2224 and 2230 MX disk multiplexers,
"hog" mode addresses are 390. 3AO and 3BO.
A system with one device belonging to a particular class uses the
first address for that class.
Addition of devices belonging to the
same class are assigned the next higher-order address, as listed above
and in the more detailed listing in Appendix B.
2.2.1
2200 PERIPHERAL DEFAULT ADDRESSES
When 2200 system power is first turned on (initialized), the set
of addresses list on page 2-7 will be valid (automatically preselected)
in the system until changed by a SELECT command, and/or if no device
addresses are supplied within the BASIC I/O statement.
2-6
2200 OPERATIONS/STATEMENTS
SELECT PARAMETER
ADDRESS
&
CARRIAGE WIDTH
(Specified Line Length)
CI (Console Input)
Program Entry, Command & Immediate
001
Mode Operations
CO (Console Output)
System Outputs such as ccho of
005 (64)
console inputs and error messages
DISK (where
applicable)
TAPE
All disk statements
310
Default file designator
Ito
All tape operations
lOA
(DATASAVE, DATALOAD, LOAD, SAVE, etc)
)
LIST
LIST, LIST DC
005 (64)
PRINT
PRINT, PRINTUSING, HEX PRINT
005 (64)
INPUT
INPUT, KEYIN
001
PLOT
413
PLOT (where
applicable)
2.2.2
ADDRESS SETTING ON 2200 I/O CONTROLLER CARDS
There are two types of device address switches on controller boards:
HEX: SWI/:
,------,
HEX:
10
8
4
2
1
80
sWII:
,----...,
I,D
20
~~
10
c;:I::J
J c;:I::J
I,
?
8
4
2
1
o::c:::J
1 c;:I::J
O,!
rrr
(,
r::::;::x:::]
5 r::::;::x:::]
4 crr::::::J
1 DI::J
D:I:::J
D:I:::J
(J1~
FIGURE 2-1
)
" C!I:J
7 r::::;::x:::]
(IFF
FIGURE 2-2
8-BANK ROCKER TYPE
ADDRESS SWITCH
5-BANK ROCKER TYPE
ADDRESS SIHTCH
2-7
The 8-bank rocker-type address switch located on the 6374 I/O board
18
set as shown in the example below.
FIGURE 2-3
DEV] CE ADDRESS
SWITCH
FIGURE 2-4
EXAMPLE:
HEX ADDRESS
FOR TAPE
READER
618
16
6 = MICROPROGRAM HEX
DIGIT
1
HIGH ORDER
SWITCH
8
LOW ORDER
SWITCH
1, 2, 4, 8
10, 20, 40, 80
2-8
LOW ORDER SWITCHES
HIGH ORDER SWITCHES
The HEXADECIMAL address (of the form XY Y2) must be broken down:
1
)
x - The most significant digit of the HEX address.
Used by
2200 microprogram; NOT USED in device address switch
settings.
o
As
explained previously, this is a digit from
to 6, identifying a particular class of device.
Y - Next most significant digit of the HEX address. This HEX
1
digit, broken down into four Binary bits, determines the
settings of switches 8 through 5.
HEX VALUE
80
40
20
10
SWITCH 1/
SW8
SW7
SW6
SW5
HEX DIGIT
)
0
0
0
0
0
1
0
0
0
1
2
0
0
1
0
3
0
0
1
1
4
0
1
0
0
5
0
1
0
1
6
0
1
1
0
7
0
1
1
1
8
1
0
0
0
9
1
0
0
1
A
1
0
1
0
B
1
0
1
1
C
1
1
0
0
D
1
1
0
1
E
1
1
1
0
F
1
1
1
1
Where:
)
1
=
switch is ON,
0 = switch is off.
2-9
Y2 - Least most significant digit of the HEX address.
Broken down
into four Binary bits, this HEX digit determines the settings
of switches 4
throu~h
1.
HEX VALUE
8
4
2
1
SWITCH II
HEX DIGIT
SW4
SW3
SW2
SW1
0
0
0
0
0
1
0
0
0
1
2
0
0
1
0
3
0
0
1
1
4
0
1
0
0
5
0
1
r
1
6
0
1
1
0
7
0
1
1
1
8
1
0
0
0
9
1
0
0
1
A
1
0
1
0
B
1
0
1
1
C
1
1
0
0
D
1
1
0
1
E
1
1
1
0
F
1
1
1
1
Where 1
o
2-10
switch ON
switch OFF
The 6309 pc (2200 A, B, C) and 6709 pc (2200 S, T) must be checked
for proper RN1 size setup.
Two versjons of 0309 exist:
one with a
5-bank rocker switch, and an earlier version with strapping (jumper
wires) in place of the switches.
The 6709 pc has a 5-bank rocker
switch for RAM address setup.
Verify the following, according to RAM size and 6309/6709 pc supplied
with the system.
6309 (version without switches) connections
for RAM Capacity
MEMORY
1 BIT
SIZE
)
4 BIT
2 BIT
8BIT
L8 - pin 5
L8 - pin 11
L7 - pin 5
L7 - pin 11
TO:
TO:
TO:
TO:
4K
+OV
-
+5V
+5V
+5V
8K
+OV
+OV
-
+5V
+5V
12K
-+OV
+5V
+OV
-
+5V
16K
+OV
+OV
-
+OV
+5V
20K
+OV
-
+5V
+5V
-+OV
24K
+OV
-
+OV
-
+5V
-+OV
28K
+OV
-
+5V
-+OV
+OV
32K
+OV
+OV
+OV
-
+{)V
~
~
6309/6709 Switch Settings for RAM Capacity
SWITCH
)
4K
8K
12K
16K
20K
24K
28K
32K
l(ADD 16K)
0
0
0
0
1
1
1
1
2 (ADD
8K)
0
0
1
1
0
0
1
1
3 (ADD
4K)
0
1
0
1
0
1
0
1
4(NOT USED)
X
X
X
X
X
X
X
X
5(NOT USED)
X
X
X
X
X
X
X
X
Where:
1
Switch ON
0
Switch OFF
X· Don't Care
2-11
6309 PC
RAM SIZE
SWITCH
6709 PC
RAM SIZE
SWITCH
FIGURE 2-5
2.4
INCOMING INSPECTION
1)
Unpack and inspect each unit for possible shipping damage.
Exercise extreme caution when unpacking the 2216 Video Display
unit.
Report to the shipping carrier and Horne Office immediately
any physical damage.
2)
Remove CPU top cover plate and ensure that all pc boards are
firmly plugged into the correct socket.
3)
If the CPU is a model A, B or C, a 2200 PS will be included
in the system.
Remove the top cover of the 2200 PS Power
Supply and inspect for damage.
4)
Remove top cover of the Video Display console and inspect for
damage.
5)
USE EXTREME CAUTION.
Remove covers to other peripheral devices and inspect for damaged
or loosened assemblies.
6)
For 2200 A, B or C systems, leave 2200 PS cover off; for
2200 S or T systems, leave CPU cover off.
all other units.
2-12
Replace covers to
7)
Perform voltage check procedure documented in Section 8.
This
eliminates the possibility of causing component failures due
to improperly adjusted supply voltages.
2.5
INSTALLATION PROCEDURE
1.
Ensure that all pc boards are properly seated in
their connectors after verifying switch settings,
voltages, etc.
2.
Replace all chassis covers.
3.
Connect peripherals to CPU I/O controllers.
Ensure
lock clips on peripheral cable connectors are snapped
in.
FIGURE 2-6
)
•
PERIPHERAL CONTROLLER AMPHENOL I/O CONNECTORS
4.
8e certain that each peripheral is connected to the
proper CPU I/O controller.
5.
Plug the main power cable from the CPU chassis into the
2200 PS (for A, B, C units).
)
6.
With all AC power switches in the system OFF, plug
in all AC line cords.
2-13
7.
Once the system has been properly installed and initialized
by switching the CPU (2200 S, T) or 2200 PS (2200 A, B, C)
ON, the "READY" indication should appear in the upper
left corner of the video display screen.
FIGURE 2-7
'" £MM'
CURSOR
CPU INITIALIZATION
(POWER UP)
The system should now be ready for initial checkout.
B.
For initial checkout, run appropriate diagnostic tests to
verify operation of each unit in the system (i.e., CPU, options,
peripherals) Manual Keyboard/Display operations must also
be verified.
NOTE
All 2200 Options must be installed by a Wang
Laboratories Customer Engineer or representative;
no user-installed options/conversions/retrofits
are offered. Consult Section 9 for Conversions.
2-14
SECTION 2
NOTES:
)
)
2-15
1
1
1
1
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1
1
1
1
1
1
1
1
1
1
1
Pl
1
1
1
1
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1
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1
SECTION 3
OPERATION
3.1
GENERAL
Refer to the 2200 BASIC Programming Manual (WL #700-3231B), the
2200 Reference Manual (WL #700-3038) and other pertinent peripheral
reference manuals for user instructions in total system operation.
For those already familiar with 2200 system BASIC language, the System
2200 Pocket Guide (WL #700-3030B) will provide quick reference to most
general 2200 programming information.
3.2
3.2.1
PROGRAMMING OF OUTPUT DEVICES
THE SELECT STATEMENT
The SELECT statement must be used to select the input or output
devices.
)
A SELECT statement can be used either in the immediate mode
or as a statement within a program.
When used, the syntax of the seLECT
statement requires that it contain a PRINT, LIST or CO command and a
Device Type Code.
Line length can also be specified.
Each of these
SELECT parameters is described below.
3.2.2
DEVICE TYPE CODES
To restate, every peripheral attached to the WANG System 2200 is
assigned a three-character Device Type Code.
The Device Code is in the
form (XYY), where X is the Device Type and YY is the Device Address.
The Device Type (X) determines which internal System 2200 I/O routines
are used to control the device.
Some devices automatically execute a
line feed (i.e., advances the paper to a new line) following the
execution of a carriage return while others do not.
In most cases,
carriage return commands are initiated from the System 2200 CPU.
However,
there is one exception to this rule; certain printers initiate their own
carriage return command whenever 80 characters (including spaces) are
)
printed on a single line.
3-1
TYPE
o
OPERATION
This Device Type addresses devices that do not automatically
execute a line feed after a carriage return; therefore the
System 2200 supplies a line feed after each system-generated
carriage return.
When this Device Type is selected for the
Printers with CR/LF, for instance, output which is normally
single spaced is now double spaced.
2
This Device Type addresses devices that automatically execute
a line feed after a carriage return; it is the Device Type
normally used with the Printer.
With this Device Type, the
System 2200 does not supply a line feed command after each
system-generated carriage return.
When using this Device
Type for single spaced output, only 79 or 131 characters can
be output per line with printers (see paragraph 3.2.7).
4
This Device Type suppresses the automatic carriage return
issued by the System 2200 at the end of PRINT, PRINTUSING
and HEXPRTNT statements that contain no trailing punctuation.
Whenever a system-generated carriage return is initiated,
the system automatically adds a line feed following it.
The
use of this Device Type is further discussed in the section
on Special Techniques (see paragraph 3.2.7).
The results of using the various device types with an 80 column
printer are shown in Figures 3-1 through 3-4.
The device address (YY) of the I/O Controllers are preset to the
primary addresses by WANG Laboratories before the unit is shipped, and
must be the address used in SELECT statements used with those devices.
For example, a printer is set to 15.
If a second printer is used on
the same System 2200, it is assigned device address 16 by the WANG
Service Representative who installs a system.
be any of the following:
The second Printer can
Model 2261 High-Speed Printer, Model 2221
Line Printer (132 column), Model 2231 Line Printer (80 column) or Model
2241 Thermal Printer.
3-2
THIS PPOGRAtl
WITH THE OBVIOUS CHANGES IN THE PRltn
TATEMENT WRS USED IN RLL
EYAMPLES
:I.0FQRI=:l.TO:l.e
:I.:I.:I.11:l.:l.1.112':222'2'22~
. ... :::a:] .... ]4444444444'5~'5~55'5'5'5:566'=o666666677177
20 PRINT
7
7777
88see···.... 30 NEYT I
11:111:111112222222.:221:;;:13:13334444444444'5'555'5'5'5'555666666666'=077777
77777ElSSSS"'''''''....
:l.1111:1.11:1.:l.22222222223333333334444444444'5'5'5~:5'5'5'55S66666
'=0666677777
777""7ElSsSe..........
11:1.:l.111:1.:I.:l.22222222223333333...:4444444444'5'5'5SSSSS:556666b6666677777
77777e888s·........
11:l1.11:1.:I.1:1.222222222233332333344444444445SS5~'55S55066666
6'=06677777
77777SS8SS......"''''
11:1..1:1.111112222222222333333333444444444455'55'5'55555"'06666666677777
777778E- ~8e"'......"
IN THE ABOVE EYAl"lPLE THE STATEMENT SELEl T PRINT 2.1'5 WAS USED
ACTUAL LINE LENGTH WFl§ 8E1 64 IS THE DEFAULT 'lRLUE FO\< LWE LE~./(,TH
1:1.:1.1.1.1:1..111..:222222222:;33::33:33344444444445555S555S5666666666677777777778888e..........
11:1.11.:1.11:1.122;l2222222J.3::l.33333:>34444444444SS5'5'5555556666;;6666677777 77777888aS.........
11.11.1:1..1:1.:1.12222222222333333333344444444445:555'5'55555666666666677777777778888S..........
.1.1.11.1.:11:1..112222222222333333333344444444445'5'55555'5'556666666666777777777788888.......
111:1:1.1.111:1.2222222222333::33333:;;44444444445'=>5'555555'5'>0666666667777777777S8SSS."'.....
IN THE ABOVE E.><.RMPLE
LENGTH WAS
as so
THE cTFlTEtlENT :"ELECT PRINT 215,$S) WAS USED
AN A{!('!TIGUAL
C~
IF
ACTUAL LINE
UC'-UF~
:11:1:1111:11:1.2222222222333333333:;;44444444445:5'55'=>55'=>'5566666666667777777777888138••••
11111:1.11:1.:1.2222222222333333333)4444444444'=>'=>'=>55,=>'555566666666667777777777138131313........
.1.1.1.11:1.111:122222222.22333333333)4444444444'=>5'55'=>'55'5556666666666777777777788888••••
1111:11.1.1.:1.1222222222233333333334444444444'=>'=>555555'556666666666777777777788888.......
1.:1.:1.:1.1:11.111222222222233333333334444444444555'5'555'5556666666666777777777788888••••
11.1.1:11:1.1..112222222.2223333333333444444444455:5555'555566666666667777777777S8SS8
.
1U.:111.1H.1.222222.i!.i!.i!233333333334444444444'5:5'5'55555SS6666666666777777777788888
..
111U.:1111:122222222223333333!334444444444'55'5'5'5555'5'56666666666777777777788888
..
1:1:1:11:1..1.11122222222223333333333444444444455'5'55555'556666666666777777777788888"' .
1:1.:111:1..1.1:112222222222333333333344444444445'55'55555:5:56666666666777777777788888•••'"
11:1:11111:1.1222222222233:3::.. ~3::3444444444455555555S5666666666677777777778813138....'"
IN nE ABOVE: EXAMPLE
THE: STATEMENT SELECT PRINT 215<El0' WAS USED ACTUAL LINE
)
:11:1.11111:1:1.22222222223:1333333134444444444'55'=>'=>55'5'55'561:.66666666777777777788888888S'"
1:1.:1:1.:1..1.1.11:1.22222222223:;;33333.33344444444445'55'35555550566666";666777777777788888888a"
.1.11.1:1.111.1.1.22222222223:;;3:3333334444444444555'=>5'5'5'5556'=0666666667,.,'77777778a88888S8"
:1..1.1.1111.1..1.122222222223;:3:333333344444444445'5'5555'55'5'5666666666677777777""7a888888as_
:1.1J..1:1.:l.l:l.U22.:2222222333::333J.334444444444'S'SSS5'5"'555S66666666667777777777S8888$888.
:1:1.:I..1.:I.:l.11:1:122222222221333::.3333J444444444455'5'55'5'5'=>'5566";66666667,-'77777778asaSSS88'"
HL\
.. ~E ABOI,E E'<AMPLE
THE ::TATEr1ENT SELE T PP!NT 01'5<88' WAS USED
LU& I-EN1.>Tti lilA:: cot
.1.1J..1:1.J..11.1:1.2.:.... _.2.U,,:,<:: ~
:4444444444':55555'55'5'505o5o566<5666':;77777777778a888888S8
:1..1.1..1:1.:1..1..1.1.12.=:""... 2
.;::...::: _ ___ .;,_~4444444444'55'55S~::;S'55b~6666~7777777777S6a88aae88
.1.1.1.1:1.:1:1.1:1:1.222.2~2 ,.22__ ::3..!>::?::;;4444444..44'5'5'55'5'5'5'5s.>66666666I$777777777786S8888S8a
.1.:1.1:1:1:1.111122222::: ''':''':~~:::_:::4444444444'5'555'55'55'''''o566'1Ii6666.777777777St!l88S88SS8
11.1.1.1.11..1..1:l22222~222,_:: :3: _ :: : _ 4444444444'5'555'55''5'5~66"666<:>6777777'77786S88saa88
:1:1.:1.u..1:1..1:1.1222.22.<:.......... 2:
_:
444444
44';i'5'5'555:5'55'5666666'&S667777777777888B888a88
1:11U.11:1..1.::i.24:.2.2...:____
4-144-1-1-1
45'5555'55'55S<6'1$66oi6l56'1$o57777777771888SSSSses
:1.:1.:1.1:1..11.1.1.:1.22.2.2 __
-I .. -I-I"-I4-1"4'5555'55'!5'55'5666ti<6'666667777777777eess888SSS
.1.1:1.1.1:1111:1222;:' __
-I
4'5'5'5'5'55'5'5'51;66666666677777777778888888S88
.1.1.1.1.11.1.11.12222':__
-I
H4
.,.C;'5'5'55'5'5550S'I$o5056666'1$o5777i777"''7788SS8888Sl:.
JfJ
I..IN~
FIGURE 3-1.
rH!o HE.~'Vt E-HIlFLE
LEN..,fH r~ri;:' ~l<I
THE
~THTE~'Ern
"!oLE' T FRlrn
-as "'''''
WH3
U~E(
Samples of Printout Using Different Device Type Codes,
Line Lengths and PRINT.
)
3-3
~ELECT
LIST
FIGURE 3-2
0i5~80\
LIST
10 FOP I = 1 TO 10
"liliiLl1i12~~2~~~~~2~}3~33~33344444444445555555555b6b
66666667777777777
20 FRINT
88888*,...+ ...... "
Ir~ THE ABO".,'E E:--:At'lF'LE THE STATEt'lE~n SELECT LIST 0.15',80)
~·JAS U5EC,
FIGURE 3-3
SELECT LI5T 215'64'
LIST
ia FOR I
= .1 TO 10
20 PRINT ".1.11.11.11i~.1~2~2~22222~]J~:}:2~]444444444455555555556666
666666777777;"77788888** +:t:-+ "
30 NE'.T I
H4 THE ABO',,'F E. AI'1FLE,
SELECT LIST
THE STATEt'lENT SELECT LIST 2.15(64) l,JAS USED
FIGURE 3-4
~L5'80'
LIST
.10 FOP I = .1 TO 10
20 FPINT ".111.1L111.1.122~~~~2222::~~:3~:3}44444444445555555555666
66666667777777777
88888"***'+<"
s0 NEAT I
H~
THE
ABO~/E
E,'.ANf-·LE,
THE :,TATEI'lENT SELECT LIST 215(80) WAS USED
Sample Printout using LIST with Different Device Type Codes and
Line Lengths
3-4
3.2.3
PRINT
I: SELECT
)
PRINT 2151
This statement selects the Printer with the Device Type Code and
address 15 for all program output resulting from the execution of PRINT,
PRINTUSING or HEXPRlNT statements.
Printout resulting from PRINT
statements entered in the immediate mode appear on the CRT unless the
Printer is selected for m (see SELECT CO 215).
Example:
: 10 SELECT PRINT 215
: SELECT PRINT 215
or
: 10 PRINT "X","Xt2"
:20 PRINT "X","Xt2"
: 30 FOR X=l TO 5
:20 FOR X=l TO 5
:40 PRINT X,Xt2
:30 PRINT X,Xt2
:50 NEXT X
:40 NEXT X
When either of these programs is executed, the printed output is:
x
)
3.2.4
Xt2
1
1
2
4
3
9
4
16
5
25
LIST
I:SELECT LIST 2151
This statement selects the Printer with the Device Type Code and
address 15 for all program listings.
Example:
To list the program in the first example above on the Printer, key
)
in as immediate mode statements:
3-5
: SELECT LIST 215
:LIST
The printed output is:
10 SELECT PRINT 215
20 PRINT IIX", ''Xt2 1l
30 FOR X=l TO 5
40 PRINT X,Xt2
50 NEXT X
3.2.5
CONSOLE OUTPUT
This statement selects the Printer with Device Type Code and address
15 for all console output.
READY message;
This includes all system displays, such as the
output from STOP and END statements; and data keyed in
on the keyboard and entered into the System 2200; and all output from
immediate mode operations, TRACE statements, and error messages.
Example:
Key in as an immediate mode statement SELECT CO 215, touch the
RETURN/EXECUTE Key and touch the RESET key.
The output on the printer
is:
: READY
All information entered in the System 2200 via the keyboard is now
printed on the Printer.
3.2.6
LINE LENGTH
The maximum number of characters per line that can be printed is
255.
To accommodate various paper widths and special forms whose width
is less than 255 characters, the length of the output line can be
specified by enclosing the desired line length in parentheses following
the Device Type Code in the SELECT statement.
This number is stored
within the System 2200 and indicates the effective line length of the
selected device to the System.
For example:
3-6
SELECT PRINT 215 (80)
(Selects a printer for printing, sets
SELECT LIST 215 (50)
(Selects a printer for listing, sets
SELECT CO 215 (75)
(Selects a printer for console output,
line length to 80)
line length to 50)
sets line length to 75)
If a line length is not specified for PRINT, LIST or CO, the last
line lengths selected for these operations are used.
sets these line lengths to 64 characters.
Master Initialization
The maximum line length which
can be specified in a SELECT statement is 255.
However, the use of a
line length greater than the physical carriage width of a specific
peripheral device is not recommended.
The line length setting is used by the System 2200 to generate an
automatic carriage return when a line exceeds the specified line length
and when no carriage return is supplied by the program.
printout from being lost.
)
This prevents
As a line of output is printed on a device,
the System 2200 keeps a count of the number of characters sent.
If
this line count equals the current value of the line length before
the output line is complete, a carriage return is executed, the line
count is reset to zero, and the unfinished output is continued on the
next line.
If the output is completed and a carriage return is trans-
mitted before the line count equals the line length, the system automatically resets the line count to zero for the start of a new line (a
print statement with no trailing comma or semi-colon causes a carriage
return to be executed at the end of the output).
The line count is
reset to zero under anyone of the following conditions:
1.
2.
The line count equals the line length.
A carriage return is output when a PRINT, PRINTUSING or
HEXPRINT statement is executed.
not reset the line count.)
)
3.
The system is RESET.
4.
A CLEAR command is executed.
5.
The sytem is Master Initialized.
3-7
(Printing a HEX(OD) does
The following example illustrates the automatic carriage return
generated by the selected line length.
This program is entered in the
CPU (note line length is set to 5):
10 SELECT PRINT 215 (5)
20 PRINT "THE QUICK BROWN FOX JUMPS OVER THE LAZY OOG"
When the program is executed, it produces the following output:
THE Q
UICK
BROWN
FOX
JUMPS
OVER
THE
!.J\Zy
DOG
Note that spaces in the line are included in the line count.
3.2.7
SPECIAL TECHNIQUES
The normal Device Type used with printers is type 2.
When the
Printer is selected with this device type for LIST, PRINT, or CO,
normal single spaced output is produced.
with printers.
Device Type 0 can also be used
In this case, output which appears single spaced
under type 2 appears double spaced.
This is because both the CPU and
the Printer execute line feed commands following each system-generated
carriage return.
Device Type 4 in
in~ended
for use with System 2200 plotter peri-
pherals and has limited application with other types of peripherals.
There are, however, two instances where it can be of use with the Model
2231 Printer.
3-8
USING DEVICE TYPE 4 TO LIST AND PRINT (WITH 2231)
)
10 FOP I
=
~(1
"1111111111~~.2.2222.2';::.2::::::::'::::444444444455555555556.;r;66666667;"7;";";-'777-;­
F'PIrlT
1 TO 10
8888888E:8 + ..
:0 tIE::r I
IrJ THE AE:O'·/E E:AI'1F'LE.
THE STATEl'lEtn SELECT LIST 4.15' 8(1
I
I,JAS U,;£O
FIGURE 3-5
1111.l11111<h..::,;:·.:..:....:.::~.:...~.::::...:- .:
::::--.:.: ':4444444444'Y555S'::'S':,556':'t;.6br::-.':'t:.66;-;--;-((';"7;--;--;-88:::88+'''
111111111~2~.2_~....:~~~':~
=_'::::444444444455555555556666t66r;.66;";-;"7-;--;-;7;;88888*+++11
11111111~~~~2~':":~'::~':::::::
1111111~~~~~~~.:...
111111~~.:...~'::~:"":~"":_':_':
-=:
::::'::::
__ :':
f
+1
':~_44444444445555555555~6666b6666-;-(77;-;--;-7;-;-88888~~.~11~
::::::44444444445555~55555r::t.66666r::6,=;;";;"-;--;-;;7788888**+~1111
:4444444444555'55555556666666666;";;;";7;-'77788888·~**~11111
11111~~~~~~22~_===~=~_=_ 444444444455555555~,5~bb6b6bb66~~~~~~~~~~88888*~*~111111
lt~
THE t1Eu'··'E E. HHF'LE
THE ST8TEi'lErn :=ELECT F'~·Itn 415' ::::0' l·lA:=-. USEe·
ln4llfH (WI
FIGURE 3-6
)
3-9
ACTUAL Llt4E
The first instance concerns the printing of lines which contain
exactly 80 characters.
Assume the Printer has been selected with Device
Type 2 and Line Length 80 (i.e., SELECT PRINT 215 (80)).
For output
lines fewer than 80 characters in length and containing no trailing
punctuation, the CPU issues a carriage return following the final character in the line.
The Printer follows this carriage return with an
automatic line feed.
beneath the first.
The next line of output is then printed directly
When a line containing exactly 80 characters is
printed, an additional event occurs.
After the 80th character is
printed, the Printer itself executes a carriage return followed by an
automatic line feed.
The CPU then issues the carriage return that
normally occurs when the line count equals the selected line length,
and the Printer follows this with another automatic line feed.
result is a skipped line before the next line of output.
The
Note that if
single spacing is required, only 79 characters can be output when using
SELECT PRINT 215.
This skipped line can be avoided by using the following technique.
Immediately before printing one or more consecutive PRINT, PRINTUSING
or HEXPRINT statements, any of which produces an output line containing
exactly 80 characters, place a SELECT PRINT 415 statement in the program.
Before the next statement that prints a line of fewer than 80 characters;
include a SELECT PRINT 215 statement.
Example:
100 SELECT PRINT 415
110 PRINT (output line of exactly 80 characters)
·120 PRINTUSING 130, A,B,C
130 % (image containing exactly 80 characters)
140 SELECT PRINT 215
150 HEX PRINT A$ (output line of fewer than 80 characters)
This technique works because the Device Type 4 suppresses the normal
carriage return supplied by the CPU at the end of the PRINT statements
in lines 110 and 120.
The only carriage returns (and subsequent line
feeds) produced are those supplied by the Printer when the 80th character
of lines 110 and 120 are printed.
Care must be taken to ensure that
3-10
output lines containing fewer than 80 characters are not printed while
the printer, for instance, is selected with Device Type 4.
occurs,
If this
the output from consecutive print statements is printed allan
one line until the end of the printer carriage is reached; at this
time carriage return and line feed are automatically executed by the
Printer.
If output stops in mid-line, for example, the next PRINT
statement encountered causes printing to begin at the next space in
the line.
To clear the Printer buffer, deselect the Printer by
pressing the lit SELECT switch.
Light the SELECT switch again to
continue operations.
Device Type 4 is also useful in producing of double spaced program
listings.
Normally, when double spacing is desired,
the Printer is
selected with Device Type 0 (i.e., SELECT LIST 015).
In this case,
all LIST output is double spaced.
Carriage returns followed by line
feeds are initiated by the CPU at the end of each program text line as
well as whenever the line count equals the selected line length.
a printer executes a carriage return,
After
it generates another line feed,
producing the double spacing after each printed line.
)
With Device Type 4, the CPU suppresses the carriage return (and
therefore the accompanying line feed) normally supplied when the line
count equals the selected line length.
The carriage return that normally
follows the end of a text line is not affected.
COMBINED PARAMETERS
It is possible to combine parameters in a SELECT statement
Example:
SELECT PRINT 215 (80), LIST 215 (80), CO 215 (75)
but it is not possible to select two output devices for the same
parameter,
i.e.,
the statement
SELECT LIST 215, LIST 005
)
will allow listing of programs only on the CRT.
3-11
3.2.8
SUMMARY 0F CONSOLE AND NON-<:ONSOLE DEVICE OUTPUT FROM CPU
Figure 3-7 applies for output to non-console peripheral devices
only.
Due to the complexity of the CPU instruction set and the differences
in printing or display devices that can be selected for console output,
a chart for console output variations is nearly impossible.
However,
there are several basic rules which apply to the CRT as a console output
device which will be described here.
1.
All ERROR, STOP and END PROGRAM messages are displayed on the
Console Output Device regardless of the device selected for
PRINT.
Also, all immediate mode PRINT statements are displayed
on the Console Output Device.
2.
When a printable character is printed, the CRT Cursor is moved
one position to the right and the line character counter is incremented.
If a non-printable character is printed (HEX 00 thru
OF), the cursor does not move nor is the line character counter incremented.
3.
When any BASIC statement is executed, a CR{LF is generated.
The CR{LF will be printed at the completion of a program or at
the completion of a statement in HALT{STEP.
4.
When zoned format is specified (comma separating print elements)
all characters in the print element are printed as an entity.
Therefore, if a statement specifies seventeen characters to be
printed in zone four, sixteen will not be printed in zone four and
the remainder in zone one, but all seventeen will be printed in
zone one of the next line.
5.
When more than sixteen lines are printed on the CRT, a "roll"
is performed, moving all printed lines up one line.
Whenever
a roll is performed, a CR{LF is automatically generated.
It is
therefore impossible to do a line feed or other cursor line
movement without generating a CR{LF.
3-12
I FIGURE
3-7
I
',"
•!
g
"l
Q
"l
..l
o
rfJ
Z
o
u
)
=-------------l~~l
THIS PAGE INTENTIONALLY LEFT BLANK.
3-14
SECTION 3
)
NOTES:
)
3-15
SECTION 4
THEORY OF OPERATION
4.1
CPU
4.1.1
DESCRIPTION
G~ERAl
INTRJDUCTION
The 22JO CPU is a single-user, noninterrupt, microprogrammed
system whicn allows a user to execute programs written in 2200 BASIC
language.
2200
a~IC
is a conversational-interpreter language.
to learn and use,
It is easy
and can be used not only for on-line conversational
computing, but also for a wide range of scientific and business applications.
4.1.2
)
HARDWARE VERSUS SOFTWARE
The 2200 CPU can be thought of to be a computer within a computer.
At the
hard~are
subassembli~s:
level is the inner computer, consisting of the following
an arithmetic logic unit,
ters, and Llput/output buses.
the data memory, several regis-
These subassemblies are composed of discrete
logic devices interconnected to perform the various functions required.
The in3er computer cannot function by itself.
It requires some type
of control to transfer data through the subassemblies and perform various
operation~.
The necessary control was written in the form of a program
in machine Language by the designer.
Machine language is simply the
binary language of ones and zeroes which the CPU can understand.
The
machine language program which controls the CPU is known as the microcode.
The microcode consists of many individual machine language instructions
called microinstructions.
Around the inner computer is the outer computer, or user level
computer.
)
The user level computer is controlled by the operator, who
directs the inner computer to perform various tasks and functions.
4-1
The
user does not directly control the inner computer because the user's
language is BASIC and the inner computer uses machine language.
user's BASIC languEge program is referred to as software.
The
To convert
the software to machine language instructions that can be executed by
the CPU, a method of translation is required.
Such a method of trans-
lation is used in the 2200 and is known as a BASIC interpreter.
An
interpreter transl&tes one BASIC language statement at a time, executes
the necessary machine language ins truc tions at onl'.e, then translates
the next BASIC statement, etc.
Note that the interpreter method of
translation differc from other translators (compilers and assemblers).
The translator program for the 2200 is permanently stored in the
Instruction ROM for convenience.
The Instruction ROM contains all the
machine language ir.structions necessary to control the CPU, as described
previously.
The translator program is also sometimes referred to as the
firmware.
The translator program is written in sets of routines which adapt
the user level computer to the inner computer.
is written to interpret each IlA.SIC statement.
Essentially, one routine
Eacb routine consists of
a series of machine language instructions called a microroutine.
AlII
FIGURE 4-1
SIMPLIFIED 2200 CPU BLOCK DIAGRAM
4-2
As
wlth the llser'<-, program,
the nucrOlostructl0ns are executed sequentlally,
hilt nny
lIH.. sequence when certalTl condltlOll'-. are met.
I1so
Jump out of
i .... known
111\
HIH 0 III Illl '->.
tn
out of
lOci
II
1 ....
JJl(
I/{
I IH
mo .... t
01
thl
n
11/111
\10(£'
llt
tr'lilbldtor progr 1m I
L1H
III I III ....
utd III
(0Il1I1l1111
mloilnJ7f-J by hr mclting
. . . l1hrollt loe.
til(
10 prOll-'-,S llll
'->0 ftw'lre,
recogol/ed by thL (PU
thL BASIC word entered by the user IS
lite flrmw'lre IS then dIrected to the routIne
that Wlll tnnolate the BASIL '''''rd and perform the necessary data
manIpulatIons.
Each mlLrOInstructIon .in the fIrmware controls the flow of data
through the (PU.
the ALU,
.'-> it
arlthrnetu
ALU,
)
The moot important data path 1n the CPU 1S through
IS the 'workhorse t
of the CPU, performl.ng the necessary
1I1d Hooll-an functlons.
SInce ,11 data mUht flow through the
th( InI IOlnstruLtIon not only bpecl.fl.ec; the data flow path, but
also e.,peL.iflC'
the type of functIon the ALU IS to perform.
The Al U lequI1Ps two data word Inputs,
or regIster sources,
to
perform the lnd1.c"lted operatIon on, and one resultant data word output,
which 15 sent to the dest1nat10n reg1ster.
paths for wput
In the 2200 CPU, the data
to the ALU are des1gnated the A Bus and the B Bus, and
the output from the ALU 1S des1gnated the C Bus.
for the ALU sourcp
The reg1sters selected
(A and B Buses) can also be designated for the ALU
debt1nat1on (C BUb) and/or the resultant data can be sent to the Data Memory.
AgaIn, the TI11crcnnstrtJct1on specifies the regIster sources and the
det>tInatIon
To Eu rtlll r
understand how the firmware ties the micro-level computer
lo the user-ll- vel compu ter, a generalized descrIptIon of the CPU hardware
mJ the
)
Al'-,(l,
t>J
,.,!lOWll
III
phy . . . H 11
IDJ
croe ode
InstructIons IS descrIbed In the followIng paragraphs.
mp] 1 f I eel b lock dIagrams of each of the PC Boards In the CPU are
J
J)
un.. '"
/1
)
lhrough 4-1],
to famIlIarIze the reader wIth the
loe It.iOll of the h'lrdware components.
4-3
4.1. 3
GENERAL HARDWARE DESCRIPTION
4.1.3.1
1.)
Register Structure
Status Registers
There are four 4-bit Status Registers used to sense or set various
2200 conditions.
Status Register 1 (6311-L19, L20) sets the RAM/ROM
selection and Input Device inhibit and senses Special Function keys
and arithmetic 'carry' operations (6310-L46).
Status Register 2
(6311-L16) is set by the microprogram to indicate the phase and
processing mode.
Status Register 3 (6311-L18) sets the memory
addressing mode and senses HALT/STEP, I/O device busy and other I/O
operations.
Status Register 4 (6311-L14) is set by the microcode
during 1/0 operations.
2.)
Program Counter Register
The PC Register (6309-L9, L19, L29, L40, L41) is a sixteen bit
reglster used to indirectly hold the address of data words and the type
Cl0---------------,
"'-'0 ----------~
-
---
C
8US
II" - .
J-or a
HH
,-~
CLOCK
~""""LPh
[lECQDlR
\,01 F TRAP
',<;1''1l'LTTON
(O."lHiI:
""-0
BIa-BI l
I-------.
1-----_
R~G1SnR
'>TA til ...
-~
In"'--~l
- .,. ,us
---
'------+-----------;HULTlPLEXER
,-----,~}{t...., t
k1l.,l
fIGURE 4-2
6311 I/O
CONTROL
DATA
'u'fE.
It~~~ ~
III
L-_ _
{-;~.01
-
~
-JrE-
-
0,-0,
~
I/O
I--+--~-o>{G~~~OR ~
REGI<=:TER
_ _ _ _ _ --0
...---,AB 1-A8S
RE<;ET
-0>{
4-4
-\T I-\T4
~1t ~T~
"OlJRCI!
Y <'Izr
SELECTOR
Pa- Dl
I-~
)
StrBROUTINE
i----.
-00
StAQ(,
RU'ISTI:R
L---.
U&
--00
-
-.
Ie
.
-
'\s-"n
ID -rA
8
t
AU'
PROGRAH
COUN~R
)
~ REG::m I
Rl'GlSH.R
FIGURE 4-3
RfrISTlR
6309 REGISTERS
of read/write operation to be performed.
The PC Register works with
the PC Register Source Selector (6309-L7, LB, L17, LiB, L27, L2B, L3B,
L39).
The Sourre Selector allows the PC Register data to be selected
the Ie Register or the Uemory
from the Auxiliary Reg1sters, the 'e' BUb,
Size Switches.
The output of the PC Register is sent to the Data Memory
Address Register to provide the actual address for the Data Memory.
3.)
Auxiliary PC Registers
The sixteen Auxiliary PC
Re~isters
(6309-L6, L16, L26, L37) are
used to temporarily save and restore the contents of the PC Register.
Transfers or exchanges from the PC Register to an Auxiliary Register
or from an Auxiliary Register to the PC Register may be performed.
TI1ese tr,lnsfers and exchanges are extremely useful when data is being
moved, lJr \.. hen two <:.ets of data are being operated on at the same time.
The Auxiliary Registers also save time and memory by not having to save
and recall the PC Registers in Memory when these type of operations are
)
being performed.
When the PC Register is transferred to an Auxiliary
Register, incrementing or decrementing of the transferred data by 1 or
4-5
2 can also be specifIed.
The Auxiliary Register works in conjunction
with the Program Counter (6309-LS, LIS, LZS, L36).
The Program Counter
contains the data from the PC Register that is transferred to the
Auxiliary Register.
Also,
the incrementing or decrementing mentioned
above is done in the Program Counter.
4.)
Data Memory Address Register
A Data
Me~ry
Address Register (6308-LI3, LIZ, L38 and L39)
receives the PC Register data.
From the sixteen PC Register bits,
eleven Data Memory Address bits, a Memory Select and a Write Enable
are developed.
This register also provides the data selection for
the CL and CH Data Memory Read Registers.
The Data Memory Address is
DATA KDl>RY ADDRlSS
r-_---.~-.II-."
DATA
Ht.'1l'RY
IlDO
AOllhE<;S
IlJ):;ISnR
r--------~ HE>Il'V
SELECT
_ _ REF
WTI:N -\iiEN
4
I
~
~C'
~C5
... HlR
... HERO
... 'lOT
.. Hlr
ll!'llN(.
-- .. m . .
HICL
_ _ . . [lA<;!
, UC
_
.. IUl
.. R£<;n
--.fl
_~2
4-6
r
[
.Jill:,
FIGURE 4-4
6308 MEMORY SELECT
AND SYSTEM TIMING
used to address data words in the 8 bit ROM or to address data words
being read from or written into the RAM.
During RAM Refresh cycles, the
Data Memory Address Register receives the RAM column address from the
)
Refresh Counter (6308-L26, 27).
5.)
File Registers
The eight 4 bit File Registers (63l0-L23 thru L26) are Ilsed as
general purpose registers during arithmetic computations and related
calculator processing.
The File Registers can be either source or object
registers for any of the register transfer microinstructions.
The
File Register write address is derived from the microcode instruction
bits R - R while the two read addresses are derived from R - R and
2
O
6
4
R14 - RIO'
6.)
Instruction Counter Register
TI,e IC Register (6309-L13, L23, L34, L45) is a sixteen bit register
used to hold the address of the current microcode instruction.
Although
this register is not addressable by register instructions, its contents
can be changed by Branch mini instructions.
)
7.)
Subroutine Stack Registers
These sixteen 16 bit registers (6309-LlO, L20, L3l, L42) are used
to hold the contents of the IC Register during Subroutine Branch
instructions.
The!~e
branch addresses.
registers are circular and can hold up lo sixteen
The SSR is addressed by the SSR Address Counter
(6309-L4) which is incremented or decremented by Subroutine Branch
or Subroutine Return, respectively.
The subroutine branches that occur
are at the microprogram level, not the software level.
Because
certain microroutines, called recursive subroutines, can easily
overflow the SSR, an area in Memory known as the Called Subroutine
Stack (CSS) is set up and used in place of the SSR (see Section 4.3.1.4).
8.)
K Input/Output Register
'!1le K Input/Output Register (63ll-L34, L35) is used to receive and
send data to and from I/O devices.
The KH Register contains the four
high order bits and the KL Register contains the four low order bits.
)
4-7
9.)
C Data Memory Read Register
The C Data Memory Read Register (6308 - LIS, L16) is used to receive
data from the MaS Memory or the 8-bit ROM.
The CH Register receives the
four high order data bits and the CL Register receives the four low
order data bits.
The two registers together contain an eight bit data
word.
4.1.3.2
1.)
Memory Structure
Data Memory
The Data Memory is composed of two basic parts:
the MaS Memory
(RAM) to store data and programs, and the 8-bit ROM,
containing math
constants, text
ato~~t
timing constants and console device information.
The MaS Memory can be read from and wri tten into, but the 8 bi t ROM is
hardwired and can only be read from.
The RAM read or write addn'ss or the ROM read address is derived
from the PC Register by the Data Memory Address Register.
In addition,
two modes of RAM data manipulation, set by Status Register 3-3, are
available.
The Horizontal Mode reads/writes two 4-bit data words, at the
same RAM address, sequentially.
The Vertical Mode reads/writes two 4-bit
data words, at the same RAM address, by page.
To further understand
this operation, refer to Figure 4-7 and the following description .
. ,,============~
.Ul
.,
FIGURE 4-5
FIGURE 4-6
6307 4K X 16
6361 8-BIT
L"""
Ror1
DECOOER
4-8
MOS MEMORY
FIGURE 4-7 DATA MEMORY STRUCTURE
)
rl-I '
11
DO,
DD,
A basic 4K byte Memory contains sixteen 2048 x 1 bit RAMs.
Memory is divided into four blocks of four RAMs each.
The
When data is
written into Memory, only four bits from the data bus (C Bus) can be
)
written at a time.
cycles.
To write a complete 8-bit word requires two machine
The first four bits are written into one block of four RAMs
and the second four bits are written into a different block of four
RAMs by changing the wrEN signal.
wrEN is derived from two bits of
the PC Register (AD and A4 ). The Data Memory address during the
two write operations remains unchanged.
The same 8-bit word that was written in Memory in two machine cycles
is read from Memory during one machine cycle.
Consider each address of
the Data Memory to be composed of register pairs consisting of two
registers, with two 4-bit words in each register (refer to Figure 4-8).
All sixteen Data Out (DO IS-DOD) bits are applied to the CL/CH Data
Memory Read Selector (6308-L28 thru L3l) and Register (6308-LlS, L16).
FIGURE 4-8
lEClStER 0 (EVD)
SO
)
REGISTER PAIRS IN DATA MEMORY
aEGISUR I (000)
4-9
The same two PC Register bits that WTEN was derived from are used to
select the data from Memory.
Suppose the data written into block A
of Figure 4-8 is read into the CL Register.
The CH register will receive the
next 4-bit word (B) in the horizontal mode or the corresponding register
4-bit word (B') in the vertical mode.
The two 4-bit words are recpived
at the same time by the CH/CL Registers.
Any sequpntial (hori7ontal)
or (vertical) page read can be performed without changing the Data
Memory Address.
This 4-bit write/8-bit read scheme of addressing
provides the convenience of 4-bit addressing and the speed of 8-bit
reads.
2.)
Control Memory
The Instruction ROM (6325 Memory) contains up to 64k of 20-bit words
that make up the BASIC Interpreter, or control memory.
Each instruction
of the microprogram contained in the Instruction Memory is read from
the ROM at the address specified by the IC Register.
The IC Register
r:--
l
-'
LOW
ORDER
PDS
FIGURE 4-9
UI~lAl
1-
.1 TTL TO
1I.~1Bl--·
JC ...
~lcl--.!
HOS
-l
6325 ROM
512 X 10 BITS
I
"-t:~J
ADDRfSS
-=---=-----------..
10.. IC.
ID2 ,
~
RDM
SElf CT
l_D,'--
-L
PIN
4-10
:~:~
f
PATCH ADDR!SS D!COD'!R
Lo
Al
~
lC:z-ID:z
[;JO" 1 10,
DPTE"! r=:t~OH
COOl'
--.
DISABLE
"O-A,
I
leI
CHIP
St.LI:::CT
PR()(,RAMI'W!LE
RFAr) ONLY
ME!'lORY
---
-\
J.
I
OUTPUT UTCH
!
Dl'
FIGURE 4-10 6547 SUPERPATCH BOARD
is incremented sequentially every machine cycle but can be changed by
Branch and Return microinstructions.
In some models, a 'superpatch' is
used in conjunction with the Instruction ROM to correct microinstructions
that were written incorrectly.
The superpatch decodes the address of
an incorrect instruction being accessed, disables the Instruction ROM
and provides the correct microinstruction for the CPU.
4.1.3.3
Supporting Hardware
Arithme tic Logic Unit
1. )
The ALU (63l0-L20) performs arithmetic or logic functions as
specified by the decoded microinstruction at the function select word
input.
The 4-bit A and B data word inputs are derived from the Band
A Buses respectively and operated on by the ALU.
F output is applied to the C Bus (Data
BU~
The resultant 4-bit
for use in the CPU.
Arithmetic
operations with carry may also be performed by the ALU by the use of
)
additional circuitry (63l0-L9, L46).
sensed by Status Register 1.
4-11
When a carry is generated, it is
PIll
.---+----------1 RlCIStD.
BI - 1l1 1
S
,
Ao-Alt-A-;~~l
8 BUS
~:T~"----j-----+l~
A BUS
SELECTOR.
.,--,-----------+----.j
rutlCnO~l
1.
HI\I
INSTRUCTIONS
--
ALU
CARRY
_ _ _ _~_JA-'
FIGURE 4-11
2.)
6310 ALU BOARD
Micro Instruction Decoder
The Micro Instruction Decoder (63l0-L33, L34) is used to decode
the control memory instruction word and determine if it is a Register
Instruction, a Mini Instruction or Branch Instruction.
Instruction is specified, an additional decoder,
If a Mini
the Mini Instruction
Decoder (63l0-Ll, L4l) decodes register transfers and exchanges,
subroutine' returns and T/0 control instructions.
instructions and L34 dpcodes the Branch and Mini
3.)
L33 decodes the Register
rnstruction.
System Timing
The
epe
timing is derived from a 10 MHz Oscillator (630B-L9) and
four shift registers (630B-L19, L20, L23, L32) phase shifted from each
other.
clocks,
These shift register outputs are gated to
devel~p
the system
resulting in sixteen clock times, each 100 nanoseconds apart.
4-12
A system clock is therefore generated once every sixteen clock times,
or 1.6 microseconds.
This is the machine cycle period.
See Figures
4-12 and 4-13.
Another part of the system timing is the Machine Cycle Counter
(630S-L6, L17) and Decoder (6308-Ll) which interrupts the normal CPU
machine cycle to allow the Data Memory to be refreshed.
The clocks
and their functions in the CPU are:
MERO:
Used to clock the SSR Address Counter, all output strobes
MER:
Provides clocks for the Program Counter, Status Registers,
and the RAM Select and Write Enable Decoders.
File Registers and IC Register.
MOT:
Provides a clock pulse to increment or decrement the
Program Counter by one count.
MTF:
Provides two clock pulses to increment or decrement
UDC:
Loads the PC Register.
MXS:
Allows clocks to be generated to enable the Auxiliary Registers
the Program Counter by two counts.
)
and increment or decrement the PC Register.
RESET: Disables the Instruction ROM and clocks a new address to
the Data Memory.
CS:
Used in conjunction with All to select the upper or lower
MHL:
Provides the clock for the CH and CL Data Registers.
MNT:
Clears the Write Enable and Memory Select circuits.
half of an SK byte Data Memory.
Also
provides the clock to generate DIN.
DIN:
Provides a clock for the ROM Output Latch to generate a
ROM Instruction and also disables the RAM output.
DAST:
Provides the Data Memory Data Output clock.
CK:
Not used.
REF:
Enables the Memory clocks to generate a refresh cycle.
REL:
Clocks the Wri te Enable to the RAMs.
01:
Generates RAM Read Clock and enables the ROM to read a
02:
Generates RAM Write Clock.
new address from the Instruction Counter.
)
4-13
FIGURE 4-12 MODEL 2200 AlBIC CPU TIMING
..
1IIY
~r--2
3
f-t-F
F l= 1= J- ~ JI - l--
'-L-
iii
J-fIJI-ff-
;-1-
J-
f-
t=
'-
k-~~~~-"''''<AC"",m,,--J
1 Horizontal division
'0
-
t
1
t
tj!.
5
t
6
7
'.
9
t
10
11
12
13
"
"
0
c-
F= r- -
t- -
-
t
I
100 ns.
=
-
I
- -- -
I--
L-
f-- -
'L-
II
f-t-
tI
FIGURE 4-13 MODEL 2200 SIT CPU TIMING
4-14
l'-
4.)
Register Clock Decoder
The Register Clock Decoder (631l-L2l, L22) enables the clocks for
the PC Register, Status Registers and the K Register to be generated as
specified by the microinstruction.
5.)
B Bus Multiplexer/Selectors
The microinstruction can select the B Bus data from any register
in the CPU.
The B Bus Multiplexer (63ll-L26 thru L29) provides B Bus
input from the four Status Registers, the K Register or the PC Register
bits All - A4 ·
In addition to the B Bus Multiplexer, there are three other levels
of B Bus selection.
B Bus Selector #1 (6310-L35 thru L38) provides
inputs to B Bus Selector #2 (63l0-L27, L39).
Selector #1 output can
be obtained from PC Register bits A
- A
or A - A ' the CH or CL
O
15
3
12
Registers, or a hardwired 'dummy' register. Selector #2 can output
the data from Selector #1, the B Bus Multiplexer or the File Registers.
The output of Selector #2 is applied to B Bus Selector #3 (63l0-L17).
Depending on the type of ALU operation to be performed, Selector #3
outputs either the data from Selector #2 or the nine's complement of
that data to the ALU A Word input.
The addresses for the B Bus
Multiplexer and Selectors #1 and #2 are derived from ROM Instruction
bits R
and R
thru RIO'
19
15
6.)
A Bus Selector
The A Bus Selector (6310-12, L3) provides the ALU with the B
Word input.
The output may be selected from the File Registers, the
CH or CL Registers or ROM bits R - R • The address for the A Bus
7
4
Selector is derived from ROM Instruction bits R thru R •
7
4
4.1.3.4
Input/Output Structure
The 2200 uses an eight bit parallel Input/Output data path to
interface many type of devices.
)
The K Register, discussed in paragraph
4.1.3.1, is used for this data I/O path.
4-15
In addition to data, each device requires a unique eight bit address.
The address is also derived from the K Register and loaded into the AB
Latch (63ll-L15, L25) when specified by a CIO instruction and R •
7
To tell the I/O device when to input data to or receive data from
the CPU, three strobes are used, generated by the I/O Strobe Generator
(6311-11, 110, Lll).
The Address Bus Strobe (ABS) strobes the eight bit device address
to the I/O devices.
Since each I/O device has a different address, only
one device may be enabled at one time.
The Output Bus Strobe (OBS) is
a 5 usec data output strobe that sends the data in the K Register to
the device which is currently enabled.
The Control Bus Strobe (CBS)
is a 5 usec output strobe that requests the currently enabled device
to send an IBS to the CPU.
4.2
The Input Bus Strobe is sensed by Status
4.1.~.1).
Register 1 (paragraph
GENERAL INSTRUCTION SET DESCRIPTION
The 2200 Instruction set provides a general form for writing the
microinstructions used in the CPU.
There are three instruction groups:
Register Instructions, which
allow the arithmetic and logical ALU operations to be performed on data
contained in various registers; Branch Instructions, which test for
certain register conditions and if met, branch the microprogram to the
address specified; and Mini Instructions, which control I/O operations,
subroutine returns, and register transfers and exchanges.
The Instruction Set is shown in Table 4-1.
The Op Codes for the
various instructions are always the same for each instruction, but the
A and B Bus Sources,
the C Bus destination, memory operation, branch
addresses, etc. are the variables in the instruction.
Although there
are a limited number of instruction types, an almost unlimited number
of different instructions can be written simply by changing the
instruction variables.
versitile.
This feature makes the instruction set very
By writing the instruction variables using the rules shown
4-16
in Tables 4-2 through 4-7, each instruction can be customized to
perform a specific operation with data from the CPU hardware.
For
example, suppose an instruction is required to OR the contents of
Status Register 4 with File Register 5 and put the results in the PC3
Register and also in Memory with a Write 1.
OR is 00000.
First, the Op Code for an
Status Register 4 is selected on the B Bus with the X
Bit ON and B Field as 1001.
The Write 1 is 10.
File Register 5 is
selected on the A Bus by specifying the A Field as 0100 (Register 1 is
0000, Register 2 is 0001, etc.).
Register is 1011.
The C Bus destination of the PC3
By following the format in Table 4-1, the complete
instruction is written as 00000110011001001011.
Although the hardware
requires a binary instruction to perform the operation, the instruction
is normally written in hexadecimal as '0664B'.
In a similar manner,
the complete microprogram is written to produce the desired results
and then is stored in a 'hardwired' Instruction Memory.
)
)
4-17
RQMINSTRUCTIONBITS
INSTRUCTlOHllESIG'iATORS
OpCode
X
SBusSource
Memory
ABusSource
CBusOest.
REGlSTERINSTRLlCTIONS
OR(OR)
0
0
0
•
0
X'
B
B
B
8
'Z
'1
Exclus1veOR(xOR)
0
0
0
0
1
X
B
8
8
8
'Z
'1
ANO(ANO)
0
0
0
"Z '1 A
"Z '1 A
A
C
C
B1naryAdd(A)
0
0
1
0
0
X
8
8
8
8
A
'Z '1
Binary Add W/tarry(AC)
0
0
1
0
1
X
8
8
8
8
"Z '1
A
A
A
Dec11!1111Add(DA)
0
0
1
1
0
X
8
8
8
'Z
'1
A
A
A
A
,
,
,
, ,
,,
,
OeclmalAddw/caITY(OAC)
0
0
1
1
1
X
8
8
8
'Z '1
A
A
A
A
C
C
ORlllVl'Iedtate(ORI)
0
1
0
0
0
X
8
8
8
8
'1
1
C
C
Excluslve 011. IlllIledlate(XOIH)
0
1
0
0
1
X
B
8
8
8
"
"1
1
Andllllllediate(ANOl)
0
1
0
1
0
X
B
8
8
8
"1
1
I
1
1
Binary Add Inmedhte(AI)
0
1
1
0
0
X
8
8
8
8
"1
1
1
1
I
DecimalSubtractw/carry(DSC)
1
0
X
,
8
8
8
1
1
X
8
8
8
8
A
A
A
C
C
A
A
A
A
C
Inned. Operand
B1naryAddw/clnrned(ACI}
0
1
1
0
1
X
B
8
8
8
DectlnalAdd IIIIIIl!diate(DAl)
0
1
1
1
0
X
8
8
8
8
Decimal Add w/c Inrned(OACI)
0
1
1
1
1
X
8
B
8
OpCode
BBusSource
8
",
",
",
"
",
",
1
1
1
1
"1
1
1
I
1
"1
1
1
1
1
1
1
1
1
'1
A Bus Source
IC2Address
, ,
,
C
C
C
C
C
C
,
,,
C
, ,
, ,
, ,
,,
,
,
C
C
C
C
C
C
C
C
, ,
, , ,
,
,
C
C
C
C
ICIAddress
BIlAItCHtll.'i.TRUClIOMS
Branch 1f - to Register(BER)
1
0
0
0
B
B
B
B
Y
Y
V
Y
A
A
A
A
Y
V
V
V
Branch If ~ to Register(BHR)
1
0
0
I
B
B
B
B
V
Y
Y
Y
A
A
A
A
V
V
Y
Y
V
Y
Y
Y
Y
Y
Y
0
0
IC4Address
IC3Address
SubrouttneBranch(SB)
1
0
lOY
Y
Y
V
Y
Y
Y
Y
Y
Y
Y
V
Y
uncond1t1onalBranch{B)
1
0
1
1
Y
V
Y
Y
Y
V
Y
Y
Y
Y
Y
Y
Branch 1f True(BT)
1
1
0
o
Branch 1f False{Bf)
1
1
0
I
BranchH-toHask(BEQ)
I
1
V
-----BBusSource
~
Branch H
to Hasl::(BNE)
B
B
B
B
Y
Y
Y
Y
H
H
V
Y
B
B
B
B
Y
Y
V
V
H
H
y
y
lOB
B
B
B
Y
Y
H
H
H
lIB
B
B
B
Y
Y
Y
Y
...
H
H
Y
V
OpCodel
OpCode2
Memory SiLl
H
Address/Oata
HINIINSTRUCTIONS
o
Controll/O(CIO)
1
0
1
1
0
0
0
0
0
",
'1
:.lr:..._o_-" °
0
A Bus Source
o
o
SubroutIne Return{SR)
TransferPCtoIC(TPl)
1
0
I
1
0
0
0
0
1
1
0
1
1
0
0
1
0
1
o
I
0
I
1
0
0
0
1
0
I)
1
Ii
1
1
0
0
1
0
I
1
0
0
0
1
1
0
1
1
0
0
0
1
I
0
I
1
0
0
1
I
0
1
1
0
0
1
Transfer IC to PC(T1P)
Tra1\~fer He<T()ry ,He to 1>C(T1'.p)
TranJfer PC to Aux(TP)
o
o
o
o
1
",
",
A
'1
"1
A
"1
A
"2
"1
A
'Z
'1
A
"1
A
"
A
A
Aux Reglster
TranslerAux
topC(TA)
[xchdngt! PC and
"u~ (xP)
Tran~fer
~,
pr to
Transfr~ p~
"
Trandt!r ~r to
TranS'",r PL tl
Exchange PC and
l(TP+ll
~''''
(It[
,
1
'(TP+2)
0
1
l(TP-2)
0
1
AU~.+
J
0
1
",
0
" "1
", "
",
",
1
0
1
:1
A
"1
A
"
A
" I'
1J
0
1
0
I
0
I
1
0
1
1
10M
Exchange PC and Aux.·2(lP-2)
0
1
0
I
1
0
1
1
_1~H2MIA
v
•
M?
2
R
R
A
R
R
A
R
R
"'
M•• A
HI
A
A
2200 MICROCODE INSTRUCTION SET
4-18
A
A
Exchange PC and Aux.+2(XP+2)
TABLE 4-1
------; I
"Z H;! A
0
XP+I)
Exchange PC and Aux.-l(XP-l)
0
R
R
Register Source
Auxiliary Register and
All Other
TIP Instructions
Instructions
(l000 through 0111 One of eight File Registers
One of Eight File Registers
1000
CII Data Register
CH Data Register
iDOL
Illegal
CH Data Register; PC decre-
1010
Illegal
ment
CH Data Register; PC increment
1011
Illegal
1100
CL Data Register
CL Data Register
!l01
Illegal
CL Data Register; PC decre-
1110
Illegal
CL Data Register; PC increment
Ull
Illegal
Dummy Register; PC increment
Dummy Register; PC decrement
ment
1---------+------------..1----------------1
I Field (R7- Rh
1------0000
Immediate Operand
The immediate operand specified is used as the A Bus data
1111
TABLE 4-2
A BUS SOURCE SELECTION
)
4-19
B Field (I{, rl{lO)
Reo:ister Source
X RH (1{1L.)
1-----------
=0
X
0000 through 0111 One of eii(ht File Registers
ait (R14)
=
1000
KH I/O Register
Status
1001
KL I/O Register
Status Register 4
Register 3
1010
Status Register 1
PC2
1011
Status Register 2
PC3
1100
Pel
PC4
1101
CH Data Register
CH Data Register
1110
CL Data Register
CL Data Register
1111
Dummy
Dummy
TABLE 4-3
r Fif'ld
(R
B BIIS DESTINATIOH SELECTION
)
3-R O
Register Destination
X Bit (Rl4)
=0
0000 through 0111 One of eight File Registers
X Bit (U4)
I/O Register
1001
,zL
I/O Register
1010
Status Register 1
PC2
1011
Status Register 2
PC3
1100
PCl
PC4
1101
Illegal
Ulegal
1110
Illegal
Illegal
1111
Dummy
Dummy
TABLE 4-4
=1
One of eight File Registers
!{II
1000
1
One of eight File Registers
Status Register 3
Status Register 4
C BUS DESTINATION SELECTION
4-20
)
--
-----..,--------------------------..,
Register Source/Destination
0000
~
1111
fABLE 4-5
FIPld (R 9 ,R S )
M
M
2
M
)
Data Memory Operation
l
a
0
AUXILIARY REGISTER SELECTION
No read or write
0
1
Read 8 bits from Data Memory
1
a
Wr1te 1-
1
1
Wrlte 2 ; write 4 bits into Data Memory
write 4 bits into Data Memory
[ABU. 4-6
D Fleld R6 - R
O
~
)
- -
DATA MEMORY
S BIt (R ) =
7
OPERATION~
a
S Bit (R ) = 1
7
- - - - - -f----- - - - - - - - - - -
f-
0000000
No Operation
0010000
Generate CBS
Illegal
0100000
Generate OBS
Illegal
Generate ABS
Illegal
1000000
'---
-
~
---
-
lARLE 4-7
Load Address Bus Latches
with data from K register
CONTROL I/O OPERATIONS
4-21
4.3
CPU FIRMWARE DESCRIPTION
As rrentioned in section 4.1,
the BASIC Interpreter contained in
Instruction ROM is the important link between the user's BASIC program
and the machine instructions.
The firmware not only allows the user
to perform calculations and data manipulation through the software,
but also sets up and keeps track of the various pointers, flags, buffers,
tables and stacks necessary for program execution.
The pointers,
flags, buffers, tables and stacks are stored in a
predetermined area of the Data Memory.
The Data Memory is mainly used
for storing the user's program and data, except for this small portion
lIr;en for "housekeeping".
rigure 4-1/... denicts the D:::lta Memorv al1n('Atinnc;
of these areas used by the firmware.
0000
r-----------......,
Ct>neral Scratch "rea
(J2 byte!')
0040
Point... r ... Counts, Fl.. ""s
(34 byte.. )
00"
f-----------___1
01::8
f------------___1
Device Tdblt>
(~S bytes)
Disk "".;Irk. "r.. a
(11 bytes)
OUF f-~---------___1
Operator Stilek (OS)
(49bytt>s)
01"0
f------------___1
H.1th ScratCh Area
(48hytt's}
0200
----------'----'------1
DU1lllf,
Varla!>le Ta~lf'
l50bytes)
FIGURE 4-14
DATA MEMORY
ALLOCATION
026~
I/O Buf[t'(
(256 bitO'S)
(floots at end of text I
---------- - - - Called Subroutine Stack lC::'S)
j
ValuE' <;t",k (V<;)
(float,> abuvp '1y~hol tdllle]
- =-~~~h~l-~~J~~\iJ--1\ hri(~r
Symhol
u<"<;cription of <;ome or these .1re.'lS is as follows:
the
I'ahlp (VSV) contains the user defined variables and their values;
the V<lIIlP SLH k (VS)
is used to temporarily hold values during expression
.1I1alysis and suhroutine information; the Operator Stack (OS) holds the
operators during expression evaluation and i()R!('nSUB information: the
Dummy Variable Table contains information for user defined functions
(DEFFN).
The use of these tables is further
para~raphs.
4-22
e~plained
in subsequent
4.1.1
CPU PROCESSINr;
When power is applied to the CPU, Master Initialization occllrs.
Master Initialization sets a 'trap' address in thp control memory which
is the start of the Master Initialization microprogram.
During this
microprogram much of the CPU hardware is initialized and the various
tables and stacks in the RAM are initialized or set to specific conditions.
When Master Initialization is complete, the CPU enters the Text
Entry Phase (during normal operation, the 2200 System is in one of
three phases:
text entry, variable and line number resolution, or
program execution).
4.3.1.1
Text Entry Phase
Text entry phase is identified by a colon (or
being displayed.
'?' for INPUT)
The system then waits for the user to input text.
Input characters are placed into the RAM I/O buffer (at end of text area)
until an execute (CR) is encountered.
The text line is then syntactically
analyzed, syntax errors causing an errOr message to be displayed.
If
there are no syntax errors and the text line is a system command, the
command is executed; if it is a statement without a line number, it is
executed as a one-line user program (immediate execution).
paragraph 4.3.1.4 for a description of Execution Phase.
Refer to
If it is a
statement with a line number, it is threaded into the users present text
program.
That is, two bytes are reserved before each text line in the
program as a pointer (thread) to the next highest program text line.
Hence, when a new text line is added, the next lowest text line is found
and its thread is set to point to the new line.
If the line number of
the new text line is equal to the line number of a previously entered
statement, the new statement is threaded into the program in place of
the previous statement (if the over-riding text line consists solely
of a line number and a carriage return, the over-ridden text line is
removed and the new line is not threaded in - this is line deletion).
Note that lines with syntax errors are also threaded into the users
program.
4.3.1.2
Variable and Line Number Resolution Phase
)
The Resolution phase is entered just prior to the execution phase.
The Resolution phase is triggered by a RUN command.
4-23
Its function is
to assemble the variable symbol table, allocate value areas in RAM for
user variables,
and assure that referenced user line numbers exist.
consists of a complete scan of the users program.
is error free,
It
If the entire pass
then the resolution phase transfers control to the
execution phase directly.
If an error is detected, an error message is
displayed, execution is inhibited, and control returns to the text entry
phase.
The resolution phase scan verifies the presence of valid line numbers
and user defined functions that have been referenced, and constructs
a variable symbol/value table.
defined function is encountered,
As each referenced line number or user
the body of the user text is scanned
for a match with the current element.
As each referenced variable is
encountered, the symbol table is scanned for a match with the current
variable name.
continues.
If a match is found, then the scan of the program
If no match is found, then the variable is entered into the
value table and is set equal to zero (numerics) or is assigned a value
of one blank character (alphanumerics).
The symbol table is assembled
from high order address to low order address, starting with the highest
RAM address (see Figure 4-14).
When a variable is defined by a user, it is allocated space in the
symbol table during resolution phase.
given a value of 0;
Numeric variables are initially
alphanumeric variables are given a value of one
blank character (for a l6-character default length, 16 blanks are
assigned, but the trailing blanks are not normally considered to be
part of the value).
Alphanumeric variable values have a default
maximum length of 16 characters which may be ridden over by the user
with a DIM statement (the user may set the maximum variable length
from 1 to 64 charac ters) .
Each symbol table entry consists of two parts:
(name, atom,
the symbol prefix
dimensions, thread to next symbol, etc.) and the symbol
data (i.e., variable values).
Figure 4--15 shows the Symb;)l TabLe Entry Format.
The Symbol Atom
is used to specify numeric or alphanumeric variables and scalar, vector,
or array information.
4-24
-
Uerter
lIl",lt or 1"1"
L-~-Atom
friilim
-TllTf'.d 01
(Ia~l ent ry
)
r.~ ~t
~ ... n
t.. ,j
I" t .. LoJ.. II '" t h, .... d 00)
DI.M 11
Where XX
=
and y
=
DIH 12
(arfll)9 only; for vectors DIM '2"'1)
Hat. String Lellgth
(alph8nu~rlc
-
00 for scalar
01 for vector
11 fOl array
0 for numeric:.
1 for alphanume ric
\artables only)
Varl,,"l.. V.. l'le
(
I I I
I I I I
lExP. Low ....Exp. HighJLMantissa
(13 Digits)
(EIOloIMI
FIGURE 4-15
SYMBOL TABLE ENTRY FORMAT
Where E
and M
o
o
J
for positive exponent;
1 for negative expo
for positive mantissa;
1 for neg. mantissa
The thread of next symbol is a pointer to the next symbol in the
symbol table used to speed up searching for a particular variable.
The
val ues of arrays are stored row by row from left to righ to
Numeric values are normalized (leading zeroes removed) and stored
in floating point format.
)
The decimal point is assumed to be after
the first digit (Scientific notation).
Alphanumeric values are character strings which are left justified
and filled in with blanks on the right up to the maximum length of the
value.
The end of the value is assumed to be the last nonblank character
(except when the value is all blanks, in which case, the value is assumed
to be one blank).
Hence, trailing blanks are not part of alphanumeric
values.
4.3.1.3
Text Atomizing
Text Words (Verbs,
Commands, Function Names, etc.)
The BASIC verbs, commands, and function names in text are replaced by
text atoms.
A text atom is an 8-bi t code with the 8-bit on; the lower
7 bits specify the position of the basic word entry in the text atom
table in the CPU's 8-bit ROM.
)
Striking a verb, command, or function
key on the keyboard will cause the direct entry of the text atom into
text.
Entering a verb, command, or function by individual characters
will result in the word being atomized at a later time.
4-25
f------llIW~"'_'--_j­
EDtrv 2
Ilnt
Address
Type
o1 2 •
4.
5 8 9 •
C -
Verb
arc: trig function
word not in list
cOIIIID8nd
flDlctlan
function
logical operator
select parameteT
FIGURE 4-16
TEXT ATOM TABLE
The Text Atom table occupies 96 entries in the 8-bit ROM (see
Figure 4-16).
text atom.
Each entry consists of a l6-bit pointer for every possible
When an atom is requested, two bytes of 8-bit ROM are read
from the Text Atom table at the address of the entry number specified
by the atom.
The sixteen bits read from the Text Atom table are used to specify
the type of BASIC word the atom represents and the address of the word
in the appropriate Atom List.
The 2200 microprogram provides for up
to eight such word lists which can be referenced by the Text Atom Table.
The 2200 currently uses seven word lists.
Text Word List:
The Atom List specified by the Text Atom Table is scanned until a
match of the Text Atom and the Atom List entry is found.
then read from the B-bit ROM.
The word is
The number of byte locations occupied
in the B-bit ROM depends on the length of the BASIC word.
The Text Word
List structure is shown in Figure 4_17.
~~~~s of
BASIC-word
rou~
NUlllber of Characters in word
Character 1
P.utry 1
Character 2
~
Character
FIGURE 4-17
TEXT WORD LI ST
STRUCTURE
~~
ATO.
Address of BASIC word rout.ine
~umber
of Characters in word
f-------
----1
Charact.".,,--o".-,
Character 2
j
Character n
ATOM
4-26
Entry 2
Statement Numbers:
Statement numbers and references to statement numbers are stored
)
in packed decimal format after a statement number atom.
The statement
number atom occupies 1 byte and the decimal number two bytes.
With
this structure, the maximum statement number length is 4 digits.
Statement number: (0001 through 9999)
4.1.1.4
Execution Phase
Execution phase is entered only after a successful resolution phase.
During execution phase, each statement is executed as it is scanned.
To
execute a BASIC statement, the text is scanned and compared with the
BASIC atoms stored in the 8 Bit ROM.
When a match is found, the specific
microroutine to process the BASIC Statement is executed.
The address
of the correct microroutine for each BASIC statement is found in the
)
Atom Table information that corresponds to the BASIC text word.
After
execution of the statement, scanning continues.
Three pushdown stacks are now active:
the called subroutine stack
(CSS) , the value stack (VS), and the operator stack (OS).
The CSS is
used principally to store subroutine return addresses for recursive
subroutines.
The value stack is used for operand storage during expression
evaluation and for such purposes as storing loop and subroutine information.
The
as stores operator atoms for expression analysis as well as atoms
for looping and subroutines, etc.
4.3.1.5
Recursion
The 2200 CPU has a l6-level, circular subroutine return stack.
Therefore, for recursive subroutines, which could easily overflow this
stack, a special Called Subroutine Stack (CSS) is set up in RAM (by
)
recursion we mean,
for example, that an expression may contain within
4-27
itself smaller elements which are themselves expressions).
Thus, when
the syntax scan encounters an overall expression, it will call the
Expression Processor, and if a smaller independent expression is found
within this overall eKpression, the Expression Processor is again called
in to evaluate the smaller expression.
When evaluation of the smaller
expression is complete, the Expression Processor is again called to
complete evaluation of the overall expression.
The Called Subroutine Stack is a "pushdown" stack, operating on
a last-in/first-out (LIFO) basis.
Before entry into a recursive routine,
the return address is stored in the
~s
esse
Exit from the recursive routine
made by a branch which removes the return address from the CSS and
branches to the point specified.
Examples of 2200 microroutines which are
recursive are:
VAR
- process a numeric variable
EXPR -
expression processor
TERM - evaluate a term
FUNC - process a function
These recursive subroutines are utilized by the 2200 and are not
directly user accessible.
4.3.1.6
Expression Evaluation
Expressions are evaluated according to the following priorities:
Priority 4 (highest) ••. ( ) (Any expression within parentheses l )
Priority 3
Priority 2
t (Exponentiation)
*, / (Multiplication, Division)
Priority 1 (lowest) •• +, - (Addition, Subtraction)
lSince expressions may contain nested parentheses, the innermost
parenthetic expression is evaluated first, according to the priorities
established above.
In similar manner, remaining parenthetic expressions
are sequentially evaluated, until the outermost parenthetic expression
has been evaluated.
4-28
EXAMPLE:
.-}NESTED" PARENTHETIC
EXPRESSIONS
~
~)
X
+
* Z
~
Y
(A t B
"-v--'
+
C
+
*
~I+ R)
B»
1 (7i"
4
L
{5
'l__ --(6
-r;,_------Jf
NOTE:
Numbers in circles indicate sequence of execution.
An operand is any numeric value, specified by a number, variable,
or function.
Operators (+, -,
to be processed in expressions.
*, I,
t)
indicate how the operands are
Operands are stored in the Value Stack
(VS) of Data Memory; operators are stored in the Operation Stack (OS)
of Data Memory (refer to Figure 4-14).
Expression evaluation is performed by certain microcode routines.
When an expression is evaluated, the operand is stored in the Value Stack
(VS); as each operator (+, -, *, I, t) is encountered, it is compared
with the last operator already entered into the Operator Stack.
If the
last operator in OS is of higher execution priority than the current
operator, the last OS operator is removed, and the indicated operation
)
is performed on the last two VS entries.
two VS entries.
4-29
The result replaces the last
Operator Stack execution continues until an operator with a lower
execution priority than the current operator is found.
The current
operation is carried out, and the evaluation scan of the expression
for execution of lower priority operators is continued until the overall
expression is evaluated.
An example of this operation is shown in
Figure 4-18.
Note that operands with leading minus signs cause the following:
a)
Store zero (0) in VS, following operand (step 1 below).
b)
Store "negative" operator (-) in OS (step 2 below).
c)
Store scalar operand value in VS (step 3 below).
d)
Perform a higher-priority operation (should one be present)
on the two operands in VS preceeding the zero stored (steps
4-6 below).
e)
Replace operands (used in step d) with results of step (d).
f)
Perform next OS operation (-) on last two operand values in
VS (step 7 below).
1)
phceO 10VS
2)
phce -inOS
~l
ph"e' in OS
$)
phceSi"VS
6}
perfor",.opcrat!onon4and
5,thenreplacetheopetaud"
viththeresult
FIGURE 4-18 EXPRESSION EVALUATION OF AN OPERAND WITH A
LEADING MINUS SIGN
4-30
4.3.1.7
Looping (FOR/NEXT)
A BASIC program loop is initiated by a FOR statement and terminated
by a NEXT statement.
)
When the FOR statement is encountered, the following
steps occur:
1)
The scalar variable (index variable) is set equal to the initial
value of the expression.
10 FOR Y = 1
EX:
20 X
2)
=
m 10
Y
The symbol table address of the index variable is placed in the
value stack:
Symbol table address of Y to VS.
3)
The address of the statement following the FOR statement is
placed into the VS:
Address of line #20 to VS.
4)
The values of the limit and step expressions are placed into
the VS:
LIMIT
10
STEP
1, unless otherwise specified by a
STEP statement.
5)
A 'FOR' atom is placed into the OS:
FOR atom to OS
)
The 20 bytes of information in the VS are known as 'FOR group'.
The
FOR group is not touched until the companion NEXT statement is executed
(or the FeR group is flushed; see SUBROUTINES (GOSUB/RETURN».
When the NEXT statement is encountered, the system scans the VS
(which now nnly contains FOR groups and GOSUB return addresses) to find
the FOR group to which the current NEXT applies.
group is found,
When the correct FOR
the index variable is retrieved and its value is in-
cremented by the step value.
If the new index value is greater than
or equal to the limit value, the current FOR group is removed from the
VS and processing procedes in line number order.
is
lPHS
If the index value
than the limit, processing continues at the address stored in
tIll' FOR group.
Scannln~
)
is empty,
for the FOR group in the VS proceeds only until the stack
or a subroutine return address is found at which time an
message is output.
e~ror
Hence, a GOSUB or COTO statement after a FOR state-
ment and before a NEXT statement is illegal if there is no companion
RETURN statement before the NEXT statement.
4~3l
4.3.1.8
Subroutines (CO:;Ull/IU':rUI(N)
A svbroutine call is made when a GOSUB statement is executed, and
a return from the subroutine is made when a RETURN statement is executed.
\..Jhen ;] COSUH . . . t.llPffil'lll
is l'ncountprpd,
til('
rnllowinl~ sleps
1)
TIlt' ,I<JJn'ss of L11l' slatemt'nl immpJialely foJ
2)
A subroutine atom is placed into the OS.
illwjn~
are tilkpn:
tl,c COSUB
statement is put into the VS.
When a RETURN st<ltement is encountered, the value stack is scanned
for a subroutine return address.
Any incompleted FOR groups encountered
are flushed (removed) from the VS.
If there are no subroutine return
addresses in the VS, an error message is issued.
When a return address
is found, processing proceeds at the specified statement.
4.3.1.9
Device Selection
Each 2200 device has a two-digit Hex address by which the device
may be referenced or selected.
associated with each device.
A one hex-digit device type is also
The device type, device address, and
carriage length where applicable are stored in a Device Table (Data
Memory area) which has entries for the I/O devices.
The SELECT verb is used to select devices for I/O operations.
Whenever MASTER INITIALIZATION occurs, the primary 2200 console devices
are automatically selected for all I/O operations.
device information is stored in the 8-bit ROM.
The primary console
Primary console device
addresses (default addresses) are as follows:
Device
Type
Device
Address
Pri,ptary Console Input Device : Keyboard
0
01
Primary Console output Device : CRT
0
05
Primary Tape Device
Primary Cassette
1
OA
Primary Disk Device
Primary Disk
3
10
Primary Plot Device
Primary Plotter
4
13
4-32
Carriage
Length
64
DEVICE TYPES:
o
parallel ASCII with CR/LF
)
serial 2200 cassette
parallel ASCII with CR but no LF
3
disk
4
parallel ASCII with no carriage return generated at end of line
Program and command entry is always input from the console input
device.
The console devices may be changed from the primary devices by
using the console selection overrides:
CI (console input), CO (console
output), TAPE (tape), DISK (disk), PLOT (plotter) selection parameters.
The optional 'length' field specifies the carriage length of the selected
device.
Whenever a CLEAR command (with no parameters) is executed,
the current console devices are selected for all I/O operations.
The program selection overrides are used to control I/O during the
execution of a user program.
The PRINT select parameter specifies the
output device to be used during program execution; the INPUT select
parameter selects the input device.
ERROR, END PROGRAM, and STOP messages
are always written on the console output device.
The command selection override SELECT LIST is used to specify
the device to be listed on.
The console, program, and command selection overrides are maintained
until:
1)
They are changed by another SELECT verb.
2)
They are reset to the primary console devices by a MASTER INITIALIZATION.
3)
They are reset to the console devices hv the execution of a CLEAR
command (with no parameters).
I nUlled ic1te
Device Specification:
"or r /0 operations involving the reading or writing of program or
)
data on cassette, disk, etc., the user may specify the device type and
device address preceded by a slash (/) in the BASIC I/O statement.
f.xample:
DATASAVE/lOB, X, Y, Z
4-33
1'1 ll' IJtlluIH'r:.:
For I/O operaLlons involving reading or writing of program or data
on
cas~et te
disk, etc., six file numbers are defined (Ill, #2, 113, #4,
't
#0 i~ ,uso legal for disk files, and is the default file
115, 116).
number assignpd to the disk.
These can be assigned device type and addresses just as BASIC I/O
verbs are.
Therefore, in addition to the normal device selection I/O
operations can be done via file numbers.
Example:
SELECT #3, lOB
DATASAVE #3, X, Y, Z
CLEAR and MASTLR INITIALIZATION will clear all file number assignments.
Reference to an unassigned file number wIll cause an error output.
The following BASIC statements can use file numbers and immediate
device specification:
LOAD, SAVE, DATALOAD, DATASAVE, REWIND, BACKSPACE,
DATARESAVE, DISK statements, and $GIO, $IF ON.
4.3.1.10
Output Device Switching
When switching from one output device to another, the problem exists
of keeping track of the count of characters in a line for the various
devices, since only one line character count is maintained within the
CPU.
To handle this problem, a PRINT Line Character Count and PRINT
Flag exist.
At the beginning of the PRINT and PRINTUSING routines the PRINT
line count is restored (i.e., the current line character count is set
equal to Print Line Character Count unless the 'cannot restore PRINT
line character count' bit is set in the PRINT Flag); at the end of PRINT
and PRINTUSING, the current line count is saved by the Print Line
Character Count.
If the PRINT line count cannot be restored, the current
line character ODunt is set to zero.
The 'cannot restore the PRINT
line character count' bit is set whenever:
1)
LISTing is being done and the LIST device is the same device as
2)
A new PRINT device is selected (by a SELECT PRINT statement).
3)
Output is being done which is not the result of the PRINT or PRINT
the PRINT device.
USING verbs (console output) and the console output device address
equals the PRINT device address.
4-34
The PRINT line count is not saved or restored when a PRINT statement is executed in the immediate execution mode since the resultant
output goes to the Console Output device, not the PRINT device.
4.4
4. 4.1
DETAILED TIlEORY OF CPU OPERATION (CENTRAL PROCESSOR
&
POWER SUPPLY)
CPU HARDWARE
To show how the microinstructions are decoded and used by the
CPU, a series of instructions in the Master Initialization Microroutine
are described in this section.
Each instruction is clocked through the
CPU hardware by machine cycle, the machine cycle beginning at MERO and
ending at DIN.
All events that occur at the different clock times during
the machine cycle are described.
Due to the complexity of the Master
Initialization Microroutine, only a small portion is described here.
Machine cycles described are as follows:
)
,,
,
•,
1
·
·
"
20
21
""
""
""
"
""
.
""
"
"""
"
..
...
...
96 thru lDO
3D,
3D3
105thrulD7
""
llOthru1l3
116
U.'"
U.
12.
12'
Ll2
123
126
)
'"
12.
12'
139
...
Sun Mutet' Iu1tialiuU...
Set Ie Reghle.. t.o Tup Ad4rua
Bunch to Dt-able Suhrouti_ (SI)
Initialize Stat... ileghter 1 (mtI)
Clear SurU8 bglner 2 «(al)
bithl1zeStatueltegbterJ (mil)
Inmch to ~by Slbrout1D. (5.)
.....
Raturn to ll1.eahle Sw>n>uUu (sa)
llX:re-..t IChpner (llOOP)
SetXBRegiater-O(caI)
Set n. lIealater· 0 (,..1)
nuable All Devieea (CIO)
Return to Kuter Iuitt&11zaUoa Proar_ (Sa)
lnc:r_utICRegiater(IIOOP)
set Statusllqiater 4 .. 0 (mIl
Br. .chto ZeroPl-4S .... routin. (SIl)
PC hgiaur4" 0 (01ll)
PC Ileghter J .. 0 (cal)
Ileturn to Muter Initial1zart- l'rosr_ (51.)
Iucrement lCbgbter (IIOOP)
Cl.... r AunUa..,. Ilea:htera (tP)
PC Reghter 1 - 2 and D1...... 1e T1Id.Da (On)
I12fre.h Me.:J1"J'
Wr1te01DtoKathScratchAreaof~I"J'W)
Tr&lUlfer "_ry Size to PC Reat-ter to (1XP)
Write PC4 into pu. llea1.te~ • (oa.t)
Write I' 1IIto FU.. "p.eter] «(Jil)
~~~.: ~::~~~~..::p.eter 2
p.
«(Jil)
Write
1nto ","_ry (A)
E:l<chaD.S" PC end AI. lilt by 2. Write I'] tntll "'-"ry (1:1'+2)
~ns.PCResJ.et .. rllndA"a1U.ryResJ..te~ (n')
RIIuti.... ln.tru"t1oua
lI.....,h to MOVEFP (D)
lDutina Iutruetioll (CIlJ)
IIoutina1ntltruCtiOll.
Writ.. 0 iDtll SJIIboI Table (AI)
Wrtu0 intllSJIIbolTabl. (AI)
BiMry Add I' in Pil. Repstet 1 (AI)
hcllUlge PC ba end Am: Ilea +2 (nf-2)
EzchaD.le PC'-'I ....J Aux lei (n)
InDclI If Not SqUIll to Kaak (1111I)
Write 0 intO S}'IIhol T"le (A.I)
WriteOilltoSJ'lbolTable(A.I)
Binary Add P in Pile Reaiat.r 1 (Al)
E:l<chaD.ae PC IleE and Am: IleS
Exehanle PC Ilel aDd Aux . . .
Brap<:hIfNotEqual (liNE)
BrllDChIfNotEq\.llll (111m)
S'-routinelleturu (n)
4-35
+2 (XP+2)
(XI'
FIGURE 4-19
DETAILED 2200 CPU BLOCK DIAGRAM
4-36
Machine Cycle 1.
1.
(Start Master Initialization)
MER
6311:
WOLF TRAP is active when the power is applied.
At MER time, RTT
and TRAP are clocked low.
6310:
All the outputs of L41 are high.
L46 pin 12 is clocked low,
enabling L32 pin 12.
6309:
RTT clears the IC Register (L13, L23, L34 and L45) and sets the
ROM Address (ID
I
- IDS' IC
I
- IC ' IB - IB and IA - lAS) to
I
S
I
S
address Hex 0000.
2.
02
6325:
)
The ROM address bits IA
I
- lAS' IB
I
- IB
S
and leI are applied
to TTL to MaS drivers L9, LIS, L19, L2S and L29.
IC
2
and IC
4
decode a 'a' at L52 pin 4, selecting the ala address for ROM
columns 4 and B (ala enables ROMs L34 thru L37 and L30 thru L33).
At 02 time L3S is clocked and the ROM Address Read is applied to
pin S of all ROMs.
ID
I
and IC
S
low set L53 pins S and 11 high,
which select the C3 inputs to the ROM Multiplexer L41 thru L51.
The C3 inputs are from Raw 4, therefore ROMs L34 and L30 are
selected for output of the ROM instruction.
The ROM instruction
contaIned at the selected address is Hex B041S and is applied to
the ROM Output Latch L55, L56, L5S, L60 and L62.
ID
)
2
and ID
4
are low and decoded by L52 pin 12.
L3S pin 9 (X) will
be connected to L52 pin 12 for the first ROM board.
4-37
I.
DIN
6325 :
At DIN time, L38 pin 11 is clocked low, enabling the ROM Output
Latch, and the ROM Instruction is clocked into the Latch.
(Set IC Register to Trap Address)
Machine Cycle 2.
6310:
The ROM Instruction clocked from the ROM has an Op Code B (1011),
indicating an unconditional branch.
R
is low, and L32 pin 11
19
enables L34 pin 12 (L32 pin 12 was set low at MER above).
low and R
LB.
1.
17
, R
are high.
16
R
is
18
L34 decodes a '3' at pin 4, generated
LB sets BRH and BRL low.
MER
6311:
L6 pin 4 returned high prior to MER.
MER clocks RTT inactive.
6309:
TRAP selects the C3 inputs to the IC Register Source Selector
L11, L12, L2l, L22, L32, L33, L43 and L44.
BIDI and BRL were decoded previously, enabling the load input to
the IC Register.
MER loads the IC Register with the hardwired
Trap address (Hex 0001).
2.
DIN
6325:
The ROMs are selected as described in Cycle 1 from address Hex 0001
and the ROM Instruction is clocked into the ROM Output Latch at
DIN time.
The ROM Instruction contained at the selected address
~ is Hex A163B.
(1010 0001 0110 0011 1011).
4-38
Machine Cycle 3 (Branch to Disable Subroutine)
6310:
)
The ROM Instruction has an Op Code A (1010), indicating a Subroutine
Branch.
R
is low and L34 remains enabled.
19
'2' at pin 3, generating SB.
L34 now decodes a
SB keeps BRH and BRL active.
The ROM bits R - R
are applied to the input of the IC Register
O
15
Selector.
1.
MERO
6309:
The IC Register still contains the previous ROM address, Hex 0001.
The address bits are inverted by L14, L34, L35 and L46 and applied
to the input of the Subroutine Stack Register (SSR) LID, L20, L3l
and L42.
At MERO time,
Register ID
)
8
thru IA
I
L3 pin 6 goes low, writing the IC
into the SSR.
When MERO returns high, the
SSR Address Counter L4 is decremented.
Note that first the IC
Register is written into the SSR at the present SSR Counter
Address and then the SSR Counter is decremented.
2.
MER
6311:
WOLF TRAP is now inactive and MER clocks TRAP high.
6309:
With TRAP high, L2 pins 8 and 11 go low, selecting the CO inputs to
the IC Register Selector.
applied earlier.
The CO inputs are the ROM bits R
- R
15
O
As BRH and BRL are still active, the ROM
Instruction bits R - R are loaded into the IC Register by MER
l5
O
for the new ROM Address.
)
Note that the ROM Address bi ts IA
8
- IA
I
are from ROM bits R - R ' IB - IB from R
- R , IC - IC from
3
O
8
I
II
8
8
I
4-39
H
7
- 1\, ,Uld IIl K - " \ from 1(15 - 1(12'
lAS - ID
R
15
1.
l
- R
O
Therefore the HOM Address
(Hex 136B) is not the same as the ROM address bits
from the ROM Instruction (Hex l63B).
DIN
6325:
The ROM Instruction contained at address Hex l36B is clocked into
the ROM Output Latch at DIN time.
43C2A.
The ROM Instruction is Hex
(0100 0011 1100 0010 1010.)
Machine Cycle 4.
(Initialize Status Register 1)
6310:
The ROM Instruction has an Op Code 01000 indicating an OR Immediate.
R
high disables L34 outputs.
19
high, CG is set low.
With L34 outputs high and R
19
R
and R
are low, enabling L33 pin 2
19
17
(lG) and pins 14 and 15 (2G, 2C).
the YO outputs low.
R
and R
are low, setting
15
16
2YO low sets 53, 52 and 51 of the ALU high
and R
high sets the M bit of the ALU high indicating an F = A+B
17
logic operation (+indicates a logical OR operation, not an
arithmetic addition).
The 'B' Bus is selected as follows:
At L40, R
is high, selecting the B inputs.
19
setting the Y outputs of L40 high.
R
- RIO are high,
13
B Bus Selector #1, L35 thru
L3K, selects the D inputs, which are wired low, and presents
3
them to 'B' Bus Selector 112, L29/L39.
L40 pins 9 and 12 select
the C3 inputs and the Y outputs are applied to B Bus Selector
#3, L17.
L33 pin 12 is high, selecting the B inputs of L17.
The
B Bus is then applied as data to the ALU A - AD inputs as 0000.
3
This method of selecting the B Bus from hardwired 0000 data is
known as a 'dummy register'.
The dummy register is always selected when
the B Field of the ROM Instruction is 1111.
4-40
The A Bus is selected in a similar manner as follows:
R
is low and selects the CO inputs to the A Bus Selector L2/L3
18
via L4 pins 3 and 11.
R7 is low and enables L2/L3 pins 1 and 15.
The CO inputs are ROM bits R - R , the immediate operand.
7
4
R - R
7
4
is applied to the ALU B - B inputs as 0010.
3
O
The ALU performs the OR operation and outputs F
3
- F
O
This is applied to the A inputs of C Bus Selector L8.
13 is low, selecting the A inputs for C Bus data.
as 0010.
L44 pin
L19 inverts
the selected data and outputs the C Bus 08 thru 01 as 1101.
1.
~R
6311:
C Bus Data 08 thru 01 is 1101 and is appled to inverter L17.
01, D2 and DB are low while D4 is high which sets L20 pin 4
high.
)
CG enables L21 pin 1.
decodes a '2'.
R3 and R2 are 1 0 and L21 pin 6
R ' R and R
are 0 1 0, and at
O
l
14
pin 7 decodes a '6', generating STl •
t
STl
t
~R
time, L22
clocks L20 pin 1 and
STl- 2 is set high, inhibiting all input devices.
STl-l and
5Tl-3 are set low.
6310:
STl
t
clocks L46 pin 8 high to set STI-O low.
6309:
The ROM Address (10
Register at
~R
8
thru IA ) that had been loaded into the IC
l
time of machine cycle 3 is now incremented.
Note
that although MER is applied to all counters in the IC Register,
only L45 will be incremented by MER until the carry output, pin
15, goes high to enable the following counter.
The IC Register now contains ROM Address Hex 136C as seen on the
~)
10, IC, IB and IA Bus.
4-41
2.
DIN
6325 :
The ROM Instruction at address Hex l36C is clocked into the ROM
Output Latch at DIN time.
The ROM Instruction is Hex 43COB.
(01000011 1100 00001011).
Machine Cycle 5.
(Clear Status Register 2)
6310:
The ROM Instruction Op Code again specifies an OR Immediate.
All
operations are the same as described in machine cycle 4 except
the A Bus data is now 0000 and the resultant C Bus data
D8 thru Dl is 1 1 1 1.
6311:
The C Bus data D8 thru Dl is applied to inverter L17 and is seen
as 0000 by the Status Registers.
CG is low and enables L2l pin 1.
a '2' at pin 6.
R and R are 1
2
3
R , R and R
are 1 1 O.
l
O
14
'7' at pin 9 generating ST2 .
t
ST2
clearing all four bits of SR2 to
a
t
a
and L2l decodes
At MER time, L22 decodes
clocks Status Register 2 (L16)
0 0 O.
6309:
MER increments the IC Register to Hex l36D in the same manner as
described in machine cycle 4.
2.
IHN
6325:
The ROM Instruction at address Hex 136D is clocked into the ROM
Output Latch at DIN time.
The ROM Instruction is Hex 47C88 (0100
0111 1011 1000 1000).
4-42
Machine Cycle 6.
(Ini tialize Status Register 3)
6310:
)
The ROM Instruction Op Code again specifies an OR Immediate.
All
operations are the same as described in machine cycle 4
a
except the A Bus data is now 1
data 08 thru 01 is
1.
a
a
0
and the resultant C Bus
1 1 1.
MER
6311:
The C Bus data 08 thru 01 is applied to inverter L17 and is seen
as 1 0 0 0 by the Status Registers.
R and R are 1
3
Z
CG is low and enables LZl pin 1.
at pin 6.
and L18 pins 1 and 6).
~)
aa
R , R and R
are
O
l
14
at pin 1 generating ST3 •
t
is set high.
data into RAM.
ST3
1.
a
and LZl decodes a
'z'
At MER time, LZZ decodes a '0'
clocks Status Register 3 (L19 pin 1
t
L18 pin 4 (08) is high at this time and ST3-3
ST3-3 indicates the addressing mode for reading/writing
When ST3-3 is high, the Horizontal Mode is
When it is low, the Vertical Mode is used.
addresses the RAM Sequentially
addresses the RAM by page
(±
(±
se~ected.
The Horizontal Mode
1) while the Vertical Mode
16),
6309:
MER increments the IC Register to Hex l36E in the same manner as
described in machine cycle 4.
Z.
DiN
6325:
The ROM Instruction at address Hex l36E is clocked into the ROM
Output Latch.
The ROM Instruction is Hex A1733 (1010 0001 0111 0011 0011).
)
4-43
Machine Cycle 7.
(Branch
to
Delay Subroutine)
6310:
The ROM Instruction Op Code is A(lOlO) indicating a Subroutine Branch
to the address specified by R
- R •
15
O
L46 pin 12 is still low at this time.
are 0 1 O.
R
and R
18
17
R19 is low, enabling L34.
R ,
16
L34 decodes a '2' at pin 3 and SB is active.
SB enables BRH and BRL.
1.
MERO
6309:
SB enables L3 pin 4.
At MERO time, L3 pin 6 goes low, writing the
IC Register into the SSR.
Since the IC Register still contains the
address of the last ROM instruction (NOT R
- R of the present ROM
15
O
Instruction), this address is written into the SSR.
When L3 pin 6
returns high, the SSR Address Counter is decremented.
2.
MER
6309:
With BRH and BRL active, MER clocks the IC Register to load the
bits R
- R .
15
O
~OM
The IC Register now contains the address of the
subroutine branch, Hex 1373.
3.
DIN
6325:
The ROM Instruction at Address Hex 1373 is clocked into the ROM
Output Latch.
The ROM instruction is Hex Al734 (1010 0001 0111 0011
0100).
Machine Cycle 8.
'l1lC
,\Nil
(Delay)
Delay Subroutine generates a 10 usee delay by performing many
InulIl'diate
ROM Instructions with a dummy B field.
4-44
The 10 usee delay
is obtained by doing the 5 usec delay subroutine twice.
machine cycles 8 thru 19.
This is done in
The twentieth machine cycle is a Subroutine
Return to the Disable Subroutine at Address l36F.
Machine cycles 8 thru
19 are omitted.
Machine Cycle 20.
(Return to Disable Subroutine)
6325:
At DIN of machine cycle 19, the ROM instruction at address
Hex 1379 was clocked into the ROM Output Latch.
The ROM Instruction
at that address is Hex 58400 (0101 1000 0100 0000 0000),
Op Code
1 (01011) indicates a Mini Instruction and Op Code 2 (00001) a
Subroutine Return.
6310:
R
and R
low enable L33.
17
19
)
R
and R
high select the Y3 outputs.
16
15
R
high sets the lY3 and 2Y3 outputs low.
18
to decode a Mini Instruction.
decodes a '2', enabling L4l.
R
and R
are 01 and Ll
13
14
RIO' R
and R
are 1 0 O.
12
ll
a '1' at pin 2, setting SR active.
1.
lY3 enables Ll pin 15
L4l decodes
SR set BRH and BRL active.
MERO
6309:
With SR active, L2 pin 11 is high selecting the C2 inputs to the
IC Register Selector.
Register.
The C2 inputs are from the Subroutine Stack
Since the address of the last Subroutine Branch was
written into the SSR and then the SSR Address Counter was decremented,
the SSR Counter must now be incremented to that SSR address.
accomplish this, SR also enables L3 pin 1.
L4 is incremented.
To
At the end of MERO,
The IC Register Source Selector now sees the
address of the Subroutine Branch.
4-45
2.
MER
6309:
BRH and BRL are active, enabling a load into the IC Register.
At
MER, the IC Register is loaded with the address of the ROM
Instruction that specified the Subroutine Branch.
The address is Hex
136E.
6310:
SR sets L46 pin 14 high.
3.
At MER, pin 12 goes high disabling L34.
DIN
6325 :
The ROM Instruction at address Hex l36E is clocked into the ROM
Output Latch.
The ROM instruction is Hex A1733.
(1010 0001 0111
0011 0011).
Machine Cycle 21.
(Increment IC Register)
6310:
The ROM Instruction clocked from the ROM in cycle 20 has an OP
Code A, indicating a Subroutine Branch.
However, L34, which
decodes branch instructions, was disabled by SR during the last cycle.
Therefore, L34 will not decode the Subroutine Branch.
high disables L33.
Also, R
19
By disabling both L33 and L34, no CPU instruction
will be performed.
1.
MER
6309:
MER increments the IC Register by one count.
The IC Register now
contains the ROM Address of the instruction immediately following the
Subroutine Branch.
4-46
6310:
L46 pin 14 returned high when the new ROM Instruction was clocked
)
during cycle 20.
MER clocks L46 pin 12 low, enabling L32 pin 12.
Note that although L34 nOW decodes an SB, no IC Register or
Subroutine Stack Register operations are performed because the
clocks necessary for these operations have passed.
This entire
machine cycle only increments the IC Register to the last
Subroutine Branch Instruction Address +1.
2.
DIN
6325:
The ROM Instruction at address Hex l36F is clocked into the ROM
Output Latch.
The ROM Instruction is Hex 43C08 (0100 0011 1100
0000 1000).
Machine Cycle 22.
(Set KH Register
0).
6310:
The ROM Instruction Op Code specifies an OR Immediate All operations
.are the same as described in machine cycle 4 except the 'A' Bus
data is now 0 0 0 0 ad the resultant
1.
'c'
Bus data DB - 01 is 1 1 1 1.
MER
6311:
The
'c' Bus data 08 - 01 is applied to the I/O Buffer Selector L32.
CG is low and enables L2l pin 1.
'2' at pin 6.
R and R
2
3
R , R and R
are 0 0 O.
l
O
14
at pin 5 generating KH •
t
KH
t
~re
1 0 and L2l decodes
At MER, L22 decodes a '4'
clocks the KH Register, clearing all
four bits to 1111.
6309:
)
MER increments the IC Register to Hex 1370 in a similar manner
as described in machine cycle 4.
4-47
In this case however, the Carry
Output [rom L45 pin 15 was high because a count of 15 (Hex F) was stored
in the counter.
CO enables L34 pin 7 for count.
is incremented to 0 and L34 is incremented to 7.
2.
At MER, L45
CO returns low.
DIN
6325:
The ROM Instruction at address Hex 1370 is clocked into the ROM
Output Latch.
The ROM Instruction is Hex 43C09 (0100 0011 1100
0000 1001).
Machine Cycle 23.
1.
(Set KL Register
0) •
MER
This operation is exactly the same as the KH
=
0 done in machine
cycle 22, except at this instruction, the KL Register is
cleared.
2.
DIN
6325:
The ROM Instruction at address Hex 1371 is clocked into the ROM
Output Latch.
The ROM Instruction is Hex 580CO (0101 1000 0000
1100 0000).
Machine Cycle 24.
(Disable all devices)
6310:
The ROM Instruction Op Code 1 is 01011 indicating a Mini Instruction.
Op Code 2 is 00000, indicating Control I/O (CIO).
R
and R
are low, enabling L33.
19
17
the Y3 outputs.
R
and R
are 1 1, selecting
16
15
lY3 enables Ll pin 15 for the Mini Instruction.
R
and R
are Oland Ll decodes a '2' to enable L4l pin 12.
13
14
RIO' R
and R12 are 0 0 O.
ll
4-48
L4l decodes a '0' generating CIa.
1.
MERO
6311:
)
CIO active enables L36 pin 1.
R , R , R and R are 0, 0, I, I,
6
7
4
5
enabling L36 pin 5 and 124 pin 6.
The
KH
and KL Registers were
cleared in the last two machine cycles, setting OB
8
thru OBI high.
At MERO, the Address Bus Latch, L15/L25, and LIO pin 10 are
clocked.
The Address Bus AB
8
thru AB
I
are now high.
When MMV LIO
pin 12 times out, MMV Lll pin 2 will be triggered, generating ABS,
strobing a device address of 'XOO'.
2.
MER
6309:
The IC Register is incremented to ROM address Hex 1372 as described
in machine cycle 4.
3.
DIN
6325:
The ROM Instruction at address Hex 1372 is clocked into the ROM
Output Latch.
The ROM Instruction is Hex 58400 (0101 1000 0100
0000 0000).
Machine Cycle 25 (Return to Master Initialization Program)
1.
MERO
6310:
The ROM Instruction Op Code 1 indicates a Mini Instruction.
Op Code
2 indicates a Subroutine Return.
The Subroutine Return is decoded in the same manner as described
in machine cycle 20.
)
4-49
2.
MER
6 J09:
The IC Register is lUdded with the ROM address in the same manner
as described in machine cycle 20.
3.
DIN
6325:
The Ie Register contains the ROM Address Hex 0001.
The ROM
Instruction is clocked into the ROM Output Latch at DIN.
Machine Cycle 26 (Increment IC Register)
1.
MER
6309:
No operation can be performed on the ROM Instruction because the
ROM Instruction Decoders were disabled in the previous cycle.
At
MER, the IC Register is incremented by one to the ROM address Hex
0002.
2.
DIN
6325:
The ROM Instruction at Hex 0002 is clocked into the ROM Output
Latch.
The ROM Instruction is Hex 47C09 (0100 0111 1100 0000 1001).
Machine Cycle 27.
(Set Status Register 4
0)
6310:
The ROM Instruction Op Code specifies an OR Immediate.
All operations
are the same as described in DIN of machine cycle 4 except the 'A'
Bus data is now 0 0 0 0 and the resultant
4-50
'c' Bus data D8 - Dl is 1 1
1 1.
6311:
The
'c' Bus data D8 - Dl is applied to inverter L17 and is seen as
aa aa
by Status Register 4, L14.
pin 1.
R
3
and R are 1
2
and R
are
14
a
1 1.
At
a
CG is active and enables L2l
and L2l decodes a '2' at pin 6.
MER,
R , R
l
O
122 decodes a 'I' at pin 2
generating ST4 , which clocks Status Register 4 to zero.
t
6309:
MER increments the IC Register to Hex 0003 in a similar manner as
described in machine cycle 4.
2.
DIN
6325:
The ROM Instruction at address Hex 0003 is clocked into the ROM
Output Latch.
The ROM Instruction is Hex AlE15 (1010 0001 1110
0001 0101).
Machine Cycle 28.
(Branch to Zero Pl-4 Subroutine).
6310:
The ROM Instruction Op Code indicates a Subroutine Branch to the
address specified by R
- R •
O
15
SB, BRR and BRL are set active as
described in machine cycle 6.
1.
MERO
6309:
The IC Register is written into the Subroutine Stack as described
in machine cycle 3.
2.
MER
6309:
)
ROM bits R
- R are loaded into the IC Register.
15
O
now contains the branch address, Hex lIES.
4-51
The IC Register
3.
DIN
63Z5 :
The ROM Instruction at address Hex lIES is clocked into the ROM
Output Latch.
The ROM Instruction is Hex 47COC (0100 0111 1100
0000 1100).
Machine Cycle 29.
(PC Register 4=0)
6310 :
The ROM Instruction Op Code specifies an OR Immediate.
All operations
are the same as described in machine cycle 4 except the
'A' Bus data is now 0 0 0 0 and the resultant 'c' Bus data D8
Dl
islll1.
1.
MER
6311:
CG is active and enables L21 to decode a ' 3' at pin 7 from R and R '
Z
3
R and R are 0 0 causing L8 pin 11 to be low.
O
l
L7 pins 1 and 4 are enabled.
lZ.
With L21 pin 7 low,
R
is 1, however, enabling only L7 pin
14
At MER, L30 pin 13 goes low via LZ pin 6, generating AT ·
4
6309:
The 'Co Bus data D8
Dl is applied to the PC Register Source Selector
L7, L8, L17, L18, L27, LZ8, L38 and L39 as 1 1 1 1.
CG low sets
LZ pins 3 and 6 high, selecting the C3 inputs to the PC Register
Source Selector.
The C3 inputs are from the
to the PC Register L9, L19, LZ9 and L40.
'c' Bus and are applied
When AT
4
is generated, L9
is clocked and PC Register 4 (L9) bits A
- A
are cleared.
IZ
15
MER also increments the IC Register to Hex llE6 in a similar manner
as described in machine cycle 4.
4-5Z
2.
DIN
6325:
)
The ROM Instruction at address Hex lIES is clocked into the ROM
Output Latch.
The ROM Instruction is Hex 47COB (0100 0111 1100
0000 1011).
Machine Cycle 30.
(PC
Register 3=0)
Machine cycles 3D, 31 and 32 clear the remaining PC registers in the
same manner PC Register 4 was cleared in machine cycle 29.
Machine
cycle 30 (PC Register 3=0) clears PC Register 3 (L19) bits All - AS
with AT
3
generated by L22 decoding a '3'.
Machine cycle 31 (PC Register
2=0) clears PC Register 2 (L29) bits A - A with AT generated by L22
2
7
4
decoding a '2'.
1 (L40) with AT
Machine cycle 32 (PC Register 1=0) clears PC Register
I
generated by L7 pin S.
At UDC, L4l is loaded
with the output of L40 and PC Register 1 bits A - A are cleared.
O
3
Machine Cycle 33 (Return to Master Initialization Program)
A Subroutine Return is decoded in the same manner as described in
machine cycle 20 and the IC Register is loaded with the address of
the Subroutine Branch.
The ROM Instruction Decoders are also
disabled at this time.
Machine Cycle 34 (Increment IC Register)
1.
MERO
6310 :
L46 pin 12 is clocked low to enable L32 pin 12.
)
4-53
2.
MER
6309:
The IC Register is incremented to Hex 0004 as described in machine
cyc Ie 21.
3.
DIN
6325:
The ROM Instruction at address Hex 0004 is clocked into the ROM
Output Latch.
The ROM Instruction is Hex 58800 (0101 1000 1000
0000 0000).
Machine
c~cle
35.
(Clear Auxiliary Registers)
The ROM Instruction Op Code 1 indicates a Mini Instruction.
Op
Code 2 indicates a Transfer PC Register to Auxiliary Register (TP).
Recall that the PC Register was cleared in machine cycles 29 through
32.
The Auxiliary Register will now be cleared by transferring the
cleared PC Register into the Aux. Register.
6310:
R
high disables L34.
19
R
and R
low enable L33.
19
17
R
high set the Y3 outputs active.
18
decode a Mini Instruction.
'2 ' at pin 10 enabling L41.
R , R
and
15
16
lY3 enables Ll pin 15 to
are 0 1.
R
and R
14
13
Ll decodes a
RIO' Rn and R12 are 0 1 O.
L4l
decodes a '2 ' at pin 3 enabling WW to be generated.
l.
MERO
6309:
The Program Counter, L5, L15, L25 and L36, is loaded with the PC
Register bits A
- A '
15
O
2.
MER
6309:
The IC Register is incremented to Hex 0005 as described in machine
cycle 4.
4-54
3.
MXS
6310:
MXS generates WW.
6309:
WW writes the output of the PC into the Auxiliary Register at the
address specified by R - R which is 1 1 1 1.
O
3
4.
DIN
6325:
The ROM Instruction at address Hex 0005 is clocked into the ROM
Output Latch.
The ROM Instruction is Hex 43C2C (0100 0011 1100
0010 1100).
Machine Cycle 36.
(PC Register 1
2 and Disable Timing)
6310:
The ROM Instruction Op Code specifies an OR Immediate.
All operations
are the same as described in machine cycle 3 exce£t the 'A' Bus
data is noW 0010 and the resultant
1.
'c' Bus data D8 - Dl is 1101.
MOT
The type of MOS Memory used in the CPU requires that the data be
refreshed every 2 msec.
To accomplish this, the normal machine
cycle is interrupted and a refresh cycle is initiated.
A refresh
cycle occurs one every 36 machine cycles and refreshes all RAMs at
a selected column address.
only the column address (A
entire RAM column.
The RAM chip is designed in such a way that
4
- AD) need be changed to refresh the
As the refresh occurs once every 36 machine
cycles (57.6 u sec) and there are 32 columns to be addressed, an
entire RAM refresh takes 1.85 msec.
)
4-55
6308:
L6, L17, LIB and Ll form a machine cycle counter/decoder.
clocked by MHL once every machine cycle.
L6 is
During machine cycle 35,
Ll pin 8 decoded a count of 35, setting L3 pin 4 high and enabling
R0
2
of L6 and Ll7.
MOT of this cycle clocks L3 pin 15 high and pin 14 low.
L3 pin 14
clears L2, setting p_ ,s 11 and 15 low which sets L44 pin 1 high,
disabling DIN.
2.
MER
6309:
CG active selects the C3 inputs to the PC Register Source Selector,
applying the 'C' Bus, DB - Dl, to the inputs of the PC Register.
6311 :
AT
l
is generated at MER in the same manner as described in machine
cycle 32.
6309:
AT
I
loads PC Register 1 with 1101.
The IC Register is incremented
to Hex 0006 as described in machine cycle 4.
3.
UDC time
6309
PC Register 1 is loaded into latch L4l, setting the Data Memory
Address A
- A to Hex 0001.
O
15
4.
MHL
6308:
With L3 pin 15 high, MHL clocks L3 pin 10 low, setting REF active.
MHL also resets the Machine Cycle Counter L6/L17 and Ll pin 8 returns
4-56
high.
)
REF selects the A inputs to L25 and 140 for memory addressing.
Memory column Address bits A - A are now selected from the Refresh
4
O
Address Counter L26 and L27.
high.
REF also clears L4, setting pin 10
This disables CPU timing signals MERO, MOT, MER, MTF, UDC,
MXS, DAST and MHL.
6307:
REF sets L37 pin 1 low, enabling L59 pins I, 4 and 10, and REF
enables L33, L35 and L36 for memory column addressing.
Note that
MS does not have to be active to address or clock the RAMs.
5.
MNT
6308:
MNT clears the Memory Select and Write Enable Latches L24.
If a WTEN
signal had been the last ROM Instruction performed and it was not
cleared, refresh for the RAMs controlled by the WTEN signal would
not occur.
Machine Cycle 37 (Refresh Memory)
1.
MOT
6308:
During cycle 36, Ll pin 8 returned high, setting L3 pin 4 low.
MOT
clocks L3 pin 14 high, removing the clear from L2 pins 3 and 8.
2.
RESET
6307:
Tile refresh cycle for the RAMs consists of applying three clocks,
CLK , CLK and CLK to the RAM with the Write Enable low during CLK
l
2
3
3
time.
RESET provides CLK
I
via L6l pin 9 and L49 pin 7.
)
4-57
3.
MER
6308:
The clear was removed from L2 at MOT.
If RUN/STEP and TFF are both
inactive, L5 pin 3 is low, enabling L44 and DIN.
4.
01
6307 :
01 provides CLK
5.
2
for refresh via L60 pin 9 and L48 pin 7.
02
6307:
02 provides the final refresh clock, CLK
6 and L48 pin 5.
WTEN
4
3
for the RAMs via L60 pin
At this time all Write Enable signals WTEN
are inactive.
I
-
L54 and L57 pins 2 are enabled and Write Enable
for all RAMs is low as required for refresh.
6.
MHL
6308:
The inputs to L3 pins 9 and 12 were changed during MOT.
MHL clocks
L3 pin 10 high, setting REF inactive, Temoving the clear from L4
pin 8 and incrementing the Refresh Address Counter.
MHL also clocks
the first count into the Machine Cycle Counter.
7.
MNT
6308:
MNT clocks L4 pin 10 low, removing the disable from the system
timing.
8.
MNT also generates DIN via L44 pin 3.
DIN
6325:
The ROM Instruction at Hex 0006 is clocked into the ROM Output
Latch.
The ROM Instruction is Hex 63FOF (OlIO 0011 1111 0000 1111).
4-58
Machine Cycle 38.
(Write 0 into Math Scratch Area of Memory)
The ROM Instruction Op Code indicates a Binary Add Immediate.
investigation shows M ' M are 1 1, indicating a Write Z.
Z
l
Further
Therefore,
the resultant 'c' Bus data of the Binary Add will be written into memory
at the address set up in the PC Register in this machine cycle 36.
6310:
R
and R19 are low causing L44 pin 8 to be low.
17
This sets the 'M'
bit of the ALU low and the Function Selection for F = A plus B.
The 'B' Bus data is selected as dUlllIlly as described in machine cycle
4.
The 'A' Bus data is also selected as described in machine cycle
4 and is 0000.
a resultant F
'c'
1.
3
The binary addition is performed in the ALU with
-
Fa
=
a a a o.
R
low selects the A inputs of the
16
Bus Selector L8, presenting 1 1 l I t o the
'c'
Bus 08 - 01.
MERO
6308:
During machine cycle 6, ST3-3 was set high for horizontal addressing
of the RAM.
During machine cycle 4, STl-3 was set low for RAM
selection and during machine cycle 36, A
- A were set low, except
O
15
AI' which was set high.
With ST3-3 high, L37 selects the B inputs.
pin 9 from R , R and R •
9
9
19
inputs to L36.
LZ3 decodes a '3' at
LZ3 pin 10 is high, selecting the B
The Y outputs of L36 are 1
a
at pin 4 and 7.
LZ3 pin 9 low and STl-3 low, LZ4 pins 16 and lZ are low.
With
At MERO
LZ4 pins 14 and 10 are clocked low.
LZ4 pin 14 enables LZ3 to decode
WTENz
from A and A •
O
4
LZ4 pin 10
enables L14 to decode MSI from Al4 and A15.
6307:
)
Data from the 'c' Bus is applied to Input Gates L58, L56, L55 and
L53.
With MS active, the Input Gates are enabled and the 'C' Bus
4-59
delta is applied to the RAMs.
01
DI
01
' to L55 as 01 8 and to L53 as OIIZ'
4
Z
DID is applied to input gate L56 as
and 01
15
3
In a similar manner, DI ,
l
are applied to the remaining data inputs as 01
thru
4
,
The Data Memory Address AD thru All is applied to TTL to MOS Drivers
L33, L35, L36, L38, L50, L5Z and L34.
These drivers are enabled by
MS and a RAM address of Hex 001 is applied to all RAMs.
WTEN
Z
is applied to TTL to MOS Driver L57.
With REL active, L57
is enabled and RAMs L9, LID, Lll and LIZ are write enabled.
thru 01
Z.
7
01
4
is applied as data to RAMs LIZ thru L9.
MER
6311:
The Memory Data Register, L31, is clocked with the
·c·
Bus data.
6309:
The IC Register is incremented to Hex 0007 as described in machine
cycle 4.
3.
0Z
6307:
0Z, applied to L60, generates CLK
Z
from L48 to provide the write
clock for the RAMs selected at MERO of this cycle.
4.
DIN
63Z5 :
The ROM Instruction at address Hex 0007 is clocked into the ROM
Output Latch.
The ROM Instruction is Hex AOCFA.
This instruction
indicates a subroutine branch to a routine that initializes the
Random Number Generator.
An argument of 0 for the Random No.
Generator was written into memory during the last cycle.
This
will be used to initialize the Generator in this subroutine.
4-60
The instructions in this subroutine are of the type discussed
previously and will be omitted.
Machine Cycle 92.
(Transfer Memory Size to PC Register 4)
The next ROM Instruction to be performed was clocked into the
ROM Output Latch at DIN of the last cycle.
The ROM Instruction
is at address Hex 0009 and is Hex 59COO (0101 1001 1100 0000 0000).
6310:
The ROM Instruction Op Code 1 specifies a Mini Instruction and
Op Code Z a Transfer RAM Size to PC Register 4.
The Mini Instruction is decoded in the same manner as described
in machine cycle ZO.
Cl decodes a
'z' from R13 and R14 and L41
decodes a '7' from RIO' R
and R ' setting TMP active.
ll
lZ
TMP
sets PCG active via L12 and LZ2.
6309:
TMP
With
inputs.
active, the PC Register Source Selector selects the Cl
The Cl inputs for PC4 are from the memory size setting,
all others (PCl - PC3) are wired low.
is set to 4K.
L8 pin 5 will be low and L7 pin 5 and 11 and L8
pin 11 will be high.
1.
Suppose the memory size
The input to PC4 is seen as 1110.
MER
6311:
R
low enables L30 pins Z and 13.
14
As LZI is not enabled, LZ2
pins 3 and 4 will be high, enabling L30 pin 5 and 10.
active, MER is gated through L2 pin 3, generating AT
I
With PCG
- AT •
4
6309:
AT
I
- AT
4 clocks PC Registers PCl - PC4.
MER increments the
IC Register to Hex OOOA as described in machine cycle 4.
)
4~1
2.
UDC
6309:
L4l is loaded with PCl data.
The PC Register bits A - A
15
O
are now Hex IFFF.
3.
DIN
6325:
The ROM Instruction at address Hex OOOA is clocked into the
ROM Output Latch.
The ROM Instruction is Hex 47003 (0100 0111
0000 0000 0011).
Machine Cycle 93.
(Write PC4 into File Register 4)
6310:
The ROM Instruction Op Code specifies an OR Immediate.
All
operations are the same as described in machine cycle 4 except
the 'B' Bus is selected as follows:
R
is high, selecting the B inputs to L40.
19
1 1
a
R
- R
are
13
10
0, this being transposed to the Y outputs.
'B' Bus
Selector #1 selects the D inputs, which are from PC Register 4
4
(A
12
- A ), and presents them to 'B' Bus Selector #2.
15
L40
pins 9 and 12 select the C3 inputs, which are applied to the
A inputs of the ALU via 'B' Bus Selector #3.
The B inputs to the ALU are selected from the 'A' Bus in the
same manner as described in machine cycle 4.
is 0000, and the resultant ALU output is 0001.
The 'At Bus data
This is applied
to the File Register L23 through L26 and inverted by L19 for
'e' Bus data.
4-62
1.
MER
6310:
With CG active and R low, L30 pins 2 and 5 are enabled.
3
MER
clocks (writes into) the File Register at the address specified
by R ' R and R (011).
2
O
l
File Register 4 now contains the RAM
size established by PC Register 4.
6309:
The IC Register is incremented to Hex OOOB as described in
machine cycle 4.
2.
DIN
6325:
The ROM Instruction at address Hex OOOB is clocked into the
ROM Output Latch.
The ROM Instruction is Hex 43CF2 (0100 0011
1100 1111 0010).
Machine Cycle 94.
(Write F into File Register 3)
6310:
The ROM Instruction Op Code specifies an OR Immediate.
All
operations are the same as described in machine cycle 4 with
the resultant ALU output 1111.
1.
MER
6310:
MER writes the data from the ALU (Hex F) into the File Register
at address 010 (File Register 3) in the same manner as described
in the previous machine cycle.
6309:
The IC Register is incremented to Hex OOOD as described in
)
machine cycle 4.
4-63
Machin". Cyc1". 95.
(Writ". F into
Fn".
R".gist".r 2)
An F is written into File Register 2 in the same manner as described
in Cycle 94.
Machin". Cycles 96 - 100
The instructions performed in these cycles are routine but their
result is of importance.
Cycle 96 writes an 8 into File Register 1, completing the RAM size
storage into the File Registers F4 - Fl with Hex IFF8.
Cycles 97 - 101 set the PC Registers with the Data Memory Address
where the data in the File Registers will be written.
known as a system pointer.
The address is
This particular system pointer is called
VSVBEG, referring to the beginning of the Value Stack.
A reference to
the CPU Software Theory of Operation will show the Value Stack beginning
is the end of RAM.
When data is to be written into the Value Stack or
any time .the RAM size is required, the pointer being developed at this
time will be recalled.
Cycle 97 writes a 4 into PCl by generating AT .
I
Cycle 98 writes
a 5 into PC2, cycle 99 branches to a subroutine to write the File Registers
into memory.
Cycles 100 and 101 write 0 into PC3 and PC4.
Data Memory Address to
Hex
This sets the
0054.
Machine Cycle 102 (Write F4 into Memory)
The
ROM
Instruction clocked during the last cycle is Hex 23E3F
(0010 0011 1110 0011 1111).
4-&4
6310:
The ROM Instruction Op Code specifies a Binary Add.
and
~9 o
With R
17
0, L32 pin 8 goes low, setting the M bit of the ALU
low and decoding an F = A plus B function.
The A inputs to
the ALU are selected from a dummy 'B' Bus in the same manner
as described in machine cycle 4.
The 'A' Bus is selected as follows:
R is low enabling the 'A' Bus selector L2/L3 and setting
7
pin 2 low.
R is high, enabling L4 pins 1 and 12.
18
R and R
6
7
are low, setting L4 pin 3 high, selecting the Cl inputs to the
'A' Bus Selector.
The Cl inputs are from the File Register.
The File Register B Read address is selected from R , R and
4
5
R , which are 110, selecting File Register 4.
6
PC4 was previously
written into File Register 4.
)
The Binary Add is performed in the ALU with the resultant output
'c' Bus (D8 - Dl) 1110.
to the
1.
MERO
6308:
R , R and R are 010, decoding a '2' at L23 pin 10 setting
19
8
9
L24 pin 16 low.
low.
MS
I
STl-3 is low (RAM status) setting L24 pin 12
MERO clocks both portions of L24 enabling L14 to decode
- MS
4
and L23 to decode wrEN
l
- WTEN •
4
MERO also clocks
the Data Memory Address Register L12, L13, L38 and L39 with the
PC Register (Hex 0054).
A14 and
~5
With A and A 0 0, L23 decodes wrEN •
O
4
l
are 0 0, and L14 decodes MS "
l
)
4-65
2.
MER
6311:
The Memory Data Register, L3l, is clocked with the
'c' Bus
data.
6309:
The lC Register is incremented to Hex 0302.
3.
REL
The data on the
'c' Bus is written into RAMs L13 - L16 as de-
scribed in machine cycle 38.
4.
DIN
6325:
The ROM Instruction at Hex 0302 is clocked into the ROM Output
Latch.
The ROM Instruction is Hex 5BB2l (0101 1011 1011 0010 0001).
Machine Cycle 103 (Exchange PC and AX, Inc. by 2;Write F3 into Memory)
The ROM Instruction Op Code 1 indicates a Mini Instruction.
Op
Code 2 indicates an Exchange PC Register and Auxiliary Register and Increment Auxiliary Register by 2.
6310:
The Mini Instruction is decoded by L33 as described in cycle 20.
Ll decodes a '3' at pin 9 from R
and R , enabling CTA and
14
13
WW to be generated.
pin 8.
R
is low, setting PCG active via L30
12
With R
high, the M bit of the ALU is enabled for a
17
logic operation of F = B.
disregarded.
The 'B' Bus is not used and can be
The 'A' Bus is selected from File Register 3 in
a similar manner as described in the previous cycle.
An 'F'
was written into File Register 3 previously, and the resultant
'c' Bus 08 - 01 is 0000.
4-66
1.
MERO
6309:
The Program Counter L5, L15, L25, L36 is loaded with the PC
Register bits A
- A '
15
O
The PC Register is Hex 0054.
6308:
Write Enable and Memory Select are decoded in a similar manner
as described in the previous cycle except L23 decodes a '3'
at pin 9, selecting A and A to decode WTEN .
2
4
O
Also, MERO
clocks the PC Register into the Data Memory Address Register.
The PC Register still contains Hex 0054.
2.
MER
6311:
With PCB active, MER is gated through L2 pin 3 to generate
AT
1
- AT •
4
'c'
The Memory Data Register is clocked with the
Bus data.
6309:
TIP, CG and TMP are all inactive, selecting the Auxiliary
Register as the input to the PC Register.
Register address is 0001.
The Auxiliary
The data at this address of the
Auxiliary Register is clocked into the PC Register by AT
but this data is unknown.
1
- AT ,
4
Also, the IC Register is incremented
to Hex 0303.
3.
MTF
6310:
R
is high, enabling L43 pin 1.
1l
MTF generates CTA.
6309:
R10 is
)
a
enabling L3 pin 9.
CTA increments the Program Counter
at L36 pin 5 by a count of two (CTA is composed of
nsec pulses).
two
100
The Program Counter now contains Hex 0056.
4-67
4.
MXS
6309:
L30 pin 13 was enabled earlier in this cycle.
MXS now generates
WW and the Program Counter data (Hex 0056) is written into
the Auxiliary Registers L6, L16, LZ6 and L37 at the address
specified by R - R (0001).
3
O
5.
REL
6307:
REL enables WTEN
6.
Z
to be applied to the RAMs.
0Z
6307:
The data on the
'c'
RAMs L9 - L1Z.
It is important to note here that the RAM address
Bus (from File Register 3) is written into
is the same as the address used during the previous cycle.
this case, however, WTEN
writing.
Z
In
enables a different group of RAMs for
In this manner, an eight bit word is written into
eight RAMs at the same address.
When this word is read, it
can be read as a complete eight bit word.
It is also important
to note at this time how the eleven bit RAM address is derived
from the sixteen bit PC Register.
The sixteen PC Register bits
are applied to the Data Memory Address Register L13, L1Z, L38
and L19 on the 6308.
A
and A
are used to decode the MS
14
15
qignals for the Memory Board select and A and A decode the
O
4
WTEN signals to write enable one of four groups of RAMs and
select the data to be read from Memory by the CH and CL Read
Buffers.
A
is used to select the first half (first 4K) or
13
second half (second 4K) of the Memory Board.
The remainder
of the PC Register develops the actual RAM address as follows:
4-68
7.
PC Register Bit
RAM Address Bit
AI"
AD
A2 •
Al
A3 •
A
2
AS'
A
3
A6 "
A
4
A7 •
AS
AS'
A
6
A9 •
A
7
AID
AS
An
A
9
A12
A
lO
AU
An
DIN
6325:
The ROM Instruction at Hex 03D3 is clocked into the ROM Output
Latch.
The ROM Instruction is Hex 59001 (0101 1001 0000 0000
0001).
Machine Cycle 104 (Exchange PC Register and Auxiliary Register)
The ROM Instruction Op Code 1 indicates a Mini Instruction.
Op
Code Z indicates an Exchange PC Register and Auxiliary Register.
6310:
The Mini Instruction is decoded by L33 as described in cycle 20.
Ll decodes a '2' at pin 10 enabling L4l to decode a '4' at pin
5 from RIO' R , and R '
lZ
ll
enables WW to be generated.
J
4-69
L4l pin 5 low sets PCG active and
1.
HERO
6,09:
The Program Counter is loaded with the PC Register data (the
data in the PC Register is unknown).
2.
MER
6308:
The unknown PC Register is clocked into the Data Memory
Address Register.
6311:
With PCG active, MER is gated through L2 pin 3 to generate
AT I - AT 4 ·
6309:
TIP, CG, and TMP are all inactive, addressing the PC Register
Source Selector to select the Auxiliary Register as the input
to the PC Register.
The address of the Auxiliary Register is
0001, at which the VSVBEG pointer address +2 (Hex 0056) was
written in the last cycle.
The Auxiliary Register data is
now clocked into the PC Register by AT
I
- AT
4
(note the output
of the Auxiliary Register is the binary compliment of the PC
Register and the PC Register inverts the Auxiliary Register).
The lC Register is incremented to Hex 03D4.
3.
UDC
6309 :
L4l is loaded with PCI.
The PC Register bits A
- A are
15
O
Hex 0056, which results in a RAM address of Hex 053, which
will be clocked into the Data Memory Address Register at
MERO of the next cycle.
4-70
4.
MXS
6310:
MXS generates WW.
6309 :
WW writes the Program Counter (unknown) into the Auxiliary
Register.
5.
DIN
The ROM Instruction at Hex 03D4 is clocked into the ROM Output
Latch.
The ROM Instruction is 23ElF (0010 0011 1110 0001 1111).
Machine Cycles 105 - 107
Machine cycles 105 and 106 write File Register 2 and File Register
1 respectively into memory in the same manner as previously described.
Cycle 107 is a Subroutine Return to Master Initialization Program.
Machine Cycle 108 (Branch to MOVEFP)
Cycle 108 branches to a subroutine that will move the data in the
File Registers to the PC Registers.
As you will recall, the RAM size
is still contained in the File Registers.
The PC Register will now be
loaded with this data to address the end of RAM.
Machine Cycle 109
l11e ROM Instruction clocked during the last cycle was 03COC (0000 0011
1100 0000 1100), at address 0353.
)
4-71
6310:
The ROM Instruction Op Code indicates an OR.
L33 pin 9 decodes
the OR instruction selecting the ALU function for a logical
F
= A + B.
The 'B' Bus is selected from the 'dummy' as described
in cycle 4 and the 'A' Bus is selected from File Register 1 in
a similar manner as described in cycle 101.
The resultant
'c'
Bus data is the compliment of File Register 1 (File Register 1
contains 1000).
1.
MER
6311:
With CG active, L2l decodes a '3' at pin 7 from R and R .
2
3
R and R are 0 0 causing LB pin B to be low.
O
l
L7 pin 10.
At MER, AT
R
is 0 enabling
14
PCG is inactive, enabling L30 pins 1, 4, 9 and 12.
I
is generated.
6309:
The 'c' Bus is applied to the PC Register Source Selector.
The C3 inputs are selected with CG active.
AT
I
clocks the
'c' Bus (File Register 1) into PC Register 1.
The IC Register is incremented to Hex 0354.
2.
DOC
L4l is loaded with PC Register 1.
3.
DIN
The ROM Instruction at Hex 0354 is clocked into the ROM Output
Latch.
Machine Cycles 110 - 113
In a similar manner as described in machine cycle 109, PC Registers
2, 3 and 4 are loaded with File Registers 2, 3 and 4.
4-72
Machine cycle 113
writes a 4 into File Register 1 and 115 is a branch to a Subroutine
to clear the end of the Symbol Table.
Machine Cycle 116 (Write 0 into Symbol Table)
The ROM Instruction at Hex 043F is 63EOF (0110 0011 1110 0000 1111).
6310:
The Op Code indicates a Binary Add Immediate.
All operations are
the same as described in cycle 38 with the resultant
'c' Bus data
1 1 1 1.
1.
MERO
6308:
WTEN
3
and MS
I
are decoded from A ' A and A , A
in a similar
O
4
14
15
manner as described in machine cycle 38.
The PC Register is clocked
into the Data Memory Address Register.
2.
MER
6309:
The IC Register is incremented to Hex 0440.
3.
REL
6307:
Data on the
cycle 38.
'c' Bus is written into RAMs L5-L8 as described in
The RAM address derived from the Data Memory Address
Register is Hex 7FC.
4.
MNT
6308:
MNT clears the Memory Select and Write Enable Latches.
5.
DIN
6325:
)
The ROM Instruction at Hex 0440 is clocked into the ROM Output
Latch.
The ROM Instruction is Hex 63FOF (0110 0011 1111 0000 1111).
4-73
Machine Cycle 117.
(Write 0 Into Symbol Table)
Machine Cycle 116 is identical to cycle 116 except WTEN
4
is decoded
and the data is written into RAMs Ll-L4.
Machine Cycle 118.
(Binary Add F in File Register 1)
The ROM Instruction is Hex 600FO, indicating a Binary Add Immediate
(without carry).
1.
MER
6310:
The 'B' Bus is selected from File Register 1 and the 'A' Bus
from R - R with the resultant ALU output 0 0 1 17
4
This 3 is
written into File Register 1 in a similar manner as described in
cycle 93.
2.
DIN
6325 :
The ROM Instruction at Hex 0442 is clocked into the ROM Output
Latch.
The ROM Instruction is Hex 5B80l (0101 1011 1000 0000 0001).
Machine Cycle 119.
(Exchange PC Reg. and Aux. Reg. +2)
The ROM Instruction Op Code 1 indicates a Mini Instruction and Op
Code 2 an Exchange PC Register and Auxiliary Register +2.
an~
the
Silmf:'
All operations
as described in Machine Cycle 103, \.n.th the final Auxiliary
I{l'gislpr v,due Hex IFF".
Machine Cycle 120.
(Exchange PC Reg. and Aux. Reg.)
The ROM Instruction is Hex 59001.
Op Code 1 indicates a Mini
Instruction and Op Code 2 an Exchange PC Register and Auxiliary Register.
This is similar to machine cycle 103.
The PC and Auxiliary Registers
now contain Hex lFFA.
Machine Cycle 121.
(Branch If Not Equal to Mask)
The ROM Instruction is Hex F030F (1111 0000 0011 0000 1111).
6310:
The Op Code indicates a Branch if Not Equal to Mask.
L34 to decode a '7' at pin 9 from R , R
and RIO.
17
16
R
low enables
19
With L34 pin 9
low, the ALU is selected for an Exclusive OR function, F ; ~,
and FNHG is high.
)
The B Bus is selected from File Register 1
(' B' Bus Selector #2 is selected for CO imputs by R
and R
and
14
15
and R ) and applied to the
File Register read address by R , R
12
13
14
ALU
A inputs.
The 'A' Bus is selected from the mask (R
7
- R ) as
4
described in cycle 3.
The two ALU imputs are compared.
If they are equal, the A;B output
from the ALU is high; if not equal, A;B is low.
Register 1 is 0100 and the 'A' Bus is 0000.
low and FNHG is high, setting
1.
m
At this time, File
The A;B output is
active.
MER
6309:
)
With BRL active, IC Registers 1 and 2 are loaded with ROM Bits R 3
R (F) and R
- R (3), therefore the IC Register contains
O
ll
S
043F (IC Registers 3 and 4 do not change because BRH is not active).
4-75
2.
DIN
6325:
Ihe ROM Instruction at Hex 043F is 63EOF.
Machine Cycle 122.
(Write
a
into Symbol Table)
The Subroutine has branched back to the same instruction that was
performed in cycle 116.
Another 0 is written into memory at the new
RAM address Hex 7FD.
This process of writing zeroes into memory and incrementing the
PC Register will continue until the end of Memory is reached.
Each
machine cycle will be explained briefly.
Machine Cycle 123.
(Write
a into Symbol Table)
All operations are the same as described in cycle 117 with a RAM
address of Hex 7FD.
Machine Cycle 124.
(Binary Add F in File Register 1)
File Register 1 contains a 3 as a result of cycle 118.
Binary
Addition without carry is again performed by the ALU, the resultant
output 0010 is written back into File Register 1.
Machine Cycle 125.
(Exchange PC Reg. and Aux. Reg. +2)
All operations are the same as described in cycle 119 with the
final Auxiliary Register value Hex lFFC.
4-76
Machine Cycle 126.
(Exchange PC Reg. and Aux. Reg.)
The PC Register is loaded with the value of the Auxiliary Register.
Machine Cycle 127.
(Branch If Not Equal)
The mask and File Register 1 are not equal and the branch is made
back to ROM address 043F in the same manner as described in cycle 121.
Machine Cycles 128 and 129 write a 0 into memory at PC Reg. value
Hex lFFC (RAM address Hex 7FE).
to 0001.
Cycle 130 decrements the File Register
Cycle 131 increments the Aux. Register to Hex lFFE and 132
transfers this to the PC Register.
043F.
Cycle 133 branches back to ROM address
At this time the RAM address is Hex 7FF, the last address location
in the memory.
Cycles 134 and 135 write zeroes into that address and
136 decrements File Register 1 to 0000.
Cycles 137 and 138 increment
and transfer the PC Register and Aux. Register to Hex '2000.
Machine Cycle 139.
(Branch i f Not Equal)
File Register 1 now contains a O.
When the ALU compares the A
and B inputs, the A=B output goes high, preventing the branch from being
performed by inhibiting BRL.
1.
MER
6309:
MER increments the IC ReRister to Hex 0445.
)
2.
DIN
The ROM Instruction at Hex 0445 is Hex 58400.
4-77
The ROM Instruction indicates a Subroutine Return.
The program
returns to Hex 0014 as described in machine cycles 20 and 21.
A recap of the important instructions that
h~ve
been performed
would be helpful at this time.
Cycle 2 set the IC Register to the TRAP address.
6 initialized Status Registers 1, 2 and 3.
Cycles 4, 5 and
Cycles 22 and 23 set the KH
and KL Registers to 0 and cycle 24 strobed a device address of
d1sable all I/O devices.
(SR4).
37 refreshed the Data Memory.
Registers.
pointer.
to
Cycle 27 initialized the last Status Register
Cycles 29 thru 32 cleared the PC Register to O.
PC Register 4.
'xoo'
Cycles 36 and
Cycle 92 transferred the Memory Size into
Cycles 93 thru 96 wrote the memory size into the File
Cycles 97 thru 101 set the PC Register to the VSVBEG system
(Cycles 92 thru 113 show how the PC and F1le Registers work
in conjunction with one another, transferring data back and forth.)
Cycles 116 through 138 cleared four eight bit words in the Symbol
Table with several Branch if Not Equal Instructions performed.
At this point,
the remainder of the Instruction Set will be
discussed without the use of successive machine cycles.
4-78
Decimal Subtract with Carry (DSC)
A typical ROM Instruction using DSC is Hex 19806 (0001 1001
10000000 0110).
The DSC Instruction subtracts the B Bus data from
the A Bus data with the result output to the C Bus.
6310:
L33 decodes the DSC at pin 12.
With L33 pin 4 high, DSC is active
and 144 pin 8 is low, setting the ALU for an arithmetic operation
and selecting the F = A plus B function.
Status bit STl-O (carry)
was set active in the preceding instruction, enabling the Carry
Function in the ALU.
becomes F
With the carry input active the ALU function
A plus (B+l).
The B Bus is selected from File Register 7.
register contains a 3.
Suppose this
The 3 is applied to BCD 9's Compliment
Converter L6, which was enabled by DSC, converting the B Bus data
to 0110 as the A word input to the ALU.
The A Bus is selected from File Register O.
a 7.
Suppose FRO contains
The resultant ALU output is 1110, with no carry.
A portion
of the ALU output is applied to the Binary to BCD Converter L9.
is high, selecting the B inputs to the C Bus selector L8.
R
16
The resultant output of the selector is 0100 (7-3=4).
operation did not produce a carry, L46 pin
Since the ALU
will be low, allowing
the Status Register to be cleared the next time it is clocked.
Transfer PC Register to IC Register (TPI)
The TPI Instruction is particularly useful in recursive subroutines.
Instead of storing the return address In the Subroutine Stack Register,
)
the return address is stored in the PC Register, saving time and SSR
space.
4-79
A typical TPI Instruction is Hex 59400 (0101 1001 0100 0000 0000).
6310:
(~)
Code I is decoded as a Mini Instruction enabling L4l to decode
TP1 at pin 6.
1.
TPI sets BRR and BRL active.
MER
6309:
TPI selects the Cl inputs to the IC Register Source Selector.
PC Register is applied to the IC Register.
The
With BRR and BRL are
active, MER clocks the PC Register into the IC Register.
Transfer IC Register to PC Register (TIP)
This Register instruction is similar to the TPI Instruction, again
used in recursive subroutines.
A typical TIP Instruction is Hex 59800
(0101 1001 1000 0000 0000).
6310:
Op Code 1 is decoded as a Mini Instruction enabling L4l to decode
TIP at pin 7.
TIP sets PCG active.
6309 :
TIP selects the C2 inputs to the PC Register Source Selector.
1.
MER
6311 :
MER generates AT
I
AT
4
via L2 pin 3.
6309:
AT
2.
1
- AT
4
clocks the IC Register into the PC Register.
UDC
6309:
UDC loads L41 with PC Register 1.
4-80
The PC Register now contains
the data from the IC Register.
The address in the IC Register that
is transferred is the address of the TIP Instruction.
Transfer PC Register to Auxiliary Register, Increment by 1 (TP+l)
This instruction is similar to the TP Instruction discussed in
machine cycle 35 except after the PC Register is transferred to the
Program Counter, the PC is incremented by one and then written into
the Auxiliary Register.
A typical TP+l Instruction is Hex 5AOOO (0101
1010 0000 0000 0000).
6310:
Op Code 1 is decoded as a Mini Instruction and Ll decodes a TIX
at pin 9, enabling CTA and
1.
WW to be generated.
MERO
6309:
The value of the PC Register is loaded into the Program Counter.
2.
MOT
6310:
R
is low, gating MDT to generate CTA.
ll
6309:
RIO is low, and CTA is applied to the count up input of the Program
Counter (L36 pin 5).
The PC is incremented by one from the PC
Register data loaded at
3.
HERO.
MXS
6310:
MXS generates WW.
6309:
WW writes the Program Counter into the Auxiliary Register at the
)
address specified by R - R '
3
O
4-81
Transfer PC RegIster to Auxlilary Reglster, Decrement by l(TP-l)
ThlS Instructl0n IS Identlcal to the TP+l Instructl0n except RIO
LS now hlgh, applylng CTA to the count down lnput of the Program Counter,
decrementIng the value by 1.
Also, TP+2 and TP-2 are Identlcal to TP+l and TP-l respectlvely,
except CTA IS generated from MTF Instead of MOT.
Branch If Equal to Reglsters (BER)
The BER Inhtructl0n compares the reglster speclfled In the A Fleld
wHh the reglster speclfIed In the B Fleld.
If the reglsters are equal,
a branch wlll be made to the In page ROM address speclfled by the Y
Slnce only B bl ts are speclfled In the Y fleld, and there are
Fleld
16 bltS In the ROM address, only the low order bltS (IB and IA) are
changed by the Y fleld, effectlng an In page branch.
A typlcal BER
Instructl0n LS Hex B220C (10000010 0010 0000 1100).
6310
R
hlgh desables L33.
19
pLn 1.
R
low enables L34 to decode a '0' at
19
The ALU functl0n IS set to F=A<±lB, and FHG IS set hlgh,
,nlhl1n~
143 pin 1.
With R
low thL B BUh 1S selected from the register addressed
19
by
1~15
- R
12
(B FLeld) by L40.
for CO mputh.
B Bus '>elector //2 IS selected
The (0 Inputs are from the Flle Reglsters at the
Iddre% spenf1ed by R , R
and R
(Flle Reglster 3)
14
l3
l2
Reglster 3 1S applled as the A word to the ALU.
4-B2
Flle
The A Bus is also selected from the File Registers at the address
specified by R , R and R (File Register 1) and is applied as the
6
S
4
B word to the ALU.
If the A word does not equal the B word, the A=B output of the ALU
will remain low and the IC Register will be incremented to the
next address by MER.
However, if the A word and B word are equal,
the A=B output goes high, generating BRL.
ALU works in the following manner:
the function selected is
performed on the A and B input words.
word bits F
3
- F
O
The A=B output of the
If the resultant output
are all high, then the A=B output goes high.
The A=B output being active does not necessarily mean the A and B
Words are equal.
6309:
With BRL active, R - R and R
- R are loaded into the IC
O
3
ll
S
Register by MER.
)
The ID and IC words of the IC Register remain
unchanged, but the IB and IA words are changed to the new in page
ROM address.
In this example, the final IC Register value would
be XX2C.
6310:
In addition to BER being performed, the Instruction can also increment or decrement the PC Register.
Suppose the A Field (R
in the example is changed to 1110.
The A Bus is now selected
from the CL Register.
7
- R )
4
LIS pin 12 is low, enabling L7 pin 12 and
setting II active.
With R and R high, LS pin 8 and 9 are low, enabling L14 pin 4
6
S
and setting A active.
6308:
A and B set L4 pin 16 high and pin 4 low.
UDC.
4-83
MOT clocks L4, disabling
6310:
MXS is gated through L14 pin 5 to produce IC.
6309:
UDC prevents L41 from being loaded with L40.
IC increments the
value of L4l by one.
Branch if Not Equal to Registers (BNR)
This branch instruction is similar to the BER discussed above.
In this case, however,
are not equal.
the branch is executed if the registers specified
A typical BNR Instruction is Hex 932lB (1001 0011 0010
0001 1011).
6310:
L34 decodes a 'I' at pin 2.
The ALU is set for an
and FNHG is set high, enabling L43 pin 5.
F=A~
B function
If the two registers
selected are not equal, A=B is low, generating BRL to load the
branch address.
All other operations discussed in BER are the same.
Branch (B)
The Branch Instruction is an unconditional branch to the address
specified by the last 16 bits of the Branch Instruction.
A typical B
Instruction is Hex B195B (lOll 0001 1001 0101 1011).
6310:
R
high disables L31 and enables L34.
19
4 from R , R
and R , generating LB.
17
18
16
L34 decodes a '3' at pin
LB sets BRR and BRL active.
6309:
MER loads the IC Register with the ROM Instruction bits R
- RD.
15
The branch address loaded is Hex l59B.
4-84
Branch if True (BT)
TIle BT Instruction tests the register specified by the B field
wi th the ROM bits R - R (called the mask).
7
4
For each 'I' bit in the
mask, there must be a corresponding 'I' bit from the register for the
branch to be made.
If there are additional 'I' bits in the
they are ignored and the branch is made.
re~ister,
If a 'dummy' is selected for
the 'B' Bus, a NOOP (No Branch) results.
Example:
Hex CE513 (1100 1110 0101 0001 0011)
6310:
R
high disables L33 and enables L34.
19
L34 decodes a '4' at pin
5 from R , R
and R , generating FHG and setting the ALU for
18
17
16
an F=A + B (A OR B) function.
from the CL Register.
(R
)
7
-
The A word for the ALU is selected
The B word is the ROM Instruction mask
R )·
4
The ALU will perform the logic function on the input words, and if
the result produces an F
3
- F
O
output of 1111, the A=B output will
go high.
Suppose the CL Register contains 1011.
The mask bits are 0001,
which requires only the LSB of the register by a '1' for a branch.
The ALU performs an OR with 1011 and 1110 (8), with the result 1111.
The A=B output goes high, generating BRL.
6309:
MER loads L34 and L45 with the in page branch address XX53.
Suppose the CL register contained 1100.
OR wi th 1100 and 1110, resulting in 1110.
The ALU now performs the
The A=B output will
rem,t In low, <lnd no branch will be performed.
4-85
Branch if False (BF)
The BF Instruction is similar to the BT Instruction except and in
page branch will be made if the register bits compared with the mask
are '0'
for the corresponding 'I' bit in the mask.
Example:
Hex DB329 (1101 1011 0011 0010 1001)
6310:
R
high enables L34 to decode a '5' at pin 6, generating FHG
19
and setting the ALU for an
F~A
• B (A AND B) function.
The
B Bus is selected as follows:
6310:
R
low selects the A inputs to L40.
19
'B' Bus Selector #2 is
selected for C2 inputs from 'B' Bus Multiplexer bits BI
S
- BI .
I
The address for the B Bus Multiplexer is derived from L40 and is
all for b-4, b-2 and b-l.
6311:
The address for the B Bus Multiplex, L26 thru L29, selects
Status Register 2, L16, for input.
6310:
Status Register 2 is applied to the ALU as the A word.
The B
word, from R - R is 0010.
4
7
Suppose SR2 contains 1001.
with
,1
resul t of (Joao; the A • B result is 1111, causing the
output to he active.
A=I\
The ALU performs the A • B function
As with the other branch instructions,
high generates BRL, performing the in page branch.
4-S6
A~B
Suppose SR2 contained 1011.
The resultant AND function is 1101,
and no branch will be made.
If the B field specifies a 'dummy' the A word input will be 0000,
and a branch will be made.
Branch if Equal to Mask (BEQ)
The BEQ Instruction is identical to the BER Instruction except
the compare is done between a register specified by the B Field and the
A Field mask, instead of an A Field register.
Example:
Hex E6603 (1110 0110 0110 0000 0011) would branch to
Hex XX63 if the compare was equal.
Branch if Not Equal to Mask (BNE)
The BNE Instruction is discussed in machine cycle 121.
)
)
4-87
4.4.2
CPU I'OWER SUPPLY
There are six regulated supplies, each independently variable, in
the 2200 power supply.
All six are of the series pass variety, each
controlled by an IC voltage regulator.
There are four transformer
operated, full wave unregulated supplies which supply the necessary
voltage for the regulators.
The six regulated supplies are the +SVRL for the TTL logic in the
CPU, the +SVRM, +8VR, -12VR and -ISVR for the ROMs, PROMs and RAMs.
As
all regulators operate in the same manner, only the +SVRL will be discussed
here.
Ref"r to sC!lem<1tic L567 and Figure 4-20.
supply is the voltage regulator L4.
The heart of the regulated
The unregulated +14V is applied
to L4 pin 8 to provide the operating voltage for the IC.
output from a reference amplifier in the IC.
Pin 4 is an
The reference amplifier
contains a current source and temperature compensator to prevent drifting.
The output of the reference amplifier is applied to the voltage divider
network RI, R2 and R3.
R2 is adjustable and the voltage developed at the wiper is applied
to the non-inverting input of the error amplifier at pin 3.
By varying
the voltage at the non-inverting input, the output voltage will change.
Since the IC Regulator cannot supply large output currents, external
circuitry must be provided.
Pin 7 is the collector output of the internal
series pass transistor which provides the necessary drive for the first
driver transistor QS.
Q5 provides the necessary current for the second
driver Q8, which controls the series pass transistors Q6 and Q7.
The reguLlted output voltage is constantly monitored by the error
e>mplifier by applying a sample to the inverting input at pin 2.
regulation is performed
38
Voltage
follows:
If the output voltage tries to go positive, the inverting input at
pin 2 also follows positive, resulting in a more negative input to the
4-88
internal series pass transistor, causing it to conduct less, resulting
in a more positive voltage at pin 7 (the voltage drop across R4 is less
due to the decrease current, hence QS base tends toward +14V).
QS conducts
less, driver Q8 controlled by QS conducts less and finally the series
pass transistors conduct less, decreasing the output voltage.
In a
similar manner, the output voltage is increased when a negative output
change is detected.
Note that no regulation can take place unless
there is a change in the output voltage to initiate a correction, so
that the regulation is less than perfect.
The regulators also employ foldback current limiting as follows:
Resistors RS, R7 and R8 form the external current sensing network.
As the current in the external circuit increases, the voltage drop across
the sensing network changes, until a point is reached where the internal
current limiter transistor is turned on.
internal series pass transistor off.
The current limiter turns the
The output voltage drops to zero
and the output current remains at a safe value when the output current
exceeds the predetermined value.
capal:itor C8 compensates the internal error amplifier to avoid
instability.
As mentioned previously, all other regulator circuits
operate in the same manner.
Diode D2 connected between LS pin 1 and
Ll pin 1 prevents to +SVRM supply from ever becoming more positive than
the +8VR supply.
This is necessary to prevent damage to the MOS Memory.
Also diode Dl prevents the +8VR supply from rising above +14.2V, again
to prevent damage to the memory.
REGULATED DC
FIGURE 4-20 TYPICAL 2200 REGULATOR
4-89
4.4.
2LOO
A
MNI';MONIC~
Allows the PC Register to be incremented
or decremented at the end of an instruction.
A
15
- A
0
Output bits of the PC Register.
Output bits of the Data Memory Address
Register.
The Address Bus for I/O Devices.
Address Bus Strobe.
The address bits for the A Bus Source
Selector.
The clocks generated to load the four
sub registers that make up the PC Register.
b4, b2, hI
The buffered B Bus Source Selector bits
used as the address for the B Bus Multiplexer.
B
Allows the PC Register to be incremented or
decremented at the end of a register instruction
when a dummy register is used.
The four output bits of the B Bus Multiplexer.
BRH
Branch High.
Loads the eight MSB of IC
Register.
Branch Low.
Loads the eight LSB of the IC
Register.
Control Buffer Strobe sent to an I/O device
to request an input.
4-90
Carry Gate.
CAG
Allows Status Register 1 to
detect a carry.
)
CG
C Bus Gate.
Allows the C Bus to be applied
to and clocks to be generated for the various
registers in the CPU.
The four high order output bits from the
Data Memory Buffer.
The four low order output bits from the
Data Memory Buffer.
The Increment/Decrement clock for the
Program Counter.
CK
(see timing section)
CS
(see timing section)
CIO
Control Input/Output.
Allows input/output
strobes to be generated.
CPB
Indicates the CPU is Busy.
C Bus data output.
Used to decrement the PC Register.
DSC
Decimal Subtract with Carry.
a-
Buffered D
DIN
(see timing section)
)
4-91
D bits.
l
DAST
(see timing section)
Derived data bits from DI
DO
15
- 00
0
- DI '
O
Data Memory Output bits.
Error Gate.
ERG
3
Not used.
Used to detect a 'Branch if Equal' condition.
Used to detect a "Branch if Not Equal'
condition.
Halt
HALT/STEP from keyboard.
Input Bus data bit for Special Functions.
Input Bus data bits.
IC
Used to increment the PC Register.
ID8-1, lC8-1, IBS-I, IA8-1
The output of the IC Register.
Input Bus Strobe.
Indicates an unconditional Branch.
MER
MER
O
(see timing section)
(see timing section)
MOT
(see timing section)
MXS
(see timing section)
MTF
(see timing section)
4-92
MNT
(see timing section)
MHL
(see timing section)
Selects one of four Data Memory positions.
Output Bus data.
OBS
Output Bus Strobe.
Decoded to allow one of four PC Register
clocks, AT
PCG
4
- AT , to be generated.
I
Allows all four PC Register clocks to be
generated.
Active when a patch instruction has been
decoded.
Resets the CPU and I/O Devices.
The twenty bits that comprise the Instruction
Word.
Ready/Busy signal from I/O Devices.
Reset signal developed from PRMS.
REF
RESET
REL
SB
)
Allows the Data Memory to be refreshed.
(see timing section)
(see timing section)
Indicates a Subroutine Branch instruction
was decoded.
4-93
SR
Indicates a Subroutine Return instruction
was decoded.
51'
Clock for Status Register 1.
It
ST
ST
ST
Clock for Status Register 2.
2t
Clock for Status Register 3.
3t
Clock for Status Register 4.
4t
SKFN
Enables a Special Function to be input.
Iix
Indicates a register transfer or exchange
instruction was decoded.
TIP
Transfer IC Register to PC Register.
TMP
Transfer memory size to PC Register.
TPI
Transfer PC Register to IC Register.
TRAP
Generated when the power switch is turned
ON, to master initialize the CPU.
UDC
WTEN
The clock to load PCI.
4
- WTEN
I
Enables one of four sections of Data Memory
to be written into.
WW
Enables a write into one of sixteen Auxiliary
Registers.
4-94
SECTION 4
NOTES:
)
)
4-95
SECTION 5
USER TERMINAL & POWER SuPPLY HARDWARE OPERATION
5.1
VIDEO DISPLAY
The Video Display Unit provides visual interface between the 2200
CPU and operator.
The Display provides fast and efficient viewing of
programs and data stored in the CPU.
A Video Display Controller (located in a CPU I/O Slot) is used to
control display of dot matrix characters on a Cathode Ray Tube screen
(CRT) by providing video information and all required synchronization/
timing signals.
5.1.1
VIDEO DISPLAY PRINCIPLES
The Motorola Video Display Chassis electronics causes the electron
beam of the Cathode Ray Tube to scan from left to right across the CRT
Screen. Refer to Figure 5-2 for a basic explanation of how beam scan
is affected by the WANG I/O Controller. A more comprehensive timing
illustration is found in Section 6.
5-1
Each character row is comprised of
5 x 7 DOT CHARACTER MATRIX
.~:::::
!
ut SCAllU:n (mfaUA)
:,,<1
Sc.o., U'<l: (ClLI.aACTI:11lal'51
led
~CAlI
LIlli: (ClI.\ ....ctu DOTS)
'thSCAIILUlIICllAUCJU;Dots)
Hh SCAlI
!! I!:!!!!!:!!!:.
Ll~l
(otAMcn:a DOl'S)
~" SCAlI LIIlZ (0I.0U0CTn DllTS)
I'h SCAllLIIllt (CIL\&foClUDaI'S)
a'h5CA:l:LllIl(ClIUACfElDllTSI
,.bSCoUILUfl (IOOO'U....)
IO'h SCAlI
:::::::::::.::
~::::::::::::::===:
............................ - - . .
...................
un
(1 r:vasol
aon)
l\.bSt.ull,.tllI(lIOllA'r.\l
•••••••
0
'-
•••
MAGNIFIED
VIEW OF
CHARACTER
MATRIX
-----.
12tb SCAlI LIJQl (IIQ DAb)
lltloSGUlLDIC(IlOD.l.TA)
lU. SCAIILlJIl. (lIOtlLU)
UUO 5alIUIIII: (JIOWotA)
FIRST SCAN LINE
FIGURE 5-2
'FIELD'
16 CHARACTER
ROWS
256 SCAN LINES
LAST SCAN LINE
MAGNIFIED
VIEW OF
CHARACTER ROW
SCAN LINE 0
Jr:.HORlZONTAL RETRACE
__~""--,==,:,==-:="-==:",,:::,,,,:~=-=-,=-,,
_
- - - - - - 1-1=--=-=-==-=~="'=-=-=
_ ~~~~=-=-=:""=:"":!:"",:=-=-,=,,,,, 1-1=--=-=--=:-::~=-:=-=-=~~~_
~~~-=-=-=-=-=...: ..
~=-...:::...:::.."
::-:::-:=-==-=~=-=c-::::-=~~--
0-1
___~~=-=-=-=~L::=-':=--=-" 1-1=-=--=-=--=~=-:=-=-==
_
--~~:....==-==--:=--:=-~=--=-,="" '-=-=-=-=:-:!~=-==-=~~~---
-_::::::::::::~::::~~;. .~~~~~~~:' I,"=-:::-::::-=::-::~=-==-'=-~~--__
1 '-=--=--=-=~-=-=-=~~~
-~=--==-==--:=-=-=-=--=
..!...:=--=::"":=-'I '-=-=-=-=:-::j~::-::=-==-=~~~
__~~=-=-=-=-=~!:....:=--==-=_,1-1=-=--=-=--=~=-=="'=-==
__
_
-~~~=-=-=-=-=~!:....:=--==-=-, ''-::::-::'-:~=-~=-=-=-==-=~---~~~=-=-=-=-=:..='!
. .!:....:=--==-=""'I '-=-=--=:-:::-:~=-=-=-=~~~~ _
__~~~==-=-=:....;::!
..L::::....:=-=_"
.... -
,,--=:-::::-:~=-~=-=-=,-,==-=~
_
~~~::~::.::~::~:==-~~~~~~~-:::~~~~~~~:: :,. -=~= - = =:- -:= :-_-~= -:- -:=:!~!" - = =:-. .,~ _- = =-:-. .,~=S~C-!);AN=~ . .!~L: -I~NE~-. .;-=1~5C
~------
*HORIZONTAL RETRACE TO FIRST ,SCAN LINE OF NEXT CHARACTER ROW
*HORlZONTAL AND VERTICAL RETRACE ARE BLANKED (SEE TEXT)
5-2
fifteen scan lines and has 64 character positions available.
Using the
first character row as an example, the first scan line is blankAd; the
next spven scan lines contain character information; the ninth line in
the character row is blanked; the tenth is for cursor display.
The
remaining five lines contain no display data, and consequently appear
blank for adequate spacing to the beginning of the next character row.
The entire display, comprised of 256 scan lines is called a field.
Sixty fields are generated per second; therefore, all video data is
displayed 60 times per second.
This repetitive field generation cannot
be detected by the human eye and video display therefore appears to
be continuous.
When each scan line reaches the right-hand scan-line sweep limit,
the electron beam is quickly returned (retraced) to the left and the
starting position of the next scan line is reached.
At the right-hand sweep limit of the last scan line, the CRT electron
beam is retraced to the top left (starting point) of the first scan
line, thus beginning a new display field.
Since beam retrace is visually objectionable, the electron beam
is turned off (blanked) during both horizontal (scan line) retrace
and vertical (end-of-field) retrace.
Accordingly, these intervals are
termed horizontal retrace blanking and vertical retrace blanking,
respectively.
5.1.2
THEORY OF OPERATION
A simplified overall block diagram of the Display Unit is shown in
Figure 5-3.
The Display Unit consists of a Video Amplifier, a Sync Separator,
a Vertical Oscillator and Driver, a Horizontal Oscillator and Driver, a CRT
and Low and High Voltage Power Supplies.
)
5-3
Composite
Video Input
FIGURE 5-3 VIDEO DISPLAY UNIT
Refer to Motorola Schematics XM3:a and XM227 and the simplified
diagrams that accompany the circuit descriptions to follow; for simplicity
of explanation references to specific components apply to XM35l.
5.1.2.1
Video Amplifier
The video circuit is a wide band transistorized amplifier utilizing
up to four stages with a capability of 60 volts output for .5 volts input,
(2.5V PP Maximum Input).
On
some models the input impedance is switch
selected for 75 ohms terminated or l2KQ unterminated.
The high impedance
operation permits use of bridging connections to drive a number of
monitors from a common signal source.
The frequency response within is
3db from 10 Hz to 15 MHz and, depending on CRT type, is capable of up
to 800 lines resolution at the CRT center.
The first video amplifier (Ql) is an emitter follower.
It provides
impedance matching and couples the input to the low impedance load.
IlH pmltL<.'r reHIAtor HI)
ad1uAtahlC' Jow
IH .t
low
r<'~AtAtlln('(' conI rot
lmpe().,nc(· drlvp 91~n:ll wllhollt
COMPOS I
VIDEO
which provldpli 0111
the need for f n''!"PIIC Y
To CRT Circuit
FIGURE 5-4 VIDEO AMPLIFIER
5-4
compensation.
On composite video models,
sync information is removed
at the collector, and C3 provides high frequency roll off to limit the
collector bandwidth to the synchronizing signals (50/60 Hz vertical and
up to 20 KHz horizontal).
base biased.
CI provides DC blocking, permitting QI to be
The video signal is coupled from the contrast control by
C4 to the base of amplifier Q2 which is operated common emitter.
emitter of Q2 and base of Q3 are AC grounded by capacitor C6.
The
Bypass
capacitor C5 is used for frequency compensation increasing Q2 gain at
high frequencies.
The output is DC coupled to the base of the connnon
emitter stage Q4.
The output stages Q3 and Q4 form a Cascode pair which
is used in place of a single output stage to obtain a high gain bandwidth
by reducing the input capacity or "Miller effect".
As a result of an
increase in temperature, the emitter base drop of Q4 decreases, causing
an increase of collector current.
The forward drop of D8 and D13, both
silicon diodes, decreases with an increase in temperature.
This re$ults
in a lower base voltage for Q4, cancelling variations of Q4 collector
current with temperature.
The video bias control RIO is used to set
the quiescent collector voltage of the output stage.
DC restoration is accomplished by setting this control so the sync
tips, which are negative going at the collector of Q3, just go into saturation.
Variations in the video drive will result in variations of Q2 base current
during sync time due to the low load reflected back to Q2 when Q3 is saturated.
The charge on C4 will depend on the amplitude of Q3 collector current
during sync time.
The result is a clamping action which holds the sync
tips at a constant level despite video input signal variations.
The out-
put is DC coupled to the CRT through Rl8 which isolates the output stage
from transients should they occur as a result of CRT arcing.
and Rl5 are used for high frequency compensation.
)
5-5
C5, C7, C8
5.1.2.2
Sync Separator
The function of the sync separator is to receive the composite
video signal and separate the sync pulses, discarding all other information.
When a signal is applied to the base of Q5 it is driven positive
causing current to flow from emitter to base, charging Cll.
As the in-
put signal drops, a charge remains on Cll because its only discharge path
is through the high resistance of R24, since the transistor is cut off at
this time and its base has stopped drawing current.
When the next sync
pulse arrives it must overcome the residual charge voltage on ell which
is holding the transistor in cutoff.
Between pulses some of the charge
will be lost,through R24, but it is somewhat less than the height of
the sync pulse.
The amount of charge lost by Cll will determine when
the transistor is turned on.
Q5 conducts only when Cll is charging,
while video information is blocked by Cll's residual voltage which is
holding Q5 in cutoff at that time.
The charge amplitude depends on
the peak to peak input to Q5 and thus makes the bias for Q5 track
the amplitude of the input signal, allowing only the positive peaks
(sync pulses) to be amplified.
Composite Video
~L....
S
Sync
, eparator
....J~TTOO
Horiz. Phase Det.
Vertical Oscillator
Clipping Level
Recovered Sync--__~~~
FIGURE 5-5 - SYNC SEPARATOR AND WAVEFORM ANALYSIS
)-6
5.1.2.3
Vertical Oscillator
The function of the vertical oscillator is to provide the vertical
sweep frequency to move the beam from top to bottom.
At the output of
the vertical oscillator, a pulse shaping network is incorporated that
will develop the required waveform.
This waveform is then applied to
subsequent stages that amplify and apply it to the vertical deflection
coils to scan the electron beam vertically.
Blanking
Sync
lnpvt
Vert. Drive
FIGURE 5-6
VERTICAL SWEEP
QlO and Qll are connected as a regenerative switch; bias is supplied
from the voltage divider R56, R55, R82 and R50.
The vertical hold control
will vary the bias on the base of Q10, thus allowing an adjustment of its
frequency.
In the free running condition capacitors C37 and C38 charge
through R58 and D3.
The oscillator is held in cutoff at this time by the
bias on QlO, and the CRT is being scanned vertically from top to bottom.
At the bottom of the raster the charge is of sufficient amplitude to forward
bias Q10 on.
Its collector current develops a positive pulse across R57
which forward biases Qll on, developing a negative pulse at the base of Q10,
driving it into saturation.
Its collector/emitter resistance is reduced
to a fraction of an ohm discharging C37 and C38.
This initiates vertical
retrace and forces the beam back to the top of the CRT.
Note that the charge
path is through a high resistance during trace allowing a relatively long
scan time; but discharge is through a low resistance during vertical retrace.
The discharge causes Q10 emitter to become less positive, decreasing
its collector current, biasing Qll toward cutoff.
Qll's collector voltage
rises positive and reverse biases Q10, allowing the capacitors to charge
again, repeating the sequence.
Sync from the collector of Q5 is integrated
by R26 and C35 and applied to the free running oscillator.
)
forward biases QlO, synchronizing the oscillator frequency.
5-7
This prematurely
C38, C37 and
RSR form the pulse shaping network that develops the required sawtooth waveform.
CJf>
fllter~
thl'
'.Jwtooth from the power
feedback load resistor.
~upply.
H~7
IH the
common
L2 in conjunction with C37 and C38 determine the
on time of the oscillator.
R54 is used for damping.
D3 provides a small
incremental voltage above ground to overcome the forward base/emitter drop
of the following stages.
5.1.2.4
Vertical Driver and Output
The task of the vertical amplifiers is to increase the level of
driving signal generated by the vertical oscillator to a level which is
sufficient for driving the vertical deflection coils.
A sawtooth of
voltage must be applied to the vertical output transistor to produce a
sawtooth of current through the vertical deflection coils to achieve
vertical deflection.
The vertical driver, Q12, is an emitter follower which transforms the
high impedance input to a low impedance drive for the vertical output.
Q13
amplifies the vertical sawtooth output current waveform from the oscillator.
Q13's output current waveshape is used to drive the yoke L5 through transformer T3.
voltage.
R61 limits the dissipation of Q12 by reducing average collector
R63 is the emitter load resistor for Q12.
DC coupling is
employed from the vertical oscillator to the vertical output.
R64" and R65 set the current gain of Q13 with R65 (vertical size)
adj ustable.
When the driving signal at the base of Q13 goes negative, vertical
retrace will be initiated. At the instant of vertical retrace, a high
positive pulse is introduced to the collector of Q13. During the time it
was turned on, a large magnetic field was built around T3 and the vertical
deflection coils, then when Q13 is cut off, this field collapses and causes
a large self-induced voltage to be produced in the form of a positive pulse
at the collector.
5-8
C39 increases turn off time of Ql3 reducing the amplitude of the
positive pulse at its collector.
Additional pulse limiting is provided
by a VDR (Voltage Dependent Resistor) R8l, across the primary of the
vertical output transformer.
The resistance of the VDR varies inversely
with the voltage across it thus further limiting the positive pulse on
the collector of the vertical output transistor to a safe value.
Since the primary impedance of T3 decreases with current, the degree
to which the primary shunts the reflected load impedance will vary with
collector current,
resulting in vertical non-linearity, stretching the
top and compressing the bottom of the raster.
In order to counteract thiS,
a concave sawtooth is applied to the base of the output transistor.
Results
Waveform
~
~
~
Vertical drive
I without parabola
~
Parabola at junction of C37/C38
~
~
~
~
Parabola and drive
added
I waveforms
FIGURE 5-7 - VERTICAL WAVEFORM ANALYSIS
To develop this waveform, a portion of the vertical sawtooth in the
emitter circuit of Ql3 is coupled back to the wave shaping network C37
and C38 via R59 (vertical linearity control) and R60.
C38 combines this
sawtooth to the sawtooth developed by the oscillator producing a parabola.
The amount of parabola added to the sawtooth waveform is governed by the
setting of the vertical linearity control.
An additional feedback path
through R62 and C40 serves to optimize the drive waveshape for best
linearity.
~)
R66 and C41 provide damping to shape the collector pulse so it may
be used for retrace blanking.
5-9
The horizontal oscillator is used to generate a signal to drive the
horizontal deflection coils and ultimately sweep the electron beam from
left to right across the face of the CRT. It is susceptible to false
triggering by noise because its synchronizing pulses are selected by a
process of differentiation, and differentiators are high-pass filters.
Thus, any noise which passes through the sync separator would be applied
to the oscillator resulting in instability.
To insure operation on the
correct frequency and immunity to noise, the oscillator is controlled by
an automatic-frequency-control circuit (AFC).
Correction
Voltage
Sync Input
Pulse Input Sample
from Horiz Output
FIGURE 5-8 HORIZONTAL OSCILLATOR AUTOMATIC FREQUENCY CONTROL
The AFC phase detector is a keyed clamp circuit.
Its function is
to develop a control voltage for synchronizing the horizontal oscillator
with the incoming sync pulses.
If the oscillator deviates in phase with
respect to the sync, a correction voltage (proportional to the amount the
oscillator deviated) is developed and applied to the oscillator, pulling
it back in phase lock with sync.
Two inputs are required to generate the required output, one from
the sync separator and one from the horizontal deflection system.
R27 and Cl3 are used to couple the horizontal sync into the phase
detector.
The capacity of Cl3 is made small so as to differentiate the
vertical serrated sync pulses, thus coupling only horizontal sync to the
AFC network.
C32, C23, R4S and CIS integrate and couple a positive pulse
from the horizontal output transformer (this pulse is a representation
of the oscillator frequency) into the phase detector for frequency comparison with the sync pulse.
5-10
To explain the operation of the AFC circuit, begin with sync separator
stage (QS).
-)
Prior to the arrival of the sync pulse at base of QS, it is cut
off and has a high collector voltage.
Since Cl3 is connected to the collector
of QS, it will be charged up to nearly the supply voltage.
turns on the sync separator,
When a sync pulse
its collector voltage decreases.
Cl3 will now discharge coupling the sync to the cathodes of DI and D2.
This voltage will forward bias both diodes (DI and D2) into conduction, shorting CIS to ground.
The sawtooth on C15 is thus clamped to ground at sync time.
If the
horizontal time base is in phase with the sync, the sync pulse will occur
when the sawtooth is passing through its AC axis and the net charge on CIS
will be zero.
(Figure S-9B)
If the horizontal time base is lagging
the sync, the sawtooth on CIS will be clamped to ground at a point negative
from the AC axis.
(Figure S-9C).
This will result in a positive DC charge on CIS
This is the correct polarity to cause the horizontal
oscillator to speed up to correct the phase lag.
Horizontal Syn Reference
A
B
C
Ov
Ov
o
-1~~-i~~Oscillator freq.
correct;
no correction voltage.
Oscillator slow;
correction voltage.
~--~~---Pos.
Ov
Oscillator fast;
negative correction voltage.
FIGURE 5-9 - HORIZONTAL OSCILLATOR
FREQUENCY CORRECTION
Likewise, if the horizontal time base is leading the sync, the sawtooth on CIS will be clamped at a point positive from its AC axis, resulting
in a net negative charge on CIS which is the required polarity to slow the
horizontal oscillator (Figure 5-90).
the phase detector filter.
)
R30, C23, CIS and R4S comprise
The bandpass of this filter is chosen to
provide correction of horizontal oscillator phase without ringing or
hunting.
5-11
5.1.2.6
Horizontal Oscillator
The horizontal oscillator acts like a switch turning on and off at a
predetermined rate.
The base of Q6 receives a DC voltage from the AFC to
keep the oscillator locked in phase and frequency with the transmitted sync.
The oscillator frequency is sensitive to base input voltage changes.
This permits control by both the AFC output and setting of the hold control
R34, while oscillator range is set with the core adjustment of Ll.
From AFC
To Hariz Output
FIGURE 5-10 HORIZONTAL OSCILLATOR
The horizontal oscillator is similar to a Hartley Oscillator with
a tapped oscillator coil, Ll, in its emitter circuit which sustains
oscillation.
The main frequency determining components are Ll, C18,
C19 and R36.
The output of the oscillator is a 22% duty cycle square
wave.
This waveform is produced by the abrupt switch on, to saturation,
and off, to cutoff, of the horizontal oscillator transistor.
This
unsymmetrical square wave is not quite suitable for switching (or driving)
the horizontal output transistor and must be applied to the Horizontal
Pulse Shaper first.
5.1.2.7
Horizontal Pulse Shaper
This stage is incorporated to insure that a more perfect square
wave is applied to the Horizontal Driver.
The pulse shaper, Q7, achieves
the shaping by being driven into saturation and cutoff by the existing
driving signal on its base.
This squares the waveform by clipping off
the top and bottom portion.
The base of Q7 is directly coupled to the collector of the oscillator.
Therefore, the collector voltage of the oscillator will apply bias to Q7.
Since the emitter of Q7 and the collector of the oscillator both return to
the +30 volt supply, Q7 will stay in cutoff until the oscillator transistor
5-12
turns on and forward biases it.
of Q7.
R39 is used to raise the input impedance
C20 increases the conduction of Q7 to 50% by holding a charge posi-
tive at the base of Q7 after Q6 turns off.
R4l is a collector load resistor
for Q7 and base load for Q8.
5.1.2.8
Horizontal Driver
The function of the driver is to amplify the existing driving signal
from the pulse shaper to a power level sufficient to drive the horizontal
output transistor.
Forward bias is applied to the base of the driver, Q8, by DC coupling
from the collector of the shaper, Q7.
The driver will follow the oscillator
as it has no forward bias when the oscillator is cut off.
When the oscillator
conducts, its collector current will turn on the shaper and the driver.
The output of the driver is coupled into a driver transformer (Tl).
When the driver is driven sharply into cutoff, the primary winding of Tl
and its stray capacitance ring because the driver stage unloaded the circuit
and allowed the "Q" of it to rise.
This ringing could exceed the collector
to emitter breakdown voltage of the horizontal driver.
To prevent this un-
desirable condition, a damping resistor (R42) and series capacitor (C2l)
are placed across the primary of Tl to lower the circuit "Q".
This keeps
the tuned circuit loaded even when the driver cuts off, preventing
oscillations from occurring on the driving signal.
C22 and R43 decouple
the driving signal from the 73 volt supply.
The driver transformer (Tl) has a turns ratio of approximately 30:1
with the voltage stepped down and current stepped up.
This transformer
provides current step up and coupling to the base of the horizontal
output transistor.
5.1.2.9
Horizontal Output
A simplified diagram of the horizontal output showing collector
)
current when the output transistor Q9 is turned on is illustrated below.
5-13
II
'~Cro:~RIlE-NT
'"
01
HORII
OUTPln
QA.MPUI.
C2ll
-i
_Il
DQ1COll:i
I
I
t
•
I
L. __ •
I
.J
+------1111
1+
+7>1
FIGURE 5-11
HORIZONTAL OUTPUT
This stage must be capable of developing both a sawtooth of current
through the horizontal deflection coils and a high voltage pulse for the
high voltage rectifier (not shown).
In order for a transistorized horiz-
ontal output stage to perform these functions properly, it must be driven
with a square wave of voltage.
is almost purely inductive.
A square wave is needed because the circuit
The circuit is virtually absent of resistance
because the output transistor, Q9 exhibits only a fraction of an ohm when
driven into saturation by the driving signal.
Since the only impedance
left in the circuit noW is the yoke and flyback (high voltage transformer),
the circuit is primarily inductive.
Q9, the horizontal output transistor, is simply a switch which is
turned on and off at a horizontal scan rate by the driving signal applied
to its base.
Shown with respect to time, Figure 5-12 shows the Horizontal
Output Waveforms, Figure 5-l2A the driving signal applied to base of Q9,
Figure 5-l2B current through deflection coils, Figure 5-l2C pulse appearing
on collector of Q9 during retrace and Figure 5-120 CRT scan relative
to time.
Figure 5-12A shows the drive voltage applied to the base of Q9.
From T1 to T2, the input signal turns on Q9 and drives it into saturation.
In this oondition, the emitter/collector resistance is reduced
to a fraction of an ohm, thus simulating a closed switch.
During this
time Figure 5-l2B illustrates the flow of current from zero to maximum through the yoke (horizontal deflection coils) in a direction to
move the beam from the center of the screen to the right side.
5-14
)
A.
B.
'HLi'rll
Horizontal drive
signal(Q9 base)
III i
I
i
. i.
Current through
def lect ion coil
H
"
D.
C.
'
0
.
Horizontal output
"
IS
CRT beam scan with
relation to ti~e.
signal(Q9 collector)
o
damped
FIGURE 5-12 - HORIZONTAL OUTPUT WAVEFORM ANALYSIS
At T2, Q9 is driven sharply into cutoff, thereby initiating horizontal retrace.
Between T2 and T4, Q9 is driven into cutoff, and the
current supplied to the deflection coil ceases.
However, an induced volt-
age appears across the deflection coils as the magnetic field collapses
and an oscillation then occurs between the deflection coils and C28.
The
damper diode, Dl, then conducts on the negative ring of this oscillation
and the beam is returned to the center of the screen at a linear rate.
It is important to note here that Q9 conduction causes scan which
starts at the CRT center and moves to the right edge and damper Dl
conduction causes scan from the left edge to the CRT center.
From T2 to T3, the direction of curren t through the yoke is shown
in Figure 5-l2B.
During horizontal retrace, the current rises to
a high value in the reverse direction causing retrace which quickly
returns the beam to the left side of the screen.
Then, from T-3 to
T-4, the yoke current gradually decreases to zero during damper conduction allowing the beam to return to the center of the screen.
J
The beam movement relative to time is illustrated in Figure 5-12D.
5-15
From T4 to TS, Q9 is turned on by the driving signal on its base,
thus causing current to rise (Figure 5-12B) at a sawtooth rate.
This
rising current produces an increasing magnetic field in the yoke which
will deflect the beam from the center of the screen to the right side.
When the beam reaches the right side of the screen, Q9 is abruptly
cut off causing retrace and again, repeating the sequence of events.
Figure 5-12C indicates the collector voltage waveform of Q9.
The instant Q9 is switched off, the collapsing magnetic field produces
a positive pulse.
This pulse is stepped up by the flyback transformer
(not shown) and rectified to produce the required high voltage to
accelerate the CRT beam toward the screen.
Transistors require bias to turn on and, note, the horizontal output
stage has no DC voltage paths to its base to form the required emitter/base
forward bias for turning on.
Q9 will turn on only when the driving
signal on its base is positive enough to forward bias it, therefore,
no harm will be done to the horizontal amplifier stage in the event of
lost drive.
The secondary of Tl provides the required low drive impedance for Q9.
R44 and C24 form a time constant for fast turn-off of the base of Q9.
transition of time between saturation and cut off is very critical.
The
If this
time is too long, the maximum collector dissipation would be exceeded.
To
alleviate this undesirable condition, this network is incorporated in the
base circuit.
Q9 operates as a switch which, once each horizontal period, connects
the supply voltage across the parallel combination of the horizontal yoke
and the primary of T2.
The required sawtooth of deflection current through
the horizontal yoke is formed by the L-R time constant of the yoke and output transformer primary.
The damper diode, Dl, conducts during the period
between retrace and turn on of Q9.
pulse limiter/boost rectifier.
A second diode, D2, is employed as a
The horizontal retrace pulses charge C27
through D2 providing a DC supply voltage for use at the CRT.
Should moment-
ary transients appear at the collector of Q9 they will be limited to the
voltage on C27 since D2 will conduct i f the collector voltage rises to this
value.
5-16
C28 is used to tune the retrace pulse to the proper frequency.
is charged through D5 developing the video output supply voltage.
C43D
D4 serves
as the high voltage rectifier supplying the DC voltage for the CRT 2nd anode.
The capacitance of the CRT is used to filter this voltage.
Since the low
side of the deflection coils are connected to ground, a capacitor, C29
is in series with the yoke, blocking the DC voltage which would decenter
the raster.
The linearity of scan is critical in a monitor due to its application
in reproduction of a fixed image.
Two circuits are included to control line-
arity and width of the horizontal sweep.
and in series with the yoke.
The width coil L4 is adjustable
By changing the inductance of the width coil
the amount of deflection current flowing through the yoke is varied and the
raster size (scan without picture information) changes in a horizontal
direction.
The linearity coil L3 is a factory adjusted, magnetically biased
coil which shapes the deflection current for optimum trace linearity.
If
the yoke was a pure inductance, a sawtooth current through it would be
adequate.
However, to compensate for its internal resistance, the linearity
coil reshapes the sweep current to compensate for system losses which could
cause right side compression.
C3l, R49, C42 and R68 are the damping network
components for the linearity and width coils.
5.1.2.10
Retrace Blanking
The blanking function disables the CRT during retrace, which occurs
at blanking time when video information is not being received.
As a result
of this action the vertical and horizontal retraces are not observed.
Both
vertical and horizontal retrace blanking are provided by pulses applied to
Vertical Output
To CRT
Horiz Output
FIGURE 5-13 BLANKING CIRCUIT
)
5-17
the CRT.
The collector pulse from the horizontal output transistor is placed
across R23 through R46.
The vertical collector voltage is differentiated by
C30 to remove the sawtooth portion of the waveform.
appears across R23.
The remaining pulse
The mixed vertical and horizontal pulses on R23 are
coupled to the CRT cathode by ClO.
5.1.2.11
Power Supply (73V Version)
Two basic power supplies are used in Motorola Display modules: a 73V
supply for large screen (12 inch) applications and a l2V supply for
small screen (9 inch) displays.
The power supply is a transformer operated, full wave, regulated supply
which maintains constant output voltage with input variations of ±15%.
A
switch (SWl) is provided to allow operation from 115 or 230 volts, 50/60 HzAC.
The regulator is a series pass circuit.
Q16 is the series pass transistor,
Q15 the reference amplifier and Q14 the output driver.
The output voltage of the regulator appears at the emitter of Q16.
This voltage is divided between R7l, R74 and R73.
The voltage appearing
on the arm of potentiometer R74 is a reference input to the base of Q15.
A temperature compensated Zener diode (D6) is used to establish
a fixed reference voltage at the emitter of Q15.
R72 provides a bias
current for D6, establishing its operating point.
Unregulated DC
B+
FIGURE 5-14 POWER SUPPLY
5-18
An increase in output voltage results in an increase of voltage at
the base of Q15.
Since the emitter of Q15 is held at a fixed reference
voltage, the change in base voltage will turn Q15 on harder, reducing its
collector voltage.
This reduces forward bias for Q14 resulting in less
emitter current and less base current for Q16.
Q16 will conduct less,
lowering the output voltage.
R79 provides a shunt current path for Q16 allowing it to run
cooler, improving reliability.
5.1.2.12
C44 is an RF noise filter.
Power Supply (12V Version)
Operationally the 12 volt supply is similar to the 73 volt version
just discussed.
The IC replaces the temperature compensated Zener diode, reference
and regulator driver circuitry.
The IC operating voltage is supplied by
diode Dl05 and capacitor ClOl and the power transformer winding.
)
5.2
THE TAPE DRIVE UNIT
The Tape Drive Unit is used in the 2200 System to store data or
programs from the CPU memory onto a cassette; this data can be read
back into the CPU memory when required, providing a convenient method
of mass storage.
Data Out
Strobe
J
----1;;:;;:;;--,
-----1~~~J
FIGURE 5-15 - TAPE DRIVE UNIT
5-19
5.2.1
THEORY OF OPERATION
Refer to the simplified block diagram in Figure 5-15.
5.2.1.1
Input Decoder
Information pertaining to Track 0 and Track 1 Data, Head In or Out,
Speed, Direction, Record Current On or Off, and Motors On or Off is sent
by the CPU to the Input Decoder.
The Input Decoder generates the signals
necessary to perform the tape drive operations and also checks the status
of the clear leader, rewind and reset.
5.2.1.2
Signal Conditioner
During a write operation, the Signal Conditioner changes data from
the 2200 to a form that is required by the tape head.
During a read opera-
tion, the Signal Conditioner changes the data from the tape head to a form
that can be used by the 2200.
5.2.1.3
Take-up Motor Control
The Take-up Motor Control determines which take up motor is to be
used during a read/write, and rewind operations; it also controls
braking signals for these motors.
5.2.1.4
Direction Control
The Direction Control determines the direction of the tape during
read and write operations.
The Direction Control Decoder energizes
the forward or reverse pinch roller solenoids to move the tape in the
required direction.
5.2.1.5
Output Buffer
The Output Buffer provides the Track 0 and Track 1 data signals for
the CPU and generates a data strobe for the CPU from these data signals.
5.2.2
DETAILED THEORY OF OPERATION
Refer to schematics L558, L559 and 6175, where applicable.
5-20
5.2.2.1
Input Decoder (L558)
When the I/O controller for the tape drive is selected, GION is active.
This removes the clear from latch L12 and resets MMV L9, which resets latch
L7 and removes the clear from L5 pin 13.
When L7 is reset, the clear is re-
moved from L13, and Lll pin 9, L8 pin 5 and L6 pins 2 ;md 12 are enabled.
At the time the CPU generates OBS, DSTB clocks data GB
I
- GB
8
through
L12 and L13 to be used to control tape drive operations:
5.2.2.2
Tape Forward Operation (LOAD, SAVE, SKIP)
During a Forward operation, L12 pins 3 and 6 and L13 pin 10 are high,
and all others are low.
L12 pin 15 is high only during SAVE.
L12 pin 11 resets L5 pin 7 and causes L6 pin 11 to go high, enabling
16 pin 10 and L7 pin 5.
L12 pin 6 causes L6 pin 3 to go low, leaving PACR
and NACR inactive, and setting L6 pin 8 low, enabling NACF and PACF.
causes the Forward take-up motor to turn.
enables L8 pin 13 and disables L2 pin 1.
This
At the same time, L12 pin 6
Since L13 pin 10 is high, L7 pin
6 is low, causing L8 pin 11 to go high, energizing the forward pinch roller.
With both of the above operations occurring, the tape is moved forward and
taken up on the forward take-up reel.
At the end of the forward operation,
L12 pin 11 goes high, causing L6 pin 11 to go low.
This disables NACF and
PACF, (turning off the forward take-up motor) triggers MMV L5 pin 5 and
triggers MMV L5 pin 12.
MMV 15 pin 9 goes low for approximately 15 msec
to keep the forward pinch roller energized while MMV L5 pin 7 enables NACF
and NACR to apply a braking force to the tape by turning on both the
forward and reverse take-up motors at half speed.
This series of events
is necessary to prevent the tape from moving when the forward (or reverse)
operation has ended.
5.2.2.3
Tape Reverse Operation (BACKSPACE)
During a Reverse operation, L12 pin 3 and L13 pin 10 are high, and
)
all others are low.
L12 pin 12 low enables L2 pin 2 and L6 pin 4, and
disables L8 pin 13.
L6 pin 11 high sets PACR and NACR active and L2 pin
3 low.
The reverse pinch roller allows the tape to move in the reverse
direction and the tape is taken upon the reverse take-up reel.
5-21
The tape
motion'is stopped at the end of the operation in the same manner described
for a Forward operation.
5.2.2.4
Rewind
During Rewind (from CPU) L13 pin 11 is high and all others are low.
L6 pin 6 is low setting PACR and NACR active, causing the reverse take-up
motor to turn.
L12 pin 3 low sets GHS active, to turn the take-up motor
at high speed.
When the clear leader is detected, LOP goes high, sending
LOP to the CPU.
The tape is then deselected by the CPU, GION goes high
and clears latch L12.
L2l pin 3 high sets GHS inactive, taking the
reverse motor out of high speed.
L12 pin 6 high disables PACR and NACR and L12
pin 11 high triggers MMV L5 pin 5.
active.
approximately 100
5.2.2.5
L5 pin 7 goes low, setting NACR and NACF
Both Forward and Reverse Motors are turned on at half speed for
~sec
to apply a brake to the tape.
Power Driver (L559)
The Power Drivers turn the Forward and Reverse Take-up Motors.
One
side of the motor is connected to M while the other side is connected
x
to an AC voltage.
When the NAC and PAC signals are active, transistors
Q3 and Q4 (or Ql and Q2) are turned on.
The positive portion of the AC
signal is conducted through the motor through D4 (or Dl) and Q3 (or Q2)
while the negative portions conduct through D3 (or D2) and Q4 (or Ql).
5.2.2.6
Speed Control (L559)
During normal operation, GHS is inactive.
In this mode of operation,
a resistor is connected in series with the motor to ±OV.
is indicated, GHS goes low, turning on Q5 and Q6.
When a Rewind
This places HLC effectively
at ±aV, removing the series resistor from the circuit and causing the
motor to turn at a higher speed.
DA1A TO rE lo.'RITTE1\
TRACK 1
TRi\CK 0
FIGURE 5-16 DATA FROM CPU
5-22
Signal Conditioner (6175) & Output Buffer (L558)
5.2.2.7
To insure that all data is read correctly, a ewo track system of NRZ
recording is employed.
Track one produces a flux change for a binary
"one " while track zero produces a flux change for a binary "zero " of
CPU data.
The data cannot be written on tape in this manner, of course, and
is converted to an analog current pulse by the Signal Conditioner.
The digital signal for track 0 is applied to the push-pull amplifier
Ql, Q2, Q5 and Q6 (or Q3, Q4, Q7 and Q8 for track 1).
When the digital
signal changes from a 1 to 0 or 0 to I, a change in the direction of the
current through the head winding results.
This change of current causes
a reversal in the direction of the magnetic flux in the recording head.
As shown in Figure 5-17,
the magnetic lines of force in the head bridge
the head gap through the magnetic tape.
the moving tape.
As the tape moves,
The tape head is in contact with
the magnetic particles which constitute
its oxide coating are magnetized and create small magnets in line with the
direction of tape motion.
)
The polarity of these magnets is ultimately
determined by the direction of the current in the head winding.
When the
direction of this current changes, so will the polarity of the magnets, thus
creating a succession of these, with the North poles of one next to the
North poles of the next.
I'AGNETIC TAPE
1
0
DATA
0
1
! ...Jr-;;..;......;..,;C::U~RR!!E!!NT!....!!TH~R~OU!!!G~H2H!IEA~Dur---;;..;.---1.I
5)
)
MAGNETIC TAPE
J
c;
TAPE MOTION
FIGURE 5-17 MAGNETIC TAPE RECORDING
5-23
1
.Jr-----..
~
0
TAPE MOTION
G
TAPE MOTION
~
~
S-N TO N-S TRANSITION
N-S TO S-N TRANSITION
FIGURE 5-18 TAPE DATA SENSING
The read
p~ocess
is the opposite of the write process described above.
As the tape and its magnetized portions move past the head, lines of force
are induced in the head; when the magnetism changes direction (N + S to
S + N), so do t'1e lines of force.
Each change is translated into a pulse
in the tape head winding, in much the same manner as in a transformer.
If
a N-S to S-N tape transition induces a negative going pulse, a S-N to N-S
transition will induce a positive going one (8ee Figure 5-18).
When reading data, alternate positive and negative-going pulses
are generated as the magnet boundaries are crossed.
The data written
on track 1 in Figure 5-14 would be read back as shown in Figute 5-20.
This signal is amplified by L7 (or L8) amplifier and applied to the
pulse shaping network of Q10, Q11, Q9 and MMVs L1 and L2, producing a
40 usec digital pulse for every flux reversal on the tape (Figure 5-21).
The LTCK and LDK signals read from Track 0 and Track 1 are applied
to the Output
B~fer
and Clock Generator, L1 and L9 (L558).
The signal
from each track is gated through L2 to trigger MMV L9 and develop an 11
usec clock signal to strobe the buffered data into the CPU.
Since there
is always a signal on either Track 0 or Track 1 (but never both), one
clock pulse for each data signal is generated as shown in Figure 5-22.
5-24
1
II
II
1
1
1
tJ
1
FIGURE 5-20
FLUX TRANSITIONS
-N
N
1
S S-N N-S
rI
I'l
1
1
S-N
1
III
N-
1
RESULTING DATA
FIGURE 5-21
1
I'l
I'l
1
1
1
I'l
1
TRACK 1 DATA
FIGURE 5-22
TRACK
I'l
DATA
CLOCK GENERATION
CLOCK SIGNAL
)
5-25
THIS PAGE INTENTIONALLY LEFT BLANK
5-26
SECTION 6
CPU INPUT/OUTPUT CONTROLLER CIRCUIT BOARDS
HARDWARE OPERATION
6.1
INPUT/OUTPUT DEVICE SELECTION
6.1.1
INTRODUCTION
Whenever a peripheral device Input/Output Controller is to be accessed
by the CPU, it is addressed, and an acknowledge signal is sent back to the
CPU indicating that the controller is ready for use.
I/O device may be selected at one time.
Only one peripheral
This address/selection is controlled
by the user's program via the 2200 Microcode.
All I/O controllers are
addressed and subsequently "selected" in the manner described in paragraphs
to follow.
Although there are hardware differences between various controllers,
all are composed of three basic sections:
Select Latch, and a Ready Busy Decoder.
same for all controllers.
6.1.2
an Address Comparator, a
The select operation is the
Refer to Figure 6.1.
ADDRESS COMPARATOR
The Input Comparator compares the data on the Address Bus AB - AB
1
S
with the settings of the address switches located on the controller.
When the data and switches have an equal value, the output of the Input
Comparator changes from low to high.
......
..,
FIGURE 6-1;
1/0 Device Selection
( .1. 3
( OlllJl I
ll/( I
t
III
r
It
I
or
I(
1111(1/
I I
I
It (11
{I ()( 1 t I
I
h 1) II,
(llll pill
t IJ
ry Al
(VI
{llltl til
d
I IIllI
(I ( (r
till
Iy
1I11t11 1111011
b\l~Y
!lC'lodC'r
f.1.4
I It
Ippilid
w II I
1,1111
I(
I
lei
/
Input.
mAIJi/EII'}
meOD/II
I.hen the controller 1S selected (Select I atch set), the Rc,luy/Busy
Decoder w1ll lnd1cate Ready (act1ve low) to the CPU only d
the per1pheral
The Ready IndIcator wIll stay actIve
deV1ce 18 not dOlng an operatIon.
untIl the perIpheral devIce beIng used generates a Busy IndIcator,
allow1ng the CPU to do another I/O operatlon.
Normally, the uevlcP belng
(eml
used wlll generate a Busy lndlcator after the I/O Bus
-
Of,,)
has
hpen strobed hy OBS, the CPU OlltPllt strohe.
6.2
VI)I 0 illS!'] AY CONr,W] J II,
6.2.1
(J
VIIU1J
r/lL()F?Y OJ
OJ I rllTT()N
lhe LlHory 01 operltl0n lor thL vldlO dl'-.pL-lY controll( r
plall1pd 'lnd 11111str,qtpd In till
6.2.1.1
followlnf
rlrl~
I . . . <x-
r'lph<.,o
1 Lmlll!'
\Jl llPllng IS derIved frol1l
~.6
111
'1H?
C.... pprox.)
(l
Lll1 !tor.
thL
oscIllator frequency has a perIod of one-seventh 01 one (II IT ll.U r.
osc11lator clocks a
d1v1de-by-s~ven
J
he
r1ng counter wh1ch generates t1ID1ng
at character t1rnes.
6.2.1.2
!)pV1ce Se1ect10n anG Data Input
lhe Input 11ecoder
a control funct10n.
deter~lne~
lf the data 1S a prlntable cllaracter or
Refer to paragraph 6.1 for a descrlptlon of uev1ce
~p1pct10n.
6.2.1.3
(loLl
)0CO<!PT
l.JlIPn a pr1ntab1e character lS recPlveJt the dati 1<.., ~elll to the
Inptlt of the memory and a Dat, Strohl? l~ sent to the (lock J)uoder.
At the approprla~te tImet a WrIte rnahle IS generated
Dpcou0r and the dat~ 1" wrlltpn Into
6-2
I1C'PlOry.
It
till
(JO(
k
6.2.1. 4
Horizontal Counter
'I Ill' lIorizontal Countpr count..., th(' numher of character times in
C'<lch ~c.an
line.
When 64 charrtcter spaces have hl'en counted,
d
horizontal
blanking llu1se is generated to blank the display dllring 11orizontdl retrace.
When 68 character spaces have been counted a horizontal sync pulse is
generated to keep the horizontal oscillator in the display unit
synchronized with the controller.
6.2.1.5
Vertical Counter
\{hen 240 horizontal lines have been scanned (0-239), a vertical
blanking pulse is generated (vertical blank (VB) blanks the display
during vertical retrace).
The vertical sync pulse, starting at line
240 and terminating at the end of vertical retrace (beginning of line
244), is generated to keep the vertical oscillator in the display unit
synchronized with the controller.
6.2.1 .. 6
Cursor Character and Row Counters
The Cursor Counters keep track of the horizontal and vertical
position of the cursor.
6.2.1.7
Cursor Character and Row Compare
The Cursor Row Counter is compared with the Display Row Counter and
the Cursor Character Counter is compared with the Horizontal Sync Counter.
When all counters
a~e
equal, the output decoder allows a cursor to be
written on the display.
6.2.1.8
Memory Address Selection
The Memory Address Selection circuit determines the memory address
to be used during read and write
operations~
When a character is read
from memory, the address is determined by the Display Rowand Character
Counters.
When a character is written into memory, the address is deter-
mined by the Cursor Rowand Character Counters.
6-3
GRAPHIC EXPLANATION OF DISPLAY TIMING
Ilbph:r
c:olltrQUu.~
• IIOIlIWllTAL SYlle
~r_u
<iii) *
eharac.ur rae 69~n
Ita. (HDr1&. C""""tu)
e_t
(+1) •
-------1
tlI.bt~
..........
BOI.IZOIlTAL 1lt.A*(D) ~
c.hUat:tu: tt.-6
,."
Chancter Poll1t1l1Da
", ~"4-"::"~"~'~6+'""+"::.'+"::.'-t::+71-'-t-------i
66
" "
67681
... ~+_+-!-l-+-+-!-;;h++-----__i
V
I
D
E
I
... ~++-!-t-+-+-t-;;l;-++-------i
I
12
1100.
o
D
I
S
P
L
.,,1-+-+-+-1-1+-+-t~~+-+-----_t
.,,1-+-+-+-1-+-+-+"'7.:1:-+-+_................---1
A
Y
I
I
I
I
1
I
"
.. <:h.ar..,tu tt-. 69 tht'U n ar.
:~~::~.;:~ :~.::~~lI('iij\nd
tn-ufon haw
DO
aetu.al ."r_
locaUoaC.) •
..
--------~
*
TItE TlME INTERVAL FOR SCAN LINES·
240THRU 255 ARE USED FOR VERTICAL
RETIlACE,$¥liCRONIZATION AND VERTiCAl
BLArtKtHG('R".VifJ
LlNES240THRU
243 ARE NOT PHYSJCALlY SCMNfO.
SltlCETttESESCAN!NTERVALSARE
COl'fTAINED lIlTHINTHE VERTiCAl
FIGURE 6-2
RETRACE/5YNCRONIZATIDNTIMEFRAttE.
LINESZ44 THRU 255 AilE SCANI.EO.BUT
AIl:E81ANKEDIlURINGTHEREMAIHDEROF
THE v£llTlCAL. BUHICJHG INTERVAl..
6-4
6.2.1.9
Character Generator Row Select Counter
The Character Generator Row Select Counter counts the number of
horizontal scan lines in the character row to determine the address of
the Character Generator.
When eight scan lines in a character row have
been completed, the Character Generator is disabled.
The ninth scan line
enables the cursor to be written, and the first and tenth through fifteenth
lines are left blank.
When 15 scan lines have been completed, a Step Row
Display pulse increments the Character Row Counter and the Character Row
Select Counter is reset to zero (0000 2 ),
6.2.1.10
Character Generator and Conversion
The row address and data inputs to the character generator provide
a printable dot matrix.
This matrix is transferred, 1ine-by-1ine, to a
para11e1-to-seria1 shift register and the entire character row (one of 16
character rows) is subsequently written on the CRT display screen.
6.2.1.11
Output Gates
The Output Gate determines whether a character or a cursor is to
be written on the display screen.
It also blanks the display and allows
the horizontal and vertical sync pulses to be sent to the display unit.
..
470
FIGURE 6-3
uo
CC/NtIITION
8
VERTICAL SYNC
HOIlIZO!lTALSYlfC
IlOB.IZONTALBLANI:
VUTtCAL Bu.H1t
)
I-NICH(DFP)
0.. LOV(Otl)
6-5
VOLTAGE AT
"
6.2.1.1?
Roll Counter and Compare
A normal display has a 16-character row capacity.
When an attempt
is made to write more than 16 rows into display, a roll is initiated
a
The 16 character rows stored in display RAM are addressed according
to the counting sequence of the character row counter.
Whenever a
roll is executed, the character row counting sequence is modified (updated)
by the roll counter as follows:
Character Row Counter
Nwnber of Rolls Executed
Counting Sequence
Sequence
IS
0
1
1
15,
2
2
15, 0
0
1
0
2
3
3
3
15, 0
4
4
15, 0
3
4
5
5
15, 0
4
5
6
6
15, 0
5
6
7
8
8
9
I
Roll Counter Counting
9
15, 0 + 6
7
15, 0
8
15, 0
9
8
10
10
15, 0 ' 9
11
11
15, 0 +10
10
11
12
12
15, 0
11
12
13
13 + 15, 0
12
13
14
14
15, 0 + 13
14
15
15
0
15
16
0
(continues)
I
14
(Sequence Repeats)
top character
I
15
bottom character
row in display
row in display
screen
screen (new display
information)
6-6
0
(repeats)
The roll counter keeps track of the number of rolls executed, and
thus causes the character row count to be modified as listed above.
)
The visual effect is that the top character row is erased from
display (and display RAM) and all character rows beneath move up one
character row position.
6.2.1.13
Control Function Decoder
When a control function is received, the control function decoder
determines the type of function to be performed and increments or decrements the Cursor, Character, and Row Counters for the appropriate number
of counts.
6.2.1.14
Control Functions
When a Control Function is sent from the CPU, the Control Function
Decoder determines what type of control was sent.
If the control moves
the cursor up or down, the Cursor Row Counter is decremented or incremented,
respectively.
If the control moves the cursor left or right, the Cursor
Character Counter is decremented or incremented, respectively.
If a
cursor home is issued, the Cursor Rowand Character Counters are cleared.
If a clear page (ETX) is issued, several actions occur.
First, the
Cursor Rowand Character Counters are cleared to position the cursor in
the home position.
Second, the memory address is selected from the
Cursor Counters and a memory write is enabled.
Next, the Cursor Counters
are incremented to address every memory location.
into each of these memory locations.
A "SPACE" is written
When every location contains a
"SPACE", the clear page execution sequence is completed.
6.2.1.15
Read Cycle
The Display Rowand Character Counters are always being incremented.
The counters are used to address the memory sequentially.
As the data irt
each memory location is read, it is converted to a dot pattern by the
)
character generator and sent out serially to be displayed on the CRT screen.
6-7
6.2.1.16
Write Cycle
When a printable character is sent from the CPU, the Input Decoder
sends a Data Strobe to the Clock Decoder, which generates a Write Enable
at character time.
memory address.
The Write Enable selects the cursor position for the
The character is then written into memory_and the cursor
is moved one position to the right.
The character that was written into
memory is displayed during the next read cycle.
6.2.2
DETAILED THEORY OF OPERATION
Refer to schematics 63l2A and 6313 for the following circuit descriptions.
All CRT controllers operate as described in the Detailed
Theory of Operation.
6-6.
Also refer to the Timing Diagram in Figures 6-5 and
Circuit differences in CRT controllers are also documented in this
section.
6.2.2.1
Device Selection
The CRT controller is selected as described in Paragraph 6.1.
L37,
L39 is the Address Comparator, L36 is the Select Latch, and LlO the
Ready/Busy Decoder.
6.2.2.2
"D" Clock and Clock Decode Logic
All timing on the CRT controller is derived from the "D" clock of
.116
~sec.
L9 and LlO form a divide by seven ring counter to provide
timing at one character intervals.
BOC, LOAD SiR, STEP DISPLAY CRT, and
RFAD STROBE are all developed every character time.
When a printable character is generated by a PRINT statement or by
an input from the primary input device, DATA STROBE is developed and sets
QO of Clock Decode Latch L4 at HS and BOC times.
and allows Ql to be set.
and resets QO and Ql.
QU generates
~
Ql is set at LOAD SiR time, develops WRITE ENABLE
WRITE ENABLE is only active during horizontal sync
to prevent character flickering on the display screen.
6-B
6.2.2.3
)
Vertical Counter
L4 and L5 form a divide by 256 counter.
When a count of 240 is
detected at L6 pin 6, VB is generated and remains active for 16 horizontal
sweeps (until the end of scan line 255).
L23 is also enabled at count
240 and is active for the next three horizontal sweeps to provide a
vertical sync pulse (VS) for the Video Display Unit.
The beam returns
to the upper left corner of the screen during VS.
Scan lines 244-255
are subsequently scanned from the top of display.
Scan line 0 begins
at the 13th scan line from the top of the screen.
6.2.2.4
Horizontal Counter
READ STROBE, the basic .81 usee clock, is applied to divide by eight
L8.
The divide 8 output is applied to divide by ten L7.
Output D is the
divide by ten output of L7, or the divide by eighty output of the clock.
During the first 63 clock pulses, D remains low.
At the 64th clock pulse
(after the 64th character) output D toggles high.
This output is applied
to L18 pin 9 and is called HB (Horizontal Blanking) at pin 8.
HB prevents
video information from appearing at the video output connector and increments
the Vertical Counter L5.
The D output is also applied to L23 pin 3.
When output A of L7 is
low and output D of L8 is high, L23 pin 6 goes low, generating HS.
occurs from the 69th to the 72nd character times.
the video output gate to the display unit.
This
HS is gated through
HS returns the beam from the
right hand display scan limit to the left hand display scan limit.
The
Horizontal Counter is still counting character times and HB is still
active.
Character positions 73-80 are the first eight character times
on the new scan line.
After the 80th character time, HB is inactive, and
character 1 is written in the ninth character position from the left
side of the CRT.
L6 pin 8 is active every 16 clock pulses.
pin 5.
This is applied to L9
When the D output of L7 is high at the 65th character, L9 pin 6
will be low until the 79th clock pulse, when L6 pin 8 is low.
The low
from the 65th through 78th characters is inverted and used to reset the
Display Character Counter L34/35.
1'.-9
6.2.2.5
Control Functions
Data on the OB lines is detected as being either a printable character or a control function.
If a control function is defined, L43 and
L44 select the particular function and initiate the appropriate action.
1)
Cursor Home - When a Cursor Home is indicated at L44 pin 10, the
cursor must be placed in the upper left corner of the display.
L13
pin 12 high clears the Cursor Character Counters L19 pin 14 and
L32 pin 14 and L42 pin 2 loads the Cursor Row Counter L17 with the
Roll Counter Address.
If no rolls were performed before the Home
was given, the address will be Row O.
If rolls were performed, the
number of rolls must be loaded into the Row Counter to properly
position the Cursor.
If the Cursor were allowed to return to Row 0,
it would appear wherever Row 0 happened to be at that particular
time.
2)
Carriage Return - A line return at L43 pin 6 clears the Cursor
Character Counters L19 pin 14 and L32 pin 14, positioning the
cursor at left of the line.
3)
Cursor Up - A Cursor Up at L43 pin 7 decrements the Cursor Row
Counter L17 pin 4.
4)
Cursor Down - If a Cursor Down (Line Feed) is indicated at L43 pin II,
the Cursor Row Counter L17 pin 5, is incremented.
If the Line Feed
is indicated on the last line (line 15) a Roll is also generated.
5)
Cursor Left - When a Cursor Left (Backspace) is indicated at L43
pin 9, the Cursor Character Counter L19 pin 4 is decremented.
If
the Counter is at a count of all zeroes (the cursor at the left of
the line) a decrement will sct the counter to all ones and the Cursor
will be positioned at the last character of the same line.
6)
Cursor Right - A Cursor Right indicated at L43 pin 10 increments
the Cursor Character Counter L19 pin 5 and moves the cursor one
space to the right.
6-10
7)
Bell - A Bell indicated at L44 pin 4 triggers L12 pin 5.
H, and
triggered by L5 pin H.
enables L12 pin
112 pin 6
every 16 vertical fields, L12 pin 12 is
This sounds the audible alarm until L12
pin 6 times out.
8)
Erase Page
(ETX)
-
When ETX is decoded at L44 pin 12, the Roll
Counter L31 is reset, Q2 of Mode Select Latch L14 is set and Q3 at
Clock Decode L4 is set.
Clock Decode Q3 allows Reset Row Display
to be generated at VB time to reset the Display Row Counter.
The Cursor Row Counter L17 is reset by loading the reset Roll
Counter Output into the Cursor Row Counter.
time, Q3 of L14 is set.
At the next ROC
ENABLE B6 and ENABLE WP are set active
to allow a write operation in memory.
ENABLE WP selects the
Cursor Rowand Character Counter inputs for memory address
selection.
ENABLE WP is applied to L41 pin 1.
Every LOAD SiR
pulse applies a count pulse to the Cursor Character Counter L19
pin 5.
After 63 counts, L13 pin 6 goes low, causing a count up
pulse at the Cursor Row Counter L17 pin 5.
This continues until
a count of 15 is reached in the Cursor Row Counter L17 indicating
)
16 rows of characters.
While the character and row counters are
being incremented, a "SPACE" is being written into every memory
location.
The 16th count generates a carry from L17 pin 12 which
resets Q3 in the Mode Select Latch L14.
This puts ENABLE B6 and
ENA&LE WP in their inactive states, and terminates the Erase operation.
6.2.2.6
Roll
When all 16 character rows are filled and a line feed is executed,
a roll is generated in the controller.
The Line Feed is decoded at L43 pin 11 at OBS time.
OBS triggers
MMV L25 pin 6 which in turn triggers MMV L25 pin 10, strobing L43.
L25 times out, L43 pin H
returns high.
When
This produces a count up to the
ClIrHor Row Counter Ll7 pin 5 and triggers MMV L40 pin 6.
Since the
Cursor Row Counter L17 was incremented one count from 15, its outputs
A through D are now low.
)
If this is the first roll, the outputs of
the Roll Counter are also low and a compare enables L27 pin 12.
When
L40 pin 6 returns low, MMV L40 pin 11 triggers, setting pin 10 high.
6-11
When MMV L40 appears at L27 pin 13, L27 pin 11 goes low.
several things.
and also sets QO of L14 at the next BOC time.
ENABLE WP.
This does
First, it sets Ql of L14 which generates a Busy (R/B high)
QO produces ENABLE B6 and
L27 pin 11 also clears the Cursor Character Counters L19 pin 14
and L32 pin 14, and sets latch L3 pin 11 to enable L3 pin 4.
When MMV L40
times out, L27 pin 11 will go high again and cause the Roll Counter L3l
pin 14 to be incremented.
ENABLE B6 and ENABLE WP were set active.
ENABLE WP selects the
memory address from the Cursor Rowand Character Counters L17 and L19/L32
and also allows the Cursor Character Counter to be incremented by LOAD SiR.
This writes "SPACES" into the memory for all 64 characters in Row O.
When
the Cursor Character Counter reaches a count of 63, L13 pin 6 goes low.
This resets QO and Ql of L14 and sets a low at the input of the Cursor
Row Counter L17 pin 5.
The next LOAD SiR pulse causes L13 pin 6 to go
high, incrementing the Cursor Row Counter L17 pin 5.
When L14 QO and Ql are reset, ENABLE B6 and ENABLE WP are set inactive.
Memory addresses are now selected from the Display Rowand Character Counters
L28 and L34/35.
At the end of the first horizontal line, HS is generated and is
gated to L3 pin 5, triggering MMV L2.
L2 Q produces a count pulse to
increment the Display Row Counter L28 pin 14 so the first row displayed
is now Row 1.
6.2.2.7
L2 Q resets latch L3.
Character Generation
Data is read from memory, clocked through Latch L13 and applied to
the character generator L15.
The row address is generated by counting the
number of horizontal scan lines.
HE clears the character generator and
increments the Row Address Counter L18.
When a count of 8 is reached, the
address inputs to L15 are disabled by L24 pin 4 low so as not to generate
an additional character in scan lines 8 through 15.
L23 pin 8 decodes a
count of 9 to enable the cursor to be written on that row.
6-12
No information
is written on scan lines 0 or 8 nor on scan lines 10 through 15 of each
character.
L23 decodes a count of 15 to reset the Row Address Counter.
Step Row Display is also generated at this time when the "D" output has
a positive to negative transition.
For a complete display, this occurs
for every character row, or 16 times.
6.2.2.8
Cursor Generation
The cursor row and character position is stored in the Cursor Row
and Character Counters L28 and L19/32.
The outputs of the counters are connected to two five bit comparators
which can be considered as one ten bit comparator with the A=B output at
L27 pin 8.
When the outputs of the horizontal and vertical counters equal
the count of the cursor counters, an A=B is generated and enables Lll
pin 9.
When Cursor Enable is active in scan line 9, a cursor is printed
on the Video Display.
6.2.2.9
Writing a Character Into Memory
When a printable character is generated by a PRINT statement or by
reading from an input device, DATA STROBE is developed.
sets QO of the Clock Decode Latch L4.
Ql to be set at HS and BOG time.
DATA STROBE
QO generates W BUSY and allows
W BUSY sets RB Busy to the CPU.
Ql sets, WRITE ENABLE is active, and L2 pin 10 is enabled.
When
At the next
LOAD SIR time, the DO and Dl inputs go low and reset QO and Ql.
WRITE ENABLE is applied to L13 pin 11 and sets ENABLE WP active.
ENABLE WP selects the Cursor Rowand Character Counters for the memory
address, enables L4l pin 1, and enables the data inputs to the memory
at L2l pin 2.
The data present at Bl through B6 is written into memory
at the location indicated by the cursor.
At LOAD SIR time, the Cursor
Character Counter L19 pin 5 is incremented by one count and WRITE ENABLE,
ENABLE WP and W BUSY are reset to their inactive states.
)
6-13
Since HS is used to set WRITE ENABLE, only one character can be
written into memory for each horizontal scan line.
6.2.2.10
Lower to Upper Case Conversion
When both the B6 and B7 bits are high, a lowercase character is
indicated.
In uppercase displays, it is not necessary to distinguish
between upper and lower case and only uppercase is printed.
Lll
generates a "0" for bit 6 if both bits 6 and 7 are active, indicating
the same character in uppercase.
6.2.3
1)
DIFFERENCES IN VIDEO DISPLAY CONTROLLERS
63l2A and 6312.
The 6312 Controllers has one circuit change and one
circuit deletion.
The circuit change is in the device selection detection.
AB
- AB
8
I
compared.
being compared with the switch settings, AB
Instead of
is
I
5
The eight exclusive OR on the 63l2A is replaced by a five
bit comparator on the 6312.
- AB
Circuit operation is exactly the same.
The circuit deletion is the alarm detector L12.
The BELL code no
longer can be used to sound an alarm.
2)
63l2A and 6350A.
The only difference between the 60 Hz and 50 Hz
Controllers is in the Vertical Counter.
At count 240, L7 pin 6 goes low, setting latch LlO, generating VB
and enabling Ll pin 12.
Ll pin 2.
At count 256, L7 pin 6 returns high, enabling
Ll pin 1 goes high at count 288, pin 11 at count 304, pin 5
at count 306 and pin 3 at count 307.
Pin 8 goes low at this time and
a new vertical timing cycle starts.
Vertical Sync is generated at L13
pin 8 and occurs from count 272 to 279.
3)
6313 and 6529.
The 6529 has the capability of displaying Upper and
Lower case English or Dual Language.
When a lower case character is
specified, L29 sets L28 which enables character generator L2.
upper case, character generator L8 is enabled.
6-14
For
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
--'
1
1
1
1
1
1
1
1
1
1
1
1
JI
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
FIGURE 6-4
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DISPLAY CONTROLLER - SIMPLIFIED FUNCTIONAL BLOCK DIAGRAM
6-17
6.3
KEYBOARD CONTROLLER
The Keyboard Controller is used to input information to the CPU from
the keyboard.
Since the keyboard is the primary console input device,
all CPU control is initiated through it.
6.3.1
GENERAL THEORY OF OPERATION
The theory of operation for the Keyboard Controller is described in
the following paragraphs.
Refer to the simplified block diagram Figure
6-7.
,---------.,
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~[fBOAlllJ MA R11
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DEViCE
SELECTIOri
FIGURE 6-7 KEYBOARD CONTROLLER
6.3.1.1
Device Selection
Refer to Section 6.1 for description of Device Selection.
6.3.1.2
Scan Clock
The Scan Clock provides an address for the RAM, ROM and the Y Multiplexer.
The clock also prOVides the necessary timing for the Y Decoder
and control functions.
6-18
6.3.1.3
Y Multiplexer
The Y Multiplexer receives the strobe from the key that was depressed
)
on the keyboard.
6.3.1.4
ROM and Output Latch
Once a key is depressed, the ROM is enabled for an output.
The output
of the ROM is stored in the Output Latch until the proper time for use by
the CPU.
6.3.1.5
Function Decoder
When Shift, Shift Lock, Halt/Step or Reset keys are depressed, the
Function Decoder provides the proper signals for the controller and the
CPU.
6.3.2
DETAILED THEORY OF OPERATION
Refer to schematic 6367 for the following circuit descriptions.
6.3.2.1
Device Selection
The Keyboard Controller is selected as described in Section 6.1.
L2B, L29 is the Address Comparator, L2l the Select Latch and LIB the
Ready/Busy Decoder.
6.3.2.2
Keyboard Input Cycle
Oscillator LB is applied to the twelve bit counter L7, L14 and LIS.
L14 and LIS are the address and keyboard scan counters, the output of L7
being the input clock.
For every scan and address increment, L7 is in-
cremented 16 times.
Assume the Q outputs of all the counters have just changed to low.
LIS pin 11 disables L24 pin 6, sets AD
of RAM L12 high (selecting the
B
upper half of RAM) and enables L23 pin 2. As the counter is incremented
)
up from 0, the Y Multiplexer, the ROM and the RAM are sequentially addressed,
and the X Decoder decodes the count for output to the keyboard.
6-19
When a key on the keyboard is depressed, the X Decoder output is
connected to a Y Multiplexer Input.
At some time, the address of the
Y Multiplexer and the decoded output of the X Decoder will be equal,
causing a low at one input of L6.
L6 pin 6 will go high, causing 1.23
pin 3 to go low, setting the RAM input high.
RAM at this address at count 14 of L7.
A '1' is written into the
If more than one key is depressed,
a '1' will be written into the RAM for each key, each at a different RAM
address.
After the counter has been incremented to 128, QD of LIS goes high,
enabling L24 pin 4, and L38 pin 5.
When the address of the depressed
key is addressed again, L6 pin 6 goes high, enabling L24 pin 1.
Since
L7 counts 16 times before the address is incremented again, L7 is used
to perform several functions.
When L7 pin 11 goes low, L38 pin 6 goes
high, addressing the upper half of the RAM again.
written previously at that address
~
The data that was
Ll2 pin 14 is the data
now read.
compliment, and will be low, enabling L24 pin 5.
At count 4 of L7,
L24 pin 4 goes high, causing L24 pin 6 to go low.
Latch L23 is reset
(pin 11 high), enabling L24 pin 10, at count 8 of L7, L24 pin 2 returns
low, enabling the latch to be reset.
the lower half of RAM.
L38 pin 6 also goes low, addressing
Since nothing was written at this address, a '1'
at the output will enable L24 pin 13.
At count 11 of L7, L24 pin 12 goes high, clocking the ROM data
through L33 and L35.
FF L21.
At count 12 of L7, L24 pin 12 returns high, clocking
L21 pin 9 goes high at this time.
If
CPR
is inactive, L40 pin 6
goes low, triggering MMV L27.
L27 pin 6 high allows the outputs of L33
and L35 to be presented to the
IB
lines and also generates
IBS.
L27
pin 7 low clears L21 to prepare for another character output.
At count 14 of L7, Ll2 pin 15 goes high, enabling RAM Write.
L23 pin 8 is still low, presenting a 'I' to the RAM data input.
Latch
This '1'
= low) of the RAM. If the key
8
remains depressed during the next cycle, L24 pin 13 will be low, preventing
will be written in the lower half (AD
IBS from being generated.
Therefore, only one word will be strobed to
the CPU no matter how long the key is depressed.
At count 16 of L7, pin 11 goes
lo~
,setting latch L23 pin 8 high.
L38 pin 11 is used to enabled the ROM and output latch when a Special
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Function Key is depressed.
Since the SF key uses the Y4 line and the
Edit key the Y6 line, L38 pin 11 inhibit, an IB
9
output except during
Y4 or Y6.
6.3.2.3
Function Key Detector
The Function Key Detector detects a Prime, Halt, or Shift from the
keyboard.
1)
Prime.
L3 pin 5 is normally low.
When the Reset is depressed,
L3 pin 5 goes high and pin 1 low, triggering MMV Ll pin 6.
This
generates Prime to the CPU and clears L9 pin 13 and L9 pin 1.
2)
Halt.
The HALT/STEP key is applied to L2 pins 7 and 11.
L2 pin 10
goes low when the key is depressed, triggering MMV Ll pin 10 and
generating Halt to the CPU.
3)
Shift Lock.
The SHIFT LOCK key is applied to L2 pins
Depressing the key presets L9 pin 10 and L9 pin 4.
~
and 6.
L9 pin 8 goes
low, disabling L19 pin 8, setting A address of ROM L22 low and
8
turning on the Shift Lamp. L9 will remain preset until either Reset
or Shift Left/Right is keyed.
4)
Shift Left/Right.
When either the Shift Left or Right key is
depressed, LID pin 10 goes low, clocking L9 pin 3 and clearing
L9 pin 13.
L19 pin 11 goes high, setting AB
S
low and turning on
the Shift Lamp.
6.4
TAPE DRIVE CONTROLLER
The Tape Drive Controller is used to control the flow of uata to
and from the Digital Cassette Tape Drive.
The controller works in
conjunction with the motor and pinch control logic in the Digital
Cassette Tape Drive Unit (refer to Section 5 of this manual).
6-22
6.4.1
GENERAL THEORY OF OPERATION
The theory of operation of the Tape Drive Controller is described
in the following paragraphs.
Refer to the simplified overall block
diagram in Figure 6-9.
.. m
1lJ<------------,
TAPE UNIT
HG.URE 6-9
6.4.1.1
TAPE DRiVE CONTROLLER
Device Selection
Refer to paragraph 6.1 of this manual.
6.4.1.2
Control Decoder
The Control Decoder provides selection, control and data signals
for the CPU and the Tape Drive Unit.
6.4.1.3
Output Buffer
The Output Buffer provides buffered data signals for the Tape Drive
Unit from the CPU.
6.4.2
)
DETAILED THEORY OF OPERATION -
TAPE DRIVE CONTROLLER
Refer to schematic 6316 for the following circuit descriptions.
6-23
6.4.2.1
Control Decoder
When the controller 1S selected by thL CPU, L4 p1n 5 goes h1gh.
11ns sets LION actlVe, enables L9 p1ns 2, 4, 9 ~nd 13 and LIO pin 4,
and sets RB to Ready (low).
for the tape dr1ve unlt.
LIO enabled allows
L9 enabled allows IB
I
OB~
- IB
to generate
6
D~rl
to be generated
from the tape drive unit to the CPU.
RB stays Ready unt1l the controller is deselected or BSY goes ac-
HSY 18 actlve durIng a tape braklne operatIon or a Rewlnd from
tlve.
the front panel rewlnd sW1tch.
When BSY lS actlve, RB goes hlgh, send1ng
a Busy cond1t1on to the CPU.
The data clock slgnal from the tape dr1ve unit, COSTB, generates IBS
to the CPU when CBS, CPB and BSY are 1nactlve.
6.4.2.2
Output Ruffer
Output Bus OBI - OB lS applled to buffers r6 and L7. The output
S
of the buffers prov1des CB - CBS as data for the tape dr1ve lOglC.
l
6.5
DISK CONTROLLER
Ihe dlSk controller
provlde~
bufferIng of InformatIon beIng trans-
fprred between the dIsk and the CPU.
processor,
6.5.1
the controller
Ib
only
u~ed
SInce the dl.... k unlt has
Itb
own
to transfer data and strobes.
(£NloRAL TllloORY Of OIERATION
lhe theory of operatlon of the D1Sk Controller 18 descrIbed 1n the
followlng paragraphs.
Refer to the slmpl1fled block dlagram In Flgure
6-10.
6.5.1.1
DeVlce Selectlon
Refer to seetlon 6.1 of thlS manual.
6-24
FIGURE 6-10 DISK CONTROLLER
6.5.~.2
Input Buffer
The Input Buffer receives data being sent from the disk microprocessor allowing it to be transferred to the CPU when the controller
is enabled.
6.5.1.3
Output Buffer
The Output Buffer provides buffered data signals for the Disk Unit
from the CPU.
6.5.2
DETAILED THEORY OF OPERATION
Refer to schematic 6541 for the following circuit descriptions.
6.5.2.1
Device Selection
The disk controller is selected in the same manner as described
in section 6.1.
Lll, L12 is the Address Comparator, L13 the Select
Latch, and L15 the Ready/Busy Decoder.
)
6-25
In addition a Drive #3 Latch,
which detects the '40' bit with the specified address, is used to enable
the third disk drive in triple disk systems.
6.5.2.2
Prime Circuit
PRMS is initially generated in the CPU and comes into the controller
at connector 3 pin 3.
When the RESET Key is depressed, PRMS clears the
Select Latch, Drive #3 Latch and sends a GPRM to the disk.
6.5.2.3
Input Ruffer
Data GKB
Ll and L2.
- GKA and strobe GISN from the disk are buffered by
O
3
When the controlled is enabled, the data and strobe are sent
to the CPU via L3, L9 and LlO.
6.5.2.4
Output Buffer
CPU Output Bus Data OR
OBI is applied to buffers L6 and L7. The
S
output of the buffers provides data for the disk unit. When the controller
is enabled,
OBS
is gated through L15 to provide the data strobe for the
disk.
6.6
DISK MULTIPLEXER CONTROLLER (2230MXA/B)
The Disk Multiplex Master and Slave Controllers provide a means
to efficiently use one disk system with up to four 2200 CPUs.
The Disk
Multiplexer controls the transfer of data and strobes between the disk
and the appropriate CPU.
6.6.1
THEORY OF OPERATION
The simplified and detailed theory of operation is described in
the following paragraphs.
Refer to the simplified block diagram in
Figure 6.11.
6-26
r---------------------.
I
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FIGURE 6-11
6.6.1.1
!'MlDl o:HIKLIDl
JI
DISK MULTIPLEXER CONTROLLER
Device Selection
Refer to Section 6.1 of this manual for a description of device
selection.
6.6.1.2
Scan Clock
The Scan Clock provides the Channel Scanner with two 6.4 usec
)
clocks.
6.6.1.3
Channel Scanner
The Channel Scanner checks each CPU sequentially for a disk
access indication.
If a CPU is trying to access the disk, the
Channel Scanner will connect that CPU to the disk to allow one disk
operation to be performed.
The Channel Scanner also informs each
CPU if the disk it is attempting to access is Busy.
6.6.1.4
CPU I/O Buffer
To eliminate the need for complex multiplexing of each channel,
the CPU I/O Buffer uses Tri-State devices for data transfer.
When
the controller is enabled for a disk operation, the I/O Buffer is
removed from its high impedance state and allowed to transfer data to
and from the disk.
)
The I/O Buffers on the other Multiplexers remain
in their high impedance states.
6-27
6.6.1.5
Hog Latch
The Hog Latch connects the disk to a CPU when the Hog Mode program
command is generated.
The Hog Latch allows the CPU to remain connected
to the disk until a program command to disable the Hog Mode is generated.
6.6.2
DETAILED THEORY OF OPERATION
Refer to schematics 6785 and 6786 and Figure 6-12.
The IC numbers
called out in the circuit descriptions apply only to the 6785.
6.6.2.1
Scan Clock
CK1 from the CPU is applied to L8 pins 3 and 11.
L8 are applied to L9 with the CKL clock.
The outputs of
Once every four CKL clocks,
L9 pins 6 and 8 will generate a Scan Clock 1 and Scan Clock 2 (refer
to Figure 3).
6.6.2.2
Channel Scanner
The Channel Scanner is composed of an Address Counter (L20) , a
Disk Access Request Detector (L2) and Latch (L19), and a Disk Busy
Indicator (L3).
When the disk is not accessed, L19 pin 6 is high, enabling L21
pin 6 to gate the scan clock to the Address Counter.
The Address
Counter sequentially changes the address to L2 and L3 at 6.4 usec
intervals.
When the disk is addressed by a CPU, one of the four C
inputs to 12 will go high, setting L19 pin 2 high.
At scan clock 2,
119 pin 6 is clocked low, preventing scan clock 1 from incrementing
the Address Counter and enabling L3 to output a Disk Busy indication
to the channel selected.
Suppose channel 1 was selected to access the disk.
With the 6785
Controller selected, L18 pin 4 will be high setting the CO input to L2
high.
When the address for L2 is 0, the high at the CO input is applied
to 1.19 pin 2.
When Scan Clock 2 clocks L19, L3 is enabled and the
6-28
address for L2 and L3 is prevented from changing.
If the disk is
Busy, L3 pin 1 is low, L3 pin 7 will be high setting L22 pin 4 low,
keeping RB high (RB high = Busy).
If the disk is not Busy, the output
selected at L3 will be low, setting L22 pin 6 low, indicating Ready
to the CPU.
All other outputs of L3 are high, so that even if another
controller is selected, that CPU will not be allowed to receive a
Ready (RB = low).
6.6.2.3
CPU 1/0 Buffer
The Output Bus bits OBI thru OB are applied to L27 and L30. With
8
the controller selected, L22 pin 1 is enabled. At OBS time, MMV L24 is
triggered, enabling L27 and L30 to output data to the disk.
Since OBS
is also sent to the disk to clock the data in, L24 ensures that the
data is present on the output bus for a slightly longer time than OBS.
Due to signal degredation on long cables, L7A ensures that the disk
receives an OBS of the correct duration.
The input data from the disk is applied to the Disk Input Buffer.
Because of the length of the multiplexer cables, erroneous data is
prevented from being received by the CPU by the following method:
The data and the data strobe from the disk are applied to latch
L13/L14 and M}W LIS.
LIS pin 13 high triggers MMV LIS pin 10
after a slight delay.
LIS pin 4 low is gated through L18 pin 10
to indicate a CPU Busy condition to the disk.
LIS pin 4 remains
active for approximately 15 usec to prevent the disk from sending
more data to the CPU before it is ready.
LIS pin 5 high clocks the
disk data into latch L14/l5 and is applied to Buffers LID and L11.
LID and Lll were enabled when LIS pin 14 triggered low.
is now applied to buffers L28 and L3l.
The data
The buffers are enabled
by L22 pin 6 low, presenting the input data to the CPU.
When LIS
pin 5 times out (approx. 4.5 usec), L12 pin 4 goes low for approximately
7 usec to generate lBS.
CPU by lBS.
)
The input data is now clocked into the
When LIS pin 4 times out, buffers LID and Lll return
to their high impedance state, and a Ready is now indicated to
the disk.
6-29
6.6.2.4
Prime Circuit
When the RESET key is depressed on the keyboard, a PRMS is generated
by the CPU.
PRMS clears the Device Selection Latch L17, which removes
the channel enable to L2, and also clears the Hog Latch L17A.
PRMS
is also applied to Tri State Buffer L33, whose output is connected to
the same type of buffer in the other controllers.
When one of the PRMS
signals is present on the PRIME line, MMV L24 is triggered.
If the PRMS
is generated by a CPU other than the one presently selected, L22 pin 9
low will prevent PRIME from being sent to the disk.
When PRMS is
generated by the CPU that has control of the disk, L2 pin 7 goes low
and L19 pin 6 is clocked high by scan clock 2, enabling L22 pin 9.
MMV L24 pin 5 is on for a sufficient length of time to allow L22 pin 8
to generate
PRIME
for the disk and to trigger MMV L12.
MMV L12 pin 5
disables L2 for approximately 150 usee to allow the disk to complete
the Prime Routine before another CPU can be selected by L2.
6.6.2.5
Hog Latch
When the Hog Mode is programmed by specifying an address with the
80 bit on, L17A pin 8 is clocked low by ABS.
This sets the respective
C input to L2 high until the Hog Mode is deselected by a program command
or until PRMS is generated.
The CPU that specified the Hog Mode will
have complete control of the disk and cannot be interrupted by another
CPU.
6.6.2.6
Drive #3 Latch
When an address with the 40 bit on is specified, L17 pin 9 is clocked
low by
ABS,
generating DN3 for the disk.
....
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....
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)
6-31
THIS PAGE INTENTIONALLY LEFT BLANK
6-32
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SECTION 6
NOTES:
)
)
6-35
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SECTION 7
SYSTEM DIAGNOSTICS
NOTE:
All diagnostics will run with 4K RAM, except
where specified.
The following units have diagnostics incorporated
on diskettes presently:
MODELS: -01
-30MXA/B
-02
-40
-03
-42
-09
-43
-12
-60
-21
-61
-21 W
-62
-24
-70
-30
-S, T CPU Tests
Eventually, 2200 System unit diaQnostics
will be incorporated on diskettes.
7.1
7 . 1. 1
MODEL 2200 A, B AND C CPU BASIC DIAGNOSTIC TESTS
TESTS 1
&
2
The BASIC Diagnostic Tests #1 and #2 check the following BASIC
statements:
LOAD, LOAD NAME, LOAD LINE NO., LET, IF/THEN, FOR/NEXT, DIM,
DIM for STRING ARRAYS, STR(), DATA READ/RESTORE, GOSUB/RETURN,
DEFFN, TRACE, DEFFN, DATA SAVE, DATA LOAD, LOAD, NAME, REWIND,
SKIP NF and BACKSPACE NF.
At the end of each test, a go/nogo indication is displayed.
Test:
)
7-1
To use the BASIC
(a)
Key CLEAR, EXECUTE.
(b)
LOAD the program into the 2200.
(c)
Key RUN, EXECUTE.
(d)
The function being tested and the results of the test are displayed
on the Video Display Unit for the first thirteen tests.
(e)
When TRACE is tested, CONTINUE, EXECUTE must be keyed after each
portion of the test as indicated on the Video Display.
(f)
After DEFFN has been tested, rewind and remove the Diagnostic Test
Tape and insert an unprotected blank cassette.
(g)
Key CONTINUE, EXECUTE.
(h)
When DATA SAVE and DATA LOAD Tests are completed, rewind and remove
the cassette and insert BASIC Diagnostic Test #2.
(i)
Key CONTINUE, EXECUTE.
(j)
When BASIC Diagnostic #2 stops, the BASIC Diagnostic Tests are
completed.
7.1.2
MODEL 2200B BASIC DIAGNOSTIC TEST
The 2200B BASIC Diagnostic Test checks the following BASIC statements:
AND, OR, XOR, ROTATE, ADD, ON GOTO, ON GOSUB, NUM, VAL, BIN,
800L, CONVERT PACK, UNPACK and POS.
To use the 22008 BASIC test:
(a)
Key CLEAR, EXECUTE.
(b)
Load the program into the 2200.
7-2
(c)
(d)
Key RUN, EXECUTE.
The function being tested and the results of the test are displayed
on the Video Display Unit.
7.1. 3
MODEL 2200C BASIC DIAGNOSTIC TEST
The 2200C Diagnostic Test checks the following BASTC statements:
ON ERROR GO TO, RETURN CLEAR, COM CLEAR, STR(), DEFFN TEXT
ENTRY, PROTECTED PROGRAMS.
To use the 2200C BASIC Diagnostic Test:
(a)
Key CLEAR, EXECUTE.
(b)
LOAD the program into the 2200.
(c)
Key RUN, EXECUTE.
(d)
When DEFFN TEXT ENTRY is tested, follow the instructions displayed
on the Video Display.
Do not protect the program.
The following will be displayed after each
Special Function Key is depressed:
)
S.F. Key '0
:A$=
S. F. Key '1
S.F. Key , 2
:A$="l"
S.F. Key , 3
:PRESS SF KEYS '4 and '16
:RUN 280
S.F. Key '4
:RUN 140
S.F. Key '16
:STOP
S. F. Key , 5
(CLEARS DISPLAY)
S. F. Key '6
: 302 PRINT HEX (03)
S.F. Key , 7
:304 PRINT"
S.F. Key '8
:306 N=20
S.F. Key '9
:308 PRINT TAB(N);'ON ERROR GO TO ...••.. •
*****
*****"
S.F. Key '10
: RUN 302
S.F. Key 'II
(CPU STARTS NEXT TEST)
7-3
2200C DIAGNOSTIC
(e)
Protected Programs are now tested.
on the Video Display.
Follow the instructions displayed
The following should appear after the S.F. Keys
are depressed:
S.F. Key '0
:SAVE P
S.F. Key '1
: BACKSPACE IF
S.F. Key '2
: LOAD
S.F. Key , 3
:5000
S.F. Key '4
:SAVE
S.F. Key '5
:LIST
tERR 44
tERR 44
tERR 44
7.1.4
MODEL 2200S BASIC DIAGNOSTIC TEST
The 2200S BASIC Diagnostic Test checks the following BASIC statements:
LOAD, LOAD NAME, LOAD LINE NO., LET, IF/THEN, FOR/NEXT, DIM,
l
STRO, DATA READ/RESTORE, eOSUB/RETURN, DEFFN, DEFFN , ON GOTO,
ON eOSUB, VAL, mNVERT, NUM and RETURN CLEAR.
To use the 2200S BASIC Test:
(a)
(b)
(c)
(d)
Key CLEAR, EXECUTE.
LOAD the program into the 2200.
Key RUN, EXECUTE.
The function being tested and the results of the test are displayed
on the Video Display Unit.
(e)
This test is continuous.
2200S
Memory Tes t .
2200T
Basic Diagnostic
2200T
Memory Test
7-4
7.1.5
MODEL 2200T DIAGNOSTIC TESTS
The Model 2200T is equivalent to a 2200C wi th Options I, 2
and
5
or a
noDs
with Option 24.
Accordin!\ly, lh,-
dl.l~nllst
I,'"
for the nOOT CPU are as follows:
Paragraph #
Title
7.1. 3
2200C Rasic Diagnostic
7.1.4
2200S Basic Diagnostic
7.2
2200 Memory and Math Diagnostics
7.3
2200 B & C Memory Diagnostic
7.4.1
Matrix Option 1 Diagnostic
(MEM-l, MEM-2, and MATH-3)
7.4.2
General I/O Option 2 or 23
Diagnostic
7.4.6
7.2
Sort Option 5 Diagnostic
2200 MEMORY AND MATH DIAGNOSTIC TESTS (MEM-I, MEM-2, and MATH-3)
The 2200 Memory and Math Diagnostic Tests check the RAM and 8 bit
ROM in 2200 Systems.
To use the test:
)
(a)
Key CLEAR, EXECUTE.
(b)
LOAD the program into the 2200.
(c)
Key RUN, EXECUTE.
(d)
When asked for, key the memory size in 'k' bytes, EXECUTE.
(e)
When asked for, key 1, 2 or 3, EXECUTE for the test desired.
(f)
The test selected is continuous.
The total number of tests
completed and the number of errors is displayed.
7-5
(g)
If an error occurs, the type of failure that occurred is displayed.
(h)
To select a new test, key RESET and perform steps a - e .
7.3
2200 B & C MEMORY DIAGNOSTIC
An improved 2200 memory diagnostic was written for 2200 Band C
units.
The test checks the memory and calls out both the bad board
and bad IC on the board.
The board that is called out faulty is correct,
but the IC that is called out is not necessarily correct due to the
addressing and decoding of all the memory ICs.
The memory boards are
referred to as boards #1, 2, 3 and 4; board #1 is nearest the 6308.
Equipment Required:
2200 B or C
2215 or 2222
2216/2217
OPERATING INSTRUCTIONS:
1)
CLEAR EXECUTE
2)
LOAD EXECUTE
3)
RUN EXECUTE
4)
Enter memory size (4, 8, 12, 16, 20, 24, 28, or 12), EXECUTE
5)
'The correct memory size program is loaded and the tebt
displaying LOOP O.
begln~
by
The test is not complete until LOOP 1 is dis-
played.
7.4
OPTION DIAGNOSTICS
7.4.1
M~7~IX
(OPTION 1 OR OPTION 21)
DI~CNOSTIC
11>e MATRiX Diagnostic Test checks 2200 Systems with Option 1 or 21.
To use the MATRIX Test:
(a)
Key CLEAR, EXECUTE.
(b)
LOAD the program into the 2200.
(c ) Key RUN, EXECUTE.
7-6
(d)
Key 1, 2 or 3, EXECUTE for the test desired.
(e)
MATRIX Microcode Diagnostic Test 1 checks MAT EQUALITY, MAT ADDITION
and SUBTRACTION, MAT CON, MAT ZER, MAT IDN, MAT SCALAR MULT, MAT TRN,
MAT MULT, MAT INV, MAT REDIM and MAT READ.
(f)
This test is continuous.
(h)
Follow the instructions indicated on the Video Display Unit for this
test.
(i)
MATRIX PRINT TEST 3 checks for correct output of the matrix.
(j)
Follow the instructions indicated on the Video Display Unit for
this test.
7.4.2
GENERAL I/O (OPTION 2 OR 23)
INTERACTIVE DIAGNOSTIC
The GI/O Diagnostic Test checks the following BASIC statements in
2200 Systems with Option 2 or 23:
$GIO (output), $GIO (input), $GIO
C6XX and $IF ON.
(a)
Key CLEAR, EXECUTE.
(b)
LOAD the program into the 2200.
(c)
Key RUN, EXECUTE.
(d)
Follow the instructions indicated on the Video Display Unit.
(e)
If a STOP ERROR message is displayed, key RUN, EXECUTE to start
the test again.
J
7-7
AUTOMATIC DIAGNOSTIC
This test should be used in conjunction with the GIIO Test described
in Paragraph 5.24.
This test checks the following BASIC statements:
$IF ON, $TRAN, $GIO and A$()< or >A, B, C.
To use the test:
(a)
Key CLEAR, EXECUTE.
(b)
LOAD the program into the 2200.
(c)
Key RUN, EXECUTE.
(d)
The function being tested and the results are displayed on the
Video Display Unit.
(e)
This test is continuous.
7.4.3
EDIT (OPTION 3) DIAGNOSTIC
a)
Enter any statement number and statement,
e.g. 10 PRINT "NOW IS THE TIME FOR"
EXECUTE
b)
Key Edit, asterisk will appear signifying Edit mode, enter statement
number, Key Recall, statement line appears on screen.
c)
Move cursor one step by solid arrow to left or right.
d)
Move cursor five steph by dotted arrow to left or right.
"INSERT" moves character or basic keyword above cursor and rest
of line one space to the right.
"DELETE" deletes character or basic keyword above cursor and moves
rest of line to the left one space.
7-8
II
ERASE" erases text starting with character above cursor.
Key Execute to exit Edit mode.
NOTE 1:
SPECIAL FUNCTION KEYS ARE INOPERATIVE IN EDIT MODE.
NOTE 2:
EXIT FROM EDIT MODE CAN BE MADE REGARDLESS OF THE POSITION
OF THE CURSOR ON THE TEXT LINE.
7.4.4
AUDIO ALARM
(OPTIONS 4 & 31) DIAGNOSTIC
PRINT HEX (07) will cause a "BEEP" from the speaker.
10
FOR 1=1 to 5
20
FOR J=l to 50
30
NEXT J
40
PRINT HEX (07)
50
NEXT I
60
STOP
Run Execute causes five BEEPS and stop.
7.4.5
SORT
(OPTION
5) DIAGNOSTIC
The SORT Diagnostic Test checks the following BASIC statements on
2200 Systems with Option 5:
MAT CONVERT, MAT MOVE, MAT SORT, MAT MERGE, MAT COpy and MAT
SEARCH.
To use the SORT Test:
(a)
Key (LEAR, I:XECUTE.
(b)
LOAD the program into the 2200.
(c)
Key RUN, EXECUTE.
(d)
This tes t is automatic and continuous.
)
7-9
7.4.6
ADVANCED
PROGRAM~BLE
(OPTION 22) DIAGNOSTIC
Verify proper operation by executing the 2200B, 2200S, and
OP-l/2l (Matrix) Diagnostic Tests documented in this section.
7.4.7
DISK ROM (OPTION 24) DIAGNOSTIC
See 2200T diagnostics, paragraph 7.1.5.
7.4.8
KEYBOARD CLICKER (OPTION 32) TEST
a)
Connect keyboard to controller and turn system ON.
b)
Depress every key on keyboard including special funtion
keys.
Listen for click and check for entry on CRT.
NOTE:
The RESET, HALT/STEP, SHIFT and SHIFT LOCK keys do
not produce a click.
7.5
7.5.1
PERIPHERAL DEVICE DIAGNOSTICS
2200 INPUT SYSTEM DIAGNOSTIC
The diagnostic tape checks the following input devices and are
accessed by the following Special Function keys:
KEY
MODEL NUMBER
01
2214 Mark Sense Card Reader
02
2203 Punched Tape Reader
03
2234/2244 Card Readers (Hollerith codes)*
04
2234/2244 Card Readers (binary codes)*
TIle following equipment is needed:
2200Bl, 2216/2217, 2215 or 2222.
7-10
Operating Instructions
Enter:
CLEAR EXECUTE
LOAD EXECUTE
RUN EXECUTE
The CRT now displays instructions.
SPECIAL FUNCTION 01 - 2214 MARK SENSE CARD READER
1.
The test consists of entering 17 cards 1nto the card reader.
(See end of ISN for card codes)
(a)
Load cards 1 through 5.
After card #5 1S loaded, the next
f11e on tape w111 be loaded.
(b)
Load cards 6 through 14.
Load cards 15 through 17 four times each.
(c)
Card 15 checks for HEX (FF)
)
Card 16 checks for 1 b1t per byte
Card 17 checks for skips
FIGURE 7-1
I
T
MODEL 2214 DIAGNOSTIC CARD #1
TOO tn
TLEFN J
USE Nf) 2~
or
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FIGURE 7-14 MODEL 2214 DIAGNOSTIC CARD #14
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FIGURE 7-15 MODEL 2214 DIAGNOSTIC CARD #15
7-18
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FIGURE 7-16
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MODEL 2214 DIAGNOSTIC CPRD #16
,
or
CARD
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)
FIGURE 7-17 MODEL 2214 DIAGNOSTIC CARD #17
7-19
/.
:;I'I:CIAI. 1,IINC'J'lON 02 -
:>PL'(O
i.ll
Ftllltot iOIl
220) I'AI'Ell TAPE
1({'yH
O()-{) I ,wd 14
RI;;ADEIl
1I'i('
p.lpl'r tape Ill.
Spec ial Func t ion Key 04 uses paper tape 112.
Special Function Key 15 displays the tests for the 2203 on the
CRT.
Tape III is shorter than tape 112.
Make a loop out of tape III with
a diameter of at least 8 inches.
Key 00 - Paper Tape Reads Display Patterns - The 2203 reads tape
III and displays the pattern in hexadecimal and binary notation.
Key 01 - Read Forward/Backward Rapidly - The 2203 reads tape III
forwards or backwards rapidly.
Lines 1 and 4 on the CRT should not
change since this is the data being read.
Key 02 - Read and Compare Loop Tape Forward - This test reads tape
III and checks for any errors.
Key
O~
The tape must start on the blank section.
- Read and Compare Loop Tape Backward - This test reads
tape III backwards and checks for any errors.
The tape must start on
the blank section.
OPERATING INSTRUCTIONS - 2203 TEST
1)
Make loop of ASCII tape; join at blank leader ends.
2)
Load paper tape into reader.
3)
Load diagnostic cassette into 2217 tape drive.
4)
Rewind~
5)
When finished loading tape blocks, Run, Execute.
Load, Execute.
7-20
FIGURE 7-18 MODEL 2203 TEST TAPES
· ..
....
....
·· ·....
......
·......·.......
... ......
• •••
..·..........· ...••..
.... ..
.....
.....
·.......
.....
......
..· .....
·.. ...
·...
....·....... ....
··••••...............••..
·......
....
.. ....
···· ...
· ...
.... ..
....
·..·.......
.... ..
....
...
·.....
.......· ....
·....
·............ ...
...
.. .•
...
•
· .
....
...
...
...
..
...... ..
·.......
·
·........
.....
·....·............
·..·......
. ......
.
·.....
...
· ..
....
·..·....
..... ...
·......... ..
....... ..
...
·......
·. .
.....
·..·......
·........ .
·...
..··..·.... ...
.........
·.......
·....·..
..
...
·..·....
·.
~.
..
.....
·......
....
·...·. ..... ..
·...... ..
· ...· ..
·.....
.......
·....
.···.........
·.·..·. ..·. ..
.··.........
.......
......
·.....
......
·.· .....
. ...
.·..· ...
·....·.... ....
....... ....
...
.··...... ....
.....
· ....
·.....
·..·....
..... ..
·.....
.........· .
·...
\~:
)
L'
7-21
........
·........
.........
·........
·.......
......
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. . ...
.
·........
· ..
·..·......
..
.
·........ ....
....... .......
...
·.. .· .....
·.·. ...
·.. . ..
·..·... ......
·.....
....
· .....
....
·....
...
....
...
·......... ......
...
.. ........
...
..
·.. ·. ...
.···.. ....
.·.. ..
..
.·. ..
·....· ...
·.·. .....
·.......
....
...
..·.. ...
·
.........
",
:
···• .•..
·· ..
···· .... ......
··· ...... .......
·· ....••...•
.. .••
••
•• .
..
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·.....
..... ..
.....
.....
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. ...
. ..
..
·...
. ...
...
.....
...
..
· ....... ..
·......... ......
··..... . ...
·· .
TIle following shollid apppar in the 2216 display screen:
2203 PAPER TAPE READER DIAGNOSTIC
FUNCTION KEYS CONTROL THIS PROGRAM
KEYS 0 THROUGH 4 FOR 2203 EXERCISE
KEY 0 PAPER TAPE READ DISPLAY PATTERNS
KEY 1 READ FORWARD/BACKWARD RAPIDLY
KEY 2 READ AND COMPARE LOOP TAPE
KEY 3 READ AND COMPARE LOOP TAPE (REVERSE)
KEY 4 (TEST OF PAPER TAPE MICRO-CODE)
USES SPECIAL PAPER TAPE
KEY 14 BACKWARD READ PAPER TAPE
KEY 15 DESCRIPTION OF FUNCTION KEY
STOP SELECT DESIRED FUNCTION
FI GURE
7-19
Key 04 - Paper Tape Microcode Test - This test uses tape #2.
tape must be started at the blank end.
The
To operate, key RUN, EXECUTE,
Special Function 04.
3.
SPECIAL FUNCTION 03/04 - 2234/2244 HOPPER CARD READER
(a)
Reset the card reader with at least 30 of the same type
cards.
(b)
On the 2200, key Run, Execute.
(c)
The CRT displays the results of each card read.
(d)
Observe the CRT for any change in characters as the cards are
being read.
4.
DUPLICATING TEST CARDS AND PUNCHED TAPES
(a)
Cards - Samples of the 17 card, Model 2214 test deck are
found on pages 7-11 through 7-19.
7-22
(b)
Tapes
1)
The follow1ng 1S the contents of Tape #1.
To produce th1S
tape, key the following characters [rom a teletype keyboard-
)
567890987
J spaces\
1
SPCl( l
ABC"DEFGHI JKLMNOPQRSTUVWXYZ01234456 789 ! "#$%&' () *~-@+? >< 1t / .• A~DF
t
I
~
12 J4'
DATA PUNCHED ON PAPLR TAPL - 2201 [LSI
3"
T
A
U
%
B
V
&
C
W
F
D
X
SPACE
E
Y
F
Z
G
0
H
1
A
lJ
SPACE
*
SPACE
2
@
J
3
K
4
+
L
4
6
M
6
N
7
8
0
8
9
P
9
<
0
9
Q
R
S
8
II
SPACE
3" Blank Leader
END
)
7-23
2)
To duplicate Tape ff2, enter the following program into
the 2200's memory:
10D1M C$1,D$1,E$2,F$1
20C$=HEX(00)
30D$=HEX(01):E$=HEX(4l42)
40F$=HEX(00)
50G0SUB 210
60F0R l=lT0 256
70ADD(C$,01)
80DATA SAVE BT/41D,C$
90NEXT
100DATA SAVE BT/41D,D$
1l0DATA SAVE BT/41D,E$
l20F0R P=2T0 10
130ADD(D$,19)
l40F0R 1=1 T0 P
l50DATA SAVE BT/41D,D$
l60NEXT
I
l70DATA SAVE BT/41D,E$
l80NEXT P
190G0SUB 210
200ST0p
2l0F0R Q=lT0 30
220DATA SAVE BT/41D,F$
230NEXT Q
240RETURN
Key
RUN EXECUTE
on the teletype.
while holding the "Lock On" button down
This button must be held during the entire
punching of the tape.
NOTE:
These tapes must be punched on an EIA Standard
RS-232 Compatible Teletypewriter.
7-24
7.5.2
OUTPUT SYSTEM DIAGNOSTIC
This diagnostic cassette checks the following output devices:
2201, 2202, 2207, 2212
2221, 2231, and 2232
LOAD the tape and Key RUN, EXECUTE for instructions on conducting
individual peripheral tests (listed on Display console).
7.5.3
MODEL 2207A/2227 DIAGNOSTICS
A test procedure has been set up for the Field Engineering Division
to communicate with WYLBUR, PHI's IBM series 360 computer.
The test pro-
cedure will be used to assure the customer that 2200 TC units are functioning properly.
IMPORTANT
THESE TESTS WILL NOT BE USED FOR DEMO OR TRAINING PURPOSES.
)
The WYLBUR test procedure describes how to sign on to WYLBUR,
and to playback a test in WYLBUR's memory.
In order to use these test procedures you must obtain the "keyword"
from a Home Office Field Engineer.
Since the keyword is frequently
changed, access to WYLBUR would be impossible without first obtaining
the latest keyword.
Before contacting WYLBUR for a 2200/2227 telecommunication test,
run the off line 2227 diagnostic (with test connector), described below:
This diagnostic cassette has five -07A/27 telecommunications tests.
The first block is a general 2207A/2227 OFF-LINE test for 2200 A or B;
the second block is a Model 2227 ON-LINE test (System 2200-to-System
)
7-25
2200 via modems); the third block is a 2207A/2227 OFF-LINE test for
2200B CPUs
only;
the fourth block is a Model 2207A ON-LINE Teletype
test; the fifth block is the WYLBUR diagnostic.
To load any diagnostic on this cassette, rewind, key CLEAR, EXECUTE,
LOAD, EXECUTE, RUN, EXECUTE and follow the instructions listed in this
section, along with those listed on the CRT.
(a)
Plug RS-232-C Cannon test connector* into Model 2207/2227 controller
(b)
Set
PC.
RCV switch to HEX 19 (Model 2207/2227)
Set XMT swi tch to HEX lD (Model 2207/2227)
Set EOM switch to HEX OD (Model 2227 only)
(c)
(d)
Plug controller board into CPU and turn System 2200 power ON.
For Model 2207, set the red ASCII/BINARY switch to the BINARY
position (DOWN).
This will select 8 bits per character with no
parity.
(e)
For Model 2227, set switches NBl and NB2 to the UP position (8 bits
per character).
(f)
For Model 2227, set OPS switch to either UP or DOWN position (not
critical) .
(g)
For Model 2227, set PAR switch to the UP position (no parity).
(h)
For Model 2227, set SB to the UP position (2 stop bits).
(i)
RUN, EXECUTE
(j)
Enter 64 characters on Model 2215/2222 keyboard:
:ABCDEFGHIJKLMNOPQRSTUVWXYZ0123456789: ; <=>? ! "11$%&' 0*+, -. / [ 1t-<-ABC
(k)
Enter "YES" for continuous test loop or "NO" for one test run.
(1)
If characters are received into display exactly as sent, OFF-LINE
test verifies good.
Turn System 2200 power OFF.
Remove RS-232-C
test connector from controller board.
;"H~)-2'\2 Cannon Special Test Connector:
IIDB-25P; WI.. 11350-1030 (Hale) or
DB-25S; WL 11350-1031 (Female).
Pins 2 and 3 are wired together; pins 4 and 5 are wired together;
and pins 6, 8 and 20 are wired together.
7-26
BLOCK #2 (MODEL 2227 ON-LINE)
(a)
This test may be used in the event of a WYLBUR test failure.
Connect RS-232-C cable from Model 2227 controller board to modem.
Both Home Office and remote terminal must use the same or compatible
modem type.
(b)
Call 617-851-4111, extensions 2124, 2125, or 2126 between 9 a.m.
and 4:30 p.m. EDT, Monday through Friday.
(c)
Home Office:
(d)
Remote Office:
(e)
Enter data shown in OFF-LINE test.
(f)
The Home Office should display data received from remote Model 2227.
(g)
key special function 00 (System 2200) to TRANSMIT DATA.
Reverse procedure; that is, Home Office keys 00, remote office keys
01.
(h)
key special function 01 (System 2200) to RECEIVE DATA.
Send data.
Remote office should display data received from Home Office Model 2227.
BLOCK #3 - 2207A/2227 OFF-LINE Test For 2200B Only
The instructions for this test are listed on the CRT.
BLOCK #4 - MODEL 2207A (Teletype ON-LINE Test)
Since the mechanical paper tape reading mechanism of TELETYPE units
may also be used with the System 2200, the following test will verify
TELETYPE punch/reader operation.
(a)
With System 2200 power OFF, connect RS-232-C cable from Model 2207
controller to TELETYPE unit. (ASCII/BINARY SWITCH DOWN)
~)
Turn System 2200 power ON.
(c)
Clear System 2200 RAM (CLEAR, EXECUTE).
(d)
Reset System 2200.
(e)
LOAD 2200 Output Writer System Tape.
same test.
)
(The 2207,27,50,52 tape has the
See Service Newsletter #3-5, General section, item #2.)
(f)
RUN, EXECUTE.
(g)
Follow instruction on CRT.
(h)
All operating instructions for this diagnostic are printed on the
CRT.
7-27
This diagnostic performs two tests:
1)
OATALOAO/OATASAVE (Indicates "OK" or "ERROR")
2)
OATALOAD BT/OATASAVE BT (Indicates "OK" or ERROR")
NOTE:
When DATALOAD BT/DATASAVE BT test is being run,
hold Teletype punch ON button down.
BLOCK #5 - WYLBUR TEST
If Block #1 verifies good for 2227, proceed with the following:
Set address switches to:
RCV
HEX 19,
BAUD RATE:
XMT
HEX 10,
EOM
=
HEX 11
Set baud rate switch to 300 baud.
NUMBER OF BITS:
Set NBI switch DOWN and NB2 switch UP for 7 data bit
structure.
PARITY:
Set PAR switch DOWN and OPS switch UP for even parity.
STOP BITS:
Set stop bit switch UP for two stop bits.
Resultant switch settings should appear as follows:
UP
- 110
UP
150
DOWN - 300
UPUP
600
}-M"O AA~
- 1200
DOWN - NBI
UP- NBZ
J-
NUMBER OF BITS
DOWN -PAR
UP -
/)')r
PARITY: DOIm-CVEN PARITY
UP - 1 STOP SIT:
DOHN-2 STOP BITS
7-28
TEST:
1)
Dial WYLBUR at 617-646-9600.
2)
If using a model 103 modem (or 103 equivalent), wait for carrier
tone and then press "data" button.
3)
If using acoustic coupler wait for high pitch sound from telephone
and place receiver down into cups located on coupler.
A light
will illuminate on coupler when carrier tone is established.
If
not, redial WYLBUR.
NOTE:
The coupler should be set for full duplex operation.
EXAMPLE: On OMNITECH coupler, both switches located
at rear of coupler must be out.
4)
Key special function 00 for 2200A; 01 for 2200B.
5)
Enter the word "GTWX" from keyboard and EXECUTE.
6)
The computer will respond with "Wang Computer Service".
If this
does not occur, repeat step three (3).
7)
The computer will again respond with "TERMINAL?"+ENTER "W33"
then C/R.
8)
The computer will respond with "INITIALS?" ENTER "FES" then C/R.
9)
The computer will respond with "ACCOUNT?" ENTER "FS" then C/R.
10)
The computer will respond with "KEYWORD?" Enter keyword obtained
from Home Office) then C/R.
11)
The computer will respond with "COMMAND?".
)
7-29
You are signed on to the computer system.
If you want to play out the
program which is already in the computer, follow procedure below.
The steps below follow step 10 of sign-on procedures.
1)
ENTER "USE 2200 ON W3J002" the
2)
The computer response "COMMAND?" ENTER "LIST UNN", the C(R.
3)
C(R.
The computer will then send the test and it will be displayed on
CRT.
1)
This is a 2200 T.C. test.
2)
The 2200 can operate at 110, 150, 300, 600, and 1200 baud rate
depending on modem.
3)
The bell 103A or compatible can operate at up to 300 baud(while
bell 202C up to 1200 baud.
4)
The 2200 system can be selected for 5 to 8 data bits per character.
5)
The even or odd or not parity is switch selectable.
Also 1 or 2
stop bits are switch selected.
6)
The 2200 T.C. uses half duplex mode which means it cannot receive
and transmit at the same time.
7)
You must have received seven lines and this is the end of transmission.
4)
When the test is completed the computer will respond with "COMMAND?"
5)
The computer will respond with "COMMAND?"
ENTER "CLR ACT" C(R.
Ii)
ENTER "SIGNOFF", then C(R.
l)
The computer will respond with "OK TO CLEAR?"
8)
ENTER "CLEAR", then C(R.
Y)
The computer will
~~ivc
statistics on how long the terminal has
been signed on, etc.
10)
The computer will send "END OF SESSION"; this concludes the test.
7-30
1.5.4
MO~EL
2221W ryIAGNOSTICS
OPERATING INSTRUCTIONS
1.
Load tape or disk
2.
Key Run, Execute
(CRT will display available Special Functions)
3.
Key desired Special Function Key
SF
00 - Selects CRT for all Print statements and gives list
available Special Functions
SF
01 - 2221 Diagnostic - Checks printer characters as well
as functions.
Program is written specifically for
a 66 line/page form.
When used with other lengths of form, the printout
will be interrupted by the automatic top of form.
However, all functions and characters will still
be checked.
SF
15 - Continuously sends space codes (Hex 20) to printer,
Must be used to adjust timing of strobes for print
solenoids.
Insures that solenoids do not fire
while adjustments are being made, thus preventing
the print wires from tearing the ribbon.
SF
14 - Continuously sends character strings to printer
for quality test.
To repeatedly send portions of the 2221 diagnostic to the printer,
the GOTO statement can be inserted to loop on portions desired.
For
example, if the audio signal doesn't function, the procedure should
be to continuously send the code, Hex (07) to the printer and trace
it with a scope.
To do this, just insert in the program a GOTO
statement at the end of the audio routine, looping back to the beginning
~)
of tile routine.
7-31
7.5.)
MODEL 2224 & 2230 MXA/MXB DIAGNOSTIC
In order to run this diagnostic, the 2200 CPU and disk unit
(2230, 2240, 2242, 2243) must be operative.
The programmable hog mode
is checked by the test; the manual hog mode must be checked manually.
OPERATING INSTRUCTIONS:
1)
Turn on all pertinent units.
2)
Load tape, REWIND.
3)
CLEAR EXECUTE
LOAD EXECUTE
RUN EXECUTE
4)
Follow directions and answer the questions displayed on the CRT.
7. ;.6
2230/2260 DIAGNOSTICS
2230/2260 DISK HARDWARE DIAGNOSTICS
This diagnostic is very similar to the 2230 Disk Hardware Diagnostic.
It can be used on both the 2230 and the 2260 models.
INSnUCTlONS
1)
CLEAR, EXECUTE.
2)
LOAD, EXECUTE.
3)
RUN, EXECUTE.
4)
The CRT displays the following:
ENTER I, 2, 3, or 4.
1 -
- 2230-1 Disk Drive
2 -
- 2230-2 Disk Drive
1
4
2230-3 Disk Drive
~
-
2260 Disk Drive
7-32
5)
SNTER Y ()'es) or N (no) for the first test.
1hls t.est is long, and
may be skipped and returned to later.
This diagnostic checks the following:
(a)
WRITES and READS on every sector.
(b)
DATASAVE DA/DATALOAD DA using 1 to 10 variables.
(c)
DATASAVE DA/DATALOAD DA using Alphanumeric variables.
(d)
DATASAVE DA{DATALOAD DA using Alphanumeric arrays.
(e)
DATASAVE BA{DATALOAD BA using Numeric and Alpha.
(f)
Numeric Sector Addressing.
(g)
READ after a WRITE.
Hardware diagnostics yield the following results:
TEST A:
FIXED DISK
ERRORS = X
Y.Z%
REMOVABLE DISK:
Y.Z%
ERRORS = X
Where:
X = Quantity of errors
Y.Z
Percentage; indicates number of sectors
failed vs. total number of sectors on
the disk under test.
TEST B:
FIXED DISK
Testing DATASAVE DA, DATALOAD DA. using from 1 to 10 variables.
Loop # ( ) Complete
(1 - 5 loop count)
REMOVABLE DISK
Testing DATASAVE DA. DATALOAD DA. using from 1 to 10 variables.
)
Loop # ( ) Complete
(1 - 5 loop count)
7-33
TEST C:
FIXED DISK:
Alpha-numeric variables
(1 - 5 loop count)
Loop # ( ) Complete
REMOVABLE DISK:
Alpha-numeric variables
(1 - 5 loop count)
Loop # ( ) Complete
TEST D:
FIXED DISK:
Alpha and Numeric Arrays
(1 - 5 loop counter)
Loop # ( ) Complete
REMOVABLE DISK
Alpha and Numeric Arrays
Loop # ( ) Complete
(1 - 5 loop counter)
TEST E:
FIXED DISK:
Testing DATASAVE BA, DATALOAD BA, using numeric and alphanumeric
sector addressing.
Loop # ( ) Complete
(1 - 5 loop counter)
7-34
REMOVABLE DISK:
Testing DATASAVE BA, DATALOAD BA, using numeric .md alphanumeric
~ector
addressing.
(1 - 5 loop counter)
Loop n ( ) Complete
TEST F:
FIXED DISK:
Read after Write at random locations.
LOCATION
nnlilin
TOTAL SECTORS
nnn
(1 - 260) count
(0 - 19,583)
REMOVABLE DISK:
Read after Write at random locations.
LOCATION
TOTAL SECTORS
IIllnnll
(0 -
111111
(1 - 260) counter
19,583)
\<hen TEST F completes, the cassette automatically rewinds and reload5
the first block, to allow continued testing.
NOTE:
A failure in tests B through E produces "STOP ERROR" on CRT, and
processing halts.
A failure in test F produces ERROR 85 on CRT.
)
7-35
2230/2260 tHCRO-CODE DIAGl'I::JSTICS
This diagnostic is exactly the same as the 2230 MICROCODE Diagnostic
except that it has been expanded for the 2260 addresses.
INSTRUCTIONS
1)
CLEAR, EXECUTE.
2)
LOAD, EXECUTE.
3)
RUN, EXECUTE,
4)
ENTER 1, 2, 3, or 4 for the following:
1 -
2 - - - - - -
2230-1 Disk Drive
2230-2 Disk Drive
2230-3 Disk Drive
4
2260 Disk Drive
This diagnostic checks the following instructions:
DATALOAD/DATASAVE DC OPEN
DATALOAD/DATASAVE DC
DATALOAD/DATASAVE DA
DATALOAD/DATASAVE BA
DSKIP, DBACKSPACE
VERIFY
LIMITS
MOVE END
CATALOG INDEX
SCRATCH DISK
COPY
MOVE
DATASAvi DC CLOSE
SCRATCH
A test passed prints "OK" on the CRT; a test failure results in
"ERROR" on the CRT.
7-36
1.5.7
MODEL 2230 MXA & MXB DIAGNOSTICS
See
par~gr3ph
7.5.5.
MODEL 2234/2244 DIAGNOSTICS
7.5.8
7.3.8.1
Electromechanical Tests
There are four card reader errors that are detected and displayed
on the light panel of the 34/44.
1)
Read Check
2)
Pick Check
They are:
3)
Stack Check (stacker full)
4)
Hopper Check (Hopper empty)
To simulate these errors in the 34/44, place card reader in local
status (card reader need not be connected to 2200) and place approximately
300 standard 80 column punched or mark sense cards in the card reader
hopper.
1.
Read Check - depress reset pushbutton to initiate card feeding.
Place one hand on top of card stack and press firmly until the
picking and feeding of cards becomes slightly erratic.
This
pressure is meant to alter the constant speed of the card as it
passes beneath the read head.
With the correct pressure (a little
experimentation will be necessary here) a read check error can
be produced.
2.
Pick Check - depress reset pushbutton to again initiate card
movement through the card reader.
Place one hand on top of the
card deck and apply sufficient pressure to prevent the picker
section from actually selecting the next card and sending it
into the drive rollers that guide the card beneath the read
stdtion.
The picker section will attempt to pick the card six
times and then, i f a card is not sent through the reader in this
)
time frame, a pick check error is produced.
7-37
Stack Check
wInch lS also called stacker full, can be Slffiply
pull~ng
checked by
downward the stacker bln whu:h recelves cards
that have been read by the card reader.
behlnd the stacker Inn wInch
by a full load of cards
18 suspected,
There 18 a IDlcrOswltch
actuated when the bln
18
18
depressed
If thlS test falls and a bad ffilCro"wltch
depress reset pushbutton to lnltlate card flow dnd
place one hand, palm up, In the stacker seetlon near where the
cards are fed out from the read statl0n.
The deslred result 18
to slow or stop a card as It passes from the read statlon and
slffiulate a deck of cards flillng the stacker, wlth no more room
for any cards to be fed through the reader
4
Hopper Check - also called hopper empty can be lnltlated by
lnltlatlng card flow and llftlng the deck of cards ln the hopper
to be read, so that the m1croswltch located at the bottom of the
hopper wlil sprlng upward
ThlS wll1 lndlcate a hopper empty
(no cards ln hopper) condltlon and lilumlnate the error llght
Data Tests
3.2
The
te'-.t dl'-,Cr"lbed hllow verIfies proper 0IHr,tloll of
(nOCUMAI [ON M-200) or
2244 (DO( UMAl roN IM-2(0) whln
WAN(
I
1 WAN(
11',(
d
lJV.
WIll,
,
6534 I/O controller PC
ThlS test may be performed only wlth 80 column punch cards (2234) or
wlth 80 column mark sense cards (2244).
III
1111
I
01
I
r
II
III
I
I
I
I
I
II
I~ 3
I
I
II
1
I
II
1q
I I I
I 1'1
I
I
Iq
11
1111
II
III
I
I
I
//1/1//7111117111/
I
I
'n
I
I
II
Ill)'
11
' I
111111
11
I
..
I
I
R9
I'
I
..1'1
III I
I
I I
~~~I"'n1
I
I
I
I II
1111
I 11 I
I
I
II
II I 1111 I
I
I
,
II
I
I I III I
I
I
,
"
I I
I I
I
I
II I I I II
fi I Ou'llool
,
1 11 ,II
Use the followlng card format
I
II
.
III
1'1 I 181IB8R~IR'881~qq"'1 131'38~q'lllllll IIII
"119
191'J1"'
'nq]
ql I"
1
, ,
S
~
7-38
L'1ch card read nerforms one complete te<;jt loop
lnstruct.lons for operatl.on are as follows
(a)
Place INPUT SYSTEM DIAGNOSTIC cassette 1n 2217 tape dr1ve, close
drlve door,
rew1nd cassette.
(b)
CLEAR, EXECUTE.
(c)
W,th 2234/44 ON, load a stack (5 to 10 d1agnost1c test cards)
1nto the reader 1nput hopper.
(d)
(l)
(f)
Press RESET on the card reader.
LOAD, EXECUTE
KlY <-,pC'cl'1l
functIon
03
for rLldlnl, 1I0IIIIUIII dltl
04
lor re,d,ng IIINARY d,ta
The proper block on tape w1ll be automat1cally loaded and card
read1ng w1ll beg1n.
(g)
If any errors occur, the HEX values read wlll lmmedlately be displayed
on the CRT.
Comparlson to predeternnned "good data values" (see [
should reveal the symptoms of a reader/controller problem.
7.5.9
7.:'.9.1
MODEL 2234/1 OR 2244/1 IJI/lr,NOSrICS
See Paragraph 7.5.8.J.
Data/Program Tests
)
7-39
1)
ASSEMBLY OF 2234A/44A TEST CARD DECK
"44.\
/~.~~
°7~
22~4~A~§~~i~~i~~~~~~
22l,4A
' - - - t n ' C'T'
' - - - - - - r h i r c i Pros:. Deck
' - - - - - - - R l . : l l l k C,ITd
AT
' - - - - . . l P I A.l.1''--Uollerith Tr<l.ns.Deck
----E~d Care.
' - - - - - - - - 2nd ProgrOlIl: [J.'cl<
FIGURE
7-21
~-------IJlank
Card
'----'!D·~f,inat:y Data Deck
' - - - - - - - - - E n d C::Irc.
' - - - - - - - - - - l s t I't:c~:ral':l D~c.k
1.
Take the Program Card Deck and divide it into three respective
programs.
(Look for the END card at the end of each program,
it has an "E" punched in the BOth column).
The end cards for
each program appears as follows:
2.
1st program
1370 LOAD/62B
E
2nd program
1560 LOAD/62B
E
3rd program
1370 LOAD/62B
E
Take twenty cards of PRHV card, shown in Fig. #7-22, with a blank
card at the end of the deck and place i t behind the 1st program
deck.
3.
(Be sure to check for the number of cards).
Take 20 cards of each of the following card:
HTD-l, HTD-2, HTD-3,
HTD-4 and HTD-5, shown in Fig. #7-23, #7-24, #7-25, #7-26, and #7-27
and place a blank card at the end of the deck.
4.
Take 20 BO-co1umn mark sense cards and mark them, shown in Fig. 1/7-2B,
with a No. 2 pencil.
Place a blank card at the end of the mark
sense deck.
5.
Take a deck of the Wang Special Educational Program cards and
mark them as shown in the sheets provided.
6.
Combine the decks and the program together, shown in Fig. 1/7-2l.
7-40
FIGURE 7-22; PRHV 1 SAMPLE CARD
L
I
1111111111111111111111111111111111111111
I II II II II II II II II II II II II II II II II II II II I
10 10 10 I 010 1.10 I 01' 10 1'1'1 010 I" I 010 I 0I 0I cI 0I' I" 1010 10 10 I 0Inl 0I 01'10 h 10 10 10 10 In 10
1e
1
1
~
1t
111,1 "
II ~ ~
111 : ,\ I; I Iii I I ~
l 111 ; :
~
~ ~i I s;'1
~
1 111 1
I ;i i ;;Ii II ;
i. :
iI ;;
i
i 'l,i
II I i i
ii ; ii ;
i
111112111' 11111111111' 111' 111' 11111111111111111111111111111111111111111111111111
.13311331133113311131133113311' 3113 3113 3III 3113 JII3 Jill 3113 ,113 3113 lll3 lill 3113 3I
/1414111414141'14141'1414141'1'141,11141414141'1414141'14141.141.1.141414141.141
,115511' 5115 '1155115 5115 ~ 115 5115 '115 511s 5115 5115 5115 5115 5115 5115 5115 ,115 51155115
'lslsl,I.I,I'I,I,I'I'16I'15161'I'I'I'I'16161,I,16I,I'1.lel,I'15161'1616I,16161,1
'11711171111711 1'117711 I'll I I 1111117111 11 111 11171117111111117117 U71111 I 1111 IIJ
.1.1. I. 18 hi. I. 181. I. 1.131'1' lsi' 13 I. I' I. I. lsi. 131' h h hl'l' Ill. I. 18 hi. I. Is I. I
11113119111'
911" 31199119111'111'
'II' III"
119
'119'
II" II' 9119 '119 'II'
911" II' 9119
,)'\1
,.
lJ"
tl:,,;
JSi"l
I' . . . .
"'1(\>1)>,\1
IUi1"11n'1J . . . . . 1ft
"I/ll/11'~
1;.lII~Oi".J'
)1.-"):15
FIGURE 7-23; HTD-l SAMPLE CARD
_
11 11
.... 1
1
•
0000000000" 00"" 0" 000000" 00000000111111111111111111111111111111110" 00" 0" 0000000n0
1
1i
~ ~
~~~ ~1
l;~ ; 711 ~ 1,1 : ~ 1 1 1 I ; ~'1 J; 1 1°; 11 ~ I 1 I
I II : \;III~ 1 1'1°; 1 )I!; II
IIII iii
;i ;; ;;;i
i
;; i 77;
;;oi
i
iii
iiii
111' 111111111211 11111111111' 1' , 1111112111111111111111111111111111111111111111111
'33 133 J333313333333 I 33 J3333I 3: 3 J J J 3133333 J3I 333 J333I 333 J3" I J3J3J 3l 3333,333 J3333
/444144444441.4444 4414444 44 414 444444144 4444414 444 4441444 444 414 44441. 4444 4444 44 44
J:r 55 51~ S 5 5 ~ "51~i5 5S 55 5155 55 5 5 sis 55 5 5S 515 5 5 5 5 5 sis 5 5 5 5 5 51555 55 ~
sis 5 5'35 J
5 5 5S 5 55 5 55 5
'; 566 515; 6'" 'Is' 5' 65'16 66 55' 51' 56566; I' 555' 6'166 66 6' ;1s5' 66' ,15 66' 6565' 6' 66' 66'
11171),111 111 I 11') 11 11 11///71111 1 ) 1) 11)11717') Ill) 11 11 III 11) I 11111 111) 111 111J'11
•••••••• 11111111.8 •• "" '11111111.""'" 11111111"" •••• 11111111 •••••• , •••• ,.,. I
99"
3"J I 9'"
9'" 911111111111111119
9999
999"" 99' '11111111111111119'
99999'r 9'
'" 99'
1 I'
' to
I
'111'
"
Dli} J! "g'
>1 llo'\
I ;,SHJ. I H'
of; lin
I ,r /'lin. fft
~
""~",,,, ~\
\00
~
FIGURE 7-24; HTD-2 SAMPLE CARD
1111111111111111111111111111111111111111111111111111111111111111
0" 000no 0" 000000" 0"" 00no 00no 0000011111111111111111111111111111111 000000"" 0"" 00" 00
,2 J
S I'"
0 1111. S; "
110llunl'l'111l Il"lCJ
J' I O'
•
H
••
}...
I I,;J to'
(;
'11"
'1 I 'l511n I tlO
11111111111111111111111111111111111111111111111111111111111111111111111111111111
221122211111111111111112211112211211111211112 211111/1111111111111111111111111111
PJ 313 33333313 33333313 333JJ 31J: 3333313 3 JJ 33313 33333313 l 3333313 33333l 3333333333333
/444144 4444414 444 44 414 44 44 4414444 44414 44 444414 4444 4414 44 44 4414' 44 414444 44 44' 444 4
.1 255 sis 5 5 ~ ~ ~ sls!l S 5 '5 S 5155 S '5 '5 '5 51~ '5 '5 '5 '5 '5 SIi'S '5 '5 '5 5 5115 5 '5 B 5515 '555'5 '5 515 '5 '5, 2 5 '5 '5 5 '5 '5 5 '5 55 55 '5
~
U 6 66616
)
J
0
Ii Ii 6 0 516 Ii Ii Ii Ii
0
"IoSIiI~
!
616 66 Ii Ii Ii 616 Ii 6 Ii Ii Ii 61s Ii Ii Ii GIi 616
0
Ii 6 Ii Ii 616 &66 Ii Ii .116 Ii Ii ~ Ii Ii Ii Ii Ii 66 Ii 66 Ii Ii Ii
Illll r /lllll11 11' 71) 11 lI1111111IJ 17) II )lllll111111111!111))) I 111,) 117/7111111 11
• B88B8•• 11111111., 88" B'1I111111B 88••• 881111111188 •• " 8811111111'"' 88.8 •• 8.88.81
99'" 9J9"99999"
99911111111111111119'
9999"'"
9999911111111111111119
99" 9" 9" 9' 9'
9
1'010'
111C II
' S I 0;':'"
'\IllS
31, • • I •••••
'I'lll I
"'0
~\III;l\j~O'1l
j;
7-41
.~
~U.'10"IJ.t"
FIGURE 7-25; HTD-3 SAMPLE CARD
l\..f..f( T;:
FI_I-
:.
\ .... 11
h
I
~
(
I ... ,I
-
;'. 1 ",'-~
.'
1111111111111111111111111111111111111111111111111111111111111111
00000000000000000000000000000000111111111111111111111111111111110000000000000000
II J
t,
1"
!'OllIlQMIiI_I1I1I1"'f1nn1l14l''''lI''111JGll:t1", ...; IJ ~);1ll"'1'''• •, . ,,,.~
'llj"~"~I>lo HO'lil~"l.>nil~"1':lnltnl<l~'lnlll~JO
11111 1 1111111 111111 1 I 1 111111 I 111111 I I 1 1 I I I ' 11 I I I 111 1 11 I I III t I I II 1111 t I 11111 11 \1 I
22122222221222222212222222122122221222222212222222122 2 2 2 2 212 2 2 2 2 2 2 2 2 2 2 2 2 2 2 222222
, 3 313 3 3 3 3 3 313 3 3 3 3 3 313 3 3 33 3 313: 3 3 3 3 313 3 3 3 3 3 313 3 3 3 3 3 313 J 3 3 3 3 3133111111111111111111
/4441444444, 1444444414444 4 4 414 4 4 4 4 4 414 4 4 4' 4 414 4 4 4 4 4 414 4 4 4 4 4 414 4 444114444 44 4 I 4 4 4 4
J55551'5555551555555515555555155555551555555515555555155555551555;55555555555555
.; II &&1& 0 &. &6 &1& &&&&; 61& &&&&6 &1& &&&&&&1& &&&&&'1& 6 6; &&&16 &&&&&61& &6' 6 6 &&&&6 &&&&6 &
111 1 1 1) III 1 11111' II 1 II11I11I 1 I 1 11 1 1 1 1 1 1 I 1111111 II 1 1 1 1 I1111I 1 1 I 1 II 1 II 1 I 1 III 1 II; 1 1
1111111111111111181811811111111181111111111111118811 1 11811111111111811181818&111
Itlt3 9 9999 9 9 9 9 9 911111111111111119 9 9 99 9 9 999199 9 9 9111111111111111199 9 9 9 9 9 9 9919 9 99 9
., I'"
111'OhI11.oIolnl' ' .... lGnU_ l.n"1I~~:lIJ1U"'J:iJll.l'l.'l·,·1UU ..... q.t~IIUS1~U"'~'!>I·!iWi'IJt..~~..... ,U" .. nIt tl)or,/5nll"'n
1111111111111111111111111111111111111111111111111111111111111111
1111111111111111111111111111111111111111111111111111111111111111
0000000000000000000000000000000011111111111111111111111111111111000 0 00 000 00 0 0 0 00
'lJ4S"tttOlll11JW;~li1J1!1!1II.ll1nl'2'I'lnllllOJ'll
' l ..
"",a • • •
"l<'"\'
~,
'j~'
IQflll.JU&".-;".UIl'JIlI2i3Jn!i"nIIIUO
111 1 1 1 I I 111 1 1 I 11 111 1 1 1 1 1 111 I 1 I 1 "11 I I 1 I 1 I 11 " I 1 1 111 1 I 1 1 1 I I ' 1 1 1 1 1 1 1 1 1 1 11 1 I 1 I 111 1 I
2212222222122222221222222212222222122222221222222 212 22 2 2 2 212 222222 2 222222222 22 22
/33133 3 3 3 3 3133333331333333 313: 3 3 3 3 313 3 3 3 3 3 313333333 (3 1 3 3 3 J 311 33 3 33 J I 3 33 1 33 33 3 3 3 1
/44414414844144444441444 '44 414 44 4 4 44144 I 4 44411 4 4 4 4 4 4144"'44144 41111111111111111
J55551'5555551555555515555555155555551555555515555555155555551555;,5555555555555
'0 &&6&1&' 6 6' 6 ,16& 6 6 6 &&1& 6 &6&& &1& 6 E&6 &&16 6 6 6 6 6 '1& 6 6& &6 &1& & &6 &6&16& &" 6& 6 &6 6& &6 &6 &
l l l l l l l l l l l l l l l l ' III lllill llllll1lll1 llill 111111111 III III llllll11J I llll II II ll;ll
111111111111111181888888111111111888186811111111881818 88111111111888 8118118 8 8181
919919999999999911111111111111119999999999199999111111111111111199 9 9 9 9 9 9 9 911 9 9 9 9
• J I I \ • I , • '0 " 11 IJ '" 1,15 II It I 20
n /1" '"1~ 16 11 :
D
:,:~,l'
,1 \J '14 l'
• ")" 'I t i l t
os_. I
q If
~e ~I
FIGURE 7-26; HTD-4 SAMPLE CARD
7-42
>1 S):>'
~1
'16
~ ~ ~~~a"
lJ Cl i-l.\ f... " N &s 10
nq
/1 II IJ " II
n" 10
FIGURE 7-21. HTD-S SAMPLE CARD
0000000000000000000000000000000000000000001100000000000000000000000000000000011000
1 I
J'
'I
"
0
I JIoI ~ "I l:II!I10T"7
11 "'5"'i 11 lI"'1J11 J1
n »0/.
SJll .)lItO. O,I'J"~ ",0""5415 »»~"11glol H"
»IUHHtI IfU1'JlIl1IlM>!i1'571111tR
111111' 111 11 111111 1I '1111111 11 1111 11111111 1111 11111111 1111 I 111111 111111 111111 111
12222211111222222222212222211111221222222222222222222222 222222211 222222222222222
/13333133331111,3333331333313: 33111133 333 3333333 3333311113,: 33 333 313 33 3333333333
141
'14' 414' 4111"" 41" 441'" I•• '111'''''''''''''' I'" III
,u
..
•sslss' 'Is ssl' slsslls 55 sis 5ssis sSis 515 5lis 5S555 5SS 55 5\15515 5115 51111111111111111
'.6 61i. 6.1" 'I' 'I' 1616 I i 61' '6 61' 6£ Ii 61i 1'1' 66I i 6. is 66661&i1i161i6" 6I i 66' 66I i 6' 6
1111111111111111' 11111111/1111111111111211111111111111111111111111111 2111111/ 11
I. II 8 11111111111. a 8' III1 a I ' S' III II'! IIIIIIII i 1111118' 1111'1 ~. 1"11111'111118 BII ~
'959]99 9 99 9 9 9 9 99 9 9 9 9 9 9 9 C19 9 9!U)g 9 9 9 9 S 9 9 9 99 9 ')9 9 99 9 9 99 9 "I 99 9999 9 9 9 9 9 9 9 9 99 9 9 99 9199 9 9 9
r I. ' . I' • 0
1113" "''' 11 .... 21"11 .. ,.IH.n~~n 1T1.. ... U.1 . " . "
111111111
HH'.St,.
"',$C$
Ulo:llolU'II' lotHY, IltH,U ... IUlllnl1 l . r "
"".
11111111111111111111111111111
I II II II II II II: II II II II II II II II II II II II II I
1111111111111111111111111111111111111111
11:,11 II II II II II II II II II II II II II II II II II II I
;1111111111111111111111111111111111111111
~Ii II II II II II II II II II II II II II II II II II II II I
6,1 I I I I I I I I I I I I I I I I I I I I I I I I I I I I I I I I I I I I I I I
!el
,I I
III
:1 I
II
I I
II
I I
II
I I
II
I I
II
I I
II
I I
II
I I
II
I I
II II
I I I I
II II
I I I I
II II .. II II II II
I
II
I I
II
I I
II
II
I I
II
I I
II
II II II II II II II II II II II
1,1 I I I I I I I I I 1'1'1 I I I I I I I I
II II' II II II II II II II II II
I I I I I I I I I I I I I I I I I I I I I I
II II II II II II 11.,11 II II II
I
I
FIGURE 7-28, 80-cnLUMN
I
MARK/SENS~
)
7-43
CARD
rO'lTf'lTS OF
w, (MARK SFNSE) PROGRAM DECK
srI LIAL
*ONE STATCMeNT PER GARD
III \11 I
I If ~
1111
r
11[
I
h
1
ITH
I
I
I
I
lr
I I
I
t1
!~
I I~
f
r
11
I
T
If
r HI
r
111
I
t
r I
1111
f-l
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SEC 2234A/2244A MATNTCNANCF MANUAL FOR CARD MARKING INSTRUCTIONS.
7-44
The test described below verifies proper operation of a WANG 2234A
(DOCUMATION M-200 with 6225/6449A WANG I/O Controller) or a WANG 2244A
(DOCUMATION TM-200 with 6225/6449B WANG I/O Controller).
)
The cards used are as follows:
(a)
With all units ON, ensure that the following switches are set:
2244A:
(b)
(c)
POSITION
SWITCH
2234A:
LOCAL/REMOTE
REMOTE
AUTO/MANUAL
AUTO
LOCAL/REMOTE
REMOTE
AUTO/MANUAL
AUTO
PUNCH/OPT. MARK
PUNCH
CLOCK/NON-CLOCK
NON-CLOCK
Key RESET on the 2200 keyboa rd.
Load the 2234A/44A diagnostic card deck into the reader input hopper
and key RESET on the card reader panel.
(d)
CLEAR, EXECUTE at 2200 keyboard.
(e)
Enter the following:
(f)
EXECUTE.
(g)
RUN,
10 LOAD/62B.
I':XECUTE.
The 2200 accepts a program (on punched cards) via the card reader.
(h)
This program, executed automatically, checks the punch read station
in the 2234A and 2244A by reading and checking the diagnostic card
deck.
DATALOAD BT (N=162)/62A (the Binary Data card) and DATASAVE
BT /42F (the Look-Ahead card feed) are tested.
)
The CRT displays
the quantity of cards read, along with a test fail/pass indication.
The next test loads automatically via card reader.
7-45
(1)
1111<..,
pr()~'rll1l
(!leck.., the lIo11erlth
trlnsl~tlon
of the controller board,
uSing DAIALOAD (N=82)/629 (the Hollenth Data card) and DATASAvr
BT /42E (the Look-Ahead data cards for Hollerith to A~CIT tr,ns] ition).
Flve separate card stacks wlthln the dlagnostlc are read
After the program is finished,
of the
card btacks have passed or fa1led testing.
of the 5 stacks fail,
~equcntl111y.
the CRT will display which (if any)
Also, if any
the CRT w1ll 1ndicate that 1f it is deSired to
cont1nue to the next test, key EXECUTE and the next test program on
cards Wlll be loaded.
I f the 5 decks are tested w1thout fa1lures,
the next program on cards 1S loaded automatlcally.
(J)
When the 2234A tes tends,
the remainder of cards
in
the d1agnostic
deck Wlll be mark sense type, and cannot be read by a punch read
stat10n.
(k)
Change the follow1ng sW1uh settings ('n th" 2244A card reader
PUNCH/OPT MARK
OPT MARK
CLOCK/NON CLOCK
CLOCK
(1)
Key RESET on card reader.
(m)
Key EXECUTE to resume.
(n)
Th1S program reads and checks a mark sense card (WL #700-1222) type
1n a deck, uSing DATALOAD (N=162)/62A (the Binary Data card) and
DATASAVE BT /42E (the Look-Ahead data card).
(0)
Next, key EXECUTE to load spec1al mark sense program cards (Wang
Format; WL #700-1224).
The result1ng program Wh1Ch 1S loaded
executes automatlcally.
Upon completlon of thls program, the
follow1ng appears on the CRT.
5E5 E5 [5 E5 F5 [5 F5 E5 E5 F5 E5 E5 E5 ESE5E
tttttttttt 0
TRANSFER
1
STOP
FND
TO
OF
2
4
FIGURE 7-29
250
TEST
7-46
This ll'sl
st.'nSl~ {"ilrds.
7.5.10
verifIes .111 BAS[C commands and formula from \.J;lI1f', mark
IIHlng the LOAD/62C cOITDnand.
MODEL 2240/2242/2243 DIAGNOSTICS
The 2240/2242/2243 diagnostics (hardware and microcode) replace
the 2240 only tests.
Prior to running any disk diagnostic, insure
that the switches on the 6375, 6541, or 6541-1 board are set to HEX 010.
2240/2242/2243 MICROCODE DIAGNOSTIC (VERSION 6/25/74)
The 2240/2242/2243 Microcode Diagnostic checks the following
instructions:
(a)
DALALOAD/DATASAVE DC OPEN
(b)
DATALOAD/DATASAVE DC
(c)
DATALOAD/DATASAVE DA
(d)
DATALOAD/DATASAVE BA
(e)
DSKIP, DBACKSPACE
(f)
VERIFY
(g)
LIMITS
(h)
MOVE END
(i)
CATALOGUE INDEX
(j)
SCRATCH DISK
(k)
COPY
(1)
MOVE
(m)
DATA SAVE DC CLOSE
(n)
SCRATCH
An approximate time is displayed on the CRT for each test; this is
the maximum time needed to check a 2243.
for the smaller capacity units.
The length of time decreases
The test automatically rewinds the tape
and repeats the diagnostic indefinitely if no error conditions exist.
)
7-47
1)
Equipment Needed:
2200Bl (4K memory minimum)
2216/2217
2215 or 2222
2240, 2242, or 2243
2)
Operating Instructions:
(a)
Format all disks to be used if not already formatted.
(b)
Insert tape into tape drive and rewind.
(c)
Key:
CLEAR EXECUTE
LOAD EXECUTE
RUN EXECUTE
(d)
(e)
Key correct number, EXECUTE.
To restart a test that terminated due to an error, key:
RESET RUN EXECUTE
2240/2142/2243 HAlDHAL DIAGNOSTIC
The 2240/2242/2243 Hardware Diagnostic checks the following instructions:
(a)
TEST #1 - Writes at every sector address and reads the information
(b)
DATASAVE DA, DATALOAD DA from 1 to 10 variables.
(c)
ALPHANUMERIC VARIABLE
to check for errors.
(d)
ALPHANUMERIC ARRAYS
(e)
DATASAVE EA, DATALOAD BA using numeric and alphanumeric sector addressing.
(f)
Read after write at 260 random locations.
Tests b, c, J, and e run five loops per disk drive.
It is advisable
to skip TEST #1 the first time because of the length of time required to
complete TEST #1.
After tests b, c, d, e, and f are completed, the
program automatically rewinds the tape and runs TEST #1.
NOTE:
MODEL 2240 DIAGrWSTIC ERRORS
ON NEXT PAGE.
7-48
DOCUr~ENTED
Tile last program o[ the Hardware Diagnostic contains an error (2240
l~{'.ld
.Jfter \.Jritp at Random Locations).
Statement 60 reads:
L = 1024* C-l
Change statement 60 to read:
L = 512* C-l
To correct the tape, key the following:
1)
CLEAR EXECUTE
2)
SKIP 6F: LOAD EXECUTE
3)
60 L=5l2* C-l EXECUTE
4)
BACKSPACE IF
5)
SAVE (lnsure tape protect is closed)
6)
Remove tape and open tape protect.
MODEL 2240 PROGRAMMING PROBLEM
The following sample program illustrates how an error code 25 is
generated.
10
SELECT III 310, 112 BIO
20
S
30
200
40
0
2
GO SUB , 100
50
PRINT S
60
STOP
99
DEFFN' 100
100
DATASAVE DA 110, (S,S) END
110
RETURN
Because an end of file is written on the disk and a return is executed
for the GOSUB' 100, and error 25 will result at statement 110.
If the
DATASAVE DA #D (5,5) END was used for saving array or data, no error
would occur.
7.5.11
)
MnnEL 7241 DIAr.wnQTIr
Check the 2241 with the 2231 diagnostic contained in the "2200
Output Writer System Tape".
7-49
OPERATINC INSTRUCTIONS
--
1)
Turn on all pertInent unltS.
2)
Insert t'lpe luta tape drIve, depress RFWIND.
3)
Key
CLEAR EXeCUTE
LOAD EXECUTE
The Tape dr1 ve loads several blocks and stops
RUN EXECUTE
The CRT 1S d1splay1ng 1nstruct10ns for runn1ng
dlagnostlcs for varIous deVlces.
If no 'lcknowledge pulse 1S supp11eu to the 2250 from the external
dev1ce,
the dev1ce can reset RBI from a low (busy cond1t10n) to a h1gh
Th1S L~H trans1t10n from the dev1ce w1ll result
(ready cond1t10n)
1n L34-8 be1ng clocked
L~H,
so that RB goes low (L36-5 enabled h1gh)
Incllcatlng to the CPU that the deVIce
7 ) 12
"lS
ready.
MODEL 2250 DIAGNOSTIC
M1n1mum Equ1pment Needed
(a)
D1agnost1c Test Tape
(b)
Two D1agnost1c Connectors (See pages 34,35)
(c)
2200/2250 System
1)
Before 1nsert1ng 2250 1nto the CPU, set 2250 address sW1tch to HEX 3E.
2)
Turn 2200 system off and 1nsert 2250 1nto CPU I/O slot. (DO NOT FORCE
3)
Turn 2200 system on.
PC BOARD).
The 2250 d1agnost1c test occup1es one block of a mult1block system
dIagnostIC tape,
and IS run as follows
4)
LOAD, rXLCUfE
5)
RUN, EXECUTE
6)
KEY SPECIAL FUNCTION 14
7-50
At this point the 2250 test will be loaded:
THERE ARE TWO CONNECTORS FOR 2250 DTAG.
\lOTH DIAGNOSTICS MUST BE RUN
****************
KEY SPECIAL FUNCTION KEY 00 FOR CONN. III
KEY SPECIAL FUNCTION KEY 01 FOR CONN. 112
JUMP L7 PINS 8 AND 12 FOR CONN. 112 DIAG.
FIGURE
-------
7-30
KEY RESET TO STOP TEST
****************
*
SET SWITCHES TO 3E FOR THESE DIAGNOSTICS
*******************
A good diagnostic run appears as follows:
i'
(PASS II
xx
FIGURE
Pass Count
7-31
A failure appears as:
ERROR-TEST FAILED
FIGURE
STOP
7-32
The test connectors are constructed as follows:
CONNECTOR III
Put jumpers between Pin II (output) and Pin II (input) as listed
on the next page for Amphenol connector.
7-51
OU'!1'UT SI eNAL
PIN 1/
PIN 1/
INPUT SJ(;NAL
TERM
OUTPUT
INPUT
TERM
OBS
9,18,19
31
O
OBIO
OB2
0
OB3
0
OB4
0
OB5
0
OB6
0
OB7
0
OB8
0
-IBS,ACK,RBI
20
5
IB1
21
6
IB2
22
IB3
23
8
IB4
24
1
IB5
25
2
IB6
4
IB8
26
IB7
27
1
1
1
1
1
1
1
1
PARTS REQUIRED:
36 Pin Ampheno1 connector (male).
WL 1/350-2049 or 350-2051.
USE:
Attach this connector to 2250 controller card and run 2250 diagnostic
for connector 1/1.
CONNECTOR 1/2
Put jumpers between Pin 1/ (output) and Pin 1/ (input) as listed below
for Amphenol connector.
OUTPUT SIGNAL
PIN 1/
PIN 1/
INPUT SIGNAL
TERM
OUTPUT
INPUT
TERM
CBSU
16
9,18,19
COBI
COB
2
COB
4
COB
8
CPB
O
12
5
13
6
14
7
15
8
32
1
P~So
10
2
3
IRB
17
DORB
28
4
oV
34
11
7-52
IBS,ACK, RBI
IBI
I
illI
IB3
1
IB4
1
IB5
1
IB6
1
IB7
1
IB8
1
END I
PARTS REQUIRED:
36 Pin amphenol connector (male).
)
WL #350-2049 or 350-2051.
USE:
Attach this connector to 2250 controller card and run 2250 diagnostic
for connector #2.
7.5.13
MODEL 2252 DIAGNOSTIC
Equ~pment Requ~red:
2200B, 2252 diagnostic connector*, 2252 diagnostic
test cassette.
Instruct~ons:
1)
Set address switch bank to HEX SA.
2)
Attach diagnostic connector to 2250 controller card.
3)
Load diagnostic tape.
4)
Run, Execute.
5)
Press special function key 15.
6)
All switches on 2252 controller card mounting bracket should be in
the UP position.
)
7)
Press special function key 00 (Display:
8)
Run diagnostic for several loops.
9)
Reset 2200.
+??????????).
10)
All 2252 mounting bracket switches should be in the DOWN position.
11)
Press special function key 01 (Display:
12)
Run diagnostic for several loops.
7-53
-.0000000000).
Some Jiagnostic failures are due to an improperly wired diagnostic
connector.
I t has been found that when 40 pins are tied together
to the ground pin,
some of the connections remain open.
Threading
a hus wire through the hole in the center of the pins will help
solve this problem.
To check which pins are still open,
the
procedure below should be followed.
(a)
Attach connector to board
(b)
1\.11 switches up
(c)
(d)
10
SELECT INPUT 25A
20
INPUT A$
30
GO TO 10
Display should ap,Jear as:
+??????????
(?
(e)
=
HEXC3F)
If any pin is open on anyone or more digits, that digit
will drop bits.
From display and hex codes it can be
determined which bit is dropping.
The following procedure is also recommended as a quick checkout
for board along with diagnostic.
(a)
Do not attach any connector or cable to 2252
(b)
All switches up
(c)
10
SELECT INPUT 25A
20
INPUT A$
30
GO TO 10
(d)
Run
(e)
Execute
(f)
Display should look like this:
+0000000000
(g)
With sign and Data switch down, display should look like
this when the above program is run:
-??????????
7-54
2252 MICRO INTERFACE DIAGNOSTIC CONNECTOR
Bus together the following pin numbers on 50 pin connector:
PINS BUSSED:
1 through 16,19,20,21,22,23,24,25,26,27,28,29,30,32,33,34,37,38,39,40,
41,42,43,44,45,46,47, and 48.
Also connect pins 18 and 31 to each other, but not to the above pins.
PARTS REQUIRED:
50 Pin Amphenol Connector (male), WL #350-2027.
USE:
Attach this connector to 2252 controller card to run diagnostic.
7.5.14
MODEL 2261 DIAGNOSTIC
The 2261 uses the 2221 diagnostic contained in the "2200 Output Wr j tpr
System Tape".
All output is identical except for HEX codes SE and SF,
and the expand function.
Operating Instructions:
1)
The 2261 I/O controller board must be set to address 15
16
2)
Turn on all pertinent units; select the 2261.
3)
Insert tape into tape drive, depress REWIND.
4)
Key: CLEAR, EXECUTE.
LOAD, EXECUTE.
RUN, EXECUTE.
The tape drive loads several blocks and stops.
The CRT is displaying instructions for running
diagnostics for various devices.
5)
)
Key: Special Function 02.
The tape drive loads the 2221 diagnostic
and displays instructions.
7-55
7.5.15
MOIJ},'L 2262 DIAr;NOSTIC
OPERATING INSTRUCTIONS:
1)
Plug cursor into digitizer and place near center of tablet.
2)
Select the Switch Stream Mode on the control panel.
3)
Load the 2262 diagnostic.
RESET, RUN, EXECUTE.
The following is
displayed on the CRT:
2262 TEST
SIGN BIT
(NEG-NO BUTTONS)
FLAG SWITCH
(0,1,2,4)
X-VALUE
Y-VALUE
0
XXXX
YYYY
X LIMITS
0000-1999
0001-2001
30 x 40 In. Tablet
0000-3999
0001-3001
36 x 48 In. Tablet
0000-4799
0001-3601
WHEN TEST IS COMPLETE HIT RESET
4)
Y LIMITS
20 x 20 In. Tablet
& SPECIAL FUNCTION KEY 15.
The 2200 should be reading coordinates, the 2200 ready light on the
digitizer should be flashing and the proximity light should be on.
5)
Depress the Z-axis button.
Insure that the sign changes from minus
to plus and a set of coordinates is constantly being displayed.
Release Z-axis button.
6)
Depress Flag #1.
to 1.
7)
Depress Flag #2.
to 2.
8)
Check for sign change and that flag bit changes
Release Flag #2 button.
Depress Flag #3.
to 4.
Check for sign change and that flag bit changes
Release Flag #1 button.
Check for sign change and that flag bit changes
Release Flag #3 button.
7-56
9)
Place cursor at left margin approximately in the center of the
tablet.
10)
Select the High Stream Rate.
Move the cursor very slowly from left
to right checking that X begins at coordinate 0000 and counts in
units up to 0009.
Check all digits from tens to thousands by
continuing to move the cursor toward the right margin.
The last
count in the X direction is 1999 for a 2262-1.
11)
Place the cursor at the bottom margin near the center of the tablet.
Move the cursor very slowly from the bottom of the tablet to the top
checking that the Y begins at coordinate 0001 and counts in units
up to 0009.
Check all digits from tens to thousands by continuing
to move the cursor up the tablet.
The last count in the Y direction
is 2001 for a 2262-1.
12)
Select the Single Point Mode.
Digitize approximately 5 random
points on the tablet by depressing the
while moving the cursor.
~
axis and Flag Switches
Ensure that the Flag bit and coordinates
change each time the appropriat" switch is depressed.
The SIGN
bit should change only the first time a button is depressed.
13)
Select the Switch Stream Mode.
While depressing the Z-axis switch,
move the Stream Rate Slider Switch from low to high range, checking
that the number of points being digitized increases as the slider
is moved to the high range.
14)
Remove the cursor and connect the stylus to the front control panel.
15)
Select the Switch Stream Mode.
Check that the sign bit changes
from minus to plus when the stylus is depressed on the tablet.
Check that coordinates are being read by the 2200.
)
7-57
IISI I'IWCMM L 1,'( :
11-1 KEf 1
~-'2t'>'
l'lAGNocTIC
TEST
~(t
~Erl 131./213 . . :--5
s0 F.EII WArJG CUSTOMER ENGINEERING [>IVISION
40 ('1f'1 A$12
50 SELECT PRINT 205. WPUT GSA. CO 6SA
60 PI'. un HE'«020AllA0A)."
2262
TEST"
70 PRWT HE;>,<0A0A),"
SIGU BIT
FLAG SWITCH
X-VALUE
Y-VALUE"
80 FI' un HE".(0A).
"(NEG-NO BUTTONS)
(0.1.2.4)"
90 FF.un HEX<0A0A0A).
X-LIMITS
'''-LIMITS''
100 FPIUT HEX(OA'.
20 X 20 IN
TABLET
0000-1999
0001-2001"
110 PPUH HEX<0A).
30 X 40 IN
TABLET
0000-2999
0001-4001"
120 PPWT HEX<0A).
36 X 48 IN
TABLET
0000-3599
0001-4801"
130 FRIUT HEX(0A0A)
140 PRIUT HE,>«0Al." WHEN TEST IS COMPLETE HIT RESET & SPECIAL FUNCTION KEY :l!S "
150 IUPUT RS
160 FPUH HEXfl'l10A0AOAllAOAOAOA)
170 FPunUSING 180. STR(AS. L 1 ) . STR(AS. 2.1). STR(AS. 4. 4). STR(AS. 8. 4)
180
%
II
•
••••
..1111
f!l""-'"
1':;t0 GOlD 1'50
20U
210
2"a
230
240
250
['EFFW I")
SELECT PRIUT a05.TAPE 10A
PRINT HE/,(030A0A)
SELECT INPUT 001. CO 005
STOP " ENO OF PROGRAM"
REI1 S
7.5.16
,--"
MODEL 2209 DIAGNOSTIC
PART 1
This diagnostic contains four files:
#1 Dynamic Write
#2 Sequential Read
113 Random Read
#4 Results (Tables showing errors accumulated)
Operation
1)
Put diagnostic Part I into the system 2200 tape drive.
2)
Push the REWIND pushbutton.
7-58
3)
Key CLEAR EXECUTE.
4)
Key LOAD, RETURN/EXEC.
5)
When loading is completed, key RUN, RETURN/EXEC.
(Leave the cassette
in the system 2200 tape drive.)
From this point on the test (files 1, 2 and 3) operates automatically.
The test requires approximately 10 minutes per pass; there are 10 passes
in the test requiring 100 minutes.
When all 10 passes are completed,
END OF TEST is displayed on the CRT.
If less than 10 passes are desired and file 4 is to be displayed
(file 4 tabulates all accumulated errors):
1)
Key RESET.
2)
Rewind tape cassette.
3)
Key CLEAR P (clear program).
4)
Key SKIP 3F:
5)
Key:
LOAD (this loads file 4).
SF 01 prints Table 1 on the CRT, table 1 includes the error
results of file #1.
SF 02 prints Table 2 on the CRT, table 2 includes the error
results of file #2.
SF 03 prints Table 3 on the CRT, table 3 includes the error
results of file #3.
Error Information
The error information is interpreted on the separate tables.
Any
printout within the table area indicates the number, and the types of
errors that occurred when the specified operation was executed.
~59
~IAr.~0STIC
ABBREVIATIONS
ERROR CODE ABBREVIATIONS
RDY - Tape Ready
NER - Non Recoverable Error
PRT - Tape Protected
DTE - Data Transfer Error
EOF - End of File
BOF - Buffer Overflow
EOT - End of Tape
IVC - Invalid Command
BOT - Beginning of Tape
CNT - Count Not Equal
RER - Recoverable Error
OPERATION ABBREVIATIONS
WRT - Write
RRD - Reread
WCP - Write Gap
FSF - Forward Space A File
BWT - Backspace Write
FSR - Forward Space A Record
WFM - Write File Mark
BSF - Backspace A File
RDR - Read A Record
BSR - Backspace A Record
RDF - Read A File Mark
CLN - Clean
RD
- Read
DATA (FILE #) indicates the file number in which the error occurr~d.
ERROR # indicates the number of errors that occurred in a given data file.
PART 2
This diagnostic contains five files; the first file contains the
menu.
File 2 contains the General Diagnostic which provides a quick
check of all functions and operations.
File 3 contains the Error Verify
Diagnostic which checks for all error conditions but does not utilize
all commands used in the General Diagnostic.
File 4 contains the Function
Diagnostic which checks individual functions as displayed on the CRT.
File 5 contains the End of Tape Diagnostic which verifies the fact that
the 2209 can recognize the EOT marker.
7-60
OPERATING INSTRUCTIONS
To load the menu of Part 2:
1)
Insert diagnostic Part 2 into the tape drive.
2)
Key CLEAR EXECUTE.
3)
LOAD EXECUTE.
4)
When loading is completed, key RUN EXECUTE.
REWIND.
The menu is now displayed.
The General, Error Verify and Function Diagnostics can be run by
keying the appropriate special function key.
To run the End of Tape Mark
Diagnostic, place the 2209 tape at BOT by depressing the RESET and REWIND
pushbuttons on the 2209.
pushbutton.
When the tape is at BOT, depress the ON LINE
Place an EOT marker on tape between the file reel and the
file reel fixed roller guide; key special function key 19.
7.5.17
WCS 20/30 DIAGNOSTIC PROGRAMS
The WCS diagnostics are versatile and powerful tests contained
on a ·single diskette.
The tests consist of a:
Memory Test
CPU Test
Printer Test (2201, 2221, 222lW, 2231 and 2261)
Platter Verify Test (all disks)
Disk Instruction (CPU/Disk Microcode Test) (all disks)
WCS/Disk (Disk Hardware Test) (all disks)
An
allocation has been made for future peripheral tests.
During each test, any errors that occurred are displayed momentarily
or printed on the printer if a hard copy output was selected.
At the end of
all tests selected, an "OK" or "NG" message is displayed and printed
)
(if selected) for each test.
7-61
1)
Memory Test - Approximate running time is 5 min. for each 4K.
TIle memory test checks all RAM locations except those used by the
CPU for housekeeping.
the RAM.
The test uses high speed matrix verbs to exercise
This method detects errors in marginal RAM chips that could
not be detected with earlier memory tests.
2)
CPU Test - Approximate running time is 13 min.
This test checks most of the BASIC verbs used in programming
including the Matrix, GIO and Sort verbs.
3)
Printer Test -
Approximate running time is 6 min.
Models 2201, 2221, 222lW, 2231 or 2261 are able to be tested.
Six
unique tests are run to check all printer functions.
4)
Platter Verify Test - Approximate running time is 5 min. (for diskette).
The platter test verifies all sectors on a hard or flexible disk
platter by utilizing write and read commands.
This test can be used
to check any number of platters.
5)
Disk Instruction (CPU/Disk Microcode Test) - Approximate running time
is 3 min. for each disk.
The disk microcode test checks all disk verbs.
Whenever this test
is selected, ensure that disk platters containing no useful information
are used.
6)
WCS/Disk (Disk Hardware Test) - Approximate running time is 40 min.
This test checks the operation of hard and flexible disk drives used
in the system.
One or two drives may be tested, however, only one of each
type may be tested (a dual and triple flexible disk drive or a 2230-1 and
a 2260 may not be tested at the same time, but a combination of 2230 or
2260 and flexible drive may be tested).
Whenever this test is selected,
ensure that disk platters containing no useful information are used.
7-62
7)
Peripheral Tests
~1en
available, the peripheral tests will be selected by the user and
tested after all other tests have been run.
OPERATING INSTRUCTIONS
NOTE:
Do not write protect the diagnostic diskette.
1.
Insert the Diagnostic Diskette into the Shugart Flexible
Disk Drive.
Key LOAD DCF "START".
be set to address 310 or 320.
2.
The drive used must
Key RUN EXECUTE.
An input for a hard copy test result output is requested.
I f a hard copy is desired, an input for the type of printer
is requested.
A "ltl is for a 2201 and a "a" is for either
the 2221, 2221W, 2231 or 2261 high speed printer.
An input for
the address of the primary diskette drive (the drive from which
the diagnostic is to be run) is requested next.
If an address
other than 310 or 320 is keyed, a reenter message is displayed.
3.
The next input request is for a hard disk (2230 or 2260).
If a hard disk is to be tested, input "y".
this disk is then requested.
The address for
If no hard disk is to be
tested, enter "N".
4.
After this preliminary information is entered, SEARCH THE
INDEX PROGRAM is momentarily displayed.
All system programs
are displayed and the tests to be run are requested.
tests are performed in the order displayed.
The
Any or all
tests may be performed by keying the test number when
requested.
As each test is requested, an asterisk is
displayed next to the test name.
~en
all tests desired
have been keyed, key "0" to stop the request.
)
The tests
chosen are then displayed, requesting a "0" for acceptance
or a "1" to change the tests.
7-63
5.
Information for each test is now requested.
For the
memory test~ the memory size and the type of test (system
or burn-in) is requested.
The system test runs 300 times
while the burn-in test runs 65,000 times.
As before, after the
information is keyed, a "0" for acceptance or a "1" to change
the data is requested.
6.
The printer test requests the type of printer to be tested
and then an acceptance input.
7.
The platter verify test requests the address of the platter
to be verified, the type of disk drive the platter is in
and then an acceptance.
Other platters may be verified
at the end of test.
8.
The Disk Instruction (CPU/Disk microcode) test requires no input
information if it is being used with other disk tests.
If it is
the only disk test, the disk type (single, dual or triple)
is requested prior to the test.
9.
The WCS/Disk (disk hardware) test first requests the
number of disk drives to be tested (lor 2).
If two
units are chosen, one may be a hard disk unit (2230 or
2260) and the other a flexible disk unit (single, dual or
triple), but two of the same type may not be tested.
When
the flexible disk units are chosen, all drives in the
unit are tested (i.e., requesting a triple flexible disk
unit will test all three drives in that unit).
or hurn in test is then
10.
requested~
A system
and finally an acceptance.
As each test is performed, a pass/fail message is displayed
and printed (if requested).
When all tests have been
completed, a pass/fail message for all test results is
displayed.
When the message after each test is displayed,
an error message is printed for each portion of the test
that failed.
When the end of the system tests message is
displayed, only a pass/fail for the particular test is
printed, without a description of the particular failure.
7-64
11.
When using the Diagnostic Test, the test platter must
not be write protected.
The reason for this is all
information requested at the beginning of the test is
written on the diskette in order to clear this information
and all variables from memory and test as much memory
as possible during the memory test.
Because the diskette
is not write protected, BE SURE to remove the diskette
when instructed during the disk tests.
12.
In all tests except the memory test, SF Key '15 will
return the user to the beginning of the diagnostic tests.
7-65
THIS PAGE INTENTIONALLY LEFT BLANK
7-66
SECTION 7
NOTES:
)
7-67
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-1
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SECTION 8
MAINTENANCE INFORMATION
FOO
USER TERMINALS, POWER SUPPLIES & CPU'S
8.1
PREVENTIVE MAINTENANCE
The 2200 System must be properly maintained for trouble-free
operation.
This requires periodic cleaning and visual and electrical
checks.
8.1.1
CLEANING
Thorough cleaning should be performed periodically.
Cleaning
intervals are determined by the amount of use and environmental
conditions.
Under normal use and conditions, cleaning should be once
every nine to twelve months.
In areas of excessive air contamination
(smoke, dust, etc.), more frequent cleaning is required.
8.1.1.1 Central Processing Unit
Clean the CPU as follows:
(a)
Remove the top and bottom covers from the CPU.
(b)
Remove the I/O Controllers.
(c)
Use a small soft-bristle brush or an air gun (if available) to
remove dust from the inside of the CPU.
(d)
Remove each printed circuit board from the CPU and clean the
finger connectors using an eraser.
(e)
Clean the finger connectors on each I/O controller in a similar
manner and replace them into the CPU.
8-1
(f)
Use a mild detergent and a soft cloth or sponge to remove dirt
and grime from the outside of the CPU.
Do not use abrasive or
corrosive chemicals.
(g)
Return the top and bottom covers to the CPU and tighten securely.
8.1.1.2
Video Displav/Tape Drive Unit
Clean the Video Display/Tape Drive Unit in the following manner:
(a)
Remove the top cover from the unit.
(b)
Use a small, soft-bristle brush (or air gun) to remove dust and
dirt from inside the unit.
(c)
Use a soft cloth and a mild detergent to clean the face of the
CRT.
(d)
Do not use an abrasive cleanser.
Clean the outside covers of the unit with a soft cloth or sponge
and a mild detergent.
(e)
Return the top cover and tighten securely.
8.l.l.1
Power Suoolv (2200 A, B, C Systems)
Clean the power supply in the following manner:
(a)
Remove the power cord from the AC outlet.
(b)
Remove the top cover.
(c)
Use a small, soft-bristle paintbrush (or air gun) to remove dust and
dirt from inside the power supply.
(d)
Use a soft cloth or sponge and a detergent to clean the blades of
the cooling fan.
8-2
(e)
Clean the outside covers with a soft cloth or sponge and detergent.
(f)
Replace top cover and insert power cord into AC outlet.
8.1.2
LUBRICATION
No lubrication is required in 2200 System preventive maintenance.
8.2
TROUBLESHOOTING
This subsection provides troubleshooting aids.
Not all troubles
can be located with these aids; however, they will identify more common
faults.
Observe the symptoms carefully to isolate the problem by logical
deduction.
8.2.1
VIDEO DISPLAY
SAFETY WARNING
1)
A good practice, when working inside any electronic chassis, is to
use only one hand.
This will avoid the possibility of carelessly
putting one hand on chassis or ground and the other on an electrical
connection, causing severe electrical shock.
2)
Extreme care should be used in handling the Cathode Ray Tube; rough
handling may cause implosion, due to atmospheric pressure.
Do not
nick or scratch the CRT or subject it to any undue pressure.
3)
When video display removals/replacements are necessary, follow
instructions in paragraph 8.5.2.
4)
Avoid prolonged exposure at close range to unshielded areas of the
cathode ray tube.
)
Possible danger of personal injury from unnecessary
exposure to X-ray radiation may result.
8-3
VIDEO DISPLAY TROUBLESHOOTING FLOW CHART
(page 8-7)
C (page 8-7)
8-4
TYPICAL DISPLAY
FIGURE 8-1
NO PICTURE (VIOEO)
RASTER OK
FIGURE 8-4
~YMPTOMS
FI GURE 8-2.
NO CONTR ~ST WEAK
OR WASHEO OUT PICTURE
FIGURE 8-5
FIGURE 8-3
RASTER KEYSTONEO
FI GURE 8-6
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=:EEEEEEE:EEEUEEEEEEEEEEEEEEEEE
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RASTER BLOOM
(LOW HIGH VOLTAGE)
FIGURE 8-7
PULLING OR TEARI%
FIGURE 8-8
RASTER KEYSTONEO
FIGURE 8-9
I
t
REOUCEO HORIZONTAL
SIZE OR A VERTICAL
LINE IN c,n rE'JTER
FIGURE 8-10
NO RASTER
FIGURE 8-11
TOP EXPANOEO BOTTOM
COMPRESSED, VERT
HOLO CONTROL ON ENO
OR WILL NOT HOLO
FIGURE 8-12
~~~~H~HiHi~~~~i~~~~~~Hi~~U~
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)
TOP COMPRESSED BOTTOM
EXPANOEO,COLLECTOR
VOLTS OC NORMAL ON
OUTPUT ANO ORIVER
STAGE
NO VERTICAL SWEEP
8-5
REDUCED HEIGHT
TYPICAL DISPLAY SYMPTOMS
FIGURE 8-13
FIGURE 8-14
LOSS OF HORIZONTAL
SYNC
lOSS OF VERTICAL SYNC
FIGURE 8-15
FIGURE 8-16
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(EEEEEEEEEEEEEEEEEEEEEEEEEEEEEEE
lOSS OF BOTH VERT/CAL
AND HORIZONTAL SYNC
RIGHT SlOE COMPRESSEO
LEFT SIDE EXPANDED
FIGURE 8-17
FIGURE 8-18
REOUCED SIZE BOTH
HOAIZDNTAll Y AND
VERTICAll Y
NO RASTER
,,-
FIGURE 8-19
FIGURE 8-20
--~~rd'"
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WEAVE
HUM
8-6
VIDEO DISPLAY TROUBLESHOOTING FLOW CHART
(Continued)
FROM
PAGE 8-4
8-4
A
FRrn PAGE 8-4
C
8-7
8.2.2
THE TAPE DRIVE UNIT
A digital tape is a very high quality tape.
Just as important as
the tape's recording qualities, is the atmosphere in which it is used,
the drive mechanism it is used in, and how tape and tape drive mechanism
is cared for day to day.
Even with all these subjects at perfection,
a digital tape will fail eventually.
Oxide coated materials such as magnetic tape cassettes are extremely
durable but require certain environmental control for long life and proper
operation.
All storage material manufactured in the United States conforms to
specifications set forth by the American National Standards Inst.
(ANSI).
Not only do U.S. manufacturers meet ANSI specifications, but in most
instances surpass
them.
Oxide wear is probably the single most contributing factor to data
destruction.
It is caused by excessive tape to head or disk to head
contact, dirt, humidity, and storage care.
Tape to head contact is a mechanical function of the tape
drive.
Drives should be checked periodically for excessive oxide wear
and defects corrected immediately.
Humidity and temperature are important factors to consider not
only in operation but also during storage.
Tapes are tested by manufac-
turers at four hour temperature and humidity cycles of 50° to 113°F and
20% to 80% relative humidity continuously for fifteen days.
These tests
exercise the material for more than 1.5 million passes during which time
data must be written and read without error.
For tape, low humidity
(between 5% and 10% R.H.) normally does not cause tape or data degradation during operation.
During storage, however,
low humidity can cause
the oxide binders to dry out, causing oxide shed, and can also cause
cinching problems when the tape is used.
Static discharges generally do affect recorded data.
The level
of the recorded data is not sufficient and will be destroyed by a static
discharge.
8-8
The following recommendations are made:
1.
If tapes are subjected to environmental extremities during storage
or transportation, they should be normalized at the operating environment for at least 24 hours.
2.
Stored tapes should be loaded and rewound at least once a month
to prevent tape distortion caused by tension.
3.
Head lubricants should never be used.
They cause oxide degradation.
4.
Only tapes made to ANSI specifications should be used to insure
long life and quality data reproduction.
Tapes manufactured in
foreign countries sometimes do not meet these requirements and
result in data being lost after repeated use.
Below are listed several ways to lengthen the life of digital tapes.
1.
The -..netic. head of the tape dri_ ehould be cleaned at I_at
!\rea it t.he tape drive Is uaed oal,.
ODe. . .
week by the c:usto-r.
oace ..
cia,.
bead.
A. dWlt buildup can &Crape tape and head .urrace. when the
tape
Ute ran ill tbe "'••1' CODsole will dr_ dust oata the
~ve-nt
oc.cu'u.
~ve
the cae.ette door (two th..-b scr_.)
to rNch the aar;netLc he&d .urface.
tuiDa
care DOt to daaage thb
IlUrhea, latly wipe the tape bead uaLoa alcohol cleaalDI pada that
. ., be abtallled locally at audio aupply fint8 or . .,. be ordered
fro. W_I LUs (\ILl '660-0130).
~e
people reco_end usLng ..
bud de.iDa upe because 1t Is rut and IIblple; however. thea.
cle_tns tapes an abr._L". and viII eventually veal' dDvn the TD-Z4
head.
2.
The ataoaphue in wich .. digital upe u
perfora&Dce.
used 1D will .ffect lu
The tape 1. recorded •• petie.Uy. and of course,
ean be destroyed _petlc:ally.
The user tenUnal emit. _gnetic
fielda tbat can eventually weaken or change data
OQ
cassettea i f
tbey are left oa. top of or close proximity to tbe user tendnlll
when aot in I»e.
The amplitude of the eigual frolll the tape decreaaea
rith age because of auch environ_ntal condition•• .md vill eveutually degrade digital information atored on tape to the point
vhere .m error «eure during LOAD.
to un1.lll.1ze such problelU it u
recolllDended to 1.1rIDediately relllOVlt
tbe cassette £'rOll the WIer tendoal after use. return the tape to
Ita ease. and IStore it in II desk or casBette file sOIIIevhere a fev
feat froa the U5er tenninal or any other equip_ot suspected of
)
lenerating • _gaetie field.
8-9
If e.pes are \Sed co the extent tfult they need co be re-recorded
every IIlOnth then they should be replaced.
R.e-recording and exceaaive
U8e tenda to defol' and stretch the tape.
1.
Iter_cording the tapea .:tnthly is a vi_e Idea, but clrMUnq the
tape _gnetlcal.:y prior
rerecording also I'telpll.
to
To do thi..-.
amply LOAD the progr_ 1.tl.to the .,atell, erase t.he tape vttb •
bulk cape eraser ...d then rerecord t.he prograa.
4.
It. 1& further reeo_nded that cwo identical tape l1brari_ (work
library. reference library) be lILIint.ained t.o ensure that a tape
c1aaaged by • tApe drive or heavy uae
Clm
be rerecorded
OIl
a new
replacement tape drive.
5.
If ,our tape. have 0111,
on_
block of dat.a on th_. record the
block aeveral times em the same tape.
6.
The Wang tape drive 18 designed for a specific IIleC:hanical "dra.".
The tape is pulled past the read/record head by a eapst.an and
pinch roller at a relatively st.able speed; however, the spool
of tape which it 18 PJ.1l1ng could snap or jerk as it's being
pulled. or a worn bearing may cause a varying pulling t.orque.
Theae it.eM wuld C3U8e jitter or speed changes while reading or
recording.
To overcome jitter, a drag torque is applied
con.tantly to the right hand spool during a tape read or writ.e •
.nae 8lDOunt of force CDlIIlpensates for bearing fluct.uations and
prevents the reverse spool (right) from a free-wheeling.
The
friction of the cassett.e itself (which is deterllt1ned by tape
caasette length. thickness, and packaging) adds to mechanical
drag.
Using the incorrect length or thickness of t.ape viII change the
drag torque.
Cassettes &old by Wang Lab_ are within ·the correc.t.
specifications.
1.
A tape drive will veal' in various ways.
If the _chaohllll which
atabilizes the Illilgnet.ic head wears. head akev lILly change and an
aUlplitude drop viII occ.ur during a tape read.
If tapes are re-
recorded, even though skew position has changed, the nevly
recorded data will becOlDe aa high in quality 88 the original tape.
(The head skew problellll would nill exist, and rerecording would
be only a telllporary corrective measure in this C8lf1e.)
8.
If . . error doea occur, in most. c.a_. a progra. vhicb might. ot.herviae be Don-retrievable _y possibl, be rerecorded . . follows:
a)
Vlt.h casset.te door relIoved, apply .tight. fingertip pressure
to the right. spool of the caasett.e drive as the upe !.Dada.
11th _y help st.abilize any jit.t.er.
b)
Rerecord che saved progr'"
OIl: ..
8-10
sub.tit.uce tape drive unic.
TAPE DRIVE TROUBLESHOOTING FLOW CHART
)
BEGIN
Check the ftlt Protftl
~t~~~PI~~:: ~ ~:'Id 1'.'"------.
5.ttcll is
o~nl
8-11
8.2.3
THE CENTRAL PROCESSING UNIT
Troubleshooting a CPU should be a relatively simple procedure from
a systems standpoint.
1)
Perform the following steps:
Remove all peripheral controllers from CPU and check address switch
settings (replace display, keyboard, and cassette controllers).
2)
Check RAM size selection switches per Section 2 of this manual and
check CPU voltages per paragraph 8.3.2.
3)
If system diagnostics cannot be rtlll (system IIdead" or "locked up"),
replace boards presently in CPU until the problem disappears.
4)
Run all diagnostics appropriate for that CPU and all associated
software options.
5)
If a "bad" run of any CPU-only diagnostic occurs, and assuming the
user console to be functioning properly, substitute known good
processor circuit boards until the diagnostic error no longer occurs.
6)
If error still occurs, the system problem may be associated with
I/O controllers.
Replace I/O controllers into CPU chassis, recheck
voltages, and run appropriate peripheral diagnostics (refer to
Sec tion 7).
7)
Ensure that peripheral connections to controllers are secure.
8)
Assuming peripherals themselves are functioning properly, substitute
a known good peripheral controller for a suspected bad controller.
(Set address switch on new board.)
9)
If the system problem appears to be in a peripheral, troubleshoot
that peripheral according to Service Bulletin procedures.
Beginning on page 8-13, block diagrams for central processor boards
(2200 A, B, C. S*, 1*) are presented to aid in comprehension of CPU hardware.
*NOTE
Block diagrams for 2200S/T CPU's will be forthcoming
in subsequent updates to this manual.
8-12
6307 CIRCUIT BOARD - BLOCK DIAGRAM
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8-13
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8-14
6309 CIRCUIT BOARD - BLOCK DIAGRAM
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6310 CIRCUIT BOARD - BLOCK DIAGRAM
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6361 CIRCUIT BOARD - BLOCK DIAGRAM
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8-20
8.3
ADJUSTMENTS
Adjustments, particularly electrical adjustments, should be performed
only when the parameter measured proves to be out of tolerance.
Do
not make either electrical or mechanical adjustments indescriminately.
Be certain that measurement devices are properly calibrated and are
utilized for optimum results.
8.3.1
RECOMMENDED TEST EQUIPMENT/TOOL LIST
a)
Digital Voltmeter, with an accuracy of at least +.1% of full
scale and 1 mv. resolution factor.
Multimeter/VTVM accuracy
and resolution factors are unacceptable for certain critical
measurements.
Acceptable Type/Equivalent:
b)
FLUKE #8000A
Multimeter, 20,000 'J/v (min.): 2% or ~reater full scalp accuracv:
for less critical measurements.
Acceptable Type/Equivalent:
c)
Oscilloscope, with two x 1 probes and two x 10 probes.
Acceptable Type/Equivalent:
d)
TEKTRONIX #465
Electronic Counter
Acceptable Type/Equivalent:
e)
TRIPLETT VOM #630NA
HP #5381A
Test Cassette
Acceptable Type/Equivalent:
INFORMATION TERMINALS
X-1000-800FCI
f)
Allen Wrench Set
g)
Plastic Alignment Screwdriver for video display adjustments.
11)
Torque Driver (Utica TS-IOO)
)
8-21
Dr~ver
i)
Hex Nut
j)
Thickness Gauge (J.C. Chestman 5811/20)
k)
Gap Gauge (Wang D-22-ll8)
1)
Solenoid Gap Gauge (Wang D-22-035)
m)
Penetration Gauge (Wang D-22-056)
n)
Heavy Duty Screwdriver with heavily insulated handle and
set.
shaft, for discharge of video display anode voltage.
0)
Insulated Heavy-Gauge Ground Wire with insulated Aligator clips
(for use with item (n), above.
p)
Small Screwdriver with insulated shaft, used mostly for
voltage adjustments.
8.3.2
CPU - VOLTAGE ADJUST PROCEDURE
a)
b)
Remove top cover of 2200 PS (A, Bar C system).
Remove top cover of CPU and, with the exception of the 2200 S,T
L567 pc, remove all plug-in CPU circuit boards.
c)
Place L567 circuit board on an extender pcb.
d)
Turn Supply/CPU power ON.
e)
Check voltages for specified value(s), as listed in Table 8-1.
Adjust L567 pc trimpots where indicated in figures 8-28A and
8-28B to obtain correct voltage levels only where necessary.
Never allow the -15VR power supply to exceed -17 vdc, otherwise permanent damage to the CPU will result.
8-22
f)
With an oscilloscope and a Xl probe, measure the ripple at
the points indicated in Table 8-1.
exceed the limits specified.
AC ripple should not
If any voltage or ripple
measurement is out of specification, troubleshoot the CPU
power supply.
Connect a Digital voltmeter between the point indicated and
±
avo
If necessary, adjust the voltage to coincide within limits the specified
limits.
TABLE 8-1
LOCATION
L567 Pin 11
L567 Pin 2
1
L567 Pin 12
1
L567 Pin 15
1
L567 Pin 52
L567 Pin 6
2
-12
-l~
LIMITS
VOLTAGE
+12
FIGU~E
ADJ
RIPPLE
+5VRM
+4.90 vdc to +5.10 vdc
R17
15 mvp-p
+5VRL
+4.80 vdc to +5.20 vdc
R2
15 mvp-p
+8VR
+8.50 vdc to +8.80 vdc
R13
20 mvp-p
+12VR
+11.80 vdc to +12.60 vdc
R30
15 mvp-p
-12VR
-11. 80 vdc to -12.60 vdc
R34
35 mvp-p
-15VR
-14.80 vdc to -15.30 vdc
R40
25 mvp-p
+8
+5'1'\
+5\fL
-12
8-29A
FI r;URE 8-29B
8-23
f)
Note that when increasing RAM capacity by conversion, adding
options
~hich
require addition of ROM IC's, or adding extra
I/O capabilities to the CPU, all LOAD-CONDITION voltages should
be rechecked and, if necessary, readjusted on the L567 pc.
g)
A similar procedure should be followed for any peripheral unit
with a self-contained power supply; some of these procedures
are documented in subsequent text on "Electrical Adjustments I I .
h)
Replace unit covers when these procedures have been successfully
completed.
TABLE 8-2
POWER SUPPLY/CPU
2200 PS
C0NN.
PIN NO.
MOT~OARD
COlOR
GAUll
CONNECTIONS
TE~",""'-S
2200 AlBIc
.... leNAt
ItJTHER.lIOARll
NAMI
18
"'0
+SVLR
II
RIO
"WI R
IR
ALD
"'\\ R
18
R>D
+')V\ It
I'
ORN
+',VR"1
18
ORN
,,',\'I'M
<n
11,18
IH
LIX
18
WilT/III K
II
18
(,I{r-./)U
I'."
18
".
"
>'
IH
\,'Hl
WilT/GIL"
9,«(,311)
....IIT/nL
10,(6]11)
WllT'ORN
110,(631])
r-~IIllT
+ I ~VR
FRONT VIEW OF 2200PS CPU CONNECTOR
(For 2200A, B, C)
8-24
8.3.3
VIDEO DISPLAY UNIT
CAUTION:
No work should be attempted on an exposed Video
Display Chassis by anyone not familiar with
servicing procedures and precautions. See
Video Display Safety Warning in paragraph 8.2.1.
Perform the following adjustments on the Video Display Chassis;
refer to Figures 8-30, 3-31, and 8--59.
(a)
Remove the Video Display Chassis from the Video Display/Tape
Drive Unit.
(b)
Connect a voltmeter to pin 22 of the video PCB and adjust Regulator,
R74*, for a meter reading of +73.0 vdc
~1.0
vdc.
For systems using
the 9 inch Video Display Chassis, connect the voltmeter to pin 18
and adjust R103 for +12.0 VDC +0.5 VDC.
*CAUTION:
Do not "run" the regulator control through its
range or damage to the display unit may result.
(c)
Remove the video input cable from the display chassis.
a jumper from chassis ground to the
~nter
Connect
conductor of the input
connector.
(d)
Connect a XIO oscilloscope probe to Q3 collector and adjust Video
Bias, R10 (R14 on 9 inch model), for +30 vdc.
while adjusting RIO, temporarily connect a 0.05
If Q3 oscillates
~f
to 0.68
capacitor between Q2 base and ground.
(e)
Remove the shorting jumper and reconnect the video cable.
8-25
~f
25V
Rl0J
REGULATOR
ADJUST
U'
L1
09
T1
010
L2
HORIZ
LINEARITY
Q7 BLANKING
AMP
BOARD
I
FIGURE
8-30
I
06 SYNC - - - : , - - ; ;
AMP
05
SYNC
SEP
01
1ST VlIlEO
AMP
02
03
2ND VIOED
AMP
3RU
VIDEO
BIAS
ADJUST
VIDEO
AMP
015
REF
06
012
VERT
07
AFC
PHASE
06
08
T1
HORIZ
HORIZ
HORIZ
II
HORIZ FREQ.
SET
TO
CRT
Fil PIN 8
RID
VIDEO
BIAS
8-26
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
JI
1
1
1
1
1
1
1
1
1
1
1
1
JI
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
(f)
Enter the following program in the 2200:
1 PRINT "HO";
GO
)
ro
1
RUN
EXECUTE
The display should fill with alternate HO.
(g)
Set Horizontal Hold and Vertical Hold controls to midrange (see
Figures 8-59 and 8-71).
(h)
Adjust Horizontal Freq. Adjust, Ll, for horizontal sync (see
Figures 8-30 and 8-31).
(i)
Adjust Vertical Size, R65 (R5l on the SM-227 diaplay).
(See
Figures 8-30 and 8-31), for a vertical height of 8.5 inches
(21.6 cm) or 4.5 inches (11.4 cm) on the SM-227.
(j)
Adjust Width, L4, for 10 inches (25.4 cm) horizontal deflection
(see Figures 8-30 and 8-31) or 6.5 inches (16.5 cm) on the SM-227.
(k)
Adjust Vertical Linearity, R52 (R59 on the XM-227 display), for
characters of equal height.
(1)
Adjust the centering tabs (Figure 8-60) on the CRT yoke for a
centered display.
(m)
Be sure the tabs are at least 90° from each other.
Repeat steps (h) through (1) until proper horizontal deflection,
vertical deflection, and centering raster are achieved.
(n)
Adjust Focus, R17, for best overall focus (Figure 31).
This
adjustment is not on the XM-227 display.
8.3.4
TAPE DRIVE UNIT
Perform the following adjustments on the tape drive power supply
1
chassis:
J
(a)
Remove the top cover from the Video Display/Tape Drive Unit.
8-29
(b)
Place the L559 PCB on an extender.
(c)
Refer to Table 8-3.
Connect a voltmeter between the point indicated
and +OV and measure the voltage.
TABLE 8-3
CASSETTE DRIVE CHASSIS POWER SUPPLY TEST POINTS
LOCATION
VOLTAGE
LIMITS
ADJUST
1559 Pin B.l
+5VR
+4.80 vdc to +5.20 vdc
1559 Pin A.l
+9V
+8.5 vdc to +11.0 vdc
L559 Pin 0.1
-9V
-8.8 vdc to -11.5 vdc
L559 Pin H.2
CP+
+25 vdc to +37 vdc
1559 Pin K.2
CP-
-25 vdc to -37 vdc
(d)
RIPPLE
6324RlO
35 mvp-p
-
0.6 v p-p
0.8 v p-p
1 v p-p
1 v p-p
With an oscilloscope and a Xl probe, measure the AC ripple at
the points indicated in Table 8-3.
AC ripple should not exceed
the limits specified.
(e)
If any voltage or ripple measurement is out of specification,
troubleshoot the tape drive power supply.
Forward Speed Check/Adjustment
(a)
(b)
Connect oscilloscope or frequency counter to L7 pin 6 (6175 pc).
Insert an IT 800 FCI Standard Test Tape into the tape drive.
Key LOAD, EXECUTE.
(c)
The frequency indicated should be 3000 + 50 Hz frequency or 333 vs
+ 5 vs (period of one cycle).
(d)
If the frequency is not within specifications, change the capstan
drive belt as described in paragraph 8.5.3.
8-30
-
(e)
If the frequency is not within specifications after the belt is
changed, the capstan motor pulley must be changed.
different pulleys available.
There are three
The pulleys for 60 Hz operation are
color coded, gold the slowest, silver intermediate and red the
fastest.
silver,
For 50 Jjz operation, the respective pulleys are large
violet and black.
Head Skew Adjustment
(a)
Using XlO probes, connect channell of an oscilloscope to L7 pin 6
and channel 2 to L8 pin 6 on the 6175 PC board.
Set the oscilloscope
control as follows:
Vertical Sense; Display Mode:
Sweep Time:
(b)
.1V/div.; chopped
50
.
~sec/div.
Trigger Mode:
AC; Normal
Trigger Source:
Channel 1
Insert an IT 800 FCI Standard Test Tape into the tape drive.
Key
LOAD, EXECUTE.
(c)
Two sine waves should be observed.
Use the vertical position controls
to position the sine waves with equal swings above and below the zero
reference line.
(d)
Refer to Figure 8-35.
The channel 2 trace should not deviate from the
channell trace by IIDre than 20
deviation is greater than 20
~sec
~sec,
in either direction.
I
r til('
perform steps (e) throllflh (II).
FIGURE 8-35
)
R- 11
(e)
Refer to Figure 8-36.
Using a sharp instrument, scrape the glyptol
from the adjusting screws.
NOTE:
When adJusting the skew, always loosen one screw
first and then tighten the opposite one.
FIGURE 8-36
o
~-----Skew
(f)
Adjustment Screws
If channel 2 trace lags channel 1 (to the right of channell) loosen
the left screw approximately one-half turn.
CAUTION:
Never allow the torque on the adjustment screw
to exceed 10 inch-ounces (.7 newton-em.) or
damage to the tape head will result.
(g)
While observing the two traces on the oscilloscope, tighten the
opposite screw until the skew specification can be met.
If necessary,
alternately loosen and tighten the two screws until the skew is correct.
Finally, tighten both screws to 10 inch-ounces.
(h)
If channel 2 trace leads channell (to the left of channell), start
the adjustment by loosening the right screw.
Then proceed as
described in step (g).
(i)
Reapply glyptol to the screws when the adjustment is complete.
(j)
The amplitude of both signals should be at least 6 volts p_p.
If not, check the head and/or the 6175 PC board.
8-32
File Protect Switch Adjustment
(a)
Insert an unprotected cassette (with tab) into the tape drive.
(b)
Loosen the two screws holding the switch in place.
(c)
Move the switch towards the cassette until it actuates, then move
it an additional .050 inch (.127 em) to .070 inch (.178 cm).
(d)
(e)
Tighten the screws.
Insert a protected cassette (tab removed) into the tape drive.
The switch should not actuate.
If it does, reposition the switch
and repeat steps (a) through (e).
)
8-33
8.4
8.4.1
I
101 ~
)]01
lor"
:101
:101
::01
lol~
;1,,1 10!1
[01 ~
101o~loJ'
1,,1'
101"
=
I<t
2200 CPU; MODELS A, B,
[o!"
101"
~
CHASSIS LAYOUT(S) & SUPPLEMENTARY DATA
1,,1~
a 28K.
32K G 101"
;10! l'J 20K. 24K G lo;~
;01 l'J 12K. 16K G Jol'<
)Jol 8 4K. 8K Bioi'
;101 loi~
;101 101"
!~l ~
;101 lor'
;)o! 101"
;1 o~ "I ~ I ~
10)'
::01
IOI~
;101
to! ~
:10) 10 I~
if a ]
!*
10:-
;101
Ie ~
-101 10'
lol~
101"
;!ol
f!!'
:101 101'<
c; 6 I/O
--
;01.
'6l0J/6101IfllOJ-1I6101-1
-- 6308
::01.. -- TEST
;Io!_
ROM/SUPERPATCH*
, --- ROM/SUPERPATCH*
~I.
ioj.
;0 1•
-----
iiol~
-- I/O
;\0]
101"
jjio!~
--
I/O
101-
ilal
lo!-
;! ol~
101:
;101
101"
i!o!~
I/O
101"
ilol
101"
;1 ol~
----
lol~
jlol
!ol-
;]01:
1
~
."
n
II
I
07
07-1
07-1
07-1
ROM/SUPERPATCH*
:101. - - ROM/SlIPnPATCU*
;101. - - ROM/SUPERPATCH*
6309
6310
8l:===:J;[l2J'o!, - -
I/O
8l:===:J;[l2Jlol' - -
I/O
TABLE 8-5
RAM SLOT'
RAM 1 P.'.M 2 RAM 3 RAM 4
K
K
2K
.6K
OK
4K
oK
2K
07
07-1
07-1
07-1
07-1
7-1
07-1
07-1
-
07
07-1
07-1
07-1
07-1
07-1
07
07-1
07-1
07-1
I/O
I/O
-
--
07
07-1
07 = 4K 6307/6707 RAM
07-1 • 8K 6307-1/6707-1 RAM
* •
6325/6527/(.~47
rill:==:::J;:r;:IQI~ - - 1/0
8-34
07
07-1
FIGURE 8-37
;!ol: - - 6311
;\01,
-
* • 6325/6527 /(.~47
1ill:=:;::=:J,[l2Jior~ - - I/O
l'J::===:J;~\01' - -
-
I/O
:101. - - ROM/SUPERPATCH*
,'01, - -
07
07 1
07-1
07 1
07-1
07-1
07 = 4K 6307/6707 RA~
07-1 • 8K 6307-1/6707-1 RAB
I/O
;'0'- -- 6308
;'0" --
07
07 1
07 1
07-1
07-1
07-1
07-1
07-1
I/O
;10[- - - SPARE
.lo/. - - 6361
;'oJ. - - 6307-1/6707-1
;'01· - - 6307-1/6707-1
tW· - - 6307-1/6707-1
"0" -_
K
2K
6K
OK
4K
.oK
2K
ROM/SUPERPATCH*
6309
6310
6311
101:
! I
I
50"
lol~
lor-
K
6307-1/6707-1
ilOl
jlol
RAM SLOTt!
IWI 1.. R \M 2 RAM ) RA.."'f II
;101;:01.
t! .. 1 101-
lo!~
101"
~
TABLE 8-4
-- SPARE
-- 6361
-- 6307-1/6707-1
;10\. -- 6307-1/6707-1
::01_
;!ol_
, 0:=
i'''!:
; ~ "i 10
SLOTS
FIGURE 8-38
2200 A/B/C, 6 I/O SLOT CPU MOTHERBOARD - WIRING SIDE
- - - - - - + 5 VRM
_ - - - + 5 VRM
-------15 VR
i----- -12
VR
.....- - - +12 VR
i-----+8
VR
0;----+0 V
+0 V
i----+O
V
-----':0 V
+0 V
-----+0 V
r - - - - + 5 VLR
i - - - - + 5 VLR
r-----+5 VLR
+5 VLR
+8 VU
-15 VU
+15 VU
1----_
r-----
115 VAC
115 VAC
.....---AC NEUT
i---;-
FIGURE 8-39
)
8-35
AC NEUT
CHAS GND
8.4.2
2200 CPU; MODELS A, B, C; 11 I/O SLOTS (2219)
:101
lo!~
:101
lol~
ilol~
.101
lol~
:101 lo!;
;!"l~
:101 Er;23K,
.12KIDJ
;)01 ~20X. 24r.:E
;!OI ~12K. 161(ffiJ
;101 0I
4~. 8X
;101 lo}'
ilOl rol..
lo!~
i§l
)01"
lo!~
:101·
lol~
jlol..
;g I.I~
:lol~
;101
;10]"
lol~
j!oI1o!~
,101
;101
iJ.,I.
jlol:
! I
i lo !
II
;101
I
:101
101..
;lol~
101$
iiol~
'01·
;Iolt
jlOl
6378
pt
! I
eloJ:::I"==::J;l;)loi
I!
i!Ol
ROM/SUPERPATCH*
ROH/SUPERPATCH*
-
ROH/SUPERPATCH*
-
6309
6310
6311
I/O
FIGURE 8-40
I/O
-
I/O
-
I/O
I/O
I/O
lor..
dol: -
I/O
'01..
:101: -
I/O
6521 PC
I
l3Cioil==::=lli)!!*-
:rol
'01"
.Iolt
jlol
IOJ..
;(01=
-
I/O
I/O
I/o
RAM SLOTH
RAIl 1 RAM 2 RAM 3 RAM 4
4K
8K
1 2K
1 6K
2 OK
2I+K
2:IlK
3 2K
07
07-1
07-1
07-1
07-1
07-1
07-1
07-1
07
07-1
07-1
07-1
07 1
07-1
-- -- - -
07
07-1
07-1
07-1
-
-
07
07-1
07 = 4K 6307/6707 RAM
07-1 = 8K 6307-1/6707-1 RAM
• - 6325/6527/&>47
8-36
I
6308
EF==:-t' -
EjlI'I'===::;j2J;I'1
----1 6521 pCr----------;
101:
6361
6307-1/6707-1
6307-1/6707-1
6307-1/6707-1
TEST
jlol\ .101: -
101:
SPARE
1'1.:J7/UOlltohl1-Ilr.1Ol_1
;/e/:
lol!
I
-
;]01:
6322 PC
;101
-
--
;Io:~
lo!~
jlol lo!"
:!ollo!!
ilol 101"
tlol'o!.
;/01 /01"
--
iJo!. ;]01_ -
;!el lo!!
:101 101"
.::101 lol~
:101 [01"
ijOi
;!o(,
10['
--
TABLE 8-6
2200 AlBic, 11 rio SLOT CPU (2219) - 6322 MOTHERBOARD, WIRING SIDE
+5 VRM
+5 VRM
-15 VR
-12 VR
+12 VR
+8 VR
~O
v
__
v
~~__--=:----_:':.O v
"!=-~:r
--_:':.O
: . . . _ . . . . . : : - - - - - - +0
v
_ ___.:='------:':.O v
;:..__=v
~
:':.0
:.--i=------ +5
FIGURE 8-41
8-37
VLR
8.4.3
6222 VERSION; 2219 CHASSIS
!OJ..
;:01
!ol~
[01"
;.:>1
I,':
101 ~
101:
ill 23K.
"IB 20K.
_~!ol"
....I"j ..
1
10('
t'!
=
32KEl I,,!·
24K 13 lol!
'01:2] 12K, 16KEl loj"
:>1 §
4K, BK Ell-,:
- :>\
,
;>1 \0;-
II:>]
H~
;:>1 '""
:: ~1 1-
101"
:,,[ 101"
)01'<
:,,1
~:
101"
~
;10\ !"I~
;!:>I 1"11
"! j'I,,':.
.,1 I,,·
ioj"
101-"
: .,} 1,,1"
fol"
:',,1
101:
i
e ;
I,;"
~ ~! 'o,!
}OI"
:n]
101"
)"j loi~
&1..
;:01 10:"
':';01 101"
!"j ..
;i:>1
101"
jlol
bU'"
;!ol
I
1I
1I
-- SPARE
-- 6361
-- 6307-1/6707-1
-- 6307-1/6707-1
,101.. -- 6307-1/6707-1
;!o!,I
jlol-
;10('
;101_
;101'
--
.10::',,: .. - -
ROM/SUPERPATCH*
-- ROM/SUPERPATCU*
-- ROM/SUPERPATCH*
-- ROM/SUPERPATCH*
-- 6309
6310
-;:!ol: -- 6311
:1"1"
~:~:.
j:c.j:
;1" ;~
--
I/O
--
I/O
::::
::::: -- I/O
10["
ilo!~
101;
;!"I'
11m
i 10l
EI"
jlol
101"
:Iolt
lOr:
:101
'01'
;1,,):
Jol"
;101
'0/"
i 1ol:
loj..
:Iol~
loj ..
#101'
I
,,,j ..
=1...1
! I
'01·
;!Ol
J iI
101"
;;101
101"
ilalt
101:
jlol
loj"
;101_
----
FIGURE 8-42
I/O
I/O
I/O
I/O
I/O
-
I/O
I/O
I/O
RAM SLOT'
RAIl 1 P.'<lI 2 RAM 3 RAM 4
4K
Q7
8K
U7-1
1 2K 07-1
1 6K 07-1
2 OK 07-1
2 4K 0-1
2 K 07-1
32K 07-1
-- --- ---
07
07-1
07-1
07-1
07-1
07-1
07
07-1
07-1
07-1
=
-
-
0
07-1
07
4K 6307/6707 RAM
07·1 • 8K 6307-1/6707-1 RAM
*•
6325/6527/f.~47
8-38
I
il,l..
I
!
61ll7/U01IUQ1_1/6101·1
6308
TABLE 8-7
2200 A/B/C, 11 I/O SLOT CPU (2219) - 6222 MOTHERBOARD, WIRING SIDE
+5 VRM
+5 VRM
15 VR
-12 VR
+12 VR
+8 VR
___----.<:.0 V
_...!=.------.<:.o
+0
~~=3f=====+0
K;r--...
;;------.<:.O
V
.<:.0 V
• .---..r-- -----+5
,.....-......------+5
r-'"'lIir-------+5
V
V
V
VLR
VLR
VLR
i-.---------+
5 VLR
W-------_
15 VU
+8 VU
+15 VU
115 VAC
115 VAC
nC NEUT
IC NEUT
ellA5 GND
FIGURE 8-43
)
8-39
8.4.4
2200 CPU; MODELS S, T
-+--
c:===::J
:::J-~'
I
c:===::J
FIGURE 8-44
-1------
:=-+--}~
2200S/T; 3 SLOT I/O CHASSIS
TABLE 8-8
~~~-l---­
~~~->--
c:===::::J c:=:::=J
.",
c:===J c:===J c:===J --+--- 6125/6135
~
ES§SES
c:===J
_I- c:=:::=J
c:===J
c:===J
l-
I
on
r
21
671~
€on,> A
~60
PC
(0
T
(S vith <WT 24)
I
67011C
,01.
I..OI.Dl\1C
TlIbl. 8-9 .hoVe the "... 1oWl UM cOllUaurat1C1u for th" 6707 and
6717 HOS "".ary Boarda
wbua EOi 4195 hila
-+-- ~rol
c:=:::=J c:=:::=J
~Om~~
siT with
OPT 2l
SEECB.UT
I---+--
GJ [;]
vith
on "
=&~61081
c:===J ~ - ~
c:===::::J c====J _ I - - - c:===J c:===J - I - c:=:::=J c:=:::=J - I - -
I
sIT
SiT vith
~lt.
6117-1 at.
~
n..
6717
Nn
oaly b. uad 1n 2200 cpu.
The 6707, 6707-1, 6717 and
18pl_tad
8R. 81: lind 16k HOS . . . . ry Boarde rupect1vely
8
" 88
6301-1
U01-1
0'
0'
6107-1
or
6707-1
or
6717-1
6117-1
6707-1
"17-1
6117
... 117-1
6307-1
n01
0'
6101
0'
c:===::J
c:===::J
c===.J
c===.J
c:===::J
c:=:::=J -+-c:===::J
c:::==:J
c:=:::=J
c:=:::=J
c:===::::J
c:=:::=J
c:::==:J
c:::==:J
c:::==:J
c:::==:J
c:=:::=:::J
c:=:::=:::J
c:=:::=J
c:=:::=:::J
c:=:::=:::J
c:=:::=J
c:=:::=J
c:=:::=:::J
c:=:::=:::J
c:=:::=:::J
c:=:::=:::J
c:=:::=:::J
c:=:::=:::J
c:=:::=:::J
c:=:::=J
c:=:::=J
c:=:::=J
c:=:::=:::J
c:===::J
c:=:::=J
c:=:::=J
c:===::J
c:=:::=J
.,'"
,"',
or
6]07-1
6707
6707-1
0'
TABLE 8-9
OlD \lH£'f USINC
6U)-1 IK SL01H
TABLE 8-10
r-=~/T v;:n6109
I
~-20.
21
-6125/6135A~6735'
",m
:":':-,/-,-"'-,,----,-,/-,-.-,,-.-'---,--~
OP-20,22
OP-20,23
(S with OP-20.24)
€onS)
6102 A - - - - . . . . 6108 I
SEECllAIT
ror.LOADIIIC;
2200S/T with OP-20
(6 I/O SLOTS)
c:=:=::J c:=:::=J -
'«J~i~~~
!'_1--_-'--_-'
0
I
CJ GJ
8
FIGURE 8-45
(\.0
L-
6711
l..--._-11...-_.J.-_-J..._--1_
c===J c:=:=::J c=:::::::J
I
or
6711
°08
_
8-40
FIGURE 8-46
.J
FIGURE 8-47
FI
_
ooF
I
I
I
I
I
I
I
I
I
'-+--
I
I
I
I
I
1
I
1
I
I
jk.l
I
~I
I
I
I
1
-l-1
I
I
I
I
t·
t
I
",,
,
I
-I
q
I
t
I
I
I
I
t
I
I
I
=~==:=~:
~/I
00:
I
~-"'I
I
8-41
8.4.5
'~t'"
L_===:J
I
c====J
===:::J
1_=
2200 SIT - 9 SLOT (OP 20A)
:=J
110
C ==::J
",
C-=-==:J
'"
C===:J
[-_
J
~
c::::::==:::J
c:::::::::==:J
~=:J
'"
c:==:::J
'"
c:==:::J
'I/O
I
I c::::::::::==:J
c==::::J I
I c:==:::J
I
II
1c:==:::J
c::::::::=== I
I c:==:::J
C---J C
:::J c:==:::J
-I
I C:=:===:J I
I
I
II
1c:===:J
C:::::::::::=::JI
II
I
FIGURE 8-48
'"
",
TABLE 8-11
~
I
II
II
I
1
II
II
I
I
II
I
SfT\lith
0I'-20A,21
S/Tvith
OP-20A,22
,
S/Twith
,I
9-s1ot
Sw1thOP-2l'IA,24)
OP-20",23
I
I
672.5/6735,.
SE! ClL\l.T
POI. LOADDIG
LS67
"""'-'roo<
table 8-12 shows the various IlAH cCDfigUTadoD,8 for the 6707 aDd
6117 MOS HeJ.)ry Boards.
The 6717 can (Idly be used ill 2200 CPU.
where tCN 4795 haa buD. illlplemented.
The 6707, 6707-1, 6717 and
6711-1 are 4~. 81:. 81. and 16K K>S HuloI'1 80arda respectively.
1:\
"",""
"
"
m
'"
'"
,2<
,=
TABLE 8-12
1
,
6107
o.
'lG'
orEll
6301-1
6)07-1
o.
6107-1
o.
6107-1
o.
6701-1
o.
o.
'711
6717-1
no'
6307-1
o.
o.
1107
6701-1
O.
511)
orEll
6301-1
6717-1
'711·1
"11
6117-1
r
~
orD WIlEM
usn~
6711-1 1M SLOt'l
8-42
2200 SiT WITH OP-20A (9 I/O SLOTS)
6568 - WIRE SIDE
FIGURE 8-49
)
8-43
8.4.6
2200 PS- POWER SUPPLY FOR CPU MODELS A, B and C
FIGURE
8-50
-20VU FILTER CAP
124.000~f
EM! LII1E
FILTER
FRONT VIEW
,
115VAC/5A 5B
POWER - U ~
230VAC/3A SB
INOICATOR
FIGURE
2200 PS (POWER SUPPLY
8-51
FOR 2200 A/B/C cPU s
IN1200A
FOR +8 5VU
8-44
MDA-970
8-52
FH,Ul{r n-s'3
CLOSl-UP VIEW (TOP-RLllR SECTlOI,)
)
8-45
8.4.7
2215 BASIC KEYBOARD
The 2215 keyboard is comprised of a 6348 circuit board with I/O
cable (Ref:
Schematic Manual), mounted in a metal chassis.
FIGURE 8-54
To disassemble, remove six mounting screws from base plate; reverse
procedure for assembly.
The I/O controller for interfacing a 2215 keyboard with a CPU is
the 6367 circuit board.
This board is plugged into one of the CPU I/O
slots, shown in the CPU chassis layout diagrams in this publication.
8.4.8
2222 ALPHANUMERIC KEYBOARD
The 22b2 keyboard is comprised of a 6330 circuit board with I/O
cable (Ref:
Schematic Manual), mounted in a metal chassis.
FIGURE 8-55
To disassemble, remove six mounting screws from base plate; reverse
procedure for assembly.
The I/O controller for interfacing a 2222 keyboard with a CPU is
the 6367 circuit board.
This board is plugged into one of the CPU I/O
slots, shown in the CPU chassis layout diagrams in this publication.
8-46
-
8.4.9
2223
UPPER/roWER CASE ALPHANUMERIC KEYWORD KEYBOARD
The 2223 keyboard is comprised of a 6443 circuit board (also used as
2220 console keyboard) with the I/O cable (Ref:
Schematic Manual), mounted
in a metal chassis.
fIGURE 8-56
To disassemble, remove six mounting screws from base plate; reverse
procedure for assembly.
The I/O controller for interfacing a 2223 keyboard with a CPU is
either the 6367 (A, B, C systems) or the 6562 (S, T systems; 2220) circuit
board.
The controller is plugged into one of the CPU I/O slots, shown
in the CPU chassis layout diagrams in this publication.
8-47
8.4.10
2216/2217 VIDEO DISPLAY AND CASSETTE DRIVE CONSOLE
TAPE BUSY
INDICATOR
CASSETTE DRIVE
DOOR RELEASE
CASSETTE
REWIND
SCREEN
CONTRAST
IFRONT VIEW!
FIGURE 8-57
FIGURE 8-58
Y-IIIIIIIIIIIIIIIIIIIIIIIIIIII\\\\\
CONSOLE
EXHAUST
FAN
CASSETTE
DRIVE
CONTROLLER
CABLE
•
•
CONSOLE AC
LINE CORD
AC POWER
ON - OFF
DISPLAY
CONTROLLER
CABLE
IREAR
VIEW I
115V. 1.5A
SB
8-48
)
2216/2217 VIDEO DISPLAY AND CASSETTE DRIVE CONSOLE
REAR VIEW
VIDEO INPUT
CABLE
TD-24
MOTOROLA
XM-351
CHASSIS
(2216 )
(2217) - - - -....
HORIZONTAL
HOLD
VERTICAL
HOLD
I
\
TD-24
DRIVE ELECTRONICS
AC POWER
FOR CONSOLE
COMPONENTS
(2217)
FIGURE 8-59
The 2216 Video Display is comprised of an 8" x 10.5" CRT mounted in
a Motorola display chassis (Motorola #XM35l).
Also mounted within the
Motorola chassis is the CRT electronics plug-in circuit board (Motorola
IIv13A) •
FiGURE 8-60
RASTER
AC INPUT
CONNECTOR
1152JDV
AC SWITCH
VIDEO
CENTERING TAB
INPUT
MAGNETS
HDRIZ YOKE
LEAD (REO)
R18
R1B
T3
VERTICAL
OUTPUT
R18
TRANS
013
VERTiCAL
OUTPUT
MODEL XM351
CHASSIS REAR VIEW - COMPONENT LOCATION
MODEL 2216 VIDEO DISPLAY CHASSIS DIFFERENCES
Two versions of the WANG 2216 exist:
Version A (Figure 8-61) has one BNC connector and a 115/220 VAC line
switch mounted on the rear panel.
A 75 ohm termination resistor is
mounted on the Motorola circuit board.
8-50
115/220 VAC
LINE SWITCH
ONE BNC
CONNECTOR
FIGURE 8-61
MOTOROLA
CIRCUIT
BOARD
75 OHM
TERMINATION
RESISTOR ----!I~-
SLIDE
SWITCH
INPUT BNC
CONNECTOR
75 OHM
TERMINATION
RESISTOR
OUTPUT ENC
CONNECTOR
FIGURE 8-62
J
8-51
115/220 VAC
LINE SWITCH
FIGURE 8-63
Version B (Figure 8-62) has two BNC connectors mounted on the rear panel.
The 75 ohm termination resistor is mounted on a rear panel slide switch
instead of being mounted on the Motorola circuit board as in Version A.
The Version B rear panel slide switch is not to be confused with the
115/220 VAC line switch located on the Version A rear panel.
The
Version B 115/220 VAC line switch is relocated on the side of the
chassis as shown in Figure 8-63.
8-52
APPLICATION NOTE - Version B units may be cascaded by connecting a
male-to-male coaxial cable from the output BNC of the first unit to
the input BNC of the next unit.
Only the last unit must have the
75 ohm termination resistor switched in; all other units must have
the resistor switched out and the output BNC switched in.
Viewing
the Version B 2216 from the rear, sliding the switch to the left
switches the termination resistor in and the output BNC out; sliding
the switch to the right switches the termination resistor out
the output BNC in.
See Figures 8-64 and 8-65 below.
FIGURE 8-64
One Momror
Two
Qf
More Manltols (Senes Connected)
,."~~~j . ,"~::~:i~~;j~;J
INPuT JACK
Hl
OUIPUTJKCK
INPUIJ4CK
Hilc
OUTPUIJACK
,N'UTJAC.
flISOUTPUTJ.CK
Three or More Momtors (Senes Connected)
Impedance SWItch Arrangement
FIG.URE. 8-65
--E)
".
2216
CONTROLLER
IN
CPU
......
COAX
/'
....
~
-=-
8-53
"\
~
ann
8.4.11
2220 INTEGRATED VIDEO DISPLAY/CASSETTE DRIVE/KEYWORD KEYBOARD CONSOLE
,
'"\
(_l
CA"SnrJ
DInV::: .
HORIZONTAL
ADJUST
L
'
SCREEN
BUSY INDICATOR
_
(COVERED BY INSF.~
BRIGHTNESS
TAPE DRIVE
/
DOOR RELEASE
~ ~ CASSETTE DRIVE
~______ CASSETTE
----:::::-::--c:::--:....
;:-;:J
---- -:;:l
I,CRLCN CO~rRAo~J
__ 3"""
, ,
f i---.
f--:
..l3.
• I ,
\
,
I
\e.
,\ ~
REWIND
CPU BUSY
INDICATOR
UPPER/LOWER
CASE KEYWORD
KEYBOARD
FIGURE 8-66
IFRONT VIEW I
FI GURE 8-67
IREAR VIEWI
KEYBOARD ASSEMBLY
SCREW
11111111111111111111111111111111
•
•
covm
SCRE'IS
~
AC POWER
ON - OFF
KEYBOARD
&
CASSETTE DRIVE
CONTROLLER
CABLES
115V, LOA
SB
FUSE
AC LINE CORD
FOR CONSOLE
8-54
VIDEO DISPLAY
CONTROLLER
CABLE
rD-!4
MOLJ~JTI'J(;
SCD\J.. WS
(2 ea. SJllt,)
MOTOROLA
XH-227
CHASSIS
TOP/REAR
VIEW
617'> PC
~lOLEX
CO'f.'Il:CTOR
FOR FA:l
MOLEX CONNECTOR
FOR VIDEO INPUT
FROM BNC
AC I:lTERLOCK
SWITCH
fIGURE 8-68
TD-24
DRIVE ELgCl'JZO,lICS
FIGURE 8-69
DISPLAY
MOUllTIHG
SCREWS
MOU.X CONNECTOR
FOR FAll
HOU:X CO;nECTOR
FOR COV::R. ;II~,L.G
COVgR
BASEPLATE
HOUlITING
SCREIlS
(2 ea. side)
DISSASSEaBLY
VIEW
KEYBOARD
PLATE
MOUNTING
(2 ea. side)
COVER SCREWS
(LOC. @ REAR)
DRIve
KEYBOARD PLATE
:10UNTI:lG SCRr:WS
STRIP
8-55
2220 CONSOLE - TOP VIEW
FIGURE 8-70
8-56
The 2220 video display
1S
comprised of a 5.5" x 7.5" CRT, mounted
in a Motorola display chassis (Motorola #XM227).
Motorola chassis
1S
Also mounted within the
the CRT electronics circuit board (Motorola #V4lA).
FIGURE 8-71
XM-227
MOTOROLA
DISPLAY
CHASSIS
FIGURE 8-72
TO SERViCE
COMPONENT
SIDE OF
CIRCUIT BOARD
DISCONNECT
12 HIGH VOLlAGE
CAT SOCKET
OSEN 2 SCREWS
A AND REMOVE
XFMA
~LA~ ~~~~~~®
ON SIDE AND
SWING PANEL
H~f;':ENT~
~I ~(
~ .:v
H~iH
,,'VOLT/230VOLT
OPERATION
SELECTOR
_.:-
~;
~... "",",,
<
]~ Q.j.~:.~~~
~~
<~_
..
...... ~
A
~I
ACINPUT
R52VERTLIN
/
.--/
--- 8
A14 VIDEO BIAS
~~~MINATION
SWITCH
~~~ER
XFMR
e?~:~SITE
014 VERTICAL
OUTPUT
INPUT
8-57
~~ll~l~~~U:~~I~RiZROE~TU~~TOR
FROM BOTTOM
Qll
0101
ABU
REGULATOR
A9Z
HORIZONTAL
..,
QUT~ ~
~
CRT
R58
0103
SOCKET
PARTS LOCATION - BOTTOM VIRIii
FiGURE. 8-73
A coaxial cable with BNC connectors interface the display module
to its I/O controller in the CPU.
The primary I/O controllers for this video display are the 6312
plus 6313 p1ggyback configuration circuit boards for 60 Hz line operat1ng frequency.
For 50 Hz line frequency, the piggyback circuit board
1S a 6350 instead of a 6313 (Ref:
Schematic Manual).
The keyword keyboard is identical to the model 2223 (a 6443 circuit
board).
The I/O controller can be either a 6367 (A, B, C systems) or a
6562 (S, T systems).
As
Reference:
Schematic Manual.
w1th the 2223, an I/O cable connects cassette drive electronics
to CPU I/O controller.
8-58
8 4 12
2226 INTEGRATED VIDE 0
J l"PLAY /KJ YWORD KFYBOARD CONSOLE
FRONT
VIEW
FUNCTION STRIP
FIGURE 8-74
/' SCREEN BRIGHTNESS
FUNCTION STRIP
CLAMP
SCREEN CONTRAST
UPPER/LOWER
CASE
KEYWORD KEYBOARD
CPU BUSY
INDICATOR
REAR VIEW
FIGURE 8-75
115V, l.OA
SB FUSE
rillllllllllllll!1I111111111
,
KEYBOARD ASSEMBLY
SCREW
• •
KEYBOARD
AC POWER
ON - OFF
&
VIDEO DISPLAY
CONTROLLER
CABLES
AC LINE
CORD FOR
CONSOLE
MOTOROLA
XM351
DISPLAY
CHASSIS
BASEPLATE
MOUNTING
SCREWS
(2 ea
AC INTERLOCK
8-59
slde)
FRONT VIEW - DISASSEMBLED
HOLEX CONNECTOR
FOR COVER WIRING
KEYBOARD
PLATE
ASSY
SCREWS
(2 ea. s1de)
BASEPLATE
MOUNTING
SCREWS
(2 ea. side)
CONSOLE
COVER
KEYBOARD COVER
PLATE
Note that for 2216/17, 2220, and 2226 consoles, a coaxial cable with
BNC connectors interface all display modules to thin I/O controller in
the CPU.
Although certain options exist for console display character sets,
the primary I/O controllers for the Video Displays are the 6312 plus 6313
(piggyback configuration) circuit boards for 60 Hz line operating
frequency.
For 50 Hz line frequency, the controller board is a 6350,
instead of the 6312 (Ref:
Schematic Manual).
For optional dual
language (upper & lower case) character set, the 6529 piggyback circuit
board is attached to either 6312 (60
H~)
or 6350 (50 Hz).
Front and rear panel controls plus Motorola circuit board adjustments
are documented in the Electrical Adjustments section concerning the Video
Displays (page, paragraph).
8-60
8.4.13
2217 (TD-24) CASSETTE DRIVE
The 2217 Cassette Drive is comprised of a TD-24 (60 Hz unit) or
TD-24-l (50 Hz unit) mechanical drive unit, interface circuit boards:
6175, L558 and L559, and an electronic subassembly chassis (6324 motherboard accommodates L558, L559) with self contained power supply (Ref:
Schematic Manual).
The I/O controller for interfacing the 2217 cassette drive can be
either a 6316 (A, B, C systems) or 6562 (S, T systems).
An I/O cable
connects cassette drive electronics to CPU I/O controller.
FIGURE 8-79
FIGURE 8-78
FRONT VIEW
REAR VIEW
8-61
FIGURE 8-80
REVERSE R.EEL
CAPST.\~
~:OTOR
CASSETTE CUI C<:
FIGURE 8-81
ICASSETTE CUIDE!
CAS;~~
GUIDEI--
_
8-62
CAPST!'1-1
~
OTOR
FIGURE 8-82
8.5
COMPONENT REPLACEMENTS
CAUTION:
Always disconnect the line cord from the power
source before servicing any unit.
8.5.1
CPU
Printed Circuit Boards:
(a)
Remove top cover.
(b)
Remove the PC boards by pulling upwards.
Power Supply Components:
)
(a)
Remove the four screws securing the top cover and remove cover.
(b)
Remove the four screws securing the bottom cover and remove cover.
(c)
Desolder the defective component from the bottom side of the
motherboard.
8-63
8.5.2
VIDEO DISPLAY UNIT
Printed Circuit Board Removal:
(a)
Carefully remove the socket from the CRT.
(b)
Gently pry the circuit board from the chassis.
(c)
Lift the circuit board up and out of chassis.
CRT Replacement:
CAUTION:
Use extreme care in handling the CRT as rough
handling may cause it to implode. Do not nick
or scratch glass or subject it to any undue
pressure in removal or installation. Use goggles
and heavy gloves for protection.
(a)
(b)
Turn display unit power OFF.
Disconnect CRT socket by applying a gentle, steady pull to the rear,
as shown below.
FIGURE 8-83
8-64
(c)
Attach one end of a heavily insulated length of wire with insulated
alligator clips to display chassis ground (not to
±0
volt logic
ground).
(d)
Clip opposite end of ground wire to the metal shaft of a heavy duty
plastic handle straight-slot screwdriver.
CAUTION:
SEE FIGURE FOR FOLLOWING PROCEDURE.
(e)
Using a plastic-shaft alignment screwdriver, lift the rubber anode
cap covering the CRT anode connection enough to allow insertion
of the tip of the metal shaft screwdriver to be used to ground the
CRT high voltage anode.
FIGURE 8-84
(f)
Without scratching or nicking the CRT, and without touching the
metal screwdriver shaft with your hands, discharge the CRr anode
by touching the grounded screwdriver to the metal CRT anode clip
while it is still connected to the CRT.
(g)
Remove shorting wire hookup.
(h)
Remove CRT from chassis by loosening screws at corners of CRT and
sliding the CRT forward.
8-65
(i)
Remove retaining band if present.
(j)
Remove the deflection yoke from the CRT.
(k)
Apply tape to the replacement CRT before installing.
If new tape
is not available, reuse the tape from the old tube.
(1)
Mount the deflection yoke on the replacement CRT.
(m)
Ins tall the new CRT and secure the screws.
Power Transistor Replacement:
When replacing any "plug-in" transistor, Le., the regulator, horizontal
or vertical output, please observe the following precautions:
(a)
The transistor sockets are not captive, that is, the transistor
mounting screws also secure the socket.
When installing the
transistor, the socket must be held in its proper location.
This location is indicated by flanges on the socket which fit
into the heat sink.
(b)
When replacing the regulator and output transistors, silicone grease
should be applied evenly to both sides of the mica insulator.
(c)
All transistor mounting screws must be tight before applying power
to the display unit.
This insures proper cooling and electrical
connections.
NOTE:
Use caution when tightening transistor mounting
screws. If the screw threads are stripped by
excessive pressure, a poor electrical and mechanical connection can result. Non-compliance
with these instructions can result in failure of
the transistor and/or its related components.
8-66
8.5.3
TAPE DRIVE UNIT
6175 Printed Circuit Board Removal:
(a)
Desolder the head cables from the 6175 PC board.
(b)
Remove the finger connector from J2.
(c)
Remove the three screws holding the PC board to the tape drive.
5960 Phototransistor Assembly Replacement:
(a)
Remove the four wires from the tape head by pulling upwards.
(b)
Remove the four screws holding the PC board in place, shown as "A"
in Figure 8-85.
FIGURE 8-85
FIGURE 8-86
00
0
00
)
8-67
(c)
Desolder the yellow and blue wires from the 5960 PC board.
(d)
Install a new PC board in the reverse order.
The correct placement
of the head wires is shown in Figure 8-86.
Head Assembly Replacement:
(a)
Remove the 5960 Photo transistor Assembly as described in steps (a)
and (b) above.
(b)
Remove the two large, outermost hex screws from the head assembly,
shown as "B lI in Figure
8-85.
(c)
Install the new head assembly in the reverse order.
(d)
Perform the Head Skew Adjustment as described in paragraph 8.3.4.
Capstan Drive Belt Replacement:
(a)
Loosen the capstan motor pulley and push it toward the rear.
(b)
Remove the defective drive belt.
(c)
Install a new drive belt.
(d)
Rotate the reverse capstan pulley until the capstan motor pulley is
positioned correctly on the shaft.
(e)
Tighten the capstan motor pulley.
Opaque-Detect Light Source Replacement:
(a)
Remove the two knurled nuts from the rear of the 6179 PC board.
(b)
Pull the board toward the rear.
(c)
Desolder the two wires on the PC board.
(d)
Install a new PC board in the reverse order.
8-68
SECTION 8
NOTES:
)
8-69
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
~I
I
I
I
I
~I
I
I
I
I
I
I
I
"."
J
I
I
I
I
SECTION 9
2200 SYSTEM
OPTION CONVERSIONS & RETROFITS
This section describes 2200 system conversion and retrofit
porcedures. with references called out for diagnostic tests and/or
PROM/ROM loading of circuit boards where required.
The following software/hardware options are available for 2200
A. B. C. Sand T systems:
TABLE 9-1
2200 OI'TIOH ,
WLI STOCI. ,
morIOtf D!SCI.IPTlO!l
ACOOIK)MTINC CPU - (USACE)
2200A
117-2200Pl
Or-2
177-22OOP2
General I/O 10M
"-3
177-2200'3
Edit 10K
or..
177-22OOP4
Audio Alan for
OP-S
117-22oopS
Matrtz
22001
2200c
2200$
1200t
.,K Mu.tually
or-1
axcluiw vith
01-'
J:
Stallard
Sc..adard
Sundard.
2216 Dhplay
CoaIIerc1al Matrix/
Sort ROH(Hutually
uc:luaive with or-1)
Or-20
117-2200-20
OF-lOA
177-2ZOQ-ZOA
9 1/0 Slot OIass18
Or-21
177-2200-21
Katru ROM.
St.adard
Or-22
177-2200-22
Advanced Prograllllll8ble
5t_ourd
3 Extra I/O Slots
10K plus OP-21
OP-2)
177-2200-23
CeDeral I/O ROM
Standard.
plus 01'-22
Or-24
177-2200-24
Disk C8pablltty
SuDd.lrd
plus or-23
"-30
177-2220-30
Upper/Lower ca.e
DiBplay (for 2220.
2216,\. or 2226)
OP-31
177-2220-31
Audio Aut'll for
2220 -.4 2226
coDsoles
OP-32
177-2220-32
lCeyboud Clicker
X • Opt lor. .-vaHahle:
- - Option DOt avan.bi'"
9-1
9.1
2200 A/B/C ROM £. SUPERPATCH OPTIONS - PREREQUISITE INFORMATION
An introductory explanation of ROM «(,125) and Superpatch (6547,
fJ527) circuit board versions used in A, R, and C CPU's conversions
follows:
9.1.1
SUPER PATCH BOARDS
The following patch/superpatch boards exist:
(a)
(b)
6127 - First revision patchboard, now obsolete.
6527 - First "superpatch", supercedes the 6327 PC.
See ROM and
SUPERPATCH chart, page 9-5.
(c)
6547 - Latest version of 2200 A/B/C superpatch PC board.
Many
intermi ttent software problems and problems associated with 2200
disk sys terns can be eliminated by subs titut ing a (,547 version j n
place of a 6527 superpatch.
See ROM and SUPERPATCH chart, page 9-5.
The 6547 was initially installed on a customer complaint basis,
wjth priority to 2200B systems incorporating disk units (2230, 40, 42,
41, 60).
The (,547 must be used in all 2200C systems and will be used in
all existing 2200 A and B systems.
Use 6527 PC boards as is in all existing 2200 systems, except
for the limitations stated above and in the ROM and SUPERPATCH chart,
on page 7-5.
9.1.2
MARKING OF ROM AND SUPERPATCH PC BOARDS
Suffix identification of software (ROM/PROM) circuit board loading
is as follows:
A
2200 A
CPU
B
2200 B
CPU
9-2
C
2200 C
X
Software extension for 6325-B or -C; packaged on separate
CPU
M
Matrix Option (Option 1) for 2200B/C
PC board labeled 6125-BX or
GIO
E
SORT
K
-ex.
General I/O (Option 2) for 2200B/C
Edit (Option 3) for 2200 A/B/C/S.
Sort (Cornmerical Matrix) Option (Option 5) for 2200B/C
Katakana; Japanese (mutually exclusive with Edit)
Numbers appearing in a PC board suffix identification indicates a
software update.
Example:
Improvements made in the microprogram for 6325-BXl
ROH ICs resulted in a "new" PC board,
places -BXl).
6325-BX~
(re-
The only physical differences between
BXl and BX2 are that L5, Lll, LIS, L21, L25, and L35
(ROM ICs) have updated patterns (different WL #377-XXXX
stock numhers).
Q.2
MODELS 22005 and 2200T ROM BOARDS
The original ROM board, the 6725, with 12K capability was phased
out of production and replaced by the 6735 24K ROM board.
The 6725
can only be used in 22005 and -SE units without software variations.
All future units will contain the 7025 or 6735 ROM board.
See 6735/7025
loading charts in this section.
Microcode bugs were discovered involving three ROM chips on the
6735, however the bugs do not interfere with the basic 22005 system.
If a software option is added, the three chips noted below must be
checked and changed
dS
a group if necessary:
IC LOCATION
FROM
TO
L26
377-0238
377-0292
L23
377-0239
377-0293
L2
377-0240
377-0294
)
9-3
The Hodel 2200T
IS
equiv~lent
to the software capability of a
nooc
wi th Options 1, 2 and 5 (Matrix ROM, General I/O and Commercial Matrix
respectively).
The loading of the 6735 board contains the integrated
circuits for Option 24 plus five additional Ies for disk capahility.
9.3
ROM AND SUPERPA1CH CHIIRl - 2200 A/B/C/S/T r,PI,'s
This chart (Figure 9-1) provides a cross reference between 2200A,
B, C, Sand T RO!': options and the required
soft~lare
versions of (,325
(2200A/B/C) or 6725 (2200S) or 6735/7025 (2200S/T) 20-bit ROMs, 6527 or
6547 Superpatch (2200A/B/C), 6361 8-bit ROM (2200A/B/C), and (,708 Memory
Control (2200S/T).
Identification of ROM options is as follows:
OPTION 1/
DESCRIPTION
1, 21
Mat rix
2, 23
General I/O
3
Edit ROM
RO~1
~
OP 22
5
Sort /CoDunerci al Matrix ROM
22
Advanced Programmable + OP 21
Disk ROM + OP 23
24
Japanese
Option
Katakana ROM
To find which versions of RON and Superpatch boards are required:
1)
Locate the CPU version A, B, C, S, or T.
2)
Locate option(s) being used.
3)
Place straight edge (ruler, etc.) so that it underlines the desired
CPU and option(s)
4)
co~ination.
Read across (left-to-right) and up at each mark on that horizontal line.
For example:
A 2200B CPt' with options 2 apd 3 require a 6325-Bl,
6325-BX2-GIO, 6547-E4-E, and a 636l-B.
9-4
~
)
,,,
"."
,,,
"
I
en
LU
0<
=>
t!>
u::
".
'"
".
n.
".
OI~HIJC:)
lllOSn:>
OI~
Ix:)
"
~
~6
".
"
nos n:Q
O!:)-GJrH
".
'CO
-0'
·. .••· ••·•·•·•·•·•· ·
9-5
__
__
..
Across the top of the ROil and Superpatch tahle 1S a llSt of page
nUP1hers In thIS sectIon where the load] ng dIagram for each software verSIon
of the boards can be found.
For 1nstance, the 10ad1ng d1agrarns for the
boards called out 1n the example above ,"ould be found on the follow1ng
pages:
PAGE II
PC /I
FIGURE II
6325-Bl
9-27
9-19
6325-BX2-GIO
9-11
9-4
6547-B4-E
9-14
9-9
636l-B
9-29
9-25
Be aware that certa1n opt1ons use e>ther a 6527 verS10n or a 6547
vprSJon Superpatch; the fInal determInatIon 18 based on the facts stated
1n paragraph 9.1.1.
As a general gU1del1ne, the (,547 1S requ1red 1n
systems w1th dlSYS or 1n systems ,"lth 1nterrn1ttent software problems;
also,
6547-Al
replaces
('527-Al
6547-AIE replaces
6527-AIE
6547-B4
6527-B2
replaces
6547-B4E replaces
6527-112E
6547-B6K replaces
6527-B3K and
6547-B5K
Before 1nstalllng any 6547 or 6527 Superpatch 2200 A, Band C
Opt1on boards, lt 1S 1rnperat1ve that the follow1ng Clrcu1t boards be
checked (and updated 1f necessary; Ref:
Techn>cal Procedures Manual)
for proper "Electron1c Level" mark1ng (Ref:
as 1nd1cated on page 9-7.
9-6
SerVlce Newsletter Vol 3 115)
ELEC.
LEVEL
CIRCUIT
BOARD
m
L558
GJ
6311Rl
[!]
6316
Since the 6527 and 6547 superpatch boards are software extensions
for EA ROM 6325 boards, they may be plugged into anyone of three ROM
board slots (6322 motherboard), or into anyone of four ROM board slots
(6522 or 6222 motherboards).
After installation of an updated ROM or Superpatch circuit board has been
completed, a possibility exists that re-recording of customer tapes may be
necessary, due to a change on the DATA RESAVE function.
To determine the likelihood of the above situation, instruct the
customer to load all Data tapes into the system and verify their integrity.
If ERROR 43 is generated during verification, note which block(s) produced
the error.
Any tapes with invalid blocks must be reconstructed by the
technique described below (it is imperative that this procedure be carried
out promptly):
(a)
Request one 2217 on loan from Home Office.
(b)
Insert loaned 2217 controller (device address switches set to HEX OB)
into CPU I/O slot.
(c)
Load one block of customer's tape into the system via console tape
drive, checking again for errors.
(d)
Record that block on the external 2217.
(e)
When an erroneous block is encountered, that block must be manually
re-entered, then recorded on the external 2217.
(f)
This procedure should be repeated for all blocks, until all tapes
are correct.
9-7
(g)
Return loaned 2217 to Home Office.
(h)
Any further problems should be referred to the Home Office for
resolution.
THIS SPACE INTENTIONALLY LEFT BLANK
9-8
9.4
9.4.1
)
OPTION CONVERSIONS
OPTION 1
(MATRIX OPTION) - CONVERSION PROCEDURE (Kit, WL #177-2200 PI)
Option 1 is available only for 2200B or 2200C systems; parts required
are as follows:
2200B SYSTEM
2200C SYSTEM
(a)
6325-Bl
6325-Cl
(b)
6325-BX2
6325-CXl
(c)
6547-B4
6547-C1E
(d)
Four EA ROM ICs:
Four EA ROM ICs:
WLI 1/377-0223 (L3)
WLI 1/377-0223 (L3)
WLI 11377-0224 (L7)
WLI 11377-0224 (L7)
WLI 11377-0221 (112)
WLI 11377-0221 (112)
WLI 11377-0222 (L16)
WLI 11377-0222 (L16)
INSTRUCTIONS:
The above four EA ROMs (item d) must be loaded on either the
6325-BX2 (for 2200B system) or on the 6325-CXl (for the 2200C
system).
Loading diagrams are provided as follows:
FIGURE 9-2
D
D
D
D
D
D
D
D
6325-BX2/H
NOTE'
·(Asterillk) denotes Ie's added for tlatrix Option
(Option 1)
9-9
D
D
D
6325-CXI/K
NOTE"
*(.... teriBk) denotes 4 Ie'. added for Katr1x Option
(Option 1)
FIGURE 9-3
After EA ROMs have been loaded on the 6325-BX2 (2200B) or 6325-CXl
(2200C) , change the white sticker-label on the wiring side of that PC
board as follows:
LABEL CHANGE
SYSTEM
PC /I
FROM
TO
2200B
6325-BX2
BX2
BX2/M
2200C
6325-CXl
CXl
CXl!M
This label reflects the specific option which has been added, for
future identification.
Refer to Section 7 for OP-l Diagnostic test.
9-10
9.4.2
OPTION 2 (GENERAL I/O) - CONVERSION PROCEDURE (Ki t, WL #177-2200 P2)
Option 2 is available only for 2200B or 2200C systems; parts
required are as follows:
2200B SYSTEM
2200C SYSTEM
(a)
6325-B1
6325-Cl
(b)
6325-BlCZ
6325-CXl
(c)
6547-B4
6547-C1E
(d)
Six EA ROM lCs:
Six EA ROM lCs:
WLl 1/377-0249 (L13)
WLI 1/377-0249 (U3)
WLI 1/377-0250 (L17)
WLI 1/377-0250 (U7)
WLI 1/377-0247 (L23)
WLI 1/377-0247 (L23)
WLI 1/377-0248 (L27)
WLI 1/377-0248 (L27)
WLI 1/377-0245 (L33)
WLl 1/377-0245 (L33)
WLl 1/377-0246 (L37)
WLI 1/377-0246 (L37)
INSTRUCTIONS:
Tr.e above six EA ROMs (item d) must be loaded on either the 6325-BX2
(for 2200B system) or on the 6325-CX1 (for 2200C system).
diagrams are provided as follows:
FIGURE 9-4
00
I7
*L377-02';0
00
o
0
f.ll'j-BX2/( 10
)
N(ll~
"(Allterl11k) d..llut.s b IC'II added (or General
1/0 (Option 2)
9-11
Loading
H
377-025!l
"L-l?
377-0250
D
D
D
D
6J25-cn/clO
NOTE:
"(Asterisk) doi!notl'8 6 le'e added for' General
I/O (Option 2)
FIGURE 9-5
After EA ROMs have been loaded on 6325-BX2 (2200B) or 6325-CXl (2200C),
change the white sticker-label on the wire side of that board as follows:
LABEL CHANGE
FROM
2200B
2200C
6325-BX2
BX2
BX2-GIO
6325-CXl
CXl
CXl-GIO
This label reflects the specific option which has been added; for
future identification.
Refer to Section 7 for OP-2 Diagnostic test.
9.4.3
OPTION 3
(EDIT OPTION) - CONVERSION PROCEDURE (Kit, WL #177-2200 P3)
Option 3 conversion is available for 2200A and 2200B systems;
option 3 is standard software in 2200C, 2200S and 2200T systems.
Option 3 allows the user to modify program statements with minimal
programming.
Three new debugging commands are introduced:
and ERASE.
9-12
INSERT, DELETE,
Parts required are as follows:
2200A SYSTEM
)
2200B SYSTEM
(a)
6325-A2
6325-Bl
(b)
6527-Al (or) 6547-Al
6527-B2 (or) 6547-B4
(e)
Six PROM lCs:
Six PROM lCs:
WLl 1/378-0256 (Ll)
WLl 1/378-0255 (L2)
WLl 1/378-0257 (L3)
WLl 1/378-0253 (L4)
WLl 1/378-0252 (L5)
WLl 1/378-0254 (L6)
WLl 1/378-0262 (11)
For
WLl 1/378-0261 (L2)
either
For
WLl 1/378-0263 (L3)
6527-Al
6527-B2
WLl 1/378-0219 (L4)
or
WLl 1/378-0258 (L5)
6547-Al
only
WLl 1/378-0260 (L6)
(OR)
WLl 1/378-0294 (11)
WLl 11378-0293 (L2 )
WLl 1/378-0295 (L3)
WLl 11378-0291 (L4)
WLl 1/378-0290 (L5)
For
6547-B4
only
WLl 1/378-0292 (L6)
Six PROMs in item (e) must be loaded on either the 6527/6547-Al (for
2200A system) or on the 6527-B2/6547-B4 (for 2200B system).
Loading
diagrams are provided as follows:
FIGURE 9-7
FIGURE 9-6
6527-AI/E
6527-U2h
~~qJ
1
DJ[][]
. ..
'~
9-J."l
FIGURE
6547-Al/E
9-8
6.547-B4/E
mmO]
mmO]
FIGURE
9-9
\\r---------------
6541-nh
0] OJ OJ 1
OJmm
9-14
FIGURE
9-10
After PROMs have been loaded on the 6527/47-Al (2200A) or the
6527-B2/6547-84 (2200B), change the white sticker-label on the wiring
side of the superpatch (just upgraded) as followh:
LABEL CHANt:!·.
SYSTEM
PC II
FROM
TO
2200A
6527-Al
Al
Al/E
2200A
6547-Al
Al
AIlE
2200B
6527-B2
B2
B2/E
2200B
6547-B4
B4
B4/E
This label reflects the specific option which has been added, for
future identification.
(d)
(e)
2200A SYSTEM
2200B SYSTEM
Edit Keyboard:
Edit Keyboard:
22l5E (6348/E PC)
22l5E (6348/E PC)
2222E (6330/E PC)
2222E (6330/E PC)
2223 (6443 PC)
2223 (6443 PC)
Keyboard Controller:
6367 -
Ensure that ECN's 4090 and 4525 have been performed
(R"f:
6317 -
Technical Procedures Manual).
L22
WI. 11377-0225, for 22l5E and 2222E only.
L22
WI. 11377-0260, for 2223 only.
Ensure that ECN 4090 has been p"rform"d (R"f: Technical
Procedures
WI. 11378-0249 for 22l5E only.
L2l
WI. 11378-0250Rl for 2222E only.
6528 - L23
L23
(f)
Manu~).
L2l
WL 11378-0249 for 22l5E only.
WI. //378-0250Rl for 2222E only.
Edit option Special Function strip:
WI. 1/615-0359
Refer to Section 7 for OP-3 Diagnostic test.
9-15
9.4.4
OPTION 4 & OPTION 31
(Kit,
(AUDIO ALARM)
- CONVERSION PROCEDURE
WL #177-2200 N)
The Speaker Option allows the user to program an audible alarm
which can be used as a warning device, error detector, or timer.
PARTS NEEDED:
1 - Speaker with hardware to mount on 2216/17 (or 2220) rear panel.
1 - Speaker cable.
1 - 63l2A/63l3 (or 63l2A/6529) 2216 controller with speaker socket for
60 Hz units or 6350A/63l3 for 50 Hz units.
PROCEDURE:
(a)
Replace the 2216 controller (6312) with a 63l2A PC for 60 Hz units
or 6350 with a 6350A pc for 50 Hz units.
(b)
Mount speaker on bracket provided in conversion kit.
(c)
Install cable to speaker.
FIGURE 9-11
10 CRT CO~:TROLU H
PIIONL JArK
9-16
(d)
Rcute speaker cable out via CRT cable hole in 2216 or 2220 chassis
ar.d plug this cable into the 2216/2220 CRT controller board (63l2A) Or
6350A).
Refer to Section 7 for OP-4/3l Diagnostic test.
9.4.5
OPTION 5 (SORT ROM) - CCRVERSION PROCEDURE (Kit, WL #177-2200 P5)
Option 5 is available only for 2200B or 2200C systems; parts required
are as follows:
NOTE:
Options 1 and 5 cannot be incorporated into the
same 2200 system simultaneously; i.e., they are
mutually exclusive.
nOOB SYSTEM
2200C SYSTEM
(~)
6325-Bl
6325-Cl
(b)
6325-BX2
6325-CXl
(c)
6547-B4
6547-CIE
(c)
Four EA ROM 1Cs:
Four EA ROM 1Cs:
WL1 11377-0267 (L3)
WL1 11377-0267 (L3)
WL1 1/377-0268 (L7)
WL1 11377-0268 (L7)
WL1 11377-0265 (L12)
WL1 1/377-0265 (L12)
WL1 11377-0266 (L16)
WL1 1/377-0266 (L16)
The above four EA ROMs (item d) must be loaded on either the
6325-BX2 (for the 2200B system) or on the 6325-CXl (for the 2200C
system).
Loading diagrams are provided as follows:
)
9-17
D
D
D
D
D
D
D
D
6J15-BX2!C;ORT
NOTE:
.(AIIt"rhll) dl!nntea Ie'. addad for SORT Option
FIGURE 9-12
o
D
D
D
D
D
6J25-CXl/sORT
NOT!:
-(Altarhk) denot . .
Ie'.
added for SORT Option.
FIGURE 9-13
9-18
~
~
'\,
/
After EA ROMs have been loaded on the hl25-IlX2 (220011) or hJ25-CXI
(2200C), change the white sticker-label on the
wirin~
side of that PC
board as follows:
LABEL CHANGE
SYSTEM
PC II
FROM
TO
2200B
6325-BX2
BX2
BX2/S0RT
2200C
6325-CXl
CXl
CXl/SORT
This label reflects the specific option which has been added, for
future identification.
Refer to Section 7 for OP-5 Diagnostic test.
1.4.6
OPTION 20 (THREE EXTRA I/O SLOTS FOR 2200S CPU)
CONVERSION PROCEDURE (Kit, WL #177-2200-20)
To add Option 20, the following parts are required:
DESCRIPTION
CPU Cover, WL #451-2101
6
Connectors, !iL #350-0011
2
Blank Face Plate, WL #449-0096
4
Screws, WL #650-4165
(a)
Unplug unit from outlet.
(b)
Remove the top and bottom covers and all PC boards.
(c)
Starting with the first I/O board, remove all hex nuts and hardware
up to, but not including, the L567 board.
Be sure to mark the location
of the nylon insulating washers (8) to be sure of correct replacement.
Put the hardware in a safe place.
9-19
(d)
Remove the two hex spacers from under the fourth I/O space.
Discard
the spacers but retain the screws.
(e)
Gently pull the right side of the motherboard away from the chassis.
Slip the six connectors between the chassis and motherboard.
(f)
Push the motherboard back into position while guiding the connectors
through the slots in the chassis.
Replace all hardware and tighten
securely.
(g)
Install three I/O controllers in the connectors installed in Step (e).
(h)
Solder all pins of the six connectors installed in step (e).
(i)
Be sure to follow the above procedure to insure proper connector
alignment.
(j)
Check for solder bridges and cold solder joints on all pins.
(k)
Replace covers.
Top cover is replaced with new cover allowing
access to all I/O connectors.
(1)
Install I/O controllers and connect the I/O cables from the
respective peripheral device.
(m)
Plug unit into outlet and apply power.
Check power supply voltages
and readjust if necessary, due to the increased load.
(n)
9.4.7
Return CPU cover #451-2105 to Home Office.
OPTION 20A (9 SLOT I/O) - CONVERSION PROCEDURE (Kit WL #177-2200-20A)
Request a 9-slot I/O 22005 or 2200T chassis and return previous
chassis to Home Office when 9-slot I/O CPU arrives.
9.4.8
OPTION 21
(MATRIX ROM) - CONVERSION PROCEDURE (Kit, WL #177-2200-21)
This is the software equivalent to Option 1 (2200A/B/C); Option 21
is for 22005 only (automatically included in 2200T software).
9-20
INSTRUCTIONS:
After changing LIon the 6708A from WL 11377-0259 (without Option 21)
to WL 11377-0244 (with Option 21), change the sticker label to 670BB
on the wiring side of the 670B PC board.
Testing Option 21:
Use Option 1 Matrix Diagnostic in Section 7.
9.4.9
OPTION 22 - ADVANCED PROGRAMMING AND MATRIX ROMS
A conversion kit, consisting of 6715 ROM board, ICs L2 (377-0294),
L4 (377-0297), L21 (377-0296), L23 (377-0293), L26 (377-0292), L2B
(377-02 Q 5) and an additional ROM IC, 377-0283 (for the 6708 pc), is
supplied.
Remove the 6725 or 6735 ROM board from the CPU.
Insert the new
Ie's (L3, LIO-L15, L22, L25 and L27) on the 6735 ROM board.
Change the
6735 sticker label from 6735A to 6735B and reinstall the upgraded 6735
ROM board into the CPU.
dlJU'" \lITH OPTION 22 LOADING CHART
~~~~Q~DD
~~
~~
~~
L12 .
1.11
un
~
1.9
1.8
o~ ~s~ EJo~
~
l'
1..2)
67]5-1'.
~I'
~
L22
1..21
l'
D
1.20
DD~~
1.5
~~
-, I
V"
~~I
~~
.=-1
L4
L)
12
nnWl~~
~Ldldld~
nrmmlWlml
bJl:JldLdbJ
6708 Ht!!;T CONTAIN A. 377-0283 (OR -312 WllEN -0283 EXHAUSTED)
"Mdtrtnru.l flllJlfl FrOG! 671')-" to 6735-1\ .
.../
FIGURE 9-14
9-21
Remove the r 70 8 PC board.
377-0283.
Remove Ll and replace it with ROH
Change the sticker label from 670RA or H to
('70RC,
1C
and re-
install the 6708 pc board into the CPU.
NOTE:
The 377-0283 ROM used on the 6708 PC SOARD requires that the single key command LIST be disabled. To initiate a LIST, the word must be
spell ed out.
To test Option 22, use the 2200B, 2200S and Matrix Diagnostic
Programs as described Section 7.
9.4.10
OPTION 21 - GENERAL I/O, ADVANCED PROGRAMMING AND MATRIX ROMS
A conversion kit consisting of a (,735 ROM board IC's L2 (377-0294),
L4 (377-02 9 7), L9 (377-07.84), Ll(, (377-0285), L2l (377-0296), L23 (3770293), L2(' (377-0292), L28 (377-0295) and an additional ROM, 377-0283
for the (,708 pc is supplied.
Remove the (,725 or 6735 ROM board from the CPU.
Insert the new
IC's (L3, LIO-L15, L22, L25 and L27) on a 6735A or B ROM board.
Change
the 6735A or B sticker label to 6735C and reinstall the upgraded (,735
ROM board in the
cpu.
2200<; wITH OPT!011 23 LOAfHNG CHART
D D[J [Jw
" [Jw [Jw
s::: ~2::: ~2~ D
DEJ
~
Q~:J Q~:J ~C;:J ~:;:~
~
,
LIZ
0'
I
Lli
.....
I
r.w
.f'
[..'J
~ [J~
f',
IH
I
1.23
,
~
L22
67011 ~IUST (,ONTATN A )77~02R)
(OR -312
Cl'
1.21
""'lin
"
117
-0281 EXHAUSTff)J
9-22
11'1
~Q
..........
~.....
V'I
U9
FIGURE 9-15
-.J
,~
rlf,
w
"'Additioni'll Chip"! from 6135-/\ t.o 6735-C.
N
w-'
I
I
V'
1.20
~.
Il
rn.....
,
....
""
II,
.,
l,o>
t~
o..J
"
.....
.0 -,
..... 1
6735-C
,
U8
'"
-.D
~,
.}
L'I
II
t>.....
w.....
~
I
IJI,
~w••
""
~
......
~
I
11\
~~ ~~ ~w,
""'....
...........
'-',
U7
N....
.j'
~....
U6
N"
. . . ....._
~
US
Remove the 6708 board.
the 377-0283 ROM IC.
Check ROM IC Ll; if not a 377-0283, install
Change the 6708A or B sticker label to 6708C and
reinstall the upgraded 6708 board into the CPU.
NOTE:
The 377-0283 ROM used on the 6708 PC board requires that the single key command LIST be disabled. To initiate a LIST, the word must be
spelled out.
Return 6725 ROM board for credit.
To test Option 23, use the 2200B, 22005 and Matrix and GIlD Diagnostic programs as described in Section 7.
9.4.11
OPTION 24 - DISK ROM
Upgrading any 22005 to OP-24 is equivalent to converting to a 2200T
CPU.
A conversion kit consisting of all ICs in the OP-23 kit, plus
five new ICs (L5 = 377-0307, L8 = 377-0303, L17 = 377-0304, L20 = 377-0306,
and L29 = 377-0305) for disk capabilities.
Follow directions for OP-21 (except for label changes) and add the
5 new IC's as indicated on the 6735 loading diagram for 2200T (6735D)
below:
2200t LOADING CHART
(OR)
2200S WITH OP-24
LOADING CHART
~~~~~
w ~.:
~J
~
~~
~~
*~
~~
~~
1..12
1..11
1.10
1..9
1.6
~1
8~
~1
[;Jw
i~
1.2)
1.21
LZl
1.20
6735-D
FIGURE 9-16
ll.
~
~~
\..4
67H-r to 673S-D.
.... ( hi 1"9 lddf'd t (l fonn a f, 7)5-0
9-23
g~
LJ
L1
rinmlWlmlfm
~~ld~GJ
~~~~D
0......
0......
0.....
0.....
........
........
~...
51'
.........
:el'
t.1
129
1.28
1.27
1.26
US
5:1'
fl70A MUST CONTAIN A 377-0291.
"".1'111"" chan~ed from
81 ~w
.: [Jw ~~
8~
L5
N-..l
0
....
"' .....
Change labels on 6735 (A, B, or C) and 6708 (A, B, or C) to 6735D
and 6708D respectively.
Use 2200T d1agnostics in Section 7 to test Opt10n 24.
9.4.12
OPTION 30 (UPPER/LOWER CASE DISPLAY) - CONVERSION PROCEDURE
1)
Remove CRT Controller (6312/6313) from CPU I/O slot.
2)
Remove the nylon hardware holding the 6313 PC hoard to the
63l2/63l2A controller chassis.
3)
Replace the 6313 PC board with a 6529 PC board.
4)
Replace all hardware and tighten 6529 and 63l2/l2A securely.
5)
Reinsert converted controller into the CPU I/O slot.
6)
Test for upper and lower case characters on the CRT screen.
(Be
sure the keyboard switch is in the A/a position.)
7)
Change s ticker on controller face plate from "2216" to "22l6A".
8)
Return 6313 to Home Office for credit.
9.4.13
OPTION 32 (KEYBOARD CLICKER) - CONVERSION PROCEDURE (Kit, WL #200-0036)
CONVERSION KIT
1-
Two 1" spacers (462-0019)
2.
Two 1 1/2" 4-40 screws (650-2480)
3.
Three 1/8" spacers (462-0110)
4.
Three 1/2" 4-40 screws (650- 2160)
5.
Two 5/16" 5-40 screws (650-2902)
6.
Two //4 lock washers (653-2002)
9-24
7.
Two 114 fldt washers (653-2000)
8.
nO-6771 PCB
9.
10.
B.
ColI (320-0049)
Rlght angle hracket (451-4379)
INSTALLATION PROCEDURE
1.
Parts and tools required:
(a)
2.
Conversion kit
(b)
Soldering iron and solder
( c)
Approximately 30" of 28 gauge wire
(d)
Approximately 6" of tubing
(e)
Straight edge and Phillips screwdrivers
Howlt rlght angle bracket to the coil uSlng 5/16" screws and
flat washers so that screwS do not touch the coil.
3.
MODEL 2220 AND 2226 - Mount the 6771 board to the 6443 keyboard
using the 1" spacers and 1 1/2" screwS.
The wire slde of the
6771 must face the wire side of the 6443.
MODEL 2215, 2222 AND 2223 - Mount the 6771 board to the 6441,
6330 or 6348 using the l/e" spacers and 1/2" scre"s.
The wire
side of the 6771 must face the wire side of the 6443 or 6330.
l/~"
spacers and 1/2" screw to mount coil as shown.
4.
Use
5.
Connect four wires as shown in diagram:
1/1 is connected to +l5VR.
(a)
W~re
(b)
Wire 112 lS connected to +OV.
(c)
Wire 113 is connected to pin 27 of the 50-pin male
(d)
Wlre #4 lS connected to pln 29 of the 50-pin male
connector (+5V).
connector (KST).
9-25
6.
Check the keyboard controller in the system:
(a)
If the keyboard controller is a 6741 or 6742, the
installation is complete.
(b)
If the keyboard controller is a 6367, check for ECN #4B49;
this ECN must be incorporated.
ECN 4B49:
Add a jumper
from pin B (+5V) to Jl-27. Add a jumper wire form L24-B
l
to L20-9. Add a jumper wire from L20-8 to Jl-29.
(c)
If the keyboard controller is a 6562, check for ECN #4850;
this ECN must be incorporated.
ECN 4850:
Add a jumper
wire from pin B (+5V) to Jl-27. Add a jumper wire from
l
L3l-8 to L27-9. Add a jumper wire from L27-8 to Jl-29.
FIGURE 9-17
HOUNT 6771 Hl:.Kl:.
LSl~(.
SLRF\.'<; MD SPACERS
O'
:r~~~
•
If the option does not work, follow these steps:
(a)
Verify +15VR on the 6771 board with power on.
(b)
Verify +CV on the 6771 board.
(cl
Insure that wire #3 is connected to pin 27 of the male
connector (+5V).
(d)
Insure that wire #4 is connected to pin 29 of the male
connector (KST).
(e)
Using a scope, check for a KST pulse when a key is depressed.
(f)
Verify that ECN's are incorporated correctly.
9-26
ADDITIONAL ROM &SUPERPATCH LOADING DIAGRAMS
I=l
~
L-l
371-0161
FIGURE
9-18
r:;-l
~
L-l
]17-0163
FIGURE
9-19
632:>-81
DD
DD
0
I
,/
D
DD
00
0
D
6325-BXl
9-27
FIGURE
9-20
00
00
00
00
o
o
o
FIGURE
9-21
o
6J25-BX1
"(ABte["lak) denotes le'a that differ frOIll 632S-BXl
P.C. board
FIGURE
9-22
6J2S-Cl
NOTE:
""(Asterisk) denoteB thp
the 6325-81
0
00
1('9
p.e
that differ froal
bond
o
*L-8
377-0258
o
o
00
o
o
6325-CXl
NOTE:
"'(Aerisk) denotes 2 IC'~ that differ frolll
the 6325-8X1 J> C
9-28
board
FIGURE
9-23
6361-Al
6361-81
ornrnrn
rnrnrnrn
9-29
FIGURE
9-24
FIGURE
9-25
FIGURE
6527-Al
9-26
\\,-------------
6527-11
FIGURE
9-27
FIGURE
9-28
9-30
FIGURE
6547-Al
9-29
[J. [J. [J.
[][][]
00
t. ...
:t
6547-B4
9-31
00
t. ...
:t
00
t. ...
It
FIGURE
9-30
00000 0
CJ
[=:J
FIGURE 9-31
22005 LOA,DINL CHART
~~~nn
tJlJldU~
6735-.
~~DD
"UPON SUPPLY DEPLETIOtoi OF ntl':SE THRFE CHIPS, USE THE
FOIl-OWING:
DD~~
nnWl~ml
~L:JldLdbJ
~~~~~
CJD~
........
w-..
........
1.27
..... ,
1.26 - 377-0218 U8e 171-0292
1..21 - )11-02)1 U8e 311-029)
L2 - 377-0240 U.e )77-0294
NOTE:
1.29
THE ABOVE CHIPS ARE A CROUP AIm MUST BE REPUCED TOGETHER.
6108 BOARD CONTAINS A )77-0259 OR 02U (MATRIX)
9-32
1.28
FIGURE 9-32
""....
...,
0>.
....1
1.26
U5
~
........
FIGURE 9-33
2200T LOADING CHAIlT
:
~':: '2°':: ~.o~:1' ~~'::
D~~
~
~I'
';; I'
Ll2
Lll
I'
LIO
L9
81'
6735-D
L8
N....
~j"
, 1.23
0""
0""
0 ....
81'
:1'
il'
122
1.21
1.20
""....
N....
e~
tot ....
~,.
~l'
e~
e~
B~
e~
L11
Ll6
LlS
Ll4
L13
~
~j"
~,.
~,.
~ ~~ ~.: ~~ ~~
670R MUST CONT\IN A 177-0291
·("'hJp8 chanRed from a 611')-C to 6715-D
"'.("'hlps IIddt!d
~lJGJlJ
~[;J~~~
g~~~
0'-'
!
fillmlmlrm
0 fOJlll • b11')-D
\
--I
9-33
8~
~~
g~
~~
C~
1.29
1.28
U1
L26
1.25
6527-BJ/K
FIGURE
9-34
(KATAKANA VERSION)
6547-B5iK
(KATAKANA VERSION)
SUPERSEDED BY
6547-B6K
6547-86)(
(KATAKANA Vl:.RSION)
SUPERSI:.DES
6547-B5K
OJ OJ OJ
OJ OJ OJ
FIGURE
9-35
mOJO]
mDJm
FIGURE
9-36
9-34
D
D
FIGURE
9-37
6)2~-BX1IH/GIO
D
D
FIGURE
9-38
6325-BX2/CIO/SORT
I
/
9-35
i=I
L::J
L-l
377-0203
FIGURE
9-39
6325-CXl/H/no
FIGURE
9-40
6J25-CX1/GlO/SORT
NOTE
*(Aaterlak) danot•• 2 IC'. thu dtff.r fr ... the 6)25-BX2 PC Board.
9-36
9.5
2200 SYSTEM MEMORY OPTIONS
CPU
MODEL
WLI II
CPU DESCRIPTION
2200-Al
2200-AZ
2200-A3
2200-A4
2200-AS
2200-A6
2200-A7
2200-A8
177 2200 Al
A2
A3
A4
AS
A6
A7
A8
4K
8K
12K
16K
20K
24K
28K
32K
2200-Bl
2200-B2
2200-B3
2200-B4
2200-B5
2200-B6
2200-B7
2200-B8
Bl
B2
B3
B4
B5
B6
B7
B8
4K
8K
12K
16K
20K
24K
28K
32K
2200-Cl
2200-C2
2200-C3
2200-C4
2200-C5
2200-C6
2200-C7
2200-C8
Cl
C2
C3
C4
C5
C6
C7
C8
4K
8K
12K
16K
20K
24K
28K
32K
2200-S1
2200-S2
2200-S3
2200-S4
2200-S5
2200-S6
2200-S7
2200-S8
31
32
33
34
35
36
37
38
4K
8K
12K
16K
20K NOT AVAILABLE
24K
28K NOT AVAILABLE
32K
2200-Tl
2200-T2
2200-T3
2200-T4
2200-T5
2200- f6
2200-T7
2200-T8
Tl
4K
8K
12K
16K
20K NOT AVAILABLE
24K
28K NOT AVAILABLE
32K
T2
T3
T4
T5
T6
T7
T8
9-37
9.6
2200 SYSTEM RETROFITS
Wang Labs retrofit conversion numbers are assigned as follows:
CONVERSION DESCRIPTION
WLI STOCK 1/
2200-A TO 2200-B
200-0200
2200A TO 2200C
200-0200-AC
2200A TO 2200C CONVERSION W/KEYBD
200-0200-AK
2200B TO 2200C CONVERSION
200-0200-BC
2200B TO 2200C CONVERSION W/KEYBD
2200B
TO
C CONVERSION INTERNATIONAL
200-0200-BK
200-0200-IC
601 TO 2201
200-0201 6
701 TO 2201
200-0201 7
602 TO 2202
200-0202 6
702 TO 2202
200-0202 7
612 TO 2212
200-0212 6
712 TO 2212
200-0212
2216 TO 2216C UPDATE
200-0216 C
621 TO 2221
200-0221 6
721 TO 2221
200-0221 7
2224-2 TO 2224-3
200-0224 23
2224-2 TO 2224-4
200-0224 24
2224-3 TO 22-24-4
200-0224 34
2230-1 TO 2230-2
200-0230 1
2230-1 TO 2230-3
200-0230 2
2230-2 TO 2230-3
200-0230 3
630-1 TO 2230-1
200-0230 61
630-1 TO 2230-2
200-0230 62
630-1 TO 2230-3
200-0230 63
630-2 TO 2230-2
200-0230 64
630-2 TO 2230-3
200-0230 65
630-3 TO 2230-3
200-0230 66
730 ON 2230 FORMAT
200-0230
730-1 TO 2230-1
200-0230 71
730-1 TO 2230-2
200-0230 72
2230-3
200-0230 73
730-2 TO 2230-2
200-0230 74
730-2 TO 2230-3
730-3 TO 2230-3
200-0230 75
200-0230 76
730-1
TO
9-38
632A TO 2232A
200-0232 6A
732A TO 2232A
200-0232 7A
2234 TO 2234A
200-0234 A
640 / 740 TO 2240
200-0240
2240-1 TO 2240-2
200-0240 1
640-1 TO 2240-1
200-0240 61
640-1 TO 2240-2
200-0240 62
640-2 TO 2240-2
200-0240 63
640 / 740 ON 2240 FORMAT
200-0240 7
740-1 TO 2240-1
200-0240 71
740-1 TO 2240-2
200-0240 72
740-2 TO 2240-2
200-0240 73
641 TO 2241
200-0241 6
741 TO 2241
200-0241 7
2242 TO 2240-2
200-0242
2244 TO 2244A
200-0244 A
9.7
9.7.1
9.7.2
PERIPHERAL RETROFIT
IN~TRUCTIONS
600/700 PERIPHERAL CONVERSIONS TO 2200 PERIPHERALS
601/701 to 2201
No change in 601/701; add 2201 I/O controller card 6318 or 6368.
9.7.3
602/702 to 2202
No change in 602/702; add 2202 I/O controller card 6368.
9.7.4
612/712 to 2212
No change in 612/712; add 2212 I/O controller card 6368.
9.7.5
621/721 to 2221
Remove 6234 board from 621/721 and the cable.
Add a new cable
(WLI #220-0105) and place the Centronics fingerboard into connector 1.
Add a 2221 I/O controller card 6329 or 6379.
j
\
9-39
9.7.6
630/730 to 2230
Turn all switches on the 6295 ON.
Change the 6299 using ECN #3876.
Add 2230 I/O controller card 6375.
Add a 6327 board into the ROM
connectors.
Change the I/O cable:
END
WIRE FROM
Arnphenol
Pin 33
Pin 11
Fingerboard
Pin 13
Pin 10
WIRE TO
Change the PROMS on the 6298 according to the table included on
the 6298 schematic diagram in the Schematic Manual.
9.7.7
632/732 to 2232
No change in 632/732; add 2232 I/O controller card 6368.
9.7.8
640/740 to 2240
1.
Change PROMs on 6298 board.
2.
Change jumper on 6395 from 5MHz to 10MHz, and turn all switches ON.
3.
Change the I/O cable:
END
9.7.9
PART A
WIRE FROM
WIRE TO
Arnphenol
Pin 33
Pin 11
Fingerboard
Pin 13
Pin 10
2234 TO 2234A AND 2244 TO 2244A/CONVERSION
2234 TO 2234A CONVERSION KIT PART #200-0234A
REMOVE
ADD
2234 CONTROLLER
2234A CONTROLLER PIGGYBACK
9-40
PROM/RAM LOADING CILAIl:'r fOil. 2234.\
210-6449 A
Dg DD
OJ83
)11-
]17-
]77-
]77-
OUl,
02610
020'i
QIQS
rn
~
~
rn
B
§
EJ
§
0382
0]81
0380
OJ19
FIGURE 9-41
PART B
2244 TO 2244A CONVERSION KIT PART #200-0244A
REMOVE
ADD
2244 CONTROLLER
2244A CONTROLLER PIGGYBACK
PitOH/WI LQADlhC CHARt FOR 2244,\
210-6449-B
§ §
0)89
03811
BB
OJ91
039
]71-
]11-
377-
371-
0264
0264
OIQS
020S
0 0 0 0
§
0381
B § B
0386
FIGURE 9-42
9-41
0384
018S
9.8
9.3.1
MISCELLANEOUS 2200 SYSTEM RETROFITS
MODEL 2201 ON/OFF SWITCH-CONVERSION PROCEDURE
This explains the steps necessary to modify a 2201 so that it
~~y
be turned off if not in use when connected to an operating 2200 system.
The charge for this conversion is $50.00 plus normal service call charges.
This conversion can only be done on units that have the belly band attached
to the top cover.
PARTS REQUIRED:
WLI PART NUMBER:
Modified Band
458-0022
1 Switch
325-0021
2 Fast-on Terminals
654-0048
1 Silicon Diode
380-1001
2 18 inch Sections of 18 Gauge Wire
600-0009
PROCEDURE:
1)
Replace old band with modified band using existing hardware from old
band.
2)
Attach one 18" wire to pin 2 of the switch and the other wire to
pin 3.
3)
Insert the switch into the band so that the words ON/OFF are readable.
Bt.tLY BAND
,,,
~-_
..:
... _-------.,
:"'._-_......
_._~
FIGURE
9-43
SOLDER
FINGERBOARJ) l
P2
JOINT~
I
WHITE \.lIRE
___
WHITE WIRE /
DESOLDEltr.D
:
~
I
I
:
I
/'
FRO" PIN 1
I
ADDED
1
DIODE
L
4
1
RELA {
SOCKET
9-42
I
...l...
.J
RELAY
4)
5)
Desolder the white wire from pin 1 of the relay socket.
Solder the diode to pins 1 and 4 of the relay socket with the cathode
connecting pin 1.
6)
Solder one 18" wire to pin 1 of the relay socket and the other 18"
wire to the white wire that was removed in step 4; tape the connection.
9.8.2
CONVERSION FROM 2201 'fO 2212 AND 2232
(6368 PC ONLY)
To change a 6368 I/O board from a 2201 I/O to a 2212 or 2232 I/O
board, connect L13-12 to +0 volts.
(The board will work as a 2212 I/O
without the jumper but a number 1 will be plotted instead of a letter L.)
9.8.3
CONVERSION OF 2215 AND 2222 WITH 6367 PC BOARD
The 6317 is no longer being produced but will continue to be used.
The 6367 can be converted to be used as either a 2215 or a 2222
controller board.
See diagram below.
FIGURE
9-44
Jumper A in/B out
2222
Jlnnper B in/ A out - 2215
\
)
9-43
9-44
SECTION 9
NOTES:
9-45
1
1
1
1
, 1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
'-"'I
1
1
1
1
1
1
1
_I
1
1
1
1
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