Internet Data Sheet HYS[64/72]T[32/64/128]xx0HU

Internet Data Sheet HYS[64/72]T[32/64/128]xx0HU
December 2006
HYS64T32x00HU–[25F/2.5/3/3S/3.7/5]–B
HYS[64/72]T64x00HU–[25F/2.5/3/3S/3.7/5]–B
HYS[64/72]T128x20HU–[25F/2.5/3/3S/3.7/5]–B
240-Pin unbuffered DDR2 SDRAM Modules
DDR2 SDRAM
UDIMM SDRAM
RoHS Compliant
Internet Data Sheet
Rev. 1.3
Internet Data Sheet
HYS[64/72]T[32/64/128]xx0HU-[25F/2.5/3/3S/3.7/5]-B
Unbuffered DDR2 SDRAM Module
HYS64T32x00HU–[25F/2.5/3/3S/3.7/5]–B, HYS[64/72]T64x00HU–[25F/2.5/3/3S/3.7/5]–B,
HYS[64/72]T128x20HU–[25F/2.5/3/3S/3.7/5]–B
Revision History: 2006-12, Rev. 1.3
Page
Subjects (major changes since last revision)
All
Adapted internet edition
4, 5
Added WhiteBox Products for Speed Grade –3S and –3.7
45, 46
Added WhiteBox Products for Speed Grade –3S and –3.7 to IDD tables.
70, 74, 78, Updated SPD codes for –3S and –3.7 WhiteBox Products.
82
Previous Revision: 2006-09, Rev. 1.21
All
Qimonda update
Previous Revision: 2006-06, Rev. 1.2
43
SPD codes updated
Previous Revision: 2006-01, Rev. 1.1
3
Added PC2-6400-555 product types
42
Added IDD currents
24
Added Speed Grade bin for DDR2-800D
48
Added IDD Measurement Contions for DDR2-800D
55
Added SPD codes for PC2-6400-555 product types
Previous Revision: Rev. 1.0
We Listen to Your Comments
Any information within this document that you feel is wrong, unclear or missing at all?
Your feedback will help us to continuously improve the quality of this document.
Please send your proposal (including a reference to this document) to:
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qag_techdoc_rev400 / 3.2 QAG / 2006-08-07
03292006-6GMD-RSFT
2
Internet Data Sheet
HYS[64/72]T[32/64/128]xx0HU-[25F/2.5/3/3S/3.7/5]-B
Unbuffered DDR2 SDRAM Module
1
Overview
This chapter gives an overview of the 240-Pin unbuffered DDR2 SDRAM Modules product family and describes its main
characteristics.
1.1
Features
Feature list and performance tables
• 240-Pin PC2–6400, PC2–5300, PC2–4200 and
PC2–3200 DDR2 SDRAM memory modules.
• 32M × 64, 64M × 64, 64M × 72, 128M × 64 and 128M ×72
module organization and 32M × 16, 64M × 8 chip
organization
• Standard Double-Data-Rate-Two Synchronous DRAMs
(DDR2 SDRAM) with a single + 1.8 V (± 0.1 V) power
supply
• 256MB, 512MB and 1GB modules built with 512-Mbit
DDR2 SDRAMs in P-TFBGA-84 and P-TFBGA-60
chipsize packages
• All speed grades faster than DDR2–400 comply with
DDR2–400 timing specifications.
• Programmable CAS Latencies (3, 4 and 5),
Burst Length (8 & 4) and Burst Type
•
•
•
•
•
•
•
•
•
•
•
Auto Refresh (CBR) and Self Refresh
Programmable self refresh rate via EMRS2 setting
Programmable partial array refresh via EMRS2 settings
Average Refresh Period 7.8 µs at a TCASE lower than
85 °C, 3.9µs between 85 °C and 95 °C.
DCC enabling via EMRS2 setting
All inputs and outputs SSTL_1.8 compatible
Off-Chip Driver Impedance Adjustment (OCD) and
On-Die Termination (ODT)
Serial Presence Detect with E2PROM
UDIMM Dimensions (nominal):
30 mm high, 133.35 mm wide
Based on standard reference layouts Raw Card “C”,
“D”,”E”,”F” and “G“
RoHS compliant products1)
TABLE 1
Performance Table
Product Type Speed Code
–25F
–2.5
–3
–3S
–3.7
–5
Unit
Speed Grade
PC2–6400
5–5–5
PC2–6400
6–6–6
PC2–5300
4–4–4
PC2–5300
5–5–5
PC2–4200
4–4–4
PC2–3200
3–3–3
—
Max. Clock Frequency @CL6 fCK6
400
400
—
—
—
—
MHz
@CL5 fCK5
400
333
333
333
266
200
MHz
@CL4 fCK4
266
266
333
266
266
200
MHz
@CL3 fCK3
200
200
200
200
200
200
MHz
tRCD
tRP
tRAS
tRC
12.5
15
12
15
15
15
ns
12.5
15
12
15
15
15
ns
45
45
45
45
45
40
ns
57.5
60
57
60
60
55
ns
Min. RAS-CAS-Delay
Min. Row Precharge Time
Min. Row Active Time
Min. Row Cycle Time
1) RoHS Compliant Product: Restriction of the use of certain hazardous substances (RoHS) in electrical and electronic equipment as defined
in the directive 2002/95/EC issued by the European Parliament and of the Council of 27 January 2003. These substances include mercury,
lead, cadmium, hexavalent chromium, polybrominated biphenyls and polybrominated biphenyl ethers.
Rev. 1.3, 2006-12
03292006-6GMD-RSFT
3
Internet Data Sheet
HYS[64/72]T[32/64/128]xx0HU-[25F/2.5/3/3S/3.7/5]-B
Unbuffered DDR2 SDRAM Module
1.2
Description
The memory array is designed with 512-Mbit Double-DataRate-Two (DDR2) Synchronous DRAMs. Decoupling
capacitors are mounted on the PCB board. The DIMMs
feature serial presence detect based on a serial E2PROM
device using the 2-pin I2C protocol. The first 128 bytes are
programmed with configuration data and are write protected;
the second 128 bytes are available to the customer.
The Qimonda HYS[64/72]T[32/64/128]xx0HU-[25F/2.5/3/3S/3.7/5]-B
module family are unbuffered DIMM modules “UDIMMs” with
30 mm height based on DDR2 technology. DIMMs are
available as non-ECC modules in 32M × 64 (256 MB),
64M × 64 (512 MB), 128M × 64(1 GB) and as ECC modules
in 64M × 72 (512 MB), 128M × 72(1 GB) organization and
density, intended for mounting into 240-pin connector
sockets.
TABLE 2
Ordering Information for RoHS Compliant Products
Product Type1)
Compliance Code2)
Description
SDRAM
Technology
HYS64T32000HU–25F–B
256 MB 1R×16 PC2–6400U–555–12–C1
1 Rank, Non-ECC
512 Mbit (×16)
HYS64T64000HU–25F–B
512 MB 1R×8 PC2–6400U–555–12–D0
1 Rank, Non-ECC
512 Mbit (×8)
HYS72T64000HU–25F–B
512 MB 1R×8 PC2–6400E–555–12–F0
1 Rank, ECC
512 Mbit (×8)
HYS64T128020HU–25F–B
1 GB 2R×8 PC2–6400U–555–12–E0
2 Ranks, Non-ECC
512 Mbit (×8)
HYS72T128020HU–25F–B
1 GB 2R×8 PC2–6400E–555–12–G0
2 Ranks, ECC
512 Mbit (×8)
HYS64T32000HU–2.5–B
256 MB 1R×16 PC2–6400U–666–12–C1
1 Rank, Non-ECC
512 Mbit (×16)
HYS64T64000HU–2.5–B
512 MB 1R×8 PC2–6400U–666–12–D0
1 Rank, Non-ECC
512 Mbit (×8)
HYS72T64000HU–2.5–B
512 MB 1R×8 PC2–6400E–666–12–F0
1 Rank, ECC
512 Mbit (×8)
HYS64T128020HU–2.5–B
1 GB 2R×8 PC2–6400U–666–12–E0
2 Ranks, Non-ECC
512 Mbit (×8)
HYS72T128020HU–2.5–B
1 GB 2R×8 PC2–6400E–666–12–G0
2 Ranks, ECC
512 Mbit (×8)
HYS64T32000HU–3–B
256 MB 1R×16 PC2–5300U–444–12–C1
1 Rank, Non-ECC
512 Mbit (×16)
HYS64T64000HU–3–B
512 MB 1R×8 PC2–5300U–444–12–D0
1 Rank, Non-ECC
512 Mbit (×8)
HYS72T64000HU–3–B
512 MB 1R×8 PC2–5300E–444–12–F0
1 Rank, ECC
512 Mbit (×8)
HYS64T128020HU–3–B
1 GB 2R×8 PC2–5300U–444–12–E0
2 Ranks, Non-ECC
512 Mbit (×8)
HYS72T128020HU–3–B
1 GB 2R×8 PC2–5300E–444–12–G0
2 Ranks, ECC
512 Mbit (×8)
HYS64T32000HU–3S–B
256 MB 1R×16 PC2–5300U–555–12–C1
1 Rank, Non-ECC
512 Mbit (×16)
HYS64T32900HU–3S–B
256 MB 1R×16 PC2–5300U–555–12–C1
1 Rank, Non-ECC
512 Mbit (×16)
HYS64T64000HU–3S–B
512 MB 1R×8 PC2–5300U–555–12–D0
1 Rank, Non-ECC
512 Mbit (×8)
HYS64T64900HU–3S–B
512 MB 1R×8 PC2–5300U–555–12–D0
1 Rank, Non-ECC
512 Mbit (×8)
HYS72T64000HU–3S–B
512 MB 1R×8 PC2–5300E–555–12–F0
1 Rank, ECC
512 Mbit (×8)
HYS64T128020HU–3S–B
1 GB 2R×8 PC2–5300U–555–12–E0
2 Ranks, Non-ECC
512 Mbit (×8)
HYS64T128920HU–3S–B
1 GB 2R×8 PC2–5300U–555–12–E0
2 Ranks, Non-ECC
512 Mbit (×8)
HYS72T128020HU–3S–B
1 GB 2R×8 PC2–5300E–555–12–G0
2 Ranks, ECC
512 Mbit (×8)
PC2–6400
PC2–6400
PC2–5300
PC2–5300
Rev. 1.3, 2006-12
03292006-6GMD-RSFT
4
Internet Data Sheet
HYS[64/72]T[32/64/128]xx0HU-[25F/2.5/3/3S/3.7/5]-B
Unbuffered DDR2 SDRAM Module
Product Type1)
Compliance Code2)
Description
SDRAM
Technology
HYS64T32000HU–3.7–B
256 MB 1R×16 PC2–4200U–444–12–C1
1 Rank, Non-ECC
512 Mbit (×16)
HYS64T32900HU–3.7–B
256 MB 1R×16 PC2–4200U–444–12–C1
1 Rank, Non-ECC
512 Mbit (×16)
HYS64T64000HU–3.7–B
512 MB 1R×8 PC2–4200U–444–12–D0
1 Rank, Non-ECC
512 Mbit (×8)
HYS64T64900HU–3.7–B
512 MB 1R×8 PC2–4200U–444–12–D0
1 Rank, Non-ECC
512 Mbit (×8)
HYS72T64000HU–3.7–B
512 MB 1R×8 PC2–4200E–444–12–F0
1 Rank, ECC
512 Mbit (×8)
HYS64T128020HU–3.7–B
1 GB 2R×8 PC2–4200U–444–12–E0
2 Ranks, Non-ECC
512 Mbit (×8)
HYS64T128920HU–3.7–B
1 GB 2R×8 PC2–4200U–444–12–E0
2 Ranks, Non-ECC
512 Mbit (×8)
HYS72T128020HU–3.7–B
1 GB 2R×8 PC2–4200E–444–12–G0
2 Ranks, ECC
512 Mbit (×8)
HYS64T32000HU–5–B
256 MB 1R×16 PC2–3200U–333–12–C1
1 Rank, Non-ECC
512 Mbit (×16)
HYS64T64000HU–5–B
512 MB 1R×8 PC2–3200U–333–12–D0
1 Rank, Non-ECC
512 Mbit (×8)
HYS72T64000HU–5–B
512 MB 1R×8 PC2–3200E–333–12–F0
1 Rank, ECC
512 Mbit (×8)
HYS64T128020HU–5–B
1 GB 2R×8 PC2–3200U–333–12–E0
2 Ranks, Non-ECC
512 Mbit (×8)
HYS72T128020HU–5–B
1 GB 2R×8 PC2–3200E–333–12–G0
2 Ranks, ECC
512 Mbit (×8)
PC2–4200
PC2–3200
1) All Product Type numbers end with a place code, designating the silicon die revision. Example: HYS64T64000HU–3.7–B, indicating Rev.
“B” dies are used for DDR2 SDRAM components. For all Qimonda DDR2 module and component nomenclature see Chapter 6 of this data
sheet.
2) The Compliance Code is printed on the module label and describes the speed grade, for example “PC2–4200U–444–12–C1”, where
4200U means Unbuffered DIMM modules with 4.26 GB/sec Module Bandwidth and “444-12” means Column Address Strobe (CAS)
latency = 4, Row Column Delay (RCD) latency = 4 and Row Precharge (RP) latency = 4 using the latest JEDEC SPD Revision 1.2 and
produced on the Raw Card “C”.
Rev. 1.3, 2006-12
03292006-6GMD-RSFT
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Internet Data Sheet
HYS[64/72]T[32/64/128]xx0HU-[25F/2.5/3/3S/3.7/5]-B
Unbuffered DDR2 SDRAM Module
TABLE 3
Address Format
DIMM
Density
Module
Organization
Memory
Ranks
ECC/
Non-ECC
# of SDRAMs # of row/bank/column
bits
Raw
Card
256 MByte
32M × 64
1
Non-ECC
4
13/2/10
C
512 MByte
64M × 64
1
Non-ECC
8
14/2/10
D
512 MByte
72M × 64
1
ECC
9
14/2/10
F
1 GByte
128M × 64
2
Non-ECC
16
14/2/10
E
1 GByte
128M × 72
2
ECC
18
14/2/10
G
TABLE 4
Components on Modules
Product Type
1)
DRAM Components
1)
DRAM Density
DRAM Organisation Note2)
HYS64T32000HU
HYS64T32900HU
HYB18T512160BF
512 Mbit
32M × 16
HYS64T64000HU
HYS64T64900HU
HYB18T512800BF
512 Mbit
64M × 8
HYS72T64000HU
HYB18T512800BF
512 Mbit
64M × 8
HYS64T128020HU
HYS64T128920HU
HYB18T512800BF
512 Mbit
64M × 8
HYS72T128020HU
HYB18T512800BF
512 Mbit
64M × 8
1) Green Product
2) For a detailed description of all functionalities of the DRAM components on these modules see the component data sheet.
Rev. 1.3, 2006-12
03292006-6GMD-RSFT
6
Internet Data Sheet
HYS[64/72]T[32/64/128]xx0HU-[25F/2.5/3/3S/3.7/5]-B
Unbuffered DDR2 SDRAM Module
2
Pin Configuration
This chapter describes the Pin Configuration.
2.1
Pin Configuration
This chapter contains the Pin Configuration tables.
The pin configuration of the Unbuffered DDR2 SDRAM DIMM
is listed by function in Table 5 (240 pins). The abbreviations
used in columns Pin and Buffer Type are explained in Table 6
and Table 7 respectively. The pin numbering is depicted in
Figure 1 for non-ECC modules (×64) and Figure 2 for ECC
modules (×72).
TABLE 5
Pin Configuration of UDIMM
Ball No.
Name
Pin
Type
Buffer
Type
Function
Clock Signals 2:0, Complement Clock Signals 2:0
Clock Signals
185
CK0
I
SSTL
137
CK1
I
SSTL
220
CK2
I
SSTL
186
CK0
I
SSTL
138
CK1
I
SSTL
221
CK2
I
SSTL
52
CKE0
I
SSTL
171
CKE1
I
SSTL
NC
NC
—
Not Connected
Note: 1 Rank module
193
S0#
I
SSTL
76
S1#
I
SSTL
Chip Select Rank 1:0
Note: 2 Ranks module
NC
NC
—
192
RAS
I
SSTL
Row Address Strobe
74
CAS
I
SSTL
Column Address Strobe
73
WE
I
SSTL
Write Enable
71
BA0
I
SSTL
Bank Address Bus 1:0
190
BA1
I
SSTL
54
BA2
I
SSTL
Bank Address Bus 2
Greater than 512Mb DDR2 SDRAMS
NC
NC
—
Not Connected
Less than 1Gb DDR2 SDRAMS
Clock Enable Rank 1:0
Note: 2 Ranks module
Control Signals
Not Connected
Note: 1 Rank module
Address Signals
Rev. 1.3, 2006-12
03292006-6GMD-RSFT
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Internet Data Sheet
HYS[64/72]T[32/64/128]xx0HU-[25F/2.5/3/3S/3.7/5]-B
Unbuffered DDR2 SDRAM Module
Ball No.
Name
Pin
Type
Buffer
Type
Function
188
A0
I
SSTL
Address Bus 12:0
183
A1
I
SSTL
63
A2
I
SSTL
182
A3
I
SSTL
61
A4
I
SSTL
60
A5
I
SSTL
180
A6
I
SSTL
58
A7
I
SSTL
179
A8
I
SSTL
177
A9
I
SSTL
70
A10
I
SSTL
AP
I
SSTL
57
A11
I
SSTL
176
A12
I
SSTL
196
A13
I
SSTL
Address Signal 13
Note: 1 Gbit based module and 512M ×4/×8
NC
NC
—
Not Connected
Note: Module based on 1 Gbit ×16
Module based on 512 Mbit ×16 or smaller
A14
I
SSTL
Address Signal 14
Note: Modules based on 2 Gbit
NC
NC
—
Not Connected
Note: Modules based on 1 Gbit or smaller
3
DQ0
I/O
SSTL
4
DQ1
I/O
SSTL
Data Bus 63:0
Data Input/Output pins
9
DQ2
I/O
SSTL
10
DQ3
I/O
SSTL
122
DQ4
I/O
SSTL
123
DQ5
I/O
SSTL
128
DQ6
I/O
SSTL
129
DQ7
I/O
SSTL
174
Data Signals
Rev. 1.3, 2006-12
03292006-6GMD-RSFT
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Internet Data Sheet
HYS[64/72]T[32/64/128]xx0HU-[25F/2.5/3/3S/3.7/5]-B
Unbuffered DDR2 SDRAM Module
Ball No.
Name
Pin
Type
Buffer
Type
Function
12
DQ8
I/O
SSTL
13
DQ9
I/O
SSTL
Data Bus 63:0
Data Input/Output pins
21
DQ10
I/O
SSTL
22
DQ11
I/O
SSTL
131
DQ12
I/O
SSTL
132
DQ13
I/O
SSTL
140
DQ14
I/O
SSTL
141
DQ15
I/O
SSTL
24
DQ16
I/O
SSTL
25
DQ17
I/O
SSTL
30
DQ18
I/O
SSTL
31
DQ19
I/O
SSTL
143
DQ20
I/O
SSTL
144
DQ21
I/O
SSTL
149
DQ22
I/O
SSTL
150
DQ23
I/O
SSTL
33
DQ24
I/O
SSTL
34
DQ25
I/O
SSTL
39
DQ26
I/O
SSTL
40
DQ27
I/O
SSTL
152
DQ28
I/O
SSTL
153
DQ29
I/O
SSTL
158
DQ30
I/O
SSTL
159
DQ31
I/O
SSTL
80
DQ32
I/O
SSTL
81
DQ33
I/O
SSTL
86
DQ34
I/O
SSTL
87
DQ35
I/O
SSTL
199
DQ36
I/O
SSTL
200
DQ37
I/O
SSTL
205
DQ38
I/O
SSTL
206
DQ39
I/O
SSTL
89
DQ40
I/O
SSTL
90
DQ41
I/O
SSTL
95
DQ42
I/O
SSTL
96
DQ43
I/O
SSTL
208
DQ44
I/O
SSTL
209
DQ45
I/O
SSTL
214
DQ46
I/O
SSTL
215
DQ47
I/O
SSTL
Rev. 1.3, 2006-12
03292006-6GMD-RSFT
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Internet Data Sheet
HYS[64/72]T[32/64/128]xx0HU-[25F/2.5/3/3S/3.7/5]-B
Unbuffered DDR2 SDRAM Module
Ball No.
Name
Pin
Type
Buffer
Type
Function
98
DQ48
I/O
SSTL
99
DQ49
I/O
SSTL
Data Bus 63:0
Data Input/Output pins
107
DQ50
I/O
SSTL
108
DQ51
I/O
SSTL
217
DQ52
I/O
SSTL
218
DQ53
I/O
SSTL
226
DQ54
I/O
SSTL
227
DQ55
I/O
SSTL
110
DQ56
I/O
SSTL
111
DQ57
I/O
SSTL
116
DQ58
I/O
SSTL
117
DQ59
I/O
SSTL
229
DQ60
I/O
SSTL
230
DQ61
I/O
SSTL
235
DQ62
I/O
SSTL
236
DQ63
I/O
SSTL
CB0
I/O
SSTL
Check Bit 0
Note: ECC type module only
NC
NC
—
Not Connected
Note: ECC type module only
CB1
I/O
SSTL
Check Bit 1
Note: ECC type module only
NC
NC
—
Not Connected
Note: ECC type module only
CB2
I/O
SSTL
Check Bit 2
Note: ECC type module only
NC
NC
—
Not Connected
Note: ECC type module only
CB3
I/O
SSTL
Check Bit 3
Note: ECC type module only
NC
NC
—
Not Connected
Note: ECC type module only
CB4
I/O
SSTL
Check Bit 4
Note: ECC type module only
NC
NC
—
Not Connected
Note: ECC type module only
CB5
I/O
SSTL
Check Bit 5
Note: ECC type module only
NC
NC
—
Not Connected
Note: ECC type module only
Check Bit Signals
42
43
48
49
161
162
Rev. 1.3, 2006-12
03292006-6GMD-RSFT
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Internet Data Sheet
HYS[64/72]T[32/64/128]xx0HU-[25F/2.5/3/3S/3.7/5]-B
Unbuffered DDR2 SDRAM Module
Ball No.
Name
Pin
Type
Buffer
Type
Function
167
CB6
I/O
SSTL
Check Bit 6
Note: ECC type module only
NC
NC
—
Not Connected
Note: ECC type module only
CB7
I/O
SSTL
Check Bit 7
Note: ECC type module only
NC
NC
—
Not Connected
Note: Non-ECC module
7
DQS0
I/O
SSTL
Data Strobe Bus 8:0
16
DQS1
I/O
SSTL
28
DQS2
I/O
SSTL
37
DQS3
I/O
SSTL
84
DQS4
I/O
SSTL
93
DQS5
I/O
SSTL
105
DQS6
I/O
SSTL
114
DQS7
I/O
SSTL
46
DQS8
I/O
SSTL
6
DQS0
I/O
SSTL
168
Data Strobe Bus
Complement Data Strobe Bus 8:0
15
DQS1
I/O
SSTL
27
DQS2
I/O
SSTL
36
DQS3
I/O
SSTL
83
DQS4
I/O
SSTL
92
DQS5
I/O
SSTL
104
DQS6
I/O
SSTL
113
DQS7
I/O
SSTL
45
DQS8
I/O
SSTL
125
DM0
I
SSTL
134
DM1
I
SSTL
146
DM2
I
SSTL
155
DM3
I
SSTL
202
DM4
I
SSTL
211
DM5
I
SSTL
223
DM6
I
SSTL
232
DM7
I
SSTL
164
DM8
I
SSTL
120
SCL
I
CMOS
Serial Bus Clock
119
SDA
I/O
OD
Serial Bus Data
Data Mask Signals
Data Mask Bus 8:0
EEPROM
Rev. 1.3, 2006-12
03292006-6GMD-RSFT
11
Internet Data Sheet
HYS[64/72]T[32/64/128]xx0HU-[25F/2.5/3/3S/3.7/5]-B
Unbuffered DDR2 SDRAM Module
Ball No.
Name
Pin
Type
Buffer
Type
Function
239
SA0
I
CMOS
Serial Address Select Bus 2:0
240
SA1
I
CMOS
101
SA2
I
CMOS
Power Supplies
VREF
AI
VDDSPD PWR
VDDQ
PWR
—
I/O Reference Voltage
—
EEPROM Power Supply
—
I/O Driver Power Supply
53,59,64,67,69,,
172,178,184,187,
189,197
VDD
PWR
—
Power Supply
2,5,8,11,14,17,,
20,23,26,29,32,
35,38,41,44,47,,
50,65,66,79,82,
85,88,91,94,97,,
100,103,106,
109,112,115,118,
121,124,127,,
130,133,136,139,
142,145,148,,
151,154,157,160,
163,166,169,
198,201,204,207,
210,213,216,,
219,222,225,228,
231,234,237
VSS
GND
—
Ground Plane
195
ODT0
I
SSTL
On-Die Termination Control 0
77
ODT1
I
SSTL
On-Die Termination Control 1
Note: 2 Rank modules
NC
NC
—
Not Connected
Note: 1 Rank modules
18,19,55,68,102,1 NC
26,135,147,
156,165,173,203,
212, 224,233
NC
—
Not connected
Note: Pins not connected on Qimonda UDIMMs
1
238
51,56,62,72,75,,
78,170,175,181,,
191,194
Other Pins
Rev. 1.3, 2006-12
03292006-6GMD-RSFT
12
Internet Data Sheet
HYS[64/72]T[32/64/128]xx0HU-[25F/2.5/3/3S/3.7/5]-B
Unbuffered DDR2 SDRAM Module
TABLE 6
Abbreviations for Pin Type
Abbreviation
Description
I
Standard input-only pin. Digital levels.
O
Output. Digital levels.
I/O
I/O is a bidirectional input/output signal.
AI
Input. Analog levels.
PWR
Power
GND
Ground
NC
Not Connected
TABLE 7
Abbreviations for Buffer Type
Abbreviation
Description
SSTL
Serial Stub Terminated Logic (SSTL_18)
LV-CMOS
Low Voltage CMOS
CMOS
CMOS Levels
OD
Open Drain. The corresponding pin has 2 operational states, active low and tri-state,
and allows multiple devices to share as a wire-OR.
Rev. 1.3, 2006-12
03292006-6GMD-RSFT
13
Internet Data Sheet
HYS[64/72]T[32/64/128]xx0HU-[25F/2.5/3/3S/3.7/5]-B
Unbuffered DDR2 SDRAM Module
FIGURE 1
Pin Configuration UDIMM ×64 (240 Pin)
95() 3LQ
'4
3LQ
966 3LQ
'46
3LQ
'4
3LQ
966 3LQ
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Rev. 1.3, 2006-12
03292006-6GMD-RSFT
3LQ
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6$
033
7
Internet Data Sheet
HYS[64/72]T[32/64/128]xx0HU-[25F/2.5/3/3S/3.7/5]-B
Unbuffered DDR2 SDRAM Module
FIGURE 2
Pin Configuration UDIMM ×72 (240 Pin)
95() 3LQ
'4
3LQ
966 3LQ
'46
3LQ
'4
3LQ
966 3LQ
'4
3LQ
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3LQ
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Rev. 1.3, 2006-12
03292006-6GMD-RSFT
3LQ
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6$
033
7
Internet Data Sheet
HYS[64/72]T[32/64/128]xx0HU-[25F/2.5/3/3S/3.7/5]-B
Unbuffered DDR2 SDRAM Module
3
Electrical Characteristics
This chapter describes the Electrical Characteristics.
3.1
Absolute Maximum Ratings
Caution is needed not to exceed absolute maximum ratings of the DRAM device listed in Table 8 at any time.
TABLE 8
Absolute Maximum Ratings
Symbol
VDD
VDDQ
VDDL
VIN, VOUT
TSTG
Parameter
Rating
Unit
Note
Min.
Max.
Voltage on VDD pin relative to VSS
–1.0
+2.3
V
1)
Voltage on VDDQ pin relative to VSS
–0.5
+2.3
V
1)2)
Voltage on VDDL pin relative to VSS
–0.5
+2.3
V
1)2)
Voltage on any pin relative to VSS
–0.5
+2.3
V
1)
°C
1)2)
Storage Temperature
–55
+100
1) When VDD and VDDQ and VDDL are less than 500 mV; VREF may be equal to or less than 300 mV.
2) Storage Temperature is the case surface temperature on the center/top side of the DRAM.
Attention: Stresses greater than those listed under “Absolute Maximum Ratings” may cause permanent damage to
the device. This is a stress rating only and functional operation of the device at these or any other
conditions above those indicated in the operational sections of this specification is not implied. Exposure
to absolute maximum rating conditions for extended periods may affect reliability.
TABLE 9
DRAM Component Operating Temperature Range
Symbol
TOPER
Parameter
Rating
Operating Temperature
Min.
Max.
0
95
Unit
Note
°C
1)2)3)4)
1) Operating Temperature is the case surface temperature on the center / top side of the DRAM.
2) The operating temperature range are the temperatures where all DRAM specification will be supported. During operation, the DRAM case
temperature must be maintained between 0 - 95 °C under all other specification parameters.
3) Above 85 °C the Auto-Refresh command interval has to be reduced to tREFI= 3.9 µs
4) When operating this product in the 85 °C to 95 °C TCASE temperature range, the High Temperature Self Refresh has to be enabled by
setting EMR(2) bit A7 to “1”. When the High Temperature Self Refresh is enabled there is an increase of IDD6 by approximately 50%
Rev. 1.3, 2006-12
03292006-6GMD-RSFT
16
Internet Data Sheet
HYS[64/72]T[32/64/128]xx0HU-[25F/2.5/3/3S/3.7/5]-B
Unbuffered DDR2 SDRAM Module
3.2
DC Operating Conditions
This chapter contains the DC Operating Conditions tables.
TABLE 10
Operating Conditions
Parameter
Symbol
Values
Unit
Min.
Max.
0
+65
°C
0
+95
°C
Storage Temperature
TOPR
TCASE
TSTG
– 50
+100
°C
Barometric Pressure (operating & storage)
PBar
+69
+105
kPa
Operating Humidity (relative)
HOPR
10
90
%
Operating temperature (ambient)
DRAM Case Temperature
Note
1)2)3)4)
5)
1)
2)
3)
4)
DRAM Component Case Temperature is the surface temperature in the center on the top side of any of the DRAMs.
Within the DRAM Component Case Temperature Range all DRAM specifications will be supported
Above 85 °C DRAM Case Temperature the Auto-Refresh command interval has to be reduced to tREFI = 3.9 µs
When operating this product in the 85 °C to 95 °C TCASE temperature range, the High Temperature Self Refresh has to be enabled by
setting EMR(2) bit A7 to “1”. When the High Temperature Self Refresh is enabled there is an increase of IDD6 by approximately 50%.
5) Up to 3000 m.
TABLE 11
Supply Voltage Levels and DC Operating Conditions
Parameter
Device Supply Voltage
Output Supply Voltage
Input Reference Voltage
SPD Supply Voltage
DC Input Logic High
DC Input Logic Low
Symbol
VDD
VDDQ
VREF
VDDSPD
VIH(DC)
VIL (DC)
IL
Values
Unit
Min.
Typ.
Max.
1.7
1.8
1.9
V
1.7
1.8
1.9
V
1)
0.49 × VDDQ
0.5 × VDDQ
0.51 × VDDQ
V
2)
1.7
—
3.6
V
VREF + 0.125
—
– 0.30
—
VDDQ + 0.3
VREF – 0.125
V
V
In / Output Leakage Current
–5
—
5
µA
1) Under all conditions, VDDQ must be less than or equal to VDD
2) Peak to peak AC noise on VREF may not exceed ± 2% VREF (DC).VREF is also expected to track noise in VDDQ.
3) Input voltage for any connector pin under test of 0 V ≤ VIN ≤ VDDQ + 0.3 V; all other pins at 0 V. Current is per pin
Rev. 1.3, 2006-12
03292006-6GMD-RSFT
Note
17
3)
Internet Data Sheet
HYS[64/72]T[32/64/128]xx0HU-[25F/2.5/3/3S/3.7/5]-B
Unbuffered DDR2 SDRAM Module
3.3
Timing Characteristics
This chapter describes the AC Characteristics.
3.3.1
Speed Grade Definitions
All Speed grades faster than DDR2-DDR400B comply with DDR2-DDR400B timing specifications(tCK = 5ns with tRAS = 40ns).
Speed Grade Definition for: DDR2–800(Table 12), DDR2–667(Table 13), DDR2–533C(Table 14) and DDR2–400B(Table 15)
TABLE 12
Speed Grade Definition Speed Bins for DDR2–800
Speed Grade
DDR2–800D
DDR2–800E
QAG Sort Name
–25F
–2.5
CAS-RCD-RP latencies
5–5–5
6–6–6
Parameter
Clock Frequency
@ CL = 3
@ CL = 4
@ CL = 5
@ CL = 6
Row Active Time
Row Cycle Time
RAS-CAS-Delay
Row Precharge Time
Unit
Note
tCK
Symbol
Min.
Max.
Min.
Max.
—
tCK
tCK
tCK
tCK
tRAS
tRC
tRCD
tRP
5
8
5
8
ns
1)2)3)4)
3.75
8
3.75
8
ns
1)2)3)4)
2.5
8
3
8
ns
1)2)3)4)
2.5
8
2.5
8
ns
1)2)3)4)
45
70000
45
70000
ns
1)2)3)4)5)
57.5
—
60
—
ns
1)2)3)4)
12.5
—
15
—
ns
1)2)3)4)
12.5
—
15
—
ns
1)2)3)4)
1) Timings are guaranteed with CK/CK differential Slew Rate of 2.0 V/ns. For DQS signals timings are guaranteed with a differential Slew
Rate of 2.0 V/ns in differential strobe mode and a Slew Rate of 1 V/ns in single ended mode. Timings are further guaranteed for normal
OCD drive strength (EMRS(1) A1 = 0)
2) The CK/CK input reference level (for timing reference to CK/CK) is the point at which CK and CK cross. The DQS / DQS, RDQS / RDQS,
input reference level is the crosspoint when in differential strobe mode.
3) Inputs are not recognized as valid until VREF stabilizes. During the period before VREF stabilizes, CKE = 0.2 x VDDQ is recognized as low.
4) The output timing reference voltage level is VTT.
5) tRAS.MAX is calculated from the maximum amount of time a DDR2 device can operate without a refresh command which is equal to 9 x tREFI.
TABLE 13
Speed Grade Definition Speed Bins for DDR2–667
Speed Grade
DDR2–667C
DDR2–667D
QAG Sort Name
–3
–3S
CAS-RCD-RP latencies
4–4–4
5–5–5
Parameter
Clock Frequency
@ CL = 3
@ CL = 4
@ CL = 5
Rev. 1.3, 2006-12
03292006-6GMD-RSFT
Unit
Note
tCK
Symbol
Min.
Max.
Min.
Max.
—
tCK
tCK
tCK
5
8
5
8
ns
1)2)3)4)
3
8
3.75
8
ns
1)2)3)4)
3
8
3
8
ns
1)2)3)4)
18
Internet Data Sheet
HYS[64/72]T[32/64/128]xx0HU-[25F/2.5/3/3S/3.7/5]-B
Unbuffered DDR2 SDRAM Module
Speed Grade
DDR2–667C
DDR2–667D
QAG Sort Name
–3
–3S
CAS-RCD-RP latencies
4–4–4
5–5–5
Unit
Note
tCK
Parameter
Symbol
Min.
Max.
Min.
Max.
—
Row Active Time
tRAS
tRC
tRCD
tRP
45
70000
45
70000
ns
1)2)3)4)5)
57
—
60
—
ns
1)2)3)4)
12
—
15
—
ns
1)2)3)4)
12
—
15
—
ns
1)2)3)4)
Row Cycle Time
RAS-CAS-Delay
Row Precharge Time
1) Timings are guaranteed with CK/CK differential Slew Rate of 2.0 V/ns. For DQS signals timings are guaranteed with a differential Slew
Rate of 2.0 V/ns in differential strobe mode and a Slew Rate of 1 V/ns in single ended mode. Timings are further guaranteed for normal
OCD drive strength (EMRS(1) A1 = 0) .
2) The CK/CK input reference level (for timing reference to CK/CK) is the point at which CK and CK cross. The DQS / DQS, RDQS / RDQS,
input reference level is the crosspoint when in differential strobe mode
3) Inputs are not recognized as valid until VREF stabilizes. During the period before VREF stabilizes, CKE = 0.2 x VDDQ is recognized as low.
4) The output timing reference voltage level is VTT.
5) tRAS.MAX is calculated from the maximum amount of time a DDR2 device can operate without a refresh command which is equal to 9 x tREFI.
TABLE 14
Speed Grade Definition Speed Bins for DDR2–533C
Speed Grade
DDR2–533C
QAG Sort Name
–3.7
CAS-RCD-RP latencies
4–4–4
Parameter
Clock Frequency
@ CL = 3
@ CL = 4
@ CL = 5
Row Active Time
Row Cycle Time
RAS-CAS-Delay
Row Precharge Time
Unit
Note
tCK
Symbol
Min.
Max.
—
tCK
tCK
tCK
tRAS
tRC
tRCD
tRP
5
8
ns
1)2)3)4)
3.75
8
ns
1)2)3)4)
3.75
8
ns
1)2)3)4)
45
70000
ns
1)2)3)4)5)
60
—
ns
1)2)3)4)
15
—
ns
1)2)3)4)
15
—
ns
1)2)3)4)
1) Timings are guaranteed with CK/CK differential Slew Rate of 2.0 V/ns. For DQS signals timings are guaranteed with a differential Slew
Rate of 2.0 V/ns in differential strobe mode and a Slew Rate of 1 V/ns in single ended mode.Timings are further guaranteed for normal
OCD drive strength (EMRS(1) A1 = 0)
2) The CK/CK input reference level (for timing reference to CK/CK) is the point at which CK and CK cross. The DQS / DQS, RDQS / RDQS,
input reference level is the crosspoint when in differential strobe mode.
3) Inputs are not recognized as valid until VREF stabilizes. During the period before VREF stabilizes, CKE = 0.2 x VDDQ is recognized as low.
4) The output timing reference voltage level is VTT.
5) tRAS.MAX is calculated from the maximum amount of time a DDR2 device can operate without a refresh command which is equal to 9 x tREFI.
Rev. 1.3, 2006-12
03292006-6GMD-RSFT
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Unbuffered DDR2 SDRAM Module
TABLE 15
Speed Grade Definition Speed Bins for DDR2-400B
Speed Grade
DDR2–400B
QAG Sort Name
–5
CAS-RCD-RP latencies
3–3–3
Parameter
Clock Frequency
@ CL = 3
@ CL = 4
@ CL = 5
Row Active Time
Row Cycle Time
RAS-CAS-Delay
Row Precharge Time
Unit
Note
tCK
Symbol
Min.
Max.
—
tCK
tCK
tCK
tRAS
tRC
tRCD
tRP
5
8
ns
1)2)3)4)
5
8
ns
1)2)3)4)
5
8
ns
1)2)3)4)
40
70000
ns
1)2)3)4)5)
55
—
ns
1)2)3)4)
15
—
ns
1)2)3)4)
15
—
ns
1)2)3)4)
1) Timings are guaranteed with CK/CK differential Slew Rate of 2.0 V/ns. For DQS signals timings are guaranteed with a differential Slew
Rate of 2.0 V/ns in differential strobe mode and a Slew Rate of 1 V/ns in single ended mode. Timings are further guaranteed for normal
OCD drive strength (EMRS(1) A1 = 0) .
2) The CK/CK input reference level (for timing reference to CK/CK) is the point at which CK and CK cross. The DQS / DQS, RDQS / RDQS,
input reference level is the crosspoint when in differential strobe mode
3) Inputs are not recognized as valid until VREF stabilizes. During the period before VREF stabilizes, CKE = 0.2 x VDDQ is recognized as low.
4) The output timing reference voltage level is VTT.
5) tRAS.MAX is calculated from the maximum amount of time a DDR2 device can operate without a refresh command which is equal to 9 x tREFI.
3.3.2
Component AC Timing Parameters
Timing Parameters for: DDR2–800(Table 16), DDR2–667(Table 17), DDR2–533C(Table 18) and DDR2–400B(Table 19)
TABLE 16
DRAM Component Timing Parameter by Speed Grade - DDR2–800
Parameter
Symbol
DDR2–800
Unit
Note
1)2)3)4)5)6)7)8)
Min.
Max.
tAC
tCCD
tCH.AVG
tCK.AVG
tCKE
–400
+400
ps
2
—
nCK
0.48
0.52
tCK.AVG
10)11)
2500
8000
ps
10)11)
3
—
nCK
12)
tCL.AVG
Auto-Precharge write recovery + precharge time tDAL
Minimum time clocks remain ON after CKE
tDELAY
0.48
0.52
tCK.AVG
10)11)
WR + tnRP
—
nCK
13)14)
tIS + tCK .AVG +
tIH
––
ns
125
––
ps
DQ output access time from CK / CK
CAS to CAS command delay
Average clock high pulse width
Average clock period
CKE minimum pulse width ( high and low pulse
width)
Average clock low pulse width
asynchronously drops LOW
DQ and DM input hold time
Rev. 1.3, 2006-12
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tDH.BASE
20
9)
19)20)15)
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Unbuffered DDR2 SDRAM Module
Parameter
Symbol
DDR2–800
Unit
Note
1)2)3)4)5)6)7)8)
tDIPW
DQS output access time from CK / CK
tDQSCK
DQS input high pulse width
tDQSH
DQS input low pulse width
tDQSL
DQS-DQ skew for DQS & associated DQ signals tDQSQ
DQS latching rising transition to associated clock tDQSS
DQ and DM input pulse width for each input
Min.
Max.
0.35
—
tCK.AVG
–350
+350
ps
0.35
—
0.35
—
tCK.AVG
tCK.AVG
—
200
ps
16)
17)
9)
– 0.25
+ 0.25
tCK.AVG
tDS.BASE
tDSH
tDSS
tHP
50
––
ps
18)19)20)
17)
tHZ
Address and control input hold time
tIH.BASE
Control & address input pulse width for each input tIPW
Address and control input setup time
tIS.BASE
DQ low impedance time from CK/CK
tLZ.DQ
DQS/DQS low-impedance time from CK / CK
tLZ.DQS
MRS command to ODT update delay
tMOD
Mode register set command cycle time
tMRD
OCD drive mode output delay
tOIT
DQ/DQS output hold time from DQS
tQH
DQ hold skew factor
tQHS
Read preamble
tRPRE
Read postamble
tRPST
Internal Read to Precharge command delay
tRTP
Write preamble
tWPRE
Write postamble
tWPST
Write recovery time
tWR
Internal write to read command delay
tWTR
Exit power down to read command
tXARD
Exit active power-down mode to read command tXARDS
edges
DQ and DM input setup time
DQS falling edge hold time from CK
DQS falling edge to CK setup time
CK half pulse width
Data-out high-impedance time from CK / CK
0.2
—
0.2
—
tCK.AVG
tCK.AVG
Min(tCH.ABS,
tCL.ABS)
__
ps
21)
—
tAC.MAX
ps
9)22)
250
—
ps
23)25)
0.6
—
tCK.AVG
175
—
ps
24)25)
2 x tAC.MIN
tAC.MAX
ps
9)22)
tAC.MIN
tAC.MAX
ps
9)22)
0
12
ns
31)
2
—
nCK
0
12
ns
31)
tHP – tQHS
—
ps
26)
—
300
ps
27)
0.9
1.1
28)29)
0.4
0.6
tCK.AVG
tCK.AVG
7.5
—
ns
31)
0.35
—
0.4
0.6
tCK.AVG
tCK.AVG
15
—
ns
31)
7.5
—
ns
31)32)
2
—
nCK
8 – AL
—
nCK
17)
28)30)
(slow exit, lower power)
Exit precharge power-down to any valid
command (other than NOP or Deselect)
tXP
2
—
nCK
Exit self-refresh to a non-read command
tRFC +10
—
ns
Exit self-refresh to read command
tXSNR
tXSRD
200
—
nCK
Write command to DQS associated clock edges
WL
RL – 1
1) For details and notes see the relevant Qimonda component data sheet
2) VDDQ = 1.8 V ± 0.1V; VDD = 1.8 V ± 0.1 V. See notes 5)6)7)8)
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03292006-6GMD-RSFT
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nCK
31)
Internet Data Sheet
HYS[64/72]T[32/64/128]xx0HU-[25F/2.5/3/3S/3.7/5]-B
Unbuffered DDR2 SDRAM Module
3) Timing that is not specified is illegal and after such an event, in order to guarantee proper operation, the DRAM must be powered down
and then restarted through the specified initialization sequence before normal operation can continue.
4) Timings are guaranteed with CK/CK differential Slew Rate of 2.0 V/ns. For DQS signals timings are guaranteed with a differential Slew
Rate of 2.0 V/ns in differential strobe mode and a Slew Rate of 1 V/ns in single ended mode.
5) The CK / CK input reference level (for timing reference to CK / CK) is the point at which CK and CK cross. The DQS / DQS, RDQS / RDQS,
input reference level is the crosspoint when in differential strobe mode.
6) Inputs are not recognized as valid until VREF stabilizes. During the period before VREF stabilizes, CKE = 0.2 x VDDQ is recognized as low.
7) The output timing reference voltage level is VTT.
8) New units, ‘tCK.AVG‘ and ‘nCK‘, are introduced in DDR2–667 and DDR2–800. Unit ‘tCK.AVG‘ represents the actual tCK.AVG of the input clock
under operation. Unit ‘nCK‘ represents one clock cycle of the input clock, counting the actual clock edges. Note that in DDR2–400 and
DDR2–533, ‘tCK‘ is used for both concepts. Example: tXP = 2 [nCK] means; if Power Down exit is registered at Tm, an Active command
may be registered at Tm + 2, even if (Tm + 2 - Tm) is 2 x tCK.AVG + tERR.2PER(Min).
9) When the device is operated with input clock jitter, this parameter needs to be derated by the actual tERR(6-10per) of the input clock. (output
deratings are relative to the SDRAM input clock.) For example, if the measured jitter into a DDR2–667 SDRAM has tERR(6-10PER).MIN = – 272
ps and tERR(6- 10PER).MAX = + 293 ps, then tDQSCK.MIN(DERATED) = tDQSCK.MIN – tERR(6-10PER).MAX = – 400 ps – 293 ps = – 693 ps and
tDQSCK.MAX(DERATED) = tDQSCK.MAX – tERR(6-10PER).MIN = 400 ps + 272 ps = + 672 ps. Similarly, tLZ.DQ for DDR2–667 derates to tLZ.DQ.MIN(DERATED)
= - 900 ps – 293 ps = – 1193 ps and tLZ.DQ.MAX(DERATED) = 450 ps + 272 ps = + 722 ps. (Caution on the MIN/MAX usage!)
10) Input clock jitter spec parameter. These parameters are referred to as 'input clock jitter spec parameters' and these parameters apply to
DDR2–667 and DDR2–800 only. The jitter specified is a random jitter meeting a Gaussian distribution.
11) These parameters are specified per their average values, however it is understood that the relationship between the average timing and
the absolute instantaneous timing holds all the times (min. and max of SPEC values are to be used for calculations ).
12) tCKE.MIN of 3 clocks means CKE must be registered on three consecutive positive clock edges. CKE must remain at the valid input level the
entire time it takes to achieve the 3 clocks of registration. Thus, after any CKE transition, CKE may not transition from its valid level during
the time period of tIS + 2 x tCK + tIH.
13) DAL = WR + RU{tRP(ns) / tCK(ns)}, where RU stands for round up. WR refers to the tWR parameter stored in the MRS. For tRP, if the result
of the division is not already an integer, round up to the next highest integer. tCK refers to the application clock period. Example: For
DDR2–533 at tCK = 3.75 ns with tWR programmed to 4 clocks. tDAL = 4 + (15 ns / 3.75 ns) clocks = 4 + (4) clocks = 8 clocks.
14) tDAL.nCK = WR [nCK] + tnRP.nCK = WR + RU{tRP [ps] / tCK.AVG[ps] }, where WR is the value programmed in the EMR.
15) Input waveform timing tDH with differential data strobe enabled MR[bit10] = 0, is referenced from the differential data strobe crosspoint to
the input signal crossing at the VIH.DC level for a falling signal and from the differential data strobe crosspoint to the input signal crossing
at the VIL.DC level for a rising signal applied to the device under test. DQS, DQS signals must be monotonic between VIL.DC.MAX and
VIH.DC.MIN. See Figure 4.
16) tDQSQ: Consists of data pin skew and output pattern effects, and p-channel to n-channel variation of the output drivers as well as output
slew rate mismatch between DQS / DQS and associated DQ in any given cycle.
17) These parameters are measured from a data strobe signal ((L/U/R)DQS / DQS) crossing to its respective clock signal (CK / CK) crossing.
The spec values are not affected by the amount of clock jitter applied (i.e. tJIT.PER, tJIT.CC, etc.), as these are relative to the clock signal
crossing. That is, these parameters should be met whether clock jitter is present or not.
18) Input waveform timing tDS with differential data strobe enabled MR[bit10] = 0, is referenced from the input signal crossing at the VIH.AC level
to the differential data strobe crosspoint for a rising signal, and from the input signal crossing at the VIL.AC level to the differential data strobe
crosspoint for a falling signal applied to the device under test. DQS, DQS signals must be monotonic between Vil(DC)MAX and Vih(DC)MIN. See
Figure 4.
19) If tDS or tDH is violated, data corruption may occur and the data must be re-written with valid data before a valid READ can be executed.
20) These parameters are measured from a data signal ((L/U)DM, (L/U)DQ0, (L/U)DQ1, etc.) transition edge to its respective data strobe signal
((L/U/R)DQS / DQS) crossing.
21) tHP is the minimum of the absolute half period of the actual input clock. tHP is an input parameter but not an input specification parameter.
It is used in conjunction with tQHS to derive the DRAM output timing tQH. The value to be used for tQH calculation is determined by the
following equation; tHP = MIN (tCH.ABS, tCL.ABS), where, tCH.ABS is the minimum of the actual instantaneous clock high time; tCL.ABS is the
minimum of the actual instantaneous clock low time.
22) tHZ and tLZ transitions occur in the same access time as valid data transitions. These parameters are referenced to a specific voltage level
which specifies when the device output is no longer driving (tHZ), or begins driving (tLZ) .
23) Input waveform timing is referenced from the input signal crossing at the VIL.DC level for a rising signal and VIH.DC for a falling signal applied
to the device under test. See Figure 5.
24) Input waveform timing is referenced from the input signal crossing at the VIH.AC level for a rising signal and VIL.AC for a falling signal applied
to the device under test. See Figure 5.
25) These parameters are measured from a command/address signal (CKE, CS, RAS, CAS, WE, ODT, BA0, A0, A1, etc.) transition edge to
its respective clock signal (CK / CK) crossing. The spec values are not affected by the amount of clock jitter applied (i.e. tJIT.PER, tJIT.CC,
etc.), as the setup and hold are relative to the clock signal crossing that latches the command/address. That is, these parameters should
be met whether clock jitter is present or not.
Rev. 1.3, 2006-12
03292006-6GMD-RSFT
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Internet Data Sheet
HYS[64/72]T[32/64/128]xx0HU-[25F/2.5/3/3S/3.7/5]-B
Unbuffered DDR2 SDRAM Module
26) tQH = tHP – tQHS, where: tHP is the minimum of the absolute half period of the actual input clock; and tQHS is the specification value under the
max column. {The less half-pulse width distortion present, the larger the tQH value is; and the larger the valid data eye will be.}
Examples: 1) If the system provides tHP of 1315 ps into a DDR2–667 SDRAM, the DRAM provides tQH of 975 ps minimum. 2) If the system
provides tHP of 1420 ps into a DDR2–667 SDRAM, the DRAM provides tQH of 1080 ps minimum.
27) tQHS accounts for: 1) The pulse duration distortion of on-chip clock circuits, which represents how well the actual tHP at the input is
transferred to the output; and 2) The worst case push-out of DQS on one transition followed by the worst case pull-in of DQ on the next
transition, both of which are independent of each other, due to data pin skew, output pattern effects, and pchannel to n-channel variation
of the output drivers.
28) tRPST end point and tRPRE begin point are not referenced to a specific voltage level but specify when the device output is no longer driving
(tRPST), or begins driving (tRPRE). Figure 3 shows a method to calculate these points when the device is no longer driving (tRPST), or begins
driving (tRPRE) by measuring the signal at two different voltages. The actual voltage measurement points are not critical as long as the
calculation is consistent.
29) When the device is operated with input clock jitter, this parameter needs to be derated by the actual tJIT.PER of the input clock. (output
deratings are relative to the SDRAM input clock.) For example, if the measured jitter into a DDR2–667 SDRAM has tJIT.PER.MIN = – 72 ps
and tJIT.PER.MAX = + 93 ps, then tRPRE.MIN(DERATED) = tRPRE.MIN + tJIT.PER.MIN = 0.9 x tCK.AVG – 72 ps = + 2178 ps and tRPRE.MAX(DERATED) = tRPRE.MAX
+ tJIT.PER.MAX = 1.1 x tCK.AVG + 93 ps = + 2843 ps. (Caution on the MIN/MAX usage!).
30) When the device is operated with input clock jitter, this parameter needs to be derated by the actual tJIT.DUTY of the input clock. (output
deratings are relative to the SDRAM input clock.) For example, if the measured jitter into a DDR2–667 SDRAM has tJIT.DUTY.MIN = – 72 ps
and tJIT.DUTY.MAX = + 93 ps, then tRPST.MIN(DERATED) = tRPST.MIN + tJIT.DUTY.MIN = 0.4 x tCK.AVG – 72 ps = + 928 ps and tRPST.MAX(DERATED) = tRPST.MAX
+ tJIT.DUTY.MAX = 0.6 x tCK.AVG + 93 ps = + 1592 ps. (Caution on the MIN/MAX usage!).
31) For these parameters, the DDR2 SDRAM device is characterized and verified to support tnPARAM = RU{tPARAM / tCK.AVG}, which is in clock
cycles, assuming all input clock jitter specifications are satisfied. For example, the device will support tnRP = RU{tRP / tCK.AVG}, which is in
clock cycles, if all input clock jitter specifications are met. This means: For DDR2–667 5–5–5, of which tRP = 15 ns, the device will support
tnRP = RU{tRP / tCK.AVG} = 5, i.e. as long as the input clock jitter specifications are met, Precharge command at Tm and Active command at
Tm + 5 is valid even if (Tm + 5 - Tm) is less than 15 ns due to input clock jitter.
32) tWTR is at lease two clocks (2 x tCK) independent of operation frequency.
TABLE 17
DRAM Component Timing Parameter by Speed Grade - DDR2–667
Parameter
Symbol
DDR2–667
Unit
Note
1)2)3)4)5)6)7)8)
Min.
Max.
tAC
tCCD
tCH.AVG
tCK.AVG
tCKE
–450
+450
ps
2
—
nCK
0.48
0.52
tCK.AVG
3000
8000
ps
3
—
nCK
12)
tCL.AVG
Auto-Precharge write recovery + precharge time tDAL
Minimum time clocks remain ON after CKE
tDELAY
0.48
0.52
tCK.AVG
10)11)
WR + tnRP
—
nCK
13)14)
tIS + tCK .AVG +
tIH
—
ns
tDH.BASE
DQ and DM input pulse width for each input
tDIPW
DQS output access time from CK / CK
tDQSCK
DQS input high pulse width
tDQSH
DQS input low pulse width
tDQSL
DQS-DQ skew for DQS & associated DQ signals tDQSQ
DQS latching rising transition to associated clock tDQSS
175
—
ps
0.35
—
tCK.AVG
–400
+400
ps
0.35
—
0.35
—
tCK.AVG
tCK.AVG
—
240
ps
16)
– 0.25
+ 0.25
tCK.AVG
17)
DQ output access time from CK / CK
CAS to CAS command delay
Average clock high pulse width
Average clock period
CKE minimum pulse width ( high and low pulse
width)
Average clock low pulse width
asynchronously drops LOW
DQ and DM input hold time
edges
Rev. 1.3, 2006-12
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9)
10)11)
19)20)15)
9)
Internet Data Sheet
HYS[64/72]T[32/64/128]xx0HU-[25F/2.5/3/3S/3.7/5]-B
Unbuffered DDR2 SDRAM Module
Parameter
Symbol
DDR2–667
Unit
Note
1)2)3)4)5)6)7)8)
DQ and DM input setup time
DQS falling edge hold time from CK
DQS falling edge to CK setup time
CK half pulse width
tDS.BASE
tDSH
tDSS
tHP
tHZ
Address and control input hold time
tIH.BASE
Control & address input pulse width for each input tIPW
Address and control input setup time
tIS.BASE
DQ low impedance time from CK/CK
tLZ.DQ
DQS/DQS low-impedance time from CK / CK
tLZ.DQS
MRS command to ODT update delay
tMOD
Mode register set command cycle time
tMRD
OCD drive mode output delay
tOIT
DQ/DQS output hold time from DQS
tQH
DQ hold skew factor
tQHS
Read preamble
tRPRE
Read postamble
tRPST
Internal Read to Precharge command delay
tRTP
Write preamble
tWPRE
Write postamble
tWPST
Write recovery time
tWR
Internal write to read command delay
tWTR
Exit power down to read command
tXARD
Exit active power-down mode to read command tXARDS
Data-out high-impedance time from CK / CK
Min.
Max.
100
—
ps
18)19)20)
0.2
—
17)
0.2
—
tCK.AVG
tCK.AVG
Min(tCH.ABS,
tCL.ABS)
—
ps
21)
—
tAC.MAX
ps
9)22)
275
—
ps
25)23)
17)
0.6
—
tCK.AVG
200
—
ps
24)25)
2 x tAC.MIN
ps
9)22)
tAC.MIN
tAC.MAX
tAC.MAX
ps
9)22)
0
12
ns
31)
2
—
nCK
0
12
ns
31)
tHP – tQHS
—
ps
26)
—
340
ps
27)
0.9
1.1
28)29)
0.4
0.6
tCK.AVG
tCK.AVG
7.5
—
ns
31)
0.35
—
0.4
0.6
tCK.AVG
tCK.AVG
15
—
ns
31)
7.5
—
ns
31)32)
2
—
nCK
7 – AL
—
nCK
28)30)
(slow exit, lower power)
Exit precharge power-down to any valid
command (other than NOP or Deselect)
tXP
2
—
nCK
Exit self-refresh to a non-read command
tRFC +10
—
ns
Exit self-refresh to read command
tXSNR
tXSRD
200
—
nCK
Write command to DQS associated clock edges
WL
RL–1
31)
nCK
1) For details and notes see the relevant Qimonda component data sheet
2) VDDQ = 1.8 V ± 0.1V; VDD = 1.8 V ± 0.1 V. See notes 5)6)7)8)
3) Timing that is not specified is illegal and after such an event, in order to guarantee proper operation, the DRAM must be powered down
and then restarted through the specified initialization sequence before normal operation can continue.
4) Timings are guaranteed with CK/CK differential Slew Rate of 2.0 V/ns. For DQS signals timings are guaranteed with a differential Slew
Rate of 2.0 V/ns in differential strobe mode and a Slew Rate of 1 V/ns in single ended mode.
5) The CK / CK input reference level (for timing reference to CK / CK) is the point at which CK and CK cross. The DQS / DQS, RDQS / RDQS,
input reference level is the crosspoint when in differential strobe mode.
6) Inputs are not recognized as valid until VREF stabilizes. During the period before VREF stabilizes, CKE = 0.2 x VDDQ is recognized as low.
7) The output timing reference voltage level is VTT.
Rev. 1.3, 2006-12
03292006-6GMD-RSFT
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Internet Data Sheet
HYS[64/72]T[32/64/128]xx0HU-[25F/2.5/3/3S/3.7/5]-B
Unbuffered DDR2 SDRAM Module
8) New units, ‘tCK.AVG‘ and ‘nCK‘, are introduced in DDR2–667 and DDR2–800. Unit ‘tCK.AVG‘ represents the actual tCK.AVG of the input clock
under operation. Unit ‘nCK‘ represents one clock cycle of the input clock, counting the actual clock edges. Note that in DDR2–400 and
DDR2–533, ‘tCK‘ is used for both concepts. Example: tXP = 2 [nCK] means; if Power Down exit is registered at Tm, an Active command
may be registered at Tm + 2, even if (Tm + 2 - Tm) is 2 x tCK.AVG + tERR.2PER(Min).
9) When the device is operated with input clock jitter, this parameter needs to be derated by the actual tERR(6-10per) of the input clock. (output
deratings are relative to the SDRAM input clock.) For example, if the measured jitter into a DDR2–667 SDRAM has tERR(6-10PER).MIN = – 272
ps and tERR(6- 10PER).MAX = + 293 ps, then tDQSCK.MIN(DERATED) = tDQSCK.MIN – tERR(6-10PER).MAX = – 400 ps – 293 ps = – 693 ps and
tDQSCK.MAX(DERATED) = tDQSCK.MAX – tERR(6-10PER).MIN = 400 ps + 272 ps = + 672 ps. Similarly, tLZ.DQ for DDR2–667 derates to tLZ.DQ.MIN(DERATED)
= - 900 ps – 293 ps = – 1193 ps and tLZ.DQ.MAX(DERATED) = 450 ps + 272 ps = + 722 ps. (Caution on the MIN/MAX usage!)
10) Input clock jitter spec parameter. These parameters are referred to as 'input clock jitter spec parameters' and these parameters apply to
DDR2–667 and DDR2–800 only. The jitter specified is a random jitter meeting a Gaussian distribution.
11) These parameters are specified per their average values, however it is understood that the relationship between the average timing and
the absolute instantaneous timing holds all the times (min. and max of SPEC values are to be used for calculations ).
12) tCKE.MIN of 3 clocks means CKE must be registered on three consecutive positive clock edges. CKE must remain at the valid input level the
entire time it takes to achieve the 3 clocks of registration. Thus, after any CKE transition, CKE may not transition from its valid level during
the time period of tIS + 2 x tCK + tIH.
13) DAL = WR + RU{tRP(ns) / tCK(ns)}, where RU stands for round up. WR refers to the tWR parameter stored in the MRS. For tRP, if the result
of the division is not already an integer, round up to the next highest integer. tCK refers to the application clock period. Example: For
DDR2–533 at tCK = 3.75 ns with tWR programmed to 4 clocks. tDAL = 4 + (15 ns / 3.75 ns) clocks = 4 + (4) clocks = 8 clocks.
14) tDAL.nCK = WR [nCK] + tnRP.nCK = WR + RU{tRP [ps] / tCK.AVG[ps] }, where WR is the value programmed in the EMR.
15) Input waveform timing tDH with differential data strobe enabled MR[bit10] = 0, is referenced from the differential data strobe crosspoint to
the input signal crossing at the VIH.DC level for a falling signal and from the differential data strobe crosspoint to the input signal crossing
at the VIL.DC level for a rising signal applied to the device under test. DQS, DQS signals must be monotonic between VIL.DC.MAX and
VIH.DC.MIN. See Figure 4.
16) tDQSQ: Consists of data pin skew and output pattern effects, and p-channel to n-channel variation of the output drivers as well as output
slew rate mismatch between DQS / DQS and associated DQ in any given cycle.
17) These parameters are measured from a data strobe signal ((L/U/R)DQS / DQS) crossing to its respective clock signal (CK / CK) crossing.
The spec values are not affected by the amount of clock jitter applied (i.e. tJIT.PER, tJIT.CC, etc.), as these are relative to the clock signal
crossing. That is, these parameters should be met whether clock jitter is present or not.
18) Input waveform timing tDS with differential data strobe enabled MR[bit10] = 0, is referenced from the input signal crossing at the VIH.AC level
to the differential data strobe crosspoint for a rising signal, and from the input signal crossing at the VIL.AC level to the differential data strobe
crosspoint for a falling signal applied to the device under test. DQS, DQS signals must be monotonic between Vil(DC)MAX and Vih(DC)MIN. See
Figure 4.
19) If tDS or tDH is violated, data corruption may occur and the data must be re-written with valid data before a valid READ can be executed.
20) These parameters are measured from a data signal ((L/U)DM, (L/U)DQ0, (L/U)DQ1, etc.) transition edge to its respective data strobe signal
((L/U/R)DQS / DQS) crossing.
21) tHP is the minimum of the absolute half period of the actual input clock. tHP is an input parameter but not an input specification parameter.
It is used in conjunction with tQHS to derive the DRAM output timing tQH. The value to be used for tQH calculation is determined by the
following equation; tHP = MIN (tCH.ABS, tCL.ABS), where, tCH.ABS is the minimum of the actual instantaneous clock high time; tCL.ABS is the
minimum of the actual instantaneous clock low time.
22) tHZ and tLZ transitions occur in the same access time as valid data transitions. These parameters are referenced to a specific voltage level
which specifies when the device output is no longer driving (tHZ), or begins driving (tLZ) .
23) Input waveform timing is referenced from the input signal crossing at the VIL.DC level for a rising signal and VIH.DC for a falling signal applied
to the device under test. See Figure 5.
24) Input waveform timing is referenced from the input signal crossing at the VIH.AC level for a rising signal and VIL.AC for a falling signal applied
to the device under test. See Figure 5.
25) These parameters are measured from a command/address signal (CKE, CS, RAS, CAS, WE, ODT, BA0, A0, A1, etc.) transition edge to
its respective clock signal (CK / CK) crossing. The spec values are not affected by the amount of clock jitter applied (i.e. tJIT.PER, tJIT.CC,
etc.), as the setup and hold are relative to the clock signal crossing that latches the command/address. That is, these parameters should
be met whether clock jitter is present or not.
26) tQH = tHP – tQHS, where: tHP is the minimum of the absolute half period of the actual input clock; and tQHS is the specification value under the
max column. {The less half-pulse width distortion present, the larger the tQH value is; and the larger the valid data eye will be.}
Examples: 1) If the system provides tHP of 1315 ps into a DDR2–667 SDRAM, the DRAM provides tQH of 975 ps minimum. 2) If the system
provides tHP of 1420 ps into a DDR2–667 SDRAM, the DRAM provides tQH of 1080 ps minimum.
27) tQHS accounts for: 1) The pulse duration distortion of on-chip clock circuits, which represents how well the actual tHP at the input is
transferred to the output; and 2) The worst case push-out of DQS on one transition followed by the worst case pull-in of DQ on the next
transition, both of which are independent of each other, due to data pin skew, output pattern effects, and pchannel to n-channel variation
of the output drivers.
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HYS[64/72]T[32/64/128]xx0HU-[25F/2.5/3/3S/3.7/5]-B
Unbuffered DDR2 SDRAM Module
28) tRPST end point and tRPRE begin point are not referenced to a specific voltage level but specify when the device output is no longer driving
(tRPST), or begins driving (tRPRE). Figure 3 shows a method to calculate these points when the device is no longer driving (tRPST), or begins
driving (tRPRE) by measuring the signal at two different voltages. The actual voltage measurement points are not critical as long as the
calculation is consistent.
29) When the device is operated with input clock jitter, this parameter needs to be derated by the actual tJIT.PER of the input clock. (output
deratings are relative to the SDRAM input clock.) For example, if the measured jitter into a DDR2–667 SDRAM has tJIT.PER.MIN = – 72 ps
and tJIT.PER.MAX = + 93 ps, then tRPRE.MIN(DERATED) = tRPRE.MIN + tJIT.PER.MIN = 0.9 x tCK.AVG – 72 ps = + 2178 ps and tRPRE.MAX(DERATED) = tRPRE.MAX
+ tJIT.PER.MAX = 1.1 x tCK.AVG + 93 ps = + 2843 ps. (Caution on the MIN/MAX usage!).
30) When the device is operated with input clock jitter, this parameter needs to be derated by the actual tJIT.DUTY of the input clock. (output
deratings are relative to the SDRAM input clock.) For example, if the measured jitter into a DDR2–667 SDRAM has tJIT.DUTY.MIN = – 72 ps
and tJIT.DUTY.MAX = + 93 ps, then tRPST.MIN(DERATED) = tRPST.MIN + tJIT.DUTY.MIN = 0.4 x tCK.AVG – 72 ps = + 928 ps and tRPST.MAX(DERATED) = tRPST.MAX
+ tJIT.DUTY.MAX = 0.6 x tCK.AVG + 93 ps = + 1592 ps. (Caution on the MIN/MAX usage!).
31) For these parameters, the DDR2 SDRAM device is characterized and verified to support tnPARAM = RU{tPARAM / tCK.AVG}, which is in clock
cycles, assuming all input clock jitter specifications are satisfied. For example, the device will support tnRP = RU{tRP / tCK.AVG}, which is in
clock cycles, if all input clock jitter specifications are met. This means: For DDR2–667 5–5–5, of which tRP = 15 ns, the device will support
tnRP = RU{tRP / tCK.AVG} = 5, i.e. as long as the input clock jitter specifications are met, Precharge command at Tm and Active command at
Tm + 5 is valid even if (Tm + 5 - Tm) is less than 15 ns due to input clock jitter.
32) tWTR is at lease two clocks (2 x tCK) independent of operation frequency.
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03292006-6GMD-RSFT
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Internet Data Sheet
HYS[64/72]T[32/64/128]xx0HU-[25F/2.5/3/3S/3.7/5]-B
Unbuffered DDR2 SDRAM Module
FIGURE 3
Method for calculating transitions and endpoint
92+[P9
977[P9
92+[P9
977[P9
W/=
W+=
W535(EHJLQSRLQW
W5367
H QGSRLQW
92/[P9
977[P9
92/[P9
977[P9
7 7
7 7
W+=W5367
HQGSRLQW 77
W/=W535(
E HJLQSRLQW 7
7
FIGURE 4
Differential input waveform timing - tDS and tDS
'46
'46
W'6
W'+
W'6
W'+
9''4
9,+DFPLQ
9,+GFPLQ
95()GF
9,/GF PD[
9,/DF PD[
966
FIGURE 5
Differential input waveform timing - tlS and tlH
&.
&.
W,6
W,+
W,6
W,+
9''4
9,+DFPLQ
9,+GFPLQ
95()GF
9,/GFPD[
9,/DFPD[
966
Rev. 1.3, 2006-12
03292006-6GMD-RSFT
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Internet Data Sheet
HYS[64/72]T[32/64/128]xx0HU-[25F/2.5/3/3S/3.7/5]-B
Unbuffered DDR2 SDRAM Module
TABLE 18
DRAM Component Timing Parameter by Speed Grade - DDR2–533
Parameter
Symbol
DDR2–533
Unit
Note
1)2)3)4)5)6)7)
Min.
Max.
tAC
tCCD
tCH
tCKE
tCL
tDAL
–500
+500
ps
2
—
0.45
0.55
Minimum time clocks remain ON after CKE
asynchronously drops LOW
DQ and DM input hold time (differential data
strobe)
DQ output access time from CK / CK
3
—
0.45
0.55
WR + tRP
—
tCK
tCK
tCK
tCK
tCK
tDELAY
tIS + tCK + tIH
—
ns
9)
tDH(base)
225
—
ps
10)
–25
—
ps
11)
tDIPW
tDQSCK
tDQSL,H
tDQSQ
0.35
—
tCK
–450
+450
ps
0.35
—
tCK
—
300
ps
tDQSS
tDS(base)
– 0.25
+ 0.25
tCK
100
—
ps
11)
–25
—
ps
11)
tDSH
0.2
—
tCK
DQS falling edge to CK setup time (write cycle) tDSS
0.2
—
tCK
CAS A to CAS B command period
CK, CK high-level width
CKE minimum high and low pulse width
CK, CK low-level width
Auto-Precharge write recovery + precharge
time
DQ and DM input hold time (single ended data tDH1(base)
strobe)
DQ and DM input pulse width (each input)
DQS output access time from CK / CK
DQS input low (high) pulse width (write cycle)
DQS-DQ skew (for DQS & associated DQ
signals)
Write command to 1st DQS latching transition
DQ and DM input setup time (differential data
strobe)
DQ and DM input setup time (single ended data tDS1(base)
strobe)
DQS falling edge hold time from CK (write
cycle)
Clock half period
Data-out high-impedance time from CK / CK
Address and control input hold time
Address and control input pulse width
(each input)
Address and control input setup time
DQ low-impedance time from CK / CK
DQS low-impedance from CK / CK
Mode register set command cycle time
OCD drive mode output delay
Data output hold time from DQS
Data hold skew factor
Average periodic refresh Interval
Rev. 1.3, 2006-12
03292006-6GMD-RSFT
tHP
tHZ
tIH(base)
tIPW
MIN. (tCL, tCH)
tIS(base)
tLZ(DQ)
tLZ(DQS)
tMRD
tOIT
tQH
tQHS
tREFI
28
8)18)
11)
12)
—
tAC.MAX
ps
13)
375
—
ps
11)
0.6
—
tCK
250
—
ps
11)
2 × tAC.MIN
ps
14)
tAC.MIN
tAC.MAX
tAC.MAX
ps
14)
2
—
tCK
0
12
ns
tHP –tQHS
—
—
—
400
ps
—
7.8
µs
14)15)
Internet Data Sheet
HYS[64/72]T[32/64/128]xx0HU-[25F/2.5/3/3S/3.7/5]-B
Unbuffered DDR2 SDRAM Module
Parameter
Symbol
DDR2–533
Unit
Note
1)2)3)4)5)6)7)
Min.
Max.
tREFI
tRFC
—
3.9
µs
16)18)
105
—
ns
17)
tRP
tRP
tRPRE
tRPST
tRRD
tRP + 1tCK
—
ns
15 + 1tCK
—
ns
0.9
1.1
14)
0.40
0.60
tCK
tCK
7.5
—
ns
14)18)
Active bank A to Active bank B command
period
tRRD
10
—
ns
16)22)
Internal Read to Precharge command delay
tRTP
tWPRE
tWPST
tWR
7.5
—
ns
0.25
—
0.40
0.60
tCK
tCK
15
—
ns
tWTR
tXARD
7.5
—
ns
20)
2
—
tCK
21)
Exit active power-down mode to Read
command (slow exit, lower power)
tXARDS
6 – AL
—
tCK
21)
Exit precharge power-down to any valid
command (other than NOP or Deselect)
tXP
2
—
tCK
Exit Self-Refresh to non-Read command
tXSNR
tXSRD
tRFC +10
—
ns
200
—
WR
tWR/tCK
—
tCK
tCK
Average periodic refresh Interval
Auto-Refresh to Active/Auto-Refresh
command period
Precharge-All (4 banks) command period
Precharge-All (8 banks) command period
Read preamble
Read postamble
Active bank A to Active bank B command
period
Write preamble
Write postamble
Write recovery time for write without AutoPrecharge
Internal Write to Read command delay
Exit power down to any valid command
(other than NOP or Deselect)
Exit Self-Refresh to Read command
Write recovery time for write with AutoPrecharge
14)
19)
22)
1) For details and notes see the relevant Qimonda component data sheet
2) VDDQ = 1.8 V ± 0.1 V; VDD = 1.8 V ±0.1 V. See notes 5)6)7)8)
3) Timing that is not specified is illegal and after such an event, in order to guarantee proper operation, the DRAM must be powered down
and then restarted through the specified initialization sequence before normal operation can continue.
4) Timings are guaranteed with CK/CK differential Slew Rate of 2.0 V/ns. For DQS signals timings are guaranteed with a differential Slew
Rate of 2.0 V/ns in differential strobe mode and a Slew Rate of 1 V/ns in single ended mode.
5) The CK / CK input reference level (for timing reference to CK / CK) is the point at which CK and CK cross. The DQS / DQS, RDQS/ RDQS,
input reference level is the crosspoint when in differential strobe mode.
6) Inputs are not recognized as valid until VREF stabilizes. During the period before VREF stabilizes, CKE = 0.2 x VDDQ is recognized as low.
7) The output timing reference voltage level is VTT.
8) For each of the terms, if not already an integer, round to the next highest integer. tCK refers to the application clock period. WR refers to
the WR parameter stored in the MR.
9) The clock frequency is allowed to change during self-refresh mode or precharge power-down mode.
10) For timing definition, refer to the Component data sheet.
11) Consists of data pin skew and output pattern effects, and p-channel to n-channel variation of the output drivers as well as output Slew Rate
mis-match between DQS / DQS and associated DQ in any given cycle.
12) MIN (tCL, tCH) refers to the smaller of the actual clock low time and the actual clock high time as provided to the device (i.e. this value can
be greater than the minimum specification limits for tCL and tCH).
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HYS[64/72]T[32/64/128]xx0HU-[25F/2.5/3/3S/3.7/5]-B
Unbuffered DDR2 SDRAM Module
13) The tHZ, tRPST and tLZ, tRPRE parameters are referenced to a specific voltage level, which specify when the device output is no longer driving
(tHZ, tRPST), or begins driving (tLZ, tRPRE). tHZ and tLZ transitions occur in the same access time windows as valid data transitions.These
parameters are verified by design and characterization, but not subject to production test.
14) The Auto-Refresh command interval has be reduced to 3.9 µs when operating the DDR2 DRAM in a temperature range between 85 °C
and 95 °C.
15) 0 °C≤ TCASE ≤ 85 °C
16) 85 °C < TCASE ≤ 95 °C
17) A maximum of eight Auto-Refresh commands can be posted to any given DDR2 SDRAM device.
18) The tRRD timing parameter depends on the page size of the DRAM organization. See Table 2 “Ordering Information for RoHS
Compliant Products” on Page 4.
19) The maximum limit for the tWPST parameter is not a device limit. The device operates with a greater value for this parameter, but system
performance (bus turnaround) degrades accordingly.
20) Minimum tWTR is two clocks when operating the DDR2-SDRAM at frequencies ≤ 200 ΜΗz.
21) User can choose two different active power-down modes for additional power saving via MRS address bit A12. In “standard active powerdown mode” (MR, A12 = “0”) a fast power-down exit timing tXARD can be used. In “low active power-down mode” (MR, A12 =”1”) a slow
power-down exit timing tXARDS has to be satisfied.
22) WR must be programmed to fulfill the minimum requirement for the tWR timing parameter, where WRMIN[cycles] = tWR(ns)/tCK(ns) rounded
up to the next integer value. tDAL = WR + (tRP/tCK). For each of the terms, if not already an integer, round to the next highest integer. tCK
refers to the application clock period. WR refers to the WR parameter stored in the MRS.
Rev. 1.3, 2006-12
03292006-6GMD-RSFT
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Internet Data Sheet
HYS[64/72]T[32/64/128]xx0HU-[25F/2.5/3/3S/3.7/5]-B
Unbuffered DDR2 SDRAM Module
TABLE 19
DRAM Component Timing Parameter by Speed Grade - DDR2-400
Parameter
Symbol
DDR2–400
Unit
Note
1)2)3)4)5)6)7)
Min.
Max.
tAC
tCCD
tCH
tCKE
tCL
tDAL
–600
+600
ps
2
—
0.45
0.55
Minimum time clocks remain ON after CKE
asynchronously drops LOW
DQ and DM input hold time (differential data
strobe)
DQ output access time from CK / CK
CAS A to CAS B command period
CK, CK high-level width
CKE minimum high and low pulse width
CK, CK low-level width
Auto-Precharge write recovery + precharge
time
3
—
0.45
0.55
WR + tRP
—
tCK
tCK
tCK
tCK
tCK
tDELAY
tIS + tCK + tIH
—
ns
9)
tDH(base)
275
—
ps
10)
–25
—
ps
11)
0.35
—
tCK
–500
+500
ps
0.35
—
tCK
—
350
ps
– 0.25
+ 0.25
tCK
DQ and DM input hold time (single ended data tDH1(base)
strobe)
DQ and DM input pulse width (each input)
DQS output access time from CK / CK
DQS input low (high) pulse width (write cycle)
DQS-DQ skew (for DQS & associated DQ
signals)
tDIPW
tDQSCK
tDQSL,H
tDQSQ
Write command to 1st DQS latching transition tDQSS
8)21)
11)
DQ and DM input setup time (differential data
strobe)
tDS(base)
150
—
ps
11)
DQ and DM input setup time (single ended
data strobe)
tDS1(base)
–25
—
ps
11)
DQS falling edge hold time from CK (write
cycle)
tDSH
0.2
—
tCK
DQS falling edge to CK setup time (write cycle) tDSS
0.2
—
tCK
Clock half period
Data-out high-impedance time from CK / CK
Address and control input hold time
Address and control input pulse width
(each input)
Address and control input setup time
DQ low-impedance time from CK / CK
DQS low-impedance from CK / CK
Mode register set command cycle time
OCD drive mode output delay
Data output hold time from DQS
Data hold skew factor
Average periodic refresh Interval
Rev. 1.3, 2006-12
03292006-6GMD-RSFT
tHP
tHZ
tIH(base)
tIPW
MIN. (tCL, tCH)
tIS(base)
tLZ(DQ)
tLZ(DQS)
tMRD
tOIT
tQH
tQHS
tREFI
31
—
12)
—
tAC.MAX
ps
13)
475
—
ps
11)
0.6
—
tCK
350
—
ps
11)
2 × tAC.MIN
ps
14)
tAC.MIN
tAC.MAX
tAC.MAX
ps
14)
2
—
tCK
0
12
ns
tHP –tQHS
—
—
—
450
ps
—
7.8
µs
14)15)
Internet Data Sheet
HYS[64/72]T[32/64/128]xx0HU-[25F/2.5/3/3S/3.7/5]-B
Unbuffered DDR2 SDRAM Module
Parameter
Symbol
DDR2–400
Unit
Note
1)2)3)4)5)6)7)
Min.
Max.
—
3.9
µs
16)18)
105
—
ns
17)
tRP
tRP
tRPRE
tRPST
tRRD
tRP + 1tCK
15 + 1tCK
—
ns
—
ns
0.9
1.1
14)
0.40
0.60
tCK
tCK
7.5
—
ns
14)18)
Active bank A to Active bank B command
period
tRRD
10
—
ns
16)22)
Internal Read to Precharge command delay
tRTP
tWPRE
tWPST
tWR
7.5
—
ns
0.25
—
0.40
0.60
tCK
tCK
15
—
ns
tWTR
tXARD
10
—
ns
20)
2
—
tCK
21)
Exit active power-down mode to Read
command (slow exit, lower power)
tXARDS
6 – AL
—
tCK
21)
Exit precharge power-down to any valid
command (other than NOP or Deselect)
tXP
2
—
tCK
Exit Self-Refresh to non-Read command
tXSNR
tXSRD
tRFC +10
—
ns
200
—
WR
tWR/tCK
—
tCK
tCK
Average periodic refresh Interval
tREFI
Auto-Refresh to Active/Auto-Refresh
command period
Precharge-All (4 banks) command period
Precharge-All (8 banks) command period
Read preamble
Read postamble
Active bank A to Active bank B command
period
Write preamble
Write postamble
Write recovery time for write without AutoPrecharge
Internal Write to Read command delay
Exit power down to any valid command
(other than NOP or Deselect)
Exit Self-Refresh to Read command
Write recovery time for write with AutoPrecharge
14)
19)
22)
1) For details and notes see the relevant Qimonda component data sheet
2) VDDQ = 1.8 V ± 0.1 V; VDD = 1.8 V ±0.1 V. See notes 5)6)7)8)
3) Timing that is not specified is illegal and after such an event, in order to guarantee proper operation, the DRAM must be powered down
and then restarted through the specified initialization sequence before normal operation can continue.
4) Timings are guaranteed with CK/CK differential Slew Rate of 2.0 V/ns. For DQS signals timings are guaranteed with a differential Slew
Rate of 2.0 V/ns in differential strobe mode and a Slew Rate of 1 V/ns in single ended mode.
5) The CK / CK input reference level (for timing reference to CK / CK) is the point at which CK and CK cross. The DQS / DQS, RDQS/ RDQS,
input reference level is the crosspoint when in differential strobe mode.
6) Inputs are not recognized as valid until VREF stabilizes. During the period before VREF stabilizes, CKE = 0.2 x VDDQ is recognized as low.
7) The output timing reference voltage level is VTT.
8) For each of the terms, if not already an integer, round to the next highest integer. tCK refers to the application clock period. WR refers to
the WR parameter stored in the MR.
9) The clock frequency is allowed to change during self-refresh mode or precharge power-down mode.
10) For timing definition, refer to the Component data sheet.
11) Consists of data pin skew and output pattern effects, and p-channel to n-channel variation of the output drivers as well as output Slew Rate
mis-match between DQS / DQS and associated DQ in any given cycle.
12) MIN (tCL, tCH) refers to the smaller of the actual clock low time and the actual clock high time as provided to the device (i.e. this value can
be greater than the minimum specification limits for tCL and tCH).
Rev. 1.3, 2006-12
03292006-6GMD-RSFT
32
Internet Data Sheet
HYS[64/72]T[32/64/128]xx0HU-[25F/2.5/3/3S/3.7/5]-B
Unbuffered DDR2 SDRAM Module
13) The tHZ, tRPST and tLZ, tRPRE parameters are referenced to a specific voltage level, which specify when the device output is no longer driving
(tHZ, tRPST), or begins driving (tLZ, tRPRE). tHZ and tLZ transitions occur in the same access time windows as valid data transitions.These
parameters are verified by design and characterization, but not subject to production test.
14) The Auto-Refresh command interval has be reduced to 3.9 µs when operating the DDR2 DRAM in a temperature range between 85 °C
and 95 °C.
15) 0 °C≤ TCASE ≤ 85 °C
16) 85 °C < TCASE ≤ 95 °C
17) A maximum of eight Auto-Refresh commands can be posted to any given DDR2 SDRAM device.
18) The tRRD timing parameter depends on the page size of the DRAM organization. See Table 2 “Ordering Information for RoHS
Compliant Products” on Page 4.
19) The maximum limit for the tWPST parameter is not a device limit. The device operates with a greater value for this parameter, but system
performance (bus turnaround) degrades accordingly.
20) Minimum tWTR is two clocks when operating the DDR2-SDRAM at frequencies ≤ 200 ΜΗz.
21) User can choose two different active power-down modes for additional power saving via MRS address bit A12. In “standard active powerdown mode” (MR, A12 = “0”) a fast power-down exit timing tXARD can be used. In “low active power-down mode” (MR, A12 =”1”) a slow
power-down exit timing tXARDS has to be satisfied.
22) WR must be programmed to fulfill the minimum requirement for the tWR timing parameter, where WRMIN[cycles] = tWR(ns)/tCK(ns) rounded
up to the next integer value. tDAL = WR + (tRP/tCK). For each of the terms, if not already an integer, round to the next highest integer. tCK
refers to the application clock period. WR refers to the WR parameter stored in the MRS.
3.3.3
ODT AC Electrical Characteristics
ODT AC Characteristics for: DDR2–800 & DDR2–667(Table 20) and DDR2–533C & DDR2–400B(Table 21)
TABLE 20
ODT AC Character. and Operating Conditions for DDR2-800 & DDR2-667
Symbol
tAOND
tAON
tAONPD
tAOFD
tAOF
tAOFPD
tANPD
tAXPD
Parameter / Condition
Values
Unit
Note
Min.
Max.
ODT turn-on delay
2
2
nCK
1)
ODT turn-on
tAC.MAX + 0.7 ns
2 tCK + tAC.MAX + 1 ns
ns
1)2)
ODT turn-on (Power-Down Modes)
tAC.MIN
tAC.MIN + 2 ns
ns
1)
ODT turn-off delay
2.5
2.5
nCK
1)
ODT turn-off
tAC.MAX + 0.6 ns
2.5 tCK + tAC.MAX + 1 ns
ns
1)3)
ODT turn-off (Power-Down Modes)
tAC.MIN
tAC.MIN + 2 ns
ns
1)
ODT to Power Down Mode Entry Latency
3
—
nCK
1)
1)
ODT Power Down Exit Latency
8
—
nCK
1) New units, 'tCK.AVG' and 'nCK', are introduced in DDR2-667 and DDR2-800. Unit 'tCK.AVG' represents the actual tCK.AVG of the input clock
under operation. Unit 'nCK' represents one clock cycle of the input clock, counting the actual clock edges. Note that in DDR2-400 and
DDR2-533, 'tCK' is used for both concepts. Example: tXP = 2 [nCK] means; if Power Down exit is registered at Tm, an Active command may
be registered at Tm + 2, even if (Tm + 2 - Tm) is 2 × tCK.AVG+ tEPR.2PER(MIN).
2) ODT turn on time min is when the device leaves high impedance and ODT resistance begins to turn on. ODT turn on time max is when
the ODT resistance is fully on. Both are measured from tAOND, which is interpreted differently per speed bin. For DDR2-667/800, tAOND is
2 clock cycles after the clock edge that registered a first ODT HIGH counting the actual input clock edges.
3) ODT turn off time min. is when the device starts to turn off ODT resistance. ODT turn off time max is when the bus is in high impedance.
Both are measured from tAOFD. Both are measured from tAOFD, which is interpreted differently per speed bin. For DDR2-667/800,if tCK.AVG =
3 ns is assumed, tAOFD= 1.5 ns (0.5 × 3 ns) after the second trailing clock edge counting from the clock edge that registered a first ODT
LOW and by counting the actual input clock edge.
Rev. 1.3, 2006-12
03292006-6GMD-RSFT
33
Internet Data Sheet
HYS[64/72]T[32/64/128]xx0HU-[25F/2.5/3/3S/3.7/5]-B
Unbuffered DDR2 SDRAM Module
TABLE 21
ODT AC Character. and Operating Conditions for DDR2-533 & DDR2-400
Symbol
Parameter / Condition
Values
Min.
tAOND
tAON
tAONPD
tAOFD
tAOF
tAOFPD
tANPD
tAXPD
Unit
Note
Max.
ODT turn-on delay
2
2
tCK
ODT turn-on
tAC.MAX + 1 ns
2 tCK + tAC.MAX + 1 ns
ns
ODT turn-on (Power-Down Modes)
tAC.MIN
tAC.MIN + 2 ns
ODT turn-off delay
2.5
2.5
tCK
ODT turn-off
tAC.MAX + 0.6 ns
2.5 tCK + tAC.MAX + 1 ns
ns
ODT turn-off (Power-Down Modes)
tAC.MIN
tAC.MIN + 2 ns
ODT to Power Down Mode Entry Latency
3
—
ODT Power Down Exit Latency
8
—
tCK
tCK
1)
ns
2)
ns
1) ODT turn on time min is when the device leaves high impedance and ODT resistance begins to turn on. ODT turn on time max is when
the ODT resistance is fully on. Both are measured from tAOND, which is interpreted differently per speed bin. For DDR2-400/533, tAOND is
10 ns (= 2 x 5 ns) after the clock edge that registered a first ODT HIGH if tCK = 5 ns.
2) ODT turn off time min. is when the device starts to turn off ODT resistance. ODT turn off time max is when the bus is in high impedance.
Both are measured from tAOFD. Both are measured from tAOFD, which is interpreted differently per speed bin. For DDR2-400/533, tAOFD is
12.5 ns (= 2.5 x 5 ns) after the clock edge that registered a first ODT HIGH if tCK = 5 ns.
Rev. 1.3, 2006-12
03292006-6GMD-RSFT
34
Internet Data Sheet
HYS[64/72]T[32/64/128]xx0HU-[25F/2.5/3/3S/3.7/5]-B
Unbuffered DDR2 SDRAM Module
3.4
IDD Specifications and Conditions
List of tables defining IDD Specifications and Conditions.
• Table 22 “IDD Measurement Conditions” on Page 35
• Table 23 “Definitions for IDD” on Page 36
• Table 25 “IDD Specification for HYS[64/72]T[32/64/128]0x0HU-2.5-B” on Page 38
• Table 26 “IDD Specification for HYS[64/72]T[32/64/128]0x0HU-3-B” on Page 39
• Table 27 “IDD Specification for HYS[64/72]T[32/64/128]xx0HU-3S-B” on Page 40
• Table 27 “IDD Specification for HYS[64/72]T[32/64/128]xx0HU-3S-B” on Page 40
• Table 28 “IDD Specification for HYS[64/72]T[32/64/128]xx0HU-3.7-B” on Page 41
• Table 29 “I DD Specification for HYS[64/72]T[32/647128]0x0HU-5-B” on Page 42
TABLE 22
IDD Measurement Conditions
Parameter
Symbol Note
1)2)3)4)5)
Operating Current 0
IDD0
One bank Active - Precharge; tCK = tCK.MIN, tRC = tRC.MIN, tRAS = tRAS.MIN, CKE is HIGH, CS is HIGH between
valid commands. Address and control inputs are SWITCHING, Databus inputs are SWITCHING.
Operating Current 1
One bank Active - Read - Precharge; IOUT = 0 mA, BL = 4, tCK = tCK.MIN, tRC = tRC.MIN, tRAS = tRAS.MIN,
tRCD = tRCD.MIN, AL = 0, CL = CLMIN; CKE is HIGH, CS is HIGH between valid commands. Address and
control inputs are SWITCHING, Databus inputs are SWITCHING.
IDD1
6)
Precharge Standby Current
IDD2N
All banks idle; CS is HIGH; CKE is HIGH; tCK = tCK.MIN; Other control and address inputs are SWITCHING,
Databus inputs are SWITCHING.
Precharge Power-Down Current
Other control and address inputs are STABLE, Data bus inputs are FLOATING.
IDD2P
Precharge Quiet Standby Current
All banks idle; CS is HIGH; CKE is HIGH; tCK = tCK.MIN; Other control and address inputs are STABLE,
Data bus inputs are FLOATING.
IDD2Q
Active Standby Current
Burst Read: All banks open; Continuous burst reads; BL = 4; AL = 0, CL = CLMIN; tCK = tCK.MIN;
tRAS = tRAS.MAX, tRP = tRP.MIN; CKE is HIGH, CS is HIGH between valid commands. Address inputs are
SWITCHING; Data Bus inputs are SWITCHING; IOUT = 0 mA.
IDD3N
Active Power-Down Current
IDD3P(0)
All banks open; tCK = tCK.MIN, CKE is LOW; Other control and address inputs are STABLE, Data bus inputs
are FLOATING. MRS A12 bit is set to LOW (Fast Power-down Exit);
Active Power-Down Current
IDD3P(1)
All banks open; tCK = tCK.MIN, CKE is LOW; Other control and address inputs are STABLE, Data bus inputs
are FLOATING. MRS A12 bit is set to HIGH (Slow Power-down Exit);
Operating Current - Burst Read
IDD4R
All banks open; Continuous burst reads; BL = 4; AL = 0, CL = CLMIN; tCK = tCKMIN; tRAS = tRASMAX;
tRP = tRPMIN; CKE is HIGH, CS is HIGH between valid commands; Address inputs are SWITCHING; Data
bus inputs are SWITCHING; IOUT = 0mA.
Operating Current - Burst Write
All banks open; Continuous burst writes; BL = 4; AL = 0, CL = CLMIN; tCK = tCK.MIN;
tRAS = tRAS.MAX., tRP = tRP.MAX; CKE is HIGH, CS is HIGH between valid commands. Address inputs are
SWITCHING; Data Bus inputs are SWITCHING;
Rev. 1.3, 2006-12
03292006-6GMD-RSFT
35
IDD4W
6)
Internet Data Sheet
HYS[64/72]T[32/64/128]xx0HU-[25F/2.5/3/3S/3.7/5]-B
Unbuffered DDR2 SDRAM Module
Parameter
Symbol Note
1)2)3)4)5)
Burst Refresh Current
tCK = tCK.MIN., Refresh command every tRFC = tRFC.MIN interval, CKE is HIGH, CS is HIGH between valid
commands, Other control and address inputs are SWITCHING, Data bus inputs are SWITCHING.
IDD5B
Distributed Refresh Current
tCK = tCK.MIN., Refresh command every tRFC = tREFI interval, CKE is LOW and CS is HIGH between valid
commands, Other control and address inputs are SWITCHING, Data bus inputs are SWITCHING.
IDD5D
Self-Refresh Current
IDD6
CKE ≤ 0.2 V; external clock off, CK and CK at 0 V; Other control and address inputs are FLOATING, Data
bus inputs are FLOATING. IDD6 current values are guaranteed up to TCASE of 85 °C max.
All Bank Interleave Read Current
IDD7
All banks are being interleaved at minimum tRC without violating tRRD using a burst length of 4. Control
and address bus inputs are STABLE during DESELECTS. Iout = 0 mA.
1) VDDQ = 1.8 V ± 0.1 V; VDD = 1.8 V ± 0.1 V
2) IDD specifications are tested after the device is properly initialized and IDD parameter are specified with ODT disabled.
3) Definitions for IDD see Table 23
4) For two rank modules: for all active current measurements the other rank is in Precharge Power-Down Mode IDD2P
6)
5) For details and notes see the relevant Qimonda component data sheet
6) IDD1, IDD4R and IDD7 current measurements are defined with the outputs disabled (IOUT = 0 mA). To achieve this on module level the output
buffers can be disabled using an EMRS(1) (Extended Mode Register Command) by setting A12 bit to HIGH.
TABLE 23
Definitions for IDD
Parameter
Description
LOW
VIN ≤ VIL(ac).MAX, HIGH is defined as VIN ≥ VIH(ac).MIN
STABLE
Inputs are stable at a HIGH or LOW level
FLOATING
Inputs are VREF = VDDQ /2
SWITCHING
Inputs are changing between HIGH and LOW every other clock (once per 2 cycles) for address and control
signals, and inputs changing between HIGH and LOW every other data transfer (once per cycle) for DQ
signals not including mask or strobes
Rev. 1.3, 2006-12
03292006-6GMD-RSFT
36
Internet Data Sheet
HYS[64/72]T[32/64/128]xx0HU-[25F/2.5/3/3S/3.7/5]-B
Unbuffered DDR2 SDRAM Module
TABLE 24
IDD Specification for HYS[64/72]T[32/64/128]0x0HU-25F-B
860
960
mA
2)
60
110
130
mA
3)
410
460
820
920
mA
3)
180
360
410
720
810
mA
3)
160
310
350
620
700
mA
3)
40
70
80
140
160
mA
3)4)
240
480
540
960
1080
mA
3)5)
720
1240
1400
1300
1460
mA
2)
800
1240
1400
1300
1460
mA
2)
580
1160
1310
1220
1370
mA
2)
40
70
80
140
160
mA
3)6)
28
56
63
112
126
mA
3)6)
1060
1360
mA
2)
HYS72T128020HU–2.5F–B
2)
HYS64T128020HU–2.5F–B
mA
HYS72T64000HU–2.5F–B
820
HYS64T64000HU–2.5F–B
Note1)
HYS64T32000HU–2.5F–B
Unit
Product Type
Organization
256MB
512MB
512MB
1GB
1GB
1 Rank
1 Rank
1 Rank
2 Ranks
2 Ranks
×64
×64
×72
×64
×72
-25F
-25F
-25F
-25F
-25F
Symbol
Max.
Max.
Max.
Max.
Max.
IDD0
IDD1
IDD2P
IDD2N
IDD2Q
IDD3P( MRS = 0)
IDD3P( MRS = 1)
IDD3N
IDD4R
IDD4W
IDD5B
IDD5D
IDD6
IDD7
420
670
760
730
480
800
900
30
60
200
1530
1420
1590
1) Calculated values from component data. ODT disabled. IDD1, IDD4R, and IDD7, are defined with the outputs disabled.
2) The other rank is in IDD2P Precharge Power-Down Current mode
3) Both ranks are in the same IDDcurrent mode
4) Fast: MRS(12)=0
5) Slow: MRS(12)=1
6) IDD5D and IDD6 values are for 0°C ≤ TCase ≤ 85°C
Rev. 1.3, 2006-12
03292006-6GMD-RSFT
37
Internet Data Sheet
HYS[64/72]T[32/64/128]xx0HU-[25F/2.5/3/3S/3.7/5]-B
Unbuffered DDR2 SDRAM Module
TABLE 25
Product Type
HYS64T32000HU–2.5–B
HYS64T64000HU–2.5–B
HYS72T64000HU–2.5–B
HYS64T128020HU–2.5–B
HYS72T128020HU–2.5–B
IDD Specification for HYS[64/72]T[32/64/128]0x0HU-2.5-B
Organization
256MB
512MB
512MB
1GB
1GB
1 Rank
1 Rank
1 Rank
2 Ranks
2 Ranks
×64
×64
×72
×64
×72
-2.5
-2.5
-2.5
-2.5
-2.5
Symbol
Max.
Max.
Max.
Max.
Max.
IDD0
IDD1
IDD2P
IDD2N
IDD2Q
IDD3P( MRS = 0)
IDD3P( MRS = 1)
IDD3N
IDD4R
IDD4W
IDD5B
IDD5D
IDD6
IDD7
400
640
720
700
460
760
860
30
60
200
Unit
Note1)
780
mA
2)
820
920
mA
2)
60
110
130
mA
3)
410
460
820
920
mA
3)
180
360
410
720
810
mA
3)
160
310
350
620
700
mA
3)
40
70
80
140
160
mA
3)4)
240
480
540
960
1080
mA
3)5)
720
1240
1400
1300
1460
mA
2)
800
1240
1400
1300
1460
mA
2)
580
1160
1310
1220
1370
mA
2)
40
70
80
140
160
mA
3)6)
28
56
63
112
126
mA
3)6)
1020
1280
1440
1340
1500
mA
1) Calculated values from component data. ODT disabled. IDD1, IDD4R, and IDD7, are defined with the outputs disabled.
2) The other rank is in IDD2P Precharge Power-Down Current mode
3) Both ranks are in the same IDDcurrent mode
4) Fast: MRS(12)=0
5) Slow: MRS(12)=1
6) IDD5D and IDD6 values are for 0°C ≤ TCase ≤ 85°C
Rev. 1.3, 2006-12
03292006-6GMD-RSFT
38
2)
Internet Data Sheet
HYS[64/72]T[32/64/128]xx0HU-[25F/2.5/3/3S/3.7/5]-B
Unbuffered DDR2 SDRAM Module
TABLE 26
IDD Specification for HYS[64/72]T[32/64/128]0x0HU-3-B
780
870
mA
2)
60
110
130
mA
3)
360
410
720
810
mA
3)
160
320
360
640
720
mA
3)
130
260
300
530
590
mA
3)
40
70
80
140
160
mA
3)4)
200
400
450
800
900
mA
3)5)
620
1040
1170
1100
1230
mA
2)
680
1040
1170
1100
1230
mA
2)
560
1120
1260
1180
1320
mA
2)
40
70
80
140
160
mA
3)6)
28
56
63
112
126
mA
3)6)
1010
1280
mA
2)
HYS72T128020HU–3–B
2)
HYS64T128020HU–3–B
mA
HYS72T64000HU–3–B
740
HYS64T64000HU–3–B
Note1)
HYS64T32000HU–3–B
Unit
Product Type
Organization
256MB
512MB
512MB
1GB
1GB
1 Rank
1 Rank
1 Rank
2 Ranks
2 Ranks
×64
×64
×72
×64
×72
-3
-3
-3
-3
-3
Symbol
Max.
Max.
Max.
Max.
Max.
IDD0
IDD1
IDD2P
IDD2N
IDD2Q
IDD3P( MRS = 0)
IDD3P( MRS = 1)
IDD3N
IDD4R
IDD4W
IDD5B
IDD5D
IDD6
IDD7
380
600
680
660
420
720
810
30
60
180
1440
1340
1500
1) Calculated values from component data. ODT disabled. IDD1, IDD4R, and IDD7, are defined with the outputs disabled.
2) The other rank is in IDD2P Precharge Power-Down Current mode
3) Both ranks are in the same IDDcurrent mode
4) Fast: MRS(12)=0
5) Slow: MRS(12)=1
6) IDD5D and IDD6 values are for 0°C ≤ TCase ≤ 85°C
Rev. 1.3, 2006-12
03292006-6GMD-RSFT
39
Internet Data Sheet
HYS[64/72]T[32/64/128]xx0HU-[25F/2.5/3/3S/3.7/5]-B
Unbuffered DDR2 SDRAM Module
TABLE 27
IDD Specification for HYS[64/72]T[32/64/128]xx0HU-3S-B
740
830
mA
2)
60
110
130
mA
3)
360
410
720
810
mA
3)
160
320
360
640
720
mA
3)
130
260
300
530
590
mA
3)
40
70
80
140
160
mA
3)4)
200
400
450
800
900
mA
3)5)
620
1040
1170
1100
1230
mA
2)
680
1040
1170
1100
1230
mA
2)
560
1120
1260
1180
1320
mA
2)
40
70
80
140
160
mA
3)6)
28
56
63
112
126
mA
3)6)
960
1220
mA
2)
HYS72T128020HU–3S–B
2)
HYS64T128020HU–3S–B
HYS64T128920HU–3S–B
mA
HYS72T64000HU–3S–B
700
HYS64T64000HU–3S–B
HYS64T64900HU–3S–B
Note1)
HYS64T32000HU–3S–B
HYS64T32900HU–3S–B
Unit
Product Type
Organization
256MB
512MB
512MB
1GB
1GB
1 Rank
1 Rank
1 Rank
2 Ranks
2 Ranks
×64
×64
×72
×64
×72
-3S
-3S
-3S
-3S
-3S
Symbol
Max.
Max.
Max.
Max.
Max.
IDD0
IDD1
IDD2P
IDD2N
IDD2Q
IDD3P( MRS = 0)
IDD3P( MRS = 1)
IDD3N
IDD4R
IDD4W
IDD5B
IDD5D
IDD6
IDD7
360
570
640
620
400
680
770
30
60
180
1370
1270
1430
1) Calculated values from component data. ODT disabled. IDD1, IDD4R, and IDD7, are defined with the outputs disabled.
2) The other rank is in IDD2P Precharge Power-Down Current mode
3) Both ranks are in the same IDDcurrent mode
4) Fast: MRS(12)=0
5) Slow: MRS(12)=1
6) IDD5D and IDD6 values are for 0°C ≤ TCase ≤ 85°C
Rev. 1.3, 2006-12
03292006-6GMD-RSFT
40
Internet Data Sheet
HYS[64/72]T[32/64/128]xx0HU-[25F/2.5/3/3S/3.7/5]-B
Unbuffered DDR2 SDRAM Module
TABLE 28
Product Type
HYS64T32000HU–3.7–B
HYS64T32900HU–3.7–B
HYS64T64000HU–3.7–B
HYS64T64900HU–3.7–B
HYS72T64000HU–3.7–B
HYS64T128020HU–3.7–B
HYS64T128920HU–3.7–B
HYS72T128020HU–3.7–B
IDD Specification for HYS[64/72]T[32/64/128]xx0HU-3.7-B
Organization
256MB
512MB
512MB
1GB
1GB
1 Rank
1 Rank
1 Rank
2 Ranks
2 Ranks
×64
×64
×72
×64
×72
-3.7
-3.7
-3.7
-3.7
-3.7
Symbol
Max.
Max.
Max.
Max.
Max.
IDD0
IDD1
IDD2P
IDD2N
IDD2Q
IDD3P( MRS = 0)
IDD3P( MRS = 1)
IDD3N
IDD4R
IDD4W
IDD5B
IDD5D
IDD6
IDD7
320
520
590
580
360
600
680
30
60
150
Unit
Note1)
650
mA
2)
660
740
mA
2)
60
110
130
mA
3)
300
340
610
680
mA
3)
140
280
320
560
630
mA
3)
110
220
250
450
500
mA
3)
40
70
80
140
160
mA
3)4)
170
340
390
690
770
mA
3)5)
520
880
990
940
1050
mA
2)
580
880
990
940
1050
mA
2)
520
1040
1170
1100
1230
mA
2)
40
70
80
140
160
mA
3)6)
28
56
63
112
126
mA
3)6)
920
1160
mA
2)
1310
1220
1370
1) Calculated values from component data. ODT disabled. IDD1, IDD4R, and IDD7, are defined with the outputs disabled.
2) The other rank is in IDD2P Precharge Power-Down Current mode
3) Both ranks are in the same IDDcurrent mode
4) Fast: MRS(12)=0
5) Slow: MRS(12)=1
6) IDD5D and IDD6 values are for 0°C ≤ TCase ≤ 85°C
Rev. 1.3, 2006-12
03292006-6GMD-RSFT
41
Internet Data Sheet
HYS[64/72]T[32/64/128]xx0HU-[25F/2.5/3/3S/3.7/5]-B
Unbuffered DDR2 SDRAM Module
TABLE 29
IDD Specification for HYS[64/72]T[32/647128]0x0HU-5-B
620
690
mA
2)
60
110
130
mA
3)
270
310
540
610
mA
3)
130
260
290
510
580
mA
3)
100
190
220
380
430
mA
3)
40
70
80
140
160
mA
3)4)
160
310
350
620
700
mA
3)5)
460
760
860
820
920
mA
2)
520
760
860
820
920
mA
2)
500
1000
1130
1060
1190
mA
2)
40
70
80
140
160
mA
3)6)
28
56
63
112
126
mA
3)6)
880
1130
mA
2)
HYS72T128020HU–5–B
2)
HYS64T128020HU–5–B
mA
HYS72T64000HU–5–B
610
HYS64T64000HU–5–B
Note1)
HYS64T32000HU–5–B
Unit
Product Type
Organization
256MB
512MB
512MB
1GB
1GB
1 Rank
1 Rank
1 Rank
2 Ranks
2 Ranks
×64
×64
×72
×64
×72
-5
-5
-5
-5
-5
Symbol
Max.
Max.
Max.
Max.
Max.
IDD0
IDD1
IDD2P
IDD2N
IDD2Q
IDD3P( MRS = 0)
IDD3P( MRS = 1)
IDD3N
IDD4R
IDD4W
IDD5B
IDD5D
IDD6
IDD7
300
490
550
540
330
560
630
30
60
140
1270
1180
1330
1) Calculated values from component data. ODT disabled. IDD1, IDD4R, and IDD7, are defined with the outputs disabled.
2) The other rank is in IDD2P Precharge Power-Down Current mode
3) Both ranks are in the same IDDcurrent mode
4) Fast: MRS(12)=0
5) Slow: MRS(12)=1
6) IDD5D and IDD6 values are for 0°C ≤ TCase ≤ 85°C
Rev. 1.3, 2006-12
03292006-6GMD-RSFT
42
Internet Data Sheet
HYS[64/72]T[32/64/128]xx0HU-[25F/2.5/3/3S/3.7/5]-B
Unbuffered DDR2 SDRAM Module
4
SPD Codes
This chapter lists all hexadecimal byte values stored in the EEPROM of the products described in this data sheet. SPD stands
for serial presence detect. All values with XX in the table are module specific bytes which are defined during production.
List of SPD Code Tables
•
•
•
•
•
•
•
•
Table 30 “SPD Codes for HYS[64/72]T[32/64/128]xxxHU–25F–B” on Page 43
Table 31 “SPD Codes for HYS[64/72]T[32/64/128]xxxHU–2.5–B” on Page 48
Table 32 “SPD Codes for HYS[64/72]T[32/64/128]xxxHU–3–B” on Page 53
Table 33 “SPD Codes for HYS64T[32/64]x00HU–3S–B” on Page 58
Table 34 “SPD Codes for HYS[64/72]T[64/128]xx0HU–3S–B” on Page 62
Table 35 “SPD Codes for HYS64T[32/64]x00HU–3.7–B” on Page 66
Table 36 “SPD Codes for HYS[64/72]T[64/128]xx0HU–3.7–B” on Page 70
Table 37 “SPD Codes for HYS[64/72]T[32/64/128]xxxHU–5–B” on Page 74
TABLE 30
Product Type
HYS64T32000HU–25F–B
HYS64T64000HU–25F–B
HYS72T64000HU–25F–B
HYS64T128020HU–25F–B
HYS72T128020HU–25F–B
SPD Codes for HYS[64/72]T[32/64/128]xxxHU–25F–B
Organization
256MB
512MB
512MB
1 GByte
1 GByte
×64
×64
×72
×64
×72
1 Rank
(×16)
1 Rank
(×8)
1 Rank
(×8)
2 Ranks
(×8)
2 Ranks
(×8)
Label Code
PC2–
6400U–
555
PC2–
6400U–
555
PC2–
6400E–
555
PC2–
6400U–
555
PC2–
6400E–
555
JEDEC SPD Revision
Rev. 1.2
Rev. 1.2
Rev. 1.2
Rev. 1.2
Rev. 1.2
Byte#
Description
HEX
HEX
HEX
HEX
HEX
0
Programmed SPD Bytes in EEPROM
80
80
80
80
80
1
Total number of Bytes in EEPROM
08
08
08
08
08
2
Memory Type (DDR2)
08
08
08
08
08
3
Number of Row Addresses
0D
0E
0E
0E
0E
4
Number of Column Addresses
0A
0A
0A
0A
0A
5
DIMM Rank and Stacking Information
60
60
60
61
61
6
Data Width
40
40
48
40
48
Rev. 1.3, 2006-12
03292006-6GMD-RSFT
43
Internet Data Sheet
Product Type
HYS64T32000HU–25F–B
HYS64T64000HU–25F–B
HYS72T64000HU–25F–B
HYS64T128020HU–25F–B
HYS72T128020HU–25F–B
HYS[64/72]T[32/64/128]xx0HU-[25F/2.5/3/3S/3.7/5]-B
Unbuffered DDR2 SDRAM Module
Organization
256MB
512MB
512MB
1 GByte
1 GByte
×64
×64
×72
×64
×72
1 Rank
(×16)
1 Rank
(×8)
1 Rank
(×8)
2 Ranks
(×8)
2 Ranks
(×8)
Label Code
PC2–
6400U–
555
PC2–
6400U–
555
PC2–
6400E–
555
PC2–
6400U–
555
PC2–
6400E–
555
JEDEC SPD Revision
Rev. 1.2
Rev. 1.2
Rev. 1.2
Rev. 1.2
Rev. 1.2
Byte#
Description
HEX
HEX
HEX
HEX
HEX
7
Not used
00
00
00
00
00
8
Interface Voltage Level
05
05
05
05
05
9
25
25
25
25
25
10
tCK @ CLMAX (Byte 18) [ns]
tAC SDRAM @ CLMAX (Byte 18) [ns]
40
40
40
40
40
11
Error Correction Support (non-ECC, ECC)
00
00
02
00
02
12
Refresh Rate and Type
82
82
82
82
82
13
Primary SDRAM Width
10
08
08
08
08
14
Error Checking SDRAM Width
00
00
08
00
08
15
Not used
00
00
00
00
00
16
Burst Length Supported
0C
0C
0C
0C
0C
17
Number of Banks on SDRAM Device
04
04
04
04
04
18
Supported CAS Latencies
70
70
70
70
70
19
DIMM Mechanical Characteristics
01
01
01
01
01
20
DIMM Type Information
02
02
02
02
02
21
DIMM Attributes
00
00
00
00
00
22
Component Attributes
07
07
07
07
07
23
tCK @ CLMAX -1 (Byte 18) [ns]
tAC SDRAM @ CLMAX -1 [ns]
tCK @ CLMAX -2 (Byte 18) [ns]
tAC SDRAM @ CLMAX -2 [ns]
tRP.MIN [ns]
tRRD.MIN [ns]
tRCD.MIN [ns]
tRAS.MIN [ns]
25
25
25
25
25
40
40
40
40
40
3D
3D
3D
3D
3D
50
50
50
50
50
32
32
32
32
32
28
1E
1E
1E
1E
32
32
32
32
32
2D
2D
2D
2D
2D
24
25
26
27
28
29
30
Rev. 1.3, 2006-12
03292006-6GMD-RSFT
44
Internet Data Sheet
Product Type
HYS64T32000HU–25F–B
HYS64T64000HU–25F–B
HYS72T64000HU–25F–B
HYS64T128020HU–25F–B
HYS72T128020HU–25F–B
HYS[64/72]T[32/64/128]xx0HU-[25F/2.5/3/3S/3.7/5]-B
Unbuffered DDR2 SDRAM Module
Organization
256MB
512MB
512MB
1 GByte
1 GByte
×64
×64
×72
×64
×72
1 Rank
(×16)
1 Rank
(×8)
1 Rank
(×8)
2 Ranks
(×8)
2 Ranks
(×8)
Label Code
PC2–
6400U–
555
PC2–
6400U–
555
PC2–
6400E–
555
PC2–
6400U–
555
PC2–
6400E–
555
JEDEC SPD Revision
Rev. 1.2
Rev. 1.2
Rev. 1.2
Rev. 1.2
Rev. 1.2
Byte#
Description
HEX
HEX
HEX
HEX
HEX
31
Module Density per Rank
40
80
80
80
80
32
38
tAS.MIN and tCS.MIN [ns]
tAH.MIN and tCH.MIN [ns]
tDS.MIN [ns]
tDH.MIN [ns]
tWR.MIN [ns]
tWTR.MIN [ns]
tRTP.MIN [ns]
39
Analysis Characteristics
40
45
tRC and tRFC Extension
tRC.MIN [ns]
tRFC.MIN [ns]
tCK.MAX [ns]
tDQSQ.MAX [ns]
tQHS.MAX [ns]
1E
1E
1E
1E
1E
46
PLL Relock Time
00
00
00
00
00
47
TCASE.MAX Delta / ∆T4R4W Delta
56
50
50
50
50
48
Psi(T-A) DRAM
7A
7A
7A
7A
7A
49
∆T0 (DT0)
7F
5F
5F
5F
5F
50
∆T2N (DT2N, UDIMM) or ∆T2Q (DT2Q, RDIMM)
3B
3B
3B
3B
3B
51
∆T2P (DT2P)
36
36
36
36
36
52
∆T3N (DT3N)
2E
2E
2E
2E
2E
53
∆T3P.fast (DT3P fast)
5A
5A
5A
5A
5A
54
∆T3P.slow (DT3P slow)
2A
2A
2A
2A
2A
33
34
35
36
37
41
42
43
44
Rev. 1.3, 2006-12
03292006-6GMD-RSFT
45
17
17
17
17
17
25
25
25
25
25
05
05
05
05
05
12
12
12
12
12
3C
3C
3C
3C
3C
1E
1E
1E
1E
1E
1E
1E
1E
1E
1E
00
00
00
00
00
30
30
30
30
30
39
39
39
39
39
69
69
69
69
69
80
80
80
80
80
14
14
14
14
14
Internet Data Sheet
Product Type
HYS64T32000HU–25F–B
HYS64T64000HU–25F–B
HYS72T64000HU–25F–B
HYS64T128020HU–25F–B
HYS72T128020HU–25F–B
HYS[64/72]T[32/64/128]xx0HU-[25F/2.5/3/3S/3.7/5]-B
Unbuffered DDR2 SDRAM Module
Organization
256MB
512MB
512MB
1 GByte
1 GByte
×64
×64
×72
×64
×72
1 Rank
(×16)
1 Rank
(×8)
1 Rank
(×8)
2 Ranks
(×8)
2 Ranks
(×8)
Label Code
PC2–
6400U–
555
PC2–
6400U–
555
PC2–
6400E–
555
PC2–
6400U–
555
PC2–
6400E–
555
JEDEC SPD Revision
Rev. 1.2
Rev. 1.2
Rev. 1.2
Rev. 1.2
Rev. 1.2
Byte#
Description
HEX
HEX
HEX
HEX
HEX
55
∆T4R (DT4R) / ∆T4R4W Sign (DT4R4W)
68
5A
5A
5A
5A
56
∆T5B (DT5B)
22
22
22
22
22
57
∆T7 (DT7)
3D
27
27
27
27
58
Psi(ca) PLL
00
00
00
00
00
59
Psi(ca) REG
00
00
00
00
00
60
∆TPLL (DTPLL)
00
00
00
00
00
61
∆TREG (DTREG) / Toggle Rate
00
00
00
00
00
62
SPD Revision
12
12
12
12
12
63
Checksum of Bytes 0-62
52
37
49
38
4A
64
Manufacturer’s JEDEC ID Code (1)
7F
7F
7F
7F
7F
65
Manufacturer’s JEDEC ID Code (2)
7F
7F
7F
7F
7F
66
Manufacturer’s JEDEC ID Code (3)
7F
7F
7F
7F
7F
67
Manufacturer’s JEDEC ID Code (4)
7F
7F
7F
7F
7F
68
Manufacturer’s JEDEC ID Code (5)
7F
7F
7F
7F
7F
69
Manufacturer’s JEDEC ID Code (6)
51
51
51
51
51
70
Manufacturer’s JEDEC ID Code (7)
00
00
00
00
00
71
Manufacturer’s JEDEC ID Code (8)
00
00
00
00
00
72
Module Manufacturer Location
xx
xx
xx
xx
xx
73
Product Type, Char 1
36
36
37
36
37
74
Product Type, Char 2
34
34
32
34
32
75
Product Type, Char 3
54
54
54
54
54
76
Product Type, Char 4
33
36
36
31
31
77
Product Type, Char 5
32
34
34
32
32
78
Product Type, Char 6
30
30
30
38
38
Rev. 1.3, 2006-12
03292006-6GMD-RSFT
46
Internet Data Sheet
Product Type
HYS64T32000HU–25F–B
HYS64T64000HU–25F–B
HYS72T64000HU–25F–B
HYS64T128020HU–25F–B
HYS72T128020HU–25F–B
HYS[64/72]T[32/64/128]xx0HU-[25F/2.5/3/3S/3.7/5]-B
Unbuffered DDR2 SDRAM Module
Organization
256MB
512MB
512MB
1 GByte
1 GByte
×64
×64
×72
×64
×72
1 Rank
(×16)
1 Rank
(×8)
1 Rank
(×8)
2 Ranks
(×8)
2 Ranks
(×8)
Label Code
PC2–
6400U–
555
PC2–
6400U–
555
PC2–
6400E–
555
PC2–
6400U–
555
PC2–
6400E–
555
JEDEC SPD Revision
Rev. 1.2
Rev. 1.2
Rev. 1.2
Rev. 1.2
Rev. 1.2
Byte#
Description
HEX
HEX
HEX
HEX
HEX
79
Product Type, Char 7
30
30
30
30
30
80
Product Type, Char 8
30
30
30
32
32
81
Product Type, Char 9
48
48
48
30
30
82
Product Type, Char 10
55
55
55
48
48
83
Product Type, Char 11
32
32
32
55
55
84
Product Type, Char 12
35
35
35
32
32
85
Product Type, Char 13
46
46
46
35
35
86
Product Type, Char 14
42
42
42
46
46
87
Product Type, Char 15
20
20
20
42
42
88
Product Type, Char 16
20
20
20
20
20
89
Product Type, Char 17
20
20
20
20
20
90
Product Type, Char 18
20
20
20
20
20
91
Module Revision Code
3x
3x
3x
3x
3x
92
Test Program Revision Code
xx
xx
xx
xx
xx
93
Module Manufacturing Date Year
xx
xx
xx
xx
xx
94
Module Manufacturing Date Week
xx
xx
xx
xx
xx
95 - 98
Module Serial Number
xx
xx
xx
xx
xx
99 - 127 Not used
00
00
00
00
00
128 255
FF
FF
FF
FF
FF
Blank for customer use
Rev. 1.3, 2006-12
03292006-6GMD-RSFT
47
Internet Data Sheet
HYS[64/72]T[32/64/128]xx0HU-[25F/2.5/3/3S/3.7/5]-B
Unbuffered DDR2 SDRAM Module
TABLE 31
Product Type
HYS64T32000HU–2.5–B
HYS64T64000HU–2.5–B
HYS72T64000HU–2.5–B
HYS64T128020HU–2.5–B
HYS72T128020HU–2.5–B
SPD Codes for HYS[64/72]T[32/64/128]xxxHU–2.5–B
Organization
256MB
512MB
512MB
1 GByte
1 GByte
×64
×64
×72
×64
×72
1 Rank
(×16)
1 Rank
(×8)
1 Rank
(×8)
2 Ranks
(×8)
2 Ranks
(×8)
Label Code
PC2–
6400U–
666
PC2–
6400U–
666
PC2–
6400E–
666
PC2–
6400U–
666
PC2–
6400E–
666
JEDEC SPD Revision
Rev. 1.2
Rev. 1.2
Rev. 1.2
Rev. 1.2
Rev. 1.2
Byte#
Description
HEX
HEX
HEX
HEX
HEX
0
Programmed SPD Bytes in EEPROM
80
80
80
80
80
1
Total number of Bytes in EEPROM
08
08
08
08
08
2
Memory Type (DDR2)
08
08
08
08
08
3
Number of Row Addresses
0D
0E
0E
0E
0E
4
Number of Column Addresses
0A
0A
0A
0A
0A
5
DIMM Rank and Stacking Information
60
60
60
61
61
6
Data Width
40
40
48
40
48
7
Not used
00
00
00
00
00
8
Interface Voltage Level
05
05
05
05
05
9
25
25
25
25
25
10
tCK @ CLMAX (Byte 18) [ns]
tAC SDRAM @ CLMAX (Byte 18) [ns]
40
40
40
40
40
11
Error Correction Support (non-ECC, ECC)
00
00
02
00
02
12
Refresh Rate and Type
82
82
82
82
82
13
Primary SDRAM Width
10
08
08
08
08
14
Error Checking SDRAM Width
00
00
08
00
08
15
Not used
00
00
00
00
00
16
Burst Length Supported
0C
0C
0C
0C
0C
17
Number of Banks on SDRAM Device
04
04
04
04
04
18
Supported CAS Latencies
70
70
70
70
70
19
DIMM Mechanical Characteristics
01
01
01
01
01
20
DIMM Type Information
02
02
02
02
02
Rev. 1.3, 2006-12
03292006-6GMD-RSFT
48
Internet Data Sheet
Product Type
HYS64T32000HU–2.5–B
HYS64T64000HU–2.5–B
HYS72T64000HU–2.5–B
HYS64T128020HU–2.5–B
HYS72T128020HU–2.5–B
HYS[64/72]T[32/64/128]xx0HU-[25F/2.5/3/3S/3.7/5]-B
Unbuffered DDR2 SDRAM Module
Organization
256MB
512MB
512MB
1 GByte
1 GByte
×64
×64
×72
×64
×72
1 Rank
(×16)
1 Rank
(×8)
1 Rank
(×8)
2 Ranks
(×8)
2 Ranks
(×8)
Label Code
PC2–
6400U–
666
PC2–
6400U–
666
PC2–
6400E–
666
PC2–
6400U–
666
PC2–
6400E–
666
JEDEC SPD Revision
Rev. 1.2
Rev. 1.2
Rev. 1.2
Rev. 1.2
Rev. 1.2
Byte#
Description
HEX
HEX
HEX
HEX
HEX
21
DIMM Attributes
00
00
00
00
00
22
Component Attributes
07
07
07
07
07
23
30
30
30
30
30
45
45
45
45
45
30
tCK @ CLMAX -1 (Byte 18) [ns]
tAC SDRAM @ CLMAX -1 [ns]
tCK @ CLMAX -2 (Byte 18) [ns]
tAC SDRAM @ CLMAX -2 [ns]
tRP.MIN [ns]
tRRD.MIN [ns]
tRCD.MIN [ns]
tRAS.MIN [ns]
2D
2D
2D
2D
2D
31
Module Density per Rank
40
80
80
80
80
32
17
17
17
17
17
38
tAS.MIN and tCS.MIN [ns]
tAH.MIN and tCH.MIN [ns]
tDS.MIN [ns]
tDH.MIN [ns]
tWR.MIN [ns]
tWTR.MIN [ns]
tRTP.MIN [ns]
1E
1E
1E
1E
1E
39
Analysis Characteristics
00
00
00
00
00
40
tRC and tRFC Extension
tRC.MIN [ns]
tRFC.MIN [ns]
tCK.MAX [ns]
tDQSQ.MAX [ns]
00
00
00
00
00
24
25
26
27
28
29
33
34
35
36
37
41
42
43
44
Rev. 1.3, 2006-12
03292006-6GMD-RSFT
49
3D
3D
3D
3D
3D
50
50
50
50
50
3C
3C
3C
3C
3C
28
1E
1E
1E
1E
3C
3C
3C
3C
3C
25
25
25
25
25
05
05
05
05
05
12
12
12
12
12
3C
3C
3C
3C
3C
1E
1E
1E
1E
1E
3C
3C
3C
3C
3C
69
69
69
69
69
80
80
80
80
80
14
14
14
14
14
Internet Data Sheet
Product Type
HYS64T32000HU–2.5–B
HYS64T64000HU–2.5–B
HYS72T64000HU–2.5–B
HYS64T128020HU–2.5–B
HYS72T128020HU–2.5–B
HYS[64/72]T[32/64/128]xx0HU-[25F/2.5/3/3S/3.7/5]-B
Unbuffered DDR2 SDRAM Module
Organization
256MB
512MB
512MB
1 GByte
1 GByte
×64
×64
×72
×64
×72
1 Rank
(×16)
1 Rank
(×8)
1 Rank
(×8)
2 Ranks
(×8)
2 Ranks
(×8)
Label Code
PC2–
6400U–
666
PC2–
6400U–
666
PC2–
6400E–
666
PC2–
6400U–
666
PC2–
6400E–
666
JEDEC SPD Revision
Rev. 1.2
Rev. 1.2
Rev. 1.2
Rev. 1.2
Rev. 1.2
Byte#
Description
HEX
HEX
HEX
HEX
HEX
45
tQHS.MAX [ns]
1E
1E
1E
1E
1E
46
PLL Relock Time
00
00
00
00
00
47
TCASE.MAX Delta / ∆T4R4W Delta
55
50
50
50
50
48
Psi(T-A) DRAM
72
7A
7A
7A
7A
49
∆T0 (DT0)
6F
5B
5B
5B
5B
50
∆T2N (DT2N, UDIMM) or ∆T2Q (DT2Q, RDIMM)
37
3B
3B
3B
3B
51
∆T2P (DT2P)
33
36
36
36
36
52
∆T3N (DT3N)
2B
2E
2E
2E
2E
53
∆T3P.fast (DT3P fast)
54
5A
5A
5A
5A
54
∆T3P.slow (DT3P slow)
27
2A
2A
2A
2A
55
∆T4R (DT4R) / ∆T4R4W Sign (DT4R4W)
62
5A
5A
5A
5A
56
∆T5B (DT5B)
1F
22
22
22
22
57
∆T7 (DT7)
37
25
25
25
25
58
Psi(ca) PLL
00
00
00
00
00
59
Psi(ca) REG
00
00
00
00
00
60
∆TPLL (DTPLL)
00
00
00
00
00
61
∆TREG (DTREG) / Toggle Rate
00
00
00
00
00
62
SPD Revision
12
12
12
12
12
63
Checksum of Bytes 0-62
0E
28
3A
29
3B
64
Manufacturer’s JEDEC ID Code (1)
7F
7F
7F
7F
7F
65
Manufacturer’s JEDEC ID Code (2)
7F
7F
7F
7F
7F
66
Manufacturer’s JEDEC ID Code (3)
7F
7F
7F
7F
7F
67
Manufacturer’s JEDEC ID Code (4)
7F
7F
7F
7F
7F
68
Manufacturer’s JEDEC ID Code (5)
7F
7F
7F
7F
7F
Rev. 1.3, 2006-12
03292006-6GMD-RSFT
50
Internet Data Sheet
Product Type
HYS64T32000HU–2.5–B
HYS64T64000HU–2.5–B
HYS72T64000HU–2.5–B
HYS64T128020HU–2.5–B
HYS72T128020HU–2.5–B
HYS[64/72]T[32/64/128]xx0HU-[25F/2.5/3/3S/3.7/5]-B
Unbuffered DDR2 SDRAM Module
Organization
256MB
512MB
512MB
1 GByte
1 GByte
×64
×64
×72
×64
×72
1 Rank
(×16)
1 Rank
(×8)
1 Rank
(×8)
2 Ranks
(×8)
2 Ranks
(×8)
Label Code
PC2–
6400U–
666
PC2–
6400U–
666
PC2–
6400E–
666
PC2–
6400U–
666
PC2–
6400E–
666
JEDEC SPD Revision
Rev. 1.2
Rev. 1.2
Rev. 1.2
Rev. 1.2
Rev. 1.2
Byte#
Description
HEX
HEX
HEX
HEX
HEX
69
Manufacturer’s JEDEC ID Code (6)
51
51
51
51
51
70
Manufacturer’s JEDEC ID Code (7)
00
00
00
00
00
71
Manufacturer’s JEDEC ID Code (8)
00
00
00
00
00
72
Module Manufacturer Location
xx
xx
xx
xx
xx
73
Product Type, Char 1
36
36
37
36
37
74
Product Type, Char 2
34
34
32
34
32
75
Product Type, Char 3
54
54
54
54
54
76
Product Type, Char 4
33
36
36
31
31
77
Product Type, Char 5
32
34
34
32
32
78
Product Type, Char 6
30
30
30
38
38
79
Product Type, Char 7
30
30
30
30
30
80
Product Type, Char 8
30
30
30
32
32
81
Product Type, Char 9
48
48
48
30
30
82
Product Type, Char 10
55
55
55
48
48
83
Product Type, Char 11
32
32
32
55
55
84
Product Type, Char 12
2E
2E
2E
32
32
85
Product Type, Char 13
35
35
35
2E
2E
86
Product Type, Char 14
42
42
42
35
35
87
Product Type, Char 15
20
20
20
42
42
88
Product Type, Char 16
20
20
20
20
20
89
Product Type, Char 17
20
20
20
20
20
90
Product Type, Char 18
20
20
20
20
20
91
Module Revision Code
4x
4x
4x
4x
4x
92
Test Program Revision Code
xx
xx
xx
xx
xx
Rev. 1.3, 2006-12
03292006-6GMD-RSFT
51
Internet Data Sheet
Product Type
HYS64T32000HU–2.5–B
HYS64T64000HU–2.5–B
HYS72T64000HU–2.5–B
HYS64T128020HU–2.5–B
HYS72T128020HU–2.5–B
HYS[64/72]T[32/64/128]xx0HU-[25F/2.5/3/3S/3.7/5]-B
Unbuffered DDR2 SDRAM Module
Organization
256MB
512MB
512MB
1 GByte
1 GByte
×64
×64
×72
×64
×72
1 Rank
(×16)
1 Rank
(×8)
1 Rank
(×8)
2 Ranks
(×8)
2 Ranks
(×8)
Label Code
PC2–
6400U–
666
PC2–
6400U–
666
PC2–
6400E–
666
PC2–
6400U–
666
PC2–
6400E–
666
JEDEC SPD Revision
Rev. 1.2
Rev. 1.2
Rev. 1.2
Rev. 1.2
Rev. 1.2
Byte#
Description
HEX
HEX
HEX
HEX
HEX
93
Module Manufacturing Date Year
xx
xx
xx
xx
xx
94
Module Manufacturing Date Week
xx
xx
xx
xx
xx
95 - 98
Module Serial Number
xx
xx
xx
xx
xx
99 - 127 Not used
00
00
00
00
00
128 255
FF
FF
FF
FF
FF
Blank for customer use
Rev. 1.3, 2006-12
03292006-6GMD-RSFT
52
Internet Data Sheet
HYS[64/72]T[32/64/128]xx0HU-[25F/2.5/3/3S/3.7/5]-B
Unbuffered DDR2 SDRAM Module
TABLE 32
Product Type
HYS64T32000HU–3–B
HYS64T64000HU–3–B
HYS72T64000HU–3–B
HYS64T128020HU–3–B
HYS72T128020HU–3–B
SPD Codes for HYS[64/72]T[32/64/128]xxxHU–3–B
Organization
256MB
512MB
512MB
1 GByte
1 GByte
×64
×64
×72
×64
×72
1 Rank
(×16)
1 Rank
(×8)
1 Rank
(×8)
2 Ranks
(×8)
2 Ranks
(×8)
Label Code
PC2–
5300U–
444
PC2–
5300U–
444
PC2–
5300E–
444
PC2–
5300U–
444
PC2–
5300E–
444
JEDEC SPD Revision
Rev. 1.2
Rev. 1.2
Rev. 1.2
Rev. 1.2
Rev. 1.2
Byte#
Description
HEX
HEX
HEX
HEX
HEX
0
Programmed SPD Bytes in EEPROM
80
80
80
80
80
1
Total number of Bytes in EEPROM
08
08
08
08
08
2
Memory Type (DDR2)
08
08
08
08
08
3
Number of Row Addresses
0D
0E
0E
0E
0E
4
Number of Column Addresses
0A
0A
0A
0A
0A
5
DIMM Rank and Stacking Information
60
60
60
61
61
6
Data Width
40
40
48
40
48
7
Not used
00
00
00
00
00
8
Interface Voltage Level
05
05
05
05
05
9
tCK @ CLMAX (Byte 18) [ns]
tAC SDRAM @ CLMAX (Byte 18) [ns]
30
30
30
30
30
45
45
45
45
45
11
Error Correction Support (non-ECC, ECC)
00
00
02
00
02
12
Refresh Rate and Type
82
82
82
82
82
13
Primary SDRAM Width
10
08
08
08
08
14
Error Checking SDRAM Width
00
00
08
00
08
15
Not used
00
00
00
00
00
16
Burst Length Supported
0C
0C
0C
0C
0C
17
Number of Banks on SDRAM Device
04
04
04
04
04
18
Supported CAS Latencies
38
38
38
38
38
19
DIMM Mechanical Characteristics
01
01
01
01
01
20
DIMM Type Information
02
02
02
02
02
21
DIMM Attributes
00
00
00
00
00
10
Rev. 1.3, 2006-12
03292006-6GMD-RSFT
53
Internet Data Sheet
Product Type
HYS64T32000HU–3–B
HYS64T64000HU–3–B
HYS72T64000HU–3–B
HYS64T128020HU–3–B
HYS72T128020HU–3–B
HYS[64/72]T[32/64/128]xx0HU-[25F/2.5/3/3S/3.7/5]-B
Unbuffered DDR2 SDRAM Module
Organization
256MB
512MB
512MB
1 GByte
1 GByte
×64
×64
×72
×64
×72
1 Rank
(×16)
1 Rank
(×8)
1 Rank
(×8)
2 Ranks
(×8)
2 Ranks
(×8)
Label Code
PC2–
5300U–
444
PC2–
5300U–
444
PC2–
5300E–
444
PC2–
5300U–
444
PC2–
5300E–
444
JEDEC SPD Revision
Rev. 1.2
Rev. 1.2
Rev. 1.2
Rev. 1.2
Rev. 1.2
Byte#
Description
HEX
HEX
HEX
HEX
HEX
22
Component Attributes
07
07
07
07
07
23
30
30
30
30
30
45
45
45
45
45
50
50
50
50
50
60
60
60
60
60
30
tCK @ CLMAX -1 (Byte 18) [ns]
tAC SDRAM @ CLMAX -1 [ns]
tCK @ CLMAX -2 (Byte 18) [ns]
tAC SDRAM @ CLMAX -2 [ns]
tRP.MIN [ns]
tRRD.MIN [ns]
tRCD.MIN [ns]
tRAS.MIN [ns]
31
Module Density per Rank
32
38
tAS.MIN and tCS.MIN [ns]
tAH.MIN and tCH.MIN [ns]
tDS.MIN [ns]
tDH.MIN [ns]
tWR.MIN [ns]
tWTR.MIN [ns]
tRTP.MIN [ns]
39
Analysis Characteristics
40
tRC and tRFC Extension
tRC.MIN [ns]
tRFC.MIN [ns]
tCK.MAX [ns]
tDQSQ.MAX [ns]
tQHS.MAX [ns]
24
25
26
27
28
29
33
34
35
36
37
41
42
43
44
45
Rev. 1.3, 2006-12
03292006-6GMD-RSFT
54
30
30
30
30
30
28
1E
1E
1E
1E
30
30
30
30
30
2D
2D
2D
2D
2D
40
80
80
80
80
20
20
20
20
20
27
27
27
27
27
10
10
10
10
10
17
17
17
17
17
3C
3C
3C
3C
3C
1E
1E
1E
1E
1E
1E
1E
1E
1E
1E
00
00
00
00
00
00
00
00
00
00
39
39
39
39
39
69
69
69
69
69
80
80
80
80
80
18
18
18
18
18
22
22
22
22
22
Internet Data Sheet
Product Type
HYS64T32000HU–3–B
HYS64T64000HU–3–B
HYS72T64000HU–3–B
HYS64T128020HU–3–B
HYS72T128020HU–3–B
HYS[64/72]T[32/64/128]xx0HU-[25F/2.5/3/3S/3.7/5]-B
Unbuffered DDR2 SDRAM Module
Organization
256MB
512MB
512MB
1 GByte
1 GByte
×64
×64
×72
×64
×72
1 Rank
(×16)
1 Rank
(×8)
1 Rank
(×8)
2 Ranks
(×8)
2 Ranks
(×8)
Label Code
PC2–
5300U–
444
PC2–
5300U–
444
PC2–
5300E–
444
PC2–
5300U–
444
PC2–
5300E–
444
JEDEC SPD Revision
Rev. 1.2
Rev. 1.2
Rev. 1.2
Rev. 1.2
Rev. 1.2
Byte#
Description
HEX
HEX
HEX
HEX
HEX
46
PLL Relock Time
00
00
00
00
00
47
TCASE.MAX Delta / ∆T4R4W Delta
54
50
50
50
50
48
Psi(T-A) DRAM
72
7A
7A
7A
7A
49
∆T0 (DT0)
67
53
53
53
53
50
∆T2N (DT2N, UDIMM) or ∆T2Q (DT2Q, RDIMM)
31
34
34
34
34
51
∆T2P (DT2P)
33
36
36
36
36
52
∆T3N (DT3N)
24
27
27
27
27
53
∆T3P.fast (DT3P fast)
47
4C
4C
4C
4C
54
∆T3P.slow (DT3P slow)
27
2A
2A
2A
2A
55
∆T4R (DT4R) / ∆T4R4W Sign (DT4R4W)
54
4C
4C
4C
4C
56
∆T5B (DT5B)
1E
20
20
20
20
57
∆T7 (DT7)
37
25
25
25
25
58
Psi(ca) PLL
00
00
00
00
00
59
Psi(ca) REG
00
00
00
00
00
60
∆TPLL (DTPLL)
00
00
00
00
00
61
∆TREG (DTREG) / Toggle Rate
00
00
00
00
00
62
SPD Revision
12
12
12
12
12
63
Checksum of Bytes 0-62
DF
F7
09
F8
0A
64
Manufacturer’s JEDEC ID Code (1)
7F
7F
7F
7F
7F
65
Manufacturer’s JEDEC ID Code (2)
7F
7F
7F
7F
7F
66
Manufacturer’s JEDEC ID Code (3)
7F
7F
7F
7F
7F
67
Manufacturer’s JEDEC ID Code (4)
7F
7F
7F
7F
7F
68
Manufacturer’s JEDEC ID Code (5)
7F
7F
7F
7F
7F
69
Manufacturer’s JEDEC ID Code (6)
51
51
51
51
51
Rev. 1.3, 2006-12
03292006-6GMD-RSFT
55
Internet Data Sheet
Product Type
HYS64T32000HU–3–B
HYS64T64000HU–3–B
HYS72T64000HU–3–B
HYS64T128020HU–3–B
HYS72T128020HU–3–B
HYS[64/72]T[32/64/128]xx0HU-[25F/2.5/3/3S/3.7/5]-B
Unbuffered DDR2 SDRAM Module
Organization
256MB
512MB
512MB
1 GByte
1 GByte
×64
×64
×72
×64
×72
1 Rank
(×16)
1 Rank
(×8)
1 Rank
(×8)
2 Ranks
(×8)
2 Ranks
(×8)
Label Code
PC2–
5300U–
444
PC2–
5300U–
444
PC2–
5300E–
444
PC2–
5300U–
444
PC2–
5300E–
444
JEDEC SPD Revision
Rev. 1.2
Rev. 1.2
Rev. 1.2
Rev. 1.2
Rev. 1.2
Byte#
Description
HEX
HEX
HEX
HEX
HEX
70
Manufacturer’s JEDEC ID Code (7)
00
00
00
00
00
71
Manufacturer’s JEDEC ID Code (8)
00
00
00
00
00
72
Module Manufacturer Location
xx
xx
xx
xx
xx
73
Product Type, Char 1
36
36
37
36
37
74
Product Type, Char 2
34
34
32
34
32
75
Product Type, Char 3
54
54
54
54
54
76
Product Type, Char 4
33
36
36
31
31
77
Product Type, Char 5
32
34
34
32
32
78
Product Type, Char 6
30
30
30
38
38
79
Product Type, Char 7
30
30
30
30
30
80
Product Type, Char 8
30
30
30
32
32
81
Product Type, Char 9
48
48
48
30
30
82
Product Type, Char 10
55
55
55
48
48
83
Product Type, Char 11
33
33
33
55
55
84
Product Type, Char 12
42
42
42
33
33
85
Product Type, Char 13
20
20
20
42
42
86
Product Type, Char 14
20
20
20
20
20
87
Product Type, Char 15
20
20
20
20
20
88
Product Type, Char 16
20
20
20
20
20
89
Product Type, Char 17
20
20
20
20
20
90
Product Type, Char 18
20
20
20
20
20
91
Module Revision Code
3x
4x
4x
4x
4x
92
Test Program Revision Code
xx
xx
xx
xx
xx
93
Module Manufacturing Date Year
xx
xx
xx
xx
xx
Rev. 1.3, 2006-12
03292006-6GMD-RSFT
56
Internet Data Sheet
Product Type
HYS64T32000HU–3–B
HYS64T64000HU–3–B
HYS72T64000HU–3–B
HYS64T128020HU–3–B
HYS72T128020HU–3–B
HYS[64/72]T[32/64/128]xx0HU-[25F/2.5/3/3S/3.7/5]-B
Unbuffered DDR2 SDRAM Module
Organization
256MB
512MB
512MB
1 GByte
1 GByte
×64
×64
×72
×64
×72
1 Rank
(×16)
1 Rank
(×8)
1 Rank
(×8)
2 Ranks
(×8)
2 Ranks
(×8)
Label Code
PC2–
5300U–
444
PC2–
5300U–
444
PC2–
5300E–
444
PC2–
5300U–
444
PC2–
5300E–
444
JEDEC SPD Revision
Rev. 1.2
Rev. 1.2
Rev. 1.2
Rev. 1.2
Rev. 1.2
Byte#
Description
HEX
HEX
HEX
HEX
HEX
94
Module Manufacturing Date Week
xx
xx
xx
xx
xx
95 - 98
Module Serial Number
xx
xx
xx
xx
xx
99 - 127 Not used
00
00
00
00
00
128 255
FF
FF
FF
FF
FF
Blank for customer use
Rev. 1.3, 2006-12
03292006-6GMD-RSFT
57
Internet Data Sheet
HYS[64/72]T[32/64/128]xx0HU-[25F/2.5/3/3S/3.7/5]-B
Unbuffered DDR2 SDRAM Module
TABLE 33
Product Type
HYS64T32000HU–3S–B
HYS64T32900HU–3S–B
HYS64T64000HU–3S–B
HYS64T64900HU–3S–B
SPD Codes for HYS64T[32/64]x00HU–3S–B
Organization
256MB
256MB
512MB
512MB
×64
×64
×64
×64
1 Rank (×16) 1 Rank (×16) 1 Rank (×8)
1 Rank (×8)
Label Code
PC2–
5300U–555
PC2–
5300U–555
PC2–
5300U–555
PC2–
5300U–555
JEDEC SPD Revision
Rev. 1.2
Rev. 1.2
Rev. 1.2
Rev. 1.2
Byte#
Description
HEX
HEX
HEX
HEX
0
Programmed SPD Bytes in EEPROM
80
80
80
80
1
Total number of Bytes in EEPROM
08
08
08
08
2
Memory Type (DDR2)
08
08
08
08
3
Number of Row Addresses
0D
0D
0E
0E
4
Number of Column Addresses
0A
0A
0A
0A
5
DIMM Rank and Stacking Information
60
60
60
60
6
Data Width
40
40
40
40
7
Not used
00
00
00
00
8
Interface Voltage Level
05
05
05
05
9
30
30
30
30
10
tCK @ CLMAX (Byte 18) [ns]
tAC SDRAM @ CLMAX (Byte 18) [ns]
45
45
45
45
11
Error Correction Support (non-ECC, ECC)
00
00
00
00
12
Refresh Rate and Type
82
82
82
82
13
Primary SDRAM Width
10
10
08
08
14
Error Checking SDRAM Width
00
00
00
00
15
Not used
00
00
00
00
16
Burst Length Supported
0C
0C
0C
0C
17
Number of Banks on SDRAM Device
04
04
04
04
18
Supported CAS Latencies
38
38
38
38
19
DIMM Mechanical Characteristics
01
01
01
01
20
DIMM Type Information
02
02
02
02
21
DIMM Attributes
00
00
00
00
22
Component Attributes
07
07
07
07
Rev. 1.3, 2006-12
03292006-6GMD-RSFT
58
Internet Data Sheet
Product Type
HYS64T32000HU–3S–B
HYS64T32900HU–3S–B
HYS64T64000HU–3S–B
HYS64T64900HU–3S–B
HYS[64/72]T[32/64/128]xx0HU-[25F/2.5/3/3S/3.7/5]-B
Unbuffered DDR2 SDRAM Module
Organization
256MB
256MB
512MB
512MB
×64
×64
×64
×64
1 Rank (×16) 1 Rank (×16) 1 Rank (×8)
1 Rank (×8)
Label Code
PC2–
5300U–555
PC2–
5300U–555
PC2–
5300U–555
PC2–
5300U–555
JEDEC SPD Revision
Rev. 1.2
Rev. 1.2
Rev. 1.2
Rev. 1.2
Byte#
Description
HEX
HEX
HEX
HEX
23
3D
3D
3D
3D
50
50
50
50
50
50
50
50
60
60
60
60
30
tCK @ CLMAX -1 (Byte 18) [ns]
tAC SDRAM @ CLMAX -1 [ns]
tCK @ CLMAX -2 (Byte 18) [ns]
tAC SDRAM @ CLMAX -2 [ns]
tRP.MIN [ns]
tRRD.MIN [ns]
tRCD.MIN [ns]
tRAS.MIN [ns]
31
Module Density per Rank
32
38
tAS.MIN and tCS.MIN [ns]
tAH.MIN and tCH.MIN [ns]
tDS.MIN [ns]
tDH.MIN [ns]
tWR.MIN [ns]
tWTR.MIN [ns]
tRTP.MIN [ns]
39
Analysis Characteristics
40
45
tRC and tRFC Extension
tRC.MIN [ns]
tRFC.MIN [ns]
tCK.MAX [ns]
tDQSQ.MAX [ns]
tQHS.MAX [ns]
22
22
22
22
46
PLL Relock Time
00
00
00
00
47
TCASE.MAX Delta / ∆T4R4W Delta
54
54
50
50
48
Psi(T-A) DRAM
72
72
7A
7A
24
25
26
27
28
29
33
34
35
36
37
41
42
43
44
Rev. 1.3, 2006-12
03292006-6GMD-RSFT
59
3C
3C
3C
3C
28
28
1E
1E
3C
3C
3C
3C
2D
2D
2D
2D
40
40
80
80
20
20
20
20
27
27
27
27
10
10
10
10
17
17
17
17
3C
3C
3C
3C
1E
1E
1E
1E
1E
1E
1E
1E
00
00
00
00
00
00
00
00
3C
3C
3C
3C
69
69
69
69
80
80
80
80
18
18
18
18
Internet Data Sheet
Product Type
HYS64T32000HU–3S–B
HYS64T32900HU–3S–B
HYS64T64000HU–3S–B
HYS64T64900HU–3S–B
HYS[64/72]T[32/64/128]xx0HU-[25F/2.5/3/3S/3.7/5]-B
Unbuffered DDR2 SDRAM Module
Organization
256MB
256MB
512MB
512MB
×64
×64
×64
×64
1 Rank (×16) 1 Rank (×16) 1 Rank (×8)
1 Rank (×8)
Label Code
PC2–
5300U–555
PC2–
5300U–555
PC2–
5300U–555
PC2–
5300U–555
JEDEC SPD Revision
Rev. 1.2
Rev. 1.2
Rev. 1.2
Rev. 1.2
Byte#
Description
HEX
HEX
HEX
HEX
49
∆T0 (DT0)
5F
5F
4B
4B
50
∆T2N (DT2N, UDIMM) or ∆T2Q (DT2Q, RDIMM)
31
31
34
34
51
∆T2P (DT2P)
33
33
36
36
52
∆T3N (DT3N)
24
24
27
27
53
∆T3P.fast (DT3P fast)
47
47
4C
4C
54
∆T3P.slow (DT3P slow)
27
27
2A
2A
55
∆T4R (DT4R) / ∆T4R4W Sign (DT4R4W)
54
54
4C
4C
56
∆T5B (DT5B)
1E
1E
20
20
57
∆T7 (DT7)
34
34
23
23
58
Psi(ca) PLL
00
00
00
00
59
Psi(ca) REG
00
00
00
00
60
∆TPLL (DTPLL)
00
00
00
00
61
∆TREG (DTREG) / Toggle Rate
00
00
00
00
62
SPD Revision
12
12
12
12
63
Checksum of Bytes 0-62
07
07
20
20
64
Manufacturer’s JEDEC ID Code (1)
7F
7F
7F
7F
65
Manufacturer’s JEDEC ID Code (2)
7F
7F
7F
7F
66
Manufacturer’s JEDEC ID Code (3)
7F
7F
7F
7F
67
Manufacturer’s JEDEC ID Code (4)
7F
7F
7F
7F
68
Manufacturer’s JEDEC ID Code (5)
7F
7F
7F
7F
69
Manufacturer’s JEDEC ID Code (6)
51
51
51
51
70
Manufacturer’s JEDEC ID Code (7)
00
00
00
00
71
Manufacturer’s JEDEC ID Code (8)
00
00
00
00
72
Module Manufacturer Location
xx
xx
xx
xx
73
Product Type, Char 1
36
36
36
36
74
Product Type, Char 2
34
34
34
34
Rev. 1.3, 2006-12
03292006-6GMD-RSFT
60
Internet Data Sheet
Product Type
HYS64T32000HU–3S–B
HYS64T32900HU–3S–B
HYS64T64000HU–3S–B
HYS64T64900HU–3S–B
HYS[64/72]T[32/64/128]xx0HU-[25F/2.5/3/3S/3.7/5]-B
Unbuffered DDR2 SDRAM Module
Organization
256MB
256MB
512MB
512MB
×64
×64
×64
×64
1 Rank (×16) 1 Rank (×16) 1 Rank (×8)
1 Rank (×8)
Label Code
PC2–
5300U–555
PC2–
5300U–555
PC2–
5300U–555
PC2–
5300U–555
JEDEC SPD Revision
Rev. 1.2
Rev. 1.2
Rev. 1.2
Rev. 1.2
Byte#
Description
HEX
HEX
HEX
HEX
75
Product Type, Char 3
54
54
54
54
76
Product Type, Char 4
33
33
36
36
77
Product Type, Char 5
32
32
34
34
78
Product Type, Char 6
30
39
30
39
79
Product Type, Char 7
30
30
30
30
80
Product Type, Char 8
30
30
30
30
81
Product Type, Char 9
48
48
48
48
82
Product Type, Char 10
55
55
55
55
83
Product Type, Char 11
33
33
33
33
84
Product Type, Char 12
53
53
53
53
85
Product Type, Char 13
42
42
42
42
86
Product Type, Char 14
20
20
20
20
87
Product Type, Char 15
20
20
20
20
88
Product Type, Char 16
20
20
20
20
89
Product Type, Char 17
20
20
20
20
90
Product Type, Char 18
20
20
20
20
91
Module Revision Code
4x
2x
4x
2x
92
Test Program Revision Code
xx
xx
xx
xx
93
Module Manufacturing Date Year
xx
xx
xx
xx
94
Module Manufacturing Date Week
xx
xx
xx
xx
95 - 98
Module Serial Number
xx
xx
xx
xx
99 - 127 Not used
00
00
00
00
128 255
FF
FF
FF
FF
Blank for customer use
Rev. 1.3, 2006-12
03292006-6GMD-RSFT
61
Internet Data Sheet
HYS[64/72]T[32/64/128]xx0HU-[25F/2.5/3/3S/3.7/5]-B
Unbuffered DDR2 SDRAM Module
TABLE 34
Product Type
HYS72T64000HU–3S–B
HYS64T128020HU–3S–B
HYS64T128920HU–3S–B
HYS72T128020HU–3S–B
SPD Codes for HYS[64/72]T[64/128]xx0HU–3S–B
Organization
512MB
1 GByte
1 GByte
1 GByte
×72
×64
×64
×72
1 Rank (×8)
2 Ranks (×8) 2 Ranks (×8) 2 Ranks (×8)
Label Code
PC2–
5300E–555
PC2–
5300U–555
PC2–
5300U–555
PC2–
5300E–555
JEDEC SPD Revision
Rev. 1.2
Rev. 1.2
Rev. 1.2
Rev. 1.2
Byte#
HEX
HEX
HEX
HEX
Description
0
Programmed SPD Bytes in EEPROM
80
80
80
80
1
Total number of Bytes in EEPROM
08
08
08
08
2
Memory Type (DDR2)
08
08
08
08
3
Number of Row Addresses
0E
0E
0E
0E
4
Number of Column Addresses
0A
0A
0A
0A
5
DIMM Rank and Stacking Information
60
61
61
61
6
Data Width
48
40
40
48
7
Not used
00
00
00
00
8
Interface Voltage Level
05
05
05
05
9
tCK @ CLMAX (Byte 18) [ns]
tAC SDRAM @ CLMAX (Byte 18) [ns]
30
30
30
30
45
45
45
45
11
Error Correction Support (non-ECC, ECC)
02
00
00
02
12
Refresh Rate and Type
82
82
82
82
13
Primary SDRAM Width
08
08
08
08
14
Error Checking SDRAM Width
08
00
00
08
15
Not used
00
00
00
00
16
Burst Length Supported
0C
0C
0C
0C
17
Number of Banks on SDRAM Device
04
04
04
04
18
Supported CAS Latencies
38
38
38
38
19
DIMM Mechanical Characteristics
01
01
01
01
20
DIMM Type Information
02
02
02
02
21
DIMM Attributes
00
00
00
00
22
Component Attributes
07
07
07
07
10
Rev. 1.3, 2006-12
03292006-6GMD-RSFT
62
Internet Data Sheet
Product Type
HYS72T64000HU–3S–B
HYS64T128020HU–3S–B
HYS64T128920HU–3S–B
HYS72T128020HU–3S–B
HYS[64/72]T[32/64/128]xx0HU-[25F/2.5/3/3S/3.7/5]-B
Unbuffered DDR2 SDRAM Module
Organization
512MB
1 GByte
1 GByte
1 GByte
×72
×64
×64
×72
1 Rank (×8)
2 Ranks (×8) 2 Ranks (×8) 2 Ranks (×8)
Label Code
PC2–
5300E–555
PC2–
5300U–555
PC2–
5300U–555
PC2–
5300E–555
JEDEC SPD Revision
Rev. 1.2
Rev. 1.2
Rev. 1.2
Rev. 1.2
Byte#
Description
HEX
HEX
HEX
HEX
23
3D
3D
3D
3D
50
50
50
50
30
tCK @ CLMAX -1 (Byte 18) [ns]
tAC SDRAM @ CLMAX -1 [ns]
tCK @ CLMAX -2 (Byte 18) [ns]
tAC SDRAM @ CLMAX -2 [ns]
tRP.MIN [ns]
tRRD.MIN [ns]
tRCD.MIN [ns]
tRAS.MIN [ns]
2D
2D
2D
2D
31
Module Density per Rank
80
80
80
80
32
20
20
20
20
38
tAS.MIN and tCS.MIN [ns]
tAH.MIN and tCH.MIN [ns]
tDS.MIN [ns]
tDH.MIN [ns]
tWR.MIN [ns]
tWTR.MIN [ns]
tRTP.MIN [ns]
1E
1E
1E
1E
39
Analysis Characteristics
00
00
00
00
40
tRC and tRFC Extension
tRC.MIN [ns]
tRFC.MIN [ns]
tCK.MAX [ns]
tDQSQ.MAX [ns]
tQHS.MAX [ns]
00
00
00
00
24
25
26
27
28
29
33
34
35
36
37
41
42
43
44
45
50
50
50
50
60
60
60
60
3C
3C
3C
3C
1E
1E
1E
1E
3C
3C
3C
3C
27
27
27
27
10
10
10
10
17
17
17
17
3C
3C
3C
3C
1E
1E
1E
1E
3C
3C
3C
3C
69
69
69
69
80
80
80
80
18
18
18
18
22
22
22
22
46
PLL Relock Time
00
00
00
00
47
TCASE.MAX Delta / ∆T4R4W Delta
50
50
50
50
48
Psi(T-A) DRAM
7A
7A
7A
7A
Rev. 1.3, 2006-12
03292006-6GMD-RSFT
63
Internet Data Sheet
Product Type
HYS72T64000HU–3S–B
HYS64T128020HU–3S–B
HYS64T128920HU–3S–B
HYS72T128020HU–3S–B
HYS[64/72]T[32/64/128]xx0HU-[25F/2.5/3/3S/3.7/5]-B
Unbuffered DDR2 SDRAM Module
Organization
512MB
1 GByte
1 GByte
1 GByte
×72
×64
×64
×72
1 Rank (×8)
2 Ranks (×8) 2 Ranks (×8) 2 Ranks (×8)
Label Code
PC2–
5300E–555
PC2–
5300U–555
PC2–
5300U–555
PC2–
5300E–555
JEDEC SPD Revision
Rev. 1.2
Rev. 1.2
Rev. 1.2
Rev. 1.2
Byte#
Description
HEX
HEX
HEX
HEX
49
∆T0 (DT0)
4B
4B
4B
4B
50
∆T2N (DT2N, UDIMM) or ∆T2Q (DT2Q, RDIMM)
34
34
34
34
51
∆T2P (DT2P)
36
36
36
36
52
∆T3N (DT3N)
27
27
27
27
53
∆T3P.fast (DT3P fast)
4C
4C
4C
4C
54
∆T3P.slow (DT3P slow)
2A
2A
2A
2A
55
∆T4R (DT4R) / ∆T4R4W Sign (DT4R4W)
4C
4C
4C
4C
56
∆T5B (DT5B)
20
20
20
20
57
∆T7 (DT7)
23
23
23
23
58
Psi(ca) PLL
00
00
00
00
59
Psi(ca) REG
00
00
00
00
60
∆TPLL (DTPLL)
00
00
00
00
61
∆TREG (DTREG) / Toggle Rate
00
00
00
00
62
SPD Revision
12
12
12
12
63
Checksum of Bytes 0-62
32
21
21
33
64
Manufacturer’s JEDEC ID Code (1)
7F
7F
7F
7F
65
Manufacturer’s JEDEC ID Code (2)
7F
7F
7F
7F
66
Manufacturer’s JEDEC ID Code (3)
7F
7F
7F
7F
67
Manufacturer’s JEDEC ID Code (4)
7F
7F
7F
7F
68
Manufacturer’s JEDEC ID Code (5)
7F
7F
7F
7F
69
Manufacturer’s JEDEC ID Code (6)
51
51
51
51
70
Manufacturer’s JEDEC ID Code (7)
00
00
00
00
71
Manufacturer’s JEDEC ID Code (8)
00
00
00
00
72
Module Manufacturer Location
xx
xx
xx
xx
73
Product Type, Char 1
37
36
36
37
74
Product Type, Char 2
32
34
34
32
Rev. 1.3, 2006-12
03292006-6GMD-RSFT
64
Internet Data Sheet
Product Type
HYS72T64000HU–3S–B
HYS64T128020HU–3S–B
HYS64T128920HU–3S–B
HYS72T128020HU–3S–B
HYS[64/72]T[32/64/128]xx0HU-[25F/2.5/3/3S/3.7/5]-B
Unbuffered DDR2 SDRAM Module
Organization
512MB
1 GByte
1 GByte
1 GByte
×72
×64
×64
×72
1 Rank (×8)
2 Ranks (×8) 2 Ranks (×8) 2 Ranks (×8)
Label Code
PC2–
5300E–555
PC2–
5300U–555
PC2–
5300U–555
PC2–
5300E–555
JEDEC SPD Revision
Rev. 1.2
Rev. 1.2
Rev. 1.2
Rev. 1.2
Byte#
Description
HEX
HEX
HEX
HEX
75
Product Type, Char 3
54
54
54
54
76
Product Type, Char 4
36
31
31
31
77
Product Type, Char 5
34
32
32
32
78
Product Type, Char 6
30
38
38
38
79
Product Type, Char 7
30
30
39
30
80
Product Type, Char 8
30
32
32
32
81
Product Type, Char 9
48
30
30
30
82
Product Type, Char 10
55
48
48
48
83
Product Type, Char 11
33
55
55
55
84
Product Type, Char 12
53
33
33
33
85
Product Type, Char 13
42
53
53
53
86
Product Type, Char 14
20
42
42
42
87
Product Type, Char 15
20
20
20
20
88
Product Type, Char 16
20
20
20
20
89
Product Type, Char 17
20
20
20
20
90
Product Type, Char 18
20
20
20
20
91
Module Revision Code
4x
4x
2x
4x
92
Test Program Revision Code
xx
xx
xx
xx
93
Module Manufacturing Date Year
xx
xx
xx
xx
94
Module Manufacturing Date Week
xx
xx
xx
xx
95 - 98
Module Serial Number
xx
xx
xx
xx
99 - 127 Not used
00
00
00
00
128 255
FF
FF
FF
FF
Blank for customer use
Rev. 1.3, 2006-12
03292006-6GMD-RSFT
65
Internet Data Sheet
HYS[64/72]T[32/64/128]xx0HU-[25F/2.5/3/3S/3.7/5]-B
Unbuffered DDR2 SDRAM Module
TABLE 35
Product Type
HYS64T32000HU–3.7–B
HYS64T32900HU–3.7–B
HYS64T64000HU–3.7–B
HYS64T64900HU–3.7–B
SPD Codes for HYS64T[32/64]x00HU–3.7–B
Organization
256MB
256MB
512MB
512MB
×64
×64
×64
×64
1 Rank (×16) 1 Rank (×16) 1 Rank (×8)
1 Rank (×8)
Label Code
PC2–
4200U–444
PC2–
4200U–444
PC2–
4200U–444
PC2–
4200U–444
JEDEC SPD Revision
Rev. 1.2
Rev. 1.2
Rev. 1.2
Rev. 1.2
Byte#
HEX
HEX
HEX
HEX
Description
0
Programmed SPD Bytes in EEPROM
80
80
80
80
1
Total number of Bytes in EEPROM
08
08
08
08
2
Memory Type (DDR2)
08
08
08
08
3
Number of Row Addresses
0D
0D
0E
0E
4
Number of Column Addresses
0A
0A
0A
0A
5
DIMM Rank and Stacking Information
60
60
60
60
6
Data Width
40
40
40
40
7
Not used
00
00
00
00
8
Interface Voltage Level
05
05
05
05
9
tCK @ CLMAX (Byte 18) [ns]
tAC SDRAM @ CLMAX (Byte 18) [ns]
3D
3D
3D
3D
50
50
50
50
11
Error Correction Support (non-ECC, ECC)
00
00
00
00
12
Refresh Rate and Type
82
82
82
82
13
Primary SDRAM Width
10
10
08
08
14
Error Checking SDRAM Width
00
00
00
00
15
Not used
00
00
00
00
16
Burst Length Supported
0C
0C
0C
0C
17
Number of Banks on SDRAM Device
04
04
04
04
18
Supported CAS Latencies
38
38
38
38
19
DIMM Mechanical Characteristics
01
01
01
01
20
DIMM Type Information
02
02
02
02
21
DIMM Attributes
00
00
00
00
22
Component Attributes
07
07
07
07
10
Rev. 1.3, 2006-12
03292006-6GMD-RSFT
66
Internet Data Sheet
Product Type
HYS64T32000HU–3.7–B
HYS64T32900HU–3.7–B
HYS64T64000HU–3.7–B
HYS64T64900HU–3.7–B
HYS[64/72]T[32/64/128]xx0HU-[25F/2.5/3/3S/3.7/5]-B
Unbuffered DDR2 SDRAM Module
Organization
256MB
256MB
512MB
512MB
×64
×64
×64
×64
1 Rank (×16) 1 Rank (×16) 1 Rank (×8)
1 Rank (×8)
Label Code
PC2–
4200U–444
PC2–
4200U–444
PC2–
4200U–444
PC2–
4200U–444
JEDEC SPD Revision
Rev. 1.2
Rev. 1.2
Rev. 1.2
Rev. 1.2
Byte#
Description
HEX
HEX
HEX
HEX
23
3D
3D
3D
3D
50
50
50
50
30
tCK @ CLMAX -1 (Byte 18) [ns]
tAC SDRAM @ CLMAX -1 [ns]
tCK @ CLMAX -2 (Byte 18) [ns]
tAC SDRAM @ CLMAX -2 [ns]
tRP.MIN [ns]
tRRD.MIN [ns]
tRCD.MIN [ns]
tRAS.MIN [ns]
2D
2D
2D
2D
31
Module Density per Rank
40
40
80
80
32
25
25
25
25
38
tAS.MIN and tCS.MIN [ns]
tAH.MIN and tCH.MIN [ns]
tDS.MIN [ns]
tDH.MIN [ns]
tWR.MIN [ns]
tWTR.MIN [ns]
tRTP.MIN [ns]
1E
1E
1E
1E
39
Analysis Characteristics
00
00
00
00
40
tRC and tRFC Extension
tRC.MIN [ns]
tRFC.MIN [ns]
tCK.MAX [ns]
tDQSQ.MAX [ns]
tQHS.MAX [ns]
00
00
00
00
24
25
26
27
28
29
33
34
35
36
37
41
42
43
44
45
50
50
50
50
60
60
60
60
3C
3C
3C
3C
28
28
1E
1E
3C
3C
3C
3C
37
37
37
37
10
10
10
10
22
22
22
22
3C
3C
3C
3C
1E
1E
1E
1E
3C
3C
3C
3C
69
69
69
69
80
80
80
80
1E
1E
1E
1E
28
28
28
28
46
PLL Relock Time
00
00
00
00
47
TCASE.MAX Delta / ∆T4R4W Delta
54
54
50
50
48
Psi(T-A) DRAM
72
72
7A
7A
Rev. 1.3, 2006-12
03292006-6GMD-RSFT
67
Internet Data Sheet
Product Type
HYS64T32000HU–3.7–B
HYS64T32900HU–3.7–B
HYS64T64000HU–3.7–B
HYS64T64900HU–3.7–B
HYS[64/72]T[32/64/128]xx0HU-[25F/2.5/3/3S/3.7/5]-B
Unbuffered DDR2 SDRAM Module
Organization
256MB
256MB
512MB
512MB
×64
×64
×64
×64
1 Rank (×16) 1 Rank (×16) 1 Rank (×8)
1 Rank (×8)
Label Code
PC2–
4200U–444
PC2–
4200U–444
PC2–
4200U–444
PC2–
4200U–444
JEDEC SPD Revision
Rev. 1.2
Rev. 1.2
Rev. 1.2
Rev. 1.2
Byte#
Description
HEX
HEX
HEX
HEX
49
∆T0 (DT0)
53
53
43
43
50
∆T2N (DT2N, UDIMM) or ∆T2Q (DT2Q, RDIMM)
29
29
2C
2C
51
∆T2P (DT2P)
33
33
36
36
52
∆T3N (DT3N)
1F
1F
21
21
53
∆T3P.fast (DT3P fast)
3D
3D
41
41
54
∆T3P.slow (DT3P slow)
27
27
2A
2A
55
∆T4R (DT4R) / ∆T4R4W Sign (DT4R4W)
46
46
40
40
56
∆T5B (DT5B)
1C
1C
1E
1E
57
∆T7 (DT7)
32
32
22
22
58
Psi(ca) PLL
00
00
00
00
59
Psi(ca) REG
00
00
00
00
60
∆TPLL (DTPLL)
00
00
00
00
61
∆TREG (DTREG) / Toggle Rate
00
00
00
00
62
SPD Revision
12
12
12
12
63
Checksum of Bytes 0-62
16
16
34
34
64
Manufacturer’s JEDEC ID Code (1)
7F
7F
7F
7F
65
Manufacturer’s JEDEC ID Code (2)
7F
7F
7F
7F
66
Manufacturer’s JEDEC ID Code (3)
7F
7F
7F
7F
67
Manufacturer’s JEDEC ID Code (4)
7F
7F
7F
7F
68
Manufacturer’s JEDEC ID Code (5)
7F
7F
7F
7F
69
Manufacturer’s JEDEC ID Code (6)
51
51
51
51
70
Manufacturer’s JEDEC ID Code (7)
00
00
00
00
71
Manufacturer’s JEDEC ID Code (8)
00
00
00
00
72
Module Manufacturer Location
xx
xx
xx
xx
73
Product Type, Char 1
36
36
36
36
74
Product Type, Char 2
34
34
34
34
Rev. 1.3, 2006-12
03292006-6GMD-RSFT
68
Internet Data Sheet
Product Type
HYS64T32000HU–3.7–B
HYS64T32900HU–3.7–B
HYS64T64000HU–3.7–B
HYS64T64900HU–3.7–B
HYS[64/72]T[32/64/128]xx0HU-[25F/2.5/3/3S/3.7/5]-B
Unbuffered DDR2 SDRAM Module
Organization
256MB
256MB
512MB
512MB
×64
×64
×64
×64
1 Rank (×16) 1 Rank (×16) 1 Rank (×8)
1 Rank (×8)
Label Code
PC2–
4200U–444
PC2–
4200U–444
PC2–
4200U–444
PC2–
4200U–444
JEDEC SPD Revision
Rev. 1.2
Rev. 1.2
Rev. 1.2
Rev. 1.2
Byte#
Description
HEX
HEX
HEX
HEX
75
Product Type, Char 3
54
54
54
54
76
Product Type, Char 4
33
33
36
36
77
Product Type, Char 5
32
32
34
34
78
Product Type, Char 6
30
39
30
39
79
Product Type, Char 7
30
30
30
30
80
Product Type, Char 8
30
30
30
30
81
Product Type, Char 9
48
48
48
48
82
Product Type, Char 10
55
55
55
55
83
Product Type, Char 11
33
33
33
33
84
Product Type, Char 12
2E
2E
2E
2E
85
Product Type, Char 13
37
37
37
37
86
Product Type, Char 14
42
42
42
42
87
Product Type, Char 15
20
20
20
20
88
Product Type, Char 16
20
20
20
20
89
Product Type, Char 17
20
20
20
20
90
Product Type, Char 18
20
20
20
20
91
Module Revision Code
4x
2x
4x
2x
92
Test Program Revision Code
xx
xx
xx
xx
93
Module Manufacturing Date Year
xx
xx
xx
xx
94
Module Manufacturing Date Week
xx
xx
xx
xx
95 - 98
Module Serial Number
xx
xx
xx
xx
99 - 127 Not used
00
00
00
00
128 255
FF
FF
FF
FF
Blank for customer use
Rev. 1.3, 2006-12
03292006-6GMD-RSFT
69
Internet Data Sheet
HYS[64/72]T[32/64/128]xx0HU-[25F/2.5/3/3S/3.7/5]-B
Unbuffered DDR2 SDRAM Module
TABLE 36
Product Type
HYS72T64000HU–3.7–B
HYS64T128020HU–3.7–B
HYS64T128920HU–3.7–B
HYS72T128020HU–3.7–B
SPD Codes for HYS[64/72]T[64/128]xx0HU–3.7–B
Organization
512MB
1 GByte
1 GByte
1 GByte
×72
×64
×64
×72
1 Rank (×8)
2 Ranks (×8) 2 Ranks (×8) 2 Ranks (×8)
Label Code
PC2–
4200E–444
PC2–
4200U–444
PC2–
4200U–444
PC2–
4200E–444
JEDEC SPD Revision
Rev. 1.2
Rev. 1.2
Rev. 1.2
Rev. 1.2
Byte#
Description
HEX
HEX
HEX
HEX
0
Programmed SPD Bytes in EEPROM
80
80
80
80
1
Total number of Bytes in EEPROM
08
08
08
08
2
Memory Type (DDR2)
08
08
08
08
3
Number of Row Addresses
0E
0E
0E
0E
4
Number of Column Addresses
0A
0A
0A
0A
5
DIMM Rank and Stacking Information
60
61
61
61
6
Data Width
48
40
40
48
7
Not used
00
00
00
00
8
Interface Voltage Level
05
05
05
05
9
tCK @ CLMAX (Byte 18) [ns]
tAC SDRAM @ CLMAX (Byte 18) [ns]
3D
3D
3D
3D
50
50
50
50
11
Error Correction Support (non-ECC, ECC)
02
00
00
02
12
Refresh Rate and Type
82
82
82
82
13
Primary SDRAM Width
08
08
08
08
10
14
Error Checking SDRAM Width
08
00
00
08
15
Not used
00
00
00
00
16
Burst Length Supported
0C
0C
0C
0C
17
Number of Banks on SDRAM Device
04
04
04
04
18
Supported CAS Latencies
38
38
38
38
19
DIMM Mechanical Characteristics
01
01
01
01
20
DIMM Type Information
02
02
02
02
21
DIMM Attributes
00
00
00
00
22
Component Attributes
07
07
07
07
Rev. 1.3, 2006-12
03292006-6GMD-RSFT
70
Internet Data Sheet
Product Type
HYS72T64000HU–3.7–B
HYS64T128020HU–3.7–B
HYS64T128920HU–3.7–B
HYS72T128020HU–3.7–B
HYS[64/72]T[32/64/128]xx0HU-[25F/2.5/3/3S/3.7/5]-B
Unbuffered DDR2 SDRAM Module
Organization
512MB
1 GByte
1 GByte
1 GByte
×72
×64
×64
×72
1 Rank (×8)
2 Ranks (×8) 2 Ranks (×8) 2 Ranks (×8)
Label Code
PC2–
4200E–444
PC2–
4200U–444
PC2–
4200U–444
PC2–
4200E–444
JEDEC SPD Revision
Rev. 1.2
Rev. 1.2
Rev. 1.2
Rev. 1.2
Byte#
Description
HEX
HEX
HEX
HEX
23
tCK @ CLMAX -1 (Byte 18) [ns]
tAC SDRAM @ CLMAX -1 [ns]
tCK @ CLMAX -2 (Byte 18) [ns]
tAC SDRAM @ CLMAX -2 [ns]
tRP.MIN [ns]
tRRD.MIN [ns]
tRCD.MIN [ns]
tRAS.MIN [ns]
24
25
26
27
28
29
30
3D
3D
3D
3D
50
50
50
50
50
50
50
50
60
60
60
60
3C
3C
3C
3C
1E
1E
1E
1E
3C
3C
3C
3C
2D
2D
2D
2D
31
Module Density per Rank
80
80
80
80
32
tAS.MIN and tCS.MIN [ns]
tAH.MIN and tCH.MIN [ns]
tDS.MIN [ns]
tDH.MIN [ns]
tWR.MIN [ns]
tWTR.MIN [ns]
tRTP.MIN [ns]
25
25
25
25
33
34
35
36
37
38
37
37
37
37
10
10
10
10
22
22
22
22
3C
3C
3C
3C
1E
1E
1E
1E
1E
1E
1E
1E
39
Analysis Characteristics
00
00
00
00
40
00
00
00
00
45
tRC and tRFC Extension
tRC.MIN [ns]
tRFC.MIN [ns]
tCK.MAX [ns]
tDQSQ.MAX [ns]
tQHS.MAX [ns]
46
3C
3C
3C
3C
69
69
69
69
80
80
80
80
1E
1E
1E
1E
28
28
28
28
PLL Relock Time
00
00
00
00
47
TCASE.MAX Delta / ∆T4R4W Delta
50
50
50
50
48
Psi(T-A) DRAM
7A
7A
7A
7A
41
42
43
44
Rev. 1.3, 2006-12
03292006-6GMD-RSFT
71
Internet Data Sheet
Product Type
HYS72T64000HU–3.7–B
HYS64T128020HU–3.7–B
HYS64T128920HU–3.7–B
HYS72T128020HU–3.7–B
HYS[64/72]T[32/64/128]xx0HU-[25F/2.5/3/3S/3.7/5]-B
Unbuffered DDR2 SDRAM Module
Organization
512MB
1 GByte
1 GByte
1 GByte
×72
×64
×64
×72
1 Rank (×8)
2 Ranks (×8) 2 Ranks (×8) 2 Ranks (×8)
Label Code
PC2–
4200E–444
PC2–
4200U–444
PC2–
4200U–444
PC2–
4200E–444
JEDEC SPD Revision
Rev. 1.2
Rev. 1.2
Rev. 1.2
Rev. 1.2
Byte#
Description
HEX
HEX
HEX
HEX
49
∆T0 (DT0)
43
43
43
43
50
∆T2N (DT2N, UDIMM) or ∆T2Q (DT2Q, RDIMM)
2C
2C
2C
2C
51
∆T2P (DT2P)
36
36
36
36
52
∆T3N (DT3N)
21
21
21
21
53
∆T3P.fast (DT3P fast)
41
41
41
41
54
∆T3P.slow (DT3P slow)
2A
2A
2A
2A
55
∆T4R (DT4R) / ∆T4R4W Sign (DT4R4W)
40
40
40
40
56
∆T5B (DT5B)
1E
1E
1E
1E
57
∆T7 (DT7)
22
22
22
22
58
Psi(ca) PLL
00
00
00
00
59
Psi(ca) REG
00
00
00
00
60
∆TPLL (DTPLL)
00
00
00
00
61
∆TREG (DTREG) / Toggle Rate
00
00
00
00
62
SPD Revision
12
12
12
12
63
Checksum of Bytes 0-62
46
35
35
47
64
Manufacturer’s JEDEC ID Code (1)
7F
7F
7F
7F
65
Manufacturer’s JEDEC ID Code (2)
7F
7F
7F
7F
66
Manufacturer’s JEDEC ID Code (3)
7F
7F
7F
7F
67
Manufacturer’s JEDEC ID Code (4)
7F
7F
7F
7F
68
Manufacturer’s JEDEC ID Code (5)
7F
7F
7F
7F
69
Manufacturer’s JEDEC ID Code (6)
51
51
51
51
70
Manufacturer’s JEDEC ID Code (7)
00
00
00
00
71
Manufacturer’s JEDEC ID Code (8)
00
00
00
00
72
Module Manufacturer Location
xx
xx
xx
xx
73
Product Type, Char 1
37
36
36
37
74
Product Type, Char 2
32
34
34
32
Rev. 1.3, 2006-12
03292006-6GMD-RSFT
72
Internet Data Sheet
Product Type
HYS72T64000HU–3.7–B
HYS64T128020HU–3.7–B
HYS64T128920HU–3.7–B
HYS72T128020HU–3.7–B
HYS[64/72]T[32/64/128]xx0HU-[25F/2.5/3/3S/3.7/5]-B
Unbuffered DDR2 SDRAM Module
Organization
512MB
1 GByte
1 GByte
1 GByte
×72
×64
×64
×72
1 Rank (×8)
2 Ranks (×8) 2 Ranks (×8) 2 Ranks (×8)
Label Code
PC2–
4200E–444
PC2–
4200U–444
PC2–
4200U–444
PC2–
4200E–444
JEDEC SPD Revision
Rev. 1.2
Rev. 1.2
Rev. 1.2
Rev. 1.2
Byte#
Description
HEX
HEX
HEX
HEX
75
Product Type, Char 3
54
54
54
54
76
Product Type, Char 4
36
31
31
31
77
Product Type, Char 5
34
32
32
32
78
Product Type, Char 6
30
38
38
38
79
Product Type, Char 7
30
30
39
30
80
Product Type, Char 8
30
32
32
32
81
Product Type, Char 9
48
30
30
30
82
Product Type, Char 10
55
48
48
48
83
Product Type, Char 11
33
55
55
55
84
Product Type, Char 12
2E
33
33
33
85
Product Type, Char 13
37
2E
2E
2E
86
Product Type, Char 14
42
37
37
37
87
Product Type, Char 15
20
42
42
42
88
Product Type, Char 16
20
20
20
20
89
Product Type, Char 17
20
20
20
20
90
Product Type, Char 18
20
20
20
20
91
Module Revision Code
4x
4x
2x
4x
92
Test Program Revision Code
xx
xx
xx
xx
93
Module Manufacturing Date Year
xx
xx
xx
xx
94
Module Manufacturing Date Week
xx
xx
xx
xx
95 - 98
Module Serial Number
xx
xx
xx
xx
99 - 127 Not used
00
00
00
00
128 255
FF
FF
FF
FF
Blank for customer use
Rev. 1.3, 2006-12
03292006-6GMD-RSFT
73
Internet Data Sheet
HYS[64/72]T[32/64/128]xx0HU-[25F/2.5/3/3S/3.7/5]-B
Unbuffered DDR2 SDRAM Module
TABLE 37
Product Type
HYS64T32000HU–5–B
HYS64T64000HU–5–B
HYS72T64000HU–5–B
HYS64T128020HU–5–B
HYS72T128020HU–5–B
SPD Codes for HYS[64/72]T[32/64/128]xxxHU–5–B
Organization
256MB
512MB
512MB
1 GByte
1 GByte
×64
×64
×72
×64
×72
1 Rank
(×16)
1 Rank
(×8)
1 Rank
(×8)
2 Ranks
(×8)
2 Ranks
(×8)
Label Code
PC2–
3200U–
333
PC2–
3200U–
333
PC2–
3200E–
333
PC2–
3200U–
333
PC2–
3200E–
333
JEDEC SPD Revision
Rev. 1.2
Rev. 1.2
Rev. 1.2
Rev. 1.2
Rev. 1.2
Byte#
Description
HEX
HEX
HEX
HEX
HEX
0
Programmed SPD Bytes in EEPROM
80
80
80
80
80
1
Total number of Bytes in EEPROM
08
08
08
08
08
2
Memory Type (DDR2)
08
08
08
08
08
3
Number of Row Addresses
0D
0E
0E
0E
0E
4
Number of Column Addresses
0A
0A
0A
0A
0A
5
DIMM Rank and Stacking Information
60
60
60
61
61
6
Data Width
40
40
48
40
48
7
Not used
00
00
00
00
00
8
Interface Voltage Level
05
05
05
05
05
9
tCK @ CLMAX (Byte 18) [ns]
tAC SDRAM @ CLMAX (Byte 18) [ns]
50
50
50
50
50
60
60
60
60
60
11
Error Correction Support (non-ECC, ECC)
00
00
02
00
02
12
Refresh Rate and Type
82
82
82
82
82
13
Primary SDRAM Width
10
08
08
08
08
14
Error Checking SDRAM Width
00
00
08
00
08
15
Not used
00
00
00
00
00
16
Burst Length Supported
0C
0C
0C
0C
0C
17
Number of Banks on SDRAM Device
04
04
04
04
04
18
Supported CAS Latencies
38
38
38
38
38
19
DIMM Mechanical Characteristics
01
01
01
01
01
20
DIMM Type Information
02
02
02
02
02
21
DIMM Attributes
00
00
00
00
00
10
Rev. 1.3, 2006-12
03292006-6GMD-RSFT
74
Internet Data Sheet
Product Type
HYS64T32000HU–5–B
HYS64T64000HU–5–B
HYS72T64000HU–5–B
HYS64T128020HU–5–B
HYS72T128020HU–5–B
HYS[64/72]T[32/64/128]xx0HU-[25F/2.5/3/3S/3.7/5]-B
Unbuffered DDR2 SDRAM Module
Organization
256MB
512MB
512MB
1 GByte
1 GByte
×64
×64
×72
×64
×72
1 Rank
(×16)
1 Rank
(×8)
1 Rank
(×8)
2 Ranks
(×8)
2 Ranks
(×8)
Label Code
PC2–
3200U–
333
PC2–
3200U–
333
PC2–
3200E–
333
PC2–
3200U–
333
PC2–
3200E–
333
JEDEC SPD Revision
Rev. 1.2
Rev. 1.2
Rev. 1.2
Rev. 1.2
Rev. 1.2
Byte#
Description
HEX
HEX
HEX
HEX
HEX
22
Component Attributes
07
07
07
07
07
23
50
50
50
50
50
60
60
60
60
60
50
50
50
50
50
60
60
60
60
60
30
tCK @ CLMAX -1 (Byte 18) [ns]
tAC SDRAM @ CLMAX -1 [ns]
tCK @ CLMAX -2 (Byte 18) [ns]
tAC SDRAM @ CLMAX -2 [ns]
tRP.MIN [ns]
tRRD.MIN [ns]
tRCD.MIN [ns]
tRAS.MIN [ns]
31
Module Density per Rank
32
38
tAS.MIN and tCS.MIN [ns]
tAH.MIN and tCH.MIN [ns]
tDS.MIN [ns]
tDH.MIN [ns]
tWR.MIN [ns]
tWTR.MIN [ns]
tRTP.MIN [ns]
39
Analysis Characteristics
40
tRC and tRFC Extension
tRC.MIN [ns]
tRFC.MIN [ns]
tCK.MAX [ns]
tDQSQ.MAX [ns]
tQHS.MAX [ns]
24
25
26
27
28
29
33
34
35
36
37
41
42
43
44
45
Rev. 1.3, 2006-12
03292006-6GMD-RSFT
75
3C
3C
3C
3C
3C
28
1E
1E
1E
1E
3C
3C
3C
3C
3C
28
28
28
28
28
40
80
80
80
80
35
35
35
35
35
47
47
47
47
47
15
15
15
15
15
27
27
27
27
27
3C
3C
3C
3C
3C
28
28
28
28
28
1E
1E
1E
1E
1E
00
00
00
00
00
00
00
00
00
00
37
37
37
37
37
69
69
69
69
69
80
80
80
80
80
23
23
23
23
23
2D
2D
2D
2D
2D
Internet Data Sheet
Product Type
HYS64T32000HU–5–B
HYS64T64000HU–5–B
HYS72T64000HU–5–B
HYS64T128020HU–5–B
HYS72T128020HU–5–B
HYS[64/72]T[32/64/128]xx0HU-[25F/2.5/3/3S/3.7/5]-B
Unbuffered DDR2 SDRAM Module
Organization
256MB
512MB
512MB
1 GByte
1 GByte
×64
×64
×72
×64
×72
1 Rank
(×16)
1 Rank
(×8)
1 Rank
(×8)
2 Ranks
(×8)
2 Ranks
(×8)
Label Code
PC2–
3200U–
333
PC2–
3200U–
333
PC2–
3200E–
333
PC2–
3200U–
333
PC2–
3200E–
333
JEDEC SPD Revision
Rev. 1.2
Rev. 1.2
Rev. 1.2
Rev. 1.2
Rev. 1.2
Byte#
Description
HEX
HEX
HEX
HEX
HEX
46
PLL Relock Time
00
00
00
00
00
47
TCASE.MAX Delta / ∆T4R4W Delta
54
50
50
50
50
48
Psi(T-A) DRAM
72
7A
7A
7A
7A
49
∆T0 (DT0)
4B
3B
3B
3B
3B
50
∆T2N (DT2N, UDIMM) or ∆T2Q (DT2Q, RDIMM)
25
27
27
27
27
51
∆T2P (DT2P)
33
36
36
36
36
52
∆T3N (DT3N)
1C
1E
1E
1E
1E
53
∆T3P.fast (DT3P fast)
34
38
38
38
38
54
∆T3P.slow (DT3P slow)
27
2A
2A
2A
2A
55
∆T4R (DT4R) / ∆T4R4W Sign (DT4R4W)
3E
38
38
38
38
56
∆T5B (DT5B)
1B
1D
1D
1D
1D
57
∆T7 (DT7)
30
21
21
21
21
58
Psi(ca) PLL
00
00
00
00
00
59
Psi(ca) REG
00
00
00
00
00
60
∆TPLL (DTPLL)
00
00
00
00
00
61
∆TREG (DTREG) / Toggle Rate
00
00
00
00
00
62
SPD Revision
12
12
12
12
12
63
Checksum of Bytes 0-62
6D
8B
9D
8C
9E
64
Manufacturer’s JEDEC ID Code (1)
7F
7F
7F
7F
7F
65
Manufacturer’s JEDEC ID Code (2)
7F
7F
7F
7F
7F
66
Manufacturer’s JEDEC ID Code (3)
7F
7F
7F
7F
7F
67
Manufacturer’s JEDEC ID Code (4)
7F
7F
7F
7F
7F
68
Manufacturer’s JEDEC ID Code (5)
7F
7F
7F
7F
7F
69
Manufacturer’s JEDEC ID Code (6)
51
51
51
51
51
Rev. 1.3, 2006-12
03292006-6GMD-RSFT
76
Internet Data Sheet
Product Type
HYS64T32000HU–5–B
HYS64T64000HU–5–B
HYS72T64000HU–5–B
HYS64T128020HU–5–B
HYS72T128020HU–5–B
HYS[64/72]T[32/64/128]xx0HU-[25F/2.5/3/3S/3.7/5]-B
Unbuffered DDR2 SDRAM Module
Organization
256MB
512MB
512MB
1 GByte
1 GByte
×64
×64
×72
×64
×72
1 Rank
(×16)
1 Rank
(×8)
1 Rank
(×8)
2 Ranks
(×8)
2 Ranks
(×8)
Label Code
PC2–
3200U–
333
PC2–
3200U–
333
PC2–
3200E–
333
PC2–
3200U–
333
PC2–
3200E–
333
JEDEC SPD Revision
Rev. 1.2
Rev. 1.2
Rev. 1.2
Rev. 1.2
Rev. 1.2
Byte#
Description
HEX
HEX
HEX
HEX
HEX
70
Manufacturer’s JEDEC ID Code (7)
00
00
00
00
00
71
Manufacturer’s JEDEC ID Code (8)
00
00
00
00
00
72
Module Manufacturer Location
xx
xx
xx
xx
xx
73
Product Type, Char 1
36
36
37
36
37
74
Product Type, Char 2
34
34
32
34
32
75
Product Type, Char 3
54
54
54
54
54
76
Product Type, Char 4
33
36
36
31
31
77
Product Type, Char 5
32
34
34
32
32
78
Product Type, Char 6
30
30
30
38
38
79
Product Type, Char 7
30
30
30
30
30
80
Product Type, Char 8
30
30
30
32
32
81
Product Type, Char 9
48
48
48
30
30
82
Product Type, Char 10
55
55
55
48
48
83
Product Type, Char 11
35
35
35
55
55
84
Product Type, Char 12
42
42
42
35
35
85
Product Type, Char 13
20
20
20
42
42
86
Product Type, Char 14
20
20
20
20
20
87
Product Type, Char 15
20
20
20
20
20
88
Product Type, Char 16
20
20
20
20
20
89
Product Type, Char 17
20
20
20
20
20
90
Product Type, Char 18
20
20
20
20
20
91
Module Revision Code
4x
4x
4x
4x
4x
92
Test Program Revision Code
xx
xx
xx
xx
xx
93
Module Manufacturing Date Year
xx
xx
xx
xx
xx
Rev. 1.3, 2006-12
03292006-6GMD-RSFT
77
Internet Data Sheet
Product Type
HYS64T32000HU–5–B
HYS64T64000HU–5–B
HYS72T64000HU–5–B
HYS64T128020HU–5–B
HYS72T128020HU–5–B
HYS[64/72]T[32/64/128]xx0HU-[25F/2.5/3/3S/3.7/5]-B
Unbuffered DDR2 SDRAM Module
Organization
256MB
512MB
512MB
1 GByte
1 GByte
×64
×64
×72
×64
×72
1 Rank
(×16)
1 Rank
(×8)
1 Rank
(×8)
2 Ranks
(×8)
2 Ranks
(×8)
Label Code
PC2–
3200U–
333
PC2–
3200U–
333
PC2–
3200E–
333
PC2–
3200U–
333
PC2–
3200E–
333
JEDEC SPD Revision
Rev. 1.2
Rev. 1.2
Rev. 1.2
Rev. 1.2
Rev. 1.2
Byte#
Description
HEX
HEX
HEX
HEX
HEX
94
Module Manufacturing Date Week
xx
xx
xx
xx
xx
95 - 98
Module Serial Number
xx
xx
xx
xx
xx
99 - 127 Not used
00
00
00
00
00
128 255
FF
FF
FF
FF
FF
Blank for customer use
Rev. 1.3, 2006-12
03292006-6GMD-RSFT
78
Internet Data Sheet
HYS[64/72]T[32/64/128]xx0HU-[25F/2.5/3/3S/3.7/5]-B
Unbuffered DDR2 SDRAM Module
5
Package Outlines
This chapter contains the Package Outline tables.
FIGURE 6
Package Outline Raw Card C L-DIM-240-3
$ % &
0$
;
[
&
“
“ $
“
%
“
'HWD LORIFR QWD FWV “ $ % &
%XUU PD [ DOORZ
H G
*/' Notes
1. Drawing according to ISO 8015
2. Dimensions in mm
3. General tolerances +/- 0.15
Rev. 1.3, 2006-12
03292006-6GMD-RSFT
79
Internet Data Sheet
HYS[64/72]T[32/64/128]xx0HU-[25F/2.5/3/3S/3.7/5]-B
Unbuffered DDR2 SDRAM Module
FIGURE 7
¡ $ % &
Package Outline Raw Card D L-DIM-240-8
0$;
“
“
&
“
“
“
“
“
“
“
“
$
“
%
0,1
“
'HWDLO RI FRQWDFWV
“
$ % &
%XUU PD[ DOORZHG
*/'
Notes
1. Drawing according to ISO 8015
2. Dimensions in mm
3. General tolerances +/- 0.15
Rev. 1.3, 2006-12
03292006-6GMD-RSFT
80
Internet Data Sheet
HYS[64/72]T[32/64/128]xx0HU-[25F/2.5/3/3S/3.7/5]-B
Unbuffered DDR2 SDRAM Module
FIGURE 8
¡ $ % &
Package Outline Raw Card E L-DIM-240-9
0$;
“
“
&
“
“
“
“
“
“
“
“
$
“
%
0,1
“
'HWDLO RI FRQWDFWV
“
$ % &
%XUU PD[ DOORZHG
*/'
Notes
1. Drawing according to ISO 8015
2. Dimensions in mm
3. General tolerances +/- 0.15
Rev. 1.3, 2006-12
03292006-6GMD-RSFT
81
Internet Data Sheet
HYS[64/72]T[32/64/128]xx0HU-[25F/2.5/3/3S/3.7/5]-B
Unbuffered DDR2 SDRAM Module
FIGURE 9
¡ $ % &
Package Outline Raw Card F L-DIM-240-6
0$;
“
“
&
“
“
“
“
“
“
“
“
$
“
%
0,1
“
'HWDLO RI FRQWDFWV
“
$ % &
%XUU PD[ DOORZHG
*/'
Notes
1. Drawing according to ISO 8015
2. Dimensions in mm
3. General tolerances +/- 0.15
Rev. 1.3, 2006-12
03292006-6GMD-RSFT
82
Internet Data Sheet
HYS[64/72]T[32/64/128]xx0HU-[25F/2.5/3/3S/3.7/5]-B
Unbuffered DDR2 SDRAM Module
FIGURE 10
¡ $ % &
Package Outline Raw Card G L-DIM-240-7
0$;
“
“
&
“
“
“
“
“
“
“
“
$
“
%
0,1
“
'HWDLO RI FRQWDFWV
“
$ % &
%XUU PD[ DOORZHG
*/'
Notes
1. Drawing according to ISO 8015
2. Dimensions in mm
3. General tolerances +/- 0.15
Rev. 1.3, 2006-12
03292006-6GMD-RSFT
83
Internet Data Sheet
HYS[64/72]T[32/64/128]xx0HU-[25F/2.5/3/3S/3.7/5]-B
Unbuffered DDR2 SDRAM Module
6
Product Type Nomenclature
Qimonda’s nomenclature uses simple coding combined with
some propriatory coding. Table 38 provides examples for
module and component product type number as well as the
field number. The detailed field description together with
possible values and coding explanation is listed for modules
in Table 39 and for components in Table 40.
TABLE 38
Nomenclature Fields and Examples
Example for
Field Number
1
2
3
4
5
6
7
8
9
10
11
Micro-DIMM
HYS
64
T
64/128
0
2
0
K
M
–5
–A
DDR2 DRAM
HYB
18
T
512/1G 16
0
A
C
–5
TABLE 39
DDR2 DIMM Nomenclature
Field
Description
Values
Coding
1
Qimonda Module Prefix
HYS
Constant
2
Module Data Width [bit]
64
Non-ECC
72
ECC
3
DRAM Technology
T
DDR2
4
Memory Density per I/O [Mbit];
Module Density1)
32
256 MByte
64
512 MByte
128
1 GByte
256
2 GByte
512
4 GByte
5
Raw Card Generation
0 .. 9
Look up table
6
Number of Module Ranks
0, 2, 4
1, 2, 4
7
Product Variations
0 .. 9
Look up table
8
Package, Lead-Free Status
A .. Z
Look up table
9
Module Type
Rev. 1.3, 2006-12
03292006-6GMD-RSFT
D
SO-DIMM
M
Micro-DIMM
R
Registered
U
Unbuffered
F
Fully Buffered
84
Internet Data Sheet
HYS[64/72]T[32/64/128]xx0HU-[25F/2.5/3/3S/3.7/5]-B
Unbuffered DDR2 SDRAM Module
Field
Description
Values
Coding
10
Speed Grade
–2.5F
PC2–6400 5–5–5
–2.5
PC2–6400 6–6–6
11
Die Revision
–3
PC2–5300 4–4–4
–3S
PC2–5300 5–5–5
–3.7
PC2–4200 4–4–4
–5
PC2–3200 3–3–3
–A
First
–B
Second
1) Multiplying “Memory Density per I/O” with “Module Data Width” and dividing by 8 for Non-ECC and 9 for ECC modules gives the overall
module memory density in MBytes as listed in column “Coding”.
TABLE 40
DDR2 DRAM Nomenclature
Field
Description
Values
Coding
1
Qimonda Component Prefix
HYB
Constant
2
Interface Voltage [V]
18
SSTL_18
3
DRAM Technology
T
DDR2
4
Component Density [Mbit]
256
256 Mbit
512
512 Mbit
1G
1 Gbit
5+6
Number of I/Os
2G
2 Gbit
40
×4
80
×8
16
×16
7
Product Variations
0 .. 9
Look up table
8
Die Revision
A
First
B
Second
C
FBGA, lead-containing
F
FBGA, lead-free
–25F
DDR2-800 5-5-5
–2.5
DDR2-800 6-6-6
–3
DDR2-667 4-4-4
–3S
DDR2-667 5-5-5
–3.7
DDR2-533 4-4-4
–5
DDR2-400 3-3-3
9
Package, Lead-Free Status
10
Speed Grade
Rev. 1.3, 2006-12
03292006-6GMD-RSFT
85
Internet Data Sheet
HYS[64/72]T[32/64/128]xx0HU-[25F/2.5/3/3S/3.7/5]-B
Unbuffered DDR2 SDRAM Module
Table of Contents
1
1.1
1.2
Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3
Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3
Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
2
2.1
Pin Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
Pin Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
3
3.1
3.2
3.3
3.3.1
3.3.2
3.3.3
3.4
Electrical Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Absolute Maximum Ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
DC Operating Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Timing Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Speed Grade Definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Component AC Timing Parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
ODT AC Electrical Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
IDD Specifications and Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4
SPD Codes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43
5
Package Outlines . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79
6
Product Type Nomenclature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 84
16
16
17
18
18
20
33
35
Table of Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 86
Rev. 1.3, 2006-12
03292006-6GMD-RSFT
86
Internet Data Sheet
Edition 2006-12
Published by Qimonda AG
Gustav-Heinemann-Ring 212
D-81739 München, Germany
© Qimonda AG 2006.
All Rights Reserved.
Legal Disclaimer
The information given in this Internet Data Sheet shall in no event be regarded as a guarantee of conditions or characteristics
(“Beschaffenheitsgarantie”). With respect to any examples or hints given herein, any typical values stated herein and/or any
information regarding the application of the device, Qimonda hereby disclaims any and all warranties and liabilities of any kind,
including without limitation warranties of non-infringement of intellectual property rights of any third party.
Information
For further information on technology, delivery terms and conditions and prices please contact your nearest Qimonda Office.
Warnings
Due to technical requirements components may contain dangerous substances. For information on the types in question please
contact your nearest Qimonda Office.
Under no circumstances may the Qimonda product as referred to in this Internet Data Sheet be used in
1. Any applications that are intended for military usage (including but not limited to weaponry), or
2. Any applications, devices or systems which are safety critical or serve the purpose of supporting, maintaining, sustaining
or protecting human life (such applications, devices and systems collectively referred to as "Critical Systems"), if
a) A failure of the Qimonda product can reasonable be expected to - directly or indirectly (i) Have a detrimental effect on such Critical Systems in terms of reliability, effectiveness or safety; or
(ii) Cause the failure of such Critical Systems; or
b) A failure or malfunction of such Critical Systems can reasonably be expected to - directly or indirectly (i) Endanger the health or the life of the user of such Critical Systems or any other person; or
(ii) Otherwise cause material damages (including but not limited to death, bodily injury or significant damages to
property, whether tangible or intangible).
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