STMicroelectronics ML605 Board User Manual

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Documento
UM1528
User manual
STxP70-4 board support package for the ML605 board
Synopsis
The STxP70-4 board support package (BSP) has been developed to enable you to quickly
and easily evaluate the STxP70 core and peripherals programming.
The STxP70-4 board support package has been developed for an Xilinx ML605 evaluation
board containing an STxP70-4 FPGA mapping. Using the STxP70 Professional Toolset
together with an ST Micro Connect 2 to connect to the board you can use the BSP to
evaluate the STxP70 before developing your own custom board and FPGA mapping. The
source files supplied with the BSP may then be adapted for testing purposes.
This document describes the entire test environment that was used during the development
of the STxP70-4 board support package. It contains all the necessary information about
software configurations, software versions, project configuration settings, board connections
or configurations and so on. The board support package, delivered as a C source file
project, can be used with different host platforms (Windows, Linux). This document
introduces several source files examples in order to help the reader to evaluate the Xilinx
ML605 board with the STxP70-4 core mapping.
To use the STxP70-4 board support package you will need to purchase an Xilinx ML605
development board directly from Xilinx, and obtain the associated development kit and
debug card, see Prerequisites. The STxP70-4 board support package and default
STxP70-4 FPGA mapping are available on request from your local ST FAE.
Prerequisites
In order to use the board support package, the following are required:
April 2012
1.
The Xilinx ML605 Board Development Kit
2.
The Xilinx XM 105 debug card
3.
The ST Micro Connect 2 and STMC I/O convertor Type C
4.
STxP70 Professional Toolset R2011.2 or later
5.
FPGA mapping based on STxP70 V4Br3 core
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Contents
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Contents
1
2
Package description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
1.1
Package import . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
1.2
Package tree . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
4
Example_ASC0_LCD . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
1.2.2
Example_Flash . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
1.2.3
Example_GPIO . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
1.2.4
Example_GPIO_LCD . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
1.2.5
Example_ITC and Example_ITC_functions . . . . . . . . . . . . . . . . . . . . . . . 7
1.2.6
Example_TCU . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
Software configuration requirements . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
2.1
3
1.2.1
STxP70 Professional Toolset R2011.2 . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
2.1.1
System and multi-context hardware libraries . . . . . . . . . . . . . . . . . . . . . . 9
2.1.2
CORE_CFG register value . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
2.1.3
Configuration file (target.ini) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
2.1.4
Configuration settings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
2.2
Run and debug . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
2.3
FPGA mapping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
Hardware configuration requirements . . . . . . . . . . . . . . . . . . . . . . . . . 14
3.1
Programming . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
3.2
Loading through compact Flash . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
3.3
Connection with the board . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
3.3.1
ST Micro Connect 2 (Ethernet) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
3.3.2
ST Micro Connect 2 (USB) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
The STxP70 system library . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
4.1
Supported architecture, host machine and configuration . . . . . . . . . . . . . 17
4.1.1
4.2
Naming conventions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
4.3
Type definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
4.4
Generic driver implementation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
4.4.1
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Unsupported features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
Peripheral I/O registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
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6
Contents
4.5
Library contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
4.6
Building and using the STxP70 system library . . . . . . . . . . . . . . . . . . . . . 23
The STxP70 board support package library . . . . . . . . . . . . . . . . . . . . . 24
5.1
File structure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
5.2
Supported architecture and configuration . . . . . . . . . . . . . . . . . . . . . . . . 25
5.3
Naming convention . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
5.4
Type definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
5.5
Generic driver implementation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
5.6
Library contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
5.7
Building and using the STxP70 BSP library . . . . . . . . . . . . . . . . . . . . . . . 27
Reference documents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
Appendix A FPGA design summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
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Package description
1
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Package description
The board support package was developed using the STxP70 Professional Toolset
R2011.2. It can be used with this toolset and later revisions. It is delivered as a set of
exported projects with launch configuration: STxP70bsplib.stz. This file can be obtained
from your local ST FAE.
1.1
Package import
To import the package using the STxP70 Professional Toolset R2011.2:
1.2
1.
Create a new folder to contain the STxP70bsplib workspace and save the
STxP70bsplib.stz file in it. For example: C:\STM\STxP70bsplib.
2.
Launch the STxP70 Professional Toolset R2011.2 STWorkbench.
3.
Select File &gt; Import. The Import window is displayed.
4.
Expand the General folder, select Projects with Launch Configurations and click on
Next.
5.
Browse for the STxP70bsplib.stz archive file and click on Finish.
Package tree
The BSP package library is described in detail in Chapter 5: The STxP70 board support
package library on page 24. In brief it is made of three types of directories:
●
●
C projects containing the example source code:
–
Example_ASC0_LCD
–
Example_Flash
–
Example_GPIO
–
Example_GPIO_LCD
–
Example_ITC
–
Example_ITC_Functions
–
Example_TCU
C projects containing libraries source files:
–
●
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stxp70_bsplib
Storage directories containing extra files and documents:
–
config_file project contains the target.ini file
–
include project contains the BSP header files
–
lib project contains the BSP library files
–
link project contains the link script file
–
obj project contains the object files
–
tools contains the cp2103 USB to Serial driver
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1.2.1
Package description
Example_ASC0_LCD
The ML605 board FPGA mapping used has one on-chip asynchronous/synchronous serial
controller (ASC) with the symbolic name ASC0. The pins RXD and TXD of ASC0 are wired
on a USB connector through an asynchronous serial-to-USB interface. A USB driver allows
this interface to be used as a COM port. This example program uses the connection through
channel 0 and sends data to the ML605 board LCD screen.
Before running this program, install the appropriate drivers to use the USB-to-serial
interface (cp2103) on the board. These drivers are provided by Silabs and instructions on
their use can be found in the readme.txt file in the directory tools/usb_cp210x. Once
the drivers are installed, connect a USB cable from your PC to the board. Check in the PC
hardware device manager which COM ports have been associated with the newly installed
cp210x drivers.
Figure 1.
USB to UART connector
LEDs
GPIO dip
switches
USB to UART
connector
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Package description
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To initiate the connection between the PC and the board, complete the following steps:
1.
Open a HyperTerminal window (Start &gt; Programs &gt; Accessories &gt;
Communications &gt; HyperTerminal).
2.
Enter a name for the connection. (We recommend that you use a name that reflects the
properties of the connection, for example 9600-8bitdata-1stopbit-oddparity.)
3.
Adapt the connection port used for the USB by selecting the appropriate COM port
4.
Set the Properties of the connection (9600 bits per second, 8 bit data, odd parity, 1
stop bit, No hardware flow control) and save it.
(If you open a previously saved connection, verify the properties of the connection
before connecting.)
5.
Launch the example program on the evaluation board (Connect and run the program)
Check that the terminal window displays the following message:
press any key to begin the demonstration..
ASC Demonstration using the LCD
What do you want to do? Print on Lcd or eXit program?
6.
1.2.2
The terminal is now behaving like a monitor, waiting for you to enter a command. Two
commands have already been provided. These are:
&gt; L
The text entered following the L command is displayed on the LCD. You may
enter two lines of up to 16 characters each.
&gt; X
Enter X to exit from the program. If you wish, you may design and program your
own commands. If you enter an unknown command, the window displays the
error message “wrong command”.
Example_Flash
This example provides the flexible static memory controller (FSMC) initialization and it
shows how to use high level functions to program, lock, erase sectors or full Flash memory.
The application results are displayed on the console.
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1.2.3
Package description
Example_GPIO
This example tests the input push buttons SW7 and SW5 (see Figure 2) and the output
(LEDs). The program waits for you to use the inputs, displaying the change and the value of
the GPIO data register at each change. There are two tests for LED illumination. The first
LED test starts when the program starts. The second LED test starts when push button
SW7 (on the ML605 Board) is pressed. The program terminates when push button SW5 (on
the ML605 Board) is pressed, during the second LED test.
Figure 2.
Example_GPIO push buttons
SW5
SW7
1.2.4
Example_GPIO_LCD
This example uses the interrupts with the GPIOs. It displays a string of text on the LCD and
scrolls it horizontally in a “ticker-tape” fashion. The first part of the program uses the function
LCD_Send_Data() to set up the scrolling text. You can then increment the DDRAM
address by pressing push button SW7. You can select to display the message on either the
upper or lower line of the LCD screen by toggling DIP switch 8. When you press push button
SW5, the second part of program is executed, that uses the LCD_Send_Line() function
and the LCD_Rotate_Line() function to scroll the text automatically. Pressing push
buttons SW7 and SW5 now changes the direction of scrolling to the left or right respectively.
Toggling DIP switch 1 terminates the program.
1.2.5
Example_ITC and Example_ITC_functions
The purpose of these examples is to illustrate the use of ITC high level functions. In both
examples the code configures the ITC as follows:
Note:
●
IRQ0 and IRQ3 and their respective handlers are enabled to use the default handlers
defined in it_vectors.s file
●
IRQ1 is configured to use a dynamic handler
When declaring an interrupt handler, use the __attribute__ ((interrupt)) directive.
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Package description
1.2.6
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Example_TCU
This example configures a 32-bit timer and generates an interrupt triggered by a CR
comparison event. It uses two assembly functions:
●
getcc gets the value of the cycle count register
●
clrcc clears the cycle count register
The program counts the number of cycles between two timer consecutive overflows over
the course of twenty successive timer overflows and then computes an average.
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2
Software configuration requirements
Software configuration requirements
The software used during the development of the board support package is:
2.1
●
STxP70 Professional Toolset R2011.2
●
iMPACT from Xilinx ISE WebPACK 12.4 (not part of the BSP delivery, and only
required if you are developing your own FPGA mapping - see Section 2.3: FPGA
mapping on page 12 for details)
STxP70 Professional Toolset R2011.2
This section describes the software configuration requirements that relate to the STxP70
Professional Toolset R2011.2.
2.1.1
System and multi-context hardware libraries
In addition to the standard C libraries, the toolset uses two specific STxP70 libraries:
●
STxP70 system library
(handles the Interrupt Controller and the Timer and Counter Unit)
●
STxP70 multi-context hardware abstraction layer library, initial release
(handles the multi-context feature)
These libraries are provided with the toolset installation. Please refer to STxP70
Professional Toolset documentation, in particular to the application note Building STxP70
libraries (8226669) for more information.
2.1.2
CORE_CFG register value
In order to be compliant with the original mapping with the release date 27 January 2012
and be available with the BSP, the CORE_CFG register value set in the STxP70
Configuration &amp; Architecture field in the Properties of the project has to be 0x4A5AA82A.
This corresponds to the features shown in Table 1. The CORE_CFG1 is set to the default
(0xc00).
Table 1.
CORE_CFG register details
Field
Value
Context number
4
Register bank number
1
Multiplier
Yes
EFU interface
64 bits
MFU interface
No
External Memory interface
64 bits
ITC number of nodes
15+1 nodes
EVC
16 local evt - 16 global evt
Hardware Loops
2 hardware loops for each context
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Software configuration requirements
Table 1.
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CORE_CFG register details (continued)
Field
2.1.3
Value
Data Memory Size
128K Bytes
Data Cache
DCACHE not implemented
Program Memory size
128K Bytes
Program Cache
PCACHE not implemented
Configuration file (target.ini)
The configuration file (target.ini file) provided with the board support package (in the
config_file folder) allows access to the target through the debugger using the hosttarget interface STMC2 (ST Micro Connect 2) - see Section 3.3: Connection with the board
on page 15.
By default, the launch configuration provided with the BSP, points automatically to the
specific target sx_debug (described below), provided that you select the corresponding
executable (.out file) for each example, see Section 2.2: Run and debug on page 11.
[sxv4_ml605_stmc2_usb_memec]
Rule=target:type EMU
Rule=define ML605
Rule=define V4
Section=Core
Section=Memory_Map
OwnerParam=&lt;BEGIN&gt;
# USB connection - default is 192.168.2.1
connect STMC2 -h 192.168.2.1 -freq 25000000 -irlen 5
# Ethernet connection - contact local IT for address
#connect STMC2 -h x.x.x.x -freq 10000000 -irlen 5
config compliant_revision_num 0x00000002
config thread_timeout 30000
# logtrace &quot;./xp70_debug.txt&quot;
&lt;OWNER PARAM END&gt;
[Memory_Map]
Rule=require ML605
MemoryMap = DRAM
MemoryMap = PRAM
MemoryMap = ERAM
MemoryMap = INTFSMCR
MemoryMap = FLASH
MemoryMap = IPE
0x00000000
0x00400000
0x00800000
0x03000000
0x10000000
0xFF000000
0x00020000
0x00020000
0x02000000
0x00010000
0x02000000
0x01000000
rw
rwx
rwx
rw
rwx
rw
The link file provided in the board support package (in the link directory) is compliant with
this configuration file (meaning that the memory sections are compliant). See the STxP70
professional toolset user manual (7833754) for details of the configuration file. A default
configuration file is provided and included in the toolset at the following location:
\STxP70_Toolset_2011.2\bin directory). You can rename the toolset default
configuration file and replace it in the same location with the one provided with the board
support package (located in the config_file folder).
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2.1.4
Software configuration requirements
Configuration settings
Depending on the routine you want to run, you must include one or more libraries. To do
this, include the main header file at the beginning of your code (for example,
#include &quot;stxp70_mylib.h&quot;) and specify its path in the include field of the
configuration settings. Set the name and the path of the library in the STxP70 Linker &gt;
Libraries field.
Note:
The name of a library whose filename is libstxp70mylib.a should be entered as
stxp70mylib.
Specify the correct link file in the STxP70 Linker &gt; General field.
The following commands are issued when building a project:
stxp70cc -Mextrcdir &quot;%Toolset_inst_dir%\_STxP70-Extension_/bin&quot; -g
-keep -I&quot;%BSP_inst_dir%\STxP70bsplib\include&quot; -MMD -MP
-MF &quot;pgrm_name.d&quot; -MT&quot; pgrm_name.d&quot; -corecfg=0x4a5aa82a -c -o&quot;
pgrm_name.o&quot; &quot;../ pgrm_name.c&quot;
stxp70cc -Mextrcdir &quot;%Toolset_inst_dir%\_STxP70-Extension_/bin&quot;
-T%BSP_inst_dir%\STxP70bsplib\link\stxp70bsp.ld -corecfg=0x4a5aa82a
-o&quot; pgrm_name.out&quot; ./ pgrm_name.o
-L%BSP_inst_dir%\STxP70bsplib\lib -lstxp70bsp
The first line corresponds to the call of the compiler and the second line to the call of the
linker (see the STxP70 compiler user manual (8027948) for details about the use of the
stxp70cc command).
%Toolset_inst_dir% corresponds to the installation directory of the toolset.
%BSP_inst_dir% corresponds to the workspace/installation directory of the board support
package.
pgrm_name is the name of the program.
2.2
Run and debug
While using the runner or the debugger, the user has to select the sx_debug target from
the targets defined in the target.ini file, (provided in the config_file folder of the
BSP).
Errors when running or debugging can occur if the memory map of the link file and the
target.ini file are not compliant. If you use your own configuration file, ensure the
memory map is compliant with one of the link files.
The user can launch directly, the executable provided for each example (Section 1.2.1:
Example_ASC0_LCD on page 5 to Section 1.2.6: Example_TCU on page 8), because the
BSP is exported with the configuration launch option. In STWorkbench, under Debug
configuration, select the specific STxP70 Debug C/C++ application you want to debug.
The window provides a debugger folder pointing by default to the single core target set to
sx_debug. (If you have C code changes, the application can be rebuilt before debugging).
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Software configuration requirements
2.3
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FPGA mapping
iMPACT, included in the Xilinx ISE LabTools 12.4, is a Xilinx software GUI used to convert a
.bit file into a .mcs file. A .bit file is made for the ML605 board using a Xilinx Virtex 6
FPGA. The default FPGA mapping in based on an STxP70-4 core and peripherals and is
provided with the board support package upon request, see Figure 3. More information is
available in Appendix A: FPGA design summary on page 28. Please contact your local ST
FAE for more information.
Figure 3.
Block diagram
The iMPACT software enables the .bit file to be converted into a .mcs file; then this file
can be programmed into the configuration Flash memory of the FPGA. The .bit file can
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Software configuration requirements
also be translated into ACE files and saved into a compact Flash that can be used for
loading the FPGA mapping. For more details, please refer to Xilinx documentation, see
Chapter 6: Reference documents on page 28.
Details about the iMPACT features
The ISE LabTools 12.4 can be downloaded for free from the Xilinx website. Register at
www.xilinx.com/register then go to www.xilinx.com/support/download/index.htm to obtain
the latest Xilinx Software Service Pack.
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Hardware configuration requirements
3
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Hardware configuration requirements
The main board used is the Xilinx ML605 board Virtex6 evaluation board. For connection
and setup you are required to use an interface daughter board also provided by Xilinx: the
FMC-XM105 Debug board. For detailed information about both boards, we recommend you
refer to the Xilinx documentation listed in Chapter 6: Reference documents on page 28.
3.1
Programming
The ML605 board does not contain any mapping by default: the FPGA may be
reprogrammed using the Xilinx iMPACT tool. You will need a mini USB cable (provided by
Xilinx with the ML605 Evaluation board kit) connected through your PC to the USB JTAG
J22 on the ML605 board. Please refer to Section 2.3: FPGA mapping on page 12 for
software requirements and to the Xilinx ML 605 User guide for more information.
3.2
Loading through compact Flash
Instead of programming the FPGA with the Xilinx iMPACT tool, it may also be loaded
through the compact Flash shipped with the board. The main advantages of loading are that
it is faster compared to programming and we can switch quickly and easily from one
mapping to another one. For loading, you need to save in this compact Flash the ACE files
derived from the .bit files; the compact Flash can have up to 8 mappings (ACE files); the
compact Flash will need to be inserted in the compact Flash connector U73. The Jumper
J69 can be put on in order to have the system ACEerror LED enabled. Enabling and
selection of compact Flash ACE files is performed with the S1 4 DIP switches and the
system ACE Reset push button (SW3 near J38). In our case using the ACE file provided by
default with the BSP (see Figure 4), the S1 DIP switches will have to be set as follows:
●
S1 switch 4 = 1 (On): enable system ACE Compact Flash controller to configure the
FPGA
●
S1 switches 1, 2, and 3 = 0 (Off): to select binary address 0 on Compact Flash (the first
ACE file is selected)
After the ACE Reset button is pressed, the system ACE status LED will blink during the
transfer and the LCD will indicate that the load is effective at the end: the message is:
“STxP70S4Br3 Demo 27.01.2012 100Mhz”.
Please refer to the Xilinx ML 605 User guide for more information.
Figure 4.
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ACE folder tree
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Figure 5.
Hardware configuration requirements
System ACE on ML605 board
Board
On/Off
ACE S1 switches
Ace reset (SW3)
Jumper
J69
Compact
Flash
connector
3.3
Connection with the board
To connect the PC to the board for debug purposes, use an ST Micro Connect 2 host-target
interface (STMC2) through either Ethernet or USB. The BSP requires the STMC2 to be
supplied with an STMC I/O convertor Type C, so use the order code STMC2-JTAG, to order
your STMC2.
Plug and fix the interface board on the HPC FMC connector of the main board. The JTAG
signals have been redirected (in the FPGA mapping) on the interface daughter board
connector J1 pins1 to 20: due to the shape of the STMC2 JTAG cable plug, the J1 pins 21
and 22 must be bent. (Pin 1 on the JTAG cable is the red wire.)
To connect the JTAG link on the interface board to the STMC2: connect the J1 connector on
the board to the 20-way M-ICE header cable. Connect the M-ICE header cable to the
20-way header on the STMC2 I/O convertor Type C. The I/O convertor Type C is then
connected using a SCSI-V cable (supplied with the STMC2) to the LVDS connector on the
STMC2. See Figure 6.
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Hardware configuration requirements
Figure 6.
3.3.1
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Connecting the interface board to the STMC2
ST Micro Connect 2 (Ethernet)
Ethernet connection is supported on Linux and Windows 2000 and XP platforms. It is
expected that an ST Micro Connect 2 connected to an Ethernet LAN will be configured with
either a static address for that network, or dynamically using DHCP. Use of the default IP
address is not advised.
More information is provided in the ST Micro Connect 2 Datasheet (7912386).
3.3.2
ST Micro Connect 2 (USB)
USB connection is supported on Windows XP and Red Hat Linux - Fedora Core platforms.
The ST Micro Connect 2 uses the TCP/IP protocol to communicate over a USB connection.
When the ST Micro Connect 2 is connected to the host using USB, the host dynamically
creates a network interface for that connection. In addition to the IP address given to the
ST Micro Connect 2, a separate IP address must be assigned to the host for this USB
network interface. The network interface is normally configured automatically by the
ST Micro Connect 2 DHCP server to operate with the factory setup of the STMC2. It is not
normally necessary to change these values.
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4
The STxP70 system library
The STxP70 system library
The STxP70 system library consists of the interrupt controller (ITC) and the timer control
unit (TCU) modules. These modules contain software drivers dedicated to the configuration
and control of these hardware elements. The library provided with the STxP70 Professional
Toolset R2011.2 is available in the directory:
&lt;toolset installation directory&gt;\stxp70cc\4.3\src\lib\libsys
For more information, please look at the more detailed documentation provided with the
library and available with the toolset.
4.1
Supported architecture, host machine and configuration
This version of the system library supports core architecture V4Br3 of the STxP70 core, and
was tested on a PC environment (Windows XP). The version of the toolset used to develop
this board support package is R2011.2.
The toolset system library provides a configuration file stxp70_config.h (located in the
/libsys/include directory) which defines the configurable features of the library.
Figure 7 provides a listing of the default contents of this file.
Figure 7.
Default stxp70_config.h
#ifndef __STXP70_CONFIG_H__
#define __STXP70_CONFIG_H__
/* Definition of clock SR */
#ifndef VIRTUAL_PLATFORM_HCE_STXP70
#define PERIPH_CLK
12.5 /* in MHz */
/* hw dependent: value to be changed by user */
#define CORE_CLK
50 /* in MHz */
/* hw dependent: value to be changed by user */
#else
#define PERIPH_CLK
26 /* in MHz */ /* hw dependent: no impact in TLM */
#define CORE_CLK
52 /* in MHz */ /* hw dependent: no impact in TLM */
#endif
#define ITC_NUMBER_MAX 0x1F /* ITC implementation dependent */
#define IT_NMI
31 /* ITC implementation dependent */
// In case of dynamic management of interrupt vector table
#define DYNAMIC_VECTOR_HANDLER_SETUP
#define MAX_TIMER_NB 0x4 /* TCU implementation dependent */
#define IT_TCU_GLB0
#define IT_TCU_GLB1
#endif
2 // Mapping to IT_2
3 // Mapping to IT_3
/* __STXP70_CONFIG_H__ */
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This header file must be included in the application when using the STxP70 system library.
The global header file stxp70_system.h includes this file by default, therefore the only
include required is:
#include &quot;stxp70_system.h&quot;
Note:
It is important to ensure that peripheral and core clock frequencies defined in the toolset
system library configuration file match the values set in the mapping file. This means that
the toolset system library configuration file will need to be modified and the library rebuilt,
see Section 4.6: Building and using the STxP70 system library on page 23.
4.1.1
Unsupported features
The following features are not supported in the current implementation of the library:
●
●
4.2
unsupported ITC functions:
–
fast interrupts
–
address offset field bit does not exist in MIC registers (interrupts registers); the
address offset is equal to 1 word by default
–
multi-thread context
unsupported TCU functions:
–
chaining three or four timers or counters is not implemented (chaining two timers
or counters is implemented)
–
multi-threading
Naming conventions
All functions and macros are prefixed by the name of the module. The name of the module
is separated from the rest of symbol name by an underscore (_). Function names are
written in lower case and macros are written in CAPITALS.
For example, TCU_init() is a function and TCU_SET_BIT() is a macro in the TCU
module.
4.3
Type definition
The file stxp70_type.h contains common macros (such as set, clear, and read register
bitmasks), bit descriptions, and standard definitions for data types. Figure 8 provides a
listing of stxp70_type.h.
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The STxP70 system library
Figure 8.
stxp70_type.h
#ifndef __STXP70TYPE_H
#define __STXP70TYPE_H
#include &lt;stdbool.h&gt;
#define stxP70_boolean bool
typedef
typedef
typedef
typedef
typedef
typedef
typedef
typedef
char stxP70_int8; /* signed 8 bits integer */
unsigned char stxP70_byte; /* unsigned 8 bits integer */
short stxP70_int16; /* signed 16 bits integer */
unsigned short stxP70_word16; /* unsigned 16 bits integer */
int stxP70_int32; /* signed 32 bits integer */
unsigned int stxP70_word32; /* unsigned 32 bits integer */
long long stxP70_int64; /* signed 64 bits integer */
unsigned long long stxP70_word64; /* unsigned 64 bits integer */
#ifndef NULL
#define NULL 0
#endif
/* Define for IO register */
typedef volatile stxP70_word32 stxP70_tRegister;
/* set clear configuration register */
typedef struct {
stxP70_tRegister val;
/* direct value register */
stxP70_tRegister set;
/* set register
*/
stxP70_tRegister clear;
/* clear register
*/
stxP70_tRegister toggle;
/* toggle register */
} Config_Register_st ;
/* Generic Macro
*/
#define STXP70_SET_BIT(reg,mask)
(reg |= (stxP70_tRegister)(mask))
#define STXP70_CLEAR_BIT(reg,mask)
#define STXP70_READ_BIT(reg,mask)
(reg &amp;= (stxP70_tRegister)(~(mask)))
(reg &amp; (stxP70_tRegister)(mask))
#define STXP70_WRITE_BIT(reg,val,mask)
(stxP70_tRegister)(~(mask))) \
(reg = ((reg &amp;
| ((val)&amp;(stxP70_tRegister)(mask))))
#define STXP70_READ_REG(reg)
(reg)
#define STXP70_WRITE_REG(reg,val) (reg = (val))
#define STXP70_TEST_BIT(reg,mask) STXP70_READ_BIT(reg,mask)
#define STXP70_BIT_0
#define STXP70_BIT_1
Note:
0x0001
0x0002
1
The standard register type stxP70_tRegister is defined as an unsigned 32-bit register
(that is, a 32-bit word).
2
This header also defines generic bitmasks, for example the mask STXP70_BIT_n, where n
stands for a given bit within a register. (The least significant bit is designated as bit 0.)
3
The #ifndef command is used to avoid the problem of multiple declarations of the same
mask or macros if this file is included more than once.
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Generic driver implementation
This section provides a brief introduction to the basic principles involved in creating a driver
for an STxP70 peripheral. Not all of the peripherals, however, use a mechanism that is as
simple as the one described below (please see the specific sections in this user guide that
describe the individual peripherals for more information on drivers for those peripherals).
For example, access to the interrupt controller is organized differently as it is associated
with the X3 extension.
As the behavior of peripherals and controllers depends upon the values of their I/O
registers, a peripheral driver controls a peripheral by programming the memory mapped I/O
registers of that peripheral. The drivers therefore operate by reading or writing given values
at specific memory addresses.
4.4.1
Peripheral I/O registers
All registers are 32 bits wide. Some of the registers and specific bits within registers are
reserved. Any bit marked as reserved should always be read as 0.
Each peripheral has a given number of 32-bit control registers mapped at specific
addresses within the memory of the system. From a software point of view, these
peripherals are managed by means of a C struct. This structure is created and located
(by using the __attribute__ directive) at the base address of the corresponding I/O
space. Each field of the struct is therefore superimposed over one of the I/O registers of
the peripheral; the register can be read to or written from by reading or writing the equivalent
field in the struct.
A simple example of a peripheral driver implementation
The driver for a hypothetical peripheral called MyPeriph requires three source files:
●
stxp70_MyPeriph_regs.h
●
stxp70_MyPeriph.h
●
stxp70_MyPeriph.c
The file stxp70_MyPeriph_regs.h contains the definition of a struct for accessing the
I/O registers. For the purposes of this example, the peripheral MyPeriph has two 32-bit
registers; therefore the struct MYPERIPH_Register_st correspondingly has two fields,
both of which have a type of stxP70_tRegister.
Note:
The typedef for stxP70_tRegister is in stxp70_type.h.
As individual bits within a given register may have their own specific significance, bitmasks
for referencing a specific bit or set of bits within a register can be defined in this file. For
example, if bit 0 of the register MYPERIPH_REG1 is called CLK_EN, then a macro
MYPERIPH_CLK_EN can be defined to create a bitmask for this bit(a). All subsequent access
to the CLK_EN bit can then be performed by applying the mask MYPERIPH_CLK_EN to the
field MYPERIPH_REG1.
Figure 9 shows a listing of the example stxp70_MyPeriph_regs.h file.
a. A set of generic masks called STXP70_BIT_n, where n is the number of a bit within the register from 0 to 31,
are specifically provided for this purpose.
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The STxP70 system library
Figure 9.
Simple example stxp70_MyPeriph_regs.h
#include &lt;stxp70_type.h&gt;
typedef struct {
stxP70_tRegister MYPERIPH_REG1;
stxP70_tRegister MYPERIPH_REG2;
} MYPERIPH_Register_st
#define MYPERIPH_CLK_EN STXP70_BIT_0
The file stxp70_MyPeriph.h contains all the macros required to enable read and write
operations into the I/O registers of the peripheral. This file declares one or more instances of
the typedef MYPERIPH_Register_st (defined in the stxp70_MyPeriph_regs.h file)
as an extern structure. It also defines generic macros for the peripheral (for example, a
macro to set any bit of any register, as in the macro MYPERIPH_SET_BIT in the example
listing in Figure 10); and from these generic macros it may also define specific macros (as
with the macro MYPERIPH_ENABLE_CLK in the example, which uses MYPERIPH_SET_BIT
in order to set the MYPERIPH_CLK_EN bit in the register represented by the field
MYPERIPH_REG1).
Figure 10. Simple example stxp70_MyPeriph.h
#include “stxp70_MyPeriph_regs.h”
extern volatile MYPERIPH_Register_st MYPERIPH_Register;
#define MYPERIPH_SET_BIT(reg, mask) \
STXP70_SET_BIT(MYPERIPH_Register.reg, mask)
#define MYPERIPH_ENABLE_CLK() \
MYPERIPH_SET_BIT(MYPERIPH_REG1, MYPERIPH_CLK_EN)
The file stxp70_MyPeriph.c contains all the functions required to configure the
peripheral by reading and writing its registers. The file must declare one or more instances
of a struct of the type MYPERIPH_Register_st, using the __attribute__ directive to
ensure that this struct is the only variable stored within a named data section. See
Figure 11 for an example of a struct declaration MYPERIPH _Register, to be placed
within a data section named &quot;.stxp70_myperiph&quot;.
Figure 11. Simple example stxp70_MyPeriph.c
#include &lt;stxp70_system.h&gt;
#include &quot;stxp70_MyPeriph.h&quot;
volatile MYPERIPH _Register_st __attribute__ ((section (&quot;.stxp70_myperiph&quot;)))
MYPERIPH _Register;
Note:
\
The __attribute__ directive is an extension to the C language available for the compiler
supplied as part of the STxP70 toolset. See the STxP70 compiler user manual (8027948)
for more information.
Finally, a linker section map places this named data section at the correct location in the
memory of the I/O device. The address of the struct is specified in the link file
(stxp70.ld file), as in the example in Figure 12.
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Figure 12. Simple example stxp70.ld
MEMORY
{ ...
MYPERIPH(rw) : org = 0xXXXXXXXX, len = XXM
/* My Peripheral */
...
}
...
SECTIONS
{ ...
.stxp70_ myperiph 0xXXXXXXXX NOINIT : { *(.stxp70_ myperiph) } &gt; MYPERIPH
...
}
The value given in Figure 12 as 0xXXXXXXXX must be replaced with the address of the
origin of the memory space of the peripheral’s registers.
Any application that uses this driver can now transparently reference the registers of the
peripheral by reading from and writing to the fields of the struct MyPeriph_Register
defined in stxp70_MyPeriph.c.
4.5
Library contents
Table 2 lists the files provided in the sub folders of the system library:
&lt;toolset_installation_directory&gt;/stxpc70cc/4.3/src/lib/libsys/.
Table 2.
Organization of the system library
Name
Description
Directory
Global header file
Main header file. Must be included in the source of the
project.
/include
stxp70_config.h
Definition of configurable features.
/include
stxp70_type.h
Standard definition of the library’s data types.
/include
stxp70_core.h
stxp70_core.c
stxp70_core_asm.s
Global core instructions.
/include
/src
/src
stxp70_system.h
Common files
Files relating to ITC module
stxp70_itc.h
stxp70_itc.c
stxp70_itc_asm.s
C macros and functions required to access the ITC.
/include
/src
/src
it_vectors.h
it_vectors.s
Interrupt vector table definition (static case).
/include
/src
Files relating to TCU module
stxp70_tcu_regs.h
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Definition of the C struct for accessing memorymapped registers and definition of the masks for
accessing specific bits of the Timer Counter Unit (TCU)
registers.
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The STxP70 system library
Table 2.
Organization of the system library (continued)
Name
4.6
Description
Directory
stxp70_tcu.h
stxp70_tcu.c
C macros and functions required to access the TCU.
/include
/src
stxp70_init.h
stxp70_init.c
A function required to compute the Division Factor and
resolution according the peripheral clock.
/include
/src
Building and using the STxP70 system library
The STxP70 library stxp70system.a should be rebuilt in order to match the BSP
requirements in terms of peripheral configurations. The clock values are provided in
Appendix A: FPGA design summary on page 29 of this document.
The build guidelines are described in the application note Building STxP70 libraries
(8226669).
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The STxP70 board support package library
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The STxP70 board support package library
The STxP70 board support package library (stxp70_bsplib) supports the following
peripherals:
●
general purpose I/Os (GPIOs)
●
liquid crystal displays (LCD)
●
asynchronous serial controller (ASC)
This library contains the software drivers dedicated to the configuration and the control of
these peripherals. The library consists mainly of bitmasks and macro definitions, although
some simple functions (designed to give a good compromise between performance and
code size) are also provided.
This library is provided through the board support package only.
5.1
File structure
After the STxP70 BSP has been imported as described in Chapter 1: Package description
on page 4, the BSP content is organized as shown in Table 3.
Table 3.
Organization of the BSP
Directory
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Description
/STxP70bsplib
The BSP workspace directory containing all example
directories with the main source file (provided as an example
of generic source code using the system library and the BSP
library).
/STxP70bsplib/include
This directory contains the header files (.h).
/STxP70bsplib/lib
This directory contains the built library.
/STxP70bsplib/link
This directory contains the link script file defining the memory
mapping for the C structures that represent the peripheral
registers.
/STxP70bsplib/obj
This directory contains the object files generated during the
build of the library.
/STxP70bsplib/stxp70_bsplib
This directory contains the source files, both C code (.c) and
assembly code (.asm), and the makefile used to build the
BSP library.
/STxP70bsplib/tools
This directory contains the drivers to install on the PC to use
the ASC0 (with the USB connection).
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5.2
The STxP70 board support package library
Supported architecture and configuration
This version of the library has been tested on PC environment (Windows XP). The board
support package was tested using the STxP70 Professional Toolset R2011.2.
A configuration file config.h (located in the /STxP70bsplib/include directory) is
provided. The config.h file defines the configurable features for the library. The first half
of this file reflects the content of the stxp70_config.h file of the system library (this is
because the BSP library uses many of the same features). The second half is as shown in
Figure 13.
Figure 13. Configuration file, config.h
/*--------------------------------------------------*/
/*
Specific configurable features */
/*---------------------------------------------------*/
#ifndef __STXP70_SP_CONFIG_H__
#define __STXP70_SP_CONFIG_H__
/* definition of the
#define IT_GPIO_LSB
#define IT_GPIO_MSB
#define IT_TCU_GLB0
#define IT_TCU_GLB1
#define IT_ASC0_TBE
#define IT_ASC0_RBF
#define IT_ASC1_TBE
#define IT_ASC1_RBF
#define IT_ASCS_ERRORS
/* masks to define
#define GPIO_LSB_RQ
#define GPIO_MSB_RQ
#define TCU_GLB_RQ0
#define TCU_GLB_RQ1
#define ASC0_TBE_IRQ
#define ASC0_RBF_IRQ
#define ASC1_TBE_IRQ
#define ASC1_RBF_IRQ
#define ASCS_ERRORS
#endif
5.3
interrupt lines for the peripherals */
0 /* mapping to IT_0 */
1 /* mapping to IT_1 */
2 /* mapping to IT_2 */
3 /* mapping to IT_3 */
4 /* mapping to IT_4 */
5 /* mapping to IT_5 */
6 /* mapping to IT_6 */
7 /* mapping to IT_7 */
8 /* mapping to IT_8 */
the interrupt mask */
STXP70_BIT_0
STXP70_BIT_1
STXP70_BIT_2
STXP70_BIT_3
STXP70_BIT_4
STXP70_BIT_5
STXP70_BIT_6
STXP70_BIT_7
STXP70_BIT_8
/* __STXP70_SP_CONFIG_H__ */
Naming convention
All functions and macros are prefixed by the name of the module. They are separated by an
underscore from the rest of symbol name. Macro names are written in capitals.
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Type definition
The file STxP70_type.h contains standard definitions for data types, common macros
(set, clear, read register bits according masks) used by the library, and bit descriptions. It is
identical to the equivalent file in the system library, except for the addition of the code shown
in Figure 14.
Figure 14. Extract from STxP70_type.h]
/*-----------------------------------------*/
/*
Specific type definition */
/*-----------------------------------------*/
#ifndef _STXP70_SP_TYPE_H
#define _STXP70_SP_TYPE_H
#define STXP70_CR
&quot;\r\n&quot;
#endif /* _STXP70_SP_TYPE_H */
This code defines the carriage-return mask that is required for specific programs such as
those using the ASC.
5.5
Generic driver implementation
The basic implementation of the drivers in the BSP library is the same as for the system
library. Please refer to the generic driver implementation for the system library in
Section 4.4: Generic driver implementation on page 20.
5.6
Library contents
For each hardware component, there is a specific file which contains the definitions and the
specific routines to control it. Table 4 lists the different files provided with the BSP library.
Table 4.
Organization of the BSP library
Name
Description
Directory
Global header file
stxp70_bsp.h
The main header file that must be included in the source
/include
of the project.
Common files
stxp70_config.h
Description of configurable features.
/include
stxp70_type.h
Standard definition of the data types.
/include
Files related to GPIO module
stxp70_gpio_regs.h
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C structure definition to access memory mapped
registers and masks definition to access specific bit of
the registers of the general purpose I/O (GPIO).
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The STxP70 board support package library
Table 4.
Organization of the BSP library (continued)
Name
stxp70_gpio.h
stxp70_gpio.c
Description
C macros and functions to use the GPIO.
Directory
/include
/src
Files related to LCD module
stxp70_lcd.h
stxp70_lcd.c
C macros and functions to use the LCD.
/include
/src
Files related to ASC module
stxp70_asc_regs.h
C structure definition to access memory mapped
registers and masks definition to access specific bit of
/include
the registers of the asynchronous serial controller (ASC).
stxp70_asc.h
stxp70_asc.c
C macros and functions to use the ASC.
/include
/src
makefile
Generates the library.
/src
stxp70bsp.ld
Link file.
/link
Specific files
5.7
Building and using the STxP70 BSP library
The STxP70 library libstxp70bsp.a can be rebuilt under STWorkbench by right-clicking
on the stxp70_bsplib project and selecting the rebuild option.
Note:
The makefile copies the BSP library into the lib folder used by the different examples
(described in Section 1.2.1: Example_ASC0_LCD on page 5 to Section 1.2.6:
Example_TCU on page 8).
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Reference documents
6
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Reference documents
The following STMicroelectronics documentation can be found on the STMicroelectronics
website: www.st.com:
●
STxP70 professional toolset user manual (7833754)
●
STxP70 compiler user manual (8027948)
●
Building STxP70 libraries Application Note (8226669)
●
ST Micro Connect 2 host-target interface datasheet (7912386)
The following documents can be obtained from your ST FAE on request:
●
STxP70 standard peripherals reference manual (8073766)
●
STxP70-4 core and instruction set architecture reference manual (8154580)
●
STxP70-4 processor supercore datasheet (8270160)
Xilinx documentation can be obtained from http://www.Xilinx.com and then by selecting the
Support tab followed by the Product Support and Documentation tab. Search for the
following titles:
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●
Xilinx UG534 ML605 Hardware, User Guide V1.6
●
Xilinx UG537 FMC XM105 Debug Card, User Guide
●
Xilinx UG533 Getting Started with the Virtex-6 FPGA ML605
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FPGA design summary
Appendix A
FPGA design summary
FPGA design summary content :
#############################
- FPGA mapping identification on LCD: &quot;STxP70S4Br3 DEMO 27.01.12 100MHz&quot;
=====================================
- Mapped Configuration : STxP70 core : S4B.r3 - CORE_CFG = 0x4A5AA82A / CORE_CFG1 =
0xc00
========================
- Core configuration :
---------------------Core parameters : Dual issue
: Yes
Second ALU
: Yes
Number of contexts : 4
Register File
: 1 register bank per context
(32 registers for Ctxt0 after reset)
Hardware loops
: 2 per context
Multiplier
: Yes
EFU : EFU interface : No
MFU : MFU interface : No
EVC : EVC : Yes
EVC Global events : 16
EVC Local events : 16
ITC : ITC available : Yes
Number of maskable interrupts : 15 (+1 non maskable interrupt)
Memory Parameters :
Data Memory : Internal Data Memory : Yes
Internal Data Memory Size : 128 kBytes
Data Cache : No
Program Memory : Internal Program Memory : Yes
Internal Program Memory size : 128 kBytes
Program Cache : No
External Memory : EXTM Interface : Yes
EXTM Interface Data size : STBus Type3 64 bits
ROM Patch : Internal Rom Patch : No
Synthesis Parameter : FPGA Mapping : Yes
Scan insertion : No
Scan chains number : Not Applicable
- STxP70 Extensions : No
---------------------
- Clock frequencies :
=====================
Core
: 100.00 Mhz (200*5/1/10)
Periph : 100.00 Mhz (200*5/1/10)
DDR3
: 200.00 Mhz (200*5/1/5)
- Memory mapping :
==================
MemoryMap = DRAM
MemoryMap = PRAM
MemoryMap = ERAM (DDR)
MemoryMap = INTFSMCR
MemoryMap = FLASH
MemoryMap = IPE
0x00000000
0x00400000
0x00800000
0x03000000
0x10000000
0xFF000000
0x00020000
0x00020000
0x02000000
0x00010000
0x1C000000
0x01000000
rw
rwx
rwx
rw
rwx
rw
(size is 128kBytes)
(size is 128kBytes)
(size is 32 MBytes)
- Switches :
============
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FPGA design summary
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DIP_SW(1)
DIP_SW(2)
DIP_SW(3)
DIP_SW(4)
DIP_SW(5)
:
:
:
:
:
ROM enable (not applicable on this mapping)
Reset Address ('0'=0x40_0000; '1'=0x80_0000)
IT disabling mode ('0'=mode off; '1'=mode on)
Fetch enable ('0'=fetch disable; '1'=fetch enable)
Wake up ('0'=no wake-up; '1'=wake-up)
- Peripherals :
===============
- ASC
ASC0 is mapped at address 0xFF00_0000.
RX and TX are wired on USB through an asynchronous serial to USB interface, a
windows USB driver allows COM usage of this interface.
Interrupt asc0_tbe_irq is connected to MI4 STxP70 IT line
Interrupt asc0_rbf_irq is connected to MI5 STxP70 IT line
ASC1 is mapped at address 0xFF00_1000.
Interrupt asc1_tbe_irq is connected to MI6 STxP70 IT line
Interrupt asc1_rbf_irq is connected to MI7 STxP70 IT line
ASC0 and ASC1 errors interrupts outputs ored on MI8 STxP70 IT line
- TCU
TCU0 is mapped at address 0xFF02_0000.
No outputs are available, but see event paragraph.
No Inputs are available.
Interrupt tcu_glb_rq0 (OR of it rq 0 to 7) is connected to MI2 STXP70 IT line.
Iterrupt tcu_glb_rq1 (OR of it rq 8 to 15) is connected to MI3 STXP70 IT line.
- GPIO
GPIO is mapped at address 0xFF05_0000
Iterrupt gpio_lsb_rq is connected to MI0 STXP70 IT line.
Interrupt gpio_msb_rq is connected to MI1 STXP70 IT line.
LED(1)
LED(2)
LED(3)
LED(4)
&lt;=
&lt;=
&lt;=
&lt;=
not tap_reset_ni
not reset_ni
idle0_o
idle1_o
when
when
when
when
GPIO_out(31)='0'
GPIO_out(31)='0'
GPIO_out(31)='0'
GPIO_out(31)='0'
else
else
else
else
not
not
not
not
GPIO_out(0);
GPIO_out(1);
GPIO_out(2);
GPIO_out(3);
GPIO_in(31 downto 0) &lt;= &quot;0000&quot; &amp; &quot;0000&quot; &amp; &quot;0000&quot; &amp; &quot;0000&quot; &amp; DIP(8 downto 1) &amp;
&quot;0000&quot; &amp; GPIO_SW_N &amp; GPIO_SW_E &amp; GPIO_SW_S &amp; GPIO_SW_W;
gpio_LCD_DB &lt;= GPIO_out(23 downto 16);
gpio_LCD_E &lt;= GPIO_out(24);
gpio_LCD_RS &lt;= GPIO_out(25);
- LCD display
allows to show some information on the FPGA contents (IP,
mapping date), and using push button 3 some static values such as:
&quot;tcpm rom
(1)= &quot;, DIP_SW(1) value
&quot;evb_ivb_cfg(2)= &quot;, DIP_SW(2) value
&quot;it_dis_mode(3)= &quot;, DIP_SW(3) value
&quot;p_fetch_en (4)= &quot;, DIP_SW(4) value
&quot;wake_up_i (5)= &quot;, DIP_SW(5) value
&quot;idle0
= &quot;, STxP70 idle0 value
&quot;idle1
= &quot;, STxP70 idle1 value
-- LCD drive source
LCD_DB(7 downto 4) &lt;= fpga_LCD_DB when GPIO_out(31)='0' else GPIO_out(23 downto
20);
LCD_E
&lt;= fpga_LCD_E when GPIO_out(31)='0' else GPIO_out(24);
LCD_RS
&lt;= fpga_LCD_RS when GPIO_out(31)='0' else GPIO_out(25);
- FSMC + FLASH
FSMC is mapped at address 0x300_0000
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Revision history
Revision history
Table 5.
Document revision history
Date
Revision
19-Apr-2012
1
Changes
Initial release.
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