Features BlueCore® CSR8635 QFN General Description Applications

Features BlueCore® CSR8635 QFN General Description Applications

Features

Bluetooth

®

v4.0 specification compliant

80MHz RISC MCU and 80MIPS Kalimba DSP

Stereo codec with 1 microphone input

Internal ROM, serial flash memory and EEPROM interfaces

High-performance Stereo codec

Radio includes integrated balun with RF performance of 8dBm transmit power and -89dBm receiver sensitivity

AVRCP v1.4

5-band fully configurable EQ

Wideband speech supported by HFP v1.6 and mSBC codec

CSR's latest CVC technology for narrowband and wideband voice connections including wind noise reduction

Multipoint support for A2DP connection to 2

A2DP sources for music playback

Secure simple pairing, CSR's proximity pairing and

CSR's proximity connections

Stereo line-in

Serial interfaces: USB 2.0, UART, I²C and SPI

SBC, MP3 and AAC decoder support

Wired audio support

Integrated dual switch-mode regulators, linear regulators and battery charger

External crystal load capacitors not required for typical crystals

3 LED outputs (RGB)

68-lead QFN 8 x 8 x 0.9mm 0.4mm pitch

Green (RoHS compliant and no antimony or halogenated flame retardants)

XTAL

BT_RF

BlueCore

®

CSR8635 QFN

CSR8635 Stereo ROM Solution

1-mic CVC Audio Enhancement

Fully Qualified Single-chip

Bluetooth

®

v4.0 System

Production Information

CSR8635A04

Issue 5

2.4GHz

Radio

+

Balun

ROM

RAM

Baseband

MCU

Kalimba

DSP

I/O

SPI/I

2

C

UART/USB

PIO

Audio In /Out

Debug SPI

Serial

Flash /

EEPROM

General Description Applications

CSR's BlueCore

®

CSR8635 QFN is a single-chip

Bluetooth ROM audio solution for rapid evaluation and development of Bluetooth ROM stereo applications.

BlueCore

®

CSR8635 QFN consumer audio platform for wired and wireless applications using the QFN package integrates an ultra-low power DSP and application performance stereo codec, a power management subsystem and LED drivers.

Stereo speakers

Speakerphones

1-mic stereo headset or headphones

Handsfree car kits

The enhanced Kalimba DSP coprocessor with 80MIPS supports enhanced audio and DSP applications.

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See

CSR Glossary

at www.csrsupport.com

.

The CSR configuration tools and the development kit provide a flexible and powerful development platform to design advanced and high-quality Bluetooth stereo products using BlueCore

Bluetooth audio solution.

®

CSR8635 QFN single-chip

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Ordering Information

Package

Device

Type Size

Order Number

Shipment

Method

CSR8635 Stereo

ROM Solution

QFN‑68-lead

(Pb free)

8 x 8 x 0.9mm

0.4mm pitch

Tape and reel CSR8635A04‑IQQF‑R

Note:

CSR8635 QFN is a ROM-based device where the product code has the form CSR8635Axx. Axx is the specific

ROM-variant, A04 is the ROM-variant for CSR8635 Stereo ROM Solution.

Minimum order quantity is 2kpcs taped and reeled.

Supply chain: CSR's manufacturing policy is to multisource volume products. For further details, contact your local sales account manager or representative.

Contacts

General information

Information on this product

Customer support for this product

Details of compliance and standards

Help with this document www.csr.com

[email protected]

www.csrsupport.com

[email protected]

[email protected]

CSR8635 Stereo ROM Solution Development Kit Ordering Information

Description

CSR8635 Stereo ROM Solution Audio Development Kit

Order Number

DK‑8635‑10163‑1A

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Device Details

Bluetooth low energy

Dual-mode Bluetooth low energy radio

Support for Bluetooth basic rate / EDR and low energy connections

3 Bluetooth low energy connections at the same time as basic rate A2DP

Bluetooth Radio

On-chip balun (50Ω impedance)

No production trimming of external components

Bluetooth v4.0 specification compliant

Bluetooth Transmitter

UART interface for debug

USB 2.0 (full-speed) interface, including charger enumeration

1-bit SPI flash memory interface

SPI interface for debug and programming

I²C interface for EEPROM

Up to 22 general purpose PIOs with 3 extra opendrain PIOs available when LED not used

PCM and I²S (only in HCI mode) interfaces

3 LED drivers (includes RGB) with PWM flasher independent of MCU

8dBm (typ) RF transmit power with level control

Class 1, Class 2 and Class 3 support, no external

PA or TX/RX switch required

Bluetooth Receiver

-91dBm (typ) π/4 DQPSK receiver sensitivity and

-81dBm (typ) 8DPSK receiver sensitivity

Integrated channel filters

Digital demodulator for improved sensitivity and cochannel rejection

Real-time digitised RSSI available to application

Fast AGC for enhanced dynamic range

Channel classification for AFH

Integrated Power Control and Regulation

Automatic power switching to charger when present

2 high-efficiency switch-mode regulators with 1.8V

and 1.35V outputs direct from battery supply

3.3V linear regulator for USB supply

Low-voltage linear regulator for internal digital circuits

Low-voltage linear regulator for internal analogue circuits

Power-on-reset detects low supply voltage

Power management includes digital shutdown and wake-up commands for ultra-low power modes

Bluetooth Synthesiser

Fully integrated synthesiser requires no external

VCO, varactor diode, resonator or loop filter

Compatible with crystals 16MHz to 32MHz

Kalimba DSP

Enhanced Kalimba DSP coprocessor, 80MIPS,

24‑bit fixed point core

2 single-cycle MACs; 24 x 24-bit multiply and 56-bit accumulator

32-bit instruction word, dual 24-bit data memory

6K x 32-bit program RAM including 1K instruction cache for executing out of internal ROM

16K x 24-bit + 16K x 24-bit 2-bank data RAM

Battery Charger

Lithium ion / Lithium polymer battery charger

Instant-on function automatically selects the power supply between battery and USB, which enables operation even if the battery is fully discharged

Fast charging support up to 200mA with no external components. Higher charge currents using external pass device.

Supports USB charger detection

Support for thermistor protection of battery pack

Support to enable end product design to PSE law:

Design to JIS-C 8712/8714 (batteries)

Testing based on IEEE 1725

Audio Interfaces

Baseband and Software

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Supported sample rates of 8, 11.025, 16, 22.05, 32,

44.1, 48 and 96kHz (DAC only)

Auxiliary Features

■ Crystal oscillator with built-in digital trimming

Package Option

Internal ROM

Memory protection unit supporting accelerated VM

56KB internal RAM, enables full-speed data transfer, and full piconet support

Logic for forward error correction, header error control, access code correlation, CRC, demodulation, encryption bit stream generation, whitening and transmit pulse shaping

68-lead QFN 8 x 8 x 0.9mm 0.4mm pitch

Physical Interfaces

Production Information

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CSR8635 Stereo ROM Solution Details

Bluetooth Profiles

Bluetooth v4.0 specification support

A2DP v1.2

AVRCP v1.4

HFP v1.6

HSP v1.2

DI v1.3

Music Enhancements

Configurable 5-band EQ for music playback (rock, pop, classical, jazz, dance etc)

SBC, MP3, AAC and Faststream decoder

Volume Boost

Stereo Widening (S3D)

Additional Functionality

Support for multi-language programmable audio prompts

CSR's proximity pairing and CSR's proximity connection

Multipoint support for A2DP connection to 2 A2DP sources for music playback

Talk-time extension

CSR8600 ROM Series Configuration Tool

Configures the CSR8635 stereo ROM solution software features:

Bluetooth v4.0 specification features

Reconnection policies, e.g. reconnect on power-on

Audio features, including default volumes

Button events: configuring button presses and durations for certain events, e.g. double press on

PIO for last number redial

LED indications for states, e.g. device connected, and events, e.g. power on

Indication tones for events and ringtones

Battery divider ratios and thresholds, e.g. thresholds for battery low indication, full battery etc.

Advanced Multipoint settings

CSR8635 Stereo ROM Solution Development Kit

Example CSR8635 QFN module design

Carrier board

Output stage: headphone amplifier

Interface adapters and cables

Works in conjunction with the CSR8600 ROM Series

Configuration Tool and other supporting utilities

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Functional Block Diagram

SPI_DEBUG

I

2

C

PIO Serial Flash UART

R G B

SPI

(Debug)

PIO Port

I

2

C/SPI

Master

/Slave

Serial Flash

Interface

UART

4Mbps

LED PWM

Control and

Output

DMA ports

System

RAM

ROM

PM

DM1

DM2

USB

USB v2.0

Full-speed

3.3V

XTAL AIO[0]

Clock

Generation

AUX ADC

Bluetooth Modem

Bluetooth

Baseband

TX

RX

Bluetooth Radio and Balun

BT_RF

80MHz DSP

Memory

Management

Unit

80MHz MCU

VM Accelerator

(MPU)

Audio

Interface

PIO Port

PCM1 / I

2

S

High-quality ADC

High-quality ADC

High-quality DAC

High-quality DAC

LINE/MIC_AN

LINE/MIC_AP

LINE_BN

LINE_BP

SPKR_LN

SPKR_LP

SPKR_RN

SPKR_RP

VDD_AUDIO

VDD_AUDIO_DRV

MIC_BIAS

Voltage / Temperature

Monitor

MIC Bias

Switch

PMU

Interface and

BIST

Engine

0.85V to

1.2V

Low-voltage

VDD_DIG

Linear

Regulator

SENSE

1.35V

Low-voltage

VDD_ANA

Linear

Regulator

SENSE

1.35V

Low-voltage

VDD_AUX

Linear

Regulator

SENSE

1.8V

Switchmode

Regulator

SENSE

1.35V

Switchmode

Regulator

SENSE

Bypass

LDO

SENSE

Li-ion

Charger

VBAT

VBAT_SENSE

CHG_EXT

VCHG

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Document History

Revision Date

1 19 JUL 13

2 20 AUG 13

3

4

5

13 SEP 13

23 SEP 13

24 SEP 13

Change Reason

Original publication of this document.

Updates include:

Engineering Sample release added.

RF specification.

PCB design and assembly considerations.

MIC_BN and MIC_BP to LINE_BN and LINE_BP.

AVRCP v1.4 added.

HFP and HSP profiles added.

PCM interface for HCI only.

Minor editorial updates.

Updates include:

Pre-production Information added.

Development kit information.

Package dimensions.

Example application schematic.

Updates include:

Production Information added.

Ordering information.

RF specification.

Package information.

VDD_DIG_MEM signal name corrected to VDD_DIG.

SPI_PCM#_SEL signal name corrected to SPI_PCM#.

Example application schematic.

Audio codec parameters.

Power consumption.

Minor editorial updates.

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Status Information

The status of this Data Sheet is Production Information. CSR Product Data Sheets progress according to the following format:

■ Advance Information:

■ Information for designers concerning CSR product in development. All values specified are the target values of the design.

Minimum and maximum values specified are only given as guidance to the final specification limits and must not be considered as the final values.

■ Engineering Sample:

■ Information about initial devices. Devices are untested or partially tested prototypes, their status is described in an

Engineering Sample Release Note. All values specified are the target values of the design. Minimum and maximum values specified are only given as guidance to the final specification limits and must not be considered as the final values.

■ All detailed specifications including pinouts and electrical specifications may be changed by CSR without notice.

■ Pre-production Information:

■ Pinout and mechanical dimension specifications finalised. All values specified are the target values of the design. Minimum and maximum values specified are only given as guidance to the final specification limits and must not be considered as the final values.

■ All electrical specifications may be changed by CSR without notice.

■ Production Information:

■ Final Data Sheet including the guaranteed minimum and maximum limits for the electrical specifications.

■ Production Data Sheets supersede all previous document versions.

Device Implementation

Important Note:

As the feature-set of the CSR8635 QFN is firmware build-specific, see the relevant software release note for the exact implementation of features on the CSR8635 QFN.

Life Support Policy and Use in Safety-critical Applications

CSR's products are not authorised for use in life-support or safety-critical applications. Use in such applications is done at the sole discretion of the customer. CSR will not warrant the use of its devices in such applications.

CSR Green Semiconductor Products and RoHS Compliance

CSR8635 QFN devices meet the requirements of Directive 2002/95/EC of the European Parliament and of the Council on the

Restriction of Hazardous Substance (RoHS). CSR8635 QFN devices are free from halogenated or antimony trioxide-based flame retardants and other hazardous chemicals. For more information, see CSR's

Environmental Compliance Statement for CSR Green

Semiconductor Products

.

Trademarks, Patents and Licences

Unless otherwise stated, words and logos marked with ™ or ® are trademarks registered or owned by CSR plc or its affiliates.

Bluetooth

®

and the Bluetooth

®

logos are trademarks owned by Bluetooth

®

SIG, Inc. and licensed to CSR. Other products, services and names used in this document may have been trademarked by their respective owners.

The publication of this information does not imply that any license is granted under any patent or other rights owned by CSR plc and/or its affiliates.

CSR reserves the right to make technical changes to its products as part of its development programme.

While every care has been taken to ensure the accuracy of the contents of this document, CSR cannot accept responsibility for any errors.

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Refer to www.csrsupport.com

for compliance and conformance to standards information.

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7

8

1

2

3

4

5

6

Contents

Ordering Information ........................................................................................................................................... 2

Contacts ..................................................................................................................................................... 2

CSR8635 Stereo ROM Solution Development Kit Ordering Information ................................................... 2

Device Details ..................................................................................................................................................... 3

CSR8635 Stereo ROM Solution Details .............................................................................................................. 4

Functional Block Diagram .................................................................................................................................. 5

Package Information ......................................................................................................................................... 13

1.1 Pinout Diagram ........................................................................................................................................ 13

1.2 Device Terminal Functions ....................................................................................................................... 14

1.3 Package Dimensions ............................................................................................................................... 20

1.4 PCB Design and Assembly Considerations ............................................................................................. 21

1.5 Typical Solder Reflow Profile ................................................................................................................... 21

Bluetooth Modem .............................................................................................................................................. 22

2.1 RF Ports ................................................................................................................................................... 22

2.1.1

BT_RF ........................................................................................................................................ 22

2.2 RF Receiver ............................................................................................................................................. 22

2.2.1

Low Noise Amplifier .................................................................................................................... 22

2.2.2

RSSI Analogue to Digital Converter ........................................................................................... 22

2.3 RF Transmitter ......................................................................................................................................... 22

2.3.1

IQ Modulator ............................................................................................................................... 22

2.3.2

Power Amplifier .......................................................................................................................... 23

2.4 Bluetooth Radio Synthesiser .................................................................................................................... 23

2.5 Baseband ................................................................................................................................................. 23

2.5.1

Burst Mode Controller ................................................................................................................. 23

2.5.2

Physical Layer Hardware Engine ............................................................................................... 23

Clock Generation ............................................................................................................................................... 24

3.1 Crystal ...................................................................................................................................................... 24

3.1.1

Negative Resistance Model ........................................................................................................ 25

3.1.2

Crystal Specification ................................................................................................................... 25

3.1.3

Crystal Calibration ...................................................................................................................... 25

3.2 Non-crystal Oscillator ............................................................................................................................... 26

3.2.1

XTAL_IN Impedance in Non-crystal Mode ................................................................................. 27

Bluetooth Stack Microcontroller ......................................................................................................................... 28

4.1 VM Accelerator ......................................................................................................................................... 28

Kalimba DSP ..................................................................................................................................................... 29

6.1 Memory Management Unit ....................................................................................................................... 30

6.2 System RAM ............................................................................................................................................ 30

6.3 Kalimba DSP RAM ................................................................................................................................... 30

6.4 Internal ROM ............................................................................................................................................ 30

6.5 Serial Flash Interface ............................................................................................................................... 30

Serial Interfaces ................................................................................................................................................ 31

7.1 USB Interface ........................................................................................................................................... 31

7.2 UART Interface ........................................................................................................................................ 31

7.3 Programming and Debug Interface .......................................................................................................... 33

7.3.1

Multi-slave Operation .................................................................................................................. 33

7.4 I²C EEPROM Interface ............................................................................................................................. 34

Interfaces ........................................................................................................................................................... 35

8.1 Programmable I/O Ports, PIO .................................................................................................................. 35

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9

8.2 Analogue I/O Ports, AIO ........................................................................................................................... 35

8.3 LED Drivers .............................................................................................................................................. 35

Audio Interface .................................................................................................................................................. 37

9.1 Audio Input and Output ............................................................................................................................ 37

9.2 Audio Codec Interface .............................................................................................................................. 38

9.2.1

Audio Codec Block Diagram ....................................................................................................... 38

9.2.2

ADC ............................................................................................................................................ 38

9.2.3

ADC Sample Rate Selection ...................................................................................................... 38

9.2.4

ADC Audio Input Gain ................................................................................................................ 39

9.2.5

ADC Pre-amplifier and ADC Analogue Gain .............................................................................. 39

9.2.6

ADC Digital Gain ........................................................................................................................ 39

9.2.7

ADC Digital IIR Filter .................................................................................................................. 40

9.2.8

DAC ............................................................................................................................................ 40

9.2.9

DAC Sample Rate Selection ...................................................................................................... 40

9.2.10 DAC Digital Gain ........................................................................................................................ 40

9.2.11 DAC Analogue Gain ................................................................................................................... 40

9.2.12 DAC Digital FIR Filter ................................................................................................................. 41

9.2.13 Microphone Input ........................................................................................................................ 41

9.2.14 Line Input .................................................................................................................................... 42

9.2.15 Output Stage .............................................................................................................................. 42

9.2.16 Mono Operation .......................................................................................................................... 43

9.2.17 Side Tone ................................................................................................................................... 43

9.2.18 Integrated Digital IIR Filter .......................................................................................................... 45

9.3 PCM1 Interface ........................................................................................................................................ 46

9.3.1

PCM Interface Master/Slave ....................................................................................................... 46

9.3.2

Long Frame Sync ....................................................................................................................... 47

9.3.3

Short Frame Sync ....................................................................................................................... 47

9.3.4

Multi-slot Operation .................................................................................................................... 48

9.3.5

GCI Interface .............................................................................................................................. 48

9.3.6

Slots and Sample Formats ......................................................................................................... 48

9.3.7

Additional Features ..................................................................................................................... 49

9.3.8

PCM Timing Information ............................................................................................................. 49

9.3.9

PCM_CLK and PCM_SYNC Generation .................................................................................... 53

9.3.10 PCM Configuration ..................................................................................................................... 53

9.4 Digital Audio Interface (I²S) ...................................................................................................................... 53

10 Power Control and Regulation .......................................................................................................................... 57

10.1 1.8V Switch-mode Regulator ................................................................................................................... 59

10.2 1.35V Switch-mode Regulator ................................................................................................................. 60

10.4 Bypass LDO Linear Regulator ................................................................................................................. 62

10.5 Low-voltage VDD_DIG Linear Regulator ................................................................................................. 63

10.6 Low-voltage VDD_AUX Linear Regulator ................................................................................................ 63

10.7 Low-voltage VDD_ANA Linear Regulator ................................................................................................ 63

10.8 Voltage Regulator Enable ........................................................................................................................ 63

10.9 External Regulators and Power Sequencing ........................................................................................... 63

10.10Reset, RST# ............................................................................................................................................. 63

10.10.1 Digital Pin States on Reset ......................................................................................................... 64

10.10.2 Status After Reset ...................................................................................................................... 64

10.11Automatic Reset Protection ...................................................................................................................... 64

11 Battery Charger ................................................................................................................................................. 65

11.1 Battery Charger Hardware Operating Modes ........................................................................................... 65

11.1.1 Disabled Mode ............................................................................................................................ 66

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11.1.2 Trickle Charge Mode .................................................................................................................. 66

11.1.3 Fast Charge Mode ...................................................................................................................... 66

11.1.4 Standby Mode ............................................................................................................................ 66

11.1.5 Error Mode .................................................................................................................................. 66

11.2 Battery Charger Trimming and Calibration ............................................................................................... 66

11.3 VM Battery Charger Control ..................................................................................................................... 66

11.4 Battery Charger Firmware and PS Keys .................................................................................................. 66

11.5 External Mode .......................................................................................................................................... 67

12 Example Application Schematic ........................................................................................................................ 68

13 Electrical Characteristics ................................................................................................................................... 70

13.1 Absolute Maximum Ratings ..................................................................................................................... 70

13.2 Recommended Operating Conditions ...................................................................................................... 71

13.3 Input/Output Terminal Characteristics ...................................................................................................... 72

13.3.1 Regulators: Available For External Use ...................................................................................... 72

13.3.2 Regulators: For Internal Use Only .............................................................................................. 74

13.3.3 Regulator Enable ........................................................................................................................ 75

13.3.4 Battery Charger .......................................................................................................................... 75

13.3.5 USB ............................................................................................................................................ 77

13.3.6 Stereo Codec: Analogue to Digital Converter ............................................................................. 78

13.3.7 Stereo Codec: Digital to Analogue Converter ............................................................................. 79

13.3.8 Digital .......................................................................................................................................... 80

13.3.9 LED Driver Pads ......................................................................................................................... 80

13.3.10 Auxiliary ADC ............................................................................................................................. 81

13.3.11 Auxiliary DAC ............................................................................................................................. 81

13.4 ESD Protection ......................................................................................................................................... 82

13.4.1 USB Electrostatic Discharge Immunity ....................................................................................... 82

14 Power Consumption .......................................................................................................................................... 84

15 CSR Green Semiconductor Products and RoHS Compliance .......................................................................... 87

16 Software ............................................................................................................................................................ 88

16.1 CSR8635 Stereo ROM Solution ............................................................................................................... 88

16.1.1 Advanced Multipoint Support ...................................................................................................... 89

16.1.2 A2DP Multipoint Support ............................................................................................................ 89

16.1.3 Wired Audio Mode ...................................................................................................................... 89

16.1.4 USB Modes Including USB Audio Mode .................................................................................... 89

16.1.5 Smartphone Applications (Apps) ................................................................................................ 90

16.1.6 Programmable Audio Prompts ................................................................................................... 90

16.1.7 CSR’s Intelligent Power Management ........................................................................................ 91

16.1.8 Proximity Pairing ......................................................................................................................... 91

16.2 6 th

Generation 1-mic CVC ENR Technology for Hands-free and Audio Enhancements ......................... 92

16.2.1 Acoustic Echo Cancellation ........................................................................................................ 92

16.2.2 Noise Suppression with Wind Noise Reduction ......................................................................... 93

16.2.3 Non-linear Processing (NLP) ...................................................................................................... 93

16.2.4 Howling Control (HC) .................................................................................................................. 93

16.2.5 Comfort Noise Generator ........................................................................................................... 93

16.2.6 Equalisation ................................................................................................................................ 93

16.2.7 Automatic Gain Control .............................................................................................................. 93

16.2.8 Packet Loss Concealment .......................................................................................................... 93

16.2.9 Adaptive Equalisation (AEQ) ...................................................................................................... 94

16.2.10 Auxiliary Stream Mix ................................................................................................................... 94

16.2.11 Clipper ........................................................................................................................................ 94

16.2.12 Noise Dependent Volume Control .............................................................................................. 94

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16.2.13 Input Output Gains ..................................................................................................................... 94

16.3 Music Enhancements ............................................................................................................................... 95

16.3.1 Audio Decoders .......................................................................................................................... 95

16.3.2 Configurable EQ ......................................................................................................................... 95

16.3.3 Stereo Widening (S3D) ............................................................................................................... 95

16.3.4 Volume Boost ............................................................................................................................. 96

16.4 CSR8635 Stereo ROM Solution Development Kit ................................................................................... 96

17 Tape and Reel Information ................................................................................................................................ 97

17.1 Tape Orientation ...................................................................................................................................... 97

17.2 Tape Dimensions ..................................................................................................................................... 98

17.3 Reel Information ....................................................................................................................................... 99

17.4 Moisture Sensitivity Level ......................................................................................................................... 99

18 Document References ..................................................................................................................................... 100

Terms and Definitions .............................................................................................................................................. 101

List of Figures

Figure 1.1

Device Pinout ....................................................................................................................................... 13

Figure 2.1

Simplified Circuit BT_RF ...................................................................................................................... 22

Figure 3.1

Crystal Oscillator Overview .................................................................................................................. 24

Figure 5.1

Kalimba DSP Interface to Internal Functions ....................................................................................... 29

Figure 6.1

Serial Flash Interface ........................................................................................................................... 30

Figure 7.1

Universal Asynchronous Receiver ....................................................................................................... 32

Figure 7.2

Example I²C EEPROM Connection ..................................................................................................... 34

Figure 8.1

LED Equivalent Circuit ......................................................................................................................... 36

Figure 9.1

Audio Interface ..................................................................................................................................... 37

Figure 9.2

Audio Codec Input and Output Stages ................................................................................................ 38

Figure 9.3

Audio Input Gain .................................................................................................................................. 39

Figure 9.4

Microphone Biasing ............................................................................................................................. 41

Figure 9.5

Differential Input ................................................................................................................................... 42

Figure 9.6

Single-ended Input ............................................................................................................................... 42

Figure 9.7

Speaker Output .................................................................................................................................... 43

Figure 9.8

Side Tone ............................................................................................................................................ 44

Figure 9.9

PCM Interface Master .......................................................................................................................... 46

Figure 9.10 PCM Interface Slave ............................................................................................................................ 47

Figure 9.11 Long Frame Sync (Shown with 8-bit Companded Sample) ................................................................. 47

Figure 9.12 Short Frame Sync (Shown with 16-bit Sample) ................................................................................... 47

Figure 9.13 Multi-slot Operation with 2 Slots and 8-bit Companded Samples ........................................................ 48

Figure 9.15 16-bit Slot Length and Sample Formats .............................................................................................. 49

Figure 9.16 PCM Master Timing Long Frame Sync ................................................................................................ 50

Figure 9.17 PCM Master Timing Short Frame Sync ............................................................................................... 51

Figure 9.18 PCM Slave Timing Long Frame Sync .................................................................................................. 52

Figure 9.19 PCM Slave Timing Short Frame Sync ................................................................................................. 53

Figure 9.20 Digital Audio Interface Modes .............................................................................................................. 54

Figure 9.21 Digital Audio Interface Slave Timing .................................................................................................... 55

Figure 9.22 Digital Audio Interface Master Timing .................................................................................................. 56

Figure 10.1 1.80V and 1.35V Dual-supply Switch-mode System Configuration ..................................................... 58

Figure 10.2 1.80V Parallel-supply Switch-mode System Configuration .................................................................. 59

Figure 10.3 1.8V Switch-mode Regulator Output Configuration ............................................................................. 60

Figure 10.4 1.35V Switch-mode Regulator Output Configuration ........................................................................... 61

Figure 10.5 1.8V and 1.35V Switch-mode Regulators Outputs Parallel Configuration ........................................... 62

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Figure 11.1 Battery Charger Mode-to-Mode Transition Diagram ............................................................................ 65

Figure 11.2 Battery Charger External Mode Typical Configuration ........................................................................ 67

Figure 12.1 Single Microphone and Stereo Line Input ............................................................................................ 68

Figure 12.2 Dual/Stereo Line Input ......................................................................................................................... 69

Figure 16.1 Programmable Audio Prompts in External SPI Flash .......................................................................... 90

Figure 16.2 Programmable Audio Prompts in External I²C EEPROM .................................................................... 91

Figure 16.3 1-mic CVC Block Diagram ................................................................................................................... 92

Figure 16.4 Configurable EQ GUI with Drag Points ................................................................................................ 95

Figure 16.5 Volume Boost GUI with Drag Points .................................................................................................... 96

Figure 17.1 CSR8635 QFN Tape Orientation ......................................................................................................... 97

Figure 17.2 Reel Dimensions .................................................................................................................................. 99

List of Tables

Table 3.1

Typical On-chip Capacitance Values .................................................................................................... 24

Table 3.2

Transconductance and On-chip Parasitic Capacitance ........................................................................ 25

Table 3.3

Crystal Specification ............................................................................................................................. 25

Table 3.4

External Clock Specifications ............................................................................................................... 27

Table 7.1

PS Keys for UART/PIO Multiplexing ..................................................................................................... 31

Table 7.2

Possible UART Settings ....................................................................................................................... 32

Table 7.3

Standard Baud Rates ........................................................................................................................... 33

Table 8.1

Table 9.1

Alternative PIO Functions ..................................................................................................................... 35

Alternative Functions of the Digital Audio Bus Interface on the PCM1 Interface .................................. 37

Table 9.2

ADC Audio Input Gain Rate .................................................................................................................. 39

Table 9.3

DAC Digital Gain Rate Selection .......................................................................................................... 40

Table 9.4

DAC Analogue Gain Rate Selection ..................................................................................................... 41

Table 9.5

Table 9.6

Table 9.7

Table 9.8

Table 9.9

Side Tone Gain ..................................................................................................................................... 44

PCM Master Timing .............................................................................................................................. 49

PCM Slave Timing ................................................................................................................................ 52

Alternative Functions of the Digital Audio Bus Interface on the PCM Interface .................................... 54

Digital Audio Interface Slave Timing ..................................................................................................... 55

Table 9.10 I²S Slave Mode Timing ......................................................................................................................... 55

Table 9.11 Digital Audio Interface Master Timing ................................................................................................... 56

Table 9.12 I²S Master Mode Timing Parameters, WS and SCK as Outputs .......................................................... 56

Table 10.1 Recommended Configurations for Power Control and Regulation ....................................................... 57

Table 10.2 Pin States on Reset .............................................................................................................................. 64

Table 11.1 Battery Charger Operating Modes Determined by Battery Voltage and Current .................................. 65

Table 13.1 ESD Handling Ratings .......................................................................................................................... 82

List of Equations

Equation 3.1 Negative Resistance ............................................................................................................................ 25

Equation 3.2 Crystal Calibration Using PSKEY_ANA_FTRIM_OFFSET .................................................................. 26

Equation 7.1 Baud Rate ............................................................................................................................................ 32

Equation 8.1 LED Current ......................................................................................................................................... 36

Equation 8.2 LED PAD Voltage ................................................................................................................................ 36

Equation 9.1 IIR Filter Transfer Function, H(z) ......................................................................................................... 45

Equation 9.2 IIR Filter Plus DC Blocking Transfer Function, H

DC

(z) ........................................................................ 45

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1 Package Information

1.1

Pinout Diagram

Orientation from Top of Device

68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52

10

11

12

7

8

9

13

14

15

16

17

4

5

6

1

2

3

18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34

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Figure 1.1: Device Pinout

45

44

43

42

41

40

39

38

37

36

35

51

50

49

48

47

46

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1.2

Device Terminal Functions

Radio

BT_RF

Oscillator

XTAL_IN

XTAL_OUT

USB

USB_DP

USB_DN

Lead Pad Type

12 RF

Lead Pad Type

19

Analogue

18

Lead Pad Type

56

55

Bidirectional

Supply Domain

VDD_BT_RADIO

Supply Domain

VDD_AUX

Supply Domain

VDD_USB

Description

Bluetooth 50Ω transmitter output / receiver input

Description

For crystal or external clock input

Drive for crystal

Description

USB data plus with selectable internal

1.5kΩ pull-up resistor

USB data minus

SPI/PCM Interface

SPI_PCM#

Lead Pad Type

29

Input with weak pulldown

Supply Domain

VDD_PADS_1

Description

SPI/PCM select input:

■ 0 = PCM/PIO interface

■ 1 = SPI

Note:

SPI and PCM1 interfaces are mapped as alternative functions on the PIO port.

PIO Port

PIO[21]

PIO[18]

PIO[17]

PIO[16]

PIO[15]

PIO[14]

Lead Pad Type

64

Bidirectional with weak pull-down

65

Bidirectional with weak pull-down

Supply Domain

VDD_PADS_2

VDD_PADS_2

Description

Programmable input / output line 21.

Programmable input / output line 18.

Programmable input / output line 17.

32

Bidirectional with strong pull-down

VDD_PADS_1

Alternative function:

■ UART_CTS: UART clear to send, active low

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27

Bidirectional with strong pull-up

VDD_PADS_1

Programmable input / output line 16.

Alternative function:

■ UART_RTS: UART request to send, active low

21

23

Bidirectional with strong pull-up

VDD_PADS_1

Bidirectional with strong pull-up

VDD_PADS_1

Programmable input / output line 15.

Alternative function:

■ UART_TX: UART data output

Programmable input / output line 14.

Alternative function:

■ UART_RX: UART data input

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PIO Port

PIO[13]

PIO[12]

PIO[11]

PIO[10]

PIO[9]

PIO[8]

PIO[7]

PIO[6]

PIO[5]

Lead Pad Type

31

22

26

Supply Domain

Bidirectional with strong pull-down

VDD_PADS_1

Bidirectional with strong pull-up

VDD_PADS_1

Bidirectional with strong pull-down

VDD_PADS_1

Description

Programmable input / output line 13.

Alternative function:

■ QSPI_IO[1]: SPI flash data bit 1

Programmable input / output line 12.

Alternative function:

■ QSPI_FLASH_CS#: SPI flash chip select

■ I2C_WP: I²C bus memory write protect line

Programmable input / output line 11.

Alternative function:

■ QSPI_IO[0]: SPI flash data bit 0

■ I2C_SDA: I²C serial data line

25

58

61

Bidirectional with strong pull-down

VDD_PADS_1

Bidirectional with strong pull-down

VDD_PADS_2

Bidirectional with strong pull-up

VDD_PADS_2

Programmable input / output line 10.

Alternative function:

■ QSPI_FLASH_CLK: SPI flash clock

■ I2C_SCL: I²C serial clock line

Programmable input / output line 9.

Alternative function:

■ UART_CTS: UART clear to send, active low

Programmable input / output line 8.

Alternative function:

■ UART_RTS: UART request to send, active low

57

62

Bidirectional with strong pull-down

VDD_PADS_2

Bidirectional with strong pull-down

VDD_PADS_2

Programmable input / output line 7.

Programmable input / output line 6.

34

Bidirectional with weak pull-down

VDD_PADS_1

Programmable input / output line 5.

Alternative function:

■ SPI_CLK: SPI clock

■ PCM1_CLK: PCM1 synchronous data clock

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PIO Port

PIO[4]

PIO[3]

PIO[2]

PIO[1]

PIO[0]

AIO[0]

Lead Pad Type

24

Bidirectional with weak pull-down

VDD_PADS_1

28

Bidirectional with weak pull-down

VDD_PADS_1

30

Bidirectional with weak pull-down

VDD_PADS_1

60

Bidirectional with strong pull-up

VDD_PADS_2

59

Bidirectional with strong pull-up

VDD_PADS_2

20 Bidirectional

Supply Domain

VDD_AUX

Description

Programmable input / output line 4.

Alternative function:

■ SPI_CS#: chip select for SPI, active low

■ PCM1_SYNC: PCM1 synchronous data sync

Programmable input / output line 3.

Alternative function:

■ SPI_MISO: SPI data output

■ PCM1_OUT: PCM1 synchronous data output

Programmable input / output line 2.

Alternative function:

■ SPI_MOSI: SPI data input

■ PCM1_IN: PCM1 synchronous data input

Programmable input / output line 1.

Alternative function:

■ UART_TX: UART data output

Programmable input / output line 0.

Alternative function:

■ UART_RX: UART data input

Analogue programmable input / output line 0.

Test and Debug

RST#

Codec

MIC_BIAS

AU_REF

SPKR_RN

SPKR_RP

Lead Pad Type

35

Supply Domain

Input with strong pull-up VDD_PADS_1

Description

Reset if low. Pull low for minimum 5ms to cause a reset.

Lead Pad Type Supply Domain Description

2 Microphone bias

1

Analogue in VDD_AUDIO

Decoupling of audio reference (for highquality audio)

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6 Speaker output negative, right

Analogue out VDD_AUDIO_DRV

7 Speaker output positive, right

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Codec

SPKR_LN

SPKR_LP

LINE/MIC_AN

LINE/MIC_AP

LINE_BN

LINE_BP

68

4

5

Lead Pad Type

9

Analogue out

10

67

Analogue in

Analogue in

Supply Domain

VDD_AUDIO_DRV

VDD_AUDIO

VDD_AUDIO

Description

Speaker output negative, left

Speaker output positive, left

Line or microphone input negative, channel A

Line or microphone input positive, channel A

Line input negative, channel B

Line input positive, channel B

LED Drivers

LED[2]

LED[1]

Lead Pad Type

66

36

Bidirectional

Bidirectional

Supply Domain

VDD_PADS_2

VDD_PADS_1

Description

LED driver.

Alternative function: programmable output PIO[31]

Note:

As output is open-drain, an external pull-up is required when PIO[31] is configured as a programmable output.

LED driver.

Alternative function: programmable output PIO[30].

Note:

As output is open-drain, an external pull-up is required when PIO[30] is configured as a programmable output.

LED[0] 37 Bidirectional VDD_PADS_1

LED driver.

Alternative function: programmable output PIO[29].

Note:

As output is open-drain, an external pull-up is required when PIO[29] is configured as a programmable output.

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Power Supplies and Control Lead Description

CHG_EXT

LX_1V35

LX_1V8

SMPS_1V35_SENSE

SMPS_1V8_SENSE

43

50

47

52

53

External battery charger control.

External battery charger transistor base control when using external charger boost. Otherwise leave unconnected.

1.35V switch-mode power regulator inductor connection.

1.8V switch-mode power regulator inductor connection.

1.35V switch-mode power regulator sense input.

1.8V switch-mode power regulator sense input.

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Power Supplies and Control

SMP_BYP

SMP_VBAT

VSS_SMPS_1V35

VSS_SMPS_1V8

VBAT

VBAT_SENSE

VCHG

Lead

49

48

45

44

51

46

42

Description

Supply via bypass regulator for 1.8V and 1.35V switchmode power supply regulator inputs. Must be connected to the same potential as

VOUT_3V3.

1.8V and 1.35V switch-mode power supply regulator inputs.

Must be at the same potential as VBAT.

1.35V switch-mode regulator ground.

1.8V switch-mode regulator ground.

Battery positive terminal.

Battery charger sense input, connect as Section 12 shows.

Charger input.

Typically connected to VBUS (USB supply) as Section 12 shows.

VDD_ANA

VDD_AUDIO

VDD_AUDIO_DRV

VDD_AUX

VDD_AUX_1V8

VDD_BT_LO

VDD_BT_RADIO

17

3

8

14

15, 16

13

11

Analogue LDO linear regulator output (1.35V).

Connect to 1.35V supply, see Section 12 for connections.

Positive supply for audio.

Connect to 1.35V supply, see Section 12 for connections.

Positive supply for audio output amplifiers.

Connect to 1.8V supply, see Section 12 for connections.

Auxiliary supply.

Connect to 1.35V supply, see Section 12 for connections.

Auxiliary LDO regulator input.

Connect to 1.8V supply, see Section 12 for connections.

Bluetooth radio local oscillator supply (1.35V).

Connect to 1.35V supply, see Section 12 for connections.

Bluetooth radio supply.

Connect to 1.35V supply, see Section 12 for connections.

Digital LDO regulator output, see Section 12 for connections.

VDD_DIG 38

VDD_PADS_1 33 Positive supply input for input/output ports.

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Power Supplies and Control

VDD_PADS_2

VDD_USB

VOUT_3V3

VREGENABLE

VREGIN_DIG

VSS

Lead

63

54

41

40

39

Exposed pad

Description

Positive supply input for input/output ports.

Positive supply for USB port.

3.3V bypass linear regulator output.

Connect external minimum 2.2µF ceramic decoupling capacitor.

Regulator enable input.

Can also be sensed as an input.

Regulator enable and multifunction button. A high input (tolerant to

VBAT) enables the on-chip regulators, which can then be latched on internally and the button used as a multifunction input.

Digital LDO regulator input, see Section 12 for connections.

Typically connected to a 1.35V supply.

Ground connections.

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1.3

Package Dimensions

Top View

D

A aaa C A aaa C B bbb C

A

A2 ccc C

A3

A1

0.10

E

Laser Mark for Pin 1

Identification in This Area

Bottom View

D2

18

17

B eee C A B

1.30

34

35

L

1

68

Pin 1 ID

E2

0.30

b

0.30

e ddd

M

C A B

52

51

1.30

L eee C A B

Seating

Plane

Side View

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A3 b

D

D2 e

Notes

Description

A

A1

A2

Description

Pitch

Min

0.80

0.00

-

Typ

0.85

0.035

0.65

Max

0.90

0.05

0.67

Description

E

E2

L

Min

7.90

4.50

0.35

-

0.15

7.90

4.50

-

0.203

0.20

8.00

4.60

0.40

-

0.25

8.10

4.70

aaa bbb ccc ddd eee

-

-

-

-

0.10

0.10

0.08

0.10

0.10

1.

Dimensions and tolerances conform to ASME Y14.5M. - 1994

2.

Pin 1 identifier is placed on top surfaceof the package by using identation mark or other feature of package body.

3.

Exact shape and size of this feature is optional.

4.

Package warpage 0.08mm maximum.

QFN

-

-

-

-

-

8 x 8 x 0.9mm

0.4mm pitch

JEDEC

Units

MO-220 mm

Typ

8.00

4.60

0.40

Max

8.10

4.70

0.45

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1.4

PCB Design and Assembly Considerations

This section lists recommendations to achieve maximum board-level reliability of the 8 x 8 x 0.9mm QFN 68-lead package:

NSMD lands (lands smaller than the solder mask aperture) are preferred, because of the greater accuracy of the metal definition process compared to the solder mask process. With solder mask defined pads, the overlap of the solder mask on the land creates a step in the solder at the land interface, which can cause stress concentration and act as a point for crack initiation.

CSR recommends that the PCB land pattern is in accordance with IPC standard IPC-7351.

Solder paste must be used during the assembly process.

1.5

Typical Solder Reflow Profile

For information, see

Typical Solder Reflow Profile for Lead-free Devices Information Note

.

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2 Bluetooth Modem

2.1

RF Ports

2.1.1

BT_RF

CSR8635 QFN contains an on-chip balun which combines the balanced outputs of the PA on transmit and produces the balanced input signals for the LNA required on receive. No matching components are needed as the receive mode impedance is 50Ω and the transmitter has been optimised to deliver power into a 50Ω load.

VDD

_

PA

+

On-chip Balun

BT_RF

VSS_BT_RF

LNA

+

_

Figure 2.1: Simplified Circuit BT_RF

2.2

RF Receiver

The receiver features a near-zero IF architecture that enables the channel filters to be integrated onto the die. Sufficient out-of-band blocking specification at the LNA input enables the receiver to operate in close proximity to GSM and

W‑CDMA cellular phone transmitters without being desensitised. A digital FSK discriminator means that no discriminator tank is needed and its excellent performance in the presence of noise enables CSR8635 QFN to exceed the Bluetooth requirements for co‑channel and adjacent channel rejection.

For EDR, the demodulator contains an ADC which digitises the IF received signal. This information is then passed to the EDR modem.

2.2.1

Low Noise Amplifier

The LNA operates in differential mode and takes its input from the balanced port of the on-chip balun.

2.2.2

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The ADC implements fast AGC. The ADC samples the RSSI voltage on a slot-by-slot basis. The front-end LNA gain is changed according to the measured RSSI value, keeping the first mixer input signal within a limited range. This improves the dynamic range of the receiver, improving performance in interference-limited environments.

2.3

RF Transmitter

2.3.1

IQ Modulator

The transmitter features a direct IQ modulator to minimise frequency drift during a transmit timeslot, which results in a controlled modulation index. Digital baseband transmit circuitry provides the required spectral shaping.

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2.3.2

Power Amplifier

The internal PA output power is software controlled and configured through a PS Key. The internal PA on the CSR8635

QFN has a maximum output power that enables it to operate as a Class 1, Class 2 and Class 3 Bluetooth radio without requiring an external RF PA.

2.4

Bluetooth Radio Synthesiser

The Bluetooth radio synthesiser is fully integrated onto the die with no requirement for an external VCO screening can, varactor tuning diodes, LC resonators or loop filter. The synthesiser is guaranteed to lock in sufficient time across the guaranteed temperature range to meet the Bluetooth v4.0 specification.

2.5

Baseband

2.5.1

Burst Mode Controller

During transmission the BMC constructs a packet from header information previously loaded into memory-mapped registers by the software and payload data/voice taken from the appropriate ring buffer in the RAM. During reception, the BMC stores the packet header in memory-mapped registers and the payload data in the appropriate ring buffer in

RAM. This architecture minimises the intervention required by the processor during transmission and reception.

2.5.2

Physical Layer Hardware Engine

Dedicated logic performs:

Forward error correction

Header error control

Cyclic redundancy check

Encryption

Data whitening

Access code correlation

Audio transcoding

Firmware performs the following voice data translations and operations:

A-law/µ-law/linear voice data (from host)

A-law/µ-law/CVSD (over the air)

Voice interpolation for lost packets

Rate mismatch correction

The hardware supports all optional and mandatory features of the Bluetooth v4.0 specification including AFH and eSCO.

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3 Clock Generation

CSR8635 QFN accepts a reference clock input from either a crystal or an external clock source, e.g. a TCXO.

The external reference clock is required in active and deep sleep modes and must be present when CSR8635 QFN is enabled.

3.1

Crystal

CSR8635 QFN contains a crystal driver circuit that acts as a transconductance amplifier that drives an external crystal connected between XTAL_IN and XTAL_OUT. The crystal driver circuit forms a Pierce oscillator with the external crystal. External capacitors are not required for standard crystals that require a load capacitance of around 9pF.

CSR recommends this option.

g m

On-chip Capacitance Control

Amplifier g m

Control LVL[3:0]

XTAL_IN XTAL_OUT

External Crystal

Figure 3.1: Crystal Oscillator Overview

The on-chip capacitance is adjusted using PSKEY_XTAL_OSC_CONFIG, see Table 3.1. The default values suit a typical crystal requiring a 9pF load capacitance. In deep sleep mode, the crystal oscillation is maintained, but at a lower drive strength to reduce power consumption. The drive strength and load capacitance are configured with a PS Key.

Value

XTAL_IN

(Typical)

XTAL_OUT

(Typical)

15.6 pF

Normal Mode

PSKEY_XTAL_OSC_CONFIG [3:2]

01

10.8 pF

10

6.0 pF

11

1.1 pF

20.8 pF 16.0 pF 11.2 pF 6.4 pF

00

15.6 pF

Low Power Mode

PSKEY_XTAL_OSC_CONFIG [1:0]

01

10.8 pF

10

6.0 pF

11

1.1 pF

16.0 pF 11.2 pF 6.4 pF 1.5 pF

Table 3.1: Typical On-chip Capacitance Values

The drive strength is configured with PSKEY_XTAL_LVL. The default level for this PS Key is sufficient for typical crystals. The level control is set in the range 0 to 15, where 15 is the maximum drive level.

Increasing the crystal amplifier drive level increases the transconductance of the crystal amplifier, which creates an increase in the oscillator margin (ratio of oscillator amplifiers is equivalent to the negative resistance of the crystal

ESR).

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Note:

Excessive amplifier transconductance can lead to an increase in the oscillator phase noise if the oscillator amplifier is excessively overdriven. Set the transconductance to the minimum level to give the desired oscillation ratio. Higher values can increase power consumption. Also, insufficient drive strength can prevent the the crystal from starting to oscillate.

3.1.1

Negative Resistance Model

The crystal and its load capacitor can be modelled as a frequency dependant resistive element. Consider the driver amplifier as a circuit that provides negative resistance. For oscillation, the value of the negative resistance should be greater than that of the crystal circuit equivalence resistance. Equation 3.1 shows how to calculate the equivalent negative resistance.

R neg

=−

2πf

2

(C g m

C in

C out out

C in

+(C

0

+C int

)(C out

+C in

))

2

Equation 3.1: Negative Resistance

Where:

■ g m

= Transconductance of the crystal oscillator amplifier

C o

= Static capacitance of the crystal, which is sometimes referred to as the shunt or case capacitance

C int

= On-chip parasitic capacitance between input and output of XTAL amplifier.

C in

= Internal capacitance on XTAL_IN, see Table 3.1

C out

= Internal capacitance on XTAL_OUT, see Table 3.1

Parameter

Transconductance

C int

Min

2

-

Typ

-

1.5

Max

-

-

Unit mS pF

Table 3.2: Transconductance and On-chip Parasitic Capacitance

3.1.2

Crystal Specification

Table 3.3 shows the specification for an external crystal.

Parameter

Frequency

Min

16

Typ

26

Max

32

Unit

MHz

Initial Frequency error from nominal frequency which can be compensated for

±285

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Frequency Stability ±20

Crystal ESR 60 ppm ppm

Table 3.3: Crystal Specification

3.1.3

Crystal Calibration

The actual crystal frequency depends on the capacitance of XTAL_IN and XTAL_OUT on the PCB and the CSR8635

QFN, as well as the capacitance of the crystal.

The Bluetooth specification requires ±20ppm clock accuracy. The actual frequency at which a crystal oscillates contains two error terms, which are typically mentioned in the crystal device datasheets:

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Initial Frequency Error: The difference between the desired frequency and the actual oscillating frequency caused by the crystal itself and its PCB connections. It is also called as Calibration Tolerance or Frequency

Tolerance.

Frequency Stability: The total of how far the crystal can move off frequency with temperature, aging or other effects. It is also called as Temperature Stability, Frequency Stability or Aging.

CSR8635 QFN has the capability to compensate for Initial Frequency errors by a simple per-device basis on the production line, with the trim value stored in the non-volatile memory (PS Key). However, it is not possible to compensate for frequency stability, therefore a crystal must be chosen with a Frequency Stability that is better than ±20 ppm clock accuracy.

Some crystal datasheets combine both these terms into one tolerance value. This causes a problem because only the initial frequency error can be compensated for and CSR8635 QFN cannot compensate for the temperature or aging performance. If frequency stability is not explicity stated, CSR cannot guarantee remaining within the Bluetooth's

±20ppm frequency accuracy specification.

Crystal calibration uses a single measurement of RF output frequency and can be performed quickly as part of the product final test. Typically, a TXSTART radio command is sent and then a measurement of the output RF frequency is read . From this, the calibration factor to correct actual offset from the desired frequency can be calculated. This offset value is stored in PSKEY_ANA_FTRIM_OFFSET. CSR8635 QFN then compensates for the initial frequency offset of the crystal.

The value in PSKEY_ANA_FTRIM_OFFSET is a 16-bit 2's complement signed integer which specifies the fractional part of the ratio between the true crystal frequency, f actual

, and the value set in PSKEY_ANA_FREQ, f nominal

. Equation

3.2 shows the value of PSKEY_ANA_FTRIM_OFFSET in parts per 2

20

rounded to the nearest integer.

For more information on TXSTART radio test see

BlueTest User Guide

.

PSKEY_ANA_FTRIM_OFFSET = ( f actual f nominal

− 1) × 2

20

Equation 3.2: Crystal Calibration Using PSKEY_ANA_FTRIM_OFFSET

3.2

Non-crystal Oscillator

Apply the external reference clock to the CSR8635 QFN XTAL_IN input. Connect XTAL_OUT to ground.

The external clock is either a low-level sinusoid, or a digital-level square wave. The clock must meet the specification in Table 3.4. The external reference clock is required in active and deep sleep modes, it must be present when CSR8635

QFN is enabled.

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Frequency

(a)

Duty cycle

Edge jitter (at zero crossing)

Min

19.2

40:60

-

Typ

26

50:50

-

Max

40

60:40

10

Unit

MHz

ps rms

(b)

Signal level

AC coupled sinusoid amplitude

DC coupled digital extremes

DC coupled digital digital amplitude

XTAL_IN input impedance

XTAL_IN input capacitance

0.2

0

0.4

0.4

-

-

VDD_AUX

(c)

VDD_AUX

(c)

1.2

V

V

V pk-pk

30

-

-

1

kΩ pF

Table 3.4: External Clock Specifications

(a)

The frequency should be an integer multiple of 250kHz except for the CDMA/3G frequencies

(b) 100Hz to 1MHz

(c)

VDD_AUX is 1.35V nominal

3.2.1

XTAL_IN Impedance in Non-crystal Mode

The impedance of XTAL_IN does not change significantly between operating modes. When transitioning from deep sleep to active states, the capacitive load can change. For this reason, CSR recommends using a buffered clock input.

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4 Bluetooth Stack Microcontroller

The CSR8635 QFN uses a 16-bit RISC 80MHz MCU for low power consumption and efficient use of memory. It contains a single-cycle multiplier and a memory protection unit for the VM accelerator, see Section 4.1.

The MCU, interrupt controller and event timer run the Bluetooth software stack and control the Bluetooth radio and host interfaces.

4.1

VM Accelerator

CSR8635 QFN contains a VM accelerator alongside the MCU. This hardware accelerator improves the performance of VM applications.

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5 Kalimba DSP

The Kalimba DSP is an open platform DSP enabling signal processing functions to be performed on over‑air data or codec data to enhance audio applications. Figure 5.1 shows the Kalimba DSP interfaces to other functional blocks within CSR8635 QFN.

Kalimba DSP Core

Memory

Management

Unit

MCU Register Interface (including Debug)

DSP MMU Port

DSP, MCU and Memory Window Control

Programmable Clock = 80MHz

Data Memory

Inteface

Address

Generators

Instruction Decode

Program Flow DEBUG

Clock Select PIO

Internal Control Register

MMU Interface

Interrupt Controller

Timer

MCU Window

Flash Window

ALU

PIO In/Out

IRQ to Subsystem

IRQ from Subsystem

1

µs Timer Clock

DSP RAMs

DM2

DM1

PM

DSP Data Memory 2 Interface (DM2)

DSP Data Memory 1 Interface (DM1)

DSP Program Memory Interface (PM)

Figure 5.1: Kalimba DSP Interface to Internal Functions

The key features of the DSP include:

80MIPS performance, 24‑bit fixed point DSP core

Single‑cycle MAC; 24 x 24‑bit multiply and 56‑bit accumulate includes 2 rMAC registers and new instructions for improved performance over previous architecture

32‑bit instruction word

Separate program memory and dual data memory, enabling an ALU operation and up to 2 memory accesses in a single cycle

Zero overhead looping, including a very low‑power 32‑instruction cache

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Single cycle barrel shifter with up to 56‑bit input and 56‑bit output

Multiple cycle divide (performed in the background)

Bit reversed addressing

Orthogonal instruction set

Low overhead interrupt

For more information see

Kalimba Architecture 3 DSP User Guide

.

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6 Memory Interface and Management

6.1

Memory Management Unit

The MMU provides dynamically allocated ring buffers that hold the data that is in transit between the host, the air or the Kalimba DSP. The dynamic allocation of memory ensures efficient use of the available RAM and is performed by a hardware MMU to minimise the overheads on the processor during data/voice transfers. The use of DMA ports also helps with efficient transfer of data to other peripherals.

6.2

System RAM

56KB of integrated RAM supports the RISC MCU and is shared between the ring buffers for holding voice/data for each active connection and the general-purpose memory required by the Bluetooth stack.

6.3

Kalimba DSP RAM

Additional integrated RAM provides support for the Kalimba DSP:

16K x 24-bit for data memory 1 (DM1)

16K x 24-bit for data memory 2 (DM2)

6K x 32-bit for program memory (PM)

6.4

Internal ROM

Internal ROM is provided for system firmware implementation.

6.5

Serial Flash Interface

CSR8635 QFN supports external serial flash ICs. This enables additional data storage areas for device-specific data.

CSR8635 QFN supports serial single I/O devices with a 1-bit I/O flash-memory interface.

Figure 6.1 shows a typical connection between CSR8635 QFN and a serial flash IC.

1.8V

MCU

MCU Program

MCU Data

Kalimba DSP Program

Memory

Management

Unit

QSPI_FLASH_CLK

QSPI_FLASH_CS#

QSPI_IO[0]

QSPI_IO[1]

Serial Quad I/O Flash

VDD

RESET#/HOLD#/IO3

WP#/IO2

CLK

CS#

DI/IO0

DO/IO1

Kalimba DSP

Figure 6.1: Serial Flash Interface

CSR8635 QFN supports Winbond, Microchip/SST, Macronix (and compatible) selected serial flash devices for PS

Key and voice prompt storage up to 16Mb, see firmware release note for up-to-date device support.

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7 Serial Interfaces

7.1

USB Interface

CSR8635 QFN has a full-speed (12Mbps) USB interface for communicating with other compatible digital devices. The

USB interface on CSR8635 QFN acts as a USB peripheral, responding to requests from a master host controller.

CSR8635 QFN contains internal USB termination resistors and requires no external resistor matching.

CSR8635 QFN supports the

Universal Serial Bus Specification, Revision v2.0 (USB v2.0 Specification)

USB standard charger detection and fully supports the www.usb.org

. For more information on how to integrate the USB interface on CSR8635 QFN see the

USB Design Considerations Application Note

.

USB Battery Charging Specification

, supports

, available from http://

Bluetooth and

As well as describing USB basics and architecture, the application note describes:

Power distribution for high and low bus-powered configurations

Power distribution for self-powered configuration, which includes USB VBUS monitoring

USB enumeration

Electrical design guidelines for the power supply and data lines, as well as PCB tracks and the effects of ferrite beads

USB suspend modes and Bluetooth low-power modes:

Global suspend

Selective suspend, includes remote wake

Wake on Bluetooth, includes permitted devices and set-up prior to selective suspend

Suspend mode current draw

PIO status in suspend mode

Resume, detach and wake PIOs

Battery charging from USB, which describes dead battery provision, charge currents, charging in suspend modes and USB VBUS voltage consideration

USB termination when interface is not in use

Internal modules, certification and non-specification compliant operation

7.2

UART Interface

CSR8635 QFN has one optional standard UART serial interface that provides a simple mechanism for communicating with other serial devices using the RS232 protocol, including for test and debug. The UART interface is multiplexed with PIOs and other functions, and hardware flow control is optional. PS Keys configure this multiplexing, see Table

7.1.

PS Key

PSKEY_UART_RX_PIO

PIO Location Option

PIO[0] (default) or PIO[14]

PSKEY_UART_TX_PIO PIO[1] (default) or PIO[15]

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PSKEY_UART_RTS_PIO PIO[8] (default) or PIO[16]

PSKEY_UART_CTS_PIO PIO[9] (default) or PIO[17]

Table 7.1: PS Keys for UART/PIO Multiplexing

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Figure 7.1 shows the 4 signals that implement the UART function.

PIO[1] or PIO[15]

PIO[0] or PIO[14]

PIO[8] or PIO[16]

PIO[9] or PIO[17]

UART_TX

UART_RX

UART_RTS

UART_CTS

Figure 7.1: Universal Asynchronous Receiver

When CSR8635 QFN is connected to another digital device, UART_RX and UART_TX transfer data between the 2 devices. The remaining 2 signals, UART_CTS and UART_RTS, implement optional RS232 hardware flow control where both are active low indicators.

UART configuration parameters, such as baud rate and packet format, are set using CSR8635 QFN firmware.

Note:

To communicate with the UART at its maximum data rate using a standard PC, the PC requires an accelerated serial port adapter card.

Table 7.2 shows the possible UART settings.

Parameter

Baud rate

Flow control

Parity

Number of stop bits

Bits per byte

Minimum

Maximum

Possible Values

1200 baud (≤2%Error)

9600 baud (≤1%Error)

4Mbaud (≤1%Error)

RTS/CTS or None

None, Odd or Even

1 or 2

8

Table 7.3 lists common baud rates and their associated values for the PSKEY_UART_BAUDRATE. There is no requirement to use these standard values. Any baud rate within the supported range is set in the PS Key according to the formula in Equation 7.1.

Equation 7.1: Baud Rate

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Baud Rate

38400

57600

76800

115200

230400

460800

921600

1382400

1843200

2764800

3686400

1200

2400

4800

9600

19200

Hex

0x0005

Persistent Store Value

0x000a

0x0014

0x0027

0x004f

0x009d

0x00ec

0x013b

0x01d8

0x03b0

0x075f

0x0ebf

0x161e

0x1d7e

0x2c3d

0x3afb

944

1887

3775

5662

157

236

315

472

7550

11325

15099

Dec

5

10

20

39

79

Error

-0.18%

0.03%

0.14%

0.03%

0.03%

-0.02%

0.00%

-0.01%

0.00%

0.00%

0.00%

1.73%

1.73%

1.73%

-0.82%

0.45%

Table 7.3: Standard Baud Rates

7.3

Programming and Debug Interface

CSR8635 QFN provides a debug SPI interface for programming, configuring (PS Keys) and debugging the CSR8635

QFN. Access to this interface is required in production. Ensure the 4 SPI signals and the SPI_PCM# line are brought out to either test points or a header. To use the SPI interface, the SPI_PCM# line requires the option of being pulled high externally.

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CSR provides development and production tools to communicate over the SPI from a PC, although a level translator circuit is often required. All are available from CSR.

7.3.1

Multi-slave Operation

Avoid connecting CSR8635 QFN in a multi-slave arrangement by simple parallel connection of slave MISO lines. When

CSR8635 QFN is deselected (SPI_CS# = 1), the SPI_MISO line does not float. Instead, CSR8635 QFN outputs 0 if the processor is running or 1 if it is stopped.

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7.4

I²C EEPROM Interface

CSR8635 QFN supports optional I²C EEPROM for storage of PS Keys and voice prompt data if SPI flash is not used.

Figure 7.2 shows an example I²C EEPROM connection where:

PIO[10] is the I²C EEPROM SCL line

PIO[11] is the I²C EEPROM SDA line

PIO[12] is the I²C EEPROM WP line

1.8V

C1

PIO[12]/QSPI_FLASH_CS#/I2C_WP

PIO[10]/QSPI_FLASH_CLK/I2C_SCL

PIO[11]/QSPI_IO[0]/I2C_SDA

R1

2.2kΩ

R2

2.2kΩ

R3

2.2kΩ

8

7

6

5

U1

VCC

WP

SCL

SDA

24AAxxx

10nF

A0

A1

A2

VSS

1

2

3

4

Figure 7.2: Example I²C EEPROM Connection

Note:

The I²C EEPROM requires external pull-up resistors, see Figure 7.2. Ensure that external pull-up resistors are suitably sized for the I²C interface speed and PCB track capacitance.

To minimise boot time, CSR recommends using 400kHz capable I²C EEPROMs and I2C_CONFIG and

ANA_FREQ should be the first 2 keys in the EEPROM PS-store image.

EEPROMs must be suitable for operation at 1.8V.

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8 Interfaces

8.1

Programmable I/O Ports, PIO

CSR8635 QFN provides 22 lines of programmable bidirectional I/O, PIO[21:0]. Some of the PIOs on the CSR8635

QFN have alternative functions, see Table 8.1.

PIO

PIO[0]

PIO[1]

PIO[2]

PIO[3]

PIO[4]

PIO[5]

PIO[8]

PIO[9]

PIO[10] -

PIO[11] -

PIO[12] -

PIO[13] -

PIO[14] -

PIO[15] -

-

-

SPI_CS#

SPI_CLK

PIO[16] -

PIO[17] -

-

-

Debug SPI

(See Section 7.3)

SPI_MOSI

SPI_MISO

-

-

-

-

-

-

SPI Flash

(See Section 6.5)

-

-

-

-

-

-

QSPI_FLASH_CLK

QSPI_IO[0]

QSPI_FLASH_CS#

QSPI_IO[1]

Function

-

-

UART

(See Section 7.2)

UART_RX (default) -

UART_TX (default) -

PCM

(See Section 9.3)

PCM1_IN

PCM1_OUT

-

-

-

-

-

-

UART_RTS (default) -

UART_CTS (default) -

PCM1_SYNC

PCM1_CLK

UART_RX

UART_TX

-

-

-

-

-

-

UART_RTS

UART_CTS -

-

-

-

-

-

-

-

EEPROM

(See Section 7.4)

-

-

-

-

-

-

I2C_SCL

I2C_SDA

-

I2C_WP

Note:

See the relevant software release note for the implementation of these PIO lines, as they are firmware buildspecific.

8.2

Analogue I/O Ports, AIO

CSR8635 QFN has 1 general-purpose analogue interface pin, AIO[0]. Typically, this connects to a thermistor for battery pack temperature measurements during charge control. See Section 12 for typical connections.

8.3

LED Drivers

CSR8635 QFN includes a 3-pad synchronised PWM LED driver for driving RGB LEDs for producing a wide range of colours. All LEDs are controlled by firmware.

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The terminals are open-drain outputs, so the LED must be connected from a positive supply rail to the pad in series with a current-limiting resistor.

LED Supply

LED Forward Voltage, V

F

R

LED

Resistor Voltage Drop, V

R

LED[2, 1 or 0]

Pad Voltage, V

PAD

; R

ON

= 20Ω

Figure 8.1: LED Equivalent Circuit

From Figure 8.1 it is possible to derive Equation 8.1 to calculate I

LED the LED to give a specific luminous intensity, then the value of R

LED

. If a known value of current is required through

is calculated.

I

LED

=

VDD − VF

RLED + RON

Equation 8.1: LED Current

For the LED pads to act as resistance, the external series resistor, R

LED it, V

R

, keeps V

PAD

below 0.5V. Equation 8.2 also applies.

, needs to be such that the voltage drop across

VDD = V

F

+ V

R

+ V

PAD

Equation 8.2: LED PAD Voltage

Note:

The supply domain in Section 1.2 for LED[2:0] must remain powered for LED functions to operate.

The LED current adds to the overall current. Conservative LED selection extends battery life.

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9 Audio Interface

The audio interface circuit consists of:

Stereo/dual-mono audio codec

Dual analogue audio inputs

Dual analogue audio outputs

Configurable PCM (PCM1) and I²S interfaces, for configuration information contact CSR

Figure 9.1 shows the functional blocks of the interface. The codec supports stereo/dual-mono playback and recording of audio signals at multiple sample rates with a 16-bit resolution. The ADC and the DAC of the codec each contain 2 independent high-quality channels. Any ADC or DAC channel runs at its own independent sample rate.

Stereo / Dual-mono Codec

PCM1

PCM1 Interface

MMU Voice Port Voice Port

Digital

Audio

Memory

Management

Unit

Register Interface

Registers

Stereo

Audio

Codec

Driver

2 x Differential

DAC Outputs

2 x Differential

ADC Inputs

Figure 9.1: Audio Interface

The interface for the digital audio bus shares the same pins as the PCM1 codec interface described in Section 9.3.

Table 9.1 lists the alternative functions.

Important Note:

The term

PCM

in Section 9.3 and its subsections refers to the PCM1 interface.

PCM Interface

PCM_OUT

PCM_IN

PCM_SYNC

I²S Interface

SD_OUT

SD_IN

WS

SCK

Table 9.1: Alternative Functions of the Digital Audio Bus Interface on the PCM1 Interface

9.1

Audio Input and Output

The audio input circuitry consists of 2 independent 16-bit high-quality ADC channels:

Programmable as either stereo or dual-mono inputs

1 input programmable as either microphone or line input, the other as line input only

Each channel is independently configurable to be either single-ended or fully differential

Each channel has an analogue and digital programmable gain stage, this also aids optimisation of different microphones

The audio output circuitry consists of a dual differential class A-B output stage.

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Note:

CSR8635 QFN is designed for a differential audio output. If a single-ended audio output is required, use an external differential to single-ended converter.

9.2

Audio Codec Interface

The main features of the interface are:

Stereo and mono analogue input for voice band and audio band

Stereo and mono analogue output for voice band and audio band

Support for I²S stereo digital audio bus standard

Support for PCM interface including PCM master codecs that require an external system clock

Important Note:

To avoid any confusion regarding stereo operation this data sheet explicitly states which is the left and right channel for audio output. With respect to audio input, software and any registers, channel 0 or channel A represents the left channel and channel 1 or channel B represents the right channel.

9.2.1

Audio Codec Block Diagram

Digital Circuitry

Stereo Audio and Voice Band Input

LINE_BP

LINE_BN

High-quality ADC Digital Codec 16 Input B

LINE/MIC_AP

LINE/MIC_AN

Stereo Audio and Voice Band Output

SPKR_LN

SPKR_LP

Low-pass Filter

SPKR_RN

SPKR_RP

Low-pass Filter

High-quality ADC Digital Codec

High-quality DAC

High-quality DAC

16

16

16

Input A

Figure 9.2: Audio Codec Input and Output Stages

The CSR8635 QFN audio codec uses a fully differential architecture in the analogue signal path, which results in low noise sensitivity and good power supply rejection while effectively doubling the signal amplitude. It operates from a dual power supply, VDD_AUDIO for the audio circuits and VDD_AUDIO_DRV for the audio driver circuits.

9.2.2

ADC

Figure 9.2 shows the CSR8635 QFN consists of 2 high-quality ADCs:

Each ADC has a second-order Sigma-Delta converter.

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There are 2 gain stages for each channel, 1 of which is an analogue gain stage and the other is a digital gain stage, see Section 9.2.4.

9.2.3

ADC Sample Rate Selection

Each ADC supports the following pre-defined sample rates, although other rates are programmable, e.g. 40kHz:

8kHz

11.025kHz

16kHz

22.050kHz

24kHz

32kHz

44.1kHz

48kHz

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9.2.4

ADC Audio Input Gain

ADC Pre-amplifier and ADC Analogue Gain:

-3dB to 42dB in 3dB steps

ADC Pre-amplifier:

0dB, 9dB, 21dB and 30dB

ADC Analogue Gain:

-3dB to 12dB in 3dB steps

Audio Input

ADC Digital Gain:

-24dB to 21.5dB in alternating

2.5dB and 3dB steps

To Digital Codec

Digital Gain Selection

Value

0

1

4

5

2

3

6

7

System Gain = ADC Pre-amplifier + ADC Analogue Gain + ADC Digital Gain

Figure 9.3: Audio Input Gain

9.2.5

ADC Pre-amplifier and ADC Analogue Gain

CSR8635 QFN has an analogue gain stage based on an ADC pre-amplifier and ADC analogue amplifier:

The ADC pre-amplifier has 4 gain settings: 0dB, 9dB, 21dB and 30dB

The ADC analogue amplifier gain is -3dB to 12dB in 3dB steps

The overall analogue gain for the pre-amplifier and analogue amplifier is -3dB to 42dB in 3dB steps, see Figure

9.3

At mid to high gain levels it acts as a microphone pre-amplifier, see Section 9.2.13

At low gain levels it acts as an audio line level amplifier

9.2.6

ADC Digital Gain

A digital gain stage inside the ADC varies from -24dB to 21.5dB, see Table 9.2. There is also a a 9-bit gain setting allowing gain changes in 1/32 steps, for more information contact CSR.

fine gain interface

with

The firmware controls the audio input gain.

ADC Digital Gain Setting

(dB)

0

3.5

6

Digital Gain Selection

Value

8

9

12

15.5

18

21.5

Table 9.2: ADC Audio Input Gain Rate

12

13

10

11

14

15

ADC Digital Gain Setting

(dB)

-24

-20.5

-18

-14.5

-12

-8.5

-6

-2.5

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9.2.7

ADC Digital IIR Filter

The ADC contains 2 integrated anti-aliasing filters:

long

IIR filter suitable for music (>44.1kHz)

A

G.722 filter is a digital IIR filter that improves the stop-band attenuation required for G.722 compliance (which is the best selection for 8kHz / 16kHz / voice)

For more information contact CSR.

9.2.8

DAC

The DAC consists of:

2 fourth-order Sigma-Delta converters enabling 2 separate channels that are identical in functionality, as Figure

9.2 shows.

2 gain stages for each channel, 1 of which is an analogue gain stage and the other is a digital gain stage.

9.2.9

DAC Sample Rate Selection

Each DAC supports the following sample rates:

8kHz

11.025kHz

16kHz

22.050kHz

32kHz

40kHz

44.1kHz

48kHz

96kHz

9.2.10 DAC Digital Gain

A digital gain stage inside the DAC varies from -24dB to 21.5dB, see Table 9.3. There is also a a 9-bit gain setting enabling gain changes in 1/32 steps, for more information contact CSR.

fine gain interface

with

The overall gain control of the DAC is controlled by the firmware. Its setting is a combined function of the digital and analogue amplifier settings.

Digital Gain Selection

Value

0

1

4

5

2

3

6

7

DAC Digital Gain Setting

(dB)

0

3.5

6

12

15.5

18

21.5

Digital Gain Selection

Value

8

9

12

13

10

11

14

15

DAC Digital Gain Setting

(dB)

-24

-20.5

-18

-14.5

-12

-8.5

-6

-2.5

9.2.11 DAC Analogue Gain

Table 9.3: DAC Digital Gain Rate Selection

Table 9.4 shows the DAC analogue gain stage consists of 8 gain selection values that represent seven 3dB steps.

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The firmware controls the overall gain control of the DAC. Its setting is a combined function of the digital and analogue amplifier settings.

Analogue Gain Selection

Value

7

6

5

4

DAC Analogue Gain

Setting (dB)

0

-3

-6

-9

Analogue Gain Selection

Value

3

2

1

0

DAC Analogue Gain

Setting (dB)

-12

-15

-18

-21

Table 9.4: DAC Analogue Gain Rate Selection

9.2.12 DAC Digital FIR Filter

The DAC contains an integrated digital FIR filter with the following modes:

A default

A

A

short long

FIR filter for best performance at ≥ 44.1kHz.

FIR to reduce latency.

narrow

FIR (a very sharp roll-off at Nyquist) for G.722 compliance. Best for 8kHz / 16kHz.

9.2.13 Microphone Input

CSR8635 QFN contains an independent low-noise microphone bias generator. The microphone bias generator is recommended for biasing electret condensor microphones. Figure 9.4 shows a biasing circuit for microphones with a sensitivity between about ‑40 to ‑60dB (0dB = 1V/Pa).

Where:

The microphone bias generator derives its power from VBAT or 3V3_USB and requires no capacitor on its output.

The microphone bias generator maintains regulation within the limits 70μA to 2.8mA, supporting a 2mA source typically required by 2 electret condensor microphones. If the microphone sits below these limits, then the microphone output must be pre-loaded with a large value resistor to ground.

Biasing resistors R1 is 2.2kΩ.

The input impedance at LINE/MIC_AN and LINE/MIC_AP is typically 6kΩ.

C1 and C2 are 100/150nF if bass roll-off is required to limit wind noise on the microphone.

R1 sets the microphone load impedance and are normally around 2.2kΩ.

Microphone Bias

(MIC_BIAS)

C1

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R1

LINE/MIC_AP

C2

LINE/MIC_AN

Input

Amplifier

+

MIC1

Figure 9.4: Microphone Biasing

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The microphone bias characteristics include:

Power supply:

CSR8635 QFN microphone supply is VBAT or 3V3_USB

Minimum input voltage = Output voltage + drop-out voltage

Maximum input voltage is 4.3V

Drop-out voltage:

■ 300mV maximum

Output voltage:

1.8V or 2.6V

Tolerance 90% to 110%

Output current:

70μA to 2.8mA

No load capacitor required

9.2.14 Line Input

Figure 9.5 and Figure 9.6 show 2 circuits for line input operation and show connections for either differential or singleended inputs.

In line input mode, the input impedance of the pins to ground varies from 6kΩ to 34kΩ depending on input gain setting.

C1

LINE/MIC_AN

C2

C3

LINE/MIC_AP

LINE_BN

C4

LINE_BP

Figure 9.5: Differential Input

C1

LINE/MIC_AP

C2

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C3

LINE/MIC_AN

LINE_AP

C4

LINE_AN

Figure 9.6: Single-ended Input

9.2.15 Output Stage

The output stage digital circuitry converts the signal from 16-bit per sample, linear PCM of variable sampling frequency to bit stream, which is fed into the analogue output circuitry.

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The analogue output circuit comprises a DAC, a buffer with gain-setting, a low-pass filter and a class AB output stage amplifier. Figure 9.7 shows that the output is available as a differential signal between SPKR_LN and SPKR_LP for the left channel, and between SPKR_RN and SPKR_RP for the right channel.

SPKR_LP

SPKR_LN

SPKR_RP

SPKR_RN

Figure 9.7: Speaker Output

9.2.16 Mono Operation

Mono operation is a single-channel operation of the stereo codec. The left channel represents the single mono channel for audio in and audio out. In mono operation, the right channel is the auxiliary mono channel for dual-mono channel operation.

In single channel mono operation, disable the other channel to reduce power consumption.

9.2.17 Side Tone

In some applications it is necessary to implement side tone. This side tone function involves feeding a properly gained microphone signal in to the DAC stream, e.g. earpiece. The side tone routing selects the version of the microphone signal from before or after the digital gain in the ADC interface and adds it to the output signal before or after the digital gain of the DAC interface, see Figure 9.8.

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Digital Input

Side Tone Route

DAC Interface

DAC

Digital Gain

Demux

Side Tone

Analogue Output

Side Tone Gain

Side Tone Route Mux

Digital Output Digital Gain Analogue Input

ADC Interface

ADC

Figure 9.8: Side Tone

The ADC provides simple gain to the side tone data. The gain values range from -32.6dB to 12.0dB in alternating steps of 2.5dB and 3.5dB, see Table 9.5.

5

6

3

4

7

Value

0

1

2

Side Tone Gain

-32.6dB

-30.1dB

-26.6dB

-24.1dB

-20.6dB

13

14

11

12

15

Value

8

9

10

Side Tone Gain

-8.5dB

-6.0dB

-2.5dB

0dB

3.5dB

6.0dB

9.5dB

12.0dB

-14.5dB

-12.0dB

Table 9.5: Side Tone Gain

Note:

The values of side tone are shown for information only. During standard operation, the application software controls the side tone gain.

The following PS Keys configure the side tone hardware:

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PSKEY_SIDE_TONE_ENABLE

PSKEY_SIDE_TONE_GAIN

PSKEY_SIDE_TONE_AFTER_ADC

PSKEY_SIDE_TONE_AFTER_DAC

9.2.18 Integrated Digital IIR Filter

CSR8635 QFN has a programmable digital filter integrated into the ADC channel of the codec. The filter is a 2-stage, second order IIR and is for functions such as custom wind noise reduction. The filter also has optional DC blocking.

The filter has 10 configuration words:

1 for gain value

8 for coefficient values

1 for enabling and disabling the DC blocking

The gain and coefficients are all 12-bit 2's complement signed integer with the format NN.NNNNNNNNNN.

Note:

The position of the binary point is between bit[10] and bit[9], where bit[11] is the most significant bit.

For example:

01.1111111111

01.0000000000

=

= most positive number, close to 2

1

0

00.0000000000

11.0000000000

10.0000000000

=

=

=

-1

-2

, most negative number

Equation 9.1 shows the equation for the IIR filter. Equation 9.2 shows the equation for when the DC blocking is enabled.

The filter is configured, enabled and disabled from the VM via the CodecSetIIRFilterA and

CodecSetIIRFilterB

traps. This requires firmware support. The configuration function takes 10 variables in the following order:

3

4

1

2

0 :

5

6

7

9

:

:

:

:

:

:

:

:

:

Gain b

01 b

02 a

01 a

02 b

11 b

12 a

11 a

12

DC Block (1 = enable, 0 = disable)

Filter, H(z) = Gain ×

( 1 + b01 z

−1 + b

02 z

−2 )

( 1 + a01 z

−1 + a

02 z

−2 )

×

( 1 + b11 z

−1 + b

( 1 + a11 z

−1 + a

12 z

−2 )

12 z

−2 )

Equation 9.1: IIR Filter Transfer Function, H(z)

Filter with DC Blocking, H

DC

(z) = H(z) × ( 1 − z

−1

)

Equation 9.2: IIR Filter Plus DC Blocking Transfer Function, H

DC

(z)

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9.3

PCM1 Interface

Important Note:

The PCM1 interface is provided as a test interface and is only accessible when running the CSR8635 QFN in HCIonly mode.

Section 9 describes the various digital audio interfaces multiplexed on the the PCM1 interface. The PCM1 interface also shares the same physical set of pins with the SPI interface, see Section 7.3 and Section 8.1. Either interface is selected using SPI_PCM#:

SPI_PCM# = 1 selects SPI

SPI_PCM# = 0 selects PCM

Important Note:

The term

PCM

refers to PCM1.

The audio PCM interface on the CSR8635 QFN supports:

Continuous transmission and reception of PCM encoded audio data over Bluetooth.

Processor overhead reduction through hardware support for continual transmission and reception of PCM data.

A bidirectional digital audio interface that routes directly into the baseband layer of the firmware. It does not pass through the HCI protocol layer.

Hardware on the CSR8635 QFN for sending data to and from a SCO connection.

Up to 3 SCO connections on the PCM interface at any one time.

PCM interface master, generating PCM_SYNC and PCM_CLK.

PCM interface slave, accepting externally generated PCM_SYNC and PCM_CLK.

Various clock formats including:

Long Frame Sync

Short Frame Sync

■ GCI timing environments

13-bit or 16-bit linear, 8-bit µ-law or A-law companded sample formats.

Receives and transmits on any selection of 3 of the first 4 slots following PCM_SYNC.

The PCM configuration options are enabled by setting the PSKEY_PCM_CONFIG32.

9.3.1

PCM Interface Master/Slave

When configured as the master of the PCM interface, CSR8635 QFN generates PCM_CLK and PCM_SYNC.

PCM_OUT

PCM_IN

PCM_CLK

PCM_SYNC

8/48kHz

Figure 9.9: PCM Interface Master

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PCM_OUT

PCM_IN

PCM_CLK

PCM_SYNC

Up to 2400kHz

8/48kHz

Figure 9.10: PCM Interface Slave

9.3.2

Long Frame Sync

Long Frame Sync is the name given to a clocking format that controls the transfer of PCM data words or samples. In

Long Frame Sync, the rising edge of PCM_SYNC indicates the start of the PCM word. When CSR8635 QFN is configured as PCM master, generating PCM_SYNC and PCM_CLK, then PCM_SYNC is 8 bits long. When CSR8635

QFN is configured as PCM Slave, PCM_SYNC is from 1 cycle PCM_CLK to half the PCM_SYNC rate.

PCM_SYNC

PCM_CLK

PCM_OUT 1 2 3 4 5 6 7 8

PCM_IN

Undefined

1 2 3 4 5 6 7 8

Undefined

Figure 9.11: Long Frame Sync (Shown with 8-bit Companded Sample)

CSR8635 QFN samples PCM_IN on the falling edge of PCM_CLK and transmits PCM_OUT on the rising edge.

PCM_OUT is configurable as high impedance on the falling edge of PCM_CLK in the LSB position or on the rising edge.

9.3.3

Short Frame Sync

In Short Frame Sync, the falling edge of PCM_SYNC indicates the start of the PCM word. PCM_SYNC is always 1 clock cycle long.

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PCM_SYNC

PCM_CLK

PCM_OUT 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16

PCM_IN Undefined 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 Undefined

Figure 9.12: Short Frame Sync (Shown with 16-bit Sample)

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As with Long Frame Sync, CSR8635 QFN samples PCM_IN on the falling edge of PCM_CLK and transmits PCM_OUT on the rising edge. PCM_OUT is configurable as high impedance on the falling edge of PCM_CLK in the LSB position or on the rising edge.

9.3.4

Multi-slot Operation

More than 1 SCO connection over the PCM interface is supported using multiple slots. Up to 3 SCO connections are carried over any of the first 4 slots.

LONG_PCM_SYNC

Or

SHORT_PCM_SYNC

PCM_CLK

PCM_OUT 1 2 3 4 5 6 7 8 1 2 3 4 5 6 7 8

PCM_IN Do Not Care 1 2 3 4 5 6 7 8 1 2 3 4 5 6 7 8 Do Not Care

Figure 9.13: Multi-slot Operation with 2 Slots and 8-bit Companded Samples

9.3.5

GCI Interface

CSR8635 QFN is compatible with the GCI, a standard synchronous 2B+D ISDN timing interface. The 2 64kbps B channels are accessed when this mode is configured.

PCM_SYNC

PCM_CLK

PCM_OUT 1 2 3 4 5 6 7 8 1 2 3 4 5 6 7 8

PCM_IN

Do Not

Care

1 2 3 4 5

B1 Channel

6 7 8 1 2 3 4 5

B2 Channel

6 7 8

Do Not

Care

The start of frame is indicated by the rising edge of PCM_SYNC and runs at 8kHz.

9.3.6

Slots and Sample Formats

CSR8635 QFN receives and transmits on any selection of the first 4 slots following each sync pulse. Slot durations are either 8 or 16 clock cycles:

8 clock cycles for 8-bit sample formats.

16 clock cycles for 8-bit, 13-bit or 16-bit sample formats.

CSR8635 QFN supports:

13-bit linear, 16-bit linear and 8-bit µ-law or A-law sample formats.

A sample rate of 8ksps.

Little or big endian bit order.

For 16-bit slots, the 3 or 8 unused bits in each slot are filled with sign extension, padded with zeros or a programmable 3-bit audio attenuation compatible with some codecs.

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PCM_OUT 1 2 3

Sign

Extension

4 5 6 7 8 9 10 11 12 13 14 15 16

8-bit

Sample

A 16-bit slot with 8-bit companded sample and sign extension selected.

PCM_OUT 1 2

8-bit

Sample

3 4 5 6 7 8 9 10 11 12 13 14 15 16

Zeros

Padding

A 16-bit slot with 8-bit companded sample and zeros padding selected.

PCM_OUT 1

Sign

Extension

2 3 4 5 6 7 8 9 10 11 12 13 14 15 16

13-bit

Sample

A 16-bit slot with 13-bit linear sample and sign extension selected.

PCM_OUT

1 2

13-bit

Sample

3 4 5 6 7 8 9 10 11 12 13 14 15 16

Audio

Gain

A 16-bit slot with 13-bit linear sample and audio gain selected.

Figure 9.15: 16-bit Slot Length and Sample Formats

9.3.7

Additional Features

CSR8635 QFN has a mute facility that forces PCM_OUT to be 0. In master mode, CSR8635 QFN is compatible with some codecs which control power down by forcing PCM_SYNC to 0 while keeping PCM_CLK running.

9.3.8

PCM Timing Information

Symbol Unit f mclk

t mclkh

(a)

Parameter Min Typ Max is programmable. See

Section 9.3.10.

-

128

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256

512

-

PCM_CLK frequency

48MHz DDS generation. Selection of frequency is programmable. See

Section 9.3.10.

2.9

-

PCM_SYNC frequency for SCO connection 8 -

PCM_CLK high 4MHz DDS generation 980 kHz kHz kHz ns

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Symbol t mclkl

(a) t hpinclkl

Parameter

PCM_CLK low 4MHz DDS generation t t

t dmclksynch dmclkpout dmclklsyncl

PCM_CLK jitter 48MHz DDS generation

Delay time from PCM_CLK high to PCM_SYNC high

Delay time from PCM_CLK high to valid

PCM_OUT

Delay time from PCM_CLK low to PCM_SYNC low

(Long Frame Sync only) t t dmclkhsyncl dmclklpoutz

Delay time from PCM_CLK high to PCM_SYNC low

Delay time from PCM_CLK low to PCM_OUT high impedance t dmclkhpoutz

Delay time from PCM_CLK high to PCM_OUT high impedance t supinclkl

Set-up time for PCM_IN valid to PCM_CLK low

Hold time for PCM_CLK low to PCM_IN invalid

Min

730

-

-

-

-

-

-

-

20

0

Typ

-

-

-

-

-

-

-

-

-

-

Max

-

21

20

20

20

20

20

20

-

-

Table 9.6: PCM Master Timing

(a)

Assumes normal system clock operation. Figures vary during low-power modes, when system clock speeds are reduced.

t dmclksynch t dmclklsyncl t dmclkhsyncl

PCM_SYNC

Unit ns ns pk-pk ns ns ns ns ns ns ns ns f mlk t mclkh t mclkl

PCM_CLK

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PCM_OUT t dmclkpout

MSB (LSB) t r

,t f

LSB (MSB) t dmclklpoutz t dmclkhpoutz

PCM_IN t supinclkl t hpinclkl

MSB (LSB) LSB (MSB)

Figure 9.16: PCM Master Timing Long Frame Sync

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PCM_SYNC t dmclksynch t dmclkhsyncl t mclkh f mlk t mclkl

PCM_CLK

PCM_OUT

PCM_IN t dmclkpout

MSB (LSB) t r

,t f

LSB (MSB) t dmclklpoutz t dmclkhpoutz t supinclkl t hpinclkl

MSB (LSB) LSB (MSB)

Figure 9.17: PCM Master Timing Short Frame Sync

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Symbol f sclk f sclk t sclkl t sclkh t hsclksynch t susclksynch t t t dpout dsclkhpout dpoutz t supinsclkl t hpinsclkl

Parameter

PCM clock frequency (Slave mode: input)

PCM clock frequency (GCI mode)

PCM_CLK low time

PCM_CLK high time

Hold time from PCM_CLK low to PCM_SYNC high

Set-up time for PCM_SYNC high to PCM_CLK low

Delay time from PCM_SYNC or PCM_CLK, whichever is later, to valid PCM_OUT data (Long

Frame Sync only)

Delay time from CLK high to PCM_OUT valid data

Delay time from PCM_SYNC or PCM_CLK low, whichever is later, to PCM_OUT data line high impedance

Set-up time for PCM_IN valid to CLK low

Hold time for PCM_CLK low to PCM_IN invalid

Table 9.7: PCM Slave Timing

(a)

Max frequency is the frequency defined by PSKEY_PCM_MIN_CPU_CLOCK

(b) Max frequency is twice the frequency defined by PSKEY_PCM_MIN_CPU_CLOCK

200

200

2

Min

64

128

20

20

2

-

-

t sclkh f sclk t tsclkl

PCM_CLK t hsclksynch t susclksynch

-

-

-

-

-

Typ

-

-

-

-

-

ns ns ns ns ns

Unit kHz kHz ns ns ns ns

20

15

Max

(a)

(b)

-

-

-

-

15

-

-

PCM_OUT

PCM_IN t dpout

MSB (LSB) t dsclkhpout t r

,t f

LSB (MSB) t dpoutz t dpoutz t supinsclkl t hpinsclkl

MSB (LSB) LSB (MSB)

Figure 9.18: PCM Slave Timing Long Frame Sync

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t sclkh f sclk t tsclkl

PCM_CLK

PCM_SYNC t susclksynch t hsclksynch

PCM_OUT t dsclkhpout

MSB (LSB) t r

,t f

LSB (MSB) t dpoutz t dpoutz

PCM_IN t supinsclkl t hpinsclkl

MSB (LSB) LSB (MSB)

Figure 9.19: PCM Slave Timing Short Frame Sync

9.3.9

PCM_CLK and PCM_SYNC Generation

CSR8635 QFN has 2 methods of generating PCM_CLK and PCM_SYNC in master mode:

Generating these signals by DDS from CSR8635 QFN internal 4MHz clock. Using this mode limits PCM_CLK to 128, 256 or 512kHz and PCM_SYNC to 8kHz.

Generating these signals by DDS from an internal 48MHz clock, which enables a greater range of frequencies to be generated with low jitter but consumes more power. To select this second method set bit

48M_PCM_CLK_GEN_EN in PSKEY_PCM_CONFIG32. When in this mode and with long frame sync, the length of PCM_SYNC is either 8 or 16 cycles of PCM_CLK, determined by LONG_LENGTH_SYNC_EN in

PSKEY_PCM_CONFIG32.

PSKEY_PCM_USE_LOW_JITTER_MODE sets the low jitter mode when the sync rate is 8kHz and the PCM clock is set either by PSKEY_PCM_CLOCK_RATE or through the audio API, see

BlueCore Audio API Specification

.

9.3.10 PCM Configuration

Configure the PCM by using the PS Key PSKEY_PCM_CONFIG32 or through the audio API, see

BlueCore Audio API

Specification

. The default for PSKEY_PCM_CONFIG32 is 0x00800000, i.e. first slot following sync is active, 13-bit linear voice format, long frame sync and interface master generating 256kHz PCM_CLK from 4MHz internal clock with no tristate of PCM_OUT.

9.4

Digital Audio Interface (I²S)

Important Note:

The I²S interface is provided as a test interface and is only accessible when running the CSR8635 QFN in HCIonly mode.

The digital audio interface supports the industry standard formats for I²S, left-justified or right-justified. The interface shares the same pins as the PCM interface, which means each audio bus is mutually exclusive in its usage. Table

9.8 lists these alternative functions. Figure 9.20 shows the timing diagram.

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PCM Interface

PCM_OUT

PCM_IN

PCM_SYNC

PCM_CLK

I²S Interface

SD_OUT

SD_IN

WS

SCK

Table 9.8: Alternative Functions of the Digital Audio Bus Interface on the PCM Interface

Configure the digital audio interface using PSKEY_DIGITAL_AUDIO_CONFIG, see and the PS Key file.

WS

Left Channel Right Channel

SCK

SD_IN/OUT

MSB

WS

LSB MSB

Left -justified Mode

Left Channel

LSB

Right Channel

SCK

SD_IN/OUT

WS

MSB

Left Channel

LSB MSB

Right -justified Mode

Right Channel

LSB

SCK

MSB LSB MSB LSB

I

2

S Mode

Figure 9.20: Digital Audio Interface Modes

The internal representation of audio samples within CSR8635 QFN is 16-bit and data on SD_OUT is limited to 16-bit per channel.

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Symbol

-

t ch t cl

Parameter

SCK Frequency

WS Frequency

SCK high time

SCK low time

Min

-

-

80

80

Symbol t t t t t ssu sh opd isu ih

WS(Input)

Parameter

Table 9.9: Digital Audio Interface Slave Timing

Min Typ

WS valid to SCK high set-up time

SCK high to WS invalid hold time

SCK low to SD_OUT valid delay time

SD_IN valid to SCK high set-up time

SCK high to SD_IN invalid hold time

20

2.5

-

20

2.5

-

-

-

-

-

Table 9.10: I²S Slave Mode Timing

Typ

-

-

-

t ch t ssu t cl

SCK(Input) t sh

Max

6.2

96

-

-

-

-

Max

-

-

20 t opd

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Unit

MHz kHz ns ns ns ns

Unit ns ns ns

SD_IN t isu

Figure 9.21: Digital Audio Interface Slave Timing t ih

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Symbol

-

-

Symbol t spd t opd t isu t ih

WS(Output)

Parameter

SCK Frequency

WS Frequency

Min

-

-

Typ

-

-

Table 9.11: Digital Audio Interface Master Timing

Max

6.2

96

Parameter

SCK low to WS valid delay time

SCK low to SD_OUT valid delay time

SD_IN valid to SCK high set-up time

SCK high to SD_IN invalid hold time

Min

18.44

0

-

-

Typ

-

-

-

-

Max

39.27

18.44

-

-

Table 9.12: I²S Master Mode Timing Parameters, WS and SCK as Outputs t spd

SCK(Output) t opd

SD_OUT t isu t ih

SD_IN

Unit

MHz kHz ns ns

Unit ns ns

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10 Power Control and Regulation

For greater power efficiency the CSR8635 QFN contains 2 switch-mode regulators:

1 generates a 1.80V supply rail with an output current of 185mA, see Section 10.1.

1 generates a 1.35V supply rail with an output current of 160mA, see Section 10.2.

Combining the 2 switch-mode regulators in parallel generates a single 1.80V supply rail with an output current of 340mA, see Section 10.3.

CSR8635 QFN contains 4 LDO linear regulators:

3.30V bypass regulator, see Section 10.4.

0.85V to 1.20V VDD_DIG linear regulator, see Section 10.5.

1.35V VDD_AUX linear regulator, see Section 10.6.

1.35V VDD_ANA linear regulator, see Section 10.7.

The recommended configurations for power control and regulation on the CSR8635 QFN are:

3 switch-mode configurations:

A 1.80V and 1.35V dual-supply rail system using the 1.80V and 1.35V switch-mode regulators, see Figure

10.1. This is the default power control and regulation configuration for the CSR8635 QFN.

A 1.80V single-supply rail system using the 1.80V switch-mode regulator.

A 1.80V parallel-supply rail system for higher currents using the 1.80V and 1.35V switch-mode regulators with combined outputs, see Figure 10.2.

A linear configuration using an external 1.8V rail omitting all regulators

Table 10.1 shows settings for the recommended configurations for power control and regulation on the CSR8635 QFN.

Supply

Configuration

1.8V

Switch-mode

1.35V

Regulators

VDD_AUX

Linear

Regulator

VDD_ANA

Linear

Regulator

1.8V

Supply Rail

1.35V

Dual-supply

SMPS

Single-supply

SMPS

Parallelsupply SMPS

Linear supply

ON

ON

ON

ON

OFF

ON

OFF

ON

ON

OFF

ON

ON

SMPS

SMPS

SMPS

SMPS

LDO

LDO

OFF OFF ON ON External LDO

Table 10.1: Recommended Configurations for Power Control and Regulation

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CSR8670

application note.

Configuring the Power Supplies on

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VCHG

VBAT_SENSE

VBAT

Charger

50 to 200mA

SMP_VBAT

VREGENABLE

Charge

Reference

EN OUT

Bypass Linear

Regulator

Reference

VOUT_3V3

IN

EN

1.35V

OUT

Switch-mode

Regulator

SENSE

IN

EN

1.8V

OUT

Switch-mode

Regulator

SENSE

Analogue and Auxiliary

EN

IN

VDD_AUX

Regulator

OUT

SENSE

Auxiliary Circuits

EN

IN

VDD_ANA

OUT

Regulator

SENSE

Bluetooth

I/O

Audio Circuits

SMP_BYP

LX_1V35

SMPS_1V35_SENSE

LX_1V8

SMPS_1V8_SENSE

VDD_AUX_1V8

VDD_AUX

VDD_ANA

VDD_BT_RADIO

VDD_BT_RADIO

VDD_BT_LO

VDD_PADS_1

VDD_PADS_2

1.8V

1.35V

3.3V

Audio Driver

VDD_AUDIO_DRV

Audio Core

VDD_AUDIO

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Digital Core Circuits

EN IN

VDD_DIG

Regulator

OUT

SENSE

VREGIN_DIG

VDD_DIG

Figure 10.1: 1.80V and 1.35V Dual-supply Switch-mode System Configuration

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VCHG

VBAT_SENSE

VBAT

Charger

50 to 200mA

SMP_VBAT

VREGENABLE

Charge

Reference

EN

OUT

Bypass Linear

Regulator

Reference

VOUT_3V3

IN

EN

1.35V

SENSE

Switch-mode

Regulator

OUT

IN

1.8V

OUT

Switch-mode

EN

Analogue and Auxiliary

EN

IN

VDD_AUX

Regulator

OUT

SENSE

Auxiliary Circuits

EN

IN

VDD_ANA

Regulator

OUT

SENSE

Bluetooth

I/O

Audio Circuits

SMP_BYP

SMPS_1V35_SENSE

LX_1V35

LX_1V8

SMPS_1V8_SENSE

VDD_AUX_1V8

VDD_AUX

VDD_ANA

VDD_BT_RADIO

VDD_BT_RADIO

VDD_BT_LO

VDD_PADS_1

VDD_PADS_2

1.8V

1.35V

3.3V

Audio Driver

VDD_AUDIO_DRV

Audio Core

VDD_AUDIO

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Digital Core Circuits

EN IN

VDD_DIG

Regulator

OUT

SENSE

VREGIN_DIG

VDD_DIG

Figure 10.2: 1.80V Parallel-supply Switch-mode System Configuration

10.1 1.8V Switch-mode Regulator

CSR recommends using the integrated switch-mode regulator to power the 1.80V supply rail.

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Figure 10.3 shows that an external LC filter circuit of a low-resistance series inductor, L1 (4.7µH), followed by a low

ESR shunt capacitor, C3 (2.2µF), is required between the LX_1V8 terminal and the 1.80V supply rail. Connect the

1.80V supply rail and the VDD_AUX_1V8 pin.

L1

4.7µH

C1

2.2µF

C2

2.2µF

VBAT

3V3_USB

LX

1.8V Switch-mode

Regulator

SENSE

LX_1V8

SMPS_1V8_SENSE

VSS_SMPS_1V8

To 1.35V Switch-mode

Regulator Input

1.8V Supply Rail

C3

2.2µF

Figure 10.3: 1.8V Switch-mode Regulator Output Configuration

Minimise the series resistance of the tracks between the regulator input, VBAT and 3V3_USB, ground terminals, the filter and decoupling components, and the external voltage source to maintain high-efficiency power conversion and low supply ripple.

Ensure a solid ground plane between C1, C2, C3 and VSS_SMPS_1V8.

Also minimise the collective parasitic capacitance on the track between LX_1V8 and the inductor L1, to maximise efficiency.

For the regulator to meet the specifications in Section 13.3.1.1 requires a total resistance of <1.0Ω (<0.5Ω recommended) for the following:

The track between the battery and VBAT.

The track between LX_1V8 and the inductor.

The inductor, L1, ESR.

The track between the inductor, L1, and the sense point on the 1.80V supply rail.

The following enable the 1.80V switch-mode regulator:

VREGENABLE pin

The CSR8635 QFN firmware with reference to PSKEY_PSU_ENABLES

VCHG pin

The switching frequency is adjustable by setting an offset from 4.00MHz using PSKEY_SMPS_FREQ_OFFSET, which also affects the 1.35V switch-mode regulator.

When the 1.80V switch-mode regulator is not required, leave unconnected:

The regulator input VBAT and 3V3_USB

The regulator output LX_1V8

10.2 1.35V Switch-mode Regulator

Figure 10.4 shows that an external LC filter circuit of a low-resistance series inductor L1 (4.7µH), followed by a low

ESR shunt capacitor, C3 (4.7µF), is required between the LX_1V35 terminal and the 1.35V supply rail. Connect the

1.35V supply rail and the SMPS_1V35_SENSE pin.

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C1

2.2µF

C2

2.2µF

VBAT

3V3_USB

LX

1.35V Switchmode Regulator

SENSE

LX_1V35

SMPS_1V35_SENSE

VSS_SMPS_1V35

To 1.8V Switch-mode

Regulator Input

L1

4.7µH

1.35V Supply Rail

C3

4.7µF

Figure 10.4: 1.35V Switch-mode Regulator Output Configuration

Minimise the series resistance of the tracks between the regulator input, VBAT and 3V3_USB, ground terminals, the filter and decoupling components, and the external voltage source to maintain high-efficiency power conversion and low supply ripple.

Ensure a solid ground plane between C1, C2, C3 and VSS_SMPS_1V35.

Also minimise the collective parasitic capacitance on the track between LX_1V35 and the inductor L1, to maximise efficiency.

For the regulator to meet the specifications in Section 13.3.2.1 requires a total resistance of <1.0Ω (<0.5Ω recommended) for the following:

The track between the battery and VBAT.

The track between LX_1V8 and the inductor.

The inductor, L1, ESR.

The track between the inductor, L1, and the sense point on the 1.35V supply rail.

The following enable the 1.35V switch-mode regulator:

VREGENABLE pin

The CSR8635 QFN firmware with reference to PSKEY_PSU_ENABLES

VCHG pin

The switching frequency is adjustable by setting an offset from 4.00MHz using PSKEY_SMPS_FREQ_OFFSET, which also affects the 1.80V switch-mode regulator.

When the 1.35V switch-mode regulator is not required, leave unconnected:

The regulator input VBAT and 3V3_USB

The regulator output LX_1V35

10.3 1.8V and 1.35V Switch-mode Regulators Combined

For applications that require a single 1.80V supply rail with higher currents CSR recommends combining the outputs of the integrated 1.80V and 1.35V switch-mode regulators in parallel to power a single 1.80V supply rail, see Figure

10.5.

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1.80V supply rail and the VDD_AUX_1V8 pin and ground the SMPS_1V35_SENSE pin.

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C1

2.2µF

C2

2.2µF

VBAT

3V3_USB

1.35V Switchmode Regulator

LX

SENSE

LX_1V35

SMPS_1V35_SENSE

VSS_SMPS_1V35

LX

1.8V Switch-mode

Regulator

SENSE

LX_1V8

SMPS_1V8_SENSE

VSS_SMPS_1V8

L1

4.7µH

1.8V Supply Rail

C3

2.2µF

Figure 10.5: 1.8V and 1.35V Switch-mode Regulators Outputs Parallel Configuration

Minimise the series resistance of the tracks between the regulator input VBAT and 3V3_USB, ground terminals, the filter and decoupling components, and the external voltage source to maintain high-efficiency power conversion and low supply ripple.

Ensure a solid ground plane between C1, C2, C3, VSS_SMPS_1V8 and VSS_SMPS_1V35.

Also minimise the collective parasitic capacitance on the track between LX_1V8, LX_1V35 and the inductor L1, to maximise efficiency.

For the regulator to meet the specifications in Section 13.3.1.2 requires a total resistance of <1.0Ω (<0.5Ω recommended) for the following:

The track between the battery and VBAT.

The track between LX_1V8, LX_1V35 and the inductor.

The inductor L1, ESR.

The track between the inductor, L1, and the sense point on the 1.80V supply rail.

The following enable the 1.80V switch-mode regulator:

VREGENABLE pin

The CSR8635 QFN firmware with reference to PSKEY_PSU_ENABLES

VCHG pin

The switching frequency is adjustable by setting an offset from 4.00MHz using PSKEY_SMPS_FREQ_OFFSET.

When the 1.80V switch-mode regulator is not required, leave unconnected:

The regulator input VBAT and 3V3_USB

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10.4 Bypass LDO Linear Regulator

The integrated bypass LDO linear regulator is available as a 3.30V supply rail and is an alternative supply rail to the battery supply. This is especially useful when the battery has no charge and the CSR8635 QFN needs to power up.

The input voltage should be between 4.25V to 6.50V.

Note:

The integrated bypass LDO linear regulator can operate down to 3.1V with a reduced performance.

Externally decouple the output of this regulator using a low ESR MLC capacitor of a minimum 2.2µF to the 3V3_USB pin.

The output voltage is switched on when VCHG gets above 3.0V.

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10.5 Low-voltage VDD_DIG Linear Regulator

The integrated low-voltage VDD_DIG linear regulator powers the digital circuits on CSR8635 QFN. Externally decouple the output of this regulator using a low ESR MLC capacitor of 470nF.

10.6 Low-voltage VDD_AUX Linear Regulator

The integrated low-voltage VDD_AUX linear regulator is optionally available to provide a 1.35V auxiliary supply rail when the 1.35V switch-mode regulator is not used. When using the integrated low-voltage VDD_AUX linear regulator, externally decouple the output of this regulator using a low ESR MLC capacitor of a minimum 470nF to the VDD_AUX pin.

10.7 Low-voltage VDD_ANA Linear Regulator

The integrated low-voltage VDD_ANA linear regulator is optionally available to power the 1.35V analogue supply rail when the 1.35V switch-mode regulator is not used. When using the integrated low-voltage VDD_ANA linear regulator, externally decouple the output of this regulator using a 2.2µF low ESR MLC capacitor to the VDD_ANA pin.

10.8 Voltage Regulator Enable

When using the integrated regulators the voltage regulator enable pin, VREGENABLE, enables the CSR8635 QFN and the following regulators:

1.8V switch-mode regulator

1.35V switch-mode regulator

Low-voltage VDD_DIG linear regulator

Low-voltage VDD_AUX linear regulator

The VREGENABLE pin is active high, with a pull-down, typical 100kΩ, which is disabled by

PSKEY_VREG_ENABLE_STRONG_PULL.

CSR8635 QFN boots-up when the voltage regulator enable pin is pulled high typically for 10 to 15ms, enabling the regulators. The firmware then latches the regulators on. The voltage regulator enable pin can then be released.

The status of the VREGENABLE pin is available to firmware through an internal connection. VREGENABLE also works as an input line.

Note:

VREGENABLE should be asserted after the VBAT supply when VREGENABLE is not used as a power-on button.

10.9 External Regulators and Power Sequencing

CSR recommends that the integrated regulators supply the CSR8635 QFN and it is configured based on the information in this data sheet.

If any of the supply rails for the CSR8635 QFN are supplied from an external regulator, then it should match or be better than the internal regulator available on CSR8635 QFN. For more information see regulator characteristics in Section

13.

Note:

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The internal regulators described in Section 10.1 to Section 10.7 are not recommended for external circuitry other than that shown in Section 12.

For information about power sequencing of external regulators to supply the CSR8635 QFN contact CSR.

10.10 Reset, RST#

CSR8635 QFN is reset from several sources:

RST# pin

Power-on reset

USB charger attach reset

Software configured watchdog timer

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The RST# pin is an active low reset and is internally filtered using the internal low frequency clock oscillator. CSR recommends applying RST# for a period >5ms.

At reset the digital I/O pins are set to inputs for bidirectional pins and outputs are set to tristate.

10.10.1 Digital Pin States on Reset

Table 10.2 shows the pin states of CSR8635 QFN on reset.

Pin Name

USB_DP

USB_DN

PIO[0]

PIO[1]

PIO[2]

PIO[3]

PIO[4]

PIO[5]

PIO[6]

PIO[7]

PIO[8]

I/O Type

Digital bidirectional

Digital bidirectional

Digital bidirectional

Digital bidirectional

Digital bidirectional

Digital bidirectional

Digital bidirectional

Digital bidirectional

Digital bidirectional

Digital bidirectional

Digital bidirectional

Full Chip Reset

PDW

PDW

PDW

PDW

PDS

N/A

N/A

PUS

PUS

PDS

PUS

Pin Name

PIO[9]

PIO[10]

PIO[11]

PIO[12]

PIO[13]

PIO[14]

PIO[15]

PIO[16]

PIO[17]

PIO[18]

PIO[21]

I/O Type

Digital bidirectional

Digital bidirectional

Digital bidirectional

Digital bidirectional

Digital bidirectional

Digital bidirectional

Digital bidirectional

Digital bidirectional

Digital bidirectional

Digital bidirectional

Digital bidirectional

Full Chip Reset

PDS

PUS

PUS

PUS

PDS

PDS

PDS

PDS

PUS

PDW

PDW

Table 10.2: Pin States on Reset

Note:

PUS = Strong pull-up

PDS = Strong pull-down

PUW = Weak pull-up

PDW = Weak pull-down

10.10.2 Status After Reset

The status of CSR8635 QFN after a reset is:

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Warm reset: baud rate and RAM data remain available

Cold reset: baud rate and RAM data not available

10.11 Automatic Reset Protection

CSR8635 QFN includes an automatic reset protection circuit which restarts/resets CSR8635 QFN when an unexpected reset occurs, e.g. ESD strike or lowering of RST#. The automatic reset protection circuit enables resets from the VM without the requirement for external circuitry.

Note:

The reset protection is cleared after typically 2s (1.6s min to 2.4s max).

If RST# is held low for >2.4s CSR8635 QFN turns off. A rising edge on VREGENABLE or VCHG is required to power on CSR8635 QFN.

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11 Battery Charger

11.1 Battery Charger Hardware Operating Modes

The battery charger hardware is controlled by the VM, see Section 11.3.The battery charger has 5 modes:

Disabled

Trickle charge

Fast charge

Standby: fully charged or float charge

Error: charging input voltage, VCHG, is too low

The battery charger operating mode is determined by the battery voltage and current, see Table 11.1 and Figure

11.1.

The internal charger circuit can provide up to 200mA of charge current, for currents higher than this the CSR8635 QFN can control an external pass transistor, see Section 11.5.

Mode

Disabled

Trickle charge

Fast charge

Standby

Error

Battery Charger Enabled

No

Yes

Yes

Yes

Yes

VBAT_SENSE

X

>0 and <V fast

>V fast

and <V float

I term

(a)

and >(V float

- V hyst

)

>(VCHG - 50mV)

Table 11.1: Battery Charger Operating Modes Determined by Battery Voltage and Current

(a) I term

is approximately 10% of I fast

for a given I fast

setting

Figure 11.1 shows the mode-to-mode transition voltages. These voltages are fixed and calibrated by CSR, see Section

11.2. The transition between modes can occur at any time.

Fast Charge Mode

Constant Current

I fast

I trickle

Constant Voltage

Standby Mode

Trickle Charge Mode

V hyst

V fast

Figure 11.1: Battery Charger Mode-to-Mode Transition Diagram

V float

I term

Battery Voltage

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Note:

The battery voltage remains constant in Fast Charge Constant Voltage Mode, the curved line on Figure 11.1 is for clarity only.

11.1.1 Disabled Mode

In the disabled mode the battery charger is fully disabled and draws no active current on any of its terminals.

11.1.2 Trickle Charge Mode

In the trickle charge mode, when the voltage on VBAT_SENSE is lower than the V fast approximately 10% of the fast charge current, I fast

, is sourced from the VBAT pin.

threshold, a current of

The V fast

threshold detection has hysteresis to prevent the charger from oscillating between modes.

11.1.3 Fast Charge Mode

When the voltage on VBAT_SENSE is greater than V fast

, the current sourced from the VBAT pin increases to I fast

I fast

is between 10mA and 200mA set by PS Key or a VM trap. In addition, I for process variation in the charger circuit.

fast

.

is calibrated in production test to correct

The current is held constant at I fast

until the voltage at VBAT_SENSE reaches V float

, then the charger reduces the current sourced to maintain a constant voltage on the VBAT_SENSE pin.

When the current sourced is below the termination current, I term mode. I term

is typically 10% of the fast charge current.

, the charging stops and the charger enters standby

11.1.4 Standby Mode

When the battery is fully charged, the charger enters standby mode, and battery charging stops. The battery voltage on the VBAT_SENSE pin is monitored, and when it drops below a threshold set at V

V float

, the charger re-enters fast charge mode.

hyst

below the final charging voltage,

11.1.5 Error Mode

The charger enters the error mode if the voltage on the VCHG pin is too low to operate the charger correctly

(VBAT_SENSE is greater than VCHG - 50mV (typical)).

In this mode, charging is stopped. The battery charger does not require a reset to resume normal operation.

11.2 Battery Charger Trimming and Calibration

The battery charger default trim values are written by CSR into non-volatile memory when each IC is characterised.

CSR provides various PS Keys for overriding the default trims, see Section 11.4.

11.3 VM Battery Charger Control

The VM charger code has overall supervisory control of the battery charger and is responsible for:

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Monitoring the temperature of the battery

Monitoring the temperature of the die to protect against silicon damage

Monitoring the time spent in the various charge states

Enabling/disabling the charger circuitry based on the monitored information

Driving the user visible charger status LED(s)

11.4 Battery Charger Firmware and PS Keys

The battery charger firmware sets up the charger hardware based on the PS Key settings and traps called from the

VM charger code. It also performs the initial analogue trimming. Settings for the charger current depend on the battery capacity and type, which are set by the user in the PS Keys.

For more information on the CSR8635 QFN, including details on setting up, calibrating, trimming and the PS Keys, see

Lithium Polymer Battery Charger Calibration and Operation for CSR8670

application note.

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11.5 External Mode

The external mode is for charging higher capacity batteries using an external pass device. The current is controlled by sinking a varying current into the CHG_EXT pin, and the current is determined by measuring the voltage drop across a resistor, R sense

, connected in series with the external pass device, see Figure 11.2. The voltage drop is determined by looking at the difference between the VBAT_SENSE and VBAT pins. The voltage drop across R sense

is typically

200mV. The value of the external series resistor determines the charger current. This current can be trimmed with a

PS Key.

In Figure 11.2, R1 (220mΩ) and C1 (4.7µF) form an RC snubber that is required to maintain stability across all battery

ESRs. The battery ESR must be <1.0Ω.

VCHG

CHG_EXT

VBAT_SENSE

TR 1

External Pass Device

R sense

VBAT

R1

220mΩ

C1

4.7

µF

BAT 1

Li+ Cell

Figure 11.2: Battery Charger External Mode Typical Configuration

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12 Example Application Schematic

Line Jack

CON1

UNMATED

MATED

UNMATED

MATED

6

7

8

9

10

11

L 5

R 2

SHIELD 1

STX-3100-9N

Mic1

L4

15nH

C17

15p

R2

2k2

Line Input / Microphone Auto Switch Circuit

C13

2u2

C14

2u2

LINE_L

C15

100n

MIC_N

C16

100n

MIC_P

JACK_DET_PIO

C19

2u2

1V8

LINE_BP

LINE_BN

C18

2u2

U1

LINE/MIC_AN

LINE/MIC_AP

LINE/MIC_PIO

Analogue 2xSPDT Switch eg MAX4717 / TS3A24157 or alternatives

MIC_BIAS

A N T

50R i

2

U2

OUT

Bluetooth RF

IN

4

3

GND GND 1

2.45GHz

B T _ R F

50R i

12

BT_RF

PCB Layout Notes

Ensure the following components are placed next to CSR8635 QFN and have good low impedance connections both to signal and GND

C2 and C3

Ensure the following tracks have good low impedance connections

(no via share and short thick tracks)

VSS_SMPS_1V8 to Battery Ground

VSS_SMPS_1V35 to Battery Ground

LX_1V8 to Inductor

LX_1V35 to Inductor

L1 to C4 track

L2 to C7 track

C4 to VSS_SMPS_1V8

C7 to VSS_SMPS_1V35

VBAT to Battery and C2 - should be <1ohm from battery

VCHG to charger connector and C1

VDD_DIG to Ground

Ensure good low impedance ground return path through GND plane for SMPSU current from C4 to VSS_SMPS_1V8 and C7 to VSS_SMPS_1V35 back to C3 & C4

Ensure routing from L2 to pin 39 and from L2 to C8/9 & pins 11 & 13 are kept separate

CSR recommend low Rdc inductors (<0.5R) for L1 & L2 for optimum power efficiency

For example Taiyo Yuden CB2012T4R7M

Suggest analogue and digital grounds are separated if possible and star connected near VSS_AUDIO as shown

Ensure analogue tracks stay over Analogue ground as much as possible

VBAT VBUS

S1

MFB

C1

2u2

VBAT

C2

2u2

3V3_USB

C3

2u2

1V8_SMPS

L1

4u7

C4

2u2

C5

10n

CHARGER

BYPASS REG

SP100

STAR

VBAT

1V8 SMPS

3V3

1V35 SMPS

AUX LDO

1V35

ANA LDO

1V35

1V35

C12

2u2

1V35_SMPS

C6

10n

L2

4u7

C7

4u7

CSR8635 QFN

MIC BIAS

C8

15p

C9

2u2

C10

470n

1V8_SMPS

Left Right

Speakers (16-32 Ohm)

C11

100n

XTAL_IN 19

XT1

26MHz

DIG LDO

XTAL_OUT 18

PIO[29] / LED[0] 37

PIO[30] / LED[1] 36

PIO[31] / LED[2] 66

PIO[0] / UART_RX 59

PIO[1] / UART_TX 60

PIO[6] 62

PIO[7] 57

PIO[8] / UART_RTS#

61

PIO[9] / UART_CTS# 58

PIO[18] 65

PIO[21] 64

LED_0

LED_1

LED_2

PIO_0

PIO_1

PIO_6

PIO_7

PIO_8

PIO_9

PIO_18

PIO_21

PIO[2] / PCM1_IN / SPI_MOSI 30

PIO[3] / PCM1_OUT / SPI_MISO 28

PIO[4] / PCM1_SYNC / SPI_CS# 24

PIO[5] / PCM1_CLK / SPI_CLK 34

SPI_PCM# 29

PIO[12] / QSPI_FLASH_CS# / I2C_WP 22

PIO[10] / QSPI_FLASH_CLK / I2C_SCL 25

PIO[11] / QSPI_IO[0] / I2C_SDA 26

PIO[13] / QSPI_IO[1]

31

PIO[14] / UART_RX 23

PIO[15] / UART_TX 21

PIO[16] / UART_RTS# 27

PIO[17] / UART_CTS# 32

AIO[0] 20

USB_P 56

USB_N 55

RST# 35

PIO_2

PIO_3

PIO_4

PIO_5

SPI_PCM#

PIO_12

PIO_10

PIO_11

PIO_13

JACK_DET_PIO

LINE/MIC_PIO

PIO_16

PIO_17

AIO_0

USB_P

USB_N

RSTB

Optional Ancilliary Circuits

USB / Charger Interface Optional Fast charge

400mohm = 500mA

VBUS VBUS

CHG_EXT 1

VBAT_SENSE

VBAT

Q100

BCX51

R104

1%

400mR

C105

4u7

R108

220mR

CON100

USB MINI-B

VBUS 1

D- 2

D+ 3

ID 4

GND 5

USB_N

USB_P

Connect VBAT_SENSE to VBAT if not using this circuit

LED outputs

PIO / UART

Battery temperature sensor

1V35_SMPS

R100

VBAT VBUS

Typical LED's and Buttons

Optional I2C EEPROM memory Optional 1x SPI FLASH memory

Lithium Polymer Battery

(battery protection built in)

AIO_0

9k1

1V8_SMPS

C100

1V8_SMPS D100

BAT54C

PIO_n

1V8 1V8 1V8 1V8 1V8

THERM

10k

C102

10n

R101

220R

R102

330R

R103

330R

S100

F4

S101

F3

S103

VOL+

PIO_12

PIO_10

PIO_11

R105

2k2

R106

2k2

8

7

6

5

U101

VCC

WP

SCL

SDA

10n

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Li+ CELL

VBAT

CON101

3.7V

D101 D102

D

Q1

S102

F2

S104

VOL-

R107

2k2

A0 1

A1 2

A2 3

VSS 4

24AAxxx

G 1V8_SMPS

S

C101

10n

PIO_11

PIO_13

8

5

2

3

7

U100

VDD

SI/SIO0

SO/SIO1

WP/SIO2

CE 1

SCK 6

HOLD/SIO3

VSS 4

PIO_12

PIO_10

SPI Flash

Size of EEPROM depends on voice prompt requirements

PIO / PCM1 / Debug SPI / I

2

S

SPI/PCM# high for SPI. Low for all other functions

PIO / Serial Flash / I 2 C

PIO / LINE-MIC Select / Jack Detect

Analogue Input / Output

USB (12Mbps)

Reset

Figure 12.1: Single Microphone and Stereo Line Input

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A N T

50R i

2

U2

OUT

Bluetooth RF

IN 4

3

GND GND 1

2.45GHz

B T _ R F

50R i

12

BT_RF

PCB Layout Notes

Ensure the following components are placed next to CSR8635 QFN and have good low impedance connections both to signal and GND

C2 and C3

Ensure the following tracks have good low impedance connections

(no via share and short thick tracks)

VSS_SMPS_1V8 to Battery Ground

VSS_SMPS_1V35 to Battery Ground

LX_1V8 to Inductor

LX_1V35 to Inductor

L1 to C4 track

L2 to C7 track

C4 to VSS_SMPS_1V8

C7 to VSS_SMPS_1V35

VBAT to Battery and C2 - should be <1ohm from battery

VCHG to charger connector and C1

VDD_DIG to Ground

Ensure good low impedance ground return path through GND plane for SMPSU current from C4 to VSS_SMPS_1V8 and C7 to VSS_SMPS_1V35 back to C3 & C4

Ensure routing from L2 to pin 39 and from L2 to C8/9 & pins 11 & 13 are kept separate

CSR recommend low Rdc inductors (<0.5R) for L1 & L2 for optimum power efficiency

For example Taiyo Yuden CB2012T4R7M

Suggest analogue and digital grounds are separated if possible and star connected near VSS_AUDIO as shown

Ensure analogue tracks stay over Analogue ground as much as possible

VBAT VBUS

S1

MFB

C1

2u2

VBAT

C2

2u2

3V3_USB

C3

2u2

1V8_SMPS

L1

4u7

C4

2u2

C5

10n

CHARGER

BYPASS REG

SP100

STAR

VBAT

1V8 SMPS

3V3

1V35 SMPS

1V35_SMPS

AUX LDO

1V35

ANA LDO

1V35

1V35

C6

10n

L2

4u7

C7

4u7

CSR8635 QFN

C8

15p

C9

2u2

C10

470n

C11

100n

XT1

26MHz

XTAL_IN 19

DIG LDO

XTAL_OUT 18

PIO[29] / LED[0] 37

PIO[30] / LED[1] 36

PIO[31] / LED[2] 66

PIO[0] / UART_RX 59

PIO[1] / UART_TX 60

PIO[6] 62

PIO[7] 57

PIO[8] / UART_RTS# 61

PIO[9] / UART_CTS# 58

PIO[18] 65

PIO[21] 64

LED_0

LED_1

LED_2

PIO_0

PIO_1

PIO_6

PIO_7

PIO_8

PIO_9

PIO_18

PIO_21

PIO[2] / PCM1_IN / SPI_MOSI30

PIO[3] / PCM1_OUT / SPI_MISO28

PIO[4] / PCM1_SYNC / SPI_CS#24

PIO[5] / PCM1_CLK / SPI_CLK 34

SPI_PCM# 29

PIO[12] / QSPI_FLASH_CS# / I2C_WP22

PIO[10] / QSPI_FLASH_CLK / I2C_SCL25

PIO[11] / QSPI_IO[0] / I2C_SDA26

PIO[13] / QSPI_IO[1] 31

PIO[14] / UART_RX 23

PIO[15] / UART_TX 21

PIO[16] / UART_RTS# 27

PIO[17] / UART_CTS# 32

AIO[0] 20

USB_P 56

USB_N 55

RST# 35

PIO_2

PIO_3

PIO_4

PIO_5

SPI_PCM#

PIO_12

PIO_10

PIO_11

PIO_13

PIO_14

PIO_15

PIO_16

PIO_17

AIO_0

USB_P

USB_N

RSTB

C12

2u2

C13

2u2

C14

2u2

Line Inputs

C15

2u2

C16

2u2

1V8_SMPS

Left Right

Speakers (16-32 Ohm)

Optional Ancilliary Circuits

USB / Charger Interface Optional Fast charge

400mohm = 500mA

VBUS VBUS

CHG_EXT 1

VBAT_SENSE

VBAT

Q100

BCX51

R104

1%

400mR

C105

4u7

R108

220mR

CON100

USB MINI-B

VBUS 1

D- 2

D+ 3

ID 4

GND 5

USB_N

USB_P

Connect VBAT_SENSE to VBAT if not using this circuit

LED outputs

PIO / UART

Battery temperature sensor

VBAT VBUS 1V35_SMPS

R100

Typical LED's and Buttons

Optional I2C EEPROM memory

Lithium Polymer Battery

(battery protection built in)

AIO_0

9k1

1V8_SMPS

C100

D100

BAT54C

1V8 1V8 1V8 1V8 1V8

R105

2k2

R106

2k2 U101

10n

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Li+ CELL

VBAT

3.7V

D

THERM

10k

Q1

C102

10n

PIO_n

D101

R101

220R

D102

R102

330R

D103

R103

330R

F4 F3 F2 VOL+ VOL-

PIO_12

PIO_10

PIO_11

8

7

6

5

A0 1

A1 2

A2 3

VSS 4

24AAxxx

G

R107

2k2

VCC

WP

SCL

SDA

S

Optional 1x SPI FLASH memory

1V8_SMPS

C101

10n

PIO_11

PIO_13

1V8_SMPS

5

2

3

7

8

U100

VDD

SI/SIO0

SO/SIO1

WP/SIO2

HOLD/SIO3

CE 1

SCK 6

VSS 4

SPI Flash

PIO_12

PIO_10

Size of EEPROM depends on voice prompt requirements

PIO / PCM1 / Debug SPI / I

2

S

SPI/PCM# high for SPI. Low for all other functions

PIO / Serial Flash / I

2

C

PIO / UART

Analogue Input / Output

USB (12Mbps)

Reset

Figure 12.2: Dual/Stereo Line Input

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13 Electrical Characteristics

13.1 Absolute Maximum Ratings

Rating

Storage temperature

Supply Voltage

Charger VCHG

LEDs

Battery

1.8V

LED[2:0]

VBAT_SENSE

VREGENABLE

VDD_AUDIO_DRV

VDD_AUX_1V8

VDD_PADS_1

VDD_PADS_2

1.35V

SMPS_1V35_SENSE

VDD_AUDIO

VREGIN_DIG

Other terminal voltages

Min

-40

-0.4

-0.4

-0.4

-0.4

-0.4

-0.4

-0.4

-0.4

-0.4

-0.4

-0.4

VSS - 0.4

Max

105

5.75 / 6.50

(a)

4.40

4.40

4.40

1.95

1.95

3.60

3.60

1.45

1.45

1.95

VDD + 0.4

V

V

V

V

V

V

V

V

V

V

V

Unit

°C

V

(a) Standard maximum input voltage is 5.75V, a 6.50V maximum requires a correct patch bundle, for more information contact CSR

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13.2 Recommended Operating Conditions

Rating

Operating temperature range

Supply Voltage

Charger VCHG

LEDs

Battery

1.8V

1.35V

LED[2:0]

VBAT_SENSE

VREGENABLE

VDD_AUDIO_DRV

VDD_AUX_1V8

VDD_PADS_1

VDD_PADS_2

SMPS_1V35_SENSE

VDD_AUDIO

VREGIN_DIG

Min

-40

4.75 / 3.10

(a)

1.10

0

0

1.70

1.70

1.70

1.70

1.30

1.30

1.30

Typ

20

5.00

3.70

3.70

3.70

1.80

1.80

1.80

1.80

1.35

1.35

1.35 or 1.80

(c)

Max

85

5.75 / 6.50

(b)

4.30

4.25

4.25

1.95

1.95

3.60

3.60

1.45

1.45

1.95

(a)

Minimum input voltage of 4.75 V is required for full specification, regulator operates at reduced load current from 3.1 V

(b)

Standard maximum input voltage is 5.75 V, a 6.50 V maximum requires a correct patch bundle, for more information contact CSR

(c)

Typical value depends on output required by the low-voltage VDD_DIG linear regulator, see Section 13.3.2.2

V

V

V

V

V

V

V

V

V

V

Unit

°C

V

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13.3 Input/Output Terminal Characteristics

Note:

For all I/O terminal characteristics:

■ Current drawn into a pin is defined as positive; current supplied out of a pin is defined as negative.

13.3.1 Regulators: Available For External Use

13.3.1.1 1.8V Switch-mode Regulator

1.8V Switch-mode Regulator

Input voltage

Output voltage

Normal Operation

Transient settling time

Load current

Current available for external use, audio with 16Ω load

(a)

Peak conversion efficiency

(b)

Switching frequency

Inductor saturation current, audio and 16Ω load

Inductor ESR

Low-power Mode, Automatically Entered in Deep Sleep

Transient settling time

Load current

Current available for external use

Peak conversion efficiency

Switching frequency

-

-

-

-

3.63

250

0.1

Min

2.80

1.70

-

0.005

-

-

100

-

90

30

-

4.00

-

0.3

200

-

-

85

-

Typ

3.70

1.80

-

185

25

-

4.00

-

0.8

5

-

-

5

200

Max

4.25

1.90

μs mA mA

% kHz

Unit

V

V

μs mA mA

%

MHz mA

Ω

(a)

(b)

Conversion efficiency depends on inductor selection.

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13.3.1.2 Combined 1.8V and 1.35V Switch-mode Regulator

Combined 1.8V and 1.35V Switch-mode Regulator

Input voltage

Output voltage

Normal Operation

Transient settling time

Load current

Current available for external use, audio with 16Ω load

(a)

Peak conversion efficiency (b)

Switching frequency

Inductor saturation current, audio and 16Ω load

Inductor ESR

Low-power Mode, Automatically Entered in Deep Sleep

Transient settling time

Load current

Current available for external use

Peak conversion efficiency

Switching frequency

Min

2.80

1.70

-

0.005

-

-

100

-

3.63

400

0.1

-

-

-

(a)

More current available for audio loads above 16Ω.

(b)

Conversion efficiency depends on inductor selection.

90

4.00

-

0.3

30

-

-

200

-

-

85

-

Typ

3.60

1.80

%

MHz mA

Ω

μs mA mA

μs mA mA

% kHz

Unit

V

V

-

4.00

-

0.8

-

340

25

5

-

-

5

200

Max

4.25

1.90

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13.3.1.3 Bypass LDO Regulator

Normal Operation

Input voltage

Output voltage (V in

> 4.75V)

Output current (V in

> 4.75V)

Min

4.25 / 3.10

(a)

3.00

-

Typ

5.00

3.30

-

Max

5.75 / 6.50

(b)

3.60

250

(a) Minimum input voltage of 4.25V is required for full specification, regulator operates at reduced load current from 3.1V

(b)

Standard maximum input voltage is 5.75V, a 6.50V maximum requires a correct patch bundle, for more information contact CSR

13.3.2 Regulators: For Internal Use Only

13.3.2.1 1.35V Switch-mode Regulator

1.35V Switch-mode Regulator

Input voltage

Output voltage

Normal Operation

Transient settling time

Load current

Current available for external use

Min

2.80

1.30

-

-

-

Typ

3.60

1.35

30

-

-

Max

4.25

1.40

-

160

0

Peak conversion efficiency

(a)

Switching frequency

Inductor saturation current, audio and 16Ω load

Inductor ESR

Low-power Mode, Automatically Entered in Deep Sleep

Transient settling time

-

3.63

220

0.1

88

4.00

-

0.3

-

4.00

-

0.8

200 -

Load current 0.005

5

Prepared for qingbo keven.zhou - excelpoint.com.cn - Friday, September 27, 2013

Current available for external use 0

Peak conversion efficiency 85 -

Switching frequency 100 200

(a)

Conversion efficiency depends on inductor selection.

μs mA mA

%

MHz mA

Ω

Unit

V

V

μs mA mA

% kHz

Unit

V

V mA

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13.3.2.2 Low-voltage VDD_DIG Linear Regulator

Normal Operation

Input voltage

Output voltage

(a)

Internal load current

(a)

Output voltage level is software controlled

13.3.2.3 Low-voltage VDD_AUX Linear Regulator

Normal Operation

Input voltage

Output voltage

Internal load current

13.3.2.4 Low-voltage VDD_ANA Linear Regulator

Normal Operation

Input voltage

Output voltage

Load current

13.3.3 Regulator Enable

VREGENABLE, Switching Threshold

Rising threshold

13.3.4 Battery Charger

Min

1.30

0.80

-

Min

1.70

1.30

-

Min

1.70

1.30

-

Min

1.0

Typ

1.35 or 1.80

0.90 / 1.20

-

Typ

1.80

1.35

-

Typ

1.80

1.35

-

Typ

-

Max

1.95

1.25

80

Max

1.95

1.45

60

Max

1.95

1.45

5

Max

-

Battery Charger

Input voltage, VCHG

Min

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4.75 / 3.10

(a)

Typ

5.00

Max

5.75 / 6.50

(b)

(a)

Reduced specification from 3.1V to 4.75V. Full specification >4.75V.

(b)

Standard maximum input voltage is 5.75V, a 6.50V maximum requires a correct patch bundle, for more information contact CSR.

Unit

V

Unit

V

V mA

Unit

V

V mA

Unit

V

V mA

Unit

V

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Trickle Charge Mode

Charge current I trickle

, as percentage of fast charge current

V fast

rising threshold

V fast

rising threshold trim step size

V fast

falling threshold

Fast Charge Mode

Charge current during constant current mode, I fast

Maximum charge setting

(VCHG-VBAT > 0.55V)

Minimum charge setting

(VCHG-VBAT > 0.55V)

Reduced headroom charge current, as a percentage of I fast

(VCHG-VBAT < 0.55V)

Charge current step size

V float

threshold, calibrated

Charge termination current I term

, as percentage of I fast

Standby Mode

Voltage hysteresis on VBAT, V hyst

Typ

200

10

-

10

4.20

10

Typ

10

2.9

0.1

2.8

Typ

-

Min

194

-

50

-

4.16

7

Min

8

-

-

-

Min

100

Error Charge Mode

Headroom

(a)

error falling threshold

(a) Headroom = VCHG - VBAT

Min

-

Typ

50

Max

-

Unit mV

External Charge Mode

(a) Min Typ Max

Fast charge current, I fast

200 500

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Control current into CHG_EXT 0 20

Voltage on CHG_EXT

External pass device h fe

Sense voltage, between VBAT_SENSE and VBAT at maximum current

0

-

195

-

50

200

5.75 / 6.50

(b)

-

205 mV

(a)

In the external mode, the battery charger meets all the previous charger electrical characteristics and the additional or superseded electrical characteristics are listed in this table.

(b)

Standard maximum input voltage is 5.75V, a 6.50V maximum requires a correct patch bundle, for more information contact CSR.

Unit mA mA

V

-

Max

206

-

100

-

4.24

20

Max

12

-

-

-

Max

150

Unit mA mA

% mA

V

%

Unit

%

V

V

V

Unit mV

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13.3.5 USB

VDD_USB for correct USB operation

Input Threshold

V

IL

input logic level low

V

IH

input logic level high

Output Voltage Levels to Correctly Terminated USB Cable

V

OL

output logic level low

V

OH

output logic level high

Min

3.1

-

0.7 x

VDD_USB

0

2.8

-

-

Typ

3.3

Max

3.6

0.3 x

VDD_USB

-

Unit

V

V

V

-

-

0.2

VDD_USB

V

V

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13.3.6 Stereo Codec: Analogue to Digital Converter

Analogue to Digital Converter

Parameter

Resolution

Input Sample Rate,

F sample

-

Conditions

Maximum ADC Input

Signal Amplitude

0dB = 1600mV pk-pk

SNR f in

= 1kHz

B/W = 20Hz→F sample

(20kHz max)

/2

A-Weighted

THD+N < 0.1%

1.6V

pk-pk

input

F sample

8kHz

16kHz

32kHz

44.1kHz

48kHz

F sample

THD+N f in

= 1kHz

B/W = 20Hz→F

(20kHz max)

1.6V

pk-pk

input sample

/2

8kHz

48kHz

Digital gain

Analogue gain

Digital gain resolution = 1/32

Pre-amplifier setting = 0dB, 9dB, 21dB or

30dB

Analogue setting = -3dB to 12dB in 3dB steps

Stereo separation (crosstalk)

Min

-

8

13

-3

-

-

-

-24

-

-

-

-

-

Typ

-

-

-

94.4

92.4

92.5

93.2

91.9

0.004

0.016

-

Max

16

48

2260

-

-89.9

-

-

-

-

-

42

-

-

-

21.5

Unit

Bits kHz mV pk-pk dB dB dB dB dB dB dB

%

% dB

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13.3.7 Stereo Codec: Digital to Analogue Converter

Digital to Analogue Converter

Parameter Conditions

Resolution

Output Sample

Rate, F sample

-

F sample

SNR f in

= 1kHz

B/W = 20Hz→20kHz

A-Weighted

THD+N < 0.1%

0dBFS input

THD+N f in

= 1kHz

B/W = 20Hz→20kHz

0dBFS input

Digital Gain

Analogue Gain

Digital Gain Resolution = 1/32

Analogue Gain Resolution = 3dB

Output voltage Full-scale swing (differential)

Stereo separation (crosstalk)

8kHz

48kHz

48kHz

48kHz

48kHz

48kHz

48kHz

F sample

8kHz

8kHz

Load

100kΩ

32Ω

16Ω

Load

100kΩ

32Ω

16Ω

100kΩ

32Ω

16Ω

Min

-

8

-

-

-24

-21

-

-

-

-

-

-

-

-

-

Typ

-

-

95.4

96.5

95.8

0.0021

0.0031

-

-

-

-90.5

0.0034

0.0037

0.0029

0.0042

21.5

0

778

-

-

-

-

-

-

-

Max

16

96

-

-

-

Unit

Bits kHz dB dB dB

%

% dB dB mV rms dB

%

%

%

%

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13.3.8 Digital

Digital Terminals

Input Voltage

V

IL

input logic level low

V

IH

input logic level high

Tr/Tf

Output Voltage

V

OL

output logic level low, l

OL

= 4.0mA

V

OH

output logic level high, l

OH

= -4.0mA

Tr/Tf

Input and Tristate Currents

Strong pull-up

Strong pull-down

Weak pull-up

Weak pull-down

C

I

Input Capacitance

Min

-0.4

0.7 x VDD

-

-

0.75 X VDD

-

Typ

-

-

-

-

-

-

Max

0.4

VDD + 0.4

25

0.4

-

5

13.3.9 LED Driver Pads

LED Driver Pads

Current, I

PAD

High impedance state

Current sink state

I

PAD

= 10mA

-

-

Min

-

-

-

Typ

-

Max

5

10

0.55

LED pad voltage, V

PAD

LED pad resistance

V

PAD

< 0.5V

40

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V

OL

output logic level low (a)

0 -

V

OH

output logic level high

(a)

V

IL

input logic level low

V

IH

input logic level high

-

-

0.8

0

0.8

-

-

-

(a)

LED output port is open-drain and requires a pull-up

-150

10

-5

0.33

1.0

-40

40

-1.0

1.0

-

-10

150

-0.33

5.0

5.0

Unit

V

V

V

V

Unit

µA mA

V

Ω

μA

μA

μA

μA pF

V

V ns

V

V ns

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13.3.10 Auxiliary ADC

Auxiliary ADC

Resolution

Input voltage range

(a)

Accuracy

(Guaranteed monotonic)

Offset

Gain error

Input bandwidth

Conversion time

Sample rate

(b)

INL

DNL

-1

-0.8

-

1.38

-

Min

-

0

-1

0

100

1.69

-

-

-

-

-

-

Typ

-

1

0.8

-

2.75

700

Max

10

VDD_AUX

1

1

LSB

% kHz

µs

Samples/s

Unit

Bits

V

LSB

LSB

(a)

LSB size = VDD_AUX/1023

(b)

The auxiliary ADC is accessed through a VM function. The sample rate given is achieved as part of this function.

13.3.11 Auxiliary DAC

Auxiliary DAC

Resolution

Supply voltage, VDD_AUX

Output voltage range

Full-scale output voltage

LSB size

Min

-

1.30

0

1.30

0

Typ

-

1.35

-

1.35

1.32

Max

10

1.40

VDD_AUX

1.40

2.64

Offset

Integral non-linearity

-1.32

-1

0

0

1.32

1 mV

LSB

Settling time

(a) 250

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(a)

The settling time does not include any capacitive load

Important Note:

Access to the auxiliary DAC is firmware-dependent, for more information about its availability contact CSR.

Unit

Bits

V

V

V mV

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13.4 ESD Protection

Apply ESD static handling precautions during manufacturing.

Table 13.1 shows the ESD handling maximum ratings.

Condition

Human Body Model Contact Discharge per

ANSI/ESDA/JEDEC JS‑001

Charged Device Model Contact Discharge per

JEDEC/EIA JESD22‑C101

Class Max Rating

2

2kV (all pins except CHG_EXT; CHG_EXT is rated at 1kV)

III 500V (all pins)

Table 13.1: ESD Handling Ratings

13.4.1 USB Electrostatic Discharge Immunity

CSR8635 QFN has integrated ESD protection on the USB_DP and USB_DN pins as detailed in IEC 61000‑4‑2.

CSR has tested CSR8635 QFN assembled in development kits to assess the Electrostatic Discharge Immunity. The tests were based on IEC 61000‑4‑2 requirements. Tests were performed up to level 4 (8kV contact discharge / 15kV air discharge).

CSR can demonstrate normal performance up to level 2 (4kV contact discharge / 4kV air discharge) as per IEC 6100-4-2 classification 1. Above level 2, temporary degradation is seen (classification 2).

CSR8635 QFN contains a reset protection circuit and software, which will attempt to re-make any connections lost in a ESD event. If the device at the far end permits this, self-recovery of the Bluetooth link is possible if CSR8635 QFN resets on an ESD strike. This classes CSR8635 QFN as IEC 61000‑4‑2 classification 2 to level 4 (8kV contact discharge / 15kV air discharge). If self-recovery is not implemented, CSR8635 QFN is IEC 61000‑4‑2 classification 3 to level 4.

Note:

Any test detailed in the IEC-61000-4-2 level 4 test specification does not damage CSR8635 QFN.

The CSR8635 QFN USB VBUS pin is protected to level 4 using an external 2.2µF decoupling capacitor on VCHG.

Important Note:

CSR recommends correct PCB routing and to route the VBUS track through a decoupling capacitor pad.

When the USB connector is a long way from CSR8635 QFN, place an extra 1µF or 2.2µF capacitor near the USB connector.

No components (including 22Ω series resistors) are required between CSR8635 QFN and the USB_DP and

USB_DN lines.

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CSR8635 QFN and signal the unintended reset to the VM.

Table 13.2 summarises the level of protection.

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IEC 61000‑4‑2

Level

ESD Test Voltage

(Positive and Negative)

IEC 61000‑4‑2

Classification

Comments

1

2

3

4

2kV contact / 2kV air

4kV contact / 4kV air

6kV contact / 8kV air

8kV contact / 15kV air

Class 1

Class 1

Class 2 or class 3

Class 2 or class 3

Normal performance within specification limits

Normal performance within specification limits

Temporary degradation or operator intervention required

Temporary degradation or operator intervention required

Table 13.2: USB Electrostatic Discharge Protection Level

For more information contact CSR.

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14 Power Consumption

DUT Role

Slave

Slave

Slave

Slave

Slave

Slave

Slave

Slave

Slave

Slave

Slave

Slave

Connection

SCO eSCO eSCO

Packet Type Packet Size

HV3

EV3

3EV3

30

30

60

Average

Current

11.0

11.8

9.2

SCO eSCO eSCO eSCO

SCO eSCO eSCO

1-mic CVC:

8kHz sampling

Narrowband

1-mic CVC:

8kHz sampling

Narrowband

1-mic CVC:

16kHz sampling

Wideband

1-mic CVC:

16kHz sampling

FESI

1-mic CVC hands-free:

8kHz sampling

Narrowband

1-mic CVC hands-free:

8kHz sampling

Narrowband

1-mic CVC hands-free:

16kHz sampling

Wideband

HV3

2EV3

2EV3

2EV3

HV3

2EV3

2EV3

30

60

60

60

30

60

60

12.6

10.8

11.4

10.9

12.2

10.4

11.2

1-mic CVC hands-free:

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■ FESI

2EV3 60 10.7

A2DP Stereo streaming SBC high quality:

Bit-Pool = 50, 16 blocks and 8 subbands

48kHz sampling

No sniff

White noise

13.3

Unit mA mA mA mA mA mA mA mA mA mA mA mA

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Slave

Slave

Master

Master

Master

DUT Role

Slave

Master

Master

Master

Master

Master

Master

Connection Packet Type Packet Size

Average

Current

A2DP Stereo streaming SBC low quality:

Bit-Pool = 20, 16 blocks and 8 subbands

48kHz sampling

No sniff

White noise

ACL

ACL

SCO

Sniff = 500ms

Sniff = 1280ms eSCO eSCO

SCO eSCO eSCO eSCO

SCO

1-mic CVC:

8kHz sampling

Narrowband

1-mic CVC:

8kHz sampling

Narrowband

1-mic CVC:

16kHz sampling

Wideband

1-mic CVC:

16kHz sampling

FESI

1-mic CVC hands-free:

8kHz sampling

Narrowband

-

-

-

HV3

EV3

3EV3

HV3

2EV3

2EV3

2EV3

HV3

-

-

-

30

30

60

30

60

60

60

30

11.8

213

142

10.8

11.2

8.8

12.5

10.5

11.0

10.6

12.1

1-mic CVC hands-free:

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■ Narrowband

2EV3 60 10.1

Unit mA mA mA mA mA mA mA

µA

µA mA mA mA

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DUT Role Connection Packet Type Packet Size

Master

Master

Master

Master eSCO eSCO

1-mic CVC hands-free:

16kHz sampling

Wideband

1-mic CVC hands-free:

16kHz sampling

FESI

A2DP Stereo streaming SBC high quality:

Bit-Pool = 50, 16 blocks and 8 subbands

48kHz sampling

No sniff

White noise

-

2EV3

2EV3

A2DP Stereo streaming SBC low quality:

Bit-Pool = 20, 16 blocks and 8 subbands

48kHz sampling

No sniff

White noise

ACL

ACL

Sniff = 500ms

Sniff = 1280ms

-

-

-

-

60

60

Master

Master

-

-

Note:

Current consumption values are taken with:

VBAT pin = 3.7V

RF TX power set to 0dBm

No RF retransmissions in case of eSCO

Microphones and speakers disconnected

Audio gateway transmits silence when SCO/eSCO channel is open

LEDs disconnected

AFH classification master disabled

Average

Current

10.8

10.2

13.2

10.9

197

142

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Unit mA mA mA mA

µA

µA

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15 CSR Green Semiconductor Products and RoHS Compliance

CSR confirms that CSR Green semiconductor products comply with the following regulatory requirements:

Restriction on Hazardous Substances directive guidelines in the EU RoHS Directive 2011/65/EU

1

.

EU REACH, Regulation (EC) No 1907/2006

POP regulation (EC) No 850/2004

1

1

.

1

:

List of substances subject to authorisation (Annex XIV)

Restrictions on the manufacture, placing on the market and use of certain dangerous substances, preparations and articles (Annex XVII). This Annex now includes requirements that were contained within

EU Directive, 76/769/EEC. There are many substance restrictions within this Annex, including, but not limited to, the control of use of Perfluorooctane sulfonates (PFOS).

When requested by customers, notification of substances identified on the Candidate List as Substances of Very High Concern (SVHC)

EU Packaging and Packaging Waste, Directive 94/62/EC 1

Montreal Protocol on substances that deplete the ozone layer.

Conflict minerals, Section 1502, Dodd-Frank Wall Street Reform and Consumer Protection act, which affects columbite-tantalite (coltan / tantalum), cassiterite (tin), gold, wolframite (tungsten) or their derivatives. CSR is a fabless semiconductor company: all manufacturing is performed by key suppliers. CSR have mandated that the suppliers shall not use materials that are sourced from "conflict zone mines" but understand that this requires accurate data from the EICC programme. CSR shall provide a complete EICC / GeSI template upon request.

CSR has defined the "CSR Green" standard based on current regulatory and customer requirements including free from bromine, chlorine and antimony trioxide.

Products and shipment packaging are marked and labelled with applicable environmental marking symbols in accordance with relevant regulatory requirements.

This identifies the main environmental compliance regulatory restrictions CSR specify. For more information on the full

"CSR Green" standard, contact [email protected]

.

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1

Including applicable amendments to EU law which are published in the EU Official Journal, or SVHC

Candidate List updates published by the European Chemicals Agency (ECHA).

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16 Software

CSR8635 QFN:

Includes integrated Bluetooth v4.0 specification qualified HCI stack firmware

Includes integrated CSR8635 Stereo ROM Solution, with 6 a configurable EQ th

generation 1-mic CVC audio enhancements and

Can be shipped with CSR’s CSR8635 stereo ROM solution development kit for CSR8635 QFN, order code

DK‑8635‑10163‑1A

The CSR8635 QFN software architecture enables Bluetooth processing and the application program to run on the internal RISC MCU, and the audio enhancements on the Kalimba DSP.

16.1 CSR8635 Stereo ROM Solution

The CSR8635 stereo ROM solution software supports:

6 th

generation 1-mic CVC audio enhancements

WNR

PLC / BEC mSBC wideband speech codec

A2DP v1.2

HFP v1.6 and HSP v1.2

SCMS-T

Bluetooth v4.0 specification is supported in the ROM software

Secure simple pairing

Proximity pairing (device-initiated pairing) for greatly simplifying the out-of-box pairing process, for more information see Section 16.1.8

For connection to more than 1 mobile phone, advanced Multipoint is supported. This enables a user to take calls from a work and personal phone or a work phone and a VoIP dongle for Skype users. This has minimal impact on power consumption and is easy to configure.

Most of the CSR8635 stereo ROM solution ROM software features are configured on the CSR8635 QFN using the Headset Configuration Tool. The tool reads and writes device configurations directly to the EEPROM, serial flash or alternatively to a PSR file. Configurable device features include:

Bluetooth v4.0 specification features

Reconnection policies, e.g. reconnect on power-on

Audio features, including default volumes

Button events: configuring button presses and durations for certain events, e.g. double press on PIO[1]

■ for last number redial

LED indications for states, e.g. device connected, and events, e.g. power on

Indication tones for events and ringtones

HFP v1.6 supported features

Battery divider ratios and thresholds, e.g. thresholds for battery low indication, full battery etc.

Advanced Multipoint settings

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AAC, SBC, MP3 and Faststream decoder

Stereo widening (S3D)

Volume Boost

USB audio mode for streaming high-quality music from a PC whilst charging, enables the device to:

Playback high-quality stereo music, e.g. iTunes

Use bidirectional audio in conversation mode, e.g. for Skype

Wired audio mode for pendant-style devices supports music playback using a line-in jack. Enables non

Bluetooth operation in low battery modes or when using the device in an airplane-mode.

Support for smartphone applications (apps)

The CSR8635 stereo ROM solution has undergone extensive interoperability testing to ensure it works with the majority of phones on the market

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16.1.1 Advanced Multipoint Support

Advanced Multipoint enables the connection of 2 devices to a CSR8635 QFN device at the same time, examples include:

2 phones connected to a CSR8635 QFN device

Phone and a VoIP dongle connected to a CSR8635 QFN device

Phone and tablet

The CSR8635 stereo ROM solution:

Supports up to 2 simultaneous connections (either HFP or HSP)

Enables multiple-call handling from both devices at the same time

Treats all device buttons:

During a call from one device, as if there is 1 device connected

During multiple calls (1 on each device), as if there is a single AG with multiple calls in progress (threeway calling)

During multiple calls (more than 1 on each device), as if there are multiple calls on a single device enabling the user to switch between the active and held calls

16.1.2 A2DP Multipoint Support

A2DP Multipoint support enables the connection of 2 A2DP source devices to CSR8635 QFN at the same time, examples include:

2 A2DP-capable phones connected to a CSR8635 QFN device

A2DP-capable phone and an A2DP-only source device, e.g. a PC or an iPod touch

The CSR8635 stereo ROM solution enables:

Music streaming from either of the connected A2DP source devices where the music player is controlled on the source device

Advanced HFP Multipoint functions to interrupt music streaming for calls, and resume music streaming on the completion of the calls

AVRCP v1.4 connections to both connected devices, enabling the device to remotely control the primary device, i.e. the device currently streaming audio

16.1.3 Wired Audio Mode

CSR8635 QFN supports a wired audio mode for playing music over a wired connection.

If CSR8635 QFN is powered, the audio path is routed through CSR8635 QFN, including via the DSP, this enables the

CSR8635 QFN to:

Mix audio sources, e.g. tones and programmable audio prompts

Control the volume of the audio, i.e. volume up and volume down

Utilise the 5 band EQ

In wired audio mode, if required, the CSR8635 QFN is still available for Bluetooth audio. This enables seamless transition from wired audio mode to Bluetooth audio mode and back again. This transition is configurable to occur automatically as the battery voltage of the device reduces to a point at which Bluetooth audio is no longer possible.

16.1.4 USB Modes Including USB Audio Mode

CSR8635 QFN supports a variety of USB modes which enables the USB interface to extend the functionality of a

CSR8635 QFN based stereo device.

CSR8635 QFN supports:

USB charger enumeration

USB soundcard enumeration (USB audio mode)

USB mass storage enumeration

USB audio mode enables the device to enumerate as a soundcard while charging from a USB master device, e.g. a

PC. In this mode, the device enumerates as either a stereo music soundcard (for high quality music playback) or a bidirectional voice quality soundcard. This enables the device for either listening to music streaming from the USB host device or for voice applications, e.g. Skype.

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The USB audio mode operates at the same time as the wired audio mode and the USB audio interrupts the wired audio mode if USB audio is attached. This enables a device to have both wired audio and USB modes connected at the same time.

In USB audio mode, if required, the device is still available for Bluetooth audio.

16.1.5 Smartphone Applications (Apps)

CSR8635 QFN includes CSR’s proprietary mechanism for communicating with smartphone apps, it enables full UI control of the device from within the application running on a smartphone, e.g. Google Android OS-based handset. For more information on this feature contact CSR.

16.1.6 Programmable Audio Prompts

CSR8635 QFN enables a user to configure and load pre-programmed audio prompts from:

An external EEPROM, in this implementation the prompts are stored in the same EEPROM as the PS Keys, see Figure 16.2. A larger EEPROM is necessary for programmable audio prompts. This implementation supports EEPROMs up to 512Kb. An EEPROM of 512Kb enables approximately 15 seconds of audio storage.

An external SPI flash, in this implementation the prompts are stored in the same SPI flash as the PS Keys, see Figure 16.1.

The programmable audio prompts provide a mechanism for higher-quality audio indications to replace standard tone indications. A programmable audio prompt is assigned to any user event in place of a standard tone.

Programmable audio prompts contain either voice prompts to indicate that events have occurred or provide user-defined higher quality ring tones/indications, e.g. custom power on/off tones.

The Headset Configuration Tool can generate the content for the programmable audio prompts from standard WAV audio files. The tool also enables the user to configure which prompts are assigned to which user events.

Section 6.5 describes the SPI flash interface and Section 7.4 describes the I²C interface to an external EEPROM.

SPI Flash

PS Keys

Configuration

Patches

CSR8635 SPI

Programmable

Audio Prompts

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CSR8635 I

2

C

EEPROM

PS Keys

Configuration

Patches

Programmable

Audio Prompts

Figure 16.2: Programmable Audio Prompts in External I²C EEPROM

Note:

When using the SPI flash interface for programmable audio prompts, an EEPROM device is not required in the

CSR8635 stereo ROM solution.

16.1.7 CSR’s Intelligent Power Management

IPM extends the available talk time of a CSR8635 QFN-based device, by automatically reducing the audio processing performed by CVC at a series of low battery capacity thresholds.

Configurable IPM features include:

IPM enable/disable

The battery capacity that engages IPM

A user-action to enable or disable the IPM

If engaged, CVC processing reduces automatically on reaching the preset battery capacity. Once the audio is terminated, the DSP shuts down to achieve maximum power savings before the next call.

IPM resets when recharging the device. The talk time extension depends on:

The battery size

The battery condition

The threshold capacity configured for the IPM to engage

16.1.8 Proximity Pairing

Proximity pairing is device-initiated pairing and it simplifies the out-of-box pairing process. Proximity pairing enables the device to find the closest discoverable phone. The device then initiates the pairing activity and the user simply has to accept the incoming pairing invitation on the phone.

This means that the phone-user does not have to hunt through phone menus to pair with the new device.

Depending on the phone UI:

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For a Bluetooth v2.1 (or above) phone the device pairing is without a PIN code

Proximity pairing is based on finding and pairing with the closest phone. To do this, the device finds the loudest phone by carrying out RSSI power threshold measurements. The loudest phone is the one with the largest RSSI power threshold measurement, and it is defined as the closest device. The device then attempts to pair with and connect to this device.

Proximity pairing is configurable using the Headset Configuration Tool available from www.csrsupport.com

.

16.1.9 Proximity Connection

Proximity connection is an extension to proximity pairing, see Section 16.1.8. It enables the device‑user to take advantage of the proximity of devices each time the device powers up and not just during a first time pairing event.

Proximity connection enables a user with multiple handsets to easily connect to the closest discoverable phone by comparing the proximity of devices to the device at power-on to the list of previously paired devices.

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Proximity connection speeds up the device connection process. It requires the device to initiate a SLC connection to the nearest device first and combines this with the device's storage of the last 8 paired/connected devices. Using proximity connection means functions operate equally well for the most or least recently paired or connected device.

16.2 6

th

Generation 1-mic CVC ENR Technology for Hands-free and Audio

Enhancements

1-mic CVC full-duplex voice processing software is a fully integrated and highly optimised set of DSP algorithms developed to ensure easy design and build of hands-free products.

CVC enables greater acoustic design flexibility for a wide variety of environments and configurations as a result of sophisticated noise and echo suppression technology. CVC reduces the affects of noise on both sides of the conversation and smartly adjusts the receive volume levels and dynamically frequency shapes the voice to achieve optimal intelligibility and comfort for the hands-free user.

The 6 th

generation CVC features include:

Full-duplex AEC

Bit error and packet loss concealment

Transmit and receive noise suppression including WNR

Transmit and receive Parametric Equalisation

Transmit and receive AGC

Noise dependent volume control

Receive frequency enhanced speech intelligibility using adaptive equaliser

Narrowband, wideband and frequency expansion operations

1-mic CVC includes a tuning tool enabling the developer to easily adapt CVC with different audio configurations and tuning parameters. The tool provides real-time system statistics with immediate feedback enabling designers to quickly investigate the effect of changes.

Figure 16.3 shows the functional block diagram of CSR’s proprietary 1-mic CVC DSP solution for a hands-free product.

Send In

Mic

Gain

Acoustic Echo

Canceller

Noise

Suppression

Nonlinear

Processing

Howling

Control

Comfort Noise Send Equaliser Send AGC

NDVC

Receive Out

Speaker Gain Clipper

Auxiliary

Stream Mix

Receive AGC

Receive

Equaliser

Adaptive

Equaliser

Noise

Suppression

Packet Loss

Concealment

Send

Out

Receive

In

Section 16.2.1 to Section 16.2.13 describe the audio processing functions provided within CVC.

16.2.1 Acoustic Echo Cancellation

The AEC includes:

A referenced sub-band adaptive linear filter that models the acoustic path from the receive reference point to the microphone input

A non-linear processing function that applies narrowband and wideband attenuation adaptively as a result of residual echo present after the linear filter.

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16.2.2 Noise Suppression with Wind Noise Reduction

The signal-channel noise suppression block is implemented in both signal paths. They are completely independent and individually tuned. Noise suppression is a sub-band stationary / quasi-stationary noise suppression algorithm that uses the temporal characteristics of speech and noise to remove the noise from the composite signal while maximising speech quality. The current implementation can improve the SNR by up to 20dB.

In the transmit path, noise suppression aggressiveness is typically 95% improving SNR by 15 to 19dB to compensate for the upstream processing and to maintain superior voice quality, while the Rx is typically tuned down to 80% improving

SNR by 8 to 12dB because of the cellular network processing. The user can parametrically adjust these default settings.

The noise suppression block contains a new WNR feature (send path only). The WNR removes unwanted noise during a hands-free conversation, cleaning the audio for the far-end listener. It detects and tackle winds of various intensities and durations. Once the wind is detected, a good balance between voice quality and WNR is achieved.

16.2.3 Non-linear Processing (NLP)

The non-linear processing module detects the presence of echo after the primary sub-band linear filter and adaptively applies attenuation at frequencies where echo is identified. It is used to minimise echo due to non-linearity caused by the system, i.e. the loudspeaker and microphone, amplifiers, electronics etc. CSR recommends minimal use of nonlinear processing due to the inherent distortion that it introduces.

16.2.4 Howling Control (HC)

The Howling Control is a programmable coupling threshold that when triggered applies attenuation to the send path.

This control enables CVC to operate in car-to-car calls without experiencing echo events during very high volume situations.

16.2.5 Comfort Noise Generator

The CNG:

Creates a spectrally and temporally consistent noise floor for the far-end listener.

Adaptively inserts noise modelled from the noise present at the microphone into gaps introduced when the non-linear processing of the AEC applies attenuation. The noise level applied is user-controllable.

16.2.6 Equalisation

The equalisation filters:

Are independent in the send and receive signal channels

Are independently enabled

Are configurable to achieve the required frequency response

Each channel comprises of 5 stages of cascaded 2 nd

order IIR filters

Compensate for the frequency response of transducers in the system, i.e. the microphone and loud speaker

16.2.7 Automatic Gain Control

The AGC block attempts to:

Normalise the amplitude of the incoming audio signal to a desired range to increase perceived loudness

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Reduce amplitude variance observed from different users, phones and networks

Maintaining a consistent long-term loudness for the speech ensures it is more easily heard by the listener and it also provides the subsequent processing block a larger amplitude signal to process. The behaviour of the AGC differs from a dynamic range audio compressor. The convergence time for the AGC is much slower to reduce the non-linear distortion.

16.2.8 Packet Loss Concealment

Bit errors and packet loss can occur in the Bluetooth transmission due to a variety of reasons, e.g. Wi-Fi interference or RF signal degradation due to distance or physical objects. As a result of these errors, the user hears glitches referred to as

pops

and substitution.

clicks

in the audio stream. The PLC block improves the receive path audio quality in the presence of bit and packet errors within the Bluetooth link by using a variety of techniques such as pitch-based waveform

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The PLC tries to re-synthesise the lost packet from the history buffer with the same pitch period. The PLC uses a highly efficient 3-phase pitch estimator and performs cross-fading at the concatenation boundaries, i.e. the PLC attempts to clean up the audio signal by removing the

pops

and

clicks

and smoothing out gaps. This improves the audio quality for the user and the improved signal enables proceding processing blocks to perform better.

The PLC significantly improves dealing with bit errors, using the BFI output from the firmware. The DSP calculates an average BER and selectively applies the PLC to the incoming data. This optimises audio quality for a variety of bit errors and packet loss conditions. The PLC is enabled in all modes.

Note:

The PLC is enabled in all modes, HFK (full processing), pass-through and loopback by default.

16.2.9 Adaptive Equalisation (AEQ)

The adaptive equalisation block improves the intelligibility of the receive path voice signal in the presence of near end noise by altering the spectral shape of the receive path signal while maintaining the overall power level. It has been empirically observed that consonants, which are dominantly high frequency based and much lower in amplitude than vowels, significantly contribute to the intelligibility of the voice signal. In the presence of noise, the lower amplitude consonants become masked by this noise. Therefore, by increasing the frequency components that contribute to the consonants while in the presence of noise, the intelligibility can be improved. In order to maintain a consistent amplitude level, the adaptive equalization block will adaptively increase the high frequencies relative to the middle frequencies and also reduce the low frequencies accordingly. The adaptive equalizer also has the capability to compensate for variations in voice transmission channels, which include farend devices and telecommunication channels.

The Frequency Emphasis feature can be used with any standard narrow band call, when the DAC is operating at a sample rate of 8kHz. To complement the AEQ, High Frequency Emphasis can be added to improve the intelligibility of the far end caller. The emphasis feature repairs frequencies (3469Hz to 4000Hz) that were lost due to the filters of the cellular network and Bluetooth link. Information contained in the original speech from 281Hz to 3469Hz is used to reconstruct the lost high frequency content.

The Frequency Expansion feature can be used with any standard narrow band call, but a special mode is invoked when the DAC operate at a sample rate of 16kHz. The frequency expansion allows users to add in frequencies far beyond the band limits caused by the cellular network and Bluetooth link. These expansion frequencies are added between

3469Hz and 6156Hz. As in frequency emphasis, it uses the information contained in the original speech from 281Hz to 3469Hz to reconstruct the lost high frequency content.

16.2.10 Auxiliary Stream Mix

The auxiliary stream mixer enables the system to seamlessly mix audio signals such as tones, beeps and voice prompts with the incoming SCO stream. This avoids any interruption to the SCO stream and as a result prevents any speech from being lost.

16.2.11 Clipper

The clipper block intentionally distorts or performance. This processing block can significantly improve the echo performance in cheap non-linear system designs.

clips

the receive signal prior to the reference input of the AEC in order to more accurately model the behaviour of the post reference input blocks such as the DAC, power amplifier and the loudspeaker. The AEC attempts to correlate the signal received at the reference input and the microphone input. Any non-linearities introduced that are not accounted for after the reference input will significantly degrade the AEC

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16.2.12 Noise Dependent Volume Control

The NDVC block improves the intelligibility of the receive path signal by increasing the analogue DAC gain value based on the send noise estimate from the send path noise suppression block. As the send noise estimate increases, the

NDVC algorithm increases the analogue DAC gain value. The NDVC uses hysteresis to minimise the artefacts generated by rapidly adjusting the DAC gain due to the fluctuation in the environmental noise.

16.2.13 Input Output Gains

Fixed gain controls are provided at the input to the CVC system. The mic gain is used set the ADC level so that proper levels can be set according to hardware constraints, industry standards and the digital resolution of the DSP fixed point processor. The speake gain represents the output DAC which drive the speaker. The DAC level varies under software control for events such as the Bluetooth volume, NDVC, tone mixing and other volume based activities.

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16.3 Music Enhancements

16.3.1 Audio Decoders

CSR8635 QFN supports:

A wide range of standard decoders:

SBC

MP3

■ AAC

Faststream codec:

Low-latency

No video/lip-sync issues while watching a video or playing games

Jitter handling and high quality sample rate matching

Low power consumption

16.3.2 Configurable EQ

The configurable equaliser on the CSR8635 QFN:

Each EQ filter contains up to 5 fully tuneable stages of cascaded 2 nd

order IIR filters per bank

Enables compensation for imperfections in loudspeaker performance and frequency adjustments to the received audio to enhance music brightness

Contains tiering for multiple customer presets, e.g. rock, pop, classical, jazz, dance etc.

Contains an easy to use GUI, with drag points, see Figure 16.4

Figure 16.4: Configurable EQ GUI with Drag Points

Is configurable with up to 6 switchable bank presets. This enables the device user to select between the EQ bank presets through button presses.

16.3.3 Stereo Widening (S3D)

The stereo widening feature on CSR8635 QFN:

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Is highly optimised at <1MIPS of the Kalimba DSP

Reduces listener fatigue for headphone listening

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16.3.4 Volume Boost

The volume boost feature on the CSR8635 QFN is a dynamic range compander and provides:

Additional loudness without clipping

Multi-stage compression and expansion

Processing modules for dynamic bass boost

Easy to use GUI, with drag points, see Figure 16.5

Figure 16.5: Volume Boost GUI with Drag Points

Louder audio output without distortion

16.4 CSR8635 Stereo ROM Solution Development Kit

CSR's audio development kit for the CSR8635 QFN, order code DK‑8635‑10163‑1A, includes a CSR8635 stereo ROM solution demonstrator board and necessary interface adapters and cables are available. In conjunction with the

CSR8600 ROM Series Configuration Tool and other supporting utilities the development kit provides the best environment for designing audio solutions with the CSR8635 QFN.

Important Note:

The CSR8635 Stereo ROM Solution audio development kit is subject to change and updates, for up-to-date information see www.csrsupport.com

.

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17 Tape and Reel Information

For tape and reel packing and labelling see

IC Packing and Labelling Specification

.

17.1 Tape Orientation

Figure 17.1 shows the CSR8635 QFN packing tape orientation.

Pin 1

User Direction of Feed

Figure 17.1: CSR8635 QFN Tape Orientation

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17.2 Tape Dimensions

4.0

See Note 1

0.25

2.0

See Note 6

0.30 ± 0.05

R0.3 MAX

R0.25

A

1.75

7.5

See Note 6

Bo

±

A

0

Section A-A

Ko

B

0

Ao

12.0

A

K

0

8.30

8.30

1.10

Unit mm

Notes

1. 10 sprocket hole pitch cumulative tolerance ±0.2

2. Camber not to exceed 1mm in 100mm

3. Material: PS + C

4. A

0

measured as indicated

5. K

0

0

and B

measured from a plane on the inside bottom of the pocket to the top surface of the carrier

6. Pocket position relative to sprocket hole measured as true position of pocket, not pocket hole

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17.3 Reel Information

ATTENTION

Electrostatic Sensitive Devices

Safe Handling Required

"A" a

(rim height)

102.0

2.0

330.0

2.0

"b" REF

88 REF

Detail "A"

20.2

MIN

2.0 0.5

13.0

6

PS

Detail "B"

6

PS

(MEASURED AT HUB)

(MEASURED AT HUB)

W1

W2

Figure 17.2: Reel Dimensions

Package Type

Nominal Hub Width

(Tape Width) a b W1 W2 Max

8 x 8 x 0.9mm

QFN

16

4.5

98.0

16.4

(3.0/-0.2)

19.1

17.4 Moisture Sensitivity Level

CSR8635 QFN is qualified to moisture sensitivity level MSL3 in accordance with JEDEC J-STD-020.

Units mm

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18 Document References

Document

BlueCore Audio API Specification

BlueTest User Guide

Bluetooth and USB Design Considerations

Core Specification of the Bluetooth System

CSR8635 QFN Performance Specification

Electrostatic Discharge (ESD) Sensitivity Testing,

Machine Model (MM)

CS-102736-UG

CS-101412-AN

Bluetooth Specification Version 4.0, 17 December 2009

CS-303738-SP

JESD22-A115C

ESDA/JEDEC Joint Standard For Electrostatic Discharge

Sensitivity Testing Human Body Model (HBM) -

Component Level

ANSI/ESDA/JEDEC JS-001-201

Field-Induced Charged-Device Model Test Method for

Electrostatic- Discharge-Withstand Thresholds of

Microelectronic Components

IC Packing and Labelling Specification

Reference, Date

CS-209064-DD

JESD22-C101E

CS-112584-SP

IEC 61000-4-2

Electromagnetic compatibility (EMC) – Part 4-2: Testing and measurement techniques – Electrostatic discharge immunity test

Kalimba Architecture 3 DSP User Guide

Lithium Polymer Battery Charger Calibration and

Operation for CSR8670

Moisture / Reflow Sensitivity Classification for

Nonhermitic Solid State Surface Mount Devices

IEC 61000-4-2, Edition 2.0, 2008-12

CS-202067-UG

CS-204572-AN

IPC / JEDEC J-STD-020

Optimising BlueCore5-Multimedia ADC Performance

Application Note

CS-120059-AN

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Selection of I²C EEPROMS for Use with BlueCore

bcore-an-008P

Typical Solder Reflow Profile for Lead-free Device

Universal Serial Bus Specification

CS-116434-AN v2.0, 27 April 2000

USB Battery Charging Specification

v1.2 December 7 th

March 15 th 2012

2010, also errata and ECNs through

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Terms and Definitions

Bluetooth ®

BMC

CNG codec

CRC

CSR

CTS

CVC

AG

AGC

ALU

AVRCP

BCCMD

BCSP

BEC

BER

BFI

BIST

BlueCore

®

AAC

AC

ACL

ADC

AEC

AFC

AFH

Term

8DPSK

π/4 DQPSK

µ-law

A-law

A2DP

Definition

8-phase Differential Phase Shift Keying

π/4 rotated Differential Quaternary Phase Shift Keying

Audio companding standard (G.711)

Audio companding standard (G.711)

Advanced Audio Distribution Profile

Advanced Audio Coding

Alternating Current

Asynchronous Connection-oriented

Analogue to Digital Converter

Acoustic Echo Cancellation

Automatic Frequency Control

Adaptive Frequency Hopping

Audio Gateway

Automatic Gain Control

Arithmetic Logic Unit

Audio/Video Remote Control Profile

BlueCore CoMmanD

BlueCore Serial Protocol

Bit Error Concealment

Bit Error Rate

Bad Frame Indicator

Built-In Self-Test

Group term for CSR’s range of Bluetooth wireless technology ICs

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Set of technologies providing audio and data transfer over short-range radio connections

Burst Mode Controller

Comfort Noise Generation

Coder decoder

Cyclic Redundancy Check

Cambridge Silicon Radio

Clear To Send

Clear Voice Capture

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GSM

GUI

H4DS

HBM

HCI etc

FIR

FSK

G.722

GCI

HFP

HSP

I²C

I²S i.e.

EMC

EQ eSCO

ESD

ESR

DUT e.g.

EDR

EEPROM

EIA

DDS

DI

DMA

DNL

DSP

Term

CVSD

DAC

DC

Definition

Continuously Variable Slope Delta Modulation

Digital to Analogue Converter

Direct Current

Direct Digital Synthesis

Device Id profile

Direct Memory Access

Differential Non Linearity (ADC accuracy parameter)

Digital Signal Processor (or Processing)

Device Under Test

exempli gratia

, for example

Enhanced Data Rate

Electrically Erasable Programmable Read Only Memory

Electronic Industries Alliance

ElectroMagnetic Compatibility

EQualiser extended SCO

Electrostatic Discharge

Equivalent Series Resistance

et cetera

, and the rest, and so forth

Finite Impulse Response (filter)

Frequency Shift Keying

An ITU-T standard wideband speech codec operating at 48, 56 and 64 kbps

General Circuit Interface

Global System for Mobile communications

H4 Deep Sleep

Human Body Model

Host Controller Interface

Hands-Free Profile

HeadSet Profile

Inter-Integrated Circuit Interface

Inter-Integrated Circuit Sound

Id est

, that is

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MMU

MP3 mSBC

N/A

NDVC

NSMD

PA

PC

PCB

LSB

MAC

Mb

MCU

MIPS

MISO

MLC

Kb

LC

LDO

LED

LM

LNA

IIR

INL

IPC

IPM

IQ

IC

IF

Term

I/O

ISDN

JEDEC

Kalimba

Definition

Input/Output

Integrated Circuit

Intermediate Frequency

Infinite Impulse Response (filter)

Integral Non-Linearity (ADC accuracy parameter)

See www.ipc.org

Intelligent Power Management

In-Phase and Quadrature

Integrated Services Digital Network

Joint Electron Device Engineering Council (now the JEDEC Solid State Technology Association)

An open platform DSP co-processor, enabling support of enhanced audio applications, such as echo and noise suppression and file compression / decompression

Kilobit

An inductor (L) and capacitor (C) network

Low (voltage) Drop-Out

Light-Emitting Diode

Link Manager

Low Noise Amplifier

Least Significant Bit (or Byte)

Multiplier and ACcumulator

Megabit

MicroController Unit

Million Instructions Per Second

Master In Slave Out

MultiLayer Ceramic

MPEG-1 audio layer 3 modified Sub-Band Coding

Not Applicable

Noise Dependent Volume Control

Non-Solder Mask Defined

Power Amplifier

Personal Computer

Printed Circuit Board

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SCO

SDA

SIG

SLC

SMPS

SNR

SPI

TBD

TCXO

THD+N

ROM

RSSI

RTS

RX

SBC

SCL

SCMS

Term

PCM

PIN

PIO

PIO

PLC plc

PS Key

PWM

QFN

RAM

RC

RF

RGB

RISC

RoHS

Definition

Pulse Code Modulation

Personal Identification Number

Parallel Input/Output

Programmable Input/Output, also known as general purpose I/O

Packet Loss Concealment public limited company

Persistent Store Key

Pulse Width Modulation

Quad-Flat No-lead

Random Access Memory

A Resistor and Capacitor network

Radio Frequency

Red Green Blue

Reduced Instruction Set Computer

Restriction of Hazardous Substances in Electrical and Electronic Equipment Directive (2002/95/

EC)

Read Only Memory

Received Signal Strength Indication

Request To Send

Receive or Receiver

Sub-Band Coding

Serial Clock Line

Serial Copy Management System (SCMS-T). A content protection scheme for secure transport and use of compressed digital music

Synchronous Connection-Oriented

(Bluetooth) Special Interest Group

Service Level Connection

Switch-Mode Power Supply

Signal-to-Noise Ratio

Serial Peripheral Interface

To Be Defined

Temperature Compensated crystal Oscillator

Total Harmonic Distortion and Noise

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Term

TX

UART

UI

USB

VCO

VM

VoIP

W-CDMA

Wi-Fi

®

WNR

Definition

Transmit or Transmitter

Universal Asynchronous Receiver Transmitter

User Interface

Universal Serial Bus

Voltage Controlled Oscillator

Virtual Machine

Voice over Internet Protocol

Wideband Code Division Multiple Access

Wireless Fidelity (IEEE 802.11 wireless networking)

Wind Noise Reduction

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