Memory Testing

Memory Testing
• Introduction
• Memory Architecture & Fault Models
• Test Algorithms
• DC / AC / Dynamic Tests
• Built-in Self Testing Schemes
• Built-in Self Repair Schemes
Memory testing.1
Memory Market Share in 1999
17
• DRAM: 8 X 10
• Flash:
• ROM:
6 X 10
16
2 X 10
16
15
• SRAM: 9 X 10
Memory testing.2
DRAM Price per Bit
1991: US$ 400 / Mega bits
1995: US$ 3.75 / Mega bits
1999: US$ 0.1~0.3 / Mega bits
Memory testing.3
Test Time as a Function of Memory Size
Cycle time: 10 ns
Size n
Testing time (in seconds)
n log2n
n3/2
64n
n2
16k
0.01
0.0023
0.021
64k
0.04
0.01
0.168
256k
0.17
0.047
1.34
1M
0.67
0.21
10.7
183 Mins
4M
2.68
0.92
85.9
49.2 Hrs
4.03
11.4 Mins
36.5 Days
91.6 Mins
584 Days
16M
10.8
64M
43.2
16.2
2.7
42
11.4 Mins
Memory testing.4
Architecture of a DRAM Chip
Address
Address latch
Column decoder
Refresh logic
Memory
cell
array
Write driver
Sense amplifiers
Data register
Row
decoder
Data
Control Signal
Data Data Read/write
out
in
Memory testing.5
Fault Models
1.
SAF
Stuck-At Fault
2.
TF
Transition Fault
3.
CF
Coupling Fault
4.
NPSF
Neighborhood Pattern Sensitive Fault
5.
AF
Address decoding fault
Memory testing.6
Stuck-At Fault
• The logic value of a cell or a line is always 0 or 1.
Transition Fault
• A cell or a line that fails to undergo a 0
transition.
1 or a 1
0
Coupling Fault
• A write operation to one cell changes the content of
a second cell.
Memory testing.7
Neighborhood Pattern Sensitive Fault
• The content of a cell, or the ability to change its
content, is influenced by the contents of some other
cells in the memory.
Address Decoder Fault (AF)
•
Any fault that affects address decoder:
•
With a certain address, no cell will be accessed.
•
A certain cell is never accessed.
•
With a certain address, multiple cells are accessed
simultaneously.
•
A certain cell can be accessed by multiple addresses.
Memory testing.8
Memory Chip Test Algorithms
•
Traditional tests
•
Tests for stuck-at, transition and coupling faults
•
Tests for neighborhood pattern sensitive faults
Memory testing.9
Traditional Tests
Algorithm
• Zero-One
• Checkerboard
• GALPAT
• Walking 1/0
• Sliding Diagonal
• Butterfly
Test length
Test Time Order
+ + + ⋅ + − ⋅ ⋅ • n is the number of bits of the memory array.
Memory testing.10
March Algorithms
Algorithm March X
Step1: write 0 with up addressing
order;
Step2: read 0 and write 1 with up
addressing order;
Step3: read 1 and write 0 with down
addressing order;
Step4: read 0 with down addressing
order.
Memory testing.11
Notation of March Algorithms
: address 0 to address n-1
: address n-1 to address 0
: either way
w0 : write 0
w1 : write 1
r0 : read a cell whose value should be 0
r1 : read a cell whose value should be 1
Memory testing.12
March Algorithms
EX:
MATS ( modified algorithmic Test Sequence)
(w0);
(r0,w1);
(r1);
s1: write 0 to all cells
s2: for each cell
read 0 ;
write 1;
s3: read 1 from all cells
Memory testing.13
Some March Algorithms
MATS :
(w0);
(r0,w1);
(r1)
MATS+:
(w0);
(r0,w1);
(r1,w0)
Marching 1/0 :
(w0); (r0,w1,r1);
(r1,w0,r0);
(w1);
(r1,w0,r0);
(r0, w1, r1);
MATS++ :
MARCH X :
MARCH C :
(w0);
(w0);
(w0);
(r0,w1);
(r0,w1);
(r0,w1);
(r0,w1);
(r1,w0,r0);
(r1,w0);
(r0)
(r1,w0);
(r0);
(r1,w0);
(r0);
Memory testing.14
Some March Algorithms (Cont.)
MARCH A :
(w0);
(r0,w1,w0,w1);
(r1,w0,w1);
(r1,w0,w1,w0);
(r0,w1,w0);
MARCH Y :
(w0);
MARCH B :
(w0);
(r0,w1,r1,w0,r0,w1);
(r1,w0,w1,w0);
(r0,w1,w0)
(r0,w1,r1);
(r1,w0,r0);
(r0)
(r1,w0,w1);
Memory testing.15
Tests for Stuck-At, Transition and
Coupling Faults
March alg.
Test len.
Fault coverage
MATS
4n
Some AFs, SAFs
MATS+
5n
AFs, SAFs
Marching 1/0
14n
AFs, SAFs, TFs
MATS++
6n
AFs, SAFs, TFs
March X
6n
AFs, SAFs, TFs, Some CFs
March C-
10n
AFs, SAFs, TFs, Some CFs
March A
15n
AFs, SAFs, TFs, Some CFs
March Y
8n
AFs, SAFs, TFs, Some CFs
March B
17n
AFs, SAFs, TFs, Some CFs
Memory testing.16
NPSF
n
n
n
n
b
n
n
n
n
b: base cell
n: neighbor cells
ANPSF:
PNPSF:
SNPSF:
Active Neighborhood
Passive Neighborhood
Static Neighborhood
Pattern Sensitive Fault
Pattern Sensitive Fault
Pattern Sensitive Fault
n changes
Contain n patterns
b changes
b cannot change
Ex:
Ex:
n: 0
b: 1
1
0
Contain n patterns
b is forced to a certain
value
Ex:
n: 00000000
b: 0 or 1
n: 11111111
b: 1
Memory testing.17
DC Parametric Testing
• Contains:
1. Open / Short test.
2. Power consumption test.
3. Leakage test.
4. Threshold test.
5. Output drive current test.
6. Output short current test.
Memory testing.18
AC Parametric Testing
• Output signal: - the rise & fall times.
• Relationship between input signals:
– the setup & hold times.
• Relationship between input and output signals:
– the delay & access times.
• Successive relationship between input and output
signals:
–
the speed test.
Memory testing.19
Dynamic Faults
•
Recovery faults:
−
Sense amplifier recovery
− Write recovery.
− Retention faults:
− Sleeping sickness
− Refresh line stuck-at
− Static data loss.
−
Bit-line precharge voltage imbalance faults.
Memory testing.20
BIST: Pros & Cons
•
Advantages:
– Minimal use of testers.
– Can be used for embedded RAMs.
•
Disadvantages:
– Silicon area overhead.
– Speed; slow access time.
– Extra pins or multiplexing pins.
– Testability of the test hardware itself.
– A high fault coverage is a challenge.
Memory testing.21
rst_l
clk
hold_l
test_h
di
addr Memory
wen
data
Module
compress_h clk
rst
si
se
Compressor
sys_addr
sys_d
isys_wen
Algorithm-Based
Pattern Generator
Typical Memory BIST Architecture
Using Mentor’s Architecture
q
so
BIST Circuitry
Memory testing.22
sys_addr1
sys_addr2
sys_di2
sys_wen2
sys_addr3
sys_di3
sys_wen3
rst_
l clk
Algorithm-Based
Pattern Generator
Multiple Memory BIST Architecture
hold_l
test_h
addr1
di2
addr2
wen2
di3
addr3
wen3
ROM4KX4
Module
4
data
RAM8KX8
Module
8
data
RAM8KX8
Module
data
8
compress_h
BIST
Circuitry
se
si
q
Compressor
so
Memory testing.23
Serial Testing of Embedded RAM
Go
Done
BIST mode
Control Block
Counters
Timing
Generator
BIST on
S0
S1
msb
Mission
mode
interface
{
Control
Data out
Data in
Address
Read/Write
Clock
1sb
c-1
Multiplexers
log W
2
Address
Multiplexers
c
Data In
Multiplexers
c
Data Out
2
Control
RAM
(w words c bits)
Memory testing.24
Built-in Self-Repair
•
BIST can only identify faulty chip.
•
Laser cut may be infeasible in some cases, e.g., field
testing.
•
Two types:
– Use fault-array comparator
! Repair by cell
! Repair by column (or row)
– Use switch array
Memory testing.25
BISR Using Switch Array
BISR module
Fault-Address
Buffers
Address
input
RAM
Decoder
Select
Switch Array
BIST module
RAM-Array
module
Data
Out
Data
input
Memory testing.26
BISR via Fault-Address Comparison
BISR module
Fault-Address
Buffers
Address
input
Fault-Address
Compare
BIST module
RAM
Decoder
RAM-Array
module
Data
Out
Data
input
Memory testing.27
Download PDF