ADSP-BF531/ADSP-BF532/ADSP-BF533 Embedded Processor

ADSP-BF531/ADSP-BF532/ADSP-BF533 Embedded Processor
Blackfin®
Embedded Processor
ADSP-BF531/ADSP-BF532/ADSP-BF533
FEATURES
External memory controller with glueless support for
SDRAM, SRAM, flash, and ROM
Flexible memory booting options from SPI® and
external memory
Up to 600 MHz high performance Blackfin processor
Two 16-bit MACs, two 40-bit ALUs, four 8-bit video ALUs,
40-bit shifter
RISC-like register and instruction model for ease of pro­
gramming and compiler-friendly support
Advanced debug, trace, and performance monitoring
0.85 V to 1.30 V core VDD with on-chip voltage regulation
1.8 V, 2.5 V, and 3.3 V compliant I/O
160-ball CSP_BGA, 169-ball PBGA, and 176-lead LQFP
packages
PERIPHERALS
Parallel peripheral interface PPI/GPIO, supporting
ITU-R 656 video data formats
Two dual-channel, full duplex synchronous serial ports, sup­
porting eight stereo I2S channels
Four memory-to-memory DMAs
Eight peripheral DMAs
SPI-compatible port
Three 32-bit timer/counters with PWM support
Real-time clock and watchdog timer
32-bit core timer
Up to 16 general-purpose I/O pins (GPIO)
UART with support for IrDA®
Event handler
Debug/JTAG interface
On-chip PLL capable of 0.5� to 64� frequency multiplication
MEMORY
Up to 148K bytes of on-chip memory:
16K bytes of instruction SRAM/Cache
Up to 64K bytes of instruction SRAM
Up to32K bytes of data SRAM/Cache
Up to32K bytes of data SRAM
4K bytes of scratchpad SRAM
Memory management unit providing memory protection
B
INTERRUPT
CONTROLLER
L1
DATA
MEMORY
DMA CORE BUS
EXTERNAL ACCESS BUS
DMA
EXTERNAL
BUS
EXTERNAL PORT
FLASH, SDRAM CONTROL
WATCHDOG
TIMER
RTC
PPI
DMA
CONTROLLER
DMA ACCESS BUS
L1
INSTRUCTION
MEMORY
PERIPHERAL ACCESS BUS
JTAG TEST AND EMULATION
VOLTAGE REGULATOR
TIMER0-2
GPIO
PORT
F
SPI
UART
SPORT0-1
16
BOOT ROM
Figure 1. Functional Block Diagram
Blackfin and the Blackfin logo are registered trademarks of Analog Devices, Inc.
Rev. E
Information furnished by Analog Devices is believed to be accurate and reliable.
However, no responsibility is assumed by Analog Devices for its use, nor for any
infringements of patents or other rights of third parties that may result from its use.
Specifications subject to change without notice. No license is granted by implication
or otherwise under any patent or patent rights of Analog Devices. Trademarks and
registered trademarks are the property of their respective owners.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106 U.S.A.
Tel: 781.329.4700
www.analog.com
Fax: 781.461.3113
©2007 Analog Devices, Inc. All rights reserved.
ADSP-BF531/ADSP-BF532/ADSP-BF533
TABLE OF CONTENTS
General Description ................................................. 3
Serial Peripheral Interface (SPI) Port
—Slave Timing ............................................. 38
Portable Low Power Architecture ............................. 3
Universal Asynchronous Receiver-Transmitter
(UART) Port—Receive and Transmit Timing ...... 39
System Integration ................................................ 3
ADSP-BF531/ADSP-BF532/ADSP-BF533 Processor Peripherals ....................................................... 3
General-Purpose I/O Port F Pin Cycle Timing ......... 40
Blackfin Processor Core .......................................... 4
Timer Cycle Timing .......................................... 41
Memory Architecture ............................................ 4
JTAG Test and Emulation Port Timing .................. 42
DMA Controllers .................................................. 8
Output Drive Currents ......................................... 43
Real-Time Clock ................................................... 8
Power Dissipation ............................................... 45
Watchdog Timer .................................................. 9
Test Conditions .................................................. 45
Timers ............................................................... 9
Environmental Conditions .................................... 48
Serial Ports (SPORTs) ............................................ 9
160-Ball BGA Ball Assignment .................................. 49
Serial Peripheral Interface (SPI) Port ....................... 10
169-Ball PBGA ball assignment .................................. 52
UART Port ........................................................ 10
176-Lead LQFP Pinout ............................................ 55
General-Purpose I/O Port F ................................... 10
Outline Dimensions ................................................ 57
Parallel Peripheral Interface ................................... 11
Surface Mount Design .......................................... 58
Dynamic Power Management ................................ 11
Ordering Guide ..................................................... 59
Voltage Regulation .............................................. 13
Clock Signals ..................................................... 13
Booting Modes ................................................... 14
REVISION HISTORY
Instruction Set Description ................................... 15
7/07—Revision E: Changed from Rev. D to Rev. E
Development Tools ............................................. 15
Designing an Emulator-Compatible Processor Board .. 16
Combined ADSP-BF531/532 Rev D and ADSP-BF533 Rev D Data sheets into this Revision E .................................. 1
Related Documents ............................................. 17
Changed Features .................................................... 1
Pin Descriptions .................................................... 18
Reformatted Processor Comparison ............................. 3
Specifications ........................................................ 21
Rewrote General-Purpose I/O Port F ........................... 10
Operating Conditions .......................................... 21
Rewrote Parallel Peripheral Interface ........................... 11
Electrical Characteristics ....................................... 22
Rewrote Dynamic Power Management ........................ 11
Absolute Maximum Ratings .................................. 23
Rewrote Voltage Regulation ...................................... 13
Package Information ........................................... 23
Rewrote Clock Signals ............................................. 13
ESD Sensitivity ................................................... 23
Rewrote Booting Modes ........................................... 14
Timing Specifications .......................................... 24
Rewrote EZ-KIT Lite Evaluation Board ........................ 16
Clock and Reset Timing .................................... 25
Reformatted Pin Descriptions .................................... 18
Asynchronous Memory Read Cycle Timing ........... 26
Changed Operating Conditions ................................. 21
Asynchronous Memory Write Cycle Timing .......... 27
Changed Electrical Characteristics .............................. 22
SDRAM Interface Timing .................................. 28
Reformatted Timing Specifications ............................. 24
External Port Bus Request and Grant Cycle Timing .. 29
Added Figures to Parallel Peripheral Interface Timing ..... 30
Parallel Peripheral Interface Timing ..................... 30
Changed Serial Ports ............................................... 34
Serial Ports ..................................................... 34
Changed Ordering Guide ......................................... 59
Serial Peripheral Interface (SPI) Port
—Master Timing .......................................... 37
8/06—Revision D: Changed from Rev. C to Rev. D
Rev. E |
Page 2 of 60 |
July 2007
ADSP-BF531/ADSP-BF532/ADSP-BF533
GENERAL DESCRIPTION
The ADSP-BF531/ADSP-BF532/ADSP-BF533 processors are
members of the Blackfin family of products, incorporating the
Analog Devices/Intel Micro Signal Architecture (MSA). Blackfin processors combine a dual-MAC state-of-the-art signal
processing engine, the advantages of a clean, orthogonal RISClike microprocessor instruction set, and single instruction, mul­
tiple data (SIMD) multimedia capabilities into a single
instruction set architecture.
The ADSP-BF531/ADSP-BF532/ADSP-BF533 processors are
completely code and pin-compatible, differing only with respect
to their performance and on-chip memory. Specific perfor­
mance and memory configurations are shown in Table 1.
ADSP-BF532
SPORTs
UART
SPI
GP Timers
Watchdog Timers
RTC
Parallel Peripheral Interface
GPIOs
L1 Instruction SRAM/Cache
L1 Instruction SRAM
L1 Data SRAM/Cache
L1 Data SRAM
L1 Scratchpad
L3 Boot ROM
2
1
1
3
1
1
1
16
16K bytes
16K bytes
16K bytes
2
1
1
3
1
1
1
16
16K bytes
32K bytes
32K bytes
Maximum Speed Grade
Package Options:
CSP_BGA
Plastic BGA
LQFP
400 MHz 400 MHz 600 MHz
Memory Configuration
Features
4K bytes
1K bytes
ADSP-BF533
ADSP-BF531
Table 1. Processor Comparison
SYSTEM INTEGRATION
The ADSP-BF531/ADSP-BF532/ADSP-BF533 processors are
highly integrated system-on-a-chip solutions for the next gener­
ation of digital communication and consumer multimedia
applications. By combining industry-standard interfaces with a
high performance signal processing core, users can develop
cost-effective solutions quickly without the need for costly
external components. The system peripherals include a UART
port, an SPI port, two serial ports (SPORTs), four general-pur­
pose timers (three with PWM capability), a real-time clock, a
watchdog timer, and a parallel peripheral interface.
ADSP-BF531/ADSP-BF532/ADSP-BF533
PROCESSOR PERIPHERALS
2
1
1
3
1
1
1
16
16K bytes
64K bytes
32K bytes
32K bytes
4K bytes 4K bytes
1K bytes 1K bytes
160-Ball 160-Ball 160-Ball
169-Ball 169-Ball 169-Ball
176-Lead 176-Lead 176-Lead
By integrating a rich set of industry-leading system peripherals
and memory, Blackfin processors are the platform of choice for
next generation applications that require RISC-like program­
mability, multimedia support, and leading-edge signal
processing in one integrated package.
PORTABLE LOW POWER ARCHITECTURE
Blackfin processors provide world-class power management
and performance. Blackfin processors are designed in a low
power and low voltage design methodology and feature
dynamic power management—the ability to vary both the volt­
age and frequency of operation to significantly lower overall
Rev. E |
power consumption. Varying the voltage and frequency can
result in a substantial reduction in power consumption, com­
pared with just varying the frequency of operation. This
translates into longer battery life for portable appliances.
The ADSP-BF531/ADSP-BF532/ADSP-BF533 processors con­
tain a rich set of peripherals connected to the core via several
high bandwidth buses, providing flexibility in system configura­
tion as well as excellent overall system performance (see the
functional block diagram in Figure 1 on Page 1). The generalpurpose peripherals include functions such as UART, timers
with PWM (pulse-width modulation) and pulse measurement
capability, general-purpose I/O pins, a real-time clock, and a
watchdog timer. This set of functions satisfies a wide variety of
typical system support needs and is augmented by the system
expansion capabilities of the part. In addition to these generalpurpose peripherals, the ADSP-BF531/ADSP-BF532/
ADSP-BF533 processors contain high speed serial and parallel
ports for interfacing to a variety of audio, video, and modem
codec functions; an interrupt controller for flexible manage­
ment of interrupts from the on-chip peripherals or external
sources; and power management control functions to tailor the
performance and power characteristics of the processor and sys­
tem to many application scenarios.
All of the peripherals, except for general-purpose I/O, real-time
clock, and timers, are supported by a flexible DMA structure.
There is also a separate memory DMA channel dedicated to
data transfers between the processor’s various memory spaces,
including external SDRAM and asynchronous memory. Multi­
ple on-chip buses running at up to 133 MHz provide enough
bandwidth to keep the processor core running along with activ­
ity on all of the on-chip and external peripherals.
The ADSP-BF531/ADSP-BF532/ADSP-BF533 processors
include an on-chip voltage regulator in support of the proces­
sor’s dynamic power management capability. The voltage
regulator provides a range of core voltage levels from a single
2.25 V to 3.6 V input. The voltage regulator can be bypassed at
the user’s discretion.
Page 3 of 60 |
July 2007
ADSP-BF531/ADSP-BF532/ADSP-BF533
BLACKFIN PROCESSOR CORE
As shown in Figure 2 on Page 5, the Blackfin processor core
contains two 16-bit multipliers, two 40-bit accumulators, two
40-bit ALUs, four video ALUs, and a 40-bit shifter. The compu­
tation units process 8-bit, 16-bit, or 32-bit data from the
register file.
The compute register file contains eight 32-bit registers. When
performing compute operations on 16-bit operand data, the
register file operates as 16 independent 16-bit registers. All
operands for compute operations come from the multiported
register file and instruction constant fields.
Each MAC can perform a 16-bit by 16-bit multiply in each
cycle, accumulating the results into the 40-bit accumulators.
Signed and unsigned formats, rounding, and saturation are
supported.
The ALUs perform a traditional set of arithmetic and logical
operations on 16-bit or 32-bit data. In addition, many special
instructions are included to accelerate various signal processing
tasks. These include bit operations such as field extract and
population count, modulo 232 multiply, divide primitives, satu­
ration and rounding, and sign/exponent detection. The set of
video instructions includes byte alignment and packing opera­
tions, 16-bit and 8-bit adds with clipping, 8-bit average
operations, and 8-bit subtract/absolute value/accumulate (SAA)
operations. Also provided are the compare/select and vector
search instructions.
For certain instructions, two 16-bit ALU operations can be per­
formed simultaneously on register pairs (a 16-bit high half and
16-bit low half of a compute register). Quad 16-bit operations
are possible using the second ALU.
The 40-bit shifter can perform shifts and rotates and is used to
support normalization, field extract, and field deposit
instructions.
The program sequencer controls the flow of instruction execu­
tion, including instruction alignment and decoding. For
program flow control, the sequencer supports PC relative and
indirect conditional jumps (with static branch prediction), and
subroutine calls. Hardware is provided to support zero-over­
head looping. The architecture is fully interlocked, meaning that
the programmer need not manage the pipeline when executing
instructions with data dependencies.
The address arithmetic unit provides two addresses for simulta­
neous dual fetches from memory. It contains a multiported
register file consisting of four sets of 32-bit index, modify,
length, and base registers (for circular buffering), and eight
additional 32-bit pointer registers (for C-style indexed stack
manipulation).
Blackfin processors support a modified Harvard architecture in
combination with a hierarchical memory structure. Level 1 (L1)
memories are those that typically operate at the full processor
speed with little or no latency. At the L1 level, the instruction
memory holds instructions only. The two data memories hold
data, and a dedicated scratchpad data memory stores stack and
local variable information.
Rev. E |
In addition, multiple L1 memory blocks are provided, offering a
configurable mix of SRAM and cache. The memory manage­
ment unit (MMU) provides memory protection for individual
tasks that may be operating on the core and can protect system
registers from unintended access.
The architecture provides three modes of operation: user mode,
supervisor mode, and emulation mode. User mode has
restricted access to certain system resources, thus providing a
protected software environment, while supervisor mode has
unrestricted access to the system and core resources.
The Blackfin processor instruction set has been optimized so
that 16-bit opcodes represent the most frequently used instruc­
tions, resulting in excellent compiled code density. Complex
DSP instructions are encoded into 32-bit opcodes, representing
fully featured multifunction instructions. Blackfin processors
support a limited multi-issue capability, where a 32-bit instruc­
tion can be issued in parallel with two 16-bit instructions,
allowing the programmer to use many of the core resources in a
single instruction cycle.
The Blackfin processor assembly language uses an algebraic syn­
tax for ease of coding and readability. The architecture has been
optimized for use in conjunction with the C/C++ compiler,
resulting in fast and efficient software implementations.
MEMORY ARCHITECTURE
The ADSP-BF531/ADSP-BF532/ADSP-BF533 processors view
memory as a single unified 4G byte address space, using 32-bit
addresses. All resources, including internal memory, external
memory, and I/O control registers, occupy separate sections of
this common address space. The memory portions of this
address space are arranged in a hierarchical structure to provide
a good cost/performance balance of some very fast, low latency
on-chip memory as cache or SRAM, and larger, lower cost and
performance off-chip memory systems. See Figure 4 on Page 6,
Figure 5 on Page 6, and Figure 3 on Page 6.
The L1 memory system is the primary highest performance
memory available to the Blackfin processor. The off-chip mem­
ory system, accessed through the external bus interface unit
(EBIU), provides expansion with SDRAM, flash memory, and
SRAM, optionally accessing up to 132M bytes of
physical memory.
The memory DMA controller provides high bandwidth datamovement capability. It can perform block transfers of code or
data between the internal memory and the external
memory spaces.
Internal (On-Chip) Memory
The ADSP-BF531/ADSP-BF532/ADSP-BF533 processor has
three blocks of on-chip memory providing high bandwidth
access to the core.
The first is the L1 instruction memory, consisting of up to
80K bytes SRAM, of which 16K bytes can be configured as a
four way set-associative cache. This memory is accessed at full
processor speed.
Page 4 of 60 |
July 2007
ADSP-BF531/ADSP-BF532/ADSP-BF533
ADDRESS ARITHMETIC UNIT
32
DA0
32
L3
B3
M3
I2
L2
B2
M2
I1
L1
B1
M1
I0
L0
B0
M0
SP
FP
P5
DAG1
P4
P3
DAG0
P2
P1
P0
TO MEMORY
DA1
I3
32
PREG
32
RAB
SD
LD1
LD0
32
32
32
ASTAT
32
32
SEQUENCER
R7.H
R6.H
R7.L
R6.L
R5.H
R5.L
R4.H
R4.L
R3.H
R3.L
R2.H
R2.L
R1.H
R1.L
R0.H
R0.L
16
ALIGN
16
8
8
8
8
DECODE
BARREL
SHIFTER
40
40
A0
32
40
40
A1
LOOP BUFFER
CONTROL
UNIT
32
DATA ARITHMETIC UNIT
Figure 2. Blackfin Processor Core
The second on-chip memory block is the L1 data memory, con­
sisting of one or two banks of up to 32K bytes. The memory
banks are configurable, offering both cache and SRAM func­
tionality. This memory block is accessed at full processor speed.
The third memory block is a 4K byte scratchpad SRAM which
runs at the same speed as the L1 memories, but is only accessible
as data SRAM and cannot be configured as cache memory.
External (Off-Chip) Memory
External memory is accessed via the external bus interface unit
(EBIU). This 16-bit interface provides a glueless connection to a
bank of synchronous DRAM (SDRAM) as well as up to four
banks of asynchronous memory devices including flash,
EPROM, ROM, SRAM, and memory mapped I/O devices.
The PC133-compliant SDRAM controller can be programmed
to interface to up to 128M bytes of SDRAM. The SDRAM con­
troller allows one row to be open for each internal SDRAM
bank, for up to four internal SDRAM banks, improving overall
system performance.
The asynchronous memory controller can be programmed to
control up to four banks of devices with very flexible timing
parameters for a wide variety of devices. Each bank occupies a
Rev. E |
1M byte segment regardless of the size of the devices used, so
that these banks will only be contiguous if each is fully popu­
lated with 1M byte of memory.
I/O Memory Space
Blackfin processors do not define a separate I/O space. All
resources are mapped through the flat 32-bit address space.
On-chip I/O devices have their control registers mapped into
memory mapped registers (MMRs) at addresses near the top of
the 4G byte address space. These are separated into two smaller
blocks, one containing the control MMRs for all core functions,
and the other containing the registers needed for setup and con­
trol of the on-chip peripherals outside of the core. The MMRs
are accessible only in supervisor mode and appear as reserved
space to on-chip peripherals.
Booting
The ADSP-BF531/ADSP-BF532/ADSP-BF533 processor con­
tains a small boot kernel, which configures the appropriate
peripheral for booting. If the ADSP-BF531/ADSP-BF532/
ADSP-BF533 processor is configured to boot from boot ROM
memory space, the processor starts executing from the on-chip
boot ROM. For more information, see Booting Modes on
Page 14.
Page 5 of 60 |
July 2007
ADSP-BF531/ADSP-BF532/ADSP-BF533
0xFFFF FFFF
0xFFFF FFFF
CORE MMR REGISTERS (2M BYTE)
CORE MMR REGISTERS (2M BYTE)
0xFFE0 0000
0xFFE0 0000
SYSTEM MMR REGISTERS (2M BYTE)
SYSTEM MMR REGISTERS (2M BYTE)
0xFFC0 0000
0xFFC0 0000
RESERVED
RESERVED
0xFFB0 1000
0xFFB0 1000
0xFFB0 0000
RESERVED
RESERVED
0xFFA1 4000
INTERNAL MEMORY MAP
0xFFA1 4000
INSTRUCTION SRAM/CACHE (16K BYTE)
0xFFA1 0000
RESERVED
0xFFA0 C000
INSTRUCTION SRAM (16K BYTE)
0xFFA0 8000
RESERVED
0xFFA0 0000
RESERVED
0xFF90 8000
RESERVED
INSTRUCTION SRAM/CACHE (16K BYTE)
0xFFA1 0000
INSTRUCTION SRAM (64K BYTE)
0xFFA0 0000
RESERVED
0xFF90 8000
DATA BANK B SRAM/CACHE (16K BYTE)
0xFF90 4000
DATA BANK B SRAM (16K BYTE)
INTERNAL MEMORY MAP
SCRATCHPAD SRAM (4K BYTE)
SCRATCHPAD SRAM (4K BYTE)
0xFFB0 0000
0xFF90 0000
RESERVED
0xFF90 4000
0xFF80 8000
DATA BANK A SRAM/CACHE (16K BYTE)
RESERVED
0xFF80 8000
0xFF80 4000
DATA BANK A SRAM (16K BYTE)
DATA BANK A SRAM/CACHE (16K BYTE)
0xFF80 4000
0xFF80 0000
RESERVED
RESERVED
RESERVED
EXTERNAL MEMORY MAP
RESERVED
0x2040 0000
ASYNC MEMORY BANK 3 (1M BYTE)
0x2030 0000
ASYNC MEMORY BANK 2 (1M BYTE)
0x2020 0000
ASYNC MEMORY BANK 1 (1M BYTE)
0x2010 0000
ASYNC MEMORY BANK 0 (1M BYTE)
0x2000 0000
RESERVED
0x0800 0000
0x2040 0000
ASYNC MEMORY BANK 3 (1M BYTE)
0x2030 0000
ASYNC MEMORY BANK 2 (1M BYTE)
0x2020 0000
ASYNC MEMORY BANK 1 (1M BYTE)
0x2010 0000
ASYNC MEMORY BANK 0 (1M BYTE)
0x2000 0000
RESERVED
0x0800 0000
EXTERNAL MEMORY MAP
0xEF00 0000
0xEF00 0000
SDRAM MEMORY (16M BYTE TO 128M BYTE)
SDRAM MEMORY (16M BYTE TO 128M BYTE)
0x0000 0000
0x0000 0000
Figure 3. ADSP-BF531 Internal/External Memory Map
Figure 5. ADSP-BF533 Internal/External Memory Map
Event Handling
0xFFFF FFFF
CORE MMR REGISTERS (2M BYTE)
0xFFE0 0000
SYSTEM MMR REGISTERS (2M BYTE)
0xFFC0 0000
RESERVED
0xFFB0 1000
SCRATCHPAD SRAM (4K BYTE)
INTERNAL MEMORY MAP
0xFFB0 0000
RESERVED
0xFFA1 4000
INSTRUCTION SRAM/CACHE (16K BYTE)
0xFFA1 0000
INSTRUCTION SRAM (32K BYTE)
0xFFA0 8000
RESERVED
0xFFA0 0000
RESERVED
0xFF90 8000
DATA BANK B SRAM/CACHE (16K BYTE)
The event controller on the ADSP-BF531/ADSP-BF532/
ADSP-BF533 processor handles all asynchronous and synchro­
nous events to the processor. The ADSP-BF531/ADSP-BF532/
ADSP-BF533 processor provides event handling that supports
both nesting and prioritization. Nesting allows multiple event
service routines to be active simultaneously. Prioritization
ensures that servicing of a higher priority event takes prece­
dence over servicing of a lower priority event. The controller
provides support for five different types of events:
• Emulation – An emulation event causes the processor to
enter emulation mode, allowing command and control of
the processor via the JTAG interface.
0xFF90 4000
RESERVED
• Reset – This event resets the processor.
0xFF80 8000
DATA BANK A SRAM/CACHE (16K BYTE)
• Nonmaskable Interrupt (NMI) – The NMI event can be
generated by the software watchdog timer or by the NMI
input signal to the processor. The NMI event is frequently
used as a power-down indicator to initiate an orderly shut­
down of the system.
0xFF80 4000
RESERVED
0xEF00 0000
EXTERNAL MEMORY MAP
RESERVED
0x2040 0000
ASYNC MEMORY BANK 3 (1M BYTE)
0x2030 0000
ASYNC MEMORY BANK 2 (1M BYTE)
0x2020 0000
ASYNC MEMORY BANK 1 (1M BYTE)
0x2010 0000
ASYNC MEMORY BANK 0 (1M BYTE)
0x2000 0000
RESERVED
0x0800 0000
• Exceptions – Events that occur synchronously to program
flow (i.e., the exception will be taken before the instruction
is allowed to complete). Conditions such as data alignment
violations and undefined instructions cause exceptions.
• Interrupts – Events that occur asynchronously to program
flow. They are caused by input pins, timers, and other
peripherals, as well as by an explicit software instruction.
SDRAM MEMORY (16M BYTE TO 128M BYTE)
0x0000 0000
Figure 4. ADSP-BF532 Internal/External Memory Map
Rev. E |
Page 6 of 60 |
July 2007
ADSP-BF531/ADSP-BF532/ADSP-BF533
Each event type has an associated register to hold the return
address and an associated return-from-event instruction. When
an event is triggered, the state of the processor is saved on the
supervisor stack.
The ADSP-BF531/ADSP-BF532/ADSP-BF533 processor event
controller consists of two stages, the core event controller (CEC)
and the system interrupt controller (SIC). The core event con­
troller works with the system interrupt controller to prioritize
and control all system events. Conceptually, interrupts from the
peripherals enter into the SIC, and are then routed directly into
the general-purpose interrupts of the CEC.
Core Event Controller (CEC)
The CEC supports nine general-purpose interrupts (IVG15–7),
in addition to the dedicated interrupt and exception events. Of
these general-purpose interrupts, the two lowest priority inter­
rupts (IVG15–14) are recommended to be reserved for software
interrupt handlers, leaving seven prioritized interrupt inputs to
support the peripherals of the processor. Table 2 describes the
inputs to the CEC, identifies their names in the event vector
table (EVT), and lists their priorities.
Table 2. Core Event Controller (CEC)
Priority
(0 is Highest)
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
Event Class
Emulation/Test Control
Reset
Nonmaskable Interrupt
Exception
Reserved
Hardware Error
Core Timer
General Interrupt 7
General Interrupt 8
General Interrupt 9
General Interrupt 10
General Interrupt 11
General Interrupt 12
General Interrupt 13
General Interrupt 14
General Interrupt 15
EVT Entry
EMU
RST
NMI
EVX
IVHW
IVTMR
IVG7
IVG8
IVG9
IVG10
IVG11
IVG12
IVG13
IVG14
IVG15
Table 3. System Interrupt Controller (SIC)
Peripheral Interrupt Event
PLL Wakeup
DMA Error
PPI Error
SPORT 0 Error
SPORT 1 Error
SPI Error
UART Error
Real-Time Clock
DMA Channel 0 (PPI)
DMA Channel 1 (SPORT 0 Receive)
DMA Channel 2 (SPORT 0 Transmit)
DMA Channel 3 (SPORT 1 Receive)
DMA Channel 4 (SPORT 1 Transmit)
DMA Channel 5 (SPI)
DMA Channel 6 (UART Receive)
DMA Channel 7 (UART Transmit)
Timer 0
Timer 1
Timer 2
Port F GPIO Interrupt A
Port F GPIO Interrupt B
Memory DMA Stream 0
Memory DMA Stream 1
Software Watchdog Timer
Default Mapping
IVG7
IVG7
IVG7
IVG7
IVG7
IVG7
IVG7
IVG8
IVG8
IVG9
IVG9
IVG9
IVG9
IVG10
IVG10
IVG10
IVG11
IVG11
IVG11
IVG12
IVG12
IVG13
IVG13
IVG13
Event Control
The ADSP-BF531/ADSP-BF532/ADSP-BF533 processor pro­
vides the user with a very flexible mechanism to control the
processing of events. In the CEC, three registers are used to
coordinate and control events. Each register is 32 bits wide:
• CEC interrupt latch register (ILAT) – The ILAT register
indicates when events have been latched. The appropriate
bit is set when the processor has latched the event and
cleared when the event has been accepted into the system.
This register is updated automatically by the controller, but
it may also be written to clear (cancel) latched events. This
register may be read while in supervisor mode and may
only be written while in supervisor mode when the corre­
sponding IMASK bit is cleared.
System Interrupt Controller (SIC)
The system interrupt controller provides the mapping and rout­
ing of events from the many peripheral interrupt sources to the
prioritized general-purpose interrupt inputs of the CEC.
Although the ADSP-BF531/ADSP-BF532/ADSP-BF533 proces­
sor provides a default mapping, the user can alter the mappings
and priorities of interrupt events by writing the appropriate val­
ues into the interrupt assignment registers (SIC_IARx). Table 3
describes the inputs into the SIC and the default mappings into
the CEC.
Rev. E |
Page 7 of 60 |
• CEC interrupt mask register (IMASK) – The IMASK regis­
ter controls the masking and unmasking of individual
events. When a bit is set in the IMASK register, that event is
unmasked and will be processed by the CEC when asserted.
A cleared bit in the IMASK register masks the event,
preventing the processor from servicing the event even
though the event may be latched in the ILAT register. This
register may be read or written while in supervisor mode.
July 2007
ADSP-BF531/ADSP-BF532/ADSP-BF533
Note that general-purpose interrupts can be globally
enabled and disabled with the STI and CLI instructions,
respectively.
• CEC interrupt pending register (IPEND) – The IPEND
register keeps track of all nested events. A set bit in the
IPEND register indicates the event is currently active or
nested at some level. This register is updated automatically
by the controller but may be read while in supervisor mode.
The SIC allows further control of event processing by providing
three 32-bit interrupt control and status registers. Each register
contains a bit corresponding to each of the peripheral interrupt
events shown in Table 3.
• SIC interrupt mask register (SIC_IMASK) – This register
controls the masking and unmasking of each peripheral
interrupt event. When a bit is set in this register, that
peripheral event is unmasked and will be processed by the
system when asserted. A cleared bit in this register masks
the peripheral event, preventing the processor from servic­
ing the event.
and the asynchronous memory controller. DMA-capable
peripherals include the SPORTs, SPI port, UART, and PPI. Each
individual DMA-capable peripheral has at least one dedicated
DMA channel.
The ADSP-BF531/ADSP-BF532/ADSP-BF533 processor DMA
controller supports both 1-dimensional (1-D) and 2-dimen­
sional (2-D) DMA transfers. DMA transfer initialization can be
implemented from registers or from sets of parameters called
descriptor blocks.
The 2-D DMA capability supports arbitrary row and column
sizes up to 64K elements by 64K elements, and arbitrary row
and column step sizes up to ±32K elements. Furthermore, the
column step size can be less than the row step size, allowing
implementation of interleaved data streams. This feature is
especially useful in video applications where data can be
de-interleaved on the fly.
Examples of DMA types supported by the ADSP-BF531/
ADSP-BF532/ADSP-BF533 processor DMA controller include:
• A single, linear buffer that stops upon completion
• SIC interrupt status register (SIC_ISR) – As multiple
peripherals can be mapped to a single event, this register
allows the software to determine which peripheral event
source triggered the interrupt. A set bit indicates the
peripheral is asserting the interrupt, and a cleared bit indi­
cates the peripheral is not asserting the event.
• A circular, autorefreshing buffer that interrupts on each
full or fractionally full buffer
• SIC interrupt wakeup enable register (SIC_IWR) – By
enabling the corresponding bit in this register, a peripheral
can be configured to wake up the processor, should the
core be idled when the event is generated. See Dynamic
Power Management on Page 11.
In addition to the dedicated peripheral DMA channels, there are
two pairs of memory DMA channels provided for transfers
between the various memories of the ADSP-BF531/
ADSP-BF532/ADSP-BF533 processor system. This enables
transfers of blocks of data between any of the memories—
including external SDRAM, ROM, SRAM, and flash memory—
with minimal processor intervention. Memory DMA transfers
can be controlled by a very flexible descriptor-based methodol­
ogy or by a standard register-based autobuffer mechanism.
Because multiple interrupt sources can map to a single generalpurpose interrupt, multiple pulse assertions can occur simulta­
neously, before or during interrupt processing for an interrupt
event already detected on this interrupt input. The IPEND reg­
ister contents are monitored by the SIC as the interrupt
acknowledgement.
The appropriate ILAT register bit is set when an interrupt rising
edge is detected (detection requires two core clock cycles). The
bit is cleared when the respective IPEND register bit is set. The
IPEND bit indicates that the event has entered into the proces­
sor pipeline. At this point the CEC will recognize and queue the
next rising edge event on the corresponding event input. The
minimum latency from the rising edge transition of the generalpurpose interrupt to the IPEND output asserted is three core
clock cycles; however, the latency can be much higher, depend­
ing on the activity within and the state of the processor.
DMA CONTROLLERS
The ADSP-BF531/ADSP-BF532/ADSP-BF533 processor has
multiple, independent DMA channels that support automated
data transfers with minimal overhead for the processor core.
DMA transfers can occur between the processor’s internal
memories and any of its DMA-capable peripherals. Addition­
ally, DMA transfers can be accomplished between any of the
DMA-capable peripherals and external devices connected to the
external memory interfaces, including the SDRAM controller
Rev. E |
• 1-D or 2-D DMA using a linked list of descriptors
• 2-D DMA using an array of descriptors, specifying only the
base DMA address within a common page
REAL-TIME CLOCK
The processor real-time clock (RTC) provides a robust set of
digital watch features, including current time, stopwatch, and
alarm. The RTC is clocked by a 32.768 kHz crystal external to
the ADSP-BF531/ADSP-BF532/ADSP-BF533 processor. The
RTC peripheral has dedicated power supply pins so that it can
remain powered up and clocked even when the rest of the pro­
cessor is in a low power state. The RTC provides several
programmable interrupt options, including interrupt per sec­
ond, minute, hour, or day clock ticks, interrupt on
programmable stopwatch countdown, or interrupt at a pro­
grammed alarm time.
The 32.768 kHz input clock frequency is divided down to a 1 Hz
signal by a prescaler. The counter function of the timer consists
of four counters: a 60 second counter, a 60 minute counter, a 24
hour counter, and a 32,768 day counter.
When enabled, the alarm function generates an interrupt when
the output of the timer matches the programmed value in the
alarm control register. There are two alarms: The first alarm is
for a time of day. The second alarm is for a day and time of
that day.
Page 8 of 60 |
July 2007
ADSP-BF531/ADSP-BF532/ADSP-BF533
The stopwatch function counts down from a programmed
value, with one second resolution. When the stopwatch is
enabled and the counter underflows, an interrupt is generated.
Like other peripherals, the RTC can wake up the processor from
sleep mode upon generation of any RTC wakeup event.
Additionally, an RTC wakeup event can wake up the processor
from deep sleep mode, and wake up the on-chip internal voltage
regulator from a powered-down state.
Connect RTC pins RTXI and RTXO with external components
as shown in Figure 6.
RTXI
RTXO
The timer units can be used in conjunction with the UART to
measure the width of the pulses in the data stream to provide an
autobaud detect function for a serial channel.
The timers can generate interrupts to the processor core provid­
ing periodic events for synchronization, either to the system
clock or to a count of external signals.
In addition to the three general-purpose programmable timers,
a fourth timer is also provided. This extra timer is clocked by the
internal processor clock and is typically used as a system tick
clock for generation of operating system periodic interrupts.
R1
X1
C1
clock the timer, or as a mechanism for measuring pulse widths
and periods of external events. These timers can be synchro­
nized to an external clock input to the PF1 pin (TACLK), an
external clock input to the PPI_CLK pin (TMRCLK), or to the
internal SCLK.
SERIAL PORTS (SPORTs)
C2
The ADSP-BF531/ADSP-BF532/ADSP-BF533 processor incor­
porates two dual-channel synchronous serial ports (SPORT0
and SPORT1) for serial and multiprocessor communications.
The SPORTs support the following features:
SUGGESTED COMPONENTS:
X1 = ECL IPTEK EC38J (THROUGH-HOLE PACKAGE) OR
EPSON MC405 12 pF LOAD (SURFACE-MOUNT PACKAGE)
C1 = 22pF
C2 = 22pF
R1 = 10MΩ
NOTE: C1 AND C2 ARE SPECIFIC TO CRYSTAL SPECIFIED FOR X1.
CONTACT CRYSTAL MANUFACTURER FOR DETAILS. C1 AND C2
SPECI FICATIO NS ASSUME BOARD TRACE CAPACITANCE OF 3pF.
• I2S capable operation.
• Bidirectional operation – Each SPORT has two sets of inde­
pendent transmit and receive pins, enabling eight channels
of I2S stereo audio.
• Buffered (8-deep) transmit and receive ports – Each port
has a data register for transferring data words to and from
other processor components and shift registers for shifting
data in and out of the data registers.
Figure 6. External Components for RTC
WATCHDOG TIMER
The ADSP-BF531/ADSP-BF532/ADSP-BF533 processor
includes a 32-bit timer that can be used to implement a software
watchdog function. A software watchdog can improve system
availability by forcing the processor to a known state through
generation of a hardware reset, nonmaskable interrupt (NMI),
or general-purpose interrupt, if the timer expires before being
reset by software. The programmer initializes the count value of
the timer, enables the appropriate interrupt, then enables the
timer. Thereafter, the software must reload the counter before it
counts to zero from the programmed value. This protects the
system from remaining in an unknown state where software,
which would normally reset the timer, has stopped running due
to an external noise condition or software error.
If configured to generate a hardware reset, the watchdog timer
resets both the core and the processor peripherals. After a reset,
software can determine if the watchdog was the source of the
hardware reset by interrogating a status bit in the watchdog
timer control register.
The timer is clocked by the system clock (SCLK), at a maximum
frequency of fSCLK.
TIMERS
• Clocking – Each transmit and receive port can either use an
external serial clock or generate its own, in frequencies
ranging from (fSCLK/131,070) Hz to (fSCLK/2) Hz.
• Word length – Each SPORT supports serial data words
from 3 bits to 32 bits in length, transferred most-signifi­
cant-bit first or least-significant-bit first.
• Framing – Each transmit and receive port can run with or
without frame sync signals for each data word. Frame sync
signals can be generated internally or externally, active high
or low, and with either of two pulse widths and early or late
frame sync.
• Companding in hardware – Each SPORT can perform
A-law or μ-law companding according to ITU recommen­
dation G.711. Companding can be selected on the transmit
and/or receive channel of the SPORT without additional
latencies.
• DMA operations with single-cycle overhead – Each SPORT
can automatically receive and transmit multiple buffers of
memory data. The processor can link or chain sequences of
DMA transfers between a SPORT and memory.
There are four general-purpose programmable timer units in
the ADSP-BF531/ADSP-BF532/ADSP-BF533 processor. Three
timers have an external pin that can be configured either as a
pulse-width modulator (PWM) or timer output, as an input to
Rev. E |
Page 9 of 60 |
July 2007
ADSP-BF531/ADSP-BF532/ADSP-BF533
data to and from memory. The UART has two dedicated
DMA channels, one for transmit and one for receive. These
DMA channels have lower default priority than most DMA
channels because of their relatively low service rates.
• Interrupts – Each transmit and receive port generates an
interrupt upon completing the transfer of a data-word or
after transferring an entire data buffer or buffers
through DMA.
• Multichannel capability – Each SPORT supports 128 chan­
nels out of a 1,024-channel window and is compatible with
the H.100, H.110, MVIP-90, and HMVIP standards.
The baud rate, serial data format, error code generation and sta­
tus, and interrupts for the UART port are programmable.
The UART programmable features include:
An additional 250 mV of SPORT input hysteresis can be
enabled by setting Bit 15 of the PLL_CTL register. When this bit
is set, all SPORT input pins have the increased hysteresis.
• Supporting bit rates ranging from (fSCLK/1,048,576) bits per
second to (fSCLK/16) bits per second.
• Supporting data formats from seven bits to 12 bits per frame.
SERIAL PERIPHERAL INTERFACE (SPI) PORT
The ADSP-BF531/ADSP-BF532/ADSP-BF533 processor has an
SPI-compatible port that enables the processor to communicate
with multiple SPI-compatible devices.
The SPI interface uses three pins for transferring data: two data
pins (master output-slave input, MOSI, and master input-slave
output, MISO) and a clock pin (serial clock, SCK). An SPI chip
select input pin (SPISS) lets other SPI devices select the proces­
sor, and seven SPI chip select output pins (SPISEL7–1) let the
processor select other SPI devices. The SPI select pins are reconfigured general-purpose I/O pins. Using these pins, the SPI port
provides a full-duplex, synchronous serial interface which sup­
ports both master/slave modes and multimaster environments.
The baud rate and clock phase/polarities for the SPI port are
programmable, and it has an integrated DMA controller, con­
figurable to support transmit or receive data streams. The SPI
DMA controller can only service unidirectional accesses at any
given time.
The SPI port clock rate is calculated as:
f SCLK
SPI Clock Rate = ----------------------------------2 × SPI_BAUD
Where the 16-bit SPI_BAUD register contains a value of 2 to
65,535.
• Both transmit and receive operations can be configured to
generate maskable interrupts to the processor.
The UART port’s clock rate is calculated as:
f SCLK
UART Clock Rate = ---------------------------------------------16 × UART_Divisor
Where the 16-bit UART_Divisor comes from the UART_DLH
register (most significant 8 bits) and UART_DLL register (least
significant 8 bits).
In conjunction with the general-purpose timer functions,
autobaud detection is supported.
The capabilities of the UART are further extended with support
for the Infrared Data Association (IrDA) serial infrared physical
layer link specification (SIR) protocol.
GENERAL-PURPOSE I/O PORT F
The ADSP-BF531/ADSP-BF532/ADSP-BF533 processor has 16
bidirectional, general-purpose I/O pins on Port F (PF15–0).
Each general-purpose I/O pin can be individually controlled by
manipulation of the GPIO control, status and interrupt
registers:
• GPIO direction control register – Specifies the direction of
each individual PFx pin as input or output.
During transfers, the SPI port simultaneously transmits and
receives by serially shifting data in and out on its two serial data
lines. The serial clock line synchronizes the shifting and sam­
pling of data on the two serial data lines.
UART PORT
The ADSP-BF531/ADSP-BF532/ADSP-BF533 processor pro­
vides a full-duplex universal asynchronous receiver/transmitter
(UART) port, which is fully compatible with PC-standard
UARTs. The UART port provides a simplified UART interface
to other peripherals or hosts, supporting full-duplex, DMA-sup­
ported, asynchronous transfers of serial data. The UART port
includes support for 5 data bits to 8 data bits, 1 stop bit or 2 stop
bits, and none, even, or odd parity. The UART port supports
two modes of operation:
• PIO (programmed I/O) – The processor sends or receives
data by writing or reading I/O-mapped UART registers.
The data is double-buffered on both transmit and receive.
• DMA (direct memory access) – The DMA controller trans­
fers both transmit and receive data. This reduces the
number and frequency of interrupts required to transfer
Rev. E |
Page 10 of 60 |
• GPIO control and status registers – The ADSP-BF531/
ADSP-BF532/ADSP-BF533 processor employs a “write one
to modify” mechanism that allows any combination of
individual GPIO pins to be modified in a single instruction,
without affecting the level of any other GPIO pins. Four
control registers are provided. One register is written in
order to set GPIO pin values, one register is written in
order to clear GPIO pin values, one register is written in
order to toggle GPIO pin values, and one register is written
in order to specify GPIO pin values. Reading the GPIO sta­
tus register allows software to interrogate the sense of the
GPIO pin.
• GPIO interrupt mask registers – The two GPIO interrupt
mask registers allow each individual PFx pin to function as
an interrupt to the processor. Similar to the two GPIO con­
trol registers that are used to set and clear individual GPIO
pin values, one GPIO interrupt mask register sets bits to
enable interrupt function, and the other GPIO interrupt
mask register clears bits to disable interrupt function. PFx
July 2007
ADSP-BF531/ADSP-BF532/ADSP-BF533
pins defined as inputs can be configured to generate hard­
ware interrupts, while output PFx pins can be triggered by
software interrupts.
• GPIO interrupt sensitivity registers – The two GPIO inter­
rupt sensitivity registers specify whether individual PFx
pins are level- or edge-sensitive and specify—if edge-sensi­
tive—whether just the rising edge or both the rising and
falling edges of the signal are significant. One register
selects the type of sensitivity, and one register selects which
edges are significant for edge-sensitivity.
PARALLEL PERIPHERAL INTERFACE
The processor provides a parallel peripheral interface (PPI) that
can connect directly to parallel A/D and D/A converters, video
encoders and decoders, and other general-purpose peripherals.
The PPI consists of a dedicated input clock pin, up to three
frame synchronization pins, and up to 16 data pins. The input
clock supports parallel data rates up to half the system clock rate
and the synchronization signals can be configured as either
inputs or outputs.
The PPI supports a variety of general-purpose and ITU-R 656
modes of operation. In general-purpose mode, the PPI provides
half-duplex, bi-directional data transfer with up to 16 bits of
data. Up to three frame synchronization signals are also pro­
vided. In ITU-R 656 mode, the PPI provides half-duplex bi­
directional transfer of 8- or 10-bit video data. Additionally, onchip decode of embedded start-of-line (SOL) and start-of-field
(SOF) preamble packets is supported.
General-Purpose Mode Descriptions
The general-purpose modes of the PPI are intended to suit a
wide variety of data capture and transmission applications.
Three distinct submodes are supported:
• Input mode – Frame syncs and data are inputs into the PPI.
• Frame capture mode – Frame syncs are outputs from the
PPI, but data are inputs.
• Output mode – Frame syncs and data are outputs from the
PPI.
Input Mode
Input mode is intended for ADC applications, as well as video
communication with hardware signaling. In its simplest form,
PPI_FS1 is an external frame sync input that controls when to
read data. The PPI_DELAY MMR allows for a delay (in
PPI_CLK cycles) between reception of this frame sync and the
initiation of data reads. The number of input data samples is
user programmable and defined by the contents of the
PPI_COUNT register. The PPI supports 8-bit and 10-bit
through 16-bit data, programmable in the PPI_CONTROL
register.
Rev. E |
Frame Capture Mode
Frame capture mode allows the video source(s) to act as a slave
(e.g., for frame capture). The ADSP-BF531/ADSP-BF532/
ADSP-BF533 processors control when to read from the video
source(s). PPI_FS1 is an HSYNC output and PPI_FS2 is a
VSYNC output.
Output Mode
Output mode is used for transmitting video or other data with
up to three output frame syncs. Typically, a single frame sync is
appropriate for data converter applications, whereas two or
three frame syncs could be used for sending video with hard­
ware signaling.
ITU-R 656 Mode Descriptions
The ITU-R 656 modes of the PPI are intended to suit a wide
variety of video capture, processing, and transmission applica­
tions. Three distinct submodes are supported:
• Active video only mode
• Vertical blanking only mode
• Entire field mode
Active Video Only Mode
Active video only mode is used when only the active video por­
tion of a field is of interest and not any of the blanking intervals.
The PPI does not read in any data between the end of active
video (EAV) and start of active video (SAV) preamble symbols,
or any data present during the vertical blanking intervals. In this
mode, the control byte sequences are not stored to memory;
they are filtered by the PPI. After synchronizing to the start of
Field 1, the PPI ignores incoming samples until it sees an SAV
code. The user specifies the number of active video lines per
frame (in PPI_COUNT register).
Vertical Blanking Interval Mode
In this mode, the PPI only transfers vertical blanking interval
(VBI) data.
Entire Field Mode
In this mode, the entire incoming bit stream is read in through
the PPI. This includes active video, control preamble sequences,
and ancillary data that may be embedded in horizontal and ver­
tical blanking intervals. Data transfer starts immediately after
synchronization to Field 1. Data is transferred to or from the
synchronous channels through eight DMA engines that work
autonomously from the processor core.
DYNAMIC POWER MANAGEMENT
The ADSP-BF531/ADSP-BF532/ADSP-BF533 processor pro­
vides four operating modes, each with a different performance/
power profile. In addition, dynamic power management pro­
vides the control functions to dynamically alter the processor
core supply voltage, further reducing power dissipation. Control
of clocking to each of the processor peripherals also reduces
power consumption. See Table 4 for a summary of the power
settings for each mode.
Page 11 of 60 |
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ADSP-BF531/ADSP-BF532/ADSP-BF533
Full-On Operating Mode—Maximum Performance
In the full-on mode, the PLL is enabled and is not bypassed,
providing capability for maximum operational frequency. This
is the power-up default execution state in which maximum per­
formance can be achieved. The processor core and all enabled
peripherals run at full speed.
Active Operating Mode—Moderate Power Savings
In the active mode, the PLL is enabled but bypassed. Because the
PLL is bypassed, the processor’s core clock (CCLK) and system
clock (SCLK) run at the input clock (CLKIN) frequency. In this
mode, the CLKIN to CCLK multiplier ratio can be changed,
although the changes are not realized until the full-on mode is
entered. DMA access is available to appropriately configured L1
memories.
In the active mode, it is possible to disable the PLL through the
PLL control register (PLL_CTL). If disabled, the PLL must be
re-enabled before transitioning to the full-on or sleep modes.
Table 4. Power Settings
PLL
Mode
PLL
Bypassed
Full-On
Enabled No
Active
Enabled/ Yes
Disabled
Sleep
Enabled
Deep Sleep Disabled
Hibernate Disabled
Core
Clock
(CCLK)
Enabled
Enabled
System
Clock
Core
(SCLK)
Power
Enabled On
Enabled On
Disabled Enabled On
Disabled Disabled On
Disabled Disabled Off
Sleep Operating Mode—High Dynamic Power Savings
Hibernate State—Maximum Static Power Savings
The hibernate state maximizes static power savings by disabling
the voltage and clocks to the processor core (CCLK) and to all
the synchronous peripherals (SCLK). The internal voltage regu­
lator for the processor can be shut off by writing b#00 to
the FREQ bits of the VR_CTL register. In addition to disabling
the clocks, this sets the internal power supply voltage (VDDINT) to
0 V to provide the lowest static power dissipation. Any critical
information stored internally (memory contents, register con­
tents, etc.) must be written to a nonvolatile storage device prior
to removing power if the processor state is to be preserved.
Since VDDEXT is still supplied in this mode, all of the external pins
three-state, unless otherwise specified. This allows other devices
that may be connected to the processor to still have power
applied without drawing unwanted current. The internal supply
regulator can be woken up either by a real-time clock wakeup or
by asserting the RESET pin.
Power Savings
As shown in Table 5, the ADSP-BF531/ADSP-BF532/
ADSP-BF533 processor supports three different power
domains. The use of multiple power domains maximizes flexi­
bility, while maintaining compliance with industry standards
and conventions. By isolating the internal logic of the processor
into its own power domain, separate from the RTC and other
I/O, the processor can take advantage of dynamic power man­
agement without affecting the RTC or other I/O devices. There
are no sequencing requirements for the various power domains.
Table 5. Power Domains
The sleep mode reduces dynamic power dissipation by disabling
the clock to the processor core (CCLK). The PLL and system
clock (SCLK), however, continue to operate in this mode. Typi­
cally an external event or RTC activity will wake up the
processor. When in the sleep mode, assertion of wakeup will
cause the processor to sense the value of the BYPASS bit in the
PLL control register (PLL_CTL). If BYPASS is disabled, the pro­
cessor will transition to the full-on mode. If BYPASS is enabled,
the processor will transition to the active mode.
When in the sleep mode, system DMA access to L1 memory is
not supported.
Deep Sleep Operating Mode—Maximum Dynamic Power
Savings
The deep sleep mode maximizes dynamic power savings by dis­
abling the clocks to the processor core (CCLK) and to all
synchronous peripherals (SCLK). Asynchronous peripherals,
such as the RTC, may still be running but will not be able to
access internal resources or external memory. This powereddown mode can only be exited by assertion of the reset interrupt
(RESET) or by an asynchronous interrupt generated by the
RTC. When in deep sleep mode, an RTC asynchronous
Rev. E |
interrupt causes the processor to transition to the active mode.
Assertion of RESET while in deep sleep mode causes the proces­
sor to transition to the full-on mode.
Power Domain
All internal logic, except RTC
RTC internal logic and crystal I/O
All other I/O
VDD Range
VDDINT
VDDRTC
VDDEXT
The power dissipated by a processor is largely a function of the
clock frequency of the processor and the square of the operating
voltage. For example, reducing the clock frequency by 25%
results in a 25% reduction in dynamic power dissipation, while
reducing the voltage by 25% reduces dynamic power dissipation
by more than 40%. Further, these power savings are additive, in
that if the clock frequency and supply voltage are both reduced,
the power savings can be dramatic.
The dynamic power management feature of the ADSP-BF531/
ADSP-BF532/ADSP-BF533 processor allows both the proces­
sor’s input voltage (VDDINT) and clock frequency (fCCLK) to be
dynamically controlled.
The savings in power dissipation can be modeled using the
power savings factor and % power savings calculations.
Page 12 of 60 |
July 2007
ADSP-BF531/ADSP-BF532/ADSP-BF533
The power savings factor is calculated as:
Voltage Regulator Layout Guidelines
power savings factor
Regulator external component placement, board routing, and
bypass capacitors all have a significant effect on noise injected
into the other analog circuits on-chip. The VROUT1-0 traces
and voltage regulator external components should be consid­
ered as noise sources when doing board layout and should not
be routed or placed near sensitive circuits or components on the
board. All internal and I/O power supplies should be well
bypassed with bypass capacitors placed as close to the
ADSP-BF531/ADSP-BF532/ADSP-BF533 processors as
possible.
f CCLKRED ⎛ V DDINTRED ⎞ 2 ⎛ t RED ⎞
- × -------------------------- × ----------= -------------------f CCLKNOM ⎝ V DDINTNOM⎠ ⎝ t NOM ⎠
where the variables in the equation are:
fCCLKNOM is the nominal core clock frequency
fCCLKRED is the reduced core clock frequency
VDDINTNOM is the nominal internal supply voltage
VDDINTRED is the reduced internal supply voltage
For further details on the on-chip voltage regulator and related
board design guidelines, see the Switching Regulator Design
Considerations for ADSP-BF533 Blackfin Processors (EE-228)
applications note on the Analog Devices web site (www.ana­
log.com)—use site search on “EE-228”.
tNOM is the duration running at fCCLKNOM
tRED is the duration running at fCCLKRED
The percent power savings is calculated as:
% power savings = (1 – power savings factor) × 100%
CLOCK SIGNALS
VOLTAGE REGULATION
The Blackfin processor provides an on-chip voltage regulator
that can generate appropriate VDDINT voltage levels from the
VDDEXT supply. See Operating Conditions on Page 21 for regula­
tor tolerances and acceptable VDDEXT ranges for specific models.
Figure 7 shows the typical external components required to
complete the power management system. The regulator con­
trols the internal logic voltage levels and is programmable with
the voltage regulator control register (VR_CTL) in increments
of 50 mV. To reduce standby power consumption, the internal
voltage regulator can be programmed to remove power to the
processor core while keeping I/O power (VDDEXT) supplied. While
in the hibernate state, I/O power is still being applied, eliminat­
ing the need for external buffers. The voltage regulator can be
activated from this power-down state either through an RTC
wakeup or by asserting RESET, both of which will then initiate a
boot sequence. The regulator can also be disabled and bypassed
at the user’s discretion.
The ADSP-BF531/ADSP-BF532/ADSP-BF533 processor can be
clocked by an external crystal, a sine wave input, or a buffered,
shaped clock derived from an external clock oscillator.
If an external clock is used, it should be a TTL compatible signal
and must not be halted, changed, or operated below the speci­
fied frequency during normal operation. This signal is
connected to the processor’s CLKIN pin. When an external
clock is used, the XTAL pin must be left unconnected.
Alternatively, because the ADSP-BF531/ADSP-BF532/
ADSP-BF533 processor includes an on-chip oscillator circuit,
an external crystal may be used. For fundamental frequency
operation, use the circuit shown in Figure 8.
Blackfin
CLKOUT
TO PLL CIRCUITRY
EN
2.25V TO 3.6V
INPUT VOLTAGE
RANGE
VDDEXT
(LOW-INDUCTANCE)
SET OF DECOUPLING CAPACITORS
+
CLKIN
VDDEXT
XTAL
FOR OVERTONE
OPERATION ONLY:
100µF
10µH
100nF
+
+
18pF*
VDDINT
18pF*
100µF
FDS9431A
10µF
LOW ESR
NOTE: VALUES MARKED WITH * MUST BE CUSTOMIZED
DEPENDING ON THE CRYSTAL AND LAYOUT. PLEASE
ANALYZE CAREFULLY.
100µF
ZHCS1000
VROUT
SHORT AND LOWINDUCTANCE WIRE
NOTE: DESIGNER SHOULD MINIMIZE
TRACE LENGTH TO FDS9431A.
VROUT
GND
Figure 7. Voltage Regulator Circuit
Rev. E |
Figure 8. External Crystal Connections
A parallel-resonant, fundamental frequency, microprocessorgrade crystal is connected across the CLKIN and XTAL pins.
The on-chip resistance between CLKIN and the XTAL pin is in
the 500 kΩ range. Further parallel resistors are typically not rec­
ommended. The two capacitors and the series resistor shown in
Figure 8 fine tune the phase and amplitude of the sine
Page 13 of 60 |
July 2007
ADSP-BF531/ADSP-BF532/ADSP-BF533
frequency. The capacitor and resistor values shown in Figure 8
are typical values only. The capacitor values are dependent upon
the crystal manufacturer's load capacitance recommendations
and the physical PCB layout. The resistor value depends on the
drive level specified by the crystal manufacturer. System designs
should verify the customized values based on careful investiga­
tion on multiple devices over the allowed temperature range.
A third-overtone crystal can be used at frequencies above
25 MHz. The circuit is then modified to ensure crystal operation
only at the third overtone, by adding a tuned inductor circuit as
shown in Figure 8.
As shown in Figure 9, the core clock (CCLK) and system
peripheral clock (SCLK) are derived from the input clock
(CLKIN) signal. An on-chip PLL is capable of multiplying the
CLKIN signal by a user programmable 0.5× to 64× multiplica­
tion factor (bounded by specified minimum and maximum
VCO frequencies). The default multiplier is 10×, but it can be
modified by a software instruction sequence. On-the-fly
frequency changes can be effected by simply writing to the
PLL_DIV register.
“FI NE” ADJUSTMENT
REQUI RES PLL SEQ UENCING
CLKIN
The core clock (CCLK) frequency can also be dynamically
changed by means of the CSEL1–0 bits of the PLL_DIV register.
Supported CCLK divider ratios are 1, 2, 4, and 8, as shown in
Table 7. This programmable core clock capability is useful for
fast core frequency modifications.
Table 7. Core Clock Ratios
Signal Name
CSEL1–0
00
01
10
11
CCLK
Example Frequency Ratios
(MHz)
VCO
CCLK
300
300
300
150
400
100
200
25
BOOTING MODES
Table 8. Booting Modes
VCO
÷ 1 to 15
SCLK
BMODE1–0
00
SCLK ≤ CCLK
SCLK ≤ 133 MHz
01
10
11
Figure 9. Frequency Modification Methods
All on-chip peripherals are clocked by the system clock (SCLK).
The system clock frequency is programmable by means of the
SSEL3–0 bits of the PLL_DIV register. The values programmed
into the SSEL fields define a divide ratio between the PLL output
(VCO) and the system clock. SCLK divider values are 1 through
15. Table 6 illustrates typical system clock ratios.
• Execute from 16-bit external memory – Execution starts
from address 0x2000 0000 with 16-bit packing. The boot
ROM is bypassed in this mode. All configuration settings
are set for the slowest device possible (3-cycle hold time;
15-cycle R/W access times; 4-cycle setup).
Example Frequency Ratios
Divider Ratio (MHz)
VCO/SCLK
VCO
SCLK
1:1
100
100
3:1
400
133
10:1
500
50
• Boot from 8-bit or 16-bit external flash memory – The flash
boot routine located in boot ROM memory space is set up
using asynchronous Memory Bank 0. All configuration set­
tings are set for the slowest device possible (3-cycle hold
time; 15-cycle R/W access times; 4-cycle setup).
The maximum frequency of the system clock is fSCLK. The divisor
ratio must be chosen to limit the system clock frequency to its
maximum of fSCLK. The SSEL value can be changed dynamically
without any PLL lock latencies by writing the appropriate values
Rev. E |
Description
Execute from 16-bit external memory (bypass
boot ROM)
Boot from 8-bit or 16-bit FLASH
Boot from serial master connected to SPI
Boot from serial slave EEPROM /flash (8-,16-,
or 24-bit address range, or Atmel AT45DB041,
AT45DB081, or AT45DB161serial flash)
The BMODE pins of the reset configuration register, sampled
during power-on resets and software-initiated resets, imple­
ment the following modes:
Table 6. Example System Clock Ratios
Signal Name
SSEL3–0
0001
0011
1010
Divider Ratio
VCO/CCLK
1:1
2:1
4:1
8:1
The ADSP-BF531/ADSP-BF532/ADSP-BF533 processor has
two mechanisms (listed in Table 8) for automatically loading
internal L1 instruction memory after a reset. A third mode is
provided to execute from external memory, bypassing the boot
sequence.
“CO ARSE” ADJUSTMENT
ON-THE-FLY
÷ 1, 2, 4, 8
PLL
0.5× to 64×
to the PLL divisor register (PLL_DIV). When the SSEL value is
changed, it will affect all the peripherals that derive their clock
signals from the SCLK signal.
Page 14 of 60 |
• Boot from SPI serial EEPROM/flash (8-, 16-, or 24-bit
addressable, or Atmel AT45DB041, AT45DB081, or
AT45DB161) – The SPI uses the PF2 output pin to select a
single SPI EEPROM/flash device, submits a read command
and successive address bytes (0x00) until a valid 8-, 16-, or
July 2007
ADSP-BF531/ADSP-BF532/ADSP-BF533
24-bit addressable EEPROM/flash device is detected, and
begins clocking data into the processor at the beginning of
L1 instruction memory.
• Boot from SPI serial master – The Blackfin processor oper­
ates in SPI slave mode and is configured to receive the bytes
of the LDR file from an SPI host (master) agent. To hold off
the host device from transmitting while the boot ROM is
busy, the Blackfin processor asserts a GPIO pin, called host
wait (HWAIT), to signal the host device not to send any
more bytes until the flag is deasserted. The GPIO pin is
chosen by the user and this information is transferred to
the Blackfin processor via bits[10:5] of the FLAG header in
the LDR image.
For each of the boot modes, a 10-byte header is first read from
an external memory device. The header specifies the number of
bytes to be transferred and the memory destination address.
Multiple memory blocks may be loaded by any boot sequence.
Once all blocks are loaded, program execution commences from
the start of L1 instruction SRAM.
In addition, Bit 4 of the reset configuration register can be set by
application code to bypass the normal boot sequence during a
software reset. For this case, the processor jumps directly to the
beginning of L1 instruction memory.
INSTRUCTION SET DESCRIPTION
The Blackfin processor family assembly language instruction set
employs an algebraic syntax designed for ease of coding and
readability. The instructions have been specifically tuned to pro­
vide a flexible, densely encoded instruction set that compiles to
a very small final memory size. The instruction set also provides
fully featured multifunction instructions that allow the pro­
grammer to use many of the processor core resources in a single
instruction. Coupled with many features more often seen on
microcontrollers, this instruction set is very efficient when com­
piling C and C++ source code. In addition, the architecture
supports both user (algorithm/application code) and supervisor
(O/S kernel, device drivers, debuggers, ISRs) modes of opera­
tion, allowing multiple levels of access to core processor
resources.
The assembly language, which takes advantage of the proces­
sor’s unique architecture, offers the following advantages:
• Seamlessly integrated DSP/CPU features are optimized for
both 8-bit and 16-bit operations.
• A multi-issue load/store modified Harvard architecture,
which supports two 16-bit MAC or four 8-bit ALU + two
load/store + two pointer updates per cycle.
• Microcontroller features, such as arbitrary bit and bit-field
manipulation, insertion, and extraction; integer operations
on 8-, 16-, and 32-bit data types; and separate user and
supervisor stack pointers.
• Code density enhancements, which include intermixing of
16-bit and 32-bit instructions (no mode switching, no code
segregation). Frequently used instructions are encoded in
16 bits.
DEVELOPMENT TOOLS
The ADSP-BF531/ADSP-BF532/ADSP-BF533 processor is sup­
ported by a complete set of CROSSCORE®† software and
hardware development tools, including Analog Devices emula­
tors and VisualDSP++®‡ development environment. The same
emulator hardware that supports other Blackfin processors also
fully emulates the ADSP-BF531/ADSP-BF532/ADSP-BF533
processor.
The VisualDSP++ project management environment lets pro­
grammers develop and debug an application. This environment
includes an easy to use assembler (which is based on an alge­
braic syntax), an archiver (librarian/library builder), a linker, a
loader, a cycle-accurate instruction level simulator, a C/C++
compiler, and a C/C++ runtime library that includes DSP and
mathematical functions. A key point for these tools is C/C++
code efficiency. The compiler has been developed for efficient
translation of C/C++ code to processor assembly. The processor
has architectural features that improve the efficiency of com­
piled C/C++ code.
The VisualDSP++ debugger has a number of important fea­
tures. Data visualization is enhanced by a plotting package that
offers a significant level of flexibility. This graphical representa­
tion of user data enables the programmer to quickly determine
the performance of an algorithm. As algorithms grow in com­
plexity, this capability can have increasing significance on the
designer’s development schedule, increasing productivity.
Statistical profiling enables the programmer to nonintrusively
poll the processor as it is running the program. This feature,
unique to VisualDSP++, enables the software developer to pas­
sively gather important code execution metrics without
interrupting the real-time characteristics of the program. Essen­
tially, the developer can identify bottlenecks in software quickly
and efficiently. By using the profiler, the programmer can focus
on those areas in the program that impact performance and take
corrective action.
Debugging both C/C++ and assembly programs with the
VisualDSP++ debugger, programmers can:
• View mixed C/C++ and assembly code (interleaved source
and object information).
• All registers, I/O, and memory are mapped into a unified
4G byte memory space, providing a simplified program­
ming model.
• Insert breakpoints.
• Set conditional breakpoints on registers, memory, and stacks.
†
‡
Rev. E |
CROSSCORE is a registered trademark of Analog Devices, Inc.
VisualDSP++ is a registered trademark of Analog Devices, Inc.
Page 15 of 60 |
July 2007
ADSP-BF531/ADSP-BF532/ADSP-BF533
• Trace instruction execution.
• Perform linear or statistical profiling of program execution.
• Fill, dump, and graphically plot the contents of memory.
Hardware tools include Blackfin processor PC plug-in cards.
Third party software tools include DSP libraries, real-time oper­
ating systems, and block diagram design tools.
EZ-KIT Lite Evaluation Board
• Perform source level debugging.
• Create custom debugger windows.
The VisualDSP++ IDDE lets programmers define and manage
software development. Its dialog boxes and property pages let
programmers configure and manage all of the Blackfin develop­
ment tools, including the color syntax highlighting in the
VisualDSP++ editor. This capability permits programmers to:
• Control how the development tools process inputs and
generate outputs
• Maintain a one-to-one correspondence with the tool’s command line switches
The VisualDSP++ Kernel (VDK) incorporates scheduling and
resource management tailored specifically to address the mem­
ory and timing constraints of DSP programming. These
capabilities enable engineers to develop code more effectively,
eliminating the need to start from the very beginning, when
developing new application code. The VDK features include
threads, critical and unscheduled regions, semaphores, events,
and device flags. The VDK also supports priority-based, pre­
emptive, cooperative, and time-sliced scheduling approaches. In
addition, the VDK was designed to be scalable. If the application
does not use a specific feature, the support code for that feature
is excluded from the target system.
Because the VDK is a library, a developer can decide whether to
use it or not. The VDK is integrated into the VisualDSP++
development environment, but can also be used via standard
command line tools. When the VDK is used, the development
environment assists the developer with many error prone tasks
and assists in managing system resources, automating the gen­
eration of various VDK-based objects, and visualizing the
system state, when debugging an application that uses the VDK.
Use the expert linker to visually manipulate the placement of
code and data on the embedded system. View memory utiliza­
tion in a color coded graphical form, easily move code and data
to different areas of the processor or external memory with the
drag of the mouse, and examine runtime stack and heap usage.
The expert linker is fully compatible with existing linker defini­
tion file (LDF), allowing the developer to move between the
graphical and textual environments.
Analog Devices emulators use the IEEE 1149.1 JTAG test access
port of the ADSP-BF531/ADSP-BF532/ADSP-BF533 processor
to monitor and control the target board processor during emu­
lation. The emulator provides full speed emulation, allowing
inspection and modification of memory, registers, and proces­
sor stacks. Nonintrusive in-circuit emulation is assured by the
use of the processor’s JTAG interface—the emulator does not
affect target system loading or timing.
Analog Devices offers a range of EZ-KIT Lite® evaluation plat­
forms to use as a cost effective method to learn more about
developing or prototyping applications with Analog Devices
processors, platforms, and software tools. Each EZ-KIT Lite
includes an evaluation board along with an evaluation suite of
the VisualDSP++ development and debugging environment
with the C/C++ compiler, assembler, and linker. Also included
are sample application programs, power supply, and a USB
cable. All evaluation versions of the software tools are limited
for use only with the EZ-KIT Lite product.
The USB controller on the EZ-KIT Lite board connects the
board to the USB port of the user’s PC, enabling the Visu­
alDSP++ evaluation suite to emulate the on-board processor incircuit. This permits the customer to download, execute, and
debug programs for the EZ-KIT Lite system. It also allows incircuit programming of the on-board flash device to store userspecific boot code, enabling the board to run as a standalone
unit without being connected to the PC.
With a full version of VisualDSP++ installed (sold separately),
engineers can develop software for the EZ-KIT Lite or any cus­
tom defined system. Connecting one of Analog Devices JTAG
emulators to the EZ-KIT Lite board enables high speed, nonintrusive emulation.
For evaluation of ADSP-BF531/ADSP-BF532/ADSP-BF533
processors, use the EZ-KIT Lite board available from Analog
Devices. Order part number ADDS-BF533-EZLITE. The board
comes with on-chip emulation capabilities and is equipped to
enable software development. Multiple daughter cards are
available.
DESIGNING AN EMULATOR-COMPATIBLE
PROCESSOR BOARD
The Analog Devices family of emulators are tools that every sys­
tem developer needs to test and debug hardware and software
systems. Analog Devices has supplied an IEEE 1149.1 JTAG test
access port (TAP) on each JTAG processor. The emulator uses
the TAP to access the internal features of the processor, allow­
ing the developer to load code, set breakpoints, observe
variables, observe memory, and examine registers. The proces­
sor must be halted to send data and commands, but once an
operation has been completed by the emulator, the processor
system is set running at full speed with no impact on
system timing.
To use these emulators, the target board must include a header
that connects the processor’s JTAG port to the emulator.
In addition to the software and hardware development tools
available from Analog Devices, third parties provide a wide
range of tools supporting the Blackfin processor family.
Rev. E |
Page 16 of 60 |
July 2007
ADSP-BF531/ADSP-BF532/ADSP-BF533
For details on target board design issues including mechanical
layout, single processor connections, multiprocessor scan
chains, signal buffering, signal termination, and emulator pod
logic, see the Analog Devices JTAG Emulation Technical Refer­
ence (EE-68) on the Analog Devices website
(www.analog.com)—use site search on “EE-68.” This document
is updated regularly to keep pace with improvements to emula­
tor support.
RELATED DOCUMENTS
The following publications that describe the ADSP-BF531/
ADSP-BF532/ADSP-BF533 processors (and related processors)
can be ordered from any Analog Devices sales office or accessed
electronically on our website:
• Getting Started With Blackfin Processors
• ADSP-BF533 Blackfin Processor Hardware Reference
• ADSP-BF53x/BF56x Blackfin Processor Programming
Reference
• ADSP-BF531 Blackfin Processor Anomaly List
• ADSP-BF532 Blackfin Processor Anomaly List
• ADSP-BF533 Blackfin Processor Anomaly List
Rev. E |
Page 17 of 60 |
July 2007
ADSP-BF531/ADSP-BF532/ADSP-BF533
PIN DESCRIPTIONS
ADSP-BF531/ADSP-BF532/ADSP-BF533 processor pin defini­
tions are listed in Table 9.
All pins are three-stated during and immediately after reset,
except the memory interface, asynchronous memory control,
and synchronous memory control pins, which are driven high.
If BR is active, then the memory pins are also three-stated. All
unused I/O pins have their input buffers disabled with the
exception of the pins that need pull-ups or pull-downs as noted
in the table footnotes.
In order to maintain maximum functionality and reduce pack­
age size and pin count, some pins have dual, multiplexed
functionality. In cases where pin functionality is reconfigurable,
the default state is shown in plain text, while alternate function­
ality is shown in italics.
Table 9. Pin Descriptions
Type Function
Driver
Type1
ADDR19–1
O
Address Bus for Async/Sync Access
A
DATA15–0
I/O
Data Bus for Async/Sync Access
A
ABE1–0/SDQM1–0
O
Byte Enables/Data Masks for Async/Sync Access
A
Pin Name
Memory Interface
BR
I
Bus Request (This pin should be pulled HIGH if not used.)
BG
O
Bus Grant
A
BGH
O
Bus Grant Hang
A
AMS3–0
O
Bank Select
A
ARDY
I
Hardware Ready Control (This pin should be pulled HIGH if not used.)
AOE
O
Output Enable
A
ARE
O
Read Enable
A
AWE
O
Write Enable
A
SRAS
O
Row Address Strobe
A
SCAS
O
Column Address Strobe
A
SWE
O
Write Enable
A
SCKE
O
Clock Enable
A
CLKOUT
O
Clock Output
B
SA10
O
A10 Pin
A
SMS
O
Bank Select
A
TMR0
I/O
Timer 0
C
TMR1/PPI_FS1
I/O
Timer 1/PPI Frame Sync1
C
TMR2/PPI_FS2
I/O
Timer 2/PPI Frame Sync2
C
PPI3–0
I/O
PPI3–0
C
PPI_CLK/TMRCLK
I
PPI Clock/External Timer Reference
Asynchronous Memory Control
Synchronous Memory Control
Timers
PPI Port
Rev. E |
Page 18 of 60 |
July 2007
ADSP-BF531/ADSP-BF532/ADSP-BF533
Table 9. Pin Descriptions (Continued)
Type Function
Driver
Type1
PF0/SPISS
I/O
GPIO/SPI Slave Select Input
C
PF1/SPISEL1/TACLK
I/O
GPIO/SPI Slave Select Enable 1/Timer Alternate Clock Input
C
PF2/SPISEL2
I/O
GPIO/SPI Slave Select Enable 2
C
PF3/SPISEL3/PPI_FS3
I/O
GPIO/SPI Slave Select Enable 3/PPI Frame Sync 3
C
PF4/SPISEL4/PPI15
I/O
GPIO/SPI Slave Select Enable 4/PPI 15
C
PF5/SPISEL5/PPI14
I/O
GPIO/SPI Slave Select Enable 5/PPI 14
C
PF6/SPISEL6/PPI13
I/O
GPIO/SPI Slave Select Enable 6/PPI 13
C
PF7/SPISEL7/PPI12
I/O
GPIO/SPI Slave Select Enable 7/PPI 12
C
PF8/PPI11
I/O
GPIO/PPI 11
C
PF9/PPI10
I/O
GPIO/PPI 10
C
PF10/PPI9
I/O
GPIO/PPI 9
C
PF11/PPI8
I/O
GPIO/PPI 8
C
PF12/PPI7
I/O
GPIO/PPI 7
C
PF13/PPI6
I/O
GPIO/PPI 6
C
PF14/PPI5
I/O
GPIO/PPI 5
C
PF15/PPI4
I/O
GPIO/PPI 4
C
TCK
I
JTAG Clock
TDO
O
JTAG Serial Data Out
TDI
I
JTAG Serial Data In
Pin Name
Port F: GPIO/Parallel Peripheral
Interface Port/SPI/Timers
JTAG Port
C
TMS
I
JTAG Mode Select
TRST
I
JTAG Reset (This pin should be pulled LOW if JTAG is not used.)
EMU
O
Emulation Output
C
MOSI
I/O
Master Out Slave In
C
MISO
I/O
Master In Slave Out (This pin should be pulled HIGH through a 4.7 kΩ resistor if booting via the C
SPI port.)
SCK
I/O
SPI Clock
D
I/O
SPORT0 Receive Serial Clock
D
C
SPI Port
Serial Ports
RSCLK0
RFS0
I/O
SPORT0 Receive Frame Sync
DR0PRI
I
SPORT0 Receive Data Primary
DR0SEC
I
SPORT0 Receive Data Secondary
TSCLK0
I/O
SPORT0 Transmit Serial Clock
D
TFS0
I/O
SPORT0 Transmit Frame Sync
C
DT0PRI
O
SPORT0 Transmit Data Primary
C
DT0SEC
O
SPORT0 Transmit Data Secondary
C
RSCLK1
I/O
SPORT1 Receive Serial Clock
D
Rev. E |
Page 19 of 60 |
July 2007
ADSP-BF531/ADSP-BF532/ADSP-BF533
Table 9. Pin Descriptions (Continued)
Pin Name
RFS1
Type Function
Driver
Type1
I/O
C
SPORT1 Receive Frame Sync
DR1PRI
I
SPORT1 Receive Data Primary
DR1SEC
I
SPORT1 Receive Data Secondary
TSCLK1
I/O
SPORT1 Transmit Serial Clock
D
TFS1
I/O
SPORT1 Transmit Frame Sync
C
DT1PRI
O
SPORT1 Transmit Data Primary
C
DT1SEC
O
SPORT1 Transmit Data Secondary
C
RX
I
UART Receive
TX
O
UART Transmit
RTXI
I
RTC Crystal Input (This pin should be pulled LOW when not used.)
RTXO
O
RTC Crystal Output
CLKIN
I
Clock/Crystal Input (This pin needs to be at a level or clocking.)
XTAL
O
Crystal Output
UART Port
C
Real-Time Clock
Clock
Mode Controls
RESET
I
Reset (This pin is always active during core power-on.)
NMI
I
Nonmaskable Interrupt (This pin should be pulled LOW when not used.)
BMODE1–0
I
Boot Mode Strap (These pins must be pulled to the state required for the desired boot mode.)
O
External FET Drive
VDDEXT
P
I/O Power Supply
VDDINT
P
Core Power Supply
VDDRTC
P
Real-Time Clock Power Supply
GND
G
External Ground
Voltage Regulator
VROUT1–0
Supplies
1
Refer to Figure 30 on Page 43 to Figure 41 on Page 45.
Rev. E |
Page 20 of 60 |
July 2007
ADSP-BF531/ADSP-BF532/ADSP-BF533
SPECIFICATIONS
Component specifications are subject to change
without notice.
OPERATING CONDITIONS
Parameter
Conditions
VDDINT Internal Supply Voltage
1
VDDINT Internal Supply Voltage
1
VDDINT Internal Supply Voltage
1
2
Nonautomotive 400 MHz and 500 MHz speed grade models
2
Nonautomotive 533 MHz speed grade models
600 MHz speed grade models
2
Min Nominal
Max Unit
0.8 1.2
1.32
0.8 1.25
1.375 V
V
0.8 1.30
1.45
V
VDDINT Internal Supply Voltage1
Automotive grade models2
0.95 1.2
1.32
V
VDDEXT External Supply Voltage
Nonautomotive grade models2
1.75 1.8/2.5/3.3 3.6
V
2.7 3.3
3.6
V
1.75 1.8/2.5/3.3 3.6
V
2
VDDEXT External Supply Voltage
Automotive grade models
2
VDDRTC Real-Time Clock
Power Supply Voltage
Nonautomotive grade models
VDDRTC Real-Time Clock
Power Supply Voltage
Automotive grade models2
2.7 3.3
3.6
V
VIH
High Level Input Voltage3, 4
VDDEXT =1.85 V
1.3
3.6
V
VIH
High Level Input Voltage3, 4
VDDEXT =Maximum
2.0
3.6
V
VDDEXT =Maximum
2.2
3.6
V
VDDEXT =1.75 V
–0.3
+0.3 V
VIHCLKIN High Level Input Voltage
5
Low Level Input Voltage
3, 6
VIL
Low Level Input Voltage
3, 6
VDDEXT =2.25 V
–0.3
+0.6 V
TJ
Junction Temperature
160-Ball Chip Scale Ball Grid Array (CSP_BGA) @ TAMBIENT = 0°C to +70°C
0
+95
TJ
Junction Temperature
160-Ball Chip Scale Ball Grid Array (CSP_BGA) @ TAMBIENT = –40°C to +85°C
–40
+105 °C
TJ
Junction Temperature
160-Ball Chip Scale Ball Grid Array (CSP_BGA) @ TAMBIENT = –40°C to +105°C –40
+125 °C
TJ
Junction Temperature
169-Ball Plastic Ball Grid Array (PBGA) @ TAMBIENT = –40°C to +105°C
–40
+125 °C
TJ
Junction Temperature
169-Ball Plastic Ball Grid Array (PBGA) @ TAMBIENT = –40°C to +85°C
–40
+105 °C
TJ
Junction Temperature
176-Lead Quad Flatpack (LQFP) @ TAMBIENT = –40°C to +85°C
–40
+100 °C
VIL
1
°C
The regulator can generate VDDINT at levels of 0.85 V to 1.2 V with –5% to +10% tolerance, 1.25 V with–4% to +10% tolerance, and 1.3 V with –0% to +10% tolerance.
See Ordering Guide on Page 59.
3
Applies to all input and bidirectional pins except CLKIN.
4
The ADSP-BF531/ADSP-BF532/ADSP-BF533 processors are 3.3 V tolerant (always accepts up to 3.6 V maximum VIH), but voltage compliance (on outputs, VOH) depends on
the input VDDEXT, because VOH (maximum) approximately equals VDDEXT (maximum). This 3.3 V tolerance applies to bidirectional pins (DATA15–0, TMR2–0, PF15–0, PPI3–0,
RSCLK1–0, TSCLK1–0, RFS1–0, TFS1–0, MOSI, MISO, SCK) and input only pins (BR, ARDY, PPI_CLK, DR0PRI, DR0SEC, DR1PRI, DR1SEC, RX, RTXI, TCK, TDI, TMS,
TRST, CLKIN, RESET, NMI, and BMODE1–0).
5
Applies to CLKIN pin only.
6
Applies to all input and bidirectional pins.
2
Rev. E |
Page 21 of 60 |
July 2007
ADSP-BF531/ADSP-BF532/ADSP-BF533
ELECTRICAL CHARACTERISTICS
Low Power1
Parameter
High Speed2
Test Conditions
Min Typical Max Min Typical Max Unit
VOH
High Level Output Voltage3
@ VDDEXT = 1.75 V, IOH = –0.5 mA
1.5
1.5
V
VOH
High Level Output Voltage
3
@ VDDEXT = 2.25 V, IOH = –0.5 mA
1.9
1.9
V
VOH
High Level Output Voltage
3
@ VDDEXT = 3.0 V, IOH = –0.5 mA
2.4
2.4
V
VOL
Low Level Output Voltage
3
@ VDDEXT = 1.75 V, IOL = 2.0 mA
0.2
0.2
V
VOL
Low Level Output Voltage
3
@ VDDEXT = 2.25 V/3.0 V, IOL = 2.0 mA
0.4
0.4
V
IIH
High Level Input Current4
@ VDDEXT = Maximum, VIN = VDD Maximum
10.0
10.0 μA
IIHP
High Level Input Current JTAG5
@ VDDEXT = Maximum, VIN = VDD Maximum
50.0
50.0 μA
@ VDDEXT = Maximum, VIN = 0 V
10.0
10.0 μA
6
Low Level Input Current
IIL
4
7
IOZH
Three-State Leakage Current
@ VDDEXT = Maximum, VIN = VDD Maximum
10.0
10.0 μA
IOZL6
Three-State Leakage Current7
@ VDDEXT = Maximum, VIN = 0 V
10.0
10.0 μA
CIN
Input Capacitance8
fIN = 1 MHz, TAMBIENT = 25°C, VIN = 2.5 V
4
IDDHIBERNATE
VDDINT Current in Hibernate State
VDDEXT = 3.65 V
with voltage regulator off (VDDINT = 0 V)
50
50
μA
IDDRTC
VDDRTC Current
VDDRTC = 3.3 V, TJUNCTION = 25°C
20
20
μA
IDDDEEPSLEEP
VDDINT Current in Deep Sleep Mode VDDINT = 0.8 V, TJUNCTION = 25°C
7.5
35
mA
IDDSLEEP
VDDINT Current in Sleep Mode
10
37.5
mA
IDD_TYP10, 11
VDDINT Current Dissipation (Typical) VDDINT = 0.8 V, fCCLK = 50 MHz, TJUNCTION = 25°C
20
47
mA
IDD_TYP
10, 11
VDDINT Current Dissipation (Typical) VDDINT = 1.14 V, fCCLK = 400 MHz, TJUNCTION = 25°C
132
198
mA
IDD_TYP
10, 11
VDDINT Current Dissipation (Typical) VDDINT = 1.2 V, fCCLK = 500 MHz, TJUNCTION = 25°C
240
mA
IDD_TYP
10, 11
VDDINT Current Dissipation (Typical) VDDINT = 1.2 V, fCCLK = 533 MHz, TJUNCTION = 25°C
250
mA
IDD_TYP10, 11
VDDINT Current Dissipation (Typical) VDDINT = 1.3 V, fCCLK = 600 MHz, TJUNCTION = 25°C
308
mA
10
VDDINT = 0.8 V, TJUNCTION = 25°C, SCLK = 25 MHz
1
89
4
89
Applies to all 400 MHz speed grade models. See Ordering Guide on Page 59.
Applies to all 500 MHz, 533 MHz, and 600 MHz speed grade models. See Ordering Guide on Page 59.
3
Applies to output and bidirectional pins.
4
Applies to input pins except JTAG inputs.
5
Applies to JTAG input pins (TCK, TDI, TMS, TRST).
6
Absolute value.
7
Applies to three-statable pins.
8
Applies to all signal pins.
9
Guaranteed, but not tested.
10
See Estimating Power for ADSP-BF531/BF532/BF533 Blackfin Processors (EE-229) on the Analog Devices website (www.analog.com)—use site search on “EE-229.”
11
Processor executing 75% dual MAC, 25% ADD with moderate data bus activity.
2
Rev. E |
Page 22 of 60 |
July 2007
pF
ADSP-BF531/ADSP-BF532/ADSP-BF533
ABSOLUTE MAXIMUM RATINGS
Stresses greater than those listed in the table may cause perma­
nent damage to the device. These are stress ratings only.
Functional operation of the device at these or any other condi­
tions greater than those indicated in the operational sections of
this specification is not implied. Exposure to absolute maximum
rating conditions for extended periods may affect device
reliability.
PACKAGE INFORMATION
The information presented in Figure 10 and Table 11 provides
details about the package branding for the Blackfin processors.
For a complete listing of product availability, see the Ordering
Guide on Page 59.
a
Parameter
Rating
Internal (Core) Supply Voltage (VDDINT)
–0.3 V to + 1.4 V
External (I/O) Supply Voltage (VDDEXT)
–0.5 V to +3.8 V
Input Voltage1
–0.5 V to +3.8 V
ADSP-BF53x
tppZ-cc
vvvvvv.x n.n
yyww country_of_origin
Output Voltage Swing
–0.5 V to VDDEXT +0.5 V
Load Capacitance2
200 pF
Storage Temperature Range
–65 C to +150°C
Junction Temperature Under Bias
125°C
B
Figure 10. Product Information on Package
Table 11. Package Brand Information
1
Applies to 100% transient duty cycle. For other duty cycles see Table 10.
2
For proper SDRAM controller operation, the maximum load capacitance is 50 pF
(at 3.3 V) or 30 pF (at 2.5 V) for ADDR19–1, DATA15–0, ABE1–0/SDQM1–0,
CLKOUT, SCKE, SA10, SRAS, SCAS, SWE, and SMS.
Table 10. Maximum Duty Cycle for Input Transient Voltage1
Brand Key
Field Description
ADSP-BF53x Either ADSP-BF531, ADSP-BF532, or ADSP-BF533
t
Temperature Range
pp
Package Type
VIN Min (V)
VIN Max (V)2
Maximum Duty Cycle
–0.50
+3.80
100%
Z
RoHS Compliant Part
–0.70
+4.00
40%
cc
See Ordering Guide
–0.80
+4.10
25%
vvvvvv.x
Assembly Lot Code
–0.90
+4.20
15%
–1.00
+4.30
10%
n.n
Silicon Revision
yyww
Date Code
1
2
Applies to all signal pins with the exception of CLKIN, XTAL, VROUT1–0.
Only one of the listed options can apply to a particular design.
ESD SENSITIVITY
ESD (electrostatic discharge) sensitive device.
Charged devices and circuit boards can discharge
without detection. Although this product features
patented or proprietary circuitry, damage may occur
on devices subjected to high energy ESD. Therefore,
proper ESD precautions should be take to avoid
performance degradation or loss of functionality.
Rev. E |
Page 23 of 60 |
July 2007
ADSP-BF531/ADSP-BF532/ADSP-BF533
TIMING SPECIFICATIONS
Table 12 through Table 15 describe the timing requirements for
the ADSP-BF531/ADSP-BF532/ADSP-BF533 processor clocks.
Take care in selecting MSEL, SSEL, and CSEL ratios so as not to
exceed the maximum core clock and system clock as described
in Absolute Maximum Ratings on Page 23, and the voltage con­
trolled oscillator (VCO) operating frequencies described in
Table 14. Table 14 describes phase-locked loop operating
conditions.
Table 12. Core Clock (CCLK) Requirements—400 MHz Models1
Internal Regulator Setting
1.20 V
1.10 V
1.00 V
0.90 V
0.85 V
Parameter
fCCLK
CCLK Frequency (VDDINT =1.14 V Minimum)
fCCLK
CCLK Frequency (VDDINT =1.045 V Minimum)
fCCLK
CCLK Frequency (VDDINT =0.95 V Minimum)
fCCLK
CCLK Frequency (VDDINT =0.85 V Minimum)
fCCLK
CCLK Frequency (VDDINT =0.8 V Minimum)
1
2
TJUNCTION = 125°C
Max
400
333
295
All2 Other TJUNCTION
Max
400
364
333
280
250
Unit
MHz
MHz
MHz
MHz
MHz
Max
600
533
500
444
400
333
250
Unit
MHz
MHz
MHz
MHz
MHz
MHz
MHz
See Ordering Guide on Page 59.
See Operating Conditions on Page 21.
Table 13. Core Clock (CCLK) Requirements—500 MHz, 533 MHz, and 600 MHz Models
Parameter
fCCLK
CCLK Frequency (VDDINT =1.3 V Minimum)1
fCCLK
CCLK Frequency (VDDINT =1.2 V Minimum)2
CCLK Frequency (VDDINT =1.14 V Minimum)3
fCCLK
fCCLK
CCLK Frequency (VDDINT =1.045 V Minimum)
fCCLK
CCLK Frequency (VDDINT =0.95 V Minimum)
fCCLK
CCLK Frequency (VDDINT =0.85 V Minimum)
fCCLK
CCLK Frequency (VDDINT =0.8 V Minimum)
Internal Regulator Setting
1.30 V
1.25 V
1.20 V
1.10 V
1.00 V
0.90 V
0.85 V
1
Applies to 600 MHz models only. See Ordering Guide on Page 59.
Applies to 533 MHz and 600 MHz models only. See Ordering Guide on Page 59. 533 MHz models cannot support internal regulator levels above 1.25 V.
3
Applies to 500 MHz, 533 MHz, and 600 MHz models. See Ordering Guide on Page 59. 500 MHz models cannot support internal regulator levels above 1.20 V.
2
Table 14. Phase-Locked Loop Operating Conditions
Parameter
fVCO
Voltage Controlled Oscillator (VCO) Frequency
Min
Max
Unit
50
Maximum fCCLK
MHz
Table 15. System Clock (SCLK) Requirements
Parameter1
MBGA/PBGA
fSCLK
fSCLK
LQFP
fSCLK
fSCLK
1
VDDEXT = 1.8 V
Max
VDDEXT = 2.5 V/3.3 V
Max
Unit
CLKOUT/SCLK Frequency (VDDINT ≥ 1.14 V)
CLKOUT/SCLK Frequency (VDDINT < 1.14 V)
100
100
133
100
MHz
MHz
CLKOUT/SCLK Frequency (VDDINT ≥ 1.14 V)
CLKOUT/SCLK Frequency (VDDINT < 1.14 V)
100
83
133
83
MHz
MHz
tSCLK (= 1/fSCLK) must be greater than or equal to tCCLK.
Rev. E |
Page 24 of 60 |
July 2007
ADSP-BF531/ADSP-BF532/ADSP-BF533
Clock and Reset Timing
Table 16 and Figure 11 describe clock and reset operations. Per
Absolute Maximum Ratings on Page 23, combinations of
CLKIN and clock multipliers/divisors must not result in core/
system clocks exceeding the maximum limits allowed for the
processor, including system clock restrictions related to supply
voltage.
Table 16. Clock and Reset Timing
Parameter
Timing Requirements
tCKIN
CLKIN Period1, 2, 3, 4
tCKINL
CLKIN Low Pulse
tCKINH
CLKIN High Pulse
tWRST
RESET Asserted Pulse Width Low5
1
Min
Max
Unit
25.0
10.0
10.0
11 tCKIN
100.0
ns
ns
ns
ns
Applies to PLL bypass mode and PLL nonbypass mode.
CLKIN frequency must not change on the fly.
3
Combinations of the CLKIN frequency and the PLL clock multiplier must not exceed the allowed fVCO, fCCLK, and fSCLK settings discussed in Table 12 on Page 24 through
Table 15 on Page 24. Since the default behavior of the PLL is to multiply the CLKIN frequency by 10, the 400 MHz speed grade parts cannot use the full CLKIN period range.
4
If the DF bit in the PLL_CTL register is set, then the maximum tCKIN period is 50 ns.
5
Applies after power-up sequence is complete. At power-up, the processor’s internal phase-locked loop requires no more than 2,000 CLKIN cycles, while RESET is asserted,
assuming stable power supplies and CLKIN (not including start-up time of external clock oscillator).
2
tCKIN
CLKIN
tCKINL
tCKINH
tWRST
RESET
Figure 11. Clock and Reset Timing
Rev. E |
Page 25 of 60 |
July 2007
ADSP-BF531/ADSP-BF532/ADSP-BF533
Asynchronous Memory Read Cycle Timing
Table 17. Asynchronous Memory Read Cycle Timing
Parameter
Timing Requirements
tSDAT
DATA15–0 Setup Before CLKOUT
tHDAT
DATA15–0 Hold After CLKOUT
tSARDY
ARDY Setup Before CLKOUT
tHARDY
ARDY Hold After CLKOUT
Switching Characteristics
tDO
Output Delay After CLKOUT1
tHO
Output Hold After CLKOUT 1
1
VDDEXT = 1.8 V
Min
Max
VDDEXT = 2.5 V/3.3 V
Min
Max
Unit
2.1
1.0
4.0
1.0
2.1
0.8
4.0
0.0
ns
ns
ns
ns
6.0
6.0
1.0
ns
ns
0.8
Output pins include AMS3–0, ABE1–0, ADDR19–1, DATA15–0, AOE, ARE.
SETUP
2 CYCLES
PROGRAMMED READ ACCESS
4 CYCLES
HOLD
1 CYCLE
ACCESS EXTENDED
3 CYCLES
CLKOUT
t DO
t HO
AMSx
ABE1–0
ABE, ADDRESS
ADDR19–1
AOE
t DO
tHO
ARE
t SARDY
t HARDY
tHARDY
ARDY
t SARDY
t SDAT
tHDAT
DATA15–0
READ
Figure 12. Asynchronous Memory Read Cycle Timing
Rev. E |
Page 26 of 60 |
July 2007
ADSP-BF531/ADSP-BF532/ADSP-BF533
Asynchronous Memory Write Cycle Timing
Table 18. Asynchronous Memory Write Cycle Timing
Parameter
Timing Requirements
tSARDY
ARDY Setup Before CLKOUT
tHARDY
ARDY Hold After CLKOUT
Switching Characteristics
tDDAT
DATA15–0 Disable After CLKOUT
tENDAT
DATA15–0 Enable After CLKOUT
Output Delay After CLKOUT1
tDO
tHO
Output Hold After CLKOUT 1
1
VDDEXT = 1.8 V
Min
Max
VDDEXT = 2.5 V/3.3 V
Min
Max
Unit
4.0
1.0
4.0
0.0
6.0
1.0
Output pins include AMS3–0, ABE1–0, ADDR19–1, DATA15–0, AOE, AWE.
SETUP
2 CYCLES
PROGRAMMED WRITE
ACCESS 2 CYCLES
ACCESS
EXTENDED
1 CYCLE
HOLD
1 CYCLE
CLKOUT
t DO
t HO
AMSx
ABE1–0
ABE, ADDRESS
ADDR19–1
tDO
tHO
AWE
t HARDY
t SARDY
ARDY
tSARDY
t ENDAT
DATA15–0
6.0
1.0
6.0
1.0
t DD AT
WRITE DATA
Figure 13. Asynchronous Memory Write Cycle Timing
Rev. E |
Page 27 of 60 |
July 2007
ns
ns
6.0
0.8
ns
ns
ns
ns
ADSP-BF531/ADSP-BF532/ADSP-BF533
SDRAM Interface Timing
Table 19. SDRAM Interface Timing1
Parameter
Timing Requirements
tSSDAT
DATA Setup Before CLKOUT
tHSDAT
DATA Hold After CLKOUT
Switching Characteristics
tSCLK
CLKOUT Period2
tSCLKH
CLKOUT Width High
CLKOUT Width Low
tSCLKL
tDCAD
Command, ADDR, Data Delay After CLKOUT3
tHCAD
Command, ADDR, Data Hold After CLKOUT1
tDSDAT
Data Disable After CLKOUT
tENSDAT
Data Enable After CLKOUT
VDDEXT = 1.8 V
Min
Max
VDDEXT = 2.5 V/3.3 V
Min
Max
Unit
2.1
0.8
1.5
0.8
ns
ns
10.0
2.5
2.5
7.5
2.5
2.5
ns
ns
ns
ns
ns
ns
ns
6.0
1.0
4.0
1.0
6.0
1.0
4.0
1.0
1
SDRAM timing for TJUNCTION = 125°C is limited to 100 MHz.
Refer to Table 15 on Page 24 for maximum fSCLK at various VDDINT.
3
Command pins include: SRAS, SCAS, SWE, SDQM, SMS, SA10, SCKE.
2
tSCLK
tSCLKH
CLKOUT
tSSDAT
tSCLKL
tH SDAT
DATA(IN)
tDC AD
tENSDAT
tHCAD
DATA(OUT)
tDCAD
CMND ADDR
(OUT)
tHCAD
NOTE: COMMAND = SRAS, SCAS, SWE, SDQM, SMS, SA10, SCKE.
Figure 14. SDRAM Interface Timing
Rev. E |
Page 28 of 60 |
tDSDAT
July 2007
ADSP-BF531/ADSP-BF532/ADSP-BF533
External Port Bus Request and Grant Cycle Timing
Table 20 and Figure 15 describe external port bus request and
bus grant operations.
Table 20. External Port Bus Request and Grant Cycle Timing
Parameter
Timing Requirements
tBS BR Asserted to CLKOUT High Setup
tBH CLKOUT High to BR Deasserted Hold Time
Switching Characteristics
tSD CLKOUT Low to AMSx, Address, and ARE/AWE Disable
tSE CLKOUT Low to AMSx, Address, and ARE/AWE Enable
tDBG CLKOUT High to BG High Setup
tEBG CLKOUT High to BG Deasserted Hold Time
tDBH CLKOUT High to BGH High Setup
tEBH CLKOUT High to BGH Deasserted Hold Time
VDDEXT = 1.8 V
VDDEXT = 1.8 V VDDEXT = 2.5 V/3.3 V
LQFP/PBGA Packages MBGA Package
All Packages
Min
Max
Min
Max
Min
Max
Unit
4.6
1.0
4.6
1.0
4.5
4.5
6.0
6.0
6.0
6.0
4.6
0.0
4.5
4.5
4.6
4.6
4.6
4.6
ns
ns
4.5
4.5
3.6
3.6
3.6
3.6
CLKOUT
tBS
tBH
BR
tSD
tSE
AMSx
tSD
tSE
ADDR19-1
ABE1-0
tSD
tSE
AWE
ARE
tDBG
tEBG
BG
tDBH
BGH
Figure 15. External Port Bus Request and Grant Cycle Timing
Rev. E |
Page 29 of 60 |
July 2007
tEBH
ns
ns
ns
ns
ns
ns
ADSP-BF531/ADSP-BF532/ADSP-BF533
Parallel Peripheral Interface Timing
Table 21 and Figure 16 through Figure 21 on Page 33 describe
parallel peripheral interface operations.
Table 21. Parallel Peripheral Interface Timing
Parameter
Timing Requirements
tPCLKW PPI_CLK Width
tPCLK PPI_CLK Period1
tSFSPE External Frame Sync Setup Before PPI_CLK Edge
(Nonsampling Edge for Rx, Sampling Edge for Tx)
tHFSPE External Frame Sync Hold After PPI_CLK
VDDEXT = 1.8 V
LQFP/PBGA Packages
Min
Max
VDDEXT = 1.8 V
MBGA Package
Min
Max
VDDEXT = 2.5 V/3.3 V
All Packages
Min
Max
Unit
8.0
20.0
6.0
8.0
20.0
6.0
1.02
2.03
3.5
1.5
1.02
2.03
3.5
1.5
6.0
15.0
4.02
6.03
1.02
2.03
3.5
1.5
tSDRPE Receive Data Setup Before PPI_CLK
tHDRPE Receive Data Hold After PPI_CLK
Switching Characteristics—GP Output and Frame Capture Modes
tDFSPE Internal Frame Sync Delay After PPI_CLK
tHOFSPE Internal Frame Sync Hold After PPI_CLK
1.7
tDDTPE Transmit Data Delay After PPI_CLK
tHDTPE Transmit Data Hold After PPI_CLK
1.8
11.0
8.0
1.7
11.0
1.8
PPI_CLK frequency cannot exceed fSCLK/2
2
Applies when PPI_CONTROL Bit 8 is cleared. See Figure 17 on Page 31 and Figure 20 on Page 32.
3
Applies when PPI_CONTROL Bit 8 is set. See Figure 18 on Page 31 and Figure 21 on Page 33.
FRAME
SYNC IS
DRIVEN
OUT
DATA0
IS
SAMPLED
POLC = 0
PPI_CLK
PPI_CLK
POLC = 1
tDFSPE
t
HOFSPE
POLS = 1
PPI_FS1
POLS = 0
POLS = 1
PPI_FS2
POLS = 0
tSDRPE
tHDRPE
PPI_DATA
Figure 16. PPI GP Rx Mode with Internal Frame Sync Timing
Rev. E |
Page 30 of 60 |
July 2007
ns
ns
8.0
1.7
9.0
1
ns
ns
ns
ns
ns
9.0
1.8
ns
ns
ns
ns
ADSP-BF531/ADSP-BF532/ADSP-BF533
DATA0 IS
SAMPLED
FRAME
SYNC IS
SAMPLED
FOR
DATA0
DATA1 IS
SAMPLED
PPI_CLK
POLC = 0
PPI_CLK
POLC = 1
t
HFSPE
tSFSPE
POLS = 1
PPI_FS1
POLS = 0
POLS = 1
PPI_FS2
POLS = 0
t
SDRPE
t
HDRPE
PPI_DATA
Figure 17. PPI GP Rx Mode with External Frame Sync Timing
DATA
SAMPLING/
FRAME
SYNC
SAMPLING
EDGE
DATA
SAMPLING/
FRAME
SYNC
SAMPLING
EDGE
PPI_CLK
POLC = 0
PPI_CLK
POLC = 1
t
SFSPE
t
HFSPE
POLS = 1
PPI_FS1
POLS = 0
POLS = 1
PPI_FS2
POLS = 0
t
SDRPE
t
HDRPE
PPI_DATA
Figure 18. PPI GP Rx Mode with External Frame Sync Timing (Bit 8 of PPI_CONTROL Set)
Rev. E |
Page 31 of 60 |
July 2007
ADSP-BF531/ADSP-BF532/ADSP-BF533
FRAME
SYNC IS
DRIVEN
OUT
DATA0 IS
DRIVEN
OUT
PPI_CLK
POLC = 0
PPI_CLK
POLC = 1
t
DFSPE
tHOFSPE
POLS = 1
PPI_FS1
POLS = 0
POLS = 1
PPI_FS2
POLS = 0
t
t
DDTPE
HDTPE
PPI_DATA
DATA0
Figure 19. PPI GP Tx Mode with Internal Frame Sync Timing
FRAME
SYNC IS
SAMPLED
DATA0 IS
DRIVEN
OUT
PPI_CLK
POLC = 0
PPI_CLK
POLC = 1
tHFSPE
tSFSPE
POLS = 1
PPI_FS1
POLS = 0
POLS = 1
PPI_FS2
POLS = 0
tHDTPE
PPI_DATA
DATA0
t
DDTPE
Figure 20. PPI GP Tx Mode with External Frame Sync Timing
Rev. E |
Page 32 of 60 |
July 2007
ADSP-BF531/ADSP-BF532/ADSP-BF533
DATA
DRIVING/
FRAME
SYNC
SAMPLING
EDGE
DATA
DRIVING/
FRAME
SYNC
SAMPLING
EDGE
PPI_CLK
POLC = 0
PPI_CLK
POLC = 1
t
t
HFSPE
SFSPE
POLS = 1
PPI_FS1
POLS = 0
POLS = 1
PPI_FS2
POLS = 0
tDDTPE
t
HDTPE
PPI_DATA
Figure 21. PPI GP Tx Mode with External Frame Sync Timing (Bit 8 of PPI_CONTROL Set)
Rev. E |
Page 33 of 60 |
July 2007
ADSP-BF531/ADSP-BF532/ADSP-BF533
Serial Ports
Table 22 through Table 25 on Page 35 and Figure 22 on Page 35
through Figure 23 on Page 36 describe Serial Port operations.
Table 22. Serial Ports—External Clock
Parameter
Timing Requirements
tSFSE
TFSx/RFSx Setup Before TSCLKx/RSCLKx1
tHFSE
TFSx/RFSx Hold After TSCLKx/RSCLKx1
tSDRE
Receive Data Setup Before RSCLKx1
tHDRE Receive Data Hold After RSCLKx1
tSCLKEW TSCLKx/RSCLKx Width
tSCLKE TSCLKx/RSCLKx Period
Switching Characteristics
tDFSE
TFSx/RFSx Delay After TSCLKx/RSCLKx (Internally Generated TFSx/RFSx)3
tHOFSE TFSx/RFSx Hold After TSCLKx/RSCLKx (Internally Generated TFSx/RFSx)1
tDDTE Transmit Data Delay After TSCLKx1
tHDTE Transmit Data Hold After TSCLKx1
VDDEXT = 1.8 V
Min
Max
VDDEXT = 2.5 V/3.3 V
Min
Max
Unit
3.0
3.0
3.0
3.0
8.0
20.0
3.0
3.0
3.0
3.0
4.5
15.02
10.0
0.0
ns
ns
ns
ns
ns
ns
10.0
0.0
10.0
0.0
10.0
0.0
ns
ns
ns
ns
1
Referenced to sample edge.
For receive mode with external RSCLKx and external RFSx only, the maximum specification is 11.11 ns (90 MHz).
3
Referenced to drive edge.
2
Table 23. Serial Ports—Internal Clock
VDDEXT = 1.8 V VDDEXT = 1.8 V VDDEXT = 2.5 V/3.3 V
LQFP/PBGA MBGA Package
All Packages
Packages
Min
Max
Min
Max
Min
Max
Unit
Parameter
Timing Requirements
tSFSI TFSx/RFSx Setup Before TSCLKx/RSCLKx1
11.0
tHFSI TFSx/RFSx Hold After TSCLKx/RSCLKx1
−2.0
9.5
tSDRI Receive Data Setup Before RSCLKx1
1
tHDRI Receive Data Hold After RSCLKx
0.0
tSCLKEW TSCLKx/RSCLKx Width
4.5
tSCLKE TSCLKx/RSCLKx Period
20.0
Switching Characteristics
tDFSI TFSx/RFSx Delay After TSCLKx/RSCLKx (Internally Generated TFSx/RFSx)2
tHOFSI TFSx/RFSx Hold After TSCLKx/RSCLKx (Internally Generated TFSx/RFSx)1 −1.0
tDDTI Transmit Data Delay After TSCLKx1
tHDTI Transmit Data Hold After TSCLKx1
−2.5
tSCLKIW TSCLKx/RSCLKx Width
6.0
1
2
Referenced to sample edge.
Referenced to drive edge.
Rev. E |
Page 34 of 60 |
July 2007
11.0
−2.0
9.0
0.0
4.5
15.0
3.0
9.0
−2.0
9.0
0.0
4.5
15.0
3.0
−1.0
3.0
3.0
−1.0
3.0
−2.0
6.0
ns
ns
ns
ns
ns
ns
3.0
−2.0
4.5
ns
ns
ns
ns
ns
ADSP-BF531/ADSP-BF532/ADSP-BF533
DATA RECEIVE—INTERNAL CLOCK
DATA RECEIVE—EXTERNAL CLOCK
DRIVE
EDGE
DRIVE
EDGE
SAMPLE
EDGE
SAMPLE
EDGE
tSCLKIW
tSCLKEW
RSCLKx
RSCLKx
tDFSI
tDFSE
tHOFSI
tSFSI
tHFSI
RFSx
tHOFSE
tSFSE
tHFSE
tSDRE
tHDRE
RFSx
tSDRI
tHDRI
DRx
DRx
NOTE: EITHER THE RISING EDGE OR FALLING EDGE OF RSCLKx OR TSCLKx CAN BE USED AS THE ACTIVE SAMPLING EDGE.
DATA TRANSMIT—INTERNAL CLOCK
DRIVE
EDGE
DATA TRANSMIT—EXTERNAL CLOCK
SAMPLE
EDGE
DRIVE
EDGE
SAMPLE
EDGE
tSCLKIW
tSCLKEW
TSCLKx
TSCLKx
tDFSI
tHOFSI
tDFSE
tSFSI
tHFSI
tHOFSE
TFSx
tSFSE
tHFSE
TFSx
tDDTI
tDDTE
tHDTI
tHDTE
DTx
DTx
NOTE: EITHER THE RISING EDGE OR FALLING EDGE OF RSCLKx OR TSCLKx CAN BE USED AS THE ACTIVE SAMPLING EDGE.
Figure 22. Serial Ports
Table 24. Serial Ports—Enable and Three-State
Parameter
Switching Characteristics
tDTENE
Data Enable Delay from External TSCLKx1
tDDTTE
Data Disable Delay from External TSCLKx1
tDTENI
Data Enable Delay from Internal TSCLKx1
tDDTTI
Data Disable Delay from Internal TSCLKx1
1
Min
VDDEXT = 1.8 V
Max
VDDEXT = 2.5 V/3.3 V
Min
Max
Unit
0
0
10.0
10.0
−2.0
−2.0
3.0
3.0
ns
ns
ns
ns
Referenced to drive edge.
Table 25. External Late Frame Sync
VDDEXT = 1.8 V
VDDEXT = 1.8 V
LQFP/PBGA Packages
MBGA Package
Min
Max
Min
Max
Parameter
Switching Characteristics
tDDTLFSE Data Delay from Late External TFSx or External RFSx
with MCE = 1, MFD = 01, 2
tDTENLFS Data Enable from Late FS or MCE = 1, MFD = 01, 2 0
10.5
10.0
0
1
MCE = 1, TFSx enable and TFSx valid follow tDTENLFS and tDDTLFSE.
2
If external RFSx/TFSx setup to RSCLKx/TSCLK x> tSCLKE/2, then tDDTTE/I and tDTENE/I apply; otherwise tDDTLFSE and tDTENLFS apply.
Rev. E |
Page 35 of 60 |
VDDEXT = 2.5 V/3.3 V
All Packages
Min
Max
July 2007
10.0
0
Unit
ns
ns
ADSP-BF531/ADSP-BF532/ADSP-BF533
EXTERNAL RFSx WITH MCE = 1, MFD = 0
DRIVE
RSCLKx
SAMPLE
DRIVE
tSFSE/I
tHOFSE/I
RFSx
tDDTTE/I
tDTENE/I
tDTENLFS
1ST BIT
DTx
2ND BIT
tDDTLFSE
LATE EXTERNAL TFSx
DRIVE
TSCLKx
SAMPLE
DRIVE
tHOFSE/I
tSFSE/I
TFSx
tDDTTE/I
tDTENE/I
tDTENLFS
DTx
1ST BIT
2ND BIT
tDDTLFSE
Figure 23. External Late Frame Sync
Rev. E |
Page 36 of 60 |
July 2007
ADSP-BF531/ADSP-BF532/ADSP-BF533
Serial Peripheral Interface (SPI) Port
—Master Timing
Table 26 and Figure 24 describe SPI port master operations.
Table 26. Serial Peripheral Interface (SPI) Port—Master Timing
VDDEXT = 1.8 V
VDDEXT = 1.8 V
LQFP/PBGA Packages
MBGA Package
Min
Max
Min
Max
Parameter
Timing Requirements
tSSPIDM Data Input Valid to SCK Edge (Data Input Setup) 10.5
tHSPIDM SCK Sampling Edge to Data Input Invalid
–1.5
Switching Characteristics
tSDSCIM SPISELx Low to First SCK Edge
2tSCLK –1.5
tSPICHM Serial Clock High Period
2tSCLK –1.5
tSPICLM Serial Clock Low Period
2tSCLK –1.5
tSPICLK Serial Clock Period
4tSCLK –1.5
tHDSM Last SCK Edge to SPISELx High
2tSCLK –1.5
tSPITDM Sequential Transfer Delay
2tSCLK –1.5
0
tDDSPIDM SCK Edge to Data Out Valid (Data Out Delay)
tHDSPIDM SCK Edge to Data Out Invalid (Data Out Hold) –1.0
6
+4.0
VDDEXT = 2.5 V/3.3 V
All Packages
Min
Max
Unit
8.5
–1.5
7.5
–1.5
ns
ns
2tSCLK –1.5
2tSCLK –1.5
2tSCLK –1.5
4tSCLK –1.5
2tSCLK –1.5
2tSCLK –1.5
0
–1.0
2tSCLK –1.5
2tSCLK –1.5
2tSCLK –1.5
4tSCLK –1.5
2tSCLK –1.5
2tSCLK –1.5
0
–1.0
ns
ns
ns
ns
ns
ns
ns
ns
6
+4.0
SPISELx
(OUTPUT)
tSDSCIM
tSPICHM
tSPICLM
tSPICLM
tSPICHM
tSPICLK
tHDSM
SCK
(CPOL = 0)
(OUTPUT)
SCK
(CPOL = 1)
(OUTPUT)
tDDSPIDM
MOSI
(OUTPUT)
tHDSPIDM
MSB
CPHA = 1
tSSPIDM
MISO
(INPUT)
LSB
tHSPIDM
tSSPIDM
MSB VALID
LSB VALID
tDDSPIDM
MOSI
(OUTPUT)
CPHA = 0
tHDSPIDM
MSB
tSSPIDM
MISO
(INPUT)
tHSPIDM
LSB
tHSPIDM
MSB VALID
LSB VALID
Figure 24. Serial Peripheral Interface (SPI) Port—Master Timing
Rev. E |
Page 37 of 60 |
July 2007
tSPITDM
6
+4.0
ADSP-BF531/ADSP-BF532/ADSP-BF533
Serial Peripheral Interface (SPI) Port
—Slave Timing
Table 27 and Figure 25 describe SPI port slave operations.
Table 27. Serial Peripheral Interface (SPI) Port—Slave Timing
VDDEXT = 1.8 V
VDDEXT = 1.8 V
LQFP/PBGA Packages
MBGA Package
Min
Max
Min
Max
Parameter
Timing Requirements
tSPICHS Serial Clock High Period
2tSCLK –1.5
tSPICLS Serial Clock Low Period
2tSCLK –1.5
tSPICLK Serial Clock Period
4tSCLK –1.5
2tSCLK –1.5
tHDS Last SCK Edge to SPISS Not Asserted
tSPITDS Sequential Transfer Delay
2tSCLK –1.5
tSDSCI SPISS Assertion to First SCK Edge
2tSCLK –1.5
tSSPID Data Input Valid to SCK Edge (Data Input Setup) 1.6
tHSPID SCK Sampling Edge to Data Input Invalid
1.6
Switching Characteristics
tDSOE SPISS Assertion to Data Out Active
0
tDSDHI SPISS Deassertion to Data High Impedance
0
tDDSPID SCK Edge to Data Out Valid (Data Out Delay)
0
tHDSPID SCK Edge to Data Out Invalid (Data Out Hold) 0
2tSCLK –1.5
2tSCLK –1.5
4tSCLK –1.5
2tSCLK –1.5
2tSCLK –1.5
2tSCLK –1.5
1.6
1.6
10
10
10
10
0
0
0
0
9
9
10
10
VDDEXT = 2.5 V/3.3 V
All Packages
Min
Max
Unit
2tSCLK –1.5
2tSCLK –1.5
4tSCLK –1.5
2tSCLK –1.5
2tSCLK –1.5
2tSCLK –1.5
1.6
1.6
ns
ns
ns
ns
ns
ns
ns
ns
0
0
0
0
SPISS
(INPUT)
tSPICHS
tSPICLS
tSPICLS
tSPICHS
tSPICLK
tHDS
tSPITDS
SCK
(CPOL = 0)
(INPUT)
tSDSCI
SCK
(CPOL = 1)
(INPUT)
tDSOE
tDDSPID
tHDSPID
MISO
(OUTPUT)
tDSDHI
MSB
CPHA = 1
tSSPID
MOSI
(INPUT)
LSB
tHSPID
tSSPID
tHSPID
MSB VALID
tDSOE
MISO
(OUTPUT)
tDDSPID
LSB VALID
tDDSPID
tDSDHI
MSB
LSB
tHSPID
CPHA = 0
tSSPID
MOSI
(INPUT)
MSB VALID
LSB VALID
Figure 25. Serial Peripheral Interface (SPI) Port—Slave Timing
Rev. E |
Page 38 of 60 |
July 2007
8
8
10
10
ns
ns
ns
ns
ADSP-BF531/ADSP-BF532/ADSP-BF533
Universal Asynchronous Receiver-Transmitter
(UART) Port—Receive and Transmit Timing
Figure 26 describes UART port receive and transmit operations.
The maximum baud rate is SCLK/16. As shown in Figure 26
there is some latency between the generation internal UART
interrupts and the external data operations. These latencies are
negligible at the data transmission rates for the UART.
CLKOUT
(SAMPLE CLOCK)
Rx
DATA[8:5]
STOP
RECEIVE
INTERNAL
UART RECEIVE
INTERRUPT
UART RECEIVE BIT SET BY DATA STOP;
CLEARED BY FIFO READ
START
Tx
DATA[8:5]
STOP[2:1]
TRANSMIT
INTERNAL
UART TRANSMIT
INTERRUPT
UART TRANSMIT BIT SET BY PROGRAM;
CLEARED BY WRITE TO TRANSMIT
Figure 26. UART Port—Receive and Transmit Timing
Rev. E |
Page 39 of 60 |
July 2007
ADSP-BF531/ADSP-BF532/ADSP-BF533
General-Purpose I/O Port F Pin Cycle Timing
Table 28 and Figure 27 describe GPIO pin operations.
Table 28. General-Purpose I/O Port F Pin Cycle Timing
Parameter
Timing Requirement
tWFI
GPIO Input Pulse Width
Switching Characteristic
tDFO
GPIO Output Delay from CLKOUT Low
VDDEXT = 1.8 V
Min
Max
VDDEXT = 2.5 V/3.3 V
Min
Max
Unit
tSCLK + 1
tSCLK + 1
6
CLKOUT
tDFO
PFx (OUTPUT)
GPIO OUTPUT
tWFI
PFx (INPUT)
GPIO INPUT
Figure 27. GPIO Cycle Timing
Rev. E |
Page 40 of 60 |
July 2007
ns
6
ns
ADSP-BF531/ADSP-BF532/ADSP-BF533
Timer Cycle Timing
Table 29 and Figure 28 describe timer expired operations. The
input signal is asynchronous in width capture mode and exter­
nal clock mode and has an absolute maximum input frequency
of fSCLK/2 MHz.
Table 29. Timer Cycle Timing
Parameter
Timing Characteristics
tWL Timer Pulse Width Input Low1 (Measured in SCLK Cycles)
tWH Timer Pulse Width Input High1 (Measured in SCLK Cycles)
Switching Characteristic
tHTO Timer Pulse Width Output2 (Measured in SCLK Cycles)
Min
VDDEXT = 1.8 V
Max
1
1
1
1
(232–1)
VDDEXT = 2.5 V/3.3 V
Min
Max
Unit
1
1
SCLK
SCLK
1
(232–1)
SCLK
The minimum pulse widths apply for TMRx input pins in width capture and external clock modes. They also apply to the PF1 or PPI_CLK input pins in PWM output mode.
2
The minimum time for tHTO is one cycle, and the maximum time for tHTO equals (232–1) cycles.
CLKOUT
tHTO
TMRx
(PWM OUTPUT MODE)
TMRx
(WIDTH CAPTURE AND
EXTERNAL CLOCK MODES)
tWL
tWH
Figure 28. Timer PWM_OUT Cycle Timing
Rev. E |
Page 41 of 60 |
July 2007
ADSP-BF531/ADSP-BF532/ADSP-BF533
JTAG Test and Emulation Port Timing
Table 30 and Figure 29 describe JTAG port operations.
Table 30. JTAG Port Timing
Parameter
Timing Requirements
tTCK
TCK Period
TDI, TMS Setup Before TCK High
tSTAP
tHTAP
TDI, TMS Hold After TCK High
tSSYS
System Inputs Setup Before TCK High1
tHSYS
System Inputs Hold After TCK High1
tTRSTW
TRST Pulse Width2 (Measured in TCK Cycles)
Switching Characteristics
tDTDO
TDO Delay from TCK Low
tDSYS
System Outputs Delay After TCK Low3
Min
VDDEXT = 1.8 V
Max
20
4
4
4
5
4
0
1
10
12
VDDEXT = 2.5 V/3.3 V
Min
Max
Unit
20
4
4
4
5
4
ns
ns
ns
ns
ns
TCK
0
10
12
ns
ns
System Inputs = DATA15–0, ARDY, TMR2–0, PF15–0, PPI_CLK, RSCLK0–1, RFS0–1, DR0PRI, DR0SEC, TSCLK0–1, TFS0–1, DR1PRI, DR1SEC, MOSI, MISO, SCK, RX,
RESET, NMI, BMODE1–0, BR, PP3–0.
50 MHz maximum
3
System Outputs = DATA15–0, ADDR19–1, ABE1–0, AOE, ARE, AWE, AMS3–0, SRAS, SCAS, SWE, SCKE, CLKOUT, SA10, SMS, TMR2–0, PF15–0, RSCLK0–1, RFS0–1,
TSCLK0–1, TFS0–1, DT0PRI, DT0SEC, DT1PRI, DT1SEC, MOSI, MISO, SCK, TX, BG, BGH, PPI3–0.
2
tTCK
TCK
tSTAP
tHTAP
TMS
TDI
tDTDO
TDO
tSSYS
tHSYS
SYSTEM
INPUTS
tDSYS
SYSTEM
OUTPUT
Figure 29. JTAG Port Timing
Rev. E |
Page 42 of 60 |
July 2007
ADSP-BF531/ADSP-BF532/ADSP-BF533
OUTPUT DRIVE CURRENTS
150
150
VDDEXT = 2.75V
VDDEXT = 2.50V
VDDEXT = 2.25V
SOURCE CURRENT (mA)
100
50
0
VOH
–50
–100
VOL
50
–150
0
0
1.0
1.5
2.0
2.5
3.0
3.5
SOURCE VOLTAGE (V)
Figure 32. Drive Current A (VDDEXT = 3.3 V)
–50
VOL
150
VDDEXT = 2.75V
VDDEXT = 2.50V
VDDEXT = 2.25V
100
0
0.5
1.0
1.5
2.0
2.5
3.0
SOURCE CURRENT (mA)
–150
0.5
VOH
–100
SOURCE VOLTAGE (V)
Figure 30. Drive Current A (VDDEXT = 2.5 V)
80
60
VDDEXT = 1.9V
VDDEXT = 1.8V
40
VDDEXT = 1.7V
50
0
VOH
–50
–100
VOL
20
–150
0
0
0.5
1.0
1.5
2.0
2.5
3.0
SOURCE VOLTAGE (V)
–20
Figure 33. Drive Current B (VDDEXT = 2.5 V)
–40
80
–60
–80
0
0.5
1.0
1.5
60
VDDEXT = 1.9V
VDDEXT = 1.8V
40
VDDEXT = 1.7V
2.0
SOURCE VOLTAGE (V)
SOURCE CURRENT (mA)
SOURCE CURRENT (mA)
VDDEXT = 3.65V
VDDEXT = 3.30V
VDDEXT = 2.95V
100
SOURCE CURRENT (mA)
Figure 30 through Figure 41 show typical current-voltage char­
acteristics for the output drivers of the ADSP-BF531/
ADSP-BF532/ADSP-BF533 processor. The curves represent the
current drive capability of the output drivers as a function of
output voltage.
Figure 31. Drive Current A (VDDEXT = 1.8 V)
20
0
–20
–40
–60
–80
0
0.5
1.0
1.5
SOURCE VOLTAGE (V)
Figure 34. Drive Current B (VDDEXT = 1.8 V)
Rev. E |
Page 43 of 60 |
July 2007
2.0
ADSP-BF531/ADSP-BF532/ADSP-BF533
100
150
60
SOURCE CURRENT (mA)
SOURCE CURRENT (mA)
100
VDDEXT = 3.65V
VDDEXT = 3.30V
VDDEXT = 2.95V
80
VDDEXT = 3.65V
VDDEXT = 3.30V
VDDEXT = 2.95V
50
0
VOH
–50
–100
40
20
0
VOH
–20
–40
VOL
–60
VOL
–80
–150
0
0.5
1.0
1.5
2.0
SOURCE VOLTAGE (V)
2.5
3.0
–100
0
3.5
0.5
1.0
1.5
2.0
2.5
3.0
3.5
SOURCE VOLTAGE (V)
Figure 35. Drive Current B (VDDEXT = 3.3 V)
Figure 38. Drive Current C (VDDEXT = 3.3 V)
60
100
VDDEXT = 2.75V
VDDEXT = 2.50V
VDDEXT = 2.25V
40
VDDEXT = 2.75V
80
VDDEXT = 2.50V
VDDEXT = 2.25V
60
0
SOURCE CURRENT (mA)
SOURCE CURRENT (mA)
20
VOH
–20
–40
20
0
VOH
–20
–40
–60
VOL
–60
40
VOL
–80
0
0.5
1.0
1.5
2.0
2.5
3.0
–100
SOURCE VOLTAGE (V)
0
0.5
1.0
1.5
2.0
2.5
3.0
SOURCE VOLTAGE (V)
Figure 36. Drive Current C (VDDEXT = 2.5 V)
Figure 39. Drive Current D (VDDEXT = 2.5 V)
30
VDDEXT = 1.9V
VDDEXT = 1.8V
60
VDDEXT = 1.7V
VDDEXT = 1.9V
VDDEXT = 1.8V
40
10
SOURCE CURRENT (mA)
SOURCE CURRENT (mA)
20
0
–10
–20
VDDEXT = 1.7V
20
0
–20
–30
–40
–40
0
0.5
1.0
1.5
2.0
SOURCE VOLTAGE (V)
–60
0
Figure 37. Drive Current C (VDDEXT = 1.8 V)
0.5
1.0
SOURCE VOLTAGE (V)
1.5
Figure 40. Drive Current D (VDDEXT = 1.8 V)
Rev. E |
Page 44 of 60 |
July 2007
2.0
ADSP-BF531/ADSP-BF532/ADSP-BF533
VTRIP (high) is 2.0 V and VTRIP (low) is 1.0 V . Time tTRIP is the
interval from when the output starts driving to when the output
reaches the VTRIP (high) or VTRIP (low) trip voltage.
150
VDDEXT = 3.65V
VDDEXT = 3.30V
VDDEXT = 2.95V
SOURCE CURRENT (mA)
100
Time tENA is calculated as shown in the equation:
50
t ENA = t ENA_MEASURED – t TRIP
0
If multiple pins (such as the data bus) are enabled, the measure­
ment value is that of the first pin to start driving.
VOH
Output Disable Time Measurement
–50
VOL
–100
–150
0
0.5
1.0
1.5
2.0
SOURCE VOLTAGE (V)
2.5
3.0
3.5
Figure 41. Drive Current D (VDDEXT = 3.3 V)
POWER DISSIPATION
Output pins are considered to be disabled when they stop driv­
ing, go into a high impedance state, and start to decay from their
output high or low voltage. The output disable time tDIS is the
difference between tDIS_MEASURED and tDECAY as shown on the left
side of Figure 42. t DIS = t DIS_MEASURED – t DECAY
The time for the voltage on the bus to decay by ΔV is dependent
on the capacitive load CL and the load current II. This decay time
can be approximated by the equation:
Many operating conditions can affect power dissipation. System
designers should refer to Estimating Power for ADSP-BF531/
BF532/BF533 Blackfin Processors (EE-229) on the Analog
Devices website (www.analog.com)—use site search on
“EE-229.” This document provides detailed information for
optimizing your design for lowest power.
The time tDECAY is calculated with test loads CL and IL, and with
ΔV equal to 0.1 V for VDDEXT (nominal) = 1.8 V or 0.5 V for
VDDEXT (nominal) = 2.5 V/3.3 V.
See the ADSP-BF533 Blackfin Processor Hardware Reference
Manual for definitions of the various operating modes and for
instructions on how to minimize system power.
The time tDIS_MEASURED is the interval from when the reference
signal switches, to when the output voltage decays ΔV from the
measured output high or output low voltage.
t DECAY = (C L ΔV) ⁄ I L
TEST CONDITIONS
All timing parameters appearing in this data sheet were mea­
sured under the conditions described in this section. Figure 42
shows the measurement point for ac measurements (except out­
put enable/disable). The measurement point VMEAS is 0.95 V for
VDDEXT (nominal) = 1.8 V or 1.5 V for VDDEXT (nominal) = 2.5 V/
3.3 V.
INPUT
OR
OUTPUT
VMEAS
REFERENCE
SIGNAL
tDIS_MEASURED
tDIS
VOH
(MEASURED)
VOL
(MEASURED)
VMEAS
tENA_MEASURED
tENA
VOH (MEASURED) � �V
VOL (MEASURED) + �V
VOH(MEASURED)
VTRIP(HIGH)
VTRIP(LOW)
VOL(MEASURED)
tDECAY
Figure 42. Voltage Reference Levels for AC
Measurements (Except Output Enable/Disable)
OUTPUT STOPS DRIVING
tTRIP
OUTPUT STARTS DRIVING
HIGH IMPEDANCE STATE
Output Enable Time Measurement
Figure 43. Output Enable/Disable
Output pins are considered to be enabled when they have made
a transition from a high impedance state to the point when they
start driving.
The output enable time tENA is the interval from the point when a
reference signal reaches a high or low voltage level to the point
when the output starts driving as shown on the right side of
Figure 43.
The time tENA_MEASURED is the interval, from when the reference signal switches, to when the output voltage reaches VTRIP(high) or
VTRIP (low). For VDDEXT (nominal) = 1.8 V—VTRIP (high) is 1.3 V
and VTRIP (low) is 0.7 V. For VDDEXT (nominal) = 2.5 V/3.3 V—
Rev. E |
Example System Hold Time Calculation
To determine the data output hold time in a particular system,
first calculate tDECAY using the equation given above. Choose ΔV
to be the difference between the ADSP-BF531/ADSP-BF532/
ADSP-BF533 processor’s output voltage and the input threshold for the device requiring the hold time. CLis the total bus
capacitance (per data line), and IL is the total leakage or
three-state current (per data line). The hold time will be tDECAY
Page 45 of 60 |
July 2007
ADSP-BF531/ADSP-BF532/ADSP-BF533
Capacitive Loading
Output delays and holds are based on standard capacitive loads:
30 pF on all pins (see Figure 44). VLOAD is 0.95 V for VDDEXT
(nominal) = 1.8 V or 1.5 V for VDDEXT (nominal) =
2.5 V/3.3 V. Figure 45 through Figure 56 on Page 48 show how
output rise time varies with capacitance. The delay and hold
specifications given should be derated by a factor derived from
these figures. The graphs in these figures may not be linear out­
side the ranges shown.
14
RISE AND FALL TIME ns (10% to 90%)
plus the various output disable times as specified in the Timing
Specifications on Page 24 (for example tDSDAT for an SDRAM
write cycle as shown in SDRAM Interface Timing on Page 28).
12
RISE TIME
10
6
4
2
0
50�
TO
OUTPUT
PIN
FALL TIME
8
0
50
VLOAD
100
150
LOAD CAPACITANCE (pF)
200
250
Figure 46. Typical Rise and Fall Times (10% to 90%) versus Load Capacitance
for Driver A at VDDEXT = 2.25 V
30pF
12
RISE AND FALL TIME ns (10% to 90%)
Figure 44. Equivalent Device Loading for AC Measurements
(Includes All Fixtures)
16
RISE AND FALL TIME ns (10% to 90%)
14
RISE TIME
12
10
FALL TIME
8
10
RISE TIME
8
FALL TIME
6
4
2
6
0
4
2
50
100
150
LOAD CAPACITANCE (pF)
200
50
100
150
LOAD CAPACITANCE (pF)
200
250
Figure 47. Typical Rise and Fall Times (10% to 90%) versus Load Capacitance
for Driver A at VDDEXT = 3.65 V
0
0
0
250
14
RISE AND FALL TIME ns (10% to 90%)
Figure 45. Typical Rise and Fall Times (10% to 90%) versus Load Capacitance
for Driver A at VDDEXT = 1.75 V
12
RISE TIME
10
8
FALL TIME
6
4
2
0
0
50
100
150
LOAD CAPACITANCE (pF)
200
250
Figure 48. Typical Rise and Fall Times (10% to 90%) versus Load Capacitance
for Driver B at VDDEXT = 1.75 V
Rev. E |
Page 46 of 60 |
July 2007
ADSP-BF531/ADSP-BF532/ADSP-BF533
30
RISE AND FALL TIME ns (10% to 90%)
RISE AND FALL TIME ns (10% to 90%)
12
10
RISE TIME
8
FALL TIME
6
4
RISE TIME
20
15
FALL TIME
10
5
2
0
25
0
50
100
150
LOAD CAPACITANCE (pF)
200
0
0
250
Figure 49. Typical Rise and Fall Times (10% to 90%) versus Load Capacitance
for Driver B at VDDEXT = 2.25 V
50
100
150
LOAD CAPACITANCE (pF)
200
250
Figure 52. Typical Rise and Fall Times (10% to 90%) versus Load Capacitance
for Driver C at VDDEXT = 2.25 V
20
RISE AND FALL TIME ns (10% to 90%)
RISE AND FALL TIME ns (10% to 90%)
10
9
8
RISE TIME
7
6
FALL TIME
5
4
3
18
16
RISE TIME
14
12
FALL TIME
10
8
6
4
2
2
1
0
0
0
50
100
150
LOAD CAPACITANCE (pF)
200
0
50
250
Figure 50. Typical Rise and Fall Times (10% to 90%) versus Load Capacitance
for Driver B at VDDEXT = 3.65 V
100
150
LOAD CAPACITANCE (pF)
200
250
Figure 53. Typical Rise and Fall Times (10% to 90%) versus Load Capacitance
for Driver C at VDDEXT = 3.65 V
18
RISE AND FALL TIME ns (10% to 90%)
RISE AND FALL TIME ns (10% to 90%)
30
25
RISE TIME
20
FALL TIME
15
10
16
RISE TIME
14
12
FALL TIME
10
8
6
4
2
5
0
0
50
100
150
200
250
LOAD CAPACITANCE (pF)
0
0
50
100
150
LOAD CAPACITANCE (pF)
200
250
Figure 51. Typical Rise and Fall Times (10% to 90%) versus Load Capacitance
for Driver C at VDDEXT = 1.75 V
Rev. E |
Figure 54. Typical Rise and Fall Times (10% to 90%) versus Load Capacitance
for Driver D at VDDEXT = 1.75 V
Page 47 of 60 |
July 2007
ADSP-BF531/ADSP-BF532/ADSP-BF533
where:
RISE AND FALL TIME ns (10% to 90%)
18
TA = ambient temperature (�C).
16
In Table 31 through Table 33, airflow measurements comply
with JEDEC standards JESD51–2 and JESD51–6, and the junc­
tion-to-board measurement complies with JESD51–8. The
junction-to-case measurement complies with MIL-STD-883
(Method 1012.1). All measurements use a 2S2P JEDEC test
board.
14
RISE TIME
12
10
FALL TIME
8
Thermal resistance θJA in Table 31 through Table 33 is the figure
of merit relating to performance of the package and board in a
convective environment. θJMA represents the thermal resistance
under two conditions of airflow. ΨJT represents the correlation
between TJ and TCASE.
6
4
2
0
0
50
100
150
LOAD CAPACITANCE (pF)
200
250
Table 31. Thermal Characteristics for BC-160 Package
Figure 55. Typical Rise and Fall Times (10% to 90%) versus Load Capacitance
for Driver D at VDDEXT = 2.25 V
RISE AND FALL TIME ns (10% to 90%)
14
12
RISE TIME
10
8
FALL TIME
Parameter
Condition
Typical
Unit
θJA
0 Linear m/s Airflow
27.1
�C/W
θJMA
1 Linear m/s Airflow
23.85
�C/W
θJMA
2 Linear m/s Airflow
22.7
�C/W
θJC
Not Applicable
7.26
�C/W
ΨJT
0 Linear m/s Airflow
0.14
�C/W
ΨJT
1 Linear m/s Airflow
0.26
�C/W
ΨJT
2 Linear m/s Airflow
0.35
�C/W
6
Table 32. Thermal Characteristics for ST-176-1 Package
4
2
0
0
50
100
150
LOAD CAPACITANCE (pF)
200
250
Parameter
Condition
Typical
Unit
θJA
0 Linear m/s Airflow
34.9
�C/W
θJMA
1 Linear m/s Airflow
33.0
�C/W
θJMA
2 Linear m/s Airflow
32.0
�C/W
Figure 56. Typical Rise and Fall Times (10% to 90%) versus Load Capacitance
for Driver D at VDDEXT = 3.65 V
ΨJT
0 Linear m/s Airflow
0.50
�C/W
ΨJT
1 Linear m/s Airflow
0.75
�C/W
ENVIRONMENTAL CONDITIONS
ΨJT
2 Linear m/s Airflow
1.00
�C/W
To determine the junction temperature on the application
printed circuit board use:
T J = T CASE + (Ψ JT × P D )
Table 33. Thermal Characteristics for B-169 Package
Parameter
Condition
Typical
Unit
where:
θJA
0 Linear m/s Airflow
22.8
�C/W
TJ = junction temperature (�C).
θJMA
1 Linear m/s Airflow
20.3
�C/W
TCASE = case temperature (�C) measured by customer at top center of package.
θJMA
2 Linear m/s Airflow
19.3
�C/W
ΨJT = from Table 31 through Table 33.
θJC
Not Applicable
10.39
�C/W
ΨJT
0 Linear m/s Airflow
0.59
�C/W
ΨJT
1 Linear m/s Airflow
0.88
�C/W
ΨJT
2 Linear m/s Airflow
1.37
�C/W
PD = power dissipation (see Power Dissipation on Page 45 for the method to calculate PD).
Values of θJA are provided for package comparison and printed circuit board design considerations. θJA can be used for a first order approximation of TJ by the equation:
T J = T A + (θ JA × P D )
Rev. E |
Page 48 of 60 |
July 2007
ADSP-BF531/ADSP-BF532/ADSP-BF533
160-BALL BGA BALL ASSIGNMENT
Table 34 lists the BGA ball assignment by signal. Table 35 on
Page 50 lists the BGA ball assignment by ball number.
Table 34. 160-Ball CSP_BGA Ball Assignment (Alphabetically by Signal)
Signal
ABE0
ABE1
ADDR1
ADDR2
ADDR3
ADDR4
ADDR5
ADDR6
ADDR7
ADDR8
ADDR9
ADDR10
ADDR11
ADDR12
ADDR13
ADDR14
ADDR15
ADDR16
ADDR17
ADDR18
ADDR19
AMS0
AMS1
AMS2
AMS3
AOE
ARDY
ARE
AWE
BG
BGH
BMODE0
BMODE1
BR
CLKIN
CLKOUT
DATA0
DATA1
DATA2
DATA3
Ball No.
H13
H12
J14
K14
L14
J13
K13
L13
K12
L12
M12
M13
M14
N14
N13
N12
M11
N11
P13
P12
P11
E14
F14
F13
G12
G13
E13
G14
H14
P10
N10
N4
P3
D14
A12
B14
M9
N9
P9
M8
Signal
DATA4
DATA5
DATA6
DATA7
DATA8
DATA9
DATA10
DATA11
DATA12
DATA13
DATA14
DATA15
DR0PRI
DR0SEC
DR1PRI
DR1SEC
DT0PRI
DT0SEC
DT1PRI
DT1SEC
EMU
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
Ball No.
N8
P8
M7
N7
P7
M6
N6
P6
M5
N5
P5
P4
K1
J2
G3
F3
H1
H2
F2
E3
M2
A10
A14
B11
C4
C5
C11
D4
D7
D8
D10
D11
F4
F11
G11
H4
H11
K4
K11
L5
Rev. E |
Signal
GND
GND
GND
GND
GND
GND
MISO
MOSI
NMI
PF0
PF1
PF2
PF3
PF4
PF5
PF6
PF7
PF8
PF9
PF10
PF11
PF12
PF13
PF14
PF15
PPI_CLK
PPI0
PPI1
PPI2
PPI3
RESET
RFS0
RFS1
RSCLK0
RSCLK1
RTXI
RTXO
RX
SA10
SCAS
Page 49 of 60 |
July 2007
Ball No.
L6
L8
L10
M4
M10
P14
E2
D3
B10
D2
C1
C2
C3
B1
B2
B3
B4
A2
A3
A4
A5
B5
B6
A6
C6
C9
C8
B8
A7
B7
C10
J3
G2
L1
G1
A9
A8
L3
E12
C14
Signal
SCK
SCKE
SMS
SRAS
SWE
TCK
TDI
TDO
TFS0
TFS1
TMR0
TMR1
TMR2
TMS
TRST
TSCLK0
TSCLK1
TX
VDDEXT
VDDEXT
VDDEXT
VDDEXT
VDDEXT
VDDEXT
VDDEXT
VDDEXT
VDDEXT
VDDEXT
VDDEXT
VDDEXT
VDDINT
VDDINT
VDDINT
VDDINT
VDDINT
VDDINT
VDDRTC
VROUT0
VROUT1
XTAL
Ball No.
D1
B13
C13
D13
D12
P2
M3
N3
H3
E1
L2
M1
K2
N2
N1
J1
F1
K3
A1
C7
C12
D5
D9
F12
G4
J4
J12
L7
L11
P1
D6
E4
E11
J11
L4
L9
B9
A13
B12
A11
ADSP-BF531/ADSP-BF532/ADSP-BF533
Table 35. 160-Ball CSP_BGA Ball Assignment (Numerically by Ball Number)
Ball No.
A1
A2
A3
A4
A5
A6
A7
A8
A9
A10
A11
A12
A13
A14
B1
B2
B3
B4
B5
B6
B7
B8
B9
B10
B11
B12
B13
B14
C1
C2
C3
C4
C5
C6
C7
C8
C9
C10
C11
C12
Signal
VDDEXT
PF8
PF9
PF10
PF11
PF14
PPI2
RTXO
RTXI
GND
XTAL
CLKIN
VROUT0
GND
PF4
PF5
PF6
PF7
PF12
PF13
PPI3
PPI1
VDDRTC
NMI
GND
VROUT1
SCKE
CLKOUT
PF1
PF2
PF3
GND
GND
PF15
VDDEXT
PPI0
PPI_CLK
RESET
GND
VDDEXT
Ball No.
C13
C14
D1
D2
D3
D4
D5
D6
D7
D8
D9
D10
D11
D12
D13
D14
E1
E2
E3
E4
E11
E12
E13
E14
F1
F2
F3
F4
F11
F12
F13
F14
G1
G2
G3
G4
G11
G12
G13
G14
Signal
SMS
SCAS
SCK
PF0
MOSI
GND
VDDEXT
VDDINT
GND
GND
VDDEXT
GND
GND
SWE
SRAS
BR
TFS1
MISO
DT1SEC
VDDINT
VDDINT
SA10
ARDY
AMS0
TSCLK1
DT1PRI
DR1SEC
GND
GND
VDDEXT
AMS2
AMS1
RSCLK1
RFS1
DR1PRI
VDDEXT
GND
AMS3
AOE
ARE
Rev. E |
Ball No.
H1
H2
H3
H4
H11
H12
H13
H14
J1
J2
J3
J4
J11
J12
J13
J14
K1
K2
K3
K4
K11
K12
K13
K14
L1
L2
L3
L4
L5
L6
L7
L8
L9
L10
L11
L12
L13
L14
M1
M2
Page 50 of 60 |
Signal
DT0PRI
DT0SEC
TFS0
GND
GND
ABE1
ABE0
AWE
TSCLK0
DR0SEC
RFS0
VDDEXT
VDDINT
VDDEXT
ADDR4
ADDR1
DR0PRI
TMR2
TX
GND
GND
ADDR7
ADDR5
ADDR2
RSCLK0
TMR0
RX
VDDINT
GND
GND
VDDEXT
GND
VDDINT
GND
VDDEXT
ADDR8
ADDR6
ADDR3
TMR1
EMU
July 2007
Ball No.
M3
M4
M5
M6
M7
M8
M9
M10
M11
M12
M13
M14
N1
N2
N3
N4
N5
N6
N7
N8
N9
N10
N11
N12
N13
N14
P1
P2
P3
P4
P5
P6
P7
P8
P9
P10
P11
P12
P13
P14
Signal
TDI
GND
DATA12
DATA9
DATA6
DATA3
DATA0
GND
ADDR15
ADDR9
ADDR10
ADDR11
TRST
TMS
TDO
BMODE0
DATA13
DATA10
DATA7
DATA4
DATA1
BGH
ADDR16
ADDR14
ADDR13
ADDR12
VDDEXT
TCK
BMODE1
DATA15
DATA14
DATA11
DATA8
DATA5
DATA2
BG
ADDR19
ADDR18
ADDR17
GND
ADSP-BF531/ADSP-BF532/ADSP-BF533
Figure 57 lists the top view of the BGA ball configuration.
Figure 58 lists the bottom view of the BGA ball configuration.
1
2
3
4
5
6
7
8
9 10 11 12 13 14
A
B
C
D
E
F
G
H
J
K
L
M
N
P
KEY:
VDDINT
GND
VDDRTC
I/O
VROUT
VDDEXT
Figure 57. 160-Ball CSP_BGA Ground Configuration (Top View)
14 13 12 11 10 9
8
7
6
5
4
3
2
1
A
B
C
D
E
F
G
H
J
K
L
M
N
P
KEY:
VDDINT
GND
VDDRTC
VDDEXT
I/O
VROUT
Figure 58. 160-Ball CSP_BGA Ground Configuration (Bottom View)
Rev. E |
Page 51 of 60 |
July 2007
ADSP-BF531/ADSP-BF532/ADSP-BF533
169-BALL PBGA BALL ASSIGNMENT
Table 36 lists the PBGA ball assignment by signal. Table 37 on
Page 53 lists the PBGA ball assignment by ball number.
Table 36. 169-Ball PBGA Ball Assignment (Alphabetically by Signal)
Signal
ABE0
ABE1
ADDR1
ADDR2
ADDR3
ADDR4
ADDR5
ADDR6
ADDR7
ADDR8
ADDR9
ADDR10
ADDR11
ADDR12
ADDR13
ADDR14
ADDR15
ADDR16
ADDR17
ADDR18
ADDR19
AMS0
AMS1
AMS2
AMS3
AOE
ARDY
ARE
AWE
BG
BGH
BMODE0
BMODE1
BR
CLKIN
CLKOUT
DATA0
DATA1
DATA2
DATA3
Ball No.
H16
H17
J16
J17
K16
K17
L16
L17
M16
M17
N17
N16
P17
P16
R17
R16
T17
U15
T15
U16
T14
D17
E16
E17
F16
F17
C16
G16
G17
T13
U17
U5
T5
C17
A14
D16
U14
T12
U13
T11
Signal
DATA4
DATA5
DATA6
DATA7
DATA8
DATA9
DATA10
DATA11
DATA12
DATA13
DATA14
DATA15
DR0PRI
DR0SEC
DR1PRI
DR1SEC
DT0PRI
DT0SEC
DT1PRI
DT1SEC
EMU
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
Ball No.
U12
U11
T10
U10
T9
U9
T8
U8
U7
T7
U6
T6
M2
M1
H1
H2
K2
K1
F1
F2
U1
B16
F11
G7
G8
G9
G10
G11
H7
H8
H9
H10
H11
J7
J8
J9
J10
J11
K7
K8
Signal
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
MISO
MOSI
NMI
PF0
PF1
PF2
PF3
PF4
PF5
PF6
PF7
PF8
PF9
PF10
PF11
PF12
PF13
PF14
PF15
PPI_CLK
PPI0
PPI1
PPI2
PPI3
RESET
RFS0
RFS1
RSCLK0
RSCLK1
RTCVDD
Rev. E |
Ball No.
K9
K10
K11
L7
L8
L9
L10
L11
M9
T16
E2
E1
B11
D2
C1
B1
C2
A1
A2
B3
A3
B4
A4
B5
A5
A6
B6
A7
B7
B10
B9
A9
B8
A8
A12
N1
J1
N2
J2
F10
Page 52 of 60 |
Signal
RTXI
RTXO
RX
SA10
SCAS
SCK
SCKE
SMS
SRAS
SWE
TCK
TDI
TDO
TFS0
TFS1
TMR0
TMR1
TMR2
TMS
TRST
TSCLK0
TSCLK1
TX
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDDEXT
VDDEXT
VDDEXT
VDDEXT
VDDEXT
VDDEXT
VDDEXT
VDDEXT
July 2007
Ball No.
A10
A11
T1
B15
A16
D1
B14
A17
A15
B17
U4
U3
T4
L1
G2
R1
P2
P1
T3
U2
L2
G1
R2
F12
G12
H12
J12
K12
L12
M10
M11
M12
B2
F6
F7
F8
F9
G6
H6
J6
Signal
VDDEXT
VDDEXT
VDDEXT
VDDEXT
VDDEXT
VDDEXT
VROUT0
VROUT1
XTAL
Ball No.
K6
L6
M6
M7
M8
T2
B12
B13
A13
ADSP-BF531/ADSP-BF532/ADSP-BF533
Table 37. 169-Ball PBGA Ball Assignment (Numerically by Ball Number)
Ball No.
A1
A2
A3
A4
A5
A6
A7
A8
A9
A10
A11
A12
A13
A14
A15
A16
A17
B1
B2
B3
B4
B5
B6
B7
B8
B9
B10
B11
B12
B13
B14
B15
B16
B17
C1
C2
C16
C17
D1
D2
Signal
PF4
PF5
PF7
PF9
PF11
PF12
PF14
PPI3
PPI1
RTXI
RTXO
RESET
XTAL
CLKIN
SRAS
SCAS
SMS
PF2
VDDEXT
PF6
PF8
PF10
PF13
PF15
PPI2
PPI0
PPI_CLK
NMI
VROUT0
VROUT1
SCKE
SA10
GND
SWE
PF1
PF3
ARDY
BR
SCK
PF0
Ball No.
D16
D17
E1
E2
E16
E17
F1
F2
F6
F7
F8
F9
F10
F11
F12
F16
F17
G1
G2
G6
G7
G8
G9
G10
G11
G12
G16
G17
H1
H2
H6
H7
H8
H9
H10
H11
H12
H16
H17
J1
Signal
CLKOUT
AMS0
MOSI
MISO
AMS1
AMS2
DT1PRI
DT1SEC
VDDEXT
VDDEXT
VDDEXT
VDDEXT
RTCVDD
GND
VDD
AMS3
AOE
TSCLK1
TFS1
VDDEXT
GND
GND
GND
GND
GND
VDD
ARE
AWE
DR1PRI
DR1SEC
VDDEXT
GND
GND
GND
GND
GND
VDD
ABE0
ABE1
RFS1
Ball No.
J2
J6
J7
J8
J9
J10
J11
J12
J16
J17
K1
K2
K6
K7
K8
K9
K10
K11
K12
K16
K17
L1
L2
L6
L7
L8
L9
L10
L11
L12
L16
L17
M1
M2
M6
M7
M8
M9
M10
M11
Rev. E |
Signal
RSCLK1
VDDEXT
GND
GND
GND
GND
GND
VDD
ADDR1
ADDR2
DT0SEC
DT0PRI
VDDEXT
GND
GND
GND
GND
GND
VDD
ADDR3
ADDR4
TFS0
TSCLK0
VDDEXT
GND
GND
GND
GND
GND
VDD
ADDR5
ADDR6
DR0SEC
DR0PRI
VDDEXT
VDDEXT
VDDEXT
GND
VDD
VDD
Page 53 of 60 |
Ball No.
M12
M16
M17
N1
N2
N16
N17
P1
P2
P16
P17
R1
R2
R16
R17
T1
T2
T3
T4
T5
T6
T7
T8
T9
T10
T11
T12
T13
T14
T15
T16
T17
U1
U2
U3
U4
U5
U6
U7
U8
July 2007
Signal
VDD
ADDR7
ADDR8
RFS0
RSCLK0
ADDR10
ADDR9
TMR2
TMR1
ADDR12
ADDR11
TMR0
TX
ADDR14
ADDR13
RX
VDDEXT
TMS
TDO
BMODE1
DATA15
DATA13
DATA10
DATA8
DATA6
DATA3
DATA1
BG
ADDR19
ADDR17
GND
ADDR15
EMU
TRST
TDI
TCK
BMODE0
DATA14
DATA12
DATA11
Ball No.
U9
U10
U11
U12
U13
U14
U15
U16
U17
Signal
DATA9
DATA7
DATA5
DATA4
DATA2
DATA0
ADDR16
ADDR18
BGH
ADSP-BF531/ADSP-BF532/ADSP-BF533
A1 BALL PAD CORNER
A
B
C
D
E
F
G
KEY
H
J
K
L
V
DDINT
GND
NC
V
DDEXT
I/O
V
ROUT
M
N
P
R
T
U
2
1
4
6
5
3
8
7
10
12
11
9
14
13
16
15
17
TOP VIEW
Figure 59. 169-Ball PBGA Ground Configuration (Top View)
A1 BALL PAD CORNER
A
B
KEY:
C
D
E
V
DDINT
GND
NC
V
DDEXT
I/O
V
F
G
H
J
K
L
M
N
P
R
T
U
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
BOTTOM VIEW
Figure 60. 169-Ball PBGA Ground Configuration (Bottom View)
Rev. E |
Page 54 of 60 |
July 2007
ROUT
ADSP-BF531/ADSP-BF532/ADSP-BF533
176-LEAD LQFP PINOUT
Table 38 lists the LQFP pinout by signal. Table 39 on Page 56
lists the LQFP pinout by lead number.
Table 38. 176-Lead LQFP Pin Assignment (Alphabetically by Signal)
Signal
ABE0
ABE1
ADDR1
ADDR2
ADDR3
ADDR4
ADDR5
ADDR6
ADDR7
ADDR8
ADDR9
ADDR10
ADDR11
ADDR12
ADDR13
ADDR14
ADDR15
ADDR16
ADDR17
ADDR18
ADDR19
AMS0
AMS1
AMS2
AMS3
AOE
ARDY
ARE
AWE
BG
BGH
BMODE0
BMODE1
BR
CLKIN
CLKOUT
DATA0
DATA1
DATA10
Lead No.
151
150
149
148
147
146
142
141
140
139
138
137
136
135
127
126
125
124
123
122
121
161
160
159
158
154
162
153
152
119
120
96
95
163
10
169
116
115
103
Signal
DATA3
DATA4
DATA5
DATA6
DATA7
DATA8
DATA9
DATA10
DATA11
DATA12
DATA13
DATA14
DATA15
DR0PRI
DR0SEC
DR1PRI
DR1SEC
DT0PRI
DT0SEC
DT1PRI
DT1SEC
EMU
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
Lead No.
113
112
110
109
108
105
104
103
102
101
100
99
98
74
73
63
62
68
67
59
58
83
1
2
3
7
8
9
15
19
30
39
40
41
42
43
44
56
70
Signal
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
MISO
MOSI
NMI
PF0
PF1
PF2
PF3
PF4
PF5
PF6
PF7
PF8
PF9
PF10
PF11
PF12
PF13
PF14
PF15
Rev. E |
Lead No.
88
89
90
91
92
97
106
117
128
129
130
131
132
133
144
155
170
174
175
176
54
55
14
51
50
49
48
47
46
38
37
36
35
34
33
32
29
28
27
Page 55 of 60 |
Signal
PPI_CLK
PPI0
PPI1
PPI2
PPI3
RESET
RFS0
RFS1
RSCLK0
RSCLK1
RTXI
RTXO
RX
SA10
SCAS
SCK
SCKE
SMS
SRAS
SWE
TCK
TDI
TDO
TFS0
TFS1
TMR0
TMR1
TMR2
TMS
TRST
TSCLK0
TSCLK1
TX
VDDEXT
VDDEXT
VDDEXT
VDDEXT
VDDEXT
VDDEXT
July 2007
Lead No.
21
22
23
24
26
13
75
64
76
65
17
16
82
164
166
53
173
172
167
165
94
86
87
69
60
79
78
77
85
84
72
61
81
6
12
20
31
45
57
Signal
VDDEXT
VDDEXT
VDDEXT
VDDEXT
VDDEXT
VDDEXT
VDDEXT
VDDEXT
VDDINT
VDDINT
VDDINT
VDDINT
VDDINT
VDDINT
VDDINT
VDDINT
VDDRTC
VROUT0
VROUT1
XTAL
Lead No.
71
93
107
118
134
145
156
171
25
52
66
80
111
143
157
168
18
5
4
11
ADSP-BF531/ADSP-BF532/ADSP-BF533
Table 39. 176-Lead LQFP Pin Assignment (Numerically by Lead Number)
Lead No.
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
Signal
GND
GND
GND
VROUT1
VROUT0
VDDEXT
GND
GND
GND
CLKIN
XTAL
VDDEXT
RESET
NMI
GND
RTXO
RTXI
VDDRTC
GND
VDDEXT
PPI_CLK
PPI0
PPI1
PPI2
VDDINT
PPI3
PF15
PF14
PF13
GND
VDDEXT
PF12
PF11
PF10
PF9
PF8
PF7
PF6
GND
GND
Lead No.
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
Signal
GND
GND
GND
GND
VDDEXT
PF5
PF4
PF3
PF2
PF1
PF0
VDDINT
SCK
MISO
MOSI
GND
VDDEXT
DT1SEC
DT1PRI
TFS1
TSCLK1
DR1SEC
DR1PRI
RFS1
RSCLK1
VDDINT
DT0SEC
DT0PRI
TFS0
GND
VDDEXT
TSCLK0
DR0SEC
DR0PRI
RFS0
RSCLK0
TMR2
TMR1
TMR0
VDDINT
Lead No.
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
101
102
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
Rev. E |
Signal
TX
RX
EMU
TRST
TMS
TDI
TDO
GND
GND
GND
GND
GND
VDDEXT
TCK
BMODE1
BMODE0
GND
DATA15
DATA14
DATA13
DATA12
DATA11
DATA10
DATA9
DATA8
GND
VDDEXT
DATA7
DATA6
DATA5
VDDINT
DATA4
DATA3
DATA2
DATA1
DATA0
GND
VDDEXT
BG
BGH
Page 56 of 60 |
Lead No.
121
122
123
124
125
126
127
128
129
130
131
132
133
134
135
136
137
138
139
140
141
142
143
144
145
146
147
148
149
150
151
152
153
154
155
156
157
158
159
160
July 2007
Signal
ADDR19
ADDR18
ADDR17
ADDR16
ADDR15
ADDR14
ADDR13
GND
GND
GND
GND
GND
GND
VDDEXT
ADDR12
ADDR11
ADDR10
ADDR9
ADDR8
ADDR7
ADDR6
ADDR5
VDDINT
GND
VDDEXT
ADDR4
ADDR3
ADDR2
ADDR1
ABE1
ABE0
AWE
ARE
AOE
GND
VDDEXT
VDDINT
AMS3
AMS2
AMS1
Lead No.
161
162
163
164
165
166
167
168
169
170
171
172
173
174
175
176
Signal
AMS0
ARDY
BR
SA10
SWE
SCAS
SRAS
VDDINT
CLKOUT
GND
VDDEXT
SMS
SCKE
GND
GND
GND
ADSP-BF531/ADSP-BF532/ADSP-BF533
OUTLINE DIMENSIONS
Dimensions in the outline dimension figures are shown in
millimeters.
26.00 BSC SQ
0.75
0.60
0.45
24.00 BSC SQ
176
1
133
132
PIN 1
0.27
0.22
0.17
SEATING
PLANE
0.08 MAX LEAD
COPLANARITY
0.15
0.05
1.45
1.40
1.35
1.60 MAX
89
88
44
45
0.50 BSC
LEAD PITCH
DETAIL A
DETAIL A
TOP VIEW (PINS DOWN)
NOTES
1. DIMENSIONS IN MILLIMETERS
2. ACTUAL POSITION OF EACH LEAD IS WITHIN 0.08 OF ITS
IDEAL POSITION, WHEN MEASURED IN THE LATERAL DIRECTION.
3. CENTER DIMENSIONS ARE NOMINAL
Figure 61. 176-Lead Low Profile Quad Flat Package (LQFP) ST-176-1
12.00 BSC SQ
14 12 10
8
6 4
2
13 11 9
7
5
3 1
A
B
C
D
E
F
G
H
J
K
L
M
N
P
BALL A1
INDICATOR
10.40
BSC
SQ
TOP VIEW
1.70
MAX
A1 CORNER
INDEX AREA
0.80 BSC
BALL PITCH
1.31
1.21
1.11
DETAIL A
SEATING
PLANE
0.40 NOM
(NOTE 3)
NOTES
1. DIMENSIONS ARE IN MILLIMETERS.
2. COMPLIES WITH JEDEC REGISTERED OUTLINE
MO-205, VARIATION AE WITH EXCEPTION OF
THE BALL DIAMETER.
3. MINIMUM BALL HEIGHT 0.25.
BOTTOM VIEW
0.12
0.50
MAX
0.45
COPLANARITY
0.40
BALL DIAMETER
DETAIL A
Figure 62. 160-Ball Chip Scale Package Ball Grid Array (CSP_BGA) BC-160-2
Rev. E |
Page 57 of 60 |
July 2007
ADSP-BF531/ADSP-BF532/ADSP-BF533
A1 BALL PAD CORNER
19.00 BSC SQ
16.00 BSC SQ
1.00 BSC
BALL PITCH
A
B
C
D
E
F
G
H
J
K
L
M
N
P
R
T
U
16 14 12 10 8
6
4
2
17 15 13 11 9
7
5
3
1
TOP VIEW
BOTTOM VIEW
0.40 MIN
2.50
2.23
1.97
SIDE VIEW
DETAIL A
0.20 MAX
COPLANARITY
NOTES
1. DIMENSIONS ARE IN MILLIMETERS.
2. COMPLIES WITH JEDEC REGISTERED OUTLINE
MS-034, VARIATION AAG-2
.
3. MINIMUM BALL HEIGHT 0.40
0.70
BALL DIAMETER 0.60
0.50
SEATING PLANE
DETAIL A
Figure 63. 169-Ball Plastic Ball Grid Array (B-169)
SURFACE MOUNT DESIGN
Table 40 is provided as an aid to PCB design. For industrystandard design recommendations, refer to IPC-7351,
Generic Requirements for Surface Mount Design and Land Pat­
tern Standard.
Table 40. BGA Data for Use with Surface Mount Design
Package
Chip Scale Package Ball Grid Array (CSP_BGA) BC-160-2
Plastic Ball Grid Array (PBGA) B-169
Rev. E |
Ball Attach Type
Solder Mask Defined
Solder Mask Defined
Page 58 of 60 |
July 2007
Solder Mask Opening
0.40 mm diameter
0.43 mm diameter
Ball Pad Size
0.55 mm diameter
0.56 mm diameter
ADSP-BF531/ADSP-BF532/ADSP-BF533
ORDERING GUIDE
Model
ADSP-BF531SBB400
ADSP-BF531SBBZ400
ADSP-BF531SBBC400
ADSP-BF531SBBCZ4002
ADSP-BF531SBST400
ADSP-BF531SBSTZ4002
ADSP-BF531WBBCZ-4A2,3
ADSP-BF531WBBZ-4A2,3
ADSP-BF531WBSTZ-4A2,3
ADSP-BF531WYBCZ-4A2,3
ADSP-BF531WYBZ-4A2,3
ADSP-BF532SBB400
ADSP-BF532SBBZ4002
ADSP-BF532SBBC400
ADSP-BF532SBBCZ4002
ADSP-BF532SBST400
ADSP-BF532SBSTZ400
ADSP-BF532WBBCZ-4A2
ADSP-BF532WBBZ-4A2,3
ADSP-BF532WBSTZ-4A2,3
ADSP-BF532WYBCZ-4A2,3
ADSP-BF532WYBZ-4A2,3
Temperature Speed Grade Operating Voltage
Range1
(Max)
(Nom)
Package Description
–40°C to +85°C 400 MHz
1.2 V internal, 1.8 V or 2.5 V or 3.3 V I/O 169-Ball Plastic Ball Grid Array
(PBGA)
–40°C to +85°C 400 MHz
1.2 V internal, 1.8 V or 2.5 V or 3.3 V I/O 169-Ball Plastic Ball Grid Array
(PBGA)
–40°C to +85°C 400 MHz
1.2 V internal,
160-Ball Chip Scale Package
1.8 V, 2.5 V or 3.3 V I/O
Ball Grid Array (CSP_BGA)
–40°C to +85°C 400 MHz
1.2 V internal,
160-Ball Chip Scale Package
1.8 V, 2.5 V or 3.3 V I/O
Ball Grid Array (CSP_BGA)
–40°C to +85°C 400 MHz
1.2 V internal, 1.8 V or 2.5 V or 3.3 V I/O 176-Lead Quad Flatpack
(LQFP)
–40°C to +85°C 400 MHz
1.2 V internal, 1.8 V or 2.5 V or 3.3 V I/O 176-Lead Quad Flatpack
(LQFP)
–40°C to +85°C 400 MHz
1.2 V internal, 3.0 V or 3.3 V I/O
160-Ball Chip Scale Package
Ball Grid Array (CSP_BGA)
–40°C to +85°C 400 MHz
1.2 V internal, 3.0 V or 3.3 V I/O
169-Ball Plastic Ball Grid Array
(PBGA)
–40°C to +85°C 400 MHz
1.2 V internal, 3.0 V or 3.3 V I/O
176-Lead Quad Flatpack
(LQFP)
–40°C to +105°C 400 MHz
1.2 V internal, 3.0 V or 3.3 V I/O
160-Ball Chip Scale Package
Ball Grid Array (CSP_BGA)
–40°C to +105°C 400 MHz
1.2 V internal, 3.0 V or 3.3 V I/O
169-Ball Plastic Ball Grid Array
(PBGA)
–40°C to +85°C 400 MHz
1.2 V internal, 1.8 V or 2.5 V or 3.3 V I/O 169-Ball Plastic Ball Grid Array
(PBGA)
–40°C to +85°C 400 MHz
1.2 V internal, 1.8 V or 2.5 V or 3.3 V I/O 169-Ball Plastic Ball Grid Array
(PBGA)
–40°C to +85°C 400 MHz
1.2 V internal,
160-Ball Chip Scale Package
1.8 V, 2.5 V or 3.3 V I/O
Ball Grid Array (CSP_BGA)
–40°C to +85°C 400 MHz
1.2 V internal,
160-Ball Chip Scale Package
1.8 V, 2.5 V or 3.3 V I/O
Ball Grid Array (CSP_BGA)
–40°C to +85°C 400 MHz
1.2 V internal, 1.8 V or 2.5 V or 3.3 V I/O 176-Lead Quad Flatpack
(LQFP)
–40°C to +85°C 400 MHz
1.2 V internal, 1.8 V or 2.5 V or 3.3 V I/O 176-Lead Quad Flatpack
(LQFP)
–40°C to +85°C 400 MHz
1.2 V internal, 3.0 V or 3.3 V I/O
160-Ball Chip Scale Package
Ball Grid Array (CSP_BGA)
–40°C to +85°C 400 MHz
1.2 V internal, 3.0 V or 3.3 V I/O
169-Ball Plastic Ball Grid Array
(PBGA)
–40°C to +85°C 400 MHz
1.2 V internal, 3.0 V or 3.3 V I/O
176-Lead Quad Flatpack
(LQFP)
–40°C to +105°C 400 MHz
1.2 V internal, 3.0 V or 3.3 V I/O
160-Ball Chip Scale Package
Ball Grid Array (CSP_BGA)
–40°C to +105°C 400 MHz
1.2 V internal, 3.0 V or 3.3 V I/O
169-Ball Plastic Ball Grid Array
(PBGA)
Rev. E |
Page 59 of 60 |
July 2007
Package
Option
B-169
B-169
BC-160-2
BC-160-2
ST-176-1
ST-176-1
BC-160-2
B-169
ST-176-1
BC-160-2
B-169
B-169
B-169
BC-160-2
BC-160-2
ST-176-1
ST-176-1
BC-160-2
B-169
ST-176-1
BC-160-2
B-169
ADSP-BF531/ADSP-BF532/ADSP-BF533
Model
ADSP-BF533SBB500
ADSP-BF533SBBZ5002
ADSP-BF533SBBC500
ADSP-BF533SBBCZ5002
ADSP-BF533SBBC-5V
ADSP-BF533SBBCZ-5V2
ADSP-BF533SBBCZ4002
ADSP-BF533SBST400
ADSP-BF533SBSTZ4002
ADSP-BF533SKBC-6V
ADSP-BF533SKBCZ-6V2
ADSP-BF533WBBCZ-5A2,3
ADSP-BF533WBBZ-5A2,3
ADSP-BF533WYBCZ-4A2,3
ADSP-BF533WYBZ-4A2,3
Temperature Speed Grade Operating Voltage
Range1
(Max)
(Nom)
Package Description
–40°C to +85°C 500 MHz
1.2 V Internal, 1.8 V or 2.5 V or 3.3 V I/O 169-Ball Plastic Ball Grid Array
(PBGA)
–40°C to +85°C 500 MHz
1.2 V Internal, 1.8 V or 2.5 V or 3.3 V I/O 169-Ball Plastic Ball Grid Array
(PBGA)
–40°C to +85°C 500 MHz
1.2 V Internal
160-Ball Chip Scale Package
1.8 V, 2.5 V or 3.3 V I/O
Ball Grid Array (CSP_BGA)
–40°C to +85°C 500 MHz
1.2 V Internal
160-Ball Chip Scale Package
1.8 V, 2.5 V or 3.3 V I/O
Ball Grid Array (CSP_BGA)
–40°C to +85°C 533 MHz
1.25 V Internal
160-Ball Chip Scale Package
1.8 V, 2.5 V or 3.3 V I/O
Ball Grid Array (CSP_BGA)
–40°C to +85°C 533 MHz
1.2 V Internal
160-Ball Chip Scale Package
1.8 V, 2.5 V or 3.3 V I/O
Ball Grid Array (CSP_BGA)
–40°C to +85°C 400 MHz
1.25 V internal,
160-Ball Chip Scale Package
1.8 V, 2.5 V or 3.3 V I/O
Ball Grid Array (CSP_BGA)
–40°C to +85°C 400 MHz
1.2 V internal, 1.8 V or 2.5 V or 3.3 V I/O 176-Lead Quad Flatpack
(LQFP)
–40°C to +85°C 400 MHz
1.2 V internal, 1.8 V or 2.5 V or 3.3 V I/O 176-Lead Quad Flatpack
(LQFP)
0°C to +70°C
600 MHz
1.3 V Internal
160-Ball Chip Scale Package
1.8 V, 2.5 V or 3.3 V I/O
Ball Grid Array (CSP_BGA)
0°C to +70°C
600 MHz
1.3 V Internal
160-Ball Chip Scale Package
1.8 V, 2.5 V or 3.3 V I/O
Ball Grid Array (CSP_BGA)
–40°C to +85°C 500 MHz
1.2 V Internal, 3.0 V or 3.3 V I/O
160-Ball Chip Scale Package
Ball Grid Array (CSP_BGA)
–40°C to +85°C 500 MHz
1.2 V Internal, 3.0 V or 3.3 V I/O
169-Ball Plastic Ball Grid Array
(PBGA)
–40°C to +105°C 400 MHz
1.2 V internal, 3.0 V or 3.3 V I/O
160-Ball Chip Scale Package
Ball Grid Array (CSP_BGA)
–40°C to +105°C 400 MHz
1.2 V internal, 3.0 V or 3.3 V I/O
169-Ball Plastic Ball Grid Array
(PBGA)
1
Referenced temperature is ambient temperature.
Z = RoHS Compliant Part.
3
Automotive grade part.
2
©2007 Analog Devices, Inc. All rights reserved. Trademarks and
registered trademarks are the property of their respective owners.
D03728-0-7/07(E)
Rev. E |
Page 60 of 60 |
July 2007
Package
Option
B-169
B-169
BC-160-2
BC-160-2
BC-160-2
BC-160-2
BC-160-2
ST-176-1
ST-176-1
BC-160-2
BC-160-2
BC-160-2
B-169
BC-160-2
B-169
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