HSPICE Simulation and Analysis User Guide

HSPICE Simulation and Analysis User Guide
HSPICE® Simulation and
Analysis User Guide
Version X-2005.09, September 2005
Copyright Notice and Proprietary Information
Copyright  2005 Synopsys, Inc. All rights reserved. This software and documentation contain confidential and proprietary
information that is the property of Synopsys, Inc. The software and documentation are furnished under a license agreement and
may be used or copied only in accordance with the terms of the license agreement. No part of the software and documentation may
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__________________________________________ and its employees. This is copy number __________.”
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Disclosure to nationals of other countries contrary to United States law is prohibited. It is the reader’s responsibility to
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SYNOPSYS, INC., AND ITS LICENSORS MAKE NO WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, WITH
REGARD TO THIS MATERIAL, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
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Synopsys, AMPS, Arcadia, C Level Design, C2HDL, C2V, C2VHDL, Cadabra, Calaveras Algorithm, CATS, CRITIC,
CSim, Design Compiler, DesignPower, DesignWare, EPIC, Formality, HSIM, HSPICE, Hypermodel, iN-Phase, in-Sync,
Leda, MAST, Meta, Meta-Software, ModelTools, NanoSim, OpenVera, PathMill, Photolynx, Physical Compiler, PowerMill,
PrimeTime, RailMill, RapidScript, Saber, SiVL, SNUG, SolvNet, Superlog, System Compiler, Testify, TetraMAX, TimeMill,
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Dynamic-Macromodeling, Dynamic Model Switcher, ECL Compiler, ECO Compiler, EDAnavigator, Encore, Encore PQ,
Evaccess, ExpressModel, Floorplan Manager, Formal Model Checker, FoundryModel, FPGA Compiler II, FPGA Express,
Frame Compiler, Galaxy, Gatran, HANEX, HDL Advisor, HDL Compiler, Hercules, Hercules-Explorer, Hercules-II,
Hierarchical Optimization Technology, High Performance Option, HotPlace, HSIMplus, HSPICE-Link, iN-Tandem,
Integrator, Interactive Waveform Viewer, i-Virtual Stepper, Jupiter, Jupiter-DP, JupiterXT, JupiterXT-ASIC, JVXtreme,
Liberty, Libra-Passport, Library Compiler, Libra-Visa, Magellan, Mars, Mars-Rail, Mars-Xtalk, Medici, Metacapture,
Metacircuit, Metamanager, Metamixsim, Milkyway, ModelSource, Module Compiler, MS-3200, MS-3400, Nova Product
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Passport, Planet, Planet-PL, Planet-RTL, Polaris, Polaris-CBS, Polaris-MT, Power Compiler, PowerCODE, PowerGate,
ProFPGA, ProGen, Prospector, Protocol Compiler, PSMGen, Raphael, Raphael-NES, RoadRunner, RTL Analyzer,
Saturn, ScanBand, Schematic Compiler, Scirocco, Scirocco-i, Shadow Debugger, Silicon Blueprint, Silicon Early Access,
SinglePass-SoC, Smart Extraction, SmartLicense, SmartModel Library, Softwire, Source-Level Design, Star, Star-DC,
Star-MS, Star-MTB, Star-Power, Star-Rail, Star-RC, Star-RCXT, Star-Sim, Star-SimXT, Star-Time, Star-XP, SWIFT,
Taurus, TimeSlice, TimeTracker, Timing Annotator, TopoPlace, TopoRoute, Trace-On-Demand, True-Hspice,
TSUPREM-4, TymeWare, VCS Express, VCSi, Venus, Verification Portal, VFormal, VHDL Compiler, VHDL System
Simulator, VirSim, and VMC are trademarks of Synopsys, Inc.
Service Marks (SM)
MAP-in, SVP Café, and TAP-in are service marks of Synopsys, Inc.
SystemC is a trademark of the Open SystemC Initiative and is used under license.
ARM and AMBA are registered trademarks of ARM Limited.
All other product or company names may be trademarks of their respective owners.
Printed in the U.S.A.
HSPICE® Simulation and Analysis User Guide, X-2005.09
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HSPICE® Simulation and Analysis User Guide
X-2005.09
Contents
About This Manual xxiii
Inside This Manual. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
xxiii
The HSPICE Documentation Set. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
xxv
Searching Across the HSPICE Documentation Set. . . . . . . . . . . . . . . . . . . . .
xxvi
Other Related Publications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
xxvi
Conventions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
xxvii
Customer Support . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
xxviii
Accessing SolvNet xxviii
Contacting the Synopsys Technical Support Center xxviii
1.
2.
Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
1
HSPICE Varieties. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
2
Features. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3
HSPICE Features for Running Higher-Level Simulations . . . . . . . . . . . .
5
Simulation Structure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
6
Experimental Methods Supported by HSPICE . . . . . . . . . . . . . . . . . . . .
6
HSPICE Data Flow. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
7
Simulation Process Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
9
Setup and Simulation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
11
Setting Environment Variables . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
11
Setting License Variables. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
License Queuing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
11
12
Standard Input Files. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
13
Design and File Naming Conventions . . . . . . . . . . . . . . . . . . . . . . . . . . .
13
Output Configuration File . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
14
Initialization File . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
14
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Contents
iv
DC Operating Point Initial Conditions File). . . . . . . . . . . . . . . . . . . . . . . .
15
Input Netlist File . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
15
Library Input File . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
15
Analog Transition Data File . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
15
Standard Output Files . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
16
AC Analysis Results File . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
17
AC Analysis Measurement Reults File . . . . . . . . . . . . . . . . . . . . . . . . . . .
17
DC Analysis Results File . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
18
DC Analysis Measurement Results File. . . . . . . . . . . . . . . . . . . . . . . . . .
18
Digital Output File. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
18
FFT Analysis Graph Data File . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
18
Hardcopy Graph Data File . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
18
HBLSP Analysis Extraction Results File . . . . . . . . . . . . . . . . . . . . . . . . .
18
HBLSP Analysis Results File . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
19
HBLSP Analysis Print Information File. . . . . . . . . . . . . . . . . . . . . . . . . . .
19
Operating Point Information File. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
19
Operating Point Node Voltages File . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
19
Output Listing File . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
19
Output Status File . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
20
Output Tables . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
21
Subcircuit Cross-Listing File. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
21
Transient Analysis Measurement Results File . . . . . . . . . . . . . . . . . . . . .
21
Transient Analysis Results File . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
21
Starting HSPICE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
22
Redirecting Output . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
23
Running an HSPICE Simulation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
24
Interactive Simulation. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
26
Examples of Starting HSPICE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
26
Starting HSPICE RF . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
28
Improving Simulation Performance with Multithreading . . . . . . . . . . . . . . . . . .
29
Running HSPICE-MT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
29
Performance Improvement Estimations . . . . . . . . . . . . . . . . . . . . . . . . . .
30
Simulating in Client/Server Mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
30
Server. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
31
Client . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
31
Simulating with Stand-alone .MEASURE Calculations . . . . . . . . . . . . . . . . . .
33
HSPICE® Simulation and Analysis User Guide
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Input Netlist and Data Entry . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
35
Input Netlist File Guidelines . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
35
Input Line Format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
First Character . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
36
38
Delimiters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
38
Node Identifiers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
39
Instance Names . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
39
Hierarchy Paths . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
41
Numbers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
41
Parameters and Expressions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
42
Input Netlist File Structure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
43
Schematic Netlists . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
43
Input Netlist File Composition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
45
Title of Simulation. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
46
Comments and Line Continuation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
47
Element and Source Statements . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
48
Defining Subcircuits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
50
Node Naming Conventions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Using Wildcards on Node Names . . . . . . . . . . . . . . . . . . . . . . . . . .
50
51
Element, Instance, and Subcircuit Naming Conventions . . . . . . . . . . . . .
53
Subcircuit Node Names . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
53
Path Names of Subcircuit Nodes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
54
Abbreviated Subcircuit Node Names . . . . . . . . . . . . . . . . . . . . . . . . . . . .
55
Automatic Node Name Generation . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
55
Global Node Names. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
56
Circuit Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
56
Data-Driven Analysis . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
56
Library Calls and Definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Library Building Rules . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
57
57
Automatic Library Selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
57
Defining Parameters. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Predefined Analysis . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Measurement Parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
58
58
59
Altering Design Variables and Subcircuits . . . . . . . . . . . . . . . . . . . . . . . .
Using Multiple .ALTER Blocks . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
59
60
Connecting Nodes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
60
Deleting a Library . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
61
Ending a Netlist . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
61
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4.
vi
Condition-Controlled Netlists (IF-ELSE). . . . . . . . . . . . . . . . . . . . . . . . . .
61
Using Subcircuits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
63
Hierarchical Parameters. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
M (Multiply) Parameter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
S (Scale) Parameter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Using Hierarchical Parameters to Simplify Simulation . . . . . . . . . . .
64
64
65
65
Undefined Subcircuit Search . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
66
Subcircuit Call Statement Discrete Device Libraries. . . . . . . . . . . . . . . . . . . .
67
DDL Library Access . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
67
Vendor Libraries . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
68
Subcircuit Library Structure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
69
Elements . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
71
Passive Elements. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
71
Values for Elements . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
71
Resistor Elements in a HSPICE or HSPICE RF Netlist . . . . . . . . . . . . . .
Linear Resistors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Behavioral Resistors in HSPICE or HSPICE RF . . . . . . . . . . . . . . .
Frequency-Dependent Resistors . . . . . . . . . . . . . . . . . . . . . . . . . . .
Skin Effect Resistors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
72
74
75
76
77
Capacitors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Linear Capacitors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Frequency-Dependent Capacitors . . . . . . . . . . . . . . . . . . . . . . . . . .
Behavioral Capacitors in HSPICE or HSPICE RF . . . . . . . . . . . . . .
DC Block Capacitors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Charge-Conserved Capacitors. . . . . . . . . . . . . . . . . . . . . . . . . . . . .
77
80
81
83
83
84
Inductors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Mutual Inductors. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Ideal Transformer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Linear Inductors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Frequency-Dependent Inductors . . . . . . . . . . . . . . . . . . . . . . . . . . .
AC Choke Inductors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
85
88
90
92
93
94
Active Elements . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
95
Diode Element . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
95
Bipolar Junction Transistor (BJT) Element . . . . . . . . . . . . . . . . . . . . . . . .
97
JFETs and MESFETs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
100
MOSFETs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
102
Transmission Lines . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
105
W Element . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
105
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5.
W Element Statement . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
106
Lossless (T Element) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Ideal Transmission Line . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
110
112
Lossy (U Element) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
114
Frequency-Dependent Multi-Terminal S Element . . . . . . . . . . . . . . . . . .
115
Frequency Table Model . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
121
Group Delay Handler in Time Domain Analysis . . . . . . . . . . . . . . . . . . . .
121
Pre-Conditioning S Parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
122
IBIS Buffers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
123
Sources and Stimuli . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
125
Independent Source Elements. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
125
Source Element Conventions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
126
Independent Source Element. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
126
DC Sources . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
129
AC Sources . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
130
Transient Sources . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
130
Mixed Sources . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
130
Port Element . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
131
Independent Source Functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
135
Pulse Source Function . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
135
Sinusoidal Source Function . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
139
Exponential Source Function . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
142
Piecewise Linear (PWL) Source Function . . . . . . . . . . . . . . . . . . . . . . . .
General Form . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
MSINC and ASPEC Form . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
145
145
145
Data-Driven Piecewise Linear Source . . . . . . . . . . . . . . . . . . . . . . . . . . .
147
Single-Frequency FM Source Function . . . . . . . . . . . . . . . . . . . . . . . . . .
149
Amplitude Modulation Source Function . . . . . . . . . . . . . . . . . . . . . . . . . .
151
Pattern Source Function . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Nested-Structure Pattern Source . . . . . . . . . . . . . . . . . . . . . . . . . . .
Pattern-Command Driven Pattern Source . . . . . . . . . . . . . . . . . . . .
153
156
157
Pseudo Random-Bit Generator Source (PRBS Function) . . . . . . . . . . . .
Linear Feedback Shift Register . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Conventions for Feedback Tap Specification . . . . . . . . . . . . . . . . . .
PRBS Syntax . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
158
159
159
160
Voltage and Current Controlled Elements . . . . . . . . . . . . . . . . . . . . . . . . . . . .
162
Polynomial Functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
164
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One-Dimensional Function. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Two-Dimensional Function . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Three-Dimensional Function . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
164
165
166
Piecewise Linear Function . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
167
Power Sources. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
168
Independent Sources . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Outputs. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
168
171
Controlled Sources. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
171
Voltage-Dependent Voltage Sources — E Elements . . . . . . . . . . . . . . . . . . . .
171
Voltage-Controlled Voltage Source (VCVS) . . . . . . . . . . . . . . . . . . . . . . .
Linear . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Polynomial (POLY) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Piecewise Linear (PWL) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Multi-Input Gates . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Delay Element . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Laplace Transform . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Pole-Zero Function . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Frequency Response Table . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
172
172
172
172
172
172
173
174
175
Behavioral Voltage Source . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
176
Ideal Op-Amp . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
176
Ideal Transformer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
176
E Element Examples . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Ideal OpAmp . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Voltage Summer. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Polynomial Function . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Zero-Delay Inverter Gate . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Ideal Transformer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Voltage-Controlled Oscillator (VCO). . . . . . . . . . . . . . . . . . . . . . . . .
179
179
180
180
181
181
181
Using the E Element for AC Analysis . . . . . . . . . . . . . . . . . . . . . . . . . . . .
181
Current-Dependent Current Sources — F Elements . . . . . . . . . . . . . . . . . . . .
182
Current-Controlled Current Source (CCCS) Syntax. . . . . . . . . . . . . . . . .
Linear . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Polynomial (POLY) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Piecewise Linear (PWL) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Multi-Input Gates . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Delay Element . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
182
182
182
183
183
183
Voltage-Dependent Current Sources — G Elements. . . . . . . . . . . . . . . . . . . .
186
Voltage-Controlled Current Source (VCCS) . . . . . . . . . . . . . . . . . . . . . . .
Linear . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Polynomial (POLY) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Piecewise Linear (PWL) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
186
187
187
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Multi-Input Gate . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Delay Element . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Laplace Transform . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Pole-Zero Function . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Frequency Response Table . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
187
187
187
188
188
Behavioral Current Source (Noise Model) Syntax . . . . . . . . . . . . . . . . . .
188
Voltage-Controlled Resistor (VCR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Linear . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Polynomial (POLY) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Piecewise Linear (PWL) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Multi-Input Gates . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
188
188
189
189
189
Voltage-Controlled Capacitor (VCCAP) . . . . . . . . . . . . . . . . . . . . . . . . . .
NPWL Function . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
PPWL Function . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
189
190
190
G Element Examples . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Switch. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Switch-Level MOSFET . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Voltage-Controlled Capacitor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Zero-Delay Gate . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Delay Element . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Diode Equation. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Diode Breakdown . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Triodes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Behavioral Noise Model . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
193
193
193
193
194
194
194
194
195
195
Current-Dependent Voltage Sources — H Elements. . . . . . . . . . . . . . . . . . . .
195
Current-Controlled Voltage Source (CCVS) . . . . . . . . . . . . . . . . . . . . . . .
Linear . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Polynomial (POLY) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Piecewise Linear (PWL) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Multi-Input Gate . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Delay Element . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
195
195
196
196
196
196
H Element Examples . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
198
Digital and Mixed Mode Stimuli . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
199
U Element Digital Input Elements and Models. . . . . . . . . . . . . . . . . . . . .
General Form . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Model Syntax . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Digital-to-Analog Input Model Parameters . . . . . . . . . . . . . . . . . . . .
199
200
201
201
U Element Digital Outputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Model Syntax . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Analog-to-Digital Output Model Parameters. . . . . . . . . . . . . . . . . . .
203
203
204
Replacing Sources With Digital Inputs. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
206
Specifying a Digital Vector File . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
208
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Commands in a Digital Vector File . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
6.
x
209
Vector Patterns. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
209
Defining Tabular Data. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Input Stimuli . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Expected Output. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Verilog Value Format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Periodic Tabular Data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
209
210
211
212
213
Waveform Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
214
Modifying Waveform Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . .
214
Using the Context-Based Control Option . . . . . . . . . . . . . . . . . . . . . . . . .
215
Comment Lines and Line Continuations . . . . . . . . . . . . . . . . . . . . . . . . .
216
Parameter Usage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
First Group . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Second Group . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Third Group . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
216
216
217
217
Digital Vector File Example . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
218
Parameters and Functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
221
Using Parameters in Simulation (.PARAM) . . . . . . . . . . . . . . . . . . . . . . . . . . .
222
Defining Parameters. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
222
Assigning Parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Inline Parameter Assignments . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Parameters in Output . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
224
224
224
User-Defined Function Parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
225
Predefined Analysis Function. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
225
Measurement Parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
225
.PRINT|.PROBE|.PLOT|.GRAPH Parameters . . . . . . . . . . . . . . . . . . . . .
226
Multiply Parameter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
226
Using Algebraic Expressions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
226
Built-In Functions and Variables . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
227
Parameter Scoping and Passing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
232
Library Integrity . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
233
Reusing Cells . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
233
Creating Parameters in a Library . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
233
String Parameter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
236
Parameter Defaults and Inheritance. . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Parameter Passing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
237
238
Parameter Passing Solutions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
240
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7.
Simulation Output . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
241
Overview of Output Statements . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
241
Output Commands . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
241
Output Variables. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
243
Displaying Simulation Results . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
244
.PRINT Statement . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Statement Order. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
244
244
.PLOT Statement . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
245
.PROBE Statement . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
245
.GRAPH Statement . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
.MODEL Statement for .GRAPH . . . . . . . . . . . . . . . . . . . . . . . . . . .
246
246
Using Wildcards in PRINT, PROBE, PLOT, and GRAPH Statements . . .
Supported Wildcard Templates . . . . . . . . . . . . . . . . . . . . . . . . . . . .
247
248
Print Control Options . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Changing the File Descriptor Limit . . . . . . . . . . . . . . . . . . . . . . . . . .
249
249
Printing the Subcircuit Output . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
249
Selecting Simulation Output Parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
251
DC and Transient Output Variables . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Nodal Capacitance Output . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Nodal Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Current: Independent Voltage Sources . . . . . . . . . . . . . . . . . . . . . .
Current: Element Branches . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Current: Subcircuit Pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
251
252
252
252
253
256
AC Analysis Output Variables . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Nodal Capacitance Output . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Nodal Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Current: Independent Voltage Sources . . . . . . . . . . . . . . . . . . . . . .
Current: Element Branches . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Current: Subcircuit Pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Group Time Delay . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Network . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Noise and Distortion. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
260
261
262
263
264
264
265
265
266
Element Template Output. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
267
Specifying User-Defined Analysis (.MEASURE) . . . . . . . . . . . . . . . . . . . . . . .
268
.MEASURE Statement Order. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
269
.MEASURE Parameter Types . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
269
FIND and WHEN Functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
271
Equation Evaluation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
271
Average, RMS, MIN, MAX, INTEG, and PP . . . . . . . . . . . . . . . . . . . . . . .
271
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INTEGRAL Function . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
272
DERIVATIVE Function . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
272
ERROR Function . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Error Equations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
272
273
.SURGE Statement . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
274
.CHECK Statements . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
275
Setting Global Hi/Lo Levels . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
275
Slew, Rise, and Fall Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
276
Edge Timing Verification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
278
Setup and Hold Verification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
279
IR Drop Detection. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
281
DSPF Flow. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
282
How HSPICE RF Uses a DSPF File . . . . . . . . . . . . . . . . . . . . . . . . . . . .
284
SIM_DSPF_SCALER/SIM_DSPF_SCALEC . . . . . . . . . . . . . . . . . . . . . .
284
Selective DSPF Expansion . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
285
Multi-Threshold Selective DSPF Expansion . . . . . . . . . . . . . . . . . . . . . .
286
Sample DSPF Flow . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
287
Reusing Simulation Output as Input Stimuli. . . . . . . . . . . . . . . . . . . . . . . . . . .
287
Output Files . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
288
.POWER Statement . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
289
SIM_POWERSTART and SIM_POWERSTOP Options . . . . . . . . . . . . . .
290
SIM_POWERPOST Option . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
290
POWER_TOP Option. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
290
POWER_ANALYSIS Option . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
291
Output Format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
292
.POWERDC Statement . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
294
Output Format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
295
Element Template Listings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
296
Analog Compression . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
SIM_DELTAV (Voltage). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
SIM_DELTAI (Current) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
308
308
309
Tabulated Data Output . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
309
WDB Output Format. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
310
XP Output Format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
310
NW Output Format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
310
VCD Output Format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
311
Turbowave Output Format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
311
Undertow Output Format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
311
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Limiting Output Data Size in HSPICE RF . . . . . . . . . . . . . . . . . . . . . . . . . . . .
8.
311
SIM_POSTTOP Option . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
312
SIM_POSTSKIP Option . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
312
SIM_POSTAT Option . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
312
SIM_POSTDOWN Option . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
313
SIM_POSTSCOPE Option. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
313
Node Hierarchy . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
314
Initializing DC/Operating Point Analysis . . . . . . . . . . . . . . . . . . . . . . . . . . .
315
Simulation Flow . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
315
Initialization and Analysis. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
316
DC Initialization and Operating Point Calculation . . . . . . . . . . . . . . . . . . . . . .
319
.OP Statement — Operating Point . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Output. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
319
319
Element Statement IC Parameter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
320
Initial Conditions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
321
SAVE and LOAD Statements . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
.SAVE Statement . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
.LOAD Statement . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
321
322
323
.DC Statement—DC Sweeps. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
323
Other DC Analysis Statements . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
324
DC Initialization Control Options . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
324
Accuracy and Convergence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
325
Accuracy Tolerances . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
325
Accuracy Control Options . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
328
Autoconverge Process . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
DCON and GMINDC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
328
330
Reducing DC Errors. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
332
Shorted Element Nodes. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
334
Inserting Conductance, Using DCSTEP . . . . . . . . . . . . . . . . . . . . . . . . .
334
Floating-Point Overflow . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
335
Diagnosing Convergence Problems. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
335
Non-Convergence Diagnostic Table. . . . . . . . . . . . . . . . . . . . . . . . . . . . .
336
Traceback of Non-Convergence Source . . . . . . . . . . . . . . . . . . . . . . . . .
337
Solutions for Non-Convergent Circuits . . . . . . . . . . . . . . . . . . . . . . . . . . .
Poor Initial Conditions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
338
338
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9.
xiv
Inappropriate Model Parameters . . . . . . . . . . . . . . . . . . . . . . . . . . .
PN Junctions (Diodes, MOSFETs, BJTs). . . . . . . . . . . . . . . . . . . . .
339
341
Transient Analysis . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
343
Simulation Flow . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
343
Overview of Transient Analysis . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
344
Transient Analysis Output . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
346
Transient Analysis of an RC Network. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
347
Transient Analysis of an Inverter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
348
Using the .BIASCHK Statement. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
350
Data Checking Methods. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Limit and Noise Method . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Maximum Method. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Minimum Method . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Region Method . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
351
351
352
352
352
Transient Control Options . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
353
Matrix Manipulation Options . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
353
Simulation Speed and Accuracy . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
354
Simulation Speed . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
354
Simulation Accuracy. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Timestep Control for Accuracy . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Models and Accuracy . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Guidelines for Choosing Accuracy Options . . . . . . . . . . . . . . . . . . .
355
355
356
357
Linear Acceleration (SIM_LA Option) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
357
PACT Algorithm . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
358
PI Algorithm . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Specifying Maximum Resistance . . . . . . . . . . . . . . . . . . . . . . . . . . .
Specifying Minimum Capacitance . . . . . . . . . . . . . . . . . . . . . . . . . .
359
360
360
Other PACT Options (HSPICE RF) . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Specifying Error Tolerance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Specifying Upper Frequency . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Specifying Minimum Switching Time . . . . . . . . . . . . . . . . . . . . . . . .
Node Reduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
360
360
361
361
362
SIM_LA Options Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
362
Numerical Integration Algorithm Controls (HSPICE) . . . . . . . . . . . . . . . . . . . .
363
Gear and Trapezoidal Algorithms. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
363
Numerical Integration Algorithm Controls (HSPICE RF) . . . . . . . . . . . . . . . . .
366
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Selecting Timestep Control Algorithms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
366
Iteration Count Dynamic Timestep Algorithm. . . . . . . . . . . . . . . . . . . . . .
368
Local Truncation Error (LTE) Dynamic Timestep . . . . . . . . . . . . . . . . . . .
368
DVDT Dynamic Timestep Algorithm. . . . . . . . . . . . . . . . . . . . . . . . . . . . .
368
Timestep Controls in HSPICE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
370
Timestep Control in HSPICE RF . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
.OPTION SIM_ACCURACY . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
.OPTION METHOD . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
.OPTION MAXORD . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
.OPTION SIM_ORDER . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
.OPTION SIM_TG_THETA. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
.OPTION SIM_TRAP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
.OPTION PURETP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
.OPTION SIM_OSC_DETECT_TOL . . . . . . . . . . . . . . . . . . . . . . . .
Examples . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
371
371
372
373
373
373
373
373
373
374
Fourier Analysis . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Accuracy and DELMAX . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Fourier Equation. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
375
376
376
10. AC Sweep and Small Signal Analysis . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
379
Using the .AC Statement . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
379
.AC Control Options . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
380
AC Small Signal Analysis. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
380
AC Analysis of an RC Network . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
382
Other AC Analysis Statements . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
385
Using .DISTO for Small-Signal Distortion Analysis . . . . . . . . . . . . . . . . .
385
Using .NOISE for Small-Signal Noise Analysis . . . . . . . . . . . . . . . . . . . .
385
Using .SAMPLE for Noise Folding Analysis . . . . . . . . . . . . . . . . . . . . . . .
387
11. Linear Network Parameter Analysis. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
389
.LIN Analysis . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
389
Identifying Ports with the Port Element . . . . . . . . . . . . . . . . . . . . . . . . . .
390
Using the P (Port) Element for Mixed-Mode Measurement . . . . . . . . . . .
394
.LIN Input Syntax . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
395
.LIN Output Syntax. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
PARAM Definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
TYPE Definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
395
396
398
Multi-Port Scattering (S) Parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . .
398
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Two-Port Transfer and Noise Calculations . . . . . . . . . . . . . . . . . . . . . . . .
Equivalent Input Noise Voltage and Current. . . . . . . . . . . . . . . . . . .
Equivalent Noise Resistance and Conductance . . . . . . . . . . . . . . .
Noise Correlation Impedance and Admittance. . . . . . . . . . . . . . . . .
Optimum Matching for Noise . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Noise Figure and Minimum Noise Figure . . . . . . . . . . . . . . . . . . . . .
Associated Gain . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Output Format for Group Delay in .sc* Files. . . . . . . . . . . . . . . . . . .
Output Format for Two-Port Noise Parameters in .sc* Files . . . . . . .
399
400
400
400
401
401
401
402
402
Noise Parameters. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
403
Hybrid (H) Parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
404
Group Delay . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
404
RF Measurements From .LIN . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
405
Impedance Characterizations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
406
Stability Measurements . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
406
Gain Measurements. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
406
Matching for Optimal Gain . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
406
Noise Measurements . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
407
Two-Port Transfer and Noise Measurements . . . . . . . . . . . . . . . . . . . . . .
407
Output Format for Two-Port Noise Parameters in .sc* Files. . . . . . . . . . .
VSWR. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
ZIN(i) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
YIN(i) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
K_STABILITY_FACTOR (Rollett Stability Factor) . . . . . . . . . . . . . . .
MU_STABILITY_FACTOR (Edwards-Sinsky Stability Factor) . . . . .
Maximum Available Power Gain—G_MAX. . . . . . . . . . . . . . . . . . . .
Maximum Stable Gain - G_MSG . . . . . . . . . . . . . . . . . . . . . . . . . . .
Maximum Unilateral Transducer Power Gain —G_TUMAX . . . . . . .
Unilateral Power Gain—GU . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Simultaneous Conjugate Match for G_MAX. . . . . . . . . . . . . . . . . . .
Equivalent Input Noise Voltage and Current—IN2, VN2, RHON . . .
Equivalent Noise Resistance and Conductance—RN, GN . . . . . . .
Noise Correlation Impedance and Admittance—ZCOR, YCOR. . . .
ZOPT, YOPT, GAMMA_OPT – Optimum Matching for Noise. . . . . .
Noise Figure and Noise Figure Minimum—NF, NFMIN . . . . . . . . . .
Associated Gain—G_As. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
408
408
408
409
409
409
409
410
410
411
411
412
413
413
413
414
415
Extracting Mixed-Mode Scattering (S) Parameters . . . . . . . . . . . . . . . . . . . . .
415
Defaults . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
416
Output File Formats . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
417
Two-Port Parameter Measurement . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
417
Output Format and Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
418
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Contents
Features Supported . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
419
Prerequisites and Limitations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
419
Reported Statistics for the Performance Log (HSPICE RF Only) . . . . . .
419
Errors and Warnings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
420
.NET Parameter Analysis. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
420
Network Analysis Example: Bipolar Transistor. . . . . . . . . . . . . . . . . . . . .
423
.NET Parameter Analysis . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
424
Bandpass Netlist: Network Analysis Results . . . . . . . . . . . . . . . . . . . . . .
425
References. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
426
12. Using HSPICE with Verilog-A . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
429
Getting Started. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
430
Example: JFET Compact Device Model . . . . . . . . . . . . . . . . . . . . . . . . .
430
Introduction to Verilog-A. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
433
Verilog-A Module Template . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
433
Data Types . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
434
Analog Operators and Filters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
434
Mathematical Functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
436
Transcendental Functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
437
AC Analysis Stimuli . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
438
Noise Functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
439
Analog Events . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
439
Timestep and Simulator Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
440
System Tasks and I/O Functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
441
Simulator Environment Functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
442
Module Hierarchy . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
442
Simulation with Verilog-A Modules. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
443
Loading Verilog-A Devices . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
443
HSPICE .hdl Netlist Command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
444
HSPICE -hdl Command-line Option. . . . . . . . . . . . . . . . . . . . . . . . . . . . .
444
Verilog-A Search Path . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
444
HSPICE -vamodel Command-line Option . . . . . . . . . . . . . . . . . . . . . . . .
445
Verilog-A File Loading Considerations . . . . . . . . . . . . . . . . . . . . . . . . . . .
446
Verilog-A Behavior in a .ALTER Analysis . . . . . . . . . . . . . . . . . . . . . . . . .
446
Instantiating Verilog-A Devices . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
447
Using Model Cards with Verilog-A Modules . . . . . . . . . . . . . . . . . . . . . . .
448
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xviii
Restrictions on Verilog-A Module Names. . . . . . . . . . . . . . . . . . . . . . . . .
449
Overriding Subcircuits with Verilog-A Modules . . . . . . . . . . . . . . . . . . . .
Netlist Option . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Command-line Option . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
450
450
451
Disabling .OPTION vamodel with .OPTION spmodel . . . . . . . . . . . . . . .
452
Using Vector Buses or "Ports" . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
453
Using Integer Parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
453
Implicit Parameter M Support. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
453
Module and Parameter Name Case Sensitivity . . . . . . . . . . . . . . . . . . . . . . . .
454
Module Names . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
454
Module Parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
454
Output Simulation Data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
455
V() and I() Access Functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
455
Output Bus Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
456
Output Internal Module Variables. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
457
Output Module Parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
458
Verilog-A Device Output Simulation Data. . . . . . . . . . . . . . . . . . . . . . . . .
458
Using Wildcards in Verilog-A . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
459
Port Probing and Branch Current Reporting Conventions . . . . . . . . . . . .
460
Unsupported Output Function Features. . . . . . . . . . . . . . . . . . . . . . . . . .
460
Using the Stand-alone Compiler . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
460
Setting Environment Option for HSPICE Verilog-A Compiler. . . . . . . . . . . . . .
461
The Compiled Model Library Cache . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
461
Cache Location . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
462
Deleting the Cache. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
462
Unsupported Language Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
463
Known Limitations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
467
analysis() Function Behavior . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
467
13. DC Mismatch Analysis . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
469
Mismatch . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
469
Simulation Methods for Variability . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
469
DCmatch Analysis . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
470
Input Syntax . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
471
DCmatch Definition Block . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Input Syntax . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
472
472
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Accessing Instance Parameters in Expressions for Sigma . . . . . . .
473
DCmatch Table Output. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
473
Output From .PROBE and .MEASURE Commands . . . . . . . . . . . . . . . .
Syntax for .PROBE Command . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Syntax for .MEASURE Command . . . . . . . . . . . . . . . . . . . . . . . . . .
475
475
475
Practical Considerations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
DCmatch Variability as a Function of Device Geometry. . . . . . . . . .
Parameter Traceability . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
476
476
477
Example . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
477
Reference List . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
478
14. Statistical Analysis and Optimization . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
479
Analytical Model Types . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
480
Simulating Circuit and Model Temperatures . . . . . . . . . . . . . . . . . . . . . . . . . .
481
Temperature Analysis. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
483
.TEMP Statement. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
484
Worst Case Analysis . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
484
Model Skew Parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Using Skew Parameters in HSPICE . . . . . . . . . . . . . . . . . . . . . . . . .
Skew File Interface to Device Models. . . . . . . . . . . . . . . . . . . . . . . .
484
486
488
Monte Carlo Analysis . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
489
Functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Gaussian Parameter Distribution . . . . . . . . . . . . . . . . . . . . . . . . . . .
Uniform Parameter Distribution . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Random Limit Parameter Distribution. . . . . . . . . . . . . . . . . . . . . . . .
489
489
489
490
Monte Carlo Setup . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
490
Monte Carlo Output . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
492
.PARAM Distribution Function . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
492
Monte Carlo Parameter Distribution . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
494
Monte Carlo Examples. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Gaussian, Uniform, and Limit Functions . . . . . . . . . . . . . . . . . . . . .
Major and Minor Distribution . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
RC Time Constant . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Switched Capacitor Filter Design . . . . . . . . . . . . . . . . . . . . . . . . . . .
495
495
497
498
499
Worst Case and Monte Carlo Sweep Example . . . . . . . . . . . . . . . . . . . . . . . .
502
HSPICE Input File . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
502
Transient Sigma Sweep Results . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
503
Monte Carlo Results . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
504
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Optimization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
xx
510
Optimization Control. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
511
Simulation Accuracy. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
512
Curve Fit Optimization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
512
Goal Optimization. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
513
Timing Analysis . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
513
Optimization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Optimizing Analysis (.DC, .TRAN, .AC) . . . . . . . . . . . . . . . . . . . . . .
514
515
Optimization Examples . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
515
MOS Level 3 Model DC Optimization. . . . . . . . . . . . . . . . . . . . . . . . . . . .
Input Netlist File for Level 3 Model DC Optimization . . . . . . . . . . . .
516
516
MOS Level 13 Model DC Optimization. . . . . . . . . . . . . . . . . . . . . . . . . . .
DC Optimization Input Netlist File for Level 13 Model . . . . . . . . . . .
518
519
RC Network Optimization. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Optimization Results . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Optimized Parameters OPTRC . . . . . . . . . . . . . . . . . . . . . . . . . . . .
520
520
522
Optimizing CMOS Tristate Buffer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Input Netlist File to Optimize a CMOS Tristate Buffer. . . . . . . . . . . .
523
524
BJT S Parameters Optimization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Key HSPICE Features Used . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Input Netlist File for Optimizing BJT S Parameters . . . . . . . . . . . . .
525
526
526
BJT Model DC Optimization. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
BJT Model DC Optimization Input Netlist File . . . . . . . . . . . . . . . . .
527
528
Optimizing GaAsFET Model DC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
GaAsFET Model DC Optimization Input Netlist File. . . . . . . . . . . . .
529
530
Optimizing MOS Op-amp . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
MOS Op-amp Optimization Input Netlist File . . . . . . . . . . . . . . . . . .
530
531
15. Running Demonstration Files. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
533
Using the Demo Directory Tree . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
534
Two-Bit Adder Demo . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
535
One-Bit Subcircuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
535
MOS Two-Bit Adder Input File . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
536
MOS I-V and C-V Plotting Demo . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
536
Plotting Variables . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
537
MOS I-V and C-V Plot Example Input File . . . . . . . . . . . . . . . . . . . . . . . .
541
CMOS Output Driver Demo . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
541
Strategy . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
542
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CMOS Output Driver Example Input File . . . . . . . . . . . . . . . . . . . . . . . . .
A.
546
Temperature Coefficients Demo . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
546
Input File for Optimized Temperature Coefficients . . . . . . . . . . . . . . . . . .
547
Optimization Section . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
548
Simulating Electrical Measurements . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
548
T2N2222 Optimization Example Input File. . . . . . . . . . . . . . . . . . . . . . . .
549
Modeling Wide-Channel MOS Transistors . . . . . . . . . . . . . . . . . . . . . . . . . . . .
549
Demonstration Input Files . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
552
Full Simulation Examples . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
571
Simulation Example Using AvanWaves . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
571
Input Netlist and Circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
571
Execution and Output Files . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Example.ic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Example.lis . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Example.st0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
573
574
574
577
Simulation Graphical Output in AvanWaves. . . . . . . . . . . . . . . . . . . . . . .
580
Simulation Example Using Cosmos-Scope . . . . . . . . . . . . . . . . . . . . . . . . . . .
587
Input Netlist and Circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
587
Execution and Output Files . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
589
View HSPICE Results in Cosmos-Scope. . . . . . . . . . . . . . . . . . . . . . . . .
Viewing HSPICE Transient Analysis Waveforms . . . . . . . . . . . . . . .
Viewing HSPICE AC Analysis Waveforms . . . . . . . . . . . . . . . . . . . .
Viewing HSPICE DC Analysis Waveforms . . . . . . . . . . . . . . . . . . . .
590
590
592
594
Index . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
597
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Contents
xxii
HSPICE® Simulation and Analysis User Guide
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About This Manual
This manual describes how to use HSPICE to simulate and analyze your circuit
designs.
Inside This Manual
This manual contains the chapters described below. For descriptions of the
other manuals in the HSPICE documentation set, see the next section, “The
HSPICE Documentation Set.”
Chapter
Description
Chapter 1, Overview
Describes HSPICE features and the simulation
process.
Chapter 2, Setup and
Simulation
Describes the environment variables, standard I/O
files, invocation commands, and simulation modes.
Chapter 3, Input Netlist and
Data Entry
Describes the input netlist file and methods of
entering data.
Chapter 4, Elements
Describes the syntax for the basic elements of a
circuit netlist in HSPICE or HSPICE RF.
Chapter 5, Sources and
Stimuli
Describes element and model statements for
independent sources, dependent sources,
analog-to-digital elements, and digital-to-analog
elements.
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About This Manual
Inside This Manual
xxiv
Chapter
Description
Chapter 6, Parameters and
Functions
Describes how to use parameters within an
HSPICE netlist.
Chapter 7, Simulation
Output
Describes how to use output format statements
and variables to display steady state, frequency,
and time domain simulation results.
Chapter 8, Initializing DC/
Operating Point Analysis
Describes DC initialization and operating point
analysis.
Chapter 9, Transient
Analysis
Describes how to use transient analysis to
compute the circuit solution.
Chapter 10, AC Sweep and
Small Signal Analysis
Describes how to perform AC sweep and small
signal analysis.
Chapter 11, Linear Network
Parameter Analysis
Describes how to perform an AC sweep to extract
small-signal linear network parameters.
Chapter 12, Using HSPICE
with Verilog-A
Describes how to use Verilog-A in HSPICE
simulations.
Chapter 13, DC Mismatch
Analysis
Describes the use of DCmatch analysis.
Chapter 14, Statistical
Analysis and Optimization
Describes how to use statistical analysis and
optimization in HSPICE to analyze and optimize
electrical yield.
Chapter 15, Running
Demonstration Files
Contains examples of basic file construction
techniques, advanced features, and simulation
tricks. Lists and describes several HSPICE and
HSPICE RF input files.
Appendix A, Full Simulation
Examples
Contains information and sample input netlists for
two full simulation examples.
HSPICE® Simulation and Analysis User Guide
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About This Manual
The HSPICE Documentation Set
The HSPICE Documentation Set
This manual is a part of the HSPICE documentation set, which includes the
following manuals:
Manual
Description
HSPICE Simulation and
Analysis User Guide
Describes how to use HSPICE to simulate and
analyze your circuit designs. This is the main
HSPICE user guide.
HSPICE Signal Integrity
Guide
Describes how to use HSPICE to maintain signal
integrity in your chip design.
HSPICE Applications
Manual
Provides application examples and additional
HSPICE user information.
HSPICE Command
Reference
Provides reference information for HSPICE
commands.
HPSPICE Elements and
Device Models Manual
Describes standard models you can use when
simulating your circuit designs in HSPICE,
including passive devices, diodes, JFET and
MESFET devices, and BJT devices.
HPSPICE MOSFET Models
Manual
Describes standard MOSFET models you can
use when simulating your circuit designs in
HSPICE.
HSPICE RF Manual
Describes a special set of analysis and design
capabilities added to HSPICE to support RF and
high-speed circuit design.
AvanWaves User Guide
Describes the AvanWaves tool, which you can
use to display waveforms generated during
HSPICE circuit design simulation.
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About This Manual
Searching Across the HSPICE Documentation Set
Manual
Description
HSPICE Quick Reference
Guide
Provides key reference information for using
HSPICE, including syntax and descriptions for
commands, options, parameters, elements, and
more.
HSPICE Device Models
Quick Reference Guide
Provides key reference information for using
HSPICE device models, including passive
devices, diodes, JFET and MESFET devices,
and BJT devices.
Searching Across the HSPICE Documentation Set
Synopsys includes an index with your HSPICE documentation that lets you
search the entire HSPICE documentation set for a particular topic or keyword.
In a single operation, you can instantly generate a list of hits that are
hyperlinked to the occurrences of your search term. For information on how to
perform searches across multiple PDF documents, see the HSPICE release
notes (available on SolvNet at http://solvnet.synopsys.com) or the Adobe
Reader online help.
Note: To use this feature, the HSPICE documentation files, the Index directory,
and the index.pdx file must reside in the same directory. (This is the default
installation for Synopsys documentation.) Also, Adobe Acrobat must be
invoked as a standalone application rather than as a plug-in to your web
browser.
Other Related Publications
For additional information about HSPICE, see:
xxvi
■
The HSPICE release notes, available on SolvNet (see Accessing SolvNet
on page xxviii)
■
Documentation on the Web, which provides HTML and PDF documents and
is available through SolvNet at http://solvnet.synopsys.com
■
The Synopsys MediaDocs Shop, from which you can order printed copies
of Synopsys documents, at http://mediadocs.synopsys.com
HSPICE® Simulation and Analysis User Guide
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About This Manual
Conventions
You might also want to refer to the documentation for the following related
Synopsys products:
■
CosmosScope
■
Aurora
■
Raphael
■
VCS
Conventions
The following conventions are used in Synopsys documentation:
Convention
Description
Courier
Indicates command syntax.
Italic
Indicates a user-defined value, such as object_name.
Bold
Indicates user input—text you type verbatim—in syntax and
examples.
[]
Denotes optional parameters, such as
write_file [-f filename]
...
Indicates that a parameter can be repeated as many times
as necessary:
pin1 [pin2 ... pinN]
|
Indicates a choice among alternatives, such as
low | medium | high
\
Indicates a continuation of a command line.
/
Indicates levels of directory structure.
Edit > Copy
Indicates a path to a menu command, such as opening the
Edit menu and choosing Copy.
Control-c
Indicates a keyboard combination, such as holding down
the Control key and pressing c.
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About This Manual
Customer Support
Customer Support
Customer support is available through SolvNet online customer support and
through contacting the Synopsys Technical Support Center.
Accessing SolvNet
SolvNet includes an electronic knowledge base of technical articles and
answers to frequently asked questions about Synopsys tools. SolvNet also
gives you access to a wide range of Synopsys online services, which include
downloading software, viewing Documentation on the Web, and entering a call
to the Support Center.
To access SolvNet:
1. Go to the SolvNet Web page at http://solvnet.synopsys.com.
2. If prompted, enter your user name and password. (If you do not have a
Synopsys user name and password, follow the instructions to register with
SolvNet.)
If you need help using SolvNet, click SolvNet Help in the Support Resources
section.
Contacting the Synopsys Technical Support Center
If you have problems, questions, or suggestions, you can contact the Synopsys
Technical Support Center in the following ways:
xxviii
■
Open a call to your local support center from the Web by going to
http://solvnet.synopsys.com (Synopsys user name and password required),
then clicking “Enter a Call to the Support Center.”
■
Send an e-mail message to your local support center.
•
E-mail [email protected] from within North America.
•
Find other local support center e-mail addresses at
http://www.synopsys.com/support/support_ctr.
HSPICE® Simulation and Analysis User Guide
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About This Manual
Customer Support
■
Telephone your local support center.
•
Call (800) 245-8005 from within the continental United States.
•
Call (650) 584-4200 from Canada.
•
Find other local support center telephone numbers at
http://www.synopsys.com/support/support_ctr.
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Customer Support
xxx
HSPICE® Simulation and Analysis User Guide
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1
Overview
1
Describes HSPICE features and the simulation process.
Synopsys HSPICE is an optimizing analog circuit simulator. You can use it to
simulate electrical circuits in steady-state, transient, and frequency domains.
HSPICE or HSPICE RF is unequalled for fast, accurate circuit and behavioral
simulation. It facilitates circuit-level analysis of performance and yield, by using
Monte Carlo, worst-case, parametric sweep, and data-table sweep analyses,
and employs the most reliable automatic-convergence capability (see
Figure 1).
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1: Overview
HSPICE Varieties
Figure 1
Synopsys HSPICE or HSPICE RF Design Features
Transmission Line
Signal Integrity
Monte Carlo
Worst-Case Analysis
HSPICE or
HSPICE RF
Photocurrent/
Radiation Effects
Incremental
Optimization
Circuit Cell
Optimization
Cell
Characterization
AC, DC,
Transient
HSPICE or HSPICE RF forms the cornerstone of a suite of Synopsys tools and
services that allows accurate calibration of logic and circuit model libraries to
actual silicon performance.
The size of the circuits that HSPICE or HSPICE RF can simulate is limited only
by memory. As a 32-bit application, HSPICE can address a maximum of 2Gb or
4Gb of memory, depending on your system.
For a description of commands that you can include in your HSPICE netlist,
see the HSPICE Command Reference.
HSPICE Varieties
Synopsys HSPICE is available in two varieties:
■
HSPICE
■
HSPICE RF
Like traditional SPICE simulators, HSPICE is Fortran-based, but it is faster and
has more capabilities than typical SPICE simulators. HSPICE accurately
simulates, analyzes, and optimizes circuits, from DC, to microwave frequencies
that are greater than 100 GHz. HSPICE is ideal for cell design and process
modeling. It is also the tool of choice for signal-integrity and transmission-line
analysis.
HSPICE RF is a newer, C++ version of the traditional Fortran-based HSPICE.
Many (but not all) HSPICE simulation capabilities have been implemented in
2
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Features
HSPICE RF, and HSPICE RF offers some new capabilities that are not in
available in traditional HSPICE.
HSPICE RF usually produces results at the desired level of accuracy in a
shorter time than HSPICE requires for the same level of accuracy. HSPICE RF
can also perform HSPICE simulations of Radio Frequency (RF) devices, which
HSPICE does not support.
This guide describes all of the features that HSPICE supports. HSPICE RF
also supports some (but not all) of these features. For descriptions of features
that HSPICE RF supports, but HSPICE does not, see the HSPICE RF User
Guide. The HSPICE RF User Guide also indicates which features of HSPICE
are supported in HSPICE RF.
Features
Synopsys HSPICE or HSPICE RF is compatible with most SPICE variations,
and has the following additional features:
■
Superior convergence
■
Accurate modeling, including many foundry models
■
Hierarchical node naming and reference
■
Circuit optimization for models and cells, with incremental or simultaneous
multiparameter optimizations in AC, DC, and transient simulations
■
Interpreted Monte Carlo and worst-case design support
■
Input, output, and behavioral algebraics for cells with parameters
■
Cell characterization tools, to characterize standard cell libraries
■
Geometric lossy-coupled transmission lines for PCB, multi-chip, package,
and IC technologies
■
Discrete component, pin, package, and vendor IC libraries
■
Interactive graphing and analysis of multiple simulation waveforms by using
with AvanWaves and CosmosScope
■
Flexible license manager that allocates licenses intelligently based on run
status and user-specified job priorities you specify.
If you suspend a simulation job, the load sharing facility (LSF) license
manager signals HSPICE to release that job’s license. This frees the license
for another simulation job, or so the stopped job can reclaim the license and
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1: Overview
Features
resume. You can also prioritize simulation jobs you submit; LSF
automatically suspends low-priority simulation jobs to run high-priority jobs.
When the high-priority job completes, LSF releases the license back to the
lower-priority job, which resumes from where it was suspended.
■
A number of circuit analysis types (see Figure 2) and device modeling
technologies (see Figure 3).
Figure 2
Synopsys HSPICE or HSPICE RF Circuit Analysis Types
Parametric
Operating
Point
Pole-Zero
Monte Carlo
Optimization
HSPICE or
HSPICE RF
Monte Carlo
Data Driven
Frequency
Transient
S-parameter
Monte Carlo
analysis
supported in
Synopsys HSPICE
only
4
Optimization
Monte Carlo
Data Driven
Monte Carlo
Optimization
Mixed
AC/Transient
Data Driven
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Features
Figure 3
Synopsys HSPICE Modeling Technologies
SPICE
40+ Industrial and
Academic Models
Magnetics
MOS
BJT
IBIS
Lossy
Transmission
Lines
Mixed Signal
Device Models
Diode
SOI
Common
Model
Interface
JFET/
GaAsFET
Tunnel
Diode
HSPICE Features for Running Higher-Level Simulations
Simulations at the integrated circuit level and at the system level require careful
planning of the organization and interaction between transistor models and
subcircuits. Methods that worked for small circuits might have too many
limitations when applied to higher-level simulations.
You can use the following HSPICE or HSPICE RF features to organize how
simulation circuits and models run:
■
Explicit include files – .INCLUDE statement.
■
Implicit include files – .OPTION SEARCH = ‘lib_directory’ (HSPICE
only).
■
Algebraics and parameters for devices and models – .PARAM statement.
■
Parameter library files – .LIB statement.
■
Automatic model selector – LMIN, LMAX, WMIN, and WMAX model
parameters.
■
Parameter sweep – SWEEP analysis statement.
■
Statistical analysis – SWEEP MONTE analysis statement (HSPICE only).
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Simulation Structure
■
Multiple alternative – .ALTER statement (HSPICE only).
■
Automatic measurements – .MEASURE statement.
■
Condition-controlled netlists (IF-ELSEIF-ELSE-ENDIF statements).
Simulation Structure
Experimental Methods Supported by HSPICE
Typically, you use experiments to analyze and verify complex designs. These
experiments can be simple sweeps, more complex Monte Carlo and
optimization analyses (HSPICE only), or setup and hold violation analyses of
DC, AC, and transient conditions.
Figure 4
Simulation Program Structure
Simulation Experiment
Single point
Analysis
Initial
Conditions
Optimization
Circuit
Transient
Sweep
Results
Analysis
DC
Timing
Violations
Statistical
Worst Case
Library
Stimuli
AC
Options
For each simulation experiment, you must specify tolerances and limits to
achieve the desired goals, such as optimizing or centering a design. Common
factors for each experiment are:
6
■
process
■
voltage
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Simulation Structure
■
temperature
■
parasitics
HSPICE or HSPICE RF supports two experimental methods:
■
Single point – a simple procedure that produces a single result, or a single
set of output data.
■
Multipoint – performs an analysis (single point) sweep for each value in an
outer loop (multipoint) sweep.
The following are examples of multipoint experiments:
■
Process variation – Monte Carlo or worst-case model parameter variation
(HSPICE only).
■
Element variation – Monte Carlo (HSPICE only) or element parameter
sweeps.
■
Voltage variation – VCC, VDD, or substrate supply variation.
■
Temperature variation – design temperature sensitivity.
■
Timing analysis – basic timing, jitter, and signal integrity analysis.
■
Parameter optimization – balancing complex constraints, such as speed
versus power, or frequency versus slew rate versus offset (analog circuits).
HSPICE Data Flow
HSPICE or HSPICE RF accepts input and simulation control information from
several different sources. They can output results in a number of convenient
forms for review and analysis. Figure 5 shows the overall data flow.
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1: Overview
Simulation Structure
Figure 5
Overview of Data Flow
hspice.ini
Command line input
(initialization file)
meta.cfg
(output
configuration file)
<design>.sp
(netlist input file)
Models and
device libraries
command.inc
(command include
file – optional)
HSPICE
or
HSPICE RF
(simulation)
<design>.tr#
(graph data
output file)
AvanWaves
(graph and
analysis)
Other output files:
<design>.lis
<design>.mt#
<design>.sw#
<design>.ms#
<design>.ac#
<design>.ma#
<design>.gr#
<design>.pa#
<design>.st#
<design>.ft#
<design>.a2d
Graphics
hardcopy file
Printer or
plotter
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Simulation Structure
1. To begin design entry and simulation, create an input netlist file.
Most schematic editors and netlisters support the SPICE or HSPICE
hierarchical format.
2. HSPICE or HSPICE RF executes the analyses specified in the input file.
3. HSPICE or HSPICE RF stores the simulation results requested in either an
output listing file or (if you specified .OPTION POST) a graph data file.
If you specified POST, HSPICE or HSPICE RF stores the circuit solution (in
either steady state, time, or frequency domain).
4. To view or plot the results for any nodal voltage or branch current, use a
high-resolution graphic output terminal or laser printer.
HSPICE provides a complete set of print and plot variables for viewing
analysis results. HSPICE RF supports some, but not all, HSPICE print
variables.
The HSPICE or HSPICE RF programs include a textual command line
interface. For example, to execute the program, enter the hspice or hspicext
command, the input file name, and the desired options. You can use the
command line at the prompt in a Unix shell, or a DOS command line, or (for
HSPICE only) click on an icon in a Windows environment.
You can specify whether the HSPICE or HSPICE RF program simulation output
appears in an output listing file, or in a graph data file (HSPICE only). HSPICE
or HSPICE RF creates standard output files to describe initial conditions (.ic
extension) and output status (.st0 extension). In addition, HSPICE or HSPICE
RF creates various output files, in response to user-defined input options—for
example, HSPICE creates a <design>.tr0 file, in response to a .TRAN
transient analysis statement.
The default waveform display tool for HSPICE is AvanWaves. AvanWaves
output display and analysis includes a graphical user interface. Use the mouse
to select options, and to execute commands, in the AvanWaves windows. Refer
to the AvanWaves User Guide for instructions about how to use AvanWaves.
The default waveform display tool for HSPICE RF is CosmosScope. See the
CosmosScope User Guide for instructions about how to use CosmosScope.
Simulation Process Overview
Figure 6 shows the HSPICE or HSPICE RF simulation process.
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1: Overview
Simulation Structure
Figure 6
Simulation Process
1. Invocation
2. Run script
3. Licensing
Select version
Select best architecture
Run HSPICE
Find license file in
LM_LICENSE_FILE
Get FLEXlm license token
4. Simulation
configuration
Read ~/meta.cfg or
Read <installdir>/meta.cfg
5. Design input
Read input file: demo.sp
Open temp. files in $tmpdir
Open output file
Read hspice.ini file
6. Library input
Read .INCLUDE statement files
Read .LIB
Read implicit include (.inc) files
7. Operating point
initialization
Read .ic file (optional)
Find operating point
Write .ic file (optional)
8. Multipoint analysis
Open measure data files .mt0
Initialize outer loop sweep
Set analysis temperature
9. Single point analysis
Open graph data file .tr0
Perform analysis sweep
10. Worst case .ALTER
11. Clean up
10
hspice -i demo.sp -o demo.lis -OR- hspicerf -a ckt.in ckt
Process library delete/add
Process parameter and
topology changes
Close all files
Release all tokens
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Setup and Simulation
2
Describes the environment variables, standard I/O files, invocation
commands, and simulation modes.
For descriptions of individual HSPICE commands mentioned in this chapter,
see the HSPICE Command Reference manual.
Setting Environment Variables
Before using HSPICE, you need to set these environment variables
■
LM_LICENSE_FILE—Specifies the path to the license file (required)
■
META_QUEUE—Enables HSPICE licenses to be queued
■
tmpdir (UNIX), TEMP or TMP (Windows)—Allows you to control the location
of the temporary files
Setting License Variables
HSPICE or HSPICE RF requires you to set the LM_LICENSE_FILE
environment variable. This variable specifies the full path to the license.dat
license file. Set the LM_LICENSE_FILE environment variable to point to the
HSPICE and HSPICE RF license file.
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Setting Environment Variables
For example, if your HSPICE RF license file is in
/usr/cad/hspicext/license.dat
And your HSPICE license file is in
/usr/cad/hspice/license.dat
Then you would enter:
setenv LM_LICENSE_FILE /usr/cad/hspicext/license.dat:\
/usr/cad/hspice/license.dat
You can also set the variable [email protected] to point to a license file on a
server.
■
If you are using the C shell, add the following line to the .cshrc file:
setenv LM_LICENSE_FILE [email protected]
■
If you are using the Bash or Bourne shell, add these lines to the .bashrc or
.profile file:
[email protected]
export LM_LICENSE_FILE
The port and host name variables correspond to the TCP port and license
server host name specified in the SERVER line of the Synopsys license file.
Note: To ensure better performance, it is recommended that you use
[email protected] rather than using the path to the license file.
Each license file can contain licenses for many packages from multiple
vendors. You can specify multiple license files by separating each entry. For
UNIX, use a colon (:) and for Windows, use a semicolon (;).
For details about setting license file environment variable, see “Setting Up
HSPICE for Each User” in the Installation Guide.
License Queuing
Setting the optional META_QUEUE environment variable to 1 enables HSPICE
licenses to be queued:
setenv META_QUEUE 1
The licensing queuing works as follows: If you have five HSPICE floating
licenses and all five licenses are checked out with the META_QUEUE
environment variable enabled, then the next job submitted waits in the queue
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Standard Input Files
until a license is available (when one of the previous five jobs finishes). When
META_QUEUE is enabled and all available licenses are in use, an error message
is issued that says no licenses are available.
If you have more than one HSPICE token (INCREMENT line) and the version
dates are different, only the first token in your license file is queued. FLEXlm
queues the first increment line that satisfies the request. If you have two
increment lines with different versions, two license pools are created on the
server. When you issue the queuing request, the server attempts to satisfy the
request, but if it is not possible, the server queues the first increment line that
satisfies the request. Once that particular increment line is queued, it waits for
that increment line to become free. The server does not continually look for any
other line that satisfies this request. This is normal operation for FLEXlm.
Standard Input Files
This section describes the standard input files to HSPICE or HSPICE RF.
Design and File Naming Conventions
The design name identifies the circuit and any related files, including:
■
Schematic and netlist files.
■
Simulator input and output files.
■
Design configuration files.
■
Hardcopy files.
HSPICE, HSPICE RF, and AvanWaves extract the design name from their input
files, and perform actions based on that name. For example, AvanWaves reads
the <design>.cfg configuration file to restore node setups used in previous
AvanWaves runs.
HSPICE, HSPICE RF, and AvanWaves read and write files related to the
current circuit design. Files related to a design usually reside in one directory.
The output file is stdout on Unix platforms, which you can redirect.
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Standard Input Files
Table 1 lists input file types, and their standard names. The sections that follow
describe these files.
Table 1 Input Files
Input File Type
File Name
Output configuration file
meta.cfg
Initialization file
hspice.ini
DC operating point initial conditions file
<design>.ic#
Input netlist file
<design>.sp
Library input file
<library_name>
Analog transition data file
<design>.d2a
Output Configuration File
You use the output configuration file to set up the printer, plotter, and terminal. It
includes a line, default_include = <filename>, to set up a path to the
default .ini file (for example, hspice.ini).
The default include filename is case-sensitive (except for the PC and Windows
versions of HSPICE).
Initialization File
You use the initialization file to specify user defaults. If the run directory
contains an hspice.ini file, HSPICE or HSPICE RF includes its contents at the
top of the input file.
To include initialization files, you can define
default_include = <filename> in a command.inc or meta.cfg file.
You can use an initialization file to set options (for .OPTION statements) and to
access libraries.
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Standard Input Files
DC Operating Point Initial Conditions File)
The DC operating point initial conditions file, <design>.ic#, is an optional input
file that contains initial DC conditions for particular nodes. You can use this file
to initialize DC conditions, by using either a .NODESET or an .IC statement.
A .SAVE statement can also create a <design>.ic# file. A subsequent .LOAD
statement initializes the circuit to the DC operating point values specified in this
file.
Input Netlist File
The input netlist file, <design>.sp, contains the design netlist. Optionally, it can
also contain statements specifying the type of analysis to run, type of output
desired, and what library to use.
Library Input File
You use <library_name> files to identify libraries and macros that need to be
included for simulating <design>.sp.
Analog Transition Data File
When you run HSPICE in standalone mode, a <design>.d2a file contains state
information for a U Element mixed-mode simulation.
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Standard Output Files
Standard Output Files
This section describes the standard output files from HSPICE or HSPICE RF.
The various types of output files produced are listed in Table 2.
Table 2 HSPICE Output Files and Suffixes
16
Output File Type
Extension
AC analysis measurement results
.ma#
AC analysis results (from .POST statement)
.ac#
DC analysis measurement results
.ms#
DC analysis results (from .POST statement)
.sw#
Digital output
.a2d
FFT analysis graph data (from FFT statement)
.ft#
Hardcopy graph data (from meta.cfg
PRTDEFAULT)
.gr# †
HBLSP analysis extraction results
.p2d#
HBLSP large-signal analysis results (from
.PROBE statement)
.ls#.
HBLSP small-signal analysis results (from
.PROBE statement)
.ss#
HBLSP large-signal analysis results (from
.PRINT statement)
.printls#
HBLSP small-signal analysis results (from
.PRINT statement)
.printss#
Operating point information (from .OPTION
OPFILE statement)
.dp#
Operating point node voltages (initial
conditions)
.ic#
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Standard Output Files
Table 2 HSPICE Output Files and Suffixes (Continued)
Output File Type
Extension
Output listing
.lis, or user-specified
Output status
.st#
Output tables (from .DCMATCH OUTVAR
statement)
.dm#
Subcircuit cross-listing (HSPICE only; not
supported in HSPICE RF)
.pa#
Transient analysis measurement results
.mt#
Transient analysis results (from .POST
statement)
.tr#
# Either a sweep number, or a hardcopy file number. For .ac#, .dp#, .dm#,
.ic#, .st#, .sw#, and .tr# files, # is from 0 through 9999.
† Requires a .GRAPH statement, or a pointer to a file in the meta.cfg file.
The PC version of HSPICE does not generate this file.
In HSPICE RF, you cannot replicate output commands within subcircuit
(subckt) definitions.
AC Analysis Results File
HSPICE writes AC analysis results to file <output_file>.ac#, where # is
0-9999, according to your specifications following the .AC statement. These
results list the output variables as a function of frequency.
AC Analysis Measurement Reults File
HSPICE writes AC analysis measurement results to file <output_file>.ma#
when the input file includes a .MEASURE AC statement.
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Standard Output Files
DC Analysis Results File
HSPICE writes DC analysis results to file <output_file>.sw#, where # is
0-9999, when the input file includes a .DC statement. This file contains the
results of the applied stepped or swept DC parameters defined in that
statement. The results can include noise, distortion, or network analysis.
DC Analysis Measurement Results File
HSPICE writes DC analysis measurement results to file <output_file>.ms#
when the input file includes a .MEASURE DC statement.
Digital Output File
The digital output file, <design>.a2d, contains data that the A2D conversion
option of the U element converted to digital form.
FFT Analysis Graph Data File
The FFT analysis graph data file, <output_file>.ft#, contains the
graphical data needed to display the FFT analysis waveforms.
Hardcopy Graph Data File
HSPICE writes hardcopy graph data to file <output_file>.gr# when the
input file includes a .GRAPH statement. The file produced is in the form of a
printer file, typically in Adobe PostScript or HP PCL format. This facility is not
available in the PC version of HSPICE.
HBLSP Analysis Extraction Results File
HSPICE RF writes HBSLP analysis extraction results to file
<output_file>.p2d#, where # is 0-9999, according to your specifications
following the .HBLSP statement. These results list the extracted large- and
small-signal S parameters and noise parameters.
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Standard Output Files
HBLSP Analysis Results File
HSPICE RF writes HBSLP large-signal analysis results to file
<output_file>.ls#, and small-signal analysis results to file
<output_file>.ss#, where # is 0-9999, according to your specifications
following the .PROBE statement. These results are viewable in CosmosScope.
HBLSP Analysis Print Information File
HSPICE RF writes HBSLP large-signal analysis results to file
<output_file>.printls#, and small-signal analysis results to file
<output_file>.printss#, where # is 0-9999, according to your
specifications following the .PRINT statement.
Operating Point Information File
HSPICE writes operating point information to file <design>.dp# when the
input file includes an .OPTION OPFILE=1 statement.
Operating Point Node Voltages File
HSPICE writes operating point node voltages to file <output_file>.ic#,
where # is 0-9999, when the input file includes a .SAVE statement. These
node voltages are the DC operating point initial conditions.
Output Listing File
The output listing is a text file. It can be named <output_file> (no file
extension), <output_file>.lis, or with a file extension that you specify,
depending on which format you use to start the simulation.
For HSPICE RF, the output is a table of simulation results. If the output is text
(the default), the output is HTML, which you can view in a web browser. If you
set the -a command-line argument, this table displays ASCII text output to
stdout, which you can redirect to an output file.
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Standard Output Files
The output file includes the following information:
■
Name of the simulator used.
■
Version of the HSPICE simulator used (HSPICE RF does not produce
backward-compatible .lis files).
■
Synopsys message block.
■
Input filename.
■
User name.
■
License details.
■
Copy of the input netlist file.
■
Node count.
■
Operating point parameters.
■
Details of the volt drop, current, and power for each source and subcircuit.
■
Low-resolution plots, originating from a .PLOT statement.
■
Results of a .PRINT statement.
■
Results of the .OPTION statements.
The Synopsys interactive waveform display tool, CosmosScope, can display
both the text simulation results, and binary output, in the X-window
environment.
Output Status File
The output status file, <output_file>.st#, where # is 0-9999, contains the
following runtime reports:
■
Start and end times for each CPU phase.
■
Options settings, with warnings for obsolete options.
■
Status of preprocessing checks for licensing, input syntax, models, and
circuit topology.
■
Convergence strategies that HSPICE uses on difficult circuits.
You can use the information in this file to diagnose problems, particularly when
communicating with Synopsys Customer Support.
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Standard Output Files
Output Tables
The .DCMATCH output tables file, <output_file>.dm#, contains the
variability data from analysis.
Subcircuit Cross-Listing File
If the input netlist includes subcircuits, HSPICE automatically generates a
subcircuit cross-listing file, <output_file>.pa#, where # is 0-9999. This
file relates the subcircuit node names, in the subcircuit call, to the node names
used in the corresponding subcircuit definitions. In HSPICE RF, you cannot
replicate output commands within subcircuit (subckt) definitions.
Transient Analysis Measurement Results File
HSPICE writes transient analysis measurement results to file
<output_file>.mt# when the input file includes an .MEASURE TRAN
statement.
Transient Analysis Results File
Both HSPICE and HSPICE RF place the results of transient analysis in
file<output_file>.tr#, where # is 0-9999, as set forth in the -n
command-line argument. This file lists the numerical results of transient
analysis. A .TRAN statement in the input file, together with an .OPTION POST
statement, creates this post-analysis file.
If the input file includes an .OPTION POST statement, then the output file
contains simulation output suitable for a waveform display tool.
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Starting HSPICE
Starting HSPICE
Use the following syntax to start HSPICE:
hspice <-i <path/input_file>> <-o <path/output_file>>
<-n number> <-html <path/html_file>> <-b> <-d>
<-mt number> <-I>
HSPICE accepts these command-line arguments:
Arguments
Description
-i
Specifies the input netlist filename for which an extension <.ext> is
path/input_f optional. If you do not specify an input filename extension in the
ile
command, HSPICE searches for a <input_file>.sp file. HSPICE
uses the input filename as the root for the output files. HSPICE also
checks for an initial conditions file (.ic) that has the input file root
name. The following is an example of an input filename:
/usr/sim/work/rb_design.sp
In this filename:
• /usr/sim/work/ is the directory path to the design.
• rb_design is the design root name.
• .sp is the filename suffix.
-o
path/output_file
Name of the output file. If you do not specify an extension, HSPICE
assigns .lis. Everything up to the final period is the root filename,
and everything after the last period is the filename extension.
• If you either do not use this option or you use it without specifying
a filename, HSPICE uses the output root filename specified in
the -html option.
• If you do not specify an output filename in either this or
the -html option, HSPICE uses the input root filename as the
output file root filename.
• If you include the .lis extension in the filename that you enter
using this option, then HSPICE does not append another .lis
extension to the root filename of the output file.
• If you do not specify an output filename, HSPICE directs output
to stdout.
-n number
22
Specifies the starting number for numbering output data file
revisions (output_file.tr#, output_file.ac#,
output_file.sw#, where # is between 0 and 9999.).
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Starting HSPICE
Arguments
Description
-html
path/html_file
Specifies an HTML output file.
• If you do not specify a path, HSPICE saves the HTML output file
in the same directory that you specified in the -o option.
• If you do not specify an -o option, HSPICE saves the HTML
output in the working directory.
• If you do not specify an output filename in either the -o or -html
option, then HSPICE uses the input root filename as the output
file root filename.
-b
(PC) Batch processing switch for Windows platforms only.
-d
(UNIX) Displays the content of .st0 files on screen while running
HSPICE. For example, to show the status during simulation. At he
prompt, you could also enter: tail -f *.st0.
-mt number
Number of processors for multi-threaded simulation.
• If you omit the number, an error message results. You must
include this parameter.
• If you specify a number that is larger than the number of
available CPUs, then HSPICE sets the number of threads equal
to the number of available CPUs.
-I
Interactive mode.
Redirecting Output
Use the following syntax to redirect the output to a file instead of to stdout:
hspice input_file <-n number> > output_file
For example:
hspice demo.sp -n 7 > demo.out
Where:
demo.sp is the input netlist file. The .sp extension is optional.
-n 7 starts the output data file revision numbers at 7; for example: demo.tr7,
demo.ac7, demo.sw7, and so forth.
> redirects the program output listing to file demo.out.
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Running an HSPICE Simulation
Running an HSPICE Simulation
Perform these steps to run a HSPICE simulation.
1. Invocation.
For example, at the shell prompt, enter:
hspice demo.sp > demo.out &
This command invokes the UNIX hspice shell command on input netlist file
demo.sp and directs the output listing to file demo.out. The “&” character at
the end of the command invokes HSPICE in the background, so that you can
continue to use the window and keyboard while HSPICE runs.
2. Script execution.
The hspice shell command starts the HSPICE executable from the
appropriate architecture (machine type) directory. The UNIX run script
launches a HSPICE simulation. This procedure establishes the environment
for the HSPICE executable. The script prompts for information, such as the
platform that you are using, and the version of HSPICE to run. (Available
versions are determined when you install HSPICE.)
3. Licensing.
HSPICE supports the FLEXlm licensing management system. When you
use FLEXlm licensing, HSPICE reads the LM_LICENSE_FILE environment
variable to find the location of the license.dat file.
If HSPICE cannot authorize access, the job terminates at this point, and
prints an error message in the output listing file.
4. Simulation configuration.
HSPICE reads the appropriate meta.cfg file. The search order for the
configuration file is the user login directory, and then the product installation
directory.
5. Design input.
HSPICE opens the input netlist file demo.sp. If this file does not exist, a no
input data error appears in the output listing file.
(UNIX) HSPICE opens three scratch files in the /tmp directory. To change
this directory, reset the tmpdir environment variable in the HSPICE
command script.
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Running an HSPICE Simulation
(Windows) HSPICE opens three scratch files in the c:\<path>\TEMP (or
\TMP) directory. To change this directory, reset the TEMP or TMP
environment variable in the HSPICE command script.
HSPICE opens the output listing file demo.out for writing. If you do not own
the current directory, HSPICE terminates with a file open error.
Here’s an example of a simple HSPICE input netlist:
Inverter Circuit
.OPTION LIST NODE POST
.TRAN 200P 20N SWEEP TEMP -55 75 10
.PRINT TRAN V(IN) V(OUT)
M1 VCC IN OUT VCC PCH L = 1U W = 20U
M2 OUT IN 0 0 NCH L = 1U W = 20U
VCC VCC 0 5
VIN IN 0 0 PULSE .2 4.8 2N 1N 1N 5N 20N CLOAD OUT 0 .75P
.MODEL PCH PMOS
.MODEL NCH NMOS
.ALTER
CLOAD OUT 0 1.5P
.END
You can find the complete netlist for this example in the following directory:
$installdir/demo/hspice/apps/inv_ex1.sp
6. Library input.
HSPICE reads any files that you specified in .INCLUDE and .LIB
statements.
7. Operating point initialization.
HSPICE reads any initial conditions that you specified in .IC and
.NODESET statements, finds an operating point (that you can save with
a .SAVE statement), and writes any operating point information that you
requested.
8. Multipoint analysis.
HSPICE performs the experiments specified in analysis statements. In the
above example, the .TRAN statement causes HSPICE to perform a
multipoint transient analysis for 20 ns for temperatures ranging from -55°C
to 75°C, in steps of 10°C.
9. Single-point analysis.
HSPICE performs a single or double sweep of the designated quantity, and
produces one set of output files.
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Interactive Simulation
10. Worst-case .ALTER.
You can vary simulation conditions, and repeat the specified single or
multipoint analysis. The above example changes CLOAD from 0.75 pF to 1.5
pF, and repeats the multipoint transient analysis.
11. Normal termination.
After you complete the simulation, HSPICE closes all files it opened and
releases all license tokens.
Interactive Simulation
To invoke HSPICE in interactive mode, enter:
hspice -I
You can then use other HSPICE commands to help you simulate circuits
interactively. You can also use the help command for detailed information about
a command.
HSPICE interactive mode also supports saving commands into a script file. To
save the commands that you use, and replay them later, enter:
hspice> save command <filename>
To run the command you have saved in a command file, enter the following line:
hspice -I -L command.cmd
Examples of Starting HSPICE
The following are some additional examples of commands to start running
HSPICE.
■
hspice -i demo.sp
demo is the root filename. Without the -o option and without redirection,
HSPICE does not generate an output listing file.
■
hspice -i demo.sp -o demo
demo is the output file root name (designated with the -o option). Output
files are named demo.lis, demo.tr0, demo.st0, and demo.ic0.
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Examples of Starting HSPICE
■
hspice -i rbdir/demo.sp
demo is the root name. HSPICE writes the demo.lis, demo.tr0, and demo.st0
output files into the directory where you executed the HSPICE command. It
also writes the demo.ic0 output file into the same directory as the input
source—that is, rbdir.
■
hspice -i a.b.sp
a.b is the root name. The output files are ./a.b.lis, ./a.b.tr0,
./a.b.st0, and ./a.b.ic0.
■
hspice -i a.b -o d.e
a.b is the root name for the input file.
d.e is the root for output file names, except for the .ic file, to which HSPICE
assigns the a.b input file root name. The output files are d.e.lis, d.e.tr0,
d.e.st0, and a.b.ic0.
■
hspice -i a.b.sp -o outdir/d.e
a.b is the root for the .ic0 file. HSPICE writes the .ic0 file into a file named
a.b.ic0.
d.e is the root for other output files. Output files are outdir/d.e.lis,
outdir/d.e.tr0, and outdir/d.e.st0.
■
hspice -i indir/a.b.sp -o outdir/d.e.lis
a.b is the root for the .ic file. HSPICE writes the .ic0 file into a file named
indir/a.b.ic0.
d.e is the root for the output files.
■
hspice test.sp -o test.lis -html test.html
This command creates output file in both .lis and .html format, after
simulating the test.sp input netlist.
■
hspice test.sp -html test.html
This command creates only a .html output file, after simulating the test.sp
input netlist.
■
hspice test.sp -o test.lis
This command creates only a .lis output file, after simulating the test.sp
input netlist.
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Starting HSPICE RF
■
hspice -i test.sp -o -html outdir/a.html
This command creates output files in both .lis and .html format. Both files
are in the outdir directory, and their root filename is a.
■
hspice -i test.sp -o out1/a.lis -html out2/b.html
This command creates output files in both .lis and .html format. The .lis file
is in the out1 directory, and its root filename is a. The .html file is in the out2
directory, and its root filename is b.
Starting HSPICE RF
Use the following syntax to start HSPICE RF:
hspicerf [-a] inputfile [outputfile] [-h] [-v]
HSPICE RF accepts these command-line arguments:
Argument
Description
-a
Generates output to sdout in ASCII format. For example,
% hspicerf -a ckt.in
You can redirect the ASCII output to another file. For example:
% hspicerf -a ckt.in > xt
Output from a .PRINT command goes to an ASCII file with
a .print# or .printac# file extension.
inputfile
The name of the input netlist.
outputfile
The name of the output listing file.
• If specified, the simulation output is written to this file and given
a .lis file extension. For example,
% hspicerf ckt.in xt
automatically sets -a and generates output to xt.lis.
• If not specified (the default), an html directory is created and
the simulation output is written to an hspicerf.html file in that
directory. For example,
% hspicerf ckt.in
generates output to html/hspicerf.html.
Use your web browser to view this file.
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Improving Simulation Performance with Multithreading
Argument
Description
-h
Returns a help message.
-v
Returns version information.
Improving Simulation Performance with Multithreading
HSPICE simulations include device model evaluations and matrix solutions.
You can run model evaluations concurrently on multiple CPUs, by using
multithreading to significantly improve simulation performance. Model
evaluation dominates most of the time. To determine how much time HSPICE
spends evaluating models and solving matrices, specify .OPTION ACCT = 2
in the netlist.
By using multithreading, you can speed-up simulations with no loss of
accuracy. Multithreading gives the best results for circuit designs that contain
many MOSFET, JFET, diode, or BJT models in the netlist.
Running HSPICE-MT
On UNIX platforms, use this syntax to run HSPICE-MT:
hspice -mt number -i input_file -o output_file
On Windows platforms, use this syntax to run HSPICE-MT:
hspice_mt.exe -mt number -i input_file -o output_file
For a description of the options shown in the syntax lines above, see section
Starting HSPICE on page 22.
In Windows NT Explorer:
1. Double-click the hsp_mt application icon.
2. Select the File/Simulate button, to select the input netlist file.
In Windows, the program automatically detects the number of available
processors. Under the Synopsys HSPUI (HSPICE User Interface):
1. Select the correct hsp_mt.exe version in the Version combo box.
2. Select the correct number of CPUs in the MT option box.
3. Click the Open button, to select the input netlist file.
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Simulating in Client/Server Mode
4. Click the Simulate button, to start the simulation.
Performance Improvement Estimations
For HSPICE-MT, the CPU time is:
Tmt = Tserial + Tparallel/Ncpu + Toverhead
Where:
Tserial represents HSPICE calculations that are not threaded.
Tparallel represents threaded HSPICE calculations.
Ncpu is the number of CPUs used.
Toverhead is the overhead from multithreading. Typically, this represents a
small fraction of the total runtime.
For example, for a 151-stage NAND ring oscillator using LEVEL 49,
Tparallel is about 80% of T1cpu (the CPU time associated with a single
CPU) if you run with two threads on a multi-CPU machine. Ideally, assuming
Toverhead = 0, you can achieve a speedup of:
T1cpu/(0.2T1cpu + 0.8T1cpu/2cpus) = 1.67
The typical Tparallel value is 0.6 to 0.7 for moderate to large circuits.
Simulating in Client/Server Mode
When you run many small simulation cases, you can use the client/server
mode to improve performance. This performance improvement occurs because
you check out and check in an HSPICE license only once. This is an effective
measure when you characterize cells.
1. Enter Client/Server mode:
hspice -C
This step creates an HSPICE server, and checks out an HSPICE license.
2. Simulate your netlist
hspice -C input_file
This step runs simulation without checking out an HSPICE license.
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Simulating in Client/Server Mode
Note: This mode also supports other HSPICE command line options. For a
description of these options shown, see section Starting HSPICE on
page 22.
3. Exit Client/Server mode
hspice -C -K
This step releases the HSPICE license and exits HSPICE.
Server
The server name is a specific name connected with the machine on which
HSPICE runs. When you create the server, HSPICE also generates a
hidden .hspicecc directory in your home directory. HSPICE places some
related files in this directory, and removes them when the server exits.
HSPICE Client/Server mode does not let one user create several servers on
the same machine.
When you create a server, the output on the screen is:
***************************************
*Starting HSPICE Client/Server Mode...*
***************************************
Checking out HSPICE license...
HSPICE license has been checked out.
***********************************************
*Welcome to HSPICE Client/Server Mode!*
*******************************************
After you create the server, it automatically runs in the background.
If the server does not receive any request from a client for 12 hours, the server
releases the license, and exits automatically.
Client
The client can send a request to the server to ask whether an HSPICE license
has been checked out, or to kill the server.
■
If the request is to check the license status, the server checks whether an
HSPICE license has been checked out, and replies to the client. The syntax
of this request is:
hspice -C casename.sp
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Simulating in Client/Server Mode
Where casename is the name of the circuit design to simulate.
•
If the client receives ok, it begins to simulate the circuit design.
•
If the client receives no, it exits.
■
If the server receives several requests at the same time, it queues these
requests, and process them in the order that the server received them.
■
If HSPICE does not find a server, it creates a server first. Then the server
checks out an HSPICE license, and simulates the circuit.
■
If the request is to kill the server, the server releases the HSPICE license
and other sources, and exits.
When you kill the server, any simulation cases that are queued on that
server do not run, and the server's name disappears from the
hidden .hspicecc directory in your home directory.
If you do not specify an output file, HSPICE directs output to the client terminal.
Use the following syntax to redirect the output to a file, instead of to the
terminal:
hspice -C casename.sp >output_file
Note: HSPICE RF does not support PKG and EBD simulation.
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Simulating with Stand-alone .MEASURE Calculations
Simulating with Stand-alone .MEASURE Calculations
When you want to calculate new measurements from previous simulation
results produced by HSPICE, you can use the following mode to rerun
HSPICE:
hspice -meas measurefile -i wavefile <-o <outputfile>>
Argument
Description
-meas measurefile
This fomat is similar to the HSPICE netlist format. The
first line is a comment line, and the last line is an .END
statement. Seven commands are supported:
• .MEASURE
• .PARAM
• .TEMP
• .OPTION
• .DATA
• .ENDDATA
• .END
Note: The .DATA statement in the measure file must
be consistent with the .DATA statement in the wavefile.
The .OPTION statement support four types:
• MEASFAIL
• NUMDGT
• INGOLD
• MEASDGT
Warnings are issued if other options or statements are
used. Wave files formatted as PSF and CSDF are not
supported.
-i wavefile
This argument specifies the *.tr#, *.ac#, and *.sw# files
produced by HSPICE. Wave files formatted as PSF are
not supported.
-o outputfile
Specifies the same output files as HSPICE. Some case
results are different from the measure result HSPICE
produces due to an accuracy problem.
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Simulating with Stand-alone .MEASURE Calculations
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Input Netlist and Data Entry
3
Describes the input netlist file and methods of entering data.
For descriptions of individual HSPICE commands referenced in this chapter,
see the HSPICE Command Reference.
Input Netlist File Guidelines
HSPICE and HSPICE RF operate on an input netlist file, and store results in
either an output listing file or a graph data file. An input file, with the name
<design>.sp, contains the following:
■
Design netlist (subcircuits, macros, power supplies, and so on).
■
Statement naming the library to use (optional).
■
Specifies the type of analysis to run (optional).
■
Specifies the type of output desired (optional).
An input filename can be up to 1024 characters long. The input netlist file
cannot be in a packed or compressed format.
To generate input netlist and library input files, HSPICE or HSPICE RF uses
either a schematic netlister or a text editor.
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Input Netlist File Guidelines
Statements in the input netlist file can be in any order, except that the first line is
a title line, and the last .ALTER submodule must appear at the end of the file
and before the .END statement.
Note: If you do not place an .END statement and a [Return] at the end of the
input netlist file, HSPICE or HSPICE RF issues an error message.
Netlist input processing is case insensitive, except for file names and their
paths. HSPICE and HSPICE RF do not limit the identifier length, line length, or
file size.
Input Line Format
■
The input reader can accept an input token, such as:
•
a statement name.
•
a node name.
•
a parameter name or value.
Any valid string of characters between two token delimiters is a token. You
can use a character string as a parameter value in HSPICE, but not in
HSPICE RF. See Delimiters on page 38.
■
An input statement, or equation can be up to 1024 characters long.
■
HSPICE or HSPICE RF ignores differences between upper and lower case
in input lines, except in quoted filenames.
■
To continue a statement on the next line, enter a plus (+) sign as the first
non-numeric, non-blank character in the next line.
■
To indicate “to the power of” in your netlist, use two asterisks (**). For
example, 2**5 represents two to the fifth power (25)
■
To continue all HSPICE or HSPICE RF statements, including quoted strings
(such as paths and algebraics), use a backslash (\) or a double backslash
(\\) at the end of the line that you want to continue.
•
36
A single backslash preserves white space.
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Input Netlist File Guidelines
■
Names must begin with an alphabetic character, but thereafter can contain
numbers and the following characters:
! # $ % * + / < > [ ] _ { } : ; ? | .
,
•
When you use an asterisk (*) or a question mark (?) with
a .PRINT, .PROBE, .PLOT (HSPICE), .GRAPH, .LPRINT (HSPICE
RF), or .CHECK (HSPICE RF) statement, HSPICE or HSPICE RF uses
the character as a wildcard. For additional information, see Using
Wildcards on Node Names on page 51.
•
When you use curly brackets ( { } ), HSPICE converts them to square
brackets ( [ ] ) automatically.
•
Names are input tokens. Token delimiters must precede and follow
names. See “Delimiters” below.
•
Names can be up to 1024 characters long and are not case-sensitive.
•
Do not use any of the time keywords as a parameter name or node
name in your netlist.
•
The following symbols are reserved operator keywords:
()
=
“
’
Do not use these symbols as part of any parameter or node name that
you define. Using any of these reserved operator keywords as names
causes a syntax error, and HSPICE or HSPICE RF stops immediately.
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Input Netlist File Guidelines
First Character
The first character in every line specifies how HSPICE and HSPICE RF
interprets the remaining line. Table 3 lists and describes the valid characters.
Table 3 First Character Descriptions
Line
If the First Character is...
Indicates
First line of a netlist
Any character
Title or comment line. The
first line of an included file is
a normal line and not a
comment.
Subsequent lines of
netlist, and all lines
of included files
. (period)
Netlist keyword. For
example,
.TRAN 0.5ns 20ns
c, C, d, D, e, E, f, F, g, G, h,
H, i, I, j, J, k, K, l, L, m, M,
q, Q, r, R, s, S, v, V,w,W
Element instantiation
* (asterisk)
# (number)
Comment line (HSPICE)
Comment line (HSPICE RF)
+ (plus)
Continues previous line
Delimiters
38
■
An input token is any item in the input file that HSPICE or HSPICE RF
recognizes. Input token delimiters are: tab, blank, comma (,), equal sign (=),
and parentheses ( ).
■
Single (‘) or double quotes (“) delimit expressions and filenames.
■
Colons (:) delimit element attributes (for example, M1:VGS).
■
Periods (.) indicate hierarchy. For example, X1.X2.n1 is the n1 node on the
X2 subcircuit of the X1 circuit.
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Node Identifiers
Node identifiers can be up to 1024 characters long, including periods and
extensions. Node identifiers are used for node numbers and node names.
■
Node numbers are valid in the range of 0 through 9999999999999999
(1-1e16).
■
Leading zeros in node numbers are ignored.
■
Trailing characters in node numbers are ignored. For example, node 1A is
the same as node 1.
■
A node name can begin with any of these characters:
! # % * / < > _ ? | . &
For additional information, see Node Naming Conventions on page 50.
■
To make node names global across all subcircuits, use a .GLOBAL
statement.
■
The 0, GND, GND!, and GROUND node names all refer to the global HSPICE
or HSPICE RF ground. Simulation treats nodes with any of these names as
a ground node, and produces v(0) into the output files.
Instance Names
The names of element instances begin with the element key letter (see
Table 4), except in subcircuits where instance names begin with X. (Subcircuits
are sometimes called macros or modules.) Instance names can be up to 1024
characters long. The .OPTION LENNAM defines the length of names in
printouts (default = 8).
Table 4 Element Identifiers
Letter
(First
Char)
Element
Example Line
B
IBIS buffer
b_io_0 nd_pu0 nd_pd0 nd_out
nd_in0 nd_en0 nd_outofin0
nd_pc0 nd_gc0
C
Capacitor
Cbypass 1 0 10pf
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Table 4 Element Identifiers (Continued)
Letter
(First
Char)
Element
Example Line
D
Diode
D7 3 9 D1
E
Voltage-controlled voltage source
Ea 1 2 3 4 K
F
Current-controlled current source
Fsub n1 n2 vin 2.0
G
Voltage-controlled current source
G12 4 0 3 0 10
H
Current-controlled voltage source
H3 4 5 Vout 2.0
I
Current source
I A 2 6 1e-6
J
JFET or MESFET
J1 7 2 3 GAASFET
K
Linear mutual inductor (general form)
K1 L1 L2 1
L
Linear inductor
LX a b 1e-9
M
MOS transistor
M834 1 2 3 4 N1
P
Port
P1 in gnd port=1 z0=50
Q
Bipolar transistor
Q5 3 6 7 8 pnp1
R
Resistor
R10 21 10 1000
S, T, U, W
Transmission line
S1 nd1 nd2 s_model2
V
Voltage source
V1 8 0 5
W
Transmission Line
W1 in1 0 out1 0 N=1 L=1
X
Subcircuit call
X1 2 4 17 31 MULTI WN = 100
LN = 5
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Hierarchy Paths
■
A period (.) indicates path hierarchy.
■
Paths can be up to 1024 characters long.
■
Path numbers compress the hierarchy for post-processing and listing files.
■
You can find path number cross references in the listing and in the
<design>.pa0 file.
■
The .OPTION PATHNUM controls whether the list files show full path names
or path numbers.
Numbers
Note: You can enter numbers as integer, floating point, floating point with an
integer exponent, or integer or floating point with one of the scale factors
listed in Table 5. real.
Table 5 Scale Factors
Scale Factor
Prefix
Symbol
Multiplying Factor
T
tera
T
1e+12
G
giga
G
1e+9
MEG or X
mega
M
1e+6
K
kilo
k
1e+3
M
milli
m
1e-3
U
micro
µ
1e-6
N
nano
n
1e-9
P
pico
p
1e-12
F
femto
f
1e-15
A
atto
a
1e-18
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Note: Scale factor A is not a scale factor in a character string that contains
amps. For example, HSPICE interprets the 20amps string as 20e-18mps
(20-18mps), but it correctly interprets 20amps as 20 amperes of current, not
as 20e-18mps (20-18mps).
■
Numbers can use exponential format or engineering key letter format, but
not both (1e-12 or 1p, but not 1e-6u).
■
To designate exponents, use D or E.
■
The .OPTION EXPMAX limits the exponent size.
■
Trailing alphabetic characters are interpreted as units comments.
■
Units comments are not checked.
■
The .OPTION INGOLD controls the format of numbers in printouts.
■
The .OPTION NUMDGT = x controls the listing printout accuracy.
■
The .OPTION MEASDGT = x controls the measure file printout accuracy.
■
The .OPTION VFLOOR = x specifies the smallest voltage for which
HSPICE or HSPICE RF prints the value. Smaller voltages print as 0.
Parameters and Expressions
■
Parameter names in HSPICE or HSPICE RF use HSPICE name syntax
rules, except that names must begin with an alphabetic character. The other
characters must be either a number, or one of these characters:
! # $ % [ ] _
42
■
To define parameter hierarchy overrides and defaults, use the .OPTION
PARHIER = global | local statement.
■
If you create multiple definitions for the same parameter or option, HSPICE
or HSPICE RF uses the last parameter definition or .OPTION statement,
even if that definition occurs later in the input than a reference to the
parameter or option. HSPICE or HSPICE RF does not warn you when you
redefine a parameter.
■
You must define a parameter before you use that parameter to define
another parameter.
■
When you select design parameter names, be careful to avoid conflicts with
parameterized libraries.
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■
To delimit expressions, use single or double quotes.
■
Expressions cannot exceed 1024 characters.
■
For improved readability, use a double slash (\\) at end of a line, to continue
the line.
■
You can nest functions up to three levels.
■
Any function that you define can contain up to two arguments.
■
Use the PAR (expression or parameter) function to evaluate expressions in
output statements.
Input Netlist File Structure
An input netlist file should consist of one main program, and one or more
optional submodules. Use a submodule (preceded by an .ALTER statement) to
automatically change an input netlist file; then rerun the simulation with
different options, netlist, analysis statements, and test vectors.
You can use several high-level call statements (.INCLUDE, .LIB and .DEL
LIB) to restructure the input netlist file modules. These statements can call
netlists, model parameters, test vectors, analysis, and option macros into a file,
from library files or other files. The input netlist file also can call an external data
file, which contains parameterized data for element sources and models.
Schematic Netlists
HSPICE or HSPICE RF typically use netlisters to generate circuits from
schematics, and accept either hierarchical or flat netlists. The normal SPICE
netlisters flatten all subcircuits, and rename all nodes to numbers. Avoid flat
netlisters if possible.
The process of creating a schematic involves:
■
Symbol creation with a symbol editor.
■
Circuit encapsulation.
■
Property creation.
■
Symbol placement.
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■
Symbol property definition.
■
Wire routing and definition
Table 6 Input Netlist File Sections
Sections
Examples
Definition
Title
.TITLE
The first line in the netlist is the title of the
input netlist file.
Set-up
.OPTION
.IC or .NODESET
.PARAM
.GLOBAL
Sets conditions for simulation.
Initial values in circuit and subcircuit.
Set parameter values in the netlist.
Set node name globally in netlist.
Sources
Sources and digital inputs
Sets input stimuli (I or V element).
Netlist
Circuit elements
.SUBKCT, .ENDS, or
.MACRO, .EOM
Circuit for simulation.
Subcircuit definitions.
Analysis
.DC, .TRAN, .AC, and so on.
.SAVE and .LOAD
.DATA
.TEMP
Statements to perform analyses.
Save and load operating point information.
Create table for data-driven analysis.
Set temperature analysis.
Output
.PRINT, .PLOT, .GRAPH,
.PROBE
.MEASURE
Statements to output variables.
.INCLUDE
General include files.
.MALIAS
Assigns an alias to a diode, BJT, JFET, or
MOSFET.
.MODEL
Element model descriptions.
.LIB
Library.
Library,
Model
and File
Inclusion
44
Statement to evaluate and report userdefined functions of a circuit.
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Table 6 Input Netlist File Sections (Continued)
Sections
Examples
Definition
.OPTION SEARCH
Search path for libraries and included files.
.PROTECT and .UNPROTECT
Control printback to output listing.
Alter
blocks
.ALIAS
.ALTER
.DELETE LIB
Renames a previous model.
Sequence for in-line case analysis.
Removes previous library selection.
End of
netlist
.END
Required statement; end of netlist.
Input Netlist File Composition
The HSPICE and HSPICE RF circuit description syntax is compatible with the
SPICE input netlist format. Figure 7 shows the basic structure of an input
netlist.
Figure 7
Basic Netlist Structure
Title line: First line is automatically a comment
* Comments (all lines beginning with an asterisk)
*
Input control statements
Netlist body: description of circuit topology.
.MODEL statements
*
.OPTION statements
.OPTION with option statements
.PRINT and other output statements.
Analysis statement (such as .POWER, .TRAN)
.END
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control statements
Analysis/output
control statements
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Input Netlist File Composition
The following is an example of a simple netlist file, called inv_ckt.in. It shows a
small inverter test case that measures the timing behavior of the inverter. To
create the circuit:
1. Define the MOSFET models for the PMOS and NMOS transistors of the
inverter.
2. Insert the power supplies for both VDD and GND power rails.
3. Insert the pulse source to the inverter input.
This circuit uses transient analysis and produces output graphical waveform
data for the input and output ports of the inverter circuit.
* Sample inverter circuit
* **** MOS models *****
.MODEL n1 NMOS LEVEL=3 THETA=0.4 ...
.MODEL p1 PMOS LEVEL=3 ...
* ***** Define power supplies and sources *****
VDD VDD 0 5
VPULSE VIN 0 PULSE 0 5 2N 2N 2N 98N 200N
VGND GND 0 0
* ***** Actual circuit topology *****
M1 VOUT VIN VDD VDD p1
M2 VOUT VIN GND GND n1
* ***** Analysis statement *****
.TRAN 1n 300n
* ***** Output control statements *****
.OPTION POST PROBE
.PROBE V(VIN) V(VOUT)
.END
For a description of individual commands used in HSPICE or HSPICE RF
netlists, see the HSPICE Command Reference manual.
Title of Simulation
You set the simulation title in the first line of the input file. HSPICE or HSPICE
RF always reads this line, and uses it as the title of the simulation, regardless of
the line’s contents. The simulation prints the title verbatim, in each section
heading of the output listing file.
To set the title, you can place a .TITLE statement on the first line of the netlist.
However, HSPICE or HSPICE RF does not require the .TITLE syntax.
The first line of the input file is always the implicit title. If any statement appears
as the first line in a file, simulation interprets it as a title, and does not execute it.
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Input Netlist File Composition
An .ALTER statement does not support use the .TITLE statement. To change
a title for a .ALTER statement, place the title content in the .ALTER statement
itself.
Comments and Line Continuation
The first line of a netlist is always a comment, regardless of its first character;
comments that are not the first line of the netlist require either an asterisk (*) in
HSPICE or a number (#) in HSPICE RF as the first character of the line, or a
dollar sign ($) directly in front of the comment anywhere on the line. For
example,
* <comment_on_a_line_by_itself>
or
<HSPICE_statement> $ <comment_following_HSPICE_input>
You can place comment statements anywhere in the circuit description. The
dollar sign must be used for comments that do not begin in the first character
position on a line (for example, for comments that follow simulator input on the
same line). If it is not the first nonblank character, then the dollar sign must be
preceded by a space or comma, unless that character is a units comment
(scale factor) to a number. You can place the dollar sign within node or element
names. For example,
* RF = 1K GAIN SHOULD BE 100
$ MAY THE FORCE BE WITH MY CIRCUIT
VIN 1 0 PL 0 0 5V 5NS $ 10v 50ns
R12 1 0 1MEG $ FEED BACK
.PARAM a=1w$comment a=1, w treated as a space and ignored
.PARAM a=1k$comment a=1e3, k is a scale factor
A dollar sign is the preferred way to indicate comments, because of the
flexibility of its placement within the code.
Line continuations require a plus sign (+) as the first character in the line that
follows. Here is an example of comments and line continuation in a netlist file:
.ABC Title Line (HSPICE or HSPICE RF ignores the netlist keyword
* on this line, because the first line is always a comment)
* This is
.MODEL n1
* This is
+ LEVEL =
a comment line
NMOS $ this is an example of an inline comment
a comment line and the following line is a continuation
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Input Netlist File Composition
Element and Source Statements
Element statements describe the netlists of devices and sources. Use nodes to
connect elements to one another. Nodes can be either numbers or names.
Element statements specify:
■
Type of device.
■
Nodes to which the device is connected.
■
Operating electrical characteristics of the device.
Element statements can also reference model statements that define the
electrical parameters of the element.
Table 7 lists the parameters of an element statements.
Table 7 Element Parameters
Parameter
Description
elname
Element name that cannot exceed 1023 characters, and must begin with a
specific letter for each element type:
B IBIS buffer
C Capacitor
D Diode
E,F,G,H Dependent current and voltage sources
I
Current (inductance) source
J JFET or MESFET
K Mutual inductor
L Inductor model or magnetic core mutual inductor model
M MOSFET
Q BJT
P Port
R Resistor
S, T, U, WTransmission line
V Voltage source
X Subcircuit call
node1 ...
48
Node names identify the nodes that connect to the element. The node name
begins with a letter and can contain a maximum of 1023 characters. You cannot
use the following characters in node names: = ( ),’ <space>
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Table 7 Element Parameters (Continued)
Parameter
Description
mname
HSPICE or HSPICE RF requires a model reference name for all elements,
except passive devices.
pname1 ...
An element parameter name identifies the parameter value that follows this
name.
expression
Any mathematical expression containing values or parameters, such as
param1 * val2
val1 ...
Value of the pname1 parameter, or of the corresponding model node. The value
can be a number or an algebraic expression.
M = val
Element multiplier. Replicates val element times, in parallel. Do not assign a
negative value or zero as the M value.
For descriptions of element statements for the various types of supported
elements, see the chapters about individual types of elements in this user
guide.
Example 1:
Q1234567
4000
5000 6000 SUBSTRATE BJTMODEL AREA = 1.0
The preceding example specifies a bipolar junction transistor, with its collector
connected to node 4000, its base connected to node 5000, its emitter
connected to node 6000, and its substrate connected to the SUBSTRATE node.
The BJTMODEL name references the model statement, which describes the
transistor parameters.
M1 ADDR SIG1 GND SBS N1 10U 100U
The preceding example specifies a MOSFET named M1, where:
■
drain node = ADDR
■
gate node = SIG1
■
source node = GND
■
substrate nodes = SBS
The preceding element statement calls an associated model statement, N1.
The MOSFET dimensions are width = 100 microns and length = 10 microns.
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Example 2:
M1 ADDR SIG1 GND SBS N1 w1+w l1+l
The preceding example specifies a MOSFET named M1, where:
■
drain node = ADDR
■
gate node = SIG1
■
source node = GND
■
substrate nodes = SBS
The preceding element statement calls an associated model statement, N1.
MOSFET dimensions are algebraic expressions (width = w1+w, and
length = l1+l).
Defining Subcircuits
You can create a subcircuit description for a commonly-used circuit, and
include one or more references to the subcircuit in your netlist.
■
Use .SUBCKT and .MACRO statements to define subcircuits within your
HSPICE netlist or HSPICE RF.
■
Use the .ENDS statement to terminate a .SUBCKT statement.
■
Use the .EOM statement to terminate a .MACRO statement.
■
Use X<subcircuit_name> (the subcircuit call statement) to call a
subcircuit that you previously defined in a .MACRO or .SUBCKT command in
your netlist, where <subcircuit_name> is the element name of the
subcircuit that you are calling. This subcircuit element name can be up to 15
characters long.
■
Use the .INCLUDE statement to include another netlist as a subcircuit in the
current netlist.
Node Naming Conventions
Nodes are the points of connection between elements in the input netlist file.
You can use either names or numbers to designate nodes. Node numbers can
be from 1 to 999999999999999; node number 0 is always ground. HSPICE or
HSPICE RF ignores letters that follow numbers in node names. When the node
name begins with a letter or a valid special character, the node name can
contain a maximum of 1024 characters.
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Input Netlist File Composition
In addition to letters and digits, node names can include the following
characters:
+, -, *, /, $, #, [], !, <>, _, %
If you use braces { } in node names, HSPICE or HSPICE RF changes them to
brackets [ ]. You cannot use the following characters in node names:
() , = ‘ <blank>
The period (.) is reserved for use as a separator between a subcircuit name
and a node name: <subcircuitName>.<nodeName>. If a node name contains
a period, the node will be considered a top level node unless there is a valid
match to a subcircuit name and node name in the hierarchy.:
The sorting order for operating point nodes is:
a-z, !, #, $, %, *, +, -, /
Using Wildcards on Node Names
You can use wildcards to match node names.
■
? wildcard matches any single character. For example, 9? matches 92, 9a,
9A, and 9%.
■
* wildcard matches any string of zero or more characters. For example:
■
•
If your netlist includes a resistor named r1 and a voltage source named
vin, then .PRINT i(*) prints the current for both of these elements:
i(r1) and i(vin).
•
And .PRINT v(o*) prints the voltages for all nodes whose names start
with o; if your netlist contains nodes named in and out, this example
prints only the v(out) voltage.
[ ] matches any character tht appears within the brackets. For example,
[123] matches 1, 2, or 3. A hyphen inside the brackets indicates a
character range. For example, [0-9] is the same as [0123456789], and
matches any digit.
For example, the following prints the results of a transient analysis for the
voltage at the matched node name.
.PRINT TRAN V(9?t*u)
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Input Netlist File Composition
Wildcards must begin with a letter or a number. For example:
.PROBE v(*)
correct format
.PROBE *
incorrect format
.PROBE x*
correct format
Here are some practical applications for these wildcards:
■
If your netlist includes a resistor named r1 and a voltage source named
vin, then .PRINT i(*) prints the current for both elements i(r1) and
i(vin).
■
The statement .PRINT v(o*) prints the voltages for all nodes whose
names start with o; if your netlist contains nodes named in and out, this
example prints only the v(out) voltage.
■
If your netlist contains nodes named 0, 1, 2, and 3, then .PRINT v(0,*)
or .PRINT v(0 *) prints the voltage between node 0 and each of the other
nodes: v(0,1), v(0,2), and v(0,3).
Examples
The following examples use wildcards with .PRINT, .PROBE, and .LPRINT
statements. You must create an .admrc file to use these wildcards.
■
Probe all top-level in a design hierarchy.
.PROBE v(*)
■
Probe all first-level nodes, where zero-level are top-level nodes whose
names start with a, and all nodes at all levels below it. For example: a1, a2,
a3, a00, ayz.
.PROBE v(a*)
■
Print all first-level nodes, where zero-level are top-level nodes, and all nodes
at all levels below it. For example: X1.A, X4.554, Xab.abc123.
.PRINT v(*.*)
■
Probe all first-level nodes that start with x, where zero-level are top-level
nodes, and all nodes at all levels below it. For example: x1.A, x4.554,
xab.abc123. This example creates only waveform data, without an ASCII
table of results.
.PROBE v(x*.*)
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■
Print all second-level nodes. For example: x1.x2.a, xab.xdff.in.
.PRINT v(x*.*.*)
■
Match all first-level nodes with names that are exactly two characters long.
For example: x1.in, x4.12.
.PRINT v(x*.*.*)
■
In HSPICE RF, print the logic state of all top-level nodes, whose names start
with b. For example: b1, b2, b3, b56, bac.
.LPRINT (1,4) b*
Element, Instance, and Subcircuit Naming Conventions
Instances and subcircuits are elements and as such, follow the naming
conventions for elements.
Element names in HSPICE or HSPICE RF begin with a letter designating the
element type, followed by up to 1023 alphanumeric characters. Element type
letters are R for resistor, C for capacitor, M for a MOSFET device, and so on
(see Element and Source Statements on page 48).
Subcircuit Node Names
HSPICE assigns two subcircuit node names.
■
To assign the first name, HSPICE or HSPICE RF uses the (.) extension to
concatenate the circuit path name with the node name—for example,
X1.XBIAS.M5.
Node designations that start with the same number, followed by any letter,
are the same node. For example, 1c and 1d are the same node.
■
The second subcircuit node name is a unique number that HSPICE
automatically assigns to an input netlist subcircuit. The ( : ) extension
concatenates this number with the internal node name, to form the entire
subcircuit’s node name (for example, 10:M5). The output listing file crossreferences the node name.
Note: HSPICE RF does not support short names for internal subcircuits, such
as 10:M5.
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To indicate the ground node, use either the number 0, the name GND, or !GND.
Every node should have at least two connections, except for transmission line
nodes (unterminated transmission lines are permitted) and MOSFET substrate
nodes (which have two internal connections). Floating power supply nodes are
terminated with a 1Megohm resistor and a warning message.
Path Names of Subcircuit Nodes
A path name consists of a sequence of subcircuit names, starting at the
highest-level subcircuit call, and ending at an element or bottom-level node.
Periods separate the subcircuit names in the path name. The maximum length
of the path name, including the node name, is 1024 characters.
You can use path names in .PRINT, .PLOT, .NODESET, and .IC statements,
as another way to reference internal nodes (nodes not appearing on the
parameter list). You can use the path name to reference any node, including
any internal node. Subcircuit node and element names follow the rules shown
in Figure 8 on page 54.
Figure 8
Subcircuit Calling Tree, with Circuit Numbers and Instance Names
0 (CKT)
1 (X1)
3 (X3)
sig24
2 (X2)
n (abc) is
circuit number (instance name)
4 (X4)
sig25
sig26
In Figure 8, the path name of the sig25 node in the X4 subcircuit is
X1.X4.sig25. You can use this path in HSPICE or HSPICE RF statements,
such as:
.PRINT v(X1.X4.sig25)
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Abbreviated Subcircuit Node Names
In HSPICE, you can use circuit numbers as an alternative to path names, to
reference nodes or elements in .PRINT, .PLOT, .NODESET, or .IC
statements. Compiling the circuit assigns a circuit number to all subcircuits,
creating an abbreviated path name:
<subckt-num>:<name>
Note: HSPICE RF does not recognize this type of abbreviated subcircuit name.
The subcircuit name and a colon precede every occurrence of a node or
element in the output listing file. For example, 4:INTNODE1 is a node named
INTNODE1, in a subcircuit assigned the number 4.
Any node not in a subcircuit has a 0: prefix (0 references the main circuit). To
identify nodes and subcircuits in the output listing file, HSPICE uses a circuit
number that references the subcircuit where the node or element appears.
Abbreviated path names let you use DC operating point node voltage output, as
input in a .NODESET statement for a later run.
You can copy the part of the output listing titled Operating Point Information or
you can type it directly into the input file, preceded by a .NODESET statement.
This eliminates recomputing the DC operating point in the second simulation.
Automatic Node Name Generation
HSPICE or HSPICE RF can automatically assign internal node names. To
check both nodal voltages and branch currents, you can use the assigned node
name when you print or plot. HSPICE or HSPICE RF supports several special
cases for node assignment—for example, simulation automatically assigns
node 0 as a ground node.
For CSOS (CMOS Silicon on Sapphire), if you assign a value of -1 to the bulk
node, the name of the bulk node is B#. Use this name to print the voltage at the
bulk node. When printing or plotting current—for example .PLOT I(R1)—
HSPICE inserts a zero-valued voltage source. This source inserts an extra
node in the circuit named Vnn, where nn is a number that HSPICE (or HSPICE
RF) automatically generates; this number appears in the output listing file.
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Global Node Names
The .GLOBAL statement globally assigns a node name, in HSPICE or HSPICE
RF. This means that all references to a global node name, used at any level of
the hierarchy in the circuit, connect to the same node.
The most common use of a .GLOBAL statement is if your netlist file includes
subcircuits. This statement assigns a common node name to subcircuit nodes.
Another common use of .GLOBAL statements is to assign power supply
connections of all subcircuits. For example, .GLOBAL VCC connects all
subcircuits with the internal node name VCC.
Ordinarily, in a subcircuit, the node name consists of the circuit number,
concatenated to the node name. When you use a .GLOBAL statement,
HSPICE or HSPICE RF does not concatenate the node name with the circuit
number, and assigns only the global name. You can then exclude the power
node name in the subcircuit or macro call.
Circuit Temperature
To specify the circuit temperature for a HSPICE or HSPICE RF simulation, use
the .TEMP statement, or the TEMP parameter in the .DC, .AC, and .TRAN
statements. HSPICE compares the circuit simulation temperature against the
reference temperature in the TNOM control option. HSPICE or HSPICE RF uses
the difference between the circuit simulation temperature and the TNOM
reference temperature to define derating factors for component values.
In HSPICE RF, you can use multiple .TEMP statements to specify multiple
temperatures for different portions of the circuit. HSPICE permits only one
temperature for the entire circuit. Multiple .TEMP statements in a circuit behave
as a sweep function.
Data-Driven Analysis
In data-driven analysis, you can modify any number of parameters, then use
the new parameter values to perform an operating point, DC, AC, or transient
analysis. An array of parameter values can be either inline (in the simulation
input file) or stored as an external ASCII file. The .DATA statement associates
a list of parameter names with corresponding values in the array.
HSPICE supports the entire functionality of the .DATA statement. However,
HSPICE RF supports .DATA only for:
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Data-driven analysis.
■
Inline or external data files.
For more details about using the .DATA statement in different types of analysis,
see Chapter 8, “Initializing DC/Operating Point Analysis,”, and Chapter 9,
“Transient Analysis.”.
Library Calls and Definitions
To create and read from libraries of commonly-used commands, device
models, subcircuit analysis, and statements in library files, use the .LIB call
statement. As HSPICE or HSPICE RF encounters each .LIB call name in the
main data file, it reads the corresponding entry from the designated library file,
until it finds an .ENDL statement.
You can also place a .LIB call statement in an .ALTER block.
Library Building Rules
1. A library cannot contain .ALTER statements.
A library can contain nested .LIB calls to itself or to other libraries. If you
use a relative path in a nested .LIB call, the path starts from the directory
of the parent library, not from the work directory. If the path starts from the
work directory, HSPICE can also find the library, but it prints a warning. The
depth of nested calls is limited only by the constraints of your system
configuration.
2. A library cannot contain a call to a library of its own entry name, within the
same library file.
3. A HSPICE or HSPICE RF library cannot contain the .END statement.
4. .ALTER processing cannot change .LIB statements, within a file that
an .INCLUDE statement calls.
Automatic Library Selection
Automatic library selection searches a sequence of up to 40 directories. The
hspice.ini file sets the default search paths.
Note: HSPICE RF does not read the hspice.ini file.
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Use this file for directories that you want HSPICE to always search. HSPICE
searches for libraries in the order specified in .OPTION SEARCH statements.
When HSPICE encounters a subcircuit call, the search order is:
1. Read the input file for a .SUBCKT or .MACRO with the specified call name.
2. Read any .INC files or .LIB files for a .SUBCKT or .MACRO with the
specified call name.
3. Search the directory containing the input file for the call_name.inc file.
4. Search the directories in the .OPTION SEARCH list.
You can use the HSPICE library search and selection features to simulate
process corner cases, using .OPTION SEARCH =‘<libdir>’ to target
different process directories. For example, if you store an input or output buffer
subcircuit in a file named iobuf.inc, you can create three copies of the file, to
simulate fast, slow and typical corner cases. Each file contains different
HSPICE transistor models, representing the different process corners. Store
these files (all named iobuf.inc) in separate directories.
Defining Parameters
The .PARAM statement defines parameters. Parameters in HSPICE or HSPICE
RF are names that have associated numeric values. You can also use either of
the following specialized methods to define parameters:
■
Predefined Analysis
■
Measurement Parameters
Predefined Analysis
HSPICE or HSPICE RF provides several specialized analysis types, which
require a way to control the analysis. For the syntax used in these .PARAM
commands, see the HSPICE Command Reference manual.
HSPICE or HSPICE RF supports the following predefined analysis parameters:
58
■
Temperature functions (fn)
■
Optimization guess/range
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HSPICE also supports the following predefined parameter types, that HSPICE
RF does not support:
■
frequency
■
time
■
Monte Carlo functions
Measurement Parameters
A .MEASURE statement produces a measurement parameter. In general, the
rules for measurement parameters are the same as those for standard
parameters. However, measurement parameters are not defined in a .PARAM
statement, but directly in the .MEASURE statement. For more information, see
.MEASURE Parameter Types on page 269.
Altering Design Variables and Subcircuits
The following rules apply when you use an .ALTER block to alter design
variables and subcircuits in HSPICE. This section does not apply to HSPICE
RF.
1. If the name of a new element, .MODEL statement, or subcircuit definition is
identical to the name of an original statement of the same type, then the new
statement replaces the old. Add new statements in the input netlist file.
2. You can alter element and .MODEL statements within a subcircuit definition.
You can also add a new element or .MODEL statement to a subcircuit
definition. To modify the topology in subcircuit definitions, put the element
into libraries. To add a library, use .LIB; to delete, use .DEL LIB.
3. If a parameter name in a new .PARAM statement in the .ALTER module is
identical to a previous parameter name, then the new assigned value
replaces the old value.
4. If you used parameter (variable) values for elements (or model parameter
values) when you used .ALTER, use the .PARAM statement to change
these parameter values. Do not use numerical values to redescribe
elements or model parameters.
5. If you used an .OPTION statement (in an original input file or a .ALTER
block) to turn on an option, you can turn that option off.
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6. Each .ALTER simulation run prints only the actual altered input. A
special .ALTER title identifies the run.
7. .ALTER processing cannot revise .LIB statements within a file that
an .INCLUDE statement calls. However, .ALTER processing can
accept .INCLUDE statements, within a file that a .LIB statement calls.
Using Multiple .ALTER Blocks
This section does not apply to HSPICE RF.
1. For the first simulation run, HSPICE reads the input file, up to the
first .ALTER statement, and performs the analyses up to that .ALTER
statement.
2. After it completes the first simulation, HSPICE reads the input between the
first .ALTER statement, and either the next .ALTER statement or the .END
statement.
3. HSPICE then uses these statements to modify the input netlist file.
4. HSPICE then resimulates the circuit.
5. For each additional .ALTER statement, HSPICE performs the simulation
that precedes the first .ALTER statement.
6. HSPICE then performs another simulation, using the input between the
current .ALTER statement, and either the next .ALTER statement or
the .END statement.
If you do not want to rerun the simulation that precedes the first .ALTER
statement, every time you run an .ALTER simulation, then do the following:
1. Put the statements that precede the first .ALTER statement, into a library.
2. Use the .LIB statement in the main input file.
3. Put a .DEL LIB statement in the .ALTER section, to delete that library for
the .ALTER simulation run.
Connecting Nodes
Use a .CONNECT statement to connect two nodes in your HSPICE netlist, so
that simulation evaluates two nodes as only one node. Both nodes must be at
the same level in the circuit design that you are simulating: you cannot connect
nodes that belong to different subcircuits. You also cannot use this statement in
HSPICE RF.
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Deleting a Library
Use a .DEL LIB statement to remove library data from memory. The next time
you run a simulation, the .DEL LIB statement removes the .LIB call
statement, with the same library number and entry name, from memory. You
can then use a .LIB statement to replace the deleted library.
You can use a .DEL LIB statement with a .ALTER statement. HSPICE RF
does not support the .ALTER statement.
Ending a Netlist
An .END statement must be the last statement in the input netlist file. Text that
follows the .END statement is a comment, and has no effect on the simulation.
An input file that contains more than one simulation run must include an .END
statement for each simulation run. You can concatenate several simulations
into a single file.
Condition-Controlled Netlists (IF-ELSE)
You can use the IF-ELSE structure to change the circuit topology, expand the
circuit, set parameter values for each device instance, or select different model
cards in each IF-ELSE block.
.if (condition1)
<statement_block1>
# The following statement block in {braces} is
# optional, and you can repeat it multiple times:
{ .elseif (condition2)
<statement_block2>
}
# The following statement block in [brackets]
# is optional, and you cannot repeat it:
[ .else
<statement_block3>
]
.endif
■
In an .IF, .ELSEIF, or .ELSE condition statement, complex Boolean
expressions must not be ambiguous. For example, change (a==b &&
c>=d) to ( (a==b) && (c>=d) ).
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In an IF, ELSEIF, or ELSE statement block, you can include most valid
HSPICE or HSPICE RF analysis and output statements. The exceptions
are:
•
.END, .ALTER, .SUBCKT, .ENDS, .MACRO, .EOM, .GLOB AL, .DEL
LIB, .MALIAS, .ALIAS, .LIST, .NOLIST, and .CONNECT
statements.
•
search, d_ibis, d_imic, d_lv56, biasfi, modsrh, cmiflag,
nxx, and brief options.
■
You can include IF-ELSEIF-ELSE statements in subcircuits, but you cannot
include subcircuits in IF-ELSEIF-ELSE statements.
■
However, you can use IF-ELSEIF-ELSE blocks to select different
submodules, to structure the netlist (using .INC, .LIB, and .VEC
statements).
■
If two or more models in an IF-ELSE block have the same model name and
model type, they must also be the same revision level.
■
Parameters in an IF-ELSE block do not affect the parameter value within the
condition expression. HSPICE or HSPICE RF updates the parameter value
only after it selects the IF-ELSE block.
■
You can nest IF-ELSE blocks.
■
You can include an unlimited number of ELSEIF statements within an IFELSE block.
■
You cannot include sweep parameters or simulation results within an IFELSE block.
■
You cannot use an IF-ELSE block within another statement. In the following
example, HSPICE or HSPICE RF does not recognize the IF-ELSE block as
part of the resistor definition:
r 1 0
.if (r_val>10k)
+ 10k
.else
+ r_val
.endif
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Using Subcircuits
Using Subcircuits
Reusable cells are the key to saving labor in any CAD system. This also applies
to circuit simulation, in HSPICE or HSPICE RF.
■
To create and simulate a reusable circuit, construct it as a subcircuit.
■
Use parameters to expand the utility of a subcircuit.
Traditional SPICE includes the basic subcircuit, but does not provide a way to
consistently name nodes. However, HSPICE or HSPICE RF provides a simple
method for naming subcircuit nodes and elements: use the subcircuit call name
as a prefix to the node or element name.
In HSPICE RF, you cannot replicate output commands within subcircuit
(subckt) definitions.
Figure 9
Subcircuit Representation
MP
MN
INV
The following input creates an instance named X1 of the INV cell macro, which
consists of two MOSFETs, named MN and MP:
X1 IN OUT VD_LOCAL VS_LOCAL inv W = 20
.MACRO INV IN OUT VDD VSS W = 10 L = 1 DJUNC = 0
MP OUT IN VDD VDD PCH W = W L = L DTEMP = DJUNC
MN OUT IN VSS VSS NCH W = ’W/2’ L = L DTEMP = DJUNC
.EOM
Note: To access the name of the MOSFET, inside of the INV subcircuit that X1
calls, the names are X1.MP and X1.MN. So to print the current that flows
through the MOSFETs, use .PRINT I (X1.MP).
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Using Subcircuits
Hierarchical Parameters
You can use two hierarchical parameters, the M (multiply) parameter and the S
(scale) parameter.
M (Multiply) Parameter
The most basic HSPICE subcircuit parameter or HSPICE RF is the M (multiply)
parameter. This keyword is common to all elements, including subcircuits,
except for voltage sources. The M parameter multiplies the internal component
values, which in effect creates parallel copies of the element or subcircuit. To
simulate 32 output buffers switching simultaneously, you need to place only one
subcircuit; for example,
X1 in out buffer M = 32
Multiply works hierarchically. For a subcircuit within a subcircuit, HSPICE or
HSPICE RF multiplies the product of both levels. Do not assign a negative
value or zero as the M value.
Figure 10
How Hierarchical Multiply Works
X1 in out inv M = 2
M=8
mp out in vdd pch W = 10 L = 1 M = 4
M=6
mn out in vss nch W = 5 L = 1 M = 3
UNEXPANDED
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Using Subcircuits
S (Scale) Parameter
To scale a subcircuit, use the S (local scale) parameter. This parameter
behaves in much the same way as the M parameter in the preceding section.
.OPTION hier_scale=value
.OPTION scale=value
X1 node1 node2 subname S = valueM parameter
The OPTION HIER_SCALE statement defines how HSPICE or HSPICE RF
interprets the S parameter, where value is either:
■
0 (the default), indicating a user-defined parameter, or
■
1, indicating a scale parameter.
The .OPTION SCALE statement defines the original (default) scale of the
subcircuit. The specified S scale is relative to this default scale of the subcircuit.
The scale in the subname subcircuit is value*scale. Subcircuits can originate
from multiple sources, so scaling is multiplicative (cumulative) throughout your
design hierarchy.
x1 a y inv S=1u
subckt inv in out
x2 a b kk S=1m
.ends
In this example:
■
HSPICE or HSPICE RF scales the X1 subcircuit by the first S scaling value,
1u*scale.
■
Because scaling is cumulative, X2 (a subcircuit of X1) is then scaled, in
effect, by the S scaling values of both X1 and X2: 1m*1u*scale.
Using Hierarchical Parameters to Simplify Simulation
You can use the hierarchical parameter to simplify simulations. An example is
shown in the following listing and Figure 11.
X1 D Q Qbar CL CLBAR dlatch flip = 0
.macro dlatch
+ D Q Qbar CL CLBAR flip = vcc
.nodeset v(din) = flip
xinv1 din qbar inv
xinv2 Qbar Q inv
m1 q CLBAR din nch w = 5 l = 1
m2 D CL din nch w = 5 l = 1
.eom
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Using Subcircuits
Figure 11
D Latch with Nodeset
Q
clbar
cl
Q
D
din
.Nodeset
HSPICE does not limit the size or complexity of subcircuits; they can contain
subcircuit references, and any model or element statement. However, in
HSPICE RF, you cannot replicate output commands within subcircuit
definitions. To specify subcircuit nodes in .PRINT or .PLOT statements,
specify the full subcircuit path and node name.
Undefined Subcircuit Search
This section does not apply to HSPICE RF.
If a subcircuit call is in a data file that does not describe the subcircuit, HSPICE
automatically searches the:
1. Present directory for the file.
2. Directories specified in .OPTION SEARCH = “directory_path_name”
statements.
3. Directory where the Discrete Device Library is located.
HSPICE searches for the model reference name file that has an .inc suffix. For
example, if the data file includes an undefined subcircuit, such as
X 1 1 2 INV, HSPICE searches the system directories for the inv.inc file and
when found, places that file in the calling data file.
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Subcircuit Call Statement Discrete Device Libraries
Subcircuit Call Statement Discrete Device Libraries
The Synopsys Discrete Device Library (DDL) is a collection of HSPICE device
models of discrete components, which you can use with HSPICE or HSPICE
RF. The $installdir/parts directory contains the various subdirectories that form
the DDL. Synopsys used its own ATEM discrete device characterization system
to derive the BJT, MESFET, JFET, MOSFET, and diode models from laboratory
measurements. The behavior of op-amp, timer, comparator, SCR, and
converter models closely resembles that described in manufacturers’ data
sheets. HSPICE and HSPICE RF have a built-in op-amp model generator.
Note: The value of the $installdir environment variable is the pathname to
the directory where you installed HSPICE or HSPICE RF. This installation
directory contains subdirectories, such as /parts and /bin. It also contains
certain files, such as a prototype meta.cfg file, and the license files.
DDL Library Access
To include a DDL library component in a data file, use the X subcircuit call
statement with the DDL element call. The DDL element statement includes the
model name, which the actual DDL library file uses.
For example, the following element statement creates an instance of the
1N4004 diode model:
X1 2 1 D1N4004
Where D1N4004 is the model name.
See Element and Source Statements on page 48 and the HSPICE Elements
and Device Models Manual for descriptions of element statements.
Optional parameter fields in the element statement can override the internal
specification of the model. For example, for op-amp devices, you can override
the offset voltage, and the gain and offset current. Because the DDL library
devices are based on HSPICE circuit-level models, simulation automatically
compensates for the effects of supply voltage, loading, and temperature.
HSPICE or HSPICE RF accesses DDL models in several ways:
■
The installation script creates an hspice.ini initialization file.
■
HSPICE or HSPICE RF writes the search path for the DDL and vendor
libraries into a .OPTION SEARCH = ‘<lib_path>’ statement.
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Subcircuit Call Statement Discrete Device Libraries
This provides immediate access to all libraries for all users. It also
automatically includes the models in the input netlist. If the input netlist
references a model or subcircuit, HSPICE or HSPICE RF searches the
directory to which the DDLPATH environment variable points for a file with
the same name as the reference name. This file is an include file so its
filename suffix is .inc. HSPICE installation sets the DDLPATH variable in the
meta.cfg configuration file.
■
Set .OPTION SEARCH = ‘<lib_path>’ in the input netlist.
Use this method to list the personal libraries to search. HSPICE or HSPICE
RF first searches the default libraries referenced in the hspice.ini file, then
searches libraries in the order listed in the input file.
■
Directly include a specific model, using the .INCLUDE statement. For
example, to use a model named T2N2211, store the model in a file named
T2N2211.inc, and put the following statement in the input file:
.INCLUDE <path>/T2N2211.inc
This method requires you to store each model in its own .inc file, so it is not
generally useful. However, you can use it to debug new models, when you
test only a small number of models.
Vendor Libraries
The vendor library is the interface between commercial parts and circuit or
system simulation..
■
ASIC vendors provide comprehensive cells, corresponding to inverters,
gates, latches, and output buffers.
■
Memory and microprocessor vendors supply input and output buffers.
■
Interface vendors supply complete cells for simple functions and output
buffers, to use in generic family output.
■
Analog vendors supply behavioral models.
To avoid name and parameter conflicts, models in vendor cell libraries should
be within the subcircuit definitions.
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Figure 12
Vendor Library Usage
x1 in out vdd vss buffer_f
.OPTION search = ‘/usr/lib/vendor’
/usr/lib/vendor/buffer_f.inc
/usr/lib/vendor/skew.dat
.macro buffer_f in out vdd vss
.lib ‘/usr/lib/vendor/skew.dat’ ff
.lib ff $ fast model
.param vendor_xl = -.1u
.inc ‘/usr/lib/vendor/model.dat’
.endl ff
.inc ‘/usr/lib/vendor/buffer.inc’
.eom
/usr/lib/vendor/buffer.inc
/usr/lib/vendor/model.dat
.model nch nmos level = 28
+ xl = vendor_xl ...
.macro buffer in out vdd vss
m1 out in vdd vdd nch w = 10 l = 1
...
Subcircuit Library Structure
Your library structure must adhere to the .INCLUDE statement specification in
the implicit subcircuit. You can use this statement to specify the directory that
contains the <subname>.inc subcircuit file, and then reference the <subname>
in each subcircuit call.
The component naming conventions for each subcircuit is:
<subname>.inc
Store the subcircuit in a directory that is accessible by a.OPTION
SEARCH = ‘<lib_path>’ statement.
Create subcircuit libraries in a hierarchy. Typically, the top-level subcircuit fully
describes the input/output buffer; any hierarchy is buried inside. The buried
hierarchy can include model statements, lower-level components, and
parameter assignments. Your library cannot use .LIB or .INCLUDE
statements anywhere in the hierarchy.
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Passive Elements
4
Elements
4
Describes the syntax for the basic elements of a circuit netlist in
HSPICE or HSPICE RF.
Elements are local and sometimes customized instances of a device model
specified in your design netlist.
For descriptions of the standard device models on which elements (instances)
are based, see the HSPICE Elements and Device Models Manual and the
HSPICE MOSFET Models Manual.
Passive Elements
This section describes the passive elements: resistors, capacitors, and
inductors.
Values for Elements
HSPICE RF accepts equation-based resistors and capacitors. You can specify
the value of a resistor or capacitor as an arbitrary equation, involving node
voltages or variable parameters. Unlike HSPICE, you cannot use parameters to
indirectly reference node voltages in HSPICE RF.
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Passive Elements
Resistor Elements in a HSPICE or HSPICE RF Netlist
Rxxx n1 n2 <mname> Rval <TC1 <TC2><TC>> <SCALE=val> <M=val>
+ <AC=val> <DTEMP=val> <L=val> <W=val> <C=val>
+ <NOISE = val>
Rxxx n1 n2 <mname> <R = >resistance <<TC1 = >val>
+ <<TC2 = >val> <<TC = >val> <SCALE = val> <M = val>
+ <AC = val> <DTEMP = val> <L = val> <W = val>
+ <C = val> <NOISE = val>
Rxxx n1 n2 R=‘equation’ ...
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Parameter
Description
Rxxx
Resistor element name. Must begin with R, followed by up to 1023
alphanumeric characters.
n1
Positive terminal node name.
n2
Negative terminal node name.
mname
Resistor model name. Use this name in elements, to reference a
resistor model.
TC
TC1 alias. The current definition overrides the previous definition.
TC1
First-order temperature coefficient for the resistor. Refer to the “Using
Passive Device Models” chapter in the HSPICE Elements and Device
Models Manual for temperature-dependent relations.
TC2
Second-order temperature coefficient for the resistor.
SCALE
Element scale factor; scales resistance and capacitance by its value.
Default = 1.0.
R=
resistance
Resistance value at room temperature. This can be:
•
•
•
•
•
a numeric value in ohms
a parameter in ohms
a function of any node voltages
a function of branch currents
any independent variables such as time, hertz, and temper
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Parameter
Description
M
Multiplier to simulate parallel resistors. For example, for two parallel
instances of a resistor, set M = 2, to multiply the number of resistors by
2. Default = 1.0.
AC
Resistance for AC analysis. Default = Reff.
DTEMP
Temperature difference between the element and the circuit, in degrees
Celsius. Default = 0.0.
L
Resistor length in meters. Default=0.0, if you did not specify L in a
resistor model.
W
Resistor width. Default = 0.0, if you did not specify W in the model.
C
Capacitance connected from node n2 to bulk. Default = 0.0, if you did
not specify C in a resistor model.
user-defined Can be a function of any node voltages, element currents, temperature,
equation
frequency, or time
NOISE
• NOISE = 0, do not evaluate resistor noise.
• NOISE = 1, evaluate resistor noise (default).
Resistance can be a value (in units of ohms) or an equation. Required
parameters are the two nodes, and the resistance or model name. If you
specify other parameters, the node and model name must precede those
parameters. Other parameters can follow in any order. If you specify a resistor
model (see the HSPICE Elements and Device Models Manual), the resistance
value is optional.
HSPICE Examples
In the following example, the R1 resistor connects from the Rnode1 node to the
Rnode2 node, with a resistance of 100 ohms.
R1 Rnode1 Rnode2 100
The RC1 resistor connects from node 12 to node 17, with a resistance of 1
kilohm, and temperature coefficients of 0.001 and 0.
RC1 12 17 R = 1k TC1 = 0.001 TC2 = 0
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The Rterm resistor connects from the input node to ground, with a resistance
determined by the square root of the analysis frequency (non-zero for AC
analysis only).
Rterm input gnd R = ’sqrt(HERTZ)’
The Rxxx resistor, from node 98999999 to node 87654321, with a resistance of
1 ohm for DC and time-domain analyses, and 10 gigohms for AC analyses.
Rxxx 98999999 87654321 1 AC = 1e10
HSPICE RF Examples
Some basic examples for HSPICE RF include:
■
R1 is a resistor whose resistance follows the voltage at node c.
R1 1 0 ‘v(c)’
■
R2 is a resistor whose resistance is the sum of the absolute values of nodes
c and d.
R2 1 0 ‘abs(v(c)) + abs(v(d))’
■
R3 is a resistor whose resistance is the sum of the rconst parameter, and
100 times tx1 for a total of 1100 ohms.
.PARAM rconst=100 tx1=10
R3 4 5 ‘rconst + tx1 * 100’
Linear Resistors
Rxxx node1 node2 < modelname > < R = > value < TC1 = val >
+ < TC2 = val > < W = val > < L = val > < M = val >
+ < C = val > < DTEMP = val > < SCALE = val >
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Parameter
Description
Rxxx
Name of a resistor.
node1 and node2
Names or numbers of the connecting nodes.
modelname
Name of the resistor model.
value
Nominal resistance value, in ohms.
R
Resistance, in ohms, at room temperature.
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Parameter
Description
TC1, TC2
Temperature coefficient.
W
Resistor width.
L
Resistor length.
M
Parallel multiplier.
C
Parasitic capacitance between node2 and the substrate.
DTEMP
Temperature difference between element and circuit.
SCALE
Scaling factor.
Example
R1 1 2 10.0
Rload 1 GND RVAL
.param rx=100
R3 2 3 RX TC1 = 0.001 TC2 = 0
RP X1.A X2.X5.B .5
.MODEL RVAL R
In the example above, R1 is a simple 10Ω linear resistor and Rload calls a
resistor model named RVAL, which is defined later in the netlist.
Note: If a resistor calls a model, then you do not need to specify a constant
resistance, as you do with R1.
■
R3 takes its value from the RX parameter, and uses the TC1 and TC2
temperature coefficients, which become 0.001 and 0, respectively.
■
RP spans across different circuit hierarchies, and is 0.5Ω.
Behavioral Resistors in HSPICE or HSPICE RF
Rxxx n1 n2 . . . <R=> ‘equation’ . . .
Note: The equation can be a function of any node voltage or branch current,
and any independent variables such as time, hertz, or temper.
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Example
R1 A B R = ‘V(A) + I(VDD)’
Frequency-Dependent Resistors
Rxxx n1 n2 R=equation <CONVOLUTION=[0|1|2] <FBASE=value>
+ <FMAX=value>>
Parameter
CONVOLUTION
Description
Indicates which method is used.
• 0 : Acts the same as the conventional method. This is the
default.
• 1 : Applies recursive convolution, and if the rational function
is not accurate enough, it switches to linear convolution.
• 2 : Applies linear convolution.
FBASE
Specifies the lower bound of the transient analysis frequency.
For CONVOLUTION=1 mode, HSPICE starts sampling at this
frequency. For CONVOLUTION=2 mode, HSPICE uses this
value as the base frequency point for Inverse Fourier
Transformation.
For recursive convolution, the default value is 0Hz, and for linear
convolution, HSPICE uses the reciprocal of the transient
period.
FMAX
Specifies the possible maximum frequency of interest. The
default value is the frequency point where the function reaches
close enough to infinity value, assuming that the monotonous
function is approaching the infinity value and that it is taken at
10THz.
The equation should be a function of HERTZ. If CONVOLUTION
is turned on when a HERTZ keyword is not used in the equation,
it is automatically be turned off to let the resistor behave as
conventional.The equation can be a function of temperature,
but it cannot be node voltage or branch current and time.
The equation can only be a function of time-independent variables such as
hertz, and temperature.
Example
R1 1 2 r='1.0 + 1e-5*sqrt(HERTZ)' CONVOLUTION=1
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Skin Effect Resistors
Rxxx n1 n2 R=value Rs=value
The Rs indicates the skin effect coefficient of the resistor.
The complex impedance of the resistor can be expressed as the following
equation:
R(f) = Ro + (1+j)*Rs*sqrt(f)
The Ro, j, and f are DC resistance, imaginably unit (j^2 = -1) and frequency,
respectively.
Capacitors
Cxxx n1 n2 <mname> <C = >capacitance <<TC1 = >val>
+ <<TC2 = >val> <SCALE = val> <IC = val> <M = val>
+ <W = val> <L = val> <DTEMP = val>
Cxxx n1 n2 <C = >’equation’ <CTYPE = 0|1>
+ <above_options...>
Polynomial form:
Cxxx n1 n2 POLY c0 c1... <above_options...>
Parameter
Description
Cxxx
Capacitor element name. Must begin with C, followed by up to 1023
alphanumeric characters.
n1
Positive terminal node name.
n2
Negative terminal node name.
mname
Capacitance model name. Elements use this name to reference a
capacitor.
C = capacitance Capacitance at room temperature—a numeric value or a parameter
in farads.
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Parameter
Description
TC1
First-order temperature coefficient for the capacitor. Refer to
Chapter 2, “Using Passive Device Models”, in the HSPICE
Elements and Device Models Manual for temperature-dependant
relations.
TC2
Second-order temperature coefficient for the capacitor.
SCALE
Element scale parameter, scales capacitance by its value.
Default = 1.0.
IC
Initial voltage across the capacitor, in volts. If you specify UIC in
the .TRAN statement, HSPICE or HSPICE RF uses this value as
the DC operating point voltage. The .IC statement overrides it.
M
Multiplier, used to simulate multiple parallel capacitors.
Default = 1.0
W
Capacitor width, in meters. Default = 0.0, if you did not specify W in
a capacitor model.
L
Capacitor length, in meters. Default = 0.0, if you did not specify L in
a capacitor model.
DTEMP
Element temperature difference from the circuit temperature, in
degrees Celsius. Default = 0.0.
C = ’equation’
Capacitance at room temperature, specified as a function of:
• any node voltages
• any branch currents
• any independent variables such as time, hertz, and temper
CTYPE
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Determines capacitance charge calculation for elements with
capacitance equations. If the C capacitance is a function of
V(n1<,n2>), set CTYPE = 0. Use this setting correctly, to ensure
proper capacitance calculations, and correct simulation results.
Default = 0.
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Parameter
Description
POLY
Keyword, to specify capacitance as a non-linear polynomial.
c0 c1...
Coefficients of a polynomial, described as a function of the voltage
across the capacitor. c0 represents the magnitude of the 0th order
term, c1 represents the magnitude of the 1st order term, and so on.
You cannot use parameters as coefficient values.
You can specify capacitance as a numeric value, in units of farads, as an
equation, or as a polynomial of the voltage. The only required fields are the two
nodes, and the capacitance or model name.
■
If you use the parameter labels, the nodes and model name must precede
the labels. Other arguments can follow in any order.
■
If you specify a capacitor model (see the HSPICE Elements and Device
Models Manual), the capacitance value is optional.
If you use an equation to specify capacitance, the CTYPE parameter
determines how HSPICE calculates the capacitance charge. The calculation is
different, depending on whether the equation uses a self-referential voltage
(that is, the voltage across the capacitor, whose capacitance is determined by
the equation).
To avoid syntax conflicts, if a capacitor model has the same name as a
capacitance parameter, HSPICE or HSPICE RF uses the model name.
Example 1
In the following example, C1 assumes its capacitance value from the model,
not the parameter.
.PARAMETER CAPXX = 1
C1 1 2 CAPXX
.MODEL CAPXX C CAP = 1
Example 2
In the following example, the C1 capacitors connect from node 1 to node 2, with
a capacitance of 20 picofarads:
C1 1 2 20p
In this next example, Cshunt refers to three capacitors in parallel, connected
from the node output to ground, each with a capacitance of 100 femtofarads.
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Cshunt output gnd C = 100f M = 3
The Cload capacitor connects from the driver node to the output node. The
capacitance is determined by the voltage on the capcontrol node, times 1E-6.
The initial voltage across the capacitor is 0 volts.
Cload driver output C = ’1u*v(capcontrol)’ CTYPE = 1
+ IC = 0v
The C99 capacitor connects from the in node to the out node. The capacitance
is determined by the polynomial C = c0 + c1*v + c2*v*v, where v is the voltage
across the capacitor.
C99 in out POLY 2.0 0.5 0.01
Linear Capacitors
Cxxx node1 node2 < modelname > < C = > value < TC1 = val >
+ < TC2 = val > <W = val > < L = val > < DTEMP = val >
+ < M = val > < SCALE = val > < IC = val >
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Parameter
Description
Cxxx
Name of a capacitor. Must begin with C, followed by up to 1023
alphanumeric characters.
node1 and node2
Names or numbers of connecting nodes.
value
Nominal capacitance value, in Farads.
modelname
Name of the capacitor model.
C
Capacitance, in Farads, at room temperature.
TC1, TC2
Specifies the temperature coefficient.
W
Capacitor width.
L
Capacitor length.
M
Multiplier to simulate multiple parallel capacitors.
DTEMP
Temperature difference between element and circuit.
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Parameter
Description
SCALE
Scaling factor.
IC
Initial capacitor voltage.
Example
Cbypass 1 0 10PF
C1 2 3 CBX
.MODEL CBX C
CB B 0 10P IC = 4V
CP X1.XA.1 0 0.1P
In this example:
■
Cbypass is a straightforward, 10-picofarad (PF) capacitor.
■
C1, which calls the CBX model, does not have a constant capacitance.
■
CB is a 10 PF capacitor, with an initial voltage of 4V across it.
■
CP is a 0.1 PF capacitor.
Frequency-Dependent Capacitors
You can specify frequency-dependent capacitors using the C=’equation’
with the HERTZ keyword. The HERTZ keyword represents the operating
frequency. In time domain analyses, an expression with the HERTZ keyword
behaves differently according to the value assigned to the CONVOLUTION
keyword.
Syntax
Cxxx n1 n2 C=’equation’ <CONVOLUTION=[0|1|2]
+ <FBASE=val> <FMAX=val>>
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Parameter
Description
n1 n2
Names or numbers of connecting nodes.
equation
Expressed as a function of HERTZ. If CONVOLUTION=1 or 2 and
HERTZ is not used in the equation, CONVOLUTION is turned off
and the capacitor behaves conventionally.
The equation can be a function of temperature, but it does not
support variables of node voltage, branch current, or time. If
these variables exist in the expression and CONVOLUTION=1 or
2, then only their values at the operating point are considered in
calculation.
CONVOLUTION
Specifies the method used.
• 0 (default): HERTZ=0 in time domain analysis.
• 1 or 2: performs Inverse Fast Fourier Transformation (IFFT)
linear convolution.
FBASE
Base frequency to use for transient analysis. This value becomes
the base frequency point for Inverse Fast Fourier Transformation
(IFFT) when CONVOLUTION=1 or 2. If you do not set this value,
the base frequency is a reciprocal value of the transient period.
FMAX
Maximum frequency to use for transient analysis. Used as the
maximum frequency point for Inverse Fourier Transformation. If
you do not set this value, the reciprocal value of RISETIME is
taken.
Example
C1 1 2 C='1e-6 - HERTZ/1e16' CONVOLUTION=1 fbase=10
+ fmax=30meg
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Behavioral Capacitors in HSPICE or HSPICE RF
Cxxx n1 n2 . . . C=‘equation’ CTYPE=0 or 1
Parameter
Description
CTYPE
Determines the calculation mode for elements that use capacitance
equations. Set this parameter carefully, to ensure correct simulation
results. HSPICE RF extends the definition and values of CTYPE,
relative to HSPICE:
• CTYPE=0, if C depends only on its own terminal voltages—that is, a
function of V(n1<, n2>).
• CTYPE=1, if C depends only on outside voltages or currents.
• CTYPE=2, if C depends on both its own terminal and outside
voltages. This is the default for HSPICE RF. HSPICE does not
support C=2.
You can specify the capacitor value as a function of any node voltage or branch
current, and any independent variables such as time, hertz, and temper.
Example
C1 1 0 C=’1e-9*V(10)’ CTYPE=1
V10 10 0 PWL(0,1v t1,1v t2,4v)
DC Block Capacitors
Cxxx node1 node2 <C=> INFINITY
<IC = val>
When the capacitance of a capacitor is infinity, this element is called a “DC
block.” In HSPICE, you specify an INFINITY value for such capacitors.
HPSICE does not support any other capacitor parameters for DC block
elements, because HSPICE assumes that an infinite capacitor value is
independent of any scaling factors.
The DC block acts as an open circuit for all DC analyses. HSPICE calculates
the DC voltage across the nodes of the circuit. In all other (non-DC) analyses, a
DC voltage source of this value represents the DC block—HSPICE does not
allow dv/dt variations.
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Charge-Conserved Capacitors
Cxxx node1 node2 q=’expression’
HSPICE supports AC, DC, TRAN, and PZ analyses for charge-conserved
capacitors.
The expression supports the following parameters and variables:
■
■
parameters
•
node voltages
•
branch currents
variables
•
time
•
temper
•
hertz
Note: The hertz variable is not supported in transient analyses.
Parameters must be used directly in an equation. HSPICE does not support
parameters that represent an equation containing variables.
Error Handling. If you use an unsupported parameter in an expression,
HSPICE issues an error message and aborts the simulation. HSPICE ignores
unsupported analysis types and then issues warning a message.
Limitations.
capacitors:
The following syntax does not support charge-conserving
Cxx node1 node2 C=’expression’
Capacitor equations are not implicitly converted to charge equations.
Example 1: Capacitance-based Capacitor
C1 a b C = ‘Co*(1+alpha*V(a,b)’ ctype=0
You can obtain Q by integrating ‘C’ w.r.t V(a,b)
Example 2: Charge-based Capacitor
C1 a b Q = ‘Co*V(a,b)(1+0.5*alpha*V(a,b))
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Example 3: Capacitance-based Capactor
.option list node post
r1 1 2 100
r2 3 0 200
Vin 1 0 pulse(0 5v 1ns 2ns 2ns 10ns 20ns)
C1 2 3 c = 'cos(v(2,3)) + v(1,2)’ ctype=2
.tran 1ns 100ns
.print tran i(c1)
.end
Example 4: Charge-based Capacitor
.option list node post
r1 1 2 100
r2 3 0 200
Vin 1 0 pulse(0 5v 1ns 2ns 2ns 10ns 20ns)
C1 2 3 q = 'sin(v(2,3)) + v(2,3)*v(1,2)'
.tran 1ns 100ns
.print tran i(c1)
.end
Inductors
General form:
Lxxx n1 n2 <L = >inductance <mname> <<TC1 = >val>
+ <<TC2 = >val> <SCALE = val> <IC = val> <M = val>
+ <DTEMP = val> <R = val>
Lxxx n1 n2 L = ‘equation’ <LTYPE = val> <above_options...>
Polynomial form:
Lxxx n1 n2 POLY c0 c1... <above_options...>
Magnetic winding form:
Lxxx n1 n2 NT = turns <above_options...>
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Parameter
Description
Lxxx
Inductor element name. Must begin with L, followed by up to
1023 alphanumeric characters.
n1
Positive terminal node name.
n2
Negative terminal node name.
TC1
First-order temperature coefficient for the inductor. Refer to
Chapter 2, “Using Passive Device Models”, in the HSPICE
Elements and Device Models Manual for temperature-dependent
relations.
TC2
Second-order temperature coefficient for the inductor.
SCALE
Element scale parameter; scales inductance by its value.
Default = 1.0.
IC
Initial current through the inductor, in amperes. HSPICE or
HSPICE RF uses this value as the DC operating point voltage,
when you specify UIC in the .TRAN statement. The .IC
statement overrides it.
L = inductance
Inductance value. This can be:
•
•
•
•
•
86
a numeric value, in henries
a parameter in henries
a function of any node voltages
a function of branch currents
any independent variables such as time, hertz, and
temper
M
Multiplier, used to simulate parallel inductors. Default = 1.0.
DTEMP
Temperature difference between the element and the circuit, in
degrees Celsius. Default = 0.0.
R
Resistance of the inductor, in ohms. Default = 0.0.
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Parameter
Description
L = ‘equation’
Inductance at room temperature, specified as:
• a function of any node voltages
• a function of branch currents
• any independent variables such as time, hertz, and
temper
LTYPE
Calculates inductance flux for elements, using inductance
equations. If the L inductance is a function of I(Lxxx), then set
LTYPE = 0. Otherwise, set LTYPE = 1. Use this setting correctly,
to ensure proper inductance calculations, and correct simulation
results. Default = 0.
POLY
Keyword that specifies the inductance, calculated by a
polynomial.
c0 c1...
Coefficients of a polynomial in the current, describing the
inductor value. c0 is the magnitude of the 0th order term, c1 is the
magnitude of the 1st order term, and so on.
NT = turns
Number of turns of an inductive magnetic winding.
mname
Saturable core model name. See Chapter 2, “Using Passive
Device Models”, in the HSPICE Elements and Device Models
Manual for model information.
In this syntax, the inductance can be either a value (in units of henries), an
equation, a polynomial of the current, or a magnetic winding. Required fields
are the two nodes, and the inductance or model name.
■
If you specify parameters, the nodes and model name must be first. Other
parameters can be in any order.
■
If you specify an inductor model (see Chapter 2 in the HSPICE Elements
and Device Models Manual), the inductance value is optional.
Example 1
In the following example, the L1 inductor connects from the coilin node to the
coilout node, with an inductance of 100 nanohenries.
L1 coilin coilout 100n
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Example 2
The Lloop inductor connects from node 12 to node 17. Its inductance is 1
microhenry, and its temperature coefficients are 0.001 and 0.
Lloop 12 17 L = 1u TC1 = 0.001 TC2 = 0
Example 3
The Lcoil inductor connects from the input node to ground. Its inductance is
determined by the product of the current through the inductor, and 1E-6.
Lcoil input gnd L = ’1u*i(input)’ LTYPE = 0
Example 4
The L99 inductor connects from the in node to the out node. Its inductance is
determined by the polynomial L = c0 + c1*i + c2*i*i, where i is the current
through the inductor. The inductor also has a specified DC resistance of 10
ohms.
L99 in out POLY 4.0 0.35 0.01 R = 10
Example 5
The L inductor connects from node 1 to node, as a magnetic winding element,
with 10 turns of wire.
L 1 2 NT = 10
Mutual Inductors
General form:
Kxxx Lyyy Lzzz <K = >coupling
Mutual core form:
Kaaa Lbbb <Lccc ... <Lddd>> mname <MAG = magnetization>
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Parameter
Description
Kxxx
Mutual inductor element name. Must begin with K, followed by up
to 1023 alphanumeric characters.
Lyyy
Name of the first of two coupled inductors.
Lzzz
Name of the second of two coupled inductors.
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Parameter
Description
K = coupling
Coefficient of mutual coupling. K is a unitless number, with
magnitude > 0 and < 1. If K is negative, the direction of coupling
reverses. This is equivalent to reversing the polarity of either of
the coupled inductors. Use the K = coupling syntax when using a
parameter value or an equation.
Kaaa
Saturable core element name. Must begin with K, followed by up
to 1023 alphanumeric characters.
Lbbb, Lccc, Lddd
Names of the windings about the Kaaa core. One winding
element is required, and each winding element must use the
magnetic winding syntax.
mname
Saturable core model name. See Chapter 2, “Using Passive
Device Models”, in the HSPICE Elements and Device Models
Manual for model information.
MAG =
magnetization
Initial magnetization of the saturable core. You can set this to +1,
0, or -1, where +/- 1 refer to positive and negative values of the
BS model parameter (see Chapter 2, “Using Passive Device
Models”, in the HSPICE Elements and Device Models Manual).
In this syntax, coupling is a unitless value, from zero to one, representing the
coupling strength. If you use parameter labels, the nodes and model name
must be first. Other arguments can be in any order. If you specify an inductor
model (see the HSPICE Elements and Device Models Manual), the inductance
value is optional.
You can determine the coupling coefficient, based on geometric and spatial
information. To determine the final coupling inductance, HSPICE or HSPICE
RF divides the coupling coefficient by the square-root of the product of the selfinductances.
When using the mutual inductor element to calculate the coupling between
more than two inductors, HSPICE or HSPICE RF can automatically calculate
an approximate second-order coupling. See the third example below for a
specific situation.
Note: The automatic inductance calculation is an estimation, and is accurate for
a subset of geometries. The second-order coupling coefficient is the product
of the two first-order coefficients, which is not correct for many geometries.
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Example 1
The Lin and Lout inductors are coupled, with a coefficient of 0.9.
K1 Lin Lout 0.9
Example 2
The Lhigh and Llow inductors are coupled, with a coefficient equal to the value
of the COUPLE parameter.
Kxfmr Lhigh Llow K = COUPLE
■
The K1 mutual inductor couples L1 and L2.
■
The K2 mutual inductor couples L2 and L3.
Example 3
The coupling coefficients are 0.98 and 0.87. HSPICE or HSPICE RF
automatically calculates the mutual inductance between L1 and L3, with a
coefficient of 0.98*0.87 = 0.853.
K1 L1 L2 0.98
K2 L2 L3 0.87
Ideal Transformer
Kxxxx Li Lj <k=> IDEAL
Ideal transformers use IDEAL keyword with the K element to designate ideal K
transformer coupling.
This keyword activates the following equation set for non-DC values, which is
presented here with multiple coupled inductors. Ij is the current into the first
terminal of Lj.
V1/sqrt(L1) = V2/sqrt(L2) = V3/sqrt(L3) = V4/sqrt(L4) = ...
(I1*sqrt(L1) + (I2*sqrt(L2) + (I3*sqrt(L3) + (I4*sqrt(L4) +
... = 0
HSPICE can solve any I or V interms of L ratios. DC is treated as expected—
inductors are treated as short circuits. Mutual coupling is ignored for DC.
Inductors that use the INFINITY keyword can be coupled with IDEAL K
Elements. In this situation, all inductors involved must have the INFINITY value,
and for K=IDEAL, the ratio of all L values is unity. Then, for two L values:
v2 = v1
i2 + i1 = 0
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Example 1
This example is a standard 5-pin ideal balun transformer subcircuit. Two pins
are grounded for standard operation. With all K values being IDEAL, the
absolute L values are not crucial—only their ratios are important.
**
**
all K's ideal
**
**
o----in**
Lin=1
** 0 o------**
.subckt BALUN1 in
Lin
in
gnd
Lo1
out1 gnd
Lo2
gnd
out2
K12
Lin Lo1
K13
Lin Lo2
K23
Lo1 Lo2
.ends
-----o out1
Lo1=.25
-----o 0
Lo2=.25
-----o out2
out1 out2
L=1
L=0.25
L=0.25
IDEAL
IDEAL
IDEAL
Example 2
This example is a 2-pin ideal 4:1 step-up balun transformer subcircuit with
shared DC path (no DC isolation). Input and output have a common pin, and
both inductors have the same value. Note that Rload = 4*Rin.
**
**
all K's ideal
**in o-------------------o out=in
**
L1=1
**
-----o 0
**
L2=1
**
-----o out2
**
** With all K's ideal, the actual L's values are
** not important -- only their ratio to each other.
.subckt BALUN2 in out2
L1
in
gnd
L=1
L2
gnd out2 L=1
K12
L1
L2
IDEAL
.ends
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Example 3
This example is a 3-pin ideal balun transformer with shared DC path (no DC
isolation). All inductors have the same value (here set to unity).
**
**
all K's ideal -----o out1
**
Lo2=1
**
-----o 0
**
Lo1=1
**
-----o out2
**
in
Lin=1
**
o-------------------o in
**
.subckt BALUN3 in out1 out2
Lo2
gnd out1 L=1
Lo1
out2 gnd
L=1
Lin
in
out2 L=1
K12
Lin Lo1 IDEAL
K13
Lin Lo2 IDEAL
K23
Lo1 Lo2 IDEAL
.ends
Linear Inductors
Lxxx node1 node2 <L => inductance <TC1 = val> <TC2 = val>
+ <M = val> <DTEMP = val> <IC = val>
92
Parameter
Description
Lxxx
Name of an inductor.
node1 and node2
Names or numbers of the connecting nodes.
inductance
Nominal inductance value, in Henries.
L
Inductance, in Henries, at room temperature.
TC1, TC2
Temperature coefficient.
M
Multiplier for parallel inductors.
DTEMP
Temperature difference between the element and the circuit.
IC
Initial inductor current.
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Example:
LX A B 1E-9
LR 1 0 1u IC = 10mA
■
LX is a 1 nH inductor.
■
LR is a 1 uH inductor, with an initial current of 10 mA.
Frequency-Dependent Inductors
You can specify frequency-dependent inductors using the L=’equation’ with
the HERTZ keyword. The HERTZ keyword represents the operating frequency.
In time domain analyses, an expression with the HERTZ keyword behaves
differently according to the value assigned to the CONVOLUTION keyword.
Syntax
Lxxx n1 n2 L=’equation’ <CONVOLUTION=[0|1|2] <FBASE=valule>
+ <FMAX=value>>
Parameter
Description
Lxxx
Inductor element name. Must begin with L, followed by up to
1023 alphanumeric characters
n1 n2
Positive and negative terminal node names.
equation
The equation should be a function of HERTZ. If CONVOLUTION
is turned on when a HERTZ keyword is not used in the equation,
CONVOLUTION is automatically be turned off and the inductor
behaves conventionally.The equation can be a function of
temperature, but it does not support variables of node voltage,
branch current, or time. If these variables exist in the equation
with CONVOLUTION turned on, only their values at the operating
point are considered in the calculation.
CONVOLUTION
Indicates which method is used.
• 0 (default): Acts the same as the conventional method.
• 1 : Applies recursive convolution, and if the rational function
is not accurate enough, it switches to linear convolution.
• 2 : Applies linear convolution.
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Parameter
Description
FBASE
Specifies the lower bound of the transient analysis frequency.
• For CONVOLUTION=1 mode, HSPICE starts sampling at this
frequency.
• For CONVOLUTION=2 mode, HSPICE uses this value as the
base frequency point for Inverse Fourier Transformation.
• For recursive convolution, the default value is 0Hz.
• For linear convolution, HSPICE uses the reciprocal of the
transient period.
FMAX
Specifies the possible maximum frequency of interest. The
default value is the frequency point where the function reaches
close enough to infinity value, assuming that the monotonous
function is approaching the infinity value and that it is taken at
10THz.
Example
L1 1 2 L='0.5n + 0.5n/(1 + HERTZ/1e8)' CONVOLUTION=1 fbase=10
+ fmax=30meg
AC Choke Inductors
Lxxx node1 node2
<L=> INFINITY
<IC = val>
When the inductance of an inductor is infinity, this element is called an “AC
choke.” In HSPICE, you specify an INFINITY value for inductors.
HSPICE does not support any other inductor parameters, because HSPICE
assumes that the infinite inductance value is independent of temperature and
scaling factors. The AC choke acts as a short circuit for all DC analyses, and
HSPICE calculates the DC current through the inductor. In all other (non-DC)
analyses, a DC current source of this value represents the choke—HSPICE
does not allow di/dt variations.
To properly simulate power line inductors using HSPICE RF, either set them to
ANALOG mode, or invoke the SIM_RAIL option:
.OPTION SIM_ANALOG = “L1”
or
.OPTION SIM_RAIL = ON
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Active Elements
This section describes the passive elements: diodes and transistors.
Diode Element
Geometric (LEVEL=1) or Non-Geometric (LEVEL=3) form:
Dxxx nplus nminus mname <<AREA = >area> <<PJ = >val>
+ <WP = val> <LP = val> <WM = val> <LM = val> <OFF>
+ <IC = vd> <M = val> <DTEMP = val>
Dxxx nplus nminus mname <W = width> <L = length> <WP = val>
+ <LP = val> <WM = val> <LM = val> <OFF> <IC = vd> <M = val>
+ <DTEMP = val>
Fowler-Nordheim (LEVEL = 2) form:
Dxxx nplus nminus mname <W = val <L = val>> <WP = val>
+ <OFF> <IC = vd> <M = val>
Parameter
Description
Dxxx
Diode element name. Must begin with D, followed by up to 1023
alphanumeric characters.
nplus
Positive terminal (anode) node name. The series resistor for the
equivalent circuit is attached to this terminal.
nminus
Negative terminal (cathode) node name.
mname
Diode model name reference.
AREA
Area of the diode (unitless for LEVEL = 1 diode, and square meters for
LEVEL = 3 diode). This affects saturation currents, capacitances, and
resistances (diode model parameters are IK, IKR, JS, CJO, and RS).
The SCALE option does not affect the area factor for the LEVEL = 1
diode. Default = 1.0. Overrides AREA from the diode model. If you do
not specify the AREA, HSPICE or HSPICE RF calculates it from the
width and length.
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Parameter
Description
PJ
Periphery of junction (unitless for LEVEL = 1 diode, and meters for
LEVEL=3 diode). Overrides PJ from the diode model. If you do not
specify PJ, HSPICE or HSPICE RF calculates it from the width and
length specifications.
WP
Width of polysilicon capacitor, in meters (for LEVEL = 3 diode only).
Overrides WP in the diode model. Default = 0.0.
LP
Length of polysilicon capacitor, in meters (for LEVEL = 3 diode only).
Overrides LP in the diode model. Default = 0.0.
WM
Width of metal capacitor, in meters (for LEVEL = 3 diode only).
Overrides WM in the diode model. Default = 0.0.
LM
Length of metal capacitor, in meters (for LEVEL = 3 diode only).
Overrides LM in the diode model. Default = 0.0.
OFF
Sets the initial condition for this element to OFF, in DC analysis.
Default=ON.
IC = vd
Initial voltage, across the diode element. Use this value when you
specify the UIC option in the .TRAN statement. The .IC statement
overrides this value.
M
Multiplier, to simulate multiple diodes in parallel. The M setting affects
all currents, capacitances, and resistances. Default = 1.
DTEMP
The difference between the element temperature and the circuit
temperature, in degrees Celsius. Default = 0.0.
W
Width of the diode, in meters (LEVEL=3 diode model only)
L
Length of the diode, in meters (LEVEL = 3 diode model only)
You must specify two nodes and a model name. If you specify other
parameters, the nodes and model name must be first and the other parameters
can appear in any order.
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Example 1
The D1 diode, with anode and cathode, connects to nodes 1 and 2. Diode1
specifies the diode model.
D1 1 2 diode1
Example 2
The Dprot diode, with anode and cathode, connects to both the output node
and ground, references the firstd diode model, and specifies an area of 10
(unitless for LEVEL = 1 model). The initial condition has the diode OFF.
Dprot output gnd firstd 10 OFF
Example 3
The Ddrive diode, with anode and cathode, connects to the driver and output
nodes. The width and length are 500 microns. This diode references the
model_d diode model.
Ddrive driver output model_d W = 5e-4 L = 5e-4 IC = 0.2
Bipolar Junction Transistor (BJT) Element
Qxxx nc nb ne <ns> mname <area> <OFF>
+ <IC = vbeval,vceval> <M = val> <DTEMP = val>
Qxxx nc nb ne <ns> mname <AREA = area> <AREAB = val>
+ <AREAC = val> <OFF> <VBE = vbeval> <VCE = vceval>
+ <M = val> <DTEMP = val>
Parameter
Description
Qxxx
BJT element name. Must begin with Q, then up to 1023 alphanumeric
characters.
nc
Collector terminal node name.
nb
Base terminal node name.
ne
Emitter terminal node name.
ns
Substrate terminal node name, which is optional. You can also use the
BULK parameter to set this name in the BJT model.
mname
BJT model name reference.
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Parameter
Description
area,
Emitter area multiplying factor, which affects currents, resistances, and
AREA = area capacitances. Default = 1.0.
OFF
Sets initial condition for this element to OFF, in DC analysis.
Default=ON.
IC = vbeval, Initial internal base-emitter voltage (vbeval) and collector-emitter
vceval, VBE, voltage (vceval). HSPICE or HSPICE RF uses this value when
VCE
the .TRAN statement includes UIC. The .IC statement overrides it.
M
Multiplier, to simulate multiple BJTs in parallel. The M setting affects all
currents, capacitances, and resistances. Default = 1.
DTEMP
The difference between the element temperature and the circuit
temperature, in degrees Celsius. Default = 0.0.
AREAB
Base area multiplying factor, which affects currents, resistances, and
capacitances. Default = AREA.
AREAC
Collector area multiplying factor, which affects currents, resistances,
and capacitances. Default = AREA.
The only required fields are the collector, base, and emitter nodes, and the
model name. The nodes and model name must precede other fields in the
netlist.
Example 1
In the Q1 BJT element below:
Q1 1 2 3 model_1
98
■
The collector connects to node 1.
■
The base connects to node 2.
■
The emitter connects to node 3.
■
model_1 references the BJT model.
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Active Elements
Example 2
In the following Qopamp1 BJT element:
Qopamp1 c1 b3 e2 s 1stagepnp AREA = 1.5 AREAB = 2.5
AREAC = 3.0
■
The collector connects to the c1 node.
■
The base connects to the b3 node.
■
The emitter connects to the e2 node.
■
The substrate connects to the s node.
■
1stagepnp references the BJT model.
■
The AREA area factor is 1.5.
■
The AREAB area factor is 2.5.
■
The AREAC area factor is 3.0.
Example 3
In the Qdrive BJT element below:
Qdrive driver in output model_npn 0.1
■
The collector connects to the driver node.
■
The base connects to the in node.
■
The emitter connects to the output node.
■
model_npn references the BJT model.
■
The area factor is 0.1.
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Active Elements
JFETs and MESFETs
Jxxx nd ng ns <nb> mname <<<AREA> = area | <W = val>
+ <L = val>> <OFF> <IC = vdsval,vgsval> <M = val>
+ <DTEMP = val>
Jxxx nd ng ns <nb> mname <<<AREA> = area> | <W = val>
+ <L = val>> <OFF> <VDS = vdsval> <VGS = vgsval>
+ <M = val> <DTEMP = val>
100
Parameter
Description
Jxxx
JFET or MESFET element name. Must begin with J, followed by up
to 1023 alphanumeric characters.
nd
Drain terminal node name
ng
Gate terminal node name
ns
Source terminal node name
nb
Bulk terminal node name, which is optional.
mname
JFET or MESFET model name reference
area,
AREA = area
Area multiplying factor that affects the BETA, RD, RS, IS, CGS, and
CGD model parameters. Default = 1.0, in units of square meters.
W
FET gate width in meters
L
FET gate length in meters
OFF
Sets initial condition to OFF for this element, in DC analysis.
Default = ON.
IC = vdsval,
vgsval, VDS,
VGS
Initial internal drain-source voltage (vdsval) and gate-source voltage
(vgsval). Use this argument when the .TRAN statement contains
UIC. The .IC statement overrides it.
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Parameter
Description
M
Multiplier to simulate multiple JFETs or MESFETs in parallel. The M
setting affects all currents, capacitances, and resistances.
Default = 1.
DTEMP
The difference between the element temperature and the circuit
temperature, in degrees Celsius. Default = 0.0.
Only drain, gate, and source nodes, and model name fields are required. Node
and model names must precede other fields.
Example 1
In the J1 JFET element below:
J1 1 2 3 model_1
■
The drain connects to node 1.
■
The source connects to node 2.
■
The gate connects to node 3.
■
model_1 references the JFET model.
Example 2
In the following Jopamp1 JFET element:
Jopamp1 d1 g3 s2 b 1stage AREA = 100u
■
The drain connects to the d1 node.
■
The source connects to the g3 node.
■
The gate connects to the s2 node.
■
1stage references the JFET model.
■
The area is 100 microns.
Example 3
In the Jdrive JFET element below:
Jdrive driver in output model_jfet W = 10u L = 10u
■
The drain connects to the driver node.
■
The source connects to the in node.
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■
The gate connects to the output node.
■
model_jfet references the JFET model.
■
The width is 10 microns.
■
The length is 10 microns.
MOSFETs
Mxxx nd ng ns <nb> mname <<L = >length> <<W = >width>
+ <AD = val> AS = val> <PD = val> <PS = val>
+ <NRD = val> <NRS = val> <RDC = val> <RSC = val> <OFF>
+ <IC = vds,vgs,vbs> <M = val> <DTEMP = val>
+ <GEO = val> <DELVTO = val>
.OPTION WL
Mxxx nd ng ns <nb> mname <width> <length> <other_options...>
102
Parameter
Description
Mxxx
MOSFET element name. Must begin with M, followed by up to 1023
alphanumeric characters.
nd
Drain terminal node name.
ng
Gate terminal node name.
ns
Source terminal node name.
nb
Bulk terminal node name, which is optional. To set this argument in the
MOSFET model, use the BULK parameter.
mname
MOSFET model name reference
L
MOSFET channel length, in meters. This parameter overrides
.OPTION DEFL. Default = DEFL, with a maximum value of 0.1m.
W
MOSFET channel width, in meters. This parameter overrides DEFW in
an .OPTION statement. Default = DEFW.
AD
Drain diffusion area. Overrides DEFAD in the .OPTION statement.
Default = DEFAD, if you set the ACM = 0 model parameter.
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Parameter
Description
AS
Source diffusion area. Overrides DEFAS in the .OPTION statement.
Default = DEFAS, if you set the ACM = 0 model parameter.
PD
Perimeter of drain junction, including channel edge. Overrides
.OPTION DEFPD. Default = DEFAD, if you set the ACM = 0 or 1 model
parameter. Default = 0.0, if you set ACM = 2 or 3.
PS
Perimeter of source junction, including channel edge. Overrides
.OPTION DEFPS. Default = DEFAS, if you set the ACM = 0 or 1 model
parameter. Default = 0.0, if you set ACM = 2 or 3.
NRD
Number of squares of drain diffusion for resistance calculations.
Overrides .OPTION DEFNRD. Default = DEFNRD, if you set ACM =
0 or 1 model parameter. Default = 0.0, if you set ACM = 2 or 3.
NRS
Number of squares of source diffusion for resistance calculations.
Overrides DEFNRS in the .OPTION statement. Default = DEFNRS when
you set the MOSFET model parameter ACM = 0 or 1. Default = 0.0,
when you set ACM = 2 or 3.
RDC
Additional drain resistance due to contact resistance, in units of ohms.
This value overrides the RDC setting in the MOSFET model
specification. Default = 0.0.
RSC
Additional source resistance due to contact resistance, in units of ohms.
This value overrides the RSC setting in the MOSFET model
specification. Default = 0.0.
OFF
Sets initial condition for this element to OFF, in DC analysis.
Default = ON. This command does not work for depletion devices.
IC = vds, vgs, Initial voltage across external drain and source (vds), gate and source
vbs
(vgs), and bulk and source terminals (vbs). Use these arguments
with .TRAN UIC. .IC statements override these values.
M
Multiplier, to simulate multiple MOSFETs in parallel. Affects all channel
widths, diode leakages, capacitances, and resistances. Default = 1.
DTEMP
The difference between the element temperature and the circuit
temperature, in degrees Celsius. Default = 0.0.
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Parameter
Description
GEO
Source/drain sharing selector for a MOSFET model parameter value of
ACM = 3. Default = 0.0.
DELVTO
Zero-bias threshold voltage shift. Default = 0.0.
The only required fields are the drain, gate and source nodes, and the model
name. The nodes and model name must precede other fields in the netlist. If
you did not specify a label, use the second syntax with the .OPTION WL
statement, to exchange the width and length options.
Example
In the following M1 MOSFET element:
M1 1 2 3 model_1
■
The drain connects to node 1.
■
The gate connects to node 2.
■
The source connects to node 3.
■
model_1 references the MOSFET model.
In the following Mopamp1 MOSFET element:
Mopamp1 d1 g3 s2 b 1stage L = 2u W = 10u
■
The drain connects to the d1 node.
■
The gate connects to the g3 node.
■
The source connects to the s2 node.
■
1stage references the MOSFET model.
■
The length of the gate is 2 microns.
■
The width of the gate is 10 microns.
In the following Mdrive MOSFET element:
Mdrive driver in output bsim3v3 W = 3u L = 0.25u
+ DTEMP = 4.0
104
■
The drain connects to the driver node.
■
The gate connects to the in node.
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■
The source connects to the output node.
■
bsim3v3 references the MOSFET model.
■
The length of the gate is 3 microns.
■
The width of the gate is 0.25 microns.
■
The device temperature is 4 degrees Celsius higher than the circuit
temperature.
Transmission Lines
A transmission line is a passive element that connects any two conductors, at
any distance apart. One conductor sends the input signal through the
transmission line, and the other conductor receives the output signal from the
transmission line. The signal that is transmitted from one end of the pair to the
other end, is voltage between the conductors.
Examples of transmission lines include:
■
Power transmission lines
■
Telephone lines
■
Waveguides
■
Traces on printed circuit boards and multi-chip modules (MCMs)
■
Bonding wires in semiconductor IC packages
■
On-chip interconnections
W Element
Wxxx i1 i2 ... iN iR o1 o2 ... oN oR N=val L=val
+ TABLEMODEL=name
Parameter
Description
N
Number of signal conductors (excluding the reference conductor).
i1...iN
Node names for the near-end signal-conductor terminal.
iR
Node name for the near-end reference-conductor terminal.
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Parameter
Description
o1...oN
Node names for the far-end signal-conductor terminal.
oR
Node name for the far-end reference-conductor terminal.
L
Length of the transmission line.
TABLEMODEL
Name of the frequency-dependent tabular model.
The W element supports five different formats to specify the transmission line
properties:
■
■
Model 1: RLGC-Model specification.
•
Internally specified in a .model statement.
•
Externally specified in a different file.
Model 2: U-Model specification.
•
RLGC input for up to five coupled conductors.
•
Geometric input (planer, coax, twin-lead).
•
Measured-parameter input.
•
Skin effect.
■
Model 3: Built-in field solver model.
■
Model 4: Frequency-dependent tabular model.
■
Model 5: S Parameter Model
W Element Statement
The general syntax for a lossy (W Element) transmission line element is:
RLGC file form:
Wxxx in1 <in2 <...inx>> refin out1 <out2 <...outx>>
+ refout <RLGCfile = fname> <COORD=0|DESCART|1|POLAR>
+ N = val L = val
U Model form:
Wxxx in1 <in2 <...inx>> refin out1 <out2 <...outx>>
+ refout <Umodel = mname> N = val L = val
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Field solver form:
Wxxx in1 <in2 <...inx>> refin out1 <out2 <...outx>>
+ refout <FSmodel = mname> N = val L = val
The number of ports on a single transmission line are not limited. You must
provide one input and output port, the ground references, a model or file
reference, a number of conductors, and a length. HSPICE RF does not support
the Field Solver form of the W element.
S Model form:
Wxxx in1 <in2 <...inx>> refin out1 <out2 <...outx>>
+ refout <Smodel = mname> <NODEMAP=XiYj...> N = val L = val
Parameter
Description
Wxxx
Lossy (W Element) transmission line element name. Must start
with W, followed by up to 1023 alphanumeric characters.
inx
Signal input node for xth transmission line (in1 is required).
refin
Ground reference for input signal
outx
Signal output node for the xth transmission line (each input port
must have a corresponding output port).
refout
Ground reference for output signal.
N
Number of conductors (excluding the reference conductor).
L
Physical length of the transmission line, in units of meters.
RLGCfile = fname
File name reference for the file containing the RLGC
information for the transmission lines (for syntax, see Chapter
3, “Using Transmission Lines,” in the HSPICE Signal Integrity
Guide).
COORD
Invokes the polar field solver only if COORD=1 or
COORD=POLAR.
ORIGIN
Should be (radius, degree) for the polar field solver.
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Parameter
Description
Umodel = mname
U-model lossy transmission-line model reference name. A
lossy transmission line model, used to represent the
characteristics of the W-element transmission line.
FSmodel = mname
Internal field solver model name. References the PETL internal
field solver, as the source of the transmission-line
characteristics (for syntax, see the HSPICE Signal Integrity
Guide).
NODEMAP
String that assigns each index of the S
parameter matrix to
one of the W Element terminals. This string must be an array of
pairs that consists of a letter and a number, (for example, Xn),
where
• X= I, i, N, or n to indicate near end (input side) terminal of
the W element
• X= O, i, F, or f to indicate far end (output side) terminal of the
W element.
The default value for NODEMAP is "I1I2I3...InO1O2O3...On"
Smodel
S Model name reference, which contains the S Parameters of
the transmission lines (for the S Model syntax, the HSPICE
Signal Integrity Guide).
Example 1
The W1 lossy transmission line connects the in node to the out node:
W1 in gnd out gnd RLGCfile = cable.rlgc N = 1 L = 5
Where,
■
Both signal references are grounded
■
The RLGC file is named cable.rlgc
■
The transmission line is 5 meters long.
Example 2
The Wcable element is a two-conductor lossy transmission line:
Wcable in1 in2 gnd out1 out2 gnd Umodel = umod_1 N = 2
+ L = 10
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Where,
■
in1 and in2 input nodes connect to the out1 and out2 output node
■
Both signal references are grounded.
■
umod_1 references the U-model.
■
The transmission line is 10 meters long.
Example 3
The Wnet1 element is a five-conductor lossy transmission line:
Wnet1 i1 i2 i3 i4 i5 gnd o1 gnd o3 gnd o5 gnd
+ FSmodel = board1 N = 5 L = 1m
Where,
■
The i1, i2, i3, i4 and i5 input nodes connect to the o1, o3, and o5 output
nodes.
■
The i5 input and three outputs (o1, o3, and o5) are all grounded.
■
board1 references the Field Solver model.
■
The transmission line is 1 millimeter long.
Example 4: S Model Example
Wnet1 i1 i2 gnd o1 o2 gnd
+ Smodel = smod_1 nodemap=i1i2o1o2
+ N = 2 L = 10m
Where,
■
in1 and in2 input nodes connect to the out1 and out2 output node.
■
Both signal references are grounded.
■
smod_1 references the S Model.
■
The transmission line is 10 meters long.
You can specify parameters in the W Element card in any order. You can
specify the number of signal conductors, N, after the node list. You can also mix
nodes and parameters in the W Element card.
You can specify only one of the RLGCfile, FSmodel, Umodel, or Smodel
models, in a single W Element card.
Figure 13 shows node numbering for the element syntax.
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Figure 13
Terminal Node Numbering for the W Element
N+1 conductor line
[i1]1
1.1 [i ]
12
1.2
[i1]N
1.N
1’
[v1]1
R(f), L(f), G(f), C(f)
[v2]1
[v1]2
Signal Conductors
[v2]2
.
.
.
.
.
.
[v1]N
+
_
[i2]1
[i2]2
.
.
.
Reference conductor
2.1
2.2
[i2]N
2.N
[v2]N
+
_
2’
x
0
Lossless (T Element)
General form:
Txxx in refin out refout Z0 = val TD = val <L = val>
+ <IC = v1,i1,v2,i2>
Txxx in refin out refout Z0 = val F = val <NL = val>
+ <IC = v1,i1,v2,i2>
U Model form:
Txxx in refin out refout mname L = val
110
Parameter
Description
Txxx
Lossless transmission line element name. Must begin with T,
followed by up to 1023 alphanumeric characters.
in
Signal input node.
refin
Ground reference for the input signal.
out
Signal output node.
refout
Ground reference for the output signal.
Z0
Characteristic impedance of the transmission line.
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TD
Signal delay from a transmission line, in seconds per meter.
L
Physical length of the transmission line, in units of meters.
Default = 1.
IC = v1,i1,v2,i2
Initial conditions of the transmission line. Specify the voltage on
the input port (v1), current into the input port (i1), voltage on the
output port (v2), and the current into the output port (i2).
F
Frequency at which the transmission line has the electrical length
specified in NL.
NL
Normalized electrical length of the transmission line (at the
frequency specified in the F parameter), in units of wavelengths
per line length. Default = 0.25, which is a quarter-wavelength.
mname
U-model reference name. A lossy transmission line model,
representing the characteristics of the lossless transmission line.
Only one input and output port is allowed.
Example 1
The T1 transmission line connects the in node to the out node:
T1 in gnd out gnd Z0 = 50 TD = 5n L = 5
■
Both signal references are grounded.
■
Impedance is 50 ohms.
■
The transmission delay is 5 nanoseconds per meter.
■
The transmission line is 5 meters long.
Example 2
The Tcable transmission line connects the in1 node to the out1 node:
Tcable in1 gnd out1 gnd Z0 = 100 F = 100k NL = 1
■
Both signal references are grounded.
■
Impedance is 100 ohms.
■
The normalized electrical length is 1 wavelength at 100 kHz.
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Example 3
The Tnet1 transmission line connects the driver node to the output node:
Tnet1 driver gnd output gnd Umodel1 L = 1m
■
Both signal references are grounded.
■
Umodel1 references the U-model.
■
The transmission line is 1 millimeter long.
Ideal Transmission Line
For the ideal transmission line, voltage and current will propagate without loss
along the length of the line (±x direction) with spatial and time-dependence
given according to the following equation:
v ( x, t ) = Re [ Ae
j ( ωt – βx )
+ Be
j ( ϖt + βx )
]
A j ( ωt – βx ) B j ( ωt + βx )
v ( x, t ) = Re ----- e
– ----- e
Z0
Z0
The A represents the incident voltage, B represents the reflected voltage, Z0 is
the characteristic impeadance, and β is the propagation constant. The latter are
related to the transmission line inductance (L) and capacitance (C) by the
following equation:
Z0 =
L--C
β = ω LC
The L and C terms are in per-unit-length units (Henries/meter, Farads/meter).
The following equation gives the phase velocity:
ω
1
υ ρ = ---- = ----------β
LC
At the end of the transmission line ( x = l ), the propagation term β l becomes
the following equation:
l
β l = ω LC ⋅ l = ω ----vp
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This is equivalent to an ideal delay with the following value:
τ=
l
= LC ⋅ l
vp
τ : absolute time delay (sec)
l : physical length (L ) (meters )
v p : phase velocity (meters / sec)
Using standard distance=velocity*time relationships, the HSPICE T element
parameter values are related to these terms according to:
vp = f ⋅ λ =
1
td
f : frequency
λ : wavelength
t d : relative time delay (TD) (sec/ meter )
τ=
l
l
lλ
= td ⋅ l =
=
= LC ⋅ l
vp
f ⋅λ
f
l : physical length (L ) (meters )
l λ : normalized length (NL )
f : frequency at NL (F) (Hz)
τ = TD ⋅ L =
NL
= LC ⋅ L
F
HSPICE therefore allows you to specify a transmission line in three different
ways:
■
Z0, TD, L
■
Z0, NL, F
■
L, with
L
and
C
LC values taken from a U model.
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Lossy (U Element)
Uxxx in1 <in2 <...in5>> refin out1 <out2 <...out5>>
+ refout mname L = val <LUMPS = val>
Parameter
Description
Uxxx
Lossy (U Element) transmission line element name. Must begin with U,
followed by up to 1023 alphanumeric characters.
inx
Signal input node for the xth transmission line (in1 is required).
refin
Ground reference for the input signal.
outx
Signal output node for the xth transmission line (each input port must
have a corresponding output port).
refout
Ground reference for the output signal.
mname
Model reference name for the U-model lossy transmission-line.
L
Physical length of the transmission line, in units of meters.
LUMPS
Number of lumped-parameter sections used to simulate the element.
In this syntax, the number of ports on a single transmission line is limited to five
in and five out. One input and output port, the ground references, a model
reference, and a length are all required.
Example 1
The U1 transmission line connects the in node to the out node:
U1 in gnd out gnd umodel_RG58 L = 5
114
■
Both signal references are grounded.
■
umodel_RG58 references the U-model.
■
The transmission line is 5 meters long.
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Example 2
The Ucable transmission line connects the in1 and in2 input nodes to the out1
and out2 output nodes:
Ucable in1 in2 gnd out1 out2 gnd twistpr L = 10
■
Both signal references are grounded.
■
twistpr references the U-model.
■
The transmission line is 10 meters long.
Example 3
The Unet1 element is a five-conductor lossy transmission line:
Unet1 i1 i2 i3 i4 i5 gnd o1 gnd o3 gnd o5 gnd Umodel1 L = 1m
■
The i1, i2, i3, i4, and i5 input nodes connect to the o1, o3, and o5 output
nodes.
■
The i5 input, and the three outputs (o1, o3, and o5) are all grounded.
■
Umodel1 references the U-model.
■
The transmission line is 1 millimeter long.
Frequency-Dependent Multi-Terminal S Element
The S element uses the following parameters to define a frequency-dependent,
multi-terminal network:
■
S (scattering)
■
Y (admittance)
■
Z (impedance)
You can use an S element in the following types of analyses:
■
DC
■
AC
■
Transient
■
Small Signal
For a description of the S parameter and SP model analysis, see Chapter 2 of
the HSPICE Signal Integrity Guide.
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S Element Syntax (HSPICE):
Sxxx nd1 nd2 ... ndN ndRef
+ <MNAME=Smodel_name> <FQMODEL=sp_model_name>
+ <TYPE=[s|y]> <Zo=[value|vector_value]>
+ <FBASE = base_frequency> <FMAX=maximum_frequency>
+ <PRECFAC=val> <DELAYHANDLE=[1|0|ON|OFF]>
+ <DELAYFREQ=val>
+ <INTERPOLATION=STEP|LINEAR|SPLINE>
+ <INTDATTYP =[RI|MA|DBA]> <HIGHPASS=value>
+ <LOWPASS=value> <MIXEDMODE=[0|1]>
+ <DATATYPE=data_string>
+ <DTEMP=val> <NOISE=[1|0]>
S Element Syntax (HSPICE RF):
Sxxx nd1 nd2 ... ndN [ndR] s_model_name
S model Syntax (HSPICE):
.MODEL S_model_name S
+ N=dimension
+ [FQMODEL=sp_model_name | TSTONEFILE=filename |
+ CITIFILE=filename] <TYPE=[s | y]>
+ <Zo=[value | vector_value]>
+ <FBASE=base_frequency> <FMAX=maximum_frequency>
+ <PRECFAC=val> <DELAYHANDLE=ON | OFF> <DELAYFREQ=val>
S Model Syntax (HSPICE RF):
.model S_model_name S
+ [FQMODEL=sp_model_name | TSTONEFILE=filename |
+ CITIFILE=filename] <TYPE=[S | Y | Z]>
+ <FBASE = base_frequency> <FMAX = max_frequency>
+ <Zo=[50 | vector_value ] | Zof=ref_model>
+ <HIGHPASS=[0 | 1 | 2]> <LOWPASS=[0 | 1 | 2]>
+ <DELAYHANDLE=[0 | 1]> <DELAYFREQ=val>
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Parameter
Description
nd1 nd2 ... ndN
Nodes of an S element (see Figure 14). Three kinds of
definitions are present:
• With no reference node ndRef, the default reference node
in this situation is GND. Each node ndi (i=1~N) and GND
construct one of the N ports of the S element.
• With one reference node, ndRef is defined. Each node ndi
(i=1~N) and the ndRef construct one of the N ports of the S
element.
With an N reference node, each port has its own reference
node. You can write the node definition in a clearer way as:
nd1+ nd1- nd2+ nd2- ... ndN+ ndNEach pair of the nodes (ndi+ and ndi-, i=1~N) constructs one
of the N ports of the S element.
nd_ref or NdR
Reference node.
MNAME
Name of the S model.
FQMODEL
Frequency behavior of the S,Y, or Z parameters. .MODEL
statement of sp type, which defines the frequency-dependent
matrices array.
TSTONEFILE
Name of a Touchstone file. Data contains frequency-dependent
array of matrixes. Touchstone files must follow the .s#p file
extension rule, where # represents the dimension of the
network.
For details, see Touchstone® File Format Specification by the
EIA/IBIS Open Forum (http://www.eda.org).
CITIFILE
Name of the CITIfile, which is a data file that contains
frequency-dependent data.
For details, see Using Instruments with ADS by Agilent
Technologies (http://www.agilent.com).
TYPE
Parameter type:
• S (scattering), the default
• Y (admittance)
• Z (impedance)
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Parameter
Description
Zo
Characteristic impedance value of the reference line
(frequency-independent). For multi-terminal lines (N>1),
HSPICE assumes that the characteristic impedance matrix of
the reference lines are diagonal, and their diagonal values are
set to Zo. You can also set a vector value for non-uniform
diagonal values. Use Zof to specify more general types of a
reference-line system. The default is 50.
FBASE
Base frequency used for transient analysis. HSPICE uses this
value as the base frequency point for Inverse Fast Fourier
Transformation (IFFT).
• If FBASE is not set, HSPICE uses a reciprocal of the
transient period as the base frequency.
• If FBASE is set smaller than the reciprocal value of transient
period, transient analysis performs circular convolution by
using the reciprocal value of FBASE as a base period.
FMAX
Maximum frequency for transient analysis. Used as the
maximum frequency point for Inverse Fast Fourier Transform
(IFFT).
PRECFAC
Preconditioning factor to avoid a singularity (infinite admittance
matrix). See Pre-Conditioning S Parameters on page 122.
Default=0.75.
DELAYHANDLE
Delay frequency for transmission line type parameters.
Default=OFF.
• 1 of ON activates the delay handler. See Group Delay
Handler in Time Domain Analysis on page 121
• 0 of OFF (default) deactivates the delay handler.
You must set the delay handler, if the delay of the model is
longer than the base period specified in the FBASE parameter.
If you set DELAYHANDLE=OFF but DELAYFQ is not zero,
HSPICE simulates the S element in delay mode.
DELAYFREQ
118
Delay frequency for transmission-line type parameters. The
default is FMAX. If the DELAYHANDLE is set to OFF, but
DELAYFREQ is nonzero, HSPICE still simulates the S element
in delay mode.
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Parameter
Description
INTERPOLATION
The interpolation method:
• STEP: piecewise step
• SPLINE: b-spline curve fit
• LINEAR: piecewise linear (default)
INTDATTYP
Data type for the linear interpolation of the complex data.
• RI: real-imaginary based interpolation
• DBA: dB-angle based interpolation
• MA: magnitude-angle based interpolation (default)
HIGHPASS
Specifies high-frequency extrapolation:
0: Use zero in Y dimension (open circuit).
1: Use highest frequency.
2: Use linear extrapolation, with the highest two points.
3: Apply window function (default).
This option overrides EXTRAPOLATION in ,model SP.
LOWPASS
Specifies low-frequency extrapolation:
0: Use zero in Y dimension (open circuit).
1: Use lowest frequency (default).
2: Use linear extrapolation, with the lowest two points.
This option overrides EXTRAPOLATION in .model SP.
MIXEDMODE
Set to 1 if the parameters are represented in the mixed mode.
DATATYPE
A string used to determine the order of the indices of the mixedsignal incident or reflected vector. The string must be an array
of a letter and a number (Xn) where:
• X = D to indicate a differential term
= C to indicate a common term
= S to indicate a single (grounded) term
• n = the port number
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Parameter
Description
DTEMP
Temperature difference between the element and the circuit.a
Expressed in °C. The default is 0.0.
NOISE
If 1, element generates thermal noise. If 0, element is
considered noiseless. Default=0.
a. Circuit temperature is specified by using the .TEMP statement or by sweeping the global
TEMP variable in .DC, .AC, or .TRAN statements. When neither .TEMP or TEMP is used,
circuit temperature is set by using .OPTION TNOM. The default for TNOM is 25 °C, unless you
use .OPTION SPICE, which has a default of 27 °C. You can use the DTEMP parameter to
specify the temperature of the element.
You can set all optional parameters, except MNAME, in both the S element and
the S model statement. Parameters in element statements have higher
priorities. You must specify either the FQMODEL, TSTONEFILE, or CITIFILE
parameter in either the S model or the S element statement.
When used with the generic frequency-domain model (.MODEL SP), an S
(scattering) element is a convenient way to describe a multi-terminal network.
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Figure 14
Terminal Node Notation
.
.
.
.
.
.
.
.
.
N+1 terminal system
[vinc]1
[vinc]N
[i]N
[i]1
[vref]1
[vref]N
ndN
(+) [v]N
nd1
(+) [v]1
(-) ndR
(reference node)
Frequency Table Model
The Frequency Table Model is a generic model that you can use to describe
frequency-varying behavior. Currently, the S element and .sp use this model.
For a description of this model, see “Frequency Table Model” in Chapter 6,
Linear N-Ports/Transmission Lines, in the HSPICE Elements and Device
Models Manual.
Group Delay Handler in Time Domain Analysis
The S element accepts a constant group delay matrix in time-domain analysis.
You can also express a weak dependence of the delay matrix on the frequency,
as a combination of the constant delay matrix and the phase shift value at each
frequency point.
To activate or deactivate this delay handler, specify the <DELAYHANDLE=0|1>
keyword in the S model statement.
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The delay matrix is a constant matrix, which HSPICE RF extracts using finite
difference calculation at selected target frequency points. HSPICE RF obtains
the ϒ ω ( i, j ) delay matrix component as:
d θ Sij
1 d θ Sij
ϒ ω ( i, j ) = -------------- = ------ ⋅ -------------2π
df
dω
■
■
f is the target frequency, which you can set using <DELAYFREQ=val>. The
default target frequency is the maximum frequency point.
θ Sij is the phase of Sij.
After time domain analysis obtains the group delay matrix, the following
equation eliminates the delay amount from the frequency domain systemtransfer function:
y ′ mn ( ω ) = y mn ( ω ) × e
j ωΤ mn
The convolution process then uses the following equation to calculate the
delay:
T
i k ( t ) = ( y′ k1 ( t ), y′ k2 ( t ), …, y′ kN ( t ) ) ×  v 1 ( t – T ), v 2 ( t – T ), …, v Nt – T 

K1
K2
KN
(1)
Pre-Conditioning S Parameters
Certain S parameters, such as series inductor (2-port), show a singularity when
converting S to Y parameters. To avoid this singularity, the S element adds
kRref series resistance, to pre-condition S matrices:
S ′ = [ kI + ( 2 – k ) S ] [ ( 2 + k ) I – kS ]
■
Rref is the reference impedance vector.
■
k is the pre-conditioning factor.
–1
To compensate for this modification, the S element adds a negative resistor (–
kRref) to the modified nodal analysis (NMA) matrix, in actual circuit
compensation. To specify this pre-conditioning factor, use the <PREFAC=val>
keyword in the S model statement. The default pre-conditioning factor is 0.75.
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IBIS Buffers
Figure 15
Pre-Conditioning S Parameters
preconditioning
S
S
kRref
NMA stamp
kRref
Y’
Y’
Y
IBIS Buffers
The general syntax of a B element card for IBIS I/O buffers is:
bxxx node_1 node_2 ... node_N
+ file='filename' model='model_name'
+ keyword_1=value_1 ... [keyword_M=value_M]
Parameter
Description
bname
Buffer name, and starts with the letter B, which can be
followed by up to 1023 alphanumeric characters.
node_1 node_2 ...
node_N
List of I/O buffer external nodes. The number of nodes and
their meaning are specific to different buffer types.
file=’filename’
Name of the IBIS file.
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IBIS Buffers
Parameter
Description
model=’model_name’ Name of the model.
keyword_i = value_i
Assigns a value of value_i to the keyword_i keyword.
Specify optional keywords in brackets ( [ ] ). For more
information about keywords, see “Specifying Command
Keywords” in the HSPICE Signal Integrity User Guide.
Example
B1 nd_pc nd_gc nd_in nd_out_of_in
+ buffer = 1
+ file = 'test.ibs'
+ model = 'IBIS_IN'
■
This example represents an input buffer named B1.
■
The four terminals are named nd_pc, nd_gc, nd_in and nd_out_of_in.
■
The IBIS model named IBIS_IN is located in the IBIS file named test.ibs.
Note: HSPICE or HSPICE RF connects the nd_pc and nd_gc nodes to the
voltage sources. Do not manually connect these nodes to voltage sources.
For more examples, see the “Modeling Input/Output Buffers Using IBIS”
chapter in the HSPICE Signal Integrity User Guide.
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Sources and Stimuli
5
Describes element and model statements for independent sources,
dependent sources, analog-to-digital elements, and digital-to-analog
elements.
This chapter also explains each type of element and model statement and
provides explicit formulas and examples to show how various combinations of
parameters affect the simulation.
Independent Source Elements
Use independent source element statements to specify DC, AC, transient, and
mixed independent voltage and current sources. Some types of analysis use
the associated analysis sources. For example, in a DC analysis, if you specify
both DC and AC sources in one independent source element statement,
HSPICE or HSPICE RF removes the AC source from the circuit for the DC
analysis. If you specify an independent source for an AC, transient, and DC
analysis, HSPICE or HSPICE RF removes transient sources, calculates the
operating point, and removes DC sources for the AC analysis. Initial transient
values always override the DC value.
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Independent Source Elements
Source Element Conventions
You do not need to ground voltage sources. HSPICE or HSPICE RF assumes
that positive current flows from the positive node, through the source, to the
negative node. A positive current source forces current to flow out of the n+
node, through the source, and into the n- node.
You can use parameters as values in independent sources. Do not use any of
the reserved keywords to identify these parameters:
AC
PU
ACI
PULSE
AM
PWL
DC
R
EXP
RD
PAT
SFFM
PE
SIN
PL
Independent Source Element
The general syntax for an independent source is:
Vxxx n+ n- <<DC=> dcval> <tranfun> <AC=acmag> <acphase>>
Ixxx n+ n- <<DC=> dcval> <tranfun> <AC=acmag> <acphase>> <M=val>
126
Parameter
Description
Vxxx
Independent voltage source element name. Must begin with V, followed
by up to 1023 alphanumeric characters.
Ixxx
Independent current source element name. Must begin with I, followed
by up to 1023 alphanumeric characters.
n+
Positive node.
n-
Negative node.
DC=dcval
DC source keyword and value, in volts. The tranfun value at time zero
overrides the DC value. Default=0.0.
tranfun
Transient source function (one or more of: AM, DC, EXP, PAT, PE, PL,
PU, PULSE, PWL, SFFM, SIN). The functions specify the
characteristics of a time-varying source. See the individual functions for
syntax.
AC
AC source keyword for use in AC small-signal analysis.
acmag
Magnitude (RMS) of the AC source, in volts.
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Independent Source Elements
Parameter
Description
acphase
Phase of the AC source, in degrees. Default=0.0.
M
Multiplier, to simulate multiple parallel current sources. HSPICE or
HSPICE RF multiplies source current by M. Default=1.0.
Example 1
VX 1 0 5V
Where,
■
The VX voltage source has a 5-volt DC bias.
■
The positive terminal connects to node 1.
■
The negative terminal is grounded.
Example 2
VB 2 0 DC=VCC
Where,
■
The VCC parameter specifies the DC bias for the VB voltage source.
■
The positive terminal connects to node 2.
■
The negative terminal is grounded.
Example 3
VH 3 6 DC=2 AC=1,90
Where,
■
The VH voltage source has a 2-volt DC bias, and a 1-volt RMS AC bias, with
90 degree phase offset.
■
The positive terminal connects to node 3.
■
The negative terminal connects to node 6.
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Example 4
IG 8 7 PL(1MA 0S 5MA 25MS)
Where,
■
The piecewise-linear relationship defines the time-varying response for the
IG current source, which is 1 milliamp at time=0, and 5 milliamps at 25
milliseconds.
■
The positive terminal connects to node 8.
■
The negative terminal connects to node 7.
Example 5
VCC in out VCC PWL 0 0 10NS VCC 15NS VCC 20NS 0
Where,
■
The VCC parameter specifies the DC bias for the VCC voltage source.
■
The piecewise-linear relationship defines the time-varying response for the
VCC voltage source, which is 0 volts at time=0, VCC from 10 to 15
nanoseconds, and back to 0 volts at 20 nanoseconds.
■
The positive terminal connects to the in node.
■
The negative terminal connects to the out node.
■
HSPICE or HSPICE RF determines the operating point for this source,
without the DC value (the result is 0 volts).
Example 6
VIN 13 2 0.001 AC 1 SIN (0 1 1MEG)
Where,
128
■
The VIN voltage source has a 0.001-volt DC bias, and a 1-volt RMS AC bias.
■
The sinusoidal time-varying response ranges from 0 to 1 volts, with a
frequency of 1 megahertz.
■
The positive terminal connects to node 13.
■
The negative terminal connects to node 2.
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Example 7
ISRC 23 21 AC 0.333 45.0 SFFM (0 1 10K 5 1K)
Where,
■
The ISRC current source has a 1/3-amp RMS AC response, with a 45degree phase offset.
■
The frequency-modulated, time-varying response ranges from 0 to 1 volts,
with a carrier frequency of 10 kHz, a signal frequency of 1 kHz, and a
modulation index of 5.
■
The positive terminal connects to node 23.
■
The negative terminal connects to node 21.
Example 8
VMEAS 12 9
Where,
■
The VMEAS voltage source has a 0-volt DC bias.
■
The positive terminal connects to node 12.
■
The negative terminal connects to node 9.
DC Sources
For a DC source, you can specify the DC current or voltage in different ways:
V1
V1
I1
I1
1
1
1
1
0
0
0
0
DC=5V
5V
DC=5mA
5mA
■
The first two examples specify a DC voltage source of 5 V, connected
between node 1 and ground.
■
The third and fourth examples specify a 5 mA DC current source, between
node 1 and ground.
The direction of current in both sources is from node 1 to ground.
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AC Sources
AC current and voltage sources are impulse functions, used for an AC analysis.
To specify the magnitude and phase of the impulse, use the AC keyword.
V1 1 0 AC=10V,90
VIN 1 0 AC 10V 90
The preceding two examples specify an AC voltage source, with a magnitude of
10 V and a phase of 90 degrees. To specify the frequency sweep range of the
AC analysis, use the .AC analysis statement. The AC or frequency domain
analysis provides the impulse response of the circuit.
Transient Sources
For transient analysis, you can specify the source as a function of time. The
following functions are available:
■
pulse
■
exponential
■
damped sinusoidal
■
single-frequency FM
■
piecewise linear
■
pattern
■
PRBS (Pseudo Random-Bit Generator Source)
Mixed Sources
Mixed sources specify source values for more than one type of analysis. For
example, you can specify a DC source, an AC source, and a transient source,
all of which connect to the same nodes. In this case, when you run specific
analyses, HSPICE or HSPICE RF selects the appropriate DC, AC, or transient
source. The exception is the zero-time value of a transient source, which overrides the DC value; it is selected for operating-point calculation for all analyses.
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Example
VIN 13 2 0.5 AC 1 SIN (0 1 1MEG)
Where,
■
DC source of 0.5 V
■
AC source of 1 V
■
Transient damped sinusoidal source
Each source connects between nodes 13 and 2.
For DC analysis, the program uses zero source value, because the sinusoidal
source is zero at time zero.
Port Element
The port element identifies the ports used in .LIN analysis. Each port element
requires a unique port number. If your design uses N port elements, your netlist
must contain the sequential set of port numbers, 1 through N (for example, in a
design containing 512 ports, you must number each port sequentially, 1 to
512).
Each port has an associated system impedance, zo. If you do not explicitly
specify the system impedance, the default is 50 ohms.
The port element behaves as either a noiseless impedance or a voltage source
in series with the port impedance for all other analyses (DC, AC, or TRAN).
■
You can use this element as a pure terminating resistance or as a voltage or
power source.
■
You can use the RDC, RAC, RHB, RHBAC, and rtran values to override the port
impedance value for a particular analysis.
Syntax
Pxxx p n port=portnumber
+ $ **** Voltage or Power Information ********
+ <DC mag> <AC <mag <phase>>> <HBAC <mag <phase>>>
+ <HB <mag <phase <harm <tone <modharm <modtone>>>>>>>
+ <transient_waveform> <TRANFORHB=[0|1]>
+ <DCOPEN=[0|1]>
+ $ **** Source Impedance Information ********
+ <Z0=val> <RDC=val> <RAC=val>
+ <RHBAC=val> <RHB=val> <RTRAN=val>
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+ $ **** Power Switch ********
+ <power=[0|1|2|W|dbm]>
Parameter
Description
port=portnumber
The port number. Numbered sequentially beginning with
1 with no shared port numbers.
<DC mag>
DC voltage or power source value.
<AC <mag <phase>>>
AC voltage or power source value.
<HBAC <mag <phase>>>
(HSPICE RF) HBAC voltage or power source value.
<HB <mag <phase <harm
<tone <modharm
<modtone>>>>>>>
(HSPICE RF) HB voltage, current, or power source
value. Multiple HB specifications with different harm,
tone, modharm, and modtone values are allowed.
• phase is in degrees
• harm and tone are indices corresponding to the
tones specified in the .HB statement. Indexing starts
at 1 (corresponding to the first harmonic of a tone).
• modtone and modharm specify sources for multitone simulation. A source specifies a tone and a
harmonic, and up to 1 offset tone and harmonic
(modtone for tones and modharm for harmonics).
The signal is then described as:
V(or I) = mag*cos(2*pi*
(harm*tone+modharm*modtone)*t + phase)
<transient_waveform>
132
(Transient analysis) Voltage or power source waveform.
Any one of waveforms: AM, EXP, PULSE, PWL, SFFM, or
SIN. Multiple transient descriptions are not allowed.
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Parameter
Description
<TRANFORHB=[0|1]>
• 0 (default): The transient description is ignored if an
HB value is given or a DC value is given. If no DC or
HB value is given and TRANFORHB=0, then HB
analysis treats the source as a DC source, and the
DC source value is the time=0 value.
• 1: HB analysis uses the transient description if its
value is VMRF, SIN, PULSE, PWL, or LFSR. If the type
is a non-repeating PWL source, then the
time=infinity value is used as a DC analysis
source value. For example, the following statement is
treated as a DC source with value=1 for HB
analysis:
v1 1 0 PWL (0 0 1n 1 1u 1)
+ TRANFORHB=1
In contrast, the following statement is a 0V DC
source:
v1 1 0 PWL (0 0 1n 1 1u 1)
+ TRANFORHB=0
The following statement is treated as a periodic
source with a 1us period that uses PWL values:
v1 1 0 PWL (0 0 1n 1 0.999u 1 1u 0) R
+ TRANFORHB=1
To override the global TRANFORHB option, explicitly set
TRANFORHB for a voltage or current source.
DCOPEN
Switch for open DC connection when DC mag is not set.
• 0 (default): P element behaves as an impedance
termination.
• 1 : P element is considered an open circuit in DC
operating point analysis. DCOPEN=1 is mainly used in
.LIN analysis so the P element will not affect the
self-biasing device under test by opening the
termination at the operating point.
<z0=val>
(LIN analysis) System impedance used when converting
to a power source, inserted in series with the voltage
source. Currently, this only supports real impedance.
• When power=0, z0 defaults to 0.
• When power=1, z0 defaults to 50 ohms.
You can also enter zo=val.
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Parameter
Description
<RDC=val>
(DC analysis) Series resistance (overrides z0).
<RAC=val>
(AC analysis) Series resistance (overrides z0).
<RHBAC=val>
(HSPICE RF HBAC analysis) Series resistance
(overrides z0).
<RHB=val>
(HSPICE RF HB analysis) Series resistance (overrides
z0).
<RTRAN=val>
(Transient analysis) Series resistance (overrides z0).
<power=[0 | 1 | 2 | W | dbm]> (HSPICE RF) power switch
• When 0 (default), element treated as a voltage or
current source.
• When 1 or W, element treated as a power source,
realized as a voltage source with a series impedance.
In this case, the source value is interpreted as RMS
available power in units of Watts.
• When 2 or dbm, element treated as a power source in
series with the port imedance. Values are in dbms.
You can use this parameter for Transient analysis if the
power source is either DC or SIN.
Example
For example, the following port element specifications identify a 2-port network
with 50-Ohm reference impedances between the "in" and "out" nodes.
P1 in gnd port=1 z0=50
P2 out gnd port=2 z0=50
Computing scattering parameters requires z0 reference impedance values.
The order of the port parameters (in the P Element) determines the order of
the S, Y, and Z parameters. Unlike the .NET command, .LIN does not require
you to insert additional sources into the circuit. To calculate the requested
transfer parameters, HSPICE automatically inserts these sources as needed at
the port terminals. You can define an unlimited number of ports.
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Independent Source Functions
HSPICE or HSPICE RF uses the following types of independent source
functions:
■
Pulse (PULSE function)
■
Sinusoidal (SIN function)
■
Exponential (EXP function)
■
Piecewise linear (PWL function)
■
Single-frequency FM (SFFM function)
■
Single-frequency AM (AM function)
■
Pattern (PATTERN function)
■
Pseudo Random Bit Generator Source (PRBS function)
HSPICE also provides a data-driven version of PWL (not supported in HSPICE
RF). If you use the data-driven PWL, you can reuse the results of an
experiment or of a previous simulation, as one or more input sources for a
transient simulation.
If you use the independent sources supplied with HSPICE or HSPICE RF, you
can specify several useful analog and digital test vectors for steady state, time
domain, or frequency domain analysis. For example, in the time domain, you
can specify both current and voltage transient waveforms, as exponential,
sinusoidal, piecewise linear, AM, or single-sided FM functions.
Pulse Source Function
HSPICE or HSPICE RF provides a trapezoidal pulse source function, which
starts with an initial delay from the beginning of the transient simulation interval,
to an onset ramp. During the onset ramp, the voltage or current changes
linearly, from its initial value, to the pulse plateau value. After the pulse plateau,
the voltage or current moves linearly, along a recovery ramp, back to its initial
value. The entire pulse repeats, with a period named per, from onset to onset.
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The syntax for a pulse source, in an independent voltage or current source, is:
Vxxx n+ n- PU<LSE> <(>v1 v2 <td <tr <tf <pw
+ <per>>>>> <)>
Ixxx n+ n- PU<LSE> <(>v1 v2 <td <tr <tf <pw
+ <per>>>>> <)>
Parameter
Description
Vxxx, Ixxx
Independent voltage source, which exhibits the pulse response.
PULSE
Keyword for a pulsed time-varying source. The short form is PU.
v1
Initial value of the voltage or current, before the pulse onset (units of
volts or amps).
v2
Pulse plateau value (units of volts or amps).
td
Delay (propagation) time in seconds, from the beginning of the
transient interval, to the first onset ramp. Default=0.0; HSPICE or
HSPICE RF sets negative values to zero.
tr
Duration of the onset ramp (in seconds), from the initial value, to the
pulse plateau value (reverse transit time). Default=TSTEP.
tf
Duration of the recovery ramp (in seconds), from the pulse plateau,
back to the initial value (forward transit time). Default=TSTEP.
pw
Pulse width (the width of the plateau portion of the pulse), in
seconds. Default=TSTOP.
per
Pulse repetition period, in seconds. Default=TSTOP.
Table 8 Time-Value Relationship for a PULSE Source
136
Time
Value
0
v1
td
v1
td + tr
v2
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Table 8 Time-Value Relationship for a PULSE Source (Continued)
Time
Value
td + tr + pw
v2
td + tr + pw + tf
v1
tstop
v1
Linear interpolation determines the intermediate points.
Note: TSTEP is the printing increment, and TSTOP is the final time.
Example 1:
The following example shows the pulse source, connected between node 3 and
node 0. In the pulse:
■
The output high voltage is 1 V.
■
The output low voltage is -1 V.
■
The delay is 2 ns.
■
The rise and fall time are each 2 ns.
■
The high pulse width is 50 ns.
■
The period is 100 ns.
VIN 3 0 PULSE (-1 1 2NS 2NS 2NS 50NS 100NS)
Example 2:
The following example is a pulse source, which connects between node 99 and
node 0. The syntax shows parameter values for all specifications.
V1 99 0 PU lv hv tdlay tris tfall tpw tper
Example 3:
The following example shows an entire netlist, which contains a PULSE voltage
source. In the source:
■
The initial voltage is 1 volt.
■
The pulse voltage is 2 volts.
■
The delay time, rise time, and fall time are each 5 nanoseconds.
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■
The pulse width is 20 nanoseconds.
■
The pulse period is 50 nanoseconds.
You can find the sample netlist for this example in the following directory:
$installdir/demo/hspice/sources/pulse.sp
Figure 16 shows the result of simulating this netlist, in HSPICE or HSPICE RF.
Figure 16
138
Pulse Source Function
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Sinusoidal Source Function
HSPICE or HSPICE RF provides a damped sinusoidal source, which is the
product of a dying exponential with a sine wave. To apply this waveform, you
must specify:
■
Sine wave frequency
■
Exponential decay constant
■
Beginning phase
■
Beginning time of the waveform
Syntax
The syntax for a sinusoidal source in an independent voltage or current source
is:
Vxxx n+ n- SIN <(> vo va <freq <td <q <j>>>> <)>
Ixxx n+ n- SIN <(> vo va <freq <td <q <j>>>> <)>
Parameter
Description
Vxxx, Ixxx
Independent voltage source that exhibits the sinusoidal response.
SIN
Keyword for a sinusoidal time-varying source.
vo
Voltage or current offset, in volts or amps.
va
Voltage or current peak value (vpeak), in volts or amps.
freq
Source frequency in Hz. Default=1/TSTOP.
td
Time (propagation) delay before beginning the sinusoidal variation, in
seconds. Default=0.0. Response is 0 volts or amps, until HSPICE or
HSPICE RF reaches the delay value, even with a non-zero DC voltage.
q
Damping factor, in units of 1/seconds. Default=0.0.
j
Phase delay, in units of degrees. Default=0.0.
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The following table of expressions defines the waveform shape:
Table 9 Waveform Shape Expressions
Time
Value
0 to td
2⋅Π⋅ϕ
vo + va ⋅ SIN  --------------------
360
td to tstop
vo + va ⋅ Exp [ – ( Time – td ) Þ θ ]
ϕ 

SIN  2 ⋅ Π ⋅ freq ⋅ ( time – td ) + --------- 
360


In these expressions, TSTOP is the final time.
Example
VIN 3 0 SIN (0 1 100MEG 1NS 1e10)
This damped sinusoidal source connects between nodes 3 and 0. In this
waveform:
■
Peak value is 1 V.
■
Offset is 0 V.
■
Frequency is 100 MHz.
■
Time delay is 1 ns.
■
Damping factor is 1e10.
■
Phase delay is zero degrees.
See Figure 17 on page 141 for a plot of the source output.
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Figure 17
Sinusoidal Source Function
You can find the sample netlist for this example in the following directory:
$installdir/demo/hspice/sources/sin.sp
Table 10 SIN Voltage Source
Parameter
Value
initial voltage
0 volts
pulse voltage
1 volt
delay time
2 nanoseconds
frequency
100 MHz
damping factor
50 MHz
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Exponential Source Function
The general syntax for an exponential source, in an independent voltage or
current source, is:
Vxxx n+ n- EXP <(> v1 v2 <td1 <t1 <td2 <t2>>>> <)>
Ixxx n+ n- EXP <(> v1 v2 <td1 <t1 <td2 <t2>>>> <)>
Parameter
Description
Vxxx, Ixxx
Independent voltage source, exhibiting an exponential response.
EXP
Keyword for an exponential time-varying source.
v1
Initial value of voltage or current, in volts or amps.
v2
Pulsed value of voltage or current, in volts or amps.
td1
Rise delay time, in seconds. Default=0.0.
td2
Fall delay time, in seconds. Default=td1+TSTEP.
t1
Rise time constant, in seconds. Default=TSTEP.
t2
Fall time constant, in seconds. Default=TSTEP.
TSTEP is the printing increment, and TSTOP is the final time.
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The following table of expressions defines the waveform shape:
Table 11
Time
Value
0 to td1
v1
td1 to td2
– td1-
v1 + ( v2 – v1 ) ⋅ 1 – exp  – Time
-------------------------

τ
1
td2 to tstop
Time – td1 )- +
v1 + ( v2 – v1 ) ⋅ 1 – exp  – (------------------------------

τ
1
Time – td2 )
( v1 – v2 ) ⋅ 1 – exp  – (------------------------------

τ2
Example
VIN 3 0 EXP (-4 -1 2NS 30NS 60NS 40NS)
The above example describes an exponential transient source, which connects
between nodes 3 and 0. In this source:
■
Initial t=0 voltage is -4 V.
■
Final voltage is -1 V.
■
Waveform rises exponentially, from -4 V to -1 V, with a time constant of 30
ns.
■
At 60 ns, the waveform starts dropping to -4 V again, with a time constant of
40 ns.
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Figure 18
Exponential Source Function
You can find the sample netlist for this example in the following directory:
$installdir/demo/hspice/sources/exp.sp
This example shows an entire netlist, which contains an EXP voltage source. In
this source:
144
■
Initial t=0 voltage is -4 V.
■
Final voltage is -1 V.
■
Waveform rises exponentially, from -4 V to -1 V, with a time constant of 30
ns.
■
At 80 ns, the waveform starts dropping to -4 V again, with a time constant of
40 ns.
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Piecewise Linear (PWL) Source Function
The general syntax for a piecewise linear source, in an independent voltage or
current source, is:
General Form
Vxxx n+ n- PWL <(> t1 v1 <t2 v2 t3 v3…> <R <=repeat>>
+ <TD=delay> <)>
Ixxx n+ n- PWL <(> t1 v1 <t2 v2 t3 v3…> <R <=repeat>>
+ <TD=delay> <)>
MSINC and ASPEC Form
Vxxx n+ n- PL <(> v1 t1 <v2 t2 v3 t3…> <R <=repeat>>
+ <TD=delay> <)>
Ixxx n+ n- PL <(> v1 t1 <v2 t2 v3 t3…> <R <=repeat>>
+ <TD=delay> <)>
Parameter
Description
Vxxx, Ixxx
Independent voltage source; uses a piecewise linear response.
PWL
Keyword for a piecewise linear time-varying source.
v1 v2 … vn
Current or voltage values at the corresponding timepoint.
t1 t2 … tn
Timepoint values, where the corresponding current or voltage value is
valid.
R=repeat
Keyword and time value to specify a repeating function. With no
argument, the source repeats from the beginning of the function.
repeat is the time, in units of seconds, which specifies the start point
of the waveform to repeat. This time needs to be less than the greatest
time point, tn.
TD=delay
Time, in units of seconds, which specifies the length of time to delay
(propagation delay) the piecewise linear function.
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■
Each pair of values (t1, v1) specifies that the value of the source is v1 (in
volts or amps), at time t1.
■
Linear interpolation between the time points determines the value of the
source, at intermediate values of time.
■
The PL form of the function accommodates ASPEC style formats, and
reverses the order of the time-voltage pairs to voltage-time pairs.
■
If you do not specify a time-zero point, HSPICE or HSPICE RF uses the DC
value of the source, as the time-zero source value.
■
HSPICE or HSPICE RF does not force the source to terminate at the
TSTOP value, specified in the .TRAN statement.
If the slope of the piecewise linear function changes below a specified
tolerance, the timestep algorithm might not choose the specified time points as
simulation time points. To obtain a value for the source voltage or current,
HSPICE or HSPICE RF extrapolates neighboring values. As a result, the
simulated voltage might deviate slightly from the voltage specified in the PWL
list. To force HSPICE or HSPICE RF to use the specified values, use .OPTION
SLOPETOL, which reduces the slope change tolerance.
R causes the function to repeat. You can specify a value after this R, to indicate
the beginning of the function to repeat. The repeat time must equal a
breakpoint in the function. For example, if t1 = 1, t2 = 2, t3 = 3, and t4 = 4, then
the repeat value can be 1, 2, or 3.
Specify TD=val to cause a delay at the beginning of the function. You can use
TD with or without the repeat function.
Example
You can find the sample netlist for this example in the following directory:
$installdir/demo/hspice/sources/pwl.sp
This example shows an entire netlist, which contains two piecewise linear
voltage sources. The two sources have the same function:
■
First is in normal format. The repeat starts at the beginning of the function.
■
Second is in ASPEC format. The repeat starts at the first timepoint.
See Figure 19 for the difference in responses.
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Figure 19
Results of Using the Repeat Function
Data-Driven Piecewise Linear Source
The general syntax for a data-driven piecewise linear source, in an
independent voltage or current source, is:
Vxxx n+ n- PWL (TIME, PV)
Ixxx n+ n- PWL (TIME, PV)
.DATA dataname
TIME PV
t1 v1
t2 v2
t3 v3
t4 v4
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.. ..
.ENDDATA
.TRAN DATA=datanam
HSPICE RF does not support the data-driven PWL syntax.
Parameter
Description
TIME
Parameter name for time value, provided in a .DATA statement.
PV
Parameter name for amplitude value, provided in a .DATA statement.
You must use this source with a .DATA statement that contains time-value
pairs. For each tn-vn (time-value) pair that you specify in the .DATA block, the
data-driven PWL function outputs a current or voltage of the specified tn
duration and with the specified vn amplitude.
When you use this source, you can reuse the results of one simulation, as an
input source in another simulation. The transient analysis must be data-driven.
Example
You can find the sample netlist for this example in the following directory:
$installdir/demo/hspice/sources/datadrive_pwl.sp
This example is an entire netlist, containing two data-driven, piecewise linear
voltage sources. The .DATA statement contains the two sets of values
referenced in the pv1 and pv2 sources. The .TRAN statement references the
data name.
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Single-Frequency FM Source Function
The general syntax for including a single-frequency, frequency-modulated
source in an independent voltage or current source is:
Vxxx n+ n- SFFM <(> vo va <fc <mdi <fs>>> <)>
Ixxx n+ n- SFFM <(> vo va <fc <mdi <fs>>> <)>
Parameter
Description
Vxxx, Ixxx
Independent voltage source, which exhibits the frequencymodulated response.
SFFM
Keyword for a single-frequency, frequency-modulated, time-varying
source.
vo
Output voltage or current offset, in volts or amps.
va
Output voltage or current amplitude, in volts or amps.
fc
Carrier frequency, in Hz. Default=1/TSTOP.
mdi
Modulation index, which determines the magnitude of deviation from
the carrier frequency. Values normally lie between 1 and 10.
Default=0.0.
fs
Signal frequency, in Hz. Default=1/TSTOP.
The following expression defines the waveform shape:
sourcevalue = vo + va ⋅ SIN [ 2 ⋅ π ⋅ fc ⋅ Time + mdi ⋅ SIN ( 2 ⋅ π ⋅ fs ⋅ Time ) ]
Example
You can find the sample netlist for this example in the following directory:
$installdir/demo/hspice/sources/sffm.sp
This example shows an entire netlist, which contains a single-frequency,
frequency-modulated voltage source. In this source.
■
The offset voltage is 0 volts.
■
The maximum voltage is 1 millivolt.
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■
The carrier frequency is 20 kHz.
■
The signal is 5 kHz, with a modulation index of 10 (the maximum wavelength
is roughly 10 times as long as the minimum).
Figure 20
150
Single Frequency FM Source
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Amplitude Modulation Source Function
The general syntax for including a single-frequency, frequency-modulated
source in an independent voltage or current source is:
Vxxx n+ n- AM < (> sa oc fm fc <td> <)>
Ixxx n+ n- AM < (> sa oc fm fc <td> <)>
Parameter
Description
Vxxx, Ixxx
Independent voltage source, which exhibits the amplitude-modulated
response.
AM
Keyword for an amplitude-modulated, time-varying source.
sa
Signal amplitude, in volts or amps. Default=0.0.
fc
Carrier frequency, in hertz. Default=0.0.
fm
Modulation frequency, in hertz. Default=1/TSTOP.
oc
Offset constant, a unitless constant that determines the absolute
magnitude of the modulation. Default=0.0.
td
Delay time (propagation delay) before the start of the signal, in seconds.
Default=0.0.
The following expression defines the waveform shape:
sourcevalue = sa ⋅ { oc + SIN [ 2 ⋅ π ⋅ fm ⋅ ( Time – td ) ] } ⋅ SIN [ 2 ⋅ π ⋅ fc ⋅ ( Time – td ) ]
Example
You can find the sample netlist for this example in the following directory:
$installdir/demo/hspice/sources/amsrc.sp
This example shows an entire netlist, which contains three amplitudemodulated voltage sources.
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■
■
■
152
In the first source:
•
Amplitude is 10.
•
Offset constant is 1.
•
Carrier frequency is 1 kHz.
•
Modulation frequency of 100 Hz.
•
Delay is 1 millisecond.
In the second source, only the amplitude and offset constant differ from the
first source:
•
Amplitude is 2.5.
•
Offset constant is 4.
•
Carrier frequency is 1 kHz.
•
Modulation frequency of 100 Hz.
•
Delay is 1 millisecond.
The third source exchanges the carrier and modulation frequencies,
compared to the first source:
•
Amplitude is 10.
•
Offset constant is 1.
•
Carrier frequency is 100 Hz.
•
Modulation frequency of 1 kHz.
•
Delay is 1 millisecond.
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Figure 21
Amplitude Modulation Plot
Pattern Source Function
The pattern source function uses four states, '1','0','m', and 'z', which represent
the high, low, middle voltage, or current and high impedance state respectively.
The series of these four states is called a “b-string.”
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The following general syntax is for including a pattern source in an independent
voltage or current source:
Syntax
Vxxx n+ n- PAT <(> vhi vlo td tr tf
+ <R=repeat> <)>
Ixxx n+ n- PAT <(> vhi vlo td tr tf
+ <R=repeat> <)>
154
tsample data <RB=val>
tsample data <RB=val>
Parameter
Description
Vxxx, Ixxx
Independent voltage source that exhibits a pattern response.
PAT
Keyword for a pattern time-varying source.
vhi
High voltage or current value for pattern sources (units of volts
or amps).
vlo
Low voltage or current value for pattern sources (units of volts
or amps).
td
Delay (propagation) time in seconds from the beginning of the
transient interval to the first onset ramp. It can be negative. The
state in the delay time is the same as the first state specified in
data.
tr
Duration of the onset ramp (in seconds) from the low value to
the high value (reverse transit time).
tf
Duration of the recovery ramp (in seconds) from the high value
back to the low value (forward transit time).
tsample
Time spent at '0' or '1' or 'M' or 'Z' pattern value (in seconds).
data
String of '1' ,'0','M', 'Z' representing a pattern source. The first
alphabet must be 'B', which represents it is a binary bit stream.
This series is called b-string. '1' represents the high voltage or
current value, '0' is the low voltage or current value, 'M'
represents the value which is equal to 0.5*(vhi+vlo).'Z'
represents the high impedance state (only for voltage source).
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Parameter
Description
RB
Keyword to specify the starting bit when repeating. The repeat
data starts from the bit indicated by RB. RB must be an integer.
If the value is larger than the length of the b-string, an error is
reported. If the value is less than 1, it is set to 1 automatically.
R=repeat
Keyword to specify how many times to execute the repeating
operation be executed. With no argument, the source repeats
from the beginning of the b-string. If R=-1, it means the
repeating operation will continue forever. R must be an integer
and if it is less than -1, it will be set to 0 automatically.
The time from 0 to the first transition is:
tdelay+N*tsample-tr(tf)/2
■
N is the number of the same bit, from the beginning.
■
If the first transition is rising, this equation uses tr.
■
If the first transition is falling, it uses tf.
Example
The following example shows a pattern source with two b-strings:
*FILE: pattern source gereral form
v1 1 0 pat (5 0 0n 1n 1n 5n b1011 r=1 rb=2 b0m1z)
r1 1 0 1
In this pattern:
■
High voltage is 5 v
■
Low voltage is 0 v
■
Time delay is 0 n
■
Rise time is 1 n
■
Fall time is 1 n
■
Sample time is 5 n
The first b-string is 1011, which repeats once and then repeats from the
second bit, which is 0. The second b-string is 0m1z. Since neither R and RB is
specified here, they are set to the default value, which is R=0, RB=1.
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Example
The following b-string and its repeat time R and repeating start bit RB cannot
use parameter—it is considered as a undivided unit in HSPICE and can only be
defined in pattern command.
*FILE:pattern source using parameter
.param td=40ps tr=20ps tf=80ps tsample=400ps
VIN 1 0 PAT (2 0 td tr tf tsample b1010110 r=2)
r1 1 0 1
In this pattern:
■
High voltage is 2 V.
■
Low voltage is 0 V.
■
Time delay is 40 ps.
■
Rise time is 20 ps.
■
Fall time is 80 ps.
■
Sample time is 400 ps.
■
Data is 1010110.
Nested-Structure Pattern Source
HSPICE provides Nested Structure (NS) for the pattern source function to
construct complex waveforms. NS is a combination of a b-string and other
nested structures defined in pattern command, which is explained later in this
section.
The following general syntax is for an NS pattern source.
Syntax
Vxxx n+ n- PAT <(> vhi vlo td tr tf tsample
+ [component 1 ... component n] <RB=val> <R=repeat> <)>
Ixxx n+ n- PAT <(> vhi vlo td tr tf tsample
+ [component 1 ... component n] <RB=val> <R=repeat> <) >
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Parameter
Description
component
Component is the element that makes up NS, which can be
a b-string or a patname defined in other .PAT commands.
Brackets ( [ ] ) must be used.
RB=val
Keyword to specify the starting component when repeating.
The repeat data starts from the component indicated by
RB. RB must be an integer. If RB is larger than the length
of the NS, an error is reported. If RB is less than 1, it is
automatically set to 1.
R=repeat
Keyword to specify how many times the repeating operation
is executed. With no argument, the source repeats from the
beginning of the NS. If R=-1, the repeating operation
continuse forever. R must be an integer, and if it is less than
-1, it is automatically set to 0.
If the component is a b-string, it can also be followed by R=repeat and RB=val
to specify the repeat time and repeating start bit.
Example
*FILE: Pattern source using nested structure
v1 1 0 pat (5 0 0n 1n 1n 5n [b1011 r=1 rb=2 b0m1z] r=2 rb=2)
r1 1 0 1
When expanding the nested structure, you get the pattern source like this:
'b1011 r=1 rb=2 b0m1z b0m1z b0m1z'
The whole NS repeats twice, and each time it repeats from the second b0m1z
component.
Pattern-Command Driven Pattern Source
The following general syntax is for including a pattern-command driven pattern
source in an independent voltage or current source. The RB and R of a b-string
or NS can be reset in an independent source. With no argument, the R and RB
are the same when defined in the pattern command.
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Syntax
Vxxx n+ n- PAT <(> vhi vlo td tr tf tsample PatName <RB=val>
+ <R=repeat> <)>
Ixxx n+ n- PAT <(> vhi vlo td tr tf tsample Patname <RB=val>
+ <R=repeat> <)>
Additional syntax applies to the pattern-command driven pattern source:
.PAT <PatName>=data <RB=val> <R=repeat>
.PAT <patName>=[component 1 ... component n] <RB=val>
+ <R=repeat>
The PatName is the pattern name that has an associated b-string or nested
structure.
Example 1
v1 1 0 pat (5 0 0n 1n 1n 5n a1 a2 r=2 rb=2)
.PAT a1=b1010 r=1 rb=1
.PAT a2=b0101 r=1 rb=1
The final pattern source is:
b1010 r=1 rb=1 b0101 r=2 rb=2
When the independent source uses the pattern command to specify its pattern
source, r and rb can be reset.
Example 2
*FILE 2: Pattern source driven by pattern command
v1 1 0 pat (5 0 0n 1n 1n 5n [a1 b0011] r=1 rb=1)
.PAT a1=[b1010 b0101] r=0 rb=1
The final pattern source is:
b1010 b0101 b0011 b1010 b0101 b0011
The a1 is a predefined NS, and it can be referenced by pattern source.
Pseudo Random-Bit Generator Source (PRBS Function)
The Pseudo Random Bit Generator Source can be used in several applications
from cryptography and bit-error-rate measurement, to wireless communication
systems employing spread spectrum or CDMA techniques. In general, PRBS
uses a Linear Feedback Shift Register (LFSR) to generate a pseudo random bit
sequence.
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Linear Feedback Shift Register
LFSR consists of several simple-shift registers in which a binary-weighted
modulo-2 sum of the taps is fed back to the input. The modulo-2 sum of two1bit binary numbers yields 0 if the two numbers are identical and 1 if the differ is
0+0=0, 0+1=1, or 1+1=0.
Figure 22
LFSR Diagram
g(0)
g(1)
g(2)
g(m-1)
g(m)
D(n)
input
D(n-1)
D(n-2)
D(2)
D(1)
output
For any given tap, the weight “gi” is either 0, (meaning "no connection"), or 1,
(meaning it is fed back). Two exceptions are g0 and gm, which are always 1
and therefore always connected. The gm is not really a feedback connection,
but rather an input of the shift register that is assigned a feedback weight for
mathematical purposes.
The maximum number of bits is defined by the first number in your TAPS
definition. For example [23, 22, 21, 20, 19, 7] denotes a 23 stage LFSR. The
TAPS definition is a specific feedback tap sequence that generates an MSequence PRB. The LFSR stages limit is between 2 and 30. The seed cannot
be set to zero; HSPICE reports an error and exits the simulation if you set the
seed to zero.
Conventions for Feedback Tap Specification
A given set of feedback connections can be expressed in a convenient and
easy-to-use shorthand form with the connection numbers listed within a pair of
brackets. The g0 connection is implied and not listed since it is always
connected. Although gm is also always connected, it is listed in order to convey
the shift register size (number of registers).
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The following line is a set of feedback taps where j is the total number of
feedback taps (not including g0), f(1) = m is the highest-order feedback tap
(and the size of the LFSR), and f(j) are the remaining feedback taps:
[f(1), f(2), f(3), ..., f(j)]
Example
The following line shows that the number of registers is 7 and the total number
of feedback taps is 4:
[7, 3, 2, 1]
The following feedback input applies for this specification:
D(n)=[D(n-7)+D(n-3)+D(n-2)+D(n-1)] mod 2
PRBS Syntax
The Pseudo Random Bit Generator Source uses the following syntax.
Syntax
lxxx n+ n- LFSR <(> vlow vhigh tdelay trise tfall rate seed <[>
+ taps <]> <rout=val> <)>
160
Parameter
Description
LFSR
Specifies the voltage or current source as PRBS.
vlow
The minimum voltage or current level.
vhigh
The maximum voltage or current level.
tdelay
Specifies the initial time delay to the first transition.
trise
Specifies the duration of the onset ramp (in seconds), from
the initial value to the pulse plateau value (reverse transit
time).
tfall
Specifies the duration of the recovery ramp (in seconds),
from the pulse plateau, back to the initial value (forward
transit time).
rate
The bit rate.
seed
The initial value loaded into the shift register.
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Parameter
Description
taps
The bits used to generate feedback.
rout
The output resistance.
Example 1
The following example shows the pattern source that is connected between
node in and node gnd:
vin in gnd LFSR (0 1 1m 1n 1n 10meg 1 [5, 2] rout=10)
Where,
■
The output low voltage is 0 , and the output high voltage is 1 v.
■
The delay time is 1 ms.
■
The rise and fall times are each 1 ns.
■
The bit rate is 10meg bits/s.
■
The seed is 1.
■
The taps are [5, 2].
■
The output resistance is 10 ohm.
■
The output from the LFSR is:
1000010101110110001111100110100.....
Example 2
The following example shows the pattern source connected between node 1
and node 0:
.PARAM td1 = 2.5m tr1 = 2n
vin 1 0 LFSR (2 4 td1 tr1 1n 6meg 2 [10, 5, 3, 2])
Where,
■
The output low voltage is 2 v, and the output high voltage is 4 v.
■
The delay is 2.5 ms.
■
The rise time is 2 ns, and the fall time is 1 ns.
■
The bit rate is 6meg bits/s.
■
The seed is 2.
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■
The taps are [10, 5, 3, 2].
■
The output resistance is 0 ohm.
Example 3
This example shows an entire netlist, which contains one PRBS voltage
source:
You can find the sample netlist for this example in the following directory:
$installdir/demo/hspice/sources/prbs.sp
Voltage and Current Controlled Elements
HSPICE or HSPICE RF provides two voltage-controlled and two currentcontrolled elements, known as E, G, H, and F Elements. You can use these
controlled elements to model:
■
MOS transistors
■
bipolar transistors
■
tunnel diodes
■
SCRs
■
analog functions, such as:
•
operational amplifiers
•
summers
•
comparators
•
voltage-controlled oscillators
•
modulators
•
switched capacitor circuits
Depending on whether you used the polynomial or piecewise linear functions,
the controlled elements can be:
■
Linear functions of controlling-node voltages.
■
Non-linear functions of controlling-node voltages.
■
Linear functions of branch currents.
■
Non-linear functions of branch currents.
The functions of the E, F, G, and H controlled elements are different.
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■
■
■
The E element can be:
•
A voltage-controlled voltage source
•
A behavioral voltage source
•
An ideal op-amp.
•
An ideal transformer.
•
An ideal delay element.
•
A piecewise linear, voltage-controlled, multi-input AND, NAND, OR, or
NOR gate.
The F element can be:
•
A current-controlled current source.
•
An ideal delay element.
•
A piecewise linear, current-controlled, multi-input AND, NAND, OR, or
NOR gate.
The G element can be:
•
A voltage-controlled current source.
•
A behavioral current source.
•
A voltage-controlled resistor.
•
A piecewise linear, voltage-controlled capacitor.
•
An ideal delay element.
•
A piecewise linear, multi-input AND, NAND, OR, or NOR gate.
The H element can be:
•
A current-controlled voltage source.
•
An ideal delay element.
•
A piecewise linear, current-controlled, multi-input AND, NAND, OR, or
NOR gate.
The next section describes polynomial and piecewise linear functions. Later
sections describe element statements for linear or non-linear functions. See the
HSPICE Applications Manual for detailed PWL examples.
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Polynomial Functions
You can use the controlled element statement to define the controlled output
variable (current, resistance, or voltage), as a polynomial function of one or
more voltages or branch currents. You can select three polynomial equations,
using the POLY(NDIM) parameter in the E, F, G, or H element statement.
Value
Description
POLY(1)
One-dimensional equation (function of one controlling variable).
POLY(2)
Two-dimensional equation (function of two controlling variables).
POLY(3)
Three-dimensional equation (function of three controlling variables).
Each polynomial equation includes polynomial coefficient parameters (P0, P1
… Pn), which you can set to explicitly define the equation.
One-Dimensional Function
If the function is one-dimensional (a function of one branch current or node
voltage), the following expression determines the FV function value:
FV = P0 + ( P1 ⋅ FA ) + ( P2 ⋅ FA 2 ) + ( P3 ⋅ FA 3 ) + ( P4 ⋅ FA 4 ) + ( P5 ⋅ FA 5 ) + …
Parameter
Description
FV
Controlled voltage or current, from the controlled source.
P0. . .PN
Coefficients of a polynomial equation.
FA
Controlling branch current, or nodal voltage.
Note: If you specify one coefficient in a one-dimensional polynomial, HSPICE
or HSPICE RF assumes that the coefficient is P1 (P0 = 0.0). Use this as
input for linear controlled sources.
The following controlled source statement is a one-dimensional function. This
voltage-controlled voltage source connects to nodes 5 and 0.
E1 5 0 POLY(1) 3 2 1 2.5
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1. The single-dimension polynomial function parameter, POLY(1), informs
HSPICE or HSPICE RF that E1 is a function of the difference of one nodal
voltage pair.
In this example, the voltage difference is between nodes 3 and 2, so
FA=V(3,2).
2. The dependent source statement then specifies that P0=1 and P1=2.5.
From the one-dimensional polynomial equation above, the defining equation
for V(5,0) is:
V ( 5, 0 ) = 1 + 2.5 ⋅ V (3,2)
You can also express V(5,0) as E1:
E1 = 1 + 2.5 ⋅ V (3,2)
Two-Dimensional Function
If the function is two-dimensional (that is, a function of two node voltages or two
branch currents), the following expression determines FV:
2
2
FV = P0 + ( P1 ⋅ FA ) + ( P2 ⋅ FB ) + ( P3 ⋅ FA ) + ( P4 ⋅ FA ⋅ FB ) + ( P5 ⋅ FB )
3
2
2
3
+ ( P6 ⋅ FA ) + ( P7 ⋅ FA ⋅ FB ) + ( P8 ⋅ FA ⋅ FB ) + ( P9 ⋅ FB ) + ...
For a two-dimensional polynomial, the controlled source is a function of two
nodal voltages or currents. To specify a two-dimensional polynomial, set
POLY(2) in the controlled source statement.
For example, generate a voltage-controlled source that specifies the controlled
voltage, V(1,0), as:
V ( 1, 0 ) = 3 ⋅ V (3,2) + 4 ⋅ V (7,6) 2
or
E1 = 3 ⋅ V (3,2) + 4 ⋅ V (7,6) 2
To implement this function, use this controlled-source element statement:
E1 1 0 POLY(2) 3 2 7 6 0 3 0 0 0 4
This example specifies a controlled voltage source, which connects between
nodes 1 and 0. Two differential voltages control this voltage source:
■
Voltage difference between nodes 3 and 2.
■
Voltage difference between nodes 7 and 6.
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That is, FA=V(3,2), and FB=V(7,6). The polynomial coefficients are:
■
P0=0
■
P1=3
■
P2=0
■
P3=0
■
P4=0
■
P5=4
Three-Dimensional Function
For a three-dimensional polynomial function, with FA, FB, and FC as its
arguments, the following expression determines the FV function value:
FV = P0 + ( P1 ⋅ FA ) + ( P2 ⋅ FB ) + ( P3 ⋅ FC ) + ( P4 ⋅ FA 2 )
+ ( P5 ⋅ FA ⋅ FB ) + ( P6 ⋅ FA ⋅ FC ) + ( P7 ⋅ FB 2 ) + ( P8 ⋅ FB ⋅ FC )
+ ( P9 ⋅ FC 2 ) + ( P10 ⋅ FA 3 ) + ( P11 ⋅ FA 2 ⋅ FB ) + ( P12 ⋅ FA 2 ⋅ FC )
+ ( P13 ⋅ FA ⋅ FB 2 ) + ( P14 ⋅ FA ⋅ FB ⋅ FC ) + ( P15 ⋅ FA ⋅ FC 2 )
+ ( P16 ⋅ FB 3 ) + ( P17 ⋅ FB 2 ⋅ FC ) + ( P18 ⋅ FB ⋅ FC 2 )
+ ( P19 ⋅ FC 3 ) + ( P20 ⋅ FA 4 ) + …
For example, generate a voltage-controlled source that specifies the voltage
as:
V ( 1, 0 ) = 3 ⋅ V (3,2) + 4 ⋅ V (7,6) 2 + 5 ⋅ V (9,8) 3
or
E1 = 3 ⋅ V (3,2) + 4 ⋅ V (7,6) 2 + 5 ⋅ V (9,8) 3
The resulting three-dimensional polynomial equation is:
FA = V (3,2)
FB = V (7,6)
FC = V (9,8) [
P1 = 3
P7 = 4
P19 = 5
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Substitute these values into the voltage controlled voltage source statement:
E1 1 0 POLY(3) 3 2 7 6 9 8 0 3 0 0 0 0 0 4 0 0 0 0 0 0
+ 0 0 0 0 0 5
The preceding example specifies a controlled voltage source, which connects
between nodes 1 and 0. Three differential voltages control this voltage source:
■
Voltage difference between nodes 3 and 2.
■
Voltage difference between nodes 7 and 6.
■
Voltage difference between nodes 9 and 8.
That is:
■
FA=V(3,2)
■
FB=V(7,6)
■
FC=V(9,8)
The statement defines the polynomial coefficients as:
■
P1=3
■
P7=4
■
P19=5
■
Other coefficients are zero.
Piecewise Linear Function
You can use the one-dimensional piecewise linear (PWL) function to model
special element characteristics, such as those of:
■
tunnel diodes
■
silicon-controlled rectifiers
■
diode breakdown regions
To describe the piecewise linear function, specify measured data points.
Although data points describe the device characteristic, HSPICE or HSPICE
RF automatically smooths the corners, to ensure derivative continuity. This, in
turn, results in better convergence.
The DELTA parameter controls the curvature of the characteristic at the
corners. The smaller the DELTA, the sharper the corners are. The maximum
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DELTA is limited to half of the smallest breakpoint distance. If the breakpoints
are sufficiently separated, specify the DELTA to a proper value.
■
You can specify up to 100 point pairs.
■
You must specify at least two point pairs (each point consists of an x and a
y coefficient).
To model bidirectional switch or transfer gates, G Elements use the NPWL and
PPWL functions, which behave the same way as NMOS and PMOS transistors.
You can also use the piecewise linear function to model multi-input AND,
NAND,OR, and NOR gates. In this usage, only one input determines the state
of the output.
■
In AND and NAND gates, the input with the smallest value determines the
corresponding output of the gates.
■
In OR and NOR gates, the input with the largest value determines the
corresponding output of the gates.
Power Sources
This section describes independent sources and controlled sources.
Independent Sources
A power source is a special kind of voltage or current source, which supplies
the network with a pre-defined power that varies by time or frequency. The
source produces a specific input impedance.
To apply a power source to a network, you can use either:
■
A Norton-equivalent circuit (if you specify this circuit and a current source)—
the I (current source) element, or
■
A Thevenin-equivalent circuit (if you specify this circuit and a voltage
source)—the V (voltage source) element.
As with other independent sources, simulation assumes that positive current
flows from the positive node, through the source, to the negative node. A power
source is a time-variant or frequency-dependent utility source; therefore, the
value/phase can be a function of either time or frequency.
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A power source is a sub-class of the independent voltage/current source, with
some additional keywords or parameters:
■
You can use I and V elements in DC, AC, and transient analysis.
■
The I and V elements can be data-driven.
Supported formats include:
■
PULSE, a trapezoidal pulse function.
■
PWL, a piecewise linear function, with repeat function.
■
PL, a piecewise linear function. PWL and PL are the same piecewise linear
function, except PL uses the v1 t1 pair instead of the t1 v1 pair.
■
SIN, a damped sinusoidal function.
■
EXP, an exponential function.
■
SFFM, a single-frequency FM function.
■
AM, an amplitude-modulation function.
Syntax
If you use the power keyword in the netlist, then simulation recognizes a
current/voltage source as a power source:
Vxxx node+ node- power=<powerVal <powerFun>> imp=value1
+ imp_ac=value2,value3 powerFun=<FREQ <TIME>>(...)
Ixxx node+ node- power=<powerVal <powerFun>> imp=value1
+ imp_ac=value2,value3 powerFun=<FREQ <TIME>>(...)
Parameter
Description
powerVal
A constant power source supplies the available power. If you specify
option=POWER_DB, then the value is in decibels; otherwise it is in
Watts*POWER_SCAL. In this equation, POWER_SCAL is a scaling
factor that you specify in the .OPTION statement.
powerFun
This function name indicates the time-variant or frequency-variant
power source. In this equation, powerFun defines the functional
dependence on time or frequency.
• If the function name for powerFun is FREQ, then it is a frequency
power source: FREQ(freq1, val1, freq2, val2,...)
• If the function name for powerFun is TIME, then it is a piece-wise
time variant function: TIME(t1, val1, t2, val2...)
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Parameter
Description
imp=
DC impedance value.
imp_ac=
Magnitude and phase offset (in degrees) of AC impedance.
Example 1
V11 10 20 power=5 imp=5K
This example applies a 5-decibel/unit power source to node 10 and node 20, in
a Thevenin-equivalent manner. The impedance of this power source is 5k
Ohms.
Example 2
Iname 1 0 power=20 imp=9MEG
This example applies a 20-decibel/unit power source to node 1 and to ground,
in a Norton-equivalent manner. The source impedance is 9 mega-ohms.
Example 3
V5 6 0 power=FREQ(10HZ, 2, 10KHZ, 0.01) imp=2MEG
+ imp_ac=(100K, 60)
V5 6 0 power=func1 imp=2MEG imp_ac=(100K, 60DEC)
+ func1=FREQ(10HZ, 2, 10KHZ, 0.01)
In the two preceding examples, a power source operates at two different
frequencies, with two different values:
■
At 10 Hz, the power value is 2 decibel/unit.
■
At 10 kHz, the power value is 0.01 decibel/unit.
Also in these examples:
170
■
The DC impedance is 2 mega-ohms.
■
The AC impedance is 100 kilo-ohms.
■
The phase offset is 60 degrees.
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Table 12 Independent Source Options
Option
Description
POWER_SCAL
Sets the scaling factor for power values.
• If you specify this value, the power unit is in
Watts*POWER_SCAL.
• Default is 1.
POWER_DB
Specifies that the power value is in decibels.
Outputs
None.
Controlled Sources
In addition to independent power sources, you can also create four types of
controlled sources:
■
Voltage-controlled voltage source (VCVS), or E element
■
Current-controlled current source (CCCS), or F element
■
Voltage-controlled current source (VCCS), or G element
■
Current-controlled voltage source (CCVS), or H element
Voltage-Dependent Voltage Sources — E Elements
This section explains E Element syntax statements, and defines their
parameters. See also “Using G and E Elements” in the HSPICE Applications
Manual.
■
Level=1 is an OPAMP.
■
Level=2 is a TRANSFORMER.
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Voltage-Controlled Voltage Source (VCVS)
The syntax is:
Linear
Exxx n+ n- <VCVS> in+ in- gain <MAX=val> <MIN=val>
+ <SCALE=val> <TC1=val> <TC2=val><ABS=1> <IC=val>
Polynomial (POLY)
Exxx n+ n- <VCVS> POLY(NDIM) in1+ in1- ...
+ inndim+ inndim-<TC1=val> <TC2=val> <SCALE=val>
+ <MAX=val> <MIN=val> <ABS=1> p0 <p1…> <IC=val>
In this syntax, dim (dimensions)< 3.
Piecewise Linear (PWL)
Exxx n+ n- <VCVS> PWL(1) in+ in<DELTA=val>
+ <SCALE=val> <TC1=val> <TC2=val> x1,y1 x2,y2
+ x100,y100 <IC=val>
...
Multi-Input Gates
Exxx n+ n- <VCVS> gatetype(k) in1+ in1- ... inj+ inj+ <DELTA=val> <TC1=val> <TC2=val> <SCALE=val>
+ x1,y1 ...
x100,y100 <IC=val>
In this syntax, gatetype(k) can be AND, NAND, OR, or NOR gates.
Delay Element
Exxx n+ n- <VCVS> DELAY in+ in- TD=val <SCALE=val>
+ <TC1=val> <TC2=val> <NPDELAY=val>
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Laplace Transform
Syntax
Transconductance H(s):
Gxxx n+ n- LAPLACE in+ in- k0, k1, ..., kn / d0,
+ d1, ..., dm
<SCALE=val> <TC1=val> <TC2=val> <M=val>
Voltage Gain H(s):
Exxx n+ n- LAPLACE in+ in- k0, k1, ..., kn / d0,
+ d1, ..., dm
<SCALE=val> <TC1=val> <TC2=val>
H(s) is a rational function, in the following form:
k0 + k1 s + … + kn sn
H ( s ) = --------------------------------------------------d0 + d1 s + … + dm s m
You can use parameters to define the values of all coefficients (k0, k1, ..., d0,
d1, ...).
Example
Glowpass 0 out LAPLACE in 0
Ehipass out 0 LAPLACE in 0
1.0 / 1.0
2.0
2.0
1.0
0.0,0.0,0.0,1.0 / 1.0,2.0,2.0,1.0
The Glowpass element statement describes a third-order low-pass filter, with
the transfer function:
1
H ( s ) = ---------------------------------------1 + 2s + 2s 2 + s 3
The Ehipass element statement describes a third-order high-pass filter, with
the transfer function:
s3
H ( s ) = ---------------------------------------1 + 2s + 2s 2 + s 3
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Pole-Zero Function
Syntax
Transconductance H(s):
Gxxx n+ n- POLE in+ in- a αz1, fz1, ..., αzn, fzn / b,
+ αp1, fp1, ..., αpm, fpm <SCALE=val> <TC1=val>
+ <TC2=val> <M=val>
Voltage Gain H(s):
Exxx n+ n- POLE in+ in- a αz1, fz1, ..., αzn, fzn / b,
+ αp1, fp1, ..., αpm, fpm <SCALE=val> <TC1=val>
+ <TC2=val>
The following equation defines H(s) in terms of poles and zeros:
a ⋅ ( s + α z1 – j2 π f z1 )… ( s + α zn – j2 π f zn ) ( s + α zn + j2 π f zn )
H ( s ) = -----------------------------------------------------------------------------------------------------------------------------------------------------b ⋅ ( s + α p1 – j2 π f p1 )… ( s + α pm – j2 π f pm ) ( s + α pm + j2 π f pm )
The complex poles or zeros are in conjugate pairs. The element description
specifies only one of them, and the program includes the conjugate. You can
use parameters to specify the a, b, α, and f values.
Example
Ghigh_pass 0 out POLE in 0 1.0 0.0,0.0 / 1.0 0.001,0.0
Elow_pass out 0 POLE in 0 1.0 / 1.0, 1.0,0.0 0.5,0.1379
The Ghigh_pass statement describes a high-pass filter, with the transfer
function:
1.0 ⋅ ( s + 0.0 + j ⋅ 0.0 ) H ( s ) = ---------------------------------------------------------1.0 ⋅ ( s + 0.001 + j ⋅ 0.0 )
The Elow_pass statement describes a low-pass filter, with the transfer
function:
1.0
H ( s ) = --------------------------------------------------------------------------------------------------------------------------------------------------1.0 ⋅ ( s + 1 ) ( s + 0.5 + j2 π ⋅ 0.1379 ) ( s + 0.5 – ( j2 π ⋅ 0.1379 ) )
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Frequency Response Table
Syntax
Transconductance H(s):
Gxxx n+ n- FREQ in+ inf1, a1, φ1, ..., fi, ai, φ1
+ <DELF=val> <MAXF=val> <SCALE=val> <TC1=val>
+ <TC2=val> <M=val> <LEVEL=val> <ACCURACY=val>
Voltage Gain H(s):
Exxx n+ n- FREQ in+ inf1, a1, φ1, ..., fi, ai, φ1
+ <DELF=val> <MAXF=val> <SCALE=val> <TC1=val>
+ <TC2=val> <LEVEL=val> <ACCURACY=val>
■
Each fi is a frequency point, in hertz.
■
ai is the magnitude, in dB.
■
φ1 is the phase, in degrees.
At each frequency, HSPICE or HSPICE RF uses interpolation to calculate the
network response, magnitude, and phase. HSPICE or HSPICE RF interpolates
the magnitude (in dB) logarithmically, as a function of frequency. It also
interpolates the phase (in degrees) linearly, as a function of frequency.
ai – ak
H ( j2 π f ) =  ----------------------------- ( log f – log f i ) + a i
 log f i – log f k
φi – φk
∠H ( j2 π f ) =  --------------- ( f – f i ) + φ i
 fi – fk 
Example
Eftable output
+ 1.0k
-3.97m
+ 2.0k
-2.00m
+ 3.0k
17.80m
+ .........
+ 10.0k -53.20
0 FREQ input
293.7
211.0
82.45
0
-1125.5
■
The first column is frequency, in hertz.
■
The second column is magnitude, in dB.
■
The third column is phase, in degrees.
Set the LEVEL to 1 for a high-pass filter.
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Set the last frequency point to the highest frequency response value that is a
real number, with zero phase.
You can use parameters to set the frequency, magnitude, and phase, in the
table.
Behavioral Voltage Source
Syntax
Exxx n+ n- VOL=’equation’ <MAX=val> <MIN=val>
Ideal Op-Amp
Syntax
Exxx n+ n- OPAMP in+ inYou can also substitute Level=1 in place of OPAMP:
Exxx n+ n- in+ in- level=1
Ideal Transformer
Syntax
Exxx n+ n- TRANSFORMER in+ in- k
You can also substitute Level=2 in place of TRANSFORMER:
Exxx n+ n- in+ in- level=2 k
Parameter
Description
ABS
Output is an absolute value, if ABS=1.
DELAY
Keyword for the delay element. Same as for the voltage-controlled
voltage source, except it has an associated propagation delay, TD.
This element adjusts propagation delay in macro (subcircuit)
modeling.
DELAY is a reserved word; do not use it as a node name.
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Parameter
Description
DELTA
Controls the curvature of the piecewise linear corners. This parameter
defaults to one-fourth of the smallest distance between breakpoints.
The maximum is one-half of the smallest distance between
breakpoints.
Exxx
Voltage-controlled element name. Must begin with E, followed by up to
1023 alphanumeric characters.
gain
Voltage gain.
gatetype(k)
Can be AND, NAND, OR, or NOR.
k represents the number of inputs of the gate.
x and y represent the piecewise linear variation of output, as a function
of input. In multi-input gates, only one input determines the state of the
output.
IC
Initial condition: initial estimate of controlling voltage value(s). If you do
not specify IC, default=0.0.
in +/-
Positive or negative controlling nodes. Specify one pair for each
dimension.
k
Ideal transformer turn ratio: V(in+,in-) = k ⋅ V(n+,n-)
or, number of gates input.
MAX
Maximum output voltage value. The default is undefined, and sets no
maximum value.
MIN
Minimum output voltage value. The default is undefined, and sets no
minimum value.
n+/-
Positive or negative node of a controlled element.
NDIM
Number of polynomial dimensions. If you do not set POLY(NDIM),
HSPICE or HSPICE RF assumes a one-dimensional polynomial.
NDIM must be a positive number.
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Parameter
Description
NPDELAY
Sets the number of data points to use in delay simulations. The default
value is the larger of either 10, or the smaller of TD/tstep and tstop/
min 〈 TD, tstop〉
tstep. That is, NPDELAY default = max ---------------------------------------, 10
tstep
The .TRAN statement specifies tstep and tstop values.
OPAMP
or Level=1
The keyword for an ideal op-amp element. OPAMP is a HSPICE
reserved word; do not use it as a node name.
P0, P1 …
The polynomial coefficients.
If you specify one coefficient, HSPICE or HSPICE RF assumes that it
is P1 (P0=0.0), and that the element is linear.
If you specify more than one polynomial coefficient, the element is
nonlinear, and P0, P1, P2 ... represent them (see Polynomial
Functions on page 164).
POLY
Keyword for the polynomial function. If you do not specify
POLY(ndim), HSPICE assumes a one-dimensional polynomial.
Ndim must be a positive number.
PWL
Keyword for the piecewise linear function.
SCALE
Multiplier for the element value.
TC1,TC2
First-order and second-order temperature coefficients. Temperature
changes update the SCALE:
SCALEeff = SCALE ⋅ ( 1 + TC1 ⋅ ∆ t + TC2 ⋅ ∆ t 2 )
TD
Keyword for the time (propagation) delay.
TRANSFORM Keyword for an ideal transformer. TRANSFORMER is a reserved
ER
word; do not use it as a node name.
or Level=2
VCVS
178
Keyword for a voltage-controlled voltage source. VCVS is a reserved
word; do not use it as a node name.
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Parameter
Description
x1,...
Controlling voltage across the in+ and in- nodes. The x values must be
in increasing order.
y1,...
Corresponding element values of x.
Figure 23
Equivalent VCVS and Ideal Transformer HSPICE Models
VCVS (op-amp) with Gain = g
+
V2
V1
Equivalent HSPICE model
<=>
+
-
V1
V2
V2=g*V2
Ideal transformer with ratio K
I1
k:1
..
V1
Equivalent HSPICE model
I2
I1
I2
V2
<=>
V1
I1=k*I2
+
-
V2
V1=k*V2
E Element Examples
Ideal OpAmp
You can use the voltage-controlled voltage source to build a voltage amplifier,
with supply limits.
■
The output voltage across nodes 2,3 is v(14,1) * 2.
■
The value of the voltage gain parameter is 2.
■
The MAX parameter sets a maximum E1 voltage of 5 V.
■
The MIN parameter sets a minimum E1 voltage output of -5 V.
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Example
If V(14,1) = -4V, then HSPICE or HSPICE RF sets E1 to -5V, and not -8V as the
equation suggests.
Eopamp 2 3 14 1 MAX=+5 MIN=-5 2.0
To specify a value for polynomial coefficient parameters, use the following
format:
.PARAM CU = 2.0
E1 2 3 14 1 MAX=+5 MIN=-5 CU
Voltage Summer
An ideal voltage summer specifies the source voltage, as a function of three
controlling voltage(s):
■
V(13,0)
■
V(15,0)
■
V(17,0)
To describe a voltage source, the voltage summer uses this value:
V (13,0) + V (15,0) + V (17,0)
This example represents an ideal voltage summer. It initializes the three
controlling voltages for a DC operating point analysis, to 1.5, 2.0, and 17.25 V.
EX 17 0 POLY(3) 13 0 15 0 17 0 0 1 1 1 IC=1.5,2.0,17.25
Polynomial Function
A voltage-controlled source can also output a non-linear function, using a onedimensional polynomial. This example does not specify the POLY parameter,
so HSPICE or HSPICE RF assumes it is a one-dimensional polynomial—that
is, a function of one controlling voltage. The equation corresponds to the
element syntax. Behavioral equations replace this older method.
V (3,4) = 10.5 + 2.1 *V(21,17) + 1.75 *V(21,17)2”
E2 3 4 POLY 21 17 10.5 2.1 1.75
E2 3 4 VOLT = “10.5 + 2.1 *V(21,17) + 1.75 *V(21,17)2”
E2 3 4 POLY 21 17 10.5 2.1 1.75
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Zero-Delay Inverter Gate
Use a piecewise linear transfer function to build a simple inverter, with no delay.
Einv out 0 PWL(1) in 0 .7v,5v 1v,0v
Ideal Transformer
If the turn ratio is 10 to 1, the voltage relationship is V(out)=V(in)/10.
Etrans out 0 TRANSFORMER in 0 10
You can also substitute Level=2 in place of TRANSFORMER:
Etrans out 0 in 0 level=2 10
Voltage-Controlled Oscillator (VCO)
The VOL keyword defines a single-ended input, which controls output of a
VCO.
In the following example, the voltage at the control node controls the frequency
of the sinusoidal output voltage at the out node. v0 is the DC offset voltage, and
gain is the amplitude. The output is a sinusoidal voltage, whose frequency is
specified in freq · control.
Evco out 0
+ VOL=’v0+gain*SIN(6.28 freq*v(control)*TIME)’
Note: This equation is valid only for a steady-state VCO (fixed voltage). If you
sweep the control voltage, this equation does not apply.
Using the E Element for AC Analysis
The following equation describes an E Element:
E1 ee 0 vol = f(v(1), v(2))
In an AC analysis, the voltage is computed as follows:
v(ee) = A * delta_v1 + B * delta_v2
where:
■
A is the derivative of f(v(1), v(2)) to v(1) at the operating point
■
B is the derivative of f(v(1), v(2)) to v(2) at the operating point
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■
delta_v1 is the AC voltage variation of v(1)
■
delta_v2 is the AC voltage variation of v(2)
Example
You can find the sample netlist for this example in the following directory:
$installdir/demo/hspice/sources/eelm.sp
The AC voltage of node n3 is:
v(n3) = 1.0 *v(n1)(ac) + 1.0 * v(n2)(ac)
= 1.0 * 5.0 + 1.0 * 2.0
= 7.0 (v)
The AC voltage of node n4 is:
v(n4) = v(n2)(op) * v(n1)(ac) + v(n1)(op) * v(n2)(ac)
= 4.0 * 5.0 + 6.0 * 2.0
= 32.0 (v)
Current-Dependent Current Sources — F Elements
This section explains the F element syntax and parameters.
Current-Controlled Current Source (CCCS) Syntax
Linear
Fxxx n+ n- <CCCS> vn1 gain <MAX=val> <MIN=val> <SCALE=val>
+ <TC1=val> <TC2=val> <M=val> <ABS=1> <IC=val>
Polynomial (POLY)
Fxxx n+ n- <CCCS> POLY(ndim) vn1 <... vnndim> <MAX=val>
+ <MIN=val> <TC1=val> <TC2=val> <SCALE=val> <M=val>
+ <ABS=1> p0 <p1…> <IC=val>
In this syntax, dim (dimensions)< 3.
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Piecewise Linear (PWL)
Fxxx n+ n- <CCCS> PWL(1) vn1 <DELTA=val>
+ <SCALE=val><TC1=val> <TC2=val> <M=val>
+ x1,y1 ... x100,y100 <IC=val>
Multi-Input Gates
Fxxx n+ n- <CCCS> gatetype(k) vn1, ... vnk <DELTA=val>
+ <SCALE=val> <TC1=val> <TC2=val> <M=val> <ABS=1>
+ x1,y1 ...
x100,y100 <IC=val>
In this syntax, gatetype(k) can be AND, NAND, OR, or NOR gates.
Delay Element
Fxxx n+ n- <CCCS> DELAY vn1 TD=val <SCALE=val>
+ <TC1=val><TC2=val> NPDELAY=val
Note: G Elements with algebraics make F Elements obsolete. You can still use
F Elements for backward-compatibility with existing designs.
Parameter
Description
ABS
Output is an absolute value, if ABS=1.
CCCS
Keyword for current-controlled current source. CCCS is a HSPICE
reserved keyword; do not use it as a node name.
DELAY
Keyword for the delay element. Same as for a current-controlled current
source, but has an associated propagation delay, TD. Adjusts the
propagation delay in the macro model (subcircuit) process. DELAY is a
reserved word; do not use it as a node name.
DELTA
Controls the curvature of piecewise linear corners. The default is 1/4 of
the smallest distance between breakpoints. The maximum is 1/2 of the
smallest distance between breakpoints.
Fxxx
Element name of the current-controlled current source. Must begin with
F, followed by up to 1023 alphanumeric characters.
gain
Current gain.
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Parameter
Description
gatetype(k)
AND, NAND, OR, or NOR. k is the number of inputs for the gate. x and
y are the piecewise linear variation of the output, as a function of input.
In multi-input gates, only one input determines the output state. Do not
use the above keywords as node names.
IC
Initial condition (estimate) of the controlling current(s), in amps. If you
do not specify IC, the default=0.0.
M
Number of replications of the element, in parallel.
MAX
Maximum output current. Default=undefined; sets no maximum.
MIN
Minimum output current. Default=undefined; sets no minimum.
n+/-
Connecting nodes for a positive or negative controlled source.
NDIM
Number of polynomial dimensions. If you do not specify POLY(NDIM),
HSPICE or HSPICE RF assumes a one-dimensional polynomial. NDIM
must be a positive number.
NPDELAY
Number of data points to use in delay simulations. The default value is
the larger of either 10, or the smaller of TD/tstep and tstop/tstep. That
min 〈 TD, tstop〉
is, NPDELAY default = max ---------------------------------------, 10
tstep
The .TRAN statement specifies the tstep and tstop values.
P0, P1 …
The polynomial coefficients.
If you specify one coefficient, HSPICE or HSPICE RF assumes it is P1
(P0=0.0), and the source element is linear.
If you specify more than one polynomial coefficient, then the source is
non-linear, and HSPICE or HSPICE RF assumes that the polynomials
are P0, P1, P2 … See Polynomial Functions on page 164.
184
POLY
Keyword for the polynomial function. If you do not specify POLY(ndim),
HSPICE assumes that this is a one-dimensional polynomial. Ndim must
be a positive number.
PWL
Keyword for the piecewise linear function.
SCALE
Multiplier for the element value.
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Parameter
Description
TC1,TC2
First-order and second-order temperature coefficients. Temperature
changes update the
SCALE: SCALEeff = SCALE ⋅ ( 1 + TC1 ⋅ ∆ t + TC2 ⋅ ∆ t 2 )
TD
Keyword for the time (propagation) delay.
vn1 …
Names of voltage sources, through which the controlling current flows.
Specify one name for each dimension.
x1,...
Controlling current, through the vn1 source. Specify the x values in
increasing order.
y1,...
Corresponding output current values of x.
Example 1
F1 13 5 VSENS MAX=+3 MIN=-3 5
Example 1 describes a current-controlled current source, connected between
nodes 13 and 5. The current, which controls the value of the controlled source,
flows through the voltage source named VSENS.
Note: To use a current-controlled current source, you can place a dummy
independent voltage source into the path of the controlling current.
The defining equation is:
I ( F1 ) = 5 ⋅ I ( VSENS )
■
Current gain is 5.
■
Maximum current flow through F1 is 3 A.
■
Minimum current flow is -3 A.
If I(VSENS) = 2 A, then this examples sets I(F1) to 3 amps, not 10 amps (as the
equation suggests). You can define a parameter for the polynomial
coefficient(s):
.PARAM VU = 5
F1 13 5 VSENS MAX=+3 MIN=-3 VU
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Example 2
F2 12 10 POLY VCC 1MA 1.3M
Example 2 is a current-controlled current source, with the value:
I(F2)=1e-3 + 1.3e-3 ⋅ I(VCC)
Current flows from the positive node, through the source, to the negative node.
The positive controlling-current flows from the positive node, through the
source, to the negative node of vnam (linear), or to the negative node of each
voltage source (nonlinear).
Example 3
Fd 1 0 DELAY vin TD=7ns SCALE=5
Example 3 is a delayed, current-controlled current source.
Example 4
Filim 0 out PWL(1) vsrc -1a,-1a 1a,1a
Example 4 is a piecewise-linear, current-controlled current source.
Voltage-Dependent Current Sources — G Elements
This section explains G element syntax statements, and their parameters.
■
Level=0 is a Voltage-Controlled Current Source (VCCS).
■
Level=1 is a Voltage-Controlled Resistor (VCR).
■
Level=2 is a Voltage-Controlled Capacitor (VCCAP), Negative Piece-Wise
Linear (NPWL).
■
Level=3 is a VCCAP, Positive Piece-Wise Linear (PPWL).
See also “Using G and E Elements” in the HSPICE Applications Manual.
Voltage-Controlled Current Source (VCCS)
The Level=0 syntax is:
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Linear
Gxxx n+ n- <VCCS> in+ in- transconductance <MAX=val>
+ <MIN=val> <SCALE=val> <M=val> <TC1=val> <TC2=val>
+ <ABS=1> <IC=val>
Polynomial (POLY)
Gxxx n+ n- <VCCS> POLY(NDIM) in1+ in1- ... <inndim+ inndim->
+ <MAX=val> <MIN=val> <SCALE=val> <M=val> <TC1=val>
+ <TC2=val> <ABS=1> P0<P1…> <IC=vals>
Piecewise Linear (PWL)
Gxxx n+ n- <VCCS> PWL(1) in+ in- <DELTA=val>
+ <SCALE=val> <M=val> <TC1=val> <TC2=val>
+ x1,y1 x2,y2 ... x100,y100 <IC=val> <SMOOTH=val>
Gxxx n+ n- <VCCS> NPWL(1) in+ in- <DELTA=val>
+ <SCALE=val> <M=val> <TC1=val><TC2=val>
+ x1,y1 x2,y2 ... x100,y100 <IC=val> <SMOOTH=val>
Gxxx n+ n- <VCCS> PPWL(1) in+ in- <DELTA=val>
+ <SCALE=val> <M=val> <TC1=val> <TC2=val>
+ x1,y1 x2,y2 ... x100,y100 <IC=val> <SMOOTH=val>
Multi-Input Gate
Gxxx n+ n- <VCCS> gatetype(k) in1+ in1- ...
+ ink+ ink- <DELTA=val> <TC1=val> <TC2=val> <SCALE=val>
+ <M=val> x1,y1 ... x100,y100<IC=val>
In this syntax, gatetype(k) can be AND, NAND, OR, or NOR gates.
Delay Element
Gxxx n+ n- <VCCS> DELAY in+ in- TD=val <SCALE=val>
+ <TC1=val> <TC2=val> NPDELAY=val
Laplace Transform
For details, see Laplace Transform on page 173.
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Pole-Zero Function
For details, see Pole-Zero Function on page 174.
Frequency Response Table
For details, see Frequency Response Table on page 175.
Behavioral Current Source (Noise Model) Syntax
Gxxx n+ n- CUR=’equation’ <MAX>=val> <MIN=val> <M=val>
+ <SCALE=val>
* correlated noise source
gname node1 node2 noise=’noise_equation’
This syntax creates a simple two-terminal current noise source, whose value is
described in A/sqrt(Hz). The output noise generated from this noise source is:
noise_equation*H
H is the transfer function from the terminal pair (node1,node2) to the circuit
output, where the output noise is measured.
* correlated noise source
gname node1 node2 node3 node4 noise=’noise_equation’
This syntax produces a noise source correlation between the terminal pairs
(node1 node2) and (node3 node4). The resulting output noise is computed
as:
noise_equation*sqrt(H1*H2*)
■
H1 is the transfer function from (node1,node2) to the output.
■
H2 is the transfer function from (node3,node4) to the output.
The noise_equation expression can involve node voltages and currents through
voltage sources.
Voltage-Controlled Resistor (VCR)
Linear
Gxxx n+ n- VCR in+ in- transfactor <MAX=val> <MIN=val>
+ <SCALE=val> <M=val> <TC1=val> <TC2=val> <IC=val>
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Polynomial (POLY)
Gxxx n+ n- VCR POLY(NDIM) in1+ in1- ...
+ <inndim+ inndim-> <MAX=val> <MIN=val><SCALE=val>
+ <M=val> <TC1=val> <TC2=val>
P0 <P1…> <IC=vals>
Piecewise Linear (PWL)
Gxxx n+ n- VCR PWL(1) in+ in- <DELTA=val> <SCALE=val>
+ <M=val> <TC1=val> <TC2=val> x1,y1 x2,y2 ... x100,y100
+ <IC=val> <SMOOTH=val>
Gxxx n+ n- VCR NPWL(1) in+ in- <DELTA=val> <SCALE=val>
+ <M=val> <TC1=val> <TC2=val> x1,y1 x2,y2 ... x100,y100
+ <IC=val> <SMOOTH=val>
Gxxx n+ n- VCR PPWL(1) in+ in- <DELTA=val> <SCALE=val>
+ <M=val> <TC1=val> <TC2=val> x1,y1 x2,y2 ... x100,y100
+ <IC=val> <SMOOTH=val>
Multi-Input Gates
Gxxx n+ n- VCR gatetype(k) in1+ in1- ... ink+ ink+ <DELTA=val> <TC1=val> <TC2=val> <SCALE=val> <M=val>
+ x1,y1 ... x100,y100 <IC=val>
Voltage-Controlled Capacitor (VCCAP)
Level=2 (NPWL) and Level=3 (PPWL) piecewise linear syntax is:
Gxxx n+ n- VCCAP PWL(1) in+ in<DELTA=val>
+ <SCALE=val> <M=val> <TC1=val> <TC2=val>
+ x1,y1 x2,y2 ... x100,y100 <IC=val> <SMOOTH=val>
HSPICE or HSPICE RF uses either Level=2 (NPWL) or Level=3 (PPWL),
based on the relationship of the (n+, n-) and (in+, in-) nodes.
Use the NPWL and PPWL functions to interchange the n+ and n- nodes, but
use the same transfer function. The following summarizes this action:
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NPWL Function
For the in- node connected to n+:
■
If v(n+,n-) < 0, then the controlling voltage is v(in+,in-).
■
Otherwise, the controlling voltage is v(in+,n-).
For the in- node connected to n-:
■
If v(n+,n-) > 0, then the controlling voltage is v(in+,in-).
■
Otherwise, the controlling voltage is v(in+,n+).
PPWL Function
For the in- node, connected to n+:
■
If v(n+,n-) > 0, then the controlling voltage is v(in+,in-).
■
Otherwise, the controlling voltage is v(in+,n-).
For the in- node, connected to n-:
■
If v(n+,n-) < 0, then the controlling voltage is v(in+,in-).
■
Otherwise, the controlling voltage is v(in+,n+).
If the in- node does not connect to either n+ or n-, then HSPICE or HSPICE RF
changes NPWL and PPWL to PWL.
Parameter
Description
ABS
Output is an absolute value, if ABS=1.
CUR, VALUE
Current output that flows from n+ to n-. The equation that you define
can be a function of:
•
•
•
•
•
DELAY
190
node voltages
branch currents
time (time variable)
temperature (temper variable)
frequency (hertz variable)
Keyword for the delay element. Same as in the voltage-controlled
current source, but has an associated propagation delay, TD.
Adjusts propagation delay in macro (subcircuit) modeling. DELAY
is a keyword; do not use it as a node name.
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Parameter
Description
DELTA
Controls curvature of piecewise linear corners. Defaults to
1/4 of the smallest distance between breakpoints. Maximum is 1/2
of the smallest distance between breakpoints.
Gxxx
Name of the voltage-controlled element. Must begin with G,
followed by up to 1023 alphanumeric characters.
gatetype(k)
AND, NAND, OR, or NOR. The k parameter is the number of inputs
of the gate. x and y represent the piecewise linear variation of the
output, as a function of the input. In multi-input gates, only one input
determines the state of the output.
IC
Initial condition. Initial estimate of the value(s) of controlling
voltage(s). If you do not specify IC, the default=0.0.
in +/-
Positive or negative controlling nodes. Specify one pair for each
dimension.
M
Number of replications of the elements in parallel.
MAX
Maximum value of the current or resistance. The default is
undefined, and sets no maximum value.
MIN
Minimum value of the current or resistance. The default is
undefined, and sets no minimum value.
n+/-
Positive or negative node of the controlled element.
NDIM
Number of polynomial dimensions. If you do not specify
POLY(NDIM), HSPICE assumes a one-dimensional polynomial.
NDIM must be a positive number.
NPDELAY
Sets the number of data points to use in delay simulations. The
default value is the larger of either 10, or the smaller of TD/tstep and
tstop/tstep. That is,
min 〈 TD, tstop〉
NPDELAY default = max ---------------------------------------, 10 .
tstep
The .TRAN statement specifies the tstep and tstop values.
NPWL
Models symmetrical bidirectional switch/transfer gate, NMOS.
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Parameter
Description
P0, P1 …
The polynomial coefficients.
• If you specify one coefficient, HSPICE or HSPICE RF assumes
that it is P1 (P0=0.0), and the element is linear.
• If you specify more than one polynomial coefficient, the element
is non-linear, and the coefficients are P0, P1, P2 ... (see
Polynomial Functions on page 164).
POLY
Keyword for the polynomial dimension function. If you do not
specify POLY(ndim), HSPICE assumes that it is a one-dimensional
polynomial. Ndim must be a positive number.
PWL
Keyword for the piecewise linear function.
PPWL
Models symmetrical bidirectional switch/transfer gate, PMOS.
SCALE
Multiplier for the element value.
SMOOTH
For piecewise-linear, dependent-source elements, SMOOTH
selects the curve-smoothing method.
A curve-smoothing method simulates exact data points that you
provide. You can use this method to make HSPICE or HSPICE RF
simulate specific data points, which correspond to either measured
data or data sheets.
Choices for SMOOTH are 1 or 2:
• Selects the smoothing method used in Hspice versions before
release H93A. Use this method to maintain compatibility with
simulations that you ran, using releases older than H93A.
• Selects the smoothing method, which uses data points that you
provide. This is the default for Hspice versions starting with
release H93A.
TC1,TC2
First-order and second-order temperature coefficients.
Temperature changes update the
SCALE: SCALEeff = SCALE ⋅ ( 1 + TC1 ⋅ ∆ t + TC2 ⋅ ∆ t 2 ) .
TD
Keyword for the time (propagation) delay.
transconductance Voltage-to-current conversion factor.
transfactor
192
Voltage-to-resistance conversion factor.
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Parameter
Description
VCCAP
Keyword for voltage-controlled capacitance element. VCCAP is a
reserved HSPICE keyword; do not use it as a node name.
VCCS
Keyword for the voltage-controlled current source. VCCS is a
reserved HSPICE keyword; do not use it as a node name.
VCR
Keyword for the voltage controlled resistor element. VCR is a
reserved HSPICE keyword; do not use it as a node name.
x1,...
Controlling voltage, across the in+ and in- nodes. Specify the
x values in increasing order.
y1,...
Corresponding element values of x.
G Element Examples
Switch
A voltage-controlled resistor represents a basic switch characteristic. The
resistance between nodes 2 and 0 varies linearly, from 10 meg to 1 m ohms,
when voltage across nodes 1 and 0 varies between 0 and 1 volt. The
resistance remains at 10 meg when below the lower voltage limit, and at 1 m
ohms when above the upper voltage limit.
Gswitch 2 0 VCR PWL(1) 1 0 0v,10meg 1v,1m
Switch-Level MOSFET
To model a switch level n-channel MOSFET, use the N-piecewise linear
resistance switch. The resistance value does not change when you switch the d
and s node positions.
Gnmos d s VCR NPWL(1) g s LEVEL=1 0.4v,150g
+ 1v,10meg 2v,50k 3v,4k 5v,2k
Voltage-Controlled Capacitor
The capacitance value across the (out,0) nodes varies linearly (from 1 p to 5 p),
when voltage across the ctrl,0 nodes varies between 2 v and 2.5 v. The
capacitance value remains constant at 1 picofarad when below the lower
voltage limit, and at 5 picofarads when above the upper voltage limit.
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Gcap out 0 VCCAP PWL(1) ctrl 0 2v,1p 2.5v,5p
Zero-Delay Gate
To implement a two-input AND gate, use an expression and a piecewise linear
table.
■
The inputs are voltages at the a and b nodes.
■
The output is the current flow from the out to 0 node.
■
HSPICE or HSPICE RF multiplies the current by the SCALE value—which
in this example, is the inverse of the load resistance, connected across the
out,0 nodes.
Gand out 0 AND(2) a 0 b 0 SCALE=’1/rload’ 0v,0a 1v,.5a
+ 4v,4.5a 5v,5a
Delay Element
A delay is a low-pass filter type delay, similar to that of an opamp. In contrast, a
transmission line has an infinite frequency response. A glitch input to a G delay
attenuates in a way that is similar to a buffer circuit. In this example, the output
of the delay element is the current flow, from the out node to the 1 node, with a
value equal to the voltage across the (in, 0) nodes, multiplied by the SCALE
value, and delayed by the TD value.
Gdel out 0 DELAY in 0 TD=5ns SCALE=2 NPDELAY=25
Diode Equation
To model forward-bias diode characteristics, from node 5 to ground, use a
runtime expression. The saturation current is 1e-14 amp, and the thermal
voltage is 0.025 v.
Gdio 5 0 CUR=’1e-14*(EXP(V(5)/0.025)-1.0)’
Diode Breakdown
You can model the diode breakdown region to a forward region. When voltage
across a diode is above or below the piecewise linear limit values (-2.2v, 2v),
the diode current remains at the corresponding limit values (-1a, 1.2a).
Gdiode 1 0 PWL(1) 1 0 -2.2v,-1a -2v,-1pa .3v,.15pa
+.6v,10ua 1v,1a 2v,1.2a
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Triodes
Both of the following voltage-controlled current sources implement a basic
triode.
■
The first example uses the poly(2) operator, to multiply the anode and grid
voltages together, and to scale by .02.
■
The second example uses the explicit behavioral algebraic description.
gt i_anode cathode poly(2) anode,cathode
+ grid,cathode 0 0 0 0 .02
gt i_anode cathode
+ cur=’20m*v(anode,cathode)*v(grid,cathode)’
Behavioral Noise Model
The following netlist shows a 1000 Ohm resistor (g1) implemented using a G
element. The g1noise element, placed in parallel with the g1 resistor, delivers
the thermal noise expected from a resistor. The r1 resistor is included for
comparison: the noise due to r1 should be the same as the noise due to
g1noise.
* Resistor implemented using g-element
v1 1 0 1
r1 1 2 1k
g1 1 2 cur='v(1,2)*0.001'
g1noise 1 2 noise='sqrt(4*1.3806266e-23*(TEMPER+273.15)*0.001)'
rout 2 0 1meg
.ac lin 1 100 100
.noise v(2) v1 1
.end
Current-Dependent Voltage Sources — H Elements
This section explains H element syntax statements, and defines their
parameters.
Current-Controlled Voltage Source (CCVS)
Linear
Hxxx n+ n- <CCVS> vn1 transresistance <MAX=val> <MIN=val>
+ <SCALE=val> <TC1=val><TC2=val> <ABS=1> <IC=val>
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Polynomial (POLY)
Hxxx n+ n- <CCVS> POLY(NDIM) vn1 <... vnndim>
+ <MAX=val><MIN=val> <TC1=val> <TC2=val> <SCALE=val>
+ <ABS=1> P0 <P1…> <IC=val>
Piecewise Linear (PWL)
Hxxx n+ n- <CCVS> PWL(1) vn1 <DELTA=val> <SCALE=val>
+ <TC1=val> <TC2=val> x1,y1 ...
x100,y100 <IC=val>
Multi-Input Gate
Hxxx n+ n- gatetype(k) vn1, ...vnk <DELTA=val> <SCALE=val>
+ <TC1=val> <TC2=val> x1,y1 ...
x100,y100 <IC=val>
In this syntax, gatetype(k) can be AND, NAND, OR, or NOR gates.
Delay Element
Hxxx n+ n- <CCVS> DELAY vn1 TD=val <SCALE=val> <TC1=val>
+ <TC2=val> <NPDELAY=val>
Note: E Elements with algebraics make CCVS elements obsolete. You can still
use CCVS elements for backward-compatibility with existing designs.
196
Parameter
Description
ABS
Output is an absolute value, if ABS=1.
CCVS
Keyword for the current-controlled voltage source. CCVS is a
HSPICE reserved keyword; do not use it as a node name.
DELAY
Keyword for the delay element. Same as for a current-controlled
voltage source, but has an associated propagation delay, TD. Use
this element to adjust the propagation delay in the macro
(subcircuit) model process. DELAY is a HSPICE reserved keyword;
do not use it as a node name.
DELTA
Controls curvature of piecewise linear corners. The default is 1/4 of
the smallest distance between breakpoints. Maximum is 1/2 of the
smallest distance between breakpoints.
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Parameter
Description
gatetype(k)
Can be AND, NAND, OR, or NOR. The k value is the number of
inputs of the gate. The x and y terms are the piecewise linear
variation of the output, as a function of the input. In multi-input
gates, one input determines the output state.
Hxxx
Element name of current-controlled voltage source. Must start with
H, followed by up to 1023 alphanumeric characters.
IC
Initial condition (estimate) of the controlling current(s), in amps. If
you do not specify IC, the default=0.0.
MAX
Maximum voltage. Default is undefined; sets no maximum.
MIN
Minimum voltage. Default is undefined; sets no minimum.
n+/-
Connecting nodes for positive or negative controlled source.
NDIM
Number of polynomial dimensions. If you do not specify
POLY(NDIM), HSPICE or HSPICE RF assumes a one-dimensional
polynomial. NDIM must be a positive number.
NPDELAY
Number of data points to use in delay simulations. The default value
is the larger of either 10, or the smaller of TD/tstep and tstop/tstep.
min 〈 TD, tstop〉
That is: NPDELAY default = max ---------------------------------------, 10 .
tstep
The .TRAN statement specifies the tstep and tstop values.
P0, P1 . . .
Polynomial coefficients.
• If you specify one polynomial coefficient, the source is linear, and
HSPICE or HSPICE RF assumes that the polynomial is P1
(P0=0.0).
• If you specify more than one polynomial coefficient, the source is
non-linear. HSPICE assumes the polynomials are P0, P1, P2 …
See Polynomial Functions on page 164.
POLY
Keyword for polynomial dimension function. If you do not specify
POLY(ndim), HSPICE assumes a one-dimensional polynomial.
Ndim must be a positive number.
PWL
Keyword for a piecewise linear function.
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Parameter
Description
SCALE
Multiplier for the element value.
TC1,TC2
First-order and second-order temperature coefficients. Temperature
changes update the SCALE:
SCALEeff = SCALE ⋅ ( 1 + TC1 ⋅ ∆ t + TC2 ⋅ ∆ t 2 )
TD
Keyword for the time (propagation) delay.
transresistance
Current-to-voltage conversion factor.
vn1 …
Names of voltage sources, through which controlling current flows.
You must specify one name for each dimension.
x1,...
Controlling current, through the vn1 source. Specify the x values in
increasing order.
y1,...
Corresponding output voltage values of x.
H Element Examples
HX 20 10 VCUR MAX=+10 MIN=-10 1000
The example above selects a linear current-controlled voltage source. The
controlling current flows through the dependent voltage source, called VCUR.
Example
The defining equation of the CCVS is:
HX = 1000 ⋅ I ( VCUR )
The defining equation specifies that the voltage output of HX is 1000 times the
value of the current flowing through VCUR.
■
If the equation produces a value of HX greater than +10 V, then the MAX=
parameter sets HX to 10 V.
■
If the equation produces a value of HX less than -10 V, then the MIN=
parameter sets HX to -10 V.
VCUR is the name of the independent voltage source, through which the
controlling current flows. If the controlling current does not flow through an
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independent voltage source, you must insert a dummy independent voltage
source.
Example
.PARAM CT=1000
HX 20 10 VCUR MAX=+10 MIN=-10 CT
HXY 13 20 POLY(2) VIN1 VIN2 0 0 0 0 1 IC=0.5, 1.3
The example above describes a dependent voltage source, with the value:
V = I ( VIN1 ) ⋅ I ( VIN2 )
This two-dimensional polynomial equation specifies:
■
FA1=VIN1
■
FA2=VIN2
■
P0=0
■
P1=0
■
P2=0
■
P3=0
■
P4=1
The initial controlling current is .5 mA through VIN1, and 1.3 mA for VIN2.
Positive controlling current flows from the positive node, through the source, to
the negative node of vnam (linear). The (non-linear) polynomial specifies the
source voltage, as a function of the controlling current(s).
Digital and Mixed Mode Stimuli
HSPICE input netlists support two types of digital stimuli:
■
U element digital input files (HSPICE only).
■
Vector input files (HSPICE or HSPICE RF).
This section describes both types.
U Element Digital Input Elements and Models
This section describes the input file format for a U Element. For a description of
the U Element, see the HSPICE Signal Integrity Guide.
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In HSPICE (but not in HSPICE RF), the U Element can reference digital input
and digital output models for mixed-mode simulation. If you run HSPICE in
standalone mode, the state information originates from a digital file. Digital
outputs are handled in a similar fashion. In digital input file mode, the input file
is named <design>.d2a, and the output file is named <design>.a2d.
A2D and D2A functions accept the terminal “\” backslash character as a linecontinuation character, to allow more than 255 characters in a line. Use line
continuation if the first line of a digital file, which contains the signal name list, is
longer than the maximum line length that your text editor accepts.
Do not put a blank first line in a digital D2A file. If the first line of a digital file is
blank, HSPICE issues an error message.
Example
The following example demonstrates how to use the “\” line continuation
character, to format an input file for text editing. The example file contains a
signal list for a 64-bit bus.
...
a00
a08
...
a56
...
a01 a02 a03 a04 a05 a06 a07 \
a09 a10 a11 a12 a13 a14 a15 \
* Continuation of signal names
a57 a58 a59 a60 a61 a62 a63 End of signal names
Remainder of file
General Form
The general syntax for a U element digital source is:
Uxxx interface nlo nhi mname SIGNAME = sname IS = val
200
Parameter
Description
Uxxx
Digital input element name. Must begin with U, followed by up to 1023
alphanumeric characters.
interface
Interface node in the circuit, to which the digital input attaches.
nlo
Node connected to the low-level reference.
nhi
Node connected to the high-level reference.
mname
Digital input model reference (U model).
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SIGNAME=
sname
Signal name, as referenced in the digital output file header. Can be a
string of up to eight alphanumeric characters.
IS=val
Initial state of the input element. Must be a state that the model defines.
Model Syntax
.MODEL mname U LEVEL=5 <parameters...>
Digital input (not supported in HSPICE RF).
Digital-to-Analog Input Model Parameters
Table 13 Digital-to-Analog Parameters
Names (Alias)
Units
Default
Description
CLO
farad
0
Capacitance, to low-level node.
CHI
farad
0
Capacitance, to high-level node.
S0NAME
State 0 character abbreviation. A string of
up to four alphanumerical characters.
S0TSW
sec
State 0 switching time.
S0RLO
ohm
State 0 resistance, to low-level node.
S0RHI
ohm
State 0 resistance, to high-level node.
S1NAME
State 1 character abbreviation. A string of
up to four alphanumerical characters.
S1TSW
sec
State 1 switching time.
S1RLO
ohm
State 1 resistance, to low-level node.
S1RHI
ohm
State 1 resistance, to high-level node.
S19NAME
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State 19 character abbreviation. A string of
up to four alphanumerical characters.
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Table 13 Digital-to-Analog Parameters (Continued)
Names (Alias)
Units
Default
Description
S19TSW
sec
State 19 switching time.
S19RLO
ohm
State 19 resistance, to low-level node.
S19RHI
ohm
State 19 resistance, to high-level node.
TIMESTEP
sec
Step size for digital input files only.
To define up to 20 different states in the model definition, use the SnNAME,
SnTSW, SnRLO and SnRHI parameters, where n ranges from 0 to 19.
Figure 24 is the circuit representation of the element.
Figure 24
Digital-to-Analog Converter Element
RHI
Node to
Hi_ref
source
CHI
CLO
Node to
Low_ref
source
Interface
Node
RLO
Example
The following example shows how to use the U element and model, as a digital
input for a HSPICE netlist (you cannot use the U element in a HSPICE RF
netlist).
You can find the sample netlist for this example in the following directory:
$installdir/demo/hspice/sources/uelm.sp
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The associated digital input file is:
1
00
09
10
11
20
30
39
40
41
50
60
70
80
1:1
z:1
0:1
z:1
1:1
0:1
x:1
1:1
x:1
0:1
1:1
0:1
1:1
U Element Digital Outputs
The general syntax for a digital output in a HSPICE output (not supported in
HSPICE RF) is:
U<name> interface reference mname SIGNAME = sname
Parameter
Description
Uxxx
Digital output element name. Must begin with U, followed by up to 1023
alphanumeric characters.
interface
Interface node in the circuit, at which HSPICE measures the digital
output.
reference
Node to use as a reference for the output.
mname
Digital output model reference (U model).
SIGNAME=
sname
Signal name, as referenced in the digital output file header. A string of
up to eight alphanumeric characters.
Model Syntax
.MODEL mname U LEVEL=4 <parameters...>
Digital output (not supported in HSPICE RF).
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Analog-to-Digital Output Model Parameters
Table 14 Analog-to-Digital Parameters
Name (Alias)
Units
Default
Description
RLOAD
ohm
1/gmin
Output resistance.
CLOAD
farad
0
Output capacitance.
S0NAME
State 0 character abbreviation. A string of
up to four alphanumerical characters.
S0VLO
volt
State 0 low-level voltage.
S0VHI
volt
State 0 high-level voltage.
S1NAME
State 1 character abbreviation. A string of
up to four alphanumerical characters.
S1VLO
volt
State 1 low-level voltage.
S1VHI
volt
State 1 high-level voltage.
S19NAME
State 19 character abbreviation. A string of
up to four alphanumerical characters.
S19VLO
volt
State 19 low-level voltage.
S19VHI
volt
State 19 high-level voltage.
TIMESTEP
sec
TIMESCALE
1E-9
Step size for digital input file.
Scale factor for time.
To define up to 20 different states in the model definition, use the SnNAME,
SnVLO and SnVHI parameters, where n ranges from 0 to 19. Figure 25 shows
the circuit representation of the element.
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Figure 25
Analog-to-Digital Converter Element
Interface Node
CLOAD
RLOAD
Analog-to-Digital
state conversion by
U model (level=4)
Reference Node
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Replacing Sources With Digital Inputs
Figure 26
Digital File Signal Correspondence
Traditional voltage pulse sources ...
V1 carry-in gnd PWL(0NS,lo 1NS,hi 7.5NS,hi 8.5NS,lo 15NS lo R
V2 A[0] gnd PWL (0NS,hi 1NS,lo 15.0NS,lo 16.0NS,hi 30NS hi R
V3 A[1] gnd PWL (0NS,hi 1NS,lo 15.0NS,lo 16.0NS,hi 30NS hi R
V4 B[0] gnd PWL (0NS,hi 1NS,lo 30.0NS,lo 31.0NS,hi 60NS hi
V5 B[1] gnd PWL (0NS,hi 1NS,lo 30.0NS,lo 31.0NS,hi 60NS hi
... become D2A drivers ...
UC carry-in VLD2A VHD2A D2A SIGNAME=1 IS=0
UA[0] A[0] VLD2A VHD2A D2A SIGNAME=2 IS=1
UA[1] A[1] VLD2A VHD2A D2A SIGNAME=3 IS=1
UB[0] B[0] VLD2A VHD2A D2A SIGNAME=4 IS=1
UB[1] B[1] VLD2A VHD2A D2A SIGNAME=5 IS=1
... that get their input from
the Digital stimulus file ...
<designname>.d2a
Signalname list
Time (in model time units)
Statechange: Signal list
1 2 3 4 5
0 1:1 0:2 0:3 0:4 0:5
75 0:1
150 1:1 1:2 1:3
225 0:1
300 1:1 0:2 0:3 1:4 1:5
375 0:1
450 1:1 1:2 1:3
525 0:1
600 1:1 0:2 0:3 0:4 0:5
Example
The following is an example of replacing sources with digital inputs. The
pathname to this example is:
$installdir/demo/hspice/cchar/digin.sp
* EXAMPLE OF U-ELEMENT DIGITAL OUTPUT
.OPTION POST
VOUT carry_out GND PWL 0N 0V 10N 0V 11N 5V 19N 5V 20N 0V
+ 30N 0V 31N 5V 39N 5V 40N 0V
VREF REF GND DC 0.0V
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UCO carry_out REF A2D SIGNAME=12
R1 REF 0 1k
* DEFAULT DIGITAL OUTPUT MODEL (no "X" value)
.MODEL A2D U LEVEL=4 TIMESTEP=0.1NS TIMESCALE=1
+ S0NAME=0 S0VLO=-1 S0VHI= 2.7
+ S4NAME=1 S4VLO= 1.4 S4VHI=9.0
+ CLOAD=0.05pf
.TRAN 1N 500N
.END
The digital output file should look something like this:
12
0
105
197
305
397
0:1
1:1
0:1
1:1
0:1
■
12 represents the signal name
■
The first column is the time, in units of 0.1 nanoseconds.
■
The second column has the signal value:name pairs.
■
This file uses more columns to represent subsequent outputs.
For another example, see the file identified below and the plot in Figure 27.
$installdir/demo/hspice/cchar/tdgtl.sp
In this next example, a 2-bit MOS adder uses a digital input file. In the plot, the
a[0], a[1], b[0], b[1], and carry-in nodes all originate from a digital file
input similar to Figure 26 above. HSPICE or HSPICE RF outputs a digital file.
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Figure 27
Digital Stimulus File Input
Specifying a Digital Vector File
You can call a digital vector (VEC) file from an HSPICE netlist or from HSPICE
RF. A VEC file consists of three parts:
■
Vector Pattern Definition section
■
Waveform Characteristics section
■
Tabular Data section
To incorporate this information into your simulation, include the .VEC command
in your netlist.
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Commands in a Digital Vector File
For descriptions of all commands that you can use in a VEC file, see the
HSPICE Command Reference Manual.
Vector Patterns
The Vector Pattern Definition section defines the vectors, their names, sizes,
signal direction, sequence or order for each vector stimulus, and so on. A
RADIX line must occur first and the other lines can appear in any order in this
section. All keywords are case-insensitive.
Here is an example Vector Pattern Definition section:
; start of Vector Pattern Definition section
RADIX 1111 1111
VNAME A B C D E F G H
IO IIII IIII
TUNIT ns
These four lines are required and appear in the first lines of a VEC file:
■
RADIX defines eight single-bit vectors.
■
VNAME gives each vector a name.
■
IO determines which vectors are inputs, outputs, or bidirectional signals. In
this example, all eight are input signals.
■
TUNIT indicates that the time unit for the tabular data to follow is in units of
nanoseconds.
For additional information about these keywords, see Defining Tabular Data on
page 209.
Defining Tabular Data
Although the Tabular Data section generally appears last in a VEC file (after the
Vector Pattern and Waveform Characteristics definitions), this chapter
describes it first to introduce the definitions of a vector.
The Tabular Data section defines (in tabular format) the values of the signals at
specified times. Rows in the Tabular Data section must appear in chronological
order, because row placement carries sequential timing information. Its general
format is:
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time1 signal1_value1 signal2_value1 signal3_value1...
time2 signal1_value2 signal2_value2 signal3_value2...
time3 signal1_value3 signal2_value3 signal3_value3...
.
.
Where timex is the specified time, and signaln_valuen is the values of specific
signals at specific points in time. The set of values for a particular signal (over
all times) is a vector, which appears as a vertical column in the tabular data and
vector table. The set of all signal1_valuen constitutes one vector.
For example,
11.0 1000 1000
20.0 1100 1100
33.0 1010 1001
This example shows that:
■
At 11.0 time units, the value for the first and fifth vectors is 1.
■
At 20.0 time units, the first, second, fifth, and sixth vectors are 1.
■
At 33.0 time units, the first, third, fifth, and eighth vectors are 1.
Input Stimuli
HSPICE or HSPICE RF converts each input signal into a PWL (piecewise
linear) voltage source, and a series resistance. Table shows the legal states for
an input signal. Signal values can have any of these legal states.
Table 15 Legal States for an Input Signal
210
State
Description
0
Drive to ZERO (gnd). Resistance set to 0.
1
Drive to ONE (vdd). Resistance set to 0.
Z, z
Floating to HIGH IMPEDANCE. A TRIZ statement defines resistance
value.
X, x
Drive to ZERO (gnd). Resistance set to 0.
L
Resistive drive to ZERO (gnd). An OUT or OUTZ statement defines
resistance value.
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Table 15 Legal States for an Input Signal (Continued)
H
Resistive drive to ONE (vdd). An OUT or OUTZ statement defines
resistance value.
U, u
Drive to ZERO (gnd). Resistance set to 0.
Expected Output
HSPICE or HSPICE RF converts each output signal into a .DOUT statement in
the netlist. During simulation, HSPICE or HSPICE RF compares the actual
results with the expected output vector(s). If the states are different, an error
message appears. The legal states for expected outputs include the values
listed in Table 16.
Table 16 Legal States for an Output Signal
State
Description
0
Expect ZERO.
1
Expect ONE.
X, x
Don’t care.
U, u
Don’t care.
Z, z
Expect HIGH IMPEDANCE (don’t care). Simulation evaluates Z, z as
“don’t care”, because HSPICE or HSPICE RF cannot detect a high
impedance state.
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For example,
...
IO OOOO; start of tabular section data
11.0
20.0
30.0
35.0
1001
1100
1000
xx00
Where:
■
The first line is a comment line, because of the semicolon character.
■
The second line expects the output to be 1 for the first and fourth vectors,
while all others are expected to be low.
■
At 20 time units, HSPICE or HSPICE RF expects the first and second
vectors to be high, and the third and fourth to be low.
■
At 30 time units, HSPICE or HSPICE RF expects only the first vector to be
high, and all others low.
■
At 35 time units, HSPICE or HSPICE RF expects the output of the first two
vectors to be “don’t care”; it expects vectors 3 and 4 to be low.
Verilog Value Format
HSPICE or HSPICE RF accepts Verilog-sized format to specify numbers; for
example,
<size> ’<base format> <number>
Where:
■
<size> specifies the number of bits, in decimal format.
■
<base format> indicates:
■
•
binary (’b or ’B)
•
octal (’o or ’O)
•
hexadecimal (’h or ’H).
<number> are combinations of the 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, A, B, C, D, E,
and F characters. Depending on what base format you choose, only a
subset of these characters might be legal.
You can also use unknown values (X) and high-impedance (Z) in the
<number> field. An X or Z sets four bits in the hexadecimal base, three bits
in the octal base, or one bit in the binary base.
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If the most significant bit of a number is 0, X, or Z, HSPICE or HSPICE RF
automatically extends the number (if necessary), to fill the remaining bits
with 0, X, or Z, respectively. If the most significant bit is 1, HSPICE or
HSPICE RF uses 0 to extend it.
For example,
4’b1111
12’hABx
32’bZ
8’h1
This example specifies values for:
■
4-bit signal in binary
■
12-bit signal in hexadecimal
■
32-bit signal in binary
■
8-bit signal in hexadecimal
Equivalents of these lines in non-Verilog format, are:
1111
AB xxxx
ZZZZ ZZZZ ZZZZ ZZZZ ZZZZ ZZZZ ZZZZ ZZZZ
1000 0000
Periodic Tabular Data
Tabular data is often periodic, so you do not need to specify the absolute time
at every time point. When you specify the PERIOD statement, the Tabular Data
section omits the absolute times. For more information, see Defining Tabular
Data on page 209.
For example, the PERIOD statement in the following sets the time interval to
10ns between successive lines in the tabular data. This is a shortcut when you
use vectors in regular intervals throughout the entire simulation.
RADIX 1111 1111
VNAME A B C D E F G H
IO IIII IIII
TUNIT ns
PERIOD 10
; start of vector data section
1000 1000
1100 1100
1010 1001
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Waveform Characteristics
The Waveform Characteristics section defines various attributes for signals,
such as the rise or fall time, the thresholds for logic high or low, and so on. For
example,
TRISE 0.3 137F 0000
TFALL 0.5 137F 0000
VIH 5.0 137F 0000
VIL 0.0 137F 0000
The waveform characteristics are based on a bit-mask. Where:
■
The TRISE (signal rise time) setting of 0.3ns applies to the first four vectors,
but not to the last four.
■
The example does not show how many bits are in each of the first four
vectors, although the first vector is at least one bit.
■
The fourth vector is four bits, because F is hexadecimal for binary 1111.
■
All bits of the fourth vector have a rise time of 0.3ns for the constant you
defined in TUNIT. This also applies to TFALL (fall time), VIH (voltage for
logic-high inputs), and VIL (voltage for logic-low inputs).
Modifying Waveform Characteristics
The TDELAY, IDELAY, and ODELAY statements define the delay time of the
signal, relative to the absolute time of each row in the Tabular Data section.
■
TDELAY applies to the input and output delay time of input, output, and
bidirectional signals.
■
IDELAY applies to the input delay time of bidirectional signals.
■
ODELAY applies to the output delay time of bidirectional signals.
The SLOPE statement specifies the rise and fall times for the input signal. To
specify the signals to which the slope applies, use a mask.
The TFALL statement sets an input fall time for specific vectors.
The TRISE statement sets an input rise time for specific vectors.
The TUNIT statement defines the time unit.
The OUT and OUTZ keywords are equivalent, and specify output resistance for
each signal (for which the mask applies); OUT (or OUTZ) applies only to input
signals.
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The TRIZ statement specifies the output impedance, when the signal (for
which the mask applies) is in tristate; TRIZ applies only to the input signals.
The VIH statement specifies the logic-high voltage for each input signal to
which the mask applies.
The VIL statement specifies the logic-low voltage for each input signal to which
the mask applies.
Similar to the TDELAY statement, the VREF statement specifies the name of the
reference voltage for each input vector to which the mask applies. VREF applies
only to input signals.
Similar to the TDELAY statement, the VTH statement specifies the logic
threshold voltage for each output signal to which the mask applies. The
threshold voltage determines the logic state of output signals for comparison
with the expected output signals.
The VOH statement specifies the logic-high voltage for each output signal to
which the mask applies.
The VOL statement specifies the logic-low voltage for each output signal to
which the mask applies.
Using the Context-Based Control Option
The OPTION CBC (Context-Based Control) specifies the direction of
bidirectional signals. A bidirectional signal is an input if its value is 0, 1, or Z;
conversely, a bidirectional signal is an output if its value is H, L, U, or X.
For example,
RADIX 1 1 1
IO I O B
VNAME A Z B
OPTION CBC
10.0 0 X L
20.0 1 1 H
30.0 1 0 Z
This example sets up three vectors, named A, Z, and B. Vector A is an input,
vector Z is an output, and vector B is a bidirectional signal (defined in the IO
statement).
The OPTION CBC line turns on context-based control. The next line sets vector
A to a logic-low at 10.0 ns, and vector Z is "do not care." Because the L value
is under vector B, HSPICE expects a logic-low output.
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At 20 ns, vector A transitions high, and the expected outputs at vectors Z and B
are high. Finally, at 30 ns, HSPICE expects vector Z to be low, vector B
changes from an output to a high-impedance input, and vector the A signal
does not change.
Comment Lines and Line Continuations
Any line in a VEC file that begins with a semicolon (;) is a comment line.
Comments can also start at any point along a line. HSPICE or HSPICE RF
ignores characters after a semicolon. For example,
; This is a comment line
radix 1 1 4 1234 ; This is a radix line
As in netlists, any line in a VEC file that starts with a plus sign (+) is a
continuation from the previous line.
Parameter Usage
You can use .PARAM statements with some VEC statement when you run
HSPICE. These VEC statements fall into the three groups, which are described
in the following sections. No other VEC statements but those identified here
support .PARAM statements.
First Group
■
PERIOD
■
TDELAY
■
IDELAY
■
ODELAY
■
SLOPE
■
TRISE
■
TFALL
For these statements, the TUNIT statement defines the time unit. If you do not
include a TUNIT statement, the default time unit value is ns.
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Do not specify absolute unit values in a .PARAM statement. For example, if in
your netlist:
.param myperiod = 10ns
$ ‘ns’ makes this incorrect
And in your VEC file:
tunit ns
period myperiod
What you wanted for the time period is 10ns; however, because you specified
absolute units, 1e-8ns is the value used. In this example, the correct form is:
.param myperiod = 10
Second Group
■
OUT or OUTZ
■
TRIZ
In these statements, the unit is ohms.
■
If you do not include an OUT (or OUTZ) statement, the default is 0.
■
If you do not include a TRIZ statement, the default is 1000M.
The .PARAM definition for this group follows the HSPICE syntax.
For example, if in your netlist:
.param myout=10
$ means 10 ohm
.param mytriz= 10Meg
$ means 10,000,000 ohm, don't
$ confuse Meg with M, M means 0.001
And in your VEC file:
out myout
triz mytriz
Then, HSPICE returns 10 ohm for OUT and 10,000,000 ohm for TRIZ.
Third Group
■
VIH
■
VIL
■
VOH
■
VOL
■
VTH
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In these statements, the unit is volts.
■
If you do not include an VIH statement, the default is 3.3.
■
If you do not include a VIL statement, the default is 0.0.
■
If you do not include a VOH statement, the default is 2.64.
■
If you do not include an VOL statement, the default is 0.66.
■
If you do not include an VTH statement, the default is 1.65.
Digital Vector File Example
; specifies # of bits associated with each vector
radix 1 2 444
;****************************************************
; defines name for each vector. For multi-bit vectors,
; innermost [] provide the bit index range, MSB:LSB
vname v1 va[[1:0]] vb[[12:1]]
;actual signal names: v1, va[0], va[1], vb1 ... vb12
;****************************************************
; defines vector as input, output, or bi-directional
io i o bbb
; defines time unit
tunit ns
;****************************************************
; vb12-vb5 are output when ‘v1’ is ‘high’
enable v1 0 0 FF0
; vb4-vb1 are output when ‘v1’ is ‘low’
enable ~v1 0 0 00F
;****************************************************
; all signals have a delay of 1 ns
; Note: do not put the unit (such as ns) here again.
; HSPICE multiplies this value by the specified ‘tunit’.
tdelay 1.0
; va1 and va0 signals have 1.5ns delays
tdelay 1.5 0 3 000
;****************************************************
; specify input rise/fall times (if you want different
; rise/fall times, use the trise/tfall statement.)
; Note: do not put the unit (such as ns) here again.
; HSPICE multiplies this value by the specified ‘tunit’.
slope 1.2
;****************************************************
; specify the logic ‘high’ voltage for input signals
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vih 3.3 1 0 000
vih 5.0 0 0 FFF
; to specify logic low, use ‘vil’
;****************************************************
; va & vb switch from ‘lo’ to ‘hi’ at 1.75 volts
vth 1.75 0 1 FFF
;****************************************************
; tabular data section
10.0 1 3 FFF
20.0 0 2 AFF
30.0 1 0 888
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6
Parameters and Functions
6
Describes how to use parameters within an HSPICE netlist.
Parameters are similar to the variables used in most programming languages.
Parameters hold a value that you assign when you create your circuit design or
that the simulation calculates based on circuit solution values. Parameters can
store static values for a variety of quantities (resistance, source voltage, rise
time, and so on). You can also use them in sweep or statistical analysis.
For descriptions of individual HSPICE commands referenced in this chapter,
see the HSPICE Command Reference manual.
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Using Parameters in Simulation (.PARAM)
Using Parameters in Simulation (.PARAM)
Defining Parameters
Parameters in HSPICE are names that you associate with numeric values.
(See “Defining Parameters.”) You can use any of these methods to define
parameters:
Table 17
.PARAM Syntax
Parameter
Description
Simple assignment
.PARAM <SimpleParam> = 1e-12
Algebraic definition
.PARAM <AlgebraicParam> = ‘SimpleParam*8.2’
SimpleParam excludes the output variable.
You can also use algebraic parameters in .PRINT and .PROBE
statements (HSPICE or HSPICE RF), and in .PLOT, and .GRAPH
statements (HSPICE only). For example:
.PRINT AlgebraicParam=par(’algebraic expression’)
You can use the same syntax for .PROBE, .PLOT, and .GRAPH
statements. See Using Algebraic Expressions on page 226.
User-defined function
.PARAM <MyFunc( x, y )> = ‘Sqrt((x*x)+(y*y))’
Character string
definition
.PARAM <paramname>=str(‘string’)
Subcircuit default
.SUBCKT <SubName> <ParamDefName> = <Value>
str(‘string’)
.MACRO <SubName> <ParamDefName> = <Value>
str(‘string’)
Predefined analysis
function
222
.PARAM <mcVar> = Agauss(1.0,0.1)
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Table 17
.PARAM Syntax (Continued)
Parameter
Description
.MEASURE statement
.MEASURE <DC | AC | TRAN> result TRIG ...
+ TARG ... <GOAL = val> <MINVAL = val>
+ <WEIGHT = val> <MeasType> <MeasParam>
(See Specifying User-Defined Analysis (.MEASURE) on page 268)
.PRINT | .PROBE |
.PLOT | .GRAPH
.PRINT | .PROBE | .PLOT | .GRAPH <DC|AC|TRAN>
+ outParam = Par_Expression
A parameter definition in HSPICE always uses the last value found in the input
netlist (subject to local versus global parameter rules). The definitions below
assign a value of 3 to the DupParam parameter.
.PARAM DupParam = 1
...
.PARAM DupParam = 3
HSPICE assigns 3 as the value for all instances of DupParam, including
instances that are earlier in the input than the .PARAM DupParam = 3
statement.
All parameter values in HSPICE are IEEE double floating point numbers.
Parameter resolution order is:
1. Resolve all literal assignments.
2. Resolve all expressions.
3. Resolve all function calls.
Table 18 shows the parameter passing order.
Table 18 Parameter Passing Order
.OPTION PARHIER = GLOBAL
.OPTION PARHIER = LOCAL
Analysis sweep parameters
Analysis sweep parameters
.PARAM statement (library)
.SUBCKT call (instance)
.SUBCKT call (instance)
.SUBCKT definition (symbol)
.SUBCKT definition (symbol)
.PARAM statement (library)
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Using Parameters in Simulation (.PARAM)
Assigning Parameters
You can assign the following types of values to parameters:
■
Constant real number.
■
Algebraic expression of real values.
■
Predefined function.
■
Function that you define.
■
Circuit value.
■
Model value.
To invoke the algebraic processor, enclose a complex expression in single
quotes. A simple expression consists of one parameter name.
The parameter keeps the assigned value, unless:
■
Later definition changes its value, or
■
Algebraic expression assigns a new value during simulation.
HSPICE does not warn you, if they reassign a parameter.
Inline Parameter Assignments
To define circuit values, using a direct algebraic evaluation:
r1 n1 0 R = ’1k/sqrt(HERTZ)’ $ Resistance for frequency
Parameters in Output
To use an algebraic expression as an output variable in
a .PRINT, .PLOT, .PROBE .GRAPH, or .MEASURE statement, use the PAR
keyword. (See Chapter 7, “Simulation Output,” for more information about
simulation output.)
Example
.PRINT DC v(3) gain = PAR(‘v(3)/v(2)’) PAR(‘v(4)/v(2)’)
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User-Defined Function Parameters
You can define a function that is similar to the parameter assignment, but you
cannot nest the functions more than two deep.
The format of a function is:
funcname1(arg1[,arg2...]) = expression1
+ [funcname2(arg1[,arg2...]) = expression2] off
■
An expression can contain parameters that you did not define.
■
A function must have at least one argument, and can have up to 20 (and in
many cases, more than 20) arguments.
■
You can redefine functions.
Parameter
Description
funcname
Specifies the function name. This parameter must be distinct from
array names and built-in functions. In subsequently defined functions,
all embedded functions must be previously defined.
arg1, arg2
Specifies variables used in the expression.
off
Voids all user-defined functions.
Example
f(a,b) = POW(a,2)+a*b g(d) = SQRT(d)
+ h(e) = e*f(1,2)-g(3)
Predefined Analysis Function
HSPICE includes specialized analysis types, such as Optimization and Monte
Carlo, that require a way to control the analysis.
Measurement Parameters
.MEASURE statements produce a measurement parameter. The rules for
measurement parameters are the same as for standard parameters, except
that measurement parameters are defined in a .MEASURE statement, not in
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a .PARAM statement. For a description of the .MEASURE statement, see
Specifying User-Defined Analysis (.MEASURE) on page 268.
.PRINT|.PROBE|.PLOT|.GRAPH Parameters
.PRINT|.PROBE|.PLOT|.GRAPH statements in HSPICE produce a print
parameter. The rules for print parameters are the same as the rules for
standard parameters, except that you define the parameter directly in
a .PRINT|.PROBE|.PLOT|.GRAPH statement, not in a .PARAM statement.
HSPICE RF does not support .PLOT|.GRAPH statements.
For more information about the .PRINT|.PROBE|.PLOT|.GRAPH statements,
see Displaying Simulation Results on page 244.
Multiply Parameter
The most basic subcircuit parameter in HSPICE is the M (multiply) parameter.
For a description of this parameter, see M (Multiply) Parameter on page 64.
Using Algebraic Expressions
Note: Synopsys HSPICE uses double-precision numbers (15 digits) for
expressions, user-defined parameters, and sweep variables. For better
precision, use parameters (instead of constants) in algebraic expressions,
because constants are only single-precision numbers (7 digits).
In HSPICE, an algebraic expression, with quoted strings, can replace any
parameter in the netlist.
In HSPICE, you can then use these expressions as output variables
in .PLOT, .PRINT, and .GRAPH statements. Algebraic expressions can expand
your options in an input netlist file.
Some uses of algebraic expressions are:
■
Parameters:
.PARAM x = ’y+3’
■
Functions:
.PARAM rho(leff,weff) = ’2+*leff*weff-2u’
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Algebra in elements:
■
R1 1 0 r = ’ABS(v(1)/i(m1))+10’
Algebra in .MEASURE statements:
■
.MEAS vmax MAX V(1)
.MEAS imax MAX I(q2)
.MEAS ivmax PARAM = ’vmax*imax’
Algebra in output statements:
■
.PRINT conductance = PAR(‘i(m1)/v(22)’)
The basic syntax for using algebraic expressions for output is:
PAR(‘algebraic expression’)
In addition to using quotations, you must define the expression inside the
PAR( ) statement for output.The continuation character for quoted parameter
strings, in HSPICE, is a double backslash (\\). (Outside of quoted strings, the
single backslash (\) is the continuation character.)
Built-In Functions and Variables
In addition to simple arithmetic operations (+, -, *, /), HSPICE provides
several built-in functions and variables, listed in Table 19 and Table 20
respectively, that you can use in expressions:
Table 19
Synopsys HSPICE Built-in Functions
HSPICE Form
Function
Class
Description
sin(x)
sine
trig
Returns the sine of x (radians)
cos(x)
cosine
trig
Returns the cosine of x (radians)
tan(x)
tangent
trig
Returns the tangent of x (radians)
asin(x)
arc sine
trig
Returns the inverse sine of x (radians)
acos(x)
arc cosine
trig
Returns the inverse cosine of x (radians)
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Table 19
Synopsys HSPICE Built-in Functions (Continued)
HSPICE Form
Function
Class
Description
atan(x)
arc tangent
trig
Returns the inverse tangent of x (radians)
sinh(x)
hyperbolic
sine
trig
Returns the hyperbolic sine of x (radians)
cosh(x)
hyperbolic
cosine
trig
Returns the hyperbolic cosine of x (radians)
tanh(x)
hyperbolic
tangent
trig
Returns the hyperbolic tangent of x (radians)
abs(x)
absolute
value
math
Returns the absolute value of x: |x|
sqrt(x)
square root
math
Returns the square root of the absolute
value of x: sqrt(-x) = -sqrt(|x|)
pow(x,y)
absolute
power
math
Returns the value of x raised to the integer
part of y: x(integer part of y)
pwr(x,y)
signed
power
math
Returns the absolute value of x, raised to the
y power, with the sign of x: (sign of x)|x|y
x**y
power
If x<0, returns the value of x raised to the
integer part of y.
If x=0, returns 0.
If x>0, returns the value of x raised to the y
power.
log(x)
natural
logarithm
math
Returns the natural logarithm of the absolute
value of x, with the sign of x: (sign of
x)log(|x|)
log10(x)
base 10
logarithm
math
Returns the base 10 logarithm of the
absolute value of x, with the sign of x: (sign
of x)log10(|x|)
exp(x)
exponential
math
Returns e, raised to the power x: ex
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Table 19
Synopsys HSPICE Built-in Functions (Continued)
HSPICE Form
Function
Class
Description
db(x)
decibels
math
Returns the base 10 logarithm of the
absolute value of x, multiplied by 20, with the
sign of x: (sign of x)20log10(|x|)
int(x)
integer
math
Returns the integer portion of x. The
fractional portion of the number is lost.
nint(x)
integer
math
Rounds x up or down, to the nearest integer.
sgn(x)
return sign
math
Returns -1 if x is less than 0.
Returns 0 if x is equal to 0.
Returns 1 if x is greater than 0
sign(x,y)
transfer
sign
math
Returns the absolute value of x, with the sign
of y: (sign of y)|x|
min(x,y)
smaller of
two args
control
Returns the numeric minimum of x and y
max(x,y)
larger of
two args
control
Returns the numeric maximum of x and y
val(element)
get value
various
Returns a parameter value for a specified
element. For example, val(r1) returns the
resistance value of the r1 resistor.
val(element.
parameter)
get value
various
Returns a value for a specified parameter of
a specified element. For example,
val(rload.temp) returns the value of the temp
(temperature) parameter for the rload
element.
val(model_type:
model_name.
model_param)
get value
various
Returns a value for a specified parameter of
a specified model of a specific type. For
example, val(nmos:mos1.rs) returns the
value of the rs parameter for the mos1
model, which is an nmos model type.
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Table 19
Synopsys HSPICE Built-in Functions (Continued)
HSPICE Form
Function
Class
Description
lv
(<Element>)
or
lx
(<Element>)
element
templates
various
Returns various element values during
simulation. See Element Template Output on
page 267 for more information.
v(<Node>),
i(<Element>)...
circuit
output
variables
various
Returns various circuit values during
simulation. See DC and Transient Output
Variables on page 251 for more information.
[cond] ?x : y
ternary
operator
Returns x if cond is not zero. Otherwise,
returns y.
.param z=’condition ? x:y’
<
<=
>
>=
==
relational
operator
(less than)
Returns 1 if the left operand is less than the
right operand. Otherwise, returns 0.
relational
operator
(less than
or equal)
Returns 1 if the left operand is less than or
equal to the right operand. Otherwise,
returns 0.
relational
operator
(greater
than)
Returns 1 if the left operand is greater than
the right operand. Otherwise, returns 0.
relational
operator
(greater
than or
equal)
Returns 1 if the left operand is greater than
or equal to the right operand. Otherwise,
returns 0.
equality
Returns 1 if the operands are equal.
Otherwise, returns 0.
.para x=y<z (y less than z)
.para x=y<=z (y less than or equal to z)
.para x=y>z (y greater than z)
.para x=y>=z (y greater than or equal to z)
.para x=y==z (y equal to z)
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Table 19
Synopsys HSPICE Built-in Functions (Continued)
HSPICE Form
Function
Class
Description
inequality
!=
Returns 1 if the operands are not equal.
Otherwise, returns 0.
.para x=y!=z (y not equal to z)
&&
Logical
AND
Returns 1 if neither operand is zero.
Otherwise, returns 0. .para x=y&&z (y AND
z)
||
Logical OR
Returns 1 if either or both operands are not
zero. Returns 0 only if both operands are
zero.
.para x=y||z (y OR z)
Example
.parameters p1=4 p2=5 p3=6
r1 1 0 value='p1 ? p2+1 : p3'
HSPICE reserves the variable names listed in Table 20 for use in elements,
such as E, G, R, C, and L. You can use them in expressions, but you cannot
redefine them; for example, this statement would be illegal:
.param temper=100
Table 20
Synopsys HSPICE Special Variables
HSPICE Form
time
Function
Class
Description
current
simulation time
control
Uses parameters to define the current
simulation time, during transient analysis.
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Table 20
Synopsys HSPICE Special Variables (Continued)
HSPICE Form
Function
Class
Description
temper
current circuit
temperature
control
Uses parameters to define the current
simulation temperature, during transient/
temperature analysis.
hertz
current
simulation
frequency
control
Uses parameters to define the frequency,
during AC analysis.
Parameter Scoping and Passing
If you use parameters to define values in sub-circuits, you need to create fewer
similar cells, to provide enough functionality in your library. You can pass circuit
parameters into hierarchical designs, and assign different values to the same
parameter within individual cells, when you run simulation.
For example, if you use parameters to set the initial state of a latch in its
subcircuit definition, then you can override this initial default in the instance call.
You need to create only one cell, to handle both initial state versions of the
latch.
You can also use parameters to define the cell layout. For example, you can
use parameters in a MOS inverter, to simulate a range of inverter sizes, with
only one cell definition. Local instances of the cell can assign different values to
the size parameter for the inverter.
In HSPICE, you can also perform Monte Carlo analysis or optimization on a cell
that uses parameters.
How you handle hierarchical parameters depends on how you construct and
analyze your cells. You can construct a design in which information flows from
the top of the design, down into the lowest hierarchical levels.
■
To centralize the control at the top of the design hierarchy, set global
parameters.
■
To construct a library of small cells that are individually controlled from
within, set local parameters and build up to the block level.
This section describes the scope of parameter names, and how HSPICE
resolves naming conflicts between levels of hierarchy.
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Library Integrity
Integrity is a fundamental requirement for any symbol library. Library integrity
can be as simple as a consistent, intuitive name scheme, or as complex as
libraries with built-in range checking.
Library integrity might be poor if you use libraries from different vendors in a
circuit design. Because names of circuit parameters are not standardized
between vendors, two components can include the same parameter name for
different functions. For example, one vendor might build a library that uses the
name Tau as a parameter to control one or more subcircuits in their library.
Another vendor might use Tau to control a different aspect of their library. If you
set a global parameter named Tau to control one library, you also modify the
behavior of the second library, which might not be the intent.
If the scope of a higher-level parameter is global to all sub-circuits at lower
levels of the design hierarchy, higher-level definitions override lower-level
parameter values with the same names. The scope of a lower-level parameter
is local to the subcircuit where you define the parameter (but global to all
subcircuits that are even lower in the design hierarchy). Local scoping rules in
HSPICE prevent higher-level parameters from overriding lower-level
parameters of the same name, when that is not desired.
Reusing Cells
Parameter name problems also occur if different groups collaborate on a
design. Global parameters prevail over local parameters, so all circuit
designers must know the names of all parameters, even those used in sections
of the design for which they are not responsible. This can lead to a large
investment in standard libraries. To avoid this situation, use local parameter
scoping, to encapsulate all information about a section of a design, within that
section.
Creating Parameters in a Library
To ensure that the input netlist includes critical, user-supplied parameters when
you run simulation, you can use “illegal defaults”—that is, defaults that cause
the simulator to abort if you do not supply overrides for the defaults.
If a library cell includes illegal defaults, you must provide a value for each
instance of those cells. If you do not, the simulation aborts.
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For example, you might define a default MOSFET width of 0.0. HSPICE aborts,
because MOSFET models require this parameter.
Example 1
* Subcircuit default definition
.SUBCKT Inv A Y Wid = 0 $ Inherit illegal values by default
mp1 <NodeList> <Model> L = 1u W = ’Wid*2’
mn1 <NodeList> <Model> L = 1u W = Wid
.ENDS
* Invoke symbols in a design
x1 A Y1 Inv$ Bad! No widths specified
x2 A Y2 Inv Wid = 1u $ Overrides illegal value for Width
This simulation aborts on the x1 subcircuit instance, because you never set the
required Wid parameter on the subcircuit instance line. The x2 subcircuit
simulates correctly. Additionally, the instances of the Inv cell are subject to
accidental interference, because the Wid global parameter is exposed outside
the domain of the library. Anyone can specify an alternative value for the
parameter, in another section of the library or the circuit design. This might
prevent the simulation from catching the condition on x1.
Example 2
In this example, the name of a global parameter conflicts with the internal
library parameter named Wid. Another user might specify such a global
parameter, in a different library. In this example, the user of the library has
specified a different meaning for the Wid parameter, to define an independent
source.
.Param Wid = 5u$ Default Pulse Width for source
v1 Pulsed 0 Pulse ( 0v 5v 0u 0.1u 0.1u Wid 10u )
...
* Subcircuit default definition
.SUBCKT Inv A Y Wid = 0 $ Inherit illegals by default
mp1 <NodeList> <Model> L = 1u W = ’Wid*2’
mn1 <NodeList> <Model> L = 1u W = Wid
.Ends
* Invoke symbols in a design
x1 A Y1 Inv$ Incorrect width!
x2 A Y2 Inv Wid = 1u $ Incorrect! Both x1 and x2
$ simulate with mp1 = 10u and
$ mn1 = 5u instead of 2u and 1u.
Under global parameter scoping rules, simulation succeeds, but incorrectly.
HSPICE does not warn you that the x1 inverter has no assigned width,
because the global parameter definition for Wid overrides the subcircuit default.
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Note: Similarly, sweeping with different values of Wid dynamically changes both
the Wid library internal parameter value, and the pulse width value to the
Wid value of the current sweep.
In global scoping, the highest-level name prevails, when resolving name
conflicts. Local scoping uses the lowest-level name.
When you use the parameter inheritance method, you can specify to use local
scoping rules. This feature can cause different results than you obtained using
HSPICE versions before release 95.1, on existing circuits.
When you use local scoping rules, the Example 2 netlist correctly aborts in x1
for W = 0 (default Wid = 0, in the .SUBCKT definition, has higher precedence,
than the .PARAM statement). This results in the correct device sizes for x2. This
change can affect your simulation results, if you intentionally or accidentally
create a circuit such as the second one shown above.
As an alternative to width testing in the Example 2 netlist, you can
use .OPTION DEFW to achieve a limited version of library integrity. This option
sets the default width for all MOS devices during a simulation. Part of the
definition is still in the top-level circuit, so this method can still make unwanted
changes to library values, without notification from the HSPICE simulator.
Table 21 compares the three primary methods for configuring libraries, to
achieve required parameter checking for default MOS transistor widths.
Table 21
Method
Local
Methods for Configuring Libraries
Parameter
Location
On a .SUBCKT
definition line
Pros
Cons
Protects library from global
circuit parameter definitions,
unless you override it. Single
location for default values.
You cannot use it with
versions of HSPICE before
Release 95.1.
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Table 21
Method
Methods for Configuring Libraries (Continued)
Parameter
Location
Pros
Cons
Global
At the global level
and on .SUBCKT
definition lines
Works with older HSPICE
versions.
An indiscreet user, another
vendor assignment, or the
intervening hierarchy can
change the library. Cannot
override a global value at a
lower level.
Special
.OPTION DEFW
statement
Simple to do.
Third-party libraries, or other
sections of the design, might
depend on .OPTION DEFW.
String Parameter
HSPICE uses a special delimiter to identify string and double parameter types.
The single quotes (‘), double quotes (“), or curly brackets ( {} ) do not work for
these kinds of delimiters. Instead, use the sp1 = str('string') keyword for an sp1
parameter definition and use the str(sp1) keyword for a string parameter
instance.
Example
The following sample netlist shows an example of how you can use these
definitions for various commands, keywords, parameters, and elements:
xibis1 vccq vss out in IBIS
+ IBIS_FILE=str('file1.ibs') IBIS_MODEL=str('model1')
xibis2 vccq vss out in IBIS
+ IBIS_FILE=str('file2.ibs') IBIS_MODEL=str('model2')
.subckt IBIS vccq vss out in
+ IBIS_FILE=str('file.ibs')
+ IBIS_MODEL=str('ibis_model')
ven en 0 vcc
BMCH vccq vss out in en v0dq0 vccq vss buffer=3
+ file= str(IBIS_FILE) model=str(IBIS_MODEL)
+ typ = typ ramp_rwf = 2 ramp_fwf = 2 power=on
.ends
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HSPICE can now support these kinds of definitions and instances with the
following netlist components:
■
.PARAM statements
■
.SUBCKT statements
■
FQMODEL keywords
■
S Parameters
■
FILE and MODEL keywords
■
B Elements
■
RLGCFILE, UMODEL, FSMODEL, RLGCMODEL, TABLEMODEL, and SMODEL
keywords in the W Element
Parameter Defaults and Inheritance
Use the .OPTION PARHIER parameter to specify scoping rules.
Syntax:
.OPTION PARHIER = < GLOBAL | LOCAL >
The default setting is GLOBAL, which uses the same scoping rules that
HSPICE used before Release 95.1.
Example
This example explicitly shows the difference between local and global scoping
for using parameters in sub-circuits.
The input netlist includes the following:
.OPTION parhier=<global | local>
.PARAM DefPwid = 1u
.SUBCKT Inv a y DefPwid = 2u DefNwid = 1u
Mp1 <MosPinList> pMosMod L = 1.2u W = DefPwid
Mn1 <MosPinList> nMosMod L = 1.2u W = DefNwid
.ENDS
Set the .OPTION PARHIER = parameter scoping option to GLOBAL.
The netlist also includes the following input statements:
xInv0 a y0 Inv$ override DefPwid default,
$ xInv0.Mp1 width = 1u
xInv1 a y1 Inv DefPwid = 5u $ override DefPwid=5u,
$ xInv1.Mp1 width = 1u
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.measure tran Wid0 param = ’lv2(xInv0.Mp1)’$ lv2 is the
$ template for
.measure tran Wid1 param = ’lv2(xInv1.Mp1)’$ the channel
$ width
$ ‘lv2(xInv1.Mp1)’
.ENDS
Simulating this netlist produces the following results in the listing file:
wid0 = 1.0000E-06
wid1 = 1.0000E-06
If you change the .OPTION PARHIER = parameter scoping option
to LOCAL:
xInv0 a y0 Inv
$ not override .param
$ DefPwid=2u,
$ xInv0.Mp1 width = 2u
xInv1 a y1 Inv DefPwid = 5u
$ override .param
$ DefPwid=2u,
$ xInv1.Mp1 width = 5u:
.measure tran Wid0 param = ’lv2(xInv0.Mp1)’$ override the
.measure tran Wid1 param = ’lv2(xInv1.Mp1)’$ global .PARAM
...
Simulation produces the following results in the listing file:
wid0 = 2.0000E-06
wid1 = 5.0000E-06
Parameter Passing
Figure 28 shows a flat representation of a hierarchical circuit, which contains
three resistors.
Each of the three resistors obtains its simulation time resistance from the Val
parameter. The netlist defines the Val parameter in four places, with three
different values.
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Figure 28
+
Hierarchical Parameter Passing Problem
Sub1
Sub2
Sub3
r1
r2
r3
1V
-
TEST OF PARHIER
.OPTION list node post = 2
+ ingold = 2
+ parhier = <Local|Global>
.PARAM Val = 1
x1 n0 0 Sub1
.SubCkt Sub1 n1 n2 Val = 1
r1 n1 n2 Val
x2 n1 n2 Sub2
.Ends Sub1
.SubCkt Sub2 n1 n2 Val = 2
r2 n1 n2 Val
x3 n1 n2 Sub3
.Ends Sub2
.SubCkt Sub3 n1 n2 Val = 3
r3 n1 n2 Val
.Ends Sub3
.OP
.END
The total resistance of the chain has two possible solutions: 0.3333Ω and
0.5455Ω .
You can use .OPTION PARHIER to specify which parameter value prevails,
when you define parameters with the same name at different levels of the
design hierarchy.
Under global scoping rules, if names conflict, the top-level assignment .PARAM
Val = 1 overrides the subcircuit defaults, and the total is 0.3333Ω. Under
local scoping rules, the lower level assignments prevail, and the total is
0.5455Ω (one, two, and three ohms in parallel).
The example in Figure 28 produces the results in Table 22, based on how you
set .OPTION PARHIER to local/global:
Table 22 PARHIER = LOCAL vs. PARHIER = GLOBAL Results
Element
PARHIER = Local
PARHIER = Global
r1
1.0
1.0
r2
2.0
1.0
r3
3.0
1.0
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Parameter Passing Solutions
Changes in scoping rules can cause different simulation results for circuit
designs created before HSPICE Release 95.1, than for designs created after
that release. The checklist below determines whether you will see simulation
differences when you use the new default scoping rules. These checks are
especially important if your netlists contain devices from multiple vendor
libraries.
240
■
Check your sub-circuits for parameter defaults, on the .SUBCKT or .MACRO
line.
■
Check your sub-circuits for a .PARAM statement, within a .SUBCKT
definition.
■
To check your circuits for global parameter definitions, use the .PARAM
statement.
■
If any of the names from the first three checks are identical, set up two
HSPICE simulation jobs: one with .OPTION PARHIER = GLOBAL, and
one with .OPTION PARHIER = LOCAL. Then look for differences in the
output.
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Overview of Output Statements
7
Simulation Output
7
Describes how to use output format statements and variables to
display steady state, frequency, and time domain simulation results.
You can also use output variables in behavioral circuit analysis, modeling, and
simulation techniques. To display electrical specifications such as rise time,
slew rate, amplifier gain, and current density, use the output format features.
For descriptions of individual HSPICE commands referenced in this chapter,
see the HSPICE Command Reference Manual.
Overview of Output Statements
Output Commands
The input netlist file contains output statements, including .PRINT,
.PLOT, .GRAPH, .PROBE, .MEASURE, and .DOUT. Each statement specifies
the output variables, and the type of simulation result, to display—such
as .DC, .AC, or .TRAN. When you specify .OPTION POST, Synopsys HSPICE
puts all output variables, referenced in .PRINT, .PLOT, .GRAPH, .PROBE,
.MEASURE, .DOUT, and .STIM statements, into AvanWaves interface files.
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HSPICE RF supports only .OPTION POST, .OPTION PROBE, .PRINT,
.PROBE, and .MEASURE. It does not support .DOUT, .PLOT, .GRAPH,
or .STIM. AvanWaves provides high-resolution, post-simulation, and
interactive display of waveforms.
Table 23 Output Statements
Output
Statement
Description
.PRINT
Prints numeric analysis results in the output listing file (and postprocessor data, if you specify .OPTION POST).
.PLOT
Obsolete option. Use .PRINT or ..PROBE to generate
necessary plot in the output listing file. Generates low-resolution
(ASCII) plots in the output listing file (and post-processor data, if
you specify .OPTION POST), in HSPICE only (not supported in
HSPICE RF).
(HSPICE only)
.GRAPH
(HSPICE only)
242
Obsolete option. Use .PRINT or ..PROBE to generate
necessary plot in the output listing file. Generates highresolution plots for specific printing devices (such as HP
LaserJet), or in PostScript format (intended for hard-copy
outputs, without using a post-processor).
.PROBE
Outputs data to post-processor output files, but not to the output
listing (used with .OPTION PROBE, to limit output).
.MEASURE
Prints the results of specific user-defined analyses (and postprocessor data, if you specify .OPTION POST), to the output
listing file. or HSPICE RF
.DOUT
Specifies the expected final state of an output signal (HSPICE
only; not supported in HSPICE RF).
.STIM
Specifies simulation results to transform to PWL, Data Card, or
Digital Vector File format. Not supported in HSPICE RF.
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Output Variables
The output format statements require special output variables, to print or plot
analysis results for nodal voltages and branch currents. HSPICE or HSPICE
RF uses the following output variables:
■
DC and transient analysis
■
AC analysis
■
element template (HSPICE only; not supported in HSPICE RF)
■
.MEASURE statement
■
parametric analysis
For HSPICE or HSPICE RF, DC and transient analysis displays:
■
individual nodal voltages: V(n1 [,n2])
■
branch currents: I(Vxx)
■
element power dissipation: In(element)
AC analysis displays imaginary and real components of a nodal voltage or
branch current, and the magnitude and phase of a nodal voltage or branch
current. AC analysis results also print impedance parameters, and input and
output noise.
Element template analysis displays element-specific nodal voltages, branch
currents, element parameters, and the derivatives of the element’s node
voltage, current, or charge. This analysis is available in HSPICE only; HSPICE
RF does not support element template output.
The .MEASURE statement variables define the electrical characteristics to
measure in a .MEASURE statement analysis or HSPICE RF.
Parametric analysis variables are mathematical expressions, which operate on
nodal voltages, branch currents, element template variables (HSPICE only; not
supported in HSPICE RF), or other parameters that you specify. Use these
variables when you run behavioral analysis of simulation results. See Using
Algebraic Expressions on page 226 or HSPICE RF.
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Displaying Simulation Results
The following section describes the statements that you can use to display
simulation results for your specific requirements.
.PRINT Statement
The .PRINT statement specifies output variables for which HSPICE or HSPICE
RF prints values.
■
The maximum number of variables in a single .PRINT statement, was 32
before Release 2002.2, but has been extended. For example, you can enter:
.PRINT v(1) v(2) ... v(32) v(33) v(34)
This function previously required two .PRINT statements:
.PRINT v(1) v(2) ... v(32)
.PRINT v(33) v(34)
■
To simplify parsing of the output listings, HSPICE or HSPICE RF prints a
single x in the first column, to indicate the beginning of the .PRINT output
data. A single y in the first column indicates the end of the .PRINT output
data.
You can include wildcards in .PRINT statements.
You can also use the iall keyword in a .PRINT statement, to print all branch
currents of all diode, BJT, JFET, or MOSFET elements in your circuit design.
Example
If your circuit contains four MOSFET elements (named m1, m2, m3, m4),
then .PRINT iall (m*) is equivalent to .PRINT i(m1) i(m2) i(m3) i(m4). It prints
the output currents of all four MOSFET elements.
Statement Order
HSPICE or HSPICE RF creates different .sw0 and .tr0 files, based on the order
of the .PRINT and .DC statements. If you do not specify an analysis type for
a .PRINT command, the type matches the last analysis command in the
netlist, before the .PRINT statement.
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.PLOT Statement
Note: This is an obsolete statement. You can gain the same functionality by
using the .PRINT Statement.
The .PLOT statement plots the output values of one or more variables, in a
selected HSPICE analysis. Each .PLOT statement defines the contents of one
plot, which can contain more than one output variable.
Note: You cannot use .PLOT in HSPICE RF.
If you do not specify plot limits, HSPICE determines the minimum and
maximum values of each output variable that it plots, and scales each plot to fit
common limits. To force HSPICE to set limits for certain variables, set the plot
limits to (0,0) for the variables.
To make HSPICE find plot limits for each plot individually, use
.OPTION PLIM to create a different axis for each plot variable. The PLIM
option is similar to the plot limit algorithm in SPICE2G.6, where each plot can
have limits different from any other plot. A number from 2 through 9 indicates
the overlap of two or more traces on a plot.
If more than one output variable appears on the same plot, HSPICE prints and
plots the first variable specified. To print out more than one variable, include
another .PLOT statement.
You can specify an unlimited number of .PLOT statements for each type of
analysis. To set the plot width, use .OPTION CO (columns out). If you set CO
to 80, the plot has 50 columns. If CO is 132, the plot has 100 columns.
You can include wildcards in .PLOT statements (HSPICE only).
.PROBE Statement
HSPICE or HSPICE RF usually saves all voltages, supply currents, and output
variables. Set .OPTION PROBE, to save output variables only. Use
the .PROBE statement to specify the quantities to print in the output listing.
If you are interested only in the output data file, and you do not want tabular or
plot data in your listing file, set .OPTION PROBE and use .PROBE to select the
values to save in the output listing.
You can include wildcards in .PROBE statements.
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.GRAPH Statement
Note: This is an obsolete statement. You can gain the same functionality by
using the .PROBE Statement.
Use the .GRAPH statement when you need high-resolution plots of HSPICE
simulation results.
Note: You cannot use .GRAPH statements in the PC version of HSPICE, or in
any versions of HSPICE RF.
The .GRAPH statement is similar to the .PLOT statement, with the addition of
an optional model. When you specify a model, you can add or change graphing
properties for the graph. The .GRAPH statement generates a .gr# graph data
file and sends this file directly to the default high resolution graphical device (to
specify this device, set PRTDEFAULT in the meta.cfg configuration file).
.MODEL Statement for .GRAPH
For a description of how to use the .MODEL statement with
.GRAPH, see the HSPICE Command Reference manual. HSPICE RF does not
support the .GRAPH statement.
Table 24 Model Parameters
Name
(Alias)
Default
Description
MONO
0.0
Monotonic option. MONO = 1 automatically resets the x-axis, if any
change occurs in the x direction.
TIC
0.0
Shows tick marks.
FREQ
0.0
Plots symbol frequency.
• A value of 0 does not generate plot symbols.
• A value of n generates a plot symbol every n points.
This is not the same as the FREQ keyword in element statements (see
“Modeling Filters and Networks” in the HSPICE Applications Manual).
XGRID
,
YGRID
246
0.0
Set these values to 1.0, to turn on the axis grid lines.
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Table 24 Model Parameters (Continued)
Name
(Alias)
Default
Description
XMIN,
XMAX
0.0
• If XMIN is not equal to XMAX, then XMIN and XMAX determine the
x-axis plot limits.
• If XMIN equals XMAX, or if you do not set XMIN and XMAX, then
HSPICE automatically sets the plot limits. These limits apply to the
actual x-axis variable value, regardless of the XSCAL type.
XSCA
L
1.0
Scale for the x-axis. Two common axis scales are:
YMIN,
YMAX
0.0
Linear(LIN)
(XSCAL = 1)
Logarithm(LOG) (XSCAL = 2)
If YMIN is not equal to YMAX, then YMIN and YMAX determine the yaxis plot limits.
The y-axis limits in the .GRAPH statement overrides YMIN and YMAX
in the model.
If you do not specify plot limits, HSPICE sets the plot limits. These limits
apply to the actual y-axis variable value, regardless of the YSCAL type.
YSCA
L
1.0
Scale for the y-axis. Two common axis scales are:
Linear(LIN)
(XSCAL = 1)
Logarithm(LOG) (XSCAL = 2)
Using Wildcards in PRINT, PROBE, PLOT, and GRAPH
Statements
You can include wildcards in .PRINT and .PROBE statements (HSPICE and
HSPICE RF), and in .PLOT and .GRAPH statements (HSPICE only). Refer to
this example netlist in the discussion that follows:
* test wildcard
.option post
v1 1 0 10
r1 1 n20 10
r20 n20 n21 10
r21 n21 0 10
.dc v1 1 10 1
***Wildcard equivalent for:
*.print i(r1) i(r20) i(r21) i(v1)
.print i(*)
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***Wildcard equivalent for:
*.probe v(0) v(1)
.probe v(?)
***Wildcard equivalent for:
*.print v(n20) v(n21)
.print v(n2?)
***Wildcard equivalent for:
*.probe v(n20, 1) v(n21, 1)
.probe v(n2*, 1)
.end
Supported Wildcard Templates
v vm vr vi vp vdb vt
i im ir ii ip idb it
p pm pr pi pp pdb pt
lxn<n> lvn<n> (n is a number 0~9)
i1 im1 ir1 ii1 ip1 idb1 it1
i2 im2 ir2 ii2 ip2 idb2 it2
i3 im3 ir3 ii3 ip3 idb3 it3
i4 im4 ir4 ii4 ip4 idb4 it4
iall
For detailed information about the templates, see Selecting Simulation Output
Parameters on page 251.
Using wildcards in statements such as v(n2?) and v(n2*,1) in the
preceding test case (named test wildcard), you can also use the following in
statements (they are not equivalent if you use an .AC statement instead of
a .DC statement):
vm(n2?) vr(n2?) vi(n2?) vp(n2?) vdb(n2?) vt(n2?)
vm(n2*,1) vr(n2*,1) vi(n2*,1) vp(n2*,1) vdb(n2*,1) vt(n2*,1)
Using wildcards in statements such as i(*) in this test wildcard case. You can
also use the following in statements (they are not equivalent if you use an .AC
statement instead of a .DC statement):
im(*) ir(*) ip(*) idb(*) it(*)
iall is an output template for all branch currents of diode, BJT, JFET, or
MOSFET output. For example, iall(m*) is equivalent to:
i1(m*) i2(m*) i3(m*) i4(m*).
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Print Control Options
The codes that you can use to specify the element templates for output in
HSPICE or HSPICE RF are:
■
.OPTION CO to set column widths in printouts.
■
.WIDTH statement to set the width of a printout.
■
.OPTION INGOLD for output in exponential form.
■
.OPTION POST to display high-resolution AvanWaves plots of simulation
results, on either a graphics terminal or a high-resolution laser printer.
■
.OPTION ACCT to generate a detailed accounting report. HSPICE RF does
not support this statement.
Changing the File Descriptor Limit
A simulation that uses a large number of .ALTER statements might fail,
because of the limit on the number of file descriptors. For example, for a Sun
workstation, the default number of file descriptors is 64, so a design with more
than 50 .ALTER statements probably fails, with the following error message:
error could not open output spool file /tmp/tmp.nnn
a critical system resource is inaccessible or exhausted
To prevent this error on a Sun workstation, enter the following operating system
command, before you start the simulation:
limit descriptors 128
For platforms other than Sun workstations, ask your system administrator to
help you increase the number of files that you can open concurrently.
Printing the Subcircuit Output
The following examples demonstrate how to print or plot voltages of nodes that
are in subcircuit definitions, using .PRINT, .PLOT,
.PROBE, or .GRAPH.
Note: In the following example, you can substitute .PROBE, .PLOT, or .GRAPH
instead of .PRINT. HSPICE RF does not support .PLOT or .GRAPH.
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Example 1
.GLOBAL vdd vss
X1 1 2 3 nor2
X2 3 4 5 nor2
.SUBCKT nor2 A B Y
.PRINT v(B) v(N1) $ Print statement 1
M1 N1 A vdd vdd pch w = 6u l = 0.8u
M2 Y B N1 vdd pch w = 6u l = 0.8u
M3 Y A vss vss vss nch w = 3u l = 0.8u
M4 Y B vss vss nch w = 3u l = 0.8u
.ENDS
Print statement 1 prints out the voltage on the B input node, and on the N1
internal node for every instance of the nor2 subcircuit.
.PRINT v(1) v(X1.A) $ Print statement 2
The preceding .PRINT statement specifies two ways to print the voltage on the
A input of the X1 instance.
.PRINT v(3) v(X1.Y)
v(X2.A) $ Print statement 3
The preceding .PRINT statement specifies three different ways to print the
voltage at the Y output of the X1 instance (or the A input of the X2 instance).
.PRINT v(X2.N1) $ Print statement 4
The preceding .PRINT statement prints the voltage on the N1 internal node of
the X2 instance.
.PRINT i(X1.M1) $ Print statement 5
The preceding .PRINT statement prints out the drain-to-source current,
through the M1 MOSFET in the X1 instance.
Example 2
X1 5 6 YYY
.SUBCKT YYY 15 16
X2 16 36 ZZZ
R1 15 25 1
R2 25 16 1
.ENDS
.SUBCKT ZZZ 16 36
C1 16 0 10P
R3 36 56 10K
C2 56 0 1P
.ENDS
.PRINT V(X1.25) V(X1.X2.56) V(6)
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Value
Description
V(X1.25)
Local node to the YYY subcircuit definition, which the X1 subcircuit
calls.
V(X1.X2.56)
Local node to the ZZZ subcircuit. The X2 subcircuit calls this node; X1
calls X2.
V(6)
Voltage of node 16, in the X1 instance of the YYY subcircuit.
This example prints voltage analysis results at node 56, within the X2 and X1
subcircuits. The full path, X1.X2.56, specifies that node 56 is within the X2
subcircuit, which in turn is within the X1 subcircuit.
Selecting Simulation Output Parameters
Parameters provide the appropriate simulation output. To define simulation
parameters, use the .OPTION and .MEASURE statements, and define specific
variable elements.
DC and Transient Output Variables
■
Voltage differences between specified nodes (or between one specified
node and ground).
■
Current output for an independent voltage source.
■
Current output for any element.
■
Current output for a subcircuit pin.
■
Element templates (HSPICE only; HSPICE RF does not support element
template output). For each device type, the templates contain:
•
values of variables that you set
•
state variables
•
element charges
•
capacitance currents
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•
capacitances
•
derivatives
Print Control Options on page 249 summarizes the codes that you can use, to
specify the element templates for output in HSPICE or HSPICE RF.
Nodal Capacitance Output
Syntax
Cap(nxxx)
For nodal capacitance output, HSPICE prints or plots the capacitance of the
specified node nxxxx.
Example
.print dc Cap(5) Cap(6)
Nodal Voltage
Syntax
V(n1<,n2>)
Parameter
Description
n1, n2
HSPICE or HSPICE RF prints or plots the voltage difference (n1-n2)
between the specified nodes. If you omit n2, HSPICE or HSPICE RF
prints or plots the voltage difference between n1 and ground (node 0).
Current: Independent Voltage Sources
Syntax
I(Vxxx)
252
Parameter
Description
Vxxx
Voltage source element name. If an independent power supply is
within a subcircuit, then to access its current output, append a dot and
the subcircuit name to the element name. For example, I(X1.Vxxx).
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Example
.PLOT TRAN I(VIN)
.PRINT DC I(X1.VSRC)
.PLOT DC I(XSUB.XSUBSUB.VY)
Current: Element Branches
Syntax
In(Wwww)
Iall(Wwww)
Parameter
Description
n
Node position number, in the element statement. For example, if the
element contains four nodes, I3 is the branch current output for the
third node. If you do not specify n, HSPICE or HSPICE RF assumes
the first node.
Wwww
Element name. To access current output for an element in a subcircuit,
append a dot and the subcircuit name to the element name. For
example, I3(X1.Wwww).
Iall (Wwww)
An alias just for diode, BJT, JFET, and MOSFET devices.
• If Wwww is a diode, it is equivalent to:
I1(Wwww) I2(Wwww).
• If Wwww is one of the other device types, it is equivalent to:
I1(Wwww) I2(Wwww) I3(Wwww) I4(Wwww)
Example 1
I1(R1)
This example specifies the current through the first R1 resistor node.
Example 2
I4(X1.M1)
This example specifies the current, through the fourth node (the substrate
node) of the M1 MOSFET, defined in the X1 subcircuit.
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Example 3
I2(Q1)
The last example specifies the current, through the second node (the base
node) of the Q1 bipolar transistor.
To define each branch circuit, use a single element statement. When HSPICE
or HSPICE RF evaluates branch currents, it inserts a zero-volt power supply, in
series with branch elements.
If HSPICE cannot interpret a .PRINT or .PLOT statement that contains a
branch current, it generates a warning.
Branch current direction for the elements in Figure 29 through Figure 34 is
defined in terms of arrow notation (current direction), and node position number
(terminal type).
Figure 29
Resistor (node1, node2)
I1 (R1)
node1
R1
I2 (R1)
Figure 30
node2
Inductor (node1, node2); capacitor (node 1, node2)
node1
I1(L1)
I1(C1)
I2(L1)
I2(C1)
node2
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Figure 31
Figure 32
Diode (node1, node2)
I1 (D1)
node1 (anode, P-type, + node)
I2 (D2)
node2 (anode, N-type, - node)
JFET (node1, node2, node3) - n-channel
node1 (drain node)
I1 (J1)
node2
(gate node)
I2 (J1)
Figure 33
node2 (source node)
I3 (J1)
MOSFET (node1, node2, node3, node4) - n-channel
node1 (drain node)
I1 (M1)
node2 (gate node)
node4 (substrate node)
I4 (M1)
I2 (M1)
node3 (source node)
I3 (M1)
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Figure 34
BJT (node1, node2, node3, node4) - npn
node1 (collector node)
I1 (Q1)
node2 (base node)
I2 (Q1)
node4 (substrate node)
I4 (Q1)
node3 (emitter node)
I3 (Q1)
Current: Subcircuit Pin
Syntax
ISUB(X****.****)
Example
.PROBE ISUB(X1.PIN1)
Power Output
For power calculations, HSPICE or HSPICE RF computes dissipated or stored
power in each passive element (R, L, C), and source (V, I, G, E, F, and H). To
compute this power, HSPICE or HSPICE RF multiplies the voltage across an
element, and its corresponding branch current.
However, for semiconductor devices, HSPICE or HSPICE RF calculates only
the dissipated power. It excludes the power stored in the device junction or
parasitic capacitances, from the device power computation. The following
sections show equations for calculating the power that different types of
devices dissipate.
HSPICE or HSPICE RF also computes the total power dissipated in the circuit,
which is the sum of the power dissipated in:
■
Devices
■
Resistors
■
Independent current sources
■
All dependent sources
For hierarchical designs, HSPICE or HSPICE RF also computes the power
dissipation for each subcircuit.
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Note: For the total power (dissipated power + stored power), HSPICE or
HSPICE RF does not add the power of each independent source (voltage
and current sources).
Print or Plot Power
Note: To output the instantaneous element power, and the total power
dissipation, use a .PRINT or .PLOT statement in HSPICE.HSPICE RF
does not support .PLOT statements or POWER variables in DC/transient
analysis.
.PRINT <DC | TRAN> P(element_or_subcircuit_name)POWER
HSPICE calculates power only for transient and DC sweep analyses. Use
the .MEASURE statement to compute the average, rms, minimum, maximum,
and peak-to-peak value of the power. The POWER keyword invokes the total
power dissipation output.
HSPICE RF supports p(instance) but not the POWER variable in DC/transient
analysis.
Example
.PRINT TRAN
P(M1)
P(VIN)
P(CLOAD)
POWER
.PRINT TRAN
P(Q1)
P(DIO)
P(J10)
POWER
.PRINT TRAN
POWER
$ Total transient analysis
* power dissipation
.PLOT DC POWER
P(IIN)
P(RLOAD)
P(R1)
.PLOT DC POWER
P(V1)
P(RLOAD)
P(VS)
.PRINT TRAN P(Xf1) P(Xf1.Xh1)
Diode Power Dissipation
Pd = Vpp' ⋅ ( Ido + Icap ) + Vp'n ⋅ Ido
Parameter
Description
Pd
Power dissipated in the diode.
Ido
DC component of the diode current.
Icap
Capacitive component of the diode current.
Vp'n
Voltage across the junction.
Vpp'
Voltage across the series resistance, RS.
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BJT Power Dissipation
■
Vertical
Pd = Vc'e' ⋅ Ico + Vb'e' ⋅ Ibo + Vcc' ⋅ Ictot + Vee' ⋅ Ietot + Vsc' ⋅ Iso – Vcc' ÞIstot
■
Lateral
Pd = Vc'e' ⋅ Ico + Vb'e' ⋅ Ibo + Vcc' ⋅ Ictot + Vbb' ⋅ Ibtot + Vee' ⋅ Ietot +
Vsb' ⋅ Iso – Vbb' ÞIstot
258
Parameter
Description
Ibo
DC component of the base current.
Ico
DC component of the collector current.
Iso
DC component of the substrate current.
Pd
Power dissipated in a BJT.
Ibtot
Total base current (excluding the substrate current).
Ictot
Total collector current (excluding the substrate current).
Ietot
Total emitter current.
Istot
Total substrate current.
Vb'e'
Voltage across the base-emitter junction.
Vbb'
Voltage across the series base resistance, RB.
Vc'e'
Voltage across the collector-emitter terminals.
Vcc'
Voltage across the series collector resistance, RC.
Vee'
Voltage across the series emitter resistance, RE.
Vsb'
Voltage across the substrate-base junction.
Vsc'
Voltage across the substrate-collector junction.
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JFET Power Dissipation
Pd = Vd's' ⋅ Ido + Vgd' ⋅ Igdo + Vgs' ⋅ Igso +
Vs's ⋅ ( Ido + Igso + Icgs ) + Vdd' ⋅ ( Ido – Igdo – Icgd )
Parameter
Description
Icgd
Capacitive component of the gate-drain junction current.
Icgs
Capacitive component of the gate-source junction current.
Ido
DC component of the drain current.
Igdo
DC component of the gate-drain junction current.
Igso
DC component of the gate-source junction current.
Pd
Power dissipated in a JFET.
Vd's'
Voltage across the internal drain-source terminals.
Vdd'
Voltage across the series drain resistance, RD.
Vgd'
Voltage across the gate-drain junction.
Vgs'
Voltage across the gate-source junction.
Vs's
Voltage across the series source resistance, RS.
MOSFET Power Dissipation
Pd = Vd's' ⋅ Ido + Vbd' ⋅ Ibdo + Vbs' ⋅ Ibso +
Vs's ⋅ ( Ido + Ibso + Icbs + Icgs ) + Vdd' ⋅ ( Ido – Ibdo – Icbd – Icgd )
Parameter
Description
Ibdo
DC component of the bulk-drain junction current.
Ibso
DC component of the bulk-source junction current.
Icbd
Capacitive component of the bulk-drain junction current.
Icbs
Capacitive component of the bulk-source junction current.
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Parameter
Description
Icgd
Capacitive component of the gate-drain current.
Icgs
Capacitive component of the gate-source current.
Ido
DC component of the drain current.
Pd
Power dissipated in the MOSFET.
Vbd'
Voltage across the bulk-drain junction.
Vbs'
Voltage across the bulk-source junction.
Vd's'
Voltage across the internal drain-source terminals.
Vdd'
Voltage across the series drain resistance, RD.
Vs's
Voltage across the series source resistance, RS.
AC Analysis Output Variables
Output variables for AC analysis include:
■
Voltage differences between specified nodes (or between one specified
node and ground).
■
Current output for an independent voltage source.
■
Current output for a subcircuit pin.
■
Element branch current.
■
Impedance (Z), admittance (Y), hybrid (H), and scattering (S) parameters.
■
Input and output impedance, and admittance.
Table 25 lists AC output variable types. In this table, the type symbol is
appended to the variable symbol, to form the output variable name. For
example, VI is the imaginary part of the voltage, or IM is the magnitude of the
current.
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Table 25 AC Output Variable Types
Type Symbol
Variable Type
DB
decibel
I
imaginary part
M
magnitude
P
phase
R
real part
T
group delay
Specify real or imaginary parts, magnitude, phase, decibels, and group delay
for voltages and currents.
Nodal Capacitance Output
Syntax
Cap(nxxx)
For nodal capacitance output, HSPICE prints or plots the capacitance of the
specified node nxxxx.
Example
.print ac Cap(5) Cap(6)
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Nodal Voltage
Syntax
Vz(n1<,n2>)
Parameter
Description
z
Specifies the voltage output type (see Table 25 on page 261)
n1, n2
Specifies node names. If you omit n2, HSPICE or HSPICE RF
assumes ground (node 0).
Example
.PLOT AC VM(5) VDB(5) VP(5)
The preceding example applies to HSPICE, but not HSPICE RF. It plots the
magnitude of the AC voltage of node 5, using the VM output variable. HSPICE
uses the VDB output variable to plot the voltage at node 5, and uses the VP
output variable to plot the phase of the nodal voltage at node 5.
To produce complex results, an AC analysis uses either the SPICE or HSPICE
method, and the .OPTION ACOUT control option, to calculate the values of
real or imaginary parts for complex voltages of AC analysis, and their
magnitude, phase, decibel, and group delay values. The default for HSPICE is
ACOUT = 1. To use the SPICE method, set ACOUT = 0.
A typical use of the SPICE method is to calculate the nodal vector difference,
when comparing adjacent nodes in a circuit. You can use this method to find
the phase or magnitude across a capacitor, inductor, or semiconductor device.
Use the HSPICE method to calculate an inter-stage gain in a circuit (such as an
amplifier circuit), and to compare its gain, phase, and magnitude.
The following examples define the AC analysis output variables for the HSPICE
method, and then for the SPICE method.
■
Real and imaginary:
VR(N1,N2) =
VI(N1,N2) =
262
REAL [V(N1,0)] - REAL [V(N2,0)]
IMAG [V(N1,0)] - IMAG [V(N2,0)]
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■
Magnitude:
VM(N1,0) = [VR(N1,0)2 + VI(N1,0)2]0.5
VM(N2,0) = [VR(N2,0)2 + VI(N2,0)2]0.5
VM(N1,N2) = VM(N1,0) - VM(N2,0)
■
Phase:
VP(N1,0) = ARCTAN[VI(N1,0)/VR(N1,0)]
VP(N2,0) = ARCTAN[VI(N2,0)/VR(N2,0)]
VP(N1,N2) = VP(N1,0) - VP(N2,0)
■
Decibel:
VDB(N1,0) = 20 ⋅ LOG10[VM(N1,0)]
VDB(N1,N2) = 20 ⋅ LOG10(VM(N1,0)/VM(N2,0))
SPICE Method Example:
■
Real and imaginary:
VR(N1,N2) = REAL [V(N1,0) - V(N2,0)]
VI(N1,N2) = IMAG [V(N1,0) - V(N2,0)]
■
Magnitude:
VM(N1,N2) = [VR(N1,N2)2+VI(N1,N2)2]0.5
■
Phase:
VP(N1,N2) = ARCTAN[VI(N1,N2)/VR(N1,N2)]
■
Decibel:
VDB(N1,N2) = 20 ⋅ LOG10[VM(N1,N2)]
Current: Independent Voltage Sources
Syntax
Iz(Vxxx)
Parameter
Description
z
Current output type (see Table 25 on page 261).
Vxxx
Voltage source element name. If an independent power supply is
within a subcircuit, then to access its current output, append a dot and
the subcircuit name to the element name. For example, IM(X1.Vxxx).
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Example
.PLOT AC IR(V1) IM(VN2B) IP(X1.X2.VSRC)
This example applies to HSPICE, but not to HSPICE RF.
Current: Element Branches
Syntax
Izn(Wwww)
Parameter
Description
z
Current output type (see Table 25 on page 261).
n
Node position number, in the element statement. For example, if the
element contains four nodes, IM3 denotes the magnitude of the branch
current output for the third node.
Wwww
Element name. If the element is within a subcircuit, then to access its
current output, append a dot and the subcircuit name to the element
name. For example, IM3(X1.Wwww).
.PRINT AC IP1(Q5) IM1(Q5) IDB4(X1.M1)
If you use the form In(Xxxx) for AC analysis output, then HSPICE or HSPICE
RF prints the magnitude value, IMn(Xxxx).
Current: Subcircuit Pin
Syntax
ISUB(X****.****)
Example
.PROBE ISUB(X1.PIN1)
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Group Time Delay
The TD group time delay is associated with AC analysis. TD is the negative
derivative of the phase in radians, with respect to radian frequency. HSPICE or
HSPICE RF uses the difference method to compute TD:
phase2 – phase1 -)
1 - ⋅ (----------------------------------------------TD = – -------( f2 – f1 )
360
phase1 and phase2 are the phases (in degrees) of the specified signal, at the
f1 and f2 frequencies (in hertz).
Syntax
.PRINT AC VT(10) VT(2,25) IT(RL)
.PLOT AC IT1(Q1) IT3(M15) IT(D1)
Note: Because the phase has a discontinuity every 360×, TD shows the same
discontinuity, even though TD is continuous. The .PRINT example applies to
both HSPICE and HSPICE RF, but the .PLOT example applies only to
HSPICE.
Example
INTEG.SP ACTIVE INTEGRATOR
****** INPUT LISTING
******
V1
1
0
.5
AC
1
R1
1
2
2K
C1
2
3
5NF
E3
3
0
2 0 -1000.0
.AC DEC
15
1K
100K
.PLOT AC
VT(3)
(0,4U)
.END
VP(3)
Network
Syntax
Xij (z), ZIN(z), ZOUT(z), YIN(z), YOUT(z)
Parameter
Description
X
Specifies Z (impedance), Y (admittance), H (hybrid), or S (scattering).
ij
i and j can be 1 or 2. They identify the matrix parameter to print.
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Parameter
Description
z
Output type (see Table 25 on page 261). If you omit z, HSPICE or
HSPICE RF prints the magnitude of the output variable.
ZIN
Input impedance. For a one-port network, ZIN, Z11, and H11 are the
same.
ZOUT
Output impedance.
YIN
Input admittance. For a one-port network, YIN and Y11 are the same.
YOUT
Output admittance.
Example
.PRINT
.PRINT
.PLOT
AC
AC
AC
Z11(R)
ZIN(R)
S22(M)
Z12(R)
ZIN(I)
S22(P)
Y21(I)
Y22
S11
S11(DB)
YOUT(M)
YOUT(P)
H11(M)
S21(R)
H21(P)
H12(R)
The .PRINT examples apply to both HSPICE and HSPICE RF. The .PLOT
example applies only to HSPICE.
Noise and Distortion
This section describes the variables used for noise and distortion analysis.
Syntax
ovar <(z)>
266
Parameter
Description
ovar
Noise and distortion analysis parameter. It can be ONOISE (output
noise), INOISE (equivalent input noise), or any of the distortion
analysis parameters (HD2, HD3, SIM2, DIM2, DIM3).
z
Output type (only for distortion). If you omit z, HSPICE or HSPICE RF
outputs the magnitude of the output variable.
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Example
.PRINT DISTO HD2(M) HD2(DB)
Prints the magnitude and decibel values of the second harmonic distortion
component, through the load resistor that you specified in the .DISTO
statement (not shown). You cannot use the .DISTO statement in HSPICE RF.
.PLOT NOISE INOISE ONOISE
Note: You can specify the noise and distortion output variable, and other AC
output variables, in the .PRINT AC or .PLOT AC statements. The .PRINT
example applies to both HSPICE and HSPICE RF. The .PLOT example
applies only to HSPICE.
Element Template Output
.PRINT, .PROBE (HSPICE and HSPICE RF), .PLOT, and .GRAPH (HSPICE
only) statements use element templates to output user-input parameters, state
variables, stored charges, capacitor currents, capacitances, and derivatives of
variables. Element templates are listed at the end of this chapter HSPICE RF
does not support element template output.
Syntax
Elname:Property
Parameter
Description
Elname
Name of the element.
Property
Property name of an element, such as a user-input parameter, state
variable, stored charge, capacitance current, capacitance, or
derivative of a variable.
The alias is:
LVnn(Elname)
LXnn(Elname)
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Parameter
Description
LV
Form to obtain output of user-input parameters, and state variables.
LX
Form to obtain output of stored charges, capacitor currents,
capacitances, and derivatives of variables.
nn
Code number for the desired parameter (listed in tables in this section).
Elname
Name of the element.
Example
.PLOT TRAN V(1,12) I(X2.VSIN) I2(Q3) DI01:GD
.PRINT TRAN X2.M1:CGGBO M1:CGDBO X2.M1:CGSBO
The .PRINT example applies to both HSPICE and HSPICE RF; the .PLOT
example applies to HSPICE only.
Specifying User-Defined Analysis (.MEASURE)
Use the .MEASURE statement to modify information, and to define the results of
successive HSPICE or HSPICE RF simulations.
Computing the measurement results is based on postprocessing output. If you
use the INTERP option to reduce the size of the postprocessing output, then
the measurement results can contain interpolation errors. See the HSPICE
Command Reference manual for more information about the INTERP option.
Fundamental measurement modes in HSPICE are:
268
■
Rise, fall, and delay
■
Find-when
■
Equation evaluation
■
Average, RMS, min, max, and peak-to-peak
■
Integral evaluation
■
Derivative evaluation
■
Relative error
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Specifying User-Defined Analysis (.MEASURE)
If a .MEASURE statement does not execute, then HSPICE or HSPICE RF
writes 0.0e0 in the .mt# file as the .MEASURE result, and writes FAILED in the
output listing file. Use .OPTION MEASFAIL to write results to the .mt#, .ms#,
or .ma# files. See the HSPICE Command Reference manual for information
about .OPTION MEASFAIL.
Note: Beginning with the 2004.03 release, the .mt# format consists of 72
characters in a line and fields that contain 16 characters each. The extra line
that existed in previous releases has been removed.
To control the output variables, listed in .MEASURE statements, use
the .PUTMEAS option. See the HSPICE Command Reference manual for more
information.
In versions of HSPICE before 2003.09, to automatically sort large numbers
of .MEASURE statements, you could use the .OPTION MEASSORT statement.
Starting in version 2003.09, this option is obsolete. Now the measure
performance is order-independent, and HSPICE ignores this option.
.MEASURE Statement Order
The .MEASURE statement matches the last analysis command in the netlist
before the .MEASURE statement.
Example
.tran 20p 1.0n sweep sigma -3 3 0.5
.tran 20p 1.0n sweep monte=20
.meas mover max v(2,1)
In this example, .meas matches the second .tran statement and generates
only one measure output file.
.MEASURE Parameter Types
You cannot use measurement parameter results that the .PARAM statements
in .SUBCKT blocks produce, outside of the subcircuit. That is, you cannot pass
any measurement parameters defined in .SUBCKT statements, as bottom-up
parameters in hierarchical designs.
Measurement parameter names must not conflict with standard parameter
names. HSPICE or HSPICE RF issues an error message, if it encounters a
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measurement parameter with the same name as a standard parameter
definition.
To prevent .MEASURE statement parameters from overwriting parameter values
in other statements, HSPICE or HSPICE RF keeps track of parameter types. If
you use the same parameter name in both a .MEASURE statement and
a .PARAM statement at the same hierarchical level, simulation terminates and
reports an error.
No error occurs if parameter assignments are at different hierarchical
levels. .PRINT statements that occur at different levels, do not print
hierarchical information for parameter name headings.
Example
In HSPICE RF simulation output, you cannot apply .MEASURE to waveforms
generated from another .MEASURE statement in a parameter sweep.
The following example illustrates how HSPICE or HSPICE RF handles
.MEASURE statement parameters.
...
.MEASURE tran length TRIG v(clk) VAL = 1.4
+ TD = 11ns RISE = 1 TARGv(neq) VAL = 1.4 TD = 11ns
+ RISE = 1
.SUBCKT path out in width = 0.9u length = 600u
+ rm1 in m1 m2mg w = 'width' l = 'length/6'
...
.ENDS
In the above listing, the length in the resistor statement:
rm1 in m1 m2mg w = 'width' l = 'length/6'
does not inherit its value from length in the .MEASURE statement:
.MEASURE tran length ...
because they are of different types.
The correct value of l in rm1 should be:
l = length/6 = 100u
The value should not be derived from a measured value in transient analysis.
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FIND and WHEN Functions
The FIND and WHEN functions of the .MEASURE statement specify to
measure:
■
Any independent variables (time, frequency, parameter).
■
Any dependent variables (voltage or current for example).
■
Derivative of a dependent variable, if a specific event occurs.
You can use these measure statements in unity gain frequency or phase
measurements. You can also use these statements to measure the time,
frequency, or any parameter value:
■
When two signals cross each other.
■
When a signal crosses a constant value.
The measurement starts after a specified time delay, TD. To find a specific
event, set RISE, FALL, or CROSS to a value (or parameter), or specify LAST for
the last event.
LAST is a reserved word; you cannot use it as a parameter name in the above
measure statements. For definitions of parameters of the measure statement,
see Displaying Simulation Results on page 244.
Equation Evaluation
Use the Equation Evaluation form of the .MEASURE statement to evaluate an
equation, that is a function of the results of previous .MEASURE statements.
The equation must not be a function of node voltages or branch currents.
The expression option is an arithmetic expression that uses results from
other prior .MEASURE statements. If equation or expression includes node
voltages or branch currents, Unexpected results may incur.
Average, RMS, MIN, MAX, INTEG, and PP
Average (AVG), RMS, MIN, MAX, and peak-to-peak (PP) measurement modes
report statistical functions of the output variable, rather than analysis values.
■
AVG calculates the area under an output variable, divided by the periods of
interest.
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■
RMS divides the square root of the area under the output variable square, by
the period of interest.
•
MIN reports the minimum value of the output function, over the specified
interval.
•
MAX reports the maximum value of the output function, over the
specified interval.
•
PP (peak-to-peak) reports the maximum value, minus the minimum
value, over the specified interval.
AVG, RMS, and INTEG have no meaning in a DC data sweep, so if you
use them, HSPICE or HSPICE RF issues a warning message.
INTEGRAL Function
The INTEGRAL function reports the integral of an output variable, over a
specified period.
DERIVATIVE Function
The DERIVATIVE function provides the derivative of:
■
An output variable, at a specified time or frequency.
■
Any sweep variable, depending on the type of analysis.
■
A specified output variable, when some specific event occurs.
In the HSPICE RF example below, the SLEW measurement provides the slope
of V(OUT) during the first time, when V(1) is 90% of VDD.
.MEAS TRAN SLEW DERIV V(OUT) WHEN V(1) = ‘0.90*VDD’
ERROR Function
The relative error function reports the relative difference between two output
variables. You can use this format in optimization and curve-fitting of measured
data. The relative error format specifies the variable to measure and calculate,
from the .PARAM variable. To calculate the relative error between the two,
HSPICE or HSPICE RF uses the ERR, ERR1, ERR2, or ERR3 function. With this
format, you can specify a group of parameters to vary, to match the calculated
value and the measured data.
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Error Equations
ERR
1. ERR sums the squares of (M-C)/max (M, MINVAL) for each point.
2. It then divides by the number of points.
3. Finally, it calculates the square root of the result.
•
M (meas_var) is the measured value of the device or circuit response.
•
C (calc_var) is the calculated value of the device or circuit response.
•
NPTS is the number of data points.
NPTS
1
ERR = --------------- ⋅
NPTS
∑
i=1
1/2
2
Mi – Ci
 ---------------------------------------------
 max (MINVAL,M i)
ERR1
ERR1 computes the relative error at each point. For NPTS points, HSPICE or
HSPICE RF calculates NPTS ERR1 error functions. For device
characterization, the ERR1 approach is more efficient than the other error
functions (ERR, ERR2, ERR3).
Mi – Ci
ERR1 i = --------------------------------------------- , i = 1,NPTS
max (MINVAL,M i)
HSPICE or HSPICE RF does not print out each calculated ERR1 value. When
you set the ERR1 option, HSPICE or HSPICE RF calculates an ERR value, as
follows:
1/2
NPTS
1
ERR = --------------- ⋅
NPTS
∑
ERR1 i2
i=1
ERR2
This option computes the absolute relative error, at each point. For NPTS
points, HSPICE or HSPICE RF calls NPTS error functions.
Mi – Ci
ERR2 i = --------------------------------------------- , i = 1,NPTS
max (MINVAL,M i)
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.SURGE Statement
The returned value printed for ERR2 is:
NPTS
1
ERR = --------------- ⋅
NPTS
∑
ERR2 i
i=1
ERR3
M
± log ------i
Ci
ERR3 i = ---------------------------------------------------------------- , i = 1,NPTS
log [ max (MINVAL, M i ) ]
The + and - signs correspond to a positive and negative M/C ratio.
Note: If the M measured value is less than MINVAL, HSPICE or HSPICE RF
uses MINVAL instead. If the absolute value of M is less than the IGNOR or
YMIN value, or greater than the YMAX value, the error calculation does not
consider this point.
.SURGE Statement
The .SURGE statement in HSPICE RF automatically detects and reports a
current surge that exceeds the specified surge tolerance. Surge current is the
current flowing into or out of a node to the lower sub-circuit hierarchy. HSPICE
does not use the .SURGE statement.
Syntax
.SURGE surge_threshold surge_width node1 < node2 .... noden >
Parameter
Description
surge_threshold
Defines the minimum absolute surge current.
surge_width
Defines the minimum duration of a surge.
nodex
Can be any valid node name, at the current or lower subcircuit
level.
The .SURGE statement reports any current surge that is greater than
surge_threshold for a duration of more than surge_width.
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Example
In the example below, the .SURGE statement detects any current surge that
has an absolute amplitude of more than 1mA, and that exceeds 100ns,
x(xm.x1.a), x(xm.x2.c), and x(xn.y).
.SUBCKT sa a b
...
.ENDS
.SUBCKT sb c d
...
.ENDS
.SUBCKT sx x y
x1 x y sa
x2 x a sb
.ENDS
xm 1 2 sx
xn 2 a sx
.SURGE 1mA 100ns xm.x1.a xm.x2.c xn.y
.CHECK Statements
The .CHECK statements in HSPICE RF offer the following instrumentation:
■
Setting Global Hi/Lo Levels
■
Slew, Rise, and Fall Conditions
■
Edge Timing Verification
■
Setup and Hold Verification
■
IR Drop Detection
The results of these statements appear in a file with an .err filename extension.
To prevent creating unwieldy files, HSPICE RF reports only the first 10
violations for a particular check, in the .err file.
Note: HSPICE does not support the .CHECK statement.
Setting Global Hi/Lo Levels
To globally set the desired high and low definitions for all .CHECK statements,
use the GLOBAL_LEVEL command.
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Syntax
.CHECK GLOBAL_LEVEL (hi lo hi_th lo_th)
Parameter
Description
hi
Value for logic high.
lo
Value for logic low.
hi_th
Is the minimum value considered high.
lo_th
Is the maximum value considered low.
These parameters can be either numbers or expressions, and hi_th and lo_th
can be either absolute values or percentages, if punctuated with the % symbol.
You can also locally set different logic levels for individual timing checks.
Example
The first example defines a logic high as 5 volts, and a logic low as 0 volts. A
voltage value as small as 4 volts is considered high, while a value up to 1 volt is
low.
.CHECK GLOBAL_LEVEL (5 0 4 1)
The second example illustrates an alternative definition for the first example:
.CHECK GLOBAL_LEVEL (5 0 80% 20%)
Slew, Rise, and Fall Conditions
276
■
To verify that a slew rate occurs within the specified window of time, use the
CHECK SLEW command.
■
To verify that a rise time occurs within the specified window of time, use the
CHECK RISE command.
■
To verify that a fall time occurs within the specified window of time, use the
CHECK FALL command.
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.CHECK Statements
Syntax
.CHECK SLEW (min
<(hi lo hi_th
.CHECK RISE (min
<(hi lo hi_th
.CHECK FALL (min
<(hi lo hi_th
max) node1 <node2 ...>
lo_th)>
max) node1 <node2 ...>
lo_th)>
max) node1 <node2 ...>
lo_th)>
Parameter
Description
min
Is the lower boundary for the time window.
max
Is the upper limit.
node1 <
node2 ... >
Is a list of all nodes to check.
Note: When you specify node names, you can use the wildcard character (*).
You can also use the hi, lo, hi_th, and lo_th parameters to set local logic
levels for each particular timing check.
Example
This example defines a window between 1.5 and 2.2 nanoseconds (ns) wide, in
which the va and vb signals must complete their rise transition. Values for hi, lo,
and the thresholds are defined in .CHECK GLOBAL_LEVEL, which is
described in the section Setting Global Hi/Lo Levels on page 275.
.CHECK RISE (1.5ns 2.2ns) va vb
Figure 35 illustrates this example.
Figure 35
RISE Time Example
HI
HI_thresh
LO_thresh
LO
1.5 ns < t < 2.2 ns
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.CHECK Statements
The next example sets the condition that a* nodes must have a slew rate
between (HI_thresh - LO_thresh)/3ns and (HI_thresh - LO_thresh)/1ns. If either
node has a slew rate greater than that defined in the .CHECK SLEW
statement, HSPICE RF reports the violation in the .err file.
.CHECK SLEW (1ns 3ns) a* (3.3 0 2.6 0.7)
The slew rate check in Figure 36 defines its own hi, lo, and corresponding
threshold values, as indicated by the four values after the node names.
Figure 36
SLEW Example
3.3
2.6
0.7
0.0
1ns < t < 3ns
Edge Timing Verification
The edge condition verifies that a triggering event provokes an appropriate
RISE or FALL action, within the specified time window.
Syntax
.CHECK EDGE (ref RISE|FALL min max RISE|FALL)
+ node1 < node2 ... > < (hi lo hi_th low_th) >
Parameter
Description
ref
Name of the reference signal.
min
Minimum time.
max
Maximum time.
node1 < node2 ... > List of nodes to which you apply the edge condition.
You can also use the hi, lo, hi_th, and lo_th parameters to set local logic levels
for each particular timing check.
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.CHECK Statements
Example
This example sets the condition that the rising action of the clock (clk) triggers
the falling edge of VOUTA within 1 to 3 ns, as shown in Figure 37:
.CHECK EDGE (clk RISE 1ns 3ns FALL) VOUTA
Values for hi, lo, and the thresholds are those defined in .CHECK
GLOBAL_LEVEL, which is described in the section Setting Global Hi/Lo Levels
on page 275.
Figure 37
EDGE Example
voutA
CLK
HI
HI_thresh
LO_thresh
LO
1ns < t < 3 ns
Setup and Hold Verification
Use the SETUP and HOLD statements to ensure that specified signals do not
switch for a specified period of time.
Syntax
.CHECK SETUP (ref RISE|FALL duration RISE|FALL) node1 \
+ < node2 ... > < (hi lo hi_th low_th) >
.CHECK HOLD (ref RISE|FALL duration RISE|FALL) node1 \
+ < node2 ... > < (hi lo hi_th low_th) >
Parameter
Description
ref
Reference or trigger signal.
node1 < node2 ... >
Specified nodes for which the SETUP or HOLD condition
applies.
For HOLD, duration is the minimum time required after the triggering event,
before the specified nodes can rise or fall.
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For SETUP, duration is the minimum time before the triggering event, during
which the specified nodes cannot rise or fall.
Example
This example specifies that v1 and v2 must not switch for 2 ns, before every
rising edge of nodeA.
.CHECK SETUP (nodeA RISE 2ns FALL) v1 v2
Figure 38
SETUP Example
nodeA
v1
HI
HI_thresh
LO_thresh
LO
t > = 2ns
The following example specifies that vin* (such as vin1, vin2, and so on), must
not switch for 2 ns, after every falling edge of nodeA.
.CHECK HOLD (nodeA FALL 2ns RISE) vin*
Figure 39
HOLD Example
vin*
nodeA
HI
HI_thresh
LO_thresh
LO
t > = 2ns
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IR Drop Detection
You can check that the IR drop does not exceed, or does not fall below, a
specified value for a specified duration.
Syntax
.CHECK IRDROP ( volt_val time ) node1 < node2 ... > \
+ < ( hi lo hi_th low_th ) >
Parameter
Description
volt_val
Is the limiting voltage value.
• A positive volt_val (voltage value) indicates ground bounce
checking.
• A negative volt_val denotes VDD drop.
duration
Is the maximum allowable time. If you set duration to 0, then
HSPICE RF reports every glitch that strays beyond the
specified volt_val.
node1 < node2 ... >
Are the specified nodes for which the IR drop checking applies.
Example
The example below specifies that v1 must not fall below -2 volts for any
duration exceeding 1 ns.
.CHECK IRDROP (-2 1ns) v1
Figure 40
IR Drop Example
v1
-2 volts
t < = 1ns
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DSPF Flow
DSPF Flow
DSPF (Detailed Standard Parasitic Format) is a standard output format for
parasitic extraction tools, such as Star-RC.
HSPICE RF can output simulation results in this format; HSPICE does not
support this format.
This section provides an overview of DSPF, describes how HSPICE RF uses a
DSPF file, introduces Selective DSPF Expansion, and details Multi-Threshold
Selective DSPF Expansion.
Note: HSPICE RF requires both a DSPF file and an ideal netlist.
Very large circuits generate very large DSPF files; this is when using one of the
two options described below can really improve performance.
To run the simulation, using DSPF expansion, include a SIM_DSPF option in
your ideal netlist. For example:
.OPTION SIM_DSPF = “add4.dspf”
This option maps parasitics of the DSPF file, into the hierarchical ideal netlist.
Example
$ models
.MODEL p pmos
.MODEL n nmos
.INCLUDE add4.dspf
.OPTION SIM_DSPF=“add4.dspf”
.VEC “dspf_adder.vec”
.TRAN 1n 5u
vdd vdd 0 3.3
.OPTION POST
.END
The SIM_DSPF option accelerates the simulation by more than 100%. Using
the SIM_LA option at the same time, further reduces the total CPU time:
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$ models
.MODEL p pmos
.MODEL n nmos
.INCLUDE add4.dspf
.OPTION SIM_DSPF=“add4.dspf”
.OPTION SIM_LA=PACT
.VEC “dspf_adder.vec”
.TRAN 1n 5u
vdd vdd 0 3.3
.OPTION POST
.END
To expand only active nodes, such as those that move, include the
SIM_DSPF_ACTIVE option in your netlist. For example:
.OPTION SIM_DSPF_ACTIVE = “active_net_filename”
This option is most effective when used with a large design—for example, over
5K transistors. Smaller designs lose some of the performance gain, due to
internal overhead processing.
When you have included the appropriate control option, run HSPICE RF, using
the ideal netlist.
The structure of a DSPF file is:
*|DSPF 1.0
*|DESIGN “demo”
*|Date “October 6, 1998”
...
.SUBCKT < name > < pins >
* Net Section
C1 ...
R1 ...
...
* Instance Section
...
.ENDS
Note: HSPICE RF supports only flat DSPF files; it ignores any hierarchy
statements, such as .SUBCKT and .x1.
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How HSPICE RF Uses a DSPF File
HSPICE RF requires both a DSPF file, and an ideal extracted netlist. DSPF
includes both a standard and a selective DSPF expansion flow.
To run simulation, using the standard DSPF expansion, include an .OPTION
SIM_DSPF statement in your netlist.
Example
.OPTION SIM_DSPF = “dspf_filename”
Figure 41
ideal.in
Generate DSPF Flow
parser
DSPF parser
simulation
DSPF
HSPICE RF expands all nets from the DSPF file unless a selective DSPF mode
is specified, in which case, see Figure 42.
Note: When you use this option, you can include multiple DSPF files.
SIM_DSPF_SCALER/SIM_DSPF_SCALEC
These options are supported to scale the resistance and the capacitance
values in the standard parasitic file for DSPF flow.
Syntax
.OPTION SIM_DSPF_SCALER = scaleR
.OPTION SIM_DSPF_SCALEC = scaleC
284
■
scaleR is the scale factor for resistances.
■
scaleC is the scale factor for capacitances.
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Selective DSPF Expansion
To invoke selective DSPF expansion, use the SIM_DSPF_ACTIVE option in
your HSPICE RF netlist. HSPICE does not support the DSPF format.
Syntax
.OPTION SIM_DSPF_ACTIVE = “active_net_filename”
If the active_net_filename file does not exist in the first run, no nets are
expanded. Active nets are added to the file as they are identified in the
subsequent transient simulation. A second run using the same file and option
causes only the nets listed in the active_net_filename file to be expanded. It is
possible that activity changes are due to timing changes caused by expansion
of the active nets. In this case, additional nets are listed in the
active_net_filename file and a warning is issued.
By default, a node is considered active if the voltage varies by more than 0.1 V.
You may change this value with the SIM_DSPF_VTOL option, described under
Multi-Threshold Selective DSPF Expansion on page 286.
HSPICE RF uses the active_net_filename file and the DSPF file, with the ideal
netlist, to expand only the active portions of the circuit. If a net is latent, then
HSPICE RF does not expand it, which saves memory and CPU time. Figure 42
on page 286 shows the selective DSPF flow.
Another option available for selective DSPF expansion is
SIM_DSPF_MAX_ITER.
Alternate Syntax
.OPTION SIM_DSPF_MAX_ITER = value
Default value = 1
In this syntax, value is the number of runs for the second pass.
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DSPF Flow
Figure 42
Selective DSPF Flow
ideal.in
parse
active_node
file
exists?
No
simulation
create
active_node file
Yes
DSPF parses
only “active”
nodes
simulation
update (add)
active_node file
Multi-Threshold Selective DSPF Expansion
For greater accuracy, you can specify multiple DSPF active thresholds.
Syntax
.OPTION SIM_DSPF_VTOL = “value | scope1 scope2 ... scopen
>”
In this syntax, value is the tolerance of voltage change and scopex can be a
subcircuit definition, which uses a prefix of @, or a subcircuit instance.
Example
The value should be relatively small, compared to the operating range of the
circuit, or smaller than SIM_V_SUPPLY. The first example sets the sensitivity
voltage to 0.01V. Subcircuit definition snsamp and the subcircuit instance xvco
have full parasitics, if their nodes move more than 0.01V during active nodes
generation. xand and xff are less sensitive than the default, indicating that they
are not sensitive to parasitics.
.OPTION SIM_DSPF_VTOL = “0.01 | @snsamp xvco”
.OPTION SIM_DSPF_VTOL = “0.25 | xand xff”
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Sample DSPF Flow
Figure 43 shows a sample verification flow that includes DSPF.
Figure 43
Verification Flow
HSPICE RF
extracted
netlist (spf)
Ideal
Netlist
HSPICE RF
DSPF flow
*.wdb
active nets files
Reusing Simulation Output as Input Stimuli
You can use the .STIM statement to reuse the results (output) of one
simulation, as input stimuli in a new simulation.
Note: .STIM is an abbreviation of .STIMULI. You can use either form to
specify this statement in HSPICE. HSPICE RF does not support this
statement.
The .STIM statement specifies:
■
Expected stimulus (PWL Source, DATA CARD, or VEC FILE).
■
Signals to transform.
■
Independent variables.
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One .STIM statement produces one corresponding output file.
Output Files
The .STIM statement generates the following output files:
Output File Type
Extension
PWL Source
.pwl$_tr#
The .STIM statement writes PWL source results to
output_file.pwl$_tr#. This output file results from a .STIM <tran>
pwl statement in the input file.
Data Card
.dat$_tr#, .dat$_ac#, or .dat$_sw#
The .STIM statement writes DATA Card results to
output_file.dat$_sw#, output_file.dat$_ac#, or
output_file.dat$_tr#. This output file is the result of a .stim <tran|
ac|dc> data statement in the input file.
Digital Vector File
.vec$_tr#
The .STIM statement writes Digital Vector File results to
output_file.vec$_tr#. This output file is the result of a .stim <tran>
vec statement in the input file.
Symbol
Description
tr | ac | sw
• tr = transient analysis.
• ac = AC analysis.
• sw = DC sweep analysis.
#
Either a sweep number, or a hard-copy file number. For a single sweep
run, the default number is 0.
$
Serial number of the current .STIM statement, within statements of
the same stimulus type (pwl, data, or vec).
$=0 ~ n-1 (n is the number of the .STIM statement of that type). The
initial $ value is 0.
For example, if you specify three .STIM pwl statements, HSPICE
generates three PWL output files, with the suffix names pwl0_tr#,
pwl1_tr#, and pwl2_tr#.
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.POWER Statement
The .POWER statement in HSPICE RF creates a table, which by default
contains these measurements for every signal specified:
■
AVG
■
RMS
■
MAX
■
MIN
By default, the scope of this measurement is set from zero, to the maximum
time point specified in the .TRAN statement.
Note: HSPICE does not support this statement.
Syntax
.POWER <signals> <REF = vname FROM = start_time
+ TO = end_time>
Example
.power x1.in
.tran 4ps 100ps
In this example, no simulation start and stop time is specified for the x1.in
signal, so the simulation scope for this signal runs from the start (0ps) to the
last .tran time (100ps).
You can use the FROM and TO times to specify a separate measurement start
and stop time for each signal:
.param myendtime=80ps
.power x2.in REF = a123 from=20ps to=80ps
.power x0.in REF = abc from=30ps to=’myendtime - 10ps’
In this example:
■
The scope for simulating the x2.in signal is from 20 ps to 80 ps.
■
The scope for simulating the x0.in signal is from 30 ps to 70 ps.
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SIM_POWERSTART and SIM_POWERSTOP Options
You can also use the SIM_POWERSTART and SIM_POWERSTOP options
with the .POWER statement, to specify default start and stop times for
measuring signals during simulation. These default times apply to all signals
that do not have their own defined FROM and TO measurement times.
Syntax
.OPTION SIM_POWERSTART = < time >
.OPTION SIM_POWERSTOP = < time >
These options control the power measurement scope; the default is for the
entire run.
Example
.OPTION SIM_POWERSTART = 10ps
.OPTION SIM_POWERSTOP = 90ps
.power x1.in
In this example, the scope for simulating the x1.in signal is from 10
picoseconds (ps) to 90 ps.
SIM_POWERPOST Option
Syntax
.OPTION SIM_POWERPOST = ON|OFF
Considering the potentially enormous number of signals, there will be no
waveform dumping by default for the signals in the .POWER statement. Setting
SIM_POWERPOST to ON turns on power analysis.
POWER_TOP Option
Syntax
POWER_TOP = < value >
By default, power analysis is performed on the top levels of hierarchy. By
applying the POWER_TOP option, you can control the number of hierarchy
levels for power analysis.
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Example
In the example below, HSPICE RF produces .POWER statement results for
top-level and first-level subcircuits, that is, the children subcircuits of the toplevel subcircuits.
.OPTION POWER_TOP = 2
POWER_ANALYSIS Option
When using the POWER_ANALYSIS option, HSPICE RF traverses down all
hierarchies and prints node(s) specified in the .POWER statement with larger
port current than threshold current.
Syntax
.OPTION POWER_ANALYSIS = “< time point > < tol >”
.OPTION POWER_ANALYSIS = “bottom < time point > < tol >”
These two options do not return tabulated data, but do provide a list of signals
that match the tolerance setting. The first POWER_ANALYSIS option produces
a list of signals that consume more current than tol at time point, in this format:
*** time = < time point > threshold = < tol > ***
VDD = value
X13.VDD = value
X13.X1.VDD = value
X14.VDD = value
X14.X1.VDD = value
The second POWER_ANALYSIS option produces the list of lowest-level
signals, known as leaf subcircuits, that consume more than tol at time point.
Output is similar to this:
*** time = < time point > threshold = < tol > ***
X13.X1.VDD = value
X14.X1.VDD = value
Example
The POWER_ANALYSIS and .POWER statements print the names of leaf
subcircuits that use more than 100uA at 100ns into the simulation into the
output format.
.OPTION POWER_ANALYSIS = “ bottom 100ns 100ua ”
.POWER VDD
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Output Format
Power analysis, using the .POWER statement, creates a table that can be read
by any spreadsheet to post-process the data.
Table 26
Port
Name
.POWER Table Header
Sig#
Definition
Parent
DepthUp
DepthDn
Max
(A)
Min
(A)
RMS
(A)
Avg
(A)
Tabulated data increases your analysis capability; based on the data generated
in this format, you could analyze:
■
Sub-circuits that consume maximum amount of power.
■
Leaf-nodes that consume maximum amount of power.
■
Parent’s power
To derive the MAX sub-block, use Depth-Up as primary key, and Avg(A) as
secondary key, when sorting data.
Table 27
.POWER Output Example 1
Port
Name
Sig#
Definition
Parent
DepthUp
DepthDn
Max
(A)
Min
(A)
RMS
(A)
Avg
(A)
vdd
2
“”
-1
0
2
..
..
..
9
xa.vdd
6
“buf”
2
1
1
..
..
..
5
xb.vdd
14
“inv”
2
1
0
..
..
..
4
xa.x2.v
dd
10
“inv”
6
2
0
..
..
..
3
xa.x1.v
dd
8
“inv”
6
2
0
..
..
..
2
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Example
The MAX leaf node could be derived by sorting data, using Depth-Dn as
primary key, and Avg(A) as secondary key.
Table 28
.POWER Output Example 2
Port
Name
Sig#
Definition
Parent
DepthUp
DepthDn
Max
(A)
Min
(A)
RMS
(A)
Avg
(A)
xb.vdd
14
“inv”
2
1
0
..
..
..
4
xa.x2.v
dd
10
“inv”
6
2
0
..
..
..
3
xa.x1.v
dd
8
“inv”
6
2
0
..
..
..
2
xa.vdd
6
“buf”
2
1
1
..
..
..
5
vdd
2
“”
-1
0
2
..
..
..
9
To find the Parent’s power, search the corresponding parent’s ID. For example,
xa.x2.vdd has a parent ID of 6: find the signal with ID 6 that consumes 5 units
of average power
Table 29
.POWER Output Example 3
Port
Name
Sig#
Definition
Parent
DepthUp
DepthDn
Max
(A)
Min
(A)
RMS
(A)
Avg
(A)
xb.vdd
14
“inv”
2
1
0
..
..
..
4
xa.x2.v
dd
10
“inv”
6
2
0
..
..
..
3
xa.x1.v
dd
8
“inv”
6
2
0
..
..
..
2
xa.vdd
6
“buf”
2
1
1
..
..
..
5
vdd
2
“”
-1
0
2
..
..
..
9
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.POWERDC Statement
.POWERDC Statement
The .POWERDC (standby current) statement calculates the DC leakage
current in the design hierarchy. It creates a table that lists the measurements of
the AVG, MAX, and MIN values for the current of every instance in the
subcircuit. This table also specifies the sum of the power of each port in the
subcircuit.
Note: HSPICE RF supports .POWERDC only in HSPICE mode.
Syntax
.POWERDC <keyword> <subckt_name1...>
■
keyword is either of the following:
•
TOP prints the power of all the top level instances.
•
ALL prints the power of all the instances.
Note: If you do not specify a keyword, the default is ALL.
■
subckt_name# prints the power of all instances in this subcircuit definition.
Note: You can use wildcards in the subcircuit definitions.
To increase the accuracy of operating point (OP) calculations, set:
.opt sim_powerdc_hspice
For even higher accuracy in OP calculations, set:
.opt sim_powerdc_accuracy=value
This sim_powerdc_accuracy setting has the same effect as the accuracy
setting for transient analysis. A higher value means greater accuracy, but more
time before the calculation completes.
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.POWERDC Statement
Output Format
*** Leakage Current Result ***
Subckt Name = XXX
Instance Name
Port
Max(A)
Min(A)
Avg(A)
.....
Total Power
Max(W)
Min(W)
Avg(W)
NOTE:
Power = Sum{Ii * Vi}
Subckt Name = XXX
Instance Name
Port
Max(A)
Min(A)
Avg(A)
.....
Total Power
Max(W)
Min(W)
Avg(W)
Example
.global vdd vss
.powerdc all
x1 in1 mid1 inv
x2 mid1 out1 inv
.subckt inv in out
mn out in vss vss nch
mp vdd in out vdd pch
.ends
.end
(Output)
*** Leakage Current Result ***
Subckt Name = Top Level
Instance Name
Port
Max(A)
x1
in
.......
x1
out
.......
x2
in
.......
x2
out
.......
Total Power
.......
Subckt Name = inv
Instance Name
Port
Max(A)
mn
d
.......
mn
g
.......
mn
s
.......
mn
b
.......
mp
d
.......
mp
g
.......
mp
s
.......
mp
b
.......
Total Power
.......
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Avg(A)
Min(A)
Avg(A)
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Element Template Listings
Element Template Listings
This section applies only to HSPICE. HSPICE RF does not support element
template output. HSPICE RF Output File Format
Table 30 Resistor
Name
Alias
Description
G
LV1
Conductance at analysis temperature.
R
LV2
Resistance at analysis temperature.
TC1
LV3
First temperature coefficient.
TC2
LV4
Second temperature coefficient.
Table 31 Capacitor
Name
Alias
Description
CEFF
LV1
Computed effective capacitance.
IC
LV2
Initial condition.
Q
LX0
Charge, stored in capacitor.
CURR
LX1
Current, flowing through capacitor.
VOLT
LX2
Voltage, across capacitor.
–
LX3
Capacitance (not used after HSPICE releases after
95.3).
Table 32 Inductor
296
Name
Alias
Description
LEFF
LV1
Computed effective inductance.
IC
LV2
Initial condition.
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Table 32 Inductor (Continued)
Name
Alias
Description
FLUX
LX0
Flux, in the inductor.
VOLT
LX1
Voltage, across inductor.
CURR
LX2
Current, flowing through inductor.
–
LX4
Inductance (not used after HSPICE releases after 95.3).
Table 33 Mutual Inductor
Name
Alias
Description
K
LV1
Mutual inductance.
Table 34 Voltage-Controlled Current Source (G Element)
Name
Alias
Description
CURR
LX0
Current, through the source, if VCCS.
R
LX0
Resistance value, if VCR.
C
LX0
Capacitance value, if VCCAP.
CV
LX1
Controlling voltage.
CQ
LX1
Capacitance charge, if VCCAP.
DI
LX2
Derivative of the source current, relative to the control
voltage.
ICAP
LX2
Capacitance current, if VCCAP.
VCAP
LX3
Voltage, across capacitance, if VCCAP.
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Table 35 Voltage-Controlled Voltage Source (E Element)
Name
Alias
Description
VOLT
LX0
Source voltage.
CURR
LX1
Current, through source.
CV
LX2
Controlling voltage.
DV
LX3
Derivative of the source voltage, relative to the control
current.
Table 36 Current-Controlled Current Source (F Element)
Name
Alias
Description
CURR
LX0
Current, through source.
CI
LX1
Controlling current.
DI
LX2
Derivative of the source current, relative to the control
current.
Table 37 Current-Controlled Voltage Source (H Element)
298
Name
Alias
Description
VOLT
LX0
Source voltage.
CURR
LX1
Source current.
CI
LX2
Controlling current.
DV
LX3
Derivative of the source voltage, relative to the control
current.
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Table 38 Independent Voltage Source
Name
Alias
Description
VOLT
LV1
DC/transient voltage.
VOLTM
LV2
AC voltage magnitude.
VOLTP
LV3
AC voltage phase.
Table 39 Independent Current Source
Name
Alias
Description
CURR
LV1
DC/transient current.
CURRM
LV2
AC current magnitude.
CURRP
LV3
AC current phase.
Table 40 Diode
Name
Alias
Description
AREA
LV1
Diode area factor.
AREAX
LV23
Area, after scaling.
IC
LV2
Initial voltage, across diode.
VD
LX0
Voltage, across diode (VD), excluding RS (series
resistance).
IDC
LX1
DC current, through diode (ID), excluding RS. Total diode
current is the sum of IDC and ICAP.
GD
LX2
Equivalent conductance (GD).
QD
LX3
Charge of diode capacitor (QD).
ICAP
LX4
Current, through the diode capacitor.
Total diode current is the sum of IDC and ICAP.
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Table 40 Diode (Continued)
Name
Alias
Description
C
LX5
Total diode capacitance.
PID
LX7
Photo current, in diode.
Table 41 BJT
300
Name
Alias
Description
AREA
LV1
Area factor.
ICVBE
LV2
Initial condition for base-emitter voltage (VBE).
ICVCE
LV3
Initial condition for collector-emitter voltage (VCE).
MULT
LV4
Number of multiple BJTs.
FT
LV5
FT (Unity gain bandwidth).
ISUB
LV6
Substrate current.
GSUB
LV7
Substrate conductance.
LOGIC
LV8
LOG 10 (IC).
LOGIB
LV9
LOG 10 (IB).
BETA
LV10
BETA.
LOGBETAI
LV11
LOG 10 (BETA) current.
ICTOL
LV12
Collector current tolerance.
IBTOL
LV13
Base current tolerance.
RB
LV14
Base resistance.
GRE
LV15
Emitter conductance, 1/RE.
GRC
LV16
Collector conductance, 1/RC.
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Table 41 BJT (Continued)
Name
Alias
Description
PIBC
LV18
Photo current, base-collector.
PIBE
LV19
Photo current, base-emitter.
VBE
LX0
VBE.
VBC
LX1
Base-collector voltage (VBC).
CCO
LX2
Collector current (CCO).
CBO
LX3
Base current (CBO).
GPI
LX4
gπ = ¹ib /¹vbe, constant vbc.
GU
LX5
gµ = ¹ib /¹vbc, constant vbe.
GM
LX6
gm = ¹ic /¹vbe+ ¹ic /¹vbe, constant vce.
G0
LX7
g0 = ¹ic /¹vce, constant vbe.
QBE
LX8
Base-emitter charge (QBE).
CQBE
LX9
Base-emitter charge current (CQBE).
QBC
LX10
Base-collector charge (QBC).
CQBC
LX11
Base-collector charge current (CQBC).
QCS
LX12
Current-substrate charge (QCS).
CQCS
LX13
Current-substrate charge current (CQCS).
QBX
LX14
Base-internal base charge (QBX).
CQBX
LX15
Base-internal base charge current (CQBX).
GXO
LX16
1/Rbeff Internal conductance (GXO).
CEXBC
LX17
Base-collector equivalent current (CEXBC).
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Table 41 BJT (Continued)
Name
Alias
Description
–
LX18
Base-collector conductance (GEQCBO), (not used in
HSPICE releases after 95.3).
CAP_BE
LX19
cbe capacitance (Cπ).
CAP_IBC
LX20
cbc internal base-collector capacitance (Cµ).
CAP_SCB
LX21
csc substrate-collector capacitance for vertical transistors.
csb substrate-base capacitance for lateral transistors.
CAP_XBC
LX22
cbcx external base-collector capacitance.
CMCMO
LX23
¹(TF*IBE) /¹vbc.
VSUB
LX24
Substrate voltage.
Table 42 JFET
302
Name
Alias
Description
AREA
LV1
JFET area factor.
VDS
LV2
Initial condition for drain-source voltage.
VGS
LV3
Initial condition for gate-source voltage.
PIGD
LV16
Photo current, gate-drain in JFET.
PIGS
LV17
Photo current, gate-source in JFET.
VGS
LX0
VGS.
VGD
LX1
Gate-drain voltage (VGD).
CGSO
LX2
Gate-to-source (CGSO).
CDO
LX3
Drain current (CDO).
CGDO
LX4
Gate-to-drain current (CGDO).
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Element Template Listings
Table 42 JFET (Continued)
Name
Alias
Description
GMO
LX5
Transconductance (GMO).
GDSO
LX6
Drain-source transconductance (GDSO).
GGSO
LX7
Gate-source transconductance (GGSO).
GGDO
LX8
Gate-drain transconductance (GGDO).
QGS
LX9
Gate-source charge (QGS).
CQGS
LX10
Gate-source charge current (CQGS).
QGD
LX11
Gate-drain charge (QGD).
CQGD
LX12
Gate-drain charge current (CQGD).
CAP_GS
LX13
Gate-source capacitance.
CAP_GD
LX14
Gate-drain capacitance.
–
LX15
Body-source voltage (not used after HSPICE release
95.3).
QDS
LX16
Drain-source charge (QDS).
CQDS
LX17
Drain-source charge current (CQDS).
GMBS
LX18
Drain-body (backgate) transconductance (GMBS).
Table 43 MOSFET
Name
Alias
Description
L
LV1
Channel length (L).
W
LV2
Channel width (W).
AD
LV3
Area of the drain diode (AD).
AS
LV4
Area of the source diode (AS).
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Table 43 MOSFET (Continued)
Name
Alias
Description
ICVDS
LV5
Initial condition for drain-source voltage (VDS).
ICVGS
LV6
Initial condition for gate-source voltage (VGS).
ICVBS
LV7
Initial condition for bulk-source voltage (VBS).
–
LV8
Device polarity:
• 1 = forward
• -1 = reverse (not used after HSPICE releases after
95.3).
304
VTH
LV9
Threshold voltage (bias dependent).
VDSAT
LV10
Saturation voltage (VDSAT).
PD
LV11
Drain diode periphery (PD).
PS
LV12
Source diode periphery (PS).
RDS
LV13
Drain resistance (squares), (RDS).
RSS
LV14
Source resistance (squares), (RSS).
XQC
LV15
Charge-sharing coefficient (XQC).
GDEFF
LV16
Effective drain conductance (1/RDeff).
GSEFF
LV17
Effective source conductance (1/RSeff).
CDSAT
LV18
Drain-bulk saturation current, at -1 volt bias.
CSSAT
LV19
Source-bulk saturation current, at -1 volt bias.
VDBEFF
LV20
Effective drain bulk voltage.
BETAEFF
LV21
BETA, effective.
GAMMAEFF
LV22
GAMMA, effective.
DELTAL
LV23
∆L (MOS6 amount of channel length modulation), (valid
only for LEVELs 1, 2, 3 and 6).
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Element Template Listings
Table 43 MOSFET (Continued)
Name
Alias
Description
UBEFF
LV24
UB effective (valid only for LEVELs 1, 2, 3 and 6).
VG
LV25
VG drive (valid only for LEVELs 1, 2, 3 and 6).
VFBEFF
LV26
VFB effective.
–
LV31
Drain current tolerance (not used in HSPICE releases
after 95.3).
IDSTOL
LV32
Source-diode current tolerance.
IDDTOL
LV33
Drain-diode current tolerance.
COVLGS
LV36
Gate-source overlap capacitance.
COVLGD
LV37
Gate-drain overlap capacitance.
COVLGB
LV38
Gate-bulk overlap capacitance.
VBS
LX1
Bulk-source voltage (VBS).
VGS
LX2
Gate-source voltage (VGS).
VDS
LX3
Drain-source voltage (VDS).
CDO
LX4
DC-drain current (CDO).
CBSO
LX5
DC source-bulk diode current (CBSO).
CBDO
LX6
DC drain-bulk diode current (CBDO).
GMO
LX7
DC-gate transconductance (GMO).
GDSO
LX8
DC drain-source conductance (GDSO).
GMBSO
LX9
DC-substrate transconductance (GMBSO).
GBDO
LX10
Conductance of the drain diode (GBDO).
GBSO
LX11
Conductance of the source diode (GBSO).
Meyer and Charge Conservation Model Parameters
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Element Template Listings
Table 43 MOSFET (Continued)
306
Name
Alias
Description
QB
LX12
Bulk charge (QB).
CQB
LX13
Bulk-charge current (CQB).
QG
LX14
Gate charge (QG).
CQG
LX15
Gate-charge current (CQG).
QD
LX16
Channel charge (QD).
CQD
LX17
Channel-charge current (CQD).
CGGBO
LX18
CGGBO = ∂Qg/ ∂Vgb = CGS + CGD + CGB
CGDBO
LX19
CGDBO = ∂Qg/ ∂Vdb , (for Meyer CGD = -CGDBO)
CGSBO
LX20
CGSBO = ∂Qg/ ∂Vsb , (for Meyer CGS = -CGSBO)
CBGBO
LX21
CBGBO = ∂Qb/ ∂Vgb , (for Meyer CGB = -CBGBO)
CBDBO
LX22
CBDBO = ∂Qb/ ∂Vdb
CBSBO
LX23
CBSBO = ∂Qb/ ∂Vsb
QBD
LX24
Drain-bulk charge (QBD).
–
LX25
Drain-bulk charge current (CQBD), (not used in HSPICE
releases after 95.3).
QBS
LX26
Source-bulk charge (QBS).
–
LX27
Source-bulk charge current (CQBS), (not used after
HSPICE releases after 95.3).
CAP_BS
LX28
Bulk-source capacitance.
CAP_BD
LX29
Bulk-drain capacitance.
CQS
LX31
Channel-charge current (CQS).
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Element Template Listings
Table 43 MOSFET (Continued)
Name
Alias
Description
CDGBO
LX32
CDGBO = ∂Qd/ ∂Vgb
CDDBO
LX33
CDDBO = ∂Qd/ ∂Vdb
CDSBO
LX34
CDSBO = ∂Qd/ ∂Vsb
Table 44 Saturable Core Element
Name
Alias
Description
MU
LX0
Dynamic permeability (mu), Weber/(amp-turn-meter).
H
LX1
Magnetizing force (H), Ampere-turns/meter.
B
LX2
Magnetic flux density (B), Webers/meter2.
Table 45 Saturable Core Winding
Name
Alias
Description
LEFF
LV1
Effective winding inductance (Henry).
IC
LV2
Initial condition.
FLUX
LX0
Flux, through winding (Weber-turn).
VOLT
LX1
Voltage, across winding (Volt).
HSPICE RF supports the output formats in this section:
■
Analog Compression
■
Tabulated Data Output
■
WDB Output Format
■
XP Output Format
■
NW Output Format
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Element Template Listings
■
VCD Output Format
■
Turbowave Output Format
■
Undertow Output Format
■
.GEN Output Format
If your netlist includes an unsupported output format, HSPICE RF prints a
warning message, indicating that the selected format is not supported. HSPICE
RF then defaults the output to WDB format.
You can use the waveform viewer to view certain output formats:
■
WDB#: XP/Cosmos Scope (Recommended)
■
NW#: XP/Avanwaves
■
XP#: XP/Avanwaves/Cosmos Scope
Note: If the waveform file is larger than 2GB, use split waveforms.
Analog Compression
Analog compression eliminates unnecessary data points from a HSPICE RF
voltage or current waveform, to reduce the size of the waveform file.
SIM_DELTAV (Voltage)
To determine the selection criteria for HSPICE RF voltage waveforms in the
WDB or NW format, set a SIM_DELTAV value. During simulation, HSPICE RF
checks whether the value of the X signal at the n timestep changes by more
than the SIM_DELTAV option, from its previous value at the n-1 timestep.
■
If yes, then HSPICE RF saves the new data point.
■
Otherwise, this new data point is lost.
Typically such an algorithm yields a reduced file size, with minimal resolution
loss, as long as you set an appropriate SIM_DELTAV value. If a value for the
SIM_DELTAV option is too large, the waveform degrades.
308
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Element Template Listings
Figure 44
Analog Compression Formats
NW retains these data
points that are ON the line,
plotting 3 segments. But
NW and WDB both eliminate these data points,
WDB eliminates these data
which are within DELTAV or DELTAI of the previous points, plotting only ONE
data point, and are not ON the plotted waveform line. segment for this line.
Example
In the following example, at the n timestep, HSPICE RF saves only datapoints
that change by more than 1 millivolt (the default), from their previous values at
the n-1 timestep.
.OPTION SIM_DELTAV = 1mv
SIM_DELTAI (Current)
You can also specify selective storage on HSPICE RF current waveforms in the
WDB or NW format, using SIM_DELTAI.
In the following example, at the n timestep, HSPICE RF saves only datapoints
that change by more than 0 amps (the default), from their previous values at the
n-1 timestep.
.OPTION SIM_DELTAI = 0amps
Tabulated Data Output
HSPICE RF outputs all analog waveforms that you specified in the .PRINT
statements. HSPICE RF saves these waveforms as ASCII tabulated data, into
a file with the .PRINT extension.
To display waveforms graphically, Cosmos-Scope can directly read the
tabulated data. For more information about Cosmos-Scope, see the CosmosScope User’s and Reference Manual.
Note: Tabulated data excludes waveforms specified in .PROBE statements.
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Element Template Listings
WDB Output Format
Waveform database (WDB) output is the default format for the POST option. It
was developed for maximum efficiency. The output file is *.wdb0.
Signals across multiple hierarchies, that map to the same node, are named
together. They also share the same waveform data.
You can also set-up the database, so that Cosmos-Scope extracts one signal at
a time. This means that Cosmos-Scope does not need to read the entire output
files, to display a single waveform.
Example
.OPTION POST = wdba
The WDB format was designed to make accessing waveform data faster and
more efficient. It is a true database, so the waveform browser does not have to
load the complete waveform file for you to view a single signal. This feature is
especially useful if the size of the waveform file is several gigabytes.
Furthermore, the WDB format is more compact than XP and NW, which are
described later in this section. However, if the NW file is already very small,
then WDB offers little advantage in size or speed.
XP Output Format
HSPICE RF outputs the XP binary format to a file with the .xp# extension. This
format is compatible with the HSPICE tr# binary format.
The syntax to output a *.xp# file in XP format is:
.OPTION POST = xp
NW Output Format
HSPICE RF outputs the NW format to a file with the extension
.nw#. This format was developed by Synopsys, so you need the AvanWaves
waveform display tool to process a file in NW format.
The syntax to output a *.nw# file in NW format is:
.OPTION POST = nw
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Limiting Output Data Size in HSPICE RF
VCD Output Format
To output your waveforms in VCD (Value Change Dump) format, set the VCD
option, in conjunction with the .LPRINT statement.
.OPTION VCD
.LPRINT (0.5 4.5) v(0) v(2) v(6)
Turbowave Output Format
To use Turbowave output format:
.OPTION POST=tw
This format supports analog compression, as described in Analog
Compression on page 308.
Undertow Output Format
To use Veritools Undertow output format:
.OPTION POST=ut
Limiting Output Data Size in HSPICE RF
For multi-million transistor simulations, an unrestricted waveform file can grow
to several gigabytes in size. The file becomes unreadable in some waveform
viewers, and requires excessive space on the hard drive.
This section describes options that limit the number of nodes output to the
waveform file, to reduced the file size. HSPICE RF supports the following
options to control the output:
■
SIM_POSTTOP Option
■
SIM_POSTSKIP Option
■
SIM_POSTAT Option
■
SIM_POSTDOWN Option
■
SIM_POSTSCOPE Option
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Limiting Output Data Size in HSPICE RF
SIM_POSTTOP Option
The SIM_POSTTOP option limits the data written to your waveform file, to data
from only the top n level nodes.
Note: To enable the waveform display interface, you also need the POST
option.
Example
.OPTION SIM_POSTTOP = n
■
Default value = 3
■
This syntax outputs instances from up to n levels deep.
■
SIM_POSTTOP = 1 specifies to output only the top-level signals.
■
If you specify the PROBE option, without the SIM_POSTTOP option, then
HSPICE RF sets the SIM_POSTTOP = 0.
■
If you do not specify either the PROBE or the SIM_POSTTOP option, then
HSPICE RF outputs all levels.
SIM_POSTSKIP Option
This option specifies that SIM_POSTTOP should skip any instances, and their
children, that the subckt_definition defines. To specify more than one definition,
use this option once for each definition to skip.
Syntax
.OPTION SIM_POSTSKIP = subckt_definition
SIM_POSTAT Option
The SIM_POSTAT option limits the waveform output to only the nodes in the
specified subcircuit instance.
312
■
This option has precedence over SIM_POSTSKIP.
■
You can use this option in conjunction with SIM_POSTTOP.
■
To specify multiple instances, you can either use wildcards, or set the option
multiple times.
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Syntax
.OPTION SIM_POSTAT = instance
This syntax includes an instance in the output.
SIM_POSTDOWN Option
This option includes an instance, and all children of that instance, in the output.
SIM_POSTDOWN is identical to SIM_POSTAT, except that SIM_POSTDOWN
includes all children of the specified level.
Syntax
.OPTION SIM_POSTDOWN = instance
SIM_POSTSCOPE Option
Use this option to specify the signals to probe, from within a scope.
Syntax
.OPTION SIM_POSTSCOPE = net|port|all
■
Default value = net
■
net indicates to output only nets in the scope.
■
port indicates to output both nets and ports.
■
all indicates to output nets, ports, and global variables.
Examples
Refer to Figure on page 314 when you examine the following examples.
■
This example specifies to output all nets:
.OPTION POST
■
This example outputs top, X1, and X2:
.OPTION SIM_POSTTOP = 2
■
This example outputs top, and skips X2. X1, because it is an instance of the
ADD sub-circuit:
.OPTION SIM_POSTTOP = 2
.OPTION SIM_POSTSKIP = ADD
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Node Hierarchy
■
This example outputs X1.X4:
.OPTION SIM_POSTAT = X1.X4
■
This example outputs top, X1, X1.X4, X1.X4.X1, X1.X4.X2, and X2:
.OPTION SIM_POSTTOP = 2
.OPTION SIM_POSTDOWN = X1.X4
Node Hierarchy
top
X1(ADD)
314
X5
X4
X3
X1
X2(SUB)
X2
X1
X6
X2
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Initializing DC/Operating Point Analysis
8
Describes DC initialization and operating point analysis.
For descriptions of individual HSPICE commands referenced in this chapter,
see the HSPICE Command Reference manual.
Simulation Flow
Figure 45 shows the simulation flow for DC analysis in Synopsys HSPICE and
HSPICE RF.
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Initialization and Analysis
Figure 45
DC Initialization and Operating Point Analysis Simulation Flow
Simulation Experiment
Transient
DC
Operating point
Sweep analysis
simulation
AC
DC-related AC
small-signal analysis
.DCMATCH
.PZ
.OPTION: Tolerance
ABSI (ABSTOL)
ABSMOS
ABSV
ABSVDC
KCLTEST
RELI
RELMOS
RELV
RELVDC
Matrix
ITL1
NOPIV
PIVOT
PIVREF
PIVREL
PIVTOL
SPARSE
NOTOP
Monte Carlo
analysis
.SENS
.TF
Convergence
CONVERGE
CSHDC
DCFOR
DCHOLD
DCON
DCSTEP
DCTRAN
DV
GMAX
GMINDC
GRAMP
GSHUNT
ICSWEEP
NEWTOL
OFF
Limit
RESMIN
Initialization and Analysis
Before it performs .OP, .DC sweep, .AC, or .TRAN analyses, HSPICE or
HSPICE RF first sets the DC operating point values for all nodes and sources.
To do this, HSPICE or HSPICE RF does one of the following:
■
Calculates all values
■
Applies values specified in .NODESET and .IC statements
■
Applies values stored in an initial conditions file.
The .OPTION OFF statement, and the OFF and IC = val element
parameters, also control initialization.
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Initialization and Analysis
Initialization is fundamental to simulation. HSPICE or HSPICE RF starts any
analysis with known nodal voltages (or initial estimates for unknown voltages),
and some branch currents. It then iteratively finds the exact solution. Initial
estimates that are close to the exact solution, increase the likelihood of a
convergent solution and a lower simulation time.
A transient analysis first calculates a DC operating point, using the DC
equivalent model of the circuit (unless you specify the UIC parameter in
the .TRAN statement). HSPICE or HSPICE RF then uses the resulting DC
operating point as an initial estimate, to solve the next timepoint in the transient
analysis.
1. If you do not provide an initial guess, or if you provide only partial
information, HSPICE or HSPICE RF provides a default estimate for each
node in the circuit.
2. HSPICE or HSPICE RF then uses this estimate to iteratively find the exact
solution.
The .NODESET and statements supply an initial guess for the exact DC
solution of nodes within a circuit.
3. To set any circuit node to any value, use the .NODESET statement.
4. HSPICE or HSPICE RF then connects a voltage source equivalent, to each
initialized node (a current source, with a GMAX parallel conductance, set
with a .OPTION statement).
5. HSPICE or HSPICE RF next calculates a DC operating point, with
the .NODESET voltage source equivalent connected.
6. HSPICE or HSPICE RF disconnects the equivalent voltage sources, which
you set in the .NODESET statement, and recalculates the DC operating
point.
This is the DC operating point solution.
Figure 46
Equivalent Voltage Source: NODESET and .IC
I=GMAX*V
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Node
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8: Initializing DC/Operating Point Analysis
Initialization and Analysis
The .IC statement provides both an initial guess and a solution for selected
nodes within the circuit. Nodes that you initialize with the .IC statement,
become part of the solution of the DC operating point.
You can also use the OFF option to initialize active devices. The OFF option
works with .IC and .NODESET voltages, as follows:
1. If the netlist includes any .IC or .NODESET statements, HSPICE or
HSPICE RF sets node voltages, according to those statements.
2. If you set the OFF option, then HSPICE or HSPICE RF sets values to zero
for the terminal voltages of all active devices (BJTs, diodes, MOSFETs,
JFETs, MESFETs) that are not set in .IC or .NODESET statements, or by
sources.
3. If element statements specify any IC parameters, HSPICE or HSPICE RF
sets those initial conditions.
4. HSPICE or HSPICE RF uses the resulting voltage settings, as the initial
guess at the operating point.
Use OFF to find an exact solution, during an operating point analysis, in a
large circuit. The majority of device terminals are at zero volts for the
operating point solution. To initialize the terminal voltages to zero for
selected active devices, set the OFF parameter, in the element statements
for those devices.
After HSPICE finds a DC operating point, use .SAVE to store operatingpoint node voltages in a <design>.ic file. Then use the .LOAD statement to
restore operating-point values, from the ic file for later analyses.
Note: HSPICE RF does not support the .SAVE and .LOAD (save and restart)
statements.
When you set initial conditions for Transient Analysis:
318
■
If you include UIC in a .TRAN statement, HSPICE or HSPICE RF starts a
transient analysis, using node voltages specified in an .IC statement.
■
Use the .OP statement, to store an estimate of the DC operating point,
during a transient analysis.
■
HSPICE RF does not output node voltage from operating point (.OP), if time
(t) < 0.
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DC Initialization and Operating Point Calculation
■
An internal timestep too small error message indicates that the circuit failed
to converge. The cause of the failure can be that HSPICE or HSPICE RF
cannot use stated initial conditions to calculate the actual DC operating
point.
DC Initialization and Operating Point Calculation
You use a .OP statement in HSPICE or HSPICE RF to:
■
Calculate the DC operating point of a circuit
■
Produce an operating point during a transient analysis
A simulation can only have one .OP statement.
.OP Statement — Operating Point
When you include an .OP statement in an input file, HSPICE or HSPICE RF
calculates the DC operating point of the circuit. You can also use the .OP
statement to produce an operating point, during a transient analysis. You can
include only one .OP statement in a simulation.
If an analysis requires calculating an operating point, you do not need to
specify the .OP statement; HSPICE or HSPICE RF calculates an operating
point. If you use a .OP statement, and if you include the UIC keyword in
a .TRAN analysis statement, then simulation omits the time = 0 operating point
analysis, and issues a warning in the output listing.
Output
***** OPERATING POINT INFORMATION TNOM = 25.000
TEMP = 25.000
***** OPERATING POINT STATUS IS ALL SIMULATION TIME IS 0.
NODE
VOLTAGE NODE
VOLTAGE NODE
VOLTAGE
+ 0:2 = 0 0:3 = 437.3258M 0:4 = 455.1343M
+ 0:5 = 478.6763M 0:6 = 496.4858M 0:7 = 537.8452M
+ 0:8 = 555.6659M 0:10 = 5.0000 0:11 = 234.3306M
**** VOLTAGE SOURCES
SUBCKT
ELEMENT 0:VNCE 0:VN7
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DC Initialization and Operating Point Calculation
VOLTS 0 5.00000 0 -5.00000
AMPS -2.07407U -405.41294P 2.07407U
POWER 0. 2.02706N 0.
2.02706N
405.41294P
TOTAL VOLTAGE SOURCE POWER DISSIPATION = 4.0541 N WATTS
**** BIPOLAR JUNCTION TRANSISTORS
SUBCKT
ELEMENT
0:QN1 0:QN2
0:QN3 0:QN4
* Note: HSPICE RF does not support qn(element)
* charge output.
MODEL
0:N1
0:N1
0:N1
0:N1
IB 999.99912N 2.00000U 5.00000U 10.00000U
IC -987.65345N -1.97530U -4.93827U -9.87654U
VBE 437.32588M 455.13437M 478.67632M 496.48580M
VCE 437.32588M 17.80849M 23.54195M 17.80948M
VBC 437.32588M 455.13437M 478.67632M 496.48580M
VS 0. 0. 0. 0.
POWER 5.39908N 875.09107N 2.27712U 4.78896U
BETAD -987.65432M -987.65432M -987.65432M -987.65432M
GM 0. 0. 0. 0.
RPI 2.0810E+06 1.0405E+06 416.20796K 208.10396K
RX 250.00000M
250.00000M 250.00000M 250.00000M
RO 2.0810E+06 1.0405E+06 416.20796K 208.10396K
CPI 1.43092N 1.44033N 1.45279N 1.46225N
CMU 954.16927P 960.66843P 969.64689P 977.06866P
CCS 800.00000P 800.00000P 800.00000P 800.00000P
BETAAC 0. 0. 0. 0.
FT
0. 0. 0. 0.
Element Statement IC Parameter
Use the element statement parameter, IC = <val>, to set DC terminal voltages
for selected active devices.
HSPICE uses the value, set in IC = <val>, as the DC operating point value, in
the DC solution.
■
HSPICE RF does not support this option, so IC is always set to IC=OFF.
Example
This example describes an H element dependent-voltage source:
HXCC 13 20 VIN1 VIN2 IC = 0.5, 1.3
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DC Initialization and Operating Point Calculation
The current, through VIN1, initializes to 0.5 mA. The current, through VIN2,
initializes to 1.3 mA.
Initial Conditions
Use the .IC statement, or the .DCVOLT statement, to set transient initial
conditions in HSPICE, but not in HSPICE RF. How it initializes depends on
whether the .TRAN analysis statement includes the UIC parameter.
Note: In HSPICE RF, .IC is always set to OFF.
If you specify the UIC parameter in the .TRAN statement, HSPICE does not
calculate the initial DC operating point, but directly enters transient analysis.
Transient analysis uses the .IC initialization values as part of the solution for
timepoint zero (calculating the zero timepoint applies a fixed equivalent voltage
source). The .IC statement is equivalent to specifying the IC parameter on
each element statement, but is more convenient. You can still specify the IC
parameter, but it does not have precedence over values set in the .IC
statement.
If you do not specify the UIC parameter in the .TRAN statement, HSPICE
computes the DC operating point solution before the transient analysis. The
node voltages that you specify in the .IC statement are fixed to determine the
DC operating point. HSPICE RF does not output node voltage from operating
point (.OP) if time (t) < 0. Transient analysis releases the initialized nodes to
calculate the second and later time points.
.NODESET initializes all specified nodal voltages for DC operating point
analysis. Use the .NODESET statement to correct convergence problems in DC
analysis. If you set the node values in the circuit, close to the actual DC
operating point solution, you enhance convergence of the simulation. The
HSPICE or HSPICE RF simulator uses the NODESET voltages only in the first
iteration.
SAVE and LOAD Statements
HSPICE saves the operating point, unless you use the .SAVE LEVEL = NONE
statement. HSPICE restores the saved operating-point file, only if the input file
contains a .LOAD statement.
The .SAVE statement in HSPICE stores the operating point of a circuit, in a file
that you specify. HSPICE RF does not support the .SAVE statement. For quick
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DC Initialization and Operating Point Calculation
DC convergence in subsequent simulations, use the .LOAD statement to input
the contents of this file. HSPICE saves the operating point by default, even if
the HSPICE input file does not contain a .SAVE statement. To not save the
operating point, specify .SAVE LEVEL = NONE.
A parameter or temperature sweep saves only the first operating point.
Note: HSPICE RF does not support .SAVE and .LOAD statements.
If any node initialization commands, such as .NODESET and .IC, appear in the
netlist after the .LOAD command, then they overwrite the .LOAD initialization. If
you use this feature to set particular states for multistate circuits (such as flipflops), you can still use the .SAVE command to speed up the DC convergence.
.SAVE and .LOAD work even on changed circuit topologies. Adding or deleting
nodes results in a new circuit topology. HSPICE initializes the new nodes, as if
you did not save an operating point. HSPICE ignores references to deleted
nodes, but initializes coincidental nodes to the values that you saved from the
previous run.
When you initialize nodes to voltages, HSPICE inserts Norton-equivalent
circuits at each initialized node. The conductance value of a Norton-equivalent
circuit is GMAX = 100, which might be too large for some circuits.
If using .SAVE and .LOAD does not speed up simulation, or causes simulation
problems, use .OPTION GMAX = 1e-12 to minimize the effect of Nortonequivalent circuits on matrix conductances.
HSPICE still uses the initialized node voltages to initialize devices. HSPICE RF
does not output node voltage from operating point (.OP), if time (t) < 0.
.SAVE Statement
The .SAVE statement in HSPICE stores the operating point of a circuit, in a file
that you specify. HSPICE RF does not support the .SAVE statement. For quick
DC convergence in subsequent simulations, use the .LOAD statement to input
the contents of this file. HSPICE saves the operating point by default, even if
the HSPICE input file does not contain a .SAVE statement. To not save the
operating point, specify .SAVE LEVEL = NONE.
You can save the operating point data as either an .IC or a .NODESET
statement.
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.DC Statement—DC Sweeps
.LOAD Statement
Use the .LOAD statement to input the contents of a file, that you stored using
the .SAVE statement in HSPICE.
Note: HSPICE RF does not support the .SAVE and .LOAD (save and restart)
statements.
Files stored with the .SAVE statement contain operating point data for the point
in the analysis at which you executed .SAVE. Do not use the .LOAD command
for concatenated netlist files.
.DC Statement—DC Sweeps
You can use the .DC statement in DC analysis, to:
■
Sweep any parameter value (HSPICE and HSPICE RF).
■
Sweep any source value (HSPICE and HSPICE RF).
■
Sweep temperature range (HSPICE and HSPICE RF).
■
Perform a DC Monte Carlo (random sweep) analysis (HSPICE only; not
supported in HSPICE RF).
■
Perform a data-driven sweep (HSPICE and HSPICE RF).
■
Perform a DC circuit optimization for a data-driven sweep (HSPICE and
HSPICE RF).
■
Perform a DC circuit optimization, using start and stop (HSPICE only; not
supported in HSPICE RF).
■
Perform a DC model characterization (HSPICE only; not supported in
HSPICE RF).
The .DC statement format depends on the application that uses it.
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Other DC Analysis Statements
Other DC Analysis Statements
HSPICE or HSPICE RF also provides the following DC analysis statements.
Each statement uses the DC-equivalent model of the circuit in its analysis.
For .PZ, the equivalent circuit includes capacitors and inductors.
Statement
Description
.DCMATCH
(HSPICE) A technique for computing the effects of local variations in
device characteristics on the DC solution of a circuit.
.PZ
Performs pole/zero analysis.
.SENS
(HSPICE) Obtains DC small-signal sensitivities of output variables for
circuit parameters.
.TF
Calculates DC small-signal values for transfer functions (ratio of
output variable, to input source).
HSPICE or HSPICE RF includes DC control options, and DC initialization
statements, to model resistive parasitics and initialize nodes. These statements
enhance convergence properties and accuracy of simulation. This section
describes how to perform DC-related, small-signal analysis.
DC Initialization Control Options
Use control options in a DC operating-point analysis, to control DC
convergence properties and simulation algorithms. Many of these options also
affect transient analysis, because DC convergence is an integral part of
transient convergence. Include the following options for both DC and transient
convergence:
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■
Absolute and relative voltages.
■
Current tolerances.
■
Matrix options.
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Use .OPTION statements to specify the following options, which control DC
analysis:
ABSTOL
DV
ITL2
PIVREL
CAPTAB
GDCPATH
KCLTEST
PIVTOL
CSHDC
GRAMP
MAXAMP
RESMIN
DCCAP
GSHDC
NEWTOL
SPARSE
DCFOR
GSHUNT
NOPIV
SYMB
DCHOLD
ICSWEEP
OFF
DCIC
ITLPTRAN
PIVOT
DCSTEP
ITL1
PIVREF
DC and AC analysis also use some of these options. Many of these options
also affect the transient analysis, because DC convergence is an integral part
of transient convergence. For a description of transient analysis, see Chapter 9,
“Transient Analysis.”.
Accuracy and Convergence
Convergence is the ability to solve a set of circuit equations, within specified
tolerances, and within a specified number of iterations. In numerical circuit
simulation, a designer specifies a relative and absolute accuracy for the circuit
solution. The simulator iteration algorithm then attempts to converge to a
solution that is within these set tolerances. That is, if consecutive simulations
achieve results within the specified accuracy tolerances, circuit simulation has
converged. How quickly the simulator converges, is often a primary concern to
a designer—especially for preliminary design trials. So designers willingly
sacrifice some accuracy for simulations that converge quickly.
Accuracy Tolerances
HSPICE or HSPICE RF uses accuracy tolerances that you specify, to assure
convergence. These tolerances determine when, and whether, to exit the
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convergence loop. For each iteration of the convergence loop, HSPICE or
HSPICE RF subtracts previously-calculated values from the new solution, and
compares the result with the accuracy tolerances.
If the difference between two consecutive iterations is within the specified
accuracy tolerances, the circuit simulation has converged.
| Vnk - Vnk-1 | < = accuracy tolerance
■
Vnk is the solution at the n timepoint for iteration k.
■
Vnk-1 is the solution at the n timepoint for iteration k - 1.
As Table 46 shows, HSPICE or HSPICE RF defaults to specific absolute and
relative values. You can change these tolerances, so that simulation time is not
excessive, but accuracy is not compromised. Accuracy Control Options on
page 328 describes the options in Table 46.
Table 46
Absolute and Relative Accuracy Tolerances
Type
.OPTION
Default
Nodal Voltage Tolerances
ABSVDC
50 µv
RELVDC
.001
ABSI
1 nA
RELI
.01
ABSMOS
1 uA
RELMOS
.05
Current Element Tolerances
HSPICE or HSPICE RF compares nodal voltages and element currents, to the
values from the previous iteration.
■
If the absolute value of the difference is less than ABSVDC or ABSI, then
the node or element has converged.
ABSV and ABSI set the floor value, below which HSPICE or HSPICE RF
ignores values. Values above the floor use RELVDC and RELI as relative
tolerances. If the iteration-to-iteration absolute difference is less than these
tolerances, then it is convergent.
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Note: ABSMOS and RELMOS are the tolerances for MOSFET drain currents.
Accuracy settings directly affect the number of iterations before convergence.
■
If accuracy tolerances are tight, the circuit requires more time to converge.
■
If the accuracy setting is too loose, the resulting solution can be inaccurate
and unstable.
Table 47 shows an example of the relationship between the RELVDC value,
and the number of iterations.
Table 47
RELV vs. Accuracy and Simulation Time for 2 Bit Adder
RELVDC
Iteration
Delay (ns)
Period (ns)
Fall time (ns)
.001
540
31.746
14.336
1.2797
.005
434
31.202
14.366
1.2743
.01
426
31.202
14.366
1.2724
.02
413
31.202
14.365
1.3433
.05
386
31.203
14.365
1.3315
.1
365
31.203
14.363
1.3805
.2
354
31.203
14.363
1.3908
.3
354
31.203
14.363
1.3909
.4
341
31.202
14.363
1.3916
.4
344
31.202
14.362
1.3904
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Accuracy and Convergence
Accuracy Control Options
The default control option settings are designed to maximize accuracy, without
significantly degrading performance. For a description of these options and
their settings, see Simulation Speed and Accuracy on page 354.
ABSH
DCON
RELH
ABSI
DCTRAN
RELI
ABSMOS
DI
RELMOS
ABSVDC
GMAX
RELV
CONVERGE
GMINDC
RELVDC
Autoconverge Process
If a circuit does not converge in the number of iterations that ITL1 specifies,
HSPICE or HSPICE RF initiates an auto-convergence process. This process
manipulates DCON, GRAMP, and GMINDC, and even CONVERGE in some cases.
Figure 47 shows the autoconverge process.
Note: HSPICE uses autoconvergence in transient analysis, but it also uses
autoconvergence in DC analysis if the Newton-Raphson (N-R) method fails
to converge.
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Figure 47
Autoconvergence Process Flow Diagram
Start
STEP 1
Iterates up to the ITL1 limit.
Iterate
Y
Results
Converged?
N
STEP 2
Sets DCON = 1.
If DV = 1000, sets DV from 1000 to max(0.1. Vmax/50).
Sets GRAMP = (Imax/GMINDC).
Ramps GMINDC, from GMINDC⋅10GRAMP to 1e-12.
Try DCON = 1
Converged?
Y
Results
STEP 3
Sets DCON = 2.
Relaxes DV to 1e6.
Sets GRAMP = (Imax/GMINDC).
Ramps GMINDC, from GMINDC⋅10GRAMP to 1e-12.
N
Try DCON = 2
Converged?
Y
Results
N
STEP 4
Adds CSHDC and GSHUNT, from each node, to ground.
Ramps supplies, from zero to the set values.
Removes CSHDC and GSHUNT, after DC convergence.
Also iterates to a stable DC-bias point.
Try CONVERGE=1
Converged?
Y
Results
N
STEP 5
Adds CSHDC, from each node, to ground.
Ramps gmath=cshdc/delta in the range of 1.0e-12 to 10.0.
Set gmath to zero, if convergence occurs with gmath under
1.0e-12, and iterates further to a stable DC bias point.
Try CONVERGE=4
Y
Converged?
Results
N
Non-convergence report
Referring to Figure 47:
■
Setting .OPTION DCON = -1 disables steps 2 and 3.
■
Setting .OPTION CONVERGE = -1 disables steps 4 and 5.
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■
Setting .OPTION DCON = -1 CONVERGE = -1 disables steps 2, 3, 4,
and 5.
■
If you set the DV option to a value other than the default, step 2 uses the
value you set for DV, but step 3 changes DV to 1e6.
■
Setting .OPTION GRAMP has no effect on autoconverge. Autoconverge sets
GRAMP independently.
■
If you set .OPTION GMINDC, then GMINDC ramps to the value you set,
instead of to 1e-12, in steps 2 and 3.
DCON and GMINDC
The GMINDC option helps stabilize the circuit, during DC operating-point
analysis. For MOSFETs, GMINDC helps stabilize the device in the vicinity of the
threshold region. HSPICE or HSPICE RF inserts GMINDC between:
■
Drain and bulk.
■
Source and bulk.
■
Drain and source.
The drain-to-source GMINDC helps to:
■
Linearize the transition from cutoff to weakly-on.
■
Smooth-out model discontinuities.
■
Compensate for the effects of negative conductances.
The pn junction insertion of GMINDC in junction diodes linearizes the low
conductance region. As a result, the device behaves like a resistor in the lowconductance region. This prevents the occurrence of zero conductance, and
improves the convergence of the circuit.
If a circuit does not converge, HSPICE or HSPICE RF automatically sets the
DCON option. This option invokes GMINDC ramping, in steps 2 and 3 of
Figure 47.
GMINDC for various elements is shown in Figure 48.
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Figure 48
GMINDC Insertion
GMINDC
Diode element
GMINDC
BJT element
GMINDC
GMINDC
MOSFET element
GMINDC
GMINDC
JFET or MESFET
element
GMINDC
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Reducing DC Errors
Reducing DC Errors
To reduce DC errors, perform the following steps:
1. To check topology, set .OPTION NODE, to list nodal cross-references.
•
Do all MOS p-channel substrates connect to either VCC or positive
supplies?
•
Do all MOS n-channel substrates connect to either GND or negative
supplies?
•
Do all vertical NPN substrates connect to either GND or negative
supplies?
•
Do all lateral PNP substrates connect to negative supplies?
•
Do all latches have either an OFF transistor, a .NODESET, or an .IC, on
one side?
•
Do all series capacitors have a parallel resistance, or is .OPTION
DCSTEP set?
2. Check your .MODEL statements.
332
•
Check all model parameter units. Use model printouts to verify actual
values and units, because HSPICE multiplies some model parameters
by scaling options.
•
Are sub-threshold parameters of MOS models, set with reasonable
value (such as NFS = 1e11 for SPICE 1, 2, and 3 models, or N0 = 1.0
for HSPICE BSIM1, BSIM2, and Level 28 device models)?
•
Do not set UTRA in MOS Level 2 models.
•
Are JS and JSW set in the MOS model for the DC portion of a diode
model? A typical JS value is 1e-4A/M2.
•
Are CJ and CJSW set, in MOS diode models?
•
Is weak-inversion NG and ND set in JFET/MESFET models?
•
If you use the MOS Level 6 LGAMMA equation, is UPDATE=1?
•
Make sure that DIODE models have non-zero values for saturation
current, junction capacitance, and series resistance.
•
Use MOS ACM = 1, ACM = 2, or ACM = 3 source and drain diode
calculations, to automatically generate parasitics.
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3. General remarks:
•
Ideal current sources require large values of .OPTION GRAMP,
especially for BJT and MESFET circuits. Such circuits do not ramp up
with the supply voltages, and can force reverse-bias conditions, leading
to excessive nodal voltages.
•
Schmitt triggers are unpredictable for DC sweep analysis, and
sometimes for operating points for the same reasons that oscillators and
flip-flops are unpredictable. Use slow transient.
•
Large circuits tend to have more convergence problems, because they
have a higher probability of uncovering a modeling problem.
•
Circuits that converge individually, but fail when combined, are almost
guaranteed to have a modeling problem.
•
Open-loop op-amps have high gain, which can lead to difficulties in
converging. Start op-amps in unity-gain configuration, and open them
up in transient analysis, using a voltage-variable resistor, or a resistor
with a large AC value (for AC analysis).
4. Check your options:
•
Remove all convergence-related options, and try first with no
special .OPTION settings.
•
Check non-convergence diagnostic tables for non-convergent nodes.
Look up non-convergent nodes in the circuit schematic. They are
usually latches, Schmitt triggers, or oscillating nodes.
•
For stubborn convergence failures, bypass DC all together, and
use .TRAN with UIC set. Continue transient analysis until transients
settle out, then specify the .OP time, to obtain an operating point during
the transient analysis. To specify an AC analysis during the transient
analysis, add an .AC statement to the .OP time statement.
•
SCALE and SCALM scaling options have a significant effect on
parameter values in both elements and models. Be careful with units.
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Shorted Element Nodes
HSPICE or HSPICE RF disregards any capacitor, resistor, inductor, diode, BJT,
or MOSFET, if all of its leads connect together. Simulation does not count the
component in its component tally, and issues a warning:
** warning **
all nodes of element x:<name> are connected together
Inserting Conductance, Using DCSTEP
In a DC operating-point analysis, failure to include conductances in a capacitor
model results in broken circuit loops (because a DC analysis opens all
capacitors). This might not be solvable. If you include a small conductance in
the capacitor model, the circuit loops are complete, and HSPICE or HSPICE
RF can solve them.
Modeling capacitors as complete opens, can result in this error:
“No DC Path to Ground”
For a DC analysis, use .OPTION DCSTEP, to assign a conductance value to
all capacitors in the circuit. DCSTEP calculates the value as:
conductance = capacitance/DCSTEP
In Figure 49 on page 335, HSPICE or HSPICE RF inserts conductance (G), in
parallel with capacitance (Cg). This provides current paths around
capacitances, in DC analysis.
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Figure 49
Conductance Insertion
Cg
original circuit
Cg
G
after conductance
insertion
G
G
G
G = Cg/DCSTEP
Floating-Point Overflow
If MOS conductance is negative or zero, HSPICE or HSPICE RF might have
difficulty converging. An indication of this type of problem is a floating-point
overflow, during matrix solutions. HSPICE or HSPICE RF detects floating-point
overflow, and invokes the Damped Pseudo Transient algorithm
(CONVERGE = 1), to try to achieve DC convergence without requiring you to
intervene. If GMINDC is 1.0e-12 or less when a floating-point overflows,
HSPICE or HSPICE RF sets it to 1.0e-11.
Diagnosing Convergence Problems
Before simulation, HSPICE or HSPICE RF diagnoses potential convergence
problems in the input circuit, and provides an early warning, to help you in
debugging your circuit. If HSPICE or HSPICE RF detects a circuit condition that
might cause convergence problems, it prints the following message into the
output file:
“Warning: Zero diagonal value detected at node ( ) in
equation solver, which might cause convergence problems.
If your simulation fails, try adding a large resistor
between node ( ) and ground.”
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Non-Convergence Diagnostic Table
If a circuit cannot converge, HSPICE or HSPICE RF automatically generates
two printouts, called the diagnostic tables:
■
Nodal voltage printout. Prints the names of all no-convergent node voltages,
and the associated voltage error tolerances (tol).
■
Element printout, which lists all non-convergent elements, and their
associated element currents, element voltages, model parameters, and
current error tolerances (tol).
1. To locate the branch current or nodal voltage that causes non-convergence,
analyze the diagnostic tables. Look for unusually large values of branch
currents, nodal voltages or tolerances.
2. After you locate the cause, use the .NODESET or .IC statements, to
initialize the node or branch.
If circuit simulation does not converge, HSPICE or HSPICE RF
automatically generates a non-convergence diagnostic table, indicating:
•
The quantity of recorded voltage failures.
•
The quantity of recorded branch element failures.
Any node in a circuit can create voltage failures, including hidden nodes
(such as extra nodes that parasitic resistors create).
3. Check the element printout for the sub-circuit, model, and element name for
all parts of the circuit where node voltages or currents do not converge.
For example, Table 48 identifies the xinv21, xinv22, xinv23, and xinv24
inverters, as problem sub-circuits in a ring oscillator. It also indicates that the pchannel transistors, in the xinv21, xinv22, xinv24 sub-circuits, are
nonconvergent elements. The n-channel transistor of xinv23 is also a
nonconvergent element.
The table lists voltages and currents for the transistors, so you can check
whether they have reasonable values. The tolds, tolbd, and tolbs error
tolerances indicate how close the element currents (drain to source, bulk to
drain, and bulk to source) are, to a convergent solution. For tol variables, a
value close to or below 1.0 is a convergent solution. In Table 48, the tol values
that are around 100, indicate that the currents were far from convergence. The
element current and voltage values are also shown (id, ibs, ibd, vgs, vds, and
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vbs). Examine whether these values are realistic, and determine the transistor
regions of operation.
Table 48 Subcircuit Voltage, Current, and Tolerance
subckt
element
model
xinv21
21:mphc1
0:p1
xinv22
22:mphc1
0:p1
xinv23
23:mphc1
0:p1
xinv23
23:mnch1
0:n1
xinv24
24: mphc1
0:p1
id
27.5809f
140.5646u
1.8123p
1.7017m
5.5132u
ibs
205.9804f
3.1881f
31.2989f
0.
200.0000f
ibd
0.
0.
0.
-168.7011f
0.
vgs
4.9994
-4.9992
69.9223
4.9998
-67.8955
vds
4.9994
206.6633u
69.9225
-64.9225
2.0269
vbs
4.9994
206.6633u
69.9225
0.
2.0269
vth
653.8030
m
745.5860
m
732.8632
m
549.4114
m
656.5097
m
tolds
114.8609
82.5624
155.9508
104.5004
5.3653
tolbd
0.
0.
0.
0.
0.
tolbs
3.534e-19
107.1528
m
0.
0.
0.
Traceback of Non-Convergence Source
To locate a non-convergence source, trace the circuit path for error tolerance.
For example, in an inverter chain, the last inverter can have a very high error
tolerance. If this is the case, examine the error tolerance of the elements that
drive the inverter. If the driving tolerance is high, the driving element could be
the source of non-convergence. However, if the tolerance is low, check the
driven element as the source of non-convergence.
Examine the voltages and current levels of a non-convergent MOSFET to
discover the operating region of the MOSFET. This information can flow to the
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location of the discontinuity in the model—for example, subthreshold-to-linear,
or linear-to-saturation.
When considering error tolerances, check the current and nodal voltage values.
If these values are extremely low, a relatively large number is divided by a very
small number. This produces a large calculation result, which can cause the
non-convergence errors. To solve this, increase the value of the absoluteaccuracy options.
Use the diagnostic table, with the DC iteration limit (ITL1 statement), to find the
sources of non-convergence. When you increase or decrease ITL1, HSPICE or
HSPICE RF prints output for the problem nodes and elements for a new
iteration—that is, the last iteration of the analysis that you set in ITL1.
Solutions for Non-Convergent Circuits
Non-convergent circuits generally result from:
■
Poor Initial Conditions
■
Inappropriate Model Parameters
■
PN Junctions (Diodes, MOSFETs, BJTs)
The following sections explain these conditions.
Poor Initial Conditions
Multi-stable circuits need state information, to guide the DC solution. You must
initialize ring oscillators and flip-flops. These multi-stable circuits can either
produce an intermediate forbidden state, or cause a DC convergence problem.
To initialize a circuit, use the .IC statement, which forces a node to the
requested voltage. Ring oscillators usually require you to set only one stage.
Figure 50
Ring Oscillator
.IC V(1)=5V
1
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The best way to set up the flip-flop is to use an .IC statement in the subcircuit
definition.
Example
The following example sets the local Qset parameter to 0, and uses this value
for the .IC statement, to initialize the Q latch output node. As a result, all
latches have a default state of Q low. Setting Qset to vdd calls a latch, which
overrides this state.
.subckt latch in Q Q/ d Qset = 0
.ic Q = Qset
...
.ends
Xff data_in[1] out[1] out[1]/ strobe LATCH Qset = vdd
Inappropriate Model Parameters
If you impose non-physical model parameters, you might create a
discontinuous IDS or capacitance model. This can cause an internal timestep
too small error, during the transient simulation. The mosivcv.sp demonstration
file shows IDS, VGS, GM, GDS, GMB, and CV plots for MOS devices. A sweep
near threshold, from Vth-0.5 V to Vth+0.5 V (using a delta of 0.01 V),
sometimes discloses a possible discontinuity in the curves.
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Figure 51
Discontinuous I-V Characteristics
Ids
I-V characteristics exhibiting
saturation conductance = zero
Vds
Ids
I-V exhibiting VDSAT slope error
Vds
Ids
I-V exhibiting negative resistance region
Vds
If simulation does not converge when you add a component or change a
component value, then the model parameters are not appropriate, or do not
correspond to physical values they represent.
1. Check the input netlist file for non-convergent elements.
Devices with a TOL value greater than 1, are non-convergent.
2. Find the devices, at the beginning of the combined-logic string of gates, that
seem to start the non-convergent string.
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Diagnosing Convergence Problems
3. Check the operating point of these devices very closely, to see what region
they operate in.
Model parameters associated with this region are probably inappropriate.
Circuit simulation uses single-transistor characterization, to simulate a large
collection of devices. If a circuit fails to converge, the cause can be a single
transistor, anywhere in the circuit.
PN Junctions (Diodes, MOSFETs, BJTs)
PN junctions found in diode, BJT, and MOSFET models, might exhibit nonconvergent behavior, in both DC and transient analysis.
Example
PN junctions often have a high off resistance, resulting in an ill-conditioned
matrix. To overcome this, use .OPTION GMINDC and
.OPTION GMIN to automatically parallel every PN junction in a design, with a
conductance.
Non-convergence can occur if you overdrive the PN junction. This happens if
you omit a current-limiting resistor, or if the resistor has a very small value. In
transient analysis, protection diodes are often temporarily forward-biased (due
to the inductive switching effect). This overdrives the diode, and can result in
non-convergence, if you omit a current-limiting resistor.
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Diagnosing Convergence Problems
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9
Describes how to use transient analysis to compute the circuit
solution.
Transient analysis computes the circuit solution, as a function of time, over a
time range specified in the .TRAN statement.
For descriptions of individual HSPICE commands referenced in this chapter,
see the HSPICE Command Reference.
Simulation Flow
Figure 52 illustrates the simulation flow for transient analysis in Synopsys
HSPICE and HSPICE RF.
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Overview of Transient Analysis
Figure 52
Transient Analysis Simulation Flow
Simulation Experiment
Transient
DC
UIC
.FOUR
.OPTION:
Method
BYPASS
CSHUNT
DVDT
GSHUNT
LVLTIM = x
MAXORD = x
METHOD
RUNLVL = x
AC
Time-sweep
simulation
.FFT
HSPICE only
Tolerance
ABSV = x
ABSVAR = x
ACCURATE
BYTOL = x
CHGTOL = x
DELMAX = x
FAST
MBYPASS
MU
Limit
RELQ = x
RELTOL
RELV = x
RELVAR = x
SLOPETOL = x
TIMERES
TRTOL = x
VNTOL
AUTOSTOP
BKPSIZ
DVTR = x
FS = x
FT = x
GMIN = x
IMAX = x
IMIN = x
ITL3 = x
ITL4 = x
ITL5 = x
RMAX = x
RMIN = x
VFLOOR
Overview of Transient Analysis
Transient analysis simulates a circuit at a specific time. Some of its algorithms,
control options, convergence-related issues, and initialization parameters are
different than those used in DC analysis. However, a transient analysis first
performs a DC operating point analysis, unless you specify the UIC option in
the .TRAN statement. Therefore, most DC analysis algorithms, control options,
initialization issues, and convergence issues, also apply to transient analysis.
Unless you set the initial circuit operating conditions, some circuits (such as
oscillators, or circuits with feedback) do not have stable operating point
solutions. For these circuits, either:
344
■
Break the feedback loop, to calculate a stable DC operating point, or
■
Specify the initial conditions, in the simulation input.
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Overview of Transient Analysis
If you include the UIC parameter in the .TRAN statement, HSPICE or HSPICE
RF bypasses the DC operating point analysis. Instead, it uses node voltages,
specified in an .IC statement, to start a transient analysis. For example, if
a .IC statement sets a node to 5 V in, the value at that node for the first time
point (time 0) is 5 V.
You can use the .OP statement to store an estimate of the DC operating point,
during a transient analysis.
Example
In the following example, the UIC parameter (in the .TRAN statement)
bypasses the initial DC operating point analysis. The .OP statement calculates
the transient operating point (at t = 20 ns), during the transient analysis.
.TRAN 1ns 100ns UIC
.OP 20ns
Although a transient analysis might provide a convergent DC solution, the
transient analysis can still fail to converge. In a transient analysis, the internal
timestep too small error message indicates that the circuit failed to converge.
The cause of this convergence failure might be that stated initial conditions are
not close enough to the actual DC operating point values. Use the commands
in this chapter to help achieve convergence in a transient analysis.
Syntax
.OPTION SIM_ACCURACY = value
Default value = 1.
In this syntax, value is a positive number. If you specify .OPTION ACCURATE,
then the default value is 10. This option is applicable for all modes.
SIM_ACCURACY tightens all tolerances, such as:
■
Newton-Raphson tolerance.
■
Local truncation error.
■
Other errors.
The default is calibrated to provide good out-of-the-box accuracy, with good
performance. HSPICE RF supports this syntax; HSPICE does not.
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You can apply different accuracy settings to different blocks or time intervals. To
set global accuracy, use:
.OPTION SIM_ACCURACY = n
In this syntax, n is a number greater than 0. The syntax to set accuracy on a
block, instance, or time interval is similar to SIM_V_SUPPLY.
Example
This example sets accuracy to 3 for the XNAND1 and XNAND2 instances, and
accuracy to 4 for all instances of the INV subcircuit. Globally, the accuracy is 2.
If accuracy settings conflict, then HSPICE RF uses the higher accuracy value.
At 12.0ns before the end of the simulation, the global accuracy level is 5.
Because this is higher than 2, 3, or 4, it overrides all previous settings.
.OPTION SIM_ACCURACY = 2
.OPTION SIM_ACCURACY = “3 | XNAND1 XNAND2”
.OPTION SIM_ACCURACY = “4 | @INV”
.OPTION SIM_ACCURACY = “5 | 12.0n”
Note: SIM_ACCURACY has precedence over ACCURATE.
Transient Analysis Output
.print tran ov1 [ov2 ... ovN]
.probe tran ov1 [ov2 ... ovN]
.measure tran measspec
.plot tran ov1 [ov2 ... ovN]
.graph tran ov1 [ov2 ... ovN]
HSPICE RF does not support .PLOT or .GRAPH.
The ov1, ... ovN output variables can include the following:
■
V(n): voltage at node n.
■
V(n1<,n2>): voltage between the n1 and n2 nodes.
■
Vn(d1): voltage at nth terminal of the d1 device.
■
In(d1): current into nth terminal of the d1 device.
■
‘expression’: expression, involving the plot variables above
You can use wildcards (*), or as specified in the .hspicerf configuration file) to
specify multiple output variables in a single command. Output is affected by
.OPTION POST or .OPTION PROBE, sim_deltai, and sim_deltav.
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Transient Analysis of an RC Network
Parameter
*.print
Description
Writes the output from the .PRINT statement to a *.print file. HSPICE
does not generate a *.print# file.
• The header line contains column labels.
• The first column is time.
• The remaining columns represent the output variables specified
with .PRINT.
• Rows that follow the header contain the data values for simulated
time points.
*.tr#
Writes output from the .PROBE, .PRINT, .PLOT, .GRAPH,
or .MEASURE statement to a *.tr# file.
Transient Analysis of an RC Network
You can run a transient analysis, using an RC network, with a pulse source, a
DC source, and an AC source.
1. Type the following netlist into a file named quickTRAN.sp.
A SIMPLE TRANSIENT RUN
.OPTION LIST NODE POST
.OP
.TRAN 10N 2U
.PRINT TRAN V(1) V(2) I(R2) I(C1)
V1 1 0 10 AC 1 PULSE 0 5 10N 20N 20N 500N 2U
R1 1 2 1K
R2 2 0 1K
C1 2 0 .001U
.END
You can find the complete netlist for this example in the following directory:
$installdir/demo/hspice/apps/quickTRAN.sp
Note: The V1 source specification includes a pulse source. For
the syntax of pulse sources and other types of sources, seeChapter 5,
“Sources and Stimuli.”.
1. To run HSPICE, type the following:
hspice quickTRAN.sp > quickTRAN.lis
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2. To examine the simulation results and status, use an editor and view the .lis
and .st0 files.
3. Run AvanWaves and open the .sp file.
4. To view the waveform, select the quickTRAN.tr0 file from the Results
Browser window.
5. Display the voltage at nodes 1 and 2 on the x-axis.
Figure 53 on page 348 shows the waveforms.
Figure 53
Voltages at RC Network Circuit Node 1 and Node 2
A simple transient
5.0
4.0
3.0
2.0
1.0
0.
0.
200.0n
400.0n
600.0n
800.0n 1.0u
1.20u
time CL(n)
1.40u
1.60u
1.80u
2.0u
Transient Analysis of an Inverter
As a final example, analyze the behavior of the simple MOS inverter shown in
Figure 54.
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Transient Analysis of an Inverter
Figure 54
MOS Inverter Circuit
VCC
VCC
+
_
M1
IN
VIN
OUT
CLOAD
0.75 pF
+
_
M2
1. Type the following netlist data into a file named quickINV.sp.
Inverter Circuit
.OPTION LIST NODE POST
.TRAN 200P 20N
.PRINT TRAN V(IN) V(OUT)
M1 OUT IN VCC VCC PCH L = 1U W = 20U
M2 OUT IN 0 0 NCH L = 1U W = 20U
VCC VCC 0 5
VIN IN 0 0 PULSE .2 4.8 2N 1N 1N 5N 20N
CLOAD OUT 0 .75P
.MODEL PCH PMOS LEVEL = 1
.MODEL NCH NMOS LEVEL = 1
.END
You can find the complete netlist for this example in the following directory:
$installdir/demo/hspice/apps/quickINV.sp
2. To run HSPICE, type the following:
hspice quickINV.sp > quickINV.lis
3. Use AvanWaves to examine the voltage waveforms, at the inverter IN and
OUT nodes.
Figure 55 shows the waveforms.
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Figure 55
Voltage at MOS Inverter Node 1 and Node 2
Inverter Circuit
04/21/2003 16.48.25
1
5.0
Volt (lin)
4.0
Input
quickinv.t
in
out
Output
3.0
2.0
1.0
0
0.0
2.0
4.0
6.0
8.0
10.0
time (lin)
12.0
14.0
16.0
18.0
20.0
Using the .BIASCHK Statement
The .BIASCHK statement can monitor the voltage bias, current, device-size,
expression and region during analysis, and reports:
■
Element name
■
Time
■
Terminals
■
Bias that exceeds the limit
■
Number of times the bias exceeds the limit for an element
HSPICE or HSPICE RF saves the information as both a warning and a
BIASCHK summary in the *.lis file. You can use this command only for active
elements and capacitors.
You can also use .OPTION BIASFILE and .OPTION BIAWARN with
the .BIASCHK statement.
The following limitations apply to the .BIASCHK command:
350
■
.BIASCHK is only supported for diode, jfet, nmos, pmos, bjt, and c models,
as well as subcircuits.
■
For a device-size check, only W and L MOSFET models are supported.
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Using the .BIASCHK Statement
■
Wildcards in element and model names, and except definitions are
supported but not in expressions.
See the HSPICE Command Reference for more information about
the .BIASCHK command.
Data Checking Methods
Four methods are available to check the data with the .BIASCHK command:
■
Limit and noise method
■
Maximum method
■
Minimum method
■
Region method
Note: The region method of data checking is only supported in MOSFET
models.
Limit and Noise Method
For a transient simulation using the limit and noise method to check the data,
use the following syntax:
For local_max
v(tn-1) > limit_value
The bias corresponds anyone of the following two conditions:
■
v(tn-1) > v(tn) && v(tn-1) >= v(tn-2)
■
v(tn-1) >= v(tn) && v(tn-1) > v(tn-2)
local_min: The minimum bias after the time last local max occurs.
During a transient analysis, the local_max is recorded if it is greater than the
limit. In the summary reported after transient analysis, the local_max(current) is
replaced with the local_max(next) when the following comparison is true:
local_max(current) - local_min < noise && local_max(next) - local_min < noise
&& local_max(current) < local_max(next)
At the end of the simulation, all local_max values are listed as biaschk
warnings. During other analyses, warnings are issued when the value you want
to check is greater than the limit_value you specify.
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Maximum Method
For a transient simulation using the maximum method to check the data, use
the following syntax:
For local_max:
v(tn-1) > max_value
The bias corresponds any one of the following two conditions:
■
v(tn-1) > v(tn) && v(tn-1) >= v(tn-2)
■
v(tn-1) >= v(tn) && v(tn-1) > v(tn-2)
During a transient analysis, all local_max values are listed as biaschk
warnings. During other analyses, warnings are issued when the value you want
to check is greater than max_value you specify.
Minimum Method
For a transient simulation using the minimum method to check the data, use the
following syntax:
For local_min:
v(tn) < min_value
The bias corresponds any one of the following two conditions:
■
v(tn-1) < v(tn) && v(tn-1) <= v(tn-2)
■
v(tn-1) <= v(tn) && v(tn-1) < v(tn-2)
During a transient analysis, all local_min values are listed as biaschk warnings.
During other analyses, warnings are issued when the value you want to check
is smaller than min_value you specify.
Region Method
This method is only for MOSFET models. Three regions exist:
■
cutoff
■
linear
■
saturation
When the specified transistor enters and exits during transient analysis, the
specified region is reported.
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Transient Control Options
Example
The following example is a netlist that uses the .BIASCHK command for a
transient simulation.
You can find the sample netlist for this example in the following directory:
$installdir/demo/hspice/apps/biaschk.sp
Transient Control Options
Method, tolerance, and limit options in this section modify the behavior of
transient analysis integration routines. Delta is the internal timestep. TSTEP
and TSTOP are the step and stop values in the .TRAN statement. Asterisk
denotes an option only available in HSPICE RF (not supported in HSPICE).
Table 49 Transient Control Options, Arranged by Category
Method
Tolerance
BYPASS
CSHUNT
DVDT
GSHUNT
INTERP
ITRPRT
LVLTIM
MAXORD
METHOD
POST*
PROBE*
PURETPSIM_
ORDER*
RUNLVL
SIM_TRAP*
TRCON
ABSH
ABSV
ABSVAR
ACCURAT
E BYTOL
CHGTOL
DI
FAST
MBYPASS
MAXAMP
MU
RELH
RELI
RELQ
RELTOL
RELV
Limit
RELVAR
SIM_ACCURACY*
SIM_DELTAI*
SIM_DELTAV*
SIM_MAXSTEP*
SLOPETOL
TIMERES
TRTOL
VNTOL
AUTOSTOP
BKPSIZ
DELMAX
DVTR
FS
FT
GMIN
ITL3
ITL4
ITL5
RMAX
RMIN
VFLOOR
Matrix Manipulation Options
After HSPICE generates individual linear elements in an input netlist, it
constructs linear equations for the matrix. You can set variables that affect how
HSPICE constructs and solves the matrix equation, including .OPTION PIVOT
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and .OPTION GMIN (HSPICE RF does not support these options). GMIN
places a variable in the matrix, so the matrix does not become ill-conditioned.
.OPTION PIVOT selects a pivoting method, which reduces simulation time,
and assists in DC and transient convergence. Pivoting reduces errors, resulting
from elements in the matrix that are widely different in magnitude. PIVOT
searches the matrix, to find the largest element value, and uses this value as
the pivot.
Simulation Speed and Accuracy
Convergence is the ability to solve a set of circuit equations within specified
tolerances and within a specified number of iterations. In numerical circuit
simulation, you can specify relative and absolute accuracy for the circuit
solution. The simulator iteration algorithm attempts to converge to a solution
that is within these set tolerances. If consecutive simulations achieve results
within the specified accuracy tolerances, circuit simulation has converged. How
quickly the simulator converges, is often a primary concern to a designer—
especially for preliminary design trials. So designers willingly sacrifice some
accuracy for simulations that converge quickly.
Simulation Speed
HSPICE or HSPICE RF can substantially reduce the computer time needed to
solve complex problems. Use the following options to alter the internal
algorithms to increase simulation efficiency.
354
■
.OPTION FAST – sets additional options, which increase simulation speed,
with minimal loss of accuracy
■
.OPTION AUTOSTOP – terminates the simulation, after completing
all .MEASURE statements. This is of special interest, when testing corners.
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Simulation Speed and Accuracy
Simulation Accuracy
In HSPICE or HSPICE RF, the default control option values aim for superior
accuracy, within an acceptable amount of simulation time. The control options
and their default settings (to maximize accuracy) are:
DVDT = 4LVLTIM = 1RMAX = 5SLOPETOL = 0.75
FT = FS = 0.25BYPASS = 1BYTOL = MBYPASSxVNTOL = 0.100m
Note: BYPASS is on (set to 1), only when DVDT = 4. For other DVDT settings,
BYPASS is off (0). The SLOPETOL value is 0.75, only if DVDT = 4 and
LVLTIM = 1. For all other values of DVDT or LVLTIM, SLOPETOL defaults to
0.5.
Timestep Control for Accuracy
The DVDT control option selects the timestep control algorithm. For a
description of the relationships between DVDT and other control options, see
Selecting Timestep Control Algorithms on page 366.
The DELMAX control option also affects simulation accuracy. DELMAX specifies
the maximum timestep size. If you do not set .OPTION DELMAX, HSPICE or
HSPICE RF computes a DELMAX value. Factors that determine the computed
DELMAX value are:
■
.OPTION RMAX and .OPTION FS.
■
Breakpoint locations for a PWL source.
■
Breakpoint locations for a PULSE source.
■
Smallest period for a SIN source.
■
Smallest delay for a transmission line component.
■
Smallest ideal delay for a transmission line component.
■
TSTEP value, in a .TRAN analysis.
■
Number of points, in an FFT analysis (HSPICE only).
Use the FS and RMAX control options, to control the DELMAX value.
■
.OPTION FS, which defaults to 0.25, scales the breakpoint interval in the
DELMAX calculation.
■
.OPTION RMAX defaults to 5 (if DVDT = 4 and LVLTIM = 1), and scales the
TSTEP (timestep) size in the DELMAX calculation.
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For circuits that contain oscillators or ideal delay elements, use
.OPTION DELMAX, to set DELMAX to one-hundredth of the period or less.
.OPTION ACCURATE tightens the simulation options, to output the most
accurate set of simulation algorithms and tolerances. If you set ACCURATE to
1, HSPICE or HSPICE RF uses these control options:
Table 50.
DVDT = 2
BYTOL = 0
RELVAR = 0.2
LVLTIM = 3
BYPASS = 0
ABSVAR = 0.2
FT = FS = 0.2
RMAX = 2
RELMOS = 0.01
SLOPETOL = 0.5
Models and Accuracy
Simulation accuracy depends on the sophistication and accuracy of the models
you use. Advanced MOS, BJT, and GaAs models provide superior results for
critical applications.
The following model types increase simulation accuracy:
■
Algebraic models, which describe parasitic interconnect capacitances as a
function of the width of the transistor. The wire model extension of the
resistor can model the metal, diffusion, or poly interconnects, to preserve
the relationship between the physical layout and the electrical property.
■
The ACM parameter in MOS models, which calculates source and drain
junction parasitic defaults. ACM equations calculate:
•
size of the bottom wall
•
length of the sidewall diodes
•
length of a lightly doped structure.
SPICE defaults do not calculate the junction diode. Specify AD, AS, PD, PS,
NRD, NRS, to override the default calculations.
■
356
CAPOP = 4 models the most advanced charge conservation, nonreciprocal gate capacitances. HSPICE or HSPICE RF calculates the gate
capacitors and overlaps, from the IDS model for LEVEL 49 or 53. Simulation
ignores the CAPOP parameter; instead, use the CAPMOD model
parameter, with a reasonable value.
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Linear Acceleration (SIM_LA Option)
Guidelines for Choosing Accuracy Options
Use .OPTION ACCURATE for:
■
Analog or mixed signal circuits.
■
Circuits with long time constants, such as RC networks.
■
Circuits with ground bounce.
Use the default options (DVDT = 4) for:
■
Digital CMOS.
■
CMOS cell characterization.
■
Circuits with fast moving edges (short rise and fall times).
For ideal delay elements, use one of the following:
■
ACCURATE.
■
DVDT = 3.
■
DVDT = 4. If the minimum pulse width of a signal is less than the minimum
ideal delay, set DELMAX to a value smaller than the minimum pulse width.
Linear Acceleration (SIM_LA Option)
HSPICE RF provides a linear acceleration capability, using the SIM_LA option.
HSPICE does not support this option.
SIM_LA accelerates simulation of circuits that include large linear RC
networks. To do this, HSPICE RF linearly reduces all matrices that represent
RC networks. The result is a smaller matrix that maintains the original port
behavior, yet achieves significant savings in memory and computation. Thus,
the SIM_LA option is ideal for circuits with large numbers of resistors and
capacitors, such as clock trees, power lines, or substrate networks.
In general, the RC elements are separated into their own network. Both the
main circuit elements (including .PRINT, .PROBE, and .MEASURE elements),
and the RC elements, share the port nodes of the RC network. All other RC
nodes are internal nodes. The currents flowing into the port nodes are a
frequency-dependent function of the voltages at those nodes, a relationship
represented by the multiport admittance of a network.
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Linear Acceleration (SIM_LA Option)
1. The SIM_LA option formulates matrices, to represent multiport admittance.
2. Then, to eliminate as many internal nodes as possible, it reduces the size of
these matrices, while preserving the admittance, otherwise known as port
node behavior.
Multiport Admittance vs. Frequency
admittance
Figure 56
ce
tan
t
i
dm
al a
u
t
ac
approx
f0
frequency
3. The amount of reduction depends on the specified upper frequency f0,
which is the threshold frequency where SIM_LA preserves the admittance.
For frequencies below f0, the approx signal matches the original admittance.
Above f0, the two waveforms diverge, but presumably the higher frequencies
are not of interest. The lower the f0 frequency, the greater the amount of
reduction.
You can choose one of two algorithms, explained below:
■
PACT Algorithm
■
PI Algorithm
PACT Algorithm
The PACT (Pole Analysis via Congruence Transforms) algorithm reduces the
RC networks in a well-conditioned manner, while preserving network stability.
358
■
The transform preserves the first two moments of admittance at DC (slope
and offset), so that DC behavior is correct (see Figure 57 on page 359).
■
The algorithm preserves enough low-frequency poles from the original
network, to maintain the circuit behavior up to a specified maximum
frequency f0, within the specified tolerance.
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Linear Acceleration (SIM_LA Option)
This approach is the most accurate of the two algorithms, and is the default.
PACT Algorithm
ed
erv
s
pre
et
s
f
of
nd
ce
a
tan
e
t
i
p
slo
adm
ual
t
c
a
admittance
Figure 57
PACT: poles added
f0
frequency
PI Algorithm
This algorithm creates a pi model of the RC network.
■
For a two-port, the pi model reduced network consists of:
•
a resistor connecting the two ports, and
•
a capacitor connecting each port to ground
The result resembles the Greek letter pi.
■
For a general multiport, SIM_LA preserves the DC admittance between the
ports, and the total capacitance that connects the ports to ground. All
floating capacitances are lumped to ground.
Syntax
The syntax for choosing between the two algorithms is:
.OPTION SIM_LA = PACT | PI
Default value = PACT
If you set the entire netlist to ANALOG mode, the linear matrix is not reduced.
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Linear Acceleration (SIM_LA Option)
Specifying Maximum Resistance
You can control the maximum resistance to preserve.
Syntax
.OPTION SIM_LA_MAXR = value
Default value = 1e15 ohms
In this syntax, value is the maximum resistance preserved in the reduction.
SIM_LA assumes that any resistor greater than value has an infinite resistance,
and drops the resistor after reduction finishes.
Specifying Minimum Capacitance
You can specify the minimum capacitance to preserve.
Syntax
.OPTION SIM_LA_MINC = value
Default value = 1e-16 farads.
In this syntax, value is the minimum capacitance preserved in the reduction.
After reduction completes, SIM_LA lumps any capacitor smaller than value, to
ground.
Other PACT Options (HSPICE RF)
HSPICE RF provides four additional PACT options.
Specifying Error Tolerance
You can specify the error tolerance.
Syntax
.OPTION SIM_LA_TOL = value
Default value = 0.05
In this syntax, value (the error tolerance for the PACT algorithm) is a value
between 0.0 and 1.0.
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Linear Acceleration (SIM_LA Option)
Specifying Upper Frequency
You can specify the upper frequency.
Syntax
.OPTION SIM_LA_FREQ = value
Default value = 1 GHz
In this syntax, value is the upper frequency for which the PACT algorithm must
preserve accuracy. If value is 0, then PACT drops all capacitors, because only
DC is of interest.
The maximum frequency required for accurate reduction, depends on both the
technology of the circuit, and the time scale of interest. In general, the faster the
circuit, the higher the maximum frequency.
Specifying Minimum Switching Time
As an alternative to SIM_LA_FREQ, you can specify the minimum switching
time.
Syntax
.OPTION SIM_LA_TIME = value
Default value = 1ns
In this syntax, value is the minimum switching time for which the PACT
algorithm preserves accuracy. Waveforms that occur more rapidly than this
time, are not accurately represented. SIM_LA_TIME is simply the dual of
SIM_LA_FREQ. The default is equivalent to setting SIM_LA_FREQ = 1 GHz.
Example 1
A circuit has a typical rise time of 1ns, so set the maximum frequency to 1 GHz,
or set the minimum switching time to 1ns:
.OPTION SIM_LA_FREQ = 1 GHz
or
.OPTION SIM_LA_TIME = 1ns
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Linear Acceleration (SIM_LA Option)
However, if spikes occur in 0.1ns, HSPICE RF does not accurately simulate
them. To capture the behavior of the spikes, use:
.OPTION SIM_LA_FREQ = 10 GHz
or
.OPTION SIM_LA_TIME = 0.1ns
Note: Higher frequencies (smaller times) increase accuracy, but only up to the
minimum time step used in HSPICE RF.
Node Reduction
To reduce the number of nodes, instead of the number of elements, use the
SIM_LA_MINMODE option.
Syntax
.OPTION SIM_LA_MINMODE = ON|OFF
SIM_LA Options Summary
362
Parameter
Description
SIM_LA
Activates linear matrix reduction, and selects between four
methods. Default is PACT.
SIM_LA_FREQ
Upper frequency for which accuracy must be preserved.
Default=1 GHz.
SIM_LA_MAXR
Maximum resistance for linear matrix reduction. Default is
1e15 ohms.
SIM_LA_MINC
Minimum capacitance for linear matrix reduction. Default=1e16 farads.
SIM_LA_TIME
Minimum time for which accuracy must be preserved. This is
a dual of SIM_LA_FREQ. Default is 1ns.
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Numerical Integration Algorithm Controls (HSPICE)
Parameter
Description
SIM_LA_TOL
Error tolerance for the PACT algorithm. Default is 0.05.
SIM_LA_MINMODE
Reduces the number of nodes, instead of the number of
elements.
Numerical Integration Algorithm Controls (HSPICE)
In HSPICE transient analysis, you can select one of three options to convert
differential terms into algebraic terms:
■
Gear
■
Backward-Euler
■
Trapezoidal
Gear algorithm:
.OPTION METHOD = GEAR
Backward-Euler:
.OPTION METHOD = GEAR MU = 0
Trapezoidal algorithm (default):
.OPTION METHOD = TRAP
Each algorithm has advantages and disadvantages. Ideally, the trapezoidal is
the preferred algorithm overall, because of its highest accuracy level and lowest
simulation time.
However, selecting the appropriate algorithm for convergence is not always that
easy or ideal. Which algorithm you select, largely depends on the type of
circuit, and its associated behavior when you use different input stimuli.
Gear and Trapezoidal Algorithms
The algorithm that you select, automatically sets the timestep control algorithm.
In HSPICE, if you select the GEAR algorithm (including Backward-Euler), the
timestep control algorithm defaults to the truncation timestep algorithm.
However, if you select the trapezoidal algorithm, the DVDT algorithm is the
default. To change these HSPICE defaults, use the timestep control options.
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Figure 58
Time Domain Algorithm
Initialization.IC
NODESET
Iteration Solution
Converged
Reversal
Time Step Algorithm
Advancement
(tnew = told + ∆t)
Time Step Unit Check
Timestep too
small error
Fail
Extrapolated Solution
for timepoint n
The trapezoidal algorithm can cause computational oscillation—that is,
oscillation that the algorithm itself causes, not oscillation from the circuit
design. This also produces an unusually long simulation time. If this occurs in
inductive circuits (such as switching regulators), use the GEAR algorithm.
If transient analysis fails to converge using .OPTION METHOD= TRAP and
DVDT timesteps (for example, due to trapezoidal oscillation), and HSPICE
reports an internal timestep too small error, HSPICE then starts the
autoconvergence process by default. This process sets .OPTION
METHOD=GEAR and LVLTIM=2, and uses the Local Truncation Error (LTE)
timestep algorithm. HSPICE then runs another transient analysis, to
automatically obtain convergent results.
To manually improve on autoconvergence results, or if autoconvergence fails to
converge, you can do either of the following:
■
Set .OPTION METHOD=GEAR in the netlist, and try to obtain convergent
results directly.
To improve accuracy or speed, you can adjust TSTEP in a .TRAN statement,
or in transient control options (such as RMAX, RELQ, CHGTOL, or TRTOL).
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■
Set .OPTON METHOD=TRAP in the netlist, then manually adjust TSTEP and
the relevant control options (such as CSHUNT or GSHUNT).
Figure 59
Iteration Algorithm
Initial Guess
Element Evaluation
I.V.Q. Flux
Linearization of non-linear elements
Element Convergence Test
Gear or Trapezoidal
ABSI
RELI
ABSMOS
RELMOS
METHOD
MAXORD
GMIN
Assemble and Solve Matrix Equations
PIVOT
PIVREL
PIVTOL
ABSV
FAIL
Nodal Voltage Convergence Test
RELV
NEWTOL
Converged
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Numerical Integration Algorithm Controls (HSPICE RF)
Numerical Integration Algorithm Controls (HSPICE RF)
In HSPICE RF, you can select either the Backward-Euler or Trapezoidal
integration algorithm. Each of these algorithms has its own advantages and
disadvantages for specific circuit types. For pre-charging simulation or timing
critical simulation, the Trapezoidal algorithm usually improves accuracy.
x
Default value = 1.9
In this syntax, x is a real number between 1.0 and 2.0.
Note: SIM_ORDER has precedence over SIM_TRAP.
■
A higher order is more accurate, especially with inductors (such as crystal
oscillators), which need SIM_ORDER = 2.0.
■
A lower order has more damping.
Setting SIM_ORDER to its lowest value, as in the example below, selects
the Backward-Euler integration algorithm.
.OPTION SIM_ORDER = 1.0
Selecting Timestep Control Algorithms
In HSPICE or HSPICE RF, you can select one of three dynamic timestepcontrol algorithms:
■
Iteration Count Dynamic Timestep Algorithm
■
Local Truncation Error (LTE) Dynamic Timestep
■
DVDT Dynamic Timestep Algorithm
Each algorithm uses a dynamically-changing timestep, which increases the
accuracy of simulation, and reduces the simulation time. To do this, simulation
varies the value of the timestep, over the transient analysis sweep, depending
on the stability of the output. Dynamic timestep algorithms increase the
timestep value when internal nodal voltages are stable, and decrease the
timestep value when nodal voltages change quickly.
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Figure 60
Internal Variable Timestep
Changing Time Step - Dynamic
∆tD-1
∆tD
The LVLTIM option selects the timestep algorithm:
■
LVLTIM = 0 selects the iteration count algorithm.
■
LVLTIM = 1 selects the DVDT timestep algorithm, and the iteration count
algorithm. To control operation of the timestep control algorithm, set the
DVDT control option. For LVLTIM = 1 and DVDT = 0, 1, 2, or 3, the algorithm
does not use timestep reversal. For DVDT = 4, the algorithm uses timestep
reversal.
For more information about the DVDT algorithm, see DVDT Dynamic
Timestep Algorithm on page 368.
■
LVLTIM = 2 selects the truncation timestep algorithm, and the iteration count
algorithm (with reversal).
■
LVLTIM = 3 selects the DVDT timestep algorithm (with timestep reversal),
and the iteration count algorithm. For LVLTIM = 3 and DVDT = 0, 1, 2, 3, or
4, the algorithm uses timestep reversal.
If HSPICE or HSPICE RF starts the autoconvergence process, it sets
LVLTIM = 2.
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Iteration Count Dynamic Timestep Algorithm
The simplest dynamic timestep algorithm is the iteration count
algorithm. .OPTION IMAX and .OPTION IMIN control this algorithm.
Local Truncation Error (LTE) Dynamic Timestep
The local truncation error timestep method uses a Taylor-series approximation,
to calculate the next timestep for a transient analysis. This method uses the
allowed local truncation error, to calculate an internal timestep. If the calculated
timestep is smaller than the current timestep, HSPICE or HSPICE RF sets back
the timepoint (timestep reversal), and uses the calculated timestep to
increment the time. If the calculated timestep is larger than the current
timestep, then HSPICE or HSPICE RF does not reverse the timestep. The next
timepoint uses a new timestep.
To select the timestep algorithm for local truncation error, set LVLTIM = 2 or
METHOD=GEAR. The control options, available with the algorithm for local
truncation error, are:
TRTOL (default = 7)
CHGTOL (default = 1e-15)
RELQ (default = 0.01)
For some circuits (such as magnetic core circuits), GEAR and LTE provide
more accurate result than TRAP. You can use this method with circuits
containing inductors, diodes, BJTs (even Level 4 and above), MOSFETs, or
JFETs.
DVDT Dynamic Timestep Algorithm
To select this algorithm, set the LVLTIM option to 1 or 3.
■
368
If you set LVLTIM = 1, the DVDT algorithm does not use timestep reversal.
HSPICE or HSPICE RF saves the results for the current timepoint, and uses
a new timestep for the next timepoint.
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■
If you set LVLTIM = 3, the algorithm uses timestep reversal. If the results do
not converge at a specified iteration, HSPICE or HSPICE RF ignores the
results of the current timepoint, sets back the time by the old timestep, and
then uses a new timestep. Therefore, LVLTIM = 3 is more accurate, and
more time-consuming, than LVLTIM = 1.
This algorithm uses different tests, to decide whether to reverse the
timestep, depending on how you set the DVDT control option.
■
For DVDT = 0, 1, 2, or 3, the decision is based on the SLOPETOL control
option.
■
For DVDT = 4, the decision is based on how you set the SLOPETOL,
RELVAR, and ABSVAR control options.
The DVDT algorithm calculates the internal timestep, based on the rate of
nodal voltage changes.
■
For circuits with rapidly-changing nodal voltages, the DVDT algorithm uses
a small timestep.
■
For circuits with slowly-changing nodal voltages, the DVDT algorithm uses
larger timesteps.
The DVDT = 4 setting selects a timestep control algorithm for non-linear node
voltages. If you set the LVLTIM option to either 1 or 3, then DVDT = 4 also uses
timestep reversals. To measure non-linear node voltages, HSPICE or HSPICE
RF measures changes in slopes of the voltages. If the change in slope is larger
than the SLOPETOL control setting, simulation reduces the timestep by the
factor set in the FT control option. The FT option defaults to 0.25.
HSPICE or HSPICE RF sets the SLOPETOL value to 0.75 for LVLTIM = 1, and
to 0.50 for LVLTIM = 3. Reducing the value of SLOPETOL increases simulation
accuracy, but also increases simulation time.
■
For LVLTIM = 1, SLOPETOL and FT control simulation accuracy.
■
For LVLTIM = 3, the RELVAR and ABSVAR control options also affect the
timestep, and therefore affect the simulation accuracy.
Use .OPTION RELVAR and .OPTION ABSVAR with the DVDT option to
improve simulation time or accuracy. For faster simulation time, increase
RELVAR and ABSVAR (but this might decrease accuracy).
Note: If you need backward compatibility with HSPICE Release 95.3, use these
options. Setting .OPTION DVDT = 3 automatically sets all of these values.
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LVLTIM = 1 RMAX = 2 SLOPETOL = 0.5
FT = FS = 0.25 BYPASS = 0 BYTOL = 0.050
Timestep Controls in HSPICE
The RMIN, RMAX, FS, FT, and DELMAX control options define the minimum and
maximum internal timestep for the DVDT algorithm. If the timestep is below the
minimum, program execution stops.
Example
If the timestep becomes less than the minimum internal timestep (defined as
TSTEP x RMIN), HSPICE reports an internal timestep too small error.
Note: RMIN is the minimum timestep coefficient. Default is 1e-9. TSTEP is the
time increment set in the .TRAN statement.
If you set .OPTION DELMAX, HSPICE uses DVDT = 0. If you do not
specify .OPTION DELMAX, then HSPICE computes a DELMAX value. For
DVDT = 0, 1, or 2, the maximum internal timestep is:
min[(TSTOP/50), DELMAX, (TSTEPxRMAX)]
The TSTOP time is the transient sweep range, as set in the .TRAN statement.
One exception is in the autospeedup process. When dealing with large nonlinear circuit with very big TSTOP or TSTEP values (for example, .TRAN 1n 1),
HSPICE might activate autospeedup. This process automatically sets RMAX to
a bigger value, and sets the maximum internal timestep to:
min[(TSTOP/20),(TSTEPxRMAX)]
Set TRCON=-1 to disable autospeedup. You can then adjust TSTEP and RMAX,
to balance accuracy and speed.
In circuits with piecewise linear (PWL) transient sources, then
.OPTION SLOPETOL also affects the internal timestep. A PWL source, with a
large number of voltage or current segments, contributes a correspondinglylarge number of entries to the internal breakpoint table. The number of
breakpoint table entries contributes to the internal timestep control.
If the difference in the slope for consecutive segments of a PWL source, is less
than the SLOPETOL value, then HSPICE ignores the breakpoint table entry for
the point between the segments. For a PWL source, with a signal that changes
value slowly, ignoring its breakpoint table entries can help reduce the
simulation time. Data in the breakpoint table is a factor in the internal timestep
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control, so setting a high SLOPETOL reduces the number of usable breakpoint
table entries, which reduces the simulation time.
Timestep Control in HSPICE RF
This section describes Timestep Control options in HSPICE RF.
■
The default time step method mixes Trapezoidal and Gear-2. This yields a
more accurate scheme than Trapezoidal and BE.
■
Detection of numerical oscillations inserts fewer BE steps than in previous
HSPICE versions.
.OPTION SIM_ACCURACY
To modify the size of timesteps in HSPICE RF, use the SIM_ACCURACY option.
A timestep is a time interval at which you evaluate a signal. HSPICE RF
discretely expresses the time continuum as a series of points. At each point or
timestep, a circuit simulator evaluates the corresponding voltage or current
value of a signal. Thus, a resulting signal waveform is a series of individual data
points; connecting these points results in a smooth curve.
Syntax
.OPTION SIM_ACCURACY = value
Default value = 1
where value is a positive number. If you specify .OPTION ACCURATE, then the
default value is 10. This option applies to all modes. SIM_ACCURACY tightens
all tolerances, such as:
■
Newton-Raphson tolerance.
■
Local truncation error.
■
Other errors.
The default is calibrated to provide good out-of-the-box accuracy, with good
performance.
You can apply different accuracy settings to different blocks or time intervals. To
set global accuracy, use:
.OPTION SIM_ACCURACY = n
In this syntax, n is a number greater than 0. The syntax to set accuracy on a
block, instance, or time interval is similar to SIM_V_SUPPLY.
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Example
This example sets accuracy to 3 for the XNAND1 and XNAND2 instances, and
accuracy to 4 for all instances of the INV subcircuit. Globally, the accuracy is 2.
If accuracy settings conflict, then HSPICE RF uses the higher accuracy value.
At 12.0ns before the end of the simulation, the global accuracy level is 5.
Because this is higher than 2, 3, or 4, it overrides all previous settings.
.OPTION SIM_ACCURACY = 2
.OPTION SIM_ACCURACY =
.OPTION SIM_ACCURACY =
.OPTION SIM_ACCURACY =
.OPTION SIM_ACCURACY =
.OPTION SIM_ACCURACY =
.OPTION SIM_ACCURACY =
“3
“4
“5
“5
“3
“5
|
|
|
|
|
|
XNAND1 XNAND2”
@INV”
12.0n”
20n”
40ns”
20ns 3 | 35ns 7 | 50ns”
Default value = infinity.
Note: SIM_ACCURACY has precedence over ACCURATE.
.OPTION METHOD
To select a timestep control option, select the METHOD option.
HSPICE RF supports three basic time step algorithms: Trapezoidal, secondorder Gear (Gear-2), and Backward Euler (BE). BE is the same as first-order
Gear. HSPICE RF also supports a hybrid algorithm, which is a mixture of the
three basic algorithms.
HSPICE RF contains an algorithm for auto-detection of numerical oscillations
commonly encountered with trapezoidal integration. If HSPICE RF detects
such oscillations, it inserts BE steps, but not more than one BE step for every
10 time steps. To turn off auto-detection, use the PURETP option.
Syntax
.OPTION METHOD = [TRAP | GEAR | TRAPGEAR]
372
■
TRAP selects the trapezoidal algorithm.
■
GEAR selects the Gear algorithm.
■
TRAPGEAR (default) selects a hybrid method.
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.OPTION MAXORD
Selects the maximum order of integration for the GEAR method.
■
1=first-order Gear (Backward Euler).
■
2=second-order Gear (Gear-2)
.OPTION SIM_ORDER
Controls the amount of BE to mix with the Trapezoidal method for hybrid
integration. It affects time stepping when you set method to trap or trapgear.
■
SIM_ORDER=1 is BE.
■
SIM_ORDER=2 (default) is Trapezoidal.
■
Any real number from 1 to 2 is valid.
.OPTION SIM_TG_THETA
For the hybrid TRAPGEAR method, controls the amount of Gear-2 method to
mix with trapezoidal integration. Default=0.1.
■
SIM_TG_THETA=0 selects trapezoidal without Gear-2.
■
SIM_TG_THETA=1 selects pure Gear-2.
■
Any real number from 0 to 1 is valid.
.OPTION SIM_TRAP
Changes the default SIM_TG_THETA to 0, so that method=trapgear acts like
METHOD=TRAP. You can set this flag to 0 (default) or 1.
.OPTION PURETP
Turns off insertion of BE steps, due to auto-detection of numerical oscillations.
You can set this flag to 0 (default) or 1.
.OPTION SIM_OSC_DETECT_TOL
Tolerance for detecting numerical oscillations. If HSPICE RF detects numerical
oscillations, it inserts BE steps. Smaller values of this tolerance result in fewer
BE steps. Default=10-8.
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Examples
The default behavior is a hybrid method, combining 90% trapezoidal with 10%
Gear-2. HSPICE RF inserts BE steps, when the simulator encounters a
breakpoint, or when the auto-detection algorithm finds numerical oscillations.
Example 1
.option method=trap purept
This option sets pure trapezoidal method integration. No Gear-2 or BE is mixed
in. Use this setting when you simulate harmonic oscillators.
Example 2
.option method=gear maxord=1
Sets pure Backward Euler integration.
Example 3
.option method=trap sim_order=1
Sets pure Backward Euler integration.
Example 4
.option method=gear
Sets pure Gear-2 integration.
Example 5
.option sim_order=1.9
This causes a mixture of 10% Gear-2 and 90% BE-trapezoidal hybrid
integration. The BE-trapezoidal part is 10% BE.
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Fourier Analysis
Fourier Analysis
This section describes the Fourier and FFT Analysis flow for HSPICE.
Figure 61
Fourier and FFT Analysis
.FOUR Statement
Transient
Time-sweep
simulation
.FFT
.FOUR
Output Variables
Display Options
.FFT Statement
Transient
Output Variable
V
I
Time-sweep
simulation
.FFT
.FOUR
Display Option
P
Other
Window
Format
HSPICE provides two different Fourier analyses, but HSPICE RF does not
support either type of Fourier analysis:
■
.FOUR is the same as is available in SPICE 2G6: a standard, fixed-window
analysis tool. The .FOUR statement performs a Fourier analysis, as part of
the transient analysis.
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Fourier Analysis
■
.FFT is a much more flexible Fourier analysis tool. Use it for analysis tasks
that require more detail and precision.
Accuracy and DELMAX
For better accuracy, set small values for .OPTION RMAX or
.OPTION DELMAX. For maximum accuracy, set .OPTION DELMAX to (period/
500). For circuits with very high resonance factors (high-Q circuits, such as
crystal oscillators, tank circuits, and active filters), set DELMAX to less than
(period/500).
Fourier Equation
The total harmonic distortion is the square root of the sum of the squares, of
the second through ninth normalized harmonic, times 100, expressed as a
percent:
 9

1

2
-----⋅
THD =
R 
R1  ∑ m
m = 2 
1/2
⋅ 100%
This interpolation can result in various inaccuracies.
Example
If the transient analysis runs at intervals longer than 1/(501*f), then the
frequency response of the interpolation dominates the power spectrum.
Furthermore, this interpolation does not derive an error range for the output.
The following equation calculates the Fourier coefficients:
9
g( t) =
9
∑
m=0
C m ⋅ cos ( mt ) +
∑
D m ⋅ sin ( mt )
m=0
The following equations calculate values for the preceding equation:
π
Cm
1
= --- ⋅
π
∫ g ( t ) Þ cos ( m ⋅ t ) Þdt
–π
π
Dm
376
1
= --- ⋅
π
∫ g ( t ) Þ sin ( m ⋅ t ) Þdt
–π
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Fourier Analysis
9
g( t) =
9
∑
C m ⋅ cos ( m ⋅ t ) +
m=0
∑
D m ⋅ sin ( m ⋅ t )
m=0
The following equations approximate the C and D values:
500
Cm =
2⋅π⋅m⋅n
-
∑ g ( n ⋅ ∆ t ) ⋅ cos  -------------------------501 
n=0
500
Dm =
2⋅π⋅m⋅n
-
∑ g ( n ⋅ ∆ t ) ⋅ sin  -------------------------501 
n=0
The following equations calculate the magnitude and phase:
R m = ( C m2 + D m2 ) 1 / 2
Cm
Φ m = arctan  -------
 D m
Example 1
The following is input for an .OP, .TRAN, or .FOUR analysis.
You can find the sample netlist for this example in the following directory:
$installdir/demo/hspice/apps/four.sp
Example 2
******
cmos inverter
**** fourier analysis
tnom = 25.000 temp = 25.000 ****
fourier components of transient response v(2)
dc component = 2.430D+00
harmonic
no
1
2
3
frequency fourier
(hz)
component
20.0000x
40.0000x
60.0000x
3.0462
115.7006m
753.0446m
4
80.0000x
77.8910m
5
100.0000x
296.5549m
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normalized phase
component (deg)
1.0000
176.5386
37.9817m -106.2672
247.2061m
normalized
phase (deg)
0.
-282.8057
170.7288
-5.8098
25.5697m -125.9511
-302.4897
97.3517m
164.5430
-11.9956
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Fourier Analysis
6
120.0000x
50.0994m
16.4464m -148.1115
7
140.0000x
125.2127m
41.1043m
157.7399
-18.7987
8
160.0000x
25.6916m
8.4339m
172.9579
-3.5807
9
180.0000x
47.7347m
15.6701m
154.1858
-22.3528
total harmonic distortion =
27.3791
-324.6501
percent
Spectrum analysis represents a time-domain signal, within the frequency
domain. It most commonly uses the Fourier transform. A Discrete Fourier
Transform (DFT) uses sequences of time values to determine the frequency
content of analog signals, in circuit simulation.
The Fast Fourier Transform (FFT) calculates the DFT, which Synopsys HSPICE
uses for spectrum analysis. The .FFT statement uses the internal time point
values.
By default, .FFT uses a second-order interpolation to obtain waveform
samples, based on the number of points that you specify.
You can use windowing functions to reduce the effects of waveform truncation
on the spectral content. You can also use the .FFT command to specify:
378
■
output format
■
frequency
■
number of harmonics
■
total harmonic distortion (THD)
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AC Sweep and Small Signal Analysis
01
Describes how to perform AC sweep and small signal analysis.
This chapter covers AC small signal analysis, AC analysis of an RC network,
and other AC analysis statements. For information on output variables, see AC
Analysis Output Variables on page 260.
For descriptions of individual HSPICE commands referenced in this chapter,
see the HSPICE Command Reference.
Using the .AC Statement
You can use the .AC statement for the following applications:
■
Single/double sweeps
■
Sweeps using parameters
■
.AC analysis optimization
■
Random/Monte Carlo anlayses
See the HSPICE Command Reference for .AC command syntax and examples
of all these applications.
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AC Small Signal Analysis
.AC Control Options
You can use the following .AC control options when performing an AC analysis:
■
ABSH
■
ACOUT
■
DI
■
MAXAMP
■
RELH
■
UNWRAP
See “Options in HSPICE Netlists” in the HSPICE Command Reference for
these AC control options syntax.
AC Small Signal Analysis
AC small signal analysis in HSPICE or HSPICE RF computes AC output
variables as a function of frequency (see Figure 62). HSPICE or HSPICE RF
first solves for the DC operating point conditions. It then uses these conditions
to develop linear, small-signal models for all non-linear devices in the circuit.
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AC Small Signal Analysis
Figure 62
AC Small Signal Analysis Flow
Simulation Experiment
DC
Transient
Other AC analysis
statements
AC
AC small-signal
simulation
.NOISE
.DISTO
.SAMPLE
.NETWORK
.OPTION:
Method
DC options, to solve
operating-point
ABSH
ACOUT
DI
MAXAMP
RELH
UNWRAP
In HSPICE or HSPICE RF, the output of AC Analysis includes voltages and
currents.
HSPICE or HSPICE RF converts capacitor and inductor values to their
corresponding admittances:
y C = j ω C for capacitors
1
y L = --------for inductors
jωL
Resistors can have different DC and AC values. If you specify AC = <value> in
a resistor statement, HSPICE or HSPICE RF uses the DC value of resistance
to calculate the operating point, but uses the AC resistance value in the AC
analysis. When you analyze operational amplifiers, HSPICE or HSPICE RF
uses a low value for the feedback resistance to compute the operating point for
the unity gain configuration. You can then use a very large value for the AC
resistance in AC analysis of the open loop configuration.
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AC Analysis of an RC Network
AC analysis of bipolar transistors is based on the small-signal equivalent circuit,
as described in the HSPICE Elements and Device Models Manual. MOSFET
AC-equivalent circuit models are described in the HSPICE Elements and
Device Models Manual.
The AC analysis statement can sweep values for:
■
Frequency.
■
Element.
■
Temperature.
■
Model parameter (HSPICE and HSPICE RF).
■
Randomized (Monte Carlo) distribution (HSPICE only; not supported in
HSPICE RF).
■
Optimization and AC analysis (HSPICE or HSPICE RF).
Additionally, as part of the small-signal analysis tools, HSPICE or HSPICE RF
provides:
■
Noise analysis.
■
Distortion analysis.
■
Network analysis.
■
Sampling noise.
You can use the .AC statement in several different formats, depending on the
application. You can also use the .AC statement to perform data-driven
analysis in HSPICE, but not in HSPICE RF.
AC Analysis of an RC Network
Figure 63 shows a simple RC network with a DC and AC source applied. The
circuit consists of:
382
■
Two resistors, R1 and R2.
■
Capacitor C1.
■
Voltage source V1.
■
Node 1 is the connection between the source positive terminal and R1.
■
Node 2 is where R1, R2, and C1 are connected.
■
HSPICE ground is always node 0.
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AC Analysis of an RC Network
Figure 63
RC Network Circuit
1
R1
1k
V1
10 VDC
1VAC
2
+
_
R2
1k
C1
0.001 mF
0
The input netlist for the RC network circuit is:
A SIMPLE AC RUN
.OPTION LIST NODE POST
.OP
.AC DEC 10 1K 1MEG
.PRINT AC V(1) V(2) I(R2) I(C1)
V1 1 0 10 AC 1
R1 1 2 1K
R2 2 0 1K
C1 2 0 .001U
.END
You can find the complete netlist for this example in the following directory:
$installdir/demo/hspice/apps/quickAC.sp
Follow the procedure below to perform AC analysis for an RC network circuit.
1. Type the above netlist into a file named quickAC.sp.
2. To run a HSPICE analysis, type:
hspice quickAC.sp > quickAC.lis
For HSPICE RF, type:
hspicext quickAC.sp > quickAC.lis
When the run finishes, HSPICE displays:
>info:
***** hspice job concluded
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AC Analysis of an RC Network
This is followed by a line that shows the amount of real time, user time, and
system time needed for the analysis.
Your run directory includes the following new files:
•
quickAC.ac0
•
quickAC.ic0
•
quickAC.lis
•
quickAC.st0
3. Use an editor to view the .lis and .st0 files to examine the simulation results
and status.
4. Run AvanWaves and open the .sp file.
5. To view the waveform, select the quickAC.ac0 file from the Results Browser
window.
6. Display the voltage at node 2 by using a log scale on the x-axis.
Figure 64 shows the waveform that HSPICE or HSPICE RF produces if you
sweep the response of node 2, as you vary the frequency of the input from 1
kHz to 1 MHz.
Figure 64
RC Network Node 2 Frequency Response
A simple AC run
04/14/2003 16:52:48
500.0m
quickAC.ac
2*m
volt maglin
450.0m
400.0m
350.0m
300.0m
250.0m
200.0m
151.657m
1.0k
10.0k
100.k
1.0x
hertz (log)
As you sweep the input from 1 kHz to 1 MHz, the quickAC.lis file displays:
384
■
Input netlist.
■
Details about the elements and topology.
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Other AC Analysis Statements
■
Operating point information.
■
Table of requested data.
The quickAC.ic0 file contains information about DC operating point conditions.
The quickAC.st0 file contains information about the simulation run status.
To use the operating point conditions for subsequent simulation runs, execute
the .LOAD statement (HSPICE only; HSPICE RF does not support the .LOAD
statement).
Other AC Analysis Statements
You can use the following commands to perform other types of AC analyses:
■
Using .DISTO for Small-Signal Distortion Analysis
■
Using .NOISE for Small-Signal Noise Analysis
■
Using .SAMPLE for Noise Folding Analysis
Use the .NOISE and .AC statements to control the noise analysis of the circuit.
Using .DISTO for Small-Signal Distortion Analysis
The .DISTO statement computes the distortion characteristics of the circuit in
an AC small-signal, sinusoidal, steady-state analysis. HSPICE computes and
reports five distortion measures at the specified load resistor. The analysis is
performed assuming that one or two signal frequencies are imposed at the
input. The first frequency, F1 (used to calculate harmonic distortion), is the
nominal analysis frequency set by the .AC statement frequency sweep. The
optional second input frequency, F2 (used to calculate intermodulation
distortion), is set implicitly by specifying the skw2 parameter, which is the ratio
F2/F1.
See .DISTO in the HSPICE Command Reference for command syntax and
examples.
Using .NOISE for Small-Signal Noise Analysis
Noise calculations in HSPICE or HSPICE RF are based on complex AC nodal
voltages, which in turn are based on the DC operating point. For descriptions of
noise models for each device type, see the HSPICE Elements and Device
Models Manual. Each noise source does not statistically correlate to other
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Other AC Analysis Statements
noise sources in the circuit; the HSPICE or HSPICE RF simulator calculates
each noise source independently. The total output noise voltage is the RMS
sum of the individual noise contributions:
N
onoise =
∑
2
Zk i nk
2
k=0
Parameter
Description
onoise
Total output noise(HSPICE or HSPICE RF).
ink
Normal current source due to thermal, shot, or other noise.
Zk
Equivalent transimpedance between each noise current source and
output.
N
Number of noise sources associated with all circuit elements.
The input noise (inoise) voltage is the total output noise divided by the gain or
transfer function of the circuit. HSPICE or HSPICE RF prints the contribution of
each noise generator in the circuit for each inter frequency point. The simulator
also normalizes the output and input noise levels relative to the square root of
the noise bandwidth. The units are volts/Hz1/2 or amps/Hz1/2.
To simulate flicker noise sources in the noise analysis, include values for the KF
and AF parameters on the appropriate device model statements. Use
the .PRINT or .PLOT statement to print or plot output noise, and the
equivalent input noise.
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Other AC Analysis Statements
If you specify more than one .NOISE statement in a single simulation, HSPICE
or HSPICE RF runs only the last statement.
Table 51 .NOISE Measurements Available for MOSFETs
.ac
.lis
Unit
Description
nd
rd
2
V
------Hz
Output thermal noise due to drain resistor
ns
rs
2
V
------Hz
Output thermal noise due to source resistor
ni
id
2
V
------Hz
Output channel thermal noise
nf
fn
2
V
------Hz
Output flicker noise
ntg
total
2
V
------Hz
Total output noise:
TOT = RD + RS + ID + FN
Using .SAMPLE for Noise Folding Analysis
For data acquisition of analog signals, data sampling noise often needs to be
analyzed. This is accomplished with the .SAMPLE statement used in
conjunction with the .NOISE and .AC statements. The SAMPLE analysis
performs a simple noise folding analysis at the output node.
See “.SAMPLE” in the HSPICE Command Reference for the command syntax.
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Other AC Analysis Statements
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Linear Network Parameter Analysis
11
Describes how to perform an AC sweep to extract small-signal linear
network parameters.
The chapter covers .LIN analysis, RF measurements from .LIN, extracting
mixed-mode S (scattering) parameters, and .NET parameter analysis.
For descriptions of individual HSPICE commands referenced in this chapter,
see the HSPICE Command Reference manual.
.LIN Analysis
The .LIN command extracts noise and linear transfer parameters for a general
multi-port network.
When used with the .AC command, .LIN makes available a broad set of
linear port-wise measurements:
■
Multi-port scattering [S] parameters
■
Noise parameters
■
Stability factors
■
Gain factors
■
Matching coefficients
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.LIN Analysis
The .LIN analysis is similar to basic small-signal, swept-frequency .AC
analysis, but it also automatically calculates a series of noise and small-signal
transfer parameters between the terminals identified using port (P) elements.
HSPICE can output the result of group delay extraction and two-port noise
analysis to either a .sc* file, a TOUCHSTONE file, or a CITIfile.
The .PRINT/.PROBE/.MEAS output syntax for .LIN supports H (hybrid)
parameters and S/Y/Z/H group delay.
Figure 65
Basic Circuit in .LIN Analysis
I1
Z01
P1
I2
+
V1
-
Circuit
under
test
+
V2
P2
Z02
-
Identifying Ports with the Port Element
The .LIN command computes the S (scattering), Y (admittance), and Z
(impedance) parameters directly based on the location of the port (P) elements
in your circuit, and the specified values for their reference impedances.
The port element identifies the ports used in .LIN analysis. Each port element
requires a unique port number. If your design uses N port elements, your netlist
must contain the sequential set of port numbers 1 through N (for example, in a
design containing 512 ports, you must number each port sequentially 1 to 512).
Each port has an associated system impedance, z0. If you do not explicitly
specify the system impedance, the default is 50 ohms.
The port element behaves as either a noiseless impedance or a voltage source
in series with the port impedance for all other analyses (DC, AC, or TRAN).
390
■
You can use this element as a pure terminating resistance or as a voltage or
power source.
■
You can use the RDC, RAC, RHB, RHBAC, and rtran values to override the port
impedance value for a particular analysis.
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.LIN Analysis
Syntax
Pxxx p n port=portnumber
+ $ **** Voltage or Power Information ********
+ <DC mag> <AC <mag <phase>>> <HBAC <mag <phase>>>
+ <HB <mag <phase <harm <tone <modharm <modtone>>>>>>>
+ <transient_waveform> <TRANFORHB=[0|1]>
+ <DCOPEN=[0|1]>
+ $ **** Source Impedance Information ********
+ <Z0=val> <RDC=val> <RAC=val>
+ <RHBAC=val> <RHB=val> <RTRAN=val>
+ $ **** Power Switch ********
+ <power=[0|1|2|W|dbm]>
Parameter
Description
port=portnumber
The port number. Numbered sequentially beginning with
1 with no shared port numbers.
<DC mag>
DC voltage or power source value.
<AC <mag <phase>>>
AC voltage or power source value.
<HBAC <mag <phase>>>
(HSPICE RF) HBAC voltage or power source value.
<HB <mag <phase <harm
<tone <modharm
<modtone>>>>>>>
(HSPICE RF) HB voltage, current, or power source
value. Multiple HB specifications with different harm,
tone, modharm, and modtone values are allowed.
• phase is in degrees
• harm and tone are indices corresponding to the
tones specified in the .HB statement. Indexing starts
at 1 (corresponding to the first harmonic of a tone).
• modtone and modharm specify sources for multitone simulation. A source specifies a tone and a
harmonic, and up to 1 offset tone and harmonic
(modtone for tones and modharm for harmonics).
The signal is then described as:
V(or I) = mag*cos(2*pi*
(harm*tone+modharm*modtone)*t + phase)
<transient_waveform>
(Transient analysis) Voltage or power source waveform.
Any one of waveforms: AM, EXP, PULSE, PWL, SFFM, or
SIN. Multiple transient descriptions are not allowed.
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.LIN Analysis
Parameter
Description
<TRANFORHB=[0|1]>
• 0 (default): The transient description is ignored if an
HB value is given or a DC value is given. If no DC or
HB value is given and TRANFORHB=0, then HB
analysis treats the source as a DC source, and the
DC source value is the time=0 value.
• 1: HB analysis uses the transient description if its
value is VMRF, SIN, PULSE, PWL, or LFSR. If the type
is a non-repeating PWL source, then the
time=infinity value is used as a DC analysis
source value. For example, the following statement is
treated as a DC source with value=1 for HB
analysis:
v1 1 0 PWL (0 0 1n 1 1u 1)
+ TRANFORHB=1
In contrast, the following statement is a 0V DC
source:
v1 1 0 PWL (0 0 1n 1 1u 1)
+ TRANFORHB=0
The following statement is treated as a periodic
source with a 1us period that uses PWL values:
v1 1 0 PWL (0 0 1n 1 0.999u 1 1u 0) R
+ TRANFORHB=1
To override the global TRANFORHB option, explicitly set
TRANFORHB for a voltage or current source.
DCOPEN
Switch for open DC connection when DC mag is not set.
• 0 (default): P element behaves as an impedance
termination.
• 1 : P element is considered an open circuit in DC
operating point analysis. DCOPEN=1 is mainly used in
.LIN analysis so the P element will not affect the
self-biasing device under test by opening the
termination at the operating point.
<z0=val>
(LIN analysis) System impedance used when converting
to a power source, inserted in series with the voltage
source. Currently, this only supports real impedance.
• When power=0, z0 defaults to 0.
• When power=1, z0 defaults to 50 ohms.
You can also enter zo=val.
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.LIN Analysis
Parameter
Description
<RDC=val>
(DC analysis) Series resistance (overrides z0).
<RAC=val>
(AC analysis) Series resistance (overrides z0).
<RHBAC=val>
(HSPICE RF HBAC analysis) Series resistance
(overrides z0).
<RHB=val>
(HSPICE RF HB analysis) Series resistance (overrides
z0).
<RTRAN=val>
(Transient analysis) Series resistance (overrides z0).
<power=[0 | 1 | 2 | W | dbm]> (HSPICE RF) power switch
• When 0 (default), element treated as a voltage or
current source.
• When 1 or W, element treated as a power source,
realized as a voltage source with a series impedance.
In this case, the source value is interpreted as RMS
available power in units of Watts.
• When 2 or dbm, element treated as a power source in
series with the port imedance. Values are in dbms.
You can use this parameter for Transient analysis if the
power source is either DC or SIN.
Example
For example, the following port element specifications identify a 2-port network
with 50-Ohm reference impedances between the "in" and "out" nodes.
P1 in gnd port=1 z0=50
P2 out gnd port=2 z0=50
Computing scattering parameters requires z0 reference impedance values.
The order of the port parameters (in the P Element) determines the order of
the S, Y, and Z parameters. Unlike the .NET command, .LIN does not require
you to insert additional sources into the circuit. To calculate the requested
transfer parameters, HSPICE automatically inserts these sources as needed at
the port terminals. You can define an unlimited number of ports.
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.LIN Analysis
Using the P (Port) Element for Mixed-Mode Measurement
You can use a port element with three terminals as the port element for
measuring the mixed mode S parameters. Except for the number of external
terminals, the syntax of the port element remains the same. The .LIN analysis
function internally sets the necessary drive mode (common/differential) of
these mixed mode port elements. For analyses other than the .LIN analysis
(such as DC, AC, TRAN, and so on), the mixed-mode P Element acts as a
differential driver that drives positive nodes with half of their specified voltage
and the negative nodes with a negated half of the specified voltage. Figure 66
shows the block diagram of the mixed mode port element.
Figure 66
Mixed Mode Port Element
P1 (port element)
n1+
Zo
Zo
V+
Vn2-
n1_ref
P1 n1+ n1- n1_ref Zo=50
The port element can also be used as a signal source with a built in reference
impedance. For further information on its use as a signal source, see Chapter
5, “Sources and Stimuli.”
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.LIN Analysis
.LIN Input Syntax
For the .LIN command syntax, see the HSPICE Command Reference.
.LIN Output Syntax
.PRINT | PROBE | AC PARAM(TYPE) ...
■
PARAM can be:
Xmn | X(m,n) | LINPARAM
■
X can be:
S | Y | Z | H
■
mn refers to a pair of port numbers, where m can be 1 or 2, and n can be 1
or 2.
■
LINPARAM can be:
NFMIN,GAMMA_OPT,ZOPT,RN,K_STABILITY_FACTOR,G_MAX,
G_MAX_S_OPT,G_MAX_L_OPT,NF,G_AS,VSWR(n),GD
■
TYPE can be:
R,I,M,P,PD,PR,DB,DBM
■
In the .PRINT or .PROBE output syntax for .LIN, you can include complex
two-port hybrid (H-) parameters:
Hmn | Hmn(TYPE) | H(m,n) | H(m,n)(TYPE)
m = 1 or 2
n = 1 or 2
TYPE = R, I, M, P, PD, PR, or DB
If m,n=0 or m,n>2, HSPICE issues a warning and ignores the output request.
■
To calculate a one-port H parameter, you must specify at least one port (P)
element.
■
To calculate a two-port H parameter, you must specify two or more port
elements.
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.LIN Analysis
The hybrid parameters are transformed from S-parameters:
■
For a one-port circuit, the calculation is:
( 1 + S 11 )
H 11 = Z 01 --------------------( 1 – S 11 )
■
For a two-port circuit, the calculation is:
( 1 + S 11 ) ( 1 + S n ) – S 12 S 21
H 11 = Z 01 --------------------------------------------------------------( 1 – S 11 ) ( 1 + S n ) + S 12 S 21
H 12 =
2S 12
Z 02
-------- -----------------------------------------------------------------Z 01 ( 1 – S 11 ) ( 1 + S 22 ) + S 12 S 21
H 21 =
– S 21
Z 02
-------- -----------------------------------------------------------------Z 01 ( 1 – S 11 ) ( 1 + S 22 ) + S 12 S 21
1 ( 1 – S 11 ) ( 1 – S 22 ) – S 12 S 21
H 22 = -------- -----------------------------------------------------------------Z 02 ( 1 – S 11 ) ( 1 + S 22 ) + S 12 S 21
For networks with more than two ports when computing the 1,2 H index
parameters, HSPICE assumes that ports numbered 3 and above terminate in
their port reference impedance (z0). The above two-port calculations therefore
remain appropriate, because S11, S12, S21, and S22 remain valid, and
simulation can ignore higher order S-parameters.
PARAM Definitions
396
■
S (scattering parameters)
■
Y (admittance parameters)
■
Z (impedance parameters)
■
H (hybrid parameters)
■
NFMIN (noise figure minimum)
■
NF (Noise figure)
■
VN2 (Equivalent input noise voltage squared
■
IN2 (Equivalent input noise current squared)
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.LIN Analysis
■
RHON (Correlation coefficient between input noise voltage and input noise
current)
■
RN (Noise equivalent resistance)
■
GN (Noise equivalent conductance)
■
ZCOR (Noise correlation impedance)
■
YCOR (Noise correlation admittance)
■
ZOPT (Optimum source impedance for noise)
■
YOPT (Optimum source admittance for noise)
■
GAMMA_OPT (source reflection coefficient that achieves the minimum
noise figure)
■
ZOPT (source impedance which achieves minimum noise)
■
RN (noise equivalent resistance)
■
K_STABILITY_FACTOR (Rollett stability factor)
■
MU_STABILITY_FACTOR (Edwards & Sinsky stability factor)
■
G_MAX (maximum available/operating power gain)
■
G_MSG (Maximum stable gain)
■
G_TUMAX (Maximum unilateral transducer power gain)
■
G_U (Unilateral power gain)
■
G_MAX_GAMMA1 (source reflection coefficient which achieves maximum
available power gain)
■
G_MAX_GAMMA2 (load reflection coefficient which achieves maximum
operating power gain)
■
G_MAX_Z1 = Source impedance needed to realize G_MAX (complex,
Ohms)
■
G_MAX_Z2 = Load impedance needed to realize G_MAX (complex, Ohms)
■
G_MAX_Y1 = Source admittance needed to realize G_MAX (complex,
Siemens)
■
G_MAX_Y2 = Load admittance needed to realize G_MAX (complex,
Siemens)
■
G_AS (associate gain—maximum gain at the minimum noise figure)
■
VSWR(n) (voltage standing-wave ratio at the n port)
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.LIN Analysis
■
GD (group delay from port=1 to port=2)
■
G_MSG (maximum stable gain)
■
G_TUMAX (maximum unilateral transducer power gain)
■
G_U (unilateral power gain)
TYPE Definitions
■
R = Real
■
I = Imaginary
■
M = Magnitude
■
P = PD = Phase in degrees
■
PR = Phase in radians
■
DB = decibels
Examples
.print AC S11 S21(DB) S(2,3)(D) S(2,1)(I)
.print AC NFMIN GAMMA_OPT G_AS
.probe AC RN G_MAX ZOPT Y(3,1)(M) Y31(P)
Multi-Port Scattering (S) Parameters
S Parameters represent the ratio of incident and scattered (or forward and
reflected) normalized voltage waves. Figure 67 shows a two-port network.
Figure 67
Two-Port Network
I1
Port=1
398
Z01
I2
+
V1
-
Two-Port
Network
+
V2
Z02
Port=2
-
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.LIN Analysis
The following equations define the incident (forward) waves for this two-port
network:
v 1 + Z 01 I 1
a 1 = ----------------------2 ⋅ Z 01
v 2 + Z 02 I 2
a 2 = ----------------------2 ⋅ Z 02
The following equations define the scattered (reflected) waves for this two-port
network:
v 1 – Z 01 I 1
b 1 = ----------------------2 ⋅ Z 01
v 2 – Z 02 I 2
b 2 = ----------------------2 ⋅ Z 02
The following equations define the S Parameters:
b
S 11 = ----1a1 a2 = 0
b
S 12 = ----1a2 a1 = 0
b
S 21 = ----2a1 a2 = 0
b
S 22 = ----2a2 a1 = 0
Each S Parameter is a complex number, which can represent gain, isolation, or
a reflection coefficient.
Example
The following examples show how you can represent a gain, isolation, or
reflection coefficient:
.PRINT
.PRINT
.PRINT
.PRINT
AC
AC
AC
AC
S11(DB)
S21(DB)
S12(DB)
S22(DB)
$
$
$
$
Input return loss
Gain
Isolation
Output return loss
Two-Port Transfer and Noise Calculations
Two-port noise analysis is a linear AC noise analysis method that determines
the noise figure of a linear 2-port for an arbitrary source impedance.
Several output parameter measurements are specific to 2-port networks. .LIN
analysis supports 2-port calculations for 3 or more ports if port=1 is the input
and port=2 the output. All other ports terminate in their characteristic
impedance. This is equivalent to operating on the 2-port [S] sub-matrix
extracted from the multi-port [S] matrix. This occurs for both signal and noise
calculations. A warning appears if N>2 and you specified 2-port quantities.
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.LIN Analysis
Noise and signal port-wise calculations do not require that port elements use a
ground reference. You can therefore measure fully-differential circuits.
.LIN generates a set of noise parameters. The analysis assumes a noise
model consisting of:
■
A shunt current noise source, called In, at the input of a noiseless 2-port
linear network.
■
A series voltage noise source, called Vn, at the input of a noiseless 2-port
linear network.
■
A source with impedance, called Zs, that drives this 2-port network.
■
The 2-port network drives a noiseless load, called Zl.
Equivalent Input Noise Voltage and Current
For each analysis frequency, HSPICE computes a noise equivalent circuit for a
linear two-port. The noise equivalent circuit calculation results in an equivalent
noise voltage and current, and their correlation coefficient.
■
VN2: Equivalent input noise voltage squared (Real, V2).
■
IN2: Equivalent input noise current squared (Real, A2).
■
RHON: Correlation coefficient between the input noise voltage and the input
noise current (complex, unitless).
Equivalent Noise Resistance and Conductance
These measurements are the equivalent resistance and conductance, which
generate the equivalent noise voltage and current values at a temperature of
T=290K in a 1Hz bandwidth.
■
RN: Noise equivalent resistance (Real, Ohms)
■
GN: Noise equivalent conductance (Real, Siemens)
Noise Correlation Impedance and Admittance
These measurements represent the equivalent impedance and admittance that
you can insert at the input of the noise equivalent circuit to account for the
correlation between the equivalent noise voltage and the current values.
400
■
ZCOR: Noise correlation impedance (Complex, Ohms)
■
YCOR: Noise correlation admittance (Complex, Siemens)
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.LIN Analysis
Optimum Matching for Noise
These measurements represent the optimum impedance, admittance, and
reflection coefficient value that result in the best noise performance (minimum
noise figure).
■
ZOPT: Optimum source impedance for noise (Complex, Ohms)
■
YOPT: Optimum source admittance for noise (Complex, Siemens)
■
GAMMA_OPT: Optimum source reflection coefficient (Complex, unitless)
Because ZOPT and YOPT can commonly take on infinite values when
computing optimum noise conditions, calculations for optimum noise loading
reflect the GAMMA_OPT coefficient.
Noise Figure and Minimum Noise Figure
Noise figure represents the ratio of the SNR (signal to noise ratio) at the input
to the SNR at the output. You can set the input source impedance to ZOPT to
obtain the minimum noise figure.
■
NFMIN: Minimum noise figure (source at ZOPT) (real, unitless, power ratio)
■
NF: Noise figure (value obtained with source impedance at Zc[1]) (real,
unitless, power ratio)
Associated Gain
This measurement assumes that the input impedance matches the minimum
noise figure, and the output matches the maximum gain.
G_AS is the associated gain—maximum power gain at NFMIN (real, power
ratio)
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.LIN Analysis
Output Format for Group Delay in .sc* Files
All of the S/Y/Z/H parameters support a group delay calculation. The output
syntax of .PRINT/.PROBE for group delay is:
Xmn(T) | Xmn(TD) | X(m,n)(T) | X(m,n)(TD)
■
X = S, Y, Z, or H
■
m, n = port number (1 or 2 for H parameter)
The output of group delay matrices in .sc* files lets HSPICE directly read back
the group delay information, the tabulated data uses the regular HSPICE model
syntax with the SP keyword:
*| group delay parameters
.MODEL SMODEL_GD SP N=2 SPACING=POI INTERPOLATION=LINEAR
+ MATRIX=NONSYMMETRIC VALTYPE=REAL
+ DATA=3
+
1e+08
+
0
5e-09
+
5e-09
0
+
{...data...}
model name is the model name of the S parameters, plus _GD.
GROUPDELAY=[0|1] in the top line indicates group delay data:
*| N=2 DATA=3 NOISE=0 GROUPDELAY=1
*| NumOfBlock=1 NumOfParam=0
Output Format for Two-Port Noise Parameters in .sc* Files
Output of two-port noise parameter data in .sc* files shows the tabulated data
with the following quantities in the following order:
*| 2-port noise parameters
*|
frequency Fmin[dB] GammaOpt(M) GammaOpt(P) RN/Z0
*|
{...data...}
In this syntax:
402
■
Fmin[dB] = minimum noise figure (dB).
■
GammaOpt(M) = magnitude of the reflection coefficient needed to realize
Fmin.
■
GammaOpt(P) = phase (degrees) of the reflection coefficient needed to
realize Fmin.
■
RN/Z0 = normalized noise resistance.
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.LIN Analysis
Both GammaOpt and RN/Z0 values are normalized with respect to the
characteristic impedance of the port=1 element (that is, Z01).
Noise Parameters
You can use the .LIN analysis to compute the equivalent two-port noise
parameters for a network. The noisecalc=1 option automatically calculates the
following equivalent circuit values.
HSPICE can output the result of .LIN noise analysis to a .sc*, TOUCHSTONE,
or CITIfile.
Figure 68
Noise Equivalent Circuit
Vn
+In
Port=1
Two-Port
Network
Port=2
■
Vn is the equivalent input-referred noise voltage source.
■
In is the equivalent input-referred noise current source.
■
InVn is their correlation.
HSPICE noise analysis also makes the following measurements available:
Vn 2
R n = ---------4kT
In 2
G n = --------4kT
I n∗ V n
Z cor = ------------= R cor + jX cor
2
In

R
2
F min = 1 + 2G n  R cor + ------n – ( X cor ) 
Gn


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Z opt =
R
2
------n – ( R cor ) – jX cor
Gn
Z opt – Z 0
γ I opt = --------------------Z opt + Z 0
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.LIN Analysis
Hybrid (H) Parameters
.LIN analysis can calculate the complex two-port H (hybrid) parameter of a
multi-terminal network.
The H parameters of a two-port network relate the voltages and currents at
input and output ports:
V1 = h11 ⋅ I1 + h12 ⋅ V2
I2 = h21 ⋅ I1 + h22 ⋅ V2
In the preceding equations:
■
H = h11 h12 Hybrid matrix
h21 h22
■
V1 = Voltage at input port
■
I2 = Current at output port
■
V2 = Voltage at output port
■
I1 = Current at input port
You can add the hybrid H parameter matrixes of two networks to describe
networks that are in series at their input and in parallel at their output.
.LIN can calculate H parameters based on the scattering parameters of the
networks. .LIN analysis can extract one-port and two-port network H
parameters. For networks with more than two ports, .LIN assumes that the
ports numbered 3 and above terminate in their port characteristic impedance
(Zc[i], i>2).
Group Delay
Group delay measures the transit time of a signal through a network versus
frequency. It reduces the linear portion of the phase response to a constant
value, and transforms the deviations from linear phase into deviations from
constant group delay (which causes phase distortion in communications
systems). The average delay represents the average signal transit time through
a network system.
HSPICE can output the result of .LIN group delay measurement to a .sc*,
TOUCHSTONE, or CITIfile.
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Group delay is a function of frequency:
d ( phase )
gd ( w ) = –-------------------------d(w)
In the preceding equation:
■
gd = Group delay at the f frequency, 2 π f = w
■
phase = phase response at the f frequency
■
w = radians frequency
All complex S, Y, Z, and H parameters support a group delay calculation.
Syntax
Xmn(T) | Xmn(TD) | X(m,n)(T) | X(m,n)(TD)
X = S, Y, Z, or H (parameters)
m,n = port number (1 or 2 for H-parameters)
The results of the group delay calculation are scalar real numbers in units of
seconds. For .LIN, group delay values are a function of frequency. The
calculation is:
r ij = |r ij |e
jf ij ( w )
Differentiating the complex logarithm with respect to omega results in:
1 d|r ij |
1- dr ij ------df
----------- = - ----------+ j ------r ij dw |r ij | dw
dw
The group delay is the negative derivative of the phase. Simulation can
compute it from the imaginary component of the derivative w.r.t. frequency of
the measurement:
dr
r ij dw
1 ij
df- = – Im ---- -------τ ( w ) = – -----dw
RF Measurements From .LIN
In addition to S, Y, Z, and H parameters, a LIN analysis can include the output
measurements in the following sections.
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Impedance Characterizations
■
VSWR(i) = Voltage standing wave ratio at port i (real, unit-less)
■
ZIN(i) = Input impedance at port i (complex, Ohms)
■
YIN(i) = Input admittance at port i (complex, Siemens)
Stability Measurements
■
K_STABILITY_FACTOR = Rollett stability factor (real, unit-less)
■
MU_STABILITY_FACTOR = Edwards & Sinsky stability factor (real, unitless)
Gain Measurements
■
G_MAX = Maximum available/operating power gain (real, power ratio)
■
G_MSG = Maximum stable gain (real, power ratio)
■
G_TUMAX = Maximum unilateral transducer power gain (real, power ratio)
■
G_U = Unilateral power gain (real, power ratio)
Matching for Optimal Gain
406
■
G_MAX_GAMMA1 = Source reflection coefficient needed to realize G_MAX
(complex, unit-less)
■
G_MAX_GAMMA2 = Load reflection coefficient needed to realize G_MAX
(complex, unit-less)
■
G_MAX_Z1 = Source impedance needed to realize G_MAX (complex,
Ohms)
■
G_MAX_Z2 = Load impedance needed to realize G_MAX (complex, Ohms)
■
G_MAX_Y1 = Source admittance needed to realize G_MAX (complex,
Siemens)
■
G_MAX_Y2 = Load admittance needed to realize G_MAX (complex,
Siemens)
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RF Measurements From .LIN
Noise Measurements
■
VN2 = Equivalent input noise voltage squared (real, V2)
■
IN2 = Equivalent input noise current squared (real, A2)
■
RHON = Correlation coefficient between input noise voltage and input noise
current (complex, unit-less)
■
RN = Noise equivalent resistance (real, Ohms)
■
GN = Noise equivalent conductance (real, Siemens)
■
ZCOR = Noise correlation impedance (complex, Ohms)
■
YCOR = Noise correlation admittance (complex, Siemens)
■
ZOPT = Optimum source impedance for noise (complex, Ohms)
■
YOPT = Optimum source admittance for noise (complex, Siemens)
■
GAMMA_OPT = Optimum source reflection coefficient (complex, unit-less)
■
NFMIN = Noise figure minimum (source at Zopt) (real, unit-less power ratio)
■
NF = Noise figure (value obtained with source impedance at Z01) (real, unitless power ratio)
■
G_AS = Associated gain -- maximum power gain at NFMIN (real, power
ratio)
Two-Port Transfer and Noise Measurements
Several of the output parameter measurements are assumed to be for two-port
networks. When the network has 3 or more ports, the measurements are still
carried out by assuming that port=1 is the input and port=2 is the output. All
other ports are assumed terminated in their (noiseless) characteristic (z0)
impedances. Note that this assumption is equivalent to operating on the twoport [S] sub-matrix extracted from the multi-port [S] matrix. This is true for both
signal and noise calculations. A warning message is issued in cases where
N>2 when two-port quantities are requested.
Signal and noise port-wise calculations do not require that port elements use a
ground reference. Measurements are therefore possible; for example, for fully
differential circuits.
Since Zopt and Yopt can commonly take on infinite values when computing
optimum noise conditions, calculations for optimum noise loading is performed
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in terms of the reflection coefficient GammaOpt, and is made as robust as
possible.
Output Format for Two-Port Noise Parameters in .sc* Files
The output of two-port noise parameter data in .sc* files are slightly modified.
The tabulated data appears with the following quantities in the following order:
*| 2-port noise parameters
*| frequency Fmin[dB] GammaOpt(M) GammaOpt(P)
*|
{...data...}
RN/Z0
Where
■
Fmin[dB] is the minimum noise figure (dB)
■
GammaOpt(M) is the magnitude of reflection coefficient needed to realize
Fmin
■
GammaOpt(P) is the phase (degrees) of reflection coefficient needed to
realize Fmin
■
RN/Z0 is the normalized noise resistance
Both GammaOpt and RN/Z0 values are normalized with respect to the
characteristic impedance of the port=1 element; for example, Z01.
VSWR
The Voltage Standing Wave Ratio represents the ratio of maximum to minimum
voltages along a standing wave pattern due to a port’s impedance mismatch.
All ports other than the port of interest terminate in their characteristic
impedances. VSWR is a real number related to that port’s scattering
parameter:
1 + s ii
VSWR [ i ] = ----------------1 – s ii
ZIN(i)
The Input Impedance at the i port is the complex impedance into a port with all
other ports terminated in their appropriate characteristic impedance. It is
related to that port’s scattering parameter:
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1 + S ii
ZIN [ i ] = Z 0i --------------1 – S ii
YIN(i)
The Input Admittance at the i port is the complex admittance into a port with all
other ports terminated in their appropriate characteristic impedance. It is
related to that port’s scattering parameter:
1 1 – S ii
YIN [ i ] = ------- --------------Z 0i 1 + S ii
K_STABILITY_FACTOR (Rollett Stability Factor)
The Rollett stability factor is:
2
2
2
1 – s 11 – s 22 + ∆
K = -------------------------------------------------------2 s 12 s 21
∆ determines the two-port S matrix calculated from this equation:
∆ = s 11 s 22 – s 12 s 21
An amplifier where K>1 is unconditionally stable at the selected frequency.
MU_STABILITY_FACTOR (Edwards-Sinsky Stability Factor)
The following equation defines the Edwards-Sinsky stability factor.
2
1 – |S 11 |
µ = ----------------------------------------------------* |+ |S 21S 12|
|S 22 – ∆ S 11
∆ = S 11 S 22 – S 12 S 21
An amplifier with µ>1 is considered unconditionally stable at the specified
frequency.
Maximum Available Power Gain—G_MAX
This is the gain value that can be realized if the two-port is simultaneously
conjugate-matched at both input and output (with no additional feedback):
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s 21
2
---------  K – K – 1
G max =


s 12
K is the Rollett stability factor. Special cases of G_MAX are handled in the
following manner:
■
If |S12|=0 and (|S11|=1 or |S22|=1), G_MAX = |S21|2
■
If |S12|=0 and |S11|≠1 and |S22|≠1, G_MAX = G_TUMAX
■
If |S12|≠0 and K≤1, G_MAX = G_MSG
When values for K≤1, the Maximum Available Power Gain is undefined, and
HSPICE RF returns the Maximum Stable Gain.
Maximum Stable Gain - G_MSG
For a two-port that is conditionally stable (K<1), the following equation
calculates the maximum stable gain:
s 21
G MSG = --------s 12
To achieve this gain, resistively load the unstable two-port so that K=1, and
then simultaneously conjugately match the input and output ports. G_MSG is
therefore equivalent to G_MAX with K = 1. In terms of admittance parameters:
y 21
G MSG = ---------y 12
MSG is equivalent to the Maximum Available Power Gain if K=1.
Maximum Unilateral Transducer Power Gain —G_TUMAX
This is the highest possible gain that a two-port with no feedback (that is,
S12=0) can achieve.
2
s 21
G tumax = -----------------------------------------------------2
2
( 1 – s 11 ) ( 1 – s 22 )
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Unilateral Power Gain—GU
This is the highest gain that the active two-port can ever achieve by embedding
in a matching network that includes feedback. The frequency where the
unilateral gain becomes unity defines the boundary between an active and a
passive circuit. The frequency is usually referred to as fmax, the maximum
frequency of oscillation.
To realize this gain, HSPICE RF neutralizes the feedback of the two-port, and
simultaneously conjugate-matches both input and output:
2
s 21
------- – 1
s 12
G U = -----------------------------------------------s
s 21
 21 
2K ------ – 2Re  ------- 
s
 s 12 
12
Simultaneous Conjugate Match for G_MAX
A simultaneous conjugate match is required at the source and load to realize
the Gmax gain value. The source reflection coefficient at the input must be:
B 12
B1
C ∗1
--------Γ1 =
------------- – --------------- – 1
2
C1 2 C1
2C 1
2
2
B 1 = 1 – s 22 + s 11 – ∆
∗
C 1 = s 11 – ∆ s22
2
∆ = s 11 s 22 – s 12 s 21
The load reflection coefficient (G_MAX_GAMMA_2) is:
B 22
B2
C 2∗
Γ 2 = --------- ------------- – --------------- – 1
2
C2 2 C2
2C 2
In the preceding equation:
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2
2
B 2 = 1 – s 11 + s 22 – ∆
2
∗
C 2 = s 22 – ∆ s11
∆ = s 11 s 22 – s 12 s 21
You can obtain useful solutions only when:
B1
------------>1
2C 1
B2
----------->1
2C 2
These equations also imply that K>1.
HSPICE RF derives calculations for the related impedances and admittances
from the preceding values.
■
For G_MAX_Z1:
1 + Γ1
Z 1 = Z 01 --------------1 – Γ1
■
For G_MAX_Z2:
1 + Γ2
Z 2 = Z 02 --------------1 – Γ2
■
For G_MAX_Y1
1 1 – Γ1
Y 1 = -------- --------------Z 01 1 + Γ 1
■
For G_MAX_Y2
1 1 – Γ2
Y 2 = -------- --------------Z 02 1 + Γ 2
Equivalent Input Noise Voltage and Current—IN2, VN2, RHON
For each analysis frequency, HSPICE RF computes a noise-equivalent circuit
for a linear two-port. The noise analysis assumes that all ports terminate in
noise-less resistances. For circuits with more than two ports, ports identified as
3 and above terminate, and the analysis considers only ports 1 and 2. The
noise-equivalent circuit calculation results in an equivalent noise voltage and
current, and their correlation coefficient. These values are:
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VN2 = |v n |
2
IN2 = |i n |
2
i n v*n
RHON = ρ n = ------------------------2
2
|i n | |v n |
Equivalent Noise Resistance and Conductance—RN, GN
These measurements are the equivalent resistance and conductance that
would generate the equivalent noise voltage and current values at a
temperature of T0 = 290k in a 1 Hz bandwidth (that is, ∆f = 1Hz ).
2
|v n |
RN = R n = ----------------4kT 0 ∆ f
2
|i n |
GN = G n = ----------------4kT 0 ∆ f
Noise Correlation Impedance and Admittance—ZCOR, YCOR
These measurements represent the equivalent impedance and admittance that
you can insert at the input of the noise-equivalent circuit to account for the
correlation between the equivalent noise voltage and the current values.
2
|v n |
i*n v n
ZCOR = ρ n --------- = ------------ = R cor + jX cor
2
2
|i n |
|i n |
2
YCOR = ρ n
|i n |
i nv n *
--------- = ------------ = G cor + jB cor
2
2
|v n |
|v n |
ZOPT, YOPT, GAMMA_OPT – Optimum Matching for Noise
The equivalent input noise sources and their correlation make it possible to
compute the impedance, admittance, and reflection coefficient values that, if
presented at the input of the noisy two-port, result in the best noise
performance. These values are:
Z opt =
R
2
------n – X cor – jX cor
Gn
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1 =
Y opt = --------Z opt
Gn
2
------ – B cor – jB cor
Rn
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Z opt – Z 01
GAMMA_OPT= Γ opt = ----------------------Z opt + Z 01
Noise Figure and Noise Figure Minimum—NF, NFMIN
If you set the input source impedance to ZOPT, the two-port operates with the
minimum Noise Figure. The definition of Noise Figure (F) is unusual, because it
involves the available gain of the two-port and not its transducer gain. You can
express it in the following form:
Na
F = 1 + --------------------G a kT 0 ∆ f
■
Ga is the available power gain.
■
Na is the available noise power at the output of the two-port (due solely to
the two-port’s noise and not to the input impedance).
■
k is Boltzmann’s constant.
■
T0 is the 290 Kelvin reference temperature.
The NMIN minimum noise figure value is computed as:

R
2 
NFMIN = F min = 1 + 2G n  R cor + ------n – Xcor 
Gn


NFMIN>1. For input source impedance values other than ZOPT, the Noise
Figure varies as a function of the input source reflection coefficient, according
to:
2
R n | Γ S – Γ opt |
F = F min + --------------------------------2
2Z 01 |1+ Γ opt |
The HSPICE RF Noise Figure measurement (NF) returns the noise figure value
if the input terminates in the port characteristic impedance (that is, Γs = 0 ). This
value is:
Gn
R n | Γ opt |
2
NF = F min + --------------------------------= F min + -------- |Z 01 – Z opt |
2
Z 01
2Z 01 |1+ Γ opt |
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Associated Gain—G_As
HSPICE RF also includes a measurement named Associated Gain, which
assumes that the Γ s inout impedance is matched for the minimum noise figure
(that is, Γ s = Γ opt ), while the output is matched for the maximum gain.
2
2
s 21 ( 1 – Γ Opt )
G AS = --------------------------------------------------------------2
2
1 – s 11 Γ Opt ( 1 – s′ 22 )
s 12 s 21 Γ Opt
′ = s + ---------------------------In the preceding equation: s 22
22 1 – s Γ 11 Opt
Extracting Mixed-Mode Scattering (S) Parameters
In HSPICE RF, the .LIN analysis includes a keyword for extracting mixedmode scattering (S) parameters.
Syntax
.LIN … [ mixedmode2port= dd|dc|ds|cd|cc|cs|sd|sc|ss ]
The following keyword in the .PRINT/.PROBE statements specifies the
elements in the mixed mode S-parameter matrices:
S|Y|Z<xy>nm<(t)>
Parameter
Description
x, y
One of the following:
• D (differential)
• C (common)
• S (single-ended)
For example:
• SCC = common mode S-parameters
• SDC or SCD = cross mode S-parameters
If you omit x,y, then HSPICE uses the value set for the
mixedmode2port.
Scc
Common-mode S-parameters
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Parameter
Description
Scd and Sdc
Mode-conversion or cross-mode S parameters
m, n
port number
type
One of the following:
•
•
•
•
•
DB: magnitude in decibels
I: imaginary part
M: magnitude (default)
P: phase in degree
R: real part
Defaults
Availability and default value for the “mixedmode2port” keyword depends on
the port configuration.
Example 1
p1=p2=single
Where,
■
Available: ss
■
Default: ss
Example 2
p1=p2=balanced
Where,
■
Available: dd,cd,dc,cc
■
Default: dd
Example 3
p1=balanced p2=single
Where,
416
■
Available: ds,cs
■
Default: ds
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Extracting Mixed-Mode Scattering (S) Parameters
Example 4
p1=single p2=balanced
Where,
■
Available: sd,sc
■
Default: sd
Output File Formats
An sc# file format for the mixed mode:
■
The S element model has additional keywords, such as mixedmodei and
idatatype, if the netlist includes one or more balanced ports.
■
The mixedmode2port keyword prints in the header line.
■
The other S Element keywords also appear in the header lines.
Touchstone format for the mixed mode:
The following lines for data mapping are added to the head of the Touchstone
output file if the netlist includes one or more balanced ports.
!
!
!
!
S11
S12
S13
S14
=
=
=
=
SDD11
SDD12
SDC11
SDC12
Two-Port Parameter Measurement
Two-port parameter measurement function takes the first 2 ports, then reads
the corresponding parameter with the drive condition specified by the
mixedmode2port keyword.
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Output Format and Description
Parameter
Description
*.ac#
Output from both the .PROBE and .PRINT statements.
*.printac#
Output from the .PRINT statement. This is available in HSPICE RF
only.
*.sc#
The extracted S parameters/2-port noise parameters are written to
a *.sc# file by using the S-element format. If you want to simulate the S
element, you can reference the *.sc# file in your netlist.
* N=numOfPorts DATA=numOfFreq NOISE=[0|1] GROUPDELAY=[0|1]
* NumOfBlock=numOfSweepBlocks NumOfParam=numOfSweptParameters
* MIXEDMODE=[0|1] DATATYPE=mixedModeDataTypeString
.MODEL mname S
+ N=numOfPorts FQMODEL=SFQMODEL TYPE=S Zo=*** *** ...
.MODEL SFQMODEL SP N=numberOfPorts SPACING=POI
INTERPOLATION=LINEAR MATRIX=NONSYMMETRIC
+ DATA= numberOfData
+ freq1
+ s11real s11imag s12real s12imag ... s1Nreal s1Nimag
...
+ sN1real sN1imag ... sNNreal sNNimag
...
...
+ freqNumberOfData
+ s11real s11imag s12real s12imag ...s1Nreal s1Nimag
...
+ sN1real sN1imag ... sNNreal sNNimag
*
*
*
*
2-port noise parameter
frequency
Fmin [dB]
GammaOpt(M)
0.10000E+09 0. 1.0000 0. 1.0281
...
GammaOpt(P)
RN/Zo
The 2-port noise section starts with “*” so that you can include this file in your
HSPICE or HSPICE RF input netlists.
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Features Supported
.LIN analysis in HSPICE and HSPICE RF supports the following features:
■
Automatic calculation of bias-dependent S, Y, and Z parameters. No
additional sources required.
■
Automatic calculation of noise parameters.
■
Automatic calculation of group delay matrices.
In addition, HSPICE RF supports all existing HSPICE RF models. For noise
analysis, HSPICE and HSPICE RF view port 1 as the input and port 2 as the
output.
Prerequisites and Limitations
The following prerequisites and limitations apply to .LIN analysis in HSPICE
RF:
■
Requires one .LIN statement to specify calculation options.
■
Requires one .AC statement to specify frequency sweep and parameter
sweep.
■
Requires at least one P element, numbered from port 1 to N.
■
For noise analysis, HSPICE RF views port 1 as the input and port 2 as the
output.
Reported Statistics for the Performance Log (HSPICE RF Only)
■
■
Simulation time
•
DC op time
•
Total simulation time
Memory used
•
Total memory
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Errors and Warnings
■
If the circuit contains fewer than two P Elements and noisecalc=1, then the
2-port noise calculation is skipped.
■
If the circuit contains fewer than two P Elements, does not let you cannot
use the .PRINT, .PROBE, or .MEAS command with any 2-port noise or gain
parameters.
■
If the circuit contains more than two P Elements, all two-port parameters are
computed. By default, port=1 is the input and port=2 is the output. All other
ports terminate in their reference impedances.
Example
.OPTION POST=2
.AC DEC 1 20MEG 20G
.LIN noisecalc = 1
Pout outs gnd port=2 RDC=50 RAC=50 DC=0 AC=1 0
Pin ins gnd port=1 RDC=50 RAC=50 DC=0.5 AC=0.5 0
xlna_2_ ins outs lna
.subckt lna in out
rhspr5 in _n481 50
rhspr6 _n523 out 100
vvdd _n523 gnd dc = 1.8
qhspnpn3 out _n481 gnd gnd bjtm1 area = 3
.ends lna
.global gnd
.END
.NET Parameter Analysis
HSPICE or HSPICE RF uses the AC analysis results to perform network
analysis. The .NET statement defines Z, Y, H, and S parameters to calculate.
The following list shows various combinations of the .NET statement for
network matrices that HSPICE or HSPICE RF calculates:
.NET Vout Isrc
.NET Iout Vsrc
.NET Iout Isrc
.NET Vout Vsrc
([M]T represents
420
V
I
[V1
[I1
the
=
[Z]
[I]
=
[Y]
[V]
T
=
[H]
[I1 V2]T
I2]
T
V2]
=
[S]
[V1 I2]T
transpose of the M matrix).
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.NET Parameter Analysis
Note: The preceding list does not mean that you must use combination (1) to
calculate Z parameters. However, if you specify .NET Vout Isrc,
HSPICE or HSPICE RF initially evaluates the Z matrix parameters. It then
uses standard conversion equations to determine S parameters or any other
requested parameters.
Figure 69 shows the importance of variables in the .NET statement. Here, Isrc
and Vce are the DC biases, applied to the BJT.
Figure 69
Parameters with .NET V(2) Isrc
I2
1
I1
+
-
Isrc
+
+
V1
V2
-
-
Vce
This .NET statement provides an incorrect result for the Z parameter
calculation:
.NET V(2) Isrc
When HSPICE or HSPICE RF runs AC analysis, it shorts all DC voltage
sources; all DC current sources are open-circuited. As a result, V(2) shorts to
ground and its value is zero in AC analysis. This affects the results of the
network analysis.
In this example, HSPICE or HSPICE RF attempts to calculate the Z parameters
(Z11 and Z21), defined as Z11 = V1/I1 and Z21 = V2/I1 with I2=0. The above
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.NET Parameter Analysis
example does not satisfy the requirement that I2 must be zero. Instead, V2 is
zero, which results in incorrect values for Z11 and Z21.
Figure 70 shows the correct biasing configurations for performing network
analysis for the Z, Y, H, and S parameters.
Figure 70
Network Parameter Configurations
Z -parameter: .NET V(C) IB
I2
Y-parameter: .NET I(Vc) VBE
I2
C
I1
I1
IB
V1
+
-
+
V2
-
IC
VBE
H-parameter: .NET I(Vc) IB
I2
+
V1
-
+
V1
-
+
V2
-
VCE
S-parameter: .NET V(C) VBE
I2
C
I1
IB
C
I2
I1
+
V2
-
VCE
VBE
V1
+
-
+
V2
-
I2
Example
To calculate the H parameters, HSPICE or HSPICE RF uses the .NET
statement.
.NET I(VC) IB
VC denotes the voltage at the C node, which is the collector of the BJT. With
this statement, HSPICE or HSPICE RF uses the following equations to
calculate H parameters immediately after AC analysis:
V1 = H11 ⋅ I1 + H12 ⋅ V2
I2 = H21 ⋅ I1 + H22 ⋅ V2
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.NET Parameter Analysis
To calculate Hybrid parameters (H11 and H21), the DC voltage source (VCE)
sets V2 to zero, and the DC current source (IB) sets I1 to zero. Setting I1 and
V2 to zero, precisely meets the conditions of the circuit under examination: the
input current source is open-circuited, and the output voltage source shorts to
ground.
A data file containing measured results can drive external DC biases applied to
a BJT. Not all DC currents and voltages (at input and output ports) might be
available. When you run a network analysis, examine the circuit and select
suitable input and output variables. This helps you to obtain correctlycalculated results. The following example demonstrates HSPICE network
analysis of a BJT or HSPICE RF.
Network Analysis Example: Bipolar Transistor
You can find the sample netlist for this example in the following directory:
$installdir/demo/hspice/bjt/net_ana.sp
Other possible biasing configurations for the network analysis are:
$S-parameter
.NET v(c) vbb rin = 50 rout = 50
ve
e
0
0
vbb
b
0
dc = 'vbe' ac = 0.1
icc
0
c
'ic'
q1
c
b
e 0
bjt
$Z-parameter
.NET v(c) ibb rin = 50 rout = 50
ve
e
0
0
ibb
0
b
dc = 'ib' ac = 0.1
icc
0
c
'ic'
q1
c
b
e 0
bjt
$Y-parameter
.NET i(vc) vbb rin = 50 rout = 50
ve
e
0
0
vbb
b
0
'vbe' ac = 0.1
vc
c
0
'vce'
q1
c
b
e 0
bjt
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.NET Parameter Analysis
.NET Parameter Analysis
Xij(z), ZIN(z), ZOUT(z), YIN(z), YOUT(z)
Parameter
Description
X
In HSPICE or HSPICE RF, can be Z (impedance), Y (admittance), H
(hybrid), or S (scattering).
ij
i and j identify the matrix parameter to print in HSPICE or HSPICE RF.
Value can be 1 or 2. Use with the X value above (for example, Sij, Zij, Yij,
or Hij).
ZIN
Input impedance. For the one-port network, ZIN, Z11, and H11 are the
same. (HSPICE or HSPICE RF).
ZOUT
Output impedance. (HSPICE or HSPICE RF).
z
Output type (HSPICE or HSPICE RF):
•
•
•
•
•
•
R: real part.
I: imaginary part.
M: magnitude.
P: phase.
DB: decibel.
T: group time delay (HSPICE RF does not support group time delays
in AC analysis output).
YIN
Input admittance. For a one-port network, YIN is the same as Y11.
(HSPICE or HSPICE RF).
YOUT
Output admittance. (HSPICE or HSPICE RF).
If you omit z, output includes the magnitude of the output variable. The output
of AC Analysis includes voltages and currents.
Example
.PRINT AC Z11(R) Z12(R) Y21(I) Y22 S11 S11(DB) Z11(T)
.PRINT AC ZIN(R) ZIN(I) YOUT(M) YOUT(P) H11(M) H11(T)
.PLOT
AC S22(M) S22(P) S21(R) H21(P) H12(R) S22(T)
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.NET Parameter Analysis
Bandpass Netlist: Network Analysis Results
You can find the sample netlist for this example in the following directory:
$installdir/demo/hspice/filters/fbpnet.sp
Figure 71
S11 Magnitude and Phase Plots
BAND-PASS NETLIST: HSPICE NETWORK ANALYSIS RESULTS
04/14/2003 18:31:54
FBPL.AC0
S11[dB]
0
-10.0
-20.0
S11 [LIN]
-30.0
-40.0
179.141
100.0
FBPL.AC0
S11[PHASE]
0
-100.0
-175.88
200.0x
220.0x
240.0x
260.0x
280.0x
300.0x
HERTZ [LIN]
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References
Figure 72
ZIN Magnitude and Phase Plots
BAND-PASS NETLIST: HSPICE NETWORK ANALYSIS RESULTS
04/14/2003 18:31:54
120.0
FBPL.AC0
ZIN[MAG
100.0
80.0
60.0
ZIN [LIN]
40.0
FBPL.AC0
ZIN[PHASE
20.0
90_0
50_0
0
-50_0
-90_0
200.0x
220.0x
240.0x
260.0x
280.0x
300.0x
HERTZ [LIN]
References
1. Goyal, Ravender. “S-Parameter Output From SPICE Program”, MSN & CT,
February 1988, pp. 63 and 66.
2. Robert J. Weber "Introduction to Microwave Circuits", IEEE Press.
3. Behzad Razavi, "Design of Analog CMOS Integrated Circuits", McGraw Hill.
4. Reinhold Ludwig, Pavel Bretchko, "RF Circuit Design Theory and
Applications".
5. G.D. Vendelin, Design of Amplifiers and Oscillators by the S-Parameter
Method, John Wiley & Sons, 1982.
6. R.S. Carson, High-Frequency Amplifiers, 2nd Edition, John Wiley & Sons,
1982.
7. G. Gonzalez, Microwave Transistor Amplifiers: Analysis and Design, 2nd
Edition, Prentice-Hall, 1997.
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References
8. M.L. Edwards and J.H. Sinsky, "A single stability parameter for linear 2-port
networks," IEEE 1992 MTT-S Symposium Digest, pages 885-888.
9. H. Rothe and W. Dahlke, "Theory of noisy fourpoles", Proc. IRE, volume 44,
pages 811-818, June 1956.
10. David E. Bockeman, “Combined Differential and Common-Mode Scattering
Parameters: Theory and Simulation,” IEEE trans. on MTT Volume 43,
Number 7, Jul. 1995.
11. “Understanding Mixed Mode S parameters,” http://www.geocities.com/
billbeale0179/Accelerant/Understandmm.pdf
12. Robert J. Weber "Introduction to Microwave Circuits", IEEE Press.
13. Behzad Razavi, "Design of Analog CMOS Integrated Circuits", McGraw Hill.
14. Reinhold Ludwig, Pavel Bretchko, "RF Circuit Design Theory and
Applications."
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References
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Using HSPICE with Verilog-A
21
Describes how to use Verilog-A in HSPICE simulations.
Verilog-A is used to create and use analog behavioral descriptions that
encapsulate high-level behavioral and structural descriptions of systems and
components.
The language allows the behavior of each model, or module, to be described
mathematically in terms of its ports and parameters applied to an instance of
the module. A module can be defined at a level of abstraction appropriate for
the model and analysis, including architectural design, and verification. VerilogA supports both a top-down design as well as a bottom-up verification
methodology.
Verilog-A was derived from the IEEE 1364 Verilog Hardware Description
Language (HDL) specification and is intended for describing behavior in analog
systems. The Verilog-A language that HSPICE supports is compliant to VerilogAMS LRM2.1 from Accellera with some LRM2.2 features added, such as
$table_model, $param_given, output parameters, and the above function.
The Verilog-A implementation in HSPICE supports a mixed design of Verilog-A
descriptions and transistor-level SPICE netlists with a simple use model. Most
analysis features available in HSPICE are supported for Verilog-A based
devices, including AC, DC, transient analysis, statistical analysis, and
optimization.
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Getting Started
Getting Started
This section explains how to get started using a compact device model written
in Verilog-A in HSPICE.
Verilog-A devices use the following conventions:
■
modules are loaded into the simulator with either the .hdl netlist command
or the –hdl HSPICE command-line option.
■
modules are instantiated in the same manner as HSPICE sub-circuits. The
first character for the name of instance should be “X”.
■
instance and model parameters can be modified in the same way as other
HSPICE instances.
■
module names should not conflict with any HSPICE built-in device keyword
(for example, C, D, NMOS, PMOS, and so on). If this happens, HSPICE
issues a warning message and ignores the Verilog-A module definition.
■
node voltages and branch currents can be output using conventional output
commands.
Note: Before you run a circuit with a Verilog-A module, check to be sure that
your environment has been set up to source the cshrc.meta file. For details,
see the HSPICE chapter to the Installation Guide.
The following example illustrates how a compact device model written in
Verilog-A can be analyzed with HSPICE.
Example: JFET Compact Device Model
HSPICE contains a large number of compact device models coded natively in
the simulator. Verilog-A provides a convenient method to introduce new
compact models. The JFET device model uses a simple expression to relate
the source-drain current to the gate voltage.
The simplified Verilog-A description of this model is shown in below.
`include "constants.vams"
`include "disciplines.vams"
module jfet(d, g, s);
parameter real Vto = -2.0 from (-inf:inf); // Threshold voltage
parameter real Beta = 1.0e-4 from [0:inf);// Transconductance
parameter real Lambda = 0.0 from [0:inf); // Channel modulation
electrical d, g, s;
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real Id, Vgs, Vds;
analog begin
Vgs = V(g,s);
Vds = V(d,s);
if (Vds <= Vgs-Vto)
Id = Beta*(1+Lambda*Vds)*Vds*(2*(Vgs-Vto)- Vds);
else if (Vgs-Vto < Vds)
Id = Beta*(1+Lambda*Vds)*(Vgs-Vto)*(Vgs-Vto);
I(d,s) <+ Id;
end
endmodule
In this example the module name is jfet and the module has three ports, named
d, g, and s. Three parameters, Vto, Beta, and Lambda, can be passed in from
the netlist. The electrical behavior is defined between the analog begin and end
statements. The node voltages across the gate to source and drain to source is
accessed and assigned to the variables Vgs and Vgd. These values are used
to determine the drain-source current, Id. The calculated current is contributed
to the branch from d to s in the final statement using the contribution operator,
<+.
This Verilog-A module is loaded into HSPICE with an .HDL command in the
netlist. The device is then instantiated using the X prefix for the device name.
The connectivity, module name, and parameter assignments follow the format
of a sub-circuit device. The following instantiation line in the netlist is for this
device:
x1 drain gate source jfet Beta=1.1e-4 lambda=0.01
The nodes drain, gate, and source are mapped to the ports d, g, s in the same
order as defined in the module definition. Any parameters in the instantiation
line are passed to the module; otherwise, the default value defined on the
parameter declaration line is used. The parameter declaration allows ranges
and exclusions to be easily defined.
The parameter passed in from the netlist is tested during the simulation and a
run- time error occurs if the parameter is out of the allowed range.
The device is used in the HSPICE netlist in exactly the same manner that a
built-in device is used. The netlist example shown in below performs a simple
DC-IV analysis.
Verilog-A version of the SPICE JFET
.hdl jfet.va
.options post=1
VCC Drain
0
3.0
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Getting Started
VG
VS
Gate
0
Source 0
0.5
0.0
X1 Drain Gate Source jfet Vto=-2.0 Beta=1.1e-4 Lambda=0.01
.dc VCC 0.0 4.0 0.01 VG -2.0 0.0 0.5
.print I(VCC)
.end
When the simulation is performed, the program compiles the Verilog-A source
file into a compiled object file. This object file is automatically cached and
subsequent simulations do not require the compile step unless the Verilog-A
source file is modified. After simulation, HSPICE outputs the data in the same
fashion as other devices. In this example the drain-source current is plotted as
a function of Vds and parameterized by Vgs. Figure 73 displays the plot of the
drain-source current for this model.
Figure 73
432
IV Characteristics of a Verilog-A JFET
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Introduction to Verilog-A
Introduction to Verilog-A
The following is a Verilog-A module example provides an overview of the
language. See the Verilog-AMS LRM2.1 from Accellera for syntax and usage
details.
Verilog-A Module Template
The following basic template illustrates basic of the language's features.
`include "disciplines.vams" // Natures and disciplines
`include "constants.vams"
// Common physical and math
// constants
module my_model(port1, bus);
electrical port1;
electrical [0:1] bus;
parameter real real_param = 1.0 from [0:inf);
parameter integer int_param = 1 from [-1:1] exclude 0;
real real_var;
analog begin
@ ( initial_step ) begin
/*
Code inside an initial_step block is executed
at the first step of each analysis */
end
real_var = I(port1); // Current port1 to ground
V(bus[0], bus[1]) <+ real_var * real_param * int_param;
@ ( final_step ) begin
/* Code inside an final_step block is executed
at the last step of each analysis */
end
end
endmodule
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Introduction to Verilog-A
Data Types
Four Verilog-A data types are available. The parameter type is used to pass
values from the netlist to the module.
Table 52 Verilog-A Data Types
Data Type
Description
integer
Discrete numerical type
integer integer_name {, integer_name};
genvar
Special integer-valued variable for behavioral
looping constructs
genvar genvar_name {, genvar_name};
real
Continuous numerical type
real real_name {, real_name};
parameter
Attribute that indicates data type is determined at
module instantiation.
parameter [{integer | real }] param_name =
default_value [ from
[ range_begin:range_end ] [ exclude
exclude_value_or_range ] ] ;
Analog Operators and Filters
Analog operators and filters maintain memory states of past behavior. They can
not be used in an analog function.
Table 53 Verilog-A Analog Operators and Filters
Operator
Function
Time derivative
The ddt operator computes the time derivative of its argument.
ddt(expr)
Time integral
The idt operator computes the time-integral of its argument.
idt(expr, [ic [ , assert [ , abstol ] ] ] )
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Introduction to Verilog-A
Table 53 Verilog-A Analog Operators and Filters (Continued)
Operator
Function
Linear time
delay
absdelay() implements the absolute transport delay for
continuous waveform.
absdelay(input, time_delay [, maxdelay ])
Discrete
waveform filters
The transition filter smooths out piecewise linear waveforms.
transition(expr[,td[,rise_time[,fall_time
[,time_tol]]]])
The slew analog operator bounds the rate of change (slope) of
the waveform.
slew(expr[,max_pos_slew_rate
[,max_neg_slew_rate]])
The last_crossing() function returns a real value representing
the simulation time when a signal expression last crossed zero.
last_crossing(expr, direction)
Laplace
transform filters
laplace_zd() implements the zero-denominator form of the
Laplace transform filter. The laplace_np() implements the
numerator-pole form of the Laplace transform filter.
laplace_nd() implements the numerator- denominator form of
the Laplace transform filter. laplace_zp() implements the zeropole form of the Laplace transform filter.
laplace_*(expr, u, v)
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Introduction to Verilog-A
Table 53 Verilog-A Analog Operators and Filters (Continued)
Operator
Function
Z-transform
filters
The Z-transform filters implement linear discrete-time filters. All
Z-transform filters share three common arguments: T, t, and t0.
T specifies the period of the filter, is mandatory, and must be
positive. t specifies the transition time, is optional, and must be
nonnegative.
• zi_zd() implements the zero-denominator form of the Ztransform filter.
• zi_np() implements the numerator-pole form of the Ztransform filter.
• zi_nd() implements the numerator-denominator form of the
Z-transform filter.
• zi_zp() implements the zero-pole form of the Z-transform
filter.
zi_*( expr , u , v , T [ , t [ , t0 ] ] )
Limited
Exponential
Limits exponential argument change from one iteration to the
next.
limexp(arg)
Mathematical Functions
The following mathematical functions are available when using HSPICE with
Verilog-A.
Table 54 Verilog-A Mathematical Functions
436
Function
Description
Domain
Return Value
ln()
natural log
x>0
real
log(x)
log base 10
x>0
real
exp(x)
exponential
x<80
real
sqrt(x)
square root
x>=0
real
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Introduction to Verilog-A
Table 54 Verilog-A Mathematical Functions (Continued)
Function
Description
Domain
Return Value
min(x,y)
Minimum of x
and y
all x, y
If either is real, returns real,
otherwise returns the type of
x,y.
max(x,y)
Maximum of x
and y
all x, y
If either is real, returns real,
otherwise returns the type of
x,y.
abs(x)
absolute value
all x
same as x
pow(x,y)
xy
if x>=0,
all y; if
x<0, int(y)
real
floor(x)
Floor
all x
real
ceil(x)
Ceiling
all x
real
Transcendental Functions
The following mathematical functions are available when using HSPICE with
Verilog-A.
Table 55 Verilog-A Transcendental Function
Function
Description
Domain
sin(x)
sine
all x
cos(x)
cosine
all x
tan(x)
tangent
x != n (pi/2), n is odd
asin(x)
arc-sine
-1<= x <= 1
acos(x)
arc-cosine
-1<= x <= 1
atan(x)
arc-tangent
all x
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Introduction to Verilog-A
Table 55 Verilog-A Transcendental Function (Continued)
Function
Description
Domain
atan2(x,y)
arc-tangent of x/y
all x, all y
hypot(x,y)
sqrt(x2 + y2)
all x, all y
sinh(x)
hyperbolic sine
x < 80
cosh(x)
hyperbolic cosine
x < 80
tanh(x)
hyperbolic
tangent
all x
asinh(x)
arc-hyperbolic
sine
all x
acosh(x)
arc-hyperbolic
cosine
x >= 1
atanh(x)
arch-hyperbolic
tangent
-1 <= x <= 1
AC Analysis Stimuli
The The AC stimulus function produces a sinusoidal stimulus for use during a
small-signal analysis:
ac_stim( [ analysis_name [ , mag [ , phase ]]])
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Introduction to Verilog-A
Noise Functions
The noise functions contribute noise during small-signal analyses. The
functions have an optional name, which the simulator uses to tabularize the
contributions.
Table 56 Verilog-A Noise Functions
Function
Description
White Noise
Generates a frequency-independent noise of
power pwr.
white_noise(pwr[,name])
Flicker Noise
Generates a frequency-dependent noise of
power pwr at 1 Hz which varies in proportion to
the expression 1/fexp.
flicker_noise(pwr,exp[,name])
Noise Table
Defines noise via a piecewise-linear function of
frequency. Vector is frequency, power pairs in
ascending frequencies.
Noise_table(vector[,name])
Analog Events
The following analog events are available when using HSPICE with Verilog-A..
Table 57 Verilog-A Analog Event Controlled Statements
Function
Description
Initial
Step
Event trigger at first step of an analysis.
Final
Step
Event trigger at last step of an analysis.
Cross
Zero crossing threshold detection.
@(initial_step[(list_of_analyses)])
@(final_step[(list_of_analyses)])
cross(expr[,dir[,time_tol[,expr_tol]]]);
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Timestep and Simulator Control
Table 57 Verilog-A Analog Event Controlled Statements (Continued)
Function
Description
Timer
Generatse analog event at specific time.
timer(start_time[,period[,time_tol]]);
Above
Generates an event when a specified expression becomes greater
than or equal to zero.
above(expr[,time_tol[,expr_tol]]);
Timestep and Simulator Control
These functions provide a mechanism to alert the simulator to discontinuities or
to limit the time step.
Table 58 Verilog-A Discontinuity and Time Step Limit Functions
Function
Purpose
Bound time step
Controls the maximum time step the simulator takes during a
transient simulation.
$bound_step( expression );
Announce
discontinuity
Provides the simulator information about known discontinuities
to provide help for simulator convergence algorithms.
$discontinuity [ ( constant_expression ) ] ;
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Timestep and Simulator Control
System Tasks and I/O Functions
System functions provide access to system-level tasks as well as access to
simulator information.
Table 59 Verilog-A System Tasks and I/O Functions
Function
Return Value
$param_given
Returns 1 if the parameter was overridden by a module instance
parameter value assignment and 0 otherwise.
$table_model
Models behavior of a system by interpolating between data
points that are samples of that system’s behavior.
$strobe
Display simulation data when the simulator has converged on a
solution for all nodes using a printf() style format.
$display
$write
$strobe(args);
Open a file for writing and assign it to an associated channel.
$fopen
multi-channel_desc = $fopen("file");
$fclose
Closes a file from a previously-opened channel(s).
$fclose(multi-channel_descriptor);
$fstrobe
$fdisplay
$fwrite
Write simulation data to an opened channel(s) when the
simulator has converged. Follows format for $strobe.
$fstrobe(multi-channel_descriptor,
"information to be written");
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Timestep and Simulator Control
Simulator Environment Functions
The environment parameter functions return simulator environment information
to the module.Return circuit ambient temperature in Kelvin.
Table 60 Verilog-A Environment Parameter Functions
Function
Return Value
Circuit
temperature
Return circuit ambient temperature in Kelvin.
Time
Return absolute time in seconds.
$temperature
$abstime
Thermal
voltage
$vt can optionally have Temperature (in Kelvin) as an
input argument and returns the thermal voltage (kT/q)
at the given temperature. $vt without the optional
input temperature argument returns the thermal
voltage using $temperature.
$vt [ (Temperature) ]
Analysis flag
Returns true (1) if current analysis matches any one
of the passed arguments.
$analysis(str {, str } )
Module Hierarchy
Modules can instantiate other modules so that networks of modules can be
constructed. Structural statements are used inside the module block but cannot
be used inside the analog block.
module_name #({.param1(expr){, .param2(expr})}
instance_name ({node {, node});
Example
my_src #(.fstart(100), .ramp(z)) u1 (plus, minus);
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Simulation with Verilog-A Modules
When simulating with Verilog-A in HSPICE, you need to have the following
basic input files:
■
HSPICE netlist/model card (Mandatory)
■
Verilog-A model file (e.g., *.va or *.vams file) or Compiled Model Library file
(*.cml) (Mandatory)
■
HSPICE Verilog-A feature setup options (Optional, Mandatory under certain
conditions)
Basic output files:
■
HSPICE standard output files
■
The *.val file, Verilog-A log file, which contains Verilog-A specific message
from compiling and simulating phase. The contents of *.val file is also
echoed to the *.lis file.
■
Compiled Verilog-A code (.cml file) (when Verilog-A modules are compiled
manually).
Loading Verilog-A Devices
This section describes how to load Verilog-A modules into HSPICE. A module
must be loaded before it can be instantiated.
Verilog modules are loaded into the HSPICE simulation in one of two ways: via
the .hdl command inside the HSPICE netlist or via the HSPICE commandline option – hdl.
Files can be in the current directory or specified via an absolute or relative path.
The Verilog-A file is assumed to have a *.va extension when only a prefix is
provided. For example, .hdl “model” looks for the model va file only, not the
model file.
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HSPICE .hdl Netlist Command
The netlist statement allows you to declare the Verilog-A source name and path
explicitly within the netlist.
Syntax
.hdl "filename"
Example
.hdl "/myhome/Verilog_A_lib/res.va"
The .hdl netlist command is used to load a Verilog-A model file res.va from
the directory /myhome/Verilog_A_lib.
HSPICE -hdl Command-line Option
The -hdl command-line option is equivalent to the .hdl command in netlists.
The Verilog-A file is assumed to have a *.va extension when only a prefix is
provided. One -hdloption can include one Veirlog-A file, using multple -hdl
options if multiple Verilog-A files needed.
Syntax
-hdl name
Example
hspice amp.sp -hdl amp.va
In this example the modules are loaded from the amp.va Verilog-A source file.
Verilog-A Search Path
During a simulation, HSPICE searches in the current directory for Verilog-A
files. You can also provide a search path via either a command-line option or an
environment variable (for example, HSP_HDL_PATH) to have HSPICE search
other directories for the files. The -hdlpath HSPICE command-line option is
provided for HSPICE Verilog-A use only, which defines the search path
specifically for Verilog-A files.
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Syntax
hspice -hdlpath path
Example 1
hspice amp.sp -hdlpath ./my_modules
When a Verilog-A file cannot be found in current working directory, HSPICE
searches the directory defined by -hdlpath, in this case the relative directory
./my_modules, for it.
Alternatively, you can also use the HSP_HDL_PATH environment variable to
define search path for Verilog-A files.
Example 2
This example assumes the csh shell is used.
setenv HSP_HDL_PATH
/lib_path/veriloga
When a Verilog-A file cannot be found in the current working directory or the
directory defined by -hdlpath, or there is no -hdlpath defined, HSPICE
searches directory defined by HSP_HDL_PATH for the Verilog-A file.
The directory search order for Verilog-A files is:
1. Current working directory
2. Path defined by -hdlpath
3. Path defined by HSP_HDL_PATH
The path defined by either -hdlpath or HSP_HDL_PATH can consist a set of
directory names. The path separator must follow HSPICE conventions or
platform conventions (“;” on UNIX). Path entries that do not exist are ignored
and no error or warning messages are issued.
HSPICE -vamodel Command-line Option
Use the -vamodel command-line option to specify cell names for Verilog-A
definitions.
Syntax
hspice <name> -vamodel <name2> ...
The name is the cell name that uses a Verilog-A definition rather than a
subcircuit definition when both exist. Each command-line -vamodel option can
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take no more than one name. Repeat -vamodel if multiple Verilog-A modules
are defined. If a name is not specified after -vamodel, then in any case the
Verilog-A definition overrides the subcircuit (whenever it is available).
Verilog-A File Loading Considerations
Several restrictions and issues must be considered when loading Verilog- A
modules:
■
The load command (.hdl) can be placed anywhere in the top level circuit.
All Verilog-A modules are loaded into the system prior to any device
instantiation.
■
The .hdl statement is not allowed inside .subckt blocks. If an .hdl
statement is used inside a .subckt block, the simulation exits and an error
message is issued.
■
The .hdl statement is not allowed inside IF-ELSEIF-ELSE blocks. If an
.hdl statement is found within a block, the simulation exits and an error
message is issued.
■
When a module to be loaded has the same name as a previously-loaded
module, or the names differ in case only, the latter one is ignored and the
simulator issues a warning message.
■
If a Verilog-A module file is not found or the Compiled Model Library file has
an incompatible version, the simulation exits and an error message is
issued.
Verilog-A Behavior in a .ALTER Analysis
Verilog-A .hdl load commands can be placed in .alter statements to vary
the simulation behavior. One use can be to compare multiple variations of
Verilog-A modules
Example
For the first simulation run, HSPICE loads the module called va_amp from the
amp_one.va file. In the second run, HSPICE loads the va_amp module from
the amp_two.va file.
* simple .alter test
.hdl amp_one.va
v1 1 0 10
x1 1 0 va_amp
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.tran 10n 100n
.alter alter1
.hdl amp_two.va
.end
Instantiating Verilog-A Devices
Verilog-A devices are X elements. A Verilog-A device can have zero or more
nodes and can accept zero or more parameter assignments. Verilog-A devices
also support the concept of a model card. In either instance statements or
model card statements, invalid parameters that are not predefined in the
Verilog-A module file are ignored. HSPICE issues a warning message on those
invalid parameters.
Syntax
X<inst> <nodes> moduleName|ModelName param=value
Verilog-A module definitions are unique in each HSPICE simulation. A VerilogA module that matches the name, or differs only in case of a previously loaded
module is ignored. A Verilog-A module definition is ignored if its name conflicts
with HSPICE built-in models.
For any X element, the default search order to find the cell definition is:
1. HSPICE sub-circuit definition
2. Verilog-A model card
3. Verilog-A module definition
Example
Suppose you have the following HSPICE netlist fragment:
.hdl "mydiode"
X1 a b mydiode
.model mydiode D …
In this example, the simulation fails even though the Verilog-A module
mydiode is loaded. The reason is that the simulator finds the model card
mydiode first, which is an HSPICE built-in 'D' model—not a Verilog-A model.
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Using Model Cards with Verilog-A Modules
The HSPICE Verilog-A device supports the concept of model cards, with similar
usage to HSPICE standard built-in devices. The 'type' of model card(s) should
be the same as the Verilog-A module name. Every Verilog-A module can have
one or more associated model cards. The 'type' of model card(s) is the same
as the Verilog-A module name.
Unlike built-in device model cards and instances, you can specify any module
parameter in Verilog-A model cards, instance statements, or inherited
parameter values from module definitions. Instance parameters always
override model parameters.
If the model card includes parameters that is not predefined in its associated
module file, HSPICE issues a warning message and ignores the parameter.
Syntax
.model mname type <pname1= > <pname2= >
+ <pname3= > …
Parameter
Description
mname
User defined model name reference. Elements must use this name to
refer to this model card.
type
Model type, it must be the same as Verilog-A module name.
pname#
Parameter name. Every parameter must be predefined in its associate
Verilog-A module with default parameter value set. For legibility, use
either blanks or commas to separate each assignment. Use a plus sign
(+) to start a continuation line.
Example
For the following examples, assume the following Verilog-A module is used:
module va_amp(in, out);
input in;
output out;
..
electrical in, out;
parameter real gain=1.0;
parameter real fc=100e6;
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analog begin
…
Its associated model cards can then be:
.model myamp_model va_amp gain=2 fc=200e6
.model myamp_model_2 va_amp gain=10
The instantiations of Verilog-A module va_amp can be in the following different
ways:
x1
x2
x3
x4
x5
n1
n3
n5
n7
n9
n2 myamp_model
n4 myamp_model gain=3.0
n6 myamp_model gain=2.0 fc=150e6
n8 myamp_model_2 fc=300e6
n10 va_amp
The instance x1 inherits model myamp_model parameters, i.e., gain=2,
fc=200e6; Similarly, the instance x2 inherits 'fc=200e6' from model
myamp_model but overrides 'gain' with the value 3.0. The instance x3 overrides
all model myamp_model parameters. The instance x4 inherits parameter
'gain=10' from model myamp_model_2, and overrides parameter 'fc', which is
an implicit parameter in myamp_model_2.
Alternatively, the instance x5 does not use a model card and directly
instantiates the Verilog-A module 'va_amp' and inherits all module va_amp
default parameters, which are "gain=1" and "fc=100e6."
Restrictions on Verilog-A Module Names
Verilog-A module name cannot conflict with certain HSPICE built-in device
keywords. If a conflict occurs, HSPICE issues a warning message and the
Verilog-A module definition is ignored.
The following built-in device keywords cannot be used as Verilog-A module
names:
AMP
C
CORE
D
L
NJF
NMOS
NPN
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OPT
PJF
PLOT
PMOS
PNP
R
U
W
SP
Overriding Subcircuits with Verilog-A Modules
If both a sub-circuit and a Verilog-A module have the same case-insensitive
name, by default, HSPICE uses the sub-circuit definition. This behavior can be
changed by setting the vamodel options, either at the command line or in
a .OPTION statement.
The VAMODEL option works on cell-based definitions only. Instance-based
overriding is not supported.
Netlist Option
Syntax
.OPTION vamodel[=name]
The name is the cell name that uses a Verilog-A definition rather than the subcircuit when both exist. Each vamodel option can take no more than one
name. Multiple names need multiple vamodel options.
If no name is provided for the vamodel option, HSPICE uses the Verilog-A
definition whenever it is available.
Example 1
.option vamodel=vco
This example instructs HSPICE to use Verilog-A definition for all instantiations
of cell vco.
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Example 2
.option vamodel=vco vamodel=chargepump
This example instructs HSPICE to use Verilog-A definition for all instantiations
of cell vco and cell chargepump.
Example 3
.option vamodel
This example instructs HSPICE to always use the Verilog-A definition whenever
it is available.
Command-line Option
Syntax
-vamodel <name> -vamodel <name2> …
The name is the cell name that uses a Verilog-A definition rather than subcircuit when both are exist. Each command-line -vamodel option can take no
more than one name. Repeat -vamodel if multiple Verilog-A modules are
defined.
If no name after -vamodel is supplied, then in any case the Verilog-A
definition, whenever it is available, overrides the sub-circuit.
The following examples show various ways to set the option and the resulting
HSPICE behavior.
Example 1
hspice pll.sp –vamodel vco
This example instructs HSPICE to use Verilog-A definition for all instantiations
of cell vco.
Example 2
hspice pll.sp –vamodel vco –vamodel chargepump
This example instructs HSPICE to use Verilog-A definition for all instantiations
of cell vco and cell chargepump.
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Example 3
hspice pll.sp –vamodel
This example instructs HSPICE to always use a Verilog-A definition whenever it
is available.
Disabling .OPTION vamodel with .OPTION spmodel
Use the .OPTION spmodel netlist option to switch back to the HSPICE
definition. For example, if you override the HSPICE definition with the Verilog-A
definition using .OPTION vamodel, use .OPTION spmodel during .ALTER
analysis to revert to the HSPICE definition, which is the same as the
VAMODEL option. The SPMODEL option works on cell-based definitions only.
Instance-based overriding is not supported.
Syntax
.OPTION spmodel[=name]
The name is the cell name that will use spice definition. Each “spmodel” option
can take no more than one name, multiple names need multiple “spmodel”
options.
Example 1
.option spmodel
This example disables the previous .OPTION vamodel, but has no effect on
the other vamodel options if they are specified for the individual cells. For
example, if .option vamodel=vco is set, the cell of vco uses the Verilog-A
definition whenever it is available.
Example 2
.option spmodel=chargepump
This example disables the previous .option vamodel=chargepump, which
causes all instantiations of chargepump to now use the subcircuit definition
again.
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Using Vector Buses or "Ports"
The Verilog-A language supports the concept of buses (vector ports), whereas
HSPICE does not. If you instantiate a module that has a vector port, the
connections to individual bus signals in the HSPICE netlist must be specified.
The Verilog-A module internally expands the vector port and connects them to
the signals inside the Verilog-A module.
Example
Given a Verilog-A module with a vector port defined:
module d2a(out, in, clk);
input [1:4] in;
input clk;
output out;
electrical [1:4] in;
electrical out;
analog begin …
Its instantiation in HSPICE could be:
x1 out in1 in2 in3 in4 clk d2a
In this case, the nodes in1 through in4 are mapped to ports in[1] -> in[4],
respectively. The order of the vector definition is important. If the bus in VerilogA module is specified as electrical [4:1], then the signals would be connected
as in1 -> in4 to in[4] -> in[1] respectively.
Using Integer Parameters
HSPICE netlist parameters are all of type real. When an integer Verilog-A
parameter is assigned a real value, it is coerced to an integer value.
Implicit Parameter M Support
Verilog-A supports the multiplicity factor. A Verilog-A device can have
parameter that is not device specific:
M
Multiplicity factor
If a loaded Verilog-A module has parameter with the name of either 'M' or 'm,'
then that module parameter cannot be set in the instance line. The 'M' or 'm'
parameter in the instance line always means the "Multiplicity factor" parameter
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and the appropriate multiplicity factor is applied to the Verilog-A device during
the simulation. The implicit device parameter scaling factor S and the
temperature difference between the element and circuit, DTEMP, are not
supported.
Module and Parameter Name Case Sensitivity
Verilog-A is a case sensitive language, whereas HSPICE is case insensitive.
This places certain restrictions on use in terms of module and parameter
names and output control.
Module Names
When an attempt to load a second module into the system with a module name
that differs from a previously loaded module by case only, then the second
module is ignored and a warning message is issued
Module Parameters
Parameters in the same module with names that differ by case only cannot be
reassigned in either Verilog-A instance line or Verilog-A .MODEL cards. HSPICE
issues a warning message and ignores this parameter definition.
Example
In this example a simple amplifier accepts two parameters, gain and Gain, as
input to the module.
module my_amp(in, out);
electrical in, out;
parameter real gain = 1.0;
parameter real Gain = 1.0;
analog V(out) <+ (Gain+gain)*V(in);
endmodule
If you instantiate this module as:
x1 n1 n2 my_amp Gain=1
HSPICE cannot uniquely define the Gain parameter, so a warning message is
issued and the definition of Gain is ignored. This module can be instantiated as
is, provided neither the Gain nor gain parameter is assigned in the netlist.
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Output Simulation Data
Verilog-A devices support the same output capabilities as built-in devices. You
can access the following Verilog-A device quantities via any of these HSPICE
output statements: .PRINT, .PLOT, .PROBE, .GRAPH, .DOUT, etc.
■
Port current
■
Port voltage
■
Internal node voltage
■
Internal named branch current
■
Internal module variables
■
Module parameters
V() and I() Access Functions
You can access port voltage and internal node voltage of Verilog-A devices via
the V() function. Port current and internal branch currents can be accessed via
the I() function.
Examples:
For the following examples, assume the Verilog-A module definition fragment
is:
module va_fnc(plus, minus);
inout plus, minus;
electrical plus, minus;
electrical int1, int2;
branch (int1, int2) br1;
//creates an internal branch br1 between internal
//nodes int1 and int2;
analog begin
…
And the Verilog-A module may be instantiated in the netlist as:
x1 1 2 va_fnc
To print the current on Verilog-A device port name plus for the instance x1:
.print I(x1.plus)
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The plus is the port name defined in Verilog-A module, not the netlist node
name.
To print the Verilog-A module internal node named int1 for the instance x1:
.print V(x1.int1)
If the va_fnc module is hierarchical and has a child instance called c1 with an
internal node int1 then the node int1 can be output as
.print V(x1.c1.int1)
That is, the full HSPICE instance name is concatenated with the full internal
Verilog-A instance name to form the complete name.
During compilation of Verilog-A modules, the compiler optimizes some internal
branches out of the system such that these branches are not available for
output. HSPICE Verilog-A provides a compilation environment variable,
HSP_VACOMP_OPTIONS, with –B option being set, all internal named branches
in Verilog-A modules become accessible. However, making all internal
branches accessible may have negative impact on simulation performance;
turn on the option only when necessary.
Refer to section “Setting Environment option for HSPICE Verilog-A Compiler”
for examples of setting HSP_VACOMP_OPTIONS.
After HSP_VACOMP_OPTIONS –B is set, you can probe branch current with
HSPICE output commands. In the previous Verilog-A module, there is an
internal branch name br1 declared. To probe the branch current
.print I(x1.br1)
Output Bus Signals
Verilog-A bus signals can be accessed with HSPICE output commands using
the Verilog-A naming and accessing conventions.
Example
Given an example Verilog-A module:
module my_bus(in, out);
electrical in;
electrical [1:4] out;
…
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And instantiated in the netlist as
x1 1 2 3 4 5 my_bus
then the values of the vector port out can be output by explicitly listing each
position.
.print v(x1.out[1]), v(x1.out[2]), v(x1.out[3]), v(x1.out[4])
Bus elements can also be specified using wildcards, as described in the
section Using Wildcards in Verilog-A on page 459.
Output Internal Module Variables
Verilog-A internal variables, by default, are hidden from output. HSPICE
Verilog-A provides a compilation environment variable,
HSP_VACOMP_OPTIONS, with –G option being set, all internal variables of
Verilog-A instances become accessible. However, making all internal variables
accessible may have negative impact on simulation performance, turn on the
option only when necessary.
Refer to section “Setting Environment option for HSPICE Verilog-A Compiler”
for examples of setting HSP_VACOMP_OPTIONS.
After HSP_VACOMP_OPTIONS -G is set, you can use HSPICE output command
to access internal module variables of Verilog-A instances.
Syntax
Instance:internal_variable
Example
.print xva_vco:freq
This example outputs internal variable frequency value of Verilog-A instance
xva_vco.
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Output Module Parameters
You can use HSPICE output commands to output parameter values for VerilogA instances.
Syntax
Instance:parameter
Example
.print xva_1:gain
This example outputs the gain parameter value for the xva_1 Verilog-A
instance.
Verilog-A Device Output Simulation Data
When Verilog-A information is output via the HSPICE output commands, the
case of the node names associated with the quantities to be output is ignored.
Contributions from the Verilog-A noise sources that have the same name when
case is ignored are combined.
Example
I(d,s) <+ white_noise(4*k*T/R1, "thermalnoise");
I(d2,s2) <+ white_noise(4*k*T/R2, "ThermalNoise");
The two noise contributions are combined into one contribution called
thermalnoise in the output files.
The internal nodes of Verilog-A devices are accessible via the V() function
when the full hierarchical name is provided. The port current and named
branches (on the instance base only) can be accessible via the I() function.
Verilog-A module variables are not accessible.
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Using Wildcards in Verilog-A
Verilog-A names support the use of wildcards to simplify using the output
commands.
Examples:
Given the Verilog-A module,
module test(p,n);
electrical p,n;
electrical int1, int2;
…
instantiated as
x1 1 2 test
then all of the internal nodes (in this case int1 and int2) can be printed using
the command:
.print v(x1.*)
All indices of a bus in the module:
module my_bus(in, out);
electrical in;
electrical [1:4] out;
…
can be specified as:
x1 1 2 3 4 5 my_bus
.print v(x1.out[*])
.print v(x1.*)
Both of the internal nodes, int1 and int2 for the child ch1 in the instance
x_par1 can be specified using
.print v(x_par1.ch1.int*)
The HSPICE .OPTION POST command does not output internal nodes from
Verilog-A modules. Use the wildcard feature to specify a Verilog-A instance if
you need to output all internal nodes.
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Using the Stand-alone Compiler
Port Probing and Branch Current Reporting Conventions
When printing and reporting currents for Verilog-A devices, HSPICE follows the
same conventions when specifying the direction of current flow as in built-in
devices. A positive branch current implies that current is flowing into the device
terminal or internal branch.
Unsupported Output Function Features
The following output functions are not supported in this release:
■
Port probing: In( ), where n is the node number). Instead, you can use
I(instance.port_name_in_module).
■
Iall(): Instead, you can output all the terminal currents using a wild card.
■
Isub(): This is not applicable to Verilog-A components.
■
P() and Power(): Instead, you can use the $strobe Verilog-A function .
■
Nodal capacitance
■
Group delay
Using the Stand-alone Compiler
Verilog-A modules used in HSPICE simulations are automatically compiled and
cached by the simulator. You can compile files manually if you wish (to check
syntax for example). The Verilog-A compiler takes a Verilog-A file as an input
and produces a Compiled Model Library (CML) file, which is a platform-specific
shared library.
Example 1
hsp-vacomp resistor.va
The Verilog-A compiler, hsp-vacomp, compiles the Verilog-A module file
resistor.va, and produces a Compiled Model Library file resistor.cml in the
same directory.
You can include the Compiled Model Library file in the same manner as the
Verilog-A file in an HSPICE netlist.
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Example 2
.hdl "resistor.cml"
Note: When a CML file is specified in the load command the compiler is never
invoked, even if the source file is modified.
Setting Environment Option for HSPICE Verilog-A Compiler
While Verilog-A modules are automatically compiled in HSPICE simulation, you
can set environment variable HSP_VACOMP_OPTIONS to control compiler
options from default setting.
Example 1
setenv HSP_VACOMP_OPTIONS –G
When –G is set, all internal variables are accessible for output.
Example 2
setenv HSP_VACOMP_OPTIONS –B
When –B is set, all internal named branches are accessible for output.
The Compiled Model Library Cache
The HSPICE Verilog-A solution provides the performance of a compiled
solution without the need for user intervention. The first time a Verilog-A source
file is loaded, or after a Verilog-A source file is modified, the system
automatically invokes the compiler. The Compiled Model Library (CML) is
automatically cached and subsequent simulations use this cached file and
bypass the compilation process. Although for the most part you do not need to
be concerned with the cache mechanism, you can control some aspects. You
can change the cache location, prevent caching, or delete the cache.
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The Compiled Model Library Cache
Cache Location
By default the cache directory is located in your $HOME directory under the
hidden directory .hsp-model-cache
This directory holds a directory structure that indicates compiler version,
platform, and model directory.
Example
Given the load command
.hdl "/users/finn/modules/amp.va"
the compiler generates a CML file in
/users/finn/.hsp-modelcache/1.17/users/finn/modules/lib.<arch>/amp.cml
Where <arch> is one of hpux, sun, linux, etc.
The location of the cache can be changed from the default value by setting the
environment variable HSP_CML_CACHE to an appropriate location.
Example
The following sets the environment variable HSP_CML_CACHE so that the
model cache is created under the my_local_cache directory.
setenv HSP_CML_CACHE /users/finn/my_local_cache
If the previous example were now simulated the CML file would be
/users/finn/my_local_cache/1.17/users/finn/modules/lib.<arch>
/amp.cml
Deleting the Cache
The cache structure is maintained unless you chooses to delete it manually.
You can do this any time; HSPICE automatically recreates the cache when
needed. One reason to delete the cache is if a newer version of the HSPICE
Verilog-A compiler is used and the previous cache is no longer necessary. The
cache can be deleted using conventional operating system commands.
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Unsupported Language Features
Example
To delete the default cache, from the operating system command prompt,
execute
rm –r ~/.hsp-model-cache
Unsupported Language Features
The following Verilog-A LRM 2.1 Language Features are not supported.
■
Escaped identifiers
For example:
real \bus+index; // Not supported
■
Derived natures described in LRM version 2.1 section 3.4.1.1
For example, the following deriving the nature New_curr from Ttl_curr is not
supported.
nature Ttl_curr
units = "A" ;
access = I ;
abstol = 1u ;
endnature
// The derived nature is not supported:
nature New_curr : Ttl_curr
abstol = 1m ;
maxval = 12.3 ;
endnature
■
Input, output, and inout enforcement described in LRM version 2.1, section
7.1.
module test(in,out);
electrical in,out;
input in;
output out;
real out_value;
analog begin
out_value = 1.0;
V(in) <+ out_value;
// Input node used as output
// is not prevented, V(in) will be
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// assigned to out_value
end
endmodule
■
The defparam statement as described in LRM version 2.1, section 7.2.1
For example:
module rc(n1, n2);
electrical n1, n2;
my_res r1 (n1, n2);
my_cap c1 (n1, n2);
endmodule
module my_res(n1, n2);
electrical n1, n2;
parameter dev_temp = 27;
parameter res = 50;
parameter tcr = 1;
analog
V(n1,n2) <+ I(n1,n2)*res*tcr*($temperaturedev_temp);
endmodule
module my_cap(n1, n2);
electrical n1, n2;
parameter dev_temp = 25;
parameter cap = 1;
parameter tcc = 1;
analog
I(n1,n2) <+ cap*ddt(V(n1,n2))*tcc*($temperature
dev_temp);
endmodule
// defparam statement not supported
module annotate;
defparam
rc.r1.dev_temp = 30;
rc.c1.dev_temp = 25;
endmodule
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Unsupported Language Features
■
Ordered parameter lists in hierarchical instantiation as described in LRM
version 2.1, section 7.2.2.
For example:
module module_a(out,out2);
electrical out,out2;
parameter real value1 = -10.0;
parameter real value2 = -20.0;
analog begin
V(out) <+ value1;
V(out2) <+ value2;
end
endmodule
module test_param_by_order(out,out2);
electrical out,out2;
parameter real value1 = -1.0;
parameter real value2 = -2.0;
// Ordered parameter lists are not supported:
module_a #(1,2) A1(out,out2);
// instead use:
module_a #(.value1(1),.value2(2)) A1(out,out2);
endmodule
■
Out-of-module-references as described in the LRM version 2.1, section 7.
For example:
In this example, the reference to example2.net inside the example1
module is not supported.
module example1;
electrical example2.net; // Feature not supported
endmodule
module example2;
electrical net;
endmodule
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Unsupported Language Features
■
Vector ports, where the port expression defining the size of a port is a
parameter expression, as described in LRM version 2.1 section 7.3.1.
Example:
In this example, the vector port range size must be a constant—not a
parameter value.
module test(out);
parameter integer size = 7 from [1:16];
electrical [0:size] out; // Feature not supported
analog begin
V(out[0]) <+ 0.0;
end
endmodule
■
‘timescale directive, as described in LRM version 2.1, section 10.1.
`timescale 1ns/10ps
■
// Feature not supported
The $monitor function, as described in LRM version 2.1, section 10.6.
$monitor("\nEvent occurred."); // Feature not supported
■
The `default_discipline directive, as described in LRM version 2.1, section
11.1.
Example
In the following example, the ports in and out must have their discipline
explicitly declared.
`include "disciplines.vams"
`default_discipline electrical
// Feature not supported
module test(in,out);
// in,out default to electrical
analog
V(out) <+ I(in);
endmodule
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Known Limitations
■
Access to HSPICE primitives from a Verilog-A module, as described in LRM
version 2.1, section E.2.
Example
module spice_rc (p1,p2);
electrical p1, p2;
capacitor #(.c(3p)) C3 (p1, p2); // Feature not
// supported
resistor #(.r(1k)) R1 (p1, p2); // Feature not
// supported
endmodule
Known Limitations
This section describes the known limitiations when using Verilog-A with
HSPICE.
analysis() Function Behavior
The analysis() function definition assumes that the operating point (OP)
analysis associated with any user-specified analysis is unique to that userspecified analysis.
For example, when you specify the following function, it must return 1 for AC
analysis and 1 for its underlying operation point (OP) analysis.
analysis("ac")
Similarly, analysis("tran") must return 1 for transient analysis and 1 for its
underlying OP analysis.
In HSPICE, a single "common" OP analysis is performed in the setup that is
outside the context of AC, transient, or other analyses. Since that OP is outside
the context of the user-specified analysis, the analysis() function does not know
the parent analysis type (during the OP analysis). The analysis("ac"),
analysis("tran"), etc., returns 0 during this “common” OP analysis. You can
ensure that the analysis function returns true (1) during these analyses by
adding “static” to the list of functions.
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Example
if ( analysis("ac") )
begin
// do something
end
Should be written as:
if( analysis("ac", "static") )
begin
// do something
end
The same is true for the “tran” and “noise” analysis names.
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DC Mismatch Analysis
31
Describes the use of DCmatch analysis.
Mismatch
The characteristics of identically designed devices on the same piece of silicon
differ slightly between each other as a result of variations in manufacturing.
These are random time-independent variations by nature and are collectively
called mismatch.
Mismatch is one of the limiting factors in analog signal processing. It affects
more and more circuit types as device dimensions and signal swings are
reduced. Mismatch is a function of the geometry of the devices involved, their
spatial relationship (distance and orientation) and their environment. Mismatch
does not include batch-to-batch or wafer-to-wafer variations, or offsets caused
by operating point differences or device degradation.
Simulation Methods for Variability
The Monte Carlo method is generally used for predicting variations in circuit
response; however it is computationally expensive. For cases where the circuit
response of interest is based on a DC solution, a method called DC mismatch
(DCmatch) analysis can be used. DCmatch is related to sensitivity and noise
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DCmatch Analysis
analyses, and requires less time than Monte Carlo. Thus, DCmatch analysis
provides an efficient technique for the approximate computation of variability in
circuit DC solutions.
DCmatch Analysis
In DCmatch analysis, the combined effects of variations of all devices on a
specified node voltage or branch current are determined. The variations
considered are local (that is, for devices in close proximity). DCmatch analysis
also allows for identifying groups of matched devices (that is, devices that
should be implemented on the layout according to special rules).
DCmatch analysis is based on the following dependencies and assumptions:
■
variations in device characteristics are modeled through variations in the
underlying model parameters.
■
statistics of the model parameters exhibit Gaussian distributions.
■
no correlation exists between the variations of different parameters of a
single device, or between the same parameter for different devices.
■
effects on a circuit’s DC solution are small; therefore, these variations also
exhibit Gaussian distributions.
In HSPICE, the variations in model parameters are defined in a special
DCmatch definition block by using expressions with parameters and functions.
This approach allows for a very flexible description of the relationship between
device geometry and DCmatch variation. Similar to device model parameters,
the expressions must be derived from dedicated test structures for a given
semiconductor technology.
HSPICE runs the DCmatch analysis either from a default operating point or for
each value of the independent variable in a single DC sweep. The default
output is in the form of tables containing the sorted contributions of the relevant
devices to the total variation, as well as information on matched devices. In the
current implementation, a heuristic algorithm makes a best guess effort to
identify matched devices. This means that the results are suggestions only. In
addition to the table, the total variation and contributions of selected devices
can be output using .PROBE and .MEASURE commands.
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DCmatch Analysis
Input Syntax
.DCMATCH OUTVAR <THRESHOLD=T> <FILE=string>
+ <PERTURBATION=P> <INTERVAL=Int>
Parameter
Description
OUTVAR
Valid node voltages, the difference between node
pairs, or branch currents.
THRESHOLD
Report devices with a relative variance contribution
above Threshold in the summary table.
• T=0: reports results for all devices
• T<0: suppresses table output; however,
individual results are still available through
.PROBE or .MEASURE statements.
The upper limit for T is 1, but at least 10 devices are
reported, or all if there are less than 10. Default
value is 0.01.
FILE
Valid file name for the output tables. Default is
basename.dm# where “#” is the usual sequence
number for HSPICE output files.
PERTURBATION
Indicates that perturbations of P standard deviation
will be used in calculating the finite difference
approximations to device derivatives. The valid
range for P is 0.01 to 6, with a default value of 2.
INTERVAL
Applies only if a DC sweep is specified. Int is a
positive integer. A summary is printed at the first
sweep point, then for each subsequent increment of
Int, and then, if not already printed, at the final
sweep point. Only single sweeps are supported.
Note: If more than one DCmatch analysis is specified per simulation, only the
last statement is used.
Example 1
.DCmatch V(9) V(4,2) I(VCC)
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HSPICE reports DCmatch variations on the voltage of node 9, the voltage
difference between nodes 4 and 2, and on the current through the source VCC.
Example 2:
.DC XVal Start=1K Stop=9K Step=1K
.DCmatch V(out) Interval=3
The variable XVal is being swept in the DC command, from 1k to 9k in
increments of 1k. DCmatch variations are calculated for the voltage on node
out. Tables with DCmatch results are generated for the set XVal={1K, 4K, 7K,
9K}.
DCmatch Definition Block
The variations in device characteristics are described in a special definition
block separate from the model file. The block contains an entry for each device
type for which the DCmatch contribution must be calculated. The syntax
chosen for the DCmatch Definition block allows for future extensions to other
types of variability analysis.
Input Syntax
.Variation
.Local_Variation
modelType modelName modelParam1='Expression1 for Sigma'
+ modelParam2='Expression2 for Sigma'
.End_Local_Variation
.End_Variation
The variable ExpressionN for Sigma defines the DCmatch variation for the
model parameter of a device with the specified modelType and modelName.
The expression can be a constant, a parameter, or a function containing
allowed instance parameters. The variation can be specified as a percentage of
the nominal value, by adding a space and a % character after the expression.
With this syntax, the specified variation is divided by 100 internally. Note that
expressions that require single quotes according to standard HSPICE syntax
must be on a single line.
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Accessing Instance Parameters in Expressions for Sigma
Instance parameters can be referenced to specify DCmatch variation as a
function of device geometry, using the syntax E(*); for example, E(L) and
E(W).
Supported instance parameters are:
Resistor
L
W
M
Diode
L
W
M
BJT
AREA
AREAB
AREAC
JFET
L
W
M
MOS
L
W
M
M
Example
.Variation
.Local_Variation
nmos snps20N vth0='1.234e-9/sqrt(E(W)*E(L)*E(M))'
pmos snps20P u0='2.345e-6/sqrt(E(W)*E(L)*E(M))' %
res rmod res =3 %
.End_Local_Variation
.End_Variation
In this example, the nmos device has an absolute variation of model parameter
vth0, dependent on the square root of the total device area. The pmos device
shows a relative variation of model parameter u0, dependent on the square
root of the device area. The resistor exhibits a relative variation of the
parameter res.
DCmatch Table Output
For each output variable and sweep point, HSPICE generates a sorted table
with the contributions of all the relevant devices. Each table is preceded by a
header with the following information:
■
sweep or operating points for which the table is generated
■
name of the output variable
■
DC value of this output variable
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■
values used for DCmatch options
■
number of devices which had no local variability specified
■
sigma of the specified output variables due to mismatch
■
number of devices that had local variance contributions below the threshold
value and were not included in the table.
The table includes the sorted device contributions in the following format:
■
Contribution Sigma (in volts or amperes). Values below 100nV or 1pA are
rounded to zero to avoid reporting numerical noise.
■
Contribution Variance for the ith device (in percent).
2
sigma ( i ) -------------------------------× 100
n
2
sigma
(
k
)
∑
1
The Threshold applies to this column.
■
Cumulative Variance through ith device (in percent)
i
∑1sigma ( k )
2
-------------------------------- × 100
n
2
sigma
(
k
)
∑
1
The table also includes a suggestion on matched devices that should be
verified independently. Devices with the same number in the column “Matched
pair” are likely to be matched. Their layout should be reviewed for conformity to
established matching rules.
Example
sweep point = operating point
output = v(out) node voltage =
1.25V threshold = 1.000E-2
perturbation = 2.00
interval = 1
10 Devices had no Local Variability specified.
Total Output Sigma = 547.77uV
4 Devices with Local Variance Contribution larger than Threshold
--------------------------------------------------------------Contribution Contribution Cumulative
Matched
Device
Sigma(V)
Variance (%) Variance (%) pair
Name
295.89u
29.18
29.18
1
xi82.mn1
295.66u
29.13
58.31
1
xi82.mn2
252.11u
21.18
79.49
2
xi82.mp4
247.95u
20.49
99.98
2
xi82.mp3
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6.49u
1.72u
658.15n
0.
14.04m
984.29u
144.36u
0.
100.00
100.00
100.00
100.00
0
0
0
0
xi82.mp5
xi82.mn7
xi82.mn6
xi82.mn8
Output From .PROBE and .MEASURE Commands
The sigma of the contribution of individual devices and the total of all
contributions can be output using .PROBE and .MEASURE commands, for the
output variable specified on the .DCMATCH command. If multiple output
variables are specified, a result is produced for the last one only. The output
statements are ignored if a .DCMATCH command does not exist in the netlist.
Syntax for .PROBE Command
A .PROBE statement in conjunction with .OPTION POST creates a graph data
file that has the x-values being the sweep datapoints and the y-values being the
sigma of the total output variation or the device contribution at these sweep
datapoints.
.PROBE DC DCmatch_total
.PROBE DC DCmatch(InstanceName)
This type of output is useful in conjunction with a DC sweep; for example, for
plotting DCMATCH as a function of bias current, temperature, or a circuit
parameter.
Syntax for .MEASURE Command
In .MEASURE statements, the keyword DCMATCH_TOTAL is used for the total
output sigma as referenced by the output variable specified in the .DCMATCH
command. The keyword DCmatch(InstanceName)is used to output the
contribution sigma of the specified instance.
.MEAS
.MEAS
.MEAS
.MEAS
DC
DC
DC
DC
result3
result4
result5
result6
max dcmatch_total
max dcmatch(InstanceName)
find dcmatch_total at=SweepValue
find dcmatch(InstanceName) at=SweepValue
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In combination with other DC measures:
.MEAS DC systoffset avg V(inp,inn)
.MEAS DC matchoffset avg DCMATCH_TOTAL
.MEAS DC maxoffset param='abs(systoffset)+3.0*matchoffset'
The result systoffset reports the systematic offset of the amplifier; the result
matchoffset reports the variation due to mismatch; and the result
maxoffset reports the maximum (3-sigma) offset of the amplifier.
Practical Considerations
This section discusses practical considerations when using DCmatch analysis.
DCmatch Variability as a Function of Device Geometry
Various parameter relationships for device variability have been used in the
industry. Two approaches are shown below with their expressions for HSPICE.
Example 1
This example assumes a standard transistor size and scales the variation with
the number of devices in parallel. This covers the practice of interdigitating
matched devices of a characterized standard size:
pmos pch vth0 ='dmvp0/sqrt(E(M))'
u0=’dmup0/sqrt(E(M))’ %
Example 2
This example shows an approach that calculates the variation as a function of
device size. Two of the three terms implement the well known dependence on
the inverse of the square root of the device area:
pmos pch vth0 =
+ 'dmpvtwl/sqrt(E(W)*E(L)*E(M)) + dmpvtwll/(E(L)*sqrt(E(W)*E(M)))’
+ u0 =’dmpu0wl/sqrt(E(W)*E(L)*E(M))’ %
Note that the HSPICE approach with user-defined expressions for sigma allows
for much more flexibility than the relationships shown in the above two
examples.
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Parameter Traceability
The parameters and expressions are derived from characterizing dedicated
test structures for a given semiconductor technology. To use this information
successfully, it must be understood how it relates to the results from the
DCmatch analysis.
In the simple example considered in this discussion, variability is modeled as
threshold dependence only in the DCmatch definition block, VTH0 =dmvp0. It
is assumed that this VTH0 change maps directly to a VGS change. In the
characterization of the test structures, the differences in VGS for a transistor
pair at a certain current are collected and then the sigma is calculated as 1mV.
The value for dmvp0 will be defined as 1mV / sqrt ( 2 ) = 0.707mV, because two
devices are involved. After simulating the same setup, HSPICE reports a
contribution of 0.707mV from each device, and a total variation of sqrt ( 0.7072
+ 0.7072 ) mV = 1mV. This is the same value as the original sigma from the test
structure. Thus, all simulation results represent one sigma. For this example to
work properly, it is crucial to know that
■
transistor pairs were measured
■
characterization results represent one sigma
■
DCmatch parameter value was adjusted for a single transistor
■
simulation results represent one sigma.
Of course other scenarios are possible—it is just important to know how the
individual pieces are connected when interpreting the results.
Example
An example netlist for running DCmatch analysis using a classic 7-transistor
CMOS operational amplifier, with device sizes setup as a function of parameter
k, is available in the HSPICE demo directory as:
$installdir/demo/hspice/apps/opampdcm.sp
The following lines relate to DCmatch analysis:
...
.param k=2
...
mn1 net031 inn net044 nmosbulk snps20N L='k*0.5u' W='k*3.5u' M=4
mn2 net18 inp net044 nmosbulk snps20N L='k*0.5u' W='k*3.5u' M=4
mp3 net031 net031 vdda pmosbulk snps20P L='k*0.5u' W='k*4.5u' M=4
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Reference List
mp4 net18 net031 vdda pmosbulk snps20P L='k*0.5u' W='k*4.5u' M=4
...
.variation
.local_variation
nmos snps20N vth0='1.234e-9/sqrt(E(W)*E(L)*E(M))'
+
u0='2.345e-6/sqrt(E(W)*E(L)*E(M))' %
pmos snps20P vth0='1.234e-9/sqrt(E(W)*E(L)*E(M))'
+
u0='2.345e-6/sqrt(E(W)*E(L)*E(M))' %
.end_local_variation
.end_variation
.dcmatch v(out)
.dc k start=1 stop=4 step=0.5
.meas DC systoffset find V(pos,neg) at=2
.meas DC dcmoffset find dcmatch_total at=2
.meas DC maxoffset param='abs(systoffset)+3.0*dcmoffset'
.option post
...
The DCmatch analysis produces four types of output from this netlist:
■
table from operating point in the run listing
■
table from DC sweep in file opampdcm.dm0
■
total output variation as a function of k in file opampdcm.sw0
■
values for systematic offset, total DCmatch variation, and 3-sigma amplifier
offset for k=2 in file opampdcm.sw0
Reference List
1. M.Pelgrom, A.Duinmaijer, and A.Welbers, “Matching Properties of MOS
Transistors,” IEEE J. Solid-State Circuits, vol. 24, no. 5, pp. 1433-1439, May
1989
2. P.R.Kinget, “Device Mismatch and Tradeoffs in the Design of Analog
Circuits,” IEEE J. Solid-State Circuits, vol. 40, no. 6, pp. 1212-1224, June
2005
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Statistical Analysis and Optimization
41
Describes how to use statistical analysis and optimization in HSPICE
to analyze and optimize electrical yield.
When you design an electrical circuit, it must meet tolerances for the specific
manufacturing process. The electrical yield is the number of parts that meet the
electrical test specifications. Overall process efficiency requires maximum
yield. To analyze and optimize the yield, Synopsys HSPICE uses statistical
techniques and observes the effects of variations in element and model
parameters.
Note: HSPICE RF does not support the Worst Case, Monte Carlo, and
Optimization analyses described in this chapter.
■
Analytical Model Types
■
Simulating Circuit and Model Temperatures
■
Worst Case Analysis
■
Monte Carlo Analysis
■
Worst Case and Monte Carlo Sweep Example
■
Optimization
■
Optimization Examples
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Analytical Model Types
For descriptions of individual HSPICE commands referenced in this chapter,
see the HSPICE Command Reference manual.
Analytical Model Types
To model parametric and statistical variation in circuit behavior, use:
■
The .PARAM statement investigates the performance of a circuit as you
change circuit parameters. For details about the .PARAM statement, see the
HSPICE Command Reference manual.
■
Temperature Variation Analysis varies the circuit and component
temperatures, and compares the circuit responses. You can study the
temperature-dependent effects of the circuit, in detail.
■
Monte Carlo Analysis. If you know the statistical standard deviations of
component values, use this analysis to center a design. This provides
maximum process yield, and determines component tolerances. HSPICE
supports Monte Carlo analysis; HSPICE RF does not.
■
Worst Case Corners Analysis (HSPICE RF does not support worst-case
analysis). If you know the component value limit, use this analysis to
automate quality assurance, for:
■
480
•
Basic circuit function.
•
Process extremes.
•
Quick estimation of speed and power trade-offs.
•
Best case and worst case model selection.
•
Parameter corners.
•
Library files.
Data-Driven Analysis (HSPICE only; not used in HSPICE RF). Use for cell
characterization, response surface, or Taguchi analysis. See
“Characterizing Cells” in the HSPICE Applications Manual. Automates
characterization of cells, and calculates the coefficient of polynomial delay
for timing simulation. You can simultaneously vary any number of
parameters, and perform an unlimited number of analyses. This analysis
uses ASCII file format so HSPICE can automatically generate parameter
values. This analysis can replace hundreds or thousands of HSPICE
simulation runs.
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Simulating Circuit and Model Temperatures
Use yield analyses to modify:
■
DC operating points.
■
DC sweeps.
■
AC sweeps.
■
Transient analysis.
These analyses can generate scatter plots for operating point analysis. They
can also generate a family of curve plots for DC, AC, and transient analysis.
Use the .MEASURE statement with yield analyses to view distributions of delay
times, power, or any other characteristic described in a .MEASURE statement.
Often, this is more useful than viewing a family of curves that a Monte Carlo
analysis generates. HSPICE supports Monte Carlo analysis; HSPICE RF does
not.
When you use the .MEASURE statement, HSPICE generates a table of results
in an .mt# file. You can read this file in ASCII format and you can use
AvanWaves to display it. Also, if you use .MEASURE statements in a Monte
Carlo or data-driven analysis (HSPICE only; HSPICE RF does not support
Monte Carlo or data-driven analysis), then the HSPICE output file includes
calculations for standard statistical descriptors:
Mean
x1 + x2 + … + xn
= --------------------------------------N
( x 1 – Mean ) 2 + … ( x n – Mean ) 2
= -----------------------------------------------------------------------------N–1
Variance
Sigma
=
Variance
Average Deviation
x 1 – Mean + … + x n – Mean
= --------------------------------------------------------------------------N–1
Simulating Circuit and Model Temperatures
Temperature affects all electrical circuits. Figure 74 shows the key temperature
parameters associated with circuit simulation:
■
Model reference temperature – you can model different models at different
temperatures. Each model has a TREF (temperature reference) parameter.
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■
Element junction temperature – each resistor, transistor, or other element
generates heat so an element is hotter than the ambient temperature.
■
Part temperature – at the system level each part has its own temperature.
■
System temperature – a collection of parts form a system, which has a local
temperature.
■
Ambient temperature – the ambient temperature is the air temperature of
the system.
Figure 74
Part Junction Temperature Sets System Performance
Ambient Temperature
System Temperature
source
drain
gate
Model Junction Temperature
Part Temperature
source
drain
gate
Part Junction Temperature
HSPICE or HSPICE RF calculates temperatures as differences from the
ambient temperature:
Tambient + ∆ system + ∆ part + ∆ junction = Tjunction
Ids = f ( Tjunction, Tmodel )
Every element includes a DTEMP keyword, which defines the difference
between junction and ambient temperature.
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Example
The following example uses DTEMP in a MOSFET element statement:
M1 drain gate source bulk Model_name W=10u
+ L=1u DTEMP=+20
Temperature Analysis
You can specify three temperatures:
■
Model reference temperature specified in a .MODEL statement. The
temperature parameter is usually TREF, but can be TEMP or TNOM in some
models. This parameter specifies the temperature, in °C, at which HSPICE
or HSPICE RF measures and extracts the model parameters. Set the value
of TNOM in an .OPTION statement. Its default value is 25 °C.
■
Circuit temperature that you specify using a .TEMP statement or the TEMP
parameter. This is the temperature, in °C, at which HSPICE or HSPICE RF
simulates all elements. To modify the temperature for a particular element,
use the DTEMP parameter. The default circuit temperature is the value of
TNOM.
■
Individual element temperature, which is the circuit temperature, plus an
optional amount that you specify in the DTEMP parameter.
To specify the temperature of a circuit in a simulation run, use either the .TEMP
statement, or the TEMP parameter in the .DC, .AC, or .TRAN statements.
HSPICE or HSPICE RF compares the circuit simulation temperature that one
of these statements sets against the reference temperature that the TNOM
option sets. TNOM defaults to 25 °C, unless you use the SPICE option, which
defaults to 27 °C. To calculate the derating of component values and model
parameters, HSPICE or HSPICE RF uses the difference between the circuit
simulation temperature, and the TNOM reference temperature.
Elements and models within a circuit can operate at different temperatures. For
example, a high-speed input/output buffer that switches at 50 MHz is much
hotter than a low-drive NAND gate that switches at 1 MHz). To simulate this
temperature difference, specify both an element temperature parameter
(DTEMP), and a model reference parameter (TREF). If you specify DTEMP in an
element statement, the element temperature for the simulation is:
element temperature = circuit temperature + DTEMP
Specify the DTEMP value in the element statement (resistor, capacitor, inductor,
diode, BJT, JFET, or MOSFET statement), or in a subcircuit element. Assign a
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parameter to DTEMP, then use the .DC statement to sweep the parameter. The
DTEMP value defaults to zero.
If you specify TREF in the model statement, the model reference temperature
changes (TREF overrides TNOM). Derating the model parameters is based on
the difference between circuit simulator temperature and TREF (instead of
TNOM).
.TEMP Statement
To specify the temperature of a circuit for a HSPICE or HSPICE RF simulation,
use the .TEMP statement.
Worst Case Analysis
Circuit designers often use worst-case analysis when designing and analyzing
MOS and BJT IC circuits. To simulate the worst case, set all variables to their 2sigma or 3-sigma worst case values. Because several independent variables
rarely attain their worst-case values simultaneously, this technique tends to be
overly pessimistic and can lead to over-designing the circuit. However, this
analysis is useful as a fast check.
Model Skew Parameters
The Synopsys HSPICE Device Models include physically-measurable model
parameters. The circuit simulator uses parameter variations to predict how an
actual circuit responds to extremes in the manufacturing process. Physicallymeasurable model parameters are called skew parameters, because they skew
from a statistical mean to obtain predicted performance variations.
Examples of skew parameters are the difference between the drawn and
physical dimension of metal, polysilicon, or active layers, on an integrated
circuit.
Generally, you specify skew parameters independently of each other, so you
can use combinations of skew parameters to represent worst cases. Typical
skew parameters for CMOS technology include:
■
484
XL – polysilicon CD (critical dimension of the poly layer, representing the
difference between drawn and actual size).
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■
XWn, XWp – active CD (critical dimension of the active layer, representing
the difference between drawn and actual size).
■
TOX – thickness of the gate oxide.
■
RSHn, RSHp – resistivity of the active layer.
■
DELVTOn, DELVTOp– variation in threshold voltage.
You can use these parameters in any level of MOS model, within the HSPICE
device models. The DELVTO parameter shifts the threshold value. HSPICE
adds this value to VTO for the Level 3 model, and adds or subtracts it from
VFB0 for the BSIM model. Table 61 on page 485 shows whether HSPICE adds
or subtracts deviations from the average.
Table 61 Sigma Deviations
Type
Param
Slow
Fast
NMOS
XL
+
-
RSH
+
-
DELVTO
+
-
TOX
+
-
XW
-
+
XL
+
-
RSH
+
-
DELVTO
-
+
TOX
+
-
XW
-
+
PMOS
HSPICE selects skew parameters based on the available historical data that it
collects either during fabrication or electrical test. For example, HSPICE
collects the XL skew parameter for poly CD during fabrication. This parameter
is usually the most important skew parameter for a MOS process.
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Figure 75 is an example of data that historical records produce.
Figure 75
Historical Records for Skew Parameters in a MOS Process
3 sigma
2 sigma
Fab Database
1 sigma
Run# PolyCD
Mean
101 +0.04u
102 -0.06u
pop.#
103 +0.03u
...
XL value
Using Skew Parameters in HSPICE
Figure 76 shows how to create a worst-case corners library file for a CMOS
process model in HSPICE (HSPICE RF does not support worst-case analysis).
Specify the physically-measured parameter variations so that their proper
minimum and maximum values are consistent with measured current (IDS)
variations. For example, HSPICE can generate a 3-sigma variation in IDS from
a 2-sigma variation in physically-measured parameters.
Figure 76
SS
Worst Case Corners Library File for a CMOS Process Model
Slow Corner Skew Parameters
EE
Extracted Skew Parameters
TT
Typical Corner Skew Parameters + Gaussian
FF
Fast Corner Skew Parameters
pop.
IDS
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The .LIB (library) statement, and the .INCLUDE (include file) statement,
access the models and skew. The library contains parameters that
modify .MODEL statements. The following example of .LIB features both
worst-case and statistical-distribution data by using model skew parameters. In
statistical distribution, the median value is the default for all non-Monte Carlo
analysis (HSPICE RF does not support Monte Carlo analysis).
Example
.LIB TT
$TYPICAL P-CHANNEL AND N-CHANNEL CMOS LIBRARY DATE:3/4/91
$ PROCESS: 1.0U CMOS, FAB22, STATISTICS COLLECTED 3/90-2/91
$ following distributions are 3 sigma ABSOLUTE GAUSSIAN
.PARAM
$ polysilicon Critical Dimensions
+ polycd=agauss(0,0.06u,1) xl=’polycd-sigma*0.06u’
$ Active layer Critical Dimensions
+ nactcd=agauss(0,0.3u,1) xwn=’nactcd+sigma*0.3u’
+ pactcd=agauss(0,0.3u,1) xwp=’pactcd+sigma*0.3u’
$ Gate Oxide Critical Dimensions (200 angstrom +/- 10a at 1
$ sigma)
+ toxcd=agauss(200,10,1) tox=’toxcd-sigma*10’
$ Threshold voltage variation
+ vtoncd=agauss(0,0.05v,1) delvton=’vtoncd-sigma*0.05’
+ vtopcd=agauss(0,0.05v,1) delvtop=’vtopcd+sigma*0.05’
.INC ‘/usr/meta/lib/cmos1_mod.dat’$ model include file
.ENDL TT
.LIB FF
$HIGH GAIN P-CH AND N-CH CMOS LIBRARY 3SIGMA VALUES
.PARAM TOX=230 XL=-0.18u DELVTON=-.15V DELVTOP= 0.15V
.INC ‘/usr/meta/lib/cmos1_mod.dat’$ model include file
.ENDL FF
The /usr/meta/lib/cmos1_mod.dat include file contains the model.
.MODEL NCH NMOS LEVEL=2 XL=XL TOX=TOX DELVTO=DELVTON . .
.MODEL PCH PMOS LEVEL=2 XL=XL TOX=TOX DELVTO=DELVTOP . .
Note: The model keyname (left) equals the skew parameter (right). Model keys
and skew parameters can use the same names.
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Skew File Interface to Device Models
Skew parameters are model parameters for transistor models or passive
components. A typical device model set includes:
■
MOSFET models for all device sizes by using an automatic model selector.
■
RC wire models for polysilicon, metal1, and metal2 layers in the drawn
dimension. Models include temperature coefficients and fringe capacitance.
■
Single-diode and distributed-diode models for N+, P+, and well (includes
temperature, leakage, and capacitance based on the drawn dimension).
■
BJT models for parasitic bipolar transistors. You can also use these for any
special BJTs, such as a BiCMOS for ECL BJT process (includes current and
capacitance as a function of temperature).
■
Metal1 and metal2 transmission line models for long metal lines.
■
Models must accept elements. Sizes are based on a drawn dimension. If
you draw a cell at 2 µ dimension, and shrink it to 1 µ, the physical size is 0.9
µ. Τhe effective electrical size is 0.8 µ. Account for the four dimension levels:
•
drawn size
•
shrunken size
•
physical size
•
electrical size
Most simulator models scale directly from drawn to electrical size. HSPICE
MOS models support all four size levels as in Figure 77.
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Figure 77
Device Model from Drawn to Electrical Size
Drawn Size
Shrunken Size
2m
1m
LMLT
WMLT
XL
XW
Electrical Size
source
Physical Size
source
drain
drain
gate
gate
LD
WD
0.8 m
0.9 m
Monte Carlo Analysis
Monte Carlo analysis (HSPICE only; HSPICE RF does not support Monte
Carlo analysis) uses a random number generator to create the following types
of functions.
Functions
Gaussian Parameter Distribution
■
Relative variation—variation is a ratio of the average.
■
Absolute variation—adds variation to the average.
■
Bimodal–multiplies distribution to statistically reduce nominal parameters.
Uniform Parameter Distribution
■
Relative variation—variation is a ratio of the average.
■
Absolute variation—adds variation to the average.
■
Bimodal–multiplies distribution to statistically reduce nominal parameters.
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Random Limit Parameter Distribution
■
Absolute variation—adds variation to the average.
■
Monte Carlo analysis randomly selects the min or max variation.
The value of the MONTE analysis keyword determines how many times to
perform operating point, DC sweep, AC sweep, or transient analysis.
Monte Carlo Setup
To set up a Monte Carlo analysis, use the following HSPICE statements:
■
.PARAM statement—sets a model or element parameter to a Gaussian,
Uniform, or Limit function distribution.
■
.DC, .AC, or .TRAN analysis—enables MONTE.
■
.MEASURE statement—calculates the output mean, variance, sigma, and
standard deviation.
■
.MODEL statement—sets model parameters to a Gaussian, Uniform, or
Limit function distribution.
Select the type of analysis to run, such as operating point, DC sweep, AC
sweep, or TRAN sweep.
Operating Point
.DC MONTE=<firstrun = num1>
or
.DC MONTE=list <(> <num1:num2> <num3> <num5:num6>
+ <num7> <)>
DC Sweep
.DC vin 1 5 0.25 sweep MONTE=val <firstrun = num1>
or
.DC vin 1 5 0.25 sweep MONTE=list<(> <num1:num2> <num3>
+ <num5:num6> <num7> <)>
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AC Sweep
.AC dec 10 100 1meg sweep MONTE=val <firstrun = num1>
or
.AC dec 10 100 1meg sweep MONTE=list<(> <num1:num2>
+ <num3> <num5:num6> <num7> <)>
TRAN Sweep
.TRAN 1n 10n sweep MONTE=val <firstrun = num1>
or
.TRAN 1n 10n sweep MONTE=list<(> <num1:num2> <num3>
+ <num5:num6> <num7> <)>
The val value specifies the number of Monte Carlo iterations to perform. A
reasonable number is 30. The statistical significance of 30 iterations is quite
high. If the circuit operates correctly for all 30 iterations, there is a 99%
probability that over 80% of all possible component values operate correctly.
The relative error of a quantity, determined through Monte Carlo analysis, is
proportional to val-1/2.
The firstrun values specify the desired number of iterations. HSPICE runs from
num1 to num1+val-1. The number after firstrun can be a parameter. You can
write only one number after list. The colon represents "from ... to ...". Specifying
only one number makes HSPICE runs only a the one specified point.
Example 1
In this example, HSPICE runs from the 90th to 99th Monte Carlo iterations:
.tran 1n 10 sweep monte=10 firstrun=90
You can write more than one number after list. The colon represents "from ... to
...". Specifying only one number makes HSPICE run only at that single point.
Example 2
In this example, HSPICE begins running at the 10th iteration, then continues
from the 20th to the 30th, at the 40th, and finally from the 46th to 72nd Monte
Carlo iteration. The numbers after list can not be parameter.
.tran 1n 10n sweep monte=list(10 20:30 40 46:72)
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Monte Carlo Output
■
.MEASURE statements are the most convenient way to summarize the
results.
■
.PRINT statements generate tabular results, and print the values of all
Monte Carlo parameters.
■
.MCBRIEF determines the output types of the random parameters during
Monte Carlo analysis to improve output performance.
■
If one iteration is out of specification, you can obtain the component values
from the tabular listing. A detailed resimulation of that iteration might help
identify the problem.
■
.GRAPH generates a high-resolution plot for each iteration.
■
By contrast, AvanWaves superimposes all iterations as a single plot so you
can analyze each iteration individually.
.PARAM Distribution Function
This section describes how to use assign a .PARAM parameter in Monte Carlo
analysis. For a general description of the .PARAM statement, see the HSPICE
Command Reference.
You can assign a .PARAM parameter to the keywords of elements and models,
and assign a distribution function to each .PARAM parameter. HSPICE
recalculates the distribution function each time that and element or model
keyword uses a parameter. When you use this feature, Monte Carlo analysis
can use a parameterized schematic netlist without additional modifications.
Syntax
.PARAM xx=UNIF(nominal_val, rel_variation
+ <, multiplier>)
.PARAM xx=AUNIF(nominal_val, abs_variation <,
+ multiplier>)
.PARAM xx=GAUSS(nominal_val, rel_variation, sigma <,
+ multiplier>)
.PARAM xx=AGAUSS(nominal_val, abs_variation, sigma <,
+ multiplier>)
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.PARAM xx=LIMIT(nominal_val, abs_variation)
Parameter
Description
xx
Distribution function calculates the value of this parameter.
UNIF
Uniform distribution function by using relative variation.
AUNIF
Uniform distribution function by using absolute variation.
GAUSS
Gaussian distribution function by using relative variation.
AGAUSS
Gaussian distribution function by using absolute variation
LIMIT
Random-limit distribution function by using absolute variation.
Adds +/- abs_variation to nominal_val based on whether the
random outcome of a -1 to 1 distribution is greater than or less
than 0.
nominal_val
Nominal value in Monte Carlo analysis and default value in all
other analyses.
abs_variation
AUNIF and AGAUSS vary the nominal_val by +/abs_variation.
rel_variation
UNIF and GAUSS vary the nominal_val by +/- (nominal_val ⋅
rel_variation).
sigma
Specifies abs_variation or rel_variation at the sigma level. For
example, if sigma=3, then the standard deviation is
abs_variation divided by 3.
multiplier
If you do not specify a multiplier, the default is 1. HSPICE
recalculates many times and saves the largest deviation. The
resulting parameter value might be greater than or less than
nominal_val. The resulting distribution is bimodal.
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Example 1
In this example, each R has an unique variation.
.param mc_var = agauss(0,1,3)
.param val = '1000*(1+mc_var)'
v_vin vin 0 dc=1 ac=.1
r1 vin 0 '1000*(1+mc_var)'
r2 vin 0 '1000*(1+mc_var)'
$ +/- 20% swing
Example 2
In this example, each R has an identical variation.
.param mc_var = agauss(0,1,3)
.param val = '1+mc_var'
v_vin vin 0 dc=1 ac=.1
r1 vin 0 '1000*val'
r2 vin 0 '1000*val'
Figure 78
$ +/- 20% swing
Monte Carlo Distribution
Gaussian Distribution
Uniform Distribution
Population
Population
Abs
variation
Abs
variation
3 Sigma
Nom_value
Nom_value
Rel_variation=Abs_variation/Nom_value
Monte Carlo Parameter Distribution
Each time you use a parameter, Monte Carlo calculates a new random variable.
494
■
If you do not specify a Monte Carlo distribution, then HSPICE assumes the
nominal value.
■
If you specify a Monte Carlo distribution for only one analysis, HSPICE uses
the nominal value for all other analyses.
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Monte Carlo Analysis
You can assign a Monte Carlo distribution to all elements that share a common
model. The actual element value varies according to the element distribution. If
you assign a Monte Carlo distribution to a model keyword, then all elements
that share the model, use the same keyword value. You can use this feature to
create double element and model distributions.
For example, the MOSFET channel length varies from transistor to transistor by
a small amount that corresponds to the die distribution. The die distribution is
responsible for offset voltages in operational amplifiers, and for the tendency of
flip-flops to settle into random states. However, all transistors on a die site vary
according to the wafer or fabrication run distribution. This value is much larger
than the die distribution, but affects all transistors the same way. You can
specify the wafer distribution in the MOSFET model to set the speed and power
dissipation characteristics.
Monte Carlo Examples
HSPICE supports Monte Carlo analysis; HSPICE RF does not.
Gaussian, Uniform, and Limit Functions
You can find the sample netlist for this example in the following directory:
$installdir/demo/hspice/apps/mont1.sp
Figure 79
119.182
Uniform Functions
MONT1.SP TEST OF MONTE CARLO, GAUSSIAN, UNIFORM, AND LIMIT FUNCTIONS
May 15 2003 11:41:23
MONT1_SV0
RUNIF_1
110.0
VOLT [LIN]
100.0
90.0
80.1384
120.0
MONT1_SV0
RUNIF_10
110.0
100.0
90.0
80.0402
1.0
10.0
20.0
30.0
40.0
50.0
60.0
MONTE CARLO [LIN]
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Figure 80
Gaussian Functions
MONT1.SP TEST OF MONTE CARLO, GAUSSIAN, UNIFORM, AND LIMIT FUNCTIONS
May 15 2003 11:41:23
MONT1_SV
RGAUSS_1
115.0
110.0
105.0
100.0
VOLT [LIN]
95.0
90.0
118.375
MONT1_SV
RGAUSS_1
110.0
100.0
90.0
80.9998
1.0
10.0
20.0
30.0
40.0
50.0
60.0
MONTE CARLO [LIN]
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Figure 81
Limit Functions
MONT1.SP TEST OF MONTE CARLO, GAUSSIAN, UNIFORM, AND LIMIT FUNCTIONS
May 15 2003 11:41:23
MONT1.SV0
120.0
LIMIT
115.0
110.0
VOLT [LIN]
105.0
100.0
95.0
90.0
85.0
80.0
1.0
10.0
20.0
30.0
40.0
50.0
60.0
MONTE CARLO [LIN]
Major and Minor Distribution
In MOS IC processes, manufacturing tolerance parameters have both a major
and a minor statistical distribution.
■
The major distribution is the wafer-to-wafer and run-to-run variation. It
determines electrical yield.
■
The minor distribution is the transistor-to-transistor process variation. It is
responsible for critical second-order effects, such as amplifier offset voltage
and flip-flop preference.
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Figure 82
Major and Minor Distribution of Manufacturing Variations
major distribution
minor distribution
pop.#
XL
(polysilicon linewidth variation)
The following example is a Monte Carlo analysis of a DC sweep in HSPICE.
HSPICE supports Monte Carlo analysis; HSPICE RF does not. Monte Carlo
sweeps the VDD supply voltage from 4.5 volts to 5.5 volts.
You can find the sample netlist for this example in the following directory:
$installdir/demo/hspice/apps/mondc_a.sp
■
The M1 through M4 transistors form two inverters.
■
The nominal value of the LENGTH parameter sets the channel lengths for
the MOSFETs, which are set to 1u in this example.
■
All transistors are on the same integrated circuit die. The LEFF parameter
specifies the distribution—for example, a ±5% distribution in channel length
variation at the ±3-sigma level.
■
Each MOSFET has an independent random Gaussian value.
The PHOTO parameter controls the difference between the physical gate
length and the drawn gate length. Because both n-channel and p-channel
transistors use the same layer for the gates, Monte Carlo analysis sets
XPHOTO distribution to the PHOTO local parameter.
XPHOTO controls PHOTO lithography for both NMOS and PMOS devices,
which is consistent with the physics of manufacturing.
RC Time Constant
This simple example shows uniform distribution for resistance and capacitance.
It also shows the resulting transient waveforms for 10 different random values.
You can find the sample netlist for this example in the following directory:
$installdir/demo/hspice/apps/rc_monte.sp
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Figure 83
Monte Carlo Analysis of RC Time Constant
*FILE: NOM1.SP WITH UNIFORM DISTRIBUTION
May 15 2003 12:38:49
992.750N
MONT1.SV0
1
900.0N
VOLT [LIN]
800.0N
700.0N
600.0N
10
500.0N
9
8
400.0N
300.0N
0
200.0N
400.0N
600.0N
800.0N
1.0
7
5
26
3
1
TIME [LIN]
Switched Capacitor Filter Design
Capacitors used in switched-capacitor filters consist of parallel connections of a
basic cell. Use Monte Carlo techniques in HSPICE to estimate the variation in
total capacitance. The capacitance calculation uses two distributions:
■
Minor (element) distribution of cell capacitance from cell-to-cell on a single
die.
■
Major (model) distribution of the capacitance from wafer-to-wafer or from
manufacturing run-to-run.
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Figure 84
Monte Carlo Distribution
cap-to-cap
(element)
C1a
C1b
C1a
C1b
C1c
C1d
C1c
C1d
run-to-run
(model)
You can approach this problem from physical or electrical levels.
■
The physical level relies on physical distributions, such as oxide thickness
and polysilicon line width control.
■
The electrical level relies on actual capacitor measurements.
Physical Approach
1. Oxide thickness control is excellent for small areas on a single wafer.
Therefore, you can use a local variation in polysilicon to control the variation
in capacitance for adjacent cells.
2. Next, define a local poly line-width variation and a global (model-level) poly
line-width variation. In this example:
•
The local polysilicon linewidth control for a line 10 m wide, manufactured
with process A, is ±0.02 m for a 1-sigma distribution.
•
The global (model level) polysilicon line-width control is much wider; use
0.1 m for this example.
3. The global oxide thickness is 200 angstroms with a ±5 angstrom variation at
1 sigma.
4. The cap element is square with local poly variation in both directions.
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5. The cap model has two distributions:
•
poly line-width distribution
•
oxide thickness distribution.
The effective length is:
Leff = Ldrawn - 2 ⋅ DEL
The model poly distribution is half the physical per-side values:
C1a 1 0 CMOD W=ELPOLY L=ELPOLY
C1b 1 0 CMOD W=ELPOLY L=ELPOLY
C1C 1 0 CMOD W=ELPOLY L=ELPOLY
C1D 1 0 CMOD W=ELPOLY L=ELPOLY
$ 10U POLYWIDTH,0.05U=1SIGMA
$ CAP MODEL USES 2*MODPOLY .05u= 1 sigma
$ 5angstrom oxide thickness AT 1SIGMA
.PARAM ELPOLY=AGAUSS(10U,0.02U,1)
+ MODPOLY=AGAUSS(0,.05U,1)
+ POLYCAP=AGAUSS(200e-10,5e-10,1)
.MODEL CMOD C THICK=POLYCAP DEL=MODPOLY
Electrical Approach
The electrical approach assumes no physical interpretation, but requires a local
(element) distribution and a global (model) distribution. In this example:
■
You can match the capacitors to ±1% for the 2-sigma population.
■
The process can maintain a ±10% variation from run to run for a 2-sigma
distribution.
C1a 1 0 CMOD SCALE=ELCAP
C1b 1 0 CMOD SCALE=ELCAP
C1C 1 0 CMOD SCALE=ELCAP
C1D 1 0 CMOD SCALE=ELCAP
.PARAM ELCAP=Gauss(1,.01,2) $ 1% at 2 sigma
+ MODCAP=Gauss(.25p,.1,2) $10% at 2 sigma
.MODEL CMOD C CAP=MODCAP
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Worst Case and Monte Carlo Sweep Example
Worst Case and Monte Carlo Sweep Example
HSPICE supports Monte Carlo and worst-case analysis; HSPICE RF does not.
The following example measures the delay of a pair of inverters.
■
An inverter buffers the input.
■
Another inverter loads the output.
The model is prepared according to the scheme described in the previous
sections:
■
The first .TRAN analysis statement sweeps from the worst-case 3-sigma
slow to 3-sigma fast.
■
The second .TRAN performs 100 Monte Carlo sweeps.
HSPICE Input File
The HSPICE input file can contain an analysis setup section. To accelerate the
simulation, .OPTION AUTOSTOP automatically stops the simulation when
the .MEASURE statements achieve their target values.
$ inv.sp sweep mosfet -3 sigma to +3 sigma, use measure output
.option nopage nomod post autostop
.tran 20p 1.0n
sweep sigma -3 3 .5
.option co=132
.probe tran v(in) v(1) v(2) v(3) v(4)
.param vref=2.5
.meas m_delay trig v(2) val=vref fall=1
+ targ v(4) val=vref fall=1
.meas m_over max v(2,1)
.meas m_under min v(3,0)
.param sigma=0
.global 1
vcc 1 0 5.0
vin in 0 pwl 0,0 0.2n,5
x1 in 2 inv
x2 2 3 inv
x3 3 4 inv
x4 4 out inv
.macro inv in out
mn out in 0 0 nch w=10u l=1u
mp out in 1 1 pch w=10u l=1u
.eom
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.inc gen28.inc
.end
Transient Sigma Sweep Results
The plot in Figure 85 shows the family of transient analysis curves for the
transient sweep of the sigma parameter from -3 to +3. HSPICE then
algebraically couples sigma into the skew parameters. The resulting
parameters modify the actual NMOS and PMOS models.
Figure 85
Sweep of Skew Parameters from -3 Sigma to +3 Sigma
MONTE CARLO YIELD ESTIMATION
INV.TR1
2
out
5.0
4.50
4.0
VOLT [LIN]
3.50
3.0
2.50
L
2.0
1.50
1.0
500.0N
37.6334N
L
0
100.0P
200.0P
300.0P
TIME [LIN]
400.0P
500.0P
550.0P
To view the transient curves, plot the .MEASURE output file. The plot in
Figure 86 shows the measured pair delay, and the total dissipative power,
against the SIGMA parameter.
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Worst Case and Monte Carlo Sweep Example
Figure 86
Sweep MOS Inverter, Pair Delay and Power: -3 Sigma to 3 Sigma
* INV.SP SWEEP MOS INVERTER -3 SIGMA TO +3 SIGMA
INV.MT0
M_DELAY
350.0P
PARAMETER [LIN]
300.0P
250.0P
200.0P
INV.MT0
M_POWER
158.445P
8.9454M
8.0M
7.0M
6.0M
5.4135M
-3.0
-2.0
-1.0
0
SIGMA [LIN]
1.0
2.0
3.0
Monte Carlo Results
This section evaluates the output of the Monte Carlo analysis in HSPICE.
HSPICE supports Monte Carlo analysis; HSPICE RF does not. The plot in
Figure 87 is a quality-control step, which plots TOX against XL (polysilicon
critical dimension). Synopsys graphing software returned the cloud of points
based on:
■
Setting XL as the X-axis independent variable.
■
Plotting TOX with a symbol frequency of 1.
These settings plot points without connecting lines. The resulting graph
demonstrates that the TOX model parameter is randomly independent of XL.
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Worst Case and Monte Carlo Sweep Example
Figure 87
Scatter Plot, XL and TOX
PARAM [LIN]
SCATTER PLOT DEMONSTRATING INDEPENDENCE OF XL AND TOX
INV1.MT0
[email protected]
240.0
220.0
200.0
180.0
160.0
140.0
120.0
100.0
80.0
60.0
40.0
20.0
0
-500.0N -400.0N
-200.0N
0
200.0N
400.0N 500.0N
XL0POLYYC0 [LIN]
The next graph (see Figure 88) is a standard scatter plot showing the
measured delay for the inverter pair against the Monte Carlo index number. If a
particular result looks interesting—for example, if the simulation 68 (monte
carlo index = 68) produces the smallest delay—then you can read the output
listing file, and obtain the Monte Carlo parameters for that simulation.
*** monte carlo index = 68 ***
MONTE CARLO PARAMETER DEFINITIONS
polycd: xl = -1.6245E-07
nactcd: xwn = 3.4997E-08
pactcd: xwp = 3.6255E-08
toxcd: tox = 191.0
vtoncd: delvton = -2.2821E-02
vtopcd: delvtop = 4.1776E-02
rshncd: rshn = 45.16
rshpcd: rshp = 166.2
m_delay = 1.7946E-10 targ= 3.4746E-10 trig= 1.6799E-10
m_power = 7.7781E-03 from= 0.0000E+00 to= 1.7946E-10
In the preceding listing, the m_delay value of 1.79e-10 seconds is the fastest
pair delay. You can also examine the Monte Carlo parameters.
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Worst Case and Monte Carlo Sweep Example
Figure 88
Scatter Plot of Inverter Pair Delay
SCATTER PLOT OF INVERTER PAIR DELAY
INV1.MT0
M_DELAY
350.0P
300.0P
250.0P
200.0P
150.0P
100.0P
50.0P
0
1.0
20.0
40.0
60.0
80.0
100.0
INDEX (LIN)
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Worst Case and Monte Carlo Sweep Example
Plotting against the Monte Carlo index number does not help to center the
design. To center the design:
1. Graph the various process parameters against the pair delay.
This graph determines the most sensitive process variables.
2. Select the pair delay as the X-axis independent variable.
3. Set the symbol frequency to 1 to obtain the scatter plot.
Figure 89 plots the expected sensitivity of the output pair delay to channel
length variation (polysilicon variation).
Figure 89
Sensitivity of Delay with Poly CD (XL)
SCATTER PLOT OF INVERTER PAIR DELAY
INV1.MT0
M_DELAY
350.0P
300.0P
250.0P
200.0P
150.0P
100.0P
50.0P
0
1.0
20.0
40.0
60.0
80.0
100.0
INDEX (LIN)
The next plot shows the TOX parameter against the pair delay (Figure 90). The
scatter plot does not have a clear tilt, because TOX is a secondary process
parameter compared to XL. To explore this in more detail, set the XL skew
parameter to a constant and run a simulation.
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Worst Case and Monte Carlo Sweep Example
Figure 90
Sensitivity of Delay with TOX
SENSITIVITY OF PAIR DELAY WITH RESPECT TO TOX
INV1.MT0
[email protected]
240.0
PARAM [LIN]
220.0
200.0
180.0
160.0
140.0
120.0
100.0
100.0P
150.0P
200.0P
250.0P
300.0P
350.0P
M_DELAY (LIN)
The plot in Figure 91 overlays a 3-sigma, worst-case corners response on a
100-point Monte Carlo analysis. The actual (Monte Carlo) distribution for
power/delay is very different from the +3 sigma to -3 sigma plot.
■
This example simulated the worst case in 0.5 sigma steps.
■
The actual response is closer to ± 1.5 sigma instead of ± 3 sigma.
■
This produces a predicted delay variation of 100 ps instead of 200 ps.
Therefore, the advantage of using Monte Carlo over traditional 3-sigma, worstcase corners is a 100% improvement in accuracy of simulated-to-actual
distribution. This shows how the worst-case procedure is overly pessimistic.
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Worst Case and Monte Carlo Sweep Example
Figure 91
Superimposing Sigma Sweep Over Monte Carlo
SUPERIMPOSE +3 SIGMA TO -3 SIGMA SWEEP OVER MONTE CARLO
INV1.MT0
M_POWER
INV.MT0
M_POWER
10.0M
9.50M
+3 sigma
PARAM [LIN]
9.0M
8.50M
8.0M
7.50M
7.0M
6.50M
-3 sigma
6.0M
5.50M
5.0M
100.0P.0
150.0P
200.0P
250.0P
M_DELAY (LIN)
300.0P
350.0P
400.0P
Figure 92 superimposes the assumed part grades from marketing studies onto
the Monte Carlo plot. This example uses a 250 ps delay and 7.5 mW power
dissipation to determine the four binning grades. A manual count shows:
■
Bin1 - 13%
■
Bin2 - 37%
■
Bin3 - 27%
■
Bin4 - 23%
If this circuit is representative of the entire chip, then the present yield should
be 13% for the premium Bin 1 parts, assuming variations in design and
process.
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Optimization
Figure 92
Speed/Power Yield Estimation
MONTE CARLO YIELD ESTIMATION
9.0M
8.750M
PARAM [LIN]
8.50M
8.250M
INv1.MT0
M_POWER
Bin 2 - 37 sims
Bin 4 - 23 sims
8.0M
7.750M
7.50M
7.250M
7.0M
6.750M
6.50M
6.250M
6.0M
150.0P
Bin 1 - 13 sims
200.0P
250.0P
M_DELAY (LIN)
Bin3 - 27 sims
300.0P
350.0P
Optimization
Optimization automatically generates model parameters and component
values from a set of electrical specifications or measured data. When you
define an optimization program and a circuit topology, HSPICE automatically
selects the design components and model parameters to meet your DC, AC,
and transient electrical specifications.
The circuit-result targets are part of the .MEASURE command structure and you
use a .MODEL statement to set up the optimization.
Note: HSPICE uses post-processing output to compute the .MEASURE
statements. If you set INTERP=1 to reduce the post-processing output, the
measurement results might contain interpolation errors. See the HSPICE
Command Reference manual for more information about these options.
HSPICE employs an incremental optimization technique. This technique solves
the DC parameters first, then the AC parameters, and finally the transient
parameters. A set of optimizer measurement functions not only makes
transistor optimization easy, but significantly improves cell and circuit
optimization.
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Optimization
To perform optimization, create an input netlist file that specifies:
■
Minimum and maximum parameter and component limits.
■
Variable parameters and components.
■
An initial estimate of the selected parameter and component values.
■
Circuit performance goals or a model-versus-data error function.
If you provide the input netlist file, optimization specifications, component limits,
and initial guess, then the optimizer reiterates the circuit simulation until it either
meets the target electrical specification, or finds an optimized solution.
For improved optimization, reduced simulation time, and increased likelihood of
a convergent solution, the initial estimate of component values should produce
a circuit whose specifications are near those of the original target. This reduces
the number of times the optimizer reselects component values and resimulates
the circuit.
Optimization Control
How much time an optimization requires before it completes depends on:
■
Number of iterations allowed.
■
Relative input tolerance.
■
Output tolerance.
■
Gradient tolerance.
The default values are satisfactory for most applications. Generally, 10 to 30
iterations are sufficient to obtain accurate optimizations.
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Optimization
Simulation Accuracy
For optimization, set the simulator with tighter convergence options than
normal. The following are suggested options:
For DC MOS model optimizations:
absmos=1e-8
relmos=1e-5
relv=1e-4
For DC JFET, BJT, and diode model optimizations:
absi=1e-10
reli=1e-5
relv=1e-4
For transient optimizations:
relv=1e-4
relvar=1e-2
Curve Fit Optimization
Use optimization to curve-fit DC, AC, or transient data.
1. Use the .DATA statement to store the numeric data for curves in the data
file as in-line data.
2. Use the .PARAM xxx=OPTxxx statement to specify the variable circuit
components and the parameter values for the netlist.
The optimization analysis statements use the DATA= keyword to call the inline data.
3. Use the .MEASURE statement to compare the simulation result to the values
in the data file
In this statement, use the ERR1 keyword to control the comparison.
If the calculated value is not within the error tolerances specified in the
optimization model, HSPICE selects a new set of component values. HSPICE
then simulates the circuit again and repeats this process until it obtains the
closest fit to the curve or until the set of error tolerances is satisfied.
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Optimization
Goal Optimization
Goal optimization differs from curve-fit optimization, because it usually
optimizes only a particular electrical specification, such as rise time or power
dissipation.
1. To specify goal optimizations, use the GOAL keyword.
2. In the .MEASURE statement, select a relational operator where GOAL is the
target electrical specification to measure.
For example, you can choose a relational operator in multiple-constraint
optimizations when the absolute accuracy of some criteria is less important
than for others.
Timing Analysis
To analyze circuit timing violation, HSPICE uses a binary search algorithm.
This algorithm generate a set of operational parameters, which produce a
failure in the required behavior of the circuit. When a circuit timing failure
occurs, you can identify a timing constraint, which can lead to a design
guideline. Typical types of timing constraint violations include:
■
Data setup time before a clock.
■
Data hold time after a clock.
■
Minimum pulse width required to allow a signal to propagate to the output.
■
Maximum toggle frequency of the component(s).
Bisection Optimization finds the value of an input variable (target value)
associated with a goal value for an output variable. To relate them, you can use
various types of input and output variables, such as voltage, current, delay
time, or gain, and a transfer function.
You can use the bisection feature in either a pass-fail mode or a bisection
mode. In each case, the process is largely the same.
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Optimization
Optimization
Optimization requires several statements:
■
.MODEL modname OPT ...
■
.PARAM parameter=OPTxxx (init, min, max)
Use .PARAM statements to define initial, lower, and upper bounds.
■
A .DC, .AC, or .TRAN analysis statement, with:
MODEL=modname
OPTIMIZE=OPTxxx
RESULTS=measurename
Use the .PRINT, .PLOT, and .GRAPH output statements, with
the .DC, .AC, or .TRAN analysis statements.
Only use an analysis statement with the OPTIMIZE keyword for
optimization. To generate output for the optimized circuit, specify another
analysis statement (.DC, .AC, or .TRAN), and the output statements.
■
.MEASURE measurename ... <GOAL = | < | > val>
Include a space on either side of the relational operator:
=
<
>
For a description of the types of .MEASURE statements that you can use in
optimization, see Chapter 7, “Simulation Output.”
The proper specification order is:
1. Analysis statement with OPTIMIZE.
2. .MEASURE statements specifying optimization goals or error functions.
3. Ordinary analysis statement.
4. Output statements.
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Optimization Examples
Optimizing Analysis (.DC, .TRAN, .AC)
The following syntax optimizes HSPICE simulation for a DC, AC, and Transient
analysis.
.DC <DATA=filename> SWEEP OPTIMIZE=OPTxxx
+ RESULTS=ierr1 ... ierrn MODEL=optmod
.AC <DATA=filename> SWEEP OPTIMIZE=OPTxxx
+ RESULTS=ierr1 ... ierrn MODEL=optmod
.TRAN <DATA=filename> SWEEP OPTIMIZE=OPTxxx
+ RESULTS=ierr1 ... ierrn MODEL=optmod
Parameter
Description
DATA
Specifies an in-line file of parameter data to use in optimization.
MODEL
The optimization reference name, which you also specify in the .MODEL
optimization statement.
OPTIMIZE
Indicates that the analysis is for optimization. Specifies the parameter
reference name used in the .PARAM optimization statement. In
a .PARAM optimization statements, if OPTIMIZE selects the parameter
reference name, then the associated parameters vary during an
optimization analysis.
RESULTS
The measurement reference name. You also specify this name in
the .MEASURE optimization statement. RESULTS passes the analysis
data to the .MEASURE optimization statement.
Optimization Examples
This section contains examples of HSPICE optimizations (for HSPICE RF
optimization, see “Optimization” in the HSPICE RF Manual):
■
MOS Level 3 Model DC Optimization
■
MOS Level 13 Model DC Optimization
■
RC Network Optimization
■
Optimizing CMOS Tristate Buffer
■
BJT S Parameters Optimization
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Optimization Examples
■
BJT Model DC Optimization
■
Optimizing GaAsFET Model DC
■
Optimizing MOS Op-amp
MOS Level 3 Model DC Optimization
This example shows an optimization of I-V data to a Level 3 MOS model. The
data consists of gate curves (ids versus vgs) and drain curves (ids versus vds).
This example optimizes the Level 3 parameters:
■
VTO
■
GAMMA
■
UO
■
VMAX
■
THETA
■
KAPPA
After optimization, HSPICE compares the model to the data for the gate, and
then to the drain curves. .OPTION POST generates AvanWaves files for
comparing the model to the data.
Input Netlist File for Level 3 Model DC Optimization
You can find the sample netlist for this example in the following directory:
$installdir/demo/hspice/devopt/ml3opt.sp
The HSPICE input netlist shows:
516
■
Using .OPTION to tighten tolerances, which increases the accuracy of the
simulation. Use this method for I-V optimization.
■
.MODEL optmod OPT itropt=30 limits the number of iterations to 30.
■
The circuit is one transistor. The VDS, VGS, and VBS parameter names,
match names used in the data statements.
■
.PARAM statements specify XL, XW, TOX, and RSH process variation
parameters, as constants. The device characterizes these measured
parameters.
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Optimization Examples
■
The model references parameters. In GAMMA= GAMMA, the left side is a
Level 3 model parameter name; the right side is a .PARAM parameter name.
■
The long .PARAM statement specifies initial, min and max values for the
optimized parameters. Optimization initializes UO at 480, and maintains it
within the range 400 to 1000.
■
The first .DC statement indicates that:
■
•
Data is in the in-line .DATA all block, which contains merged gate and
drain curve data.
•
Parameters that you declared as OPT1 (in this example, all optimized
parameters) are optimized.
•
The COMP1 error function matches the name of a .MEASURE
statement.
•
The OPTMOD model sets the iteration limit.
The .MEASURE statement specifies least-squares relative error. HSPICE
divides the difference between data par(ids) and model i(m1) by the larger
of:
•
the absolute value of par(ids), or
•
minval=10e-6
If you use minval, low current data does not dominate the error.
■
Use the remaining .DC and .PRINT statements for print-back after
optimization. You can place them anywhere in the netlist input file, because
parsing the file correctly assigns them.
■
The .PARAM VDS=0 VGS=0 VBS=0 IDS=0 statements declare these data
column names as parameters.
The .DATA statements contain data for IDS versus VDS, VGS, and VBS.
Select data that matches the model parameters to optimize.
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Optimization Examples
Example
To optimize GAMMA, use data with back bias (VBS= -2 in this case). To
optimize KAPPA, the saturation region must contain data. In this example, the
all data set contains:
■
Gate curves: vds=0.1 vbs=0,-2 vgs=1 to 5 in steps of 0.25.
■
Drain curves: vbs=0 vgs=2,3,4,5 vds=0.25 to 5 in steps of 0.25.
Figure 93 shows the results.
Figure 93
Level 3 MOSFET Optimization
$LEVEL 8 MOSFET OPTIMIZATION
APRIL 22, 2004 4:58:09
OPTLEVELS.90
IM
ANP [LIN]
381.270U
300.0U
IO
200.0U
100.0U
0
1.0
1.50
2.0
2.5
3.0
YOS [LIN]
3.5
4.0
4.50
5.0
OPTLEVELS.90
IM
ANP [LIN]
5.0M
4.0M
IO
3.0M
2.0M
1.0M
250.0N
1.0
2.0
3.0
4.0
5.0
YOS [LIN]
MOS Level 13 Model DC Optimization
This example shows I-V data optimization to a Level 13 MOS model. The data
consists of gate curves (ids versus vgs) and drain curves (ids versus vds). This
example demonstrates two-stage optimization.
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Optimization Examples
1. HSPICE optimizes the vfb0, k1, muz, x2m, and u00 Level 13 parameters to
the gate data.
2. HSPICE optimizes the MUS, X3MS, and U1 Level 13 parameters, and the
ALPHA impact ionization parameter to the drain data.
After optimization, HSPICE compares the model to the data. The POST option
generates AvanWaves files to compare the model to the data. Figure 94 on
page 519 shows the results.
DC Optimization Input Netlist File for Level 13 Model
You can find the sample netlist for this example in the following directory:
$installdir/demo/hspice/mos/ml13opt.sp
Figure 94
Level 13 MOSFET Optimization
ANPORT.SP MOS OPERATIONAL AMPLIFIER OPTIMIZATION
APRIL 22, 2003 5:21:26
MLLSOPT.SV0
IM
ANP [LIN]
300.0U
IO
200.0U
100.0U
0
1.0
1.50
2.0
2.5
3.0
YOS [LIN]
3.5
4.0
4.50
5.0
MLLSOPT.SV1
IM
ANP [LIN]
4.9787M
4.0M
IO
3.0M
2.0M
1.0M
250.0M
1.0
2.0
YOS [LIN]
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Optimization Examples
RC Network Optimization
The following example optimizes the power dissipation and time constant for an
RC network. The circuit is a parallel resistor and capacitor. Design targets are:
■
1 s time constant.
■
50 mW rms power dissipation through the resistor.
The HSPICE strategy is:
■
RC1 .MEASURE calculates the RC time constant, where the GOAL
of .3679 V corresponds to 1 s time constant e-rc.
■
RC2 .MEASURE calculates the rms power, where the GOAL is 50 mW.
■
OPTrc identifies RX and CX as optimization parameters, and sets their
starting, minimum, and maximum values.
Network optimization uses these HSPICE features:
■
Measure voltages and report times that are subject to a goal.
■
Measure device power dissipation subject to a goal.
■
Measure statements replace the tabular or plot output.
■
Parameters used as element values.
■
Parameter optimizing function.
■
Transient analysis with SWEEP optimizing.
Example
You can find the sample netlist for this example in the following directory:
$installdir/demo/hspice/ciropt/rcopt.sp
Optimization Results
RESIDUAL SUM OF SQUARES
NORM OF THE GRADIENT
MARQUARDT SCALING PARAMETER
NO. OF FUNCTION EVALUATIONS
NO. OF ITERATIONS = 9
520
=
=
=
=
4.291583E-16
5.083346E-04
2.297208E-04
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Optimization Examples
Residual Sum of Squares
The residual sum of squares is a measure of the total error. The smaller this
value is the more accurate the optimization results are.
ne
residual sum of squares =
∑ Ei
2
i=1
In this equation, E is the error function, and ne is the number of error functions.
Norm of the Gradient
The norm of the gradient is another measure of the total error. The smaller this
value is the more accurate the optimization results are. The following equations
calculates the G gradient:
ne
Gj =
∑ E i ⋅ ( ∆E i ⁄ ∆P j )
i=1
np
norm of the gradient = 2 ⋅
∑ Gj
2
i=1
In this equation, P is the parameter, and np is the number of parameters to
optimize.
Marquardt Scaling Parameter
The Levenburg-Marquardt algorithm uses this parameter to find the actual
solution for the optimizing parameters. The search direction is a combination of
the Steepest Descent method and the Gauss-Newton method.
The optimizer initially uses the Steepest Descent method as the fastest
approach to the solution. It then uses the Gauss-Newton method to find the
solution. During this process, the Marquardt Scaling Parameter becomes very
small, but starts to increase again if the solution starts to deviate. If this
happens, the optimizer chooses between the two methods to work toward the
solution again.
If the optimizer does not attain the optimal solution, it prints both an error
message, and a large Marquardt Scaling Parameter value.
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Number of Function Evaluations
This is the number of analyses (for example, finite difference or central
difference) needed to find a minimum of the function.
Number of Iterations
This is the number of iterations needed to find the optimized or actual solution.
Optimized Parameters OPTRC
.param rx =
7.4823 $
.param cx = 133.9934m $
Figure 95
55.6965 5.7945m
44.3035 5.1872m
Power Dissipation and Time Constant (VOLT) RCOPT.TR0 =
Before Optimization, RCOPT.TR1 = Optimized Result
*FILE: RCOPT.SP OPTIMIZE THE POWER DISSIPATION AND TIME CONSTANT
APRIL 22, 2004 5:38:12
998.587N
RCOPT.TR0
1
900.0N
RCOPT.TR1
1
800.0N
VOLT [LIN]
700.0N
600.0N
500.0N
400.0N
300.0N
200.0N
100.0N
929.90U
522
0
200.0M
400.0M
600.0M
TIME [LIN]
800.0M
1.0
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Optimization Examples
Figure 96
Power Dissipation and Time Constant (WATT) RCOPT.TR0 =
Before Optimization, RCOPT.TR1 = Optimized Result
*FILE: RCOPT.SP OPTIMIZE THE POWER DISSIPATION AND TIME CONTSTANT
APRIL 22, 2004 5:38:12
RCOPT.TR0
PIR1
1.80
RCOPT.TR1
PIR1
1.60
MATT [LIN]
1.40
1.20
1.0
800.0M
600.0M
400.0M
200.0M
0
0
200.0N
400.0N
600.0N
TIME [LIN]
800.0N
1.0
Optimizing CMOS Tristate Buffer
The example circuit is an inverting CMOS tristate buffer. The design targets
are:
1. Rising edge delay of 5 ns (input 50% voltage to output 50% voltage).
2. Falling edge delay of 5 ns (input 50% voltage to output 50% voltage).
3. RMS power dissipation should be as low as possible.
4. Output load consists of:
•
pad capacitance
•
leadframe inductance
•
50 pF capacitive load
The HSPICE strategy is:
■
Simultaneously optimize both the rising and falling delay buffer.
■
Set up the internal power supplies, and the tristate enable as global nodes.
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Optimization Examples
■
Optimize all device widths except:
•
Initial inverter (assumed to be standard size).
•
Tristate inverter and part of the tristate control (optimizing is not
sensitive to this path).
■
Perform an initial transient analysis for plotting purposes. Then optimize and
perform a final transient analysis for plotting.
■
To use a weighted RMS power measure, specify unrealistically-low power
goals. Then use MINVAL to attenuate the error.
Input Netlist File to Optimize a CMOS Tristate Buffer
You can find the sample netlist for this example in the following directory:
$installdir/demo/hspice/apps/trist_buf_opt.sp
Figure 97
Tristate Buffer Optimization Circuit
g
VCC
p
VCC
VCC
MP1
VCC
VCC
VCC
MP3
MP2
DATAN
BUS
MN1
Cbus
MN2
PEN
MP11
MP10
NENN
MP5
MN3
MN12
MP12
VCC
PENN
MP4
Cext
Cpad
MN10
MN11
NEN
MN5
MN4
ENB
VCC
MP13
ENBN
Cenb
524
Cenbn
MN13
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Optimization Examples
Figure 98
Tristate Input/Output Optimization ACIC2B.TR0 = Before
Optimization, ACIC2B.TR1 = Optimized Result
* TRI-STATE I/O OPTIMIZATION
APRIL 22, 2003 5:52:46
5.0
ASIC2.TR1
OUT
4.50
OUTBAR
ASIC2.TR0
OUT
4.0
OUTBAR
VOLT [LIN]
3.50
3.0
2.50
2.0
1.50
1.0
500.0N
0
0
2.0N
4.0N
6.0N
8.0N
TIME [LIN]
10.0N
12.0N
14.0N
15.0N
BJT S Parameters Optimization
The following example optimizes the S parameters to match those specified for
a set of measurements. The .DATA MEASURED in-line data statement contains
these measured S parameters as a function of frequency. The model
parameters of the microwave transistor (LBB, LCC, LEE, TF, CBE, CBC, RB,
RE, RC, and IS) vary. As a result, the measured S parameters (in the .DATA
statement) match the calculated S parameters from the simulation results.
This optimization uses a 2n6604 microwave transistor, and an equivalent circuit
that consists of a BJT, with parasitic resistances and inductances. The BJT is
biased at a 10 mA collector current (0.1 mA base current at DC bias and
bf=100).
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Key HSPICE Features Used
■
.NET command to simulate network analyzer action.
■
.AC optimization.
■
Optimized element and model parameters.
■
Optimizing, compares measured S Parameters to calculated parameters.
■
S Parameters used in magnitude and phase (real and imaginary available).
■
Weighting of data-driven frequency versus S Parameter table. Used for the
phase domain.
Input Netlist File for Optimizing BJT S Parameters
* BJTOPT.SP BJT S PARAMETER OPTIMIZATION
.OPTION ACCT NOMOD POST=2
BJT Equivalent Circuit Input
Use the bjtopt.sp netlist file located in your $installdir/demo/hspice/devopt
directory for optimizing BJT S Parameters.
Optimization Results
RESIDUAL SUM OF SQUARES
NORM OF THE GRADIENT
MARQUARDT SCALING PARAMETER
CO. OF FUNCTION EVALUATIONS
NO. OF ITERATIONS
=
=
=
=
=
5.142639e-02
6.068882e-02
0.340303
170
35
The maximum number of iterations (25) was exceeded. However, the results
probably are accurate. Increase ITROPT accordingly.
Optimized Parameters OPT1– Final Values
***OPTIMIZED PARAMETERS OPT1 SENS %NORM-SEN
.PARAM LBB = 1.5834N $ 27.3566X 2.4368
.PARAM LCC = 2.1334N $ 12.5835X 1.5138
.PARAM LEE =723.0995P $254.2312X 12.3262
.PARAM TF
= 12.7611P $ 7.4344G 10.0532
.PARAM CBE =620.5195F $ 23.0855G 1.5300
.PARAM CBC = 1.0263P $346.0167G 44.5016
.PARAM RB
= 2.0582
$ 12.8257M 2.3084
.PARAM RE
=869.8714M $ 66.8123M 4.5597
.PARAM RC
= 54.2262
$ 3.1427M 20.7359
.PARAM IS
= 99.9900P $ 3.6533X 34.4463M
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Optimization Examples
Figure 99
BJT-S Parameter Optimization
FILE: BJTOPT.SP NETWORK S-PARAMETER OPTIMIZATION
APRIL 22, 2004 6:22:34
BJTOPT.AC0
20.0
10.0
1.9879
BJTOPT.AC0
650.0N
[LIN]
600.0N
550.0N
BJTOPT.AC0
500.0N
450.0N
400.0N
96.8250N
BJTOPT.AC0
50.0N
20.0N
100.0X
500.0X
1.08
1.508
2.06
HERTZ [LIN]
BJT Model DC Optimization
The goal is to match forward and reverse Gummel plots obtained from a
HP4145 semiconductor analyzer by using the HSPICE LEVEL=1 GummelPoon BJT model. Because Gummel plots are at low base currents, HSPICE
does not optimize the base resistance. HSPICE also does not optimize forward
and reverse Early voltages (VAF and VAR), because simulation did not
measure VCE data.
The key feature in this optimization is incremental optimization.
1. HSPICE first optimizes the forward-Gummel data points.
2. HSPICE updates forward-optimized parameters into the model.
After updating, you cannot change these parameters.
3. HSPICE next optimizes the reverse-Gummel data points.
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Optimization Examples
BJT Model DC Optimization Input Netlist File
You can find the sample netlist for this example in the following directory:
$installdir/demo/hspice/devopt/opt_bjt.sp
Figure 100 BJT Optimization Forward Gummel Plots
*FILE: OPT_BJT.SP BJT OPTIMIZATION T2N9547
APRIL 22, 2004 17:42:41
OPT_BJT.SV0
I2IQ1
10.0N
PARIIB
1.0N
I1IQ1
AMP 2 LOW
PARIIC
100.0U
10.0U
1.0U
100.0M
10.0M
1.0M
100.0P
528
400.0M
500.0M
600.0M
BASEF [LIN]
700.0M
800.0M
820.0M
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Optimization Examples
Figure 101 BJT Optimization Reverse Gummel Plots
*FILE: OPT_BJT.SP BJT OPTIMIZATION T2N9547
APRIL 22, 2004 17:42:41
OPT_BJT.SV1
I2IQ1
10.0N
PARIIB
1.0N
I1IQ1
PARIIC
AMP 2 LCV
100.0U
10.0U
1.0U
100.0M
10.0M
1.0M
100.0P
200.0M
300.0M
400.0M
500.0M
BASER [LIN]
600.0M
700.0M
800.0M
Optimizing GaAsFET Model DC
This example circuit is a high-performance, GaAsFET transistor. The design
target is to match HP4145 DC measured data to the HSPICE LEVEL=3 JFET
model.
The HSPICE strategy is:
■
.MEASURE IDSERR is an ERR1 type function. It provides linear attenuation
of the error results starting at 20 mA. This function ignores all currents below
1 mA. The high-current fit is the most important for this model.
■
The OPT1 function simultaneously optimizes all DC parameters.
■
The .DATA statement merges TD1.dat and TD2.dat data files.
■
The graph plot model sets the MONO=1 parameter to remove the retrace
lines from the family of curves.
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Optimization Examples
GaAsFET Model DC Optimization Input Netlist File
You can find the sample netlist for this example in the following directory:
$installdir/demo/hspice/devopt/jopt.sp
Figure 102 JFET Optimization
*FILE: JOPT.SP JFET OPTIMIZATION
APRIL 22, 2004 18:41:12
JOPT.SVO
45.0M
40.0M
PARAM [LIN]
35.0M
30.0M
25.0M
20.0M
15.0M
10.0M
5.0M
0
0
1.0
2.0
DESIRED [LIN]
3.0
4.0
Optimizing MOS Op-amp
The design goals for the MOS operational amplifier are:
530
■
Minimize the gate area (and therefore the total cell area).
■
Minimize the power dissipation.
■
Open-loop transient step response of 100 ns for rising and falling edges.
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Optimization Examples
The HSPICE strategy is:
■
Simultaneously optimize two amplifier cells for rising and falling edges.
■
Total power is power for two cells.
■
The optimization transient analysis must be longer to allow for a range of
values in intermediate results.
■
All transistor widths and lengths are optimized.
■
Calculate the transistor area algebraically use a voltage value and minimize
the resulting voltage.
■
The transistor area measure statement uses MINVAL, which assigns less
weight to the area minimization.
■
Optimizes the bias voltage.
MOS Op-amp Optimization Input Netlist File
You can find the sample netlist for this example in the following directory:
$installdir/demo/hspice/ciropt/ampopt.sp
Figure 103 CMOS Op-amp
vsupply
M4
M3
M6
vout
vin-
M1
vbias
M2
vin+
M5
M7
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Optimization Examples
Figure 104 Operational Amplifier Optimization
AMPORT.SP MOS OPERATIONAL AMPLIFIER OPTIMIZATION
APRIL 22, 2004 18:57:06
3.9877
AMPORT.TR0
3.0
VOLT [LIN]
2.0
1.0
AMPORT.TR0
POWER
6.40M
6.20M
6.0M
5.80M
5.60M
5.40M
0
25.0N
50.0N
75.0N
100.0N
125.0N
150.0N
TIME [LIN]
532
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Running Demonstration Files
51
Contains examples of basic file construction techniques, advanced
features, and simulation tricks. Lists and describes several HSPICE
and HSPICE RF input files.
This chapter includes the following topics:
■
Using the Demo Directory Tree
■
Two-Bit Adder Demo
■
MOS I-V and C-V Plotting Demo
■
CMOS Output Driver Demo
■
Temperature Coefficients Demo
■
Simulating Electrical Measurements
■
Modeling Wide-Channel MOS Transistors
■
Demonstration Input Files
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Using the Demo Directory Tree
Using the Demo Directory Tree
Demonstration Input Files on page 552 lists demonstration files, which are
designed as good training examples. Most HSPICE or HSPICE RF distributions
include these examples in the demo directory tree, where $installdir is the
installation directory environment variable:
534
Directory
File
Description
$installdir/demo/
hspice
/alge
algebraic output
/apps
general applications
/behave
analog behavioral components
/bench
standard benchmarks
/bjt
bipolar components
/cchar
characteristics of cell prototypes
/ciropt
circuit level optimization
/ddl
Discrete Device Library
/devopt
device level optimization
/fft
Fourier analysis (HSPICE only)
/filters
filters
/mag
transformers, magnetic core components
/mos
MOS components
/rad
radiation effects (photocurrent)
/sources
dependent and independent sources
/tline
filters and transmission lines
/veriloga
Verilog-A examples
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Two-Bit Adder Demo
Two-Bit Adder Demo
This two-bit adder shows how to improve efficiency, accuracy, and productivity
in circuit simulation. The adder is in the $installdir/demo/hspice/apps/
mos2bit.sp (or $installdir/demo/hspicext/apps/mos2bit.sp for HSPICE RF)
demonstration file. It consists of two-input NAND gates, defined using the
NAND sub-circuit. CMOS devices include length, width, and output loading
parameters. Descriptive names enhance the readability of this circuit.
One-Bit Subcircuit
The ONEBIT subcircuit defines the two half adders, with carry in and carry out.
To create the two-bit adder, HSPICE or HSPICE RF uses two calls to ONEBIT.
Independent piecewise linear voltage sources provide the input stimuli. The R
repeat function creates complex waveforms.
Figure 105 One-bit Adder sub-circuit
in1
1
X8
X2
in2
X4
X7
10
13
X5
X1
half1
2
X8
4
TIME [LIN]
X3
9
carry-in
X6
#1_nand
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carry-out
X9
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MOS I-V and C-V Plotting Demo
Figure 106 Two-bit Adder Circuit
A(0)
B(0)
A(1)
B(1)
carry-out_1
carry-in
One Bit
One Bit
C(0)
C(1)
carry-out_2
Figure 107 1-bit NAND Gate Binary Adder
in1
1
X8
X2
in2
X4
X7
10
13
X5
X1
half1
2
X8
4
TIME [LIN]
X3
9
carry-in
X6
#1_nand
out
half2
carry-out
X9
MOS Two-Bit Adder Input File
You can find the sample netlist for this example in the following directory:
$installdir/demo/hspice/apps/mos2bit.sp
MOS I-V and C-V Plotting Demo
To diagnose a simulation or modeling problem, you usually need to review the
basic characteristics of the transistors. You can use this demonstration
template file, $installdir/demo/hspice/mos/mosivcv.sp (or $installdir/demo/
hspicext/mos/mosivcv.sp for HSPICE RF), with any MOS model. The example
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MOS I-V and C-V Plotting Demo
shows how to easily create input files, and how to display the complete
graphical results. The following features aid model evaluations:
Table 62 MOS I-V and C-V Plotting Demo
Value
Description
SCALE=1u
Sets the element units to microns (not meters). Most circuit
designs use microns.
DCCAP
Forces HSPICE or HSPICE RF to evaluate the voltage variable
capacitors, during a DC sweep.
node names
Makes a circuit easy to understand. Symbolic name contains up
to 16 characters.
.GRAPH
.GRAPH statements create high-resolution plots. To set
additional characteristics, add a graph model.
Plotting Variables
Use this template to plot internal variables, such as:
Table 63 Demo Plotting Variables
Variable
Description
i(mn1)
i1, i2, i3, or i4 can specify the true branch currents for each
transistor node.
LV18(mn6)
Total gate capacitance (C-V plot).
LX7(mn1)
GM gate transconductance. (LX8 specifies GDS, and LX9
specifies GMB).
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MOS I-V and C-V Plotting Demo
Figure 108 MOS IDS Plot
*FILE: MOS2BJT.SP TR0 BJT MOS ADDER
APRIL 24, 2003 13:12:24
4.50
MOS2BJT.TR0
4.0
MOS2BJT.TR0
3.50
VOLT [LIN]
VOLT [LIN]
3.0
2.50
2.0
1.50
1.0
500.0M
0
0
10.0N
20.0N
30.0N
40.0N
50.0N
60.0N
TIME [LIN]
538
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MOS I-V and C-V Plotting Demo
Figure 109 MOS VGS Plot
*FILE: MOS1VGS.SP IDS, VGS,CV, AND GM PLOT
APRIL 24, 2003 14:18:58
MOS1VGS.SV0
200.0U
180.0U
160.0U
AMP [LIN]
140.0U
120.0U
100.0U
80.0U
60.0U
40.0U
20.0U
0
0
1.0
2.0
3.0
VOLTS [LIN]
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5.0
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MOS I-V and C-V Plotting Demo
Figure 110 MOS GM Plot
*FILE: MOS1VGS.SP IDS, VGS,CV, AND GM PLOTS
APRIL 24, 2003 14:31:48
59.5887U
MOS1VGS.SV0
55.0U
50.0U
45.0U
AMP [LIN]
40.0U
35.0U
30.0U
25.0U
20.0U
15.0U
10.0U
5.0U
0
540
0
1.0
2.0
3.0
VOLTS [LIN]
4.0
5.0
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CMOS Output Driver Demo
Figure 111 MOS C-V Plot
*FILE: MOS1VGS.SP IDS, VGS,CV, AND GM PLOTS
APRIL 24, 2003 14:42:16
13.7840F
MOS1VGS.SV0
13.0F
12.0F
LX [LIN]
11.0F
10.0F
9.0F
8.0F
7.0F
6.0F
0
1.0
2.0
3.0
VOLTS [LIN]
4.0
5.0
MOS I-V and C-V Plot Example Input File
You can find the sample netlist for this example in the following directory:
$installdir/demo/hspice/mos/mosivcv.sp
CMOS Output Driver Demo
ASIC designers need to integrate high-performance IC parts onto a printed
circuit board (PCB). The output driver circuit is critical to system performance.
The $installdir/demo/hspice/apps/asic1.sp (or $installdir/demo/hspicext/apps/
asic1.sp for HSPICE RF) demonstration file shows models for an output driver,
the bond wire and leadframe, and a six-inch length of copper transmission line.
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CMOS Output Driver Demo
This simulation demonstrates how to:
■
Define parameters, and measure test outputs.
■
Use the LUMP5 macro to input geometric units, and convert them to
electrical units.
■
Use .MEASURE statements to calculate the peak local supply current,
voltage drop, and power.
■
Measure RMS power, delay, rise times, and fall times.
■
Simulate and measure an output driver under load. The load consists of:
•
Bondwire and leadframe inductance.
•
Bondwire and leadframe resistance.
•
Leadframe capacitance.
•
Six inches of 6-mil copper, on an FR-4 printed circuit board.
•
Capacitive load, at the end of the copper wire.
Strategy
The HSPICE or HSPICE RF strategy is to:
542
■
Create a five-lump transmission line model for the copper wire.
■
Create single lumped models for leadframe loads.
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CMOS Output Driver Demo
Figure 112 Noise Bounce
*FILE: MOS1VGS.SP IDS, VGS,CV, AND GM PLOTS
APRIL 24, 2004 14:53:29
MOS1VGS.SV0
59.5887U
GM_N
55.0U
GM_P
50.0U
45.0U
LX [LIN]
40.0U
35.0U
30.0U
25.0U
20.0U
15.0U
10.0U
5.0U
0
0
1.0
2.0
3.0
4.0
5.0
VOLTS [LIN]
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CMOS Output Driver Demo
Figure 113 Asic1.sp Demo Local Supply Voltage
*FILE: MOS1VGS.SP IDS, VGS,CV, AND GM PLOTS
APRIL 24, 2003 15:24:31
13.7840F
MOS1VGS.SV0
CG-TOT_N
13.0F
CG-TOT_P
LX [LIN]
12.0F
11.0F
10.0F
9.0F
8.0F
7.0F
6.0F
0
544
1.0
2.0
3.0
VOLTS [LIN]
4.0
5.0
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CMOS Output Driver Demo
Figure 114 Asic1.sp Demo Local Supply Current
*FILE: ASIC1.SP GROUND BOUNCE FOR I/O CMOS DRIVER
APRIL 24, 2003 15:29:24
5.8829
ASIC1.TR0
5.0
LX [LIN]
4.0
3.0
2.0
1.0
0
-1.0
0
5.0N
10.0N
15.0N
20.0N
25.0N
30.0N
TIME [LIN]
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Temperature Coefficients Demo
Figure 115 Asic1.sp Demo Input and Output Signals
*FILE: ASIC1.SP GROUND BOUNCE FOR I/O CMOS DRIVER
APRIL 24, 2004 15:39:18
ASIC1.TR0
POWER
325.0M
300.0M
275.0M
PARAM [LIN]
250.0M
225.0M
200.0M
175.0M
150.0M
125.0M
100.0M
75.0M
50.0M
25.0M
0
5.0N
10.0N
15.0N
20.0N
25.0N
30.0N
TIME [LIN]
CMOS Output Driver Example Input File
You can find the sample netlist for this example in the following directory:
$installdir/demo/hspice/apps/asic1.sp
Temperature Coefficients Demo
SPICE-type simulators do not always automatically compensate for variations
in temperature. The simulators make many assumptions that are not valid for
all technologies. Many of the critical model parameters in HSPICE or HSPICE
RF provide first-order and second-order temperature coefficients, to ensure
accurate simulations.
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Temperature Coefficients Demo
You can optimize these temperature coefficients in either of two ways.
■
The first method uses the TEMP DC sweep variable.
All analysis sweeps allow two sweep variables. To optimize the temperature
coefficients, one of these must be the optimize variable. Sweeping TEMP
limits the component to a linear element, such as a resistor, inductor, or
capacitor.
■
The second method uses multiple components at different temperatures.
Example
The following example, the $installdir/demo/hspice/ciropt/opttemp.sp (or
$installdir/demo/hspicext/ciropt/opttemp.sp for HSPICE RF) demo file,
simulates three circuits of a voltage source. It also simulates a resistor at -25, 0,
and +25 °C from nominal, using the DTEMP parameter for element delta
temperatures. The resistors share a common model.
You need three temperatures to solve a second-order equation. You can extend
this simulation template to a transient simulation of non-linear components
(such as bipolar transistors, diodes, and FETs).
This example uses some simulation shortcuts. In the internal output templates
for resistors, LV1 (resistor) is the conductance (reciprocal resistance) at the
desired temperature.
■
You can run optimization in the resistance domain.
■
To optimize more complex elements, use the current or voltage domain, with
measured sweep data.
The error function expects a sweep on at least two points, so the data
statement must include two duplicate points.
Input File for Optimized Temperature Coefficients
You can find the sample netlist for this example in the following directory:
$installdir/demo/hspice/ciropt/opttemp.sp
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Simulating Electrical Measurements
Optimization Section
.model optmod opt
.dc data=RES_TEMP optimize=opt1
+
[email protected],[email protected],[email protected]
+
model=optmod
.param tc1r_opt=opt1(.001,-.1,.1)
.param tc2r_opt=opt1(1u,-1m,1m)
.meas [email protected] err2 par(R_meas_t1) par('1.0 / lv1(r-25)')
.meas [email protected] err2 par(R_meas_t2) par('1.0 / lv1(r0) ')
.meas [email protected] err2 par(R_meas_t3) par('1.0 / lv1(r+25) ')
* * Output section *
.dc data=RES_TEMP
.print 'r1_diff'=par('1.0/lv1(r-25)')
+
'r2_diff'=par('1.0/lv1(r0) ')
+
'r3_diff'=par('1.0/lv1(r+25)')
.data RES_TEMP R_meas_t1 R_meas_t2 R_meas_t3
950 1000 1010
950 1000 1010
.enddata
.end
Simulating Electrical Measurements
In this example, HSPICE or HSPICE RF simulates electrical measurements,
which return device characteristics for data sheets. The demonstration file for
this example is $installdir/demo/hspice/ddl/t2n2222.sp (or $installdir/demo/
hspicext/ddl/t2n2222.sp for HSPICE RF). This example automatically includes
DDL models by reference, using either the DDLPATH environment variable, or
the .OPTION SEARCH=path statement. It also combines an AC circuit and
measurement, with a transient circuit and measurement.
The AC circuit measures the maximum Hfe, which is the small-signal common
emitter gain. HSPICE or HSPICE RF uses the .MEASURE WHEN statement to
calculate the unity gain frequency, and the phase at the specified frequency. In
the Transient Measurements section of the input file, a segmented transient
statement speeds-up simulation, and compresses the output graph.
Measurements include:
548
■
TURN ONfrom 90% of input rising, to 90% of output falling.
■
OUTPUT FALLfrom 90% to 10% of output falling.
■
TURN OFFfrom 10% of input falling, to 10% of output rising.
■
OUTPUT RISEfrom 10% to 90% of output rising.
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Modeling Wide-Channel MOS Transistors
Figure 116 T2N2222 Optimization
*FILE: ASIC2.SP TEST OF I/O STAGE LUMPED MOS MODEL
APRIL 24, 2003 15:52:09
ASIC2.TR0
10.0M
9.0M
8.0M
7.0M
PARAM (LIN)
6.0M
5.0M
4.0M
3.0M
2.0M
1.0M
0
-1.0M 0
200.0P
400.0P
600.0P
800.0P
TIME [LIN]
T2N2222 Optimization Example Input File
You can find the sample netlist for this example in the following directory:
$installdir/demo/hspice/ddl/t2n2222.sp
Modeling Wide-Channel MOS Transistors
If you select an appropriate model for I/O cell transistors, simulation accuracy
improves. For wide-channel devices, model the transistor as a group of
transistors, connected in parallel, with appropriate RC delay networks. If you
model the device as only one transistor, the polysilicon gate introduces delay.
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Modeling Wide-Channel MOS Transistors
When you scale to higher-speed technologies, the area of the polysilicon gate
decreases, reducing the gate capacitance. However, if you scale the gate oxide
thickness, the capacitance per unit area increases, which also increases the
RC product.
Example
The following example illustrates how scaling affects the delay. For example, for
a device with:
■
Channel width = 100 microns.
■
Channel length = 5 microns.
■
Gate oxide thickness = 800 Angstroms.
The resulting RC product for the polysilicon gate is:
W
Rpoly = ----- ⋅ 40
L
Esio ⋅ nsi
poly = ----------------------- ⋅ L ⋅ W
tox
100
Rpoly = --------- ⋅ 40 = 800 ,
5
3.9 ⋅ 8.86
Co = ---------------------- ⋅ 100 ⋅ 5 = 215 fF RC = 138 ps
800
For a transistor with:
■
Channel width = 100 microns.
■
Channel length = 1.2 microns.
■
Gate oxide thickness = 250 Angstroms.
The resulting RC product for the polysilicon gate is:
channel width
Rpoly = ----------------------------------------- ⋅ 40
channel length
3.9 ⋅ 8.86
Co = ---------------------- ⋅ channel width ⋅ channel length RC = 546 ps
Tox
You can use a nine-stage ladder model to model the RC delay in CMOS
devices.
550
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Modeling Wide-Channel MOS Transistors
Figure 117 Nine-stage Ladder Model
Drain
M1
W/18
M2
W/9
M3
W/9
M4
W/9
M5
W/19
M6
W/9
M7
W/9
M8
W/9
M9
W/9
M10
W/18
Bulk Source
In this example, the nine-stage ladder model is in data file $installdir/demo/
hspice/apps /asic3.sp. To optimize this model, HSPICE uses measured data
from a wide channel transistor as the target data\. Optimization produces a
nine-stage ladder model, which matches the timing characteristics of the
physical data (HSPICE RF does not support optimization). HSPICE compares
the simulation results for the nine-stage ladder model, and the one-stage model
by using the nine-stage ladder model as the reference. The one-stage model
results are about 10% faster than actual physical data indicates.
Example
You can find the sample Nine-Stage Ladder model netlist for this example in the
following directory:
$installdir/demo/hspice/apps/asic3.sp
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Demonstration Input Files
Figure 118 Asic3 Single vs. Lumped Model
*FILE: ASIC2.SP TEST OF I/O STAGE LUMPED MOS MODEL
APRIL 24, 2004 16:02:35
ASIC2.TR0
10.0M
9.0M
8.0M
PARAM [LIN]
7.0M
6.0M
5.0M
4.0M
3.0M
2.0M
1.0M
0
-1.0M 0
200.0
400.0
600.0
800.0
TIME [LIN]
Demonstration Input Files
File Name
Description
Algebraic Output Variable Examples$installdir/demo/hspice/alge
552
alg.sp
demonstrates algebraic parameters
alg_fil.sp
magnitude response of the behavioral filter model
alg_vco.sp
voltage-controlled oscillator
alg_vf.sp
voltage-to-frequency converter behavioral model
xalg1.sp
QA of parameters
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Demonstration Input Files
File Name
Description
xalg2.sp
QA of parameters
Applications of General Interest$installdir/demo/hspice/apps
alm124.sp
AC, noise, and transient op-amp analysis
alter2.sp
.ALTER examples
ampg.sp
pole/zero analysis of a G source amplifier
asic1.sp
ground bounce for I/O CMOS driver
asic3.sp
ten-stage lumped MOS model
bjt2bit.sp
BJT two-bit adder
bjt4bit.sp
four-bit all NAND gate, binary adder
bjtdiff.sp
BJT diff amp with every analysis type
bjtschmt.sp
bipolar Schmidt trigger
bjtsense.sp
bipolar sense amplifier
cellchar.sp
characteristics of ASIC inverter cell
crystal.sp
crystal oscillator circuit
gaasamp.sp
simple GaAsFET amplifier
grouptim.sp
group time-delay example
inv.sp
sweep MOSFET -3 sigma to +3 sigma use .MEASURE output
mcdiff.sp
CMOS differential amplifier
mondc_a.sp
Monte Carlo of MOS diffusion and photolithographic effects
(HSPICE only)
mondc_b.sp
Monte Carlo DC analysis (HSPICE only)
mont1.sp
Monte Carlo Gaussian, uniform, and limit function (HSPICE only)
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Demonstration Input Files
File Name
Description
mos2bit.sp
two-bit MOS adder
opampdcm.sp
DCmatch analysis
pll.sp
phase-locked loop
sclopass.sp
switched-capacitor low-pass filter
worst.sp
worst case skew models by using .ALTER
xbjt2bit.sp
BJT NAND gate two-bit binary adder
Behavioral Applications$installdir/demo/hspice/behave
554
acl.sp
acl gate
amp_mod.sp
amplitude modulator with pulse waveform carrier
behave.sp
AND/NAND gates by using G, E Elements
calg2.sp
voltage variable capacitance
det_dff.sp
double edge-triggered flip-flop
diff.sp
differentiator circuit
diode.sp
behavioral diode by using a PWL VCCS
dlatch.sp
CMOS D-latch by using behaviorals
galg1.sp
sampling a sine wave
idealop.sp
ninth-order low-pass filter
integ.sp
integrator circuit
invb_op.sp
optimizes the CMOS macromodel inverter
ivx.sp
characteristics of the PMOS and NMOS as a switch
op_amp.sp
op-amp from Chua and Lin
pd.sp
phase detector modeled as switches
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Demonstration Input Files
File Name
Description
pdb.sp
phase detector by using behavioral NAND gates
pwl10.sp
operational amplifier used as a voltage follower
pwl2.sp
PPW-VCCS with a gain of 1 amp/volt
pwl4.sp
eight-input NAND gate
pwl7.sp
modeling inverter by using a PWL VCVS
pwl8.sp
smoothing the triangle waveform by using the PWL CCCS
ring5bm.sp
five-stage ring oscillator – macromodel CMOS inverter
ringb.sp
ring oscillator by using behavioral model
sampling.sp
sampling a sine wave
scr.sp
silicon-controlled rectifier, modeled using the PWL CCVS
swcap5.sp
fifth-order elliptic switched capacitor filter
switch.sp
test for PWL switch element
swrc.sp
switched capacitor RC circuit
triode.sp
triode model family of curves by using behavioral elements
triodex.sp
triode model family of curves by using behavioral elements
tunnel.sp
modeling tunnel diode characteristic by using PWL VCCS
vcob.sp
voltage-controlled oscillator by using PWL functions
Benchmarks$installdir/demo/hspice/bench
bigmos1.sp
large MOS simulation
demo.sp
quick demo file to test installation
m2bit.sp
72-transistor two-bit adder – typical cell simulation
m2bitf.sp
fast simulation example
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15: Running Demonstration Files
Demonstration Input Files
File Name
Description
m2bitsw.sp
Fast simulation example. Same as m2bitf.sp, but uses behavioral
elements
senseamp.sp
bipolar analog test case
Timing Analysis$installdir/demo/hspice/bisect
fig3a.sp
DFF bisection search for setup time
fig3b.sp
DFF early, optimum, and late setup times
inv_a.sp
inverter bisection (pass-fail)
BJT and Diode Devices$installdir/demo/hspice/bjt
bjtbeta.sp
plot BJT beta
bjtft.sp
plot BJT FT by using s-parameters
bjtgm.sp
plot BJT Gm, Gpi
dpntun.sp
junction tunnel diode
snaphsp.sp
convert SNAP to HSPICE
tun.sp
tunnel oxide diode
Cell Characterization$installdir/demo/hspice/cchar
556
dff.sp
DFF bisection search for setup time
inv3.sp
characteristics of an inverter
inva.sp
characteristics of an inverter
invb.sp
characteristics of an inverter
load1.sp
inverter sweep, delay versus fanout
setupbsc.sp
setup characteristics
setupold.sp
setup characteristics
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Demonstration Input Files
File Name
Description
setuppas.sp
setup characteristics
sigma.sp
sweep MOSFET -3 sigma to +3 sigma by using measure output
tdgtl.a2d
Viewsim A2D HSPICE or HSPICE RF input file
tdgtl.d2a
Viewsim D2A HSPICE or HSPICE RF input file
tdgtl.sp
two-bit adder by using D2A Elements
Circuit Optimization$installdir/demo/hspice/ciropt
ampgain.sp
set unity gain frequency of a BJT diff pair
ampopt.sp
optimize area, power, speed of a MOS amp
asic2.sp
optimize speed, power of a CMOS output buffer
asic6.sp
find best width of a CMOS input buffer
delayopt.sp
optimize group delay of an LCR circuit
lpopt.sp
match lossy filter to ideal filter
opttemp.sp
find first and second temperature coefficients of a resistor
rcopt.sp
optimize speed or power for an RC circuit
DDL$installdir/demo/hspice/ddl
ad8bit.sp
eight-bit A/D flash converter
alf155.sp
characteristics of National JFET op-amp
alf156.sp
characteristics of National JFET op-amp
alf157.sp
characteristics of National JFET op-amp
alf255.sp
characteristics of National JFET op-amp
alf347.sp
characteristics of National JFET op-amp
alf351.sp
characteristics of National wide-bandwidth, JFET input, op-amp
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Demonstration Input Files
File Name
Description
alf353.sp
characteristics of National wide-bandwidth, dual JFET input, opamp
alf355.sp
characteristics of Motorola JFET, op-amp
alf356.sp
characteristics of Motorola JFET, op-amp
alf357.sp
characteristics of Motorola JFET, op-amp
alf3741.sp
alm101a.sp
558
alm107.sp
characteristics of National op-amp
alm108.sp
characteristics of National op-amp
alm108a.sp
characteristics of National op-amp
alm118.sp
characteristics of National op-amp
alm124.sp
characteristics of National low-power, quad op-amp
alm124a.sp
characteristics of National low-power, quad op-amp
alm158.sp
characteristics of National op-amp
alm158a.sp
characteristics of National op-amp
alm201.sp
characteristics of LM201 op-amp
alm201a.sp
characteristics of LM201 op-amp
alm207.sp
characteristics of National op-amp
alm208.sp
characteristics of National op-amp
alm208a.sp
characteristics of National op-amp
alm224.sp
characteristics of National op-amp
alm258.sp
characteristics of National op-amp
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Demonstration Input Files
File Name
Description
alm258a.sp
characteristics of National op-amp
alm301a.sp
characteristics of National op-amp
alm307.sp
characteristics of National op-amp
alm308.sp
characteristics of National op-amp
alm308a.sp
characteristics of National op-amp
alm318.sp
characteristics of National op-amp
alm324.sp
characteristics of National op-amp
alm358.sp
characteristics of National op-amp
alm358a.sp
characteristics of National op-amp
alm725.sp
characteristics of National op-amp
alm741.sp
characteristics of National op-amp
alm747.sp
characteristics of National op-amp
alm747c.sp
characteristics of National op-amp
alm1458.sp
characteristics of National dual op-amp
alm1558.sp
characteristics of National dual op-amp
alm2902.sp
characteristics of National op-amp
alm2904.sp
characteristics of National op-amp
amc1458.sp
characteristics of Motorola internally-compensated, highperformance op-amp
amc1536.sp
characteristics of Motorola internally-compensated, high-voltage
op-amp
amc1741.sp
characteristics of Motorola internally-compensated, highperformance op-amp
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Demonstration Input Files
560
File Name
Description
amc1747.sp
characteristics of Motorola internally-compensated, highperformance op-amp
ane5534.sp
characteristics of TI low-noise, high-speed op-amp
anjm4558.sp
characteristics of TI dual op-amp
anjm4559.sp
characteristics of TI dual op-amp
anjm4560.sp
characteristics of TI dual op-amp
aop04.sp
characteristics of PMI op-amp
aop07.sp
characteristics of PMI ultra-low offset voltage, op-amp
aop14.sp
characteristics of PMI op-amp
aop15b.sp
characteristics of PMI precision JFET input, op-amp
aop16b.sp
characteristics of PMI precision JFET input, op-amp
at094cns.sp
characteristics of TI op-amp
atl071c.sp
characteristics of TI low-noise, op-amp
atl072c.sp
characteristics of TI low-noise, op-amp
atl074c.sp
characteristics of TI low-noise, op-amp
atl081c.sp
characteristics of TI JFET op-amp
atl082c.sp
characteristics of TI JFET op-amp
atl084c.sp
characteristics of TI JFET op-amp
atl092cp.sp
characteristics of TI op-amp
atl094cn.sp
characteristics of TI op-amp
aupc358.sp
characteristics of NEC general, dual op-amp
aupc1251.sp
characteristics of NEC general, dual op-amp
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Demonstration Input Files
File Name
Description
j2n3330.sp
characteristics of JFET 2n3330 I-V
mirf340.sp
characteristics of IRF340 I-V
t2n2222.sp
characteristics of BJT 2n2222
Device Optimization (HSPICE only)$installdir/demo/hspice/devopt
beta.sp
LEVEL=2 beta optimization
bjtopt.sp
s-parameter optimization of a 2n6604 BJT
bjtopt1.sp
2n2222 DC optimization
bjtopt2.sp
2n2222 Hfe optimization
d.sp
diode, multiple temperatures
dcopt1.sp
1n3019 diode, I-V and C-V optimization
gaas.sp
JFET optimization
jopt.sp
300u/1u GaAs FET, DC optimization
jopt2.sp
JFET optimization
joptac.sp
300u/1u GaAs FET, 40 MHz–20 GHz, s-parameter optimization
l3.sp
MOS LEVEL 3 optimization
l3a.sp
MOS LEVEL 3 optimization
l28.sp
LEVEL=28 optimization
ml2opt.sp
MOS LEVEL=2 I-V optimization
ml3opt.sp
MOS LEVEL=3 I-V optimization
ml6opt.sp
MOS LEVEL=6 I-V optimization
ml13opt.sp
MOS LEVEL=13 I-V optimization
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Demonstration Input Files
File Name
Description
opt_bjt.sp
2n3947 forward and reverse Gummel optimization
Fourier Analysis (HSPICE only)$installdir/demo/hspice/fft
562
am.sp
FFT analysis, AM source
bart.sp
FFT analysis, Bartlett window
black.sp
FFT analysis, Blackman window
dist.sp
FFT analysis, second harmonic distortion
exam1.sp
FFT analysis, AM source
exam3.sp
FFT analysis, high-frequency signal detection test
exam4.sp
FFT analysis, small-signal harmonic distortion test
exp.sp
FFT analysis, exponential source
fft.sp
FFT analysis, transient, sweeping a resistor
fft1.sp
FFT analysis, transient
fft2.sp
FFT analysis on the product of three waveforms
fft3.sp
FFT analysis, transient, sweeping frequency
fft4.sp
FFT analysis, transient, Monte Carlo Gaussian distribution
fft5.sp
FFT analysis, data-driven transient analysis
fft6.sp
FFT analysis, sinusoidal source
gauss.sp
FFT analysis, Gaussian window
hamm.sp
FFT analysis, Hamming window
hann.sp
FFT analysis, Hanning window
harris.sp
FFT analysis, Blackman-Harris window
intermod.sp
FFT analysis, intermodulation distortion
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Demonstration Input Files
File Name
Description
kaiser.sp
FFT analysis, Kaiser window
mod.sp
FFT analysis, modulated pulse
pulse.sp
FFT analysis, pulse source
pwl.sp
FFT analysis, piecewise linear source
rect.sp
FFT analysis, rectangular window
rectan.sp
FFT analysis, rectangular window
sffm.sp
FFT analysis, single-frequency FM source
sine.sp
FFT analysis, sinusoidal source
swcap5.sp
FFT analysis, fifth-order elliptic, switched-capacitor filter
tri.sp
FFT analysis, rectangular window
win.sp
FFT analysis, window test
window.sp
FFT analysis, window test
winreal.sp
FFT analysis, window test
Filters$installdir/demo/hspice/filters
fbp_1.sp
bandpass LCR filter, measurement
fbp_2.sp
bandpass LCR filter, pole/zero
fbpnet.sp
bandpass LCR filter, s-parameters
fbprlc.sp
LCR AC analysis for resonance
fhp4th.sp
high-pass LCR, fourth-order Butterworth filter
fkerwin.sp
pole/zero analysis of Kerwin’s circuit
flp5th.sp
low-pass, fifth-order filter
flp9th.sp
low-pass, ninth-order FNDR, with ideal op-amps
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Demonstration Input Files
File Name
Description
micro1.sp
test of microstrip
micro2.sp
test of microstrip
tcoax.sp
test of RG58/AU coax
trans1m.sp
FR-4, printed-circuit, lumped transmission line
Magnetics$installdir/demo/hspice/mag
aircore.sp
air-core transformer circuit
bhloop.sp
b-h loop, non-linear, magnetic-core transformer
mag2.sp
three primary, two secondary, magnetic-core transformer
magcore.sp
magnetic-core transformer circuit
royerosc.sp
Royer magnetic-core oscillator
MOSFET Devices$installdir/demo/hspice/mos
564
bsim3.sp
LEVEL=47 BSIM3 model
cap13.sp
plot MOS capacitances, LEVEL=13 model
cap_b.sp
capacitances for LEVEL=13 model
cap_m.sp
capacitance for LEVEL=13 model
capop0.sp
plot MOS capacitances, LEVEL=2
capop1.sp
plot MOS capacitances, LEVEL=2
capop2.sp
plot MOS capacitances, LEVEL=2
capop4.sp
plot MOS capacitances, LEVEL=6
chrgpump.sp
charge-conservation test, LEVEL=3
iiplot.sp
plot of impact ionization current
ml6fex.sp
plot temperature effects, LEVEL=6
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Demonstration Input Files
File Name
Description
ml13fex.sp
plot temperature effects, LEVEL=13
ml13ft.sp
s-parameters for LEVEL=13
ml13iv.sp
plot I-V for LEVEL=13
ml27iv.sp
plot I-V for LEVEL=27 SOSFET
mosiv.sp
plot I-V for files that you include
mosivcv.sp
plot I-V and C-V for LEVEL=3
qpulse.sp
charge-conservation test, LEVEL=6
qswitch.sp
charge-conservation test, LEVEL=6
selector.sp
automatic model selector for width and length
tgam2.sp
LEVEL=6, gamma model
tmos34.sp
MOS LEVEL=34 EPFL, test DC
Radiation Effects$installdir/demo/hspice/rad
brad1.sp
example of bipolar radiation effects
brad2.sp
example of bipolar radiation effects
brad3.sp
example of bipolar radiation effects
brad4.sp
example of bipolar radiation effects
brad5.sp
example of bipolar radiation effects
brad6.sp
example of bipolar radiation effects
drad1.sp
example of diode radiation effects
drad2.sp
example of diode radiation effects
drad4.sp
example of diode radiation effects
drad5.sp
example of diode radiation effects
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Demonstration Input Files
566
File Name
Description
drad6.sp
example of diode radiation effects
dradarb2.sp
example of diode radiation effects
jex1.sp
example of JFET radiation effects
jex2.sp
example of JFET radiation effects
jprad1.sp
example of JFET radiation effects
jprad2.sp
example of JFET radiation effects
jprad4.sp
example of JFET radiation effects
jrad1.sp
example of JFET radiation effects
jrad2.sp
example of JFET radiation effects
jrad3.sp
example of JFET radiation effects
jrad4.sp
example of JFET radiation effects
jrad5.sp
example of JFET radiation effects
jrad6.sp
example of JFET radiation effects
mrad1.sp
example of MOSFET radiation effects
mrad2.sp
example of MOSFET radiation effects
mrad3.sp
example of MOSFET radiation effects
mrad3p.sp
example of MOSFET radiation effects
mrad3px.sp
example of MOSFET radiation effects
rad1.sp
example of total MOSFET dose
rad2.sp
diode photo-current test circuit
rad3.sp
diode photo-current test circuit, RLEV=3
rad4.sp
diode photo-current test circuit
HSPICE® Simulation and Analysis User Guide
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15: Running Demonstration Files
Demonstration Input Files
File Name
Description
rad5.sp
BJT photo-current test circuit, with an NPN transistor
rad6.sp
BJT secondary photo-current effect, which varies with R1
rad7.sp
BJT RLEV=6 example (semi-empirical model)
rad8.sp
JFET RLEV=1 example with Wirth-Rogers square pulse
rad9.sp
JFET stepwise-increasing radiation source
rad10.sp
GaAs RLEV=5 example (semi-empirical model)
rad11.sp
NMOS E-model, LEVEL=8 with Wirth-Rogers square pulse
rad12.sp
NMOS 0.5x resistive voltage-divider
rad13.sp
three-input NMOS NAND gate with non-EPI, EPI and SOS
examples
rad14.sp
GaAs differential-amplifier circuit
rad14dc.sp
n-channel JFET, DC I-V curves
Sources$installdir/demo/hspice/sources
amsrc.sp
amplitude modulation
exp.sp
exponential independent source
pulse.sp
test of pulse
pwl.sp
repeated piecewise-linear source
pwl10.sp
op-amp, voltage follower
rtest.sp
voltage-controlled resistor, inverter chain
sffm.sp
single-frequency, FM modulation source
sin.sp
sinusoidal source, waveform
vcr1.sp
switched-capacitor network by using G-switch
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Demonstration Input Files
File Name
Description
Transmission Lines$installdir/demo/hspice/tline
568
fr4.sp
microstrip test, FR-4 PC board material
fr4o.sp
optimizing model for microstrip FR-4 PC board material
fr4x.sp
FR4 microstrip test
hd.sp
ground bounce for I/O CMOS driver
rcsnubts.sp
ground bounce for I/O CMOS driver, at snubber output
rcsnubtt.sp
ground bounce for I/O CMOS driver
strip1.sp
two microstrips, in series (8 mil and 16 mil wide)
strip2.sp
two microstrips, coupled together
t14p.sp
1400 mil by 140 mil, 50-ohm tline, on FR-4, 50 MHz to 10.05 GHz
t14xx.sp
1400 mil by 140 mil, 50-ohm tline, on FR-4 optimization
t1400.sp
1400 mil by 140 mil, 50-ohm tline, on FR-4 optimization
tcoax.sp
RG58/AU coax, with 50-ohm termination
tfr4.sp
microstrip test
tfr4o.sp
microstrip test
tl.sp
series source, coupled and shunt-terminated transmission lines
transmis.sp
algebraics, and lumped transmission lines
twin2.sp
twin-lead model
xfr4.sp
microstrip test sub-circuit, expanded
xfr4a.sp
microstrip test sub-circuit, expanded, larger ground-resistance
xfr4b.sp
microstrip test
xulump.sp
test 5-, 20-, and 100-lump, U models
HSPICE® Simulation and Analysis User Guide
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Demonstration Input Files
File Name
Description
Verilog-A$installdir/demo/hspice/veriloga
resistor.sp
a very simple Verilog-A resistor model
sinev.sp
simple voltage source
deadband.sp
deadband amplifier
pll.sp
behavioral model of PLL
psfet.sp
Parker Skellern FET model
colpitts.va
Colpitts BJT oscillator
ecl.sp
ECL inverter
opamp.sp
opamp
sample_hold.sp sample and hold
biterrorrate.sp
bit error rate counter
dac.sp
DAC and ADC
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Demonstration Input Files
570
HSPICE® Simulation and Analysis User Guide
X-2005.09
A
Full Simulation Examples
A
Contains information and sample input netlists for two full
simulation examples.
The examples in this chapter show the basic text and post-processor output for
two sample input netlists.
Note: The examples are for Synopsys HSPICE, but with minimal
modifications, you can also apply these examples to HSPICE RF.
The first example uses AvanWaves to view results. The second example uses
Cosmos-Scope.
Simulation Example Using AvanWaves
Input Netlist and Circuit
The following example is an input netlist for a linear CMOS amplifier. Comment
lines indicate the individual sections of the netlist.
* Example HSPICE netlist, using a linear CMOS amplifier
* netlist options
.option post probe brief nomod
* defined parameters
.param analog_voltage=1.0
* global definitions
.global vdd
* source statements
Vinput in gnd SIN ( 0.0v analog_voltage 10x )
Vsupply vdd gnd DC=5.0v
* circuit statements
Rinterm in gnd 51
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Simulation Example Using AvanWaves
Cincap in infilt 0.001
Rdamp infilt clamp 100
Dlow gnd clamp diode_mod
Dhigh clamp vdd diode_mod
Xinv1 clamp inv1out inverter
Rpull clamp inv1out 1x
Xinv2 inv1out inv2out inverter
Routterm inv2out gnd 100x
* subcircuit definitions
.subckt inverter in out
Mpmos out in vdd vdd pmos_mod l=1u w=6u
Mnmos out in gnd gnd nmos_mod l=1u w=2u
.ends
* model definitions
.model pmos_mod pmos level=3
.model nmos_mod nmos level=3
.model diode_mod d
* analysis specifications
.TRAN 10n 1u sweep analog_voltage lin 5 1.0 5.0
* output specifications
.probe TRAN v(in) v(clamp) v(inv1out) v(inv2out) i(dlow)
.measure TRAN falltime TRIG v(inv2out) VAL=4.5v FALL=1
+
TARG V(inv2out) VAL=0.5v FALL=1
.end
You can find the complete sample netlist for this example in the following
directory:
$installdir/demo/hspice/bench/example.sp
Figure 119 is a circuit diagram for the linear CMOS amplifier in the circuit
portion of the netlist. The two sources in the diagram are also in the netlist.
Note: The inverter symbols in the circuit diagram are constructed from two
complementary MOSFET elements. Also, the diode and MOSFET models
in the netlist do not have non-default parameter values, except to specify
Level 3 MOSFET models (empirical model).
572
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Simulation Example Using AvanWaves
Figure 119 Circuit Diagram for Linear CMOS Inverter
Analog
Source
10 MHz
1V to 5V
+5V
10 MOhm
0.001 F
100 Ohm
Output
Node
100 MOhm
51 Ohm
Execution and Output Files
The following section displays the output files from a HSPICE simulation of the
amplifier shown in the previous section. To execute the simulation, enter:
hspice example.sp > example.lis
In this syntax, the input netlist name is example.sp, and the output listing file
name is example.lis. Simulation creates the following output files:
Table 64
HSPICE Output Files
File Name
Description
example.ic
Initial conditions for the circuit.
example.lis
Text simulation output listing.
example.mt0
Post-processor output for .MEASURE statements.
example.pa0
Subcircuit path table.
example.st0
Run-time statistics.
example.tr0
Post-processor output for transient analysis.
The following subsections show text files to simulate the amplifier by using
HSPICE on a Sun workstation. The example does not show the two postprocessor output files, which are in binary format.
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Simulation Example Using AvanWaves
Example.ic
* "simulator" "HSPICE"
* "version" "98.4 (981215) "
* "format" "HSP"
* "rundate" "13:58:43 01/08/1999"
* "netlist" "example.sp "
* "runtitle" "* example hspice netlist using a linear
* cmos amplifier "
* time =
0.
* temperature =
25.0000
*** BEGIN: Saved Operating Point ***
.option gmindc=
1.0000p
.nodeset
+ clamp =
2.6200
+ in =
0.
+ infilt =
2.6200
+ inv1out =
2.6200
+ inv2out =
2.6199
+ vdd =
5.0000
***
END: Saved Operating Point ***
Example.lis
Using: /net/sleepy/l0/group/hspice/98.4beta/sol4/hspice
****** HSPICE -- 98.4 (981215) 13:58:43 01/08/1999 solaris
Copyright (C) 1985-2002 by Synopsys Corporation.
Unpublished-rights reserved under US copyright laws.
This program is protected by law and is subject to the
terms and conditions of the license agreement found in:
/afs/rtp.synopsys.com/product/hspice/current/license.txt
Use of this program is your acceptance to be bound by this
license agreement. HSPICE is a trademark of Synopsys, Inc.
Input File: example.sp
lic:
lic: FLEXlm:v5.12 USER:hspiceuser HOSTNAME:hspiceserv
+ HOSTID:8086420f PID:1459
lic:
lic:
lic:
lic:
574
Using FLEXlm license file:
/afs/rtp/product/distrib/bin/license/license.dat
Checkout hspice; Encryption code: AC34CE559E01F6E05809
License/Maintenance for hspice will expire on 14-apr-
HSPICE® Simulation and Analysis User Guide
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Simulation Example Using AvanWaves
+ 1999/1999.200
lic: 1(in_use)/10 FLOATING license(s) on SERVER hspiceserv
lic:
******
* example hspice netlist using a linear cmos amplifier
******
* netlist options
.option post probe brief nomod
* defined parameters
Opening plot unit= 15
file=./example.pa0
****** HSPICE -98.4 (981215) 13:58:43
****** 01/08/1999 solaris ******
* example hspice netlist using a linear cmos amplifier
***** transient analysis tnom= 25.000 temp= 25.000 *****
*** parameter analog_voltage
=
1.000E+00 ***
node
=voltage
node
=voltage
+0:clamp =
2.6200 0:in
=
0.
+0:inv1out =2.6200 0:inv2out = 2.6199
node
=voltage
0:infilt =
2.6200
0:vdd
=
5.0000
Opening plot unit= 15
file=./example.tr0
**warning** negative-mos conductance = 1:mnmos iter= 2
vds,vgs,vbs =
2.45
2.93
0.
gm,gds,gmbs,ids=
-3.636E-05
1.744E-04 0. 1.598E-04
******
* example hspice netlist using a linear cmos amplifier
***** transient analysis tnom= 25.000 temp= 25.000 *****
falltime= 3.9149E-08 targ= 7.1916E-08
trig= 3.2767E-08
*** HSPICE -- 98.4 (981215) 13:58:43
*** 01/08/1999 solaris ***
* example hspice netlist using a linear cmos amplifier
****** transient analysis tnom= 25.000 temp= 25.000 ******
*** parameter analog_voltage
=
2.000E+00 ***
node
=voltage
node
=voltage
node
=voltage
+0:clamp = 2.6200
0:in
=
0.
0:infilt =
2.6200
+0:inv1out = 2.6200 0:inv2out = 2.6199 0:vdd
=
5.0000
******
* example hspice netlist using a linear cmos amplifier
***** transient analysis tnom= 25.000 temp= 25.000 *****
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falltime= 1.5645E-08 targ= 5.7994E-08
trig= 4.2348E-08
**** HSPICE -98.4 (981215) 13:58:43
**** 01/08/1999 solaris ****
* example hspice netlist using a linear cmos amplifier
***** transient analysis tnom= 25.000 temp= 25.000 *****
*** parameter analog_voltage
=
3.000E+00 ***
node
=voltage
node
=voltage
node
=voltage
+0:clamp =
2.6200 0:in
=
0.
0:infilt =
2.6200
+0:inv1out = 2.6200 0:inv2out = 2.6199 0:vdd
=
5.0000
******
* example hspice netlist using a linear cmos amplifier
***** transient analysis tnom= 25.000 temp= 25.000 *****
falltime= 1.1917E-08 targ= 5.6075E-08
trig= 4.4158E-08
****** HSPICE -- 98.4 (981215) 13:58:43
****** 01/08/1999 solaris ******
* example hspice netlist using a linear cmos amplifier
***** transient analysis tnom= 25.000 temp= 25.000 *****
*** parameter analog_voltage
=
4.000E+00 ***
node
=voltage
node
=voltage
node
=voltage
+0:clamp =
2.6200 0:in
=
0.
0:infilt =
2.6200
+0:inv1out = 2.6200 0:inv2out = 2.6199 0:vdd
=
5.0000
******
* example hspice netlist using a linear cmos amplifier
***** transient analysis tnom= 25.000 temp= 25.000 *****
falltime= 7.5424E-09 targ= 5.3989E-08
trig= 4.6447E-08
****** HSPICE -- 98.4 (981215) 13:58:43
****** 01/08/1999 solaris ******
* example hspice netlist using a linear cmos amplifier
***** transient analysis tnom= 25.000 temp= 25.000 *****
*** parameter analog_voltage
=
5.000E+00 ***
node
=voltage
node
=voltage
node
=voltage
+0:clamp =
2.6200 0:in
=
0.
0:infilt =
2.6200
+0:inv1out = 2.6200 0:inv2out = 2.6199 0:vdd
=
5.0000
******
* example hspice netlist using a linear cmos amplifier
***** transient analysis tnom= 25.000 temp= 25.000 *****
falltime= 6.1706E-09 targ= 5.3242E-08
576
trig= 4.7072E-08
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Simulation Example Using AvanWaves
meas_variable = falltime
mean = 16.0848n
varian = 1.802e-16
sigma = 13.4237n
avgdev =
9.2256n
max
= 39.1488n
min
=
6.1706n
***** job concluded
****** HSPICE -- 98.4 (981215) 13:58:43
****** 01/08/1999 solaris ******
* example hspice netlist using a linear cmos amplifier
*** job statistics summary tnom= 25.000 temp= 25.000 ***
total memory used
155 kbytes
# nodes = 8 # elements= 14
# diodes= 2 # bjts
=
analysis
time
# points
op point
0.04
1
transient
4.71
505
readin
0.03
errchk
0.01
setup
0.01
output
0.01
0 # jfets
= 0 # mosfets = 4
tot. iter
conv.iter
23
9322
2624 rev= 664
total cpu time
4.84 seconds
job started at 13:58:43 01/08/1999
job ended
at 13:58:50 01/08/1999
lic: Release hspice token(s)
HSPICE job example.sp completed.
Fri Jan 8 13:58:50 EST 1999
Example.pa0
1 xinv1.
2 xinv2.
Example.st0
***** HSPICE -98.4 (981215) 13:58:43
***** 01/08/1999 solaris
Input File: example.sp
lic: FLEXlm:v5.12 USER:hspiceuser HOSTNAME:hspiceserv
+ HOSTID:8086420f PID:1459
lic: Using FLEXlm license file:
lic: /afs/rtp/product/distrib/bin/license/license.dat
lic: Checkout hspice; Encryption code: AC34CE559E01F6E05809
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lic: License/Maintenance for hspice will expire on
+ 14-apr-1999/1999.200
lic: 1(in_use)/10 FLOATING license(s) on SERVER hspiceserv
lic:
init: begin read circuit files, cpu clock= 2.21E+00
option probe
option nomod
init: end read circuit files, cpu clock= 2.23E+00
+ memory= 145 kb
init: begin check errors, cpu clock= 2.23E+00
init: end check errors, cpu clock= 2.24E+00 memory= 144 kb
init: begin setup matrix, pivot=
10 cpu clock= 2.24E+00
establish matrix -- done, cpu clock= 2.24E+00 memory= 146 kb
re-order matrix -- done, cpu clock= 2.24E+00 memory= 146 kb
init: end setup matrix, cpu clock= 2.25E+00 memory= 154 kb
sweep: parameter parameter1
begin, #sweeps=
5
parameter: analog_voltage =
1.00E+00
dcop: begin dcop, cpu clock= 2.25E+00
dcop: end dcop, cpu clock= 2.27E+00 memory= 154 kb
tot_iter= 11
output: ./example.mt0
sweep: tran tran1 begin, stop_t= 1.00E-06 #sweeps= 101
cpu clock= 2.28E+00
tran: time= 1.03750E-07 tot_iter= 78
conv_iter= 24
tran: time= 2.03750E-07 tot_iter= 179
conv_iter= 53
tran: time= 3.03750E-07 tot_iter= 280
conv_iter= 82
tran: time= 4.03750E-07 tot_iter= 381
conv_iter= 111
tran: time= 5.03750E-07 tot_iter= 482
conv_iter= 140
tran: time= 6.03750E-07 tot_iter= 583
conv_iter= 169
tran: time= 7.03750E-07 tot_iter= 684
conv_iter= 198
tran: time= 8.03750E-07 tot_iter= 785
conv_iter= 227
tran: time= 9.03750E-07 tot_iter= 886
conv_iter= 256
tran: time= 1.00000E-06 tot_iter= 987
conv_iter= 285
sweep: tran tran1 end, cpu clock= 2.82E+00 memory= 155 kb
parameter: analog_voltage =
2.00E+00
dcop: begin dcop, cpu clock= 2.83E+00
dcop: end dcop, cpu clock= 2.83E+00 memory= 155 kb
+ tot_iter= 14
output: ./example.mt0
sweep: tran tran2 begin, stop_t= 1.00E-06 #sweeps=
+ cpu clock= 2.83E+00
tran: time= 1.01016E-07 tot_iter= 186
conv_iter=
tran: time= 2.02642E-07 tot_iter= 338
conv_iter=
tran: time= 3.01763E-07 tot_iter= 495
conv_iter=
tran: time= 4.04254E-07 tot_iter= 668
conv_iter=
578
101
54
98
145
198
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Simulation Example Using AvanWaves
tran:
tran:
tran:
tran:
tran:
tran:
time=
time=
time=
time=
time=
time=
5.02594E-07
6.10102E-07
7.01850E-07
8.01776E-07
9.04268E-07
1.00000E-06
tot_iter=
tot_iter=
tot_iter=
tot_iter=
tot_iter=
tot_iter=
841
983
1161
1306
1481
1654
conv_iter= 248
conv_iter= 289
conv_iter= 340
conv_iter= 383
conv_iter= 436
conv_iter= 486
sweep: tran tran2 end, cpu clock= 3.71E+00 memory= 155 kb
parameter: analog_voltage =
3.00E+00
dcop: begin dcop, cpu clock= 3.71E+00
dcop: end dcop, cpu clock= 3.72E+00 memory= 155 kb
+ tot_iter= 17
output: ./example.mt0
sweep: tran tran3 begin, stop_t= 1.00E-06 #sweeps= 101
+ cpu clock= 3.72E+00
tran: time= 1.00313E-07 tot_iter= 143
conv_iter= 42
tran: time= 2.01211E-07 tot_iter= 340
conv_iter= 100
tran: time= 3.01801E-07 tot_iter= 539
conv_iter= 156
tran: time= 4.02192E-07 tot_iter= 729
conv_iter= 211
tran: time= 5.01997E-07 tot_iter= 917
conv_iter= 265
tran: time= 6.01801E-07 tot_iter= 1088
conv_iter= 314
tran: time= 7.01801E-07 tot_iter= 1221
conv_iter= 351
tran: time= 8.01801E-07 tot_iter= 1362
conv_iter= 392
tran: time= 9.02387E-07 tot_iter= 1515
conv_iter= 435
tran: time= 1.00000E-06 tot_iter= 1674
conv_iter= 479
sweep: tran tran3 end, cpu clock= 4.57E+00 memory= 155 kb
parameter: analog_voltage =
4.00E+00
dcop: begin dcop, cpu clock= 4.57E+00
output: ./example.mt0
sweep: tran tran4 begin, stop_t= 1.00E-06 #sweeps= 101
+ cpu clock= 4.58E+00
tran: time= 1.00110E-07 tot_iter= 236
conv_iter= 70
tran: time= 2.04376E-07 tot_iter= 475
conv_iter= 139
tran: time= 3.07892E-07 tot_iter= 767
conv_iter= 221
tran: time= 4.01056E-07 tot_iter= 951
conv_iter= 273
tran: time= 5.01086E-07 tot_iter= 1250
conv_iter= 353
tran: time= 6.00965E-07 tot_iter= 1541
conv_iter= 432
tran: time= 7.03668E-07 tot_iter= 1805
conv_iter= 506
tran: time= 8.01114E-07 tot_iter= 2046
conv_iter= 571
tran: time= 9.01005E-07 tot_iter= 2308
conv_iter= 640
tran: time= 1.00000E-06 tot_iter= 2528
conv_iter= 703
sweep: tran tran4 end, cpu clock= 5.83E+00 memory= 155 kb
parameter: analog_voltage =
5.00E+00
dcop: begin dcop, cpu clock= 5.83E+00
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dcop: end dcop, cpu clock= 5.84E+00 memory= 155 kb
+ tot_iter= 23
output: ./example.mt0
sweep: tran tran5 begin, stop_t= 1.00E-06 #sweeps= 101
+ cpu clock= 5.84E+00
tran: time= 1.00195E-07 tot_iter= 176
conv_iter= 47
tran: time= 2.00617E-07 tot_iter= 431
conv_iter= 115
tran: time= 3.00475E-07 tot_iter= 661
conv_iter= 176
tran: time= 4.00719E-07 tot_iter= 914
conv_iter= 246
tran: time= 5.04084E-07 tot_iter= 1157
conv_iter= 311
tran: time= 6.00666E-07 tot_iter= 1347
conv_iter= 363
tran: time= 7.01830E-07 tot_iter= 1623
conv_iter= 435
tran: time= 8.02418E-07 tot_iter= 1900
conv_iter= 514
tran: time= 9.01178E-07 tot_iter= 2161
conv_iter= 585
tran: time= 1.00000E-06 tot_iter= 2410
conv_iter= 650
sweep: tran tran5 end, cpu clock= 7.03E+00 memory= 155 kb
sweep: parameter
parameter
1 end
>info:
***** hspice job concluded
lic: Release hspice token(s)
Simulation Graphical Output in AvanWaves
The plots in Figure 120 through Figure 125 show the six different postprocessor outputs from the simulation of the example netlist. These plots are
postscript output from the actual data in AvanWaves, a Synopsys graphical
waveform viewer.
580
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Simulation Example Using AvanWaves
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Figure 120 Plot of Voltage on Node in
example HSPICE netlist using a linear CMOS amplifier
5
4.5
4
3.5
3
2.5
2
1.5
Voltages
1
650m
0
-650m
-1
-1.5
-2
-2.5
-3
-3.5
-4
-4.5
-5
582
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Simulation Example Using AvanWaves
Figure 121 Plot of Voltage on Node clamp vs. Time
example HSPICE netlist using a linear CMOS amplifier
6
5.5
5
4.5
4
3.5
Voltages
3
2.5
2
1.5
1
500m
0
-500m
-50n
0 50n
250n
150n
300n 350n400n 450n500n 550n600n 650n700n 750n
200n
100n
800n 850n900n 950n
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Figure 122 Plot of Voltage on Node inv1out vs.Time
Voltages
example HSPICE netlist using a linear CMOS amplifier
5.2
5
4.8
4.6
4.4
4.2
4
3.8
3.6
3.4
3.2
3
2.8
2.6
2.4
2.2
2
1.8
1.6
1.4
1.2
1
800m
600m
400m
200m
0
-200m
0
-50n
584
250n
150n
50n
300n 350n 400n 450n500n 550n600n 650n700n 750n
100n
200n
800n 850n
HSPICE® Simulation and Analysis User Guide
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A: Full Simulation Examples
Simulation Example Using AvanWaves
Figure 123 Plot of Voltage on Node inv2out vs. Time
Voltages
example HSPICE netlist using a linear CMOS amplifier
5.2
5
4.8
4.6
4.4
4.2
4
3.8
3.6
3.4
3.2
3
2.8
2.6
2.4
2.2
2
1.8
1.6
1.4
1.2
1
800m
600m
400m
200m
0
-200m
800n
700n
300n
1000n
900n
500n
600n
400n
200n
750n
950n
850n
650n
-50n 0 50n 100n150n
350n
550n
450n
250n
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Figure 124 Plot of Current through Diode dlow vs. Time
example HSPICE netlist using a linear CMOS amplifier
17m
16m
15m
14m
13m
12m
11m
Currents
10m
9m
8m
7m
6m
5m
4m
3m
2m
1m
0
800n
700n
300n
900n
1000n
500n
600n
400n
200n
750n
950n
850n
650n
-50n 0 50n 100n150n
350n
550n
450n
250n
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Simulation Example Using Cosmos-Scope
Figure 125 Plot of Measured Variable falltime vs. Amplifier Input Voltage
example HSPICE netlist using a linear CMOS amplifier
40n
38n
36n
34n
32n
30n
28n
Measure
26n
24n
22n
20n
18n
16n
14n
12n
10n
8n
6n
800m 1 1.2 1.4 1.6 1.8 2 2.2 2.4 2.6 2.8 3 3.2 3.4 3.6 3.8
4 4.2 4.4 4.6 4.8 5
Simulation Example Using Cosmos-Scope
This example demonstrates the basic steps to perform simulation output and to
view the waveform results by using the Synopsys CosmosScope Waveform
Viewer.
Input Netlist and Circuit
The following example of an HSPICE netlist shows the input netlist for a BJT
diff amplifier. Comment lines indicate the individual sections of the netlists. See
the HSPICE Command Reference manual for information about individual
commands.
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*file: bjtdiff.sp bjt diff amp with every analysis type
*# ANALYSIS: ac dc tran tf noise new four sens pz disto temp
*# OPTIONS: list node ingold=2 measdgt=5 numdgt=8
+ probe post
*# TEMPERATURE: 25
* netlist options
.OPTION list node ingold=2 measdgt=6 numdgt=8 probe post
* defined parameters
.PARAM rb1x=aunif(20k,1k,30k) rb2x=aunif(20k,1k,30k)
* analysis specifications
.TF v(5) vin
.DC vin -0.20 0.20 0.01 sweep monte=3
.AC dec 10 100k 10meghz
.NOISE v(4) vin 20
.NET v(5) vin rout=10k
.PZ v(5) vin
.DISTRO rc1 20 .9 1m 1.0
.SENS v(4)
.TRAN 5ns 200ns
.FOUR 5meg v(5) v(15)
.TEMP -55 150
* output specifications
.MEAS qa_propdly trig v(1) val=0.09 rise=1
+
targ v(5) val=6.8 rise=1
.MEAS qa_magnitude max v(5)
.MEAS qa_rmspower rms power
.MEAS qa_avgv5
avg v(5)
.MEAS ac qa_bandwidth trig at=100k targ vdb(5) val=36 fall=1
.MEAS ac qa_phase find vp(5) when vm(5)=52.12
.MEAS ac qa_freq when vm(5)=52.12
.PROBE dc v(4) v(5) v(14) v(15)
.PROBE ac vm(5) vp(5) vm(15) vp(15)
.PROBE ac vt(5) vt(15)
.PROBE noise onoise(m) inoise(m)
.PROBE ac z11(m) z12(m) z22(m) zin(m)
.PROBE disto hd2 hd3 sim2 dim2 dim3
.PROBE tran v(4) v(5) v(14) v(15)
.PROBE tran p(vcc) p(vee) p(vin) power
* source statements
VIN 1 0 sin(0 0.1 5meg) ac 1
VCC 8 0 12
VEE 9 0 -12
* circuit statements
q1
4 2 6 qnl
q11 14 12 16 qpl
q2
5 3 6 qnl
q21 15 13 16 qpl
rs1
1 2 1k
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Simulation Example Using Cosmos-Scope
rs11 1 12 1k
rs2
3 0 1k
rs12 13 0 1k
rc1
4 8 10k
rc11 14 9 10k
rc2
5 8 10k
rc12 15 9 10k
q3
6 7 9 qnl
q13 16 17 8 qpl
q4
7 7 9 qnl
q14 17 17 8 qpl
rb1
7 8 rb1x
rb2 17 9 rb2x
* model definitions
.MODEL qnl npn(bf=80 rb=100 ccs=2pf tf=0.3ns tr=6ns cje=3pf
+ cjc=2pf va=50 rc=10 trb=.005 trc=.005)
.MODEL qpl pnp(bf=80 rb=100 ccs=2pf tf=0.3ns tr=6ns cje=3pf
+ cjc=2pf va=50 bulk=0 rc=10)
.END
You can find the complete sample netlist for this example in the following
directory:
$installdir/demo/hspice/apps/bjtdiff.sp
Use the previous example (linear CMOS amp) to draw a circuit diagram for this
BJT diff amplifier. Also, specify parameter values.
Execution and Output Files
This section displays the various output files from a HSPICE simulation of the
BJT diff amplifier example. To execute the simulation, enter:
hspice bjtdiff.sp > bjtdiff.lis
where the input file is bjtdiff.sp, and the output file is bjtdiff.lis.
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Simulation creates the following output files:
Table 65
Output Files
File Name
Description
bjtdiff.ic
Initial conditions for the circuit.
bjtdiff.lis
Text simulation output listing.
bjtdiff.mt0
Post-processor output for .MEASURE statements.
bjtdiff.st0
Run-time statistics.
bjtdiff.tr0
Post-processor output for transient analysis.
bjtdiff.sw0
Post-processor output for DC analysis.
bjtdiff.ac0
Post-processor output for AC analysis.
bjtdiff.ma0
Post-processor output for AC analysis measurements.
View HSPICE Results in Cosmos-Scope
The steps below show how to use the Synopsys Cosmos-Scope Waveform
Viewer to view the results of AC, DC, and transient analysis from the BJT diff
amplifier simulation. Refer to previous examples of .lis, .ic, and .st0 files.
Viewing HSPICE Transient Analysis Waveforms
1. Invoke Cosmos-Scope.
From a Unix command line, type:
% cscope
On a Windows-NT system, choose the menu command:
Programs > (user_install_location)> Cosmos-Scope
2. Open the Open Plotfiles dialog box:
File > Open > Plotfiles
3. In the Open Plotfiles dialog box, in the Files of Type fields, select the Hspice
Transient (*.tr*) item.
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4. In the menu, click on bjtdiff.tr0, and click Open.
The Signal Manager and the bjtdiff Plot File windows open.
5. Hold down the Ctrl key, and select the v(4), v(5), and ITPOWERD(power)
signals.
6. Click on Plot from the bjtdiff Plot File window.
Three cascaded plots open.
7. To see three signals in one plot, right-click on the top-most signal name.
The Signal Menu opens.
8. From the Signal Menu, select Stack Region > Analog 0.
9. Repeat Step 7 for the next topmost signal.
A plot opens similar the one shown in Figure 126 on page 592.
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Figure 126 Transient Analysis: Plot of v(4), v(5), and ITPOWERD (power)
Graph1
8.0
(TPOWRD)>t(s)
0.1208
(v):t(s)
v(4)
0.1207
7.0
v(5)
0.1206
(V)
6.0
5.0
(TPOWRD)
0.1205
0.1204
0.1203
0.1202
4.0
0.1201
0.12
3.0
0.1199
0.0
25n
50n
75n
100n
125n
t(s)
150n
175n
200n
225n
Viewing HSPICE AC Analysis Waveforms
1. From the Signal Manager dialog box, select bjtdiff(1), and click on Close
Plotfiles.
All transient plots (waveforms) close.
2. In the Signal Manager, click on Open Plotfiles.
3. In the Open Plotfiles dialog box, in the Files of Type fields, select the
HSPICE AC (*.ac*) item.
4. Click on bjtdiff.ac0 in the menu, and click Open.
The bjtdiff Plot File windows open.
5. Hold down the Ctrl key, and select the dim2(mag) and dim3(mag) signals.
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6. Click on Plot from the bjtdiff Plot File window.
Two cascaded plots open.
7. For two signals in a plot, right-click on dim2(mag).
A Signal Menu opens.
8. From the Signal Menu, select Stack Region > Analog 0.
A plot opens similar to Figure 127.
Figure 127 AC Analysis Result: Plot of dim2(mag), dim3(mag) from bjtdiff.ac0
0.071
(DIM2):Frequency(Hertz)
Graph2
0.02
dim2(meg)
0.07075 0.018
Frequency (Hertz
dim3(meg)
0.0705
(DIM3):Frequency
(Hertz)
0.016
0.07025
0.014
0.07
0.012
0.06975
0.01
0.0695
0.008
0.06925
0.006
0.069
0.06875
0.004
0.0685 0.002
0.0
0.0
(DIM2)
(DIM3)
0.06825
1meg
2meg
3meg
4meg 5meg 6meg
Frequency (Hertz)
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7meg
8meg
9meg
10meg
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Viewing HSPICE DC Analysis Waveforms
1. From the Signal Manager dialog box, select bjtdiff(1), and click on Close
Plotfiles.
All AC plots (waveforms) close.
2. In the Signal Manager, click on Open Plotfiles.
3. In the Open Plotfiles dialog, Files of Type field, select HSPICE DC (*.sw*).
4. Click on bjtdiff.sw0 and Open in the menu.
The Plot File windows open.
5. Hold down the Ctrl key and select all signals.
6. Click on Plot from the bjtdiff Plot File window.
Four cascaded plots open.
7. To see four signals in one plot, right-click on the name of the top-most signal.
A Signal Menu opens.
8. From the Signal Menu, select Stack Region > Analog 0.
9. Repeat Steps 7 and 8 for the next two top-most signals.
A plot opens similar to the one shown in Figure 128 on page 595.
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Figure 128 DC Analysis Result: Plot of v(14), v(15), v(4), and v(5) from
bjtdiff.sw0
(V): Voltage K(Volt)
v(14)
Graph3
15.0
v(15)
v(4)
10.0
v(5)
(V)
5.0
0.0
-5.0
-10.0
-15.0
-0.25
-0.2
-0.15
-0.1
-0.05
0.0
0.05
Voltages K(volt)
0.1
0.15
0.2
0.25
The Cosmos-Scope User’s and Reference Manual includes a full tutorial,
information about the various Scope tools, and reference information about the
Measure tool. You can also find more information on the Synopsys website:
http:// www.synopsys.com
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Index
Symbols
!GND node 54
$installdir installation directory 67
A
A2D
function 200
model parameter 200
output model parameters 204
See also mixed mode
.a2d file 16, 18, 200
ABS element parameter 196
abs(x) function 228
ABSI option 327
ABSMOS option 327
absolute
power function 228
value function 228
value parameter 196
ABSV option 327
ABSVAR option 356
AC analysis 243
output 260
RC network 382
resistance 381
small signals 380
sources 130
AC analysis measurement results file 17
AC analysis results file 17
.AC statement 483, 515
.ac# file 16, 17
accuracy
control options 328
simulation time 327
tolerance 325, 326, 354
ACCURATE option 356
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ACM model parameter 356
acos(x) function 227
ACOUT option 262–263
adder
circuit 536
demo 535
NAND gate binary 536
subcircuit 535
admittance
AC input 266
AC output 266
Y parameters 260
AF model parameter 386
AGAUSS keyword 493
algebraic
expressions 226
models 356
algorithm
linear acceleration 358
numerical integration 366
algorithms
Damped Pseudo Transient algorithm 335
DVDT 367, 368
GEAR 363
integration 363
iteration count 367
Levenberg-Marquardt 521
local truncation error 367, 368
timestep control 366, 367, 369
trapezoidal integration 363
.ALTER
blocks 59–60
statement 60, 61, 249
AM
source function 151, 151
analog transition data file 15
analysis
AC 243
597
Index
B
accuracy 325–327
data driven 480, 481
DC 243
element template 243
Fourier 375
initialization 316
inverter 348
.MEASURE statement 243
Monte Carlo 481, 489, 489–509
optimization 515
parametric 243
POWER_ANALYSIS option 291
RC network 347, 382
statistical 484–509
Taguchi 480
temperature 480, 483
transient 243, 344
worst case 480, 484–509
yield 480
arccos(x) function 227
arcsin(x) function 227
arctan(x) function 228
arguments, command line 28, 30
arithmetic operators 227
ASCII output 28
ASIC libraries 68
asin(x) function 227
atan(x) function 228
ATEM characterization system 67
AUNIF keyword 493
autoconvergence 330
AUTOSTOP option 354
average deviation 481
average value, measuring 271
B
-b argument 23
B# node name in CSOS 55
backslash continuation character 227
Backward-Euler
algorithm 366
integration 366
behavioral
current source 188
voltage source 176
Behavioral capacitors 83
598
Behavioral resistors 75
Biaschk 350
Bipolar Junction Transistors. See BJTs
BJTs
current flow 255
element template listings 300
elements, names 97
power dissipation 258
S-parameters, optimization 525
bond wire example 541
branch current
output 253
breakpoint table
reducing size 371
buffer 123
C
C Element (capacitor) 80
capacitance
element parameter 77
manufacturing variations 499
capacitor
conductance requirement 334
current flow 254
element 77, 80, 296
frequency-dependent 81
linear 80
models 77
voltage controlled 189, 193
CAPOP model parameter 356
CCCS element parameter 182
CCVS element parameter 195, 196
cell characterization 480
characterization of models 323
.CHECK statements 275–281
CHGTOL option 368
circuits
adder 536
description syntax 45
inverter, MOS 349
nonconvergent 338
RC network 383
reusable 63
subcircuit numbers 54
temperature 483
See also subcircuits
CLOAD model parameter 204
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Index
D
CMOS
output driver demo 541
tristate buffer, optimization 523
command-line arguments
HSPICE 22
HSPICE RF 28
commands
Hspice 22–27
limit descriptors 249
output 241
comment line
netlist 47
VEC files 216
common emitter gain 548
compression of input files 35
conductance
for capacitors 334
pn junction 341
configuration file 14
continuation character, parameter strings 227
continuation of line
netlist 47
control options
accuracy 328
defaults 369
algorithm selection 324
convergence 324, 328
DC convergence 325
initialization 324
method 353
printing 249
transient analysis
method 353–354
controlled sources 162, 164
CONVERGE option 329, 335
convergence
control options 328
problems 335
analyzing 336
autoconverge process 330
causes 338
CONVERGE option 335
DCON setting 330
diagnosing 335–341
diagnostic tables 336
floating point overflow 335
GMINDC ramping 330
.NODESET statement 321
reducing 332
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cos(x) function 227
cosh(x) function 228
current
branch 254
controlled
current sources 163, 182, 298
voltage sources 163, 195, 298
in HSPICE elements 254
output 252
sources 186
C-V plots 537
D
-d argument 23
D2A
function 200
input model parameters 201
model parameter 200
See also mixed mode
.d2a file 200
Damped Pseudo Transient algorithm 335
data
flow, overview 7
.DATA statement 56
data-driven analysis 56
data-driven analysis 480, 481
PWL source function 148
db(x) function 229
DC
analysis 243, 324–325
capacitor conductances 334
initialization 324
convergence control options 324, 325
errors, reducing 332
operating point
analysis 319
bypassing 345
initial conditions file 15
See also operating point
sources 129
sweep 323
DC analysis measurement results file 18
DC analysis results file 18
DC initialization control options 325
.DC statement 323, 483, 515
DCCAP option 537
.DCMATCH output tables file 21
599
Index
D
DCON option 329, 330
DCSTEP option 334
.DCVOLT statement 321
DDL 67, 68, 548
DDLPATH environment variable 68, 548
decibel function 229
DEFAULT_INCLUDE variable 14
DEFW option 235
.DEL LIB statement 43
in .ALTER blocks 59
with .ALTER 61
with .LIB 61
with multiple .ALTER statements 60
DELAY element parameter 190, 196
delays
element example 194
group 265
time (TD) 265
DELMAX option 355, 356, 370, 376
DELTA
element parameter 191, 196
DELVTO model parameter 485
demo files
2n2222 BJTs transistor characterization 561
2n3330 JFETs transistor characterization 561
A/D flash converter 557
A2D 557
AC analysis 553
acl gate 554
adders
72-transistor two-bit 555
BJT NAND gate two-bit 554
BJT two-bit 553
D2A 557
MOS two-bit 554
NAND gate four-bit binary 553
air core transformer 564
algebraic
output variables 552–553
parameters 552
transmission lines 568
.ALTER statement 553
AM source 567
amplifier 557
amplitude modulator 554
analog 556
AND gate 554
automatic model selection program 565
600
behavioral applications 554–555
behavioral models 556
diode 554
D-latch 554
filter 552
NAND gate 555
ring oscillator 555
triode 555
voltage to frequency converter 552
benchmarks 555–556
bisection 556
BJTs
analog circuit 556
beta plot 556
differential amplifier 553, 557
diodes 556
ft plot 556
gm, gpi plots 556
photocurrent 567
Schmidt trigger 553
sense amplifier 553
BSIM3 model, LEVEL=47 564
capacitances, MOS models
LEVEL=13 564
LEVEL=2 564
LEVEL=6 564
cell characterization 553, 554, 556–557
charge conservation, MOS models
LEVEL=3 564
LEVEL=6 565
circuit optimization 557
CMOS
differential amplifier 553
I/O driver ground bounce 553, 568
input buffer 557
inverter macro 555
output buffer 557
coax transmission line 568
crystal oscillator 553
current controlled
current source 555
voltage source 555
D2A 557
DC analysis, MOS model LEVEL=34 565
DDL 557–561
delay 553, 556, 557
device optimization 561–562
differential amplifier 553
differentiator 554
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Index
D
diffusion effects 553
diode photocurrent 566
D-latch 554
E Element 554
edge triggered flip-flop 554
exponential source 567
FFT
AM source 562
analysis 562–563
Bartlett window 562
Blackman window 562
Blackman-Harris window 562
data-driven transient analysis 562
exponential source 562
Gaussian window 562
Hamming window 562
Hanning window 562
harmonic distortion 562
high frequency detection 562
intermodulation distortion 562
Kaiser window 563
modulated pulse source 563
Monte Carlo, Gaussian distribution 562
product of waveforms 562
pulse source 563
PWL 563
rectangular window 563
single-frequency FM source 563
sinusoidal source 562
small-signal distortion 562
switched capacitor 563
transient 562
window tests 563
filter matching 557
filters 563–564
behavioral 552
fifth-order 555, 563
fourth-order Butterworth 563
Kerwin’s circuit 563
LCR bandpass 563
matching lossy to ideal 557
ninth-order low-pass 554, 563
switched capacitor low-pass 554
FR-4 microstrip transmission line 564, 568
G Element 553, 554
GaAsFET amplifier 553
gamma model LEVEL=6 565
general applications 553–554
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ground bounce 553, 568
group time delay 553
impact ionization plot 564
input 552
installation test 555
integrator 554
inverter 553, 554, 555, 556
characterization 556
IRF340 NMOS transistor characterization 561
I-V plots
LEVEL=3 565
MOSFETS model LEVEL=13 565
SOSFETS model LEVEL=27 565
JFETs photocurrent 567
junction tunnel diode 556
LCR circuit 557
lumped
MOS model 553
transmission lines 564, 568
magnetic core transformer 564
magnetics 564
microstrip transmission lines 564, 568
coupled 568
optimization 568
series 568
Monte Carlo analysis 553
Gaussian distribution 553
limit function 553
uniform distribution 553
MOS 555, 557
MOSFETs 564–565
sigma sweep 557
sweep 553
NAND gate 554, 555
NMOS E-mode model, LEVEL=8 567
noise analysis 553
op-amp 553, 554
characterization 558–560
voltage follower 555, 567
optimization 554
2n3947 Gummel model 562
DC 561
diode 561
GaAs 561
group delay 557
Hfe 561
I-V 561
JFETs 561
LEVEL=2 model beta 561
601
Index
D
LEVEL=28 561
MOS 561
s-parameter 561
speed, power, area 557
width 557
parameters 552
phase
detector 554
locked loop 554
photocurrent 565–567
GaAs device 567
photolithographic effects 553
pll 554
pole/zero analysis 553, 563
pulse source 567
PWL 567
CCCS 555
CCVS 555
switch element 555
VCCS 554, 555
VCO 555
VCVS 555
radiation effects 565–567
bipolar devices 565–566
DC I-V, JFETs 567
GaAs differential amplifier 567
JFETs devices 566
MOSFETs devices 566
NMOS 567
RC circuit optimization 557
resistor temperature coefficients 557
RG58/AU coax test 564
ring oscillator 555
Royer magnetic core oscillator 564
Schmidt trigger 553
sense amplifier 553
series source coupled transmission lines 568
setup 556
characterization 557
shunt terminated transmission lines 568
silicon controlled rectifier 555
sine wave sampling 554, 555
single-frequency FM source 567
sinusoidal source 567
skew models 554
SNAP to HSPICE conversion 556
sources 567
s-parameters 556, 563, 565
602
sweep 553
switch 554
switched capacitor 554, 555, 567
temperature effects
LEVEL=13 565
LEVEL=6 564
timing analysis 556
total radiation dose 566
transient analysis 553
transistor characterization 561
transmission lines 568
triode model 555
tunnel diodes 555, 556
twinlead transmission line model 568
U models 568
unity gain frequency 557
verilog-a 569
Viewsim
A2D input 557
D2A input 557
voltage follower 555
voltage-controlled
current source 554, 555
oscillator 552, 555
resistor inverter 567
voltage source 555
voltage-to-frequency converter 552
voltage-variable capacitor 554
waveform smoothing 555
worst case skew model 554
derivative, measuring 271
design
name 13
Detailed Standard Parasitic Format See DSPF
deviation, average 481
device characterization 67
diagnostic tables 336–337
digital
files 199
vector file 208
digital output file 18
digital vector file
Waveform Characteristics section 214
DIM2
parameter 266
DIM3
parameter 266
diodes
breakdown example 194
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Index
E
current flow 255
elements 299
equations 194
junction 96
models 95
polysilicon capacitor length 96
power dissipation 257
directories
installation directory 67
TEMP 25
TMP 25
tmp 24
distortion 266
.dm# file 21
.DOUT statement 211
.dp# file 16
DSPF
expansion 282, 284
selective 285
file
structure 283
use requirements 284
flow, selective 285
multiple active thresholds 286
utility
INE 284
DTEMP parameter 482, 483, 547
DV option 330
DVDT
algorithm 363, 367
option 355, 367, 368, 369
dynamic timestep algorithm 368
E
E Elements
applications 163
element multiplier 178
syntax statements 171
temperature coefficients 178
time delay keyword 178
edge condition 278
electrical measurements 548
element
active
BJTs 97
diodes 95
JFETs 100
MESFETs 100
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MOSFETs 102
C (capacitor) 80
IC parameter 320
identifiers 39
independent source 125, 135
L (inductor) 92
markers, mutual inductors 88
names 53
OFF parameter 318
parameters See element parameters 71
passive
capacitors 77
inductor 85
mutual inductor 88
resistors 71
R (resistor) 74
statements 48, 67
current output 253
independent sources 126
Laplace 173
pole/zero 174
temperature 483
templates 267–296
analysis 243
BJTs 300
capacitor 296
current-controlled 298
function 230
independent 299
inductor 296
JFETs 302
MOSFETs 303
mutual inductor 297
resistor 296
saturable core 307
voltage-controlled 297, 298
transmission line 106, 110, 114
voltage-controlled 162
element parameters
.ALTER blocks 59
BJTs 97–98
capacitors 77–79
DTEMP 482
F Elements 182–185
G Elements 186–193
H Elements 196–198
IBIS buffers 123
independent sources 126–127
603
Index
F
data driven PWL function 147
PULSE function 136, 139, 142, 145
SFFM function 149
inductors 86–87
JFETs and MESFETs 100–101
linear inductors 86
MOSFETs 102–104
mutual inductors, Kxxx 88
POLY 164
PWL 145, 148
resistors 72–73
transmission lines
T Element 111
U Element 114
W Element 107, 107–108
.END statement
for multiple HSPICE runs 61
in libraries 57
location 61
missing 36
with .ALTER 60
.ENDL statement 57
environment variables 11, 68, 548
LM_LICENSE_FILE 11
META_QUEUE 11, 12
[email protected] 12
TEMP 25
TMP 25
tmpdir 24
equations 271, 273
ERR function 272, 273
ERR1 function 273, 512
ERR2 function 273
ERR3 function 274
errors
cannot open
output spool file 249
DC 332
digital file has blank first line 200
file open 25
functions 272–274
internal timestep too small 319, 339, 345
missing .END statement 36
no DC path to ground 334
no input data 24
parameter name conflict 270
system resource inaccessible 249
example
604
AC analysis 262, 382
comment line 47
digital vector file 218
DSPF selective flow 285
experiments 7
HSPICE vs. SPICE methods 262
Monte Carlo 495, 502
network analysis, bipolar transistor 423
optimization 515
.OPTION (various) See individual option listings
slew rate 278
transient analysis 347, 348
worst case 502
EXP source function
fall time 142
initial value 142
pulsed value 142
rise time 142
exp(x) function 228
experiment 7
exponential function 142, 228
expressions, algebraic 226
external data files 44
F
F Elements
applications 163
multiply parameter 184
syntax statements 182
time delay keyword 185
value multiplier 184
fall time
EXP source function 142
verification 276
FAST option 354
FFT analysis graph data file 18
file
analog transition data 15
DC operating point initial conditions 15
initialization 14
input netlist 15
library input 15
output configuration 14
file descriptors limit 249
files
.a2d 16, 200
AC analysis measurement results 17
AC analysis results 17
HSPICE® Simulation and Analysis User Guide
X-2005.09
Index
G
.ac# 16
.d2a 200
DC analysis measurement results 18
DC analysis results 18
digital output 18
external data 44, 56
FFT analysis graph data 18, 21
.ft# 16
.gr# 16
graph data 9
hardcopy graph data 18
HBLSP analysis extraction results 18
HBLSP analysis print information 19
HBLSP analysis results 19
hspice.ini 67
.ic 16, 318
include files 43
including 14
input 9, 22
limit on number 249
.lis 17
.ls# 16, 19
.ma# 16
.ms# 16
.mt# 17
multiple simulation runs 61
names 13, ??–23
operating point node voltages 19
output
listing 20
status 20
version number 22
.p2d# 16, 18
.pa# 17
.printls# 16
.printss# 16
scratch files 24, 25
.ss# 16
.ss# file 19
.st# 17
subcircuit cross-listing 21
.sw# 16
.tr# 17
transient analysis measurement results 19, 21
transient analysis results 21
files, output 16
FIND keyword 271
first character descriptions 38
HSPICE® Simulation and Analysis User Guide
X-2005.09
flags, command line 28, 30
format
output 292
DSPF 282, 283
NW 310
WDB 310
Fourier
analysis 375
coefficients 376
equation 376
FREQ
function 175
model parameter 246
frequency
response
table 175, 188
variable 232
frequency-dependent
capacitor 81
inductor 93
FS option 370
FT option 369, 370
.ft# file 16, 18
functions
A2D 200
built-in 227–231
D2A 200
DERIVATIVE 272
ERR 272
INTEG 272
LAPLACE 173, 187
NPWL 190
POLE 174, 188
PPWL 190
table 227
See also independent sources
G
G Elements
applications 163
controlling voltages 191, 193
current 191
curve smoothing 192
element value multiplier 192
gate type 191
initial conditions 191
multiply parameter 191
names 191
605
Index
H
polynomial 192
resistance 191
syntax statements 186
time delay keyword 192
transconductance 192
voltage to resistance factor 192
GaAsFET model DC optimization 529
gain, calculating 262
GAUSS
functions 496
keyword 493
parameter distribution 489
GEAR algorithm 363
global parameters 233
GLOBAL_LEVEL, .CHECK statement 275
GMIN option 341
GMINDC option 330, 341
GND node 54
GOAL keyword 513
.gr# file 16, 18
GRAMP
option 330, 333
.GRAPH statement 242, 246, 249, 537
ground bounce checking 281
ground, node name 54
Gxxx element parameters 191
H
-h argument
usage information 29
H Elements
applications 163
controlling voltage 198
data points 197
element multiplier 198
element name 197
gate type 197
initial conditions 197
maximum current 197
minimum current 197
syntax statements 195
time delay keyword 198
transresistance 198
H parameters 422
hardcopy graph data file 18
HBLSP analysis extraction results file 18
606
HBLSP analysis print information 19
HBLSP analysis results file 19
HD2 distortion 266
HD3 distortion 266
hertz variable 232
hierarchical designs, flattened 43
hold time verification 279
HOLD, .CHECK statement 279
HSPICE
installation directory 67
starting 24
version
95.3 compatibility 369
hspice command 22–27
hspice.ini file 67
-html argument 23
hybrid (H) parameters 260
I
-I argument 23
-i argument 22
IBIS buffers 123
.ic file 16, 318
IC parameter 191, 197, 320, 321
.IC statement 316, 318, 321
from .SAVE 322
.ic# file 19
ideal
current sources 333
delay elements 163, 356
op-amp 163, 176, 179
transformer 163, 176, 181
IDELAY statement 214
imaginary
part of AC voltage 262–263
impedance
AC 266
Z parameters 260
include files 14
.INCLUDE statement 43, 60, 68, 69
independent sources
AC 126, 130
AM function 151
current 126, 299
data driven PWL function 147
DC 126, 129
HSPICE® Simulation and Analysis User Guide
X-2005.09
Index
J
elements 126
EXP function 142
functions 135
mixed types 130
PULSE function 135
PWL function 145
SFFM function 149
SIN function 139
transient 126, 130
types 135
voltage 126, 299
See also sources
individual element temperature 483
inductor
frequency-dependent 93
inductors
current flow 254
element 85, 296
node names 86
initial conditions 317
file 15
statement 321
initialization 316, 318
file 14
saved operating point 322
initialization file 14
INOISE parameter 266
input
admittance 266
analog transition data file 15
data
adding library data 61
for data driven analysis 56
DC operating point initial conditions file 15
files
analog transition data 15
character case 36
compression 35
DC operating point 15
demonstration 552
initialization 14
library 15
names 13, 22
netlist 15, 35
output configuration file 14
structure 43
table of components 44
impedance 266
initialization file 14
HSPICE® Simulation and Analysis User Guide
X-2005.09
library file 15
netlist 45
netlist file
See also input files
15, 45–61, 571
output configuration file 14
input netlist file 15
input stimuli 287
input/output
cell modeling 549
installation directory $installdir 67
int(x) function 229
integer function 229
integration
algorithms 363
interfaces
AvanWaves 241
internal
nodes, referencing 54
interstage gain 262
inverter
analysis, transient 348
circuit, MOS 349
invoking
HSPICE RF 28
IR drop
checking 281
iterations
algorithm 365
count algorithm 367
number 522
I-V and C-V plotting demo 536
J
JFETs
current flow 255
elements 100, 302
length 100
power dissipation 259
width 100
K
keywords
analysis statement syntax 515
DTEMP 482
ERR1 512
GOAL 513
LAST 271
607
Index
L
MONTE 490
optimization syntax 514
PAR 227
power output 257
PP 272
source functions 126
KF model parameter 386
L
L Element (inductor) 92
Laplace
function 173, 187
transform 173, 187
frequency 175, 188
LAST keyword 271
leadframe example 541
LENGTH model parameter 498
Levenberg-Marquardt algorithm 521
.LIB
call statement 57
statement 43, 69
in .ALTER blocks 57, 59
with .DEL LIB 61
with multiple .ALTER statements 60
libraries
adding with .LIB 61
ASIC cells 68
building 57
configuring 235
creating parameters 233
DDL 67
duplicated parameter names 233
.END statement 57
integrity 233
search 68
selecting 58
subcircuits 69
vendor 68
library input file 15
limit descriptors command 249
LIMIT keyword 493
line 94
line continuation
VEC files 216
linear
acceleration 357–??
capacitor 80
608
inductor 92
matrix reduction 357
resistor 74
.lis file 17, 20
LM_LICENSE_FILE environment variable 11
LMAX model parameter 5
LMIN model parameter 5
.LOAD statement 321
local
parameters 233
truncation error algorithm 367, 368
log(x) function 228
log10(x) function 228
logarithm function 228
.ls# file 16, 19
LV 267, 268
LV18 model parameter 537
LVLTIM option 356, 367, 369
LX 268
LX7 model parameter 537
LX8 model parameter 537
LX9 model parameter 537
M
M element parameter 184, 191
.ma# file 16, 17
macros 61
magnitude
AC voltage 263
magnitude, AC voltage 260, 262, 263
manufacturing tolerances 497
Marquardt scaling parameter 521
MAX parameter 191, 197
max(x,y) function 229
maximum value, measuring 271
mean, statistical 481
.MEASURE statement 242, 243, 270
expression 271
failure message 269
parameters 226
measuring parameter types 269
MESFETs 100
META_QUEUE environment variable 11, 12
Meyer and Charge Conservation parameters 305
MIN parameter 191, 197
HSPICE® Simulation and Analysis User Guide
X-2005.09
Index
N
min(x,y) function 229
minimum
value, measuring 271
mixed mode
See also D2A, A2D
mixed sources 130
MODEL keyword 515
model parameters
A2D 200
.ALTER blocks 59
capacitance distribution 499
D2A 200, 201–202
DELVTO 485
DTEMP 483
.GRAPH statement parameters 246
LENGTH 498
manufacturing tolerances 497
MONO 246
output 246
PHOTO 498
RSH 485
sigma deviations, worst case analysis 485
skew 484
TEMP 56, 483
temperature analysis 483
TIC 246
TOX 485
TREF 481, 483, 484
XPHOTO 498
model parameters See model parameters diodes
.MODEL statement 483
for .GRAPH 246
models
algebraic 356
characterization 323
DTEMP parameter 547
LV18 537
LX7, LX8, LX9 537
Monte Carlo analysis 489, 494, 502
reference temperature 483
specifying 68
typical set 488
MONO model parameter 246
Monte Carlo
analysis 480, 481, 502–509
demo files 553
distribution options 492–493
MONTE keyword 490
MOS
HSPICE® Simulation and Analysis User Guide
X-2005.09
inverter circuit 349
op-amp optimization 530
MOSFETs
current flow 256
drain diffusion area 102
elements 102, 303
initial conditions 103
node names 102
perimeter 103
power dissipation 259
source 103, 104
squares 103
temperature differential 103
zero-bias voltage threshold shift 104
.ms# file 16, 18
-mt argument 23
.mt# file 17, 19, 21
multiple .ALTER statements 60
multiply parameter 64, 73, 127
multipoint experiment 7
multithreading 29
mutual inductor 88, 297
N
-n argument 22
NAND gate adder 536
natural
log function 228
NDIM 164
.NET parameter analysis 420
netlist 43
file example 46
flat 43
input files 35
schematic 43
structure 45
netlist file
example 46
network output 265, 424
nodal voltage output 252, 262
nodes
connection requirements 54
floating supply 54
internal 54
MOSFET’s substrate 54
names 50, 53, 55, 537
automatic generation 55
609
Index
O
ground node 54
period in 51
subcircuits 53, 54
zeros in 55
numbers 50, 53
phase or magnitude difference 262
shorted 334
terminators 54
.NODESET statement 316
DC operating point initialization 321
from .SAVE 322
noise
calculations 385
input 266
output 266, 386
norm of the gradient 521
NPDELAY element parameter 197
NPWL function 190
numerical integration 366
NW
output format 310
O
-o argument 22
ODELAY statement 214
OFF parameter 318
one-dimensional function 164
ONOISE parameter 266
.OP statement 318, 319, 345
op-amps
open loops 333
optimization 530
operating point
estimate 318, 345
.IC statement initialization 321
initial conditions 15
.NODESET statement initialization 321
restoring 323
saving 55, 322
solution 317, 318
transient 345
operating point information file 19
operating point node voltages file 19
operators 227
OPT keyword 514
optimization
AC analysis 526
610
analysis statements 515
CMOS tristate buffer 523
control 511
convergence options 512
curve-fit 512
cv 561
data-driven vs. s-parameters 526
DC analysis 516, 519, 527, 529
example 515, 551
goal 513
incremental 527
lengths and widths 531
MODEL keyword 515
MOS 518, 530
network 520, 526
parameters 526
magnitude and phase 526
measured vs. calculated 526
results
function evaluations 522
iterations 522
Marquadt scaling parameter 521
norm of the gradient 521
residual sum of squares 521
S parameters 525
simulation accuracy 512
simultaneous 523, 529, 531
statements 514
syntax 514
time
analysis 513
required 511
OPTIMIZE keyword 514
.OPTION
ACCT, for accounting reports 249
.ALTER blocks 59
CO, for column width 249
DCSTEP 334
INGOLD, for exponential output 249
MAXORD 373
METHOD 372
POST
example 313
POST, for displaying AvanWaves plots 249
POWER_ANALYSIS 291
POWER_TOP 290
PURETP 373
SIM_ACCURACY 345, 371
SIM_ACTIVE 283, 285
HSPICE® Simulation and Analysis User Guide
X-2005.09
Index
O
SIM_ANALOG 94
SIM_DSPF 282, 284
SIM_DSPF_ACTIVE 285
SIM_DSPF_VTOL 285
SIM_LA 283, 359
SIM_LA_FREQ 361
SIM_LA_MAXR 360
SIM_LA_MINC 360
SIM_LA_MINMODE 362
SIM_LA_TIME 361
SIM_LA_TOL 360
SIM_ORDER 373
SIM_OSC_DETECT_TOL 373
SIM_POSTAT 312
SIM_POSTDOWN 313
SIM_POSTSCOPE 313
SIM_POSTSKIP 312
SIM_POSTTOP 312
SIM_POWERPOST 290
SIM_RAIL 94
SIM_TG_THETA 373
SIM_TRAP 373
.OPTIONS
POWER_ANALYSIS 291
OPTxxx parameter 512, 514
oscillators
DELMAX option setting 356
output
AC analysis measurement results file 17
AC analysis results file 17
admittance 266
ASCII 28
commands 241
current 253
data, redirecting 23
DC analysis measurement results file 18
DC analysis results file 18
.DCMATCH output tables file 21
digital output file 18
driver example 541
FFT analysis graph data file 18
files
AC analysis measurement results 17
AC analysis results 17
DC analysis measurement results 18
DC analysis results 18
.DCMATCH output tables file 21
digital output 18
FFT analysis graph data 18
HSPICE® Simulation and Analysis User Guide
X-2005.09
hardcopy data 18
HBLSP analysis extraction results 18
HBLSP analysis print information 19
HBLSP analysis results 19
names 13
operating point information 19
operating point node voltages 19
output listing 19
output status 20
redirecting 13
subcircuit cross-listing 21
transient analysis measurement results 21
transient analysis results 21
version number, specifying 22
format 292
DSPF 282
NW 310
tabulated data 309
WDB 310
graphing 246
hardcopy graph data file 18
HBLSP analysis extraction results file 18
HBLSP analysis print information 19
HBLSP analysis results file 19
impedance 266
network 265
nodal voltage, AC 262
noise 266, 386
operating point information file 19
operating point node voltages file 19
output listing file 19
output status file 20
parameters 251
power 256
.POWER statement 292
printing 249–251
redirecting 23, 28
restricting 311
reusing 287
saving 245
statements 241
subcircuit cross-listing file 21
transient analysis measurement results file 21
transient analysis results file 21
variables 243
AC formats 263
function 230
voltage 252
611
Index
P
output configuration file 14
output files 16
output listing file 19
output status file 20
overview of data flow 7
overview of simulation process 9
P
.p2d# file 16, 18
.pa# file 17, 21
packed input files 35
PACT (linear acceleration) algorithm 358
PAR keyword 227
.PARAM statement 58, 269, 480
in .ALTER blocks 59
parameter analysis, .NET 420
parameters
ACM 356
admittance (Y) 260
AF 386
algebraic 226, 227
analysis 225
assignment 224
CAPOP 356
cell geometry 232
constants 224
data type 223
data-driven analysis 56
defaults 237
defining 222, 233
DIM2 266
DIM3 266
evaluation order 223
HD2 266
HD3 266
hierarchical 64, 232, 270
hybrid (H) 260
IC 321
impedance (Z) 260
inheritance 235, 237
INOISE 266
input netlist file 42
KF 386
libraries 233–235
M 64
measurement 226
model 201, 204
612
modifying 56
multiply 226
ONOISE 266
optimization 232
OPTxxx 512, 514
output 251
overriding 234, 237
PARHIER option 237
passing 232–240
order 223
problems 240
Release 95.1 and earlier 240
repeated 270
scattering (S) 260
scope 232–233, 240
SIM2 266
simple 224
subcircuit 64
user-defined 225
UTRA 332
parametric analysis 243
PARHIER option 237
path names 54
peak-to-peak value, measuring 271
phase
AC voltage 263
calculating 262
PHOTO model parameter 498
PI (linear acceleration) algorithm 359
piecewise linear sources See PWL
pivot
selection 354
PIVOT option 354
plot limits 245
.PLOT statement 242
simulation results 245, 249
pn junction conductance 341
POLE
function 174, 188
transconductance element statement 174
voltage gain element statement 174
pole/zero
conjugate pairs 174
function, Laplace transform 174, 188
POLY parameter 164, 192, 197
polynomial function 164
one-dimensional 164
three-dimensional 166
HSPICE® Simulation and Analysis User Guide
X-2005.09
Index
Q
two-dimensional 165
[email protected] environment variable 12
POST option 9
example 313
pow(x,y) function 228
power
dissipation 256, 260
function 228
output 256
stored 256
POWER keyword 257
.POWER statement 289, 294
output 292
signals 289, 290, 292
POWER_ANALYSIS option 291
POWER_TOP option 290
PP keyword 272
PPWL
element parameter 192
function 190
print
control options 249
.PRINT statement 242
simulation results 244, 249
printer, device specification 246
.printls# file 16, 19
.printss# file 16, 19
.PROBE statement 242, 245, 249
program structure 6
PRTDEFAULT printer 246
PULSE source function 136, 139, 142, 145
delay time 136
initial value 136
onset ramp duration 136
plateau value 136
recovery ramp duration 136
repetition period 136
width 136
PUTMEAS option 269
PWL
current controlled gates 163
data driven 147
element parameter 184, 192, 197
functions 163, 167
gates 163
output values 145
parameters 145
HSPICE® Simulation and Analysis User Guide
X-2005.09
repeat parameter 145
segment time values 145
simulation time 370
sources, data driven 147
voltage-controlled capacitors 163
voltage-controlled gates 163
See also data driven PWL source
pwr(x,y) function 228
.PZ statement 324
Q
quality assurance 480
R
R Element (resistor) 74
random limit parameter distribution 490
RC
analysis 347, 382
circuit 383
optimizing 520
rcells, reusing 233
real part of AC voltage 262–263
reference temperature 56, 483
RELI option 327
RELMOS option 327, 356
RELQ option 368
RELV option 327
RELVAR option 356
repeat function 535
residual sum of squares 521
resistance 381
resistor
current flow 254
element 72
element template listings 296
length parameter 73
linear 74
model name 72
node to bulk capacitance 73
voltage controlled 188
width parameter 73
restricting output 311
reusing simulation output 287
rise time
example 277
verify 276
613
Index
S
RISE, .CHECK statement 277
RLOAD model parameter 204
RMAX option 370
RMIN option 370
rms value, measuring 271
RSH model parameter 485
S
S19NAME model parameter 204
S19VHI model parameter 204
S19VLO model parameter 204
S1NAME model parameter 204
S1VHI model parameter 204
S1VLO model parameter 204
saturable core
elements 89, 307
models 87, 89
winding names 307
.SAVE statement 321
scale factors 41
SCALE parameter 72, 178, 184, 192, 198, 537
scaling, effect on delays 550
scattering (S) parameters 260
schematic
netlists 43
scope of parameters 233
scratch files 24, 25
SEARCH option 69, 548
search path, setting 58
.SENS statement 324
SETUP
.CHECK statement 279
time verification 279
SFFM source function
carrier frequency 149
modulation index 149
output amplitude 149
output offset 149
signal frequency 149
sgn(x) function 229
shorted nodes 334
sign function 229
SIGNAME element parameter 203
signed power function 228
silicon-on-sapphire devices 55
SIM_ACCURACY option 345, 371
614
SIM_ACTIVE option 283, 285
SIM_ANALOG option 94
SIM_DELTAI options 309
SIM_DELTAV option 308
SIM_DSPF option 282, 284
SIM_DSPF_ACTIVE option 285
SIM_DSPF_SCALEC option 284
SIM_DSPF_SCALER option 284
SIM_DSPF_VTOL option 285
SIM_LA option 283, 359
SIM_LA_FREQ option 361
SIM_LA_MAXR option 360
SIM_LA_MINC option 360
SIM_LA_MINMODE option 362
SIM_LA_TIME option 361
SIM_LA_TOL option 360
SIM_POSTAT option 312, 313
SIM_POSTDOWN option 313
SIM_POSTSCOPE option 313
SIM_POSTSKIP option 312
SIM_POSTTOP option 312
SIM_POWERPOST option 290
SIM_RAIL option 94
SIM2 distortion measure 266
simulation
ABSVAR option 369
accuracy 355, 512
models 356
option 357, 369
timestep 355
tolerances 325, 326, 327, 354
electrical measurements 548
example 571
graphical output 580
multiple runs 61
performance, multithreading 29
process, overview 9
reducing time 370
results
graphing 246
printing 249–251
specifying 269–270
reusing output 287
speed 354
structure 6
time, RELVAR option 369
title 46
HSPICE® Simulation and Analysis User Guide
X-2005.09
Index
S
SIN source function 139
sin(x) function 227
single point experiment 7
single-frequency FM source function 149
sinh(x) function 228
sinusoidal source function 139
skew
file 488
parameters 484
slew rate
example 278
verification 276
SLEW, .CHECK statement 278
SLOPETOL option
simulation time 370
timestep control 369
SMOOTH element parameter 192
SONAME model parameter 204
source
data driven 147
keywords 126
statements 48
See also independent sources
SOVHI model parameter 204
SOVLO model parameter 204
SPICE
compatibility
AC output 262–263
plot 245
sqrt(x) function 228
square root function 228
.ss# file 16, 19
.st# file 17, 20
statement
.CHECK 275
EDGE 278
example 276, 278, 280
HOLD 279
IR drop 281
SETUP 279
.DOUT 211
.POWER 289, 294
signals 289, 290, 292
.SURGE 274
.TRAN 289
statements
.AC 483
.DATA 56
HSPICE® Simulation and Analysis User Guide
X-2005.09
.DC 323, 483, 515
.DCVOLT 321
DOUT 242
element 48
.ENDL 57
.GRAPH 242, 246, 250
.IC 321
initial conditions 321
.LIB 57
.LOAD 321, 323
.MEASURE 242, 243, 268
.MODEL 483
.OP 319
.OPTION
CO 249
.PARAM 58
.PLOT 242, 245, 250
.PRINT 242, 244, 250
.PROBE 242, 245, 250
.SAVE 321, 322
source 48
.STIM 242, 287
.SUBCKT 269
.TEMP 56, 483, 484
.TRAN 483
statistical analysis 484–509
statistics
calculations 481
.STIM statement 242, 287
stimuli 287
structure simulation 6
subcircuit cross-listing file 21
subcircuits
adder 535
calling tree 54
changing in .ALTER blocks 59
creating reusable circuits 63
hierarchical parameters 64
library structure 69
multiplying 64
node names 53, 55
output printing 249
path names 54
power dissipation computation 256
.PRINT and .PLOT statements 66
search order 66
zero prefix 55
.SUBCKT statement 269
615
Index
T
surge current detection 274
.SURGE statement 274
.sw# file 16, 18
sweep
variables 547
switch example 193
switch-level MOSFET’s example 193
T
tabular data 209
tabulated data output 309
Taguchi analysis 480
tan(x) function 227
tanh(x) function 228
TC1, TC2 element parameters 178
TD parameter 178, 185, 192, 198, 265, 271
TDELAY statement 214
TEMP
directory 25
environment variable 25
model parameter 56, 483
sweep variable 547
.TEMP statement 483, 484
temper variable 232
temperature
circuit 481, 483
coefficients 72, 546
derating 56, 483
element 483
optimizing coefficients 547
reference 56, 483
sweeping 547
variable 232
Temperature Variation Analysis 480
.TF statement 324
three-dimensional function 166
TIC model parameter 246
time
delay 265
domain algorithm 364
variable 231
TIMESCALE model parameter 204
timestep
algorithms 367
control
algorithms 366–369
CHGTOL 368
616
DELMAX 370
FS 370
FT 370
minimum internal timestep 370
Minimum Timestep Coefficient 370
options 355, 369
RELQ 368
RMAX 370
RMIN 370
TRTOL 368
TSTEP 370
default control algorithm 363
DVDT algorithm 368
local truncation error algorithm 368
reversal 368
TIMESTEP model parameter 204
title for simulation 46
.TITLE statement 46
TMP directory 25
tmp directory 24
TMP environment variable 25
tmpdir environment variable 24
TNOM option 56, 483
TOX model parameter 485
.tr# file 17, 21
.TRAN statement 289, 483, 515
transconductance
FREQ function 175
LAPLACE function 173
POLE function 174
transfer sign function 229
transient
analysis 243
initial conditions 321, 344
inverter 348
RC network 347
sources 130
output variables 251
transient analysis measurement results file 21
transient analysis results file 21
transmission lines
example 541
U Element 114
Trapezoidal (TRAP) integration algorithm 366
trapezoidal integration
algorithm 363
TREF model parameter 483, 484
HSPICE® Simulation and Analysis User Guide
X-2005.09
Index
U
triode tube 195
TRTOL option 368
truncation algorithm 367
TSTEP
timestep control 370
two-dimensional function 165
U
U Elements 200
digital input 199
UIC
analysis parameter 318
transient analysis parameter 345
UNIF keyword 493
uniform parameter distribution 489
unity gain frequency 548
utility, INE 284
UTRA model parameter restriction 332
V
-v argument
version information 29
variables
AC formats 263
changing in .ALTER blocks 59
DEFAULT_INCLUDE 14
Hspice-specific 231
output 243
AC 260
DC 251
transient 251
plotting 537
sweeping 547
TEMP 25
TMP 25
tmpdir 24
variables, environment 11
variance, statistical 481
VCCAP 189
VCCS See voltage controlled current source
VCD
format 310
VCR See voltage controlled resistor
VCVS See voltage controlled voltage source
vector patterns 209
vendor libraries 68
HSPICE® Simulation and Analysis User Guide
X-2005.09
Verilog value format 212
version
95.3 compatibility 369
determining 29
VIH statement 215
VIL statement 215
Vnn node name in CSOS 55
VOH statement 215
VOL keyword 181
voltage
failure 336
gain
FREQ function 175
LAPLACE function 173
POLE function 174
initial conditions 321
logic high 215
logic low 215
nodal output DC 252
sources 171, 195, 252
summer 180
voltage-controlled
capacitor 189, 193
current source 163, 182, 186, 193, 297
oscillator 181
resistor 163, 188, 193
voltage source 163, 172, 298
VREF statement 215
VTH statement 215
Vxxx source element statement 126
W
W Elements 106
warnings
all nodes connected together 334
floating power supply nodes 54
zero diagonal value detected 335
waveform
characteristics 214
Waveform Characteristics section 214
WDB format
output 310
WHEN keyword 271, 548
.WIDTH
for printout width 249
wildcard uses 51
WMAX model parameter 5
617
Index
X
WMIN model parameter 5
worst case analysis 484, 502, 509
Worst Case Corners Analysis 480
X
XGRID model parameter 246
XL model parameter 485
XMAX model parameter 247
XMIN model parameter 247
XPHOTO model parameter 498
XSCAL model parameter 247
XW model parameter 485
618
Y
YGRID model parameter 246
yield analysis 480
YIN keyword 266, 424
YMAX parameter 247
YMIN parameter 247
YOUT keyword 266, 424
YSCAL model parameter 247
Z
zero delay gate 181, 194
ZIN keyword 266, 424
ZOUT keyword 266, 424
HSPICE® Simulation and Analysis User Guide
X-2005.09
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