Intel LXT915 Simple Quad Ethernet Repeater

Intel LXT915 Simple Quad Ethernet Repeater
Intel® LXT915 Simple Quad Ethernet
Repeater
Datasheet
The Intel® LXT915 Simple Quad Ethernet Repeater is an integrated multi-port repeater designed
for mixed-media networks. It provides all the active circuitry required for the repeater function
in a single CMOS device. It includes one Attachment Unit Interface (AUI) port and four
10BASE-T transceivers. The AUI port allows connection of an external transceiver (10BASE-2,
10BASE-5, 10BASE-T or FOIRL) or a drop cable. The 10BASE-T transceivers are entirely selfcontained with internal filters that simplify the design work required for FCC-compliant EMI
performance.
An Inter-Repeater Backplane (IRB) interface allows 128 or more 10BASE-T ports to be
cascaded, creating a large single-segment multi-port repeater.
The LXT915 Repeater requires only a single 5-volt power supply due to its advanced CMOS
fabrication process.
Applications
■
Remote or Stand-alone Unmanaged Hubs
■
Stackable Unmanaged Hubs
■
Synchronous or asynchronous InterRepeater Backplane supports “hot
swapping”
Inter-repeater backplane allows cascaded
repeaters, linking 128 or more 10BASE-T
ports
Packaged in 64-pin PQFP
Product Features
■
■
■
■
Four integrated 10BASE-T transceivers
and one AUI transceiver on a single chip
Six integrated LED drivers with four
unique operational modes
On-chip transmit and receive filtering
Automatic polarity detection and correction
■
■
Order Number: 249343-003
20-Dec-2005
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Copyright © 2005, Intel Corporation. All Rights Reserved.
Datasheet
Intel® LXT915 Simple Quad Ethernet Repeater
Contents
1.0
Pin Assignments and Signal Descriptions ....................................................................7
2.0
Functional Description .................................................................................................. 11
2.1
2.2
2.3
2.4
2.5
2.6
2.7
2.8
3.0
Introduction.......................................................................................................... 11
External Interfaces .............................................................................................. 11
2.2.1 10BASE-T Ports .....................................................................................11
2.2.2 AUI Port.................................................................................................. 11
2.2.3 Inter-Repeater Backplane ...................................................................... 11
2.2.3.1 Synchronous IRB Operation...................................................... 12
2.2.3.2 Asynchronous IRB Operation ....................................................12
Internal Repeater Circuitry .................................................................................. 12
Initialization.......................................................................................................... 13
10BASE-T Port Operation ................................................................................... 15
2.5.1 10BASE-T Reception ............................................................................. 15
2.5.2 Polarity Detection and Correction...........................................................15
2.5.3 10BASE-T Link Integrity Testing ............................................................ 15
2.5.4 10BASE-T Transmission ........................................................................ 15
AUI Port Operation .............................................................................................. 16
2.6.1 AUI Reception ........................................................................................ 16
2.6.2 AUI Transmission ................................................................................... 16
Collision Handling................................................................................................ 16
LED Display......................................................................................................... 16
2.8.1 LED Mode 0 (Default)............................................................................. 16
2.8.2 LED Mode 1 ........................................................................................... 17
2.8.3 LED Mode 2 ........................................................................................... 17
2.8.4 LED Mode 3 ........................................................................................... 17
Application Information .................................................................................................20
3.1
3.2
3.3
Layout Requirements ..........................................................................................20
3.1.1 The Twisted Pair Interface ..................................................................... 20
3.1.2 The RBIAS Pin ....................................................................................... 20
Unmanaged Hub Application............................................................................... 20
Magnetics Requirements.....................................................................................24
3.3.1 The Twisted Pair Interface ..................................................................... 24
3.3.2 Component Selection ............................................................................. 24
4.0
Test Specifications......................................................................................................... 25
5.0
Mechanical Specifications............................................................................................. 29
5.1
6.0
Datasheet
Top Label Markings............................................................................................. 30
Ordering Information ..................................................................................................... 31
3
Intel® LXT915 Simple Quad Ethernet Repeater
Figures
1
2
3
4
5
6
7
8
9
10
11
12
Block Diagram ....................................................................................................... 6
Pin Assignments ................................................................................................... 7
Global State Machine .......................................................................................... 13
Partitioning State Diagram .................................................................................. 14
Integrated LED Driver Indications ....................................................................... 19
8-Port Unmanaged Hub Application, LED Mode 1 Selected (1 of 2) .................. 22
8-Port Unmanaged Hub Application LED Mode 1 Selected (2 of 2) ................... 23
Inter-Repeater Bus Timing .................................................................................. 28
Package Specifications ....................................................................................... 29
Sample HQFP Package – Intel® SLXT915QC Repeater .................................... 30
Sample Pb-Free (RoHS-Compliant) HQFP Package – Intel® EGLXT915QC Repeater30
Ordering Information Matrix – Sample ................................................................ 32
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
Twisted-Pair Port Signal Descriptions ................................................................... 8
AUI Port Signal Descriptions ................................................................................. 8
Control, Status and Miscellaneous Signal Descriptions ........................................ 8
Inter-Repeater Backplane Signal Descriptions ..................................................... 9
Power Supply Signal Descriptions ...................................................................... 10
LED Mode Selection ........................................................................................... 17
Mode 0 LED Truth Table (Default) ...................................................................... 17
Mode 1 LED Truth Table ..................................................................................... 17
Mode 2 LED Truth Table ..................................................................................... 18
Mode 3 LED Truth Table ..................................................................................... 18
Manufacturers Magnetics List ............................................................................ 24
Absolute Maximum Ratings ................................................................................ 25
Recommended Operating Conditions ................................................................. 25
I/O Electrical Characteristics1 ............................................................................. 25
AUI Electrical Characteristics .............................................................................. 26
TP Electrical Characteristics ............................................................................... 26
IRB Electrical Characteristics .............................................................................. 26
Switching Characteristics .................................................................................... 27
Inter-Repeater Bus Timing .................................................................................. 28
Product Information ............................................................................................. 31
Tables
4
Datasheet
Intel® LXT915 Simple Quad Ethernet Repeater
Revision History
Date
Revision
20-Dec-2005
003
February 2001
Datasheet
002
Page
Description
7
Modified Figure 2 “Pin Assignments” on page 7.
30
Added Section 5.1, “Top Label Markings” on page 30.
31
Added Table 20 “Product Information” on page 31.
32
Added Figure 12 “Ordering Information Matrix – Sample” on
page 32.
26
I/O Electrical Characteristics table: Supply current
Under Max: Change value from 180 to 240.
Under Test Conditions: Add text: “100Ω test load, no LEDs”.
Add table note to value: Supply current may vary depending on the
transformer, LED, and resistor selections.
Swapped values for VIH and VIHRESET.
5
Intel® LXT915 Simple Quad Ethernet Repeater
Figure 1. Block Diagram
LEDM0
LEDM1
RESET
SYSCLK
A/SYNC
DO/DI
Filter
DOP
DON
DIP
DIN
4
4
DO/DI
4
DO/DI
Twisted-pair
port #1
F
TP Port #2
F
TP Port #3
F
TP Port #4
CIP
CIN
IRENA
IRDEN
IRCFS
IRCOL
IRDAT
BCLKIO
Inter-Repeater
Backplane Port
Repeater
(State Machine, Timing
Recovery, FIFO, ect.)
DOP
DON
DIP
DIN
Control
AUI port
(DTE only)
4
LED Drivers
LEDTP1-4
LEDAUI
LEDC
F
DSQE
6
Datasheet
Intel® LXT915 Simple Quad Ethernet Repeater
1.0
Pin Assignments and Signal Descriptions
TPDIN3
TPDIN2
TPDIP3
TPDIN1
TPDIP2
TPDIP1
VCC
VCC
VCC
VCC
IRENA
IRDEN
IRDAT
IRCFS
IRCOL
GND
Figure 2. Pin Assignments
64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49
BCLKIO
1
48
TPDIP4
SYSCLK
2
47
TPDIN4
A/SYNC
3
46
GND
n/c
4
45
TPDON1
n/c
5
44
TPDOP1
GND
6
43
VCC
LEDM0
7
l
42
TPDOP2
41
TPDON2
40
GND
n/c
8
GND
9
RESET
10
DSQE
11
n/c
12
n/c
13
n/c
14
35
TPDON4
VCC
15
34
GND
VCC
16
33
AUICIN
Part #
FPO #
LXT915QC XX
XXXXXXXX
Rev #
LXT915QC
BSMC
39
TPDON3
38
TPDOP3
37
VCC
36
TPDOP4
AUICIP
AUIDIN
AUIDIP
AUIDON
AUIDOP
GND
RBIAS
GND
GND
LEDM1
LEDAUI
LEDTP4
LEDTP3
LEDTP2
LEDCF
LEDTP1
17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32
Package Topside Markings
Marking
Definition
Part #
LXT915 is the unique identifier for this product family.
Rev #
Identifies the particular silicon “stepping” (Refer to Specification Update for additional stepping
information.)
Lot #
Identifies the batch.
FPO #
Identifies the Finish Process Order.
Datasheet
7
Intel® LXT915 Simple Quad Ethernet Repeater
Table 1.
Pin
Symbol
I/O
44
45
TPDOP1
TPDON1
O
O
42
41
TPDOP2
TPDON2
O
O
38
39
TPDOP3
TPDON3
O
O
36
35
TPDOP4
TPDON4
O
O
54
53
TPDIP1
TPDIN1
I
I
52
51
TPDIP2
TPDIN2
I
I
50
49
TPDIP3
TPDIN3
I
I
48
47
TPDIP4
TPDIN4
I
I
Table 2.
Description
Twisted-Pair Data Outputs (Positive and Negative). These pins are the positive
(TPDOP1-4) and negative (TPDON1-4) outputs to the network from the respective twistedpair ports.
Twisted-Pair Data Inputs (Positive and Negative). These pins are the positive (TPDIP14) and negative (TPDIN1-4) inputs from the network to the respective twisted-pair ports.
AUI Port Signal Descriptions
Pin
Symbol
I/O
Description
28
29
AUIDOP
AUIDON
O
O
AUI Data Outputs (Positive and Negative). These pins are the positive and negative data
outputs from the AUI port.
30
31
AUIDIP
AUIDIN
I
I
AUI Data Inputs (Positive and Negative). These pins are the positive and negative data
inputs to the AUI port.
32
33
AUICIP
AUICIN
I
I
AUI Collision Inputs (Positive and Negative). These pins are the positive and negative
collision inputs to the AUI port.
Table 3.
Control, Status and Miscellaneous Signal Descriptions
Pin
Symbol
I/O
Description
2
SYSCLK
I
System Clock. The required 20 MHz system clock is input at this pin. Clock must have a
40-60 duty cycle with <10 ns rise time.
10
RESET
I
Reset. This pin resets the LXT915 internal circuitry when pulled or driven High for ≥ 1 ms.
11
DSQE
I
Disable SQE. When High the SQE function is disabled.
7
24
LEDM0
LEDM1
I
I
LED Mode Select 0 & 1. These two pins select one of four possible modes of LED
operation. The Functional Description section describes the four modes and Table 6 lists
the four settings.
O
Collision & FIFO Error LED Driver. This tri-state LED driver pin reports collisions and
FIFO errors. It pulses Low to report collisions, and pulses High to report FIFO errors. When
this pin is connected to the anode of one LED and to the cathode of a second LED, the
LXT915 will simultaneously monitor and report both conditions independently.
17
8
Twisted-Pair Port Signal Descriptions
LEDCF
Datasheet
Intel® LXT915 Simple Quad Ethernet Repeater
Table 3.
Control, Status and Miscellaneous Signal Descriptions (Continued)
Pin
Symbol
I/O
18
LEDTP1
O
19
LEDTP2
O
20
LEDTP3
O
21
LEDTP4
O
Description
TP Port LED Drivers. These tri-state LED drivers use an alternating pulsed output to
report TP port status. Each pin should be tied to a pair of LEDs (to the anode of one LED
and the cathode of a second LED). When connected this way, each pin reports five
separate conditions (receive, transmit, link integrity, reverse polarity and auto partition).
22
LEDAUI
O
AUI Port LED Driver. This tri-state LED driver uses an alternating pulsed output to report
AUI port status. This pin should be tied to a pair of LEDs (to the anode of one LED and the
cathode of a second LED). When connected this way, this pin reports five separate
conditions (receive, transmit, receive jabber, receive collision and auto partition).
4
5
8
12
13
14
NC
_
No Connects. Leave these pins unconnected (mandatory).
Table 4.
Pin
1
Inter-Repeater Backplane Signal Descriptions
Symbol
BCLKIO
I/O
Description
I/O
Backplane Clock. This 10 MHz clock synchronizes multiple repeaters on a common
backplane. In the synchronous mode, BCLKIO must be supplied to all repeaters from a
common external source. In the asynchronous mode, BCLKIO is supplied only when a
repeater is outputting data to the bus. Each repeater outputs its internally recovered clock
when it takes control of the bus. Other repeaters on the backplane then sync to BCLKIO for
the duration of the transmission.
3
A/SYNC
I
Backplane Synch Mode Select. This pin selects the backplane synch mode. When this
pin is left floating an internal pull-up defaults to the Asynchronous mode (A/SYNC High). In
the asynchronous mode 12 or more LXT915s can be connected on the backplane, and an
external 10 MHz backplane clock source is not required. When the synchronous mode is
selected (A/SYNC tied Low), 32 or more LXT915s can be connected to the backplane and
an external 10 MHz backplane clock source is required.
59
IRENA
I/O
Inter-Repeater Backplane Enable. This pin allows individual LXT915s to take control of
the Inter-Repeater Backplane (IRB) data bus (IRDAT). The IRENA bus must be pulled up
locally by a 330 Ω resistor.1
60
IRDAT
I/O
IRB Data. This pin is used to pass data between multiple repeaters on the IRB. The IRDAT
bus must be pulled up locally by a 330 Ω resistor.1
61
IRDEN
O
IRB Driver Enable. The IRDEN pin is used to enable external bus drivers which may be
required in synchronous systems with large backplanes. This is an active low signal,
maintained for the duration of the data transmission. IRDEN must be pulled up locally by a
330 Ω resistor.
62
IRCFS
I/O
63
IRCOL
I/O
IRB Collision Flag Sense (IRCFS) and IRB Collision (IRCOL). These two pins are used
for collision signalling between multiple LXT915 devices on the IRB. Both the IRCFS bus
and the IRCOL bus must be pulled up globally with 330 Ω resistors.1 (IRCFS requires a
precision resistor [±1%].) 2
1. IRENA and IRDAT can be buffered between boards in multi-board configurations. Where buffering is used, a 330 Ω pull-up
resistor can be used on each signal, on each board. Where no buffering is used, the total impedance should be no less than
330 Ω.
2. IRCFS and IRCOL cannot be buffered. In multi-board configurations, the total impedance on IRCOL should be no smaller
than 330 W. IRCFS should be pulled up only once, by a single 330 Ω, 1% resistor.
Datasheet
9
Intel® LXT915 Simple Quad Ethernet Repeater
Table 5.
Pin
15
16
37
43
55
56
57
58
6
9
23
25
27
34
40
46
64
26
10
Power Supply Signal Descriptions
Symbol
VCC
GND
RBIAS
I/O
Description
_
Power Supply. These pins each require a +5 VDC power supply. These various pins may be
supplied from a single power source, but special de-coupling requirements may apply. Each VCC
pin must be within ±0.3 V of every other VCC pin.
_
Ground. These pins provide ground return paths for the various VCC power supply pins. Connect
these pins to external ground (mandatory).
I
Bias. This pin provides bias current for internal circuitry. Connect this pin to ground through an
external 12.4k 1% resistor.
Datasheet
Intel® LXT915 Simple Quad Ethernet Repeater
2.0
Functional Description
2.1
Introduction
The LXT915 is an integrated hub repeater for 10BASE-T networks. The hub repeater is the central
point for information transfer across the network. The LXT915 offers multiple operating modes to
suit a broad range of applications from simple 4-, 8- or 16-port stand-alone models up to 128-port
stackable hubs.
The main functions of the LXT915 are data recovery and retransmission and collision propagation.
Data packets received at the AUI or 10BASE-T ports are detected and recovered by the port
receivers before being passed to the repeater core circuitry for retiming and retransmission. Data
packets received through the IRB port are essentially passed directly to the core for retransmission.
After recovery of a valid data packet, the repeater broadcasts it to all enabled stations, except the
originator station.
2.2
External Interfaces
The LXT915 includes four 10BASE-T ports with internal filters. The LXT915 also includes an
Attachment Unit Interface (AUI) port and an Inter-Repeater Backplane (IRB) port. The IRB port
enables multiple LXT915 devices to be interconnected, creating a large, single-segment, multi-port
repeater.
2.2.1
10BASE-T Ports
The four 10BASE-T transceiver ports are completely self-contained. Since the transmitters and
receivers include the required filtering, only simple, inexpensive transformers are required to
complete the 10BASE-T interface. Each individual Twisted-Pair (TP) port is implemented in
accordance with the IEEE 802.3 10BASE-T standard. Refer to Table 1 for TP Port signal
descriptions.
2.2.2
AUI Port
The AUI port operates in standard DTE mode and allows connection of an external transceiver
(10BASE-2, 10BASE-5, 10BASE-T or FOIRL) or a drop cable. Refer to Table 2 for AUI Port
signal descriptions.
2.2.3
Inter-Repeater Backplane
The Inter-Repeater Backplane (IRB) allows several LXT915s to function as a single repeater. The
IRB also allows several multi-repeater boards to be integrated in a standard rack and to function as
a single unit. The IRB supports “hot swapping” for easy maintenance and troubleshooting. Each
individual repeater distributes recovered and retimed data to other repeaters on the IRB for
broadcast on all ports simultaneously. This simultaneous rebroadcast allows the multi-repeater
system to act as a single large repeater unit. The maximum number of repeaters on the IRB is
Datasheet
11
Intel® LXT915 Simple Quad Ethernet Repeater
limited by bus loading factors such as parasitic capacitance. The IRB can be operated
synchronously or asynchronously. Refer to Table 3 for control signals and to Table 4 for IRB
signal descriptions.
2.2.3.1
Synchronous IRB Operation
In the synchronous mode, a common external source provides the 10 MHz backplane clock
(BCLKIO) and the 20 MHz system clock (SYSCLK) to all repeaters. (BCLKIO must be
synchronous to SYSCLK and may be derived from SYSCLK using a divide-by-two circuit.) In the
synchronous mode 32 or more LXT915s may be connected on the IRB, providing 128 10BASE-T
ports and 32 AUI ports.
2.2.3.2
Asynchronous IRB Operation
In the asynchronous mode an external BCLKIO source is not required. The repeaters run
independently until one takes control of the IRB. The transmitting repeater then outputs its own 10
MHz clock onto the BCLKIO line. All other repeaters sync to that clock for the duration of the
transmission. In the asynchronous mode, 12 or more LXT915s may be connected to the IRB,
providing 48 10BASE-T ports and 12 AUI ports.
Note:
2.3
The maximum number of repeaters which may be linked on the backplane is limited by board
design factors. The numbers listed above are engineering estimates only. Stronger drivers and
reduced capacitive loading in PCB layout may allow an increased device count.
Internal Repeater Circuitry
The basic repeater circuitry is shared among all the ports within the LXT915. It consists of a global
repeater state machine, several timers and counters and the timing recovery circuit. The timing
recovery circuit includes a FIFO for retiming and recovery of the clock which is used to clock the
receive data out onto the IRB.
The shared functional blocks of the LXT915 are controlled by the global state machine shown in
Figure 3. This diagram and all associated notations used are in strict accordance with section 9.6 of
the IEEE 802.3 standard.
The LXT915 also implements the Partition State Diagram as defined by the IEEE 802.3 standard
and shown in Figure 4. The value of CCLIMIT as implemented in the LXT915 is 64.
The CCLIMIT value sets the number of consecutive collisions that must occur before the port is
subjected to automatic partitioning. Auto-partition/reconnection is also supported by the
LXT915 with Tw5 conforming to the standard requirement of 450 to 560 bit times.
12
Datasheet
Intel® LXT915 Simple Quad Ethernet Repeater
Figure 3. Global State Machine
Power On
START
Begin
UCT
IDLE
Out (ALL) = Idle
Collin(ANY) = SQE[N Port(Collin = SQE)]
Datain(ANY) = II * Collin(ALL) = SQE:[N Port(Datain = II)]
SEND PREAMBLE PATTERN
Out (ALLXN) = Preamble Pattern
Collin(N) = SQE + Datain(N) = II * Collin (ALL) = SQE
Collin(ANYXN) = SQE
TT(ALLXN) 62 * DataRdy * Collin(ALL) = SQE * Datain(N) = II
SEND TWO ONES
Out (ALLXN) = TwoOnes
Collin(ANYXN) = SQE
Collin(N) = SQE + Datain = II * Collin(ALL) = SQE
TwoOnesSent * Collin(ALL) = SQE * Datain(N) = II
SEND DATA
Out (ALLXN) = Data
Collin(N) = SQE + Datain(N) = II *
Collin(ALL) = SQE *
AllDataSent * TT(ANAYXN) < 96
Collin(ANYXN) = SQE
TRANSMIT COLLISION
RECEIVE COLLISION
Out (All) = Jam
Out (ALLXN) = Jam
Collin(ALL) = SQE * TT(ALL) 96 * Tw2Done
Collin(ONLY1) = SQE *
TT(ALL) 96:[M Port(Collin = SQE)]
Collin(ANYXN) = SQE
ONE PORT LEFT
Out (ALLXM) = Jam
II = input_idle (no activity)
II = activity
Collin(ANYXM) = SQE
Datain(M) = II*
Collin(ALL) = SQE*
Tw2Done
Datain(N) = II *
Collin(ALL) = SQE *
TT(ALLXN) 96 *
Tw2Done
Datain(N) = II *
Collin(ALL) = SQE *
TT(ALLXN) 96 *
AllDataSent
WAIT
StartTw1
Out(ALL) = Idle
Collin(ANY) = SQE + Tw1Done
2.4
Initialization
The following description applies to the initial power-on reset and to any subsequent hardware
reset. When a reset occurs (RESET pin pulled high for > 1 ms), the device senses the levels at the
various control pins ( Table 3 and Table 4) to determine the correct operating modes for the LEDs
and the IRB.
Datasheet
13
Intel® LXT915 Simple Quad Ethernet Repeater
Figure 4. Partitioning State Diagram
Begin
COUNT CLEAR
CC(X) = 0
Datain(X) = DIPresent(X)
Collin(X) = CIPresent(X)
DIPresent(X) = II *
CIPresent(X) = SQE
COLLISION COUNT IDLE
Datain(X) = DIPresent(X)
Collin(X) = CIPresent(X)
PARTITION WAIT
DIPresent(X) = II + CIPresent(X) = SQE
Datain(X) = II
Collin(X) = SQE
WATCH FOR
COLLISION
StartTw5
Datain(X) = DIPresent(X)
DIPresent(X) = II *CIPresent(X) = SQE
Collin(X) = CIPresent(X)
PARTITION HOLD
Datain(X) = II
Collin(X) = SQE
DIPresent(X) = II *
CIPresent(X) = SQE
CIPresent(X) = SQE
Tw5Done * DIPresent(X) = II *
CIPresent(X) = SQE
DIPresent(X) = II + CIPresent(X) = SQE
COLLSION COUNT
INCREMENT
PARTITION COLLISION
WATCH
CC(X) = CC(X) + 1
Datain(X) = DIPresent(X)
Datain(X) = II
Collin(X) = SQE
Collin(X) = CIPresent(X)
StartTw6
StartTw5
CIPresent(X) =
SQE
DIPresent(X) = II
CIPresent = SQE
CC(X) ≥
CCLimit + (Tw6Done *
CIPresent(X) = SQE)
DIPresent(X) = II *
CIPresent(X) = SQE *
CC(X) < CCLimit *
Tw6Done
Tw5Done * DIPresent(X) = II *
CIPresent(X) = SQE
WAIT TO RESTORE
PORT
Datain(X) = II
Collin(X) = SQE
CC(X) = 0
DIPresent(X) = II * CIPresent (X) = SQE
14
Datasheet
Intel® LXT915 Simple Quad Ethernet Repeater
2.5
10BASE-T Port Operation
2.5.1
10BASE-T Reception
Each LXT915 port receiver acquires data packets from its twisted-pair input (DIP/DIN). An
internal RC filter and an intelligent squelch function discriminate noise from link test pulses and
valid data streams. No external filters are required. The receive function is activated only by valid
data streams (above the squelch level and with proper timing). If the differential signal at the DI
circuit inputs falls below 75% of the threshold level (unsquelched) for eight bit times (typical), the
port receiver enters the idle state.
2.5.2
Polarity Detection and Correction
The LXT915 ports detect and correct for reversed polarity by monitoring link pulses and end-offrame sequences. A reversed polarity condition is declared when the port receives sixteen or more
incorrect link pulses consecutively, or four frames with reversed start-of-idle sequence. In these
cases the receiver reverses the polarity of the signal and thereby corrects for this failure condition.
If the port enters the link fail state and no valid data or link pulses are received within 96 to 128 ms,
the polarity is reset to the default non-flipped condition. (If Link Integrity Testing is disabled,
polarity detection is based only on received data.)
2.5.3
10BASE-T Link Integrity Testing
The LXT915 fully supports the 10BASE-T Link Integrity test function. The link integrity test
determines the status of the receive side twisted-pair cable. The receiver recognizes link integrity
pulses transmitted in the absence of data traffic. With no data packets or link integrity pulses within
100 (±50) ms, the port enters a link fail state and disables its transmitter. The port remains in the
link fail state until it detects three or more data packets or link integrity pulses.
2.5.4
10BASE-T Transmission
Each LXT915 10BASE-T port receives NRZ data from the repeater core and passes it through a
Manchester encoder. The encoded data is then transmitted to the twisted-pair network (the DO
circuit). The advanced integrated pulse shaping and filtering network produces the pre-distorted
and pre-filtered output signal to meet the 10 Base-T jitter template. An internal continuous resistorcapacitor filter is used to remove any high-frequency clocking noise from the pulse shaping
circuitry. Integrated filters simplify the design work required for FCC compliant EMI performance.
During idle periods, the LXT915 ports transmit link integrity test pulses in accordance with the
802.3 10BASE-T standard.
Data packets transmitted by the LXT915 contain a minimum of 56 preamble bits before the start of
frame delimiter (SFD). In the Asynchronous mode, preamble regeneration takes place on the
transmit side. In the Synchronous mode, the preamble is regenerated on the receive side and
distributed via the IRB. If the total packet is less than 96 bits including the preamble, the
LXT915 extends the packet length to 96 bits by appending a Jam signal (1010...) at the end.
Datasheet
15
Intel® LXT915 Simple Quad Ethernet Repeater
2.6
AUI Port Operation
2.6.1
AUI Reception
The LXT915 AUI port receiver acquires data packets from the network (DIP/DIN). Only valid data
streams above the squelch level activate the receive function. If the differential signal at the DI
circuit inputs falls below 75% of the threshold level (unsquelched) for 8 bit times (typical), the AUI
receiver enters the idle state.
2.6.2
AUI Transmission
The LXT915 AUI port receives NRZ data from the repeater core, and passes it through a
Manchester encoder. The encoded data then goes out on the network (DOP/DON).
2.7
Collision Handling
A collision occurs when two or more repeater ports receive simultaneously, or when the AUI CIP/
CIN signal is active. The LXT915 fully complies with the IEEE 802.3 collision specifications, both
in individual and multi-repeater applications. In multiple-repeater configurations, collision
signaling on the IRB allows all repeaters to share collision parameters, acting as a single large
repeater.
IRCOL is a digital open-drain pin. IRCFS is an analog/digital port. The IRCOL and IRCFS lines
are pulled up globally (i.e., each signal requires one pull-up resistor for all boards). If there are
eight 3-repeater boards in the system, all eight boards share a single pull-up resistor for IRCOL and
a single pull-up resistor for IRCFS. The global pull-up may be located on one of the boards, or on
the backplane. The IRCFS line requires a precision (± 1%) resistor.
The IRENA, IRDAT and IRDEN lines are each pulled up locally (one pull-up resistor per board) if
external bus drivers are used. If no bus drivers are used then only one global pull-up per signal is
used.
2.8
LED Display
The LED display interface consists of seven integrated LED drivers, one for each of the five
network ports and two for common functions. Each pin provides a three-state pulsed output (+5 V,
high Z, and 0 V) which allows multiple conditions to be monitored and reported independently.
Table 6 shows the LED Mode selected with each LEDM1 and LEDM0 combination. Figure 5
shows the LED Driver output conditions and Table 7 through Table 10 list the repeater states
associated with each of the five conditions.
2.8.1
LED Mode 0 (Default)
This mode is selected when LEDM1 and LEDM0 are floated or pulled low. Refer to Table 7.
16
Datasheet
Intel® LXT915 Simple Quad Ethernet Repeater
2.8.2
LED Mode 1
This mode is selected when LEDM1 is tied, floated or pulled low and LEDM0 is pulled high by a
pull-up resistor. Refer to Table 8.
2.8.3
LED Mode 2
This mode is selected when LEDM1 is pulled high by a pull-up resistor and LEDM0 is floated or
pulled low. Refer to Table 9.
2.8.4
LED Mode 3
This mode is selected when LEDM1 is pulled high by a pull-up resistor and LEDM0 is also pulled
high by a pull-up resistor. Refer to Table 10.
Table 6.
LED Mode Selection
LEDM1
LEDM0
Pin 24
Pin 7
0
0
0 (default)
0
1
1
1
0
2
1
1
3
LED Mode Selected
Table 7.
Table 8.
Datasheet
Mode 0 LED Truth Table (Default)
Condition
LEDTP 1-4
LEDAUI
LEDCF
1
Rx Link Pulse
N/A
FIFO Error
2
Tx Packet
Tx Packet
N/A
3
Reversed Polarity
N/A
Collision
4
Rx Packet
Rx Packet
N/A
5
Partitioned Out
Partitioned Out
N/A
Mode 1 LED Truth Table
Condition
LEDTP 1-4
LEDAUI
LEDCF
1
Rx Link Pulse
N/A
MAU Jabber Lockup Protection (MJLP)
2
N/A
N/A
N/A
3
N/A
N/A
Collision
4
Rx Packet
Rx Packet
N/A
5
N/A
N/A
N/A
17
Intel® LXT915 Simple Quad Ethernet Repeater
Table 9.
Mode 2 LED Truth Table
Condition
LEDTP 1-4
LEDAUI
LEDCF
1
Rx Link Pulse
N/A
MAU Jabber Lockup Protection (MJLP)
2
Partitioned Out
Partitioned Out
N/A
3
N/A
N/A
Collision
4
Rx Packet
Rx Packet
N/A
5
N/A
N/A
N/A
LEDAUI
LEDCF
Table 10. Mode 3 LED Truth Table
18
Condition
LEDTP 1-4
1
Rx Link Pulse
N/A
MAU Jabber Lockup Protection (MJLP)
2
Rx Packet
Rx Packet
N/A
3
Partitioned Out
Partitioned Out
Collision
4
N/A
N/A
N/A
5
N/A
N/A
N/A
Datasheet
Intel® LXT915 Simple Quad Ethernet Repeater
Figure 5. Integrated LED Driver Indications
NOTE: The drivers are capable of driving a 10 mA load. The signal is pulsed every 4 ms, making the average
current approximately 5 mA.
+5 V
2 mA Operation
5 mA Operation
+5 V
820 Ω
330 Ω
Red
Red
LXT915
LED
Driver
LXT915
LED
Driver
470 Ω
Green
70 Ω
Green
820 Ω
330 Ω
Condition 1:
Steady Green
4 ms
4 ms 4 ms
Condition 2:
Blinking Green
4 ms
4 ms 4 ms
4 ms 4 ms
+5V
High Z
0V (Gnd)
256 ms
4 ms 4 ms
256
ms
4 ms 4 ms
4 ms 4 ms
+5V
High Z
0V (Gnd)
Condition 3:
Steady Red
4 ms 4 ms
4 ms
4 ms
4 ms 4 ms
Condition 4:
Blinking Red
+5V
High Z
0V (Gnd)
256 ms
256
ms
4 ms 4 ms
4 ms 4 ms
4 ms 4 ms
4 ms 4 ms
+5V
High Z
0V (Gnd)
5.33 Hz
Condition 5:
Alternating Red/Green
4 ms 4 ms
4 ms 4 ms
4 ms
4 ms 4 ms
+5V
High Z
0V (Gnd)
93.75 ms
Datasheet
19
Intel® LXT915 Simple Quad Ethernet Repeater
3.0
Application Information
3.1
Layout Requirements
3.1.1
The Twisted Pair Interface
The four, twisted-pair output circuits are identical. Each TPDOP/TPDON signal has a 24.9 Ω, 1%,
series resistor and a 120 pF capacitor differentially across the positive and negative outputs. These
signals go directly to a 1:√2 transformer creating the necessary 100 Ω termination for the cable.
The TPDIP/TPDIN signals have a 100 Ω resistor across the positive and negative input signals to
terminate the 100 Ω signal received from the line. To calculate the impedance on the output line
interface, use:
(24.9 Ω + 24.9 Ω)
* √2
2
≈ 100 Ω.
The layout of the twisted-pair ports is critical in complex designs. Run the signals directly from the
device to the discrete termination components (located close to the transformers).
The signals running from the transformers to the connector should run in close pairs directly to the
connector. Be careful not to cross the transmit and receive pairs. One way to avoid a problem is to
run the receive pairs on the component side and the transmit pairs on the solder side. Careful
planning during the schematic and layout stages can avoid these problems.
The PCB layout should have no ground or power planes from the transformers to the connectors.
The data signals should be the only traces in this area. Place the chassis ground for the connectors
near the edge of the PCB, away from the signals, connecting the connector shield with the chassis.
3.1.2
The RBIAS Pin
The RBIAS signal sets the levels for the output drivers of the LXT915. Any emissions or common
mode noise entering the device here could be measured on the twisted pair output signals. The
LXT915 requires a 12.4 kΩ, 1% resistor directly connected to RBIAS at pin 26. This connection
should be as short as possible. The ground rails from pins 25 & 27 should come directly off of the
device to enclose the resistor and pin forming a shielded area between the RBIAS connection and
the switching signals on the PCB.
3.2
Unmanaged Hub Application
Figure 6 shows an eight-port unmanaged hub application. The application shows a pair of
LXT915s connected using the Asynchronous IRB mode.
Figure 6 (Sheet 1) has the LXT915 set up with the LEDs in Mode 1 with one link LED per port and
a single collision LED. In LED Mode 1, the twisted pair port LEDs display link integrity only
(refer to Table 8). LED Mode 1 is selected by pulling LEDM0 High with a 1 kΩ resistor on pin 7
and pulling LEDM1 Low with pin 24 attached to ground.
20
Datasheet
Intel® LXT915 Simple Quad Ethernet Repeater
Figure 7 (Sheet 2) shows the second LXT915 set up in the same LED Mode (Mode 1). The AC/DC
plug and regulator circuits are commonly used in remote hub applications.
The VCC and GND pins are at the bottom of each diagram. All VCC pins use a single power
supply with decoupling capacitors installed between the VCC and GND pins and their respective
planes.
Datasheet
21
22
VCC
1
PB_SWITCH
S1
2
OUT
20MHz_OSC
Y1
22
R50
8
LED
R18
78.7
1%
78.7
1%
R26
12.4K
R17
RESET
BCLKIO
20MHz
Mode
R25
1%
78.7
R19
32
33
30
31
28
29
26
24
10
11
1
2
14
8
7
5
12
1K
R49
VCC
T5
9
16
1
IRCOL*
BCLKIO
1%
8
7
5
4
2
1
TG01-0756
8
10
12
5
7
13
15
4
16
1
2
VCC
R9
R10
R11
R12
38
39
36
35
1
2
3
4
5
6
7
8
1%
1%
1%
1%
1%
1%
1%
1%
24.9
24.9
24.9
24.9
24.9
24.9
3
24
23
PM6044
VIN-
VIN-
EN
VO-
120pf
24.9
120pf
24.9
12
47
48
49
50
51
52
1.5K
1.5K
3
2
9
1%
100
R2
1%
100
R1
13
5
4
8
VIN+
D6
J1
R21
BNC
R20
510
1
2
TX1:1.41X4
15
14
3
4
5
9
2
1
8
10
11
12
13
5
6
7
CD+
.001uf
C1
DP8392
VEE
VEE
VEE
TX-
TX+
RX-
RX+
CD-
1%
100
R3
1%
100
GND
HBE
TXD
RXI
CDS
RR-
RR+
120pf
9
C6
SPARK
GAP
1N4148
1K
1-3KV
BNC
2
TG01-1006N2
8
7
6
5
4
3
1
RX1:1X4
R28
10
7
8
11
6
8
4
5
6
7
15
14
13
12
2
3
4
5
3
2
1
8
16
1MEG
R27
10
9
15
14
16
12
TG54-1006N2
1
120pf
6
R8
41
9
VIN+
11
cgnd
R22
510
7
R7
42
7
2
U2
16
R23
510
53
R6
45
10
VO+
1
T1
C5
T2
link4
link3
link2
54
R5
44
21
20
6
U3
R54
R4
C4
C3
IRCOL
IRCFS
IRDAT
IRENA
510
D5
D4
D3
D2
RJ45X4
CN1A
RJ45X4
CN1B
RJ45X4
CN1C
RJ45X4
CN1D
R24
510
LED
LEDs
4
C2
330
link1
Green
YELLOW
19
R53
1%
330
R13
D1
3
330
330
R16
VCC
COLLISION
18
22
4
17
13
3
63
62
61
60
59
R14
R15
12
13
15
TPDIN4
AUICIP
1.5K
TPDIP4
R52
TPDIN3
1.5K
TPDIP3
NC
NC
R51
TPDIN2
AUIDIP
AUICIN
LXT915PC
TPDIP2
AUIDON
AUIDIN
TPDIN1
TPDIP1
TPDON4
TPDOP4
TPDON3
TPDOP3
TPDON2
TPDOP2
TPDON1
TPDOP1
LEDTP4
LEDTP3
LEDTP2
LEDTP1
LEDAUI
LEDCF
AUIDOP
RBIAS
LEDM1
RESET
DSQE
A/SYNC*
IRCFS*
NC
SYSCLK
IRDEN*
NC
IRDAT
IRENA*
NC
LEDM0
NC
U1
Selected
22
1%
1
TP4
TP3
TP2
TP1
VCC
Intel® LXT915 Simple Quad Ethernet Repeater
Figure 6. 8-Port Unmanaged Hub Application, LED Mode 1 Selected (1 of 2)
Datasheet
Intel® LXT915 Simple Quad Ethernet Repeater
Figure 7. 8-Port Unmanaged Hub Application LED Mode 1 Selected (2 of 2)
Datasheet
23
Intel® LXT915 Simple Quad Ethernet Repeater
3.3
Magnetics Requirements
3.3.1
The Twisted Pair Interface
The LXT915 requires transformers with a 1:1 ratio for the receive pairs and 1:√2 on the transmit
pairs. The transformer isolation voltage should be rated at 2 KV to protect the circuitry from static
voltages across the connectors and cables. Magnetics suitable for the LXT915 are currently
available, and are used on the LXT914 Quad Repeater. Available magnetics include the following
options:
• simple per-port Rx/Tx pair transformers
• receive quad transformers and
transmit quad transformers
• single 40 pin octal transformers
3.3.2
Component Selection
Table 11 is a list of available Quad and Single port transformers with manufacturers and part
numbers. This information was valid as of the printing date of this document. Before committing
to a specific component, designers should contact the manufacturer for current product
specifications, and should test and validate the magnetics for the specific application.
Table 11. Manufacturers Magnetics List
Manufacturer
24
Quad Transmit
Quad Receive
BEL
S553-5999-02
S553-5999-03
HALO
TD54-1006L1
TG54-1006N2
TD01-1006L1
TG01-1006N2
Nanopulse
5976
5977
Kappa
TP4003P
TP497P101
PCA
EPE6009
EPE6010
TDK
TLA-3T107
TLA-3T106
VALOR
PT4116
PT4117
Quad Port Tx/Rx
TG44-S010NX
TG45-S010NX
TG46-S010NX
Datasheet
Intel® LXT915 Simple Quad Ethernet Repeater
4.0
Test Specifications
Note:
Table 12 through Table 19 and Figure 8 represent the performance specifications of the
LXT915. These specifications are guaranteed by test except where noted “by design.” Minimum
and maximum values listed in Table 14 through Table 19 apply over the recommended operating
conditions specified in Table 13.
.
Table 12. Absolute Maximum Ratings
Parameter
Symbol
Min
Typ
Max
Units
Supply voltage
VCC
-0.3
–
6
V
Operating temperature
TOP
0
–
+70
°C
Storage temperature
TST
-65
–
+150
°C
NOTE: Exceeding these values may cause permanent damage.
Functional operation under these conditions is not implied.
Exposure to maximum rating conditions for extended periods may affect device reliability.
Table 13. Recommended Operating Conditions
Parameter
Symbol
Min
Typ
Max
Units
Recommended supply voltage
VCC
4.75
5.0
5.25
V
Recommended operating temperature
TOP
0
–
70
°C
Table 14. I/O Electrical Characteristics1
Parameter
Supply current
Symbol
Min
Typ2
Max
ICC
–
–
240
Units
3
mA
Test Conditions
100Ω test load on TPOs, no LEDs
VIL
–
–
0.8
V
VILRESET
–
–
0.8
V
VIH
2.0
–
–
V
VIHRESET
4.0
–
–
V
Output Low voltage
VOL
–
–
0.4
V
IOL = 1.6 mA
Output Low voltage
VOL
–
–
10
% VCC
IOL < 10 μA
Output Low voltage (LED)
VOLL
–
–
1.0
V
IOLL = 5 mA
Output High voltage
VOH
2.4
–
–
V
IOH = 40 μA
Output High voltage
VOH
90
–
–
% VCC
IOH < 10 μA
Output High voltage (LED)
VOHL
4
–
–
V
IOHL = -5 mA
Input Low current
IIL
–
–
2
mA
VOL = .4 V
Output rise / fall time
–
–
3
8
ns
CLOAD = 20 pF
RESET pulse width
PWRESET
1.0
–
–
ms
VCC = 4.75 V
RESET fall time
TFRESET
–
–
20.0
μs
VIHRESET to VILRESET
Input Low voltage
Input Low voltage (RESET)
Input High voltage
Input High voltage (RESET)
VCC = 5.25 V
VCC = 4.75 V
1. Not applicable to IRB signals; IRB electrical characteristics are specified in Table 17.
2. Typical values are at 25° C and are for design aid only; they are not guaranteed and not subject to production testing.
3. Supply current may vary depending on the transformer, LED, and resistor selections.
Datasheet
25
Intel® LXT915 Simple Quad Ethernet Repeater
Table 15. AUI Electrical Characteristics
Symbol
Min
Typ1
Max
Units
Input Low current
IIL
–
–
-700
μA
Input High current
IIH
–
–
500
μA
Differential output voltage
VOD
±550
–
±1200
mV
Receive input impedance
ZIN
–
20
–
kΩ
Differential squelch threshold
VDS
–
220
–
mV
Parameter
Test Conditions
Between CIP/CIN & DIP/DIN
1. Typical values are at 25 °C and are for design aid only; they are not guaranteed and no subject to production testing.
Table 16.
TP Electrical Characteristics
Symbol
Min
Typ1
Max
Units
Transmit output impedance
ZOUT
–
5
–
Ω
Peak differential output voltage
VOD
3.3
3.5
3.7
V
Load = 100 Ω at TPOP and TPON
Transmit timing jitter addition
–
–
± 6.4
± 10
ns
0 line length
Transmit timing jitter added by the
MAU and PLS sections2
–
–
± 3.5
± 5.5
ns
After line model specified by IEEE
802.3 for 10BASE-T
Parameter
Test Conditions
Receive input impedance
ZIN
–
20
–
kΩ
Between TPIP/TPIN
Differential squelch threshold
VDS
300
420
565
mV
5 MHz square wave input
1. Typical values are at 25 °C and are for design aid only; they are not guaranteed and not subject to production testing.
2. IEEE 802.3 specifies maximum jitter additions at 1.5 ns for the AUI cable, 0.5 ns from the encoder, and 3.5 ns from the MAU.
Table 17. IRB Electrical Characteristics
Test
Conditions
Sym
Min.
Typ1
Max
Output Low voltage
VOL
–
0.3
0.6
V
Output rise or fall time
TRF
–
4
12
ns
Input Low voltage: IRENA, IRCOL & IRDAT
VILIRB
–
–
0.8
V
RL = 330Ω
Input High voltage: IRENA, IRCOL & IRDAT
VIHIRB
3.0
–
–
V
RL = 330Ω
Parameter
Units
Input Low voltage: BCLKIO
VILBCLK
–
–
0.4
V
RL = 330Ω
Input High voltage: BCLKIO
VIHBCLK
4.0
–
–
V
RL = 330Ω
1. Typical values are at 25 °C and are for design aid only; they are not guaranteed and not subject to production testing.
26
Datasheet
Intel® LXT915 Simple Quad Ethernet Repeater
Table 18.
Switching Characteristics
Parameter
Typ1
Min
Max
Maximum transmit time
5.0
–
5.5
ms
Unjab time
–
9.6
–
μs
Time link loss
–
60
–
ms
Time between Link Integrity Pulses
10
–
20
ms
Interval for valid receive Link Integrity Pulses
4.1
–
30
ms
Jabber Timing
Link Integrity Timing
Units
1. Typical values are at 25 °C and are for design aid only; they are not guaranteed and not subject to production testing.
Datasheet
27
Intel® LXT915 Simple Quad Ethernet Repeater
Figure 8. Inter-Repeater Bus Timing
Rx DATA
tIRB4
tIRB8
TPs
tIRB5
tIRB9
AUI
tIRB7
tIRB1
IRDEN
tIRB6
tIRB2
IRENA
tIRB3
IRDAT
BCLKIO
Table 19. Inter-Repeater Bus Timing
Parameter
Symbol
Min
Typical1
Max.
Units
Start of Frame to IRDEN Low (active)
tIRB1
10
–
150
ns
Start of Frame to IRENA Low (active)
tIRB2
125
–
225
ns
BCLKIO to IRDAT valid (Synchronous mode)
tIRB3
5
–
30
ns
BCLKIO to IRDAT valid (Asynchronous mode)
tIRB3
–
50
–
ns
IRENA Low (active) to TP outputs active
tIRB4
525
–
600
ns
IRENA Low (active) to AUI output active
tIRB5
475
–
525
ns
End of Frame clock to IRENA High (inactive)
tIRB6
5
–
30
ns
IRENA High (inactive) to IRDEN High (inactive)
tIRB7
95
–
105
ns
IRENA High (inactive) to TP outputs inactive
tIRB8
575
–
600
ns
IRENA High (inactive) to AUI output inactive
tIRB9
425
–
450
ns
1. Typical values are at 25 °C and are for design aid only; they are not guaranteed and not subject to production testing.
28
Datasheet
Intel® LXT915 Simple Quad Ethernet Repeater
5.0
Mechanical Specifications
Figure 9. Package Specifications
P/N LXT915QC
• 64-pin Quad Flat Pack
• Temperature Range 0° C - +70° C
D
D1
Inches
Dim
Millimeters
Min
Max
Min
Max
A
–
0.130
–
3.30
A1
0.000
0.01
0.000
0.025
A2
0.100
0.110
2.55
3.05
B
0.012
0.018
0.30
0.45
D
0.695
0.715
17.65
18.15
D1
0.547
0.551
13.90
14.00
E
0.695
0.715
17.65
18.15
E1
0.547
0.555
13.90
14.10
e
L
0.80 BSC
0.032 BSC
0.026
L1
0.037
E1
0.65
0.077 REF
E
e
/2
e
0.95
1.95 REF
θ
0°
7°
0°
7°
θ3
5°
16°
5°
16°
θ3
L1
A2
A
θ
A1
Datasheet
L
B
θ3
29
Intel® LXT915 Simple Quad Ethernet Repeater
5.1
Top Label Markings
Figure 10 shows a sample HQFP package for the LXT915 Repeater.
Notes:
1. In contrast to the Pb-Free (RoHS-compliant) HQFP package, the non-RoHS-compliant
packages do not have the “e3” symbol in the last line of the package label.
2. Further information regarding RoHS and lead-free components can be obtained from your
local Intel representative.
For general information, see http://www.intel.com/technology/silicon/leadfree.htm.
Figure 10. Sample HQFP Package – Intel® SLXT915QC Repeater
Pin 1
LXT915QC B3
XXXXXXXX
Part Number
FPO Number
BSMC
Bottom Side Mark Code
B5432-01
Figure 11 shows a sample Pb-free RoHS-compliant HQFP package for the LXT915 Repeater.
Figure 11. Sample Pb-Free (RoHS-Compliant) HQFP Package – Intel® EGLXT915QC Repeater
Pin 1
EGLXT915C B3
Part Number
XXXXXXXX
FPO Number
BSMC
Pb-Free Indication
e3
Bottom Side Mark Code
B5433-01
30
Datasheet
Intel® LXT915 Simple Quad Ethernet Repeater
6.0
Ordering Information
Table 20 lists the LXT915 product ordering information. Figure 12 provides the ordering
information matrix.
Table 20. Product Information
Intel Number
Datasheet
Revision
Package Type
Pin Count
RoHS Compliant
SLXT915QC.B3
B3
HQFP
64
No
EGLXT915QC.B3
B3
HQFP
64
Yes
31
Intel® LXT915 Simple Quad Ethernet Repeater
Figure 12 shows an order matrix with sample information for the LXT915.
Figure 12. Ordering Information Matrix – Sample
S
LXT
915
Q
C
B3
Product Revision
xn = 2 Alphanumeric characters
Temperature Range
A = Ambient (0 – 550 C)
C = Commercial (0 – 700 C)
E = Extended (-40 – 850 C)
Internal Package Designator
L = LQFP
P = PLCC
N = DIP
Q = PQFP
H = QFP
T = TQFP
B = BGA
C = CBGA
E = TBGA
K = HSBGA (BGA with heat slug
Product Code
xxxxx = 3-5 Digit alphanumeric
IXA Product Prefix
LXT = PHY layer device
IXE = Switching engine
IXF = Formatting device (MAC/Framer)
IXP = Network processor
Intel Package Designator
Pb-Free
Package
Leaded
WB
WJ
HQFP
LQFP
HB
DJ
BJ
TQFP
FA
JA
TQFP
FA
WD
PQFP
HD
QU
EG
PQFP
KU
PQFP
S
WG
QFN
HG
UB
QFN
LB
UC
PDIP
PD
EP
SSOP
PA
EE
PLCC
N
RU
MMAP
HZ
PC
MMAP
RC
EL
PBGA
FL
PR
PBGA
FW
LU
EW
PBGA
GD
PBGA
GW
WF
CBGA
HF
JP
FCBGA
HL
SC
TBGA
TL
B5436-01
32
Datasheet
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