Datasheet - Mouser Electronics

Datasheet - Mouser Electronics

The following document contains information on Cypress products. Although the document is marked with the name

“Broadcom”, the company that originally developed the specification, Cypress will continue to offer these products to new and existing customers.

CONTINUITY OF SPECIFICATIONS

There is no change to this document as a result of offering the device as a Cypress product. Any changes that have been made are the result of normal document improvements and are noted in the document history page, where supported. Future revisions will occur when appropriate, and changes will be noted in a document history page.

CONTINUITY OF ORDERING PART NUMBERS

Cypress continues to support existing part numbers. To order these products, please use only the Ordering Part

Numbers listed in this document.

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or contact your local sales office for additional information about

Cypress products and services.

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Cypress Semiconductor Corporation

Document Number: 002-14797 Rev. *G

198 Champion Court San Jose

,

CA 95134-1709 408-943-2600

Revised July 1, 2016

Data Sheet

BCM4343W

Single-Chip IEEE 802.11 b/g/n MAC/Baseband/

Radio with Bluetooth 4.1, an FM Receiver, and

Wireless Charging

GENERAL DESCRIPTION

The Broadcom

®

BCM4343W is a highly integrated single-chip solution and offers the lowest RBOM in the industry for wearables, tablets, and a wide range of other portable devices. The chip includes a 2.4

GHz WLAN IEEE 802.11 b/g/n MAC/baseband/radio,

Bluetooth 4.1 support, and an FM receiver. In addition, it integrates a power amplifier (PA) that meets the output power requirements of most handheld systems, a low-noise amplifier (LNA) for best-in-class receiver sensitivity, and an internal transmit/receive (iTR) RF switch, further reducing the overall solution cost and printed circuit board area.

The WLAN host interface supports gSPI and SDIO v2.0 modes, providing a raw data transfer rate up to

200 Mbps when operating in 4-bit mode at a 50 MHz bus frequency. An independent, high-speed UART is provided for the Bluetooth/FM host interface.

Using advanced design techniques and process technology to reduce active and idle power, the

BCM4343W is designed to address the needs of highly mobile devices that require minimal power consumption and compact size. It includes a power management unit that simplifies the system power topology and allows for operation directly from a rechargeable mobile platform battery while maximizing battery life.

The BCM4343W implements the world’s most advanced Enhanced Collaborative Coexistence algorithms and hardware mechanisms, allowing for an extremely collaborative WLAN and Bluetooth coexistence.

Figure 1: BCM4343W System Block Diagram

VDDIO VBAT

WLAN

Host I/F

Bluetooth

Host I/F

FM RX

Host I/F

WL_REG_ON

WL_IRQ

SDIO*/SPI

CLK_REQ

BT_REG_ON

PCM

BT_DEV_WAKE

BT_HOST_WAKE

UART

I

2

S

Stereo Analog Out

BCM4343W

2.4 GHz WLAN +

Bluetooth TX/RX

FM

RX

BPF

5300 California Avenue • Irvine, CA 92617 • Phone: 949-926-5000 • Fax: 949-926-5203

4343W-DS107-R

August 24, 2015

Broadcom Corporation

5300 California Avenue

Irvine, CA 92617

© 2015 by Broadcom Corporation

All rights reserved

Printed in the U.S.A.

Broadcom

®

, the pulse logo, Connecting everything

®

, the Connecting everything logo, OneDriver

,

SmartAudio

®

, and TurboQAM

®

are among the trademarks of Broadcom Corporation and/or its affiliates in the

United States, certain other countries and/or the EU. Any other trademarks or trade names mentioned are the property of their respective owners.

This data sheet (including, without limitation, the Broadcom component(s) identified herein) is not designed, intended, or certified for use in any military, nuclear, medical, mass transportation, aviation, navigations, pollution control, hazardous substances management, or other high-risk application. BROADCOM

PROVIDES THIS DATA SHEET “AS-IS,” WITHOUT WARRANTY OF ANY KIND. BROADCOM DISCLAIMS

ALL WARRANTIES, EXPRESSED AND IMPLIED, INCLUDING, WITHOUT LIMITATION, THE IMPLIED

WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE, AND NON-

INFRINGEMENT.

BCM4343W Data Sheet Revision History

FEATURES

IEEE 802.11x Key Features

• Single-band 2.4 GHz IEEE 802.11b/g/n.

• Support for 2.4 GHz Broadcom TurboQAM

®

data rates (256-QAM) and 20 MHz channel bandwidth.

• Integrated iTR switch supports a single 2.4 GHz antenna shared between WLAN and Bluetooth.

• Supports explicit IEEE 802.11n transmit beamforming.

• Tx and Rx Low-density Parity Check (LDPC) support for improved range and power efficiency.

• Supports standard SDIO v2.0 and gSPI host interfaces.

• Supports Space-Time Block Coding (STBC) in the receiver.

• Integrated ARM Cortex-M3 processor and onchip memory for complete WLAN subsystem functionality, minimizing the need to wake up the applications processor for standard WLAN functions. This allows for further minimization of power consumption, while maintaining the ability to field-upgrade with future features. On-chip memory includes 512 KB SRAM and 640 KB

ROM.

• OneDriver

software architecture for easy migration from existing embedded WLAN and

Bluetooth devices as well as to future devices.

Bluetooth and FM Key Features

• Complies with Bluetooth Core Specification

Version 4.1 with provisions for supporting future specifications.

• Bluetooth Class 1 or Class 2 transmitter operation.

• Supports extended Synchronous Connections

(eSCO), for enhanced voice quality by allowing for retransmission of dropped packets.

• Adaptive Frequency Hopping (AFH) for reducing radio frequency interference.

• Interface support — Host Controller Interface

(HCI) using a high-speed UART interface and

PCM for audio data.

FEATURES

Bluetooth and FM Key Features (Continued)

• FM receiver unit supports HCI for communication.

• Low-power consumption improves battery life of handheld devices.

• FM receiver: 65 MHz to 108 MHz FM bands; supports the European Radio Data Systems

(RDS) and the North American Radio Broadcast

Data System (RBDS) standards.

• Supports multiple simultaneous Advanced Audio

Distribution Profiles (A2DP) for stereo sound.

• Automatic frequency detection for standard crystal and TCXO values.

General Features

• Supports a battery voltage range from 3.0V to

4.8V with an internal switching regulator.

• Programmable dynamic power management.

• 4 Kbit One-Time Programmable (OTP) memory for storing board parameters.

• Can be routed on low-cost 1 x 1 PCB stack-ups.

• 74-ball WLBGA package (4.87 mm × 2.87 mm,

0.4 mm pitch).

• 153-bump WLCSP package (115 μm bump diameter, 180 μm bump pitch).

• Security:

– WPA and WPA2 (Personal) support for powerful encryption and authentication.

– AES in WLAN hardware for faster data encryption and IEEE 802.11i compatibility.

– Reference WLAN subsystem provides Cisco

Compatible Extensions (CCX, CCX 2.0, CCX

3.0, CCX 4.0, CCX 5.0).

– Reference WLAN subsystem provides Wi–Fi

Protected Setup (WPS).

• Worldwide regulatory support: Global products supported with worldwide homologated design.

• Multimode wireless charging support that complies with the Alliance for Wireless Power

(A4WP), the Wireless Power Consortium (WPC), and the Power Matters Alliance (PMA).

Broadcom

®

August 24, 2015 • 4343W-DS107-R

Single-Chip IEEE 802.11 b/g/n MAC/Baseband/Radio

Page 3

BROADCOM CONFIDENTIAL

BCM4343W Data Sheet

Revision History

Revision

4343W-DS107-R

Date

08/24/15

4343W-DS106-R

4343W-DS105-R

4343W-DS104-R

4343W-DS103-R

4343W-DS102-R

4343W-DS101-R

4343W-DS100-R

Revision History

07/01/15

01/12/15

10/03/14

09/05/14

6/09/14

4/18/14

4/07/14

Change Description

Updated:

Figure 3: “Typical Power Topology (1 of 2),” on page 21

and

Figure 4: “Typical Power Topology (2 of 2),” on page 22

.

Table 2: “Crystal Oscillator and External Clock Requirements and

Performance,” on page 30 .

Table 23: “I/O States,” on page 110 .

Updated:

Table 23: “I/O States,” on page 110 .

Table 26: “ESD Specifications,” on page 114

.

Table 29: “WLAN 2.4 GHz Receiver Performance Specifications,” on page 118 .

Table 30: “WLAN 2.4 GHz Transmitter Performance

Specifications,” on page 121 .

Table 38: “FM Receiver Specifications,” on page 130

.

Table 43: “2.4 GHz Mode WLAN Power Consumption,” on page 140

.

Table 50: “Part Ordering Information,” on page 155

.

Refer to the earlier release for detailed revision history.

Refer to the earlier release for detailed revision history.

Refer to the earlier release for detailed revision history.

Refer to the earlier release for detailed revision history.

Refer to the earlier release for detailed revision history.

Initial release.

Broadcom

®

August 24, 2015 • 4343W-DS107-R

Single-Chip IEEE 802.11 b/g/n MAC/Baseband/Radio

Page 4

BROADCOM CONFIDENTIAL

BCM4343W Data Sheet Table of Contents

Table of Contents

About This Document ................................................................................................................................ 14

Purpose and Audience .......................................................................................................................... 14

Acronyms and Abbreviations................................................................................................................. 14

Document Conventions ......................................................................................................................... 14

Technical Support ...................................................................................................................................... 14

Section 1: Overview .......................................................................................................... 15

Overview...................................................................................................................................................... 15

Features....................................................................................................................................................... 17

Standards Compliance............................................................................................................................... 18

Section 2: Power Supplies and Power Management ..................................................... 19

Power Supply Topology............................................................................................................................. 19

BCM4343W PMU Features ......................................................................................................................... 20

WLAN Power Management ........................................................................................................................ 23

PMU Sequencing ........................................................................................................................................ 24

Power-Off Shutdown .................................................................................................................................. 25

Power-Up/Power-Down/Reset Circuits..................................................................................................... 25

Wireless Charging ...................................................................................................................................... 26

Section 3: Frequency References.................................................................................... 29

Crystal Interface and Clock Generation ................................................................................................... 29

TCXO............................................................................................................................................................ 30

External 32.768 kHz Low-Power Oscillator .............................................................................................. 31

Section 4: WLAN System Interfaces................................................................................ 33

SDIO v2.0..................................................................................................................................................... 33

SDIO Pin Descriptions........................................................................................................................... 33

Generic SPI Mode ....................................................................................................................................... 35

SPI Protocol .......................................................................................................................................... 36

Command Structure ....................................................................................................................... 38

Write............................................................................................................................................... 38

Write/Read ..................................................................................................................................... 38

Read............................................................................................................................................... 38

Status ............................................................................................................................................. 39

gSPI Host-Device Handshake............................................................................................................... 41

Boot-Up Sequence ................................................................................................................................ 41

Section 5: Wireless LAN MAC and PHY .......................................................................... 44

MAC Features ............................................................................................................................................. 44

MAC Description ................................................................................................................................... 44

Broadcom ®

August 24, 2015 • 4343W-DS107-R

Single-Chip IEEE 802.11 b/g/n MAC/Baseband/Radio

Page 5

BROADCOM CONFIDENTIAL

BCM4343W Data Sheet Table of Contents

PSM ............................................................................................................................................... 45

WEP............................................................................................................................................... 46

TXE ................................................................................................................................................ 46

RXE................................................................................................................................................ 46

IFS.................................................................................................................................................. 47

TSF ................................................................................................................................................ 47

NAV................................................................................................................................................ 47

MAC-PHY Interface........................................................................................................................ 47

PHY Description ......................................................................................................................................... 48

PHY Features........................................................................................................................................ 48

Section 6: WLAN Radio Subsystem ................................................................................ 50

Receive Path ............................................................................................................................................... 51

Transmit Path.............................................................................................................................................. 51

Calibration................................................................................................................................................... 51

Section 7: Bluetooth + FM Subsystem Overview ........................................................... 52

Features....................................................................................................................................................... 52

Bluetooth Radio.......................................................................................................................................... 54

Transmit ................................................................................................................................................ 54

Digital Modulator ................................................................................................................................... 54

Digital Demodulator and Bit Synchronizer............................................................................................. 54

Power Amplifier ..................................................................................................................................... 54

Receiver ................................................................................................................................................ 55

Digital Demodulator and Bit Synchronizer............................................................................................. 55

Receiver Signal Strength Indicator........................................................................................................ 55

Local Oscillator Generation ................................................................................................................... 55

Calibration ............................................................................................................................................. 55

Section 8: Bluetooth Baseband Core .............................................................................. 56

Bluetooth 4.1 Features............................................................................................................................... 56

Link Control Layer...................................................................................................................................... 57

Test Mode Support ..................................................................................................................................... 57

Bluetooth Power Management Unit .......................................................................................................... 58

RF Power Management ........................................................................................................................ 58

Host Controller Power Management ..................................................................................................... 58

BBC Power Management...................................................................................................................... 60

FM Power Management ........................................................................................................................ 60

Wideband Speech ................................................................................................................................. 60

Packet Loss Concealment..................................................................................................................... 61

Codec Encoding .................................................................................................................................... 61

Broadcom ®

August 24, 2015 • 4343W-DS107-R

Single-Chip IEEE 802.11 b/g/n MAC/Baseband/Radio

Page 6

BROADCOM CONFIDENTIAL

BCM4343W Data Sheet Table of Contents

Multiple Simultaneous A2DP Audio Streams ........................................................................................ 61

FM Over Bluetooth ................................................................................................................................ 62

Adaptive Frequency Hopping.................................................................................................................... 62

Advanced Bluetooth/WLAN Coexistence................................................................................................. 62

Fast Connection (Interlaced Page and Inquiry Scans) ........................................................................... 62

Section 9: Microprocessor and Memory Unit for Bluetooth.......................................... 63

RAM, ROM, and Patch Memory ................................................................................................................. 63

Reset............................................................................................................................................................ 63

Section 10: Bluetooth Peripheral Transport Unit ........................................................... 64

PCM Interface.............................................................................................................................................. 64

Slot Mapping ......................................................................................................................................... 64

Frame Synchronization ......................................................................................................................... 64

Data Formatting..................................................................................................................................... 64

Wideband Speech Support ................................................................................................................... 65

Multiplexed Bluetooth and FM over PCM.............................................................................................. 65

PCM Interface Timing............................................................................................................................ 66

Short Frame Sync, Master Mode ................................................................................................... 66

Short Frame Sync, Slave Mode ..................................................................................................... 67

Long Frame Sync, Master Mode.................................................................................................... 68

Long Frame Sync, Slave Mode...................................................................................................... 69

UART Interface............................................................................................................................................ 70

I

2

S Interface................................................................................................................................................. 72

I

2

S Timing.............................................................................................................................................. 72

Section 11: FM Receiver Subsystem ............................................................................... 75

FM Radio ..................................................................................................................................................... 75

Digital FM Audio Interfaces ....................................................................................................................... 75

Analog FM Audio Interfaces ...................................................................................................................... 75

FM Over Bluetooth ..................................................................................................................................... 75

eSCO............................................................................................................................................................ 75

Wideband Speech Link .............................................................................................................................. 76

A2DP ............................................................................................................................................................ 76

Autotune and Search Algorithms ............................................................................................................. 76

Audio Features ........................................................................................................................................... 77

RDS/RBDS................................................................................................................................................... 79

Section 12: CPU and Global Functions ........................................................................... 80

WLAN CPU and Memory Subsystem........................................................................................................ 80

One-Time Programmable Memory ............................................................................................................ 80

GPIO Interface............................................................................................................................................. 81

Broadcom ®

August 24, 2015 • 4343W-DS107-R

Single-Chip IEEE 802.11 b/g/n MAC/Baseband/Radio

Page 7

BROADCOM CONFIDENTIAL

BCM4343W Data Sheet Table of Contents

External Coexistence Interface ................................................................................................................. 81

2-Wire Coexistence ............................................................................................................................... 81

3-Wire and 4-Wire Coexistence Interfaces............................................................................................ 82

JTAG Interface ........................................................................................................................................... 83

UART Interface ........................................................................................................................................... 83

Section 13: WLAN Software Architecture ....................................................................... 84

Host Software Architecture ....................................................................................................................... 84

Device Software Architecture.................................................................................................................... 84

Remote Downloader.............................................................................................................................. 85

Wireless Configuration Utility ................................................................................................................... 85

Section 14: Pinout and Signal Descriptions ................................................................... 86

Ball Map....................................................................................................................................................... 86

WLBGA Ball List in Ball Number Order with X-Y Coordinates .............................................................. 88

WLCSP Bump List in Bump Order with X-Y Coordinates....................................................................... 91

WLBGA Ball List Ordered By Ball Name .................................................................................................. 96

WLCSP Bump List Ordered By Name....................................................................................................... 97

Signal Descriptions .................................................................................................................................... 99

WLAN GPIO Signals and Strapping Options ......................................................................................... 108

Chip Debug Options................................................................................................................................. 109

I/O States ................................................................................................................................................... 109

Section 15: DC Characteristics ...................................................................................... 113

Absolute Maximum Ratings .................................................................................................................... 113

Environmental Ratings ............................................................................................................................ 114

Electrostatic Discharge Specifications .................................................................................................. 114

Recommended Operating Conditions and DC Characteristics ........................................................... 115

Section 16: WLAN RF Specifications ............................................................................ 117

2.4 GHz Band General RF Specifications............................................................................................... 117

WLAN 2.4 GHz Receiver Performance Specifications .......................................................................... 118

WLAN 2.4 GHz Transmitter Performance Specifications ..................................................................... 121

General Spurious Emissions Specifications ......................................................................................... 123

Section 17: Bluetooth RF Specifications ...................................................................... 124

Section 18: FM Receiver Specifications........................................................................ 130

Section 19: Internal Regulator Electrical Specifications ............................................. 135

Core Buck Switching Regulator.............................................................................................................. 135

3.3V LDO (LDO3P3) .................................................................................................................................. 137

CLDO ......................................................................................................................................................... 138

LNLDO ....................................................................................................................................................... 139

Broadcom ®

August 24, 2015 • 4343W-DS107-R

Single-Chip IEEE 802.11 b/g/n MAC/Baseband/Radio

Page 8

BROADCOM CONFIDENTIAL

BCM4343W Data Sheet Table of Contents

Section 20: System Power Consumption...................................................................... 140

WLAN Current Consumption................................................................................................................... 140

2.4 GHz Mode ..................................................................................................................................... 140

Bluetooth and FM Current Consumption ............................................................................................... 141

Section 21: Interface Timing and AC Characteristics .................................................. 142

SDIO Default Mode Timing ...................................................................................................................... 142

SDIO High-Speed Mode Timing............................................................................................................... 144

gSPI Signal Timing ................................................................................................................................... 145

JTAG Timing ............................................................................................................................................. 146

Section 22: Power-Up Sequence and Timing ............................................................... 147

Sequencing of Reset and Regulator Control Signals ........................................................................... 147

Description of Control Signals ............................................................................................................. 147

Control Signal Timing Diagrams.......................................................................................................... 148

Section 23: Package Information ................................................................................... 150

Package Thermal Characteristics ........................................................................................................... 150

Junction Temperature Estimation and PSI Versus Theta

jc

................................................................. 150

Section 24: Mechanical Information .............................................................................. 151

Section 25: Ordering Information .................................................................................. 155

Broadcom ®

August 24, 2015 • 4343W-DS107-R

Single-Chip IEEE 802.11 b/g/n MAC/Baseband/Radio

Page 9

BROADCOM CONFIDENTIAL

BCM4343W Data Sheet List of Figures

List of Figures

Figure 1: BCM4343W System Block Diagram ................................................................................................... 1

Figure 2: BCM4343W Block Diagram .............................................................................................................. 16

Figure 3: Typical Power Topology (1 of 2) ....................................................................................................... 21

Figure 4: Typical Power Topology (2 of 2) ....................................................................................................... 22

Figure 5: A4WP System Block Diagram .......................................................................................................... 26

Figure 6: Magnetic Coupling for Wireless Charging ........................................................................................ 27

Figure 7: An Example Multimode Wireless Charging Implementation ............................................................. 27

Figure 8: BCM4343W Interface to a BCM59350 ............................................................................................. 28

Figure 9: Recommended Oscillator Configuration ........................................................................................... 29

Figure 10: Recommended Circuit to Use with an External Dedicated TCXO .................................................. 30

Figure 11: Signal Connections to SDIO Host (SD 4-Bit Mode)........................................................................ 33

Figure 12: Signal Connections to SDIO Host (SD 1-Bit Mode)........................................................................ 34

Figure 13: Signal Connections to SDIO Host (gSPI Mode) ............................................................................. 35

Figure 14: gSPI Write Protocol ........................................................................................................................ 36

Figure 15: gSPI Read Protocol ........................................................................................................................ 37

Figure 16: gSPI Command Structure............................................................................................................... 38

Figure 17: gSPI Signal Timing Without Status................................................................................................. 39

Figure 18: gSPI Signal Timing with Status (Response Delay = 0)................................................................... 40

Figure 19: WLAN Boot-Up Sequence .............................................................................................................. 43

Figure 20: WLAN MAC Architecture ................................................................................................................ 45

Figure 21: WLAN PHY Block Diagram............................................................................................................. 49

Figure 22: Radio Functional Block Diagram .................................................................................................... 50

Figure 23: Startup Signaling Sequence ........................................................................................................... 59

Figure 24: CVSD Decoder Output Waveform Without PLC............................................................................. 61

Figure 25: CVSD Decoder Output Waveform After Applying PLC................................................................... 61

Figure 26: Functional Multiplex Data Diagram................................................................................................. 65

Figure 27: PCM Timing Diagram (Short Frame Sync, Master Mode) .............................................................. 66

Figure 28: PCM Timing Diagram (Short Frame Sync, Slave Mode) ................................................................ 67

Figure 29: PCM Timing Diagram (Long Frame Sync, Master Mode)............................................................... 68

Figure 30: PCM Timing Diagram (Long Frame Sync, Slave Mode)................................................................. 69

Figure 31: UART Timing .................................................................................................................................. 71

Figure 32: I

2

S Transmitter Timing.................................................................................................................... 74

Figure 33: I

2

S Receiver Timing........................................................................................................................ 74

Figure 34: Blending and Switching Usage ....................................................................................................... 77

Figure 35: Blending and Switching Separation ................................................................................................ 78

Broadcom

®

August 24, 2015 • 4343W-DS107-R

Single-Chip IEEE 802.11 b/g/n MAC/Baseband/Radio

Page 10

BROADCOM CONFIDENTIAL

BCM4343W Data Sheet List of Figures

Figure 36: Soft Muting Characteristic............................................................................................................... 78

Figure 37: 2-Wire Coexistence Interface to an LTE IC .................................................................................... 81

Figure 38: 3-Wire Coexistence Interface to an LTE IC .................................................................................... 82

Figure 39: 4-Wire Coexistence Interface to an LTE IC .................................................................................... 83

Figure 40: WLAN Software Architecture .......................................................................................................... 85

Figure 41: 74-Ball WLBGA Ball Map (Bottom View) ........................................................................................ 86

Figure 42: 153-Bump WLCSP (Top View) ....................................................................................................... 87

Figure 43: RF Port Location........................................................................................................................... 117

Figure 44: SDIO Bus Timing (Default Mode) ................................................................................................. 142

Figure 45: SDIO Bus Timing (High-Speed Mode).......................................................................................... 144

Figure 46: gSPI Timing .................................................................................................................................. 145

Figure 47: WLAN = ON, Bluetooth = ON ....................................................................................................... 148

Figure 48: WLAN = OFF, Bluetooth = OFF.................................................................................................... 148

Figure 49: WLAN = ON, Bluetooth = OFF ..................................................................................................... 148

Figure 50: WLAN = OFF, Bluetooth = ON ..................................................................................................... 149

Figure 51: 74-Ball WLBGA Mechanical Information ...................................................................................... 151

Figure 52: 153-Bump WLCSP Mechanical Information ................................................................................. 152

Figure 53: WLCSP Package Keep-Out Areas—Top View with the Bumps Facing Down ............................ 153

Figure 54: WLBGA Package Keep-Out Areas—Top View with the Bumps Facing Down ............................ 154

Broadcom

®

August 24, 2015 • 4343W-DS107-R

Single-Chip IEEE 802.11 b/g/n MAC/Baseband/Radio

Page 11

BROADCOM CONFIDENTIAL

BCM4343W Data Sheet List of Tables

List of Tables

Table 1: Power-Up/Power-Down/Reset Control Signals.................................................................................. 25

Table 2: Crystal Oscillator and External Clock Requirements and Performance............................................. 30

Table 3: External 32.768 kHz Sleep-Clock Specifications ............................................................................... 31

Table 4: SDIO Pin Descriptions ....................................................................................................................... 33

Table 5: gSPI Status Field Details ................................................................................................................... 40

Table 6: gSPI Registers ................................................................................................................................... 41

Table 7: Power Control Pin Description ........................................................................................................... 58

Table 8: PCM Interface Timing Specifications (Short Frame Sync, Master Mode).......................................... 66

Table 9: PCM Interface Timing Specifications (Short Frame Sync, Slave Mode)............................................ 67

Table 10: PCM Interface Timing Specifications (Long Frame Sync, Master Mode) ........................................ 68

Table 11: PCM Interface Timing Specifications (Long Frame Sync, Slave Mode) .......................................... 69

Table 12: Example of Common Baud Rates.................................................................................................... 70

Table 13: UART Timing Specifications ............................................................................................................ 71

Table 14: Timing for I

2

S Transmitters and Receivers ...................................................................................... 73

Table 15: BCM4343W WLBGA Ball List — Ordered By Ball Number ............................................................. 88

Table 16: BCM4343W WLCSP Bump List — Ordered By Bump Number....................................................... 91

Table 17: BCM4343W WLBGA Ball List — Ordered By Ball Name ................................................................ 96

Table 18: BCM4343W WLCSP Bump List — Ordered By Bump Name .......................................................... 97

Table 19: WLBGA Signal Descriptions ............................................................................................................ 99

Table 20: WLCSP Signal Descriptions .......................................................................................................... 103

Table 21: GPIO Functions and Strapping Options......................................................................................... 108

Table 22: Chip Debug Options....................................................................................................................... 109

Table 23: I/O States ....................................................................................................................................... 110

Table 24: Absolute Maximum Ratings ........................................................................................................... 113

Table 25: Environmental Ratings................................................................................................................... 114

Table 26: ESD Specifications ........................................................................................................................ 114

Table 27: Recommended Operating Conditions and DC Characteristics...................................................... 115

Table 28: 2.4 GHz Band General RF Specifications...................................................................................... 117

Table 29: WLAN 2.4 GHz Receiver Performance Specifications .................................................................. 118

Table 30: WLAN 2.4 GHz Transmitter Performance Specifications .............................................................. 121

Table 31: General Spurious Emissions Specifications .................................................................................. 123

Table 32: Bluetooth Receiver RF Specifications............................................................................................ 124

Table 33: LTE Specifications for Spurious Emissions ................................................................................... 127

Table 34: Bluetooth Transmitter RF Specifications........................................................................................ 128

Table 35: LTE Specifications for Out-of-Band Noise Floor ............................................................................ 129

Broadcom

®

August 24, 2015 • 4343W-DS107-R

Single-Chip IEEE 802.11 b/g/n MAC/Baseband/Radio

Page 12

BROADCOM CONFIDENTIAL

BCM4343W Data Sheet List of Tables

Table 36: Local Oscillator Performance......................................................................................................... 129

Table 37: BLE RF Specifications ................................................................................................................... 129

Table 38: FM Receiver Specifications ........................................................................................................... 130

Table 39: Core Buck Switching Regulator (CBUCK) Specifications .............................................................. 135

Table 40: LDO3P3 Specifications .................................................................................................................. 137

Table 41: CLDO Specifications...................................................................................................................... 138

Table 42: LNLDO Specifications.................................................................................................................... 139

Table 43: 2.4 GHz Mode WLAN Power Consumption ................................................................................... 140

Table 44: Bluetooth BLE and FM Current Consumption................................................................................ 141

Table 45: SDIO Bus Timing Parameters (Default Mode).............................................................................. 143

Table 46: SDIO Bus Timing Parameters (High-Speed Mode) ...................................................................... 144

Table 47: gSPI Timing Parameters................................................................................................................ 145

Table 48: JTAG Timing Characteristics ......................................................................................................... 146

Table 49: Package Thermal Characteristics .................................................................................................. 150

Table 50: Part Ordering Information .............................................................................................................. 155

Broadcom

®

August 24, 2015 • 4343W-DS107-R

Single-Chip IEEE 802.11 b/g/n MAC/Baseband/Radio

Page 13

BROADCOM CONFIDENTIAL

BCM4343W Data Sheet About This Document

About This Document

Purpose and Audience

This document provides details of the functional, operational, and electrical characteristics of the

Broadcom

®

BCM4343W. It is intended for hardware design, application, and OEM engineers.

Acronyms and Abbreviations

In most cases, acronyms and abbreviations are defined on first use.

For a comprehensive list of acronyms and other terms used in Broadcom documents, go to: http://www.broadcom.com/press/glossary.php

.

Document Conventions

The following conventions may be used in this document:

Convention

Bold

Monospace

< >

[ ]

Description

User input and actions: for example, type exit, click OK, press Alt+C

Code: #include <iostream>

HTML: <td rowspan = 3>

Command line commands and parameters: wl [‐l] <command>

Placeholders for required elements: enter your <username> or wl <command>

Indicates optional command-line parameters: wl [‐l]

Indicates bit and byte ranges (inclusive): [0:3] or [7:0]

Technical Support

Broadcom provides customer access to a wide range of information, including technical documentation, schematic diagrams, product bill of materials, PCB layout information, and software updates through its customer support portal ( https://support.broadcom.com

). For a CSP account, contact your Sales or Engineering support representative.

In addition, Broadcom provides other product support through its Downloads and Support site

( http://www.broadcom.com/support/ ).

Broadcom

®

August 24, 2015 • 4343W-DS107-R

Single-Chip IEEE 802.11 b/g/n MAC/Baseband/Radio

Page 14

BROADCOM CONFIDENTIAL

BCM4343W Data Sheet Overview

Section 1: Overview

Overview

The Broadcom

®

BCM4343W provides the highest level of integration for a mobile or handheld wireless system, with integrated IEEE 802.11 b/g/n. It provides a small form-factor solution with minimal external components to drive down cost for mass volumes and allows for handheld device flexibility in size, form, and function. The

BCM4343W is designed to address the needs of highly mobile devices that require minimal power consumption and reliable operation.

Figure 2 on page 16

shows the interconnection of all the major physical blocks in the BCM4343W and their associated external interfaces, which are described in greater detail in subsequent sections.

Broadcom

®

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BROADCOM CONFIDENTIAL

BCM4343W Data Sheet

Figure 2: BCM4343W Block Diagram

FM_RX

Digital

I/O

LNA

RSSI

LO

Gen.

FM RF

FM RX

ADC

ADC

FM Digital

FM Demod. 

MDX RDS 

Decode

FM

I/F

Control

DPLL

UART

Debug 

UART

I

2

S/PCM

GPIO

Wake/

WiMax 

Coex.

PTU

BPL

Buffer

APU

BT Clock/ 

Hopper

BlueRF 

Interface

LCU

RX/TX

Buffer

Modem

Digital 

Demod. 

& Bit 

Sync

Digital

Mod.

RF

PA

Sleep‐ time 

Keeping

BT PHY

BTFM Clock Control

Clock 

Management

PMU

LPO

XO 

Buffer

PMU 

Ctrl

POR

IF

PLL

AHB

Cortex

M3

Debug

AHB to APB 

Bridge

APB

WD Timer

SW Timer

GPIO

Ctrl

SDIO gSPI

ARM

CM3

RAM

ROM

RAM

ROM

Patch

InterCtrl

DMA

Bus Arb 

ARM IP

PMU

Control

JTAG supported over SDIO or BT PCM

SDIO or gSPI

SWREG

LDOx2

LPO

XTAL OSC.

POR

Power

Supply

Sleep CLK

XTAL

WL_REG_ON

WDT

OTP

GPIO

UART

JTAG*

GPIO

UART

Supported over SDIO or BT PCM

BT‐WLAN

ECI

2.4 GHz

PA

Shared LNA

BPF

WLAN

Overview

* Via GPIO configuration, JTAG is supported over SDIO or BT PCM

Broadcom ®

August 24, 2015 • 4343W-DS107-R

BROADCOM CONFIDENTIAL

Single-Chip IEEE 802.11 b/g/n MAC/Baseband/Radio

Page 16

BCM4343W Data Sheet Features

Features

The BCM4343W supports the following WLAN, Bluetooth, and FM features:

• IEEE 802.11b/g/n single-band radio with an internal power amplifier, LNA, and T/R switch

• Bluetooth v4.1 with integrated Class 1 PA

• Concurrent Bluetooth, FM (RX) RDS/RBDS, and WLAN operation

• On-chip WLAN driver execution capable of supporting IEEE 802.11 functionality

• Simultaneous BT/WLAN reception with a single antenna

• WLAN host interface options:

– SDIO v2.0, including default and high-speed timing.

– gSPI—up to a 50 MHz clock rate

• BT UART (up to 4 Mbps) host digital interface that can be used concurrently with the above WLAN host interfaces.

• ECI—enhanced coexistence support, which coordinates BT SCO transmissions around WLAN receptions.

• I

2

S/PCM for FM/BT audio, HCI for FM block control

• HCI high-speed UART (H4 and H5) transport support

• Wideband speech support (16 bits, 16 kHz sampling PCM, through I

2

S and PCM interfaces)

• Bluetooth SmartAudio

®

technology improves voice and music quality to headsets.

• Bluetooth low power inquiry and page scan

• Bluetooth Low Energy (BLE) support

• Bluetooth Packet Loss Concealment (PLC)

• FM advanced internal antenna support

• FM auto searching/tuning functions

• FM multiple audio routing options: I

2

S, PCM, eSCO, and A2DP

• FM mono-stereo blending and switching, and soft mute support

• FM audio pause detection support

• Multiple simultaneous A2DP audio streams

• FM over Bluetooth operation and on-chip stereo headset emulation

Broadcom

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August 24, 2015 • 4343W-DS107-R

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BROADCOM CONFIDENTIAL

BCM4343W Data Sheet Standards Compliance

Standards Compliance

The BCM4343W supports the following standards:

• Bluetooth 2.1 + EDR

• Bluetooth 3.0

• Bluetooth 4.1 (Bluetooth Low Energy)

• 65 MHz to 108 MHz FM bands (US, Europe, and Japan)

• IEEE 802.11n—Handheld Device Class (Section 11)

• IEEE 802.11b

• IEEE 802.11g

• IEEE 802.11d

• IEEE 802.11h

• IEEE 802.11i

The BCM4343W will support the following future drafts/standards:

• IEEE 802.11r — Fast Roaming (between APs)

• IEEE 802.11k — Resource Management

• IEEE 802.11w — Secure Management Frames

• IEEE 802.11 Extensions:

• IEEE 802.11e QoS Enhancements (as per the WMM

®

specification is already supported)

• IEEE 802.11i MAC Enhancements

• IEEE 802.11r Fast Roaming Support

• IEEE 802.11k Radio Resource Measurement

The BCM4343W supports the following security features and proprietary protocols:

• Security:

– WEP

– WPA

Personal

– WPA2

Personal

– WMM

– WMM-PS (U-APSD)

– WMM-SA

– WAPI

– AES (Hardware Accelerator)

– TKIP (host-computed)

– CKIP (SW Support)

• Proprietary Protocols:

– CCXv2

– CCXv3

– CCXv4

– CCXv5

• IEEE 802.15.2 Coexistence Compliance — on silicon solution compliant with IEEE 3-wire requirements.

Broadcom

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BROADCOM CONFIDENTIAL

BCM4343W Data Sheet Power Supplies and Power Management

Section 2: Power Supplies and Power

Management

Power Supply Topology

One Buck regulator, multiple LDO regulators, and a power management unit (PMU) are integrated into the

BCM4343W. All regulators are programmable via the PMU. These blocks simplify power supply design for

Bluetooth, WLAN, and FM functions in embedded designs.

A single VBAT (3.0V to 4.8V DC maximum) and VDDIO supply (1.8V to 3.3V) can be used, with all additional voltages being provided by the regulators in the BCM4343W.

Two control signals, BT_REG_ON and WL_REG_ON, are used to power up the regulators and take the respective circuit blocks out of reset. The CBUCK CLDO and LNLDO power up when any of the reset signals are deasserted. All regulators are powered down only when both BT_REG_ON and WL_REG_ON are deasserted. The CLDO and LNLDO can be turned on and off based on the dynamic demands of the digital baseband.

The BCM4343W allows for an extremely low power-consumption mode by completely shutting down the

CBUCK, CLDO, and LNLDO regulators. When in this state, LPLDO1 provides the BCM4343W with all required voltage, further reducing leakage currents.

Note: VBAT should be connected to the LDO_VDDBAT5V and SR_VDDBAT5V pins of the device.

Note: VDDIO should be connected to the SYS_VDDIO and WCC_VDDIO pins of the device.

Broadcom

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BROADCOM CONFIDENTIAL

BCM4343W Data Sheet BCM4343W PMU Features

BCM4343W PMU Features

The PMU supports the following:

• VBAT to 1.35Vout (170 mA nominal, 370 mA maximum) Core-Buck (CBUCK) switching regulator

• VBAT to 3.3Vout (250 mA nominal, 450 mA maximum 800 mA peak maximum) LDO3P3

• 1.35V to 1.2Vout (100 mA nominal, 150 mA maximum) LNLDO

• 1.35V to 1.2Vout (80 mA nominal, 200 mA maximum) CLDO with bypass mode for deep sleep

• Additional internal LDOs (not externally accessible)

• PMU internal timer auto-calibration by the crystal clock for precise wake-up timing from extremely low power-consumption mode.

• PMU input supplies automatic sensing and fast switching to support A4WP operations.

Figure 3 on page 21

and

Figure 4 on page 22 show the typical power topology of the BCM4343W.

Broadcom

®

August 24, 2015 • 4343W-DS107-R

Single-Chip IEEE 802.11 b/g/n MAC/Baseband/Radio

Page 20

BROADCOM CONFIDENTIAL

BCM4343W Data Sheet

BCM4343W PMU Features

Figure 3: Typical Power Topology (1 of 2)

BCM4343W

1.2V

VBAT:

Operational:

Performance:

2.4—4.8V

3.0—4.8V

Absolute Maximum: 5.5V

VDDIO

Operational: 1.8—3.3V

VBAT

1.35V

SR_VDDBAT5V

VDD1P35

Int_SR_VBAT

(320 mA)

SW1

Core Buck 

Regulator 

Peak: 370 mA

Avg: 170 mA

VBAT

SR_VBAT5V

SR_VLX

2.2 uH

0603

SR_PVSS

4.7 uF

0402

GND

PMU_VSS

LDO_VDD_1P5

Mini PMU

Internal VCOLDO

80 mA (NMOS)

Internal RXLDO

10 mA (NMOS)

Internal ADCLDO

10 mA (NMOS)

Internal TXLDO

80 mA (PMOS)

Internal AFELDO

80 mA (NMOS)

Mini PMU is placed  in WL radio

LNLDO

(100 mA)

1.2V

VOUT_LNLDO

1.2V

1.2V

1.2V

1.2V

1.2V

600 @

100 MHz

2.2 uF

0402

0.1 uF

0201

WL RF—TX Mixer and PA

(not all versions)

WLRF_XTAL_

VDD1P2

FM_RFVDD

FM_RFPLL

WL RF—LOGEN

WL RF—RX LNA

WL RF—ADC REF

WL RF—TX

WL RF—AFE and TIA

10 mA average, 

> 10 mA at start‐up

WL RF—RFPLL PFD and MMD

WL RF—XTAL

FM LNA, Mixer

4.6 mA

FM PLL, LOGEN, Audio DAC

Broadcom ®

WCC_VDDIO

WCC_VDDIO

(40 mA)

SYS_VDDIO

WPT_1P8

SYS_VDDIO

(40 mA)

VSEL1

(40 mA)

WPT_1P8 o_wpt_resetb

WL_REG_ON

BT_REG_ON o_wl_resetb o_bt_resetb

Supply ball

Ground ball

BT/WLAN reset balls

Supply bump/pad

Ground bump/pad

External to chip

LPLDO1

(5 mA)

1.1V

WPTLDO

(40 mA)

1.3V

CL LDO

Peak: 200 mA

Avg: 80 mA

(Bypass in deep‐ sleep)

1.3V, 1.2V,  or 0.95V

(AVS)

VOUT_CLDO

2.2 uF

0402

Power switch

No power switch

No dedicated power switch, but internal power‐ down modes and block‐specific power switches

VDDC1

VDDC2

August 24, 2015 • 4343W-DS107-R

WLAN/BT/CLB/Top, Always On

WL OTP

WL Digital and PHY

WL VDDM (SROMs & AOS)

BT VDDM

BT Digital

Single-Chip IEEE 802.11 b/g/n MAC/Baseband/Radio

Page 21

BROADCOM CONFIDENTIAL

BCM4343W Data Sheet

BCM4343W PMU Features

Figure 4: Typical Power Topology (2 of 2)

BCM4343W

1.8V, 2.5V, and 3.3V

6.4 mA

WL BBPLL/DFLL

VBAT

LDO_

VDDBAT5V

LDO3P3 with

Back‐Power 

Protection

(Peak 450‐800 mA

200 mA Average) 3.3V

VOUT_3P3

4.7 uF

0402

WPT_3P3

SW2

Peak: 92 mA

Average: 75 mA

Resistance: 1 ohm

22  ohm

WLRF_PA_VDD

1 uF

0201

2.5V Cap‐less 

LNLDO

(10 mA)

WL OTP 3.3V

480 to 800 mA

WL RF—PA (2.4 GHz)

6.4 mA

WL RF—ADC, AFE, LOGEN, 

LNA, NMOS Mini‐PMU LDOs

1 uF

0201

BT_PAVDD

Placed inside WL Radio

Peak: 70 mA

Average: 15 mA

BT Class 1 PA

External to chip

Supply ball

Power switch

No power switch

No dedicated power switch, but internal power‐ down modes and block‐specific power switches

Broadcom ®

August 24, 2015 • 4343W-DS107-R

BROADCOM CONFIDENTIAL

Single-Chip IEEE 802.11 b/g/n MAC/Baseband/Radio

Page 22

BCM4343W Data Sheet WLAN Power Management

WLAN Power Management

The BCM4343W has been designed with the stringent power consumption requirements of mobile devices in mind. All areas of the chip design are optimized to minimize power consumption. Silicon processes and cell libraries were chosen to reduce leakage current and supply voltages. Additionally, the BCM4343W integrated

RAM is a high volatile memory with dynamic clock control. The dominant supply current consumed by the RAM is leakage current only. Additionally, the BCM4343W includes an advanced WLAN power management unit

(PMU) sequencer. The PMU sequencer provides significant power savings by putting the BCM4343W into various power management states appropriate to the operating environment and the activities that are being performed. The power management unit enables and disables internal regulators, switches, and other blocks based on a computation of the required resources and a table that describes the relationship between resources and the time needed to enable and disable them. Power-up sequences are fully programmable. Configurable, free-running counters (running at the 32.768 kHz LPO clock) in the PMU sequencer are used to turn on/turn off individual regulators and power switches. Clock speeds are dynamically changed (or gated altogether) for the current mode. Slower clock speeds are used wherever possible.

The BCM4343W WLAN power states are described as follows:

• Active mode— All WLAN blocks in the BCM4343W are powered up and fully functional with active carrier sensing and frame transmission and receiving. All required regulators are enabled and put in the most efficient mode based on the load current. Clock speeds are dynamically adjusted by the PMU sequencer.

• Doze mode—The radio, analog domains, and most of the linear regulators are powered down. The rest of the BCM4343W remains powered up in an IDLE state. All main clocks (PLL, crystal oscillator) are shut down to reduce active power to the minimum. The 32.768 kHz LPO clock is available only for the PMU sequencer. This condition is necessary to allow the PMU sequencer to wake up the chip and transition to

Active mode. In Doze mode, the primary power consumed is due to leakage current.

• Deep-sleep mode—Most of the chip, including analog and digital domains, and most of the regulators are powered off. Logic states in the digital core are saved and preserved to retention memory in the always-on domain before the digital core is powered off. To avoid lengthy hardware reinitialization, the logic states in the digital core are restored to their pre-deep-sleep settings when a wake-up event is triggered by an external interrupt, a host resume through the SDIO bus, or by the PMU timers.

• Power-down mode—The BCM4343W is effectively powered off by shutting down all internal regulators.

The chip is brought out of this mode by external logic re-enabling the internal regulators.

Broadcom

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BROADCOM CONFIDENTIAL

BCM4343W Data Sheet PMU Sequencing

PMU Sequencing

The PMU sequencer is used to minimize system power consumption. It enables and disables various system resources based on a computation of required resources and a table that describes the relationship between resources and the time required to enable and disable them.

Resource requests can derive from several sources: clock requests from cores, the minimum resources defined in the ResourceMin register, and the resources requested by any active resource request timers. The PMU sequencer maps clock requests into a set of resources required to produce the requested clocks.

Each resource is in one of the following four states:

• enabled

• disabled

• transition_on

• transition_off

The timer value is 0 when the resource is enabled or disabled and nonzero during state transition. The timer is loaded with the time_on or time_off value of the resource when the PMU determines that the resource must be enabled or disabled. That timer decrements on each 32.768 kHz PMU clock. When it reaches 0, the state changes from transition_off to disabled or transition_on to enabled. If the time_on value is 0, the resource can transition immediately from disabled to enabled. Similarly, a time_off value of 0 indicates that the resource can transition immediately from enabled to disabled. The terms enable sequence and disable sequence refer to either the immediate transition or the timer load-decrement sequence.

During each clock cycle, the PMU sequencer performs the following actions:

• Computes the required resource set based on requests and the resource dependency table.

• Decrements all timers whose values are nonzero. If a timer reaches 0, the PMU clears the

ResourcePending bit for the resource and inverts the ResourceState bit.

• Compares the request with the current resource status and determines which resources must be enabled or disabled.

• Initiates a disable sequence for each resource that is enabled, no longer being requested, and has no powered-up dependents.

• Initiates an enable sequence for each resource that is disabled, is being requested, and has all of its dependencies enabled.

Broadcom

®

August 24, 2015 • 4343W-DS107-R

Single-Chip IEEE 802.11 b/g/n MAC/Baseband/Radio

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BROADCOM CONFIDENTIAL

BCM4343W Data Sheet Power-Off Shutdown

Power-Off Shutdown

The BCM4343W provides a low-power shutdown feature that allows the device to be turned off while the host, and any other devices in the system, remain operational. When the BCM4343W is not needed in the system,

VDDIO_RF and VDDC are shut down while VDDIO remains powered. This allows the BCM4343W to be effectively off while keeping the I/O pins powered so that they do not draw extra current from any other devices connected to the I/O.

During a low-power shutdown state, provided VDDIO remains applied to the BCM4343W, all outputs are tristated, and most input signals are disabled. Input voltages must remain within the limits defined for normal operation. This is done to prevent current paths or create loading on any digital signals in the system, and enables the BCM4343W to be fully integrated in an embedded device and to take full advantage of the lowest power-savings modes.

When the BCM4343W is powered on from this state, it is the same as a normal power-up, and the device does not retain any information about its state from before it was powered down.

Power-Up/Power-Down/Reset Circuits

The BCM4343W has two signals (see

Table 1

) that enable or disable the Bluetooth and WLAN circuits and the internal regulator blocks, allowing the host to control power consumption. For timing diagrams of these signals and the required power-up sequences, see

Section 22: “Power-Up Sequence and Timing,” on page 147

.

Table 1: Power-Up/Power-Down/Reset Control Signals

Signal Description

WL_REG_ON This signal is used by the PMU (with BT_REG_ON) to power-up the WLAN section. It is also

OR-gated with the BT_REG_ON input to control the internal BCM4343W regulators. When this pin is high, the regulators are enabled and the WLAN section is out of reset. When this pin is low, the WLAN section is in reset. If BT_REG_ON and WL_REG_ON are both low, the regulators are disabled. This pin has an internal 200 k

 pull-down resistor that is enabled by default. It can be disabled through programming.

BT_REG_ON This signal is used by the PMU (with WL_REG_ON) to decide whether or not to power down the internal BCM4343W regulators. If BT_REG_ON and WL_REG_ON are low, the regulators will be disabled. This pin has an internal 200 k

 pull-down resistor that is enabled by default.

It can be disabled through programming.

Broadcom

®

August 24, 2015 • 4343W-DS107-R

Single-Chip IEEE 802.11 b/g/n MAC/Baseband/Radio

Page 25

BROADCOM CONFIDENTIAL

BCM4343W Data Sheet Wireless Charging

Wireless Charging

The BCM4343W, when paired with a Broadcom BCM5935X wireless power transfer (WPT) front-end device, complies with the following three wireless charging standards:

• Alliance for Wireless Power (A4WP)

• Wireless Power Consortium (WPC)

• Power Matters Alliance (PMA)

To support the WPC and PMA standards, control-plane signaling is accomplished using in-band signaling between the BCM5935X WPT front-end device (located in the power receiving entity) and the power transmitting wireless charger.

To support the A4WP standard, energy is transferred from a Power Transmitting Unit (PTU) to a Power

Receiving Unit (PRU). The energy transferred charges the PRU battery. Bidirectional communication between the PTU and PRU is accomplished using Bluetooth Low Energy (BLE), where the PTU is a BLE client and the

PRU is a BLE server. Using a BLE link, the PRU sends performance data to the PTU so that it can adapt its power output to meet the needs of the PRU.

The most common use for wireless charging is to charge a mobile device battery.

Figure 5

shows a simple block diagram of a system that supports the A4WP standard.

Figure 5: A4WP System Block Diagram

BT

Power Receiving Unit

(PRU)

A4WP‐Compatible Mobile Device

BLE Server

Wireless Power Transfer at 6.78 MHz

Power Transmitting Unit

(PTU) aka Power Plate

BLE Client

BT

Bluetooth low‐energy (BLE) bidirectional  communication enables the transmitter to  adapt to mobile device system needs.

Note: A single PTU can be used to charge multiple devices.

Broadcom

®

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BROADCOM CONFIDENTIAL

BCM4343W Data Sheet Wireless Charging

Figure 6

shows an example of the magnetic coupling between a single PTU and one or more PRUs.

Figure 6: Magnetic Coupling for Wireless Charging

Power Transmitting 

Unit

Power Receiving Unit(s)

RX1

TX RX2

RX3

Figure 7

shows an example A4WP-compliant wireless charging implementation.

Figure 7: An Example Multimode Wireless Charging Implementation

WPC/PMA

Coil

A4WP

Coil

Motherboard

BSC

BSC

NTC

Bridge 

Rectifier

BSC IF

Slave

WPT Front End (Power IC)

Load

Control

Voltage 

Regulator

3.3V

LDO

Power 

Monitoring/

Control

WPT_IRQ

1.8V

LDO

VBAT

SPDT

1V8

SPDT

BCM5935X

USB External Charger

Battery 

Charging

V1P8SYS

VBAT

WPT_3V3 (VBAT)

WPT_1V8 (VDDIO)

SYS_VDDIO,

WCC_VDDIO

PMU

VDDIO VBAT

Host (AP)

BT_REG_ON

LDO_VDDBAT5V,

SR_VDDBAT5V

WL_REG_ON

PMU

Wake‐Up

Internal

Power

POR

WPT_IRQ

BSC_CLK

BSC_SDA

NFC_GPIO NFC IC

BT_VDDIO Domain

OTP for A4WPT 

Parameters

BCM4343W

Broadcom

®

August 24, 2015 • 4343W-DS107-R

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Page 27

BROADCOM CONFIDENTIAL

BCM4343W Data Sheet

Figure 8

shows the signal interface between a BCM4343W and a BCM59350.

Figure 8: BCM4343W Interface to a BCM59350

BCM4343W

BT_GPIO_3 (WPT_INTb)

BT_GPIO_4 (BSC_SDA)

BT_GPIO_5 (BSC_SCL)

BCM59350 

Wireless 

Charging PMU

Wireless Charging

Broadcom

®

August 24, 2015 • 4343W-DS107-R

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BROADCOM CONFIDENTIAL

BCM4343W Data Sheet Frequency References

Section 3: Frequency References

An external crystal is used for generating all radio frequencies and normal operation clocking. As an alternative, an external frequency reference driven by a temperature-compensated crystal oscillator (TCXO) signal may be used. No software settings are required to differentiate between the two. In addition, a low-power oscillator

(LPO) is provided for lower power mode timing.

Crystal Interface and Clock Generation

The BCM4343W can use an external crystal to provide a frequency reference. The recommended configuration

for the crystal oscillator, including all external components, is shown in Figure 9

. Consult the reference schematics for the latest configuration.

Figure 9: Recommended Oscillator Configuration

C

WLRF_XTAL_XOP

12 – 27 pF

C

WLRF_XTAL_XON

R

12 – 27 pF

Note: Resistor value determined by crystal drive level.

See reference schematics for details.

The BCM4343W uses a fractional-N synthesizer to generate the radio frequencies, clocks, and data/packet timing so that it can operate using numerous frequency references. The frequency reference can be an external source such as a TCXO or a crystal interfaced directly to the BCM4343W.

The default frequency reference setting is a 37.4 MHz crystal or TCXO. The signal requirements and

characteristics for the crystal interface are shown in Table 2 on page 30 .

Note: Although the fractional-N synthesizer can support many reference frequencies, frequencies other than the default require support to be added in the driver, plus additional extensive system testing. Contact Broadcom for further details.

Broadcom

®

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BROADCOM CONFIDENTIAL

BCM4343W Data Sheet TCXO

TCXO

As an alternative to a crystal, an external precision TCXO can be used as the frequency reference, provided that it meets the phase noise requirements listed in

Table 2 on page 30 .

If the TCXO is dedicated to driving the BCM4343W, it should be connected to the WLRF_XTAL_XOP pin through an external capacitor with value ranges from 200 pF to 1000 pF as shown in

Figure 10 .

Figure 10: Recommended Circuit to Use with an External Dedicated TCXO

200 pF – 1000 pF

TCXO

NC

WLRF_XTAL_XOP

WLRF_XTAL_XON

Parameter

Frequency

Crystal load capacitance

ESR

Drive level

Table 2: Crystal Oscillator and External Clock Requirements and Performance

Conditions/Notes

External crystal must be able to tolerate this drive level.

Resistive

Capacitive

AC-coupled analog signal

Crystal

External Frequency

Reference

Min. Typ. Max.

Min.

Typ. Max.

37.4

12 a

– –

200 –

60

400 b

10k 100k –

7

1260

Units

MHz pF

μW

Ω pF mV p-p

Input Impedance

(WLRF_XTAL_XOP)

WLRF_XTAL_XOP input voltage

WLRF_XTAL_XOP input low level

WLRF_XTAL_XOP input high level

Frequency tolerance

Initial + over temperature

Duty cycle

Phase Noise c, d, e

(IEEE 802.11 b/g)

DC-coupled digital signal

DC-coupled digital signal

37.4 MHz clock

–20 –

37.4 MHz clock at 10 kHz offset –

37.4 MHz clock at 100 kHz offset –

20

0

1.0

–20

40

50

0.2

1.26

20

60

–129

–136

V

V ppm

% dBc/Hz dBc/Hz

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BCM4343W Data Sheet External 32.768 kHz Low-Power Oscillator

Table 2: Crystal Oscillator and External Clock Requirements and Performance (Cont.)

Crystal

External Frequency

Reference

Parameter

Phase Noise c, d, e

(IEEE 802.11n,

2.4 GHz)

Phase Noise c, d, e

(256-QAM)

Conditions/Notes Min. Typ. Max.

Min.

Typ. Max.

37.4 MHz clock at 10 kHz offset –

37.4 MHz clock at 100 kHz offset –

37.4 MHz clock at 10 kHz offset –

37.4 MHz clock at 100 kHz offset –

–134

–141

–140

–147

Units

dBc/Hz dBc/Hz dBc/Hz dBc/Hz a. The frequency step size is approximately 80 Hz. The BCM4343W does not auto-detect the reference clock frequency; the frequency is specified in the software and/or NVRAM file.

b. To use 256-QAM, a 800 mV minimum voltage is required.

c. For a clock reference other than 37.4 MHz, 20 × log10(f/37.4) dB should be added to the limits, where f = the reference clock frequency in MHz.

d. Phase noise is assumed flat above 100 kHz.

e. The BCM4343W supports a 26 MHz reference clock sharing option. See the phase noise requirement in the table.

External 32.768 kHz Low-Power Oscillator

The BCM4343W uses a secondary low-frequency sleep clock for low-power mode timing. Either the internal low-precision LPO or an external 32.768 kHz precision oscillator is required. The internal LPO frequency range is approximately 33 kHz ± 30% over process, voltage, and temperature, which is adequate for some applications. However, one trade-off caused by this wide LPO tolerance is a small current consumption increase during power save mode that is incurred by the need to wake up earlier to avoid missing beacons.

Whenever possible, the preferred approach is to use a precision external 32.768 kHz clock that meets the requirements listed in

Table 3 on page 31

.

Note:

The BCM4343W will auto-detect the LPO clock. If it senses a clock on the EXT_SLEEP_CLK pin, it will use that clock. If it doesn't sense a clock, it will use its own internal LPO.

• To use the internal LPO: Tie EXT_SLEEP_CLK to ground. Do not leave this pin floating.

• To use an external LPO: Connect the external 32.768 kHz clock to EXT_SLEEP_CLK.

Parameter

Nominal input frequency

Frequency accuracy

Duty cycle

Input signal amplitude

Signal type

Table 3: External 32.768 kHz Sleep-Clock Specifications

LPO Clock

32.768

±200

30–70

200–3300

Square wave or sine wave

Units

kHz ppm

% mV, p-p

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BCM4343W Data Sheet External 32.768 kHz Low-Power Oscillator

Parameter

Input impedance

Clock jitter a

Table 3: External 32.768 kHz Sleep-Clock Specifications (Cont.)

LPO Clock

>100

<5

<10,000 a. When power is applied or switched off.

Units

kΩ pF ppm

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BCM4343W Data Sheet WLAN System Interfaces

Section 4: WLAN System Interfaces

SDIO v2.0

The BCM4343W WLAN section supports SDIO version 2.0. for both 1-bit (25 Mbps) and 4-bit modes (100

Mbps), as well as high speed 4-bit mode (50 MHz clocks—200 Mbps). It has the ability to map the interrupt signal on a GPIO pin. This out-of-band interrupt signal notifies the host when the WLAN device wants to turn on the SDIO interface. The ability to force control of the gated clocks from within the WLAN chip is also provided.

SDIO mode is enabled using the strapping option pins. See

Table 21 on page 108 for details.

Three functions are supported:

• Function 0 standard SDIO function. The maximum block size is 32 bytes.

• Function 1 backplane function to access the internal System-on-a-Chip (SoC) address space. The maximum block size is 64 bytes.

• Function 2 WLAN function for efficient WLAN packet transfer through DMA. The maximum block size is

512 bytes.

SDIO Pin Descriptions

DATA0

DATA1

DATA2

DATA3

CLK

CMD

Table 4: SDIO Pin Descriptions

SD 4-Bit Mode SD 1-Bit Mode

Data line 0 DATA Data line

Data line 1 or Interrupt IRQ

Data line 2 NC

Interrupt

Not used

Data line 3

Clock

Command line

NC

CLK

CMD

Not used

Clock

Command line

gSPI Mode

DO

IRQ

NC

Data output

Interrupt

Not used

CS Card select

SCLK Clock

DI Data input

Figure 11: Signal Connections to SDIO Host (SD 4-Bit Mode)

CLK

SD Host

CMD

DAT[3:0]

BCM4343W

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BCM4343W Data Sheet

Figure 12: Signal Connections to SDIO Host (SD 1-Bit Mode)

CLK

SD Host

CMD

DATA

IRQ

BCM4343W

SDIO v2.0

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BCM4343W Data Sheet Generic SPI Mode

Generic SPI Mode

In addition to the full SDIO mode, the BCM4343W includes the option of using the simplified generic SPI (gSPI) interface/protocol. Characteristics of the gSPI mode include:

• Up to 50 MHz operation

• Fixed delays for responses and data from the device

• Alignment to host gSPI frames (16 or 32 bits)

• Up to 2 KB frame size per transfer

• Little-endian and big-endian configurations

• A configurable active edge for shifting

• Packet transfer through DMA for WLAN gSPI mode is enabled using the strapping option pins. See

Table 21 on page 108 for details.

Figure 13: Signal Connections to SDIO Host (gSPI Mode)

SD Host

SCLK

DI

DO

IRQ

CS

BCM4343W

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BCM4343W Data Sheet Generic SPI Mode

SPI Protocol

The SPI protocol supports both 16-bit and 32-bit word operation. Byte endianess is supported in both modes.

Figure 14

and Figure 15 on page 37

show the basic write and write/read commands.

Figure 14: gSPI Write Protocol

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BCM4343W Data Sheet

Figure 15: gSPI Read Protocol

Generic SPI Mode

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BCM4343W Data Sheet Generic SPI Mode

Command Structure

The gSPI command structure is 32 bits. The bit positions and definitions are shown in Figure 16 .

Figure 16: gSPI Command Structure

C

A F1 F0

Write

The host puts the first bit of the data onto the bus half a clock-cycle before the first active edge following the CS going low. The following bits are clocked out on the falling edge of the gSPI clock. The device samples the data on the active edge.

Write/Read

The host reads on the rising edge of the clock requiring data from the device to be made available before the first rising-clock edge of the data. The last clock edge of the fixed delay word can be used to represent the first bit of the following data word. This allows data to be ready for the first clock edge without relying on asynchronous delays.

Read

The read command always follows a separate write to set up the WLAN device for a read. This command differs from the write/read command in the following respects: a) chip selects go high between the command/address and the data, and b) the time interval between the command/address is not fixed.

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BCM4343W Data Sheet Generic SPI Mode

Status

The gSPI interface supports status notification to the host after a read/write transaction. This status notification provides information about packet errors, protocol errors, available packets in the RX queue, etc. The status information helps reduce the number of interrupts to the host. The status-reporting feature can be switched off using a register bit, without any timing overhead. The gSPI bus timing for read/write transactions with and

without status notification are as shown in Figure 17 below and

Figure 18 on page 40

. See

Table 5 on page 40

for information on status-field details.

Figure 17: gSPI Signal Timing Without Status

Write

CS

SCLK

MOSI

C31 C30 C1 C0 D31 D30

Command 32 bits

D1

Write Data 16*n bits

D0

Write-Read

CS

SCLK

MOSI

MISO

C31 C30 C0

D31 D30

Read

CS

SCLK

MOSI

MISO

C31 C30 C0

D31 D30

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BROADCOM CONFIDENTIAL

Bit

0

1

2

7

8

3

5

9:19

BCM4343W Data Sheet

Write

Write-Read

Figure 18: gSPI Signal Timing with Status (Response Delay = 0)

CS

SCLK

MOSI

MISO

C31 C1 C0 D31

Command 32 bits

D1 D0

Write Data 16*n bits

S31

Status 32 bits

S0

CS

SCLK

MOSI

MISO

C31 C0

Command 32 bits

D31 D1 D0

Read Data 16*n bits Status 32 bits

Read

CS

SCLK

MOSI

MISO

C31 C0

Command 32 bits

D31 D1 D0

Read Data 16*n bits Status 32 bits

Generic SPI Mode

Name

Data not available

Underflow

Overflow

F2 interrupt

F2 RX ready

Reserved

F2 packet available

F2 packet length

Table 5: gSPI Status Field Details

Description

The requested read data is not available.

FIFO underflow occurred due to current (F2, F3) read command.

FIFO overflow occurred due to current (F1, F2, F3) write command.

F2 channel interrupt.

F2 FIFO is ready to receive data (FIFO empty).

Packet is available/ready in F2 TX FIFO.

Length of packet available in F2 FIFO

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BCM4343W Data Sheet Generic SPI Mode

gSPI Host-Device Handshake

To initiate communication through the gSPI after power-up, the host needs to bring up the WLAN chip by writing to the wake-up WLAN register bit. Writing a 1 to this bit will start up the necessary crystals and PLLs so that the

BCM4343W is ready for data transfer. The device can signal an interrupt to the host indicating that the device is awake and ready. This procedure also needs to be followed for waking up the device in sleep mode. The device can interrupt the host using the WLAN IRQ line whenever it has any information to pass to the host. On getting an interrupt, the host needs to read the interrupt and/or status register to determine the cause of the interrupt and then take necessary actions.

Boot-Up Sequence

After power-up, the gSPI host needs to wait 50 ms for the device to be out of reset. For this, the host needs to poll with a read command to F0 address 0x14. Address 0x14 contains a predefined bit pattern. As soon as the host gets a response back with the correct register content, it implies that the device has powered up and is out of reset. After that, the host needs to set the wake-up WLAN bit (F0 reg 0x00 bit 7). Wake-up WLAN turns the

PLL on; however, the PLL doesn't lock until the host programs the PLL registers to set the crystal frequency.

For the first time after power-up, the host needs to wait for the availability of the low-power clock inside the device. Once it is available, the host needs to write to a PMU register to set the crystal frequency. This will turn on the PLL. After the PLL is locked, the chipActive interrupt is issued to the host. This indicates device awake/

ready status. See Table 6

for information on gSPI registers.

In Table 6

, the following notation is used for register access:

• R: Readable from host and CPU

• W: Writable from host

• U: Writable from CPU

Address Register

x0000 Word length

Endianess

Bit

0

High-speed mode 4

Interrupt polarity 5

Wake-up

1

7

Access Default

R/W/U 0

R/W/U

R/W/U

R/W/U

R/W

Table 6: gSPI Registers

0

1

1

0

Description

0: 16-bit word length

1: 32-bit word length

0: Little endian

1: Big endian

0: Normal mode. Sample on SPICLK rising edge, output on falling edge.

1: High-speed mode. Sample and output on rising edge of SPICLK (default).

0: Interrupt active polarity is low.

1: Interrupt active polarity is high (default).

A write of 1 denotes a wake-up command from host to device. This will be followed by an F2 interrupt from the gSPI device to host, indicating device awake status.

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BCM4343W Data Sheet Generic SPI Mode

Table 6: gSPI Registers (Cont.)

Address Register

x0002 x0003 x0004 x0005 x0006, x0007 x0008 to x000B x000C, x000D

Status enable

Interrupt with status

Bit

0

1

Access Default

R/W

R/W

1

0

Description

0: No status sent to host after a read/write.

1: Status sent to host after a read/write.

0: Do not interrupt if status is sent.

1: Interrupt host even if status is sent.

Reserved

Interrupt register

0

R/W

R

R

R

0

0

0

0

0

0

0

0

Requested data not available. Cleared by writing a 1 to this location.

F2/F3 FIFO underflow from the last read.

1

2

5

Interrupt register 5

6

6

7

Interrupt enable register

Status register

R

R

R

R

F2/F3 FIFO overflow from the last write.

F2 packet available

F3 packet available

F1 overflow from the last write.

F1 Interrupt

F2 Interrupt

7 R 0 F3 Interrupt

15:0 R/W/U 16'hE0E7 Particular interrupt is enabled if a corresponding bit is set.

31:0 R 32'h0000 Same as status bit definitions x000E, x000F x0014 to x0017 x0018 to x001B x001C to x001F

F1 info. register

F2 info. register 0

Test-Read only register

0

1

1

R

R

13:2 R/U

R/U

R

15:2 R/U

31:0 R

Test–R/W register 31:0 R/W/U 32'h000000

00

Response delay registers

7:0 R/W

1

0

12'h40

1

0

14'h800

32'hFEEDB

EAD

0x1D = 4, other registers =

0

F1 enabled

F1 ready for data transfer

F1 maximum packet size

F2 enabled

F2 ready for data transfer

F2 maximum packet size

This register contains a predefined pattern, which the host can read to determine if the gSPI interface is working properly.

This is a dummy register where the host can write some pattern and read it back to determine if the gSPI interface is working properly.

Individual response delays for F0, F1, F2, and F3.

The value of the registers is the number of byte delays that are introduced before data is shifted out of the gSPI interface during host reads.

Figure 19 on page 43 shows the WLAN boot-up sequence from power-up to firmware download, including the

initial device power-on reset (POR) evoked by the WL_REG_ON signal. After initial power-up, the

WL_REG_ON signal can be held low to disable the BCM4343W or pulsed low to induce a subsequent reset.

Note:

The BCM4343W has an internal power-on reset (POR) circuit. The device will be held in reset for a maximum of 3 ms after VDDC and VDDIO have both passed the 0.6V threshold.

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BCM4343W Data Sheet Generic SPI Mode

Figure 19: WLAN Boot-Up Sequence

VBAT

VDDIO

WL_REG_ON

Ramp time from 0V to 4.3V > 40 µs

0.6V

> 2 Sleep Clock cycles

< 1.5 ms

VDDC

(from internal PMU)

Internal POR

< 3 ms 

< 50 ms 

After a fixed delay following internal POR going high,  the device responds to host F0 (address 0x14) reads.

Device requests a reference clock.

15 

1 ms 

SPI Host Interaction:

Host polls F0 (address 0x14) until it reads  a predefined pattern.

Host sets wake‐up‐wlan bit  and waits 15 ms

1

, the  maximum time for  reference clock availability.

After 15 ms

1 the reference clock  is assumed to be up.  Access to 

PLL registers is possible.

After 15 

1 ms, the host  programs the PLL registers to  set the crystal frequency.

WL_IRQ

Chip‐active interrupt is asserted after the PLL locks.

Host downloads  code.

This wait time is programmable in sleep‐clock increments from 1 to 255 (30 us to 15 ms).

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BCM4343W Data Sheet Wireless LAN MAC and PHY

Section 5: Wireless LAN MAC and PHY

MAC Features

The BCM4343W WLAN MAC supports features specified in the IEEE 802.11 base standard, and amended by

IEEE 802.11n. The salient features are listed below:

• Transmission and reception of aggregated MPDUs (A-MPDU).

• Support for power management schemes, including WMM power-save, power-save multipoll (PSMP) and multiphase PSMP operation.

• Support for immediate ACK and Block-ACK policies.

• Interframe space timing support, including RIFS.

• Support for RTS/CTS and CTS-to-self frame sequences for protecting frame exchanges.

• Back-off counters in hardware for supporting multiple priorities as specified in the WMM specification.

• Timing synchronization function (TSF), network allocation vector (NAV) maintenance, and target beacon transmission time (TBTT) generation in hardware.

• Hardware off-load for AES-CCMP, legacy WPA TKIP, legacy WEP ciphers, WAPI, and support for key management.

• Support for coexistence with Bluetooth and other external radios.

• Programmable independent basic service set (IBSS) or infrastructure basic service set functionality

• Statistics counters for MIB support.

MAC Description

The BCM4343W WLAN MAC is designed to support high throughput operation with low-power consumption. It does so without compromising on Bluetooth coexistence policies, thereby enabling optimal performance over both networks. In addition, several power-saving modes that have been implemented allow the MAC to consume very little power while maintaining network-wide timing synchronization. The architecture diagram of

the MAC is shown in Figure 20 on page 45 .

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BCM4343W Data Sheet

Figure 20: WLAN MAC Architecture

Embedded CPU Interface

Host Registers, DMA Engines

PMQ

TX‐FIFO

32 KB

RX‐FIFO

10 KB

PSM

IFS

Backoff, BTCX

TSF

NAV

EXT‐ IHR

WEP

WEP, TKIP, AES

IHR 

BUS

TXE

TX A‐MPDU

MAC ‐ PHY Interface

RXE

RX A‐MPDU

SHM 

BUS

Shared Memory

6 KB

MAC Features

PSM

UCODE

Memory

The following sections provide an overview of the important modules in the MAC.

PSM

The programmable state machine (PSM) is a microcoded engine that provides most of the low-level control to the hardware to implement the IEEE 802.11 specification. It is a microcontroller that is highly optimized for flowcontrol operations, which are predominant in implementations of communication protocols. The instruction set and fundamental operations are simple and general, which allows algorithms to be optimized until very late in the design process. It also allows for changes to the algorithms to track evolving IEEE 802.11 specifications.

The PSM fetches instructions from the microcode memory. It uses the shared memory to obtain operands for instructions, as a data store, and to exchange data between both the host and the MAC data pipeline (via the

SHM bus). The PSM also uses a scratch-pad memory (similar to a register bank) to store frequently accessed and temporary variables.

The PSM exercises fine-grained control over the hardware engines by programming internal hardware registers

(IHR). These IHRs are collocated with the hardware functions they control and are accessed by the PSM via the IHR bus.

The PSM fetches instructions from the microcode memory using an address determined by the program counter, an instruction literal, or a program stack. For ALU operations, the operands are obtained from shared memory, scratch-pad memory, IHRs, or instruction literals, and the results are written into the shared memory, scratch-pad memory, or IHRs.

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BCM4343W Data Sheet MAC Features

There are two basic branch instructions: conditional branches and ALU-based branches. To better support the many decision points in the IEEE 802.11 algorithms, branches can depend on either readily available signals from the hardware modules (branch condition signals are available to the PSM without polling the IHRs) or on the results of ALU operations.

WEP

The wired equivalent privacy (WEP) engine encapsulates all the hardware accelerators to perform the encryption and decryption, as well as the MIC computation and verification. The accelerators implement the following cipher algorithms: legacy WEP, WPA TKIP, and WPA2 AES-CCMP.

Based on the frame type and association information, the PSM determines the appropriate cipher algorithm to be used. It supplies the keys to the hardware engines from an on-chip key table. The WEP interfaces with the transmit engine (TXE) to encrypt and compute the MIC on transmit frames and the receive engine (RXE) to decrypt and verify the MIC on receive frames. WAPI is also supported.

TXE

The transmit engine (TXE) constitutes the transmit data path of the MAC. It coordinates the DMA engines to store the transmit frames in the TXFIFO. It interfaces with WEP module to encrypt frames and transfers the frames across the MAC-PHY interface at the appropriate time determined by the channel access mechanisms.

The data received from the DMA engines are stored in transmit FIFOs. The MAC supports multiple logical queues to support traffic streams that have different QoS priority requirements. The PSM uses the channel access information from the IFS module to schedule a queue from which the next frame is transmitted. Once the frame is scheduled, the TXE hardware transmits the frame based on a precise timing trigger received from the IFS module.

The TXE module also contains the hardware that allows the rapid assembly of MPDUs into an A-MPDU for transmission. The hardware module aggregates the encrypted MPDUs by adding appropriate headers and pad delimiters as needed.

RXE

The receive engine (RXE) constitutes the receive data path of the MAC. It interfaces with the DMA engine to drain the received frames from the RX FIFO. It transfers bytes across the MAC-PHY interface and interfaces with the WEP module to decrypt frames. The decrypted data is stored in the RX FIFO.

The RXE module contains programmable filters that are programmed by the PSM to accept or filter frames based on several criteria such as receiver address, BSSID, and certain frame types.

The RXE module also contains the hardware required to detect A-MPDUs, parse the headers of the containers, and disaggregate them into component MPDUS.

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BCM4343W Data Sheet MAC Features

IFS

The IFS module contains the timers required to determine interframe space timing including RIFS timing. It also contains multiple back-off engines required to support prioritized access to the medium as specified by WMM.

The interframe spacing timers are triggered by the cessation of channel activity on the medium, as indicated by the PHY. These timers provide precise timing to the TXE to begin frame transmission. The TXE uses this information to send response frames or perform transmit frame-bursting (RIFS or SIFS separated, as within a

TXOP).

The back-off engines (for each access category) monitor channel activity, in each slot duration, to determine whether to continue or pause the back-off counters. When the back-off counters reach 0, the TXE gets notified so that it may commence frame transmission. In the event of multiple back-off counters decrementing to 0 at the same time, the hardware resolves the conflict based on policies provided by the PSM.

The IFS module also incorporates hardware that allows the MAC to enter a low-power state when operating under the IEEE power-saving mode. In this mode, the MAC is in a suspended state with its clock turned off. A sleep timer, whose count value is initialized by the PSM, runs on a slow clock and determines the duration over which the MAC remains in this suspended state. Once the timer expires, the MAC is restored to its functional state. The PSM updates the TSF timer based on the sleep duration, ensuring that the TSF is synchronized to the network.

The IFS module also contains the PTA hardware that assists the PSM in Bluetooth coexistence functions.

TSF

The timing synchronization function (TSF) module maintains the TSF timer of the MAC. It also maintains the target beacon transmission time (TBTT). The TSF timer hardware, under the control of the PSM, is capable of adopting timestamps received from beacon and probe response frames in order to maintain synchronization with the network.

The TSF module also generates trigger signals for events that are specified as offsets from the TSF timer, such as uplink and downlink transmission times used in PSMP.

NAV

The network allocation vector (NAV) timer module is responsible for maintaining the NAV information conveyed through the duration field of MAC frames. This ensures that the MAC complies with the protection mechanisms specified in the standard.

The hardware, under the control of the PSM, maintains the NAV timer and updates the timer appropriately based on received frames. This timing information is provided to the IFS module, which uses it as a virtual carriersense indication.

MAC-PHY Interface

The MAC-PHY interface consists of a data path interface to exchange RX/TX data from/to the PHY. In addition, there is a programming interface, which can be controlled either by the host or the PSM to configure and control the PHY.

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BCM4343W Data Sheet PHY Description

PHY Description

The BCM4343W WLAN digital PHY is designed to comply with IEEE 802.11b/g/n single stream to provide wireless LAN connectivity supporting data rates from 1 Mbps to 96 Mbps for low-power, high-performance handheld applications.

The PHY has been designed to meet specification requirements in the presence of interference, radio nonlinearity, and impairments. It incorporates efficient implementations of the filters, FFT, and Viterbi decoder algorithms. Efficient algorithms have been designed to achieve maximum throughput and reliability, including algorithms for carrier sense/rejection, frequency/phase/timing acquisition and tracking, and channel estimation and tracking. The PHY receiver also contains a robust IEEE 802.11b demodulator. The PHY carrier sense has been tuned to provide high throughput for IEEE 802.11g/IEEE 802.11b hybrid networks with Bluetooth coexistence.

PHY Features

• Supports the IEEE 802.11b/g/n single-stream standards.

• Explicit IEEE 802.11n transmit beamforming.

• Supports optional Greenfield mode in TX and RX.

• Tx and Rx LDPC for improved range and power efficiency.

• Supports IEEE 802.11h/d for worldwide operation.

• Algorithms achieving low power, enhanced sensitivity, range, and reliability.

• Algorithms to maximize throughput performance in the presence of Bluetooth signals.

• Automatic gain control scheme for blocking and nonblocking application scenarios for cellular applications.

• Closed-loop transmit power control.

• Designed to meet FCC and other regulatory requirements.

• Support for 2.4 GHz Broadcom TurboQAM data rates and 20 MHz channel bandwidth.

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BCM4343W Data Sheet PHY Description

Figure 21: WLAN PHY Block Diagram

Filters  and 

Radio 

Comp

AFE  and 

Radio

Radio 

Control 

Block

Frequency  and Timing 

Synch

Carrier Sense, 

AGC, and Rx 

FSM

CCK/DSSS 

Demodulate

OFDM 

Demodulate

Buffers

FFT/IFFT

Viterbi 

Decoder

Descramble  and 

Deframe

MAC 

Interface

Filters and 

Radio Comp

Tx FSM

PA Comp

Modulation  and Coding

Modulate/

Spread

Frame and 

Scramble

COEX

The PHY is capable of fully calibrating the RF front-end to extract the highest performance. On power-up, the

PHY performs a full calibration suite to correct for IQ mismatch and local oscillator leakage. The PHY also performs periodic calibration to compensate for any temperature related drift, thus maintaining highperformance over time. A closed-loop transmit control algorithm maintains the output power at its required level and can control TX power on a per-packet basis.

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BCM4343W Data Sheet WLAN Radio Subsystem

Section 6: WLAN Radio Subsystem

The BCM4343W includes an integrated WLAN RF transceiver that has been optimized for use in 2.4 GHz

Wireless LAN systems. It is designed to provide low power, low cost, and robust communications for applications operating in the globally available 2.4 GHz unlicensed ISM band. The transmit and receive sections include all on-chip filtering, mixing, and gain control functions. Improvements to the radio design include shared

TX/RX baseband filters and high immunity to supply noise.

Figure 22 shows the radio functional block diagram.

Figure 22: Radio Functional Block Diagram

4 ~ 6 nH 

Recommend 

Q = 40

10 pF

WLRF_2G_RF

WLRF_2G_eLG

WL TXLPF

WL PA WL PGA

WL TX G‐Mixer WL TXLPF

WL DAC

WL DAC

WLAN BB

Voltage 

Regulators

WL ADC

WL RXLPF

SLNA

WL G‐LNA12

Gm

BT LNA GM

WL RX G‐Mixer

WL RXLPF

WL ATX

WL ARX

WL GTX

WL GRX

WL LOGEN WL PLL

WL ADC

BT RX

BT TX

BT LOGEN BT PLL

CLB

Shared XO

LPO/Ext LPO/RCAL

BT RXLPF

BT LNA Load

BT PA

BT RX Mixer

BT RXLPF

BT ADC

BT ADC

BT BB BT FM

BT DAC

BT DAC

BT TX Mixer BT TXLPF

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BCM4343W Data Sheet Receive Path

Receive Path

The BCM4343W has a wide dynamic range, direct conversion receiver. It employs high-order on-chip channel filtering to ensure reliable operation in the noisy 2.4 GHz ISM band.

Transmit Path

Baseband data is modulated and upconverted to the 2.4 GHz ISM band. A linear on-chip power amplifier is included, which is capable of delivering high output powers while meeting IEEE 802.11b/g/n specifications without the need for an external PA. This PA is supplied by an internal LDO that is directly supplied by VBAT, thereby eliminating the need for a separate PALDO. Closed-loop output power control is integrated.

Calibration

The BCM4343W features dynamic on-chip calibration, eliminating process variation across components. This enables the BCM4343W to be used in high-volume applications because calibration routines are not required during manufacturing testing. These calibration routines are performed periodically during normal radio operation. Automatic calibration examples include baseband filter calibration for optimum transmit and receive performance and LOFT calibration for leakage reduction. In addition, I/Q calibration, R calibration, and VCO calibration are performed on-chip.

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BCM4343W Data Sheet Bluetooth + FM Subsystem Overview

Section 7: Bluetooth + FM Subsystem

Overview

The Broadcom BCM4343W is a Bluetooth 4.1-compliant, baseband processor and 2.4 GHz transceiver with an integrated FM/RDS/RBDS receiver. It features the highest level of integration and eliminates all critical external components, thus minimizing the footprint, power consumption, and system cost of a Bluetooth plus FM radio solution.

The BCM4343W is the optimal solution for any Bluetooth voice and/or data application that also requires an FM radio receiver. The Bluetooth subsystem presents a standard Host Controller Interface (HCI) via a high speed

UART and PCM interface for audio. The FM subsystem supports the HCI control interface as well as I

2

S, PCM, and stereo analog interfaces. The BCM4343W incorporates all Bluetooth 4.1 features including secure simple pairing, sniff subrating, and encryption pause and resume.

The BCM4343W Bluetooth radio transceiver provides enhanced radio performance to meet the most stringent mobile phone temperature applications and the tightest integration into mobile handsets and portable devices.

It is fully compatible with any of the standard TCXO frequencies and provides full radio compatibility to operate simultaneously with GPS, WLAN, NFC, and cellular radios.

The Bluetooth transmitter also features a Class 1 power amplifier with Class 2 capability.

Features

Major Bluetooth features of the BCM4343W include:

• Supports key features of upcoming Bluetooth standards

• Fully supports Bluetooth Core Specification version 4.1 plus enhanced data rate (EDR) features:

– Adaptive Frequency Hopping (AFH)

– Quality of Service (QoS)

– Extended Synchronous Connections (eSCO)—voice connections

– Fast connect (interlaced page and inquiry scans)

– Secure Simple Pairing (SSP)

– Sniff Subrating (SSR)

– Encryption Pause Resume (EPR)

– Extended Inquiry Response (EIR)

– Link Supervision Timeout (LST)

• UART baud rates up to 4 Mbps

• Supports all Bluetooth 4.1 packet types

• Supports maximum Bluetooth data rates over HCI UART

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BCM4343W Data Sheet Features

• Multipoint operation with up to seven active slaves

– Maximum of seven simultaneous active ACL links

– Maximum of three simultaneous active SCO and eSCO connections with scatternet support

• Trigger Beacon fast connect (TBFC)

• Narrowband and wideband packet loss concealment

• Scatternet operation with up to four active piconets with background scan and support for scatter mode

• High-speed HCI UART transport support with low-power out-of-band BT_DEV_WAKE and

BT_HOST_WAKE signaling (see “Host Controller Power Management” on page 58

)

• Channel-quality driven data rate and packet type selection

• Standard Bluetooth test modes

• Extended radio and production test mode features

• Full support for power savings modes

– Bluetooth clock request

– Bluetooth standard sniff

– Deep-sleep modes and software regulator shutdown

• TCXO input and auto-detection of all standard handset clock frequencies. Also supports a low-power crystal, which can be used during power save mode for better timing accuracy.

Major FM Radio features include:

• 65 MHz to 108 MHz FM bands supported (US, Europe, and Japan)

• FM subsystem control using the Bluetooth HCI interface

• FM subsystem operates from reference clock inputs.

• Improved audio interface capabilities with full-featured bidirectional PCM, I

2

S, and stereo analog output.

• I

2

S can be master or slave.

FM Receiver-Specific Features Include:

• Excellent FM radio performance with 1 µV sensitivity for 26 dB (S+N)/N

• Signal-dependent stereo/mono blending

• Signal dependent soft mute

• Auto search and tuning modes

• Audio silence detection

• RSSI and IF frequency status indicators

• RDS and RBDS demodulator and decoder with filter and buffering functions

• Automatic frequency jump

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BCM4343W Data Sheet Bluetooth Radio

Bluetooth Radio

The BCM4343W has an integrated radio transceiver that has been optimized for use in 2.4 GHz Bluetooth wireless systems. It has been designed to provide low-power, low-cost, robust communications for applications operating in the globally available 2.4 GHz unlicensed ISM band. It is fully compliant with the Bluetooth Radio

Specification and EDR specification and meets or exceeds the requirements to provide the highest communication link quality of service.

Transmit

The BCM4343W features a fully integrated zero-IF transmitter. The baseband transmit data is GFSK-modulated in the modem block and upconverted to the 2.4 GHz ISM band in the transmitter path. The transmitter path has signal filters, an I/Q upconverter, an output power amplifier, and RF filters. The transmitter path also incorporates

/4–DQPSK for 2 Mbps and 8–DPSK for 3 Mbps to support EDR. The transmitter section is compatible with the

Bluetooth Low Energy specification. The transmitter PA bias can also be adjusted to provide Bluetooth Class 1 or Class 2 operation.

Digital Modulator

The digital modulator performs the data modulation and filtering required for the GFSK,

/4–DQPSK, and 8–

DPSK signal. The fully digital modulator minimizes any frequency drift or anomalies in the modulation characteristics of the transmitted signal and is much more stable than direct VCO modulation schemes.

Digital Demodulator and Bit Synchronizer

The digital demodulator and bit synchronizer take the low-IF received signal and perform an optimal frequency tracking and bit-synchronization algorithm.

Power Amplifier

The fully integrated PA supports Class 1 or Class 2 output using a highly linearized, temperature-compensated design. This provides greater flexibility in front-end matching and filtering. Due to the linear nature of the PA combined with some integrated filtering, external filtering is required to meet the Bluetooth and regulatory harmonic and spurious requirements. For integrated mobile handset applications in which Bluetooth is integrated next to the cellular radio, external filtering can be applied to achieve near-thermal noise levels for spurious and radiated noise emissions. The transmitter features a sophisticated on-chip transmit signal strength indicator (TSSI) block to keep the absolute output power variation within a tight range across process, voltage, and temperature.

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BCM4343W Data Sheet Bluetooth Radio

Receiver

The receiver path uses a low-IF scheme to downconvert the received signal for demodulation in the digital demodulator and bit synchronizer. The receiver path provides a high degree of linearity, an extended dynamic range, and high-order on-chip channel filtering to ensure reliable operation in the noisy 2.4 GHz ISM band. The front-end topology with built-in out-of-band attenuation enables the BCM4343W to be used in most applications with minimal off-chip filtering. For integrated handset operation, in which the Bluetooth function is integrated close to the cellular transmitter, external filtering is required to eliminate the desensitization of the receiver by the cellular transmit signal.

Digital Demodulator and Bit Synchronizer

The digital demodulator and bit synchronizer take the low-IF received signal and perform an optimal frequency tracking and bit synchronization algorithm.

Receiver Signal Strength Indicator

The radio portion of the BCM4343W provides a Receiver Signal Strength Indicator (RSSI) signal to the baseband so that the controller can take part in a Bluetooth power-controlled link by providing a metric of its own receiver signal strength to determine whether the transmitter should increase or decrease its output power.

Local Oscillator Generation

Local Oscillator (LO) generation provides fast frequency hopping (1600 hops/second) across the 79 maximum available channels. The LO generation subblock employs an architecture for high immunity to LO pulling during

PA operation. The BCM4343W uses an internal RF and IF loop filter.

Calibration

The BCM4343W radio transceiver features an automated calibration scheme that is self contained in the radio.

No user interaction is required during normal operation or during manufacturing to optimize performance.

Calibration optimizes the performance of all the major blocks within the radio to within 2% of optimal conditions, including filter gain and phase characteristics, matching between key components, and key gain blocks. This takes into account process variation and temperature variation. Calibration occurs transparently during normal operation during the settling time of the hops and calibrates for temperature variations as the device cools and heats during normal operation in its environment.

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BCM4343W Data Sheet Bluetooth Baseband Core

Section 8: Bluetooth Baseband Core

The Bluetooth Baseband Core (BBC) implements all of the time-critical functions required for high-performance

Bluetooth operation. The BBC manages the buffering, segmentation, and routing of data for all connections. It also buffers data that passes through it, handles data flow control, schedules SCO/ACL TX/RX transactions, monitors Bluetooth slot usage, optimally segments and packages data into baseband packets, manages connection status indicators, and composes and decodes HCI packets. In addition to these functions, it independently handles HCI event types and HCI command types.

The following transmit and receive functions are also implemented in the BBC hardware to increase the reliability and security of data before sending and receiving it over the air:

• Symbol timing recovery, data deframing, forward error correction (FEC), header error control (HEC), cyclic redundancy check (CRC), data decryption, and data dewhitening in the receiver.

• Data framing, FEC generation, HEC generation, CRC generation, key generation, data encryption, and data whitening in the transmitter.

Bluetooth 4.1 Features

The BBC supports all Bluetooth 4.1 features, with the following benefits:

• Dual-mode classic Bluetooth and classic Low Energy (BT and BLE) operation.

• Low energy physical layer

• Low energy link layer

• Enhancements to HCI for low energy

• Low energy direct test mode

• 128 AES-CCM secure connection for both BT and BLE

Note:

The BCM4343W is compatible with the Bluetooth Low Energy operating mode, which provides a dramatic reduction in the power consumption of the Bluetooth radio and baseband. The primary application for this mode is to provide support for low data rate devices, such as sensors and remote controls.

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BCM4343W Data Sheet Link Control Layer

Link Control Layer

The link control layer is part of the Bluetooth link control functions that are implemented in dedicated logic in the link control unit (LCU). This layer contains the command controller that takes commands from the software, and other controllers that are activated or configured by the command controller, to perform the link control tasks.

Each task performs a different state in the Bluetooth link controller.

• Major states:

– Standby

– Connection

• Substates:

– Page

– Page Scan

– Inquiry

– Inquiry Scan

– Sniff

– BLE Adv

– BLE Scan/Initiation

Test Mode Support

The BCM4343W fully supports Bluetooth Test mode as described in Part I:1 of the Specification of the Bluetooth

System Version 3.0

. This includes the transmitter tests, normal and delayed loopback tests, and reduced hopping sequence.

In addition to the standard Bluetooth Test Mode, the BCM4343W also supports enhanced testing features to simplify RF debugging and qualification as well as type-approval testing. These features include:

• Fixed frequency carrier-wave (unmodulated) transmission

– Simplifies some type-approval measurements (Japan)

– Aids in transmitter performance analysis

• Fixed frequency constant receiver mode

– Receiver output directed to an I/O pin

– Allows for direct BER measurements using standard RF test equipment

– Facilitates spurious emissions testing for receive mode

• Fixed frequency constant transmission

– Eight-bit fixed pattern or PRBS-9

– Enables modulated signal measurements with standard RF test equipment

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BCM4343W Data Sheet Bluetooth Power Management Unit

Bluetooth Power Management Unit

The Bluetooth Power Management Unit (PMU) provides power management features that can be invoked by either software through power management registers or packet handling in the baseband core. The power management functions provided by the BCM4343W are:

RF Power Management

Host Controller Power Management

BBC Power Management

FM Power Management

RF Power Management

The BBC generates power-down control signals for the transmit path, receive path, PLL, and power amplifier to the 2.4 GHz transceiver. The transceiver then processes the power-down functions accordingly.

Host Controller Power Management

When running in UART mode, the BCM4343W can be configured so that dedicated signals are used for power management handshaking between the BCM4343W and the host. The basic power saving functions supported by those handshaking signals include the standard Bluetooth defined power savings modes and standby modes of operation.

Table 7 describes the power-control handshake signals used with the UART interface.

Table 7: Power Control Pin Description

Signal Type Description

BT_DEV_WAKE I

BT_HOST_WAKE O

Bluetooth device wake-up signal: Signal from the host to the BCM4343W indicating that the host requires attention.

• Asserted: The Bluetooth device must wake up or remain awake.

• Deasserted: The Bluetooth device may sleep when sleep criteria are met.

The polarity of this signal is software configurable and can be asserted high or low.

Host wake-up signal. Signal from the BCM4343W to the host indicating that the

BCM4343W requires attention.

• Asserted: Host device must wake up or remain awake.

• Deasserted: Host device may sleep when sleep criteria are met.

The polarity of this signal is software configurable and can be asserted high or low.

CLK_REQ O The BCM4343W asserts CLK_REQ when Bluetooth or WLAN directs the host to turn on the reference clock. The CLK_REQ polarity is active-high. Add an external

100 kΩ pull-down resistor to ensure the signal is deasserted when the BCM4343W powers up or resets when VDDIO is present.

Note:

Pad function Control Register is set to 0 for these pins.

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BCM4343W Data Sheet

Figure 23: Startup Signaling Sequence

Bluetooth Power Management Unit

LPO

VDDIO

HostResetX

Host IOs unconfigured

Host IOs configured

T1

BT_GPIO_0 

(BT_DEV_WAKE)

T2

BTH IOs unconfigured BTH IOs configured

BT_REG_ON

BT_GPIO_1 

(BT_HOST_WAKE)

BT_UART_CTS_N

T3

BT_UART_RTS_N

T4

Host side drives  this line low

BTH device drives this  line low indicating  transport is ready

CLK_REQ_OUT

T5

Driven

Pulled

Notes :  

T1 is the time for host to settle it’s IOs after a reset.

T2 is the time for host to drive BT_REG_ON high after the Host IOs are configured. 

T3 is the time for BTH (Bluetooth) device to settle its IOs after a reset and reference clock settling time has  elapsed.

T4 is the time for BTH device to drive BT_UART_RTS_N low after the host drives  BT_UART_CTS_N low. This  assumes the BTH device has already completed initialization.

T5 is the time for BTH device to drive CLK_REQ_OUT high after BT_REG_ON goes high. Note this pin is used for  designs that use an external reference clock source from the Host. This pin is irrelevant for Crystal reference  clock based designs where the BTH device generates it’s own reference clock from an external crystal connected  to it’s oscillator circuit.

Timing diagram assumes VBAT is present.

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BCM4343W Data Sheet Bluetooth Power Management Unit

BBC Power Management

The following are low-power operations for the BBC:

• Physical layer packet-handling turns the RF on and off dynamically within transmit/receive packets.

• Bluetooth-specified low-power connection modes: sniff and hold. While in these modes, the BCM4343W runs on the low-power oscillator and wakes up after a predefined time period.

• A low-power shutdown feature allows the device to be turned off while the host and any other devices in the system remain operational. When the BCM4343W is not needed in the system, the RF and core supplies are shut down while the I/O remains powered. This allows the BCM4343W to effectively be off while keeping the I/O pins powered, so they do not draw extra current from any other I/O-connected devices.

During the low-power shut-down state, provided VDDIO remains applied to the BCM4343W, all outputs are tristated, and most input signals are disabled. Input voltages must remain within the limits defined for normal operation. This is done to prevent current paths or create loading on digital signals in the system and enables the BCM4343W to be fully integrated in an embedded device to take full advantage of the lowest powersaving modes.

Two BCM4343W input signals are designed to be high-impedance inputs that do not load the driving signal even if the chip does not have VDDIO power supplied to it: the frequency reference input (WRF_TCXO_IN) and the 32.768 kHz input (LPO). When the BCM4343W is powered on from this state, it is the same as a normal power-up, and the device does not contain any information about its state from the time before it was powered down.

FM Power Management

The BCM4343W FM subsystem can operate independently of, or in tandem with, the Bluetooth RF and BBC subsystems. The FM subsystem power management scheme operates in conjunction with the Bluetooth RF and

BBC subsystems. The FM block does not have a low power state, it is either on or off.

Wideband Speech

The BCM4343W provides support for wideband speech (WBS) technology. The BCM4343W can perform subband-codec (SBC), as well as mSBC, encoding and decoding of linear 16 bits at 16 kHz (256 kbps rate) transferred over the PCM bus.

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BCM4343W Data Sheet Bluetooth Power Management Unit

Packet Loss Concealment

Packet Loss Concealment (PLC) improves the apparent audio quality for systems with marginal link performance. Bluetooth messages are sent in packets. When a packet is lost, it creates a gap in the received audio bit-stream. Packet loss can be mitigated in several ways:

• Fill in zeros.

• Ramp down the output audio signal toward zero (this is the method used in current Bluetooth headsets).

• Repeat the last frame (or packet) of the received bit-stream and decode it as usual (frame repeat).

These techniques cause distortion and popping in the audio stream. The BCM4343W uses a proprietary waveform extension algorithm to provide dramatic improvement in the audio quality.

Figure 24 and Figure 25

show audio waveforms with and without Packet Loss Concealment. Broadcom PLC/BEC algorithms also support wideband speech.

Figure 24: CVSD Decoder Output Waveform Without PLC

Packet losses causes ramp-down

Figure 25: CVSD Decoder Output Waveform After Applying PLC

Codec Encoding

The BCM4343W can support SBC and mSBC encoding and decoding for wideband speech.

Multiple Simultaneous A2DP Audio Streams

The BCM4343W has the ability to take a single audio stream and output it to multiple Bluetooth devices simultaneously. This allows a user to share his or her music (or any audio stream) with a friend.

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BCM4343W Data Sheet Adaptive Frequency Hopping

FM Over Bluetooth

FM Over Bluetooth enables the BCM4343W to stream data from FM over Bluetooth without requiring the host to be awake. This can significantly extend battery life for usage cases where someone is listening to FM radio on a Bluetooth headset.

Adaptive Frequency Hopping

The BCM4343W gathers link quality statistics on a channel by channel basis to facilitate channel assessment and channel map selection. The link quality is determined using both RF and baseband signal processing to provide a more accurate frequency-hop map.

Advanced Bluetooth/WLAN Coexistence

The BCM4343W includes advanced coexistence technologies that are only possible with a Bluetooth/WLAN integrated die solution. These coexistence technologies are targeted at small form-factor platforms, such as cell phones and media players, including applications such as VoWLAN + SCO and Video-over-WLAN + High

Fidelity BT Stereo.

Support is provided for platforms that share a single antenna between Bluetooth and WLAN. Dual-antenna applications are also supported. The BCM4343W radio architecture allows for lossless simultaneous Bluetooth and WLAN reception for shared antenna applications. This is possible only via an integrated solution (shared

LNA and joint AGC algorithm). It has superior performance versus implementations that need to arbitrate between Bluetooth and WLAN reception.

The BCM4343W integrated solution enables MAC-layer signaling (firmware) and a greater degree of sharing via an enhanced coexistence interface. Information is exchanged between the Bluetooth and WLAN cores without host processor involvement.

The BCM4343W also supports Transmit Power Control (TPC) on the STA together with standard Bluetooth TPC to limit mutual interference and receiver desensitization. Preemption mechanisms are utilized to prevent AP transmissions from colliding with Bluetooth frames. Improved channel classification techniques have been implemented in Bluetooth for faster and more accurate detection and elimination of interferers (including non-

WLAN 2.4 GHz interference).

The Bluetooth AFH classification is also enhanced by the WLAN core’s channel information.

Fast Connection (Interlaced Page and Inquiry Scans)

The BCM4343W supports page scan and inquiry scan modes that significantly reduce the average inquiry response and connection times. These scanning modes are compatible with the Bluetooth version 2.1 page and inquiry procedures.

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BCM4343W Data Sheet Microprocessor and Memory Unit for Bluetooth

Section 9: Microprocessor and Memory

Unit for Bluetooth

The Bluetooth microprocessor core is based on the ARM Cortex-M3 32-bit RISC processor with embedded ICE-

RT debug and JTAG interface units. It runs software from the link control (LC) layer up to the host controller interface (HCI).

The ARM core is paired with a memory unit that contains 576 KB of ROM for program storage and boot ROM, and 160 KB of RAM for data scratch-pad and patch RAM code. The internal ROM allows for flexibility during power-on reset (POR) to enable the same device to be used in various configurations. At power-up, the lowerlayer protocol stack is executed from the internal ROM memory.

External patches may be applied to the ROM-based firmware to provide flexibility for bug fixes or feature additions. These patches may be downloaded from the host to the BCM4343W through the UART transports.

RAM, ROM, and Patch Memory

The BCM4343W Bluetooth core has 160 KB of internal RAM which is mapped between general purpose scratch-pad memory and patch memory, and 576 KB of ROM used for the lower-layer protocol stack, test mode software, and boot ROM. The patch memory is used for bug fixes and feature additions to ROM memory code.

Reset

The BCM4343W has an integrated power-on reset circuit that resets all circuits to a known power-on state. The

BT POR circuit is out of reset after BT_REG_ON goes high. If BT_REG_ON is low, then the POR circuit is held in reset.

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BCM4343W Data Sheet Bluetooth Peripheral Transport Unit

Section 10: Bluetooth Peripheral Transport

Unit

PCM Interface

The BCM4343W supports two independent PCM interfaces that share pins with the I

2

S interfaces. The PCM interface on the BCM4343W can connect to linear PCM codec devices in master or slave mode. In master mode, the BCM4343W generates the PCM_CLK and PCM_SYNC signals, and in slave mode, these signals are provided by another master on the PCM interface and are inputs to the BCM4343W. The configuration of the

PCM interface may be adjusted by the host through the use of vendor-specific HCI commands.

Slot Mapping

The BCM4343W supports up to three simultaneous full-duplex SCO or eSCO channels through the PCM interface. These three channels are time-multiplexed onto the single PCM interface by using a time-slotting scheme where the 8 kHz or 16 kHz audio sample interval is divided into as many as 16 slots. The number of slots is dependent on the selected interface rate of 128 kHz, 512 kHz, or 1024 kHz. The corresponding number of slots for these interface rates is 1, 2, 4, 8, and 16, respectively. Transmit and receive PCM data from an SCO channel is always mapped to the same slot. The PCM data output driver tristates its output on unused slots to allow other devices to share the same PCM interface signals. The data output driver tristates its output after the falling edge of the PCM clock during the last bit of the slot.

Frame Synchronization

The BCM4343W supports both short- and long-frame synchronization in both master and slave modes. In shortframe synchronization mode, the frame synchronization signal is an active-high pulse at the audio frame rate that is a single-bit period in width and is synchronized to the rising edge of the bit clock. The PCM slave looks for a high on the falling edge of the bit clock and expects the first bit of the first slot to start at the next rising edge of the clock. In long-frame synchronization mode, the frame synchronization signal is again an active-high pulse at the audio frame rate; however, the duration is three bit periods and the pulse starts coincident with the first bit of the first slot.

Data Formatting

The BCM4343W may be configured to generate and accept several different data formats. For conventional narrowband speech mode, the BCM4343W uses 13 of the 16 bits in each PCM frame. The location and order of these 13 bits can be configured to support various data formats on the PCM interface. The remaining three bits are ignored on the input and may be filled with 0’s, 1’s, a sign bit, or a programmed value on the output. The default format is 13-bit 2’s complement data, left justified, and clocked MSB first.

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BCM4343W Data Sheet PCM Interface

Wideband Speech Support

When the host encodes Wideband Speech (WBS) packets in transparent mode, the encoded packets are transferred over the PCM bus for an eSCO voice connection. In this mode, the PCM bus is typically configured in master mode for a 4 kHz sync rate with 16-bit samples, resulting in a 64 kbps bit rate. The BCM4343W also supports slave transparent mode using a proprietary rate-matching scheme. In SBC-code mode, linear 16-bit data at 16 kHz (256 kbps rate) is transferred over the PCM bus.

Multiplexed Bluetooth and FM over PCM

In this mode of operation, the BCM4343W multiplexes both FM and Bluetooth audio PCM channels over the same interface, reducing the number of required I/Os. This mode of operation is initiated through an HCI command from the host. The data stream format contains three channels: a Bluetooth channel followed by two

FM channels (audio left and right). In this mode of operation, the bus data rate only supports 48 kHz operation per channel with 16 bits sent for each channel. This is done to allow the low data rate Bluetooth data to coexist in the same interface as the higher speed I

2

S data. To accomplish this, the Bluetooth data is repeated six times for 8 kHz data and three times for 16 kHz data. An initial sync pulse on the PCM_SYNC line is used to indicate the beginning of the frame.

To support multiple Bluetooth audio streams within the Bluetooth channel, both 16 kHz and 8 kHz streams can be multiplexed. This mode of operation is only supported when the Bluetooth host is the master.

Figure 26

shows the operation of the multiplexed transport with three simultaneous SCO connections. To accommodate additional SCO channels, the transport clock speed is increased. To change between modes of operation, the transport must be halted and restarted in the new configuration.

Figure 26: Functional Multiplex Data Diagram

BT SCO 1 RX BT SCO 2 RX

1 Frame

BT SCO 3 RX

PCM_OUT

BT SCO 1 TX BT SCO 2 TX

PCM_IN

PCM_SYNC

PCM_CLK

16 bits per SCO frame 

Each SCO channel duplicates the data 6 times.  

Each WBS frame duplicates the data 3 times per frame.

CLK

BT SCO 3 TX

FM right

FM right

FM left

FM left

16 bits per frame  16 bits per frame 

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BCM4343W Data Sheet

PCM Interface Timing

Short Frame Sync, Master Mode

Figure 27: PCM Timing Diagram (Short Frame Sync, Master Mode)

1

2 3

PCM_BCLK

4

PCM_SYNC

PCM_OUT

5

8

6

High Impedance

7

PCM_IN

PCM Interface

Table 8: PCM Interface Timing Specifications (Short Frame Sync, Master Mode)

Ref No.

Characteristics

7

8

5

6

3

4

1

2

PCM bit clock frequency

PCM bit clock low

PCM bit clock high

PCM_SYNC delay

PCM_OUT delay

PCM_IN setup

PCM_IN hold

Delay from rising edge of PCM_BCLK during last bit period to PCM_OUT becoming high impedance

Minimum Typical

8

0

0

8

41

41

0

Maximum Unit

12

25

25

25 ns ns ns ns

MHz ns ns ns

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BCM4343W Data Sheet

Short Frame Sync, Slave Mode

Figure 28: PCM Timing Diagram (Short Frame Sync, Slave Mode)

1

2

3

PCM_BCLK

4

5

PCM_SYNC

9

PCM_OUT

High Impedance

6

7

8

PCM_IN

PCM Interface

Table 9: PCM Interface Timing Specifications (Short Frame Sync, Slave Mode)

Ref No.

Characteristics

7

8

5

6

9

3

4

1

2

PCM bit clock frequency

PCM bit clock low

PCM bit clock high

PCM_SYNC setup

PCM_SYNC hold

PCM_OUT delay

PCM_IN setup

PCM_IN hold

Delay from rising edge of PCM_BCLK during last bit period to PCM_OUT becoming high impedance

Minimum Typical Maximum Unit

8

8

8

0

0

41

41

8

12

25

25 ns ns ns ns ns

MHz ns ns ns

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BCM4343W Data Sheet

Long Frame Sync, Master Mode

Figure 29: PCM Timing Diagram (Long Frame Sync, Master Mode)

1

2

3

PCM_BCLK

4

PCM_SYNC

PCM_OUT

5

Bit 0 Bit 1

8

6

High Impedance

7

Bit 0

PCM_IN

Bit 1

PCM Interface

Table 10: PCM Interface Timing Specifications (Long Frame Sync, Master Mode)

Ref No.

Characteristics

6

7

4

5

8

1

2

3

PCM bit clock frequency

PCM bit clock low

PCM bit clock high

PCM_SYNC delay

PCM_OUT delay

PCM_IN setup

PCM_IN hold

Delay from rising edge of PCM_BCLK during last bit period to PCM_OUT becoming high impedance

Minimum Typical

8

8

0

0

0

41

41

Maximum Unit

12

25

25

25 ns ns ns ns ns

MHz ns ns

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BCM4343W Data Sheet

Long Frame Sync, Slave Mode

Figure 30: PCM Timing Diagram (Long Frame Sync, Slave Mode)

1

2

3

PCM_BCLK

4

5

PCM_SYNC

PCM_OUT

6

Bit 0

Bit 1

9

7

HIGH IMPEDANCE

8

Bit 0 Bit 1

PCM_IN

PCM Interface

Table 11: PCM Interface Timing Specifications (Long Frame Sync, Slave Mode)

Ref No.

Characteristics

6

7

4

5

8

9

1

2

3

PCM bit clock frequency

PCM bit clock low

PCM bit clock high

PCM_SYNC setup

PCM_SYNC hold

PCM_OUT delay

PCM_IN setup

PCM_IN hold

Delay from rising edge of PCM_BCLK during last bit period to PCM_OUT becoming high impedance

Minimum Typical

0

8

8

8

8

0

41

41

Maximum Unit

12

25

25 ns ns ns ns

MHz ns ns ns ns

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BCM4343W Data Sheet UART Interface

Desired Rate

230400

115200

57600

38400

28800

19200

14400

9600

4000000

3692000

3000000

2000000

1500000

1444444

921600

460800

UART Interface

The BCM4343W shares a single UART for Bluetooth and FM. The UART is a standard 4-wire interface (RX, TX,

RTS, and CTS) with adjustable baud rates from 9600 bps to 4.0 Mbps. The interface features an automatic baud rate detection capability that returns a baud rate selection. Alternatively, the baud rate may be selected through a vendor-specific UART HCI command.

The UART has a 1040-byte receive FIFO and a 1040-byte transmit FIFO to support EDR. Access to the FIFOs is conducted through the Advanced High Performance Bus (AHB) interface through either DMA or the CPU. The

UART supports the Bluetooth 4.1 UART HCI specification: H4 and H5. The default baud rate is 115.2 Kbaud.

The UART supports the 3-wire H5 UART transport as described in the Bluetooth specification (Three-wire UART

Transport Layer

). Compared to H4, the H5 UART transport reduces the number of signal lines required by eliminating the CTS and RTS signals.

The BCM4343W UART can perform XON/XOFF flow control and includes hardware support for the Serial Line

Input Protocol (SLIP). It can also perform a wake-on activity function. For example, activity on the RX or CTS inputs can wake the chip from a sleep state.

Normally, the UART baud rate is set by a configuration record downloaded after device reset or by automatic baud rate detection, and the host does not need to adjust the baud rate. Support for changing the baud rate during normal HCI UART operation is included through a vendor-specific command that allows the host to adjust the contents of the baud rate registers. The BCM4343W UARTs operate correctly with the host UART as long

as the combined baud rate error of the two devices is within ±2% (see Table 12 ).

Table 12: Example of Common Baud Rates

Actual Rate

230796

115385

57692

38400

28846

19200

14423

9600

4000000

3692308

3000000

2000000

1500000

1454544

923077

461538

Error (%)

0.17

0.16

0.16

0.00

0.16

0.00

0.16

0.00

0.00

0.01

0.00

0.00

0.00

0.70

0.16

0.16

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BCM4343W Data Sheet

UART timing is defined in

Figure 31 and Table 13 .

Figure 31: UART Timing

UART_CTS_N

1

UART_TXD

Midpoint of STOP bit

UART_RXD

UART_RTS_N

3

2

UART Interface

Midpoint of STOP bit

Table 13: UART Timing Specifications

Ref No.

Characteristics

1

2

3

Delay time, UART_CTS_N low to UART_TXD valid

Setup time, UART_CTS_N high before midpoint of stop bit

Delay time, midpoint of stop bit to UART_RTS_N high

Minimum Typical

– –

Maximum Unit

1.5

Bit periods

0.5

0.5

Bit periods

Bit periods

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BCM4343W Data Sheet I

2

S Interface

I

2

S Interface

The BCM4343W supports an independent I

2

The I

2

S digital audio port for high-fidelity FM audio or Bluetooth audio.

S interface supports both master and slave modes. The I

2

S signals are:

• I

2

S Clock: I

2

S SCK

• I

2

S Word Select: I

2

S WS

• I

2

S Data Out: I

2

S SDO

• I

2

S Data In: I

2

S SDI

I

2

S SCK and I

2

S WS become outputs in master mode and inputs in slave mode, while I

2

S SDO is always an output. The channel word length is 16 bits and the data is justified so that the MSB of the left-channel data is aligned with the MSB of the I

2

S bus, per the I

2

S specification. The MSB of each data word is transmitted one bit-clock cycle after the I is transmitted when I

2

2

S WS transition, synchronous with the falling edge of the bit clock. Left-channel data

S WS is low, and right-channel data is transmitted when I

2

S WS is high. Data bits sent by the BCM4343W are synchronized with the falling edge of I2S_SCK and should be sampled by the receiver on the rising edge of I2S_SSCK.

The clock rate in master mode is either of the following:

48 kHz x 32 bits per frame = 1.536 MHz

48 kHz x 50 bits per frame = 2.400 MHz

The master clock is generated from the input reference clock using an N/M clock divider.

In slave mode, clock rates up to 3.072 MHz are supported.

I

2

S Timing

Note:

Timing values specified in

Table 14

are relative to high and low threshold levels.

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BCM4343W Data Sheet I

2

S Interface

Table 14: Timing for I

2

S Transmitters and Receivers

Transmitter

Lower LImit Upper Limit

Clock period T

Min.

T tr

Max.

Min.

Max.

Master mode: Clock generated by transmitter or receiver.

High t

HC

Low t

LC

0.35T

0.35T

tr tr

Slave mode: Clock accepted by transmitter or receiver.

High t

HC

Low t

LC

Rise time t

RC

Transmitter

0.35T

tr

0.35T

tr

0.15T

tr

Delay t dtr

Hold time t htr

Receiver

Setup time t sr

Hold time t hr

0

0.8T

Receiver

Lower Limit

Min.

T r

Max.

Upper Limit

Min.

Max.

0.35T

0.35T

– tr tr

0.35T

0.35T

0.2T

0 r tr tr

Notes

1

2

2

3

3

4

5

4

6

6

Note:

• The system clock period T must be greater than T tr

and T r

because both the transmitter and receiver have to be able to handle the data transfer rate.

• At all data rates in master mode, the transmitter or receiver generates a clock signal with a fixed mark/space ratio. For this reason, t

HC

and t

LC

are specified with respect to T.

• In slave mode, the transmitter and receiver need a clock signal with minimum high and low periods so that they can detect the signal. As long as the minimum periods are greater than 0.35T

r

, any clock that meets the requirements can be used.

• Because the delay (t dtr

) and the maximum transmitter speed (defined by T tr

) are related, a fast transmitter driven by a slow clock edge can result in t dtr

not exceeding t

RC equal to zero, as long as the clock rise-time, t

RC than 0.15T

tr

.

, does not exceed t

RCmax

, which means t becomes zero or negative. Therefore, the transmitter has to guarantee that t htr htr

is greater than or

, where t

RCmax

is not less

• To allow data to be clocked out on a falling edge, the delay is specified with respect to the rising edge of the clock signal and T, always giving the receiver sufficient setup time.

• The data setup and hold time must not be less than the specified receiver setup and hold time.

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BCM4343W Data Sheet I

2

S Interface

Note:

The time periods specified in Figure 32

and

Figure 33

are defined by the transmitter speed. The receiver specifications must match transmitter performance.

Figure 32: I

2

S Transmitter Timing

T t

RC

* t

LC

> 0.35T

t

HC

> 0.35T

SCK

V

H

= 2.0V

V

L

= 0.8V

t htr

> 0 t dtr

< 0.8T

SD and WS

T = Clock period

T tr

T = T tr

* t

= Minimum allowed clock period for transmitter

RC is only relevant for transmitters in slave mode.

Figure 33: I

2

S Receiver Timing

T t

LC

> 0.35T

SCK t

HC

> 0.35

V

H

= 2.0V

V

L

= 0.8V

t sr

> 0.2T

t hr

> 0

SD and WS

T = Clock period

T r

= Minimum allowed clock period for transmitter

T > T r

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BCM4343W Data Sheet FM Receiver Subsystem

Section 11: FM Receiver Subsystem

FM Radio

The BCM4343W includes a completely integrated FM radio receiver with RDS/RBDS covering all FM bands from 65 MHz to 108 MHz. The receiver is controlled through commands on the HCI. FM received audio is available as a stereo analog output or in digital form through I

2

S or PCM. The FM radio operates from the external clock reference.

Digital FM Audio Interfaces

The FM audio can be transmitted via the shared PCM and I

2

S pins, and the sampling rate is programmable.

The BCM4343W supports a three-wire PCM or I

2

S audio interface in either a master or slave configuration. The master or slave configuration is selected using vendor specific commands over the HCI interface. In addition, multiple sampling rates are supported, derived from either the FM or Bluetooth clocks. In master mode, the clock rate is either of the following:

• 48 kHz x 32 bits per frame = 1.536 MHz

• 48 kHz x 50 bits per frame = 2.400 MHz

In slave mode, clock rates up to 3.072 MHz are supported.

Analog FM Audio Interfaces

The demodulated FM audio signal is available as line-level analog stereo output, generated by twin internal high

SNR audio DACs.

FM Over Bluetooth

The BCM4343W can output received FM audio onto Bluetooth using one of following three links: eSCO, WBS, or A2DP. For all link types, after a link has been established, the host processor can enter sleep mode while the

BCM4343W streams FM audio to the remote Bluetooth device, thus minimizing system current consumption.

eSCO

In this use case, the stereo FM audio is downsampled to 8 kHz and a mono or stereo stream is sent through the

Bluetooth eSCO link to a remote Bluetooth device, typically a headset. Two Bluetooth voice connections must be used to transport stereo.

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BCM4343W Data Sheet Wideband Speech Link

Wideband Speech Link

In this case, the stereo FM audio is downsampled to 16 kHz and a mono or stereo stream is sent through the

Bluetooth wideband speech link to a remote Bluetooth device, typically a headset. Two Bluetooth voice connections must be used to transport stereo.

A2DP

In this case, the stereo FM audio is encoded by the on-chip SBC encoder and transported as an A2DP link to a remote Bluetooth device. Sampling rates of 48 kHz, 44.1 kHz, and 32 kHz joint stereo are supported. An A2DP lite stack is implemented in the BCM4343W to support this use case, which eliminates the need to route the

SBC-encoded audio back to the host to create the A2DP packets.

Autotune and Search Algorithms

The BCM4343W supports a number of FM search and tune functions, allowing the host to implement many convenient user functions by accessing the Broadcom FM stack.

• Tune to Play—Allows the FM receiver to be programmed to a specific frequency.

• Search for SNR > Threshold—Checks the power level of the available channel and the estimated SNR of the channel to help achieve precise control of the expected sound quality for the selected FM channel.

Specifically, the host can adjust its SNR requirements to retrieve a signal with a specific sound quality, or adjust this to return the weakest channels.

• Alternate Frequency Jump—Allows the FM receiver to automatically jump to an alternate FM channel that carries the same information, but has a better SNR. For example, when traveling, a user may pass through a region where a number of channels carry the same station. When the user passes from one area to the next, the FM receiver can automatically switch to another channel with a stronger signal to spare the user from having to manually change the channel to continue listening to the same station.

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BCM4343W Data Sheet Audio Features

Audio Features

A number of features are implemented in the BCM4343W to provide the best possible audio experience for the user.

• Mono/Stereo Blend or Switch—The BCM4343W provides automatic control of the stereo or mono settings based on the FM signal carrier-to-noise ratio (C/N). This feature is used to maintain the best possible audio

SNR based on the FM channel condition. Two modes of operation are supported:

– Blend: In this mode, fine control of stereo separation is used to achieve optimal audio quality over a

wide range of input C/N. The amount of separation is fully programmable. In Figure 34

, the separation is programmed to maintain a minimum 50 dB SNR across the blend range.

– Switch: In this mode, the audio switches from full stereo to full mono at a predetermined level to maintain optimal audio quality. The stereo-to-mono switch point and the mono-to-stereo switch points

are fully programmable to provide the desired amount of audio SNR. In Figure 35

, the switch point is programmed to switch to mono to maintain a 40 dB SNR.

Figure 34: Blending and Switching Usage

Input C/N (dB)

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BCM4343W Data Sheet

Figure 35: Blending and Switching Separation

Audio Features

Input C/N (dB)

• Soft Mute—Improves the user experience by dynamically muting the output audio proportionate to the FM signal C/N. This prevents a blast of static to the user. The mute characteristic is fully programmable to accommodate fine tuning of the output signal level. An example mute characteristic is shown in

Figure 36 .

Figure 36: Soft Muting Characteristic

Input C/N (dB)

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BCM4343W Data Sheet RDS/RBDS

• High Cut—A programmable high-cut filter is provided to reduce the amount of high-frequency noise caused by static in the output audio signal. Like the soft mute circuit, it is fully programmable to provide any amount of high cut based on the FM signal C/N.

• Audio Pause Detect—The FM receiver monitors the magnitude of the audio signal and notifies the host through an interrupt when the magnitude of the signal has fallen below the threshold set for a programmable period. This feature can be used to provide alternate frequency jumps during periods of silence to minimize disturbances to the listener. Filtering techniques are used within the audio pause detection block to provide more robust presence-to-silence detection and silence-to-presence detection.

• Automatic Antenna Tuning—The BCM4343W has an on-chip automatic antenna tuning network. When used with a single off-chip inductor, the on-chip circuitry automatically chooses an optimal on-chip matching component to obtain the highest signal strength for the desired frequency. The high-Q nature of this matching network simultaneously provides out-of-band blocking protection as well as a reduction of radiated spurious emissions from the FM antenna. It is designed to accommodate a wide range of external wire antennas.

RDS/RBDS

The BCM4343W integrates a RDS/RBDS modem, the decoder includes programmable filtering and buffering functions. The RDS/RBDS data can be read out through the HCI interface.

In addition, the RDS/RBDS receive functionality supports the following:

• Block decoding, error correction, and synchronization

• A flywheel synchronization feature, allowing the host to set parameters for acquisition, maintenance, and loss of sync. (It is possible to set up the BCM4343W such that synchronization is achieved when a minimum of two good blocks (error free) are decoded in sequence. The number of good blocks required for sync is programmable.)

• Storage capability up to 126 blocks of RDS data

• Full or partial block-B match detection with host interruption

• Audio pause detection with programmable parameters

• Program Identification (PI) code detection with host interruption

• Automatic frequency jumping

• Block-E filtering

• Soft muting

• Signal dependent mono/stereo blending

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BCM4343W Data Sheet CPU and Global Functions

Section 12: CPU and Global Functions

WLAN CPU and Memory Subsystem

The BCM4343W includes an integrated ARM Cortex-M3 processor with internal RAM and ROM. The ARM

Cortex-M3 processor is a low-power processor that features low gate count, low interrupt latency, and low-cost debugging. It is intended for deeply embedded applications that require fast interrupt response features. The processor implements the ARM architecture v7-M with support for the Thumb-2 instruction set. ARM Cortex-M3 provides a 30% performance gain over ARM7TDMI.

At 0.19 µW/MHz, the Cortex-M3 is the most power efficient general purpose microprocessor available, outperforming 8- and 16-bit devices on MIPS/µW. It supports integrated sleep modes.

ARM Cortex-M3 uses multiple technologies to reduce cost through improved memory utilization, reduced pin overhead, and reduced silicon area. ARM Cortex-M3 supports independent buses for code and data access

(ICode/DCode and system buses). ARM Cortex-M3 supports extensive debug features including real-time tracing of program execution.

On-chip memory for the CPU includes 512 KB SRAM and 640 KB ROM.

One-Time Programmable Memory

Various hardware configuration parameters may be stored in an internal 4096-bit One-Time Programmable

(OTP) memory, which is read by system software after a device reset. In addition, customer-specific parameters, including the system vendor ID and the MAC address, can be stored, depending on the specific board design.

The initial state of all bits in an unprogrammed OTP device is 0. After any bit is programmed to a 1, it cannot be reprogrammed to 0. The entire OTP array can be programmed in a single write cycle using a utility provided with the Broadcom WLAN manufacturing test tools. Alternatively, multiple write cycles can be used to selectively program specific bytes, but only bits which are still in the 0 state can be altered during each programming cycle.

Prior to OTP memory programming, all values should be verified using the appropriate editable nvram.txt file, which is provided with the reference board design package. Documentation on the OTP development process is available on the Broadcom customer support portal (http://www.broadcom.com/support).

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BCM4343W Data Sheet GPIO Interface

GPIO Interface

Five general purpose I/O (GPIO) pins are available on the BCM4343W that can be used to connect to various external devices.

GPIOs are tristated by default. Subsequently, they can be programmed to be either input or output pins via the

GPIO control register. They can also be programmed to have internal pull-up or pull-down resistors.

GPIO_0 is normally used as a WL_HOST_WAKE signal.

The BCM4343W supports 2-wire, 3-wire, and 4-wire coexistence configurations using GPIO_1 through GPIO_4.

The signal functions of GPIO_1 through GPIO_4 are programmable to support the three coexistence configurations.

External Coexistence Interface

The BCM4343W supports 2-wire, 3-wire, and 4-wire coexistence interfaces to enable signaling between the device and an external colocated wireless device in order to manage wireless medium sharing for optimal performance. The external colocated device can be any of the following ICs: GPS, WiMAX, LTE, or UWB. An

LTE IC is used in this section for illustration.

2-Wire Coexistence

Figure 37 shows a 2-wire LTE coexistence example. The following definitions apply to the GPIOs in the figure:

• GPIO_1: WLAN_SECI_TX output to an LTE IC.

• GPIO_2: WLAN_SECI_RX input from an LTE IC.

Figure 37: 2-Wire Coexistence Interface to an LTE IC

WLAN

Coexistence 

Interface

GPIO_1

GPIO_2

WLAN_SECI_TX

WLAN_SECI_RX

UART_IN

UART_OUT

BT/FM

BCM4343W LTE/IC

Notes: 

 OR’ing to generate ISM_RX_PRIORITY for ERCX_TXCONF or BT_RX_PRIORITY is achieved by  setting the GPIO mask registers appropriately.

 WLAN_SECI_OUT and WLAN_SECI_IN are multiplexed on the GPIOs.

See Figure 31 on page 71 and Table 13: “UART Timing Specifications,” on page 71

for UART timing.

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BROADCOM CONFIDENTIAL

BCM4343W Data Sheet External Coexistence Interface

3-Wire and 4-Wire Coexistence Interfaces

Figure 38

and Figure 39 show 3-wire and 4-wire LTE coexistence examples, respectively. The following

definitions apply to the GPIOs in the figures:

• For the 3-wire coexistence interface:

• GPIO_2: WLAN priority output to an LTE IC.

• GPIO_3: LTE_RX input from an LTE IC.

• GPIO_4: LTE_TX input from an LTE IC.

For the 4-wire coexistence interface:

• GPIO_1: WLAN priority output to an LTE IC.

• GPIO_2: LTE frame sync input from an LTE IC. This GPIO applies only to the 4-wire coexistence interface.

• GPIO_3: LTE_RX input from an LTE IC.

• GPIO_4: LTE_TX input from an LTE IC.

Figure 38: 3-Wire Coexistence Interface to an LTE IC

WLAN

Coexistence 

Interface

GPIO_2

GPIO_3

GPIO_4

WLAN Priority

LTE_RX

LTE_TX

BT/FM

BCM4343W

LTE/IC

Note: OR’ing to generate WCN_PRIORITY for ERCX_TXCONF or BT_RX_PRIORITY is achieved by  setting the GPIO mask registers appropriately.

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BROADCOM CONFIDENTIAL

BCM4343W Data Sheet

Figure 39: 4-Wire Coexistence Interface to an LTE IC

WLAN

Coexistence 

Interface

GPIO_1

GPIO_2

GPIO_3

GPIO_4

WLAN Priority

LTE_Frame_Sync

LTE_RX

LTE_TX

BT/FM

BCM4343W

LTE/IC

Note: OR’ing to generate WCN_PRIORITY for ERCX_TXCONF or BT_RX_PRIORITY is achieved by  setting the GPIO mask registers appropriately.

JTAG Interface

JTAG Interface

The BCM4343W supports the IEEE 1149.1 JTAG boundary scan standard over SDIO for performing device package and PCB assembly testing during manufacturing. In addition, the JTAG interface allows Broadcom to assist customers by using proprietary debug and characterization test tools during board bring-up. Therefore, it is highly recommended to provide access to the JTAG pins by means of test points or a header on all PCB designs.

UART Interface

One UART interface can be enabled by software as an alternate function on the JTAG pins. UART_RX is available on the JTAG_TDI pin, and UART_TX is available on the JTAG_TDO pin.

The UART is primarily for debugging during development. By adding an external RS-232 transceiver, this UART enables the BCM4343W to operate as RS-232 data termination equipment (DTE) for exchanging and managing data with other serial devices. It is compatible with the industry standard 16550 UART, and it provides a FIFO size of 64 × 8 in each direction.

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BROADCOM CONFIDENTIAL

BCM4343W Data Sheet WLAN Software Architecture

Section 13: WLAN Software Architecture

Host Software Architecture

The host driver (DHD) provides a transparent connection between the host operating system and the

BCM4343W media (for example, WLAN) by presenting a network driver interface to the host operating system and communicating with the BCM4343W over an interface-specific bus (SPI, SDIO, and so on) to:

• Forward transmit and receive frames between the host network stack and the BCM4343W device.

• Pass control requests from the host to the BCM4343W device, returning the BCM4343W device responses.

The driver communicates with the BCM4343W over the bus using a control channel and a data channel to pass control messages and data messages. The actual message format is based on the BDC protocol.

Device Software Architecture

The wireless device, protocol, and bus drivers are run on the embedded ARM processor using a Broadcomdefined operating system called HNDRTE, which transfers data over a propriety Broadcom format over the

SDIO/SPI interface between the host and device (BDC/LMAC). The data portion of the format consists of

IEEE 802.11 frames wrapped in a Broadcom encapsulation. The host architecture provides all missing functionality between a network device and the Broadcom device interface. The host can also be customized to provide functionality between the Broadcom device interface and a full network device interface.

This transfer requires a message-oriented (framed) interconnect between the host and device. The SDIO bus is an addressed bus—each host-initiated bus operation contains an explicit device target address—and does not natively support a higher-level data frame concept. Broadcom has implemented a hardware/software message encapsulation scheme that ignores the bus operation code address and prefixes each frame with a 4byte length tag for framing. The device presents a packet-level interface over which data, control, and asynchronous event (from the device) packets are supported.

The data and control packets received from the bus are initially processed by the bus driver and then passed on to the protocol driver. If the packets are data packets, they are transferred to the wireless device driver (and out through its medium), and a data packet received from the device medium follows the same path in the reverse direction. If the packets are control packets, the protocol header is decoded by the protocol driver. If the packets are wireless IOCTL packets, the IOCTL API of the wireless driver is called to configure the wireless device. The microcode running in the D11 core processes all time-critical tasks.

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BROADCOM CONFIDENTIAL

BCM4343W Data Sheet Wireless Configuration Utility

Remote Downloader

When the BCM4343W powers up, the DHD initializes and downloads the firmware to run in the device.

Figure 40: WLAN Software Architecture

DHD Host Driver

SPI/SDIO

BDC/LMAC Protocol

Wireless Device Driver

D11 Core

Wireless Configuration Utility

The device driver that supports the Broadcom IEEE 802.11 family of wireless solutions provides an input/output control (IOCTL) interface for making advanced configuration settings. The IOCTL interface makes it possible to make settings that are normally not possible when using just the native operating system-specific IEEE 802.11 configuration mechanisms. The utility uses IOCTLs to query or set a number of different driver/chip operating properties.

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BCM4343W Data Sheet

Pinout and Signal Descriptions

Section 14: Pinout and Signal Descriptions

Ball Map

Figure 41

shows the 74-ball WLBGA ball map. Figure 42 on page 87

shows the 153-bump WLCSP.

Figure 41: 74-Ball WLBGA Ball Map (Bottom View)

A B C

1

BT_UART_R

XD

BT_DEV_W

AKE

BT_HOST_

WAKE

D

4

BT_I2S_CL

K

BT_PCM_O

UT

BT_PCM_IN VSSC

E F G H J K

FM_RF_IN

BT_VCO_V

DD

BT_IF_VDD BT_PAVDD

WLRF_2G_ eLG

WLRF_2G_

RF

BT_GPIO_3 VDDC

WLRF_AFE

_GND

L M

WLRF_PA_

VDD

1

2

BT_UART_T

XD

BT_UART_C

TS_N

FM_OUT1 FM_OUT2

FM_RF_VD

D

BTFM_PLL_

VDD

BTFM_PLL_

VSS

BT_IF_VSS

WLRF_LNA

_GND

WLRF_GEN

ERAL_GND

WLRF_PA_

GND

WLRF_VDD

_

1P35

2

3

BT_I2S_

WS

BT_I2S_DO

BT_UART_R

TS_N

VDDC

FM_RF_VS

S

BT_VCO_V

SS

WLRF_GPI

O

WLRF_VCO

_GND

WLRF_XTA

L_

VDD1P2

3

GPIO_3

WLRF_XTA

L_GND

WLRF_XTA

L_XOP

4

5

BT_PCM_C

LK

BT_PCM_S

YNC

SYS_VDDI

O

WPT_1P8 WPT_3P3 LPO_IN BT_GPIO_4 BT_GPIO_5 VSSC GPIO_4 GPIO_2

WLRF_XTA

L_XON

5

6

SR_VLX PMU_AVSS

VOUT_CLD

O

VOUT_LNL

DO

BT_REG_O

N

WCC_VDDI

O

WL_REG_O

N

GPIO_1 GPIO_0

SDIO_DATA

_0

SDIO_CMD CLK_REQ

6

7

SR_PVSS

SR_VDDBA

T5V

LDO_VDD1

P5

A B C D

VOUT_3P3

LDO_VDDB

AT5V

E F G

SDIO_DATA

_1

SDIO_DATA

_3

H J K

SDIO_DATA

_2

SDIO_CLK 7

L M

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BROADCOM CONFIDENTIAL

BCM4343W Data Sheet

Figure 42: 153-Bump WLCSP (Top View)

Ball Map

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BROADCOM CONFIDENTIAL

BCM4343W Data Sheet WLBGA Ball List in Ball Number Order with X-Y Coordinates

Ball Number

E2

E3

E5

D4

D5

D6

E1

E6

E7

F1

C6

C7

D2

D3

C3

C4

C5

B6

B7

C1

C2

B2

B3

B4

B5

A4

A5

A6

A7

B1

A1

A2

A3

WLBGA Ball List in Ball Number Order with X-Y Coordinates

Table 15

provides ball numbers and names in ball number order. The table includes the X and Y coordinates for a top view with a (0,0) center.

Table 15: BCM4343W WLBGA Ball List — Ordered By Ball Number

Ball Name

BT_UART_RXD

BT_UART_TXD

BT_I2S_WS or BT_PCM_SYNC

BT_I2S_CLK or BT_PCM_CLK

BT_PCM_CLK or BT_I2S_CLK

SR_VLX

SR_PVSS

BT_DEV_WAKE

BT_UART_CTS_N

BT_I2S_DO or BT_PCM_OUT

BT_PCM_OUT or BT_I2S_DO

BT_PCM_SYNC or BT_I2S_WS

PMU_AVSS

SR_VBAT5V

BT_HOST_WAKE

FM_OUT1

BT_UART_RTS_N

BT_PCM_IN or BT_I2S_DI

SYS_VDDIO

VOUT_CLDO

LDO_VDD15V

FM_OUT2

VDDC

VSSC

WPT_1P8

VOUT_LNLDO

FM_RF_IN

FM_RF_VDD

FM_RF_VSS

WPT_3P3

BT_REG_ON

VOUT_3P3

BT_VCO_VDD

X Coordinate

–399.996

0

399.996

799.992

1199.988

–799.992

–399.996

0

399.996

799.992

–1199.988

–799.992

–399.996

399.996

799.992

1199.988

–1199.988

–1200.006

–799.992

–399.996

0

399.996

799.992

1199.988

–1200.006

–799.992

–399.996

0

399.996

799.992

1199.988

–1200.006

–799.992

Y Coordinate

1399.995

1399.995

1399.986

1399.986

1399.986

999.99

999.999

999.999

999.99

999.99

599.994

599.994

599.994

599.994

599.994

599.994

199.998

2199.996

2199.996

2199.996

2199.996

2199.996

2199.978

2199.978

1800

1800

1800

1800

1800

1799.982

1799.982

1399.995

1399.986

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BROADCOM CONFIDENTIAL

BCM4343W Data Sheet WLBGA Ball List in Ball Number Order with X-Y Coordinates

L4

L5

L6

K5

K6

L2

L3

L7

M1

M2

M3

J7

K1

K2

K4

J3

J5

J6

H6

H7

J1

J2

H2

H3

H4

H5

Ball Number

F2

F4

G2

G4

G5

G6

H1

F5

F6

F7

G1

Table 15: BCM4343W WLBGA Ball List — Ordered By Ball Number (Cont.)

Ball Name

BTFM_PLL_VDD

BT_GPIO_3

LPO_IN

WCC_VDDIO

LDO_VBAT5V

BT_IF_VDD

BTFM_PLL_VSS

VDDC

BT_GPIO_4

WL_REG_ON

BT_PAVDD

BT_IF_VSS

BT_VCO_VSS

WLRF_AFE_GND

BT_GPIO_5

GPIO_1

SDIO_DATA_1

WLRF_2G_eLG

WLRF_LNA_GND

WLRF_GPIO

VSSC

GPIO_0

SDIO_DATA_3

WLRF_2G_RF

WLRF_GENERAL_GND

GPIO_3

GPIO_4

SDIO_DATA_0

WLRF_PA_GND

WLRF_VCO_GND

WLRF_XTAL_GND

GPIO_2

SDIO_CMD

SDIO_DATA_2

WLRF_PA_VDD

WLRF_VDD_1P35

WLRF_XTAL_VDD1P2

399.996

800.001

–799.992

–399.996

0

399.996

800.001

1200.006

–1199.988

–799.992

–399.996

–799.992

–399.996

0

399.996

800.001

1200.006

–1199.988

–799.992

–399.996

399.996

800.001

1200.006

–1199.988

–799.992

0

X Coordinate

–799.992

0

399.996

800.001

1199.988

–1199.988

–799.992

0

399.996

800.001

–1199.988

–1399.995

–1399.995

–1799.982

–1799.982

–1799.982

–1799.991

–1799.991

–1799.991

–2199.978

–2199.978

–2199.978

–599.994

–599.994

–599.994

–599.994

–599.994

–599.994

–999.99

–999.99

–999.99

–999.999

–999.999

–999.999

–1399.986

–1399.986

–1399.995

Y Coordinate

199.998

199.998

199.998

199.998

199.998

–199.998

–199.998

–199.998

–199.998

–199.998

–599.994

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BCM4343W Data Sheet WLBGA Ball List in Ball Number Order with X-Y Coordinates

Ball Number

M4

M5

M6

M7

Table 15: BCM4343W WLBGA Ball List — Ordered By Ball Number (Cont.)

Ball Name

WLRF_XTAL_XOP

WLRF_XTAL_XON

CLK_REQ

SDIO_CLK

X Coordinate

0

399.996

800.001

1200.006

Y Coordinate

–2199.978

–2199.978

–2199.996

–2199.996

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BROADCOM CONFIDENTIAL

BCM4343W Data Sheet WLCSP Bump List in Bump Order with X-Y Coordinates

WLCSP Bump List in Bump Order with X-Y Coordinates

Table 16: BCM4343W WLCSP Bump List — Ordered By Bump Number

1

2

3

Bump

Number Bump Name

7

8

9

10

4

5

6

11

12

13

14

15

16

17

18

19

28

29

30

25

26

27

20

21

22

23

24

BT_UART_RXD

BT_VDDC_ISO_2

BT_PCM_CLK or

BT_I2S_CLK

BT_TM1

BT_GPIO_3

BT_DEV_WAKE

BT_UART_RTS_N

BT_GPIO_4

BT_VDDC_ISO_1

BT_GPIO_5

BT_HOST_WAKE

BT_UART_TXD

Bump View

(0,0 Center of Die)

X Coordinate

1228.248

944.082

238.266

–327.438

662.544

379.692

1086.822

521.118

–44.586

–327.438

BT_GPIO_2

BT_VDDC

BT_I2S_CLK or

BT_PCM_CLK

1228.248

945.396

662.544

379.692

–186.012

BT_VDDC

BT_PCM_SYNC or

BT_I2S_WS

516.501

1086.822

BT_I2S_WS or

BT_PCM_SYNC

BT_PCM_OUT or

BT_I2S_DO

238.266

–327.438

BT_PCM_IN or BT_I2S_DI 662.544

VSSC

BT_UART_CTS_N

96.840

–186.012

BT_I2S_DI or BT_PCM_IN 238.266

BT_I2S_DO or

BT_PCM_OUT

–327.438

VSSC 96.840

BT_VDDC

VSSC

BT_VDDC

VSSC

VSSC

518.391

238.266

–44.586

110.286

–327.438

Y Coordinate

2133.594

2195.919

2275.020

2275.020

2133.594

2133.594

1992.168

1992.168

1992.168

1992.168

1850.742

1850.742

1850.742

1850.742

1850.742

1717.578

1709.316

1709.316

1709.316

1567.890

1567.890

1567.890

1426.464

1426.464

1285.038

1189.863

860.760

719.334

561.303

436.482

Top View

(0,0 Center of Die)

X Coordinate

–1228.248

–944.082

–238.266

327.438

–662.544

–379.692

–1086.822

–521.118

44.586

327.438

–1228.248

–945.396

–662.544

–379.692

186.012

–516.501

–1086.822

–238.266

327.438

–662.544

–96.840

186.012

–238.266

327.438

–96.840

–518.391

–238.266

44.586

–110.286

327.438

Y Coordinate

2133.594

2195.919

2275.020

2275.020

2133.594

2133.594

1992.168

1992.168

1992.168

1992.168

1850.742

1850.742

1850.742

1850.742

1850.742

1717.578

1709.316

1709.316

1709.316

1567.890

1567.890

1567.890

1426.464

1426.464

1285.038

1189.863

860.760

719.334

561.303

436.482

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BROADCOM CONFIDENTIAL

BCM4343W Data Sheet WLCSP Bump List in Bump Order with X-Y Coordinates

Bump

Number Bump Name

59

60

61

62

55

56

57

58

63

64

65

66

67

51

52

53

54

47

48

49

50

43

44

45

46

39

40

41

42

35

36

37

38

31

32

33

34

BT_VDDC

VSSC

VSSC

BT_VDDC

BT_PAVSS

VSSC

FM_DAC_VOUT1

FM_DAC_AVSS

FM_PLLAVSS

FM_DAC_VOUT2

FM_DAC_AVDD

FM_VCOVSS

FM_PLLDVDD1P2

FM_VCOVDD1P2

FM_RFVDD1P2

FM_RFVSS

FM_IFVSS

FM_IFDVDD1P2

FM_RFINMAIN

BT_DVSS

BT_IFVDD1P2

BT_AGPIO

BT_PAVDD2P5

BT_LNAVDD1P2

BT_LNAVSS

BT_PLLVSS

BT_VCOVDD1P2

BT_VCOVSS

BT_PLLVDD1P2

WRF_AFE_GND

WRF_RFIN_ELG_2G

WRF_RX2G_GND

WRF_RFIO_2G

WRF_GENERAL_GND

WRF_PA_GND3P3

WRF_VCO_GND

WRF_GPAIO_OUT

Table 16: BCM4343W WLCSP Bump List — Ordered By Bump Number (Cont.)

Bump View

(0,0 Center of Die)

Top View

(0,0 Center of Die)

563.990

563.990

383.225

160.911

148.775

–55.274

–255.272

–263.768

–463.766

–499.995

–655.268

–663.764

–699.993

–999.990

–1006.290

–1006.290

–1458.198

–1590.210

–1649.615

–1682.370

–1729.224

436.473

153.630

153.630

–185.976

–455.270

–836.352

1443.096

1443.096

1275.098

1243.098

1243.098

1043.100

960.593

892.373

764.213

563.990

X Coordinate Y Coordinate X Coordinate Y Coordinate

972.990

772.304

1276.551

686.628

886.626

1185.471

1185.462

781.893

781.893

429.885

1185.471

786.393

429.885

583.250

1262.642

1082.642

1206.990

628.713

986.531

451.188

799.992

521.118

238.266

–44.586

229.986

1185.471

–875.142

1243.031

1043.033

820.485

1243.031

1043.033

1252.220

820.485

1120.383

1274.787

1172.988

–972.990

–772.304

–1276.551

–686.628

–886.626

–1185.471

–1185.462

–781.893

–781.893

–429.885

–1185.471

–786.393

–429.885

–583.250

–1262.642

–1082.642

–1206.990

–628.713

–986.531

–451.188

–799.992

–521.118

–238.266

44.586

–229.986

–1185.471

875.142

–1243.031

–1043.033

–820.485

–1243.031

–1043.033

–1252.220

–820.485

–1120.383

–1274.787

–1172.988

563.990

563.990

383.225

160.911

148.775

–55.274

–255.272

–263.768

–463.766

–499.995

–655.268

–663.764

–699.993

–999.990

–1006.290

–1006.290

–1458.198

–1590.210

–1649.615

–1682.370

–1729.224

436.473

153.630

153.630

–185.976

–455.270

–836.352

1443.096

1443.096

1275.098

1243.098

1243.098

1043.100

960.593

892.373

764.213

563.990

Broadcom

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August 24, 2015 • 4343W-DS107-R

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Page 92

BROADCOM CONFIDENTIAL

BCM4343W Data Sheet WLCSP Bump List in Bump Order with X-Y Coordinates

Bump

Number Bump Name

96

97

98

99

92

93

94

95

100

101

102

103

104

88

89

90

91

84

85

86

87

80

81

82

83

76

77

78

79

72

73

74

75

68

69

70

71

WRF_PMU_VDD1P35

WRF_PA_GND3P3

WRF_PA_VDD3P3

WRF_PA_VDD3P3

WRF_XTAL_GND1P2

WRF_XTAL_VDD1P2

WRF_XTAL_XOP

WRF_XTAL_XON

LPO_IN

WCC_VDDIO

VSSC

WCC_VDDIO

GPIO_12

GPIO_11

GPIO_9

GPIO_10

GPIO_8

VSSC

VDDC

GPIO_7

VSSC

GPIO_6

VSSC

GPIO_4

VSSC

VDDC

GPIO_5

VDDC

WL_VDDP_ISO

GPIO_2

GPIO_3

WCC_VDDIO

GPIO_0

GPIO_1

VSSC

WCC_VDDIO

SDIO_CMD

Table 16: BCM4343W WLCSP Bump List — Ordered By Bump Number (Cont.)

Bump View

(0,0 Center of Die)

Top View

(0,0 Center of Die)

12.204

–129.222

–129.222

–129.222

–270.648

–270.648

–412.074

–412.074

–553.500

–553.500

–553.500

–694.926

–694.926

–694.926

–836.352

–977.778

–977.778

–1119.204

–1120.266

–1260.630

–1260.630

–1800.135

–1829.615

–2016.945

–2016.945

–2086.677

–2106.621

–2298.978

–2298.978

2133.594

2133.594

1850.742

1002.186

436.482

295.056

153.630

153.630

X Coordinate Y Coordinate X Coordinate Y Coordinate

–1157.994

–186.012

–468.864

–1299.420

–610.290

–1157.994

–44.586

–1299.420

96.840

–186.012

–1157.994

–44.586

–733.716

–1299.420

–1157.994

–1016.568

–1299.420

–1157.994

–720.954

–1016.568

–1299.420

612.878

986.531

1249.686

1069.686

274.613

75.519

311.126

131.126

96.840

–186.012

96.813

–44.586

–1299.420

–1157.994

–1016.568

–1299.420

1157.994

186.012

468.864

1299.420

610.290

1157.994

44.586

1299.420

–96.840

186.012

1157.994

44.586

733.716

1299.420

1157.994

1016.568

1299.420

1157.994

720.954

1016.568

1299.420

–612.878

–986.531

–1249.686

–1069.686

–274.613

–75.519

–311.126

–131.126

–96.840

186.012

–96.813

44.586

1299.420

1157.994

1016.568

1299.420

12.204

–129.222

–129.222

–129.222

–270.648

–270.648

–412.074

–412.074

–553.500

–553.500

–553.500

–694.926

–694.926

–694.926

–836.352

–977.778

–977.778

–1119.204

–1120.266

–1260.630

–1260.630

–1800.135

–1829.615

–2016.945

–2016.945

–2086.677

–2106.621

–2298.978

–2298.978

2133.594

2133.594

1850.742

1002.186

436.482

295.056

153.630

153.630

Broadcom

®

August 24, 2015 • 4343W-DS107-R

Single-Chip IEEE 802.11 b/g/n MAC/Baseband/Radio

Page 93

BROADCOM CONFIDENTIAL

BCM4343W Data Sheet WLCSP Bump List in Bump Order with X-Y Coordinates

Bump

Number Bump Name

133

134

135

136

129

130

131

132

137

138

139

140

141

125

126

127

128

121

122

123

124

117

118

119

120

113

114

115

116

109

110

111

112

105

106

107

108

GPIO_14

VSSC

VDDC

SDIO_CLK

GPIO_15

PACKAGEOPTION_0

VSSC

SDIO_DATA_0

PACKAGEOPTION_1

VDDC

SDIO_DATA_1

PACKAGEOPTION_2

JTAG_SEL

SDIO_DATA_2

GPIO_13

WCC_VDDIO

VSSC

SDIO_DATA_3

SR_PVSS

SR_PVSS

VSSC

SR_VLX

SR_VLX

SR_VLX

SR_VDDBAT5V

SR_VDDBAT5V

PMU_AVSS

SR_VDDBAT5V

LDO_VDD1P5

VOUT_CLDO

LDO_VDD1P5

VOUT_CLDO

WCC_VDDIO

VOUT_LNLDO

VOUT_3P3

SYS_VDDIO

LDO_VDDBAT5V

Table 16: BCM4343W WLCSP Bump List — Ordered By Bump Number (Cont.)

Bump View

(0,0 Center of Die)

Top View

(0,0 Center of Die)

–2109.186

–2250.612

2274.984

2274.984

2133.563

2133.563

2133.563

1992.141

1992.141

1992.141

1850.720

1850.720

1709.298

1567.877

1567.877

1426.455

1285.034

1285.034

1285.034

1143.612

1143.612

–1268.568

–1402.056

–1543.482

–1543.482

–1551.420

–1551.420

–1682.775

–1684.908

–1692.846

–1826.334

–1826.334

–1834.272

–1834.272

–1967.760

–2056.131

–2109.186

X Coordinate Y Coordinate X Coordinate Y Coordinate

–1299.420

–1157.994

–739.130

–1021.973

–597.708

–880.551

–1163.394

–739.130

–1021.973

–1304.816

–597.708

–880.551

–1021.973

–880.551

–1163.394

–739.130

–597.708

–880.551

–1163.394

–739.130

–1304.816

–137.700

–841.113

–1016.568

–1299.420

109.152

–173.700

–843.237

–1157.994

–32.274

–1016.568

–1299.420

109.152

–173.700

–1157.994

–232.227

–1016.568

1299.420

1157.994

739.130

1021.973

597.708

880.551

1163.394

739.130

1021.973

1304.816

597.708

880.551

1021.973

880.551

1163.394

739.130

597.708

880.551

1163.394

739.130

1304.816

137.700

841.113

1016.568

1299.420

–109.152

173.700

843.237

1157.994

32.274

1016.568

1299.420

–109.152

173.700

1157.994

232.227

1016.568

–2109.186

–2250.612

2274.984

2274.984

2133.563

2133.563

2133.563

1992.141

1992.141

1992.141

1850.720

1850.720

1709.298

1567.877

1567.877

1426.455

1285.034

1285.034

1285.034

1143.612

1143.612

–1268.568

–1402.056

–1543.482

–1543.482

–1551.420

–1551.420

–1682.775

–1684.908

–1692.846

–1826.334

–1826.334

–1834.272

–1834.272

–1967.760

–2056.131

–2109.186

Broadcom

®

August 24, 2015 • 4343W-DS107-R

Single-Chip IEEE 802.11 b/g/n MAC/Baseband/Radio

Page 94

BROADCOM CONFIDENTIAL

BCM4343W Data Sheet WLCSP Bump List in Bump Order with X-Y Coordinates

Bump

Table 16: BCM4343W WLCSP Bump List — Ordered By Bump Number (Cont.)

Number Bump Name

146

147

148

149

142

143

144

145

150

151

152

153

VSSC

VOUT_3P3_SENSE

VOUT_3P3

WPT_1P8

WPT_3P3

LDO_VDDBAT5V

WL_REG_ON

BT_REG_ON

WL_VDDM_ISO

PLL_VSSC

PLL_VDDC

CLK_REQ

Bump View

(0,0 Center of Die)

Top View

(0,0 Center of Die)

X Coordinate Y Coordinate X Coordinate Y Coordinate

–597.708

–880.551

–1163.394

–739.130

–1021.973

–1304.816

–597.708

–880.551

–875.142

–116.586

29.286

238.266

1002.191

1002.191

1002.191

860.769

860.769

860.769

719.348

719.348

12.204

–985.716

–1130.076

1992.168

597.708

880.551

1163.394

739.130

1021.973

1304.816

597.708

880.551

875.142

116.586

–29.286

–238.266

1002.191

1002.191

1002.191

860.769

860.769

860.769

719.348

719.348

12.204

-985.716

–1130.076

1992.168

Broadcom

®

August 24, 2015 • 4343W-DS107-R

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Page 95

BROADCOM CONFIDENTIAL

BCM4343W Data Sheet WLBGA Ball List Ordered By Ball Name

WLBGA Ball List Ordered By Ball Name

Table 17

provides the ball numbers and names in ball name order.

Ball Name

BT_DEV_WAKE

BT_GPIO_3

BT_GPIO_4

BT_GPIO_5

BT_HOST_WAKE

BT_I2S_CLK or BT_PCM_CLK

BT_I2S_DO or BT_PCM_OUT

BT_I2S_WS or BT_PCM_SYNC

BT_IF_VDD

BT_IF_VSS

BT_PAVDD

BT_PCM_CLK or BT_I2S_CLK

BT_PCM_IN or BT_I2S_DI

BT_PCM_OUT or BT_I2S_DO

BT_PCM_SYNC or BT_I2S_WS

BT_REG_ON

BT_UART_CTS_N

BT_UART_RTS_N

BT_UART_RXD

BT_UART_TXD

BT_VCO_VDD

BT_VCO_VSS

BTFM_PLL_VDD

BTFM_PLL_VSS

CLK_REQ

FM_OUT1

FM_OUT2

FM_RF_IN

FM_RF_VDD

FM_RF_VSS

GPIO_0

GPIO_1

GPIO_2

GPIO_3

GPIO_4

LDO_VDD1P5

LDO_VDDBAT5V

Ball Number

E2

E3

J6

H6

M6

C2

D2

E1

L5

K4

K5

C7

F7

F1

H3

F2

G2

B2

C3

A1

A2

C4

B4

B5

E6

G1

H2

H1

A5

C1

A4

B3

A3

B1

F4

G5

H5

Table 17: BCM4343W WLBGA Ball List — Ordered By Ball Name

Ball Name

LPO_IN

PMU_AVSS

SDIO_CLK

SDIO_CMD

SDIO_DATA_0

SDIO_DATA_1

SDIO_DATA_2

SDIO_DATA_3

SR_PVSS

SR_VDDBAT5V

SR_VLX

SYS_VDDIO

VDDC

VDDC

VOUT_3P3

VOUT_CLDO

VOUT_LNLDO

VSSC

VSSC

WCC_VDDIO

WL_REG_ON

WLRF_2G_eLG

WLRF_2G_RF

WLRF_AFE_GND

WLRF_GENERAL_GND

WLRF_GPIO

WLRF_LNA_GND

WLRF_PA_GND

WLRF_PA_VDD

WLRF_VCO_GND

WLRF_VDD_1P35

WLRF_XTAL_GND

WLRF_XTAL_VDD1P2

WLRF_XTAL_XON

WLRF_XTAL_XOP

WPT_1P8

WPT_3P3

Ball Number

M1

L3

M2

L4

K2

J3

J2

L2

M3

M5

M4

D5

E5

G6

J1

K1

H4

D6

D4

J5

F6

D3

G4

E7

C6

A7

B7

A6

C5

K6

H7

L7

J7

F5

B6

M7

L6

Broadcom

®

August 24, 2015 • 4343W-DS107-R

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Page 96

BROADCOM CONFIDENTIAL

BCM4343W Data Sheet WLCSP Bump List Ordered By Name

WLCSP Bump List Ordered By Name

Table 18

provides the bump numbers and names in bump name order.

Bump Name Bump Number(s)

BT_AGPIO

BT_DEV_WAKE

BT_DVSS

BT_GPIO_2

BT_GPIO_3

BT_GPIO_4

BT_GPIO_5

BT_HOST_WAKE

BT_I2S_CLK or BT_PCM_CLK 15

BT_I2S_DI or BT_PCM_IN 23

BT_I2S_DO or BT_PCM_OUT 24

BT_I2S_WS or BT_PCM_SYNC 18

BT_IFVDD1P2

BT_LNAVDD1P2

BT_LNAVSS

BT_PAVDD2P5

51

54

55

53

5

8

10

11

52

6

50

13

BT_PAVSS 35

BT_PCM_CLK or BT_I2S_CLK 3

BT_PCM_IN or BT_I2S_DI 20

BT_PCM_OUT or BT_I2S_DO 19

BT_PCM_SYNC or BT_I2S_WS 17

BT_PLLVDD1P2 59

BT_PLLVSS

BT_REG_ON

56

149

BT_TM1

BT_UART_CTS_N

BT_UART_RTS_N

BT_UART_RXD

BT_UART_TXD

BT_VCOVDD1P2

BT_VCOVSS

BT_VDDC

BT_VDDC_ISO_1

BT_VDDC_ISO_2

7

1

4

22

12

57

58

14, 16, 26, 28, 31,

34

9

2

Table 18: BCM4343W WLCSP Bump List — Ordered By Bump Name

Bump Name

CLK_REQ

FM_DAC_AVDD

FM_DAC_AVSS

FM_DAC_VOUT1

FM_DAC_VOUT2

FM_IFDVDD1P2

FM_IFVSS

FM_PLLAVSS

FM_PLLDVDD1P2

FM_RFINMAIN

FM_RFVDD1P2

FM_RFVSS

FM_VCOVDD1P2

FM_VCOVSS

GPIO_0

GPIO_1

GPIO_2

GPIO_3

GPIO_4

GPIO_5

GPIO_6

GPIO_7

GPIO_8

GPIO_9

GPIO_10

GPIO_11

GPIO_12

GPIO_13

GPIO_14

GPIO_15

JTAG_SEL

LDO_VDD1P5

LDO_VDDBAT5V

LPO_IN

PACKAGEOPTION_0

Bump Number(s)

89

87

84

82

97

98

91

94

83

81

80

119

105

109

117

133, 135

141, 147

76

110

44

42

100

101

43

49

45

46

40

48

47

39

153

41

38

37

Broadcom

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August 24, 2015 • 4343W-DS107-R

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Page 97

BROADCOM CONFIDENTIAL

BCM4343W Data Sheet

Bump Name

PACKAGEOPTION_1

PACKAGEOPTION_2

PLL_VDDC

PLL_VSSC

PMU_AVSS

SDIO_CLK

SDIO_CMD

SDIO_DATA_0

SDIO_DATA_1

SDIO_DATA_2

SDIO_DATA_3

SR_PVSS

SR_VDDBAT5V

SR_VLX

SYS_VDDIO

VDDC

VOUT_3P3

VOUT_3P3_SENSE

VOUT_CLDO

VOUT_LNLDO

VSSC

Bump Number(s)

131

108

104

112

113

116

152

151

115

118

122

123, 124

129, 130, 132

126, 127, 128

140

86, 93, 95, 107,

114

139, 144

143

134, 136

68

61

63

62

66

138

21, 25, 27, 29, 30,

32, 33, 36, 78, 85,

88, 90, 92, 102,

106, 111, 121, 125,

142

77, 79, 99, 103,

120, 137

148

150

96

145

146

60

64

67

65, 69, 70, 71

Bump Name

WRF_XTAL_GND1P2

WRF_XTAL_VDD1P2

WRF_XTAL_XON

WRF_XTAL_XOP

WLCSP Bump List Ordered By Name

Bump Number(s)

72

73

75

74

WCC_VDDIO

WL_REG_ON

WL_VDDM_ISO

WL_VDDP_ISO

WPT_1P8

WPT_3P3

WRF_AFE_GND

WRF_GENERAL_GND

WRF_GPAIO_OUT

WRF_PA_GND3P3

WRF_PMU_VDD1P35

WRF_RFIN_ELG_2G

WRF_RFIO_2G

WRF_RX2G_GND

WRF_VCO_GND

Broadcom

®

August 24, 2015 • 4343W-DS107-R

Single-Chip IEEE 802.11 b/g/n MAC/Baseband/Radio

Page 98

BROADCOM CONFIDENTIAL

BCM4343W Data Sheet Signal Descriptions

Signal Descriptions

Table 19

provides the WLBGA package signal descriptions.

Table 19: WLBGA Signal Descriptions

Signal Name WLBGA Ball Type Description

RF Signal Interface

WLRF_2G_RF

SDIO Bus Interface

SDIO_CLK

SDIO_CMD

SDIO_DATA_0

SDIO_DATA_1

SDIO_DATA_2

SDIO_DATA_3

K1

M7

L6

K6

H7

L7

J7

I

O

I/O

I/O

I/O

I/O

I/O

2.4 GHz BT and WLAN RF output port

SDIO clock input

SDIO command line

SDIO data line 0

SDIO data line 1.

SDIO data line 2. Also used as a strapping option (see

Table 23 on page 110

).

SDIO data line 3

Note:

Per Section 6 of the SDIO specification, 10 to 100 kΩ pull-ups are required on the four DATA lines and the CMD line. This requirement must be met during all operating states by using external pull-up resistors or properly programming internal SDIO host pull-ups.

WLAN GPIO Interface

WLRF_GPIO J3 I/O Test pin. Not connected in normal operation.

Clocks

WLRF_XTAL_XON

WLRF_XTAL_XOP

CLK_REQ

LPO_IN

M5

M4

M6

F5 I

I

O

O

XTAL oscillator output

XTAL oscillator input

External system clock request—Used when the system clock is not provided by a dedicated crystal (for example, when a shared TCXO is used). Asserted to indicate to the host that the clock is required. Shared by

BT, and WLAN.

External sleep clock input (32.768 kHz). If an external 32.768 kHz clock cannot be provided, pull this pin low. However, BLE will be always on and cannot go to deep sleep.

FM Receiver

FM_OUT1

FM_OUT2

FM_RF_IN

FM_RF_VDD

C2

D2

E1

E2

I

I

O

O

FM analog output 1

FM analog output 2

FM radio antenna port

FM power supply

Broadcom

®

August 24, 2015 • 4343W-DS107-R

Single-Chip IEEE 802.11 b/g/n MAC/Baseband/Radio

Page 99

BROADCOM CONFIDENTIAL

BCM4343W Data Sheet Signal Descriptions

Table 19: WLBGA Signal Descriptions (Cont.)

Signal Name WLBGA Ball Type Description

Bluetooth PCM

BT_PCM_CLK or BT_I2S_CLK

BT_PCM_IN or BT_I2S_DI

BT_PCM_OUT or BT_I2S_DO

BT_PCM_SYNC or BT_I2S_WS

A5

C4

B4

B5

I

I/O

O

I/O

PCM or I

2

S clock; can be master (output) or slave (input)

PCM or I

2

S data input sensing

PCM or I

2

S data output

PCM SYNC or I2S_WS; can be master

(output) or slave (input)

Bluetooth GPIO

BT_GPIO_3

BT_GPIO_4

BT_GPIO_5

Bluetooth UART and Wake

F4

G5

H5

I/O

I/O

I/O

WPT_INTb to wireless charging PMU.

BSC_SDA to/from wireless charging PMU.

BSC_SCL from wireless charging PMU.

BT_UART_CTS_N

BT_UART_RTS_N

BT_UART_RXD

B2

C3

A1 I

I

O

UART clear-to-send. Active-low clear-to-send signal for the HCI UART interface.

UART request-to-send. Active-low requestto-send signal for the HCI UART interface.

UART serial input. Serial data input for the

HCI UART interface.

BT_UART_TXD

BT_DEV_WAKE

A2

B1

O

I/O

UART serial output. Serial data output for the

HCI UART interface.

DEV_WAKE or general-purpose I/O signal.

BT_HOST_WAKE C1 I/O HOST_WAKE or general-purpose I/O signal.

Note:

By default, the Bluetooth BT WAKE signals provide GPIO/WAKE functionality, and the UART pins provide UART functionality. Through software configuration, the PCM interface can also be routed over the

BT_WAKE/UART signals as follows:

• PCM_CLK on the UART_RTS_N pin

• PCM_OUT on the UART_CTS_N pin

• PCM_SYNC on the BT_HOST_WAKE pin

• PCM_IN on the BT_DEV_WAKE pin

In this case, the BT HCI transport included sleep signaling will operate using UART_RXD and UART_TXD; that is, using a 3-Wire UART Transport.

Bluetooth/FM I

2

S

BT_I2S_CLK or BT_PCM_CLK A4 I/O

BT_I2S_DO or BT_PCM_OUT

BT_I2S_WS or BT_PCM_SYNC

B3

A3

I/O

I/O

I

2

S or PCM clock; can be master (output) or slave (input)

I

2

S or PCM data output

I

2

S WS or PCM sync; can be master (output) or slave (input)

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August 24, 2015 • 4343W-DS107-R

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Page 100

BROADCOM CONFIDENTIAL

BCM4343W Data Sheet Signal Descriptions

Signal Name

Miscellaneous

WL_REG_ON

BT_REG_ON

WPT_3P3

WPT_1P8

GPIO_0

GPIO_1

GPIO_2

GPIO_3

GPIO_4

WLRF_2G_eLG

Integrated Voltage Regulators

SR_VDDBAT5V

SR_VLX

LDO_VDDBAT5V

LDO_VDD1P5

VOUT_LNLDO

VOUT_CLDO

Bluetooth Power Supplies

BT_PAVDD

BT_IF_VDD

BTFM_PLL_VDD

BT_VCO_VDD

Table 19: WLBGA Signal Descriptions (Cont.)

WLBGA Ball Type Description

G6

E6

E5

D5

J6

H6

L5

K4

K5

J1

B7

A6

F7

C7

D6

C6

H1

G1

F2

F1

I

I

I

I

I

I

O

O

I

I

I/O

I/O

I/O

I

I/O

N/A

N/A

I/O

Used by PMU to power up or power down the internal regulators used by the WLAN section.

Also, when deasserted, this pin holds the

WLAN section in reset. This pin has an internal 200 k

 pull-down resistor that is enabled by default. It can be disabled through programming.

Used by PMU to power up or power down the internal regulators used by the Bluetooth/FM section. Also, when deasserted, this pin holds the Bluetooth/FM section in reset. This pin has an internal 200 k

 pull-down resistor that is enabled by default. It can be disabled through programming.

Not used. Do not connect to this pin.

Not used. Do not connect to this pin.

Programmable GPIO pins. This pin becomes an output pin when it is used as

WLAN_HOST_WAKE/out-of-band signal.

Programmable GPIO pins

Programmable GPIO pins

Programmable GPIO pins

Programmable GPIO pins

Connect to an external inductor. See the reference schematic for details.

I

O

SR VBAT input power supply

CBUCK switching regulator output. See

Table 39 on page 135

for details of the inductor and capacitor required on this output.

LDO VBAT

LNLDO input

Output of low-noise LNLDO

Output of core LDO

Bluetooth PA power supply

Bluetooth IF block power supply

Bluetooth RF PLL power supply

Bluetooth RF power supply

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August 24, 2015 • 4343W-DS107-R

Single-Chip IEEE 802.11 b/g/n MAC/Baseband/Radio

Page 101

BROADCOM CONFIDENTIAL

BCM4343W Data Sheet Signal Descriptions

Signal Name

Power Supplies

WLRF_XTAL_VDD1P2

WLRF_PA_VDD

WCC_VDDIO

SYS_VDDIO

WLRF_VDD_1P35

VDDC

VOUT_3P3

Ground

BT_IF_VSS

BTFM_PLL_VSS

BT_VCO_VSS

FM_RF_VSS

PMU_AVSS

SR_PVSS

VSSC

WLRF_AFE_GND

WLRF_LNA_GND

WLRF_GENERAL_GND

WLRF_PA_GND

WLRF_VCO_GND

WLRF_XTAL_GND

Table 19: WLBGA Signal Descriptions (Cont.)

WLBGA Ball Type Description

M3

M1

F6

C5

M2

D3, G4

E7

H2

G2

H3

E3

B6

A7

D4, J5

H4

J2

K2

L2

L3

L4

I

I

I

I

I

I

I

I

I

I

I

I

I

I

I

O

I

I

I

I

XTAL oscillator supply

Power amplifier supply

VDDIO input supply. Connect to VDDIO.

VDDIO input supply. Connect to VDDIO.

LNLDO input supply

Core supply for WLAN and BT.

3.3V output supply. See the reference schematic for details.

1.2V Bluetooth IF block ground

Bluetooth/FM RF PLL ground

1.2V Bluetooth RF ground

FM RF ground

Quiet ground

Switcher-power ground

Core ground for WLAN and BT

AFE ground

2.4 GHz internal LNA ground

Miscellaneous RF ground

2.4 GHz PA ground

VCO/LO generator ground

XTAL ground

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®

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BROADCOM CONFIDENTIAL

BCM4343W Data Sheet Signal Descriptions

Table 20 provides the WLCSP package signal descriptions.

Table 20: WLCSP Signal Descriptions

Signal Name WLCSP Bump Type Description or Instruction

RF Signal Interface

WRF_RFIN_ELG_2G 61 I Connect to an external inductor. See the reference schematic for details.

2.4 GHz BT and WLAN RF input/output port WRF_RFIO_2G

SDIO Bus Interface

SDIO_CLK

SDIO_CMD

SDIO_DATA_0

SDIO_DATA_1

SDIO_DATA_2

SDIO_DATA_3

63

108

104

112

115

118

122

I

I/O

I/O

I/O

I/O

I/O

I/O

SDIO clock input

SDIO command line

SDIO data line 0

SDIO data line 1.

SDIO data line 2. Also used as a strapping

option (see Table 23 on page 110

).

SDIO data line 3

Note:

Per Section 6 of the SDIO specification, 10 to 100 kΩ pull-ups are required on the four DATA lines and the CMD line. This requirement must be met during all operating states by using external pull-up resistors or properly programming internal SDIO host pull-ups.

WLAN GPIO Interface

WRF_GPAIO_OUT 67 O Test pin. Not connected in normal operation.

Clocks

WRF_XTAL_XON

WRF_XTAL_XOP

CLK_REQ

LPO_IN

75

74

153

76 I

I

O

O

XTAL oscillator output

XTAL oscillator input

External system clock request—Used when the system clock is not provided by a dedicated crystal (for example, when a shared TCXO is used). Asserted to indicate to the host that the clock is required. Shared by BT, and WLAN.

External sleep clock input (32.768 kHz). If an external 32.768 kHz clock cannot be provided, pull this pin low. However, BLE will be always on and cannot go to deep sleep.

FM

FM_DAC_VOUT1

FM_DAC_VOUT2

FM_RFINMAIN

37

40

49 I

O

O

FM DAC output 1

FM DAC output 2

FM RF input

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BROADCOM CONFIDENTIAL

BCM4343W Data Sheet Signal Descriptions

Table 20: WLCSP Signal Descriptions (Cont.)

Signal Name WLCSP Bump Type Description or Instruction

Bluetooth PCM

BT_PCM_CLK or BT_I2S_CLK

BT_PCM_IN or BT_I2S_DI

BT_PCM_OUT or BT_I2S_DO

BT_PCMM_SYNC or BT_I2S_WS

3

20

19

17

Bluetooth GPIO

BT_AGPIO

BT_GPIO_2

BT_GPIO_3

BT_GPIO_4

BT_GPIO_5

BT_TM1

Bluetooth UART and Wake

52

13

5

8

10

4

I/O

I/O

I/O

I/O

I/O

I/O

Bluetooth analog GPIO

Bluetooth general purpose I/O

WPT_INTb to wireless charging PMU.

BSC_SDA to/from wireless charging PMU.

BSC_SCL from wireless charging PMU

ARM JTAG mode

BT_UART_CTS_N

BT_UART_RTS_N

BT_UART_RXD

BT_UART_TXD

22

7

1

12

I

I

O

O

UART clear-to-send. Active-low clear-to-send signal for the HCI UART interface.

UART request-to-send. Active-low request-tosend signal for the HCI UART interface.

UART serial input. Serial data input for the HCI

UART interface.

UART serial output. Serial data output for the

HCI UART interface.

BT_DEV_WAKE

BT_HOST_WAKE

6

11

I/O

I/O

DEV_WAKE or general-purpose

I/O signal

HOST_WAKE or general-purpose I/O signal

Note:

By default, the Bluetooth BT WAKE signals provide GPIO/WAKE functionality, and the UART pins provide UART functionality. Through software configuration, the PCM interface can also be routed over the

BT_WAKE/UART signals as follows:

• PCM_CLK on the UART_RTS_N pin

• PCM_OUT on the UART_CTS_N pin

• PCM_SYNC on the BT_HOST_WAKE pin

• PCM_IN on the BT_DEV_WAKE pin

In this case, the BT HCI transport included sleep signaling will operate using UART_RXD and UART_TXD; that is, using a 3-Wire UART Transport.

Bluetooth/FM I

2

S

BT_I2S_CLK or BT_PCM_CLK

BT_I2S_DI or BT_PCM_IN

15

23 I

I

I/O

O

I/O

I/O

PCM or I

2

S clock; can be master (output) or slave (input)

PCM or I

2

S data input sensing

PCM or I

2

S data output

PCM SYNC or I2S WS; can be master (output) or slave (input)

I

2

S or PCM clock; can be master (output) or slave (input)

I

2

S or PCM data input

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BROADCOM CONFIDENTIAL

BCM4343W Data Sheet Signal Descriptions

Signal Name

BT_I2S_DO or BT_PCM_OUT

BT_I2S_WS or BT_PCM_SYNC

Table 20: WLCSP Signal Descriptions (Cont.)

WLCSP Bump Type Description or Instruction

24

18

O

I/O

I

2

S or PCM data output

I

2

S WS or PCM SYNC; can be master (output) or slave (input)

Miscellaneous

WL_REG_ON 148 I

BT_REG_ON

WPT_3P3

WPT_1P8

GPIO_0

GPIO_1

GPIO_2

GPIO_3

GPIO_4

GPIO_5

GPIO_6

GPIO_7

GPIO_8

GPIO_9

GPIO_10

GPIO_11

GPIO_12

GPIO_13

GPIO_14

GPIO_15

PACKAGEOPTION_0

PACKAGEOPTION_1

PACKAGEOPTION_2

JTAG_SEL

149

146

145

100

101

97

98

91

94

89

87

84

82

83

81

80

119

105

109

110

113

116

117

I

I

I

I

I

N/A

N/A

I/O

I/O

I/O

I/O

I/O

I/O

I/O

I/O

I/O

I/O

I/O

I/O

I/O

I/O

I/O

I/O

Used by PMU to power up or power down the internal regulators used by the WLAN section.

Also, when deasserted, this pin holds the WLAN section in reset. This pin has an internal 200 k

 pull-down resistor that is enabled by default. It can be disabled through programming.

Used by PMU to power up or power down the internal regulators used by the Bluetooth/FM section. Also, when deasserted, this pin holds the Bluetooth/FM section in reset. This pin has an internal 200 k

 pull-down resistor that is enabled by default. It can be disabled through programming.

Not used. Do not connect to this pin.

Not used. Do not connect to this pin.

Programmable GPIO pin. This pin becomes an output pin when it is used as

WLAN_HOST_WAKE/out-of-band signal.

Programmable GPIO pin

Programmable GPIO pin

Programmable GPIO pin

Programmable GPIO pin

Programmable GPIO pin

Programmable GPIO pin

Programmable GPIO pin

Programmable GPIO pin

Programmable GPIO pin

Programmable GPIO pin

Programmable GPIO pin

Programmable GPIO pin

Programmable GPIO pin

Programmable GPIO pin

Programmable GPIO pin

VDDIO

Ground

Ground

JTAG select. Connect to ground.

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BROADCOM CONFIDENTIAL

BCM4343W Data Sheet Signal Descriptions

Signal Name

Integrated Voltage Regulators

SR_VDDBAT5V

SR_VLX

LDO_VDDBAT5V

LDO_VDD1P5

VOUT_LNLDO

VOUT_CLDO

Bluetooth Power Supplies

BT_IFVDD1P2

BT_LNAVDD1P2

BT_PAVDD2P5

BT_PLLVDD1P2

BT_VCOVDD1P2

BT_VDDC

Table 20: WLCSP Signal Descriptions (Cont.)

WLCSP Bump Type Description or Instruction

129, 130, 132

126, 127, 128

141, 147

133, 135

138

134, 136

51

54

53

59

57

14, 16, 26, 28,

31, 34

9

2

I

I

I

O

O

O

PWR

PWR

PWR

PWR

SR VBAT input power supply

CBUCK switching regulator output. See

Table 39 on page 135

for details of the inductor and capacitor required on this output.

LDO VBAT

LNLDO input

Output of low-noise LDO (LNLDO)

Output of core LDO

Bluetooth IF-block power supply

Bluetooth RF LNA power supply

Bluetooth RF PA power supply

PWR Bluetooth RF PLL power supply

PWR Bluetooth RF power supply

Bluetooth core power supply

PWR Bluetooth core power supply

PWR Bluetooth core power supply

BT_VDDC_ISO_1

BT_VDDC_ISO_2

Power Supplies

FM_DAC_AVDD

FM_IFDVDD1P2

FM_PLLDVDD1P2

FM_RFVDD1P2

FM_VCOVDD1P2

PLL_VDDC

SYS_VDDIO

VDDC

VOUT_3P3

VOUT_3P3_SENSE

WCC_VDDIO

WL_VDDM_ISO

WL_VDDP_ISO

WRF_XTAL_VDD1P2

WRF_PA_VDD3P3

WRF_PMU_VDD1P35

41

48

43

45

PWR

PWR

PWR

PWR

FM DAC power supply

FM IF power supply

FM PLL power supply

FM RF power supply

44

152

140

86, 93, 95, 107,

114

I

I

PWR FM VCO power supply

PWR Core PLL power supply

VDDIO input supply. Connect to VDDIO.

Core supply for WLAN and BT

139, 144 O 3.3V output supply. See the reference schematic for details.

Voltage sense pin for LDO 3.3V output

VDDIO input supply. Connect to VDDIO.

143

77, 79, 99, 103,

120, 137

150

I

O

96

73

70, 71

68

I

I

I

Test pin. Not connected in normal operation.

Test pin. Not connected in normal operation.

XTAL oscillator supply

Power amplifier supply

LNLDO input supply

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BROADCOM CONFIDENTIAL

BCM4343W Data Sheet

Signal Name

Ground

BT_DVSS

BT_LNAVSS

BT_PAVSS

BT_PLLVSS

BT_VCOVSS

FM_DAC_AVSS

FM_IFVSS

FM_PLLAVSS

FM_RFVSS

FM_VCOVSS

PLL_VSSC

PMU_AVSS

SR_PVSS

VSSC

WRF_AFE_GND

WRF_RX2G_GND

WRF_GENERAL_GND

WRF_PA_GND3P3

WRF_VCO_GND

WRF_XTAL_GND1P2

Table 20: WLCSP Signal Descriptions (Cont.)

WLCSP Bump Type Description or Instruction

58

38

47

39

50

55

35

56

46

42

151

131

123, 124

21, 25, 27, 29,

30, 32, 33, 36,

78, 85, 88, 90,

92, 102, 106,

111, 121, 125,

142

60

62

64

65, 69

66

72

I

I

I

I

I

I

GND Bluetooth digital ground

GND Bluetooth LNA ground

GND Bluetooth PA ground

GND Bluetooth PLL ground

GND Bluetooth VCO ground

GND FM DAC analog ground

GND FM IF-block ground

GND FM PLL analog ground

I

I

GND FM RF ground

GND FM VCO ground

I

GND PLL core ground

Quiet ground

Switcher-power ground

Core ground for WLAN and BT

AFE ground

2.4 GHz internal LNA ground

Miscellaneous RF ground

2.4 GHz PA ground

VCO/LO generator ground

XTAL ground

Signal Descriptions

Broadcom

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BROADCOM CONFIDENTIAL

BCM4343W Data Sheet WLAN GPIO Signals and Strapping Options

WLAN GPIO Signals and Strapping Options

The pins listed in Table 21 are sampled at power-on reset (POR) to determine the various operating modes.

Sampling occurs a few milliseconds after an internal POR or deassertion of the external POR. After the POR, each pin assumes the GPIO or alternative function specified in the signal descriptions table. Each strapping option pin has an internal pull-up (PU) or pull-down (PD) resistor that determines the default mode. To change the mode, connect an external PU resistor to VDDIO or a PD resistor to ground using a 10 kΩ resistor or less.

Note:

Refer to the reference board schematics for more information.

Table 21: GPIO Functions and Strapping Options

Pin Name WLBGA Pin # Default Function

SDIO_DATA_2 L7 1 WLAN host interface select

Description

This pin selects the WLAN host interface mode. The default is SDIO. For gSPI, pull this pin low.

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BCM4343W Data Sheet Chip Debug Options

Chip Debug Options

The chip can be accessed for debugging via the JTAG interface, multiplexed on the SDIO_DATA_0 through

SDIO_DATA_3 (and SDIO_CLK) I/O or the Bluetooth PCM I/O depending on the bootstrap state of GPIO_1 and

GPIO_2.

Table 22

shows the debug options of the device.

JTAG_SEL GPIO_2

0

0

0

0

0

0

1

1

GPIO_1

0

1

0

1

Table 22: Chip Debug Options

Function

SDIO I/O Pad

Function

Normal mode

JTAG over SDIO

SDIO

JTAG

JTAG over BT PCM SDIO

SWD over GPIO_1/

GPIO_2

SDIO

BT PCM I/O Pad

Function

BT PCM

BT PCM

JTAG

BT PCM

I/O States

The following notations are used in

Table 23 on page 110 :

• I: Input signal

• O: Output signal

• I/O: Input/Output signal

• PU = Pulled up

• PD = Pulled down

• NoPull = Neither pulled up nor pulled down

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BROADCOM CONFIDENTIAL

BCM4343W Data Sheet

I/O States

Table 23: I/O States a

Name

WL_REG_ON

BT_REG_ON

CLK_REQ

BT_HOST_

WAKE

BT_UART_CTS

BT_UART_RTS O

BT_UART_RXD I

BT_UART_TXD

SDIO_DATA_0

SDIO_DATA_1

SDIO_DATA_2

SDIO_DATA_3

SDIO_CMD

SDIO_CLK

BT_PCM_CLK

BT_PCM_IN

BT_PCM_OUT

I/O Keeper b

Active Mode

I N Input; PD (pull-down can be disabled)

Low Power State/Sleep

(All Power Present)

Power-Down c

WL_REG_ON = 0

BT_REG_ON = 0

Input; PD (pull-down can be disabled)

Input; PD (of 200K)

I N Input; PD (pull down can be disabled)

Input; PD (pull down can be disabled)

Input; PD (of 200K)

I/O Y

I/O

BT_DEV_WAKE I/O

I

O

I/O

I/O

I/O

I/O

I/O

I

I/O

I/O

I/O

BT_PCM_SYNC I/O

BT_I2S_WS I/O

BT_I2S_CLK I/O

Y

Y

Y

Y

Y

Y

N

N

N

N

N

N

Y

Y

Y

Y

Y

Y

Out-of-Reset;

(WL_REG_ON = 1;

BT_REG_ON =

Do Not Care)

Input; PD (200k)

Input; PD (200k)

(WL_REG_ON = 1

BT_REG_ON = 0)

VDDIOs Present

Input; PD (200k)

Input; PD (200k)

Open drain or push-pull

(programmable). Active high.

Open drain or push-pull

(programmable). Active high

I/O; PU, PD, NoPull

(programmable)

I/O; PU, PD, NoPull

(programmable)

Input; NoPull

I/O; PU, PD, NoPull

(programmable)

Input; PU, PD, NoPull

(programmable)

Input; NoPull

PD

High-Z, NoPull

High-Z, NoPull

High-Z, NoPull

Output; NoPull

Input; PU

Input; NoPull d

Input; NoPull d

Output; NoPull

Input; NoPull

Input; NoPull

Input; NoPull d d

High-Z, NoPull

High-Z, NoPull

Open drain, active high.

Open drain, active high.

Input, PD

Input, PD

Input; PU

Input; PU

Input; PU

Output; NoPull

SDIO MODE -> NoPull

SDIO MODE -> NoPull

SDIO MODE -> NoPull

Output; NoPull

SDIO MODE -> NoPull

SDIO MODE -> NoPull

SDIO MODE -> NoPull

High-Z, NoPull –

SDIO MODE -> NoPull SDIO MODE -> PU

SDIO MODE -> NoPull SDIO MODE -> PU

SDIO MODE -> NoPull SDIO MODE -> PU

Input; PU

SDIO MODE ->

NoPull

SDIO MODE ->

NoPull

SDIO MODE ->

NoPull

SDIO MODE -> NoPull

SDIO MODE -> NoPull

SDIO MODE -> NoPull

SDIO MODE -> NoPull

SDIO MODE -> NoPull SDIO MODE -> PU

SDIO MODE -> NoPull SDIO MODE -> PU

SDIO MODE ->

NoPull

SDIO MODE ->

NoPull

SDIO MODE -> NoPull SDIO MODE -> NoPull SDIO MODE -> NoPull SDIO MODE -> NoPull SDIO MODE ->

NoPull

Input; NoPull d

Input; NoPull d

High-Z, NoPull – Input, PD

High-Z, NoPull

High-Z, NoPull

Input, PD

Input, PD

Input; NoPull d

Input; NoPull d

High-Z, NoPull – Input, PD

Input; NoPull e

Input; NoPull e

Input; NoPull

Input; NoPull

e e

High-Z, NoPull

High-Z, NoPull

Input, PD

Input, PD

Out-of-Reset;

(WL_REG_ON = 0

BT_REG_ON = 1)

VDDIOs Present Power Rail

– –

Input; PD (200k)

Open drain, active high.

Output, Drive low WCC_VDDIO

Input, PD

Input, NoPull

Output, NoPull

Input, NoPull

Output, NoPull

Input; PU

Input; PU

Input; PU

Input; PU

Input; PU

Input

Input, PD

Input, PD

Input, PD

Input, PD

Input, PD

WCC_VDDIO

WCC_VDDIO

WCC_VDDIO

WCC_VDDIO

WCC_VDDIO

WCC_VDDIO

WCC_VDDIO

WCC_VDDIO

WCC_VDDIO

WCC_VDDIO

WCC_VDDIO

WCC_VDDIO

WCC_VDDIO

WCC_VDDIO

WCC_VDDIO

WCC_VDDIO

WCC_VDDIO

Output, Drive low WCC_VDDIO

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BROADCOM CONFIDENTIAL

BCM4343W Data Sheet

I/O States

Table 23: I/O States a

(Cont.)

Name I/O Keeper b

Active Mode

BT_I2S_DO I/O Y

Input; NoPull e

JTAG_SEL

GPIO_0

I

I/O

Y

Y

PD

TBD

Low Power State/Sleep

(All Power Present)

Power-Down c

WL_REG_ON = 0

BT_REG_ON = 0

Input; NoPull

e

High-Z, NoPull

PD

Active mode

High-Z, NoPull

High-Z, NoPull f

Out-of-Reset;

(WL_REG_ON = 1;

BT_REG_ON =

Do Not Care)

Input, PD

Input, SDIO OOB Int,

NoPull

Input, PD

(WL_REG_ON = 1

BT_REG_ON = 0)

VDDIOs Present

Input, PD

Out-of-Reset;

(WL_REG_ON = 0

BT_REG_ON = 1)

VDDIOs Present Power Rail

Input, PD WCC_VDDIO

PD

Active mode

Input, PD

Input, NoPull

WCC_VDDIO

WCC_VDDIO

GPIO_1

GPIO_2

GPIO_5

GPIO_6

GPIO_7

GPIO_8

GPIO_9

GPIO_10

I/O

I/O

GPIO_3 I/O

GPIO_4 I/O

I/O

I/O

I/O

I/O

I/O

I/O

Y

Y

Y

Y

N

Y

Y

Y

Y

Y

TBD

TBD

TBD

TBD

TBD

TBD

TBD

TBD

TBD

TBD

Active mode

Active mode

Active mode

Active mode

Active mode

Active mode

Active mode

Active mode

High-Z, NoPull f

High-Z, NoPull f

High-Z, NoPull f

High-Z, NoPull f

High-Z, NoPull f

High-Z, NoPull f

High-Z, NoPull f

High-Z, NoPull f

High-Z, NoPull f

High-Z, NoPull f

Input, GCI GPIO[7],

NoPull

Input, GCI GPIO[0],

PU

Input, GCI GPIO[1],

PU

Input, GCI GPIO[2],

PU

Input, GCI GPIO[3],

NoPull

Output, WLAN UART

RTS#, NoPull

Input, WLAN UART

CTS#, NoPull

Input, WLAN UART

RX, NoPull

Output, WLAN UART

TX, NoPull

Input, Low, NoPull

Active mode

Active mode

Active mode

Active mode

Active mode

Active mode

Active mode

Active mode

Active mode

Active mode

Input, Strap, PD WCC_VDDIO

Input, Strap, NoPull WCC_VDDIO

Input, PU

Input, PU

Input, PU

Input, NoPull

Input, NoPull

Input, NoPull

WCC_VDDIO

WCC_VDDIO

WCC_VDDIO

WCC_VDDIO

Output, NoPull, Low WCC_VDDIO

WCC_VDDIO

WCC_VDDIO

Output, NoPull, Low WCC_VDDIO

GPIO_11

GPIO_12

GPIO_13

GPIO_14

GPIO_15

I/O

I/O

I/O

I/O

I/O

Y

Y

Y

Y

Y

TBD

TBD

TBD

TBD

TBD

Active mode

Active mode

Active mode

Active mode

Active mode

High-Z, NoPull f

High-Z, NoPull f

High-Z, NoPull f

High-Z, NoPull f

High-Z, NoPull f

Input, GCI GPIO[6],

NoPull

Input, GCI GPIO[7],

NoPull

Input, PD

Input, PD

Active mode

Active mode

Active mode

Active mode

Active mode

Input, NoPull

Input, NoPull

Input, NoPull

Input, PD

Input, PD

WCC_VDDIO

WCC_VDDIO

WCC_VDDIO

WCC_VDDIO

WCC_VDDIO a. PU = pulled up, PD = pulled down.

b. N = pad has no keeper. Y = pad has a keeper. Keeper is always active except in the power-down state. If there is no keeper, and it is an input and there is

NoPull, then the pad should be driven to prevent leakage due to floating pad, for example, SDIO_CLK.

c. In the Power-down state (xx_REG_ON = 0): High-Z; NoPull => The pad is disabled because power is not supplied.

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BROADCOM CONFIDENTIAL

BCM4343W Data Sheet d. Depending on whether the PCM interface is enabled and the configuration is master or slave mode, it can be either an output or input.

e. Depending on whether the I

2

S interface is enabled and the configuration is master or slave mode, it can be either an output or input. f. The GPIO pull states for the active and low-power states are hardware defaults. They can all be subsequently programmed as a pull-up or pull-down.

I/O States

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Single-Chip IEEE 802.11 b/g/n MAC/Baseband/Radio

Page 112

BCM4343W Data Sheet DC Characteristics

Section 15: DC Characteristics

Note:

Values in this data sheet are design goals and are subject to change based on the results of device characterization.

Absolute Maximum Ratings

Caution!

The absolute maximum ratings in Table 24

indicate levels where permanent damage to the device can occur, even if these limits are exceeded for only a brief duration. Functional operation is not guaranteed under these conditions. Excluding VBAT, operation at the absolute maximum conditions for extended periods can adversely affect long-term reliability of the device.

Rating

DC supply for VBAT and PA driver supply

DC supply voltage for digital I/O

DC supply voltage for RF switch I/Os

DC input supply voltage for CLDO and LNLDO

DC supply voltage for RF analog

DC supply voltage for core

Maximum undershoot voltage for I/O b

Maximum overshoot voltage for I/O b

Maximum junction temperature

Table 24: Absolute Maximum Ratings

Symbol

VBAT

VDDIO

VDDIO_RF

VDDRF

VDDC

V undershoot

V overshoot

T j a. Continuous operation at 6.0V is supported.

b. Duration not to exceed 25% of the duty cycle.

Value

–0.5 to +6.0

a

–0.5 to 3.9

–0.5 to 3.9

–0.5 to 1.575

–0.5 to 1.32

–0.5 to 1.32

–0.5

VDDIO + 0.5

125

V

V

V

V

V

V

V

Unit

V

°C

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August 24, 2015 • 4343W-DS107-R

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BROADCOM CONFIDENTIAL

BCM4343W Data Sheet Environmental Ratings

Environmental Ratings

The environmental ratings are shown in

Table 25 .

Table 25: Environmental Ratings

Characteristic

Ambient temperature (T

Storage temperature

Relative humidity

A

)

Value

–30 to +70°C a

–40 to +125°C

Less than 60

Less than 85

Units

C

C

%

%

Conditions/Comments

Operation

Storage

Operation a. Functionality is guaranteed, but specifications require derating at extreme temperatures (see the specification tables for details).

Electrostatic Discharge Specifications

Extreme caution must be exercised to prevent electrostatic discharge (ESD) damage. Proper use of wrist and heel grounding straps to discharge static electricity is required when handling these devices. Always store unused material in its antistatic packaging.

Table 26: ESD Specifications

Pin Type Symbol Condition

ESD, Handling Reference:

NQY00083, Section 3.4,

Group D9, Table B

ESD_HAND_HBM

Machine Model (MM)

CDM

ESD_HAND_MM

Human Body Model Contact

Discharge per JEDEC EID/

JESD22-A114

Machine Model Contact

ESD_HAND_CDM Charged Device Model Contact

Discharge per JEDEC EIA/

JESD22-C101

ESD Rating

1000

30

300

V

V

Unit

V

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BROADCOM CONFIDENTIAL

BCM4343W Data Sheet Recommended Operating Conditions and DC Characteristics

Recommended Operating Conditions and DC Characteristics

Functional operation is not guaranteed outside the limits shown in Table 27 , and operation outside these limits

for extended periods can adversely affect long-term reliability of the device.

Element

Table 27: Recommended Operating Conditions and DC Characteristics

DC supply voltage for VBAT

DC supply voltage for core

DC supply voltage for RF blocks in chip

DC supply voltage for digital I/O

DC supply voltage for RF switch I/Os

External TSSI input

Internal POR threshold

SDIO Interface I/O Pins

For VDDIO_SD = 1.8V:

Input high voltage

Input low voltage

Output high voltage @ 2 mA

Output low voltage @ 2 mA

For VDDIO_SD = 3.3V:

Input high voltage

Input low voltage

Output high voltage @ 2 mA

Output low voltage @ 2 mA

Symbol

VBAT

Minimum

3.0

a

VDD

VDDRF

VDDIO,

VDDIO_SD

1.14

1.14

1.71

VDDIO_RF 3.13

TSSI 0.15

Vth_POR 0.4

VIH

VIL

VOH

VOL

VIH

VIL

VOH

VOL

1.27

1.40

Value

Typical Maximum

1.2

1.2

4.8

b

Unit

V

1.26

1.26

3.63 V

V

V

3.3

0.625 × VDDIO –

– –

0.75 × VDDIO –

3.46

0.95

0.7

0.58

0.45

0.25 ×

VDDIO

0.125 ×

VDDIO

V

V

V

V

V

V

V

V

V

V

V

Other Digital I/O Pins

For VDDIO = 1.8V:

Input high voltage

Input low voltage

VIH

VIL

VOH

VOL

0.65 × VDDIO –

VDDIO – 0.45 –

0.35 ×

VDDIO

0.45

V

V

V

V

Output high voltage @ 2 mA

Output low voltage @ 2 mA

For VDDIO = 3.3V:

Input high voltage

Input low voltage

Output high voltage @ 2 mA

Output low Voltage @ 2 mA

VIH

VIL

VOH

VOL

2.00

VDDIO – 0.4

0.80

0.40

V

V

V

V

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BROADCOM CONFIDENTIAL

BCM4343W Data Sheet Recommended Operating Conditions and DC Characteristics

Table 27: Recommended Operating Conditions and DC Characteristics (Cont.)

Element Symbol Minimum

Value

Typical Maximum Unit

RF Switch Control Output Pins c

For VDDIO_RF = 3.3V:

Output high voltage @ 2 mA

Output low voltage @ 2 mA

Input capacitance

VOH

VOL

C

IN

VDDIO – 0.4

0.40

5 a. The BCM4343W is functional across this range of voltages. However, optimal RF performance specified in the data sheet is guaranteed only for 3.2V < VBAT < 4.8V.

b. The maximum continuous voltage is 4.8V. Voltages up to 6.0V for up to 10 seconds, cumulative duration over the lifetime of the device are allowed. Voltages as high as 5.0V for up to 250 seconds, cumulative duration over the lifetime of the device are allowed.

c. Programmable 2 mA to 16 mA drive strength. Default is 10 mA.

V

V pF

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BCM4343W Data Sheet WLAN RF Specifications

Section 16: WLAN RF Specifications

The BCM4343W includes an integrated direct conversion radio that supports the 2.4 GHz band. This section describes the RF characteristics of the 2.4 GHz radio.

Note:

Values in this data sheet are design goals and may change based on device characterization results.

Unless otherwise stated, the specifications in this section apply when the operating conditions are within the limits specified in

Table 25: “Environmental Ratings,” on page 114

and Table 27: “Recommended Operating

Conditions and DC Characteristics,” on page 115 . Functional operation outside these limits is not guaranteed.

Typical values apply for the following conditions:

• VBAT = 3.6V.

• Ambient temperature +25°C.

Figure 43: RF Port Location

TX

C2

Chip

Port

Filter

BCM4343W

Antenna

Port

RX

10 pF

L1

4.7 nH

C1

10 pF

Note:

All specifications apply at the chip port unless otherwise specified.

2.4 GHz Band General RF Specifications

Item

TX/RX switch time

RX/TX switch time

Table 28: 2.4 GHz Band General RF Specifications

Condition

Including TX ramp down

Including TX ramp up

Minimum

Typical

5

2

Maximum Unit

µs

µs

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BCM4343W Data Sheet WLAN 2.4 GHz Receiver Performance Specifications

WLAN 2.4 GHz Receiver Performance Specifications

Note:

Unless otherwise specified, the specifications in

Table 29 are measured at the chip port (for the

location of the chip port, see

Figure 43 on page 117

).

Table 29: WLAN 2.4 GHz Receiver Performance Specifications

Parameter Condition/Notes Minimum Typical

Frequency range

RX sensitivity (8% PER for

1024 octet PSDU) a

1 Mbps DSSS

2 Mbps DSSS

5.5 Mbps DSSS

RX sensitivity (10% PER for

1000 octet PSDU) at WLAN

RF port a

11 Mbps DSSS

6 Mbps OFDM

9 Mbps OFDM

12 Mbps OFDM

RX sensitivity

(10% PER for 4096 octet

PSDU). Defined for default parameters: Mixed mode,

800 ns GI.

2400

–97.5

–93.5

–91.5

–88.5

–91.5

–90.5

–87.5

18 Mbps OFDM

24 Mbps OFDM

36 Mbps OFDM

48 Mbps OFDM

–85.5

–82.5

–80.5

–76.5

–87.5

–84.5

–82.5

–78.5

54 Mbps OFDM –75.5

–77.5

20 MHz channel spacing for all MCS rates (Mixed mode)

256-QAM, R = 5/6

256-QAM, R = 3/4

–67.5

–69.5

–69.5

–71.5

–99.5

–95.5

–93.5

–90.5

–93.5

–92.5

–89.5

MCS7

MCS6

MCS5

MCS4

MCS3

MCS2

MCS1

MCS0

–71.5

–73.5

–74.5

–79.5

–82.5

–84.5

–86.5

–90.5

–73.5

–75.5

–76.5

–81.5

–84.5

–86.5

–88.5

–92.5

Maximum Unit

2500

MHz dBm dBm dBm dBm dBm dBm dBm dBm dBm dBm dBm dBm dBm dBm dBm dBm dBm dBm dBm dBm dBm dBm

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BCM4343W Data Sheet WLAN 2.4 GHz Receiver Performance Specifications

Parameter

Blocking level for 3 dB RX sensitivity degradation

(without external filtering).

b

Maximum receive level

@ 2.4 GHz

Table 29: WLAN 2.4 GHz Receiver Performance Specifications (Cont.)

Condition/Notes Minimum Typical

704–716 MHz

777–787 MHz

776–794 MHz

815–830 MHz

816–824 MHz

816–849 MHz

824–849 MHz

824–849 MHz

LTE

LTE

CDMA2000

LTE

CDMA2000

LTE

WCDMA

CDMA2000

824–849 MHz

824–849 MHz

830–845 MHz

832–862 MHz

LTE

GSM850

LTE

LTE

880–915 MHz

880–915 MHz

WCDMA

LTE

880–915 MHz E-GSM

1710–1755 MHz WCDMA

1710–1755 MHz LTE

1710–1755 MHz CDMA2000

1710–1785 MHz WCDMA

1710–1785 MHz LTE

1710–1785 MHz GSM1800

1850–1910 MHz GSM1900

1850–1910 MHz CDMA2000

1850–1910 MHz WCDMA

1850–1910 MHz LTE

1850–1915 MHz LTE

1920–1980 MHz WCDMA

1920–1980 MHz CDMA2000

1920–1980 MHz LTE

2300–2400 MHz LTE

2500–2570 MHz LTE

2570–2620 MHz LTE

5G WLAN –

@ 1, 2 Mbps (8% PER, 1024 octets) –6

–12 @ 5.5, 11 Mbps (8% PER, 1024 octets)

@ 6–54 Mbps (10% PER, 1000 octets)

–15.5

–16

–17

–17.5

–19.5

–19.5

–44

–43

–34

–14.5

–14.5

–13

–14.5

–12.5

–11.5

–16

–13.5

>–4

–10

–12

–9

–13

–11.5

–8

–11.5

–11.5

–13

–13

–13.5

–12.5

–13.5

–11.5

–11.5

–12.5

Maximum Unit

– dBm dBm dBm dBm dBm dBm dBm dBm dBm dBm dBm dBm dBm dBm dBm dBm dBm dBm dBm dBm dBm dBm dBm dBm dBm dBm dBm dBm dBm dBm dBm dBm dBm dBm dBm

– dBm

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BCM4343W Data Sheet WLAN 2.4 GHz Receiver Performance Specifications

Table 29: WLAN 2.4 GHz Receiver Performance Specifications (Cont.)

Parameter Condition/Notes

Adjacent channel rejection-

DSSS.

(Difference between interfering and desired signal [25 MHz apart] at 8%

PER for 1024 octet PSDU with desired signal level as specified in Condition/

Notes.)

11 Mbps DSSS –70 dBm

Adjacent channel rejection-

OFDM.

(Difference between interfering and desired signal (25 MHz apart) at

10% PER for 1000 c

octet

PSDU with desired signal level as specified in

Condition/Notes.)

RCPI accuracy

Return loss d

6 Mbps OFDM

9 Mbps OFDM

12 Mbps OFDM

18 Mbps OFDM

24 Mbps OFDM

36 Mbps OFDM

48 Mbps OFDM

–79 dBm

–78 dBm

–76 dBm

–74 dBm

–71 dBm

–67 dBm

–63 dBm

54 Mbps OFDM –62 dBm

65 Mbps OFDM –61 dBm

Range –98 dBm to –75 dBm

Minimum Typical

35

8

4

0

–1

16

15

13

11

–2

–3

Range above –75 dBm –5

Zo = 50Ω across the dynamic range. 10

Maximum Unit

5

3 dB a. Optimal RF performance, as specified in this data sheet, is guaranteed only for temperatures between –10°C and 55°C.

b. The cellular standard listed for each band indicates the type of modulation used to generate the interfering signal in that band for the purpose of this test. It is not intended to indicate any specific usage of each band in any specific country.

c. For 65 Mbps, the size is 4096.

d. The minimum and maximum values shown have a 95% confidence level.

dB dB dB dB dB dB dB dB dB dB dB dB

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BCM4343W Data Sheet WLAN 2.4 GHz Transmitter Performance Specifications

WLAN 2.4 GHz Transmitter Performance Specifications

Note:

Unless otherwise specified, the specifications in

Table 29 are measured at the chip port (for the

location of the chip port, see

Figure 43 on page 117

).

Table 30: WLAN 2.4 GHz Transmitter Performance Specifications

Parameter Condition/Notes Minimum Typical Maximum Unit

Frequency range

Transmitted power in cellular and WLAN 5G bands (at 21 dBm, 90% duty cycle, 1 Mbps CCK).

a

– –

776–794 MHz CDMA2000 –

869–960 MHz CDMAOne, GSM850 –

1450–1495 MHz DAB

1570–1580 MHz GPS

1592–1610 MHz GLONASS

1710–1800 MHz DSC-1800-Uplink

1805–1880 MHz GSM1800

1850–1910 MHz GSM1900

1910–1930 MHz TDSCDMA, LTE

1930–1990 MHz GSM1900,

CDMAOne, WCDMA

2010–2075 MHz TDSCDMA

2110–2170 MHz WCDMA

2305–2370 MHz LTE Band 40

2370–2400 MHz LTE Band 40

2496–2530 MHz LTE Band 41

Harmonic level (at 21 dBm with 90% duty cycle, 1

Mbps CCK)

2530–2560 MHz LTE Band 41

2570–2690 MHz LTE Band 41

5000–5900 MHz WLAN 5G

4.8–5.0 GHz

7.2–7.5 GHz

2nd harmonic

3rd harmonic

9.6–10 GHz 4th harmonic –

–167.5 –

–163.5 –

–154.5 –

–152.5 –

–149.5 –

–145.5 –

–143.5 –

–140.5 –

–138.5 –

–139

–127.5 –

–124.5 –

–104.5 –

–81.5

–94.5

–120.5 –

–121.5 –

–109.5 –

–26.5

–23.5

–32.5

– dBm/Hz dBm/Hz dBm/Hz dBm/Hz dBm/Hz dBm/Hz dBm/Hz

– dBm/

MHz dBm/

MHz dBm/

MHz

MHz dBm/Hz dBm/Hz dBm/Hz dBm/Hz dBm/Hz dBm/Hz dBm/Hz dBm/Hz dBm/Hz dBm/Hz

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BCM4343W Data Sheet WLAN 2.4 GHz Transmitter Performance Specifications

Table 30: WLAN 2.4 GHz Transmitter Performance Specifications (Cont.)

Parameter Condition/Notes Minimum Typical Maximum Unit

TX power at the chip port for the highest power level setting at 25°C,

VBA = 3.6V, and spectral mask and EVM compliance b, c

IEEE 802.11b

(DSSS/CCK)

OFDM, BPSK

EVM Does Not Exceed

–9 dB

–8 dB

OFDM, QPSK –13 dB

OFDM, 16-QAM –19 dB

21

20.5

20.5

20.5

–25 dB 18 OFDM, 64-QAM

(R = 3/4)

OFDM, 64-QAM

(R = 5/6)

–27 dB 17.5

OFDM, 256-QAM

(R = 5/6)

–32 dB

15

9 TX power control dynamic range

Closed loop TX power variation at highest power level setting

Carrier suppression

Gain control step

Return loss

Load pull variation for output power, EVM, and

Adjacent Channel Power

Ratio (ACPR)

Across full temperature and voltage range. Applies across 5 to 21 dBm output power range.

Zo = 50

VSWR = 2:1.

EVM degradation

15

Output power variation –

ACPR-compliant power level

4

VSWR = 3:1.

EVM degradation –

Output power variation –

ACPR-compliant power level

0.25

6

3.5

±2

15

4

±3

15

±1.5

– dBm dBm dBm dBm dBm dBm dBm dB dB dB dB dBm a. The cellular standards listed indicate only typical usages of that band in some countries. Other standards may also be used within those bands.

b. TX power for channel 1 and channel 11 is specified separately by nonvolatile memory parameters to ensure band-edge compliance. c. Optimal RF performance, as specified in this data sheet, is guaranteed only for temperatures between –10°C and 55°C.

dBc dB dB dB dB dBm

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BCM4343W Data Sheet General Spurious Emissions Specifications

General Spurious Emissions Specifications

Table 31: General Spurious Emissions Specifications

Parameter

Frequency range –

Condition/Notes

General Spurious Emissions

TX emissions

RX/standby emissions

30 MHz < f < 1 GHz RBW = 100 kHz –

1 GHz < f < 12.75 GHz RBW = 1 MHz

1.8 GHz < f < 1.9 GHz RBW = 1 MHz

5.15 GHz < f < 5.3 GHz RBW = 1 MHz

30 MHz < f < 1 GHz

RBW = 100 kHz –

1 GHz < f < 12.75 GHz RBW = 1 MHz

1.8 GHz < f < 1.9 GHz RBW = 1 MHz

5.15 GHz < f < 5.3 GHz RBW = 1 MHz

Note:

The specifications in this table apply at the chip port.

Minimum Typical Maximum Unit

2400 – 2500 MHz

–99

–44

–68

–88

–99

–54

–88

–88

–96

–41

–65

–85

–96

–51

–85

–85 dBm dBm dBm dBm dBm dBm dBm dBm

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BCM4343W Data Sheet Bluetooth RF Specifications

Section 17: Bluetooth RF Specifications

Note:

Values in this data sheet are design goals and are subject to change based on the results of device characterization.

Unless otherwise stated, limit values apply for the conditions specified in

Table 25: “Environmental Ratings,” on page 114 and

Table 27: “Recommended Operating Conditions and DC Characteristics,” on page 115

. Typical values apply for the following conditions:

• VBAT = 3.6V.

• Ambient temperature +25°C.

Note:

All Bluetooth specifications apply at the chip port. For the location of the chip port, see Figure 43:

“RF Port Location,” on page 117 .

Table 32: Bluetooth Receiver RF Specifications

Parameter

Frequency range

RX sensitivity

Input IP3

Maximum input at antenna

Interference Performance a

Conditions Minimum Typical Maximum Unit

Note:

The specifications in this table are measured at the chip output port unless otherwise specified.

General

– 2402

GFSK, 0.1% BER, 1 Mbps –

/4–DQPSK, 0.01% BER,

2 Mbps

8–DPSK, 0.01% BER,

3 Mbps

–16

–94

–96

–90

2480

–20

MHz dBm dBm dBm dBm dBm

C/I co-channel GFSK, 0.1% BER

C/I 1 MHz adjacent channel GFSK, 0.1% BER

C/I 2 MHz adjacent channel GFSK, 0.1% BER

C/I

 3 MHz adjacent channel GFSK, 0.1% BER

C/I image channel GFSK, 0.1% BER

C/I 1 MHz adjacent to image channel

GFSK, 0.1% BER

C/I co-channel

/4–DQPSK, 0.1% BER

C/I 1 MHz adjacent channel

/4–DQPSK, 0.1% BER

C/I 2 MHz adjacent channel

/4–DQPSK, 0.1% BER

C/I

 3 MHz adjacent channel /4–DQPSK, 0.1% BER

11

0.0

–30

–40

–9

–20

13

0.0

–30

–40 dB dB dB dB dB dB dB dB dB dB

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BCM4343W Data Sheet Bluetooth RF Specifications

2310 MHz

2330 MHz

2350 MHz

2370 MHz

2510 MHz

2530 MHz

2550 MHz

2570 MHz

2310 MHz

2330 MHz

2350 MHz

2370 MHz

2510 MHz

2530 MHz

2550 MHz

2570 MHz

2310 MHz

2330 MHz

2350 MHz

Table 32: Bluetooth Receiver RF Specifications (Cont.)

Parameter Conditions

C/I image channel

C/I 1 MHz adjacent to image channel

C/I co-channel

C/I 1 MHz adjacent to image channel

/4–DQPSK, 0.1% BER

/4–DQPSK, 0.1% BER

8–DPSK, 0.1% BER

C/I 1 MHz adjacent channel 8–DPSK, 0.1% BER

C/I 2 MHz adjacent channel 8–DPSK, 0.1% BER

C/I

 3 MHz adjacent channel 8–DPSK, 0.1% BER

C/I Image channel 8–DPSK, 0.1% BER

8–DPSK, 0.1% BER

Minimum

Out-of-Band Blocking Performance (CW)

30–2000 MHz

2000–2399 MHz

2498–3000 MHz

3000 MHz–12.75 GHz

0.1% BER

0.1% BER

0.1% BER

0.1% BER

Out-of-Band Blocking Performance, Modulated Interferer (LTE)

GFSK (1 Mbps)

LTE band40 TDD 20M BW –

LTE band40 TDD 20M BW –

LTE band40 TDD 20M BW –

LTE band40 TDD 20M BW –

LTE band7 FDD 20M BW –

LTE band7 FDD 20M BW –

LTE band7 FDD 20M BW –

LTE band7 FDD 20M BW –

/4 DPSK (2 Mbps)

LTE band40 TDD 20M BW –

LTE band40 TDD 20M BW –

LTE band40 TDD 20M BW –

LTE band40 TDD 20M BW –

LTE band7 FDD 20M BW –

LTE band7 FDD 20M BW –

LTE band7 FDD 20M BW –

LTE band7 FDD 20M BW –

8DPSK (3 Mbps)

LTE band40 TDD 20M BW –

LTE band40 TDD 20M BW –

LTE band40 TDD 20M BW –

Typical

–10.0

–27

–27

–10.0

–20

–19

–20

–24

–24

–20

–20

–20

–20

–19

–20

–24

–24

–21

–21

–20

–20

–19

–20

Maximum Unit

–7

–20 dB dB

21

5.0

–25

–33

0.0

–13 dBm dBm dBm dBm dBm dBm dBm dBm dB dB dB dB dB dB dBm dBm dBm dBm dBm dBm dBm dBm dBm dBm dBm dBm dBm dBm dBm

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BCM4343W Data Sheet Bluetooth RF Specifications

Parameter

2370 MHz

2510 MHz

2530 MHz

2550 MHz

2570 MHz

LTE band40 TDD 20M BW –

LTE band7 FDD 20M BW

LTE band7 FDD 20M BW

LTE band7 FDD 20M BW

LTE band7 FDD 20M BW

Out-of-Band Blocking Performance, Modulated Interferer (Non-LTE)

–24

–24

–21

–20

–20

698–716 MHz

776–849 MHz

824–849 MHz

824–849 MHz

Table 32: Bluetooth Receiver RF Specifications (Cont.)

Conditions

WCDMA

WCDMA

GSM850

WCDMA

Minimum

GFSK (1 Mbps) a

Typical

–12

–12

–12

–12

Maximum Unit

– dBm dBm dBm dBm dBm

– dBm dBm dBm dBm

880–915 MHz

880–915 MHz

E-GSM

WCDMA

–11

–11

– dBm dBm

1710–1785 MHz

1710–1785 MHz

1850–1910 MHz

1850–1910 MHz

1880–1920 MHz

1920–1980 MHz

2010–2025 MHz

2500–2570 MHz

GSM1800

WCDMA

GSM1900

–16

–15

–18

–17

–18

–18

–18

–21

– dBm dBm dBm dBm dBm dBm dBm dBm

698–716 MHz

776–794 MHz

824–849 MHz

824–849 MHz

880–915 MHz

880–915 MHz

1710–1785 MHz

1710–1785 MHz

1850–1910 MHz

1850–1910 MHz

1880–1920 MHz

1920–1980 MHz

WCDMA

TD-SCDMA

WCDMA

TD–SCDMA

WCDMA

/4 DPSK (2 Mbps) a

WCDMA

WCDMA

GSM850

WCDMA

E-GSM

WCDMA

GSM1800

WCDMA

GSM1900

WCDMA

TD-SCDMA

WCDMA

–8

–8

–14

–14

–8

–8

–9

–9

–15

–14

–16

–15

– dBm dBm dBm dBm dBm dBm dBm dBm dBm dBm dBm dBm

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BCM4343W Data Sheet Bluetooth RF Specifications

Table 32: Bluetooth Receiver RF Specifications (Cont.)

Parameter

2010–2025 MHz

2500–2570 MHz

698–716 MHz

776–794 MHz

824–849 MHz

824–849 MHz

880–915 MHz

880–915 MHz

1710–1785 MHz

1710–1785 MHz

1850–1910 MHz

1850–1910 MHz

1880–1920 MHz

1920–1980 MHz

2010–2025 MHz

2500–2570 MHz

RX LO Leakage

2.4 GHz band

Spurious Emissions

Conditions

TD-SCDMA

WCDMA

WCDMA

WCDMA

GSM850

WCDMA

E-GSM

WCDMA

GSM1800

WCDMA

GSM1900

WCDMA

TD-SCDMA

WCDMA

TD-SCDMA

WCDMA

8DPSK (3 Mbps) a

Minimum Typical

–17

–21

–11

–11

–11

–12

–11

–11

–16

–15

–17

–17

–17

–17

–18

–21

–90.0

Maximum Unit

–80.0

dBm dBm dBm dBm dBm dBm dBm dBm dBm dBm dBm dBm dBm dBm dBm dBm dBm

30 MHz–1 GHz

1–12.75 GHz

869–894 MHz

925–960 MHz

1805–1880 MHz

1930–1990 MHz

2110–2170 MHz

–95

–70

–147

–147

–147

–147

–147

–62

–47

– a. The Bluetooth reference level for the required signal at the Bluetooth chip port is 3 dB higher than the typical sensitivity level.

dBm dBm dBm/Hz dBm/Hz dBm/Hz dBm/Hz dBm/Hz

Parameter

2500–2570 MHz

2300–2400 MHz

2570–2620 MHz

2545–2575 MHz

Table 33: LTE Specifications for Spurious Emissions

Conditions

Band 7

Band 40

Band 38

XGP Band

Typical

–147

–147

–147

–147

Unit

dBm/Hz dBm/Hz dBm/Hz dBm/Hz

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BCM4343W Data Sheet Bluetooth RF Specifications

Table 34: Bluetooth Transmitter RF Specifications a

Parameter Conditions Minimum Typical Maximum Unit

General

Frequency range

Basic rate (GFSK) TX power at Bluetooth

QPSK TX power at Bluetooth

8PSK TX power at Bluetooth

Power control step –

GFSK In-Band Spurious Emissions

–20 dBc BW –

EDR In-Band Spurious Emissions

1.0 MHz < |M – N| < 1.5 MHz

1.5 MHz < |M – N| < 2.5 MHz

|M – N|

 2.5 MHz b

M – N = the frequency range for which the spurious emission is measured relative to the transmit center frequency.

Out-of-Band Spurious Emissions

30 MHz to 1 GHz – –

2

2402

1 GHz to 12.75 GHz –

1.8 GHz to 1.9 GHz

5.15 GHz to 5.3 GHz

GPS Band Spurious Emissions

Spurious emissions –

Out-of-Band Noise Floor g

65–108 MHz

776–794 MHz

869–960 MHz

925–960 MHz

1570–1580 MHz

1805–1880 MHz

1930–1990 MHz

2110–2170 MHz

FM RX

CDMA2000 cdmaOne, GSM850

E-GSM

GPS

GSM1800 –

GSM1900, cdmaOne, WCDMA –

WCDMA –

12.0

8.0

8.0

4

0.93

–38

–31

–43

–103

2480

8

1

–20.0

–36.0 c,d

–30.0 d,e,f

–47.0

–47.0

MHz dBm dBm dBm dB

MHz

–26.0 dBc dBm

–40.0 dBm dBm dBm dBm dBm dBm

–147

–146

–146

–146

–146

–144

–143

–137

– a. Unless otherwise specified, the specifications in this table apply at the chip output port, and output power specifications are with the temperature correction algorithm and TSSI enabled.

b. Typically measured at an offset of ±3 MHz.

c. The maximum value represents the value required for Bluetooth qualification as defined in the v4.1 specification.

d. The spurious emissions during Idle mode are the same as specified in Table 34 on page 128

.

e. Specified at the Bluetooth antenna port.

f. Meets this specification using a front-end band-pass filter.

g. Transmitted power in cellular and FM bands at the Bluetooth antenna port. See Figure 43 on page 117 for

location of the port. dBm/Hz dBm/Hz dBm/Hz dBm/Hz dBm/Hz dBm/Hz dBm/Hz dBm/Hz

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BCM4343W Data Sheet Bluetooth RF Specifications

Parameter

2500–2570 MHz

2300–2400 MHz

2570–2620 MHz

2545–2575 MHz

Table 35: LTE Specifications for Out-of-Band Noise Floor

Conditions

Band 7

Band 40

Band 38

XGP Band

Typical

–130

–130

–130

–130

Unit

dBm/Hz dBm/Hz dBm/Hz dBm/Hz

Table 36: Local Oscillator Performance

Parameter Minimum Typical Maximum Unit

LO Performance

Lock time

Initial carrier frequency tolerance

Frequency Drift

72

±25

±75

DH1 packet

DH3 packet

DH5 packet

Drift rate

Frequency Deviation

±8

±8

±8

5

±25

±40

±40

20

00001111 sequence in payload a

10101010 sequence in payload b

Channel spacing

140

115

155

140

1

175

– a.

This pattern represents an average deviation in payload.

b.

Pattern represents the maximum deviation in payload for 99.9% of all frequency deviations.

s kHz kHz kHz kHz kHz/50 µs kHz kHz

MHz

Table 37: BLE RF Specifications

Parameter

Frequency range

Conditions

RX sense a

TX power b

Mod Char: delta f1 average –

Mod Char: delta f2 max

Mod Char: ratio c

– 2402

GFSK, 0.1% BER, 1 Mbps –

Minimum Typical

225

99.9

0.8

–97

8.5

255

0.95

Maximum Unit

2480

275

MHz dBm dBm kHz

%

– % a. The Bluetooth tester is set so that Dirty TX is on.

b. BLE TX power can be increased to compensate for front-end losses such as BPF, diplexer, switch, etc.). The output is capped at 12 dBm. The BLE TX power at the antenna port cannot exceed the 10 dBm specification limit.

c. At least 99.9% of all delta F2 max. frequency values recorded over 10 packets must be greater than 185 kHz.

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BROADCOM CONFIDENTIAL

BCM4343W Data Sheet FM Receiver Specifications

Section 18: FM Receiver Specifications

Note:

Values in this data sheet are design goals and are subject to change based on the results of device characterization.

Unless otherwise stated, limit values apply for the conditions specified in

Table 25: “Environmental Ratings,” on page 114 and

Table 27: “Recommended Operating Conditions and DC Characteristics,” on page 115

. Typical values apply for the following conditions:

• VBAT = 3.6V.

• Ambient temperature +25°C.

Table 38: FM Receiver Specifications

Parameter Conditions a

Minimum Typical Maximum Units

RF Parameters

Operating frequency b

Frequencies inclusive 65 –

Sensitivity c

FM only,

SNR ≥ 26 dB

Receiver adjacent channel selectivity c,d

Intermediate signalplus-noise to noise ratio (S + N)/N, stereo c

Measured for 30 dB SNR at audio output.

Signal of interest: 23 dBµV EMF (14.1 µV EMF).

At ±200 kHz.

At ±400 kHz.

Vin = 20 dBµV (10 µV EMF).

45

Intermodulation performance c,d

AM suppression, mono c

1

1.1

–5

51

62

53

Blocker level increased until desired at

30 dB SNR.

Wanted signal: 33 dBµV EMF (45 µV EMF)

Modulated interferer: At f

Wanted and + 4 MHz.

+ 400 kHz

CW interferer: At f

Wanted

+ 8 MHz.

+ 800 kHz and

– 55

Vin = 23 dBµV EMF (14.1 µV EMF).

AM at 400 Hz with m = 0.3.

No A-weighted or any other filtering applied.

40 –

108

MHz dBµV

EMF

µV EMF dBµV dB dB dB dBc dB

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BCM4343W Data Sheet FM Receiver Specifications

Parameter

RDS

RDS sensitivity e,f

Table 38: FM Receiver Specifications (Cont.)

Conditions a

Minimum Typical Maximum Units

RDS deviation = 1.2 kHz.

RDS deviation = 2 kHz.

RDS selectivity f

Wanted Signal: 33 dBµV EMF (45 µV EMF),

2 kHz RDS deviation.

Interferer: ∆f = 40 kHz, fmod = 1 kHz.

±200 kHz –

±300 kHz

±400 kHz

RF Input

RF input impedance –

Antenna tuning cap –

Maximum input level c

SNR > 26 dB.

RF conducted emissions

Local oscillator breakthrough measured on the reference port.

869–894 MHz, 925–960 MHz,

1805–1880 MHz, and 1930–1990 MHz.

GPS.

1.5

2.5

17

7.1

11

13

4.4

7

49

52

52

30

113

446

107

–55

–90 dBµV

EMF

µV EMF dBµV dBµV

EMF

µV EMF dBµV dB dB dB kΩ pF dBµV

EMF mV EMF dBµV dBm dBm

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BCM4343W Data Sheet FM Receiver Specifications

Table 38: FM Receiver Specifications (Cont.)

Parameter Conditions a

RF blocking levels at the FM antenna input with a 40 dB SNR

(assumes a 50Ω input and excludes spurs)

GSM850, E-GSM (standard); BW = 0.2 MHz.

824–849 MHz,

880–915 MHz.

GSM 850, E-GSM (edge); BW = 0.2 MHz.

824–849 MHz,

880–915 MHz.

GSM DCS 1800, PCS 1900 (standard, edge);

BW = 0.2 MHz.

1710–1785 MHz,

1850–1910 MHz.

WCDMA: II (I), III (IV,X); BW = 5 MHz.

1710–1785 MHz (1710–1755 MHz,

1710–1770 MHz),

1850–1980 MHz (1920–1980 MHz).

WCDMA: V (VI), VIII, XII, XIII, XIV;

BW = 5 MHz.

824–849 MHz (830–840 MHz),

880–915 MHz.

CDMA2000, CDMA One; BW = 1.25 MHz.

776–794 MHz,

824–849 MHz,

887–925 MHz.

CDMA2000, CDMA One; BW= 1.25 MHz.

1750–1780 MHz,

1850–1910 MHz,

1920–1980 MHz.

Bluetooth; BW = 1 MHz.

2402–2480 MHz.

LTE, Band 38, Band 40, XGP Band

WLAN-g/b; BW = 20 MHz.

2400–2483.5 MHz.

WLAN-a; BW = 20 MHz.

4915–5825 MHz.

Minimum Typical Maximum Units

– 7 – dBm

0

12

12

5

0

12

11

11

11

6

– dBm dBm dBm dBm dBm dBm dBm dBm dBm dBm

Tuning

Frequency step

Settling time

150

– kHz

µs

Search time

– 10

Single frequency switch in any direction to a frequency within the 88–108 MHz or

76–90 MHz bands. Time measured to within

5 kHz of the final frequency.

Total time for an automatic search to sweep from 88–108 MHz or 76–90 MHz

(or in the reverse direction) assuming no channels are found.

– – 8 sec

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BCM4343W Data Sheet FM Receiver Specifications

Table 38: FM Receiver Specifications (Cont.)

Parameter Conditions a

Minimum Typical Maximum Units

General Audio

Audio output level g

Maximum audio output level h

DAC audio output level

Conditions:

Vin = 66 dBµV EMF (2 mV EMF),

∆f = 22.5 kHz, fmod = 1 kHz,

∆f Pilot = 6.75 kHz

– Maximum DAC audio output level h

Audio DAC output level difference i

Left and right AC mute FM input signal fully muted with DAC enabled

Left and right hard mute

FM input signal fully muted with DAC disabled

–14.5

72

–1

60

80

333

–12.5

0

88

1

– dBFS dBFS mV

RMS mV

RMS dB dB dB

Soft mute attenuation and start level

Maximum signal plus noise-to-noise ratio

(S + N)/N, mono i

Maximum signal plus noise-to-noise ratio

(S + N)/N, stereo g

Total harmonic distortion, mono

Muting is performed dynamically, proportional to the desired FM input signal C/N. The

muting characteristic is fully programmable. See

Total harmonic distortion, stereo

Vin = 66 dBµV EMF(2 mV EMF):

∆f = 75 kHz, fmod = 400 Hz.

∆f = 75 kHz, fmod = 1 kHz.

∆f = 75 kHz, fmod = 3 kHz.

∆f = 100 kHz, fmod = 1 kHz.

Vin = 66 dBµV EMF (2 mV EMF),

∆f = 67.5 kHz, fmod = 1 kHz,

∆f pilot = 6.75 kHz, L = R

Range from 300 Hz to 15 kHz with respect to a 1 kHz tone.

Audio spurious products i

Audio bandwidth, upper (–3 dB point)

Vin = 66 dBµV EMF (2 mV EMF)

∆f = 8 kHz, for 50 µs

Audio bandwidth, lower (–3 dB point)

Audio in-band ripple 100 Hz to 13 kHz,

Vin = 66 dBµV EMF (2 mV EMF),

∆f = 8 kHz, for 50 µs.

Deemphasis time constant tolerance

With respect to 50 and 75 µs.

15

–0.5

“Audio Features” on page 77

69

64

0.8

0.8

0.8

1.0

1.5

–60

20

0.5

±5

.

dB dB

%

%

%

%

% dBc kHz

Hz dB

%

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BCM4343W Data Sheet FM Receiver Specifications

Table 38: FM Receiver Specifications (Cont.)

Parameter

RSSI range

Conditions a

With 1 dB resolution and ±5 dB accuracy at room temperature.

Minimum Typical Maximum Units

3 – 83 dBµV

EMF

1.41

–3

1.41E+4 µV EMF

77 dBµV

Stereo Decoder

Stereo channel separation

Mono stereo blend and switching

Pilot suppression

Forced Stereo mode

Vin = 66 dBµV EMF (2 mV EMF),

∆f = 67.5 kHz, fmod = 1 kHz,

∆f Pilot = 6.75 kHz,

R = 0, L = 1

– 44 – dB

Dynamically proportional to the desired FM input signal C/N. The blending and

switching characteristics are fully programmable. See “Audio Features” on page 77 .

Vin = 66 dBµV EMF (2 mV EMF),

∆f = 75 kHz, fmod = 1 kHz.

46 – – dB

Pause Detection

Audio level at which a pause is detected

Relative to 1-kHz tone, ∆f = 22.5 kHz.

4 values in 3 dB steps

4 values

–21

20

–12

40

– dB ms Audio pause duration a. The following conditions are applied to all relevant tests unless otherwise indicated: Preemphasis and deemphasis of 50 µs, R = L for mono, BAF = 300 Hz to 15 kHz, A-weighted filtering applied.

b. Contact your Broadcom representative for applications operating between 65–76 MHz.

c. Signal of interest:

∆ f = 22.5 kHz, fmod = 1 kHz.

d. Interferer:

∆ f = 22.5 kHz, fmod = 1 kHz.

e. RDS sensitivity numbers are for 87.5–108 MHz only.

f. Vin =

∆ f = 32 kHz, fmod = 1 kHz,

∆ f pilot = 7.5 kHz, and with an interferer for 95% of blocks decoded with no errors after correction, over a sample of 5000 blocks.

g. Vin = 66 dBµV EMF (2 mV EMF),

∆ f = 22.5 kHz, fmod = 1 kHz,

∆ f pilot = 6.75 kHz.

h. Vin = 66 dBµV EMF (2 mV EMF), i. Vin = 66 dBµV EMF (2 mV EMF),

∆ f = 100 kHz, fmod = 1 kHz,

∆ f pilot = 6.75 kHz.

∆ f = 22.5 kHz, fmod = 1 kHz.

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BROADCOM CONFIDENTIAL

BCM4343W Data Sheet Internal Regulator Electrical Specifications

Section 19: Internal Regulator Electrical

Specifications

Note:

Values in this data sheet are design goals and are subject to change based on device characterization results.

Functional operation is not guaranteed outside of the specification limits provided in this section.

Core Buck Switching Regulator

Table 39: Core Buck Switching Regulator (CBUCK) Specifications

Specification

Input supply voltage (DC)

Notes

DC voltage range inclusive of disturbances.

CCM, load > 100 mA VBAT = 3.6V.

Min.

2.4

Typ.

3.6

4

Max.

4.8

– a

Units

V

MHz PWM mode switching frequency

PWM output current

Output current limit

Output voltage range

PWM output voltage

DC accuracy

PWM ripple voltage, static

PWM mode peak efficiency

PFM mode efficiency

Start-up time from power down

External inductor

External output capacitor

– –

Programmable, 30 mV steps.

Default = 1.35V.

1.2

Includes load and line regulation.

Forced PWM mode.

–4

Measure with 20 MHz bandwidth limit.

Static load, max. ripple based on

VBAT = 3.6V, Vout = 1.35V,

Fsw = 4 MHz, 2.2 μH inductor L > 1.05 μH,

Cap + Board total-ESR < 20 mΩ,

C out

> 1.9 μF, ESL<200 pH

Peak efficiency at 200 mA load, inductor

DCR = 200 mΩ, VBAT = 3.6V, VOUT =

1.35V

10 mA load current, inductor

DCR = 200 mΩ, VBAT = 3.6V, VOUT =

1.35V

VDDIO already ON and steady.

Time from REG_ON rising edge to CLDO reaching 1.2V

0603 size, 2.2 μH ±20%,

DCR = 0.2Ω ± 25%

Ceramic, X5R, 0402,

ESR <30 mΩ at 4 MHz, 4.7 μF ±20%, 10V

2.0

b

– 370

1400 –

1.35

7

85

77

400

2.2

4.7

1.5

4

20

500

10 c mA mA

V

% mVpp

%

%

µs

µH

µF

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BCM4343W Data Sheet Core Buck Switching Regulator

Table 39: Core Buck Switching Regulator (CBUCK) Specifications (Cont.)

Specification

External input capacitor

Notes

For SR_VDDBATP5V pin, ceramic, X5R, 0603,

ESR < 30 mΩ at 4 MHz, ±4.7 μF ±20%,

10V

0 to 4.3V

Min.

0.67

b

Typ.

4.7

Max.

Units

µF

Input supply voltage ramp-up time

40 – – µs a. The maximum continuous voltage is 4.8V. Voltages up to 6.0V for up to 10 seconds, cumulative duration, over the lifetime of the device are allowed. Voltages as high as 5.0V for up to 250 seconds, cumulative duration, over the lifetime of the device are allowed. b. Minimum capacitor value refers to the residual capacitor value after taking into account the part-to-part tolerance, DC-bias, temperature, and aging.

c. Total capacitance includes those connected at the far end of the active load.

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BROADCOM CONFIDENTIAL

BCM4343W Data Sheet 3.3V LDO (LDO3P3)

3.3V LDO (LDO3P3)

Table 40: LDO3P3 Specifications

Specification

Input supply voltage, V

Output current

Nominal output voltage, V

Dropout voltage

PSRR o

Output voltage DC accuracy

Quiescent current

Line regulation

Load regulation

LDO turn-on time in

External output capacitor, C

External input capacitor o

Notes Min.

Typ.

Max.

Units

Min. = V o

+ 0.2V = 3.5V dropout voltage requirement must be met under maximum load for performance specifications.

Default = 3.3V.

3.1

3.6

0.001 –

– 3.3

At max. load.

Includes line/load regulation.

–5

No load –

V in

from (V o

+ 0.2V) to 4.8V, max. load – load from 1 mA to 450 mA

V in

V o

≥ V o

+ 0.2V,

= 3.3V, C o

= 4.7 µF,

Max. load, 100 Hz to 100 kHz

20

– Chip already powered up.

Ceramic, X5R, 0402,

(ESR: 5 mΩ–240 mΩ), ± 10%, 10V

For SR_VDDBATA5V pin (shared with band gap) Ceramic, X5R, 0402,

(ESR: 30m-200 mΩ), ± 10%, 10V.

Not needed if sharing VBAT capacitor

4.7 µF with SR_VDDBATP5V.

1.0

– b

66

160

4.7

4.7

4.8

450

200

+5

85

3.5

0.3

– a

250

5.64

V

µs

µF

µF mA

V mV

%

µA mV/V mV/mA dB a. The maximum continuous voltage is 4.8V. Voltages up to 6.0V for up to 10 seconds, cumulative duration, over the lifetime of the device are allowed. Voltages as high as 5.0V for up to 250 seconds, cumulative duration, over the lifetime of the device are allowed. b. Minimum capacitor value refers to the residual capacitor value after taking into account the part-to-part tolerance, DC-bias, temperature, and aging.

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BCM4343W Data Sheet CLDO

CLDO

Table 41: CLDO Specifications

Specification

Input supply voltage, V

Output current

Output voltage, V

Dropout voltage o in

Output voltage DC accuracy

Quiescent current

Line regulation

Load regulation

Leakage current

PSRR

Start-up time of PMU

LDO turn-on time

External output capacitor, C o

External input capacitor

Notes

Min. = 1.2 + 0.15V = 1.35V dropout voltage requirement must be met under maximum load.

Programmable in 10 mV steps.

Default = 1.2.V

At max. load

Includes line/load regulation

No load

200 mA load

V in

from (V o

+ 0.15V) to 1.5V, maximum load

Load from 1 mA to 300 mA

Power down

Bypass mode

@1 kHz, Vin ≥ 1.35V, C o

= 4.7 µF

VDDIO up and steady. Time from the

REG_ON rising edge to the CLDO reaching 1.2V.

LDO turn-on time when rest of the chip is up.

Total ESR: 5 mΩ–240 mΩ

Min. Typ. Max. Units

1.3

0.2

0.95

–4

20

1.35

1.2

13

1.5

200

1.26

V mA

V

150 mV

1.24

– 5

+4

%

µA mA mV/V

0.02

0.05

mV/mA

5

1

140

20

3

700

180

µA

µA dB

µs

µs

Only use an external input capacitor at the VDD_LDO pin if it is not supplied from CBUCK output.

1.1

a

2.2

1

2.2

a. Minimum capacitor value refers to the residual capacitor value after taking into account the part-to-part tolerance, DC-bias, temperature, and aging.

µF

µF

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BCM4343W Data Sheet LNLDO

LNLDO

Table 42: LNLDO Specifications

Specification Notes

Input supply voltage, Vin Min. V

IN

= V

O

(where V

O

+ 0.15V = 1.35V

= 1.2V) dropout voltage requirement must be met under maximum load.

Output current

Output voltage, V o

Programmable in 25 mV steps.

Default = 1.2V

At maximum load Dropout voltage

Output voltage DC accuracy Includes line/load regulation

Quiescent current No load

Line regulation

Load regulation

Leakage current

Output noise

Max. load

V in

from (V o

+ 0.15V) to 1.5V,

200 mA load

Load from 1 mA to 200 mA:

V in

≥ (V o

+ 0.12V)

Power-down, junction temp. = 85°C

@30 kHz, 60–150 mA load C o

= 2.2 µF

@100 kHz, 60–150 mA load C o

= 2.2 µF

Min.

Typ.

Max.

Units

1.3

0.1

1.1

–4

1.35

1.2

10

970

– 0.025

– 5

– – 60

20 –

LDO turn-on time LDO turn-on time when rest of chip is up

External output capacitor, C o

Total ESR (trace/capacitor):

5 mΩ–240 mΩ

External input capacitor Only use an external input capacitor at the

VDD_LDO pin if it is not supplied from

CBUCK output.

Total ESR (trace/capacitor): 30 mΩ–200 mΩ

0.5

a

– 1

140

2.2

1.5

150

1.275

150

+4

12

990

5

0.045

20

35

180

4.7

2.2

V mA

V mV

%

µA

µA mV/V mV/mA

µA nV/ Hz dB

µs

µF

µF a. Minimum capacitor value refers to the residual capacitor value after taking into account the part-to-part tolerance,

DC-bias, temperature, and aging.

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BCM4343W Data Sheet System Power Consumption

Section 20: System Power Consumption

Note:

The values in this data sheet are design goals and are subject to change based on device characterization.Unless otherwise stated, these values apply for the conditions specified in

Table 27: “Recommended Operating Conditions and DC Characteristics,” on page 115

.

WLAN Current Consumption

Table 43

shows typical currents consumed by the BCM4343W’s WLAN section. All values shown are with the

Bluetooth core in Reset mode with Bluetooth and FM off.

2.4 GHz Mode

Table 43: 2.4 GHz Mode WLAN Power Consumption

VBAT = 3.6V, VDDIO = 1.8V, TA 25°C

Mode Rate VBAT (mA) Vio

(µA)

Sleep Modes

Leakage (OFF)

Sleep (idle, unassociated) a

Sleep (idle, associated, inter-beacons) b

IEEE Power Save PM1 DTIM1 (Avg.) c

IEEE Power Save PM1 DTIM3 (Avg.) d

IEEE Power Save PM2 DTIM1 (Avg.) c

IEEE Power Save PM2 DTIM3 (Avg.) d

Active Modes

Rx Listen Mode e

Rx Active (at –50dBm RSSI) f

N/A

N/A

Rate 1

Rate 1

Rate 1

Rate 1

Rate 1

N/A

0.0035

0.0058

0.0058

1.05

0.35

1.05

0.35

37

0.08

80

80

74

86

74

86

12

Tx f

Rate 1

Rate 11

Rate 54

39

40

40

Rate MCS7

Rate 1 @ 20 dBm

Rate 11 @ 18 dBm

Rate 54 @ 15 dBm

41

320

290

260

Rate MCS7 @ 15 dBm 260

12

12

12

12

15

15

15

15 a. Device is initialized in Sleep mode, but not associated.

b. Device is associated, and then enters Power Save mode (idle between beacons).

c. Beacon interval = 100 ms; beacon duration = 1 ms @ 1 Mbps (Integrated Sleep + wakeup + beacon).

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BCM4343W Data Sheet Bluetooth and FM Current Consumption d. Beacon interval = 300 ms; beacon duration = 1 ms @ 1 Mbps (Integrated Sleep + wakeup + beacon).

e. Carrier sense (CCA) when no carrier present.

f. Tx output power is measured on the chip-out side; duty cycle =100%. Tx Active mode is measured in Packet

Engine mode (pseudo-random data)

Bluetooth and FM Current Consumption

The Bluetooth, BLE, and FM current consumption measurements are shown in

Table 44 .

Note:

• The WLAN core is in reset (WLAN_REG_ON = low) for all measurements provided in

Table 44 .

• For FM measurements, the Bluetooth core is in Sleep mode.

• The BT current consumption numbers are measured based on GFSK TX output power = 10 dBm.

Table 44: Bluetooth BLE and FM Current Consumption

Operating Mode

Sleep

Standard 1.28s Inquiry Scan

500 ms Sniff Master

DM1/DH1 Master

DM3/DH3 Master

DM5/DH5 Master

3DH5/3DH5 Master

SCO HV3 Master

FMRX Analog Audio only a

FMRX I

2

S Audio a

FMRX I

2

S Audio + RDS a

VBAT (VBAT = 3.6V)

Typical

8

8

FMRX Analog Audio + RDS a

BLE Scan b

8.6

187

BLE Adv. – Unconnectable 1.00 sec 93

BLE Connected 1 sec 71

6

193

305

23.3

28.4

29.1

25.1

11.8

8.6

VDDIO (VDDIO = 1.8V)

Typical

150

162

172

164

163

163 a. In Mono/Stereo blend mode.

b. No devices present. A 1.28 second interval with a scan window of 11.25 ms. mA

µA

µA

µA

Units

µA

µA

µA mA mA mA mA mA mA mA mA

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BROADCOM CONFIDENTIAL

BCM4343W Data Sheet Interface Timing and AC Characteristics

Section 21: Interface Timing and AC

Characteristics

Note:

Values in this data sheet are design goals and are subject to change based on the results of device characterization.

Unless otherwise stated, the specifications in this section apply when the operating conditions are within the

limits specified in Table 25 on page 114

and Table 27 on page 115 . Functional operation outside of these limits

is not guaranteed.

SDIO Default Mode Timing

SDIO default mode timing is shown by the combination of Figure 44

and Table 45 on page 143

.

Figure 44: SDIO Bus Timing (Default Mode)

f

PP t

WL t

WH

SDIO_CLK t

THL t

ISU t

TLH t

IH

Input

Output t

ODLY

(max) t

ODLY

(min)

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BROADCOM CONFIDENTIAL

BCM4343W Data Sheet SDIO Default Mode Timing

Table 45: SDIO Bus Timing a

Parameters (Default Mode)

Parameter Symbol Minimum Typical

SDIO CLK (All values are referred to minimum VIH and maximum VIL b

)

Frequency—Data Transfer mode

Frequency—Identification mode

Clock low time

Clock high time

Clock rise time

Clock fall time

Inputs: CMD, DAT (referenced to CLK)

fPP fOD tWL tWH tTLH tTHL

0

0

10

10

Input setup time

Input hold time tISU tIH

5

5

Outputs: CMD, DAT (referenced to CLK)

Output delay time—Data Transfer mode

Output delay time—Identification mode tODLY tODLY a. Timing is based on CL

 40 pF load on command and data.

b. min(Vih) = 0.7 × VDDIO and max(Vil) = 0.2 × VDDIO.

0

0

Maximum Unit

10

10

25

400

14

50 ns ns ns ns ns ns ns

MHz kHz ns

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BROADCOM CONFIDENTIAL

BCM4343W Data Sheet SDIO High-Speed Mode Timing

SDIO High-Speed Mode Timing

SDIO high-speed mode timing is shown by the combination of

Figure 45 and Table 46 .

Figure 45: SDIO Bus Timing (High-Speed Mode)

f

PP t

WL t

WH

50% VDD

SDIO_CLK t

THL t

ISU t

TLH t

IH

Input

Output t

ODLY t

OH

Parameter

Table 46: SDIO Bus Timing a

Parameters (High-Speed Mode)

Symbol Minimum Typical

SDIO CLK (all values are referred to minimum VIH and maximum VIL b

)

Frequency – Data Transfer Mode

Frequency – Identification Mode

Clock low time

Clock high time

Clock rise time

Clock fall time

Inputs: CMD, DAT (referenced to CLK)

fPP fOD tWL tWH tTLH tTHL

0

0

7

7

Input setup time

Input hold time tISU tIH

6

2

Outputs: CMD, DAT (referenced to CLK)

Output delay time – Data Transfer Mode

Output hold time

Total system capacitance (each line) tODLY tOH

CL a. Timing is based on CL

 40 pF load on command and data.

b. min(Vih) = 0.7 × VDDIO and max(Vil) = 0.2 × VDDIO.

2.5

Maximum Unit

50

400

3

3

14

40 ns ns ns ns pF ns ns ns

MHz kHz ns

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BROADCOM CONFIDENTIAL

BCM4343W Data Sheet gSPI Signal Timing

gSPI Signal Timing

The gSPI device always samples data on the rising edge of the clock.

Figure 46: gSPI Timing

T4

T1

T5

T2

SPI_CLK

T6 T7

SPI_DIN

T8 T9

SPI_DOUT

(falling edge)

T3

Table 47: gSPI Timing Parameters

Parameter Symbol Minimum Maximum Units Note

Clock period

Clock high/low

Clock rise/fall time T4/T5

Input setup time

Input hold time

Output setup time

Output hold time

T1

T2/T3

T6

T7

T8

T9

20.8

– ns

(0.45 × T1) – T4 (0.55 × T1) – T4 ns

5.0

5.0

5.0

5.0

2.5

– ns ns ns ns ns

F max

= 50 MHz

Setup time, SIMO valid to

SPI_CLK active edge

Hold time, SPI_CLK active edge to SIMO invalid

Setup time, SOMI valid before

SPI_CLK rising

Hold time, SPI_CLK active edge to SOMI invalid

CSX fall to 1st rising edge

CSX to clock a

Clock to CSX c

7.86

– ns ns Last falling edge to CSX high a. SPI_CSx remains active for entire duration of gSPI read/write/write_read transaction (that is, overall words for multiple word transaction)

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BROADCOM CONFIDENTIAL

BCM4343W Data Sheet

JTAG Timing

Signal Name

TCK

TDI

TMS

TDO

JTAG_TRST

Table 48: JTAG Timing Characteristics

Period

125 ns

250 ns

Output

Maximum

100 ns

Output

Minimum

0 ns

Setup

20 ns

20 ns

JTAG Timing

Hold

0 ns

0 ns

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BROADCOM CONFIDENTIAL

BCM4343W Data Sheet Power-Up Sequence and Timing

Section 22: Power-Up Sequence and

Timing

Sequencing of Reset and Regulator Control Signals

The BCM4343W has two signals that allow the host to control power consumption by enabling or disabling the

Bluetooth, WLAN, and internal regulator blocks. These signals are described below. Additionally, diagrams are

provided to indicate proper sequencing of the signals for various operational states (see Figure 47 on page 148

through Figure 50 on page 149

). The timing values indicated are minimum required values; longer delays are also acceptable.

Note:

• The WL_REG_ON and BT_REG_ON signals are OR’ed in the BCM4343W. The diagrams show both signals going high at the same time (as would be the case if both REG signals were controlled by a single host GPIO). If two independent host GPIOs are used (one for WL_REG_ON and one for BT_REG_ON), then only one of the two signals needs to be high to enable the BCM4343W regulators.

• The reset requirements for the Bluetooth core are also applicable for the FM core. In other words, if FM is to be used, then the Bluetooth core must be enabled.

• The BCM4343W has an internal power-on reset (POR) circuit. The device will be held in reset for a maximum of 110 ms after VDDC and VDDIO have both passed the POR threshold (see

Table 27: “Recommended Operating Conditions and DC Characteristics,” on page 115 ). Wait at

least 150 ms after VDDC and VDDIO are available before initiating SDIO accesses.

• VBAT and VDDIO should not rise faster than 40 µs. VBAT should be up before or at the same time as VDDIO. VDDIO should not be present first or be held high before VBAT is high.

Description of Control Signals

WL_REG_ON: Used by the PMU to power up the WLAN section. It is also OR-gated with the BT_REG_ON input to control the internal BCM4343W regulators. When this pin is high, the regulators are enabled and the WLAN section is out of reset. When this pin is low the WLAN section is in reset. If both the

BT_REG_ON and WL_REG_ON pins are low, the regulators are disabled.

BT_REG_ON: Used by the PMU (OR-gated with WL_REG_ON) to power up the internal BCM4343W regulators. If both the BT_REG_ON and WL_REG_ON pins are low, the regulators are disabled. When this pin is low and WL_REG_ON is high, the BT section is in reset.

Note:

For both the WL_REG_ON and BT_REG_ON pins, there should be at least a 10 ms time delay between consecutive toggles (where both signals have been driven low). This is to allow time for the

CBUCK regulator to discharge. If this delay is not followed, then there may be a VDDIO in-rush current on the order of 36 mA during the next PMU cold start.

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BCM4343W Data Sheet Sequencing of Reset and Regulator Control Signals

Control Signal Timing Diagrams

Figure 47: WLAN = ON, Bluetooth = ON

32.678 kHz

Sleep Clock

VBAT

VDDIO

90% of VH

~ 2 Sleep cycles

WL_REG_ON

BT_REG_ON

Figure 48: WLAN = OFF, Bluetooth = OFF

32.678 kHz

Sleep Clock

VBAT

VDDIO

WL_REG_ON

BT_REG_ON

Figure 49: WLAN = ON, Bluetooth = OFF

32.678 kHz

Sleep Clock

VBAT

VDDIO

WL_REG_ON

BT_REG_ON

90% of VH

~ 2 Sleep cycles

Broadcom

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BCM4343W Data Sheet

32.678 kHz

Sleep Clock

VBAT

VDDIO

WL_REG_ON

BT_REG_ON

90% of VH

~ 2 Sleep cycles

Sequencing of Reset and Regulator Control Signals

Figure 50: WLAN = OFF, Bluetooth = ON

Broadcom

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BROADCOM CONFIDENTIAL

BCM4343W Data Sheet Package Information

Section 23: Package Information

Package Thermal Characteristics

Table 49: Package Thermal Characteristics a

Characteristic

JA

(°C/W)

Value in Still Air

53.11

JB

(°C/W)

13.14

JC

(°C/W)

6.36

JT

(°C/W)

JB

(°C/W)

Maximum Junction Temperature T j

(°C) b

Maximum Power Dissipation (W)

0.04

14.21

125

1.2

a. No heat sink, TA = 70°C. This is an estimate based on a 4-layer PCB that conforms to EIA/JESD51–7

(101.6 mm x 114.3 mm x 1.6 mm) and P = 1.2W continuous dissipation. b. Absolute junction temperature limits maintained through active thermal monitoring and dynamic TX duty cycle limiting.

Junction Temperature Estimation and PSI Versus Theta

jc

Package thermal characterization parameter PSI-JT ( temperature (T this is

J

JT

) yields a better estimation of actual junction

) versus using the junction-to-case thermal resistance parameter Theta-J

C

(

 applications, some of the power is dissipated through the bottom and sides of the package.

JC

). The reason for

JC

assumes that all the power is dissipated through the top surface of the package case. In actual

JT

takes into account power dissipated through the top, bottom, and sides of the package. The equation for calculating the device junction temperature is as follows:

T

J

= T

T

+ P



JT

Where:

• T

J

= junction temperature at steady-state condition, °C

• T

T

= package case top center temperature at steady-state condition, °C

• P = device power dissipation, Watts

JT

= package thermal characteristics (no airflow), °C/W

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BCM4343W Data Sheet Mechanical Information

Section 24: Mechanical Information

Figure 51 shows the mechanical drawing for the BCM4343W WLBGA package.

Figure 51: 74-Ball WLBGA Mechanical Information

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BCM4343W Data Sheet Mechanical Information

Figure 52

shows the mechanical drawing for the BCM4343W WLCSP package. Figure 53 shows the WLCSP

keep-out areas.

Figure 52: 153-Bump WLCSP Mechanical Information

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BCM4343W Data Sheet

Note:

No top-layer metal is allowed in the keep-out areas.

Mechanical Information

Note:

A DXF file containing WLBGA keep-outs can be imported into a layout program. Contact your

Broadcom FAE for more information.

Figure 53: WLCSP Package Keep-Out Areas—Top View with the Bumps Facing Down

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BCM4343W Data Sheet Mechanical Information

Figure 54: WLBGA Package Keep-Out Areas—Top View with the Bumps Facing Down

Broadcom

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BROADCOM CONFIDENTIAL

BCM4343W Data Sheet Ordering Information

Section 25: Ordering Information

Table 50: Part Ordering Information

Part Number a

Package Description

BCM4343WKUBG 74-ball WLBGA halogen-free package

(4.87 mm x 2.87 mm, 0.40 pitch)

2.4 GHz single-band WLAN

IEEE 802.11n + BT 4.1 +

FMRX + Wireless Charging

BCM4343WKWBG 153-bump WLCSP 2.4 GHz single-band WLAN

IEEE 802.11n + BT 4.1 +

FMRX + Wireless Charging a. Add “T” to the end of the part number to specify “Tape and Reel.”

Operating

Ambient

Temperature

–30°C to +70°C

–30°C to +70°C

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BROADCOM CONFIDENTIAL

BCM4343W Data Sheet

Broadcom

®

Corporation reserves the right to make changes without further notice to any products or data herein to improve reliability, function, or design.

Information furnished by Broadcom Corporation is believed to be accurate and reliable. However,

Broadcom Corporation does not assume any liability arising out of the application or use of this information, nor the application or use of any product or circuit described herein, neither does it convey any license under its patent rights nor the rights of others.

Broadcom Corporation

5300 California Avenue

Irvine, CA 92617

© 2015 by BROADCOM CORPORATION. All rights reserved.

4343W-DS107-R August 24, 2015

Phone: 949-926-5000

Fax: 949-926-5203

E-mail: [email protected]

Web: www.broadcom.com

®

Mouser Electronics

Authorized Distributor

Click to View Pricing, Inventory, Delivery & Lifecycle Information:

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:

BCM4343W1KUBGT BCM4343WKUBGT

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