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User Guide

PC1-GROOVE •

CompactPCI

® PlusIO

Core™ i7 Processor High Performance CPU Card

Suitable for Classic CompactPCI© and PICMG 2.30 CompactPCI® PlusIO Systems

Document No. 5713 • Edition 27 • 1 October 2015

PC1-GROOVE

User Guide • PC1-GROOVE • Core

TM

i7 CompactPCI

®

CPU Board

Contents

About this Manual . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4

Edition History . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4

Related Documents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5

Nomenclature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5

Trade Marks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5

Legal Disclaimer - Liability Exclusion . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5

Standards . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6

PC1-GROOVE Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8

Feature Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8

Block Diagram PC1-GROOVE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13

Top View Component Assembly . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17

Strapping Headers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19

Connectors & Sockets . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19

Front Panel Elements . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19

Microprocessor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20

Thermal Considerations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21

Main Memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22

Graphics Subsystem . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23

LAN Subsystem . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23

Serial ATA Interface (SATA) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24

PCI Express Interface (PCIe) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24

Universal Serial Bus (USB) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25

Real-Time Clock . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25

LPC Super-I/O Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25

SPI Flash . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25

Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26

Watchdog . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29

PG (Power Good) LED . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30

HD (Hard Disk Activity) LED . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30

GP (General Purpose) LED . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30

EB (Ethernet Backplane) LED . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31

Hot Swap Detection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31

Power Supply Status (DEG#, FAL#) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31

Mezzanine Side Board Options . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32

CompactPCI

®

PlusIO Option . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40

Installing and Replacing Components . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47

Before You Begin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47

Installing the Board . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48

Removing the Board . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49

EMC Recommendations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50

Installing or Replacing the Memory Module . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51

Replacement of the Battery . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51

Technical Reference . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52

Local PCI Devices . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52

Local SMB Devices . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53

Hardware Monitor LM87 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53

GPIO Usage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54

GPIO Usage PCH . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54

© EKF -2- ekf.com

User Guide • PC1-GROOVE • Core

TM

i7 CompactPCI

®

CPU Board

Configuration Jumpers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56

Configuration Switches PCI Express Link Width (DSW1) . . . . . . . . . . . . . . . . . . . . 56

Loading UEFI BIOS Setup Defaults (P-GP) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57

Manufacturer Mode Jumper (P-MFG) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57

Reset Jumper PCH RTC Core (P-RTC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58

Connectors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59

Front Panel Connectors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59

DisplayPort Monitor Connector J-DP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60

Video Monitor Connector J-VGA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63

USB Connectors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64

Ethernet Connectors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64

Internal Connectors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65

Expansion Interface Header J-EXP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65

High Speed Expansion Connector J-HSE . . . . . . . . . . . . . . . . . . . . . . . . . . 66

PCI Express Expansion Header J-PCIE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68

SDVO2 Expansion Header J-SDVO2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69

Front Panel Handle Microswitch Header P-FPH . . . . . . . . . . . . . . . . . . . . . 70

PLD Programming Header P-ISP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71

Processor Debug Header XDP1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71

CompactPCI J1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72

CompactPCI J2 (PlusIO) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73

Appendix . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75

Mechanical Drawings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75

© EKF -3- ekf.com

User Guide • PC1-GROOVE • Core

TM

i7 CompactPCI

®

CPU Board

About this Manual

This manual describes the technical aspects of the PC1-GROOVE, required for installation and system integration. It is intended for the experienced user only.

Edition History

9

10

11

25

26

27

28

18

19

20

21

22

23

24

12

13

14

15

16

17

4

5

2

3

6

7

8

Ed.

Contents/Changes

1 User Manual PC1-GROOVE, english, initial edition (Text #5713, File: pc1_uge.wpd)

Added photos, added relational links

Part # change USB connector

Added to table Feature Summary: +3.3V V(I/O) option

Changed default setting of switch DSW1

Changes due to Revision 1

Added description of the front panel handle integrated switch

Added photos showing how to force system shutdown using the front panel handle integrated switch

Added photos 'Small Systems' and 'Rugged Systems'

BIOS usage of GP LED - document link added

Added photos 'Hybrid Systems', added photos of mezzanine modules and side cards, added photos of rear I/O module

Added factory settings of switch DSW1 for different side boards

Added Power Requirements

Added PCI-ID of JMB362 Rev. C Controller

Table Feature Summary: Added Clock Rates of CPU Graphics Core

Added photo PC1-C47 assembly

Added photo C47-MSATA mezzanine module

Added photos front view

Added photos DisplayPort adapter, front panel handle micro switch

Added photos DisplayPort cable adapter DVI & VGA

Added photos low profile mezzanine modules exploded view

Added MTBF value to table Feature Summary

Added recommendation regarding DsiplayPort cable (pin 20 issue)

Added information regarding selection of suitable intermediate PCB for mezzanine connector SDVO2

Added photos PC1-PCS assemblyies

Clarified resetting of UEFI BIOS settings to factory defaults

Added photos C48-M2 low profile mezzanine storage module

Table 'Feature Summary' - added RTOS support

Author gn jj jj jj gn jj jj jj jj gn jj jj gn gn jj jj jj jj jj gn jj jj gn gn gn jj jj jj

Date

2010-03-22

20 May 2010

19 October 2010

5 November 2010

2011-02-24

2011-03-31

2011-04-13

12 May 2011

13 May 2011

18 May 2011

24 May 2011

2011-06-09

2011-06-17

2011-06-30

26 July 2011

16 August 2011

22 August 2011

25 August 2011

2 September 2011

19 January 2012

28 March 2012

2012-05-04

5 March 2013

3 April 2013

29 April 2013

2015-01-16

21 May 2015

1 October 2015

© EKF -4- ekf.com

User Guide • PC1-GROOVE • Core

TM

i7 CompactPCI

®

CPU Board

Related Documents

Related Information PC1-GROOVE

PC1-GROOVE Home

PC1-GROOVE Ordering Information www.ekf.com/p/pc1/pc1.html

www.ekf.com/p/pc1/pc1_pie.pdf

Nomenclature

Signal names used herein with an attached '#' designate active low lines.

Trade Marks

Some terms used herein are property of their respective owners, e.g.

<

<

<

< Pentium, Celeron, Core™ i7, Arrandale, Ibex Peak-M, Calpella Platform, iAMT, Hanksville,

Hartwell: ® Intel

CompactPCI : ® PICMG

Windows XP, Windows 7, Windows 8: ® Microsoft

EKF, ekf system: ® EKF

EKF does not claim this list to be complete.

Legal Disclaimer - Liability Exclusion

This manual has been edited as carefully as possible. We apologize for any potential mistake.

Information provided herein is designated exclusively to the proficient user (system integrator, engineer). EKF can accept no responsibility for any damage caused by the use of this manual.

© EKF -5- ekf.com

User Guide • PC1-GROOVE • Core

TM

i7 CompactPCI

®

CPU Board

Standards

Theme Document Title

CompactFlash CF+ and CompactFlash Specification Revision 3.0

CompactPCI CompactPCI Specification, PICMG 2.0 R3.0, Oct. 1,

1999

CompactPCI

PlusIO

CompactPCI

Serial

DisplayPort

CompactPCI PlusIO Specification, PICMG 2.30

R1.0, November 11, 2009

Under developement

DVI

Ethernet

HD Audio

PCI Express

PCI Local Bus

SATA

TPM

USB

VESA DisplayPort Standard Version 1.1

March 19, 2007

Digital Visual Interface Rev. 1.0

Digital Display Working Group

IEEE Std 802.3, 2000 Edition

High Definition Audio Specification Rev.1.0

PCI Express

®

Base Specification 1.1

PCI 2.2/2.3/3.0 Standards PCI SIG

Serial ATA 2.5/2.6 Specification

Trusted Platform Module 1.2

Universal Serial Bus Specification

Origin www.compactflash.org

www.picmg.org

www.picmg.org

www.picmg.org

www.vesa.org

www.ddwg.org

standards.ieee.org

www.intel.com/design/chipsets/hdaudio.htm

www.pcisig.com

www.pcisig.com

www.sata-io.org

https://www.trustedcomputinggroup.org

www.usb.org

© EKF -6- ekf.com

User Guide • PC1-GROOVE • Core

TM

i7 CompactPCI

®

CPU Board

8HP Assembly PC1-GROOVE - PCS-BALLET - C48-M2

© EKF -7- ekf.com

User Guide • PC1-GROOVE • Core

TM

i7 CompactPCI

®

CPU Board

PC1-GROOVE Features

Feature Summary

Form Factor

Processor

Chipset

Memory (RAM)

Video

Feature Summary PC1-GROOVE

Single size CompactPCI® style Eurocard (160x100mm

2

), front panel width 4HP (20.3mm)

Designed for Intel® Core™ i7 processors (codename Arrandale) with integrated graphics and memory controller

<

Maximum junction temperature of processor core 105°C (graphics core 100°C)

<

Enhanced Intel® Speedstep® Technology

<

Intel® Turbo Boost Technology

<

Dual Core Multiprocessing

<

Intel® Virtualization Technology (VT)

< Intel® 64 Architecture

< Refresh of 5th generation graphics core with 12 Execution Units

Available processors:

< Core™ i7-610E • 2.53GHz • 4MB L3 Cache • 35W TDP • 500/766MHz Graphics

<

Core™ i7-620LE • 2.00GHz • 4MB L3 Cache • 25W TDP • 266/566MHz Graphics

<

Core™ i7-660UE • 1.33GHz • 4MB L3 Cache • 18W TDP • 166/500MHz Graphics

<

Core™ i7-620UE • 1.06GHz • 4MB L3 Cache • 18W TDP • 166/500MHz Graphics

Mobile Intel® 5 Series Chipset (Codename Ibex Peak):

QM57 Express Chipset Platform Controller Hub (PCH) with

<

8 PCI Express root ports at 2.5Gbps

<

6 x SATA 3Gbps

<

Intel® Matrix Storage Technology (RAID 0, 1, 5, 10)

<

High Definition Audio

<

14 x USB (2 EHCI controllers)

<

Integrated GbE MAC

< iAMT

< Unified SPI Flash support

< 3 Digital Display Interfaces (DisplayPort, SDVO, HDMI)

< VGA interface with integrated 350MHz RAMDAC (resolution up to 2048x1536x24@75Hz)

< Maximum memory capacity of 8GB DDR3 up to 1066MHz

< 512Mb, 1Gb, 2Gb, [4Gb] technologies for x8 and x16 devices

< Channel 0 populated as directly soldered DDR3 devices (Memory Down)

<

Channel 1 provided as 204-pin SODIMM socket to carry DDR3 module PC3-8500

<

Dual channel symmetric – memory addresses interleaved for increased performance

(SODIMM module size must match Memory Down size)

<

Intel® Flex Memory Technology (dual channel interleaved mode with unequal memory population) - memory sizes maybe unequal in both the channels

<

Dual channel asymmetric – memory sizes may differ, including no memory module populated in the SODIMM socket (single-channel)

<

Concurrently operation of two monitors with resolutions up to 2560x1536 pixel 16M colours @60Hz refresh rate (DisplayPort), up to 1600 x 1200 pixel 16M colours @60Hz

(DVI-D on side boards like CCO-CONCERT)

<

Dual screen capable (one display attached to the front panel DisplayPort connector, the other to a digital display interface provided by a side board)

< Front panel option: D-Sub (female HD15) VGA connector available, replaces DisplayPort connector

< Mezzanine option: Secondary DVI-D connector at mezzanine card front panel allows for dual digital flat panel operation, suitable mezzanine modules e.g. CCH-MARIACHI, CCI-

RAP, CCJ-RHYTHM, CCO-CONCERT. Side boards providing a 2nd DisplayPort are projected

© EKF -8- ekf.com

USB

Ethernet

SATA

PATA (IDE)

PCI Express

Mezzanine

Side Board

I/O

J2

CompactPCI®

PlusIO

User Guide • PC1-GROOVE • Core

TM

i7 CompactPCI

®

CPU Board

Feature Summary PC1-GROOVE

<

All ports over-current protected, data transfer rate of up to 480Mbps, conforming to

USB2.0

<

2 x USB type A connector (front panel)

<

4 x USB ports J2/P2 PlusIO

< 2 x USB ports via J-EXP expansion interface option (in use by several mezzanine side boards)

< 4 x USB ports via J-HSE (e.g. C40-SCFA mezzanine storage module)

< Dual EHCI controllers provided by PCH QM57

< Total of four 10/100/1000Mbps Gigabit Ethernet controllers, two accessible via RJ45 jacks from the front panel, two fed to J2/P2 PlusIO

< ETH1 equipped with Intel® 82577LM PHY (codename Hanksville), serves also as AMT out of band communication path (MAC provided by PCH QM57), Jumbo Frame support up to

4KB

<

ETH2...4 equipped with Intel® 82574L GbE controller (codename Hartwell), connected to local PCIe lanes, supports 9KB jumbo packets, TimeSync Offload compliant with 802.1as

specification

<

Total of eight 3Gbps SATA channels available

<

Quad-channel Serial ATA 3Gbps available for J2/P2 PluIO (derived from PCH QM57)

<

Intel® Matrix Storage Technology MST (Raid 1, 0, Matrix Raid)

<

Secondary on-board PCIe to SATA controller JMB362, dual channel SATA RAID, available via J-HSE expansion connector (plus 2 SATA channels in addition from PCH QM57)

<

Additional PCIe to SATA controller on mezzanine side boards e.g. CCI-RAP,

CCK-MARIMBA, CCL-CAPELLA, CCO-CONCERT

<

Option mezzanine module attached to J-HSE expansion connector

<

C40-SCFA mezzanine module available with on-board SATA to PATA bridge and

CompactFlash socket

<

12-Port PCIe Gen 2 switch provides 4 lanes to PCIe high-speed connector J-PCIE for CCJ-

RHYTHM and other mezzanine expansion cards, and 4 lanes to J2/P2 PlusIO interface

<

Possible configurations on each interface 1 Link x 4 Lanes, 4 Links x 1 Lane

<

J-EXP Legacy expansion interface connector LPC/USB/Audio (SIO, USB, HD Audio)

<

J-HSE High-speed expansion interface connector (4 x SATA, 4 x USB)

<

J-PCIE PCI Express 4-lane high-speed expansion connector

<

J-SDVO2 additional digital graphics port high-speed expansion connector

< Suitable mezzanine companion side boards available, e.g.:

< CCI-RAP: 2 x PCI Express Mini Card sockets (WLAN, GSM, Wimax, Intel® Turbo

Memory), options secondary DVI-D, IEEE 1394 (FireWire), USB SSD, C20-SATA mezzanine storage module (accommodates up to 2 SATA hard disk drives 2.5-inch

RAID capable)

<

CCJ-RHYTHM: CompactPCI Express system slot controller function by on board 6-port

24-lane PCIe switch, options DVI-D, IEEE 1394 (FireWire)

<

CCK-MARIMBA: PMC/XMC module carrier, option C20-SATA mezzanine storage module

<

CCL-CAPELLA: Up to 4 Gigabit Ethernet ports, options IEEE 1394 (FireWire), USB SSD,

C20-SATA mezzanine module

< CCO-CONCERT: Audio analog/digital, option secondary DVI-D

< C23-SATA: PCIe to 2 x SATA 1 x PATA controller

< C40-SCFA: SATA to PATA bridge & CompactFlash header, option USB SSD, 4HP envelope maintained

<

C42-SATA: 1.8-inch SATA Solid State Drive (SSD), 4HP envelope maintained

< Suitable PlusIO backplanes available (e.g. Schroff)

< High-Speed UHM connector

<

4 x PCIe

<

4 x Serial ATA (SATA)

<

2 x Gbit Ethernet

<

4 x USB

© EKF -9- ekf.com

J1

CompactPCI®

CompactPCI®

Express

Platform

Management

Secure

Computing

Firmware

Drivers

(All Major OS)

Drivers

(All Major OS)

Real-Time OS

BSP & Driver

Thermal

Conditions

Environmental

Conditions

EC Regulations

User Guide • PC1-GROOVE • Core

TM

i7 CompactPCI

®

CPU Board

Feature Summary PC1-GROOVE

<

PCH QM57 integrated 32-bit PCI bridge, 33MHz 133MBps CompactPCI master

<

Additional PCI arbiter in PLD for fully figured 8-slot CompactPCI backplane

<

+5V V(I/O) default configuration (PCI pull-up resistors 1k - blue coding key on J1)

<

+3.3V V(I/O) on request (PCI pull-up resistors 2.7k - yellow coding key on J1)

<

PC1-GROOVE can be configured as CompactPCI Express System Board (system slot controller) by optionally available mezzanine expansion card CCJ-RHYTHM

<

CPCIe 4-Link configuration (4-lanes each), for up to 4 CPCIe peripheral slots type 1 and/or type 2 on a passive CPCIe backplane

< Suitable also for hybrid CPCI/CPCIe systems/backplanes (e.g. Schroff)

<

Option AMT 6.0 Intel® Active Management Technology (iAMT)

<

ARM core based Manageability Engine (ME) in the PCH QM57

< Independent manageability firmware, stored in SPI Flash

<

Option Trusted Platform Module TPM 1.2 according to Trusted Computing Group specifications

<

Available as discrete controller on several mezzanine boards e.g. CCH/CCI/CCJ

< Discrete crypto engine silicon brands Infineon or Atmel at users choice

<

Phoenix UEFI with EKF enhancements for embedded systems

<

SPI Flash memory 2 x 16/32/64 Mb

< Updates available from website ekf.com

<

Intel® graphics driver, Intel® embedded graphics driver

<

Intel® networking driver

<

Intel® Matrix Storage Manager software

< JMicron SATA driver

<

Intel® graphics driver, Intel® embedded graphics driver

<

Intel® networking driver

< Intel® Matrix Storage Manager software

< JMicron SATA driver

<

QNX 6.5.0 available

<

VxWorks and others on request

<

Operating temperature: 0°C ... +70°C (extended temperature range on request)

<

Storage temperature: -40°C ... +85°C, max. gradient 5°C/min

<

Humidity 5% ... 95% RH non condensing

< Altitude -300m ... +3000m

< Shock 15g 0.33ms, 6g 6ms

< Vibration 1g 5-2000Hz

<

EN55022, EN55024, EN60950-1 (UL60950-1/IEC60950-1)

< 2002/95/EC (RoHS)

© EKF -10- ekf.com

User Guide • PC1-GROOVE • Core

TM

i7 CompactPCI

®

CPU Board

MTBF

Typical Power

Requirements

1)

Intel®

SpeedStep®

Frequency Modes

LFM: Low

Frequency Mode,

HFM: High

Frequency Mode

2) Add per Ethernet port 0.2/0.6A

(link only/active)

@1Gbps

Performance

Rating

Measured with

PCMark2005 under Windows®

XP, 2 x 2GB

DDR3 1066

Feature Summary PC1-GROOVE

126 x 10

3

h (14 years) @ 50° C

+3.3V +0.17V/-0.1V

Board

PC1-62-GROOVE

Board

PC1-6-GROOVE

PC1-4-GROOVE

PC1-2-GROOVE

MaxPower

LFM/HFM

1)

6.1/6.4A

2)

S3: 250mA

S4: 80mA

S5: 80mA

Processor i7-610E i7-620LE i7-620UE

Win7 Idle

LFM/HFM

1)

2.9/2.9A

2)

+5V +0.25V/-0.15V

MaxPower

LFM/HFM

1)

2.3/5.8A

Win7 Idle

LFM/HFM

1)

0.1/0.1A

S3: <10mA

S4: <10mA

S5: <10mA

CPU/MEM Score

TBD

TBD

TBD

Table items are subject to technical changes

© EKF -11- ekf.com

User Guide • PC1-GROOVE • Core

TM

i7 CompactPCI

®

CPU Board

PC1-GROOVE (Option DisplayPort) and C41-CFast Module

© EKF -12- ekf.com

User Guide • PC1-GROOVE • Core

TM

i7 CompactPCI

®

CPU Board

Block Diagram PC1-GROOVE

Sheet 3

PCIe

Switch

PCIe 0.1 - 0.4

Arrandale+ECC

2 Cores - 4 Threads

Low Power

CPU

Core™ i7

EKF

Document

#1167

DDR3

800/1067

Dual Channel i7-610E 2.53/3.2GHz SV i7-620LE 2.0/2.8GHz LV i7-660UE 1.33/2.4GHz ULV i7-620UE 1.06/2.13GHz ULV

FDI

Sheet 2

PCH

DMI2

Intel® Low Power Platform Calpella+ECC

Simplified Block Diagram

PC1-GROOVE

Sheet 1 - CPU & RAM

© EKF -13- ekf.com

User Guide • PC1-GROOVE • Core

TM

i7 CompactPCI

®

CPU Board

GbE

1

GbE

2

FDI

Sheet 1

CPU

DMI2

Sheet 3

J-SDVO2

Front Panel

Stuffing Alternates either DisplayPort or VGA

USB

CRT

SDVO/DDPB

DDPD

Sheet 3

J-EXP J-HSE

Sheet 4

J2

Hanksville

82577

LM

USB

USB

SATA

PCIe 1.6

82574

IT

PCIe 1.7

rfu

PCIe 1.8

PCH

QM57

IbexPeak-M

PCI

DDPC

GPIO

HD Audio

SMBUS

LPC

SATA

SPI

PCIe 1.3

PCIe 1.4

rfu

PCIe 1.1 - 1.2

Simplified Block Diagram

PC1-GROOVE

Sheet 2 - PCH

PCIe 1.5

Sheet 3

PCIe to SATA

Sheet 4

J1

Sheet 3

J-DDP

Sheet 3

J-EXP

Sheet 3

J-HSE

Sheet 4

2 x 82574

© EKF -14- ekf.com

User Guide • PC1-GROOVE • Core

TM

i7 CompactPCI

®

CPU Board

Sheet 2

PCH

PCIe 1.5

SATA

USB

Simplified Block Diagram

PC1-GROOVE

Sheet 3 - Mezzanine Connectors

JMB362

PCIe

SATA

SATA

Sheet 2

PCH

Sheet 2

PCH

Sheet 2

PCH

Hanksville

SDVO

DDPC

USB

GPIO

LPC

HD Audio

SMBUS

Sheet 1

CPU

PCIe 0.1 - 0.4

PCIe

Gen2

Switch

PEX 8614

12 x 12

PCIe 2.1 - 2.4

PCIe 3.1 - 3.4

Sheet 4

J2

Opt. Mezz.

Exp. Board

© EKF -15- ekf.com

User Guide • PC1-GROOVE • Core

TM

i7 CompactPCI

®

CPU Board

Sheet 2

PCH

Hanksville

Sheet 3

PCIe

Switch

PCIe 1.1 - 1.2

Hartwell

82574

IT

IT

GbE

SATA

USB

PCIe 3.1 - 3.4

PlusIO

CPCI

PICMG 2.30

PlusIO RIO or

CPCI Serial

Backplane

Sheet 2

PCH

PCI

CompactPCI

Backplane

32-Bit

Simplified Block Diagram

PC1-GROOVE

Sheet 4 - Backplane Connectors

© EKF -16- ekf.com

User Guide • PC1-GROOVE • Core

TM

i7 CompactPCI

®

CPU Board

Top View Component Assembly

SODIMM DDR3

© EKF -17- ekf.com

User Guide • PC1-GROOVE • Core

TM

i7 CompactPCI

®

CPU Board

PC1-GROOVE Top View

PC1-GROOVE Bottom View

© EKF -18- ekf.com

User Guide • PC1-GROOVE • Core

TM

i7 CompactPCI

®

CPU Board

Strapping Headers

DSW1

P-FPH

P-ISP

P-GP

P-MFG

P-RTC

Switches to configurate PCIe link width

Jumper to generate Power Button Events (Front Panel Handle Switch)

PLD Programming Connector, not stuffed

Jumper to reset UEFI BIOS Setup to EKF Factory Defaults

Jumper to enter Manufacturing Mode, not stuffed

Jumper to reset RTC Core of PCH, not stuffed

Connectors & Sockets

J1/J2

J-EXPT

J-EXPB

J-HSE

1)

J-PCIE

J-SDVO2

SODM1

XDP1

CompactPCI Bus 32-bit, 33MHz, PlusIO

Expansion Interface Connector (LPC Interface (Super-I/O, FWH), USB

Interfaces, HD Audio Interface, SMBus), available either from top (T) or bottom (B) of the board

High Speed Expansion Connector (4 x SATA, 4 x USB), Interface to

CompactFlash Carrier C40-SCFA and side boards

PCI Express Expansion Interface Connector

Digital Display Interface Connector

204-pin DDR3 Memory Module SDRAM PC3-8500 Socket

CPU Debug Port

1)

Stuffed on customers request only

Front Panel Elements

EB

GP

HD

PG

RB

Ethernet

(ETH1/2)

Graphics

(DisplayPort)

USB1/2

Dual 1000Base-TX/100Base-TX/10Base-T, RJ-45 Receptacles with integrated indicator LEDs

DisplayPort Receptacle. Alternately available with VGA Connector.

Universal Serial Bus 2.0 self powered root hub, type A receptacle

LED indicating PlusIO Ethernet activity

General Purpose LED

LED indicating any activity on SATA ports

LED indicating Power Good/Board Healthy

System Reset Button

© EKF -19- ekf.com

User Guide • PC1-GROOVE • Core

TM

i7 CompactPCI

®

CPU Board

Microprocessor

The PC1-GROOVE is designed for use with Intel® Core

TM

i7 processors (code name Arrandale). These processors integrate the graphics and memory controller within one chip that up to now were located in an external part of the chipset (GMCH). As a result the platform core is reduced from the known three chip solution (CPU, GMCH, ICH) to only two devices (CPU, PCH).

The Core

TM

i7 family includes beside the Standard-Voltage (SV) also several Ultra Low-Voltage (ULV) and Low-Voltage (LV) processors as listed below. The processors are housed in a Micro FC-BGA package for direct soldering to the PCB, i.e. the chip cannot be removed or changed by the user.

The processors supported by the PC1-GROOVE are running at core clock speeds up to 2.53GHz. Due to Enhanced Intel® SpeedStep® and Intel® Turbo Boost Technology each core can decrease or increase its nominal operating frequency. The internal Core

TM

i7 processor speed is achieved by multiplying the host base frequency of 133MHz by a variable value. The multiplier is chosen depending on the power states of the processor cores/graphics engine, the currently required performance, and the actual core temperature.

Power is applied across the CompactPCI connectors J1 (3.3V, 5V). The processor core voltage is generated by a switched voltage regulator, sourced from the 5V plane. The processor signals its required core voltage by 7 dedicated pins according to Intels IMVP-6.5 voltage regulator specification.

Processor Number of Cores

ULV Core i7-620UE

ULV Core i7-660UE

LV Core i7-620LE

SV Core i7-610E

2

2

2

2

Speed min/max

[GHz]

0.67/1.06

0.67/1.33

1.20/2.00

Processors Supported

L3

Cache

[MB]

4

4

4

TDP

[W]

18

18

25

Die Temp

[°C]

0-105

0-105

0-105

1.20/2.53

4 35 0-105

CPU ID

20652h

20655h

20652h

20652h

Stepping

C-2

K-0

C-2

C-2 sSpec

SLBPA

SLBWV

SLBP9

SLBRZ

© EKF -20- ekf.com

User Guide • PC1-GROOVE • Core

TM

i7 CompactPCI

®

CPU Board

Thermal Considerations

In order to avoid malfunctioning of the PC1-GROOVE, take care of appropriate cooling of the processor and system, e.g. by a cooling fan suitable to the maximum power consumption of the CPU chip actually in use. The processor contains digital thermal sensors (DTS) that are readable via special

CPU registers. DTS allows to get the temperatures of each CPU core separately.

Two further temperature sensors located in the system hardware monitor LM87 allows for acquisition of the boards surface temperature and the thermal state of the onboard system memory channel.

Beside this the LM87 also monitors most of the supply voltages. A suitable software on Microsoft

Windows® systems to display both, the temperatures as well as the supply voltages, is Speedfan, which can be downloaded from the web. After installation, both temperatures and voltages can be observed permanently from the Windows® taskbar.

The PC1-GROOVE is equipped with a passive heatsink. Its height takes into account the 4HP limitation in mounting space of a CompactPCI board. In addition, a forced vertical airflow through the system enclosure (e.g. bottom mount fan unit) is strongly recommended (>20m

3

/h or 2m/s (400LFM) around the CPU slot). Be sure to thoroughly discuss your actual cooling needs with EKF. Generally, the faster the CPU speed the higher its power consumption. For higher ambient temperatures, consider increasing the forced airflow to 3m/s (600LFM) or more.

The table showing the supported processors above give also the maximum power consumption (TDP

= Thermal Design Power) of a particular processor. Fortunately, the power consumption is by far lower when executing typical Windows® or Linux tasks. The heat dissipation increases when e.g.

rendering software like the Acrobat Distiller is executed.

The Core

TM

i7 processors support Intel's Enhanced SpeedStep® technology. This enables dynamic switching between multiple core voltages and frequencies depending on core temperature and currently required performance. The processors are able to reduce their core speed and core voltage in multiple steps down to 1200MHz (667MHz for ULV processors). This leads to an obvious reduction of power consumption resulting in less heating. This mode of lowering the processor core temperature is called TM2 (TM=Thermal Monitor).

Another way to reduce power consumption is to modulate the processor clock. This mode (TM1) is achieved by actuating the 'Stop Clock' input of the CPU. A throttling of 50% e.g. means a duty cycle of 50% on the stop clock input. However, while saving considerable power consumption, the data throughput of the processor is also reduced. The processor works at full speed until the core temperature reaches a critical value. Then the processor is throttled by 50%. As soon as the high temperature situation disappears the throttling will be disabled and the processors runs at full speed again.

These features are controllable by BIOS menu entries. By default the BIOS of the PC1-GROOVE enables mode TM2 which is the most efficient.

The following diagram shows the performance derating with increasing temperature for an i7-610E processor running at its maximum (2.53GHz) and minimum (1.20GHz) frequency as well as an i7-

660UE ULV processor at 1.33GHz.

© EKF -21- ekf.com

User Guide • PC1-GROOVE • Core

TM

i7 CompactPCI

®

CPU Board

Performance Derating

Core®i7-610E/-660UE

Airflow=2.5m/s

120

100

80

60

40

20

0

60 i7-610E, 1.2GHz

i7-610E, 2.53GHz

i7-660UE, 1.33GHz

65 70 75

Temp °C

80 85 90

Main Memory

The PC1-GROOVE features two channels of DDR3 SDRAMs. One channel is realized with 8 memory devices soldered to the board (Memory Down) and delivers a capacity of up to 4GB with a clock frequency of 1066MHz (PC3-8500).

The 2 nd

channel provides a socket for installing a 204-pin SODIMM module thus allowing a simple expansion of system memory (max. module height = 1.25 inch). Supported are unbuffered DDR3

SODIMMs (V

CC

=1.5V) without ECC featuring on-die termination (ODT), according the PC3-6400 or

PC3-8500 specification. Minimum module size is 512MB; maximum module size is 4GB.

It is recommended to add a SODIMM module with same size as the Memory Down to get best performance (some of the system memory is dedicated to the graphics controller). This typically results in a size of 2x1GB of memory which is recommended to run the operating systems Windows® XP,

Windows® Vista or Windows® 7.

The memory controller supports symmetric and asymmetric memory organization. The maximum memory performance can be obtained by using the symmetric mode. When in this mode, the memory controller accesses the memory channels in an interleaved way. Since Core

TM of equal capacity. In the case of unequal memory population the smaller memory channel dictates the address space of the interleaved accessible memory region. The remainder of the memory is then accessed in non-interleaved mode.

i7 processors support

Intels Flex Memory Technology, interleaved operation isn't limited to systems using memory channels

In asymmetric mode the memory always will be accessed in a non-interleaved manner with the drawback of less bandwidth. The only meaningful application of asymmetric mode is the special case when only one memory channel is populated (i.e. the SODIMM socket may be left empty).

The contents of the SPD EEPROM on the SO-DIMM is used by the BIOS at POST (Power-on Self Test) to get any necessary timing parameters to program the memory controller within the chipset.

© EKF -22- ekf.com

User Guide • PC1-GROOVE • Core

TM

i7 CompactPCI

®

CPU Board

Graphics Subsystem

The graphics subsystem is part of the Intel Core

TM controller is located within the Core

TM

i7 processor and the PCH QM57. While the graphics

i7 processor, the different interfaces like DisplayPort, SDVO and

VGA are moved to the PCH. The PC1-GROOVE offers one DisplayPort interface in the front panel.

Adapters to convert DisplayPort to any other popular interface standard are available.

A 2 nd

DisplayPort and an SDVO port is fed to the on-board connector J-SDVO2. Currently expansion boards like CCH-MARIACHI feature the display transmitter to provide a DVI channel via a pure digital

DVI-D connector. Future EKF expansion boards will feature also the possibility to gain access to a 2 nd

DisplayPort interface.

As an option, the PC1-GROOVE can be equipped with an ordinary HD D-Sub 15-lead connector (VGA style). This connector is suitable for analog signals only. Nevertheless also flat-panel displays can be attached to the D-Sub connector but with minor reduced image quality.

Independent from the video connector actually in use, DisplayPort, DVI or VGA, the VESA DDC standard is supported. This allows to read out important parameters, e.g. the maximum allowable resolution, from the attached monitor. If stuffed, DDC Power (+5V) is delivered to the legacy VGA connector. A resettable fuse is used to protect the board from an external short-circuit condition

(0.5A).

Graphics drivers for the Core

TM

i7 can be downloaded from the Intel web site.

LAN Subsystem

The Ethernet LAN subsystem is composed of four Gigabit Ethernet ports: One Intel 82577LM Physical

Layer Transceiver (PHY) using the PCH QM57 internal MAC and three Intel 82574L Gigabit Ethernet

Controllers. These devices provide also legacy 10Base-T and 100Base-TX connectivity. Two of the

Ethernet ports are fed to two RJ45 jacks located in the front panel, the others are attached to the

PlusIO interface on J2/P2. Each port includes the following features:

• One PCI Express lane per Ethernet port (250MB/s)

• 1000Base-Tx (Gigabit Ethernet), 100Base-TX (Fast Ethernet) and 10Base-T (Classic Ethernet) capability.

• Half- or full-duplex operation.

• IEEE 802.3u, 802.3ab Auto-Negotiation for the fastest available connection.

• Jumperless configuration (complete software-configurable).

Two bicoloured LEDs integrated into the dedicated RJ-45 connector in the front panel are used to signal the LAN link, the LAN connection speed and activity status. A further bicoloured LED in front panel labelled EB displays the state of the PlusIO network ports.

Each device is connected by a single PCI Express lane to the PCH. Their MAC addresses (unique hardware number) are stored in dedicated FLASH/EEPROM components. The Intel Ethernet software and drivers for the 82577 and 82574 is available from Intel's World Wide Web site for download.

When managing the board by Intel Active Management Technology (iAMT), the dedicated network port to do so is accessible by the RJ45 connector GbE1 (the upper port within the front panel).

© EKF -23- ekf.com

User Guide • PC1-GROOVE • Core

TM

i7 CompactPCI

®

CPU Board

Serial ATA Interface (SATA)

The PC1-GROOVE provides eight serial ATA (SATA) ports each capable of transferring 3Gbps

(300MByte/s). Four of the six ports integrated within the PCH are routed to the CompactPCI PlusIO interface (J2/P2 connector). The remainder SATA channels of the PCH and two further ports coming from an additional controller (JMicron JMB362) are fed to the high speed expansion connector J-HSE.

This connector allows the installation of local expansion boards like C40-SCFA to attach the popular

CompactFlash cards.

A LED named HD located in the front panel, signals disk activity status of the SATA devices.

Available for download from Intel's and JMicron's web sites are drivers for popular operating systems, e.g. Windows® XP, Windows® Vista, Windows® 7 and Linux.

PCI Express Interface (PCIe)

On PC1-GROOVE four PCI Express lanes, originating from the Core

TM

i7 processor, are building one upstream link to a PCI Express switch. The output ports (downstream ports) of the PCIe switch are connected to the CompactPCI PlusIO connector J2/P2 (four lanes) and to the local PCIe expansion interface connector J-PCIE (four lanes).

Two small DIP switches (DSW1) located on the backside of the board are used to configure different lane widths to each of both downstream interfaces. Possible settings are

• A single link x 4 lanes to J2/P2 and a single link x 4 lanes to J-PCIE

• Four links x 1 lane to J2/P2 and a single link x 4 lanes to J-PCIE

• Four links x 1 lane to J2/P2 and four links x 1 lane to J-PCIE

See section “Configuration Switches PCI Express Link Width (DSW1)” for details.

While the link speed on the upstream side of the switch is restricted to 2.5GT/s due to limitations of the PCH QM57, the downstream ports may support also PCIe Gen 2 speed (5GT/s).

© EKF -24- ekf.com

User Guide • PC1-GROOVE • Core

TM

i7 CompactPCI

®

CPU Board

Universal Serial Bus (USB)

The PC1-GROOVE is provided with twelve USB ports, all of them are USB 2.0 capable. Two USB interfaces are routed to front panel connectors, two ports are feed to the expansion board interface connectors J-EXP, four to the high speed expansion connector J-HSE, and four ports are available across the J2/P2 connector for PlusIO.

The front panel USB connectors can source up to 0.5A/5V each, over-current protected by two electronic switches. Protection for the USB ports on the expansion interfaces and on the PlusIO connector is located on expansion boards like CCH-MARIACHI and the boards on the CompactPCI

Serial backplane respective. The two USB EHCI controllers handling the USB ports are integrated into the PCH.

Real-Time Clock

The PC1-GROOVE has a time-of-day clock and 100-year calendar, integrated into the PCH. A battery on the board keeps the clock current when the computer is turned off. The PC1 uses a BR2032 lithium battery soldered in the board, giving an autonomy of more than 5 years. Under normal conditions, replacement should be superfluous during lifetime of the board.

In applications were the use of a battery is not permitted, a SuperCap can be stuffed instead of the battery.

LPC Super-I/O Interface

In a modern system, legacy ports like PS/2 keyboard/mouse, COM1/2 and LPT have been replaced by

USB and Ethernet connectivity. Hence, the PC1-GROOVE is virtually provided with all necessary I/O ports. However, for compatibility purposes the PC1 is equipped with the interface connector J-EXP to the local LPC bus (LPC = Low Pin Count interface standard), which is a serialized ISA bus replacement.

EKF offers multiple expansion boards to the PC1-GROOVE, featuring all classic Super-I/O functionality, for example the CCH-MARIACHI. Access to the connectors PS/2 (mouse, keyboard), COM, USB and audio in/out is given directly from the front panel. The CCH-MARIACHI connects to the PC1-GROOVE across the connectors P-EXPT or P-EXPB. Usually the CCH is attached to the top of the PC1-GROOVE.

Nevertheless bottom side mounting is possible on customers request.

SPI Flash

The BIOS is stored in two flash devices with Serial Peripheral Interface (SPI). 8MByte of BIOS code,

AMT firmware and user data may be stored nonvolatile in these SPI flashs (up to 16MByte of flash space is available on request).

The SPI flash contents can be reprogrammed (if suitable) by a DOS or Linux based tool. This program and the latest PC1-GROOVE BIOS binary are available from the EKF website. Read carefully the enclosed instructions. If the programming procedure fails e.g. caused by a power interruption, the

PC1-GROOVE may no more be operable. In this case you would possibly have to send in the board, because the flash devices are directly soldered to the PCB and cannot be changed by the user.

© EKF -25- ekf.com

User Guide • PC1-GROOVE • Core

TM

i7 CompactPCI

®

CPU Board

Reset

The PC1-GROOVE is provided with several supervisor circuits to monitor supply rails like the CPU core voltage, 1.5V, 3.3V or 5V. This circuitry is responsible also to generate a clean power-on reset signal.

To force a manual board reset the PC1-GROOVE offers a small tactile switch within the front panel.

This push-button is indent mounted and requires a tool, e.g. a pen to be pressed, preventing from being inadvertently activated.

The ejector within the front panel contains a micro switch that is used to generate a power button event. This is done by pushing the red button of the ejector until the handle unlocks without ejecting the board. Immediately after that push up the ejector back to its original position (the red button jumps up as well). Animated GIF: www.ekf.com/c/ccpu/img/reset_400.gif

NOTE: To prevent the board to cause a power button override, the handle should be closed immediately after unlocking the front panel handle. A power button override is triggered by opening the front panel handle for at least 4 seconds. It results in bringing the board to power state S5. In case of entering this state, unlock and lock the front panel handle a 2 nd

time to reenter normal power state S0 again. See also section 'PG (Power Good) LED' to see how the PC1-GROOVE indicates the different power states.

WARNING: The PC1-GROOVE will enter the power state S5 if the front panel handle is not closed properly when the system powers up. An open handle is signalled by a yellow blinking ‘PG LED’.

The manual reset push-button and the power button functionality of the front panel handle could be passivated by BIOS settings.

An alternative (and recommended) way to generate a system reset is to activate the signal PRST# located on CompactPCI connector J2 pin C17. Pulling this signal to GND will have the same effect as to push the tactile reset switch.

The healthy state of the PC1-GROOVE is indicated by the LED PG (Power Good) located in the front panel. This bicoloured LED signals different states of the board (see section below). As soon as this

LED begins to shine green all power voltages are within their specifications and the reset signal has been deasserted.

© EKF -26- ekf.com

User Guide • PC1-GROOVE • Core

TM

i7 CompactPCI

®

CPU Board

© EKF -27- ekf.com

2

3

User Guide • PC1-GROOVE • Core

TM

i7 CompactPCI

®

CPU Board

1 5

<4s

6

7

4 8

© EKF -28- ekf.com

User Guide • PC1-GROOVE • Core

TM

i7 CompactPCI

®

CPU Board

Watchdog

An important reliability feature is the watchdog function, which is programmable by software. The behaviour of the watchdog is defined within the PLD, which activates/deactivates the watchdog and controls its time-out period. The time-out delay is adjustable in the steps 2, 10, 50 and 255 seconds.

After alerting the WD and programming the time-out value, the related software (e.g. application program) must trigger the watchdog periodically. To simplify watchdog programming all watchdog related functions can be done by calling service requests (software SMI's).

The watchdog is in a passive state after a system reset. There is no need to trigger it at boot time. The watchdog is activated on the first trigger request. If the duration between two trigger requests exceeds the programmed period, the watchdog times out and a full system reset will be generated.

The watchdog remains in the active state until the next system reset. There is no way to disable it once it has been put on alert, whereas it is possible to reprogram its time-out value at any time.

© EKF -29- ekf.com

User Guide • PC1-GROOVE • Core

TM

i7 CompactPCI

®

CPU Board

PG (Power Good) LED

The PC1-GROOVE offers a LED labelled PG located within the front panel. After system reset, this LED defaults to signal different power states:

Off

Red steady

Red blink

Green

Sleep state S3, S4 or S5

Hardware failure

Software failure

Yellow blink Front panel handle is unlocked

Healthy

In the state Off the LEDs GP and HD decode the kind of sleep state as follows:

State

S3

S4

S5

Description

Suspend to RAM/Standby

Suspend to Disk/Hibernate

Soft Off

LED

GP

OFF

ON

ON

LED HD

ON

OFF

ON

To enter the PG LED state Software failure an appropriate service request by software SMI must be called. The PG LED remains in this red blinking state until the next SMI request is made. After that it falls back to its default function.

HD (Hard Disk Activity) LED

The PC1-GROOVE offers a LED marked as HD placed within the front panel. This LED signals activity on any device attached to the SATA ports. Since the HD activity display is realized as a bicolour LED the access of devices connected to PCH QM57 or the SATA-Controller JMB362 can be distinguished in the following way:

Off

Green

Yellow no activity access to PCH SATA Ports access to JMB362 SATA Ports

As described above this LED may change its function dependent on the state of the LED PG.

GP (General Purpose) LED

Another programmable bicoloured LED can be observed from the front panel. The status of the red part within the GP LED is controlled by the GPO18 output of the PCH. Setting this pin to "1" will switch on the red LED. To turn on or off the green LED an appropriate service request (software SMI) must be made.

While the CPU card is controlled by the BIOS firmware, the GP LED is used to signal board status information. A red blinking GP LED is an indication that the BIOS code couldn't start. For details please refer to www.ekf.com/p/pc1/firmware/biosinfo.txt

. After successful operating system boot, the GP LED is not dedicated to any particular hardware or firmware function with exception of special states of the LED PG as described above. Hence it may be freely used by customer software.

© EKF -30- ekf.com

User Guide • PC1-GROOVE • Core

TM

i7 CompactPCI

®

CPU Board

EB (Ethernet Backplane) LED

To monitor the link status and activity on both Ethernet ports attached to the backplane via the J2/P2 connector (PlusIO) a single bicoloured LED is provided in the front panel. The states are decoded as follows:

1_ETH no link link no link link

2_ETH no link no link link link

LED EB

OFF

Green

Yellow

Green/Yellow

Blinking of the LED EB in the appropriate colour means that there is activity on the port.

Hot Swap Detection

The CompactPCI specification added the signal ENUM# to the PCI bus to allow board hot swapping.

This signal is routed to the GPI3 of the PCH. A System Management Interrupt (SMI) can be requested if ENUM# changes by insertion or removal of a board.

Note that the PC1-GROOVE itself is not a hot swap device, because it makes no sense to remove the system controller from a CompactPCI system. However, it is capable to recognize the hot swap of peripheral boards and to start software that is doing any necessary system reconfiguration.

Power Supply Status (DEG#, FAL#)

Power supply failures may be detected before the system crashes down by monitoring the signals

DEG# or FAL#. These active low lines are additions of the CompactPCI specification and may be driven by the power supply. DEG# signals the degrading of the supply voltages, FAL# their possible failure. On the PC1-GROOVE the signals FAL# and DEG# are routed to the PCH GPI4 and GPI5 respectively.

© EKF -31- ekf.com

User Guide • PC1-GROOVE • Core

TM

i7 CompactPCI

®

CPU Board

Mezzanine Side Board Options

The PC1-GROOVE is provided with several stacking connectors for attachment of a mezzanine expansion module (aka side board), suitable for a variety of readily available mezzanine cards (please refer to www.ekf.com/c/ccpu/mezz_ovw.pdf for a more comprehensive overview). EKF furthermore offers custom specific development of side boads (please contact [email protected]).

4 x SATA

(2 RAID)

4 x USB

J-HSE

LPC/SMB

2 x USB

HD Audio

J-EXP

PCI Express®

1 x 4

4 x 1

J-PCIE

USB

USB

VGA

DP

J2

UHM

© EKF ekf.com

Memory

Down

Intel®

Core™ i7

SV/LV/ULV

Dual

GbE

J1

J-SDVO2

PC1-GROOVE

Mezzanine Connectors

© EKF • ekf.com

SDVO (DVI)

DisplayPort

Most mezzanine expansion modules require an assembly height of 8HP in total, together with the

CPU carrier board (resulting from two cards at 4HP pitch each).

In addition, cropped mezzanine modules are available for mass storage, which maintain the 4HP envelope (see illustrations next page), for extremely compact systems. Furthermore these small size modules may be combined with the full-size expansion boards (that means an assembly comprised of

3 PCBs).

© EKF -32- ekf.com

User Guide • PC1-GROOVE • Core

TM

i7 CompactPCI

®

CPU Board

Low Profile Storage Module Area

PC1-GROOVE with C47-MSATA RAID Mezzanine Module

© EKF -33- ekf.com

User Guide • PC1-GROOVE • Core

TM

i7 CompactPCI

®

CPU Board

PC1-GROOVE w. C41-CFAST Mezzanine Module

PC1-GROOVE w. C41-CFAST Mezzanine Module

© EKF -34- ekf.com

User Guide • PC1-GROOVE • Core

TM

i7 CompactPCI

®

CPU Board

PC1-GROOVE w. C42-SATA Mezzanine Module

Related Documents Mezzanine Modules and Side Cards

C40 ... C45 Series

Mezzanine Storage Modules

Mezzanine Modules Overview www.ekf.com/c/ccpu/c4x_mezz_ovw.pdf

www.ekf.com/c/ccpu/mezz_ovw.pdf

© EKF -35- ekf.com

User Guide • PC1-GROOVE • Core

TM

i7 CompactPCI

®

CPU Board

C41-CFAST Mezzanine Module

C42-SATA Mezzanine Module

© EKF -36- ekf.com

User Guide • PC1-GROOVE • Core

TM

i7 CompactPCI

®

CPU Board

C43-SATA Mezzanine Module

PC1-GROOVE • C44-SATA Side Card

© EKF -37- ekf.com

User Guide • PC1-GROOVE • Core

TM

i7 CompactPCI

®

CPU Board

C45-SATA Side Card

PC1-GROOVE • C45-SATA (Removable SSD)

© EKF -38- ekf.com

User Guide • PC1-GROOVE • Core

TM

i7 CompactPCI

®

CPU Board

PC1-GROOVE • C45-SATA (Internal SSD)

Custom Specific Mezzanine Module Design

© EKF -39- ekf.com

User Guide • PC1-GROOVE • Core

TM

i7 CompactPCI

®

CPU Board

<

<

<

<

CompactPCI

®

PlusIO Option

The PICMG

®

2.30 CompactPCI

CompactPCI

®

®

PlusIO specification defines the usage of rear I/O pins of the 32-bit

system slot for high-speed serial signals. For these high-speed signals a new J2 connector (3M UHM type) has been introduced, which is compatible to the classic 2.0mm hard metric connector J2, and in addition is suitable for high speed differential signals.

The main advantage of the combination of legacy PCI (J1/P1) and modern serial buses on J2/P2 is to realize hybrid backplanes. Hence, the CompactPCI

®

PlusIO standard helps to define a simple migration path from parallel PCI systems to modern serial, point-to-point interconnected systems such as

CompactPCI

®

Serial (PICMG

®

CPCI-S.0, draft/proposal as of current).

PICMG boards – depending on their particular interfaces – CompactPCI

PICMG

®

®

2.30 defines just the system slot J2/P2 extension. With respect to high speed signal peripheral controlled across J1/P1.

®

Serial, CompactPCI

®

Express or

2.16 cards may be combined in a system, in addition to 32-bit classic CompactPCI

®

boards,

The PC1-GROVE is provided with all CompactPCI

®

PICMG

®

2.30 via the connector J2/P2:

PlusIO communication channels defined by

Four PCIe Lanes 2.5GT/s or 5GT/s

Four SATA Ports 3GT/s

Four USB 2.0 Ports

Two Gigabit Ethernet Ports

USB

USB

VGA

DP

© EKF ekf.com

J-HSE

Dual

GbE

J-EXP

J-PCIE

J-SDVO2

PC1-GROOVE • CompactPCI® PlusIO • © EKF • ekf.com

J2

UHM

J1

CPCIS.0

Peripheral

Boards up to

4 x PCIe

4 x SATA

4 x USB

2 x GE

Warning: Do not operate the PC1-GROOVE in systems with a 64-bit CompactPCI

J2/P2 pin assignments of a 64-bit CPCI backplane differ substantially from a CompactPCI backplane, which may result in a short circuit situation.

®

backplane. The

®

PlusIO

© EKF -40- ekf.com

User Guide • PC1-GROOVE • Core

TM

i7 CompactPCI

®

CPU Board

The PC1-GROOVE can be used in any system with a CompactPCI

PICMG

®

®

PlusIO backplane according to the

2.30 specification. Hybrid backplanes allow the configuration of systems with CompactPCI

®

Serial slots in addition to classic CompactPCI

®

boards.

CompactPCI® PlusIO & CompactPCI® Serial

Hybrid Backplane

CompactPCI 32-Bit

Peripheral Slots

CPCIS.0

Peripheral Slots

Sample Small Systems Hybrid Backplane

Related Documents CompactPCI® PlusIO & CompactPCI® Serial

CompactPCI® Serial - Concise Guide www.ekf.com/s/serial_concise.pdf

CompactPCI® Serial - The Smart Solution

CompactPCI® Serial Home www.ekf.com/s/smart_solution.pdf

www.ekf.com/s/serial.html

CompactPCI® PlusIO Home www.ekf.com/p/plus.html

© EKF -41- ekf.com

User Guide • PC1-GROOVE • Core

TM

i7 CompactPCI

®

CPU Board

PC1-GROOVE as System Controller in a Hybrid System

Sample Hybrid CompactPCI® & CompactPCI® Serial Backplanes

© EKF -42- ekf.com

User Guide • PC1-GROOVE • Core

TM

i7 CompactPCI

®

CPU Board

Sample Hybrid System Rack

Sample Hybrid System Rack

© EKF -43- ekf.com

User Guide • PC1-GROOVE • Core

TM

i7 CompactPCI

®

CPU Board

As an alternate, the PC1-GROOVE can be combined with a CompactPCI high speed signals.

®

PlusIO rear I/O transition module, such as the PR1-RIO, which is provided with I/O connectors (on-board and back-panel) for all

PR1-RIO • Rear I/O Transition Module

PR1-RIO w. on-Board USB Stick

© EKF -44- ekf.com

User Guide • PC1-GROOVE • Core

TM

i7 CompactPCI

®

CPU Board

PR1-RIO w. on-Board PE Cable Connectors

© EKF -45- ekf.com

User Guide • PC1-GROOVE • Core

TM

i7 CompactPCI

®

CPU Board

PC1-GROOVE & PR1-RIO

PC1-GROOVE & PR1-RIO

© EKF -46- ekf.com

User Guide • PC1-GROOVE • Core

TM

i7 CompactPCI

®

CPU Board

Installing and Replacing Components

Before You Begin

Warnings

The procedures in this chapter assume familiarity with the general terminology associated with industrial electronics and with safety practices and regulatory compliance required for using and modifying electronic equipment. Disconnect any telecommunication links, networks or procedures described in this chapter. Failure links before you open the system or perform or equipment damage. Some parts of the the power switch is in its off state.

the system from its power source and from modems before performing any of the to disconnect power, or telecommunication any procedures can result in personal injury system can continue to operate even though

Caution

Electrostatic discharge (ESD) can damage components. Perform the procedures described in this chapter only at an ESD workstation. If such a some ESD protection by wearing an metal part of the system chassis or board original ESD protected packaging. Retain the station is not available, you can provide antistatic wrist strap front panel. Store the board only in its original packaging (antistatic bag and antistatic box) in case of returning the board to EKF for repair.

© EKF -47- ekf.com

User Guide • PC1-GROOVE • Core

TM

i7 CompactPCI

®

CPU Board

Installing the Board

Warning

This procedure should be done only by qualified technical personnel. Disconnect the system from its power source before doing the procedures described here. Failure to disconnect power, or telecommunication links before you open the system or perform any procedures can result in personal injury or equipment damage.

C

C

Typically you will perform the following steps:

C

Switch off the system, remove the AC power cord

C

C

Attach your antistatic wrist strap to a metallic part of the system

Remove the board packaging, be sure to touch the board only at the front panel

C

C

C

Identify the related CompactPCI slot (peripheral slot for I/O boards, system slot for CPU boards, with the system slot typically most right or most left to the backplane)

Insert card carefully (be sure not to damage components mounted on the bottom side of the board by scratching neighboured front panels)

A card with onboard connectors requires attachment of associated cabling now

Lock the ejector lever, fix screws at the front panel (top/bottom)

Retain original packaging in case of return

© EKF -48- ekf.com

User Guide • PC1-GROOVE • Core

TM

i7 CompactPCI

®

CPU Board

Removing the Board

Warning

This procedure should be done only by qualified technical personnel. Disconnect the system from its power source before doing the procedures described here. Failure to disconnect power, or telecommunication links before you open the system or perform any procedures can result in personal injury or equipment damage.

Typically you will perform the following steps:

C

Switch off the system, remove the AC power cord

C

C

Attach your antistatic wrist strap to a metallic part of the system

Identify the board, be sure to touch the board only at the front panel

C

C

C unfasten both front panel screws (top/bottom), unlock the ejector lever

Remove any onboard cabling assembly

Activate the ejector lever

C

C

Remove the card carefully (be sure not to damage components mounted on the bottom side of the board by scratching neighboured front panels)

Store board in the original packaging, do not touch any components, hold the board at the front panel only

Warning

Do not expose the card to fire. Battery cells and other components could explode and cause personal injury.

© EKF -49- ekf.com

User Guide • PC1-GROOVE • Core

TM

i7 CompactPCI

®

CPU Board

EMC Recommendations

In order to comply with the CE regulations for EMC, it is mandatory to observe the following rules:

C

C

The chassis or rack including other boards in use must comply entirely with CE

Close all board slots not in use with a blind front panel

C

C

C

C

C

Front panels must be fastened by built-in screws

Cover any unused front panel mounted connector with a shielding cap

External communications cable assemblies must be shielded (shield connected only at one end of the cable)

Use ferrite beads for cabling wherever appropriate

Some connectors may require additional isolating parts

Reccomended Accessories

Blind CPCI Front

Panels

Ferrit Bead Filters

Metal Shielding

Caps

EKF Elektronik

ARP Datacom,

63115 Dietzenbach

Conec-Polytronic,

59557 Lippstadt

Widths currently available

(1HP=5.08mm): with handle 4HP/8HP without handle

2HP/4HP/8HP/10HP/12HP

Ordering No.

102 820 (cable diameter 6.5mm)

102 821 (cable diameter 10.0mm)

102 822 (cable diameter 13.0mm)

Ordering No.

CDFA 09 165 X 13129 X (DB9)

CDSFA 15 165 X 12979 X (DB15)

CDSFA 25 165 X 12989 X (DB25)

© EKF -50- ekf.com

User Guide • PC1-GROOVE • Core

TM

i7 CompactPCI

®

CPU Board

Installing or Replacing the Memory Module

Note: If you decide to replace the memory, observe the precautions in 'Before You Begin'

By default, the PC1-GROOVE is delivered with onboard memory only, the SODIMM DDR3 SDRAM socket is empty.

To expand the memory a DDR3 SDRAM SODIMM module may be inserted in the socket SODM1. It is necessary to use an SODIMM that provide Serial Presence Detect (SPD) information, since this allows the chipset to accurately configure the memory settings for optimum performance.

A replacement memory module must match the 204-pin SODIMM form factor (known from

Notebook PCs), DDR3, V

CC

=1.5V, PC3-6400/PC3-8500 (800/1066MHz), on-die termination (ODT), unbuffered, non-ECC style. Suitable modules are available up to 4GB. The Core more than 16 address lines are not suitable.

TM

i7 memory controller supports modules of up to a maximum of 16 address lines (A0...A15). Memory modules organized by

Replacement of the Battery

When your system is turned off, a battery maintains the voltage to run the time-of-day clock and to keep the values in the CMOS RAM. The battery should last during the lifetime of the PC1-GROOVE.

For replacement, the old battery must be unsoldered, and the new one soldered. We suggest that you send back the board to EKF for battery replacement.

Warning

Danger of explosion if the battery is incorrectly replaced or shorted. Replace only with the same or equivalent type. Do not expose a battery to fire.

© EKF -51- ekf.com

User Guide • PC1-GROOVE • Core

TM

i7 CompactPCI

®

CPU Board

Technical Reference

Local PCI Devices

The following table shows the on-board PCI devices and their location within the PCI configuration space. These devices consist of some locale controllers and several devices within the Intel 5 series express chip set.

Bus

Number

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

1

2)

2

2)

0

0

Device

Number

28

28

28

26

27

28

28

28

22

22

25

2

22

0

1

22

30

31

31

28

28

29

31

31

31

0

0

Function

Number

3

4

5

0

1

0

0

2

2

3

0

0

0

0

0

1

0

0

2

6

7

0

3

5

6

0

0

Vendor ID

0x8086

0x8086

0x8086

0x8086

0x8086

0x8086

0x8086

0x8086

0x8086

0x8086

0x8086

0x8086

0x8086

0x8086

0x8086

0x8086

0x8086

0x8086

0x8086

0x8086

0x8086

0x8086

0x8086

0x8086

0x8086

0x10B5

0x197B

Device ID

0x3B4E

0x3B50

0x3B34

0x244E

0x3B07

0x3B28

0x3B2F

0x3B2C

0x3B30

0x3B2D

0x3B32

0x8614

0x2363

0x2362

0x10D3

0x3B3C

0x3B56

0x3B42

0x3B44

0x3B46

0x3B48

0x3B4A

0x3B4C

0x0044

0x0045

0x0046

0x3B64

0x3B65

0x3B66

0x3B67

0x10EA

Description

Host Bridge/DRAM Controller

Host-PCIe Bridge

Internal Graphics Device

ME Interface #1

ME Interface #2

ME IDE Redirection

Keyboard Text Redirection

PCH Gigabit LAN NC1 (82577)

USB 2.0 EHCI Controller #2

Intel High Definition Audio

PCI Express Port 1

PCI Express Port 2

PCI Express Port 3

PCI Express Port 4

PCI Express Port 5

PCI Express Port 6

PCI Express Port 7

PCI Express Port 8

USB 2.0 EHCI Controller #1

DMI-to-PCI Bridge

LPC Bridge

SATA: Non-AHCI/RAID

1)

SATA: AHCI Mode

1)

SATA: RAID 0/1/5/10 Mode 1)

SMBus Controller

SATA Controller #2

Thermal Controller

PCIe Switch (PEX8614)

PCIe-SATA-Bridge (JMB362 Rev. A)

PCIe-SATA-Bridge (JMB362 Rev. C)

Ethernet Controller NC2 (82574) 3 2) 0 0 0x8086

1)

Depends on BIOS settings.

2)

Bus number can vary depending on the PCI enumeration schema implemented in BIOS.

© EKF -52- ekf.com

User Guide • PC1-GROOVE • Core

TM

i7 CompactPCI

®

CPU Board

Local SMB Devices

The PC1-GROOVE contains a few devices that are reachable via the System Management Bus (SMBus).

These are the clock generation chip, the SPD EEPROMs for the onboard memory channel or located on the SODIMM memory module, a general purpose serial EEPROM and a supply voltage and temperature controlling device in particular. Other devices could be connected to the SMBus via the

CompactPCI signals IPMB SCL (J1 B17) and IPMB SDA (J1 C17) or pins 29/30 of the expansion connectors J-EXPT/J-EXPB.

Address

0x58

0xA0

0xA4

0xAE

0xD2

Description

Hardware Monitor/CPU Temperature Sensor (LM87)

SPD of Onboard Memory

SPD of SODIMM

General Purpose EEPROM

Main Clock Generation (CK-505)

Hardware Monitor LM87

Located on the SMBus the PC1-GROOVE offers a hardware monitor of type LM87/NSC. This device is capable to observe board and onboard memory temperatures as well as several supply voltages generated on the board with a resolution of 8 bit. The following table shows the mapping of the voltage inputs of the LM87 to the corresponding supply voltages of the PC1-GROOVE:

Input Source

AIN1

AIN2

VCCP1

VCCP2/D2-

+2.5V/D2+

+3.3V

+5V

+12V

CPU Core Voltage

Graphics Core Voltage

+1.5V

+1.8V

+1.05V

+3.3V

+5V

+10V

Resolution

[mV]

9.8

9.8

14.1

14.1

13

17.2

26

62.5

Register

0x28

0x29

0x21

0x25

0x20

0x22

0x23

0x24

Beside the continuous measuring of temperatures and voltages the LM87 may compare these values against programmable upper and lower boundaries. As soon as a measurement violates the allowed value, the LM87 may request an interrupt via the GPI13 of the PCH.

© EKF -53- ekf.com

GPIO Usage

GPIO Usage PCH

User Guide • PC1-GROOVE • Core

TM

i7 CompactPCI

®

CPU Board

GPIO

GPIO 0

GPIO 1

GPIO 2

GPIO 3

GPIO 4

GPIO 5

GPIO 6

GPIO 13

GPIO 14

GPIO 15

GPIO 16

GPIO 17

GPIO 18

GPIO 19

GPIO 20

GPIO 7

GPIO 8

GPIO 9

GPIO 10

GPIO 11

GPIO 12

GPIO 21

GPIO 22

GPIO 23

GPIO 24

GPIO 25

GPIO 26

GPIO 27

GPIO 28

GPIO 29

GPIO 30

GPIO 31

GPIO 32

GPIO 33

Type

I

I

I

I

I

I

O

O

O

I

O

O

I

I

O

I

I

O

I

O

I

I

O

O

I

O

O

O

I

O

I

I

I/O

I

Tol.

3.3V

3.3V

5V

5V

5V

5V

3.3V

3.3V

3.3V

3.3V

3.3V

3.3V

3.3V

3.3V

3.3V

3.3V

3.3V

3.3V

3.3V

3.3V

3.3V

3.3V

3.3V

3.3V

3.3V

3.3V

3.3V

3.3V

3.3V

3.3V

3.3V

3.3V

3.3V

3.3V

PC1-GROOVE GPIO Usage PCH QM57

Function

THRM_ALERT#

EXP_SMI#

Description

Monitoring of processor PROCHOT#

Expansion Interface SMI Request (J-EXP Pin 15)

CPCI_INTP

CPCI_ENUM#

CPCI_FAL#

CPCI_DEG#

CPCI_INTS_EN

CPCI_SYSEN#

N/A

USB_OC5#

USB_OC6#

GP_JUMP#

NC1_ENABLE

HM_INT#

USB_OC7#

N/A

N/A

CPCI_CLKEN

GP_LED_RED

PLD_SCL

SE_SYS_WP

PLD_SDA

SCLOCK

LPC_DRQEXP#

USB_POWEN1#

N/A

N/A

USB_POWEN2#

CPCI_SMB_EN

SLP_LAN#

SUS_PWR_DN_ACK

ACPRESENT

CLKRUN#

MFG_JUMP#

CompactPCI Interrupt Request Line INTP

CompactPCI System Enumeration Line ENUM#

CompactPCI Power Failure Line FAL#

CompactPCI Power Degeneration Line DEG#

Connect SERIRQ to CompactPCI Line INTS

LOW: SERIRQ disconnected from INTS

HIGH: SERIRQ connected to INTS

Sense CompactPCI System Slot Enable Line SYSEN#

Not used on PC1 (left NC)

USB HSE Port #2 Overcurrent Detect

USB HSE Port #3 or #4 Overcurrent Detect

Reset UEFI BIOS Setup to Factory Defaults, Jumper P-GP

Enable Ethernet Controller NC2

Hardware Monitor LM87 Interrupt Line

USB Front Panel Upper Port Overcurrent Detect

Not used on PC1 (pulled via resistor to +3.3V)

Not used on PC1 (pulled via resistor to +3.3V)

Enable CompactPCI Clock Buffer

General Purpose LED Control (via PLD)

Local Option Reg Interface (within PLD)

General Purpose Serial EEPROM Write Protection

Local Option Reg Interface (within PLD)

Serial GPIO Bus CLOCK (J2: SATA_SC)

Expansion Interface LPC DMA Request Line

USB Front Panel Upper Port Power Enable

Not used on PC1 (pulled via resistor to +3.3V)

Not used on PC1 (pulled via resistor to +3.3V)

USB Front Panel Lower Port Power Enable

Connect SMBus of CPCI IPMB/J-EXP to local SMBus

LOW: IPMB/J-EXP disconnected from SMBus

HIGH: IPMB/J-EXP connected to SMBus

Multiplexed with SLP_LAN#

Not used on PC1 (pulled via resistor to +3.3V)

Not used on PC1 (pulled via resistor to +3.3V)

Fixed to chipset internal function

Select Manufacturing Mode Jumper P-MFG

© EKF -54- ekf.com

GPIO

GPIO 34

GPIO 35-37

GPIO 53

GPIO 54

GPIO 55

GPIO 56

GPIO 57

GPIO 58

GPIO 59

GPIO 60

GPIO 61

GPIO 62

GPIO 63

GPIO 64-67

GPIO68-71

GPIO 72

GPIO 73

GPIO 74

GPIO 75

GPIO 45

GPIO 46

GPIO 47

GPIO 48

GPIO 49

GPIO 50

GPIO 51

GPIO 52

GPIO 38

GPIO 39

GPIO 40

GPIO 41

GPIO 42

GPIO 43

GPIO 44

Type

O

I

Tol.

3.3V

3.3V

I

N/A

I

O

O

I

I

O

I

I

I

I

O

I

O

I

O

I

O

I

I

I

I

I

I

O

I

I

O

I

O

O

3.3V

3.3V

3.3V

3.3V

3.3V

3.3V

N/A

3.3V

3.3V

5V

3.3V

3.3V

3.3V

3.3V

3.3V

3.3V

3.3V

3.3V

3.3V

3.3V

3.3V

3.3V

5V

3.3V

5V

3.3V

3.3V

3.3V

3.3V

3.3V

3.3V

3.3V

User Guide • PC1-GROOVE • Core

TM

i7 CompactPCI

®

CPU Board

PC1-GROOVE GPIO Usage PCH QM57

Function

STP_PCI#

HWREV

Description

Multiplexed with chipset internal function

GPIO 37/36/35

000

001

...

111

PCB Revision

0

1

...

7

Serial GPIO Bus LOAD (J2: SATA_SL)

CPCI_GNT2#

CPCI_REQ3#

CPCI_GNT3#

N/A

ENABLE_NC2

N/A

USB_OC0#

N/A

N/A

SUSCLK

SLP_S5#

BOARD_CFG

N/A

N/A

NC1_CLKREQ#

N/A

N/A

SLOAD

SDATAOUT

USB_OC1#

ENABLE_NC3

ENABLE_NC4

USB_OC4#

N/A

WDOGRST

N/A

CPCI_12VOK

N/A

N/A

CPCI_REQ1#

CPCI_GNT1#

CPCI_REQ2#

Serial GPIO Bus DATAOUT (J2: SATA_SC)

USB Front Panel Lower Port Overcurrent Detect

Enable Ethernet Controller NC3

Enable Ethernet Controller NC4

USB J-HSE Port #1 Overcurrent Detect

Not used on PC1 (pulled via resistor to +3.3V)

Last Hardware Reset caused by watchdog

Not used on PC1 (pulled via resistor to +3.3V)

CompactPCI +12V Present

Not used on PC1 (pulled via resistor to +3.3V)

Not used on PC1 (pulled via resistor to GND)

CompactPCI Bus Request Line CPCI_REQ1#

CompactPCI Bus Grant Line CPCI_GNT1#

CompactPCI Bus Request Line CPCI_REQ2#

CompactPCI Bus Grant Line CPCI_GNT2#

CompactPCI Bus Request Line CPCI_REQ3#

CompactPCI Bus Grant Line CPCI_GNT3#

Not used on PC1 (pulled via resistor to +3.3V)

Enable Ethernet Controller NC2

Not used on PC1 (pulled via resistor to +3.3V)

USB Front Panel Upper Port Overcurrent Detect

Not used on PC1 (pulled via resistor to +3.3V)

Not used on PC1 (left NC)

Multiplexed with chipset internal function

Multiplexed with chipset internal function

Board Configuration Jumpers

Not implemented in PCH QM57

Not used on PC1 (pulled via resistor to +3.3V)

Multiplexed with chipset internal function

Not used on PC1 (pulled via resistor to +3.3V)

Not used on PC1 (pulled via resistor to +3.3V)

© EKF -55- ekf.com

User Guide • PC1-GROOVE • Core

TM

i7 CompactPCI

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CPU Board

Configuration Jumpers

Configuration Switches PCI Express Link Width (DSW1)

The link width of the PCI Express interfaces attached to the PlusIO interface J2/P2 and the local expansion connector P-PCIE is configurable by two DIP switches (DSW1) located on the backside of the PC1-GROOVE. Note that changes in PCIe link width configuration are honoured by the

PC1-GROOVE not before a system reset was performed.

ON

1 2

DSW1

1

DSW1

OFF

ON

OFF

ON

1)

2

OFF

OFF

ON

ON

1)

PCIe Switch

Upstream

4 Lanes

4 Lanes

4 Lanes

1 Lane

PCIe Link Width

J2/P2 (PlusIO) J-PCIE

1 Link x 4 Lanes 1 Link x 4 Lanes

4 Links x 1 Lane 1 Link x 4 Lanes

4 Links x 1 Lane 4 Links x 1 Lane

4 Links x 1 Lane 4 Links x 1 Lane

1)

This setting is not useful and should not be used.

When a port is configured as single link, the PCIe switch may size down the link width to x2 or x1 by auto-negotiation.

The following table shows the factory settings of DSW1 with different side boards mounted to the

PC1-GROOVE:

Side Board

None

C23-SATA

CCI-RAP

CCJ-RHYTHM

CCK-MARIMBA

CCL-CAPELLA

CCO-CONCERT

1

DSW1

2

OFF ON

OFF ON

OFF ON

ON OFF

ON OFF

ON OFF

OFF ON

Upstream

4 Lanes

4 Lanes

4 Lanes

4 Lanes

4 Lanes

4 Lanes

4 Lanes

PCIe Link Width

J2/P2 (PlusIO) J-PCIE

4 Links x 1 Lane 4 Links x 1 Lane

4 Links x 1 Lane 4 Links x 1 Lane

4 Links x 1 Lane 4 Links x 1 Lane

4 Links x 1 Lane 1 Link x 4 Lanes

4 Links x 1 Lane 1 Link x 4 Lanes

4 Links x 1 Lane 1 Link x 4 Lanes

4 Links x 1 Lane 4 Links x 1 Lane

© EKF -56- ekf.com

User Guide • PC1-GROOVE • Core

TM

i7 CompactPCI

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Loading UEFI BIOS Setup Defaults (P-GP)

The jumper P-GP is used to reset the UEFI BIOS configuration settings to a default state. The UEFI BIOS on PC1-GROOVE stores most of its settings in an area within the BIOS flash, e.g. the actual boot devices. Using the jumper P-GP is only necessary, if it is not possible to enter the setup of the BIOS. To reset the settings mount a jumper on P-GP and perform a system reset. As long as the jumper is stuffed the BIOS will use the default configuration values after any system reset. To get normal operation again, the jumper has to be removed.

1

P-GP

P-GP

Jumper OFF

1)

Function

Normal operation

Jumper ON BIOS configuration reset performed

1)

This setting is the factory default.

Manufacturer Mode Jumper (P-MFG)

The jumper P-MFG is used to bring the board into the manufacturer mode. This is necessary only on board production time and should not used by customers. For normal operation the jumper should be removed.

1

1)

This setting is the factory default.

2)

P-MFG is not stuffed.

P-MFG

Jumper OFF

1)

Jumper ON

P-MFG

Function

Normal Mode

Manufacturer Mode

© EKF -57- ekf.com

User Guide • PC1-GROOVE • Core

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i7 CompactPCI

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CPU Board

Reset Jumper PCH RTC Core (P-RTC)

The jumper P-RTC is used to reset the battery backed core of the PCH. This effects some registers within the PCHs RTC core that are important before the CPU starts its work after a system reset. Note that P-RTC will neither set UEFI BIOS Setup to EKF Factory Defaults nor resets the real time clock. To reset the RTC core the board must be removed from the system rack. Short-circuit the pins of P-RTC for about 1 sec. After that reinstall the board to the system and switch on the power. It is important to accomplish the RTC reset while the board has no power.

1

1)

This setting is the factory default.

2)

P-RTC is not stuffed.

P-RTC

Jumper OFF

1)

Jumper ON

P-RTC

Function

No RTC reset performed

RTC reset performed

© EKF -58- ekf.com

User Guide • PC1-GROOVE • Core

TM

i7 CompactPCI

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CPU Board

Connectors

Caution

Some of the internal connectors provide operating voltage (3.3V and 5V) to devices inside the system chassis, such as internal peripherals. Not all of these connectors are overcurrent protected. Do not use these internal connectors for powering devices external to the computer chassis. A fault in the load presented by the external devices could cause damage to the board, the interconnecting cable and the external devices themselves.

Front Panel Connectors

Typical PC1-GROOVE Front Panel Elements

PG

GP

USB

DP

RB

HD

ETH

EB

PG

GP

USB

RB

HD

EB

ETH

VGA

PC1-GROOVE

DisplayPort

PC1-GROOVE

VGA

© EKF -59- ekf.com

User Guide • PC1-GROOVE • Core

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i7 CompactPCI

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DisplayPort Monitor Connector J-DP

20

8

6

12

10

4

2

DisplayPort J-DP

20 PWR

1)

18

16

14

HPD

GND

CONFIG2 (GND)

LANE3(N)

LANE3(P)

GND

LANE1(N)

LANE1(P)

GND

7

5

11

9

3

1

19

17

15

13

RETURN (GND)

AUX_CH(N)

AUX_CH(P)

CONFIG1

GND

LANE2(N)

LANE2(P)

GND

LANE0(N)

LANE0(P)

1)

+3.3V protected by a PolySwitch Fuse 0.5A. This voltage is switched on in S0 state only.

For attachment of either a classic style analog RGB monitor or DVI type display to the J-DP receptacle, there are both adapters and also adapter cables available, from DisplayPort to the VGA or DVI connector.

Plug Style Adapter

© EKF -60- ekf.com

User Guide • PC1-GROOVE • Core

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i7 CompactPCI

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CPU Board

Plug Style DP to DVI Adapter

Cable Adapter DP to DVI

Cable Adapter DP to VGA

© EKF -61- ekf.com

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i7 CompactPCI

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Specified by the VESA DisplayPort connector standard is a dedicated power pin 20 (+3.3V 0.5A). Both the GPU (source side) and a DP monitor (sink side) must provide power via this pin. A VESA specified

DisplayPort cable however must not connect the pins 20 of both cable ends, in order to avoid a back driving conflict. Unfortunately there are cable assemblies available with pin 20 passed through, with unpredictable results on the system behaviour. Before ordering DP cable assemblies, verify the associated wiring diagram.

Sample VESA Compliant DisplayPort Cable Assemblies

2.0m Plug to Plug, w. Latches • EKF Part. #270.66.1.02.0

Manhattan 307116, 391931

Molex 68783-0007

TE (Tyco) 2040687-2, 2040638-2

A secondary DiplayPort video output is available with the mezzanine side card PCS-BALLET, for operation of two independent monitors (e.g. Extended Desktop).

PC1-GROOVE 12HP Assembly w. PCS-BALLET & C32-FIO

© EKF -62- ekf.com

User Guide • PC1-GROOVE • Core

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i7 CompactPCI

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CPU Board

Video Monitor Connector J-VGA

As an option, the PC1-GROOVE can be equipped with a legacy VGA connector (High-Density D-Sub

15-position female connector). The connector J-VGA replaces the J-DP receptacle, and the digital

DisplayPort video interface therefore is not available concurrently with this option.

15

11

10

6

5

1

J-VGA (Option)

9

10

7

8

5

6

3

4

11

12

13

14

15

1

2

RED

GREEN

BLUE

NC

GND

GND

GND

GND

DDC_POW

1)

GND

NC

VGA_DDC_SDA

HSYNC

VSYNC

VGA_DDC_SCL

1)

+5V protected by a PolySwitch Fuse 0.5A. This power rail is switched on in S0 state only.

© EKF -63- ekf.com

USB Connectors

User Guide • PC1-GROOVE • Core

TM

i7 CompactPCI

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1 4

#270.20.04.2

©EKF • ekf.com

USB Ports 1/2 (J-USB1/J-USB2)

1

2

3

4

POW

1)

USB DATA (N)

USB DATA (P)

GND

1)

+5V protected by an Electronic Fuse 0.5A. Power rail may be switched off by software independently for each port.

Ethernet Connectors

1

1

270.02.08.5

Gigabit Ethernet Ports 1/2 (J-ETH, RJ45)

1

2

Port 1

Port 2

6

7

4

5

8

2

3

8

1

5

6

3

4

7

NC1_MDX0+

NC1_MDX0-

NC1_MDX1+

NC1_MDX2+

NC1_MDX2-

NC1_MDX1-

NC1_MDX3+

NC1_MDX3-

NC2_MDX0+

NC2_MDX0-

NC2_MDX1+

NC2_MDX2+

NC2_MDX2-

NC2_MDX1-

NC2_MDX3+

NC2_MDX3-

The lower green LED indicates LINK established when continuously on, and data transfer (activity) when blinking. If the lower green LED is permanently off, no LINK is established. The upper green/yellow dual-LED signals the link speed 1Gbit/s when lit yellow, 100Mbit/s when lit green, and

10Mbit/s when off.

© EKF -64- ekf.com

User Guide • PC1-GROOVE • Core

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i7 CompactPCI

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Internal Connectors

Expansion Interface Header J-EXP

1 2

1.27mm

Socket

40

J-EXPT (J-EXPB optinal)

GND

PCI_CLK (33MHz)

LPC_AD0

LPC_AD2

5

7

1

3

LPC_FRM#

GND

SERIRQ

EXP_SMI#

FWH_ID0 17

PCH_RCIN# 19

GND

USB_EXP_P2-

USB_EXP_P2+

21

23

25

9

11

13

15

USB_EXP_OC#

EXP_SCL

2)

GND

HDA_SDOUT

HDA_RST#/CL_RST#

3)

HDA_BITCLK/CL_CLK

3)

SPEAKER

35

37

39

27

29

31

33

28

30

32

34

18

20

22

24

26

36

38

40

10

12

14

16

6

8

2

4

+3.3V

1)

PLTRST#

LPC_AD1

LPC_AD3

LPC_DRQ#

+3.3V

1)

EXP_PME#

SIO_CLK (14.3MHz)

FWH_INIT#

PCH_A20GATE

+5V

1)

USB_EXP_P1-

USB_EXP_P1+

H_DBRESET#

EXP_SDA

2)

+5V

1)

HDA_SDIN0

HDA_SYNC

HDA_SDIN1/CL_DATA

3)

+12V

4)

3)

4)

1)

2)

Power rail switched on in state S0 only.

Connected to SMBus via switch, isolated after PCI reset.

Stuffing option, default is the HDA option.

Unswitched power rail (switched on always).

The expansion interface header footprint is available on both sides of the board, top (J-EXPT) and bottom (J-EXPB). Nevertheless the bottom side connector is stuffed only on customers request.

WARNING: Neither the +3.3V pin, nor the +5V pin, nor the +12V pin are protected against a short circuit situation! This connector therefore should be used only for attachment of an expansion board.

The maximum current flowing across these pins should be limited to 2A per power rail.

© EKF -65- ekf.com

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High Speed Expansion Connector J-HSE s1 a1 b1 s10 s9 a25 b25 s18

High Speed Expansion J-HSE

GND

SATA_HSE1_TXP

3) 5)

SATA_HSE1_TXN 3) 5) a1 a2 a3

GND

SATA_HSE1_RXN 3) 5)

SATA_HSE1_RXP

3) 5)

GND

SATA_HSE2_TXP

4) 5) 6)

SATA_HSE2_TXN

4) 5) 6)

GND

SATA_HSE2_RXN

4) 5) 6)

SATA_HSE2_RXP 4) 5) 6)

GND

USB_HSE1_P

USB_HSE1_N

GND

USB_HSE2_P

USB_HSE2_N

GND

USB_HSE1_OC#

USB_HSE2_OC#

+3.3VS

1)

+3.3VS

1)

+3.3VA

2)

+12VA

2) a20 a21 a22 a23 a24 a25 a13 a14 a15 a16 a17 a18 a19 a8 a9 a10 a11 a12 a4 a5 a6 a7 b20 b21 b22 b23 b24 b25 b13 b14 b15 b16 b17 b18 b19 b4 b5 b6 b7 b1 b2 b3 b8 b9 b10 b11 b12

GND

SATA_HSE3_TXP

4) 5) 6)

SATA_HSE3_TXN 4) 5) 6)

GND

SATA_HSE3_RXN 4) 5) 6)

SATA_HSE3_RXP

4) 5) 6)

GND

SATA_HSE4_TXP

3) 5) 6)

SATA_HSE4_TXN

3) 5) 6)

GND

SATA_HSE4_RXN

3) 5) 6)

SATA_HSE4_RXP 3) 5) 6)

GND

USB_HSE3_P

USB_HSE3_N

GND

USB_HSE4_P

USB_HSE4_N

GND

USB_HSE34_OC#

USB_HSE34_OC#

+5VS

1)

+5VS

1)

+5VA

2)

RSVD

3)

4)

1)

2)

5)

6)

Power rail switched on in state S0 only.

Power rail switched on with system power.

This SATA channel is derived from the PCH.

This SATA channel is derived from the JMB362.

All TX/RX designations with respect to SATA controller.

The SATA Port assignment PCH/JMB362 has been changed in Revision 1 of PC1-GROOVE.

WARNING: Neither the +3.3V pins, nor the +5V pins, nor the +12VA pin are protected against a short circuit situation! This connector therefore should be used only for attachment of the C40-SCFA adapter or an expansion board. The maximum current flowing across these pins should be limited to

2A per power rail.

© EKF -66- ekf.com

User Guide • PC1-GROOVE • Core

TM

i7 CompactPCI

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CPU Board

C47-MSATA • mSATA Mezzanine Module Based on HSE Connector

C48-M2 • M.2 Mezzanine Module Based on HSE Connector

© EKF -67- ekf.com

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i7 CompactPCI

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CPU Board

PCI Express Expansion Header J-PCIE

27

29

31

33

17

19

21

23

25

35

37

39

9

11

13

15

5

7

1

3

GND

+5V

1)

+5V

1)

GND

J-PCIE

GND

PE_3TP

PE_3TN

GND

PE_4TP

PE_4TN

GND

PE_CLKP

PE_CLKN

GND

PE_1TP

PE_1TN

GND

GND

PE_2TP

PE_2TN

28

30

32

34

18

20

22

24

26

36

38

40

10

12

14

16

6

8

2

4

PE_1RN

GND

GND

PE_2RP

PE_2RN

GND

PE_3RP

PE_3RN

GND

GND

+3.3V

1)

+3.3V

1)

GND

PLTRST#

PE_WAKE#

GND

PE_1RP

PE_4RP

PE_4RN

GND

1)

Power rail switched on in state S0 only.

WARNING: Neither the +3.3V pin, nor the +5V pin are protected against a short circuit situation!

The maximum current flowing across these pins should be limited to 2A per power rail.

© EKF -68- ekf.com

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i7 CompactPCI

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SDVO2 Expansion Header J-SDVO2

J-SDVO2

GND

SDVO_RED+

SDVO_RED-

GND

SDVO_GREEN+

SDVO_GREEN-

GND

SDVO_BLUE+

SDVO_BLUE-

GND

GND

DP_LANE0(P)

DP_LANE0(N)

GND

DP_LANE1(P)

DP_LANE1(N)

GND

DP_LANE2(P)

DP_LANE2(N)

GND

24

26

28

30

32

18

20

22

34

36

38

40

8

10

12

14

16

2

4

6

23

25

27

29

31

17

19

21

33

35

37

39

11

13

7

9

15

1

3

5

GND

SDVO_CLK+

SDVO_CLK-

GND

SDVO_INT+

SDVO_INT-

GND

SDVO_CTR_CLK

SDVO_CTR_DATA

GND

GND

DP_LANE3(P)

DP_LANE3(N)

GND

DP_AUX(P)

DP_AUX(N)

GND

DP_HDP

DP_CDATA

GND

A suitable mating strip line PCB must be used, depending whether the DVI or DisplayPort video output is provided on the particular mezzanine side card. With respect to the CCO-CONCERT (DVI) the C26 intermediate PCB must be used. For the PCS-BALLET (DisplayPort) however, the C66 spacer card is required.

C26 use with

CCO-CONCERT (DVI)

C66 use with

PCS-BALLET (DP)

© EKF -69- ekf.com

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i7 CompactPCI

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CPU Board

Front Panel Handle Microswitch Header P-FPH

The jumper P-FPH is used to perform power button events. By default P-FPH is connected with a short cable to a micro switch located within the front panel handle. The switch performs power button events by short-circuiting the pins 1 and 3 of P-FPH.

1

© EKF 276.02.003.11 ekf.com

1=PWRBTN# 2=NC 3=GND

P-FPH

© EKF -70- ekf.com

User Guide • PC1-GROOVE • Core

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i7 CompactPCI

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CPU Board

PLD Programming Header P-ISP

1

240.1.08.ISP

© EKF ekf.com

1=3.3V 2=TDO 3=TDI 4=NC

5=KEY 6=TMS 7=GND 8=TCK

P-ISP

Note: P-ISP is not stuffed. Its footprint is situated at the bottom side of the board.

Processor Debug Header XDP1

6

7

4

5

8

1

2

3

9

10

11

12

PREQ#

PRDY#

GND

OBSDATA0 (NC)

OBSDATA1 (NC)

GND

OBSDATA2 (NC)

OBSDATA3 (NC)

XDP1

BCLKN/HOOK5

VCC

RST#/HOOK6

DBR#/HOOK7

GND

TDO

TRST#

TDI

GND

PWRGD/HOOK0

HOOK2 (NC)

BCLKP/HOOK4

TMS

TCK1 (NC)

GND

TCK

16

17

18

19

20

13

14

15

21

22

23

24

Note: XDP1 is not stuffed. Its footprint is situated at the bottom side of the board.

© EKF -71- ekf.com

CompactPCI J1

User Guide • PC1-GROOVE • Core

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i7 CompactPCI

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13

12

11

18

17

16

15

14

21

20

19

24

23

22

5

4

3

2

1

8

7

10

9

6

J1

25

A

5V

AD1

3.3V

AD7

3.3V

AD12

3.3V

SERR#

1)

3.3V

DEVSEL#

1)

3.3V

B

REQ64#

2)

5V

AD4

GND

AD9

GND

AD15

GND

IPMB SCL

4)

GND

FRAME# 1)

C

ENUM#

1)

V(I/O)

AD3

3.3V

AD8

V(I/O)

AD14

3.3V

IPMB SDA

4)

V(I/O)

IRDY# 1)

KEY AREA

D

3.3V

AD0

5V

AD6

GND/M66EN

3)

AD11

GND

PAR

GND

STOP#

1)

BD_SEL# 7)

AD18

AD21

C/BE3#

AD26

AD30

REQ#

1)

BRSVP1A5

5)

IPMB PWR

INTA#

1)

TCK

5)

5V

AD17

GND

GND

GND

AD29

GND

BRSVP1B5

5)

GND

INTB#

1)

5V

-12V 6)

AD16

3.3V

AD23

V(I/O)

AD28

3.3V

RST#

V(I/O)

INTC#

1)

TMS

5)

TRST#

5)

GND

AD20

GND

AD25

GND

CLK

GND

INTP 1)

5V

TDO

5)

+12V

C/BE2#

AD19

AD22

AD24

AD27

AD31

GNT#

INTS 1)

INTD#

1)

TDI

5)

5V

4)

5)

2)

3)

6)

7)

1) This pin is pulled up with 1kS to V(I/O). Other pull up resistor values (e.g. 2.7kS for V(I/O)=+3.3V) are available on request.

This pin is not used on PC1-GROOVE, but pulled up with 1kS to V(I/O). Other pull up resistor values on request.

This pin is fixed to GND on PC1-GROOVE to force 33MHz operation since 66MHz operation is not supported.

This pin is pulled up with 3.0k to J1 pin A4.

This pin is not connected.

This pin is connected to a decoupling capacitor only and not used on PC1-GROOVE.

This pin is connected to power sequencing logic and should pulled low for normal operation.

E

5V

ACK64#

2)

AD2

AD5

C/BE0#

AD10

AD13

C/BE1#

PERR#

1)

LOCK#

1)

TRDY# 1)

© EKF -72- ekf.com

User Guide • PC1-GROOVE • Core

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i7 CompactPCI

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CompactPCI J2 (PlusIO)

This connector is a high speed UHM connector, suitable for Gigabit Serial I/O

Refer also to PICMG® 2.30 CompactPCI® PlusIO Specification

J2

22

21

20

19

A

GA4

2)

CLK6

CLK5

GND

2_ETH_D+

BRSVP2A18

2_ETH_D-

BRSVP2A17

4_PE_CLK-

BRSVP2A16

4_PE_CLK+

BRSVP2A15

3_PE_CLK-

AD35

3_PE_CLK+

AD38

1)

4_PE_RX00+

AD42

4_PE_RX00-

AD45

3_PE_RX00+

AD49

3_PE_RX00-

AD52

2_PE_RX00+

AD56

2_PE_RX00-

AD59

1_PE_RX00+

AD63

1_PE_RX00-

C/BE5#

V(I/O)

B

GA3

2)

GND

GND

GND

C

GA2

2)

2_ETH_B+

RSV

2_ETH_B-

RSV

2_ETH_A+

RSV

2_ETH_A-

BRSVP2C18

PRST#

1)

D

GA1

2)

1_ETH_D+

RSV

1_ETH_D-

GND

1_ETH_C+

RSV

1_ETH_C-

GND

REQ6#

1)

E

GA0

2)

1_ETH_B+

RSV

1_ETH_B-

RSV

1_ETH_A+

RSV

1_ETH_A-

BRSVP2E18

GNT6#

18

17

16

15

14

13

12

11

10

9

8

7

6

5

4

3

2

1

CLK4

CLK2

CLK1

2_ETH_C+

BRSVP2B18

2_ETH_C-

GND

2_PE_CLK+

BRSVP2B16

2_PE_CLK-

GND

1_PE_CLK+

AD34

1_PE_CLK-

GND

1_PE_CLKE#

AD41

4_PE_TX00+

GND

4_PE_TX00-

AD48

3_PE_TX00+

GND

3_PE_TX00-

AD55

2_PE_TX00+

GND

2_PE_TX00-

AD62

1_PE_TX00+

64EN#

1_PE_TX00-

BRSVP2B4

GND

CLK3

GND

DEG#

1)

FAL# 1)

2_USB2+

V(I/O)

2_USB2-

AD61

1_USB2+

V(I/O)

1_USB2-

C/BE7#

GNT3#

SYSEN# 3)

REQ1#

1)

4_PE_CLKE#

AD33

3_PE_CLKE#

V(I/O)

2_PE_CLKE#

AD40

4_USB2+

V(I/O)

4_USB2-

AD47

3_USB2+

V(I/O)

3_USB2-

AD54

GND

REQ5# 1)

2_SATA_TX+

AD58

2_SATA_TX-

GND

1_SATA_TX+

C/BE4#

1_SATA_TX-

GND

REQ4#

1)

GNT2#

GNT1#

SATA_SCL

GND

SATA_SDO

AD37

SATA_SDI 2)

GND

4_SATA_TX+

AD44

4_SATA_TX-

GND

3_SATA_TX+

AD51

3_SATA_TX-

GND

reserved

2)

BRSVP2E16

GNT5#

2_SATA_RX-

AD57

1_SATA_RX+

AD60

1_SATA_RX-

PAR64

reserved

2)

C/BE6#

GNT4#

REQ3# 1)

REQ2#

1) reserved 2)

AD32

SATA_SL

AD36

4_SATA_RX+

AD39

4_SATA_RX-

AD43

3_SATA_RX+

AD46

3_SATA_RX-

AD50

2_SATA_RX+

AD53

4)

5)

2)

3)

1)

This pin is pulled up with 1kS to V(I/O). Alternate pull up resistor values (e.g. 2.7kS for V(I/O)=+3.3V) are available on request.

This pin is not connected.

This pin is pulled up with 10kS to +3.3V.

Pin positions printed italic: 64-bit system slot signals (for reference only).

Pin positions printed blue: PlusIO options.

© EKF -73- ekf.com

User Guide • PC1-GROOVE • Core

TM

i7 CompactPCI

®

CPU Board f e d c b a

25 f e d c b a

22

1 1

J2 UHM (Top)

J1 (Bottom)

© EKF -74- ekf.com

User Guide • PC1-GROOVE • Core

TM

i7 CompactPCI

®

CPU Board

Appendix

Mechanical Drawings

The following drawing shows the positions of mounting holes and expansion connectors on the

PC1-GROOVE.

100.00

94.50

93.50

7.00

J-HSE

J-SDVO2

PC1-GROOVE

© EKF • ekf.com

J-EXP

J-PCIE

5.50

© EKF -75- ekf.com

User Guide • PC1-GROOVE • Core

TM

i7 CompactPCI

®

CPU Board

Small Industrial Systems

Small Industrial Systems

© EKF -76- ekf.com

User Guide • PC1-GROOVE • Core

TM

i7 CompactPCI

®

CPU Board

Rugged Industrial Systerms

Rugged Industrial Systems

© EKF -77- ekf.com

User Guide • PC1-GROOVE • Core

TM

i7 CompactPCI

®

CPU Board

Full Size Industrial System

Custom Specific System

© EKF -78- ekf.com

User Guide • PC1-GROOVE • Core

TM

i7 CompactPCI

®

CPU Board

C40-SCFA CompactFlash Module

C41-CFAST CFast Module

© EKF -79- ekf.com

User Guide • PC1-GROOVE • Core

TM

i7 CompactPCI

®

CPU Board

C42-SATA 1.8-Inch Micro SATA Module

C43-SATA Internal SATA Connector Module

© EKF -80- ekf.com

User Guide • PC1-GROOVE • Core

TM

i7 CompactPCI

®

CPU Board

C47-MSATA Dual mSATA SSD Module

Custom Specific Front Panel Solutions Available

© EKF -81- ekf.com

User Guide • PC1-GROOVE • Core

TM

i7 CompactPCI

®

CPU Board

PC1-GROOVE

© EKF -82- ekf.com

User Guide • PC1-GROOVE • Core

TM

i7 CompactPCI

®

CPU Board

PC1-GROOVE with C47-MSATA RAID Storage Mezzanine Module

© EKF -83- ekf.com

User Guide • PC1-GROOVE • Core

TM

i7 CompactPCI

®

CPU Board

PC1-GROOVE • PCS-BALLET Side Card (8HP Assembly)

PC1-GROOVE • PCS-BALLET Side Card (12HP Assembly)

© EKF -84- ekf.com

User Guide • PC1-GROOVE • Core

TM

i7 CompactPCI

®

CPU Board

PC1-GROOVE w. PCS-BALLET Side Card & C42-SATA Mezzanine

© EKF -85- ekf.com

User Guide • PC1-GROOVE • Core

TM

i7 CompactPCI

®

CPU Board

PC1-GROOVE w. PCS-BALLET Side Card & C47-MSATA Mezzanine

© EKF -86- ekf.com

User Guide • PC1-GROOVE • Core

TM

i7 CompactPCI

®

CPU Board

EKF Elektronik GmbH

Philipp-Reis-Str. 4 (Haus 1)

Lilienthalstr. 2 (Haus 2)

59065 HAMM

Germany

Industrial Computers Made in Germany boards. systems. solutions.

Phone +49 (0)2381/6890-0

Fax +49 (0)2381/6890-90

Internet www.ekf.com

E-Mail [email protected]

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