Intel® 82580EB/82580DB Gigabit Ethernet Controller Datasheet

Intel® 82580EB/82580DB Gigabit Ethernet Controller Datasheet
Intel® 82580EB/82580DB Gigabit
Ethernet Controller Datasheet
LAN Access Division (LAD)
FEATURES
External Interfaces Provided:
•
PCIe v2.0 (5Gbps and 2.5Gbps) x4/x2/x1; called PCIe in
this document.
•
MDI (Copper) standard IEEE 802.3 Ethernet interface for
1000BASE-T, 100BASE-TX, and 10BASE-T applications
(802.3, 802.3u, and 802.3ab)
•
Serializer-Deserializer (SERDES) to support 1000Base-SX/
LX (optical fiber)
•
Serializer-Deserializer (SERDES) to support 1000BASE-KX
and 1000BASE-BX for Gigabit backplane applications
•
SGMII interface for SFP/external PHY connections
•
NC-SI or SMBus for Manageability connection to MC
•
IEEE 1149.6 JTAG
Performance Enhancements:
iSCSI*, PXE* and UEFI* Preboot Support
•
iSCSI - SerDes, Fiber and Copper in Windows/Linux. SGMII is
not currently supported.
•
PXE - SerDes, Fiber, Copper, SGMII in Windows /Linux.
•
UEFI - SerDes, Fiber, Copper, SGMII in Windows/Linux.
Power Saving Features:
•
Advanced Configuration and Power Interface (ACPI) power
management states and wake-up capability
•
Advanced Power Management (APM) wake-up functionality
•
Low power link-disconnect state
•
PCIe v2.1 LTR (Latency Tolerance Reporting)
•
DMA Coalescing for improved system power management
•
Intel® I/O Acceleration Technology v3.0 supported:
•
Stateless offloads (Header split, RSS)
•
Direct Cache Access
IEEE802.1AS - Timing and Synchronization:
• IEEE 1588 Precision Time Protocol support
• Per-packet timestamp
•
PCIe v2.1 TLP Processing Hints (TPH)
Total Cost Of Ownership (TCO):
•
UDP, TCP and IP Checksum offload
•
UDP and TCP Transmit Segmentation Offload (TSO)
•
SCTP receive and transmit checksum offload
Virtualization Ready:
•
Enhanced VMDq1 support:
•
Queues per port: 8 TX and 8 RX queues
•
Support of up to 8 VMs per port (1 queue allocated to each
VM)
•
IPMI MC pass-thru; multi-drop NC-SI
Additional Product Details:
•
17x17 PBGA package
•
Estimated power: 2.8W (max) in dual port mode and 4.2W
(max) in quad port mode
•
Full data path Parity or ECC protection
Revision: 2.50
October 2011
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*Other names and brands may be claimed as the property of others.
Copyright © 2009, 2010, 2011; Intel Corporation. All Rights Reserved.
Legal Lines and Disclaimers
Intel® 82580EB/82580DB Gigabit Ethernet Controller
Datasheet
2
Revision: 2.50
October 2011
Revisions — Intel® 82580EB/82580DB GbE Controller
Revisions
Rev
Date
Notes
0.30
Dec 2008
Initial public release of early materials.
0.31
Jan 2009
Chapter 2.0. Signals connected to the E14, F14, N12, R1, R2 and T1 corrected
according to the latest ballout.
Section 10.4. Updated power consumption estimates.
Table 10-21. Corrected packaging information in the table. Now listed
consistently as 17x17 PBGA package.
0.5
2 April 2009
Updated EAS source used as base.
1.0
12 June 2009
Updated design information chapter added; supports Samples.
1.1
1 Oct 2009
Editorial Changes.
1.2
23 Oct 2009
Chapter 12.0, Design Guidelines - 1.9V is no longer needed at the center tap.
Language expressing that requirement has been removed.
Figure 10-1 and Table 10-3 updated to correct errors.
1.3
2.0
5 Jan 2010
15 Jan 2010
•
New EAS core added to Datasheet text.
•
Datasheet title updated to reflect dual and quad core capabilities.
•
Datasheet title changed to cover. ‘Dual’ added.
•
Section 1.0, Introduction language updated to indicate dual core support.
•
Table 2-7, SERDES/SGMII Pins updated; now includes dual port
exclusions. See asterisks.
•
Table 2-8, SFP Pins updated; now includes dual port exclusions. See
asterisks.
•
Table 2-9, LED Output Pins updated; now includes dual port exclusions.
See asterisks.
•
Table 2-10, Analog Pins updated; now includes dual port exclusions. See
asterisks.
•
Table 2-11, Testability Pins updated; now includes dual port exclusions.
See asterisks.
•
Table 2-15, Pin List in Alphabetical Order updated; now summarizes all
dual port exclusions. See asterisks.
•
Table 4-4, PCI Functions Mapping (Legacy Mode) updated; information
expanded.
•
Table 6-1, EEPROM Top Level Partitioning updated; now includes dual port
exclusions. See asterisks.
•
Section 8.8.2.4, Size Filtering added.
•
Figure 12-4, Recommended Crystal Placement and Layout on page 720
updated.
•
Chapter 13.0, Thermal Management - Thermal management chapter
added. added.
2.1
15 Jan 2010
•
Test data updated.
2.2
26 Feb 2010
•
Figure 12-5, Oscillator Solution on page 721 updated.
2.3
Revision: 2.50
October 2011
5 Mar 2010
•
Table 12-3, Oscillator Manufacturers and Part Numbers updated.
•
Confidential stamp removed from document for posting on Developer.
•
In Section 13.4.4, Package Thermal Characteristics ; Table 13-3 and Table
13-3 have been provided with updated data.
•
Appendix A., Changes from the 82576; this appendix was added to the
Datasheet.
Intel® 82580EB/82580DB Gigabit Ethernet Controller
Datasheet
3
Intel® 82580EB/82580DB GbE Controller — Revisions
Rev
Date
2.4
29 Mar 2010
2.41
25 Jun 2010
Notes
•
In Section 6.2.5, Device ID (LAN Base Address + Offset 0x0D), the device
ID was indicated as TBD because of a poorly set build variable. That has
been corrected (Device ID = 1509).
•
In Section 11.3.2.1.2, Request Status Command, the descriptive
paragraph has been updated for clarity.
•
In Section 10.7.1, Mechanical; ball, solder, and pad information has been
added to the section.
New sections:
•
Section 11.3.2.4, Filtering Over SMBus
•
Section 11.3.2.4.5, SMBus Troubleshooting
Updated.
2.42
7 Jul 2010
•
Section 8.2.5.3, SCTP CRC Offloading updated. Note added: “Software
must initialize the SCTP CRC field to zero (0x00000000) prior to
requesting a CRC calculation offload.”
•
Table 10-14, I2C Timing Parameters updated. See THD:DAT .
The PCIe PHY Auto Configuration Pointer is not supported. The discussion of
this capability has been removed from the datasheet.
Two EEPROM registers exposed:
2.43
2.44
20 Aug 2010
9/16/2010
•
Section 6.2.14, PCIe Init Configuration 1 (Word 0x18)
•
Section 6.2.15, PCIe Init Configuration 2 Word (Word 0x19)
•
Section 6.2.16, PCIe Init Configuration 3 Word (Word 0x1A)
Updated:
•
Table 2-13, Pull-Up Resistors. For NCSI_CRS_DV change Note 2 to Note
1. For NCSI_TXD[1:0] changed PD to PU.
•
Section 6.11.5, PBA Number Module (Word 0x08, 0x09). This field has
been updated. Its format has been changed.
•
Section 10.3.1, Power Supply Specification. Value for Max Decoupling
Capacitance changed to N/A..
•
Section 10.6.6, Oscillator Support. Information on this topic is now in
Section 12.5.
Updated:
•
2.45
10/13/2010
Intel® 82580EB/82580DB Gigabit Ethernet Controller
Datasheet
4
Section 6.11.5, PBA Number Module (Word 0x08, 0x09). Language
updated to address questions about final format.
In the 2.44 build, the link to the Appendix did not appear in the PDF. This build
fixes the issue. Also updated legal section.
Revision: 2.50
October 2011
Revisions — Intel® 82580EB/82580DB GbE Controller
Rev
Date
2.46
3/23/2011
Notes
•
Updated document title to better reflect brand string.
•
Table 3-9, Allocation of FC Credits. First row cell text changed. Changed
to: “Sixteen credit units to support tail write at wire speed.”
•
Section 6.11.1, Compatibility (Word 0x03). Word description updated.
•
Section 6.11.2, Port Identification LED blinking (Word 0x04). Word
description updated.
•
Section 6.11.6.1, Setup Options PCI Function 0 (Word 0x30). Bits 2:0
redefined.
•
Section 8.2.2.3.9, PAYLEN (18). Note text updated.
•
Section 7.12.16, Tx Descriptor Completion Write–Back Address Low TDWBAL (0xE038 + 0x40*n [n=0...7]; R/W). 32:2 bit description
updated.
•
Section 7.22.4, Management Control Register - MANC (0x5820; RW). Bit
expression (20:2019) a typo. Corrected to 20:19.
•
Table 10-24, Discrete/Integrated Magnetics Specifications. Added table,
section with complete information on magnetics.
•
Section 12.4.1.6, Load Capacitance. Text updated (formula corrected).
2.47
4/6/2011
•
Section 10.7.4, Package Schematics. Figure updated. Extraneous circle
removed.
2.48
5/10/2011
•
Section 6.11.2, Port Identification LED blinking (Word 0x04). Text in
section updated to better describe behavior.
2.49
8/22/2011
•
Table 6-2; 0x23 link fixed.
•
Section 7.5.5, Flow Control Receive Threshold Low - FCRTL0 (0x2160; R/
W). Phrase changed: “1b (at least 16 bytes)” to “3b (at least 48 bytes)”.
•
Table 11-2: In third row, existing text the existing text: "Supports counter
2 and also supports the following counters only when the OS is down: 1,
6, 7" has been changed to: "Supports the following counters: 1, 2, 6, 7.
•
Section 13.2, Note added at end of section: “For the 82580EB/DB, Tjmax
is calculated at 123 C.”
Revision: 2.50
October 2011

Intel® 82580EB/82580DB Gigabit Ethernet Controller
Datasheet
5
Intel® 82580EB/82580DB GbE Controller — Revisions
Rev
Date
2.50
10/20/2011
Intel® 82580EB/82580DB Gigabit Ethernet Controller
Datasheet
6
Notes
•
More Preboot data added to feature summary on page 1.
•
Section 1.4.2, Network Interfaces. Note added. States that old MDI flipchip option not supported.
•
Section 1.4.3, EEPROM Interface. Note on EEPROMless support added.
States clearly that EEPROMless mode is not supported.
•
Section 1.4.5, SMBus Interface. Statement added. Makes performance
requirement clear: “For best performance, each 82580EB/DB should have
its own dedicated SMBus link to the SMBus master device.”
•
Section 1.6.12.2, Time SYNC (IEEE1588 and IEEE 802.1AS). Statement
added. Clearly defines the limited nature of 1588 support.
•
Table 2-6, Miscellaneous Pins. Note added to TSENSP; Note states limits
of TSENSP/Z use. Refers to thermal chapter.
•
Table 2-10, Analog Pins. Error corrected. RSVD_TX_TCLK clock speed
indicated as 125 MHz instead of 1.25 MHz.
•
Section 2.5, Pin List (Alphabetical), Section 2.6, Ball-Out. Note added.
Makes clear statement about proper handling for ‘unused pins’.
•
Section 6.2.15, PCIe Init Configuration 2 Word (Word 0x19). Note added
to IO_Sup, bit14. The note defines ‘disable I/O mode’.
•
Section 6.2.22, Functions Control (Word 0x21), bit 9 description; Section
9.4.11.2, 64-bit BARs Mode Mapping, bit 3 description. Description has
been changed. New text for both: “This bit should be set only on systems
that do not generate prefetchable cycles.”
•
Table 7-10, Usable FLASH Size and CSR Mapping Window Size. Table
added to Datasheet.
•
Section 10.3, Power Delivery. Sentence added. Makes the following clear
statement about power delivery: “The device requires the following power
supplies: 3.3v, 1.8v, 1.0v. All 82580EB/DB power should be derived from
AUX power.”
Revision: 2.50
October 2011
Contents — Intel® 82580EB/82580DB GbE Controller
Contents
1.0
1.1
1.2
1.3
1.4
1.5
1.6
1.7
2.0
2.1
2.2
2.3
2.4
2.5
2.6
3.0
3.1
3.2
3.3
Introduction..............................................................................................................................19
Scope ....................................................................................................................................... 20
Terminology and Acronyms .......................................................................................................... 20
1.2.1
External Specification and Documents............................................................................ 21
Product Overview ....................................................................................................................... 22
External Interface ....................................................................................................................... 23
1.4.1
PCIe Interface ............................................................................................................ 23
1.4.2
Network Interfaces...................................................................................................... 23
1.4.3
EEPROM Interface ....................................................................................................... 23
1.4.4
Serial Flash Interface .................................................................................................. 23
1.4.5
SMBus Interface ......................................................................................................... 24
1.4.6
NC-SI Interface .......................................................................................................... 24
1.4.7
MDIO/I2C 2 wires Interfaces......................................................................................... 24
1.4.8
Software-Definable Pins (SDP) Interface (General-Purpose I/O) ........................................ 24
1.4.9
LEDs Interface............................................................................................................ 25
Features.................................................................................................................................... 25
Overview of Changes Compared to the 82576 ................................................................................ 28
1.6.1
Network Interface ....................................................................................................... 28
1.6.2
HOST Interface........................................................................................................... 29
1.6.3
Boundary Scan ........................................................................................................... 30
1.6.4
Performance Features.................................................................................................. 30
1.6.5
Receive and Transmit Queues....................................................................................... 30
1.6.6
Virtualization.............................................................................................................. 31
1.6.7
Malicious Driver Detection ............................................................................................ 31
1.6.8
2-tuple filtering .......................................................................................................... 31
1.6.9
Security Offload.......................................................................................................... 31
1.6.10
Quality of Service ....................................................................................................... 32
1.6.11
Manageability ............................................................................................................. 32
1.6.12
Embedded Features .................................................................................................... 33
1.6.13
Power Saving ............................................................................................................. 34
Device Data Flows ...................................................................................................................... 35
1.7.1
Transmit Data Flow ..................................................................................................... 35
1.7.2
Receive Data Flow....................................................................................................... 35
Pin Interface .............................................................................................................................37
Pin Assignment .......................................................................................................................... 37
2.1.1
PCIe ......................................................................................................................... 37
2.1.2
Flash and EEPROM Ports ............................................................................................. 38
2.1.3
System Management Bus (SMB) Interface ..................................................................... 39
2.1.4
NC-SI Interface Pins ................................................................................................... 39
2.1.5
Miscellaneous Pins ..................................................................................................... 40
2.1.6
SERDES/SGMII Pins ................................................................................................... 41
2.1.7
SFP Pins ................................................................................................................... 43
2.1.8
PHY Pins .................................................................................................................... 44
2.1.9
Testability Pins .......................................................................................................... 48
2.1.10
Power Supply and Ground Pins ................................................................................... 50
Pullups/Pulldowns ....................................................................................................................... 50
Strapping .................................................................................................................................. 53
Interface Diagram....................................................................................................................... 54
Pin List (Alphabetical).................................................................................................................. 55
Ball-Out .................................................................................................................................... 57
Interconnects............................................................................................................................59
PCIe ......................................................................................................................................... 59
3.1.1
PCIe Overview............................................................................................................ 59
3.1.2
Functionality - General ................................................................................................ 61
3.1.3
Host Interface ............................................................................................................ 62
3.1.4
Transaction Layer ....................................................................................................... 65
3.1.5
Data Link Layer .......................................................................................................... 72
3.1.6
Physical Layer ............................................................................................................ 74
3.1.7
Error Events and Error Reporting .................................................................................. 77
3.1.8
PCIe Power Management ............................................................................................. 81
3.1.9
PCIe Programming Interface......................................................................................... 81
Management Interfaces ............................................................................................................... 82
3.2.1
SMBus....................................................................................................................... 82
3.2.2
NC-SI........................................................................................................................ 91
Flash / EEPROM .......................................................................................................................... 92
3.3.1
EEPROM Interface ....................................................................................................... 92
3.3.2
Shared EEPROM.........................................................................................................100
3.3.3
Vital Product Data (VPD) Support .................................................................................101
3.3.4
Flash Interface ..........................................................................................................102
3.3.5
Shared FLASH ...........................................................................................................104
Revision: 2.50
October 2011
Intel® 82580EB/82580DB Gigabit Ethernet Controller
Datasheet
7
Intel® 82580EB/82580DB GbE Controller — Contents
3.4
3.5
4.0
4.1
4.2
4.3
4.4
4.5
4.6
4.7
5.0
5.1
5.2
5.3
5.4
5.5
5.6
5.7
Configurable I/O Pins ................................................................................................................ 105
3.4.1
General-Purpose I/O (Software-Definable Pins) ............................................................. 105
3.4.2
Software Watchdog ................................................................................................... 105
3.4.3
LEDs ....................................................................................................................... 106
Network Interfaces ................................................................................................................... 107
3.5.1
Overview ................................................................................................................. 107
3.5.2
MAC Functionality ..................................................................................................... 108
3.5.3
SerDes/1000BASE-BX, SGMII and 1000BASE-KX Support .............................................. 111
3.5.4
Auto-Negotiation and Link Setup Features .................................................................... 113
3.5.5
Ethernet Flow Control (FC) ......................................................................................... 120
3.5.6
Loopback Support ..................................................................................................... 125
3.5.7
Integrated Copper PHY Functionality............................................................................ 128
3.5.8
Media Auto Sense ..................................................................................................... 145
Initialization ...........................................................................................................................149
Power Up................................................................................................................................. 149
4.1.1
Power-Up Sequence .................................................................................................. 149
4.1.2
Power-Up Timing Diagram.......................................................................................... 150
Reset Operation........................................................................................................................ 151
4.2.1
Reset Sources .......................................................................................................... 151
Software Reset ......................................................................................................................... 152
4.3.1
Port Software Reset (RST).......................................................................................... 152
4.3.2
Device Software Reset (DEV_RST) .............................................................................. 152
4.3.3
Reset Effects ............................................................................................................ 156
4.3.4
PHY Behavior During a Manageability Session ............................................................... 160
Function Disable ....................................................................................................................... 161
4.4.1
General ................................................................................................................... 161
4.4.2
Overview ................................................................................................................. 161
4.4.3
Control Options ........................................................................................................ 163
4.4.4
Event Flow for Enable/Disable Functions....................................................................... 164
Device Disable.......................................................................................................................... 165
4.5.1
BIOS Handling of Device Disable ................................................................................. 166
Software Initialization and Diagnostics......................................................................................... 166
4.6.1
Introduction ............................................................................................................. 166
4.6.2
Power Up State......................................................................................................... 166
4.6.3
Initialization Sequence............................................................................................... 167
4.6.4
Interrupts During Initialization .................................................................................... 167
4.6.5
Global Reset and General Configuration ....................................................................... 167
4.6.6
Flow Control Setup.................................................................................................... 167
4.6.7
Link Setup Mechanisms and Control/Status Bit Summary ............................................... 168
4.6.8
Initialization of Statistics ............................................................................................ 172
4.6.9
Receive Initialization ................................................................................................. 173
4.6.10
Transmit Initialization ................................................................................................ 174
4.6.11
Virtualization Initialization Flow................................................................................... 175
Access to shared resources ........................................................................................................ 176
4.7.1
Acquiring ownership over a shared resource ................................................................. 177
4.7.2
Releasing ownership over a shared resource ................................................................. 177
4.7.3
Software to Software Mailbox ..................................................................................... 179
Power Management.................................................................................................................181
General Power State Information ................................................................................................ 181
5.1.1
PCI Device Power States ............................................................................................ 181
5.1.2
PCIe Link Power States .............................................................................................. 182
Power States............................................................................................................................ 182
5.2.1
D0 Uninitialized State (D0u) ....................................................................................... 183
5.2.2
D0active State.......................................................................................................... 184
5.2.3
D3 State (PCI-PM D3hot) ........................................................................................... 184
5.2.4
Dr State (D3cold) ..................................................................................................... 186
5.2.5
Link Disconnect ........................................................................................................ 187
5.2.6
Device Power-Down State .......................................................................................... 188
Power Limits by Certain Form Factors .......................................................................................... 188
Interconnects Power Management............................................................................................... 189
5.4.1
PCIe Link Power Management ..................................................................................... 189
5.4.2
NC-SI Clock Control .................................................................................................. 191
5.4.3
Internal PHY Power-Management ................................................................................ 191
Timing of Power-State Transitions ............................................................................................... 191
5.5.1
Power Up (Off to Dup to D0u to D0a ............................................................................ 192
5.5.2
Transition from D0a to D3 and Back Without PE_RST_N ................................................. 193
5.5.3
Transition From D0a to D3 and Back With PE_RST_N ..................................................... 194
5.5.4
Transition From D0a to Dr and Back Without Transition to D3 ......................................... 195
Wake Up ................................................................................................................................. 196
5.6.1
Advanced Power Management Wake Up ....................................................................... 196
5.6.2
PCIe Power Management Wake Up .............................................................................. 197
5.6.3
Wake-Up Packets ...................................................................................................... 198
DMA Coalescing ........................................................................................................................ 203
5.7.1
Entering DMA Coalescing Operating Mode..................................................................... 204
Intel® 82580EB/82580DB Gigabit Ethernet Controller
Datasheet
8
Revision: 2.50
October 2011
Contents — Intel® 82580EB/82580DB GbE Controller
5.8
6.0
6.1
6.2
6.3
6.4
6.5
6.6
6.7
6.8
5.7.2
Conditions to Exit DMA Coalescing................................................................................205
Latency Tolerance Reporting (LTR)...............................................................................................205
5.8.1
Latency Tolerance Reporting Per Function .....................................................................208
Non-Volatile Memory Map - EEPROM .......................................................................................211
EEPROM General Map .................................................................................................................211
Hardware Accessed Words ..........................................................................................................214
6.2.1
Ethernet Address (LAN Base Address + Offsets 0x00-0x02) .............................................214
6.2.2
Initialization Control Word 1 (word 0x0A) ......................................................................215
6.2.3
Subsystem ID (Word 0x0B).........................................................................................216
6.2.4
Subsystem Vendor ID (Word 0x0C) ..............................................................................216
6.2.5
Device ID (LAN Base Address + Offset 0x0D) ................................................................216
6.2.6
Vendor ID (Word 0x0E) ..............................................................................................216
6.2.7
Dummy Device ID (Word 0x1D)...................................................................................216
6.2.8
Initialization Control Word 2 (Word 0x0F)......................................................................216
6.2.9
EEPROM Sizing and Protected Fields (Word 0x12)...........................................................217
6.2.10
Initialization Control 4 (LAN Base Address + Offset 0x13)................................................219
6.2.11
PCIe L1 Exit latencies (Word 0x14) ..............................................................................220
6.2.12
PCIe Completion Timeout Configuration (Word 0x15)......................................................220
6.2.13
MSI-X Configuration (LAN Base Address + Offset 0x16) ..................................................221
6.2.14
PCIe Init Configuration 1 (Word 0x18) ..........................................................................221
6.2.15
PCIe Init Configuration 2 Word (Word 0x19) ..................................................................222
6.2.16
PCIe Init Configuration 3 Word (Word 0x1A)..................................................................222
6.2.17
PCIe Control 1 (Word 0x1B) ........................................................................................223
6.2.18
LED 1,3 Configuration Defaults (LAN Base Address + Offset 0x1C) ...................................223
6.2.19
Device Rev ID (Word 0x1E).........................................................................................224
6.2.20
LED 0,2 Configuration Defaults (LAN Base Address + Offset 0x1F)....................................225
6.2.21
Software Defined Pins Control (LAN Base Address + Offset 0x20) .....................................226
6.2.22
Functions Control (Word 0x21) ....................................................................................227
6.2.23
LAN Power Consumption (Word 0x22) ..........................................................................229
6.2.24
Initialization Control 3 (LAN Base Address + Offset 0x24)................................................229
6.2.25
PCIe Control 2 (Word 0x28) ........................................................................................230
6.2.26
PCIe Control 3 (Word 0x29) ........................................................................................231
6.2.27
End of Read-Only (RO) Area (Word 0x2C) .....................................................................231
6.2.28
Start of RO Area (Word 0x2D) .....................................................................................231
6.2.29
Watchdog Configuration (Word 0x2E) ...........................................................................232
6.2.30
VPD Pointer (Word 0x2F) ............................................................................................232
CSR Auto Configuration Pointer
(LAN Base Address + Offset 0x17) ...............................................................................................232
6.3.1
CSR Configuration Section Length - Offset 0x0...............................................................233
6.3.2
Block CRC8 (Offset 0x1) .............................................................................................233
6.3.3
CSR Address - (Offset 3*n - 1; [n = 1... Section Length]) ...............................................233
6.3.4
CSR Data LSB - (Offset 3*n; [n = 1... Section Length]) ..................................................233
6.3.5
CSR Data MSB - (Offset 3*n + 1; [n = 1... Section Length])............................................233
CSR Auto Configuration Power-Up Pointer
(LAN Base Address + Offset 0x27) ...............................................................................................233
6.4.1
CSR Configuration Power-Up Section Length - Offset 0x0 ................................................234
6.4.2
Block CRC8 (Offset 0x1) .............................................................................................234
6.4.3
CSR Address - (Offset 3*n - 1; [n = 1... Section Length]) ...............................................234
6.4.4
CSR Data LSB - (Offset 3*n; [n = 1... Section Length]) ..................................................234
6.4.5
CSR Data MSB - (Offset 3*n + 1; [n = 1... Section Length])............................................235
Reserved (Word 0x10) ...............................................................................................................235
Firmware Pointers and Control Words ...........................................................................................235
6.6.1
Pass Through LAN Configuration Pointer
(LAN Base Address + Offset 0x11) ...............................................................................235
6.6.2
Management HW Config Control (Word 0x23) ................................................................235
6.6.3
PHY Configuration Pointer (Word 0x50).........................................................................236
6.6.4
Firmware Patch Pointer (Word 0x51) ............................................................................236
6.6.5
Manageability Capability/Manageability Enable (Word 0x54) ............................................236
6.6.6
Sideband Configuration Pointer (Word 0x57) .................................................................237
6.6.7
Reserved (Word 0x5E)................................................................................................237
Firmware Patch Structure ...........................................................................................................237
6.7.1
Firmware Patch Data Size (Offset 0x0)..........................................................................237
6.7.2
Block CRC8 (Offset 0x1) .............................................................................................238
6.7.3
Patch Ram Address Word (Offset 0x2) ..........................................................................238
6.7.4
Patch Version 1 Word (Offset 0x3) ...............................................................................238
6.7.5
Patch Version 2 Word (Offset 0x4) ...............................................................................238
6.7.6
Patch Version 3 Word (Offset 0x5) ...............................................................................238
6.7.7
Patch Version 4 Word (Offset 0x6) ...............................................................................238
6.7.8
Patch Data Words (Offset 0x7, Block Length).................................................................239
PT LAN Configuration Structure ...................................................................................................239
6.8.1
PT LAN Configuration Structure Section Length - Offset 0x0.............................................239
6.8.2
Block CRC8 (Offset 0x1) .............................................................................................240
6.8.3
CSR Address - (Offset 2*n; [n = 1... Section Length]) ....................................................240
6.8.4
CSR Data LSB - (Offset 0x1 + 2*n; [n = 1... Section Length]) .........................................240
6.8.5
CSR Data MSB - (Offset 0x2 + 2*n; [n = 1... Section Length]) ........................................240
Revision: 2.50
October 2011
Intel® 82580EB/82580DB Gigabit Ethernet Controller
Datasheet
9
Intel® 82580EB/82580DB GbE Controller — Contents
6.9
6.10
6.11
7.0
7.1
7.2
7.3
7.4
7.5
6.8.6
Manageability Filters.................................................................................................. 240
PHY configuration Structure ....................................................................................................... 241
6.9.1
PHY Configuration Section Length - Offset 0x0 .............................................................. 241
6.9.2
Block CRC8 (Offset 0x1) ............................................................................................ 241
6.9.3
PHY Number and PHY Register Address (Offset 2*n; [n = 1... Section Length]) ........................................................................ 241
6.9.4
PHY data (Offset 2*n + 1; [n = 1... Section Length])..................................................... 242
Sideband Configuration Structure................................................................................................ 242
6.10.1
Section Length (Offset 0x0)........................................................................................ 242
6.10.2
Block CRC8 (Offset 0x1) ............................................................................................ 242
6.10.3
SMBus Max Fragment Size (Offset 0x2) ....................................................................... 242
6.10.4
SMBus Notification Timeout (Offset 0x3) ...................................................................... 243
6.10.5
SMBus Slave Address 0 1 (Offset 0x4) ......................................................................... 243
6.10.6
SMBus Slave Address 2 3 (Offset 0x5) ......................................................................... 243
6.10.7
NC-SI Configuration (Offset 0x6) ................................................................................ 243
6.10.8
Reserved (Offset 0x7 - 0x8) ....................................................................................... 243
6.10.9
SMBus Flags (Offset 0x9) ........................................................................................... 244
6.10.10
LAN Receive Enable 3 (Offset 0xA) .............................................................................. 244
6.10.11
LAN0 MANC Value LSB (Offset 0xB) ............................................................................. 245
6.10.12
LAN0 MANC Value MSB (Offset 0xC) ............................................................................ 246
6.10.13
LAN1 MANC Value LSB (Offset 0xD)............................................................................. 246
6.10.14
LAN1 MANC Value MSB (Offset 0xE) ............................................................................ 247
6.10.15
LAN2 MANC Value LSB (Offset 0xF) ............................................................................. 247
6.10.16
LAN2 MANC Value MSB (Offset 0x10) .......................................................................... 248
6.10.17
LAN3 MANC Value LSB (Offset 0x11) ........................................................................... 248
6.10.18
LAN3 MANC Value MSB (Offset 0x12) .......................................................................... 249
Software Accessed Words .......................................................................................................... 249
6.11.1
Compatibility (Word 0x03) ......................................................................................... 250
6.11.2
Port Identification LED blinking (Word 0x04)................................................................. 250
6.11.3
EEPROM Image Revision (Word 0x05).......................................................................... 251
6.11.4
OEM Specific (Word 0x06, 0x07) ................................................................................. 251
6.11.5
PBA Number Module (Word 0x08, 0x09) ...................................................................... 251
6.11.6
PXE Configuration Words (Word 0x30:3B) .................................................................... 252
6.11.7
iSCSI Boot Configuration Pointer (Word 0x3D) .............................................................. 256
6.11.8
Alternate MAC address pointer (Word 0x37) ................................................................. 258
6.11.9
Checksum Word (Offset 0x3F) .................................................................................... 258
6.11.10
Image Unique ID (Word 0x42, 0x43) ........................................................................... 258
Programming Interface ...........................................................................................................259
Introduction ............................................................................................................................. 259
7.1.1
Memory, I/O Address and Configuration Decoding ......................................................... 259
7.1.2
Register Conventions................................................................................................. 263
7.1.3
Register Summary .................................................................................................... 265
7.1.4
Alias Addresses ........................................................................................................ 275
7.1.5
MSI-X BAR Register Summary .................................................................................... 275
General Register Descriptions ..................................................................................................... 276
7.2.1
Device Control Register - CTRL (0x00000; R/W)............................................................ 276
7.2.2
Device Status Register - STATUS (0x0008; R) .............................................................. 280
7.2.3
Extended Device Control Register CTRL_EXT (0x0018; R/W) .......................................................................................... 281
7.2.4
MDI Control Register - MDIC (0x0020; R/W) ................................................................ 284
7.2.5
MDC/MDIO Configuration Register –
MDICNFG (0x0E04; R/W) ........................................................................................... 285
7.2.6
SERDES Control 0 - P1GCTRL0 (0x0E08; RW) ............................................................... 286
7.2.7
Copper/Fiber Switch Control - CONNSW (0x0034; R/W) ................................................. 286
7.2.8
VLAN Ether Type - VET (0x0038; R/W) ........................................................................ 287
7.2.9
LED Control - LEDCTL (0x0E00; RW) ........................................................................... 287
Internal Packet Buffer Size Registers ........................................................................................... 289
7.3.1
Internal Receive Packet Buffer Size - IRPBS (0x2404; RO).............................................. 289
7.3.2
Internal Transmit Packet Buffer Size - ITPBS (0x3404; RO) ............................................ 290
EEPROM/Flash Register Descriptions............................................................................................ 290
7.4.1
EEPROM/Flash Control Register - EEC (0x0010; R/W) .................................................... 290
7.4.2
EEPROM Read Register - EERD (0x0014; RW) ............................................................... 292
7.4.3
Flash Access - FLA (0x001C; R/W) .............................................................................. 293
7.4.4
Flash Opcode - FLASHOP (0x103C; R/W)...................................................................... 293
7.4.5
EEPROM Auto Read Bus Control - EEARBC (0x1024; R/W) .............................................. 294
7.4.6
VPD Diagnostic Register -VPDDIAG (0x1060; RO) ......................................................... 295
7.4.7
Management-EEPROM CSR I/F.................................................................................... 295
Flow Control Register Descriptions .............................................................................................. 296
7.5.1
Flow Control Address Low - FCAL (0x0028; RO) ............................................................ 296
7.5.2
Flow Control Address High - FCAH (0x002C; RO)........................................................... 297
7.5.3
Flow Control Type - FCT (0x0030; R/W) ....................................................................... 297
7.5.4
Flow Control Transmit Timer Value - FCTTV (0x0170; R/W) ............................................ 297
7.5.5
Flow Control Receive Threshold Low - FCRTL0 (0x2160; R/W)......................................... 298
7.5.6
Flow Control Receive Threshold High - FCRTH0 (0x2168; R/W) ....................................... 298
Intel® 82580EB/82580DB Gigabit Ethernet Controller
Datasheet
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Revision: 2.50
October 2011
Contents — Intel® 82580EB/82580DB GbE Controller
7.5.7
7.6
7.7
7.8
7.9
7.10
Flow Control Refresh Threshold Value FCRTV (0x2460; R/W) ................................................................................................299
7.5.8
Flow Control Status - FCSTS0 (0x2464; RO) ..................................................................299
PCIe Register Descriptions ..........................................................................................................300
7.6.1
PCIe Control - GCR (0x5B00; RW)................................................................................300
7.6.2
PCIe Statistics Control #1 - GSCL_1 (0x5B10; RW) ........................................................300
7.6.3
PCIe Statistics Control #2 - GSCL_2 (0x5B14; RW) ........................................................301
7.6.4
PCIe Statistic Control Register #5...#8 - GSCL_5_8 (0x5B90 + 4*n[n=0...3]; RW) ............302
7.6.5
PCIe Counter #0 - GSCN_0 (0x5B20; RC) .....................................................................302
7.6.6
PCIe Counter #1 - GSCN_1 (0x5B24; RC) .....................................................................302
7.6.7
PCIe Counter #2 - GSCN_2 (0x5B28; RC) .....................................................................303
7.6.8
PCIe Counter #3 - GSCN_3 (0x5B2C; RC) .....................................................................303
7.6.9
Function Active and Power State to MNG - FACTPS (0x5B30; RO) .....................................303
7.6.10
Mirrored Revision ID - MREVID (0x5B64; R/W) ..............................................................305
7.6.11
PCIe Control Extended Register - GCR_EXT (0x5B6C; RW) ..............................................305
7.6.12
PCIe BAR Control - BARCTRL (0x5BBC; R/W) Target.......................................................305
Semaphore Registers .................................................................................................................306
7.7.1
Software Semaphore - SWSM (0x5B50; R/W) ................................................................307
7.7.2
Firmware Semaphore - FWSM (0x5B54; R/WS)..............................................................307
7.7.3
Software–Firmware Synchronization - SW_FW_SYNC (0x5B5C; RWS) ...............................309
7.7.4
Software Mailbox Write - SWMBWR (0x5B04; R/W) ........................................................310
7.7.5
Software Mailbox 0 - SWMB0 (0x5B08; RO) ..................................................................310
7.7.6
Software Mailbox 1 - SWMB1 (0x5B0C; RO) ..................................................................310
7.7.7
Software Mailbox 2 - SWMB2 (0x5B18; RO) ..................................................................310
7.7.8
Software Mailbox 3 - SWMB3 (0x5B1C; RO) ..................................................................310
Interrupt Register Descriptions ....................................................................................................311
7.8.1
PCIe Interrupt Cause - PICAUSE (0x5B88; RW1/C).........................................................311
7.8.2
PCIe Interrupt Enable - PIENA (0x5B8C; R/W) ...............................................................311
7.8.3
Extended Interrupt Cause - EICR (0x1580; RC/W1C) ......................................................311
7.8.4
Extended Interrupt Cause Set - EICS (0x1520; WO) .......................................................312
7.8.5
Extended Interrupt Mask Set/Read - EIMS (0x1524; RWS) ..............................................313
7.8.6
Extended Interrupt Mask Clear - EIMC (0x1528; WO) .....................................................313
7.8.7
Extended Interrupt Auto Clear - EIAC (0x152C; R/W) .....................................................314
7.8.8
Extended Interrupt Auto Mask Enable EIAM (0x1530; R/W) ..................................................................................................314
7.8.9
Interrupt Cause Read Register - ICR (0x1500; RC/W1C) .................................................315
7.8.10
Interrupt Cause Set Register - ICS (0x1504; WO) ..........................................................317
7.8.11
Interrupt Mask Set/Read Register - IMS (0x1508; R/W) ..................................................318
7.8.12
Interrupt Mask Clear Register - IMC (0x150C; WO) ........................................................319
7.8.13
Interrupt Acknowledge Auto Mask Register - IAM (0x1510; R/W) .....................................321
7.8.14
Interrupt Throttle - EITR (0x1680 + 4*n [n = 0...9]; R/W)..............................................321
7.8.15
Interrupt Vector Allocation Registers IVAR (0x1700 + 4*n [n=0...3]; RW) ............................................................................322
7.8.16
Interrupt Vector Allocation Registers MISC IVAR_MISC (0x1740; RW) ..................................................................................323
7.8.17
General Purpose Interrupt Enable - GPIE (0x1514; RW) ..................................................323
MSI-X Table Register Descriptions................................................................................................324
7.9.1
MSI–X Table Entry Lower Address MSIXTADD (BAR3: 0x0000 + 0x10*n [n=0...9]; R/W) ....................................................325
7.9.2
MSI–X Table Entry Upper Address MSIXTUADD (BAR3: 0x0004 + 0x10*n [n=0...9]; R/W) ..................................................325
7.9.3
MSI–X Table Entry Message MSIXTMSG (BAR3: 0x0008 + 0x10*n [n=0...9]; R/W) ....................................................325
7.9.4
MSI–X Table Entry Vector Control MSIXTVCTRL (BAR3: 0x000C + 0x10*n [n=0...9]; R/W) .................................................326
7.9.5
MSIXPBA Bit Description –
MSIXPBA (BAR3: 0x2000; RO).....................................................................................326
7.9.6
MSI-X PBA Clear – PBACL (0x5B68; R/W1C)..................................................................326
Receive Register Descriptions ......................................................................................................326
7.10.1
Receive Control Register - RCTL (0x0100; R/W) .............................................................326
7.10.2
Split and Replication Receive Control SRRCTL (0xC00C + 0x40*n [n=0...7]; R/W)..................................................................329
7.10.3
Packet Split Receive Type PSRTYPE (0x5480 + 4*n [n=0...7]; R/W)......................................................................330
7.10.4
Replicated Packet Split Receive Type RPLPSRTYPE (0x54C0; R/W)........................................................................................331
7.10.5
Receive Descriptor Base Address Low RDBAL (0xC000 + 0x40*n [n=0...7]; R/W) ...................................................................332
7.10.6
Receive Descriptor Base Address High RDBAH (0xC004 + 0x40*n [n=0...7]; R/W)...................................................................332
7.10.7
Receive Descriptor Ring Length RDLEN (0xC008 + 0x40*n [n=0...7]; R/W) ...................................................................332
7.10.8
Receive Descriptor Head RDH (0xC010 + 0x40*n [n=0...7]; RO) ........................................................................333
Revision: 2.50
October 2011
Intel® 82580EB/82580DB Gigabit Ethernet Controller
Datasheet
11
Intel® 82580EB/82580DB GbE Controller — Contents
7.10.9
7.11
7.12
7.13
7.14
7.15
Receive Descriptor Tail RDT (0xC018 + 0x40*n [n=0...7]; R/W) ......................................................................
7.10.10
Receive Descriptor Control RXDCTL (0xC028 + 0x40*n [n=0...7]; R/W).................................................................
7.10.11
Receive Queue Drop Packet Count RQDPC (0xC030 + 0x40*n [n=0...7]; RC/W) ................................................................
7.10.12
Receive Checksum Control - RXCSUM (0x5000; R/W) ....................................................
7.10.13
Receive Long Packet Maximum Length RLPML (0x5004; R/W) ...............................................................................................
7.10.14
Receive Filter Control Register - RFCTL (0x5008; R/W) ..................................................
7.10.15
Multicast Table Array MTA (0x5200 + 4*n [n=0...127]; R/W)........................................................................
7.10.16
Receive Address Low - RAL (0x5400 + 8*n [n=0...15];
0x54E0 + 8*n [n=0...7]; R/W) ...................................................................................
7.10.17
Receive Address High - RAH (0x5404 + 8*n [n=0...15]; 0x54E4 + 8*n [n=0...7]; R/W) ....
7.10.18
VLAN Filter Table Array - VFTA (0x5600 + 4*n [n=0...127]; R/W) ...................................
7.10.19
Multiple Receive Queues Command Register - MRQC (0x5818; R/W)................................
7.10.20
RSS Random Key Register - RSSRK (0x5C80 + 4*n [n=0...9]; R/W) ...............................
7.10.21
Redirection Table - RETA (0x5C00 + 4*n [n=0...31]; R/W) ............................................
Filtering Register Descriptions ....................................................................................................
7.11.1
Immediate Interrupt RX - IMIR (0x5A80 + 4*n [n=0...7]; R/W)......................................
7.11.2
Immediate Interrupt Rx Ext. - IMIREXT (0x5AA0 + 4*n [n=0...7]; R/W) ..........................
7.11.3
(0x59E0 + 4*n[n=0...7]; RW) ....................................................................................
7.11.4
Immediate Interrupt Rx VLAN Priority IMIRVP (0x5AC0; R/W) ..............................................................................................
7.11.5
SYN Packet Queue Filter - SYNQF (0x55FC; RW) ...........................................................
7.11.6
EType Queue Filter - ETQF (0x5CB0 + 4*n[n=0...7]; RW) ..............................................
Transmit Register Descriptions ...................................................................................................
7.12.1
Transmit Control Register - TCTL (0x0400; R/W)...........................................................
7.12.2
Transmit Control Extended - TCTL_EXT (0x0404; R/W) ..................................................
7.12.3
Transmit IPG Register - TIPG (0x0410; R/W) ................................................................
7.12.4
Retry Buffer Control – RETX_CTL (0x041C; RW)............................................................
7.12.5
DMA Tx Control - DTXCTL (0x3590; R/W) ....................................................................
7.12.6
DMA TX TCP Flags Control Low - DTXTCPFLGL (0x359C; RW)..........................................
7.12.7
DMA TX TCP Flags Control High - DTXTCPFLGH (0x35A0; RW) ........................................
7.12.8
DMA TX Max Total Allow Size Requests - DTXMXSZRQ (0x3540; RW)...............................
7.12.9
DMA TX Maximum Packet Size - DTXMXPKTSZ (0x355C; RW) .........................................
7.12.10
Transmit Descriptor Base Address Low - TDBAL (0xE000 + 0x40*n [n=0...7]; R/W) ..........
7.12.11
Transmit Descriptor Base Address High - TDBAH (0xE004 + 0x40*n [n=0...7]; R/W).........
7.12.12
Transmit Descriptor Ring Length - TDLEN (0xE008 + 0x40*n [n=0...7]; R/W) ..................
7.12.13
Transmit Descriptor Head - TDH (0xE010 + 0x40*n [n=0...7]; RO) .................................
7.12.14
Transmit Descriptor Tail - TDT (0xE018 + 0x40*n [n=0...7]; R/W)..................................
7.12.15
Transmit Descriptor Control - TXDCTL (0xE028 + 0x40*n [n=0...7]; R/W) .......................
7.12.16
Tx Descriptor Completion Write–Back Address Low - TDWBAL
(0xE038 + 0x40*n [n=0...7]; R/W).............................................................................
7.12.17
Tx Descriptor Completion Write–Back Address High - TDWBAH
(0xE03C + 0x40*n [n=0...7];R/W)..............................................................................
DCA and TPH Register Descriptions .............................................................................................
7.13.1
Rx DCA Control Registers - RXCTL (0xC014 + 0x40*n [n=0...7]; R/W) ............................
7.13.2
Tx DCA Control Registers - TXCTL (0xE014 + 0x40*n [n=0...7]; R/W) .............................
7.13.3
DCA Requester ID Information - DCA_ID (0x5B70; RO) .................................................
7.13.4
DCA Control - DCA_CTRL (0x5B74; R/W) .....................................................................
Virtualization Register Descriptions .............................................................................................
7.14.1
VMDq Control register – VT_CTL (0x581C; R/W) ...........................................................
7.14.2
Malicious Driver Free Block - MDFB (0x3558; RWS) .......................................................
7.14.3
Last VM Misbehavior Cause – LVMMC (0x3548; RC) .......................................................
7.14.4
VM Offload register - VMOLR (0x5AD0 + 4*n [n=0...7]; RW) ..........................................
7.14.5
Replication Offload register - RPLOLR (0x5AF0; RW) ......................................................
7.14.6
VLAN VM Filter - VLVF (0x5D00 + 4*n [n=0...31]; RW) .................................................
7.14.7
Unicast Table Array - UTA (0xA000 + 4*n [n=0...127]; R/W) .........................................
7.14.8
Storm Control control register- SCCRL (0x5DB0;RW) .....................................................
7.14.9
Storm Control status - SCSTS (0x5DB4;RO) .................................................................
7.14.10
Broadcast Storm control Threshold - BSCTRH (0x5DB8;RW) ...........................................
7.14.11
Multicast Storm control Threshold - MSCTRH (0x5DBC; RW) ...........................................
7.14.12
Broadcast Storm Control Current Count - BSCCNT (0x5DC0;RO) .....................................
7.14.13
Multicast Storm control Current Count - MSCCNT (0x5DC4;RO).......................................
7.14.14
Storm Control Time Counter - SCTC (0x5DC8; RO)........................................................
7.14.15
Storm Control Basic interval- SCBI (0x5DCC; RW).........................................................
7.14.16
Virtual Mirror rule control - VMRCTL (0x5D80 + 0x4*n [n= 0...3]; RW) ............................
7.14.17
Virtual Mirror rule VLAN - VMRVLAN (0x5D90 + 0x4*n [n= 0...3]; RW) ............................
7.14.18
Virtual Mirror rule VM - VMRVM (0x5DA0 + 0x4*n [n= 0...3]; RW) ..................................
Power Management Registers Description ....................................................................................
7.15.1
DMA Coalescing Control Register - DMACR (0x2508; R/W) .............................................
7.15.2
DMA Coalescing Transmit Threshold - DMCTXTH (0x3550;RW)........................................
7.15.3
DMA Coalescing Time to Lx Request - DMCTLX (0x2514;RW) ..........................................
Intel® 82580EB/82580DB Gigabit Ethernet Controller
Datasheet
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Revision: 2.50
October 2011
Contents — Intel® 82580EB/82580DB GbE Controller
7.16
7.17
7.18
7.19
7.15.4
DMA Coalescing Receive Packet Rate Threshold - DMCRTRH (0x5DD0;RW) ........................368
7.15.5
DMA Coalescing Current RX Count - DMCCNT (0x5DD4;RO).............................................368
7.15.6
Flow Control Receive Threshold Coalescing - FCRTC (0x2170; R/W) ..................................369
7.15.7
Latency Tolerance Reporting (LTR) Minimum Values - LTRMINV (0x5BB0; R/W) .................369
7.15.8
Latency Tolerance Reporting (LTR) Maximum Values - LTRMAXV (0x5BB4; R/W) ................370
7.15.9
Latency Tolerance Reporting (LTR) Control - LTRC (0x01A0; R/W)....................................371
Timer Registers Description.........................................................................................................371
7.16.1
Watchdog Setup - WDSTP (0x1040; R/W) .....................................................................371
7.16.2
Watchdog Software Device Status - WDSWSTS (0x1044; R/W) ........................................372
7.16.3
Free Running Timer - FRTIMER (0x1048; RWS)..............................................................372
7.16.4
TCP Timer - TCPTIMER (0x104C; R/W) .........................................................................372
Time Sync Register Descriptions ..................................................................................................373
7.17.1
RX Time Sync Control register - TSYNCRXCTL (0xB620;RW) ............................................373
7.17.2
RX timestamp Low - RXSTMPL (0xB624; RO).................................................................374
7.17.3
RX timestamp High - RXSTMPH (0xB628; RO) ...............................................................374
7.17.4
RX timestamp attributes low - RXSATRL(0xB62C; RO) ....................................................374
7.17.5
RX timestamp attributes high- RXSATRH (0xB630; RO)...................................................375
7.17.6
TX Time Sync Control register - TSYNCTXCTL (0xB614; RW) ...........................................375
7.17.7
TX timestamp value Low - TXSTMPL (0xB618;RO)..........................................................375
7.17.8
TX Timestamp Value High - TXSTMPH(0xB61C; RO) .......................................................375
7.17.9
System Time Register Residue - SYSTIMR (0xB6F8; RW) ................................................375
7.17.10
System Time Register Low - SYSTIML (0xB600; RW) ......................................................376
7.17.11
System Time Register High - SYSTIMH (0xB604; RW).....................................................376
7.17.12
Increment Attributes Register - TIMINCA (0xB608; RW)..................................................376
7.17.13
Time Adjustment Offset Register Low - TIMADJL (0xB60C; RW) .......................................376
7.17.14
Time Adjustment Offset Register High - TIMADJH (0xB610;RW) .......................................377
7.17.15
TimeSync Auxiliary control register - TSAUXC (0xB640; RW) ...........................................377
7.17.16
Target Time Register 0 Low - TRGTTIML0 (0xB644; RW) .................................................378
7.17.17
Target Time Register 0 High - TRGTTIMH0 (0xB648; RW)................................................379
7.17.18
Target Time Register 1 Low - TRGTTIML1 (0xB64C; RW) .................................................379
7.17.19
Target Time Register 1 High - TRGTTIMH1 (0xB650; RW)................................................379
7.17.20
Frequency Out 0 Control Register FREQOUT0 (0xB654; RW) ............................................379
7.17.21
Frequency Out 1 Control Register - FREQOUT1 (0xB658; RW)..........................................380
7.17.22
Auxiliary Time Stamp 0 Register Low - AUXSTMPL0 (0xB65C; RO)....................................380
7.17.23
Auxiliary Time Stamp 0 Register High -AUXSTMPH0 (0xB660; RO) ...................................380
7.17.24
Auxiliary Time Stamp 1 Register Low AUXSTMPL1 (0xB664; RO) ......................................381
7.17.25
Auxiliary Time Stamp 1 Register High - AUXSTMPH1 (0xB668; RO) ..................................381
7.17.26
Time Sync RX Configuration - TSYNCRXCFG (0x5F50; R/W).............................................381
7.17.27
Time Sync SDP Configuration Register - TSSDP (0x003C; R/W)........................................381
7.17.28
Time Sync Interrupt Registers .....................................................................................383
PCS Register Descriptions ...........................................................................................................385
7.18.1
PCS Configuration - PCS_CFG (0x4200; R/W) ................................................................385
7.18.2
PCS Link Control - PCS_LCTL (0x4208; RW) ..................................................................386
7.18.3
PCS Link Status - PCS_LSTS (0x420C; RO) ...................................................................387
7.18.4
AN Advertisement - PCS_ANADV (0x4218; R/W) ............................................................388
7.18.5
Link Partner Ability - PCS_LPAB (0x421C; RO) ...............................................................389
7.18.6
Next Page Transmit - PCS_NPTX (0x4220; RW) .............................................................390
7.18.7
Link Partner Ability Next Page - PCS_LPABNP (0x4224; RO) ............................................391
7.18.8
SFP I2C Command- I2CCMD (0x1028; R/W)..................................................................391
7.18.9
SFP I2C Parameters - I2CPARAMS (0x102C; R/W)..........................................................392
Statistics Register Descriptions ....................................................................................................393
7.19.1
CRC Error Count - CRCERRS (0x4000; RC) ....................................................................393
7.19.2
Alignment Error Count - ALGNERRC (0x4004; RC) ..........................................................394
7.19.3
Symbol Error Count - SYMERRS (0x4008; RC) ...............................................................394
7.19.4
RX Error Count - RXERRC (0x400C; RC)........................................................................394
7.19.5
Missed Packets Count - MPC (0x4010; RC) ....................................................................394
7.19.6
Single Collision Count - SCC (0x4014; RC) ....................................................................395
7.19.7
Excessive Collisions Count - ECOL (0x4018; RC) ............................................................395
7.19.8
Multiple Collision Count - MCC (0x401C; RC) .................................................................395
7.19.9
Late Collisions Count - LATECOL (0x4020; RC)...............................................................395
7.19.10
Collision Count - COLC (0x4028; RC)............................................................................395
7.19.11
Defer Count - DC (0x4030; RC) ...................................................................................396
7.19.12
Transmit with No CRS - TNCRS (0x4034; RC) ................................................................396
7.19.13
Host Transmit Discarded Packets by MAC Count - HTDPMC (0x403C; RC) ..........................396
7.19.14
Receive Length Error Count - RLEC (0x4040; RC)...........................................................396
7.19.15
XON Received Count - XONRXC (0x4048; RC)................................................................397
7.19.16
XON Transmitted Count - XONTXC (0x404C; RC) ...........................................................397
7.19.17
XOFF Received Count - XOFFRXC (0x4050; RC) .............................................................397
7.19.18
XOFF Transmitted Count - XOFFTXC (0x4054; RC) .........................................................397
7.19.19
FC Received Unsupported Count - FCRUC (0x4058; RC) ..................................................398
7.19.20
Packets Received [64 Bytes] Count - PRC64 (0x405C; RC) ..............................................398
7.19.21
Packets Received [65—127 Bytes] Count - PRC127 (0x4060; RC).....................................398
7.19.22
Packets Received [128—255 Bytes] Count - PRC255 (0x4064; RC) ...................................398
7.19.23
Packets Received [256—511 Bytes] Count - PRC511 (0x4068; RC) ...................................399
7.19.24
Packets Received [512—1023 Bytes] Count - PRC1023 (0x406C; RC) ...............................399
Revision: 2.50
October 2011
Intel® 82580EB/82580DB Gigabit Ethernet Controller
Datasheet
13
Intel® 82580EB/82580DB GbE Controller — Contents
7.19.25
7.19.26
7.19.27
7.19.28
7.19.29
7.19.30
7.19.31
7.19.32
7.19.33
7.19.34
7.19.35
7.19.36
7.19.37
7.19.38
7.19.39
7.20
Packets Received [1024 to Max Bytes] Count - PRC1522 (0x4070; RC) ............................
Good Packets Received Count - GPRC (0x4074; RC) ......................................................
Broadcast Packets Received Count - BPRC (0x4078; RC) ................................................
Multicast Packets Received Count - MPRC (0x407C; RC) .................................................
Good Packets Transmitted Count - GPTC (0x4080; RC) ..................................................
Good Octets Received Count - GORCL (0x4088; RC) ......................................................
Good Octets Received Count - GORCH (0x408C; RC) .....................................................
Good Octets Transmitted Count - GOTCL (0x4090; RC) ..................................................
Good Octets Transmitted Count - GOTCH (4094; RC).....................................................
Receive No Buffers Count - RNBC (0x40A0; RC) ............................................................
Receive Undersize Count - RUC (0x40A4; RC)...............................................................
Receive Fragment Count - RFC (0x40A8; RC) ...............................................................
Receive Oversize Count - ROC (0x40AC; RC) ................................................................
Receive Jabber Count - RJC (0x40B0; RC) ....................................................................
Management Packets Received Count MNGPRC (0x40B4; RC) ..............................................................................................
7.19.40
Management Packets Dropped Count MPDC (0x40B8; RC) ..................................................................................................
7.19.41
Management Packets Transmitted Count MNGPTC (0x40BC; RC) ..............................................................................................
7.19.42
Total Octets Received - TORL (0x40C0; RC) .................................................................
7.19.43
Total Octets Received - TORH (0x40C4; RC) .................................................................
7.19.44
Total Octets Transmitted - TOTL (0x40C8; RC) .............................................................
7.19.45
Total Octets Transmitted - TOTH (0x40CC; RC).............................................................
7.19.46
Total Packets Received - TPR (0x40D0; RC)..................................................................
7.19.47
Total Packets Transmitted - TPT (0x40D4; RC)..............................................................
7.19.48
Packets Transmitted [64 Bytes] Count PTC64 (0x40D8; RC) .................................................................................................
7.19.49
Packets Transmitted [65—127 Bytes] Count PTC127 (0x40DC; RC) ...............................................................................................
7.19.50
Packets Transmitted [128—255 Bytes] Count PTC255 (0x40E0; RC) ................................................................................................
7.19.51
Packets Transmitted [256—511 Bytes] Count PTC511 (0x40E4; RC) ................................................................................................
7.19.52
Packets Transmitted [512—1023 Bytes] Count PTC1023 (0x40E8; RC) ..............................................................................................
7.19.53
Packets Transmitted [1024 Bytes or Greater] Count - PTC1522 (0x40EC; RC) ...................
7.19.54
Multicast Packets Transmitted Count MPTC (0x40F0; RC) ...................................................................................................
7.19.55
Broadcast Packets Transmitted Count BPTC (0x40F4; RC) ...................................................................................................
7.19.56
TCP Segmentation Context Transmitted Count TSCTC (0x40F8; RC) .................................................................................................
7.19.57
Interrupt Assertion Count - IAC (0x4100; RC)...............................................................
7.19.58
Rx Packets to Host Count - RPTHC (0x4104; RC)...........................................................
7.19.59
Host Good Packets Transmitted Count HGPTC (0x4118; RC) .................................................................................................
7.19.60
Receive Descriptor Minimum Threshold Count RXDMTC (0x4120; RC) ..............................................................................................
7.19.61
Host Good Octets Received Count - HGORCL (0x4128; RC).............................................
7.19.62
Host Good Octets Received Count - HGORCH (0x412C; RC) ............................................
7.19.63
Host Good Octets Transmitted Count HGOTCL (0x4130; RC) ...............................................................................................
7.19.64
Host Good Octets Transmitted Count HGOTCH (0x4134; RC) ..............................................................................................
7.19.65
Length Error Count - LENERRS (0x4138; RC)................................................................
7.19.66
SerDes/SGMII/KX Code Violation Packet Count SCVPC (0x4228; RW) ................................................................................................
7.19.67
Switch Drop Packet Count - SDPC (0x41A4; RC) ...........................................................
7.19.68
Virtualization Statistical Counters ................................................................................
Manageability statistics..............................................................................................................
7.20.1
BMC Management Packets Dropped Count BMPDC (0x4140; RC) ................................................................................................
7.20.2
BMC Management Packets Transmitted Count BMNGPTC (0x4144; RC).............................................................................................
7.20.3
BMC Management Packets Received Count BMNGPRC (0x413C; RC) ............................................................................................
7.20.4
BMC Total Unicast Packets Received BUPRC (0x4400; RC) .................................................................................................
7.20.5
BMC Total Multicast Packets Received BMPRC (0x4404; RC).................................................................................................
7.20.6
BMC Total Broadcast Packets Received BBPRC (0x4408; RC) .................................................................................................
7.20.7
BMC Total Unicast Packets Transmitted BUPTC (0x440C; RC) .................................................................................................
Intel® 82580EB/82580DB Gigabit Ethernet Controller
Datasheet
14
399
400
400
400
400
401
401
401
401
402
402
402
402
403
403
403
404
404
404
404
405
405
405
405
406
406
406
406
407
407
407
408
408
408
408
409
409
409
409
410
410
410
411
411
413
413
413
413
413
414
414
414
Revision: 2.50
October 2011
Contents — Intel® 82580EB/82580DB GbE Controller
7.20.8
7.21
7.22
7.23
BMC Total Multicast Packets Transmitted BMPTC (0x4410; RC)..................................................................................................414
7.20.9
BMC Total Broadcast Packets Transmitted BBPTC (0x4414; RC) ..................................................................................................414
7.20.10
BMC FCS Receive Errors - BCRCERRS (0x4418; RC) .......................................................414
7.20.11
BMC Alignment Errors - BALGNERRC (0x441C; RC) ........................................................415
7.20.12
BMC Pause XON Frames Received BXONRXC (0x4420; RC)..............................................................................................415
7.20.13
BMC Pause XOFF Frames Received BXOFFRXC (0x4424; RC) ............................................................................................415
7.20.14
BMC Pause XON Frames Transmitted BXONTXC (0x4428; RC)..............................................................................................415
7.20.15
BMC Pause XOFF Frames Transmitted BXOFFTXC (0x442C; RC) ............................................................................................415
7.20.16
BMC Single Collision Transmit FramesBSCC (0x4430; RC)....................................................................................................415
7.20.17
BMC Multiple Collision Transmit Frames BMCC (0x4434; RC) ...................................................................................................415
Wake Up Control Register Descriptions .........................................................................................416
7.21.1
Wakeup Control Register - WUC (0x5800; R/W) .............................................................416
7.21.2
Wakeup Filter Control Register - WUFC (0x5808; R/W) ...................................................416
7.21.3
Wakeup Status Register - WUS (0x5810; R/W1C) ..........................................................417
7.21.4
Wakeup Packet Length - WUPL (0x5900; RO) ................................................................418
7.21.5
Wakeup Packet Memory WUPM (0x5A00 + 4*n [n=0...31]; RO) .........................................................................418
7.21.6
IP Address Valid - IPAV (0x5838; R/W).........................................................................418
7.21.7
IPv4 Address Table IP4AT (0x5840 + 8*n [n=0...3]; R/W)..........................................................................419
7.21.8
IPv6 Address Table IP6AT (0x5880 + 4*n [n=0...3]; R/W)..........................................................................419
7.21.9
Flexible Host Filter Table registers FHFT (0x9000 - 0x93FC; RW) ......................................................................................419
7.21.10
Flexible Host Filter Table Extended Registers FHFT_EXT (0x9A00 - 0x9DFC; RW) ..............................................................................422
Management Register Descriptions...............................................................................................422
7.22.1
Management VLAN TAG Value MAVTV (0x5010 +4*n [n=0...7]; RW) ..........................................................................422
7.22.2
Management Flex UDP/TCP Ports MFUTP (0x5030 + 4*n [n=0...7]; RW) ..........................................................................423
7.22.3
Management Ethernet Type Filters METF (0x5060 + 4*n [n=0...3]; RW)............................................................................423
7.22.4
Management Control Register - MANC (0x5820; RW) ......................................................423
7.22.5
Management Only Traffic Register MNGONLY (0x5864; RW) ............................................................................................425
7.22.6
Manageability Decision FiltersMDEF (0x5890 + 4*n [n=0...7]; RW) ...........................................................................425
7.22.7
Manageability Decision Filters MDEF_EXT (0x5930 + 4*n[n=0...7]; RW) .....................................................................426
7.22.8
Manageability IP Address Filter MIPAF (0x58B0 + 4*n [n=0...15]; RW).........................................................................427
7.22.9
Manageability MAC Address Low MMAL (0x5910 + 8*n [n= 0...1]; RW) ..........................................................................429
7.22.10
Manageability MAC Address High MMAH (0x5914 + 8*n [n=0...1]; RW) ..........................................................................430
7.22.11
Flexible TCO Filter Table registers FTFT (0x9400-0x94FC; RW) ........................................................................................430
Memory Error Registers Description..............................................................................................431
7.23.1
Parity and ECC Error Indication- PEIND (0x1084; RC) .....................................................432
7.23.2
Parity and ECC Indication Mask – PEINDM (0x1088; RW) ................................................432
7.23.3
DMA Transmit Descriptor Parity Control DTPARC (0x3500; RW) ...............................................................................................432
7.23.4
DMA Transmit Descriptor Parity StatusDTPARS (0x3510; RW1C)............................................................................................433
7.23.5
DMA Receive Descriptor Parity Control DRPARC (0x3504; RW) ...............................................................................................433
7.23.6
DMA Receive Descriptor Parity Status DRPARS (0x3514; RW1C) ...........................................................................................433
7.23.7
Dhost Parity Control DDPARC (0x3508; RW) ...............................................................................................433
7.23.8
Rx Packet Buffer ECC Status RPBECCSTS (0x245C; RW) ..........................................................................................433
7.23.9
Tx Packet Buffer ECC Status - TPBECCSTS (0x345C; RW)................................................434
7.23.10
PCIe ECC Status Register - PCIEECCSTS (0x5BAC; R/W1C) .............................................434
7.23.11
LAN Port Parity Error Control Register LANPERRCTL (0x5F54; RW) .........................................................................................435
Revision: 2.50
October 2011
Intel® 82580EB/82580DB Gigabit Ethernet Controller
Datasheet
15
Intel® 82580EB/82580DB GbE Controller — Contents
7.23.12
7.24
8.0
8.1
8.2
8.3
8.4
8.5
8.6
8.7
8.8
8.9
8.10
9.0
9.1
9.2
9.3
9.4
LAN Port Parity Error Status Register LANPERRSTS (0x5F58; RO) ........................................................................................ 435
PHY Software Interface.............................................................................................................. 436
7.24.1
PHY Power Management - PHPM (0x0E14, RW) ............................................................. 436
7.24.2
Internal PHY Software Interface (PHYREG) ................................................................... 437
Inline Functions ......................................................................................................................459
Receive Functionality................................................................................................................. 459
8.1.1
Receive Queues Assignment ....................................................................................... 459
8.1.2
L2 Packet Filtering .................................................................................................... 473
8.1.3
Receive Data Storage ................................................................................................ 479
8.1.4
Legacy Receive Descriptor Format ............................................................................... 480
8.1.5
Advanced Receive Descriptors .................................................................................... 484
8.1.6
Receive Descriptor Fetching........................................................................................ 489
8.1.7
Receive Descriptor Write-Back .................................................................................... 489
8.1.8
Receive Descriptor Ring Structure ............................................................................... 490
8.1.9
Header Splitting and Replication.................................................................................. 492
8.1.10
Receive Packet Timestamp in Buffer ............................................................................ 495
8.1.11
Receive Packet Checksum Off Loading ......................................................................... 496
8.1.12
SCTP Offload ............................................................................................................ 500
Transmit Functionality ............................................................................................................... 501
8.2.1
Packet Transmission .................................................................................................. 501
8.2.2
Transmit Descriptors ................................................................................................. 503
8.2.3
Transmit Completions Head Write Back ........................................................................ 516
8.2.4
TCP/UDP Segmentation ............................................................................................. 517
8.2.5
Checksum Offloading in Non-Segmentation Mode .......................................................... 526
8.2.6
Multiple Transmit Queues........................................................................................... 529
Interrupts ................................................................................................................................ 529
8.3.1
Mapping of Interrupt Causes....................................................................................... 529
8.3.2
Legacy Interrupt Registers ......................................................................................... 532
8.3.3
MSI-X and Vectors .................................................................................................... 536
8.3.4
Interrupt Moderation ................................................................................................. 536
8.3.5
Clearing Interrupt Causes .......................................................................................... 539
8.3.6
Rate Controlled Low Latency Interrupts (LLI) ................................................................ 540
8.3.7
TCP Timer Interrupt .................................................................................................. 541
802.1q VLAN Support ................................................................................................................ 541
8.4.1
802.1q VLAN Packet Format ....................................................................................... 542
8.4.2
802.1q Tagged Frames .............................................................................................. 542
8.4.3
Transmitting and Receiving 802.1q Packets .................................................................. 542
8.4.4
802.1q VLAN Packet Filtering...................................................................................... 543
8.4.5
Double VLAN Support ................................................................................................ 544
Configurable LED Outputs .......................................................................................................... 545
8.5.1
MODE Encoding for LED Outputs ................................................................................. 546
Memory Error Correction and Detection ....................................................................................... 546
8.6.1
Management Parity Errors .......................................................................................... 547
CPU affinity Features................................................................................................................. 548
8.7.1
Direct Cache Access (DCA) ......................................................................................... 548
8.7.2
TLP Process Hints (TPH) ............................................................................................. 550
Virtualization............................................................................................................................ 551
8.8.1
Overview ................................................................................................................. 551
8.8.2
Packet Switching (VMDq) Model .................................................................................. 555
8.8.3
Virtualization of the Hardware..................................................................................... 565
Time SYNC (IEEE1588 and IEEE 802.1AS).................................................................................... 566
8.9.1
Overview ................................................................................................................. 566
8.9.2
Flow and Hardware/Software Responsibilities................................................................ 566
8.9.3
Hardware Time Sync Elements.................................................................................... 568
8.9.4
Time Sync Related Auxiliary Elements.......................................................................... 571
8.9.5
Time SYNC Interrupts ................................................................................................ 574
8.9.6
PTP Packet Structure ................................................................................................. 574
Statistic Counters ..................................................................................................................... 576
8.10.1
IEEE 802.3 Clause 30 Management ............................................................................. 577
8.10.2
OID_GEN_STATISTICS .............................................................................................. 578
8.10.3
RMON...................................................................................................................... 578
8.10.4
Linux net_device_stats .............................................................................................. 579
8.10.5
Statistics Hierarchy. .................................................................................................. 580
PCIe Programming Interface...................................................................................................583
PCIe* Compatibility................................................................................................................... 583
Configuration Sharing Among PCI Functions ................................................................................. 584
PCIe Register Map .................................................................................................................... 585
9.3.1
Register Attributes .................................................................................................... 585
9.3.2
PCIe Configuration Space Summary ............................................................................ 586
Mandatory PCI Configuration Registers ........................................................................................ 588
9.4.1
Vendor ID (0x0; RO) ................................................................................................. 588
9.4.2
Device ID (0x2; RO).................................................................................................. 588
9.4.3
Command Register (0x4; R/W) ................................................................................... 588
Intel® 82580EB/82580DB Gigabit Ethernet Controller
Datasheet
16
Revision: 2.50
October 2011
Contents — Intel® 82580EB/82580DB GbE Controller
9.5
9.6
10.0
10.1
10.2
10.3
10.4
10.5
10.6
10.7
10.8
10.9
11.0
11.1
11.2
11.3
11.4
12.0
12.1
9.4.4
Status Register (0x6; RO) ...........................................................................................589
9.4.5
Revision (0x8; RO).....................................................................................................590
9.4.6
Class Code (0x9; RO) .................................................................................................590
9.4.7
Cache Line Size (0xC; R/W) ........................................................................................590
9.4.8
Latency Timer (0xD; RO) ............................................................................................590
9.4.9
Header Type (0xE; RO)...............................................................................................590
9.4.10
BIST (0xF; RO)..........................................................................................................591
9.4.11
Base Address Registers (0x10...0x27; R/W) ..................................................................591
9.4.12
CardBus CIS (0x28; RO) .............................................................................................592
9.4.13
Subsystem Vendor ID (0x2C; RO) ................................................................................593
9.4.14
Subsystem ID (0x2E; RO) ...........................................................................................593
9.4.15
Expansion ROM Base Address (0x30; RO) .....................................................................593
9.4.16
Cap_Ptr (0x34; RO) ...................................................................................................593
9.4.17
Interrupt Line (0x3C; RW) ..........................................................................................593
9.4.18
Interrupt Pin (0x3D; RO) ............................................................................................593
9.4.19
Max_Lat/Min_Gnt (0x3E; RO) ......................................................................................594
PCI Capabilities .........................................................................................................................594
9.5.1
PCI Power Management Capability ...............................................................................594
9.5.2
MSI Configuration ......................................................................................................597
9.5.3
MSI-X Configuration ...................................................................................................598
9.5.4
CSR Access Via Configuration Address Space .................................................................601
9.5.5
Vital Product Data Registers ........................................................................................602
9.5.6
PCIe Configuration Registers .......................................................................................603
PCIe Extended Configuration Space..............................................................................................614
9.6.1
Advanced Error Reporting (AER) Capability....................................................................615
9.6.2
Serial Number ...........................................................................................................620
9.6.3
TLP Processing Hint Requester (TPH) Capability .............................................................622
Electrical/Mechanical Specification .........................................................................................627
Introduction..............................................................................................................................627
Operating Conditions..................................................................................................................627
10.2.1
Recommended Operating Conditions ............................................................................628
Power Delivery ..........................................................................................................................628
10.3.1
Power Supply Specification..........................................................................................628
Ball Summary ...........................................................................................................................631
Current Consumption .................................................................................................................632
DC/AC Specification ...................................................................................................................635
10.6.1
DC Specifications .......................................................................................................635
10.6.2
Digital I/F AC Specifications.........................................................................................637
10.6.3
Serdes DC/AC Specification .........................................................................................645
10.6.4
PHY Specification .......................................................................................................645
10.6.5
XTAL/Clock Specification .............................................................................................645
10.6.6
Oscillator Support ......................................................................................................646
10.6.7
GbE PHY GE_REXT Bias Connection ..............................................................................646
10.6.8
SerDes SE_RSET Bias Connection ................................................................................647
10.6.9
PCIe PE_TRIM Bias Connection ....................................................................................648
Package ...................................................................................................................................649
10.7.1
Mechanical ................................................................................................................649
10.7.2
Maximum Static Load .................................................................................................649
10.7.3
Thermal....................................................................................................................649
10.7.4
Package Schematics ...................................................................................................649
EEPROM Flash Devices ...............................................................................................................651
10.8.1
Flash........................................................................................................................651
10.8.2
EEPROM ...................................................................................................................651
Discrete/Integrated Magnetics Specifications .................................................................................652
Manageability..........................................................................................................................653
Platform Configurations ..............................................................................................................653
11.1.1
On-Board BMC Configurations......................................................................................653
Pass Through Functionality..........................................................................................................655
11.2.1
DMTF NC-SIMode.......................................................................................................656
11.2.2
SMBus Pass Through (PT) Functionality.........................................................................657
Programming Interfaces .............................................................................................................658
11.3.1
NC-SI Programming ...................................................................................................658
11.3.2
SMBus Programming ..................................................................................................665
Manageability Receive Filtering ....................................................................................................697
11.4.1
Overview and General Structure ..................................................................................697
11.4.2
L2 Filters ..................................................................................................................698
11.4.3
L3 and L4 Filters ........................................................................................................699
11.4.4
Manageability Decision Filters ......................................................................................700
11.4.5
Possible Configurations ...............................................................................................703
Design Guidelines ...................................................................................................................705
Ethernet Interface .....................................................................................................................705
12.1.1
Magnetics for 1000 BASE-T .........................................................................................705
12.1.2
Magnetics Module Qualification Steps............................................................................705
12.1.3
Third-Party Magnetics Manufacturers ............................................................................706
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Intel® 82580EB/82580DB GbE Controller — Contents
12.2
12.3
12.4
12.5
12.6
12.7
12.8
13.0
13.1
13.2
13.3
13.4
13.5
13.6
13.7
13.8
13.9
13.10
14.0
14.1
12.1.4
Layout Considerations for the Ethernet Interface ........................................................... 706
12.1.5
Physical Layer Conformance Testing ............................................................................ 712
12.1.6
Troubleshooting Common Physical Layout Issues .......................................................... 712
PCIe ....................................................................................................................................... 713
12.2.1
Link Width Configuration ............................................................................................ 713
12.2.2
Polarity Inversion and Lane Reversal ........................................................................... 713
12.2.3
PCIe Reference Clock ................................................................................................ 713
Clock Source ............................................................................................................................ 714
12.3.1
Frequency Control Device Design Considerations ........................................................... 714
12.3.2
Frequency Control Component Types ........................................................................... 714
Crystal Support ........................................................................................................................ 715
12.4.1
Crystal Selection Parameters ...................................................................................... 715
12.4.2
Crystal Placement and Layout Recommendations .......................................................... 719
Oscillator Support ..................................................................................................................... 720
12.5.1
Oscillator Placement and Layout Recommendations ....................................................... 721
Device Disable.......................................................................................................................... 721
12.6.1
BIOS Handling of Device Disable ................................................................................. 722
SMBus and NC-SI ..................................................................................................................... 722
NC-SI ..................................................................................................................................... 723
12.8.1
Design Requirements ................................................................................................ 723
12.8.2
Layout Requirements................................................................................................. 726
Thermal Management..............................................................................................................731
Thermal Design Considerations .................................................................................................. 731
Terminology ............................................................................................................................ 731
Thermal Specifications .............................................................................................................. 732
13.3.1
Case Temperature .................................................................................................... 733
Thermal Attributes ................................................................................................................... 734
13.4.1
Designing for Thermal Performance ............................................................................ 734
13.4.2
Typical System Definition .......................................................................................... 734
13.4.3
Package Mechanical Attributes .................................................................................... 734
13.4.4
Package Thermal Characteristics ................................................................................ 734
Thermal Enhancements ............................................................................................................ 739
13.5.1
Clearances .............................................................................................................. 739
13.5.2
Default Enhanced Thermal Solution ............................................................................ 739
13.5.3
Extruded Heatsinks .................................................................................................. 739
13.5.4
Attaching the Extruded Heatsink ................................................................................ 743
13.5.5
Reliability ................................................................................................................ 744
Thermal Interface Management for Heat-Sink Solutions ................................................................. 744
13.6.1
Bond Line Management ............................................................................................. 745
13.6.2
Interface Material Performance .................................................................................. 745
Measurements for Thermal Specifications .................................................................................... 745
13.7.1
Case Temperature Measurements .............................................................................. 745
Thermal Diode ......................................................................................................................... 747
Heatsink and Attach Suppliers ................................................................................................... 748
PCB Guidelines ........................................................................................................................ 748
Diagnostics .............................................................................................................................749
JTAG Test Mode Description ....................................................................................................... 749
Appendix A.
Changes from the 82576............................................................................................ 751
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Introduction — Intel® 82580EB/82580DB GbE Controller
1.0
Introduction
The Intel® 82580EB/82580DB GbE Controller is a single, compact, low power component that supports
quad and dual port gigabit Ethernet designs. The device offers four fully-integrated gigabit Ethernet
media access control (MAC), physical layer (PHY) ports and four SGMII/SerDes ports that can be
connected to an external PHY. The 82580EB/DB supports PCI Express* (PCIe v2.0 (5Gbps and
2.5Gbps)).
The device enables two-port or four port 1000BASE-T implementations using integrated PHY’s. It can be
used for server system configurations such as rack mounted or pedestal servers, in an add-on NIC or
LAN on Motherboard (LOM) design. Another possible system configuration is for blade servers. Here,
the 82580EB/DB can support up to 4 SerDes ports as LOM or mezzanine card. It can also be used in
embedded applications such as switch add-on cards and network appliances.
PCIe* 2.0 (5Gbps)
NC-SI
PCIe
SMBus
Mgmt
Queue Management & DMA
Q0 … Qn
TX
FIFO
RX
FIFO
GbE MAC
SerDes
SerDes/
SGMII
Figure 1-1.
Revision: 2.50
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PHY
1000
Base T
Q0 … Qn
TX
FIFO
RX
FIFO
GbE MAC
SerDes
SerDes/
SGMII
PHY
1000
Base T
Q0 … Qn
TX
FIFO
RX
FIFO
GbE MAC
SerDes
PHY
SerDes/
SGMII
1000
Base T
Q0 … Qn
TX
FIFO
RX
FIFO
GbE MAC
SerDes
SerDes/
SGMII
PHY
1000
Base T
Intel® 82580EB/82580DB GbE Controller
Intel® 82580EB/82580DB Gigabit Ethernet Controller
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19
Intel® 82580EB/82580DB GbE Controller — Scope
1.1
Scope
This document provides the external architecture (including device operation, pin descriptions, register
definitions, etc.) for the 82580EB/DB.
This document is a reference for software device driver developers, board designers, test engineers,
and others who may need specific technical or programming information.
1.2
Terminology and Acronyms
Table 1-1.
Glossary
Definition
Meaning
1000BASE-BX
1000BASE-BX is the PICMG 3.1 electrical specification for transmission of
1 Gb/s Ethernet or 1 Gb/s fibre channel encoded data over the backplane.
1000BASE-KX
1000BASE-KX is the IEEE802.3ap electrical specification for transmission of
1 Gb/s Ethernet over the backplane.
1000BASE-CX
1000BASE-X over specialty shielded 150  balanced copper jumper cable assemblies as
specified in IEEE 802.3 Clause 39.
1000BASE-T
1000BASE-T is the specification for 1 Gb/s Ethernet over category 5e twisted pair cables as
defined in IEEE 802.3 clause 40.
b/w
Bandwidth.
BIOS
Basic Input/Output System.
BMC
Baseboard Management Controller.
BT
Bit Time.
DCA
Direct Cache Access.
DFT
Design for Testability.
DQ
Descriptor Queue.
DW
Double word (4 bytes).
EEPROM
Electrically Erasable Programmable Memory. A non-volatile memory located on the LAN
controller that is directly accessible from the host.
EOP
End of Packet.
FC
Flow Control.
Firmware (FW)
Embedded code on the LAN controller that is responsible for the implementation of the NCSI protocol and pass through functionality.
Host Interface
RAM on the LAN controller that is shared between the firmware and the host. RAM is used to
pass commands from the host to firmware and responses from the firmware to the host.
HPC
High - Performance Computing.
IPC
Inter Processor Communication.
IPG
Inter Packet Gap.
LAN (auxiliary Power-Up)
The event of connecting the LAN controller to a power source (occurs even before system
power-up).
LOM
LAN on Motherboard.
LTR
Latency Tolerance Reporting (PCIe protocol)
LSO
Large Send Offload.
MAC
Media Access Control.
MDIO
Management Data Input/Output Interface over MDC/MDIO lines.
MIFS/MIPG
Minimum Inter Frame Spacing/Minimum Inter Packet Gap.
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External Specification and Documents — Intel® 82580EB/82580DB GbE Controller
Table 1-1.
Glossary (Continued)
Definition
MMW
MSS
Meaning
Maximum Memory Window.
Maximum Segment Size.
Largest amount of data, in a packet (without headers) that can be transmitted. Specified in
Bytes.
MPS
Maximum Payload Size in PCIe specification.
MTU
Maximum Transmit Unit.
Largest packet size (headers and data) that can be transmitted. Specified in Bytes.
NC-SI
Network Controller Sideband Interface DMTF Specification
NIC
Network Interface Controller.
TPH
TLP Process Hints (PCIe protocol).
PCS
Physical Coding Sub layer.
PHY
Physical Layer Device.
PMA
Physical Medium Attachment.
PMD
Physical Medium Dependent.
RMII
Reduced Media Independent Interface (Reduced MII).
SA
Source Address.
SDP
Software Defined Pins.
SerDes
Serializer and De-Serializer Circuit.
SFD
Start Frame Delimiter.
SGMII
Serialized Gigabit Media Independent Interface.
SMBus
System Management Bus. A bus that carries various manageability components, including
the LAN controller, BIOS, sensors and remote-control devices.
TCO
Total Cost of Ownership (TCO) System Management.
TLP
Transaction Layer Packet in the PCI Express specification.
TSO
Transmit Segmentation offload - A mode in which a large TCP/UDP I/O is handled to the
device and the device segments it to L2 packets according to the requested MSS.
VPD
Vital Product Data (PCI protocol).
1.2.1
External Specification and Documents
The 82580EB/DB implements features from the following specifications.
1.2.1.1
Network Interface documents
1. IEEE standard 802.3, 2006 Edition (Ethernet). Incorporates various IEEE Standards previously
published separately. Institute of Electrical and Electronic Engineers (IEEE).
2. IEEE standard 1149.1, 2001 Edition (JTAG). Institute of Electrical and Electronics Engineers (IEEE)
3. IEEE Std 1149.6-2003, IEEE Standard for Boundary-Scan Testing of Advanced Digital Networks,
IEEE, 2003.
4. IEEE standard 802.1Q for VLAN
5. PICMG3.1 Ethernet/Fibre Channel Over PICMG 3.0 Draft Specification, January 14, 2003, Version
D1.0
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Intel® 82580EB/82580DB GbE Controller — Product Overview
6. Serial-GMII Specification, Cisco Systems document ENG-46158, Revision 1.7
7. INF-8074i Specification for SFP (Small Form factor Pluggable) Transceiver (ftp://ftp.seagate.com/
sff)
8. IEEE Std 802.3ap-2007
9. IEEE 1588TM Standard for a Precision Clock Synchronization Protocol for Networked Measurement
and Control Systems, November 8 2002
10. IEEE 802.1AS Timing and Synchronization for Time- Sensitive Applications in Bridged Local Area
Networks Draft 2.0, February 22, 2008
1.2.1.2
Host Interface Documents
1. PCI-Express 2.1 Base specification
2. PCI Specification, version 3.0
3. PCI Bus Power Management Interface Specification, Rev. 1.2, March 2004
4. Advanced Configuration and Power Interface Specification, Rev 2.0b, October 2002
1.2.1.3
Networking Protocol documents
1. IPv4 specification (RFC 791)
2. IPv6 specification (RFC 2460)
3. TCP/UDP specification (RFC 793/768)
4. SCTP specification (RFC 2960)
5. ARP specification (RFC 826)
6. EUI-64 specification, http://standards.ieee.org/regauth/oui/tutorials/EUI64.html.
1.2.1.4
Manageability documents
1. DMTF Network Controller Sideband Interface (NC-SI) Specification rev 1.0.0a, June 2007
2. System Management Bus (SMBus) Specification, SBS Implementers Forum, Ver. 2.0, August 2000
1.3
Product Overview
The 82580EB/DB supports 4 SerDes or SGMII ports for MAC to MAC blade server connections or MAC to
external PHY connections. Alternatively, the four internal 1000BASE-T PHY’s can be used to implement
a quad port NIC or LOM design.
The 82580EB/DB targets server system configurations such as rack mounted or pedestal servers,
where the 82580EB/DB can be used as add-on NIC or LAN on Motherboard (LOM) design. Another
system configuration is blade servers, where it can be used on Mezzanine card or LOM. The 82580EB/
DB can also be used in embedded applications such as switch add-on cards and network appliances.
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External Interface — Intel® 82580EB/82580DB GbE Controller
1.4
External Interface
1.4.1
PCIe Interface
The PCIe v2.0 (5Gbps) Interface is used by the 82580EB/DB as a host interface. The interface supports
both PCIe v2.0 (2.5Gbps) and PCIe v2.0 (5Gbps) rates and can be configured to x4, x2 and x1. The
maximum aggregated raw bandwidth for a typical x4 PCIe v2.0 (5Gbps) configuration is 16 Gb/s in
each direction. See Section 2.1.1 for full pin description. The timing characteristics of this interface are
defined in PCI Express Card Electromechanical Specification rev 2.0 and in the PCIe v2.0 (5Gbps and
2.5Gbps) specification.
1.4.2
Network Interfaces
Four independent interfaces are used to connect the four 82580EB/DB ports to external devices. The
following protocols are supported:
• MDI (Copper) support for standard IEEE 802.3 Ethernet interface for 1000BASE-T, 100BASE-TX,
and 10BASE-T applications (802.3, 802.3u, and 802.3ab). Note that the 82580EB/DB does not
support the ‘MDI flip-chp’ option available on the 82576.
• SerDes interface to connect over a backplane to another SerDes compliant device or to an Optical
module. The 82580EB/DB supports both 1000BASE-BX and 1000BASE-KX (Without IEEE802.3ap
Backplane Auto-Negotiation)
• SGMII interface to attach to an external PHY, either on board or via an SFP module. The SGMII
interface shares the same pins as the SerDes
See Section 2.1.8.2 and Section 2.1.6 for full pin description; Section 10.6.3 and Section 10.6.4 for
timing characteristics of this interface.
1.4.3
EEPROM Interface
The 82580EB/DB uses an EEPROM device for storing product configuration information. Several words
of the EEPROM are accessed automatically by the 82580EB/DB after reset in order to provide pre-boot
configuration data that must be available to the 82580EB/DB before it is accessed by host software.
The remainder of the stored information is accessed by various software modules used to report
product configuration, serial number, etc.
The 82580EB/DB is intended for use with a SPI (4-wire) serial EEPROM device such as an AT25040AN
or compatible EEPROM device (See Section 10.8.2 for full list of supported EEPROM devices). See
Section 2.1.2 for full pin description and Section 10.6.2.5 for timing characteristics of this interface.
Note:
1.4.4
The 82580EB/DB does not support EEPROMless designs.
Serial Flash Interface
The 82580EB/DB provides an external SPI serial interface to a Flash or Boot ROM device such as the
Atmel* AT25F1024 or compatible Flash device (See Section 10.8.1 for full list of supported Flash
devices). The 82580EB/DB supports serial Flash devices with up to 64 Mbit (8 MByte) of memory. The
size of the Flash used by the 82580EB/DB can be configured by the EEPROM. See Section 2.1.2 for full
pin description and Section 10.6.2.4 for timing characteristics of this interface.
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Intel® 82580EB/82580DB GbE Controller — SMBus Interface
Note:
1.4.5
Though the 82580EB/DB supports devices with up to 8 MB of memory, bigger devices can
also be used. Accesses to memory beyond the Flash device size results in access wrapping
as only the lower address bits are used by the Flash device.
SMBus Interface
SMBus is an optional interface for pass-through and/or configuration traffic between a BMC and the
82580EB/DB. For best performance, each 82580EB/DB should have its own dedicated SMBus link to the
SMBus master device.
The 82580EB/DB's SMBus interface can be configured to support both slow and fast timing modes. See
Section 2.1.3 for full pin description and Section 10.6.2.2 for timing characteristics of this interface.
1.4.6
NC-SI Interface
NC-SI and SMBus interfaces are optional for pass-through and/or configuration traffic between a BMC
and the 82580EB/DB. The NC-SI interface meets the DMTF NC-SI Specification, Rev. 1.0.0a as an
integrated Network Controller (NC) device.
See Chapter 2.1.4 for full pin description and Chapter 10.6.2.6 for timing characteristics of this
interface.
1.4.7
MDIO/I2C 2 wires Interfaces
The 82580EB/DB implements four management Interfaces for control of an optional external PHY. Each
interface can be either a 2-wire Standard-mode I2C interface used to control an SFP module or an MII
Management Interface (also known as the Management Data Input/Output or MDIO Interface) for
control plane connection between the MAC and PHY devices (master side). This interface provides the
MAC and software with the ability to monitor and control the state of the external PHY. The 82580EB/DB
supports the data formats defined in IEEE 802.3 clause 22.
The 82580EB/DB supports shared MDIO operation and separate MDIO connection. When configured via
the MDICNFG register to separate MDIO operation each MDIO interface should be connected to the
relevant PHY. When configured via the MDICNFG register to shared MDIO operation the MDC/MDIO
interface of LAN port 0 can be shared by all ports to support connection to a multi-port PHY with a
single MDC/MDIO interface. See Section 2.1.7 for full pin description, Section 10.6.2.8 for MDIO timing
characteristics and Section 10.6.2.3 for I2C timing characteristics of this interface.
1.4.8
Software-Definable Pins (SDP) Interface (GeneralPurpose I/O)
The 82580EB/DB has four software-defined pins (SDP pins) per port that can be used for miscellaneous
hardware or software-control purposes. These pins can be individually configurable to act as either
standard inputs, general-purpose interrupt (GPI) inputs or output pins. The default direction of each pin
is configurable via the EEPROM (see Section 6.2.21, Section 7.2.1 and Section 7.2.3), as well as the
default value of all pins configured as outputs. Further information on SDP usage can be found in
Section 3.4 and Section 8.9.4. See Section 2.1.5 for pin description of this interface.
Intel® 82580EB/82580DB Gigabit Ethernet Controller
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LEDs Interface — Intel® 82580EB/82580DB GbE Controller
1.4.9
LEDs Interface
The 82580EB/DB implements four output drivers per port intended for driving external LED circuits.
Each of the four LED outputs can be individually configured to select the particular event, state, or
activity, which is indicated on that output. In addition, each LED can be individually configured for
output polarity as well as for blinking versus non-blinking (steady-state) indication.
The configuration for LED outputs is specified via the LEDCTL register. Furthermore, the hardwaredefault configuration for all LED outputs can be specified via EEPROM fields (see Section 6.2.18 and
Section 6.2.20), thereby supporting LED displays configurable to a particular OEM preference.
See Section 2.1.8.1 for full pin description of this interface.
See Section 8.5 for more detailed description of LED behavior.
1.5
Features
Table 1-2 to Table 1-7 list the 82580EB/DB's features and compares them to other LAD products .
Table 1-2.
82580EB/DB Network Features
Feature
Half duplex at 10/100 Mb/s operation and full duplex
operation at all supported speeds
10/100/1000 Copper PHY integrated on-chip
Jumbo frames supported
Size of jumbo frames supported
Flow control support: send/receive PAUSE frames and
receive FIFO thresholds
82580EB/DB
82599
82575
82576
Y
100 Mb/s full
duplex
Y
Y
4 ports
N
2 ports
2 ports
Y
Y
Y
Y
9.5 KB
16 KB
9.5 KB
9.5 KB
Y
Y
Y
Y
Statistics for management and RMON
Y
Y
Y
Y
802.1q VLAN support
Y
Y
Y
Y
4 ports
2 ports
2 ports
2 ports
Y
Y
N
N
SerDes interface for external PHY connection or system
interconnect
1000BASE-KX interface for Blade Server Backplane
connections
802.3ap Backplane Auto-negotiation
N
Y
N
N
SGMII interface for external 1000BASE-T PHY connection
4 ports
2 ports
2 ports
2 ports
Fiber/copper auto-sense
2 ports
4 ports
N/A
2 ports
SerDes support of non-Auto-Negotiation partner
Y
Y
Y
Y
SerDes signal detect
Y
N
Y
Y
Shared/ Per function
Per function
Per function
Per function
Per function
Per function
Per function
Per function
External PHY control I/F
- MDC/MDIO
- 2 wire I/F
Table 1-3.
82580EB/DB Host Interface Features (Sheet 1 of 2)
Feature
PCIe revision
PCIe physical layer
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82580EB/DB
82599
82575
82576
2.0 (5 Gbps or
2.5 Gbps)
2.0 (5 Gbps or
2.5 Gbps)
2.0 (2.5
Gbps)
2.0 (2.5
Gbps)
Gen 2
Gen 2
Gen 1
Gen 1
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Intel® 82580EB/82580DB GbE Controller — Features
Table 1-3.
82580EB/DB Host Interface Features (Sheet 2 of 2)
Bus width
x1, x2, x4
x1, x4, x8
x1, x2, x4
x1, x2, x4
Y
Y
N
Y
24 Per port and
for all ports
16
4
4
Outstanding requests for Tx descriptors per port
4 Per port and
for all ports
8
1
1
Outstanding requests for Rx descriptors per port
4 Per port and
for all ports
4
1
1
4
8
2
2
Max payload size supported
512 B
512 B
256 B
512 B
Max request size supported
2 KB
2 KB
512 B
512 B
Link layer retry buffer size
64-bit address support for systems using more than
4 GB of physical memory
Outstanding requests for Tx buffers per port
Credits for posted writes
3.2 KB
3.2 KB
2 KB
2 KB
Vital Product Data (VPD)
Y
Y
N
Y
End to End CRC (ECRC)
Y
Y
N
N
LTR (Latency Tolerance Reporting)
Y
N
N
N
TPH
Y
N
N
N
CSR access via Configuration space
Y
N
N
N
82580EB/DB
82599
82575
82576
Programmable host memory receive buffers
Y
Y
Y
Y
Descriptor ring management hardware for transmit and receive
Y
Y
Y
Y
ACPI register set and power down functionality supporting D0 &
D3 states
Y
Y
Y
Y
Software controlled global reset bit (resets everything except the
configuration registers)
Y
Y
Y
Y
Software Definable Pins (SDP) - per port
4
8
4
4
Four SDP pins can be configured as general purpose interrupts
Y
Y
Y
Y
Wake up
Y
Y
Y
Y
Flexible wake-up filters
8
6
4
6
Flexible filters for queue assignment in normal operation
8
N
N
N
Table 1-4.
82580EB/DB LAN Functions Features
Feature
IPv6 wake-up filters
Y
Y
Y
Y
4 LEDs
4 LEDs
4 LEDs
4 LEDs
LAN function disable capability
Y
Y
Y
Y
Programmable memory transmit buffers
Y
Y
Y
Y
Double VLAN
Y
Y
Y
Y
IEEE 1588
Y
Y
N
Y
Per-Packet Timestamp
Y
N
N
N
Default configuration by the EEPROM for all LEDs for pre-driver
functionality
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Features — Intel® 82580EB/82580DB GbE Controller
Table 1-5.
82580EB/DB LAN Performance Features
Feature
82580EB/DB
82599
82575
82576
Y
Y
Y
Y
iSCSI TCP segmentation offload (CRC)
N
Y
N
N
IPv6 support for IP/TCP and IP/UDP receive checksum offload
Y
Y
Y
Y
TCP segmentation offload
Up to 256 KB
Fragmented UDP checksum offload for packet reassembly
Y
Y
Y
Y
Message Signaled Interrupts (MSI)
Y
Y
Y
Y
Message Signaled Interrupts (MSI-X) number of vectors
10
256
10
25
Packet interrupt coalescing timers (packet timers) and absolutedelay interrupt timers for both transmit and receive operation
Y
Y
N
Y
Interrupt throttling control to limit maximum interrupt rate and
improve CPU utilization
Y
Y
Y
Y
Rx packet split header
Receive Side Scaling (RSS) number of queues per port
Total number of Rx queues per port
Total number of TX queues per port
Y
Y
Y
Y
Up to 8
Up to 16
4
Up to 16
8
128
4
16
8
128
4
16
Yes to all
Yes to all
Yes to all
Yes to all
TSO interleaving for reduced latency
Y
Y
N
Y
Receive side coalescing
N
Y
N
N
SCTP receive and transmit checksum offload
Y
Y
N
Y
UDP TSO
Y
Y
N
Y
IPSec offload
N
Y
N
Y
RX header replication
Low latency interrupt
DCA support
TCP timer interrupts
No snoop
Relax ordering
Table 1-6.
82580EB/DB Virtualization Features
Feature
Support for Virtual Machines Device queues (VMDq) per port
L2 MAC address filters (unicast and multicast)
L2 VLAN filters
PCI-SIG SR-IOV
Multicast/Broadcast Packet replication
82580EB/DB
82599
82575
82576
8 pools (single
queue)
16/32/64
pools
4 pools
8 pools
24
128
16
24
Per pool
64
-
Per pool
N
16/32/64 VF
N
8 VF
Y on Receive
Y
N
Y
VM to VM Packet forwarding (Packet Loopback)
N
Y
N
Y
RSS replication
N
Y
N
N
Traffic shaping
N
Y
N
Y
MAC and VLAN anti-spoofing
N
Y
N
Y
Malicious driver detection
Y
N
N
N
Per-pool statistics
Y
Y
N
Y
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Intel® 82580EB/82580DB GbE Controller — Overview of Changes Compared to the 82576
Table 1-6.
82580EB/DB Virtualization Features (Continued)
Feature
82580EB/DB
82599
82575
82576
Y
Y
Partial
Y
Per-pool off loads
Per-pool jumbo support
Y
Y
N
Y
Mirroring rules
4
4
0
4
Table 1-7.
82580EB/DB Manageability Features
Feature
82580EB/DB
82576
82599
Y
Y
Y
Managed ports on SMBus interface to external BMC
4
2
2
Fail-over support over SMBus
N
Y
Y
Auto-ARP reply over SMBus
N
Y
Y
NC-SI Interface to an External BMC
Y
Y
Y
Advanced pass-through-compatible management packet transmit/
receive support
DMTF NC-SI protocol standards support
Y
Y
Y
L2 address filters
2
4
4
VLAN L2 filters
8
8
8
EtherType filters
4
4
4
Flex L4 port filters
8
16
16
Flex TCO filters
1
4
4
L3 address filters (IPv4)
4
4
4
L3 address filters (IPv6)
4
4
4
1.6
Overview of Changes Compared to the 82576
The following section describes modifications done in the 82580EB/DB compared to the 82576.
1.6.1
1.6.1.1
Network Interface
Quad port
The 82580EB/DB supports 4 LAN ports (10/100/1000BASE-T on Serdes) and associated MAC and DMA
queues enabling reduction of BOM cost and board space when implementing quad port Ethernet NICs or
LOM designs.
1.6.1.2
Shared MDIO support
The 82580EB/DB enables sharing of the MDIO interface on LAN port 0 by all ports connected to an
external 1000BASE-T PHY to support connection to an external multi-port PHY device.
To abstract actual MDIO interface configuration from Software driver, MDIO setup (PHY Address,
External or Internal PHY and Shared MDIO) is loaded into the MDICNFG register from the EEPROM
following reset. Driver can issue read or write operation to the internal PHY registers using the MDIC
register, without a need to know actual MDIO configuration. Further information can be found in
Section 3.5.2.2 and Section 7.2.5.
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HOST Interface — Intel® 82580EB/82580DB GbE Controller
1.6.1.3
I2C Clock Stretching
There are situations where an I2C slave can not support the clock speed or needs to delay an access
initiated by the master. Delaying the access is done by a mechanism referred to as clock stretching. An
I2C slave is allowed to hold down the clock if it needs to delay an access. The master is required to read
back the clock signal after releasing it to a high-z state and wait until the line has actually gone high as
a result of an external Pull-up resistor.
When configured to operate in I2C mode, the 82580EB/DB supports clock stretching on the I2C_CLK
pin. When accessing PHY registers via the I2C interface the PHY can delay the access or reduce clock
speed if required.
1.6.1.4
1000BASE-KX Backplane Ethernet Interface
The 82580EB/DB can interface up to four 1Gbps 1000BASE-KX lanes for Blade Server backplane
interconnect without need for additional glue logic. The 82580EB/DB supports only parallel detection of
1000BASE-KX signaling and does not support the full Auto-Negotiation for Backplane Ethernet protocol.
1.6.2
1.6.2.1
HOST Interface
PCIe v2.0 (5Gbps and 2.5Gbps) Link speed
The 82580EB/DB supports X4, X2 and X1 PCIe v2.0 (5Gbps and 2.5Gbps) port configurations.
1.6.2.2
ECRC
The 82580EB/DB supports generation and checking of ECRC on PCI-Express traffic.
1.6.2.3
64 bit BARs support
The 82580EB/DB 64 bit BAR support modified to be similar to the 82599.
1.6.2.4
MSI-X Support
Number of MSI-X vectors supported by the 82580EB/DB changed to 10.
1.6.2.5
Outstanding Requests and Credits
Following changes to the outstanding request count and credits are implemented in the 82580EB/DB:
• Outstanding requests for TX buffers increased to 24 to improve small packet TX performance. Each
function can generate up to 24 TX buffer outstanding requests, but sum of outstanding TX Buffer
requests generated by all functions can not pass 24.
• Outstanding requests for TX descriptor fetch increased to 4. Each function can generate up to 4 TX
descriptor fetch outstanding requests, but sum of TX descriptor fetch outstanding requests
generated by all functions can not pass 4.
• Outstanding requests for RX descriptor fetch increased to 4. Each function can generate up to 4 RX
descriptor fetch outstanding requests, but sum of RX descriptor fetch outstanding requests
generated by all functions can not pass 4.
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Intel® 82580EB/82580DB GbE Controller — Boundary Scan
• Number of Credits for posted writes has been increased from 2 to 4.
1.6.2.6
CSR Access Via Configuration Space
Server systems run into scaling issues when adding a large number of PCIe cards that require IO
address resources. IO addresses on the PCIe interface are limited to 64K of addresses for all PCIe
devices by legacy definition. Furthermore, although the 82580EB/DB only needs two 32-bit registers (8
bytes), the device must allocate 32 bytes per-function in IO space. Lastly, the PCI Bridge specification
requires a granularity of 4K allocation per PCI segment for IO space (dividing the 64K address space
into at most 16 segments).
The BIOS may further reduce the available IO space by allocating IO space in a sub-optimal manner
(e.g. lots of space in one 16KB chunk, but exhausted in another) due to need to support required
legacy IO offsets such as mouse/keyboard or POST code ports.
Networking products only require IO space to support 'legacy' 16-bit operating environments where
memory-mapped PCIe device CSRs (e.g. big 32-bit or 64-bit address offsets) can't be mapped
arbitrarily into the 16-bit address space of the executable environment. These legacy environments
happen to include pre-boot BIOS environments - such as what PXE and 16-bit iSCSI boot are designed
for modern platforms using EFI BIOS components do not need IO mode. Modern operating systems
also do not need IO mode.
To support legacy pre-boot 16-bit operating environments without requiring IO address space, the
82580EB/DB enables accessing CSRs via configuration address space using the IOADDR (Configuration
address 0x98) and IODATA (Configuration address 0x9C). See Section 7.1.1.6 and Section 9.5.4.1 for
further information.
1.6.3
Boundary Scan
In addition to support of the IEEE 1149.1 boundary scan standard the 82580EB/DB supports the IEEE
1149.6 boundary scan standard to enable testing of it’s high speed differential interfaces.
1.6.4
1.6.4.1
Performance Features
TLP Process Hints (TPH) Support
The 82580EB/DB supports the TPH capability defined in the PCI Express specification. It can provide
hints to the root complex about the destination cache of DMA memory writes or instruct the root
complex to read specific type of traffic directly from the cache. See Section 8.7.2 for more information.
1.6.5
Receive and Transmit Queues
The number of Receive and Transmit queues supported by the 82580EB/DB for RSS filtering and
Virtualization is 8 per port.
1.6.5.1
Unused Receive and Transmit Ports Buffer Sharing
The 82580EB/DB supports up to 4 Gigabit Ethernet ports. When device is configured to work only as a
single port or dual port device, available internal receive and transmit buffer memory for the remaining
active ports, can be increased by four for the single port case and by two for the dual port case.
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Virtualization — Intel® 82580EB/82580DB GbE Controller
See Section 8.1.3.2 and Section 8.2.1.2 for more information.
1.6.6
Virtualization
The 82580EB/DB does not support the following virtualization features previously supported by the
82576:
• PCIe SR-IOV
• VM to VM packet forwarding
• Anti-Spoof protection
The 82580EB/DB supports 8 queues per port that can be shared between eight virtual machines
(VMDq1). By associating receive and transmit packets to separate queues dedicated to a VM,
performance of the VMM (Virtual Machine Monitor) is improved. The 82580EB/DB also supports the
following hardware Virtualization features:
• Per VM interrupt assignment
• Enabling read of statistic counters by VMs without initiating a clear by read
• Copy of received multicast and broadcast packets to multiple queues
• Per VM Offload
• Per Pool statistics
• Mirroring
• Storm Control
1.6.7
Malicious Driver Detection
Malicious behavior exhibited by the driver can be a result of incorrect activation of the network
controller or a virus on a certain VM. The 82580EB/DB contains internal circuitry to protect from an
attack on one virtual machine disrupting operation of other virtual machines. When malicious driver
behavior is detected on a certain queue, the 82580EB/DB disables activity of the queue and sends
notification to the VMM. See Section 8.8.2.8.2 for details.
1.6.8
2-tuple filtering
The 82580EB/DB supports only 2-tuple filtering compared to previous products that supported 5-tuple
filtering. The 82580EB/DB enables queuing, generating immediate interrupts and time stamping
according to TCP/UDP port destination address and L4 protocol fields. See Section 8.1.1 and
Section 8.1.1.5 for more information.
1.6.9
Security Offload
The 82580EB/DB does not support the IPSec and LinkSec offload features that were previously
supported by the 82576.
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Intel® 82580EB/82580DB GbE Controller — Quality of Service
1.6.10
1.6.10.1
Quality of Service
DCE and BCN
The 82580EB/DB does not support the (Data Center Ethernet) and Backward Congestion Notification
(BCN) features that were previously supported by 82576.
1.6.10.2
Transmit Queue Prioritization
The 82580EB/DB supports strict Transmit queue prioritization to enable transmission of high priority
real-time packets ahead of low priority packets. A Transmit queue is either a high priority queue or low
priority queue, with the high priority queues always served ahead of the low priority queues. See
Section 8.2.2.5 for information.
1.6.11
1.6.11.1
Manageability
SMBus Interface to External BMC
The 82580EB/DB supports 4 managed ports on SMBus interface to external BMC.
1.6.11.1.1
Teaming and Fail-over on SMBus
The LAN ports act independently of each other and each port has a separate SMBus address. As a
result, fail-over where manageability traffic is routed to an active port if any of the ports fail, is not
supported internally. The BMC is responsible for teaming and fail-over.
1.6.11.1.2
Auto-ARP Reply on SMBus
The 82580EB/DB can not be programmed for auto-ARP reply on reception of ARP request packets and
does not support sending of gratuitous ARP packets to reduce the traffic over the BMC interconnect.
1.6.11.2
NC-SI Interface to External BMC
The 82580EB/DB supports 4 managed ports on NC-SI interface to external BMC.
The 82580EB/DB supports the DMTF NC-SI Specification, revision 1.0.0a, as a PHY-side device based
on NC-SI specification, revision 1.2, similar to the 82576. However, the 82580EB/DB does not support
the MII protocol over the NC-SI pins.
1.6.11.2.1
NC-SI Commands.
Support for the NC-SI Get Controller Packet Statistics command was added in the 82580EB/DB.
Support for filtering related NC-SI commands and NC-SI flow control were removed. See Section 11.2.1
and Section 11.3.1 for supported NC-SI commands.
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Embedded Features — Intel® 82580EB/82580DB GbE Controller
1.6.11.2.2
NC-SI Hardware Arbitration
The 82580EB/DB does not support NC-SI HW arbitration between different Network Controller
packages. Arbitration is done by the BMC Software. Only one package can be in the Selected state at a
time. Otherwise, hardware electrical buffer conflicts will occur between packages.
1.6.11.3
Management Filtering
Quantity of management filters per port in the 82580EB/DB is reduced compared to the 82576.
Changes in amount of management filters is shown in Table 1-8.
Table 1-8.
Management Filters Reduction Per Port
Filter Type
82576 Filters
82580EB/DB Filters
Destination MAC address (6-bytes)
4
2
UDP/TCP port (16-bit)
16
8
Flexible (128-byte)
4
1
Description of management filters supported in the 82580EB/DB can be found in Section 7.22 and
Section 11.4.
Note:
On the 82580EB/DB, each MAC address is programmed individually.
1.6.11.4
Exclusive Management Filtering
In previous network controller chips the BMC needed to define which packets that were destined to
management should also be forwarded to the host. In the 82580EB/DB, decisions regarding forwarding
of packets to the host and to the BMC are separate and are configured through two sets of registers.
However, the BMC may define some types of traffic as exclusive. This traffic will be forwarded only to
the BMC, even if it passes the filtering process of the host. These types of traffic are defined using the
MNGONLY register. Further information can be found in Section 8.1.2.3 and Section 11.4.1.
1.6.12
1.6.12.1
Embedded Features
Flex Filters
Two additional Flex filters were added to the 82580EB/DB, making a total of 8 flexible filters. In addition
to Wake-on-Lan (WoL) activity, flex filters in the 82580EB/DB can also be used for queuing decisions in
normal (D0) operating mode. See Section 5.6.3.2 and Section 8.1.1.6 for more information.
1.6.12.2
Time SYNC (IEEE1588 and IEEE 802.1AS)
Though the 82580EB/DB supports the 1588 protocol standard, the device driver does not. Each
application is unique and requires customers to develop their own custom driver to support this feature.
1.6.12.2.1
Per Packet Timestamp
The 82580EB/DB supports adding an optional tailored header before the MAC header of the packet in
the receive buffer. The 128 bit tailored header contains a 64 bit timestamp (MSB bits) and 64 reserved
bits (LSB bits).
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Intel® 82580EB/82580DB GbE Controller — Power Saving
The timestamp is sampled on the MAC/PHY interface, on detection of a received packet that meets
certain criteria. Time stamping the received packet on the PHY/MAC interface avoids incurring
additional delays due to PCIe latencies. The timestamp is placed in the receive buffer ahead of the
actual received packet. See Section 8.1.10 for more information.
1.6.12.2.2
Improved System Time Accuracy
System time accuracy has been increased in the 82580EB/DB. System time Corrections with a
resolution of 2-32 ns can be entered using the TIMINCA.Incvalue field (see Section 8.9.3 for further
information). The structure of system-related registers has been modified to enable improved accuracy.
1.6.12.2.3
SYSTIM Synchronized Pulse Generation on SDP pins
Capability to generate a pulse synchronized to system time has been added to the 82580EB/DB. See
Section 8.9.4.1.2 for more information.
1.6.12.2.4
Time SYNC Interrupts
Additional capability to generate interrupts on occurrence of Time Sync events has been added to the
82580EB/DB. See Section 8.9.5 for more information.
1.6.13
1.6.13.1
Power Saving
DMA Coalescing
The 82580EB/DB supports DMA Coalescing to enable synchronizing device activity and optimize power
management of memory, CPU and RC internal circuitry. By synchronizing PCIe activity between ports
and shaping traffic on PCIe link to increase duration of idle periods, system can stay in lower power
states for a longer duration and reduce overall power consumption.
When in DMA Coalescing (Buffer Fill) operating mode, PCIe link is optionally placed in L1 power saving
state and DMA activity is placed on hold. The 82580EB/DB moves into Buffer Flush mode when internal
receive buffers pass a pre-determined threshold value, a watchdog timer expires, or the PCIe interface
invokes a move out of DMA Coalescing state. See Section 5.7.
1.6.13.2
Latency Tolerance Reporting (LTR)
The 82580EB/DB supports PCIe LTR messages to enable report of service latency and bandwidth
requirements for memory reads and writes to the Root Complex. LTR messaging support enables
central platform resources (such as main memory, RC internal interconnects, snoop resources, and
such) to be power managed without impacting Endpoint functionality and performance. See
Section 5.8.
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Device Data Flows — Intel® 82580EB/82580DB GbE Controller
1.7
Device Data Flows
1.7.1
Transmit Data Flow
Table 1-9 provides a high level description of all data/control transformation steps needed for sending
Ethernet packets to the line.
Table 1-9.
Transmit Data Flow
Step
Description
1
The host creates a descriptor ring and configures one of the 82580EB/DB's transmit queues with the address
location, length, head and tail pointers of the ring (one of 8 available Tx queues).
2
The host is requested by the TCP/IP stack to transmit a packet, it gets the packet data within one or more data
buffers.
3
The host initializes descriptor(s) that point to the data buffer(s) and have additional control parameters that
describe the needed hardware functionality. The host places that descriptor in the correct location at the
appropriate Tx ring.
4
The host updates the appropriate queue tail pointer (TDT)
5
The 82580EB/DB's DMA senses a change of a specific TDT and as a result sends a PCIe request to fetch the
descriptor(s) from host memory.
6
The descriptor(s) content is received in a PCIe read completion and is written to the appropriate location in the
descriptor queue internal cache.
7
The DMA fetches the next descriptor from the internal cache and processes its content. As a result, the DMA sends
PCIe requests to fetch the packet data from system memory.
8
The packet data is received from PCIe completions and passes through the transmit DMA that performs all
programmed data manipulations (various CPU off loading tasks as checksum off load, TSO off load, etc.) on the
packet data on the fly.
9
While the packet is passing through the DMA, it is stored into the transmit FIFO. After the entire packet is stored in
the transmit FIFO, it is forwarded to the transmit switch module.
10
The transmit switch arbitrates between host and management packets and eventually forwards the packet to the
MAC.
11
The MAC appends the L2 CRC to the packet and sends the packet to the line using a pre-configured interface.
12
When all the PCIe completions for a given packet are done, the DMA updates the appropriate descriptor(s).
13
After enough descriptors are gathered for write back or the interrupt moderation timer expires, the descriptors are
written back to host memory using PCIe posted writes. Alternatively, the head pointer can only be written back.
14
After the interrupt moderation timer expires, an interrupt is generated to notify the host device driver that the
specific packet has been read to the 82580EB/DB and the driver can release the buffers.
1.7.2
Receive Data Flow
Table 1-10 provides a high level description of all data/control transformation steps needed for
receiving Ethernet packets.
Table 1-10.
Step
Receive Data Flow
Description
1
The host creates a descriptor ring and configures one of the 82580EB/DB's receive queues with the address
location, length, head, and tail pointers of the ring (one of 8 available Rx queues).
2
The host initializes descriptors that point to empty data buffers. The host places these descriptors in the correct
location at the appropriate Rx ring.
3
The host updates the appropriate queue tail pointer (RDT).
4
The 82580EB/DB's DMA senses a change of a specific RDT and as a result sends a PCIe request to fetch the
descriptors from host memory.
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Intel® 82580EB/82580DB GbE Controller — Receive Data Flow
Table 1-10.
Receive Data Flow (Continued)
Step
Description
5
The descriptors content is received in a PCIe read completion and is written to the appropriate location in the
descriptor queue internal cache.
6
A packet enters the Rx MAC. The RX MAC checks the CRC of the packet.
7
The MAC forwards the packet to an Rx filter
8
If the packet matches the pre-programmed criteria of the Rx filtering, it is forwarded to the Rx FIFO. VLAN and
CRC are optionally stripped from the packet and L3/L4 checksum are checked and the destination queue is fixed.
9
The receive DMA fetches the next descriptor from the internal cache of the appropriate queue to be used for the
next received packet.
10
After the entire packet is placed into the Rx FIFO, the receive DMA posts the packet data to the location indicated
by the descriptor through the PCIe interface. If the packet size is greater than the buffer size, more descriptors are
fetched and their buffers are used for the received packet.
11
When the packet is placed into host memory, the receive DMA updates all the descriptor(s) that were used by
packet data.
12
After enough descriptors are gathered for write back or the interrupt moderation timer expires or the packet
requires immediate forwarding, the receive DMA writes back the descriptor content along with status bits that
indicate the packet information including what off loads were done on that packet.
13
After the interrupt moderation timer completes or an immediate packet is received, the 82580EB/DB initiates an
interrupt to the host to indicate that a new received packet is already in host memory.
14
Host reads the packet data and sends it to the TCP/IP stack for further processing. The host releases the
associated buffers and descriptors once they are no longer in use.
§§
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Pin Interface — Intel® 82580EB/82580DB GbE Controller
2.0
Pin Interface
2.1
Pin Assignment
The 82580EB/DB is packaged in a 17x17 PBGA package with 1.0 mm ball pitch. The pin count (or ball
count) is 256.
Table 2-1.
Signal Type Definition
Type
Description
DC specification
In
LVTTL input-only signal.
See Section 10.6.1.1
Out
LVTTL Output active driver.
See Section 10.6.1.1 and Section 10.6.1.2
T/S
LVTTL bi-directional, tri-state input/output pin.
See Section 10.6.1.1
O/D
Open Drain allows multiple devices to share line
using wired-OR configuration.
See Section 10.6.1.3
NC-SI-in
NC-SI compliant input signal
See Section 10.6.1.4
NC-SI-out
NC-SI compliant output signal
See Section 10.6.1.4
A
Analog signals
See Section 10.6.4
A-in
Analog input signals
See Section 10.6.3
A-out
Analog output signals
See Section 10.6.3
B
Input bias
See Section 10.6.7 and Section 10.6.8
PS
Power Supply
2.1.1
PCIe
The AC specification for these pins is described in Section 10.6.2.10.
Table 2-2.
Reserved
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PCIe Pins
Symbol
Ball #
PE_CLK_p
A16
PE_CLK_n
A15
PET_0_p
A12
PET_0_n
B12
PET_1_p
A11
PET_1_n
B11
PET_2_p
A6
PET_2_n
B6
PET_3_p
A5
PET_3_n
B5
Type
Name and Function
A-in
PCIe Differential Reference Clock in: A 100MHz
differential clock input. This clock is used as the
reference clock for the PCIe Tx/Rx circuitry and by the
PCIe core PLL to generate clocks for the PCIe core logic.
A-out
PCIe Serial Data output Lane 0: A serial differential
output pair running at a bit rate of 2.5Gb/s or 5Gb/s.
A-out
PCIe Serial Data output Lane 1: A serial differential
output pair running at a bit rate of 2.5Gb/s or 5Gb/s.
A-out
PCIe Serial Data output Lane 2: A serial differential
output pair running at a bit rate of 2.5 Gb/s or 5Gb/s.
A-out
PCIe Serial Data output Lane 3: A serial differential
output pair running at a bit rate of 2.5Gb/s or 5Gb/s.
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Intel® 82580EB/82580DB GbE Controller — Flash and EEPROM Ports
Table 2-2.
PCIe Pins (Continued)
Reserved
Symbol
Ball #
PER_0_p
A14
PER_0_n
B14
PER_1_p
A9
PER_1_n
B9
PER_2_p
A8
PER_2_n
B8
PER_3_p
A3
PER_3_n
B3
PE_WAKE_N
PE_RST_N
Type
Name and Function
A-in
PCIe Serial Data input Lane 0: A Serial differential input
pair running at a bit rate of 2.5Gb/s or 5Gb/s.
A-in
PCIe Serial Data input Lane 1: A Serial differential input
pair running at a bit rate of 2.5Gb/s or 5Gb/s.
A-in
PCIe Serial Data input Lane 2: A Serial differential input
pair running at a bit rate of 2.5Gb/s or 5Gb/s.
A-in
PCIe Serial Data input Lane 3: A Serial differential input
pair running at a bit rate of 2.5Gb/s or 5Gb/s.
D16
O/D
WAKE#: Active low signal pulled to ‘0’ to indicate that a
Power Management Event (PME) is pending and the PCI
Express link should be restored. Defined in the PCI
Express CEM specification.
B1
In
PERST#: Active low PCI Express fundamental reset
input. When pulled to ‘0’ resets chip and when deasserted (set to ‘1’) indicates that power and PCI
Express reference clock are within specified values.
Defined in the PCI Express specification.
On exit from reset all registers and state machines are
set to their initialization values.
2.1.2
PE_TXVTERM1
C6
PE_TXVTERM2
C8
PE_TXVTERM3
C9
PE_TXVTERM4
C11
PE_TRIM1
A2
PE_TRIM2
A1
A-in
A
Should be connected to 1.8V power supply for
termination
PCIe Trimming
A 1.5K 1% resistor connected between these pins.
Flash and EEPROM Ports
The AC specification for these pins is described in Section 10.6.2.4 to Section 10.6.2.5.
Table 2-3.
Reserved
Flash and EEPROM Ports Pins
Symbol
Ball #
Type
Name and Function
FLSH_SI
B15
T/S
Serial Data output to the Flash
FLSH_SO
C15
In
Serial Data input from the Flash
FLSH_SCK
B16
T/S
Flash serial clock Operates at 15.625MHz.
FLSH_CE_N
C16
T/S
Flash chip select Output
EE_DI
E15
T/S
Data output to EEPROM
EE_DO
F15
In
Data input from EEPROM
EE_SK
E16
T/S
EEPROM serial clock output Operates at ~2 MHz.
EE_CS_N
F16
T/S
EEPROM chip select Output
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Revision: 2.50
October 2011
System Management Bus (SMB) Interface — Intel® 82580EB/82580DB GbE Controller
2.1.3
System Management Bus (SMB) Interface
The AC specification for these pins is described in Section 10.6.2.2.
Table 2-4.
SMB Interface Pins
Symbol
2.1.4
Ball #
Type
Name and Function
SMBD
G3
T/S, O/D
SMB Data. Stable during the high period of the clock (unless
it is a start or stop condition).
SMBCLK
E5
T/S, O/D
SMB Clock. One clock pulse is generated for each data bit
transferred.
SMBALRT_N
G4
T/S, O/D
SMB Alert: acts as an Interrupt pin of a slave device on the
SMB
NC-SI Interface Pins
The AC specification for these pins is described in Section 10.6.2.6.
Table 2-5.
Reserved
NC-SI Interface Pins
Symbol
NCSI_CLK_IN
Ball #
H1
Type
NC-SI-In
Name and Function
NC-SI Reference Clock Input – Synchronous clock reference
for receive, transmit and control interface. It is a 50MHz
clock /- 50 ppm.
Note: When the 82580EB/DB drives the NC-SI clock
NCSI_CLK_IN should be connected to NCSI_CLK_OUT pin
on-board.
Revision: 2.50
October 2011
NCSI_CLK_OUT
H2
NC-SI-Out
NC-SI Reference Clock Output – Synchronous clock
reference for receive, transmit and control interface. It is a
50MHz clock /- 50 ppm. Serves as a clock source to the
BMC and the 82580EB/DB (when configured so).
NCSI_CRS_DV
H3
NC-SI-Out
CRS/DV – Carrier Sense / Receive Data Valid.
NCSI_RXD_1
J1
NC-SI-Out
NCSI_RXD_0
H4
NCSI_TX_EN
J2
NC-SI-In
Transmit Enable.
NCSI_TXD_1
J4
NC-SI-In
Transmit Data.
NCSI_TXD_0
J3
Receive Data.
Data signals from the 82580EB/DB to BMC.
Data signals from BMC to the 82580EB/DB.
Intel® 82580EB/82580DB Gigabit Ethernet Controller
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Intel® 82580EB/82580DB GbE Controller — Miscellaneous Pins
2.1.5
Miscellaneous Pins
The AC specification for the XTAL pins is described in sections 10.6.5.
Table 2-6.
Reserved
Miscellaneous Pins
Symbol
Ball #
SDP0_0
K1
SDP0_1
K2
SDP0_2
K3
SDP0_3
K4
SDP1_0
L1
SDP1_1
L2
SDP1_2
L3
SDP1_3
L4
SDP2_0
M1
SDP2_1
M2
SDP2_2
M3
SDP2_3
M4
SDP3_0
N1
SDP3_1
N2
SDP3_2
N3
SDP3_3
N4
TSENSP
D5
Type
Name and Function
T/S
SW Defined Pins for port 0: These pins are reserved
pins that are software programmable write/read
input/output capability. These default to inputs upon
power up, but may have their direction and output
values defined in the EEPROM. The SDP bits may be
mapped to the General Purpose Interrupt bits when
configured as inputs. The SDP0[0] pin can be used
as a watchdog output indication. All the SDP pins
can be used as SFP sideband signals (TxDisable,
present & TxFault). The 82580EB/DB does not use
these signals; it is available for SW control over SFP.
T/S
SW Defined Pins for port 1: Reserved pins that are
software programmable write/read input/output
capability. These default to inputs upon power up,
but may have their direction and output values
defined in the EEPROM. The SDP bits may be
mapped to the General Purpose Interrupt bits when
configured as inputs. The SDP1[0] pin can be used
as a watchdog output indication. All the SDP pins
can be used as SFP sideband signals (TxDisable,
present & TxFault). The 82580EB/DB does not
generate these signals; it is available for SW control
over SFP.
T/S
SW Defined Pins for port 2: These pins are reserved
pins that are software programmable write/read
input/output capability. These default to inputs upon
power up, but may have their direction and output
values defined in the EEPROM. The SDP bits may be
mapped to the General Purpose Interrupt bits when
configured as inputs. The SDP2[0] pin can be used
as a watchdog output indication. All the SDP pins
can be used as SFP sideband signals (TxDisable,
present & TxFault). The 82580EB/DB does not
generate these signals; it is available for SW control
over SFP.
T/S
SW Defined Pins for port 3: These pins are reserved
pins that are software programmable write/read
input/output capability. These default to inputs upon
power up, but may have their direction and output
values defined in the EEPROM. The SDP bits may be
mapped to the General Purpose Interrupt bits when
configured as inputs. The SDP3[0] pin can be used
as a watchdog output indication. All the SDP pins
can be used as SFP sideband signals (TxDisable,
present & TxFault). The 82580EB/DB does not
generate these signals; it is available for SW control
over SFP.
A-out
Thermal Sensor output; Can be used to measure the
82580EB/DB on-die temperature.
Note:
The TSENSP/Z pins can be used to
measure temperature, but should only be
used in the lab for measurement/
characterization purposes. For detail, see
Chapter 13.0.
TSENSZ
C5
GND
Thermal Sensor Ground.
LAN_PWR_GOOD
D4
In
LAN Power Good: A 3.3v input signal. A transition
from low to high initializes the device into operation.
If the internal Power-on-Reset circuit is used to
trigger device power-up, this signal should be
connected to VCC3P3.
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Datasheet
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Revision: 2.50
October 2011
SERDES/SGMII Pins — Intel® 82580EB/82580DB GbE Controller
Table 2-6.
Miscellaneous Pins
Reserved
2.1.6
Symbol
Ball #
Type
Name and Function
MAIN_PWR_OK
B2
In
Main Power OK – Indicates that platform main
power is up. Must be connected externally to main
core 3.3V power.
DEV_OFF_N
C4
In
Device Off: Assertion of DEV_OFF_N puts the device
in Device Disable mode. This pin is asynchronous
and is sampled once the EEPROM is ready to be read
following power-up. The DEV_OFF_N pin should
always be connected to VCC3P3 to enable device
operation.
XTAL1
P1
A-In
XTAL2
P2
A-out
Reference Clock / XTAL: These pins may be driven
by an external 25MHz crystal or driven by a single
ended external CMOS compliant 25MHz oscillator.
SERDES/SGMII Pins
The AC specification for these pins is described in Section 10.6.3.
Table 2-7.
Reserved
SERDES/SGMII Pins
Symbol
Ball #
SER0_p
P16
SER0_n
P15
SET0_p
R16
SET0_n
R15
SRDS_0_SIG_DET
N13
Type
A-in
Name and Function
SERDES/SGMII Serial Data input Port 0: Differential
SERDES Receive interface.
A Serial differential input pair running at 1.25Gb/s. An
embedded clock present in this input is recovered
along with the data.
A-out
SERDES/SGMII Serial Data output Port 0: Differential
SERDES Transmit interface.
A serial differential output pair running at 1.25Gb/s.
This output carries both data and an embedded
1.25GHz clock that is recovered along with data at the
receiving end.
In
Port 0 Signal Detect: Indicates that signal (light) is
detected from the Fiber. High for signal detect, Low
otherwise.
Polarity of Signal Detect pin is controlled by
CTRL.ILOS bit.
For non-fiber serdes applications link indication is
internal (The CONNSW.ENRGSRC register bit is
cleared to 0b) and pin should be connected to a pullup resistor.
Revision: 2.50
October 2011
SER1_p
M16
SER1_n
M15
SET1_p
N16
SET1_n
N15
A-in
SERDES/SGMII Serial Data input Port 1: Differential
fiber SERDES Receive interface.
A Serial differential input pair running at 1.25Gb/s. An
embedded clock present in this input is recovered
along with the data.
A-out
SERDES/SGMII Serial Data output Port 1: Differential
fiber SERDES Transmit interface.
A serial differential output pair running at 1.25Gb/s.
This output carries both data and an embedded
1.25GHz clock that is recovered along with data at the
receiving end.
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Datasheet
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Intel® 82580EB/82580DB GbE Controller — SERDES/SGMII Pins
Table 2-7.
Reserved
SERDES/SGMII Pins (Continued)
Symbol
SRDS_1_SIG_DET
Ball #
P14
Type
In
Name and Function
Port 1 Signal Detect: Indicates that signal (light) is
detected from the fiber. High for signal detect, Low
otherwise.
Polarity of Signal Detect pin is controlled by
CTRL.ILOS bit.
For non-fiber serdes applications link indication is
internal (The CONNSW.ENRGSRC register bit is
cleared to 0b) and pin should be connected to a pullup resistor.
SER2_p*
K16
SER2_n*
K15
A-in
SERDES/SGMII Serial Data input Port 2: Differential
SERDES Receive interface.
A Serial differential input pair running at 1.25Gb/s. An
embedded clock present in this input is recovered
along with the data.
* This port can be left unconnected in the dual port
82580DB.
SET2_p*
L16
SET2_n*
L15
A-out
SERDES/SGMII Serial Data output Port 2: Differential
SERDES Transmit interface.
A serial differential output pair running at 1.25Gb/s.
This output carries both data and an embedded
1.25GHz clock that is recovered along with data at the
receiving end.
* This port can be left unconnected in the dual port
82580DB.
SRDS_2_SIG_DET*
T15
In
Port 2 Signal Detect: Indicates that signal (light) is
detected from the Fiber. High for signal detect, Low
otherwise.
Polarity of Signal Detect pin is controlled by
CTRL.ILOS bit.
For non-fiber serdes applications link indication is
internal (The CONNSW.ENRGSRC register bit is
cleared to 0b) and pin should be connected to a pullup resistor.
* This port can be left unconnected in the dual port
82580DB.
SER3_p*
H16
SER3_n*
H15
A-in
SERDES/SGMII Serial Data input Port 3: Differential
SERDES Receive interface.
A Serial differential input pair running at 1.25Gb/s. An
embedded clock present in this input is recovered
along with the data.
* This port can be left unconnected in the dual port
82580DB.
Intel® 82580EB/82580DB Gigabit Ethernet Controller
Datasheet
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Revision: 2.50
October 2011
SFP Pins — Intel® 82580EB/82580DB GbE Controller
Table 2-7.
SERDES/SGMII Pins (Continued)
Reserved
Symbol
Ball #
SET3_p*
J16
SET3_n*
J15
Type
A-out
Name and Function
SERDES/SGMII Serial Data output Port 3: Differential
SERDES Transmit interface.
A serial differential output pair running at 1.25Gb/s.
This output carries both data and an embedded
1.25GHz clock that is recovered along with data at the
receiving end.
* This port can be left unconnected in the dual port
82580DB.
SRDS_3_SIG_DET*
T16
In
Port 3 Signal Detect: Indicates that signal (light) is
detected from the Fiber. High for signal detect, Low
otherwise.
Polarity of Signal Detect pin is controlled by
CTRL.ILOS bit.
For non-fiber serdes applications link indication is
internal (The CONNSW.ENRGSRC register bit is
cleared to 0b) and pin should be connected to a pullup resistor.
* This port can be left unconnected in the dual port
82580DB.
SE_RSET
K13
B
SerDes Bias
Connect 2.37K 1% resistor between pin and ground.
2.1.7
SFP Pins
The AC specification for these pins is described in Section 10.6.2.9.
Table 2-8.
Reserved
SFP Pins
Symbol
Ball #
Type
Name and Function
SFP0_I2C_CLK
M13
Out, O/D
Port 0 SFP 2 wire interface clock – connects to
Mod-Def1 input of SFP (O/D). Can also be used
as MDC pin (Out).
SFP0_I2C_DATA
J13
T/S, O/D
Port 0 SFP 2 wire interface data – connects to
Mod-Def2 pin of SFP (O/D). Can also be used as
MDIO pin (T/S).
SFP1_I2C_CLK
M14
Out, O/D
Port 1 SFP 2 wire interface clock – connects to
Mod-Def1 input of SFP (O/D). Can also be used
as MDC pin (Out).
SFP1_I2C_DATA
N14
T/S, O/D
Port 1 SFP 2 wire interface data – connects to
Mod-Def2 pin of SFP (O/D). Can also be used as
MDIO pin (T/S).
SFP2_I2C_CLK*
J14
Out, O/D
Port 2 SFP 2 wire interface clock – connects to
Mod-Def1 input of SFP (O/D). Can also be used
as MDC pin (Out).
* This port can be left unconnected in the dual
port 82580DB.
Revision: 2.50
October 2011
Intel® 82580EB/82580DB Gigabit Ethernet Controller
Datasheet
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Intel® 82580EB/82580DB GbE Controller — PHY Pins
Table 2-8.
SFP Pins (Continued)
Reserved
Symbol
Ball #
SFP2_I2C_DATA*
H13
Type
T/S, O/D
Name and Function
Port 2 SFP 2 wire interface data – connects to
Mod-Def2 pin of SFP (O/D). Can also be used as
MDIO pin (T/S).
* This port can be left unconnected in the dual
port 82580DB.
SFP3_I2C_CLK*
H14
Out, O/D
Port 3 SFP 2 wire interface clock – connects to
Mod-Def1 input of SFP (O/D). Can also be used
as MDC pin (Out).
* This port can be left unconnected in the dual
port 82580DB.
SFP3_I2C_DATA*
G16
T/S, O/D
Port 3 SFP 2 wire interface data – connects to
Mod-Def2 pin of SFP (O/D). Can also be used as
MDIO pin (T/S).
* This port can be left unconnected in the dual
port 82580DB.
2.1.8
2.1.8.1
PHY Pins
LED’s
The table below describes the functionality of the LED output pins. Default activity of the LED may be
modified in the EEPROM word offsets 1Ch and 1Fh from start of relevant LAN Port section. The LED
functionality is reflected and can be further modified in the configuration registers LEDCTL.
Table 2-9.
LED Output Pins
Reserved
Symbol
LED0_0
Ball #
C1
Type
Out
Name and Function
Port 0 LED0. Programmable LED which indicates
by default Link Up.
Note:
LED0_1
C2
Out
Port 0 LED1. Programmable LED which indicates
by default activity (when packets are transmitted
or received that match MAC filtering).
Note:
LED0_2
C3
Out
E4
Out
Pin is active low by default, can be
programmed via EEPROM (See
Section 6.2.20) or LEDCTL register (See
Section 7.2.9).
Port 0 LED3. Programmable LED which indicates
by default a 1000Mbps Link.
Note:
Intel® 82580EB/82580DB Gigabit Ethernet Controller
Datasheet
44
Pin is active low by default, can be
programmed via EEPROM (See
Section 6.2.18) or LEDCTL register (See
Section 7.2.9).
Port 0 LED2. Programmable LED which indicates
by default a 100Mbps Link.
Note:
LED0_3
Pin is active low by default, can be
programmed via EEPROM (See
Section 6.2.20) or LEDCTL register (See
Section 7.2.9).
Pin is active low by default, can be
programmed via EEPROM (See
Section 6.2.18) or LEDCTL register (See
Section 7.2.9).
Revision: 2.50
October 2011
PHY Pins — Intel® 82580EB/82580DB GbE Controller
Table 2-9.
LED Output Pins (Continued)
Reserved
Symbol
LED1_0
Ball #
D1
Type
Out
Name and Function
Port 1 LED0. Programmable LED which indicates
by default Link up.
Note:
LED1_1
D2
Out
Port 1 LED1. Programmable LED which indicates
by default activity (when packets are transmitted
or received that match MAC filtering).
Note:
LED1_2
D3
Out
F4
Out
E1
Out
Pin is active low by default, can be
programmed via EEPROM (See
Section 6.2.20) or LEDCTL register (See
Section 7.2.9).
Port 1 LED3. Programmable LED which indicates
by default a 1000Mbps Link.
Note:
LED2_0*
Pin is active low by default, can be
programmed via EEPROM (See
Section 6.2.18) or LEDCTL register (See
Section 7.2.9).
Port 1 LED2. Programmable LED which indicates
by default a 100Mbps Link.
Note:
LED1_3
Pin is active low by default, can be
programmed via EEPROM (See
Section 6.2.20) or LEDCTL register (See
Section 7.2.9).
Pin is active low by default, can be
programmed via EEPROM (See
Section 6.2.18) or LEDCTL register (See
Section 7.2.9).
Port 2 LED0. Programmable LED which indicates
by default Link up.
Note:
Pin is active low by default, can be
programmed via EEPROM (See
Section 6.2.20) or LEDCTL register (See
Section 7.2.9).
* This port can be left unconnected in the dual
port 82580DB.
LED2_1*
E2
Out
Port 2 LED1. Programmable LED which indicates
by default activity (when packets are transmitted
or received that match MAC filtering).
Note:
Pin is active low by default, can be
programmed via EEPROM (See
Section 6.2.18) or LEDCTL register (See
Section 7.2.9).
* This port can be left unconnected in the dual
port 82580DB.
LED2_2*
E3
Out
Port 2 LED2. Programmable LED which indicates
by default a 100Mbps Link.
Note:
Pin is active low by default, can be
programmed via EEPROM (See
Section 6.2.20) or LEDCTL register (See
Section 7.2.9).
* This port can be left unconnected in the dual
port 82580DB.
LED2_3*
G2
Out
Port 2 LED3. Programmable LED which indicates
by default a 1000Mbps Link.
Note:
Pin is active low by default, can be
programmed via EEPROM (See
Section 6.2.18) or LEDCTL register (See
Section 7.2.9).
* This port can be left unconnected in the dual
port 82580DB.
Revision: 2.50
October 2011
Intel® 82580EB/82580DB Gigabit Ethernet Controller
Datasheet
45
Intel® 82580EB/82580DB GbE Controller — PHY Pins
Table 2-9.
Reserved
LED Output Pins (Continued)
Symbol
LED3_0*
Ball #
F1
Type
Out
Name and Function
Port 3 LED0. Programmable LED which indicates
by default Link up.
Note:
Pin is active low by default, can be
programmed via EEPROM (See
Section 6.2.20) or LEDCTL register (See
Section 7.2.9).
* This port can be left unconnected in the dual
port 82580DB.
LED3_1*
F2
Out
Port 3 LED1. Programmable LED which indicates
by default activity (when packets are transmitted
or received that match MAC filtering).
Note:
Pin is active low by default, can be
programmed via EEPROM (See
Section 6.2.18) or LEDCTL register (See
Section 7.2.9).
* This port can be left unconnected in the dual
port 82580DB.
LED3_2*
F3
Out
Port 3 LED2. Programmable LED which indicates
by default a 100Mbps Link.
Note:
Pin is active low by default, can be
programmed via EEPROM (See
Section 6.2.20) or LEDCTL register (See
Section 7.2.9).
* This port can be left unconnected in the dual
port 82580DB.
LED3_3*
G1
Out
Port 3 LED3. Programmable LED which indicates
by default a 1000Mbps Link.
Note:
Pin is active low by default, can be
programmed via EEPROM (See
Section 6.2.18) or LEDCTL register (See
Section 7.2.9).
* This port can be left unconnected in the dual
port 82580DB.
Intel® 82580EB/82580DB Gigabit Ethernet Controller
Datasheet
46
Revision: 2.50
October 2011
PHY Pins — Intel® 82580EB/82580DB GbE Controller
2.1.8.2
PHY Analog Pins
The AC specification for these pins is described in sections Section 10.6.4.
Table 2-10.
Reserved
Revision: 2.50
October 2011
Analog Pins
Symbol
Ball #
MDI0_0_p
T3
MDI0_0_n
R3
MDI1_0_p
T6
MDI1_0_n
Type
A
Name and Function
Media Dependent Interface[0] for port 0, port 1, Port 2 and
port 3 accordingly:
•
1000BASE-T: In MDI configuration, MDI[0]+/corresponds to BI_DA+/- and in MDIX configuration
MDI[0]+/- corresponds to BI_DB+/-.
R6
•
100BASE-TX: In MDI configuration, MDI[0]+/- is used for
the transmit pair and in MDIX configuration MDI[0]+/- is
used for the receive pair.
MDI2_0_p*
T9
•
MDI2_0_n*
R9
10BASE-T: In MDI configuration, MDI[0]+/- is used for
the transmit pair and in MDIX configuration MDI[0]+/- is
used for the receive pair.
MDI3_0_p*
T12
MDI3_0_n*
R12
MDI0_1_p
P4
MDI0_1_n
P5
MDI1_1_p
P6
MDI1_1_n
* This port can be left unconnected in the dual port 82580DB.
A
Media Dependent Interface[1] for port 0, port 1, port 2 and
port 3 accordingly:
•
1000BASE-T: In MDI configuration, MDI[1]+/corresponds to BI_DB+/- and in MDIX configuration
MDI[1]+/- corresponds to BI_DA+/-.
P7
•
100BASE-TX: In MDI configuration, MDI[1]+/- is used for
the receive pair and in MDIX configuration MDI[1]+/- is
used for the transmit pair.
MDI2_1_p*
T10
•
MDI2_1_n*
R10
10BASE-T: In MDI configuration, MDI[1]+/- is used for
the receive pair and in MDIX configuration MDI[1]+/- is
used for the transmit pair.
MDI3_1_p*
T13
MDI3_1_n*
R13
MDI0_2_p
T4
MDI0_2_n
R4
MDI1_2_p
T7
MDI1_2_n
R7
MDI2_2_p*
T11
MDI2_2_n*
R11
MDI3_2_p*
T14
MDI3_2_n*
R14
* This port can be left unconnected in the dual port 82580DB.
A
Media Dependent Interface[2] for port 0, port 1 port 2 and
port 3:
•
1000BASE-T: In MDI configuration, MDI[2]+/corresponds to BI_DC+/- and in MDIX configuration
MDI[2]+/- corresponds to BI_DD+/-.
•
100BASE-TX: Unused.
•
10BASE-T: Unused.
* This port can be left unconnected in the dual port 82580DB.
Intel® 82580EB/82580DB Gigabit Ethernet Controller
Datasheet
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Intel® 82580EB/82580DB GbE Controller — Testability Pins
Table 2-10.
Analog Pins (Continued)
Reserved
Symbol
Ball #
MDI0_3_p
T5
MDI0_3_n
R5
MDI1_3_p
T8
MDI1_3_n
R8
MDI2_3_p*
P9
MDI2_3_n*
P10
MDI3_3_p*
P12
MDI3_3_n*
P13
GE_REXT3K
T2
Type
A
Name and Function
Media Dependent Interface[3] for port 0, port 1, port 2 and
port 3:
•
1000BASE-T: In MDI configuration, MDI[3]+/corresponds to BI_DD+/- and in MDIX configuration
MDI[3]+/- corresponds to BI_DC+/-.
•
100BASE-TX: Unused.
•
10BASE-T: Unused.
*This port can be left unconnected in the dual port 82580DB.
B
PHY Bias
Connect 3.01K 1% resistor between this pin and ground.
RSVD_TX_TCLK
R1
Out
Transmit 125 MHz clock for IEEE testing. Shared for the 4
ports.
RSVD_ATST_P
R2
A-out
Analog differential test pins. Shared for the 4 ports.
RSVD_ATST_N
T1
Not connected in normal operation
2.1.9
Testability Pins
Table 2-11.
Testability Pins
Reserved
Symbol
Not connected in normal operation.
Ball #
Type
Name and Function
RSVD_TE_VSS
C12
In
Enables test mode. When high test pins are multiplexed on
functional signals.
RSVD_TP_5
C13
T/S
RSVD_TP_6
D12
RSVD_TP_7
G14
RSVD_TP_8
G15
JTCK
F13
In
JTAG Clock Input
JTDI
E12
In
JTAG TDI Input
JTDO
D13
T/S, O/D
JTAG TDO Output
JTMS
G13
In
JTAG TMS Input
RSRVD_JRST_3P3
E13
In
JTAG Reset Input
AUX_PWR
D15
T/S
Auxiliary Power Available:
In functional mode, must be connected to ground.
Test pins for production testing. In functional mode should not
be connected.
This pin is a strapping option pin, latched at the rising edge of
PE_RST# or In-Band PCIe Reset. This pin has an internal weak
pull-up resistor. In case this pin is driven high during init time
it indicates that Auxiliary Power is available and the device
should support D3COLD power state if enabled to do so. This
pin is also used for testing and scan.
Intel® 82580EB/82580DB Gigabit Ethernet Controller
Datasheet
48
Revision: 2.50
October 2011
Testability Pins — Intel® 82580EB/82580DB GbE Controller
Table 2-11.
Reserved
Testability Pins (Continued)
Symbol
Ball #
Type
Name and Function
LAN0_DIS_N
F14
T/S
This pin is a strapping option pin, latched at the rising edge of
PE_RST# or In-Band PCIe Reset. This pin has an internal weak
pull-up resistor. In case this pin is not connected or driven
high during init time, LAN 0 is enabled. In case this pin is
driven low during init time, LAN 0 function is disabled. This pin
is also used for testing and scan.
LAN1_DIS_N
E14
T/S
This pin is a strapping option pin, latched at the rising edge of
PE_RST# or In-Band PCIe Reset. This pin has an internal weak
pull-up resistor. In case this pin is not connected or driven
high during init time, LAN 1 is enabled. In case this pin is
driven low during init time, LAN 1 function is disabled. This pin
is also used for testing and scan.
LAN2_DIS_N *
D14
T/S
This pin is a strapping option pin, latched at the rising edge of
PE_RST# or In-Band PCIe Reset. This pin has an internal weak
pull-up resistor. In case this pin is not connected or driven
high during init time, LAN 2 is enabled. In case this pin is
driven low during init time, LAN 2 function is disabled. This pin
is also used for testing and scan.
LAN3_DIS_N*
C14
T/S
* Ignored during INIT when using the dual port 82580DB.
This pin is a strapping option pin, latched at the rising edge of
PE_RST# or In-Band PCIe Reset. This pin has an internal weak
pull-up resistor. In case this pin is not connected or driven
high during init time, LAN 3 is enabled. In case this pin is
driven low during init time, LAN 3 function is disabled. This pin
is also used for testing and scan.
* Ignored during INIT when using the dual port 82580DB.
Revision: 2.50
October 2011
Intel® 82580EB/82580DB Gigabit Ethernet Controller
Datasheet
49
Intel® 82580EB/82580DB GbE Controller — Power Supply and Ground Pins
2.1.10
Power Supply and Ground Pins
Table 2-12.
Power Supply Pins
Reserved
Symbol
VCC3P3
Ball #
2.2
Name and Function
3.3V
3.3V Periphery power
supply
VCC3P3
F5, H5
3.3V
3.3V Periphery power
supply
VCC3P3
F12, H12, K12, L12
3.3V
3.3V Periphery power
supply
VCC1P0
E6,G6, H6, J6,E11, G11, H11, J11, K11, M11,
N12
1.0V
1.0V digital power supply
VCC1P0
K6
1.0V
1.0V digital power supply
VCC1P0_APE
D6, D8, D9, D11
1.0V
1.0V PCIe Analog Power
Supply
VCC1P0_ASE
L13, K14, L14
1.0V
1.0V SerDes Analog power
supply
VCC1P0_AGE
L7, L8, L9, L10
1.0V
1.0V PHY analog power
supply
VCC3P3_A
M6, M7, M8, M9, M10, P8, P11
3.3V
3.3V PHY analog power
supply
VCC3P3_AGE
L5
3.3V
3.3V PHY analog power
supply
VCC1P8_PE_1
C7
1.8V
PCIe VCO Analog power
supply connected to 1.8V.
1.8V
VCC1P8_PE_2
C10
PCIe VCO Analog power
supply connected to 1.8V.
Signal
VSS
Type
K5
Pin
A4, A7, A10, A13, B4, B7, B10, B13, D7, D10, E7, E8, E9, E10, F6, F7, F8, F9, F10, F11, G5, G7, G8, G9, G10,
G12, H7, H8, H9, H10, J5, J7, J8, J9, J10, J12, K7, K8, K9, K10, L6, L11, M5, M12, N5, N6, N7, N8, N9, N10,
N11, P3
Pullups/Pulldowns
The table below lists internal & external pull-up resistors and their functionality in different device
states. Each internal PUP has a nominal value of 100K, ranging from 50K to 150K.
The device states are defined as follows:
• Power-up = while 3.3V is stable, yet 1.0V isn’t
• Active = normal mode (not power up or disable)
• Disable = device disable (a.k.a. dynamic IDDQ – see See Section 4.5 )
Intel® 82580EB/82580DB Gigabit Ethernet Controller
Datasheet
50
Revision: 2.50
October 2011
Pullups/Pulldowns — Intel® 82580EB/82580DB GbE Controller
Table 2-13.
Pull-Up Resistors
Power up5
Signal Name
PUP
Disable6
Active
Comments
PUP
Comments
PUP
External
Comments
LAN_PWR_GOOD
N
N
Must be connected N
PE_WAKE_N
N
N
N
Y
PU
PE_RST_N
N
N
N
N
FLSH_SI
Y
N
Y
N
FLSH_SO
Y
Y
Y
N
FLSH_SCK
Y
N
Y
N
FLSH_CE_N
Y
N
Y
N
EE_DI
Y
N
Y
N
EE_DO
Y
Y
Y
N
EE_SK
Y
N
Y
N
EE_CS_N
Y
N
Y
N
SMBD
N
N
N
Y
SMBCLK
N
N
N
Y
SMBALRT_N
N
N
N
Y
NCSI_CLK_IN
N
N
N
NCSI_CLK_OUT
N
N
N
HiZ
PD (Note 1)
If active,
stable output
N
NCSI_CRS_DV
N
HiZ
N
N
Y (Note 1)
NCSI_RXD[1:0]
N
HiZ
N
N
Y (Note 2)
NCSI_TX_EN
N
HiZ
N
N
PD (Note 1)
NCSI_TXD[1:0]
N
HiZ
N
N
PU (Note 1)
SDP0[3:0]
Y
Y
Until EEPROM
done
N
May keep state
by EEPROM
control
N
SDP1[3:0]
Y
Y
Until EEPROM
done
N
May keep state
by EEPROM
control
N
SDP2[3:0]
Y
Y
Until EEPROM
done
N
May keep state
by EEPROM
control
N
SDP3[3:0]
Y
Y
Until EEPROM
done
N
May keep state
by EEPROM
control
N
DEV_OFF_N
Y
N
N
Must be
connected on
board
MAIN_PWR_OK
Y
Y
N
Must be
connected on
board
SRDS_0_SIG_DET
Y
N
N
Must be
connected
externally
SRDS_1_SIG_DET
Y
N
N
Must be
connected
externally
SRDS_2_SIG_DET
Y
N
N
Must be
connected
externally
Revision: 2.50
October 2011
Intel® 82580EB/82580DB Gigabit Ethernet Controller
Datasheet
51
Intel® 82580EB/82580DB GbE Controller — Pullups/Pulldowns
Table 2-13.
Pull-Up Resistors (Continued)
Power up5
Signal Name
PUP
Disable6
Active
Comments
PUP
SRDS_3_SIG_DET
Y
N
SFP0_I2C_CLK
Y
Y
SFP0_I2C_DATA
Y
SFP1_I2C_CLK
Comments
PUP
External
Comments
N
Must be
connected
externally
Until EEPROM
done or if I2C
disable set in
EEPROM
N
Y if I2C
Y
Until EEPROM
done or if I2C
disable set in
EEPROM
N
Y
Y
Y
Until EEPROM
done or if I2C
disable set in
EEPROM
N
Y if I2C
SFP1_I2C_DATA
Y
Y
Until EEPROM
done or if I2C
disable set in
EEPROM
N
Y
SFP2_I2C_CLK
Y
Y
Until EEPROM
done or if I2C
disable set in
EEPROM
N
Y if I2C
SFP2_I2C_DATA
Y
Y
Until EEPROM
done or if I2C
disable set in
EEPROM
N
Y
SFP3_I2C_CLK
Y
Y
Until EEPROM
done or if I2C
disable set in
EEPROM
N
Y if I2C
SFP3_I2C_DATA
Y
Y
Until EEPROM
done or if I2C
disable set in
EEPROM
N
Y
LED0_0
Y
N
N
HiZ
LED0_1
Y
N
N
HiZ
LED0_2
Y
N
N
HiZ
LED0_3
Y
N
N
HiZ
LED1_0
Y
N
N
HiZ
LED1_1
Y
N
N
HiZ
LED1_2
Y
N
N
HiZ
LED1_3
Y
N
N
HiZ
LED2_0
Y
N
N
HiZ
LED2_1
Y
N
N
HiZ
LED2_2
Y
N
N
HiZ
LED2_3
Y
N
N
HiZ
LED3_0
Y
N
N
HiZ
LED3_1
Y
N
N
HiZ
LED3_2
Y
N
N
HiZ
LED3_3
Y
N
N
HiZ
RSVD_TE_VSS
N
N
N
Intel® 82580EB/82580DB Gigabit Ethernet Controller
Datasheet
52
Connect to
ground
Revision: 2.50
October 2011
Strapping — Intel® 82580EB/82580DB GbE Controller
Table 2-13.
Pull-Up Resistors (Continued)
Power up5
Signal Name
PUP
RSVD_TP_8:5
Comments
Y
Disable6
Active
PUP
Comments
Y When
input
JTCK
N
N
JTDI
N
N
JTDO
N
N
JTMS
N
N
RSRVD_JRST_3P3
N
N
AUX_PWR
Y
LAN0_DIS_N
PUP
External
Comments
Y
N
PU in Test mode
Y- Connect PD
N
Y
N
Y
PU in Test mode
N
Y
PU in Test mode
N
Y- Connect PU
N
N
PU or PD (note
3)
Y
Y when
input
Y
PU or PD (note
4)
LAN1_DIS_N
Y
Y when
input
Y
PU or PD (note
4)
LAN2_DIS_N
Y
Y when
input
Y
PU or PD (note
4)
LAN3_DIS_N
Y
Y when
input
Y
PU or PD (note
4)
Notes:
1.
Should be pulled down if NC-SI interface is disabled.
2.
Only if NC-SI is unused or set to multi drop configuration.
3.
If Aux power is connected, should be pulled up, else should be pulled down.
4.
If the specific function is disabled, should be pulled down, else should be pulled up.
5.
Power up - LAN_PWR_GOOD = 0
6.
See Section 5.2.6 for description of Disable state.
2.3
Strapping
The following signals are used for static configuration. Unless otherwise stated, strapping options are
latched on the rising edge of LAN_PWR_GOOD, at power up, at in-band PCI Express reset and at
PE_RST_N assertion. At other times, they revert to their standard usage.
Table 2-14.
Strapping Options
Purpose
Pin
LAN0 Disable
LAN0_DIS_N
LAN1 Disable
LAN1_DIS_N
Polarity
0b – LAN0 is disabled
Pull-up / Pull-down
Internal pull-up
1b – LAN0 is enabled
0b – LAN1 is disabled
Internal pull-up
1b – LAN1 is enabled
LAN2 Disable
LAN2_DIS_N
LAN3 Disable
LAN3_DIS_N
0b – LAN2 is disabled
Internal pull-up
1b – LAN2 is enabled
0b – LAN3 is disabled
Internal pull-up
1b – LAN3 is enabled
AUX_PWR
AUX_PWR
0b – AUX power is not available
None
1b – AUX power is available
Revision: 2.50
October 2011
Intel® 82580EB/82580DB Gigabit Ethernet Controller
Datasheet
53
Intel® 82580EB/82580DB GbE Controller — Interface Diagram
2.4
Interface Diagram
Figure 2-1.
82580EB/DB Interface Diagram
Intel® 82580EB/82580DB Gigabit Ethernet Controller
Datasheet
54
Revision: 2.50
October 2011
Pin List (Alphabetical) — Intel® 82580EB/82580DB GbE Controller
2.5
Pin List (Alphabetical)
Table 2-15 lists the pins and signals in ball alphabetical order.
Note:
Unused pins can be left unconnected, except for the manageability pins of the SMBus and
NC-SI Bus. These pins must be pulled-up. Reference the 82580EB/DB Design Checklist for
details.
Table 2-15.
Pin List in Alphabetical Order
* NOTE: This port can be left unconnected in the dual port 82580DB.
Signal
Ball
Signal
Ball
Signal
PE_TRIM2
PE_TRIM1
Ball
A1
TSENSZ
C5
VSS
E9
A2
PE_TXVTERM1
C6
VSS
E10
PER_3_p
A3
VCC1P8_PE_1
C7
VCC1P0
E11
VSS
A4
PE_TXVTERM2
C8
JTDI
E12
PET_3_p
A5
PE_TXVTERM3
C9
RSVD_JRST_3P3
E13
PET_2_p
A6
VCC1P8_PE_2
C10
LAN1_DIS_N
E14
VSS
A7
PE_TXVTERM4
C11
EE_DI
E15
PER_2_p
A8
RSVD_TE_VSS
C12
EE_SK
E16
F1
PER_1_p
A9
RSVD_TP_5
C13
LED3_0*
VSS
A10
LAN3_DIS_N*
C14
LED3_1*
F2
PET_1_p
A11
FLSH_SO
C15
LED3_2*
F3
PET_0_p
A12
FLSH_CE_N
C16
LED1_3*
F4
VSS
A13
LED1_0
D1
VCC3P3
F5
PER_0_p
A14
LED1_1
D2
VSS
F6
PE_CLK_n
A15
LED1_2
D3
VSS
F7
PE_CLK_p
A16
LAN_PWR_GOOD
D4
VSS
F8
PE_RST_N
B1
TSENSP
D5
VSS
F9
MAIN_PWR_OK
B2
VCC1P0_APE
D6
VSS
F10
PER_3_n
B3
VSS
D7
VSS
F11
VSS
B4
VCC1P0_APE
D8
VCC3P3
F12
PET_3_n
B5
VCC1P0_APE
D9
JTCK
F13
PET_2_n
B6
VSS
D10
LAN0_DIS_N
F14
VSS
B7
VCC1P0_APE
D11
EE_DO
F15
PER_2_n
B8
RSVD_TP_6
D12
EE_CS_N
F16
G1
PER_1_n
B9
JTDO
D13
LED3_3
VSS
B10
LAN2_DIS_N*
D14
LED2_3
G2
PET_1_n
B11
AUX_PWR
D15
SMBD
G3
PET_0_n
B12
PE_WAKE_N
D16
SMBALRT_N
G4
VSS
B13
LED2_0*
E1
VSS
G5
PER_0_n
B14
LED2_1*
E2
VCC1P0
G6
FLSH_SI
B15
LED2_2*
E3
VSS
G7
FLSH_SCK
B16
LED0_3*
E4
VSS
G8
LED0_0
C1
SMBCLK
E5
VSS
G9
LED0_1
C2
VCC1P0
E6
VSS
G10
Revision: 2.50
October 2011
Intel® 82580EB/82580DB Gigabit Ethernet Controller
Datasheet
55
Intel® 82580EB/82580DB GbE Controller — Pin List (Alphabetical)
Table 2-15.
Pin List in Alphabetical Order
* NOTE: This port can be left unconnected in the dual port 82580DB.
Signal
Ball
Signal
Ball
Signal
Ball
LED0_2
C3
VSS
E7
VCC1P0
G11
DEVICE_OFF_N
C4
VSS
E8
VSS
G12
JTMS
G13
VCC1P0
K6
SER1_n
M15
RSVD_TP_7
G14
VSS
K7
SER1_p
M16
RSVD_TP_8
G15
VSS
K8
SDP3_0
N1
SFP3_I2C_DATA
G16
VSS
K9
SDP3_1
N2
NCSI_CLK_IN
H1
VSS
K10
SDP3_2
N3
NCSI_CLK_OUT
H2
VCC1P0
K11
SDP3_3
N4
NCSI_CRS_DV
H3
VCC3P3
K12
VSS
N5
NCSI_RXD_0
H4
SE_RSET
K13
VSS
N6
VCC3P3
H5
VCC1P0_ASE
K14
VSS
N7
VCC1P0
H6
SER2_n*
K15
VSS
N8
VSS
H7
SER2_p*
K16
VSS
N9
VSS
H8
SDP1_0
L1
VSS
N10
VSS
H9
SDP1_1
L2
VSS
N11
VSS
H10
SDP1_2
L3
VCC1P0
N12
VCC1P0
H11
SDP1_3
L4
SRDS_0_SIG_DET
N13
VCC3P3
H12
VCC3P3_AGE
L5
SFP1_I2C_DATA
N14
SFP2_I2C_DATA*
H13
VSS
L6
SET1_n
N15
SFP3_I2C_CLK*
H14
VCC1P0_AGE
L7
SET1_p
N16
SER3_n*
H15
VCC1P0_AGE
L8
XTAL_CLK_I
P1
P2
SER3_p*
H16
VCC1P0_AGE
L9
XTAL_CLK_O
NCSI_RXD_1
J1
VCC1P0_AGE
L10
VSS
P3
NCSI_TX_EN
J2
VSS
L11
MDI0_1_p
P4
NCSI_TXD_0
J3
VCC3P3
L12
MDI0_1_n
P5
NCSI_TXD_1
J4
VCC1P0_ASE
L13
MDI1_1_p
P6
VSS
J5
VCC1P0_ASE
L14
MDI1_1_n
P7
VCC1P0
J6
SET2_n*
L15
VCC3P3_A
P8
VSS
J7
SET2_p*
L16
MDI2_3_p*
P9
VSS
J8
SDP2_0
M1
MDI2_3_n*
P10
VSS
J9
SDP2_1
M2
VCC3P3_A
P11
VSS
J10
SDP2_2
M3
MDI3_3_p*
P12
VCC1P0
J11
SDP2_3
M4
MDI3_3_n*
P13
VSS
J12
VSS
M5
SRDS_1_SIG_DET
P14
SFP0_I2C_DATA
J13
VCC3P3_A
M6
SER0_n
P15
SFP2_I2C_CLK
J14
VCC3P3_A
M7
SER0_p
P16
SET3_n*
J15
VCC3P3_A
M8
RSVD_TX_TCLK
R1
SET3_p*
J16
VCC3P3_A
M9
RSVD_ATST_P
R2
SDP0_0
K1
VCC3P3_A
M10
MDI0_0_n
R3
SDP0_1
K2
VCC1P0
M11
MDI0_2_n
R4
SDP0_2
K3
VSS
M12
MDI0_3_n
R5
Intel® 82580EB/82580DB Gigabit Ethernet Controller
Datasheet
56
Revision: 2.50
October 2011
Ball-Out — Intel® 82580EB/82580DB GbE Controller
Table 2-15.
Pin List in Alphabetical Order
* NOTE: This port can be left unconnected in the dual port 82580DB.
Signal
Ball
Signal
Ball
Signal
Ball
SDP0_3
K4
SFP0_I2C_CLK
M13
MDI1_0_n
R6
VCC3P3
K5
SFP1_I2C_CLK
M14
MDI1_2_n
R7
MDI1_3_n
R8
RSVD_ATST_N
T1
MDI2_1_p*
T10
MDI2_0_n*
R9
GE_REXT3K
T2
MDI2_2_p*
T11
MDI2_1_n*
R10
MDI0_0_p
T3
MDI3_0_p*
T12
MDI2_2_n*
R11
MDI0_2_p
T4
MDI3_1_p*
T13
MDI3_0_n*
R12
MDI0_3_p
T5
MDI3_2_p*
T14
MDI3_1_n*
R13
MDI1_0_p
T6
SRDS_2_SIG_DET*
T15
SRDS_3_SIG_DET*
T16
MDI3_2_n*
R14
MDI1_2_p
T7
SET0_n
R15
MDI1_3_p
T8
SET0_p
R16
MDI2_0_p*
T9
2.6
Ball-Out
Figure 2-2 depicts a top view ball map of the 82580EB/DB, in a 17x17 PBGA package. See
Section 10.7.4 for locating A1 corner ball on package.
Note:
Revision: 2.50
October 2011
Unused pins can be left unconnected, except for the manageability pins of the SMBus and
NC-SI Bus. These pins must be pulled-up. Reference the 82580EB/DB Design Checklist for
details.
Intel® 82580EB/82580DB Gigabit Ethernet Controller
Datasheet
57
Intel® 82580EB/82580DB GbE Controller — Ball-Out
Figure 2-2.
Ball-out
§§
Intel® 82580EB/82580DB Gigabit Ethernet Controller
Datasheet
58
Revision: 2.50
October 2011
Interconnects — Intel® 82580EB/82580DB GbE Controller
3.0
Interconnects
3.1
PCIe
3.1.1
PCIe Overview
PCIe is a third generation I/O architecture that enables cost competitive next generation I/O solutions
providing industry leading price/performance and features. It is an industry-driven specification.
PCIe defines a basic set of requirements that encases the majority of the targeted application classes.
Higher-end applications' requirements, such as enterprise class servers and high-end communication
platforms, are encased by a set of advanced extensions that compliment the baseline requirements.
To guarantee headroom for future applications of PCIe, a software-managed mechanism for introducing
new, enhanced, capabilities in the platform is provided. Figure 3-1 shows PCIe architecture.
Figure 3-1.
Revision: 2.50
October 2011
PCIe Stack Structure
Intel® 82580EB/82580DB Gigabit Ethernet Controller
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PCIe's physical layer consists of a differential transmit pair and a differential receive pair. Full-duplex
data on these two point-to-point connections is self-clocked such that no dedicated clock signals are
required. The bandwidth of this interface increases linearly with frequency.
The packet is the fundamental unit of information exchange and the protocol includes a message space
to replace the various side-band signals found on many buses today. This movement of hard-wired
signals from the physical layer to messages within the transaction layer enables easy and linear
physical layer width expansion for increased bandwidth.
The common base protocol uses split transactions and several mechanisms are included to eliminate
wait states and to optimize the reordering of transactions to further improve system performance.
3.1.1.1
Architecture, Transaction and Link Layer Properties
• Split transaction, packet-based protocol
• Common flat address space for load/store access (such as PCI addressing model)
— Memory address space of 32-bits to allow compact packet header (must be used to access
addresses below 4 GB)
— Memory address space of 64-bit using extended packet header
• Transaction layer mechanisms:
— PCI-X style relaxed ordering
— Optimizations for no-snoop transactions
• Credit-based flow control
• Packet sizes/formats:
— Maximum upstream (write) payload size of 512 Bytes
— Maximum downstream (read) payload size of 2 KBytes
• Reset/initialization:
— Frequency/width/profile negotiation performed by hardware
• Data integrity support
— Using CRC-32 for transaction layer packets
• Link layer retry for recovery following error detection
— Using CRC-16 for link layer messages
• No retry following error detection
— 8b/10b encoding with running disparity
• Software configuration mechanism:
— Uses PCI configuration and bus enumeration model
— PCIe-specific configuration registers mapped via PCI extended capability mechanism
• Baseline messaging:
— In-band messaging of formerly side-band legacy signals (such as interrupts, etc.)
— System-level power management supported via messages
• Power management:
— Full support for PCI-PM
— Wake capability from D3cold state
— Compliant with ACPI, PCI-PM software model
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— Active state power management
• Support for PCIe rev 2.0
— Support for completion time out
— Support for additional registers in the PCIe capability structure.
3.1.1.2
Physical Interface Properties
• Point to point interconnect
— Full-duplex; no arbitration
• Signaling technology:
— Low Voltage Differential (LVD)
— Embedded clock signaling using 8b/10b encoding scheme
• Serial frequency of operation: 5 Gbps (Gen2) or 2.5Gbps (Gen1).
• Interface width of x4, x2, or x1.
• DFT and DFM support for high volume manufacturing
3.1.1.3
Advanced Extensions
PCIe defines a set of optional features to enhance platform capabilities for specific usage modes. The
82580EB/DB supports the following optional features:
• Extended error reporting - messaging support to communicate multiple types/severity of errors.
• Device serial number.
• Completion timeout control.
• TLP Processing Hints (TPH) - provides hints on a per transaction basis to facilitate optimized
processing of transactions that target Memory Space.
• Latency Tolerance Reporting (LTR) - messaging support to communicate service latency
requirements for Memory Reads and Writes to the Root Complex.
3.1.2
3.1.2.1
Functionality - General
Native/Legacy
All the 82580EB/DB PCI functions are native PCIe functions.
3.1.2.2
Locked Transactions
The 82580EB/DB does not support locked requests as target or master.
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3.1.3
3.1.3.1
Host Interface
Tag IDs
PCIe device numbers identify logical devices within the physical device (the 82580EB/DB is a physical
device). The 82580EB/DB implements a single logical device with up to four separate PCI functions:
LAN 0, LAN 1, LAN2 and LAN3. The device number is captured from each type 0 configuration write
transaction.
Each of the PCIe functions interfaces with the PCIe unit through one or more clients. A client ID
identifies the client and is included in the Tag field of the PCIe packet header. Completions always carry
the tag value included in the request to enable routing of the completion to the appropriate client.
Tag IDs are allocated differently for read and write. Messages are sent with a tag of 0x0.
3.1.3.1.1
TAG ID Allocation for Read Transactions
Table 3-1 lists the Tag ID allocation for read accesses. The tag ID is interpreted by hardware in order to
forward the read data to the required device.
Table 3-1.
IDs in Read Transactions
Tag ID
Description
0x0
Data request 0
0x1
Data request 1
0x2
Data request 2
0x3
Data request 3
0x4
Data request 4
0x5
Data request 5
0x6
Data request 6
0x7
Data request 7
0x8
Data request 8
0x9
Data request 9
0xA
Data request 10
0xB
Data request 11
0xC
Data request 12
0xD
Data request 13
0xE
Data request 14
0xF
Data request 15
0x10
Data request 16
0x11
Data request 17
0x12
Data request 18
0x13
Data request 19
0x14
Data request 20
0x15
Data request 21
0x16
Data request 22
0x17
Data request 23
0x18
Descriptor Tx 0
0x19
Descriptor Tx 1
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Table 3-1.
IDs in Read Transactions
0x1A
Descriptor Tx 2
0x1B
Descriptor Tx 3
0x1C
Descriptor Rx 0
0x1D
Descriptor Rx 1
0x1E
Descriptor Rx 2
0x1F
Descriptor Rx 3
3.1.3.1.2
TAG ID Allocation for Write Transactions
Request tag allocation depends on these system parameters:
• DCA supported/not supported in the system (DCA_CTRL.DCA_DIS - see Section 7.13.4 for details)
• TPH enabled in the system.
• DCA enabled/disabled for each type of traffic (TXCTL.TX Descriptor DCA EN, RXCTL.RX Descriptor
DCA EN, RXCTL.RX Header DCA EN, RXCTL.Rx Payload DCA EN).
• TPH enabled or disabled for the specific type of traffic carried by the TLP (TXCTL.TX Descriptor TPH
EN, RXCTL.RX Descriptor TPH EN, RXCTL.RX Header TPH EN, RXCTL.Rx Payload TPH EN).
• System type: Legacy DCA vs. DCA 1.0 (DCA_CTRL.DCA_MODE - see Section 7.13.4 for details).
• CPU ID (RXCTL.CPUID or TXCTL.CPUID).
I/OAT 1I/OAT 2/3See the case studies below for information on different implementations.
3.1.3.1.2.1
Case 1 - DCA Disabled in the System:
Table 3-2 describes the write requests tags. Unlike read, the values are for debug only, allowing tracing
of requests through the system.
Table 3-2.
IDs in Write Transactions, DCA Disabled Mode
Tag ID
Description
0x0 - 0x1
Reserved
0x2
Tx descriptors write-back / Tx Head write-back
0x3
Reserved
0x4
Rx descriptors write-back
0x5
Reserved
0x6
Write data
0x7 - 0x1D
Reserved
0x1E
MSI and MSI-X
0x1F
Reserved
3.1.3.1.2.2
Case 2 - DCA Enabled in the System, but Disabled for the Request:
• Legacy DCA platforms - If DCA is disabled for the request, the tags allocation is identical to the case
where DCA is disabled in the system. See Table 3-2 above.
• DCA 1.0 platforms - All write requests have a tag value of 0x00.
Note:
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When in DCA 1.0 mode, messages and MSI/MSI-x write requests are sent with the no-hint
tag.
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3.1.3.1.2.3
Case 3 - DCA Enabled in the System, DCA Enabled for the Request:
• Legacy DCA Platforms: the request tag is constructed as follows:
— Bit[0] – DCA Enable
— Bits[3:1] - The CPU ID field taken from the CPUID[2:0] bits of the RXCTL or TXCTL registers
— Bits[7:4] - Reserved
• DCA 1.0 Platforms: the request tag (all 8 bits) is taken from the CPUID field of the RXCTL or TXCTL
registers
3.1.3.1.2.4
Case 4 - TPH Enabled in the System, TPH Enabled for the Request:
• The request tag (all 8 bits) is taken from the CPUID field of the adequate register or context as
described in Table 8-58.
3.1.3.2
Completion Timeout Mechanism
In any split transaction protocol, there is a risk associated with the failure of a requester to receive an
expected completion. To enable requesters to attempt recovery from this situation in a standard
manner, the completion timeout mechanism is defined.
The completion timeout mechanism is activated for each request that requires one or more completions
when the request is transmitted. The 82580EB/DB provides a programmable range for the completion
timeout, as well as the ability to disable the completion timeout altogether. The completion timeout is
programmed through an extension of the PCIe capability structure (See Section 9.5.6.12).
The 82580EB/DB’s reaction in case of a completion timeout is defined in Table 3-12.
The 82580EB/DB controls the following aspects of completion timeout:
• Disabling or enabling completion timeout.
• Disabling or enabling re-send of a request on completion timeout.
• A programmable range of re-sends on completion timeout, if re-send enabled.
• A programmable range of timeout values.
• Programming the behavior of completion timeout is summarized in Table 3-3. System Software
may configure completion timeout independently per each LAN function.
Table 3-3.
Completion Timeout Programming
Capability
Programming capability
Completion Timeout Enabling
Controlled through PCI Device Control 2 configuration register.
Resend Request Enable
Loaded from the EEPROM into the GCR register.
Number of re-sends on timeout
Controlled through GCR register.
Completion Timeout Period
Controlled through PCI Device Control 2 configuration register.
Completion Timeout Enable - Programmed through the PCI Device Control 2 configuration Register. The
default is: Completion Timeout Enabled.
Resend Request Enable - The Completion Timeout Resend EEPROM bit (loaded to the
Completion_Timeout_Resend bit in the PCIe Control register (GCR) enables resending the request
(applies only when completion timeout is enabled). The default is to resend a request that timed out.
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Number of re-sends on timeout - Programmed through the Number of resends field in the GCR register.
The default value of resends is 3.
3.1.3.2.1
Completion Timeout Period
Programmed through the PCI Device Control 2 configuration register (See Section 9.5.6.12). The
82580EB/DB supports all ranges defined by PCIe v2.0 (5Gbps and 2.5Gbps).
A memory read request for which there are multiple completions are considered completed only when
all completions have been received by the requester. If some, but not all, requested data is returned
before the completion timeout timer expires, the requestor is permitted to keep or to discard the data
that was returned prior to timer expiration.
Note:
The completion timeout value must be programmed correctly in PCIe configuration space
(in Device Control 2 Register); the value must be set above the expected maximum latency
for completions in the system in which the 82580EB/DB is installed. This will ensure that
the 82580EB/DB receives the completions for the requests it sends out, avoiding a
completion timeout scenario. It is expected that the system BIOS will set this value
appropriately for the system.
3.1.4
Transaction Layer
The upper layer of the PCIe architecture is the transaction Layer. The transaction layer connects to the
82580EB/DB core using an implementation specific protocol. Through this core-to-transaction-layer
protocol, the application-specific parts of the 82580EB/DB interact with the PCIe subsystem and
transmit and receive requests to or from the remote PCIe agent, respectively.
3.1.4.1
Table 3-4.
Transaction Types Accepted by the 82580EB/DB
Transaction Types Accepted by the Transaction Layer
Transaction Type
Tx Later
Reaction
FC Type
Hardware Should Keep Data
From Original Packet
For Client
Configuration Read
Request
NPH
CPLH + CPLD
Requester ID, TAG, Attribute
Configuration space
Configuration Write
Request
NPH + NPD
CPLH
Requester ID, TAG, Attribute
Configuration space
Memory Read Request
NPH
CPLH + CPLD
Requester ID, TAG, Attribute
CSR
Memory Write Request
PH +
-
-
CSR
CSR
PD
IO Read Request
NPH
CPLH + CPLD
Requester ID, TAG, Attribute
IO Write Request
NPH + NPD
CPLH
Requester ID, TAG, Attribute
CSR
Read completions
CPLH + CPLD
-
-
DMA
Message
PH
-
-
Message Unit / PM
Flow control types:
• PH - Posted request headers
• PD - Posted request data payload
• NPH - Non-posted request headers
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• NPD - Non-posted request data payload
• CPLH - Completion headers
• CPLD - Completion data payload
3.1.4.1.1
Configuration Request Retry Status
PCIe supports devices requiring a lengthy self-initialization sequence to complete before they are able
to service configuration requests. This is the case for the 82580EB/DB were initialization is long due to
the EEPROM read operation following reset.
If the read of the PCIe section in the EEPROM was not completed and the 82580EB/DB receives a
configuration request, the 82580EB/DB responds with a configuration request retry completion status
to terminate the request, and thus effectively stall the configuration request until the subsystem has
completed local initialization and is ready to communicate with the host.
3.1.4.1.2
Partial Memory Read and Write Requests
The 82580EB/DB has limited support of read and write requests when only part of the byte enable bits
are set as described later in this section.
Partial writes to the MSI-X table are supported. All other partial writes are ignored and silently dropped.
Zero-length writes have no internal impact (nothing written, no effect such as clear-by-write). The
transaction is treated as a successful operation (no error event).
Partial reads with at least one byte enabled are answered as a full read. Any side effect of the full read
(such as clear by read) is applicable to partial reads also.
Zero-length reads generate a completion, but the register is not accessed and undefined data is
returned.
3.1.4.2
Table 3-5.
Transaction Types Initiated by the 82580EB/DB
Transaction Types Initiated by the Transaction Layer
Transaction type
Payload Size
FC Type
From Client
Configuration Read Request Completion
Dword
CPLH + CPLD
Configuration space
Configuration Write Request Completion
-
CPLH
Configuration space
I/O Read Request Completion
Dword
CPLH + CPLD
CSR
I/O Write Request Completion
-
CPLH
CSR
Read Request Completion
Dword/Qword
CPLH + CPLD
CSR
Memory Read Request
-
NPH
DMA
Memory Write Request
<= MAX_PAYLOAD_SIZE
PH + PD
DMA
Message
-
PH
INT / PM / Error Unit / LTR
Note:
MAX_PAYLOAD_SIZE supported is loaded from EEPROM (128 bytes, 256 bytes or 512 bytes). Effective MAX_PAYLOAD_SIZE
is defined for each PCI function according to configuration space register of this function.
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3.1.4.2.1
Data Alignment
Requests must never specify an address/length combination that causes a memory space access to
cross a 4 KB boundary. The 82580EB/DB breaks requests into 4 KB-aligned requests (if needed). This
does not pose any requirement on software. However, if software allocates a buffer across a 4 KB
boundary, hardware issues multiple requests for the buffer. Software should consider limiting buffer
sizes and base addresses to comply with a 4 KB boundary in cases where it improves performance.
The general rules for packet alignment are as follows:
1. The length of a single request should not exceed the PCIe limit of MAX_PAYLOAD_SIZE for write
and MAX_READ_REQ for read.
2. The length of a single request does not exceed the 82580EB/DB’s internal limitation.
3. A single request should not span across different memory pages as noted by the 4 KB boundary
previously mentioned.
Note:
The rules apply to all the 82580EB/DB requests (read/write, snoop and no snoop).
If a request can be sent as a single PCIe packet and still meet rules 1-3, then it is not broken at a
cache-line boundary (as defined in the PCIe Cache line size configuration word), but rather, sent as a
single packet (motivation is that the chipset might break the request along cache-line boundaries, but
the 82580EB/DB should still benefit from better PCIe utilization). However, if rules 1-3 require that the
request is broken into two or more packets, then the request is broken at a cache-line boundary.
3.1.4.2.2
Multiple Tx Data Read Requests (MULR)
The 82580EB/DB supports 24 pipelined requests for transmit data on all ports. In general, the 24
requests might belong to the same packet or to consecutive packets to be transmitted on a single LAN
port or on multiple LAN ports. However, the following restriction applies:
• All requests for a packet are issued before a request is issued for a consecutive packet
Read requests can be issued from any of the supported queues, as long as the restriction is met.
Pipelined requests might belong to the same queue or to separate queues. However, as previously
noted, all requests for a certain packet are issued (from same queue) before a request is issued for a
different packet (potentially from a different queue or LAN port).
The PCIe specification does not ensure that completions for separate requests return in-order. Read
completions for concurrent requests are not required to return in the order issued. The 82580EB/DB
handles completions that arrive in any order. Once all completions arrive for a given request, the
82580EB/DB might issue the next pending read data request.
• The 82580EB/DB incorporates a re-order buffer to support re-ordering of completions for all
requests. Each request/completion can be up to 2 KBytes long. The maximum size of a read
request is defined as the minimum {2KB, Max_Read_Request_Size}.
In addition to the 24 pipeline requests for transmit data, the 82580EB/DB can issue up to 4 read
requests for all ports (either for a single port or for multiple LAN ports) to fetch transmit descriptors and
4 read requests for all ports (either for a single LAN port or for multiple LAN ports) to fetch receive
descriptors. The requests for transmit data, transmit descriptors, and receive descriptors are
independently issued. Each descriptor read request can fetch up to 16 descriptors for reception and 24
descriptors for transmission.
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3.1.4.3
Messages
3.1.4.3.1
Message Handling by the 82580EB/DB (as a Receiver)
Message packets are special packets that carry a message code.
The upstream device transmits special messages to the 82580EB/DB by using this mechanism.
The transaction layer decodes the message code and responds to the message accordingly.
Table 3-6.
Message
code [7:0]
Supported Messages in the 82580EB/DB (as a Receiver)
Routing r2r1r0
Message
Device later response
0x14
100
PM_Active_State_NAK
Internal signal set
0x19
011
PME_Turn_Off
Internal signal set
0x50
100
Slot power limit support (has one Dword data)
Silently drop
0x7E
010,011,100
Vendor_defined type 0 no data
Unsupported request -- NEC*
0x7E
010,011,100
Vendor_defined type 0 data
Unsupported request -- NEC*
0x7F
010,011,100
Vendor_defined type 1 no data
Silently drop
0x7F
010,011,100
Vendor_defined type 1 data
Silently drop
0x00
011
Unlock
Silently drop
3.1.4.3.2
Message Handling by the 82580EB/DB (as a Transmitter)
The transaction layer is also responsible for transmitting specific messages to report internal/external
events (such as interrupts and PMEs).
Table 3-7.
Message code
[7:0]
Supported Message in the 82580EB/DB (as a Transmitter)
Routing r2r1r0
Message
0x20
100
Assert INT A
0x21
100
Assert INT B
0x22
100
Assert INT C
0x23
100
Assert INT D
0x24
100
De-assert INT A
0x25
100
De-assert INT B
0x26
100
De-assert INT C
0x27
100
De-Assert INT D
0x30
000
ERR_COR
0x31
000
ERR_NONFATAL
0x33
000
ERR_FATAL
0x18
000
PM_PME
0x1B
101
PME_TO_ACK
0x10
100
Latency Tolerance Reporting (LTR)
3.1.4.4
Ordering Rules
The 82580EB/DB meets the PCIe ordering rules (PCI-X rules) by following the PCI simple device model:
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• Deadlock avoidance - Master and target accesses are independent - The response to a target
access does not depend on the status of a master request to the bus. If master requests are
blocked, such as due to no credits, target completions might still proceed (if credits are available).
• Descriptor/data ordering - The 82580EB/DB does not proceed with some internal actions until
respective data writes have ended on the PCIe link:
— The 82580EB/DB does not update an internal header pointer until the descriptors that the
header pointer relates to are written to the PCIe link.
— The 82580EB/DB does not issue a descriptor write until the data that the descriptor relates to is
written to the PCIe link.
The 82580EB/DB might issue the following master read request from each of the following clients:
• Rx Descriptor Read (up to 4 for all LAN ports)
• Tx Descriptor Read (up to 4 for all LAN ports)
• Tx Data Read (up to 24 for all LAN ports)
Completion of separate read requests are not guaranteed to return in order. Completions for a single
read request are guaranteed to return in address order.
3.1.4.4.1
Out of Order Completion Handling
In a split transaction protocol, when using multiple read requests in a multi processor environment,
there is a risk that completions arrive from the host memory out of order and interleaved. In this case,
the 82580EB/DB sorts the request completions and transfers them to the Ethernet in the correct order.
3.1.4.5
Transaction Definition and Attributes
3.1.4.5.1
Max Payload Size
The 82580EB/DB policy to determine Max Payload Size (MPS) is as follows:
• Master requests initiated by the 82580EB/DB (including completions) limits MPS to the value
defined for the function issuing the request.
• Target write accesses to the 82580EB/DB are accepted only with a size of one Dword or two
Dwords. Write accesses in the range of (three Dwords, MPS, etc.) are flagged as UR. Write accesses
above MPS are flagged as malformed.
See section 2.2.2 - TLPs with Data Payloads - Rules of the PCIe base specification.
3.1.4.5.2
Relaxed Ordering
The 82580EB/DB takes advantage of the relaxed ordering rules in PCIe. By setting the relaxed ordering
bit in the packet header, the 82580EB/DB enables the system to optimize performance in the following
cases:
• Relaxed ordering for descriptor and data reads: When the 82580EB/DB emits a read transaction, its
split completion has no ordering relationship with the writes from the CPUs (same direction). It
should be allowed to bypass the writes from the CPUs.
• Relaxed ordering for receiving data writes: When the 82580EB/DB issues receive DMA data writes,
it also enables them to bypass each other in the path to system memory because software does not
process this data until their associated descriptor writes complete.
• The 82580EB/DB cannot relax ordering for descriptor writes, MSI/MSI-X writes or PCIe messages.
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Relaxed ordering can be used in conjunction with the no-snoop attribute to enable the memory
controller to advance non-snoop writes ahead of earlier snooped writes.
Relaxed ordering is enabled in the 82580EB/DB by clearing the RO_DIS bit in the CTRL_EXT register.
Actual setting of relaxed ordering is done for LAN traffic by the host through the DCA registers.
3.1.4.5.3
Snoop Not Required
The 82580EB/DB sets the Snoop Not Required attribute bit for master data writes. System logic might
provide a separate path into system memory for non-coherent traffic. The non-coherent path to system
memory provides higher, more uniform, bandwidth for write requests.
Note:
The Snoop Not Required attribute does not alter transaction ordering. Therefore, to achieve
maximum benefit from Snoop Not Required transactions, it is advisable to set the relaxed
ordering attribute as well (assuming that system logic supports both attributes). In fact,
some chipsets require that relaxed ordering is set for no-snoop to take effect.
Global no-snoop support is enabled in the 82580EB/DB by clearing the NS_DIS bit in the CTRL_EXT
register. Actual setting of no snoop is done for LAN traffic by the host through the DCA registers.
3.1.4.5.4
No Snoop and Relaxed Ordering for LAN Traffic
Software might configure non-snoop and relax order attributes for each queue and each type of
transaction by setting the respective bits in the RXCTRL and TXCTRL registers.
Table 3-8 lists Software configuration for the No-Snoop and Relaxed Ordering bits for LAN traffic when
I/OAT 2 is enabled.
Table 3-8.
LAN Traffic Attributes
No-Snoop
Relaxed Ordering
Rx Descriptor Read
Transaction
N
Y
Rx Descriptor Write-Back
N
N
Relaxed ordering must never be used
for this traffic.
Rx Data Write
Y
Y
See the following note and
Section 3.1.4.5.4.1
Rx Replicated Header
N
Y
Tx Descriptor Read
N
Y
Tx Descriptor Write-Back
N
Y
Tx TSO Header Read
N
Y
Tx Data Read
N
Y
Note:
Comments
Rx payload no-snoop is also conditioned by the NSE bit in the receive descriptor. See
Section 3.1.4.5.4.1.
3.1.4.5.4.1
No-Snoop Option for Payload
Under certain conditions, which occur when I/OAT is enabled, software knows that it is safe to transfer
(DMA) a new packet into a certain buffer without snooping on the front-side bus. This scenario typically
occurs when software is posting a receive buffer to hardware that the CPU has not accessed since the
last time it was owned by hardware. This might happen if the data was transferred to an application
buffer by the I/OAT DMA engine.
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In this case, software should be able to set a bit in the receive descriptor indicating that the 82580EB/
DB should perform a no-snoop DMA transfer when it eventually writes a packet to this buffer.
When a non-snoop transaction is activated, the TLP header has a non-snoop attribute in the
Transaction Descriptor field.
This is triggered by the NSE bit in the receive descriptor. See Section 8.1.5.
3.1.4.5.5
TLP processing Hint (TPH)
The TPH bit can be set to provide information to the root complex about the cache in which the data
should be stored or from which the data should be read as described in Section 8.7.2.
TPH is enabled via the TPH Requester Enable field in the TPH control register of the configuration space
(Section 9.6.3.3). Setting of the TPH bit for different type of traffic is described in Table 8-58.
3.1.4.6
Flow Control
3.1.4.6.1
82580EB/DB Flow Control Rules
The 82580EB/DB implements only the default Virtual Channel (VC0). A single set of credits is
maintained for VC0.
Table 3-9.
Allocation of FC Credits
Credit Type
Posted Request Header (PH)
Operations
Number Of Credits
Target Write (one unit)
Sixteen credit units to support tail write at
wire speed.
Message (one unit)
Posted Request Data (PD)
Target Write (Length/16 bytes=1)
MAX_PAYLOAD_SIZE/16
Message (one unit)
Non-Posted Request Header (NPH)
Target Read (one unit)
Configuration Read (one unit)
Four units (to enable concurrent target
accesses to all LAN ports).
Configuration Write (one unit)
Non-Posted Request Data (NPD)
Configuration Write (one unit)
Four units.
Completion Header (CPLH)
Read Completion (N/A)
Infinite (accepted immediately).
Completion Data (CPLD)
Read Completion (N/A)
Infinite (accepted immediately).
Rules for FC updates:
• The 82580EB/DB maintains four credits for NPD at any given time. It increments the credit by one
after the credit is consumed and sends an UpdateFC packet as soon as possible. UpdateFC packets
are scheduled immediately after a resource is available.
• The 82580EB/DB provides four credits for PH (such as for four concurrent target writes) and four
credits for NPH (such as for four concurrent target reads). UpdateFC packets are scheduled
immediately after a resource becomes available.
• The 82580EB/DB follows the PCIe recommendations for frequency of UpdateFC FCPs.
3.1.4.6.2
Upstream Flow Control Tracking
The 82580EB/DB issues a master transaction only when the required FC credits are available. Credits
are tracked for posted, non-posted, and completions (the later to operate with a switch).
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3.1.4.6.3
Flow Control Update Frequency
In any case, UpdateFC packets are scheduled immediately after a resource becomes available.
When the link is in the L0 or L0s link state, Update FCPs for each enabled type of non-infinite FC credit
must be scheduled for transmission at least once every 30 μs (-0%/+50%), except when the Extended
Sync bit of the Control Link register is set, in which case the limit is 120 μs (-0%/+50%).
3.1.4.6.4
Flow Control Timeout Mechanism
The 82580EB/DB implements the optional FC update timeout mechanism.
The mechanism is activated when the Link is in L0 or L0s Link state. It uses a timer with a limit of
200μs (-0%/+50%), where the timer is reset by the receipt of any Init or Update FCP. Alternately, the
timer may be reset by the receipt of any DLLP.
After timer expiration, the mechanism instructs the PHY to re-establish the link (via the LTSSM recovery
state).
3.1.4.7
Error Forwarding
If a TLP is received with an error-forwarding trailer (Poisoned TLP received), the transaction may either
be resent or dropped and not delivered to its destination, depending on the GCR.Completion Timeout
resend enable bit and the GCR.Number of resends field. If the re-sends were unsuccessful or if re-send
is disabled, The 82580EB/DB does not initiate any additional master requests for that PCI function until
it detects an internal reset or a software reset for the associated LAN. Software is able to access device
registers after such a fault.
System logic is expected to trigger a system-level interrupt to inform the operating system of the
problem. The operating system can then stop the process associated with the transaction, re-allocate
memory instead of the faulty area, etc.
3.1.5
3.1.5.1
Data Link Layer
ACK/NAK Scheme
The 82580EB/DB will send ACK/NAK immediately in the following cases:
1. NAK needs to be sent.
2. ACK for duplicate packet
3. ACK/NAK before low power state entry
In all other cases The 82580EB/DB will schedule ACK transmission according to time-outs specified in
the PCIe specification (Depends on link speed, link width, and max_payload_size).
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3.1.5.2
Supported DLLPs
The following DLLPs are supported by the 82580EB/DB as a receiver:
Table 3-10.
DLLPs Received by the 82580EB/DB
DLLP type
Remarks
Ack
Nak
PM_Request_Ack
InitFC1-P
Virtual Channel 0 only
InitFC1-NP
Virtual Channel 0 only
InitFC1-Cpl
Virtual Channel 0 only
InitFC2-P
Virtual Channel 0 only
InitFC2-NP
Virtual Channel 0 only
InitFC2-Cpl
Virtual Channel 0 only
UpdateFC-P
Virtual Channel 0 only
UpdateFC-NP
Virtual Channel 0 only
UpdateFC-Cpl
Virtual Channel 0 only
The following DLLPs are supported by the 82580EB/DB as a transmitter:
Table 3-11.
DLLPs Initiated by the 82580EB/DB
DLLP type
Remarks
Ack
Nak
PM_Enter_L1
PM_Enter_L23
PM_Active_State_Request_L1
InitFC1-P
Virtual Channel 0 only
InitFC1-NP
Virtual Channel 0 only
InitFC1-Cpl
Virtual Channel 0 only
InitFC2-P
Virtual Channel 0 only
InitFC2-NP
Virtual Channel 0 only
InitFC2-Cpl
Virtual Channel 0 only
UpdateFC-P
Virtual Channel 0 only
UpdateFC-NP
Virtual Channel 0 only
Note:
UpdateFC-Cpl is not sent because of the infinite FC-Cpl allocation.
3.1.5.3
Transmit EDB Nullifying
In case of a necessity to re-train, there is a need to guarantee that no abrupt termination of the Tx
packet happens. For this reason, early termination of the transmitted packet is possible. This is done by
appending an EDB (EnD Bad symbol) to the packet.
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3.1.6
3.1.6.1
Physical Layer
Link Speed
The 82580EB/DB supports 2.5GT/s and 5GT/s link speeds. The following PCIe configuration bits define
the link speed:
• Max Link Speed bit in the Link CAP register — Indicates the link speed supported by The 82580EB/
DB as determined by the Disable PCIe Gen 2 bit in the PCIe PHY Auto Configuration EEPROM
section.
• Link Speed bit in the Link Status register — Indicates the negotiated Link speed.
• Target Link Speed bit in the Link Control 2 register — used to set the target compliance mode
speed when software is using the Enter Compliance bit to force a link into compliance mode. The
default value is determined by the Disable PCIe Gen 2 bit in the PCIe PHY Auto Configuration
EEPROM section.
The 82580EB/DB does not initiate a hardware autonomous speed change and as a result the Hardware
Autonomous Speed Disable bit in the PCIe Link Control 2 register is hardwired to 0b.
The 82580EB/DB supports entering compliance mode at the speed indicated in the Target Link Speed
field in the PCIe Link Control 2 register. Compliance mode functionality is controlled via the Enter
Compliance bit in the PCIe Link Control 2 register.
3.1.6.2
Link Width
The 82580EB/DB supports a maximum link width of x4, x2, or x1 as determined by the Disable Lane
bits in the PCIe PHY Auto Configuration EEPROM section.
The max link width is loaded into the Maximum Link Width field of the PCIe Capability register
(LCAP[11:6]). The hardware default is x4 link.
During link configuration, the platform and the 82580EB/DB negotiate on a common link width. The link
width must be one of the supported PCIe link widths (x1, x2, x4), such that:
• If Maximum Link Width = x4, then the 82580EB/DB negotiates to either x4, x2 or x1.1
• If Maximum Link Width = x2, then the 82580EB/DB negotiates to either x2 or x1.
• If Maximum Link Width = x1, then the 82580EB/DB only negotiates to x1.
3.1.6.3
Polarity Inversion
If polarity inversion is detected, the receiver must invert the received data.
During the training sequence, the receiver looks at Symbols 6-15 of TS1 and TS2 as the indicator of
lane polarity inversion (D+ and D- are swapped). If lane polarity inversion occurs, the TS1 Symbols 615 received are D21.5 as opposed to the expected D10.2. Similarly, if lane polarity inversion occurs,
Symbols 6-15 of the TS2 ordered set are D26.5 as opposed to the expected D5.2. This provides clear
indication of lane polarity inversion.
1. See restriction in Section 3.1.6.6.
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3.1.6.4
L0s Exit latency
The number of FTS sequences (N_FTS) sent during L1 exit, can be loaded from the EEPROM.
3.1.6.5
Lane-to-Lane De-Skew
A multi-lane link might have many sources of lane to lane skew. Although symbols are transmitted
simultaneously on all lanes, they cannot be expected to arrive at the receiver without lane-to-lane
skew. The lane-to-lane skew can include components, which are less than a bit time, bit time units
(400/200 ps for 2.5/5 Gbps), or full symbol time units (4 ns) of skew caused by the re-timing
repeaters' insert/delete operations. Receivers use TS1 or TS2 or Skip Ordered Sets (SOS) to perform
link de-skew functions.
The 82580EB/DB supports de-skew of up to 12 symbol times (48 ns for 2.5 GbpS link rate and 24 ns for
5Gbps link rate).
3.1.6.6
Lane Reversal
The following lane reversal modes are supported (see Figure 3-2):
• Lane configuration of x4, x2, and x1.
• Lane reversal in x4, x2 and in x1.
• Degraded mode (downshift) from x4 to x2 to x1 and from x2 to x1, with one restriction - if lane
reversal is executed in x4, then downshift is only to x1 and not to x2.
Note:
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The restriction requires that a x2 interface to the 82580EB/DB must connect to lanes 0 and
1 on the 82580EB/DB. The PCIe Card Electromechanical specification does not allow to
route a x2 link to a wider connector. Therefore, a system designer is not allowed to connect
a x2 link to lanes 2 and 3 of a PCIe connector. It is also recommended that when used in x2
mode on a NIC, the 82580EB/DB is connected to lanes 0 and 1 of the NIC.
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Figure 3-2.
3.1.6.7
Lane Reversal Supported Modes
Reset
The PCIe PHY can supply core reset to the 82580EB/DB. The reset can be caused by two sources:
1. Upstream move to hot reset - Inband Mechanism (LTSSM).
2. Recovery failure (LTSSM returns to detect).
3. Upstream component moves to Disable.
3.1.6.8
Scrambler Disable
The scrambler/de-scrambler functionality in the 82580EB/DB can be eliminated by upstream according
to the PCIe specification.
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3.1.7
Error Events and Error Reporting
3.1.7.1
Mechanism in General
PCIe defines two error reporting paradigms: the baseline capability and the Advanced Error Reporting
(AER) capability. The baseline error reporting capabilities are required of all PCIe devices and define the
minimum error reporting requirements. The AER capability is defined for more robust error reporting
and is implemented with a specific PCIe capability structure.
Both mechanisms are supported by the 82580EB/DB.
Also the SERR# Enable and the Parity Error bits from the legacy Command register take part in the
error reporting and logging mechanism.
In a multi-Function device, PCI Express errors that are not related to any specific Function within the
device, are logged in the corresponding status and logging registers of all Functions in that device.
These include the following cases of Unsupported Request (UR):
• A memory or I/O access that does not match any BAR for any function
• Messages.
• Configuration accesses to a non-existent function.
3.1.7.2
Error Events
Table 3-12 lists the error events identified by the 82580EB/DB and the response in terms of logging,
reporting, and actions taken. Consult the PCIe specification for the effect on the PCI Status register.
Table 3-12.
Response and Reporting of PCIe Error Events
Error Name
Error Events
Default Severity
Action
PHY errors
Receiver error
8b/10b decode errors
Correctable.
TLP to initiate NAK and drop data.
Packet framing error
Send ERR_CORR
DLLP to drop.
TLP to initiate NAK and drop data.
Data link errors
Bad TLP
Bad DLLP
Replay timer timeout
REPLAY NUM rollover
Data link layer
protocol error
•
Bad CRC
Correctable.
•
Not legal EDB
Send ERR_CORR
•
Wrong sequence number
•
Bad CRC
•
REPLAY_TIMER expiration
•
REPLAY NUM rollover
•
Violations of Flow Control
Initialization Protocol
•
Reception of NACK/ACK with no
corresponding TLP
Correctable.
DLLP to drop.
Send ERR_CORR
Correctable.
Follow LL rules.
Send ERR_CORR
Correctable.
Follow LL rules.
Send ERR_CORR
Uncorrectable.
Follow LL rules.
Send ERR_FATAL
TLP errors
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Table 3-12.
Response and Reporting of PCIe Error Events (Continued)
Error Name
Error Events
Poisoned TLP
Default Severity
Uncorrectable.
received
•
TLP with error forwarding
ERR_NONFATAL
Unsupported
•
Wrong config access
Uncorrectable.
Request (UR)
•
MRdLk
ERR_NONFATAL
•
Configuration request type 1
Log header
•
Unsupported vendor Defined
type 0 message
•
Not valid MSG code
•
Not supported TLP type
•
Wrong function number
•
Received TLP outside address
range
Action
A poisoned completion is ignored and the
request can be retried after timeout. If
enabled, the error is reported.
Log header
Uncorrectable.
Completion timeout
ERR_NONFATAL
•
Completion timeout timer
expired
Send completion with UR.
Error is non-fatal (default case)
•
Send error message if advisory
•
Retry the request once and send
advisory error message on each
failure
•
If fails, send uncorrectable error
message
Error is defined as fatal
•
Uncorrectable.
Completer abort
•
Received target access with
data size > 64-bit
Send uncorrectable error message
Send completion with CA.
ERR_NONFATAL
Log header
Unexpected
completion
Uncorrectable.
•
Received completion without a
request for it (tag, ID, etc.)
Discard TLP.
ERR_NONFATAL
Log header
Receiver overflow
Flow control protocol
error
•
•
•
Received TLP beyond allocated
credits
Uncorrectable.
Minimum initial flow control
advertisements
Uncorrectable.
Flow control update for infinite
credit advertisement
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Receiver behavior is undefined.
ERR_FATAL
ERR_FATAL
Receiver behavior is undefined. The
82580EB/DB doesn’t report violations of
Flow Control initialization protocol
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Table 3-12.
Response and Reporting of PCIe Error Events (Continued)
Error Name
Malformed TLP (MP)
Error Events
•
Data payload exceed
Max_Payload_Size
•
Received TLP data size does not
match length field
•
TD field value does not
correspond with the observed
size
•
Power management messages
that doesn’t use TC0.
•
Usage of unsupported VC.
Completion with
unsuccessful
completion status
Byte count integrity in
completion process.
3.1.7.3
When byte count isn’t compatible
with the length field and the actual
expected completion length. For
example, length field is 10 (in
Dword), actual length is 40, but the
byte count field that indicates how
many bytes are still expected is
smaller than 40, which is not
reasonable.
Default Severity
Action
Drop the packet and free FC credits.
Uncorrectable.
ERR_FATAL
Log header
No action (already done
by originator of
completion).
Free FC credits.
No action
The 82580EB/DB doesn't check for this
error and accepts these packets.
This may cause a completion timeout
condition.
Error Forwarding (TLP poisoning)
If a TLP is received with an error-forwarding trailer, the transaction can be re-sent a number of times as
programmed in the GCR register. If transaction still fails the packet is dropped and is not delivered to its
destination. The 82580EB/DB then reacts as described in Table 3-12.
The 82580EB/DB does not initiate any additional master requests for that PCI function until it detects
an internal software reset for associated LAN port. Software is able to access device registers after such
a fault.
System logic is expected to trigger a system-level interrupt to inform the operating system of the
problem. Operating systems can then stop the process associated with the transaction, re-allocate
memory instead of the faulty area, etc.
3.1.7.4
ECRC
The 82580EB/DB supports End to End CRC (ECRC) as defined in the PCIe spec. The following
functionality is provided:
• Insertion of ECRC in all transmitted TLPs
— The 82580EB/DB indicates support for insertion of ECRC in the ECRC Generation Capable bit of
the PCIe configuration registers. This bit is loaded from the “ECRC Generation” EEPROM bit.
— Insertion of ECRC is enabled by the ECRC Generation Enable bit of the PCIe configuration
registers.
• ECRC is checked on all incoming TLPs. A packet received with an ECRC error is dropped. Note that
for completions, a completion timeout will occur later (if enabled), which would result in re-issuing
the request.
— The 82580EB/DB indicates support for ECRC checking in the ECRC Check Capable bit of the
PCIe configuration registers. This bit is loaded from the “ECRC Check” EEPROM bit.
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— Checking of ECRC is enabled by the ECRC Check Enable bit of the PCIe configuration registers.
• ECRC errors are reported
• System SW may configure ECRC independently per each LAN function
3.1.7.5
Partial Read and Write Requests
Partial memory accesses
The 82580EB/DB has limited support of reads and writes requests with only part of the byte enable bits
set:
• Partial writes with at least one byte enabled are silently dropped.
• Zero-length writes has no internal impact (nothing written, no effect such as clear-by-write). The
transaction is treated as a successful operation (no error event).
• Partial reads with at least one byte enabled are handled as a full read. Any side effect of the full
read (such as clear by read) is also applicable to partial reads.
• Zero-length reads generate a completion, but the register is not accessed and undefined data is
returned.
The 82580EB/DB does not generate an error indication in response to any of the above events.
Partial I/O accesses
• Partial access on address
— A write access is discarded
— A read access returns 0xFFFF
• Partial access on data, where the address access was correct
— A write access is discarded
— A read access performs the read
3.1.7.6
Error Pollution
Error pollution can occur if error conditions for a given transaction are not isolated on the error's first
occurrence. If the Physical layer detects and reports a receiver error, to avoid having this error
propagate and cause subsequent errors at upper layers the same packet is not signaled at the data link
or transaction layers.
Similarly, when the data link layer detects an error, subsequent errors that occur for the same packet
are not signaled at the transaction layer.
3.1.7.7
Completion with Unsuccessful Completion Status
A completion with unsuccessful completion status is dropped and not delivered to its destination. An
interrupt is generated to indicate unsuccessful completion.
3.1.7.8
Error Reporting Changes
The Rev. 1.1 specification defines two changes to advanced error reporting. A new Role-Based Error
Reporting bit in the Device Capabilities register is set to 1b to indicate that these changes are
supported by the 82580EB/DB.
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1. Setting the SERR# Enable bit in the PCI Command register also enables UR reporting (in the same
manner that the SERR# Enable bit enables reporting of correctable and uncorrectable errors). In
other words, the SERR# Enable bit overrides the UR Error Reporting Enable bit in the PCIe Device
Control register.
2. Changes in the response to some uncorrectable non-fatal errors, detected in non-posted requests
to the 82580EB/DB. These are called advisory Non-fatal error cases. For each of the errors that
follow, the following behavior is defined:
a.
The Advisory Non-Fatal Error Status bit is set in the Correctable Error Status register to indicate
the occurrence of the advisory error and the Advisory Non-Fatal Error Mask corresponding bit in
the Correctable Error Mask register is checked to determine whether to proceed further with
logging and signaling.
b.
If the Advisory Non-Fatal Error Mask bit is clear, logging proceeds by setting the corresponding
bit in the Uncorrectable Error Status register, based upon the specific uncorrectable error that's
being reported as an advisory error. If the corresponding uncorrectable error bit in the
Uncorrectable Error Mask register is clear, the First Error Pointer and Header Log registers are
updated to log the error, assuming they are not still occupied by a previously unserviced error.
c.
An ERR_COR message is sent if the Correctable Error Reporting Enable bit is set in the Device
Control register. An ERROR_NONFATAL message is not sent for this error.
The following uncorrectable non-fatal errors are considered as advisory non-fatal Errors:
• A completion with an Unsupported Request or Completer Abort (UR/CA) status that signals an
uncorrectable error for a non-posted request. If the severity of the UR/CA error is non-fatal, the
completer must handle this case as an advisory non-fatal error.
• When the requester of a non-posted request times out while waiting for the associated completion,
the requester is permitted to attempt to recover from the error by issuing a separate subsequent
request, or to signal the error without attempting recovery. The requester is permitted to attempt
recovery zero, one, or multiple (finite) times, but must signal the error (if enabled) with an
uncorrectable error message if no further recovery attempts are made. If the severity of the
completion timeout is non-fatal and the requester elects to attempt recovery by issuing a new
request, the requester must first handle the current error case as an advisory non-fatal error.
• Reception of a poisoned TLP. See Section 3.1.7.3.
• When a receiver receives an unexpected completion and the severity of the unexpected completion
error is non-fatal, the receiver must handle this case as an advisory non-fatal error.
3.1.7.9
Completion with Unsupported Request (UR) or Completer
Abort (CA)
A DMA master transaction ending with an Unsupported Request (UR) completion or a Completer Abort
(CA) completion will cause all PCIe Master transactions to stop, PICAUSE.ABR bit is set and an interrupt
is generated if the appropriate Mask bits are set. To enable PCIe master transactions following reception
of an UR or CA completion Software should issue a software reset (CTRL.RST).
3.1.8
PCIe Power Management
Described in Section 5.4.1 - Power Management.
3.1.9
PCIe Programming Interface
Described in Section 9.0 - PCIe Programming Interface
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3.2
Management Interfaces
The 82580EB/DB contains twopossible interfaces to an external BMC.
• SMBus
NC-SISince the manageability sideband throughput is lower than the network link throughput, the
82580EB/DB allocates a 2 KB internal buffer for incoming network packets prior to being sent over the
sideband interface. the 82580EB/DB also allocates a 2 KB internal buffer for outgoing network packets
prior to being sent over the Ethernet link.
Note:
3.2.1
Allocated buffer size is a function of number of active LAN ports. If only 2 LAN ports are
enabled, internal Buffer size is 4 KB. If only a single LAN port is enabled, internal buffer size
is 8 KB. Enabled LAN ports are defined in the Manageability Capability/Manageability Enable
EEPROM word (Word 0x54).
SMBus
SMBus is an optional interface for pass-through and/or configuration traffic between an external BMC
and the 82580EB/DB. The SMBus commands used to configure or read status from the 82580EB/DB
are described in Chapter 11.0.
3.2.1.1
Channel Behavior
3.2.1.1.1
SMBus Addressing
The SMBus is presented as four SMBus devices on the SMBus were each device has a different SMBus
addresses. All pass-through functionality is duplicated per SMBus address, where each SMBus address
is connected to a different LAN port.
Note:
DO NOT configure ports to the same address. When a LAN function is disabled, the
corresponding SMBus address is not presented to the external BMC.
The SMBus addresses are set by SMBus Address 0, SMBus Address 1, SMBus Address 2 and SMBus
Address 3 words in the EEPROM.
The SMBus addresses (those that are enabled from the EEPROM) can be re-assigned using the SMBus
ARP protocol.
Besides the SMBus address values, all the previously stated parameters of the SMBus (SMBus channel
selection, address mode, address enable) can be set only through EEPROM configuration. The EEPROM
is read by the 82580EB/DB at power-up, resets, and other cases described in Section 4.2.
All SMBus addresses should be in Network Byte Order (NBO); most significant byte first.
3.2.1.1.2
SMBus Notification Methods
The 82580EB/DB supports three methods of informing the external BMC that it has information that is
needed to be read by an external BMC:
• SMBus alert.
• Asynchronous notify.
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• Direct receive.
The notification method that is used by the 82580EB/DB can be configured from the SMBus using the
Receive Enable command. The default method is set from the EEPROM in the Notification Method field.
The following events cause the 82580EB/DB to send a notification event to the external BMC:
• Receiving a LAN packet that was designated to the BMC.
• Receiving a request status command from the BMC initiates a status response (see
Section 11.3.2.1.2).
• Status change has occurred and the 82580EB/DB is configured to notify the external BMC upon one
of the status changes. The following event triggers a notification to the BMC:
— A change in any of the Status Data 1 bits of the Read Status command (see Section 11.3.2.2.3
for description of this command).
There might be cases where the external BMC is hung and is unable to respond to the SMBus
notification. The 82580EB/DB has a time-out value defined in the EEPROM (see Section 6.10) to avoid
hanging while waiting for the notification response. If the BMC does not respond until the timeout
expires, the notification is de-asserted.
3.2.1.1.2.1
SMBus Alert and Alert Response Method
The SMBus Alert# signal is an additional SMBus signal that acts as an asynchronous interrupt signal to
an external SMBus master. The 82580EB/DB asserts this signal each time it has a message that it
needs the external BMC to read and if the chosen notification method is the SMBus-alert method. Note
that the SMBus alert is an open-drain signal, which means that other devices besides the 82580EB/DB
can be connected on the same alert pin and the external BMC needs a mechanism to distinguish
between the alert sources as described:
The external BMC can respond to the alert by issuing an ARA (Alert Response Address) cycle (see
Figure 3-13) to detect the alert source device. The 82580EB/DB responds to the ARA cycle (if it was the
SMBus alert source) and de-asserts the alert when the ARA cycle completes. Following the ARA cycle,
the external BMC issues a Read command to retrieve the 82580EB/DB message.
Some BMCs do not implement ARA cycle transactions. These BMCs respond to an alert by issuing a
Read command to all active the 82580EB/DB ports (0xC0/0xD0 or 0xDE). The 82580EB/DB always
responds to a Read command, even if it is not the source of the notification. The default response is a
status transaction. If the 82580EB/DB is the source of the SMBus alert, it replies to the read transaction
and de-asserts the alert after the command byte of the read transaction.
The ARA cycle is an SMBus receive byte transaction to SMBus Address 0001-100b. Note that the ARA
transaction does not support PEC. The ARA transaction format is as follows:
Table 3-13.
SMBus ARA Cycle Format
1
7
1
1
7
S
Alert Response Address
Rd
A
Slave Device Address
0001 100
1
0
Manageability Slave SMBus Address
Note:
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1
0
1
1
A
P
1
Since the master-receiver (BMC receiver) is involved in the transaction it must signal the
end of data to the 82580EB/DB by generating a NACK (a ‘1’ in the ACK bit position) on the
Slave Device Address byte that was clocked out by the 82580EB/DB. The 82580EB/DB
releases the data line to allow the master to generate a STOP condition.
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3.2.1.1.2.2
Asynchronous Notify Method
When configured to asynchronous notify method, the 82580EB/DB acts as SMBus master and notifies
the external BMC by issuing a modified form of the write word transaction. The asynchronous notify
transaction SMBus address and data payload is configured using the Receive Enable command or using
the EEPROM defaults. Note that the asynchronous notify method is not protected by a PEC byte.
Table 3-14.
Asynchronous Notify Command Format
1
7
1
1
Target Address
Wr
A
Sending Device Address
BMC Slave Address
0
0
Manageability Slave SMBus Address
S
7
1
1
A
8
1
8
1
1
Data Byte Low
A
Data Byte High
A
P
Interface
0
Alert Value
0
0

0
The target address and data byte low/high is taken from the Receive Enable command (see
Section 11.3.2.1.3) or EEPROM configuration (See Section 6.10).
3.2.1.1.2.3
Direct Receive Method
If configured, the 82580EB/DB has the capability to send the message it needs to transfer to the
external BMC as a master over the SMBus, instead of alerting the BMC, and waiting for it to read the
message.
Table 3-15 shows the message format when receiving a LAN packet that was designated to the BMC.
Note that the “F”, “L” and command fields in the message are the same as the op-code returned by the
82580EB/DB in response to a BMC Receive TCO Packet Block read command (See Section 11.3.2.2.1).
The rules for the “F” and “L” flags are also the same as used in the Receive TCO Packet Block Read
command.
Table 3-15.
Direct Receive - LAN Packet Receive Transaction Format
1
S
7
1
1
Target Address
Wr
A
F
BMC Slave Address
0
0
First
Flag
8
1
8
1
Byte Count
A
Data Byte 1
A
N
0

0
1
1
6
1
L
Command
A
Last
Flag
Receive TCO Command
0
01 0000b
1
8
1
1
A
Data Byte N
A
P
0

0
Table 3-16 shows the message format when status change has occurred and the 82580EB/DB is
configured to notify the external BMC upon a status change. Note that the op-code and Status data
fields returned by the 82580EB/DB are the same as in response to a BMC Read Status command (see
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Section 11.3.2.2.3).
Table 3-16.
Direct Receive - Status Change Transaction Format
1
S
7
1
1
8
1
Target Address
Wr
BMC Slave Address
0
A
Command
A
0
Read status op-code
0

0xDD
8
1
Byte Count
A
8
1
Data 2
A
(Status Data 1)
0x02
3.2.1.1.3
0
8
1
1
Data 3
A
P
(Status Data 2)
0
0
Receive TCO Flow
The 82580EB/DB is used as a channel for receiving packets from the network link and passing them to
the external BMC. The BMC can configure the 82580EB/DB to pass specific packets to the BMC as
described in Section 11.3.2.1.6. Once a full packet is received from the link and identified as a
manageability packet that should be transferred to the BMC, the 82580EB/DB starts the receive TCO
transaction flow to the BMC.
The maximum SMBus fragment length is defined in the EERPOM (See Section 6.10.3). The 82580EB/DB
uses the SMBus notification method to notify the BMC that it has data to deliver. The packet is divided
into fragments, where the 82580EB/DB uses the maximum fragment size allowed in each fragment.
The last fragment of the packet transfer is always the status of the packet (see Section 11.3.2.2.2). As
a result, the packet is transferred in at least two fragments. The data of the packet is transferred in the
Receive TCO LAN packet transaction as described in Section 11.3.2.2.1.
When SMBus alert is selected as the BMC notification method, the 82580EB/DB notifies the BMC on
each fragment of a multi-fragment packet. When asynchronous notify is selected as the BMC
notification method, the 82580EB/DB notifies the BMC only on the first fragment of a received packet.
It is BMC’s responsibility to read the full packet including all the fragments.
Any timeout on SMBus notification results in discarding the entire packet. Any NACK by the BMC on one
of the 82580EB/DB receive bytes also causes the packet to be silently discarded.
If a SMBus time-out occurs during reception of a packet from the network to the BMC, the 82580EB/DB
silently discards the packet.
The maximum size of the received packet is limited by the 82580EB/DB hardware to 1536 bytes.
Packets larger then 1536 bytes are silently discarded. Any packet smaller than 1536 bytes is processed
by the 82580EB/DB.
Note:
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When the RCV_EN bit is cleared (see Section 11.3.2.1.3), all receive TCO functionality is
disabled, not just the packets that are directed to the BMC.
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3.2.1.1.4
Transmit TCO Flow
The 82580EB/DB is used as a channel for transmitting packets from the external BMC to the network
link. The network packet is transferred from the external BMC over the SMBus, and then, when fully
received by the 82580EB/DB, is transmitted over the network link.
Each SMBus address is connected to a different LAN port. When a packet is received in SMBus
transactions using SMBus Address 0, SMBus Address 1, SMBus Address 2 or SMBus Address 3 it is
transmitted to the network using LAN port 0, LAN port 1, LAN port 2 or LAN port 3 respectively.
The 82580EB/DB supports packets up to the Ethernet packet length (1536 bytes). SMBus transactions
can be up to 240 bytes in length, which means that packets can be transferred over the SMBus in more
than one fragment. In each command byte there are the F and L bits. When the F bit is set, it means
that this is the first fragment of the packet; L means that it is the last fragment of the packet.
Note:
When both flags are set, the entire packet is in one fragment.
The packet is sent over the network link, only after all its fragments are received correctly over the
SMBus.
The 82580EB/DB calculates the L2 CRC on the transmitted packet and adds its four bytes at the end of
the packet. Any other packet field (such as XSUM) must be calculated and inserted by the external BMC
(the 82580EB/DB does not change any field in the transmitted packet, besides adding padding and CRC
bytes).
Note:
If the packet sent by the BMC is larger than 1536 bytes, then the packet is discarded by the
82580EB/DB and Abort is asserted.
The minimum packet length defined by the 802.3 specification is 64 bytes. The 82580EB/DB pads
packets that are less than 64 bytes to meet the specification requirements. There is one exception,
when the packet sent over the SMBus is less than 32 bytes, the external BMC must pad it for at least 32
bytes. The passing bytes value should be zero.
Note:
Packets that are smaller then 32 bytes (including padding), then the packet is discarded by
the 82580EB/DB and Abort is asserted.
If the network link goes down at anytime while the 82580EB/DB is receiving a packet from the BMC for
transmission on the network, it silently discards the packet. Note that any link down event during the
transfer of a packet to the BMC over the SMBus (after it is fully received from the network), does not
stop the operation.
Note:
If a SMBus time-out occurs during transmission of a packet from the BMC to the network
the 82580EB/DB silently discards the packet.
The transmit SMBus transactions are described in Section 11.3.2.1.
Transmit Errors in Sequence Handling
Once a packet is transferred over the SMBus from the BMC to the 82580EB/DB, the F and L flags should
follow specific rules. The F flag defines that this is the first fragment of the packet; The L flag defines
that the transaction contains the last fragment of the packet.
The following table lists the different options regarding the flags in transmit packet transactions:
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Table 3-17.
Previous
Flags in Transmit Packet Transactions
Current
Action/Notes
Last
First
Accepts both.
Last
Not First
Error for current transaction. Current transaction is discarded and an abort status is asserted.
Not Last
First
Error for previous transaction. Previous transaction (until previous first) is discarded. Current
packet is processed.
Not Last
Not First
No abort status is asserted.
Processes the current transaction.
Note that since every other Block Write command in the TCO protocol has both F and L flags off, they
cause flushing any pending transmit fragments that were previously received. In other words, when
running the TCO transmit flow, no other block write transactions are allowed in between the fragments.
3.2.1.1.5
TCO Command Aborted Flow
Bit 6 in first byte of the status returned from the 82580EB/DB to the external BMC indicates that there
was a problem with previous SMBus transactions or with the completion of the operation requested in
previous transaction.
An abort can be asserted for any of the following reasons:
• Any error in the SMBus protocol (NACK, SMBus timeout).
• If the BMC does not respond until the notification timeout (programmed in the EEPROM) expires.
• Any error in compatibility between required protocols to specific functionality (Receive Enable
command with byte count not 1/14 as defined in the command specification).
• If the 82580EB/DB does not have space to store the transmit packet from the BMC (in its internal
buffer before sending it to the link). In this case, the entire transaction completes, but the packet is
discarded and the BMC is notified about it through the Abort bit.
• Error in the F/L bit sequence during multi-fragment transactions.
• If the packet sent by the BMC is larger than 1536 bytes.
• If the packet sent by the BMC is smaller than 32 bytes (including padding).
• An internal reset to the 82580EB/DB manageability unit occurred.
• Following an unsuccessful internal register access when the MCSR_TO_RETRY EEPROM bit is
cleared.
Note:
3.2.1.1.6
An abort in the status does not always imply that the last transaction of the sequence was
incorrect. There is a gap between the time the status is read from the 82580EB/DB and the
time the transaction occurred.
Concurrent SMBus Transactions
Concurrent SMBus transactions (receive, transmit and configuration read/write) are allowed between
the four addresses supported by the 82580EB/DB. Transmit fragments can be sent between receive
fragments and configuration Read/Write commands can also be issued between receive and transmit
fragments.
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3.2.1.1.7
SMBus ARP Functionality
The 82580EB/DB supports SMBus ARP protocol as defined in the SMBus 2.0 specification. The
82580EB/DB is a persistent slave address device meaning that its SMBus address is valid after powerup and loaded from the EEPROM. The 82580EB/DB supports all SMBus ARP commands defined in the
SMBus specification, both general and directed.
Note:
SMBus ARP can be disabled through EEPROM configuration (See Section 6.10.4).
SMBus-ARP transactions are described in Section 11.3.2.3.
3.2.1.1.7.1
SMBus ARP Response Behavior
The 82580EB/DB responds as four SMBus devices, meaning that it has four sets of AR/AV flags (one for
each port). The 82580EB/DB responds four times to the SMBus-ARP master, one time for each port. All
SMBus addresses are taken from the SMBus ARP addresses word of the EEPROM. The UDID is different
between the four ports in the Vendor Specific ID field, which represent the MAC address, which is
different between the four ports. The 82580EB/DB answers first as port 0, and only when the address is
assigned, starts answering as port 1, 2 and 3 to the Get UDID command.
3.2.1.1.7.2
SMBus ARP Flow
SMBus-ARP flow is based on the status of two flags:
• AV - Address Valid - This flag is set when the 82580EB/DB has a valid SMBus address.
• AR - Address Resolved - This flag is set when the 82580EB/DB’s SMBus address is resolved (SMBus
address was assigned by the SMBus-ARP process).
Note:
These flags are internal the 82580EB/DB flags and not shown to external SMBus devices.
Since the 82580EB/DB is a Persistent SMBus Address (PSA) device, the AV flag is always set, while the
AR flag is cleared after power-up until the SMBus-ARP process completes. Since the AV flag is always
set, the 82580EB/DB always has a valid SMBus address.
When the SMBus master needs to start an SMBus-ARP process, it resets (In terms of ARP functionality)
all the devices on the SMBus by issuing either Prepare to ARP or Reset Device commands. When the
82580EB/DB accepts one of these commands, it clears its AR flag (if set from previous SMBus-ARP
process), but not its AV flag (the current SMBus address remains valid until the end of the SMBus ARP
process).
The meaning of an AR flag cleared is that the 82580EB/DB answers the following SMBus ARP
transactions that are issued by the master. The SMBus master then issues a Get UDID command
(general or directed), to identify the devices on the SMBus. The 82580EB/DB responds to the directed
command all the time and to the general command only if its AR flag is not set. After the Get UDID
command, the master assigns the 82580EB/DB’s SMBus address by issuing an Assign Address
command. The 82580EB/DB checks whether the UDID matches its own UDID, and if they match, it
switches its SMBus address to the address assigned by the command (byte 17). After accepting the
Assign Address command, the AR flag is set and from this point on (as long as the AR flag is set), the
82580EB/DB does not respond to the Get UDID general command, while all other commands should be
processed even if the AR flag is set. The 82580EB/DB stores the SMBus address that was assigned in
the SMBus-ARP process in its EEPROM, so after the next power-up, it returns to its assigned SMBus
address.
Figure 3-3 shows the SMBus-ARP behavior of the 82580EB/DB.
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Figure 3-3.
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SMBus ARP Flow
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Intel® 82580EB/82580DB GbE Controller — SMBus
SMBus ARP UDID Content
The Unique Device Identifier (UDID) provides a mechanism to isolate each device for the purpose of
address assignment. Each device has a unique identifier. The 128-bit number is comprised of the
following fields:
Table 3-18.
Unique Device Identifier (UDID)
1 Byte
1 Byte
2 Bytes
2 Bytes
2 Bytes
2 Bytes
2 Bytes
4 Bytes
Device
Capabilities
Version /
Revision
Vendor ID
Device ID
Interface
Sub-system
Vendor ID
Sub- system
Device ID
Vendor
Specific ID
See below
See below
0x8086
PCIe Dev ID1
0x0004
0x0000
0x0000
See below
MSB
LSB
1. Device ID defined in Section 9.4.2.
Where:
• Vendor ID - The device manufacturer's ID as assigned by the SBS Implementers' Forum or the PCI
SIG - Constant value: 0x8086.
• Device ID - The device ID as assigned by the device manufacturer (identified by the Vendor ID
field) - Constant value: See Section 9.4.2.
• Interface - Identifies the protocol layer interfaces supported over the SMBus connection by the
device - In this case, SMBus Version 2.0 - Constant value: 0x0004.
• Sub-system Fields - These fields are not supported and return zeros.
Device Capabilities: Dynamic and Persistent Address, PEC Support bit:
Table 3-19.
Dynamic and Persistent Address, PEC Support bit
7
6
5
Address Type
0b
1b
4
3
2
1
0
Reserved (0)
Reserved (0)
Reserved (0)
Reserved (0)
Reserved (0)
PEC Supported
0b
0b
0b
0b
0b
0b
MSB
LSB
Version/Revision: UDID Version 1, Silicon Revision:
Table 3-20.
Version/Revision: UDID Version 1, Silicon Revision
7
6
Reserved (0)
Reserved (0)
5
UDID Version
Silicon Revision ID
0b
0b
001b
See below
MSB
4
3
2
1
0
LSB
Silicon Revision ID:
Table 3-21.
Silicon version
A1
Silicon Revision ID
Revision ID
001b
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NC-SI — Intel® 82580EB/82580DB GbE Controller
Vendor Specific ID - Four LSB bytes of the 82580EB/DB’s Ethernet MAC address. The 82580EB/DB
Ethernet address is taken from offsets 0 to 2 from start of the relevant sections in the EEPROM. Note
that in the 82580EB/DB there are four MAC addresses (one for each port).
Table 3-22.
Vendor Specific ID
1 Byte
1 Byte
1 Byte
1 Byte
MAC Address, byte 3
MAC Address, byte 2
MAC Address, byte 1
MAC Address, byte 0
MSB
3.2.2
LSB
NC-SI
The NC-SI interface in the 82580EB/DB is a connection to an external BMC defined by the DMTF NC-SI
protocol. It operates as a single interface with an external BMC, where all traffic between the 82580EB/
DB and the BMC flows through the interface.
3.2.2.1
Electrical Characteristics
The 82580EB/DB complies with the electrical characteristics defined in the NC-SI specification.
The 82580EB/DB NC-SI behavior is configured on power-up in the following manner:
• The 82580EB/DB provides an NC-SI clock output if defined by the NC-SI Output Clock Disable
EEPROM bit (Section 6.2.22). The default value is to use an external clock source as defined in the
NC-SI specification.
• The output driver strength for the NC-SI_CLK_OUT pad is configured by the NC-SI Clock Pad Drive
Strength bit (default = 0b) in the Functions Control EEPROM word (Section 6.2.22).
• The output driver strength for the NC-SI output signals (NC-SI_DV & NC-SI_RX) is configured by
the EEPROM NC-SI Data Pad Drive Strength bit (default = 0b see Section 6.2.22).
• The Multi-Drop NC-SI EEPROM bit (Section 6.7) defines the NC-SI topology (point-to-point or multidrop; the default is point-to-point).
The 82580EB/DB can provide an NC-SI clock output as previously mentioned. The NC-SI clock input
(NC-SI_CLK_IN) serves as an NC-SI input clock in either case. That is, if the 82580EB/DB provides an
NC-SI output clock, the platform is required to route it back through the NC-SI clock input with the
correct latency. See the Electrical chapter for more details.
The 82580EB/DB dynamically drives its NC-SI output signals (NC-SI_DV and NC-SI_RX) as required by
the sideband protocol:
• On power-up, the 82580EB/DB floats the NC-SI outputs except for NCSI_CLK_OUT.
• If the 82580EB/DB operates in point-to-point mode, then the 82580EB/DB starts driving the NC-SI
outputs some time following power-up.
• If the 82580EB/DB operates in a multi-drop mode, the 82580EB/DB drives the NC-SI outputs as
configured by the BMC.
3.2.2.2
NC-SI Transactions
The NC-SI link supports both pass-through traffic between the BMC and the 82580EB/DB LAN
functions, as well as configuration traffic between the BMC and the 82580EB/DB internal units as
defined in the NC-SI protocol. See Section 11.2.1 and Section 11.3.1 in this manual.
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3.3
Flash / EEPROM
3.3.1
EEPROM Interface
3.3.1.1
General Overview
The 82580EB/DB uses an EEPROM device for storing product configuration information. The EEPROM is
divided into three general regions:
• Hardware accessed - Loaded by the 82580EB/DB after power-up, PCI reset de-assertion,
D3 ->D0 transition, or a software-commanded EEPROM read (CTRL_EXT.EE_RST).
• Manageability firmware accessed - Loaded by the 82580EB/DB in pass-through mode after powerup or firmware reset.
• Software accessed - Used only by software. The meaning of these registers, as listed here, is a
convention for software only and is ignored by the 82580EB/DB.
Table 3-23 lists the structure of the EEPROM image in the 82580EB/DB.
Table 3-23.
EEPROM Structure
Address
0x0 – 0x9
Content
LAN 0 MAC address and software area
0xA – 0x2F
LAN 0 and Common hardware area
0x30 – 0x3E
PXE area
0x3F
Software Checksum, for Words 0x00 - 0x3E
0x40 – 0x4F
Software area
0x50 – 0x7F
FW pointers
0x80 -0xBF
LAN 1 hardware area (with SW checksum in 0xBF)
0xC0 - 0xFF
LAN 2 hardware area (with SW checksum in 0xFF)
0x100 - 0x13F
LAN 3 hardware area (with SW checksum in 0x13F)
…
Firmware structures
…
VPD area
…
CSR and Analog configuration (PCIe/PHY/PLL/SerDes structures)
The EEPROM mapping is described in Chapter 6.0.
3.3.1.2
EEPROM Device
The EEPROM interface supports an SPI interface and expects the EEPROM to be capable of 2 MHz
operation.
The 82580EB/DB is compatible with various sizes of 4-wire serial EEPROM devices. If pass-through
mode functionality is desired, up to 256 Kbits serial SPI compatible EEPROM can be used. If no
manageability mode is desired, a 128 Kbits (16 Kbytes) serial SPI compatible EEPROM can be used. All
EEPROM's are accessed in 16-bit words although the EEPROM is designed to also accept 8-bit data
accesses.
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The 82580EB/DB automatically determines the address size to be used with the SPI EEPROM it is
connected to and sets the EEPROM address size field of the EEPROM/FLASH Control and Data register
(EEC.EE_ADDR_SIZE) field appropriately. Software can use this size to determine how to access the
EEPROM. The exact size of the EEPROM is determined within one of the EEPROM words.
Note:
The different EEPROM sizes have two differing numbers of address bits (8 bits or 16 bits),
and therefore must be accessed with a slightly different serial protocol. Software must be
aware of this if it accesses the EEPROM using direct access.
3.3.1.3
HW initial load process.
Upon power on reset or PCIe reset, the 82580EB/DB reads the global device parameters from the
EEPROM including all the parameters impacting the content of the PCIe configuration space. Upon a
software reset to one of the ports (CTRL.RST set to 1), a partial load is done of the parameters relevant
to the port were the software reset occurred. Upon a software reset to all ports (CTRL.DEV_RST = 1) a
partial load is done of the parameters relevant to all ports. Table 3-24 lists the words read in each
EEPROM auto-read sequence. During full load after power-on all hardware related EEPROM words are
loaded. Following a software reset only a subset of the hardware related EEPROM words are loaded. For
details of the content of each word - see Chapter 6.0.
Note:
LANx_start parameter in Table 3-24 relates to start of LAN related EEPROM section where:
• LAN0_start = 0x0
• LAN1_start = 0x80
• LAN2_start = 0xC0
• LAN3_start = 0x100
Table 3-24.
EEPROM Auto-Load Sequence
EEPROM Word
EEPROM Word
Address
Full Load
(Powerup)
Full Load
No MGMT
(PCI RST)
EEPROM sizing and protected
fields
0x12
Y
CSR Auto Configuration Power-Up
LAN0
0x27
Y
CSR Auto Configuration Power-Up
LAN1
LAN1_start + 0x27
Y
CSR Auto Configuration Power-Up
LAN2
LAN2_start + 0x27
Y
CSR Auto Configuration Power-Up
LAN3
LAN3_start + 0x27
Y
PCIe PHY Auto Configuration
Pointer and PCIe PHY Auto
Configuration structures.
0x10
Y
Init Control 1
0x0A
PCIe init configuration 1
0x18
PCIe init configuration 2
0x19
Y
Y
PCIe init configuration 3
0x1A
Y
Y
PCIe control 1
0x1B
Y
Y
PCIe control 2
0x28
Y
Y
PCIe control 3
0x29
Y
Y
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SW1
reset
port 0
Load
SW1
reset
port 1
Load
SW1
reset
port 2
Load
SW1
reset
port 3
Load
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
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Intel® 82580EB/82580DB GbE Controller — EEPROM Interface
Table 3-24.
EEPROM Auto-Load Sequence (Continued)
EEPROM Word
Address
EEPROM Word
Full Load
(Powerup)
Full Load
No MGMT
(PCI RST)
SW1
reset
port 0
Load
SW1
reset
port 1
Load
SW1
reset
port 2
Load
SW1
reset
port 3
Load
HW Section
Functions control
0x21
Y
Device Rev ID
0x1E
Y
Y
PCIe L1 Exit latencies
0x14
Y
Y
NC-SI and PCIe completion
timeout configuration
0x15
Y
Y
Subsystem ID2
0x0B
Y
Y
Subsystem Vendor ID2
0x0C
Y
Y
Device ID - LAN 03
0x0D
Y
Y
Device ID - LAN 13
LAN1_start + 0x0D
Y
Y
23
LAN2_start + 0x0D
Y
Y
Device ID - LAN 33
LAN3_start + 0x0D
Y
Y
Vendor ID - LAN 03
0x0E
Y
Y
Dummy function device ID3
0x1D
Y
Y
MSI-X configuration LAN 0
0x16
Y
Y
MSI-X configuration LAN 1
LAN1_start + 0x16
Y
Y
MSI-X configuration LAN 2
LAN2_start + 0x16
Y
Y
MSI-X configuration LAN 3
LAN3_start + 0x16
Y
Y
Device ID - LAN
Y
LAN power consumption
0x22
Y
Y
CSR Auto Configuration Pointer
and CSR Auto Configuration
structures - LAN0
0x17
Y
Y
CSR Auto Configuration Pointer
and CSR Auto Configuration
structures - LAN1
LAN1_start + 0x17
Y
Y
CSR Auto Configuration Pointer
and CSR Auto Configuration
structures - LAN2
LAN2_start + 0x17
Y
Y
CSR Auto Configuration Pointer
and CSR Auto Configuration
structures - LAN3
LAN3_start + 0x17
Y
Y
VPD Pointer to table
0x2F
Y
Y
VPD table entry ID TAG
ID STRING
Y
Y
VPD read or write area TAG
VPD TAG 1
Y
Y
VPD read or write area length
VPD TAG 1 LENGTH
Y
Y
VPD read or write area TAG
VPD TAG 2
Y
Y
VPD read or write area length
VPD TAG 2 LENGTH
Y
Y
VPD end TAG
VPD END
Y
Y
Init Control 3 LAN 0
0x24
Y
Y
Init Control 3 LAN 1
LAN1_start + 0x24
Y
Y
Init Control 3 LAN 2
LAN2_start + 0x24
Y
Y
Init Control 3 LAN 3
LAN3_start + 0x24
Y
Y
Init Control 4 LAN 0
0x13
Y
Y
Init Control 4 LAN 1
LAN1_start + 0x13
Y
Y
LAN2_start + 0x13
Y
Y
Init Control 4 LAN 2
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Y
Y
Y
Y
Y
Y
Y
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Table 3-24.
EEPROM Auto-Load Sequence (Continued)
Full Load
(Powerup)
Full Load
No MGMT
(PCI RST)
SW1
reset
port 0
Load
SW1
reset
port 1
Load
SW1
reset
port 2
Load
SW1
reset
port 3
Load
EEPROM Word
EEPROM Word
Address
Init Control 4 LAN 3
LAN3_start + 0x13
Y
Y
LEDCTL 1 default LAN 0
0x1C
Y
Y
LEDCTL 0 default LAN 0
0x1F
Y
Y
LEDCTL 1 default LAN 1
LAN1_start + 0x1C
Y
Y
LEDCTL 0 default LAN 1
LAN1_start + 0x1F
Y
Y
LEDCTL 1 3 default LAN 2
LAN2_start + 0x1C
Y
Y
LEDCTL 0 2 default LAN 2
LAN2_start + 0x1F
Y
Y
LEDCTL 1 3 default LAN 3
LAN3_start + 0x1C
Y
Y
LEDCTL 0 2 default LAN 3
LAN3_start + 0x1F
Y
Y
End of read only area
0x2C
Y
Y
Start of read only area
0x2D
Y
Y
Init Control 2
0x0F
Y
Y
Y
Ethernet address byte 2-1 - LAN 0 0x00
Y
Y
Y
Ethernet address byte 4-3 - LAN 0 0x01
Y
Y
Y
Ethernet address byte 6-5 - LAN 0 0x02
Y
Y
Y
Ethernet address byte 2-1 - LAN 1 LAN1_start + 0x00
Y
Y
Y
Ethernet address byte 4-3 - LAN 1 LAN1_start + 0x01
Y
Y
Y
Ethernet address byte 6-5 - LAN 1 LAN1_start + 0x02
Y
Y
Y
Ethernet address byte 2-1 - LAN 2 LAN2_start + 0x00
Y
Y
Y
Ethernet address byte 4-3 - LAN 2 LAN2_start + 0x01
Y
Y
Y
Ethernet address byte 6-5 - LAN 2 LAN2_start + 0x02
Y
Y
Y
Ethernet address byte 2-1 - LAN 3 LAN3_start + 0x00
Y
Y
Y
Ethernet address byte 4-3 - LAN 3 LAN3_start + 0x01
Y
Y
Y
Ethernet address byte 6-5 - LAN 3 LAN3_start + 0x02
Y
Y
Software defined pins control LAN0
0x20
Y
Y
Software defined pins control LAN1
LAN1_start + 0x20
Y
Y
Software defined pins control LAN2
LAN2_start + 0x20
Y
Y
Software defined pins control LAN3
LAN3_start + 0x20
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Management Section4
Pass Through LAN Configuration
Pointer LAN0
0x11
Y
Pass Through LAN Configuration
Pointer LAN1
LAN1_start + 0x11
Y
Pass Through LAN Configuration
Pointer LAN2
LAN2_start + 0x11
Y
Pass Through LAN Configuration
Pointer LAN3
LAN3_start + 0x11
Y
Management Hardware Config
Control
0x23
Y
MNG Capabilities
0x54
Y
Sideband Configuration Pointer
0x57
Y
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Table 3-24.
EEPROM Auto-Load Sequence (Continued)
EEPROM Word
EEPROM Word
Address
Reserved
0x5E
Firmware patch Pointer
0x51
Full Load
(Powerup)
Full Load
No MGMT
(PCI RST)
SW1
reset
port 0
Load
SW1
reset
port 1
Load
SW1
reset
port 2
Load
SW1
reset
port 3
Load
Y
Y
HW Section Continued
Watchdog configuration
0x2E5
Y
Y
Y
Y
Y
Y
1. Upon assertion of CTRL.DEV_RST by software partial load of parameters relevant to all ports is done. Assertion of
CTRL_EXT.EE_RST causes load of per port parameters similar to CTRL.RST.
2. Loaded only if load subsystem ID bit is set
3. Loaded only if load device ID bit is set;
4. EEPROM words listed under Management Section are also loaded following Firmware Reset
5. Word also loaded following Firmware reset.
3.3.1.4
Software Accesses
The 82580EB/DB provides two different methods for software access to the EEPROM. It can either use
the built-in controller to read the EEPROM or access the EEPROM directly using the EEPROM's 4-wire
interface.
In addition, the VPD area of the EEPROM can be accessed via the VPD capability structure of the PCIe.
Software can use the EEPROM Read (EERD) register to cause the 82580EB/DB to read a word from the
EEPROM that the software can then use. To do this, software writes the address to read to the Read
Address (EERD.ADDR) field and simultaneously writes a 1b to the Start Read bit (EERD.START). The
82580EB/DB reads the word from the EEPROM, sets the Read Done bit (EERD.DONE), and places the
data in the Read Data field (EERD.DATA). Software can poll the EEPROM Read register until it sees the
Read Done bit set and then uses the data from the Read Data field. Any words read this way are not
written to the 82580EB/DB's internal registers.
Software can also directly access the EEPROM's 4-wire interface through the EEPROM/Flash Control
(EEC) register. It can use this for reads, writes, or other EEPROM operations.
To directly access the EEPROM, software should follow these steps:
1. Take ownership of both EEPROM and Flash Semaphore bits as described in Section 4.7.1.
2. Write a 1b to the EEPROM Request bit (EEC.EE_REQ).
3. Read the EEPROM Grant bit (EEC.EE_GNT) until it becomes 1b. It remains 0b as long as the
hardware is accessing the EEPROM.
4. Write or read the EEPROM using the direct access to the 4-wire interface as defined in the EEPROM/
Flash Control and Data (EEC) register. The exact protocol used depends on the EEPROM placed on
the board and can be found in the appropriate datasheet.
5. Write a 0b to the EEPROM Request bit (EEC.EE_REQ) to enable EEPROM access by other drivers.
Notes:
If direct access via the EEPROM’s 4-wire interface to a read protected area is attempted,
the 82580EB/DB blocks the access and sets the EEC.EE_BLOCKED bit.
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Following execution of an EEPROM write operation using direct access software should
verify that the write operation has completed and EEPROM status is ready before clearing
the EEC.EE_REQ and EEC.EE_GNT bits.
Software can cause the 82580EB/DB to re-read the per-function hardware accessed fields
of the EEPROM (setting the 82580EB/DB's internal registers appropriately similar to
software reset) by writing a 1b to the EEPROM Reset bit of the Extended Device Control
register (CTRL_EXT.EE_RST).
If the EEPROM does not contain a valid signature (see Section 3.3.1.5), the 82580EB/DB
assumes 16-bit addressing. In order to access an EEPROM that requires 8-bit addressing,
software must use the direct access mode.
3.3.1.5
Signature Field
The 82580EB/DB determines if an EEPROM is present by attempting to read it. The 82580EB/DB first
reads the EEPROM Sizing and Protected Fields word at address 0x12. It checks the signature value for
bits 15 and 14. If bit 15 is 0b and bit 14 is 1b, it considers the EEPROM to be present and valid and
reads additional EEPROM words and then programs its internal registers based on the values read.
Otherwise, it ignores the values it reads from that location and does not read any other words as part of
the auto-read process. However, the EEPROM is still accessible to software.
Note:
3.3.1.6
If bit 15 in the EEPROM Sizing and Protected Fields word is read as 1b, The 82580EB/DB
assumes that there is no EEPROM connected. It does not attempt any further auto-reads of
the EEPROM. if a valid image is later programmed, The 82580EB/DB will not attempt an
auto-read until a full power cycle is performed, i.e. until the assertion of LAN_PWR_GOOD.
Protected EEPROM Space
The 82580EB/DB provides a mechanism for a hidden area in the EEPROM to the host. The hidden area
cannot be accessed (read or written to) via the EEPROM registers in the CSR space. It can be accessed
only by the manageability subsystem. This area is located at the end of the EEPROM memory. It’s size
is defined by the HEPSize field in EEPROM word 0x12. Note that the current the 82580EB/DB
manageability firmware does not use the HEPSize mechanism.
A mechanism to protect part of the EEPROM from host writes is also provided. This mechanism is
controlled by word 0x2D and 0x2C that control the start and the end of the read-only area.
Note:
3.3.1.6.1
If the VPD area is mapped to the hidden EEPROM space, Software can write to the hidden
EEPROM space via the VPD capability structure in the PCIe configuration space. To avoid
such an occurrence the VPD area pointer (EEPROM word 0x2F) should be placed in the read
only area, defined by words 0x2C and 0x2D.
Initial EEPROM Programming
In most applications, initial EEPROM programming is done directly on the EEPROM pins. Nevertheless, it
is desired to enable existing software utilities (accessing the EEPROM via the host interface) to initially
program the entire EEPROM without breaking the protection mechanism. Following a power-up
sequence, the 82580EB/DB reads the hardware initialization words in the EEPROM. If the signature in
word 0x12 does not equal 01b, the EEPROM is assumed as non-programmed. There are two effects of a
non-valid signature:
• The 82580EB/DB does not read any further EEPROM data and sets the relevant registers to default.
• The 82580EB/DB enables access to any location in the EEPROM via the EEC register.
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3.3.1.6.2
Activating the Protection Mechanism
Following initialization, the 82580EB/DB reads the EEPROM and turns on the protection mechanism if
word 0x12 contains a valid signature (equals 01b) and word 0x12, bit 4 is set (enable protection). Once
the protection mechanism is turned on, words 0x12, 0x2C and 0x2D become write-protected, the area
that is defined by word 0x12 becomes hidden (read/write protected) and the area defined by words
0x2C and 0x2D become write protected.
• No matter what is designated as the read only protected area, words 0x30:0x3F (used by PXE
driver) are writable, unless defined as hidden.
3.3.1.6.3
Non Permitted Accessing to Protected Areas in the EEPROM
This paragraph refers to EEPROM accesses via the EEC (bit banging) or EERD (parallel read access)
registers. Following a write access to the protected areas in the EEPROM, hardware responds properly
on the PCIe interface but does not initiate any access to the EEPROM. Following a read access to the
hidden area in the EEPROM (as defined by word 0x12), hardware does not access the EEPROM and
returns meaningless data to the host.
Note:
Using bit banging, the SPI EEPROM can be accessed in a burst mode. For example,
providing op-code, address, and then read or write data for multiple bytes. Hardware
inhibits any attempt to access the protected EEPROM locations even in burst accesses.
Software should not access the EEPROM in a burst-write mode starting in a non-protected
area and continue to a protected one. In such a case it is not guaranteed that the write
access to any area ever takes place.
3.3.1.7
EEPROM Recovery
The EEPROM contains fields that if programmed incorrectly might affect the functionality of the
82580EB/DB. The impact can range from an incorrect setting of some function (such as LED
programming), via disabling of entire features (such as no manageability) and link disconnection, to the
inability to access the 82580EB/DB via the regular PCIe interface.
The 82580EB/DB implements a mechanism that enables recovery from a faulty EEPROM no matter
what the impact is, using an SMBus message that instructs firmware to invalidate the EEPROM.
This mechanism uses an SMBus message that the firmware is able to receive in all modes, no matter
what the content of the EEPROM is (even in diagnostic mode). After receiving this kind of message,
firmware clears the signature of the EEPROM in word 0x12 (bits 15/14 to 00b). Afterwards, the BIOS/
operating system initiates a reset to force an EEPROM auto-load process that fails in order to enable
access to the 82580EB/DB.
Firmware is programmed to receive such a command only from a PCIe reset until one of the functions
changes it’s status from D0u to D0a. Once one of the functions moves to D0a, it can be safely assumed
that the 82580EB/DB is accessible to the host and there is no further need for this function. This
reduces the possibility of malicious software using this command as a back door and limits the time
firmware must be active in non-manageability mode.
The command is sent on a fixed SMBus address of 0xC8. The format of the command is the SMBus
Block write as follows:
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EEPROM Interface — Intel® 82580EB/82580DB GbE Controller
Table 3-25.
Command Format
Function
Command
Byte Count
Data Byte
Release EEPROM
0xC7
0x01
0xAA
Notes:
This solution requires a controllable SMBus connection to the 82580EB/DB.
If more than one the 82580EB/DB part is in a state to accept this command, all of the
devices in this state will respond with an ACK to this command and accept it. A device with
one of its ports in D0a should not respond with an ACK to this command if not in D0u state.
The 82580EB/DB is guaranteed to accept the command on the SMBus interface and on
address 0xC8. If one of the functions is not in D0u state, the 82580EB/DB will not accept
the command and will return a NACK. If the SMBus address is different from 0xC8 than the
82580EB/DB disregards the command but a ACK is returned.
When one of the functions is not in D0u state the NACK is sent at end of the command. A
ACK is always returned after the address.
After receiving a release EEPROM command, firmware should keep its current state. It is
the responsibility of the programmer that is updating the EEPROM to send a firmware reset
(if required) after the full EEPROM update process completes.
3.3.1.7.1
Access to the EEPROM Controlled Feature
The EEARBC register enables access to registers that are not accessible via regular CSR access (such as
PCIe configuration read-only registers) by emulating the auto-read process. EEARBC contains five
strobe fields that emulate the internal strobes of the internal auto-read process. This register is
common to all functions and should be accessed only after verifying that it’s not being accessed by
other functions.
Table 3-26 lists the strobe to be used when emulating a read of a specific word of the EEPROM autoread feature.
Table 3-26.
Strobes for EEARBC Auto-Read Emulation
EEPROM Word
Emulated (In Hex)
0:2
Content
MAC address
Port 0 Strobe
Port 1 Strobe
Port 2 Strobe
Port 3 Strobe
VALID_CORE0
N/A
N/A
N/A
LAN1_start + 0:2
N/A
VALID_CORE1
N/A
N/A
LAN2_start + 0:2
N/A
N/A
VALID_CORE2
N/A
LAN3_start + 0:2
N/A
N/A
N/A
VALID_CORE3
0A/0F
Init control 1/2
VALID_CORE0
VALID_CORE1
VALID_CORE2
VALID_CORE3
0B/0C/0E1
Sub-system device and
vendor
VALID_COMMON
VALID_COMMON
VALID_COMMON
VALID_COMMON
1E/1D2
Dummy device ID, Rev ID
VALID_COMMON
VALID_COMMON
VALID_COMMON
VALID_COMMON
21
Function control
VALID_COMMON
VALID_COMMON
VALID_COMMON
VALID_COMMON
0D2
Device ID port 0
VALID_CORE0
N/A
N/A
N/A
LAN1_start + 0D2
Device ID port 1
N/A
VALID_CORE1
N/A
N/A
LAN2_start + 0D2
Device ID port 2
N/A
N/A
VALID_CORE2
N/A
LAN3_start + 0D2
Device ID port 3
N/A
N/A
N/A
VALID_CORE3
20
SDP control LAN 0
VALID_CORE0
N/A
N/A
N/A
LAN1_start + 20
SDP control LAN 1
N/A
VALID_CORE1
N/A
N/A
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Intel® 82580EB/82580DB GbE Controller — Shared EEPROM
Table 3-26.
Strobes for EEARBC Auto-Read Emulation (Continued)
EEPROM Word
Emulated (In Hex)
LAN2_start + 20
Content
SDP control LAN 2
LAN3_start + 20
Port 0 Strobe
N/A
Port 1 Strobe
N/A
Port 2 Strobe
VALID_CORE2
Port 3 Strobe
N/A
SDP control LAN 3
N/A
N/A
N/A
VALID_CORE3
Init control 3/4
VALID_CORE0
N/A
N/A
N/A
LAN1_start + 24/13
Init control 3/4
N/A
VALID_CORE1
N/A
N/A
LAN2_start + 24/13
Init control 3/4
N/A
N/A
VALID_CORE2
N/A
24/13
LAN3_start + 24/13
Init control 3/4
N/A
N/A
N/A
VALID_CORE3
14/153/16/18/19/
1A/1B/22/28/29/2A/
2B
PCIe and NC-SI
configuration
VALID_COMMON
VALID_COMMON
VALID_COMMON
VALID_COMMON
1C/1F4
LED control port 0
VALID_CORE0
N/A
N/A
N/A
LAN1_start + 1C/1F4
LED control port 1
N/A
VALID_CORE1
N/A
N/A
LAN2_start + 1C/1F4
LED control port 2
N/A
N/A
VALID_CORE2
N/A
LAN3_start + 1C/1F4
LED control port 3
N/A
N/A
N/A
VALID_CORE3
2E4
Watchdog configuration
VALID_CORE0
VALID_CORE1
VALID_CORE2
VALID_CORE3
2F
VPD area
N/A
N/A
N/A
N/A
1. If word 0xA was accessed before the subsystem or subvendor ID are set, care must be taken that the load Subsystem IDs bit in
word 0xA is set.
2. If word 0xA was accessed before one of the device IDs is set, care must be taken that the load Device IDs bit in word 0xA is set.
3. For the write of EEPROM word 0x15 to take effect a software reset needs to be issued following the write.
4. Part of the parameters that can be configured through the EEARBC register can be directly set through regular registers and thus
usage of this mechanism is not needed for them. Specifically, words 0x1C, 0x1F and 0x2E controls only parameters that can be
set through regular registers.
3.3.2
Shared EEPROM
The 82580EB/DB uses a single EEPROM device to configure hardware default parameters for all LAN
devices, including Ethernet Individual Addresses (IA), LED behaviors, receive packet filters for
manageability, wake-up capability, etc. Certain EEPROM words are used to specify hardware
parameters that are LAN device-independent (such as those that affect circuit behavior). Other
EEPROM words are associated with a specific LAN device. All LAN devices access the EEPROM to obtain
their respective configuration settings.
3.3.2.1
EEPROM Deadlock Avoidance
The EEPROM is a shared resource between the following clients:
• Hardware auto-read.
• Port 0 LAN driver accesses.
• Port 1 LAN driver accesses.
• Port 2 LAN driver accesses.
• Port 3 LAN driver accesses.
• Firmware accesses.
All clients can access the EEPROM using parallel access, where hardware implements the actual access
to the EEPROM. Hardware can schedule these accesses so that all clients get served without starvation.
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However, software and hardware clients can access the EEPROM using bit banging. In this case, there is
a request/grant mechanism that locks the EEPROM to the exclusive usage of one client. If this client is
stuck (without releasing the lock), the other clients are not able to access the EEPROM. In order to
avoid this, the 82580EB/DB implements a timeout mechanism, which clears the request (and as a
result releases the grant) from a client that didn't toggle the EEPROM bit-bang interface for more than
two seconds. The EEPROM deadlock avoidance mechanism is enabled when the Deadlock Timeout
Enable bit in the Initialization Control Word 1 EEPROM word is set to 1.
Notes:
If an agent that was granted access to the EEPROM for bit-bang access didn't toggle the bit
bang interface for 500 ms, it should check if it still owns the interface before continuing the
bit-banging.
Bit bang access to both Flash and EEPROM should not be done concurrently. SW should take
ownership of both EEPROM and Flash Semaphore bits as described in Section 4.7.1 before
doing a read or write bit bang operation to the EEPROM.
3.3.2.2
EEPROM Map Shared Words
The EEPROM map in Section 6.1 identifies those words configuring either LAN devices or the entire
82580EB/DB component as “all”. Those words configuring a specific LAN device parameter are
identified by their LAN number.
The following EEPROM words warrant additional notes specifically related to quad-LAN support:
Table 3-27.
Notes on EEPROM Words
Initialization Control 1,
Initialization Control 2
These EEPROM words specify hardware-default values for parameters that apply a single value
to all LAN devices, such as link configuration parameters required for auto-negotiation, wakeup settings, PCIe bus advertised capabilities, etc.
(shared between LANs)
Initialization Control 3,
Initialization Control 4
(unique to each LAN)
3.3.3
This EEPROM word configures default values associated with each LAN device’s hardware
connections, including which link mode (internal PHY, SGMII, SerDes/1000BASE-BX,
1000BASE-KX) is used with this LAN device. Because a separate EEPROM word configures the
defaults for each LAN, extra care must be taken to ensure that the EEPROM image does not
specify a resource conflict.
Vital Product Data (VPD) Support
The EEPROM image might contain an area for VPD. This area is managed by the OEM vendor and
doesn’t influence the behavior of hardware. Word 0x2F of the EEPROM image contains a pointer to the
VPD area in the EEPROM. A value of 0xFFFF means VPD is not supported and the VPD capability doesn’t
appear in the configuration space.
The VPD area should be aligned to a Dword boundary in the EEPROM.
The maximum area size is 256 bytes but can be smaller. The VPD block is built from a list of resources.
A resource can be either large or small. The structure of these resources is listed in the following tables.
Table 3-28.
Offset
Content
Revision: 2.50
October 2011
Small Resource Structure
0
1-n
Tag = 0xxx, xyyyb (Type = Small(0), Item Name =
xxxx, length = yyy bytes)
Data
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Table 3-29.
Large Resource Structure
0
1-2
3-n
Tag = 1xxx, xxxxb (Type = Large(1), Item
Name = xxxxxxx)
Length
Data
Offset
Content
The 82580EB/DB parses the VPD structure during the auto-load process (power up and PCIe reset or
warm reset) in order to detect the read-only and read/write area boundaries. The 82580EB/DB
assumes the following VPD structure:
Table 3-30.
VPD Structure
Tag
Structure
Type
Length
(Bytes)
0x82
Large
Length of
identifier string
Identifier
0x90
Large
Length of RO
area
RO data
Data
Identifier string.
VPD-R list containing one or more VPD keywords
This part is optional and might not appear.
0x91
Large
Length of R/W
area
RW data
0x78
Small
N/A
N/A
Note:
Resource Description
VPD-W list containing one or more VPD keywords. This part is
optional and might not appear.
End tag.
The VPD-R and VPD-W structures can be in any order.
If the 82580EB/DB doesn’t detect a value of 0x82 in the first byte of the VPD area, or the structure
doesn’t follow the description listed in Table 3-30, it assumes the area is not programmed and the
entire 256 bytes area is read only. If a VPD-W tag is found after the VPD-R tag, the area defined by it’s
size is writable via the VPD structure. Refer to the PCI 3.0 specification (Appendix I) for details of the
different tags.
In any case, the VPD area is accessible for read and write via the regular EEPROM mechanisms pending
the EEPROM protection capabilities enabled. For example, if VPD is in the protected area, the VPD area
is not accessible to the software device driver (parallel or serial), but accessible through the VPD
mechanism. If the VPD area is not in the protected area, then the software device driver can access all
of it for read and write.
The VPD area can be accessed through the PCIe configuration space VPD capability structure described
in Section 9.5.5. Write accesses to a read-only area or any access outside of the VPD area via this
structure are ignored.
Note:
3.3.4
3.3.4.1
Write access to Dwords, which are only partially in the read/write area, are ignored. It is
responsibility of VPD software to make the right alignment to enable a write to the entire
area.
Flash Interface
Flash Interface Operation
The 82580EB/DB provides two different methods for software access to the Flash.
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Using the legacy Flash transactions, the Flash is read from or written to each time the host CPU
performs a read or a write operation to a memory location that is within the Flash address mapping or
after a re-boot via accesses in the space indicated by the Expansion ROM Base Address register. All
accesses to the Flash require the appropriate command sequence for the device used. Refer to the
specific Flash data sheet for more details on reading from or writing to Flash. Accesses to the Flash are
based on a direct decode of CPU accesses to a memory window defined in either:
1. The 82580EB/DB's Flash Base Address register (PCIe Control register at offset 0x10 and 0x14. See
Section 9.4.11).
2. The Expansion ROM Base Address register (PCIe Control register at offset 0x30. See
Section 9.4.15).
The 82580EB/DB controls accesses to the Flash when it decodes a valid access.
Note:
Flash read accesses must always be assembled by the 82580EB/DB each time the access is
greater than a byte-wide access.
The 82580EB/DB byte reads or writes to the Flash take on the order of 2 s. The 82580EB/
DB will delay issuing PCIe credits during this time.
The 82580EB/DB supports only byte writes to the Flash.
Another way for software to access the Flash is directly using the Flash's 4-wire interface through the
Flash Access (FLA) register. It can use this for reads, writes, or other Flash operations (accessing the
Flash status register, erase, etc.).
To directly access the Flash, software should follow these steps:
1. Take ownership of both EEPROM and Flash Semaphore bits as described in Section 4.7.1.
2. Write a 1b to the Flash Request bit (FLA.FL_REQ).
3. Read the Flash Grant bit (FLA.FL_GNT) until it becomes 1b. It remains 0b as long as there are other
accesses to the Flash.
4. Write or read the Flash using the direct access to the 4-wire interface as defined in the FLA register.
The exact protocol used depends on the Flash placed on the board and can be found in the
appropriate datasheet.
5. Write a 0b to the Flash Request bit (FLA.FL_REQ).
3.3.4.2
Flash Write Control
The Flash is write controlled by the FWE bits in the EEPROM/FLASH Control and Data (EEC) register.
Note that attempts to write to the Flash device when writes are disabled (EEC.FWE = 01b) should not
be attempted. Behavior after such an operation is undefined and can result in component and/or
system hangs.
After sending one byte write to the Flash, software checks if it can send the next byte to write (check if
the write process in the Flash had finished) by reading the FLA register, If bit (FLA.FL_BUSY) in this
register is set, the current write did not finish. If bit (FLA.FL_BUSY) is clear then software can continue
and write the next byte to the Flash.
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3.3.4.3
Flash Erase Control
When software needs to erase the Flash, it should set bit FLA.FL_ER in the FLA register to 1b (Flash
erase) and then set bits EEC.FWE in the EEPROM/Flash Control register to 0b.
Hardware gets this command and sends the Erase command to the Flash. The erase process finishes by
itself. Software should wait for the end of the erase process before any further access to the Flash. This
can be checked by using the Flash write control mechanism previously described in Section 3.3.4.2.
The op-code used for erase operation is defined in the FLASHOP register.
Note:
3.3.5
Sector erase by software is not supported. In order to delete a sector, the serial (bit bang)
interface should be used.
Shared FLASH
The 82580EB/DB provides an interface to an external serial Flash/ROM memory device, as described in
Section 2.1.2. This Flash/ROM device can be mapped into memory and/or IO address space for each
LAN device through the use of Base Address Registers (BARs).
Clearing the Flash Size and CSR_Size EEPROM fields (See Section 6.2.8) to 0, disables Flash mapping
to PCI space of all LAN ports via the Flash Base Address register. Setting the LAN Boot Disable bit in the
per LAN port Initialization Control 3 EEPROM word, disables Flash mapping to PCI space for LAN 0,
LAN1, LAN2 and LAN 3 respectively, via the Expansion ROM Base Address register.
3.3.5.1
Flash Access Contention
The 82580EB/DB implements internal arbitration between Flash accesses initiated from the LAN 0, LAN
1, LAN 2 and LAN 3 devices. If accesses from these LAN devices are initiated during the same window,
The first one is served first and only then the following devices are served in a Round Robin fashion.
Note:
The 82580EB/DB does not synchronize between the entities accessing the Flash.
Contentions caused by one entity reading and the other modifying the same location is
possible.
To avoid this contention, accesses from the LAN devices should be synchronized using external software
synchronization of the memory or I/O transactions responsible for the access. It might be possible to
ensure contention-avoidance by the nature of the software sequence.
3.3.5.2
Flash Deadlock Avoidance
The Flash is a shared resource between the following clients:
• Port 0 LAN driver accesses.
• Port 1 LAN driver accesses.
• Port 2 LAN driver accesses.
• Port 3 LAN driver accesses.
• BIOS parallel access via expansion ROM mechanism.
• Firmware accesses.
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All clients can access the flash using parallel access, where hardware implements the actual access to
the Flash. Hardware can schedule these accesses so that all the clients get served without starvation.
However, the driver and firmware clients can access the serial Flash using bit banging. In this case,
there is a request/grant mechanism that locks the serial Flash to the exclusive usage of one client. If
this client is stuck without releasing the lock, the other clients are unable to access the Flash. In order
to avoid this, the 82580EB/DB implements a time-out mechanism that releases the grant from a client
that doesn’t toggle the Flash bit-bang interface for more than two seconds.
Notes:
If an agent that was granted access to the Flash for bit-bang access doesn’t toggle the bitbang interface for 500 ms, it should check that it still owns the interface before continuing
the bit banging.
Bit bang access to both Flash and EEPROM should not be done concurrently. Software
should take ownership of both EEPROM and Flash Semaphore bits as described in
Section 4.7.1 before doing a read or write bit bang operation to the Flash.
This mode is enabled by bit five in word 0xA of the EEPROM.
3.4
Configurable I/O Pins
3.4.1
General-Purpose I/O (Software-Definable Pins)
The 82580EB/DB has four software-defined pins (SDP pins) per port that can be used for miscellaneous
hardware or software-controllable purposes. These pins and their function are bound to a specific LAN
device. For example, eight SDP pins cannot be associated with a single LAN device. These pins can each
be individually configurable to act as either input or output pins. The default direction of each of the
four pins is configurable via the EEPROM as well as the default value of any pins configured as outputs.
To avoid signal contention, all four pins are set as input pins until after the EEPROM configuration has
been loaded.
In addition to all four pins being individually configurable as inputs or outputs, they can be configured
for use as General-Purpose Interrupt (GPI) inputs. To act as GPI pins, the desired pins must be
configured as inputs. A separate GPI interrupt-detection enable is then used to enable rising-edge
detection of the input pin (rising-edge detection occurs by comparing values sampled at the internal
clock rate as opposed to an edge-detection circuit). When detected, a corresponding GPI interrupt is
indicated in the Interrupt Cause register.
The use, direction, and values of SDP pins are controlled and accessed using fields in the Device Control
(CTRL) register and Extended Device Control (CTRL_EXT) register.
The SDPs can be used for special purpose mechanisms such as watch dog indication (see Section 3.4.2
for details) or IEEE 1588 support (see Section 8.9.4 for details).
3.4.2
Software Watchdog
In some situations it might be useful to give an indication to manageability firmware or to external
devices that the 82580EB/DB hardware or the software device driver is not functional. For example, in
a pass-through NIC, the 82580EB/DB might be bypassed if it is not functional. In order to provide this
functionality, a watchdog mechanism is used. This mechanism can be enabled by default, according to
EEPROM configuration.
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Once the host driver is up and it determines that hardware is functional, it might reset the watchdog
timer to indicate that the 82580EB/DB is functional. The software device driver should then re-arm the
timer periodically. If the timer is not re-armed after pre-programmed timeout, an interrupt is sent to
firmware and a pre-programmed SDPx_0 pin (either SDP0_0, SDP1_0, SDP2_0 or SDP3_0) is asserted.
Note that the SDP indication is shared between the ports. Additionally the ICR.Software WD bit can be
set to give an interrupt to the driver when the timeout is reached.
The SDPx_0 pin on which the watchdog timeout is indicated, is defined via the CTRL.SDP0_WDE bit on
the relevant port. In this mode the CTRL.SDP0_IODIR should be set to output. The CTRL.SDP0_DATA
bit indicates the polarity of the indication. Setting the CTRL.SDP0_WDE bit in one of the ports causes
the watchdog timeout indication of all ports to be routed to this SDPx_0 pin.
The register controlling the watchdog timeout feature is the WDSTP register. This register enables
defining a time-out period and the activation of this mode. Default watchdog timeout activation and
timeout period can be set in the EEPROM.
The timer is re-armed by setting the WDSWSTS.Dev_functional bit.
If software needs to trigger the watchdog immediately because it suspects hardware is stuck, it can set
the WDSWSTS.Force_WD bit. It can also supply firmware the cause for the watchdog, by placing
additional information in the WDSWSTS.Stuck Reason field.
Note:
3.4.2.1
The watchdog circuitry has no logic to detect if hardware is not functional. Additionally if the
hardware is not functional the watchdog may expire due to software not being able to
access the hardware, thus indicating there is potential hardware problem.
Watchdog Rearm
After a watchdog indication was received, in order to rearm the mechanism the following flow should be
used:
1. Clear WD_enable bit in the WDSTP register.
2. Clear SDP0_WDE bit in CTRL register.
3. Set SDP0_WDE bit in CTRL register.
4. Set WD_enable bit in the WDSTP register.
3.4.3
LEDs
The 82580EB/DB provides four LEDs per port that can be used to indicate different statuses of the
traffic. The default setup of the LEDs is done via EEPROM word offsets 0x1C and 0x1F from start of
relevant LAN port section (LAN port 0, 1, 2 and 3). This setup is reflected in the LEDCTL register of each
port. Each software device driver can change its setup individually. For each of the LEDs the following
parameters can be defined:
• Mode: Defines which information is reflected by this LED. The encoding is described in the LEDCTL
register.
• Polarity: Defines the polarity of the LED.
• Blink mode: Determines whether or not the LED should blink or be stable.
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In addition, the blink rate of all LEDs can be defined. The possible rates are 200 ms or 83 ms for each
phase. There is one rate for all the LEDs of a port.
3.5
Network Interfaces
3.5.1
Overview
The 82580EB/DB MAC provides a complete CSMA/CD function supporting IEEE 802.3 (10 Mb/s), 802.3u
(100 Mb/s), 802.3z and 802.3ab (1000 Mb/s) implementations. The 82580EB/DB performs all of the
functions required for transmission, reception, and collision handling called out in the standards.
Each 82580EB/DB MAC can be configured to use a different media interface. The 82580EB/DB supports
the following potential configurations:
• Internal copper PHY.
• External SerDes device such as an optical SerDes (SFP or on board) or backplane (1000BASE-BX or
1000BASE-KX) connections.
• External SGMII device. This mode is used for connections to external 10/100/1000 BASE-T PHYs
that support the SGMII MAC/PHY interface.
Selection between the various configurations is programmable via each MAC's Extended Device Control
register (CTRL_EXT.LINK_MODE bits) and default is set via EEPROM settings. Table 3-31 lists the
encoding on the LINK_MODE field for each of the modes.
Table 3-31.
Link Mode Encoding
Link Mode
82580EB/DB Mode
00b
Internal PHY
01b
1000BASE-KX
10b
SGMII
11b
SerDes/1000BASE-BX
The GMII/MII interface, used to communicate between the MAC and the internal PHY or the SGMII PCS,
supports 10/100/1000 Mb/s operation, with both half- and full-duplex operation at 10/100 Mb/s, and
only full-duplex operation at 1000 Mb/s.
The SerDes function can be used to implement a fiber-optics-based solution or backplane connection
without requiring an external TBI mode transceiver/SerDes.
The SerDes interface can be used to connect to SFP modules. As such, this SerDes interface has the
following limitations:
• No Tx clock
• AC coupling only
The internal copper PHY supports 10/100/1000BASE-T signaling and is capable of performing intelligent
power-management based on both the system power-state and LAN energy-detection (detection of
unplugged cables). Power management includes the ability to shut-down to an extremely low
(powered-down) state when not needed, as well as the ability to auto-negotiate to lower-speed (and
less power-hungry) 10/100 Mb/s operation when the system is in low power-states.
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3.5.2
3.5.2.1
MAC Functionality
Internal GMII/MII Interface
The 82580EB/DB’s MAC and PHY/PCS communicate through an internal GMII/MII interface that can be
configured for either 1000 Mb/s operation (GMII) or 10/100 Mb/s (MII) mode of operation. For proper
network operation, both the MAC and PHY must be properly configured (either explicitly via software or
via hardware auto-negotiation) to identical speed and duplex settings.
All MAC configuration is performed using Device Control registers mapped into system memory or I/O
space; an internal MDIO/MDC interface, accessible via software, is used to configure the Internal PHY.
In addition an external MDIO/MDC interface is available to configure external PHY’s that are connected
to the 82580EB/DB via the SGMII interface.
3.5.2.2
MDIO/MDC PHY Management Interface
The 82580EB/DB implements an IEEE 802.3 MII Management Interface (also known as the
Management Data Input/Output or MDIO Interface) between the MAC and a PHY. This interface
provides the MAC and software the ability to monitor and control the state of the PHY. The MDIO
interface defines a physical connection, a special protocol that runs across the connection, and an
internal set of addressable registers. The interface consists of a data line (MDIO) and clock line (MDC),
which are accessible by software via the MAC register space.
• MDC (management data clock): This signal is used by the PHY as a clock timing reference for
information transfer on the MDIO signal. The MDC is not required to be a continuous signal and can
be frozen when no management data is transferred. The MDC signal has a maximum operating
frequency of 2.5 MHz.
• MDIO (management data I/O): This bi-directional signal between the MAC and PHY is used to
transfer control and status information to and from the PHY (to read and write the PHY
management registers).
Software can use MDIO accesses to read or write registers of the internal PHY or an external SGMII
PHY, by accessing the 82580EB/DB's MDIC register (see Section 7.2.4). MDIO configuration setup
(Internal/ External PHY, PHY Address and Shared MDIO) is defined in the MDICNFG register (see
Section 7.2.5).
When working in SGMII/SerDes mode, the external PHY (if it exists) can be accessed either through
MDC/MDIO as previously described, or via a two wire I2C interface bus using the I2CCMD register (see
Section 7.18.8). The two wire interface bus or the MDC/MDIO bus are connected via the same pins, and
thus are mutually exclusive. In order to be able to control an external device, either by I2C or MDC/
MDIO, the 2 wires SFP Enable bit in Initialization Control 3 EEPROM word, that’s loaded into the
CTRL_EXT.I2C Enabled register bit, should be set.
As the MDC/MDIO command can be targeted either to the internal PHY or to an external bus, the
MDICNFG.destination bit is used to define the target of the transaction. Following reset the value of the
MDICNFG.destination bit is loaded from the External MDIO bit in the Initialization Control 3 EEPROM
word. When the MDICNFG.destination is clear the MDIO access is always to the internal PHY and the
PHY address is ignored.
Each port has its own MDC/MDIO or two wire interface bus. However, the MDC/MDIO bus of LAN port 0
may be shared by all ports configured to external PHY operation (MDICNFG.destination set to 1), to
allow control of a multi PHY chip with a single MDC/MDIO bus.
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MDIO operation using a shared bus or a separate bus is controlled by the MDICNFG.Com_MDIO bit
that’s loaded from Initialization Control 3 EEPROM word following reset. The external port PHY Address
is written in the MDICNFG.PHYADD register field and is loaded from the Initialization Control 4 EEPROM
word following reset.
3.5.2.2.1
Detection of External I2C or MDIO Connection
When the CTRL_EXT.I2C Enabled bit is set to 1, Software can recognize type of external PHY control
bus (MDIO or I2C) connection according to the values loaded from the EEPROM to the
MDICNFG.Destination bit and the CTRL_EXT.LINK_MODE field in the following manner:
• External I2C operating mode - MDICNFG.Destination equals 0 and CTRL_EXT.LINK_MODE is not
equal to 0.
• External MDIO Operating mode - MDICNFG.Destination equals 1 and CTRL_EXT.LINK_MODE is not
equal to 0.
3.5.2.2.2
MDIC and MDICNFG register usage
For a MDIO read cycle, the sequence of events is as follows:
1. If default MDICNFG register values loaded from EEPROM need to be updated. The processor
performs a PCIe write access to the MDICNFG register to define the:
— PHYADD = Address of external PHY.
— Destination = Internal or external PHY.
— Com_MDIO = Shared or separate MDIO external PHY connection.
2. The processor performs a PCIe write cycle to the MDIC register with:
— Ready = 0b
— Interrupt Enable set to 1b or 0b
— Opcode = 10b (read)
— REGADD = Register address of the specific register to be accessed (0 through 31).
3. The MAC applies the following sequence on the MDIO signal to the PHY:
<PREAMBLE><01><10><PHYADD><REGADD><Z> where Z stands for the MAC tri-stating the
MDIO signal.
4. The PHY returns the following sequence on the MDIO signal:
<0><DATA><IDLE>.
5. The MAC discards the leading bit and places the following 16 data bits in the MII register.
6. The 82580EB/DB asserts an interrupt indicating MDIO “Done” if the Interrupt Enable bit was set.
7. The 82580EB/DB sets the Ready bit in the MDIC register indicating the Read is complete.
8. The processor might read the data from the MDIC register and issue a new MDIO command.
For a MDIO write cycle, the sequence of events is as follows:
1. If default MDICNFG register values loaded from EEPROM need to be updated. The processor
performs a PCIe write cycle to the MDICNFG register to define the:
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— PHYADD = Address of external PHY.
— Destination = Internal or external PHY.
— Com_MDIO = Shared or separate MDIO external PHY connection.
2. The processor performs a PCIe write cycle to the MDIC register with:
— Ready = 0b.
— Interrupt Enable set to 1b or 0b.
— Opcode = 01b (write).
— REGADD = Register address of the specific register to be accessed (0 through 31).
— Data = Specific data for desired control of the PHY.
3. The MAC applies the following sequence on the MDIO signal to the PHY:
<PREAMBLE><01><01><PHYADD><REGADD><10><DATA><IDLE>
4. The 82580EB/DB asserts an interrupt indicating MDIO “Done” if the Interrupt Enable bit was set.
5. The 82580EB/DB sets the Ready bit in the MDIC register to indicate that the write operation
completed.
6. The CPU might issue a new MDIO command.
Note:
A MDIO read or write might take as long as 64 s from the processor write to the Ready bit
assertion. When a shared MDC/MDIO bus is used, each transaction can take up to 256 s to
complete if other ports are using the bus concurrently.
If an invalid opcode is written by software, the MAC does not execute any accesses to the PHY registers.
If the PHY does not generate a 0b as the second bit of the turn-around cycle for reads, the MAC aborts
the access, sets the E (error) bit, writes 0xFFFF to the data field to indicate an error condition, and sets
the Ready bit.
Note:
3.5.2.3
After a PHY reset, access through the MDIC register should not be attempted for 300 sec.
Duplex Operation with Copper PHY
The 82580EB/DB supports half-duplex and full-duplex 10/100 Mb/s MII mode either through the
internal copper PHY or SGMII interface. However, only full-duplex mode is supported when SerDes,
1000BASE-BX or 1000BASE-KX modes are used or in any 1000 Mb/s connection.
Configuration of the duplex operation of the 82580EB/DB can either be forced or determined via the
auto-negotiation process. See Section 3.5.4.4 for details on link configuration setup and resolution.
3.5.2.3.1
Full Duplex
All aspects of the IEEE 802.3, 802.3u, 802.3z, and 802.3ab specifications are supported in full-duplex
operation. Full-duplex operation is enabled by several mechanisms, depending on the speed
configuration of the 82580EB/DB and the specific capabilities of the link partner used in the application.
During full-duplex operation, the 82580EB/DB can transmit and receive packets simultaneously across
the link interface.
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In full-duplex, transmission and reception are delineated independently by the GMII/MII control
signals. Transmission starts TX_EN is asserted, which indicates there is valid data on the TX_DATA bus
driven from the MAC to the PHY/PCS. Reception is signaled by the PHY/PCS by the asserting the RX_DV
signal, which indicates valid receive data on the RX_DATA lines to the MAC.
3.5.2.3.2
Half Duplex
In half-duplex operation, the MAC attempts to avoid contention with other traffic on the link by
monitoring the CRS signal provided by the PHY and deferring to passing traffic. When the CRS signal is
de-asserted or after a sufficient Inter-Packet Gap (IPG) has elapsed after a transmission, frame
transmission begins. The MAC signals the PHY/PCS with TX_EN at the start of transmission.
In the case of a collision, the PHY/SGMII detects the collision and asserts the COL signal to the MAC.
Frame transmission stops within four link clock times and then the 82580EB/DB sends a JAM sequence
onto the link. After the end of a collided transmission, the 82580EB/DB backs off and attempts to retransmit per the standard CSMA/CD method.
Note:
The re-transmissions are done from the data stored internally in the 82580EB/DB MAC
transmit packet buffer (no re-access to the data in host memory is performed).
The MAC behavior is different if a regular collision or a late collision is detected. If a regular collision is
detected, the MAC always tries to re-transmit until the number of excessive collisions is reached. In
case of late collision, the MAC retransmission is configurable. In addition, statistics are gathered on late
collisions.
In the case of a successful transmission, the 82580EB/DB is ready to transmit any other frame(s)
queued in the MAC's transmit FIFO, after the minimum inter-frame spacing (IFS) of the link has
elapsed.
During transmit, the PHY is expected to signal a carrier-sense (assert the CRS signal) back to the MAC
before one slot time has elapsed. The transmission completes successfully even if the PHY fails to
indicate CRS within the slot time window. If this situation occurs, the PHY can either be configured
incorrectly or be in a link down situation. Such an event is counted in the Transmit without CRS statistic
register (see Section 7.19.12).
3.5.3
SerDes/1000BASE-BX, SGMII and 1000BASE-KX Support
The 82580EB/DB can be configured to follow either SGMII, SerDes/1000BASE-BX or 1000BASE-KX
standards. When in SGMII mode, the 82580EB/DB can be configured to operate in 1 Gb/s, 100 Mb/s or
10 Mb/s speeds. When in the 10/100 Mb/s speed, the 82580EB/DB can be configured to half-duplex
mode of operation. When configured for SerDes/1000BASE-BX or 1000BASE-KX operation, the port
supports only 1 Gb/s, full-duplex operation. Since the serial interfaces are defined as differential
signals, internally the hardware has analog and digital blocks. Following is the initialization/
configuration sequence for the analog and digital blocks.
3.5.3.1
SerDes Analog Block
The analog block may require some changes to it’s configuration registers in order to work properly.
There is no special requirement for designers to do these changes as the hardware internally updates
the configuration using a default sequence or a sequence loaded from the EEPROM.
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3.5.3.2
SerDes/1000BASE-BX, SGMII and 1000BASE-KX PCS Block
The link setup for SerDes/1000BASE-BX, 1000BASE-KX and SGMII are described in sections 3.5.4.1,
3.5.4.2 and 3.5.4.3 respectively.
3.5.3.3
GbE Physical Coding Sub-Layer (PCS)
The 82580EB/DB integrates the 802.3z PCS function on-chip. The on-chip PCS circuitry is used when
the link interface is configured for SerDes/1000BASE-BX, 1000BASE-KX or SGMII operation and is
bypassed for internal PHY mode.
The packet encapsulation is based on the Fiber Channel (FC0/FC1) physical layer and uses the same
coding scheme to maintain transition density and DC balance. The physical layer device is the SerDes
and is used for 1000BASE-SX, -L-, or -CX configurations.
3.5.3.3.1
8B10B Encoding/Decoding
The GbE PCS circuitry uses the same transmission-coding scheme used in the fiber channel physical
layer specification. The 8B10B-coding scheme was chosen by the standards committee in order to
provide a balanced, continuous stream with sufficient transition density to allow for clock recovery at
the receiving station. There is a 25% overhead for this transmission code, which accounts for the datasignaling rate of 1250 Mb/s with 1000 Mb/s of actual data.
3.5.3.3.2
Code Groups and Ordered Sets
Code group and ordered set definitions are defined in clause 36 of the IEEE 802.3z standard. These
represent special symbols used in the encapsulation of GbE packets. The following table contains a brief
description of defined ordered sets and included for informational purposes only. See clause 36 of the
IEEE 802.3z specification for more details.
Table 3-32.
Brief Description of Defined Ordered Sets
Code
Ordered_Set
# of Code
Groups
/C/
Configuration
4
General reference to configuration ordered sets, either /C1/ or /C2/, which
is used during auto-negotiation to advertise and negotiate link operation
information between link partners. Last 2 code groups contain
configuration base and next page registers.
/C1/
Configuration 1
4
See /C/. Differs from /C2/ in 2nd code group for maintaining proper
signaling disparity1.
/C2/
Configuration 2
4
See /C/. Differs from /C1/ in 2nd code group for maintaining proper
signaling disparity1.
/I/
IDLE
2
General reference to idle ordered sets. Idle characters are continually
transmitted by the end stations and are replaced by encapsulated packet
data. The transitions in the idle stream enable the SerDes to maintain
clock and symbol synchronization between link partners.
/I1/
IDLE 1
2
See /I/. Differs from /I2/ in 2nd code group for maintaining proper
signaling disparity1.
/I2/
IDLE 2
2
See /I/. Differs from /I1/ in 2nd code group for maintaining proper
signaling disparity1.
/R/
Carrier_Extend
1
This ordered set is used to indicate carrier extension to the receiving PCS.
It is also used as part of the end_of_packet encapsulation delimiter as well
as IPG for packets in a burst of packets.
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Table 3-32.
Brief Description of Defined Ordered Sets (Continued)
Code
Ordered_Set
# of Code
Groups
/S/
Start_of_Packet
1
The SPD (start_of_packet delimiter) ordered set is used to indicate the
starting boundary of a packet transmission. This symbol replaces the last
byte of the preamble received from the MAC layer.
/T/
End_of_Packet
1
The EPD (end_of_packet delimiter) is comprised of three ordered sets. The
/T/ symbol is always the first of these and indicates the ending boundary
of a packet.
/V/
Error_Propagation
1
The /V/ ordered set is used by the PCS to indicate error propagation
between stations. This is normally intended to be used by repeaters to
indicate collisions.
Usage
1. The concept of running disparity is defined in the standard. In summary, this refers to the 1-0 and 0-1 transitions within 8B10B
code groups.
3.5.4
Auto-Negotiation and Link Setup Features
The method for configuring the link between two link partners is highly dependent on the mode of
operation as well as the functionality provided by the specific physical layer device (PHY or SerDes). In
SerDes mode, the 82580EB/DB provides the complete PCS and Auto-negotiation functionality as
defined in IEEE802.3 clause 36 and clause 37. In internal PHY mode, the PCS and IEEE802.3 clause 28
and clause 40 auto-negotiation functions are maintained within the PHY. In SGMII mode, the 82580EB/
DB supports the SGMII link auto-negotiation process, whereas the link auto-negotiation, as defined in
IEEE802.3 clause 28 and clause 40, is done by the external PHY. In 1000BASE-KX mode, the 82580EB/
DB supports only parallel detect of 1000BASE-KX signaling and does not support the full AutoNegotiation for Backplane Ethernet protocol as defined in IEEE802.3ap clause 73.
Configuring the link can be accomplished by several methods ranging from software forcing link
settings, software-controlled negotiation, MAC-controlled auto-negotiation, to auto-negotiation initiated
by a PHY. The following sections describe processes of bringing the link up including configuration of the
82580EB/DB and the transceiver, as well as the various methods of determining duplex and speed
configuration.
The process of determining link configuration differs slightly based on the specific link mode (internal
PHY, SerDes/1000BASE-BX, SGMII or 1000BASE-KX) being used.
When operating in SerDes/1000BASE-BX mode, the PCS layer performs auto-negotiation per clause 37
of the 802.3z standard. The transceiver used in this mode does not participate in the auto-negotiation
process as all aspects of auto-negotiation are controlled by the 82580EB/DB.
When operating in internal PHY mode, the PHY performs auto-negotiation per 802.3ab clause 40 and
extensions to clause 28. Link resolution is obtained by the MAC from the PHY after the link has been
established. The MAC accomplishes this via the MDIO interface, via specific signals from the internal
PHY to the MAC, or by MAC auto-detection functions.
When operating in SGMII mode, the PCS layer performs SGMII auto-negotiation per the SGMII
specification. The external PHY is responsible for the Ethernet auto-negotiation process.
When operating in 1000BASE-KX mode the 82580EB/DB performs parallel detect of 1000BASE-KX
operation but does not implement the full Auto-Negotiation for Backplane Ethernet sequence as defined
in IEEE802.3ap clause 73.
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3.5.4.1
SerDes/1000BASE-BX Link Configuration
When using SerDes link mode, link mode configuration can be performed using the PCS function in the
82580EB/DB. The hardware supports both hardware and software auto-negotiation methods for
determining the link configuration, as well as allowing for a manual configuration to force the link.
Hardware auto-negotiation is the preferred method.
3.5.4.1.1
Signal Detect Indication
When the CONNSW.ENRGSRC bit is set to 1, the SRDS_0/1/2/3_SIG_DET pins can be connected to a
Signal Detect or loss-of-signal (LOS) output that indicates when no laser light is being received when
the 82580EB/DB is used in a 1000BASE-SX or -LX implementation (SerDes operation). It prevents false
carrier cases occurring when transmission by a non connected port couples in to the input.
Unfortunately, there is no standard polarity for this signal coming from different manufacturers. The
CTRL.ILOS bit provides for inversion of the signal from different external optical module vendors, and
should be set when the external optical module provides a negative-true loss-of-signal.
Note:
3.5.4.1.2
In internal PHY, SGMII, 1000BASE-BX and 1000BASE-KX connections energy detect source
is always internal and value of CONNSW.ENRGSRC bit should be 0. The CTRL.ILOS bit also
inverts the internal Link-up input that provides link status indication and thus should be set
to 0 for proper operation.
MAC Link Speed
SerDes operation is only defined for 1000 Mb/s operation. Other link speeds are not supported. When
configured for the SerDes interface, the MAC speed-determination function is disabled and the Device
Status register bits (STATUS.SPEED) indicate a value of 10b for 1000 Mb/s.
3.5.4.1.3
SerDes Mode Auto-Negotiation
In SerDes mode, after power up or the 82580EB/DB reset via PE_RST_N, the 82580EB/DB initiates
IEEE802.3 clause 37 auto-negotiation based on the default settings in the device control and transmit
configuration or PCS Link Control Word registers, as well as settings read from the EEPROM. If enabled
in the EEPROM, the 82580EB/DB immediately performs auto-negotiation.
TBI mode auto-negotiation, as defined in clause 37 of the IEEE 802.3z standard, provides a protocol for
two devices to advertise and negotiate a common operational mode across a GbE link. The 82580EB/DB
fully supports the IEEE 802.3z auto-negotiation function when using the on-chip PCS and internal
SerDes.
TBI mode auto-negotiation is used to determine the following information:
• Duplex resolution (even though the 82580EB/DB MAC only supports full-duplex in SerDes mode).
• Flow control configuration.
Note:
Since speed for SerDes modes is fixed at 1000 Mb/s, speed settings in the Device Control
register are unaffected by the auto-negotiation process.
Auto-negotiation can be initiated at power up or by asserting PE_RST_N and enabling
specific bits in the EEPROM.
The auto-negotiation process is accomplished by the exchange of /C/ ordered sets that contain the
capabilities defined in the PCS_ANADV register in the 3rd and 4th symbols of the ordered sets. Next
page are supported using the PCS_NPTX_AN register.
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Bits FD and LU in the Device Status (STATUS) register, and bits in the PCS_LSTS register provide status
information regarding the negotiated link.
Auto-negotiation can be initiated by the following:
• PCS_LCMD.AN_ENABLE transition from 0b to 1b
• Receipt of /C/ ordered set during normal operation
• Receipt of a different value of the /C/ ordered set during the negotiation process
• Transition from loss of synchronization to synchronized state (if AN_ENABLE is set).
• PCS_LCMD.AN_RESTART transition from 0b to 1b
Resolution of the negotiated link determines device operation with respect to flow control capability and
duplex settings. These negotiated capabilities override advertised and software-controlled device
configuration.
Software must configure the PCS_ANADV fields to the desired advertised base page. The bits in the
Device Control register are not mapped to the txConfigWord field in hardware until after autonegotiation completes. Table 3-33 lists the mapping of the PCS_ANADV fields to the Config_reg Base
Page encoding per clause 37 of the standard.
Table 3-33.
802.3z Advertised Base Page Mapping
15
14
13:12
11:9
8:7
6
5
4:0
Nextp
Ack
RFLT
rsv
ASM
Hd
Fd
rsv
The partner advertisement can be seen in the PCS_ LPAB and PCS_ LPABNP registers.
3.5.4.1.4
Forcing Link-up in SerDes Mode
Forcing link can be accomplished by software by writing a 1b to CTRL.SLU, which forces the MAC PCS
logic into a link-up state (enables listening to incoming characters when SRDS_[n]_SIG_DET is
asserted by the external optical module or an equivalent signal is asserted by the internal PHY).
Note:
The PCS_LCMD.AN_ENABLE bit must be set to a logic zero to enable forcing link.
When link is forced via the CTRL.SLU bit, the link does not come up unless the
SRDS_[n]_SIG_DET signal is asserted or an internal energy indication is received from the
SerDes receiver, implying that there is a valid signal being received by the optical module or
SerDes circuitry.
The source of the signal detect is defined by the ENRGSRC bit in the CONNSW register.
3.5.4.1.5
HW Detection of Non-Auto-Negotiation Partner
Hardware can detect a SerDes link partner that sends idle code groups continuously, but does not
initiate or answer an auto-negotiation process. In this case, hardware initiates an auto-negotiation
process, and if it fails after some timeout, a link up is assumed. To enable this functionality the
PCS_LCTL.AN_TIMEOUT_EN bit should be set. This mode can be used instead of the force link mode as
a way to support a partner that do not support auto-negotiation.
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3.5.4.2
1000BASE-KX Link Configuration
When using 1000BASE-KX link mode, link mode configuration is forced by software since the 82580EB/
DB does not support IEEE802.3 clause 73 backplane auto-negotiation.
3.5.4.2.1
MAC Link Speed
1000BASE-KX operation is only defined for 1000 Mb/s operation. Other link speeds are not supported.
When configured for the 1000BASE-KX interface, the MAC speed-determination function is disabled and
the Device Status register bits (STATUS.SPEED) indicate a value of 10b for 1000 Mb/s.
3.5.4.2.2
1000BASE-KX Auto-Negotiation
The 82580EB/DB only supports parallel detection of the 1000BASE-KX link and does not support the full
IEEE802.3ap clause 73 backplane auto-negotiation protocol.
3.5.4.2.3
Forcing Link-up in 1000BASE-KX Mode
In 1000BASE-KX mode (EXT_CTRL.LINK_MODE = 01b) the 82580EB/DB should always operates in
force link mode (CTRL.SLU bit is set to 1). The MAC PCS logic is placed in a link-up state once energy
indication is received, implying that a valid signal is being received by the 1000BASE-KX circuitry. When
in the link-up state PCS logic can lock on incoming characters.
Note:
In 1000BASE-KX mode energy detect source is internal and value of CONNSW.ENRGSRC bit
should be 0. Clause 37 auto-negotiation should be disabled and the value of the
PCS_LCMD.AN_ENABLE bit and PCS_LCMD.AN TIMEOUT EN bit should be 0.
3.5.4.2.4
1000BASE-KX HW Detection of Link Partner
In 1000BASE-KX mode, hardware detects a 1000BASE-KX link partner that sends idle or none idle code
groups continuously. In 1000BASE-KX operation force link-up mode is used.
3.5.4.3
SGMII Link Configuration
When working in SGMII mode, the actual link setting is done by the external PHY and is dependent on
the settings of this PHY. The SGMII auto-negotiation process described in the sections that follow is only
used to establish the MAC/PHY connection.
3.5.4.3.1
SGMII Auto-Negotiation
This auto-negotiation process is not dependent on the SRDS_[n]_SIG_DET signal, as this signal
indicates optical module signal detection and is not relevant in SGMII mode.
The outcome of this auto-negotiation process includes the following information:
• Link status
• Speed
• Duplex
This information is used by hardware to configure the MAC, when operating in SGMII mode.
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Bits FD and LU of the Device Status (STATUS) register and bits in the PCS_LSTS register provide status
information regarding the negotiated link.
Auto-negotiation can be initiated by the following:
• PCS_LCMD.AN_ENABLE transition from 0b to 1b.
• Receipt of /C/ ordered set during normal operation.
• Receipt of different value of the /C/ ordered set during the negotiation process.
• Transition from loss of synchronization to a synchronized state (if AN_ENABLE is set).
• PCS_LCMD.AN_RESTART transition from 0b to 1b.
Auto-negotiation determines the 82580EB/DB operation with respect to speed and duplex settings.
These negotiated capabilities override advertised and software controlled device configuration.
When working in SGMII mode, there is no need to set the PCAS_ANADV register, as the MAC
advertisement word is fixed. In SGMII mode the PCS_LCMD.AN TIMEOUT EN bit should be 0, since
Auto-negotiation outcome is required for correct operation.The result of the SGMII level autonegotiation can be read from the PCS_LPAB register.
3.5.4.3.2
Forcing Link in SGMII mode
In SGMII, forcing of the link cannot be done at the PCS level, only in the external PHY. The forced speed
and duplex settings are reflected by the SGMII auto-negotiation process; the MAC settings are
automatically done according to this functionality.
3.5.4.3.3
MAC Speed Resolution
The MAC speed and duplex settings are always set according to the SGMII auto-negotiation process.
3.5.4.4
Copper PHY Link Configuration
When operating with the internal PHY, link configuration is generally determined by PHY autonegotiation. The software device driver must intervene in cases where a successful link is not
negotiated or the designer desires to manually configure the link. The following sections discuss the
methods of link configuration for copper PHY operation.
3.5.4.4.1
PHY Auto-Negotiation (Speed, Duplex, Flow Control)
When using a copper PHY, the PHY performs the auto-negotiation function. The actual operational
details of this operation are described in the IEEE P802.3ab draft standard and are not included here.
Auto-negotiation provides a method for two link partners to exchange information in a systematic
manner in order to establish a link configuration providing the highest common level of functionality
supported by both partners. Once configured, the link partners exchange configuration information to
resolve link settings such as:
• Speed: - 10/100/1000 Mb/s
• Duplex: - Full or half
• Flow control operation
PHY specific information required for establishing the link is also exchanged.
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Note:
If flow control is enabled in the 82580EB/DB, the settings for the desired flow control
behavior must be set by software in the PHY registers and auto-negotiation restarted. After
auto-negotiation completes, the software device driver must read the PHY registers to
determine the resolved flow control behavior of the link and reflect these in the MAC
register settings (CTRL.TFCE and CTRL.RFCE).
Once PHY auto-negotiation completes, the PHY asserts a link indication (LINK) to the MAC.
Software must have set the Set Link Up bit in the Device Control register (CTRL.SLU) before
the MAC recognizes the LINK indication from the PHY and can consider the link to be up.
3.5.4.4.2
MAC Speed Resolution
For proper link operation, both the MAC and PHY must be configured for the same speed of link
operation. The speed of the link can be determined and set by several methods with the 82580EB/DB.
These include:
• Software-forced configuration of the MAC speed setting based on PHY indications, which might be
determined as follows:
— Software reads of PHY registers directly to determine the PHY's auto-negotiated speed
— Software reads the PHY's internal PHY-to-MAC speed indication (SPD_IND) using the MAC
STATUS.SPEED register
• Software asks the MAC to attempt to auto-detect the PHY speed from the PHY-to-MAC RX_CLK,
then programs the MAC speed accordingly
• MAC automatically detects and sets the link speed of the MAC based on PHY indications by using
the PHY's internal PHY-to-MAC speed indication (SPD_IND)
Aspects of these methods are discussed in the sections that follow.
3.5.4.4.2.1
Forcing MAC Speed
There might be circumstances when the software device driver must forcibly set the link speed of the
MAC. This can occur when the link is manually configured. To force the MAC speed, the software device
driver must set the CTRL.FRCSPD (force-speed) bit to 1b and then write the speed bits in the Device
Control register (CTRL.SPEED) to the desired speed setting. See Section 7.2.1 for details.
Note:
Forcing the MAC speed using CTRL.FRCSPD overrides all other mechanisms for configuring
the MAC speed and can yield non-functional links if the MAC and PHY are not operating at
the same speed/configuration.
When forcing the 82580EB/DB to a specific speed configuration, the software device driver must also
ensure the PHY is configured to a speed setting consistent with MAC speed settings. This implies that
software must access the PHY registers to either force the PHY speed or to read the PHY status register
bits that indicate link speed of the PHY.
Note:
Forcing speed settings by CTRL.SPEED can also be accomplished by setting the
CTRL_EXT.SPD_BYPS bit. This bit bypasses the MAC's internal clock switching logic and
enables the software device driver complete control of when the speed setting takes place.
The CTRL.FRCSPD bit uses the MAC's internal clock switching logic, which does delay the
affect of the speed change.
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3.5.4.4.2.2
Using Internal PHY Direct Link-Speed Indication
The 82580EB/DB’s internal PHY provides a direct internal indication of its speed to the MAC (SPD_IND).
When using the internal PHY, the most direct method for determining the PHY link speed and either
manually or automatically configuring the MAC speed is based on these direct speed indications.
For MAC speed to be set/determined from these direct internal indications from the PHY, the MAC must
be configured such that CTRL.ASDE and CTRL.FRCSPD are both 0b (both auto-speed detection and
forced-speed override disabled). After configuring the Device Control register, MAC speed is reconfigured automatically each time the PHY indicates a new link-up event to the MAC.
When MAC speed is neither forced nor auto-sensed by the MAC, the current MAC speed setting and the
speed indicated by the PHY is reflected in the Device Status register bits STATUS.SPEED.
3.5.4.4.3
MAC Full-/Half- Duplex Resolution
The duplex configuration of the link is also resolved by the PHY during the auto-negotiation process.
The 82580EB/DB’s internal PHY provides an internal indication to the MAC of the resolved duplex
configuration using an internal full-duplex indication (FDX).
When using the internal PHY, this internal duplex indication is normally sampled by the MAC each time
the PHY indicates the establishment of a good link (LINK indication). The PHY's indicated duplex
configuration is applied in the MAC and reflected in the MAC Device Status register (STATUS.FD).
Software can override the duplex setting of the MAC via the CTRL.FD bit when the CTRL.FRCDPLX (force
duplex) bit is set. If CTRL.FRCDPLX is 0b, the CTRL.FD bit is ignored and the PHY's internal duplex
indication is applied.
3.5.4.4.4
Using PHY Registers
The software device driver might be required under some circumstances to read from, or write to, the
MII management registers in the PHY. These accesses are performed via the MDIC registers (see
Section 7.2.4). The MII registers enable the software device driver to have direct control over the PHY's
operation, which can include:
• Resetting the PHY
• Setting preferred link configuration for advertisement during the auto-negotiation process
• Restarting the auto-negotiation process
• Reading auto-negotiation status from the PHY
• Forcing the PHY to a specific link configuration
The set of PHY management registers required for all PHY devices can be found in the IEEE P802.3ab
standard. The registers for the 82580EB/DB PHY are described in Section 3.5.8.
3.5.4.4.5
Comments Regarding Forcing Link
Forcing link in GMII/MII mode (internal PHY) requires the software device driver to configure both the
MAC and PHY in a consistent manner with respect to each other as well as the link partner. After
initialization, the software device driver configures the desired modes in the MAC, then accesses the
PHY registers to set the PHY to the same configuration.
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Before enabling the link, the speed and duplex settings of the MAC can be forced by software using the
CTRL.FRCSPD, CTRL.FRCDPX, CTRL.SPEED, and CTRL.FD bits. After the PHY and MAC have both been
configured, the software device driver should write a 1b to the CTRL.SLU bit.
3.5.4.5
Loss of Signal/Link Status Indication
For all modes of operation, an LOS/LINK signal provides an indication of physical link status to the MAC.
When the MAC is configured for optical SerDes mode, the input reflects loss-of-signal connection from
the optics. In backplane mode, where there is no LOS external indication, an internal indication from
the SerDes receiver can be used. In SFP systems the LOS indication from the SFP can be used. In
internal PHY mode, this signal from the PHY indicates whether the link is up or down; typically indicated
after successful auto-negotiation. Assuming that the MAC has been configured with CTRL.SLU=1b, the
MAC status bit STATUS.LU, when read, generally reflects whether the PHY or SerDes has link (except
under forced-link setup where even the PHY link indication might have been forced).
When the link indication from the PHY is de-asserted or the loss-of-signal asserted from the SerDes, the
MAC considers this to be a transition to a link-down situation (such as cable unplugged, loss of link
partner, etc.). If the Link Status Change (LSC) interrupt is enabled, the MAC generates an interrupt to
be serviced by the software device driver.
3.5.5
Ethernet Flow Control (FC)
The 82580EB/DB supports flow control as defined in 802.3x as well as the specific operation of
asymmetrical flow control defined by 802.3z.
Flow control is implemented as a means of reducing the possibility of receive buffer overflows, which
result in the dropping of received packets, and allows for local controlling of network congestion levels.
This can be accomplished by sending an indication to a transmitting station of a nearly full receive
buffer condition at a receiving station.
The implementation of asymmetric flow control allows for one link partner to send flow control packets
while being allowed to ignore their reception. For example, not required to respond to PAUSE frames.
The following registers are defined for the implementation of flow control:
• CTRL.RFCE field is used to enable reception of legacy flow control packets and reaction to them.
• CTRL.TFCE field is used to enable transmission of legacy flow control packets.
• Flow Control Address Low, High (FCAL/H) - 6-byte flow control multicast address
• Flow Control Type (FCT) 16-bit field to indicate flow control type
• Flow Control bits in Device Control (CTRL) register - Enables flow control modes.
• Discard PAUSE Frames (DPF) and Pass MAC Control Frames (PMCF) in RCTL - controls the
forwarding of control packets to the host.
• Flow Control Receive Threshold High (FCRTH0) - A 13-bit high watermark indicating receive buffer
fullness. A single watermark is used in link FC mode.
• DMA Coalescing Receive Threshold High (FCRTC) - A 13-bit high watermark indicating receive
buffer fullness when in DMA coalescing and TX buffer is empty. Value in this register can be higher
than value placed in the FCRTH0 register since watermark needs to be set to allow for reception of
only a maximum sized RX packet before XOFF flow control takes effect and reception is stopped
(See Table 3-37 for information on flow control threshold calculation).
• Flow Control Receive Threshold Low (FCRTL0) - A 13-bit low watermark indicating receive buffer
emptiness. A single watermark is used in link FC mode.
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• Flow Control Transmit Timer Value (FCTTV) - a set of 16-bit timer values to include in transmitted
PAUSE frame. A single timer is used in Link FC mode.
• Flow Control Refresh Threshold Value (FCRTV) - 16-bit PAUSE refresh threshold value
3.5.5.1
MAC Control Frames and Receiving Flow Control Packets
3.5.5.1.1
Structure of 802.3X FC Packets
Three comparisons are used to determine the validity of a flow control frame:
1. A match on the 6-byte multicast address for MAC control frames or to the station address of the
82580EB/DB (Receive Address Register 0).
2. A match on the type field.
3. A comparison of the MAC Control Op-Code field.
The 802.3x standard defines the MAC control frame multicast address as 01-80-C2-00-00-01.
The Type field in the FC packet is compared against an IEEE reserved value of 0x8808.
The final check for a valid PAUSE frame is the MAC control op-code. At this time only the PAUSE control
frame op-code is defined. It has a value of 0x0001.
Frame-based flow control differentiates XOFF from XON based on the value of the PAUSE timer field.
Non-zero values constitute XOFF frames while a value of zero constitutes an XON frame. Values in the
Timer field are in units of pause quantum (slot time). A pause quantum lasts 64 byte times, which is
converted in absolute time duration according to the line speed.
Note:
XON frame signals the cancellation of the pause from initiated by an XOFF frame - pause for
zero pause quantum.
Table 3-34 lists the structure of a 802.3X FC packet
Table 3-34.
802.3X Packet Format
DA
01_80_C2_00_00_01 (6 bytes)
SA
Port MAC address (6 bytes)
Type
0x8808 (2 bytes)
Op-code
0x0001 (2 bytes)
Time
XXXX (2 bytes)
Pad
42 bytes
CRC
4 bytes
3.5.5.1.2
Operation and Rules
The 82580EB/DB operates in Link FC.
• Link FC is enabled by the RFCE bit in the CTRL Register.
Note:
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Link flow control capability is negotiated between link partners via the auto negotiation
process. It is the software device driver responsibility to reconfigure the link flow control
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configuration after the capabilities to be used where negotiated as it might modify the value
of these bits based on the resolved capability between the local device and the link partner.
Once the receiver has validated receiving an XOFF, or PAUSE frame, the 82580EB/DB performs the
following:
• Increments the appropriate statistics register(s)
• Sets the Flow_Control State bit in the FCSTS0 register.
• Initializes the pause timer based on the packet's PAUSE timer field (overwriting any current timer’s
value)
• Disables packet transmission or schedules the disabling of transmission after the current packet
completes.
Resumption of transmission might occur under the following conditions:
• Expiration of the PAUSE timer
• Reception of an XON frame (a frame with its PAUSE timer set to 0b)
Both conditions clear the relevant Flow_Control State bit in the relevant FCSTS0 register and
transmission can resume. Hardware records the number of received XON frames.
3.5.5.1.3
Timing Considerations
When operating at 1 Gb/s line speed, the 82580EB/DB must not begin to transmit a (new) frame more
than two pause-quantum-bit times after receiving a valid link XOFF frame, as measured at the wires. A
pause quantum is 512-bit times.
When operating in full duplex at 100 Mb/s or 1 Gb/s line speeds, the 82580EB/DB must not begin to
transmit a (new) frame more than 576-bit times after receiving a valid link XOFF frame, as measured at
the wire.
3.5.5.2
PAUSE and MAC Control Frames Forwarding
Two bits in the Receive Control register, control forwarding of PAUSE and MAC control frames to the
host. These bits are Discard PAUSE Frames (DPF) and Pass MAC Control Frames (PMCF):
• The DPF bit controls forwarding of PAUSE packets to the host.
• The PMCF bit controls forwarding of non-PAUSE packets to the host.
Note:
When flow control reception is disabled (CTRL.RFCE = 0), legacy flow control packets are
not recognized and are parsed as regular packets.
Table 3-35 lists the behavior of the DPF bit.
Table 3-35.
RFCE
Forwarding of PAUSE Packet to Host (DPF Bit)
DPF
Are FC Packets Forwarded to Host?
0
X
Yes. Packets needs to pass the L2 filters (see Section 8.1.2.1).1
1
0
Yes. Packets needs to pass the L2 filters (see Section 8.1.2.1).
1. The flow control multicast address is not part of the L2 filtering unless explicitly required.
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Table 3-36.
Transfer of Non-PAUSE Control Packets to Host (PMCF Bit)
RFCE
PMCF
0
X
Yes. Packets needs to pass the L2 filters (see Section 8.1.2.1).
X
0
Yes. Packets needs to pass the L2 filters (see Section 8.1.2.1).
3.5.5.3
Are Non-FC MAC Control Packets Forwarded to Host?
Transmission of PAUSE Frames
The 82580EB/DB generates PAUSE packets to ensure there is enough space in its receive packet
buffers to avoid packet drop. The 82580EB/DB monitors the fullness of its receive packet buffers and
compares it with the contents of a programmable threshold. When the threshold is reached, the
82580EB/DB sends a PAUSE frame. The 82580EB/DB also supports the sending of link Flow Control
(FC).
Note:
Similar to receiving link flow control packets previously mentioned, link XOFF packets can
be transmitted only if this configuration has been negotiated between the link partners via
the auto-negotiation process or some higher level protocol. The setting of this bit by the
software device driver indicates the desired configuration.
The transmission of flow control frames should only be enabled in full-duplex mode per the
IEEE 802.3 standard. Software should ensure that the transmission of flow control packets
is disabled when the 82580EB/DB is operating in half-duplex mode.
3.5.5.3.1
Operation and Rules
Transmission of link PAUSE frames is enabled by software writing a 1b to the TFCE bit in the Device
Control register.
the 82580EB/DB sends a PAUSE frame when Rx packet buffer is full above the high threshold defined in
the Flow Control Receive Threshold High (FCRT0.RTH) register field. When the threshold is reached, the
82580EB/DB sends a PAUSE frame with its pause time field equal to FCTTV. The threshold should be
large enough to overcome the worst case latency from the time that crossing the threshold is sensed till
packets are not received from the link partner. The Flow Control Receive Threshold High value should
be calculated as follows:
Flow Control Receive Threshold High = Internal RX Buffer Size - (Threshold
Cross to XOFF Transmission + Round-trip Latency + XOFF Reception to Link
Partner response)
Parameter values to be used for calculating the FCRTH0.RTH value can be found in Table 3-37.
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Table 3-37.
Flow Control Receive Threshold High (FCRTH0.RTH) Value Calculation
Latency Parameter
Affected by
Parameter Value
Threshold Cross to XOFF
Transmission
Max packet size
Max packet Size * 1.25
XOFF Reception to Link Partner
response
Max packet size
Max packet size
Round trip latency
The latencies on the wire and the LAN devices at
both sides of the wire
Note:
320 Byte (for 1000Base-T
operation).
When DMA Coalescing is enabled (DMACR.DMAC_EN = 1) value placed in the
FCRTC.RTH_Coal field should be equal or lower than:
FCRTC.RTH_Coal = FCRTH0.RTH + Max packet Size * 1.25
The FCRTC.RTH_Coal is used as the high watermark to generate XOFF flow control packets when the
internal TX buffer is empty and the 82580EB/DB is executing DMA coalescing. In this case no delay to
transmission of flow control packet exists so it’s possible to increase level of watermark before issuing a
XOFF flow control frame.
After transmitting a PAUSE frame the 82580EB/DB activates an internal shadow counter that reflects
the link partner pause timeout counter. When the counter reaches the value indicated in the FCRTV
register, then, if the PAUSE condition is still valid (meaning that the buffer fullness is still above the high
watermark), a XOFF message is sent again.
Once the receive buffer fullness reaches the low water mark, the 82580EB/DB sends a XON message (a
PAUSE frame with a timer value of zero). Software enables this capability with the XONE field of the
FCRTL.
The 82580EB/DB sends an additional PAUSE frame if it has previously sent one and the packet buffer
overflows. This is intended to minimize the amount of packets dropped if the first PAUSE frame did not
reach its target.
3.5.5.3.2
Software Initiated PAUSE Frame Transmission
The 82580EB/DB has the added capability to transmit an XOFF frame via software. This is accomplished
by software writing a 1b to the SWXOFF bit of the Transmit Control register. Once this bit is set,
hardware initiates the transmission of a PAUSE frame in a manner similar to that automatically
generated by hardware.
The SWXOFF bit is self-clearing after the PAUSE frame has been transmitted.
Note:
The Flow Control Refresh Threshold mechanism does not work in the case of softwareinitiated flow control. Therefore, it is the software’s responsibility to re-generate PAUSE
frames before expiration of the pause counter at the other partner's end.
The state of the CTRL.TFCE bit or the negotiated flow control configuration does not affect software
generated PAUSE frame transmission.
Note:
Software sends an XON frame by programming a 0b in the PAUSE timer field of the FCTTV
register. Software generation of XON packet is not allowed while the hardware flow control
mechanism is active, as both use the FCTTV registers for different purposes.
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XOFF transmission is not supported in 802.3x for half-duplex links. Software should not
initiate an XOFF or XON transmission if the 82580EB/DB is configured for half-duplex
operation.
When flow control is disabled, pause packets (XON, XOFF, and other FC) are not detected as
flow control packets and can be counted in a variety of counters (such as multicast).
3.5.5.4
IPG Control and Pacing
The 82580EB/DB supports the following modes of controlling IPG duration:
• Fixed IPG - the IPG is extended by a fixed duration
3.5.5.4.1
Fixed IPG Extension
The 82580EB/DB allows controlling of the IPG duration. The IPGT configuration field enables an
extension of IPG in 4-byte increments. One possible use of this capability is to allow the insertion of
bytes into the transmit packet after it has been transmitted by the 82580EB/DB without violating the
minimum IPG requirements. For example, a security device connected in series to the 82580EB/DB
might add security headers to transmit packets before the packets are transmitted on the network.
3.5.6
3.5.6.1
Loopback Support
General
The 82580EB/DB supports the following types of internal loopback in the LAN interfaces:
• MAC Loopback (Point 1)
• PHY Loopback (Point 2)
• SerDes, SGMII or 1000BASE-KX Loopback (Point 3)
• External PHY Loopback (Point 4)
By setting the device to loopback mode, packets that are transmitted towards the line will be looped
back to the host. The 82580EB/DB is fully functional in these modes, just not transmitting data over the
lines. Figure 3-4 shows the points of loopback.
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Figure 3-4.
82580EB/DB Loopback Modes
3.5.6.2
MAC Loopback
In MAC loopback, the PHY and SerDes blocks are not functional and data is looped back before these
blocks.
3.5.6.2.1
Setting the 82580EB/DB to MAC loopback Mode
The following procedure should be used to put the 82580EB/DB in MAC loopback mode:
• Set RCTL.LBM to 2'b01 (bits 7:6)
• Set CTRL.SLU (bit 6, should be set by default)
• Set CTRL.FRCSPD & FRCDPLX (bits 11&12)
• Set CTRL.SPEED to 2'b10 (1G) and CTRL.FD
• Set CTRL.ILOS
• Disable Auto-Negotiation in the PHY control register (Address 0 in the PHY):
— Clear Auto Neg enable bit (Bit 12)
• Set CTRL_EXT.LINK_MODE = 11b
Filter configuration and other TX/RX processes are the same as in normal mode.
Note:
3.5.6.3
This configuration is for a case were there is no link in the PHY. If there is a link, ILOS bit
should be cleared.
Internal PHY Loopback
In PHY loopback the SerDes block is not functional and data is looped back at the end of the PHY
functionality. This means all the design that is functional in copper mode, is involved in the loopback
3.5.6.3.1
Setting the 82580EB/DB to Internal PHY loopback Mode
The following procedure should be used to place the 82580EB/DB in PHY loopback mode on LAN port
0,1,2 or 3:
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• Set Link mode to Internal PHY: CTRL_EXT.LINK_MODE = 00b.
• In PHY control register (PCTRL - Address 0 in the PHY):
— Set Duplex mode (bit 8)
— Set Loopback bit (Bit 14)
— Clear Auto Neg enable bit (Bit 12)
— Set speed using bits 6 and 13 as described in EAS.
— Register value should be:
For 10 Mbps 0x4100
For 100 Mbps 0x6100
For 1000 Mbps 0x4140.
• Determine the exact type of loopback using the loopback control register (PHLBKC - address 19d,
See Section 7.24.2.16).
Note:
While in MII loopback mode PHLBKC.Force Link Status should be set to 1 to receive valid
link state and be able to Transmit and Receive normally.
Make sure a Configure command is re-issued (loopback bits set to 00b) to cancel the
loopback mode.
3.5.6.4
SerDes, SGMII and 1000BASE-KX Loopback
In SerDes, SGMII or 1000BASE-KX loopback the PHY block is not functional and data is looped back at
the end of the relevant functionality. This means all the design that is functional in SerDes/SGMII or
1000BASE-KX mode, is involved in the loopback.
Note:
3.5.6.4.1
SerDes loopback is functional only if the SerDes link is up.
Setting the 82580EB/DB to SerDes/1000BASE-BX, SGMII or
1000BASE-KX loopback Mode
The following procedure should be used to place the 82580EB/DB in SerDes loopback mode:
• Set Link mode to either SerDes, SGMII or 1000BASE-KX by:
— 1000BASE-KX: CTRL_EXT.LINK_MODE = 01b
— SGMII: CTRL_EXT.LINK_MODE = 10b
— SerDes/1000BASE-BX: CTRL_EXT.LINK_MODE = 11b
• Configure SERDES to loopback: RCTL.LBM = 11b
• Move to Force mode by setting the following bits:
— CTRL.FD (CSR 0x0 bit 0) = 1
— CTRL.SLU (CSR 0x0 bit 6) = 1
— CTRL.RFCE (CSR 0x0 bit 27) = 0
— CTRL.TFCE (CSR 0x0 bit 28) = 0
— PCS_LCTL.FORCE_LINK (CSR 0X4208 bit 5) = 1
— PCS_LCTL.FSD (CSR 0X4208 bit 4) = 1
— PCS_LCTL.FDV (CSR 0X4208 bit 3) = 1
— PCS_LCTL.FLV (CSR 0X4208 bit 0) = 1
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— PCS_LCTL.AN_ENABLE (CSR 0X4208 bit 16) = 0
—
3.5.6.5
External PHY Loopback
In External PHY loopback the SerDes block is not functional and data is sent through the MDI interface
and looped back using an external loopback plug. This means all the design that is functional in copper
mode, is involved in the loopback. If connected at 10/100 Mbps the loopback will work without any
special setup. For 1000 Mbps operation, the following flow should be used:
3.5.6.5.1
Setting the 82580EB/DB Internal PHY to External Loopback Mode
The following procedure should be used to put the 82580EB/DB internal PHY into external loopback
mode:
• Set Link mode to PHY: CTRL_EXT.LINK_MODE = 00b
• In PHY control register (Address 0 in the PHY):
— Set Duplex mode (bit 8)
— Clear Loopback bit (Bit 14)
— Set Auto Neg enable bit (Bit 12)
• Restart auto-negotiation (Set bit 9)
• Reset the PHY (Set bit 15).
• Wait for auto-negotiation to complete, then transmit and receive normally.
3.5.7
Integrated Copper PHY Functionality
The register set used to control the PHY functionality (PHYREG) is described in Section 7.24. the
registers can be programmed using the MDIC register (See Section 7.2.4).
3.5.7.1
Determining Link State
The PHY and its link partner determine the type of link established through one of three methods:
• Auto-negotiation
• Parallel detection
• Forced operation
Auto-negotiation is the only method allowed by the 802.3ab standard for establishing a 1000BASE-T
link, although forced operation could be used for test purposes. For 10/100 links, any of the three
methods can be used. The following sections discuss each in greater detail.
Figure 3-5 provides an overview of link establishment. First the PHY checks if auto-negotiation is
enabled. By default, the PHY supports auto-negotiation, see PHY Register 0, bit 12. If not, the PHY
forces operation as directed. If auto-negotiation is enabled, the PHY begins transmitting Fast Link
Pulses (FLPs) and receiving FLPs from its link partner. If FLPs are received by the PHY, auto-negotiation
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proceeds. It also can receive 100BASE-TX MLT3 and 10BASE-T Normal Link Pulses (NLPs). If either
MLT3 or NLPs are received, it aborts FLP transmission and immediately brings up the corresponding
half-duplex link.
Figure 3-5.
3.5.7.1.1
Link EstablishmentOverview of Link Establishment
False Link
The PHY does not falsely establish link with a partner operating at a different speed. For example, the
PHY does not establish a 1 Gb/s or 10 Mb/s link with a 100 MB/s link partner.
When the PHY is first powered on, reset, or encounters a link down state, it must determine the line
speed and operating conditions to use for the network link.
The PHY first checks the MDIO registers (initialized via the hardware control interface or written by
software) for operating instructions. Using these mechanisms, designers can command the PHY to do
one of the following:
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• Force twisted-pair link operation to:
— 1000T, full duplex
— 1000T, half duplex
— 100TX, full duplex
— 100TX, half duplex
— 10BASE-T, full duplex
— 10BASE-T, half duplex
• Allow auto-negotiation/parallel-detection.
In the first six cases (forced operation), the PHY immediately begins operating the network interface as
commanded. In the last case, the PHY begins the auto-negotiation/parallel-detection process.
3.5.7.1.2
Forced Operation
Forced operation can be used to establish 10 Mb/s and 100 Mb/s links, and 1000 Mb/s links for test
purposes. In this method, auto-negotiation is disabled completely and the link state of the PHY is
determined by MII Register 0.
Note:
When speed is forced, the auto cross-over feature is not functional.
In forced operation, the designer sets the link speed (10, 100, or 1000 MB/s) and duplex state (full or
half). For Gigabit (1000 MB/s) links, designers must explicitly designate one side as the master and the
other as the slave.
Note:
The paradox (per the standard): If one side of the link is forced to full-duplex operation and
the other side has auto-negotiation enabled, the auto-negotiating partner parallel-detects
to a half-duplex link while the forced side operates as directed in full-duplex mode. The
result is spurious, unexpected collisions on the side configured to auto-negotiate.
Table 3-38 lists link establishment procedures.
Table 3-38.
Determining Duplex State Via Parallel Detection
Configuration
Result
Both sides set for auto-negotiate
Link is established via auto-negotiation.
Both sides set for forced operation
No problem as long as duplex settings match.
One side set for auto-negotiation and the other for forced, halfduplex
Link is established via parallel detect.
One side set for auto-negotiation and the other for forced fullduplex
Link is established; however, sides disagree, resulting in
transmission problems (Forced side is full-duplex, autonegotiation side is half-duplex.).
3.5.7.1.3
Auto Negotiation
The PHY supports the IEEE 802.3u auto-negotiation scheme with next page capability. Next page
exchange uses Register 7 to send information and Register 8 to receive them. Next page exchange can
only occur if both ends of the link advertise their ability to exchange next pages.
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3.5.7.1.4
Parallel Detection
Parallel detection can only be used to establish 10 and 100 Mb/s links. It occurs when the PHY tries to
negotiate (transmit FLPs to its link partner), but instead of sensing FLPs from the link partner, it senses
100BASE-TX MLT3 code or 10BASE-T Normal Link Pulses (NLPs) instead. In this case, the PHY
immediately stops auto-negotiation (terminates transmission of FLPs) and immediately brings up
whatever link corresponds to what it has sensed (MLT3 or NLPs). If the PHY senses both technologies,
the parallel detection fault is detected and the PHY continues sending FLPs.
With parallel detection, it is impossible to determine the true duplex state of the link partner and the
IEEE standard requires the PHY to assume a half-duplex link. Parallel detection also does not allow
exchange of flow-control ability (PAUSE and ASM_DIR) or the master/slave relationship required by
1000BASE-T. This is why parallel detection cannot be used to establish GbE links.
3.5.7.1.5
Auto Cross-Over
Twisted pair Ethernet PHY's must be correctly configured for MDI or MDI-X operation to inter operate.
This has historically been accomplished using special patch cables, magnetics pinouts or Printed Circuit
Board (PCB) wiring. The PHY supports the automatic MDI/MDI-X configuration originally developed for
1000Base-T and standardized in IEEE 802.3u section 40. Manual (non-automatic) configuration is still
possible.
For 1000BASE-T links, pair identification is determined automatically in accordance with the standard.
For 10/100/1000 Mb/s links and during auto-negotiation, pair usage is determined by bits 9 and 10 in
the PHCTRL2 register (PHYREG18). The PHY activates an automatic cross-over detection function. If bit
PHCTRL2.Automatic MDI/MDI-X (18.10) = 1b, the PHY automatically detects which application is being
used and configures itself accordingly.
The automatic MDI/MDI-X state machine facilitates switching the MDI_PLUS[0] and MDI_MINUS[0]
signals with the MDI_PLUS[1] and MDI_MINUS[1] signals, respectively, prior to the auto-negotiation
mode of operation so that FLPs can be transmitted and received in compliance with Clause 28 autonegotiation specifications. An algorithm that controls the switching function determines the correct
polarization of the cross-over circuit. This algorithm uses an 11-Bit Linear Feedback Shift Register
(LFSR) to create a pseudo-random sequence that each end of the link uses to determine its proposed
configuration. After making the selection to either MDI or MDI-X, the node waits for a specified amount
of time while evaluating its receive channel to determine whether the other end of the link is sending
link pulses or PHY-dependent data. If link pulses or PHY-dependent data are detected, it remains in that
configuration. If link pulses or PHY-dependent data are not detected, it increments its LFSR and makes
a decision to switch based on the value of the next bit. The state machine does not move from one
state to another while link pulses are being transmitted.
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Figure 3-6.
3.5.7.1.6
Cross-Over FunctionAuto Cross-Over
10/100 MB/s Mismatch Resolution
It is a common occurrence that a link partner (such as a switch) is configured for forced full-duplex
(FDX) 10/100 Mb/s operation. The normal auto-negotiation sequence would result in the other end
settling for half-duplex (HDX) 10/100 Mb/s operation. The mechanism described in this section resolves
the mismatch automatically and transitions the 82580EB/DB into FDX mode, enabling it to operate with
a partner configured for FDX operation.
The 82580EB/DB enables the system software device driver to detect the mismatch event previously
described and sets its duplex mode to the appropriate value without a need to go through another
auto-negotiation sequence or breaking link. Once software detects a possible mismatch, it might
instruct the 82580EB/DB to change its duplex setting to either HDX or FDX mode. Software sets the
Duplex_manual_set bit to indicate that duplex setting should be changed to the value indicated by the
Duplex Mode bit in PHY Register 0. Any change in the value of the Duplex Mode bit in PHY Register 0
while the Duplex_manual_set bit is set to 1b would also cause a change in the device duplex setting.
The Duplex_manual_set bit is cleared on all PHY resets, following auto-negotiation, and when the link
goes down. Software might track the change in duplex through the PHY Duplex Mode bit in Register 17
or a MAC indication.
3.5.7.1.7
Link Criteria
Once the link state is determined-via auto-negotiation, parallel detection or forced operation, the PHY
and its link partner bring up the link.
3.5.7.1.7.1
1000BASE-T
For 1000BASE-T links, the PHY and its link partner enter a training phase. They exchange idle symbols
and use the information gained to set their adaptive filter coefficients. These coefficients are used to
equalize the incoming signal, as well as eliminate signal impairments such as echo and cross talk.
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Either side indicates completion of the training phase to its link partner by changing the encoding of the
idle symbols it transmits. When both sides so indicate, the link is up. Each side continues sending idle
symbols each time it has no data to transmit. The link is maintained as long as valid idle, data, or
carrier extension symbols are received.
3.5.7.1.7.2
100BASE-TX
For 100BASE-TX links, the PHY and its link partner immediately begin transmitting idle symbols. Each
side continues sending idle symbols each time it has no data to transmit. The link is maintained as long
as valid idle symbols or data is received.
In 100 Mb/s mode, the PHY establishes a link each time the scrambler becomes locked and remains
locked for approximately 50 ms. Link remains up unless the descrambler receives less than 12
consecutive idle symbols in any 2 ms period. This provides for a very robust operation, essentially
filtering out any small noise hits that might otherwise disrupt the link.
3.5.7.1.7.3
10BASE-T
For 10BASE-T links, the PHY and its link partner begin exchanging Normal Link Pulses (NLPs). The PHY
transmits an NLP every 16 ms and expects to receive one every 10 to 20 ms. The link is maintained as
long as normal link pulses are received.
In 10 Mb/s mode, the PHY establishes link based on the link state machine found in 802.3, clause 14.
Note:
100 Mb/s idle patterns do not bring up a 10 Mb/s link.
3.5.7.2
Link Enhancements
The PHY offers two enhanced link functions, each of which are discussed in the sections that follow:
• SmartSpeed
• Flow control
3.5.7.2.1
SmartSpeed
SmartSpeed is an enhancement to auto-negotiation that enables the PHY to react intelligently to
network conditions that prohibit establishment of a 1000BASE-T link, such as cable problems. Such
problems might allow auto-negotiation to complete, but then inhibit completion of the training phase.
Normally, if a 1000BASE-T link fails, the PHY returns to the auto-negotiation state with the same speed
settings indefinitely. With SmartSpeed enabled by programming the PHCNFG.Automatic Speed
Downshift Mode field (See Section 7.24.2.19), after a configurable number of failed attempts, as
configured in the PHCTRL1 register (bits 12:10 - See Section 7.24.2.20) the PHY automatically
downgrades the highest ability it advertises to the next lower speed: from 1000 to 100 to 10 Mb/s.
Once a link is established, and if it is later broken, the PHY automatically upgrades the capabilities
advertised to the original setting. This enables the PHY to automatically recover once the cable plant is
repaired.
3.5.7.2.1.1
Using SmartSpeed
SmartSpeed is enabled by programming the PHCNFG.Automatic Speed Downshift Mode field (See
Section 7.24.2.19). When SmartSpeed downgrades the PHY advertised capabilities, it sets bit
PHINT.Automatic Speed Downshift (PHYREG.25.1 - See Section 7.24.2.22). When link is established,
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its speed is indicated in the PHSTAT.Speed Status field (PHYREG.26.9:8 - See Section 7.24.2.23).
SmartSpeed automatically resets the highest-level auto-negotiation abilities advertised, if link is
established and then lost.
The number of failed attempts allowed is configured in the PHCTRL1 register (bits 12:10 - See
Section 7.24.2.20).
Note:
SmartSpeed and M/S fault - When SmartSpeed is enabled, the M/S (Master-Slave) number
of Attempts Before Downshift is programmed to be less than 7, resolution is not given
seven attempts to try to resolve M/S status (see IEEE 802.3 clause 40.5.2).
Time To Link with Smart Speed - in most cases, any attempt duration is approximately 2.5
seconds, in other cases it could take more than 2.5 seconds depending on configuration and
other factors.
3.5.7.3
Flow Control
Flow control is a function that is described in Clause 31 of the IEEE 802.3 standard. It allows congested
nodes to pause traffic. Flow control is essentially a MAC-to-MAC function. MACs indicate their ability to
implement flow control during auto-negotiation. This ability is communicated through two bits in the
auto-negotiation registers (PHYREG.4.10 and PHYREG.4.11).
The PHY transparently supports MAC-to-MAC advertisement of flow control through its auto-negotiation
process. Prior to auto-negotiation, the MAC indicates its flow control capabilities via PHYREG.4.10
(Pause) and PHYREG.4.11 (ASM_DIR). After auto-negotiation, the link partner's flow control capabilities
are indicated in PHYREG.5.10 and PHYREG.5.11.
There are two forms of flow control that can be established via auto-negotiation: symmetric and
asymmetric. Symmetric flow control is for point-to-point links; asymmetric for hub-to-end-node
connections. Symmetric flow control enables either node to flow-control the other. Asymmetric flowcontrol enables a repeater or switch to flow-control a DTE, but not vice versa.
Table 3-39 lists the intended operation for the various settings of ASM_DIR and PAUSE. This
information is provided for reference only; it is the responsibility of the MAC to implement the correct
function. The PHY merely enables the two MACs to communicate their abilities to each other.
Table 3-39.
Pause And Asymmetric Pause Settings
ASM_DIR settings Local
(PHYREG.4.10) and Remote
(PHYREG.5.10)
Pause Setting Local
(PHYREG.4.9)
Pause Setting Remote
(PHYREG.5.9)
Result
Both ASM_DIR = 1b
1
1
Symmetric - Either side can flow control the other
1
0
Asymmetric - Remote can flow control local only
0
1
Asymmetric - Local can flow control remote
0
0
No flow control
1
1
Symmetric - Either side can flow control the other
Either or both ASM_DIR = 0b
Either or both = 0
3.5.7.4
No flow control
Management Data Interface
The PHY supports the IEEE 802.3 MII Management Interface also known as the Management Data
Input/Output (MDIO) Interface. This interface enables upper-layer devices to monitor and control the
state of the PHY. The MDIO interface consists of a physical connection, a specific protocol that runs
across the connection, and an internal set of addressable registers.
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The PHY supports the core 16-bit MDIO registers. Registers 0-10 and 15 are required and their
functions are specified by the IEEE 802.3 specification. Additional registers are included for expanded
functionality. Specific bits in the registers are referenced using an PHY REG X.Y notation, where X is the
register number (0-31) and Y is the bit number (0-15). See the software interface chapter (See
Section 7.24).
3.5.7.5
Internal PHY Low Power Operation and Power Management
The Internal PHY incorporates numerous features to maintain the lowest power possible.
The PHY can be entered into a low-power state according to MAC control (Power Management controls)
or via PHY Register 0. In either power down mode, the PHY is not capable of receiving or transmitting
packets.
3.5.7.5.1
Power Down via the PHY Register
The PHY can be powered down using the control bit found in PHYREG.0.11. This bit powers down a
significant portion of the port but clocks to the register section remain active. This enables the PHY
management interface to remain active during register power down. The power down bit is active high.
When the PHY exits software power-down (PHYREG.0.11 = 0b), it re-initializes all analog functions, but
retains its previous configuration settings.
3.5.7.5.2
Power Management State
The internal PHY is aware of the power management state. If the PHY is not in a power down state,
then PHY behavior regarding several features are different depending on the power state, see
Section 3.5.7.5.4.
3.5.7.5.3
Disable High Speed Power Saving Options
The 82580EB/DB supports disabling 1000 Mb/s or both 1000 Mb/s and 100 Mb/s advertisement by the
internal PHY regardless of the values programmed in the PHY ANA Register (address - 4d) and the PHY
GCON Register (address - 9d).
This is for cases where the system doesn't support working in 1000 Mb/s or 100 Mb/s due to power
limitations.
This option is enabled in the following PHPM register bits:
• PHPM.Disable 1000 in non-D0a - disable 1000 Mb/s when in non-D0a states only.
• PHPM.Disable 100 in non-D0a - disable 1000 Mb/s and 100 Mb/s when in non-D0a states only.
• PHPM.Disable 1000 - disable 1000 Mb/s always.
Note:
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When Value of PHPM.Disable 1000 bit is changed, PHY initiates Auto-negotiation without
direct driver command.
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3.5.7.5.4
Low Power Link Up - Link Speed Control
Normal Internal PHY speed negotiation drives to establish a link at the highest possible speed. The
82580EB/DB supports an additional mode of operation, where the PHY drives to establish a link at a low
speed. The link-up process enables a link to come up at the lowest possible speed in cases where power
is more important than performance. Different behavior is defined for the D0 state and the other nonD0 states.
Table 3-40 lists link speed as function of power management state, link speed control, and GbE speed
enabling:
Table 3-40.
Power
Management
State
Link Speed vs. Power State
Low
Power
Link Up
(PHPM.1,
PHPM.2)
0, Xb
D0a
1, Xb
Non-D0a
X, 0b
X, 1b
GbE Disable Bits
100M Disable
Bit
Disable 100
in non-D0a
(PHPM.9)
PHY Speed Negotiation
X
X
PHY negotiates to highest speed advertised
(normal operation).
1b
X
X
PHY negotiates to highest speed advertised
(normal operation), excluding 1000 Mb/s.
0b
X
X
PHY goes through Low Power Link Up (LPLU)
procedure, starting with advertised values.
1b
X
X
PHY goes through LPLU procedure, starting with
advertised values. Does not advertise 1000 Mb/s.
Disable 1000
(PHPM.6)
Disable 1000
in non-D0a
(PHPM.3)
0b
0b
0b
0b
PHY negotiates to highest speed advertised.
0b
1b
0b
PHY negotiates to highest speed advertised,
excluding 1000 Mb/s.
1b
X
0b
X
X
1b
PHY negotiates and advertises only 10 Mb/s
0b
0b
0b
PHY goes through LPLU procedure, starting at 10
Mb/s.
0b
1b
0b
PHY goes through LPLU procedure, starting at 10
Mb/s. Does not advertise 1000 Mb/s.
X
X
1b
PHY negotiates and advertises only 10 Mb/s
The Internal PHY initiates auto-negotiation without a direct driver command in the following cases:
• When the PHPM.Disable 1000 in non-D0a bit is set and 1000 Mb/s is disabled on D3 or Dr entry
(but not in D0a), the PHY auto-negotiates on entry.
• When the PHPM.Disable 100 in non-D0a is set and 1000 Mb/s and 100 Mb/s are disabled on D3 or
Dr entry (but not in D0a), the PHY auto-negotiates on entry.
• When PHPM.LPLU changes state with a change in a power management state. For example, on
transition from D0a without PHPM.LPLU to D3 with PHPM.LPLU. Or, on transition from D3 with
PHPM.LPLU to D0 without LPLU.
• On a transition from D0a state to a non-D0a state, or from a non-D0a state to D0a state, and
PHPM.LPLU is set.
Notes:
The Low-Power Link-Up (LPLU) feature previously described should be disabled (in both
D0a state and non-D0a states) when the intended advertisement is anything other than 10
Mb/s only, 10/100 Mb/s only, or 10/100/1000 Mb/s. This is to avoid reaching (through the
LPLU procedure) a link speed that is not advertised by the user.
When the LAN PCIe Function is disabled via the LAN_PCI_DIS bit in the Software Defined
Pins Control EEPROM word, the relevant Function is in a Non-D0a state. As a result
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Management might operate with reduced link speed if the LPLU, Disable 1000 in Non-D0a
or Disable 100 in Non-D0a EEPROM bits are set.
3.5.7.5.4.1
D0a State
A power-managed link speed control lowers link speed (and power) when highest link performance is
not required. When enabled (D0 Low Power Link Up mode), any link negotiation tries to establish a lowlink speed, starting with an initial advertisement defined by software.
The D0LPLU configuration bit enables D0 Low Power Link Up. Before enabling this feature, software
must advertise to one of the following speed combinations: 10 Mb/s only, 10/100 Mb/s only, or 10/100/
1000 Mb/s.
When speed negotiation starts, the PHY tries to negotiate at a speed based on the currently advertised
values. If link establishment fails, the PHY tries to negotiate with different speeds; it enables all speeds
up to the lowest speed supported by the partner. For example, PHY advertises 10 Mb/s only, and the
partner supports 1000 Mb/s only. After the first try fails, the PHY enables 10/100/1000 Mb/s and tries
again. The PHY continues to try and establish a link until it succeeds or until it is instructed otherwise.
In the second step (adjusting to partner speed), the PHY also enables parallel detect, if needed.
Automatic MDI/MDI-X resolution is done during the first auto-negotiation stage.
3.5.7.5.4.2
Non-D0a State
The PHY might negotiate to a low speed while in non-D0a states (Dr, D0u, D3). This applies only when
the link is required by one of the following: SMBus manageability, APM Wake, or PME. Otherwise, the
PHY is disabled during the non-D0 state.
The Low Power on Link-Up (Register PHPM.LPLU, is also loaded from EEPROM) bit enables reduction in
link speed:
• At power-up entry to Dr state, the PHY advertises supports for 10 Mb/s only and goes through the
link up process.
• At any entry to a non-D0a state (Dr, D0u, D3), the PHY advertises support for
10 Mb/s only and goes through the link up process.
• While in a non-D0 state, if auto-negotiation is required, the PHY advertises support for 10 Mb/s only
and goes through the link up process.
Link negotiation begins with the PHY trying to negotiate at 10 Mb/s speed only regardless of user autonegotiation advertisement. If link establishment fails, the PHY tries to negotiate at additional speeds; it
enables all speeds up to the lowest speed supported by the partner. For example, the PHY advertises 10
Mb/s only and the partner supports 1000 Mb/s only. After the first try fails, PHY enables 10/100/1000
Mb/s and tries again. The PHY continues to try and establish a link until it succeeds or until it is
instructed otherwise. In the second step (adjusting to partner speed), the PHY also enables parallel
detect, if needed. Automatic MDI/MDI-X resolution is done during the first auto-negotiation stage.
3.5.7.5.5
Internal PHY Smart Power-Down (SPD)
Smart power-down is a link-disconnect capability applicable to all power management states. Smart
Power-down combines a power saving mechanism with the fact that the link might disappear and
resume.
Smart power-down is enabled by PHPM.SPD_EN or by SPD Enable bit in the EEPROM if the following
conditions are met:
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1. Auto-negotiation is enabled.
2. PHY detects link loss.
While in the smart power-down state, the PHY powers down circuits and clocks that are not required for
detection of link activity. The PHY is still be able to detect link pulses (including parallel detect) and
wake-up to engage in link negotiation. The PHY does not send link pulses (NLP) while in SPD state;
however, register accesses are still possible.
When the Internal PHY is in smart power-down mode and detects link activity, it re-negotiates link
speed based on the power state and the Low Power Link Up bits as defined by the PHPM.D0LPLU and
PHPM.LPLU bits.
Note:
The PHY does not enter the SPD state unless auto-negotiation is enabled.
While in the SPD state, the PHY powers down all circuits not required for detection of link activity. The
PHY must still be able to detect link pulses (including parallel detect) and wake up to engage in link
negotiation. The PHY does not send link pulses (NLP) while in SPD state.
Notes:
While in the link-disconnect state, the PHY must allow software access to its registers.
The link-disconnect state applies to all power management states (Dr, D0u, D0a, D3).
The link might change status, that is go up or go down, while in any of these states.
3.5.7.5.5.1
Internal PHY Back-to-Back Smart Power-Down
While in link disconnect, the 82580EB/DB monitors the link for link pulses to identify when a link is reconnected. The 82580EB/DB also periodically transmits pulses (every 100 ms) to resolve the case of
two the 82580EB/DB devices (or devices with the 82580EB/DB-like behavior) connected to each other
across the link. Otherwise, two such devices might be locked in Smart power-down mode, not capable
of identifying that a link was re-connected.
Back-to-back smart power-down is enabled by the SPD_B2B_EN bit in the PHPM register. The default
value is enabled. The Enable bit applies to smart power-down mode.
Note:
3.5.7.5.6
This bit should not be altered by software once the 82580EB/DB was set in smart powerdown mode. If software requires changing the back-to-back status, it first needs to
transition the PHY out of smart power-down mode and only then change the back-to-back
bit to the required state.
Internal PHY Link Energy Detect
The 82580EB/DB asserts the Link Energy Detect bit (PHPM.Link Energy Detect) each time energy is not
detected on the link. This bit provides an indication of a cable becoming plugged or unplugged.
This bit is valid only if the PHPM.Go Link disconnect bit is set.
In order to correctly deduce that there is no energy, the bit must read 0b for three consecutive reads
each second.
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3.5.7.5.7
Internal PHY Power-Down State
The 82580EB/DB ports 0 to 3 enter a power-down state when none of the port’s clients are enabled and
therefore the internal PHY has no need to maintain a link. This can happen in one of the following
cases, if the Internal PHY power-down functionality is enabled through the EEPROM PHY Power Down
Enable bit.
1. D3/Dr state: Each Internal PHY enters a low-power state if the following conditions are met:
a.
The LAN function associated with this PHY is in a non-D0 state
b.
APM WOL is inactive
c.
Manageability doesn't use this port.
d.
ACPI PME is disabled for this port.
e.
The PHY Power Down Enable EEPROM bit is set (Initialization Control Word 2, word 0xF, bit 6).
2. SerDes mode: Each Internal PHY is disabled when its LAN function is configured to SerDes mode.
3. LAN disable: Each Internal PHY can be disabled if its LAN function's LAN Disable input indicates that
the relevant function should be disabled. Since the PHY is shared between the LAN function and
manageability, it might not be desirable to power down the PHY in LAN Disable. The
PHY_in_LAN_Disable EEPROM bit determines whether the PHY (and MAC) are powered down when
the LAN Disable pin is asserted. The default is not to power down.
A LAN port can also be disabled through EEPROM settings. If the LAN_DIS EEPROM bit is set, the
Internal PHY enters power down.
Note:
3.5.7.6
Setting the EEPROM LAN_PCI_DIS bit does not move the internal PHY into power down.
However if the LPLU, Disable 1000 in Non-D0a or the Disable 100 in Non-D0a EEPROM bits
are set Management may operate with reduced link speed since the Function is in a NonD0a (uninitialized) state.
Advanced Diagnostics
The 82580EB/DB Integrated PHY incorporates hardware support for advanced diagnostics.
The hardware support enables output of internal PHY data to host memory for post processing by the
software device driver.
The current diagnostics supported are:
3.5.7.6.1
TDR - Time Domain Reflectometry
By sending a pulse onto the twisted pair and observing the retuned signal, the following can be
deduced:
1. Is there a short?
2. Is there an open?
3. Is there an impedance mismatch?
4. What is the length to any of these faults?
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3.5.7.6.2
Channel Frequency Response
By doing analysis on the Tx and Rx data, it can be established that a channel’s frequency response
(also known as insertion loss) can determine if the channel is within specification limits. (Clause
40.7.2.1 in IEEE 802.3).
3.5.7.7
1000 Mb/s Operation
3.5.7.7.1
Introduction
Figure 3-7 shows an overview of 1000BASE-T functions, followed by discussion and review of the
internal functional blocks.
Figure 3-7.
1000BASE-T Functions Overview1000Base-T Functions
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3.5.7.7.2
Transmit Functions
This section describes functions used when the Media Access Controller (MAC) transmits data through
the PHY and out onto the twisted-pair connection.
3.5.7.7.2.1
Scrambler
The scrambler randomizes the transmitted data. The purpose of scrambling is twofold:
1. Scrambling eliminates repeating data patterns (also known as spectral lines) from the 4DPAM5
waveform in order to reduce EMI.
2. Each channel (A, B, C, D) has a unique signature that the receiver uses for identification.
The scrambler is driven by a 33-bit Linear Feedback Shift Register (LFSR), which is randomly loaded at
power up. The LFSR function used by the master differs from that used by the slave, giving each
direction its own unique signature. The LFSR, in turn, generates twelve mutually uncorrelated outputs.
Eight of these are used to randomize the inputs to the 4DPAM5 and Trellis encoders. The remaining four
outputs randomize the sign of the 4DPAM5 outputs.
3.5.7.7.2.2
Transmit FIFO
The transmit FIFO re-synchronizes data transmitted by the MAC to the transmit reference used by the
PHY. The FIFO is large enough to support a frequency differential of up to +/- 1000 ppm over a packet
size of 10 KB (jumbo frame).
3.5.7.7.2.3
Transmit Phase-Locked Loop PLL
This function generates the 125 MHz timing reference used by the PHY to transmit 4DPAM5 symbols.
When the PHY is the master side of the link, the XI input is the reference for the transmit PLL. When the
PHY is the slave side of the link, the recovered receive clock is the reference for the transmit PLL.
3.5.7.7.2.4
Trellis Encoder
The Trellis encoder uses the two high-order bits of data and its previous output to generate a ninth bit,
which determines if the next 4DPAM5 pattern should be even or odd.
For data, this function is:
Trellisn = Data7n-1 XOR Data6n-2 XOR Trellisn-3
This provides forward error correction and enhances the Signal-To-Noise (SNR) ratio by a factor of 6 dB.
3.5.7.7.2.5
4DPAM5 Encoder
The 4DPAM5 encoder translates 8-byte codes transmitted by the MAC into 4DPAM5 symbols. The
encoder operates at 125 MHz, which is both the frequency of the MAC interface and the baud rate used
by 1000BASE-T.
Each 8-byte code represents one of 28 or 256 data patterns. Each 4DPAM5 symbol consists of one of
five signal levels (-2,-1,0,1,2) on each of the four twisted pair (A,B,C,D) representing 54 or 625
possible patterns per baud period. Of these, 113 patterns are reserved for control codes, leaving 512
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patterns for data. These data patterns are divided into two groups of 256 even and 256 odd data
patterns. Thus, each 8-byte octet has two possible 4DPAM5 representations: one even and one odd
pattern.
3.5.7.7.2.6
Spectral Shaper
This function causes the 4DPAM5 waveform to have a spectral signature that is very close to that of the
MLT3 waveform used by 100BASE-TX. This enables 1000BASE-T to take advantage of infrastructure
(cables, magnetics) designed for 100BASE-TX.
The shaper works by transmitting 75% of a 4DPAM5 code in the current baud period, and adding the
remaining 25% into the next baud period.
3.5.7.7.2.7
Low-Pass Filter
To aid with EMI, this filter attenuates signal components more than 180 MHz. In 1000BASE-T, the
fundamental symbol rate is 125 MHz.
3.5.7.7.2.8
Line Driver
The line driver drives the 4DPAM5 waveforms onto the four twisted-pair channels (A, B, C, D), adding
them onto the waveforms that are simultaneously being received from the link partner.
Figure 3-8.
1000BASE-T Transmit Flow And Line Coding SchemePAM-5 Encoded Output
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Figure 3-9.
3.5.7.7.3
Transmit/Receive FlowPAM-5 Encoded Input
Receive Functions
This section describes function blocks that are used when the PHY receives data from the twisted pair
interface and passes it back to the MAC.
3.5.7.7.3.1
Hybrid
The hybrid subtracts the transmitted signal from the input signal, enabling the use of simple 100BASETX compatible magnetics.
3.5.7.7.3.2
Automatic Gain Control (AGC)
AGC normalizes the amplitude of the received signal, adjusting for the attenuation produced by the
cable.
3.5.7.7.3.3
Timing Recovery
This function re-generates a receive clock from the incoming data stream which is used to sample the
data. On the slave side of the link, this clock is also used to drive the transmitter.
3.5.7.7.3.4
Analog-to-Digital Converter (ADC)
The ADC function converts the incoming data stream from an analog waveform to digitized samples for
processing by the DSP core.
3.5.7.7.3.5
Digital Signal Processor (DSP)
DSP provides per-channel adaptive filtering, which eliminates various signal impairments including:
• Inter-symbol interference (equalization)
• Echo caused by impedance mismatch of the cable
• Near-end crosstalk (NEXT) between adjacent channels (A, B, C, D)
• Far-end crosstalk (FEXT)
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• Propagation delay variations between channels of up to 120 ns
• Extraneous tones that have been coupled into the receive path
The adaptive filter coefficients are initially set during the training phase. They are continuously adjusted
(adaptive equalization) during operation through the decision-feedback loop.
3.5.7.7.3.6
Descrambler
The descrambler identifies each channel by its characteristic signature, removing the signature and rerouting the channel internally. In this way, the receiver can correct for channel swaps and polarity
reversals. The descrambler uses the same base 33-bit LFSR used by the transmitter on the other side
of the link.
The descrambler automatically loads the seed value from the incoming stream of scrambled idle
symbols. The descrambler requires approximately 15 s to lock, normally accomplished during the
training phase.
3.5.7.7.3.7
Viterbi Decoder/Decision Feedback Equalizer (DFE)
The Viterbi decoder generates clean 4DPAM5 symbols from the output of the DSP. The decoder includes
a Trellis encoder identical to the one used by the transmitter. The Viterbi decoder simultaneously looks
at the received data over several baud periods. For each baud period, it predicts whether the symbol
received should be even or odd, and compares that to the actual symbol received. The 4DPAM5 code is
organized in such a way that a single level error on any channel changes an even code to an odd one
and vice versa. In this way, the Viterbi decoder can detect single-level coding errors, effectively
improving the signal-to-noise (SNR) ratio by a factor of 6 dB. When an error occurs, this information is
quickly fed back into the equalizer to prevent future errors.
3.5.7.7.3.8
4DPAM5 Decoder
The 4DPAM5 decoder generates 8-byte data from the output of the Viterbi decoder.
3.5.7.7.3.9
100 Mb/s Operation
The MAC passes data to the PHY over the MII. The PHY encodes and scrambles the data, then transmits
it using MLT-3 for 100TX over copper. The PHY de-scrambles and decodes MLT-3 data received from the
network. When the MAC is not actively transmitting data, the PHY sends out idle symbols on the line.
3.5.7.7.3.10
10 Mb/s Operation
The PHY operates as a standard 10 Mb/s transceiver. Data transmitted by the MAC as 4-bit nibbles is
serialized, Manchester-encoded, and transmitted on the MDI[0]+/- outputs. Received data is decoded,
de-serialized into 4-bit nibbles and passed to the MAC across the internal MII. The PHY supports all the
standard 10 Mb/s functions.
3.5.7.7.3.11
Link Test
In 10 Mb/s mode, the PHY always transmits link pulses. If link test function is enabled, it monitors the
connection for link pulses. Once it detects two to seven link pulses, data transmission are enabled and
remain enabled as long as the link pulses or data reception continues. If the link pulses stop, the data
transmission is disabled.
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If the link test function is disabled, the PHY might transmit packets regardless of detected link pulses.
Setting the Port Configuration register bit (PHYREG.16.14) can disable the link test function.
3.5.7.7.3.12
10Base-T Link Failure Criteria and Override
Link failure occurs if link test is enabled and link pulses stop being received. If this condition occurs, the
PHY returns to the auto-negotiation phase, if auto-negotiation is enabled. Setting the Port Configuration
register bit (PHYREG.16.14) disables the link integrity test function, then the PHY transmits packets,
regardless of link status.
3.5.7.7.3.13
Jabber
If the MAC begins a transmission that exceeds the jabber timer, the PHY disables the transmit and
loopback functions and asserts collision indication to the MAC. The PHY automatically exits jabber mode
after 250-750 ms. This function can be disabled by setting bit PHYREG.16.10 = 1b.
3.5.7.7.3.14
Polarity Correction
The PHY automatically detects and corrects for the condition where the receive signal (MDI_PLUS[0]/
MDI_MINUS[0]) is inverted. Reversed polarity is detected if eight inverted link pulses or four inverted
end-of-frame markers are received consecutively. If link pulses or data are not received for 96-130 ms,
the polarity state is reset to a non-inverted state.
Automatic polarity correction can be disabled by setting bit PHYREG.27.5.
3.5.7.7.3.15
Dribble Bits
The PHY handles dribble bits for all of its modes. If between one and four dribble bits are received, the
nibble is passed across the interface. The data passed across is padded with 1's if necessary. If
between five and seven dribble bits are received, the second nibble is not sent onto the internal MII bus
to the MAC. This ensures that dribble bits between 1-7 do not cause the MAC to discard the frame due
to a CRC error.
3.5.7.7.3.16
PHY Address
The External PHY MDIO Address is defined in the MDICNFG.PHYADD field and is loaded at power-up
from EEPROM. If the MDICNFG.Destination bit is cleared (Internal PHY), MDIO access is always to the
internal PHY.
3.5.8
Media Auto Sense
The 82580EB/DB provides a significant amount of flexibility in pairing a LAN device with a particular
type of media (such as copper or fiber-optic) as well as the specific transceiver/interface used to
communicate with the media. Each MAC, representing a distinct LAN device, can be coupled with an
internal copper PHY or SerDes/SGMII/1000BASE-KX interface independently. The link configuration
specified for each LAN device can be specified in the LINK_MODE field of the Extended Device Control
(CTRL_EXT) register and initialized from the EEPROM Initialization Control Word 3 associated with each
LAN Port.
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In some applications, software might need to be aware of the presence of a link on the media not
currently active. In order to supply such an indication, any of the 82580EB/DB ports can set the
AUTOSENSE_EN bit in the CONNSW register (address 0x0034) in order to enable sensing of the non
active media activity.
Note:
When in SerDes/SGMII/1000BASE-KX detect mode, software should define which indication
is used to detect the energy change on the SerDes/SGMII/1000BASE-KX media. It can be
either the external signal detect pin or the internal signal detect. This is done using the
CONNSW.ENRGSRC bit. The signal detect pin is normally used when connecting in SerDes
mode to optical media where the receive LED provide such an indication.
Software can then enable the OMED interrupt in ICR in order to get an indication on any detection of
energy in the non active media.
Note:
The auto-sense capability can be used in either port independent of the usage of the other
port.
The following sections describes the procedures that should be followed in order to enable the autosense mode
3.5.8.1
Auto sense setup
3.5.8.1.1
SerDes/SGMII/1000BASE-KX Detect Mode (PHY is Active)
1. Set CONNSW.ENRGSRC to determine the sources for the signal detect indication (1b = external
SIG_DET, 0b = internal SerDes electrical idle). The default of this bit is set by EEPROM.
2. Set CONNSW.AUTOSENSE_EN.
3. When link is detected on the SerDes/SGMII/1000BASE-KX media, the 82580EB/DB sets the
interrupt bit OMED in ICR and if enabled, issues an interrupt. The CONNSW.AUTOSENSE_EN bit is
cleared .
3.5.8.1.2
PHY Detect Mode (SerDes/SGMII/1000BASE-KX is active)
1. Set CONNSW.AUTOSENSE_CONF = 1b.
2. Reset the PHY as described in Section 4.3.2.5.
3. Enable PHY to move to low power mode when cable is disconnected by setting the PHPM.SPD_EN
bit.
4. Set CONNSW.AUTOSENSE_EN = 1b and then clear CONNSW.AUTOSENSE_CONF.
5. When signal is detected on the PHY media, the 82580EB/DB sets the ICR.OMED interrupt bit and
issues an interrupt if enabled.
6. The 82580EB/DB puts the PHY in power down mode.
According to the result of the interrupt, software can then decide to switch to the other media.
Note:
Assertion of ICR.OMED PHY is a one time event. To re-enable Auto-detect after cable is
unplugged Software should clear the CONNSW.AUTOSENSE_EN bit and the procedure
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defined above should be executed again.
3.5.8.2
Switching between medias.
The 82580EB/DB's link mode is controlled by the CTRL_EXT.LINK_MODE field. The default value for the
LINK_MODE setting is directly mapped from the EEPROM's initialization Control Word 3 Link Mode field.
Software can modify the LINK_MODE indication by writing the corresponding value into this register.
Note:
Before dynamically switching between medias, the software should ensure that the current
mode of operation is not in the process of transmitting or receiving data. This is achieved by
disabling the transmitter and receiver, waiting until the 82580EB/DB is in an idle state, and
then beginning the process for changing the link mode.
The mode switch in this method is only valid until the next hardware reset of the 82580EB/
DB. After a hardware reset, the link mode is restored to the default setting by the EEPROM.
To get a permanent change of the link mode, the default in the EEPROM should be changed.
The following procedures need to be followed to actually switch between the two modes.
3.5.8.2.1
Transition to SerDes/1000BASE-KX/SGMII Modes
1. Disable the receiver by clearing RCTL.RXEN.
2. Disable the transmitter by clearing TCTL.EN.
3. Verify the 82580EB/DB has stopped processing outstanding cycles and is idle.
4. Modify LINK mode to SerDes, 1000BASE-KX or SGMII by setting CTRL_EXT.LINK_MODE to 11b,
01b or 10b respectively.
5. Set up the link as described in Section 4.6.7.3,Section 4.6.7.4 or Section 4.6.7.5.
6. Set up Tx and Rx queues and enable Tx and Rx processes.
3.5.8.2.2
Transition to Internal PHY Mode
1. Disable the receiver by clearing RCTL.RXEN.
2. Disable the transmitter by clearing TCTL.EN.
3. Verify the 82580EB/DB has stopped processing outstanding cycles and is idle.
4. Modify LINK mode to PHY mode by setting CTRL_EXT.LINK_MODE to 00b.
5. Set link-up indication by setting CTRL.SLU.
6. Reset the PHY as described in Section 4.3.2.5.
7. Set up the link as described in Section 4.6.7.2.
8. Set up the Tx and Rx queues and enable the Tx and Rx processes.
§§
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4.0
Initialization
4.1
Power Up
4.1.1
Power-Up Sequence
Figure 4-1 shows the power-up sequence from power ramp up and to when the 82580EB/DB is ready to
accept host commands.
Figure 4-1.
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Note:
The Keep_PHY_Link_Up bit (Veto bit) is set by firmware when the BMC is running IDER or
SoL. Its purpose is to prevent interruption of these processes when power is being turned
on.
4.1.2
Power-Up Timing Diagram
Figure 4-2.
Power-Up Timing Diagram
Table 4-1.
Notes to Power-Up Timing Diagram
Note
1
Xosc is stable txog after the Power is stable
2
Internal Reset is released after all power supplies are good and tppg after Xosc is stable.
3
An NVM read starts on the rising edge of the internal Reset or LAN_PWR_GOOD.
4
After reading the NVM, PHY might exit power down mode.
5
APM Wakeup and/or manageability might be enabled based on NVM contents.
6
The PCIe reference clock is valid tPE_RST-CLK before the de-assertion of PE_RST# (according to PCIe spec).
7
PE_RST# is de-asserted tPVPGL after power is stable (according to PCIe spec).
8
De-assertion of PE_RST# causes the NVM to be re-read, asserts PHY power-down (except if veto bit also known as
Keep_PHY_Link_Up bit is set), and disables Wake Up.
9
After reading the NVM, PHY exits power-down mode.
10
Link training starts after tpgtrn from PE_RST# de-assertion.
11
A first PCIe configuration access might arrive after tpgcfg from PE_RST# de-assertion.
12
A first PCI configuration response can be sent after tpgres from PE_RST# de-assertion
13
Writing a 1 to the Memory Access Enable bit in the PCI Command Register transitions the device from D0u to D0 state.
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4.2
Reset Operation
4.2.1
Reset Sources
The 82580EB/DB reset sources are described below:
4.2.1.1
LAN_PWR_GOOD
The 82580EB/DB has an internal mechanism for sensing the power pins. Once the power is up and
stable, the 82580EB/DB creates an internal reset. This reset acts as a master reset of the entire chip. It
is level sensitive, and while it is zero holds all of the registers in reset. LAN_PWR_GOOD is interpreted
to be an indication that device power supplies are all stable. LAN_PWR_GOOD changes state during
system power-up.
4.2.1.2
PE_RST_N
The de-assertion of PE_RST_N indicates that both the power and the PCIe clock sources are stable. This
pin asserts an internal reset also after a D3cold exit. Most units are reset on the rising edge of
PE_RST_N. The only exception is the PCIe unit, which is kept in reset while PE_RST_N is asserted
(level).
4.2.1.3
In-Band PCIe Reset
The 82580EB/DB generates an internal reset in response to a Physical layer message from the PCIe or
when the PCIe link goes down (entry to Polling or Detect state). This reset is equivalent to PCI reset in
previous (PCI) gigabit LAN controllers.
4.2.1.4
D3hot to D0 Transition
This is also known as ACPI Reset. The 82580EB/DB generates an internal reset on the transition from
D3hot power state to D0 (caused after configuration writes from D3 to D0 power state). Note that this
reset is per function and resets only the function that transitions from D3hot to D0.
Note:
4.2.1.5
Software drivers should implement the handshake mechanism defined in Section 5.2.3.3 to
verify that all pending PCIe completions are done, before moving the 82580EB/DB to D3.
Function Level Reset (FLR)
A FLR reset to a function is issued, by setting bit 15 in the Device Control configuration register (see
Section 9.5.6.5), is equivalent to a D0  D3  D0 transition. The only difference is that this reset does
not require driver intervention in order to stop the master transactions of this function. This reset is per
function and resets only the function without effecting activity of other functions or Lan ports.
The EEPROM is partially reloaded after an FLR reset. The words read from EEPROM at FLR are the same
as read following a full software reset. A list of these words can be found in Section 3.3.1.3.
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A FLR reset to a function resets all the queues, interrupts, and statistics registers attached to the
function. It also resets PCIe R/W configuration bits as well as disables transmit and receive flows for the
queues allocated to the function. All pending read requests are dropped and PCIe read completions to
the function might be completed as unexpected completions and silently discarded (following update of
flow control credits) without logging or signaling as an error.
Note:
If software initiates a FLR when the Transactions Pending bit in the Device Status
configuration register is set to 1b (see Section 9.5.6.6), then software must not initialize
the function until allowing time for any associated completions to arrive. The Transactions
Pending bit is cleared upon completion of the FLR.
4.3
Software Reset
4.3.1
Port Software Reset (RST)
Software can reset a port in the 82580EB/DB by setting the Port Software Reset (CTRL.RST) in the
Device Control Register. The port software reset (CTRL.RST) is per function and resets only the function
that received the software reset. Following the reset the PCI configuration space (configuration and
mapping) of the device is unaffected. Prior to issuing software reset the driver needs to operate the
master disable algorithm as defined in Section 5.2.3.3.
The CTRL.RST bit is provided primarily to recover from an indeterminate or suspected Port hung
hardware state. Most registers (receive, transmit, interrupt, statistics, etc.) and state machines in the
port are set to their power-on reset values, approximating the state following a power-on or PCIe reset.
However, PCIe configuration registers and logic common to all ports is not reset, leaving the device
mapped into system memory space and accessible by a driver.
Note:
To ensure that software reset has fully completed and that the 82580EB/DB responds
correctly to subsequent accesses, the driver should wait at least 3 milliseconds after setting
CTRL.RST before attempting to check if the bit was cleared or before attempting to access
any other register.
When asserting the CTRL.RST software reset bit, only some EEPROM bits related to the specific function
are re-read (See Section 3.3.1.3). Bits re-read from EEPROM are reset to default values.
Fields controlled by the LED, SDP and Init3 words of the EEPROM are not reset and not re-read after a
software reset. For the list of words read from EEPROM at full software reset, see Section 3.3.1.3.
4.3.2
Device Software Reset (DEV_RST)
Software can reset all the 82580EB/DB ports by setting the Device Reset bit (CTRL.DEV_RST) in the
Device Control Register. The Device Reset (CTRL.DEV_RST) resets all functions and common logic. PCI
configuration space (configuration and mapping) of the device is unaffected.
Device Reset (CTRL.DEV_RST) can be used to globally reset the entire component, if the DEV_RST_EN
bit in Initialization Control 4 EEPROM word is set. This bit is provided as a last-ditch software
mechanism to recover from an indeterminate or suspected hardware hung state that could not be
resolved by setting the CTRL.RST bit. When setting CTRL.DEV_RST, most registers (receive, transmit,
interrupt, statistics, etc.) and state machines on ports are set to power-on reset values, approximating
the state following a power-on or PCI reset. However, PCIe configuration registers are not reset, leaving
the device mapped into system memory space and accessible by the drivers.
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When CTRL.DEV_RST is asserted by software on a LAN port, all LAN ports (including LAN ports that
didn’t initiate the reset) are placed in a reset state. To notify software device drivers on all ports that
CTRL.DEV_RST has been asserted, an interrupt is generated and the ICR.DRSTA bit is set on all ports
that didn’t initiate the Device reset. In addition the STATUS.DEV_RST_SET bit is set on all ports to
indicate that Device reset was asserted.
Prior to issuing Device reset the driver needs to:
1. Get ownership of the Device reset functionality by sending message via the mailbox mechanism
described in section Section 4.7.3 and receiving acknowledge message from other drivers.
2. Initiate the master disable algorithm as defined in Section 5.2.3.3.
Note:
To ensure that Device reset has fully completed and that the 82580EB/DB responds
correctly to subsequent accesses, wait at least 3 milliseconds after setting CTRL.DEV_RST
before attempting to check if the bit was cleared or before attempting to access any other
register.
Following Device Reset assertion or reception of Device Reset interrupt (ICR.DRSTA) software should
initiate the following steps to re-initialize the port:
1. Wait for the GCR.DEV_RST in progress bit to be cleared.
2. Read STATUS.DEV_RST_SET bit and clear bit by write 1.
3. Re-initialize the port.
4. Check STATUS.DEV_RST_SET bit and verify that bit is still 0. If bit is set, return to 1. and re-start
initialization process.
5. Driver that initiated the Device reset should release ownership of Device Reset and Mailbox using
the flow described in Section 4.7.3.
When setting the Device reset bit (CTRL.DEV_RST), EEPROM bits related to all ports are re-read (See
Section 3.3.1.3). Bits re-read from EEPROM are reset to default values.
Fields controlled by the LED, SDP and Init3 words of the EEPROM are not reset and not re-read after a
software reset. For the list of words read from EEPROM at full software reset, see Section 3.3.1.3.
4.3.2.1
BME (Bus Master Enable)
Disabling Bus Master activity of a function by clearing the Configuration Command register.BME bit to
0, resets all DMA activities and MSI/MSIx operations related to the port. The Master disable is per
function and resets only the DMA activities related to this function without effecting activity of other
functions or LAN ports. Configuration accesses and target accesses to the function are still enabled and
BMC can still transmit and receive packets on the port.
A Master Disable to a function resets all the queues and DMA related interrupts attached to this
function. It also disables the transmit and receive flows for the queues allocated to this function. All
pending read requests are dropped and PCIe read completions to this function might be completed as
unexpected completions and silently discarded (following update of flow control credits) without logging
or signaling it as an error.
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Note:
Prior to issuing a master disable the Driver needs to implement the master disable
algorithm as defined in Section 5.2.3.3. After Master Enable is set back to 1 driver should
re-initialize the transmit and receive queues.
4.3.2.2
Force TCO
This reset is generated when manageability logic is enabled and BMC detects that the 82580EB/DB
does not receive or transmit data correctly. Force TCO reset is enabled if the Reset on Force TCO bit in
the Management Control EEPROM word is set 1.
Force TCO reset is generated in pass through mode when BMC issues a Force TCO command with bit 1
set and the above conditions exist.
4.3.2.3
Firmware Reset
This reset is activated by writing a 1 to the FWR bit in the HOST Interface Control Register (HICR) in
CSR address 0x8F00.
4.3.2.4
EEPROM Reset
Writing a 1 to the EEPROM Reset bit of the Extended Device Control Register (CTRL_EXT.EE_RST)
causes the 82580EB/DB to re-read the per-function configuration from the EEPROM, setting the
appropriate bits in the registers loaded by the EEPROM.
4.3.2.5
PHY Reset
Software can write a 1 to the PHY Reset bit of the Device Control Register (CTRL.PHY_RST) to reset the
internal PHY. The PHY is internally configured after a PHY reset.
Note:
The internal PHY should not be reset using PHYREG 0 bit 15 (PCTRL.Reset), since in this
case the internal PHY configuration process is bypassed and there is no guarantee the PHY
will operate correctly.
As the PHY may be accessed by the internal firmware and the driver software, the driver software
should coordinate any PHY reset with the firmware using the following procedure:
1. Check that MANC.BLK_Phy_Rst_On_IDE (offset 0x5820 bit 18) is cleared. If it is set, the BMC
requires a stable link and thus the PHY should not be reset at this stage. The driver may skip the
PHY reset if not mandatory or wait for MANC.BLK_Phy_Rst_On_IDE to clear. See Section 4.3.4 for
more details.
2. Take ownership of the relevant PHY (on port 0,1,2 or 3) using the following flow:
a.
b.
Get ownership of the software/software semaphore SWSM.SMBI bit (offset 0x5B50 bit 0).
•
Read the SWSM register.
•
If SWSM.SMBI is read as zero, the semaphore was taken.
•
Otherwise, go back to step a.
•
This step assure that other software will not access the shared resources register
(SW_FW_SYNC).
Get ownership of the software/firmware semaphore SWSM.SWESMBI bit (offset 0x5B50 bit 1):
•
Set the SWSM.SWESMBI bit.
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c.
d.
•
Read SWSM.
•
If SWSM.SWESMBI was successfully set - the semaphore was acquired - otherwise, go back
to step a.
•
This step assure that the internal firmware will not access the shared resources register
(SW_FW_SYNC).
Software reads the Software-Firmware Synchronization Register (SW_FW_SYNC) and checks
both bits in the pair of bits that control the PHY it wishes to own.
•
If both bits are cleared (both firmware and other software does not own the PHY), software
sets the software bit in the pair of bits that control the resource it wishes to own.
•
If one of the bits is set (firmware or other software owns the PHY), software tries again
later.
Release ownership of the software/firmware semaphore by clearing the SWSM.SWESMBI bit.
3. Drive PHY reset bit in CTRL bit 31.
4. Wait 100 s.
5. Release PHY reset in CTRL bit 31.
6. Release ownership of the relevant PHY to the FW using the following flow:
a.
Get ownership of the software/firmware semaphore SWSM.SWESMBI (offset 0x5B50 bit 1):
•
Set the SWSM.SWESMBI bit.
•
Read SWSM.
•
If SWSM.SWESMBI was successfully set - the semaphore was acquired - otherwise, go back
to step a.
•
Clear the bit in SW_FW_SYNC that control the software ownership of the resource to
indicate this resource is free.
•
Release ownership of the software/firmware semaphore by clearing the SWSM.SWESMBI
bit.
7. Wait for the relevant CFG_DONE bit (EEMNGCTL.CFG_DONE0, EEMNGCTL.CFG_DONE1,
EEMNGCTL.CFG_DONE2 or EEMNGCTL.CFG_DONE3).
8. Take ownership of the relevant PHY using the following flow:
a.
b.
c.
Get ownership of the software/firmware semaphore SWSM.SWESMBI (offset 0x5B50 bit 1):
•
Set the SWSM.SWESMBI bit.
•
Read SWSM.
•
If SWSM.SWESMBI was successfully set - the semaphore was acquired - otherwise, go back
to step a.
•
This step assure that the internal firmware will not access the shared resources register
(SW_FW_SYNC).
Software reads the Software-Firmware Synchronization Register (SW_FW_SYNC) and checks
both bits in the pair of bits that control the PHY it wishes to own.
•
If both bits are cleared (both firmware and other software does not own the PHY), software
sets the software bit in the pair of bits that control the resource it wishes to own.
•
If one of the bits is set (firmware or other software owns the PHY), software tries again
later.
Release ownership of the software/software semaphore and the software/firmware semaphore
by clearing SWSM.SMBI and SWSM.SWESMBI bits.
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9. Configure the PHY.
10. Release ownership of the relevant PHY using the flow described in Section 4.7.2.
Note:
Software PHY ownership should not exceed 100 mS. If Software takes PHY ownership for a
longer duration, Firmware may implement a timeout mechanism and take ownership of the
PHY.
4.3.3
Reset Effects
The resets affect the following registers and logic:
Table 4-2.
82580EB/DB Reset Effects - Common Resets
LAN_PWR_G
OOD
PE_
RST_N
LTSSM (PCIe back to detect/
polling)
X
X
X
PCIe Link data path
X
X
X
Read EEPROM (Complete Load)
X
X
X
PCI Configuration Registers- non
sticky
X
X
X
3.
PCI Configuration Registers sticky
X
X
X
4.
PCIe local registers
X
X
X
5.
Data path
X
X
Reset Activation
Read EEPROM (Per Function)
SW CTRL.
DEV_RST
In-Band PCIe
Reset
FW
Reset
X
X
Notes
18.
X
On-die memories
X
X
X
X
MAC, PCS, Auto Negotiation and
other port related logic
X
X
X
X
15.
DMA
X
X
X
X
Functions queue enable
X
X
X
X
Function interrupt & statistics
registers
X
X
X
X
Wake Up (PM) Context
X
1.
Wake Up Control Register
X
8.
Wake Up Status Registers
X
9.
Manageability Control Registers
X
MMS Unit
X
7.
10.
X
Wake-Up Management Registers
X
X
X
X
3.,11.
Memory Configuration Registers
X
X
X
X
3.
EEPROM and flash request
X
PHY/SERDES PHY
X
X
X
Strapping Pins
X
X
X
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X
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Table 4-3.
82580EB/DB Reset Effects - Per Function Resets
Reset Activation
Read EEPROM (Per
Function)
D3hotD0
FLR
Port SW Reset
(CTRL.RST)
Force
TCO
EE
Reset
X
X
X
X
X
PHY
Reset
PCI Configuration
Registers RO
PCI Configuration
Registers MSI-X
Notes
3.
X
X
6.
PCI Configuration
Registers RW
PCIe local registers
5.
Data path
X
X
X
X
On-die memories
X
X
X
X
MAC, PCS, Auto
Negotiation and
other port related
logic
X
X
X
X
DMA
X
X
15.
17.
Wake Up (PM)
Context
7.
Wake Up Control
Register
8.
Wake Up Status
Registers
9.
Manageability
Control Registers
10.
Function queue
enable
X
X
X
X
Function interrupt &
statistics registers
X
X
X
Wake-Up
Management
Registers
X
X
X
X
3.,11.
Memory
Configuration
Registers
X
X
X
X
3.
EEPROM and flash
request
X
X
PHY/SERDES PHY
X
X
16.
X
X
2.
Strapping Pins
Notes:
1. If AUX_POWER = 0b the Wakeup Context is reset (PME_Status and PME_En bits should be 0b at
reset if the 82580EB/DB does not support PME from D3cold).
2. The MMS unit must configure the PHY after any PHY reset.
3. The following register fields do not follow the general rules above:
a.
“CTRL.SDP0_IODIR, CTRL.SDP1_IODIR, CTRL_EXT.SDP2_IODIR, CTRL_EXT.SDP3_IODIR,
CONNSW.ENRGSRC field, CTRL_EXT.SFP_Enable, CTRL_EXT.LINK_MODE, CTRL_EXT.EXT_VLAN
and LED configuration registers are reset on LAN_PWR_GOOD only. Any EEPROM read resets
these fields to the values in the EEPROM.
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b.
The Aux Power Detected bit in the PCIe Device Status register is reset on LAN_PWR_GOOD and
PE_RST_N (PCIe reset) assertion only.
c.
FLA - reset on LAN_PWR_GOODInternal Power only.
d.
The bits mentioned in the next note.
4. The following registers are part of this group:
a.
VPD registers
b.
Max payload size field in PCIe Capability Control register (offset 0xA8).
c.
Active State Link PM Control field, Common Clock Configuration field and Extended Synch field
in PCIe Capability Link Control register (Offset 0xB0).
d.
Read Completion Boundary in the PCIe Link Control register (Offset 0xB0).
5. The following registers are part of this group:
a.
SWSM
b.
GCR (only part of the bits - see register description for details)
c.
FUNCTAG
d.
GSCL_1/2/3/4
e.
GSCN_0/1/2/3
f.
SW_FW_SYNC - only part of the bits - see register description for details.
6. The following registers are part of this group:
a.
MSIX control register, MSIX PBA and MSIX per vector mask.
7. The Wake Up Context is defined in the PCI Bus Power Management Interface Specification (Sticky
bits). It includes:
— PME_En bit of the Power Management Control/Status Register (PMCSR).
— PME_Status bit of the Power Management Control/Status Register (PMCSR).
— Aux_En in the PCIe registers
— The device Requester ID (since it is required for the PM_PME TLP).
The shadow copies of these bits in the Wakeup Control Register are treated identically.
8. Refers to bits in the Wake Up Control Register that are not part of the Wake-Up Context (the
PME_En and PME_Status bits).
9. The Wake Up Status Registers include the following:
a.
Wake Up Status Register
b.
Wake Up Packet Length.
c.
Wake Up Packet Memory.
10. The manageability control registers refer to the following registers:
a.
MANC 0x5820
b.
MFUTP0-7 0x5030 - 0x504C
c.
MNGONLY 0x5864
d.
MAVTV0-7 0x5010 - 0x502C
e.
MDEF0-7 0x5890 - 0x58AC
f.
MDEF_EXT 0x5930 - 0x594C
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g.
METF0-3 0x5060 - 0x506C
h.
MIPAF0-15 0x58B0 - 0x58EC
i.
MMAH/MMAL0-1 0x5910 - 0x591C
j.
FWSM
11. The Wake-up Management Registers include the following:
a.
Wake Up Filter Control
b.
IP Address Valid
c.
IPv4 Address Table
d.
IPv6 Address Table
e.
Flexible Filter Length Table
f.
Flexible Filter Mask Table
12. The Other Configuration Registers include:
a.
General Registers
b.
Interrupt Registers
c.
Receive Registers
d.
Transmit Registers
e.
Statistics Registers
f.
Diagnostic Registers
Of these registers, MTA[n], VFTA[n], WUPM[n], FTFT[n], FHFT[n], FHFT_EXT[n], TDBAH/TDBAL, and
RDBAH/RDVAL registers have no default value. If the functions associated with the registers are
enabled they must be programmed by software. Once programmed, their value is preserved through all
resets as long as power is applied to the 82580EB/DB.
Note:
In situations where the device is reset using the software reset CTRL.RST or CTRL.DEV_RST
the transmit data lines are forced to all zeros. This causes a substantial number of symbol
errors to be detected by the link partner. In TBI mode, if the duration is long enough, the
link partner might restart the Auto-Negotiation process by sending “break-link” (/C/ codes
with the configuration register value set to all zeros).
13. These registers include:
a.
MSI/MSI-X enable bits
b.
BME
c.
Error indications
14. These registers include:
a.
RXDCTL.Enable
15. The contents of the following memories are cleared to support the requirements of PCIe FLR:
a.
The Tx packet buffers
b.
The Rx packet buffers
16. Includes EEC.REQ, EEC.GNT, FLA.REQ and FLA.GNT fields.
17. The following DMA Registers are cleared only by LAN_PWR_GOOD, PCIe Reset or CTRL.DEV_RST:
DMCTLX, DTPARS, DRPARS and DDPARS.
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18. CTRL.DEV_RST assertion causes read of function related sections for all ports
4.3.4
PHY Behavior During a Manageability Session
During some manageability sessions (e.g. an IDER or SoL session as initiated by an external BMC), the
platform is reset so that it boots from a remote media. This reset must not cause the Ethernet link to
drop since the manageability session is lost. Also, the Ethernet link should be kept on continuously
during the session for the same reasons. The 82580EB/DB therefore limits the cases in which the
internal PHY would restart the link, by masking two types of events from the internal PHY:
• PE_RST# and PCIe resets (in-band and link drop) do not reset the PHY during such a manageability
session
• The PHY does not change link speed as a result of a change in power management state, to avoid
link loss. For example, the transition to D3hot state is not propagated to the PHY.
— Note however that if main power is removed, the PHY is allowed to react to the change in power
state (i.e., the PHY might respond in link speed change). The motivation for this exception is to
reduce power when operating on auxiliary power by reducing link speed.
The capability described in this section is disabled by default on LAN Power Good reset. The
Keep_PHY_Link_Up_En bit in the EEPROM must be set to '1' to enable it. Once enabled, the feature is
enabled until the next LAN Power Good (i.e., the 82580EB/DB does not revert to the hardware default
value on PE_RST#, PCIe reset or any other reset but LAN Power Good).
When the Keep_PHY_Link_Up bit (also known as “veto bit”) in the MANC Register is set, the following
behaviors are disabled:
• The PHY is not reset on PE_RST# and PCIe resets (in-band and link drop). Other reset events are
not affected - LAN Power Good reset, Device Disable, Force TCO, and PHY reset by software.
• The PHY does not change its power state. As a result link speed does not change.
• The 82580EB/DB does not initiate configuration of the PHY to avoid losing link.
The keep_PHY_link_up bit is set by the BMC through the Management Control command (See
Section 11.3.2.1.5 for SMBus command and Section 11.3.1.6.1 for NC-SI command) on the sideband
interface. It is cleared by the external BMC (again, through a command on the sideband interface)
when the manageability session ends. Once the keep_PHY_link_up bit is cleared, the PHY updates its
Dx state and acts accordingly (e.g. negotiates its speed).
The Keep_PHY_Link_Up bit is also cleared on de-assertion of the MAIN_PWR_OK input pin.
MAIN_PWR_OK must be de-asserted at least 1 msec before power drops below its 90% value. This
allows enough time to respond before auxiliary power takes over.
The Keep_PHY_Link_Up bit is a R/W bit and can be accessed by host software, but software is not
expected to clear the bit. The bit is cleared in the following cases:
• On LAN Power Good
• When the BMC resets or initializes it
• On de-assertion of the MAIN_PWR_OK input pin. The BMC should set the bit again if it wishes to
maintain speed on exit from Dr state.
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4.4
Function Disable
4.4.1
General
For a LOM (Lan on Motherboard) design, it might be desirable for the system to provide BIOS-setup
capability for selectively enabling or disabling LAN functions. It allows the end-user more control over
system resource-management and avoid conflicts with add-in NIC solutions. The 82580EB/DB provides
support for selectively enabling or disabling one or more LAN device(s) in the system.
4.4.2
Overview
Device presence (or non-presence) must be established early during BIOS execution, in order to ensure
that BIOS resource-allocation (of interrupts, of memory or IO regions) is done according to devices that
are present only. This is frequently accomplished using a BIOS CVDR (Configuration Values Driven on
Reset) mechanism. The 82580EB/DB LAN-disable mechanism is implemented in order to be compatible
with such a solution.
The 82580EB/DB provides two mechanisms to disable its LAN ports:
• Four pins (LANx_DIS_N, one per LAN port) are sampled on reset to determine the LAN-enable
configuration
• All LAN ports except the first (LAN Port 0) might be disabled using EEPROM configuration, to avoid
case were all LAN ports are disabled in the EEPROM and the EEPROM can’t be accessed.
— The LAN ports can be disabled by setting to 1 either the LAN_DIS or the LAN PCI Disable bit in
the Software Defined Pins Control EEPROM word.
Disabling a LAN port affects the PCIe function it resides on. When function 0 is disabled (either LAN0 or
LAN3), two different behaviors are possible:
• Dummy Function mode — In some system, it is required to keep all the functions at their respective
location, even when other functions are disabled. In Dummy Function mode, if function #0 (either
LAN0 or LAN3) is disabled, then it does not disappear from the PCIe configuration space. Rather,
the function presents itself as a dummy function. The device ID and class code of this function
changes to other values (dummy function Device ID 0x10A6, Class Code 0xFF0000). In addition,
the function does not require any memory or I/O space, and does not require an interrupt line.
• Legacy mode - when function 0 is disabled, then the port residing on the next existing function
moves to reside on function 0. All other ports keeps their respective locations.
The disabled LAN port is still available for manageability purposes if it was disabled using the
LAN_PCI_DIS bit of the Software Defined Pins Control word in the EEPROM or if it was disabled through
the pin mechanism and the PHY_in_LAN_Disable bit in the Software Defined Pins Control word in the
EEPROM is cleared.
Mapping between function and LAN ports as a function of the LAN0_DIS_N, LAN1_DIS_N, LAN2_DIS_N
and LAN3_DIS_N pins and the FACTPS.LAN Function Sel bit is summarized in the following tables.
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Note:
PCIe Functions Mapping of dual port SKU is like 4 port SKU with Port 2 and Port 3 disabled.
Table 4-4.
PCI Functions Mapping (Legacy Mode)
Configuration Options:
LAN Port 0
enabled
LAN Port1
enabled
LAN Port2
enabled
LAN Port 3
enabled
PCIe Function to LAN Port Mapping
FACTPS.LAN
Function Sel
PCIe
Function 0
PCIe
Function 1
PCIe
Function 2
PCIe
Function 3
LAN Port 2 and 3 are
never enabled in
82580DB SKU
Yes
Yes
Yes
Yes
0
LAN Port 0
LAN Port 1
LAN Port 2
LAN Port 3
Yes
Yes
Yes
No
0
LAN Port 0
LAN Port 1
LAN Port 2
Disabled
Yes
Yes
No
Yes
0
LAN Port 0
LAN Port 1
Disabled
LAN Port 3
Yes
Yes
No
No
0
LAN Port 0
LAN Port 1
Disabled
Disabled
Yes
No
Yes
Yes
0
LAN Port 0
Disabled
LAN Port 2
LAN Port 3
Yes
No
Yes
No
0
LAN Port 0
Disabled
LAN Port 2
Disabled
Yes
No
No
Yes
0
LAN Port 0
Disabled
Disabled
LAN Port 3
Yes
No
No
No
0
LAN Port 0
Disabled
Disabled
Disabled
No
Yes
Yes
Yes
0
LAN Port 1
Disabled
LAN Port 2
LAN Port 3
No
Yes
Yes
No
0
LAN Port 1
Disabled
LAN Port 2
Disabled
No
Yes
No
Yes
0
LAN Port 1
Disabled
Disabled
LAN Port 3
No
Yes
No
No
0
LAN Port 1
Disabled
Disabled
Disabled
No
No
Yes
Yes
0
LAN Port 2
Disabled
Disabled
LAN Port 3
No
No
Yes
No
0
LAN Port 2
Disabled
Disabled
Disabled
No
No
No
Yes
0
LAN Port 3
Disabled
Disabled
Disabled
Yes
Yes
Yes
Yes
1
LAN Port 3
LAN Port 2
LAN Port 1
LAN Port 0
Yes
Yes
No
Yes
1
LAN Port 3
Disabled
LAN Port 1
LAN Port 0
Yes
No
Yes
Yes
1
LAN Port 3
LAN Port 2
Disabled
LAN Port 0
Yes
No
No
Yes
1
LAN Port 3
Disabled
Disabled
LAN Port 0
No
Yes
Yes
Yes
1
LAN Port 3
LAN Port 2
LAN Port 1
Disabled
No
Yes
No
Yes
1
LAN Port 3
Disabled
LAN Port 1
Disabled
No
No
No
Yes
1
LAN Port 3
Disabled
Disabled
Disabled
Yes
Yes
Yes
No
1
LAN Port 2
Disabled
LAN Port 1
LAN Port 0
Yes
No
Yes
No
1
LAN Port 2
Disabled
Disabled
LAN Port 0
No
Yes
Yes
No
1
LAN Port 2
Disabled
LAN Port 1
Disabled
No
No
Yes
No
1
LAN Port 2
Disabled
Disabled
Disabled
Yes
Yes
No
No
1
LAN Port 1
Disabled
Disabled
LAN Port 0
No
Yes
No
No
1
LAN Port 1
Disabled
Disabled
Disabled
Yes
No
No
No
1
LAN Port 0
Disabled
Disabled
Disabled
No
No
No
No
0 or 1
All PCI functions are disabled. Device is in low power mode
unless used by manageability
The following EEPROM bits control Function Disable:
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• PCI functions 1 to 3 can be enabled or disabled according to the EEPROM “LAN PCIe Function
Disable” bit in the Software Defined Pins Control EEPROM word.
Note:
PCI function 0 can not be disabled via EEPROM.
• The LAN Disable EEPROM bit in the Software Defined Pins Control EEPROM word, indicates which
function and LAN port are disabled. When this bit is set port is not available to manageability
channel.
• The LAN Function Sel EEPROM bit in the Functions Control EEPROM word, defines the
correspondence between LAN Port and PCI function
• The Dummy Function Enable EEPROM bit enables the Dummy Function mode for function 0. Default
value is disabled.
• The PHY_in_LAN_disable EEPROM bit in the Software Defined Pins Control EEPROM word, controls
the availability of the disabled function to manageability channel.
When a particular LAN is fully disabled, all internal clocks to that LAN are disabled, the device is held in
reset, and the internal PHY for that LAN is powered-down. In both modes, the device does not respond
to PCI configuration cycles. Effectively, the LAN device becomes invisible to the system from both a
configuration and power-consumption standpoint.
4.4.3
Control Options
The functions have a separate enabling Mechanism. Any function that is not enabled does not function
and does not expose its PCI configuration registers.
Table 4-5.
Strapping for Control Options
Function
Control Options
LAN 0
Strapping Option + EEPROM offset 0x20 bit 13 (full/PCI only disable in case of strap)
LAN 1
Strapping Option + EEPROM offset 0x20 bit 13 (full/PCI only disable in case of strap)/ EEPROM offset 0x20
bit 11 (full disable) / EEPROM offset 0x20 bit 10 (PCI only disable)
LAN 2
Strapping Option + EEPROM offset 0x20 bit 13 (full/PCI only disable in case of strap)/ EEPROM offset 0x20
bit 11 (full disable) / EEPROM offset 0x20 bit 10 (PCI only disable)
LAN 3
Strapping Option + EEPROM offset 0x20 bit 13 (full/PCI only disable in case of strap)/ EEPROM offset 0x20
bit 11 (full disable) / EEPROM offset 0x20 bit 10 (PCI only disable)
The 82580EB/DB strapping option for LAN Disable feature are:
Table 4-6.
Symbol
LAN0_DIS_N
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Strapping for LAN Disable
Ball #
F14
Name and Function
This pin is a strapping option pin always active. This pin has an internal weak pull-up resistor. In
case this pin is not connected or driven hi during init time, LAN 0 is enabled. In case this pin is
driven low during init time, LAN 0 is disabled. This pin is also used for testing and scan. When
used for testing or scan, the LAN disable functionality is not active.
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Table 4-6.
Symbol
Strapping for LAN Disable
Ball #
Name and Function
LAN1_DIS_N
E14
This pin is a strapping option pin always active. This pin has an internal weak pull-up resistor. In
case this pin is not connected or driven hi during init time, LAN 1 is enabled. In case this pin is
driven low during init time, LAN 1 function is disabled. This pin is also used for testing and scan.
When used for testing or scan, the LAN disable functionality is not active.
LAN2_DIS_N
D14
This pin is a strapping option pin always active. This pin has an internal weak pull-up resistor. In
case this pin is not connected or driven hi during init time, LAN 2 is enabled. In case this pin is
driven low during init time, LAN 2 is disabled. This pin is also used for testing and scan. When
used for testing or scan, the LAN disable functionality is not active.
LAN3_DIS_N
C14
This pin is a strapping option pin always active. This pin has an internal weak pull-up resistor. In
case this pin is not connected or driven hi during init time, LAN 3 is enabled. In case this pin is
driven low during init time, LAN 3 is disabled. This pin is also used for testing and scan. When
used for testing or scan, the LAN disable functionality is not active.
4.4.4
Event Flow for Enable/Disable Functions
This section describes the driving levels and event sequence for device functionality. Following a Power
on Reset / LAN_PWR_GOOD / PE_RST_N/ In-Band reset the LANx_DIS_N signals should be driven hi
(or left unconnected) for nominal operation. If any of the LAN functions are not required statically its
associated Disable strapping pin can be tied statically to low.
Case A - BIOS Disables the LAN Function at boot time by using strapping:
1. Assume that following power up sequence LANx_DIS_N signals are driven high.
2. The PCIe link is established following the PE_RST_N.
3. BIOS recognizes that a LAN function in the 82580EB/DB should be disabled.
4. The BIOS drives the LANx_DIS_N signal to low level.
5. The BIOS should assert the PCIe reset, either in-band or via PE_RST_N.
6. As a result, the 82580EB/DB samples the LANx_DIS_N signals and disables the LAN function and
issues an internal reset to this function.
7. BIOS might start with the Device enumeration procedure (the disabled LAN function is invisible or
changed to dummy function).
8. Proceed with Nominal operation.
9. Re-enable could be done by driving the LANx_DIS_N signal high and then request the user to issue
a warm boot that generate bus enumeration.
4.4.4.1
Multi-Function Advertisement
If all but one of the LAN devices are disabled, the 82580EB/DB is no longer a multi-function device. The
82580EB/DB normally reports a 0x80 in the PCI Configuration Header field Header Type, indicating
multi-function capability. However, if only a single LAN is enabled, the 82580EB/DB reports a 0x0 in this
field to signify single-function capability.
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4.4.4.2
Legacy Interrupts Utilization
When more than one LAN device is enabled, the 82580EB/DB can utilize the INTA# to INTC# interrupts
for interrupt reporting. The EEPROM Initialization Control Word 3 (bits 12:11) associated with each LAN
device controls which of these interrupts are used for each LAN device. The specific interrupt pin
utilized is reported in the PCI Configuration Header Interrupt Pin field associated with each LAN device.
However, if only one LAN device is enabled, then the INTA# must be used for this LAN device,
regardless of the EEPROM configuration. Under these circumstances, the Interrupt Pin field of the PCI
Header always reports a value of 0x1, indicating INTA# usage.
4.4.4.3
Power Reporting
When more than one LAN function is enabled, the PCI Power Management Register Block has the
capability of reporting a “Common Power” value. The Common Power value is reflected in the Data field
of the PCI Power Management registers. The value reported as Common Power is specified via the LAN
Power Consumption EEPROM word (word 0x22), and is reflected in the Data field whenever the
Data_Select field has a value of 0x8 (0x8 = Common Power Value Select).
When only one LAN is enabled, the 82580EB/DB appears as a single-function device, the Common
Power value, if selected, reports 0x0 (undefined value), as Common Power is undefined for a singlefunction device.
4.5
Device Disable
For a LOM design, it might be desirable for the system to provide BIOS-setup capability for selectively
enabling or disabling LOM devices. This might allow the end-user more control over system resourcemanagement; avoid conflicts with add-in NIC solutions, etc. The 82580EB/DB provides support for
selectively enabling or disabling it.
Note:
If the 82580EB/DB is configured to provide a 50MHz NC-SI clock (via the NC-SI Output
Clock EEPROM bit), then the device should not be disabled.
Device Disable is initiated by assertion of the asynchronous DEV_OFF_N pin. The DEV_OFF_N pin
should always be connected to enable correct device operation.
The EEPROM Power Down Enable bit (see Section 6.2.19) enables device disable mode (Hardware
default is that this mode is disabled).
While in device disable mode, the PCIe link is in L3 state. The PHY is in power down mode. Output
buffers are tri-stated.
Note:
Behavior of SDP pins in device disable mode is controlled by the SDP_IDDQ_EN EEPROM bit
(See Section 6.2.2).
Assertion or deassertion of PCIe PE_RST_N does not have any effect while the device is in device
disable mode (i.e., the device stays in the respective mode as long as DEV_OFF_N is asserted).
However, the device might momentarily exit the device disable mode from the time PCIe PE_RST_N is
de-asserted again and until the EEPROM is read.
During power-up, the DEV_OFF_N pin is ignored until the EEPROM is read. From that point, the device
might enter Device Disable if DEV_OFF_N is asserted.
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Note:
De-assertion of the DEV_OFF_N pin causes a fundamental reset to the 82580EB/DB.
Note to system designer: The DEV_OFF_N pin should maintain its state during system reset and system
sleep states. It should also insure the proper default value on system power-up. For example, one could
use a GPIO pin that defaults to '1' (enable) and is on system suspend power (i.e., it maintains state in
S0-S5 ACPI states).
4.5.1
BIOS Handling of Device Disable
1. Assume that following power up sequence the DEV_OFF_N signal is driven high (else it is already
disabled).
2. The PCIe is established following the PE_RST_N.
3. BIOS recognize that the whole Device should be disabled.
4. The BIOS drive the DEV_OFF_N signal to the low level.
5. As a result, the 82580EB/DB samples the DEV_OFF_N signal and enters the device disable mode.
6. The BIOS places the Link in the Electrical IDLE state (at the other end of the PCIe link) by clearing
the LINK Disable bit in the Link Control Register.
7. BIOS might start with the Device enumeration procedure (all of the Device functions are invisible).
8. Proceed with Nominal operation.
9. Re-enable could be done by driving the DEV_OFF_N signal high followed later by bus enumeration.
4.6
Software Initialization and Diagnostics
4.6.1
Introduction
This chapter discusses general software notes for the 82580EB/DB, especially initialization steps. This
includes general hardware, power-up state, basic device configuration, initialization of transmit and
receive operation, link configuration, software reset capability, statistics, and diagnostic hints.
4.6.2
Power Up State
When the 82580EB/DB powers up it reads the EEPROM. The EEPROM contains sufficient information to
bring the link up and configure the 82580EB/DB for manageability and/or APM wakeup. However,
software initialization is required for normal operation.
The power-up sequence, as well as transitions between power states, are described in section 4.1.1.
The detailed timing is given in Section 5.5. The next section gives more details on configuration
requirements.
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4.6.3
Initialization Sequence
The following sequence of commands is typically issued to the device by the software device driver in
order to initialize the 82580EB/DB to normal operation. The major initialization steps are:
• Disable Interrupts - see Interrupts during initialization.
• Issue Global Reset and perform General Configuration - see Global Reset and General
Configuration.
• Setup the PHY and the link - see Link Setup Mechanisms and Control/Status Bit Summary.
• Initialize all statistical counters - see Initialization of Statistics.
• Initialize Receive - see Receive Initialization.
• Initialize Transmit - see Transmit Initialization.
• Enable Interrupts - see Interrupts during initialization.
4.6.4
Interrupts During Initialization
• Most drivers disable interrupts during initialization to prevent re-entering the interrupt routine.
Interrupts are disabled by writing to the EIMC (Extended Interrupt Mask Clear) register. Note that
the interrupts need to be disabled also after issuing a global reset, so a typical driver initialization
flow is:
• Disable interrupts
• Issue a Global Reset
• Disable interrupts (again)
After the initialization is done, a typical driver enables the desired interrupts by writing to the EIMS
(Extended Interrupt Mask Set) register.
4.6.5
Global Reset and General Configuration
Device initialization typically starts with a global reset that places the device into a known state and
enables the device driver to continue the initialization sequence.
Several values in the Device Control Register (CTRL) need to be set, upon power up, or after a device
reset for normal operation.
• FD bit should be set per interface negotiation (if done in software), or is set by the hardware if the
interface is Auto-Negotiating. This is reflected in the Device Status Register in the Auto-Negotiation
case.
• Speed is determined via Auto-Negotiation by the PHY, Auto-Negotiation by the PCS layer in SGMII/
SerDes mode, or forced by software if the link is forced. Status information for speed is also
readable in the STATUS register.
• ILOS bit should normally be set to 0.
4.6.6
Flow Control Setup
If flow control is enabled, program the FCRTL0, FCRTH0, FCTTV and FCRTV registers. In order to avoid
packet losses, FCRTH should be set to a value equal to at least two max size packet below the receive
buffer size. E.g. Assuming a packet buffer size of 32 KB and expected max size packet of 9.5K, the
FCRTH0 value should be set to 32 - 2 * 9.5 = 17KB i.e. FCRTH0.RTH should be set to 0x440.
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If DMA Coalescing is enabled, to avoid packet loss, the FCRTC.RTH_Coal field should also be
programmed to a value equal to at least a single max packet size below the receive buffer size (i.e. a
value equal or less than FCRTH0.RTH + max size packet).
4.6.7
Link Setup Mechanisms and Control/Status Bit Summary
The CTRL_EXT.LINK_MODE value should be set to the desired mode prior to the setting of the other
fields in the link setup procedures.
4.6.7.1
PHY Initialization
Refer to the PHY documentation for the initialization and link setup steps. The device driver uses the
MDIC register to initialize the PHY and setup the link. Section 3.5.4.4 describes the link setup for the
internal copper PHY. Section 3.5.2.2 Section describes the usage of the MDIC register.
4.6.7.2
MAC/PHY Link Setup (CTRL_EXT.LINK_MODE = 00b)
This section summarizes the various means of establishing proper MAC/PHY link setups, differences in
MAC CTRL register settings for each mechanism, and the relevant MAC status bits. The methods are
ordered in terms of preference (the first mechanism being the most preferred).
4.6.7.2.1
MAC Settings Automatically Based on Duplex and Speed Resolved
by PHY
(CTRL.FRCDPLX = 0b, CTRL.FRCSPD = 0b,)
CTRL.FD
Don't care; duplex setting is established from PHY's internal indication to the MAC
(FDX) after PHY has auto-negotiated a successful link-up.
CTRL.SLU
Must be set to 1 by software to enable communications between MAC and PHY.
CTRL.RFCE
Must be set by software after reading capabilities from PHY registers and resolving
the desired setting.
CTRL.TFCE
Must be set by software after reading capabilities from PHY registers and resolving
the desired setting.
CTRL.SPEED
Don't care; speed setting is established from PHY's internal indication to the MAC
(SPD_IND) after PHY has auto-negotiated a successful link-up.
STATUS.FD
Reflects the actual duplex setting (FDX) negotiated by the PHY and indicated to MAC.
STATUS.LU
Reflects link indication (LINK) from PHY qualified with CTRL.SLU (set to 1).
STATUS.SPEED
Reflects actual speed setting negotiated by the PHY and indicated to the MAC
(SPD_IND).
4.6.7.2.2
MAC Duplex and Speed Settings Forced by Software Based on
Resolution of PHY (CTRL.FRCDPLX = 1b, CTRL.FRCSPD = 1b)
CTRL.FD
Set by software based on reading PHY status register after PHY has auto-negotiated
a successful link-up.
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CTRL.SLU
Must be set to 1 by software to enable communications between MAC and PHY.
CTRL.RFCE
Must be set by software after reading capabilities from PHY registers and resolving
the desired setting.
CTRL.TFCE
Must be set by software after reading capabilities from PHY registers and resolving
the desired setting.
CTRL.SPEED
Set by software based on reading PHY status register after PHY has auto-negotiated
a successful link-up.
STATUS.FD
Reflects the MAC forced duplex setting written to CTRL.FD.
STATUS.LU
Reflects link indication (LINK) from PHY qualified with CTRL.SLU (set to 1).
STATUS.SPEED
Reflects MAC forced speed setting written in CTRL.SPEED.
4.6.7.2.3
MAC/PHY Duplex and Speed Settings Both Forced by Software
(Fully-Forced Link Setup) (CTRL.FRCDPLX = 1b, CTRL.FRCSPD =
1b, CTRL.SLU = 1b)
CTRL.FD
Set by software to desired full/half duplex operation (must match duplex setting of
PHY).
CTRL.SLU
Must be set to 1 by software to enable communications between MAC and PHY. PHY
must also be forced/configured to indicate positive link indication (LINK) to the MAC.
CTRL.RFCE
Must be set by software to desired flow-control operation (must match flow-control
settings of PHY).
CTRL.TFCE
Must be set by software to desired flow-control operation (must match flow-control
settings of PHY).
CTRL.SPEED
Set by software to desired link speed (must match speed setting of PHY).
STATUS.FD
Reflects the MAC duplex setting written by software to CTRL.FD.
STATUS.LU
Reflects 1 (positive link indication LINK from PHY qualified with CTRL.SLU). Note that
since both CTRL.SLU and the PHY link indication LINK are forced, this bit set does
not guarantee that operation of the link has been truly established.
STATUS.SPEED
Reflects MAC forced speed setting written in CTRL.SPEED.
4.6.7.3
MAC/SERDES Link Setup (CTRL_EXT.LINK_MODE = 11b)
Link setup procedures using an external SERDES interface mode:
4.6.7.3.1
Hardware Auto-Negotiation Enabled (PCS_LCTL. AN ENABLE = 1b;
CTRL.FRCSPD = 0b; CTRL.FRCDPLX = 0)
CTRL.FD
Ignored; duplex is set by priority resolution of PCS_ANDV and PCS_LPAB.
CTRL.SLU
Must be set to 1 by software to enable communications to the SerDes.
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CTRL.RFCE
Set by Hardware according to auto negotiation resolution1.
CTRL.TFCE
Set by Hardware according to auto negotiation resolution1.
CTRL.SPEED
Ignored; speed always 1000Mb/s when using SerDes mode communications.
STATUS.FD
Reflects hardware-negotiated priority resolution.
STATUS.LU
Reflects PCS_LSTS.AN COMPLETE (Auto-Negotiation complete).
STATUS.SPEED
Reflects 1000Mb/s speed, reporting fixed value of (10)b.
PCS_LCTL.FSD
Must be zero.
PCS_LCTL.Force Flow Control
Must be zero1.
PCS_LCTL.FSV
Must be set to 10b. Only 1000 Mb/s is supported in SerDes mode.
PCS_LCTL.FDV
Ignored; duplex is set by priority resolution of PCS_ANDV and PCS_LPAB.
PCS_LCTL.AN TIMEOUT EN
Must be 1b to enable Auto-negotiation time-out.
CONNSW.ENRGSRC
Must be 0b on 1000BASE-BX backplane, when source of the signal detect indication
is internal. When connected to an optical module and SRDS_[n]_SIG_DET pin is
connected to the module, should be 1b.
CTRL.ILOS
If SRDS_[n]_SIG_DET pin connected to optical module, should be set according to
optical module polarity.
4.6.7.3.2
Auto-Negotiation Skipped (PCS_LCTL.AN ENABLE = 0b;
CTRL.FRCSPD = 1b; CTRL.FRCDPLX = 1)
CTRL.FD
Must be set to 1b. - only full duplex is supported in SerDes mode.
CTRL.SLU
Must be set to 1b by software to enable communications to the SerDes.
CTRL.RFCE
Must be 0b (No Auto-negotiation).
CTRL.TFCE
Must be 0b (No Auto-negotiation).
CTRL.SPEED
Must be set to 10b. Only 1000 Mb/s is supported in SerDes mode.
STATUS.FD
Reflects the value written by software to CTRL.FD.
STATUS.LU
Reflects whether the PCS detected comma symbols, qualified with CTRL.SLU (set to
1b).
STATUS.SPEED
Reflects 1000Mb/s speed, reporting fixed value of 10b.
1. If PCS_LCTL.Force Flow Control is set, the auto negotiation result is not reflected in the CTRL.RFCE
and CTRL.TFCE registers. In This case, the software must set these fields after reading flow control
resolution from PCS registers.
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PCS_LCTL.FSD
Must be set to 1b by software to enable communications to the SerDes.
PCS_LCTL.Force Flow Control
Must be set to 1b.
PCS_LCTL.FSV
Must be set to 10b. Only 1000 Mb/s is supported in SerDes mode.
PCS_LCTL.FDV
Must be set to 1b - only full duplex is supported in SerDes mode.
PCS_LCTL.AN TIMEOUT EN
Must be 0b when Auto-negotiation is disabled.
CONNSW.ENRGSRC
Must be 0b on 1000BASE-BX backplane, when source of the signal detect indication
is internal. When connected to an optical module and SRDS_[n]_SIG_DET pin is
connected to the module, should be 1b.
CTRL.ILOS
If SRDS_[n]_SIG_DET pin connected to optical module, should be set according to
optical module polarity.
4.6.7.4
MAC/SGMII Link Setup (CTRL_EXT.LINK_MODE = 10b)
Link setup procedures using an external SGMII interface mode:
4.6.7.4.1
Hardware Auto-Negotiation Enabled
(PCS_LCTL. AN ENABLE = 1b, CTRL.FRCDPLX = 0b, CTRL.FRCSPD =
0b)
CTRL.FD
Ignored; duplex is set by priority resolution of PCS_ANDV and PCS_LPAB.
CTRL.SLU
Must be set to 1b by software to enable communications to the SerDes.
CTRL.RFCE
Must be set by software after reading flow control resolution from PCS registers.
CTRL.TFCE
Must be set by software after reading flow control resolution from PCS registers.
CTRL.SPEED
Ignored; speed setting is established from SGMII's internal indication to the MAC
after SGMII PHY has auto-negotiated a successful link-up.
STATUS.FD
Reflects hardware-negotiated priority resolution.
STATUS.LU
Reflects PCS_LSTS.Link OK
STATUS.SPEED
Reflects actual speed setting negotiated by the SGMII and indicated to the MAC.
PCS_LCTL.Force Flow Control
Ignored.
PCS_LCTL.FSD
Should be set to zero.
PCS_LCTL.FSV
Ignored; speed is set by priority resolution of PCS_ANDV and PCS_LPAB.
PCS_LCTL.FDV
Ignored; duplex is set by priority resolution of PCS_ANDV and PCS_LPAB.
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PCS_LCTL.AN TIMEOUT EN
Must be 0b. Auto-negotiation not supported in SGMII mode.
CONNSW.ENRGSRC
Must be 0b. In SGMII mode source of the signal detect indication is internal.
4.6.7.5
MAC/1000BASE-KX Link Setup
(CTRL_EXT.LINK_MODE = 01b)
4.6.7.5.1
Auto-Negotiation Skipped (PCS_LCTL.AN ENABLE = 0b;
CTRL.FRCSPD = 1b; CTRL.FRCDPLX = 1b)
Link setup procedures using an external 1000BASE-KX Server Backplane interface mode:
CTRL.FD
Must be set to 1b. 1000BASE-KX always in full duplex mode.
CTRL.SLU
Must be set to 1b by software to enable communications to the SerDes.
CTRL.RFCE
Must be 0b (No Auto-negotiation).
CTRL.TFCE
Must be 0b (No Auto-negotiation).
CTRL.SPEED
Must be set to 10b. Only 1000 Mb/s is supported in 1000BASE-KX mode.
STATUS.FD
Reflects the value written by software to CTRL.FD.
STATUS.LU
Reflects whether the PCS detected comma symbols, qualified with CTRL.SLU (set to
1b).
STATUS.SPEED
Reflects 1000Mb/s speed, reporting fixed value of (10b).
PCS_LCTL.FSD
Must be set to 1b by software to enable communications to the 1000BASE-KX
SerDes.
PCS_LCTL.Force Flow Control
Must be set to 1b.
PCS_LCTL.FSV
Must be set to 10b. Only 1000 Mb/s is supported in 1000BASE-KX mode.
PCS_LCTL.FDV
Must be set to 1b - only full duplex is supported in 1000BASE-KX mode.
PCS_LCTL.AN TIMEOUT EN
Must be 0b. Auto-negotiation not supported in 1000BASE-KX mode.
CONNSW.ENRGSRC
4.6.8
Must be 0b. In 1000BASE-KX mode source of the signal detect indication is
internal.
Initialization of Statistics
Statistics registers are hardware-initialized to values as detailed in each particular register's
description. The initialization of these registers begins upon transition to D0active power state (when
internal registers become accessible, as enabled by setting the Memory Access Enable of the PCIe
Command register), and is guaranteed to be completed within 1 sec of this transition. Access to
statistics registers prior to this interval might return indeterminate values.
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All of the statistical counters are cleared on read and a typical device driver reads them (thus making
them zero) as a part of the initialization sequence.
4.6.9
Receive Initialization
Program the Receive address register(s) per the station address. This can come from the EEPROM or by
any other means (for example, on some machines, this comes from the system PROM not the EEPROM
on the adapter card).
Set up the MTA (Multicast Table Array) by software. This means zeroing all entries initially and adding in
entries as requested.
Program RCTL with appropriate values. If initializing it at this stage, it is best to leave the receive logic
disabled (EN = 0b) until after the receive descriptor rings have been initialized. If VLANs are not used,
software should clear VFE. Then there is no need to initialize the VFTA. Select the receive descriptor
type.
The following should be done once per receive queue needed:
• Allocate a region of memory for the receive descriptor list.
• Receive buffers of appropriate size should be allocated and pointers to these buffers should be
stored in the descriptor ring.
• Program the descriptor base address with the address of the region.
• Set the length register to the size of the descriptor ring.
• Program SRRCTL of the queue according to the size of the buffers, the required header handling
and the drop policy.
• If header split or header replication is required for this queue, program the PSRTYPE register
according to the required headers.
• Enable the queue by setting RXDCTL.ENABLE. In the case of queue zero, the enable bit is set by
default - so the ring parameters should be set before RCTL.RXEN is set.
• Poll the RXDCTL register until the ENABLE bit is set. The tail should not be bumped before this bit
was read as one.
• Program the direction of packets to this queue according to the mode selected in the MRQC register.
Packets directed to a disabled queue are dropped.
Note:
4.6.9.1
The tail register of the queue (RDT[n]) should not be bumped until the queue is enabled.
Initialize the Receive Control Register
To properly receive packets the receiver should be enabled by setting RCTL.RXEN. This should be done
only after all other setup is accomplished. If software uses the Receive Descriptor Minimum Threshold
Interrupt, that value should be set.
4.6.9.2
Dynamic Enabling and Disabling of Receive Queues
Receive queues can be dynamically enabled or disabled given the following procedure is followed:
Enabling:
• Follow the per queue initialization described in the previous section.
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Note:
If there are still packets in the packet buffer directed to this queue according to previous
settings, they are received after the queue is re-enabled. In order to avoid this condition,
the software might poll the PBRWAC register. Once a an empty condition of the relevant
packet buffer is detected or 2 wrap around occurrences are detected the queue can be reenabled.
Disabling:
• Disable the direction of packets to this queue.
• Disable the queue by clearing RXDCTL.ENABLE. The 82580EB/DB stops fetching and writing back
descriptors from this queue immediately. The 82580EB/DB eventually completes the storage of one
buffer allocated to this queue. Any further packet directed to this queue is dropped. If the currently
processed packet is spread over more than one buffer, all subsequent buffers are not written.
• The 82580EB/DB clears RXDCTL.ENABLE only after all pending memory accesses to the descriptor
ring or to the buffers are done. The driver should poll this bit before releasing the memory allocated
to this queue.
The RX path might be disabled only after all Rx queues are disabled.
4.6.10
Transmit Initialization
• Program the TCTL register according to the MAC behavior needed.
If work in half duplex mode is expected, program the TCTL_EXT.COLD field. For internal PHY mode the
default value of 0x42 is OK. For SGMII mode, a value reflecting the 82580EB/DB and the PHY SGMII
delays should be used. A suggested value for a typical PHY is 0x46 for 10 Mbps and 0x4C for 100 Mbps.
The following should be done once per transmit queue:
• Allocate a region of memory for the transmit descriptor list.
• Program the descriptor base address with the address of the region.
• Set the length register to the size of the descriptor ring.
• Program the TXDCTL register with the desired TX descriptor write back policy. Suggested values
are:
— WTHRESH = 1b
— All other fields 0b.
• If needed, set the TDWBAL/TWDBAH to enable head write back
• Enable the queue using TXDCTL.ENABLE (queue zero is enabled by default).
• Poll the TXDCTL register until the ENABLE bit is set.
Note:
The tail register of the queue (TDT[n]) should not be bumped until the queue is enabled.
Enable transmit path by setting TCTL.EN. This should be done only after all other settings are done.
4.6.10.1
Dynamic Queue Enabling and Disabling
Transmit queues can be dynamically enabled or disabled given the following procedure is followed:
Enabling:
• Follow the per queue initialization described in the previous section.
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Disabling:
• Stop storing packets for transmission in this queue.
• Wait until the head of the queue (TDH) is equal to the tail (TDT), i.e. the queue is empty.
• Disable the queue by clearing TXDCTL.ENABLE.
The Tx path might be disabled only after all Tx queues are disabled.
4.6.11
Virtualization Initialization Flow
4.6.11.1
VMDq Mode
4.6.11.1.1
Global Filtering and Offload Capabilities
• Select the VMDQ pooling method - MAC/VLAN filtering for pool selection. MRQC.Multiple Receive
Queues Enable = 011b.
• Set the RPLOLR and RPLPSRTYPE registers to define the behavior of replicated packets.
• Configure VT_CTL.DEF_PL to define the default pool. If packets with no pools should be dropped,
set VT_CTL.Dis_def_Pool field.
• If needed, enable padding of small packets via the RCTL.PSP
4.6.11.1.2
Mirroring rules
For each mirroring rule to be activated:
a.
Set the type of traffic to be mirrored in the VMRCTL[n] register.
b.
Set the mirror pool in the VMRCTL[n].MP
c.
For pool mirroring, set the VMRVM[n] register with the pools to be mirrored.
d.
For VLAN mirroring, set the VMVRLAN[n] with the indexes from the VLVF registers of the VLANs
to be mirrored.
4.6.11.1.3
Per Pool Settings
As soon as a pool of queues is associated to a VM the software should set the following parameters:
1. Address filtering:
a.
The unicast MAC address of the VM by enabling the pool in the RAH/RAL registers.
b.
If all the MAC addresses are used, the unicast hash table (UTA) can be used. Pools servicing VMs
whose address is in the hash table should be declared as so by setting the VMOLR.ROPE. Packets
received according to this method didn’t pass perfect filtering and are indicated as such.
c.
Enable the pool in all the RAH/RAL registers representing the multicast MAC addresses this VM
belongs to.
d.
If all the MAC addresses are used, the multicast hash table (MTA) can be used. Pools servicing
VMs using multicast addresses in the hash table should be declared as so by setting the
VMOLR.ROMPE. Packets received according to this method didn’t pass perfect filtering and are
indicated as such.
e.
Define whether this VM should get all multicast/broadcast packets in the same VLAN via the
VMOLR.MPE and VMOLR.BAM fields
f.
Enable the pool in each VLVF register representing a VLAN this VM belongs to.
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g.
Define whether the pool belongs to the default VLAN and should accept untagged packets via
the VMOLR.AUPE field
2. Offloads
a.
Define whether VLAN header should be stripped from the packet (defined by VMOLR.strvlan).
b.
Set which header split is required via the PSRTYPE register.
c.
Set whether larger than standard packet are allowed by the VM and what is the largest packet
allowed (jumbo packets support) via VMOLR.RLPML & VMOLR.RLE.
3. Queues
a.
Enable Rx & Tx queues as described in Section 4.6.9 & Section 4.6.10
b.
For each Rx queue a drop/no drop flag can be set in SRRCTL.DROP_EN, controlling the behavior
in cases no receive buffers are available in the queue to receive packets. The usual behavior is
to allow drops in order to avoid head of line blocking, unless a no-drop behavior is needed for
some type of traffic (e.g. storage).
4.6.11.1.4
Security Features
4.6.11.1.4.1
Storm control
The driver may set limits to the broadcast or multicast traffic it can receive.
1. It should set the how many 64 byte chunks of Broadcast and Multicast traffic are acceptable per
interval via the BSCTRH and MSCTRH respectively.
2. It should then set the interval to be used via the SCCRL.Interval field and which action to take when
the broadcast or multicast traffic crosses the programmed threshold via the SCCRL.BDIPW,
SCCRL.BDICW, SCCRL.MDIPW, and SCCRL.MDICW fields.
3. The driver may be notified of storm control events through the ICR.SCE interrupt cause.
4.7
Access to shared resources
Part of the resources in the 82580EB/DB are shared between several software entities - namely the
drivers of the four ports and the internal firmware. In order to avoid contentions, a driver that needs to
access one of these resources should use the flow described in Section 4.7.1 in order to acquire
ownership of this resource and use the flow described in Section 4.7.2 in order to relinquish ownership
of this resource.
The shared resources are:
1. EEPROM.
2. All PHYs or SerDes ports.
3. CSRs accessed by the internal firmware after the initialization process. Currently there are no such
CSRs.
4. The flash.
5. Software to Software Mailbox
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Acquiring ownership over a shared resource — Intel® 82580EB/82580DB GbE Controller
Note:
Any other software tool that accesses the register set directly should also follow the flow
described below.
4.7.1
Acquiring ownership over a shared resource
The following flow should be used to acquire a shared resource:
1. Get ownership of the software/software semaphore SWSM.SMBI (offset 0x5B50 bit 0).
a.
Read the SWSM register.
b.
If SWSM.SMBI is read as zero, the semaphore was taken.
c.
Otherwise, go back to step a.
This step assure that other software will not access the shared resources register (SW_FW_SYNC).
2. Get ownership of the software/firmware semaphore SWSM.SWESMBI (offset 0x5B50 bit 1):
a.
Set the SWSM.SWESMBI bit.
b.
Read SWSM.
c.
If SWSM.SWESMBI was successfully set - the semaphore was acquired - otherwise, go back to
step a.
This step assure that the internal firmware will not access the shared resources register
(SW_FW_SYNC).
3. Software reads the Software-Firmware Synchronization Register (SW_FW_SYNC) and checks both
bits in the pair of bits that control the resource it wishes to own.
a.
If both bits are cleared (both firmware and other software does not own the resource), software
sets the software bit in the pair of bits that control the resource it wishes to own.
b.
If one of the bits is set (firmware or other software owns the resource), software tries again later.
4. Release ownership of the software/software semaphore and the software/firmware semaphore by
clearing SWSM.SMBI and SWSM.SWESMBI bits.
5. At this stage, the shared resources is owned by the driver and it may access it. The SWSM and
SW_FW_SYNC registers can now be used to take ownership of another shared resources.
Note:
Software ownership of SWSM.SWESMBI bit should not exceed 100 mS. If Software takes
ownership for a longer duration, Firmware may implement a timeout mechanism and take
ownership of the SWSM.SWESMBI bit.
Software ownership of bits in SW_FW_SYNC register should not exceed 1 Second. If
Software takes ownership for a longer duration, Firmware may implement a timeout
mechanism and take ownership of the relevant SW_FW_SYNC bits.
4.7.2
Releasing ownership over a shared resource
The following flow should be used to release a shared resource:
1. Get ownership of the software/software semaphore SWSM.SMBI (offset 0x5B50 bit 0).
a.
Read the SWSM register.
b.
If SWSM.SMBI is read as zero, the semaphore was taken.
c.
Otherwise, go back to step a.
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This step assures that other software will not access the shared resources register (SW_FW_SYNC).
2. Get ownership of the software/firmware semaphore SWSM.SWESMBI (offset 0x5B50 bit 1):
a.
Set the SWSM.SWESMBI bit.
b.
Read SWSM.
c.
If SWSM.SWESMBI was successfully set - the semaphore was acquired - otherwise, go back to
step a.
This step assure that the internal firmware will not access the shared resources register
(SW_FW_SYNC).
3. Clear the bit in SW_FW_SYNC that controls the software ownership of the resource to indicate this
resource is free.
4. Release ownership of the software/software semaphore and the software/firmware semaphore by
clearing SWSM.SMBI and SWSM.SWESMBI bits.
5. At this stage, the shared resource are released by the driver and it may not access it. The SWSM
and SW_FW_SYNC registers can now be used to take ownership of another shared resource.
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4.7.3
Software to Software Mailbox
In order to allow different the 82580EB/DB drivers to coordinate activities, a simple mailbox
mechanism is defined. This mechanism allows each driver to send a broadcast message to all the other
drivers on the same device.
In order to send a message the following flow should be used:
1. The Driver that wants to send the message should acquire the mailbox semaphore
(SW_FW_SYNC.SW_MB_SM) using the flow described in the previous sections.
2. The Driver should then write the message in the SWMBWR register.
3. All the drivers will then receive an interrupt (except for the driver that initiated the message) via
the SWMB cause in the ICR registers.
4. All the drivers will read the SWMB0, SWMB1, SWMB2 and SWMB3 registers to understand which
driver sent a message.
Note:
The mapping of SWMB0, SWMB1, SWMB2 and SWMB3 registers is according to the physical
ports. A function can detect which physical port it is mapped to, by reading the STATUS.LAN
ID field.
5. If the message requires an acknowledgment from the other drivers, each driver may write an
acknowledge message through their SWMBWR register.
6. The driver that sent the original message can then poll the SWMB0, SWMB1, SWMB2 and SWMB3
registers for acknowledge messages.
7. After the message was acknowledged, the driver that sent the original message should:
a.
clear the value in the SWMBWR register to avoid confusion when future messages are sent.
b.
Release the Software mailbox semaphore (SW_FW_SYNC.SW_MB_SM) using the flow described
in the previous section.
§§
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Power Management — Intel® 82580EB/82580DB GbE Controller
5.0
Power Management
This section describes how power management is implemented in the 82580EB/DB. The 82580EB/DB
supports the Advanced Configuration and Power Interface (ACPI) specification as well as Advanced
Power Management (APM).
Note:
Power management can be disabled via the power management bit in the Initialization
Control Word 1 EERPROM word (see Section 6.2.2).
5.1
General Power State Information
5.1.1
PCI Device Power States
The PCIe Specification defines function power states (D-states) that enable the platform to establish
and control power states for the 82580EB/DB ranging from fully on to fully off (drawing no power) and
various in-between levels of power-saving states, annotated as D0-D3. Similarly, PCIe defines a series
of link power states (L-states) that work specifically within the link layer between the 82580EB/DB and
its upstream PCIe port (typically in the host chipset).
Since the 82580EB/DB is a multi-port device, each of its PCI functions may be in a different state at any
given moment. The device power state is defined by the most active function. For example, if function
0 is in D0 state and all other functions are in D3 state, device state is D0. Link state follows the device
state. For a given device D-state, only certain L-states are possible as follows.
• D0 (fully on): The 82580EB/DB is completely active and responsive during this D-state. The link
can be in either L0 or a low-latency idle state referred to as L0s. Minimizing L0s exit latency is
paramount for enabling frequent entry into L0s while facilitating performance needs via a fast exit.
A deeper link power state, L1 state, is supported as well.
• D1 and D2: These modes are not supported by the 82580EB/DB.
• D3 (off): Two sub-states of D3 are supported:
— D3hot, where primary power is maintained.
— D3cold, where primary power is removed.
Link states are mapped into device states as follows:
— D3hot maps to L1 to support clock removal on mobile platforms
— D3cold maps to L2 if auxiliary power is supported on 82580EB/DB with wake-capable logic, or
to L3 if no power is delivered to 82580EB/DB. A sideband PE_WAKE_N mechanism is supported
to interface wake-enabled logic on mobile platforms during the L2 state.
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5.1.2
PCIe Link Power States
Configuring the 82580EB/DB into a D-state automatically causes the PCIe link to transition to the
appropriate L-state.
• L2/L3 Ready: This link state prepares the PCIe link for the removal of power and clock. The
82580EB/DB is in the D3hot state and is preparing to enter D3cold. The power-saving opportunities
for this state include, but are not limited to, clock gating of all PCIe architecture logic, shutdown of
the PLL, and shutdown of all transceiver circuitry.
• L2: This link state is intended to comprehend D3cold with auxiliary power support. Note that
sideband PE_WAKE_N signaling exists to cause wake-capable devices to exit this state. The powersaving opportunities for this state include, but are not limited to, shutdown of all transceiver
circuitry except detection circuitry to support exit, clock gating of all PCIe logic, and shutdown of
the PLL as well as appropriate platform voltage and clock generators.
• L3 (link off): Power and clock are removed in this link state, and there is no auxiliary power
available. To bring the 82580EB/DB and its link back up, the platform must go through a boot
sequence where power, clock, and reset are reapplied appropriately.
5.2
Power States
The 82580EB/DB supports the D0 and D3 architectural power states as described earlier. Internally, The
82580EB/DB supports the following power states:
• D0u (D0 un-initialized) - an architectural sub-state of D0
• D0a (D0 active) - an architectural sub-state of D0
• D3 - architecture state D3hot
• Dr - internal state that contains the architecture D3cold state. Dr state is entered when PE_RST_N
is asserted or a PCIe in-band reset is received
Figure 5-1 shows the power states and transitions between them.
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Figure 5-1.
Power Management State Diagram
5.2.1
D0 Uninitialized State (D0u)
The D0u state is an architectural low-power state.
When entering D0u, the 82580EB/DB:
• Asserts a reset to the PHY while the EEPROM is being read
• Disables wake up. However, if the APM Mode bit in the EEPROM's Initialization Control Word 2 is set,
then APM wake up is enabled.
5.2.1.1
Entry into D0u state
D0u is reached from either the Dr state (on de-assertion of PE_RST_N) or the D3hot state (by
configuration software writing a value of 00b to the Power State field of the PCI PM registers).
5.2.1.2
Exit from D0u state
De-asserting PE_RST_N means that the entire state of the 82580EB/DB is cleared, other than sticky
bits. State is loaded from the EEPROM, followed by establishment of the PCIe link. Once this is done,
configuration software can access the 82580EB/DB.
On a transition from D3 to D0u state, the 82580EB/DB PCI configuration space is not reset. However,
the 82580EB/DB requires that software perform a full re-initialization of the function including its PCI
configuration space.
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5.2.2
D0active State
Once memory space is enabled, the 82580EB/DB enters the D0 active state. It can transmit and receive
packets if properly configured by the software device driver. The PHY is enabled or re-enabled by the
software device driver to operate/auto-negotiate to full line speed/power if not already operating at full
capability. Any APM wake up previously active remains active. The software device driver can deactivate
APM wake up by writing to the Wake Up Control (WUC) register or activate other wake-up filters by
writing to the Wake Up Filter Control (WUFC) register.
5.2.2.1
Entry to D0a state
D0a is entered from the D0u state by writing a 1b to the Memory Access Enable or the
I/O Access Enable bit of the PCI Command register. The DMA, MAC, and PHY of the appropriate LAN
function are also enabled.
5.2.3
D3 State (PCI-PM D3hot)
The 82580EB/DB transitions to D3 when the system writes a 11b to the Power State field of the Power
Management Control/Status Register (PMCSR). Any wake-up filter settings that were enabled before
entering this state are maintained. Upon completion or during the transition to D3 state, the 82580EB/
DB clears the Memory Access Enable and I/O Access Enable bits of the PCI Command register, which
disables memory access decode. While in D3, the 82580EB/DB does not generate master cycles.
Configuration and message requests are the only TLPs accepted by a function in the D3hot state. All
other received requests must be handled as unsupported requests, and all received completions are
handled as unexpected completions. If an error caused by a received TLP (such as an unsupported
request) is detected while in D3hot, and reporting is enabled, the link must be returned to L0 if it is not
already in L0 and an error message must be sent. See section 5.3.1.4.1 in The PCIe Base Specification
5.2.3.1
Entry to D3 State
Transition to D3 state is through a configuration write to the Power State field of the PCI-PM registers.
Prior to transition from D0 to the D3 state, the software device driver disables scheduling of further
tasks to the 82580EB/DB; it masks all interrupts and does not write to the Transmit Descriptor Tail
(TDT) register or to the Receive Descriptor Tail (RDT) register and operates the master disable
algorithm as defined in Section 5.2.3.3.
If wake up capability is needed, system should enable wake capability by setting to 1b the PME_En bit
in the Power Management Control / Status Register (PMCSR). After Wake capability has been enabled
Software device driver should set up the appropriate wake up registers prior to the D3 transition.
Note:
If operation during D3cold is required, even when Wake capability is not required (e.g. for
manageability operation), system should also set the Auxiliary (AUX) Power PM Enable bit in
the PCIe Device Control register.
As a response to being programmed into D3 state, the 82580EB/DB transitions its PCIe link into the L1
link state. As part of the transition into L1 state, the 82580EB/DB suspends scheduling of new TLPs and
waits for the completion of all previous TLPs it has sent. The 82580EB/DB clears the Memory Access
Enable and I/O Access Enable bits of the PCI Command register, which disables memory access decode.
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Any receive packets that have not been transferred into system memory are kept in the 82580EB/DB
(and discarded later on D3 exit). Any transmit packets that have not be sent can still be transmitted
(assuming the Ethernet link is up).
In order to reduce power consumption, if the link is still needed for manageability or wake-up
functionality, the PHY auto-negotiates to a lower link speed on D3 entry (See Section 3.5.7.5.4).
5.2.3.2
Exit from D3 State
A D3 state is followed by either a D0u state (in preparation for a D0a state) or by a transition to Dr
state (PCI-PM D3cold state). To transition back to D0u, the system writes a 00b to the Power State field
of the Power Management Control/Status Register (PMCSR). Transition to Dr state is through PE_RST_N
assertion.
the 82580EB/DB always sets the No_Soft_Reset bit in the PCIe Power Management Control / Status
Register (PMCSR) to 0b to indicate that The 82580EB/DB performs an internal reset on transition from
D3hot to D0. Configuration context is lost when performing the soft reset. After transition from the
D3hot to the D0 state, full re-initialization sequence is needed to return The 82580EB/DB to D0
Initialized.
5.2.3.3
Master Disable Via CTRL Register
System software can disable master accesses on the PCIe link by either clearing the PCI Bus Master bit
or by bringing the function into a D3 state. From that time on, the 82580EB/DB must not issue master
accesses for this function. Due to the full-duplex nature of PCIe, and the pipelined design in the
82580EB/DB, it might happen that multiple requests from several functions are pending when the
master disable request arrives. The protocol described in this section insures that a function does not
issue master requests to the PCIe link after its Master Enable bit is cleared (or after entry to D3 state).
Two configuration bits are provided for the handshake between the 82580EB/DB function and its
software device driver:
• GIO Master Disable bit in the Device Control (CTRL) register - When the GIO Master Disable bit is
set, the 82580EB/DB blocks new master requests by this function. The 82580EB/DB then proceeds
to issue any pending requests by this function. This bit is cleared on master reset
(LAN_PWR_GOOD, PCIe reset and software reset) to enable master accesses.
• GIO Master Enable Status bit in the Device Status (STATUS) register - Cleared by the 82580EB/DB
when the GIO Master Disable bit is set and no master requests are pending by the relevant function
and is set otherwise. Indicates that no master requests are issued by this function as long as the
GIO Master Disable bit is set. The following activities must end before the 82580EB/DB clears the
GIO Master Enable Status bit:
— Master requests by the transmit and receive engines (for both data and MSI/MSIx interrupts).
— All pending completions to the 82580EB/DB are received.
In the event of a PCIe Master disable (Configuration Command register.BME set to 0) on a certain
function or LAN port or if the function is moved into D3 state during a DMA access, the 82580EB/DB
generates an internal reset to the function and stops all port DMA accesses and interrupts related to the
function. Following move to normal operating mode software driver should re-initialize the receive and
transmit queues of the relevant port.
Notes:
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The software device driver sets the GIO Master Disable bit when notified of a pending
master disable (or D3 entry). The 82580EB/DB then blocks new requests and proceeds to
issue any pending requests by this function. The software device driver then polls the GIO
Master Enable Status bit. Once the bit is cleared, it is guaranteed that no requests are
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pending from this function. The software device driver might time out if the GIO Master
Enable Status bit is not cleared within a given time.
The GIO Master Disable bit must be cleared to enable a master request to the PCIe link.
This can be done either through reset or by the software device driver.
5.2.4
Dr State (D3cold)
Transition to Dr state is initiated on several occasions:
• On system power up - Dr state begins with the assertion of the internal power detection circuit and
ends with de-assertion of PE_RST_N.
• On transition from a D0a state - During operation the system might assert PE_RST_N at any time.
In an ACPI system, a system transition to the G2/S5 state causes a transition from D0a to Dr state.
• On transition from a D3 state - The system transitions the 82580EB/DB into the Dr state by
asserting PCIe PE_RST_N.
Any wake-up filter settings that were enabled before entering this reset state are maintained.
The system might maintain PE_RST_N asserted for an arbitrary time. The de-assertion (rising edge) of
PE_RST_N causes a transition to D0u state.
While in Dr state, the 82580EB/DB might enter one of several modes with different levels of
functionality and power consumption. The lower-power modes are achieved when the 82580EB/DB is
not required to maintain any functionality (see Section 5.2.4.1).
Note:
5.2.4.1
If the 82580EB/DB is configured to provide a 50 MHz NC-SI clock (via the NC-SI Output
Clock EEPROM bit), then the NC-SI clock must be provided in Dr state as well.
Dr Disable Mode
The 82580EB/DB enters a Dr disable mode on transition to D3cold state when it does not need to
maintain any functionality. The conditions to enter either state are:
• The 82580EB/DB (all PCI functions) is in Dr state
• APM WOL is inactive for all LAN functions
• Pass-through manageability is disabled
• ACPI PME is disabled for all PCI functions
• The 82580EB/DB Power Down Enable EEPROM bit (word 0x1E, bit 15) is set (default hardware
value is disabled).
• The PHY Power Down Enable EEPROM bit is set (word 0xF, bit 6).
Entering Dr disable mode is usually done by asserting PCIe PE_RST_N. It might also be possible to
enter Dr disable mode by reading the EEPROM while already in Dr state. The usage model for this later
case is on system power up, assuming that manageability and wake up are not required. Once the
82580EB/DB enters Dr state on power-up, the EEPROM is read. If the EEPROM contents determine that
the conditions to enter Dr disable mode are met, the 82580EB/DB then enters this mode (assuming
that PCIe PE_RST_N is still asserted).
The 82580EB/DB exits Dr disable mode when Dr state is exited (See Figure 5-1 for conditions to exit Dr
state).
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5.2.4.2
Entry to Dr State
Dr entry on platform power-up begins with the assertion of the internal power detection circuit. The
EEPROM is read and determines 82580EB/DB configuration. If the APM Enable bit in the EEPROM's
Initialization Control Word 3 is set, then APM wake up is enabled. PHY and MAC states are
redetermined by the state of manageability and APM wake. To reduce power consumption, if
manageability or APM wake is enabled, the PHY auto-negotiates to a lower link speed on Dr entry (See
Section 3.5.7.5.4). The PCIe link is not enabled in Dr state following system power up (since PE_RST_N
is asserted).
Entering Dr state from D0a state is done by asserting PE_RST_N. An ACPI transition to the G2/S5 state
is reflected in the 82580EB/DB transition from D0a to Dr state. The transition can be orderly (such as
user selecting the shut down option), in which case the software device driver might have a chance to
intervene. Or, it might be an emergency transition (such as power button override), in which case, the
software device driver is not notified.
To reduce power consumption, if any of manageability, APM wake or PCI-PM PME1 is enabled, the PHY
auto-negotiates to a lower link speed on D0a to Dr transition (see Section 3.5.7.5.4).
Transition from D3 (hot) state to Dr state is done by asserting PE_RST_N. Prior to that, the system
initiates a transition of the PCIe link from L1 state to either the L2 or L3 state (assuming all functions
were already in D3 state). The link enters L2 state if PCI-PM PME is enabled.
5.2.4.3
Auxiliary Power Usage
The EEPROM D3COLD_WAKEUP_ADVEN bit and the AUX_PWR strapping pin determine when D3cold
PME is supported:
• D3COLD_WAKEUP_ADVEN denotes that PME wake should be supported
• AUX_PWR strapping pin indicates that auxiliary power is provided
D3cold PME is supported as follows:
• If the D3COLD_WAKEUP_ADVEN is set to ‘1’ and the AUX_PWR strapping is set to ‘1’, then D3cold
PME is supported
• Else D3cold PME is not supported
The amount of power required for the function (including the entire NIC) is advertised in the Power
Management Data register, which is loaded from the EEPROM.
If D3cold is supported, the PME_En and PME_Status bits of the Power Management Control/Status
Register (PMCSR), as well as their shadow bits in the Wake Up Control (WUC) register are reset only by
the power up reset (detection of power rising).
5.2.5
Link Disconnect
In any of D0u, D0a, D3, or Dr power states, the 82580EB/DB enters a link-disconnect state if it detects
a link-disconnect condition on the Ethernet link. Note that the link-disconnect state in the internal PHY
is invisible to software (other than the PHPM.Link Energy Detect bit state). In particular, while in D0
state, software might be able to access any of the 82580EB/DB registers as in a link-connect state.
1. ACPI 2.0 specifies that “OSPM will not disable wake events before setting the SLP_EN bit when
entering the S5 sleeping state. This provides support for remote management initiatives by
enabling Remote Power On (RPO) capability. This is a change from ACPI 1.0 behavior.”
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5.2.6
Device Power-Down State
The 82580EB/DB enters a global power-down state if all of the following conditions are met:
• The 82580EB/DB Power Down Enable EEPROM bit (word 0x1E bit 15) was set (default hardware
value is disabled).
• The 82580EB/DB is in Dr state.
• The link connections of all ports (PHY or SerDes) are in power down mode.
The 82580EB/DB also enters a power-down state when the DEV_OFF_N pin is asserted and the relevant
EEPROM bits were configured as previously described (see Section 4.5 for more details on DEV_OFF_N
functionality).
5.3
Power Limits by Certain Form Factors
Table 5-1 lists power limitation introduced by different form factors.
Table 5-1.
Power Limits by Form-Factor
Form Factor
LOM
PCIe add-in card (10 W slot)
Main
N/A
3 A @ 3.3 V
Auxiliary (aux enabled)
375 mA @ 3.3 V
375 mA @ 3.3 V
Auxiliary (aux disabled)
20 mA @ 3.3 V
20 mA @ 3.3 V
Note:
This auxiliary current limit only applies when the primary 3.3 V voltage source is not
available (the card is in a low power D3 state).
The 82580EB/DB exceeds the allocated auxiliary power in some configurations (such as all ports
running at 1000 Mb/s speed). The 82580EB/DB must therefore be configured to meet the previously
mentionedcertain requirements. To do so, the 82580EB/DB implements three EEPROM bits to disable
operation in certain cases:
1. The PHPM.Disable_1000 PHY register bit disables 1000 Mb/s operation under all conditions.
2. The PHPM.Disable 1000 in non-D0a PHY CSR bit disables 1000 Mb/s operation in non-D0a states1.
If PHPM.Disable 1000 in non-D0a is set, and the 82580EB/DB is at 1000 Mb/s speed on entry to a
non-D0a state, then the 82580EB/DB removes advertisement for 1000 Mb/s and auto-negotiates.
3. The PHPM.Disable 100 in non-D0a PHY CSR bit disables 1000 Mb/s and 100 Mb/s operation in nonD0a states. If PHPM.Disable 100 in non-D0a is set, and the 82580EB/DB is at 1000 Mb/s or 100 Mb/
s speeds on entry to a non-D0a state, then the 82580EB/DB removes advertisement for 1000 Mb/s
and 100 Mb/s and auto-negotiates.
Note that the 82580EB/DB restarts link auto-negotiation each time it transitions from a state where
1000 Mb/s or 100 Mb/s speed is enabled to a state where 1000 Mb/s or 100 Mb/s speed is disabled, or
vice versa. For example, if PHPM.Disable 1000 in non-D0a is set but PHPM.Disable_1000 is cleared, the
82580EB/DB restarts link auto-negotiation on transition from D0 state to D3 or Dr states.
1. The restriction is defined for all non-D0a states to have compatible behavior with previous
products.
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5.4
Interconnects Power Management
This section describes the power reduction techniques employed by the 82580EB/DB main
interconnects.
5.4.1
PCIe Link Power Management
The PCIe link state follows the power management state of the 82580EB/DB. Since the 82580EB/DB
incorporates multiple PCI functions, its power management state is defined as the power management
state of the most awake function (see Figure 5-2):
• If any function is in D0 state (either D0a or D0u), the PCIe link assumes the 82580EB/DB is in D0
state. Else,
• If the functions are in D3 state, the PCIe link assumes the 82580EB/DB is in D3 state. Else,
• The 82580EB/DB is in Dr state (PE_RST_N is asserted to all functions).
The 82580EB/DB supports all PCIe power management link states:
• L0 state is used in D0u and D0a states.
• The L0s state is used in D0a and D0u states each time link conditions apply.
• The L1 state is also used in D0a and D0u states when idle conditions apply for a longer period of
time. The L1 state is also used in the D3 state.
• The L2 state is used in the Dr state following a transition from a D3 state if PCI-PM PME is enabled.
• The L3 state is used in the Dr state following power up, on transition from D0a, and if PME is not
enabled in other Dr transitions.
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The 82580EB/DB support for active state link power management is reported via the PCIe Active State
Link PM Support register and is loaded from the EEPROM.
Figure 5-2.
Link Power Management State Diagram
While in L0 state, the 82580EB/DB transitions the transmit lane(s) into L0s state once the idle
conditions are met for a period of time as follows:
L0s configuration fields are:
• L0s enable - The default value of the Active State Link PM Control field in the PCIe Link Control
Register is set to 00b (both L0s and L1 disabled). System software may later write a different value
into the Link Control Register. The default value is loaded on any reset of the PCI configuration
registers.
• L0s exit latency (as published in the L0s Exit Latency field of the Link Capabilities Register) is
loaded from EEPROM. Separate values are loaded when the 82580EB/DB shares the same
reference PCIe clock with its partner across the link, and when the 82580EB/DB uses a different
reference clock than its partner across the link. The 82580EB/DB reports whether it uses the slot
clock configuration through the PCIe Slot Clock Configuration bit loaded from the Slot_Clock_Cfg bit
in the PCIe Init Configuration 3 EEPROM Word.
• L0s Acceptable Latency (as published in the Endpoint L0s Acceptable Latency field of the Device
Capabilities Register) is loaded from EEPROM.
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If link is in L0s state, the 82580EB/DB transitions the link into L1 state once the transmit lanes or both
directions of the link have been in L0s state for a period of time defined in the Latency_To_Enter_L1
field in the PCIe PHY Auto Configuration EEPROM section.
The following EEPROM fields control L1 behavior:
• Act_Stat_PM_Sup - Indicates support for ASPM L1 in the PCIe configuration space (loaded into the
Active State Link PM Support field)
• L1_Act_Ext_Latency - Defines L1 active exit latency
• L1_Act_Acc_Latency - Defines L1 active acceptable exit latency
• Latency_To_Enter_L1 - Defines the period (in the L0s state) before the transition into L1 state
5.4.2
NC-SI Clock Control
The 82580EB/DB can be configured to provide a 50 MHz output clock to its NC-SI interface and other
platform devices. When enabled, the NC-SI clock is provided in all power states without exception.
5.4.3
Internal PHY
Power-Management
The PHY power management features are described in Section 3.5.7.5.
5.5
Timing of Power-State Transitions
The following sections give detailed timing for the state transitions. In the diagrams the dotted
connecting lines represent the 82580EB/DB requirements, while the solid connecting lines represent
the 82580EB/DB guarantees.
The timing diagrams are not to scale. The clocks edges are shown to indicate running clocks only and
are not to be used to indicate the actual number of cycles for any operation.
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5.5.1
Power Up (Off to Dup to D0u to D0a
Figure 5-3.
Power Up (Off to Dup to D0u to D0a)
Table 5-2.
Power Up (Off to Dup to D0u to D0a)
Note
Description
1
Xosc is stable txog after power is stable.
2
LAN_PWR_GOOD is asserted after all power supplies are good and tppg after Xosc is stable.
3
An EEPROM read starts on the rising edge of LAN_PWR_GOOD.
4
After reading the EEPROM, PHY reset is de-asserted.
5
APM wake-up mode can be enabled based on what is read from the EEPROM.
6
The PCIe reference clock is valid tPE_RST-CLK before de-asserting PE_RST_N (according to PCIe specification).
7
PE_RST_N is de-asserted tPVPGL after power is stable (according to PCIe specification).
8
The internal PCIe clock is valid and stable tppg-clkint from PE_RST_N de-assertion.
9
The PCIe internal PWRGD signal is asserted tclkpr after the external PE_RST_N signal.
10
Asserting internal PCIe PWRGD causes the EEPROM to be re-read, asserts PHY reset, and disables wake up.
11
After reading the EEPROM, PHY reset is de-asserted.
12
Link training starts after tpgtrn from PE_RST_N de-assertion.
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Table 5-2.
Note
Power Up (Off to Dup to D0u to D0a) (Continued)
Description
13
A first PCIe configuration access might arrive after tpgcfg from PE_RST_N de-assertion.
14
A first PCI configuration response can be sent after tpgres from PE_RST_N de-assertion.
15
Writing a 1b to the Memory Access Enable bit in the PCI Command Register transitions the 82580EB/DB from D0u to
D0. state.
5.5.2
Transition from D0a to D3 and Back Without PE_RST_N
Figure 5-4.
Transition from D0a to D3 and Back Without PE_RST_N
Table 5-3.
Transition from D0a to D3 and Back Without PE_RST_N
Note
Description
1
Writing 11b to the Power State field of the Power Management Control/Status Register (PMCSR) transitions the
82580EB/DB to D3.
2
The system can keep the 82580EB/DB in D3 state for an arbitrary amount of time.
3
To exit D3 state, the system writes 00b to the Power State field of the PMCSR.
4
APM wake-up or SMBus mode might be enabled based on what is read in the EEPROM.
5
After reading the EEPROM, reset to the PHY is de-asserted. The PHY operates at reduced-speed if APM wake up or
SMBus is enabled, else powered-down.
6
The system can delay an arbitrary time before enabling memory access.
7
Writing a 1b to the Memory Access Enable bit or to the I/O Access Enable bit in the PCI Command Register transitions
the 82580EB/DB from D0u to D0 state and returns the PHY to full-power/speed operation.
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5.5.3
Transition From D0a to D3 and Back With PE_RST_N
Figure 5-5.
Transition From D0a to D3 and Back With PE_RST_N
Table 5-4.
Transition From D0a to D3 and Back With PE_RST_N
Note
Description
1
Writing 11b to the Power State field of the PMCSR transitions the 82580EB/DB to D3. PCIe link transitions to L1 state.
2
The system can delay an arbitrary amount of time between setting D3 mode and transition of the link to an L2 or L3
state.
3
Following link transition, PE_RST_N is asserted.
4
The system must assert PE_RST_N before stopping the PCIe reference clock. It must also wait tl2clk after link transition
to L2/L3 before stopping the reference clock.
5
On assertion of PE_RST_N, the 82580EB/DB transitions to Dr state.
6
The system starts the PCIe reference clock tPE_RST-CLK before de-assertion PE_RST_N.
7
The internal PCIe clock is valid and stable tppg-clkint from PE_RST_N de-assertion.
8
The PCIe internal PWRGD signal is asserted tclkpr after the external PE_RST_N signal.
9
Asserting internal PCIe PWRGD causes the EEPROM to be re-read, asserts PHY reset, and disables wake up.
10
APM wake-up mode might be enabled based on what is read from the EEPROM.
11
After reading the EEPROM, PHY reset is de-asserted.
12
Link training starts after tpgtrn from PE_RST_N de-assertion.
13
A first PCIe configuration access might arrive after tpgcfg from PE_RST_N de-assertion.
14
A first PCI configuration response can be sent after tpgres from PE_RST_N de-assertion.
15
Writing a 1b to the Memory Access Enable bit in the PCI Command Register transitions the 82580EB/DB from D0u to D0
state.
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Transition From D0a to Dr and Back Without Transition to D3 — Intel® 82580EB/82580DB GbE
Controller
5.5.4
Transition From D0a to Dr and Back Without Transition to
D3
Figure 5-6.
Transition From D0a to Dr and Back Without Transition to D3
Table 5-5.
Transition From D0a to Dr and Back Without Transition to D3
Note
Description
1
The system must assert PE_RST_N before stopping the PCIe reference clock. It must also wait tl2clk after link transition
to L2/L3 before stopping the reference clock.
2
On assertion of PE_RST_N, the 82580EB/DB transitions to Dr state and the PCIe link transition to electrical idle.
3
The system starts the PCIe reference clock tPE_RST-CLK before de-assertion PE_RST_N.
4
The internal PCIe clock is valid and stable tppg-clkint from PE_RST_N de-assertion.
5
The PCIe internal PWRGD signal is asserted tclkpr after the external PE_RST_N signal.
6
Asserting internal PCIe PWRGD causes the EEPROM to be re-read, asserts PHY reset, and disables wake up.
7
APM wake-up mode might be enabled based on what is read from the EEPROM.
8
After reading the EEPROM, PHY reset is de-asserted.
9
Link training starts after tpgtrn from PE_RST_N de-assertion.
10
A first PCIe configuration access might arrive after tpgcfg from PE_RST_N de-assertion.
11
A first PCI configuration response can be sent after tpgres from PE_RST_N de-assertion.
12
Writing a 1b to the Memory Access Enable bit in the PCI Command Register transitions the 82580EB/DB from D0u to
D0 state.
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Intel® 82580EB/82580DB GbE Controller — Wake Up
5.6
Wake Up
The 82580EB/DB supports two modes of wake-up management:
1. Advanced Power Management (APM) wake up
2. ACPI/PCIe defined wake up
The usual model is to activate one mode at a time but not both modes together. If both modes are
activated, the 82580EB/DB might wake up the system in unexpected events. For example, if APM is
enabled together with PCIe PME, a magic packet might wake up the system even if APMPME is disabled.
Alternatively, if APM is enabled together with some PCIe filters, packets matching these filters might
wake up the system even if PCIe PME is disabled.
5.6.1
Advanced Power Management Wake Up
Advanced Power Management Wake Up or APM Wakeup (also known as Wake on LAN) is a feature that
existed in earlier 10/100 Mb/s NICs. This functionality was designed to receive a broadcast or unicast
packet with an explicit data pattern, and then assert a subsequent signal to wake up the system. This
was accomplished by using a special signal that ran across a cable to a defined connector on the
motherboard. The NIC would assert the signal for approximately 50 ms to signal a wake up. The
82580EB/DB now uses (if configured) an in-band PM_PME message for this functionality.
On power up, the 82580EB/DB reads the APM Enable bits from the EEPROM Initialization Control Word
3 into the APM Enable (APME) bits of the Wakeup Control (WUC) register. These bits control enabling of
APM wake up.
When APM wake up is enabled, the 82580EB/DB checks all incoming packets for Magic Packets. See
Section 5.6.3.1.4 for a definition of Magic Packets.
Once the 82580EB/DB receives a matching magic packet, and if the Assert PME On APM Wakeup
(WUC.APMPME) bit is set in the Wake Up Control (WUC) register, it:
• Sets the PME_Status bit in the PMCSR register and issues a PM_PME message (in some cases, this
might require asserting the PE_WAKE_N signal first to resume power and clock to the PCIe
interface).
• Stores the first 128 bytes of the packet in the Wake Up Packet Memory (WUPM) register.
• Sets the Magic Packet Received bit in the Wake Up Status (WUS) register.
• Sets the packet length in the Wake Up Packet Length (WUPL) register.
The 82580EB/DB maintains the first Magic Packet received in the Wake Up Packet Memory (WUPM)
register until the software device driver writes a 1b to the Magic Packet Received MAG bit in the Wake
Up Status (WUS) register.
APM wake up is supported in all power states and only disabled if a subsequent EEPROM read results in
the APM Wake Up bit being cleared or software explicitly writes a 0b to the APM Wake Up (APME) bit of
the WUC register.
Note:
When WUC.APMPME is set PE_WAKE_N is asserted and a PM_PME message is issued even if
PMCSR.PME_En is cleared. To enable disabling of system Wake-up when PMCSR.PME_En is
cleared, Software driver should clear the WUC.APMPME bit after power-up or PCIe reset.
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PCIe Power Management Wake Up — Intel® 82580EB/82580DB GbE Controller
5.6.2
PCIe Power Management Wake Up
The 82580EB/DB supports PCIe power management based wake ups. It can generate system wake-up
events from three sources:
• Reception of a Magic Packet.
• Reception of a network wakeup packet.
• Detection of a link change of state.
Activating PCIe power management wake up requires the following:
• The software device driver programs the Wake Up Filter Control (WUFC) register to indicate the
packets it needs to wake up and supplies the necessary data to the IPv4/v6 Address Table (IP4AT,
IP6AT) and the Flexible Host Filter Table (FHFT). It can also set the Link Status Change Wake Up
Enable (LNKC) bit in the Wake Up Filter Control (WUFC) register to cause wake up when the link
changes state.
• The operating system (at configuration time) writes a 1b to the PME_En bit of the Power
Management Control/Status (PMCSR.8) register.
Normally, after enabling wake up, the operating system writes 11b to the lower two bits of the PMCSR
register to place the 82580EB/DB into low-power mode.
Once wake up is enabled, the 82580EB/DB monitors incoming packets, first filtering them according to
its standard address filtering method, then filtering them with all of the enabled wakeup filters. If a
packet passes both the standard address filtering and at least one of the enabled wakeup filters, the
82580EB/DB:
• Sets the PME_Status bit in the PMCSR.
• Asserts PE_WAKE_N (if the PME_En bit in the PMCSR is set).
• Stores the first 128 bytes of the packet in the Wakeup Packet Memory (WUPM) register.
• Sets one or more of the received bits in the Wake Up Status (WUS) register. Note that the
82580EB/DB sets more than one bit if a packet matches more than one filter.
• Sets the packet length in the Wake Up Packet Length (WUPL) register.
If enabled, a link state change wake up causes similar results, setting PME_Status, asserting
PE_WAKE_N and setting the Link Status Changed (LNKC) bit in the Wake Up Status (WUS) register
when the link goes up or down.
The 82580EB/DB supports the following change described in the PCIe Base Specification, Rev. 1.1RD
(section 5.3.3.4) - On receiving a PME_Turn_Off message, the 82580EB/DB must block the
transmission of PM_PME messages and transmit a PME_TO_Ack message upstream. The 82580EB/DB is
permitted to send a PM_PME message after the Link is returned to an L0 state through LDn.
PE_WAKE_N remains asserted until the operating system either writes a 1b to the PME_Status bit of
the PMCSR register or writes a 0b to the PME_En bit.
After receiving a wake-up packet, the 82580EB/DB ignores any subsequent wake-up packets until the
software device driver clears all of the received bits in the Wake Up Status (WUS) register. It also
ignores link change events until the software device driver clears the Link Status Changed (LNKC) bit in
the Wake Up Status (WUS) register.
Note:
Revision: 2.50
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A wake on link change is not supported when configured to SerDes or 1000BASE-KX mode.
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Intel® 82580EB/82580DB GbE Controller — Wake-Up Packets
5.6.3
Wake-Up Packets
The 82580EB/DB supports various wake-up packets using two types of filters:
• Pre-defined filters
• Flexible filters
Each of these filters are enabled if the corresponding bit in the Wake Up Filter Control (WUFC) register
is set to 1b.
5.6.3.1
Pre-Defined Filters
The following packets are supported by the 82580EB/DB's pre-defined filters:
• Directed packet (including exact, multicast indexed, and broadcast)
• Magic Packet
• ARP/IPv4 request packet
• Directed IPv4 packet
• Directed IPv6 packet
Each of these filters are enabled if the corresponding bit in the Wakeup Filter Control (WUFC) register is
set to 1b.
The explanation of each filter includes a table showing which bytes at which offsets are compared to
determine if the packet passes the filter.
Note:
Both VLAN frames and LLC/SNAP can increase the given offsets if they are present.
5.6.3.1.1
Directed Exact Packet
The 82580EB/DB generates a wake-up event after receiving any packet whose destination address
matches one of the 24 valid programmed receive addresses, if the Directed Exact Wake Up Enable bit is
set in the Wake Up Filter Control (WUFC.EX) register.
5.6.3.1.2
Directed Multicast Packet
For multicast packets, the upper bits of the incoming packet's destination address index a bit vector, the
Multicast Table Array (MTA) that indicates whether to accept the packet. If the Directed Multicast Wake
Up Enable bit set in the Wake Up Filter Control (WUFC.MC) register and the indexed bit in the vector is
one, then the 82580EB/DB generates a wake-up event. The exact bits used in the comparison are
programmed by software in the Multicast Offset field of the Receive Control (RCTL.MO) register.
5.6.3.1.3
Broadcast
If the Broadcast Wake Up Enable bit in the Wake Up Filter Control (WUFC.BC) register is set, the
82580EB/DB generates a wake-up event when it receives a broadcast packet.
Offset
0
# of bytes
6
Field
Destination Address
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Value
FF*6
Action
Comment
Compare
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5.6.3.1.4
Magic Packet
Magic packets are defined in:
http://www.amd.com/us-en/assets/content_type/white_papers_and_tech_docs/20213.pdf as:
Once the LAN controller has been put into the Magic Packet mode, it scans all incoming frames
addressed to the node for a specific data sequence.This sequence indicates to the controller that this is
a Magic Packet frame. A Magic Packet frame must also meet the basic requirements for the LAN
technology chosen, such as SOURCE ADDRESS, DESTINATION ADDRESS (which may be the receiving
station's IEEE address or a MULTICAST address which includes the BROADCAST address), and CRC. The
specific data sequence consists of 16 repetitions of the IEEE address of this node, with no breaks or
interruptions. This sequence can be located anywhere within the packet, but must be preceded by a
synchronization stream. The synchronization stream allows the scanning state machine to be much
simpler. The synchronization stream is defined as 6 bytes of 0xFF. The device will also accept a
BROADCAST frame, as long as the 16 repetitions of the IEEE address match the address of the machine
to be awakened.”
The 82580EB/DB expects the destination address to either:
• Be the broadcast address (FF.FF.FF.FF.FF.FF)
• Match the value in Receive Address 0 (RAH0, RAL0) register. This is initially loaded from the
EEPROM but can be changed by the software device driver.
• Match any other address filtering (RAH[n], RAL[n]) enabled by the software device driver.
The 82580EB/DB searches for the contents of Receive Address 0 (RAH0, RAL0) register as the
embedded IEEE address. It considers any non-0xFF byte after a series of at least 6 0xFFs to be the
start of the IEEE address for comparison purposes. For example, it catches the case of 7 0xFFs followed
by the IEEE address). As soon as one of the first 96 bytes after a string of 0xFFs don't match, it
continues to search for another set of at least 6 0xFFs followed by the 16 copies of the IEEE address
later in the packet. Note that this definition precludes the first byte of the destination address from
being FF.
A Magic Packet's destination address must match the address filtering enabled in the configuration
registers with the exception that broadcast packets are considered to match even if the Broadcast
Accept bit of the Receive Control (RCTL.BAM) register is 0b. If APM wake up (wake up by a Magic
Packet) is enabled in the EEPROM, the 82580EB/DB starts up with the Receive Address 0 (RAH0, RAL0)
register loaded from the EEPROM. This enables the 82580EB/DB to accept packets with the matching
IEEE address before the software device driver loads.
Table 5-6.
Offset
Magic Packet Structure
# of bytes
Field
Value
Action
0
6
Destination Address
Compare
6
6
Source Address
Skip
12
S=(0/4)
Possible VLAN Tag
Skip
12 + S
D=(0/8)
Possible Length + LLC/SNAP
Header
Skip
12 + S + D
2
Type
Any
6
Synchronizing Stream
FF*6+
Compare
any+6
96
16 copies of Node Address
A*16
Compare
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Comment
MAC header – processed by main
address filter.
Skip
Compared to Receive Address 0
(RAH0, RAL0) register.
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5.6.3.1.5
ARP/IPv4 Request Packet
The 82580EB/DB supports receiving ARP request packets for wake up if the ARP bit is set in the Wake
Up Filter Control (WUFC) register. Four IPv4 addresses are supported, which are programmed in the
IPv4 Address Table (IP4AT). A successfully matched packet must contain a broadcast MAC address, a
protocol type of 0x0806, an ARP op-code of 0x01, and one of the four programmed IPv4 addresses. The
82580EB/DB also handles ARP request packets that have VLAN tagging on both Ethernet II and
Ethernet SNAP types.
Table 5-7.
ARP Packet Structure and Processing
Offset
# of bytes
Field
Value
Action
0
6
Destination Address
Compare
6
6
Source Address
Skip
12
S=(0/4)
Possible VLAN Tag
Compare
12 + S
D=(0/8)
Possible Length + LLC/SNAP
Header
Skip
12 + S + D
2
Type
0x0806
Compare
14 + S + D
2
HW Type
0x0001
Compare
16 + S + D
2
Protocol Type
0x0800
Compare
18 + S + D
1
Hardware Size
0x06
Compare
19 + S + D
1
Protocol Address Length
0x04
Compare
20 + S + D
2
Operation
0x0001
Compare
22 + S + D
6
Sender HW Address
-
Ignore
28 + S + D
4
Sender IP Address
-
Ignore
32 + S + D
6
Target HW Address
-
Ignore
38 + S + D
4
Target IP Address
IP4AT
Compare
Comment
MAC header – processed by main
address filter.
Processed by main address filter.
ARP
Compare if the Directed ARP bit is
set to 1b.
May match any of four values in
IP4AT.
5.6.3.1.6
Directed Ipv4 Packet
The 82580EB/DB supports receiving directed IPv4 packets for wake up if the IPV4 bit is set in the Wake
Up Filter Control (WUFC) register. Four IPv4 addresses are supported, which are programmed in the
IPv4 Address Table (IP4AT). A successfully matched packet must contain the station's MAC address, a
protocol type of 0x0800, and one of the four programmed IPv4 addresses. The 82580EB/DB also
handles directed IPv4 packets that have VLAN tagging on both Ethernet II and Ethernet SNAP types.
Table 5-8.
Offset
IPv4 Packet Structure and Processing
# of bytes
Field
Value
Action
Comment
0
6
Destination Address
Compare
6
6
Source Address
Skip
12
S=(0/4)
Possible VLAN Tag
Compare
12 + S
D=(0/8)
Possible Length + LLC/SNAP
Header
Skip
12 + S + D
2
Type
0x0800
Compare
IP
14 + S + D
1
Version/ HDR length
0x4X
Compare
Check IPv4
15 + S + D
1
Type of Service
-
Ignore
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MAC header – processed by main
address filter.
Processed by main address filter.
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Wake-Up Packets — Intel® 82580EB/82580DB GbE Controller
Table 5-8.
Offset
IPv4 Packet Structure and Processing (Continued)
# of bytes
Field
Value
Action
16 + S + D
2
Packet Length
-
Ignore
18 + S + D
2
Identification
-
Ignore
20 + S + D
2
Fragment Info
-
Ignore
22 + S + D
1
Time to live
-
Ignore
23 + S + D
1
Protocol
-
Ignore
24 + S + D
2
Header Checksum
-
Ignore
26 + S + D
4
Source IP Address
-
Ignore
30 + S + D
4
Destination IP Address
IP4AT
Compare
5.6.3.1.7
Comment
May match any of four values in IP4AT.
Directed IPv6 Packet
The 82580EB/DB supports receiving directed IPv6 packets for wake up if the IPV6 bit is set in the Wake
Up Filter Control (WUFC) register. One IPv6 address is supported and is programmed in the IPv6
Address Table (IP6AT). A successfully matched packet must contain the station's MAC address, a
protocol type of 0x86DD, and the programmed IPv6 address. In addition, the IPAV.V60 bit should be
set. The 82580EB/DB also handles directed IPv6 packets that have VLAN tagging on both Ethernet II
and Ethernet SNAP types.
Table 5-9.
IPv6 Packet Structure and Processing
Offset
# of bytes
Field
Value
Action
Comment
0
6
Destination Address
Compare
6
6
Source Address
Skip
12
S=(0/4)
Possible VLAN Tag
Compare
12+ S
D=(0/8)
Possible Length + LLC/SNAP
Header
Skip
12 + S + D
2
Type
0x86DD
Compare
IP
14 + S + D
1
Version/ Priority
0x6X
Compare
Check IPv6
15 + S + D
3
Flow Label
-
Ignore
18 + S + D
2
Payload Length
-
Ignore
20 + S + D
1
Next Header
-
Ignore
21 + S + D
1
Hop Limit
-
Ignore
22 + S + D
16
Source IP Address
-
Ignore
38 + S + D
16
Destination IP Address
IP6AT
Compare
5.6.3.2
MAC header – processed
by main address filter.
Processed by main
address filter.
Match value in IP6AT.
Flexible Filters
The 82580EB/DB supports a total of 8 flexible filters. Each filter can be configured to recognize any
arbitrary pattern within the first 128 bytes of the packet. To configure the flexible filters, software
programs the mask values (required values and the minimum packet length), into the Flexible Host
Filter Table (FHFT and FHFT_EXT). These 8 flexible filters contain separate values for each filter.
Software must also enable the filters in the Wake Up Filter Control (WUFC) register, and enable the
overall wake up functionality. The overall wake up functionality must be enabled by setting PME_En in
the PMCSR or the Wake Up Control (WUC) register.
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Intel® 82580EB/82580DB GbE Controller — Wake-Up Packets
Once enabled, the flexible filters scan incoming packets for a match. If the filter encounters any byte in
the packet where the mask bit is one and the byte doesn't match the value programmed in the Flexible
Host Filter Table (FHFT or FHFT_EXT), then the filter fails that packet. If the filter reaches the required
length without failing the packet, it passes the packet and generates a wake-up event. It ignores any
mask bits set to one beyond the required length.
Note:
The flex filters are temporarily disabled when read from or written to by the host. Any
packet received during a read or write operation is dropped. Filter operation resumes once
the read or write access completes.
The following packets are listed for reference purposes only. The flexible filter could be used to filter
these packets.
5.6.3.2.1
IPX Diagnostic Responder Request Packet
An IPX diagnostic responder request packet must contain a valid MAC address, a protocol type of
0x8137, and an IPX diagnostic socket of 0x0456. It might include LLC/SNAP headers and VLAN tags.
Since filtering this packet relies on the flexible filters, which use offsets specified by the operating
system directly, the operating system must account for the extra offset LLC/SNAP headers and VLAN
tags.
Table 5-10.
IPX Diagnostic Responder Request Packet Structure and Processing
Offset
# of bytes
Field
Value
Action
0
6
Destination Address
Compare
6
6
Source Address
Skip
12
S=(0/4)
Possible VLAN Tag
Skip
12+ S
D=(0/8)
Possible Length + LLC/SNAP
Header
Skip
12 + S + D
2
Type
0x8137
Compare
14 + S + D
16
Some IPX Stuff
-
Ignore
30 + S + D
2
IPX Diagnostic Socket
0x0456
Compare
5.6.3.2.2
Comment
IPX
Directed IPX Packet
A valid directed IPX packet contains the station's MAC address, a protocol type of 0x8137, and an IPX
node address that is equal to the station's MAC address. It might include LLC/SNAP headers and VLAN
tags. Since filtering this packet relies on the flexible filters, which use offsets specified by the operating
system directly, the operating system must account for the extra offset LLC/SNAP headers and VLAN
tags.
Table 5-11.
Offset
IPX Packet Structure and Processing
# of bytes
Field
Value
Action
0
6
Destination Address
Compare
6
6
Source Address
Skip
12
S=(0/4)
Possible VLAN Tag
Skip
12+ S
D=(0/8)
Possible Length + LLC/SNAP
Header
Skip
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Comment
MAC header – processed by
main address filter.
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DMA Coalescing — Intel® 82580EB/82580DB GbE Controller
Table 5-11.
IPX Packet Structure and Processing
12 + S + D
2
Type
0x8137
Compare
14 + S + D
10
Some IPX Info
-
Ignore
24 + S + D
6
IPX Node Address
Receive
Address 0
Compare
5.6.3.2.3
IPX
Must match receive address
0.
IPv6 Neighbor Discovery Filter
In IPv6, a neighbor discovery packet is used for address resolution. A flexible filter can be used to check
for a neighborhood discovery packet.
5.6.3.2.4
Utilizing Flex Wake-Up Filters In Normal Operation
The 82580EB/DB enables utilizing the WoL Flex filters in normal operation, when in D0 power
management state, for queuing decisions. Further information can be found in Section 8.1.1.6.
5.6.3.3
Wake Up Packet Storage
The 82580EB/DB saves the first 128 bytes of the wake-up packet in its internal buffer, which can be
read through the Wake Up Packet Memory (WUPM) register after the system wakes up.
5.7
DMA Coalescing
The 82580EB/DB supports DMA Coalescing to enable synchronizing port activity and optimize power
management of memory, CPU and RC internal circuitry.
To activate DMA coalescing functionality software driver should program the following fields:
1. DMACR.DMACTHR field to set the receive threshold that causes move out of DMA Coalescing
operating mode. Receive watermark programmed should take into account latency tolerance
reported (See Section 5.8) and L1 to L0 latency to avoid Receive Buffer overflow when DMA
Coalescing is enabled.
2. DMCTXTH.DMCTTHR field to set transmit threshold that causes move out of DMA Coalescing
operating mode. Transmit watermark programmed should take into account latency tolerance
reported (See Section 5.8) and L1 to L0 latency to allow transmission of back to back packets when
DMA Coalescing is enabled.
3. DMACR.DMACWT field defines a maximum time for a receive packet to be stored in the internal
receive buffer before the 82580EB/DB moves packet to Host memory, even if the DMACR.DMACTHR
watermark is not passed.
4. DMCTLX.TTLX timer field to define, the time between detection of DMA idle status to actual move
into low power link state (L0s or L1). Value programmed in this register reduces amount of entries
into low power PCIe link state when traffic rate is high.
5. DMCRTRH.UTRESH low rate threshold field to define the upper limit to data arrival rate, were DMA
coalescing is not entered. This field avoids moving into DMA coalescing mode when traffic is sparse
and effectiveness of DMA coalescing on system power saving is limited. The time interval were data
rate is measured is defined by the Storm Control SCCRL.INTERVAL field that uses the time units
defined in the SCBI register (See Section 8.8.2.8.3.2 for description of how to set the time interval
for rate measurement).
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Intel® 82580EB/82580DB GbE Controller — Entering DMA Coalescing Operating Mode
6. FCRTC.RTH_Coal field that defines a flow control receive high watermark for sending flow control
packets. The 82580EB/DB uses the FCRTC.RTH_Coal threshold when:
— Flow control is enabled by setting the CTRL.RFCE bit.
— The 82580EB/DB is in DMA Coalescing mode.
— Internal transmit buffer is empty.
7. SRRCTL[n].DMACQ_Dis bit to define high priority queues. When a received packet is forwarded to a
queue with the SRRCTL[n].DMACQ_Dis bit set, the 82580EB/DB moves immediately out of Buffer
Fill mode and executes a DMA operation to store the packet in host memory.
8. DMACR.DMAC_EN bit should be set to 1 to enable activation of DMA Coalescing operating mode.
9. DMACR.DMAC_Lx to 10b to define that L1 low power PCIe link state is entered in DMA Coalescing
operation .
Note:
The values of DMACR.DMACTHR and FCRTC.RTH_Coal should be set so that XOFF packet
generation is avoided. In DMA Coalescing mode, when transmit buffer is empty, the XOFF
flow control threshold (FCRTC.RTH_Coal) value can be increased by maximum jumbo frame
size compared to normal operation, were high threshold is set by the FCRTH0 register.
When entering DMA coalescing mode, the value written in the FCRTH0 register is used to
generate XOFF flow control frames until the internal transmit buffer is empty. Once the
internal transmit buffer is empty the value written in the FCRTC.RTH_Coal field is used as a
watermark for generation of XOFF frames.
5.7.1
Entering DMA Coalescing Operating Mode
Enabling DMA Coalescing operation by setting the DMACR.DMAC_EN bit to 1, enables alignment of bus
master traffic and interrupts from all ports. Power saving is achieved since synchronizing PCIe accesses
between ports increases the occurrence of idle intervals on the PCIe bus and also increases the duration
of these idle intervals. Power Management Unit on platform can utilize these Idle intervals to reduce
system power.
5.7.1.1
Conditions to Enter DMA Coalescing
The 82580EB/DB enters DMA Coalescing state, were access to the PCIe bus is delayed and received
packets are buffered in internal receive memory until appropriate conditions occur, when all of the
following conditions exist:
• Internal receive buffers are empty.
• There are no pending DMA operations.
• None of the conditions defined in Section 5.7.2 to move out of DMA Coalescing exist.
Before entering the DMA coalescing power saving mode, the 82580EB/DB will:
• Flush all pending interrupts that were delayed due to the Interrupt Throttling (ITR) mechanism.
• The 82580EB/DB will flush all pending receive descriptor write backs and pre-fetch available receive
descriptors to internal cache.
Note:
The 82580EB/DB enters DMA Coalescing mode only when above conditions exist on all
active functions.
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Conditions to Exit DMA Coalescing — Intel® 82580EB/82580DB GbE Controller
5.7.2
Conditions to Exit DMA Coalescing
When in DMA Coalescing operating mode, PCIe link is placed in a link state as defined in the
DMACR.DMAC_Lx field and no PCIe activity is initiated by the 82580EB/DB. In this mode generation of
flow control packets is defined by the FCRTC.RTH_Coal threshold field. DMA Coalescing mode is exited
when one of the following events occur:
1. PCIe link is active (L0 link power state).
2. Amount of data in internal receive buffers passed the DMACR.DMACTHR threshold.
3. Empty space in internal transmit buffer is above the value defined in DMCTXTH.DMCTTHR field and
available transmit descriptors exist.
4. A high priority packet was received (See Section 8.3.6 for definition of high priority packets). A high
priority packet is defined as packet that generates an immediate interrupt when received.
5. A received packet destined to a high priority queue (SRRCTL[n].DMACQ_Dis =1b) was detected.
6. An Interrupt is pending (Link disconnect, TCP timer …).
7. DMA coalescing Watchdog timer defined in the DMACR.DMACWT field expires as a result of a
received packet not being serviced for a long duration.
8. Packet rate lower than defined in DMCRTRH.UTRESH field is detected.
9. DMA Coalescing is disabled (DMACR.DMAC_EN = 0).
10. Another the 82580EB/DB function initiated a transaction on the PCIe bus.
Note:
5.8
Even when conditions for DMA Coalescing do not exist, the 82580EB/DB will continue to be
in low power PCIe link state (L0s or L1) if there is no requirement for PCIe access.
Latency Tolerance Reporting (LTR)
The 82580EB/DB generates PCIe LTR messages to report service latency requirements for memory
reads and writes to the Root Complex for system power management.
The 82580EB/DB will report either minimum latency tolerance, maximum latency tolerance or no
latency tolerance requirements as a function of link, LAN port and function status. Minimum and
maximum latency tolerance values are programmed in the LTRMINV and LTRMAXV registers
respectively by the software driver to optimize power consumption without incurring packet loss due to
receive buffer overflow. The 82580EB/DB sends LTR messages according to the following algorithm
when the capability is enabled:
1. When Links on all ports are disconnected or all LAN ports are disabled (transmit and receive activity
not enabled) and the LTRC.LNKDLS_EN and LTRC.PDLS_EN bits are set respectively, the 82580EB/
DB will send a LTR PCIe message with LTR Requirement bits cleared, to indicate that no Latency
tolerance requirements exists.
2. When software sets LTRC.LTR_MAX, the 82580EB/DB will send a LTR message with the value
placed in the LTRMAXV register.
3. Otherwise, the 82580EB/DB will send a LTR message with a minimum value.
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Intel® 82580EB/82580DB GbE Controller — Latency Tolerance Reporting (LTR)
Note:
In all cases maximum LTR Value sent by the 82580EB/DB do not exceed the maximum
latency values in the Max No-Snoop Latency and Max Snoop Latency Registers in the
Latency Tolerance Reporting (LTR) Capability structure of Function 0.
Figure 5-7 describes the 82580EB/DB LTR message generation flow.
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Latency Tolerance Reporting (LTR) — Intel® 82580EB/82580DB GbE Controller
Figure 5-7.
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PCIe LTR Message Generation Flow per Function
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Intel® 82580EB/82580DB GbE Controller — Latency Tolerance Reporting Per Function
5.8.1
Latency Tolerance Reporting Per Function
Internal to the 82580EB/DB each function can request to generate a Minimum value LTR, a Maximum
value LTR and a LTR message with the Requirement bits cleared. The 82580EB/DB conglomerates
latency requirements from the functions that have LTR messaging enabled and sends a single LTR
message in the following manner:
• The acceptable latency values for the message sent upstream by the 82580EB/DB must reflect the
lowest latency tolerance values associated with any function.
— It is permitted that the Snooped and Non-Snooped values reported in the conglomerated
message are associated with different functions.
— If none of the functions have a Latency requirement for a certain type of traffic (Snoop/Nonsnoop), the message sent by the 82580EB/DB will not have the Requirement bit corresponding
to that type of traffic set.
• The 82580EB/DB transmits a new LTR message upstream when the capability is enabled and when
any function changes the values it has reported internally in such a way as to change the
conglomerated value reported previously by the 82580EB/DB.
Each function in the 82580EB/DB reports support of LTR messaging in the configuration space by:
• Setting the LTR Mechanism Supported bit in the PCIe Device Capabilities 2 configuration register
(Support defined by LTR_EN bit in Initialization Control Word 1 EEPROM word, that controls
enabling of the LTR structures).
• Supporting the Latency Tolerance Requirement Reporting (LTR) Capability structure in the PCIe
configuration space.
To enable generation of LTR messages by a function the LTR Mechanism Enable bit in the Device Control
2 configuration register of function 0 should be set.
Note:
5.8.1.1
A function that does not have LTR messaging enabled is considered a function that does not
have any Latency Tolerance requirements.
Conditions for Generating LTR Message with the
Requirement Bits Cleared
When LTR messaging is enabled the 82580EB/DB functions will send a LTR message with the
Requirement bits cleared in the following cases:
1. Following PE_RST_N assertion (PCIe reset) after LTR capability is enabled.
2. LAN port is disabled (both RCTRL.RXEN and TCTL.EN are cleared), receive buffer is empty and
LTRC.PDLS_EN is set.
3. LAN port is disconnected, BMC to Host traffic is disabled (MANC.EN_BMC2HOST = 0) and
LTRC.LNKDLS_EN is set.
4. Function is not in D0a state.
5. When the LSNP and LNSNP bits are cleared in the LTRMINV register and minimum LTR value needs
to be sent.
6. When the LSNP and LNSNP bits are cleared in the LTRMAXV register and maximum LTR value needs
to be sent.
Note:
A disabled function does not generate Latency Tolerance requirements.
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Latency Tolerance Reporting Per Function — Intel® 82580EB/82580DB GbE Controller
5.8.1.2
Conditions for Generating LTR Message with Maximum LTR
Value
When LTR messaging is enabled and conditions to send LTR Message with Valid bits cleared do not
exist, the 82580EB/DB functions will send a maximum value LTR message, with the values
programmed in the LTRMAXV register in the following cases:
1. Following a software write 1 operation to LTRC.LTR_MAX bit.
2. When updated data was written to the LTRMAXV register and condition defined in 1. to send a LTR
message with a maximum value exists.
Note:
5.8.1.3
When the LTRC.LTR_MAX bit is cleared, the 82580EB/DB will send a LTR message with the
value placed in the LTRMINV register, if the value is smaller than the value placed in the
LTRMAXV register.
Conditions for Generating LTR Message with Minimum LTR
Value
When LTR messaging is enabled, the 82580EB/DB functions will send a minimum value LTR message,
with the values programmed in the LTRMINV register in the following cases:
1. Following a software write 1 operation to the LTRC.LTR_MIN bit.
2. When updated data was written to the LTRMINV register and conditions to send LTR message with
Valid bits cleared or maximum value LTR do not exist.
§§
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Intel® 82580EB/82580DB GbE Controller — Latency Tolerance Reporting Per Function
NOTE:
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Non-Volatile Memory Map - EEPROM — Intel® 82580EB/82580DB GbE Controller
6.0
Non-Volatile Memory Map - EEPROM
6.1
EEPROM General Map
The 82580EB/DB EEPROM is partitioned into 4 main blocks followed by Firmware and PXE structures.
First 128 word section is allocated to words common to all LAN ports, Firmware, Software, PXE and LAN
port 0. Following 64 word sections are allocated to Lan port 1, Lan port 2 and Lan port 3 as shown in
Table 6-1.
A detailed list of EEPROM words loaded by Hardware following Power-up, Hardware reset or software
generated resets (CTRL.RST, CTRL_EXT.EE_RST or CTRL.DEV_RST) can be found in the auto load
sequence table in Section 3.3.1.3.
Table 6-1.
EEPROM Top Level Partitioning
EEPROM Word
Offsets
Partition
0x00 to 0x7F
Common Words (PCIe, PXE, SW and FW) and LAN port 0 words - see Table 6-2
0x80 to 0xBF
LAN Port 1 words - see Table 6-3
0xC0 to 0xFF
LAN Port 2 words* - see Table 6-3
0x100 to 0x13F
LAN Port 3 words* - see Table 6-3
0x140...
PXE and Firmware Structures
* Ignored on the dual port 82580DB.
Table 6-2 lists the 82580EB/DB EEPROM word map for Common words and Lan Port 0.
Table 6-2.
EEPROM Word
Offsets
Common and Lan Port 0 EEPROM Map
Used By/In
0x00:0x02
HW
0x03
SW
High Byte
Low Byte
Section 6.2.1, Ethernet Address (LAN Base Address + Offsets 0x00-0x02)
Section 6.11.1, Compatibility (Word 0x03)
Which LAN
LAN 0
All
0x04
SW
0x05
SW
Comatibility High
Compatibility Low
All
0x06
SW
Compatibility High
Compatibility Low
All
0x07
SW
Compatibility High
Compatibility Low
All
0x08
SW
0x09
SW
0x0A
HW
Section 6.2.2, Initialization Control Word 1 (word 0x0A)
All
0x0B
HW
Section 6.2.3, Subsystem ID (Word 0x0B)
All
0x0C
HW
Section 6.2.4, Subsystem Vendor ID (Word 0x0C)
0x0D
HW
Section 6.2.5, Device ID (LAN Base Address + Offset 0x0D)
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All
Section 6.11.5, PBA Number Module (Word 0x08, 0x09)
All
All
All
LAN 0
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Intel® 82580EB/82580DB GbE Controller — EEPROM General Map
Table 6-2.
EEPROM Word
Offsets
0x0E
Common and Lan Port 0 EEPROM Map (Continued)
Used By/In
High Byte
Low Byte
Which LAN
HW
Section 6.2.4, Subsystem Vendor ID (Word 0x0C)
All
0x0F
HW
Section 6.2.8, Initialization Control Word 2 (Word 0x0F)
All
0x10
HW
Reserved
0x11
HW (MNG HW)
Section 6.6.1, Pass Through LAN Configuration Pointer (LAN Base Address +
Offset 0x11)
0x12
HW
Section 6.2.9, EEPROM Sizing and Protected Fields (Word 0x12)
0x13
HW
Section 6.2.10, Initialization Control 4 (LAN Base Address + Offset 0x13)
0x14
HW
Section 6.2.11, PCIe L1 Exit latencies (Word 0x14)
0x15
HW
Section 6.2.12, PCIe Completion Timeout Configuration (Word 0x15)
0x16
HW
Section 6.2.13, MSI-X Configuration (LAN Base Address + Offset 0x16)
LAN 0
0x17
HW
Section 6.3, CSR Auto Configuration Pointer (LAN Base Address + Offset 0x17)
LAN 0
0x18
HW
Reserved
All
0x19
HW
Section 6.2.15, PCIe Init Configuration 2 Word (Word 0x19)
All
0x1A
HW
Section 6.2.16, PCIe Init Configuration 3 Word (Word 0x1A)
All
0x1B
HW
Section 6.2.17, PCIe Control 1 (Word 0x1B)
0x1C
HW
Section 6.2.18, LED 1,3 Configuration Defaults (LAN Base Address + Offset
0x1C)
0x1D
HW
Section 6.2.7, Dummy Device ID (Word 0x1D)
All
0x1E
HW
Section 6.2.19, Device Rev ID (Word 0x1E)
All
0x1F
HW
Section 6.2.20, LED 0,2 Configuration Defaults (LAN Base Address + Offset
0x1F)
LAN 0
0x20
HW
Section 6.2.21, Software Defined Pins Control (LAN Base Address + Offset
0x20)
LAN 0
0x21
HW
Section 6.2.22, Functions Control (Word 0x21)
All
0x22
HW
Section 6.2.23, LAN Power Consumption (Word 0x22)
All
0x23
HW
Section 6.6.2, Management HW Config Control (Word 0x23)
0x24
HW
Section 6.2.24, Initialization Control 3 (LAN Base Address + Offset 0x24)
0x25
HW
Reserved
0x26
HW
Reserved
0x27
HW
Reserved
LAN0
0x27
HW
Section 6.4, CSR Auto Configuration Power-Up Pointer (LAN Base Address +
Offset 0x27)
LAN0
0x28
HW
Section 6.2.25, PCIe Control 2 (Word 0x28)
All
0x29
HW
Section 6.2.26, PCIe Control 3 (Word 0x29)
All
0x2A
HW
Reserved
All
0x2B
HW
Reserved
All
0x2C
HW
Reserved
All
0x2D
HW
Section 6.2.28, Start of RO Area (Word 0x2D)
All
All
0x2E
HW
Section 6.2.29, Watchdog Configuration (Word 0x2E)
0x2F
OEM
Section 6.2.30, VPD Pointer (Word 0x2F)
0x30
PXE
Section 6.11.6.1, Setup Options PCI Function 0 (Word 0x30)
0x31
PXE
Section 6.11.6.2, Configuration Customization Options PCI Function 0 (Word
0x31)
0x32
PXE
Section 6.11.6.3, PXE Version (Word 0x32)
0x33
PXE
Section 6.11.6.4, IBA Capabilities (Word 0x33)
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All
LAN 0 (MNG
HW)
All
LAN 0
All
All
All
LAN 0
MNG HW
LAN 0
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EEPROM General Map — Intel® 82580EB/82580DB GbE Controller
Table 6-2.
EEPROM Word
Offsets
Common and Lan Port 0 EEPROM Map (Continued)
Used By/In
High Byte
Low Byte
0x34
PXE
Section 6.11.6.5, Setup Options PCI Function 1 (Word 0x34)
0x35
PXE
Section 6.11.6.6, Configuration Customization Options PCI Function 1 (Word
0x35)
0x38
PXE
Section 6.11.6.7, Setup Options PCI Function 2 (Word 0x38)
0x39
PXE
Section 6.11.6.8, Configuration Customization Options PCI Function 2 (Word
0x39)
0x3A
PXE
Section 6.11.6.9, Setup Options PCI Function 3 (Word 0x3A)
0x3B
PXE
Section 6.11.6.10, Configuration Customization Options PCI Function 3 (Word
0x3B)
0x3D
PXE
Section 6.11.7, iSCSI Boot Configuration Pointer (Word 0x3D)
0x3E
PXE
Reserved
0x3F
SW
Section 6.11.9, Checksum Word (Offset 0x3F)
0x40:0x41
SW
Reserved
0x42
SW
Section 6.11.10, Image Unique ID (Word 0x42, 0x43)
0x43
SW
Section 6.11.10, Image Unique ID (Word 0x42, 0x43)
0x44:0x4F
SW
Reserved
0x50
FW
Section 6.6.3, PHY Configuration Pointer (Word 0x50)
0x51
FW
Section 6.6.4, Firmware Patch Pointer (Word 0x51)
0x52:0x53
FW
Reserved
0x54
FW
Section 6.7, Firmware Patch Structure
Which LAN
MNG
MNG Code
MNG
MNG HW
0x55:0x56
FW
Reserved
0x57
FW
Section 6.6.6, Sideband Configuration Pointer (Word 0x57)
MNG
MNG HW
0x58:0x5D
FW
Reserved
MNG
0x5E
FW
Reserved
MNG
0x5F:0x7F
FW
Reserved
MNG
0x80:0xBF
LAN Port 1 words - see Table 6-3
0xC0:0xFF
LAN Port 2 words - see Table 6-3
0x100:0x13F
LAN Port 3 words - see Table 6-3
0x140...
PXE and Firmware Structures
Table 6-3 maps the 82580EB/DB EEPROM words that can hold different content for LAN Ports 0, 1, 2
and 3. Addresses listed in the table are an offset from the LAN Base address of the relevant EEPROM
LAN section. EEPROM LAN Base addresses of the LAN ports are as follows:
• LAN Port 0 EEPROM section Base Address - 0x0
• LAN Port 1 EEPROM section Base Address – 0x80
• LAN Port 2 EEPROM section Base Address – 0xC0
• LAN Port 3 EEPROM section Base Address – 0x100
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Intel® 82580EB/82580DB GbE Controller — Hardware Accessed Words
Table 6-3.
LAN Ports 1, 2 and 3 EEPROM Map
EEPROM Word
Offsets
Used By/In
High Byte
0x00:0x02
HW
0x03:0x0C
HW
Reserved
0x0D
HW
Section 6.2.5, Device ID (LAN Base Address + Offset 0x0D)
Low Byte
Section 6.2.1, Ethernet Address (LAN Base Address + Offsets 0x00-0x02)
0x0E:0x10
HW
Reserved
0x11
HW (MNG HW)
Section 6.6.1, Pass Through LAN Configuration Pointer (LAN Base Address + Offset 0x11)
0x12
HW
Reserved
0x13
HW
Section 6.2.10, Initialization Control 4 (LAN Base Address + Offset 0x13)
0x14:0x15
HW
Reserved
0x16
HW
Section 6.2.13, MSI-X Configuration (LAN Base Address + Offset 0x16)
0x17
HW
Section 6.3, CSR Auto Configuration Pointer (LAN Base Address + Offset 0x17)
0x18:0x1B
HW
Reserved
0x1C
HW
Section 6.2.18, LED 1,3 Configuration Defaults (LAN Base Address + Offset 0x1C)
0x1D:0x1E
HW
Reserved
0x1F
HW
Section 6.2.20, LED 0,2 Configuration Defaults (LAN Base Address + Offset 0x1F)
0x20
HW
Section 6.2.21, Software Defined Pins Control (LAN Base Address + Offset 0x20)
0x21:0x23
HW
Reserved
0x24
HW
Section 6.2.24, Initialization Control 3 (LAN Base Address + Offset 0x24)
0x25:0x26
HW
Reserved
0x27
HW
Section 6.4, CSR Auto Configuration Power-Up Pointer (LAN Base Address + Offset 0x27)
0x28:0x3E
HW
Reserved
0x3F
SW
Section 6.11.9, Checksum Word (Offset 0x3F)
6.2
Hardware Accessed Words
This section describes the EEPROM words that are loaded by 82580EB/DB hardware. Most of these bits
are located in configuration registers. The words are only read and used if the signature field in the
EEPROM Sizing & Protected Fields EEPROM word (word 0x12) is valid.
Note:
6.2.1
When Word is mentioned before an EEPROM address, address is the absolute address in
the EEPROM. When Offset is mentioned before an EEPROM address, the address is relative
to the start of the relevant EEPROM section.
Ethernet Address (LAN Base Address + Offsets 0x000x02)
The Ethernet Individual Address (IA) is a 6-byte field that must be unique for each NIC, and thus
unique for each copy of the EEPROM image. The first three bytes are vendor specific. The value from
this field is loaded into the Receive Address Register 0 (RAL0/RAH0).
The Ethernet address is loaded for LAN0 from Addresses 0x0 to 0x02 and for LAN 1, 2 and 3 from
offsets 0x0 to 0x2 at the start of the relevant sections.
Following table depicts mapping of the Ethernet MAC addresses to the EEPROM words.
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Initialization Control Word 1 (word 0x0A) — Intel® 82580EB/82580DB GbE Controller
LAN Port
MAC Address
LAN Base Address + 0x00
LAN Base Address + 0x01
LAN Base Address + 0x02
0
00-A0-C9-00-00-00
0xA000
0x00C9
0x0000
1
00-A0-C9-00-00-01
0xA000
0x00C9
0x0100
2
00-A0-C9-00-00-02
0xA000
0x00C9
0x0200
3
00-A0-C9-00-00-03
0xA000
0x00C9
0x0300
6.2.2
Initialization Control Word 1 (word 0x0A)
The Initialization Control Word 1 in the Common section contains initialization values that:
• Set defaults for some internal registers
• Enable/disable specific features
• Determine which PCI configuration space values are loaded from the EEPROM
Bit
Name
15:14
Reserved
13
LTR_EN
Default in EEPROMless mode
Description
Reserved
1b
LTR capabilities reporting enable.
0 - Do not report LTR support in the PCIe configuration Device
Capabilities 2 register.
1 - Report LTR support in the PCIe configuration Device Capabilities 2
register.
Defines default setting of LTR capabilities reporting (See
Section 9.5.6.11).
12
Reserved
11
FRCSPD
0b
Reserved
Default setting for the Force Speed bit in the Device Control register
(CTRL[11]). See See Section 7.2.1
10
FD
0b
Default setting for duplex setting. Mapped to CTRL[0]. See See Section
7.2.1
9:7
Reserved
6
SDP_IDDQ_EN
0b
When set, SDP IOs keep their value and direction when the 82580EB/
DB enters dynamic IDDQ mode either due to PCIe entering Dr state or
DEV_OFF_N pin being asserted. Otherwise, SDP IOs moves to HighZ +
pull-up mode in dynamic IDDQ mode.
5
Deadlock Timeout
Enable
1b
If set, a device granted access to the EEPROM or Flash that does not
toggle the interface for more than 2 seconds will have the request
cleared and the grant revoked. See Section 3.3.2.1.
4
Reserved
0b
Reserved.
3
Power Management
1b
0b = Power Management registers set to read only. In this mode, the
82580EB/DB does not execute a hardware transition to D3 .Reserved
Reserved.
Value should be 110b.
1b = Full support for power management (For normal operation, this bit
must be set to 1b).
See Section 9.5.1 .
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Intel® 82580EB/82580DB GbE Controller — Subsystem ID (Word 0x0B)
Bit
Name
Default in EEPROMless mode
Description
2
Reserved
1
Load Subsystem IDs
1b
When this bit is set to 1b the 82580EB/DB loads its PCIe Subsystem ID
and Subsystem Vendor ID from the EEPROM (Subsystem ID and
Subsystem Vendor ID EEPROM words).
0
Load Vendor/Device
IDs
1b
When set to 1b the 82580EB/DB loads its PCIe Device IDs from the
EEPROM (Device ID or Dummy Device ID EEPROM words) and the PCIe
Vendor ID from the EEPROM.
6.2.3
Reserved
Subsystem ID (Word 0x0B)
If the Load Subsystem IDs in Initialization Control Word 1 EEPROM word is set, the Subsystem ID word
in the Common section is read in to initialize the PCIe Subsystem ID. Default value is 0x0 (See
Section 9.4.14).
6.2.4
Subsystem Vendor ID (Word 0x0C)
If the Load Subsystem IDs bit in Initialization Control Word 1 EEPROM word is set, the Subsystem
Vendor ID word in the Common section is read in to initialize the PCIe Subsystem Vendor ID. The
default value is 0x8086 (See Section 9.4.13).
6.2.5
Device ID (LAN Base Address + Offset 0x0D)
If the Load Vendor/Device IDs bit in Initialization Control Word 1 is set, the Device ID EEPROM word is
read in from the Common, LAN 1, LAN 2 and LAN 3 sections to initialize the Device ID of LAN0, LAN1,
LAN2 and LAN3 functions, respectively. The default value is 0x1509 (See Section 9.4.2).
6.2.6
Vendor ID (Word 0x0E)
If the Load Vendor/Device IDs bit in Initialization Control Word 1 EEPROM word is set, this word is read
in to initialize the PCIe Vendor ID. The default value is 0x8086 (See Section 9.4.1).
Note:
6.2.7
If a value of 0xFFFF is placed in the Vendor ID EEPROM word, the value in the PCIe Vendor
ID register will return to the default 0x8086 value. This functionality is implemented to
avoid a system hang situation.
Dummy Device ID (Word 0x1D)
If the Load Vendor/Device IDs bit in Initialization Control Word 1 EEPROM word is set, this word is read
in to initialize the Device ID of dummy devices. The default value is 0x10A6 (See Section 9.4.2).
6.2.8
Initialization Control Word 2 (Word 0x0F)
The Initialization Control Word 2 read by the 82580EB/DB, contains additional initialization values that:
• Set defaults for some internal registers
• Enable/disable specific features
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EEPROM Sizing and Protected Fields (Word 0x12) — Intel® 82580EB/82580DB GbE Controller
Bit
Name
Default in
EEPROM-less
mode
Description
15
APM PME# Enable
0b
Initial value of the Assert PME On APM Wakeup bit in the Wake Up Control
(WUC.APMPME) register. See Section 7.21.1.
14
PCS parallel detect
1b
Enables PCS parallel detect. Mapped to PCS_LCTL.AN TIMEOUT EN bit. See See
Section 7.18.2 .
Note: Bit should be 0b only when port operates in SGMII mode
(CTRL_EXT.LINK_MODE = 10b).
13:12
Pause Capability
11b
11
ANE
0b
Desired pause capability for advertised configuration base page. Mapped to
PCS_ANADV.ASM. See Section 7.18.4.
Auto-Negotiation Enable
Mapped to PCS_LCTL.AN_ENABLE. See See Section 7.18.2 .
Note: Bit should be 0b only when port operates in internal copper PHY mode
(CTRL_EXT.LINK_MODE = 00b).
10:8
Flash Size
000b
Indicates Flash size according to the following equation:
Size = 64 KB * 2**(Flash Size field). From 64 KB up to 8 MB in powers of 2.
The Flash size impacts the requested memory space for the Flash and expansion
ROM BARs in PCIe configuration space (See CSRSize and FLSize fields in the
BARCTRL register in Section 7.6.12).
Note: When CSR_Size and Flash_size fields in the EEPROM are set to 0, Flash
access BAR in the PCI configuration space is disabled.
7
MAC clock gating
enable
1b
Enables MAC clock gating power saving mode. Mapped to STATUS[31]. This bit
is relevant only if the Enable Dynamic MAC Clock Gating bit is set. See
Section 7.2.2.
6
PHY Power Down
Enable
1b
When set, enables the Internal PHY to enter a low-power state (See
Section 3.5.7.5). This bit is mapped to CTRL_EXT[20] (See Section 7.2.3).
5
CSR_Size
0b
The CSR_Size and FLASH_Size fields define the usable FLASH size and CSR
mapping window size as shown in BARCTRL register description (See
Section 7.6.12).
Note: When CSR_Size and Flash_size fields in the EEPROM are set to 0, Flash
access BAR in the PCI configuration space is disabled.
4
LAN PLL Shutdown
Enable
0b
When set, enables shutting down the PHY PLL in low-power states when the
Internal PHY is powered down (such as link disconnect). When cleared, the PHY
PLL is not shut down in a low-power state..
3
Enable Dynamic
MAC Clock Gating
0b
When set, enables dynamic MAC clock gating mechanism. See Section 7.2.3.
2
SerDes Low Power
Enable
0b
When set, enables the SerDes to enter a low power state when the function is in
Dr state. See Chapter 5.0 and Section 7.2.3.
1
DMA clock gating
Disabled
1b
When set Disables DMA clock gating power saving mode.
0
Reserved
6.2.9
Reserved
EEPROM Sizing and Protected Fields (Word 0x12)
Provides indication on EEPROM size and protection.
Note:
Revision: 2.50
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If the Enable Protection Bit in this word is set and the signature is valid, the software device
driver has read but no write access to this word via the EEC and EERD registers; In this
case, write access is possible only via an authenticated firmware interface.
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Intel® 82580EB/82580DB GbE Controller — EEPROM Sizing and Protected Fields (Word 0x12)
Bit
Name
15:14
Signature
13:10
EEPROM Size
Default in
EEPROM-less
mode
Description
The Signature field indicates to the 82580EB/DB that there is a valid EEPROM
present. If the signature field is 01b, EEPROM read is performed, otherwise the
other bits in this word are ignored, no further EEPROM read is performed, and
default values are used for the configuration space IDs.
0010b
These bits indicate the EEPROM’s actual size.
Mapped to EEC.EE_SIZE See (Section 7.4.1).
Field
Value
EEPROM
Size
EEPROM
Address Size
[0000b - 0110b Reserved]
9:5
Reserved
4
Enable EEPROM
Protection
0b
3:0
HEPSize
0x0
0111b
16 Kbytes
2 bytes
1000b
32 Kbytes
2 bytes
Reserved
If set, all EEPROM protection schemes are enabled.
Hidden EEPROM Block Size
This field defines the EEPROM area accessible only by manageability firmware. It
can be used to store secured data and other manageability functions. The size in
bytes of the secured area equals:
0 bytes if HEPSize equals zero
2^ HEPSize bytes else (for example, 2 B, 4 B, …32 KB)
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Initialization Control 4 (LAN Base Address + Offset 0x13) — Intel® 82580EB/82580DB GbE Controller
6.2.10
Initialization Control 4 (LAN Base Address + Offset 0x13)
These words control general initialization values of LAN 0, LAN 1, LAN 2 and LAN 3 ports.
Bit
15:12
Name
TXPbsize
Default in
EEPROM-less
mode
0x0
Description
Transmit internal buffer size:
0x0 - 20 KB
0x1 - 40 KB
0x2 - 80 KB
0x3 - 1 KB
0x4 - 2 KB
0x5 - 4 KB
0x6 - 8 KB
0x7 - 16 KB
0x8 - 19 KB
0x9 - 38 KB
0xA - 76 KB
0xB:0XF reserved.
When 4 ports are enabled maximum buffer size is 20KB. When 2 ports are enabled
maximum buffer size is 40KB. When only a single port is enabled maximum buffer
size is 80KB.
Sets value of ITPBS.TXPbsize. See Section 7.3.
11:8
RXPbsize
0x0
Receive internal buffer size:
0x0 - 36 KB
0x1 - 72 KB
0x2 - 144 KB
0x3 - 1 KB
0x4 - 2 KB
0x5 - 4 KB
0x6 - 8 KB
0x7 - 16 KB
0x8 - 35 KB
0x9 - 70 KB
0xA - 140 KB
NOTES:
When 4 ports are enabled maximum buffer size is 36 KB. When 2 ports are enabled
maximum buffer size is 72 KB. When only a single port is enabled maximum buffer
size is 144 KB.
Sets value of IRPBS.RXPbsize. See Section 7.3.
7
SPD Enable
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1b
Smart Power Down – When set, enables Internal PHY Smart Power Down mode (See
Section 3.5.7.5.5).
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Intel® 82580EB/82580DB GbE Controller — PCIe L1 Exit latencies (Word 0x14)
Bit
6
Default in
EEPROM-less
mode
Name
LPLU
Description
1b
Low Power Link Up
Enables a decrease in link speed in non-D0a states when power policy and power
management states dictate it (See Section 3.5.7.5.4).
5:1
PHY_ADD
0x00
PHY address. Value loaded to MDICNFG.PHYADD field. See Section 7.2.5.
0x01
0x02
0x03
0
DEV_RST_EN
6.2.11
1b
Enable software reset (CTRL.DEV_RST) generation to all ports (See Section 4.3).
PCIe L1 Exit latencies (Word 0x14)
Bits
Default in
EEPROM-less
mode
Name
Description
15
Reserved
1b
Reserved
14:12
L1_Act_Acc_Latency
110b
Loaded to the “Endpoint L1 Acceptable Latency” field in the “Device
Capabilities” in the “PCIe configuration registers” at power up.
11:9
L1 G2 Sep exit latency
101
L1 exit latency G2S. Loaded to “Link Capabilities” -> “L1 Exit
Latency” at PCIe v2.0 (5Gbps) system in Separate clock setting.
8:6
L1 G2 Com exit latency
011b
L1 exit latency G2C. Loaded to “Link Capabilities” -> “L1 Exit
Latency” at PCIe v2.0 (5Gbps) system in Common clock setting.
5:3
L1 G1 Sep exit latency
100b
L1 exit latency G1S. Loaded to “Link Capabilities” -> “L1 Exit
Latency” at PCIe v2.0 (2.5Gbps) system in Separate clock setting.
2:0
L1 G1 Com exit latency
010b
L1 exit latency G1C. Loaded to “Link Capabilities” -> “L1 Exit
Latency” at PCIe v2.0 (2.5Gbps) system in Common clock setting.
6.2.12
Bit
PCIe Completion Timeout Configuration (Word 0x15)
Name
15:5
Reserved
4
Completion Timeout
Resend
Default in
EEPROM-less
mode
Description
Reserved.
Set value to 0x2.
1b
When set, enables to resend a request once the completion timeout expired
0b = Do not re-send request on completion timeout.
1b = Re-send request on completion timeout. See Section 7.6.1.
3::0
Reserved
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Reserved
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MSI-X Configuration (LAN Base Address + Offset 0x16) — Intel® 82580EB/82580DB GbE Controller
6.2.13
MSI-X Configuration (LAN Base Address + Offset 0x16)
These words configure MSI-X functionality for LAN 0, LAN 1, LAN 2 and LAN 3.
Bit
Name
Default in
EEPROM-less
mode
15:11
MSI_X_N
0x9
10
MSI Mask
1b
Description
This field specifies the number of entries in MSI-X tables of the relevant LAN.
The range is 0-9. MSI_X_N is equal to the number of entries minus one. See
Section 9.5.3.3.
MSI per-vector masking setting. This bit is loaded to the masking
bit (bit 8) in the Message Control word of the MSI Configuration
Capability structure.
9:0
Reserved
6.2.14
Reserved
PCIe Init Configuration 1 (Word 0x18)
This word is used to define L0s exit latencies.
Bits
Name
Default in
EEPROM-less
mode
Description
15
Reserved
0b
Reserved.
14:12
L0s acceptable latency
011b
Loaded to the “Endpoint L0s Acceptable Latency” field in the
“Device Capabilities” in the “PCIe configuration registers” at power
up.
11:9
L0s G2 Sep exit latency
111b
L0s exit latency G2S. Loaded to L0s Exit Latency field in the Link
Capabilities register in the PCIe configuration registers in PCIe v2.0
(5Gbps) system at Separate clock setting.
8:6
L0s G2 Com exit latency
100b
L0s exit latency G2C. Loaded to L0s Exit Latency field in the Link
Capabilities register in the PCIe configuration registers in PCIe v2.0
(5Gbps) system at Common clock setting.
5:3
L0s G1 Sep exit latency
111b
L0s exit latency G1S. Loaded to L0s Exit Latency field in the Link
Capabilities register in the PCIe configuration registers in PCIe v2.0
(2.5Gbps) system at Separate clock setting.
2:0
L0s G1 Com exit latency
011b
L0s exit latency G1C. Loaded to L0s Exit Latency field in the Link
Capabilities register in the PCIe configuration registers in PCIe v2.0
(2.5Gbps) system at Common clock setting.
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Intel® 82580EB/82580DB GbE Controller — PCIe Init Configuration 2 Word (Word 0x19)
6.2.15
PCIe Init Configuration 2 Word (Word 0x19)
This word is used to set defaults for some internal PCIe configuration registers.
Bit
Name
15
Reserved
14
IO_Sup
Default in
EEPROM-less
mode
Description
Reserved
1b
I/O Support (effects I/O BAR request)
When set to 1b, I/O is supported. When cleared the “I/O Access Enable” bit in the
“Command Reg” in the “Mandatory PCI Configuration” area is RO with a value of 0.
Note:
Also called the “disable I/0 feature.” Can be used for disabling allocation of
I/O port resources for use in systems and environments (such as Windows
and UEFI).
See Section 7.1.1.5 for additional information on CSR access via IO address space.
13
CSR_conf_en
0b
Enable CSR access via configuration space.
When set enables CSR access via the configuration registers located at configuration
address space 0x98 and 0x9C.
See Section 7.1.1.6 for additional information on CSR access via configuration
address space.
12
Serial Number
enable
11:0
Reserved
6.2.16
0b
“Serial number capability” enable. Should be set to one.
Reserved
PCIe Init Configuration 3 Word (Word 0x1A)
This word is used to set defaults for some internal PCIe registers.
Bit
Name
15:13
Reserved
12
Cache_Lsize
Default in
EEPROM-less
mode
Description
Reserved
1b
Cache Line Size
0b = 64 bytes.
1b = 128 bytes.
This bit defines the Cache line size reported in the PCIe mandatory
configuration register area. See Section 9.4.7.
11:10
GIO_Cap
10b
PCIe Capability Version
The value of this field is reflected in the two LSBs of the capability version in
the PCIe CAP register (config space – offset 0xA2).
This field must be set to10b to use extended configuration capability.
Note that this is not the PCIe version. It is the PCIe capability version. This
version is a field in the PCIe capability structure and is not the same as the
PCIe version. It changes only when the content of the capability structure
changes. For example, PCIe 1.0, 1.0a, and 1.1 all have a capability version of
one. PCIe 2.0 has a version of two because it added registers to the
capabilities structures. See Section 9.5.6.3.
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PCIe Control 1 (Word 0x1B) — Intel® 82580EB/82580DB GbE Controller
Bit
9:8
Default in
EEPROM-less
mode
Name
Max Payload Size
10b
Description
Default packet size
00b = 128 bytes.
01b = 256 bytes.
10b = 512 bytes.
11b = Reserved.
See Section 9.5.6.4.
7:4
Reserved
3:2
Act_Stat_PM_Sup
Reserved
11b
Determines support for active state link power management
Loaded into the PCIe Active State Link PM Support register. See
Section 9.5.6.7.
1
Slot_Clock_Cfg
0
Reserved
6.2.17
1b
When set, the 82580EB/DB uses the PCIe reference clock supplied on the
connector (for add-in solutions).
Reserved
PCIe Control 1 (Word 0x1B)
This word is used to configure initial settings for PCIe default functionality.
Bit
Name
Default in
EEPROM-less
mode
15
Reserved
0b
14
Dummy Function
Enable
0b
Description
Reserved
Controls the behavior of function 0 when
disabled. See Section 4.4.2.
0b - Legacy Mode
1b - Dummy Function Mode
13:8
Reserved
7
Reserved
6:0
Reserved
6.2.18
Reserved
0b
Reserved must be 0b
Reserved
LED 1,3 Configuration Defaults (LAN Base Address +
Offset 0x1C)
These EEPROM words specify the hardware defaults for the LEDCTL register fields controlling the LED1
(ACTIVITY indication) and LED3 (LINK_1000 indication) output behavior. Words control LEDs behavior
of LAN 0, LAN 1, LAN 2 and LAN 3 ports.
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Intel® 82580EB/82580DB GbE Controller — Device Rev ID (Word 0x1E)
Bit
15
Name
LED3 Blink
Default in
EEPROM-less
mode
0b
Description
Initial value of LED3_BLINK field.
0b = Non-blinking.
See Section 7.2.9 and Section 8.5.
14
LED3 Invert
0b
Initial value of LED3_IVRT field.
0b = Active-low output.
See Section 7.2.9 and Section 8.5.
13:12
Reserved
11:8
LED3 Mode
0111b
Reserved
7
LED1 Blink
1b
Initial value of the LED3_MODE field specifying what event/state/pattern is
displayed on LED3 (LINK_1000) output. A value of 0111b (0x7) indicates 1000
Mb/s operation.
See Section 7.2.9 and Section 8.5.
Initial value of LED1_BLINK field.
0b = Non-blinking.
See Section 7.2.9 and Section 8.5.
6
LED1 Invert
0b
Initial value of LED1_IVRT field.
0b = Active-low output.
See Section 7.2.9 and Section 8.5.
5:4
Reserved
3:0
LED1 Mode
Reserved
0011b
Initial value of the LED1_MODE field specifying what event/state/pattern is
displayed on LED1 (ACTIVITY) output. A value of 0011b (0x3) indicates the
ACTIVITY state.
See Section 7.2.9 and Section 8.5.
A value of 0x0703 is used to configure default hardware LED behavior equivalent to previous copper
adapters (LED0=LINK_UP, LED1=blinking ACTIVITY, LED2=LINK_100, and LED3=LINK_1000).
6.2.19
Bit
Device Rev ID (Word 0x1E)
Name
Default in
EEPROM-less
mode
15
Power Down
Enable
0b
14
LAN 3 iSCSI
enable
0b
LAN 2 iSCSI
enable
0b
Description
Enable Power down when DEV_OFF_N pin is asserted or PCIe in Dr state. See
Section 5.2.4.1 for details.
When set, LAN 3 class code is set to 0x010000 (SCSI)
When reset, LAN 3 class code is set to 0x020000 (LAN)
See Section 9.4.6.
13
When set, LAN 2 class code is set to 0x010000 (SCSI)
When reset, LAN 2 class code is set to 0x020000 (LAN)
See Section 9.4.6.
12
LAN 1 iSCSI
enable
0b
When set, LAN 1 class code is set to 0x010000 (SCSI)
When reset, LAN 1 class code is set to 0x020000 (LAN)
See Section 9.4.6.
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LED 0,2 Configuration Defaults (LAN Base Address + Offset 0x1F) — Intel® 82580EB/82580DB GbE
Controller
Bit
11
Name
LAN 0 iSCSI
enable
Default in
EEPROM-less
mode
0b
Description
When set, LAN 0 class code is set to 0x010000 (SCSI)
When reset, LAN 0 class code is set to 0x020000 (LAN)
See Section 9.4.6.
10:8
Reserved
7:0
DEVREVID
Reserved
0x0
Device Revision ID
The actual device revision ID is the EEPROM value XORed with the hardware default
of Rev ID. For the 82580EB/DB, the default value is zero. See Section 9.4.5.
6.2.20
LED 0,2 Configuration Defaults (LAN Base Address +
Offset 0x1F)
These EEPROM words specify the hardware defaults for the LEDCTL register fields controlling the LED0
(LINK_UP) and LED2 (LINK_100) output behaviors. Words control LEDs behavior of LAN 0, LAN 1, LAN
2 and LAN 3 ports.
Bit
15
Name
LED2 Blink
Default in
EEPROM-less
mode
0b
Description
Initial value of LED2_BLINK field.
0b = Non-blinking.
See Section 7.2.9 and Section 8.5.
14
LED2 Invert
0b
Initial value of LED2_IVRT field.
0b = Active-low output.
See Section 7.2.9 and Section 8.5.
13
Reserved
0b
Reserved
12
Reserved
0b
Reserved. Set to 0b.
11:8
LED2 Mode
0110b
Initial value of the LED2_MODE field specifying what event/state/pattern is
displayed on LED2 (LINK_100) output. A value of 0110b (0x6) indicates 100 Mb/s
operation.
See Section 7.2.9 and Section 8.5.
7
LED0 Blink
0b
Initial value of LED0_BLINK field.
0b = Non-blinking.
See Section 7.2.9 and Section 8.5.
6
LED0 Invert
0b
Initial value of LED0_IVRT field.
0b = Active-low output.
See Section 7.2.9 and Section 8.5.
5
Global Blink Mode
0b
Global Blink Mode
0b = Blink at 200 ms on and 200ms off.
1b = Blink at 83 ms on and 83 ms off.
See Section 7.2.9 and Section 8.5.
4
Reserved
0b
Reserved. Set to 0b.
3:0
LED0 Mode
0010b
Initial value of the LED0_MODE field specifying what event/state/pattern is
displayed on LED0 (LINK_UP) output. A value of 0010b (0x2) indicates the
LINK_UP state.
See Section 7.2.9 and Section 8.5.
Revision: 2.50
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Intel® 82580EB/82580DB GbE Controller — Software Defined Pins Control (LAN Base Address + Offset
0x20)
A value of 0x0602 is used to configure default hardware LED behavior equivalent to previous copper
adapters (LED0=LINK_UP, LED1=blinking ACTIVITY, LED2=LINK_100, and LED3=LINK_1000).
6.2.21
Software Defined Pins Control (LAN Base Address + Offset
0x20)
These words at offset 0x20 from start of relevant EEPROM section are used to configure initial settings
of software defined pins (SDPs) for LAN 0, LAN 1, LAN 2 and LAN 3.
Bit
15
Name
SDPDIR[3]
Default in
EEPROM-less
mode
0b
Description
SDP3 Pin – Initial Direction
This bit configures the initial hardware value of the SDP3_IODIR bit in the
Extended Device Control (CTRL_EXT) register following power up. See
Section 7.2.3.
14
SDPDIR[2]
0b
SDP2 Pin – Initial Direction
This bit configures the initial hardware value of the SDP2_IODIR bit in the
Extended Device Control (CTRL_EXT) register following power up. See See
Section 7.2.3 .
13
PHY_in_LAN_disa 0b
ble
Determines the behavior of the MAC and PHY when a LAN port is disabled through
an external pin.
0b = MAC and PHY are kept functional in LAN disable (to support manageability).
1b = MAC and PHY are powered down in LAN disable (manageability cannot access
the network through this port).
12
Disable 100 in
non-D0a
0b
11
LAN_DIS1
0b
Disables 1000Mb/s and 100 Mb/s operation in non-D0a states (See
Section 3.5.7.5.4).
Sets default value of PHPM.Disable 100 in non-D0a bit.
LAN Disable
In LAN ports 1,2 and 3, when set to 1b, the appropriate LAN is disabled (both PCIe
function and LAN access for manageability are disabled).
Note: Should be cleared to 0 for LAN port 0.
10
LAN_PCI_DIS1
0b
LAN PCIe Function Disable
In LAN ports 1,2 and 3, when set to 1b, the appropriate LAN PCI function is
disabled. For example, in the case were the LAN is functional for manageability
operation but is not connected to the host through the PCIe interface.
Note:
1.
Bit has no effect on LAN port 0 and is Reserved with a value of 0b.
2.
When bit is set, Function is in a Non-D0a (uninitialized) state. As a result if
the LPLU, Disable 1000 in Non-D0a or Disable 100 in Non-D0a EEPROM bits
are set, Management might operate with reduced link speed.
9
SDPDIR[1]
0b
SDP1 Pin – Initial Direction
This bit configures the initial hardware value of the SDP1_IODIR bit in the Device
Control (CTRL) register following power up. See Section 7.2.1 .
8
SDPDIR[0]
0b
SDP0 Pin – Initial Direction
This bit configures the initial hardware value of the SDP0_IODIR bit in the Device
Control (CTRL) register following power up. See Section 7.2.1 .
7
SDPVAL[3]
0b
SDP3 Pin – Initial Output Value
This bit configures the initial power-on value output on SDP3 (when configured as
an output) by configuring the initial hardware value of the SDP3_DATA bit in the
Extended Device Control (CTRL_EXT) register after power up. See Section 7.2.3 .
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Functions Control (Word 0x21) — Intel® 82580EB/82580DB GbE Controller
Bit
Name
6
SDPVAL[2]
Default in
EEPROM-less
mode
0b
Description
SDP2 Pin – Initial Output Value
This bit configures the initial power-on value output on SDP2 (when configured as
an output) by configuring the initial hardware value of the SDP2_DATA bit in the
Extended Device Control (CTRL_EXT) register after power up. See Section 7.2.3 .
5
WD_SDP0
0b
When set, SDP[0] is used as a watchdog timeout indication. When reset, it is used
as an SDP (as defined in bits 8 and 0). See Section 7.2.1 .
4
Giga Disable
0b
When set, GbE operation is disabled. A usage example for this bit is to disable GbE
operation if system power limits are exceeded (See Section 3.5.7.5.4).
3
Disable 1000 in
non-D0a
0b
Disables 1000 Mb/s operation in non-D0a states (See Section 3.5.7.5.4).
2
ADVD3WUC
1b
Controls reporting of D3 Cold wake-up support in the Power Management
Capabilities (PMC) configuration register. See Section 9.5.1.3.
In addition bit is loaded to CTRL.ADVD3WUC (See Section 7.2.1).
When set, D3Cold wake up capability is advertised based on whether AUX_PWR
pin is connected to 3.3V to advertise presence of auxiliary power (yes if AUX_PWR
is indicated, no otherwise). When 0b, however, D3Cold wake up capability is not
advertised even if AUX_PWR presence is indicated.
If full 1Gb/sec. operation in D3 state is desired but the system's power
requirements in this mode would exceed the D3Cold Wake up-Enabled
specification limit (375mA at 3.3V), this bit can be used to prevent the capability
from being advertised to the system.
1
SDPVAL[1]
0b
SDP1 Pin – Initial Output Value
This bit configures the initial power-on value output on SDP1 (when configured as
an output) by configuring the initial hardware value of the SDP1_DATA bit in the
Device Control (CTRL) register after power up. See See Section 7.2.1 .
0
SDPVAL[0]
0b
SDP0 Pin – Initial Output Value
This bit configures the initial power-on value output on SDP0 (when configured as
an output) by configuring the initial hardware value of the SDP0_DATA bit in the
Device Control (CTRL) register after power up. See See Section 7.2.1 .
1. Function 0 can not be disabled via EEPROM.
6.2.22
Bit
15
Functions Control (Word 0x21)
Name
Default in
EEPROM-less
mode
Description
NC-SI Clock Pad
Drive Strength
0b
Defines the drive strength of the NCSI_CLK_OUT pad. If set, the
14
NC-SI Data Pad
Drive Strength
0b
Defines the drive strength of the NCSI_CRS_DV and NCSI_RXD pads. If set, the
driving strength is stronger. See Section 10.6.1.4 for details.
13
NC-SI Output Clock
Disable
0b
If set, the clock source is external. In this case, the NCSI_CLK_OUT pad is kept
stable at zero and the NCSI_CLK_IN pad is used as an input source of the clock.
driving strength is stronger. See Section 10.6.1.4 for details.
If cleared, the 82580EB/DB outputs the NC-SI clock through the NCSI_CLK_OUT
pad. The NCSI_CLK_IN pad is still used as a NC-SI clock input.
If NC-SI is not used, then this bit should be set.
If this bit is cleared, the Device Power Down Enable bit in word 0x1E
(bit 15) should not be set.
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Intel® 82580EB/82580DB GbE Controller — Functions Control (Word 0x21)
Bit
12
Name
LAN Function Sel
Default in
EEPROM-less
mode
0b
Description
LAN Function Select
When all LAN ports are enabled and LAN Function Sel = 0b, LAN 0 is routed to PCI
Function 0, LAN 1 is routed to PCI Function 1, etc. If LAN Function Sel = 1b, LAN
0 is routed to PCI Function 3, LAN 1 is routed to PCI Function 2, etc. This bit is
Mapped to FACTPS[30]. See Section 7.6.9).
11
Reserved
0b
Reserved
10
BAR32
1b
Bit (loaded to the BARCTRL register) preserves the legacy 32 bit BAR mode when
BAR32 is set. When cleared to 0b 64 bit BAR addressing mode is selected.
Note: If PREFBAR is set the BAR32 bit should always be 0 (64 bit BAR addressing
mode).
See Section 9.4.11.
9
PREFBAR
0b
0 = BARs are marked as non prefetchable
1 = BARs are marked as prefetchable
Note: This bit should be set only on systems that do not generate prefetchable
cycles. This bit is loaded from the PREFBAR bit in the EEPROM.
See Section 9.4.11.
8:1
Reserved
00100000b
Reserved
0
NC-SI Slew Rate
1b
Defines the slew rate of the NCSI_CLK_OUT, NCSI_CRS_DV and NCSI_RXD pads.
If set, the slew rate is high.
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LAN Power Consumption (Word 0x22) — Intel® 82580EB/82580DB GbE Controller
6.2.23
Bit
LAN Power Consumption (Word 0x22)
Name
Default in
EEPROM-less
mode
Description
15:8
LAN D0 Power
0x0
The value in this field is reflected in the PCI Power Management Data Register of
the LAN functions for D0 power consumption and dissipation (Data_Select = 0 or
4). Power is defined in 100mW units. The power includes also the external logic
required for the LAN function. See Section 9.5.1.4.
7:5
Function 0 Common
Power
0x0
The value in this field is reflected in the PCI Power Management Data register of
function 0 when the Data_Select field is set to 8 (common function). The MSBs in
the data register that reflects the power values are padded with zeros. See
Section 9.5.1.4.
4:0
LAN D3 Power
0x0
The value in this field is reflected in the PCI Power Management Data register of
the LAN functions for D3 power consumption and dissipation (Data_Select = 3 or
7). Power is defined in 100 mW units. The power also includes the external logic
required for the LAN function. The MSBs in the data register that reflects the power
values are padded with zeros. See Section 9.5.1.4.
6.2.24
Initialization Control 3 (LAN Base Address + Offset 0x24)
These words control general initialization values of LAN 0, LAN 1, LAN 2 and LAN 3 ports.
Bit
15
Name
SerDes Energy
Source
Default in
EEPROM-less
mode
0b
Description
SerDes Energy Source Detection
When set to 0b, source is internal SerDes Rx circuitry for electrical idle or link-up
indication.
When set to 1b, source is external SRDS_[n]_SIG_DET signal for electrical idle or
Link-up indication.
This bit also indicates the source of the signal detect while establishing a link in
SerDes mode.
This bit sets the default value of the CONNSW.ENRGSRC bit. See Section 7.2.7.
14
2 wires SFP
Enable
0b
2 wires SFP interface enable - bit is used to enable interfacing an external PHY either
VIA the MDIO or I2C interface
0b = Disabled. When disabled, the 2 wires I/F pads are isolated.
1b = Enabled.
Used to set the default value of CTRL_EXT.I2C Enabled. See See Section 7.2.3 .
13
ILOS
0b
Default setting for the loss-of-signal polarity bit (CTRL[7]). See Section 7.2.1 .
12:11
Interrupt Pin
00b LAN 0
Controls the value advertised in the Interrupt Pin field of the PCI Configuration
header for this device/function.
01b LAN 1
10b LAN 2
11b LAN3
The encoding of this field is as follow:
ValueaaaaaaaaINT LineaaaaaaaaaaaaInterrupt Pin Field Value
a00baaaaaaaaaaINTAaaaaaaaaaaaaaaaaaaaaaa1
a01baaaaaaaaaaINTBaaaaaaaaaaaaaaaaaaaaaa2
a10baaaaaaaaaaINTCaaaaaaaaaaaaaaaaaaaaaa3
a11baaaaaaaaaaINTDaaaaaaaaaaaaaaaaaaaaaa4
If only a single device/function of the 82580EB/DB component is enabled, this value
is ignored and the Interrupt Pin field of the enabled device reports INTA# usage. See
Section 9.4.18.
10
APM Enable
9
Reserved
Revision: 2.50
October 2011
0b
Initial value of Advanced Power Management Wake Up Enable bit in the Wake Up
Control (WUC.APME) register. Mapped to CTRL[6] and to WUC[0]. see See Section
7.2.1 and See Section 7.21.1 .
Reserved
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Intel® 82580EB/82580DB GbE Controller — PCIe Control 2 (Word 0x28)
Bit
Name
Default in
EEPROM-less
mode
Description
8
Reserved
7
LAN Boot Disable
1b
Reserved
A value of 1b disables the expansion ROM BAR in the PCI configuration space.
5:4
Link Mode
00b
Initial value of Link Mode bits of the Extended Device Control
(CTRL_EXT.LINK_MODE) register, specifying which link interface and protocol is
used by the MAC.
00b = MAC operates with internal copper PHY (10/100/1000Base-T).
01b = MAC and SerDes I/F operate in 1000BASE-KX mode.
10b = MAC and SerDes operate in SGMII mode.
11b = MAC and SerDes I/F operate in SerDes (1000BASE-BX) mode.
See Section 7.2.3 .
6
Reserved
Reserved
3
Com_MDIO
0b
When this bit is set, access to the MDIO interface on this port is routed to the LAN 0
MDIO interface. In this case the LAN 0 MDIO interface is used as a common interface
for MDIO accesses to a Multi PHY device that has a single MDIO interface for all
PHYs.
0b - MDIO access routed to the dedicated LAN port MDIO interface.
1b - MDIO accesses on this LAN port are routed to the LAN 0 MDIO interface
Used to set the default value of MDICNFG.Com_MDIO bit. See Section 7.2.5.
2
External MDIO
0b
When set PHY management interface is via external MDIO interface. Loaded to
MDICNFG.Destination. See Section 7.2.5.
1
EXT_VLAN
0b
Sets the default for CTRL_EXT[26] bit. Indicates that additional VLAN is expected in
this system. See Section 7.2.3 .
0
Keep_PHY_Link_U 0b
p_En
Enables No PHY Reset when the Baseboard Management Controller (BMC) indicates
that the PHY should be kept on. When asserted, this bit prevents the PHY reset
signal and the power changes reflected to the PHY according to the
MANC.Keep_PHY_Link_Up value.
Note: This EEPROM bit should be set to the same value for all LAN ports.
6.2.25
PCIe Control 2 (Word 0x28)
This word is used to configure initial settings for the PCIe default functionality.
Bits
Name
15:13
Reserved
12
ECRC Check
Default in
EEPROM-less
mode
Description
Reserved
1b
Loaded into the ECRC Check Capable bit of the PCIe configuration registers
0b - Function is not capable of checking ECRC
1b - Function is capable of checking ECRC
11
ECRC Generation
1b
Loaded into the ECRC Generation Capable bit of the PCIe configuration registers.
0b - Function is not capable of generating ECRC
1b - Function is capable of generating ECRC
10
FLR capability enable
1b
FLR capability Enable bit is loaded to “PCIe configuration
registers” -> “Device Capabilities”.
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PCIe Control 3 (Word 0x29) — Intel® 82580EB/82580DB GbE Controller
Bits
Name
Default in
EEPROM-less
mode
Description
9:6
FLR delay
0x1
Delay in microseconds from D0 to D3 move till reset assertion.
5
FLR delay disable
0b
FLR delay disable.
0 - Add delay to FLR assertion.
1 - Do not add delay to FLR assertion.
4:0
Reserved
6.2.26
0x0
Reserved
PCIe Control 3 (Word 0x29)
This word is used for programming PCIe functionality.
Bits
Name
Default in
EEPROM-less
mode
Description
15:7
Reserved
0x0
Reserved
6
Reserved
0b
Reserved
5
Wake_pin_enable
0b
Enables the use of the wake pin for a PME event in all non L2 power states.
4
DIS Clock Gating in
DISABLE
1b
3
DIS Clock Gating in
L2
1b
Disable clock gating when LTSSM is at L2 state
2
DIS Clock Gating in
L1
1b
Disable clock gating when LTSSM is at L1 state
1:0
Reserved
6.2.27
Disable clock gating when LTSSM is at DISABLE
state.
Reserved
End of Read-Only (RO) Area (Word 0x2C)
Defines the end of the area in the EEPROM that is RO.
Bit
Name
Description
15
Reserved
Reserved
14:0
EORO_area
Defines the end of the area in the EEPROM that is RO. The resolution is one word and can be up to
byte address 0xFFFF (0x7FFF words). A value of zero indicates no RO area.
6.2.28
Start of RO Area (Word 0x2D)
Defines the start of the area in the EEPROM that is RO.
Bit
Name
Description
15
Reserved
Reserved
14:0
SORO_area
Defines the start of the area in the EEPROM that is RO. The resolution is one word and can be up to
byte address 0xFFFF (0x7FFF words).
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Intel® 82580EB/82580DB GbE Controller — Watchdog Configuration (Word 0x2E)
6.2.29
Bit
Watchdog Configuration (Word 0x2E)
Default in
EEPROM-less
mode
Name
15
Watchdog Enable
0b
Description
Enable watchdog interrupt. See Section 7.16.1.
Note:
14:11
Watchdog
Timeout
10:0
0x0
Watchdog timeout period (in seconds). See Section 7.16.1.
Note: Loaded to 4 LSB bits of WDSTP.WD_Timeout field.
Reserved
6.2.30
If bit is set to 1b value of EEPROM Watchdog Timeout field should be 2 or
higher to avoid immediate generation of a watchdog interrupt.
Reserved
VPD Pointer (Word 0x2F)
This word points to the Vital Product Data (VPD) structure. This structure is available for the NIC vendor
to store it's own data. A value of 0xFFFF indicates that the structure is not available.
Bit
15:0
Name
Description
VPD offset
6.3
Offset to VPD structure in words.
Notes:
1.
For the VPD structure to be valid bit 15 must be cleared to 0b and the VPD area
should be located in the first 32 KBytes of the EEPROM.
2.
For the VPD structure to be valid bit 0 must be cleared to 0b (Start address should
be Dword aligned).
CSR Auto Configuration Pointer
(LAN Base Address + Offset 0x17)
Word points to the CSR auto configuration structures of LAN 0, LAN 1, LAN 2 and LAN3. Sections are
loaded during HW auto-load as described in Section 3.3.1.3. If no CSR autoload is required for the
specific LAN port, the word shall be set to 0xFFFF.
The CSR Auto Configuration structure format is listed in the following tables.
Table 6-4.
CSR Auto Configuration Structure Format
Offset
High Byte[15:8]
Low Byte[7:0]
Section
0x0
Section Length = 3*n (n – number of CSRs to configure)
Section 6.3.1
0x1
Block CRC8
Section 6.3.2
0x2
CSR Address
Section 6.3.3
0x3
Data LSB
Section 6.3.4
Data MSB
Section 6.3.5
0x4
…
3*n - 1
CSR Address
Section 6.3.3
3*n
Data LSB
Section 6.3.4
3*n + 1
Data MSB
Section 6.3.5
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CSR Configuration Section Length - Offset 0x0 — Intel® 82580EB/82580DB GbE Controller
6.3.1
CSR Configuration Section Length - Offset 0x0
The section length word contains the length of the section in words. Note that section length count does
not include the section length word and Block CRC8 word.
Bits
Name
15
Reserved
14:0
Section_length
6.3.2
Section length in words.
Name
15:8
Reserved
7:0
CRC8
6.3.3
Description
CSR Address - (Offset 3*n - 1; [n = 1... Section Length])
Bits
Name
15
Reserved
14:0
CSR_ADDR
6.3.4
Default
Description
CSR Address in Double Words (4 bytes)
CSR Data LSB - (Offset 3*n; [n = 1... Section Length])
Bits
Name
Default
CSR_Data_LSB
6.3.5
Description
CSR Data LSB
CSR Data MSB - (Offset 3*n + 1; [n = 1... Section Length])
Bits
15:0
Description
Block CRC8 (Offset 0x1)
Bit
15:0
Default
Name
CSR_Data_MSB
6.4
Default
Description
CSR Data MSB
CSR Auto Configuration Power-Up Pointer
(LAN Base Address + Offset 0x27)
This word points to the CSR auto configuration Power-Up structures of LAN 0, LAN 1, LAN 2 and LAN3.
Sections are loaded during HW auto-load as described in Section 3.3.1.3. If no CSR autoload is required
for the specific LAN port, the word shall be set to 0xFFFF.
The CSR Auto Configuration Power-Up structure format is listed in the following tables.
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Intel® 82580EB/82580DB GbE Controller — CSR Configuration Power-Up Section Length - Offset 0x0
Table 6-5.
CSR Auto Configuration Power-Up Structure Format
Offset
High Byte[15:8]
Low Byte[7:0]
Section
0x0
Section Length = 3*n (n – number of CSRs to configure)
Section 6.4.1
0x1
Block CRC8
Section 6.4.2
0x2
CSR Address
Section 6.4.3
0x3
Data LSB
Section 6.4.4
Data MSB
Section 6.4.5
0x4
…
3*n - 1
CSR Address
Section 6.4.3
3*n
Data LSB
Section 6.4.4
3*n + 1
Data MSB
Section 6.4.5
6.4.1
CSR Configuration Power-Up Section Length - Offset 0x0
The section length word contains the length of the section in words. Note that section length count does
not include the section length word and Block CRC8 word.
Bits
Name
15
Reserved
14:0
Section_length
6.4.2
Reserved
7:0
CRC8
Name
15
Reserved
14:0
CSR_ADDR
Bits
Description
CSR Address - (Offset 3*n - 1; [n = 1... Section Length])
Bits
15:0
Section length in words.
Name
15:8
6.4.4
Description
Block CRC8 (Offset 0x1)
Bit
6.4.3
Default
Default
Description
CSR Address in Double Words (4 bytes)
CSR Data LSB - (Offset 3*n; [n = 1... Section Length])
Name
Default
CSR_Data_LSB
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Description
CSR Data LSB
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CSR Data MSB - (Offset 3*n + 1; [n = 1... Section Length]) — Intel® 82580EB/82580DB GbE Controller
6.4.5
CSR Data MSB - (Offset 3*n + 1; [n = 1... Section Length])
Bits
15:0
Name
Default
CSR_Data_MSB
Description
CSR Data MSB
6.5
Reserved (Word 0x10)
6.6
Firmware Pointers and Control Words
Word 0x11 in each LAN port EEPROM section are used to point to structures specific to Pass through
operation. Words 0x54 and 0x23 control some aspects of the Firmware functionality.
Word 0x51 is used to point to the load Firmware patch structure.
A value of 0xFFFF for a pointer indicates that the relevant structure is not present in the EEPROM.
6.6.1
Pass Through LAN Configuration Pointer
(LAN Base Address + Offset 0x11)
Bit
15:0
Name
Pointer
6.6.2
Description
Pointer to the PT LAN Configuration Structure. See Section 6.8 for
details of the structure.
Management HW Config Control (Word 0x23)
This word contains bits that configure special firmware behavior.
Bit
Name
Description
15
LAN3_FTCO_RST_DIS
LAN3 force TCO reset disable (1b disable; 0b enable).
14
LAN2_FTCO_RST_DIS
LAN2 force TCO reset disable (1b disable; 0b enable).
13
LAN1_FTCO_RST_DIS
LAN1 force TCO reset disable (1b disable; 0b enable).
12
LAN0_FTCO_RST_DIS
LAN0 force TCO reset disable (1b disable; 0b enable).
11
Multi-Drop NC-SI
Multi-Drop NC-SI topology.
0 - Point-to-point (default)
1 - Multi-drop
When bit is set the NCSI_CRS_DV and NCSI_RXD[1:0] pins are
High-Z Following power-up, otherwise the pins are driven.
10
PARITY_ERR_RST_EN
When set enables reset of Management logic and generation of
internal Firmware reset as a result of Parity Error detected in
Management memories.
Note: Bit should be set to 1.
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Intel® 82580EB/82580DB GbE Controller — PHY Configuration Pointer (Word 0x50)
Bit
9
Name
Enable All Phys in D3
Description
0 - Only ports activated for BMC activity will stay active in D3:
In NCSI mode – according to enable channel command to the
specific port.
In SMBUS mode – according to EEPROM port enable bit.
1- All PHYs will stay active in D3.
8:4
Reserved
Reserved
3
LAN3_FTCO_ISOL_DIS
LAN3 force TCO Isolate disable (1b disable; 0b enable).
2
LAN2_FTCO_ISOL_DIS
LAN2 force TCO Isolate disable (1b disable; 0b enable).
1
LAN1_FTCO_ISOL_DIS
LAN1 force TCO Isolate disable (1b disable; 0b enable).
0
LAN0_FTCO_ISOL_DIS
LAN0 force TCO Isolate disable (1b disable; 0b enable).
6.6.3
PHY Configuration Pointer (Word 0x50)
Bit
15:0
Name
Pointer
6.6.4
Description
Pointer to PHY configuration structure. See Section 6.9 for details of
the structure. A value of 0xFFFF means the pointer is invalid.
Firmware Patch Pointer (Word 0x51)
Bit
15:0
Name
Pointer
6.6.5
Description
Pointer to loader patch structure. See Section 6.7 for details of the
structure.
Manageability Capability/Manageability Enable (Word
0x54)
Bit
Name
Description
15
Reserved
Reserved
14
Redirection Sideband Interface
0b = SMBus.
13:12
Reserved
Reserved.
11
MCSR_TO_RETRY
0b - On CSR access Timeout return failed access to BMC.
1b = NC-SI.
1b - On CSR access Timeout retry access internally and don’t return
failed access.
Default value - 1b
10:8
Manageability Mode
0x0 = None.
0x1 = Reserved.
0x2 = Pass Through (PT) mode.
0x3 = Reserved.
0x4 = Host interface enable only.
0x5:0x7 = Reserved.
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Sideband Configuration Pointer (Word 0x57) — Intel® 82580EB/82580DB GbE Controller
Bit
Name
Description
7
Port 3 Manageability Capable
0 = Not capable
1 = Bit 3 applicable to port 3.
6
Port 2 Manageability Capable
0 = Not capable
1 = Bit 3 applicable to port 2.
5
Port 1 Manageability Capable
0 = Not capable
1 = Bit 3 applicable to port 1.
4
Port 0 Manageability Capable
0 = Not capable
1 = Bit 3 applicable to port 0.
3
Pass Through Capable
0b = Disable.
1b = Enable.
2:0
Reserved
6.6.6
Reserved
Sideband Configuration Pointer (Word 0x57)
Bit
15:0
Name
Pointer
6.6.7
Description
Pointer to the Sideband configuration pointer structure. See
Section 6.10 for details of the structure.
Reserved (Word 0x5E)
Bit
15:0
Name
Pointer
6.7
Description
Value should be 0xFFFF
Firmware Patch Structure
This structure is used for all FW patches. Firmware patch Pointer (Word 0x51) points to the start (offset
0x0) of this kind of structure. If pointer is 0xFFFF then no structure exists. Structure is loaded during
HW EEPROM auto-load as described in Section 3.3.1.3.
6.7.1
Firmware Patch Data Size (Offset 0x0)
The Data Size word contains the length of the section in words. Note that Data Size count does not
include the section length word and Block CRC8 word.
Bit
15:0
Revision: 2.50
October 2011
Name
Description
Data Size (Words)
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Intel® 82580EB/82580DB GbE Controller — Block CRC8 (Offset 0x1)
6.7.2
Block CRC8 (Offset 0x1)
Bit
Name
15:8
Reserved
7:0
CRC8
6.7.3
Patch Ram Address Word (Offset 0x2)
Bit
15:0
Name
Ram address
6.7.4
Bit
Patch Version 1 Word (Offset 0x3)
Name
Patch Generation Hour
7:0
Patch Generation Minutes
Bit
Name
Patch Generation Month
7:0
Patch Generation Day
Bit
15:8
Description
Patch Version 2 Word (Offset 0x4)
15:8
6.7.6
Description
Ram Address to load patch.
15:8
6.7.5
Description
Description
Patch Version 3 Word (Offset 0x5)
Name
Description
Patch Silicon Version Compatibility 0x00 = A0.
0x01 = A1.
0x10 = B0.
0x11 = B1.
7:0
Patch Generation Year
6.7.7
Bit
Patch Version 4 Word (Offset 0x6)
Name
15:8
Patch Major Number
7:0
Patch Minor Number
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Description
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October 2011
Patch Data Words (Offset 0x7, Block Length) — Intel® 82580EB/82580DB GbE Controller
6.7.8
Patch Data Words (Offset 0x7, Block Length)
Bit
Name
15:0
Description
Patch Firmware Data
6.8
PT LAN Configuration Structure
The Pass Through LAN Configuration Pointer (LAN Base Address + Offset 0x11) points to the start
(offset 0x0) of this type of structure, to configure manageability filters. If pointer is 0xFFFF then no
structure exists. Structure is loaded during HW EEPROM auto-load as described in Section 3.3.1.3.
Note:
When interface to BMC is via SMBus the PT LAN Configuration Structure must be used to
configure the required filters. When Interface is NC-SI, structure should be empty and value
of Pass Through LAN Configuration Pointer (Offset 0x11) should be 0XFFFF.
The PT LAN Configuration Structure format is listed in the following tables.
Table 6-6.
PT LAN Configuration Structure Format
Offset
High Byte[15:8]
Low Byte[7:0]
Section
0x0
Section Length = 3*n (n – number of CSRs to configure)
Section 6.8.1
0x1
Block CRC8
Section 6.8.2
0x2
CSR Address
Section 6.8.3
0x3
Data LSB
Section 6.8.4
0x4
Data MSB
Section 6.8.5
…
3*n - 1
CSR Address
Section 6.8.3
3*n
Data LSB
Section 6.8.4
3*n + 1
Data MSB
Section 6.8.5
6.8.1
PT LAN Configuration Structure Section Length - Offset
0x0
The section length word contains the length of the section in words. Note that section length count does
not include the section length word and Block CRC8 word.
Bits
Name
15
Reserved
14:0
Section_length
Revision: 2.50
October 2011
Default
Description
Section length in words.
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Intel® 82580EB/82580DB GbE Controller — Block CRC8 (Offset 0x1)
6.8.2
Block CRC8 (Offset 0x1)
Bit
Name
15:8
Reserved
7:0
CRC8
6.8.3
CSR Address - (Offset 2*n; [n = 1... Section Length])
Bits
Name
15
Reserved
14:0
CSR_ADDR
6.8.4
Bits
15:0
6.8.5
Bits
15:0
6.8.6
Description
Default
Description
CSR Address in Double Words (4 bytes)
CSR Data LSB - (Offset 0x1 + 2*n; [n = 1... Section
Length])
Name
Default
CSR_Data_LSB
Description
CSR Data LSB
CSR Data MSB - (Offset 0x2 + 2*n; [n = 1... Section
Length])
Name
Default
CSR_Data_MSB
Description
CSR Data MSB
Manageability Filters
Following table lists registers that can be programmed via the PT LAN Configuration structure.
Name
Description
Section
MAVTV
Management VLAN TAG Value
Section 7.22.1
MFUTP
Management Flex UDP/TCP Ports
Section 7.22.2
METF
Management Ethernet Type Filters
Section 7.22.3
MNGONLY
Management Only Traffic Register
Section 7.22.5
MDEF
Manageability Decision Filters
Section 7.22.6
MDEF_EXT
Manageability Decision Filters Extension
Section 7.22.7
MIPAF
Manageability IP Address Filter registers (IPv4 or IPV6)
Section 7.22.8
Note: Can be used to filter IPV4 Address of ARP packets.
MMAL
Manageability MAC Address Low Registers
Section 7.22.9
MMAH
Manageability MAC Address High Registers
Section 7.22.10
FTFT
Flexible TCO Filter Table registers
Section 7.22.11
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PHY configuration Structure — Intel® 82580EB/82580DB GbE Controller
6.9
PHY configuration Structure
This section describes the PHY auto configuration structure used to configure PHY related circuitry. The
programming in this section is applied after each PHY reset. After the registers in this section are
written to the PHY, the relevant EEMNGCTL.CFG_DONE bit is set.
The PHY Configuration Pointer (Word 0x50) points to the start (offset 0x0) of this type of structure, to
configure PHY registers (when device is configured to use the Internal copper PHY). If pointer is 0xFFFF
then no structure exists. Structure is loaded after internal PHY reset.
Table 6-7.
PHY Auto Configuration Structure format
Offset
High Byte[15:8]
Low Byte[7:0]
Section
0x0
Section Length = 2*n (n – number of registers to configure)
Section 6.9.1
0x1
Block CRC8
Section 6.9.2
0x2
PHY number and PHY register address
Section 6.9.3
0x3
PHY data (MDIC[15:0])
Section 6.9.4
…
2*n
PHY number and PHY register address
Section 6.9.3
2*n + 1
PHY data (MDIC[15:0])
Section 6.9.4
6.9.1
PHY Configuration Section Length - Offset 0x0
The section length word contains the length of the section in words. Note that section length count does
not include the section length word and Block CRC8 word.
Bits
Name
15
Reserved
14:0
Section_length
6.9.2
Default
Description
Section length in words.
Block CRC8 (Offset 0x1)
Bit
Name
15:8
Reserved
7:0
CRC8
6.9.3
Description
PHY Number and PHY Register Address (Offset 2*n; [n = 1... Section Length])
Bits
Name
Default
Description
15:12
Reserved
Reserved
11
Apply to port 3
If set, apply to programming when the PHY of port three is reset.
10
Apply to port 2
If set, apply to programming when the PHY of port two is reset.
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Intel® 82580EB/82580DB GbE Controller — PHY data (Offset 2*n + 1; [n = 1... Section Length])
Bits
Name
Default
Description
9
Apply to port 1
If set, apply to programming when the PHY of port one is reset.
8
Apply to port 0
If set, apply to programming when the PHY of port zero is reset.
7:0
PHY register address
PHY register address to which the data is written
6.9.4
PHY data (Offset 2*n + 1; [n = 1... Section Length])
Bits
15:0
Name
Default
Description
Reg_Data
6.10
MDIC[15:0] value (Data).
Sideband Configuration Structure
The Sideband Configuration Pointer (Word 0x57) points to the start (offset 0x0) of this structure. If
pointer is 0xFFFF then no structure exists.
6.10.1
Section Length (Offset 0x0)
The section length word contains the length of the section in words. Note that section length count does
not include the section length word and Block CRC8 word.
Bits
Name
15
Reserved
14:0
Section_length
6.10.2
Description
Section length in words.
Block CRC8 (Offset 0x1)
Bit
Name
15:8
Reserved
7:0
CRC8
6.10.3
Default
Description
SMBus Max Fragment Size (Offset 0x2)
Bit
Name
Description
15:8
Reserved
7:0
SMBus Max Fragment Size (Bytes) Maximum SMBus Fragment Size sent to BMC. Value should be in the 29 to
237 Byte range.
Reserved
Note: Fragment size should be a multiple of 4 + 1 (e.g. 29, 33, 37...).
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SMBus Notification Timeout (Offset 0x3) — Intel® 82580EB/82580DB GbE Controller
6.10.4
SMBus Notification Timeout (Offset 0x3)
Bit
15:0
Name
SMBus Notification Timeout
Description
Timeout until decision to discard a packet that was not read by the external
BMC.
Resolution of field is in 1.043 mSec units (e.g. a value of 8 results in a
timeout value of 8.344 mSec)
0b - No discard.
6.10.5
SMBus Slave Address 0 1 (Offset 0x4)
Bit
Name
Description
15:9
SMBus 1 Slave Address
SMBus Slave Address for port 1.
8
Reserved
Reserved.
7:1
SMBus 0 Slave Address
SMBus Slave Address for port 0.
0
Reserved
Reserved.
6.10.6
SMBus Slave Address 2 3 (Offset 0x5)
Bit
Name
Description
15:9
SMBus 3 Slave Address
SMBus Slave Address for port 3.
8
Reserved
Reserved.
7:1
SMBus 2 Slave Address
SMBus Slave Address for port 2.
0
Reserved
Reserved.
6.10.7
NC-SI Configuration (Offset 0x6)
Bit
Name
15:8
Reserved
7:5
Package ID
4:0
Reserved
6.10.8
Description
Reserved.
Reserved.
Reserved (Offset 0x7 - 0x8)
Reserved words should be 0x0000.
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Intel® 82580EB/82580DB GbE Controller — SMBus Flags (Offset 0x9)
6.10.9
SMBus Flags (Offset 0x9)
Bit
Name
Description
15:14
Reserved
Reserved
13
RX_P3_PAR_EN
Management RX Buffer parity check enable port 3
12
RX_P2_PAR_EN
Management RX Buffer parity check enable port 2
11
RX_P1_PAR_EN
Management RX Buffer parity check enable port 1
10
RX_P0_PAR_EN
Management RX Buffer parity check enable port 0
9
TX_PAR_EN
Management TX Buffer parity check enable
8
CMD_PAR_EN
Management ARC RAM parity check enable (Command RAM)
7:6
Reserved
Reserved
5
SMBus Block Read Command
0b = Block read command is C0.
1b = Block read command is D0.
4:3
Reserved
2
Disable SMBus ARP Functionality
Reserved
1
SMBus ARP PEC
0
Reserved
6.10.10
LAN Receive Enable 3 (Offset 0xA)
Bit
Name
Description
15:4
Reserved
Reserved
3
Enable BMC Dedicated MAC port 3 Configure BMC dedicated MAC Address on Port 3.
0b = The 82580EB/DB will share MAC address for MNG traffic with host MAC
address on Port 3. Host MAC address is specified in EEPROM words located at
LAN Base Address + offset 0x0-0x2 per port (See Section 6.2.1).
1b = The 82580EB/DB will use the BMC dedicated MAC address on port 3
(MAC address 1 (MMAL/H1) see Section 7.22.9) as filter for incoming receive
packets.
Note: MMAL/H registers can be programmed from the EEPROM using the PT
LAN Configuration structure (See Section 6.8.1).
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LAN0 MANC Value LSB (Offset 0xB) — Intel® 82580EB/82580DB GbE Controller
Bit
2
Name
Description
Enable BMC Dedicated MAC port 2 Configure BMC dedicated MAC Address on Port 2.
0b = The 82580EB/DB will share MAC address for MNG traffic with host MAC
address on Port 2. Host MAC address is specified in EEPROM words located at
LAN Base Address + offset 0x0-0x2 per port (See Section 6.2.1).
1b = The 82580EB/DB will use the BMC dedicated MAC address on port
2(MAC address 1(MMAL/H1) see Section 7.22.9) as filter for incoming
receive packets.
Note: MMAL/H registers can be programmed from the EEPROM using the PT
LAN Configuration structure (See Section 6.8.1).
1
Enable BMC Dedicated MAC port 1 Configure BMC dedicated MAC Address on Port 1.
0b = The 82580EB/DB will share MAC address for MNG traffic with host MAC
address on Port 1. Host MAC address is specified in EEPROM words located at
LAN Base Address + offset 0x0-0x2 per port (See Section 6.2.1).
1b = The 82580EB/DB will use the BMC dedicated MAC address on port
1(MAC address 1 (MMAL/H1) see Section 7.22.9) as filter for incoming
receive packets.
Note: MMAL/H registers can be programmed from the EEPROM using the PT
LAN Configuration structure (See Section 6.8.1).
0
Enable BMC Dedicated MAC port 0 Configure BMC dedicated MAC Address on Port 0.
0b = The 82580EB/DB will share MAC address for MNG traffic with host MAC
address on Port 0. Host MAC address is specified in EEPROM words located at
LAN Base Address + offset 0x0-0x2 per port (See Section 6.2.1).
1b = The 82580EB/DB will use the BMC dedicated MAC address on port 3
(MAC address 1 (MMAL/H1) see Section 7.22.9) as filter for incoming receive
packets.
Note: MMAL/H registers can be programmed from the EEPROM using the PT
LAN Configuration structure (See Section 6.8.1).
6.10.11
LAN0 MANC Value LSB (Offset 0xB)
This value will be stored in the LSB Portion of the LAN0 Management Control (MANC) register. See
Section 7.22.4 for register description.
Bit
Name
15
TCO_Isolate
14
FW_RESET
Description
TCO Isolate command.
Note: Value placed in this field is not written to MANC register.
FW Reset occurred.
Note: Value placed in this field is not written to MANC register.
13:0
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Reserved
Reserved.
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Intel® 82580EB/82580DB GbE Controller — LAN0 MANC Value MSB (Offset 0xC)
6.10.12
LAN0 MANC Value MSB (Offset 0xC)
This value will be stored in the MSB Portion of the LAN0 Management Control (MANC) register. See
Section 7.22.4 for register description.
Bit
Name
Description
15:11
Reserved
Reserved.
10
NET_TYPE
NET TYPE:
0b = pass only un-tagged packets.
1b = pass only VLAN tagged packets.
Valid only if FIXED_NET_TYPE is set.
9
FIXED_NET_TYPE
Fixed net type: If set, only packets matching the net type defined by the
NET_TYPE field passes to manageability. Otherwise, both tagged and untagged packets can be forwarded to the manageability engine.
8
EN_IPv4_FILTER
Enable IPv4 address Filters – when set, the last 128 bits of the MIPAF
register are used to store 4 IPv4 addresses for IPv4 filtering. When cleared,
these bits store a single IPv6 filter.
7
EN_XSUM_FILTER
Enable checksum filtering to MNG
When this bit is set, only packets that pass L3, L4 checksum are sent to the
MNG block.
6:4
Reserved
Reserved should be 0
3
Reserved
Reserved should be 0
2
KEEP_PHY_LINK_UP
Block PHY reset and power state changes. When this bit is set the PHY reset
and power state changes do not reach to the PHY (PHY is not reset), This bit
can not be written to, unless the Keep_PHY_Link_Up_En EEPROM bit is set.
1
RCV_TCO_EN
Enable BMC to network and network to BMC traffic
0b - The BMC can not communicate with the network.
1b - The BMC can communicate with the network
When cleared the BMC traffic is not forwarded to the network and the
network traffic is not forwarded to the BMC even if the decision filters
indicates it should. This bit does not impact the OS to BMC traffic.
0
TCO_RESET
TCO Reset occurred
Note: Value placed in this field is not written to MANC register.
6.10.13
LAN1 MANC Value LSB (Offset 0xD)
This value will be stored in the LSB Portion of the LAN1 Management Control (MANC) register. See
Section 7.22.4 for register description.
Bit
Name
15
TCO_Isolate
14
FW_RESET
Description
TCO Isolate command.
Note: Value placed in this field is not written to MANC register.
FW Reset occurred.
Note: Value placed in this field is not written to MANC register.
13:0
Reserved
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Reserved.
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LAN1 MANC Value MSB (Offset 0xE) — Intel® 82580EB/82580DB GbE Controller
6.10.14
LAN1 MANC Value MSB (Offset 0xE)
This value will be stored in the MSB Portion of the LAN1 Management Control (MANC) register. See
Section 7.22.4 for register description.
Bit
Name
Description
15:11
Reserved
Reserved.
10
NET_TYPE
NET TYPE:
0b = pass only un-tagged packets.
1b = pass only VLAN tagged packets.
Valid only if FIXED_NET_TYPE is set.
9
FIXED_NET_TYPE
Fixed net type: If set, only packets matching the net type defined by the
NET_TYPE field passes to manageability. Otherwise, both tagged and untagged packets can be forwarded to the manageability engine.
8
EN_IPv4_FILTER
Enable IPv4 address Filters – when set, the last 128 bits of the MIPAF
register are used to store 4 IPv4 addresses for IPv4 filtering. When cleared,
these bits store a single IPv6 filter.
7
EN_XSUM_FILTER
Enable checksum filtering to MNG
When this bit is set, only packets that pass L3, L4 checksum are sent to the
MNG block.
6:4
Reserved
Reserved should be 0
3
Reserved
Reserved should be 0
2
KEEP_PHY_LINK_UP
Block PHY reset and power state changes. When this bit is set the PHY reset
and power state changes do not reach to the PHY (PHY is not reset), This bit
can not be written to, unless the Keep_PHY_Link_Up_En EEPROM bit is set.
1
RCV_TCO_EN
Enable BMC to network and network to BMC traffic
The BMC can not communicate with the network.
The BMC can communicate with the network
When cleared the BMC traffic is not forwarded to the network and the
network traffic is not forwarded to the BMC even if the decision filters
indicates it should. This bit does not impact the OS to BMC traffic.
0
TCO_RESET
TCO Reset occurred
Note: Value placed in this field is not written to MANC register.
6.10.15
LAN2 MANC Value LSB (Offset 0xF)
This value will be stored in the LSB Portion of the LAN2 Management Control (MANC) register. See
Section 7.22.4 for register description.
Bit
Name
15
TCO_Isolate
14
FW_RESET
Description
TCO Isolate command.
Note: Value placed in this field is not written to MANC register.
FW Reset occurred.
Note: Value placed in this field is not written to MANC register.
13:0
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October 2011
Reserved
Reserved.
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Intel® 82580EB/82580DB GbE Controller — LAN2 MANC Value MSB (Offset 0x10)
6.10.16
LAN2 MANC Value MSB (Offset 0x10)
This value will be stored in the MSB Portion of the LAN2 Management Control (MANC) register. See
Section 7.22.4 for register description.
Bit
Name
Description
15:11
Reserved
Reserved.
10
NET_TYPE
NET TYPE:
0b = pass only un-tagged packets.
1b = pass only VLAN tagged packets.
Valid only if FIXED_NET_TYPE is set.
9
FIXED_NET_TYPE
Fixed net type: If set, only packets matching the net type defined by the
NET_TYPE field passes to manageability. Otherwise, both tagged and untagged packets can be forwarded to the manageability engine.
8
EN_IPv4_FILTER
Enable IPv4 address Filters – when set, the last 128 bits of the MIPAF
register are used to store 4 IPv4 addresses for IPv4 filtering. When cleared,
these bits store a single IPv6 filter.
7
EN_XSUM_FILTER
Enable checksum filtering to MNG
When this bit is set, only packets that pass L3, L4 checksum are sent to the
MNG block.
6:4
Reserved
Reserved should be 0
3
Reserved
Reserved should be 0
2
KEEP_PHY_LINK_UP
Block PHY reset and power state changes. When this bit is set the PHY reset
and power state changes do not reach to the PHY (PHY is not reset), This bit
can not be written to, unless the Keep_PHY_Link_Up_En EEPROM bit is set.
1
RCV_TCO_EN
Enable BMC to network and network to BMC traffic
The BMC can not communicate with the network.
The BMC can communicate with the network
When cleared the BMC traffic is not forwarded to the network and the
network traffic is not forwarded to the BMC even if the decision filters
indicates it should. This bit does not impact the OS to BMC traffic.
0
TCO_RESET
TCO Reset occurred
Note: Value placed in this field is not written to MANC register.
6.10.17
LAN3 MANC Value LSB (Offset 0x11)
This value will be stored in the LSB Portion of the LAN3 Management Control (MANC) register. See
Section 7.22.4 for register description.
Bit
Name
15
TCO_Isolate
14
FW_RESET
Description
TCO Isolate command.
Note: Value placed in this field is not written to MANC register.
FW Reset occurred.
Note: Value placed in this field is not written to MANC register.
13:0
Reserved
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Reserved.
Revision: 2.50
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LAN3 MANC Value MSB (Offset 0x12) — Intel® 82580EB/82580DB GbE Controller
6.10.18
LAN3 MANC Value MSB (Offset 0x12)
This value will be stored in the MSB Portion of the LAN3 Management Control (MANC) register. See
Section 7.22.4 for register description.
Bit
Name
Description
15:11
Reserved
Reserved.
10
NET_TYPE
NET TYPE:
0b = pass only un-tagged packets.
1b = pass only VLAN tagged packets.
Valid only if FIXED_NET_TYPE is set.
9
FIXED_NET_TYPE
Fixed net type: If set, only packets matching the net type defined by the
NET_TYPE field passes to manageability. Otherwise, both tagged and untagged packets can be forwarded to the manageability engine.
8
EN_IPv4_FILTER
Enable IPv4 address Filters – when set, the last 128 bits of the MIPAF
register are used to store 4 IPv4 addresses for IPv4 filtering. When cleared,
these bits store a single IPv6 filter.
7
EN_XSUM_FILTER
Enable checksum filtering to MNG
When this bit is set, only packets that pass L3, L4 checksum are sent to the
MNG block.
6:4
Reserved
Reserved should be 0
3
Reserved
Reserved should be 0
2
KEEP_PHY_LINK_UP
Block PHY reset and power state changes. When this bit is set the PHY reset
and power state changes do not reach to the PHY (PHY is not reset), This bit
can not be written to, unless the Keep_PHY_Link_Up_En EEPROM bit is set.
1
RCV_TCO_EN
Enable BMC to network and network to BMC traffic
The BMC can not communicate with the network.
The BMC can communicate with the network
When cleared the BMC traffic is not forwarded to the network and the
network traffic is not forwarded to the BMC even if the decision filters
indicates it should. This bit does not impact the OS to BMC traffic.
0
TCO_RESET
TCO Reset occurred
Note: Value placed in this field is not written to MANC register.
6.11
Software Accessed Words
Words 0x03 to 0x07 in the EEPROM image are reserved for compatibility information. New bits within
these fields will be defined as the need arises for determining software compatibility between various
hardware revisions.
Words 0x8 and 0x09 are used to indicate the Printed Board Assembly (PBA) number and words 0x42
and 0x43 identifies the EEPROM image.
Words 0x30 to 0x3E have been reserved for configuration and version values to be used by PXE code.
The only exceptions are word 0x3D, which is used for the iSCSI boot configuration and word 0x37 used
for Pointer to Alternate MAC address.
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Intel® 82580EB/82580DB GbE Controller — Compatibility (Word 0x03)
6.11.1
Compatibility (Word 0x03)
Bit
Name
Default
Description
15
Checksum Flag/
Reserved
0
0b = Only the checksum for LAN0 is valid
14:12
Reserved
0
Reserved
11
LOM
0
Indicates whether dedicated flash for the option ROM is attached to LAN silicon. Used by
option ROM update applications (DMIX).
1b = All 4 LAN checksum are valid.
0b: NIC (A dedicated flash is attached)
1b: LOM (No dedicated flash is attached)
10
Reserved
0
Reserved
9
Client
0
Client/Not a Client NIC
0b = Server.
1b = Client.
This bit is used by DMIX to verify the NIC is server or client. A team is required to have
server NIC or LOM.
1:8
Reserved
6.11.2
0
Reserved
Port Identification LED blinking (Word 0x04)
Driver software provides a method to identify an external port on a system through a command that
causes the LEDs to blink. Based on the setting in word 0x4, the LED drivers should blink between
STATE1 and STATE2 when a port identification command is issued.
When word 0x4 is equal to 0xFFFF or 0x0000, the blinking behavior reverts to a default.
Bit
15:12
Description
Control for LED 3
0000b or 1111b: Default LED Blinking operation is used.
0001b = Default in STATE1 + Default in STATE2.
0010b = Default in STATE1 + LED is ON in STATE2.
0011b = Default in STATE1 + LED is OFF in STATE2.
0100b = LED is ON in STATE1 + Default in STATE2.
0101b = LED is ON in STATE1 + LED is ON in STATE2.
0110b = LED is ON in STATE1 + LED is OFF in STATE2.
0111b = LED is OFF in STATE1 + Default in STATE2.
1000b = LED is OFF in STATE1 + LED is ON in STATE2.
1001b = LED is OFF in STATE1 + LED is OFF in STATE2.
All other values are Reserved.
11:8
Control for LED 2 – same encoding as for LED 3.
7:4
Control for LED 1 – same encoding as for LED 3.
3:0
Control for LED 0 – same encoding as for LED 3.
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EEPROM Image Revision (Word 0x05) — Intel® 82580EB/82580DB GbE Controller
6.11.3
EEPROM Image Revision (Word 0x05)
This word is valid only for device starter images and indicates the ID and version of the EEPROM image.
Bit
Description
15:12
EEPROM major version.
11:4
EEPROM minor version.
3:0
EEPROM image ID.
6.11.4
OEM Specific (Word 0x06, 0x07)
These words are available for OEM use.
6.11.5
PBA Number Module (Word 0x08, 0x09)
The nine-digit Printed Board Assembly (PBA) number used for Intel manufactured Network Interface
Cards (NICs) is stored in EEPROM.
Through the course of hardware ECOs, the suffix field is incremented. The purpose of this information is
to enable customer support (or any user) to identify the revision level of a product.
Network driver software should not rely on this field to identify the product or its capabilities.
PBA numbers have exceeded the length that can be stored as HEX values in two words. For newer NICs,
the high word in the PBA Number Module is a flag (0xFAFA) indicating that the actual PBA is stored in a
separate PBA block. The low word is a pointer to the starting word of the PBA block.
The following shows the format of the PBA Number Module field for new products.
PBA Number
G23456-003
Word 0x8
FAFA
Word 0x9
Pointer to PBA Block
The following provides the format of the PBA block; pointed to by word 0x9 above:
Word Offset
Description
0x0
Length in words of the PBA Block (default is 0x6)
0x1 ... 0x5
PBA Number stored in hexadecimal ASCII values.
The new PBA block contains the complete PBA number and includes the dash and the first digit of the 3digit suffix which were not included previously. Each digit is represented by its hexadecimal-ASCII
values.
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Intel® 82580EB/82580DB GbE Controller — PXE Configuration Words (Word 0x30:3B)
The following shows an example PBA number (in the new style):
Word
Offset 0
PBA Number
G23456-003
0006
6 words
Word
Offset 1
Word
Offset 2
Word
Offset 3
4732
3334
3536
G2
34
56
Word
Offset 4
2D30
-0
Word
Offset 5
3033
03
Older NICs have PBA numbers starting with [A,B,C,D,E] and are stored directly in words 0x8-0x9. The
dash in the PBA number is not stored; nor is the first digit of the 3-digit suffix (the first digit is always
0b for older products).
The following example shows a PBA number stored in the PBA Number Module field (in the old style):
PBA Number
Byte 1
E23456-003
Byte 2
E2
6.11.6
34
Byte 3
56
Byte 4
03
PXE Configuration Words (Word 0x30:3B)
PXE configuration is controlled by the words.
6.11.6.1
Setup Options PCI Function 0 (Word 0x30)
The main setup options are stored in word 0x30. These options are those that can be changed by the
user via the Control-S setup menu. Word 0x30 has the following format:
Bit(s)
Value
Name
15:13
0
RFU
12:10
000
FSD
Function
Reserved. Must be 0.
Bits 12-10 control forcing speed and duplex during driver operation.
Valid values are:
000b
001b
010b
011b
100b
101b
111b
–
–
–
–
–
–
–
Auto-negotiate
10Mbps Half Duplex
100Mbps Half Duplex
Not valid (treated as 000b)
10Mbps Full Duplex
100Mbps Full Duplex
1000Mbps Full Duplex
Default value is 000b.
9
0
RSV
Reserved. Set to 0.
9
0
RFU
Reserved. Must be 0.
8
1
DSM
Display Setup Message.
If the bit is set to 1, the “Press Control-S” message is displayed after the title message.
Default value is 1.
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Bit(s)
7-:6
Value
00
Name
PT
Function
Prompt Time.
These bits control how long the CTRL-S setup prompt message is displayed, if enabled
by DIM.
00
01
10
11
=
=
=
=
2
3
5
0
seconds (default)
seconds
seconds
seconds
Note: CTRL-S message is not displayed if 0 seconds prompt time is selected.
5
0
Reserved
Reserved
4:3
00
DBS
Default Boot Selection.
These bits select which device is the default boot device. These bits are only used if the
agent detects that the BIOS does not support boot order selection or if the MODE field of
word 0x31 is set to MODE_LEGACY.
00 = Network boot, then local boot (default)
01 = Local boot, then network boot
10 = Network boot only
11 = Local boot only
Value
2:0
Port Status
CLP
(Combo)
Executes
iSCSI Boot Option ROM CTRL-D
Menu
FCoE Boot Option ROM
CTRL-D Menu
101-111
Reserved
100
FCoE
011
iSCSI Secondary iSCSI
Displays port as iSCSI
Secondary.
Allows changing to Boot Disabled,
iSCSI Primary.
Displays port as iSCSI.
Allows changing to Boot
Disabled, FCoE Enabled.
010
iSCSI Primary
iSCSI
Displays port as iSCSI
Primary.
Allows changing to Boot Disabled,
iSCSI Secondary.
Displays port as iSCSI.
Allows changing to Boot
Disabled, FCoE Enabled.
001
Boot Disabled
NONE
Displays port as Disabled.
Allows changing to iSCSI Primary/
Secondary.
Displays port as Disabled.
Allows changing to FCoE
enabled.
000
PXE
PXE
Displays port as PXE.
Allows changing to Boot Disabled,
iSCSI Primary or Secondary.
Displays port as PXE.
Allows changing to
Boot Disabled, FCoE Enabled.
6.11.6.2
FCOE
Displays port as FCoE.
Displays port as FCoE.
Allows changing to Boot
Allows changing port to Boot
Disabled, iSCSI Primary or Secondary. Disabled.
Configuration Customization Options PCI Function 0 (Word
0x31)
Word 0x31 of the EEPROM contains settings that can be programmed by an OEM or network
administrator to customize the operation of the software. These settings cannot be changed from within
the Control-S setup menu. The lower byte contains settings that would typically be configured by a
network administrator using an external utility; these settings generally control which setup menu
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Intel® 82580EB/82580DB GbE Controller — PXE Configuration Words (Word 0x30:3B)
options are changeable. The upper byte is generally settings that would be used by an OEM to control
the operation of the agent in a LOM environment, although there is nothing in the agent to prevent
their use on a NIC implementation. The default value for this word is 4000h.
Bit(s)
Name
Function
15:14
SIG
Signature. Must be set to 01 to indicate that this word has been programmed by the agent or other
configuration software.
13
RFU
Reserved. Must be 0.
12
RFU
Reserved. Must be 0.
11
RETRY
Selects Continuous Retry operation.
If this bit is set, IBA will NOT transfer control back to the BIOS if it fails to boot due to a network error
(such as failure to receive DHCP replies). Instead, it will restart the PXE boot process again. If this bit is
set, the only way to cancel PXE boot is for the user to press ESC on the keyboard. Retry will not be
attempted due to hardware conditions such as an invalid EEPROM checksum or failing to establish link.
Default value is 0.
10:8
MODE
Selects the agent’s boot order setup mode.
This field changes the agent’s default behavior in order to make it compatible with systems that do not
completely support the BBS and PnP Expansion ROM standards. Valid values and their meanings are:
000b
Normal behavior. The agent will attempt to detect BBS and PnP Expansion ROM support as it
normally does.
001b
Force Legacy mode. The agent will not attempt to detect BBS or PnP Expansion ROM supports in
the BIOS and will assume the BIOS is not compliant. The user can change the BIOS boot order in
the Setup Menu.
010b
Force BBS mode. The agent will assume the BIOS is BBS-compliant, even though it may not be
detected as such by the agent’s detection code. The user can NOT change the BIOS boot order in
the Setup Menu.
011b
Force PnP Int18 mode. The agent will assume the BIOS allows boot order setup for PnP
Expansion ROMs and will hook interrupt 18h (to inform the BIOS that the agent is a bootable
device) in addition to registering as a BBS IPL device. The user can NOT change the BIOS boot
order in the Setup Menu.
100b
Force PnP Int19 mode. The agent will assume the BIOS allows boot order setup for PnP
Expansion ROMs and will hook interrupt 19h (to inform the BIOS that the agent is a bootable
device) in addition to registering as a BBS IPL device. The user can NOT change the BIOS boot
order in the Setup Menu.
101b
Reserved for future use. If specified, is treated as a value of 000b.
110b
Reserved for future use. If specified, is treated as a value of 000b.
111b
Reserved for future use. If specified, is treated as a value of 000b.
7
RFU
Reserved. Must be 0.
6
RFU
Reserved. Must be 0.
5
DFU
Disable Flash Update.
4
DLWS
If this bit is set to 1, the user is not allowed to update the flash image using PROSet. Default value is 0.
Disable Legacy Wakeup Support.
If this bit is set to 1, the user is not allowed to change the Legacy OS Wakeup Support menu option.
Default value is 0.
3
DBS
Disable Boot Selection.
2
DPS
Disable Protocol Select. If set to 1, the user is not allowed to change the boot protocol. Default value is 0.
1
DTM
Disable Title Message.
If this bit is set to 1, the user is not allowed to change the boot order menu option. Default value is 0.
If this bit is set to 1, the title message displaying the version of the Boot Agent is suppressed; the ControlS message is also suppressed. This is for OEMs who do not wish the boot agent to display any messages
at system boot. Default value is 0.
0
DSM
Disable Setup Menu.
If this bit is set to 1, the user is not allowed to invoke the setup menu by pressing Control-S. In this case,
the EEPROM may only be changed via an external program. Default value is 0.
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6.11.6.3
PXE Version (Word 0x32)
Word 0x32 of the EEPROM is used to store the version of the boot agent that is stored in the flash
image. When the Boot Agent loads, it can check this value to determine if any first-time configuration
needs to be performed. The agent then updates this word with its version. Some diagnostic tools to
report the version of the Boot Agent in the flash also read this word. The format of this word is:
Bit(s)
Name
Function
15 - 12
MAJ
PXE Boot Agent Major Version.
11 – 8
MIN
PXE Boot Agent Minor Version.
7–0
BLD
PXE Boot Agent Build Number.
6.11.6.4
IBA Capabilities (Word 0x33)
Word 0x33 of the EEPROM is used to enumerate the boot technologies that have been programmed into
the flash. This is updated by flash configuration tools and is not updated or read by IBA.
Bit(s)
Name
Function
15 - 14
SIG
Signature. Must be set to 01 to indicate that this word has been programmed by the agent or other
configuration software.
13 – 5
RFU
Reserved. Must be 0.
4
ISCSI
iSCSI Boot is present in flash if set to 1.
3
EFI
EFI UNDI driver is present in flash if set to 1.
2
RPL
RPL module is present in flash if set to 1.
1
UNDI
PXE UNDI driver is present in flash if set to 1.
0
BC
PXE Base Code is present in flash if set to 1.
6.11.6.5
Setup Options PCI Function 1 (Word 0x34)
This word is the same as word 0x30, but for function 1 of the device.
6.11.6.6
Configuration Customization Options PCI Function 1 (Word
0x35)
This word is the same as word 0x31, but for function 1 of the device.
6.11.6.7
Setup Options PCI Function 2 (Word 0x38)
This word is the same as word 0x30, but for function 2 of the device.
6.11.6.8
Configuration Customization Options PCI Function 2 (Word
0x39)
This word is the same as word 0x31, but for function 2 of the device.
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6.11.6.9
Setup Options PCI Function 3 (Word 0x3A)
This word is the same as word 0x30, but for function 3 of the device.
6.11.6.10
Configuration Customization Options PCI Function 3
(Word 0x3B)
This word is the same as word 0x31, but for function 3 of the device.
6.11.7
iSCSI Boot Configuration Pointer (Word 0x3D)
Bit
15:0
Name
Description
iSCSI Address
iSCSI Configuration Block EEPROM Offset
Offset of iSCSI configuration block from the start of the EEPROM. If set to 0000h or
FFFFh there is no EEPROM configuration data available for the iSCSI adapter. In this case
configuration data must be provided by the BIOS through the SM CLP interface.
6.11.7.1
iSCSI Module Structure
The table below defines the layout of the iSCSI boot configuration block stored in EEPROM. EEPROM
word 0x3D described above stores the offset within the EEPROM of the configuration block. Software
must first read word 0x3D to determine the offset of the configuration table before attempting to read
or write the configuration block.
The strings defined below are stored in UTF-8 encoding and NULL terminated. All data words are stored
in little-endian (Intel) byte order.
Size in
Bytes
Configuration Item
Comments
iSCSI Boot Signature
2
‘i’, ‘S’
iSCSI Block Size
2
The structure size is stored in this field and is set depending on the amount of free
EEPROM space available. The total size of this structure, including variable length
fields, must fit within this space.
Structure Version
1
Version of this structure. Should be set to one.
Reserved
1
Reserved for future use.
Initiator Name
255 + 1
iSCSI Initiator Name - This field is optional and can also be built by DHCP.
Reserved
34
Reserved for future use.
Below fields are per port
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Size in
Bytes
Configuration Item
Flags
2
Comments
Bit 0  Enable DHCP
0 - Use static configurations from this structure
1 - Overrides configurations retrieved from DHCP.
Bit 01h  Enable DHCP for getting iSCSI target information.
0 - Use static target configuration
1 - Use DHCP to get target information.
Bit 02h - 03h  Authentication Type
00 - none
01 - one way chap
02 - mutual chap
Bit 04h - 05h  Ctrl-D setup menu
00 - enabled
03 - disabled
Bit 06h - 07h  Reserved
Bit 08h - 09h  ARP Retries
Retry value
Bit 0Ah - 0Fh  ARP Timeout
Timeout value for each retry
Initiator IP
4
DHCP flag not set  This field should contain the configured IP address.
DHCP flag set  If DHCP bit is set this field is ignored.
Initiator Subnet Mask
4
DHCP flag not set  This field should contain the configured subnet mask.
DHCP flag set  If DHCP bit is set this field is ignored.
Initiator Gateway
4
DHCP flag not set  This field should contain the configured gateway
DHCP flag set  If DHCP bit is set this field is ignored.
Boot LUN
2
DHCP flag not set  Target LUN that Initiator will be attached to.
DHCP flag set  If DHCP bit is set this field is ignored.
Target IP
4
DHCP flag not set  IP address of iSCSI target.
DHCP flag set  If DHCP bit is set this field is ignored.
Target Port
2
DHCP flag not set  IP port of iSCSI target. Default is 3260.
DHCP flag set  If DHCP bit is set this field is ignored
Target Name
255 + 1
DHCP flag set  If DHCP bit is set this field is ignored
CHAP Password
16 + 2
The minimum CHAP secret must be 12 octets and maximum CHAP secret size is 16.
1 byte is reserved for alignment padding and 1 byte for null.
CHAP User Name
127 + 1
The user name must be non-null value and maximum size of user name allowed is
127 characters.
Vlan ID
2
Vlan Id to be used for iSCSI boot traffic. a valid Vlan ID is between 1 and 4094
Mutual CHAP Password
16 + 2
The minimum mutual CHAP secret must be 12 octets and maximum CHAP secret
size is 16. 1 byte is reserved for alignment padding and 1 byte for null.
Reserved
160
Reserved for future use.
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6.11.8
Alternate MAC address pointer (Word 0x37)
This word may point to a location in the EEPROM containing additional MAC addresses used by system
management functions. If the additional MAC addresses are not supported, the word shall be set to
0xFFFF. The structure of the alternate MAC address block can be found in Table 6-8.
Table 6-8.
Alternate MAC Address Block
Word Offset
Description1
0x0... 0x2
Alternate MAC Address for LAN port assigned to PCI function 0
0x3... 0x5
Alternate MAC Address for LAN port assigned to PCI function 1
0x6... 0x8
Alternate MAC Address for LAN port assigned to PCI function 2
0x9... 0xB
Alternate MAC Address for LAN port assigned to PCI function 3
1. An alternate MAC Address value of 0xFFFF-FFFF-FFFF means that no alternate MAC address is present for the port.
6.11.9
Checksum Word (Offset 0x3F)
The checksum words (Offset 0x3F from start of Common, LAN 1, LAN 2 and LAN 3 sections) are used to
ensure that the base EEPROM image is a valid image. The value of this word should be calculated such
that after adding all the words (0x00:0x3E), including the checksum word itself, the sum should be
0xBABA. The initial value in the 16-bit summing register should be 0x0000 and the carry bit should be
ignored after each addition.
Note:
6.11.10
Hardware does not calculate the checksum word during EEPROM write; it must be
calculated by software independently and included in the EEPROM write data. Hardware
does not compute a checksum over words 0x00:0x3F during EEPROM reads in order to
determine validity of the EEPROM image; this field is provided strictly for software
verification of EEPROM validity. All hardware configurations based on word 0x00:0x3F
content is based on the validity of the Signature field of the EEPROM Sizing & Protected
Fields EEPROM word (Signature must be 01b).
Image Unique ID (Word 0x42, 0x43)
These words contain a unique 32-bit ID for each image generated by Intel to enable tracking of images
and comparison to the original image if testing a customer EEPROM image.
§§
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Programming Interface — Intel® 82580EB/82580DB GbE Controller
7.0
Programming Interface
7.1
Introduction
This chapter details the programmer visible state inside the 82580EB/DB. In some cases, it describes
hardware structures invisible to software in order to clarify a concept. The 82580EB/DB's address space
is mapped into four regions with PCI Base Address Registers described in Section 9.4.11. These regions
are listed in the table below.
Table 7-1.
Address Space Regions
Addressable Content
How Mapped
Size of Region
Internal registers, memories and FLASH (“Memory BAR”)
Direct memory-mapped
128K + FLASH Size (1,2)
Flash (optional)
Direct memory-mapped
64K-8M
Expansion ROM (optional)
Direct memory-mapped
64K-8M (2)
Internal registers and memories, Flash (optional)
I/O Window mapped
32 bytes (3)
MSI-X (optional)
Direct memory-mapped
16K
(1) The FLASH size is defined by the BARCTRL register
(2) The FLASH space in the “Memory CSR” and Expansion ROM Base Address map the same FLASH
memory. Accessing the “memory BAR” at offset 128K and Expansion ROM at offset 0x0 are mapped to
the FLASH device at offset 0x0.
(3) The internal registers and memories can be accessed though I/O space indirectly as explained
below.
The internal register/memory space is described in the following sections. The PHY registers are
accessed through the MDIO interface.
7.1.1
7.1.1.1
Memory, I/O Address and Configuration Decoding
Memory-Mapped Access to Internal Registers and Memories
The internal registers and memories might be accessed as direct memory-mapped offsets from the
base address register (BAR0 or BAR 0/1 see Section 9.4.11). See Section 7.1.3 for the appropriate
offset for each specific internal register.
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7.1.1.2
Memory-Mapped Access to Flash
The external Flash may be accessed using direct memory-mapped offsets from the Memory base
address register (BAR0 in 32bit addressing or BAR0/BAR1 in 64 bit addressing see Section 9.4.11). For
accesses, the offset from the Memory BAR minus 128KB corresponds to the physical address within the
external Flash device. Memory mapped accesses to the external Flash are enabled when the value of
the Flash Size field in the Initialization Control Word 2 EEPROM word is not 000b.
7.1.1.3
Memory-Mapped Access to MSI-X Tables
The MSI-X tables may be accessed as direct memory-mapped offsets from the base address register
(BAR3 see Section 9.4.11). See Section 7.1.3 for the appropriate offset for each specific internal MSIX
register.
7.1.1.4
Memory-Mapped Access to Expansion ROM
The external Flash might also be accessed as a memory-mapped expansion ROM. Accesses to offsets
starting from the Expansion ROM Base address (see Section 9.4.11) reference the Flash provided that
access is enabled thorough the LAN Boot Disable bit in the Initialization Control 3 EEPROM word, and if
the Expansion ROM Base Address register contains a valid (non-zero) base memory address.
7.1.1.5
I/O-Mapped Access to Internal Registers and Memories
To support pre-boot operation (prior to the allocation of physical memory base addresses), all internal
registers and memories can be accessed using I/O operations. I/O accesses are supported only if an I/
O Base Address is allocated and mapped (BAR2 see Section 9.4.11), the BAR contains a valid (non-zero
value), and I/O address decoding is enabled in the PCIe configuration.
When an I/O BAR is mapped, the I/O address range allocated opens a 32-byte “window” in the system
I/O address map. Within this window, two I/O addressable registers are implemented: IOADDR and
IODATA. The IOADDR register is used to specify a reference to an internal register or memory, and then
the IODATA register is used as a “window” to the register or memory address specified by IOADDR:
Table 7-2.
IOADDR and IODATA in I/O Address Space
Offset
Abbreviation
0x00
IOADDR
Name
RW
Size
Internal Register or Internal Memory location address.
RW
4 bytes
0x00000-0x1FFFF – Internal Registers and Memories
0x20000-0xFFFFFFFF – Undefined
0x04
IODATA
Data field for reads or writes to the Internal Register or Internal
Memory Location as identified by the current value in IOADDR. All
32 bits of this register are read/write-able.
RW
4 bytes
0x08 – 0x1F
Reserved
Reserved
RO
4 bytes
7.1.1.5.1
IOADDR (I/O offset 0x00)
The IOADDR register must always be written as a DWORD access. Writes that are less than 32 bits are
ignored. Reads of any size return a DWORD of data; however, the chipset or CPU might only return a
subset of that DWORD.
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For software programmers, the IN and OUT instructions must be used to cause I/O cycles to be used on
the PCIe bus. Because writes must be to a 32-bit quantity, the source register of the OUT instruction
must be EAX (the only 32-bit register supported by the OUT command). For reads, the IN instruction
can have any size target register, but it is recommended that the 32-bit EAX register be used.
Because only a particular range is addressable, the upper bits of this register are hard coded to zero.
Bits 31 through 20 are not write-able and always read back as 0b.
At hardware reset (LAN_PWR_GOOD) or PCI Reset, this register value resets to 0x00000000. Once
written, the value is retained until the next write or reset.
7.1.1.5.2
IODATA (I/O offset 0x04)
The IODATA register must always be written as a DWORD access when the IOADDR register contains a
value for the Internal Register and Memories (for example, 0x00000-0x1FFFC). In this case, writes that
are less than 32 bits are ignored.
Reads to IODATA of any size returns a DWORD of data. However, the chipset or CPU might only return
a subset of that DWORD.
For software programmers, the IN and OUT instructions must be used to cause I/O cycles to be used on
the PCIe bus. Where 32-bit quantities are required on writes, the source register of the OUT instruction
must be EAX (the only 32-bit register supported by the OUT command).
Writes and reads to IODATA when the IOADDR register value is in an undefined range (0x200000xFFFFFFFC) should not be performed. Results cannot be determined.
Notes:
There are no special software timing requirements on accesses to IOADDR or IODATA. All
accesses are immediate, except when data is not readily available or acceptable. In this
case, 82580EB/DB delays the results through normal bus methods (for example, split
transaction or transaction retry).
Because a register/memory read or write takes two IO cycles to complete, software must
provide a guarantee that the two IO cycles occur as an atomic operation. Otherwise, results
can be non-deterministic from the software viewpoint.
7.1.1.5.3
Undefined I/O offsets
I/O offsets 0x08 through 0x1F are considered to be reserved offsets with the I/O window. Dword reads
from these addresses returns 0xFFFF; writes to these addresses are discarded.
7.1.1.6
Configuration Access to Internal Registers and Memories
To support 'legacy' pre-boot 16-bit operating environments without requiring IO address space, the
82580EB/DB enables accessing CSRs via configuration address space by mapping the IOADDR and
IODATA registers into configuration address space. The registers mapping in this case is shown in
Table 7-3.
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Table 7-3.
IOADDR and IODATA in Configuration Address space
Configuration
Address
Abbreviation
Name
RW
Size
0x98
IOADDR
Internal register or internal memory location address.
RW
4 bytes
RW
4 bytes
0x00000-0x1FFFF – Internal Registers and Memories
0x20000-0x7FFFFF – Undefined
0x9C
IODATA
Data field for reads or writes to the internal register or internal memory
location as identified by the current value in IOADDR. All 32 bits of this
register are read/write-able.
Software writes data to an internal CSR via Configuration space in the following manner:
1. CSR address is written to the IOADDR register where:
a.
Bit 31 (IOADDR.Configuration IO Access Enable) of the The IOADDR register should be set to 1.
b.
Bits 30:0 of IOADDR should hold the actual address of the internal register or memory being
written to.
2. Data to be written is written into the IODATA register.
— The IODATA register is used as a “window” to the register or memory address specified by
IOADDR register. As a result the data written to the IODATA register is written into the CSR
pointed to by bits 30:0 of the IOADDR register.
3. IOADDR.Configuration IO Access Enable is cleared, to avoid un-intentional CSR read operations
(that may cause clear by read) by other applications scanning the configuration space.
Software reads data from an internal CSR via Configuration space in the following manner:
1. CSR address is written to the IOADDR register where:
a.
Bit 31 (IOADDR.Configuration IO Access Enable) of the The IOADDR register should be set to 1.
b.
Bits 30:0 of IOADDR should hold the actual address of the internal register or memory being
read.
2. CSR value is read from the IODATA register.
a.
The IODATA register is used as a “window” to the register or memory address specified by
IOADDR register. As a result the data read from the IODATA register is the data of the CSR
pointed to by bits 30:0 of the IOADDR register
3. IOADDR.Configuration IO Access Enable is cleared, to avoid un-intentional CSR read operations
(that may cause clear by read) by other applications scanning the configuration space.
Notes:
When Function is in D3 state Software should not attempt to access CSRs via the IOADDR
and IODATA Configuration registers.
To enable CSR access via configuration space, Software should set to 1 bit 31
(IOADDR.Configuration IO Access Enable) of the IOADDR register. Software should clear bit
31 of the IOADDR register after completing CSR access to avoid an unintentional “clear by
read” operation, by another application scanning the configuration address space.
Bit 31 of the IOADDR register (IOADDR.Configuration IO Access Enable) has no effect when
initiating access via IO Address space.
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Register Conventions — Intel® 82580EB/82580DB GbE Controller
7.1.2
Register Conventions
All registers in the 82580EB/DB are defined to be 32 bits, should be accessed as 32 bit double-words,
There are some exceptions to this rule:
• Register pairs where two 32 bit registers make up a larger logical size
• Accesses to Flash memory (via Expansion ROM space, secondary BAR space, or the I/O space)
might be byte, word or double word accesses.
Reserved bit positions: Some registers contain certain bits that are marked as “reserved”. These bits
should never be set to a value of “one” by software. Reads from registers containing reserved bits
might return indeterminate values in the reserved bit-positions unless read values are explicitly stated.
When read, these reserved bits should be ignored by software.
Reserved and/or undefined addresses: any register address not explicitly declared in this specification
should be considered to be reserved, and should not be written to. Writing to reserved or undefined
register addresses might cause indeterminate behavior. Reads from reserved or undefined configuration
register addresses might return indeterminate values unless read values are explicitly stated for
specific addresses.
Initial values: most registers define the initial hardware values prior to being programmed. In some
cases, hardware initial values are undefined and is listed as such via the text “undefined”, “unknown”,
or “X”. Such configuration values might need to be set via EEPROM configuration or via software in
order for proper operation to occur; this need is dependent on the function of the bit. Other registers
might cite a hardware default which is overridden by a higher-precedence operation. Operations which
might supersede hardware defaults might include a valid EEPROM load, completion of a hardware
operation (such as hardware auto-negotiation), or writing of a different register whose value is then
reflected in another bit.
For registers that should be accessed as 32 bit double words, partial writes (less than a 32 bit double
word) does not take effect (the write is ignored). Partial reads returns all 32 bits of data regardless of
the byte enables.
Note:
Partial reads to read-on-clear registers (ICR) can have unexpected results since all 32 bits
are actually read regardless of the byte enables. Partial reads should not be done.
All statistics registers are implemented as 32 bit registers. Though some logical statistics
registers represent counters in excess of 32-bits in width, registers must be accessed using
32-bit operations (for example, independent access to each 32-bit field). When reading 64
bits statistics registers the least significant 32 bit register should be read first.
See special notes for VLAN Filter Table, Multicast Table Arrays and Packet Buffer Memory which appear
in the specific register definitions.
The 82580EB/DB register fields are assigned one of the attributes described in Table 7-4.
Table 7-4.
82580EB/DB Register Field Attributes
Attribute
Description
RW
Read-Write field: Register bits are read-write and can be either set or cleared by software to the desired state.
RWS
Read-Write Status field: Register bits are read-write and can be either set or cleared by software to the desired
state. However, the value of this field might be changed by the hardware to reflect a status change.
RO
Read-only register: Register bits are read-only and should not be altered by software. Register bits might be
initialized by hardware mechanisms such as pin strapping, serial EEPROM or reflect a status of the hardware state.
R/W1C
Read-only status, Write-1-to-clear status register: Register bits indicate status when read, a set bit indicating a
status event can be cleared by writing a 1b. Writing a 0b to R/W1C bit has no effect.
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Table 7-4.
82580EB/DB Register Field Attributes (Continued)
Rsv
Reserved. Write 0 to these fields and ignore read.
RC
Read-only status, Read-to-clear status register: Register bits indicate status when read, a set bit indicating a status
event is cleared by reading it.
SC
Self Clear field: a command field that is self clearing. These field are always read as zero.
WO
Write only field: a command field that can not be read, These field read values are undefined.
RC/W
Read-Write status, Read-to-clear status register: Read-to-clear status register. Register bits indicate status when
read. Register bits are read-write and can be either set or cleared by software to the desired state.
RC/W1C
Read-only status, Write-1-to-clear status register: Read-to-clear status register. Register bits indicate status when
read, a set bit indicating a status event can be cleared by writing a 1b or by reading the register. Writing a 0b to RC/
W1C bit has no effect.
RS
Read Set – This is the attribute used for Semaphore bits. These bits are set by read in case the previous values were
zero. In this case the read value is zero; otherwise the read value is one. Cleared by write zero.
PHY registers described in Section 7.2.5 use a special nomenclature to define the read/write mode of
individual bits in each register. See table bellow for details.
Table 7-5.
PHY Register Nomenclature
Register Mode
Description
LH
Latched High. Event is latched and erased when read.
LL
Latched Low. Event is latched and erased when read. For example, Link Loss is latched when the PHY
Control Register bit 2 = 0b. After read, if the link is good, the PHY Control Register bit 2 is set to 1b.
RO
Read Only.
R/W
Read and Write.
SC
Self-Clear. The bit is set, automatically executed, and then reset to normal operation.
CR
Clear after Read. For example, 1000BASE-T Status Register bits 7:0 (Idle Error Counter).
Update
Value written to the register bit does not take effect until software PHY reset is executed.
Note:
For all binary equations appearing in the register map, the symbol “|” is equivalent to a
binary OR operation.
7.1.2.1
Registers Byte Ordering
This section defines the structure of registers that contain fields carried over the network. Some
examples are L2, L3 and L4 fields.
The following example is used to describe byte ordering over the wire (hex notation):
Last
First
...,06, 05, 04, 03, 02, 01, 00
Each byte is sent with the LSbit first. That is, the bit order over the wire for this example is
Last
First
..., 0000 0011, 0000 0010, 0000 0001, 0000 0000
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The general rule for register ordering is to use Host Ordering (also called little endian). Using the
above example, a 6-byte fields (MAC address) is stored in a CSR in the following manner:
Byte 3 Byte 2 Byte 1 Byte0
DW address (N)
0x03
DW address (N+4) ...
0x02
0x01
0x00
...
0x05
0x04
The exceptions listed below use network ordering (also called big endian). Using the above example, a
16-bit field (EtherType) is stored in a CSR in the following manner:
Byte 3 Byte 2 Byte 1 Byte0
(DW aligned)
...
...
0x00
0x01
0x00
0x01
...
...
or
(Word aligned)
The following exceptions use network ordering:
All ETherType fields. For example, the VET EXT field in the VET register, the EType field in the ETQF
register, the EType field in the METF register.
Note:
The “normal” notation as it appears in text books, etc. is to use network ordering. Example:
Suppose a MAC address of 00-A0-C9-00-00-00. The order on the network is 00, then A0,
then C9, etc. However, the host ordering presentation would be:
Byte 3 Byte 2 Byte 1 Byte0
DW address (N)
00
DW address (N+4) ...
7.1.3
C9
A0
00
...
00
00
Register Summary
All the 82580EB/DB's non-PCIe configuration registers, except for the MSI-X register, are listed in the
table below. These registers are ordered by grouping and are not necessarily listed in order that they
appear in the address space.
Table 7-6.
Offset
Register Summary
Alias Offset
Abbreviation
Name
RW
General
0x0000
0x0004
CTRL
Device Control Register
0x0008
N/A
STATUS
Device Status Register
RW
RO
0x0018
N/A
CTRL_EXT
Extended Device Control Register
RW
0x0020
N/A
MDIC
MDI Control Register
RW
0x0E08
N/A
P1GCTRL0
Serdes Control 0
RW
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Table 7-6.
Register Summary (Continued)
Offset
Alias Offset
Abbreviation
Name
RW
0x0028
N/A
FCAL
Flow Control Address Low
RO
0x002C
N/A
FCAH
Flow Control Address High
RO
0x0030
N/A
FCT
Flow Control Type
RW
0x0034
N/A
CONNSW
Copper/Fiber switch control
RW
0x0038
N/A
VET
VLAN Ether Type
RW
0x0E04
N/A
MDICNFG
MDC/MDIO Configuration Register
RW
0x0170
N/A
FCTTV
Flow Control Transmit Timer Value
RW
0x0E00
N/A
LEDCTL
LED Control Register
RW
0x1028
N/A
I2CCMD
SFP I2C command
RW
0x102C
N/A
I2CPARAMS
SFP I2C Parameter
RW
0x1040
N/A
WDSTP
Watchdog setup register
RW
0x1044
N/A
WDSWSTS
Watchdog Software
RW
0x1048
N/A
FRTIMER
Free Running Timer
RWS
0x104C
N/A
TCPTimer
TCP timer
RW
0x2508
N/A
DMACR
DMA Coalescing Control Register
RW
0x2514
N/A
DMCTLX
DMA Coalescing Time to LX Request
RW
0x3550
N/A
DMCTXTH
DMA Coalescing Transmit Threshold
RW
0x5B70
N/A
DCA_ID
DCA Requester ID Information Register
RO
0x5B50
N/A
SWSM
Software Semaphore Register
RW
0x5B54
N/A
FWSM
Firmware Semaphore Register
RWS
0x5B5C
N/A
SW_FW_SYNC
Software-Firmware Synchronization
RWS
0x5B04
N/A
SWMBWR
Software Mailbox Write
RW
0x5B08
N/A
SWMB0
Software Mailbox Port 0
RO
0x5B0C
N/A
SWMB1
Software Mailbox Port 1
RO
0x5B18
N/A
SWMB2
Software Mailbox Port 2
RO
0x5B1C
N/A
SWMB3
Software Mailbox Port 3
RO
0x0E14
N/A
PHPM
PHY Power Management
RW
0x0010
N/A
EEC
EEPROM/Flash Control Register
RW
0x0014
N/A
EERD
EEPROM Read Register
RW
0x001C
N/A
FLA
Flash Access Register
RW
0x1010
N/A
EEMNGCTL
MNG EEPROM Control Register
RO
0x1014
N/A
EEMNGDATA
MNG EEPROM Read/Write data
RO
0x1024
N/A
EEARBC
EEPROM Auto Read Bus Control
RW
0x103C
N/A
FLASHOP
Flash Opcode Register
RW
0x1060
N/A
VPDDIAG
VPD Diagnostic
RO
Flash/EEPROM registers
Interrupts
0x1500
0x00C0
ICR
Interrupt Cause Read
RC/W1C
0x1504
0x00C8
ICS
Interrupt Cause Set
WO
0x1508
0x00D0
IMS
Interrupt Mask Set/Read
RW
0x150C
0x00D8
IMC
Interrupt Mask Clear
WO
0x1510
0x00E0
IAM
Interrupt Acknowledge Auto Mask
RW
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Table 7-6.
Register Summary (Continued)
Offset
Alias Offset
Abbreviation
Name
RW
0x1520
N/A
EICS
Extended Interrupt Cause Set
WO
0x1524
N/A
EIMS
Extended Interrupt Mask Set/Read
RWS
0x1528
N/A
EIMC
Extended Interrupt Mask Clear
WO
0x152C
N/A
EIAC
Extended Interrupt Auto Clear
RW
0x1530
N/A
EIAM
Extended Interrupt Auto Mask
RW
0x1580
N/A
EICR
Extended Interrupt Cause Read
RC/W1C
0x1700 0x170C
N/A
IVAR
Interrupt Vector Allocation Registers
RW
0x1740
N/A
IVAR_MISC
Interrupt Vector Allocation Registers - MISC
RW
0x1680 0x16A0
N/A
EITR
Extended Interrupt Throttling Rate 0 - 9
RW
0x1514
N/A
GPIE
General Purpose Interrupt Enable
RW
0x5B68
N/A
PBACL
MSI-X PBA Clear
R/W1C
0x0100
N/A
RCTL
RX Control
RW
0x01A0
N/A
LTRC
Latency Tolerance Reporting (LTR) Control
RW
0x2160
0x0168
FCRTL0
Flow Control Receive Threshold Low
RW
0x2168
0x0160
FCRTH0
Flow Control Receive Threshold High
RW
0x2170
N/A
FCRTC
Flow Control Receive Threshold Coalescing
RW
0x2404
N/A
IRPBS
Internal Receive Packet Buffer Size
RO
0x2460
N/A
FCRTV
Flow control Refresh timer value
RW
0xC000
0x0110,
0x2800
RDBAL[0]
RX Descriptor Base Low queue 0
RW
0xC004
0x0114,
0x2804
RDBAH[0]
RX Descriptor Base High queue 0
RW
0xC008
0x0118,
0x2808
RDLEN[0]
RX Descriptor Ring Length queue 0
RW
0xC00C
0x280C
SRRCTL[0]
Split and Replication Receive Control Register queue 0
RW
0xC010
0x0120,
0x2810
RDH[0]
RX Descriptor Head queue 0
RO
0xC018
0x0128,
0x2818
RDT[0]
RX Descriptor Tail queue 0
RW
0xC028
0x02828
RXDCTL[0]
Receive Descriptor Control queue 0
RW
0xC014
0x2814
RXCTL[0]
Receive Queue 0 DCA CTRL Register
RW
0xC040 + 0x40
* (n-1)
0x2900+
0x100 * (n1)
RDBAL[1 - 3]
RX Descriptor Base Low queue 1 - 3
RW
0xC044 + 0x40
* (n-1)
0x2904 +
0x100 * (n1)
RDBAH[1 - 3]
RX Descriptor Base High queue 1 - 3
RW
0xC048 + 0x40
* (n-1)
0x2908 +
0x100 * (n1)
RDLEN[1 - 3]
RX Descriptor Ring Length queue 1 - 3
RW
0xC04C + 0x40
* (n-1)
0x290C +
0x100 * (n1)
SRRCTL[1 - 3]
Split and Replication Receive Control Register queue 1 - 3
RW
0xC050 + 0x40
* (n-1)
0x2910 +
0x100 * (n1)
RDH[1 - 3]
RX Descriptor Head queue 1 - 3
RO
Receive
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Table 7-6.
Register Summary (Continued)
Offset
Alias Offset
Abbreviation
Name
RW
0xC058 + 0x40
* (n-1)
0x2918 +
0x100 * (n1)
RDT[1 - 3]
RX Descriptor Tail queue 1 - 3
RW
0xC068 + 0x40
* (n-1)
0x2928 +
0x100 * (n1)
RXDCTL[1 - 3]
Receive Descriptor Control queue 1 - 3
RW
0xC054 + 0x40
* (n-1)
0x2914 +
0x100 * (n1)
RXCTL[1 - 3]
Receive Queue 1 - 3 DCA CTRL Register
RW
0xC100 + 0x40
* (n- 4)
N/A
RDBAL[4-7]
RX Descriptor Base Low queue 4 - 7
RW
0xC104 + 0x40
* (n- 4)
N/A
RDBAH[4-7]
RX Descriptor Base High queue 4 - 7
RW
0xC108 + 0x40
* (n- 4)
N/A
RDLEN[4-7]
RX Descriptor Ring Length queue 4 - 7
RW
0xC10C + 0x40
* (n- 4)
N/A
SRRCTL[4 -7]
Split and Replication Receive Control Register queue 4 - 7
RW
0xC110 + 0x40
* (n- 4)
N/A
RDH[4 - 7]
RX Descriptor Head queue 4 - 7
RO
0xC118 + 0x40
* (n- 4)
N/A
RDT[4 - 7]
RX Descriptor Tail queue 4 - 7
RW
0xC128 + 0x40
* (n- 4)
N/A
RXDCTL[4 - 7]
Receive Descriptor Control queue 4 - 7
RW
0xC114 + 0x40
* (n- 4)
N/A
RXCTL[4 - 7]
Receive Queue 4 - 7 DCA CTRL Register
RW
0x5000
N/A
RXCSUM
Receive Checksum Control
RW
0x5004
N/A
RLPML
Receive Long packet maximal length
RW
0x5008
N/A
RFCTL
Receive Filter Control Register
RW
0x5200- 0x53FC 0x02000x03FC
MTA[127:0]
Multicast Table Array (n)
RW
0x5400 + 8*n
0x0040 +
8*n
RAL[0-15]
Receive Address Low (15:0)
RW
0x5404 + 8 *n
0x0044 + 8
*n
RAH[0-15]
Receive Address High (15:0)
RW
0x54E0 + 8*n
N/A
RAL[16-23]
Receive Address Low (23:16)
RW
0x54E4 + 8 *n
N/A
RAH[16-23]
Receive Address High (23:16)
RW
0x5480 –
0x549C
N/A
PSRTYPE[7:0]
Packet Split Receive type (n)
RW
0x54C0
N/A
RPLPSRTYPE
Replicated Packet Split Receive type
RW
0x581C
N/A
VT_CTL
VMDq Control register
RW
0x5600-0x57FC
0x06000x07FC
VFTA[127:0]
VLAN Filter Table Array (n)
RW
0x5818
N/A
MRQC
Multiple Receive Queues Command
RW
0x5C00-0x5C7C
N/A
RETA
Redirection Table
RW
0x5C80-0x5CA4
N/A
RSSRK
RSS Random Key Register
RW
0x5DD0
N/A
DMCRTRH
DMA Coalescing Receive Packet Rate Threshold
RW
0x5DD4
N/A
DMCCNT
DMA Coalescing Current RX Count
RO
Transmit
0x0400
N/A
TCTL
TX Control
0x0404
N/A
TCTL_EXT
TX Control extended
RW
0x0410
N/A
TIPG
TX IPG
RW
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Table 7-6.
Register Summary (Continued)
Offset
Alias Offset
Abbreviation
Name
RW
0x041C
N/A
RETX_CTL
Retry Buffer Control
RW
0x3404
N/A
ITPBS
Internal Transmit Packet Buffer Size
RO
0x359C
N/A
DTXTCPFLGL
DMA TX TCP Flags Control Low
RW
0x35A0
N/A
DTXTCPFLGH
DMA TX TCP Flags Control High
RW
0x3540
N/A
DTXMXSZRQ
DMA TX Max Total Allow Size Requests
RW
0x355C
N/A
DTXMXPKTSZ
DMA TX Max Allowable packet size
RW
0x3590
N/A
DTXCTL
DMA TX Control
RW
0xE000
0x0420,
0x3800
TDBAL[0]
TX Descriptor Base Low 0
RW
0xE004
0x0424,
0x3804
TDBAH[0]
TX Descriptor Base High 0
RW
0xE008
0x0428,
0x3808
TDLEN[0]
TX Descriptor Ring Length 0
RW
0xE010
0x0430,
0x3810
TDH[0]
TX Descriptor Head 0
RO
0xE018
0x0438,
0x3818
TDT[0]
TX Descriptor Tail 0
RW
0xE028
0x3828
TXDCTL[0]
Transmit Descriptor Control queue 0
RW
0xE014
0x3814
TXCTL[0]
TX DCA CTRL Register Queue 0
RW
0xE038
0x3838
TDWBAL[0]
Transmit Descriptor WB Address Low queue 0
RW
0xE03C
0x383C
TDWBAH[0]
Transmit Descriptor WB Address High queue 0
RW
0xE040 + 0x40
* (n-1)
0x3900 +
0x100 * (n1)
TDBAL[1-3]
TX Descriptor Base Low queue 1 - 3
RW
0xE044 + 0x40
* (n-1)
0x3904 +
0x100 * (n1)
TDBAH[1-3]
TX Descriptor Base High queue 1 - 3
RW
0xE048 + 0x40
* (n-1)
0x3908 +
0x100 * (n1)
TDLEN[1-3]
TX Descriptor Ring Length queue 1 - 3
RW
0xE050 + 0x40
* (n-1)
0x3910 +
0x100 * (n1)
TDH[1-3]
TX Descriptor Head queue 1 - 3
RO
0xE058 + 0x40
* (n-1)
0x3918 +
0x100 * (n1)
TDT[1-3]
TX Descriptor Tail queue 1 - 3
RW
0xE068 + 0x40
* (n-1)
0x3928 +
0x100 * (n1)
TXDCTL[1-3]
Transmit Descriptor Control 1 - 3
RW
0xE054 + 0x40
* (n-1)
0x3914 +
0x100 * (n1)
TXCTL[1-3]
TX DCA CTRL Register Queue 1 - 3
RW
0xE078 + 0x40
* (n-1)
0x3938 +
0x100 * (n1)
TDWBAL[1-3]
Transmit Descriptor WB Address Low queue 1 - 3
RW
0xE07C + 0x40
* (n-1)
0x393C +
0x100 * (n1)
TDWBAH[1-3]
Transmit Descriptor WB Address High queue 1 - 3
RW
0xE180 + 0x40
* (n - 4)
N/A
TDBAL[4 - 7]
TX Descriptor Base Low queue 4 - 7
RW
0xE184 + 0x40
* (n - 4)
N/A
TDBAH[4 - 7]
TX Descriptor Base High queue 4 - 7
RW
0xE188 + 0x40
* (n - 4)
N/A
TDLEN[4 - 7]
TX Descriptor Ring Length queue 4 - 7
RW
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Table 7-6.
Register Summary (Continued)
Offset
Alias Offset
Abbreviation
Name
RW
0xE190 + 0x40
* (n - 4)
N/A
TDH[4 - 7]
TX Descriptor Head queue 4 - 7
RO
0xE198 + 0x40
* (n - 4)
N/A
TDT[4 - 7]
TX Descriptor Tail queue 4 - 7
RW
0xE1A8 + 0x40
* (n - 4)
N/A
TXDCTL[4 - 7]
Transmit Descriptor Control 4 - 7
RW
0xE194 + 0x40
* (n - 4)
N/A
TXCTL[4 - 7]
TX Queue 4 - 7DCA CTRL Register
RW
0xE1B8 + 0x40
* (n - 4)
N/A
TDWBAL[4 - 7]
Transmit Descriptor WB Address Low queue 4 - 7
RW
0xE1BC + 0x40
* (n - 4)
N/A
TDWBAH[4 - 7]
Transmit Descriptor WB Address High queue 4 - 7
RW
0x5CB0 + 4*n
N/A
ETQF[0 - 7]
EType Queue Filter 0 - 7
RW
0x5A80 + 4*n
N/A
IMIR[0 - 7]
Immediate Interrupt Rx 0 - 7
RW
RW
Filters
0x5AA0 + 4*n
N/A
IMIREXT[0 - 7]
Immediate Interrupt Rx Extended 0 - 7
0x5AC0
N/A
IMIRVP
Immediate Interrupt Rx VLAN Priority
RW
0x59E0 + 4*n
N/A
TTQF[0 - 7]
Two-Tuple Queue Filter 0 - 7
RW
0x55FC
N/A
SYNQF
SYN Packet Queue Filter
RW
Virtualization
0x3548
N/A
LVMMC
Last VM Misbehavior Cause
RC
0x3558
N/A
MDFB
Malicious Driver Free Block
RWS
0x5D00 0x5D7C
N/A
VLVF
VLAN VM Filter
RW
0x5AD0 0x5ADC
N/A
VMOLR[0 - 7]
VM Offload register[0-7]
RW
0x5AF0
N/A
RPLOLR
Replication Offload register
RW
0xA000 0xA1FC
N/A
UTA
Unicast Table Array
RW
0x5D80 0x5D8C
N/A
VMRCTL
Virtual Mirror rule control
RW
0x5D90 0x5D9C
N/A
VMRVLAN
Virtual Mirror rule VLAN
RW
0x5DA0 0x5DAC
N/A
VMRVM
Virtual Mirror rule VM
RW
0x5DB0
N/A
SCCRL
Storm Control control register
RW
0x5DB4
N/A
SCSTS
Storm Control status
RO
0x5DB8
N/A
BSCTRH
Broadcast Storm control Threshold
RW
0x5DBC
N/A
MSCTRH
Multicast Storm control Threshold
RW
0x5DC0
N/A
BSCCNT
Broadcast Storm Control Current Count
RO
0x5DC4
N/A
MSCCNT
Multicast Storm control Current Count
RO
0x5DC8
N/A
SCTC
Storm Control Time Counter
RO
0x5DCC
N/A
SCBI
Storm Control Basic interval
RW
0xC070 + 0x40
*n
0x2830 +
0x100 * n
RQDPC[0 - 3]
Receive Queue drop packet count Register 1 - 3
RC/W
0xC130 + 0x40
* (n- 4)
N/A
RQDPC[4 - 7]
Receive Queue drop packet count Register 4 - 7
RC/W
VMDq Statistics
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Register Summary — Intel® 82580EB/82580DB GbE Controller
Table 7-6.
Register Summary (Continued)
Offset
Alias Offset
Abbreviation
Name
RW
0x10010 +
0x100*n
N/A
VFGPRC[0 - 7]
Per queue Good Packets Received Count
RO
0x10014 +
0x100*n
N/A
VFGPTC[0 - 7]
Per queue Good Packets Transmitted Count
RO
0x10018 +
0x100*n
N/A
VFGORC[0 - 7]
Per queue Good Octets Received Count
RO
0x10034 +
0x100*n
N/A
VFGOTC[0 - 7]
Per queue Octets Transmitted Count
RO
0x1003C +
0x100*n
N/A
VFMPRC[0 - 7]
Per queue Multicast Packets Received Count
RO
0x4000
N/A
CRCERRS
CRC Error Count
RC
0x4004
N/A
ALGNERRC
Alignment Error Count
RC
0x4008
N/A
SYMERRS
Symbol Error Count
RC
0x400C
N/A
RXERRC
RX Error Count
RC
0x4010
N/A
MPC
Missed Packets Count
RC
0x4014
N/A
SCC
Single Collision Count
RC
0x4018
N/A
ECOL
Excessive Collisions Count
RC
0x401C
N/A
MCC
Multiple Collision Count
RC
0x4020
N/A
LATECOL
Late Collisions Count
RC
0x4028
N/A
COLC
Collision Count
RC
0x4030
N/A
DC
Defer Count
RC
RC
Statistics
0x4034
N/A
TNCRS
Transmit - No CRS
0x403C
N/A
HTDPMC
Host Transmit Discarded Packets by MAC Count
RC
0x4040
N/A
RLEC
Receive Length Error Count
RC
0x4048
N/A
XONRXC
XON Received Count
RC
0x404C
N/A
XONTXC
XON Transmitted Count
RC
0x4050
N/A
XOFFRXC
XOFF Received Count
RC
0x4054
N/A
XOFFTXC
XOFF Transmitted Count
RC
0x4058
N/A
FCRUC
FC Received Unsupported Count
RC
0x405C
N/A
PRC64
Packets Received (64 Bytes) Count
RC
0x4060
N/A
PRC127
Packets Received (65-127 Bytes) Count
RC
0x4064
N/A
PRC255
Packets Received (128-255 Bytes) Count
RC
0x4068
N/A
PRC511
Packets Received (256-511 Bytes) Count
RC
0x406C
N/A
PRC1023
Packets Received (512-1023 Bytes) Count
RC
0x4070
N/A
PRC1522
Packets Received (1024-1522 Bytes)
RC
0x4074
N/A
GPRC
Good Packets Received Count
RC
0x4078
N/A
BPRC
Broadcast Packets Received Count
RC
0x407C
N/A
MPRC
Multicast Packets Received Count
RC
0x4080
N/A
GPTC
Good Packets Transmitted Count
RC
0x4088
N/A
GORCL
Good Octets Received Count (Lo)
RC
0x408C
N/A
GORCH
Good Octets Received Count (Hi)
RC
0x4090
N/A
GOTCL
Good Octets Transmitted Count (Lo)
RC
0x4094
N/A
GOTCH
Good Octets Transmitted Count (Hi)
RC
0x40A0
N/A
RNBC
Receive No Buffers Count
RC
0x40A4
N/A
RUC
Receive Under size Count
RC
Revision: 2.50
October 2011
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Intel® 82580EB/82580DB GbE Controller — Register Summary
Table 7-6.
Register Summary (Continued)
Offset
Alias Offset
Abbreviation
Name
RW
0x40A8
N/A
RFC
Receive Fragment Count
RC
0x40AC
N/A
ROC
Receive Oversize Count
RC
0x40B0
N/A
RJC
Receive Jabber Count
RC
0x40B4
N/A
MNGPRC
Management Packets Receive Count
RC
0x40B8
N/A
MPDC
Management Packets Dropped Count
RC
0x40BC
N/A
MNGPTC
Management Packets Transmitted Count
RC
0x40C0
N/A
TORL
Total Octets Received (Lo)
RC
0x40C4
N/A
TORH
Total Octets Received (Hi)
RC
0x40C8
N/A
TOTL
Total Octets Transmitted (Lo)
RC
0x40CC
N/A
TOTH
Total Octets Transmitted (Hi)
RC
0x40D0
N/A
TPR
Total Packets Received
RC
0x40D4
N/A
TPT
Total Packets transmitted
RC
0x40D8
N/A
PTC64
Packets Transmitted (64 Bytes) Count
RC
0x40DC
N/A
PTC127
Packets Transmitted (65-127 Bytes) Count
RC
0x40E0
N/A
PTC255
Packets Transmitted (128-256 Bytes) Count
RC
0x40E4
N/A
PTC511
Packets Transmitted (256-511 Bytes) Count
RC
0x40E8
N/A
PTC1023
Packets Transmitted (512-1023 Bytes) Count
RC
0x40EC
N/A
PTC1522
Packets Transmitted (1024-1522 Bytes) Count
RC
0x40F0
N/A
MPTC
Multicast Packets Transmitted Count
RC
0x40F4
N/A
BPTC
Broadcast Packets Transmitted Count
RC
0x40F8
N/A
TSCTC
TCP Segmentation Context Transmitted Count
RC
0x4100
N/A
IAC
Interrupt Assertion Count
RC
0x4104
N/A
RPTHC
Rx Packets to host count
RC
0x4118
N/A
HGPTC
Host Good Packets Transmitted Count
RC
0x4120
N/A
RXDMTC
Rx Descriptor Minimum Threshold Count
RC
0x4128
N/A
HGORCL
Host Good Octets Received Count (Lo)
RC
0x412C
N/A
HGORCH
Host Good Octets Received Count (Hi)
RC
0x4130
N/A
HGOTCL
Host Good Octets Transmitted Count (Lo)
RC
0x4134
N/A
HGOTCH
Host Good Octets Transmitted Count (Hi)
RC
0x4138
N/A
LENERRS
Length Errors count register
RC
0x4228
N/A
SCVPC
SerDes/SGMII/1000BASE-KX Code Violation Packet Count
Register
RW
0x41A4
N/A
SDPC
Switch Drop Packet Count
RC
Manageability Statistics
0x413C
N/A
BMNGPRC
BMC Management Packets Receive Count
0x4140
N/A
BMPDC
BMC Management Packets Dropped Count
RC
0x4144
N/A
BMNGPTC
BMC Management Packets Transmitted Count
RC
0x4400
N/A
BUPRC
BMC Total Unicast Packets Received
RC
0x4404
N/A
BMPRC
BMC Total Multicast Packets Received
RC
0x4408
N/A
BBPRC
BMC Total Broadcast Packets Received
RC
0x440C
N/A
BUPTC
BMC Total Unicast Packets Transmitted
RC
0x4410
N/A
BMPTC
BMC Total Multicast Packets Transmitted
RC
0x4414
N/A
BBPTC
BMC Total Broadcast Packets Transmitted
RC
0x4418
N/A
BCRCERRS
BMC FCS Receive Errors
RC
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RC
Revision: 2.50
October 2011
Register Summary — Intel® 82580EB/82580DB GbE Controller
Table 7-6.
Register Summary (Continued)
Offset
Alias Offset
Abbreviation
Name
RW
0x441C
N/A
BALGNERRC
BMC Alignment Errors
RC
0x4420
N/A
BXONRXC
BMC Pause XON Frames Received
RC
0x4424
N/A
BXOFFRXC
BMC Pause XOFF Frames Received
RC
0x4428
N/A
BXONTXC
BMC Pause XON Frames Transmitted
RC
0x442C
N/A
BXOFFTXC
BMC Pause XOFF Frames Transmitted
RC
0x4430
N/A
BSCC
BMC Single Collision Transmit Frames
RC
0x4434
N/A
BMCC
BMC Multiple Collision Transmit Frames
RC
0x5800
N/A
WUC
Wake Up Control
RW
0x5808
N/A
WUFC
Wake Up Filter Control
RW
0x5810
N/A
WUS
Wake Up Status
R/W1C
0x5900
N/A
WUPL
Wake Up Packet Length
RO
0x5A000x5A7C
N/A
WUPM
Wake Up Packet Memory
RO
0x9000-0x93FC
N/A
FHFT
Flexible Host Filter Table registers
RW
0x9A00-0x9DFC
N/A
FHFT_EXT
Flexible Host Filter Table registers extended
RW
0x5010 0x502C
N/A
MAVTV[7:0]
VLAN TAG Value 7 - 0
RW
0x5030 0x504C
N/A
MFUTP[7:0]
Management Flex UDP/TCP Ports
RW
0x5060 0x506C
N/A
METF[3:0]
Management Ethernet Type Filters
RW
0x5820
N/A
MANC
Management Control
RW
0x5838
N/A
IPAV
IP Address Valid
RW
Wake up
Manageability
0x5840- 0x5858 N/A
IP4AT
IPv4 Address Table
RW
0x5864
MNGONLY
Management Only Traffic Register
RW
N/A
0x5880- 0x588F N/A
IP6AT
IPv6 Address Table
RW
0x5890 0x58AC
N/A
MDEF[7:0]
Manageability Decision Filters
RW
0x5930 –
0x594C
N/A
MDEF_EXT[7:0]
Manageability Decision Filters
RW
0x58B0 0x58EC
N/A
MIPAF[15:0]
Manageability IP Address Filter
RW
0x5910 + 8*n
N/A
MMAL[1:0]
Manageability MAC Address Low 1:0
RW
0x5914 + 8*n
N/A
MMAH[1:0]
Manageability MAC Address High 1:0
RW
0x9400-0x94FC
N/A
FTFT
Flexible TCO Filter Table
RW
0x8800-0x8EFC
N/A
Flex MNG
Flex manageability memory address space
RW
0x5BB0
N/A
LTRMINV
Latency Tolerance Reporting (LTR) Minimum Values
PCIe
RW
0x5BB4
N/A
LTRMAXV
Latency Tolerance Reporting (LTR) Maximum Values
RW
0x5B00
N/A
GCR
PCIe Control Register
RW
0x5B10
N/A
GSCL_1
PCIe statistics control #1
RW
0x5B14
N/A
GSCL_2
PCIe statistics control #2
RW
0x5B90 0x5B9C
N/A
GSCL_5_8
PCIe statistics control Leaky Bucket Timer
RW
Revision: 2.50
October 2011
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Intel® 82580EB/82580DB GbE Controller — Register Summary
Table 7-6.
Register Summary (Continued)
Offset
Alias Offset
Abbreviation
Name
RW
0x5B20
N/A
GSCN_0
PCIe counter register #0
RW
0x5B24
N/A
GSCN_1
PCIe counter register #1
RW
0x5B28
N/A
GSCN_2
PCIe counter register #2
RW
0x5B2C
N/A
GSCN_3
PCIe counter register #3
RW
0x5B30
N/A
FACTPS
Function Active and Power State
RW
0x5B64
N/A
MREVID
Mirrored Revision ID
RO
0x5B6C
N/A
GCR_EXT
PCIe Control Extended Register
RW
0x5B74
N/A
DCA_CTRL
DCA Control Register
RW
0x5B88
N/A
PICAUSE
PCIe Interrupt Cause
R/W1C
0x5B8C
N/A
PIENA
PCIe Interrupt Enable
RW
0x5BBC
N/A
BARCTRL
PCIe BAR Control
RW
0x1084
N/A
PEIND
Parity and ECC Indication
Memory Error Detection
RC
0x1088
N/A
PEINDM
Parity and ECC Indication Mask
RW
0x245C
N/A
RPBECCSTS
Receive Packet buffer ECC control
RW
0x345C
N/A
TPBECCSTS
Transmit Packet buffer ECC control
RW
0x5BA0
N/A
PCIEERRCTL
PCIe Parity Control Register
RW
0x5BA4
N/A
PCIEECCCTL
PCIe ECC Control Register
RW
0x5BA8
N/A
PCIEERRSTS
PCIe Parity status Register
R/W1C
0x5BAC
N/A
PCIEECCSTS
PCIe ECC Status Register
R/W1C
0x5F54
N/A
LANPERRCTL
LAN Port Parity Error Control register
RW
0x5F58
N/A
LANPERRSTS
LAN Port Parity Error Status register
RO
0x3500
N/A
DTPARC
DMA Transmit Descriptor Parity Control
RW
0x3510
N/A
DTPARS
DMA Transmit Descriptor Parity Status
RW
0x3504
N/A
DRPARC
DMA Receive Descriptor Parity Control
RW
0x3514
N/A
DRPARS
DMA Receive Descriptor Parity Status
R/W1C
0x3508
N/A
DDPARC
Dhost Parity Control
RW
0x3518
N/A
DDPARS
Dhost Parity Status
R/W1C
PCS
0x4200
N/A
PCS_CFG
PCS Configuration 0 Register
RW
0x4208
N/A
PCS_LCTL
PCS Link Control Register
RW
0x420C
N/A
PCS_LSTS
PCS Link Status Register
RO
0x4210
N/A
PCS_DBG0
PCS Debug 0 register
RO
0x4214
N/A
PCS_DBG1
PCS Debug 1 register
RO
0x4218
N/A
PCS_ANADV
AN advertisement Register
RW
0x421C
N/A
PCS_LPAB
Link Partner Ability Register
RO
0x4220
N/A
PCS_NPTX
AN Next Page Transmit Register
RW
0x4224
N/A
PCS_LPABNP
Link Partner Ability Next Page Register
RO
Time Sync
0xB620
N/A
TSYNCRXCTL
RX Time Sync Control register
RW
0xB624
N/A
RXSTMPL
RX timestamp Low
RO
0xB628
N/A
RXSTMPH
RX timestamp High
RO
0xB62C
N/A
RXSATRL
RX timestamp attributes low
RO
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Revision: 2.50
October 2011
Alias Addresses — Intel® 82580EB/82580DB GbE Controller
Table 7-6.
Register Summary (Continued)
Offset
Alias Offset
Abbreviation
Name
RW
0xB630
N/A
RXSATRH
RX timestamp attributes low
RO
0xB614
N/A
TSYNCTXCTL
TX Time Sync Control register
RW
0xB618
N/A
TXSTMPL
TX timestamp value Low
RO
0xB61C
N/A
TXSTMPH
TX timestamp value High
RO
0xB6F8
N/A
SYSTIMR
System time residue register
RW
0xB600
N/A
SYSTIML
System time register Low
RW
0xB604
N/A
SYSTIMH
System time register High
RW
0xB608
N/A
TIMINCA
Increment attributes register
RW
0xB60C
N/A
TIMADJL
Time adjustment offset register low
RW
0xB610
N/A
TIMADJH
Time adjustment offset register high
RW
0xB640
N/A
TSAUXC
Auxiliary Control Register
RW
0xB644
N/A
TRGTTIML0
Target Time register 0 Low
RW
0xB648
N/A
TRGTTIMH0
Target Time register 0 High
RW
0xB64C
N/A
TRGTTIML1
Target Time register 1 Low
RW
0xB650
N/A
TRGTTIMH1
Target Time register 1 High
RW
0xB654
N/A
FREQOUT0
Frequency out 0 Control register
RW
0xB658
N/A
FREQOUT1
Frequency out 1 Control register
RW
0xB65C
N/A
AUXSTMPL0
Auxiliary Time Stamp 0 register Low
RO
0xB660
N/A
AUXSTMPH0
Auxiliary Time Stamp 0 register High
RO
0xB664
N/A
AUXSTMPL1
Auxiliary Time Stamp 1 register Low
RO
0xB668
N/A
AUXSTMPH1
Auxiliary Time Stamp 1 register High
RO
0x5F50
N/A
TSYNCRXCFG
Time Sync RX Configuration
RW
0x003C
N/A
TSSDP
Time Sync SDP Configuration Reg
RW
0xB66C
N/A
TSICR
Time Sync Interrupt Cause Register
RC/W1C
0xB670
N/A
TSIS
Time Sync Interrupt Set Register
WO
0xB674
N/A
TSIM
Time Sync Interrupt Mask Register
RW
7.1.4
Alias Addresses
Certain registers maintain an alias address designed for backward compatibility with software written
for previous GbE controllers. For these registers, the alias address is shown in the table above. Those
registers can be accessed by software at either the new offset or the alias offset. It is recommended
that software that is written solely for the 82580EB/DB, use the new address offset.
Note:
7.1.5
Revision: 2.50
October 2011
MSI-X BAR Register Summary
Intel® 82580EB/82580DB Gigabit Ethernet Controller
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Intel® 82580EB/82580DB GbE Controller — General Register Descriptions
Table 7-7.
MSI-X Register Summary
Category
Offset
MSI-X Table
0x0000 + n*0x10
[n=0...9]
Abbreviation
MSIXTADD
Name
MSI–X Table Entry Lower
Address
RW
RW
page 325
MSI-X Table
0x0004 + n*0x10
[n=0...9]
MSIXTUADD
MSI–X Table Entry Upper
Address
RW
page 325
MSI-X Table
0x0008 + n*0x10
[n=0...9]
MSIXTMSG
MSI–X Table Entry Message
R/W
page 325
MSI-X Table
0x000C + n*0x10
[n=0...9]
MSIXTVCTRL
MSI–X Table Entry Vector
Control
R/W
page 326
MSI-X Table
0x02000
MSIXPBA
MSIXPBA Bit Description
RO
page 326
7.2
General Register Descriptions
7.2.1
Device Control Register - CTRL (0x00000; R/W)
Page
This register, as well as the Extended Device Control register (CTRL_EXT), controls the major
operational modes for the device. While software write to this register to control device settings,
several bits (such as FD and SPEED) can be overridden depending on other bit settings and the
resultant link configuration determined by the PHY's Auto- Negotiation resolution. See Section 4.6.7 for
details on the setup of these registers in the different link modes.
Note:
Field
FD
This register is also aliased at address 0x0004.
Bit(s)
0
Initial Value
1
1b
Description
Full-Duplex
Controls the MAC duplex setting when explicitly set by software.
0b = half duplex.
1b = full duplex.
Reserved
1
0b
This bit is reserved and should be set to 0b for future compatibility.
GIO Master
Disable
2
0b
When set to 1b, the function of this bit blocks new master requests including
manageability requests. If no master requests are pending by this function, the
STATUS.GIO Master Enable Status bit is set. See Section 5.2.3.3 for further
information.
Reserved
5:3
0x0
Reserved
Write 0 ignore on read.
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Datasheet
276
Revision: 2.50
October 2011
Device Control Register - CTRL (0x00000; R/W) — Intel® 82580EB/82580DB GbE Controller
Field
SLU
Bit(s)
6
Initial Value
1
0b
Description
Set Link Up.
When the MAC link mode is set for GMII/MII mode (internal PHY), Set Link Up must be
set to 1 to permit the MAC to recognize the LINK signal from the PHY, which indicates
the PHY has gotten the link up, and is ready to receive and transmit data.
See Section 3.5.4 for more information about Auto-Negotiation and link configuration
in the various modes.
Notes:
1.
The CTRL.SLU bit is normally initialized to 0. However, if the APM Enable bit is set
in the EEPROM then it is initialized to 1b.
2.
The CTRL.SLU bit will be set to 1b if the Enable All Phys in D3 EEPROM bit word is
set to 1.
3.
The CTRL.SLU bit is set in NCSI mode according to the “enable channel
command” to the port.
4.
In SerDes and 1000Base-KX modes Link up can be forced by setting this bit as
described in Section 3.5.4.1.4.
ILOS
7
0b1
Invert Loss-of-Signal (LOS/LINK) Signal
Bit controls the polarity of the SRDS_[n]_SIG_DET signal or internal Link up signal.
0b = Do not invert (active high input signal).
1b = Invert signal (active low input signal).
Notes:
1.
ILOS bit value is updated to Initial Value only after LAN_PWR_GOOD or PCIe
reset.
2.
Source of the link-up signal (SRDS_[n]_SIG_DET signal or internal Link up
signal) is set via the CONNSW.ENRGSRC bit. When using internal link-up signal
bit should be 0.
3.
Should be set to zero when using internal copper PHY or when working in SGMII,
1000BASE-BX or 1000BASE-KX modes.
SPEED
9:8
10b
Speed selection.
These bits determine the speed configuration and are written by software after reading
the PHY configuration through the MDIO interface.
These signals are ignored when Auto-Speed Detection is enabled.
00b = 10 Mb/s.
01b = 100 Mb/s.
10b = 1000 Mb/s.
11b = not used.
Reserved
10
0b
Reserved
Write as 0b to ensure future compatibility.
FRCSPD
11
0b1
Force Speed
This bit is set when software needs to manually configure the MAC speed settings
according to the SPEED bits.
Note that MAC and PHY must resolve to the same speed configuration or software
must manually set the PHY to the same speed as the MAC.
Software must clear this bit to enable the PHY or ASD function to control the MAC
speed setting. Note that this bit is superseded by the CTRL_EXT.SPD_BYPS bit which
has a similar function.
FRCDPLX
12
0b
Force Duplex
When set to 1b, software can override the duplex indication from the PHY that is
indicated in the FDX to the MAC. Otherwise, in 10/100/1000Base-T link mode, the
duplex setting is sampled from the PHY FDX indication into the MAC on the asserting
edge of the PHY LINK signal. When asserted, the CTRL.FD bit sets duplex.
Reserved
15:13
0x0
Reserved
Write 0, ignore on read.
SDP0_GPIEN
16
0b
General Purpose Interrupt Detection Enable for SDP0
If software-controlled IO pin SDP0 is configured as an input, this bit (when 1b) enables
the use for GPI interrupt detection.
Revision: 2.50
October 2011
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Intel® 82580EB/82580DB GbE Controller — Device Control Register - CTRL (0x00000; R/W)
Field
Bit(s)
Initial Value
SDP1_GPIEN
17
0b
Description
General Purpose Interrupt Detection Enable for SDP1
If software-controlled IO pin SDP1 is configured as an input, this bit (when 1b) enables
the use for GPI interrupt detection.
SDP0 DATA
(RWS)
18
0b1
SDP0 Data Value
Used to read or write the value of software-controlled IO pin SDP0. If SDP0 is
configured as an output (SDP0_IODIR = 1b), this bit controls the value driven on the
pin (initial value EEPROM-configurable). If SDP0 is configured as an input, reads return
the current value of the pin.
When the SDP0_WDE bit is set, this field indicates the polarity of the watchdog
indication.
SDP1 DATA
(RWS)
19
ADVD3WUC
20
0b1
SDP1 Data Value
Used to read or write the value of software-controlled IO pin SDP1. If SDP1 is
configured as an output (SDP1_IODIR = 1b), this bit controls the value driven on the
pin (initial value EEPROM-configurable). If SDP1 is configured as an input, reads return
the current value of the pin.
1b1
D3Cold Wake up Capability Enable
When bit is 0b PME (WAKE#) is not generated in D3Cold.
Bit loaded from EEPROM (see Section 6.2.21).
SDP0_WDE
21
0b1
SDP0 used for Watchdog indication
When set, SDP0 is used as a watchdog indication. When set, the SDP0_DATA bit
indicates the polarity of the watchdog indication. In this mode, SDP0_IODIR must be
set to an output.
SDP0_IODIR
22
0b1
SDP0 Pin Direction
Controls whether software-controllable pin SDP0 is configured as an input or output
(0b = input, 1b = output). Initial value is EEPROM-configurable. This bit is not affected
by software or system reset, only by initial power-on or direct software writes.
SDP1_IODIR
23
0b1
SDP1 Pin Direction
Controls whether software-controllable pin SDP1 is configured as an input or output
(0b = input, 1b = output). Initial value is EEPROM-configurable. This bit is not affected
by software or system reset, only by initial power-on or direct software writes.
Reserved
25:24
0b
Reserved.
RST (SC)
26
0b
Port Software Reset
This bit performs reset to the respective port, resulting in a state nearly approximating
the state following a power-up reset or internal PCIe reset, except for system PCI
configuration and logic used by all ports.
0b = Normal.
1b = Reset.
This bit is self clearing and is referred to as software reset or global reset.
RFCE
27
1b
Receive Flow Control Enable
When set, indicates that the 82580EB/DB responds to the reception of flow control
packets. If Auto-Negotiation is enabled, this bit is set to the negotiated flow control
value.
In SerDes mode the resolution is done by the hardware. In internal PHY, SGMII or
1000BASE-KX modes it should be done by the software.
TFCE
28
0b
Transmit Flow Control Enable
When set, indicates that the 82580EB/DB transmits flow control packets (XON and
XOFF frames) based on the receiver fullness. If Auto-Negotiation is enabled, this bit is
set to the negotiated duplex value.
In SerDes mode the resolution is done by the hardware. In internal PHY, SGMII or
1000BASE-KX modes it should be done by the software.
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Device Control Register - CTRL (0x00000; R/W) — Intel® 82580EB/82580DB GbE Controller
Field
Bit(s)
Initial Value
DEV_RST
(SC)
29
0b
Description
Device Reset
This bit performs a reset of the entire controller device, resulting in a state nearly
approximating the state following a power-up reset or internal PCIe reset, except for
system PCI configuration.
0b = Normal.
1b = Reset.
This bit is self clearing.
Notes:
1. Assertion of DEV_RST generates an interrupt on all ports via the ICR.DRSTA
interrupt bit.
2. Device Reset (CTRL.DEV_RST) can be used to globally reset the entire component if
the DEV_RST_EN bit in Initialization Control 4 EEPROM word is set.
3. Assertion of DEV_RST sets on all ports the STATUS.DEV_RST_SET bit.
For additional information see Section 4.3.2.
VME
30
0b
VLAN Mode Enable
When set to 1b, VLAN information is stripped from all received 802.1Q packets.
PHY_RST
31
0b
PHY Reset
Generates a hardware-level reset to the internal 1000BASE-T PHY.
0b = Normal operation.
1b = Internal PHY reset asserted.
1. These bits are loaded from EEPROM.
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Intel® 82580EB/82580DB GbE Controller — Device Status Register - STATUS (0x0008; R)
7.2.2
Device Status Register - STATUS (0x0008; R)
Field
Bit(s)
Initial Value
FD
0
X
Description
Full Duplex.
0 = Half duplex (HD).
1= Full duplex (FD).
Reflects duplex setting of the MAC and/or link.
FD reflects the actual MAC duplex configuration. This normally reflects the
duplex setting for the entire link, as it normally reflects the duplex
configuration negotiated between the PHY and link partner (copper link) or
MAC and link partner (fiber link).
LU
1
X
Link up. 0 = no link established; 1 = link established. For this to be valid,
the Set Link Up bit of the Device Control Register (CTRL.SLU) must be set.
Link up provides a useful indication of whether something is attached to the
port. Successful negotiation of features/link parameters results in link
activity. The link startup process (and consequently the duration for this
activity after reset) can be several 100's of ms. When the internal PHY is
used, this reflects whether the PHY's LINK indication is present. When the
SerDes, SGMII or 1000BASE-KX interface is used, this indicates loss-ofsignal; if Auto-Negotiation is also enabled, this can also indicate successful
Auto-Negotiation. Refer to Section 3.5.4 for more details.
Note: Bit is valid only when working in Internal PHY mode. In SerDes mode
bit is always 0.
LAN ID
3:2
Port 0 = 00b
LAN ID
Port 1 = 01b
Provides software a mechanism to determine the LAN identifier for the
MAC.
Port 2 = 10b
Port 3 = 11b
00b = LAN 0.
01b = LAN 1.
10b = LAN 2.
11b = LAN 3.
TXOFF
4
X
Transmission Paused
This bit indicates the state of the transmit function when symmetrical flow
control has been enabled and negotiated with the link partner. This bit is
set to 1b when transmission is paused due to the reception of an XOFF
frame. It is cleared (0b) upon expiration of the pause timer or the receipt of
an XON frame.
Reserved
5
X
SPEED
7:6
X
Reserved
Link Speed Setting
Reflects the speed setting of the MAC and/or link when it is operating in 10/
100/1000BASE-T mode (internal PHY).
When the MAC is operating in 10/100/1000BASE-T mode with the internal
PHY, these bits normally reflect the speed of the actual link, negotiated by
the PHY and link partner and reflected internally from the PHY to the MAC
(SPD_IND). These bits also might represent the speed configuration of the
MAC only, if the MAC speed setting has been forced via software
(CTRL.SPEED) or if MAC auto-speed detection is used.
If Auto-Speed Detection is enabled, the 82580EB/DB's speed is configured
only once after the LINK signal is asserted by the PHY.
00b = 10 Mb/s.
01b = 100 Mb/s.
10b = 1000 Mb/s.
11b = 1000 Mb/s.
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Extended Device Control Register - CTRL_EXT (0x0018; R/W) — Intel® 82580EB/82580DB GbE
Controller
Field
Bit(s)
Initial Value
ASDV
9:8
X
Description
Auto-Speed Detection Value
Speed result sensed by the 82580EB/DB’s MAC auto-detection function.
These bits are provided for diagnostics purposes only. The ASD calculation
can be initiated by software writing a logic 1b to the CTRL_EXT.ASDCHK
bit. The resultant speed detection is reflected in these bits.
See Section 7.2.3 for details.
PHYRA
10
1b
PHY Reset Asserted
This read/write bit is set by hardware following the assertion of an internal
PHY reset; it is cleared by writing a 0b to it. This bit is also used by
firmware indicating a required initialization of the 82580EB/DB’s PHY.
Reserved
18:11
0x0
Reserved
GIO Master Enable
Status
19
1b
Cleared by the 82580EB/DB when the CTRL.GIO Master Disable bit is set
and no master requests are pending by this function and is set otherwise.
Indicates that no master requests are issued by this function as long as the
CTRL.GIO Master Disable bit is set.
DEV_RST_SET (R/
W1C)
20
0b
Reserved
30:21
0x0
Reserved
MAC clock gating
Enable
31
1b1
MAC clock gating Enable bit loaded from the EEPROM- indicates the device
support gating of the MAC clock.
Device Reset Set
When set indicates that a device reset (CTRL.DEV_RST) was initiated by
one of the software drivers.
Note: Bit cleared by write 1.
1. If the signature bits of the EEPROM’s Initialization Control Word 1 match (01b), this bit is read from the
EEPROM.
7.2.3
Extended Device Control Register CTRL_EXT (0x0018; R/W)
This register provides extended control of the 82580EB/DB’s functionality beyond that provided by the
Device Control register (CTRL).
Field
Bit(s)
Initial Value
Description
Reserved
1:0
0b
Reserved. Should be written as 0b to ensure future compatibility.
SDP2_GPIEN
2
0b
General Purpose Interrupt Detection Enable for SDP2.
If software-controllable IO pin SDP2 is configured as an input, this bit
(when set to 1b) enables use for GPI interrupt detection.
SDP3_GPIEN
3
0b
General Purpose Interrupt Detection Enable for SDP3.
If software-controllable IO pin SDP3 is configured as an input, this bit
(when set to 1b) enables use for GPI interrupt detection.
Reserved
5:4
00b
Reserved.
Reads as 00b.
SDP2_DATA
6
0b1
SDP2 Data Value. Used to read (write) the value of software-controllable
IO pin SDP2. If SDP2 is configured as an output (SDP2_IODIR = 1b), this
bit controls the value driven on the pin (initial value EEPROM-configurable).
If SDP2 is configured as an input, reads return the current value of the pin.
SDP3_DATA
7
0b1
SDP3 Data Value. Used to read (write) the value of software-controllable
IO pin SDP3. If SDP3 is configured as an output (SDP3_IODIR = 1b), this
bit controls the value driven on the pin (initial value EEPROM-configurable).
If SDP3 is configured as an input, reads return the current value of the pin.
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Intel® 82580EB/82580DB GbE Controller — Extended Device Control Register - CTRL_EXT (0x0018; R/
W)
Field
Reserved
Bit(s)
9:8
Initial Value
1
0b
Description
Reserved
Formally used as SDP5 and SDP4 pin input/output direction control,
respectively.
SDP2_IODIR
10
0b1
SDP2 Pin Direction. Controls whether software-controllable pin SDP2 is
configured as an input or output (0b = input, 1b = output). Initial value is
EEPROM-configurable. This bit is not affected by software or system reset,
only by initial power-on or direct software writes.
SDP3_IODIR
11
0b1
SDP3 Pin Direction. Controls whether software-controllable pin SDP3 is
configured as an input or output (0b = input, 1b = output). Initial value is
EEPROM-configurable. This bit is not affected by software or system reset,
only by initial power-on or direct software writes.
ASDCHK
12
0b
ASD Check
Initiates an Auto-Speed-Detection (ASD) sequence to sense the frequency
of the PHY receive clock (RX_CLK). The results are reflected in
STATUS.ASDV. This bit is self-clearing.
EE_RST
13
0b
EEPROM Reset
When set, initiates a reset-like event to the EEPROM function. This causes
the EEPROM to be read as if a RST# assertion had occurred. All the
82580EB/DB functions should be disabled prior to setting this bit. This bit
is self-clearing.
Reserved
14
0b
Reserved
SPD_BYPS
15
0b
Speed Select Bypass
When set to 1b, all speed detection mechanisms are bypassed, and the
82580EB/DB is immediately set to the speed indicated by CTRL.SPEED.
This provides a method for software to have full control of the speed
settings of the 82580EB/DB and when the change takes place, by
overriding the hardware clock switching circuitry.
NS_DIS
16
0
No Snoop Disable
When set to 1b, the 82580EB/DB does not set the no snoop attribute in
any PCIe packet, independent of PCIe configuration and the setting of
individual no snoop enable bits. When set to 0b, behavior of no snoop is
determined by PCIe configuration and the setting of individual no snoop
enable bits.
RO_DIS
17
0b
Relaxed Ordering Disabled
When set to 1b, the 82580EB/DB does not request any relaxed ordering
transactions on the PCIe interface regardless of the state of bit 4 in the
PCIe Device Control register. When this bit is cleared and bit 4 of the PCIe
Device Control register is set, the 82580EB/DB requests relaxed ordering
transactions as specified by registers RXCTL and TXCTL (per queue and per
flow).
SerDes Low
18
Power Enable
0b1
When set, allows the SerDes to enter a low power state when the function
is in Dr state.
Dynamic
MAC Clock
Gating
19
0b1
When set, enables Dynamic MAC Clock Gating.
PHY Power
Down Enable
20
1b1
When set, enables the PHY to enter a low-power state as described in
Section 5.4.3.
Reserved
21
0b
Reserved.
Write 0, ignore on read.
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Extended Device Control Register - CTRL_EXT (0x0018; R/W) — Intel® 82580EB/82580DB GbE
Controller
Field
LINK_MODE
Bit(s)
Initial Value
Description
23:22
0x01
Link Mode
Controls interface on the link.
00b = Direct copper (1000Base-T) interface (10/100/1000 BASE-T internal
PHY mode).
01b = 1000BASE-KX.
10b = SGMII.
11b = SerDes interface.
Reserved
24
0b
Reserved.
Write 0, ignore on read.
I2C Enabled
0b1
25
Enable I2C
This bit enables the SFPx_I2C pins that can be used to access external SFP
modules or an external 1000BASE-T PHY via the MDIO interface. If cleared,
the SFPx_I2C pads are isolated and accesses to the SFPx_I2C pins through
the I2CCMD register or the MDIC register are ignored.
EXT_VLAN
0b1
26
External VLAN Enable
When set, all incoming Rx packets are expected to have at least one VLAN
with the Ether type as defined in VET.EXT_VET that should be ignored. The
packets can have a second VLAN that should be used for all filtering
purposes. All Tx packets are expected to have at least one VLAN added to
them by the host. In the case of an additional VLAN request (VLE - VLAN
Enable is set in transmit descriptor) the second VLAN is added after the
first external VLAN is added by the host. This bit is reset only by a power
up reset or by an EEPROM full auto load and should only be changed while
Tx and Rx processes are stopped.
Reserved
27
0b
DRV_LOAD
28
0b
Reserved
Driver Loaded
This bit should be set by the driver after it is loaded. This bit should be
cleared when the driver unloads or after a PCIe soft reset. The MNG
controller reads this bit to indicate to the manageability controller (BMC)
that the driver has loaded.
Reserved
31:29
0b
Reserved
Write 0, Ignore on read.
1. These bits are read from the EEPROM.
The 82580EB/DB allows up to four externally controlled interrupts. All software-definable pins, these
can be mapped for use as GPI interrupt bits. Mappings are enabled by the SDPx_GPIEN bits only when
these signals are also configured as inputs via SDPx_IODIR. When configured to function as external
interrupt pins, a GPI interrupt is generated when the corresponding pin is sampled in an active-high
state.
The bit mappings are shown in the table bellow for clarity.
Table 7-8.
Mappings for SDI Pins Used as GPI
SDP Pin Used as GPI
Resulting ICR Bit
(GPI)
CTRL_EXT Field Settings
Direction
Enable as GPI interrupt
3
SDP3_IODIR
SDP3_GPIEN
14
2
SDP2_IODIR
SDP2_GPIEN
13
1
SDP1_IODIR
SDP1_GPIEN
12
0
SDP0_IODIR
SDP0_GPIEN
11
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Intel® 82580EB/82580DB GbE Controller — MDI Control Register - MDIC (0x0020; R/W)
Note:
If software uses the EE_RST function and desires to retain current configuration
information, the contents of the control registers should be read and stored by software.
Control register values are changed by a read of the EEPROM which occurs upon assertion
of the EE_RST bit.
Note:
The EEPROM reset function can read configuration information out of the EEPROM which
affects the configuration of PCIe space BAR settings. The changes to the BARs are not
visible unless the system reboots and the BIOS is allowed to re-map them.
The SPD_BYPS bit performs a similar function to the CTRL.FRCSPD bit in that the 82580EB/
DB’s speed settings are determined by the value software writes to the CRTL.SPEED bits.
However, with the SPD_BYPS bit asserted, the settings in CTRL.SPEED take effect
immediately rather than waiting until after the 82580EB/DB’s clock switching circuitry
performs the change.
7.2.4
MDI Control Register - MDIC (0x0020; R/W)
Software uses this register to read or write Management Data Interface (MDI) registers in the internal
PHY or an external SGMII PHY.
See Section 3.5.2.2.2 for details on usage of this register. The PHY registers described in Section 7.24
are accessible using the MDIC register.
Field
Bit(s)
Initial Value
Description
DATA
15:0
X
Data
In a Write command, software places the data bits and the MAC shifts them
out to the PHY. In a Read command, the MAC reads these bits serially from
the PHY and software can read them from this location.
REGADD
20:16
0x0
PHY Register Address: Reg. 0, 1, 2,...31
Reserved
25:21
0x0
Reserved.
OP
27:26
0x0
Opcode
01b = MDI Write
10b = MDI Read
All other values are reserved.
R (RWS)
28
1b
Ready Bit
Set to 1b by the 82580EB/DB at the end of the MDI transaction (for
example, indication of a Read or Write completion). It should be reset to 0b
by software at the same time the command is written.
MDI_IE
29
0b
Interrupt Enable
When set to 1 an Interrupt is generated at the end of an MDI cycle to
indicate an end of a read or write operation to the PHY.
MDI_ERR (RWS)
30
0b
Error
This bit is set to 1b by hardware when it fails to complete an MDI read.
Software should make sure this bit is clear (0b) before issuing an MDI read
or write command.
Note: bit is valid only when the Ready bit is set.
Reserved
31
0b
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Reserved.
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MDC/MDIO Configuration Register – MDICNFG (0x0E04; R/W) — Intel® 82580EB/82580DB GbE
Controller
7.2.5
MDC/MDIO Configuration Register –
MDICNFG (0x0E04; R/W)
This register is used to configure the MDIO connection that is accessed via the MDIC register. See
Section 3.5.2.2.2 for details on usage of this register.
Field
Bit(s)
Initial Value
Reserved
20:0
0x0
Description
Reserved.
Write 0, ignore on read.
PHYADD1
25:21
0x00 - LAN 0
External PHY Address
0x01 - LAN 1
When MDICNFG.Destination bit is 0b, default PHYADD accesses internal
PHY.
0x02 - LAN 2
0x03 - LAN 3
Reserved
29:26
0x0
Reserved.
Write 0, ignore on read.
Com_MDIO2
30
0b
Common MDIO
When this bit is set, access to the MDIO interface on this port is routed to
the LAN 0 MDIO interface. In this case the LAN 0 MDIO interface is used as
a common interface for MDIO accesses to a Multi PHY device that has a
single MDIO interface for all PHYs.
0b - MDIO access routed to the dedicated LAN port MDIO interface.
1b - MDIO accesses on this LAN port are routed to the LAN 0 MDIO
interface
Destination3
31
0b
Destination
0b = The MDIO transaction is to the internal PHY.
1b = The MDIO transaction is directed to the external MDIO pins (I2C
Interface).
Note:
•
When PHY registers access is initiated via the I2CCMD interface, access
is always via the external I2C Interface. In this case the destination
field should always be 0.
1. PHYADD Loaded from Initialization Control 4 EEPROM word to allocate per port address when using external MDIO port.
2. Common MDIO usage configuration bit is loaded from Initialization Control 3 EEPROM word.
3. Destination Loaded from EEPROM Initialization Control 3 word. When external PHY supports a MDIO interface bit is 1, otherwise bit
is 0.
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Intel® 82580EB/82580DB GbE Controller — SERDES Control 0 - P1GCTRL0 (0x0E08; RW)
7.2.6
SERDES Control 0 - P1GCTRL0 (0x0E08; RW)
Field
Bit(s)
Initial Value
Description
Reserved
0
0b
Reserved.
LPBKBUF
1
0b
External SerDes LoopBack
0b - Normal operation.
1b - Enable External SerDes loopback (RX to TX).
Reserved
3:2
11b
Reserved.
Write 11b.
Reserved
31:4
0x0
Reserved.
Write 0, ignore on read.
7.2.7
Copper/Fiber Switch Control - CONNSW (0x0034; R/W)
Field
AUTOSENSE_EN
Bit(s)
0
Initial Value
0b
Description
Auto Sense Enable
When set, the auto sense mode is active. In this mode the non-active link is
sensed by hardware as follows
PHY Sensing: The electrical idle detector of the receiver of the PHY is
activated while in SerDes, SGMII or 1000BASE-KX mode.
SerDes sensing: The electrical idle detector of the receiver of the SerDes is
activated while in internal PHY mode, assuming the ENRGSRC bit is cleared
If energy is detected in the non active media, the OMED bit in the ICR
register is set and this bit is cleared. This includes the case where energy
was present at the non-active media when this bit is being set.
AUTOSENSE_CONF 1
0b
Auto Sense Configuration Mode
This bit should be set during the configuration of the PHY/SerDes towards
the activation of the auto-sense mode to avoid spurious interrupts. While
this bit is set, the PHY/SerDes is active even though the active link is set to
SerDes, 1000BASE-KX or SGMII/PHY. Energy detection while this bit is set
is not reflected to the ICR.OMED interrupt.
ENRGSRC
2
0b1
SerDes Energy Detect Source
If set, the OMED interrupt cause is set after asserting the external signal
detect pin. If cleared, the OMED interrupt cause is set after exiting from
electrical idle of the SerDes receiver.
This bit also defines the source of the signal detect indication used to set
link up while in SerDes mode.
ASCLR_DIS
3
0b
Reserved
Reserved
8:4
0x0
Reserved
SerDesD (RO)
9
X
SerDes Signal Detect Indication
Indicates the SerDes signal detect value according to the selected source
(either external or internal). Valid only if LINK_MODE is SerDes,
1000BASE-KX or SGMII.
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VLAN Ether Type - VET (0x0038; R/W) — Intel® 82580EB/82580DB GbE Controller
Field
Bit(s)
PHYSD (RO)
10
Initial Value
X
Description
PHY Signal Detect Indication
Valid only if LINK_MODE is the PHY and the receiver is not in electrical idle.
PHY_PDN (RO)
11
X
This bit indicates that the internal GbE PHY is in power down state.
0 = Internal GbE PHY not in power down.
1 = Internal GbE PHY in power down.
Reserved
31:12
0x0
Reserved
1. The default value of the ENRGSRC bit in this register is defined in the Initialization Control 3 (Offset 0x24) EEPROM word (bit 15).
7.2.8
VLAN Ether Type - VET (0x0038; R/W)
This register contains the type field hardware matches against to recognize an 802.1Q (VLAN) Ethernet
packet. To be compliant with the 802.3ac standard, this register should be programmed with the value
0x8100.
Field
Bit(s)
VET (RO)
Initial Value
15:0
0x8100
Description
VLAN EtherType
Should be programmed with 0x8100.
VET EXT
31:16
7.2.9
0x8100
External VLAN Ether Type.
LED Control - LEDCTL (0x0E00; RW)
This register controls the setup of the LEDs. See Section 8.5.1 for details of the MODE fields encoding.
Field
LED0_MODE
Bit(s)
3:0
Initial Value
0010b1
Description
LED0/LINK# Mode
This field specifies the control source for the LED0 output. An initial value of
0010b selects LINK_UP# indication.
LED_PCI_MODE
4
0b
0b = Use LEDs as defined in the other fields of this register.
1b = Use LEDs to indicate PCI-E Lanes Idle status in SDP mode (only when
the led_mode is set to 0x8 – SDP mode)
For Port 0 LED0 3-0 indicates RX lanes 3- 0 Electrical Idle status
For Port 1 LED1 3-0 indicates TX lanes 3- 0 Electrical Idle status
GLOBAL_BLINK_MODE
5
0b1
Global Blink Mode
This field specifies the blink mode of all the LEDs.
0b = Blink at 200 ms on and 200 ms off.
1b = Blink at 83 ms on and 83 ms off.
LED0_IVRT
6
0b1
LED0/LINK# Invert
This field specifies the polarity/ inversion of the LED source prior to output
or blink control.
0b = Do not invert LED source (LED active low).
1b = Invert LED source (LED active High).
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Intel® 82580EB/82580DB GbE Controller — LED Control - LEDCTL (0x0E00; RW)
Field
LED0_BLINK
Bit(s)
7
Initial Value
1
0b
Description
LED0/LINK# Blink
This field specifies whether to apply blink logic to the (possibly inverted)
LED control source prior to the LED output.
0b = Do not blink asserted LED output.
1b = Blink asserted LED output.
LED1_MODE
11:8
0011b1
LED1/ACTIVITY# Mode
This field specifies the control source for the LED1 output. An initial value of
0011b selects FILTER ACTIVITY# indication.
Reserved
12
0b
Reserved
Write as 0 ignore on read.
Reserved
13
0b
Reserved
Write 0 ignore on read.
LED1_IVRT
14
0b1
LED1/ACTIVITY# Invert
This field specifies the polarity/ inversion of the LED source prior to output
or blink control.
0b = Do not invert LED source (LED active low).
1b = Invert LED source (LED active High).
LED1_BLINK
15
1b1
LED2_MODE
19:16
0110b1
LED1/ACTIVITY# Blink
LED2/LINK100# Mode
This field specifies the control source for the LED2 output. An initial value of
0011b selects LINK100# indication.
Reserved
20
0b
Reserved
Reserved
21
0b
Reserved
LED2_IVRT
22
0b1
LED2/LINK100# Invert
Read-only as 0b. Write as 0b for future compatibility.
This field specifies the polarity/ inversion of the LED source prior to output
or blink control.
0b = Do not invert LED source (LED active low).
1b = Invert LED source (LED active High).
LED2_BLINK
23
0b1
LED2/LINK100# Blink
LED3_MODE
27:24
0111b1
LED3/LINK1000# Mode
This field specifies the control source for the LED3 output. An initial value of
0111b selects LINK1000# indication.
Reserved
28
0b
Reserved
Read-only as 0b. Write as 0b for future compatibility.
Reserved
LED3_IVRT
29
0b
Reserved
30
0b1
LED3/LINK1000# Invert
This field specifies the polarity/ inversion of the LED source prior to output
or blink control.
0b = Do not invert LED source (LED active low).
1b = Invert LED source (LED active High).
LED3_BLINK
31
0b1
LED3/LINK1000# Blink
1. These bits are read from the EEPROM.
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Internal Packet Buffer Size Registers — Intel® 82580EB/82580DB GbE Controller
7.3
Internal Packet Buffer Size Registers
The following registers define the size of the on-chip receive and transmit buffers used to receive and
transmit packets. The overall available internal buffer size in the 82580EB/DB for all ports is 144 KB for
receive buffers and 80 KB for transmit Buffers. Disabled ports memory can be shared between active
ports and sharing can be asymmetric. The default buffer size for each port is loaded from the EEPROM
on initialization.
7.3.1
Internal Receive Packet Buffer Size - IRPBS (0x2404; RO)
Field
RXPbsize1
Bit(s)
3:0
Initial Value
0x0
Description
Receive internal buffer size:
0x0 - 36 KB
0x1 - 72 KB
0x2 - 144 KB
0x3 - 1 KB
0x4 - 2 KB
0x5 - 4 KB
0x6 - 8 KB
0x7 - 16 KB
0x8 - 35 KB
0x9 - 70 KB
0xA - 140 KB
0xB:0xF - reserved
Notes:
1.
When 4 ports are active maximum buffer size can be 36 KB. When 2
ports are active maximum buffer size can be 72 KB. When only a
single port is active maximum buffer size can be 144 KB. For further
information see Section 8.1.3.2.
2.
Values bellow 35 KB should be used for diagnostic purposes only.
3.
When port is disabled for both PCIe and Management access, the
buffer size allocated to the port is 0 Bytes. Available internal memory
can be used by other ports.
4.
Field loaded from EEPROM following Power-up, PCIe reset and
software reset.
Reserved
31:4
0x0
Reserved
1. Value loaded from Initialization Control 4 EEPROM word.
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Intel® 82580EB/82580DB GbE Controller — Internal Transmit Packet Buffer Size - ITPBS (0x3404; RO)
7.3.2
Internal Transmit Packet Buffer Size - ITPBS (0x3404; RO)
Field
TXPbsize1
Bit(s)
3:0
Initial Value
0x0
Description
Transmit internal buffer size:
0x0 - 20 KB
0x1 - 40 KB
0x2 - 80 KB
0x3 - 1 KB
0x4 - 2 KB
0x5 - 4 KB
0x6 - 8 KB
0x7 - 16 KB
0x8 - 19 KB
0x9 - 38 KB
0xA - 76 KB
0xB:0xF - reserved
Notes:
1.
When 4 ports are active maximum buffer size can be 20KB. When only
2 ports are active maximum buffer size is 40KB. When only a single
port is active maximum buffer size is 80KB. For further information
see Section 8.2.1.2.
2.
Values bellow 20 KB should be used for diagnostic purposes only.
3.
When port is disabled for both PCIe and management access, the
buffer size allocated to the port is 0 Bytes. Available internal memory
can be used by other ports.
4.
Transmit Internal Buffer size should be greater than the maximum
transmit packet size defined in the DTXMXPKTSZ register.
5.
Field loaded from EEPROM following Power-up, PCIe reset and
software reset.
Reserved
31:4
0x0
Reserved
Write 0, ignore on read.
1. Value loaded from Initialization Control 4 EEPROM word.
7.4
EEPROM/Flash Register Descriptions
7.4.1
EEPROM/Flash Control Register - EEC (0x0010; R/W)
This register provides software direct access to the EEPROM. Software can control the EEPROM by
successive writes to this register. Data and address information is clocked into the EEPROM by software
toggling the EE_SK and EE_DI bits (0 and 2) of this register with EE_CS set to 0b. Data output from the
EEPROM is latched into the EE_DO bit (bit 3) via the internal 62.5 MHz clock and can be accessed by
software via reads of this register.
Note:
Attempts to write to the Flash device via PCIe BAR or via I/O access when writes are
disabled (FWE is not equal to 10b) should not be attempted. Behavior after such an
operation is undefined and can result in component and/or system hangs. Bit banging
access to the flash via FLA register is not protected by this field.
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EEPROM/Flash Control Register - EEC (0x0010; R/W) — Intel® 82580EB/82580DB GbE Controller
Field
EE_SK
Bit(s)
0
Initial Value
0b
Description
Clock input to the EEPROM
When EE_GNT = 1b, the EE_SK output signal is mapped to this bit and provides
the serial clock input to the EEPROM. Software clocks the EEPROM via toggling
this bit with successive writes.
EE_CS
1
0b
Chip select input to the EEPROM
When EE_GNT = 1b, the EE_CS output signal is mapped to the chip select of the
EEPROM device. Software enables the EEPROM by writing a 1b to this bit.
EE_DI
2
0b
Data input to the EEPROM
When EE_GNT = 1b, the EE_DI output signal is mapped directly to this bit.
Software provides data input to the EEPROM via writes to this bit.
EE_DO (RO)
3
X1
Data output bit from the EEPROM
The EE_DO input signal is mapped directly to this bit in the register and contains
the EEPROM data output. This bit is RO from a software perspective; writes to
this bit have no effect.
FWE
5:4
01b
Flash Write Enable Control
These two bits, control whether writes to Flash memory are allowed.
00b = Flash erase (along with bit 31 in the FLA register).
01b = Flash writes disabled.
10b = Flash writes enabled.
11b = Reserved.
EE_REQ
6
0b
Request EEPROM Access
The software must write a 1b to this bit to get direct EEPROM access. It has
access when EE_GNT is 1b. When the software completes the access it must
write a 0b.
EE_GNT
7
0b
Grant EEPROM Access
When this bit is 1b the software can access the EEPROM using the SK, CS, DI,
and DO bits.
EE_PRES (RO)
8
X
EEPROM Present
This bit indicates that an EEPROM is present by monitoring the EE_DO input for
an active-low acknowledge by the serial EEPROM during initial EEPROM scan. 1b
= EEPROM present.
Auto_RD (RO)
9
0b
EEPROM Auto Read Done
When set to 1b, this bit indicates that the auto read by hardware from the
EEPROM is done. This bit is also set when the EEPROM is not present or when its
signature is not valid.
EE_ADDR_SIZE
(RO)
10
0b
EEPROM Address Size
This field defines the address size of the EEPROM.
This bit is set by the EEPROM size auto-detect mechanism. If no EEPROM is
present or the signature is not valid, a 16-bit address is assumed.
0b = 8- and 9-bit.
1b = 16-bit.
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Intel® 82580EB/82580DB GbE Controller — EEPROM Read Register - EERD (0x0014; RW)
Field
Bit(s)
14:112
EE_SIZE (RO)
Initial Value
0010b
Description
EEPROM Size
This field defines the size of the EEPROM:
Field Value
EEPROM Size
0000b - 0110b
0111b
16 Kbytes
2 bytes
1000b
32 Kbytes
2 bytes
1001b - 1111b
EE_BLOCKED (R/
W1C)
15
Reserved
31:16
0b
EEPROM Address Size
Reserved
Reserved
EEPROM access blocked
EEPROM access blocked - Bit is set by HW when bit banging transactions are
blocked due to write to read-only sections or any access to hidden area.
Note: Bit is cleared by write one.
0x0
Reserved
Write 0 ignore on read.
1. Value depends on voltage level on EE_DO pin following initialization
2. These bits are read from the EEPROM.
7.4.2
EEPROM Read Register - EERD (0x0014; RW)
This register is used by software to cause the 82580EB/DB to read individual words in the EEPROM. To
read a word, software writes the address to the Read Address field and simultaneously writes a 1b to
the Start Read field. The 82580EB/DB reads the word from the EEPROM and places it in the Read Data
field, setting the Read Done field to 1b. Software can poll this register, looking for a 1b in the Read
Done field, and then using the value in the Read Data field.
When this register is used to read a word from the EEPROM, that word does not influence any of the
82580EB/DB's internal registers even if it is normally part of the auto-read sequence.
Field
START
Bit(s)
0
Initial Value
0b
Description
Start Read
Writing a 1b to this bit causes the EEPROM to read a (16-bit) word at the
address stored in the EE_ADDR field and then storing the result in the
EE_DATA field. This bit is self-clearing.
DONE (RO)
1
0b
Read Done
Set to 1b when the EEPROM read completes.
Set to 0b when the EEPROM read is not completed.
Writes by software are ignored. Reset by setting the START bit.
ADDR
15:2
0x0
Read Address
This field is written by software along with Start Read to indicate the word
to read.
DATA (RO)
31:16
X
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Read Data. Data returned from the EEPROM read.
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Flash Access - FLA (0x001C; R/W) — Intel® 82580EB/82580DB GbE Controller
7.4.3
Flash Access - FLA (0x001C; R/W)
This register provides software direct access to the Flash. Software can control the Flash by successive
writes to this register. Data and address information is clocked into the Flash by software toggling the
FL_SCK bit (bit 0) of this register with FL_CE set to 1b. Data output from the Flash is latched into the
FL_SO bit (bit 3) of this register via the internal 125 MHz clock and can be accessed by software via
reads of this register.
Field
FL_SCK
Bit(s)
0
Initial Value
0b
Description
Clock Input to the Flash
When FL_GNT is 1b, the FL_SCK out signal is mapped to this bit and provides the
serial clock input to the Flash device. Software clocks the Flash memory via toggling
this bit with successive writes.
FL_CE
1
0b
Chip Select Input to the Flash
When FL_GNT is 1b, the FL_CE output signal is mapped to the chip select of the Flash
device. Software enables the Flash by writing a 0b to this bit.
FL_SI
2
0b
Data Input to the Flash
When FL_GNT is 1b, the FL_SI output signal is mapped directly to this bit. Software
provides data input to the Flash via writes to this bit.
FL_SO
3
X
Data Output Bit from the Flash
The FL_SO input signal is mapped directly to this bit in the register and contains the
Flash memory serial data output. This bit is read only from the software perspective
— writes to this bit have no effect.
FL_REQ
4
0b
Request Flash Access
The software must write a 1b to this bit to get direct Flash memory access. It has
access when FL_GNT is 1b. When the software completes the access it must write a
0b.
FL_GNT
5
0b
Grant Flash Access
When this bit is 1b, the software can access the Flash memory using the FL_SCK,
FL_CE, FL_SI, and FL_SO bits.
FLA_add_size 6
0b
Flash Address Size
When Flash_add_size is set, all flashes (including 64 KB) are accessed using 3 bytes
of the address. If this bit is set by one of the functions, it is also reflected in the other
one.
Reserved
29:7
0b
Reserved
Reads as 0b.
FL_BUSY
30
0b
Flash Busy
This bit is set to 1b while a write or an erase to the Flash memory is in progress.
While this bit is clear (read as 0b) software can access to write a new byte to the
Flash device.
FL_ER (SC)
31
0b
Flash Erase Command
When bit is set to 1b an erase command is sent to the Flash component only if the
EEC.FWE field is 00b (Flash Erase). This bit is automatically cleared if set to 1b and
the value of the EEC.FWE field is 00b.
7.4.4
Flash Opcode - FLASHOP (0x103C; R/W)
This register enables the host or the firmware to define the op-code used in order to erase a sector of
the flash or the complete flash. This register is reset only at power on or assertion.
This register is common to all ports and manageability. Register should be programmed according to
the parameters of the flash used.
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Intel® 82580EB/82580DB GbE Controller — EEPROM Auto Read Bus Control - EEARBC (0x1024; R/W)
Note:
The default values fit to Atmel* Serial Flash Memory devices.
Field
DERASE
Bit(s)
Initial Value
7:0
0x0062
Description
Flash Device Erase Instruction
The op-code for the Flash erase instruction.
SERASE
15:8
0x0052
Flash Block Erase Instruction
The op-code for the Flash block erase instruction. Relevant only to Flash
access by manageability.
Reserved
31:16
7.4.5
0x0
Reserved
EEPROM Auto Read Bus Control - EEARBC (0x1024; R/W)
In EEPROM-less implementations, this register is used to program the 82580EB/DB the same way it
should be programmed if an EEPROM was present. See Section 3.3.1.7.1 for details of this register
usage.
This register is common to all functions and should be accessed only following access coordination with
the other ports.
Field
VALID_CORE0
Bit(s)
0
Initial Value
0b
Description
Valid Write Active to Core 0
Write strobe to Core 0. Firmware/software sets this bit for write access to registers
loaded from EEPROM words in LAN0 section. Software should clear this bit to
terminate the write transaction.
VALID_CORE1
1
0b
Valid Write Active to Core 1
Write strobe to Core 1. Firmware/software sets this bit for write access to registers
loaded from EEPROM words in LAN1 section. Software should clear this bit to
terminate the write transaction.
VALID_COMMON
2
0b
Valid Write Active to Common
Write strobe to Common. Firmware/software sets this bit for write access to
registers loaded from EEPROM words that are common to all sections. Software
should clear this bit to terminate the write transaction.
Reserved
3
0b
Reserved
Write 0, ignore on read.
ADDR
12:4
0x0
Write Address
This field specifies the address offset of the EEPROM word from the start of the
EEPROM Section. Sections supported are:
VALID_CORE2
13
0b
•
Common and LAN0
•
LAN1
•
LAN2
•
LAN3
Valid Write Active to Core 2
Write strobe to Core 2. Firmware/software sets this bit for write access to registers
loaded from EEPROM words in LAN2 section. Software should clear this bit to
terminate the write transaction.
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VPD Diagnostic Register -VPDDIAG (0x1060; RO) — Intel® 82580EB/82580DB GbE Controller
Field
Bit(s)
VALID_CORE3
14
Initial Value
0b
Description
Valid Write Active to Core 3
Write strobe to Core 3. Firmware/software sets this bit for write access to registers
loaded from EEPROM words in LAN3 section. Software should clear this bit to
terminate the write transaction.
Reserved
15
0b
Reserved
Write 0, ignore on read.
DATA
6.
7.
31:16
0x0
Data written into the EEPROM auto read bus.
Not all EEPROM addresses are part of the auto read. By using this register software can write to the hardware registers that are
configured during auto read only.
Write access to this register is enabled only if EEPROM presence is not detected.
7.4.6
VPD Diagnostic Register -VPDDIAG (0x1060; RO)
This register stores the VPD parameters as parsed by the auto-load process. This register is used for
debug only.
Field
Bit(s)
Initial Value
Description
Valid
0
X
VPD structure valid
Reserved
4:1
X
Reserved
RD Tag
13:5
X
Offset of the Read tag in VPD relative to the start of VPD (in bytes).
WR Tag
22:14
X
Offset of the Write tag in VPD relative to the start of VPD (in bytes).
End Tag
31:23
X
Offset of the End tag in VPD relative to the start of VPD (in bytes).
7.4.7
Management-EEPROM CSR I/F
The following registers are reserved for Firmware access to the EEPROM and are not writable by the
host.
7.4.7.1
Field
Management EEPROM Control Register - EEMNGCTL (0x1010;
RO)
Bit(s)
Initial Value
Description
ADDR
14:0
0x0
Address - This field is written by MNG along with Start Read or Start write to indicate
the EEPROM address to read or write.
START
15
0b
Start - Writing a 1b to this bit causes the EEPROM to start the read or write operation
according to the write bit.
WRITE
16
0b
Write - This bit tells the EEPROM if the current operation is read or write:
0b = read
1b = write
EEBUSY
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17
0b
EEPROM Busy - This bit indicates that the EEPROM is busy processing an EEPROM
transaction and shouldn’t be accessed.
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Intel® 82580EB/82580DB GbE Controller — Flow Control Register Descriptions
CFG_DONE 01
18
0b
Configuration cycle is done for port 0 – This bit indicates that configuration cycle
(configuration of SerDes, PHY, PCIe and PLLs) is done for port 0. This bit is set to 1b to
indicate configuration done, and cleared by hardware on any of the reset sources that
causes initialization of the PHY.
Note: Port 0 driver should not try to access the PHY for configuration before this bit is
set.
CFG_DONE 11
19
0b
Configuration cycle is done for port 1 – This bit indicates that configuration cycle
(configuration of SerDes, PHY, PCIe and PLLs) is done for port 1. This bit is set to 1b to
indicate configuration done, and cleared by hardware on any of the reset sources that
cause initialization of the PHY.
Note: Port 1 driver should not try to access the PHY for configuration before this bit is
set. .
CFG_DONE 21
20
0b
Configuration cycle is done for port 2 – This bit indicates that the configuration cycle
(configuration of SerDes, PCIe and PLLs) is done for port 2. This bit is set to 1b to
indicate configuration done, and cleared by hardware on any of the reset sources that
cause initialization of the PHY.
Note: Port 2 driver should not try to access the PHY for configuration before this bit is
set.
CFG_DONE 31
21
0b
Configuration cycle is done for port 3 – This bit indicates that the configuration cycle
(configuration of SerDesPHY, PCIe and PLLs) is done for port 3. This bit is set to 1b to
indicate configuration done, and cleared by hardware on any of the reset sources that
cause initialization of the PHY.
Note: Port 3 driver should not try to access the PHY for configuration before this bit is
set.
Reserved
30:22
0x0
Reserved
DONE
31
1b
Transaction Done - This bit is cleared after Start Write or Start Read bit is set by the
MNG and is set back again when the EEPROM write or read transaction is done.
1. Bit relates to physical port. If LAN Function Swap (FACTPS.LAN Function Sel = 1) is done, Software should poll CFG_DONE bit of
original port to detect end of PHY configuration operation.
7.4.7.2
Management EEPROM Read/Write data - EEMNGDATA
(0x1014; RO)
Field
WRDATA
Bit(s)
15:0
Initial Value
0x0
Description
Write Data
Data to be written to the EEPROM.
RDDATA
31:16
–
Read Data
Data returned from the EEPROM read.
7.5
Flow Control Register Descriptions
7.5.1
Flow Control Address Low - FCAL (0x0028; RO)
Flow control packets are defined by 802.3X to be either a unique multicast address or the station
address with the Ether Type field indicating PAUSE. The FCA registers provide the value hardware uses
to compare incoming packets against, to determine that it should PAUSE its output.
The FCAL register contains the lower bits of the internal 48-bit Flow Control Ethernet address. All 32
bits are valid. Software can access the High and Low registers as a register pair if it can perform a 64bit access to the PCIe bus. The complete flow control multicast address is: 0x01_80_C2_00_00_01;
where 0x01 is the first byte on the wire, 0x80 is the second, etc.
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Flow Control Address High - FCAH (0x002C; RO) — Intel® 82580EB/82580DB GbE Controller
Note:
Any packet matching the contents of {FCAH, FCAL, FCT} when CTRL.RFCE is set is acted on
by the 82580EB/DB. Whether flow control packets are passed to the host (software)
depends on the state of the RCTL.DPF bit and whether the packet matches any of the
normal filters.
Field
FCAL
7.5.2
Bit(s)
31:0
Initial Value
0x00C28001
Description
Flow Control Address Low
Flow Control Address High - FCAH (0x002C; RO)
This register contains the upper bits of the 48-bit Flow Control Ethernet address. Only the lower 16 bits
of this register have meaning. The complete Flow Control address is {FCAH, FCAL}.
The complete flow control multicast address is: 0x01_80_C2_00_00_01; where 0x01 is the first byte
on the wire, 0x80 is the second, etc.
Field
Bit(s)
Initial Value
FCAH
15:0
0x0100
Reserved
31:16
0x0
Description
Flow Control Address High
Should be programmed with 0x01_00.
Reserved
Write 0 ignore on read.
7.5.3
Flow Control Type - FCT (0x0030; R/W)
This register contains the type field that hardware matches to recognize a flow control packet. Only the
lower 16 bits of this register have meaning. This register should be programmed with 0x88_08. The
upper byte is first on the wire FCT[15:8].
Field
Bit(s)
Initial Value
FCT
15:0
0x8808
Reserved
31:16
0x0
Description
Flow Control Type
Reserved
Write 0 ignore on read.
7.5.4
Flow Control Transmit Timer Value - FCTTV (0x0170; R/W)
The 16-bit value in the TTV field is inserted into a transmitted frame (either XOFF frames or any PAUSE
frame value in any software transmitted packets). It counts in units of slot time of 64 bytes. If software
needs to send an XON frame, it must set TTV to 0 prior to initiating the PAUSE frame.
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Intel® 82580EB/82580DB GbE Controller — Flow Control Receive Threshold Low - FCRTL0 (0x2160; R/
W)
Field
Bit(s)
Initial Value
Description
TTV
15:0
X
Transmit Timer Value
Reserved
31:16
0b
Reserved
Write 0 ignore on read.
7.5.5
Flow Control Receive Threshold Low - FCRTL0 (0x2160; R/
W)
This register contains the receive threshold used to determine when to send an XON packet The
complete register reflects the threshold in units of bytes. The lower 4 bits must be programmed to 0b
(16 byte granularity). Software must set XONE to enable the transmission of XON frames. Each time
hardware crosses the receive-high threshold (becoming more full), and then crosses the receive-low
threshold and XONE is enabled (1b), hardware transmits an XON frame. When XONE is set, the RTL
field should be programmed to at least 3b (at least 48 bytes).
Flow control reception/transmission are negotiated capabilities by the Auto-Negotiation process. When
the 82580EB/DB is manually configured, flow control operation is determined by the CTRL.RFCE and
CTRL.TFCE bits.
Field
Reserved
Bit(s)
3:0
Initial Value
0000b
Description
Reserved
Write 0 ignore on read.
RTL
16:4
0x0
Receive Threshold Low.
FIFO low water mark for flow control transmission.
An XON packet is sent if the occupied space in the packet buffer is smaller or equal
than this watermark.
This field is in 16 bytes granularity.
Reserved
30:17
0x0
Reserved
Write 0 ignore on read.
XONE
31
0b
XON Enable
0b = Disabled.
1b = Enabled.
NOTE: If FCRTL0.XONE is 1, the minimum value allowed in FCRTL0.RTL is 3
(48 bytes).
7.5.6
Flow Control Receive Threshold High - FCRTH0 (0x2168;
R/W)
This register contains the receive threshold used to determine when to send an XOFF packet. The
complete register reflects the threshold in units of bytes. This value must be at maximum 48 bytes less
than the maximum number of bytes allocated to the Receive Packet Buffer (IRPBS.RXPbsize), and the
lower 4 bits must be programmed to 0b (16 byte granularity). The value of RTH should also be bigger
than FCRTL.RTL. Each time the receive FIFO reaches the fullness indicated by RTH, hardware transmits
a PAUSE frame if the transmission of flow control frames is enabled.
Flow control reception/transmission are negotiated capabilities by the Auto-Negotiation process. When
the 82580EB/DB is manually configured, flow control operation is determined by the CTRL.RFCE and
CTRL.TFCE bits.
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Flow Control Refresh Threshold Value - FCRTV (0x2460; R/W) — Intel® 82580EB/82580DB GbE
Controller
Field
Reserved
Bit(s)
3:0
Initial Value
Description
000b
Reserved
Write 0 ignore on read.
RTH
17:4
0x0
Receive Threshold High
FIFO high water mark for flow control transmission. An XOFF packet is sent if the
occupied space in the packet buffer is bigger or equal than this watermark.
This field is in 16 bytes granularity.
See Section 3.5.5.3.1 for calculation of FCRTH0.RTH value.
Notes:
1.
When in DMA coalescing operation and internal Transmit buffer is empty
threshold high value defined in FCRTC.RTH_Coal is used instead of the
FCRTH0.RTH value to allow increase of Receive Threshold High value by
maximum supported Jumbo frame size.
2.
Value programmed should be greater than Maximum packet size.
Reserved
31:18
0x0
Reserved
Write 0 ignore on read.
7.5.7
Flow Control Refresh Threshold Value FCRTV (0x2460; R/W)
Field
Bit(s)
FC_refresh_th
15:0
Initial Value
0x0
Description
Flow Control Refresh Threshold
This value indicates the threshold value of the flow control shadow counter; when
the counter reaches this value, and the conditions for PAUSE state are still valid
(buffer fullness above low threshold value), a PAUSE (XOFF) frame is sent to link
partner.
If this field contains zero value, the Flow Control Refresh is disabled.
Reserved
31:16
7.5.8
-
Reserved
Flow Control Status - FCSTS0 (0x2464; RO)
This register describes the status of the flow control machine.
Field
Bit(s)
Initial Value
0b
Description
Flow_control
state
0
Flow control state machine signal
Above high
1
The size of data in the memory is above the high threshold
Below low
2
The size of data in the memory is below the low threshold
Reserved
15:3
0x0
Reserved
Refresh
counter
31:16
0x0
Flow control refresh counter
0b = XON
1b = XOFF
Revision: 2.50
October 2011
Intel® 82580EB/82580DB Gigabit Ethernet Controller
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Intel® 82580EB/82580DB GbE Controller — PCIe Register Descriptions
7.6
PCIe Register Descriptions
7.6.1
PCIe Control - GCR (0x5B00; RW)
Register common to all functions.
Field
Bit(s)
Reserved
1:0
Initial Value
0x0
Description
Reserved.
Write 0, ignore on read.
Discard on BME deassert
2
1b
Reserved
4:3
0x0
When set, on BME fall, the PCIE discards all requests of this function
Reserved.
Write 0, ignore on read.
Normal Completion on
Reset
5
0b
Reserved
8:6
0x0
When set on port reset (CTRL.RST), the PCIE will not discard pending
requests of the function, but will wait for normal completion.
Reserved.
Write 0, ignore on read.
Completion Timeout
1b1
9
resend enable
When set, enables a resend request after the completion timeout expires.
0b = Do not resend request after completion timeout
1b = Resend request after completion timeout.
Note: This field is loaded from the “Completion Timeout Resend” bit in the
EEPROM.
Reserved
10
0b
Reserved
Number of resends
12:11
11b
The number of resends in case of Timeout or Poisoned.
Reserved
17:13
0x0
Reserved
PCIe Capability Version
(RO)
18
1b2
Reports the PCIe capability version supported.
0b = Capability version: 0x1.
1b = Capability version: 0x2.
Reserved
30:19
0x0
DEV_RST in progress
31
0b
Reserved.
Device reset in progress
Bit is set following Device Reset assertion (CTRL.DEV_RST = 1) until no
pending requests exist in PCI-E.
Software driver should wait for bit to be cleared before re-initializing the
port (See Section 4.3.1).
1. Loaded from PCIe Completion Timeout Configuration EEPROM word (word 0x15).
2. The default value for this field is read from the PCIe Init Configuration 3 EEPROM word (address 0x1A) bits 11:10. If these bits are
set to 10b, then this field is set to 1, otherwise field is reset to zero.
7.6.2
PCIe Statistics Control #1 - GSCL_1 (0x5B10; RW)
Field
Bit(s)
Initial Value
Description
GIO_COUNT_EN_0
0
0b
Enable PCIe Statistic Counter Number 0.
GIO_COUNT_EN_1
1
0b
Enable PCIe Statistic Counter Number 1.
GIO_COUNT_EN_2
2
0b
Enable PCIe Statistic Counter Number 2.
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PCIe Statistics Control #2 - GSCL_2 (0x5B14; RW) — Intel® 82580EB/82580DB GbE Controller
Field
Bit(s)
Initial Value
Description
GIO_COUNT_EN_3
3
0b
Enable PCIe Statistic Counter Number 3.
LBC Enable 0
4
0b
When set, statistics counter 0 operates in Leaky Bucket mode.
LBC Enable 1
5
0b
When set, statistics counter 1 operates in Leaky Bucket mode.
LBC Enable 2
6
0b
When set, statistics counter 2 operates in Leaky Bucket mode.
LBC Enable 3
7
0b
When set, statistics counter 3 operates in Leaky Bucket mode.
Reserved
26:8
0b
Reserved.
GIO_COUNT_TEST
27
0b
Test Bit
GIO_64_BIT_EN
28
0b
Enable two 64-bit counters instead of four 32-bit counters.
GIO_COUNT_RESET
29
0b
Reset indication of PCIe statistical counters.
GIO_COUNT_STOP
30
0b
Stop indication of PCIe statistical counters.
GIO_COUNT_START
31
0b
Start indication of PCIe statistical counters.
Forward counters for testability.
7.6.3
PCIe Statistics Control #2 - GSCL_2 (0x5B14; RW)
This register configures the events counted by the GSCN_0, GSCN_1, GSCN_2 and GSCN_3 counters.
Field
Bit(s)
Initial Value
Description
GIO_EVENT_NUM_0
7:0
0x0
Event type that counter 0 (GSCN_0) counts.
GIO_EVENT_NUM_1
15:8
0x0
Event type that counter 1 (GSCN_1) counts.
GIO_EVENT_NUM_2
23:16
0x0
Event type that counter 2 (GSCN_2) counts.
GIO_EVENT_NUM_3
31:24
0x0
Event type that counter 3 (GSCN_3) counts.
Table 7-9 lists the encoding of possible event types counted by GSCN_0, GSCN_1, GSCN_2 and
GSCN_3.
Table 7-9.
PCIe Statistic Events Encoding
Transaction layer Events
Bad TLP from LL
Event
Mapping
(Hex)
0x0
Description
Each cycle, the counter increase in 1, if bad TLP is received (bad crc, error
reported by AL, misplaced special char, reset in thI of received tlp).
Requests that reached timeout
0x10
Number of requests that reached Time Out.
NACK DLLP received
0x20
For each cycle, the counter increase by one, if a message was transmitted.
Replay happened in Retry-Buffer
0x21
Occurs when a replay happened due to timeout (not asserted when replay
initiated due to NACK
Receive Error
0x22
Set when one of the following occurs:
1. Decoder error occurred during training in the PHY. It is reported only when
training ends.
2. Decoder error occurred during link-up or till the end of the current packet (in
case the link failed). This error is masked when entering/exiting EI.
Replay Roll-Over
0x23
Occurs when replay was initiated for more than 3 times [threshold is
configurable by the PHY CSRs]
Re-Sending Packets
0x24
Occurs when TLP is resend in case of completion timeout
Surprise Link Down
0x25
Occurs when link is unpredictably down (Not because of reset or DFT)
LTSSM in L0s in both Rx & Tx
0x30
Occurs when LTSSM enters L0s state in both Tx & Rx
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Intel® 82580EB/82580DB GbE Controller — PCIe Statistic Control Register #5...#8 - GSCL_5_8
(0x5B90 + 4*n[n=0...3]; RW)
Table 7-9.
PCIe Statistic Events Encoding (Continued)
Transaction layer Events
LTSSM in L0s in Rx
Event
Mapping
(Hex)
Description
0x31
Occurs when LTSSM enters L0s state in Rx
LTSSM in L0s in Tx
0x32
Occurs when LTSSM enters L0s state in Tx
LTSSM in L1 active
0x33
Occurs when LTSSM enters L1-Active state (Requested from Host side)
LTSSM in L1 SW
0x34
Occurs when LTSSM enters L1-Switch (Requested from Switch side)
LTSSM in recovery
0x35
Occurs when LTSSM enters Recovery state
7.6.4
Note:
PCIe Statistic Control Register #5...#8 - GSCL_5_8
(0x5B90 + 4*n[n=0...3]; RW)
This register is shared for all LAN ports.
These registers control the operation of the statistical counters GSCN_0, GSCN_1, GSCN_2 and GSCN_3
when operating Leaky Bucket mode:
• GSCL_5 controls operation of GSCN_0.
• GSCL_6 controls operation of GSCN_1.
• GSCL_7 controls operation of GSCN_2.
• GSCL_8 controls operation of GSCN_3.
Note:
There are no GSCL_3 and GSCL_4 registers.
Field
Bit(s)
Initial Value
Description
LBC threshold n
15:0
0x0
Threshold for the Leaky Bucket Counter n
LBC timer n
31:16
0x0
Time period between decrementing the value in Leaky Bucket Counter n.
7.6.5
PCIe Counter #0 - GSCN_0 (0x5B20; RC)
Counter is common for all functions.
Field
EVC
Bit(s)
31:0
Initial Value
0x0
Description
Event Counter.
Type of event counted is defined by the GSCL_2.GIO_EVENT_NUM_0 field.
Count value does not wrap around and remains stuck at the maximum
value of 0xFF...F. Value is cleared by read.
7.6.6
PCIe Counter #1 - GSCN_1 (0x5B24; RC)
Counter is common for all functions.
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PCIe Counter #2 - GSCN_2 (0x5B28; RC) — Intel® 82580EB/82580DB GbE Controller
Field
Bit(s)
EVC
Initial Value
31:0
0x0
Description
Event Counter.
Type of event counted is defined by the GSCL_2.GIO_EVENT_NUM_1 field.
Count value does not wrap around and remains stuck at the maximum
value of 0xFF...F. Value is cleared by read.
7.6.7
PCIe Counter #2 - GSCN_2 (0x5B28; RC)
Counter is common for all functions.
Field
Bit(s)
EVC
Initial Value
31:0
0x0
Description
Event Counter.
Type of event counted is defined by the GSCL_2.GIO_EVENT_NUM_2 field.
Count value does not wrap around and remains stuck at the maximum
value of 0xFF...F. Value is cleared by read.
7.6.8
PCIe Counter #3 - GSCN_3 (0x5B2C; RC)
Counter is common for all functions.
Field
Bit(s)
EVC
Initial Value
31:0
0x0
Description
Event Counter.
Type of event counted is defined by the GSCL_2.GIO_EVENT_NUM_3 field.
Count value does not wrap around and remains stuck at the maximum
value of 0xFF...F. Value is cleared by read.
7.6.9
Function Active and Power State to MNG - FACTPS
(0x5B30; RO)
Firmware uses this register for configuration
Field
Func0 Power State
Bit(s)
1:0
Initial Value
00b
Description
Power state indication of Function 0
 DR
 D0u
10b D0a
11b  D3
00b
01b
LAN0 Valid
2
0b
LAN 0 Enable
When set to 0b, it indicates that the LAN 0 function is disabled. When the
function is enabled, the bit is set to 1b.
The LAN 0 enable bit is set by the LAN0_DIS_N strapping pin.
Func0 Aux_En
3
0b
Function 0 Auxiliary (AUX) Power PM Enable bit shadow from the
configuration space.
Reserved
5:4
0b
Reserved.
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Intel® 82580EB/82580DB GbE Controller — Function Active and Power State to MNG - FACTPS (0x5B30;
RO)
Field
Func1 Power State
Bit(s)
7:6
Initial Value
00b
Description
Power state indication of Function 1
 DR
01b  D0u
10b  D0a
11b  D3
00b
LAN1 Valid
8
0b
LAN 1 Enable
When set to 0b, it indicates that the LAN 1 function is disabled. When the
function is enabled, the bit is set to 1b.
The LAN 1 enable bit is set by the LAN1_DIS_N strapping pin.
Func1 Aux_En
9
0b
Function 1 Auxiliary (AUX) Power PM Enable bit shadow from the
configuration space.
Func2 Power State
11:10
00b
Power state indication of Function 2
 DR
 D0u
10b  D0a
11b  D3
00b
01b
LAN2 Valid
12
0b
LAN 2 Enable
When set to 0b, it indicates that the LAN 2 function is disabled. When the
function is enabled, the bit is set to 1b.
The LAN 2 enable bit is set by the LAN2_DIS_N strapping pin.
Func2 Aux_En
13
0b
Func3 Power State
15:14
00b
Function 2 Auxiliary (AUX) Power PM Enable bit shadow from the
configuration space.
Power state indication of Function 3
 DR
 D0u
10b  D0a
11b  D3
00b
01b
LAN3 Valid
16
0b
LAN 3 Enable
When set to 0b, it indicates that the LAN 3 function is disabled. When the
function is enabled, the bit is set to 1b.
The LAN 3 enable bit is set by the LAN3_DIS_N strapping pin.
Func3 Aux_En
17
0b
Function 3 Auxiliary (AUX) Power PM Enable bit shadow from the
configuration space.
Reserved
28:18
0x0
Reserved
MNGCG
29
0b
MNG Clock Gated
LAN Function Sel
301
When set, indicates that the manageability clock is gated.
0b
When all LAN ports are enabled and LAN Function Sel = 0b, LAN 0 is routed
to PCIe Function 0, LAN 1 is routed to PCIe Function 1, etc.
If LAN Function Sel = 1b, LAN 0 is routed to PCIe Function 3, LAN 1 is
routed to PCIe Function 2, LAN 2 is routed to PCIe Function 1 and LAN 3 is
routed to PCIe Function 0.
If a port is disabled a description of the mapping between LAN port and
PCIe function can be found in Section 4.4.2.
Note:
PM State Changed (RC)
31
0b
PCIe Functions Mapping of dual port SKU is like 4 port SKU with
LAN 2 and LAN 3 disabled.
Indication that one or more of the functions power states had changed.
This bit is also a signal to the MNG unit to create an interrupt.
This bit is cleared on read.
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Mirrored Revision ID - MREVID (0x5B64; R/W) — Intel® 82580EB/82580DB GbE Controller
1. This bit is initiated from EEPROM word “Functions Control” (0x21). .
7.6.10
Mirrored Revision ID - MREVID (0x5B64; R/W)
Field
Bit(s)
Initial Value
1
Description
EEPROM
RevID
7:0
0x0
Mirroring of Revision ID loaded from the EEPROM in PCIe configuration
space (from word Device Rev ID word, address 0x1E).
Step REV ID
15:8
0x1
Revision ID from FUNC configuration space.
Reserved
31:16
0x0
Reserved
1. Loaded from EEPROM.
7.6.11
Field
PCIe Control Extended Register - GCR_EXT (0x5B6C; RW)
Bit(s)
Initial
Value
Description
Reserved
3:0
0x0
Reserved
APBACD
4
0b
Auto PBA Clear Disable. When set to 1, Software can clear the PBA only by direct write to clear
access to the PBA bit. When set to 0, any active PBA entry is cleared on the falling edge of the
appropriate interrupt request to the PCIe block. The appropriate interrupt request is cleared
when software sets the associated interrupt mask bit in the EIMS (re-enabling the interrupt)
or by direct write to clear to the PBA.
Reserved
31:5
0x00
Reserved
7.6.12
Note:
Field
PCIe BAR Control - BARCTRL (0x5BBC; R/W) Target
This register is shared by all LAN functions.
Bit(s)
Initial
Value
Description
Reserved
7:0
0x0
Reserved
FLSize
10:8
000b1
This field indicates the size of the external Flash device equals to 64KB x 2FLSize. See table
below for the usable FLASH size.
Note: Value is loaded from EEPROM word Initialization Control Word 2.
Reserved
12:11
0x0
Reserved
CSRSize
13
0b1
The CSRSize and FLSize fields define the usable FLASH size and CSR mapping window size as
shown in Table 7-10 below.
Note: Value is loaded from EEPROM word Initialization Control Word 2.
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Intel® 82580EB/82580DB GbE Controller — Semaphore Registers
Field
PREFBAR
Bit(s)
Initial
Value
14
0b1
Description
Prefetchable bit indication in the memory BARs
0
BARs are marked as non prefetchable
1
BARs are marked as prefetchable
Note: Value is loaded from EEPROM word Functions Control.
BAR32
15
1b1
BAR 32bit Enable. When set 32bit BARs are enabled. At 0b 64 bit BAR addressing mode is
selected.
When PREFBAR bit is set BAR32 bit value should always be 0.
Note: Value is loaded from EEPROM word Functions Control.
Reserved
31:16
0x0
Reserved
1. These bits are loaded from EEPROM.
Table 7-10.
Usable FLASH Size and CSR Mapping Window Size
FLSize
CSRSize
Resulted CSR + FLASH BAR Size
Installed FLASH Device
Usable FLASH Space
000b
0
128KB
No Flash
0
000b
1
256KB
64KB
64KB
001b
0
256KB
128KB
128KB
001b
1
n/a
n/a
Reserved
010b
0
256KB
256KB
256KB minus 128KB
010b
1
512KB
256KB
256KB
011b
0
512KB
512KB
512KB minus 128KB
011b
1
1MB
512KB
512KB
100b
0
1MB
1MB
1MB minus 128KB
100b
1
2MB
1MB
1MB
101b
0
2MB
2MB
2MB minus 128KB
101b
1
4MB
2MB
2MB
110b
0
4MB
4MB
4MB minus 128KB
110b
1
8MB
4MB
4MB
111b
0
8MB
8MB
8MB minus 128KB
111b
1
16MB
8MB
8MB
7.7
Semaphore Registers
This section contains registers common to all ports used to coordinate between all functions. The usage
of these registers is described in Section 4.7
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Software Semaphore - SWSM (0x5B50; R/W) — Intel® 82580EB/82580DB GbE Controller
7.7.1
Software Semaphore - SWSM (0x5B50; R/W)
Field
SMBI (RS)
Bit(s)
Initial Value
0
0x0
Description
Software/Software Semaphore Bit
This bit is set by hardware when this register is read by the device driver
and cleared when the HOST driver writes a 0b to it.
The first time this register is read, the value is 0b. In the next read the
value is 1b (hardware mechanism). The value remains 1b until the software
device driver clears it.
This bit can be used as a semaphore between all the device's drivers in the
82580EB/DB.
This bit is cleared on PCIe reset.
SWESMBI
1
0x0
Software/Firmware Semaphore bit
This bit should be set only by the device driver (read only to firmware). The
bit is not set if bit 0 in the FWSM register is set.
The device driver should set this bit and than read it to verify that it was
set. If it was set, it means that the device driver can access the
SW_FW_SYNC register.
The device driver should clear this bit after modifying the SW_FW_SYNC
register.
Notes:
Reserved
31:2
7.7.2
0x0
•
If Software takes ownership of the SWSM.SWESMBI bit for a duration
longer than 100 mS, Firmware may take ownership of the bit.
•
Hardware clears this bit on PCIe reset.
Reserved
Firmware Semaphore - FWSM (0x5B54; R/WS)
Field1
EEP_FW_Semaphore
Initial
Value
Bit(s)
0
0b
Description
Software/Firmware Semaphore
Firmware should set this bit to 1b before accessing the SW_FW_SYNC
register. If the software is using the SWSM register and does not lock the
SW_FW_SYNC, firmware is able to set this bit to 1b. Firmware should set
this bit back to 0b after modifying the SW_FW_SYNC register.
Note: If Software takes ownership of the SWSM.SWESMBI bit for a
duration longer than 100 mS, Firmware may take ownership of the bit.
FW_Mode
3:1
0x0
Firmware Mode
Indicates the firmware mode as follows:
000b = No MNG.
001b = Reserved.
010b = PT mode.
011b = Reserved.
100b = Host Interface enable only.
Reserved
5:4
00b
Reserved
EEP_Reload_Ind
6
0b
EEPROM reloaded indication
Set to 1b after firmware reloads the EEPROM.
Cleared by firmware once the “Clear Bit” host command is received from
host software.
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Intel® 82580EB/82580DB GbE Controller — Firmware Semaphore - FWSM (0x5B54; R/WS)
Field1
Initial
Value
Bit(s)
Description
Reserved
14:7
0x0
Reserved
FW_Val_Bit
15
0b
Firmware Valid Bit
Hardware clears this bit in reset de-assertion so software can know
firmware mode (bits 1-3) bits are invalid. Firmware should set this bit to
1b when it is ready (end of boot sequence).
Reset_Cnt
18:16
0b
Reset Counter
Firmware increments the count on every Firmware reset. After 7 Firmware
reset events counter stays stuck at 7 and does not wrap around.
Ext_Err_Ind
24:19
0x0
External error indication
Firmware writes here the reason that the firmware operation has stopped.
For example, EEPROM CRC error, etc.
Possible values:
0x00: No Error
0x01 to 0x04: Reserved.
0x05: EEPROM CRC error in SB section.
0x06: EEPROM CRC error in PT-LAN/CSRs sections.
0x07: EEPROM CRC error in FW Code section.
0x08 – CRC error in PHY section.
0x09 - Reserved.
0x0A: No Manageability (No EEPROM)
0x0B to 0x0D: Reserved.
0x0E – TCO isolate mode active.
0x0F: Management memory Parity error.
0x10 to 0x03F: Reserved
Note: When management error is detected, ICR.MGMT is set and an
interrupts is sent to the Host. Ext_Err_ind values of 0x00 or 0x0A do not
cause interrupt generation.
PCIe_Config_Err_Ind
25
0b
PCIe configuration error indication
Set to 1b by firmware when it fails to configure PCIe interface.
Cleared by firmware upon successful configuration of PCIe interface.
PHY_SERDES0_Config_
26
0b
Err_Ind
PHY/SerDes0 configuration error indication
Set to 1b by firmware when it fails to configure LAN0 PHY/SerDes.
Cleared by firmware upon successful configuration of LAN0 PHY/SerDes.
PHY_SERDES1_Config_
27
0b
Err_Ind
PHY/SerDes1 configuration error indication
Set to 1b by firmware when it fails to configure LAN1 PHY/SerDes.
Cleared by firmware upon successful configuration of LAN1 PHY/SerDes.
Reserved
28
0b
Reserved.
SERDES2_Config_
29
0b
SerDes2 configuration error indication
Err_Ind
Set to 1b by firmware when it fails to configure LAN2 SerDes.
Cleared by firmware upon successful configuration of LAN2 SerDes.
SERDES3_Config_
30
0b
Err_Ind
SerDes3 configuration error indication
Set to 1b by firmware when it fails to configure LAN3 SerDes.
Cleared by firmware upon successful configuration of LAN3 SerDes.
Reserved
31
0b
Reserved.
Notes:
1.
This register should be written only by the manageability firmware. The device driver should only read this register.
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Software–Firmware Synchronization - SW_FW_SYNC (0x5B5C; RWS) — Intel® 82580EB/82580DB GbE
Controller
2.
3.
Firmware ignores the EEPROM semaphore in operating system hung states.
Bits 15:0 are cleared on firmware reset.
7.7.3
Software–Firmware Synchronization - SW_FW_SYNC
(0x5B5C; RWS)
This register is intended to synchronize between software and firmware. This register is common to all
ports.
Note:
If Software takes ownership of bits in the SW_FW_SYNC register for a duration longer than
1 Second, Firmware may take ownership of the bit.
Field
Initial
Value
Bit(s)
Description
SW_EEP_SM
0
0b
When set to 1b, EEPROM access is owned by software
SW_PHY_SM0
1
0b
When set to 1b, SerDes/PHY 0 access is owned by software
SW_PHY_SM1
2
0b
When set to 1b, SerDes/PHY 1 access is owned by software
SW_MAC_CSR_SM 3
0b
When set to 1b, software owns access to shared CSRs
SW_FLASH_SM
4
0
When set to 1b, software owns access to the flash.
SW_PHY_SM2
5
0b
When set to 1b, SerDes/PHY 2 access is owned by software
SW_PHY_SM3
6
0b
When set to 1b, SerDes/PHY 3 access is owned by software
Reserved
7
0b
Reserved.
Write 0, ignore on read.
SW_MB_SM
8
0b
When Set to 1b, SWMBWR mailbox write register, is owned by software driver.
Reserved
15:9
0x0
Reserved for future use
FW_EEP_SM
16
0b
When set to 1b, EEPROM access is owned by firmware
FW_PHY_SM0
17
0b
When set to 1b, PHY 0 access is owned by firmware
FW_PHY_SM1
18
0b
When set to 1b, PHY 1 access is owned by firmware
FW_MAC_CSR_SM 19
0b
When set to 1b, firmware owns access to shared CSRs
FW_FLASH_SM
20
0
When set to 1b, firmware owns access to the flash.
FW_PHY_SM2
21
0b
When set to 1b, PHY 2 access is owned by firmware
FW_PHY_SM3
22
0b
When set to 1b, PHY 3 access is owned by firmware
Reserved
31:23
0x0
Reserved for future use
Reset conditions:
• The software-controlled bits 15:0 are reset as any other CSR on global resets, D3hot exit and
Forced TCO. Software is expected to clear the bits on entry to D3 state.
• The Firmware controlled bits (bits 31:16) are reset on LAN_PWR_GOOD (power-up) and firmware
reset.
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Intel® 82580EB/82580DB GbE Controller — Software Mailbox Write - SWMBWR (0x5B04; R/W)
7.7.4
Software Mailbox Write - SWMBWR (0x5B04; R/W)
Field
Mailbox
Bit(s)
31:0
Initial Value
0x0
Description
Message sent from driver to the other drivers. The interpretation of this
field is defined by the drivers.
This register is reset only by power on reset.
7.7.5
Software Mailbox 0 - SWMB0 (0x5B08; RO)
Field
Mailbox
Bit(s)
31:0
Initial Value
0x0
Description
Message sent from the driver of port 0. The interpretation of this field is
defined by the drivers.
This register is reset only by power on reset.
7.7.6
Software Mailbox 1 - SWMB1 (0x5B0C; RO)
Field
Mailbox
Bit(s)
31:0
Initial Value
0x0
Description
Message sent from the driver of port 1. The interpretation of this field is
defined by the drivers.
This register is reset only by power on reset.
7.7.7
Software Mailbox 2 - SWMB2 (0x5B18; RO)
Field
Mailbox
Bit(s)
31:0
Initial Value
0x0
Description
Message sent from the driver of port 2. The interpretation of this field is
defined by the drivers.
This register is reset only by power on reset.
7.7.8
Software Mailbox 3 - SWMB3 (0x5B1C; RO)
Field
Mailbox
Bit(s)
31:0
Initial Value
0x0
Description
Message sent from the driver of port 3.The interpretation of this field is
defined by the drivers.
This register is reset only by power on reset.
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Interrupt Register Descriptions — Intel® 82580EB/82580DB GbE Controller
7.8
Interrupt Register Descriptions
7.8.1
PCIe Interrupt Cause - PICAUSE (0x5B88; RW1/C)
Field
Bit(s)
Init.
CA
0
0b
UA
1
0b
Description
PCI Completion Abort exception issued.
Unsupported IO address exception.
Bit is set when:
IO access to address outside of the allocated address space is detected.
IO access to non-CSR address space (Flash access).
Write access to IOADDR with partial Byte-Enable.
Note:
When IO access via configuration space is enabled bit should be masked.
BE
2
0b
Wrong Byte-Enable exception in the FUNC unit.
TO
3
0b
PCI Timeout exception in the FUNC unit.
BMEF
4
0b
Asserted when bus-master-enable (BME) of the PF is de-asserted.
ABR
5
0b
PCI Completer Abort Received.
PCI Completer Abort (CA) or Unsupported Request (UR) received (Set on reception of CA or
UR).
Note:
Reserved
7.8.2
Field
31:6
0x0
When bit is set all PCIe master activity is stopped. Software should issue a software
(CTRL.RST) reset to enable PCIe activity on all ports.
Reserved
PCIe Interrupt Enable - PIENA (0x5B8C; R/W)
Bit(s)
Init.
CA
0
0b
UA
1
0b
Description
When set to 1 the PCI Completion Abort interrupt is enabled.
When set to 1 the Unsupported IO address interrupt is enabled.
Note:
When IO access via configuration space is enabled bit should be 0b.
BE
2
0b
When set to 1 the Wrong Byte-Enable interrupt is enabled.
TO
3
0b
When set to 1 the PCI Timeout interrupt is enabled.
BMEF
4
0b
When set to 1 the Bus Master Enable interrupt is enabled.
ABR
5
0b
When set to 1 the PCI completion abort received interrupt is enabled.
Reserved
31:6
0x0
Reserved
7.8.3
Extended Interrupt Cause - EICR (0x1580; RC/W1C)
This register contains the frequent interrupt conditions for the 82580EB/DB. Each time an interrupt
event occurs, the corresponding interrupt bit is set in this register. An interrupt is generated each time
one of the bits in this register is set and the corresponding interrupt is enabled via the Interrupt Mask
Set/Read (EIMS) register. The interrupt might be delayed by the selected Interrupt Throttling register.
Note that the software device driver cannot determine from the RxTxQ bits what was the cause of the
interrupt. The possible causes for asserting these bits are:
• Receive Descriptor Write Back, Receive Descriptor Minimum Threshold hit, low latency interrupt for
Rx, Transmit Descriptor Write Back.
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Intel® 82580EB/82580DB GbE Controller — Extended Interrupt Cause Set - EICS (0x1520; WO)
Writing a 1b to any bit in the register clears that bit. Writing a 0b to any bit has no effect on that bit.
Register bits are cleared on register read if GPIE.Multiple_MSIX = 0.
Auto clear can be enabled for any or all of the bits in this register, via the EIAC register.
Table 7-11.
Field
RxTxQ
EICR Register Bit Description - non MSI-X mode (GPIE.Multiple_MSIX = 0)
Bit(s)
7:0
Initial Value
0x0
Description
Receive/Transmit Queue Interrupts
One bit per queue or a bundle of queues, activated on receive/transmit queue events
for the corresponding bit, such as:
Receive Descriptor Write Back,
Receive Descriptor Minimum Threshold hit
Transmit Descriptor Write Back.
The mapping of actual queue to the appropriate RxTxQ bit is according to the IVAR
registers.
Reserved
29:8
0x0
Reserved
TCP Timer
30
0b
TCP Timer Expired
Other Cause
31
0b
Activated when the TCP timer reaches its terminal count.
Interrupt Cause Active
Activated when any bit in the ICR register is set.
Note:
Bits are not reset by Device Reset (CTRL.DEV_RST).
Table 7-12.
Field
MSIX
EICR Register Bit Description - MSI-X mode (GPIE.Multiple_MSIX = 1)
Bit(s)
9:0
Initial Value
0x0
Description
Indicates an interrupt cause mapped to MSI-X vectors 9:0
Note: Bits are not reset by Device Reset (CTRL.DEV_RST).
Reserved
31:10
7.8.4
0x0
Reserved
Extended Interrupt Cause Set - EICS (0x1520; WO)
Software uses this register to set an interrupt condition. Any bit written with a 1b sets the
corresponding bit in the Extended Interrupt Cause Read register. An interrupt is then generated if one
of the bits in this register is set and the corresponding interrupt is enabled via the Extended Interrupt
Mask Set/Read register. Bits written with 0b are unchanged.
Table 7-13.
EICS Register Bit Description - non MSI-X mode (GPIE.Multiple_MSIX = 0)
Field
Bit(s)
Initial Value
Description
RxTxQ
7:0
0x0
Sets to corresponding EICR RxTXQ interrupt condition.
Reserved
29:8
0x0
Reserved
TCP Timer
30
0b
Sets the corresponding EICR TCP Timer interrupt condition.
Reserved
31
0b
Reserved
Note:
In order to set bit 31 of the EICR (Other Causes), the ICS and IMS registers should be used
in order to enable one of the legacy causes.
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Extended Interrupt Mask Set/Read - EIMS (0x1524; RWS) — Intel® 82580EB/82580DB GbE Controller
Table 7-14.
EICS Register Bit Description - MSI-X mode (GPIE.Multiple_MSIX = 1)
Field
Bit(s)
Initial Value
Description
MSIX
9:0
0x0
Sets the corresponding EICR bit of MSI-X vectors 9:0
Reserved
31:10
0x0
Reserved
7.8.5
Extended Interrupt Mask Set/Read - EIMS (0x1524; RWS)
Reading of this register returns which bits have an interrupt mask set. An interrupt in EICR is enabled if
its corresponding mask bit is set to 1b and disabled if its corresponding mask bit is set to 0b. A PCI
interrupt is generated each time one of the bits in this register is set and the corresponding interrupt
condition occurs (subject to throttling). The occurrence of an interrupt condition is reflected by having a
bit set in the Extended Interrupt Cause Read register.
An interrupt might be enabled by writing a 1b to the corresponding mask bit location (as defined in the
EICR register) in this register. Any bits written with a 0b are unchanged. As a result, if software needs
to disable an interrupt condition that had been previously enabled, it must write to the Extended
Interrupt Mask Clear (EIMC) register rather than writing a 0b to a bit in this register.
Table 7-15.
Field
EIMS Register Bit Description - non MSI-X mode (GPIE.Multiple_MSIX = 0)
Bit(s)
Initial Value
Description
RxTxQ
7:0
0x0
Set Mask bit for the corresponding EICR RxTXQ interrupt.
Reserved
29:8
0x0
Reserved
TCP Timer
30
0b
Set Mask bit for the corresponding EICR TCP timer interrupt condition.
Other Cause
31
1b
Set Mask bit for the corresponding EICR Other Cause interrupt condition.
Note:
Bits are not reset by Device Reset (CTRL.DEV_RST).
Table 7-16.
Field
MSIX
EIMS Register Bit Description - MSI-X mode (GPIE.Multiple_MSIX = 1)
Bit(s)
9:0
Initial Value
0x0
Description
Set Mask bit for the corresponding EICR bit of MSI-X vectors 9:0.
Note: Bits are not reset by Device Reset (CTRL.DEV_RST).
Reserved
7.8.6
31:10
0x0
Reserved
Extended Interrupt Mask Clear - EIMC (0x1528; WO)
This register provides software a way to disable certain or all interrupts. Software disables a given
interrupt by writing a 1b to the corresponding bit in this register.
On interrupt handling, the software device driver should set all the bits in this register related to the
current interrupt request even though the interrupt was triggered by part of the causes that were
allocated to this vector.
Interrupts are presented to the bus interface only when the mask bit is set to 1b and the cause bit is
set to 1b. The status of the mask bit is reflected in the Extended Interrupt Mask Set/Read register and
the status of the cause bit is reflected in the Interrupt Cause Read register.
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Intel® 82580EB/82580DB GbE Controller — Extended Interrupt Auto Clear - EIAC (0x152C; R/W)
Software blocks interrupts by clearing the corresponding mask bit. This is accomplished by writing a 1b
to the corresponding bit location (as defined in the EICR register) of that interrupt in this register. Bits
written with 0b are unchanged (their mask status does not change).
Table 7-17.
EIMC Register Bit Description - non MSI-X mode (GPIE.Multiple_MSIX = 0)
Field
Bit(s)
Initial Value
Description
RxTxQ
7:0
0x0
Reserved
29:8
0x0
Reserved
TCP Timer
30
0b
Clear Mask bit for the corresponding EICR TCP timer interrupt.
Other Cause
31
1b
Clear Mask bit for the corresponding EICR other cause interrupt.
Table 7-18.
Clear Mask bit for the corresponding EICR RxTXQ interrupt.
EIMC Register Bit Description - MSI-X mode (GPIE.Multiple_MSIX = 1)
Field
Bit(s)
Initial Value
Description
MSIX
9:0
0x0
Clear Mask bit for the corresponding EICR bit of MSI-X vectors 9:0
Reserved
31:10
0x0
Reserved
7.8.7
Extended Interrupt Auto Clear - EIAC (0x152C; R/W)
This register is mapped like the EICS, EIMS, and EIMC registers, with each bit mapped to the
corresponding MSI-X vector.
This register is relevant to MSI-X mode only, where read-to-clear can not be used, as it might erase
causes tied to other vectors. If any bits are set in EIAC, the EICR register should not be read. Bits
without auto clear set, need to be cleared with write-to-clear.
Note:
EICR bits that have auto clear set are cleared by the internal emission of the corresponding
MSI-X message even if this vector is disabled by the operating system.
The MSI-X message can be delayed by EITR moderation from the time the EICR bit is
activated.
Table 7-19.
Field
MSIX
EIAC Register Bit Description - MSI-X mode (GPIE.Multiple_MSIX = 1)
Bit(s)
9:0
Initial Value
0x0
Description
Auto clear bit for the corresponding EICR bit of MSI-X vectors 9:0.
Notes:
Reserved
7.8.8
31:10
0x0
•
Bits are not reset by Device Reset (CTRL.DEV_RST).
•
When GPIE.Multiple_MSIX = 0 (Non MSI-X mode) bits 8 and 9 are read only and
should be ignored.
Reserved
Extended Interrupt Auto Mask Enable EIAM (0x1530; R/W)
Each bit in this register enables clearing of the corresponding bit in EIMS following read- or write-toclear to EICR or setting of the corresponding bit in EIMS following a write-to-set to EICS.
In MSI-X mode, this register controls which of the bits in EIMC to clear upon interrupt generation.
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Interrupt Cause Read Register - ICR (0x1500; RC/W1C) — Intel® 82580EB/82580DB GbE Controller
Table 7-20.
Field
RxTxQ
EIAM Register Bit Description - non MSI-X mode (GPIE.Multiple_MSIX = 0)
Bit(s)
7:0
Initial Value
0x0
Description
Auto Mask bit for the corresponding EICR RxTxQ interrupt.
Reserved
29:8
0x0
Reserved
TCP Timer
30
0b
Auto mask bit for the corresponding EICR TCP Timer interrupt condition.
Other Cause
31
0b
Auto mask bit for the corresponding EICR Other Cause interrupt condition.
Note:
Bits are not reset by Device Reset (CTRL.DEV_RST).
Table 7-21.
Field
MSIX
EIAM Register Bit Description - MSI-X mode (GPIE.Multiple_MSIX = 1)
Bit(s)
9:0
Initial Value
0x0
Description
Auto Mask bit for the corresponding EICR bit of MSI-X vectors 9:0.
Note: Bits are not reset by Device Reset (CTRL.DEV_RST).
Reserved
7.8.9
31:10
0x0
Reserved
Interrupt Cause Read Register - ICR (0x1500; RC/W1C)
This register contains the interrupt conditions for the 82580EB/DB that are not present directly in the
EICR. Each time an ICR interrupt causing event occurs, the corresponding interrupt bit is set in this
register. The EICR.Other bit reflects the setting of interrupt causes from ICR as masked by the Interrupt
Mask Set/Read register. Each time all un-masked causes in ICR are cleared, the EICR.Other Cause bit is
also cleared.
ICR bits are cleared on register read. Clear-on-read can be enabled/disabled through a general
configuration register bit. See Section 8.3.2 for additional information.
Auto clear is not available for the bits in this register.
In order to prevent unwanted LSC (Link Status Change) interrupts during initialization, software should
disable this interrupt until the end of initialization.
Field
TXDW
Bit(s)
0
Initial Value
0b
Description
Transmit Descriptor Written Back
Set when the 82580EB/DB writes back a Tx descriptor to memory.
Reserved
1
0b
Reserved
Write 0, ignore on read.
LSC
2
0b
Link Status Change
This bit is set each time the link status changes (either from up to down, or from
down to up). This bit is affected by the LINK indication from the PHY (internal
PHY mode).
Reserved
3
0b
Reserved
Write 0, ignore on read.
RXDMT0
4
0b
Receive Descriptor Minimum Threshold Reached
Indicates that the minimum number of receive descriptors are available and
software should load more receive descriptors.
Reserved
5
0b
Reserved
Write 0, ignore on read.
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Intel® 82580EB/82580DB GbE Controller — Interrupt Cause Read Register - ICR (0x1500; RC/W1C)
Field
Rx Miss
Bit(s)
6
Initial Value
0b
Description
Missed packet interrupt is activated for each received packet that overflows the
Rx packet buffer (overrun). Note that the packet is dropped and also increments
the associated MPC counter.
Note: Could be caused by no available receive buffers or because PCIe receive
bandwidth is inadequate.
RXDW
7
0b
Receiver Descriptor Write Back
Set when the 82580EB/DB writes back an Rx descriptor to memory.
SWMB
8
0b
Set when one of the drivers wrote a message using the SWMBWR mailbox
register.
Reserved
9
0b
Reserved
GPHY
10
0b
Internal 1000/100/10BASE-T PHY interrupt.
See Section 7.24.2.22 for further information.
GPI_SDP0
11
0b
General Purpose Interrupt on SDP0
If GPI interrupt detection is enabled on this pin (via CTRL.SDP0_GPIEN), this
interrupt cause is set when the SDP0 is sampled high.
GPI_SDP1
12
0b
General Purpose Interrupt on SDP1
If GPI interrupt detection is enabled on this pin (via CTRL.SDP1_GPIEN), this
interrupt cause is set when the SDP1 is sampled high.
GPI_SDP2
13
0b
General Purpose Interrupt on SDP2
If GPI interrupt detection is enabled on this pin (via CTRL_EXT.SDP2_GPIEN),
this interrupt cause is set when the SDP2 is sampled high.
GPI_SDP3
14
0b
General Purpose Interrupt on SDP3
If GPI interrupt detection is enabled on this pin (via CTRL_EXT.SDP3_GPIEN),
this interrupt cause is set when the SDP3 is sampled high.
Reserved
17:15
000b
Reserved
MNG
18
0b
Manageability Event Detected
Indicates that a manageability event happened. When bit is set due to detection
of error by Management, FWSM.Ext_Err_Ind field is updated with the error
cause.
Time_Sync
19
0b
Time_Sync Interrupt
This interrupt cause is set if Interrupt is generated by the Time Sync Interrupt
registers (TSICR, TSIM and TSIS).
OMED
20
0b
Other Media Energy Detect
When in SerDes/SGMII mode, indicates that link status has changed on the
external media or when in internal 1000BASE-T PHY mode, there is a change in
the 10/100/1000BASE-T link status.
Reserved
21
0b
FER
22
0b
Reserved
Fatal Error
This bit is set when a fatal error is detected in one of the memories
Reserved
23
0b
Reserved
Write 0, ignore on read.
PCI Exception
24
0b
The PCI timeout Exception is activated by one of the following events when the
specific PCI event is reported in the PICAUSE register and the appropriate bit in
the PIENA register is set:
(1) IO completion abort.
(2) Unsupported IO request (Wrong address).
(3) Byte-Enable error - Access to client that does not support Partial BE access
(All but Flash, MSIX & PCIE-target).
(4) Timeout occurred in the FUNC block.
(5) Bus-master-enable (BME) of the PF is cleared.
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Interrupt Cause Set Register - ICS (0x1504; WO) — Intel® 82580EB/82580DB GbE Controller
Field
SCE
Bit(s)
25
Initial Value
0b
Description
Storm Control Event
This bit is set when multicast or broadcast storm control mechanism is activated
or de-activated.
Software WD
26
0b
Software Watchdog
This bit is set after a software watchdog timer times out.
Reserved
27
0b
Reserved
MDDET
28
0b
Detected Malicious driver behavior
Occurs when one of the queues used malformed descriptors. In virtualized
systems, might indicate a malicious or buggy driver.
Note:
TCP timer
29
0b
This bit should never rise during normal operation.
TCP timer interrupt
Activated when the TCP timer reaches its terminal count.
DRSTA
30
0b
Device Reset Asserted
Indicates the CTRL.DEV_RST was asserted on another port or on this port. When
device reset occurs all ports should re-initialize registers and descriptor rings.
Note: Bit is not reset by Device Reset (CTRL.DEV_RST).
INTA
31
7.8.10
0
Interrupt Asserted: Indicates that the INT line is asserted. Can be used by driver
in shared interrupt scenario to decide if the received interrupt was emitted by
the 82580EB/DB. This bit is not valid in MSI/MSI-X environments
Interrupt Cause Set Register - ICS (0x1504; WO)
Software uses this register to set an interrupt condition. Any bit written with a 1b sets the
corresponding interrupt. This results in the corresponding bit being set in the Interrupt Cause Read
Register (see Section 7.8.9). A PCIe interrupt is generated if one of the bits in this register is set and
the corresponding interrupt is enabled through the Interrupt Mask Set/Read Register (see
Section 7.8.11). Bits written with 0b are unchanged. See Section 8.3.2 for additional information.
Field
Bit(s)
Initial Value
TXDW
0
0b
Reserved
1
0b
Description
Sets the Transmit Descriptor Written Back Interrupt.
Reserved
Write 0, ignore on read.
LSC
2
0b
Reserved
3
0b
Sets the Link Status Change Interrupt.
Reserved
Write 0, ignore on read.
RXDMT0
4
0b
Sets the Receive Descriptor Minimum Threshold Hit Interrupt.
Reserved
5
0b
Reserved
Rx Miss
6
0b
Sets the Rx Miss Interrupt.
RXDW
7
0b
Sets the Receiver Descriptor Write Back Interrupt.
SWMB
8
0b
Sets the SWMB mailbox interrupt.
Write 0, ignore on read.
Reserved
9
0b
Reserved
GPHY
10
0b
Sets the Internal 1000/100/10BASE-T PHY interrupt.
GPI_SDP0
11
0b
Sets the General Purpose Interrupt, related to SDP0 pin.
GPI_SDP1
12
0b
Sets the General Purpose Interrupt, related to SDP1 pin.
GPI_SDP2
13
0b
Sets the General Purpose Interrupt, related to SDP2 pin.
GPI_SDP3
14
0b
Sets the General Purpose Interrupt, related to SDP3 pin.
Revision: 2.50
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Intel® 82580EB/82580DB GbE Controller — Interrupt Mask Set/Read Register - IMS (0x1508; R/W)
Field
Bit(s)
Initial Value
Description
Reserved
17:15
000b
Reserved.
MNG
18
0b
Sets the Management Event Interrupt.
Reserved
19
0b
Reserved
OMED
20
0b
Sets the Other Media Energy Detected Interrupt.
Reserved
21
0b
Reserved
FER
22
0b
Sets the Fatal Error Interrupt.
Reserved
23
0b
Reserved
Write 0, ignore on read.
PCI Exception
24
0b
Sets the PCI Exception Interrupt.
SCE
25
0b
Set the Storm Control Event Interrupt
Software WD
26
0b
Sets the Software Watchdog Interrupt.
Reserved
27
0b
Reserved.
MDDET
28
0b
Sets the Detected Malicious driver behavior Interrupt.
TCP timer
29
0b
Sets the TCP timer interrupt.
DRSTA
30
0b
Sets the Device Reset Asserted Interrupt.
Note that when setting this bit a DRSTA interrupt is generated on this port
only.
Reserved
7.8.11
31
0b
Reserved.
Interrupt Mask Set/Read Register - IMS (0x1508; R/W)
Reading this register returns bits that have an interrupt mask set. An interrupt is enabled if its
corresponding mask bit is set to 1b and disabled if its corresponding mask bit is set to 0b. A PCIe
interrupt is generated each time one of the bits in this register is set and the corresponding interrupt
condition occurs. The occurrence of an interrupt condition is reflected by having a bit set in the
Interrupt Cause Read Register (see Section 7.8.9).
A particular interrupt can be enabled by writing a 1b to the corresponding mask bit in this register. Any
bits written with a 0b are unchanged. As a result, if software desires to disable a particular interrupt
condition that had been previously enabled, it must write to the Interrupt Mask Clear Register (see
Section 7.8.12) rather than writing a 0b to a bit in this register. See Section 8.3.2 for additional
information.
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Interrupt Mask Clear Register - IMC (0x150C; WO) — Intel® 82580EB/82580DB GbE Controller
Field
Bit(s)
Initial Value
TXDW
0
0b
Reserved
1
0b
Description
Sets/Reads the mask for Transmit Descriptor Written Back Interrupt.
Reserved
Write 0, ignore on read.
LSC
2
0b
Reserved
3
0b
Sets/Reads the mask for Link Status Change Interrupt.
Reserved
Write 0, ignore on read.
RXDMT0
4
0b
Sets/Reads the mask for Receive Descriptor Minimum Threshold Hit Interrupt.
Reserved
5
0b
Reserved
Rx Miss
6
0b
Sets/Reads the mask for the Rx Miss Interrupt.
RXDW
7
0b
Sets/Reads the mask for Receiver Descriptor Write Back Interrupt.
SWMB
8
0b
Sets/Reads the mask for Software Mailbox Interrupt.
Write 0, ignore on read.
Reserved
9
0b
Reserved
GPHY
10
0b
Sets/Reads the mask for Internal 1000/100/10BASE-T PHY interrupt.
GPI_SDP0
11
0b
Sets/Reads the mask for General Purpose Interrupt, related to SDP0 pin.
GPI_SDP1
12
0b
Sets/Reads the mask for General Purpose Interrupt, related to SDP1 pin.
GPI_SDP2
13
0b
Sets/Reads the mask for General Purpose Interrupt, related to SDP2 pin.
GPI_SDP3
14
0b
Sets/Reads the mask for General Purpose Interrupt, related to SDP3 pin.
Reserved
17:15
000b
Reserved.
MNG
18
0b
Sets/Reads the mask for Management Event Interrupt.
Reserved
19
0b
Reserved
OMED
20
0b
Sets/Reads the mask for Other Media Energy Detected Interrupt.
Reserved
21
0b
Reserved
FER
22
0b
Sets/Reads the mask for the Fatal Error Interrupt.
Reserved
23
0b
Reserved
Write 0, ignore on read.
PCI Exception
24
0b
Sets/Reads the mask for the PCI Exception Interrupt.
SCE
25
0b
Sets/Reads the mask for the Storm Control Event Interrupt.
Software WD
26
0b
Sets/Reads the mask for the Software Watchdog Interrupt.
Reserved
27
0b
Reserved.
MDDET
28
0b
Sets/Reads the mask for the Detected Malicious driver behavior Interrupt.
TCP timer
29
0b
Sets/Reads the mask for TCP timer interrupt.
DRSTA
30
0b
Sets/Reads the mask for Device Reset Asserted Interrupt.
Note: Bit is not reset by Device Reset (CTRL.DEV_RST).
Reserved
7.8.12
31
0b
Reserved.
Interrupt Mask Clear Register - IMC (0x150C; WO)
Software uses this register to disable an interrupt. Interrupts are presented to the bus interface only
when the mask bit is set to 1b and the cause bit set to 1b. The status of the mask bit is reflected in the
Interrupt Mask Set/Read Register (see Section 7.8.11), and the status of the cause bit is reflected in
the Interrupt Cause Read Register (see Section 7.8.9). Reading this register returns the value of the
IMS register.
Revision: 2.50
October 2011
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Intel® 82580EB/82580DB GbE Controller — Interrupt Mask Clear Register - IMC (0x150C; WO)
Software blocks interrupts by clearing the corresponding mask bit. This is accomplished by writing a 1b
to the corresponding bit in this register. Bits written with 0b are unchanged (their mask status does not
change).
The software device driver should set all the bits in this register related to the current interrupt request
when handling interrupts, even though the interrupt was triggered by part of the causes that were
allocated to this vector. See Section 8.3.2 for additional information.
Field
Bit(s)
Initial Value
TXDW
0
0b
Reserved
1
0b
Description
Clears the mask for Transmit Descriptor Written Back Interrupt.
Reserved
Write 0, ignore on read.
LSC
2
0b
Clears the mask for Link Status Change Interrupt.
Reserved
3
0b
Reserved
RXDMT0
4
0b
Reserved
5
0b
Write 0, ignore on read.
Clears the mask for Receive Descriptor Minimum Threshold Hit Interrupt.
Reserved
Write 0, ignore on read.
Rx Miss
6
0b
Clears the mask for the Rx Miss Interrupt.
RXDW
7
0b
Clears the mask for the Receiver Descriptor Write Back Interrupt.
SWMB
8
0b
Clears the mask for the Software Mailbox interrupt.
Reserved
9
0b
Reserved
GPHY
10
0b
Clears the mask for the Internal 1000/100 10BASE-T PHY interrupt
GPI_SDP0
11
0b
Clears the mask for the General Purpose Interrupt, related to SDP0 pin.
GPI_SDP1
12
0b
Clears the mask for the General Purpose Interrupt, related to SDP1 pin.
GPI_SDP2
13
0b
Clears the mask for the General Purpose Interrupt, related to SDP2 pin.
GPI_SDP3
14
0b
Clears the mask for the General Purpose Interrupt, related to SDP3 pin.
Reserved
17:15
000b
Reserved.
MNG
18
0b
Clears the mask for the Management Event Interrupt.
Reserved
19
0b
Reserved
OMED
20
0b
Clears the mask for the Other Media Energy Detected Interrupt.
Reserved
21
0b
Reserved
FER
22
0b
Clears the mask for the Fatal Error Interrupt.
Reserved
23
0b
Reserved
PCI Exception
24
0b
Clears the mask for the PCI Exception Interrupt.
SCE
25
0b
Clears the mask for the Storm Control Event Interrupt.
Software WD
26
0b
Clears the mask for Software Watchdog Interrupt.
Reserved
27
0b
Write 0, ignore on read.
Reserved.
Write 0, ignore on read.
MDDET
28
0b
Clears the mask for the Detected Malicious driver behavior Interrupt.
TCP timer
29
0b
Clears the mask for TCP timer interrupt.
DRSTA
30
0b
Clears the mask for Device Reset Asserted Interrupt.
Reserved
31
0b
Reserved.
Write 0, ignore on read.
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Interrupt Acknowledge Auto Mask Register - IAM (0x1510; R/W) — Intel® 82580EB/82580DB GbE
Controller
7.8.13
Interrupt Acknowledge Auto Mask Register - IAM (0x1510;
R/W)
Field
IAM_VALUE
Bit(s)
Initial Value
31:0
0b
Description
An ICR read or write will have the side effect of writing the contents of this
register to the IMC (Interrupt Mask Clear) register. If GPIE.NSICR = 0,
then the copy of this register to the IMC register will occur only if at least
one bit is set in the IMS register and there is a true interrupt as reflected
in the ICR.INTA bit.
See Section 8.3.2 for additional information.
Note: Bit 30 of this register is not reset by Device Reset (CTRL.DEV_RST).
7.8.14
Interrupt Throttle - EITR (0x1680 + 4*n [n = 0...9]; R/W)
Each EITR is responsible for an interrupt cause (RxTxQ, TCP timer and Other Cause). The allocation of
EITR-to-interrupt cause is through the IVAR registers.
Software uses this register to pace (or even out) the delivery of interrupts to the host processor. This
register provides a guaranteed inter-interrupt delay between interrupts asserted by the 82580EB/DB,
regardless of network traffic conditions. To independently validate configuration settings, software can
use the following algorithm to convert the inter-interrupt interval value to the common interrupts/sec.
performance metric:
interrupts/sec = (1 * 10-6sec x interval)-1
A counter counts in units of 1*10-6 sec. After counting “interval “number of units, an interrupt is sent to
the software. The above equation gives the number of interrupts per second. The equation below time
in seconds between consecutive interrupts.
For example, if the interval is programmed to 125 (decimal), the 82580EB/DB guarantees the
processor does not receive an interrupt for 125 s from the last interrupt. The maximum observable
interrupt rate from the 82580EB/DB should never exceed 8000 interrupts/sec.
Inversely, inter-interrupt interval value can be calculated as:
inter-interrupt interval = (1 * 10-6sec x interrupt/sec)-1
The optimal performance setting for this register is very system and configuration specific. An initial
suggested range is 2 to 175 (0x02 to 0xAF).
Note:
Setting EITR to a non zero value can cause an interrupt cause Rx/Tx statistics miscount.
Field
Bit(s)
Initial Value
Description
Reserved
1:0
0x0
Reserved
Interval
14:2
0x0
Minimum inter-interrupt interval. The interval is specified in 1 s increments. A zero
disables interrupt throttling logic.
LLI_EN
15
0b
LLI moderation enable.
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October 2011
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321
Intel® 82580EB/82580DB GbE Controller — Interrupt Vector Allocation Registers - IVAR (0x1700 +
4*n [n=0...3]; RW)
Field
Bit(s)
Initial Value
Description
Reserved
1:0
0x0
Reserved
LL Counter
(RWS)
20:16
0x0
Reflects the current credits for that EITR for LL interrupts. If the CNT_INGR is not set
this counter can be directly written by software at any time to alter the throttles
performance
Moderation
Counter
(RWS)
30:21
0x0
Down counter, exposes only the 10 most significant bits of the real 12-bit counter.
Loaded with Interval value whenever the associated interrupt is signaled. Counts
down to 0 and stops. The associated interrupt is signaled whenever this counter is
zero and an associated (via the Interrupt Select register) EICR bit is set.
If the CNT_INGR is not set this counter can be directly written by software at any
time to alter the throttles performance.
CNT_INGR
(WO)
31
0b
When set the hardware does not override the counters fields (ITR counter and LLI
credit counter), so they keep their previous value.
Relevant for the current write only and is always read as zero
Note:
EITR register and interrupt mechanism is not reset by Device Reset (CTRL.DEV_RST).
Occurrence of Device Reset interrupt causes immediate generation of all pending interrupts.
7.8.15
Interrupt Vector Allocation Registers IVAR (0x1700 + 4*n [n=0...3]; RW)
These registers have two modes of operation:
1. In MSI-X mode these registers define the allocation of the different interrupt causes as defined in
Table 8-48 to one of the MSI-X vectors. Each INT_Alloc[i] (i=0…15) field is a byte indexing an entry
in the MSI-X Table Structure and MSI-X PBA Structure.
2. In non MSI-X mode these registers define the allocation of the Rx and Tx queues interrupt causes
to one of the RxTxQ bits in the EICR. Each INT_Alloc[i] (i=0…15) field is a byte indexing the
appropriate RxTxQ bit as defined in Table 8-47.
Entries are mapped as follows:
a.
Queues RX0, TX0, RX1, TX1 are mapped in IVAR[0] Register.
b.
Queues RX2, TX2, RX3, TX3 are mapped in IVAR[1] Register.
c.
Queues RX4, TX4, RX5, TX5 are mapped in IVAR[2] Register.
d.
Queues RX6, TX6, RX7, TX7 in are mapped IVAR[3] Register.
Field
INT_Alloc[0]
Bit(s)
Initial Value
3:0
0x0
Description
Defines the MSI-X vector assigned to the interrupt cause associated with this entry,
as defined in Table 8-48. Valid values are 0 to 9 for MSI-X mode and 0 to 7 in non
MSI-X mode.
Reserved
6:4
0x0
Reserved
INT_Alloc_val[0]
7
0b
Valid bit for INT_Alloc[0]
INT_Alloc[1]
11:8
0x0
Defines the MSI-X vector assigned to the interrupt cause associated with this entry,
as defined in Table 8-48. Valid values are 0 to 9 for MSI-X mode and 0 to 7 in non
MSI-X mode.
Reserved
14:12
0x0
Reserved
INT_Alloc_val[1]
15
0b
Valid bit for INT_Alloc[1]
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Interrupt Vector Allocation Registers - MISC IVAR_MISC (0x1740; RW) — Intel® 82580EB/82580DB
GbE Controller
Field
Bit(s)
Initial Value
Description
INT_Alloc[2]
19:16
0x0
Defines the MSI-X vector assigned to the interrupt cause associated with this entry,
as defined in Table 8-48. Valid values are 0 to 9 for MSI-X mode and 0 to 7 in non
MSI-X mode.
Reserved
22:20
00b
Reserved
INT_Alloc_val[2]
23
0b
Valid bit for INT_Alloc[2]
INT_Alloc[3]
27:24
0x0
Defines the MSI-X vector assigned to the interrupt cause associated with this entry,
as defined in Table 8-48. Valid values are 0 to 9 for MSI-X mode and 0 to 7 in non
MSI-X mode.
Reserved
30:28
00b
Reserved
INT_Alloc_val[3]
31
0b
Valid bit for INT_Alloc[3]
Note:
If invalid values are written to the INT_Alloc fields the result is unexpected.
DW
0
31
24
23
INT_ALLOC[3]
16
INT_ALLOC[2]
1
2
15
8
7
INT_ALLOC[1]
INT_ALLOC[0]
…
…
INT_ALLOC[13]
INT_ALLOC[12]
0
...
3
INT_ALLOC[15]
7.8.16
INT_ALLOC[14]
Interrupt Vector Allocation Registers MISC IVAR_MISC (0x1740; RW)
This register is used only in MSI-X mode. This register defines the allocation of the Other Cause and
TCP Timer interrupts to one of the MSI-X vectors.
Field
INT_Alloc[16]
Bit(s)
3:0
Initial Value
0x0
Description
Defines the MSI-X vector assigned to the TCP timer interrupt
cause. Valid values are 0 to 9.
Reserved
6:4
00b
Reserved
INT_Alloc_val[16]
7
0b
Valid bit for INT_Alloc[16]
INT_Alloc[17]
11:8
0x0
Defines the MSI-X vector assigned to the “Other Cause”
interrupt. Valid values are 0 to 9.
Reserved
14:12
00b
Reserved
INT_Alloc_val[17]
15
0b
Valid bit for INT_Alloc[17]
Reserved
31:16
0x0
Reserved
7.8.17
Revision: 2.50
October 2011
General Purpose Interrupt Enable - GPIE (0x1514; RW)
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Intel® 82580EB/82580DB GbE Controller — MSI-X Table Register Descriptions
7.9
MSI-X Table Register Descriptions
Field
Bit(s)
Initial Value
Description
NSICR
0
0b
Non Selective Interrupt clear on read: When set, every read of ICR clears
it. When this bit is cleared, an ICR read causes it to be cleared only if an
actual interrupt was asserted or if no bit is set in the IMS register.
Reserved
3:1
0x0
Reserved.
Multiple MSIX
4
0b
0 = on-MSI mode, or MSI-X with single vector, IVAR maps Rx/Tx causes,
to 8 EICR bits, but MSIX[0] is asserted for all.
1 = MSIX mode, IVAR maps Rx/Tx causes, TCP Timer and “Other Cause”
interrupts to 10 MSI-x vectors reflected in 10 EICR bits.
Note:
Reserved
6:5
0x0
When set, the EICR register is not cleared on read.
Reserved
Write 0, ignore on read.
LL Interval
11:7
0x0
Low latency credits increment rate. The interval is specified in 4 s
increments. A value of 0x0 disables moderation of LLI for all interrupt
vectors.
Reserved
29:12
0x0
Reserved
EIAME
30
0b
Extended Interrupt Auto Mask enable: When set (usually in MSI-X mode);
upon firing of an MSI-X message, bits set in EIAM associated with this
message are cleared. Otherwise, EIAM is used only upon read or write of
EICR/EICS registers.
PBA_support
31
0b
PBA Support: When set, setting one of the extended interrupts masks via
EIMS causes the PBA bit of the associated MSI-X vector to be cleared.
Otherwise, the 82580EB/DB behaves in a way that supports legacy INT-x
interrupts.
Note: Should be cleared when working in INT-x or MSI mode and set in
MSI-X mode.
These registers are used to configure the MSI-X mechanism. The message address and message upper
address registers sets the address for each of the vectors. The message register sets the data sent to
the relevant address. The vector control registers are used to enable specific vectors.
The pending bit array register indicates which vectors have pending interrupts. The structure is listed in
Table 7-22.
Table 7-22.
MSI-X Table Structure
DWORD3
MSIXTVCTRL
DWORD2
MSIXTMSG
DWORD1
MSIXTUADD
DWORD0
MSIXTADD
Entry
Number
BAR 3 - Offset
Vector Control
Msg Data
Msg Upper Addr
Msg Addr
Entry 0
Base (0x0000)
Vector Control
Msg Data
Msg Upper Addr
Msg Addr
Entry 1
Base + 1*16
Base + 2*16
Vector Control
Msg Data
Msg Upper Addr
Msg Addr
Entry 2
…
…
…
…
…
Vector Control
Msg Data
Msg Upper Addr
Msg Addr
Entry (N-1)
Note:
Base + (N-1) *16
N = 10.
Table 7-23.
MSI-X PBA Structure
MSIXPBA[63:0]
QWORD
Number
BAR 3 - Offset
Pending Bits 0 through 63
QWORD0
Base (0x2000)
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MSI–X Table Entry Lower Address - MSIXTADD (BAR3: 0x0000 + 0x10*n [n=0...9]; R/W) — Intel®
82580EB/82580DB GbE Controller
Table 7-23.
MSI-X PBA Structure
Pending Bits 64 through 127
QWORD1
Base+1*8
…
…
…
Pending Bits ((N-1) div 64)*64 through N-1
QWORD((N-1) div 64)
BASE + ((N-1) div 64)*8
Note:
N = 10. As a result, only QWORD0 is implemented.
7.9.1
MSI–X Table Entry Lower Address MSIXTADD (BAR3: 0x0000 + 0x10*n [n=0...9]; R/W)
Field
Bit(s)
Initial Value
Description
Message
Address LSB
(RO)
1:0
0x0
For proper DWORD alignment, software must always write 0b’s to these
two bits. Otherwise, the result is undefined.
Message
Address
31:2
0x0
System-Specific Message Lower Address
7.9.2
For MSI-X messages, the contents of this field from an MSI-X table entry
specifies the lower portion of the DWORD-aligned address for the memory
write transaction.
MSI–X Table Entry Upper Address MSIXTUADD (BAR3: 0x0004 + 0x10*n [n=0...9]; R/W)
Field
Message
Address
7.9.3
Bit(s)
31:0
0x0
Description
System-Specific Message Upper Address
MSI–X Table Entry Message MSIXTMSG (BAR3: 0x0008 + 0x10*n [n=0...9]; R/W)
Field
Message
Data
Initial Value
Bit(s)
31:0
Initial Value
0x0
Description
System-Specific Message Data
For MSI-X messages, the contents of this field from an MSI-X table entry
specifies the data written during the memory write transaction.
In contrast to message data used for MSI messages, the low-order
message data bits in MSI-X messages are not modified by the function.
Revision: 2.50
October 2011
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Intel® 82580EB/82580DB GbE Controller — MSI–X Table Entry Vector Control - MSIXTVCTRL (BAR3:
0x000C + 0x10*n [n=0...9]; R/W)
7.9.4
MSI–X Table Entry Vector Control MSIXTVCTRL (BAR3: 0x000C + 0x10*n [n=0...9]; R/W)
Field
Bit(s)
Initial Value
Description
Mask
0
1b
When this bit is set, the function is prohibited from sending a message
using this MSI-X table entry. However, any other MSI-X table entries
programmed with the same vector are still capable of sending an equivalent
message unless they are also masked.
Reserved
31:1
0x0
Reserved
7.9.5
MSIXPBA Bit Description –
MSIXPBA (BAR3: 0x2000; RO)
Field
Bit(s)
Initial Value
Pending Bits
9:0
0x0
Reserved
31:10
0x0
Description
For each pending bit that is set, the function has a pending message for
the associated MSI-X Table entry.
Pending bits that have no associated MSI-X table entry are reserved.
7.9.6
MSI-X PBA Clear – PBACL (0x5B68; R/W1C)
Field
PENBITCLR
Reserved
Bit(s)
9:0
Initial Value
0x0
Description
MSI-X Pending bits Clear
Writing a 1b to any bit clears the corresponding MSIXPBA bit; writing a 0b
has no effect.
Note: Bits are set for a single PCIe clock cycle and than cleared.
Reserved
31:10
0x0
Reserved
7.10
Receive Register Descriptions
7.10.1
Receive Control Register - RCTL (0x0100; R/W)
This register controls all the 82580EB/DB receiver functions.
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Receive Control Register - RCTL (0x0100; R/W) — Intel® 82580EB/82580DB GbE Controller
Field
Reserved
Bit(s)
0
Initial Value
0b
Description
Reserved
Write to 0b for future compatibility.
RXEN
1
0b
Receiver Enable
The receiver is enabled when this bit is set to 1b. Writing this bit to 0b stops reception
after receipt of any in progress packet. All subsequent packets are then immediately
dropped until this bit is set to 1b.
SBP
2
0b
Store Bad Packets
0b = do not store.
1b = store bad packets.
This bit controls the MAC receive behavior. A packet is required to pass the address
(or normal) filtering before the SBP bit becomes effective. If SBP = 0b, then all
packets with layer 1 or 2 errors are rejected. The appropriate statistic would be
incremented. If SBP = 1b, then these packets are received (and transferred to host
memory). The receive descriptor error field (RDESC.ERRORS) should have the
corresponding bit(s) set to signal the software device driver that the packet is erred.
In some operating systems the software device driver passes this information to the
protocol stack. In either case, if a packet only has layer 3+ errors, such as IP or TCP
checksum errors, and passes other filters, the packet is always received (layer 3+
errors are not used as a packet filter).
Note: symbol errors before the SFD are ignored. Any packet must have a valid SFD
(RX_DV with no RX_ER in 10/100/1000BASE-T mode) in order to be recognized by
the 82580EB/DB (even bad packets). Also, erred packets are not routed to the MNG
even if this bit is set.
UPE
3
0b
Unicast Promiscuous Enabled
0b = Disabled.
1b = Enabled.
MPE
4
0b
Multicast Promiscuous Enabled
0b = Disabled.
1b = Enabled.
LPE
5
0b
Long Packet Reception Enable
0b = Disabled.
1b = Enabled.
LPE controls whether long packet reception is permitted. If LPE is 0b Hardware
discards long packets over 1518, 1522 or 1526 bytes depending on the
CTRL_EXT.EXT_VLAN bit and the detection of a VLAN tag in the packet. If LPE is 1b,
the maximum packet size that the 82580EB/DB can receive is defined in the
RLPML.RLPML register.
LBM
7:6
00b
Loopback mode.
Controls the loopback mode of the 82580EB/DB.
00b = Normal operation (or PHY loopback in 10/100/1000BASE-T mode).
01b = MAC loopback (test mode).
10b = Undefined.
11b = Loopback via internal SerDes (SerDes/SGMII/KX mode only).
When using the internal PHY, LBM should remain set to 00b and the PHY instead
configured for loopback through the MDIO interface.
Note: PHY devices require programming for loopback operation using MDIO accesses.
Reserved
9:8
00b
Reserved
Reserved
11:10
00b
Reserved
Set to 0b for compatibility.
Revision: 2.50
October 2011
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Intel® 82580EB/82580DB GbE Controller — Receive Control Register - RCTL (0x0100; R/W)
Field
MO
Bit(s)
13:12
Initial Value
00b
Description
Multicast Offset
Determines which bits of the incoming multicast address are used in looking up the bit
vector.
00b = bits [47:36] of received destination multicast address.
01b = bits [46:35] of received destination multicast address.
10b = bits [45:34] of received destination multicast address.
11b = bits [43:32] of received destination multicast address.
Reserved
14
0b
BAM
15
0b
Reserved
Broadcast Accept Mode.
0b = Ignore broadcast (unless it matches through exact or imperfect filters).
1b = Accept broadcast packets.
BSIZE
17:16
00b
Receive Buffer Size
BSIZE controls the size of the receive buffers and permits software to trade-off
descriptor performance versus required storage space. Buffers that are 2048 bytes
require only one descriptor per receive packet maximizing descriptor efficiency.
00b = 2048 Bytes.
01b = 1024 Bytes.
10b = 512 Bytes.
11b = 256 Bytes.
Notes:
1. BSIZE should not be modified when RXEN is set to 1b. Set RXEN =0 when
modifying the buffer size by changing this field.
2. BSIZE value only defines receive buffer size of queues with a
SRRCTL.BSIZEPACKET value of 0.
VFE
18
0b
VLAN Filter Enable
0b = Disabled (filter table does not decide packet acceptance).
1b = Enabled (filter table decides packet acceptance for 802.1Q packets).
Three bits [20:18] control the VLAN filter table. The first determines whether the
table participates in the packet acceptance criteria. The next two are used to decide
whether the CFI bit found in the 802.1Q packet should be used as part of the
acceptance criteria.
CFIEN
19
0b
Canonical Form Indicator Enable
0b = Disabled (CFI bit found in received 802.1Q packet’s tag is not compared to
decide packet acceptance).
1b = Enabled (CFI bit found in received 802.1Q packet’s tag must match RCTL.CFI to
accept 802.1Q type packet.
CFI
20
0b
Canonical Form Indicator bit value
0b = 802.1Q packets with CFI equal to this field are accepted.
1b = 802.1Q packet is discarded.
PSP
21
0b
DPF
22
0b
Pad Small Receive packets.
If this field is set, RCTL.SECRC should be set also.
Discard Pause Frames with Station MAC Address
Controls whether pause frames directly addressed to this station are forwarded to the
host.
0b = incoming pause frames with station MAC address are forwarded to the host.
1b = incoming pause frames with station MAC address are discarded.
Note: Pause frames with other MAC addresses (multicast address) are always
discarded unless the specific address is added to the accepted MAC addresses (either
multicast or unicast).
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Split and Replication Receive Control - SRRCTL (0xC00C + 0x40*n [n=0...7]; R/W) — Intel® 82580EB/
82580DB GbE Controller
Field
PMCF
Bit(s)
23
Initial Value
0b
Description
Pass MAC Control Frames
Filters out unrecognized pause and other control frames.
0b = Filter MAC Control frames.
1b = Pass/forward MAC control frames to the Host that are not XON/XOFF Flow
Control packets.
The PMCF bit controls the DMA function of MAC control frames (other than flow
control). A MAC control frame in this context must be addressed to either the MAC
control frame multicast address or the station address, match the type field, and NOT
match the PAUSE opcode of 0x0001. If PMCF = 1b then frames meeting this criteria
are transferred to host memory.
Reserved
25:24
0b
Reserved
Should be written with 0b to ensure future compatibility.
SECRC
26
0b
Strip Ethernet CRC from incoming packet
Causes the CRC to be stripped from all packets.
0b = Does not strip CRC
1b = Strips CRC.
This bit controls whether the hardware strips the Ethernet CRC from the received
packet. This stripping occurs prior to any checksum calculations. The stripped CRC is
not transferred to host memory and is not included in the length reported in the
descriptor.
Reserved
31:27
0x0
Reserved
Should be written with 0b to ensure future compatibility.
7.10.2
Split and Replication Receive Control SRRCTL (0xC00C + 0x40*n [n=0...7]; R/W)
Field
BSIZEPACKET
Bit(s)
6:0
Initial Value
0x0
Description
Receive Buffer Size for Packet Buffer
The value is in 1 KB resolution. Valid values can be from 1 KB to 127 KB. Default
buffer size is 0 KB. If this field is equal 0x0, then RCTL.BSIZE determines the packet
buffer size.
DMACQ_Dis
7
0b
DMA Coalescing disable
0 - Enable DMA Coalescing on this queue if DMACR.DMAC_EN is set to 1.
1 - Disable DMA Coalescing on this queue. When packet is destined to this queue and
device is in coalescing mode, Coalescing mode is exited immediately and PCIe moves
to L0 link power management state.
BSIZEHEADER
11:8
0x4
Receive Buffer Size for Header Buffer
The value is in 64 bytes resolution. Valid value can be from 64 bytes to 960 bytes.
Default buffer size is 256 bytes. This field must be greater than 0 if the value of
DESCTYPE is greater or equal to 2.
Note: When SRRCTL.Timestamp is set to 1 and the value of DESCTYPE is greater or
equal to 2, BSIZEHEADER size should be equal or greater than 2 (128 bytes).
Reserved
13:12
00b
Reserved
Must be set to 00b.
ReservedReser 19:14
ved
Revision: 2.50
October 2011
0x0
Reserved.
Write 0 ignore on read.
Intel® 82580EB/82580DB Gigabit Ethernet Controller
Datasheet
329
Intel® 82580EB/82580DB GbE Controller — Packet Split Receive Type - PSRTYPE (0x5480 + 4*n
[n=0...7]; R/W)
Field
RDMTS
Bit(s)
24:20
Initial Value
0x0
Description
Receive Descriptor Minimum Threshold Size
A low latency interrupt (LLI) associated with this queue is asserted whenever the
number of free descriptors becomes equal to RDMTS multiplied by 16.
DESCTYPE
27:25
000b
Defines the descriptor in Rx
000b = Legacy.
001b = Advanced descriptor one buffer.
010b = Advanced descriptor header splitting.
011b = Advanced descriptor header replication - replicate always.
100b = Advanced descriptor header replication large packet only (larger than header
buffer size).
101b = Reserved.
111b = Reserved.
ReservedReser 29:28
ved
0x0
TimestampRes 30
erved
0b
Reserved.
Write 0 ignore on read.
Timestamp Received packet
0 - Do not place timestamp at beginning of receive buffer.
1- Place timestamp at beginning of receive buffer. Timestamp is placed only in
buffers of received packets that meet the criteria defined in the TSYNCRXCTL.Type
field, 2-tuple filters or ETQF registers.
When set a 40 bit time stamp generated from the value in SYSTIMH and SYSTIML
registers is placed in the receive buffer before the MAC header of the packets defined
in the TSYNCRXCTL.Type field.
Drop_En
31
0b/1b
Drop Enabled
If set, packets received to the queue when no descriptors are available to store them
are dropped. The packet is dropped only if there are not enough free descriptors in
the host descriptor ring to store the packet. If there are enough descriptors in the
host, but they are not yet fetched by the 82580EB/DB, then the packet is not
dropped and there are no release of packets until the descriptors are fetched.
Default is 0b for queue 0 and 1b for the other queues.
7.10.3
Packet Split Receive Type PSRTYPE (0x5480 + 4*n [n=0...7]; R/W)
This register enables or disables each type of header that needs to be split. Each register controls the
behavior of 1 queue.
• Packet Split Receive Type Register (queue 0) - PSRTYPE0 (0x5480)
• Packet Split Receive Type Register (queue 1) - PSRTYPE1 (0x5484)
• Packet Split Receive Type Register (queue 2) - PSRTYPE2 (0x5488)
• Packet Split Receive Type Register (queue 3) - PSRTYPE3 (0x548C)
• Packet Split Receive Type Register (queue 4) - PSRTYPE3 (0x5490)
• Packet Split Receive Type Register (queue 5) - PSRTYPE3 (0x5494)
• Packet Split Receive Type Register (queue 6) - PSRTYPE3 (0x5498)
• Packet Split Receive Type Register (queue 7) - PSRTYPE3 (0x549C)
Intel® 82580EB/82580DB Gigabit Ethernet Controller
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Revision: 2.50
October 2011
Replicated Packet Split Receive Type - RPLPSRTYPE (0x54C0; R/W) — Intel® 82580EB/82580DB GbE
Controller
Field
Bit(s)
Initial Value
Description
Reserved
0
0b
Reserved
PSR_type1
1
1b
Header includes MAC, (VLAN/SNAP) IPv4 only
PSR_type2
2
1b
Header includes MAC, (VLAN/SNAP) IPv4, TCP only
PSR_type3
3
1b
Header includes MAC, (VLAN/SNAP) IPv4, UDP only
PSR_type4
4
1b
Header includes MAC, (VLAN/SNAP) IPv4, IPv6 only
PSR_type5
5
1b
Header includes MAC, (VLAN/SNAP) IPv4, IPv6, TCP only
PSR_type6
6
1b
Header includes MAC, (VLAN/SNAP) IPv4, IPv6, UDP only
PSR_type7
7
1b
Header includes MAC, (VLAN/SNAP) IPv6 only
PSR_type8
8
1b
Header includes MAC, (VLAN/SNAP) IPv6, TCP only
PSR_type9
9
1b
Header includes MAC, (VLAN/SNAP) IPv6, UDP only
Reserved
10
1b
Reserved
PSR_type11
11
1b
Header includes MAC, (VLAN/SNAP) IPv4, TCP, NFS only
PSR_type12
12
1b
Header includes MAC, (VLAN/SNAP) IPv4, UDP, NFS only
Reserved
13
1b
Reserved
PSR_type14
14
1b
Header includes MAC, (VLAN/SNAP) IPv4, IPv6, TCP, NFS only
PSR_type15
15
1b
Header includes MAC, (VLAN/SNAP) IPv4, IPv6, UDP, NFS only
Reserved
16
1b
Reserved
PSR_type17
17
1b
Header includes MAC, (VLAN/SNAP) IPv6, TCP, NFS only
PSR_type18
18
1b
Header includes MAC, (VLAN/SNAP) IPv6, UDP, NFS only
Reserved
31:19
0x0
Reserved
7.10.4
Replicated Packet Split Receive Type RPLPSRTYPE (0x54C0; R/W)
This register enables or disables each type of header that needs to be split. This register controls the
behavior of replicated packets.
Field
Bit(s)
Initial Value
Description
Reserved
0
0b
Reserved
PSR_type1
1
1b
Header includes MAC, (VLAN/SNAP) IPv4 only
PSR_type2
2
1b
Header includes MAC, (VLAN/SNAP) IPv4, TCP only
PSR_type3
3
1b
Header includes MAC, (VLAN/SNAP) IPv4, UDP only
PSR_type4
4
1b
Header includes MAC, (VLAN/SNAP) IPv4, IPv6 only
PSR_type5
5
1b
Header includes MAC, (VLAN/SNAP) IPv4, IPv6, TCP only
PSR_type6
6
1b
Header includes MAC, (VLAN/SNAP) IPv4, IPv6, UDP only
PSR_type7
7
1b
Header includes MAC, (VLAN/SNAP) IPv6 only
PSR_type8
8
1b
Header includes MAC, (VLAN/SNAP) IPv6, TCP only
PSR_type9
9
1b
Header includes MAC, (VLAN/SNAP) IPv6, UDP only
Reserved
10
1b
Reserved
PSR_type11
11
1b
Header includes MAC, (VLAN/SNAP) IPv4, TCP, NFS only
PSR_type12
12
1b
Header includes MAC, (VLAN/SNAP) IPv4, UDP, NFS only
Reserved
13
1b
Reserved
PSR_type14
14
1b
Header includes MAC, (VLAN/SNAP) IPv4, IPv6, TCP, NFS only
PSR_type15
15
1b
Header includes MAC, (VLAN/SNAP) IPv4, IPv6, UDP, NFS only
Revision: 2.50
October 2011
Intel® 82580EB/82580DB Gigabit Ethernet Controller
Datasheet
331
Intel® 82580EB/82580DB GbE Controller — Receive Descriptor Base Address Low - RDBAL (0xC000 +
0x40*n [n=0...7]; R/W)
Field
Bit(s)
Initial Value
Description
Reserved
16
1b
Reserved
PSR_type17
17
1b
Header includes MAC, (VLAN/SNAP) IPv6, TCP, NFS only
PSR_type18
18
1b
Header includes MAC, (VLAN/SNAP) IPv6, UDP, NFS only
Reserved
31:19
0x0
Reserved
7.10.5
Receive Descriptor Base Address Low RDBAL (0xC000 + 0x40*n [n=0...7]; R/W)
This register contains the lower bits of the 64-bit descriptor base address. The lower four bits are
always ignored. The Receive Descriptor Base Address must point to a 128 byte-aligned block of data.
Note:
In order to keep compatibility with the 82575, for queues 0-3, these registers are aliased to
addresses 0x2800, 0x2900, 0x2A00 & 0x2B00 respectively.
Field1
Lower_0
Bit(s)
6:0
Initial Value
0x0
Description
Ignored on writes.
Returns 0x0 on reads.
RDBAL
31:7
X
Receive Descriptor Base Address Low
1. Software should program RDBAL[n] register only when queue is disabled (RXDCTL[n].Enable = 0).
7.10.6
Receive Descriptor Base Address High RDBAH (0xC004 + 0x40*n [n=0...7]; R/W)
This register contains the upper 32 bits of the 64-bit descriptor base address.
Field1
RDBAH
Bit(s)
31:0
Initial Value
X
Description
Receive Descriptor Base Address [63:32]
1. Software should program RDBAH[n] register only when queue is disabled (RXDCTL[n].Enable = 0).
Note:
7.10.7
In order to keep compatibility with the 82575, for queues 0-3, these registers are aliased to
addresses 0x2804, 0x2904, 0x2A04 & 0x2B04 respectively.
Receive Descriptor Ring Length RDLEN (0xC008 + 0x40*n [n=0...7]; R/W)
This register sets the number of bytes allocated for descriptors in the circular descriptor buffer. It must
be 128-byte aligned.
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Revision: 2.50
October 2011
Receive Descriptor Head - RDH (0xC010 + 0x40*n [n=0...7]; RO) — Intel® 82580EB/82580DB GbE
Controller
Field1
0
Bit(s)
6:0
Initial Value
0x0
Description
Ignore on writes.
Bits 6:0 must be set to zero.
Bits 4:0 always read as zero.
LEN
19:7
0x0
Descriptor Ring Length (number of 8 descriptor sets).
Note: maximum allowed value in RDLEN field 19:0 is 0x80000 (32K
descriptors).
Reserved
31:20
0x0
Reserved
Reads as 0b.
Should be written to 0b for future compatibility.
1. Software should program RDLEN[n] register only when queue is disabled (RXDCTL[n].Enable = 0).
Note:
7.10.8
In order to keep compatibility with the 82575, for queues 0-3, these registers are aliased to
addresses 0x2808, 0x2908, 0x2A08 & 0x2B08 respectively.
Receive Descriptor Head RDH (0xC010 + 0x40*n [n=0...7]; RO)
The value in this register might point to descriptors that are still not in host memory. As a result, the
host cannot rely on this value in order to determine which descriptor to process.
Field
Bit(s)
Initial Value
RDH
15:0
0x0
Reserved
31:16
0x0
Description
Receive Descriptor Head
Reserved
Should be written to 0b.
Note:
7.10.9
In order to keep compatibility with the 82575, for queues 0-3, these registers are aliased to
addresses 0x2810, 0x2910, 0x2A10 & 0x2B10 respectively.
Receive Descriptor Tail RDT (0xC018 + 0x40*n [n=0...7]; R/W)
This register contains the tail pointers for the receive descriptor buffer. The register points to a 16-byte
datum. Software writes the tail register to add receive descriptors to the hardware free list for the ring.
Note:
Writing the RDT register while the corresponding queue is disabled is ignored by the
82580EB/DB.
In order to keep compatibility with the 82575, for queues 0-3, these registers are aliased to
addresses 0x2818, 0x2918, 0x2A18& 0x2B18 respectively.
Field
Bit(s)
Initial Value
RDT
15:0
0x0
Reserved
31:16
0x0
Description
Receive Descriptor Tail
Reserved.
Ignore on read, write 0 for future compatibility.
Revision: 2.50
October 2011
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Datasheet
333
Intel® 82580EB/82580DB GbE Controller — Receive Descriptor Control - RXDCTL (0xC028 + 0x40*n
[n=0...7]; R/W)
7.10.10
Receive Descriptor Control RXDCTL (0xC028 + 0x40*n [n=0...7]; R/W)
This register controls the fetching and write-back of receive descriptors. The three threshold values are
used to determine when descriptors are read from and written to host memory. The values are in units
of descriptors (each descriptor is 16 bytes).
Field
PTHRESH
Bit(s)
4:0
Initial Value
0xC
Description
Prefetch Threshold
PTHRESH is used to control when a prefetch of descriptors is considered.
This threshold refers to the number of valid, unprocessed receive
descriptors the 82580EB/DB has in its on-chip buffer. If this number drops
below PTHRESH, the algorithm considers pre-fetching descriptors from
host memory. This fetch does not happen unless there are at least
HTHRESH valid descriptors in host memory to fetch.
Note: HTHRESH should be given a non zero value each time PTHRESH is
used.
Possible values for this field are 0 to 16.
Reserved
7:5
0x0
Reserved
HTHRESH
12:8
0xA
Host Threshold
Field defines when receive descriptor prefetch is performed. Each time
enough valid descriptors, as defined in the HTHRESH field, are available in
host memory a prefetch is performed.
Possible values for this field are 0 to 16.
Reserved
15:13
0x0
WTHRESH
20:16
0x1
Reserved
Write-Back Threshold
WTHRESH controls the write-back of processed receive descriptors. This
threshold refers to the number of receive descriptors in the on-chip buffer
that are ready to be written back to host memory. In the absence of
external events (explicit flushes), the write-back occurs only after at least
WTHRESH descriptors are available for write-back.
Possible values for this field are 0 to 15.
Note: Since the default value for write-back threshold is 1b, the descriptors
are normally written back as soon as one cache line is available. WTHRESH
must contain a non-zero value to take advantage of the write-back
bursting capabilities of the 82580EB/DB.
Note: It’s recommended not to place a value above 0xC in the WTHRESH
field.
Reserved
24:21
0x0
Intel® 82580EB/82580DB Gigabit Ethernet Controller
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Reserved
Revision: 2.50
October 2011
Receive Queue Drop Packet Count - RQDPC (0xC030 + 0x40*n [n=0...7]; RC/W) — Intel® 82580EB/
82580DB GbE Controller
Field
ENABLE
Bit(s)
Initial Value
25
0b
Description
Receive Queue Enable
When set, the Enable bit enables the operation of the specific receive
queue.
1b =Enables queue.
0b =Disables queue.
Setting this bit initializes Head and Tail registers (RDH[n] and RDT[n]) of
the specific queue. Until then, the state of the queue is kept and can be
used for debug purposes.
When disabling a queue, this bit is cleared only after all activity in the
queue has stopped.
Note: When receive queue is enabled and descriptors exist, descriptors and
are fetched immediately. Actual receive activity on port starts only if the
RCTL.RXEN bit is set.
SWFLUSH
(WC)
26
0b
Receive Software Flush
Enables software to trigger receive descriptor write-back flushing,
independently of other conditions.
This bit is cleared by hardware after write-back flush is triggered (may take
a number of cycles).
Reserved
Note:
7.10.11
Field
RQDPC
31:27
0x0
Reserved
In order to keep compatibility with the 82575, for queues 0-3, these registers are aliased to
addresses 0x2828, 0x2928, 0x2A28 & 0x2B28 respectively.
Receive Queue Drop Packet Count RQDPC (0xC030 + 0x40*n [n=0...7]; RC/W)
Bit(s)
31:0
Initial Value
0x0
Description
Receive Queue drop packet count - counts the number of packets dropped by a queue
due to lack of descriptors available.
Note: Counter does not wrap around when reaching a value of 0xFFFFFFFF.
Note:
In order to keep compatibility with the 82575, for queues 0-3, these registers are aliased to
addresses 0x2830, 0x2930, 0x2A30 & 0x2B30 respectively.
Packets dropped due to the queue being disabled may not be counted by this register.
7.10.12
Receive Checksum Control - RXCSUM (0x5000; R/W)
The Receive Checksum Control register controls the receive checksum off loading features of the
82580EB/DB. The 82580EB/DB supports the off loading of three receive checksum calculations: the
Packet Checksum, the IP Header Checksum, and the TCP/UDP Checksum.
Note:
Revision: 2.50
October 2011
This register should only be initialized (written) when the receiver is not enabled (only write
this register when RCTL.RXEN = 0b)
Intel® 82580EB/82580DB Gigabit Ethernet Controller
Datasheet
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Intel® 82580EB/82580DB GbE Controller — Receive Checksum Control - RXCSUM (0x5000; R/W)
Field
PCSS
Bit(s)
7:0
Initial Value
0x0
Description
Packet Checksum Start
Controls the packet checksum calculation. The packet checksum shares the same
location as the RSS field and is reported in the receive descriptor when the
RXCSUM.PCSD bit is cleared.
If the RXCSUM.IPPCSE is set, the Packet checksum is aimed to accelerate checksum
calculation of fragmented UDP packets. Please refer to section Section 8.1.11.2 for
detailed explanation. If RXCSUM.IPPCSE is cleared (the default value), the checksum
calculation that is reported in the Rx Packet checksum field is the unadjusted 16-bit
ones complement of the packet.
The packet checksum starts from the byte indicated by RXCSUM.PCSS (0b
corresponds to the first byte of the packet), after VLAN stripping if enabled by the
CTRL.VME. For example, for an Ethernet II frame encapsulated as an 802.3ac VLAN
packet and with RXCSUM.PCSS set to 14, the packet checksum would include the
entire encapsulated frame, excluding the 14-byte Ethernet header (DA, SA, Type/
Length) and the 4-byte VLAN tag. The packet checksum does not include the Ethernet
CRC if the RCTL.SECRC bit is set. Software must make the required offsetting
computation (to back out the bytes that should not have been included and to include
the pseudo-header) prior to comparing the packet checksum against the L4 checksum
stored in the packet checksum. The partial checksum in the descriptor is aimed to
accelerate checksum calculation of fragmented UDP packets.
Note: The PCSS value should not exceed a pointer to the IP header start. If exceeded,
the IP header checksum or TCP/UDP checksum is not calculated correctly.
IPOFLD
8
1b
IP Checksum Off-load Enable
RXCSUM.IPOFLD is used to enable the IP Checksum off-loading feature. If
RXCSUM.IPOFLD is set to 1b, the 82580EB/DB calculates the IP checksum and
indicates a pass/fail indication to software via the IP Checksum Error bit (IPE) in the
Error field of the receive descriptor. Similarly, if RXCSUM.TUOFLD is set to 1b, the
82580EB/DB calculates the TCP or UDP checksum and indicates a pass/fail indication
to software via the TCP/UDP Checksum Error bit (RDESC.L4E).
This applies to checksum off loading only. Supported frame types:
Ethernet II
Ethernet SNAP
TUOFLD
9
1b
TCP/UDP Checksum Off-load Enable
Reserved
10
0b
Reserved
CRCOFL
11
0b
CRC32 Offload Enable
Enables the SCTP CRC32 checksum off-loading feature. If RXCSUM.CRCOFL is set to
1b, the 82580EB/DB calculates the CRC32 checksum and indicates a pass/fail
indication to software via the CRC32 Checksum Valid bit (RDESC.L4I) in the Extended
Status field of the receive descriptor.
In non I/OAT, this bit is read only as 0b.
IPPCSE
12
0b
IP Payload Checksum Enable
See PCSS description.
PCSD
13
0b
Packet Checksum Disable
The packet checksum and IP identification fields are mutually exclusive with the RSS
hash. Only one of the two options is reported in the Rx descriptor.
RXCSUM.PCSD Legacy Rx Descriptor (SRRCTL.DESCTYPE = 000b):
0b (checksum enable) - Packet checksum is reported in the Rx descriptor.
1b (checksum disable) - Not supported.
RXCSUM.PCSD Extended or Header Split Rx Descriptor (SRRCTL.DESCTYPE not equal
000b):
0b (checksum enable) - checksum and IP identification are reported in the Rx
descriptor.
1b (checksum disable) - RSS Hash value is reported in the Rx descriptor.
Reserved
31:14
0x0
Reserved
Intel® 82580EB/82580DB Gigabit Ethernet Controller
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Revision: 2.50
October 2011
Receive Long Packet Maximum Length - RLPML (0x5004; R/W) — Intel® 82580EB/82580DB GbE
Controller
7.10.13
Field
Receive Long Packet Maximum Length RLPML (0x5004; R/W)
Bit(s)
Initial Value
Description
RLPML
13:0
0x2600
Maximum allowed long packet length. This length is the global length of the packet
including all the potential headers of suffixes in the packet.
Reserved
31:14
0x0
Reserved
7.10.14
Receive Filter Control Register - RFCTL (0x5008; R/W)
Field
Bit(s)
Initial Value
Reserved
5:0
1b
NFSW_DIS
6
0b
Description
Reserved
NFS Write Disable
Disables filtering of NFS write request headers.
NFSR_DIS
7
0b
NFS Read Disable
Disables filtering of NFS read reply headers.
NFS_VER
9:8
00b
NFS Version
00b = NFS version 2.
01b = NFS version 3.
10b = NFS version 4.
11b = Reserved for future use.
Reserved
10
0b
IPv6XSUM_DIS
11
0b
Reserved
Write 0, ignore on read.
IPv6 XSUM Disable
Disables XSUM on IPv6 packets.
Reserved
12
0b
Reserved
13
0b
Reserved
Write 0, ignore on read.
Reserved.
Write 0, ignore on read.
IPFRSP_DIS
14
0b
Reserved
15
0b
Reserved
17:16
00b
IP Fragment Split Disable
When this bit is set, the header of IP fragmented packets are not set.
Reserved
Reserved
Must be set to 00b.
LEF
18
0b
Forward Length Error Packet
0b = packet with length error are dropped.
1b = packets with length error are forwarded to the host.
Revision: 2.50
October 2011
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Intel® 82580EB/82580DB GbE Controller — Multicast Table Array - MTA (0x5200 + 4*n [n=0...127];
R/W)
Field
Bit(s)
SYNQFP
19
Initial Value
0b
Description
Defines the priority between SYNQF & tuple filter
0b = filter priority
1b = SYN filter priority.
Reserved
31:20
0x0
Reserved
Write 0 ignore on read.
Reserved
31:20
0x08
Reserved
Should be written with 0b to ensure future capability.
7.10.15
Multicast Table Array MTA (0x5200 + 4*n [n=0...127]; R/W)
There is one register per 32 bits of the Multicast Address Table for a total of 128 registers. Software
must mask to the desired bit on reads and supply a 32-bit word on writes. The first bit of the address
used to access the table is set according to the RCTL.MO field.
Note:
All accesses to this table must be 32 bit.
Field
Bit Vector
Bit(s)
31:0
Initial Value
X
Description
Word wide bit vector specifying 32 bits in the multicast address filter table.
Figure 7-1 shows the multicast lookup algorithm. The destination address shown represents the
internally stored ordering of the received DA. Note that bit 0 indicated in this diagram is the first on the
wire.
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Revision: 2.50
October 2011
Receive Address Low - RAL (0x5400 + 8*n [n=0...15]; 0x54E0 + 8*n [n=0...7]; R/W) — Intel®
82580EB/82580DB GbE Controller
Figure 7-1.
Multicast Table Array
7.10.16
Receive Address Low - RAL (0x5400 + 8*n [n=0...15];
0x54E0 + 8*n [n=0...7]; R/W)
While “n” is the exact unicast/multicast address entry and it is equal to 0,1,...15.
These registers contain the lower bits of the 48 bit Ethernet address. All 32 bits are valid.
These registers are reset by a software reset or platform reset. If an EEPROM is present, the first
register (RAL0) is loaded from the EEPROM after a software or platform reset.
Note:
The RAL field should be written in network order.
Field
RAL
Bit(s)
31:0
Initial Value
X
Description
Receive address low
Contains the lower 32-bit of the 48-bit Ethernet address.
Revision: 2.50
October 2011
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Datasheet
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Intel® 82580EB/82580DB GbE Controller — Receive Address High - RAH (0x5404 + 8*n [n=0...15];
0x54E4 + 8*n [n=0...7]; R/W)
7.10.17
Receive Address High - RAH (0x5404 + 8*n [n=0...15];
0x54E4 + 8*n [n=0...7]; R/W)
These registers contain the upper bits of the 48 bit Ethernet address. The complete address is [RAH,
RAL]. The AV bit determines whether this address is compared against the incoming packet and is
cleared by a master reset (PCIe reset or Software reset).
ASEL enables the 82580EB/DB to perform special filtering on receive packets.
After reset, if an EEPROM is present, the first register (Receive Address Register 0) is loaded from the
IA field in the EEPROM with its Address Select field set to 00b and its Address Valid field set to 1b. If no
EEPROM is present, the Address Valid field is set to 0b and the Address Valid field for all of the other
registers is set to 0b.
Note:
The RAH field should be written in network order.
The first receive address register (RAH0) is also used for exact match pause frame checking
(DA matches the first register). As a result, RAH0 should always be used to store the
individual Ethernet MAC address of the 82580EB/DB.
Field
RAH
Bit(s)
15:0
Initial Value
X
Description
Receive address High
Contains the upper 16 bits of the 48-bit Ethernet address.
ASEL
17:16
X
Address Select
Selects how the address is to be used in the address filtering.
00b = Destination address (required for normal mode)
01b = Source address. This mode should not be used in
virtualization mode.
10b = Reserved
11b = Reserved
POOLSEL
25:18
0x0
Pool Select
In virtualization modes (MRQC.Multiple Receive Queues Enable
= 011b) indicates which Pool should get the packets matching
this MAC address. This field is a bit map (bit per VM) where more
than one bit can be set according to the limitations defined in
Section 8.8.2.5. If all the bits are zero, this address is used only
for L2 filtering and is not used as part of the queueing decision.
Reserved
30:26
0x0
Reserved
Write 0 Ignore on reads.
AV
31
Address Valid
Cleared after master reset. If an EEPROM is present, the Address
Valid field of the Receive Address Register 0 is set to 1b after a
software or PCI reset or EEPROM read.
In entries 0-15 this bit is cleared by master reset.
7.10.18
VLAN Filter Table Array - VFTA (0x5600 + 4*n [n=0...127];
R/W)
There is one register per 32 bits of the VLAN Filter Table. The size of the word array depends on the
number of bits implemented in the VLAN Filter Table. Software must mask to the desired bit on reads
and supply a 32-bit word on writes.
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Multiple Receive Queues Command Register - MRQC (0x5818; R/W) — Intel® 82580EB/82580DB GbE
Controller
Note:
All accesses to this table must be 32 bit.
The algorithm for VLAN filtering using the VFTA is identical to that used for the Multicast Table Array.
Refer to Section 7.10.15 for a block diagram of the algorithm. If VLANs are not used, there is no need
to initialize the VFTA.
Field
Bit Vector
Bit(s)
31:0
7.10.19
Field
Multiple
Receive
Queues
Enable
Initial Value
X
Description
Double-word wide bit vector specifying 32 bits in the VLAN Filter table.
Multiple Receive Queues Command Register - MRQC
(0x5818; R/W)
Bit(s)
2:0
Initial Value
0x0
Description
Multiple Receive Queues Enable
Enables support for Multiple Receive Queues and defines the mechanism that controls
queue allocation.
000b = Multiple receive queues as defined by filters (2-tuple filters, L2 Ether-type
filters, SYN filter and Flex Filters).
001b = Reserved.
010b = Multiple receive queues as defined by filters and RSS for 8 queues1.
011b = Multiple receive queues as defined by VMDq based on packet destination MAC
address (RAH.POOLSEL) and Ether-type queuing decision filters.
100b = Reserved
101b = Reserved
110b = Reserved
111b = Reserved.
If VT is not supported, the only allowed values for this field are 000b and 010b.
Writing any other value is ignored.
TheAllowed values for this field are 000b, 010b and 011b. Any other value is ignored.
Revision: 2.50
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Intel® 82580EB/82580DB Gigabit Ethernet Controller
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Intel® 82580EB/82580DB GbE Controller — RSS Random Key Register - RSSRK (0x5C80 + 4*n
[n=0...9]; R/W)
Def_Q
5:3
0x0
Defines the default queue in non VMDq mode according to value of the Multiple
Receive Queues Enable field.
If Multiple Receive Queues Enable =
000b: Def_Q defines the destination of all packets not forwarded by filters.
001b: Def_Q field is ignored.
010b: Def_Q defines the destination of all packets not forwarded by RSS or filters.
011b - Def_Q field is ignored. Queueing decision of all packets not forwarded by MAC
address and Ether-type filters is according to VT_CTL.DEF_PL field.
100-101b: Def_Q field is ignored.
110b: Def_Q field is ignored.
Note: In VMDq mode (Multiple Receive Queues Enable = 011b) the default queue is
set according to the VT_CTL.DEF_PL if packet passes MAC Address filtering of a filter
with RAH.POOLSEL = 0x0 or is a broadcast or multicast packet and does not match
Ether-type queuing decision filters.
Reserved
15:6
0x0
Reserved.
RSS Field
Enable
31:16
0x0
Each bit, when set, enables a specific field selection to be used by the hash function.
Several bits can be set at the same time.
Bit[16] = Enable TcpIPv4 hash function
Bit[17] = Enable IPv4 hash function
Bit[18] = Enable TcpIPv6Ex hash function
Bit[19] = Enable IPv6Ex hash function
Bit[20] = Enable IPv6 hash function
Bit[21] = Enable TCPIPv6 hash function
Bit[22] = Enable UDPIPv4
Bit[23] = Enable UDPIPv6
Bit[24] = Enable UDPIPv6Ext
ReservedBits[31:26] - Reserved Zero
1. Note that the RXCSUM.PCSD bit should be set to enable reception of the RSS hash value in the receive descriptor.
Note:
The MRQC.Multiple Receive Queues Enable field is used to enable/disable RSS hashing and
also to enable multiple receive queues. Disabling this feature is not recommended. Model
usage is to reset the 82580EB/DB after disabling the RSS.
7.10.20
RSS Random Key Register - RSSRK (0x5C80 + 4*n
[n=0...9]; R/W)
Field
Bit(s)
Initial Value
Description
K0
7:0
0x0
Byte n*4 of the RSS random key (n=0,1,...9).
K1
15:8
0x0
Byte n*4+1 of the RSS random key (n=0,1,...9).
K2
23:16
0x0
Byte n*4+2 of the RSS random key (n=0,1,...9).
K3
31:24
0x0
Byte n*4+3 of the RSS random key (n=0,1,...9).
The RSS Random Key Register stores a 40 byte key used by the RSS hash function.
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Redirection Table - RETA (0x5C00 + 4*n [n=0...31]; R/W) — Intel® 82580EB/82580DB GbE Controller
31
24
23
16
15
8
7
0
K[3]
K[2]
K[1]
K[0]
...
...
...
...
K[39]
...
...
K[36]
7.10.21
Redirection Table - RETA (0x5C00 + 4*n [n=0...31]; R/W)
The redirection table is a 128-entry table with each entry being eight bits wide. Only 1 to 3 bits of each
entry are used to store the queue index. The table is configured through the following R/W registers.
Field
Bit(s)
Initial Value
Description
Entry 0
7:0
0x0
Determines the tag value and physical queue for index 4*n+0
(n=0...31).
Entry 1
15:8
0x0
Determines the tag value and physical queue for index 4*n+1
(n=0...31).
Entry 2
23:16
0x0
Determines the tag value and physical queue for index 4*n+2
(n=0...31).
Entry 3
31:24
0x0
Determines the tag value and physical queue for index 4*n+3
(n=0...31).
31
24
23
16
15
8
7
0
Tag 3
Tag 2
Tag 1
Tag 0
...
...
...
...
Tag 127
...
...
...
Each entry (byte) of the redirection table contains the following:
7:3
2:0
Reserved
Queue index
• Bits [7:3] - Reserved
• Bits [2:0] - Queue index for all pools or in regular RSS. In RSS only mode, all bits are used.
The contents of the redirection table are not defined following reset of the Memory Configuration
Registers. System software must initialize the Table prior to enabling multiple receive queues. It can
also update the redirection table during run time. Such updates of the table are not synchronized with
the arrival time of received packets. Therefore, it is not guaranteed that a table update takes effect on
a specific packet boundary.
Note:
Revision: 2.50
October 2011
In case the operating system provides a redirection Table whose size is smaller than 128
bytes, the software usually replicates the operating system-provided redirection table to
span the whole 128 bytes of the hardware's redirection table.
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Intel® 82580EB/82580DB GbE Controller — Filtering Register Descriptions
7.11
Filtering Register Descriptions
7.11.1
Immediate Interrupt RX - IMIR (0x5A80 + 4*n [n=0...7];
R/W)
This register defines the filtering that corrects which packet triggers low latency interrupt. The following
IMIREXT register includes a size threshold and a control bits bitmap to trigger an immediate interrupt.
Note:
The Port field should be written in network order.
If one of the actions for this filter is set, then at least one of the PORT_BP, Size_BP, one of
the Mask bits or CtrlBit_BP bits should be cleared.
Field
Bit(s)
Initial Value
Description
Destination Port
15:0
0x0
Destination TCP port
This field is compared with the Destination TCP port in incoming packets.
Immediate
Interrupt
16
0b
Enables issuing an immediate interrupt when the following conditions are met:
PORT_BP
17
X
•
The filter associated with this register matches
•
The Length filter associated with this filter matches
•
The TCP flags filter associated with this filter matches
Port Bypass
When set to 1b, the TCP port check is bypassed and only other conditions are
checked.
When set to 0b, the TCP port is checked to fit the port field.
Reserved
28:18
0x0
Reserved
Filter Priority
31:29
000b
Defines the priority of the filter assuming two filters with same priority don’t
match. If two filters with the same priority match the incoming packet, the first
filter (lowest ordinal number) is used in order to define the queue destination of
this packet.
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Immediate Interrupt Rx Ext. - IMIREXT (0x5AA0 + 4*n [n=0...7]; R/W) — Intel® 82580EB/82580DB
GbE Controller
7.11.2
Immediate Interrupt Rx Ext. - IMIREXT (0x5AA0 + 4*n
[n=0...7]; R/W)
Field
Size_Thresh
Bit(s)
11:0
Initial Value
X
Description
Size Threshold
These 12 bits define a size threshold; a packet with a length below this threshold
triggers an interrupt. Enabled by Size_Thresh_en.
Size_BP
12
X
Size Bypass
When 1b, the size check is bypassed.
When 0b, the size check is performed.
CtrlBit
18:13
X
Control Bit
When a bit in this field equals 1b, an interrupt is immediately issued after receiving a
packet with the corresponding TCP control bits turned on.
Bit 13 (URG): Urgent pointer field significant
Bit 14 (ACK): Acknowledgment field
Bit 15 (PSH): Push function
Bit 16 (RST): Reset the connection
Bit 17 (SYN): Synchronize sequence numbers
Bit 18 (FIN): No more data from sender
CtrlBit_BP
19
X
Control Bits Bypass
When set to 1b, the control bits check is bypassed.
When set to 0b, the control bits check is performed.
Reserved
Note:
31:20
0x0
Reserved
The size used for this comparison is the size of the packet as forwarded to the host and
does not include any of the fields stripped by the MAC (VLAN or CRC). As a result, setting
the RCTL.SECRC & CTRL.VME bits should be taken into account while calculating the size
threshold.
The value of the IMIR and IMIREXT registers after reset is unknown (apart from the
IMIR.PORT_IM_EN bit which is guaranteed to be cleared). Therefore, both registers should
be programmed before IMIR.PORT_IM_EN is set for a given flow.
7.11.3
(0x59E0 + 4*n[n=0...7]; RW)
Field
Bit(s)
Initial Value
Description
Protocol
7:0
0x0
IP L4 protocol, part of the queue filters.
Queue Enable
8
0b
When set, enables filtering of Rx packets by the defined in this filter to the queue
indicated in this register.
Reserved
11:9
0x0
Reserved.
Write 0 ignore on read.
Reserved
14:12
0
Reserved.
Reserved_1
15
1b (For
legacy
reasons)
Reserved.
0x0
Identifies the Rx queue associated with this filter.
Rx Queue
Revision: 2.50
October 2011
18:16
Write 1 ignore on read.
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Intel® 82580EB/82580DB GbE Controller — Immediate Interrupt Rx VLAN Priority - IMIRVP (0x5AC0;
R/W)
Field
Bit(s)
Initial Value
Description
Reserved
26:19
0b
Reserved
1588 time stamp
27
0b
When set, packets that match this filter are time stamped according to the IEEE
1588 specification.
Mask
31:28
0xF (for
legacy
reasons)
Mask bits for the fields . The corresponding field participates in the match if the
bit below is cleared:
Bit 28 - Mask protocol comparison
Bits 31 - 29 Reserved
7.11.4
Immediate Interrupt Rx VLAN Priority IMIRVP (0x5AC0; R/W)
Field
Vlan_Pri
Bit(s)
2:0
Initial Value
000b
Description
VLAN Priority
This field includes the VLAN priority threshold. When Vlan_pri_en is set to 1b, then an
incoming packet with a VLAN tag with a priority field equal or higher to VlanPri triggers
an immediate interrupt, regardless of the EITR moderation.
Vlan_pri_en
3
0b
VLAN Priority Enable
When set to 1b, an incoming packet with VLAN tag with a priority equal or higher to
Vlan_Pri triggers an immediate interrupt, regardless of the EITR moderation.
When set to 0b, the interrupt is moderated by EITR.
Reserved
7.11.5
31:4
0x0
SYN Packet Queue Filter - SYNQF (0x55FC; RW)
Field
Queue Enable
Reserved
Bit(s)
0
Initial Value
0b
Description
When set, enables forwarding of Rx packets to the queue indicated in this
register.
Rx Queue
3:1
0x0
Identifies an Rx queue associated with SYN packets.
Reserved
31:4
0x0
Reserved
7.11.6
EType Queue Filter - ETQF (0x5CB0 + 4*n[n=0...7]; RW)
Field
EType
Bit(s)
15:0
Initial Value
0x0
Description
Identifies the protocol running on top of IEEE 802. Used to forward Rx packets
containing this EType to a specific Rx queue.
Rx Queue
18:16
0x0
Identifies the receive queue associated with this EType.
Reserved
25:19
0x0
Reserved
Filter enable
26
0b
When set, this filter is valid. Any of the actions controlled by the following fields
are gated by this field.
Reserved
27
0b
Reserved
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Transmit Register Descriptions — Intel® 82580EB/82580DB GbE Controller
Field
Bit(s)
Initial Value
Description
Reserved
28
0b
Reserved
Immediate
Interrupt
29
0x0
When set, packets that match this filter generate an immediate interrupt.
1588 time stamp
30
0b
When set, packets with this EType are time stamped according to the IEEE 1588
specification.
Queue Enable
31
0b
When set, enables filtering of Rx packets by the EType defined in this register to
the queue indicated in this register.
7.12
Transmit Register Descriptions
7.12.1
Transmit Control Register - TCTL (0x0400; R/W)
This register controls all transmit functions for the 82580EB/DB.
Field
Reserved
Bit(s)
0
Initial Value
0b
Description
Reserved
Write 0, ignore on read.
EN
1
0b
Transmit Enable
The transmitter is enabled when this bit is set to 1b. Writing 0b to this bit stops
transmission after any in progress packets are sent. Data remains in the transmit FIFO
until the device is re-enabled. Software should combine this operation with reset if the
packets in the TX FIFO should be flushed.
Reserved
2
0b
Reserved
Write 0, ignore on read.
PSP
3
1b
Pad Short Packets
0b = Do not pad.
1b = Pad.
Padding makes the packet 64 bytes long. This is not the same as the minimum
collision distance.
If padding of short packets is allowed, the total length of a packet not including FCS
should be not less than 17 bytes.
CT
11:4
0xF
Collision Threshold
This determines the number of attempts at retransmission prior to giving up on the
packet (not including the first transmission attempt). While this can be varied, it
should be set to a value of 15 in order to comply with the IEEE specification requiring
a total of 16 attempts. The Ethernet back-off algorithm is implemented and clamps to
the maximum number of slot-times after 10 retries. This field only has meaning when
in half-duplex operation.
Note: Software can choose to abort packet transmission in less than the Ethernet
mandated 16 collisions. For this reason, hardware provides CT support.
BST
21:12
0x40
Back-Off Slot Time
This value determines the back-off slot time value in byte time.
Revision: 2.50
October 2011
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Intel® 82580EB/82580DB GbE Controller — Transmit Control Extended - TCTL_EXT (0x0404; R/W)
Field
SWXOFF
Bit(s)
22
Initial Value
0b
Description
Software XOFF Transmission
When set to 1b, the 82580EB/DB schedules the transmission of an XOFF (PAUSE)
frame using the current value of the PAUSE timer (FCTTV.TTV). This bit self-clears
upon transmission of the XOFF frame.
Note: While 802.3x flow control is only defined during full duplex operation, the
sending of PAUSE frames via the SWXOFF bit is not gated by the duplex settings
within the 82580EB/DB. Software should not write a 1b to this bit while the 82580EB/
DB is configured for half-duplex operation.
Reserved
23
0b
RTLC
24
0b
Reserved
Re-transmit on Late Collision
When set, enables the 82580EB/DB to re-transmit on a late collision event.
Note: RTLC configures the 82580EB/DB to perform retransmission of packets when a
late collision is detected. Note that the collision window is speed dependent: 64 bytes
for 10/100 Mb/s and 512 bytes for 1000 Mb/s operation. If a late collision is detected
when this bit is disabled, the transmit function assumes the packet has successfully
transmitted. This bit is ignored in full-duplex mode.
Reserved
25
0b
Reserved
Reserved
27:26
0x1
Reserved
Reserved
31:28
0xA
Reserved
7.12.2
Transmit Control Extended - TCTL_EXT (0x0404; R/W)
This register controls late collision detection.
The COLD field is used to determine the latest time in which a collision indication is considered as a
valid collision and not a late collision. When using the internal PHY, the default value of 0x40 provides a
behavior consistent with the 802.3 spec requested behavior. However, when using an SGMII connected
external PHY, the SGMII interface adds some delay on top of the time budget allowed by the
specification (collisions in valid network topographies even after 512 bit time can be expected). In order
to accommodate this condition, COLD should be updated to take the SGMII inbound and outbound
delays.
Field
Bit(s)
Initial Value
Description
Reserved
9:0
0x40
Reserved
COLD
19:10
0x42
Collision Distance
Used to determine the latest time in which a collision indication is considered as a
valid collision and not a late collision.
Reserved
7.12.3
31:20
0x0
Reserved.
Transmit IPG Register - TIPG (0x0410; R/W)
This register controls the Inter Packet Gap (IPG) timer.
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Retry Buffer Control – RETX_CTL (0x041C; RW) — Intel® 82580EB/82580DB GbE Controller
Field
IPGT
Bit(s)
9:0
Initial Value
0x08
Description
IPG Back to Back
Specifies the IPG length for back to back transmissions in both full and half duplex.
Measured in increments of the MAC clock:
8 ns MAC clock when operating @ 1 Gb/s.
80 ns MAC clock when operating @ 100 Mb/s.
800 ns MAC clock when operating @ 10 Mb/s.
IPGT specifies the IPG length for back-to-back transmissions in both full duplex and
half duplex. Note that an offset of 4 byte times is added to the programmed value to
determine the total IPG. As a result, a value of 8 is recommended to achieve a 12 byte
time IPG.
IPGR1
19:10
0x04
IPG Part 1
Specifies the portion of the IPG in which the transmitter defers to receive events.
IPGR1 should be set to 2/3 of the total effective IPG (8).
Measured in increments of the MAC clock:
8 ns MAC clock when operating @ 1 Gb/s.
80 ns MAC clock when operating @ 100 Mb/s
800 ns MAC clock when operating @ 10 Mb/s.
IPGR
29:20
0x06
IPG After Deferral
Specifies the total IPG time for non back-to-back transmissions (transmission
following deferral) in half duplex.
Measured in increments of the MAC clock:
8 ns MAC clock when operating @ 1 Gb/s.
80 ns MAC clock when operating @ 100 Mb/s
800 ns MAC clock when operating @ 10 Mb/s.
An offset of 5-byte times must be added to the programmed value to determine the
total IPG after a defer event. A value of 7 is recommended to achieve a 12-byte
effective IPG. Note that the IPGR must never be set to a value greater than IPGT. If
IPGR is set to a value equal to or larger that IPGT, it overrides the IPGT IPG setting in
half duplex resulting in inter-packet gaps that are larger then intended by IPGT. In this
case, full duplex is unaffected and always relies on IPGT.
Reserved
31:30
00b
Reserved
Read as 0b.
Should be written with 0b for future compatibility.
7.12.4
Retry Buffer Control – RETX_CTL (0x041C; RW)
This register controls the collision retry buffer.
Field
Bit(s)
Initial Value
Description
Water Mark
3:0
0x3
Retry buffer water mark. This parameters defines the minimal number of QWords that
should be present in the retry buffer before transmission is started.
Reserved
31:4
0x0
Reserved.
7.12.5
DMA Tx Control - DTXCTL (0x3590; R/W)
This register is used to set some parameters controlling the DMA Tx behavior.
Revision: 2.50
October 2011
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Intel® 82580EB/82580DB GbE Controller — DMA TX TCP Flags Control Low - DTXTCPFLGL (0x359C;
RW)
Field
Bit(s)
Initial Value
Description
Reserved
1:0
0b
Reserved.
8023LL
2
1b
802.3 length location
1b = The location of the 802.3 length field in 802.3+SNAP packets, is
assumed to be 8 bytes before the end of the MAC header.
0b = The location of the 802.3 length field in 802.3+SNAP packets, is
calculated from the beginning of the MAC header assuming no VLAN present
in the packet sent by the software.
This bit is used only in case of large send (TSO) with SNAP mode.
Reserved
3
0b
OutOfSyncEnable
4
0b
Reserved
0b = Out Of sync mechanism is disabled.
1b = Out Of sync mechanism is enabled.
MDP_EN
5
0b
Malicious driver protection enable
0b = mechanism is disabled.
1b = mechanism is enabled.
Reserved
19:6
0x0
Cswthresh
25:20
0x4
Reserved
Context switch threshold.
Defines the amount of back to back transmit context descriptors above
which the driver will be considered as malicious.
Maximum value should be less than 19.
Reserved
7.12.6
31:26
0x0
Reserved
DMA TX TCP Flags Control Low - DTXTCPFLGL (0x359C;
RW)
This register holds the buses that “AND” the control flags in TCP header for the first and middle
segments of a TSO packet. See Section 8.2.4.7.1 and Section 8.2.4.7.2 for details on the use of this
register.
Field
Bit(s)
Initial Value
Description
TCP_flg_first_seg
11:0
0xFF6
TCP Flags first segment. Bits that are used to execute an AND operation with the
TCP flags in the TCP header in the first segment
Reserved
15:12
0x00
Reserved
TCP_Flg_mid_seg
27:16
0xF76
TCP Flags middle segments. Bits that are used to execute an AND operation with
the TCP flags in the TCP header in the middle segments
Reserved
31:28
0x00
Reserved
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DMA TX TCP Flags Control High - DTXTCPFLGH (0x35A0; RW) — Intel® 82580EB/82580DB GbE
Controller
7.12.7
DMA TX TCP Flags Control High - DTXTCPFLGH (0x35A0;
RW)
This register holds the buses that “AND” the control flags in TCP header for the last segment of a TSO
packet. See Section 8.2.4.7.3 for details of use of this register
Field
Bit(s)
Initial Value
Description
TCP_Flg_lst_seg
11:0
0xF7F
TCP Flags last segment. Bits that are used to execute an AND operation with the
TCP flags at TCP header in the last segment
Reserved
31:12
0x00
Reserved.
7.12.8
DMA TX Max Total Allow Size Requests - DTXMXSZRQ
(0x3540; RW)
This register limits the allowable size of concurrent outstanding TX read requests from the host memory
on the PCIe. Limiting the size of concurrent outstanding PCIe requests allows low latency packet read
requests to be serviced in a timely manner, as the low latency request is serviced right after current
outstanding requests are completed.
Note:
Register is shared by all functions.
Field
Bit(s)
Max_bytes_num_req
11:0
Initial Value
0x10
Description
Maximum allowable size of concurrent TX outstanding requests on PCIe.
Field defines maximum size in 256 byte resolution of outstanding TX requests
to be sent on PCIe. If total amount of outstanding TX requests is higher than
defined in this field, no further TX outstanding requests are sent.
Reserved
31:12
0x0
Reserved
Write 0, ignore on read.
7.12.9
DMA TX Maximum Packet Size - DTXMXPKTSZ (0x355C;
RW)
This register limits the total number of data bytes that might be transmitted in a single frame. Reducing
packet size enables better utilization of transmit buffer.
Field
Bit(s)
Initial Value
Description
MAX_TPKT_SIZE
8:0
0x98
Maximum transmit packet size that is allowed to be transmitted by the driver.
Value entered is in 64 Bytes resolution.
Notes:
1.
Default value enables transmission of maximum sized 9,728 Byte Jumbo
frames.
2.
Values programmed in this field should not exceed 9,728 Bytes.
3.
Value programmed should not exceed the TX buffer size programmed in
the ITPBS.TXPbsize register.
Reserved
31:9
0x0
Reserved
Write 0, ignore on read.
Revision: 2.50
October 2011
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Datasheet
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Intel® 82580EB/82580DB GbE Controller — Transmit Descriptor Base Address Low - TDBAL (0xE000 +
0x40*n [n=0...7]; R/W)
7.12.10
Transmit Descriptor Base Address Low - TDBAL (0xE000 +
0x40*n [n=0...7]; R/W)
These registers contain the lower 32 bits of the 64-bit descriptor base address. The lower 7 bits are
ignored. The Transmit Descriptor Base Address must point to a 128-byte aligned block of data.
Field1
Lower_0
Bit(s)
6:0
Initial Value
0x0
Description
Ignored on writes.
Returns 0x0 on reads.
TDBAL
31:7
X
Transmit Descriptor Base Address Low
1. Software should program TDBAL[n] register only when queue is disabled (TXDCTL[n].Enable = 0).
Note:
In order to keep compatibility with the 82575, for queues 0-3, these registers are aliased to
addresses 0x3800, 0x3900, 0x3A00 & 0x3B00 respectively.
7.12.11
Transmit Descriptor Base Address High - TDBAH (0xE004
+ 0x40*n [n=0...7]; R/W)
These registers contain the upper 32 bits of the 64-bit descriptor base address.
Field1
TDBAH
Bit(s)
31:0
Initial Value
X
Description
Transmit Descriptor Base Address [63:32]
1. Software should program TDBAH[n] register only when queue is disabled (TXDCTL[n].Enable = 0).
Note:
In order to keep compatibility with the 82575, for queues 0-3, these registers are aliased to
addresses 0x3804, 0x3904, 0x3A04 & 0x3B04 respectively.
7.12.12
Transmit Descriptor Ring Length - TDLEN (0xE008 +
0x40*n [n=0...7]; R/W)
These registers contain the descriptor ring length. The registers indicates the length in bytes and must
be 128-byte aligned.
Field1
0
Bit(s)
6:0
Initial Value
0x0
Description
Ignore on writes.
Reads back as 0b.
LEN
19:7
0x0
Descriptor Ring Length (number of 8 descriptor sets).
Note: maximum allowed value in TDLEN field 19:0 is 0x80000 (32K
descriptors).
Reserved
31:20
0x0
Reserved
Reads as 0b.
Should be written to 0b.
1. Software should program TDLEN[n] register only when queue is disabled (TXDCTL[n].Enable = 0).
Intel® 82580EB/82580DB Gigabit Ethernet Controller
Datasheet
352
Revision: 2.50
October 2011
Transmit Descriptor Head - TDH (0xE010 + 0x40*n [n=0...7]; RO) — Intel® 82580EB/82580DB GbE
Controller
Note:
7.12.13
In order to keep compatibility with the 82575, for queues 0-3, these registers are aliased to
addresses 0x3808, 0x3908, 0x3A08 & 0x3B08 respectively.
Transmit Descriptor Head - TDH (0xE010 + 0x40*n
[n=0...7]; RO)
These registers contain the head pointer for the transmit descriptor ring. It points to a 16-byte datum.
Hardware controls this pointer.
Note:
The values in these registers might point to descriptors that are still not in host memory. As
a result, the host cannot rely on these values in order to determine which descriptor to
release.
Field
Bit(s)
Initial Value
TDH
15:0
0x0
Reserved
31:16
0x0
Description
Transmit Descriptor Head
Reserved
Should be written to 0b.
Note:
7.12.14
In order to keep compatibility with the 82575, for queues 0-3, these registers are aliased to
addresses 0x3810, 0x3910, 0x3A10 & 0x3B10 respectively.
Transmit Descriptor Tail - TDT (0xE018 + 0x40*n
[n=0...7]; R/W)
These registers contain the tail pointer for the transmit descriptor ring and points to a 16-byte datum.
Software writes the tail pointer to add more descriptors to the transmit ready queue. Hardware
attempts to transmit all packets referenced by descriptors between head and tail.
Field
Bit(s)
Initial Value
TDT
15:0
0x0
Reserved
31:16
0x0
Description
Transmit Descriptor Tail
Reserved
Reads as 0b.
Should be written to 0b for future compatibility.
Note:
7.12.15
In order to keep compatibility with the 82575, for queues 0-3, these registers are aliased to
addresses 0x3818, 0x3918, 0x3A18 & 0x3B18 respectively.
Transmit Descriptor Control - TXDCTL (0xE028 + 0x40*n
[n=0...7]; R/W)
These registers control the fetching and write-back operations of transmit descriptors. The three
threshold values are used to determine when descriptors are read from and written to host memory.
The values are in units of descriptors (each descriptor is 16 bytes).
Revision: 2.50
October 2011
Intel® 82580EB/82580DB Gigabit Ethernet Controller
Datasheet
353
Intel® 82580EB/82580DB GbE Controller — Transmit Descriptor Control - TXDCTL (0xE028 + 0x40*n
[n=0...7]; R/W)
Since write-back of transmit descriptors is optional (under the control of RS bit in the descriptor), not
all processed descriptors are counted with respect to WTHRESH. Descriptors start accumulating after a
descriptor with RS set is processed. In addition, with transmit descriptor bursting enabled, some
descriptors are written back that did not have RS set in their respective descriptors.
Note:
When WTHRESH = 0, only descriptors with the RS bit set are written back
Field
PTHRESH
Bit(s)
Initial Value
4:0
0x0
Description
Prefetch Threshold
Controls when a prefetch of descriptors is considered. This threshold refers to the
number of valid, unprocessed transmit descriptors the 82580EB/DB has in its on-chip
buffer. If this number drops below PTHRESH, the algorithm considers pre-fetching
descriptors from host memory. However, this fetch does not happen unless there are
at least HTHRESH valid descriptors in host memory to fetch.
Note: When PTHRESH is 0x0 a Transmit descriptor fetch operation is done when any
valid descriptors are available in Host memory and space is available in internal buffer.
Reserved
7:5
0x0
Reserved
HTHRESH
12:8
0x0
Host Threshold
Prefetch of transmit descriptors is considered when number of valid transmit
descriptors in host memory is at least HTHRESH.
Note: HTHRESH should be given a non zero value each time PTHRESH is used.
Reserved
15:13
0x0
WTHRESH
20:16
0x0
Reserved
Write-Back Threshold
Controls the write-back of processed transmit descriptors. This threshold refers to the
number of transmit descriptors in the on-chip buffer that are ready to be written back
to host memory. In the absence of external events (explicit flushes), the write-back
occurs only after at least WTHRESH descriptors are available for write-back.
Possible values for this field are 0 to 23.
Note: Since the default value for write-back threshold is 0b, descriptors are normally
written back as soon as they are processed. WTHRESH must be written to a non-zero
value to take advantage of the write-back bursting capabilities of the 82580EB/DB.
Reserved
23:21
0x0
Reserved
Reserved
24
0b
Reserved
ENABLE
25
0b
Transmit Queue Enable
When set, this bit enables the operation of a specific transmit queue.
Setting this bit initializes the Tail and Head registers (TDT[n] and TDH[n]) of a specific
queue. Until then, the state of the queue is kept and can be used for debug purposes.
When disabling a queue, this bit is cleared only after all transmit activity on this queue
is stopped.
Note: When transmit queue is enabled and descriptors exist, descriptors and data are
fetched immediately. Actual transmit activity on port starts only if the TCTL.EN bit is
set.
Intel® 82580EB/82580DB Gigabit Ethernet Controller
Datasheet
354
Revision: 2.50
October 2011
Tx Descriptor Completion Write–Back Address Low - TDWBAL (0xE038 + 0x40*n [n=0...7]; R/W) —
Intel® 82580EB/82580DB GbE Controller
Field
SWFLSH (WC)
Bit(s)
Initial Value
26
0b
Description
Transmit Software Flush
This bit enables software to trigger descriptor write-back flushing, independently of
other conditions.
This bit is self cleared by hardware. Bit will clear after write-back flush is triggered
(may take a number of cycles).
Note: When working in head write-back mode (TDWBAL.Head_WB_En = 1)
TDWBAL.WB_on_EITR bit should be set for transmit descriptor flush to occur.
Priority
27
0b
Transmit queue priority
0 - Low priority
1 - High priority
When set, Transmit DMA resources are always allocated to the queue before low
priority queues. Arbitration between transmit queues with same priority is done in a
Round Robin fashion.
HWBTHRESH
31:28
0x0
Transmit Head writeback threshold
If value of field is greater than 0x0, head writeback to host will occur only when the
amount of internal pending write backs exceeds this threshold. See Section 8.2.3 for
additional information.
Note: When activating this mode the WB_on_EITR bit in the TDWBAL register should
be set to guarantee a write back after a timeout even if the threshold has not been
reached.
Note:
In order to keep compatibility with the 82575, for queues 0-3, these registers are aliased to
addresses 0x3828, 0x3928, 0x3A28 and 0x3B28 respectively.
7.12.16
Tx Descriptor Completion Write–Back Address Low TDWBAL
(0xE038 + 0x40*n [n=0...7]; R/W)
Field1
Bit(s)
Head_WB_En 0
Initial Value
0b
Description
Head Write-Back Enable
1b = Head write-back is enabled.
0b = Head write-back is disabled.
When head_WB_en is set, TXDCTL.SWFLSH is ignored and no descriptor write-back is
executed.
WB_on_EITR
1
HeadWB_Low 31:2
0b
0x0
When set, a head write back is done upon EITR expiration.
Bits 31:2 of the head write-back memory location (DWORD aligned).
Last 2 bits of this field are ignored and are always interpreted as 00b, meaning that
the actual address is QWORD aligned.
Bits 1:0 are always 00b.
1. Software should program TDWBAL[n] register only when queue is disabled (TXDCTL[n].Enable = 0).
Note:
Revision: 2.50
October 2011
In order to keep compatibility with the 82575, for queues 0-3, these registers are aliased to
addresses 0x3838, 0x3938, 0x3A38 & 0x3B38 respectively.
Intel® 82580EB/82580DB Gigabit Ethernet Controller
Datasheet
355
Intel® 82580EB/82580DB GbE Controller — Tx Descriptor Completion Write–Back Address High TDWBAH (0xE03C + 0x40*n [n=0...7];R/W)
7.12.17
Tx Descriptor Completion Write–Back Address High TDWBAH
(0xE03C + 0x40*n [n=0...7];R/W)
Field1
Bit(s)
HeadWB_High
31:0
Initial Value
0x0
Description
Highest 32 bits of the head write-back memory location.
1. Software should program TDWBAH[n] register only when queue is disabled (TXDCTL[n].Enable = 0).
Note:
In order to keep compatibility with the 82575, for queues 0-3, these registers are aliased to
addresses 0x383C, 0x393C, 0x3A3C & 0x3B3C respectively.
7.13
DCA and TPH Register Descriptions
7.13.1
Rx DCA Control Registers - RXCTL (0xC014 + 0x40*n
[n=0...7]; R/W)
Note:
RX data write no-snoop is activated when the NSE bit is set in the receive descriptor.
Field
RX Descriptor
Fetch TPH EN
Bit(s)
Initial Value
0
0b
Description
Receive Descriptor Fetch TPH Enable
When set, hardware enables TPH for all Rx descriptors fetch from memory. When
cleared, hardware does not enable TPH for descriptor fetches. This bit is cleared as a
default.
1
RX Descriptor
Writeback TPH EN1
0b
Rx Header TPH EN1 2
0b
Receive Descriptor Writeback TPH Enable
When set, hardware enables TPH for all Rx descriptors written back into memory.
When cleared, hardware does not enable TPH for descriptor write-backs. This bit is
cleared as a default. The hint used is the hint set in the Socket ID field.
Receive Header TPH Enable
When set, hardware enables TPH for all received header buffers. When cleared,
hardware does not enable TPH for Rx headers. This bit is cleared as a default. The hint
used is the hint set in the Socket ID field.
Rx Payload TPH
EN1
3
Reserved
4
0b
Receive Payload TPH Enable
When set, hardware enables TPH for all Ethernet payloads written into memory. When
cleared, hardware does not enable TPH for Ethernet payloads. This bit is cleared as a
default. The hint used is the hint set in the Socket ID field.
0b
Reserved
Write 0, ignore on read.
RX Descriptor DCA
EN1
5
Rx Header DCA
EN1
6
Rx Payload DCA
EN1
7
0b
Descriptor DCA Enable
When set, hardware enables DCA for all Rx descriptors written back into memory.
When cleared, hardware does not enable DCA for descriptor write-backs. This bit is
cleared as a default.
0b
Receive Header DCA Enable
When set, hardware enables DCA for all received header buffers. When cleared,
hardware does not enable DCA for Rx headers. This bit is cleared as a default.
0b
Receive Payload DCA Enable
When set, hardware enables DCA for all Ethernet payloads written into memory. When
cleared, hardware does not enable DCA for Ethernet payloads. This bit is cleared as a
default.
Intel® 82580EB/82580DB Gigabit Ethernet Controller
Datasheet
356
Revision: 2.50
October 2011
Rx DCA Control Registers - RXCTL (0xC014 + 0x40*n [n=0...7]; R/W) — Intel® 82580EB/82580DB GbE
Controller
Field
Bit(s)
Initial Value
RXdescRead
NSEn
8
0b
RXdescRead
ROEn
9
1b
RXdescWBNSen
10
0b
Description
Receive Descriptor Read No Snoop Enable
This bit must be reset to 0b to ensure correct functionality (Except if the software
driver can guarantee the data is present in the main memory before the DMA process
occurs).
Note: When TPH is enabled No Snoop bit should be 0.
Receive Descriptor Read Relax Order Enable
Receive Descriptor Write-Back No Snoop Enable
This bit must be reset to 0b to ensure correct functionality of descriptor write-back.
Note: When TPH is enabled No Snoop bit should be 0.
RXdescWBROen
(RO)
11
RXdataWrite
NSEn
12
0b
Receive Descriptor Write-Back Relax Order Enable
This bit must be reset to 0b to ensure correct functionality of descriptor write-back.
0b
Receive Data Write No Snoop Enable (header replication: header and data)
When set to 0b, the last bit of the Packet Buffer Address field in the advanced receive
descriptor is used as the LSB of the packet buffer address (A0), thus enabling Byte
alignment of the buffer.
When set to 1b, the last bit of the Packet Buffer Address field in advanced receive
descriptor is used as the No-Snoop Enabling (NSE) bit (buffer is Word aligned). If also
set to 1b, the NSE bit determines whether the data buffer is snooped or not.
Note: When TPH is enabled No Snoop bit should be 0.
RXdataWrite
ROEn
13
1b
Receive Data Write Relax Order Enable (header replication: header and data)
RxRepHeader
NSEn
14
0b
RxRepHeader
ROEn
15
1b
Receive Replicated/Split Header Relax Order Enable
Reserved
23:16
0b
Reserved
CPUID
31:24
0x0
Receive Replicated/Split Header No Snoop Enable
This bit must be reset to 0b to ensure correct functionality of header write to host
memory.
Note: When TPH is enabled No Snoop bit should be 0.
Physical ID
Legacy DCA capable platforms - the device driver, upon discovery of the physical CPU
ID and CPU Bus ID, programs the CPUID field with the Physical CPU and Bus ID
associated with this Rx queue.
DCA 1.0 capable platforms - the device driver programs a value, based on the relevant
APIC ID, associated with this Tx queue.
See Table 3.1.3.1.2.3 for details.
TPH capable platforms - the device driver programs a value, based on the relevant
Socket ID, associated with this receive queue.
Note that for TPH platforms, bits 31:27 of this field should always be set to zero. See
Section 8.7.2 for details.
1. Both DCA Enable bit and TPH Enable bit should not be set for the same type of traffic.
Note:
Revision: 2.50
October 2011
In order to keep compatibility with the 82575, for queues 0-3, these registers are aliased to
addresses 0x2814, 0x2914, 0x2A14 & 0x2B14 respectively.
Intel® 82580EB/82580DB Gigabit Ethernet Controller
Datasheet
357
Intel® 82580EB/82580DB GbE Controller — Tx DCA Control Registers - TXCTL (0xE014 + 0x40*n
[n=0...7]; R/W)
7.13.2
Field
Tx DCA Control Registers - TXCTL (0xE014 + 0x40*n
[n=0...7]; R/W)
Bit(s)
Initial Value
0b
Description
Tx Descriptor Fetch
TPH EN1
0
Transmit Descriptor Fetch TPH Enable
Tx Descriptor
Writeback TPH EN
1
Reserved
2
0b
Reserved
Tx Packet TPH EN
3
0b
Transmit Packet TPH Enable
When set, hardware enables TPH for all Tx descriptors fetch from memory. When
cleared, hardware does not enable TPH for descriptor fetches. This bit is cleared as a
default.
0b
Transmit Descriptor Writeback TPH Enable
When set, hardware enables TPH for all Tx descriptors written back into memory.
When cleared, hardware does not enable TPH for descriptor write-backs. This bit is
cleared as a default. The hint used is the hint set in the Socket ID field.
When set, hardware enables TPH for all Ethernet payloads read from memory. When
cleared, hardware does not enable TPH for Ethernet payloads. This bit is cleared as a
default.
Reserved
4
0b
Reserved
TX Descriptor DCA
EN1
5
0b
Descriptor DCA Enable
Reserved
7:6
00b
TXdescRDNSen
8
0b
When set, hardware enables DCA for all Tx descriptors written back into memory.
When cleared, hardware does not enable DCA for descriptor write-backs. This bit is
cleared as a default and also applies to head write-back when enabled.
Reserved
Tx Descriptor Read No Snoop Enable
This bit must be reset to 0b to ensure correct functionality (unless the software
device driver has written this bit with a write-through instruction).
Note: When TPH is enabled No Snoop bit should be 0.
TXdescRDROEn
9
1b
TXdescWBNSen
10
0b
Tx Descriptor Read Relax Order Enable
Tx Descriptor Write-Back No Snoop Enable
This bit must be reset to 0b to ensure correct functionality of descriptor write-back.
Also applies to head write-back, when enabled.
Note: When TPH is enabled No Snoop bit should be 0.
TXdescWBROen
11
1b
Tx Descriptor Write-Back Relax Order Enable
Applies to head write-back, when enabled.
TXDataReadNSEn
12
0b
Tx Data Read No Snoop Enable
Note: When TPH is enabled No Snoop bit should be 0.
TXDataReadROEn
13
1b
Reserved
23:14
0x0
Tx Data Read Relax Order Enable
Reserved
Write 0 ignore on read.
CPUID
31:24
0x0
Physical ID
Legacy DCA capable platforms - the device driver, upon discovery of the physical CPU
ID and CPU Bus ID, programs the CPUID field with the Physical CPU and Bus ID
associated with this Tx queue.
DCA 1.0 capable platforms - the device driver programs a value, based on the
relevant APIC ID, associated with this Tx queue.
See Table 3.1.3.1.2.3 for details
TPH capable platforms - the device driver programs a value, based on the relevant
Socket ID, associated with this transmit queue.
Note that for TPH platforms, bits 31:27 of this field should always be set to zero. See
Section 8.7.2 for details.
Intel® 82580EB/82580DB Gigabit Ethernet Controller
Datasheet
358
Revision: 2.50
October 2011
DCA Requester ID Information - DCA_ID (0x5B70; RO) — Intel® 82580EB/82580DB GbE Controller
1. Both DCA Enable bit and TPH Enable bit should not be set for the same type of traffic.
Note:
In order to keep compatibility with the 82575, for queues 0-3, these registers are aliased to
addresses 0x3814, 0x3914, 0x3A14 & 0x3B14 respectively.
7.13.3
DCA Requester ID Information - DCA_ID (0x5B70; RO)
The DCA requester ID field, composed of Device ID, Bus #, and Function # is set up in MMIO space for
software to program the DCA Requester ID Authentication register.
Field
Bit(s)
Initial Value
Function
Number
2:0
000b
Device
Number
7:3
Bus Number
15:8
0x0
Reserved
31:16
0x0
Description
Function Number
Function number assigned to the function based on BIOS/operating system
enumeration.
0x0
Device Number
Device number assigned to the function based on BIOS/operating system
enumeration.
Bus Number
Bus number assigned to the function based on BIOS/operating system enumeration.
7.13.4
Reserved
DCA Control - DCA_CTRL (0x5B74; R/W)
This CSR is common to all functions.
Field
DCA_DIS
Bit(s)
0
Initial Value
1b
Description
DCA Disable
0b = DCA tagging is enabled.
1b = DCA tagging is disabled.
DCA_MODE
4:1
0x0
DCA Mode
000b = Legacy DCA is supported. The TAG field in the TLP header is based on the
following coding: bit 0 is DCA enable; bits 3:1 are CPU ID).
001b = DCA 1.0 is supported. When DCA is disabled for a given message, the TAG
field is 0000,0000b. If DCA is enabled, the TAG is set per queue as programmed in the
relevant DCA Control register.
All other values are undefined.
Reserved
8:5
0x0
Reserved
Desc_PH
10:9
00b
Descriptor PH - defines the PH field used when a TPH hint is given for descriptor
associated traffic (descriptor fetch, descriptor write back or head write back).
Data_PH
12:11
10b
Data PH - defines the PH field used when a TPH hint is given for data associated traffic
(Tx data read, Rx data write).
Reserved
31:13
0x0
Reserved
Revision: 2.50
October 2011
Intel® 82580EB/82580DB Gigabit Ethernet Controller
Datasheet
359
Intel® 82580EB/82580DB GbE Controller — Virtualization Register Descriptions
7.14
Virtualization Register Descriptions
7.14.1
VMDq Control register – VT_CTL (0x581C; R/W)
Field
Initial
Value
Bit(s)
Description
Reserved
6:0
0x0
DEF_PL
9:7
000b
Reserved
Default pool - used to queue packets that did not pass any VM queuing decision.
Reserved
26:10
0x0
Reserved
FLP
27
0b
Filter local packets - filter incoming packets whose MAC source address matches one
of the LAN port DA MAC addresses. If the SA of the received packet matches one of
the DA in the RAH/RAL registers, then the VM tied to this DA does not receive the
packet. Other VMs can still receive it.
IGMAC
28
0b
If set, MAC address is ignored during pool decision. Pooling is based on VLAN only.
If this bit is set, then the VMOLR.strvlan should be set to the same value for all pools,
Dis_Def_Pool
29
0b
Drop if no pool is found. If this bit is asserted, then in a RX switching virtualized
environment, if there is no destination pool, the packet is discarded and not sent to
the default pool. Otherwise, it is sent to the pool defined by the DEF_PL field.
Rpl_En
30
0b
Replication Enable
Reserved
31
0b
Reserved
7.14.2
Malicious Driver Free Block - MDFB (0x3558; RWS)
Field
Bit(s)
Initial Value
Description
Block Queue
7:0
0x0
Indicates queue that was blocked due to malicious behavior. When bit is
set, to commence activity on offending queue, Software should initiate a
software reset and re-initialize all queues on the port.
Reserved
31:8
0x0
Reserved
7.14.3
Last VM Misbehavior Cause – LVMMC (0x3548; RC)
Bits in LVMMC register define the cause for blocking the malicious queue that was reported in the
MDFB.Block Queue field.
Field
Bit(s)
Initial Value
Description
Mac Header
0
0b
Illegal MAC header size.
IPV4 Header
1
0b
Illegal IPV4 header size.
IPV6 Header
2
0b
Illegal IPV6 header size.
Wrong MAC_IP
3
0b
Wrong MAC+IP header size
TCP LSO
4
0b
Reserved
5
0b
UDP LSO
6
0b
Illegal UDP header was detected in a large send operation.
SCTP SSO
7
0b
Illegal SCTP header was detected in a single send operation.
Leg_Size
8
0b
Illegal legacy descriptor size.
Adv_Size
9
0b
Illegal advanced descriptor size.
Intel® 82580EB/82580DB Gigabit Ethernet Controller
Datasheet
360
Illegal TCP header was detected in a large send operation.
Reserved
Revision: 2.50
October 2011
VM Offload register - VMOLR (0x5AD0 + 4*n [n=0...7]; RW) — Intel® 82580EB/82580DB GbE Controller
Field
Bit(s)
Initial Value
Description
Off_Ill
10
0b
Illegal offload request.
SCTP_aligned
11
0b
CRC request of non 4 byte aligned data.
Reserved
15:5
0b
Reserved
SSO_UDP
17
0b
Wrong parameter of headers for UDP SSO
SSO_TCP
18
0b
Wrong parameter of headers for TCP SSO
Reserved
19
0b
Reserved
DESC_TYPE
20
0b
Wrong descriptor type (other than 2,3)
Wrong_null
21
0b
Null without EOP
No EOP
22
0b
Packet without EOP (i.e. bigger than the ring size)
ILL_DBU
24
0b
Illegal DBU configuration.
Reserved
27:25
0b
Reserved
Ignore on read write 0.
Mal_PF
28
0b
Malicious Driver behavior detected on current PF
Last_Q
31:29
0x0
Last queue that detected malicious behavior.
7.14.4
VM Offload register - VMOLR (0x5AD0 + 4*n [n=0...7];
RW)
This register controls the offload and queueing options applied to each pool (VM).
Field
Bit(s)
rlpml
13:0
Reserved
15:14
lpe
0x2600
16
Reserved
Initial Value
17
Description
Long packet size (9k default)
0x0
Reserved
0b
Long packet enable
0b
Reserved
Reserved
23:18
0x0
Reserved
aupe
24
0b
Accept Untagged packets enable. When set, packets without VLAN tag can
be forwarded to this queue, assuming they pass the MAC address queueing
mechanism.
rompe
25
0b
receive overflow multicast packets - accept packets that match the MTA
table.
rope
26
0b
receive overflow packets - accept packets that match the UTA table.
bam
27
0b
Broadcast accept
mpe
28
0b
multicast promiscuous
Reserved
29
0b
Reserved
strvlan
30
0b
VLAN strip
Reserved
31
1b
Reserved - must be set to one.
7.14.5
Replication Offload register - RPLOLR (0x5AF0; RW)
This register describes the off loads applied to multicast packets.
Field
Revision: 2.50
October 2011
Bit(s)
Initial Value
Description
Intel® 82580EB/82580DB Gigabit Ethernet Controller
Datasheet
361
Intel® 82580EB/82580DB GbE Controller — VLAN VM Filter - VLVF (0x5D00 + 4*n [n=0...31]; RW)
Reserved
29:0
0x0
strvlan
30
0b
Reserved
31
1b
7.14.6
Reserved
VLAN strip
Reserved - must be set to one.
VLAN VM Filter - VLVF (0x5D00 + 4*n [n=0...31]; RW)
This register set describes which VLANs the local VMs are part of. Each of the 32 registers contains a
VLAN tag and a list of the VMs which are part of it. Only packets with a VLAN matching one of the VLAN
tags of which the VM is member of are forwarded to this VM.
Field
Bit(s)
Initial Value
VLAN_Id
11:0
0x0
POOLSEL
19:12
0x0
Description
Defines a VLAN tag, to which each VM whose bit is set in the POOLSEL field, belongs
to.
Pool Select (bitmap)
Field defines to which VMs a packet with the VLAN_Id should be forwarded to. A bit is
allocated to each of the 8 VMs, enabling forwarding the packet with the VLAN_Id to
multiple VMs.
Reserved
30:20
0x0
VI_En
31
0b
Reserved
Write 0, ignore on read.
VLAN Id Enable - this filter is valid.
Note: If RCTL.VFE is 0 all VLVF filters are disabled.
7.14.7
Unicast Table Array - UTA (0xA000 + 4*n [n=0...127]; R/
W)
There is one register per 32 bits of the Unicast Address Table for a total of 128 registers (the
UTA[127:0] designation). Software must mask to the desired bit on reads and supply a 32-bit word on
writes. The first bit of the address used to access the table is set according to the RCTL.MO field.
Note:
All accesses to this table must be 32 bit.
The lookup algorithm is the same one used for the MTA table.
This table should be zeroed by software before start of work.
Field
Bit Vector
Bit(s)
31:0
Initial Value
X
Description
Word wide bit vector specifying 32 bits in the unicast destination address filter table.
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Storm Control control register- SCCRL (0x5DB0;RW) — Intel® 82580EB/82580DB GbE Controller
7.14.8
Storm Control control register- SCCRL (0x5DB0;RW)
Field
Bit(s)
Initial Value
Description
MDIPW
0
0b
Drop multicast packets (excluding flow control and manageability packets) if
multicast threshold is exceeded in previous window
MDICW
1
0b
Drop multicast packets (excluding flow control and manageability packets) if
multicast threshold is exceeded in current window
BDIPW
2
0b
Drop broadcast packets (excluding flow control and manageability packets) if
broadcast threshold is exceeded in previous window
BDICW
3
0b
Drop broadcast packets (excluding flow control and manageability packets) if
broadcast threshold is exceeded in current window
BIDU
4
0b
BSC Includes Destination Unresolved packets: If bit is set, unicast received packets
with no destination pool and sent to the default pool are included in IBSC
RSVD
7:5
0x0
Reserved
INTERVAL
17:8
0x8
BSC/MSC Time-interval-specification: The interval size for applying Ingress Broadcast
or Multicast Storm Control. Interrupt decisions are made at the end of each interval
(and most flags are also set at interval end). Setting this field resets the counter.
RSVD
31:18
0x0
Reserved
7.14.9
Storm Control status - SCSTS (0x5DB4;RO)
Field
BSCA
Bit(s)
0
Initial Value
0b
Description
Broadcast storm control active
BSCAP
1
0b
Broadcast storm control active in previous window
MSCA
2
0b
Multicast storm control active
MSCAP
3
0b
Multicast storm control active in previous window
RSVD
31:4
0x0
Reserved
7.14.10
Field
Broadcast Storm control Threshold - BSCTRH
(0x5DB8;RW)
Bit(s)
Initial Value
Description
UTRESH
18:0
0x0
Traffic Upper Threshold-size: Represents the upper threshold for broadcast storm
control.
RSVD
31:19
0x0
Reserved
Revision: 2.50
October 2011
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Intel® 82580EB/82580DB GbE Controller — Multicast Storm control Threshold - MSCTRH (0x5DBC; RW)
7.14.11
Field
Multicast Storm control Threshold - MSCTRH (0x5DBC;
RW)
Bit(s)
Initial Value
Description
UTRESH
18:0
0x0
Traffic Upper Threshold-size: Represents the upper threshold for multicast storm
control.
RSVD
31:19
0x0
Reserved
7.14.12
Broadcast Storm Control Current Count - BSCCNT
(0x5DC0;RO)
Field
Bit(s)
Initial Value
Description
CCOUNT
24:0
0x0
IBSC Traffic Current Count: Represents the count of broadcast traffic received in the
current time interval in units of 64-byte segments.
RSVD
31:25
0x0
Reserved.
7.14.13
Field
Multicast Storm control Current Count - MSCCNT
(0x5DC4;RO)
Bit(s)
Initial Value
Description
CCOUNT
24:0
0x0
IMSC Traffic Current Count: Represents the count of multicast traffic received in the
current time interval in units of f 64-byte segments.
RSVD
31:25
0x0
Reserved.
7.14.14
Storm Control Time Counter - SCTC (0x5DC8; RO)
This register keeps track of the number of time units elapsed since the end of last time interval.
Field
Bit(s)
Initial Value
Description
COUNT
9:0
0x0
SC Time Counter: The counter for number of time units elapsed since the end of the
last time interval.
RSVD
31:10
0x0
Reserved.
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Storm Control Basic interval- SCBI (0x5DCC; RW) — Intel® 82580EB/82580DB GbE Controller
7.14.15
Storm Control Basic interval- SCBI (0x5DCC; RW)
This register defines the basic interval used as the base for the SCCRL.Interval counting in 10 Mb/s
speed. This register is defined in 16 ns clock cycles. The interval in 1000/100 is 100 or 10 time smaller
respectively.
Field
Bit(s)
Initial Value
Description
BI
24:0
0x5F5E10
Basic interval
RSVD
31:25
0x0
Reserved.
7.14.16
Virtual Mirror rule control - VMRCTL (0x5D80 + 0x4*n [n=
0...3]; RW)
This register controls the rules to be applied and the destination port.
Field
Bit(s)
Initial Value
Description
VPME
0
0b
Virtual pool mirroring enable- reflects all the packets sent to a set of given VMs.
UPME
1
0b
Uplink port mirroring enable - reflects all the traffic received from the network.
Reserved
2
0b
Reserved
VLME
3
0b
VLAN mirroring enable - reflects all the traffic received in a set of given VLANs. bit
enables mirroring operation based
Reserved
7:4
0x0
Reserved
MP
10:8
0x0
VM Mirror port destination.
Packets destined to certain VLAN groups, are mirrored to the queue defined by the MP
field, according to the VMRVLAN register. Packets destined to certain VMs, are
mirrored to the queue defined by the MP field, according to the VMRVM register.
Note: If the VMRCTL.UPME bit is set to 1 all packets received on the port will be
forwarded to the queue defined in the MP field.
Reserved
7.14.17
31:11
0x0
Reserved
Virtual Mirror rule VLAN - VMRVLAN (0x5D90 + 0x4*n [n=
0...3]; RW)
This register controls the VLAN ports as listed in the VLVF table taking part in the VLAN mirror rule.
Field
VLAN
Bit(s)
31:0
Initial Value
0x0
Description
Bitmap listing that defines which of the 32 VLANs defined in the VLVF registers
participate in the mirror rule.
Packets that have a matching Vlan_ID as defined by the VLVF registers will also be
forwarded (mirrored) to the queue defined in the VMRCTL.MP field, if the
VMRCTL.VLME bit is set to 1.
Revision: 2.50
October 2011
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Intel® 82580EB/82580DB GbE Controller — Virtual Mirror rule VM - VMRVM (0x5DA0 + 0x4*n [n=
0...3]; RW)
7.14.18
Virtual Mirror rule VM - VMRVM (0x5DA0 + 0x4*n [n=
0...3]; RW)
This register controls the VLAN ports as listed in the VLVF table taking part in the VLAN mirror rule.
Field
VM
Bit(s)
Initial Value
7:0
0x0
Description
Bitmap listing of VMs participating in the mirror rule.
Packets that are forwarded to the queues defined in the VMRVM.VM field,
will also be forwarded (mirrored) to the queue defined in the VMRCTL.MP
field, if the VMRCTL.VPME bit is set to 1.
Reserved
7.15
31:8
0x0
Reserved
Power Management Registers Description
Following registers enable control of various DMA power saving features.
7.15.1
Field
DMACWT
DMA Coalescing Control Register - DMACR (0x2508; R/W)
Bit(s)
Initial Value
13:0
0x0
Description
DMA Coalescing Watchdog Timer
This value sets the upper limit in 32 μsec units between arrival of receive packet or
interrupt cause and initiation of PCIe access to service the received packet or
interrupt cause.
Reserved
15:14
0x0
Reserved
Write 0 ignore on read.
DMACTHR
23:16
0x0
DMA Coalescing Receive Threshold
This value defines the DMA coalescing Receive threshold in 1 Kilobyte units. When
amount of data in internal receive buffer exceeds DMACTHR value, DMA coalescing is
stopped and PCIe moves to L0 state.
Notes:
1.
Value should be lower than FCRTC.RTH_Coal threshold value, to avoid needless
generation of flow control packets when in DMA coalescing operating mode.
2.
Receive threshold size should be smaller than internal receive buffer area
reported in IRPBS.RXPbsize field.
3.
Value programmed should be greater than Maximum packet size.
4.
Move out of DMA coalescing state will occur when amount of data in the internal
RX buffer exceeds by 1 Kilobytes the value programmed in this field.
Reserved
26:24
0x0
Reserved
Write 0 ignore on read.
Reserved
27:24
0x0
Reserved
Write 0 ignore on read.
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DMA Coalescing Transmit Threshold - DMCTXTH (0x3550;RW) — Intel® 82580EB/82580DB GbE
Controller
Field
DMAC_Lx
Bit(s)
Initial Value
29:28
10b
Description
Move to Lx low power link state when no PCIe transactions
00b – Stay in L0.
01b – Move to L0s when no PCIe transactions
10b - Move to L1 when no PCIe transactions
11b - Reserved
When DMA coalescing is enabled (DMACR.DMAC_EN = 1) value of field should be 10b.
Reserved
30
0b
Reserved
Write 0 ignore on read.
DMAC_EN
31
0b
DMA Coalescing Enable
0 - Disable DMA Coalescing
1 - Enable DMA Coalescing
7.15.2
Field
DMCTTHR
DMA Coalescing Transmit Threshold - DMCTXTH
(0x3550;RW)
Bit(s)
11:0
Initial Value
0xE4
Description
DMA Coalescing Transmit Threshold
This value defines the DMA coalescing transmit threshold in 64 byte units. When
amount of empty space in internal transmit buffer exceeds DMCTTHR value and
additional transmit data is available in main memory, DMA coalescing is stopped and
PCIe moves to L0 state.
Notes:
1. If value is 0x0 DMA Coalescing transmit threshold mechanism is disabled.
2. Transmit threshold size should be smaller than Internal Transmit Buffer area
reported in ITPBS.TXPbsize field.
RSVD
7.15.3
31:12
0b
Reserved
DMA Coalescing Time to Lx Request - DMCTLX
(0x2514;RW)
This CSR is common to all functions.
Field
TTLX
Bit(s)
11:0
Initial Value
0x0
Description
Time to LX request:
Represents the time between detection of low power Link condition to actual request.
Timer counts is in 1sec intervals.
RSVD
Revision: 2.50
October 2011
31:12
0x0
Reserved
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Intel® 82580EB/82580DB GbE Controller — DMA Coalescing Receive Packet Rate Threshold - DMCRTRH
(0x5DD0;RW)
7.15.4
DMA Coalescing Receive Packet Rate Threshold DMCRTRH (0x5DD0;RW)
Field
UTRESH
Bit(s)
18:0
Initial Value
0x0
Description
Receive Traffic Threshold-size:
Represents the upper threshold for RX packet rate. Packet rate below this value will
not allow entering DMA coalescing.
Threshold is measured in 64 Byte chunks of data received during the interval defined
in the SCCRL.INTERVAL field using the time units defined in the SCBI register.
RSVD
30:19
0b
Reserved
LRPRCW
(RO)
31
0b
Low Receive packet rate in current window
0b - Packet rate above DMCRTRH.UTRESH threshold detected.
1b - Packet rate below DMCRTRH.UTRESH threshold detected.
7.15.5
Field
CCOUNT
DMA Coalescing Current RX Count - DMCCNT (0x5DD4;RO)
Bit(s)
24:0
Initial Value
0x0
Description
DMA Coalescing Receive Traffic Current Count:
Represents the count of receive traffic in the current time interval in units of 64-byte
segments.
Notes:
1.
Counter does not wrap around.
2.
Count stops when value defined in DMCRTRH.UTRESH field is reached.
Reserved
31:25
0x0
Reserved.
Write 0, ignore on read.
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Flow Control Receive Threshold Coalescing - FCRTC (0x2170; R/W) — Intel® 82580EB/82580DB GbE
Controller
7.15.6
Field
Reserved
Flow Control Receive Threshold Coalescing - FCRTC
(0x2170; R/W)
Bit(s)
3:0
Initial Value
0x0
Description
Reserved
Write 0 ignore on read.
RTH_Coal
17:4
0x0
Flow control Receive Threshold High watermark value used to generate XOFF flow
control packet when executing DMA coalescing, internal transmit fifo is empty and
Transmit Flow control is enabled (CTRL.TFCE = 1b). When previous conditions exist a
XOFF packet is sent if the occupied space in the RX packet buffer is more or equal to
this watermark.
This field is in 16 bytes granularity.
See Section 3.5.5.3.1 for calculation of FCRTH0.RTH_Coal value.
Notes:
1.
To avoid sending XOFF flow control packets needlessly when executing DMA
Coalescing and internal transmit buffer is empty, value should be higher than
threshold defined in DMACR.DMACTHR field. Maximum threshold value can be up
to FCRTH0.RTH + maximum allowable packet size * 1.25.
2.
RTH_Coal threshold value is used as watermark for sending flow control packets
when DMA Coalescing is enabled and internal transmit buffer is empty.
3.
Value programmed should be greater than Maximum packet size.
Reserved
31:18
0x0
Reserved
Write 0 ignore on read.
7.15.7
Field
LTRV
Latency Tolerance Reporting (LTR) Minimum Values LTRMINV (0x5BB0; R/W)
Bit(s)
9:0
Initial Value
0x5
Description
Latency Tolerance Value
Field indicates latency tolerance supported when conditions for minimum latency
tolerance exist (See Section 5.8).
LTRV values are multiplied by 32,768ns or 1,024ns depending on the Scale field, to
indicate latency tolerance supported in nanoseconds. A value of 0 indicates that the
device will be impacted by any delay and that best possible service is requested.
the 82580EB/DB reports the same value for both Snoop and No Snoop requirements.
If no memory latency requirement exists for either Snoop or No Snoop accesses the
appropriate Requirement bit is cleared.
Note: Software should subtract time required to move from L1 to L0 from LTR value.
Scale
12:10
011b
Latency Scale
This field provides a scale for the value contained within the LTRV field.
Encoding:
010 – LTRV value times 1,024ns
011 – LTRV value times 32,768ns
Others - Reserved
Reserved
14:13
0x0
Reserved
Write 0 ignore on read.
Revision: 2.50
October 2011
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Intel® 82580EB/82580DB GbE Controller — Latency Tolerance Reporting (LTR) Maximum Values LTRMAXV (0x5BB4; R/W)
Field
Bit(s)
LSNP
Requirement
15
Reserved
30:16
Initial Value
0b
Description
LTR Snoop requirement
0 - No Latency requirements in Snoop memory access.
1 - Maximum latency tolerance in Snoop memory access specified in LTRV field.
0x0
Reserved
Write 0 ignore on read.
LNSNP
Requirement
31
0b
LTR Non-Snoop Requirement
0 - No Latency requirements in Non-Snoop memory access.
1 - Maximum latency tolerance in Non-Snoop memory access specified in LTRV field.
7.15.8
Latency Tolerance Reporting (LTR) Maximum Values LTRMAXV (0x5BB4; R/W)
Field
LTRV
Bit(s)
9:0
Initial Value
0x5
Description
Latency Tolerance Value
Field indicates latency tolerance supported when conditions for maximum latency
tolerance exist (See Section 5.8).
LTRV values are multiplied by 32,768ns or 1,024ns depending on the Scale field, to
indicate latency tolerance supported in nanoseconds. A value of 0 indicates that the
device will be impacted by any delay and that best possible service is requested.
the 82580EB/DB reports the same value for both Snoop and No Snoop requirements.
If no memory latency requirement exists for either Snoop or No Snoop accesses the
appropriate Requirement bit is cleared.
Note: Software should subtract time required to move from L1 to L0 from LTR value.
Scale
12:10
011b
Latency Scale
This field provides a scale for the value contained within the LTRV field.
Encoding:
010 – LTRV value times 1,024ns
011 – LTRV value times 32,768ns
Others - Reserved
Reserved
14:13
0x0
Reserved
Write 0 ignore on read.
LSNP
Requirement
15
Reserved
30:16
0b
LTR Snoop requirement
0 - No Latency requirements in Snoop memory access.
1 - Maximum latency tolerance in Snoop memory access specified in LTRV field.
0x0
Reserved
Write 0 ignore on read.
LNSNP
Requirement
31
0b
LTR Non-Snoop Requirement
0 - No Latency requirements in Non-Snoop memory access.
1 - Maximum latency tolerance in Non-Snoop memory access specified in LTRV field.
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Latency Tolerance Reporting (LTR) Control - LTRC (0x01A0; R/W) — Intel® 82580EB/82580DB GbE
Controller
7.15.9
Latency Tolerance Reporting (LTR) Control - LTRC
(0x01A0; R/W)
Field
Bit(s)
Initial Value
Description
Reserved
0
0b
Reserved
LTR_MIN
1
0b
LTR Send Minimum Values
When set to 1 the 82580EB/DB sends a PCIe LTR message with the LTR Snoop value,
LTR No-snoop value and LTR requirement bits as defined in the LTRMINV register.
Note: To resend LTR message with minimum value, bit should be cleared and set
again. LTR_MIN and LTR_MAX bits are exclusive.
LTR_MAX
2
0b
LTR Send Maximum Values
When set to 1 the 82580EB/DB sends a PCIe LTR message with the LTR Snoop value,
LTR No-snoop value and LTR requirement bits as defined in the LTRMAXV register.
Note: To resend LTR message with maximum value, bit should be cleared and set
again. LTR_MIN and LTR_MAX bits are exclusive.
PDLS_EN
3
1b
Port Disable LTR send enable
0 - Do not issue PCIe LTR message with requirement bits cleared on port disable.
1 - Issue PCIe LTR message with requirement bits cleared on port disable.
LNKDLS_EN
4
1b
Link Disconnect LTR send enable
0 - Do not issue PCIe LTR message with requirement bits cleared on link disconnect.
1 - Issue PCIe LTR message with requirement bits cleared on link disconnect.
Reserved
31:5
0x0
Reserved
Write 0 ignore on read.
7.16
Timer Registers Description
7.16.1
Watchdog Setup - WDSTP (0x1040; R/W)
Field
Bit(s)
Initial Value
Description
WD_Enable
0
0b1
Enable Watchdog Timer
WD_Timer_
Load_enable
(SC)
1
0b
Enables the load of the watchdog timer by writing to WD_Timer field. If this bit is not
set, the WD_Timer field is loaded by the value of WD_Timeout.
Reserved
15:2
0x0
Reserved
WD_Timer
(RWS)
23:16
WD_Timeout
Indicates the current value of the timer. Resets to the timeout value each time the
82580EB/DB functional bit in Software Device Status register is set. If this timer
expires, the WD interrupt to the firmware and the WD SDP is asserted. As a result, this
timer is stuck at zero until it is re-armed.
WD_Timeout
31:24
0x01
Defines the number of seconds until the watchdog expires. The granularity of this timer
is 1 sec. The minimal value allowed for this register when the watchdog mechanism is
enabled is two. Setting this field to 1b might cause the watchdog to expire
immediately.
Note: Writing to this field is only for DFX purposes.
Note: Writing to this field is only for DFX purposes.
Note: Only 4 LSB bits loaded from EEPROM. Initial value of 4 MSB bits is 0000b.
1. Value read from the EEPROM.
Revision: 2.50
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Intel® 82580EB/82580DB GbE Controller — Watchdog Software Device Status - WDSWSTS (0x1044; R/
W)
7.16.2
Watchdog Software Device Status - WDSWSTS (0x1044;
R/W)
Field
Bit(s)
Initial Value
Description
Dev_Function 0
al (SC)
0b
Each time this bit is set, the watchdog timer is re-armed.
Force_WD
(SC)
1
0b
Reserved
23:2
0x0
Reserved
0x0
This field can be used by software to indicate to the firmware the reason the 82580EB/
DB is malfunctioning. The encoding of this field is software/firmware dependent. A
value of 0 indicates a functional the 82580EB/DB.
This bit is self clearing
Setting this bit causes the WD timer to expire immediately. The WD_timer field is set
to 0b. It can be used by software in order to indicate some fatal error detected in the
software or in the hardware.
This bit is self clearing.
Stuck Reason 31:24
7.16.3
Free Running Timer - FRTIMER (0x1048; RWS)
This register reflects the value of a free running timer that can be used for various timeout indications.
The register is reset by a PCI reset and/or software reset.
Note:
Writing to this register is for DFX purposes only.
Field
Bit(s)
Initial Value
Description
Microsecond
9:0
X
Number of microseconds in the current millisecond.
Millisecond
19:10
X
Number of milliseconds in the current second.
Seconds
31:20
X
Number of seconds from the timer start (up to 4095 seconds).
7.16.4
TCP Timer - TCPTIMER (0x104C; R/W)
Field
Duration
Bit(s)
7:0
Initial Value
0x0
Description
Duration
Duration of the TCP interrupt interval in msec.
KickStart (WS)
8
0b
Counter Kick-Start
Writing a 1b to this bit kick-starts the counter down-count from the initial
value defined in the Duration field. Writing a 0b has no effect.
TCPCountEn
9
0b
TCP Count Enable
1b = TCP timer counting enabled.
0b = TCP timer counting disabled.
Once enabled, the TCP counter counts from its internal state. If the
internal state is equal to 0b, the down-count does not restart until
KickStart is activated. If the internal state is not 0b, the down-count
continues from internal state.
This enables a pause in the counting for debug purpose.
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Time Sync Register Descriptions — Intel® 82580EB/82580DB GbE Controller
Field
Bit(s)
TCPCountFinish (WS)
10
Initial Value
0b
Description
TCP Count Finish
This bit enables software to trigger a TCP timer interrupt, regardless of the
internal state.
Writing a 1b to this bit triggers an interrupt and resets the internal counter
to its initial value. Down-count does not restart until either KickStart is
activated or Loop is set.
Writing a 0b has no effect.
Loop
11
0b
TCP Loop
When set to 1b, the TCP counter reloads duration each time it reaches
zero, and continues down-counting from this point without kick-starting.
When set to 0b, the TCP counter stops at a zero value and does not restart until KickStart is activated.
Note: Setting this bit alone is not enough to start the timer activity. The
KickStart bit should also be set.
Reserved
31:12
-
Reserved
7.17
Time Sync Register Descriptions
7.17.1
RX Time Sync Control register - TSYNCRXCTL
(0xB620;RW)
Field
Bit(s)
Initial Value
RXTT(RO/V)
0
0x0
Description
Rx timestamp valid
Bit is set when a valid value for Rx timestamp is captured in the Rx timestamp
registers. Bit is cleared by read of Rx timestamp high register (RXSTMPH)).
Revision: 2.50
October 2011
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Intel® 82580EB/82580DB GbE Controller — RX timestamp Low - RXSTMPL (0xB624; RO)
Field
Bit(s)
Initial Value
Type
3:1
0x0
Description
Type of packets to timestamp 000b – time stamp L2 (V2) packets only (Sync or Delay_req depends on message
type in Section 7.17.26 and packets with Pdelay_Req and Pdelay_Resp message ID
values)
001b – time stamp L4 (V1) packets only (Sync or Delay_req depends on message
type in Section 7.17.26)
010b – time stamp V2 (L2 and L4) packets (Sync or Delay_req depends on message
type in Section 7.17.26 and packets with Pdelay_Req and Pdelay_Resp message ID
values)
100b – time stamp all packets.
In this mode no locking is done to the timestamp value in the RXSTMPL/H timestamp
registers, the RDESC.STATUS.TS bit in the receive descriptor stays 0, while the
RDESC.STATUS.TSIP bit in the receive descriptor is always 1 if placing timestamp in
receive buffer is enabled (See Section 8.1.10).
101b - Time stamp all packets which have a Message Type bit 3 zero, which means
timestamp all event packets. This is applicable for V2 packets only.
011b, 110b and 111b – reserved
Note: Field is also used for defining packets that have timestamp captured in receive
buffer (See Section 8.1.10).
En
4
0b
Enable RX timestamp
0 = time stamping disabled.
1 = time stamping enabled.
RSV
7.17.2
31:6
0x0
Reserved
RX timestamp Low - RXSTMPL (0xB624; RO)
Field
Bit(s)
Initial Value
RTSL
31:0
0x0
Description
Rx timestamp LSB value
Value in 1 nS resolution.
7.17.3
RX timestamp High - RXSTMPH (0xB628; RO)
Field
Bit(s)
Initial Value
RTSH
7:0
0x0
Description
Rx timestamp MSB value
Value in 232 nS resolution.
Reserved
7.17.4
31:8
0x0
Reserved.
RX timestamp attributes low - RXSATRL(0xB62C; RO)
Field
Bit(s)
Initial Value
SourceIDL
31:0
0x0
Intel® 82580EB/82580DB Gigabit Ethernet Controller
Datasheet
374
Description
Sourceuuid low
Revision: 2.50
October 2011
RX timestamp attributes high- RXSATRH (0xB630; RO) — Intel® 82580EB/82580DB GbE Controller
7.17.5
Field
RX timestamp attributes high- RXSATRH (0xB630; RO)
Bit(s)
Initial Value
SourceIDH
15:0
0x0
Sourceuuid high
SequenceID
31:16
0x0
SequenceId
7.17.6
Description
TX Time Sync Control register - TSYNCTXCTL (0xB614;
RW)
Field
Bit(s)
Initial Value
Description
TXTT(RO/V)
0
0b
Transmit timestamp valid (equals 1b when a valid value for Tx timestamp is captured
in the Tx timestamp register, clear by read of Tx timestamp register TXSTMPH)
RSV
3:1
0x0
EN
4
0b
Reserved
Enable Transmit timestamp
0b = time stamping disabled.
1b = time stamping enabled.
RSV
7.17.7
31:5
0x0
Reserved
TX timestamp value Low - TXSTMPL (0xB618;RO)
Field
Bit(s)
Initial Value
TTSL
31:0
0x0
Description
Transmit timestamp LSB value
Value in 1 nS resolution.
7.17.8
TX Timestamp Value High - TXSTMPH(0xB61C; RO)
Field
Bit(s)
Initial Value
TTSH
7:0
0x0
Description
Transmit timestamp MSB value
Value in 232 nS resolution.
Reserved
31:8
0x0
Reserved
Write 0 ignore on read.
7.17.9
System Time Register Residue - SYSTIMR (0xB6F8; RW)
Field
Bit(s)
Initial Value
STR
31:0
0x0
Description
System time Residue value.
Value in 2-32 nS resolution.
Revision: 2.50
October 2011
Intel® 82580EB/82580DB Gigabit Ethernet Controller
Datasheet
375
Intel® 82580EB/82580DB GbE Controller — System Time Register Low - SYSTIML (0xB600; RW)
7.17.10
System Time Register Low - SYSTIML (0xB600; RW)
Field
Bit(s)
Initial Value
STL
31:0
0x0
Description
System time LSB value
Value in 1 nS resolution.
7.17.11
System Time Register High - SYSTIMH (0xB604; RW)
Field
Bit(s)
Initial Value
STH
7:0
0x0
Description
System time MSB value
Value in 232 nS resolution.
Reserved
31:8
0x0
Reserved
Write 0 ignore on read.
7.17.12
Increment Attributes Register - TIMINCA (0xB608; RW)
Field
Bit(s)
Initial Value
Incvalue
30:0
0x0
Description
Increment value.
Value to be added or subtracted (depending on ISGN value) from 8 nS clock
cycle in resolution of 2-32 nS.
ISGN
31
0b
Increment sign.
0 - Each 8 nS cycle add to SYSTIM a value of 8 nS + Incvalue * 2-32 nS.
1 - Each 8 nS cycle add to SYSTIM a value of 8 nS -Incvalue * 2-32 nS.
7.17.13
Time Adjustment Offset Register Low - TIMADJL (0xB60C;
RW)
Field
Bit(s)
Initial Value
TADJL
31:0
0x0
Description
Time adjustment value Low
Value in 1 nS resolution.
Intel® 82580EB/82580DB Gigabit Ethernet Controller
Datasheet
376
Revision: 2.50
October 2011
Time Adjustment Offset Register High - TIMADJH (0xB610;RW) — Intel® 82580EB/82580DB GbE
Controller
7.17.14
Time Adjustment Offset Register High - TIMADJH
(0xB610;RW)
Field
Bit(s)
Initial Value
TADJH
7:0
0x0
Description
Time adjustment value High
Value in 232 resolution.
Software write to TIMADJH register increases or reduces system time value
(SYSTIMH, SYSTIML), depending on TIMADJH.Sign bit, by the time
adjustment value (TIMADJH, TIMADJL).
Reserved
30:8
0x0
Reserved.
Write 0 ignore on read.
Sign
7.17.15
31
0b
Sign (0b=”+”, 1b =”-“)
TimeSync Auxiliary control register - TSAUXC (0xB640;
RW)
Field
Bit(s)
Initial Value
EN_TT0
0
0b
Description
Enable target time 0.
Enable bit is set by software to 1b, to enable pulse or level change generation as a
function of the TSAUXC.PLSG0 and TSAUXC.PLSNeg0 bits. The bit is cleared by
hardware when the target time is hit and Pulse or level change occurs.
EN_TT1
1
0b
Enable target time 1.
Enable bit is set by software to 1b, to enable pulse or level change generation as a
function of the TSAUXC.PLSG1 and TSAUXC.PLSNeg1 bits. The bit is cleared by
hardware when the target time is hit and Pulse or level change occurs.
EN_CLK0
2
0b
Enable Configurable Frequency Clock 0
Clock is generated according to frequency defined in the FREQOUT0 register on the
SDP pin (0 to 3) that has both:
1. TSSDP.TS_SDPx_SEL field with a value of 10b.
2. TSSDP.TS_SDPx_EN value of 1b.
Reserved
3
0b
ST0
4
0b
Reserved
Start Clock 0 Toggle on Target Time 0
Enable Clock 0 toggle only after target time 0, that’s defined in the TRGTTIML0 and
TRGTTIMH0 registers, has passed. The clock output is initially 0 and toggles with a
frequency defined in the FREQOUT0 register.
EN_CLK1
5
0b
Enable Configurable Frequency Clock 1
Clock is generated according to frequency defined in the FREQOUT1 register on the
SDP pin (0 to 3) that has both:
1. TSSDP.TS_SDPx_SEL field with a value of 11b.
2. TSSDP.TS_SDPx_EN value of 1b.
Reserved
6
0b
Reserved
ST1
7
0b
Start Clock 1 Toggle on Target Time 1
Enable Clock 1 toggle only after Target Time 1, that’s defined in the TRGTTIML1 and
TRGTTIMH1 registers, has passed. The clock output is initially 1 and toggles with a
frequency defined in the FREQOUT1 register
Revision: 2.50
October 2011
Intel® 82580EB/82580DB Gigabit Ethernet Controller
Datasheet
377
Intel® 82580EB/82580DB GbE Controller — Target Time Register 0 Low - TRGTTIML0 (0xB644; RW)
Field
Bit(s)
Initial Value
EN_TS0
8
0b
Description
Enable hardware time stamp 0
Enable Time stamping occurrence of change in SDP pin into the AUXSTMPL0 and
AUXSTMPH0 registers.
SDP pin (0 to 3) is selected for time stamping, if the SDP pin is selected via the
TSSDP.AUX0_SDP_SEL field and the TSSDP.AUX0_TS_SDP_EN bit is set to 1b.
AUTT0
9
0b
EN_TS1
10
0b
Auxiliary timestamp taken - cleared when read from auxiliary timestamp 0 occurred
Enable hardware time stamp 1
Enable Time stamping occurrence of change in SDP pin into the AUXSTMPL1 and
AUXSTMPH1 registers.
SDP pin (0 to 3) is selected for time stamping, if the SDP pin is selected via the
TSSDP.AUX1_SDP_SEL field and the TSSDP.AUX1_TS_SDP_EN bit is set to 1b.
AUTT1
11
0b
Reserved
16:12
0x0
Auxiliary timestamp taken - cleared when read from auxiliary timestamp 1 occurred
PLSG0
17
0b
Reserved
Use Target Time 0 to generate start of pulse and Target Time 1 to generate end of
pulse. SDP pin selected to drive pulse or level change is set according to the
TSSDP.TS_SDPx_SEL field with a value of 00b and TSSDP.TS_SDPx_EN bit with a value
of 1b.
0 – Target Time 0 generates change in SDP level.
1 – Target time 0 generates start of pulse on SDP pin.
Note: Pulse or level change is generated when TSAUXC.EN_TT0 is set to 1.
Generate Negative pulse on Target Time 0 when PLSG0 is 1.
—
PLSNeg0
—
18
—
0b
0 – Generate positive pulse on Target Time 0 when PLSG0 is 1.
1 – Generate Negative pulse on target time 0 when PLSG0 is 1.
Note: If PLSNeg0 = 1, at start the selected SDP pin is set to 1.
—
PLSG1
—
19
—
0b
Use Target Time 1 to generate start of pulse and Target Time 0 to generate end of
pulse. SDP pin selected to drive pulse or level change is set according to the
TSSDP.TS_SDPx_SEL field with a value of 01b and TSSDP.TS_SDPx_EN bit with a
value of 1b.
0 – Target Time 1 generates change in SDP level.
1 – Target time 1 generates start of pulse on SDP pin.
Note: Pulse or level change is generated when TSAUXC.EN_TT1 is set to 1.
Generate Negative pulse on Target Time 1 when PLSG1 is 1.
—
PLSNeg1
—
20
—
0b
0 – Generate positive pulse on Target Time 1when PLSG1 is 1.
1 – Generate Negative pulse on target time 1 when PLSG1 is 1.
Note: If PLSNeg1 = 1, at start the selected SDP pin is set to 1.
—
Reserved
—
30:21
—
0x0
Reserved
Write 0, ignore on read
Disable SYSTIM count operation
—
Disable
sy
sti
me
7.17.16
—
31
—
1b
0b - SYSTIM timer activated
1b - SYSTIM timer disabled. Value of SYSTIMH, SYSTIML and SYSTIMR remains
constant.
Target Time Register 0 Low - TRGTTIML0 (0xB644; RW)
Field
Bit(s)
Initial Value
TTL
31:0
0x0
Description
Target Time 0 LSB register
Value in 1 nS resolution.
Intel® 82580EB/82580DB Gigabit Ethernet Controller
Datasheet
378
Revision: 2.50
October 2011
Target Time Register 0 High - TRGTTIMH0 (0xB648; RW) — Intel® 82580EB/82580DB GbE Controller
7.17.17
Target Time Register 0 High - TRGTTIMH0 (0xB648; RW)
Field
Bit(s)
Initial Value
TTH
7:0
0x0
Description
Target Time 0 MSB register
Value in 232 nS resolution.
Reserved
31:8
0x0
Reserved
Write 0 ignore on read.
7.17.18
Target Time Register 1 Low - TRGTTIML1 (0xB64C; RW)
Field
Bit(s)
Initial Value
TTL
31:0
0x0
Description
Target Time 1 LSB register
Value in 1 nS resolution.
7.17.19
Target Time Register 1 High - TRGTTIMH1 (0xB650; RW)
Field
Bit(s)
Initial Value
TTH
7:0
0x0
Description
Target Time 1 MSB register
Value in 232 nS resolution.
Reserved
31:8
0x0
Reserved
Write 0 ignore on read.
7.17.20
Frequency Out 0 Control Register FREQOUT0 (0xB654;
RW)
Field
Bit(s)
Initial Value
CHCT
7:0
0x0
Description
Clock Out Half Cycle Time
Half Cycle time of Clock 0 in 8 nS resolution.
Clock is generated on SDP pin when TSAUXC.EN_CLK0 is set to 1. SDP pin
(0 to 3) that drives Clock 0 is selected according to the
TSSDP.TS_SDPx_SEL field that has a value of 10b and a
TSSDP.TS_SDPx_EN value of 1b.
If TSAUXC.ST0 is set to 1, start of clock toggle is defined by Target Time 0
(TRGTTIML0 and TRGTTIMH0) registers.
Notes:
1. Setting this register to zero while using the frequency out feature, is
illegal.
2. Clock 0 generation should not be enabled so long as absolute value of
SYSTIM error correction using the TRGTTIMH0 and TRGTTIML0
registers is greater then 2 msec.
Reserved
31:8
0x0
Reserved
Write 0 ignore on read.
Revision: 2.50
October 2011
Intel® 82580EB/82580DB Gigabit Ethernet Controller
Datasheet
379
Intel® 82580EB/82580DB GbE Controller — Frequency Out 1 Control Register - FREQOUT1 (0xB658;
RW)
7.17.21
Frequency Out 1 Control Register - FREQOUT1 (0xB658;
RW)
Field
Bit(s)
Initial Value
CHCT
7:0
0x0
Description
Clock Out Half Cycle Time
Half Cycle time of Clock 1 in 8 nS resolution.
Clock is generated on SDP pin when TSAUXC.EN_CLK1 is set to 1. SDP pin
(0 to 3) that drives Clock 1 is selected according to the
TSSDP.TS_SDPx_SEL field that has a value of 11b and a
TSSDP.TS_SDPx_EN value of 1b.
If TSAUXC.ST1 is set to 1, start of clock toggle is defined by Target Time 1
(TRGTTIML1 and TRGTTIMH1) registers.
Notes:
1. Setting this register to zero while using the frequency out feature, is
illegal.
2. Clock 1 generation should not be enabled so long as absolute value of
SYSTIM error correction using the TRGTTIMH1 and TRGTTIML1
registers is greater then 2 msec.
Reserved
31:8
0x0
Reserved
Write 0 ignore on read.
7.17.22
Auxiliary Time Stamp 0 Register Low - AUXSTMPL0
(0xB65C; RO)
Field
Bit(s)
Initial Value
TSTL
31:0
0x0
Description
Auxiliary Time Stamp 0 LSB value
Value in 1 nS resolution.
7.17.23
Auxiliary Time Stamp 0 Register High -AUXSTMPH0
(0xB660; RO)
Reading this register will release the value stored in AUXSTMPH/L0 and will allow time stamping of the
next value.
Field
Bit(s)
Initial Value
TSTH
7:0
0x0
Description
Auxiliary Time Stamp 0 MSB value
Value in 232 nS resolution.
Reserved
31:8
0x0
Reserved
Write 0 ignore on read.
Intel® 82580EB/82580DB Gigabit Ethernet Controller
Datasheet
380
Revision: 2.50
October 2011
Auxiliary Time Stamp 1 Register Low AUXSTMPL1 (0xB664; RO) — Intel® 82580EB/82580DB GbE
Controller
7.17.24
Auxiliary Time Stamp 1 Register Low AUXSTMPL1
(0xB664; RO)
Field
Bit(s)
Initial Value
TSTL
31:0
0x0
Description
Auxiliary Time Stamp 1 LSB value
Value in 1 nS resolution.
7.17.25
Auxiliary Time Stamp 1 Register High - AUXSTMPH1
(0xB668; RO)
Reading this register will release the value stored in AUXSTMPH/L1 and will allow stamping of the next
value.
Field
Bit(s)
Initial Value
TSTH
7:0
0x0
Description
Auxiliary Time Stamp 1 MSB value
Value in 232 nS resolution.
Reserved
31:8
0x0
Reserved
Write 0 ignore on read.
7.17.26
Field
Time Sync RX Configuration - TSYNCRXCFG (0x5F50; R/W)
Bit(s)
Initial Value
Description
CTRLT
7:0
0x0
V1 control to timestamp
MSGT
15:8
0x0
V2 Message Type to timestamp
Reserved
31:16
0x0
Reserved
7.17.27
Time Sync SDP Configuration Register - TSSDP (0x003C;
R/W)
This register defines the assignment of SDP pins to the Time sync auxiliary capabilities.
Revision: 2.50
October 2011
Intel® 82580EB/82580DB Gigabit Ethernet Controller
Datasheet
381
Intel® 82580EB/82580DB GbE Controller — Time Sync SDP Configuration Register - TSSDP (0x003C;
R/W)
Field
AUX0_SDP_SEL
Bit(s)
1:0
Initial Value
00b
Description
Select one of the SDPs to serve as the trigger for auxiliary time stamp 0
(AUXSTMPL0 and AUXSTMPH0 registers)
00b = SDP0 is assigned
01b = SDP1 is assigned
10b = SDP2 is assigned
11b = SDP3 is assigned
AUX0_TS_SDP_EN 2
0b
When set indicates that one of the SDPs can be used as an external trigger to
Aux timestamp 0 (note that if this bit is set to one of the SDP pins, the
corresponding pin should be configured to input mode using SPD_DIR)
AUX1_SDP_SEL
00b
Select one of the SDPs to serve as the trigger for auxiliary time stamp 1 (in
AUXSTMPL1 and AUXSTMPH1 registers)
4:3
00b = SDP0 is assigned
01b = SDP1 is assigned
10b = SDP2 is assigned
11b = SDP3 is assigned
AUX1_TS_SDP_EN 5
0b
When set indicates that one of the SDPs can be used as an external trigger to
Aux timestamp 1 (note that if this bit is set to one of the SDP pins, the
corresponding pin should be configured to input mode using SPD_DIR)
TS_SDP0_SEL
00b
SDP0 allocation to Tsync event – when TS_SDP0_EN is set, these bits select the
Tsync event that is routed to SDP0.
7:6
00b = Target Time 0 is output on SDP0
01b = Target Time 1 is output on SDP0
10b = Freq Clock 0 is output on SDP0
11b = Freq Clock 1 is output on SDP0
TS_SDP0_EN
8
0b
When set indicates that SDP0 is assigned to Tsync.
TS_SDP1_SEL
10:9
00b
SDP1 allocation to Tsync event – when TS_SDP1_EN is set, these bits select the
Tsync event that is routed to SDP1.
00b = Target Time 0 is output on SDP1
01b = Target Time 1 is output on SDP1
10b = Freq Clock 0 is output on SDP1
11b = Freq Clock 1 is output on SDP1
TS_SDP1_EN
11
0b
When set indicates that SDP1 is assigned to Tsync.
TS_SDP2_SEL
13:12
00b
SDP2 allocation to Tsync event – when TS_SDP2_EN is set, these bits select the
Tsync event that is routed to SDP2.
00b = Target Time 0 is output on SDP2
01b = Target Time 1 is output on SDP2
10b = Freq Clock 0 is output on SDP2
11b = Freq Clock 1 is output on SDP2
TS_SDP2_EN
14
0b
When set indicates that SDP2 is assigned to Tsync.
TS_SDP3_SEL
16:15
00b
SDP3 allocation to Tsync event – when TS_SDP3_EN is set, these bits select the
Tsync event that is routed to SDP3.
00b = Target Time 0 is output on SDP3
01b = Target Time 1 is output on SDP3
10b = Freq Clock 0 is output on SDP3
11b = Freq Clock 1 is output on SDP3
TS_SDP3_EN
17
0b
When set indicates that SDP3 is assigned to Tsync.
Reserved
31:18
0x0
Reserved
Intel® 82580EB/82580DB Gigabit Ethernet Controller
Datasheet
382
Revision: 2.50
October 2011
Time Sync Interrupt Registers — Intel® 82580EB/82580DB GbE Controller
7.17.28
Time Sync Interrupt Registers
7.17.28.1
Note:
Time Sync Interrupt Cause Register - TSICR (0xB66C; RC/
W1C)
Value of register is always read as 0x0. Once ICR.Time_Sync is set, internal value of
register should be cleared by write 1 to all bits or cleared by read to enable reception of an
additional ICR.Time_Sync interrupt.
Field
Bit(s)
Initial Value
SYS WARP
0
0b
Description
SYSTIM Warp around.
Set when SYSTIM Warp Around occurs. Warp around occurrence can be
used by Software to update software time sync time.
TXTS
1
0b
RXTS
2
0b
Transmit Time Stamp
Set when new timestamp is loaded into TXSTMP register
Receive Time Stamp
Set when new timestamp is loaded into RXSTMP register
TT0
3
0b
TT1
4
0b
Target time 0 trigger.
Set when Target Time 0 (TRGTTIML/H0) trigger occurs.
Target time 1 trigger.
Set when Target Time 1 (TRGTTIML/H1) trigger occurs.
AUTT0
5
0b
Auxiliary timestamp 0 taken.
Set when new timestamp is loaded into AUXSTMP 0 (auxiliary timestamp
0) register.
AUTT1
6
0b
Auxiliary timestamp 1 taken.
Set when new timestamp is loaded into AUXSTMP 1 (auxiliary timestamp
1) register.
TADJ
7
0b
Reserved
31:8
0x0
Time Adjust 0 done
Set when Time Adjust to clock out 0 or 1 completed
Reserved.
Write 0, ignore on read.
Revision: 2.50
October 2011
Intel® 82580EB/82580DB Gigabit Ethernet Controller
Datasheet
383
Intel® 82580EB/82580DB GbE Controller — Time Sync Interrupt Registers
7.17.28.2
Time Sync Interrupt Mask Register - TSIM (0xB674; RW)
Field
Bit(s)
Initial Value
SYS WARP
0
0b
Description
SYSTIM Warp around Mask
0 – No Interrupt generated when TSICR.SWARP is set.
1 – Interrupt generated when TSICR.SWARP is set.
TXTS
1
0b
Transmit Time Stamp Mask
0 – No Interrupt generated when TSICR.TXTS is set.
1 – Interrupt generated when TSICR.TXTS is set.
RXTS
2
0b
Receive Time Stamp Mask
0 – No Interrupt generated when TSICR.RXTS is set.
1 – Interrupt generated when TSICR.RXTS is set.
TT0
3
0b
Target time 0 Trigger Mask
0 – No Interrupt generated when TSICR.TT0 is set.
1 – Interrupt generated when TSICR.TT0 is set.
TT1
4
0b
Target time 1 Trigger Mask
0 – No Interrupt generated when TSICR.TT1 is set.
1 – Interrupt generated when TSICR.TT1 is set.
AUTT0
5
0b
Auxiliary timestamp 0 taken Mask
0 – No Interrupt generated when TSICR.AUTT0 is set.
1 – Interrupt generated when TSICR.AUTT0 is set.
AUTT1
6
0b
Auxiliary timestamp 1 taken Mask
0 – No Interrupt generated when TSICR.AUTT1 is set.
1 – Interrupt generated when TSICR.AUTT1 is set.
TADJ
7
0b
Time Adjust 0 done mask
0 – No Interrupt generated when TSICR.TADJ is set.
1 – Interrupt generated when TSICR.TADJ is set.
Reserved
31:8
0x0
Reserved.
Write 0, ignore on read.
7.17.28.3
Time Sync Interrupt Set Register - TSIS (0xB670; WO)
TSIS register is Write Only. Writing 1 to a bit sets respective interrupt bit in TSICR register. Write
operation causes a single interrupt event and bit is cleared internally.
Field
Bit(s)
Initial Value
SYS WARP
(SC)
0
0b
Description
Set SYSTIM Warp Around Interrupt
0 – No TSICR.SWARP Interrupt set.
1 – TSICR.SWARP interrupt set.
TXTS (SC)
1
0b
Set Transmit Time Stamp Interrupt
0 – No TSICR.TXTS Interrupt set.
1 –TSICR.TXTS interrupt set.
RXTS (SC)
2
0b
Set Receive Time Stamp Interrupt
0 – No TSICR.RXTS Interrupt set.
1 – TSICR.RXTS Interrupt set.
Intel® 82580EB/82580DB Gigabit Ethernet Controller
Datasheet
384
Revision: 2.50
October 2011
PCS Register Descriptions — Intel® 82580EB/82580DB GbE Controller
Field
Bit(s)
Initial Value
TT0 (SC)
3
0b
Description
Set Target Time 0 Trigger Interrupt
0 – No TSICR.TT0 Interrupt set.
1 – TSICR.TT0 Interrupt set.
TT1 (SC)
4
0b
Set Target Time 1 Trigger Interrupt
0 – No TSICR.TT1 Interrupt set.
1 – TSICR.TT1 Interrupt set.
AUTT0 (SC)
5
0b
Set Auxiliary Timestamp 0 Taken Interrupt
0 – No TSICR.AUTT0 Interrupt set.
1 – TSICR.AUTT0 Interrupt set.
AUTT1 (SC)
6
0b
Set Auxiliary Timestamp 1 Taken Interrupt
0 – No TSICR.AUTT1 Interrupt set.
1 – TSICR.AUTT1 Interrupt set.
TADJ (SC)
7
0b
Set Time Adjust 0 done Interrupt
0 – No TSICR.TADJ interrupt set.
1 – TSICR.TADJ interrupt set.
Reserved
31:8
0x0
Reserved.
Write 0, ignore on read.
7.18
PCS Register Descriptions
These registers are used to configure the SerDes, SGMII and 1000BASE-KX PCS logic. Usage of these
registers is described in Section 3.5.4.1 & Section 3.5.4.3.
7.18.1
PCS Configuration - PCS_CFG (0x4200; R/W)
Field
Bit(s)
Initial Value
Description
Reserved
2:0
000b
Reserved
PCS Enable
3
1b
PCS Enable
Enables the PCS logic of the MAC. Should be set in SGMII, 1000BASE-KX and SerDes
mode for normal operation.
Clearing this bit disables RX/TX of both data and control codes. Use this to force link
down at the far end.
Reserved
29:4
0x0
Reserved
PCS Isolate
30
0b
PCS Isolate
Setting this bit isolates the PCS logic from the MAC's data path. PCS control codes are
still sent and received.
SRESET
31
0b
Soft Reset
Setting this bit puts all modules within the MAC in reset except the Host Interface.
The Host Interface is reset via HRST. This bit is NOT self clearing; GMAC is in a reset
state until this bit is cleared.
Revision: 2.50
October 2011
Intel® 82580EB/82580DB Gigabit Ethernet Controller
Datasheet
385
Intel® 82580EB/82580DB GbE Controller — PCS Link Control - PCS_LCTL (0x4208; RW)
7.18.2
PCS Link Control - PCS_LCTL (0x4208; RW)
Field
FLV
Bit(s)
0
Initial Value
0b
Description
Forced Link Value
This bit denotes the link condition when force link is set.
0b = Forced link down.
1b = Forced link up.
FSV
2:1
10b
Forced Speed Value
These bits denote the speed when force speed and duplex is set. This value is also
used when AN is disabled or when in SerDes mode.
00b = 10 Mb/s (SGMII).
01b = 100 Mb/s (SGMII).
10b = 1000 Mb/s (SerDes/SGMII/1000BASE-KX).
11b = Reserved.
FDV
3
1b
Forced Duplex Value
This bit denotes the duplex mode when force speed and duplex is set. This value is also
used when AN is disabled or when in SerDes mode.
1b = Full duplex (SerDes/SGMII/1000BASE-KX).
0b = Half duplex (SGMII).
FSD
4
0b
Force Speed and Duplex
If this bit is set, then speed and duplex mode is forced to forced speed value and
forced duplex value, respectively. Otherwise, speed and duplex mode are decided by
internal AN/SYNC state machines.
Force Link
5
0b
Force Link
If this bit is set, then the internal LINK_OK variable is forced to forced link value (bit 0
of this register).
Otherwise, LINK_OK is decided by internal AN/SYNC state machines.
LINK LATCH
LOW (LL)
6
0b
Link Latch Low Enable
Force Flow
Control
7
Reserved
15:8
-
Reserved
AN_ENABLE
16
0b1
AN Enable
If this bit is set, then link OK going LOW (negative edge) is latched until a processor
read. Afterwards, link OK is continuously updated until link OK again goes LOW
(negative edge is seen).
0b
0 = Flow control mode is set according to the AN process by following Table 37-4 in
the IEEE 802.3 spec.
1 = Flow control is set according to FC_TX_EN / FC_RX_EN bits in CTRL register.
Setting this bit enables the AN process in SerDes operating mode.
Notes:
1.
When link-up is forced (CTRL.SLU=1) the AN_ENABLE bit should be 0.
2.
Initial value loaded from ANE EEPROM bit (See Section 6.2.8).
AN RESTART
(SC)
17
0b
AN Restart
Used to reset/restart the link auto-negotiation process when using SerDes mode.
Setting this bit restarts the Auto-negotiation process.
This bit is self clearing.
Intel® 82580EB/82580DB Gigabit Ethernet Controller
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PCS Link Status - PCS_LSTS (0x420C; RO) — Intel® 82580EB/82580DB GbE Controller
Field
Bit(s)
AN TIMEOUT
EN
18
AN SGMII
BYPASS
19
AN SGMII
TRIGGER
20
Initial Value
1b1
Description
AN Timeout Enable
This bit enables the AN Timeout feature. During AN, if the link partner does not
respond with AN pages, but continues to send good IDLE symbols, then LINK UP is
assumed. (This enables LINK UP condition when link partner is not AN-capable and
does not affect otherwise).
Notes:
1.
This bit should not be set in SGMII mode.
2.
Initial value loaded from PCS parallel detect EEPROM bit (See Section 6.2.8).
0b
AN SGMII Bypass
If this bit is set, then IDLE detect state is bypassed during AN in SGMII mode. This
reduces the acknowledge time in SGMII mode.
0B
AN SGMII Trigger
If this bit is cleared, then AN is not automatically triggered in SGMII mode even if
SYNC fails. AN is triggered only in response to PHY messages or by a manual setting
like changing the AN Enable/Restart bits.
Reserved
23:21
000b
Reserved
FAST LINK
TIMER
24
0b
Fast Link Timer
LINK OK FIX
EN
25
1b
Reserved
26
0b
Reserved
Reserved
31:27
0x0
Reserved
AN timer is reduced if this bit is set.
Link OK Fix Enable
Control for enabling/disabling LinkOK/SyncOK fix. Should be set for normal operation.
1. Read from EEPROM.
7.18.3
PCS Link Status - PCS_LSTS (0x420C; RO)
Field
LINK OK
Bit(s)
0
Initial Value
0b
Description
Link OK
This bit denotes the current link ok status.
0b = Link down.
1b = Link up/OK.
SPEED
2:1
10b
Speed
This bit denotes the current operating Speed.
00b = 10 Mb/s.
01b = 100 Mb/s.
10b = 1000 Mb/s.
11b = Reserved.
DUPLEX
3
1b
Duplex
This bit denotes the current duplex mode.
1b = Full duplex.
0b = Half duplex.
SYNC OK
4
0b
Sync OK
This bit indicates the current value of Sync OK from the PCS Sync state machine.
Reserved
Revision: 2.50
October 2011
15:5
-
Reserved
Intel® 82580EB/82580DB Gigabit Ethernet Controller
Datasheet
387
Intel® 82580EB/82580DB GbE Controller — AN Advertisement - PCS_ANADV (0x4218; R/W)
Field
Bit(s)
Initial Value
AN
COMPLETE
16
0b
AN PAGE
RECEIVED
17
AN
TIMEDOUT
18
0b
AN REMOTE
FAULT
19
0b
Description
AN Complete
This bit indicates that the AN process has completed.This bit is set when the AN
process reached the Link OK state. It is reset upon AN restart or reset. It is set even if
the AN negotiation failed and no common capabilities where found.
0b
AN Page Received
This bit indicates that a link partner's page was received during an AN process.
This bit is cleared on reads.
AN Timed Out
This bit indicates an AN process was timed out. Valid after the AN Complete bit is set.
AN Remote Fault
This bit indicates that an AN page was received with a remote fault indication during
an AN process.
This bit cleared on reads.
AN ERROR
(RWS)
20
0B
AN Error
This bit indicates that a AN error condition was detected in SerDes/SGMII mode. Valid
after the AN Complete bit is set.
AN error conditions:
SerDes mode: Both nodes not Full Duplex
SGMII mode: PHY is set to 1000 Mb/s Half Duplex mode.
Software can also force a AN error condition by writing to this bit (or can clear a
existing AN error condition).
This bit is cleared at the start of AN.
Reserved
31:21
7.18.4
0x0
Reserved
AN Advertisement - PCS_ANADV (0x4218; R/W)
Field
Bit(s)
Initial Value
Reserved
4:0
-
FDCAP
5
1b
Description
Reserved
Full Duplex
Setting this bit indicates that the 82580EB/DB is capable of full duplex operation. This
bit should be set to 1b for normal operation.
HDCAP (RO)
6
0b
Half Duplex
This bit indicates that the 82580EB/DB is capable of half duplex operation. This bit is
tied to 0b because the 82580EB/DB does not support half duplex in SerDes mode.
ASM
8:7
00b1
Local PAUSE Capabilities
The 82580EB/DB's PAUSE capability is encoded in this field.
00b = No PAUSE.
01b = Symmetric PAUSE.
10b = Asymmetric PAUSE to link partner.
11b = Both symmetric and asymmetric PAUSE to the 82580EB/DB.
Reserved
11:9
-
Reserved
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Link Partner Ability - PCS_LPAB (0x421C; RO) — Intel® 82580EB/82580DB GbE Controller
Field
RFLT
Bit(s)
13:12
Initial Value
00b
Description
Remote Fault
The 82580EB/DB's remote fault condition is encoded in this field. The 82580EB/DB
might indicate a fault by setting a non-zero remote fault encoding and re-negotiating.
00b = No error, link OK.
01b = Link failure.
10b = Offline.
11b = Auto-negotiation error.
Reserved
14
-
Reserved
NEXTP
15
0b
Next Page Capable
The 82580EB/DB asserts this bit to request a next page transmission.
The 82580EB/DB clears this bit when no subsequent next pages are requested.
Reserved
31:16
0x0
Reserved
1. Loaded from EEPROM word 0x0F, bits 13:12.
7.18.5
Link Partner Ability - PCS_LPAB (0x421C; RO)
Field
Bit(s)
Initial Value
Description
Reserved
4:0
0x0
Reserved
LPFD
5
0b
LP Full Duplex (SerDes)
When set to 1b, the link partner is capable of full duplex operation. When set to 0b,
the link partner is not capable of full duplex mode.
This bit is reserved while in SGMII mode.
LPHD
6
0b
LP Half Duplex (SerDes)
When set to 1b, the link partner is capable of half duplex operation. When set to 0b,
the link partner is not capable of half duplex mode.
This bit is reserved while in SGMII mode.
LPASM
8:7
00b
LP ASMDR/LP PAUSE (SerDes)
The link partner's PAUSE capability is encoded in this field.
00b = No PAUSE.
01b = Symmetric PAUSE.
10b = Asymmetric PAUSE to link partner.
11b = Both symmetric and asymmetric PAUSE to the 82580EB/DB.
These bits are reserved while in SGMII mode.
Reserved
9
SGMII SPEED 11:10
0b
00b
Reserved
SerDes: reserved.
Speed (SGMII): Speed indication from the PHY.
PRF
13:12
00b
LP Remote Fault (SerDes)
The link partner's remote fault condition is encoded in this field.
00b = No error, link ok.
10b = Link failure.
01b = Offline.
11b = Auto-negotiation error.
SGMII [13]: Reserved
SGMII [12]: Duplex mode indication from the PHY.
Revision: 2.50
October 2011
Intel® 82580EB/82580DB Gigabit Ethernet Controller
Datasheet
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Intel® 82580EB/82580DB GbE Controller — Next Page Transmit - PCS_NPTX (0x4220; RW)
Field
ACK
Bit(s)
14
Initial Value
0b
Description
Acknowledge (SerDes)
The link partner has acknowledge page reception.
SGMII: Reserved.
LPNEXTP
15
0b
LP Next Page Capable (SerDes)
The link partner asserts this bit to indicate its ability to accept next pages.
SGMII: Link-OK indication from the PHY.
Reserved
31:16
7.18.6
Reserved
Next Page Transmit - PCS_NPTX (0x4220; RW)
Field
CODE
0x0
Bit(s)
10:0
Initial Value
0x0
Description
Message/Unformatted Code Field
The Message Field is an 11-bit wide field that encodes 2048 possible messages.
Unformatted Code Field is an 11-bit wide field that might contain an arbitrary value.
TOGGLE
11
0b
Toggle
This bit is used to ensure synchronization with the Link Partner during Next Page
exchange. This bit always takes the opposite value of the Toggle bit in the previously
exchanged Link Code Word. The initial value of the Toggle bit in the first Next Page
transmitted is the inverse of bit 11 in the base Link Code Word and, therefore, can
assume a value of 0b or 1b. The Toggle bit is set as follows:
0b = Previous value of the transmitted Link Code Word when 1b
1b = Previous value of the transmitted Link Code Word when 0b.
ACK2
12
0b
Acknowledge 2
Used to indicate that a device has successfully received its Link Partners' Link Code
Word.
PGTYPE
13
0b
Message/Unformatted Page
This bit is used to differentiate a Message Page from an Unformatted Page. The
encoding is:
0b = Unformatted page.
1b = Message page.
Reserved
14
-
Reserved
NXTPG
15
0b
Next Page
Used to indicate whether or not this is the last Next Page to be transmitted. The
encoding is:
0b = Last page.
1b = Additional Next Pages follow.
Reserved
31:16
-
Reserved
Intel® 82580EB/82580DB Gigabit Ethernet Controller
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Link Partner Ability Next Page - PCS_LPABNP (0x4224; RO) — Intel® 82580EB/82580DB GbE Controller
7.18.7
Link Partner Ability Next Page - PCS_LPABNP (0x4224;
RO)
Field
CODE
Bit(s)
10:0
Initial Value
-
Description
Message/Unformatted Code Field
The Message Field is an 11-bit wide field that encodes 2048 possible messages.
Unformatted Code Field is an 11-bit wide field that might contain an arbitrary value.
TOGGLE
11
-
Toggle
This bit is used to ensure synchronization with the Link Partner during Next Page
exchange. This bit always takes the opposite value of the Toggle bit in the previously
exchanged Link Code Word. The initial value of the Toggle bit in the first Next Page
transmitted is the inverse of bit 11 in the base Link Code Word and, therefore, can
assume a value of 0b or 1b. The Toggle bit is set as follows:
0b = Previous value of the transmitted Link Code Word when 1b
1b = Previous value of the transmitted Link Code Word when 0b.
ACK2
12
-
Acknowledge 2
Used to indicate that a device has successfully received its Link Partners' Link Code
Word.
MSGPG
13
-
Message Page
This bit is used to differentiate a Message Page from an Unformatted Page. The
encoding is:
0b = Unformatted page.
1b = Message page.
ACK
14
-
Acknowledge
The Link Partner has acknowledged Next Page reception.
NXTPG
15
-
Next Page
Used to indicate whether or not this is the last Next Page to be transmitted. The
encoding is:
0b = Last page.
1b = Additional Next Pages follow.
Reserved
7.18.8
31:16
-
Reserved
SFP I2C Command- I2CCMD (0x1028; R/W)
This register is used by software to read or write to the configuration registers in an SFP module when
the CTRL_EXT.I2C Enabled bit is set to 1.
Note:
Revision: 2.50
October 2011
According to the SFP specification, only reads are allowed from this interface; however, SFP
vendors also provide a writable register through this interface (for example, PHY registers).
As a result, write capability is also supported.
Intel® 82580EB/82580DB Gigabit Ethernet Controller
Datasheet
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Intel® 82580EB/82580DB GbE Controller — SFP I2C Parameters - I2CPARAMS (0x102C; R/W)
Field
DATA
Bit(s)
15:0
Initial Value
X
Description
Data
In a write command, software places the data bits and then the MAC shifts them out
to the I2C bus. In a read command, the MAC reads these bits serially from the I2C bus
and then software reads them from this location.
Note: This field is read in byte order and not in word order.
REGADD
23:16
0x0
PHYADD
26:24
0x0
OP
27
0b
I2C Register Address
For example, register 0, 1, 2... 255.
Device Address bits 3 -1
The actual address used is b{1010, PHYADD[2:0], 0}.
Op Code
0b = I2C write.
1b = I2C read.
Reset
28
0b
Reset Sequence
If set, sends a reset sequence before the actual read or write.
This bit is self clearing.
A reset sequence is defined as nine consecutive stop conditions.
R
29
0b
Ready Bit
Set to 1b by the 82580EB/DB at the end of the I2C transaction. For example, indicates
a read or write has completed.
Reset by a software write of a command.
IReserved
30
0b
Interrupt Enable
When set to 1b by software, it causes an Interrupt to be asserted to indicate the end
of an I2C cycle (ICR.MDAC).Reserved
E
31
0b
Error
This bit set is to 1b by hardware when it fails to complete an I2C read. Reset by a
software write of a command.
Note: Bit is valid only when Ready bit is set.
7.18.9
SFP I2C Parameters - I2CPARAMS (0x102C; R/W)
This register is used to set the parameters for the I2C access to the SFP module and to allow bit
banging access to the I2C interface.
Field
Write Time
Bit(s)
Initial Value
4:0
110b
Description
Write Time
Defines the delay between a write access and the next access. The value is in
milliseconds. A value of zero is not valid.
Read Time
7:5
010b
Read Time
Defines the delay between a read access and the next access. The value is in
microseconds. A value of Zero is not valid
I2CBB_EN
8
0b
I2C Bit Bang Enable
If set, the I2C_CLK and I2C_DATA lines are controlled via the CLK, DATA and
DATA_OE_N fields of this register. Otherwise, they are controlled by the hardware
machine activated via the I2CCMD or MDIC registers.
CLK
9
0b
I2C Clock
While in bit bang mode, controls the value driven on the I2C_CLK pad of this port.
Intel® 82580EB/82580DB Gigabit Ethernet Controller
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Statistics Register Descriptions — Intel® 82580EB/82580DB GbE Controller
Field
DATA_OUT
Bit(s)
10
Initial Value
0b
Description
I2C_DATA
While in bit bang mode and when the DATA_OE_N field is zero, controls the value
driven on the I2C_DATA pad of this port.
DATA_OE_N
11
0b
I2C_DATA_OE_N
While in bit bang mode, controls the direction of the I2C_DATA pad of this port.
0b = Pad is output.
1b = Pad is input.
DATA_IN (RO)
12
X
I2C_DATA_IN
Reflects the value of the I2C_DATA pad. While in bit bang mode when the
DATA_OE_N field is zero, this field reflects the value set in the DATA_OUT field.
CLK_OE_N
13
0b
I2C Clock Output Enable
While in bit bang mode, controls the direction of the I2C_CLK pad of this port.
0b = Pad is output.
1b = Pad is input.
CLK_IN (RO)
14
X
I2C Clock In Value
Reflects the value of the I2C_CLK pad. While in bit bang mode when the CLK_OE_N
field is zero, this field reflects the value set in the CLK_OUT field.
clk_stretch_dis
15
0b
0b - Enable slave clock stretching support in I2C access.
1b - Disable clock stretching support in I2C access.
Reserved
7.19
31:16
0x0
Reserved
Statistics Register Descriptions
All Statistics registers reset when read. In addition, they stick at 0xFFFF_FFFF when the maximum
value is reached.
For the receive statistics it should be noted that a packet is indicated as received if it passes the
82580EB/DB's filters and is placed into the packet buffer memory. A packet does not have to be
transferred to host memory in order to be counted as received.
Due to divergent paths between interrupt-generation and logging of relevant statistics counts, it might
be possible to generate an interrupt to the system for a noteworthy event prior to the associated
statistics count actually being incremented. This is extremely unlikely due to expected delays
associated with the system interrupt-collection and ISR delay, but might be observed as an interrupt for
which statistics values do not quite make sense. Hardware guarantees that any event noteworthy of
inclusion in a statistics count is reflected in the appropriate count within 1 s; a small time-delay prior
to a read of statistics might be necessary to avoid the potential for receiving an interrupt and observing
an inconsistent statistics count as part of the ISR.
7.19.1
CRC Error Count - CRCERRS (0x4000; RC)
Counts the number of receive packets with CRC errors. In order for a packet to be counted in this
register, it must pass address filtering and must be 64 bytes or greater (from <Destination Address>
through <CRC>, inclusively) in length. If receives are not enabled, then this register does not
increment.
Revision: 2.50
October 2011
Intel® 82580EB/82580DB Gigabit Ethernet Controller
Datasheet
393
Intel® 82580EB/82580DB GbE Controller — Alignment Error Count - ALGNERRC (0x4004; RC)
Field
CEC
Bit(s)
31:0
7.19.2
Initial Value
0x0
Description
CRC error count
Alignment Error Count - ALGNERRC (0x4004; RC)
Counts the number of receive packets with alignment errors (the packet is not an integer number of
bytes in length). In order for a packet to be counted in this register, it must pass address filtering and
must be 64 bytes or greater (from <Destination Address> through <CRC>, inclusive) in length. If
receives are not enabled, then this register does not increment. This register is valid only in MII mode
during 10/100 Mb/s operation.
Field
AEC
Bit(s)
31:0
7.19.3
Initial Value
0x0
Description
Alignment error count
Symbol Error Count - SYMERRS (0x4008; RC)
Counts the number of symbol errors between reads. The count increases for every bad symbol
received, whether or not a packet is currently being received and whether or not the link is up. When
working in SerDes/SGMII/1000BASE-KX mode these statistics can be read from the SCVPC register.
Field
SYMERRS
7.19.4
Bit(s)
31:0
Initial Value
0x0
Description
Symbol Error Count
RX Error Count - RXERRC (0x400C; RC)
Counts the number of packets received in which RX_ER was asserted by the PHY. In order for a packet
to be counted in this register, it must pass address filtering and must be 64 bytes or greater (from
<Destination Address> through <CRC>, inclusive) in length. If receives are not enabled, then this
register does not increment.
This register is not available in SerDes/SGMII/1000BASE-KX modes.
Field
RXEC
7.19.5
Bit(s)
31:0
Initial Value
0x0
Description
RX error count
Missed Packets Count - MPC (0x4010; RC)
Counts the number of missed packets. Packets are missed when the receive FIFO has insufficient space
to store the incoming packet. This can be caused because of too few buffers allocated, or because there
is insufficient bandwidth on the PCI bus. Events setting this counter causes ICR.Rx Miss, the Receiver
Overrun Interrupt, to be set. This register does not increment if receives are not enabled.
These packets are also counted in the Total Packets Received register as well as in Total Octets
Received.
Intel® 82580EB/82580DB Gigabit Ethernet Controller
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Single Collision Count - SCC (0x4014; RC) — Intel® 82580EB/82580DB GbE Controller
Field
MPC
7.19.6
Bit(s)
31:0
Initial Value
0x0
Description
Missed Packets Count
Single Collision Count - SCC (0x4014; RC)
This register counts the number of times that a successfully transmitted packet encountered a single
collision. This register only increments if transmits are enabled (TCTL.EN is set) and the 82580EB/DB is
in half-duplex mode.
Field
SCC
7.19.7
Bit(s)
31:0
Initial Value
0x0
Description
Number of times a transmit encountered a single collision.
Excessive Collisions Count - ECOL (0x4018; RC)
When 16 or more collisions have occurred on a packet, this register increments, regardless of the value
of collision threshold. If collision threshold is set below 16, this counter won’t increment. This register
only increments if transmits are enabled (TCTL.EN is set) and the 82580EB/DB is in half-duplex mode.
Field
ECC
Bit(s)
31:0
7.19.8
Initial Value
0x0
Description
Number of packets with more than 16 collisions.
Multiple Collision Count - MCC (0x401C; RC)
This register counts the number of times that a transmit encountered more than one collision but less
than 16. This register only increments if transmits are enabled (TCTL.EN is set) and the 82580EB/DB is
in half-duplex mode.
Field
MCC
7.19.9
Bit(s)
31:0
Initial Value
0x0
Description
Number of times a successful transmit encountered multiple collisions.
Late Collisions Count - LATECOL (0x4020; RC)
Late collisions are collisions that occur after one slot time. This register only increments if transmits are
enabled (TCTL.EN is set) and the 82580EB/DB is in half-duplex mode.
Field
LCC
7.19.10
Bit(s)
31:0
Initial Value
0x0
Description
Number of packets with late collisions.
Collision Count - COLC (0x4028; RC)
This register counts the total number of collisions seen by the transmitter. This register only increments
if transmits are enabled (TCTL.EN is set) and the 82580EB/DB is in half-duplex mode. This register
applies to clear as well as secure traffic.
Revision: 2.50
October 2011
Intel® 82580EB/82580DB Gigabit Ethernet Controller
Datasheet
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Intel® 82580EB/82580DB GbE Controller — Defer Count - DC (0x4030; RC)
Field
CCC
7.19.11
Bit(s)
31:0
Initial Value
0x0
Description
Total number of collisions experienced by the transmitter.
Defer Count - DC (0x4030; RC)
This register counts defer events. A defer event occurs when the transmitter cannot immediately send
a packet due to the medium being busy either because another device is transmitting, the IPG timer
has not expired, half-duplex deferral events, reception of XOFF frames, or the link is not up. This
register only increments if transmits are enabled (TCTL.EN is set). This counter does not increment for
streaming transmits that are deferred due to TX IPG.
Field
CDC
7.19.12
Bit(s)
31:0
Initial Value
0x0
Description
Number of defer events.
Transmit with No CRS - TNCRS (0x4034; RC)
This register counts the number of successful packet transmissions in which the CRS input from the PHY
was not asserted within one slot time of start of transmission from the MAC. Start of transmission is
defined as the assertion of TX_EN to the PHY.
The PHY should assert CRS during every transmission. Failure to do so might indicate that the link has
failed, or the PHY has an incorrect link configuration. This register only increments if transmits are
enabled (TCTL.EN is set). This register is not valid in SGMII mode and is only valid when the 82580EB/
DB is operating at half duplex.
Field
TNCRS
7.19.13
Bit(s)
31:0
0x0
Description
Number of transmissions without a CRS assertion from the PHY.
Host Transmit Discarded Packets by MAC Count - HTDPMC
(0x403C; RC)
Field
HTDPMC
Initial Value
Bit(s)
31:0
Initial Value
0x0
Description
Number of packets sent by the host but discarded by the MAC
This register counts the number of packets sent by the host (and not the manageability engine) that
are dropped by the MAC. This can include packets dropped because of excessive collisions or link fail
events.
7.19.14
Receive Length Error Count - RLEC (0x4040; RC)
This register counts receive length error events. A length error occurs if an incoming packet passes the
filter criteria but is undersized or oversized. Packets less than 64 bytes are undersized. Packets over
1518, 1522 or 1526 bytes (according to the number of VLAN tags present) are oversized if Long Packet
Enable (RCTL.LPE) is 0b. If LPE is 1b, then an incoming, packet is considered oversized if it exceeds the
size defined in RLPML.RLPML field.
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October 2011
XON Received Count - XONRXC (0x4048; RC) — Intel® 82580EB/82580DB GbE Controller
If receives are not enabled, this register does not increment. These lengths are based on bytes in the
received packet from <Destination Address> through <CRC>, inclusive. Packets sent to the
manageability engine are included in this counter.
Note:
Runt packets smaller than 25 bytes may not be counted by this counter.
Field
RLEC
7.19.15
Bit(s)
31:0
Initial Value
0x0
Description
Number of packets with receive length errors.
XON Received Count - XONRXC (0x4048; RC)
This register counts the number of valid XON packets received. XON packets can use the global
address, or the station address. This register only increments if receives are enabled (RCTL.RXEN is
set).
Field
XONRXC
7.19.16
Bit(s)
31:0
Initial Value
0x0
Description
Number of XON packets received.
XON Transmitted Count - XONTXC (0x404C; RC)
This register counts the number of XON packets transmitted. These can be either due to a full queue or
due to software initiated action (using TCTL.SWXOFF). This register only increments if transmits are
enabled (TCTL.EN is set).
Field
XONTXC
7.19.17
Bit(s)
31:0
Initial Value
0x0
Description
Number of XON packets transmitted.
XOFF Received Count - XOFFRXC (0x4050; RC)
This register counts the number of valid XOFF packets received. XOFF packets can use the global
address or the station address. This register only increments if receives are enabled (RCTL.RXEN is
set).
Field
XOFFRXC
7.19.18
Bit(s)
31:0
Initial Value
0x0
Description
Number of XOFF packets received.
XOFF Transmitted Count - XOFFTXC (0x4054; RC)
This register counts the number of XOFF packets transmitted. These can be either due to a full queue or
due to software initiated action (using TCTL.SWXOFF). This register only increments if transmits are
enabled (TCTL.EN is set).
Field
XOFFTXC
Revision: 2.50
October 2011
Bit(s)
31:0
Initial Value
0x0
Description
Number of XOFF packets transmitted.
Intel® 82580EB/82580DB Gigabit Ethernet Controller
Datasheet
397
Intel® 82580EB/82580DB GbE Controller — FC Received Unsupported Count - FCRUC (0x4058; RC)
7.19.19
FC Received Unsupported Count - FCRUC (0x4058; RC)
This register counts the number of unsupported flow control frames that are received.
The FCRUC counter increments when a flow control packet is received that matches either the reserved
flow control multicast address (in FCAH/L) or the MAC station address, and has a matching flow control
type field match (to the value in FCT), but has an incorrect opcode field. This register only increments if
receives are enabled (RCTL.RXEN is set).
Note:
When the RCTL.PMCF bit is set to 1b then the FCRUC counter will increment on reception of
packets that don’t match standard address filtering.
Field
FCRUC
7.19.20
Bit(s)
Initial Value
31:0
0x0
Description
Number of unsupported flow control frames received.
Packets Received [64 Bytes] Count - PRC64 (0x405C; RC)
This register counts the number of good packets received that are exactly 64 bytes (from <Destination
Address> through <CRC>, inclusive) in length. Packets that are counted in the Missed Packet Count
register are not counted in this register. Packets sent to the manageability engine are included in this
counter. This register does not include received flow control packets and increments only if receives are
enabled (RCTL.RXEN is set).
Field
PRC64
7.19.21
Bit(s)
Initial Value
31:0
0x0
Description
Number of packets received that are 64 bytes in length.
Packets Received [65—127 Bytes] Count - PRC127
(0x4060; RC)
This register counts the number of good packets received that are 65-127 bytes (from <Destination
Address> through <CRC>, inclusive) in length. Packets that are counted in the Missed Packet Count
register are not counted in this register. Packets sent to the manageability engine are included in this
counter. This register does not include received flow control packets and increments only if receives are
enabled (RCTL.RXEN is set).
Field
PRC127
7.19.22
Bit(s)
31:0
Initial Value
0x0
Description
Number of packets received that are 65-127 bytes in length.
Packets Received [128—255 Bytes] Count - PRC255
(0x4064; RC)
This register counts the number of good packets received that are 128-255 bytes (from <Destination
Address> through <CRC>, inclusive) in length. Packets that are counted in the Missed Packet Count
register are not counted in this register. Packets sent to the manageability engine are included in this
counter. This register does not include received flow control packets and increments only if receives are
enabled (RCTL.RXEN is set).
Intel® 82580EB/82580DB Gigabit Ethernet Controller
Datasheet
398
Revision: 2.50
October 2011
Packets Received [256—511 Bytes] Count - PRC511 (0x4068; RC) — Intel® 82580EB/82580DB GbE
Controller
Field
PRC255
7.19.23
Bit(s)
31:0
Initial Value
0x0
Description
Number of packets received that are 128-255 bytes in length.
Packets Received [256—511 Bytes] Count - PRC511
(0x4068; RC)
This register counts the number of good packets received that are 256-511 bytes (from <Destination
Address> through <CRC>, inclusive) in length. Packets that are counted in the Missed Packet Count
register are not counted in this register. Packets sent to the manageability engine are included in this
counter. This register does not include received flow control packets and increments only if receives are
enabled (RCTL.RXEN is set).
Field
PRC511
7.19.24
Bit(s)
Initial Value
31:0
0x0
Description
Number of packets received that are 256-511 bytes in length.
Packets Received [512—1023 Bytes] Count - PRC1023
(0x406C; RC)
This register counts the number of good packets received that are 512-1023 bytes (from <Destination
Address> through <CRC>, inclusive) in length. Packets that are counted in the Missed Packet Count
register are not counted in this register. Packets sent to the manageability engine are included in this
counter. This register does not include received flow control packets and increments only if receives are
enabled (RCTL.RXEN is set).
Field
PRC1023
7.19.25
Bit(s)
31:0
Initial Value
0x0
Description
Number of packets received that are 512-1023 bytes in length.
Packets Received [1024 to Max Bytes] Count - PRC1522
(0x4070; RC)
This register counts the number of good packets received that are from 1024 bytes to the maximum
(from <Destination Address> through <CRC>, inclusive) in length. The maximum is dependent on the
current receiver configuration (for example, LPE, etc.) and the type of packet being received. If a
packet is counted in Receive Oversized Count, it is not counted in this register (see Section 7.19.37).
This register does not include received flow control packets and only increments if the packet has
passed address filtering and receives are enabled (RCTL.RXEN is set). Packets sent to the
manageability engine are included in this counter.
Due to changes in the standard for maximum frame size for VLAN tagged frames in 802.3, the
82580EB/DB accepts packets that have a maximum length of 1522 bytes. The RMON statistics
associated with this range has been extended to count 1522 byte long packets. If CTRL.EXT_VLAN is
set, packets up to 1526 bytes are counted by this counter.
Field
PRC1522
Revision: 2.50
October 2011
Bit(s)
31:0
Initial Value
0x0
Description
Number of packets received that are 1024-Max bytes in length.
Intel® 82580EB/82580DB Gigabit Ethernet Controller
Datasheet
399
Intel® 82580EB/82580DB GbE Controller — Good Packets Received Count - GPRC (0x4074; RC)
7.19.26
Good Packets Received Count - GPRC (0x4074; RC)
This register counts the number of good packets received of any legal length. The legal length for the
received packet is defined by the value of Long Packet Enable (RCTL.LPE) (see Section 7.19.37). This
register does not include received flow control packets and only counts packets that pass filtering. This
register only increments if receives are enabled (RCTL.RXEN is set). This register does not count
packets counted by the Missed Packet Count (MPC) register. Packets sent to the manageability engine
are included in this counter.
Note:
GPRC can count packets interrupted by a link disconnect although they have a CRC error.
Field
GPRC
7.19.27
Bit(s)
31:0
Initial Value
0x0
Description
Number of good packets received (of any length).
Broadcast Packets Received Count - BPRC (0x4078; RC)
This register counts the number of good (no errors) broadcast packets received. This register does not
count broadcast packets received when the broadcast address filter is disabled. This register only
increments if receives are enabled (RCTL.RXEN is set). This register does not count packets counted by
the Missed Packet Count (MPC) register. Packets sent to the manageability engine are included in this
counter.
Field
BPRC
7.19.28
Bit(s)
31:0
Initial Value
0x0
Description
Number of broadcast packets received.
Multicast Packets Received Count - MPRC (0x407C; RC)
This register counts the number of good (no errors) multicast packets received. This register does not
count multicast packets received that fail to pass address filtering nor does it count received flow
control packets. This register only increments if receives are enabled (RCTL.RXEN is set). This register
does not count packets counted by the Missed Packet Count (MPC) register. Packets sent to the
manageability engine are included in this counter.
Field
MPRC
7.19.29
Bit(s)
31:0
Initial Value
0x0
Description
Number of multicast packets received.
Good Packets Transmitted Count - GPTC (0x4080; RC)
This register counts the number of good (no errors) packets transmitted. A good transmit packet is
considered one that is 64 or more bytes in length (from <Destination Address> through <CRC>,
inclusively) in length. This does not include transmitted flow control packets. This register only
increments if transmits are enabled (TCTL.EN is set). The register counts clear as well as secure
packets.
Field
GPTC
Bit(s)
31:0
Initial Value
0x0
Intel® 82580EB/82580DB Gigabit Ethernet Controller
Datasheet
400
Description
Number of good packets transmitted.
Revision: 2.50
October 2011
Good Octets Received Count - GORCL (0x4088; RC) — Intel® 82580EB/82580DB GbE Controller
7.19.30
Good Octets Received Count - GORCL (0x4088; RC)
These registers make up a 64-bit register that counts the number of good (no errors) octets received.
This register includes bytes received in a packet from the <Destination Address> field through the
<CRC> field, inclusive; GORCL must be read before GORCH.
In addition, it sticks at 0xFFFF_FFFF_FFFF_FFFF when the maximum value is reached. Only octets of
packets that pass address filtering are counted in this register. This register does not count octets of
packets counted by the Missed Packet Count (MPC) register. Octets of packets sent to the manageability
engine are included in this counter. This register only increments if receives are enabled (RCTL.RXEN is
set).
These octets do not include octets of received flow control packets.
Field
GORCL
7.19.31
Bit(s)
31:0
7.19.32
0x0
Description
Number of good octets received – lower 4 bytes.
Good Octets Received Count - GORCH (0x408C; RC)
Field
GORCH
Initial Value
Bit(s)
31:0
Initial Value
0x0
Description
Number of good octets received – upper 4 bytes.
Good Octets Transmitted Count - GOTCL (0x4090; RC)
These registers make up a 64-bit register that counts the number of good (no errors) packets
transmitted. This register must be accessed using two independent 32-bit accesses; GOTCL must be
read before GOTCH.
In addition, it sticks at 0xFFFF_FFFF_FFFF_FFFF when the maximum value is reached. This register
includes bytes transmitted in a packet from the <Destination Address> field through the <CRC> field,
inclusive. This register counts octets in successfully transmitted packets that are 64 or more bytes in
length. This register only increments if transmits are enabled (TCTL.EN is set). The register counts clear
as well as secure octets.
These octets do not include octets in transmitted flow control packets.
Field
GOTCL
7.19.33
Bit(s)
31:0
Revision: 2.50
October 2011
0x0
Description
Number of good octets transmitted – lower 4 bytes.
Good Octets Transmitted Count - GOTCH (4094; RC)
Field
GOTCH
Initial Value
Bit(s)
31:0
Initial Value
0x0
Description
Number of good octets transmitted – upper 4 bytes.
Intel® 82580EB/82580DB Gigabit Ethernet Controller
Datasheet
401
Intel® 82580EB/82580DB GbE Controller — Receive No Buffers Count - RNBC (0x40A0; RC)
7.19.34
Receive No Buffers Count - RNBC (0x40A0; RC)
This register counts the number of times that frames were received when there were no available
buffers in host memory to store those frames (receive descriptor head and tail pointers were equal).
The packet is still received if there is space in the FIFO. This register only increments if receives are
enabled (RCTL.RXEN is set).
This register does not increment when flow control packets are received.
Field
RNBC
7.19.35
Bit(s)
31:0
Initial Value
0x0
Description
Number of receive no buffer conditions.
Receive Undersize Count - RUC (0x40A4; RC)
This register counts the number of received frames that passed address filtering, and were less than
minimum size (64 bytes from <Destination Address> through <CRC>, inclusive), and had a valid CRC.
This register only increments if receives are enabled (RCTL.RXEN is set).
Field
RUC
7.19.36
Bit(s)
31:0
Initial Value
0x0
Description
Number of receive undersize errors.
Receive Fragment Count - RFC (0x40A8; RC)
This register counts the number of received frames that passed address filtering, and were less than
minimum size (64 bytes from <Destination Address> through <CRC>, inclusive), but had a bad CRC
(this is slightly different from the Receive Undersize Count register). This register only increments if
receives are enabled (RCTL.RXEN is set).
Field
RFC
Note:
7.19.37
Bit(s)
31:0
Initial Value
0x0
Description
Number of receive fragment errors.
Runt packets smaller than 25 bytes may not be counted by this counter.
Receive Oversize Count - ROC (0x40AC; RC)
This register counts the number of received frames with valid CRC field that passed address filtering,
and were greater than maximum size. Packets over 1522 bytes are oversized if LongPacketEnable
(RCTL.LPE) is 0b. If LongPacketEnable is 1b, then an incoming packet is considered oversized if it
exceeds the value set in the RLPML register.
In VMDq mode, a packet is counted only if it is bigger than the VOMLR.RLPML value for all the VMs that
where supposed to receive the packet.
If receives are not enabled, this register does not increment. These lengths are based on bytes in the
received packet from <Destination Address> through <CRC>, inclusive.
Intel® 82580EB/82580DB Gigabit Ethernet Controller
Datasheet
402
Revision: 2.50
October 2011
Receive Jabber Count - RJC (0x40B0; RC) — Intel® 82580EB/82580DB GbE Controller
Note:
The maximum size of a packet when LPE is 0b is fixed according to the
CTRL_EXT.EXT_VLAN bit and the detection of a VLAN tag in the packet.
Field
ROC
7.19.38
Bit(s)
31:0
Initial Value
0x0
Description
Number of receive oversize errors.
Receive Jabber Count - RJC (0x40B0; RC)
This register counts the number of received frames that passed address filtering, and were greater than
maximum size and had a bad CRC (this is slightly different from the Receive Oversize Count register).
Packets over 1518/1522/1526 bytes are oversized if LPE is 0b. If LPE is 1b, then an incoming packet is
considered oversized if it exceeds RLPML.LPML bytes.
If receives are not enabled, this register does not increment. These lengths are based on bytes in the
received packet from <Destination Address> through <CRC>, inclusive.
Note:
The maximum size of a packet when LPE is 0b is fixed according to the
CTRL_EXT.EXT_VLAN bit and the detection of a VLAN tag in the packet.
Field
RJC
Bit(s)
31:0
7.19.39
Initial Value
0x0
Description
Number of receive jabber errors.
Management Packets Received Count MNGPRC (0x40B4; RC)
This register counts the total number of packets received that pass the management filters as
described in Section 11.4. Any packets with errors are not counted, except packets that are dropped
because the management receive FIFO is full.
Packets sent to both the host and the management interface are not counted by this counter.
Field
MNGPRC
7.19.40
Bit(s)
31:0
Initial Value
0x0
Description
Number of management packets received.
Management Packets Dropped Count MPDC (0x40B8; RC)
This register counts the total number of packets received that pass the management filters as
described in Section 11.4, that are dropped because the management receive FIFO is full. Management
packets include any packet directed to the manageability console (for example, BMC and ARP packets).
Field
MPDC
Revision: 2.50
October 2011
Bit(s)
31:0
Initial Value
0x0
Description
Number of management packets dropped.
Intel® 82580EB/82580DB Gigabit Ethernet Controller
Datasheet
403
Intel® 82580EB/82580DB GbE Controller — Management Packets Transmitted Count - MNGPTC
(0x40BC; RC)
7.19.41
Management Packets Transmitted Count MNGPTC (0x40BC; RC)
This register counts the total number of transmitted packets originating from the manageability path.
Field
MPTC
7.19.42
Bit(s)
31:0
Initial Value
0x0
Description
Number of management packets transmitted.
Total Octets Received - TORL (0x40C0; RC)
These registers make up a logical 64-bit register which counts the total number of octets received.
This register must be accessed using two independent 32-bit accesses; TORL must be read before
TORH. This register sticks at 0xFFFF_FFFF_FFFF_FFFF when the maximum value is reached.
All packets received have their octets summed into this register, regardless of their length, whether
they are erred, or whether they are flow control packets. This register includes bytes received in a
packet from the <Destination Address> field through the <CRC> field, inclusive. This register only
increments if receives are enabled (RCTL.RXEN is set).
Note:
Broadcast rejected packets are counted in this counter (as opposed to all other rejected
packets that are not counted).
Field
TORL
7.19.43
Bit(s)
31:0
7.19.44
0x0
Description
Number of total octets received – lower 4 bytes.
Total Octets Received - TORH (0x40C4; RC)
Field
TORH
Initial Value
Bit(s)
31:0
Initial Value
0x0
Description
Number of total octets received – upper 4 bytes.
Total Octets Transmitted - TOTL (0x40C8; RC)
These registers make up a 64-bit register that counts the total number of octets transmitted. This
register must be accessed using two independent 32-bit accesses; TOTL must be read before TOTH.
This register sticks at 0xFFFF_FFFF_FFFF_FFFF when the maximum value is reached.
All transmitted packets have their octets summed into this register, regardless of their length or
whether they are flow control packets. This register includes bytes transmitted in a packet from the
<Destination Address> field through the <CRC> field, inclusive.
Octets transmitted as part of partial packet transmissions (for example, collisions in half-duplex mode)
are not included in this register. This register only increments if transmits are enabled (TCTL.EN is set).
Field
TOTL
Bit(s)
31:0
Initial Value
0x0
Intel® 82580EB/82580DB Gigabit Ethernet Controller
Datasheet
404
Description
Number of total octets transmitted – lower 4 bytes.
Revision: 2.50
October 2011
Total Octets Transmitted - TOTH (0x40CC; RC) — Intel® 82580EB/82580DB GbE Controller
7.19.45
Total Octets Transmitted - TOTH (0x40CC; RC)
Field
TOTH
7.19.46
Bit(s)
31:0
Initial Value
0x0
Description
Number of total octets transmitted – upper 4 bytes.
Total Packets Received - TPR (0x40D0; RC)
This register counts the total number of all packets received. All packets received are counted in this
register, regardless of their length, whether they have errors, or whether they are flow control packets.
This register only increments if receives are enabled (RCTL.RXEN is set).
Note:
Broadcast rejected packets are counted in this counter (as opposed to all other rejected
packets that are not counted).
Runt packets smaller than 25 bytes may not be counted by this counter.
TPR can count packets interrupted by a link disconnect although they have a CRC error.
Field
TPR
Bit(s)
31:0
7.19.47
Initial Value
0x0
Description
Number of all packets received.
Total Packets Transmitted - TPT (0x40D4; RC)
This register counts the total number of all packets transmitted. All packets transmitted are counted in
this register, regardless of their length, or whether they are flow control packets.
Partial packet transmissions (collisions in half-duplex mode) are not included in this register. This
register only increments if transmits are enabled (TCTL.EN is set). This register counts all packets,
including standard packets, secure packets, packets received over the SMBus, and packets generated
by the PT function.
Field
TPT
Bit(s)
31:0
7.19.48
Initial Value
0x0
Description
Number of all packets transmitted.
Packets Transmitted [64 Bytes] Count PTC64 (0x40D8; RC)
This register counts the number of packets transmitted that are exactly 64 bytes (from <Destination
Address> through <CRC>, inclusive) in length. Partial packet transmissions (collisions in half-duplex
mode) are not included in this register. This register does not include transmitted flow control packets
(which are 64 bytes in length). This register only increments if transmits are enabled (TCTL.EN is set).
This register counts all packets, including standard packets, secure packets, packets received over the
SMBus, and packets generated by the PT function.
Field
PTC64
Revision: 2.50
October 2011
Bit(s)
31:0
Initial Value
0x0
Description
Number of packets transmitted that are 64 bytes in length.
Intel® 82580EB/82580DB Gigabit Ethernet Controller
Datasheet
405
Intel® 82580EB/82580DB GbE Controller — Packets Transmitted [65—127 Bytes] Count - PTC127
(0x40DC; RC)
7.19.49
Packets Transmitted [65—127 Bytes] Count PTC127 (0x40DC; RC)
This register counts the number of packets transmitted that are 65-127 bytes (from <Destination
Address> through <CRC>, inclusive) in length. Partial packet transmissions (for example, collisions in
half-duplex mode) are not included in this register. This register only increments if transmits are
enabled (TCTL.EN is set). This register counts all packets, including standard packets, secure packets,
packets received over the SMBus, and packets generated by the PT function.
Field
PTC127
7.19.50
Bit(s)
31:0
Initial Value
0x0
Description
Number of packets transmitted that are 65-127 bytes in length.
Packets Transmitted [128—255 Bytes] Count PTC255 (0x40E0; RC)
This register counts the number of packets transmitted that are 128-255 bytes (from <Destination
Address> through <CRC>, inclusive) in length. Partial packet transmissions (collisions in half-duplex
mode) are not included in this register. This register only increments if transmits are enabled (TCTL.EN
is set). This register counts all packets, including standard packets, secure packets, packets received
over the SMBus, and packets generated by the PT function.
Field
PTC255
7.19.51
Bit(s)
31:0
Initial Value
0x0
Description
Number of packets transmitted that are 128-255 bytes in length.
Packets Transmitted [256—511 Bytes] Count PTC511 (0x40E4; RC)
This register counts the number of packets transmitted that are 256-511 bytes (from <Destination
Address> through <CRC>, inclusive) in length. Partial packet transmissions (for example, collisions in
half-duplex mode) are not included in this register. This register only increments if transmits are
enabled (TCTL.EN is set). This register counts all packets, including standard and secure packets.
Management packets must never be more than 200 bytes.
Field
PTC511
7.19.52
Bit(s)
31:0
Initial Value
0x0
Description
Number of packets transmitted that are 256-511 bytes in length.
Packets Transmitted [512—1023 Bytes] Count PTC1023 (0x40E8; RC)
This register counts the number of packets transmitted that are 512-1023 bytes (from <Destination
Address> through <CRC>, inclusive) in length. Partial packet transmissions (for example, collisions in
half-duplex mode) are not included in this register. This register only increments if transmits are
enabled (TCTL.EN is set). This register counts all packets, including standard and secure packets.
Management packets must never be more than 200 bytes.
Field
PTC1023
Bit(s)
31:0
Initial Value
0x0
Intel® 82580EB/82580DB Gigabit Ethernet Controller
Datasheet
406
Description
Number of packets transmitted that are 512-1023 bytes in length.
Revision: 2.50
October 2011
Packets Transmitted [1024 Bytes or Greater] Count - PTC1522 (0x40EC; RC) — Intel® 82580EB/
82580DB GbE Controller
7.19.53
Packets Transmitted [1024 Bytes or Greater] Count PTC1522 (0x40EC; RC)
This register counts the number of packets transmitted that are 1024 or more bytes (from <Destination
Address> through <CRC>, inclusive) in length. Partial packet transmissions (for example, collisions in
half-duplex mode) are not included in this register. This register only increments if transmits are
enabled (TCTL.EN is set).
Due to changes in the standard for maximum frame size for VLAN tagged frames in 802.3, the
82580EB/DB transmits packets that have a maximum length of 1522 bytes. The RMON statistics
associated with this range has been extended to count 1522 byte long packets. This register counts all
packets, including standard and secure packets (management packets must never be more than 200
bytes). If CTRL.EXT_VLAN is set, packets up to 1526 bytes are counted by this counter.
Field
PTC1522
7.19.54
Bit(s)
31:0
Initial Value
0x0
Description
Number of packets transmitted that are 1024 or more bytes in length.
Multicast Packets Transmitted Count MPTC (0x40F0; RC)
This register counts the number of multicast packets transmitted. This register does not include flow
control packets and increments only if transmits are enabled (TCTL.EN is set). Counts clear as well as
secure traffic.
Field
MPTC
7.19.55
Bit(s)
31:0
Initial Value
0x0
Description
Number of multicast packets transmitted.
Broadcast Packets Transmitted Count BPTC (0x40F4; RC)
This register counts the number of broadcast packets transmitted. This register only increments if
transmits are enabled (TCTL.EN is set). This register counts all packets, including standard and secure
packets (management packets must never be more than 200 bytes).
Field
BPTC
Revision: 2.50
October 2011
Bit(s)
31:0
Initial Value
0x0
Description
Number of broadcast packets transmitted count.
Intel® 82580EB/82580DB Gigabit Ethernet Controller
Datasheet
407
Intel® 82580EB/82580DB GbE Controller — TCP Segmentation Context Transmitted Count - TSCTC
(0x40F8; RC)
7.19.56
TCP Segmentation Context Transmitted Count TSCTC (0x40F8; RC)
This register counts the number of TCP segmentation offload transmissions and increments once the
last portion of the TCP segmentation context payload is segmented and loaded as a packet into the onchip transmit buffer. Note that it is not a measurement of the number of packets sent out (covered by
other registers). This register only increments if transmits and TCP segmentation offload are enabled.
This counter only counts pure TSO transmissions.
Field
TSCTC
7.19.57
Bit(s)
31:0
Initial Value
0x0
Description
Number of TCP Segmentation contexts transmitted count.
Interrupt Assertion Count - IAC (0x4100; RC)
This counter counts the total number of LAN interrupts generated in the system. In case of MSI-X
systems, this counter reflects the total number of MSI-X messages that are emitted.
Field
IAC
Bit(s)
31:0
7.19.58
7.19.59
Bit(s)
31:0
This is a count of all the LAN interrupt assertions that have occurred.
Initial Value
0x0
Description
This is a count of all the received packets sent to the host.
Host Good Packets Transmitted Count HGPTC (0x4118; RC)
Field
HGPTC
0x0
Description
Rx Packets to Host Count - RPTHC (0x4104; RC)
Field
RPTHC
Initial Value
Bit(s)
31:0
Initial Value
0x0
Description
Number of good packets transmitted by the host.
This register counts the number of good (non-erred) packets transmitted sent by the host. A good
transmit packet is considered one that is 64 or more bytes in length (from <Destination Address>
through <CRC>, inclusively) in length. This does not include transmitted flow control packets or
packets sent by the manageability engine. This register only increments if transmits are enabled
(TCTL.EN is set).
Intel® 82580EB/82580DB Gigabit Ethernet Controller
Datasheet
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Revision: 2.50
October 2011
Receive Descriptor Minimum Threshold Count - RXDMTC (0x4120; RC) — Intel® 82580EB/82580DB GbE
Controller
7.19.60
Field
RXDMTC
Receive Descriptor Minimum Threshold Count RXDMTC (0x4120; RC)
Bit(s)
31:0
Initial Value
0x0
Description
This is a count of the receive descriptor minimum threshold events
This register counts the number of events where the number of descriptors in one of the Rx queues was
lower than the threshold defined for this queue.
7.19.61
Field
HGORCL
7.19.62
Field
HGORCH
Host Good Octets Received Count - HGORCL (0x4128; RC)
Bit(s)
31:0
Initial Value
0x0
Description
Number of good octets received by host – lower 4 bytes
Host Good Octets Received Count - HGORCH (0x412C; RC)
Bit(s)
31:0
Initial Value
0x0
Description
Number of good octets received by host – upper 4 bytes
These registers make up a logical 64-bit register which counts the number of good (non-erred) octets
received. This register includes bytes received in a packet from the <Destination Address> field
through the <CRC> field, inclusive. This register must be accessed using two independent 32-bit
accesses.; HGORCL must be read before HGORCH.
In addition, it sticks at 0xFFFF_FFFF_FFFF_FFFF when the maximum value is reached. Only packets that
pass address filtering are counted in this register. This register counts only octets of packets that
reached the host. The only exception is packets dropped by the DMA because of lack of descriptors in
one of the queues. These packets are included in this counter.
This register only increments if receives are enabled (RCTL.RXEN is set).
7.19.63
Field
HGOTCL
Revision: 2.50
October 2011
Host Good Octets Transmitted Count HGOTCL (0x4130; RC)
Bit(s)
31:0
Initial Value
0x0
Description
Number of good octets transmitted by host – lower 4 bytes
Intel® 82580EB/82580DB Gigabit Ethernet Controller
Datasheet
409
Intel® 82580EB/82580DB GbE Controller — Host Good Octets Transmitted Count - HGOTCH (0x4134;
RC)
7.19.64
Field
HGOTCH
Host Good Octets Transmitted Count HGOTCH (0x4134; RC)
Bit(s)
31:0
Initial Value
0x0
Description
Number of good octets transmitted by host – upper 4 bytes
These registers make up a logical 64-bit register which counts the number of good (non-erred) packets
transmitted. This register must be accessed using two independent 32-bit accesses. This register resets
whenever the upper 32 bits are read (HGOTCH).
In addition, it sticks at 0xFFFF_FFFF_FFFF_FFFF when the maximum value is reached. This register
includes bytes transmitted in a packet from the <Destination Address> field through the <CRC> field,
inclusive. This register counts octets in successfully transmitted packets which are 64 or more bytes in
length. This register only increments if transmits are enabled (TCTL.EN is set). The register counts clear
as well as secure octets.
These octets do not include octets in transmitted flow control packets or manageability packets.
7.19.65
Length Error Count - LENERRS (0x4138; RC)
Field
LENERRS
Bit(s)
Initial Value
31:0
0x0
Description
Length error count.
Counts the number of receive packets with Length errors. For example, valid packets (no CRC error)
with a length/Type field with a value smaller or equal to 1500 greater than the frame size. In order for
a packet to be counted in this register, it must pass address filtering and must be 64 bytes or greater
(from <Destination Address> through <CRC>, inclusive) in length. If receives are not enabled, then
this register does not increment.
7.19.66
SerDes/SGMII/KX Code Violation Packet Count SCVPC (0x4228; RW)
This register contains the number of code violation packets received. Code violation is defined as an
invalid received code in the middle of a packet.
Field
CODEVIO
Bit(s)
31:0
Initial Value
0x0
Description
Code Violation Packet Count: At any point of time this field specifies number of
unknown protocol packets received. Valid only in SGMII/SerDes/1000BASE-KX modes.
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October 2011
Switch Drop Packet Count - SDPC (0x41A4; RC) — Intel® 82580EB/82580DB GbE Controller
7.19.67
Switch Drop Packet Count - SDPC (0x41A4; RC)
Field
SDPC
Bit(s)
31:0
7.19.68
Initial Value
0x0
Description
Switch Drop Packet Count: This register counts Rx packets dropped at the pool
selection stage of the switch or by the storm control mechanism. For example, packets
that where not routed to any of the pools and the VT_CTL.Dis_Def_Pool is set. Valid
only in VMDq mode.
Virtualization Statistical Counters
supports 5 statistical counters per queue to reduce processing overhead in virtualization
operating mode.
The 82580EB/DB
7.19.68.1
Per Queue Good Packets Received Count - “VFGPRC
(0x10010 + n*0x100 [n=0...7]; RO)
This register counts the number of legal length good packets received in queue[n]. The legal length for
the received packet is defined by the value of Long Packet Enable (RCTL.LPE) (see Section 7.19.37).
This register does not include received flow control packets and only counts packets that pass filtering.
This register only increments if receive is enabled.
Note:
VFGPRC may count packets interrupted by a link disconnect although they have a CRC
error.
Unlike some other statistics registers that are not allocated per VM, this register is not
cleared on read. Furthermore, the register wraps around back to 0x0000 on the next
increment when reaching a value of 0xFFFF and then continues normal count operation.
Field
GPRC
Bit(s)
31:0
7.19.68.2
Initial Value
0x0
Description
Number of good packets received (of any length).
Per Queue Good Packets Transmitted Count VFGPTC (0x10014 + n*0x100 [n=0...7]; RO)
This register counts the number of good (no errors) packets transmitted on queue[n]. A good transmit
packet is considered one that is 64 or more bytes in length (from <Destination Address> through
<CRC>, inclusively) in length. This does not include transmitted flow control packets. This register only
increments if transmits are enabled (TCTL.EN is set). The register counts clear as well as secure
packets. This counter includes loopback packets or packets later dropped by the MAC.
Note:
Unlike some other statistic registers that are not allocated per VM, this register is not
cleared on read. Furthermore, the register wraps around back to 0x0000 on the next
increment when reaching a value of 0xFFFF and then continues normal count operation.
Field
GPTC
Revision: 2.50
October 2011
Bit(s)
31:0
Initial Value
0x0
Description
Number of good packets transmitted.
Intel® 82580EB/82580DB Gigabit Ethernet Controller
Datasheet
411
Intel® 82580EB/82580DB GbE Controller — Virtualization Statistical Counters
7.19.68.3
Per Queue Good Octets Received Count VFGORC (0x10018 + n*0x100 [n=0...7]; RO)
This register counts the number of good (no errors) octets received on queue[n]. This register includes
bytes received in a packet from the <Destination Address> field through the <CRC> field, inclusive.
Only octets of packets that pass address filtering are counted in this register. This register only
increments if receive is enabled.
Note:
Unlike some other statistic registers that are not allocated per VM, this register is not
cleared on read. Furthermore, the register wraps around back to 0x0000 on the next
increment when reaching a value of 0xFFFF and then continues normal count operation.
Field
GORC
Bit(s)
31:0
7.19.68.4
Initial Value
0x0
Description
Number of good octets received.
Per Queue Good Octets Transmitted Count VFGOTC (0x10034 + n*0x100 [n=0...7]; RO)
This register counts the number of good (no errors) packets transmitted on queue[n]. This register
includes bytes transmitted in a packet from the <Destination Address> field through the <CRC> field,
inclusive. Register also counts any padding and VLAN tag that were added by the hardware. This
register counts octets in successfully transmitted packets that are 64 or more bytes in length. Octets
counted do not include octets in transmitted flow control packets. This register only increments if
transmit is enabled.
Note:
Unlike some other statistic registers that are not allocated per VM, this register is not
cleared on read. Furthermore, the register wraps around back to 0x0000 on the next
increment when reaching a value of 0xFFFF and then continues normal count operation.
Field
GOTC
Bit(s)
31:0
7.19.68.5
Initial Value
0x0
Description
Number of good octets transmitted – lower 4 bytes.
Per Queue Multicast Packets Received Count VFMPRC (0x10038 + n*0x100 [n=0...7]; RO)
This register counts the number of good (no errors) multicast packets received on queue[n]. This
register does not count multicast packets received that fail to pass address filtering nor does it count
received flow control packets. This register only increments if receive is enabled.
Note:
Unlike some other statistic registers that are not allocated per VM, this register is not
cleared on read. Furthermore, the register wraps around back to 0x0000 on the next
increment when reaching a value of 0xFFFF and then continues normal count operation.
Field
MPRC
Bit(s)
31:0
Initial Value
0x0
Intel® 82580EB/82580DB Gigabit Ethernet Controller
Datasheet
412
Description
Number of multicast packets received.
Revision: 2.50
October 2011
Manageability statistics — Intel® 82580EB/82580DB GbE Controller
7.20
Manageability statistics
This section describes a set of statistics counters used by the NC-SI interface and are not accessible to
the host driver.
7.20.1
BMC Management Packets Dropped Count BMPDC (0x4140; RC)
This register counts the total number of packets received that pass the management filters as
described in Section 11.4, that are dropped because the management receive FIFO is full. Management
packets include any packet directed to the manageability console (for example, BMC and ARP packets).
This register is available to the firmware only.
Field
MPDC
7.20.2
Bit(s)
31:0
Initial Value
0x0
Description
Number of management packets dropped.
BMC Management Packets Transmitted Count BMNGPTC (0x4144; RC)
This register counts the total number of transmitted packets originating from the manageability path.
This register is available to the firmware only.
Field
MPTC
7.20.3
Bit(s)
31:0
Initial Value
0x0
Description
Number of management packets transmitted.
BMC Management Packets Received Count BMNGPRC (0x413C; RC)
This register counts the total number of packets received that pass the management filters as
described in Section 11.4. Any packets with errors are not counted, except packets that are dropped
because the management receive FIFO is full. This register is available to the firmware only.
Field
MNGPRC
7.20.4
Bit(s)
31:0
Initial Value
0x0
Description
Number of management packets received.
BMC Total Unicast Packets Received BUPRC (0x4400; RC)
This register counts the number of good (no errors) unicast packets received. This register does not
count unicast packets received that fail to pass address filtering. This register only increments if
receives are enabled (RCTL.RXEN is set). This register does not count packets counted by the Missed
Packet Count (MPC) register. Packets sent to the manageability engine are included in this counter.
This register is available to the firmware only.
Revision: 2.50
October 2011
Intel® 82580EB/82580DB Gigabit Ethernet Controller
Datasheet
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Intel® 82580EB/82580DB GbE Controller — BMC Total Multicast Packets Received - BMPRC (0x4404;
RC)
Field
BUPRC
7.20.5
Bit(s)
31:0
Initial Value
0x0
Description
Number of Unicast packets received.
BMC Total Multicast Packets Received BMPRC (0x4404; RC)
This register counts the same events as the MPRC register (Section 7.19.28) for the BMC usage. This
register is available to the firmware only.
7.20.6
BMC Total Broadcast Packets Received BBPRC (0x4408; RC)
This register counts the same events as the BPRC register (Section 7.19.27) for the BMC usage. This
register is available to the firmware only.
7.20.7
BMC Total Unicast Packets Transmitted BUPTC (0x440C; RC)
This register counts the number of unicast packets transmitted. This register increments only if
transmits are enabled (TCTL.EN is set). This register is available to the firmware only
Field
BUPTC
7.20.8
Bit(s)
31:0
Initial Value
0x0
Description
Number of unicast packets transmitted.
BMC Total Multicast Packets Transmitted BMPTC (0x4410; RC)
This register counts the same events as the MPTC register (Section 7.19.54) for the BMC usage. This
register increments only if transmits are enabled (TCTL.EN is set). This register is available to the
firmware only.
7.20.9
BMC Total Broadcast Packets Transmitted BBPTC (0x4414; RC)
This register counts the same events as the BPTC register (Section 7.19.55) for the BMC usage. This
register increments only if transmits are enabled (TCTL.EN is set). This register is available to the
firmware only.
7.20.10
BMC FCS Receive Errors - BCRCERRS (0x4418; RC)
This register counts the same events as the CRCERRS register (Section 7.19.1) for the BMC usage. This
register increments only if transmits are enabled (TCTL.EN is set). This register is available to the
firmware only.
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Revision: 2.50
October 2011
BMC Alignment Errors - BALGNERRC (0x441C; RC) — Intel® 82580EB/82580DB GbE Controller
7.20.11
BMC Alignment Errors - BALGNERRC (0x441C; RC)
This register counts the same events as the ALGNERRC register (Section 7.19.2) for the BMC usage.
This register increments only if transmits are enabled (TCTL.EN is set).This register is available to the
firmware only.
7.20.12
BMC Pause XON Frames Received BXONRXC (0x4420; RC)
This register counts the same events as the XONRXC register (Section 7.19.15) for the BMC usage. This
register increments only if transmits are enabled (TCTL.EN is set). This register is available to the
firmware only.
7.20.13
BMC Pause XOFF Frames Received BXOFFRXC (0x4424; RC)
This register counts the same events as the XOFFRXC register (Section 7.19.17) for the BMC usage.
This register increments only if transmits are enabled (TCTL.EN is set). This register is available to the
firmware only.
7.20.14
BMC Pause XON Frames Transmitted BXONTXC (0x4428; RC)
This register counts the same events as the XONTXC register (Section 7.19.16) for the BMC usage. This
register increments only if transmits are enabled (TCTL.EN is set). This register is available to the
firmware only.
7.20.15
BMC Pause XOFF Frames Transmitted BXOFFTXC (0x442C; RC)
This register counts the same events as the XOFFTXC register (Section 7.19.18) for the BMC usage.
This register increments only if transmits are enabled (TCTL.EN is set). This register is available to the
firmware only.
7.20.16
BMC Single Collision Transmit FramesBSCC (0x4430; RC)
This register counts the same events as the SCC register (Section 7.19.6) for the BMC usage. This
register increments only if transmits are enabled (TCTL.EN is set). This register is available to the
firmware only.
7.20.17
BMC Multiple Collision Transmit Frames BMCC (0x4434; RC)
This register counts the same events as the MCC register (Section 7.19.8) for the BMC usage. This
register increments only if transmits are enabled (TCTL.EN is set). This register is available to the
firmware only.
Revision: 2.50
October 2011
Intel® 82580EB/82580DB Gigabit Ethernet Controller
Datasheet
415
Intel® 82580EB/82580DB GbE Controller — Wake Up Control Register Descriptions
7.21
Wake Up Control Register Descriptions
7.21.1
Wakeup Control Register - WUC (0x5800; R/W)
The PME_En and PME_Status bits of this register are reset when LAN_PWR_GOOD is 0b. When
AUX_PWR = 0b, this register is also reset by de-asserting PE_RST_N and during a D3 to D0 transition.
The other bits are reset using the standard internal resets.
Field
Bit(s)
APME
Initial Value
1
0
Description
Advance Power Management Enable
0b
If set to 1b, APM Wakeup is enabled.
If this bit is set and the APMPME bit is cleared, reception of a magic packet asserts the
WUS.MAG bit but does not assert a PME.
PME_En
1
0b
PME_En
This read/write bit is used by the software device driver to enable generation of a PME
event without writing to the Power Management Control / Status Register (PMCSR) in
the PCIe configuration space.
Note: Bit reflects value of PMCSR.PME_En bit when the bit in the PMCSR register is
modified. However when value of WUC.PME_En bit is modified by software device driver,
value is not reflected in the PMCSR.PME_En bit.
PME_Status (R/
W1C)
2
APMPME
3
0b
PME_Status
This bit is set when the 82580EB/DB receives a wakeup event. It is the same as the
PME_Status bit in the Power Management Control / Status Register (PMCSR). Writing a
1b to this bit clears also the PME_Status bit in the PMCSR.
0b1
Assert PME On APM Wakeup
If set to 1b, the 82580EB/DB sets the PME_Status bit in the Power Management Control
/ Status Register (PMCSR) and asserts PE_WAKE_N and sends a PM_PME PCIe message
when APM Wakeup is enabled (WUC.APME = 1) and the 82580EB/DB receives a
matching Magic Packet.
Note: When WUC.APMPME is set PE_WAKE_N is asserted and a PM_PME message is sent
even if PMCSR.PME_En is cleared.
Reserved
31:4
0x0
Reserved
1. Loaded from the EEPROM.
7.21.2
Wakeup Filter Control Register - WUFC (0x5808; R/W)
This register is used to enable each of the pre-defined and flexible filters for wakeup support. A value of
1b means the filter is turned on.; A value of 0b means the filter is turned off.
If the NoTCO bit is set, then any packet that passes the manageability packet filtering as described in
Section 11.4, does not cause a Wake Up event even if it passes one of the Wake Up Filters. This bit is
set at initialization and during any EEPROM read if the SMBus Enable bit of the EEPROM's Management
Control word is 1b. Otherwise its initial value is 0b.
Field
LNKC
Bit(s)
0
Initial Value
0b
Description
Link Status Change Wakeup Enable.
MAG
1
0b
Magic Packet Wakeup Enable.
EX
2
0b
Directed Exact Wakeup Enable.1
MC
3
0b
Directed Multicast Wakeup Enable.
BC
4
0b
Broadcast Wakeup Enable.
Intel® 82580EB/82580DB Gigabit Ethernet Controller
Datasheet
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Revision: 2.50
October 2011
Wakeup Status Register - WUS (0x5810; R/W1C) — Intel® 82580EB/82580DB GbE Controller
Field
Bit(s)
Initial Value
Description
ARP
5
0b
ARP Request Packet Wakeup Enable.
IPv4
6
0b
Directed IPv4 Packet Wakeup Enable.
IPv6
7
0b
Directed IPv6 Packet Wakeup Enable.
Reserved
13:8
0b
Reserved. Set these bits to 0b.
FLEX_HQ
14
0b
Flex filters Host Queuing
0 - Do not use Flex filters for queueing decisions in D0 state.
1 - Use flex filters in queuing decisions in D0 state.
Note: Should be enabled only when multi queueing is enabled
(MRQC.Multiple Receive Queues = 010b or 000b).
NoTCO
15
0b
Ignore TCO/management packets for wake up.
FLX0
16
0b
Flexible Filter 0 Enable.
FLX1
17
0b
Flexible Filter 1 Enable.
FLX2
18
0b
Flexible Filter 2 Enable.
FLX3
19
0b
Flexible Filter 3 Enable.
FLX4
20
0b
Flexible Filter 4 Enable.
FLX5
21
0b
Flexible Filter 5 Enable.
FLX6
22
0b
Flexible Filter 6 Enable.
FLX7
23
0b
Flexible Filter 7 Enable.
Reserved
31:24
0x0
Reserved.
1. If the RCTL.UPE is set, and the EX bit is set also, any unicast packet wakes up the system.
7.21.3
Wakeup Status Register - WUS (0x5810; R/W1C)
This register is used to record statistics about all wakeup packets received. If a packet matches multiple
criteria then multiple bits could be set. Writing a 1b to any bit clears that bit.
This register is not cleared when RST# is asserted. It is only cleared when LAN_PWR_GOOD is deasserted or when cleared by the software device driver.
Field
LNKC
Bit(s)
0
Initial Value
0b
Description
Link Status Change.
MAG
1
0b
Magic Packet Received.
EX
2
0b
Directed Exact Packet Received
The packet’s address matched one of the 16 pre-programmed exact values in the
Receive Address registers.
MC
3
0b
Directed Multicast Packet Received
The packet was a multicast packet hashed to a value that corresponded to a 1 bit in
the Multicast Table Array.
BC
4
0b
Broadcast Packet Received.
ARP
5
0b
ARP Request Packet Received.
IPv4
6
0b
Directed IPv4 Packet Received.
IPv6
7
0b
Directed IPv6 Packet Received.
MNG
8
0b
Indicates that a manageability event that should cause a PME happened.
Reserved
15:9
0x0
Reserved.
Write 0, ignore on read.
FLX01
Revision: 2.50
October 2011
16
0b
Flexible Filter 0 Match.
Intel® 82580EB/82580DB Gigabit Ethernet Controller
Datasheet
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Intel® 82580EB/82580DB GbE Controller — Wakeup Packet Length - WUPL (0x5900; RO)
Field
Bit(s)
Initial Value
Description
FLX11
17
0b
Flexible Filter 1 Match.
FLX21
18
0b
Flexible Filter 2 Match.
FLX31
19
0b
Flexible Filter 3 Match.
FLX41
20
0b
Flexible Filter 4 Match.
FLX51
21
0b
Flexible Filter 5 Match.
FLX61
22
0b
Flexible Filter 6 Match.
1
FLX7
23
0b
Flexible Filter 7 Match.
Reserved
31:24
0x0
Reserved.
Write 0, ignore on read.
1. Bit is set only when flex filter match is detected and WUFC.FLEX_HQ is 0.
7.21.4
Wakeup Packet Length - WUPL (0x5900; RO)
This register indicates the length of the first wakeup packet received. It is valid if one of the bits in the
Wakeup Status register (WUS) is set. It is not cleared by any reset.
Field