3 phase controller for VR10, VR9 and K8 CPUs

3 phase controller for VR10, VR9 and K8 CPUs
L6701
3 Phase Controller for VR10, VR9 and K8 CPUs
Features
■
MULTI-DAC: VR9, VR10 AND K8 DAC
SELECTABLE THROUGH SINGLE PIN
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Applications
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■
0.7% OUTPUT VOLTAGE ACCURACY
■
ADJUSTABLE REFERENCE OFFSET
■
HIGH CURRENT INTEGRATED DRIVERS
■
DYNAMIC VID MANAGEMENT
■
ACCURATE FULLY-DIFFERENTIAL LOADLINE CURRENT-SENSE ACROSS MAIN
INDUCTORS MAKES BOM INDEPENDENT
ON THE LAYOUT
PowerSSO-36
L6701 is an extremely simple, low-cost solution to
implement a three phase step-down controller
with integrated high-current drivers in a compact
PowerSSO-36 package with exposed pad.
■
PRECISE CURRENT-SHARING AND OCP
ACROSS LS MOSFETS
■
CONSTANT OVER-CURRENT PROTECTION
■
FEEDBACK DISCONNECTION
PROTECTION
■
PRELIMINARY OV PROTECTION
■
OSCILLATOR INTERNALLY FIXED AT
100kHz (300kHz RIPPLE) EXT ADJUSTABLE
■
SS_END / PGOOD SIGNAL
■
INTEGRATED REMOTE-SENSE BUFFER
■
PWSSO36 PACKAGE WITH EXPOSED PAD
■
HIGH CURRENT VRM / VRD FOR DESKTOP
/ SERVER/ WORKSTATION CPUs
■
HIGH DENSITY DC / DC CONVERTERS
The device embeds three selectable DACs: with a
single pin it is possible to program the device to
work in compatibility with VR9, VR10 or K8
applications managing D-VID with ±0.7% output
voltage accuracy over line and temperature
variations. Additional programmable offset can be
added to the reference voltage with a single
external resistor.
Fast protection against load over current let the
system works in Constant Current mode until
UVP. Preliminary OVP allows full load protection
in case of startup with failed HS. Furthermore,
feedback disconnection prevents from damaging
the load in case of misconnections in the system
board.
Combined use of DCR and RDS(on) current
sensing assures precision in voltage positioning
and safe current sharing and OCP per each
phase.
Order codes
Part number
Package
Packing
L6701
PowerSSO-36
Tube
L6701TR
PowerSSO-36
Tape & Reel
December 2005
Rev 1
1/44
www.st.com
44
L6701
Contents
1
Device Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
2
Pins description and connection diagrams . . . . . . . . . . . . . . . . . . . . . . . . 5
2.1
3
Pin description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
Maximum Ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
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4
3.1
Absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
3.2
Thermal data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
Electrical specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
4.1
5
Electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
Typical application circuit and block diagram . . . . . . . . . . . . . . . . . . . . . 11
5.1
Application circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .11
5.2
Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
6
VID Tables . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
7
Configuring the Device: DAC Selection . . . . . . . . . . . . . . . . . . . . . . . . . . 17
7.1
8
Driver Section . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
8.1
9
10
2/44
Single-Wire CPU Automatic Detection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
Power Dissipation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
Current Sharing Loop and Current Reading . . . . . . . . . . . . . . . . . . . . . . . 20
9.1
Current Sharing Loop . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
9.2
Current Reading for Current Sharing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
Output Voltage Positioning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
10.1
Load-Line (Droop Function - Optional) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
10.2
Fully-Differential Load-Line (Droop Function - Optional) . . . . . . . . . . . . . . . 22
10.3
Offset (Optional) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
10.4
Remote Voltage Sense . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
10.5
Maximum Duty Cycle limitation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
L6701
11
Dynamic VID Transitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
12
Soft Start . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
12.1
13
Low-Side-Less Startup (LSLess) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
Output voltage Monitor and Protections . . . . . . . . . . . . . . . . . . . . . . . . . . 29
13.1
Under Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
13.2
Preliminary Over Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
13.3
Over Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
13.4
Feedback Disconnection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
13.5
PGOOD (Only for VR9 and K8 Modes) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
13.6
Over Current Protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
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14
Oscillator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
15
System Control Loop Compensation . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35
15.1
16
Compensation Network Guidelines . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37
Layout Guidelines . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38
16.1
Power Components and Connections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38
16.2
Small Signal Components and Connections . . . . . . . . . . . . . . . . . . . . . . . . . 39
16.3
Embedding L6701-based VRs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40
17
Package Mechanical Data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41
18
Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43
3/44
1 Device Description
1
L6701
Device Description
L6701 is multi-phase PWM controller with embedded high-current drivers that provides
complete control logic and protections for a high-performance step-down DC-DC voltage
regulator, optimized for advanced microprocessor power supply. Multi-phase buck is the
simplest and most cost-effective topology employable to satisfy the increasing current demand
of newer microprocessors and the modern high-current DC/DC converters and POLs
requirements. It allows distributing equally load and power between the phases using smaller,
cheaper and most common external power MOSFETs and inductors. Moreover, thanks to the
equal phase-shift between each phase, the input and output capacitor count results in being
reduced. Phase-interleaving causes in fact input rms current and output ripple voltage
reduction and shows an effective output switching frequency increase: the 100kHz free-running
frequency per phase, externally adjustable through a resistor, results multiplied on the output
by the number of phases so reaching 300kHz in free-running.
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L6701 includes multiple DACs, selectable through an apposite pin, allowing compatibility with
both Intel VR9, VR10 and AMD Hammer specifications, also performing D-VID transitions
accordingly. In particular for Intel CPUs, it allows to automatically recognize the CPU with a
single-wire connection, without any additional external component, by proper connecting the
selector pin to the proper CPU pin.
Precise voltage positioning (LL) is possible thanks to an accurate fully-differential current-sense
across the main inductors still using only two pins for current-reading (pat. pend.): this makes
any BOM insensitive to the board layout saving time in the design stage.
The device internally balance the current driven by each phase by sensing the voltage drop
across the LS MOSFET RDS(on). OC protection is effective with a threshold for each phase
causing the device to work in constant-current mode.
The controller provides output voltage protections to avoid any load damage due to failed
components and/or feedback misconnections. Over-Voltage protects the load from dangerous
over stress latching immediately the device by turning-on the lower driver and driving high the
FAULT pin. Furthermore, preliminary-OVP protection also allows the device to protect the load
from dangerous OVP when VCC is not above the UVLO threshold. Under-Voltage protection
causes the device to stop switching when set while Over-Current protection, with a threshold
for each phase, causes the device to enter in constant current mode until the latched UVP.
L6701 implements soft-start increasing the reference up to the final value in 2048 clock cycles
in closed loop regulation. Low-Side-Less feature allows the device to perform soft-start over
pre-biased output avoiding dangerous current return through the main inductors as well as
negative spike at the load side.
The compact PowerSSO-36 package with exposed thermal pad allows dissipating the power to
drive the external MOSFET through the system board.
4/44
L6701
2
2 Pins description and connection diagrams
Pins description and connection diagrams
Figure 1.
Pins connection (Top view)
SGND
VCC
LGATE1
PGND
LGATE2
LGATE3
BOOT1
UGATE1
PHASE1
BOOT2
UGATE2
PHASE2
BOOT3
UGATE3
PHASE3
SSEND / PGOOD
DAC_SEL
OSC / EN / FAULT
1
36
2
35
3
34
4
33
5
32
6
31
7
30
8
29
9
28
COMP
FB
VSEN
CSCS+
ISEN1
ISEN2
ISEN3
FBG
FBR
VID5
VID0
VID1
VID2
VID3
VID4
REF_OUT
REF_IN
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2.1
Pin description
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Table 1.
10
27
11
26
12
25
13
24
14
23
15
22
16
21
17
20
18
19
Pins description
Pin n°
Name
1
SGND
2
VCC
3
LGATE1
4
PGND
5
LGATE2
Channel 2 LS Driver Output.
A small series resistor helps in reducing device-dissipated power.
6
LGATE3
Channel 3 LS Driver Output.
A small series resistor helps in reducing device-dissipated power.
7
BOOT1
Channel 1 HS driver supply.
Connect through a capacitor (100nF typ.) to PHASE1 and provide necessary
Bootstrap diode.
A small series resistor upstream the boot diode helps in reducing Boot capacitor
overcharge.
8
UGATE1
Channel 1 HS driver output.
A small series resistors helps in reducing device-dissipated power.
9
PHASE1
Channel 1 HS driver return path.
It must be connected to the HS1 MOSFET source and provides return path for
the HS driver of channel 1.
Function
All the internal references are referred to this pin. Connect to the PCB Signal
Ground.
Device Power Supply and LS driver supply.
Operative voltage is 12V ±15%. Filter with at least 1µF MLCC vs. ground.
Channel 1 LS Driver Output.
A small series resistor helps in reducing device-dissipated power.
LS Drivers return path. Connect to Power ground Plane.
5/44
L6701
2 Pins description and connection diagrams
Table 1.
Pin n°
Pins description (continued)
Name
Function
10
BOOT2
Channel 2 HS driver supply.
Connect through a capacitor (100nF typ.) to PHASE2 and provide necessary
Bootstrap diode.
A small series resistor upstream the boot diode helps in reducing Boot capacitor
overcharge.
11
UGATE2
Channel 2 HS driver output.
A small series resistors helps in reducing device-dissipated power.
12
PHASE2
Channel 2 HS driver return path.
It must be connected to the HS2 MOSFET source and provides return path for
the HS driver of channel 2.
13
BOOT3
Channel 3 HS driver supply.
Connect through a capacitor (100nF typ.) to PHASE3 and provide necessary
Bootstrap diode.
A small series resistor upstream the boot diode helps in reducing Boot capacitor
overcharge.
14
UGATE3
Channel 3 HS driver output.
A small series resistors helps in reducing device-dissipated power.
15
PHASE3
Channel 3 HS driver return path.
It must be connected to the HS3 MOSFET source and provides return path for
the HS driver of channel 3.
SSEND /
PGOOD
SSEND - Intel VR10 Mode. Soft Start END Signal.
Open Drain Output set free after SS has finished and pulled low when triggering
any protection. Pull up to 5V (typ) or lower, if not used it can be left floating.
PGOOD - Intel VR9 & AMD Hammer Mode.
Open Drain Output set free after SS has finished and pulled low when VSEN is
lower than the relative threshold. Pull up to 5V (typ) or lower, if not used it can be
left floating.
DAC_SEL
DAC SELection pin.
It allows programming the DAC table for the regulation. Internally pulled-up to 5V.
Short to GND to program VR9 DAC, leave floating to program K8 DAC while
connect to GND through 82kΩ to program VR10 DAC.
Information about the selected DAC is latched before the system start-up. See
Section 7.1 for connections to enable CPU auto-detection.
OSC / EN /
FAULT
OSC: It allows programming the switching frequency FSW of each channel.
Switching frequency can be increased according to the resistor connected from
the pin vs. SGND with a gain of 4kHz/µA (see Section 14). Leaving the pin
floating it programs a switching frequency of 100kHz per phase (300kHz on the
load).
EN: Forced low, the device stops operations with all MOSFETs OFF: all the
protections are disabled except for Preliminary Over Voltage. When set low it
resets the device from any latching condition.
FAULT: The pin is forced high (5V) to signal an OVP / UVP FAULT: to recover
from this condition, cycle VCC or the OSC pin. See Section 13 for details.
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16
17
18
6/44
L6701
Table 1.
2 Pins description and connection diagrams
Pins description (continued)
Pin n°
Name
Function
19
REF_IN
Reference Input for the regulation.
Connect directly or through a resistor to the REF_OUT pin. See Section 10.3 for
details. This pin is used as input for the protections.
20
REF_OUT
Reference Output.
Connect directly or through a resistor to the REF_IN pin. See Section 10.3 for
details.
21 to 26
VID4
to
VID0, VID5
Voltage IDentification Pins.
Internally pulled up by 12.5µA to 5V, connect to SGND to program a '0' or leave
floating to program a '1'. They allow programming output voltage as specified in
Table 5, Table 6 and Table 7 according to DAC_SEL status.
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27
FBR
Remote Buffer Non Inverting Input.
Connect to the positive side of the load to perform remote sense.
See Section 16 for proper layout of this connection.
28
FBG
Remote Buffer Inverting Input.
Connect to the negative side of the load to perform remote sense.
See Section 16 for proper layout of this connection.
29 to 31
ISEN3
to
ISEN1
LS Current Sense Pins.
These pins are used for current balance phase-to-phase as well as for the
system OCP. Connect through a resistor RISEN to the relative PHASEx pin. See
Section 9 and Section 13.6 for details.
CS+
Droop Current Sense non-inverting input.
Connect through RPH-CPH network to the main inductors. Directly connect to
output voltage when Droop function is not required. See Section 10.1 and
Section 10.2 for details.
33
CS-
Droop Current Sense inverting input.
Connect through resistor RD to the main inductors common node. Leave floating
when Droop Function is not required. See Section 10.1 and Section 10.2 for
details.
This pin also monitors the output for any feedback disconnection. See
Section 13.4 for details.
34
VSEN
35
FB
36
COMP
PAD
THERMAL
PAD
32
Remote Buffer Output. It manages OVP and UVP protections and PGOOD
(when applicable). See Section 13 for details.
Error Amplifier Inverting Input. Connect with a resistor RFB vs. VSEN and with an
RF - C F toward COMP.
Error Amplifier Output. Connect with an RF - CF vs. FB.
The device cannot be disabled by pulling down this pin.
Thermal pad connects the Silicon substrate and makes good thermal contact
with the PCB to dissipate the power necessary to drive the external MOSFETs.
Connect to the PGND plane with several VIAs to improve thermal conductivity.
7/44
L6701
3 Maximum Ratings
3
Maximum Ratings
3.1
Absolute maximum ratings
Table 2.
Absolute Maximum Ratings
Symbol
Parameter
VCC
to PGND
15
V
VBOOTx - VPHASEx
Boot Voltage
15
V
15
V
-0.3 to VCC + 0.3
V
VID0 to VID5
-0.3 to 5
V
All other Pins to PGNDx
-0.3 to 7
V
26
V
TBD
V
Value
Unit
VUGATEx - V PHASEx
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3.2
Thermal data
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LGATEx, PHASEx, to PGNDx
VPHASEx
Table 3.
Positive Peak Voltage; T<20ns @ 600kHz
Negative Peak Voltage;
Thermal data
Symbol
Parameter
Value
Unit
RTHJA
Thermal Resistance Junction to Ambient
(Device soldered on 2s2p PC Board)
30
°C/W
RTHJC
Thermal Resistance Junction to Case
1
°C/W
TMAX
Maximum Junction Temperature
150
°C
TSTG
Storage Temperature Range
-40 to 150
°C
TJ
Junction Temperature Range
0 to 125
°C
3.3
W
PTOT
8/44
Maximum Power Dissipation at 25°C
(Device soldered on 2s2p PC Board)
L6701
4 Electrical specifications
4
Electrical specifications
4.1
Electrical characteristics
Table 4.
Symbol
Electrical Characteristics
(VCC = 12V±15%, TJ = 0°C to 70°C unless otherwise specified).
Parameter
Test conditions
Min.
Typ.
Max.
Unit
Supply Current and Power-ON
ICC
VCC Supply current
HGATEx and LGATEx = OPEN
BOOTx = 12V
17
mA
IBOOTx
BOOTx Supply Current
HGATEx = OPEN;
PHASEx to PGNDx; BOOTx = 12V
0.7
mA
VCC Turn-ON
VCC Rising
VCC Turn-OFF
VCC Falling
Pre-OVP Turn-ON
VCC Rising
Pre-OVP Turn-OFF
VCC Falling
3
OSC = OPEN
OSC = OPEN; TJ = 0°C to 125°C
90
)
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UVLOVCC
UVLOOVP
9.2
7
V
V
3.8
V
V
Oscillator and Inhibit
FSW
Main Oscillator Accuracy
OSCIL
Disable Thresholds
dMAX
Maximum Duty Cycle
∆VOSC
PWMx Ramp Amplitude
FAULT
Voltage at Pin OSC
100
110
0.5
kHz
V
OSC = OPEN; IISENx = 0µA
80
%
OSC = OPEN; IISENx = 35µA
40
%
3
V
5
V
OVP Active
Reference and DAC
FBR = V OUT; FBG = GNDOUT;
kVID
VR10 and VR9 DACs; VOUT > 1V
0.7
%
-1
1
%
Output Voltage Accuracy
FBR = V OUT; FBG = GNDOUT;
K8 DAC; V OUT > 1V
IVID
-0.7
VID Pull-up Current
VR9 and VR10 Mode; Input Low
K8 Mode; Input Low
VID IL
µA
25
0.4
0.8
V
V
VID Input Thresholds
VID IH
VR9 and VR10 Mode; Input Low
K8 Mode; Input Low
0.8
2
V
V
9/44
L6701
4 Electrical specifications
Table 4.
Electrical Characteristics (continued)
(VCC = 12V±15%, TJ = 0°C to 70°C unless otherwise specified).
Symbol
Parameter
Test conditions
Min.
Typ.
Max.
Unit
Error Amplifier and Remote Buffer
A0
EA DC Gain
SR
Slew Rate
CMRR
80
dB
15
V/µs
RB DC Gain
1
V/V
Remote Buffer Common
Mode Rejection Ratio
40
dB
COMP = 10pF to SGND
)
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Differential Current Sensing and Offset
IOCTH
Over Current Threshold
kIDROOP
Droop Current Deviation
IOFFSET
Offset Current
µA
35
IDROOP = 0 to 105µA; RD=5.1kΩ
-3
10
11.5
3
µA
13
µA
Gate Drivers
HS Rise Time
BOOTx - PHASEx = 10V;
CUGATEx to PHASEx = 3.3nF
15
ns
IUGATEx
HS Source Current
BOOTx - PHASEx = 10V
1.5
A
RUGATEx
HS Sink Resistance
BOOTx - PHASEx = 12V
2.5
Ω
tRISE_LGA
TEx
LS Rise Time
VCC = 10V;
CLGATEx to PGNDx = 5.6nF
20
ns
ILGATEx
LS Source Current
VCC = 10V
1.5
A
RLGATEx
LS Sink Resistance
VCC = 12V
1.8
Ω
tRISE_UGA
TEx
Protections
OVP
Over Voltage Protection
Pre-OVP
Preliminary Over voltage
Protection
VSEN Rising, VR10 and K8 Mode
VSEN Rising, VR9 Mode
1.85
2.05
1.9
2.1
1.95
2.15
V
V
FBR Rising, VR10 and K8 Mode
FBR Rising, VR9 Mode
1.8
2.0
1.9
2.1
2.0
2.2
V
V
Hysteresis
300
mV
UVP
Under Voltage Protection
VSEN Falling; Below VID
-475
-400
-325
mV
PGOOD
PGOOD Threshold
K8 and VR9 Mode;
VSEN Falling; Below VID
-280
-230
-180
mV
VSSEND/
SSEND / PGOOD
Voltage Low
I = -4mA
PGOOD
10/44
0.4
V
L6701
5 Typical application circuit and block diagram
5
Typical application circuit and block diagram
5.1
Application circuit
Figure 2.
Typical application circuit
VIN
LIN
2
GNDIN
to BOOT1
to BOOT2
CIN
VCC
BOOT1
7
to BOOT3
VIN
)
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26
21
22
23
24
25
19
COS
DAC_SEL
OSC/EN/FAULT
36
VID4
VID2
PHASE2
VID1
VID0
LGATE2
REF_IN
ISEN2
REF_OUT
BOOT3
UGATE3
PHASE3
CF
RF
UGATE2
VID3
COMP
ISEN1
BOOT2
VID5
ROS
20
LGATE1
35
LGATE3
FB
ISEN3
RFB
34
CS+
VSEN
CS-
9
L1
3
31
LS1
RISEN
10
VIN
11
HS2
12
5
30
COUT
LS2
LOAD
RISEN
13
VIN
14
HS3
15
L3
6
29
Vcc_core
L2
LS3
RPH
18
PHASE1
HS1
RPH
17
SGND
8
RPH
1
UGATE1
PGND
L6701
4
RISEN
CPH
32
33
RD
27
28
FBR
FBG
SSEND / PGOOD
16
PGOOD
L6701 REFERENCE SCHEMATIC
11/44
L6701
5 Typical application circuit and block diagram
Figure 3.
Typical Application Circuit: Fully Differential Current Sense (Pat.Pend.)
VIN
LIN
2
GNDIN
4
1
17
18
to BOOT1
CIN
VCC
BOOT1
UGATE1
PGND
SGND
PHASE1
DAC_SEL
LGATE1
OSC/EN/FAULT
ISEN1
7
to BOOT3
VIN
8
HS1
L1
9
3
31
to BOOT2
LS1
RISEN
)
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24
25
19
COS
VID2
36
VID0
LGATE2
REF_IN
ISEN2
REF_OUT
COMP
BOOT3
UGATE3
PHASE3
CF
RF
PHASE2
VID1
ROS
20
UGATE2
VID3
35
LGATE3
FB
ISEN3
RFB
34
27
28
L6701 FULLY DIFFERENTIAL
REFERENCE SCHEMATIC
12/44
CS+
11
HS2
12
L2
5
30
COUT
LS2
LOAD
RISEN
13
VIN
14
HS3
15
L3
6
29
Vcc_core
LS3
RPH
23
VIN
RPH
22
VID4
10
RPH
21
BOOT2
VID5
L6701
26
RISEN
CPH
32
CPH
VSEN
CPH
CS-
33
RD
RD
FBR
RD
FBG
SSEND / PGOOD
16
PGOOD
L6701
5 Typical application circuit and block diagram
Block diagram
VCC
VCC
PGND
VCC
PGND
LGATE3
PHASE3
UGATE3
BOOT3
LGATE2
PHASE2
UGATE2
BOOT2
LGATE1
PHASE1
Block diagram
BOOT1
Figure 4.
UGATE1
5.2
VCC
PGND
VCC
PGND
HS1
PGND
SGND
LS1
HS2
LOGIC PWM
ADAPTIVE ANTI
CROSS CONDUCTION
SGND
LS2
HS3
LOGIC PWM
ADAPTIVE ANTI
CROSS CONDUCTION
CURRENT SHARING
CORRECTION
LS3
LOGIC PWM
ADAPTIVE ANTI
CROSS CONDUCTION
CURRENT SHARING
CORRECTION
CURRENT SHARING
CORRECTION
DIGITAL
SOFT START
VCC
DAC_SEL
MULTIPLE DAC
WITH DYNAMIC
VID CONTROL
PWM3
OCP1
L6701
CONTROL LOGIC
AND PROTECTIONS
OSC/EN/FAULT
OCP2
OCP3
LOW SIDE MOSFET
CURRENT READING
AND OVER CURRENT
1V
OVP
UVP, PGOOD
SSEND / PGOOD
64k
IINFO
x3
64k
DROOP
CURRENT READING
REMOTE
BUFFER
VSEN
CS+
CS-
FB
REF_IN
ERROR
AMPLIFIER
64k
64k
FBR
FBG
IDROOP
DAC_SEL
REF_OUT
ISEN1
ISEN2
ISEN3
SSEND / PGOOD
IOS
COMP
VID0
VID1
VID2
VID3
VID4
VID5
PWM2
PH3
PWM1
PWM3
AVG
PWM2
PH2
PWM1
PH1
3 PHASE
OSCILLATOR
)
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OSC / EN / FAULT
13/44
L6701
6 VID Tables
6
VID Tables
Table 5.
Voltage IDentification (VID) for Intel VR10 DAC.
VID4 VID3 VID2 VID1 VID0 VID5
Output
Voltage (1)
VID4 VID3 VID2 VID1 VID0 VID5
Output
Voltage (1)
0
1
0
1
0
1
1.6000
1
1
0
1
0
1
1.2000
0
1
0
1
1
0
1.5875
1
1
0
1
1
0
1.1875
0
1
0
1
1
1
1.5750
1
1
0
1
1
1
1.1750
0
1
1
0
0
0
1.5625
1
1
1
0
0
0
1.1625
0
1
1
0
0
1
1.5500
1
1
1
0
0
1
1.1500
0
1
1
0
1
0
1.5375
1
1
1
0
1
0
1.1375
0
1
1
0
1
1
1.5250
1
1
1
0
1
1
1.1250
0
1
1
1
0
0
1.5125
1
1
1
1
0
0
1.1175
0
1
1
1
0
1
1.5000
1
1
1
1
0
1
1.1000
0
1
1
1
1
0
1.4875
1
1
1
1
1
0
OFF
0
1
1
1
1
1
1.4750
1
1
1
1
1
1
OFF
1
0
0
0
0
0
1.4625
0
0
0
0
0
0
1.0875
1
0
0
0
0
1
1.4500
0
0
0
0
0
1
1.0750
1
0
0
0
1
0
1.4375
0
0
0
0
1
0
1.0625
1
0
0
0
1
1
1.4250
0
0
0
0
1
1
1.0500
1
0
0
1
0
0
1.4125
0
0
0
1
0
0
1.0375
1
0
0
1
0
1
1.4000
0
0
0
1
0
1
1.0250
1
0
0
1
1
0
1.3875
0
0
0
1
1
0
1.0125
1
0
0
1
1
1
1.3750
0
0
0
1
1
1
1.0000
1
0
1
0
0
0
1.3625
0
0
1
0
0
0
0.9875
1
0
1
0
0
1
1.3500
0
0
1
0
0
1
0.9750
1
0
1
0
1
0
1.3375
0
0
1
0
1
0
0.9625
1
0
1
0
1
1
1.3250
0
0
1
0
1
1
0.9500
1
0
1
1
0
0
1.3125
0
0
1
1
0
0
0.9375
1
0
1
1
0
1
1.3000
0
0
1
1
0
1
0.9250
1
0
1
1
1
0
1.2875
0
0
1
1
1
0
0.9125
1
0
1
1
1
1
1.2750
0
0
1
1
1
1
0.9000
1
1
0
0
0
0
1.2625
0
1
0
0
0
0
0.8875
1
1
0
0
0
1
1.2500
0
1
0
0
0
1
0.8750
1
1
0
0
1
0
1.2375
0
1
0
0
1
0
0.8625
)
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14/44
L6701
6 VID Tables
Table 5.
Voltage IDentification (VID) for Intel VR10 DAC. (continued)
VID4 VID3 VID2 VID1 VID0 VID5
Output
Voltage (1)
VID4 VID3 VID2 VID1 VID0 VID5
Output
Voltage (1)
1
1
0
0
1
1
1.2250
0
1
0
0
1
1
0.8500
1
1
0
1
0
0
1.2125
0
1
0
1
0
0
0.8375
1. Since the VIDx pins program the maximum output voltage, according to VR10.x specifications, the device automatically
regulates to a voltage 19mV lower avoiding the use of any external components to lower the output voltage. This improves
the system tolerance performance since the reference already offset is trimmed in production within ±0.7%.
Table 6.
Voltage IDentification (VID) for Intel VR9 DAC (VID5 doesn’t care)
VID4 VID3 VID2 VID1 VID0
Output Voltage(1)
VID4 VID3 VID2 VID1 VID0
Output Voltage(1)
)
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0
0
0
0
0
1.850
1
0
0
0
0
1.450
0
0
0
0
1
1.825
1
0
0
0
1
1.425
0
0
0
1
0
1.800
1
0
0
1
0
1.400
0
0
0
1
1
1.775
1
0
0
1
1
1.375
0
0
1
0
0
1.750
1
0
1
0
0
1.350
0
0
1
0
1
1.725
1
0
1
0
1
1.325
0
0
1
1
0
1.700
1
0
1
1
0
1.300
0
0
1
1
1
1.675
1
0
1
1
1
1.275
0
1
0
0
0
1.650
1
1
0
0
0
1.250
0
1
0
0
1
1.625
1
1
0
0
1
1.225
0
1
0
1
0
1.600
1
1
0
1
0
1.200
0
1
0
1
1
1.575
1
1
0
1
1
1.175
0
1
1
0
0
1.550
1
1
1
0
0
1.150
0
1
1
0
1
1.525
1
1
1
0
1
1.125
0
1
1
1
0
1.500
1
1
1
1
0
1.100
0
1
1
1
1
1.475
1
1
1
1
1
OFF
1. Since the VIDx pins program the maximum output voltage, the device automatically regulates to a voltage 19mV lower
avoiding the use of any external components to lower the output voltage. This improves the system tolerance performance
since the reference already offset is trimmed in production within ±0.7%.
15/44
L6701
6 VID Tables
Table 7.
Voltage IDentification (VID) for AMD Hammer DAC
VID5 VID4 VID3 VID2 VID1 VID0
Output
Voltage
VID5 VID4 VID3 VID2 VID1 VID0
Output
Voltage
0
0
0
0
0
1.550
0
0
0
0
0
1.575
0
0
0
0
1
1.525
0
0
0
0
1
1.550
0
0
0
1
0
1.500
0
0
0
1
0
1.525
0
0
0
1
1
1.475
0
0
0
1
1
1.500
0
0
1
0
0
1.450
0
0
1
0
0
1.475
)
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0
0
1
0
1
1.425
0
0
1
0
1
1.450
0
0
1
1
0
1.400
0
0
1
1
0
1.425
0
0
1
1
1
1.375
0
0
1
1
1
1.400
0
1
0
0
0
1.350
0
1
0
0
0
1.375
0
1
0
0
1
1.325
0
1
0
0
1
1.350
0
1
0
1
0
1.300
0
1
0
1
0
1.325
0
1
0
1
1
1.275
0
1
0
1
1
1.300
0
1
1
0
0
1.250
0
1
1
0
0
1.275
0
1
1
0
1
1.225
0
1
1
0
1
1.250
0
1
1
1
0
1.200
0
1
1
1
0
1.225
0
1
1
1
1
1.175
0
1
1
1
1
1.200
1
16/44
0
1
0
0
0
0
1.150
1
0
0
0
0
1.175
1
0
0
0
1
1.125
1
0
0
0
1
1.150
1
0
0
1
0
1.100
1
0
0
1
0
1.125
1
0
0
1
1
1.075
1
0
0
1
1
1.100
1
0
1
0
0
1.050
1
0
1
0
0
1.075
1
0
1
0
1
1.025
1
0
1
0
1
1.050
1
0
1
1
0
1.000
1
0
1
1
0
1.025
1
0
1
1
1
0.975
1
0
1
1
1
1.000
1
1
0
0
0
0.950
1
1
0
0
0
0.975
1
1
0
0
1
0.925
1
1
0
0
1
0.950
1
1
0
1
0
0.900
1
1
0
1
0
0.925
1
1
0
1
1
0.875
1
1
0
1
1
0.900
1
1
1
0
0
0.850
1
1
1
0
0
0.875
1
1
1
0
1
0.825
1
1
1
0
1
0.850
1
1
1
1
0
0.800
1
1
1
1
0
0.825
1
1
1
1
1
OFF
1
1
1
1
1
OFF
L6701
7
7 Configuring the Device: DAC Selection
Configuring the Device: DAC Selection
Multiple DACs need to be configured before the system start-up by programming the apposite
pin DAC_SEL. The embedded DAC allows to regulate the output voltage with a tolerance of
±0.7% recovering from offsets and manufacturing variations. In case of selecting VR9 and
VR10 Mode, the device automatically introduces a -19mV offset to the regulated voltage (see
Table 5 and Table 6) in order to avoid any external offset circuitry to worsen the guaranteed
accuracy and, as a consequence, the calculated system TOB. In case of selecting the K8 DAC,
VID5 gives the option to introduce +25mV offset to the regulation (See Table 7).
Output voltage is programmed through the VID pins: they are inputs of an internal DAC that is
realized by means of a series of resistors providing a partition of the internal voltage reference.
The VID code drives a multiplexer that selects a voltage on a precise point of the divider. The
DAC output is delivered to an amplifier obtaining the voltage reference available on REF_OUT.
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Single-Wire CPU Automatic
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According to the selected DAC, the device also changes the protection thresholds as a
consequence of different CPU specifications, see Table 8 for details.
Table 8.
L6701 Configuration
DAC_SEL
OPERATIVE MODE
OVP & PreOVP
UVP
PGOOD
OPEN
AMD K8 +25mV (Driven by VID5)
1.9V Fixed
-400mV
-230mV
82kΩ to GND
Intel VR10 -19mV
1.9V Fixed
-400mV
SSEND
GND
Intel VR9 -19mV
2.1V Fixed
-400mV
-230mV
L6701 has been designed to automatically detect the Intel CPU connected by monitoring the
DAC_SEL pin status at the start-up so modifying the DAC table accordingly (see Table 8). In
fact, by directly connecting the DAC_SEL pin with #BOOTSEL pin of the CPU, the controller
automatically recognize the different technology steps of the CPU so modifying the DAC table
accordingly.
See CPU related documentation for further details about compatibility.
17/44
L6701
8 Driver Section
8
Driver Section
The integrated high-current drivers allow using different types of power MOS (also multiple
MOS to reduce the equivalent RDS(on)), maintaining fast switching transition.
The drivers for the high-side MOSFETs use BOOTx pins for supply and PHASEx pins for
return. The drivers for the low-side MOSFETs use the VCC pin for supply and PGND pin for
return.
The controller embodies a anti-shoot-through and adaptive dead-time control to minimize low
side body diode conduction time maintaining good efficiency saving the use of Schottky diodes:
when the high-side MOSFET turns off, the voltage on its source begins to fall; when the voltage
reaches 2V, the low-side MOSFET gate drive is suddenly applied. When the low-side MOSFET
turns off, the voltage at LGATEx pin is sensed. When it drops below 1V, the high-side MOSFET
gate drive is suddenly applied. If the current flowing in the inductor is negative, the source of
high-side MOSFET will never drop. To allow the low-side MOSFET to turn-on even in this case,
a watchdog controller is enabled: if the source of the high-side MOSFET does not drop, the low
side MOSFET is switched on so allowing the negative current of the inductor to recirculate. This
mechanism allows the system to regulate even if the current is negative.
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8.1
Power Dissipation
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Power conversion input is flexible: 5V, 12V bus or any bus that allows the conversion (See
maximum duty cycle limitations) can be chosen freely.
L6701 embeds high current MOSFET drivers for both high side and low side MOSFETs: it is
then important to consider the power that the device is going to dissipate in driving them in
order to avoid overcoming the maximum junction operative temperature. In addition, since the
device has an exposed pad to better dissipate the power, the thermal resistance between
junction and ambient consequent to the layout is also important: thermal pad need to be
soldered to the PCB ground plane through several VIAs in order to facilitate the heat
dissipation.
Two main terms contribute in the device power dissipation: bias power and drivers' power.
●
Device Power (PDC) depends on the static consumption of the device through the supply
pins and it is simply quantifiable as follow (assuming to supply HS and LS drivers with the
same VCC of the device):
P DC = V CC ⋅ ( I CC + 3 ⋅ I CCDRx + 3 ⋅ I BOO Tx )
●
Drivers' power is the power needed by the driver to continuously switch on and off the
external MOSFETs; it is a function of the switching frequency and total gate charge of the
selected MOSFETs. It can be quantified considering that the total power PSW dissipated to
switch the MOSFETs (easy calculable) is dissipated by three main factors: external gate
resistance (when present), intrinsic MOSFET resistance and intrinsic driver resistance.
This last term is the important one to be determined to calculate the device power
dissipation. The total power dissipated to switch the MOSFETs results:
P SW = 3 ⋅ F SW ⋅ ( Q G HS ⋅ V BO OT + Q GLS ⋅ V CCDRx )
External gate resistors helps the device to dissipate the switching power since the same power
PSW will be shared between the internal driver impedance and the external resistor resulting in
a general cooling of the device.
18/44
L6701
Figure 5.
8 Driver Section
Dissipated Power
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19/44
L6701
9 Current Sharing Loop and Current Reading
9
Current Sharing Loop and Current Reading
9.1
Current Sharing Loop
L6701 embeds two separate Current Reading circuitries used to perform Current Sharing and
OCP through ISENx pins and Voltage Positioning (Droop Function) through CS+ and CS- pins
(See Section 10).
Current sharing control loop and connections are reported in Figure 6: the current read through
the ISENx pins is converted into a current IINFOx proportional to the current delivered by each
phase and the information about the average current IAVG = ΣIINFOx / 3 is internally built into the
device. The error between the read current IINFOx and the reference IAVG is then converted into
a voltage that with a proper gain is used to adjust the duty cycle whose dominant value is set by
the voltage error amplifier in order to equalize the current carried by each phase.
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9.2
Current Reading for Current Sharing
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The current flowing trough each phase is read using the voltage drop across the low side
MOSFETs RDS(on) or across a sense resistor in its series and it is internally converted into a
current. The trans-conductance ratio is issued by the external resistor RISEN placed outside the
chip between ISENx and the reading point (usually the LS MOSFET Drain).
The current sense circuit tracks the current information for a time TTRACK centered in the
middle of the LS conduction time and holds the tracked information during the rest of the
period. The current that flows from the ISENx pin is the current information used by the device to
perform current sharing and OCP and it is given by:
R dsO N
I ISENx = ----------------- ⋅ I PHASEx = I INFO x
R ISEN
where RDS(on) is the ON resistance of the low side MOSFET and RISEN is the transconductance resistor connected between the ISENx pins and the LS Drain; IPHASEx is the
current carried by the relative phase and IINFOx is the current information signal reproduced
internally. RISENx is designed according to the Over Current Protection: see Section 13.6 for
details.
Figure 6.
Current Sharing Loop and Current Reading Connections
IINFO1
PWM1 Out
IPHASEx
AVG
IAVG
IINFO2
From EA
LGATEx
PWM2 Out
IINFO3
PWM3 Out
20/44
IISENx
ISENx
RISEN
L6701
10
10 Output Voltage Positioning
Output Voltage Positioning
Output voltage positioning is performed by selecting the reference DAC and by programming
the Droop Function and Offset to the reference (See Figure 7). The current (IDROOP) sourced
from the FB pin, directly proportional to the read current, causes the output voltage to vary
according to the external RFB resistor so implementing the desired load-line resistance. The
current (IOS) sourced from the REF_IN pin causes the reference voltage to be offset according
to the resistance RFB connected.
The output voltage is then driven by the following relationship:
V O UT = VID + R O S ⋅ I O S – R FB ⋅ I DRO OP
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d Function
10.1 Load-Line (Droop
- - Optional)
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Both DROOP and OFFSET function can be disabled: see Section 10.1 and Section 10.3 for
details.
Figure 7.
Voltage Positioning
64k
REF_OUT
REF_IN
ROS
FB
COMP
RF
VSEN
64k
VID
64k
IDROOP
IOS
64k
FBR
FBG
CF
To Vcore
(Remote Sense)
COS
RFB
This method "recovers" part of the drop due to the output capacitor ESR in the load transient,
introducing a dependence of the output voltage on the load current: a static error proportional to
the output current causes the output voltage to vary according to the sensed current.
Figure 8 shows the typical Current-Sense Circuit used to implement the Droop-Function in lowcost application (saves component count). The current flowing across the three inductors is
read through the RPH - CPH filter across CS+ and CS- pins. RD programs a trans-conductance
gain and generates a current ICS proportional to the average of the currents of the three
phases. The current ICS is then mirrored and, multiplied by three, sourced by the FB pin
(IDROOP). RFB gives the final gain to program the desired load-line slope.
Considering the scheme reported on Figure 8, it is possible to observe that:
I O UT
1 + s ⋅ L ⁄ DCR
DCR
I CS = ------------ ⋅ ---------------------------------------------------- ⋅ ------------3
1 + s ⋅ R PH ⋅ C PH ⁄ 3 R D
Time constant matching between the inductor (L / DCR) and the current reading filter
( R PH ⋅ C PH ⁄ 3 ) is required to implement a real equivalent output impedance of the system so
avoiding over and/or under shoot of the output voltage as a consequence of a load transient. It
results:
21/44
L6701
10 Output Voltage Positioning
R PH ⋅ C PH
I O UT DCR
L
------------- = --------------------------- => I CS = ------------ ⋅ ------------DCR
3
3
RD
The device forces IDROOP = ICSx3, proportional to the read current, into the feedback resistor
RFB implementing the load regulation dependence. The output characteristic vs. load current is
then given by (Offset disabled):
DCR
V O UT = VID – R FB ⋅ I DROOP = VID – R FB ⋅ ------------- ⋅ I OUT = VID – R LL ⋅ I O UT
RD
Where RLL is the resulting load-line resistance implemented by the system.
The whole power supply can be then represented by a "real" voltage generator with an
equivalent output resistance RLL and a voltage value of VID.
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10.2s Fully-Differential Load-Line (Droop Function - Optional)
b
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RFB resistor can be then designed according to the RLL specifications as follow:
RD
R FB = R L L ⋅ ------------DCR
where RD is typically designed to have ICS = 35µA at the maximum output current (OCP).
Caution: Droop function is optional, in case it is not desired, the Current Sense circuit can be modified so
that the device always read a null current (See Figure 8). To do this, it is enough to connect
CS+ directly to the output voltage leaving CS- unconnected. The reaction will keep CS+ and
CS- at the same voltage, always reading a null current and also assuring the FB disconnection
protection to be effective.
Figure 8.
Droop Function Current Reading Network
PHASE1
PHASE2
DCR1
L2
DCR2
L3
DCR3
PHASE1
PHASE2
VOUT
PHASE3
L1
DCR1
L2
DCR2
L3
DCR3
VOUT
RPH
RPH
RPH
PHASE3
L1
RFB
CPH
RF
RFB
CF
RF
CF
RD
CS+
CS-
FB
IDROOP
ICS
x3
Droop Function Enabled
COMP
CS+
CS-
FB
COMP
IDROOP
ICS
x3
Droop Function Disabled
Fully-Differential current-reading for voltage-positioning allows the designer to save time in the
application fine-tuning since the BOM so obtained becomes layout-independent. The patentpending topology offered by L6701 allow implementing fully-differential current-sense still using
only two current-sense pins (CS+ and CS-). Figure 9 shows the typical Current-Sense Circuit
used to implement the Fully-Differential Droop-Function. The current flowing across the three
inductors is read through an RPH - CPH filter for each phase as well as an R D is required for
each phase to program the trans-conductance-gain. As previously mentioned, a current ICS
proportional to the average of the currents of the three phases is internally generated, mirrored
22/44
L6701
10 Output Voltage Positioning
and, multiplied by three, sourced by the FB pin (IDROOP). RFB gives the final gain to program
the desired load-line slope.
As before, the voltage positioning equations results (See Figure 9):
1 + s ⋅ L ⁄ DCR DCR
I CS = I O UT ⋅ -------------------------------------------- ⋅ ------------1+s⋅R ⋅C
R
PH
PH
D
As a consequence:
L
DCR
------------- = R PH ⋅ C PH => I CS = I O UT ⋅ ------------DCR
RD
The device forces IDROOP = ICSx3, proportional to the read current, into the feedback resistor
RFB implementing the load regulation dependence. The output characteristic vs. load current is
then given by (Offset disabled):
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DCR
V O UT = VID – R FB ⋅ I DROOP = VID – 3 ⋅ R FB ⋅ ------------- ⋅ I O UT = VID – R L LDIFF ⋅ I OUT
RD
Where RLLDIFF is the resulting differential load-line resistance implemented by the system. The
whole power supply can be then represented by a "real" voltage generator with an equivalent
output resistance RLLDIFF and a voltage value of VID.
RFB resistor can be then designed according to the Load-Line (RLLDIFF) specifications as
follow:
R LL DIFF R D
R FB = ---------------------- ⋅ ------------- .
3
DCR
where RD is typically designed to have ICS = 35µA at the maximum output current (OCP).
Table 9 contains a quick-reference guide to design applications with typical and/or differential
current sense.
Figure 9.
Fully Differential Load-Line Current-Reading (pat. pend.)
PHASE1
PHASE2
CS+
DCR1
L2
DCR2
L3
DCR3
VOUT
Fully Differential Current Reading
for Load-Line
RPH
RPH
RPH
PHASE3
L1
CPH
RD
CPH
RD
CPH
RD
RFB
RF
CS-
FB
CF
COMP
IDROOP
ICS
x3
23/44
L6701
10 Output Voltage Positioning
Table 9.
Comparison between different load-line implementations.
Fully-Differential LL
Non-Fully-Differential LL
Layout-insensitive BOM
Y
N
Time-Constant Matching
L
------------- = R PH ⋅ C PH
DCR
R PH ⋅ C PH
L
------------- = --------------------------DCR
3
R D Design (given OCP th.)
DCR
R D = OCP ⋅ ------------35µ
OCP DCR
R D = ------------- ⋅ ------------3
35µ
R FB Design (given RLL)
R LL R D
R FB = ---------- ⋅ ------------3 DCR
RD
R FB = R L L ⋅ ------------DCR
DCR
R LL = 3 ⋅ ------------- ⋅ R FB
RD
DCR
R LL = ------------- ⋅ R FB
RD
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10.3 Offset (Optional)
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e Voltage Sense
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R LL (given RD and R FB)
Positive offset can be added to the programmed reference by connecting a ROS resistor
between the REF_OUT and REF_IN pins. Referring to Figure 7, a constant current
(IOS=11.5µA) is sourced from the REF_IN pin as soon as the device is enabled, so
programming a fixed voltage drop across ROS: this voltage is directly added to the programmed
reference giving the desired offset to the output voltage as follow:
V O S = R OS ⋅ I OS
Offset current is suddenly sourced from REF_IN pin as soon as the device implements SoftStart: to avoid having steps during soft-start, the introduction of COS (in parallel to ROS) is
required. The resulting time constant need to be negligible with respect to the soft-start time as
well as long enough to smooth the initial step. Typical values are in the range of few hundreds
of nF.
Offset function can be easily disabled simply setting ROS = 0.
Caution: Offset automatically given by the DAC selection differs from the offset implemented through the
OFFSET pin: the built-in feature is trimmed in production and assures ±0.7% accuracy over
load and line variations.
L6701 embeds a Remote Sense Buffer to sense remotely the regulated voltage without any
additional external components. In this way, the output voltage programmed is regulated
between the remote buffer inputs compensating motherboard or connector losses. The device
senses the output voltage remotely through the pins FBR and FBG (FBR is for the regulated
voltage sense while FBG is for the ground sense) and reports this voltage internally at VSEN
pin with unity gain eliminating the errors. Keeping the FBR and FBG traces parallel and
guarded by a power plane results in common mode coupling for any picked-up noise.
24/44
L6701
10.5
10 Output Voltage Positioning
Maximum Duty Cycle limitation
To provide proper time for current-reading in order to equalize the current carried by each
phase, the device implements a duty-cycle limitation. This limitation is not fixed but it is linearly
variable with the current delivered to the load as follow:
I ISENx = 0µA
⎧ 0.80 ⋅ T SW
T ON ( max ) = ⎨
I ISENx = 35µA
⎩ 0.40 ⋅ T SW
Duty Cycle limitation is variable with the delivered current to provide fast load transient
response at light load as well as assuring robust over-current protection.
Figure 10 shows the maximum output voltage that the device is able to regulate considering the
TON limitation imposed by the previous relationship. If the desired output characteristic crosses
the limited-TON maximum output voltage, the output resulting voltage will start to drop after the
cross-point. In this case, the output voltage starts to decrease following the resulting
characteristic (dotted in Figure 10) until UVP is detected or anyway until IISENx = 35µA.
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Figure 10. Maximum Duty Cycle limitation
Maximum Output Voltage
Limited TON
VOUT
VOUT
0.80 VIN
0.80 VIN
0.40 VIN
0.40 VIN
Limted-TON Output Char.
Desired output Char.
Resulting Output Char.
UVP Threshold
Limted-TON Output Char.
IOUT
IOCP = 3 x IOCPx
(IISENx = 35µA)
IOUT
IOCP = 3 x IOCPx
(IISENx = 35µA)
25/44
L6701
11 Dynamic VID Transitions
11
Dynamic VID Transitions
L6701 is able to manage Dynamic VID Code changes in all its operative modes (VR10, K8 and
also VR9) so allowing Output Voltage modification during normal device operation. PGOOD
(when applicable), OVP and UVP signals are masked during every VID transition and they are
re-activated after the transition finishes with a 32 clock cycles delay to prevent from false
triggering.
When changing dynamically the regulated voltage (D-VID), the system needs to charge or
discharge the output capacitor accordingly. This means that an extra-current
ID – VID = C OUT ⋅ dV OU T ⁄ dT VI D
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needs to be delivered, especially when increasing the output regulated voltage and it must be
considered when setting the over current threshold. In the previous relationship, dVOUT is the
selected DAC LSB (12.5mV for VR10 DAC or 25mV for both VR9 and K8 DACs) and TVID is
the time interval between each LSB transition (typically externally driven). Overcoming the OC
threshold during the dynamic VID causes the device to enter the constant current limitation
slowing down the output voltage dV/dt also causing the failure in the D-VID test.
VID Sampled
VID Sampled
VID Sampled
VID Sampled
VID Stable
Ref Moved (1)
VID Sampled
VID Sampled
VID Stable
Ref Moved (1)
VID Sampled
VID Sampled
VID Stable
Ref Moved (1)
VID Sampled
VID Sampled
VID Stable
Ref Moved (1)
VID Sampled
VID Sampled
VID Sampled
VID Sampled
Ref Moved (4)
Ref Moved (3)
Ref Moved (2)
VID Sampled
VID Stable
Ref Moved (1)
VID Sampled
VID Sampled
Figure 11. Dynamic VID Transitions
VID Clock
t
VID [0,5]
t
Int. Reference
TDVID
Tsw
t
Vout
TVID
x 4 Step VID Transition
4 x 1 Step VID Transition
Vout Slope Controlled by internal
DVID-Clock Oscillator
Vout Slope Controlled by external
driving circuit (TVID)
t
L6701 checks for VID code modifications (See Figure 11) on the rising edge of an internal
additional DVID-clock and waits for a confirmation on the following falling edge. Once the new
code is stable, on the next rising edge, the reference starts stepping up or down in LSB
increments every VID-clock cycle until the new VID code is reached. During the transition, VID
code changes are ignored; the device re-starts monitoring VID after the transition has finished
on the next rising edge available. VID-clock frequency (FDVID) depends on the operative mode
selected: for VR10 Mode it is equal to three times the system switching frequency programmed
for each phase (FDVID = 3 x FSW) to assure compatibility with the specifications while, for VR9
and K8, this frequency is lowered to FDVID = FSW.
26/44
L6701
11 Dynamic VID Transitions
Caution: If the new VID code is more than 1 LSB different from the previous, the device will execute the
transition stepping the reference with the DVID-clock frequency FDVID until the new code has
reached: for this reason it is recommended to carefully control the VID change rate in order to
carefully control the slope of the output voltage variation especially in VR10 mode.
Warning: DVID sample and hold clock depends on the switching frequency FSW. To correctly perform
DVID transition so following the VID change rate, it is required to have at least 2 complete
cycles of the FDVID clock between every VID transition. If the VID update-rate is, for example,
5µsec., the minimum operating frequency results to be FSW > 133kHz in VR10 mode.
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27/44
12 Soft Start
12
L6701
Soft Start
L6701 implements a soft-start to smoothly charge the output filter avoiding high in-rush currents
to be required to the input power supply. The device increases the reference from zero up to
the programmed value in 2048 clock periods and the output voltage increases accordingly with
closed loop regulation. At the end of the digital Soft-Start, SSEND/PGOOD signal is set free.
Protections are active during this phase; Under Voltage is enabled when the reference voltage
reaches 0.6V while Over Voltage is always enabled with a threshold dependent on the selected
Operative Mode. DAC table information is frozen just before initializing the Soft-Start.
The device implements Soft-Start only when all the power supplies are above their own turn-on
thresholds and the EN pin is set free.
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12.1 Low-Side-Less Startup (LSLess)
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In order to avoid any kind of negative undershoot and dangerous return from the load during
start-up, L6701 performs a special sequence in enabling LS driver to switch: during the softstart phase, the LS driver results disabled (LS = OFF) until the HS starts to switch. This avoid
the dangerous negative spike on the output voltage that can happen if starting over a prebiased output (See Figure 12).
This particular feature of the device masks the LS turn-on only from the control loop point of
view: protections by-pass this turning ON the LS MOSFET in case of need.
Figure 12. LSLess Startup (left) vs. Non-LSLess Startup (right)
28/44
L6701
13
13 Output voltage Monitor and Protections
Output voltage Monitor and Protections
L6701 monitors through pin VSEN the regulated voltage in order to manage the OVP, UVP and
PGOOD (when applicable) conditions. Protections are active also during soft-start (See
Section 12 for details) while are masked during D-VID transitions with an additional 32 clock
cycle delay after the transition has finished to avoid false triggering.
In addition, preliminary over-voltage protection is also provided to protect the load from highside MOSFET failures before the system turn-ON.
13.1
Under Voltage
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13.2 Preliminary Over Voltage
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If the output voltage monitored by VSEN drops more than -400mV below the programmed
reference for more than one clock period, the device turns off all MOSFETs driving high the
FAULT pin and latches the condition: to recover it is required to cycle Vcc or the EN pin. This is
independent by the selected operative mode.
To provide a protection while VCC is below the UVLOVCC threshold is fundamental to avoid
damage to the load in case of failed HS MOSFETs. In fact, since the device is supplied from the
12V bus, it is basically “blind” for any voltage below the turn-on threshold (UVLOVCC). In order
to give full protection to the load, a preliminary-OVP protection is provided while VCC is within
UVLOVCC and UVLOOVP.
According to the DAC_SEL pin status, this protection turns-on the low side MOSFETs as long
as the FBR pin voltage is greater than 1.9V for VR10 and 2.1V for VR9 and K8 with a 300mV
hysteresis (See Table 10). When set, the protection drives the LS MOSFET with a gate-tosource voltage depending on the voltage applied to VCC. This protection depends also on the
EN pin status as detailed in Figure 13. Preliminary OVP is always active before UVLOVCC for
all operative modes with intervention thresholds dependent on the DAC_SEL pin status.
A simple way to provide protection to the output in all conditions when the system is OFF (then
avoiding the unprotected red region in Figure 13-Left) consists in supplying the controller
through the 5VSB bus with an OR-ing diode solution as shown in Figure 13-Right: 5VSB is
always present before +12V and, in case of HS short, the LS MOSFET is driven with 5V
assuring a reliable protection of the load.
When using the OR-ing diode solution, OR-ing diodes need to be sized according to the device
current consumption: the two diodes will then results to be different since the diode connected
to the 12V bus needs to carry the current for normal operations (IRMS) and the diode connected
to the 5VSB (IRMS-PREOVP) need to carry only the current in case of Pre-OVP protection is
active. Device current consumption (IRMS) in normal operations depends on the external
MOSFET configuration as follow:
I RMS = 3 ⋅ FSW ⋅ ( Q G HS + Q GLS ) + ( I CC + 3 ⋅ I CCDRx + 3 ⋅ I BOO Tx )
Device current consumption when Pre-OVP is active depends on the output filter configuration
since LS MOSFETs switching frequency depends on the leakage that is charging the output
filter. Test on the bench is required but, for an over-sized solution, the same diode identified for
the +12V bus can be used.
29/44
L6701
13 Output voltage Monitor and Protections
Figure 13. Output Voltage Protections and typical principle connections
(EN = 0)
Preliminary OVP
FBR/DACSEL Monitor
Vcc
UVLOVCC
(EN = Free)
OVP Protection
VSEN Monitored
Preliminary OVP Enabled
FBR Monitored
+5V
SB
+12V
VCC
UVLOOVP
No Protection
Provided
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13.3 Over Voltage
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13.4 Feedback
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Once VCC crosses the turn-ON threshold and the device is enabled (EN = Free), L6701
provides an Over Voltage Protection according to the DAC_SEL status: when the voltage
sensed by VSEN overcomes the OVP threshold, the controller permanently switches on all the
low-side MOSFETs and switches off all the high-side MOSFETs in order to protect the load.
The FAULT pin is driven high (5V) and power supply or EN pin cycling is required to restart
operations.
The OVP (and Pre-OVP) Threshold varies according to the operative mode selected as
reported in Table 10.
Table 10.
OVP and Preliminary OVP Thresholds
DAC_SEL
Operative Mode
Pre-OVP
OVP
0
VR9
2.1
2.1
82kΩ to SGND
VR10
1.9
1.9
Open
K8
1.9
1.9
L6701 allows to monitor the output voltage in two different points:
●
Remotely, through the remote buffer, across VSEN
●
Locally across the CS- pin (negligibly offset by R D ⋅ I C S ).
By comparing the voltage present at these two different locations, L6701 is able to understand
if the output voltage feedback is connected. When CS- is more than 1V higher than VSEN,
(See Figure 14) the device stops switching with the low side MOSFETs permanently ON and
drives high the FAULT pin. The condition is latched until VCC or EN cycled.
30/44
L6701
13 Output voltage Monitor and Protections
Figure 14. Feedback Disconnection
PHASE1
PHASE2
PHASE3
L1
DCR1
L2
DCR2
L3
DCR3
VOUT
RD RD RD
RFB
CD
RF
CF
RG
CS_DROOP+
CS_DROOP-
FB
COMP
VSEN
FBR
FBG
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13.5 PGOOD (Only for VR9 and K8 Modes)
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13.6 Over Current Protection - O
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IDROOP
IINFO
x3
VID
1V
FB_DISCONNECTED
It is an open-drain signal set free after the soft-start sequence has finished. It is pulled low
when the output voltage drops below -230mV of the programmed voltage.
Output current in each phase is monitored by L6701 through RISEN and so, programming the
value of these resistors, it is possible to set the OCP to the desired value. The Over Current
threshold has to be programmed to a safe value, in order to be sure that the device doesn't
enter OCP during normal operation of the device. This value must take into consideration also
the extra current needed during the Dynamic VID Transition ID-VID and, since the device reads
across MOSFETs RDS(on), the process spread and temperature variations of these sensing
elements. Moreover, since also the internal threshold spreads, the Rg design has to consider
the minimum value IOCTH(min) of the threshold as follow:
I OCPx ( m ax ) ⋅ R dsO N ( max )
Rg = -----------------------------------------------------------------I O CTH ( m in )
where IOCPx is the current measured by the current reading circuitry when the device enters
Quasi-Constant-Current.
Since the device reads the current across Low Side MOSFETs, it limits the bottom of the
inductor current entering in constant current until setting UVP as below explained. IOCPx must
be calculated starting from the corresponding output current value IOUT(OCP) as follow (ID-VID
must also be considered when D-VID are supported) since the device holds the valley current
information:
I OUT ( O CP ) ∆I PP I D – VID
I O CPx = ---------------------------- – ------------ + -----------------3
2
3
where IOUT(OCP) is still the output current value at which the device enters Quasi-ConstantCurrent, IPP is the inductor current ripple in each phase and ID-VID is the additional current
required by D-VID (when applicable). In particular, since the device limits the valley of the
31/44
L6701
13 Output voltage Monitor and Protections
inductor current, the ripple entity, when not negligible, impacts on the real OC threshold value
and must be considered.
The device detects an Over Current condition for each phase when the current information
IISENx overcomes the fixed threshold of IOCTH. When this happens, the device keeps the
relative LS MOSFET on, also skipping clock cycles, until the threshold is crossed back and
IISENx results being lower than the IOCTH threshold (this implies that the device limits the bottom
of each inductor current ripple). After exiting the OC condition, the LS MOSFET is turned off
and the HS is turned on with a duty cycle driven by the PWM comparator.
The device enters in Quasi-Constant-Current operation: the low-side MOSFETs stays ON until
the current read becomes lower than IOCPx (IINFOx < I OCTH) skipping clock cycles. The high
side MOSFET can be then turned ON with a TON imposed by the control loop after the LS turnoff and the device works in the usual way until another OCP event is detected.
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This means that the average current delivered can slightly increase in Quasi-Constant-Current
operation since the current ripple increases. In fact, the ON time increases due to the OFF time
rise because of the current has to reach the IOCPx bottom. The worst-case condition is when
the ON time reaches its maximum value (see Section 10.5). When this happens, the device
works in Real Constant Current and the output voltage decrease as the load increase. Crossing
the UVP threshold causes the device to latch driving high the OSC pin.
It can be observed that the peak current (IPEAK) is greater than IOCPx but it can be determined
as follow:
V IN – V OUT ( m in )
V IN – V O UT ( min )
I PEAK = I OCPx + ------------------------------------------- ⋅ T ON ( m ax ) = I O CPx + ------------------------------------------- ⋅ 0.40 ⋅ T SW
L
L
Where VoutMIN is the UVP threshold, (inductor saturation must be considered). When that
threshold is crossed, all MOSFETs are turned off, the FAULT pin is driven high and the device
stops working. Cycle the power supply or the EN pin to restart operation.
The maximum average current during the Constant-Current behavior results (see Figure 15):
I PEAK – I O CPx
I MAX, tot = 3 ⋅ IMAX = 3 ⋅ ⎛ IOCPx + -------------------------------------⎞
⎝
⎠
2
in this particular situation, the switching frequency for each phase results reduced. The ON time
is the maximum allowed TON(max) while the OFF time depends on the application:
I PEAK – I OCPx
1
T OFF = L ⋅ ------------------------------------f = ---------------------------------------------T O N ( max ) + T OFF
V OUT
Figure 15. Constant Current Operation
Constant Current (Exploded)
IPEAK
VOUT
0.40 VIN
IMAX
IOCPx
TON(max)
TSW
32/44
LS ON Skipping
Clock Cycles
TON(max)
TSW
Limted-TON Char.
Resulting Out. Char.
UVP Threshold
IOCP = N x IOCPx
(IDROOP = N x 35µA)
Quasi-Const.
Current
Droop Effect
IOUT
IMAX,tot
L6701
13 Output voltage Monitor and Protections
The trans-conductance resistor RISENx can be designed considering that the device limits the
bottom of the inductor current ripple and also considering the additional current delivered
during the quasi-constant-current behavior as previously described in the worst case
conditions.
Moreover, when designing D-VID compatible systems, the additional current due to the output
filter charge during dynamic VID transitions must be considered.
I O CPx ( max ) ⋅ R ds ON ( m ax )
I OUT ( O CP ) ∆I PP I D – VID
R ISENx = ------------------------------------------------------------------ where I O CPx = ---------------------------- – ------------ + -----------------3
2
3
I OCTH ( min )
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33/44
L6701
14 Oscillator
14
Oscillator
The internal oscillator generates the triangular waveform for the PWM charging and
discharging with a constant current an internal capacitor. The switching frequency for each
channel, FSW, is internally fixed at 100kHz so that the resulting switching frequency at the load
side results in being tripled (300kHz).
The current delivered to the oscillator is typically 25µA (corresponding to the free-running
frequency FSW=100kHz) and it may be varied using an external resistor (ROSC) connected
between the OSC pin and SGND. Since the OSC pin is fixed at 1.24V, the frequency is
increased proportionally to the current sunk from the pin considering the internal gain of 4KHz/
µA.
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In particular connecting ROSC to SGND the frequency is increased according to the following
relationship:
6
1.240V
kHz
4.96 ⋅ 10
ROSC vs. SGND F SW = 100kHz + ---------------------------- ⋅ 4 ----------- = 100kHz + ---------------------------R
R
( kΩ )
µA
( kΩ )
OSC
OSC
Caution: Maximum programmable switching frequency per phase must be limited to 500kHz to avoid
current reading errors causing, as a consequence, current sharing errors. Anyway, device
power dissipation must be checked prior to design high switching frequency systems.
Figure 16. ROSC vs. Switching Frequency
Rosc [kOhms] to SGND
250
200
150
100
50
0
100
150
200
250
300
350
400
Fsw [kHz] Programmed
34/44
450
500
550
L6701
15
15 System Control Loop Compensation
System Control Loop Compensation
The control loop is composed by the Current Sharing control loop (See Figure 17) and the
Average Current Mode control loop. Each loop gives, with a proper gain, the correction to the
PWM in order to minimize the error in its regulation: the Current Sharing control loop equalize
the currents in the inductors while the Average Current Mode control loop fixes the output
voltage equal to the reference programmed by VID. Figure 17 shows the block diagram of the
system control loop.
The system Control Loop is reported in Figure 18. The current information IDROOP sourced by
the DROOP pin flows into RFB implementing the dependence of the output voltage from the
read current.
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Figure 17. Main Control Loop
L3
PWM3
1/5
L2
PWM2
COUT
ROUT
1/5
L1
PWM1
1/5
ERROR AMPLIFIER
Reference
4/5
CURRENT SHARING
DUTY CYCLE
CORRECTION
IINFO1
IINFO2
IINFO3
IDROOP
COMP
FB
ZF(s)
ZF(s)
The system can be modeled with an equivalent single phase converter which only difference is
the equivalent inductor L/3 (where each phase has an L inductor).The Control Loop gain results
(obtained opening the loop after the COMP pin):
PWM ⋅ Z F ( s ) ⋅ ( R DROOP + Z P ( s ) )
G LOO P ( s ) = – -------------------------------------------------------------------------------------------------------------------ZF ( s )
1
[ Z P ( s ) + Z L ( s ) ] ⋅ --------------- + ⎛ 1 + ------------⎞ ⋅ R FB
A(s ) ⎝
A ( s )⎠
Where:
●
DCR
R D ROOP = ------------- ⋅ R FB is the equivalent output resistance determined by the droop function
RD
DCR
( R DROO P = 3 ⋅ ------------- ⋅ R FB
R
for fully differential current sense);
D
●
ZP(s) is the impedance resulting by the parallel of the output capacitor (and its ESR) and
the applied load RO;
●
ZF(s) is the compensation network impedance;
●
ZL(s) is the parallel of the three inductor impedance;
●
A(s) is the error amplifier gain;
35/44
L6701
15 System Control Loop Compensation
V IN
4
PWM = --- ⋅ ------------------- is the PWM transfer function where ∆VOSC is the oscillator ramp
5 ∆V OSC
●
amplitude and has a typical value of 3V.
Removing the dependence from the Error Amplifier gain, so assuming this gain high enough,
and with further simplifications, the control loop gain results:
G
LOOP
V
IN
4
( s ) = – --- ⋅ ---------------------- ⋅
5 ∆V
OSC
Z (s ) R + R
1 + s ⋅ C ⋅ (R
//R + ESR )
F
O
DR OOP
O
DROOP
O
--------------- ⋅ -------------------------------------------- ⋅ ------------------------------------------------------------------------------------------------------------------------------------------R
R
R
2
L
L
FB
L
L
R + ------s ⋅ C ⋅ ---- + s ⋅ ------------------ + C ⋅ ESR + C ⋅ ------- + 1
O 3
O 3
O 3
3 ⋅ RO O
The system Control Loop gain (See Figure 18) is designed in order to obtain a high DC gain to
minimize static error and to cross the 0dB axes with a constant -20dB/dec slope with the
desired crossover frequency ωT. Neglecting the effect of ZF(s), the transfer function has one
zero and two poles; both the poles are fixed once the output filter is designed (LC filter
resonance ωLC) and the zero (ωESR) is fixed by ESR and the Droop resistance.
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Figure 18. Equivalent Control Loop Block Diagram (left) and Bode Diagram (right).
PWM
d VOUT L / N
VOUT
dB
ESR
CO
RO
IDROOP
REMOTE BUFFER
64k
DROOP
Reference
FB
64k
FBG
64k
FBR
K
ZF(s)
RF[dB]
COMP
RF
ZF(s)
ZFB(s)
VOUT
GLOOP(s)
CF
VSEN
ωLC = ωF
ωESR
ωT
ω
RFB
To obtain the desired shape an RF - CF series network is considered for the ZF(s)
implementation. A zero at ωF = 1/RFCF is then introduced together with an integrator. This
integrator minimizes the static error while placing the zero ωF in correspondence with the L-C
resonance assures a simple -20dB/dec shape of the gain.
In fact, considering the usual value for the output filter, the LC resonance results to be at
frequency lower than the above reported zero.
Compensation network can be simply designed placing ωF=ωLC and imposing the cross-over
frequency ωT as desired obtaining (always considering that ωT might be not higher than 1/10th
of the switching frequency FSW):
L
C O ⋅ --R FB ⋅ ∆V O SC 5
3
L
R F = ---------------------------------- ⋅ --- ⋅ ω T ⋅ ------------------------------------------------------- C F = -------------------4
RF
3 ⋅ ( R DROOP + ESR )
V IN
36/44
L6701
15.1
15 System Control Loop Compensation
Compensation Network Guidelines
The Compensation Network design assures to having system response according to the crossover frequency selected and to the output filter considered: it is anyway possible to further finetune the compensation network modifying the bandwidth in order to get the best response of
the system as follow (See Figure 19):
●
Increase RF to increase the system bandwidth accordingly;
●
Decrease RF to decrease the system bandwidth accordingly;
●
Increase CF to move ωF to low frequencies increasing as a consequence the system
phase margin.
Having the fastest compensation network gives not the confidence to satisfy the requirements
of the load: the inductor still limits the maximum dI/dt that the system can afford. In fact, when a
load transient is applied, the best that the controller can do is to “saturate” the duty cycle to its
maximum (dMAX) or minimum (0) value. The output voltage dV/dt is then limited by the inductor
charge / discharge time and by the output capacitance. In particular, the most limiting transition
corresponds to the load removal since the inductor results being discharged only by VOUT
(while it is charged by dMAXVIN-VOUT during a load appliance).
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Referring to Figure 19-left, further tuning the Compensation network cannot give any
improvements unless the output filter changes: only modifying the main inductors or the output
capacitance improves the system response.
Figure 19. Best Load Transient achievable (d=0) and R F-CF impact on Bandwidth.
dB
CF
GLOOP(s)
K
ZF(s)
RF[dB]
RF
ωLC = ωF
ωESR
ωT
ω
37/44
16 Layout Guidelines
16
L6701
Layout Guidelines
Since the device manages control functions and high-current drivers, layout is one of the most
important things to consider when designing such high current applications. A good layout
solution can generate a benefit in lowering power-dissipation on the power paths, reducing
radiation and a proper connection between signal and power ground can optimize the
performance of the control loops.
Two kind of critical components and connections have to be considered when layouting a VRM
based on L6701: power components and connections and small signal components
connections.
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16.1
Power Components and Connections
These are the components and connections where switching and high continuous current flows
from the input to the load. The first priority when placing components has to be reserved to this
power section, minimizing the length of each connection and loop as much as possible. To
minimize noise and voltage spikes (EMI and losses) these interconnections must be a part of a
power plane and anyway realized by wide and thick copper traces: loop must be anyway
minimized. The critical components, i.e. the power transistors, must be close one to the other.
The use of multi-layer printed circuit board is recommended.
Figure 20 shows the details of the power connections involved and the current loops. The input
capacitance (CIN), or at least a portion of the total capacitance needed, has to be placed close
to the power section in order to eliminate the stray inductance generated by the copper traces.
Low ESR and ESL capacitors are preferred, MLCC are suggested to be connected near the HS
drain.
Use proper VIAs number when power traces have to move between different planes on the
PCB in order to reduce both parasitic resistance and inductance. Moreover, reproducing the
same high-current trace on more than one PCB layer will reduce the parasitic resistance
associated to that connection.
Connect output bulk capacitor as near as possible to the load, minimizing parasitic inductance
and resistance associated to the copper trace also adding extra decoupling capacitors along
the way to the load when this results in being far from the bulk capacitor bank.
Gate traces must be sized according to the driver RMS current delivered to the power
MOSFET. The device robustness allows managing applications with the power section far from
the controller without losing performances. Anyway, when possible, it is suggested to minimize
the distance between controller and power section.
38/44
L6701
16.2
16 Layout Guidelines
Small Signal Components and Connections
These are small signal components and connections to critical nodes of the application as well
as bypass capacitors for the device supply (See Figure 20). Locate the bypass capacitor (VCC
and Bootstrap capacitor) close to the device and refer sensible components such as frequency
set-up resistor ROSC to SGND. Star grounding is suggested: connect SGND to PGND plane in
a single point to avoid that drops due to the high current delivered causes errors in the device
behavior.
VSEN pin filtered vs. SGND helps in reducing noise injection into device: take care in routing
driving net for this pin in order to minimize coupled noise.
Remote Buffer Connection must be routed as parallel nets from the FBG/FBR pins to the load
in order to avoid the pick-up of any common mode noise. Connecting these pins in points far
from the load will cause a non-optimum load regulation, increasing output tolerance.
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Locate current reading components close to the device. It's also important to minimize any
offset in the measurement and, to get a better precision, to connect the traces as close as
possible to the sensing elements.
Caution: Boot Capacitor Extra Charge. Systems that do not use Schottky diodes might show big
negative spikes on the phase pin. This spike can be limited as well as the positive spike but has
an additional consequence: it causes the bootstrap capacitor to be over-charged. This extracharge can cause, in the worst case condition of maximum input voltage and during particular
transients, that boot-to-phase voltage overcomes the abs. max. ratings also causing device
failures. It is then suggested in this cases to limit this extra-charge by:
–
adding a small resistor in series to the boot diode (one resistor can be enough for all
the three diodes if placed upstream the boot diode anode, see Figure 20)
–
using non-capacitive boot diodes (such as standard diodes).
Figure 20. Power connections and related connections layout (same for all phases).
To limit CBOOT Extra-Charge
VIN
UGATEx
PHASEx
BOOTx
CIN
CBOOT
VIN
CIN
PHASEx
L
L
VCC
LGATEx
PGNDx
LOAD
LOAD
SGND
+Vcc
39/44
16 Layout Guidelines
16.3
L6701
Embedding L6701-based VRs
When embedding the VR into the application, additional care must be taken since the whole VR
is a switching DC/DC regulator and the most common systems in which it has to work are
digital systems such as MB or similar. In fact, latest MB has become faster and powerful: high
speed data bus are more and more common and switching-induced noise produced by the VR’
MOSFETs can affect data integrity if not following additional layout guidelines. Few easy points
must be considered mainly when routing traces and planes in which high switching currents
flow (high switching currents cause voltage spikes across the stray inductance of the trace
causing noise that can affect the near traces):
Keep safe guarding distance between high current switching VRD traces and data buses,
especially if high-speed data bus to minimize noise coupling.
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Keep safe guard distance or filter properly when routing bias traces for I/O sub-systems that
must walk near the VRD.
Possible causes of noise can be located in the PHASE connections, MOSFET gate drive and
Input voltage path (from input bulk capacitors and HS drain). Also PGND connections must be
considered if not insisting on a power ground plane. These connections must be carefully kept
far away from noise-sensitive data bus.
Since the generated noise is mainly due to the switching activity of the VR, noise emissions
depend on how fast the current switches. To reduce noise emission levels, it is also possible, in
addition to the previous guidelines, to reduce the current slope by properly tuning the HS gate
resistor and the PHASE snubber network.
40/44
L6701
17
17 Package Mechanical Data
Package Mechanical Data
In order to meet environmental requirements, ST offers these devices in ECOPACK®
packages. These packages have a Lead-free second level interconnect . The category of
second Level Interconnect is marked on the package and on the inner box label, in compliance
with JEDEC Standard JESD97. The maximum ratings related to soldering conditions are also
marked on the inner box label. ECOPACK is an ST trademark. ECOPACK specifications are
available at: www.st.com.
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41/44
L6701
17 Package Mechanical Data
PowerSSO-36 Mechanical Data
Dim.
A
A2
a1
b
c
D (1)
E(2)
e
e3
F
G
G1
H
h
L
M
N
O
Q
S
T
U
X
Y
mm
Min.
Typ.
2.15
2.15
0
0.18
0.23
10.10
7.4
inch
Max.
Min.
2.47
2.40
0.075
0.36
0.32
10.50
0.084
0.084
0
0.007
0.009
0.398
7.6
0.291
0.50
8.50
2.3
Typ.
Max.
0.097
0.094
0.003
0.014
0.012
0.413
0.299
0.020
0.035
0.090
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0.10
0.06
10.50
0.40
0.85
10.10
0.55
0.004
0.002
0.413
0.016
0.033
0.398
0.022
4.3
0.169
10° (max)
1.2
0.8
2.9
3.65
1.0
4.10
6.50
0.047
0.031
0.114
0.144
0.039
4.70
7.10
0.161
0.256
1. “D and E” do not include mold flash or protusions. Mold flash or protusions shall not exceed 0.15mm (0.006”)
2. No intrusion allowed inwards the leads.
3.
Flash or bleeds on exposed die pad shall not exceed 0.4 mm per side
Figure 21. Package Dimensions
42/44
0.185
0.279
L6701
18
18 Revision history
Revision history
Date
Revision
13-Dec-2005
1
Description of Changes
First draft
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L6701
18 Revision history
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Information furnished is believed to be accurate and reliable. However, STMicroelectronics assumes no responsibility for the consequences
of use of such information nor for any infringement of patents or other rights of third parties which may result from its use. No license is granted
by implication or otherwise under any patent or patent rights of STMicroelectronics. Specifications mentioned in this publication are subject
to change without notice. This publication supersedes and replaces all information previously supplied. STMicroelectronics products are not
authorized for use as critical components in life support devices or systems without express written approval of STMicroelectronics.
The ST logo is a registered trademark of STMicroelectronics.
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© 2005 STMicroelectronics - All rights reserved
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44/44
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