Controller IP for PCIe 3.0
PCI Express Datasheet
Controller IP for PCIe 3.0
Controller IP with PIPE Interface
Compliant with PCI Express® 3.0, 2.1, and 1.1
specifications, the Cadence Controller IP for
PCIe 3.0 has over 100 configuration features,
and 1500+ input parameters, to customize the
controller to the specific needs of any application.
Config Regs
HW Sec
Master Interface
Interrupt Interface
PHY for PCIe
The Cadence Controller IP for PCIe 3.0 provides
the logic required to integrate a Root Complex
(RC), Endpoint (EP), or Dual Mode (DM) controller
into any system on chip (SoC).
PCIe Core
Host Adaption Layer
Cadence IP Factory delivers custom,
synthesizable IP to support specific design
Target Interface
AXI Interface (optional)
Application Processor
1, 2, 4, 8,
or 16 Lanes
Figure 1: Example System-level Block Diagram
The Cadence Controller IP for PCIe 3.0 is architected to quickly and easily integrate into any SoC, and to connect seamlessly
to a Cadence, or third-party, PIPE 3.0- or PIPE 4.2-compliant PHY. Client applications access the controller through industry
standard ARM® AMBA® 3 AXI interface or through the native HAL interface.
The Cadence Controller IP for PCIe 3.0 is silicon-proven, and has been extensively validated with multiple hardware
platforms. As the first to market with a PCIe 3.0 x16 controller, Cadence IP Factory offers a comprehensive IP solution that is
in volume production, and has been successfully implemented in more than 400 applications.
Key Features
• Compliant with PCIe 3.0, 2.1, and 1.1 specifications
• ECRC and end-to-end datapath parity
• 250 or 500MHz core operation
• AMBA 3 and 4 AXI, and HAL client interface options
• Configurable as Root Complex, Endpoint, or Dual
• 16- or 32-bit PIPE 3.0 (v0.9), or PIPE 4.2 interface
• Ultra-low transmit/receive latency and high
• Supports Cadence or third party PHY designs
• Supports x1, x2, x4, x8, and x16 configurations
• Available separate PCLK input for PIPE interface
• Single Root IO Virtualization (SR-IOV) and bifurcation
• Up to 256 PCI Physical Functions or Virtual Functions
with Alternative Requester ID Interpretation support
• MSI, MSIx, and legacy interrupts supported
• Optional enhanced power management control
• ECNs and ECR supported
• Silicon-proven and shipping in volume
Product Details
Controller IP with PIPE Interface
The PCIe Core implements the physical layer, data link layer and
transaction layer of the PCIe protocol. The physical layer provides
the PIPE interface to easily connect to any PCIe-compliant PHY
device, and the Host Adaptation Layer (HAL), or optional AMBA
4 or 3 AXI, provides connectivity to the client. The PCIe Core
manages the functions of the PCIe protocol including data
deskewing, replay buffers, flow control, and CRC check and
Configuration Registers
The Cadence Controller IP for PCIe 3.0 implements a complete
set of PCI base configuration registers and PCI capability registers
for PCI power management, MSI and MSI-X, PCI Express and
Slot ID. In addition, the configuration registers have PCI Express
extended registers for advanced error reporting.
PIPE Interface
Physical Layer
(MAC Sublyer only)
Data Link Layer
Transaction Layer
Interrupt Interface
Host Adaption Layer
Master Interface
AXI Interface (optional)
PCIe Core
Target Interface
Client Interface
The Cadence Controller IP for PCIe 3.0 can be customized
as a RC, EP or operate in DM, supporting both the RC and EP
Local Management
Status and Error
PCLK (optional)
Figure 2: IP-level Block Diagram
or DMA engine can initiate a packet transfer to the PCIe link. The
datapath width on the Client Interface is configurable to 32-, 64-,
128-, or 256-bits depending upon the core generation and link
PIPE Interface
A local management bus (APB) is available to access configuration
and internal registers within the controller.
The PIPE 3.0 (v0.9) and PIPE 4.2 specifications are the industrystandard PHY Interfaces for the PCI Express Architecture v1.0, v2.0,
and v3.0. In addition, the PIPE Interface has an optional PCLK input
for running the PIPE Interface at a different clock rate than the
Client Interface
Cadence IP Factory
The Client Interface is implemented to support AMBA 4 or 3 AXI,
or a native Cadence interface, Host Adaptation Layer (HAL). The
Client Interface consists of separate master and target interfaces.
Cadence IP Factory can deliver various configurations of PCIe
controllers to meet your design requirements. For example, PCIe
3.0, 2.1, and PCIe 1.1.
The Target Interface is used for receiving transactions from the link
and sending responses back. With the Master Interface, the client
For more information, visit
• Low-risk solutions—silicon-proven design
• Clean, readable, synthesizable Verilog RTL
• Ease-of-use—customizable with easy integration
• Synthesis and STA scripts
• High performance—benchmarked at 95% of theoretical
maximum throughput
• Documentation – integration and user guide, release notes
• Sample verification testbench with integrated BFM and monitors
• FPGA platform for emulation and prototype development
Related Products
Available Products
• Controller IP for for PCIe 3.0
• Controller IP for PCIe 1.0/2.0
• PHY IP for PCIe 3.0
• Integrated Solution IP for PCIe 3.0
Cadence Design Systems enables global electronic design innovation and plays an essential role in the
creation of today’s electronics. Customers use Cadence software, hardware, IP, and expertise to design
and verify today’s mobile, cloud, and connectivity applications.
© 2015 Cadence Design Systems, Inc. All rights reserved worldwide. Cadence and the Cadence logo are registered trademarks of Cadence Design
Systems, Inc. in the United States and other countries. AMBA and ARM are registered trademarks of ARM Limited (or its subsidiaries) in the EU
and/or elsewhere. All rights reserved. AXI is a trademark of ARM Limited (or its subsidiaries) in the EU and/or elsewhere. PCI-SIG®, PCI Express®,
and PCIe® are registered trademarks and/or service marks of PCI-SIG. All other trademarks are the property of their respective owners.
V2.2 02/15, IP no. IP3020, IP3022, IP3024
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