Embedded Verification IP VARON/VSTAR

Embedded Verification IP VARON/VSTAR
Embedded Performance
Embedded Functional
Verification IP
Verification IP
Innovative Solution to a Verification Method!
The embedded Verification IP (VIP) within the device enables you to
visualize, monitor, capture as well as compile and analyze the data in real-time.
DUT
(ASIC, ASSP, FPGA)
CPU
CPU
CPU
CPU
Dedicated Application
System Bus - A
Visualizes System Performance in Real-time
information (data transfer rate, access to control registers) and
interrupt signal through wave forms/graphics
Real-time Verification by Checker
Enables logical and comprehensive monitoring of signs of issues and
problems by adding bus performance and functional checker to the
VIP attachment
Real-time Debugging by Analyzer
Enables multifaceted debugging through accessed information
captured in real-time or dedicated application which collects/
compares information
(C) Verification Technology, Inc. All Rights Reserved.
http://www.vtech-inc.co.jp/index_e.html
IP
IP
System Bus - B
DDRC
IP
(VARON/VSTAR Navigator)
VIP
Real-time Monitoring by Visual
Enables intuitive and instinctive monitoring of bus access
Bridge
External Tool
S/W Emulator (ICE)
IP
Real-time
Monitoring
Captured Data
Analyze
Acquire Bus Access Info
Probe through Attachment and
Controller
Visualizes and logs results of verification
・Enables to verify whether the performance or a control flow met
specification regarding bus master (CPU and DMA)
・Enables to verify whether the observed bandwidth met specified
bandwidth of bridges and memory controllers where bus access concentrates
・Enables to solve and optimize issues and problems based on a quantitative
criteria, and keeps the record of the decision
Embedded Performance
Embedded Functional
Verification IP
Verification IP
Accessible with External Tools
Covers Full Development Cycle and Various-use Cases
Spec Review
Mass Production/Maintenance
Design/Verification
DUT
H/W・S/W
Hardware
Design/Verification
Functional
Partitioning
Failure Analysis
in case of
detecting issues
System
Tuning
Continue tuning
to improve
product performance
(ASIC, ASSP, FPGA)
CPU
IP
Events and values can tackle long-term low-reproducibility issues/problems
■ Enables to solve defects at an early stage, improve product
performance, and improve the system of the next product
(C) Verification Technology, Inc. All Rights Reserved.
http://www.vtech-inc.co.jp/index_e.html
IP
System Bus - B
IP
H/W Simulator
(ex: DS-5)
(ex: Incisive・QuestaSim)
CPU
IP
Dedicated Application
(VARON/VSTAR Navigator)
Real-time
Monitor/Capture
Wave Form/Analyzed
data
File output
Export
Controller and Attachments
* Able to implement VARON in H/W Emulator
Checker
Generation
(SVA Compiler)
■ VARON has strength in extracting and analyzing issues by collecting
performance counter/timer values (latency, rate and processing time).
(Main usage: Performance analysis during prototyping, system tuning)
CPU
S/W Emulator
System Bus - A
Bridge
DDRC
■ VSTAR has strength in extracting and analyzing problems through
collecting system status of bus master events (bus access and interrupt
signal).
(Main usage: Isolate problems between H/W and S/W, debugging
CPU
VIP
Prototyping
Software
Design/Debugging
System
Debugging
Real-time
Monitor/Capture
Compiles SVA to
RTL
Embed into VIP
Aggregate/Statistical Wave FormViewer
Analysis
(ex: GTKWave・Verdi)
(ex: Excel・R)
SVA compiler is a tool to compile
System Verilog Assertion (SVA) to
RTL 【Vtech original product】
Continue tackling issues and problems through a user’s familiar environment
■ ■ Enables to solve defects at an early stage, improve product
performance, and improve the system of the next product
Embedded Performance
Embedded Functional
Verification IP
Verification IP
(VIP)
Verification
IP
(Probes)
Attachments Connect with Bus Standards (e.g., AXI3/AXI4)
VARON
VARON
VSTAR
Configuration: Attachment Setting and Connection
―
○
○
Attachment Generation, SVA Compiler Activation
○(Option)
○
○
List of Major Functions
(2.2.2)
(New)
(New)
DUT
Verification IP =
(ASIC, ASSP, FPGA)
Event Definition (SVA-RTL, Address/Data, Interrupt pin, Free pin)
○(Option)
○
CPU
Monitor
Bus Function Real-time Display (Chronological Order, Visualized Graphs)
○
○(Option)
○
○
○(Chronological
○
―
―
―
○
Order)
Control Flow Real-time Display (Chronological Order, Visualized Graph)
Capture
Trigger Function (START & STOP Condition, Trigger Position, Event Selection)
○(Option)
○
○
Access Log Capture (Address, Data, R/W)
―
―
○
Wave Form Capture (Free pin)
○
○
○
Bus Function Monitor Data Display (Chronological Order, Visualized Graph)
○
―
―
―
○
○(Option)
○
―
Export Function (File Output to External Tools)
○
○
○
Automatic Optimizer (Auto-tuning on Performance)
―
○(Option)
―
Software Profiler Link (VIP Control + Display via ICE)
―
○
―
Analyzer
○(Chronological
Order Only)
Control Flow Monitor Data Display (Chronological Order, Visualized Graph)
Statistics Analysis Script (Detailed Statistics Display)
Users’ needs will be reflected to our products
Enables users to acquire up-to-date verification environment
(C) Verification Technology, Inc. All Rights Reserved.
http://www.vtech-inc.co.jp/index_e.html
CPU
CPU
System Bus - A
Bridge
Trigger Function (START & STOP Condition, Trigger Position, Event Selection)
VIP
Attachment
IP
IP
IP
Attachment
Attachment
Attachment
Attachment
System Bus - B
DDRC
CPU
IP
Controller
Evolving
With an easy attachment to AXI3/AXI4,
information is transferred to PC.
Serial
V-BOX
USB2.0
VARON/VSTAR
Navigator
(Converter)
Data Transfer rate: 4096byte/1ms
Attachment
Monitoring
Analysis
Example
Attachment for
Function Verification
Attachment for
Performance Verification
・Access Counter
(Information on transfer and burst frequency)
・Access Cycle Counter
(Time information on latency and access cycle)
・Access Event Flag
(Determine the presence or the absence of access, and info on
occurred time)
・Access Log Capture
(Access information including address, data and R/W)
Attachment for Both VARON and VSTAR
・User defined event flag (SVA-RTL, Interrupt, Free pin)
・User defined wave form capture(Free pin)
New attachment development is on-going to meet customers’ request
Enables users to embed VARON/VSTAR easily to your next gen. device
Embedded Performance
Embedded Functional
Verification IP
Verification IP
(Probes)
Performance and Function Attachment
■Performance Attachment(VARON) counts bus access info per clock
within the attachment, and transfers info to PC in real-time.
Sampling period
Clock
Addres
Datas
■Detects bus access per clock
■Transfers performance results to PC
- Transaction
- Latency
- Quantity
4 cycle
4 cycle 3 cycle 1 cycle
: Total 2 times
: Total 7 cycles
: Total 5 cycles
Performance and Function
■When configuring Events, IDs are given to signal from SVA-RTL,
internal signal, and bus access (Address/data).
Complicated conditions including bus access can be simplified by IDs.
① PC → VIP configuration: Event condition to be monitored
② VIP → PC notification: Occurred event info
(4cycle + 3cycle)
(4cycle + 1cycle)
(*)Performance results can be displayed on PC as histogram,
in both total value and values in threshold range.
CPU1 CPU2
■Function attachment (VSTAR) converts bus access info into events
and flags within the attachment, and transfers to PC in real-time.
CPU1 CPU2
BUS
IP1
IP2
Event
Flag
0001
0010
0100
1000
BUS Access
(Address/Data)
CPU1→IP1 Write
CPU1→IP2 Write
CPU2→IP1 Write
CPU2→IP2 Write
■Detects bus access per clock
■Controls register access and converts
insert signal into flag, and transfers to
PC
(*) Event can also be used as a Trigger.
■Wave form capture (free pin) and access log capture are captured
per clock, and a specified range will be transferred to PC.
Time
CPU1
CPU2
IP1
IP2
内部信号
■Trigger saves bus access info to SRAM
and transfers to PC 【Access Log】
■Trigger saves internal signal into SRAM,
and transfers to PC 【VCD Wave Form
File】
Attachments are prepared based on usages to start verification immediately
(C) Verification Technology, Inc. All Rights Reserved.
Event/Trigger
http://www.vtech-inc.co.jp/index_e.html
BUS
IP1
IP2
Event ID
1
2
3
4
CPU ID
1
1
2
2
Examples of
Address
F0001000
F0002000
F0001000
F0002000
Bus access
Data
00000001
00000001
00000002
00000002
R/W
W
W
W
W
■Trigger configuration uses Event ID to set sequential (Event
Event) and time latency (Event time) and becomes
trigger for real-time monitoring and capture.
Simplify complicated conditions including bus access with ID
msec
AXI
Read
Trafic
AXI
Write
Trafic
Nearby trigger
■Displays events prior to trigger
■Enables to monitor and capture
specifying time (e.g., pre-trigger, ontrigger, or post-trigger)
Event
Enables to isolate problems and issues through event trigger
Embedded Performance
Embedded Functional
Verification IP
Verification IP
Real-time Monitoring
Analyzer Mode
■Performance attachment (VARON) and function attachment (VSTAR)
acquire information real-time, and displays info of approx. 3 seconds
in one screen . Enables to visualize signs of issues and problems.
■Information from performance attachment (VARON) and function
attachment (VSTAR)enables to visualize signs of issues and problems.
When stopped on a spot decision, approx. 150 sec. of info prior to stop
is saved, and able to analyze it later.
■Bus Performance Graph (e.g., Memory)
■Control Sequence (e.g., CPU)
Approx. 3 sec.
AXI
SVA
msec
AXI4-Lite
Read
Trafic
Interrupt
Write
Trafic
CPU
Event
R/W
Event
E.g., Disarray due to coalition on
R/W access to memory
Detection
AXI
SVA
AXI4-Lite
Read
Trafic
Interrupt
Write
Trafic
R/W
Event
AXI
SVA
E.g., Disarray of sequence from
Detection
CPU which controls peripheral
circuits (register R/W, interruption )
R/W
Competition
NG!
CPU
Event
Read
Trafic
AXI4-Lite
Interrupt
Write
Trafic
CPU
Event
R/W
Event
E.g., Disarray due to coalition on
R/W access causing 帯域の低下
Busy
Missing
Event
NG!
Enables intuitive and instinctive analysis
(C) Verification Technology, Inc. All Rights Reserved.
msec
Detection
Traffic ratio
01
02
03
04
05
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■Control Sequence (E.g., CPU)
Approx. 150 sec.
msec
AXI
01
02
03
04
05
Control Flow (Sequential)
Approx. 150 sec.
msec
msec
AXI
■Bus Performance Graph (E.g., Memory)
Approx. 3 sec.
msec
AXI
Performance Graph (Sequential)
Control Flow (Sequential)
Performance Graph(Sequential)
(Collision)
Busy
Read
Write
(Collision)
R/W
Competition
NG!
01
02
03
04
05
E.g., Abnormality of sequence from
Detection
CPU which controls peripheral
circuits (register R/W, interruption )
Sequence histogram
Read
Write
Event
05 Missing
(NG)
Event
01 - 05
(OK)
Enables analysis by graphical data
Embedded Performance
Embedded Functional
Verification IP
Verification IP
New Function “
Visualization”
Performance Graph (Sequential)
Trigger
Trigger
Trigger
Trigger
Intuitive and Instinctive + Logical and Comprehensive
Control Flow (Sequential)
Trigger
Trigger
E1
E1
E2
E1
E2
E3
Trigger
E1
E2
E3
■Visualization through overlap and grey
scaling residual image 【Transitional Graph
E1
E2
E3
【Sequential Graph】
E2
E3
■Visualization enables to show information that are unable to see at once
or compare. It also enables to arrange information, and enables users to
draw a solution intuitively and instinctively. In other words, it enables
users to estimate what the issues are.
Trigger
Trigger
Overlapped Graph
【Transitional Graph】
01
E3
02
05
02
(example)
Trigger
04
Trigger
E1
【Sequential Graph】
01
05
Overlapped Graph (example)
■Visualization through overlap and
coloring residual image
03
04
03
■Generates a Checker using critical and irregular conditions which were found
through visualization. Installing them onto an attachment in the verification
IP, it enables to monitor signs of issues and problems logically and comprehensibly.
E1
E2
E3
■Visualization through overlapping results
【Sequential Graph】
Delayed start
(Due to laytency)
Peak detection
Stop delay
(Due to transfer
(Due to transfer rate)
rate)
Delayed start
(Sign of a bug)
With the visualized graph…
Check whether there is
any transition
(Bug phenomenon)
Stop delay
(Sign of a bug)
With the visualized graph…
Critical extraction
Irregular extraction
(Issue)
(Problem)
Enables intuitive and instinctive analysis
(C) Verification Technology, Inc. All Rights Reserved.
http://www.vtech-inc.co.jp/index_e.html
【Transition Graph】
01
Caution
Value Limit
Irregular
State Change
Caution
Timing Limit
05
02
04
■Store as numerical data
・Margin against threshold limit (sign)
・Frequency of issues or problems
■Sequentially re-visualized using stored
data
03
Enables multi-faceted analysis
Embedded Performance
Embedded Functional
Verification IP
Verification IP
(New Feature)
Optimizer
■As the scale of IC became larger, the combination of values adjusting
system performance (e.g., control register) increases. Have you ever
experienced your target device stopped suddenly when minor modifications
to parameters were made?
■By adding the Automatic Optimizer (option), it enables
users to optimize register values automatically, which
enables users to automatically seek for system’s
optimized register values.
DUT
(ASIC, ASSP, FPGA)
CPU
CPU
CPU
CPU
IP
System Bus - B
DDRC
IP
( VARON/VSTAR Navigator)
IP
DUT
(ASIC, ASSP, FPGA)
CPU
CPU
IP
IP
System Bus - B
Performance Indicator
CPU
System Bus - A
Bridge
Progress Log Progress Graph
■By adding S/W Profiler Link (option), VARON performance
info are acquired through S/W emulator. Enables users to
conduct performance verification on both S/W and H/W
simultaneously.
DDRC
IP
S/W emulator
VIP
IP
① Takes some time to memorize how to use new tools
② Would like to compare both S/W and H/W performance to do
tradeoffs, but the tools are different.
Register value and results (Best)
VIP
Bridge
■Have you ever experienced below when verifying performance and
function of both S/W and H/W?
CPU
Dedicated Application
System Bus - A
New Feature: S/W Profiler Link
S/W Performance Info
(ex: DS-5)
H/W Performance Info(Insert)
IP
S/W Processing Status
Controller and Attachments
Collects performance info
Controller and Attachments
Automatically adjust and seek register values.
Enables Automatic adjustment based on VARON’s performance measurement results.
The tool enables you to present your users the register value with operating results.
(C) Verification Technology, Inc. All Rights Reserved.
http://www.vtech-inc.co.jp/index_e.html
Collects H/W performance info
Display H/W info through S/W emulator
Enables to see H/W performance using accustomed S/W profiler simultaneously
Enables to confirm H/W performance using users’ accustomed tool. Reduces installation cost as well.
Embedded Performance
Embedded Functional
Verification IP
Verification IP
■What is the difference between other party’s Analyzer (pattern analysis) and Profiler (performance)?
■What does the product consist of?
The product consists of (1) attachment and control circuit (soft IP),
(2) USB device driver for Windows PC, and (3) a dedicated application.
PC communication board (V-BOX) and cables are option.
Please consult with our Sales team when embedding into ASIC/ASSP as
it requires additional implementation info per processes and tools.
One of the major differences of Vtech products is that it is independent to FPGA/ASIC
vendor and design tools.
Another difference is that it does not retrieve wave form at a clock level nor configure
trigger settings like other analyzers. Instead, it retrieves necessary information and
configure triggers from bus transaction, which is specifically targeted for verifying
performance and function. The concept of visualization is also different to others.
Utilizing our products, users can narrow down issues and problems. When analysis
is required at a clock level, market-available tools per each vendor can also be used.
Our products supplement with their tools.
■How can I purchase?
When installing it onto FPGA, it is a licensing fee (annual contract) per
product purchase qty.
When embedding into ASIC/ASSP, a royalty contract per device shipment
qty is needed in addition to the licensing fee. For more details, please contact our Sales team.
■What Operating System is needed?
The product requires Windows7 PC (64bit), Intel Core i7 or above,
16GB memory or more is preferred. Xilinx or Altera’s FGPAs are assumed.
While our products are capable in retrieving wave forms, they limit to a certain wave
forms due to product concept.
Contact
Verification Technology, Inc.
■What is the IC circuit scale for ASIC/ASSP/FPGA?
The product is approx. 5k~90k gates per unit for attachment, and approx. 3k gates for
a controller. IC circuit scale varies per type and qty of attachments as well as processes.
Attachments can be connected up to 64. However, there is a limitation of 4,096 byte
of traffic to PC. The qty of attachments changes if they have many counters.
Please consult with our Sales team for IC circuit scale and attachments.
■What are the connection spec (pin counts and voltage) when
connecting to ASIC/ASSP/FPGA?
The product’s standard connection designed with 3-wire system (3.3V, TTL/CMOS) or
6-wire System (LVDS), with a transfer frequency of 20MHz~50MHz, transfer speed of
10Mbps~25Mbps.
LVDS is expandable up to 200MHz and 200Mbps depending on interconnection length
of terminal, board and cable. Please consult with our Sales Team prior to installment.
(C) Verification Technology, Inc. All Rights Reserved.
http://www.vtech-inc.co.jp/index_e.html
Email
URL(Japanese)
URL(English)
Headquart
ers
Osaka
Branch
Office
: v-sales@vtech-inc.co.jp
: www.vtech-inc.co.jp/
: www.vtech-inc.co.jp/index_e.html
Shin-yokohama Square Bldg. 5F
2-3-12, Shin-yokohama, Kohoku-ku, Yokohama City, 222-0033 Japan
Tel:045-470-8310 Fax:045-470-8319
Shindai Bldg., 23F, 1-2-1, Dojimahama, Kita-ku, Osaka City, 530-0004 Japan
Tel:06-4795-6662 Fax:06-4795-6663
Verification Technology USA, Inc.
99 South Almaden Blvd., Suite 616, San Jose, CA 95113 U.S.A.
Overseas
Offices
Verification Technology Philippines, Inc.
3/F King’s Court Bldg1, 2129 Don Chino Roces Ave, Makati, Metro Manila, Philippines
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