53C810 data sheet (SCSI processor)

53C810 data sheet (SCSI processor)
SYM53C810A
PCI-SCSI I/O Processor
Data Manual
Version 2.0
.
I N C R E A S I N G
S C S I
R E L I A B I L I T Y
N E G A T I O N
T E C H N O L O G Y
TolerANT
®
A C T I V E
T07962I
The products described in this publication are product s of Symbios Logic Inc.
SCRIPTS is a trademark and TolerANT is a registered trademark of Symbios Logic
Inc.
It is the policy of Symbios Logic to improve products as new technology,
components, software, and firmware become available. Symbios Logic, therefore,
reserves the right to change specifications without notice.
The products in this manual are not intended for use in life-support appliances,
devices, or systems. Use of these products in such applications without the written
consent of the appropriate Symbios Logic officer is prohibited
Copyright ©1995, 1996
By Symbios Logic Inc.
All Rights Reserved
Printed in U.S.A.
We use comments from our readers to improve Symbios product literature. Please
e-mail any comments regarding technical documentation to pubs@symbios.com.
Preface
Preface
SCSI and PCI Reference
Information
This manual assumes some prior knowledge of current and proposed SCSI and PCI standards. For background information, please contact:
ANSI
11 West 42nd Street
New York, NY 10036
(212) 642-4900
Ask for document number X3.131-199X (SCSI-2)
Global Engineering Documents
15 Inverness Way East
Englewood, CO 80112
(800)-854-7179 or (303) 792-2181 (outside U.S.)
Ask for document number X3.131-1994 (SCSI-2) or X3.253 (SCSI-3 Parallel Interface)
ENDL Publications
14426 Black Walnut Court
Saratoga, CA 95070
(408) 867-6642
Document names: SCSI Bench Reference, SCSI Encyclopedia
Prentice Hall
Englewood Cliffs, NJ 07632
(201) 767-5937
Ask for document number ISBN 0-13-796855-8, SCSI: Understanding the Small Computer System Interface
Symbios Logic Electronic Bulletin Board
(719) 573-3562
SCSI Electronic Bulletin Board
(719) 533-7950
Symbios Logic Internet Anonymous FTP Site
ftp.symbios.com (204.131.200.1)
Server:Bastion
Directory: /pub/symchips/scsi
Symbios Logic World-Wide Web Home Page
http://www.symbios.com
PCI Special Interest Group
P.O. Box 10470
Portland, OR 97214
(800) 433-5177; (503) 797-4201 (International); FAX (503) 234-6762
Symbios Logic PCI-SCSI Programming Guide
SYM56C810A Data Manual
i
Document History
Document History
ii
Page No.
Date
Remarks
n/a
6/95
Rev 1.0
1-1,1-3, 1-5, 2-1—24, 2-10, 2-11, 2-13,
3-2, 3-4, 3-6, 3-7, 39, 3-10, 4-1, 4-4, 46, 4-7, 5-1, 5-10, 512, 5-13—5-16, 521, 5-31, 5-35, 5-50,
6-23—6-25, 7-1, 7-2,
7-9, 7-13, 7-24
7/96
Version 2.0
SYM56C810A Data Manual
Contents
Contents
Preface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . i
SCSI and PCI Reference Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . i
Document History . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ii
List of Figures . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . xiii
List of Tables . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . xv
Chapter 1
Introduction
What is Covered in This Manual . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-1
General Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-1
TolerANT Technology . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-2
SYM53C810A Benefits Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
SCSI Performance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
PCI Performance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Integration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Flexibility . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Reliability . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Testability . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
1-3
1-3
1-3
1-3
1-4
1-4
1-4
Chapter 2
Functional Description
SCSI Core . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-1
DMA Core . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-1
SCRIPTS Processor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-1
SDMS: The Total SCSI Solution . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-2
Prefetching SCRIPTS Instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-2
Op Code Fetch Burst Capability . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-2
PCI Cache Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-3
Load/Store Instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-3
3.3 Volt/5 Volt PCI Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-3
Loopback Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-3
Parity Options . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-3
DMA FIFO . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Data Paths . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Asynchronous SCSI Send . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Synchronous SCSI Send . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Asynchronous SCSI Receive . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Synchronous SCSI Receive . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
SYM53C810A Data Manual
2-6
2-7
2-7
2-7
2-7
2-7
iii
Contents
SCSI Bus Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-9
Terminator Networks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-9
(Re)Select During (Re)Selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-9
Synchronous Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-11
Determining the Data Transfer Rate . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-11
SCNTL3 Register, bits 6–4 (SCF2–0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-11
SCNTL3 Register, bits 2–0 (CCF2–0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-11
SXFER Register, bits 7–5 (TP2–0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-11
Achieving Optimal SCSI Send Rates . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-11
Interrupt Handling . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-13
Polling and Hardware Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-13
Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-13
ISTAT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-13
SIST0 and SIST1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-13
DSTAT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-13
SIEN0 and SIEN1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-14
DIEN . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-14
DCNTL . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-14
Fatal vs. Non-Fatal Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-14
Masking . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-14
Stacked Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-15
Halting in an Orderly Fashion . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-15
Sample Interrupt Service Routine . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-16
Chapter 3
PCI Functional Description
PCI Addressing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-1
PCI Bus Commands and Functions Supported . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-1
PCI Cache Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-2
Support for PCI Cache Line Size Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-2
Selection of Cache Line Size . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-2
Alignment . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-2
MMOV Misalignment . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-2
Memory Write and Invalidate Command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-3
Multiple Cache Transfers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-3
Latency . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-3
PCI Target Retries . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-3
PCI Target Disconnect . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-3
Memory Read Line Command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-4
Memory Read Multiple Command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-4
Burst Size Selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-5
Read Multiple with Read Line Enabled . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-5
Unsupported PCI Commands . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-5
iv
SYM53C810A Data Manual
Contents
Configuration Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-6
Register 00h
Vendor ID
Read Only . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-7
Register 02h
Device ID
Read Only . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-7
Register 04h
Command
Read/Write . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-7
Register 06h
Status
Read/Write . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-8
Register 08h
Revision ID
Read Only . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-10
Register 09h
Class Code
Read Only . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-10
Register 0Ch
Cache Line Size
Read/Write . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-10
Register 0Dh
Latency Timer
Read/Write . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-10
Register 0Eh
Header Type
Read Only . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-11
Register 10h
Base Address Zero (I/O)
Read/Write . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-11
Register 14h
Base Address One (Memory)
Read/Write . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-11
Register 3Ch
Interrupt Line
Read/Write . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-11
Register 3Dh
Interrupt Pin
Read Only . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-11
Register 3Eh
Min_Gnt
Read Only . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-11
Register 3Fh
Max_Lat
Read Only . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-11
SYM53C810A Data Manual
v
Contents
Chapter 4
Signal Descriptions
Chapter 5
Operating Registers
Register 00 (80)
SCSI Control Zero (SCNTL0)
Read/Write . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-5
Register 01 (81)
SCSI Control One (SCNTL1)
Read/Write . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-7
Register 02 (82)
SCSI Control Two (SCNTL2)
Read/Write . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-9
Register 03 (83)
SCSI Control Three (SCNTL3)
Read/Write . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-9
Register 04 (84)
SCSI Chip ID (SCID)
Read/Write . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-11
Register 05 (85)
SCSI Transfer (SXFER)
Read/Write . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-11
Register 06 (86)
SCSI Destination ID (SDID)
Read/Write . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-13
Register 07 (87)
General Purpose (GPREG)
Read/Write . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-14
Register 08 (88)
SCSI First Byte Received (SFBR)
Read/Write . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-14
Register 09 (89)
SCSI Output Control Latch (SOCL)
Read /Write . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-15
Register 0A (8A)
SCSI Selector ID (SSID)
Read Only . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-15
Register 0B (8B)
SCSI Bus Control Lines (SBCL)
Read Only . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-16
Register 0C (8C)
DMA Status (DSTAT)
Read Only . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-16
Register 0D (8D)
SCSI Status Zero (SSTAT0)
Read Only . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-17
Register 0E (8E)
SCSI Status One (SSTAT1)
Read Only . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-18
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Register 0F (8F)
SCSI Status Two (SSTAT2)
(Read Only) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Registers 10-13 (90-93)
Data Structure Address (DSA)
Read/Write . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Register 14 (94)
Interrupt Status (ISTAT)
(Read/Write) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Register 18 (98)
Chip Test Zero (CTEST0)
Read/Write . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Register 19 (99)
Chip Test One (CTEST1)
Read Only . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Register 1A (9A)
Chip Test Two (CTEST2)
Read Only . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Register 1B (9B)
Chip Test Three (CTEST3)
Read/Write . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Registers 1C-1F (9C-9F)
Temporary (TEMP)
Read/Write . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Register 20 (A0)
DMA FIFO (DFIFO)
Read/Write . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Register 21 (A1)
Chip Test Four (CTEST4)
Read/Write . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Register 22 (A2)
Chip Test Five (CTEST5)
Read/Write . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Register 23 (A3)
Chip Test Six (CTEST6)
Read/Write . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Registers 24-26 (A4-A6)
DMA Byte Counter (DBC)
Read/Write . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Register 27 (A7)
DMA Command (DCMD)
Read/Write . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Registers 28-2B (A8-AB)
DMA Next Address (DNAD)
Read/Write . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Registers 2C-2F (AC-AF)
DMA SCRIPTS Pointer (DSP)
Read/Write . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Registers 30-33 (B0-B3)
DMA SCRIPTS Pointer Save (DSPS)
Read/Write . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
SYM53C810A Data Manual
5-19
5-20
5-20
5-22
5-23
5-23
5-24
5-25
5-26
5-26
5-27
5-28
5-28
5-29
5-29
5-30
5-30
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Contents
Registers 34-37 (B4-B7)
Scratch Register A (SCRATCH A)
Read/Write . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-31
Register 38 (B8)
DMA Mode (DMODE)
Read/Write . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-31
Register 39 (B9)
DMA Interrupt Enable (DIEN)
Read/Write . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-33
Register 3A (BA)
Scratch Byte Register (SBR)
Read/Write . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-33
Register 3B (BB)
DMA Control (DCNTL)
Read/Write . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-34
Register 3C-3F (BC-BF)
Adder Sum Output (ADDER)
Read Only . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-35
Register 40 (C0)
SCSI Interrupt Enable Zero (SIEN0)
Read/Write . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-36
Register 41 (C1)
SCSI Interrupt Enable One (SIEN1)
Read/Write . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-37
Register 42 (C2)
SCSI Interrupt Status Zero (SIST0)
Read Only . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-38
Register 43 (C3)
SCSI Interrupt Status One (SIST1)
Read Only . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-40
Register 44 (C4)
SCSI Longitudinal Parity (SLPAR)
Read/Write . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-40
Register 46 (C6)
Memory Access Control (MACNTL)
Read/Write . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-41
Register 47 (C7)
General Purpose Pin Control (GPCNTL)
Read/Write . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-41
Register 48 (C8)
SCSI Timer Zero (STIME0)
Read /Write . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-42
Register 49 (C9)
SCSI Timer One (STIME1)
Read/Write . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-43
Register 4A (CA)
Response ID (RESPID)
Read/Write . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-43
Register 4C (CC)
SCSI Test Zero (STEST0)
Read Only . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-44
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Register 4D (CD)
SCSI Test One (STEST1)
Read/Write . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Register 4E (CE)
SCSI Test Two (STEST2)
Read/Write . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Register 4F (CF)
SCSI Test Three (STEST3)
Read/Write . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Register 50 (D0)
SCSI Input Data Latch (SIDL)
Read Only . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Registers 54 (D4)
SCSI Output Data Latch (SODL)
Read/Write . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Registers 58 (D8)
SCSI Bus Data Lines (SBDL)
Read Only . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Registers 5C-5F (DC-DF)
Scratch Register B (SCRATCHB)
(Read/Write) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
5-45
5-45
5-46
5-47
5-48
5-48
5-49
Chapter 6
Instruction Set of the I/O Processor
SCSI SCRIPTS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-1
Sample Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-2
Block Move Instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-4
First Dword . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-4
Second Dword . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-8
I/O Instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-8
First Dword . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-8
Second Dword . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-13
Read/Write Instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
First Dword . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Second Dword . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Read-Modify-Write Cycles . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Move to/from
SFBR Cycles . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
6-14
6-14
6-14
6-14
6-14
Transfer Control Instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-17
First Dword . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-17
Second Dword . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-21
Memory Move Instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
First Dword . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Second Dword . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Third Dword . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Read/Write System Memory from a SCRIPTS Instruction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
6-21
6-23
6-23
6-23
6-23
Load and Store Instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-24
First Dword . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-24
Second Dword . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-24
SYM53C810A Data Manual
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Contents
Chapter 7
Electrical Characteristics
DC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-1
TolerANT Technology . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-6
AC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-9
PCI Interface Timing Diagrams . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-11
Target Cycles . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-11
Initiator Cycles . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-11
PCI Interface Timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-22
SCSI Timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-23
Initiator Asynchronous Send . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-23
Initiator Asynchronous Receive . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-24
Target Asynchronous Send . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-25
Target Asynchronous Receive . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-26
Initiator and Target Synchronous Transfers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-27
Appendix A
Register Summary
Appendix B
Mechanical Drawing
Index . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . I-1
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SYM53C810A Data Manual
List of Figures
List of Figures
Figure 1-1: SYM53C810A System Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-5
Figure 1-2: SYM53C810A Chip Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-5
Figure 2-1: DMA FIFO Sections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-6
Figure 2-2: SYM Host Interface Data Paths . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-8
Figure 2-3: Active or Regulated Termination . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-10
Figure 2-4: Determining the Synchronous Transfer Rate
Figure 3-1: PCI Configuration Register Map
. . . . . . . . . . . . . . . . . . . . . . . . . . . 2-12
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-6
Figure 3-2: Command Register Layout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-8
Figure 3-3: Status Register Layout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-9
Figure 4-1: SYM53C810A Pin Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-1
Figure 4-2: Functional Signal Grouping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-3
Figure 5-1: SYM53C810A Register Address Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-4
Figure 6-1: SCRIPTS Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-3
Figure 6-2: Block Move Instruction Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-5
Figure 6-3: I/O Instruction Register
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-10
Figure 6-4: Read/Write Register Instruction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-15
Figure 6-5: Transfer Control Instruction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-18
Figure 6-6: Memory to Memory Move Instruction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-22
Figure 6-7: Load and Store Instruction Format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-25
Figure 7-1: Rise and Fall Time Test Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-7
Figure 7-2: SCSI Input Filtering . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-7
Figure 7-3: Hysteresis of SCSI Receiver . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-8
Figure 7-4: Input Current as a Function of Input Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-8
Figure 7-5: Output Current as a Function of Output Voltage . . . . . . . . . . . . . . . . . . . . . . . . . 7-8
Figure 7-6: Clock Timing Waveform
Figure 7-7: Reset Input Waveforms
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-9
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-10
Figure 7-8: Interrupt Output Waveforms
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-10
Figure 7-9: PCI Configuration Register Read . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-12
Figure 7-10: PCI Configuration Register Write . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-13
Figure 7-11: Target Read . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-14
Figure 7-12: Target Write . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-15
SYM53C810A Data Manual
xi
List of Figures
Figure 7-13: Op Code Fetch, non-burst . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-16
Figure 7-14: Burst Op Code Fetch . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-17
Figure 7-15: Back to Back Read . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-18
Figure 7-16: Back to Back Write
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-19
Figure 7-17: Burst Read . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-20
Figure 7-18: Burst Write
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-21
Figure 7-19: Initiator Asynchronous Send Waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-23
Figure 7-20: Initiator Asynchronous Receive Waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-24
Figure 7-21: Target Asynchronous Send Waveforms
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-25
Figure 7-22: Target Asynchronous Receive Waveforms
. . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-26
Figure 7-23: Initiator and Target Synchronous Transfers . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-27
xii
SYM53C810A Data Manual
List of Tables
List of Tables
Table 2-1: Bits Used for Parity Control and Observation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-4
Table 2-2: SCSI Parity Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-5
Table 2-3: SCSI Parity Errors and Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-5
Table 3-1: PCI Bus Commands and Encoding Types . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-5
Table 4-1: Power and Ground Pins. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-2
Table 4-2: System Pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-4
Table 4-3: Address and Data Pins. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-4
Table 4-4: Interface Control Pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-5
Table 4-5: Arbitration Pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-5
Table 4-6: Error Reporting Pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-6
Table 4-7: SCSI Pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-6
Table 4-8: Additional Interface Pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-7
Table 5-1: Operating Register Addresses and Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-1
Table 5-2: Synchronous Clock Conversion Factor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-10
Table 5-3: Asynchronous Clock Conversion Factor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-10
Table 5-4: Examples of Synchronous Transfer Periods and Rates for SCSI-1 . . . . . . . . . . . . . 5-12
Table 5-5: Examples of Synchronous Transfer Periods and Rates for Fast SCSI . . . . . . . . . . . 5-12
Table 5-6: SCSI Synchronous Offset Values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-13
Table 6-1: Read/Write Instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-16
Table 7-1: Absolute Maximum Stress Ratings. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-1
Table 7-2: Operating Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-2
Table 7-3: SCSI Signals - SD(7-0)/, SDP/, SREQ/ SACK/ . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-2
Table 7-4: SCSI Signals - SMSG, SI_O/, SC_D/, SATN/, SBSY/, SSEL/, SRST/. . . . . . . . . . . 7-3
Table 7-5: Input Signals - CLK, SCLK, GNT/, IDSEL, RST/, TESTIN . . . . . . . . . . . . . . . . . 7-3
Table 7-6: Capacitance. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-3
Table 7-7: Output Signal - MAC/_TESTOUT, REQ/ . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-4
Table 7-8: Output Signal - IRQ/ . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-4
Table 7-9: Output Signal - SERR/ . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-4
Table 7-10: Bidirectional Signals - AD(31-0), C_BE/(3-0), FRAME, IRDY/, TRDY/,
DEVSEL/, STOP/, PERR/, PAR . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-5
SYM53C810A Data Manual
xiii
List of Tables
Table 7-11: Bidirectional Signals - GPIO0_FETCH/, GPIO1_MASTER/ . . . . . . . . . . . . . . . . 7-5
Table 7-12: TolerANT Active Negation Technology Electrical Characteristics. . . . . . . . . . . . . 7-6
Table 7-13: Clock Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-9
Table 7-14: Reset Input Timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-10
Table 7-15: Interrupt Output Timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-10
Table 7-16: SYM53C810A PCI Timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-22
Table 7-17: Initiator Asynchronous Send Timings (5 MB/s). . . . . . . . . . . . . . . . . . . . . . . . . . 7-23
Table 7-18: Initiator Asynchronous Receive Timings (5MB/s) . . . . . . . . . . . . . . . . . . . . . . . . 7-24
Table 7-19: Target Asynchronous Send Timings (5 MB/s). . . . . . . . . . . . . . . . . . . . . . . . . . . 7-25
Table 7-20: Target Asynchronous Receive Timings (5 MB/s). . . . . . . . . . . . . . . . . . . . . . . . . 7-26
Table 7-21: SCSI-1 Transfers (Single-Ended, 5.0 MB/s) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-27
Table 7-22: SCSI-2 Fast Transfers (10.0 MB/s (8-bit transfers), 40 MHz clock) . . . . . . . . . . 7-28
Table 7-23: SCSI-2 Fast Transfers (10.0 MB/s (8-bit transfers), 50 MHz clock) . . . . . . . . . . 7-28
xiv
SYM53C810A Data Manual
Introduction
What is Covered in This Manual
Chapter 1
Introduction
What is Covered in This
Manual
This manual provides reference information on the
SYM53C810A PCI- SCSI I/O Processor. It is
intended for system designers and programmers
who are using this device to design a SCSI port for
PCI-based personal computers, workstations, or
embedded applications.
This chapter includes general information about
the SYM53C810A and other members of the
SYM53C8XX family of PCI-SCSI I/O Processors.
Chapter 2 describes the main functional areas of
the chip in more detail, including the interfaces to
the SCSI bus. Chapter 3 describes the chip’s connection to the PCI bus, including the PCI commands and configuration registers supported.
Chapter 4 contains the pin diagrams and definitions of each signal. Chapter 5 describes each bit
in the operating registers, organized by address.
Chapter 6 defines all of the SCSI SCRIPTS
instructions that are supported by the
SYM53C810A. Chapter 7 contains the electrical
characteristics and AC timings for the chip. The
appendixes contain a register summary and a
mechanical drawing of the SYM53C810A.
This data manual assumes the user is familiar with
the current and proposed standards for SCSI and
PCI. For additional background information on
these topics, please refer to the list of reference
materials provided in the Preface of this document.
SYM53C810A Data Manual
General Description
The SYM53C810A PCI-SCSI I/O Processor
brings high-performance I/O solutions to host
adapter, workstation, and general computer
designs, making it easy to add SCSI to any PCI
system.
The SYM53C810A is a pin-for-pin replacement
for the SYM53C810 PCI-SCSI I/O processor. It
performs Fast SCSI transfers in single-ended
mode, and improves performance by optimizing
PCI bus utilization. A system diagram showing the
connections of the SYM53C810A in a PCI system
is pictured in Figure 1-1. A block diagram of the
SYM53C810A is pictured in Figure 1-2.
The SYM53C810A integrates a high-performance SCSI core, a PCI bus master DMA core,
and the Symbios Logic SCSI SCRIPTS™ processor to meet the flexibility requirements of SCSI-1,
SCSI-2, and future SCSI standards. It is designed
to implement multi-threaded I/O algorithms with a
minimum of processor intervention, solving the
protocol overhead problems of previous intelligent
and non-intelligent adapter designs.
The SYM53C810A is fully supported by the
Symbios Logic SCSI Device Management System
(SDMS™), a software package that supports the
Advanced SCSI Protocol Interface (ASPI). SDMS
provides BIOS and driver support for hard disk,
tape, removable media products, and CD-ROM
under the major PC operating systems.
The SYM53C810A is packaged in a compact rectangular 100-pin PQFP package to minimize board
space requirements. It operates the SCSI bus at 5
MB/s asynchronously or 10 MB/s synchronously,
and bursts data to the host at full PCI speeds. The
1-1
Introduction
TolerANT Technology
SYM53C810A increases SCRIPTS performance
and reduces PCI bus overhead by allowing instruction prefetches of four or eight dwords.
Software development tools are available to developers who use the SCSI SCRIPTS language to
create customized SCSI software applications. The
SYM53C810A allows easy firmware upgrades and
is supported by advanced SCRIPTS commands.
TolerANT Technology
All Symbios Logic Fast-SCSI devices feature TolerANT® technology, which includes active negation on the SCSI drivers and input signal filtering
on the SCSI receivers. Active negation causes the
SCSI Request, Acknowledge, Data, and Parity signals to be actively driven high rather than passively
pulled up by terminators. Active negation is
enabled by setting bit 7 in the STEST3 register in
the SYM53C8XX family products.
TolerANT receiver technology improves data
integrity in unreliable cabling environments, where
other devices would be subject to data corruption.
TolerANT receivers filter the SCSI bus signals to
eliminate unwanted transitions, without the long
signal delay associated with RC-type input filters.
This improved driver and receiver technology
helps eliminate double clocking of data, the single
biggest reliability issue with SCSI operations.
TolerANT input signal filtering is a built in feature
of all Symbios Logic fast SCSI devices. On the
SYM53C8XX family products, the user may select
a filtering period of 30 or 60 ns, with bit 1 in the
STEST2 register.
The benefits of TolerANT include increased
immunity to noise when the signal is going high,
better performance due to balanced duty cycles,
and improved fast SCSI transfer rates. In addition,
TolerANT SCSI devices do not cause glitches on
the SCSI bus at power up or power down, so other
devices on the bus are also protected from data
corruption. TolerANT is compatible with both the
Alternative One and Alternative Two termination
schemes proposed by the American National Standards Institute.
1-2
SYM53C810A Data Manual
Introduction
SYM53C810A Benefits Summary
SYM53C810A Benefits
Summary
PCI Performance
■
Bursts 2, 4, 8, or 16 dwords across PCI bus
with 80-byte DMA FIFO
■
Pre-fetches up to 8 dwords of SCRIPTS
instructions
SCSI Performance
■
Complies with PCI 2.1 specification
■
■
Supports variable block size and scatter/gather
data transfers
Supports 32-bit word data bursts with variable
burst lengths.
■
Bursts SCRIPTS op code fetches across the
PCI bus
■
Performs zero wait-state bus master data bursts
faster than 110 MB/s (@ 33 MHz)
■
Supports PCI Cache Line Size Register
■
Minimizes SCSI I/O start latency
■
Performs complex bus sequences without
interrupts, including restore data pointers
■
Reduces ISR overhead through a unique
interrupt status reporting method
■
Performs Fast SCSI bus transfers in singleended mode
■
■
■
■
up to 7 MB/s asynchronous
■
10 MB/s synchronous
New Load and Store SCRIPTS instruction
increases performance of data transfers to and
from the chip registers
Support for target to disconnect and later
reselect with no interrupt to the system
processor
Supports execution of multi-threaded I/O
algorithms in SCSI SCRIPTS with fast I/O
context switching
SYM53C810A Data Manual
Integration
■
3.3V/5 V PCI Interface
■
Full 32-bit PCI DMA bus master
■
DMA controller using Memory to Memory
Move instructions
■
High performance SCSI core
■
Integrated SCRIPTS processor
■
Compact 100-pin PQFP packaging
■
Ease of Use Direct PCI-to-SCSI connection
■
Reduced SCSI development effort
■
Support for the Advanced SCSI Protocol
Interface (ASPI) software standard via SDMS
software
■
Compatibility with existing SYM53C7XX and
53C8XX family SCRIPTS
■
Direct connection to PCI, and SCSI singleended bus
■
Development tools and sample SCSI
SCRIPTS
■
Maskable and pollable interrupts
1-3
Introduction
SYM53C810A Benefits Summary
■
■
Three programmable SCSI timers: Select/
Reselect, Handshake-to-Handshake, and
General Purpose. The time-out period is
programmable from 100 µs to greater than 1.6
seconds
SDMS software for complete PC-based
operating system support
■
Support for relative jump
■
New SCSI Selected As ID bits for use when
responding with multiple IDs
Flexibility
■
High level programming interface (SCSI
SCRIPTS)
■
Support for execution of tailored SCSI
sequences from main system RAM
■
Flexible programming interface to tune I/O
performance or to adapt to unique SCSI
devices
■
Flexibility to accommodate changes in the
logical I/O interface definition
■
Low level access to all registers and all SCSI
bus signals
■
Fetch, Master, and Memory Access control
pins
■
Support for indirect fetching of DMA address
and byte counts so that SCRIPTS can be
placed in a PROM
Reliability
■
2 KV ESD protection on SCSI signals
■
Typical 300 mV SCSI bus hysteresis
■
Average operating supply current of 50 mA
■
Protection against bus reflections due to
impedance mismatches
■
Controlled bus assertion times (reduces RFI,
improves reliability, and eases FCC
certification)
■
Latch-up protection greater than 150 mA
■
Voltage feed through protection (minimum
leakage current through SCSI pads)
■
25% of pins power and ground
■
Power and ground isolation of I/O pads and
internal chip logic
■
Symbios Logic TolerANT technology with:
■
■
Active negation of SCSI Data, Parity,
Request, and Acknowledge signals for
improved fast SCSI transfer rates.
Input signal filtering on SCSI receivers
improves data integrity, even in noisy
cabling environments.
Testability
■
Access to all SCSI signals through
programmed I/O
■
Separate SCSI and system clocks
■
SCSI loopback diagnostics
■
Selectable IRQ pin disable bit
■
SCSI bus signal continuity checking
■
Ability to route system clock to SCSI clock
■
Single-step mode operation
■
Test mode (AND tree) to check pin continuity
to the board
1-4
SYM53C810A Data Manual
Introduction
SYM53C810A Benefits Summary
SCSI Connection
Vdd
PCI
Bus
SCSI Term Connection
Vss
SCSI Bus
SYM53C810A
SCLK
Peripheral
40 MHz Oscillator or
Optional
Internal Connection
to PCI Bus Clock
Bulkhead
CPU Baseboard
CPU Box
Figure 1-1: SYM53C810A System Diagram
PCI
PCI Master and Slave Control Block
Data
FIFO
80 Bytes
SCSI
SCRIPTS
Operating
Registers
Config
Registers
SCSI FIFO and SCSI Control Block
TolerANT Technology Drivers and Receivers
Single-Ended SCSI Bus
Figure 1-2: SYM53C810A Chip Block Diagram
SYM53C810A Data Manual
1-5
Introduction
SYM53C810A Benefits Summary
1-6
SYM53C810A Data Manual
Functional Description
SCSI Core
Chapter 2
Functional Description
The SYM53C810A contains three functional
blocks: the SCSI Core, the DMA Core, and the
SCRIPTS Processor. The SYM53C810A is fully
supported by the SCSI Device Management System (SDMS), a complete software package that
supports the Symbios Logic product line of SCSI
processors and controllers.
SCSI Core
The SCSI core supports , synchronous transfer
rates up to 10 MB/s, and asynchronous transfer
rates up to 7 MB/s on an 8-bit SCSI bus. The
SCSI core can be programmed with SCSI
SCRIPTS, making it easy to fine tune the system
for specific mass storage devices or advanced SCSI
requirements.
The SCSI core offers low-level register access or a
high-level control interface. Like first generation
SCSI devices, the SYM53C810A SCSI core can
be accessed as a register-oriented device. The ability to sample and/or assert any signal on the SCSI
bus can be used in error recovery and diagnostic
procedures. In support of loopback diagnostics,
the SCSI core can perform a self-selection and
operate as both an initiator and a target.
The SCSI core is controlled by the integrated
SCRIPTS processor through a high-level logical
interface. Commands controlling the SCSI core
are fetched out of the main host memory or local
memory. These commands instruct the SCSI core
to Select, Reselect, Disconnect, Wait for a Disconnect, Transfer Information, Change Bus Phases
and, in general, implement all aspects of the SCSI
protocol. The SCRIPTS processor is a special
high-speed processor optimized for SCSI protocol.
SYM53C810A Data Manual
DMA Core
The DMA core is a bus master DMA device that
attaches directly to the industry standard PCI Bus.
The DMA core is tightly coupled to the SCSI core
through the SCRIPTS processor, which supports
uninterrupted scatter/gather memory operations.
The SYM53C810A supports 32-bit memory and
automatically supports misaligned DMA transfers.
An 80-byte FIFO allows two, four, eight, or sixteen dword bursts across the PCI bus interface to
run efficiently without throttling the bus during
PCI bus latency.
SCRIPTS Processor
The SCSI SCRIPTS processor allows both DMA
and SCSI commands to be fetched from host
memory. Algorithms written in SCSI SCRIPTS
control the actions of the SCSI and DMA cores
and are executed from 32-bit system RAM. The
SCRIPTS processor executes complex SCSI bus
sequences independently of the host CPU.
The SCRIPTS processor can begin a SCSI I/O
operation in approximately 500 ns. This compares
with 2-8 ms required for traditional intelligent host
adapters. Algorithms may be designed to tune
SCSI bus performance, to adjust to new bus device
types (such as scanners, communication gateways,
etc.), or to incorporate changes in the SCSI-2 or
SCSI-3 logical bus definitions without sacrificing
I/O performance. SCSI SCRIPTS are hardware
independent, so they can be used interchangeably
on any host or CPU system bus.
A complete set of development tools is available for
writing custom drivers with SCSI SCRIPTS. For
more information on SCSI SCRIPTS instructions
supported by the SYM53C810A, see Chapter 6.
2-1
Functional Description
SDMS: The Total SCSI Solution
SDMS: The Total SCSI
Solution
For users who do not need to develop custom drivers, Symbios Logic provides a total SCSI solution
in PC environments with the SCSI Device Management System (SDMS). SDMS provides BIOS
and driver support for hard disk, tape, and removable media peripherals for the major PC-based
operating systems.
SDMS includes a SCSI BIOS to manage all SCSI
functions related to the device. It also provides a
series of SCSI device drivers that support most
major operating systems. SDMS supports a multithreaded I/O application programming interface
(API) for user-developed SCSI applications.
SDMS supports both the ASPI and CAM SCSI
software specifications.
Prefetching SCRIPTS
Instructions
When enabled (by setting the Prefetch Enable bit
in the DCNTL register), the prefetch logic in the
SYM53C810A fetches 4 or 8 dwords of instructions. The prefetch logic automatically determines
the maximum burst size that it can perform, based
on the burst length as determined by the values in
the DMODE register and the PCI Cache Line Size
register (if cache mode is enabled). If the unit cannot perform bursts of at least four dwords, it will
disable itself.
The SYM53C810A may flush the contents of the
prefetch unit under certain conditions, listed
below, to ensure that the chip always operates from
the most current version of the software. When one
of these conditions apply, the contents of the
prefetch unit are flushed automatically.
1. On every Memory Move instruction. The
Memory Move (MMOV) instruction is often
used to place modified code directly into
memory. To make sure that the chip executes
2-2
all recent modifications, the prefetch unit
flushes its contents and loads the modified
code every time a MMOV instruction is issued.
To avoid inadvertently flushing the prefetch
unit contents, use the No Flush Memory to
Memory Move (NFMMOV) instruction for all
MMOV operations that do not modify code
within the next 4 to 8 dwords. For more
information on this instruction, refer to
Chapter 6.
2. On every Store instruction. The Store
instruction may also be used to place modified
code directly into memory. To avoid
inadvertently flushing the prefetch unit
contents, use the No Flush option for all Store
operations that do not modify code within the
next 8 dwords.
3. On every write to the DSP register.
4. On all Transfer Control instructions when the
transfer conditions are met. This is necessary
because the next instruction to be executed is
not the sequential next instruction in the
prefetch unit.
5. When the Pre-Fetch Flush bit (DCNTL bit 5)
is set. The unit flushes whenever this bit is set.
The bit is self-clearing.
Op Code Fetch
Burst Capability
Setting the Burst Op Code Fetch Enable bit in the
DMODE register (38h) causes the SYM53C810A
to burst in the first two dwords of all instruction
fetches. If the instruction is a memory-to-memory
move, the third dword will be accessed in a separate ownership. If the instruction is an indirect
type, the additional dword will be accessed in a
subsequent bus ownership. If the instruction is a
table indirect Block Move, the SYM53C810A will
use two accesses to obtain the four dwords
required, in two bursts of two dwords each.
Note: this feature can only be used if SCRIPTS
pre-fetching is disabled.
SYM53C810A Data Manual
Functional Description
PCI Cache Mode
PCI Cache Mode
Parity Options
The SYM53C810A supports the PCI specification
for an 8-bit Cache Line Size register located in
PCI configuration space. The Cache Line Size register provides the ability to sense and react to nonaligned addresses corresponding to cache line
boundaries. In conjunction with the Cache Line
Size register, the PCI commands Read Line, Read
Multiple, and Write and Invalidate are each software enabled or disabled to allow the user full flexibility in using these commands. For more
information on PCI cache mode operations, refer
to Chapter 3.
The SYM53C810A implements a flexible parity
scheme that allows control of the parity sense,
allows parity checking to be turned on or off, and
has the ability to deliberately send a byte with bad
parity over the SCSI bus to test parity error recovery procedures. Table 2-1 defines the bits that are
involved in parity control and observation.
Table 2-2 describes the parity control function of
the Enable Parity Checking and Assert SCSI Even
Parity bits in the SCNTL0 register. Table 2-3
describes the options available when a parity error
occurs.
Load/Store Instructions
The SYM53C810A supports the Load/Store
instruction type, which simplifies the movement of
data between memory and the internal chip registers. It also enables the SYM53C810A to transfer
bytes to addresses relative to the DSA register. For
more information on the Load and Store instructions, refer to Chapter 6.
3.3 Volt/5 Volt PCI Interface
The SYM53C810A can attach directly to a 3.3.
Volt or a 5 Volt PCI interface, due to separate VDD
pins for the PCI bus drivers. This allows the
devices to be used on the universal board recommended by the PCI Special Interest Group.
Loopback Mode
The SYM53C810A loopback mode allows testing
of both initiator and target functions and, in effect,
lets the chip communicate with itself. When the
Loopback Enable bit is set in the STEST1 register,
the SYM53C810A allows control of all SCSI signals, whether it is operating in initiator or target
mode. For more information on this mode of operation, refer to the SYM53C8XX Family Programming Guide.
SYM53C810A Data Manual
2-3
Functional Description
Parity Options
Table 2-1: Bits Used for Parity Control and Observation
BIt Name
Location
Description
Assert SATN/ on
Parity Errors
SCNTL0, Bit 1
Causes the SYM53C810A to automatically assert SATN/ when
it detects a parity error while operating on the SCSI bus as an
initiator.
Enable Parity
Checking
SCNTL0, Bit 3
Enables the SYM53C810A to check for parity errors on the
SCSI bus. The SYM53C810A checks for odd parity.
Assert Even SCSI
Parity
SCNTL1, Bit 2
Determines the SCSI parity sense generated by the
SYM53C810A to the SCSI bus.
Disable Halt on
SATN/ or a Parity
Error (Target Mode
Only)
SCNTL1, Bit 5
Causes the SYM53C810A not to halt operations when a SCSI
parity error is detected in target mode.
Enable Parity Error
Interrupt
SIEN0, Bit 0
Determines whether the SYM53C810A will generate an interrupt when it detects a SCSI parity error.
Parity Error
SIST0, Bit 0
This status bit is set whenever the SYM53C810A has detected a
parity error on the SCSI bus.
Status of SCSI
Parity Signal
SSTAT0, Bit 0
This status bit represents the live SCSI Parity Signal (SDP).
Latched SCSI Parity
SSTAT1, Bit 3
This bit reflects the SCSI odd parity signal corresponding to the
data latched into the SIDL register
Master Parity Error
Enable
CTEST4, Bit 3
Enables PCI parity checking during master data phases.
Master Data Parity
Error
DSTAT, Bit 6
Set when the SYM53C810A as a PCI master detects that a target device has signalled a parity error during a data phase.
Master Data Parity
Error Interrupt
Enable
DIEN, Bit 6
By clearing this bit, a Master Data Parity Error will not cause
IRQ/ to be asserted, but the status bit will be set in the DSTAT
register.
2-4
SYM53C810A Data Manual
Functional Description
Parity Options
Table 2-2: SCSI Parity Control
EPC
AESP
Description
0
0
Will not check for parity errors. Parity is generated when sending SCSI data. Asserts odd parity when sending SCSI data.
0
1
Will not check for parity errors. Parity is generated when sending SCSI data. Asserts even parity when sending SCSI data.
1
0
Checks for odd parity on SCSI data received. Parity is generated
when sending SCSI data. Asserts odd parity when sending SCSI
data.
1
1
Checks for odd parity on SCSI data received. Parity is generated
when sending SCSI data. Asserts even parity when sending
SCSI data.
Key:
EPC = Enable Parity Checking (bit 3 SCNTL0)
ASEP = Assert SCSI Even Parity (bit 2 SCNTL1)
Table 2-3: SCSI Parity Errors and Interrupts
DHP
PAR
Description
0
0
Will halt when a parity error occurs in target or initiator mode
and will NOT generate an interrupt.
0
1
Will halt when a parity error occurs in target mode and will generate an interrupt in target or initiator mode.
1
0
Will not halt in target mode when a parity error occurs until the
end of the transfer. An interrupt will not be generated.
1
1
Will not halt in target mode when a parity error occurs until the
end of the transfer. An interrupt will be generated.
Key: DHP = Disable Halt on SATN/ or Parity Error (bit 5 SCNTL1) PAR = Parity Error (bit 0 SIEN0)
This table only applies when the Enable Parity Checking bit is set.
SYM53C810A Data Manual
2-5
Functional Description
DMA FIFO
DMA FIFO
The DMA FIFO is divided into four sections, each one byte wide and 20 transfers deep. The DMA FIFO
is illustrated in Figure 2-1.
32 Bits Wide
20
Bytes
Deep
8 Bits
Byte Lane 3
8 Bits
Byte Lane 2
8 Bits
Byte Lane 1
8 Bits
Byte Lane 0
Figure 2-1: DMA FIFO Sections
2-6
SYM53C810A Data Manual
Functional Description
DMA FIFO
Data Paths
The data path through the SYM53C810A is
dependent on whether data is being moved into or
out of the chip, and whether SCSI data is being
transferred asynchronously or synchronously.
Figure 2-2 shows how data is moved to/from the
SCSI bus in each of the different modes.
The following steps determine if any bytes remain
in the data path when the chip halts an operation:
Asynchronous SCSI Send
1. Look at the DFIFO and DBC registers and
calculate if there are bytes left in the DMA
FIFO. To make this calculation, subtract the
seven least significant bits of the DBC register
from the 7-bit value of the DFIFO register.
AND the result with 7Fh for a byte count
between zero and 80.
2. Read bit 5 in the SSTAT0 register to
determine if any bytes are left in the SODL
register. If bit 5 is set in SSTAT0, then the
SODL register is full.
Asynchronous SCSI Receive
1. Look at the DFIFO and DBC registers and
calculate if there are bytes left in the DMA
FIFO. To make this calculation, subtract the
seven least significant bits of the DBC register
from the 7-bit value of the DFIFO register.
AND the result with 7Fh for a byte count
between 0 and 80.
2. Read bit 7 in the SSTAT0 register to
determine if any bytes are left in the SIDL
register. If bit 7 is set in SSTAT0, then the
SIDL register is full.
Synchronous SCSI Receive
1. Subtract the seven least significant bits of the
DBC register from the 7-bit value of the
DFIFO register. AND the result with 7Fh for a
byte count between 0 and 80.
2. Read the SSTAT1 register and examine bits 74, the binary representation of the number of
valid bytes in the SCSI FIFO, to determine if
any bytes are left in the SCSI FIFO.
Synchronous SCSI Send
1. Look at the DFIFO and DBC registers and
calculate if there are bytes left in the DMA
FIFO. To make this calculation, subtract the
seven least significant bits of the DBC register
from the 7-bit value of the DFIFO register.
AND the result with 7Fh for a byte count
between zero and 80.
2. Read bit 5 in the SSTAT0 register to
determine if any bytes are left in the SODL
register. If bit 5 is set in SSTAT0, then the
SODL register is full.
3. Read bit 6 in the SSTAT0 register to
determine if any bytes are left in the SODR
register. If bit 6 is set in SSTAT0, then the
SODR register is full.
SYM53C810A Data Manual
2-7
Functional Description
DMA FIFO
PCI Interface
PCI Interface
PCI Interface
PCI Interface
DMA FIFO
(4 bytes x 20)
DMA FIFO
(4 bytes x 20)
DMA FIFO
(4 bytes x 20)
DMA FIFO
(4 bytes x 20)
SODL Register
SIDL Register
SODL Register
SCSI Interface
SCSI Interface
SODR Register
SCSI FIFO
SCSI Interface
SCSI Interface
Asynchronous
SCSI Send
Asynchronous
SCSI Receive
Synchronous
SCSI Send
Synchronous
SCSI Receive
Figure 2-2: SYM53C810A Host Interface Data Paths
2-8
SYM53C810A Data Manual
Functional Description
SCSI Bus Interface
SCSI Bus Interface
(Re)Select During
(Re)Selection
The SYM53C810A supports single-ended operation only. All SCSI signals are active low. The
SYM53C810A contains the single-ended output
drivers and can be connected directly to the SCSI
bus. Each output is isolated from the power supply
to ensure that a powered-down SYM53C810A has
no effect on an active SCSI bus (CMOS “voltage
feed-through” phenomena). TolerANT technology provides signal filtering at the inputs of SREQ/
and SACK/ to increase immunity to signal reflections.
In multi-threaded SCSI I/O environments, it is not
uncommon to be selected or reselected while trying to perform selection/reselection. This situation
may occur when a SCSI controller (operating in
initiator mode) tries to select a target and is reselected by another. The Select SCRIPTS instruction has an alternate address to which the
SCRIPTS will jump when this situation occurs.
The analogous situation for target devices is being
selected while trying to perform a reselection.
Terminator
Networks
The terminator networks provide the biasing
needed to pull signals to an inactive voltage level,
and to match the impedance seen at the end of the
cable with the characteristic impedance of the
cable. Terminators must be installed at the extreme
ends of the SCSI chain, and only at the ends; no
system should ever have more or less than two terminators installed and active. SCSI host adapters
should provide a means of accommodating terminators. The terminators should be socketed, so
that if not needed they may be removed, or there
should be a means of disabling them with software.
Once a change in operating mode occurs, the initiator SCRIPTS should start with a Set Initiator
instruction or the target SCRIPTS should start
with a Set Target instruction. The Selection and
Reselection Enable bits (SCID bits 5 and 6,
respectively) should both be set so that the
SYM53C810A may respond as an initiator or as a
target. If only selection is enabled, the
SYM53C810A cannot be reselected as an initiator.
There are also status and interrupt bits in the
SIST0 and SIEN0 registers, respectively, indicating that the SYM53C810A has been selected (bit
5) or reselected (bit 4).
Single-ended cables can use a 220 Ω pull-up to the
terminator power supply (Term-Power) line and a
330 Ω pull-down to Ground. Symbios recommends active or regulated termination (also known
as Alt-2 or Alternative Two termination) to maximize the high performance of the SYM53C810A.
Figure 2-3 shows a Unitrode active terminator for
regulated termination. For additional information,
refer to the SCSI-2 Specification. TolerANT active
negation can be used with any ANSI-approved termination network.
SYM53C810A Data Manual
2-9
Functional Description
SCSI Bus Interface
UC5601QP
2
2.85V
C1
REG_OUT
C2
19
DISCONNECT
20
21
22
23
24
25
26
27
28
SD0 (J1.2)
SD1 (J1.4)
SD2 (J1.6)
SD3 (J1.8)
SD4 (J1.10)
SD5 (J1.12)
SD6 (J1.14)
SD7 (J1.16)
SD8 (J1.18)
3
TERML10
4
TERML11
5
TERML12
6
TERML13
7
TERML14
8
TERML15
9
TERML16
10
TERML17
11
TERML18
ATN (J1.32)
BSY (J1.36)
ACK (J1.38)
RST (J1.40)
MSG (J1.42)
SEL (J1.44)
C/D (J1.46)
REQ (J1.48)
I/O (J1.50)
TERML1
TERML2
TERML3
TERML4
TERML5
TERML6
TERML7
TERML8
TERML9
Key
C1
10 µF SMT
C2
0.1 µF SMT
J1
68-pin, high density “P” connector
Figure 2-3: Active or Regulated Termination
2-10
SYM53C810A Data Manual
Functional Description
Synchronous Operation
Synchronous Operation
The SYM53C810A can transfer synchronous
SCSI data in both initiator and target modes. The
SXFER register controls both the synchronous offset and the transfer period. It may be loaded by the
CPU before SCRIPTS execution begins, from
within SCRIPTS via a Table Indirect I/O instruction, or with a Read-Modify-Write instruction.
The SYM53C810A can receive data from the
SCSI bus at a synchronous transfer period as short
as 80 ns or 160 ns (with a 50 MHz clock), regardless of the transfer period used to send data. The
SYM53C810A can receive data at one-fourth of
the divided SCLK frequency. Depending on the
SCLK frequency, the negotiated transfer period,
and the synchronous clock divider, the
SYM53C810A can send synchronous data at
intervals as short as 100 ns for fast SCSI-2 and
200 ns for SCSI-1.
Determining the
Data Transfer Rate
Synchronous data transfer rates are controlled by
bits in two different registers of the
SYM53C810A. A brief description of the bits is
provided below. Figure 2-4 illustrates the clock
division factors used in each register, and the role
of the register bits in determining the transfer rate.
For synchronous send, the output of the SCF
divider is divided by the transfer period (XFERP)
bits in the SCSI Transfer (SXFER) register. For
valid combinations of the SCF and the XFERP,
see Table 5-4 and Table 5-5, under the description
of the XFERP bits 7-5 in the SXFER register.
SCNTL3 Register, bits 2–0 (CCF2–0)
The CCF2-0 bits select the frequency of the
SCLK for asynchronous SCSI operations. To meet
the SCSI timings as defined by the ANSI specification, these bits need to be set properly.
SXFER Register, bits 7–5 (TP2–0)
The TP2-0 divider (XFERP) bits determine the
SCSI synchronous send rate in either initiator or
target mode. This value further divides the output
from the SCF divider.
Achieving Optimal SCSI Send Rates
To achieve optimal synchronous SCSI send timings, the SCF divisor value should be set high, to
divide the clock as much as possible before presenting the clock to the TP divider bits in the
SXFER register. The TP2-0 divider value should
be as low as possible. For example, with 40 MHz
clock to achieve a 5 MB/s send rate, the SCF bits
can be set to divide by 1 and the TP bits to divide
by 8; or the SCF bits can be set to divide by 2 and
the TP bits set to divide by 4. Use the second
option to achieve optimal SCSI timings.
SCNTL3 Register, bits 6–4 (SCF2–0)
The SCF2-0 bits select the factor by which the frequency of SCLK is divided before being presented
to the synchronous SCSI control logic. The output
from this divider controls the rate at which data
can be received; this rate must not exceed 50
MHz. The receive rate is 1/4 of the divider output.
For example, if SCLK is 40MHz and the SCF
value is set to divide by one, then the maximum
rate at which data can be received is 10 MB/s (40/
(1*4) = 10).
SYM53C810A Data Manual
2-11
Functional Description
Synchronous Operation
SCF2
SCF1
SCF0
SCF
Divisor
0
0
0
1
0
0
1
1
0
0
1
0
1
0
0
1
1.5
2
3
3
SCF
Divider
SCLK
This pointmust not
exceed 50
MHz
CCF
Divider
CCF2
CCF1
CCF0
SCSI Clock
(MHz)
0
0
0
50.1-66.00
0
0
1
16.67-25.00
0
1
0
25.01-37.50
0
1
1
37.51-50.00
1
0
0
50.01-66.00
TP2
TP1
TP0
XFERP
Divisor
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
4
5
6
7
8
9
10
11
Divide by 4
Receive
Clock
Synchronous
Divider
Send Clock
(to SCSI bus)
Asynchronous
SCSI Logic
Example:
SCLK= 40 MHz, SCF=1(/1), XFERP=0(/4),
CCF=3(37.51-50.00 MHz)
Synchronous send rate=(SCLK/SCF)/XFERP=
(40/1)/4= 10 MB/s
Synchronous receive rate=(SCLK/SCF) / 4=(40/1)/4= 10 MB/s
Figure 2-4: Determining the Synchronous Transfer Rate
2-12
SYM53C810A Data Manual
Functional Description
Interrupt Handling
Interrupt Handling
The SCRIPTS processor in the SYM53C810A
performs most functions independently of the host
microprocessor. However, certain interrupt situations must be handled by the external microprocessor. This section explains all aspects of
interrupts as they apply to the SYM53C810A.
ISTAT register is set, then a SCSI-type interrupt
has occurred and the SIST0 and SIST1 registers
should be read. If the DIP bit in the ISTAT register is set, then a DMA-type interrupt has occurred
and the DSTAT register should be read. SCSItype and DMA-type interrupts may occur simultaneously, so in some cases both SIP and DIP may
be set.
SIST0 and SIST1
Polling and
Hardware Interrupts
The external microprocessor is informed of an
interrupt condition by polling or hardware interrupts. Polling means that the microprocessor must
continually loop and read a register until it detects
a bit set that indicates an interrupt. This method is
the fastest, but it wastes CPU time that could be
used for other system tasks. The preferred method
of detecting interrupts in most systems is hardware
interrupts. In this case, the SYM53C810A will
assert the Interrupt Request (IRQ/) line that will
interrupt the microprocessor, causing the microprocessor to execute an interrupt service routine. A
hybrid approach would use hardware interrupts for
long waits, and use polling for short waits.
Registers
The registers in the SYM53C810A that are used
for detecting or defining interrupts are the ISTAT,
SIST0, SIST1, DSTAT, SIEN0, SIEN1,
DCNTL, and DIEN.
ISTAT
The ISTAT is the only register that can be
accessed as a slave during SCRIPTS operation,
therefore it is the register that is polled when
polled interrupts are used. It is also the first register that should be read when the IRQ/ pin has been
asserted in association with a hardware interrupt.
The INTF (Interrupt on the Fly) bit should be the
first interrupt serviced. It must be written to one to
be cleared. This interrupt must be cleared before
servicing any other interrupts. If the SIP bit in the
SYM53C810A Data Manual
The SIST0 and SIST1 registers contain the SCSItype interrupt bits. Reading these registers will
determine which condition or conditions caused
the SCSI-type interrupt, and will clear that SCSI
interrupt condition. If the SYM53C810A is receiving data from the SCSI bus and a fatal interrupt
condition occurs, the SYM53C810A will attempt
to send the contents of the DMA FIFO to memory
before generating the interrupt. If the
SYM53C810A is sending data to the SCSI bus
and a fatal SCSI interrupt condition occurs, data
could be left in the DMA FIFO. Because of this
the DMA FIFO Empty (DFE) bit in DSTAT
should be checked. If this bit is clear, set the CLF
(Clear DMA FIFO) and CSF (Clear SCSI FIFO)
bits before continuing. The CLF bit is bit 2 in
CTEST3. The CSF bit is bit 1 in STEST3.
DSTAT
The DSTAT register contains the DMA-type
interrupt bits. Reading this register will determine
which condition or conditions caused the DMAtype interrupt, and will clear that DMA interrupt
condition. The DFE bit, bit 7 in DSTAT, is purely
a status bit; it will not generate an interrupt under
any circumstances and will not be cleared when
read. DMA interrupts will flush neither the DMA
nor SCSI FIFOs before generating the interrupt,
so the DFE bit in the DSTAT register should be
checked after any DMA interrupt. If the DFE bit
is clear, then the FIFOs must be cleared by setting
the CLF (Clear DMA FIFO) and CSF (Clear
SCSI FIFO) bits, or flushed by setting the FLF
(Flush DMA FIFO) bit.
2-13
Functional Description
Interrupt Handling
SIEN0 and SIEN1
The SIEN0 and SIEN1 registers are the interrupt
enable registers for the SCSI interrupts in SIST0
and SIST1.
DIEN
The DIEN register is the interrupt enable register
for DMA interrupts in DSTAT.
DCNTL
When bit 1 in this register is set, the IRQ/ pin will
not be asserted when an interrupt condition
occurs. The interrupt is not lost or ignored, but
merely masked at the pin. Clearing this bit when
an interrupt is pending will immediately cause the
IRQ/ pin to assert. As with any register other than
ISTAT, this register cannot be accessed except by a
SCRIPTS instruction during SCRIPTS execution.
Fatal vs. Non-Fatal
Interrupts
A fatal interrupt, as the name implies, always
causes SCRIPTS to stop running. All non-fatal
interrupts become fatal when they are enabled by
setting the appropriate interrupt enable bit. For
more information on interrupt masking, see the
discussion on masking later in this section. All
DMA interrupts (indicated by the DIP bit in
ISTAT and one or more bits in DSTAT being set)
are fatal.
Some SCSI interrupts (indicated by the SIP bit in
the ISTAT and one or more bits in SIST0 or
SIST1 being set) are non-fatal. When the
SYM53C810A is operating in initiator role, only
the Function Complete (CMP), Selected (SEL),
Reselected (RSL), General Purpose Timer Expired
(GEN), and Handshake to Handshake Timer
Expired (HTH) interrupts are non-fatal. When
operating in target role CMP, SEL, RSL, Target
mode: SATN/ active (M/A), GEN, and HTH are
non-fatal. Refer to the description for the Disable
Halt on a Parity Error or SATN/ active (Target
Mode Only) (DHP) bit in the SCNTL1 register to
2-14
configure the chip’s behavior when the SATN/
interrupt is enabled during target role operation.
The Interrupt on the Fly interrupt is also nonfatal, since SCRIPTS can continue when it occurs.
The reason for non-fatal interrupts is to prevent
SCRIPTS from stopping when an interrupt occurs
that does not require service from the CPU. This
prevents an interrupt when arbitration is complete
(CMP set), when the SYM53C810A has been
selected or reselected (SEL or RSL set), when the
initiator has asserted ATN (target mode: SATN/
active), or when the General Purpose or Handshake to Handshake timers expire. These interrupts do not require CPU intervention during
high-level SCRIPTS operation.
Masking
Masking an interrupt means disabling or ignoring
that interrupt. Interrupts can be masked by clearing bits in the SIEN0 and SIEN1 (for SCSI interrupts) registers or the DIEN (for DMA interrupts)
register. How the chip will respond to masked
interrupts depends on: whether polling or hardware interrupts are being used; whether the interrupt is fatal or non-fatal; and whether the chip is
operating in initiator or target role.
If a non-fatal interrupt is masked and that condition occurs, SCRIPTS will not stop, the appropriate bit in the SIST0 or SIST1 will still be set, the
SIP bit in the ISTAT will not be set, and the IRQ/
pin will not be asserted. See the section on nonfatal vs. fatal interrupts for a list of the non-fatal
interrupts.
If a fatal interrupt is masked and that condition
occurs, then SCRIPTS will still stop, the appropriate bit in the DSTAT, SIST0, or SIST1 register
will be set, and the SIP or DIP bits in the ISTAT
will be set, but the IRQ/ pin will not be asserted.
When the chip is initialized, enable all fatal interrupts if you are using hardware interrupts. If a fatal
interrupt is disabled and that interrupt condition
SYM53C810A Data Manual
Functional Description
Interrupt Handling
occurs, SCRIPTS will halt and the system will
never know it unless it times out and checks the
ISTAT after a certain period of inactivity.
If you are polling the ISTAT instead of using hardware interrupts, then masking a fatal interrupt will
make no difference since the SIP and DIP bits in
the ISTAT inform the system of interrupts, not the
IRQ/ pin.
Masking an interrupt after IRQ/ is asserted will not
cause IRQ/ to be deasserted.
Stacked Interrupts
The SYM53C810A stacks interrupts if they occur
one after another. If the SIP or DIP bits in the
ISTAT register are set (first level), then there is
already at least one pending interrupt, and any
future interrupts will be stacked in extra registers
behind the SIST0, SIST1, and DSTAT registers
(second level). When two interrupts have occurred
and the two levels of the stack are full, any further
interrupts will set additional bits in the extra registers behind SIST0, SIST1, and DSTAT. When the
first level of interrupts are cleared, all the interrupts that came in afterward will move into the
SIST0, SIST1, and DSTAT. After the first interrupt is cleared by reading the appropriate register,
the IRQ/ pin will be deasserted for a minimum of
three CLKs; the stacked interrupt(s) will move
into the SIST0, SIST1, or DSTAT; and the IRQ/
pin will be asserted once again.
Since a masked non-fatal interrupt will not set the
SIP or DIP bits, interrupt stacking will not occur.
A masked, non-fatal interrupt will still post the
interrupt in SIST0, but will not assert the IRQ/
pin. Since no interrupt is generated, future interrupts will move right into the SIST0 or SIST1
instead of being stacked behind another interrupt.
When another condition occurs that generates an
interrupt, the bit corresponding to the earlier
masked non-fatal interrupt will still be set.
A related situation to interrupt stacking is when
two interrupts occur simultaneously. Since stacking does not occur until the SIP or DIP bits are
SYM53C810A Data Manual
set, there is a small timing window in which multiple interrupts can occur but will not be stacked.
These could be multiple SCSI interrupts (SIP set),
multiple DMA interrupts (DIP set), or multiple
SCSI and multiple DMA interrupts (both SIP and
DIP set).
As previously mentioned, DMA interrupts will not
attempt to flush the FIFOs before generating the
interrupt. It is important to set the Clear DMA
FIFO (CLF) and Clear SCSI FIFO (CSF) bits if a
DMA interrupt occurs and the DMA FIFO Empty
(DFE) bit is not set. This is because any future
SCSI interrupts will not be posted until the DMA
FIFO is clear of data. These ‘locked out’ SCSI
interrupts will be posted as soon as the DMA
FIFO is empty.
Halting in an
Orderly Fashion
When an interrupt occurs, the SYM53C810A will
attempt to halt in an orderly fashion.
■
If the interrupt occurs in the middle of an
instruction fetch, the fetch will be completed,
except in the case of a Bus Fault. Execution
will not begin, but the DSP will point to the
next instruction since it is updated when the
current instruction is fetched.
■
If the DMA direction is a write to memory and
a SCSI interrupt occurs, the SYM53C810A
will attempt to flush the DMA FIFO to
memory before halting. Under any other
circumstances only the current cycle will be
completed before halting, so the DFE bit in
DSTAT should be checked to see if any data
remains in the DMA FIFO.
■
SCSI SREQ/SACK handshakes that have
begun will be completed before halting.
■
The SYM53C810A will attempt to clean up
any outstanding synchronous offset before
halting.
■
In the case of Transfer Control Instructions,
once instruction execution begins it will
continue to completion before halting.
2-15
Functional Description
Interrupt Handling
■
If the instruction is a JUMP/CALL WHEN/IF
<phase>, the DSP will be updated to the
transfer address before halting.
■
All other instructions may halt before
completion.
Sample Interrupt
Service Routine
6. When using polled interrupts, go back to step
1 before leaving the interrupt service routine,
in case any stacked interrupts moved in when
the first interrupt was cleared. When using
hardware interrupts, the IRQ/ pin will be
asserted again if there are any stacked
interrupts. This should cause the system to reenter the interrupt service routine.
The following is a sample of an interrupt service
routine for the SYM53C810A. It can be repeated
if polling is used, or should be called when the
IRQ/ pin is asserted if hardware interrupts are
used.
1. Read ISTAT.
2. If the INTF bit is set, it must be written to a
one to clear this status.
3. If only the SIP bit is set, read SIST0 and
SIST1 to clear the SCSI interrupt condition
and get the SCSI interrupt status. The bits in
the SIST0 and SIST1 tell which SCSI
interrupt(s) occurred and determine what
action is required to service the interrupt(s).
4. If only the DIP bit is set, read the DSTAT to
clear the interrupt condition and get the DMA
interrupt status. The bits in the DSTAT will
tell which DMA interrupt(s) occurred and
determine what action is required to service
the interrupt(s).
5. If both the SIP and DIP bits are set, read
SIST0, SIST1, and DSTAT to clear the SCSI
and DMA interrupt condition and get the
interrupt status. If using 8-bit reads of the
SIST0, SIST1, and DSTAT registers to clear
interrupts, insert a 12 CLK delay between the
consecutive reads to ensure that the interrupts
clear properly. Both the SCSI and DMA
interrupt conditions should be handled before
leaving the ISR. It is recommended that the
DMA interrupt be serviced before the SCSI
interrupt, because a serious DMA interrupt
condition could influence how the SCSI
interrupt is acted upon.
2-16
SYM53C810A Data Manual
PCI Functional Description
PCI Addressing
Chapter 3
PCI Functional Description
PCI Addressing
There are three types of PCI-defined address
space:
■
Configuration space
■
Memory space
■
I/O space
Configuration space is a contiguous 256-byte set of
addresses dedicated to each “slot” or “stub” on the
bus. Decoding C_BE/(3-0) determines if a PCI
cycle is intended to access configuration register
space. The IDSEL bus signal is a chip select that
allows access to the configuration register space
only. Any attempt to access configuration space
will be ignored unless IDSEL is asserted. The eight
lower order address lines and byte enables are used
to select a specific 8-bit register. The host processor uses this configuration space to initialize the
SYM53C810A. Figure 3-1 contains a list of the
PCI configuration registers supported in the
SYM53C810A.
The lower 128 bytes of the SYM53C810A configuration space hold system parameters while the
upper 128 bytes map into the SYM53C810A
operating registers. For all PCI cycles except configuration cycles, the SYM53C810A registers are
located on the 256-byte block boundary defined by
the base address assigned through the configured
register. The SYM53C810A operating registers are
available in both the upper and lower 128-byte
portions of the 256-byte space selected.
At initialization time, each PCI device is assigned a
base address (in the case of the SYM53C810A, the
upper 24 bits of the address are used) for memory
accesses and I/O accesses. On every access, the
SYM53C810A Data Manual
SYM53C810A compares its assigned base
addresses with the value on the Address/Data bus
during the PCI address phase. If there is a match
of the upper 24 bits, the access is for the
SYM53C810A and the low order eight bits define
the register to be accessed. A decode of C_BE/ (30) determines which registers and what type of
access is to be performed.
PCI defines memory space as a contiguous 32-bit
memory address that is shared by all system
resources, including the SYM53C810A. Base
Address Register One determines which 256-byte
memory area this device will occupy.
PCI defines I/O space as a contiguous 32-bit I/O
address that is shared by all system resources,
including the SYM53C810A. Base Address Register Zero determines which 256-byte I/O area this
device will occupy.
PCI Bus Commands and
Functions Supported
Bus commands indicate to the target the type of
transaction the master is requesting. Bus commands are encoded on the C_BE/(3-0) lines during the address phase. PCI bus command
encoding and types appear in Table 3-1.
The I/O Read command is used to read data from
an agent mapped in I/O address space. All 32
address bits are decoded.
The I/O Write command is used to write data to an
agent when mapped in I/O address space. All 32
address bits are decoded.
3-1
PCI Functional Description
PCI Cache Mode
The Memory Read, Memory Read Multiple, and
Memory Read Line commands are used to read
data from an agent mapped in memory address
space. All 32 address bits are decoded.
The Memory Write and Memory Write and Invalidate commands are used to write data to an agent
when mapped in memory address space. All 32
address bits are decoded.
PCI Cache Mode
The SYM53C810A supports the PCI specification
for an 8-bit Cache Line Size register located in
PCI configuration space. The Cache Line Size register provides the ability to sense and react to nonaligned addresses corresponding to cache line
boundaries. In conjunction with the Cache Line
Size register, the PCI commands Read Line, Read
Multiple, and Write and Invalidate are each software enabled or disabled to allow the user full flexibility in using these commands.
Support for PCI
Cache Line Size Register
The SYM3C810A supports the PCI specification
for an 8-bit Cache Line Size register in PCI configuration space; it can sense and react to non-aligned
addresses corresponding to cache line boundaries.
Selection of Cache
Line Size
The cache logic will select a cache line size based
on the values for the burst size in the DMODE
register and the PCI Cache Line Size register.
3-2
Note: the SYM53C810A will not automatically
use the value in the PCI Cache Line Size
register as the cache line size value. The
chip scales the value of the Cache Line Size
register down to the nearest binary burst
size allowed by the chip (2, 4, 8 or 16),
compares this value to the DMODE burst
size, then selects the smallest as the value
for the cache line size. The SYM53C810A
will use this value for all burst data
transfers.
Alignment
The SYM53C810A uses the calculated burst size
value to monitor the current address for alignment
to the cache line size. When it is not aligned the
chip disables bursting, allowing only single dword
transfers until a cache line boundary is reached.
When the chip is aligned, bursting is re-enabled it
will burst in increments specified by the Cache
Line Size register as explained above. If the Cache
Line Size register is not set (default = 00h), the
DMODE burst size is automatically used as the
cache line size.
MMOV
Misalignment
The SYM53C810A will not operate in a cache
alignment mode when a MMOV instruction is
issued and the read and write addresses are different distances from the nearest cache line boundary. For example, if the read address is 0x21F and
the write address is 0x42F, and the cache line size
is eight (8), the addresses are byte aligned, but they
are not the same distance from the nearest cache
boundary. The read address is 1 byte from the
cache boundary 0x220 and the write address is 17
bytes from the cache boundary 0x440. In this situation, the chip will not align to cache boundaries
and will operate as an SYM53C810.
SYM53C810A Data Manual
PCI Functional Description
PCI Cache Mode
Memory Write
and Invalidate Command
The Memory Write and Invalidate command is
identical to the Memory Write command, except
that it additionally guarantees a minimum transfer
of one complete cache line; i.e., the master intends
to write all bytes within the addressed cache line in
a single PCI transaction unless interrupted by the
target. This command requires implementation of
the PCI Cache Line Size register at address 0Ch in
PCI configuration space. The SYM53C810A
enables Memory Write and Invalidate cycles when
bit 0 in the CTEST3 register (WRIE) and bit 4 in
the PCI Command register are set. This will cause
Memory Write and Invalidate commands to be
issued when the following conditions are met:
1. The CLSE bit, WRIE bit, and PCI Config
Command register, bit 4 must be set.
2. The cache line size register must contain a
legal burst size (2, 4, 8 or 16) value AND that
value must be less than or equal to the
DMODE burst size.
Multiple Cache Transfers
When multiple cache lines of data have been
read in during a MMOV instruction (See the
description for the Read Multiple command),
the SYM53C810A will issue a Write and Invalidate command using the burst size necessary
to transfer all the data in one transfer. For
example, if the cache line size is 4, and the chip
read in 16 dwords of data using a Read Multiple command, the chip will switch the burst
size to 16, and issue a Write and Invalidate to
transfer all 16 dwords in one bus ownership.
Latency
In accordance with the PCI specification, the
chip's latency timer will be ignored when issuing a
Write and Invalidate command such that when a
latency time-out has occurred, the SYM53C810A
will continue to transfer up until a cache line
boundary. At that point, the chip will relinquish
the bus, and finish the transfer at a later time using
another bus ownership. If the chip is transferring
multiple cache lines it will continue to transfer
until the next cache boundary is reached.
3. The chip must have enough bytes in the DMA
FIFO to complete at least one full cache line
burst.
PCI Target Retries
4. The chip must be aligned to a cache line
boundary.
When these conditions have been met, the
SYM53C810A will issue a Write and Invalidate
command instead of a Memory Write command
during all PCI write cycles.
During a Write and Invalidate transfer, if the target
device issues a retry (STOP with no TRDY, indicating that no data was transferred), the
SYM53C810A will relinquish the bus and immediately try to finish the transfer on another bus
ownership. The chip will issue another Write and
Invalidate command on the next ownership, in
accordance with the PCI specification.
PCI Target Disconnect
During a Write and Invalidate transfer, if the target
device issues a disconnect the SYM53C810A will
relinquish the bus and immediately try to finish the
transfer on another bus ownership. The chip will
not issue another Write and Invalidate command
on the next ownership.
SYM53C810A Data Manual
3-3
PCI Functional Description
PCI Cache Mode
Memory Read
Line Command
This command is identical to the Memory Read
command, except that it additionally indicates that
the master intends to fetch a complete cache line.
This command is intended to be used with bulk
sequential data transfers where the memory system
and the requesting master might gain some performance advantage by reading up to a cache line
boundary rather than a single memory cycle.The
Read Line Mode function that exists in the previous SYM53C8XX chips has been modified in the
SYM53C810A to reflect the PCI cache line size
register specifications. The functionality of the
Enable Read Line bit (bit 3 in DMODE) has been
modified to more resemble the Write and Invalidate mode in terms of conditions that must be met
before a Read Line command will be issued. However, the Read Line option will operate exactly like
the previous SYM53C8XX chips when cache
mode has been disabled by a CLSE bit reset or
when certain conditions exist in the chip
(explained below).
The Read Line mode is enabled by setting bit 3 in
the DMODE register. If cache mode is disabled,
Read Line commands will be issued on every read
data transfer, except op code fetches, as in previous SYM53C8XX chips.
If cache mode has been enabled, a Read Line command will be issued on all read cycles, except op
code fetches, when the following conditions have
been met:
1. The CLSE and Enable Read Line bits must be
set.
2. The Cache Line Size register must contain a
legal burst size value (2, 4, 8 or 16) AND that
value must be less than or equal to the
DMODE burst size.
3. The number of bytes to be transferred at the
time a cache boundary has been reached must
be equal to or greater than a full cache line
size.
3-4
4. The chip must be aligned to a cache line
boundary.
When these conditions have been met, the chip
will issue a Read Line command instead of a
Memory Read during all PCI read cycles. Otherwise, it will issue a normal Memory Read command.
Memory Read
Multiple Command
This command is identical to the Memory read
command except that it additionally indicates that
the master may intend to fetch more than one
cache line before disconnecting. The
SYM53C810A supports PCI Read Multiple functionality and will issue Read Multiple commands
on the PCI bus when the Read Multiple Mode is
enabled. This mode is enabled by setting bit 2 of
the DMODE register (ERMP). The command will
be issued when certain conditions have been met.
If cache mode has been enabled, a Read Multiple
command will be issued on all read cycles, except
op code fetches, when the following conditions
have been met:
1. The CLSE and ERMP bits must be set.
2. The Cache Line Size register must contain a
legal burst size value (2, 4, 8 or 16) AND that
value must be less than or equal to the
DMODE burst size.
3. The number of bytes to be transferred at the
time a cache boundary has been reached must
be equal to or greater than the DMODE burst
size.
4. The chip must be aligned to a cache line
boundary.
When these conditions have been met, the chip
will issue a Read Multiple command instead of a
Memory Read during all PCI read cycles.
SYM53C810A Data Manual
PCI Functional Description
PCI Cache Mode
Burst Size Selection
The Read Multiple command reads in multiple
cache lines of data in a single bus ownership. The
number of cache lines to be read is determined by
the DMODE burst size bits. In other words, the
chip will switch its normal operating burst size to
reflect the DMODE burst size settings for the
Read Multiple command. For example, if the
cache line size is 4, and the DMODE burst size is
16, the chip will switch the current burst size from
4 to 16, and issue a Read Multiple. After the transfer, the chip will then switch the burst size back to
the normal operating burst size of 4.
Read Multiple with Read Line Enabled
met. Instead, a Read Multiple command will be
issued, even though the conditions for Read Line
have been met.
If the Read Multiple mode is enabled and the Read
Line mode has been disabled, Read Multiple commands will still be issued if the Read Multiple conditions are met.
Unsupported PCI
Commands
The SYM53C810A does not respond to reserved
commands, special cycle, dual address cycle, or
interrupt acknowledge commands as a slave. It will
never generate these commands as a master.
When both the Read Multiple and Read Line
modes have been enabled, the Read Line command will not be issued if the above conditions are
Table 3-1: PCI Bus Commands and Encoding Types
C_BE(3-0)
Command Type
Supported as Master
Supported as Slave
0000
Interrupt Acknowledge
No
No
0001
Special Cycle
No
No
0010
I/O Read Cycle
Yes
Yes
0011
I/O Write Cycle
Yes
Yes
0100
Reserved
n/a
0101
Reserved
n/a
0110
Memory Read
Yes
Yes
0111
Memory Write
Yes
Yes
1000
Reserved
n/a
1001
Reserved
n/a
1010
Configuration Read
No
Yes
1011
Configuration Write
No
Yes
1100
Memory Read Multiple
Yes
No (defaults to 0110)
1101
Dual Address Cycle
No
No
1110
Memory Read Line
Yes
No (defaults to 0110)
1111
Memory Write and Invalidate
Yes
No (defaults to 0111)
SYM53C810A Data Manual
3-5
PCI Functional Description
Configuration Registers
For detailed information, refer to the PCI Specification.
Configuration Registers
Figure 3-1 shows the PCI configuration registers
implemented by the SYM53C810A. Addresses
40h through 7Fh are not defined.
The Configuration registers are accessible only by
system BIOS during PCI configuration cycles, and
are not available to the user at any time. No other
cycles, including SCRIPTS operations, can access
these registers.
All PCI-compliant devices, such as the
SYM53C810A, must support the Vendor ID,
Device ID, Command, and Status Registers. Support of other PCI-compliant registers is optional.
In the SYM53C810A, registers that are not supported are not writable and return all zeroes when
read. Only those registers and bits that are currently supported by the SYM53C810A are
described in this chapter. For more detailed information on PCI registers, please see the PCI Specification.
The lower 128 bytes hold configuration data while
the upper 128 bytes hold the SYM53C810A operating registers, which are described in Chapter
Five, “Operating Registers.” The operating registers can be accessed by SCRIPTS or the host processor.
Note: the configuration register descriptions are
provided for general information only, to
indicate which PCI configuration addresses
are supported in the SYM53C810A.
31
16 15
0
Device ID = 0001h
Vendor ID = 1000h
00h
Status
Command
04h
Class Code = 010000h
Not Supported
Max_Lat
Header Type
Latency Timer
Rev ID=01h
08h
Cache Line Size
0Ch
Base Address Zero (I/O)*
10h
Base Address One (Memory)**
14h
Not Supported
18h
Not Supported
1Ch
Not Supported
20h
Not Supported
24h
Reserved
28h
Reserved
2Ch
Reserved
30h
Reserved
34h
Reserved
38h
Min_Gnt
Interrupt Pin
Interrupt Line
3Ch
Figure 3-1: PCI Configuration Register Map
*I/O Base is supported
**Memory Base is supported
Note: Addresses 40h to 7Fh are not defined. All unsupported registers are not writable and will return all zeroes when read. Reserved
registers will also return zeroes when read.
3-6
SYM53C810A Data Manual
PCI Functional Description
Configuration Registers
Register 00h
Vendor ID
Read Only
This field identifies the manufacturer of the device.
Symbios Logic Vendor ID is 1000h.
Register 02h
Device ID
Read Only
This field identifies the particular device. The
SYM53C810A device ID is 0001h.
Register 04h
Command
Read/Write
The Command Register, illustrated in Figure 3-2,
provides coarse control over a device’s ability to
generate and respond to PCI cycles. When a zero is
written to this register, the SYM53C810A is logically disconnected from the PCI bus for all
accesses except configuration accesses.
In the SYM53C810A, bits 3, 5, 7, and 9 are not
implemented. Bits 10 through 15 are reserved.
Bits 15-10 Reserved
Bit 8 SERR/ Enable
This bit enables the SERR/ driver. SERR/ is
disabled when this bit is clear. The default
value of this bit is zero. This bit and bit 6 must
be set to report address parity errors.
more information on these conditions, refer to
the section "Memory Write and Invalidate
Command" To enable Write and Invalidate
Mode, bit 0 in the CTEST3 register (Operating registers) must also be set.
Bit 2 Enable Bus Mastering
This bit controls the SYM53C810A’s ability to
act as a master on the PCI bus. A value of zero
disables the device from generating PCI bus
master accesses. A value of one allows the
SYM53C810A to behave as a bus master.
The SYM53C810A must be a bus master in
order to fetch SCRIPTS instructions and
transfer data.
Bit 1 Enable Memory Space
This bit controls the SYM53C810A’s response
to memory space accesses. A value of zero disables the device response. A value of one allows
the SYM53C810A to respond to memory
space accesses at the address specified by Base
Address One .
Bit 0 Enable I/O Space
This bit controls the SYM53C810A’s response
to I/O space accesses. A value of zero disables
the response. A value of one allows the
SYM53C810A to respond to I/O space
accesses at the address specified in Base
Address Zero.
Bit 6 Enable Parity Error Response
This bit allows the SYM53C810A to detect
parity errors on the PCI bus and report these
errors to the system. Only data parity checking
is enabled. The SYM53C810A always generates parity for the PCI bus.
Bit 4 Write and Invalidate Mode
This bit, when set, will cause Memory Write
and Invalidate cycles to be issued on the PCI
bus after certain conditions have been met. For
SYM53C810A Data Manual
3-7
PCI Functional Description
Configuration Registers
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Not Implemented
SERR/ Enable
Not Implemented
Enable Parity Response
Not Implemented
Write and Invalidate Mode
Not Implemented
15 14 13 12 1110 9 8 7 6 5 4 3 2 1 0
Enable Bus Mastering
Enable Memory Space
Enable I/O Space
Figure 3-2: Command Register Layout
Register 06h
Status
Read/Write
The Status Register, illustrated in Figure 3-3, is
used to record status information for PCI busrelated events.
In the SYM53C810A, bits 0 through 4 are
reserved and bits 5, 6, 7, and 11 are not implemented by the SYM53C810A.
Reads to this register behave normally. Writes are
slightly different in that bits can be reset, but not
set. A bit is reset whenever the register is written,
and the data in the corresponding bit location is a
one. For instance, to clear bit 15 and not affect any
other bits, write the value 8000h to the register.
Bit 14 Signaled System Error
This bit is set whenever a device asserts the
SERR/ signal.
Bit 13 Master Abort (from Master)
This bit should be set by a master device whenever its transaction (except for Special Cycle) is
terminated with master-abort. All master
devices should implement this bit.
Bit 12 Received Target Abort (from
Master)
This bit should be set by a master device whenever its transaction is terminated with a target
abort. All master devices should implement
this bit.
Bit 15 Detected Parity Error (from Slave)
This bit will be set by the SYM53C810A
whenever it detects a data parity error, even if
parity error handling is disabled.
3-8
SYM53C810A Data Manual
PCI Functional Description
Configuration Registers
Bits 10-9 DEVSEL/ Timing
These bits encode the timing of DEVSEL/.
These are encoded as 00b for fast, 01b for
medium, 10b for slow, and 11b reserved.
These bits are read only and should indicate
the slowest time that a device asserts DEVSEL/
for any bus command except Configuration
Read and Configuration Write. The
SYM53C810A supports 01b.
Detected Parity Error (from Slave)
Signaled System Error
Received Master Abort (from Master)
Received Target Abort (from Master)
Not Implemented
Bit 8 Data Parity Reported
This bit is set when the following three conditions are met: 1) The bus agent asserted
PERR/ itself or observed PERR/ asserted; 2)
The agent setting this bit acted as the bus master for the operation in which the error
occurred; and 3) The Parity Error Response bit
in the Command register is set.
Bits 7-6 Not Implemented
Bits 5-0 Reserved
15 14 13 12 1110 9 8 7 6 5 4 3 2 1 0
DEVSEL timing
00 = fast, 01 = medium, 10 = slow
Data Parity Reported
Not Implemented
Not Implemented
Not Implemented
Reserved
Reserved
Reserved
Reserved
Reserved
Figure 3-3: Status Register Layout
SYM53C810A Data Manual
3-9
PCI Functional Description
Configuration Registers
Register 08h
Revision ID
Read Only
Register 0Dh
Latency Timer
Read/Write
This register specifies device and revision identifiers. In the SYM53C810A, the upper nibble is
0001b. The lower nibble represents the current
revision level of the device. It should have the same
value as the Chip Revision Level bits in the
CTEST3 register.
The Latency Timer register specifies, in units of
PCI bus clocks, the value of the Latency Timer for
this PCI bus master. The SYM53C810A supports
this timer. All eight bits are writable, allowing
latency values of 0-255 PCI clocks. Use the following equation to calculate an optimum latency value
for the SYM53C810A:
Register 09h
Class Code
Read Only
Latency = 2 + (Burst Size * (typical wait states +1)).
Values greater than optimum are also acceptable.
This register is used to identify the generic function of the device. The upper byte of this register is
a base class code, the middle byte is a subclass
code, and the lower byte identifies a specific register-level programming interface. The value of this
register is 010000h, which indicates a SCSI controller.
Register 0Ch
Cache Line Size
Read/Write
This register specifies the system cache line size in
units of 32-bit words. Cache mode is enabled and
disabled by the Cache Line Size Enable (CLSE)
bit, bit 7 in the DCNTL register. Setting this bit
causes the SYM53C810A to align to cache line
boundaries before allowing any bursting, except
during MMOVs in which the read and write
addresses are Burst Size boundary misaligned. For
more information, see “Support for PCI Cache
Line Size Register” on page 3-2.
3-10
SYM53C810A Data Manual
PCI Functional Description
Configuration Registers
Register 0Eh
Header Type
Read Only
Register 3Dh
Interrupt Pin
Read Only
This register identifies the layout of bytes 10h
through 3Fh in configuration space and also
whether or not the device contains multiple functions. The value of this register is 00h.
This register tells which interrupt pin the device
uses. Its value is set to 01h, for the INTA/ signal.
Register 10h
Base Address Zero (I/O)
Read/Write
This 32-bit register has bit zero hardwired to one.
Bit 1 is reserved and must return a zero on all
reads, and the other bits are used to map the
device into I/O space.
Register 14h
Base Address One (Memory)
Read/Write
This register has bit 0 hardwired to zero. For
detailed information on the operation of this register, refer to the PCI Specification.
Register 3Eh
Min_Gnt
Read Only
Register 3Fh
Max_Lat
Read Only
These registers are used to specify the desired settings for Latency Timer values. Min_Gnt is used to
specify how long a burst period the device needs.
Max_Lat is used to specify how often the device
needs to gain access to the PCI bus. The value
specified in these registers is in units of 0.25
microseconds. Values of zero indicate that the
device has no major requirements for the settings
of Latency Timers. The SYM53C810A sets the
Min_Gnt register to 11h and the Max_Lat register
to 40h.
Register 3Ch
Interrupt Line
Read/Write
This register is used to communicate interrupt line
routing information. POST software will write the
routing information into this register as it initiates
and configures the system. The value in this register tells which input of the system interrupt controller(s) has been connected to the device’s
interrupt pin. Values in this register are specified by
system architecture.
SYM53C810A Data Manual
3-11
PCI Functional Description
Configuration Registers
3-12
SYM53C810A Data Manual
Signal Descriptions
Chapter 4
Signal Descriptions
AD22
Vss-I
AD23
IDSEL
C_BE3/
AD24
AD25
Vss-I
AD26
AD27
V DD- I
AD28
AD29
Vss-I
AD30
AD31
V DD -C
REQ/
GNT/
Vss-C
This chapter presents the SYM53C810A pin configuration and signal definitions using tables and
illustrations. Figure 4-1 is the pin diagram and Figure 4-2 is a functional signal grouping. The pin definitions are presented in Table 4-1 through Table 4-8. The SYM53C810A is pin-for-pin compatible
with the SYM53C810.
99
AD21
AD20
V DD- I
AD19
V SS- I
AD18
AD17
AD16
Vss-I
C_BE2/
FRAME/
IRDY/
Vss-I
TRDY/
DEVSEL/
V DD- I
STOP/
V SS-I
PERR/
PAR
C_BE1/
V SS- I
AD15
AD14
AD13
V SS-I
AD12
V DD-I
AD11
AD10
97
95
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
93
91
89
87
85
83
81
80
79
78
77
76
75
74
73
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
51
SYM53C810A
100-Pin QFP
34
36
38
40
42
44
46
48
50
AD9
Vss-I
AD8
C_BE0/
AD7
AD6
Vss-I
AD5
AD4
VDD- I
AD3
AD2
Vss-I
AD1
AD0
VDD -C
IRQ/
GPIO0_FETCH/
GPIO1_MASTER/
VSS -C
32
CLK
RST/
SERR/
V DD -S
SD0/
SD1/
SD2/
Vss-S
SD3/
SD4/
SD5/
SD6/
Vss-S
SD7/
SDP/
SATN/
SBSY/
Vss-S
SACK/
SRST/
SMSG/
SSEL/
Vss-S
SCD/
SREQ/
SIO/
V DD -S
MAC/_TESTOUT
TESTIN
SCLK
Figure 4-1: SYM53C810A Pin Diagram
The decoupling capacitor arrangement shown above is recommended to maximize the benefits of the internal split ground system. Capacitor values between 0.01 and 0.1µF should provide adequate noise isolation. Because of the number of high current drivers on the
SYM53C810A, a multi-layer PC board with power and ground planes is required.
SYM53C810A Data Manual
4-1
Signal Descriptions
The PCI/SCSI pin definitions are organized into
the following functional groups: Power and
Ground, System, Address/Data, Interface Control,
Arbitration, Error Reporting, SCSI, and Optional
Interface. A slash (/) at the end of the signal name
indicates that the active state occurs when the signal is at a low voltage. When the slash is absent, the
signal is active at a high voltage.
There are four signal type definitions:
I
Input, a standard input-only signal
O
Totem Pole Output, a standard output driver
T/S
Tri-State, a bi-directional, tri-state
input/output pin
S/T/S
Sustained Tri-state, an active low
tri-state signal owned and driven by
one and only one agent at a time
Table 4-1: Power and Ground Pins
Symbol
Pin No.
Description
VSS-I
5, 9, 13, 18, 22, 26,
32, 37, 43, 87, 93, 99
Power supplies to the PCI I/O pins
VDD-I*
3, 16, 28, 40, 90
Power supplies to the PCI I/O pins
VSS-S
58, 63, 68, 73
Power supplies to the SCSI bus I/O pins
VDD-S
54, 77
Power supplies to the SCSI bus I/O pins
VSS-C
50, 81
Power supplies to the internal logic core
VDD-C
46, 84
Power supplies to the internal logic core
*These pins can accept a VDD source of 3.3 or 5 Volts. All other VDD pins must be supplied 5 Volts.
4-2
SYM53C810A Data Manual
Signal Descriptions
System
CLK
SCLK
SD7-0
SDP
RST
SCSI
SCTRL/
AD31-0
Address and Data
C_BE/3-0
PAR
FRAME/
TRDY/
Interface Control
Arbitration
Error Reporting
IRDY/
STOP/
DEVSEL/
IDSEL
REQ/
GNT/
SERR/
PERR/
GPIO0_FETCH/
GPIO1_MASTER/
MAC/_TESTOUT
Additional Interface
IRQ/
TESTIN/
Figure 4-2: Functional Signal Grouping
SYM53C810A Data Manual
4-3
Signal Descriptions
Table 4-2: System Pins
Symbol
Pin No.
Type
Description
CLK
80
I
Clock. Clock provides timing for all transactions on the PCI bus
and is an input to every PCI device. All other PCI signals are
sampled on the rising edge of CLK, and other timing parameters are defined with respect to this edge. This clock can optionally be used as the SCSI core clock; however, the
SYM53C810A will not achieve fast SCSI transfer rates.
RST/
79
I
Reset. Reset forces the PCI sequencer of each device to a known
state. All t/s and s/t/s signals are forced to a high impedance
state, and all internal logic is reset. The RST/ input is synchronized internally to the rising edge of CLK. The CLK input must
be active while RST/ is active to properly reset the device.
Table 4-3: Address and Data Pins
Symbol
Pin No.
Type
Description
AD(31-0)
85, 86, 88,
89, 91, 92,
94, 95, 98,
100, 1, 2, 4,
6, 7, 8, 23,
24, 25, 27,
29, 30, 31,
33, 35, 36,
38, 39, 41,
42, 44, 45
T/S
Address/Data. Physical dword address and data are multiplexed
on the same PCI pins. During the first clock of a transaction,
AD(31-0) contain a physical byte address. During subsequent
clocks, AD(31-0) contain data. A bus transaction consists of an
address phase, followed by one or more data phases. PCI supports both read and write bursts. AD(7-0) define the least significant byte, and AD(31-24) define the most significant byte.
C_BE/(3-0)
96, 10, 21,
34
T/S
Command/Byte Enable. Bus command and byte enables are multiplexed on the same PCI pins. During the address phase of a
transaction, C_BE(3-0)/ define the bus command. During the
data phase, C_BE(3-0)/ are used as byte enables. The byte
enables determine which byte lanes carry meaningful data.
C_BE/(0) applies to byte lane 0, and C_BE/(3) to byte lane 3.
PAR
20
T/S
Parity. Parity is the even parity bit that protects the AD(31-0)
and C_BE/(3-0) lines. During address phase, both the address
and command bits are covered. During data phase, both data
and byte enables are covered.
4-4
SYM53C810A Data Manual
Signal Descriptions
Table 4-4: Interface Control Pins
Symbol
Pin No.
Type
Description
FRAME/
11
S/T/S
Cycle Frame. Cycle Frame is driven by the current master to indicate the beginning and duration of an access. FRAME/ is asserted
to indicate a bus transaction is beginning. While FRAME/ is
asserted, data transfers continue. When FRAME/ is deasserted, the
transaction is in the final data phase or the bus is idle.
TRDY/
14
S/T/S
Target Ready. Target Ready indicates the target agent’s (selected
device’s) ability to complete the current data phase of the transaction. TRDY/ is used with IRDY/. A data phase is completed on any
clock when both TRDY/ and IRDY/ are sampled asserted. During a
read, TRDY/ indicates that valid data is present on AD(31-0). During a write, it indicates the target is prepared to accept data. Wait
cycles are inserted until both IRDY/ and TRDY/ are asserted
together.
IRDY/
12
S/T/S
Initiator Ready. Initiator Ready indicates the initiating agent’s (bus
master’s) ability to complete the current data phase of the transaction. This signal is used with TRDY/. A data phase is completed on
any clock when both IRDY/ and TRDY/ are sampled asserted. During a write, IRDY/ indicates that valid data is present on AD(31-0).
During a read, it indicates the master is prepared to accept data.
Wait cycles are inserted until both IRDY/ and TRDY/ are asserted
together.
STOP/
17
S/T/S
Stop. Stop indicates that the selected target is requesting the master
to stop the current transaction.
DEVSEL/
15
S/T/S
Device Select. Device Select indicates that the driving device has
decoded its address as the target of the current access. As an input,
it indicates to a master whether any device on the bus has been
selected.
IDSEL
97
I
Initialization Device Select. Initialization Device Select is used as a
chip select in place of the upper 24 address lines during configuration read and write transactions.
Table 4-5: Arbitration Pins
Symbol
Pin No.
Type
Description
REQ/
83
O
Request. Request indicates to the arbiter that this agent desires to
use the PCI bus. This is a point-to-point signal. Every master has its
own REQ/.
GNT/
82
I
Grant. Grant indicates to the agent that access to the PCI bus has
been granted. This is a point-to-point signal. Every master has its
own GNT/.
SYM53C810A Data Manual
4-5
Signal Descriptions
Table 4-6: Error Reporting Pins
Symbol
Pin No.
Type
Description
PERR/
19
S/T/S
Parity Error. Parity Error may be pulsed active by an agent that
detects a parity error. PERR/ can be used by any agent to signal
data corruptions. However, on detection of a PERR/ pulse, the central resource may generate a non-maskable interrupt to the host
CPU, which often implies the system will be unable to continue
operation once error processing is complete.
SERR/
78
O
System Error. This open drain output pin is used to report address
parity errors.
Table 4-7: SCSI Pins
Symbol
Pin No.
Type
Description
SCLK
51
I
SCSI Clock. SCLK is used to derive all SCSI-related timings. The
speed of this clock is determined by the application’s requirements;
in some applications SCLK may be sourced internally from the
PCI bus clock (CLK). If SCLK is internally sourced, then the
SCLK pin should be tied low.
SD(7-0),
SDP
67, 69, 70,71,72,
74, 75, 76, 66
I/O
SCSI Data. SCSI Data includes the following data lines and parity
signals: SD(7-0) (8-bit SCSI data bus), and SDP (SCSI data parity bit).
SCTRL/
57, 55, 60, 56,
62, 64, 65, 61, 59
I/O
SCSI Control. SCSI Control includes the following signals:
SCD/
SCSI phase line, command/data
SIO/
SCSI phase line, input/output
SMSG/ SCSI phase line, message
SREQ/
Data handshake signal from target device
SACK/
Data handshake signal from initiator device
SBSY/
SCSI bus arbitration signal, busy
SATN/
SCSI Attention, the initiator is requesting a message
out phase
SRST/
SCSI bus reset
SSEL/
SCSI bus arbitration signal, select device
4-6
SYM53C810A Data Manual
Signal Descriptions
Table 4-8: Additional Interface Pins
Symbol
Pin No.
Type
Description
TESTIN/
52
I
Test In. When this pin is driven low, the SYM53C810A connects all
inputs and outputs to an “AND tree.” The SCSI control signals
and data lines are not connected to the “AND tree.” The output of
the “AND tree” is connected to the Test Out pin. This allows manufacturers to verify chip connectivity and determine exactly which
pins are not properly attached. When the TESTIN pin is driven
low, internal pull-ups are enabled on all input, output, and bidirectional pins, all outputs and bidirectional signals will be tri-stated,
and the MAC/_TESTOUT pin will be enabled. Connectivity can
be tested by driving one of the SYM53C810A pins low. The MAC/
_TESTOUT pin should respond by also driving low.
GPIO0_
FETCH/
48
I/O
General Purpose I/O pin. Optionally, when driven low, indicates that
the next bus request will be for an op code fetch. This pin powers
up as a general purpose input.
This pin has two specific purposes in the Symbios Logic SDMS
software. SDMS uses it to toggle SCSI device LEDs, turning on
the LED whenever the SYM53C810A is on the SCSI bus. SDMS
drives this pin low to turn on the LED, or drives it high to turn off
the LED. This signal can also be used as data I/O for serial
EEPROM access. In this case it is used with the GPIO0 pin, which
serves as a clock. The pin can be controlled from PCI configuration
register 35h or observed from the GPREG operating register, at
address 07h.
GPIO1_
MASTER/
49
I/O
General Purpose I/O pin. Optionally, when driven low, indicates that
the SYM53C810A is bus master. This pin powers up as a general
purpose input.
Symbios Logic SDMS software supports use of this signal in serial
EPROM applications, when enabled, in combination with the
GPIO0 pin. When this signal is used as a clock for serial EEPROM
access, the GPIO1 pin serves as data, and the pin is controlled
from PCI configuration register 35h.
MAC_
TESTOUT
53
T/S
Memory Access Control/Test Out. This pin can be programmed to
indicate local or system memory accesses (non-PCI applications).
It is also used to test the connectivity of the SYM53C810A signals
using an “AND tree” scheme. The MAC/_TESTOUT pin is only
driven as the Test Out function when the TESTIN/ pin is driven
low.
IRQ/
47
O
Interrupt. This signal, when asserted low, indicates that an interrupting condition has occurred and that service is required from
the host CPU. The output drive of this pin is programmed as either
open drain with an internal weak pull-up or, optionally, as a totem
pole driver. Refer to the description of DCNTL Register, bit 3, for
additional information.
SYM53C810A Data Manual
4-7
Signal Descriptions
4-8
SYM53C810A Data Manual
Operating Registers
Chapter 5
Operating Registers
This section contains descriptions of all
SYM53C810A operating registers. Table 5-1 summarizes the SYM53C810A operating register set.
Figure 5-1, the register map, lists registers by operating and configuration addresses. The terms “set”
and “assert” are used to refer to bits that are programmed to a binary one. Similarly, the terms
“deassert,” “clear” and “reset” are used to refer to
bits that are programmed to a binary zero. Any bits
marked as reserved should always be written to zero; mask all information read from them. Reserved
bit functions may be changed at any time. Unless
otherwise indicated, all bits in registers are active
high, that is, the feature is enabled by setting the
bit. The bottom row of every register diagram
shows the default register values, which are enabled
after the chip is powered on or reset.
Note: the only register that the host CPU can
access while the SYM53C810A is
executing SCRIPTS is the ISTAT register;
attempts to access other registers will
interfere with the operation of the chip.
However, all operating registers are
accessible with SCRIPTS. All read data is
synchronized and stable when presented to
the PCI bus.
Note: the SYM53C810A cannot fetch SCRIPTS
instructions from the operating register
space. Instructions must be fetched from
system memory.
Table 5-1: Operating Register Addresses and Descriptions
Memory
or I/O
Address
Offset
PCI
Configuration
Address
Read/Write
Label
Description
00
80
R/W
SCNTL0
SCSI Control 0
01
81
R/W
SCNTL1
SCSI Control 1
02
82
R/W
SCNTL2
SCSI Control 2
03
83
R/W
SCNTL3
SCSI Control 3
04
84
R/W
SCID
SCSI Chip ID
05
85
R/W
SXFER
SCSI Transfer
06
86
R/W
SDID
SCSI Destination ID
07
87
R/W
GPREG
General Purpose Bits
08
88
R/W
SFBR
SCSI First Byte Received
09
89
R/W
SOCL
SCSI Output Control Latch
0A
8A
R
SSID
SCSI Selector ID
SYM53C810A Data Manual
5-1
Operating Registers
Table 5-1: Operating Register Addresses and Descriptions (Continued)
Memory
or I/O
Address
Offset
PCI
Configuration
Address
Read/Write
Label
Description
0B
8B
R/W
SBCL
SCSI Bus Control Lines
0C
8C
R
DSTAT
DMA Status
0D
8D
R
SSTAT0
SCSI Status 0
0E
8E
R
SSTAT1
SCSI Status 1
0F
8F
R
SSTAT2
SCSI Status 2
10-13
90-93
R/W
DSA
Data Structure Address
14
94
R/W
ISTAT
Interrupt Status
15-17
95-97
18
98
R/W
CTEST0
Reserved
19
99
R/W
CTEST1
Chip Test 1
1A
9A
R
CTEST2
Chip Test 2
1B
9B
R
CTEST3
Chip Test 3
1C-1F
9C-9F
R/W
TEMP
Temporary Stack
20
A0
R/W
DFIFO
DMA FIFO
21
A1
R/W
CTEST4
Chip Test 4
22
A2
R/W
CTEST5
Chip Text 5
23
A3
R/W
CTEST6
Chip Test 6
24-26
A4-A6
R/W
DBC
DMA Byte Counter
27
A7
R/W
DCMD
DMA Command
28-2B
A8-AB
R/W
DNAD
DMA Next Address for Data
2C-2F
AC-AF
R/W
DSP
DMA SCRIPTS Pointer
30-33
B0-B3
R/W
DSPS
DMA SCRIPTS Pointer Save
34-37
B4-B7
R/W
SCRATCHA
General Purpose Scratch Pad A
38
B8
R/W
DMODE
DMA Mode
39
B9
R/W
DIEN
DMA Interrupt Enable
3A
BA
R/W
SBR
Scratch Byte Register
3B
BB
R/W
DCNTL
DMA Control
3C-3F
BC-BF
R
ADDER
Sum output of internal adder
40
C0
R/W
SIEN0
SCSI Interrupt Enable 0
41
C1
R/W
SIEN1
SCSI Interrupt Enable 1
42
C2
R
SIST0
SCSI Interrupt Status 0
43
C3
R
SIST1
SCSI Interrupt Status 1
44
C4
R/W
SLPAR
SCSI Longitudinal Parity
5-2
Reserved
SYM53C810A Data Manual
Operating Registers
Table 5-1: Operating Register Addresses and Descriptions (Continued)
Memory
or I/O
Address
Offset
PCI
Configuration
Address
45
C5
46
C6
R/W
MACNTL
Memory Access Control
47
C7
R/W
GPCNTL
General Purpose Control
48
C8
R/W
STIME0
SCSI Timer 0
49
C9
R/W
STIME1
SCSI Timer 1
4A
CA
R/W
RESPID
Response ID
4B
CB
4C
CC
R
STEST0
SCSI Test 0
4D
CD
R
STEST1
SCSI Test 1
4E
CE
R/W
STEST2
SCSI Test 2
4F
CF
R/W
STEST3
SCSI Test 3
50
D0
R
SIDL
SCSI Input Data Latch
51-53
D1-D3
54
D4
55-57
D5-D7
58
D8
59-5B
D9-DB
5C-5F
DC-DF
SYM53C810A Data Manual
Read/Write
Label
Description
Reserved
Reserved
Reserved
R/W
SODL
SCSI Output Data Latch
Reserved
R
SBDL
SCSI Bus Data Lines
Reserved
R/W
SCRATCHB
General Purpose Scratch Pad B
5-3
Operating Registers
Mem I/O
Config
SCNTL3
SCNTL2
SCNTL1
SCNTL0
00
80
GPREG
SDID
SXFER
SCID
04
84
SBCL
SSID
SOCL
SFBR
08
88
SSTAT2
SSTAT1
SSTAT0
DSTAT
0C
8C
10
90
ISTAT
14
94
RESERVED
18
98
1C
9C
20
A0
24
A4
DNAD
28
A8
DSP
2C
AC
DSPS
30
B0
SCRATCH A
34
B4
38
B8
3C
BC
DSA
RESERVED
CTEST3
CTEST2
CTEST1
TEMP
CTEST6
CTEST5
CTEST4
DCMD
DCNTL
DFIFO
DBC
SBR
DIEN
DMODE
ADDER
SIST1
SIST0
SIEN1
SIEN0
40
C0
GPCNTL
MACNTL
RESERVED
SLPAR
44
C4
RESERVED
RESPID
STIME1
STIME0
48
C8
STEST3
STEST2
STEST1
STEST0
4C
CC
RESERVED
SIDL
50
D0
RESERVED
SODL
54
D4
RESERVED
SBDL
58
D8
5C
DC
SCRATCH B
Figure 5-1: SYM53C810A Register Address Map
5-4
SYM53C810A Data Manual
Operating Registers
Full Arbitration, Selection/Reselection
Register 00 (80)
SCSI Control Zero (SCNTL0)
Read/Write
1. The SYM53C810A waits for a bus free
condition.
ARB1
ARB0
START
WATN
EPC
RES
AAP
TRG
7
6
5
4
3
2
1
0
0
0
0
X
0
0
Default>>>
1
1
Bit 7
ARB1 (Arbitration mode bit 1)
Bit 6
ARB0 (Arbitration mode bit 0)
ARB1
ARB0
Arbitration Mode
0
0
Simple arbitration
0
1
Reserved
1
0
Reserved
1
1
Full arbitration, selection/reselection
Simple Arbitration
1. The SYM53C810A waits for a bus free
condition to occur.
2. It asserts SBSY/ and its SCSI ID
(contained in the SCID register) onto the
SCSI bus. If the SSEL/ signal is asserted by
another SCSI device, the SYM53C810A
will deassert SBSY/, deassert its ID and set
the Lost Arbitration bit (bit 3) in the
SSTAT0 register.
3. After an arbitration delay, the CPU should
read the SBDL register to check if a higher
priority SCSI ID is present. If no higher
priority ID bit is set, and the Lost
Arbitration bit is not set, the
SYM53C810A has won arbitration.
4. Once the SYM53C810A has won
arbitration, SSEL/ must be asserted via the
SOCL for a bus clear plus a bus settle delay
(1.2 µs) before a low level selection can be
performed.
SYM53C810A Data Manual
2. It asserts SBSY/ and its SCSI ID (stored in
the SCID register) onto the SCSI bus.
3. If the SSEL/ signal is asserted by another
SCSI device or if the SYM53C810A
detects a higher priority ID, the
SYM53C810A will deassert BSY, deassert
its ID, and wait until the next bus free state
to try arbitration again.
4. The SYM53C810A repeats arbitration
until it wins control of the SCSI bus. When
it has won, the Won Arbitration bit is set in
the SSTAT0 register, bit 2.
5. The SYM53C810A performs selection by
asserting the following onto the SCSI bus:
SSEL/, the target’s ID (stored in the SDID
register), and the SYM53C810A’s ID
(stored in the SCID register).
6. After a selection is complete, the Function
Complete bit is set in the SIST0 register,
bit 6.
7. If a selection time-out occurs, the Selection
Time-Out bit is set in the SIST1 register,
bit 2.
Bit 5
START (Start sequence)
When this bit is set, the SYM53C810A will
start the arbitration sequence indicated by the
Arbitration Mode bits. The Start Sequence bit
is accessed directly in low-level mode; during
SCSI SCRIPTS operations, this bit is controlled by the SCRIPTS processor. An arbitration sequence should not be started if the
connected (CON) bit in the SCNTL1 register,
bit 4, indicates that the SYM53C810A is
already connected to the SCSI bus. This bit is
automatically cleared when the arbitration
sequence is complete. If a sequence is aborted,
bit 4 in the SCNTL1 register should be
checked to verify that the SYM53C810A did
not connect to the SCSI bus.
5-5
Operating Registers
Bit 4
WATN (Select with SATN/ on a start
sequence)
When this bit is set and the SYM53C810A is
in initiator mode, the SATN/ signal will be
asserted during SYM53C810A selection of a
SCSI target device. This is to inform the target
that the SYM53C810A has a message to send.
If a selection time-out occurs while attempting
to select a target device, SATN/ will be deasserted at the same time SSEL/ is deasserted.
When this bit is clear, the SATN/ signal will
not be asserted during selection. When executing SCSI SCRIPTS, this bit is controlled by
the SCRIPTS processor, but it may be set
manually in low level mode.
Bit 3
EPC (Enable parity checking)
When this bit is set, the SCSI data bus is
checked for odd parity when data is received
from the SCSI bus in either initiator or target
mode. If a parity error is detected, bit 0 of the
SIST0 register is set and an interrupt may be
generated.
If the Assert SATN/ on Parity Error bit is
cleared or the Enable Parity Checking bit is
cleared, SATN/ will not be automatically
asserted on the SCSI bus when a parity error is
received.
Bit 0
TRG (Target role)
This bit determines the default operating role
of the SYM53C810A. The user must manually
set target or initiator role. This can be done
using the SCRIPTS language (SET TARGET
or CLEAR TARGET). When this bit is set, the
chip is a target device by default. When this bit
is cleared, the SYM53C810A is an initiator
device by default.
CAUTION:
Writing this bit while not connected may cause the
loss of a selection or reselection due to the changing of target or initiator roles.
If the SYM53C810A is operating in initiator
mode and a parity error is detected, SATN/
can optionally be asserted, but the transfer
continues until the target changes phase. When
this bit is cleared, parity errors are not
reported.
Bit 2
Reserved
Bit 1
AAP (Assert SATN/ on parity error)
When this bit is set, the SYM53C810A automatically asserts the SATN/ signal upon detection of a parity error. SATN/ is only asserted in
initiator mode. The SATN/ signal is asserted
before deasserting SACK/ during the byte
transfer with the parity error. The Enable Parity Checking bit must also be set for the
SYM53C810A to assert SATN/ in this manner. A parity error is detected on data received
from the SCSI bus.
5-6
SYM53C810A Data Manual
Operating Registers
Register 01 (81)
SCSI Control One (SCNTL1)
Read/Write
EXC
ADB
DHP
CON
RST
AESP
IARB
SST
7
6
5
4
3
2
1
0
0
0
0
0
0
0
Default>>>
0
0
Bit 7
EXC (Extra clock cycle of data
setup)
When this bit is set, an extra clock period of
data setup is added to each SCSI data send
transfer. The extra data setup time can provide
additional system design margin, though it will
affect the SCSI transfer rates. Clearing this bit
disables the extra clock cycle of data setup
time. Setting this bit only affects SCSI send
operations.
Bit 6
ADB (Assert SCSI data bus)
When this bit is set, the SYM53C810A drives
the contents of the SCSI Output Data Latch
Register (SODL) onto the SCSI data bus.
When the SYM53C810A is an initiator, the
SCSI I/O signal must be inactive to assert the
SODL contents onto the SCSI bus. When the
SYM53C810A is a target, the SCSI I/O signal
must be active for the SODL contents to be
asserted onto the SCSI bus. The contents of
the SODL register can be asserted at any time,
even before the SYM53C810A is connected to
the SCSI bus. This bit should be cleared when
executing SCSI SCRIPTS. It is normally used
only for diagnostics testing or operation in low
level mode.
Bit 5
DHP (Disable Halt on Parity Error
or ATN) (Target Only)
The DHP bit is only defined for target role.
When this bit is cleared, the SYM53C810A
halts the SCSI data transfer when a parity error
is detected or when the SATN/ signal is
asserted. If SATN/ or a parity error is received
in the middle of a data transfer, the
SYM53C810A may transfer up to three additional bytes before halting to synchronize
SYM53C810A Data Manual
between internal core cells. During synchronous operation, the SYM53C810A transfers
data until there are no outstanding synchronous offsets. If the SYM53C810A is receiving
data, any data residing in the DMA FIFO is
sent to memory before halting.
When this bit is set, the SYM53C810A does
not halt the SCSI transfer when SATN/ or a
parity error is received.
Bit 4
CON (Connected)
This bit is automatically set any time the
SYM53C810A is connected to the SCSI bus
as an initiator or as a target. It is set after the
SYM53C810A successfully completes arbitration or when it has responded to a bus initiated
selection or reselection. This bit is also set after
the chip wins simple arbitration when operating in low level mode. When this bit is clear,
the SYM53C810A is not connected to the
SCSI bus.
The CPU can force a connected or disconnected condition by setting or clearing this bit.
This feature would be used primarily during
loopback mode.
Bit 3
RST (Assert SCSI RST/ signal)
Setting this bit asserts the SRST/ signal. The
SRST/ output remains asserted until this bit is
cleared. The 25 µs minimum assertion time
defined in the SCSI specification must be
timed out by the controlling microprocessor or
a SCRIPTS loop.
Bit 2
AESP (Assert even SCSI parity
(force bad parity))
When this bit is set, the SYM53C810A asserts
even parity. It forces a SCSI parity error on
each byte sent to the SCSI bus from the
SYM53C810A. If parity checking is enabled,
then the SYM53C810A checks data received
for odd parity. This bit is used for diagnostic
testing and should be clear for normal operation. It can be used to generate parity errors to
test error handling functions.
5-7
Operating Registers
Bit 1
IARB (Immediate Arbitration)
Setting this bit causes the SCSI core to immediately begin arbitration once a Bus Free phase
is detected following an expected SCSI disconnect. This bit is useful for multi-threaded applications. The ARB1-0 bits in SCNTL0 should
be set for full arbitration and selection before
setting this bit.
Arbitration will be re-tried until won. At that
point, the SYM53C810A will hold BSY and
SEL asserted, and wait for a select or reselect
sequence to be requested. The Immediate
Arbitration bit will be reset automatically when
the selection or reselection sequence is completed, or times out. Interrupts will not occur
until after this bit is reset.
Bit 0
SST (Start SCSI Transfer)
This bit is automatically set during SCRIPTS
execution, and should not be used. It causes
the SCSI core to begin a SCSI transfer, including SREQ/SACK handshaking. The determination of whether the transfer is a send or
receive is made according to the value written
to the I/O bit in SOCL. This bit is self-resetting. It should not be set for low level operation.
CAUTION:
Writing to this register while not connected may
cause the loss of a selection/reselection by resetting
the Connected bit.
An unexpected disconnect condition will clear
IARB without attempting arbitration. See the
SCSI Disconnect Unexpected bit (SCNTL2,
bit 7) for more information on expected versus
unexpected disconnects.
An immediate arbitration sequence can be
aborted. First, the Abort bit in the ISTAT register should be set. Then one of two things will
eventually happen:
1. The Won Arbitration bit (SSTAT0 bit 2)
will be set. In this case, the Immediate
Arbitration bit needs to be reset. This will
complete the abort sequence and
disconnect the SYM53C810A from the
SCSI bus. If it is not acceptable to go to
Bus Free phase immediately following the
arbitration phase, a low level selection may
be performed instead.
2. The abort will complete because the
SYM53C810A loses arbitration. This can
be detected by the Immediate Arbitration
bit being cleared. The Lost Arbitration bit
(SSTAT0 bit 3) should not be used to
detect this condition. No further action
needs to be taken in this case.
5-8
SYM53C810A Data Manual
Operating Registers
Register 02 (82)
SCSI Control Two (SCNTL2)
Read/Write
Register 03 (83)
SCSI Control Three (SCNTL3)
Read/Write
SDU
RES
RES
RES
RES
RES
RES
RES
RES
SCF2
SCF1
SCF0
RES
CCF2
CCF1
CCF0
7
6
5
4
3
2
1
0
7
6
5
4
3
2
1
0
0
0
X
0
0
0
Default>>>
0
X
Default>>>
X
X
X
X
X
X
Bit 7
SDU (SCSI Disconnect Unexpected)
This bit is valid in initiator mode only. When
this bit is set, the SCSI core is not expecting
the SCSI bus to enter the Bus Free phase. If it
does, an unexpected disconnect error will be
generated (see the Unexpected Disconnect bit
in the SIST0 register, bit 2). During normal
SCRIPTS mode operation, this bit is set automatically whenever the SCSI core is reselected,
or successfully selects another SCSI device.
The SDU bit should be reset with a register
write (MOVE 0X7f & SCNTL2 TO SCNTL2)
before the SCSI core expects a disconnect to
occur, normally prior to sending an Abort,
Abort Tag, Bus Device Reset, Clear Queue or
Release Recovery message, or before deasserting SACK/ after receiving a Disconnect command or Command Complete message.
Bits 6-0 Reserved
SYM53C810A Data Manual
X
0
Bit 7
Reserved
Bits 6-4 SCF2-0 (Synchronous Clock
Conversion Factor)
These bits select the factor by which the frequency of SCLK is divided before being presented to the synchronous SCSI control logic.
The bits are encoded as per Table 5-2, “Synchronous Clock Conversion Factor,” on
page 5-10. For synchronous receive, the output
of this divider is always divided by 4 and that
value determines the transfer rate. For example, if SCLK is 40 MHz and the SCF value is
set to divide by one, then the maximum synchronous receive rate is 10 Mb/s
( 〈 40 ⁄ 1 ) ⁄ 4 = 10〉 .
For synchronous send, the output of this
divider gets divided by the transfer period
(XFERP) bits in the SCSI Transfer (SXFER)
register, and that value determines the transfer
5-9
Operating Registers
rate. For valid combinations of the SCF and
XFERP, see Table 5-4 and Table 5-5.
Table 5-2: Synchronous Clock Conversion
Factor
Table 5-3: Asynchronous Clock Conversion
Factor
CCF2
CCF1
CCF0
SCSI Clock (MHz)
SCF2
SCF1
SCF0
Factor Frequency
0
0
0
50.01-66.00
0
0
0
SCLK/3
0
0
1
16.67-25.00
0
0
1
SCLK/1
0
1
0
25.01-37.50
0
1
0
SCLK/1.5
0
1
1
37.51-50.00
0
1
1
SCLK/2
1
0
0
50.01-66.00
1
0
0
SCLK/3
1
0
1
Reserved
1
0
1
Reserved
1
1
0
Reserved
1
1
0
Reserved
1
1
1
Reserved
1
1
1
Reserved
Note: for additional information on how the
synchronous transfer rate is determined,
see “Synchronous Operation” on page 211.
Bit 3
Reserved
Bits 2-0 CCF2-0 (Clock Conversion Factor
These bits select the frequency of the SCLK
for asynchronous SCSI operations. The bits are
encoded as per the following table. All other
combinations are reserved and should never be
used.
5-10
SYM53C810A Data Manual
Operating Registers
Register 04 (84)
SCSI Chip ID (SCID)
Read/Write
Register 05 (85)
SCSI Transfer (SXFER)
Read/Write
RES
RRE
SRE
RES
RES
ENC2
ENC1
ENC0
TP2
TP1
TP0
RES
MO3
MO2
MO1
MO0
7
6
5
4
3
2
1
0
7
6
5
4
3
2
1
0
0
X
0
0
0
0
Default>>>
X
Default>>>
0
Bit 7
0
X
X
0
0
0
Reserved
Bit 6
RRE (Enable Response to
Reselection)
When this bit is set, the SYM53C810A is
enabled to respond to bus-initiated reselection
at the chip ID in the RESPID register. Note
that the SYM53C810A will not automatically
reconfigure itself to initiator mode as a result of
being reselected.
Bit 5
SRE (Enable Response to Selection)
When this bit is set, the SYM53C810A is able
to respond to bus-initiated selection at the chip
ID in the RESPID register. Note that the
SYM53C810A will not automatically reconfigure itself to target mode as a result of being
selected.
Bit 4-3
Reserved
Bits 2-0 Encoded SYM53C810A Chip SCSI
ID, bits 2-0
These bits are used to store the SYM53C810A
encoded SCSI ID. This is the ID which the
chip will assert when arbitrating for the SCSI
bus. The IDs that the SYM53C810A will
respond to when being selected or reselected
are configured in the RESPID register. The
priority of the 8 possible IDs, in descending
order is:
Highest
7
6
SYM53C810A Data Manual
Lowest
5
4
3
2
1
0
0
0
Note: when using Table Indirect I/O commands,
bits 7-0 of this register will be loaded from
the I/O data structure.
Note: for additional information on how the
synchronous transfer rate is determined,
refer to Chapter 2, “Functional
Description.”
Bits 7-5 TP2-0 (SCSI Synchronous Transfer
Period)
These bits determine the SCSI synchronous
transfer period (XFERP) used by the
SYM53C810A when sending synchronous
SCSI data in either initiator or target mode.
These bits control the programmable dividers
in the chip.
TP2
TP1
TP0
XFERP
0
0
0
4
0
0
1
5
0
1
0
6
0
1
1
7
1
0
0
8
1
0
1
9
1
1
0
10
1
1
1
11
Use the following formula to calculate the synchronous send and receive rates. Table 5-4 and
Table 5-5 show examples of possible bit combinations.
5-11
Operating Registers
Synchronous Send Rate = (SCLK/SCF)/XFERP
Synchronous Receive Rate = (SCLK/SCF) / 4
Key:
SCLK = SCLK
SCF = Synchronous Clock Conversion Factor, SCNTL3 bits
6-4
XFERP = Transfer period, SXFER register bits 7-5
Table 5-4: Examples of Synchronous Transfer Periods and Rates for SCSI-1
SCLK (MHz)
SCF (SCNTL3
bits 6-4)
XFERP (SXFER
bits 7-5)
Sync Send
Rate (MB/s)
Sync Send
Period (ns)
Sync Receive
Rate (MB/s)
Synch
Receive
Period (ns)
66.67
÷3
4
5.55
180
5.55
180
66.67
÷3
5
4.44
225
5.55
180
50
÷2
4
6.25
160
6.25
160
50
÷2
5
5
200
6.25
160
40
÷2
4
5
200
5
200
37.50
÷ 1.5
4
6.25
160
6.25
160
33.33
÷ 1.5
4
5.55
180
5.55
180
25
÷1
4
6.25
160
6.25
160
20
÷1
4
5
200
5
200
16.67
÷1
4
4.17
240
4.17
240
Table 5-5: Examples of Synchronous Transfer Periods and Rates for Fast SCSI
SCLK (MHz)
SCF (SCNTL3
bits 6-4)
XFERP (SXFER
bits 7-5)
Sync Send
Rate (MB/s)
Sync Send
Period (ns)
Sync Receive
Rate (MB/s)
Synch
Receive
Period (ns)
66.67
÷ 1.5
4
11.11
90
11.11
90
66.67
÷1
5
8.88
112.5
11.11
90
50
÷1
4
12.5
80
12.5
80
50
÷1
5
10
100
12.5
80
40
÷1
4
10
100
10
100
37.50
÷1
4
9.375
106.67
9.375
106.67
33.33
÷1
4
8.33
120
8.33
120
25
÷1
4
6.25
160
6.25
160
20
÷1
4
5
200
5
200
16.67
÷1
4
4.17
240
4.17
240
5-12
SYM53C810A Data Manual
Operating Registers
Bit 4
Reserved
Bits 3-0 MO4-MO0 (Max SCSI Synchronous
Offset)
These bits describe the maximum SCSI synchronous offset used by the SYM53C810A
when transferring synchronous SCSI data in
either initiator or target mode. The following
table describes the possible combinations and
their relationship to the synchronous data offset used by the SYM53C810A. These bits
determine the SYM53C810A’s method of
transfer for Data In and Data Out phases only;
all other information transfers will occur asynchronously.
Table 5-6: SCSI Synchronous Offset Values
MO3
MO2
MO1
MO0
Synchronous
Offset
0
0
0
0
0-Asynchronous
0
0
0
1
1
0
0
1
0
2
0
0
1
1
3
0
1
0
0
4
0
1
0
1
5
0
1
1
0
6
0
1
1
1
7
1
0
0
0
8
1
X
X
1
Reserved
1
X
1
X
Reserved
1
1
X
X
Reserved
SYM53C810A Data Manual
Register 06 (86)
SCSI Destination ID (SDID)
Read/Write
RES
RES
RES
RES
RES
ENC2
ENC1
ENC0
7
6
5
4
3
2
1
0
X
X
X
0
0
0
Default>>>
X
X
Bits 7-3 Reserved
Bits 2-0 Encoded destination SCSI ID
Writing these bits sets the SCSI ID of the
intended initiator or target during SCSI reselection or selection phases, respectively. When
executing SCRIPTS, the SCRIPTS processor
writes the destination SCSI ID to this register.
The SCSI ID is defined by the user in a
SCRIPTS SELECT or RESELECT instruction. The value written should be the binaryencoded ID value. The priority of the 8 possible IDs, in descending order, is:
Highest
7
6
Lowest
5
4
3
2
1
0
5-13
Operating Registers
Register 07 (87)
General Purpose (GPREG)
Read/Write
Register 08 (88)
SCSI First Byte Received (SFBR)
Read/Write
RES
RES
RES
RES
RES
RES
GPIO1
GPIO0
1B7
1B6
1B5
1B4
1B3
1B2
1B1
1B0
7
6
5
4
3
2
1
0
7
6
5
4
3
2
1
0
0
0
0
0
0
0
Default>>>
X
X
Default>>>
X
X
X
X
0
0
Bits 7-2 Reserved
Bits 1-0 GPIO1-GPIO0 (General Purpose)
These bits can be programmed through the
GPCNTL Register to become inputs, outputs,
or, special functions. These signals can also be
programmed as live inputs and sensed through
a SCRIPTS Register to Register Move Instruction. GPIO(1-0) default as inputs. When configured as inputs, an internal pull-up is
enabled.
The Symbios Logic SDMS software uses the
GPIO 0 pin to toggle SCSI device LEDs, turning on the LED whenever the SYM53C810A
is connected to the SCSI bus. SDMS drives
this pin low to turn on the LED, or drives it
high to turn off the LED.
The GPIO 1-0 pins are used in SDMS to
access serial NVRAM. When used for accessing serial NVRAM, GPIO 1 is used as a clock
with the GPIO 0 pin serving as data.
0
0
This register contains the first byte received in any
asynchronous information transfer phase. For example, when the SYM53C810A is operating in initiator role, this register contains the first byte
received in Message In, Status Phase, Reserved In
and Data In.
When a Block Move instruction is executed for a
particular phase, the first byte received is stored in
this register—even if the present phase is the same
as the last phase. The first byte-received value for a
particular input phase is not valid until after a
MOVE instruction is executed.
This register is also the accumulator for register
read-modify-writes with the SFBR as the destination. This allows bit testing after an operation.
The SFBR can not be written to via the CPU, and
therefore not by a Memory Move. Additionally, the
Load instruction cannot be used to write to this register. However, the SFBR can be loaded via
SCRIPTS Read/Write operations. To load the
SFBR with a byte stored in system memory, the
byte must first be moved to an intermediate
SYM53C810A register (such as the SCRATCH
register), and then to the SFBR.
This register will also contain the state of the lower
eight bits of the SCSI data bus during the selection
phase if the COM bit in the DCNTL register is
clear.
5-14
SYM53C810A Data Manual
Operating Registers
Register 09 (89)
SCSI Output Control Latch (SOCL)
Read /Write
Register 0A (8A)
SCSI Selector ID (SSID)
Read Only
REQ
ACK
BSY
SEL
ATN
MSG
C/D
I/O
VAL
RES
RES
RES
RES
ENID2
ENID1
ENID0
7
6
5
4
3
2
1
0
7
6
5
4
3
2
1
0
X
X
X
0
0
0
Default>>>
0
0
Default>>>
0
0
0
0
0
Bit 7
REQ(Assert SCSI REQ/ signal)
Bit 6
ACK(Assert SCSI ACK/ signal)
Bit 5
BSY(Assert SCSI BSY/ signal)
Bit 4
SEL(Assert SCSI SEL/ signal)
Bit 3
ATN(Assert SCSI ATN/ signal)
0
0
X
Bit 7
VAL (SCSI Valid Bit)
If VAL is asserted, the two SCSI IDs were
detected on the bus during a bus-initiated
selection or reselection, and the encoded destination SCSI ID bits below are valid. If VAL is
deasserted, only one ID was present and the
contents of the encoded destination ID are
meaningless.
Bits 6-3 Reserved
Bit 2
Bit 1
MSG(Assert SCSI MSG/ signal)
C/D(Assert SCSI C_D/ signal)
Bit 0
I/O(Assert SCSI I_O/ signal)
This register is used primarily for diagnostic testing
or programmed I/O operation. It is controlled by
the SCRIPTS processor when executing SCSI
SCRIPTS. SOCL should only be used when transferring data via programmed I/O. Some bits are set
(1) or reset (0) when executing SCSI SCRIPTS.
Do not write to the register once the
SYM53C810A starts executing normal SCSI
SCRIPTS.
SYM53C810A Data Manual
Bits 2-0 Encoded Destination SCSI ID
Reading the SSID register immediately after
the SYM53C810A has been selected or reselected returns the binary-encoded SCSI ID of
the device that performed the operation. These
bits are invalid for targets that are selected
under the single initiator option of the SCSI-1
specification. This condition can be detected
by examining the VAL bit above.
5-15
Operating Registers
Register 0B (8B)
SCSI Bus Control Lines (SBCL)
Read Only
Register 0C (8C)
DMA Status (DSTAT)
Read Only
REQ
ACK
BSY
SEL
ATN
MSG
C/D
I/O
DFE
MDPE
BF
ABRT
SSI
SIR
RES
IID
7
6
5
4
3
2
1
0
7
6
5
4
3
2
1
0
0
0
0
0
X
0
Default>>>
X
X
Default>>>
X
X
X
Bit 7
REQ (SREQ/ status)
Bit 6
ACK (SACK/ status)
Bit 5
BSY (SBSY/ status)
Bit 4
SEL (SSEL/ status)
Bit 3
ATN SATN/ status)
Bit 2
MSG (SMSG/ status)
Bit 1
C/D (SC_D/ status)
X
X
X
Bit 0
I/O (SI_O/ status)
When read, this register returns the SCSI control
line status. A bit will be set when the corresponding
SCSI control line is asserted. These bits are not
latched; they are a true representation of what is on
the SCSI bus at the time the register is read. The resulting read data is synchronized before being presented to the PCI bus to prevent parity errors from
being passed to the system. This register can be
used for diagnostics testing or operation in low level
mode.
1
0
Reading this register will clear any bits that are set
at the time the register is read, but will not necessarily clear the register because additional interrupts may be pending (the SYM53C810A stacks
interrupts). The DIP bit in the ISTAT register will
also be cleared. DMA interrupt conditions may be
individually masked through the DIEN register.
When performing consecutive 8-bit reads of the
DSTAT, SIST0 and SIST1 registers (in any order), insert a delay equivalent to 12 CLK periods
between the reads to ensure that the interrupts clear
properly. See Chapter 2, “Functional Description,”
for more information on interrupts.
Bit 7
DFE (DMA FIFO empty)
This status bit is set when the DMA FIFO is
empty. It may be used to determine if any data
resides in the FIFO when an error occurs and
an interrupt is generated. This bit is a pure status bit and will not cause an interrupt.
Bit 6
MDPE (Master Data Parity Error)
This bit is set when the SYM53C810A as a
master detects a data parity error, or a target
device signals a parity error during a data
phase. This bit is completely disabled by the
Master Parity Error Enable bit (bit 3 of
CTEST4).
Bit 5
BF (Bus fault)
This bit is set when a PCI bus fault condition
is detected. A PCI bus fault can only occur
when the SYM53C810A is bus master. A PCI
bus fault occurs when a cycle ends with a Bad
Address or Target Abort Condition.
5-16
SYM53C810A Data Manual
Operating Registers
Bit 4
ABRT (Aborted)
This bit is set when an abort condition occurs.
An abort condition occurs when a software
abort command is issued by setting bit 7 of the
ISTAT register.
Bit 3
SSI (Single step interrupt)
If the Single-Step Mode bit in the DCNTL
register is set, this bit will be set and an interrupt generated after successful execution of
each SCRIPTS instruction.
Bit 2
SIR (SCRIPTS interrupt
instruction received)
This status bit is set whenever an Interrupt
instruction is evaluated as true.
Bit 1
Reserved
Bit 0
IID (Illegal instruction detected)
This status bit is set any time an illegal instruction is detected, whether the SYM53C810A is
operating in single-step mode or automatically
executing SCSI SCRIPTS. This bit will also be
set if one of the following conditions occurs:
1. If the SYM53C810A is executing a Wait
Disconnect instruction and the SCSI REQ
line is asserted without a disconnect
occurring.
2. If a Move, Chained Move, or Memory
Move command with a byte count of zero
is fetched.
3. If a Load/Store memory address maps back
into chip register space.
SYM53C810A Data Manual
Register 0D (8D)
SCSI Status Zero (SSTAT0)
Read Only
ILF
ORF
OLF
AIP
LOA
WOA
RST
SDP0/
7
6
5
4
3
2
1
0
0
0
0
0
0
0
Default>>>
0
0
Bit 7
ILF (SIDL full)
This bit is set when the SCSI Input Data Latch
register (SIDL) contains data. Data is transferred from the SCSI bus to the SCSI Input
Data Latch register before being sent to the
DMA FIFO and then to the host bus. The
SIDL register contains SCSI data received
asynchronously. Synchronous data received
does not flow through this register.
Bit 6
ORF (SODR full)
This bit is set when the SCSI Output Data
Register (SODR, a hidden buffer register
which is not accessible) contains data. The
SODR register is used by the SCSI logic as a
second storage register when sending data synchronously. It cannot be read or written by the
user. This bit can be used to determine how
many bytes reside in the chip when an error
occurs.
Bit 5
OLF (SODL full)
This bit is set when SCSI Output Data Latch
(SODL) contains data. The SODL register is
the interface between the DMA logic and the
SCSI bus. In synchronous mode, data is transferred from the host bus to the SODL register,
and then to the SCSI Output Data Register
(SODR, a hidden buffer register which is not
accessible) before being sent to the SCSI bus.
In asynchronous mode, data is transferred
from the host bus to the SODL register, and
then to the SCSI bus. The SODR buffer register is not used for asynchronous transfers. This
bit can be used to determine how many bytes
reside in the chip when an error occurs.
5-17
Operating Registers
Bit 4
AIP (Arbitration in progress)
Arbitration in Progress (AIP = 1) indicates that
the SYM53C810A has detected a Bus Free
condition, asserted BSY, and asserted its SCSI
ID onto the SCSI bus.
Bit 3
LOA (Lost arbitration)
When set, LOA indicates that the
SYM53C810A has detected a bus free condition, arbitrated for the SCSI bus, and lost arbitration due to another SCSI device asserting
the SEL/ signal.
Register 0E (8E)
SCSI Status One (SSTAT1)
Read Only
FF3
FF2
FF1
FF0
SDP0L
MSG
C/D
I/O
7
6
5
4
3
2
1
0
0
0
X
X
X
X
Default>>>
0
0
Bits 7-4 FF3-FF0 (FIFO flags)
FF3
FF2
FF1
FF0
Bytes in the
SCSI FIFO
Bit 2
WOA (Won arbitration)
When set, WOA indicates that the
SYM53C810A has detected a Bus Free condition, arbitrated for the SCSI bus and won arbitration. The arbitration mode selected in the
SCNTL0 register must be full arbitration and
selection for this bit to be set.
0
0
0
0
0
0
0
0
1
1
0
0
1
0
2
0
0
1
1
3
0
1
0
0
4
0
1
0
1
5
Bit 1
RST/ (SCSI RST/ signal)
This bit reports the current status of the SCSI
RST/ signal, and the SRST bit (bit 6) in the
ISTAT register.
0
1
1
0
6
0
1
1
1
7
1
0
0
0
8
1
0
0
1
9
Bit 0
SDP/ (SCSI SDP/ parity signal)
This bit represents the active high current status of the SCSI SDP/ parity signal.
These four bits define the number of bytes that
currently reside in the SYM53C810A’s SCSI
synchronous data FIFO. These bits are not
latched and they will change as data moves
through the FIFO. Because the FIFO can only
hold nine bytes, values over nine will not occur.
Bit 3
SDPL (Latched SCSI parity)
This bit reflects the SCSI parity signal
(SDP/), corresponding to the data latched in
the SCSI Input Data Latch register (SIDL). It
changes when a new byte is latched into the
SIDL register. This bit is active high, in other
words, it is set when the parity signal is active.
5-18
SYM53C810A Data Manual
Operating Registers
Bit 2
MSG (SCSI MSG/ signal)
Bit 1
C/D (SCSI C_D/ signal)
Bit 0
I/O (SCSI I_O/ signal)
These SCSI phase status bits are latched on the asserting edge of SREQ/ when operating in either initiator or target mode. These bits are set when the
corresponding signal is active. They are useful
when operating in low level mode.
Register 0F (8F)
SCSI Status Two (SSTAT2)
(Read Only)
RES
RES
RES
RES
RES
RES
LDSC
RES
7
6
5
4
3
2
1
0
X
X
X
X
1
X
Default>>>
X
X
Bits 7-2 Reserved
Bit 1
LDSC (Last Disconnect)
This bit is used in conjunction with the Connected (CON) bit in SCNTL1. It allows the
user to detect the case in which a target device
disconnects, and then some SCSI device
selects or reselects the SYM53C810A. If the
Connected bit is asserted and the LDSC bit is
asserted, a disconnect has occurred. This bit is
set when the Connected bit in SCNTL1 is
clear. This bit is cleared when a Block Move
instruction executes while the Connected bit in
SCNTL1 is on.
Bit 0
SYM53C810A Data Manual
Reserved
5-19
Operating Registers
Registers 10-13 (90-93)
Data Structure Address (DSA)
Read/Write
This 32-bit register contains the base address used
for all table indirect calculations. The DSA register
is usually loaded prior to starting an I/O, but it is
possible for a SCRIPTS Memory Move to load the
DSA during the I/O.
During any Memory-to-Memory Move operation,
the contents of this register are preserved. The
power-up value of this register is indeterminate.
Register 14 (94)
Interrupt Status (ISTAT)
(Read/Write)
ABRT
SRST
SIGP
SEM
CON
INTF
SIP
DIP
7
6
5
4
3
2
1
0
0
0
0
0
0
0
Default>>>
0
0
This is the only register that can be accessed by the
host CPU while the SYM53C810A is executing
SCRIPTS (without interfering in the operation of
the SYM53C810A). It may be used to poll for interrupts if hardware interrupts are disabled. There
may be stacked interrupts pending; read this register after servicing an interrupt to check for stacked
interrupts. For more information on interrupt handling refer to Chapter 2, “Functional Description.”
Bit 7
ABRT (Abort operation)
Setting this bit aborts the current operation
being executed by the SYM53C810A. If this
bit is set and an interrupt is received, reset this
bit before reading the DSTAT register to prevent further aborted interrupts from being generated. The sequence to abort any operation is:
1. Set this bit.
2. Wait for an interrupt.
3. Read the ISTAT register.
4. If the SCSI Interrupt Pending bit is set,
then read the SIST0 or SIST1 register to
determine the cause of the SCSI Interrupt
and go back to Step 2.
5. If the SCSI Interrupt Pending bit is clear,
and the DMA Interrupt Pending bit is set,
then write 00h value to this register.
6. Read the DSTAT register to verify the
aborted interrupt and to see if any other
interrupting conditions have occurred.
Bit 6
SRST (Software reset)
Setting this bit resets the SYM53C810A. All
operating registers are cleared to their default
values and all SCSI signals are deasserted. Set-
5-20
SYM53C810A Data Manual
Operating Registers
ting this bit does not cause the SCSI RST/ signal to be asserted. This reset will not clear the
53C700 compatibility bit or any of the PCI
configuration registers. This bit is not selfclearing; it must be cleared to clear the reset
condition (a hardware reset will also clear this
bit).
Bit 5
SIGP (Signal process)
SIGP is a R/W bit that can be written at any
time, and polled and reset via CTEST2. The
SIGP bit can be used in various ways to pass a
flag to or from a running SCRIPTS instruction.
The only SCRIPTS instruction directly
affected by the SIGP bit is Wait For Selection/
Reselection. Setting this bit causes that
instruction to jump to the alternate address
immediately. The instructions at the alternate
jump address should check the status of SIGP
to determine the cause of the jump. The SIGP
bit may be used at any time and is not
restricted to the wait for selection/ reselection
condition.
Bit 4
SEM (Semaphore)
This bit can be set by the SCRIPTS processor
using a SCRIPTS register write instruction.
The bit may also be set by an external processor while the SYM53C810A is executing a
SCRIPTS operation. This bit enables the
SYM53C810A to notify an external processor
of a predefined condition while SCRIPTS are
running. The external processor may also
notify the SYM53C810A of a predefined condition and the SCRIPTS processor may take
action while SCRIPTS are executing.
SYM53C810A Data Manual
Bit 3
CON (Connected)
This bit is automatically set any time the
SYM53C810A is connected to the SCSI bus
as an initiator or as a target. It will be set after
successfully completing selection or when the
SYM53C810A has responded to a bus-initiated selection or reselection. It will also be set
after the SYM53C810A wins arbitration when
operating in low level mode. When this bit is
clear, the SYM53C810A is not connected to
the SCSI bus.
Bit 2
INTF (Interrupt on the Fly)
This bit is asserted by an INTFLY instruction
during SCRIPTS execution. SCRIPTS programs will not halt when the interrupt occurs.
This bit can be used to notify a service routine,
running on the main processor while the
SCRIPTS processor is still executing a
SCRIPTS program. If this bit is set, when the
ISTAT register is read it will not automatically
be cleared. To clear this bit, it must be written
to a one. The reset operation is self-clearing.
Note: if the INTF bit is set but SIP or DIP is not
set, do not attempt to read the other chip
status registers. An interrupt-on-the-fly
interrupt must be cleared before servicing
any other interrupts indicated by SIP or
DIP.
Note: this bit must be written to one in order to
clear it after it has been set.
5-21
Operating Registers
Bit 1
SIP (SCSI interrupt pending)
This status bit is set when an interrupt condition is detected in the SCSI portion of the
SYM53C810A. The following conditions will
cause a SCSI interrupt.
■
A phase mismatch occurs (initiator mode)
or SATN/ becomes active (target mode)
■
An arbitration sequence completes
■
A selection or reselection time-out occurs
■
The SYM53C810A was selected
■
The SYM53C810A was reselected
■
A SCSI gross error occurs
■
An unexpected disconnect occurs
■
A SCSI reset occurs
■
A parity error is detected
■
■
Register 18 (98)
Chip Test Zero (CTEST0)
Read/Write
This was a general purpose read/write register in
previous SYM53C8XX family chips. Although it is
still a read/write register, Symbios reserves the right
to use these bits for future 53C8XX family enhancements.
The handshake-to-handshake timer is
expired
The general purpose timer is expired
To determine exactly which condition(s)
caused the interrupt, read the SIST0 and
SIST1 registers.
Bit 0
DIP (DMA interrupt pending)
This status bit is set when an interrupt condition is detected in the DMA portion of the
SYM53C810A. The following conditions will
cause a DMA interrupt.
■
A PCI parity error is detected
■
A bus fault is detected
■
An abort condition is detected
■
■
■
A SCRIPTS instruction is executed in
single-step mode
A SCRIPTS interrupt instruction is
executed
An illegal instruction is detected
To determine exactly which condition(s)
caused the interrupt, read the DSTAT register.
5-22
SYM53C810A Data Manual
Operating Registers
Register 19 (99)
Chip Test One (CTEST1)
Read Only
Register 1A (9A)
Chip Test Two (CTEST2)
Read Only
FMT3
FMT2
FMT1
FMT0
FFL3
FFL2
FFL1
FFL0
DDIR
SIGP
CIO
CM
RES
TEOP
DREQ
DACK
7
6
5
4
3
2
1
0
7
6
5
4
3
2
1
0
X
X
0
0
0
1
Default>>>
1
1
Default>>>
1
1
0
0
0
0
Bits 7-4 FMT3-0 (Byte empty in DMA FIFO)
These bits identify the bottom bytes in the
DMA FIFO that are empty. Each bit corresponds to a byte lane in the DMA FIFO. For
example, if byte lane three is empty, then
FMT3 will be set. Since the FMT flags indicate the status of bytes at the bottom of the
FIFO, if all FMT bits are set, the DMA FIFO
is empty.
Bits 3-0 FFL3-0 (Byte full in DMA FIFO)
These status bits identify the top bytes in the
DMA FIFO that are full. Each bit corresponds
to a byte lane in the DMA FIFO. For example,
if byte lane three is full then FFL3 will be set.
Since the FFL flags indicate the status of bytes
at the top of the FIFO, if all FFL bits are set,
the DMA FIFO is full.
0
0
Bit 7
DDIR (Data transfer direction)
This status bit indicates which direction data is
being transferred. When this bit is set, the data
will be transferred from the SCSI bus to the
host bus. When this bit is clear, the data will be
transferred from the host bus to the SCSI bus.
Bit 6
SIGP (Signal process)
This bit is a copy of the SIGP bit in the ISTAT
register (bit 5). The SIGP bit is used to signal a
running SCRIPTS instruction. When this register is read, the SIGP bit in the ISTAT register
is cleared.
Bit 5
CIO (Configured as I/O)
This bit is defined as the Configuration I/O
Enable Status bit. This read-only bit indicates
if the chip is currently enabled as I/O space.
Note: both bits 4 and 5 may be set if the chip is
dual-mapped.
Bit 4
CM (Configured as memory)
This bit is defined as the configuration memory enable status bit. This read-only bit indicates if the chip is currently enabled as
memory space.
Note: both bits 4 and 5 may be set if the chip is
dual-mapped.
Bit 3
SYM53C810A Data Manual
Reserved
5-23
Operating Registers
Bit 2
TEOP (SCSI true end of process)
This bit indicates the status of the
SYM53C810A’s internal TEOP signal. The
TEOP signal acknowledges the completion of
a transfer through the SCSI portion of the
SYM53C810A. When this bit is set, TEOP is
active. When this bit is clear, TEOP is inactive.
Register 1B (9B)
Chip Test Three (CTEST3)
Read/Write
V3
V2
V1
V0
FLF
CLF
FM
WRIE
7
6
5
4
3
2
1
0
X
X
0
0
0
0
Default>>>
X
Bit 1
DREQ (Data request status)
This bit indicates the status of the
SYM53C810A’s internal Data Request signal
(DREQ). When this bit is set, DREQ is active.
When this bit is clear, DREQ is inactive.
Bit 0
DACK (Data acknowledge status)
This bit indicates the status of the
SYM53C810A’s internal Data Acknowledge
signal (DACK/). When this bit is set, DACK/ is
inactive. When this bit is clear, DACK/ is
active.
X
Bits 7-4 V3-V0 (Chip revision level)
These bits identify the chip revision level for
software purposes.
Bit 3
FLF (Flush DMA FIFO)
When this bit is set, data residing in the DMA
FIFO is transferred to memory, starting at the
address in the DNAD register. The internal
DMAWR signal, controlled by the CTEST5
register, determines the direction of the transfer. This bit is not self clearing; once the
SYM53C810A has successfully transferred
the data, this bit should be reset.
Note: polling of FIFO flags is allowed during
flush operations.
Bit 2
CLF (Clear DMA FIFO)
When this bit is set, all data pointers for the
DMA FIFO are cleared. Any data in the FIFO
is lost. This bit automatically resets after the
SYM53C810A has successfully cleared the
appropriate FIFO pointers and registers.
Note: this bit does not clear the data visible at the
bottom of the FIFO.
Bit 1
FM (Fetch pin mode)
When set, this bit causes the FETCH/ pin to
deassert during indirect and table indirect read
operations. FETCH/ will only be active during
the op code portion of an instruction fetch.
This allows SCRIPTS to be stored in a PROM
while data tables are stored in RAM.
If this bit is not set, FETCH/ will be asserted
for all bus cycles during instruction fetches.
5-24
SYM53C810A Data Manual
Operating Registers
Bit 0
WRIE (Write and Invalidate Enable)
This bit, when set, causes Memory Write and
Invalidate commands to be issued on the PCI
bus after certain conditions have been met.
These conditions are described in more detail
in Chapter 3.
Registers 1C-1F (9C-9F)
Temporary (TEMP)
Read/Write
This 32-bit register stores the Return instruction
address pointer from the Call instruction. The address pointer stored in this register is loaded into
the DSP register when a Return instruction is executed. This address points to the next instruction to
be executed. Do not write to this register while the
SYM53C810A is executing SCRIPTS.
During any Memory-to-Memory Move operation,
the contents of this register are preserved. The
power-up value of this register is indeterminate.
SYM53C810A Data Manual
5-25
Operating Registers
Register 20 (A0)
DMA FIFO (DFIFO)
Read/Write
Register 21 (A1)
Chip Test Four (CTEST4)
Read/Write
RES
BO6
BO5
BO4
Bo3
BO2
BO1
BO0
BDIS
ZMOD
ZSD
SRTM
MPEE
FBL2
FBL1
FBL0
7
6
5
4
3
2
1
0
7
6
5
4
3
2
1
0
0
0
0
0
0
0
Default>>>
X
0
Bit 7
Default>>>
0
0
0
0
0
0
Reserved
Bits 6-0 BO6-BO0 (Byte offset counter)
These bits indicate the amount of data transferred between the SCSI core and the DMA
core. It may be used to determine the number
of bytes in the DMA FIFO when an interrupt
occurs. These bits are unstable while data is
being transferred between the two cores; once
the chip has stopped transferring data, these
bits are stable.
Since the DFIFO register counts the number
of bytes transferred between the DMA core
and the SCSI core, and the DBC register
counts the number of bytes transferred across
the host bus, the difference between these two
counters represents the number of bytes
remaining in the DMA FIFO.
The following steps will determine how many
bytes are left in the DMA FIFO when an error
occurs, regardless of the direction of the transfer:
1. Subtract the seven least significant bits of
the DBC register from the 7-bit value of
the DFIFO register.
2. AND the result with 7Fh for a byte count
between zero and 64.
Note:
5-26
to calculate the total number of bytes in
both the DMA FIFO and SCSI logic, see
the section on Data Paths in Chapter Two,
“Functional Description.”
0
0
Bit 7
BDIS (Burst Disable)
When set, this bit will cause the
SYM53C810A to perform back to back cycles
for all transfers. When reset, the
SYM53C810A performs back to back transfers
for op code fetches and burst transfers for data
moves.The handling of op code fetches is
dependent on the setting of the Burst Op Code
Fetch bit in the DMODE register.
Bit 6
ZMOD (High impedance mode)
Setting this bit causes the SYM53C810A to
place all output and bidirectional pins into a
high-impedance state. In order to read data out
of the SYM53C810A, this bit must be cleared.
This bit is intended for board-level testing only.
Do not set this bit during normal system operation.
Bit 5
ZSD (SCSI Data High Impedance)
Setting this bit causes the SYM53C810A to
place the SCSI data bus SD(7-0) and the parity line (SDP) in a high-impedance state. In
order to transfer data on the SCSI bus, this bit
must be cleared.
Bit 4
SRTM (Shadow Register Test Mode)
Setting this bit allows access to the shadow registers used by Memory-to-Memory Move
operations. When this bit is set, register
accesses to the TEMP and DSA registers are
directed to the shadow copies STEMP
(Shadow TEMP) and SDSA (Shadow DSA).
The registers are shadowed to prevent them
from being overwritten during a Memory-toMemory Move operation. The DSA and
TEMP registers contain the base address used
SYM53C810A Data Manual
Operating Registers
for table indirect calculations, and the address
pointer for a call or return instruction, respectively. This bit is intended for manufacturing
diagnostics only and should not be set during
normal operations.
Bit 3
MPEE (Master Parity Error Enable)
Setting this bit enables parity checking during
master data phases. A parity error during a bus
master read is detected by the SYM53C810A.
A parity error during a bus master write is
detected by the target, and the SYM53C810A
is informed of the error by the PERR/ pin
being asserted by the target. When this bit is
reset, the SYM53C810A will not interrupt if a
master parity error occurs. This bit is reset at
power up.
Bits 2-0 FBL2-FBL0 (FIFO byte control)
FBL2
FBL1
FBL0
DMA FIFO
Byte lane
Pins
0
X
X
Disabled
n/a
1
0
0
0
D(7-0)
1
0
1
1
D(15-8)
1
1
0
2
D(23-16)
1
1
1
3
D(31-24)
These bits steer the contents of the CTEST6
register to the appropriate byte lane of the 32bit DMA FIFO. If the FBL2 bit is set, then
FBL1 and FBL0 determine which of four byte
lanes can be read or written. When cleared, the
byte lane read or written is determined by the
current contents of the DNAD and DBC registers. Each of the four bytes that make up the
32-bit DMA FIFO can be accessed by writing
these bits to the proper value. For normal
operation, FBL2 must equal zero.
Register 22 (A2)
Chip Test Five (CTEST5)
Read/Write
ADCK
BBCK
RES
MASR
DDIR
RES
RES
RES
7
6
5
4
3
2
1
0
X
0
0
X
X
X
Default>>>
0
0
Bit 7
ADCK (Clock address incrementor)
Setting this bit increments the address pointer
contained in the DNAD register. The DNAD
register is incremented based on the DNAD
contents and the current DBC value. This bit
automatically clears itself after incrementing
the DNAD register.
Bit 6
BBCK (Clock byte counter)
Setting this bit decrements the byte count contained in the 24-bit DBC register. It is decremented based on the DBC contents and the
current DNAD value. This bit automatically
clears itself after decrementing the DBC register.
Bit 5
Reserved
Bit 4
MASR (Master control for set or
reset pulses)
This bit controls the operation of bit 3. When
this bit is set, bit 3 asserts the corresponding
signals. When this bit is reset, bit 3 deasserts
the corresponding signals. This bit and bit 3
should not be changed in the same write cycle.
Bit 3
DDIR (DMA direction)
Setting this bit either asserts or deasserts the
internal DMA Write (DMAWR) direction signal depending on the current status of the
MASR bit in this register. Asserting the
DMAWR signal indicates that data will be
transferred from the SCSI bus to the host bus.
Deasserting the DMAWR signal transfers data
from the host bus to the SCSI bus.
Bits 2-0 Reserved
SYM53C810A Data Manual
5-27
Operating Registers
Register 23 (A3)
Chip Test Six (CTEST6)
Read/Write
Registers 24-26 (A4-A6)
DMA Byte Counter (DBC)
Read/Write
DF7
DF6
DF5
DF4
DF3
DF2
DF1
DF0
7
6
5
4
3
2
1
0
0
0
0
0
0
0
Default>>>
0
0
Bits 7-0 DF7-DF0 (DMA FIFO)
Writing to this register writes data to the
appropriate byte lane of the DMA FIFO as
determined by the FBL bits in the CTEST4
register. Reading this register unloads data
from the appropriate byte lane of the DMA
FIFO as determined by the FBL bits in the
CTEST4 register. Data written to the FIFO is
loaded into the top of the FIFO. Data read out
of the FIFO is taken from the bottom. To prevent DMA data from being corrupted, this register should not be accessed before starting or
restarting SCRIPTS operation. This register
should only be written when testing the DMA
FIFO using the CTEST4 register. Writes to
this register while the test mode is not enabled
will have unexpected results.
5-28
This 24-bit register determines the number of bytes
to be transferred in a Block Move instruction.
While sending data to the SCSI bus, the counter is
decremented as data is moved into the DMA FIFO
from memory. While receiving data from the SCSI
bus, the counter is decremented as data is written
to memory from the SYM53C810A. The DBC
counter is decremented each time that data is transferred on the PCI bus. It is decremented by an
amount equal to the number of bytes that were
transferred.
The maximum number of bytes that can be transferred in any one Block Move command is
16,777,215 bytes. The maximum value that can be
loaded into the DBC register is FFFFFFh. If the
instruction is a Block Move and a value of 000000h
is loaded into the DBC register, an illegal instruction interrupt will occur if the SYM53C810A is not
in target role, Command phase.
The DBC register is also used to hold the least significant 24 bits of the first dword of a SCRIPTS
fetch, and to hold the offset value during table indirect I/O SCRIPTS. For a complete description, see
Chapter Six, “Instruction Set of the I/O Processor.” The power-up value of this register is indeterminate.
SYM53C810A Data Manual
Operating Registers
Register 27 (A7)
DMA Command (DCMD)
Read/Write
Registers 28-2B (A8-AB)
DMA Next Address (DNAD)
Read/Write
This 8-bit register determines the instruction for
the SYM53C810A to execute. This register has a
different format for each instruction. For a complete description, see Chapter Six, “Instruction Set
of the I/O Processor.”
This 32-bit register contains the general purpose
address pointer. At the start of some SCRIPTS operations, its value is copied from the DSPS register.
Its value may not be valid except in certain abort
conditions. The default value of this register is zero.
SYM53C810A Data Manual
5-29
Operating Registers
Registers 2C-2F (AC-AF)
DMA SCRIPTS Pointer (DSP)
Read/Write
Registers 30-33 (B0-B3)
DMA SCRIPTS Pointer Save (DSPS)
Read/Write
The CPU writes the address of the first SCRIPTS
instruction to this register to begin SCSI SCRIPTS
operation. In normal SCRIPTS operation, once the
starting address of the first SCRIPTS instruction is
written to this register, SCRIPTS instructions are
automatically fetched and executed until an interrupt condition occurs.
This register contains the second dword of a
SCRIPTS instruction. It is overwritten each time a
SCRIPTS instruction is fetched. When a
SCRIPTS interrupt instruction is executed, this
register holds the interrupt vector. The power-up
value of this register is indeterminate.
In single-step mode, there is a single step interrupt
after each instruction is executed. The DSP register
does not need to be written with the next address,
but the Start DMA bit (bit 2, DCNTL register)
must be set each time the step interrupt occurs to
fetch and execute the next SCRIPTS command.
When writing this register eight bits at a time, writing the upper eight bits begins execution of the
SCSI SCRIPTS. The default value of this register
is zero.
5-30
SYM53C810A Data Manual
Operating Registers
Registers 34-37 (B4-B7)
Scratch Register A (SCRATCH A)
Read/Write
This is a general purpose, user-definable scratch
pad register. Apart from CPU access, only Register
Read/Write and Memory Moves into the
SCRATCH register will alter its contents. The
power-up value of this register is indeterminate.
The SYM53C810A cannot fetch SCRIPTS instructions from this location.
Register 38 (B8)
DMA Mode (DMODE)
Read/Write
BL1
BL0
SIOM
DIOM
ERL
ERMP
BOF
MAN
7
6
5
4
3
2
1
0
0
0
0
0
0
0
Default>>>
0
0
Bit 7-6
BL1-BL0 (Burst length)
BL1
BL0
Burst Length
0
0
2- transfer burst
0
1
4- transfer burst
1
0
8-transfer burst
1
1
16-transfer burst
These bits control the maximum number of
transfers performed per bus ownership, regardless of whether the transfers are back-to-back,
burst, or a combination of both. The
SYM53C810A asserts the Bus Request (REQ/
) output when the DMA FIFO can accommodate a transfer of at least one burst size of data.
Bus Request (REQ/) is also asserted during
start-of-transfer and end-of-transfer cleanup
and alignment, even though less than a full
burst of transfers may be performed. The
SYM53C810A inserts a “fairness delay” of
four CLKs between burst-length transfers (as
set in BL1-0) during normal operation. The
fairness delay is not inserted during PCI retry
cycles. This gives the CPU and other bus master devices the opportunity to access the PCI
bus between bursts.
Bit 5
SIOM (Source I/O-Memory Enable)
This bit is defined as an I/O Memory Enable
bit for the source address of a Memory Move
or Block Move Command. If this bit is set,
then the source address is in I/O space; and if
reset, then the source address is in memory
space.
SYM53C810A Data Manual
5-31
Operating Registers
This function is useful for register-to-memory
operations using the Memory Move instruction when the SYM53C810A is I/O mapped.
Bits 4 and 5 of the CTEST2 register can be
used to determine the configuration status of
the SYM53C810A.
Bit 4
DIOM (Destination I/O-Memory
Enable)
This bit is defined as an I/O Memory Enable
bit for the destination address of a Memory
Move or Block Move Command. If this bit is
set, then the destination address is in I/O
space; and if reset, then the destination address
is in memory space.
This function is useful for memory–to–register
operations using the Memory Move instruction when the SYM53C810A is I/O mapped.
Bits 4 and 5 of the CTEST2 register can be
used to determine the configuration status of
the SYM53C810A.
accessed in a subsequent bus ownership. If the
instruction is a table indirect block move type,
the chip will access the remaining two dwords
in a subsequent bus ownership, thereby fetching the four dwords required in two bursts of
two dwords each.
Bit 0
MAN (Manual Start Mode)
Setting this bit prevents the SYM53C810A
from automatically fetching and executing
SCSI SCRIPTS when the DSP register is written. When this bit is set, the Start DMA bit in
the DCNTL register must be set to begin
SCRIPTS execution. Clearing this bit causes
the SYM53C810A to automatically begin
fetching and executing SCSI SCRIPTS when
the DSP register is written. This bit is not normally used for SCSI SCRIPTS operations.
Bit 3
ERL (Enable Read Line)
This bit enables a PCI Read Line command. If
PCI cache mode is enabled by setting bits in
the PCI Cache Line Size register, the chip
issues a Read Line command on all read cycles
if other conditions are met. For more information on these conditions, refer to Chapter 3.
ERMP (Enable Read Multiple)
This bit, when set, will cause Read Multiple
commands to be issued on the PCI bus after
certain conditions have been met. These conditions are described in Chapter 3.
Bit 1
BOF (Burst Op Code Fetch Enable)
Setting this bit causes the SYM53C810A to
fetch instructions in burst mode, if the Burst
Disable bit (CTEST4, bit7) is cleared. Specifically, the chip will burst in the first two dwords
of all instructions using a single bus ownership.
If the instruction is a memory-to-memory
move type, the third dword will be accessed in
a subsequent bus ownership. If the instruction
is an indirect type, the additional dword will be
5-32
SYM53C810A Data Manual
Operating Registers
Register 39 (B9)
DMA Interrupt Enable (DIEN)
Read/Write
Register 3A (BA)
Scratch Byte Register (SBR)
Read/Write
RES
MDPE
BF
ABRT
SSI
SIR
RES
IID
7
6
5
4
3
2
1
0
0
0
0
0
X
0
Default>>>
X
0
This register contains the interrupt mask bits corresponding to the interrupting conditions described
in the DSTAT register. An interrupt is masked by
clearing the appropriate mask bit. Masking an interrupt prevents IRQ/ from being asserted for the
corresponding interrupt, but the status bit will still
be set in the DSTAT register. Masking an interrupt
will not prevent the ISTAT DIP from being set. All
DMA interrupts are considered fatal, therefore
SCRIPTS will stop running when a DMA interrupt
occurs, whether or not the interrupt is masked. Setting a mask bit enables the assertion of IRQ/ for the
corresponding interrupt. (A masked non-fatal interrupt will not prevent un-masked or fatal interrupts from getting through; interrupt stacking
begins when either the ISTAT SIP or DIP bit is
set.)
This is a general purpose register. Apart from CPU
access, only Register Read/Write and Memory
Moves into this register will alter its contents. The
default value of this register is zero. This register
was called the DMA Watchdog Timer on previous
SYM53C8XX family products.
The SYM53C810A IRQ/ output is latched; once
asserted, it will remain asserted until the interrupt
is cleared by reading the appropriate status register.
Masking an interrupt after the IRQ/ output is asserted will not cause IRQ/ to be deasserted.
For more information on interrupts, see Chapter
Two, “Functional Description.”
Bit 7
Reserved
Bit 6
MDPE (Master Data Parity Error)
Bit 5
BF (Bus fault)
Bit 4
ABRT (Aborted)
Bit 3
SSI (Single step interrupt)
Bit 2
SIR (SCRIPTS interrupt
instruction received
Bit 1
Reserved
Bit 0
IID (Illegal instruction detected)
SYM53C810A Data Manual
5-33
Operating Registers
Register 3B (BB)
DMA Control (DCNTL)
Read/Write
CLSE
PFF
PFEN
SSM
IRQM
STD
IRQD
COM
7
6
5
4
3
2
1
0
0
0
0
0
0
0
Default>>>
0
0
Bit 7
CLSE (Cache Line Size Enable)
Setting this bit enables the SYM53C810A to
sense and react to cache line boundaries set up
by the DMODE or PCI Cache Line Size register, whichever contains the smaller value.
Clearing this bit disables the cache line size
logic and the SYM53C810A monitors the
cache line size via the DMODE register.
Bit 6
PFF (Pre-Fetch Flush)
Setting this bit will cause the pre-fetch unit to
flush its contents. The bit will reset after the
flush is complete.
Bit 5
PFEN (Pre-fetch Enable)
Setting this bit enables the pre-fetch unit if the
burst size is equal to or greater than four. For
more information on SCRIPTS instruction
prefetching, see Chapter 2.
Bit 4
SSM (Single-step mode)
Setting this bit causes the SYM53C810A to
stop after executing each SCRIPTS instruction, and generate a single step interrupt.
When this bit is clear the SYM53C810A will
not stop after each instruction; instead it continues fetching and executing instructions until
an interrupt condition occurs. This bit should
be clear for normal SCSI SCRIPTS operation.
To restart the SYM53C810A after it generates
a SCRIPTS Step interrupt, read the ISTAT
and DSTAT registers to recognize and clear
the interrupt; then set the START DMA bit in
this register.
5-34
Bit 3
IRQM (IRQ Mode)
When set, this bit enables a totem pole driver
for the IRQ pin. When reset, this bit enables an
open drain driver for the IRQ pin with a internal weak pull-up. This bit is reset at power up.
Bit 2
STD (Start DMA operation)
The SYM53C810A fetches a SCSI SCRIPTS
instruction from the address contained in the
DSP register when this bit is set. This bit is
required if the SYM53C810A is in one of the
following modes:
1. Manual start mode – Bit 0 in the DMODE
register is set
2. Single-step mode – Bit 4 in the DCNTL
register is set
When the SYM53C810A is executing
SCRIPTS in manual start mode, the Start
DMA bit needs to be set to start instruction
fetches. This bit will remain set until an interrupt occurs. When the SYM53C810A is in single-step mode, the Start DMA bit needs to be
set to restart execution of SCRIPTS after a single-step interrupt.
Bit 1
IRQD (IRQ Disable)
Setting this bit tristates the IRQ pin; clearing
the bit enables normal operation. When bit 1 in
this register is set, the IRQ/ pin will not be
asserted when an interrupt condition occurs.
The interrupt is not lost or ignored, but merely
masked at the pin. Clearing this bit when an
interrupt is pending will immediately cause the
IRQ/ pin to assert. As with any register other
than ISTAT, this register cannot be accessed
except by a SCRIPTS instruction during
SCRIPTS execution.
SYM53C810A Data Manual
Operating Registers
Bit 0
COM (53C700 compatibility)
When this bit is clear, the SYM53C810A will
behave in a manner compatible with the
SYM53C700; selection/reselection IDs will be
stored in both the SSID and SFBR registers.
When this bit is set, the ID will be stored only
in the SSID register, protecting the SFBR from
being overwritten if a selection/reselection
occurs during a DMA register-to-register operation.
Register 3C-3F (BC-BF)
Adder Sum Output (ADDER)
Read Only
This register contains the output of the internal
adder, and is used primarily for test purposes. The
power-up value for this register is indeterminate.
This bit is not affected by a software reset.
SYM53C810A Data Manual
5-35
Operating Registers
Register 40 (C0)
SCSI Interrupt Enable Zero (SIEN0)
Read/Write
M/A
CMP
SEL
RSL
SGE
UDC
RST
PAR
7
6
5
4
3
2
1
0
0
0
0
0
0
0
Bit 4
RSL (Reselected)
This bit controls whether an interrupt occurs
when the SYM53C810A has been reselected
by a SCSI initiator device. The Enable
Response to Reselection bit in the SCID register must be set for this to occur.
Default>>>
0
0
This register contains the interrupt mask bits that
correspond to the interrupting conditions described
in the SIST0 register. An interrupt is masked by
clearing the appropriate mask bit. For more information on interrupts, see Chapter 2.
Bit 7
M/A (SCSI Phase Mismatch Initiator Mode; SCSI ATN
Condition - Target Mode)
In initiator mode, this bit controls whether an
interrupt occurs when the SCSI phase asserted
by the target and sampled during SREQ/ does
not match the expected phase in the SOCL
register. This expected phase is automatically
written by the SCSI SCRIPTS program. In
target mode, this bit is set when the initiator
has asserted SATN/. See the Disable Halt on
Parity Error or SATN/ Condition bit in the
SCNTL1 register for more information on
when this status is actually raised.
Bit 6
CMP (Function Complete)
This bit controls whether an interrupt occurs
when full arbitration and selection sequence
has completed.
Bit 5
SEL (Selected)
This bit controls whether an interrupt occurs
when the SYM53C810A has been selected by
a SCSI target device. The Enable Response to
Selection bit in the SCID register must be set
for this to occur.
5-36
Bit 3
SGE (SCSI Gross Error)
This bit controls whether an interrupt occurs
when the SYM53C810A detects a SCSI Gross
Error. The following conditions are considered
SCSI Gross Errors:
1. Data underflow - the SCSI FIFO was read
when no data was present.
2. Data overflow - the SCSI FIFO was
written to while full.
3. Offset underflow - in target mode, a
SACK/ pulse was received before the
corresponding SREQ/ was sent.
4. Offset overflow - in initiator mode, an
SREQ/ pulse was received which caused
the maximum offset (Defined by the
MO3-0 bits in the SXFER register) to be
exceeded.
5. In initiator mode, a phase change occurred
with an outstanding SREQ/SACK offset.
6. Residual data in SCSI FIFO - a transfer
other than synchronous data receive was
started with data left in the SCSI
synchronous receive FIFO.
Bit 2
UDC (Unexpected Disconnect)
This bit controls whether an interrupt occurs
in the case of an unexpected disconnect. This
condition only occurs in initiator mode. It happens when the target to which the
SYM53C810A is connected disconnects from
the SCSI bus unexpectedly. See the SCSI Disconnect Unexpected bit in the SCNTL2 register for more information on expected versus
unexpected disconnects. Any disconnect in low
level mode causes this condition.
SYM53C810A Data Manual
Operating Registers
Bit 1
RST (SCSI Reset Condition)
This bit controls whether an interrupt occurs
when the SRST/ signal has been asserted by
the SYM53C810A or any other SCSI device.
Note that this condition is edge-triggered, so
that multiple interrupts cannot occur because
of a single SRST/ pulse.
Register 41 (C1)
SCSI Interrupt Enable One (SIEN1)
Read/Write
RES
RES
RES
RES
RES
STO
GEN
HTH
7
6
5
4
3
2
1
0
X
X
X
0
0
0
Default>>>
X
Bit 0
PAR (SCSI Parity Error)
This bit controls whether an interrupt occurs
when the SYM53C810A detects a parity error
while receiving or sending SCSI data. See the
Disable Halt on Parity Error or SATN/ Condition bits in the SCNTL1 register for more
information on when this condition will actually be raised.
X
This register contains the interrupt mask bits corresponding to the interrupting conditions described
in the SIST1 register. An interrupt is masked by
clearing the appropriate mask bit. For more information on interrupts, refer to Chapter 2, “Functional Description.”
Bits 7-3 Reserved
Bit 2
STO (Selection or Reselection Timeout)
This bit controls whether an interrupt occurs
when the SCSI device which the
SYM53C810A was attempting to select or
reselect did not respond within the programmed time-out period. See the description
of the STIME0 register bits 3-0 for more information on the time-out timer.
Bit 1
GEN (General Purpose Timer
Expired)
This bit controls whether an interrupt occurs
when the general purpose timer has expired.
The time measured is the time between
enabling and disabling of the timer. See the
description of the STIME1 register, bits 3-0,
for more information on the general purpose
timer.
SYM53C810A Data Manual
5-37
Operating Registers
Bit 0
HTH (Handshake to Handshake
timer Expired)
This bit controls whether an interrupt occurs
when the handshake-to-handshake timer has
expired. The time measured is the SCSI
Request to Request (target) or Acknowledge to
Acknowledge (initiator) period. See the
description of the STIME0 register, bits 7-4,
for more information on the handshake-tohandshake timer.
Register 42 (C2)
SCSI Interrupt Status Zero (SIST0)
Read Only
M/A
CMP
SEL
RSL
SGE
UDC
RST
PAR
7
6
5
4
3
2
1
0
0
0
0
0
0
0
Default>>>
0
0
Reading the SIST0 register returns the status of the
various interrupt conditions, whether or not they
are enabled in the SIEN0 register. Each bit set indicates that the corresponding condition has occurred. Reading the SIST0 will clear the interrupt
status.
Reading this register will clear any bits that are set
at the time the register is read, but will not necessarily clear the register because additional interrupts may be pending (the SYM53C810A stacks
interrupts). SCSI interrupt conditions may be individually masked through the SIEN0 register.
When performing consecutive 8-bit reads of the
DSTAT, SIST0, and SIST1 registers (in any order), insert a delay equivalent to 12 CLK periods
between the reads to ensure the interrupts clear
properly. Also, if reading the registers when both
the ISTAT SIP and DIP bits may not be set, the
SIST0 and SIST1 registers should be read before
the DSTAT register to avoid missing a SCSI interrupt. For more information on interrupts, refer to
Chapter 2, “Functional Description.”
Bit 7
M/A (Initiator Mode: Phase Mismatch; Target Mode: SATN/ Active)
In initiator mode, this bit is set if the SCSI
phase asserted by the target does not match the
instruction. The phase is sampled when SREQ/
is asserted by the target. In target mode, this
bit is set when the SATN/ signal is asserted by
the initiator.
Bit 6
CMP (Function Complete)
This bit is set when an arbitration only or full
arbitration sequence has completed.
5-38
SYM53C810A Data Manual
Operating Registers
Bit 5
SEL (Selected)
This bit is set when the SYM53C810A is
selected by another SCSI device. The Enable
Response to Selection bit must have been set in
the SCID register (and the RESPID register
must hold the chip’s ID) for the
SYM53C810A to respond to selection
attempts.
Bit 4
RSL (Reselected)
This bit is set when the SYM53C810A is reselected by another SCSI device. The Enable
Response to Reselection bit must have been set
in the SCID register (and the RESPID register
must hold the chip’s ID) for the
SYM53C810A to respond to reselection
attempts.
Bit 3
SGE (SCSI Gross Error)
This bit is set when the SYM53C810A
encounters a SCSI Gross Error Condition.
The following conditions can result in a SCSI
Gross Error Condition:
1. Data Underflow - the SCSI FIFO register
was read when no data was present.
2. Data Overflow - too many bytes were
written to the SCSI FIFO or the
synchronous offset caused the SCSI FIFO
to be overwritten.
3. Offset Underflow - the SYM53C810A is
operating in target mode and a SACK/
pulse is received when the outstanding
offset is zero.
4. Offset Overflow - the other SCSI device
sent a SREQ/ or SACK/ pulse with data
which exceeded the maximum
synchronous offset defined by the SXFER
register.
6. Residual data in the Synchronous data
FIFO - a transfer other than synchronous
data receive was started with data left in the
synchronous data FIFO.
Bit 2
UDC (Unexpected Disconnect)
This bit is set when the SYM53C810A is operating in initiator mode and the target device
unexpectedly disconnects from the SCSI bus.
This bit is only valid when the SYM53C810A
operates in the initiator mode. When the
SYM53C810A operates in low level mode, any
disconnect will cause an interrupt, even a valid
SCSI disconnect. This bit will also be set if a
selection time-out occurs (it may occur before,
at the same time, or stacked after the STO
interrupt, since this is not considered an
expected disconnect).
Bit 1
RST (SCSI RST/ Received)
This bit is set when the SYM53C810A detects
an active SRST/ signal, whether the reset was
generated external to the chip or caused by the
Assert SRST/ bit in the SCNTL1 register. This
SYM53C810A SCSI reset detection logic is
edge-sensitive, so that multiple interrupts will
not be generated for a single assertion of the
SRST/ signal.
Bit 0
PAR (Parity Error)
This bit is set when the SYM53C810A detects
a parity error while receiving SCSI data. The
Enable Parity Checking bit (bit 3 in the
SCNTL0 register) must be set for this bit to
become active. The SYM53C810A always generates parity when sending SCSI data.
5. A phase change occurred with an
outstanding synchronous offset when the
SYM53C810A was operating as an
initiator.
SYM53C810A Data Manual
5-39
Operating Registers
Register 43 (C3)
SCSI Interrupt Status One (SIST1)
Read Only
Register 44 (C4)
SCSI Longitudinal Parity (SLPAR)
Read/Write
RES
RES
RES
RES
RES
STO
GEN
HTH
7
6
5
4
3
2
1
0
X
X
X
0
0
0
Default>>>
X
X
Reading the SIST1 register returns the status of the
various interrupt conditions, whether or not they
are enabled in the SIEN1 register. Each bit that is
set indicates the corresponding condition has occurred.
This register performs a bytewise longitudinal parity check on all SCSI data received or sent through
the SCSI core. If one of the bytes received or sent
(usually the last) is the set of correct even parity
bits, SLPAR should go to zero (assuming it started
at zero). As an example, suppose that the following
three data bytes and one check byte are received
from the SCSI bus (all signals are shown active
high):
Reading the SIST1 register will clear the interrupt
condition.
Bits 7-3 Reserved
Bit 2
STO (Selection or Reselection
Time-out)
This bit is set when the SCSI device which the
SYM53C810A53C810A was attempting to
select or reselect did not respond within the
programmed time-out period. See the description of the STIME0 register, bits 3-0, for more
information on the time-out timer.
Bit 1
GEN (General Purpose Timer
Expired)
This bit is set when the general purpose timer
has expired. The time measured is the time
between enabling and disabling of the timer.
See the description of the STIME1 register,
bits 3-0, for more information on the general
purpose timer.
Bit 0
HTH (Handshake-to-Handshake
Timer Expired)
This bit is set when the handshake-to-handshake timer has expired. The time measured is
the SCSI Request to Request (target) or
Acknowledge to Acknowledge (initiator)
period. See the description of the STIME0
register, bits 7-4, for more information on the
handshake-to-handshake timer.
5-40
Data Bytes
Running SLPAR
---
00000000
1. 11001100
11001100 (XOR of word 1)
2. 01010101
10011001 (XOR of word 1 and 2)
3. 00001111
10010110 (XOR of word 1, 2 and 3)
Even Parity >>>10010110
4. 10010110
00000000
A one in any bit position of the final SLPAR value
would indicate a transmission error.
The SLPAR register can also be used to generate
the check bytes for SCSI send operations. If the
SLPAR register contains all zeros prior to sending
a block move, it will contain the appropriate check
byte at the end of the block move. This byte must
then be sent across the SCSI bus.
Note: writing any value to this register resets it to
zero.
The longitudinal parity checks are meant to provide
an added measure of SCSI data integrity and are
entirely optional. This register does not latch SCSI
selection/reselection IDs under any circumstances.
The default value of this register is zero.
SYM53C810A Data Manual
Operating Registers
Register 46 (C6)
Memory Access Control (MACNTL)
Read/Write
Register 47 (C7)
General Purpose Pin Control (GPCNTL)
Read/Write
TYP3
TYP2
TYP1
TYP0
DWR
DRD
PSCPT
SCPTS
ME
FE
RES
RES
RES
RES
GPIO1
GPIO0
7
6
5
4
3
2
1
0
7
6
5
4
3
2
1
0
X
0
1
1
1
1
Default>>>
0
1
Default>>>
0
0
0
0
0
0
Bits 7-4 TYP3-0 (Chip Type)
These bits identify the chip type for software
purposes.
Bits 3 through 0 of this register are used to determine if an external bus master access is to local or
far memory. When bits 3 through 0 are set, the corresponding access is considered local and the
MAC/_TESTOUT pin is driven high. When these
bits are clear, the corresponding access is to far
memory and the MAC/_TESTOUT pin is driven
low. This function is enabled after a Transfer Control SCRIPTS instruction is executed.
Bit 3
DWR (DataWR)
This bit is used to define if a data write is considered local memory access.
0
This register is used to determine if the pins controlled by the General Purpose register (GPREG)
are inputs or outputs. Bits 1-0 in GPCNTL correspond to bits 1-0 in the GPREG register. When the
bits are enabled as inputs, an internal pull-up is also
enabled.
Bit 7
Master Enable
The internal bus master signal will be presented on GPIO1 if this bit is set, regardless of
the state of Bit 1 (GPIO1_EN).
Bit 6
Fetch Enable
The internal op code fetch signal will be presented on GPIO0 if this bit is set, regardless of
the state of Bit 0 (GPIO0_EN).
Bit 5
Bit 2
DRD (DataRD)
This bit is used to define if a data read is considered local memory access.
Bit 1
PSCPT (Pointer SCRIPTS)
This bit is used to define if a pointer to a
SCRIPTS indirect or table indirect fetch is
considered local memory access.
0
Reserved
Bits 1-0 GPIO1_EN– GPIO0_EN (GPIO
Enable)
These bits power up set, causing the GPIO1
and GPIO0 pins to become inputs. Resetting
these bits causes GPIO1-0 to become outputs.
Bit 0
SCPTS (SCRIPTS)
This bit is used to define if a SCRIPTS fetch is
considered local memory access.
SYM53C810A Data Manual
5-41
Operating Registers
Register 48 (C8)
SCSI Timer Zero (STIME0)
Read /Write
HTH 7-4, SEL 3-0,
GEN 3-0
HTH
HTH
HTH
HRH
SEL
SEL
SEL
SEL
7
6
5
4
3
2
1
0
0
0
0
0
0
0
Default>>>
0
0
Bits 7-4 HTH (Handshake-to-Handshake
Timer Period)
These bits select the handshake-to-handshake
time-out period, the maximum time between
SCSI handshakes (SREQ/ to SREQ/ in target
mode, or SACK/ to SACK/ in initiator mode).
When this timing is exceeded, an interrupt is
generated and the HTH bit in the SIST1 register is set. The following table contains time-out
periods for the Handshake-to-Handshake
Timer, the Selection/Reselection Timer (bits 30), and the General Purpose Timer (STIME1
bits 3-0). For a more detailed explanation of
interrupts, refer to Chapter 2, “Functional
Description.”
Minimum Time-out
40 MHz
50 MHz
0000
Disabled
Disabled
0001
125 µs
100 µs
0010
250 µs
200 µs
0011
500 µs
400 µs
0100
1 ms
800 µs
0101
2 ms
1.6 ms
0110
4 ms
3.2 ms
0111
8 ms
6.4 ms
1000
16 ms
12.8 ms
1001
32 ms
25.6 ms
1010
64 ms
51.2 ms
1011
128 ms
102.4 ms
1100
256 ms
204.8 ms
1101
512 ms
409.6 ms
1110
1.024 sec
819.2 ms
1111
2.048 sec
1.6384 sec
These values will be correct if the CCF bits in the SCNTL3
register are set according to the valid combinations in the bit
description.
Bits 3-0 SEL (Selection Time-Out)
These bits select the SCSI selection/reselection
time-out period. When this timing (plus the
200 µs selection abort time) is exceeded, the
STO bit in the SIST1 register is set. For a
more detailed explanation of interrupts, refer
to Chapter 2, “Functional Description.”
5-42
SYM53C810A Data Manual
Operating Registers
Register 49 (C9)
SCSI Timer One (STIME1)
Read/Write
Register 4A (CA)
Response ID (RESPID)
Read/Write
RES
RES
RES
RES
GEN3
GEN2
GEN1
GEN0
7
6
5
4
3
2
1
0
X
X
0
0
0
0
Default>>>
X
X
Bits 7-4 Reserved
Bits 3-0 GEN3-0 (General Purpose Timer
Period)
These bits select the period of the general purpose timer. The time measured is the time
between enabling and disabling of the timer.
When this timing is exceeded, the GEN bit in
the SIST1 register is set. Refer to the table
under STIME0, bits 3-0, for the available
time-out periods.
This register contains the IDs that the chip responds to on the SCSI bus. Each bit represents one
possible ID with the most significant bit representing ID 7 and the least significant bit representing
ID 0. The SCID register still contains the chip ID
used during arbitration. The chip can respond to
more than one ID because more than one bit can be
set in the RESPID register. However, the chip can
arbitrate with only one ID value in the SCID register.
Note: to reset a timer before it has expired and to
obtain repeatable delays, the time value
must be written to zero first, and then
written back to the desired value. This is
also required when changing from one time
value to another. See Chapter 2,
“Functional Description,” for an
explanation of how interrupts are
generated when the timers expire.
SYM53C810A Data Manual
5-43
Operating Registers
Bit 1
Register 4C (CC)
SCSI Test Zero (STEST0)
Read Only
RES
SSAID
2
SSAID
1
SSAID
0
SLT
ART
SOZ
SOM
7
6
5
4
3
2
1
0
X
X
0
X
1
1
Default>>>
X
X
Bit 7
Reserved
Bits 6-4 SSAID (SCSI Selected As ID)
These bits contain the encoded value of the
SCSI ID that the SYM53C810A was selected
or reselected as during a SCSI selection or
reselection phase. These bits are read only and
contain the encoded value of 0-7 possible IDs
that could be used to select the
SYM53C810A. During a SCSI selection or
reselection phase when a valid ID has been put
on the bus, and the 53C810A responds to that
ID, the “selected as” ID is written into these
bits.
SOZ (SCSI Synchronous Offset
Zero)
This bit indicates that the current synchronous
SREQ/SACK offset is zero. This bit is not
latched and may change at any time. It is used
in low level synchronous SCSI operations.
When this bit is set, the SYM53C810A, as an
initiator, is waiting for the target to request
data transfers. If the SYM53C810A is a target,
then the initiator has sent the offset number of
acknowledges.
Bit 0
SOM (SCSI Synchronous Offset
Maximum)
This bit indicates that the current synchronous
SREQ/SACK offset is the maximum specified
by bits 3-0 in the SCSI Transfer register. This
bit is not latched and may change at any time.
It is used in low level synchronous SCSI operations. When this bit is set, the SYM53C810A,
as a target, is waiting for the initiator to
acknowledge the data transfers. If the
SYM53C810A is an initiator, then the target
has sent the offset number of requests.
Bit 3
SLT (Selection response logic test)
This bit is set when the SYM53C810A is ready
to be selected or reselected. This does not take
into account the bus settle delay of 400 ns.
This bit is used for functional test and fault
purposes.
Bit 2
ART (Arbitration Priority Encoder
Test)
This bit will always be set when the
SYM53C810A exhibits the highest priority ID
asserted on the SCSI bus during arbitration. It
is primarily used for chip level testing, but it
may be used during low level mode operation
to determine if the SYM53C810A has won
arbitration.
5-44
SYM53C810A Data Manual
Operating Registers
Register 4D (CD)
SCSI Test One (STEST1)
Read/Write
Register 4E (CE)
SCSI Test Two (STEST2)
Read/Write
SCLK
SISO
RES
RES
RES
RES
RES
RES
SCE
ROF
RES
SLB
SZM
RES
EXT
LOW
7
6
5
4
3
2
1
0
7
6
5
4
3
2
1
0
X
0
0
X
0
0
Default>>>
0
0
Default>>>
X
X
X
X
X
X
Bit 7
SCLK
This bit, when set, disables the external SCLK
(SCSI Clock) pin, and causes the chip to use
the PCI clock as the internal SCSI clock. If a
transfer rate of 10 MB/s is to be achieved on
the SCSI bus, this bit must be cleared and the
chip must be connected to at least a 40 MHz
external SCLK.
Bit 6
SISO (SCSI Isolation Mode)
This bit allows the SYM53C810A to put the
SCSI bi-directional and input pins into a low
power mode when the SCSI bus is not in use.
When this bit is set, the SCSI bus inputs are
logically isolated from the SCSI bus.
Bits 5-0 Reserved
0
0
Bit 7
SCE (SCSI Control Enable)
This bit, when set, allows all SCSI control and
data lines to be asserted through the SOCL
and SODL registers regardless of whether the
SYM53C810A is configured as a target or initiator.
Note: this bit should not be set during normal
operation, since it could cause contention
on the SCSI bus. It is included for
diagnostic purposes only.
Bit 6
ROF (Reset SCSI Offset)
Setting this bit clears any outstanding synchronous SREQ/SACK offset. This bit should be
set if a SCSI gross error condition occurs, to
clear the offset when a synchronous transfer
does not complete successfully. The bit automatically clears itself after resetting the synchronous offset.
Bit 5
Reserved
Bit 4
SLB (SCSI Loopback Mode)
Setting this bit allows the SYM53C810A to
perform SCSI loopback diagnostics. That is, it
enables the SCSI core to simultaneously perform as both initiator and target.
Bit 3
SZM (SCSI High-Impedance Mode)
Setting this bit places all the open-drain
48 mA SCSI drivers into a high-impedance
state. This is to allow internal loopback mode
operation without affecting the SCSI bus.
Bit 2
SYM53C810A Data Manual
Reserved
5-45
Operating Registers
Bit 1
EXT( Extend SREQ/SACK
filtering)
Symbios Logic TolerANT SCSI receiver technology includes a special digital filter on the
SREQ/ and SACK/ pins which will cause
glitches on deasserting edges to be disregarded.
Setting this bit will increase the filtering period
from 30ns to 60ns on the deasserting edge of
the SREQ/ and SACK/ signals.
Note: this bit must never be set during fast SCSI
(greater than 5M transfers per second)
operations, because a valid assertion could
be treated as a glitch.
Bit 0
LOW (SCSI Low level Mode)
Setting this bit places the SYM53C810A in
low level mode. In this mode, no DMA operations occur, and no SCRIPTS execute. Arbitration and selection may be performed by
setting the start sequence bit as described in
the SCNTL0 register. SCSI bus transfers are
performed by manually asserting and polling
SCSI signals. Clearing this bit allows instructions to be executed in SCSI SCRIPTS mode.
Note: it is not necessary to set this bit for access
to the SCSI bit-level registers (SODL,
SBCL, and input registers).
Register 4F (CF)
SCSI Test Three (STEST3)
Read/Write
TE
STR
HSC
DSI
RES
TTM
CSF
STW
7
6
5
4
3
2
1
0
0
0
X
0
0
0
Default>>>
0
0
Bit 7
TE (TolerANT Enable)
Setting this bit enables the active negation portion of TolerANT technology. Active negation
causes the SCSI Request, Acknowledge, Data,
and Parity signals to be actively deasserted,
instead of relying on external pull-ups, when
the SYM53C810A is driving these signals.
Active deassertion of these signals will occur
only when the SYM53C810A is in an information transfer phase. TolerANT active negation
should be enabled to improve setup and deassertion times at fast SCSI timings. Active negation is disabled after reset or when this bit is
cleared. For more information on TolerANT
technology, refer to Chapter 1.
Bit 6
STR (SCSI FIFO Test Read)
Setting this bit places the SCSI core into a test
mode in which the SCSI FIFO can be easily
read. Reading the SODL register will cause the
FIFO to unload.
Bit 5
HSC (Halt SCSI Clock)
Asserting this bit causes the internal divided
SCSI clock to come to a stop in a glitchless
manner. This bit may be used for test purposes
or to lower IDD during a power down mode.
5-46
SYM53C810A Data Manual
Operating Registers
Bit 4
DSI (Disable Single Initiator
Response)
If this bit is set, the SYM53C810A will ignore
all bus-initiated selection attempts that employ
the single-initiator option from SCSI-1. In
order to select the SYM53C810A while this bit
is set, the SYM53C810A’s SCSI ID and the
initiator’s SCSI ID must both be asserted. This
bit should be asserted in SCSI-2 systems so
that a single bit error on the SCSI bus will not
be interpreted as a single initiator response.
Bit 3
Reserved
Bit 2
TTM (Timer Test Mode)
Setting this bit facilitates testing of the selection time-out, general purpose, and handshake-to-handshake timers by greatly reducing
all three time-out periods. Setting this bit starts
all three timers and, if the respective bits in the
SIEN1 register are set, causes the
SYM53C810A to generate interrupts at timeout. This bit is intended for internal manufacturing diagnosis and should not be used.
Register 50 (D0)
SCSI Input Data Latch (SIDL)
Read Only
This register is used primarily for diagnostic testing,
programmed I/O operation or error recovery. Data
received from the SCSI bus can be read from this
register. Data can be written to the SODL register
and then read back into the SYM53C810A by
reading this register to allow loopback testing.
When receiving SCSI data, the data will flow into
this register and out to the host FIFO. This register
differs from the SBDL register; SIDL contains
latched data and the SBDL always contains exactly
what is currently on the SCSI data bus. Reading
this register causes the SCSI parity bit to be
checked, and will cause a parity error interrupt if
the data is not valid. The power-up values are indeterminate.
Bit 1
CSF (Clear SCSI FIFO)
Setting this bit will cause the “full flags” for the
SCSI FIFO to be cleared. This empties the
FIFO. This bit is self-resetting. In addition, the
SCSI FIFO pointers, the SIDL, SODL, and
SODR Full bits in the SSTAT0 register are
cleared.
Bit 0
STW (SCSI FIFO Test Write)
Setting this bit places the SCSI core into a test
mode in which the FIFO can easily be written.
While this bit is set, writes to the SODL register will cause the entire word contained in this
register to be loaded into the FIFO. Writing the
least significant byte of the SODL register will
cause the FIFO to load.
SYM53C810A Data Manual
5-47
Operating Registers
Registers 54 (D4)
SCSI Output Data Latch (SODL)
Read/Write
Registers 58 (D8)
SCSI Bus Data Lines (SBDL)
Read Only
This register is used primarily for diagnostic testing
or programmed I/O operation. Data written to this
register is asserted onto the SCSI data bus by setting the Assert Data Bus bit in the SCNTL1 register. This register is used to send data via
programmed I/O. Data flows through this register
when sending data in any mode. It is also used to
write to the synchronous data FIFO when testing
the chip. The power-up value of this register is indeterminate.
This register contains the SCSI data bus status.
Even though the SCSI data bus is active low, these
bits are active high. The signal status is not latched
and is a true representation of exactly what is on the
data bus at the time the register is read. This register is used when receiving data via programmed
I/O. This register can also be used for diagnostic
testing or in low level mode. The power-up value of
this register is indeterminate.
5-48
SYM53C810A Data Manual
Operating Registers
Registers 5C-5F (DC-DF)
Scratch Register B (SCRATCHB)
(Read/Write)
This is a general purpose user definable scratch pad
register. Apart from CPU access, only Register
Read/Write and Memory Moves directed at the
SCRATCH register will alter its contents. The
power-up values are indeterminate.
The SYM53C810A cannot fetch SCRIPTS instructions from this location.
SYM53C810A Data Manual
5-49
Operating Registers
5-50
SYM53C810A Data Manual
Instruction Set of the I/O Processor
SCSI SCRIPTS
Chapter 6
Instruction Set of the I/O Processor
After power up and initialization of the
SYM53C810A, the chip can operate in the low
level register interface mode, or using SCSI
SCRIPTS.
With the low level register interface, the user has
access to the DMA control logic and the SCSI bus
control logic. An external processor has access to
the SCSI bus signals and the low level DMA signals, which allows creation of complicated board
level test algorithms. The low level interface is useful for backward compatibility with SCSI devices
that require certain unique timings or bus
sequences to operate properly. Another feature
allowed at the low level is loopback testing. In
loopback mode, the SCSI core can be directed to
talk to the DMA core to test internal data paths all
the way out to the chip’s pins.
SCSI SCRIPTS
To operate in the SCSI SCRIPTS mode, the
SYM53C810A requires only a SCRIPTS start
address. The start address must be at a dword
(four byte) boundary. This aligns the following
SCRIPTS at a dword boundary, since all
SCRIPTS are 8 or 12 bytes long. All instructions
are fetched from external memory. The
SYM53C810A fetches and executes its own
instructions by becoming a bus master on the host
bus and fetching two or three 32-bit words into its
registers. Instructions are fetched until an interrupt instruction is encountered, or until an unexpected event (such as a hardware error) causes an
interrupt to the external processor.
Once an interrupt is generated, the SYM53C810A
halts all operations until the interrupt is serviced.
Then, the start address of the next SCRIPTS
SYM53C810A Data Manual
instruction may be written to the DMA SCRIPTS
Pointer register to restart the automatic fetching
and execution of instructions.
The SCSI SCRIPTS mode of execution allows the
SYM53C810A to make decisions based on the status of the SCSI bus, so that the microprocessor
does not have to service all of the interrupts inherent in I/O operations.
Given the rich set of SCSI-oriented features
included in the instruction set, and the ability to
re-enter the SCSI algorithm at any point, this high
level interface is all that is required for both normal
and exception conditions. There is no need to
switch to low level mode for error recovery.
Five types of SCRIPTS instructions are implemented in the SYM53C810A:
■
Block Move—used to move data between the
SCSI bus and memory
■
I/O or Read/Write—causes the SYM53C810A
to trigger common SCSI hardware sequences,
or to move registers
■
Transfer Control— allows SCRIPTS
instructions to make decisions based on real
time SCSI bus conditions
■
Memory Move— causes the SYM53C810A to
execute block moves between different parts of
main memory
Load and Store—provides a more efficient way
to move data to/from memory from/to an
internal register in the chip without using the
Memory Move instruction.
Each instruction consists of two or three 32-bit
words. The first 32-bit word is always loaded into
the DCMD and DBC registers, the second into
the DSPS register. The third word, used only by
Memory Move instructions, is loaded into the
TEMP shadow register. In an indirect I/O or Move
instruction, the first two 32-bit op code fetches will
be followed by one or two more 32-bit fetch cycles.
■
6-1
Instruction Set of the I/O Processor
SCSI SCRIPTS
Sample Operation
The following example describes execution of a
SCRIPTS instruction. This sample operation is for
a Block Move instruction. Figure 6-1 illustrates a
SCRIPTS Initiator Write operation, which uses
several Block Move instructions.
1. The host CPU, through programmed I/O,
gives the DMA SCRIPTS Pointer (DSP)
register (in the Operating Register file) the
starting address in main memory that points to
a SCSI SCRIPTS program for execution.
2. Loading the DSP register causes the
SYM53C810A to request use of the PCI bus
to fetch its first instruction from main memory
at the address just loaded.
3. The SYM53C810A typically fetches two
dwords (64 bits) and decodes the high order
byte of the first dword as a SCRIPTS
instruction. If the instruction is a Block Move,
the lower three bytes of the first dword are
stored and interpreted as the number of bytes
to be moved. The second dword is stored and
interpreted as the 32-bit beginning address in
main memory to which the move is directed.
The process repeats until the internally stored byte
count has reached zero. The SYM53C810A
releases the PCI bus and then requests use of the
PCI bus again for another SCRIPTS instruction
fetch cycle, using the incremented stored address
maintained in the DMA SCRIPTS Pointer register. Execution of SCRIPTS instructions continues
until an error condition occurs or an interrupt
SCRIPTS instruction is received. At this point, the
SYM53C810A interrupts the host CPU and waits
for further servicing by the host system. It can execute independent Block Move instructions, specifying new byte counts and starting locations in
main memory. In this manner, the SYM53C810A
performs scatter/gather operations on data without
requiring help from the host program, generating a
host interrupt, or requiring an external DMA controller to be programmed.
4. For a SCSI send operation, the SYM53C810A
waits until there is enough space in the DMA
FIFO to transfer a programmable size block of
data. For a SCSI receive operation, it waits
until enough data is collected in the DMA
FIFO for transfer to memory.
5. SYM53C810A requests use of the PCI bus
again, this time for data transfers.
6. When the SYM53C810A is again granted the
PCI bus, it will execute (as a bus master) a
burst transfer (programmable size) of data,
decrement the internally stored remaining byte
count, increment the address pointer, and then
release the PCI bus. The SYM53C810A stays
off the PCI bus until the FIFO can again hold
(for a write) or has collected (for a read)
enough data to repeat the process.
6-2
SYM53C810A Data Manual
Instruction Set of the I/O Processor
SCSI SCRIPTS
System Processor
System Memory
•
•
•
•
•
•
•
•
•
•
SCSI Initiator Write Example
select ATN 0, alt_addr
move 1, identify_msg_buf, when MSG_OUT
move 6, cmd_buf, when CMD
move 512, data_buf, when DATA_OUT
move 1, stat_in_buf, when STATUS
move 1, msg_in_buf, when MSG_IN
move SCNTL2 & 7F to SCNTL2
clear ACK
wait disconnect alt2
int 10
Data Structure
Message Buffer
Command Buffer
Data Buffer
Status Buffer
S
y
s
t
e
m
B
u
s
Write DSP
Fetch
SCRIPTS
SYM53C810A
SCSI
Bus
Data
Figure 6-1: SCRIPTS Overview
SYM53C810A Data Manual
6-3
Instruction Set of the I/O Processor
Block Move Instructions
Block Move Instructions
The Block Move SCRIPTS instruction is used to
move data between the SCSI bus and memory. For
a Block Move instruction, the SYM53C810A
operates much like a chaining DMA device with a
SCSI controller attached. Figure 6-2 illustrates the
register bit values that represent a Block Move
instruction. In Block Move instructions, bits 5 and
4 (SIOM and DIOM) in the DMODE register
determine whether the source/destination address
resides in memory or I/O space. When data is
being moved onto the SCSI bus, SIOM controls
whether that data comes from I/O or memory
space. When data is being moved off of the SCSI
bus, DIOM controls whether that data goes to I/O
or memory space.
First Dword
Bits 31-30 Instruction Type-Block Move
Bit 29
Indirect Addressing
When this bit is cleared, user data is moved to
or from the 32-bit data start address for the
Block Move instruction. The value is loaded
into the chip’s address register and incremented as data is transferred. The address of
data to be moved is in the second dword of this
instruction.
When set, the 32-bit user data start address for
the Block Move is the address of a pointer to
the actual data buffer address. The value at the
32-bit start address is loaded into the chip’s
DNAD register via a third dword fetch (4-byte
transfer across the host computer bus).
Direct
The byte count and absolute address are as
follows.
Command
Byte Count
Address of Data
6-4
Indirect
Use the fetched byte count, but fetch the data
address from the address in the instruction.
Command
Byte Count
Address of Pointer to Data
Once the data pointer address is loaded, it is
executed as when the chip operates in the
direct mode. This indirect feature allows a
table of data buffer addresses to be specified.
Using the SCSI SCRIPTS assembler, the table
offset is placed in the SCRIPTS file when the
program is assembled. Then at the actual data
transfer time, the offsets are added to the base
address of the data address table by the external processor. The logical I/O driver builds a
structure of addresses for an I/O rather than
treating each address individually. This feature
makes it possible to locate SCSI SCRIPTS in a
PROM.
Note: indirect and table indirect addressing
cannot be used simultaneously; only one
addressing method can be used at a time.
Bit 28
Table Indirect
When this bit is set, the 24-bit signed value in
the start address of the move is treated as a relative displacement from the value in the DSA
register. Both the transfer count and the
source/destination address are fetched from
this address.
Command
Not Used
Don’t Care
Table Offset
Use the signed integer offset in bits 23-0 of the
second four bytes of the instruction, added to
the value in the DSA register, to fetch first the
byte count and then the data address. The
signed value is combined with the data structure base address to generate the physical
address used to fetch values from the data
structure. Sign-extended values of all ones for
negative values are allowed, but bits 31-24 are
ignored.
SYM53C810A Data Manual
Instruction Set of the I/O Processor
Block Move Instructions
DCMD Register
DBC Register
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
I/O
24-bit Block Move byte counter
C/D
MSG/
Op Code
Table Indirect Addressing
Indirect Addressing (53C700 compatible)
0 - Instruction Type - Block Move
0 - Instruction Type - Block Move
DSPS Register
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Figure 6-2: Block Move Instruction Register
SYM53C810A Data Manual
6-5
Instruction Set of the I/O Processor
Block Move Instructions
Prior to the start of an I/O, the Data Structure
Base Address register (DSA) should be loaded
with the base address of the I/O data structure.
The address may be any address on a long
word boundary.
After a Table Indirect op code is fetched, the
DSA is added to the 24-bit signed offset value
from the op code to generate the address of the
required data; both positive and negative offsets are allowed. A subsequent fetch from that
address brings the data values into the chip.
For a MOVE instruction, the 24-bit byte count
is fetched from system memory. Then the 32bit physical address is brought into the
SYM53C810A. Execution of the move begins
at this point.
SCRIPTS can directly execute operating system I/O data structures, saving time at the
beginning of an I/O operation. The I/O data
structure can begin on any dword boundary
and may cross system segment boundaries.
There are two restrictions on the placement of
pointer data in system memory: the eight bytes
of data in the MOVE instruction must be contiguous, as shown below; and indirect data
fetches are not available during execution of a
Memory-to-Memory DMA operation.
00
Byte Count
Physical Data Address
Bit 27
Op Code
This 1-bit field defines the instruction to be
executed as a block move (MOVE).
6-6
Target Mode
OPC
Instruction Defined
0
MOVE
1
Reserved
1. The SYM53C810A verifies that it is connected
to the SCSI bus as a target before executing
this instruction.
2. The SYM53C810A asserts the SCSI phase
signals (SMSG/, SC_D/, and SI_O/) as defined
by the Phase Field bits in the instruction.
3. If the instruction is for the command phase,
the SYM53C810A receives the first command
byte and decodes its SCSI Group Code.
a) If the SCSI Group Code is either Group 0,
Group 1, Group 2, or Group 5, then the
SYM53C810A overwrites the DBC
register with the length of the Command
Descriptor Block: 6, 10, or 12 bytes.
b) If any other Group Code is received, the
DBC register is not modified and the
SYM53C810A will request the number of
bytes specified in the DBC register. If the
DBC register contains 000000h, an illegal
instruction interrupt is generated.
4. The SYM53C810A transfers the number of
bytes specified in the DBC register starting at
the address specified in the DNAD register.
5. If the SATN/ signal is asserted by the initiator
or a parity error occurred during the transfer,
the transfer can optionally be halted and an
interrupt generated. The Disable Halt on
Parity Error or ATN bit in the SCNTL1
register controls whether the SYM53C810A
will halt on these conditions immediately, or
wait until completion of the current Move.
SYM53C810A Data Manual
Instruction Set of the I/O Processor
Block Move Instructions
Initiator Mode
OPC
Instruction Defined
0
Reserved
1
MOVE
1. The SYM53C810A verifies that it is connected
to the SCSI bus as an initiator before executing
this instruction.
2. The SYM53C810A waits for an unserviced
phase to occur. An unserviced phase is defined
as any phase (with SREQ/ asserted) for which
the SYM53C810A has not yet transferred data
by responding with a SACK/.
3. The SYM53C810A compares the SCSI phase
bits in the DCMD register with the latched
SCSI phase lines stored in the SSTAT1
register. These phase lines are latched when
SREQ/ is asserted.
4. If the SCSI phase bits match the value stored
in the SSTAT1 register, the SYM53C810A
will transfer the number of bytes specified in
the DBC register starting at the address
pointed to by the DNAD register.
5. If the SCSI phase bits do not match the value
stored in the SSTAT1 register, the
SYM53C810A generates a phase mismatch
interrupt and the instruction is not executed.
6. During a Message Out phase, after the
SYM53C810A has performed a Select with
Attention (or SATN/ has been manually
asserted with a Set ATN instruction), the
SYM53C810A will deassert SATN/ during the
final SREQ/SACK handshake of the first move
of Message Out bytes after SATN/ was set.
7. When the SYM53C810A is performing a block
move for Message In phase, it will not deassert
the SACK/ signal for the last SREQ/SACK
handshake. The SACK signal must be cleared
using the Clear SACK I/O instruction.
SYM53C810A Data Manual
Bits 26-24 SCSI Phase
This 3-bit field defines the desired SCSI information transfer phase. When the
SYM53C810A operates in initiator mode,
these bits are compared with the latched SCSI
phase bits in the SSTAT1 register. When the
SYM53C810A operates in target mode, the
SYM53C810A asserts the phase defined in this
field. The following table describes the possible
combinations and the corresponding SCSI
phase.
MSG
C/D
I/O
SCSI Phase
0
0
0
Data out
0
0
1
Data in
0
1
0
Command
0
1
1
Status
1
0
0
Reserved out
1
0
1
Reserved in
1
1
0
Message out
1
1
1
Message in
Bits 23-0 Transfer Counter
This 24-bit field specifies the number of data
bytes to be moved between the SYM53C810A
and system memory. The field is stored in the
DBC register. When the SYM53C810A transfers data to/from memory, the DBC register is
decremented by the number of bytes transferred. In addition, the DNAD register is
incremented by the number of bytes transferred. This process is repeated until the DBC
register has been decremented to zero. At that
time, the SYM53C810A fetches the next
instruction.
If bit 28 is set, indicating table indirect
addressing, this field is not used. The byte
count is instead fetched from a table pointed to
by the DSA register.
6-7
Instruction Set of the I/O Processor
I/O Instructions
Second Dword
Bits 31-0 Start Address
This 32-bit field specifies the starting address
of the data to be moved to/from memory. This
field is copied to the DNAD register. When the
SYM53C810A transfers data to or from memory, the DNAD register is incremented by the
number of bytes transferred.
When bit 29 is set, indicating indirect addressing, this address is a pointer to an address in
memory that points to the data location. When
bit 28 is set, indicating table indirect addressing, the value in this field is an offset into a
table pointed to by the DSA. The table entry
contains byte count and address information.
I/O Instructions
The I/O SCRIPTS instruction causes the
SYM53C810A to trigger common SCSI hardware
sequences such as Set/Clear ACK, Set/Clear ATN,
Set/Clear Target Mode, Select With ATN, or Wait
for Reselect. Figure 6-3 illustrates the register bit
values that represent an I/O instruction.
First Dword
Bits 31-30 Instruction Type - I/O Instruction
Bits 29-27 Op Code
The following Op Code bits have different
meanings, depending on whether the
SYM53C810A is operating in initiator or target mode. Note: Op Code selections 101-111
are considered Read/Write instructions, and
are described in that section.
Target Mode
OPC2
OPC1
OPC0
Instruction Defined
0
0
0
Reselect
0
0
1
Disconnect
0
1
0
Wait Select
0
1
1
Set
1
0
0
Clear
Reselect Instruction
1. The SYM53C810A arbitrates for the SCSI bus
by asserting the SCSI ID stored in the SCID
register. If the SYM53C810A loses arbitration,
then it tries again during the next available
arbitration cycle without reporting any lost
arbitration status.
2. If the SYM53C810A wins arbitration, it
attempts to reselect the SCSI device whose ID
is defined in the destination ID field of the
instruction. Once the SYM53C810A has won
arbitration, it fetches the next instruction from
the address pointed to by the DSP register.
6-8
SYM53C810A Data Manual
Instruction Set of the I/O Processor
I/O Instructions
3. Therefore, the SCRIPTS can move on to the
next instructions before the reselection has
completed. It will continue executing
SCRIPTS until a SCRIPTS instruction that
requires a response from the initiator is
encountered.
4. If the SYM53C810A is selected or reselected
before winning arbitration, it fetches the next
instruction from the address pointed to by the
32-bit jump address field stored in the DNAD
register. The SYM53C810A should manually
be set to initiator mode if it is reselected, or to
target mode if it is selected.
Disconnect Instruction
The SYM53C810A disconnects from the SCSI
bus by deasserting all SCSI signal outputs.
Wait Select Instruction
1. If the SYM53C810A is selected, it fetches the
next instruction from the address pointed to by
the DSP register.
2. If reselected, the SYM53C810A fetches the
next instruction from the address pointed to by
the 32-bit jump address field stored in the
DNAD register. The SYM53C810A should
manually be set to initiator mode when
reselected.
3. If the CPU sets the SIGP bit in the ISTAT
register, the SYM53C810A will abort the Wait
Select instruction and fetch the next
instruction from the address pointed to by the
32-bit jump address field stored in the DNAD
register.
Set Instruction
When the SACK/ or SATN/ bits are set, the corresponding bits in the SOCL register are set. SACK/
or SATN/ should not be set except for testing purposes. When the target bit is set, the corresponding
bit in the SCNTL0 register is also set. When the
carry bit is set, the corresponding bit in the Arithmetic Logic Unit (ALU) is set.
Note: none of the signals are set on the SCSI bus
in target mode.
SYM53C810A Data Manual
6-9
Instruction Set of the I/O Processor
I/O Instructions
DCMD Register
DBC Register
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
RES
RES
RES
RES
Set/Clear ATN/
Set/Clear ACK/
Set/Clear Target Mode
Set/Clear Carry
Encoded Destination ID 0
Encoded Destination ID 1
Encoded Destination ID 2
Reserved
Reserved
Reserved
Reserved
Reserved
Select with ATN/
Table Indirect Mode
Relative Address Mode
Op Code bit 0
Op Code bit 1
Op Code bit 2
1 - Instruction Type - I/O
0 - Instruction Type - I/O
Second 32-bit word of the I/O instruction
DSPSRegister
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
32-bit Jump Address
Figure 6-3: I/O Instruction Register
6-10
SYM53C810A Data Manual
Instruction Set of the I/O Processor
I/O Instructions
Clear Instruction
When the SACK/ or SATN/ bits are set, the corresponding bits are cleared in the SOCL register.
SACK/ or SATN/ should not be set except for testing purposes. When the target bit is set, the corresponding bit in the SCNTL0 register is cleared.
When the carry bit is set, the corresponding bit in
the ALU is cleared.
Note: none of the signals are reset on the SCSI
bus in target mode.
Initiator Mode
OPC2
OPC1
OPC0
Instruction Defined
0
0
0
Select
0
0
1
Wait Disconnect
0
1
0
Wait Reselect
0
1
1
Set
1
0
0
Clear
Select Instruction
1. The SYM53C810A arbitrates for the SCSI bus
by asserting the SCSI ID stored in the SCID
register. If the SYM53C810A loses arbitration,
it tries again during the next available
arbitration cycle without reporting any lost
arbitration status.
2. If the SYM53C810A wins arbitration, it
attempts to select the SCSI device whose ID is
defined in the destination ID field of the
instruction. Once the SYM53C810A has won
arbitration, it fetches the next instruction from
the address pointed to by the DSP register.
Therefore, the SCRIPTS program can move to
the next instruction before the selection has
completed. It will continue executing
SCRIPTS until a SCRIPTS instruction that
requires a response from the target is
encountered.
3. If the SYM53C810A is selected or reselected
before winning arbitration, it fetches the next
instruction from the address pointed to by the
SYM53C810A Data Manual
32-bit jump address field stored in the DNAD
register. The SYM53C810A should manually
be set to initiator mode if it is reselected, or to
target mode if it is selected.
4. If the Select with SATN/ field is set, the
SATN/ signal is asserted during the selection
phase.
Wait Disconnect Instruction
1. The SYM53C810A waits for the target to
perform a “legal” disconnect from the SCSI
bus. A “legal” disconnect occurs when SBSY/
and SSEL/ are inactive for a minimum of one
Bus Free delay (400 ns), after the
SYM53C810A has received a Disconnect
Message or a Command Complete Message.
Wait Reselect Instruction
1. If the SYM53C810A is selected before being
reselected, it fetches the next instruction from
the address pointed to by the 32-bit jump
address field stored in the DNAD register. The
SYM53C810A should be manually set to
target mode when selected.
2. If the SYM53C810A is reselected, it fetches
the next instruction from the address pointed
to by the DSP register.
3. If the CPU sets the SIGP bit in the ISTAT
register, the SYM53C810A will abort the Wait
Reselect instruction and fetch the next
instruction from the address pointed to by the
32-bit jump address field stored in the DNAD
register.
Set Instruction
When the SACK/ or SATN/ bits are set, the corresponding bits in the SOCL register are set. When
the Target bit is set, the corresponding bit in the
SCNTL0 register is also set. When the Carry bit is
set, the corresponding bit in the ALU is set.
Clear Instruction
When the SACK/or SATN/ bits are set, the corresponding bits are cleared in the SOCL register.
When the Target bit is set, the corresponding bit in
6-11
Instruction Set of the I/O Processor
I/O Instructions
the SCNTL0 register is cleared. When the Carry
bit is set, the corresponding bit in the ALU is
cleared.
Bit 26
Relative Addressing Mode
When this bit is set, the 24-bit signed value in
the DNAD register is used as a relative displacement from the current DSP address. This
bit should only be used in conjunction with the
Select, Reselect, Wait Select, and Wait Reselect
instructions. The Select and Reselect instructions can contain an absolute alternate jump
address or a relative transfer address.
Bit 25
Table Indirect Mode
When this bit is set, the 24-bit signed value in
the DBC register is added to the value in the
DSA register, used as an offset relative to the
value in the Data Structure Base Address
(DSA) register. The SCNTL3 value, SCSI ID,
synchronous offset and synchronous period are
loaded from this address. Prior to the start of
an I/O, the DSA should be loaded with the
base address of the I/O data structure. The
address may be any address on a dword boundary. After a Table Indirect op code is fetched,
the DSA is added to the 24-bit signed offset
value from the op code to generate the address
of the required data; both positive and negative
offsets are allowed. A subsequent fetch from
that address brings the data values into the
chip.
SCRIPTS can directly execute operating system I/O data structures, saving time at the
beginning of an I/O operation. The I/O data
structure can begin on any dword boundary
and may cross system segment boundaries.
There are two restrictions on the placement of
data in system memory:
1. The I/O data structure must lie within the 8
MB above or below the base address.
2. An I/O command structure must have all four
bytes contiguous in system memory, as shown
below. The offset/period bits are ordered as in
the SXFER register. The configuration bits are
ordered as in the SCNTL3 register.
Config
ID
Offset/
period
(00)
This bit should only be used in conjunction
with the Select, Reselect, Wait Select, and Wait
Reselect instructions. Bits 25 and 26 may be
set individually or in combination:
Bit 25
Bit 26
Direct
0
0
Table Indirect
0
1
Relative
1
0
Table Relative
1
1
Direct
Uses the device ID and physical address in the
instruction.
Command
ID
Not Used
Not Used
Absolute Alternate Address
Table Indirect
Uses the physical jump address, but fetches data
using the table indirect method.
Command
Table Offset
Absolute Alternate Address
Relative
Uses the device ID in the instruction, but treats
the alternate address as a relative jump.
Command
ID
Not Used
Not Used
Alternate Jump Offset
6-12
SYM53C810A Data Manual
Instruction Set of the I/O Processor
I/O Instructions
Table Relative
Treats the alternate jump address as a relative
jump and fetches the device ID, synchronous offset, and synchronous period indirectly. Adds the
value in bits 23-0 of the first four bytes of the
SCRIPTS instruction to the data structure base
address to form the fetch address.
Command
Table Offset
Alternate Jump Offset
Bit 24
Select with ATN/
This bit specifies whether SATN/ will be
asserted during the selection phase when the
SYM53C810A is executing a Select instruction. When operating in initiator mode, set this
bit for the Select instruction. If this bit is set on
any other I/O instruction, an illegal instruction
interrupt is generated.
Bits 18-16 Encoded SCSI Destination ID
This 3-bit field specifies the destination SCSI
ID for an I/O instruction.
Bit 10
Set/Clear Carry
This bit is used in conjunction with a Set or
Clear instruction to set or clear the Carry bit.
Setting this bit with a Set instruction asserts
the Carry bit in the ALU. Setting this bit with a
Clear instruction deasserts the Carry bit in the
ALU.
Bit 9
Set/Clear Target Mode
This bit is used in conjunction with a Set or
Clear instruction to set or clear target mode.
Setting this bit with a Set instruction configures the SYM53C810A as a target device (this
sets bit 0 of the SCNTL0 register). Clearing
this bit with a Clear instruction configures the
SYM53C810A as an initiator device (this
clears bit 0 of the SCNTL0 register).
SYM53C810A Data Manual
Bit 6
Set/Clear SACK/
Bit 3
Set/Clear SATN/
These two bits are used in conjunction with a
Set or Clear instruction to assert or deassert
the corresponding SCSI control signal. Bit 6
controls the SCSI SACK/ signal; bit 3 controls
the SCSI SATN/ signal.
Setting either of these bits will set or reset the
corresponding bit in the SOCL register,
depending on the instruction used. The Set
instruction is used to assert SACK/ and/or
SATN/ on the SCSI bus. The Clear instruction
is used to deassert SACK/ and/or SATN/ on
the SCSI bus.
Since SACK/ and SATN/ are initiator signals,
they will not be asserted on the SCSI bus
unless the SYM53C810A is operating as an
initiator or the SCSI Loopback Enable bit is
set in the STEST2 register.
The Set/Clear SCSI ACK/ATN instruction
would be used after message phase Block Move
operations to give the initiator the opportunity
to assert attention before acknowledging the
last message byte. For example, if the initiator
wishes to reject a message, an Assert SCSI
ATN instruction would be issued before a
Clear SCSI ACK instruction.
Bits 2-0 Reserved
Second Dword
Bits 31-0 Start Address
This 32-bit field contains the memory address
to fetch the next instruction if the selection or
reselection fails.
If relative or table relative addressing is used,
this value is a 24-bit signed offset relative to the
current DSP register value.
6-13
Instruction Set of the I/O Processor
Read/Write Instructions
Read/Write Instructions
The Read/Write Instruction type moves the contents of one register to another, or performs arithmetic operations such as AND, OR, XOR,
Addition, and Shift. Figure 6-4 illustrates the register bit values that represent a Read/Write instruction.
First Dword
Bits 31-30 Instruction Type - Read/Write
Instruction
The Read/Write instruction uses operator bits
26 through 24 in conjunction with the op code
bits to determine which instruction is currently
selected.
Bits 29-27 Op Code
The combinations of these bits determine if the
instruction is a Read/Write or an I/O instruction. Op codes 000 through 100 are considered
I/O instructions. Refer to Table 6-1 for field
definitions.
Bits 26-24 Operator
These bits are used in conjunction with the op
code bits to determine which instruction is
currently selected. Refer to Table 6-1 for field
definitions.
Bits 22-16 Register Address - A(6-0)
Register values may be changed from
SCRIPTS in read-modify-write cycles or move
to/from SFBR cycles. A(6-0) select an 8-bit
source/destination register within the
SYM53C810A.
6-14
Second Dword
Bits 31-0 Destination Address
This field contains the 32-bit destination
address where the data is to be moved.
Read-Modify-Write
Cycles
During these cycles the register is read, the
selected operation is performed, and the result is
written back to the source register.
The Add operation can be used to increment or
decrement register values (or memory values if
used in conjunction with a Memory-to-Register
Move operation) for use as loop counters.
Move to/from
SFBR Cycles
All operations are read-modify-writes. However,
two registers are involved, one of which is always
the SFBR. The possible functions of this instruction are:
■
Write one byte (value contained within the
SCRIPTS instruction) into any chip register.
■
Move to/from the SFBR from/to any other
register.
■
Alter the value of a register with AND/OR/
ADD/XOR/SHIFT LEFT/SHIFT RIGHT
operators.
■
After moving values to the SFBR, the compare
and jump, call, or similar instructions may be
used to check the value.
■
A Move-to-SFBR followed by a Move-fromSFBR can be used to perform a register to
register move.
SYM53C810A Data Manual
Instruction Set of the I/O Processor
Read/Write Instructions
DCMD Register
DBC Register
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Immediate Data
Reserved
(must be 0)
A0
A1
A2
A3
Register
Address
A4
A5
A6
0 (Reserved)
Operator 0
Operator 1
Operator 2
Op Code bit 0
Op Code bit 1
Op Code bit 2
1 - Instruction Type - R/W
0 - Instruction Type - R/W
DSPS Register
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Figure 6-4: Read/Write Register Instruction
SYM53C810A Data Manual
6-15
Instruction Set of the I/O Processor
Read/Write Instructions
Table 6-1: Read/Write Instructions
Op Code 111
Read Modify Write
Op Code 110
Move to SFBR
Op Code 101
Move from SFBR
000
Move data into register.
Syntax: “Move data8 to
RegA”
Move data into SFBR register. Syntax: “Move data8 to
SFBR”
Move data into register.
Syntax: “Move data8 to
RegA”
001*
Shift register one bit to the
left and place the result in
the same register. Syntax:
“Move RegA SHL RegA”
Shift register one bit to the
left and place the result in
the SFBR register. Syntax:
“Move RegA SHL SFBR”
Shift the SFBR register one
bit to the left and place the
result in the register. Syntax:
“Move SFBR SHL RegA”
010
OR data with register and
place the result in the same
register. Syntax: “Move
RegA | data8 to RegA”
OR data with register and
place the result in the SFBR
register. Syntax: “Move
RegA | data8 to SFBR”
OR data with SFBR and
place the result in the register. Syntax: “Move SFBR |
data8 to RegA”
011
XOR data with register and
place the result in the same
register. Syntax: “Move
RegA XOR data8 to RegA”
XOR data with register and
place the result in the SFBR
register. Syntax: “Move
RegA XOR data8 to SFBR”
XOR data with SFBR and
place the result in the register. Syntax: “Move SFBR
XOR data8 to RegA”
100
AND data with register and
place the result in the same
register. Syntax: “Move
RegA & data8 to RegA”
AND data with register and
place the result in the SFBR
register. Syntax: “Move
RegA & data8 to SFBR”
AND data with SFBR and
place the result in the register. Syntax: “Move SFBR &
data8 to RegA”
101*
Shift register one bit to the
right and place the result in
the same register. Syntax:
“Move RegA SHR RegA”
Shift register one bit to the
right and place the result in
the SFBR register. Syntax:
“Move RegA SHR SFBR”
Shift the SFBR register one
bit to the right and place the
result in the register. Syntax:
“Move SFBR SHR RegA”
110
Add data to register without
carry and place the result in
the same register. Syntax:
“Move RegA + data8 to
RegA”
Add data to register without
carry and place the result in
the SFBR register. Syntax:
“Move RegA + data8 to
SFBR”
Add data to SFBR without
carry and place the result in
the register. Syntax: “Move
SFBR + data8 to RegA”
111
Add data to register with
carry and place the result in
the same register. Syntax:
“Move RegA + data8 to
RegA with carry”
Add data to register with
carry and place the result in
the SFBR register. Syntax:
“Move RegA + data8 to
SFBR with carry”
Add data to SFBR with
carry and place the result in
the register. Syntax: “Move
SFBR + data8 to RegA with
carry”
Operator
Notes:
1. Substitute the desired register name or address for “RegA” in the syntax examples
2. data8 indicates eight bits of data
* Data is shifted through the Carry bit and the Carry bit is shifted into the data byte
6-16
SYM53C810A Data Manual
Instruction Set of the I/O Processor
Transfer Control Instructions
Transfer Control
Instructions
The Transfer Control, or Conditional Jump,
instruction allows you to write SCRIPTS that
make decisions based on real time conditions on
the SCSI bus, such as phase or data. This instruction type includes Jump, Call, Return, and Interrupt instructions. Figure 6-5 illustrates the register
bit values that represent a Transfer Control
instruction.
First Dword
Bits 31-30 Instruction Type - Transfer Control
Instruction
Bits 29-27 Op Code
This 3-bit field specifies the type of transfer
control instruction to be executed. All transfer
control instructions can be conditional. They
can be dependent on a true/false comparison
of the ALU Carry bit or a comparison of the
SCSI information transfer phase with the
Phase field, and/or a comparison of the First
Byte Received with the Data Compare field.
Each instruction can operate in initiator or target mode.
instruction.
2. If the comparisons are false, the
SYM53C810A fetches the next instruction
from the address pointed to by the DSP
register, leaving the instruction pointer
unchanged.
Call Instruction
1. The SYM53C810A can do a true/false
comparison of the ALU carry bit, or compare
the phase and/or data as defined by the Phase
Compare, Data Compare, and True/False bit
fields. If the comparisons are true, the
SYM53C810A loads the DSP register with the
contents of the DSPS register and that address
value becomes the address of the next
instruction.
When the SYM53C810A executes a Call
instruction, the instruction pointer contained
in the DSP register is stored in the TEMP register. Since the TEMP register is not a stack
and can only hold one dword, nested call
instructions are not allowed.
2. If the comparisons are false, the
SYM53C810A fetches the next instruction
from the address pointed to by the DSP
register and the instruction pointer is not
modified.
Return Instruction
OPC2
OPC1
OPC0
Instruction Defined
0
0
0
Jump
0
0
1
Call
0
1
0
Return
0
1
1
Interrupt
1
X
X
Reserved
Jump Instruction
1. The SYM53C810Acan do a true/false
comparison of the ALU carry bit, or compare
the phase and/or data as defined by the Phase
Compare, Data Compare and True/False bit
fields. If the comparisons are true, the
SYM53C810A loads the DSP register with the
contents of the DSPS register. The DSP
register now contains the address of the next
SYM53C810A Data Manual
1. The SYM53C810A can do a true/false
comparison of the ALU carry bit, or compare
the phase and/or data as defined by the Phase
Compare, Data Compare, and True/False bit
fields. If the comparisons are true, then the
SYM53C810A loads the DSP register with the
contents of the DSPS register. That address
value becomes the address of the next
instruction.
When a Return instruction is executed, the
value stored in the TEMP register is returned
to the DSP register. The SYM53C810A does
not check to see whether the Call instruction
has already been executed. It will not generate
an interrupt if a Return instruction is executed
without previously executing a Call instruction.
6-17
Instruction Set of the I/O Processor
Transfer Control Instructions
DCMD Register
DBC Register
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Mask for compare
Wait for Valid Phase
Compare Phase
Compare Data
Jump if: True=1, False=0
Interrupt on the Fly
Carry Test
0 (Reserved)
Relative addressing mode
Data to be compared
with the SCSI First
Byte Received
I/O
C/D
MSG
Op Code bit 0
Op Code bit 1
Op Code bit 2
0 - Instruction Type - Transfer Control
1- Instruction Type - Transfer Control
DSPS Register
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Figure 6-5: Transfer Control Instruction
6-18
SYM53C810A Data Manual
Instruction Set of the I/O Processor
Transfer Control Instructions
2. If the comparisons are false, then the
SYM53C810A fetches the next instruction
from the address pointed to by the DSP
register and the instruction pointer will not be
modified.
Interrupt Instructions
Interrupt
a) The SYM53C810A can do a true/false
comparison of the ALU carry bit, or
compare the phase and/or data as defined
by the Phase Compare, Data Compare,
and True/False bit fields. If the
comparisons are true, then the
SYM53C810A generates an interrupt by
asserting the IRQ/ signal.
b) The 32-bit address field stored in the
DSPS register (not DNAD as in 53C700)
can contain a unique interrupt service
vector. When servicing the interrupt, this
unique status code allows the ISR to
quickly identify the point at which the
interrupt occurred.
c) The SYM53C810A halts and the DSP
register must be written to start any further
operation.
Interrupt on-the-Fly
a) The SYM53C810A can do a true/false
comparison of the ALU carry bit or
compare the phase and/or data as defined
by the Phase Compare, Data Compare,
and True/False bit fields. If the
comparisons are true, and the Interrupt on
the Fly bit is set (bit 20), the
SYM53C810A will assert the Interrupt on
the Fly bit (ISTAT bit 2).
Bits 26-24 SCSI Phase
This 3-bit field corresponds to the three SCSI
bus phase signals which are compared with the
phase lines latched when SREQ/ is asserted.
Comparisons can be performed to determine
the SCSI phase actually being driven on the
SCSI bus. The following table describes the
possible combinations and their correspond-
SYM53C810A Data Manual
ing SCSI phase. These bits are only valid when
the SYM53C810A is operating in initiator
mode; when the SYM53C810A is operating in
the target mode, these bits should be cleared.
MSG
C/D
I/O
SCSI Phase
0
0
0
Data out
0
0
1
Data in
0
1
0
Command
0
1
1
Status
1
0
0
Reserved out
1
0
1
Reserved in
1
1
0
Message out
1
1
1
Message in
Bit 23 Relative Addressing Mode
When this bit is set, the 24-bit signed value in
the DSPS register is used as a relative offset
from the current DSP address (which is pointing to the next instruction, not the one currently executing). Relative mode does not
apply to Return and Interrupt SCRIPTS.
Jump/Call an Absolute Address
Start execution at the new absolute address.
Command
Condition Codes
Absolute Alternate Address
Jump/Call a Relative Address
Start execution at the current address plus (or
minus) the relative offset.
Command
Don’t Care
Condition Codes
Alternate Jump Offset
The SCRIPTS program counter is a 32-bit
value pointing to the SCRIPTS instruction
currently being executed by the
SYM53C810A. The next address is formed by
adding the 32-bit program counter to the 24bit signed value of the last 24 bits of the Jump
6-19
Instruction Set of the I/O Processor
Transfer Control Instructions
or Call instruction. Because it is signed (twos
compliment), the jump can be forward or
backward.
A relative transfer can be to any address within
a 16-MB segment. The program counter is
combined with the 24-bit signed offset (using
addition or subtraction) to form the new execution address.
SCRIPTS programs may contain a mixture of
direct jumps and relative jumps to provide
maximum versatility when writing SCRIPTS.
For example, major sections of code can be
accessed with far calls using the 32-bit physical
address, then local labels can be called using
relative transfers. If a SCRIPTS instruction
uses only relative transfers it would not require
any run time alteration of physical addresses,
and could be stored in and executed from a
PROM.
Bit 21
Carry Test
When this bit is set, decisions based on the
ALU carry bit can be made. True/False comparisons are legal, but Data Compare and
Phase Compare are illegal.
Bit 20
Interrupt on the Fly
When this bit is set, the Interrupt instruction
will not halt the SCRIPTS processor. Once the
interrupt occurs, the Interrupt on the Fly bit
(ISTAT bit 2) will be asserted.
Bit 19
Jump If True/False
This bit determines whether the
SYM53C810A should branch when a comparison is true or when a comparison is false. This
bit applies to phase compares, data compares,
and carry tests. If both the Phase Compare and
Data Compare bits are set, then both compares
6-20
must be true to branch on a true condition.
Both compares must be false to branch on a
false condition.
Bit 19
Result of
Compare
0
False
Jump Taken
0
True
No Jump
1
False
No Jump
1
True
Jump Taken
Action
Bit 18
Compare Data
When this bit is set, the first byte received from
the SCSI data bus (contained in SFBR register) is compared with the Data to be Compared Field in the Transfer Control instruction.
The Wait for Valid Phase bit controls when this
compare will occur. The Jump if True/False bit
determines the condition (true or false) to
branch on.
Bit 17
Compare Phase
When the SYM53C810A is in initiator mode,
this bit controls phase compare operations.
When this bit is set, the SCSI phase signals
(latched by SREQ/) are compared to the Phase
Field in the Transfer Control instruction; if
they match, the comparison is true. The Wait
for Valid Phase bit controls when the compare
will occur. When the SYM53C810A is operating in target mode this bit, when set, tests for
an active SCSI SATN/ signal.
Bit 16
Wait For Valid Phase
If the Wait for Valid Phase bit is set, the
SYM53C810A waits for a previously unserviced phase before comparing the SCSI phase
and data. If the Wait for Valid Phase bit is clear,
the SYM53C810A compares the SCSI phase
and data immediately.
SYM53C810A Data Manual
Instruction Set of the I/O Processor
Memory Move Instructions
Bits 15-8 Data Compare Mask
The Data Compare Mask allows a SCRIPTS
instruction to test certain bits within a data
byte. During the data compare, any mask bits
that are set cause the corresponding bit in the
SFBR data byte to be ignored. For instance, a
mask of 01111111b and data compare value of
1XXXXXXXb allows the SCRIPTS processor to determine whether or not the high order
bit is set while ignoring the remaining bits.
Bits 7-0 Data Compare Value
This 8-bit field is the data to be compared
against the SCSI First Byte Received (SFBR)
register. These bits are used in conjunction
with the Data Compare Mask Field to test for
a particular data value.
Second Dword
Bits 31-0 Jump Address
This 32-bit field contains the address of the
next instruction to fetch when a jump is taken.
Once the SYM53C810A has fetched the
instruction from the address pointed to by
these 32 bits, this address is incremented by 4,
loaded into the DSP register and becomes the
current instruction pointer.
Memory Move Instructions
This SCRIPTS Instruction allows the
SYM53C810A to execute high performance block
moves of 32-bit data from one part of main memory to another. In this mode, the SYM53C810A is
an independent, high performance DMA controller irrespective of SCSI operations. Since the registers of the SYM53C810A can be mapped into
system memory, this SCRIPTS instruction also
moves an SYM53C810A register to or from memory or another SYM53C810A register. Figure 6-6
illustrates the register bit values that represent a
Memory Move instruction.
For Memory Move instructions, bits 5 and 4
(SIOM and DIOM) in the DMODE register
determine whether the source or destination
addresses reside in memory or I/O space. By setting these bits appropriately, data may be moved
within memory space, within I/O space, or
between the two address spaces.
The Memory Move instruction is used to copy the
specified number of bytes from the source address
to the destination address.
Allowing the SYM53C810A to perform memory
moves frees the system processor for other tasks
and moves data at higher speeds than available
from current DMA controllers. Up to 16 MB may
be transferred with one instruction. There are two
restrictions:
1. Both the source and destination addresses
must start with the same address alignment
(A(1-0) must be the same). If source and
destination are not aligned, then an illegal
instruction interrupt will occur.
2. Indirect addresses are not allowed. A burst of
data is fetched from the source address, put
into the DMA FIFO and then written out to
the destination address. The move continues
until the byte count decrements to zero, then
another SCRIPTS instruction is fetched from
system memory.
SYM53C810A Data Manual
6-21
Instruction Set of the I/O Processor
Memory Move Instructions
DCMD Register
DBC Register
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
1 - No Flush
0 (Reserved)
0 (Reserved)
0 (Reserved)
0 (Reserved)
0 (Reserved)
1 - Instruction Type - Memory Move
1 - Instruction Type - Memory Move
24-bit Memory Move byte counter
DSPS Register
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
TEMP Register
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Figure 6-6: Memory to Memory Move Instruction
6-22
SYM53C810A Data Manual
Instruction Set of the I/O Processor
Memory Move Instructions
The DSPS and DSA registers are additional holding registers used during the Memory Move; however, the contents of the DSA register are
preserved.
First Dword
Bits 31-30 Instruction Type - Memory Move
Instruction
Bits 29-25 Reserved
These bits are reserved and must be zero. If
any of these bits is set, an illegal instruction
interrupt will occur.
Bit 24
No Flush
Note: this bit has no effect unless the Pre-fetch
Enable bit in the DCNTL register is set.
For information on SCRIPTS instruction
prefetching, see Chapter 2.
When this bit is set, the SYM53C810A performs a Memory Move (MMOV) without
flushing the prefetch unit (NFMMOV). When
this bit is clear, the Memory Move instruction
automatically flushes the prefetch unit. NFMMOV should be used if the source and destination are not within four instructions of the
current MMOV instruction.
Bits 23-0 Transfer Count
The number of bytes to be transferred is stored
in the lower 24 bits of the first instruction
word.
Read/Write System
Memory from a SCRIPTS Instruction
By using the Memory Move instruction, single or
multiple register values may be transferred to or
from system memory.
Because the SYM53C810A will respond to
addresses as defined in the Base I/O or Base Memory registers, it could be accessed during a Memory Move operation if the source or destination
address decodes to within the chip’s register space.
If this occurs, the register indicated by the lower
seven bits of the address is taken to be the data
source or destination. In this way, register values
can be saved to system memory and later restored,
and SCRIPTS can make decisions based on data
values in system memory.
The SFBR is not writable via the CPU, and therefore not by a Memory Move. However, it can be
loaded via SCRIPTS Read/Write operations. To
load the SFBR with a byte stored in system memory, the byte must first be moved to an intermediate SYM53C810A register (for example, a
SCRATCH register), and then to the SFBR.
The same address alignment restrictions apply to
register access operations as to normal memory-to-memory transfers.
Second Dword
Bits 31-0, DSPS Register
These bits contain the source address of the
Memory Move.
Third Dword
Bits 31-0, TEMP Register
These bits contain the destination address for
the Memory Move.
SYM53C810A Data Manual
6-23
Instruction Set of the I/O Processor
Load and Store Instructions
Load and Store
Instructions
The Load and Store instruction provides a more
efficient way to move data from/to memory to/from
an internal register in the chip without using the
normal memory move instruction.
The load and store instructions are represented by
two-dword op codes. The first dword contains the
DCMD and DBC register values. The second
dword contains the DSPS value. This is either the
actual memory location of where to load or store,
or the offset from the DSA, depending on the
value of Bit 28 (DSA Relative).
A maximum of 4 bytes may be moved with these
instructions. The register address and memory
address must have the same byte alignment, and
the count set such that it does not cross dword
boundaries. The destination memory address in
the Store instruction and the source address in the
Load instruction may not map back to the operating register set of the chip. If it does, a PCI illegal
read/write cycle will occur, and the chip will issue
an interrupt (Illegal Instruction Detected) immediately following.
Bits A1, A0
Number of bytes allowed to load/
store
00
One, two, three or four
01
One, two, or three.
10
One or two
11
One
The SIOM and DIOM bits in the DMODE register determine whether the destination or source
address of the instruction is in Memory space or I/
O space. The Load/Store utilizes the PCI commands for I/O READ and I/O WRITE to access
the I/O space.
Bit 28, DSA Relative
When this bit is clear, the value in the DSPS is
the actual 32-bit memory address to perform
the load/store to/from. When this bit is set, the
chip determines the memory address to perform the load/store to/from by adding the 24bit signed offset value in the DSPS to the DSA.
Bits 27-26, Reserved
Bit 25, No Flush (Store instruction only)
Note: this bit has no effect unless the Pre-fetch
Enable bit in the DCNTL register is set.
For information on SCRIPTS instruction
prefetching, see Chapter 2.
When this bit is set, the SYM53C810A performs a Store without flushing the prefetch
unit. When this bit is clear, the Store instruction automatically flushes the prefetch unit. No
Flush should be used if the source and destination are not within four instructions of the current Store instruction.
Bit 24, Load/Store
When this bit is set, the instruction is a Load.
When cleared, it is a Store.
Bit 23, Reserved
Bits 22-16, Register Address
A6-A0 select the register to load/store to/from
within the SYM053C810A.
Note: It is not possible to load the SFBR register,
although the SFBR contents may be stored
in another location.
Bits 15-3, Reserved
Bits 2-0, Byte Count
This value is the number of bytes to load/store.
Second Dword
Bits 31-0, Memory/IO Address / DSA Offset
This is the actual memory location of where to
load or store, or the offset from the DSA register
value.
First Dword
Bit 31-29, Instruction Type
These bits should be 111, indicating the Load and
Store instruction.
6-24
SYM53C810A Data Manual
Instruction Set of the I/O Processor
Load and Store Instructions
DCMD Register
DBC Register
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Reserved
(must be 0)
A0
Byte Count
(Number of bytes
to load/store)
A1
A2
A3
Register
Address
A4
A5
A6
0 (Reserved)
Load/Store
1 - No Flush
0 - Reserved
0 - Reserved
X - DSA Relative
1
1
Instruction Type - Load and Store
1
DSPS Register - Memory/ I/O Address/DSA Offset
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Figure 6-7: Load and Store Instruction Format
SYM53C810A Data Manual
6-25
Instruction Set of the I/O Processor
Load and Store Instructions
6-26
SYM53C810A Data Manual
Electrical Characteristics
DC Characteristics
Chapter 7
Electrical Characteristics
This chapter presents electrical and timing information for the SYM53C810A, using tables and timing
diagrams. Table 7-1 through Table 7-11 list the stress ratings, operating conditions, and DC characteristics of the SYM53C810A. Table 7-12 and Figure 7-1 through Figure 7-5 show the effect of TolerANT
technology on the DC characteristics of the chip.The following section of this chapter presents the AC
characteristics of the SYM53C810A . The chip timings are presented in two sections. The first is the PCI
and external memory interface, followed by the SCSI interface timings.
DC Characteristics
Table 7-1: Absolute Maximum Stress Ratings
Symbol
Parameter
Min
Max
Unit
Test Conditions
TSTG
Storage temperature
-55
150
°C
-
VDD
Supply voltage
-0.5
7.0
V
-
VIN
Input Voltage
VSS - 0.5
VDD + 0.5
V
-
ILP*
Latch-up current
± 150
-
mA
-
ESD**
Electrostatic discharge
-
2K
V
MIL-STD 883C,
Method 3015.7
Stresses beyond those listed above may cause permanent damage to the device. These are stress ratings only; functional operation of
the device at these or any other conditions beyond those indicated in the Operating Conditions section of the manual is not implied.
* -2V < VPIN < 8V
** SCSI pins only
SYM53C810A Data Manual
7-1
Electrical Characteristics
DC Characteristics
Table 7-2: Operating Conditions
Symbol
Parameter
Min
Max
Unit
Test Conditions
VDD
Supply voltage
4.75
5.25
V
-
IDD*
Supply current (dynamic)
Supply current (static)
-
130
1
mA
mA
-
TA
Operating free air
0
70
°C
-
θJA
Thermal resistance
(junction to ambient air)
-
67
°C/W
-
Conditions that exceed the operating limits may cause the device to function incorrectly
*Average operating supply current is 50 mA.
Table 7-3: SCSI Signals - SD(7-0)/, SDP/, SREQ/ SACK/
Symbol
Parameter
Min
Max
Unit
Test Conditions
VIH
Input high voltage
2.0
VDD + 0.5
V
-
VIL
Input low voltage
VSS - 0.5
0.8
V
-
VOH*
Output high voltage
2.5
3.5
V
2.5 mA
VOL
Output low voltage
VSS
0.5
V
48 mA
IIN
Input leakage
-10
10
µA
-
IOZ
Tristate leakage
-10
10
µA
-
*TolerANT active negation enabled
7-2
SYM53C810A Data Manual
Electrical Characteristics
DC Characteristics
Table 7-4: SCSI Signals - SMSG, SI_O/, SC_D/, SATN/, SBSY/, SSEL/, SRST/
Symbol
Parameter
Min
Max
Unit
Test Conditions
VIH
Input high voltage
2.0
VDD + 0.5
V
-
VIL
Input low voltage
VSS - 0.5
0.8
V
-
VOL
Output low voltage
VSS
0.5
V
48 mA
IIN
Input leakage
(SRST/ only)
-10
-500
+10
-50
µA
µA
-
IOZ
Tristate leakage
-10
10
µA
-
Table 7-5: Input Signals - CLK, SCLK, GNT/, IDSEL, RST/, TESTIN
Symbol
Parameter
Min
Max
Unit
Test Conditions
VIH
Input high voltage
2.0
VDD + 0.5
V
-
VIL
Input low voltage
VSS - 0.5
0.8
V
-
IIN
Input leakage
-1.0
1.0
µA
-
Note: CLK, SCLK, GNT/, and IDSEL have 100 µA pull-ups that are enabled when TESTIN is low. TESTIN has a 100 µA
pull-up that is always enabled.
Table 7-6: Capacitance
Symbol
Parameter
Min
Max
Unit
Test Conditions
CI
Input capacitance of
input pads
-
7
pF
-
CIO
Input capacitance of I/O
pads
-
10
pF
-
SYM53C810A Data Manual
7-3
Electrical Characteristics
DC Characteristics
Table 7-7: Output Signal - MAC/_TESTOUT, REQ/
Symbol
Parameter
Min
Max
Unit
Test Conditions
VOH
Output high voltage
2.4
VDD
V
-16 mA
VOL
Output low voltage
VSS
0.4
V
16 mA
IOH
Output high current
-8
-
mA
VDD - 0.5 V
IOL
Output low current
16
-
mA
0.4 V
IOZ
Tristate leakage
-10
10
µA
-
Note: REQ/ has a 100 µA pull-up that is enabled when TESTIN is low
Table 7-8: Output Signal - IRQ/
Symbol
Parameter
Min
Max
Unit
Test Conditions
VOH
Output high voltage
2.4
VDD
V
-8 mA
VOL
Output low voltage
VSS
0.4
V
8 mA
IOH
Output high current
-4
-
mA
VDD - 0.5 V
IOL
Output low current
8
-
mA
0.4 V
IOZ
Tristate leakage
-10
10
µA
-
Note: IRQ/ has a 100 µA pull-up that is enabled when TESTIN is low. IRQ/ can be enabled with a register bit as an open drain output with an internal 100 µA pull-up.
Table 7-9: Output Signal - SERR/
Symbol
Parameter
Min
Max
Unit
Test Conditions
VOL
Output low voltage
VSS
0.4
V
16 mA
IOL
Output low current
16
-
mA
0.4 V
IOZ
Tristate leakage
-10
10
µA
-
7-4
SYM53C810A Data Manual
Electrical Characteristics
DC Characteristics
Table 7-10:
Bidirectional Signals - AD(31-0), C_BE/(3-0), FRAME, IRDY/, TRDY/, DEVSEL/, STOP/,
PERR/, PAR
Symbol
Parameter
Min
Max
Unit
Test Conditions
VIH
Input high voltage
2.0
VDD + 0.5
V
-
VIL
Input low voltage
VSS - 0.5
0.8
V
-
VOH
Output high voltage
2.4
VDD
V
16 mA
VOL
Output low voltage
VSS
0.4
V
16 mA
IOH
Output high current
-8
-
mA
VDD - 0.5
IOL
Output low current
16
-
mA
0.4 V
IIN
Input leakage
-10
10
µA
VSS < VIN < VDD
IOZ
Tristate leakage
-10
10
µA
-
Note: All the signals in this table have 100 µA pull-ups that are enabled when TESTIN is low
Table 7-11: Bidirectional Signals - GPIO0_FETCH/, GPIO1_MASTER/
Symbol
Parameter
Min
Max
Unit
Test Conditions
VIH
Input high voltage
2.0
VDD + 0.5
V
-
VIL
Input low voltage
VSS - 0.5
0.8
V
-
VOH
Output high voltage
2.4
VDD
V
-16 mA
VOL
Output low voltage
VSS
0.4
V
16 mA
IOH
Output high current
-8
-
mA
2.4V
IOL
Output low current
16
-
mA
0.4 V
IIN
Input leakage
-10
10
µA
-
IOZ
Tristate leakage
-10
10
µA
-
Note: All the signals in this table have 100 µA pull-ups that are enabled when TESTIN is low
SYM53C810A Data Manual
7-5
Electrical Characteristics
TolerANT Technology
TolerANT Technology
Table 7-12: TolerANT Active Negation Technology Electrical Characteristics
Symbol
Parameter
Min
Max
Units
Test Conditions
VOH1
Output high voltage
2.5
3.5
V
IOH = 2.5 mA
VOL
Output low voltage
0.1
0.5
V
IOL = 48 mA
VIH
Input high voltage
2.0
7.0
V
-
VIL
Input low voltage
-0.5
0.8
V
Referenced to VSS
VIK
Input clamp voltage
-0.66
-0.77
V
VDD = 4.75;
II = -20 mA
VTH
Threshold, high to low
1.1
1.3
V
-
VTL
Threshold, low to high
1.5
1.7
V
-
VTHVTL
Hysteresis
200
400
mV
-
IOH1
Output high current
2.5
24
mA
VOH = 2.5 V
IOL
Output low current
100
200
mA
VOL = 0.5 V
IOSH1
Short-circuit output
high current
-
625
mA
Output driving low,
pin shorted to VDD
supply2
IOSL
Short-circuit output low
current
-
95
mA
Output driving
high, pin shorted to
VSS supply
ILH
Input high leakage
-
10
µA
-0.5 < VDD < 5.25
VPIN = 2.7 V
ILL
Input low leakage
-
-10
µA
-0.5 < VDD < 5.25
VPIN = 0.5 V
RI
Input resistance
20
-
MΩ
SCSI pins3
CP
Capacitance per pin
-
10
pF
PQFP
tR1
Rise time, 10% to 90%
9.7
18.5
ns
Figure 7-1
Note: These values are guaranteed by periodic characterization; they are not 100% tested on every device.
1 Active negation outputs only: Data, Parity, SREQ/, SACK/
2Single pin only; irreversible damage may occur if sustained for one second
3SCSI RESET pin has 10 kΩ pull-up resistor
7-6
SYM53C810A Data Manual
Electrical Characteristics
TolerANT Technology
Table 7-12: TolerANT Active Negation Technology Electrical Characteristics (Continued)
Symbol
Parameter
Min
Max
Units
Test Conditions
tF
Fall time, 90% to 10%
5.2
14.7
ns
Figure 7-1
dVH/dt
Slew rate, low to high
0.15
0.49
V/ns
Figure 7-1
dVL/dt
Slew rate, high to low
0.19
0.52
V/ns
Figure 7-1
ESD
Electrostatic discharge
2
-
KV
MIL-STD-883C;
3015-7
Latch-up
100
-
mA
-
Filter delay
20
30
ns
Figure 7-2
Extended filter delay
40
60
ns
Figure 7-2
Note: These values are guaranteed by periodic characterization; they are not 100% tested on every device.
1 Active negation outputs only: Data, Parity, SREQ/, SACK/
2Single pin only; irreversible damage may occur if sustained for one second
3SCSI RESET pin has 10 kΩ pull-up resistor
47 Ω
20 pF
+
2.5 V
-
Figure 7-1: Rise and Fall Time Test Conditions
t1
REQ/ or ACK/ Input
VTH
*t1 is the input filtering period
Figure 7-2: SCSI Input Filtering
SYM53C810A Data Manual
7-7
Electrical Characteristics
TolerANT Technology
Received Logic Level
1.1
1.3
1
0
1.5
1.7
Input Voltage (Volts)
Figure 7-3: Hysteresis of SCSI Receiver
INPUT CURRENT (milliAmperes)
+40
+20
14.4 V
8.2 V
0
-0.7 V
HI-Z
-20
OUTPUT
ACTIVE
-40
-4
0
4
8
12
16
INPUT VOLTAGE (Volts)
OUTPUT SOURCE CURRENT (milliAmperes)
OUTPUT SINK CURRENT (milliAmperes)
Figure 7-4: Input Current as a Function of Input Voltage
0
-200
-400
-600
-800
0
1
2
3
4
OUTPUT VOLTAGE (Volts)
5
100
80
60
40
20
0
0
1
2
3
4
5
OUTPUT VOLTAGE (Volts)
Figure 7-5: Output Current as a Function of Output Voltage
7-8
SYM53C810A Data Manual
Electrical Characteristics
AC Characteristics
AC Characteristics
The AC characteristics described in this section apply over the entire range of operating conditions (refer
to the DC Characteristics section), Chip timings are based on simulation at worst case voltage, temperature, and processing. Timings were developed with a load capacitance of 50 pF.
t1
t3
CLK/SCLK
t4
t2
Figure 7-6: Clock Timing Waveform
Table 7-13: Clock Timing
Symbol
Parameter
Min
Max
Units
t1
Bus clock cycle time
30
DC
ns
SCSI clock cycle time (SCLK)*
25
60
ns
CLK low time**
12
-
ns
SCLK low time**
10
33
ns
CLK high time**
12
-
ns
SCLK high time**
10
33
ns
CLK slew rate
1
-
V/ns
SCLK slew rate
1
-
V/ns
t2
t3
t4
* This parameter must be met to insure SCSI timings are within specification
**Duty cycle not to exceed 60/40
SYM53C810A Data Manual
7-9
Electrical Characteristics
AC Characteristics
CLK
t2
t1
RST/
Figure 7-7: Reset Input Waveforms
Table 7-14: Reset Input Timings
Symbol
Parameter
Min
Max
Units
t1
Reset pulse width
10
-
tCLK
t2
Reset deasserted setup to CLK high
0
-
ns
t2
t3
t1
IRQ/
CLK
Figure 7-8: Interrupt Output Waveforms
Table 7-15: Interrupt Output Timings
Symbol
Parameter
Min
Max
Units
t1
CLK high to IRQ/ low
-
20
ns
t2
CLK high to IRQ/ high
-
40
ns
t3
IRQ/ deassertion time
3
-
CLKs
7-10
SYM53C810A Data Manual
Electrical Characteristics
PCI Interface Timing Diagrams
PCI Interface Timing Diagrams
Figure 7-9 through Figure 7-18 represent signal activity when the SYM53C810A accesses the PCI bus.
The timings for the PCI bus interface are listed on page 7-22. The following timing diagrams are included
in this section:
Target Cycles
■
PCI configuration register read
■
PCI configuration register write
■
Target read
■
Target write
■
Initiator Cycles
■
Op code fetch, non-burst
■
Burst op code fetch
■
Back-to-back read
■
Back-to-back write
■
Burst read
■
Burst write
SYM53C810A Data Manual
7-11
Electrical Characteristics
PCI Interface Timing Diagrams
1
2
3
4
5
CLK
(Driven by System)
FRAME/
(Driven by System)
t1
t
2
t1
AD/
(Driven by Master-Addr;
53C810A-Data)
C_BE/
(Driven by Master)
t3
Addr
In
t1
Data Out
t2
CMD
t2
PAR
(Driven by Master-Addr;
53C810A-Data)
t
Byte Enable
2
t1
t3
In
Out
t2
IRDY/
t1
(Driven by Master)
t
2
TRDY/
(Driven by 53C810A)
t
3
STOP/
(Driven by 53C810A)
t
3
DEVSEL/
(Driven by 53C810A)
t3
t1
IDSEL
(Driven by Master)
t2
Figure 7-9: PCI Configuration Register Read
7-12
SYM53C810A Data Manual
Electrical Characteristics
PCI Interface Timing Diagrams
1
2
3
4
5
CLK
(Driven by System)
FRAME/
(Driven by Master)
t
1
t
AD/
(Driven by Master)
t2
1
Addr
In
t1
C_BE/
(Driven by Master)
t2
t1
Data In
t2
t
CMD
2
Byte Enable
t2
PAR/
(Driven by Master)
t
1
t
t1
IRDY/
(Driven by Master)
2
t
TRDY/
(Driven by 53C810A)
2
t
3
STOP/
(Driven by 53C810A)
t
3
DEVSEL/
(Driven by 53C810A)
t
t1
IDSEL
(Driven by Master)
3
t2
Figure 7-10: PCI Configuration Register Write
SYM53C810A Data Manual
7-13
Electrical Characteristics
PCI Interface Timing Diagrams
1
2
3
4
5
6
7
8
9
CLK
(Driven by System)
FRAME/
(Driven by Master)
t1
t2
t1
AD
(Driven by Master-Addr;
53C810A-Data)
Addr
In
C_BE/
(Driven by Master)
CMD
t1
t
3
Data
Out
t2
Byte Enable
t2
t2
t1
PAR
(Driven by Master-Addr;
53C810A-Data)
IRDY/
(Driven by Master)
t
3
In
Out
t
2
t1
t
t
TRDY
2
3
(Driven by 53C810A)
t
3
STOP/
(Driven by 53C810A)
DEVSEL/
(Driven by 53C810A)
t3
Figure 7-11: Target Read
7-14
SYM53C810A Data Manual
Electrical Characteristics
PCI Interface Timing Diagrams
1
2
3
4
5
6
7
8
9
CLK
(Driven by System)
t
1
FRAME/
t
(Driven by Master)
2
AD/
(Driven by Master)
Addr
In
t
C_BE/
(Driven by Master)
PAR/
(Driven by Master)
IRDY/
(Driven by Master)
t
t1
t1
2
Data In
t
2
1
Byte Enable
CMD
t
2
t2
t1
t1
t
t
2
2
t2
t1
t
3
TRDY/
(Driven by 53C810A)
t
3
STOP/
(Driven by 53C810A)
DEVSEL/
(Driven by 53C810A)
t3
Figure 7-12: Target Write
SYM53C810A Data Manual
7-15
Electrical Characteristics
PCI Interface Timing Diagrams
1
2
3
4
5
6
7
8
9
10
11
12
13
14
CLK
(Driven by System)
GPIO0_FETCH/
(Driven by 53C810A)*
t
t
t
t
9
10
6
t
GNT/
(Driven by Arbiter)
t
FRAME/
(Driven by 53C810A)
t
4
5
t
3
1
Data
In
Data
In
AD/
(Driven by
53C810A-Addr;
Target-Data)
C_BE/
(Driven by 53C810A)
PAR/
(Driven by
53C810A-Addr;
Target-Data)
8
t7
GPIO1_MASTER/
(Driven by 53C810A)*
REQ/
(Driven by 53C810A)
15
Addr Out
Addr Out
t2
t
3
CMD
t
3
t
t
CMD
BE
3
t
BE
1
t2
3
IRDY/
(Driven by 53C810A)
t
3
t
1
TRDY/
(Driven by Target)
STOP/
(Driven by Target)
DEVSEL/
t2
t
t2
1
(Driven by Target)
Figure 7-13: Op Code Fetch, non-burst
7-16
SYM53C810A Data Manual
Electrical Characteristics
PCI Interface Timing Diagrams
1
2
3
4
5
6
7
9
10
11
CLK
(Driven by System)
GPIO0_FETCH/
(Driven by 53C810A)*
t
t
GPIO1_MASTER/
(Driven by 53C810A)*
t
9
t
4
t
FRAME/
(Driven by 53C810A)
t
t
t1
Data
In
3
Data In
Addr Out
t2
t
3
CMD
t
3
3
t
1
In
Out
t
t
CMD
BE
t
PAR/
(Driven by
53C810A-Addr;
Target-Data)
IRDY/
(Driven by 53C810A)
5
3
C_BE/
(Driven by 53C810A)
10
6
GNT/
(Driven by Arbiter)
AD/
(Driven by
53C810A-Addr;
Target-Data)
8
t7
t
REQ/
(Driven by 53C810A)
12
In
t2
3
3
t
1
TRDY/
(Driven by Target)
t2
STOP/
(Driven by Target)
t1
t2
DEVSEL/
(Driven by Target)
Figure 7-14: Burst Op Code Fetch
SYM53C810A Data Manual
7-17
Electrical Characteristics
PCI Interface Timing Diagrams
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
CLK
(Driven by System)
GPIO0_FETCH/
(Driven by 53C810A)*
t10
t9
GPIO1_MASTER/
(Driven by 53C810A)
REQ/
(Driven by 53C810A)
t
GNT/
(Driven by Arbiter)
t
6
t
5
4
t
FRAME/
(Driven by 53C810A)
3
t
t
3
AD/
(Driven by
53C810A-Addr;
Target-Data)
1
Data In
Addr
Out
t2
t3
C_BE/
(Driven by 53C810A)
PAR/
(Driven by
53C810A-Addr;
Target-Data)
Data In
Addr
Out
BE
CMD
CMD
BE
t1
t3
In
Out
Out
In
t2
t
3
IRDY/
(Driven by 53C810A)
TRDY/
(Driven by Target)
t1
t2
STOP/
(Driven by Target)
t1
t2
DEVSEL/
(Driven by Target)
Figure 7-15: Back to Back Read
7-18
SYM53C810A Data Manual
Electrical Characteristics
PCI Interface Timing Diagrams
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
CLK
(Driven by System)
GPIO0_FETCH/
(Driven by 53C810A)*
t
GPIO1_MASTER/
(Driven by 53C810A)*
REQ/
(Driven by 53C810A)
t
t
9
6
t
GNT/
(Driven by Arbiter)
t
FRAME/
(Driven by 53C810A)
4
5
t3
t3
t3
AD/
(Driven by 53C810A)
Addr
Out
Data
Out
Addr
Out
Data
Out
t3
t3
C_BE/
(Driven by 53C810A)
10
CMD
BE
CMD
t3
BE
t3
PAR/
(Driven by 53C810A)
t3
IRDY/
(Driven by 53C810A)
t1
TRDY/
(Driven by Target)
t2
STOP/
(Driven by Target)
t1
t2
DEVSEL/
(Driven by Target)
Figure 7-16: Back to Back Write
SYM53C810A Data Manual
7-19
7-20
DEVSEL/
(Driven by Target)
STOP/
(Driven by Target)
TRDY/
(Driven by Target)
IRDY/
(Driven by 53C810A)
PAR
(Driven by 53C810A)
C_BE/
(Driven by 53C8150A
AD
(Driven by 53C810A)
FRAME
(Driven by 53C810A)
GNT/
(Driven by Arbiter)
REQ/
(Driven by 53C810A)
GPIO1_
MASTER/
(Driven by 53C810A)
GPIO0_
FETCH/
(Driven by 53C810A)
CLK
(Driven by System)
t6
1
2
t4
t5
t9
t3
t3
t3
3
t3
5
t3
t3
CMD
t3
BE
Addr Out Data Out
4
6
t 10
7
8
10
t3
CMD
t1
t1
BE
Addr Out Data Out
9
Data Out
11
t2
t2
12
13
14
16
CMD
BE
Addr Out Data Out
15
17
18
19
Electrical Characteristics
PCI Interface Timing Diagrams
Figure 7-17: Burst Read
SYM53C810A Data Manual
SYM53C810A Data Manual
DEVSEL/
(Driven by Target)
STOP/
(Driven by Target)
TRDY/
(Driven by Target)
IRDY/
(Driven by 53C810A)
PAR
(Driven by 53C810A)
C_BE/
(Driven by 53C810A)
AD
(Driven by 53C810A)
FRAME
(Driven by 53C810A)
GNT/
(Driven by Arbiter)
REQ/
(Driven by 53C810A)
GPIO1_
MASTER/
(Driven by 53C810A)
GPIO0_
FETCH/
(Driven by 53C810A)
CLK
(Driven by System)
t6
1
2
t4
t5
t9
t3
t3
t3
3
t3
5
t3
t3
CMD
t3
BE
Addr Out Data Out
4
6
t 10
7
8
10
t3
CMD
t1
t1
BE
Addr Out Data Out
9
Data Out
11
t2
t2
12
13
14
16
CMD
BE
Addr Out Data Out
15
17
18
19
Electrical Characteristics
PCI Interface Timing Diagrams
Figure 7-18: Burst Write
7-21
Electrical Characteristics
PCI Interface Timings
PCI Interface Timings
Table 7-16: SYM53C810A PCI Timings
Symbol
Parameter
Min
Max
Unit
t1
Shared signal input setup time
7
-
ns
t2
Shared signal input hold time
0
-
ns
t3
CLK to shared signal output valid
-
11
ns
t4
Side signal input setup time
10
-
ns
t5
Side signal input hold time
0
-
ns
t6
CLK to side signal output valid
-
12
ns
t7
CLK high to FETCH/ low
-
20
ns
t8
CLK high to FETCH/ high
-
20
ns
t9
CLK high to MASTER/ low
-
20
ns
t10
CLK high to MASTER/ high
-
20
ns
7-22
SYM53C810A Data Manual
Electrical Characteristics
SCSI Timings
SCSI Timings
Initiator
Asynchronous Send
n
SREQ/
n+1
t2
t1
n
SACK/
t3
SD7-SD0,
SDP/
n+1
t4
Valid n
Valid n+1
Figure 7-19: Initiator Asynchronous Send Waveforms
Table 7-17: Initiator Asynchronous Send Timings (5 MB/s)
Symbol
Parameter
Min
Max
Units
t1
SACK/asserted from SREQ/ asserted
10
-
ns
t2
SACK/deasserted from SREQ/ deasserted
10
-
ns
t3
Data setup to SACK/asserted
55
-
ns
t4
Data hold from SSREQ/deasserted
20
-
ns
SYM53C810A Data Manual
7-23
Electrical Characteristics
SCSI Timings
Initiator
Asynchronous Receive
n
SREQ/
n+1
t1
t2
n
SACK/
t3
SD7-SD0,
SDP/
n+1
t4
Valid n
Valid n+1
Figure 7-20: Initiator Asynchronous Receive Waveforms
Table 7-18: Initiator Asynchronous Receive Timings (5MB/s)
Symbol
Parameter
Min
Max
Units
t1
SACK/asserted from SREQ/asserted
10
-
ns
t2
SACK/deasserted from SREQ/deasserted
10
-
ns
t3
Data setup to SREQ/asserted
0
-
ns
t4
Data hold from SACK/asserted
0
-
ns
7-24
SYM53C810A Data Manual
Electrical Characteristics
SCSI Timings
Target
Asynchronous Send
n
SREQ/
n+1
t2
t1
n
SACK/
t3
SD7-SD0,
SDP/
n+1
t4
Valid n
Valid n+1
Figure 7-21: Target Asynchronous Send Waveforms
Table 7-19: Target Asynchronous Send Timings (5 MB/s)
Symbol
Parameter
Min
Max
Units
t1
SREQ/ deasserted from SACK/ asserted
10
-
ns
t2
SREQ/ asserted from SACK/ deasserted
10
-
ns
t3
Data setup to SREQ/ asserted
55
-
ns
t4
Data hold from SACK/ asserted
20
-
ns
SYM53C810A Data Manual
7-25
Electrical Characteristics
SCSI Timings
Target
Asynchronous Receive
n
SREQ/
n+1
t2
t1
n
SACK/
t3
SD15-SD0,
SDP1/, SDP0/
n+1
t4
Valid n
Valid n+1
Figure 7-22: Target Asynchronous Receive Waveforms
Table 7-20: Target Asynchronous Receive Timings (5 MB/s)
Symbol
Parameter
Min
Max
Units
t1
SREQ/ deasserted from SACK/ asserted
10
-
ns
t2
SREQ/ asserted from SACK/ deasserted
10
-
ns
t3
Data setup to SACK/ asserted
0
-
ns
t4
Data hold from SREQ/ deasserted
0
-
ns
7-26
SYM53C810A Data Manual
Electrical Characteristics
SCSI Timings
Initiator and
Target Synchronous Transfers
t1
SREQ/
or SACK/
n
t3
Send Data
SD7-SD0, SDP/
n+1
t4
Valid n
t5
Receive Data
SD15-SD0,
SDP1/, SDP0/
t2
Valid n+1
t6
Valid n
Valid n+1
Figure 7-23: Initiator and Target Synchronous Transfers
Table 7-21: SCSI-1 Transfers (Single-Ended, 5.0 MB/s)
Symbol
Parameter
Min
Max
Units
t1
Send SREQ/ or SACK/ assertion pulse width
90
-
ns
t2
Send SREQ/ or SACK/ deassertion pulse width
90
-
ns
t1
Receive SREQ/ or SACK/ assertion pulse width
90
-
ns
t2
Receive SREQ/ or SACK/ deassertion pulse width
90
-
ns
t3
Send data setup to SREQ/ or SACK/ asserted
55
-
ns
t4
Send data hold from SREQ/ or SACK/ asserted
100
-
ns
t5
Receive data setup to SREQ/ or SACK/ asserted
0
-
ns
t6
Receive data hold from SREQ/ or SACK/ asserted
45
-
ns
SYM53C810A Data Manual
7-27
Electrical Characteristics
SCSI Timings
Table 7-22: SCSI-2 Fast Transfers (10.0 MB/s (8-bit transfers), 40 MHz clock)
Symbol
Parameter
Min
Max
Units
t1
Send SREQ/ or SACK/ assertion pulse width
35
-
ns
t2
Send SREQ/ or SACK/ deassertion pulse width
35
-
ns
t1
Receive SREQ/ or SACK/ assertion pulse width
20
-
ns
t2
Receive SREQ/ or SACK/ deassertion pulse width
20
-
ns
t3
Send data setup to SREQ/ or SACK/ asserted
33
-
ns
t4
Send data hold from SREQ/ or SACK/ asserted
45
-
ns
t5
Receive data setup to SREQ/ or SACK/ asserted
0
-
ns
t6
Receive data hold from SREQ/ or SACK/ asserted
10
-
ns
Table 7-23: SCSI-2 Fast Transfers (10.0 MB/s (8-bit transfers), 50 MHz clock)
Symbol
Parameter
Min
Max
Units
t1
Send SREQ/ or SACK/ assertion pulse width
35
-
ns
t2
Send SREQ/ or SACK/ deassertion pulse width
35
-
ns
t1
Receive SREQ/ or SACK/ assertion pulse width
20
-
ns
t2
Receive SREQ/ or SACK/ deassertion pulse width
20
-
ns
t3
Send data setup to SREQ/ or SACK/ asserted
33
-
ns
t4
Send data hold from SREQ/ or SACK/ asserted
40
-
ns
t5
Receive data setup to SREQ/ or SACK/ asserted
0
-
ns
t6
Receive data hold from SREQ/ or SACK/ asserted
10
-
ns
* Transfer period bits (bits 6-4 in the SXFER register) are set to zero and the Extra Clock cycle of Data Setup bit (bit 7 in
SCNTL1) is set.
* * Analysis of system configuration is recommended due to reduced driver skew margin in differential systems.
Note: for fast SCSI, set the TolerANT Enable bit (bit 7 in STEST3).
7-28
SYM53C810A Data Manual
Register Summary
Appendix A
Register Summary
Register 00 (80)
Register 02 (82)
SCSI Control Two (SCNTL2)
Read/Write
SCSI Control Zero (SCNTL0)
Read/Write
ARB1
ARB0
START
WATN
EPC
RES
AAP
TRG
7
6
5
4
3
2
1
0
0
0
0
X
0
0
Default>>>
1
1
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
ARB1 (Arbitration mode bit 1)
ARB0 (Arbitration mode bit 0)
START (Start sequence)
WATN (Select with SATN/ on a start sequence)
EPC (Enable parity checking)
Reserved
AAP (Assert SATN/ on parity error)
TRG (Target role)
SDU
RES
RES
RES
RES
RES
RES
RES
7
6
5
4
3
2
1
0
X
X
X
X
X
X
Default>>>
0
X
Bit 7
Bits 6-0
SDU (SCSI Disconnect Unexpected)
Reserved
Register 03 (83)
SCSI Control Three (SCNTL3)
Read/Write
RES
SCF2
SCF1
SCF0
RES
CCF2
CCF1
CCF0
7
6
5
4
3
2
1
0
0
0
X
0
0
0
Default>>>
Register 01 (81)
SCSI Control One (SCNTL1)
Read/Write
X
EXC
ADB
DHP
CON
RST
AESP
IARB
SST
7
6
5
4
3
2
1
0
0
0
0
0
0
0
Bit 7
Bits 6-4
Bit 3
Bits 2-0
0
Reserved
SCF2-0 (Synchronous Clock
Reserved
CCF2-0 (Clock Conversion Factor)
Default>>>
0
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
0
EXC (Extra clock cycle of data setup)
ADB (Assert SCSI data bus)
DHP (Disable Halt on Parity Error or ATN) (Target Only)
CON (Connected)
RST (Assert SCSI RST/ signal)
AESP (Assert even SCSI parity (force bad parity))
IARB (Immediate Arbitration)
SST (Start SCSI Transfer)
SYM53C810A Data Manual
A-1
Register Summary
Register 04 (84)
SCSI Chip ID (SCID)
Read/Write
Register 05 (85)
SCSI Transfer (SXFER)
Read/Write
RES
RRE
SRE
RES
RES
ENC2
ENC1
ENC0
TP2
TP1
TP0
RES
MO3
MO2
MO1
MO0
7
6
5
4
3
2
1
0
7
6
5
4
3
2
1
0
0
X
0
0
0
0
Default>>>
X
Bit 7
Bit 6
Bit 5
Bit 4-3
Bits 2-0
0
Default>>>
0
X
X
0
0
Reserved
RRE (Enable Response to
Reselection)
SRE (Enable Response to Selection)
Reserved
Encoded SYM53C810A Chip SCSI ID, bits 2-0
0
0
0
Bits 7-5
Bit 4
Bits 3-0
TP2-0 (SCSI Synchronous Transfer Period)
Reserved
MO3-MO0 (Max SCSI synchronous offset)
Register 06 (86)
SCSI Destination ID (SDID)
Read/Write
RES
RES
RES
RES
RES
ENC2
ENC1
ENC0
7
6
5
4
3
2
1
0
X
X
X
0
0
0
Default>>>
X
X
Bits 7-3
Bits 2-0
Reserved
Encoded destination SCSI ID
Register 07 (87)
General Purpose (GPREG)
Read/Write
RES
RES
RES
RES
RES
RES
GPIO1
GPIO0
7
6
5
4
3
2
1
0
X
X
X
X
0
0
Default>>>
X
X
Bits 7-2
Bits 1-0
Reserved
GPIO1-GPIO0 (General Purpose)
Register 08 (88)
SCSI First Byte Received (SFBR)
Read/Write
1B7
1B6
1B5
1B4
1B3
1B2
1B1
1B0
7
6
5
4
3
2
1
0
0
0
0
0
0
0
Default>>>
0
A-2
0
SYM53C810A Data Manual
Register Summary
Register 09 (89)
SCSI Output Control Latch (SOCL)
Read /Write
Register 0C (8C)
DMA Status (DSTAT)
Read Only
REQ
ACK
BSY
SEL
ATN
MSG
C/D
I/O
DFE
MDPE
BF
ABRT
SSI
SIR
RES
IID
7
6
5
4
3
2
1
0
7
6
5
4
3
2
1
0
0
0
0
0
X
0
Default>>>
0
Default>>>
0
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
0
0
0
0
0
0
REQ(Assert SCSI REQ/ signal)
ACK(Assert SCSI ACK/ signal)
BSY(Assert SCSI BSY/ signal)
SEL(Assert SCSI SEL/ signal)
ATN(Assert SCSI ATN/ signal)
MSG(Assert SCSI MSG/ signal)
C/D(Assert SCSI C_D/ signal)
I/O(Assert SCSI I_O/ signal)
RES
RES
RES
RES
ENID2
ENID1
ENID0
7
6
5
4
3
2
1
0
Default>>>
X
X
X
0
0
0
Register 0D (8D)
SCSI Status Zero (SSTAT0)
Read Only
ILF
ORF
OLF
AIP
LOA
WOA
RST
SDP0/
7
6
5
4
3
2
1
0
0
0
0
0
0
0
Default>>>
0
Bit 7
Bits 6-3
Bits 2-0
VAL (SCSI Valid Bit)
Reserved
Encoded Destination SCSI ID
REQ
ACK
BSY
SEL
ATN
MSG
C/D
I/O
7
6
5
4
3
2
1
0
X
X
X
X
X
X
Default>>>
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
X
REQ (SREQ/ status)
ACK (SACK/ status)
BSY (SBSY/ status)
SEL (SSEL/ status)
ATN SATN/ status)
MSG (SMSG/ status)
C/D (SC_D/ status)
I/O (SI_O/ status)
SYM53C810A Data Manual
0
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Register 0B (8B)
SCSI Bus Control Lines (SBCL)
Read Only
X
DFE (DMA FIFO empty)
MDPE (Master Data Parity Error)
BF (Bus fault)
ABRT (Aborted)
SSI (Single step interrupt)
SIR (SCRIPTS interrupt
instruction received)
Reserved
IID (Illegal instruction detected)
Bit 1
Bit 0
VAL
X
0
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Register 0A (8A)
SCSI Selector ID (SSID)
Read Only
0
1
ILF (SIDL full)
ORF (SODR full)
OLF (SODL full)
AIP (Arbitration in progress)
LOA (Lost arbitration)
WOA (Won arbitration)
RST/ (SCSI RST/ signal)
SDP/ (SCSI SDP/ parity signal)
Register 0E (8E)
SCSI Status One (SSTAT1)
Read Only
FF3
FF2
FF1
FF0
SDP0L
MSG
C/D
I/O
7
6
5
4
3
2
1
0
0
0
X
X
X
X
Default>>>
0
Bits 7-4
Bit 3
Bit 2
Bit 1
Bit 0
0
FF3-FF0 (FIFO flags)
SDPL (Latched SCSI parity)
MSG (SCSI MSG/ signal)
C/D (SCSI C_D/ signal)
I/O (SCSI I_O/ signal)
A-3
Register Summary
Register 0F (8F)
SCSI Status Two (SSTAT2)
(Read Only)
Register 1A (9A)
Chip Test Two (CTEST2)
Read Only
RES
RES
RES
RES
RES
RES
LDSC
RES
DDIR
SIGP
CIO
CM
RES
TEOP
DREQ
DACK
7
6
5
4
3
2
1
0
7
6
5
4
3
2
1
0
X
X
0
0
0
1
Default>>>
X
Default>>>
X
Bits 7-2
Bit 1
Bit 0
X
X
X
X
1
X
Reserved
LDSC (Last Disconnect)
Reserved
ABRT
SRST
SIGP
SEM
CON
INTF
SIP
DIP
7
6
5
4
3
2
1
0
0
0
0
0
0
0
Default>>>
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
V0
FLF
CLF
FM
WRIE
5
4
3
2
1
0
X
X
0
0
0
0
Default>>>
X
X
V3-V0 (Chip revision level)
FLF (Flush DMA FIFO)
CLF (Clear DMA FIFO)
FM (Fetch pin mode)
WRIE (Write and Invalidate Enable)
RES
BO6
BO5
BO4
Bo3
BO2
BO1
BO0
7
6
5
4
3
2
1
0
0
0
0
0
0
0
Default>>>
FMT2
FMT1
FMT0
FFL3
FFL2
FFL1
FFL0
7
6
5
4
3
2
1
0
1
1
0
0
0
0
Default>>>
A-4
V1
6
Register 20 (A0)
DMA FIFO (DFIFO)
Read/Write
FMT3
Bits 7-4
Bits 3-0
V2
7
Registers 1C-1F (9C-9F)
Temporary (TEMP)
Read/Write
Register 19 (99)
Chip Test One (CTEST1)
Read Only
1
V3
Bits 7-4
Bit 3
Bit 2
Bit 1
Bit 0
ABRT (Abort operation)
SRST (Software reset)
SIGP (Signal process)
SEM (Semaphore)
CON (Connected)
INTF (Interrupt on the Fly)
SIP (SCSI interrupt pending)
DIP (DMA interrupt pending)
Register 18 (98)
Chip Test Zero (CTEST0)
Read/Write
1
DDIR (Data transfer direction)
SIGP (Signal process)
CIO (Configured as I/O)
CM (Configured as memory)
Reserved
TEOP (SCSI true end of process)
DREQ (Data request status)
DACK (Data acknowledge status)
Register 1B (9B)
Chip Test Three (CTEST3)
Read/Write
Register 14 (94)
Interrupt Status (ISTAT)
(Read/Write)
0
0
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Registers 10-13 (90-93)
Data Structure Address (DSA)
Read/Write
0
0
X
Bit 7
Bits 6-0
0
Reserved
BO6-BO0 (Byte offset counter)
FMT3-0 (Byte empty in DMA FIFO)
FFL3-0 (Byte full in DMA FIFO)
SYM53C810A Data Manual
Register Summary
Register 21 (A1)
Chip Test Four (CTEST4)
Read/Write
Registers 28-2B (A8-AB)
DMA Next Address (DNAD)
Read/Write
BDIS
ZMOD
ZSD
SRTM
MPEE
FBL2
FBL1
FBL0
7
6
5
4
3
2
1
0
0
0
0
0
0
0
Default>>>
0
0
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bits 2-0
BDIS (Burst Disable)
ZMOD (High impedance mode)
ZSD (SCSI Data High Impedance)
SRTM (Shadow Register Test Mode)
MPEE (Master Parity Error Enable)
FBL2-FBL0 (FIFO byte control)
Registers 30-33 (B0-B3)
DMA SCRIPTS Pointer Save (DSPS)
Read/Write
Registers 34-37 (B4-B7)
Scratch Register A (SCRATCH A)
Read/Write
Register 22 (A2)
Chip Test Five (CTEST5)
Read/Write
ADCK
BBCK
RES
MASR
DDIR
RES
RES
RES
7
6
5
4
3
2
1
0
X
0
0
X
X
X
Default>>>
0
0
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bits 2-0
ADCK (Clock address incrementor)
BBCK (Clock byte counter)
Reserved
MASR (Master control for set or reset pulses)
DDIR (DMA direction)
Reserved
DF6
DF5
DF4
DF3
DF2
DF1
DF0
6
5
4
3
2
1
0
0
0
0
0
0
0
Default>>>
DF7-DF0 (DMA FIFO)
Registers 24-26 (A4-A6)
DMA Byte Counter (DBC)
Read/Write
Register 27 (A7)
DMA Command (DCMD)
Read/Write
BL0
SIOM
DIOM
ERL
ERMP
BOF
MAN
7
6
5
4
3
2
1
0
0
0
0
0
0
0
BL1-BL0 (Burst length)
SIOM (Source I/O-Memory Enable)
DIOM (Destination I/O-Memory Enable)
ERL (Enable Read Line)
ERMP (Enable Read Multiple)
BOF (Burst Op Code Fetch Enable)
MAN (Manual Start Mode)
Register 39 (B9)
DMA Interrupt Enable (DIEN)
Read/Write
RES
MDPE
BF
ABRT
SSI
SIR
RES
IID
7
6
5
4
3
2
1
0
0
0
0
0
X
0
Default>>>
X
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
SYM53C810A Data Manual
0
Bit 7-6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
7
Bits 7-0
BL1
0
DF7
0
Register 38 (B8)
DMA Mode (DMODE)
Read/Write
Default>>>
Register 23 (A3)
Chip Test Six (CTEST6)
Read/Write
0
Registers 2C-2F (AC-AF)
DMA SCRIPTS Pointer (DSP)
Read/Write
0
Reserved
MDPE (Master Data Parity Error)
BF (Bus fault)
ABRT (Aborted)
SSI (Single step interrupt)
SIR (SCRIPTS interrupt
instruction received
Reserved
IID (Illegal instruction detected)
A-5
Register Summary
Register 3A (BA)
Scratch Byte Register (SBR)
Read/Write
Register 41 (C1)
SCSI Interrupt Enable One (SIEN1)
Read/Write
Register 3B (BB)
DMA Control (DCNTL)
Read/Write
PFEN
SSM
IRQM
STD
IRQD
COM
7
6
5
4
3
2
1
0
0
0
0
0
0
0
Default>>>
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
RES
RES
RES
STO
GEN
HTH
6
5
4
3
2
1
0
X
X
X
0
0
0
X
PFF
0
RES
7
Default>>>
CLSE
0
RES
CLSE (Cache Line Size Enable)
PFF (Pre-Fetch Flush)
PFEN (Pre-fetch Enable)
SSM (Single-step mode)
IRQM (IRQ Mode)
STD (Start DMA operation)
IRQD (IRQ Disable)
COM (53C700 compatibility)
Bits 7-3
Bit 2
Bit 1
Bit 0
M/A
CMP
SEL
RSL
SGE
UDC
RST
PAR
7
6
5
4
3
2
1
0
0
0
0
0
0
0
Default>>>
M/A
CMP
SEL
RSL
SGE
UDC
RST
PAR
7
6
5
4
3
2
1
0
0
0
0
0
0
0
Default>>>
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
M/A (Initiator Mode: Phase Mismatch; Target
Mode: SATN/ Active)
CMP (Function Complete)
SEL (Selected)
RSL (Reselected)
SGE (SCSI Gross Error)
UDC (Unexpected Disconnect)
RST (SCSI RST/ Received)
PAR (Parity Error)
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Register 40 (C0)
SCSI Interrupt Enable Zero (SIEN0)
Read/Write
Bit 7
0
Bit 7
Register 3C-3F (BC-BF)
Adder Sum Output (ADDER)
Read Only
0
Reserved
STO (Selection or Reselection Time-out)
GEN (General Purpose Timer Expired)
HTH (Handshake to Handshake timer Expired)
Register 42 (C2)
SCSI Interrupt Status Zero (SIST0)
Read Only
0
0
X
M/A (SCSI Phase Mismatch Initiator Mode; SCSI ATN
Condition - Target Mode)
CMP (Function Complete)
SEL (Selected)
RSL (Reselected)
SGE (SCSI Gross Error)
UDC (Unexpected Disconnect)
RST (SCSI Reset Condition)
PAR (SCSI Parity Error)
Register 43 (C3)
SCSI Interrupt Status One (SIST1)
Read Only
RES
RES
RES
RES
RES
STO
GEN
HTH
7
6
5
4
3
2
1
0
X
X
X
0
0
0
Default>>>
X
Bits 7-3
Bit 2
Bit 1
Bit 0
X
Reserved
STO (Selection or Reselection Time-out)
GEN (General Purpose Timer Expired)
HTH (Handshake-to-Handshake Timer Expired)
Register 44 (C4)
SCSI Longitudinal Parity (SLPAR)
Read/Write
A-6
SYM53C810A Data Manual
Register Summary
Register 46 (C6)
Memory Access Control (MACNTL)
Read/Write
Register 4A (CA)
Response ID (RESPID)
Read/Write
TYP3
TYP2
TYP1
TYP0
DWR
DRD
PSCPT
SCPTS
7
6
5
4
3
2
1
0
0
0
0
0
0
0
Default>>>
0
1
Bits 7-4
Bit 3
Bit 2
Bit 1
Bit 0
TYP3-0 (Chip Type)
DWR (DataWR)
DRD (DataRD)
PSCPT (Pointer SCRIPTS)
SCPTS (SCRIPTS)
Register 4C (CC)
SCSI Test Zero (STEST0)
Read Only
RES
SSAID
2
SSAID
1
SSAID
0
SLT
ART
SOZ
SOM
7
6
5
4
3
2
1
0
X
X
0
X
1
1
Default>>>
X
Register 47 (C7)
General Purpose Pin Control (GPCNTL)
Read/Write
ME
FE
RES
RES
RES
RES
GPIO1
GPIO0
7
6
5
4
3
2
1
0
X
0
1
1
1
1
X
Bit 7
Bits 6-4
Bit 3
Bit 2
Bit 1
Bit 0
Reserved
SSAID (SCSI Selected As ID)
SLT (Selection response logic test)
ART (Arbitration Priority Encoder Test)
SOZ (SCSI Synchronous Offset Zero)
SOM (SCSI Synchronous Offset Maximum)
Default>>>
0
0
Bit 7
Bit 6
Bit 5
Bits 1-0
Master Enable
Fetch Enable
Reserved
GPIO1_EN– GPIO0_EN (GPIO Enable)
Register 4D (CD)
SCSI Test One (STEST1)
Read/Write
SCLK
SISO
RES
RES
RES
RES
RES
RES
7
6
5
4
3
2
1
0
X
X
X
X
X
X
Default>>>
0
Register 48 (C8)
SCSI Timer Zero (STIME0)
Read /Write
HTH
HTH
HTH
HRH
SEL
SEL
SEL
SEL
7
6
5
4
3
2
1
0
0
0
0
0
0
0
Default>>>
0
0
Bits 7-4
Bits 3-0
HTH (Handshake-to-Handshake Timer Period)
SEL (Selection Time-Out)
RES
RES
RES
GEN3
GEN2
GEN1
GEN0
7
6
5
4
3
2
1
0
X
X
0
0
0
0
Default>>>
Bits 7-4
Bits 3-0
Reserved
GEN3-0 (General Purpose Timer Period)
SYM53C810A Data Manual
SCLK
SISO (SCSI Isolation Mode)
Reserved
Register 4E (CE)
SCSI Test Two (STEST2)
Read/Write
SCE
ROF
RES
SLB
SZM
RES
EXT
LOW
7
6
5
4
3
2
1
0
X
0
0
X
0
0
0
RES
X
Bit 7
Bit 6
Bits 5-0
Default>>>
Register 49 (C9)
SCSI Timer One (STIME1)
Read/Write
X
0
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
0
SCE (SCSI Control Enable)
ROF (Reset SCSI Offset)
Reserved
SLB (SCSI Loopback Mode)
SZM (SCSI High-Impedance Mode)
Reserved
EXT( Extend SREQ/SACK
filtering)
LOW (SCSI Low level Mode)
A-7
Register Summary
Register 4F (CF)
SCSI Test Three (STEST3)
Read/Write
TE
STR
HSC
DSI
RES
TTM
CSF
STW
7
6
5
4
3
2
1
0
0
0
X
0
0
0
Default>>>
0
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
0
TE (TolerANT Enable)
STR (SCSI FIFO Test Read)
HSC (Halt SCSI Clock)
DSI (Disable Single Initiator Response)
Reserved
TTM (Timer Test Mode)
CSF (Clear SCSI FIFO)
STW (SCSI FIFO Test Write)
Register 50 (D0)
SCSI Input Data Latch (SIDL)
Read Only
Registers 54 (D4)
SCSI Output Data Latch (SODL)
Read/Write
Registers 58 (D8)
SCSI Bus Data Lines (SBDL)
Read Only
Registers 5C-5F (DC-DF)
Scratch Register B (SCRATCHB)
(Read/Write)
A-8
SYM53C810A Data Manual
Mechanical Drawing
Appendix B
Mechanical Drawing
23.9 ± 0.25
20.0 ± 0.10
18.85
0.22 min
0.38 max
Pin 81
17.9
± 0.25
14.0 12.35
± 0.1
Pin 51
100-Pin Quad Flat Pack
0.65
Pin 31
Pin 1
min
0.13
2.8
± 0.025
1.3
± 0.025
0 0 7
0.8 ± 0.15
SYM53C810A Data Manual
B-1
Mechanical Drawing
B-2
SYM53C810A Data Manual
Index
Index
Numerics
Assert SATN/ on parity error bit 5-6
3.3/5 Volt PCI interface 2-3
Assert SCSI ACK bit 5-15
53C700 compatibility bit 5-35
Assert SCSI ATN/ bit 5-15
A
Assert SCSI BSY/ bit 5-15
AAP bit 5-6
Abort operation bit 5-20
Aborted bit 5-17, 5-33
ABRT bit 5-17, 5-20, 5-33
absolute maximum stress ratings 7-1
AC characteristics 7-9–7-10
clock timing 7-9
interrupt output 7-10
Assert SCSI C_D/ bit 5-15
Assert SCSI data bus bit 5-7
Assert SCSI I_O/ bit 5-15
Assert SCSI MSG/ bit 5-15
Assert SCSI REQ/ signal bit 5-15
Assert SCSI RST/ signal bit 5-7
Assert SCSI SEL/ bit 5-15
ATN bit 5-15, 5-16
ACK bit 5-15, 5-16
B
active negation. See TolerANT
BBCK bit 5-27
ADB bit 5-7
BDIS bit 5-26
ADCK bit 5-27
benefits summary 1-3
ADDER register 5-35
BF bit 5-16, 5-33
Adder Sum Output register 5-35
bidirectional signals 7-5–??
Additional Interface Pins 4-7
BL1-BL0 bits 5-31
Address and Data Pins 4-4
Block Move Instructions 6-4
AESP bit 5-7
BO6-BO0 bits 5-26
AIP bit 5-18
BOF bit 5-32
ARB1-0 bits 5-5
BSY bit 5-15, 5-16
arbitration
arbitration mode bits 5-5
arbitration pins 4-5
Burst Disable bit 5-26
Arbitration in progress bit 5-18
Bus fault bit 5-16, 5-33
Arbitration mode bits 5-5
Byte empty in DMA FIFO bits 5-23
Arbitration Priority Encoder Test bit 5-44
Byte full in DMA FIFO bits 5-23
ART bit 5-44
Byte offset counter bits 5-26
Burst length bits 5-31
Burst Mode Fetch Enable bit 5-32
Assert even SCSI parity (force bad parity) bit 5-7
SYM53C810A Data Manual
I-1
Index
C
CTEST4 register 5-26
C_D bit 5-15, 5-16, 5-19
CTEST5 register 5-27
Cache Line Size Enable bit 5-34, A-6
CTEST6 register 5-28
cache mode, see PCI cache mode 3-2
D
capacitance 7-3
DACK bit 5-24
CCF2-0 bits 5-10
Data acknowledge status bit 5-24
chip block diagram 1-5
data path 2-7
chip revision level bits 5-24
Data request status bit 5-24
Chip Test Five register 5-27
Data Structure Address register 5-20
Chip Test Four register 5-26
Data transfer direction bit 5-23
Chip Test One register 5-23
DataRD bit 5-41
Chip Test Six register 5-28
Chip Test Two register 5-23
DataWR bit
DWR bit 5-41
Chip Test Zero register 5-22
DBC register 5-28
Chip Type bits 5-41
CM bit 5-23
DC characteristics 7-1
absolute maximum stress ratings 7-1
bidirectional signals 7-5
capacitance 7-3
input signals 7-3
operating conditions 7-2
output signals 7-4
SCSI signals 7-2
CMP bit 5-36, 5-38
DCMD register 5-29
COM bit 5-35
DCNTL register 5-34
CON bit 5-7, 5-21
DDIR bit 5-23, 5-27
configuration registers. See PCI configuration registers
Destination I/O-Memory Enable bit 5-32
Configured as I/O bit 5-23
DF7-DF0 bits 5-28
Configured as memory bit 5-23
DFE bit 5-16
Connected bit 5-7, 5-21
DFIFO register 5-26
CSF bit 5-47
DHP bit 5-7
CTEST0 register 5-22
DIEN register 5-33
CTEST1 register 5-23
DIOM bit 5-32
CTEST2 register 5-23
DIP bit 5-22
CIO bit 5-23
Clear SCSI FIFO bit 5-47
Clock address incrementor bit 5-27
Clock byte counter bit 5-27
Clock Conversion Factor bits 5-10
CLSE bit 5-34, A-6
determining the data transfer rate 2-11
Disable Halt on Parity Error or ATN bit 5-7
Disable Single Initiator Response bit 5-47
I-2
SYM53C810A Data Manual
Index
DMA Byte Counter register 5-28
ERL bit 5-32
DMA Command register 5-29
Error Reporting Pins 4-6
DMA Control register 5-34
EXC bit 5-7
DMA core 2-1
EXT bit 5-46
DMA direction bit 5-27
Extend SREQ/SACK filtering bit 5-46
DMA FIFO 2-6
Extra clock cycle of data setup bit 5-7
DMA FIFO bits 5-28
F
DMA FIFO empty bit 5-16
FBL2-FBL0 bits 5-27
DMA FIFO register 5-26
Fetch Enable bit 5-41
DMA Interrupt Enable register 5-33
fetch op code bursting 2-3
DMA interrupt pending bit 5-22
FF3-FF0 bits 5-18
DMA Mode register 5-31
FFL3-0 bits 5-23
DMA Next Address register 5-29
FIFO byte control bits 5-27
DMA SCRIPTS Pointer register 5-30
FIFO flags bits 5-18
DMA SCRIPTS Pointer Save register 5-30
FMT3-0 bits 5-23
DMA Status register 5-16
Function Complete bit 5-36, 5-38
DMODE register 5-31
DNAD register 5-29
DRD bit 5-41
DREQ bit 5-24
DSA register 5-20
DSI bit 5-47
DSP register 5-30
DSPS register 5-30
DSTAT register 5-16
G
GEN bit 5-37, 5-40
GEN3-0 bits 5-43
general description 1-1
General purpose bits 5-14
General Purpose Pin Control register 5-41
General Purpose register 5-14
General Purpose Timer Expired bit 5-37, 5-40
General Purpose Timer Period bits 5-43
E
GPCNTL register 5-41
ease of use 1-3
GPIO Enable bits 5-41
Enable parity checking bit 5-6
GPIO1-0 bits 5-14
Enable Read Line bit 5-32
GPIO1EN_GPIO0EN bits 5-41
Enable Read Multiple bit 5-32, A-5
GPREG register 5-14
Enable Response to Reselection bit 5-11
Enable Response to Selection bit 5-11
Encoded Chip SCSI ID, bits 2-0 5-11
Encoded Destination SCSI ID bits 5-15
Encoded destination SCSI ID bits 5-13
EPC bit 5-6
SYM53C810A Data Manual
H
Halt SCSI Clock bit
HSC bit 5-46
Handshake to Handshake timer Expired bit 5-38
Handshake-to-Handshake Timer Expired bit 5-40
I-3
Index
Handshake-to-Handshake Timer Period bits 5-42
IRQ Disable bit 5-34, A-6
High impedance mode bit 5-26
IRQ Mode bit 5-34
HTH bit 5-38, 5-40
IRQD bit 5-34, A-6
I
IRQM bit 5-34
I/O bit 5-19
ISTAT register 5-20
I/O Instructions 6-8
L
I_O bit 5-15
Last Disconnect bit 5-19
IARB bit 5-8
Latched SCSI parity bit 5-18
IID bit 5-17, 5-33
LDSC bit 5-19
Illegal instruction detected bit 5-17, 5-33
LOA bit 5-18
Immediate arbitration bit 5-8
Initiator Mode
Phase Mismatch 5-38
Load and Store instructions
no flush option 6-24
prefetch unit and Store instructions 2-2, 6-24
input signals 7-3
load and store instructions 6-24
instruction prefetch. See SCRIPTS instruction
prefetching
Lost arbitration bit 5-18
instruction set 6-1–6-25
instructions
block move 6-4
I/O 6-8
load and store 6-24
memory move 6-21
read/write 6-14
transfer control 6-17
LOW bit 5-46
M
M/A bit 5-36, 5-38
MACNTL register 5-41
MAN bit 5-32
Manual Start Mode bit 5-32
MASR bit 5-27
Master control for set or reset pulses bit 5-27
Interrupt on the Fly bit 5-21
Master Data Parity Error bit 5-16
MDPE bit 5-33
interrupt output timings 7-10
Master Enable bit 5-41
Interrupt Status register 5-20
Master Parity Error Enable bit 5-27
interrupts
fatal vs. non-fatal interrupts 2-14
halting 2-15
IRQ Disable bit 2-14, 5-34, A-6
masking 2-14
polling vs. hardware 2-13
registers 2-13
stacked interrupts 2-15
Max SCSI Synchronous Offset bits 5-13
INTF bit 5-21
Memory Read Multiple command 3-4
Interface Control Pins 4-5
I-4
MDPE bit 5-16
Memory Access Control register 5-41
Memory Move Instructions 6-21
Memory Move instructions
and SCRIPTS instruction prefetching 2-2
No Flush option 6-23
Memory Read Line command 3-4
SYM53C810A Data Manual
Index
Memory Write and Invalidate command 3-3
Write and Invalidate Mode bit 3-7
move to/from SFBR cycles 6-14
MPEE bit 5-27
MSG bit 5-15, 5-16, 5-19
N
NFMMOV instruction 6-23
No Flush Memory-to-Memory Move 6-23
O
OLF bit 5-17
op code fetch bursting 2-2
operating conditions 7-2
operating registers
Adder Sum Output 5-35
Chip Test Five 5-27
Chip Test Four 5-26
Chip Test One 5-23
Chip Test Six 5-28
Chip Test Three 5-24
Chip Test Two 5-23
Chip Test Zero 5-22
Data Structure Address 5-20
DMA Byte Counter 5-28
DMA Command 5-29
DMA Control 5-34
DMA FIFO 5-26
DMA Interrupt Enable 5-33
DMA Mode 5-31
DMA Next Address 5-29
DMA SCRIPTS Pointer 5-30
DMA SCRIPTS Pointer Save 5-30
DMA Status 5-16
DMA Watchdog Timer 5-33
general information 5-1
General Purpose 5-14
General Purpose Pin Control 5-41
Interrupt Status 5-20
SYM53C810A Data Manual
Memory Access Control 5-41
register address map 5-4
Response ID Zero 5-43
Scratch Register A 5-31
Scratch Register B 5-49
SCSI Bus Control Lines 5-16
SCSI Bus Data Lines 5-48
SCSI Chip ID 5-11
SCSI Control One register 5-7
SCSI Control Register Two 5-9
SCSI Control Three 5-9
SCSI Control Zero 5-5
SCSI Destination ID 5-13
SCSI First Byte Received 5-14
SCSI Input Data Latch 5-47
SCSI Interrupt Enable One 5-37
SCSI Interrupt Enable Zero 5-36
SCSI Interrupt Status One 5-40
SCSI Interrupt Status Zero 5-38
SCSI Longitudinal Parity 5-40
SCSI Output Control Latch 5-15
SCSI Output Data Latch 5-48
SCSI Selector ID 5-15
SCSI Status One 5-18
SCSI Status Two 5-19
SCSI Status Zero 5-17
SCSI Test One 5-45
SCSI Test Three 5-46
SCSI Test Two 5-45
SCSI Test Zero 5-44
SCSI Timer One 5-43
SCSI Timer Zero 5-42
SCSI Transfer 5-11
Temporary Stack 5-25
ORF bit 5-17
output signals 7-4
I-5
Index
Latency Timer 3-10
Max_Lat 3-11
Min_Gnt 3-11
Revision ID 3-10
Status 3-8
Vendor ID 3-7
P
PAR bit 5-37, 5-39
Parity 2-3–2-5
Assert even SCSI parity bit 5-7
Assert SATN/ on parity error bit 5-6
Disable Halt on Parity Error bit 5-7
Enable parity checking bit 5-6
Master Data Parity Error bit 5-33
Master Parity Error Enable bit 5-27
Parity Error bit 5-39
SCSI Parity Error bit 5-37
PCI configuration space 3-1
Parity Error bit 5-39
Phase Mismatch bit 5-38
PCI
addressing 3-1
bus commands and functions supported 3-1
pins
additional interface pins 4-7
address and data pins 4-4
arbitration pins 4-5
error reporting pins 4-6
interface control pins 4-5
SCSI pins 4-6
system pins 4-4
PCI addressing 3-1
PCI bus commands and functions supported 3-1
PCI cache mode 2-3, 3-2
Cache Line Size Enable bit 5-34, A-6
Cache Line Size register 3-10
Enable Read Line bit 5-32
Enable Read Multiple bit 5-32, A-5
Memory Read Line command 3-4
Memory Read Multiple command 3-4
Memory Write and Invalidate command 3-3
Write and Invalidate Mode bit 3-7
Write and Invalidate Enable bit 5-25, A-4
PCI commands 3-1
PCI configuration registers 3-6–3-11
Base Address One (Memory) 3-11
Base Address Zero (I/O) 3-11
Cache Line Size 3-10
Class Code 3-10
Command 3-7
Device ID 3-7
Header Type 3-11
Interrupt Line 3-11
Interrupt Pin 3-11
I-6
PCI I/O space 3-1
PCI memory space 3-1
PFEN bit 5-34, A-6
PFF bit 5-34, A-6
Pointer SCRIPTS bit
PSCPT bit 5-41
Power and Ground Pins 4-2
Pre-fetch Enable bit 5-34, A-6
Pre-Fetch Flush bit 5-34, A-6
prefetching
prefetching. See SCRIPTS instruction
R
Read Multiple commands
Enable Read Multiple bit 5-32, A-5
Read/Write Instructions 6-14
read-modify-write cycles 6-14
register addresses
operating registers
00h 5-5
01h 5-7
SYM53C810A Data Manual
Index
02h 5-9
03h 5-9
04h 5-11
05h 5-11
06h 5-13
07h 5-14
08h 5-14
09h 5-15
0Ah 5-15
0Bh 5-16
0Ch 5-16
0Dh 5-17
0Eh 5-18
0Fh 5-19
10h-13h 5-20
14h 5-20
18 5-22
19h 5-23
1Ah 5-23
1Ch-1Fh 5-25
20h 5-26
21h 5-26
22h 5-27
23h 5-28
24h-26h 5-28
27h 5-29
28h-2Bh 5-29
2Ch-2Fh 5-30
30h-33h 5-30
34h-37h 5-31
38h 5-31
39h 5-33
3Ah 5-33
3Bh 5-34
3Ch-3Fh 5-35
40h 5-36
41h 5-37
42h 5-38
43h 5-40
44h 5-40
46h 5-41
47h 5-41
SYM53C810A Data Manual
48h 5-42
49h 5-43
4Ah 5-43
4Ch 5-44
4Dh 5-45
4Eh 5-45
4Fh 5-46
50h 5-47
54h 5-48
58h 5-48
5Ch-5Fh 5-49
PCI configuration registers
00h 3-7
02h 3-7
04h 3-7
06h 3-8
08h 3-10
09h 3-10
0Ch 3-10
0Dh 3-10
0Eh 3-11
10h 3-11
14h 3-11
3Ch 3-11
3Dh 3-11
3Eh 3-11
3Fh 3-11
register bits
53C700 compatibility 5-35
Abort operation 5-20
Aborted 5-17, 5-33
Arbitration in progress 5-18
Arbitration mode 5-5
Arbitration Priority Encoder Test 5-44
Assert even SCSI parity 5-7
Assert SATN/ on parity error 5-6
Assert SCSI ACK 5-15
Assert SCSI ATN/ 5-15
Assert SCSI BSY/ 5-15
I-7
Index
Assert SCSI C_D/ 5-15
Assert SCSI data bus 5-7
Assert SCSI I_O/ 5-15
Assert SCSI MSG/ 5-15
Assert SCSI REQ/ signal 5-15
Assert SCSI RST/ signal 5-7
Assert SCSI SEL/ 5-15
Burst Disable 5-26
Burst length 5-31
Burst Mode Fetch Enable 5-32
Bus fault 5-33
Byte Empty in DMA FIFO 5-23
Byte full in DMA FIFO 5-23
Byte offset counter 5-26
Cache Line Size Enable 5-34, A-6
Chip revision level 5-24
Chip Type 5-41
Clear DMA FIFO 5-24
Clear SCSI FIFO 5-47
Clock address incrementor 5-27
Clock byte counter 5-27
Clock Conversion Factor 5-10
Configured as I/O 5-23
Configured as memory 5-23
Connected 5-7, 5-21
DACK 5-24
Data transfer direction 5-23
DataRD 5-41
DataWR 5-41
Destination I/O-Memory Enable 5-32
Disable Halt on Parity Error 5-7
Disable Single Initiator Response 5-47
DMA direction 5-27
DMA FIFO 5-28
DMA FIFO empty bit 5-16
DMA interrupt pending 5-22
DREQ 5-24
Enable parity checking 5-6
I-8
Enable Read Line 5-32
Enable Read Multiple 5-32, A-5
Enable Response to Reselection 5-11
Enable Response to Selection 5-11
Encoded Chip SCSI ID, bits 2-0 5-11
Encoded destination ID 5-13
Encoded Destination SCSI ID 5-15
Encoded NCR 53C810A Chip SCSI ID, bits
2-0 5-11, A-2
Extend SREQ/SACK filtering 5-46
Extra clock cycle of data setup 5-7
Fetch Enable 5-41
Fetch pin mode 5-24
FIFO byte control 5-27
FIFO flags 5-18
Flush DMA FIFO 5-24
Function Complete 5-36, 5-38
General Purpose Timer Expired 5-37, 5-40
General Purpose Timer Period 5-43
GPIO Enable 5-41
GPIO1-GPIO0 5-14, A-2
Halt SCSI Clock 5-46
Handshake to Handshake timer Expired 5-38
Handshake-to-Handshake Timer Expired 5-40
Handshake-to-Handshake Timer Period 5-42
High impedance mode 5-26
Illegal instruction detected 5-17, 5-33
Immediate arbitration 5-8
Interrupt on the Fly 5-21
IRQ disable 5-34, A-6
IRQ Mode 5-34
Last Disconnect 5-19
Latched SCSI parity 5-18
Lost arbitration 5-18
Manual Start Mode 5-32
Master control for set or reset pulses 5-27
Master Data Parity Error 5-16, 5-33
Master Enable 5-41
SYM53C810A Data Manual
Index
Master Parity Error Enable 5-27
Max SCSI Synchronous Offset 5-13
Parity Error 5-39
Phase Mismatch or SATN/ Active 5-38
Pointer SCRIPTS 5-41
Pre-Fetch Enable 5-34, A-6
Pre-Fetch Flush 5-34, A-6
Reselected 5-36, 5-39
Reset SCSI Offset 5-45
SACK/ status 5-16
SATN/ status 5-16
SBSY/ status 5-16
SC_D/ status 5-16
SCLK 5-45
SCRIPTS 5-41
SCRIPTS interrupt instruction received 5-17,
5-33
SCSI C_D/ signal 5-19
SCSI Control Enable 5-45
SCSI Data High Impedance 5-26
SCSI Disconnect Unexpected 5-9
SCSI FIFO Test Read 5-46
SCSI FIFO Test Write 5-47
SCSI Gross Error 5-36, 5-39
SCSI High-Impedance Mode 5-45
SCSI I_O/ signal 5-19
SCSI interrupt pending 5-22
SCSI Isolation 5-45, A-7
SCSI Loopback Mode 5-45
SCSI Low level Mode 5-46
SCSI MSG/ signal 5-19
SCSI Parity Error 5-37
SCSI Phase Mismatch or SCSI ATN Condition 5-36
SCSI Reset Condition 5-37
SCSI RST/ Received 5-39
SCSI RST/ signal 5-18
SCSI SDP/ signal 5-18
SYM53C810A Data Manual
SCSI Selected As ID 5-44, A-7
SCSI Synchrnous Offset Zero 5-44
SCSI Synchronous Offset Maximum 5-44
SCSI Synchronous Transfer Period 5-11
SCSI true end of process 5-24
SCSI Valid 5-15
Select with SATN/ on a start sequence 5-6
Selected 5-36, 5-39
Selection or Reselection Time-Out 5-37
Selection or Reselection Time-out 5-40
Selection response logic test 5-44
Selection Time-Out 5-42
Semaphore 5-21
Shadow Register Test Mode 5-26
SI_O/ status 5-16
SIDL full 5-17
Signal process 5-21, 5-23
Single step interrupt 5-17, 5-33
Single-step mode 5-34
SMSG/ status 5-16
SODL full 5-17
SODR full 5-17
Software reset 5-20
Source I/O-Memory Enable 5-31
SREQ/ status 5-16
SSEL/ status 5-16
Start DMA operation 5-34
Start SCSI transfer 5-8
Start sequence 5-5
Synchronous Clock Conversion Factor bits 5-9
Target mode 5-6
Unexpected Disconnect 5-36, 5-39
WATN 5-6
Won arbitration 5-18
Write and Invalidate Enable 5-25, A-4
Registers
see operating registers
reliability 1-4
I-9
Index
REQ bit 5-15, 5-16
reselect
during reselection 2-9
response to 2-9
sample operation 6-2
SCRIPTS bit 5-41
Reset SCSI Offset bit 5-45
SCRIPTS instruction prefetching
No Flush Memory Move instruction 6-23
Pre-fetch Enable bit 5-34, A-6
Pre-Fetch Flush bit 5-34, A-6
RESPID0 register 5-43
SCRIPTS interrupt instruction received bit 5-17,
Reselected bit 5-36, 5-39
Response ID Zero register 5-43
revision level bits 5-24
ROF bit 5-45
RRE bit 5-11
RSL bit 5-36, 5-39
RST bit 5-7, 5-37, 5-39
RST/ bit 5-18
5-33
SCRIPTS processor 2-1
performance 2-1
SCSI
pins 4-6
termination 2-9
SCSI ATN Condition - Target Mode 5-36
SCSI Bus Control Lines register 5-16
S
SCSI Bus Data Lines register 5-48
SACK/ status bit 5-16
SCSI bus interface 2-9
SATN/ active bit 5-38
SCSI C_D/ signal 5-19
SATN/ status bit 5-16
SCSI Chip ID register 5-11
SBCL register 5-16
SCSI clock rates 5-10
SBDL register 5-48
SCSI Control Enable bit 5-45
SBR register 5-33
SCSI Control One register 5-7
SBSY/ status bit 5-16
SCSI Control Three register 5-9
SC_D/ status bit 5-16
SCSI Control Two register 5-9
SCE bit 5-45
SCSI Control Zero register 5-5
SCF2-0 bits 5-9
SCSI core 2-1
SCID register 5-11
SCSI Data High Impedance bit 5-26
SCLK bit 5-45
SCSI Destination ID register 5-13
SCNTL0 register 5-5
SCSI Device Management System (SDMS) 2-2
SCNTL1 register 5-7
SCSI Disconnect Unexpected bit 5-9
SCNTL2 register 5-9
SCSI FIFO Test Read bit 5-46
SCNTL3 register 5-9
SCSI FIFO Test Write bit 5-47
SCPTS bit 5-41
SCSI First Byte Received register 5-14
Scratch Byte register 5-33
SCSI Gross Error bit 5-36, 5-39
SCRATCHA register 5-31
SCSI High-Impedance Mode bit 5-45
SCRATCHB register 5-49
SCSI I_O/ bit 5-19
SCRIPTS
I-10
SYM53C810A Data Manual
Index
SCSI Input Data Latch register 5-47
SCSI Test Three register 5-46
SCSI instructions
block move 6-4
I/O 6-8
load/store 6-24
memory move 6-21
read/write 6-14
SCSI Test Two register 5-45
SCSI Interrupt Enable One register 5-37
SCSI true end of process bit 5-24
SCSI Interrupt Enable Zero register 5-36
SCSI Valid Bit 5-15
SCSI interrupt pending bit 5-22
SDID register 5-13
SCSI Interrupt Status One register 5-40
SDP/ bit 5-18
SCSI Interrupt Status Zero register 5-38
SDPL bit 5-18
SCSI Isolation bit 5-45, A-7
SDU bit 5-9
SCSI Longitudinal Parity register 5-40
SEL bit 5-15, 5-16, 5-36, 5-39
SCSI Loopback Mode bit 5-45
SEL bits 5-42
SCSI Low level Mode 5-46
Select with SATN/ on a start sequence bit 5-6
SCSI MSG/ bit 5-19
Selected bit 5-36, 5-39
SCSI Output Control Latch register 5-15
SCSI Output Data Latch register 5-48
SCSI Parity Error bit 5-37
SCSI Phase Mismatch - Initiator Mode bit 5-36
SCSI Reset Condition bit 5-37
SCSI Test Zero register 5-44
SCSI Timer One register 5-43
SCSI Timer Zero register 5-42
SCSI timings 7-23–7-28
SCSI Transfer register 5-11
selection
during reselection 2-9
during selection 2-9
response to 2-9
SCSI RST/ Received bit 5-39
Selection or Reselection Time-out bit 5-37
STO bit 5-40
SCSI RST/ signal bit 5-18
Selection response logic test bit 5-44
SCSI SCRIPTS operation 6-1
Selection Time-Out bits 5-42
SCSI SDP0/ parity signal bit 5-18
SEM bit 5-21
SCSI Selected As ID bits 5-44, A-7
Semaphore bit 5-21
SCSI Selector ID register 5-15
SFBR register 5-14
SCSI signals 7-2
SGE bit 5-36, 5-39
SCSI Status One register 5-18
Shadow Register Test Mode bit 5-26
SCSI Status Two register 5-19
SI_O bit 5-16
SCSI Status Zero register 5-17
SI_O/ status bit 5-16
SCSI Synchronous Offset Maximum bit 5-44
SIDL bit 5-17
SCSI Synchronous Offset Zero bit 5-44
SIDL least significant byte full bit 5-17
SCSI Synchronous Transfer Period bits 5-11
SIDL register 5-47
SCSI Test One register 5-45
SIEN0 register 5-36
SYM53C810A Data Manual
I-11
Index
SIEN1 register 5-37
SSTAT2 register 5-19
Signal process bit 5-21, 5-23
stacked interrupts 2-15
SIGP bit 5-21, 5-23
START bit 5-5
Single step interrupt bit 5-17, 5-33
Start DMA operation bit 5-34
single-ended operation 2-9
Start SCSI Transfer bit 5-8
Single-step mode bit 5-34
Start sequence bit 5-5
SIOM bit 5-31
STD bit 5-34
SIP bit 5-22
STEST0 register 5-44
SIR bit 5-17, 5-33
STEST1 register 5-45
SISO bit 5-45, A-7
STEST2 register 5-45
SIST0 register 5-38
STEST3 register 5-46
SIST1 register 5-40
STIME0 register 5-42
SLB bit 5-45
STIME1 register 5-43
SLPAR register 5-40
STO bit 5-37
SLT bit 5-44
STR bit 5-46
SMSG/ status bit 5-16
STW bit 5-47
SOCL register 5-15
SXFER register 5-11
SODL least significant byte full bit 5-17
SYM53C810A
ease of use 1-3
flexibility 1-4
integration 1-3
performance 1-3
reliability 1-4
testability 1-4
SODL register 5-48
SODR least significant byte full bit 5-17
Software reset bit 5-20
SOM bit 5-44
Source I/O-Memory Enable bit 5-31
SOZ bit 5-44
SRE bit 5-11
SREQ/ status bit 5-16
SRST bit 5-20
SRTM bit 5-26
SSAID bits 5-44, A-7
SSEL/ status bit 5-16
SSI bit 5-17, 5-33
SSID register 5-15
SYMTolerANT Technology
electrical characteristics 7-6
Synchronous Clock Conversion Factor bits 5-9
synchronous data transfer rate 2-11
synchronous operation 2-11
system diagram 1-5
System Pins 4-4
SZM bit 5-45
SSM bit 5-34
T
SST bit 5-8
SSTAT0 register 5-17
Target Mode
SATN/ Active 5-38
SSTAT1 register 5-18
Target mode bit 5-6
I-12
SYM53C810A Data Manual
Index
TE bit 5-46
W
TEMP register 5-25
WATN bit 5-6
Temporary register 5-25
what is covered in this manual 1-1
TEOP bit 5-24
WOA bit 5-18
termination 2-9
Won arbitration bit 5-18
testability 1-4
Write and Invalidate command
Write and Invalidate Enable bit 5-25, A-4
Timer Test Mode bit 5-47
timing diagrams 7-11–7-27
interrupt output 7-10
PCI interface 7-22
SCSI 7-28
SCSI timings 7-23
Z
ZMOD bit 5-26
ZSD bit 5-26
timings
clock 7-9
PCI 7-22
reset input 7-10
SCSI 7-23
TolerANT 1-2
Extend SREQ/SACK filtering bit 5-46
TolerANT Enable bit 5-46
TolerANT Enable bit 5-46
TP2-0 bits 5-11
transfer control instructions 6-17
prefetch unit flushing 2-2
transfer rate 1-3
Clock conversion factor bits 5-10
synchronous 2-11
Synchronous clock conversion factor bits 5-9
TRG bit 5-6
TTM bit 5-47
TYP3-0 bits 5-41
U
UDC bit 5-36, 5-39
Unexpected Disconnect bit 5-36, 5-39
V
VAL bit 5-15
SYM53C810A Data Manual
I-13
Index
I-14
SYM53C810A Data Manual
Symbios Logic
Sales Locations
For literature on any Symbios Logic product or
service, call our hotline toll-free 1-800-856-3093
North American Sales Locations
International Sales Locations
Western Sales Area
1731 Technology Drive, Suite 610
San Jose, CA 95110
(408) 441-1080
European Sales Headquarters
Westendstrasse 193\III
80686 Muenchen
Germany
011-49-89-547470-0
3300 Irvine Avenue, Suite 255
Newport Beach, CA 92660
(714) 474-7095
Eastern Sales Area
8000 Townline Avenue, Suite 209
Bloomington, MN 55438-1000
(612) 941-7075
12377 Merit Dr.
Dallas, TX 75251
(972) 503-3205
92 Montvale Avenue, Suite 3500
Stoneham, MA 02180-3623
(617) 438-0043
30 Mansell Court, Suite 220
Roswell, GA 30076
(404) 641-8001
Asia/Pacific Sales Headquarters
37th Floor, Room 3702, Lippo Tower
Lippo Centre, 89 Queensway
Hong Kong
011-852-253-00727
© Symbios Logic Inc.
Printed in the U.S.A.
T07962I
0696-2MH
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