HDMI Transmitter/Receiver Support on

HDMI Transmitter/Receiver Support on
Application Report
SPRAAV4 – May 2008
HDMI Transmitter/Receiver Support on TMS320DM6467
Paul Yin..........................................................................................................................................
ABSTRACT
This application report describes how to equip the DM6467 device with transmit/receive
capabilities via high-definition multimedia interface (HDMI). A general description is
provided for all the DM6467 internal peripherals which are required in HDMI
transmitting/receiving, as well as the SiI9134 HDMI transmitter and the SiI9135 HDMI
receiver. The block diagrams for both the transmit side logic and the receive logic are
provided to illustrate how to connect the DM6467 device to the SiI9134 and the SiI9135
devices.
This document does not explain the actual schematics for the block diagram.
This document does not explain the software programming involved to configure
DM6467, SiI9134, or SiI9135.
1
2
3
4
Contents
Introduction ..........................................................................................
HDMI Transmitter Logic ...........................................................................
HDMI Receiver Logic ..............................................................................
References ..........................................................................................
1
3
5
6
List of Figures
1
2
Transmit Logic Block Diagram .................................................................... 3
Receive Logic Block Diagram ..................................................................... 5
1
Introduction
1.1
Introduction to DM6467 DMSoC (VPIF, McASP, GPIO, I2C)
There are four DM6467 internal peripherals involved in implementing the HDMI applications discussed in
this applicaton note. These peripherals are: video port interface (VPIF), multichannel audio serial port
(McASP), general-purpose input/output (GPIO), and inter-integrated circuit (I2C). The main features of
each peripheral are discussed below.
The DM6467 VPIF is a receiver and transmitter of video data. It has both receiver and transmitter logic.
The receiver is capable of receiving dual-channel 8-bit BT.656 and single-channel 16-bit BT.1120 (720p,
1080i, and 1080-30p), as well as 8/10/12-bit raw data. The transmitter is capable of transmitting
dual-channel 8-bit BT.656 and single-channel 16-bit BT.1120 (720p, 1080i, and 1080-30p). For more
details on the functionality of VPIF, see the TMS320DM646x DMSoC Video Port Interface (VPIF) User’s
Guide (SPRUER9).
C64x is a trademark of Texas Instruments.
All other trademarks are the property of their respective owners.
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1
Introduction
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The DM6467 McASP is a receiver and transmitter of audio data. This peripheral supports:
transmitting/receiving in time-division multiplexed (TDM), inter-integrated sound (I2S) mode, and
transmitting in digital audio interface transmit (DIT) mode. The McASP consists of transmit and receive
interfaces that may operate synchronized, or completely independently with separate master clocks, bit
clocks, frame syncs, and different transmit modes with different bit-stream formats. There are two
instances of the McASP on this device. The McASP1 module is not used in the HDMI applications due to
its integration limitations. The McASP0 module includes four serializers that can be individually enabled to
either transmit or receive in all different modes (except receiving in DIT mode). For more details on the
functionality of McASP, see the TMS320DM646x DMSoC Multichannel Audio Serial Port (McASP) User’s
Guide (SPRUER1).
The DM6467 GPIO is a group of dedicated general-purpose pins that may be configured as either inputs
or outputs. When configured as an output, you can write to an internal register to control the state driven
on the output pin. When configured as an input, you can detect the state of the input by reading the state
of an internal register. The GPIO peripheral is accessible via the ARM926 CPU as well as the C64x™
CPU. All GPIO signals can be used as interrupt sources with configurable edge detection when configured
as an input, and in case external onboard components need immediate CPU attention. For more details
on the functionality of GPIO, see the TMS320DM646x DMSoC General-Purpose Input/Output (GPIO)
User’s Guide (SPRUEQ8).
The DM6467 I2C is a dedicated peripheral providing an interface between the TMS320DM6467 DMSoC
and other devices that are compliant with the I2C-bus specification and connected by way of an I2C-bus.
External components that are attached to this 2-wire serial bus can transmit and receive data that is 2-bits
to 8-bits wide to and from the DMSoC through I2C. It can be configured to function in either slave-mode or
master-mode. In the master-mode, it can be used to control external onboard components. For more
details on the functionality of I2C, see the TMS320DM646x DMSoC Inter-Integrated Circuit (I2C) Module
User’s Guide (SPRUER0).
1.2
Introduction to SiI9134 HDMI Transmitter
The SiI9134 HDMI deep color transmitter is HDMI1.3, high-bandwidth digital content protection (HDCP)
1.2, and digital video interface (DVI) 1.0 compliant. Some of the main features of SiI9134 are introduced
below. For more details on the functionality, visit http://www.siliconimage.com.
• Integrated transition minimized differential signaling (TMD) core operating between 25 – 225 MHz and
resolution up to 1080P
• Flexible video interface support
– 24/30/36-bit RGB/YCbCr 4:4:4
– 16/20/24-bit YCbCr 4:2:2
– 8/10/12-bit YCbCr 4:2:2 (BT.656)
– 12/15/18-bit dual-edge clocking input
– BTA-T1004 video input
• Flexible video format conversion
• Flexible digital audio interface support
– High bit rate compressed DTS HD and Dolby True HD audio
– Dedicated 4-port (8-channel) I2S input
– Dedicated 4-port (8-channel) DSD input for super audio CD (SACD)
– Dedicated 1-port Sony/Philips digital interconnect format (SPDIF) input
– IEC60958 or IEC61937 compatible
• Master I2C interface for DDC connection and Slave I2C interface for control from external processor
• Integrated HDCP encryption engine for transmitting protected audio and video content
• Monitor detection supported through hot plug and receiver detection
• Programmable data enable generator and sync extraction
2
HDMI Transmitter/Receiver Support on TMS320DM6467
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HDMI Transmitter Logic
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1.3
Introduction to SiI9135 HDMI Receiver
The SiI9135 HDMI receiver with enhanced audio and deep color outputs is HDMI1.3, HDCP 1.1, and DVI
1.0 compliant. Some of the main features of SiI9135 are introduced below. For more details on the
functionality, visit http://www.siliconimage.com.
• Integrated TMDs core operating between 25 – 225 MHz and resolution up to 1080P
• Flexible video interface support
– 36-bit RGB/YCbCr 4:4:4
– 16/20/24-bit YCbCr 4:2:2
– 8/10/12-bit YCbCr 4:2:2 (BT.656)
– 12/15/18-bit dual-edge clocking output
• Flexible video format conversion
• Flexible digital audio interface support
– High bit rate compressed DTS HD and Dolby True HD audio
– Shared 4-port (8-channel) I2S input
– Shared 3-port (6-channel) DSD input for SACD
– Shared 1-port SPDIF input
– IEC60958 or IEC61937 compatible
• Slave I2C interface for DDC connection and Slave I2C interface for control from external processor
• Integrated HDCP encryption engine for receiving protected audio and video content
2
HDMI Transmitter Logic
Reset
INT Via GPIO
INT
I2C
SDA
CSDA
SCL
CSCL
DE
D[35:0]
HSYNC
VSYNC
IDCK
VP_DOUT[15:0]
VPIF
VP_CLKO2
AHCLKX0
ACLKX0
AFSX0
AXR0[3:0]
McASP0
AXR0[0]
DSDA
DSCL
HPD
TXC+
TXC–
TX0+
TX0–
TX1+
TX1–
TX2+
TX2–
ESD
Protection
and Choke
Logic
16
15
19
10
12
7
9
4
6
1
3
13
HDMI Connector
Sil9134
On-Board CTL
DM6467
DM6467 EVM
The transmitter side logic block diagram is detailed in Figure 1. There are three main blocks in this
diagram: the DM6467 evaluation module (EVM) (DM6467 DMSoC), the SiI9134 deep color transmitter,
and a generic HDMI connector.
DCLK
MCLK
SCK
WS
SD[3:0]
DL[3:0]
DR[3:0]
SPDIF
Figure 1. Transmit Logic Block Diagram
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HDMI Transmitter Logic
•
•
•
www.ti.com
Signal connection between DM6467 EVM (DM6467 DMSoC) and SiI9134
– Audio
• 4-port I2S: AHCLKX0 → MCLK, ACLKX0 → SCK, AFSX0 → WS, and AXR0[3:0] → SD[3:0]
• 1-port SPDIF: AHCLKX0 → MCLK and AXR0[0] → SPDIF
• 4-port DSD (not supported by DM6467): DCLK, DL[3:0], and DR[3:0] need to be properly
terminated
– Video
• CLK: VP_CLKO2 → IDCK
• Data
• Y/C 4:2:2: (Y) VP_DOUT[7:0] → D[23:16], (C) VP_DOUT[15:8] → D[35:28]
• Y/C 4:2:2 muxed: (Y/C) VP_DOUT[15:8] → D[23:16], D[35:28] not connected
• VSYNC, HSYNC, DE (not supported by DM6467): VSYNC, HSYNC, and DE need to be
properly terminated
– I2C Control (DM6467 Master, SiI9134 Slave)
• CLK: SCL → CSCL
• Data: SDA ↔ CSDA
– INT (interrupt signal from SiI9134 to DM6467 via GPIO)
Signal connection between SiI9134 and generic HDMI connector
– Three transition minimized differential signaling (TMDS) pair data channel
• TX0+ → Pin 7, TX0- → Pin 9, TX1+ → Pin 4, TX1- → Pin 6, TX2+ → Pin 1, TX2- → Pin 3
– One TMDS pair clock channel
• TXC+ → Pin 10, TXC- → Pin 12
– I2C control connection (SiI9134 Master)
• DSDA ↔ Pin 16, DSCL ↔ Pin 15
– Hot Plug Detect (HPD)
• HPD ← Pin 19
– Consumer Electronics Control (CEC) currently unsupported
• Pin 13 needs to be properly terminated
Additional connection considerations
– Optional electrostatic discharge (ESD) protection and choke logic support
– On-board logic or DM6467 GPIO controlled SiI9134 RESET signal
– SiI9134 signals that need to be properly terminated: CI2CA, EXT_SWING, power, and ground
signals
To summarize, the following HDMI audio and video output modes are supported in this application note:
• Audio output modes
– Up to 7.1 (4-port I2S)
– 1-port SPDIF
• Video output modes
– BT.656
– BT.1120 (720p, 1080i, and 1080-30p)
4
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HDMI Receiver Logic
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3
HDMI Receiver Logic
INT Via GPIO
I2C
SDA
SCL
DM6467
VPIF
VP_DIN[15:0]
ESD
Protection
and Choke
Logic
16
15
10
12
7
9
4
6
1
3
13
Q[35:0]
HSYNC
VSYNC
ODCK
VP_CLKIN0
AHCLKR0
ACLKR0
AFSR0
AXR0[3:0]
McASP0
ESD
Protection
and Choke
Logic
16
15
10
12
7
9
4
6
1
3
13
Reset
OSC
DSDA1
DSCL1
R1XC+
MUTEOUT R1XC–
R1X0+
MCLK
R1X0–
SCK
R1X1+
WS
R1X1–
SD[3:0]
R1X2+
XTALIN
XTALOUT R1X2–
SPDIF
19
HDMI Connector 0
Sil9135
DSDA0
DSCL0
R0XC+
R0XC–
INT
R0X0+
SCDT
R0X0–
R0X1+
CSDA
R0X1–
CSCL
R0X2+
EVNODD
R0X2–
DE
On-Board CTL
19
HDMI Connector 1
DM6467 EVM
The receiver side logic block diagram is detailed in Figure 2. There are three main blocks in this diagram:
the DM6467 EVM (DM6467 DMSoC), the SiI9135 receiver, and two generic HDMI connectors.
Figure 2. Receive Logic Block Diagram
•
Signal connection between DM6467 EVM (DM6467 DMSoC) and SiI9135
– Audio
• 4-port I2S: AHCLKR0 ← MCLK, ACLKR0 ← SCK, AFSR0 ← WS, and AXR0[3:0] ← SD[3:0]
• MUTEOUT (not supported by DM6467): MUTEOUT needs to be properly terminated
– Video
• CLK: VP_CLKIN0 ← ODCK
• Data
• Y/C 4:2:2: (Y) VP_DIN[7:0] ← D[23:16], (C) VP_DIN[15:8] ← D[35:28]
• Y/C 4:2:2 muxed: (Y/C) VP_DIN[15:8] ← D[23:16], D[35:28] not connected
• VSYNC, HSYNC, DE, EVNODD (not supported by DM6467): VSYNC, HSYNC, DE, and
EVNODD need to be properly terminated
– I2C Control (DM6467 Master, SiI9135 Slave)
• CLK: SCL → CSCL
• Data: SDA ↔ CSDA
– INT (interrupt signal from SiI9135 to DM6467 via GPIO)
– SCDT (active HDMI video indicator from SiI9135 to DM6467 via GPIO)
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References
•
•
www.ti.com
Signal connection between SiI9135 and generic HDMI connectors
– Three transition minimized differential signaling (TMDS) pair data channel
• To connector 0: R0X0+ ← Pin 7, R0X0- ← Pin 9, R0X1+ ← Pin 4, R0X1- ← Pin 6, R0X2+ ←
Pin 1, R0X2- ← Pin 3
• To connector 1: R1X0+ ← Pin 7, R1X0- ← Pin 9, R1X1+ ← Pin 4, R1X1- ← Pin 6, R1X2+ ←
Pin 1, R1X2- ← Pin 3
– One TMDS pair clock channel
• To connector 0: R0C+ ← Pin 10, R0C- ← Pin 12
• To connector 1: R1C+ ← Pin 10, R1C- ← Pin 12
– I2C control connection (SiI9135 Slave)
• To connector 0: DSDA0 ↔ Pin 16, DSCL0 ← Pin 15
• To connector 1: DSDA1 ↔ Pin 16, DSCL1 ← Pin 15
– Consumer electronics control (CEC) currently unsupported
• Pin 13 on both connectors need to be properly terminated
Additional connection considerations
– Optional ESD protection and choke logic support
– External oscillator connected between XTALIN and XTALOUT for SiI9135
– On-board logic or DM6467 GPIO controlled SiI9135 RESET signal
– SiI9135 signals that need to be properly terminated: CI2CA, R0PWR5V, R1PWR5V, power, and
ground signals
– Hot Plug Detect (HPD) signal from both HDMI connectors
• Pin 19 on both connectors are fed directly from to DM6467 via GPIO
To summarize, the following HDMI audio and video input modes are supported in this application note:
• Audio input modes
– Up to 7.1 (4-port I2S)
• Video input modes
– BT.656
– BT.1120 (720p, 1080i, and 1080-30p)
4
References
•
•
•
•
•
•
6
TMS320DM646x DMSoC Multichannel Audio Serial Port (McASP) User’s Guide (SPRUER1)
TMS320DM646x DMSoC Video Port Interface (VPIF) User’s Guide (SPRUER9)
TMS320DM646x DMSoC General-Purpose Input/Output (GPIO) User’s Guide (SPRUEQ8)
TMS320DM646x DMSoC Inter-Integrated Circuit (I2C) Module User’s Guide (SPRUER0)
SiI9134 HDMI Deep Color Transmitter Data Sheet
(http://www.siliconimage.com/products/product.aspx?id=102)
SiI9135 HDMI Receiver with Enhanced Audio and Deep Color Outputs Data Sheet
(http://www.siliconimage.com/products/product.aspx?id=109)
HDMI Transmitter/Receiver Support on TMS320DM6467
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