# Document

```CHAPTER 16 MEMORY CIRCUITS
Chapter Outline
16.1 Latches and Flip-Flops
16.2 Semiconductor Memories: Types and Architectures
16.3 Random-Access Memory (RAM) Cells
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16.1 LATCHES AND FLIP-FLOPS
Logic Classifications
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Combinational circuits: the output depends only on the present value of the input
Sequential circuits: the output depends not only on the present input values but also on the previous values
Static sequential circuits: use positive feedback to provide two stable states (bistable)
Dynamic sequential circuits: use the storage of charge on a capacitor
Latch
 Exhibits two stable operating points and one unstable operating point
 The latch needs to be triggered to change stage
 The latch together with the triggering circuitry forms a flip-flop
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The SR Flip-Flop
 The latch is triggered by input S and R
 S =1 and R = 0  Q = 1
 S =0 and R = 1  Q = 0
 S =0 and R = 0  Q unchanged
 S =0 and R = 0  Q undefined (not allowed).
CMOS Implementation of SR Flip-Flop
 The flip-flop is set by S and R when the clock  is high
 Q5 and Q6 should be able to pull the output node at least below the threshold of inverter (Q3, Q4)
 The period of the set signal should be long enough to cause regeneration to take over
 The state is latched when the clock  is low
 No static power dissipation (no conducting path between VDD and ground except during switching)
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D Flip-Flop Circuits
 Simple implementation of the D flip-flop:
   1 and   0 : the loop is open and Q is determined by D
   0 and   1 : the loop is closed and the flip-flop is in latch mode
 Two-phase non-overlapping clock is required for D flip-flop operation
 Major drawback: the output simply follows the signal on the D input line during 
 Master-slave D flip-flop:
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16.2 SEMICONDUCTOR MEMORIES
Memory Types
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Random-access memory (RAM): access time is independent of the physical location of the stored info
Sequential memories: data are available only in the same sequence in which the data were stored
Read/write memory: permits data to be stored and retrieved at comparable speeds
Memory-Chip Organization
 The bits on a memory chip are either individually
 The increase in word line and bit line lengths slows down
their transient response due to larger R and C
 Memory chip is partitioned into a number of blocks to
improve the transient response
Memory-Chip Timing
 Memory access time: the time between the initiation
of a read operation and the data at the output
 Memory cycle time: the minimum time allowed
between two consecutive memory operations.
 Access time and cycle time are in the range of a few
to few hundred nanoseconds
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16.3 RANDOM-ACCESS MEMORY (RAM) CELLS
RAM Cells
 It is imperative to reduce the cell size for a large number of bits on a chip
 The power dissipation should be minimized for RAM cells
 There are two basic types of MOS RAMs:
 Static (SRAM): utilize static latches as the storage cells. ( ~ 6 transistors/cell)
 Dynamic (DRAM): store binary data on capacitors and require periodic refreshing. (~ 1T+1C/cell)
 Both static and dynamic RAMs are volatile
Static Memory Cell
 A typical static memory cell comprises a latch (two cross-coupled inverters) and two access transistors
 The access transistors are turned on when the word line is selected
 The complementary bit lines are connected to the latch when the cell is selected
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
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The complementary bit lines are precharged to an intermediate voltage between VDD and ground
The bit lines are connected to the latches through access transistors when the cell is selected
A differential voltage develops between complementary bit lines
The voltage change vQ and vQ should be sufficiently small not to change the latch state during readout
The read operation in an SRAM is nondestructive
Readout delay is determined by the rise time of word line and time needed to develop the required voltage
The dynamic operation can be approximated by treating Q1 and Q5 as rON1 and rON5
The larger (W/L)5, the faster the vB B develops
The smaller (W/L)5, the smaller voltage change for vB B
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 The worst case scenario is to choose a precharge value of VDD
 Q5 operates in saturation region and Q1 operates in triode region:
I5 
1
1 
W  
W 
 nCox   (VDD  Vtn  VQ ) 2  I1   nCox   (VDD  Vtn )VQ  VQ2 
2
2 
 L 1 
 L 5
 The design constraint is specified by



1
VQ  (VDD  Vtn )1 
(W / L)5

1

(W / L)1




(W / L)5
1

1
  Vtn 
2
W
L
(
/
)


1
Vtn


1 


 VDD  Vtn 
 The voltage change in vQ will be very small
 The B line is discharged by I5 at the beginning:
V  I 5 t / CB
 The time needed to develop a voltage difference V is
t  CB V / I 5
 The B line will be finally discharged to 0 in steady state
 Sense amplifiers are usually used to speed up the read operation
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Write Operation of SRAM
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The complementary bit-lines are respectively set to VDD and ground before the operation
The cell is selected by the word line and the cell is connected to the bit lines thru access transistors
Q5 is in saturation and the current for charging capacitor equals to I5  I1
I5 decreases (due to reduced vGS5 and body effect) and I1 increases (due to reduced vGS1) as vQ increases
When vQ and vQ reach VDD/2, the regenerative feedback initiates and cause the flip-flop to change state
Write delay is determined by the time for vQ and vQ to reach VDD/2 and the delay time of the flip-flop
The charging (discharging) component of write delay is much smaller than the corresponding component
in the read operation because only small capacitance CQ needs to be charged (discharged)
p
is dominated by
y the word-line delayy
 The delayy time in write operation
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Design Constraint for Write Operation
 Q4 operates in saturation region and Q6 operates in triode region:
I5 
1
1 
W  
W 
 nCox   (VDD  | Vtn |) 2  I 6   nCox   (VDD  Vtn )VQ  VQ2 
2
2 
 L 1 
 L 4
 The design constraint is specified by

 p (W / L) 4
VQ  (VDD  Vtn )1 

 n (W / L) 6

2

Vtn  
(W / L) 4  p  
 V 
 
1  1 

 tn
(W / L) 6  n   VDD  Vtn  



D i P
Design
Procedure
d
off th
the SRAM C
Cell
ll
 The aspect ratios of the PMOS and NMOS devices in the latch are determined
 Choose the aspect ratio of the access transistors carefully
 Read operation specifies the upper limit of the device size
 Write operation specifies the lower limit of the device size
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Dynamic RAM Cell
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One-transistor cell: one transistor and one capacitor per cell
Only one bit line is use in DRAMs
When the cell is storing a 1, the capacitor is charged to VDDVt
When the cell is storing a 0, the capacitor is discharged to 0V
Refresh operation must be performed every 5 to 10 ms
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The bit lines are precharged to VDD/2
The word line is raised to VDD and all the access transistors in the selected row are conductive
A small voltage difference will be detected in the bit lines
VDD

V
 (CB  CS ) DD  V 
2

 2
V 
V  C 
CS 
V 
VCS  DD   S VCS  DD  for C B  CS
C B  CS 
2  CB 
2 
CSVCS  CB
Write Operation
 The data bit to be written is set to VDD or ground and CS will be charged or discharged to VDDVt or 0V
 All other cells in the selected row perform write operation at the same time
 Refresh operation: a read operation followed by a write operation for stored data
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16.4 SENSE AMPLIFIERS AND ADDRESS DECODERS
Operation of Sense Amplifier
 A sense amplifier is formed by a latch with two crosscoupled CMOS inverters
 Q5 and Q6 connect the sense amplifier to VDD and ground
when data-sensing action is required
 Precharge and equalization circuit is controlled by p
prior to a read operation (Q8 and Q9 precharge the bit
lines to VDD/2; transistor Q7 helps speed up this process
by equalizing the voltages on the two lines)
 The precharge and equalization circuit is activated by
p and complementary bit lines are set to VDD/2
 Word line goes up and the cell is connected to bit lines
 The sense amplifier turned on by s as an adequate
difference voltage signal is developed between the bit
lines by the storage cell
 The data stored in the cell is refreshed as the sense
amplifier pulls the bit lines to VDD and ground
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Dynamic Operation of Sense Amplifier
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When the sense amplifier is activated, both inverters are biased in transition region (VIN = VDD/2)
With input signal vi, the resulting output signal (gmp + gmn)vi is fed back to the input (positive feedback)
The bit line voltage rises/decays exponentially with a time constant of CB/Gm under small-signal operation
As the voltage deviates from VDD/2, the it tends to saturate at VDD or ground (large-signal operation)
VDD
 V (1)e ( Gm / CB ) t
2
V
(G / C )t
Read-0 operation: vB  DD  V (0)e m B
2
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An Alternative Sense Amplifier
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A differential amplifier with a current mirror as the active load
The charging/discharging current is defined by the bias current I
The voltage difference developed by the sense amplifier: V = I t/C
The voltage required for complete current switching: V = 2 VOV
Alternative Precharging Arrangement
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Differential Operation in Dynamic RAMs
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Each bit line is split into two identical halves
Each half-line is connected to half the cells in the column and an additional dummy cell
The dummy cell serves as the other half of a differential DRAM cell
During precharge phase, two dummy cells are precharged to VDD/2
Differential signal V(1) or V(0) is detected by the sense amplifier when it is enabled
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The decoder can be realized by NOR functions provided by the matrix structure  NOR decoder
The word lines are precharged to VDD during precharge
All the unselected word lines will be discharged
No static power dissipation due to dynamic operation
W0  A0 A1 A2  A0  A1  A2
W1  A0 A1 A2  A0  A1  A2
W2  A0 A1 A2  A0  A1  A2
W3  A0 A1 A2  A0  A1  A2
W4  A0 A1 A2  A0  A1  A2
W5  A0 A1 A2  A0  A1  A2
W6  A0 A1 A2  A0  A1  A2
W7  A0 A1 A2  A0  A1  A2
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 Column-address decoder is to connect one of the 2N bit lines to the data I/O line of the chip
 It exhibits the same function as a multiplexer
 Pass-transistor logic decoder:
 A NOR decoder + pass-transistor multiplexer
 Tree decoder:
 Utilize smaller number of transistors
 Speed decreases due to a relatively large number of series transistors in the signal path
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Pulse-Generation Circuits
 The ring oscillator:
 Generates periodic output waveforms
 Odd number of stages in the loop
 The oscillation frequency is 1/2NtP
 A one-shot or monostable multivibrator circuit
 A single output pulse with a predetermined
width is provided when triggered
 The width is determined by NtP
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MOS ROM
 The circuit can be in a static or a dynamic form
 The data stored in the ROMs is determined at the time of fabrication
 Mask programmable ROMs can avoid having custom design each ROM from scratch
 MOSFETs are included at all bit locations but only the gates of those transistors where 0’s are to be stored
are connected to the word lines
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Programmable ROM (PROM)
 The data can be programmed by the user, but only once
 A typical PROM uses polysilicon fuses to connect the emitter of each BJT to the digital line
Erasable Programmable ROM (EPROM)
 The data can be erased and reprogrammed as many times by the uses
 A floating-gate transistor can be used for EPROM at all bit locations as memory cells (stacked-gate cells)
 Programming process:
 Apply high voltage to the select gate and between the source and the drain
 Hot electrons are injected into the floating gate and become trapped
 After the programming process,
process the programmed transistors exhibit high threshold voltage
 The process of charging is self-limiting as the charge accumulation increases
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 Erasure process:
 Illuminate the cell with UV light for a specified duration
 The UV light provides the trapped electrons sufficient energy to transported back to the substrate
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