Lite End Multiport Repeater Interface Controller

Lite End Multiport Repeater Interface Controller
TC3097-8
Preliminary Data Sheet
Lite End Multiport Repeater Interface Controller
Features
Functionally conforms to Section 9 in the IEEE
802.3 specification.
9 network connection (ports) per chip including:
– 1 AUI PORT with fully compatible and drive
capability (50m AUI cable).
– 8 TP PORT with fully compatible and drive
capability (100m TP cable).
Cascadable for large multiple LEMRIC hub
applications.
On-chip Elasticity buffer, Manchester encoder
and decoder.
Separate partition state machine for each port.
Embeded LED output driver for each port
partition status, each port link/receive status
(TP port), global jam status, and global jabber
status. No external glue logic is required.
Embedded predistortion resistors for every TP
port.
Build in power reset circuit, no extra glue logic
required.
Crystal/Oscillater optional applicable.
Manchester code violation detection and reporting.
Support MAU Jabber Lockup Protection function.
Support Auto Partition/Reconnection function
to isolate a faulty segment's collision activity.
Fully integrated Link Test logic with
enable/disable option, conforming to the
10BASE-T standard.
Fully integrated polarity detect/correct logic
with enable/disable option for per TP port.
Low power consumption; fully load < 900 mW.
CMOS device feature high integration with a
single + 5V supply.
100-pin QFP package.
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Copyright © 2003, IC Plus Corp.
General Description
The TC3097 Lite End Multiport Repeater Interface
Controller (LEMRIC) may be used to implement
an IEEE 802.3 multiport repeater unit. It fully
satisfies the IEEE 802.3 repeater specification
including the functions defined by the repeater,
segment partition and jabber lockup protection
state machines.
The LEMRIC has an on-chip phase-locked-loop
(PLL) for Manchester data decoding, a
Manchester encoder, and an Elasticity Buffer for
preamble regeneration. In addition, it provides
direct LED display driver pins for per port
LINK/RCV status, per port partition jabber status,
global jam and jabber lockup status indications.
Each LEMRIC can connect up to 9 cable
segments via its network interface ports. One port
is fully Attachment Unit Interface (AUI) compatible
and is able to connect to an external Medium
Attachment Unit (MAU) using the maximum length
of AUI cable. The other 8 ports have integrated
10BASE-T transceivers. In addition, large repeater
units may be constructed by cascading LEMRICs
together over the Inter-LEMRIC bus.
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TC3097-8-DS-R24
TC3097-8
Preliminary Data Sheet
Table Of Contents
Features ..............................................................................................................................................................1
General Description ............................................................................................................................................1
Table Of Contents ...............................................................................................................................................2
1 Pin Description..........................................................................................................................................4
1.1
Config (pin 2 is connected to GND) ..................................................................................... 4
2 Principles Of Operation ............................................................................................................................7
2.1
Reset.................................................................................................................................... 7
2.2
Clock and data Recovery..................................................................................................... 7
2.3
Functional State diagrams ................................................................................................... 8
2.3.1
TP Port Auto-Partition State Diagram ..................................................................... 8
2.3.2
AUI Port Auto-Partition State Diagram.................................................................. 10
2.3.3
Global State Diagram............................................................................................ 12
2.3.4
Counters and Timers............................................................................................. 15
Automatic Preamble Regeneration....................................................................... 17
2.3.5
2.3.6
Inter-LEMRIC Bus Operation ................................................................................ 19
2.3.7
Port Block functions .............................................................................................. 26
3 Absolute Maximum Ratings.................................................................................................................29
4 D.C. Characteristics................................................................................................................................29
5 Switching Characteristics .......................................................................................................................30
6 Package Detail ..........................................................................................................................................35
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Preliminary Data Sheet
TC3097-8 Connection Diagram Config (pin 2 is connected to GND)
R
X
V G
V I
D N N N D 7
D D C C D B
R
X
I
7
A
T
X
O
7
R
B
T
R
X
X
O
7 G V I
R N D 6
A D D B
R
X
I
6
A
T
R
O
6
R
B
T
R
O
6
R
A
R
X
I
5
B
R
X
I
5
A
T
X
O
5
R
B
T
X
R
O
X
5 G V I
R N D 4
A D D B
R
X
I
4
A
T
X
O
4
R
B
T
X
O
4 V
G
R D N N N N
A D C C C D
80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51
TXO8RA
TXO8RB
RXI8A
RXI8B
VDD
TXO9RA
81
50
82
49
83
84
48
47
85
46
86
45
TXO9RB
RXI9A
RXI9B
87
GND
PALED1
PALED2
PALED3
PALED4
PALED5
PALED6
PALED7
PALED8
PALED9
GND
90
TC3097-8
100pin QFP
88
89
91
92
93
94
44
43
42
41
40
39
38
95
37
36
96
35
97
34
98
99
33
32
100
31
1
2
3
4 5
V G C J
D N O A
D D L B
E L
D E
D
L
R
L
E
D
1
Confidential.
Copyright © 2003, IC Plus Corp.
6
7
8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30
L
R
L
E
D
2
L
R
L
E
D
3
L
R
L
E
D
4
L
R
L
E
D
5
L
R
L
E
D
6
L
R
L
E
D
7
L
R
L
E
D
8
L G I I I A A A A
R N R R R C C C Y
L D E D C K K T X
E
O I N N
Z
Z Z
D
9
3/35
C
O
L
N
Z
TXO3RA
TXO3RB
VDD
RXI3B
RXI3A
TXO2RA
TXO2RB
RXI2B
RXI2A
TX1B
TX1A
RX1B
RX1A
VDD
CD18
AGND
CD1A
CP1_0
VCO_I
AVDD
R G C C V T T T
E N L L D E E E
S D K K D S S S
E
T T T
1 2
T
1 3 4
Z
July 21. 2003
TC3097-8-DS-R24
TC3097-8
Preliminary Data Sheet
1
Pin
1.1
Description
Config (pin 2 is connected to GND)
Pin No.
Symbol
Network Interface Pins
42, 46, 58, RXI2A to RXI9A
64, 68, 74,
83, 88
I/O
Description
I
Twisted-Pair Receive Input Positive
43, 47, 59, RXI2B to RXI9B
65, 69, 75,
84, 89
I
Twisted-Pair Receive Input Negative
45, 50, 56,
62, 66, 72,
81, 86
44, 49, 57,
63, 67, 73,
82, 87
38
TXO2RA to
TXO9RA
O
Twisted-Pair Transmit Output Positive
TXO2RB to
TXO9RB
O
Twisted-Pair Transmit Output Negative
RX1A
I
AUI Receive Input Positive
39
RX1B
I
AUI Receive Input Negative
40
TX1A
O
AUI Receive Output Positive
41
TX1B
O
AUI Receive Output Negative
34
CD1A
I
AUI Collision Detect Input Positive
36
CD1B
I
AUI Collision Detect Input Negative
Pin No.
Symbol
Power & Ground Pins
61, 71, 79 GND
I/O
Description
P
Ground pins for TP port 1 to port 8 output pins.
48, 60, 70, VDD
85
P
Power pins for TP port 1 to TP port 8 output pins.
51, 90, 100 GND
P
Ground pin for internal digital circuit of this device.
37, 55, 76, VDD
80
2, 14, 24 GND
P
Power pin for internal digital circuit of this device.
P
Ground pins for digital output pins.
1, 27
VDD
P
Power pins for digital output pins.
35
AGND
P
Ground pin for PLL decoder internal circuit.
31
AVDD
P
Power pin for PLL decoder internal circuit.
Pin No.
Symbol
I/O
Inter-LEMRIC Bus Pins
19
ACKI
I
18
O
ACKO
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Description
ACKnowledge Input:
Input to the network port’s arbitration chain.
ACKnowledge Output:
Output from the network port’s arbitration chain.
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Preliminary Data Sheet
Pin No.
Symbol
I/O
Description
Inter-LEMRIC Bus Pins
16
IRD
B,Z
Inter-LEMRIC Data:
When asserted as an output this signal provides a serial data
stream in NRZ format.
This signal is asserted by a LEMRIC when it is receiving data
from one of its network segments. The default condition of this
signal is to be an input. In this state, it may be driven by other
devices on the Inter-LEMRIC bus.
15
IREZ
B,Z
Inter-LEMRIC Enable:
When asserted as an output this signal provides an activity-framing
enable for the serial data stream. The signal is asserted by a
LEMRIC when it is receiving data from one of its network segments.
The default condition of this signal is to be an input. In this state it
may be driven by other devices on the inter-LEMRIC bus.
17
IRC
B,Z
Inter-LEMRIC Clock:
When asserted as an output this signal provides a clock signal for
the serial data stream. Data (XIRD) is changed on the falling edge of
the clock. The default condition of this signal is to be an input. When
an input, XIRD is sampled on the rising edge of the clock. In this
state it may be driven by other devices on the Inter-LEMRIC bus.
22
COLNZ
B,Z
Collision on Port N:
This denotes that a collision is occurring on the port receiving the
data packet (Port N). The default condition of this signal is to be
an input. In this state it may be driven by the other devices on the
Inter-LEMRIC bus.
20
ACTNZ
B,Z
Activity on Port N:
This is a bi-directional signal. The LEMRIC asserts this signal
when data or collision information is received from one of its
network segments. The LEMRIC senses this signal when this or
another LEMRIC in a multi-LEMRIC system is receiving data or
collision information.
21
AYXNZ
B,Z
Activity on ANY Port Excluding Port N:
This is a bi-directional signal. The LEMRIC asserts this signal
when a transmit collision is experienced or multiple ports have
active collisions on their network segments.
The LEMRIC senses this signal when this LEMRIC or other LEMRICs
in a multi-LEMRIC system are experiencing transmission collision or
multiple ports have active collisions on their network segments.
I/O
Description
LED Driver Pins
3
COLED
Pin No.
Symbol
O
Global Collision LED (Active-Low):
This CMOS output indicates the status of the LEMRIC's any
collision activity.
4
O
Global Jabber LED (Active-Low):
This CMOS output indicates when the LEMRIC's watchdog timer
begins to jab and stays active until end of the unjab wait period.
JABLED
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Preliminary Data Sheet
Pin No.
I/O
Description
LED Driver Pins
6-13
LRLED2 to
LRLED9
O
5
LRLED1
O
91-99
PALED1 to
PALED9
O
Link/Receive LED (active-Low):
This CMOS output goes active when the link integrity test is pass
on LEMRIC's TP port network segment and blinks when this
device is receiving from its link passing TP port segment.
AUI Receive LED (Active-Low):
This CMOS output is powered on active and blinking when this
device is receiving from its AUI port network segment.
Port Partition Jabber LED (Active-Low):
This CMOS output goes active when the LEMRIC's network
connection port is partitioned from its network segment and then
goes inactive when its network connection port is reconnection
from its network segment.
Pin No.
Symbol
Symbol
TEST Support Pins
28
TEST1
29
TEST3
30
TEST4
Pin No.
Description
B
These pins are used to facilitate device testing. When not in test
mode, these pins should be left open. [Note:] Pins TEST3 and
TEST4 can be used to modify the build in 10BASE-T operation.
TEST1 can be used to configure LED display mode (ICPLUS or
AMD compatible mode). Refer to port Block Function section for
more details.
I/O
Description
RESET & CLOCK Pins
23
RESETZ
I
Optional device Reset. A low on this pin causes the device to
reset. RESET must be high for normal operation, when not used,
please leave open.
25
26
I
O
System Clock. 20 MHz, 50% nominal, 40/60% worst case, duty
cycle. The worst-case frequency tolerance and duty cycle limit the
range over which the LEMRIC will operate correctly. However,
since this clock is used for Manchester data transmission, jitter
performance will degrade if clock sources with relatively large
tolerances are used.
I/O
Description
Decoder Filer Pins
33
CP1_O
I
Phase Lock Loop delay line external filter. This pin should be
connected correctly with a capacitor to AVDD or causing the
analog PLL of the device to be failed.
32
I
Phase Lock Loop VCO external filter. This pin should be
connected correctly with a RC filter circuit to AVDD or causing the
analog PLL of the device to be failed.
Pin No.
Symbol
I/O
CLK1
CLK2
Symbol
VCO_I
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TC3097-8-DS-R24
TC3097-8
Preliminary Data Sheet
2
2.1
Principles Of Operation
Reset
The LEMRIC resets when XRESETZ (pin 25) is pulsed low. While reset, the LEMRIC ignores all energy
and collision inputs, unjabs all ports, and initializes all timers, counters, and state machines. At the end of
reset (XRESETZ goes high), all the LEDs are turned off and the XLRLED1 is turned on.
The minimum XRESETZ low pulse is one second to let the power on LED test visually distinguishable.
The LEMRIC is fully operational when it exits reset.
2.2
Clock and data Recovery
The clock and data recovery circuit (Manchester decoder) is a linear circuit, which it recovers the NRZ
data and clock from the Manchester encoded serial data stream. Data from the active port is routed to
the decoder and the recovered data is written into the FIFO.
1
0
1
0
0
1
1
0
1
0
1
1
Manchester
Data
NRZ
Data
NRZ
Clock
Figure 1. Manchester Data - NRZ Data Relationship
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Preliminary Data Sheet
2.3
Functional State diagrams
The following state diagrams describe the auto-partition and global state machines implemented in the
LEMRIC. The notation and variables used in each diagram are described below.
2.3.1
TP Port Auto-Partition State Diagram
A partitioning state machine is implemented for each TP port. Individual Tw5 and Tw6 timers and collision
counters are implemented for each state machine.
2.3.1.1 State Diagram Notation and Variables.
=
Assign the right side constant or expression result to the left side variable.
&
Logical ”AND” operator.
+
Logical ”OR” operator when used in a state-exiting expression. Arithmetic addition
when used otherwise.
{[term]}
Group term for logical evaluation.
X
Number identifier for the particular TP port.
Values: Integers from 1 to 8
CC(X)
Consecutive collision count for TP port X.
Values: Integers from 0 to 31
DIPresent(X)
Carrier from the MAU on TP port X.
Values: Idle-Port carrier is not active.
Active-Port carrier is active.
Datain(X)
TP port X carrier to the global state machine.
Values: Idle-Port carrier has been gated off by the partition state machine.
DIPresent(X)-Port carrier is passed on to the global state machine.
TEN(X)
Status of transmission to the MAU on TP port X.
Values: Idle-Not transmitting to the port MAU.
Active-Transmitting to the port MAU.
/COLN
Inter-LEMRIC that is Port N or Port M collision.
Values: Idle-/COLN is not active.
Active-/COLN is active.
/ANYXN
Inter-LEMRIC that is not Port N or Port M collision.
Values: Idle-/ANYXN is not active.
Active-/ANYXN is active.
Tw5
Enable Tw5 initializes and starts the PORT Tw5 timer. Tw5Done indicates that the timer
has expired.
Tw6
Enable Tw6 initializes and starts the port Tw6 timer. /Tw6Done indicates that the timer is
running. Tw6Done indicates that the timer has expired.
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Preliminary Data Sheet
RESET
COUNT CLEAR - 0
COLLISION COUNT IDLE - 1
CC(X) = 0
Datain(X) = DIPresent(X)
Datain(X) = DIPresent(X)
TEN(X) = Idle &
DIPresent(X)=Idle
TEN(X)=Active +
DIPresent(X)=Active
WATCH FOR COLLISION - 2
Datain(X) = DIPresent(X)
Enable Tw5
PARTITION WAIT - 4
DIPresent(X)=Idle &
TEN(X)=Idle &
/COLN,/ANYXN=Idle
Datain(X) = Idle
{[TEN(X)=Active &
DIPresent(X)=Idle] +
[TEN(X)=Idle &
DIPresent(X)=Active]} &
Tw5Done &
/COLN,/ANYXN=Idle
TEN(X)=Idle &
DIPresent(X)=Idle
PARTITION HOLD - 5
[/COLN=Active +
/ANYXN=Active +
TEN(X)=Active] &
DIPresent(X)=Active
Datain(X) = Idle
COLLISION COUNT INCREMENT - 3
TEN(X)=Active +
DIPresent(X)=Active
CC(X) = CC(X) + 1
Datain(X) = DIPresent(X)
EnableTw6
CC(X) >= 31 +
[TEN(X)=Active &
DIPresent(X)=Active &
Tw6Done]
TEN(X)=Idle &
DIPresent(X)=Idle &
CC(X) < 31 & /Tw6Done
PARTITION COLLISION WATCH - 6
Datain(X) = Idle
EnableTw5
[/COLN=Active +
ANYXN=Active +
TEN(X)=Active] &
DIPresent(X)=Active
TEN(X)=Idle &
DIPresent(X)=Idle &
/COLN,/ANYXN=Idle
{[TEN(X)=Active & DIPresent(x)=Idle] +
[TEN(X)=Idle & DIPresent(X)=Active]} &
Tw5Done & /COLN, /ANYXN=Idle
WAIT TO RESTORE PORT - 7
Datain(X) = Idle
CC(X) = 0
TEN(X)=Idle & DIPresent(X)=Idle
Figure 2. Partition State Diagram for TP Port X
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Preliminary Data Sheet
2.3.2
AUI Port Auto-Partition State Diagram
A partition state machine is implemented for each AUI port. Individual Tw5 and Tw6 timers and collision
counters are implemented for each state machine.
2.3.2.1 State Diagram Notation and Variables.
=
Assign the right side constant or expression result to the left side variable.
&
Logical ”AND” operator.
+
Logical ”OR” operator when used in a state-exiting expression. Arithmetic addition when
used otherwise.
{[term]}
Group term for logical evaluation.
Y
Number identifier for the particular AUI port.
Values: Integers 0 and 1
Consecutive collision count for AUI port Y
Values: Integers from 0 to 31
CC(Y)
DIPresent(Y)
Carrier from the MAU on AUI port Y.
Values: Idle-Port carrier is not active.
Active-Port carrier is active.
Datain(Y)
AUI port carrier to the global state machine.
Values: Idle-Port carrier has been gated off by the partition state machine.
DIPresent(Y)-Port carrier is passed on to the global state machine.
CIPresent(Y)
Collision indication from the MAU on AUI Port Y.
Values: /SQE-Port collision is not active.
SQE-Port collision is active.
Collin(Y)
AUI port collision to the global state machine.
Values: /SQE-Port collision has been gated off by the partition state machine.
CIPresent(Y)-Port collision is passed on to the global state machine.
/COLN
Inter-LEMRIC that is Port N or Port M collision.
Values: Idle-/COLN is not active.
Active-/COLN is active.
Inter-LEMRIC that is not Port N or Port M collision.
Values: Idle-/ANYXN is not active.
Active-/ANYXN is active.
Enable Tw5 initializes and starts the PORT Tw5 timer. Tw5Done indicates that the timer
has expired.
/ANYXN
Tw5
Tw6
Enable Tw6 initializes and starts the port Tw6 timer. /Tw6Done indicates that the timer is
running. Tw6Done indicates that the timer has expired.
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Preliminary Data Sheet
RESET
COUNT CLEAR - 0
COLLISION COUNT IDLE - 1
CC(Y) = 0
Datain(Y) = DIPresent(Y)
Collin(Y)=CIPresent(Y)
Datain(Y) = DIPresent(Y)
Collin(Y)=CIPresent(Y)
DIPresent(Y)=Active +
CIPresent(Y)=SQE
DIPresent(Y)=Idle
&
CIPresent(Y)=/SQE
W ATCH FOR COLLISION - 2
Datain(Y) = DIPresent(Y)
Collin(Y)=CIPresent(Y)
EnableTw5
PARTITION W AIT - 4
DIPresent(Y)=Idle &
CIPresent(Y)=/SQE &
/COLN,/ANYXN=Idle
Datain(Y) = Idle
Collin(Y)=/SQE
DIPresent(Y)=Active &
CIPresent(Y)=/SQE &
Tw5Done &
/COLN,/ANYXN=Idle
DIPresent(Y)=Idle &
CIPresent(Y)=/SQE
{[/COLN=Active +
/ANYXN=Active] &
DIPresent(Y)=Active }
+
CIPresent(Y)=SQE
PARTITION HOLD - 5
Datain(Y) = Idle
Collin(Y)=/SQE
DIPresent(Y)=Active +
CIPresent(Y)=SQE
PARTITION COLLISION W ATCH - 6
Datain(Y) = Idle
Collin(Y)=/SQE
EnableTw5
/COLN=Active +
ANYXN=Active +
CIPresent(X)=SQE
COLLISION COUNT INCREMENT - 3
CC(Y) = CC(Y) + 1
Datain(Y) = DIPresent(Y)
Collin(Y)=CIPresent(Y)
EnableTw6
CC(Y) >= 31 +
[CIPresent(Y)=SQE &
Tw6Done]
DIPresent(Y)=Idle &
CIPresent(Y)=/SQE
CC(Y) < 31 & /Tw6Done
CIPresent(Y)=Idle &
DIPresent(Y)=Idle &
/COLN,/ANYXN=Idle
CIPresent(Y)=/SQE &
DIPresent(Y)=Active &
Tw5Done & /COLN, /ANYXN=Idle
W AIT TO RESTORE PORT - 7
Datain(Y) = Idle
Collin(Y)=/SQE
CC(Y) = 0
CIPresent(Y)=/SQE & DIPresent(Y)=Idle
Figure 3. Partition State Diagram for AUI Port Y
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Preliminary Data Sheet
2.3.3
Global State Diagram
A single global state machine is implemented for the LEMRIC and operates independently of the
auto-partition state machines. The machine state can be read externally on three pins when XRESETZ is
high. The table below defines the values assigned to these pins for each state.
XTEST2/GS2
0
XTEST1/GS1
0
XTEST0/GS0
0
State
0
0
0
1
1
State Name
Idle
Send Data
0
1
1
3
Receive Collision
1
0
0
4
Transmit Collision
1
1
0
1
1
0
5
6
One Port Left
Blind
2.3.3.1 State Diagram Notation and Variables.
=
Assign the right side constant or expression result to the left side variable.
&
Logical ”AND” operate.
+
Logical ”OR” operator.
:
<
Denotes that a variable assignment expression follows.
Denotes assignment of the expression result following the arrow to the variable
preceding the arrow.
{[term]}
Group term for logical evaluation.
Tw1
Enable Tw1 initializes and start the global Tw1 timer. Tw1Done indicates that the timer
has expired.
Tw2
Tw2Done indicates that the Tw2 timer has expired.
AllDatatSent
Flag indicating that all the received bits have been sent.
OUT(P)
Type of output the LEMRIC is sending to port P.
Values : Idle-The LEMRIC is not transmitting.
Data-The LEMRIC is sending Preamble, data or IDL to port P.
Jam-The LEMRIC is sending Jam to port P.
Status of port P carrier. All AUI and TP ports are considered.
Values : Idle-Port P carrier is not active.
Active-Port P carrier is active.
Datain(P)
Collin(P)
Status of AUI collision on port P.
Values : /SQE-Port P collision is not active.
SQE-Port P collision is active.
TT(P)
Indicates the number of bits transmitted to port P.
Values : Positive integers.
Port(test)
Function that returns the identifier of a port-passing test. For example, Port
(TPDatain=Active) returns an integer identifying the active TP port. If more than one port
passes the test, Only one of the acceptable values is returned.
Values : Integers from 0 to 8
N
N is defined by the Port function (see above). It identifies the port that caused an exit
from the ldle state to the Send Data or Receive Collision states.
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M
M is defined by the Port function (see above). It identifies the single port that caused an
exit from the Transmit Collision to the One Port Left state.
Values : Integers from 0 to 8.
ONLY1
General test, which is true if one and only one port is active due to carrier or collision. All
TP and AUI ports are considered.
>1
General test, which is true if greater than one port is active due to carrier or collision. All
TP and AUI ports are considered.
ANY
General test, which is true if one or more ports are active due to carrier or collision. All TP
and AUI ports are considered.
ANYXN
General test, which is true if any port other than port N, meets the test condition. For
example, TT (ANYXN) < 96 is true if a port other than port N was soured with fewer than
96 bits. All TP and AUI ports are considered.
ANYXM
General test, which is true if any port other than port M, is active due to carrier or
collision. All TP and AUI ports are considered.
General test, which is true if all ports other than port N meet the test condition. For
example TT (ALLXN) > = 96 is true if all ports other than port N were soured with at least
96 bits. All TP and AUI ports are considered.
General test, which is true if all ports other than port M meet the test condition. All TP and
AUI ports considered.
ALLXN
ALLXM
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IDLE
Power On
Out(ALL) = Idle
START
Datain(ANY) = Act. &
Collin(ALL) = /SQE
:[N <- Port ( Datain = Act. )]
BEGIN
UCT
Collin(ANY) = SQE :[ N <- Port ( Collin = SQE )
SEND PREAMBLE PATTERN
Out(ALLXN) = Preamble Pattern
Collin(N) = SQE + ( Datain(N) = Idle & Collin(ALL) = /SQE )
Collin(ANYXN) = SQE
TT(ALLXN) >= 62 & DataRdy &
Collin(ALL) = /SQE & Datain(N) = Act.
SEND TWO ONES
Out(ALLXN) = TwoOnes
Collin(N) = SQE + ( Datain(N) = Idle & Collin(ALL) = /SQE )
Collin(ANYXN) = SQE
TwoOnes Sent & Collin(ALL) = /SQE &
Datain(N) = Act.
SEND DATA
Out(ALLXN) = Data
Collin(N) = SQE + ( Datain(N) = Idle &
Collin(ALL) = /SQE & AllDataSent &
TT(ANYXN) < 96 )
Collin(ANYXN) = SQE
TRANSMIT COLLISION
RECEIVE COLLISION
Datain(N) = Idle & Collin(ALL) = /SQE &
TT(ALLXN) >= 96 & AllDataSent
Out(ALLXN) = Jam
Collin(ANYXN) = SQE
Out(ALL) = Jam
Collin(ALL) = /SQE & TT(ALL) >= 96 & Tw2Done
Collin(ONLY1) = SQE & TT(ALL) >= 96
:[ M <- Port ( Collin = SQE ) ]
Datain(N) = Idle &
Collin(ALL) = /SQE &
TT(ALLXN) >= 96 &
Tw2Done
ONE PORT LEFT
Out(ALLXM) = Jam
Collin(ANYXM)
= SQE
Datain(M) = Idle &
Collin(ALL) = /SQE &
Tw2Done
WAIT
StartTw1
Out(ALL) = Idle
Collin(ANY) = SQE +
Tw1Done
Figure 4. Global State Diagram for Multiple TP Ports and AUI Port
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2.3.4
Counters and Timers
The counters and timers specified on IEEE 802.3. Section 9, are implemented in the LEMRIC. The
function and values chosen for each is described below.
2.3.4.1 Tw1
Tw1 is the wait timer for the “End of Transmit” recovery time and it is 8 bit-times in duration. It starts when
the LEMRIC ends transmission of a packet and prevents the LEMRIC from receiving this transmission
(loop-back energy from the MAU) as a new receiving entity.
2.3.4.2 Tw2
Tw2 is the wait timer for the end of carrier recovery time and is 3 bit-times in duration. It starts when
collision on AUI port has ended. Tw2 prevents the LEMRIC from premature detecting the true
end-of-collision due to signal uncertainty on the segment at the end of a collision.
Refer to the following figure. If a collision (SQE) is detected on AUI segment, the Tw2 timer becomes
armed. Tw2 begins timing when collision is idle (/SQE). After Tw2 is done, the timer remains idle until the
next AUI collision.
RESET
IDLE
Tw2Done
Collin(ANY)=SQE
ARM
Tw2NotDone
Collin(ALL)=/SQE
Enable Tw2
TIMING
Tw2=Done
Figure 5. Tw2 State Diagram.
2.3.4.3 Tw3
Tw3 is the wait timer for length of continuous output and it has duration of 65536 bit-times . It starts when
transmission of a packet begins. If Tw3 expires before the end of packet transmission, the LEMRIC
enters the MAU jabber lockup protection condition and interrupts transmission for period Tw4. Refer to
the figure 6 for further details.
2.3.4.4 Tw4
Tw4 is the wait timer for time to disable output for MAU jabber lockup protection and it has duration of 96
bit-times . It starts d when Tw3 expires. While Tw4 is active, transmission to all ports is disabled. The
global state machine is reset to the idle state, the FIFO controller is also reset, and the clock recovery
circuit continues to decode the incoming data stream. If the port is still active when Tw4 expires, the
LEMRIC will resume transmission beginning with preamble.
The MAU lockup LED (XJABLED) is turned on to indicates the suspension of transmission. Refer to the
following figure.
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RESET
ID L E
D is a b le O u t= O F F
O U T (A N Y )= A c tive
T IM E O U T P U T
D is a b le O u t = O F F
E n a b le T w 3
O U T (A L L )= Id le
T w 3 = D o n e & O U T (A N Y )= A c tive
D IS A B L E O U T P U T
D is a b le O u t = O N
E n a b le T w 4
Tw4=Done
F ig u re 6 . M A U ja b b e r L o c k u p P ro te c tio n S ta te D ia g ra m
2.3.4.5 Tw5
Tw5 is the auto-partition wait timer for length of packet without collision and it has duration of 512
bit-times. It starts when carrier (or collision on AUI ports) from a port becomes active. If a collision is
detected before Tw5 expires, the collision count for that port is incremented and the port Tw6 timer will
be started. Tw5 is also used in the auto-partition algorithm to exit the Partition collision Watch state. A
separate Tw5 timer is implemented for each of the TP and AUI ports.
Refer to the auto-partition state diagrams for specific timer operation.
2.3.4.6 Tw6
Tw6 is the auto-partition wait timer for excessive length of collision and it has duration of 1024 bit-times.
It starts if a collision (multiple active port or SQE) is detected before Tw5 expires. If the collision condition
persists when Tw6 expires. The energy and data from that port are partitioned (jabbed). A separate Tw6
timer is implemented for each of the TP and AUI ports.
Refer to the auto-partition state diagrams for specific timer operation.
2.3.4.7 Collision counter
The collision counter maintains the number of consecutive collisions for a particular port. If the collision
limit is reached, the energy and data from that port are partitioned (jabbed). A separate collision counter
with limit 31 is implemented for each of the TP and AUI ports.
2.3.4.8 Transmit Timer
The transmit timer counts the number of bits transmitted to a port. If the total number of bits transmitted is
less than 96 (due to reception of a packet fragment), the LEMRIC will enter the Receive Collision global
state and transmit Jam until the transmit timer reaches a count of 96. There by extending the bit stream to
greater or equal to 96 bits time.
The transmit timer is cleared when the LEMRIC enters the Transmit Collision global state. This ensures
that at least 96 bits of jam signals are transmitted to all ports before the LEMRIC exits the Transmit
Collision state. This also means that the LEMRIC will have transmitted more than 96 bits of jam signals
to all but one port if the transmit collision state was entered from the Receive collision state. Refer to the
following figure and the global state diagrams for transmit timer operation.
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RESET
TTIDLE
TT(X) = 0
OUT(X)=Active & Bit Transmitted
COUNTING
TT(X) = TT(X)+1
HOLD
TT(X)
OUT(X) = Idle+
Global Stats S - > Tcollision
Bit Transmitted
Figure 7. Transmit Timer State Diagram for Port X.
2.3.5
Automatic Preamble Regeneration
Automatic preamble regeneration (APRG) prevents the preamble from shrinking as a packet is passed
from repeater to repeater or station to station. This shrinking, or loss of bits, is due to the bit cost of
determing the presence of carrier and synchronizing of the Manchester data for NRZ data and clock
recovery. The LEMRIC compensates for the bit loss by transmitting greater or equal to 56 bits of
preamble before sending the Start of Frame Delimiter (SFD) pattern.
2.3.5.1 APRG Circuit Operation
When carrier is detected, the LEMRIC begins sending preamble and searches for the SFD pattern in the
recovered NRZ data. The delay from carrier transition to the first transmitted bit of preamble is four to five
bit-times for AUI carrier and eight to nine bit-times for TP carrier. The LEMRIC begins to search for the
eight-bit SFD pattern 15 to 16 bits after the carrier transition.
When the SFD pattern is detected, the data followed by the SFD is loaded into a 64-bit FIFO. After the
preamble bits are sent, the SFD pattern will be sent next, and then finally the FIFO data will be
transmitted. Since at least 56 bits of preamble must be sent, the FIFO must be of sufficient depth to store
the data after the SFD pattern. A FIFO depth of 64 is chosen to allow the processing of packet with very
few bits of preamble before SFD.
The FIFO watermark is achieved by reloading the FIFO with part of the SFD pattern. A preamble counter
maintains the number of preamble bits transmitted, and is implemented such that the total count equals
56 plus the number of SFD bits not reloaded into the FIFO. For a watermark of four bits, the preamble
counter counts to 60 (56 preamble bits plus the first four bits of SFD). The received packet must contain
at least 16 preambles bits for the LEMRIC to detect SFD. There is no upper limit on the number of
preamble bits received.
The latency of bits through the LEMRIC is inversely related to the number of preamble bits received.
That is the data in a packet with a small number (less than 56) of preamble bits must be stored (and
therefore be held a longer period of time) until the full preamble can be regenerated.
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For a packet with a large number (greater or equal to 56) of preamble bits, the latency will approach the
processing time of the LEMRIC (including watermark) to get a bit from the input through the FIFO to the
output. If the number of preamble bits received is greater than 56, the LEMRIC will add up to four
preamble bits to the packet for TP carrier and up to eight preamble bits for AUI carrier.
The leading edge of the first preamble bit transmitted by the LEMRIC, as seen on the line. Denotes the
beginning of a 100 nanosecond positive (TTL logic one).
2.3.5.2 APRG State Diagram
The following state diagram describes the LEMRIC APRG operation. When carrier is detected, the
APRG circuit waits from four to noise bit-times and then begins sending preamble. The preamble counter
(PC) increments for each preamble bit sent. When the SFD pattern is detected (all eight bits), the data
bits are loaded into the FIFO and the SFD pattern is sent. The error paths indicate some sort of packet
abort, such as collision, Manchester code violation, FIFO error, or premature end of packet. The state
diagram notation is similar to that of the global state diagram.
RESET
IDLE
OUT = Idle
PC = 0
Carrier
PREAMBLE DELAY
OUT = Idle
Error
Delay Complete
LOOK FOR SFD
OUT = Preamble Bit
Error
COUNT
SFD Detected
: [FIFO < - Data after SFD]
PC = PC + 1
PREAMBLE COUNT
OUT = Preamble Bit
Error
PC > = 60
COUNT
PC<60
PC = PC + 1
OUT SFD
OUT = Remaining
SFD Bits
Error
DATA
OUT = FIFO Data
Error+FIFO Empty
Figure 8. State Diagram for Automatic Preamble Regeneration
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2.3.6
Inter-LEMRIC Bus Operation
The Inter-LEMRIC Bus consists of eight signals. These signals implement a protocol, which may be used
to connect multiple LEMRICs together. In this configuration, the logical function of a single repeater is
maintained. The resulting multi-LEMRIC system is compliant to the IEEE 802.3 Repeater Specification
and may connect serval hundred network segments. An example of a multi-LEMRIC system is shown as
follow below:
/A C K I
A
RX
A1
B U S S IG N A LS
CD
A1
LEM R IC A
TX
A1
BUS CO NTENTS :
/C O LN
IR C
/IR E
IR D
/A N Y X N
/A C T N
NETW ORK
SEGM ENT
X
C
V
R
/A C K O
A
A D D IT IO N A L
XC V R S
AND
SEGM ENTS
/A C K I
B
RX
B1
CD
B1
LEM R IC B
TX
B1
/A C K O
B
NETW ORK
SEGM ENT
X
C
V
R
A D D IT IO N A L
XC V R S
AND
SEGM ENTS
Figure 9. M U LTI-LE M R IC s S ystem T opopogy
The Inter-LEMRIC bus connects multiple LEMRICs to realize the following operations:
Port N Identification (which port the repeater receives data from)
Port M Identification (which port is the last one experiencing a collision)
Data Transfer
RECEIVE COLLISION Identification
TRANSMIT COLLISION Identification
DISABLE OUTPUT (jabber protection)
The following tables briefly describe the operation of each bus signal, the conditions required for a
LEMRIC to assert a signal and which LEMRICs (in a multi-LEMRIC system) would monitor a signal:
ACKI
Function
Input signal to the Inter-LEMRIC arbitration chain. This chain is employed
to identify PORT N and PORT M.
Note: LEMRIC contains PORT N or PORT M, it may be identified by its
ACKO signal being low when its ACKI input is high.
Conditions required for a Not Applicable
LEMRIC to drive this signal
LEMRIC Receiving the Signal This is dependent upon the method used to cascade LEMRICs, described
in Section 1.3.6.2.
ACKO
Function
Output signal from the Inter-LEMRIC arbitration chain.
Conditions required for a This is dependent upon the method used to cascade LEMRICs described
LEMRIC to drive this signal in Section 1.3.6.2.
LEMRIC Receiving the Signal Not applicable
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/ACTN
Function
This signal denotes there is activity on PORT M.
Conditions required for a A LEMRIC must contain PORT N or PORT M.
LEMRIC to drive this signal Note: Although this signal normally has only one source asserting
the signal active it is used in a wired-OR configuration.
LEMRIC Receiving the Signal This signal is monitored by all LEMRICs in the repeater system.
/ANYXN
Function
This signal denotes that a repeater port that is not PORT N or PORT M is
experiencing a collision.
Conditions required for a Any LEMRIC that satisfies the above condition.
LEMRIC to drive this signal Note : This bus line is used in a wired-OB configuration.
LEMRIC Receiving the Signal This signal is monitored by all LEMRICs in the repeater system.
/COLN
Function
Denotes PORT N or PORT M is experiencing a collision.
Conditions required for a A LEMRIC must contain PORT N or PORT M.
LEMRIC to drive this signal
LEMRIC Receiving the Signal The signal is monitored by all other LEMRICs in the repeater system.
/IRE
Function
This signal acts as an activity-framing signal for the IRC and IRD signals.
Conditions required for a A LEMRIC must contain PORT N.
LEMRIC to drive this signal
LEMRIC Receiving the Signal The signal is monitored by all other LEMRICs in the repeater system.
/IRD
Function
Decoded serial data, in NRZ format, received from the network segment
attached to PORT N.
Conditions required for a A LEMRIC must contain PORT N.
LEMRIC to drive this signal
LEMRIC Receiving the Signal The signal is monitored by all other LEMRICs in the repeater system.
/IRC
Function
Clock signal associated with IRD and IRE.
Conditions required for a A LEMRIC must contain PORT N.
LEMRIC to drive this signal
LEMRIC Receiving the Signal The signal is monitored by all other LEMRICs in the repeater system.
2.3.6.1 Methods of LEMRIC Cascading
In order to build multi-LEMRIC repeaters, PORT N and PORT M identification must be performed across
all the LEMRICs in the system.
The top of the chain, the input to Port 1 is accessible to the user via the LEMRIC's /ACKI input pin. The
output from the bottom of the chain becomes the /ACKO output pin. In a single LEMRIC system PORT N
is defined as the port in the arbitration chain with receive or collision activity. PORT N identification is
performed when the repeater is in the IDLE state. In order for the arbitration chain to function, all that
needs to be done is to tie the /ACKI signal to a logic high state. In multi-LEMRIC systems there are two
methods to propagate the arbitration chain between LEMRICs:
The first and most straightforward way is to extend the arbitration chain by daisy-chaining the
/ACKI-/ACKO signals between LEMRICs. In this approach one LEMRIC is placed at the top of the chain
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(its /ACKI input is tied high), then the /ACKO signal from this LEMRIC is send to the /ACKI input of the
next LEMRIC and so on. This arrangement is simple to implement but it places some topological
restrictions upon the repeater system. In particular, when the repeater is constructed using a backplane
with removable printed circuit boards containing the LEMRICs, If one of the boards is removed then the
/ACKI-/ACKO chain will be broken and the repeater will not operate correctly.
The second method of PORT N or PORT M identification avoids this problem. This second technique
relies on an external parallel arbiter, which monitors all of the LEMRIC's /ACKO signals and responds to
the LEMRIC with the highest priority. In this scheme each LEMRIC is assigned with a priority level. One
method of doing this is to assign a priority number, which reflects the position of a LEMRIC board on the
repeater backplane (i.e., its slot number). When a LEMRIC experiences receive activity and the repeater
system is in the IDLE state, the LEMRIC board will assert /ACKO. External arbitration logic drives the
identification number onto an arbitration bus and the LEMRIC containing PORT N will be identified. An
identical procedure is used in the TRANSMIT COLLISION state to identify PORT M. This parallel means
of arbitration is not subject to the problems caused by missing boards (I. e., empty slots in the backplane).
The logic associated with asserting this arbitration vector in the various in the various packet repetition
scenarios could be implemented in PAL or GAL type devices.
To perform PORT N or PORT M arbitration, both of the above methods employ the same signals: /ACKI,
/ACKO, and /ACTN.
The Inter-LEMRIC bus allows multi-LEMRIC operations to be performed in exactly the same manner as
if there is only a single LEMRIC in the system. The simplest way to describe the operation of
Inter-LEMRIC bus is to see how it is used in a number of common packet repetition scenarios.
2.3.6.2 EXAMPLES OF PACKET REPETITION SCENARIOS
Data Repetition
The simplest packet operation performed over the Inter-LEMRIC Bus is data repetition. In this operation
a data packet is received at one port and transmitted to all other segments.
The first task to be performed is PORT N identification. In situations where two or more ports
simultaneously receive packets the Inter-LEMRIC bus operates by choosing one of the active ports and
forcing the others to transmit data. This is done to faithfully follow the IEEE specification's allowed exit
paths from the IDLE state (I. e., to the SEND PREAMBLE PATTERN or RECEIVE COLLISION states).
The packet begins with a preamble pattern derived from the LEMRIC's on chip jam/preamble generator.
The data received at PORT N is directed through the receiving multiplexer to the PLL decoder. Once
phase lock has been achieved, the decoded data, in NRZ format, with its associated clock and enable
signals are asserted onto to IRD, /IRE and IRC Inter-LEMRIC bus lines, This serial data stream is
received from the bus by all LEMRICs in the repeater and directed to their Elasticity Buffers. Logic circuit
monitors the data stream and look for the Start of Frame Delimiter (SFD).
When this has been detected data is loaded into the elasticity buffer for later transmission. This will occur
when sufficient preamble has been transmitted and certain internal state machine operations have been
fulfilled.
Figure 11 shows two LEMRICs, A and B, daisy-chained together with LEMRIC A positioned at the top of
the chain. A packet is received at port B1 of LEMRIC B and is then repeated by the other ports in the
system. Figure 12 shows the functional timing diagram for this packet repetition represented by the
signals shown in figure 11. In this example only two ports in the system are shown, obviously the other
port also repeat the packet. It also indicates the operation of the LEMRIC's state machines in so far as
can be seen by observing the Inter-LEMRIC bus. For reference, the repeater's state transitions are
shown in terms of the states defined by the IEEE specification. The location (I. e., which port it is) of
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PORT N is also shown. The following section describes the repeater and Inter-LEMRIC bus transitions
shown in figure 10.
(NOTE1*)
RX
A1
CD
(HIGH)
A1
TX
A1
/ACKO
/ACKIB
A
(HIGH)
RX
B1
CD
(HIGH)
B1
TX
(HIGH)
B1
/ACKO
B
/ACTN
/ANYXN (HIGH)
/COLN (HIGH)
/IRE
IRD
IRC
PORT
ARB'
INTER-LEMRIC
BUS STATES
REPEATER
REPEAT
IDLE
IDLE
SEND PREAMBLE
SEND SFD
IDLE
W AIT
SEND
IDLE
STATES
PORT N
XX
PORT B1
NOTE 1:The activity shown on RX
represents the transmitted signal on TX
A1
XX
after being looped back by the attached
.
A1
FIGURE 10. Data
The repeater is stimulated into activity by the data signal received by port B1. The LEMRICs in the system
are alerted to forthcoming repeater operation by the falling edges on the /ACKI-/ACKO daisy chain and the
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/ACTN bus signal, following a defined start up delay the repeater moves to the SEND PREAMBLE state.
The LEMRIC system utilizes the start up delay to perform port arbitration. When packet transmission
begins the LEMRIC system enters the REPEAT state. The expected, for normal packet repetition,
sequence of repeater states, SEND PREAMBLE, SEND SFD and SEND DATA is followed but is not visible
upon the Inter-LEMRIC bus. They are merged together into a single REPEAT state. This is also true for the
WAIT and IDLE states; they appear as a combined Inter-LEMRIC bus IDLE state.
Once a repeat operation has begun (I. e., the repeater leaves the IDLE state) it is required to transmit at
least 96 bits of data or jam/preamble into its network segments.
If the duration of the received signal from PORT N is smaller than 96 bits, the repeater transitions to the
RECEIVE COLLISION state (described later). This behavior is known as fragment extension. After the
packet data has been repeated, including the emptying of the LEMRICs' elasticity buffers, the LEMRIC
performs the Tw1 transmit recovery operation. This is performed during the WAIT state shown in the
repeater state diagram.
2.3.6.3 EXAMPLES OF PACKET REPETITION SCENARIOS
Receive Collisions
A receive collision is a collision which occurs on the network segment attached to PORT N (i.e., the
collision is ”received” in a similar manner as a data packet is received and then repeated to the other
network segments). The receiving collision propagation follows a similar sequence of operations as is
found with data repetition:
An arbitration process is performed to find PORT N and a preamble/jam pattern is transmitted by the
repeater's other ports. When PORT N detects a collision on its segment the /COLN Inter-LEMRIC bus
signal is asserted. This forces all the LEMRICs in the system to transmit a preamble/jam pattern to their
segments. This is important since they may be already transmitting data from their elasticity buffers. The
repeater moves to the RECEIVE COLLISION state when the LEMRICs begin to transmit the jam pattern.
The repeater remains in this state until both the following conditions have been fulfilled:
1. At least 96 bits have been transmitted onto the network,
2. The activity has ended.
Under close examination the repeater specification reveals that the actual end of activity has its own
permutations of conditions:
1. Collision and receive data signals may end simultaneously,
2. Receive data may appear to end before collision signals,
3. Receive data may continue for some time after the end of the collision signal.
Network segments using coaxial media may experience spurious gaps in segment activity when the
collision signal goes inactive. This arises from the inter-action between the received and collision signal
squelch circuits. Implemented in coaxial transceivers, and the properties of the coaxial cable itself. The
repeater specification avoids propagation of these activity gaps by extending collision activity by the Tw2
wait time. Jam pattern transmission must be sustained throughout this period. After this, the repeater will
move to the WAIT state unless there is a data signal being received by PORT N.
The functional timing diagram, figure 11, shows the operation of a repeater system during a receive
collision. The system configuration is the same as earlier described and is shown in Figure 9.
The LEMRICs perform the same PORT N arbitration and data repetition operations as previously
described. The system is notified of the receive collision on port B1 by the /COLN bus signal going active.
This is the signal, which informs the main state machines to output the jam pattern rather than the data
held in the elasticity buffers. Once a collision has occurred the IRC, IRD and /IRE bus signals may
become undefined. When the collision has ended and the Tw2 operation performed, the repeater moves
to the WAIT state.
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RX
A1
CD
A1
TX
(HIGH)
A1
/ACKO A (HIGH)
/ACKI B
RX
B1
CD
TX
B1
B1
(HIGH)
(HIGH)
/ACKO B
/ACTN
/ANYXN (HIGH)
/COLN
(HIGH)
/IRE
IRD
IRC
INTER-LEMRIC
BUS STATES
IDLE
REPEATER
STATES
IDLE
PORT N
XX
PORT
ARB'
REPEAT
RXCOL
NOTE 1
RECEIVE COLLISION
PORT B1
IDLE
WAIT
IDLE
XX
NOTE1 : SEND PREAMBLE, SEND SFD , SEND DATA
FIGURE 11. Receive Collision
2.3.6.4 EXAMPLES OF PACKET REPETITION SCENARIOS
Transmit Collisions
A transmit collision is a collision that is detected upon a segment to which the repeater system is
transmitting. The state machine monitoring the colliding segment asserts the /ANYXN bus signal. The
assertion of /ANYXN causes PORT M arbitration to begin. The repeater moves to the TRANSMIT
COLLISION state when the port, which had been PORT N starts to transmit a Manchester encoded 1 on
to its network segment. While in the TRANSMIT COLLISION state all ports of the repeater must transmit
the 1010... jam pattern and PORT M arbitration is performed. Each LEMRIC is obliged, by the IEEE
specification, to ensure all of its ports transmit for at least 96 bits once the TRANSMIT COLLISION state
has been entered. This transmit activity is enforced by the /ANYXN bus signal. While /ANYXN is active
all LEMRIC ports will transmit jam. To ensure this situation lasts for at least 96 bits, the MSMs (Main state
Machine) inside the LEMRICs assert the /ANYXN signal throughout this period. After this period has
elapsed, /ANYXN will only be asserted if there are multiple ports with active collisions on their network
segments.
There are two possible ways for a repeater to leave the TRANSMIT COLLISION state. The most
straightforward is when network activity (I. e., collisions and their Tw2 extensions) end before the 96-bits
enforced period expires. Under these conditions the repeater system may be move directly to the WAIT
state when 96 bits have been transmitted to all ports. If the MSM enforced period ends and there is still
one port experiencing a collision the ONE PORT LEFT state is entered. This may be seen on the
Inter-LEMRIC bus when /ANYXN is reasserted and PORT M stops transmitting to its network segment.
In this circumstance the Inter-LEMRIC bus transitions to the RECEIVE COLLISION state. The repeater
will remain in this state while PORT M's collision, Tw2 collision extension and any receive signals are
present. When these conditions are not true, packet repetition finishes and the repeater enters the WAIT
state.
Figure 12 shows a multi-LEMRIC system operating under transmit collision conditions. There are many
different scenarios which occur during a transmit collision; this figure illustrates one of these. The
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diagram begins with packet reception by port A1. Port B1 experiences a collision, since it is not PORT N
it asserts /ANYXN. This alerts the MSMs in the system to switch from data to jam pattern transmission.
Port A1 is also monitoring the /ANYXN bus line. Its assertion forces A1 to relinquish its PORT N status,
start transmission, stop asserting /ACTN and release its hold on the arbitration signals (/ACKO A and
/ACKI B). The first bit it transmits will be a Manchester encoded ”1” in the jam pattern.
Since port B1 is the only port with a collision, it attains PORT M status and stop asserting /ANYXN. It
does however assert /ACTN, and exert its presence upon the arbitration chain (forces /ACKO B low).
The MSMs ensure that /ANYXN stays active and thus forces all of the ports, including PORT M, to
transmit to their segments.
After some time, port A1 experience of the packet being received from port A1's segment plus the jam
signal the repeater is now transmitting onto this segment. Two packets transmit as one segment, which
results in a collision. PORT M now moves from B1 to A1. Port A1 fulfills the same criteria as B1 (I. e., it
has an active collision on its segment), but in addition it is higher in the arbitration chain.
RX
A1
CD
A1
TX A1
/ACKO A
/ACKI B
RX
B1
CD
B1
TX B1
/ACKO B
/ACTN
/ANYXN
/COLN
/IRE
IRD
IRC
INTER-LEMRIC
BUS STATES
TX TO ALL
REPEAT
REPEATER
STATES
SEND DATA
PORT N
OR
PORT M
PORT A1
PORT N
TRANSMIT COLLISION
XX
PORT B1
PORT M
IDLE
RXCOL
ONE PORT LEFT
PORT A1
PORT M
WAIT
XX
FIGURE 12. Transmit Collision
Eventually the collision on port B1 ends and the /ANYXN extension by the MSMs expires. There is only
one collision on the network (this may be deduced since /ANYXN is inactive) so the repeater will move to
the ONE PORT LEFT state. The LEMRIC system treats this state in a similar manner to a receive
collision with PORT M fulfilling the role of the receiving port. The difference from a true receive collision is
that the switch from packet data to the jam pattern has already been made (controlled by /ANYXN). Thus
the state of /COLN has no effect upon repeater operation. In common with the operation of the RECEIVE
COLLISION state, the repeater remains in this condition until the collision and receive activity on PORT
M subside. The packet repetition operation completes when the Tw1 recovery time in the WAIT state has
been performed.
2.3.6.5 EXAMPLES OF PACKET REPETITION SCENARIOS
Jabber Protection
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A repeater is required to disable transmit activity if the length of its current transmission reaches the
jabber protect limit. This is defined by the IEEE specification's Tw3 time. The repeater disables output
for a time period defined by the Tw4 specification, after this period normal operation may resume.
Figure 13 shows the effect of a jabber length packet upon a LEMRIC based repeater system. The
JABBER PROTECT state is entered from the SEND DATA state. While the Tw4 period is observed the
Inter-LEMRIC bus displays the IDLE state. This is misleading since new packet activity or continuous
activity (as shown in the diagram) does not result in packet repetition. This may only occur when the Tw4
requirement has been satisfied.
RX
A1
CD
TX
A1
A1
(HIGH)
(HIGH)
/ACKO A
/ACKI B
RX
B1
CD
TX
B1
(HIGH)
B1
/ACKO B
/ACTN
/ANYXN (HIGH)
/COLN
(HIGH)
/IRE
IRD
IRC
INTER-LEMRIC
BUS STATES
IDLE
+
PORT ARB
REPEAT
REPEATER
STATES
SEND DATA
PORT N
PORT A1
JABBER PROTECT
(NOTE 1*)
XX
REPEAT
SEND PREAMBLE
PORT A1
Note 1: The IEEE Specification does not have a jabber protect state defined in its main state diagram,this behavior is defined in an additional MAU Jabber Lockup
Protection state diagram.
FIGURE 13. Jabber Protect
2.3.7
Port Block functions
The LEMRIC has 8 port logic blocks (one for each network connection). In addition to the packet
repetition operations already described, the port block performs two other functions:
1. The physical connection to the network segment (transceiver function).
2. It provides a means to protect the network from malfunctioning segments (segment partition).
2.3.7.1 TRANSCEIVER FUNCTIONS
The LEMRIC may connect to network segments in two ways:
1. Over AUI cable to transceiver boxes (Port 1)
2. To twisted pair cable via a simple interface.
The first method is only supported by LEMRIC Port 1 (the AUI port). The other is available on Ports 2 to 9.
The LEMRIC contains virtually all the digital and analog circuits required for connection to 10BASE-T
network segments. The only optional additional active component is an external drive package. The
connection for a LEMRIC port to a 10BASE-T segment is shown in figure 14. The diagram shows the
components required to connect one of the LEMRIC's ports to a 10BASE-T segment (and lists a few
module P/Ns and vendors). The major components are the integrated filter-transformer-choke module
(or discrete combination of these functions).
The operation of the 10BASE-T transceiver's logical functions may be modified by hardware reset
control. The default mode of operation is for the transceiver  to transmit and expect reception of link
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pulses. This may be modified if the XTEST4 pin pulled down (pull down resistor is needed) before
hardware reset operation. The port's transceiver will operate normally but will not transmit link pulses
nor monitor their reception. Thus the entry to a link fail state and the associated modification of
transceiver operation will not occur until another hardware reset and new logic setting on XTEST4 pin.
The on-chip 10BASE-T transceivers automatically detect and correct the polarity of the received data
stream. This polarity detection scheme relies upon the polarity of the received link pulses and the end of
packet waveform. Polarity detection and correction may be disable through XTEST3 pin pulled down by
a resistor before hardware reset operation and the associated modification of transceiver operation will
not occur until another hardware reset and new logic setting on XTEST3 pin.
When using external transceivers the user must perform collision detection and the other functions
associated with an IEEE 802.3 Media Access Unit. Figure 15 shows the connection between a repeater
port and a coaxial transceiver using the AUI type interface.
INTEGRATED
MODULE
TD+
TXORA
LPF
TXORB
TD -
1:1
COMMON
MODE
CHOKES
0.047 uF
1:1
XRXI+
RD+
51 Ohm
LPF
XRXI-
RD-
51 Ohm
0.047 uF
Vendor
Pulse Engineering
Bel Fuse
Valor
Filter-Transformer-Choke Modules
PE65424,PE65434,PE65431
0556-2006-00,0556-2006-01
FL1010 (4 Channel),FL1012*,FL1020
* There is a single common mode choke on the transmit channel only.
FIGURE 14 . Port Connection to a 10BASE-T Segment and Some
Typical Filter-Transformer-Choke Modules
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DP8392
120 Ohm
7 TX+
8 TX -
XTX1A
L
E
M
R
I
C
XTX1B
120 Ohm
RR+ 11
RR - 12
PULSE
59
Ohm
59
Ohm X'FORM
1K Ohm,1%
78 Ohm
1 CD+
2 CD -
XCD1A
XCD1B
3 RX+
6 RX -
XRX1A
XRX1B
CDS 16
RXI 14
TXO
4 VEE
5 VEE
1.5K Ohm x 4
13 VEE
0.01 uF
1 IN
47 uF
+
24
OUT 10
15
DC TO DC
CONVERTER
12 GND
13
ISOLATED 11
GND 14
BNC
CONNECTOR
15
15
HBE
9
GND 10
0.01 uF
1M Ohm
1/2 W
SPARK
GAP
FIGURE 15. Port Connection to a 10BASE2 Segment ( AUI Interface )
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3
Absolute
Maximum
Ratings
Supply Voltage (VCC)
4.75V
to
5.25V
DC Input voltage (VIN)
-0.5V
to
VCC+0.5V
DC Output Voltage (VOUT)
-0.5V
to
VCC+0.5V
Ambient Temperature Under Bias
0C
to
70C
Storage Temperature Range (TSTG)
-40C
to
125C
Operating Temperature Range
Power Dissipation (PD)
0C
250mW
to
to
70C
1150mW
4
D.C.
Characteristics
Symbol
VOH
Description
Minimum High Level Output Voltage
Conditions
IOH=-4mA
Min.
2.4
-
Units
V
VOL
Minimum Low Level Output Voltage
IOL=8mA
-
0.4
V
VIH
Minimum High Level Input Voltage
VCC=5V
2.0
VCC
V
VIL
IIL
Maximum Low Level Input Voltage
Input Low Current
VCC=5V
VIN=1.0V
VSS
-
0.8
-0.5
V
uA
IIH
Input High current
VIN=VCC
-
20
uA
ICC
Supply current
-
230
mA
VDS
Differential Squelch Threshold (XRX1+-,
XCD1+-)
Minimum Receive Squelch Threshold
(Twisted-Pair Port 2-9)
+-190
+-280
mV
+-200
+-460
mV
VRON
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5
Switching
Characteristics
PORT ARBITRATION TIMING
ACKI
T1
T2
ACKO
Symbol
ackilackol
T1
Number
Parameter
ACKI Low to ACKO Low
ackihackoh
T2
ACKI High to ACKO High
Min
Max
220
Units
ns
220
ns
Max
350
2000
350
2060
Units
ns
ns
ns
ns
Note : Timing valid with no receive or collision activities.
RECEIVE TIMING-AUI PORTS
Receive activity propagation start up and end delays for ports in non 10BASE-T mode.
RX
T5a
T6a
T3a
T4a
ACTN
ACKO
Symbol
rxaackol
rxiackoh
rxaactnl
rxiactnh
Number
T3a
T4a
T5a
T6a
Parameter
RX Active to ACKO Low
RX Inactive to ACKO High (Note 1)
RX Active to ACTN Low
RX Inactive to ACTN High (Note 1)
Min
250
1900
250
1960
Note : ACKI assumed high
Note 1 : This time includes EOP. & FIFO Data clear time.
RECEIVE TIMING-10BASE-T PORTS
Receive activity propagation start up and end delays for ports in 10BASE-T mode
RX
T5t
T6t
T3t
T4t
ACTN
ACKO
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Symbol
rxaackol
rxiackoh
Number
T3t
T4t
Parameter
RX Active to ACKO Low
RX Inactive to ACKO High (Note 1)
Min
550
1300
Max
650
1400
Units
ns
ns
rxaactnl
rxiactnh
T5t
T6t
RX Active to ACTN Low
RX Inactive to ACTN High (Note 1)
550
1360
650
1460
ns
ns
Note : ACKI assumed high.
Note 1 : This time includes EOP. & FIFO Data clear time.
TRANSMIT TIMING-AUI PORTS
Transmit activity propagation start up and end delays for ports in non 10BASE-T mode
CLOCK
T16a
ACTN
T15a
TX
Symbol
actnltxa
clkitxa
Number
T15a
T16a
Parameter
Min
/ACTN Low to TX Active
CLOCK in to TX Active (Note 1)
Max
Units
260
270
ns
ns
Max
260
Units
ns
270
ns
Note : ACKI assumed high.
Note 1 : Clock not drawn to scale.
TRANSMIT TIMING-10BASE-T PORTS
Receive activity propagation start up and end delays for ports in 10BASE-T mode
CLOCK
T16t
ACTN
T15t
TX
Symbol
actnltxa
Number
T15a
Parameter
/ACTN Low to TX Active
clkitxa
T16a
CLOCK in to TX Active (Note 1)
Min
Note : ACKI assumed high.
Note 1 : Clock not drawn to scale.
COLLISION TIMING-AUI PORTS
Collision activity propagation start up and end delays for ports in non 10BASE-T mode
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TRANSMIT COLLISION TIMING
ACKO
T29
CD
T30a
T31a
ANYXN
Symbol
cdiackoh
Number
T29
Parameter
CD Inactive to ACKO High
Min
450
Max
550
Units
ns
cdaanyxnl
T30a
CD Active to ANYXN Low
100
200
ns
cdianyxnh
T31a
CD Inactive to ANYXN High (Notes 1,2)
510
610
ns
Note 1 : TX collision extension has already been performed and no other port is driving /ANYXN.
Note 2 : Includes TW2.
RECEIVE COLLISION TIMING
CD
T32a
T33a
COLN
T38
T39
JAM
DATA
TX
Symbol
cdacoina
cdicolni
Number
T32a
T33a
Parameter
CD Active to /COLN Low
CD Inactive to /COLN High
colnljs
colnhje
T38
T39
/COLN Low to Start of JAM
/COLN High to End of JAM (Note 1)
Min
100
510
Max
200
610
Units
ns
ns
300
350
ns
ns
Note 1: Reception ended before /COLN goes high.
COLLISION TIMING-10BASE-T PORTS
Collision activity propagation start up and end delays for parts in 10BASE-T mode
TX
RX
T30t
T31t
ANYXN
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Symbol
colaanyl
Number
T30t
Parameter
Collision Active to /ANYXN Low
Min
550
Max
650
Units
ns
colianyh
T31t
Collision inactive to /ANYXN High (Note 1)
360
460
ns
Note 1 : TX collision extension has already been performed and no other port is asserting /ANYXN.
COLLISION TIMING-ALL PORTS
ACTN
ACKI
T41
ANYXN
T34
T40
TX
Symbol
T34
T35
T40
T41
T35
JAM
DATA
Number
anylmin
anyhtxai
anylsj
ackihanyh
Parameter
/ANYXN Low Time
/ANYXN High to TX to All Inactive
/ANYXN Low to Start of JAM
ACKI High to /ANYXN High
Min
96
Max
350
300
260
Units
bits
ns
ns
ns
Max
150
200
Units
ns
ns
COLLISION TIMING-ALL PORTS
ACTN
T36
ANYXN
TX
T37
TX
one port left
Symbol
T36
T37
Number
actnntxi
anyhtxoi
Parameter
/ACTN High to TX Inactive
/ANYXN High to TX ”One Port Left”
Inactive
Min
Note : 96 bits of JAM have already been propagated.
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INTER-LEMRIC BUS OUTPUT TIMING
T105
ACTN
T109
IRE
T110
T106
T103
IRC
T102
T101
IRD
T108
T107
Symbol
Number
Parameter
Min
Max
Units
ircoh
T101
IRC Output High Time
40
60
ns
ircol
ircoc
T102
T103
IRC Output Low Time
IRC Output Cycle Time
40
80
60
120
ns
ns
actnolireol
T105
/ACTN Output Low to /IRE Output Low
10
ns
reolirca
T106
IRD Output Low to IRC Active
940
ns
irdov
T107
IRD Output valid from IRC
10
ns
irdos
ircohireh
T108
T109
IRD Output Stable Valid Time
IRC Output High to /IRE High
90
50
65
ns
ns
ircclks
T110
Number of IRCs after /IRE High
5
5
clocks
INTER-LEMRIC BUS INPUT TIMING
IRE
T116
IRC
T111
T114
T112
T115
IRD
Symbol
Number
Parameter
Min
Max
Units
ircih
ircil
T111
T112
IRC input High Time
IRC input Low Time
30
30
ns
ns
irdisirc
T114
IRD input setup to IRC
10
ns
irdihirc
T115
IRD input Hold from IRC
10
ns
ircihireh
T116
IRC Input High to /IRC High
25
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ns
July 21. 2003
TC3097-8-DS-R24
TC3097-8
Preliminary Data Sheet
6
Package Detail
He
A2
A1
Y
E
MILLIMETER
MIN.
NOM .
M AX.
A1
0.05
0.25
0.50
A2
2.57
2.72
2.87
b
0.20
0.30
0.40
c
0.10
0.15
0.20
D
13.90
14.00
14.10
E
19.90
20.00
20.10
e
D
Hd
SYMBOL
0.65
Hd
17.75
17.90
18.15
He
23.75
23.90
24.15
L
0.73
0.88
1.03
L1
1.95
Y
0.08
10
e
b
0.13(0.005)
M
C
L
L1
0
Note:For Exact Dimension,
Please use metric.
Inches are just approximation.
IC Plus Corp.
Headquarters
10F, No.47, Lane 2, Kwang-Fu Road, Sec. 2,
Hsin-Chu City, Taiwan 300, R.O.C.
TEL : 886-3-575-0275
FAX : 886-3-575-0475
Website: www.icplus.com.tw
Confidential.
Copyright © 2003, IC Plus Corp.
Sales Office
4F, No. 106, Hsin-Tai-Wu Road, Sec.1,
Hsi-Chih, Taipei Hsien, Taiwan 221, R.O.C.
TEL : 886-2-2696-1669
FAX : 886-2-2696-2220
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