Embedded Video Engine

Embedded Video Engine
Document No.: FT_000792
FT800 Embedded Video Engine Datasheet Draft 0.2
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Future Technology Devices
International Ltd.
FT800
(Embedded Video Engine)
The FT800 is an easy to use graphic
controller targeted for embedded
application to generate high-quality
graphics display. It has the following
features:
·
Target LCD display in WQVGA (480x272) and
QVGA (320x240) support DE (data enable)
mode and VSYNC/HSYNC mode
·
The FT800 calculates for 8-bit colour despite
only providing pins for 6-bit (RGB-6,6,6), this
improves the half tone appearance
·
·
Display Enabled control output to LCD panel
·
Mono audio channel output with PWM output
·
64 Voice Polyphonic Sound synthesizer
·
Audio wave playback for mono 8-bit Linear
PCM, 4-bit ADPCM and µ-Law coding format at
sampling frequency from 8kHz to 48kHz. Builtin digital filter can reduce the system design
complexity of external filter
·
PWM output backlight dimming control for LED
Embedded Video Engine (EVE) with widget
support can offload the system MPU and
provide a variety of graphic features
·
Built-in graphics operations allow user with
little expertise to create high-quality display
·
Integrated with 4-wire Touch-screen Controller
incorporating median filtering and touch force
sensing. Hardware engine to recognize touch
tags and track the touch movement. It
provides up to 255 touch tag notification
·
Standard serial interface to host MPU with SPI
up to 30MHz or I2C clock up to 3.4MHz
·
Low video power consumption for portable
application
·
Programmable Interrupt
interrupts to host MPU
·
No expensive frame buffer RAM required
·
Internal 12MHz oscillator within +/-5.6%
accuracy. Integrated Clock multiplier provide
48MHz or 36MHz system clock
·
Advanced, object oriented architecture enables
low cost MPU as system host using I2C and SPI
Interfaces
·
·
Clock switch command to switch internal or
external oscillator with 12MHz crystal, or
external 12MHz clock input for better clock
requirement
Power mode control allows chip to be put in
Power down, Sleep and Standby states
·
Supports host interface I/O voltage from 1.62V
to 3.63V
·
Internal voltage regulator supplies 1.2V to the
digital core
·
-40°C to 85°C extended operating temperature
range
·
Available in a compact Pb-free VQFN-48 7mm X
7mm X 0.9mm package (RoHS compliant)
·
·
Controller provides
Video RGB parallel output (default RGB data
width of 6-6-6) with 2 bits dithering.
Configurable to support resolution up to
512x512 and LCD R/G/B data width of 1 to 6
The FT800 has Programmable Timing to adjust
HSYNC and VSYNC timing enabling the control
of many different displays
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Disclaimer:
Neither the whole nor any part of the information contained in, or the product described in this manual, may be adapted or reproduced
in any material or electronic form without the prior written consent of the copyright holder. This product and its documentation are
supplied on an as-is basis and no warranty as to their suitability for any particular purpose is either made or implied. Future Technology
Devices International Ltd will not accept any claim for damages howsoever arising as a result of use or failure of this product. Your
statutory rights are not affected. This product or any variant of it is not intended for use in any medical appliance, device or system in
which the failure of the product might reasonably be expected to result in personal injury. This document provides preliminary
information that may be subject to change without notice. No freedom to use patents or other intellectual property rights is implied by
the publication of this document.
Future Technology Devices International Ltd
Unit 1, 2 Seaward Place
Centurion Business Park
Glasgow G41 1HH
United Kingdom
Scotland Registered Company Number: SC136640
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1
Typical Applications
·
Point of Sales Machines
·
Power meter
·
Multi-function Printers
·
Home appliance devices
·
Instrumentation
·
Set-top box
·
Home Security Systems
·
Thermostats
·
Graphic touch pad – remote, dial pad
·
Sprinkler system displays
·
Tele / Video Conference Systems
·
Medical Appliances
·
Phones and Switchboards
·
GPS / SatNav
·
Medical Appliances
·
Vending Machine Control Panels
·
Elevator Controls
•
Blood Pressure displays
•
Heart monitors
•
Glucose level displays
•
Breathalyzers
•
Gas chromatographs
1.1 Part Numbers
Part Number
Package
FT800Q-x
48 Pin VQFN
Table 1- Video Controller Part Numbers
Note: Packaging codes for x is:
-R: Taped and Reel, (VQFN is 3000 pieces per reel)
-T: Tray packing, (VQFN is 260 pieces per tray)
For example: FT800Q-R is 3000 VQFN pieces in taped and reel packaging
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2
FT800 Block Diagram
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Figure 2-1 FT800 Block Diagram
For a description of each function please refer to Section 4.
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Figure 2-2 FT800 System Design Diagram
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Contents
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Typical Applications.......................................................................... 3
1.1
Part Numbers ........................................................................................3
2
FT800 Block Diagram........................................................................ 4
3
Device Pin Out and Signal Description .............................................. 8
3.1
4
Pin Out – 48pin VQFP 7mm X 7mm X 0.9mm ..........................................8
Function Description ...................................................................... 13
4.1
Serial Host Interface ........................................................................... 13
4.1.1
SPI interface .............................................................................................................. 15
4.1.2
I2C interface .............................................................................................................. 15
4.1.3
Serial data protocol ..................................................................................................... 15
4.1.4
Host Memory Read ...................................................................................................... 15
4.1.5
Host Memory Write ..................................................................................................... 16
4.1.6
Host Command........................................................................................................... 16
4.2
System Control Unit (SCU) ................................................................... 17
4.2.1
System Clock ............................................................................................................. 17
4.2.2
Clock Source .............................................................................................................. 17
4.2.3
Phase Locked Loop clock multiplier ................................................................................ 19
4.3
Graphics Engine .................................................................................. 19
4.4
Parallel RGB Interface ......................................................................... 20
4.5
Miscellaneous Control .......................................................................... 21
4.5.1
Backlight Control Pin ................................................................................................... 21
4.5.2
DISP Control Pin ......................................................................................................... 21
4.5.3
General Purpose IO pins............................................................................................... 21
4.5.4
Pins Drive Current Control ............................................................................................ 21
4.6
Audio Engine ....................................................................................... 22
4.6.1
Sound Synthesizer ...................................................................................................... 22
4.6.2
Audio Playback ........................................................................................................... 24
4.7
Touch-screen Engine ........................................................................... 25
4.8
Interrupts ........................................................................................... 27
4.9
Power Management ............................................................................. 27
4.9.1
Power supply ............................................................................................................. 27
4.9.2
Internal Regulator ....................................................................................................... 28
4.9.3
Power Modes .............................................................................................................. 29
5
EVE Memory Map ............................................................................ 33
5.1
EVE Registers ...................................................................................... 33
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Devices Characteristics and Ratings ............................................... 38
6.1
Absolute Maximum Ratings.................................................................. 38
6.2
DC Characteristics ............................................................................... 39
6.3
Touch Sense Characteristics ................................................................ 41
6.4
AC Characteristics ............................................................................... 42
6.4.1
System clock.............................................................................................................. 42
6.4.2
Host Interface SPI Mode 0 ............................................................................................ 42
6.4.3
Host Interface I2C Mode Timing .................................................................................... 43
6.4.4
RGB Video Timing ....................................................................................................... 44
7
Application Examples ..................................................................... 46
7.1
8
9
Examples of LCD Interface connection ................................................. 46
Package Parameters ....................................................................... 47
8.1
VQFN-48 Package Dimensions ............................................................. 47
8.2
Solder Reflow Profile ........................................................................... 48
FTDI Chip Contact Information ....................................................... 49
Appendix A – References.............................................................................. 50
Appendix B - List of Figures and Tables ........................................................ 50
Appendix C - Revision History ...................................................................... 52
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Device Pin Out and Signal Description
3.1 Pin Out – 48pin VQFP 7mm X 7mm X 0.9mm
Figure 3-1 Pin Configuration VQFP48 (top view)
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Pin No.
Name
Type
1
AUDIO_L
O
2
GND
P
Description
Audio PWM out, push-pull output, 16mA sink/source
current.
Pad powered from pin VCC.
Ground
In SPI mode: SPI SCLK input.
3
SPI_CLK/
I2C_SCL
I
In I2C mode: SCL input, need external 1kΩ ~ 4.7kΩ pull
up to VCCIO.
Input pad with Schmitt trigger, 3.3V tolerant.
Pad powered from pin VCCIO.
In SPI mode: SPI MISO output.
4
MISO/
I2C_SDA
In I2C mode: SDA input/Open Drain Output, need
external1kΩ ~ 4.7kΩ pull up to VCCIO.
I/O
Input with Schmitt trigger, 3.3V tolerant, 4/8/12/16mA
sink/source current.
Pad powered from pin VCCIO.
In SPI mode: SPI MOSI input.
5
MOSI/
I2C_SA0
In I2C mode: Input, A0 select of I2C device address.
I
Input pad, 3.3V tolerant.
Pad powered from pin VCCIO.
In SPI mode: SPI CS_N input, active low.
6
CS_N/
I2C_SA1
In I2C mode: Input, A1 of I2C device address.
I
Input pad, 3.3V tolerant.
Pad powered from pin VCCIO.
In SPI mode: General purpose input, output port.
In I2C mode: Input, A2 of I2C device address.
7
GPIO0/
I2C_SA2
I/O
Push-pull, three-state output. 3.3V tolerant, 4/8/12/16mA
sink/source current.
Pad powered from pin VCCIO.
8
9
10
GPIO1
VCCIO
MODE
I/O
P
I
General purpose input, output port, push-pull, three-state
output. 3.3V tolerant, 4/8/12/16mA sink/source current.
Pad powered from pin VCCIO.
I/O power supply, connect a 0.1uF decoupling capacitor
1.8V, 2.5V or 3.3V.
Note VCCIO supply to IO PAD from pin 3 to 12 only.
Host interface SPI(pull low) or I2C(pull up) mode select
input, 3.3V tolerant
Pad powered from pin VCCIO.
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Pin No.
Name
Type
Description
11
INT_N
OD
Host Interrupt, open drain output active low, pull up to
VCCIO through a 1kΩ ~10kΩ resistor.
12
PD_N
I
Power down input, active low, 3.3V tolerant, pull up to
VCCIO through 47kΩ resistor and 100nF to ground.
Pad powered from pin VCCIO.
Crystal oscillator or clock input;
X1/
CLK
I
14
X2
O
Crystal oscillator output; leave open if an external clock is
applied on pin X1/CLKIN, pad power from VCC.
15
GND
P
Power ground.
16
VCC
P
3.3V power supply input.
17
VCC1V2
O
1.2V output pin. Connect a 3.3uF minimum decoupling
capacitor.
18
VCC
P
3.3V power supply input.
19
X+
AI/O
20
Y+
AI/O
21
X-
AI/O
22
Y-
AI/O
23
GND
P
13
3.3V peak input allowed.
Pad powered from pin VCC.
Drive X right electrode of 4-wire Touch-screen panel.
Pad powered from pin VCC.
Drive Y top electrode of 4-wire Touch-screen panel.
Pad powered from pin VCC.
Drive X left electrode of 4-wire Touch-screen panel
Drive Y bottom electrode of 4-wire Touch-screen panel.
24
25
26
BACKLIGHT
DE
VSYNC
O
O
O
Pad powered from pin VCC.
Ground
LED Backlight brightness PWM control signal, push-pull
output, 4/8mA sink/source current.
Pad powered from pin VCC.
LCD Data Enable, push-pull output, 4/8mA sink/source
current.
Pad powered from pin VCC.
LCD Vertical Sync, push-pull output, 4/8mA sink/source
current.
Pad powered from pin VCC.
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Pin No.
28
Name
DISP
Type
Description
O
General purpose output pin for LCD Display Enable, pushpull output, 4/8mA sink/source current. Control by writing
to Bit 7 of REG_GPIO register.
Pad powered from pin VCC.
29
30
31
32
33
34
PCLK
B7
B6
B5
B4
B3
O
O
O
O
O
O
35
B2
O
36
GND
P
37
38
39
G7
G6
G5
O
O
O
LCD Pixel Clock, push-pull output, 4/8mA sink/source
current.
Pad powered from pin VCC.
Bit 7 of Blue RGB signals, push-pull output, 4/8mA
sink/source current.
Pad powered from pin VCC.
Bit 6 of Blue RGB signals, push-pull output, 4/8mA
sink/source current.
Pad powered from pin VCC.
Bit 5 of Blue RGB signals, push-pull output, 4/8mA
sink/source current.
Pad powered from pin VCC.
Bit 4 of Blue RGB signals, push-pull output, 4/8mA
sink/source current.
Pad powered from pin VCC.
Bit 3 of Blue RGB signals, push-pull output, 4/8mA
sink/source current.
Pad powered from pin VCC.
Bit 2 of Blue RGB signals, push-pull output, 4/8mA
sink/source current.
Pad powered from pin VCC.
Ground
Bit 7 of Green RGB signals, push-pull output, 4/8mA
sink/source current.
Pad powered from pin VCC.
Bit 6 of Green RGB signals, push-pull output, 4/8mA
sink/source current.
Pad powered from pin VCC.
Bit 5 of Green RGB signals, push-pull output, 4/8mA
sink/source current.
Pad powered from pin VCC.
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Pin No.
Name
40
G4
41
G3
42
G2
43
R7
44
R6
45
R5
46
R4
47
R3
Type
O
O
O
O
O
O
O
O
48
R2
O
EP
GND
P
Description
Bit 4 of Green RGB signals, push-pull output, 4/8mA
sink/source current.
Pad powered from pin VCC.
Bit 3 of Green RGB signals, push-pull output, 4/8mA
sink/source current.
Pad powered from pin VCC.
Bit 2 of Green RGB signals, push-pull output, 4/8mA
sink/source current.
Pad powered from pin VCC.
Bit 7 of Red RGB signals, push-pull output, 4/8mA
sink/source current.
Pad powered from pin VCC.
Bit 6 of Red RGB signals, push-pull output, 4/8mA
sink/source current.
Pad powered from pin VCC.
Bit 5 of Red RGB signals, push-pull output, 4/8mA
sink/source current.
Pad powered from pin VCC.
Bit 4 of Red RGB signals, push-pull output, 4/8mA
sink/source current.
Pad powered from pin VCC.
Bit 3 of Red RGB signals, push-pull output, 4/8mA
sink/source current.
Pad powered from pin VCC.
Bit 2 of Red RGB signals, push-pull output, 4/8mA
sink/source current.
Pad powered from pin VCC.
Ground expose thermal pad.
Table 3-1 FT800Q pin description
Note:
P
: Power or ground
I
: Input
O
: Output
OD
: Open drain output
I/O
: Bi-direction Input and Output
AI/O
: Analog Input and Output
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4
Function Description
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The FT800 is a single chip video controller with the following features:
· Embedded Video Engine
· Audio Engine
· Touch-screen Engine
· Parallel RGB video interface.
· Standard Serial Host Interface, SPI or I2C.
· Crystal Oscillator
· System Control Unit (SCU)
· Power Management Unit (PMU)
· Power management
The functions for each block are briefly described in the following subsections.
4.1 Serial Host Interface
The FT800 uses standard serial interface to communicate with most types of microcontrollers
and microprocessors. The interface mode is configurable by pull down for SPI and pull up for
I2C. Figure 4-1 shows the two configuration modes connections.
Figure 4-1 Host Interface
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1.8-3.3V
4.7K
MPU
3.3V
Vio
4.7K
VCC
FT800
CS_N
CS_N
MISO
MISO
MOSI
MOSI
SCLK
SCLK
PD_N
PD_N
INT_N
INT_N
GND
GND
Figure 4-2 SPI Interface 1.8-3.3 V connection
3.3V
5V
74LCx125
Vio
MPU
GND
VCC
FT800
CS_N
CS_N
MISO
MISO
MOSI
MOSI
SCLK
SCLK
PD_N
PD_N
INT_N
INT_N
4.7K
3.3V
GND
4.7K
GND
Figure 4-3 SPI Interface 5 V connection with level shift
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4.1.1 SPI interface
The SPI operates at up to 30MHz, only SPI Mode 0 is supported; refer to Section 6.4.2 for a
detailed timing specification.
4.1.2 I2C interface
The I2C operate at up to 3.4MHz; refer to section 6.4.3 for detail timing specification. I2C
device address is configurable between 0x20 to 0x27 depend on the I2C_SA[2:0] pin setting.
4.1.3 Serial data protocol
The EVE appears to the host MPU as a memory-mapped SPI or I2C device. The host
communicates with the EVE using reads and writes to a large (4 megabyte) address space.
Within this address space are dedicated areas for graphics, audio and control. Refer to Section
5 for memory map in detail.
The host reads and writes the EVE address space using SPI or I2C transactions. These
transactions are read, write or command. Serial data is sent by the most significant bit first.
For I2C transactions, the same bytes sequence is encapsulated in the I2C protocol.
4.1.4 Host Memory Read
For SPI Read, the host sends two zero bits, followed by the 22-bit address. This is followed by
a dummy byte. After the dummy byte, the EVE responds to each host byte with read data
bytes.
7
6
0
0
5
4
3
2
1
0
Address [21:16]
Address [15:8]
Write
Address
Address [7:0]
Dummy
Byte 0
Read Data
Byte n
For I2C Read transaction, bytes are pack in the I2C protocol as follow:[start] <DEVICE ADDRESS + write bit>
<00b+Address[21:16]>
<Address[15:8]>
<Address[7:0]>
[restart] <DEVICE ADDRESS + read bit>
<Read data byte 0>
....
<Read data byte n>[stop]
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4.1.5 Host Memory Write
For SPI Writes, the host sends a one bit and 0 bit, followed by the 22-bit address. This is
followed by the write data.
7
6
1
0
5
4
3
2
1
0
Address [21:16]
Write
Address
Address [15:8]
Address [7:0]
Byte 0
Write Data
Byte n
For I2C Write transaction, bytes are pack in the I2C protocol as follow:[start] <DEVICE ADDRESS + write bit>
<10b,Address[21:16]>
<Address[15:8]>
<Address[7:0]>
<Write data byte 0>
....
<Write data byte n>[stop]
4.1.6 Host Command
When sending a command the host transmits a 2 byte command. Table 4-1 lists the host
command functions; only the first ‘1’ bytes are used, the second bytes are dummy and
subsequent data is ignored.
NOTE: ACTIVE command is generated by dummy read from address 0.
7
6
0
1
0
0
5
4
3
2
1
0
0
0
Command [5:0]
0
0
0
0
For I2C Command transaction, bytes are packed in the I2C protocol as follows:
[start] <DEVICE ADDRESS + write bit>
<01b,Command[5:0]>
<dummy byte>[stop]
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Table 4-1 Host Command Table
1st Byte
2nd byte
3rd byte
Command
Description
00000000b
00000000b
00000000b
00h
ACTIVE
Switch from Standby/Sleep modes to
active mode. Dummy read from address
0 generate ACTIVE command.
01000001b
00000000b
NA
41h
STANDBY
01000010b
00000000b
NA
01010000b
00000000b
NA
Power Modes
42h
SLEEP
50h
PWRDOWN
Put EVE core to standby mode. Clock
gate off, PLL and Oscillator remain on
(default).
Put EVE core to sleep mode. Clock gate
off, PLL and Oscillator off.
Switch off 1.2V internal regulator. Clock
gate off, PLL and Oscillator off.
Clock Switching
01001000b
00000000b
NA
01000100b
00000000b
NA
01100010b
00000000b
NA
01100001b
00000000b
NA
01100100b
00000000b
NA
01101000b
00000000b
NA
0111XXXXb
00000000b
NA
48h
CLKINT
44h
CLKEXT
62h
CLK48M
61h
CLK36M
64h
CLK24M
Test Mode
68h
CORERST
7Xh
Reserved
Select PLL input from Internal relaxation
oscillator (default).
Select PLL input from Crystal oscillator
or external input clock.
Switch PLL output clock to 48MHz
(default).
Switch PLL output clock to 36MHz.
For Internal tests.
Send reset pulse to EVE core.
Reserved debug command do not used.
4.2 System Control Unit (SCU)
4.2.1 System Clock
The FT800 internal relaxation 12MHz oscillator is trimmed to within ±3%. On power-up the
internal oscillator clock source is selected by default. The crystal oscillator can be used to
connect an external crystal between X1 and X2, or connect to an input clock.
4.2.2 Clock Source
Switching to external crystal oscillator can be done when the FT800 is in active state by writing
command "CLKEXT". Command CLKEXT and CLKINT switched between internal oscillator and
external crystal oscillator are sync to VSYNC on the fly.
The crystal oscillator is recommended for applications which required good audio reproduction
quality.
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Figure 4-4 Use Internal Oscillator Only
Figure 4-5 Crystal Oscillator connection
Figure 4-6 External Clock Input
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4.2.3 Phase Locked Loop clock multiplier
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The internal PLL supports 12MHz inputs, which can be a crystal oscillator or an external clock.
The PLL outputs a default frequency of 48MHz and may be switched to 36MHz by SCU
command CLK48M and CLK36M.
4.3 Graphics Engine
The graphics engine executes the display list once every horizontal line; it executes the
primitive objects in the display list and constructs the display line buffer. The horizontal pixel
content in the line buffer is updated if the object is visible at the horizontal line.
Main features of the graphics engine are:
·
·
·
·
·
·
·
The primitive objects supported by the graphics processor are: Lines, Points,
rectangles, bitmaps (comprehensive set of formats), text display, textVGA display,
plotting bar graph, edge strips, line stipple etc
Operations such as stencil test, alpha blend and masking are useful for creating a rich
set of effects such as shadows, transitions, reveals, fades and wipes.
Anti aliasing of the primitive objects (except bitmaps) gives smooth effect to the
viewer.
Bitmap transform enables operations such as translate, scale and rotate.
Display pixels are plotted with 1/16th pixel precision.
Four levels of graphics state.
Tag buffer detection.
The graphics engine also supports customized build-in widgets and various functionalities such
as jpeg decode, screen saver, calibration etc. The graphics engine interprets commands from
MPU host via a 4 Kbyte FIFO in FT800 memory at RAM_CMD. The MPU writes commands into
the FIFO, and the graphics engine reads and executes the commands. The MPU updates
register REG_CMD_WRITE to indicate that there are new commands in the FIFO, and the
graphics engine updates REG_CMD_READ after commands have been executed.
Main features supported are:
·
·
·
·
·
·
Drawing of widgets such as buttons, clock, keys, gauge, text display, progress bar,
slider, toggle, dial, gradient etc.
Jpeg decode (Only baseline is supported).
Inflate functionality (zlib inflate is supported).
Timed interrupt (generate an interrupt to host processor after few milliseconds)
In built animated functionalities such as displaying logo, calibration, spinner, screen
saver and sketch.
Feature to take a snapshot of the current graphics display.
For a complete list of graphics engine commands kindly refer to FT800 Programmer Guide
[FT800_Programmer_Guide – Document FT_000793]
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4.4 Parallel RGB Interface
The RGB parallel interface consist 23 signals - DISP, PCLK, VSYNC, HSYNC, DE, 6 each for R, G
and B. This interface can be connected directly to more LCD display panel.
Several registers configure the LCD operation of these signals as follow:REG_PCLK is the PCLK divisor the default is 0, and disable the PCLK output.
PCLK frequency = System Clock frequency / REG_PCLK
PCLK_POL define the clock polarity, =0 for positive active clock edge, and 1 for negative clock
edge.
REG_CSPREAD control the transition of RGB signals with respect to PCLK active clock edge,
when REG_CSPREAD=0, R[7:2],G[7:2] and B[7:2] signal changes following the active edge of
PCLK. When REG_CSPREAD=1, R[7:2] change a PCLK clock early and B[7:2] a PCLK clock
later, will help reduce the switching noise.
REG_DITHER enables colour dither; the default is enabled. This option improves the half-tone
appearance on displays. Internally, the graphic engine computes the colour values at an 8 bit
precision; however, the LCD colour at a lower precision is sufficient. The FT800 output is only 6
bits per colour in 6:6:6 formats and a 2X2 dither matrix allow the truncated bits to contribute
to the final colour values.
REG_OUTBITS’ default is 6, 6, 6 bits for each RGB colour. A dither exponent registers scales at
above dither values appropriate to support n bits’ display, allowing dithering on lower precision
LCD displays.
REG_SWIZZLE controls the arrangement of the output colour pins, to help the PCB route
different LCD panel arrangements. Bit 0 of the register causes the order of bits in each colour
channel to be reversed. Bits 1-3 control the RGB order. Bit 1 set causes R and B channels to be
swapped while Bit 3’s rotation may be enabled. If Bit 3 is set, then (R,G,B) is rotated right if
bit 2 is one, or left if bit 2 is zero.
Table 4-2 REG_SWIZZLE RGB Pins Mapping
REG_SWIZZLE
b3 b2 b1 b0
0
0
0
0
1
1
1
1
1
1
1
1
X
X
X
X
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
0
1
0
1
R7, R6, R5,
R4, R3, R2
R[7:2]
R[2:7]
B[7:2]
B[2:7]
G[7:2]
G[2:7]
G[7:2]
G[2:7]
B[7:2]
B[2:7]
R[7:2]
R[2:7]
PINS
G7, G6, G5,
G4, G3, G2
G[7:2]
G[2:7]
G[7:2]
G[2:7]
B[7:2]
B[2:7]
R[7:2]
R[2:7]
R[7:2]
R[2:7]
B[7:2]
B[2:7]
B7, B6, B5, B4,
B3, B2
B[7:2]
B[2:7]
R[7:2]
R[2:7]
R[7:2]
R[2:7]
B[7:2]
B[2:7]
G[7:2]
G[2:7]
G[7:2]
G[2:7]
Power on Default
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4.5 Miscellaneous Control
4.5.1 Backlight Control Pin
The backlight control pin is a pulse width modulated signal controlled by two registers:
REG_PWM_HZ and REG_PWM_DUTY. REG_PWM_HZ specifies the PWM output frequency, the
range is 250-10000 Hz. REG_PWM_DUTY specifies the duty cycle; the range is 0-128. A value
of 0 means that the PWM is completely off and 128 means completely on.
4.5.2 DISP Control Pin
The DISP pin is a general purpose output use to enable or as a reset control to LCD display panel. The pin
is control by writing to Bit 7 of REG_GPIO register.
4.5.3 General Purpose IO pins
The GPIO1 and GPIO0 pins are default input. Write '1' to Bit 1 and 0 of REG_GPIO_DIR to change to
output pins respectively. In I2C mode the GPIO0 is used as SA2 and is not available as GPIO.
GPIO1 and GPIO0 are read from or write to Bit 1 and 0 of REG_GPIO register. GPIO1 is recommended to
be used as shutdown control for audio power amplifier.
4.5.4 Pins Drive Current Control
The output drive current of output pins can be change as follow by writing to Bit[6:2] of REG_GPIO
register:-
REG_GPIO
Bit[6:5]
Bit[4]
Bit[3:2]
Value
00b#
01b
10b
11b
0b#
1b
00b#
01b
10b
11b
Drive
Current
4mA
8mA
12mA
16mA
4mA
8mA
4mA
8mA
12mA
16mA
Pins
GPIO1
PCLK
MISO
GPIO0
DISP
INT_N
VSYNC
HSYNC
DE
R7..R2
G7..G2
B7..B2
BACKLIGHT
Note: #Default value
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4.6 Audio Engine
FT800 provides mono audio output through a PWM output pin, AUDIO_L. It outputs the two
audio sources, the sound synthesizer and audio file playback.
4.6.1 Sound Synthesizer
A sound processor, AUDIO ENGINE, generates the sound effects from a small ROM library of
waves table. To play a sound effect listed in Table 4.3, load the REG_SOUND register with a
code value and write 1 to the REG_PLAY register. The REG_PLAY register reads 1 while the
effect is playing and returns a ‘0’ when the effects end. Some sound effects play continuously
until it is interrupted or commanded to play the next sound effect. To interrupt an effect, write
a new value to REG_SOUND and REG_PLAY registers; e.g. write 0 (Silence) to REG_SOUND
and 1 to PEG_PLAY to stop the sound effect.
The sound volume is controlled by register REG_VOL_SOUND. The 16-bit REG_SOUND register
takes an 8-bit sound in the low byte. For some sounds, marked "pitch adjust" in the table
below, the high 8 bits contain a MIDI note value. For these sounds, note value of zero
indicates middle C. For other sounds the high byte of REG_SOUND is ignored.
Table 4-3 Sound Effect
Value Pitch adjust
Effect
00h
N
Silence
01h
Y
square wave
02h
Y
sine wave
03h
Y
sawtooth wave
04h
Y
triangle wave
05h
Y
Beeping
06h
Y
Alarm
07h
Y
Warble
08h
Y
Carousel
10h
Y
1 short pip
11h
Y
2 short pips
12h
Y
3 short pips
13h
Y
4 short pips
Value
0x32h
0x33h
0x34h
0x35h
0x36h
0x37h
0x38h
0x39h
0x40h
0x41h
0x42h
0x43h
0x44h
Pitch adjust
N
N
N
N
N
N
N
N
Y
Y
Y
Y
Y
Effect
DTMF 2
DTMF 3
DTMF 4
DTMF 5
DTMF 6
DTMF 7
DTMF 8
DTMF 9
harp
xylophone
tuba
glockenspiel
organ
14h
Y
5 short pips
0x45h
Y
trumpet
15h
16h
17h
18h
19h
1Ah
1Bh
1Ch
1Dh
1Eh
1Fh
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
6 short pips
7 short pips
8 short pips
9 short pips
10 short pips
11 short pips
12 short pips
13 short pips
14 short pips
15 short pips
16 short pips
0x46h
0x47h
0x48h
0x49h
0x50h
0x51h
0x52h
0x53h
0x54h
0x55h
0x56h
piano
chimes
music box
bell
click
switch
cowbell
notch
hihat
kickdrum
pop
23h
2Cah
30h
31h
N
N
N
N
DTMF
DTMF
DTMF
DTMF
0x57h
58h
60h
61h
Y
Y
Y
Y
N
N
N
N
N
N
N
N
#
*
0
1
N
N
N
clack
chack
mute
unmute
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Table 4-4 MIDI
MIDI ANSI
note note
21
A0
22
A#0
23
B0
24
C1
25
C#1
26
D1
27
D#1
28
E1
29
F1
30
F#1
31
G1
32
G#1
33
A1
34
A#1
35
B1
36
C2
37
C#2
38
D2
39
D#2
40
E2
41
F2
42
F#2
43
G2
44
G#2
45
A2
46
A#2
47
B2
48
C3
49
C#3
50
D3
51
D#3
52
E3
53
F3
54
F#3
55
G3
56
G#3
57
A3
58
A#3
59
B3
60
C4
61
C#4
62
D4
63
D#4
64
E4
Note Effect
Freq
(Hz)
27.5
29.1
30.9
32.7
34.6
36.7
38.9
41.2
43.7
46.2
49.0
51.9
55.0
58.3
61.7
65.4
69.3
73.4
77.8
82.4
87.3
92.5
98.0
103.8
110.0
116.5
123.5
130.8
138.6
146.8
155.6
164.8
174.6
185.0
196.0
207.7
220.0
233.1
246.9
261.6
277.2
293.7
311.1
329.6
MIDI
note
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
101
102
103
104
105
106
107
108
ANSI
note
F4
F#4
G4
G#4
A4
A#4
B4
C5
C#5
D5
D#5
E5
F5
F#5
G5
G#5
A5
A#5
B5
C6
C#6
D6
D#6
E6
F6
F#6
G6
G#6
A6
A#6
B6
C7
C#7
D7
D#7
E7
F7
F#7
G7
G#7
A7
A#7
B7
C8
Freq (Hz)
349.2
370.0
392.0
415.3
440.0
466.2
493.9
523.3
554.4
587.3
622.3
659.3
698.5
740.0
784.0
830.6
880.0
932.3
987.8
1046.5
1108.7
1174.7
1244.5
1318.5
1396.9
1480.0
1568.0
1661.2
1760.0
1864.7
1975.5
2093.0
2217.5
2349.3
2489.0
2637.0
2793.8
2960.0
3136.0
3322.4
3520.0
3729.3
3951.1
4186.0
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4.6.2 Audio Playback
The EVE can play back recorded sound through its audio output. To do this, you load the
original sound data into part of the EVE's RAM, and set registers to start the playback.
The registers controlling audio playback are:
REG_PLAYBACK_START:
the start address of the audio data
REG_PLAYBACK_LENGTH:
the length of the audio data, in bytes
REG_PLAYBACK_FREQ:
the playback frequency, in Hz
REG_PLAYBACK_FORMAT:
the playback format, one of LINEAR SAMPLES, ULAW
SAMPLES, or ADPCM SAMPLES
REG_PLAYBACK_LOOP:
if zero, sample is played once. If one, sample is repeated
indefinitely
REG_PLAYBACK_PLAY:
a write to this location triggers the start of audio playback
REG_VOL_PB:
playback volume, 0-255
The mono audio format supported is 8-bits PCM, 8-bits ULAW and 4-bits IMA-ADPCM. For
ADPCM_SAMPLES, each sample is 4 bits, so two samples are packed per byte, first sample is in
bits 0-3 and the second is in bits 4-7.
The current
audio playback read pointer can be queried by reading the
REG_PLAYBACK_READPTR. Using a large sample buffer, looping, and this read pointer, the
host MPU can supply a continuous stream of audio.
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4.7 Touch-screen Engine
The touch-screen consists of Touch screen engine, ADC, Axis-switches, and ADC input
multiplexer. The Touch screen engine reads commands from the memory map register and
generates the required control signals to the axis-switches and inputs mux and ADC. The ADC
data are acquired and processed and update in the respective register for the MPU to read.
Y+
FT800
X+
Y+
XY-
X-
LCD Touch Screen
X+
Y-
Figure 4-7 Touch screen Block Diagram
The host control the TOUCH SCREEN ENGINE operation mode by writing the
REG_TOUCH_MODE.
Table 4-5 Touch Controller Operating Mode
REG_TOUCH_MODE
Mode
Description
0
OFF
Acquisition stopped, only touch detection interrupt is still valid.
1
ONE-SHOT
Perform acquisition once every time MPU write '1' to
REG_TOUCH_MODE.
2
FRAME-SYNC
Perform acquisition for every frame sync (~60 data
acquisition/second.
3
CONTINUOUS
Perform acquisition continuously at approximately 1000 data
acquisition / second.
The Touch Screen Engine capture the raw X and Y coordinate and write to register
REG_TOUCH_RAW XY. The range of these values is 0-1023. If the touch screen is not being
pressed, both registers read 0xffff (65535).
These touch values are transformed into screen coordinates using the matrix in registers
REG_TOUCH_TRANSFORM_A-F. The post-transform coordinates are available in register REG
TOUCH SCREEN XY. If the touch screen is not being pressed, both registers read 0x8000 (32768). The values for REG TOUCH TRANSFORM A-F may be computed using an on-screen
calibration process.
If the screen is being touched, the screen coordinates are looked up in the screen's tag buffer,
delivering a final 8-bit tag value, in REG TOUCH TAG. Because the tag lookup takes a full
frame, and touch coordinates change continuously, the original (x; y) used for the tag lookup
is also available in REG TOUCH TAG XY.
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Screen touch pressure is available in REG_TOUCH_RZ. The value is relative to the resistance of
the touch contact, a lower value indicates more pressure. The register defaults to 32767 when
touch is not detected. The REG_TOUCH_THRESHOLD can be set to accept a touch only when
the force threshold is exceeded.
Refer to FT_000792.pdf Section 5 Programming Model for more details.
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4.8 Interrupts
The interrupt system is enabled by REG_INT_EN. When REG_INT_EN is 0, INTN is high. When
REG_INT_EN is 1, INTN is low when any of the interrupt flags in REG_INT_FLAGS is high, after
masking with REG_INT_MASK. Each bit in REG_INT_FLAGS is set by a corresponding interrupt
source. REG INT FLAGS is readable by the host at any time, and clears when read.
Table 4-6. Interrupt Flags bit assignment
Bit
7
6
5
4
Int Source
CONVCOMPLETE
CMDFLAG
CMDEMPTY
PLAYBACK
Conditions
Touch-screen
conversions
completed
Command FIFO
flag
Command FIFO
empty
Audio playback
ended
Bit
3
2
1
0
Int Source
SOUND
TAG
TOUCH
SWAP
Conditions
Sound effect
ended
Touch-screen tag
value change
Touch-screen
touch detected
Display list swap
occurred
4.9 Power Management
4.9.1 Power supply
The FT800 may be operated with a single supply of 3.3V apply to VCC and VCCIO pins. For
operation with host MPU at lower supply, connect the VCCIO to MPU power to match the
interface power. To ensure proper operation, the VCCIO should be powered at the same time
or after the VCC is powered.
Table 4-7 Power supply
Symbol
Typical
Description
VCCIO
1.8V, or 2.5V, or 3.3V
Supply for Host interface digital I/O
pad only, LCD RGB interface supply
from VCC.
VCC
3.3V
Supply for chip
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4.9.2 Internal Regulator
The 1.2V internal regulator provides power to the core circuit. The regulator is disabled when
device is in POWER DOWN state. Power down is activated by the SCU command write or by
holding down the PD_N pin for at least 5mS to allow the 1.2V Decoupling Capacitor to
discharge fully. The regulator is enabled only by releasing the PD_N pin. A 47k-ohm resistor is
recommended to pull the PD_N pin up to VCCIO; together with a 100nF capacitor to ground in
order to delay the 1.2V regulator powering up after the VCC is stable.
The regulator requires a compensation capacitor to be stable. To ensure sufficient phase
margins, a 4.7uF capacitor with ESR >0.5Ω is required between VCC1V2 to GND pins. Do not
connect any load to this pin.
VCCIO
VCC
1.2V
VCC
R
VCC1V2
Cin
Ccomp
4.7uF
10uF
GND
GND
GND
PD_N
GND
C
100nF
GND
Figure 4-8 1.2V regulator
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4.9.3 Power Modes
When supply to VCCIO and VCC is applied, internal 1.2V regulator is powered by VCC. An
internal POR pulse will be generated during the regulator power up until it is stable. After the
initial power up, the FT800 will stay in standby state until host command as stated below.
Table 4-8 State Flow Table
Next power state
POWERDOWN
STANDBY
SLEEP
ACTIVE
--
Toggle PD_N from
low to high
--
--
Toggle PD_N from high to
low
--
--
Dummy
Read 0
Toggle PD_N from high to
low
--
--
Dummy
Read 0
· Toggle PD_N from
high to low or Write
Command
”POWERDOWN”
Write Command
Write Command
--
”STANDBY”
”SLEEP”
Current power state
POWERDOWN
STANDBY
SLEEP
ACTIVE
Toggle PDN from high
to low
VCC/Vio
power ON
Toggle PDN from low
to high
POWERDOWN
STANDBY
Dummy Read “0”
Toggle PDN from high to low or
Write command “POWERDOWN”
Toggle PDN from high
to low
Write command “STANDBY”
Dummy Read “0”
SLEEP
ACTIVE
Write command “SLEEP”
Figure 4-9 Power State Transition
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4.9.3.1 Active state
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In Active state, the FT800 is in normal operation.
4.9.3.2 Standby state
In Standby state, the crystal oscillator and PLL remain functioning; the system clock
applied to the EVE core is disabled but register contents are retained.
4.9.3.3 Sleep state
In Sleep state, the crystal oscillator, PLL and system clock applied to the EVE core are
disabled; all register contents are retained.
4.9.3.4 Power down state
In Power down state, the internal 1.2V regulator supplying the core digital logic, the
crystal oscillator, the PLL and the system clock applied to the EVE core is disabled. All
register contents are lost and reset to default when the system is next switched on.
4.9.3.5 Wake up to Active from other power states
Wake up from power down state requires the host to pull the PD_N pin down and
release, a low to high transition enables the 1.2V regulator. Power on reset generated
when 1.2V is stable and switched to standby mode.
From standby or sleep states, host MPU reads at address 0 to wake the FT800 into a
normal operation state.
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4.9.3.6 Pin status at different power states
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The FT800 pin status depends on the power state of the chip. See the following table
for more details. At power transition from Active to Standby, Active to Sleep, all pins
retain their previous statuses. The software needs to set Audio L, Backlight, DCLK to a
known state before issuing power transition commands.
Reset States
Reset States
(VCC3.3 /
VCCIO ON)
(VCC3.3 / VCCIO ON)
Default Output Drive
Strength
AUDIO_L
Tristate Output
(hi-Z)
16mA
HOST_IO_
CLK
Input (floating)
MISO/I2C
_DAT
Tristate Output
(hi-Z)
MISO/I2C
_ADDR0
Pin Name
Active
(VCC3.3 /
VCCIO ON)
Powerdown
Mode (VCC3.3
ON / VCC1.2
OFF)
Output
Retain previous
state
Hybrid Mode
(VCC3.3 OFF /
VCCIO ON)
Input
Input (floating)
Input/Output
Tristate Output
(hi-Z)
Input (floating)
Input
Input (floating)
CS_N/I2C
_ADDR1
Input (floating)
Input
Input (floating)
GPIO0/I2C
_ADDRR2
Input (floating)
Input/Output
Tristate Output
(hi-Z)
GPIO1
Tristate Output
(hi-Z)
Input/Output
Tristate Output
(hi-Z)
SPI_MODE
_N
Input (pullup)
Input (pullup)
Input (pullup)
MODE
Input
Input
Input (floating)
INT_N
Open Drain
Output (hi-Z)
Open Drain
Output
Tristate Output
(hi-Z)
PD_N
Input
Input
Input (floating)
X1/CLK
Input (floating)
Crystal
Oscillator
Input CLK
Input
X2
Output (hi-Z)
Crystal
Oscillator
Output
4mA
4mA
4mA
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Reset States
(VCC3.3 /
VCCIO ON)
Default Output
Drive Strength
Active (VCC3.3
/ VCCIO ON)
Powerdown
Mode (VCC3.3
ON / VCC1.2
OFF)
Pin Name
Reset States
(VCC3.3 /
VCCIO ON)
X+
Tristate Output
(hi-Z)
Input/Output
Retain Previous
State
Y+
Tristate Output
(hi-Z)
Input/Output
Retain Previous
State
X-
Tristate Output
(hi-Z)
Input/Output
Retain Previous
State
Y-
Tristate Output
(hi-Z)
Input/Output
Retain Previous
State
BACKLIGHT
Output
4mA
Output
Retain Previous
State
DE
Output
4mA
Output
Output Low
VSYNC
Output
4mA
Output
Output Low
HSYNC
Output
4mA
Output
Output Low
DISP
Output
4mA
Output
Output Low
DCLK
Output
4mA
Output
Output Low
R(7:0), G(7:0),
B(7:0)
Output
4mA
Output
Output Low
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Hybrid Mode
(VCC3.3 OFF /
VCCIO ON)
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EVE Memory Map
All memory and registers in the EVE core is memory map in 22-bits address space with 2-bits
SPI command prefix. Prefix 0'b00 for read and 0'b10 for write to the address space, 0'b01
reserved for Host Commands and 0'b11 undefined. The following are the memory space
defined.
Table 5-1 EVE Memory Map
Start
Address
End
Address
Size
NAME
Description
00 0000h
02 FFFFh
256kB
RAM_G
Main graphics RAM
10 0000h
10 1FFFh
8kB
RAM_DL
Display List 2 x ram_2k_32 (Swap buffer)
10 2000h
10 23FFh
1kB
RAM_PAL
Palette 1 x 256_32_r_rw
REG_*
Register
RAM_EVERAM
EVE scratchpad 1 x ram_2k_32
Reserved
Reserved, do not modify.
10 2400h
10 9000h
10 AFFFh
18 0000 h
3F FFFF h
8kB
5.1 EVE Registers
Table 5.1 shows the definitions of the EVE core Registers. Refer to EVE Reference document
"FT_000792.pdf" Section 5 Programming Model for details.
Table 5-2 Overview of EVE Registers
Address
Register
Bits
Access
Reset value
Description
102400h
REG_ID
8
r/o
7Ch
Identification register, always reads as
0x7c
102404h
REG_FRAMES
32
r/o
00000000h
Frame counter, since reset
102408h
REG_CLOCK
32
r/o
00000000h
Clock cycles, since reset
10240Ch
REG_FREQUENCY
27
r/w
02DC6C00
h
Main clock frequency
102410h
REG_RENDERMODE
1
r/w
0
Rendering mode: 0 = normal, 1 =
single-line
102414h
REG_SNAPY
9
r/w
0
Scan line select for RENDERMODE 1
102418h
REG_SNAPSHOT
1
r/o
-
trigger for RENDERMODE 1
10241Ch
REG_CPURESET
1
r/w
0
Coprocessor reset control
102420h
REG_TAP_CRC
32
r/o
-
Live video tap crc
102424h
REG_TAP_MASK
32
r/w
FFFFFFFFh
Live video tap mask
102428h
REG_HCYCLE
10
r/w
224h
Horizontal total cycle count
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Document No.: FT_000792
FT800 Embedded Video Engine Datasheet Draft 0.2
Clearance No.: FTDI# XXX
Address
Register
Bits
Access
Reset value
Description
10242Ch
REG_HOFFSET
10
r/w
02Bh
Horizontal display start offset
102430h
REG_HSIZE
10
r/w
1E0h
Horizontal display pixel count
102434h
REG_HSYNC0
10
r/w
000h
Horizontal sync fall offset
102438h
REG_HSYNC1
10
r/w
029h
Horizontal sync rise offset
10243Ch
REG_VCYCLE
10
r/w
124h
Vertical total cycle count
102440h
REG_VOFFSET
10
r/w
00Ch
Vertical display start offset
102444h
REG_VSIZE
10
r/w
110h
Vertical display line count
102448h
REG_VSYNC0
10
r/w
000h
Vertical sync fall offset
10244Ch
REG_VSYNC1
10
r/w
00Ah
Vertical sync rise offset
102450h
REG_DLSWAP
2
r/o
-
Display list swap control
102454h
REG_ROTATE
1
r/w
0
Screen 180 degree rotate
102458h
REG_OUTBITS
9
r/w
1B6h
Output bit resolution, 3x3x3 bits
10245Ch
REG_DITHER
1
r/w
1
Output dither enable
102460h
REG_SWIZZLE
4
r/w
0
Output RGB signal swizzle
102464h
REG_CSPREAD
1
r/w
1
Output clock spreading enable
102468h
REG_PCLK_POL
1
r/w
0
PCLK polarity, 0 = clock on rising, 1
=falling
10246Ch
REG_PCLK
8
r/w
00h
PCLK frequency divider, 0 = disable
102470h
REG_TAG_X
9
r/w
000h
Tag query X coordinate
102474h
REG_TAG_Y
9
r/w
000h
Tag query Y coordinate
102478h
REG_TAG
8
r/o
-
Tag query result
10247Ch
REG_VOL_PB
8
r/w
FFh
Volume for playback
102480h
REG_VOL_SOUND
8
r/w
FFh
Volume for synth sound
102484h
REG_SOUND
16
r/w
0000h
Sound effect select
102488h
REG_PLAY
1
r/w
-
Start effect playback
10248Ch
REG_GPIO_DIR
8
r/w
80h
GPIO pin direction, 1 = output
102490h
REG_GPIO
8
r/w
00h
GPIO read/write
102494h
REG_EVE_INT
2
r/o
-
Private: EVE interrupt strobe
Copyright © 2013 Future Technology Devices International Limited
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Document No.: FT_000792
FT800 Embedded Video Engine Datasheet Draft 0.2
Clearance No.: FTDI# XXX
Address
Register
Bits
Access
Reset value
Description
102498h
REG_INT_FLAGS
8
r/o
-
Interrupt flags
10249Ch
REG_INT_EN
1
r/w
0
Global interrupt enable
1024A0h
REG_INT_MASK
8
r/w
FFh
Interrupt enable mask
1024A4h
REG_PLAYBACK_STAR
T
20
r/w
00000h
Audio playback RAM start address
1024A8h
REG_PLAYBACK_LENG
TH
20
r/w
00000h
Audio playback sample length (bytes)
1024ACh
REG_PLAYBACK_READ
PTR
20
r/o
-
Audio playback current read pointer
1024B0h
REG_PLAYBACK_FREQ
16
r/w
1F40h
Audio playback frequency (Hz)
1024B4h
REG_PLAYBACK_FOR
MAT
2
r/w
0
Audio playback format
1024B8h
REG_PLAYBACK_LOOP
1
r/w
0
Audio playback loop enable
1024BCh
REG_PLAYBACK_PLAY
1
r/o
-
Start audio playback
1024C0h
REG_PWM_HZ
14
r/w
00FAh
PWM output frequency (Hz)
1024C4h
REG_PWM_DUTY
8
r/w
80h
PWM output duty cycle 0=0%,
128=100%
1024C8h
REG_MACRO_0
32
r/w
00000000h
Display list macro command 0
1024CCh
REG_MACRO_1
32
r/w
00000000h
Display list macro command 1
1024D0h
REG_CYA0
32
r/w
00000000h
Private: see src/pipeline
1024D4h
REG_CYA1
32
r/w
00000000h
Private: see src/pipeline
1024D8h
REG_BUSYBITS
64
r/o
-
Private: see src/pipeline
1024E0h
REG_ROMSUB_SEL
2
r/w
0
Private: ROM substitute RAM, 0=off,
1=TOUCH SCREEN ENGINE, 2=AUDIO
ENGINE, 3=EVE ENGINE,
1024E4h
REG_CMD_READ
12
r/w
000h
Command buffer read pointer
1024E8h
REG_CMD_WRITE
12
r/o
-
Command buffer write pointer
1024ECh
REG_CMD_DL
13
r/w
0000h
Command DL offset
1024F0h
REG_TOUCH_MODE
2
r/w
3
Touch-screen sampling mode
Copyright © 2013 Future Technology Devices International Limited
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Document No.: FT_000792
FT800 Embedded Video Engine Datasheet Draft 0.2
Clearance No.: FTDI# XXX
Address
Register
Bits
Access
Reset value
Description
1024F4h
REG_TOUCH_ADC_MO
DE
1
r/w
1
Select single ended (low power) or
differential (accurate) sampling
1024F8h
REG_TOUCH_CHARGE
16
r/w
1770h
Touch-screen charge time, units of 6
clocks
1024FCh
REG_TOUCH_SETTLE
4
r/w
3
Touch-screen settle time, units of 6
clocks
102500h
REG_TOUCH_OVERSA
MPLE
4
r/w
7
Touch-screen oversample factor
102504h
REG_TOUCH_RZTHRE
SH
16
r/w
FFFFh
Touch-screen resistance threshold
102508h
REG_TOUCH_RAW_XY
32
r/o
-
Touch-screen raw (x; y) (16, 16)
10250Ch
REG_TOUCH_RZ
16
r/o
-
Touch-screen resistance
102510h
REG_TOUCH_SCREEN
_XY
32
r/o
-
Touch-screen screen (x; y) (16, 16)
102514h
REG_TOUCH_TAG_XY
32
r/o
-
Touch-screen screen (x; y) used for
tag lookup
102518h
REG_TOUCH_TAG
8
r/o
-
Touch-screen tag result
10251Ch
REG_TOUCH_TRANSF
ORM_A
32
r/w
10000h
Touch-screen transform coefficient
(s15.16)
102520h
REG_TOUCH_TRANSF
ORM_B
32
r/w
00000000h
Touch-screen transform coefficient
(s15.16)
102524h
REG_TOUCH_TRANSF
ORM_C
32
r/w
00000000h
Touch-screen transform coefficient
(s15.16)
102528h
REG_TOUCH_TRANSF
ORM_D
32
r/w
00000000h
Touch-screen transform coefficient
(s15.16)
10252Ch
REG_TOUCH_TRANSF
ORM_E
32
r/w
10000h
Touch-screen transform coefficient
(s15.16)
102530h
REG_TOUCH_TRANSF
ORM_F
32
r/w
00000000h
Touch-screen transform coefficient
(s15.16)
102534h
RESERVED
16
r/w
1
RESERVED
102538h
RESERVED
16
r/o
-
RESERVED
10253Ch
REG_DATESTAMP
128
r/o
"2012-1011 1.9.0"
Date-stamp and revision
Copyright © 2013 Future Technology Devices International Limited
36
Document No.: FT_000792
FT800 Embedded Video Engine Datasheet Draft 0.2
Clearance No.: FTDI# XXX
Address
Register
Bits
Access
Reset value
Description
10254Ch
RESERVED
8
r/w
00h
Reserved for test.
102550h
RESERVED
32
r/w
00000000h
Reserved for test.
102554h
RESERVED
2
r/w
0
Reserved for test.
102558h
RESERVED
1
r/w
0
Reserved for test.
10255Ch
RESERVED
1
r/w
0
Reserved for test.
102560h
RESERVED
32
r/o
-
Reserved for test.
102564h
RESERVED
1
r/w
0
Reserved for test.
102568h
RESERVED
32
r/o
-
Reserved for test.
10256Ch
RESERVED
8
r/w
00h
Reserved for SCU test.
102570h
RESERVED
8
r/w
00h
Reserved for SCU test.
102574h
REG_TOUCH_DIRECT
_XY
32
r/o
-
Touch screen direct (x; y) conversions
102578h
REG_TOUCH_DIRECT
_Z1Z2
32
r/o
-
Touch screen direct (z1; z2)
conversions
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