V58XA System

V58XA System

Service Guide

Table of Contents

Chapter 1

1.1

1.2

1.3

1.4

Jumper Settings

System Board Layout ............................................................................................... 1-1

System Board Settings ............................................................................................. 1-2

Processor Type Jumper Settings.............................................................................. 1-3

Connector and Functions.......................................................................................... 1-4

Chapter 2 Major Chipsets

2.1 M1531 ....................................................................................................................... 2-1

2.1.1 Features .................................................................................................... 2-2

2.1.2

Pin Diagram............................................................................................... 2-4

2.1.4 Numberical List ................................................................................. 2-10

2.2 M1533 ..................................................................................................................... 2-19

2.2.1 Features .................................................................................................. 2-19

2.2.4 Numerical Pin List ................................................................................... 2-35

2.3.1 Features .................................................................................................. 2-45

2.3.1.1 3D Accelerator......................................................................... 2-45

2.3.1.2 2D Accelerator ........................................................................ 2-46

2.3.1.3 Video Accelerator .................................................................... 2-46

2.3.1.4 General Features .................................................................... 2-47

2.4.1 Features .................................................................................................. 2-53

2.5 SMC 37C93xAPM.................................................................................................... 2-58

2.5.1 Features .................................................................................................. 2-58

2.5.5 Multifunction Pins with GPI/O and Other Alternate Functions ................ 2-66

Appendix A: Schematics

ii

C h a p t e r 1

Jumper Settings

1.1 System Board Layout

Note: The blackened pin of a jumper represents pin 1.

Figure 1 System Board Jumper and Connector Locations

1.2 System Board Jumper Settings

Table 1 System Board Jumper Settings

Jumper/Settings

JPX2

1-2

2-3*

System board PCB number: 97114-1

JP4

1-2, 4-5

1-2, 5-6

2-3, 5-6

2-3, 4-5

Function

BIOS logo setting

Without IBM logo shown on screen during POST

With IBM logo shown on screen during

POST

Core/bus frequency rate

P54C 6X86L P55C/6X86MX/K6

1.5

3.0

3.5

2.0

2.5

3.0

2.0

--

--

2.0

2.5

3.0

System board PCB number: 97114-2

JPX3, JP4

2-3, (1-2, 4-5)

2-3, (1-2, 5-6)

2-3, (2-3, 5-6)

2-3, (2-3, 4-5)

1-2, (1-2, 5-6)

1-2, (2-3, 5-6)

System board PCB number: 97114-1

JP3, JP5, JP6

Closed

β

, Open

α

, 3-5

Closed β , Open α , 2-4

Closed

β

, Open

α

, 4-6

Closed

β

, Open

α

, 7-8

Open α , Closed β , 1-3

Open

α

, Closed

β

, 3-5

System board PCB number: 97114-2

JP3, JP5, JP6

Closed

β

, Open

α

, 3-5

Closed β , Open α , 2-4

Closed

β

, Open

α

, 4-6

Closed

β

, Open

α

, 7-8

Open α , Closed β , 1-3

Open

α

, Closed

β

, 3-5

JP9

1-2

*

2-3

Core/bus frequency rate

P54C 6X86L P55C/6X86MX/K6

1.5

2.0

2.5

3.0

2.0

--

3.5

2.0

2.5

3.0

--

--

--

--

--

3.0

4.0 (not applicable to 55.38401.061)

4.5 (not applicable to 55.38401.061)

Processor core voltage

2.1V (reserved)

2.8V

2.9V

3.2V

3.3V

3.52V

Processor core voltage

2.2V (2.1V for 55.38401.061)

2.8V

2.9V

3.2V

3.3V

3.52V

Password security

Check password

Bypass password

α : Disconnected, no jumper installed.

β : Connections pins 1-2, 3-4, 5-6, 7-8.

*

: Default setting.

1-2 Service Guide

Jumper/Settings

JP10, JP11

(1-3, 2-4), (1-3, 2-4)

(3-5, 4-6), (1-3, 2-4)

(1-3, 2-4), (3-5, 4-6)

(3-5, 4-6), (3-5, 4-6)

Function

Host / PCI bus frequency

60 /30 MHz

66 /33 MHz

75 /30 MHz

83 /33 MHz

1.3 Processor Type Jumper Settings

Warning: You must check out the exact processor type before setting the processor type jumpers.

The wrong processor type jumper setting may damage CPU, especially the single/dual voltage setting.

Table 2 Processor Type Jumper Settings

CPU

P-166

P-200

P-166

P-200

P-233

PR166+

PR200+

PR166+

PR166

PR200

PR233

PR266

PR300

JP3

JPX3

δ

JP4 JP5

Pentium

JP6

Open

α

2-3 2-3, 5-6 Closed

β

1-3

Open

α

2-3 2-3, 4-5 Closed

β

1-3

Pentium MMX

Closed

Closed

Closed

β

β

β

2-3

2-3

2-3

2-3, 5-6

2-3, 4-5

1-2, 4-5

Open

Open

Open

α

α

α

Cyrix/IBM 6x86L

2-4

2-4

2-4

JP10

3-4, 5-6

3-4, 5-6

3-5, 4-6

3-5, 4-6

3-5, 4-6

Closed

β

2-3 1-2, 5-6 Open

α

Closed β 2-3 1-2, 5-6 Open α

Cyrix/IBM 6x86MX

2-4

2-4

Closed

β

2-3 1-2, 5-6 Open

α

AMD K6

4-6

3-5, 4-6

1-3, 2-4

3-5, 4-6

Closed

β

2-3 2-3, 5-6 Open

α

Closed

β

2-3 2-3, 4-5 Open

α

4-6

4-6

3-5, 4-6

3-5, 4-6

Closed β 2-3 1-2, 4-5 Open α 7-8

AMD K6 (for PCB number: 97114-2)

3-5, 4-6

Closed β 1-2 1-2, 5-6 Open α

Closed β 1-2 2-3, 5-6 Open α

3-5

3-5

3-5, 4-6

3-5, 4-6

JP11

1-3, 2-4

1-3, 2-4

1-3, 2-4

1-3, 2-4

1-3, 2-4

1-3, 2-4

3-5, 4-6

1-3, 2-4

1-3, 2-4

1-3, 2-4

1-3, 2-4

1-3, 2-4

1-3, 2-4

δ : JPX3 is an optional jumper, the system board may come without it.

α : Disconnected, no jumper installed.

β : Connections pins 1-2, 3-4, 5-6, 7-8.

Jumper Settings 1-3

1.4 Connector and Functions

Table 3 System Board Connector Functions

Connector Function

CN1

CN2

CN3

CN4

CN5

CN6

CN8

CN9

CN10

CN12

CN13

CN14

CN15

CN16

CN17

CN19

FN1

Lower: PS/2 keyboard connector

Upper: PS/2 mouse connector

Modem/voice-in connector

Universal serial bus (USB) connectors

Upper: Printer port

Lower: Serial port

Video port

Upper: MIDI/game port

Lower: Line-out, line-in, mic-in ports

CD audio input connector

ATI media connector (AMC)

Modem ring-in wake-up connector

Secondary IDE channel

Hard disk LED connector

Connect the red wire to pin-1, white wire to pin-2, then leave pin-3, -4 as non-connected; or connect the red wire to pin-4, white wire to pin-3, then leave pin-1,-2 as non-connected.

Primary IDE channel

Power/suspend switch connector

This connector has no directional concern.

Standby power connector

Diskette connector

Power LED connector.

Connect the green wire to pin-12, white wire to pin-14.

System board power connector

Processor fan connector

Connect to…

Keyboard

Mouse

Modem card

USB devices

Printer

Serial device

Monitor

Joystick

Speaker, microphone

CD-ROM drive

Reserved

Modem card

CD-ROM drive

Hard disk drive

Hard disk drive

Power/suspend switch

Power supply

Diskette drive

Power LED

Power supply

CPU heat sink

1-4 Service Guide

8 MB

8 MB

8 MB

16 MB

16 MB

16 MB

32 MB

32 MB

32 MB

Table 4

DIMM1

8 MB

16 MB

32 MB

8 MB

16 MB

32 MB

8 MB

16 MB

32 MB

8 MB

16 MB

32 MB

8 MB

16 MB

32 MB

DIMM Configurations

DIMM2 Total Memory

8 MB

16 MB

32 MB

8 MB

16 MB

32 MB

16 MB

24 MB

40 MB

24 MB

32 MB

48 MB

40 MB

48 MB

64 MB

Jumper Settings 1-5

C h a p t e r 2

Major Chipsets

2.1. M1531

The Aladdin-IV is the succeeding generation chipset of Aladdin-III from Acer Labs. It maintains the best system architecture (two-chip solution) to achieve the best system performance with the lowest system cost (TTL-free). The Aladdin-IV consists of two BGA chips to give the 586-class system a complete solution with most up-to-date features and architecture for multimedia/ multithreading OS and software applications. It utilizes the modern BGA package to improve the AC characterization, resolves system bottleneck and makes the system manufacturing easier.

The M1531 includes:

Higher CPU bus frequency (up to 83.3 MHz) interface for the incoming Cyrix M2 and AMD K6,

PBSRAM and Memory Cache L2 controller

Internal MESI tag bits (8K x 2) to reduce cost and enhance performance

High-performance FPM/EDO/SDRAM DRAM controller

PCI 2.1 compliant bus interface

Smart deep buffer design for CPU-to-DRAM, CPU-to-PCI, and PCI-to-DRAM to achieve the best system performance

Highly efficient PCI fair arbiter

The most flexible 32/64-bit memory bus interface for the best DRAM upgrade ability and

ECC/parity design to enhance the system reliability

With the concurrent bus design, PCI-to-PCI access can run concurrently with CPU-to-L2 and CPUto-DRAM access, while PCI-to-DRAM access can run concurrently with CPU-to-L2 access. The

M1531 also supports the snoop ahead feature to achieve the PCI master full-bandwidth access

(133 MB) and provides the enhanced power management features including ACPI support, suspend DRAM refresh, and internal chip power control to support the Microsoft’s On Now technology OS.

The M1533 offers the best power management system solution. It integrates ACPI support, deep green function, two-channel dedicated Ultra-33 IDE master controller, two-port USB controller,

SMBus controller, and PS2 keyboard/mouse controller.

The M1543 provides the best desktop system solution. It integrates ACPI support, green function, two-channel dedicated Ultra-33 IDE Master controller, two-port USB controller, SMBus controller,

PS/2 keyboard/mouse controller and the Super I/O (Floppy Disk Controller, two serial port/one parallel port) support.

The Aladdin-IV gives a highly-integrated system solution and a most up-to-date architecture to provide the best cost/performance system solution for desktop and notebook vendors.

Major Chipsets 2-1

2.1.1 Features

Supports all Intel/Cyrix/AMD/TI/IBM 586 processors. Host bus at 83.3, 75, 66, 60 and 50 MHz at 3.3V/2.5V

Supports Linear Wrap mode for Cyrix M1 and M2

Write-Allocation feature for K6

Pseudo-Synchronous PCI bus access

(CPU bus: 75 MHz - PCI bus: 30 MHz, CPU bus: 83.3 MHz - PCI bus: 33 MHz)

Supports Pipelined-burst SRAM/Memory Cache

Direct mapped, 256 KB/512 KB/1 MB

Write-Back/Dynamic-Write-Back cache policy

Built-in 8K x 2 bit SRAM for MESI protocol to reduce cost and enhance performance

Cacheable memory up to 64 MB with 8-bit Tag SRAM

Cacheable memory up to 512 MB with 11-bit Tag SRAM

3-1-1-1-1-1-1-1 for Pipelined-burst SRAM/Memory Cache at back-to-back burst read and write cycles

3.3V/5V SRAMs for Tag address

CPU single-read cycle L2 allocation

Supports FPM/EDO/SDRAM DRAMs

8 RAS lines up to 1 GB support

64-bit data path to memory

Symmetrical/Asymmetrical

3.3V or 5V DRAMs

Duplicated MA[1:0] driving pins for burst access

No buffer needed for RASJ and CASJ and MA[1:0]

CBR and RAS-only refresh for FPM

CBR and RAS-only refresh and Extended refresh and self refresh for EDO

CBR and Self refresh for SDRAM

16 Qword deep merging buffer for 3-1-1-1-1-1-1-1 posted-write cycle to enhance high-speed CPU burst access

6-3-3-3-3-3-3-3 for back-to-back FPM read page hit, 5-2-2-2-2-2-2-2 for back-to-back

EDO read page hit, 6-1-1-1-2-1-1-1 for back-to-back SDRAM read page hit, 2-2-2-2 for retired data for posted write on FPM and EDO page-hit, x-1-1-1 for retired data for posted write SDRAM page-hit

Enhanced DRAM page miss performance

Supports 64 Mbit (16M x 4, 8M x 8, 4M x 16) technology of DRAMs

2-2 Service Guide

Supports Programmable-strength RAS/CAS/ MWEJ/MA buffers

Supports Error Checking and Correction (ECC) and Parity for DRAM

Supports the most flexible six 32-bit populated banks of DRAM for easy DRAM upgrade

Supports SIMM and DIMM

Synchronous/Pseudo Synchronous 25/30/33MHz 3.3V/5V tolerance PCI interface

Concurrent PCI architecture

PCI bus arbiter: five PCI masters and M1533/ M1543 (ISA Bridge) supported

6 DWords for CPU-to-PCI memory write posted buffers

Converts back-to-back CPU to PCI memory write to PCI burst cycle

38/22 Dwords for PCI-to-DRAM Write-posted/ Read-prefetching buffers

PCI-to-DRAM up to 133 MB/sec bandwidth (even when L1/L2 write-back)

L1/L2 pipelined-snoop ahead for PCI-to-DRAM cycle

Supports PCI mechanism #1 only

Complies with PCI spec. 2.1 (N(32/16/8)+8 rule, passive release, fair arbitration)

Enhanced performance for Memory-Read-Line, Memory-Read-Multiple and Memorywrite- Invalidate PCI commands

Enhanced Power Management

ACPI

PCI bus CLKRUN function

Dynamic Clock Stop

Power-on

Suspend to Disk

Suspend to DRAM

Self refresh during Suspend

328-pin (27mm x 27mm) BGA package

Major Chipsets 2-3

2.1.2 Pin Diagram

1

2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20

A

NC

PHLDAJ

AD3 AD6 AD8 AD12 PAR

TRDYJ

AD17

AD22

AD25 AD30

REQJ3

GNTJ2

GNTJ3 MPD2 MPD0

MD61 MD29 MD62

B

BEJ0 PHLDJ AD2 AD5 AD7 AD11 CBEJ1

DEVSELJ

AD16 AD21 AD24 AD29 REQJ2

GNTJ1

MPD5

MPD1 MD63

MD27 MD60

MD28

C

BEJ3 BEJ2 BEJ1 AD4

CBEJ0

AD10 AD15

STOPJ

CBEJ2

AD20CBEJ3 AD28

REQJ1

GNT0J

MPD4

MD30 MD25 MD58 MD26 MD59

D

BEJ6 BEJ5 BEJ4 AD0 AD1 AD9 AD14

LOCKJ FRAMEJ

AD19 AD23

AD27

REQJ0 MPD7 MPD3 MD55 MD23 MD56

MD24 MD57

E

DCJ HITMJ

EADSJ

BEJ7 RSTJ

PCIMRQJ

AD13

SERRJ

IRDYJ

AD18 PCLKIN AD26 AD31 MPD6

MD31

MD20 MD53 MD21 MD54

MD22

F

BRDYJ BOFFJ

SMIACTJ

HLOCKJ

ADSJ VCC_B

VCC_C

VCC_C MD50

MD18 MD51 MD19 MD52

G HD63

CACHEJ AHOLD

KENJ NAJ

VCC_A

M1531

VCC_C

MD15 MD48 MD16 MD49 MD17

H

HD60 HD61

HD62

W RJ MIOJ

J

HD55 HD56

HD57 HD58 HD59

K

L

HD51 HD52

HD46 HD47

HD53

HD48

HD54 HCLKIN

HD49

HD50

GND GND

GND GND

GND GND

GND GND

GND GND

GND GND

GND GND

GND GND

GND

GND

GND

GND

GND

GND

GND

GND

MD45 MD13 MD46

MD10

MD14

MD47

MD43 MD11 MD44

MD12

MD40

MD8

MD41

MD9 MD42

MD5 MD38

MD6

MD39 MD7

MD35 MD3

MD36

MD4 MD37 M HD41 HD42

HD43 HD44 HD45

N

HD36 HD37

HD38 HD39 HD40

P

HD31 HD32

HD33

HD34

HD35 VCC_A

R

HD26

HD27

HD28

HD29

HD30 VDD5 VCC_A

GND GND GND GND GND GND

GND GND GND GND GND GND

VDD5S

REQJ4

GNTJ4

VCC_C

32K

MD1 MD34 MD2

SUSPEND

MD32

MD0 MD33

VCC_B

VCC_C

RASJ6

RASJ7

CASJ2

CASJ7 CASJ3

T

HD21 HD22

HD23

HD24

HD25

HD0 A12 A5 GW EJ

COEJ

CADVJ

TW EJ MAA0 MAA1TIO8 TIO9 TIO10

RASJ1

RASJ0 CASJ6

U

HD16 HD17

HD18

HD19

HD20

HD1 A13 A8 CCSJ

BWEJ CADSJ

TIO0 TIO1

MAB0

MAB1 MA5 MW EJ

RASJ4

RASJ3 RASJ2

V

HD15 HD14

HD13

HD6 HD3 A17 A14 A10

A4

A29 A25 A24 A23 TIO2 MA2 MA4 MA8

CASJ5

CASJ1 RASJ5

W HD12 HD11

HD10

HD5 HD2 A18 A15 A11 A7

Y

HD9 HD8 HD7 HD4 A20 A19 A16 A9 A6

A30 A31 A22 A21 TIO4 TIO6 MA3 MA7 MA10

CASJ0

CASJ4

A3 A28 A26 A27 TIO3 TIO5 TIO7 MA6 MA9 MA11 NC

TOP VIEW

Figure 2-1 M1531 Pin Diagram

2-4 Service Guide

2.1.3 Pin Descriptions

Table 2- 1 M1531 Signal Descriptions

Signal Type

Host Interface 3.3V/2.5V

A[31:3] I/O

Group A

BEJ[7:0]

ADSJ

BRDYJ

NAJ

AHOLD

EADSJ

BOFFJ

HITMJ

MIOJ

DCJ

WRJ

HLOCKJ

CACHEJ

I

Group A

I

Group A

O

Group A

O

Group A

O

Group A

O

Group A

O

Group A

I

Group A

I

Group A

I

Group A

I

Group A

I

Group A

I

Group A

Description

Host Address Bus Lines. A[31:3] have two functions. As inputs, along with the byte enable signals, these pins serve as the address lines of the host address bus which define the physical area of memory or I/O being accessed. As outputs, the M1531 drives them during inquiry cycles on behalf of PCI masters.

Byte Enables. These are the byte enable signals for the data bus. BEJ[7] applies to the most significant byte and BEJ[0] applies to the least significant byte. They determine which byte of data must be written to the memory, or are requested by the CPU. In local memory read and line-fill cycles, these inputs are ignored by the M1531.

Address Strobe. The CPU will start a new cycle by asserting ADSJ first.

The M1531 will not precede to execute a cycle until it detects ADSJ active.

Burst Ready. The assertion of BRDYJ means the current transaction is complete. The CPU terminates the cycle by receiving 1 or 4 active

BRDYJs depending on different types of cycles.

Next Address. This signal is asserted by the M1531 to inform the CPU that pipelined cycles are ready for execution.

CPU AHold Request Output. It connects to the input of CPU's AHOLD pin and is actively driven for inquiry cycles.

External Address Strobe. This signal is connected to the CPU EADSJ pin.

During PCI cycles, the M1531 asserts this signal to proceed snooping.

CPU Back-Off. If BOFFJ is sampled active, CPU will float all its buses in the next clock. M1531 asserts this signal to request CPU floating all its output buses.

Primary Cache Hit and Modified. When snooped, the CPU asserts HITMJ to indicate that a hit to a modified line in the data cache occurred. It is used to prohibit another bus master from accessing the data of this modified line in the memory until the line is completely written back.

Host Memory or I/O. This bus definition pin indicates the current bus cycle is either memory or input/ output.

Host Data or Code. This bus definition pin is used to distinguish data access cycles from code access cycles.

Host Write or Read. When WRJ is driven high, it indicates the current cycle is a write. Inversely, if WRJ is driven low, a read cycle is performed.

Host Lock. When HLOCKJ is asserted by the CPU, the M1531 will recognize the CPU is locking the current cycles.

Host Cacheable. This pin is used by the CPU to indicate the system that

CPU wants to perform a line fill cycle or a burst write back cycle. If it is driven inactive in a read cycle, the CPU will not cache the returned data, regardless of the state of KENJ.

Host Interface 3.3V/2.5V

Major Chipsets 2-5

Table 2- 1

Signal

KENJ/INV

SMIACTJ

HD[63:0]

MPD[7:0]

RASJ[7] /

SRASJ[0]

RASJ[6] /

SCASJ[0]

RASJ[5:0]

CASJ[7:0] /

DQM[7:0]

MA[11:2]

MAA[1:0]

MAB[1:0]

MWEJ[0]

MD[63:0]

O

Group C

O

Group C

O

Group C

O

Group C

I/O

Group C

I

Group A

I/O

Group A

I/O

Group C

O

Group C

O

Group C

O

Group C

O

Group C

M1531 Signal Descriptions

Type

O

Group A

Description

Cache Enable Output. This signal is connected to the CPU's KENJ and INV pins. KENJ is used to notify the CPU whether the address of the current transaction is cacheable. INV is used during L1 snoop cycles. The M1531 drives this signal high (low) during the EADSJ assertion of a PCI master write (read) snoop cycle.

SMM Interrupt Active. This signal is asserted by the CPU to inform the

M1531 that SMM mode is being entered.

Host Data Bus Lines. These signals are connected to the CPU's data bus.

HD[63] applies to the most significant bit and HD[0] applies to the least significant bit.

DRAM Parity /ECC check bits. These are the 8 bits for parities/ECC check bits over DRAM data bus. MPD[7] applies to the most significant bit and

MPD[0] applies to the least significant bit.

Row Address Strobe 7, (FPM/EDO) of DRAM row 7.

SDRAM Row Address Strobe (SDRAM) copy 0. It connects to SDRAM

RASJ. This is a multifunction pin and determined by Index-5Ch bit0.

Row Address Strobe 6, (FPM/EDO) of DRAM row 6.

SDRAM Column address strobe (SDRAM) copy 0. It connects to SDRAM

CASJ. This is a multifunction pin and determined by Index-5Ch bit0.

Row Address Strobes. These signals are used to drive the corresponding

RASJs of FPM/EDO DRAMs. In SDRAM, they are used to drive the corresponding SDRAM CSJs.

Column Address Strobes or Synchronous DRAM Input/Output Data Mask.

These CAS signals should be connected to the corresponding CASJs of each bank of DRAM. The value of CASJs equals that of HBEJs for write cycles. During DRAM read cycles, all of CASJs will be active. In SDRAM, these pins act as synchronized output enables during a read cycle and the byte mask during write cycle, these pins are connected to SDRAM DQM[7:0].

DRAM Address Lines. These signals are the address lines[11:2] of all

DRAMs. The M1531 supports DRAM types ranging from 256K to 64Mbits.

Memory Address copy A for [1:0]. These signals are the address lines[1:0] copy 0 of all DRAMs.

Memory Address copy B for [1:0]. These signals are the address lines[1:0] copy 1 of all DRAMs.

DRAM Write Enable. This is the DRAM write enable pin and behaves according to the early-write mechanism, i.e. , it activates before the CASJs do. For refresh cycles, it will remain deasserted.

Memory Data. These pins are connected to DRAM’s data bits. MD[63] applies to the most significant bit and MD[0] applies to the least significant bit.

Host Interface 3.3V/2.5V

CLKEN[0]/

REQJ[4]

I/O

Group C

SDRAM Clock Enable Copy 0 or PCI Master Request. This signal is used as

SDRAM clock enable copy 0 to do self refresh during suspend. It can also be used as bus request signal of the fifth PCI master. This function is controlled by Index -5Dh bit 1.

2-6 Service Guide

Table 2- 1 M1531 Signal Descriptions

Signal

CLKEN[1]/

GNTJ[4]

Type

O

Group C

Description

SDRAM Clock Enable Copy 1 or PCI Master Grant. This signal is used as

SDRAM clock enable copy 1 to do self refresh during suspend. It can also be used as grant signal of the fifth PCI master. This function is controlled by

Index -5Dh bit 1.

Secondary Cache Interface 3.3V/2.5V Tolerance

CADVJ

CADSJ

O

Group A

O

Group A

Synchronous SRAM Advance. This signal will make PBSRAM/Memory

Cache internal burst address counter advance.

Synchronous SRAM Address Strobe. This signal connects to PBSRAM/

Memory Cache ADSCJ.

CCSJ

GWEJ

O

Group A

O

Group A

Synchronous SRAM Chip Select. This signal connects to PBSRAM/Memory

Cache CE1J to mask ADSPJ and enable ADSCJ sampling.

Synchronous SRAM Global Write Enable. This signal will write all the byte lanes data into PBSRAM/Memory Cache.

COEJ Synchronous SRAM Output Enable. This signal will enable the data output driving of PBSRAM/Memory Cache.

BWEJ

TIO[10]/

MWEJ[1]/

MKREFRQJ

O

Group A

O

Group A

I/O

Group C

Synchronous SRAM Byte-Write Enable. This signal connects to byte write enable of PBSRAM/Memory Cache.

TIO[9]/

SRASJ[1]

TIO[8]/

SCASJ[1]

TIO[7:0]

TAGWEJ

I/O

Group C

I/O

Group C

I/O

Group B

O

Group B

SRAM Tag[10] or another copy of MWEJ or DRAM Cache MKREFRQJ. This pin is used for multifunction. It can be SRAM tag address bit 10, or another copy of MWEJ connected to DRAM, or MKREFRQJ connected to DRAM

Cache. Refer to Register Index-41h bit 6, bit3 and bit0 description.

SRAM Tag[9] or Synchronous DRAM (SDRAM) RAS copy 1. This pin is used for multifunction. It can be SRAM tag address bit 9, or another copy of

SRASJ connected to SDRAM. Refer to Register Index-41h bit3 and bit0 description.

SRAM Tag[8] or Synchronous DRAM (SDRAM) CAS copy 1. This pin is used for multifunction. It can be SRAM tag address bit 8, or another copy of

SCASJ connected to SDRAM. Refer to Register Index-41h bit3 and bit0 description.

SRAM Tag[7:0]. This pin contains the L2 tag address for 256-KB L2 caches.

TIO[6:0] contain the L2 tag address and TIO7 contains the L2 cache valid bit for 512-KB caches. TIO[5:0] contain L2 tag address, TIO7 contains L2 cache valid bit and TIO6 contains the L2 cache dirty bit for 1-MB cache.

Refer to index-41h cache configuration table.

Tag Write Enable. This signal, when asserted, will write into the external tag new state and tag addresses.

PCI Interface 3.3V/2.5V Tolerance

AD[31:0] I/O

Group B

PCI Address and Data Bus Lines. These lines are connected to the PCI bus.

AD[31:0] contain the information of address or data for PCI transactions.

CBEJ[3:0] I/O

Group B

PCI Bus Command and Byte Enables. Bus commands and byte enables are multiplexed in these lines for address and data phases, respectively.

Major Chipsets 2-7

Table 2- 1 M1531 Signal Descriptions

Signal

FRAMEJ

Type

I/O

Group B

Description

Cycle Frame of PCI Buses. This indicates the beginning and duration of a

PCI access. It will be as an output driven by M1531 on behalf of CPU, or as an input during PCI master access.

Device Select. When the target device has decoded the address as its own cycle, it will assert DEVSELJ.

DEVSELJ

IRDYJ

TRDYJ

STOPJ

LOCKJ

REQJ[3:0]

GNTJ[3:0]

PHLDJ

PHLDAJ

PAR

O

Group B

I

Group B

O

Group B

I/O

Group B

I/O

Group B

I/O

Group B

I/O

Group B

I/O

Group B

I/O

Group B

I/O

Group B

I

Group B

Initiator Ready. This signal indicates the initiator is ready to complete the current data phase of transaction.

Target Ready. This pin indicates the target is ready to complete the current data phase of transaction.

Stop. This signal indicates the target is requesting the master to stop the current transaction.

Lock Resource Signal. This pin indicates the PCI master or the bridge intends to do exclusive transfers.

Bus Request signals of PCI Masters. When asserted, it means the PCI

Master is requesting the PCI bus ownership from the arbiter.

Grant signals to PCI Masters. When asserted by the arbiter, it means the

PCI master has been legally granted to own the PCI bus.

PCI bus Hold Request. This active low signal is a request from

M1533/M1543 for the PCI bus.

PCI bus Hold Acknowledge. This active low signal grants PCI bus to

M1533/M1543.

Parity bit of PCI bus. It is the even parity bit across PAD[31:0] and

CBEJ[3:0].

SERRJ/

CLKRUNJ

System Error or PCI Clock RUN. If the M1531 detects parity errors in

DRAMs, it will assert SERRJ to notify the system. As CLKRUNJ, this signal will connect to M1533 CLKRUNJ to start, or maintain the PCI CLOCK. It is a multifunction pin and determined by Index-77h bit0.

Clock, Reset, and Suspend

HCLKIN I

Group A

CPU bus Clock Input. This signal is used by all of the M1531 logic that is in the Host clock domain.

RSTJ I

Group B

System Reset. This pin, when asserted, resets the M1531 state machine, and sets the register bits to their default values.

Clock, Reset, and Suspend

PCICLK I

Group B

PCI bus Clock Input. This signal is used by all of the M1531 logic that is in the PCI clock domain.

PCIMRQJ O

Group B

SUSPENDJ I

Group C

Total PCI Request. This signal is used to notify M1533/M1543 that there is

PCI master requesting PCI bus.

Suspend. When actively sampled, the M1531 will enter the I/O suspend mode. This signal should be pulled high when the suspend feature is disabled.

2-8 Service Guide

Table 2- 1

Signal

OSC32KO

Power Pins

VCC_A P

VCC_B

VCC_C

VDD_5

VDD_5S

Vss or Gnd

M1531 Signal Descriptions

Type

I

Group C

Description

The refresh reference clock of frequency 32 KHz during suspend mode.

This signal should be pulled to a fixed value when the suspend feature is disabled.

P

P

P

P

P

Vcc 3.3V or 2.5V Power for Group A. This power is used for CPU interface and L2 control signals. If this power connects to 3.3V, the relative signals will output 3.3V and accept 3.3V input. If this power connects to 2.5V, the relative signals will output 2.5V and accept 2.5V input.

Vcc 3.3V Power for Group B. This power is used for PCI interface and Tag signals. It must connect to 3.3V. The relative signals will output 3.3V and

5V input tolerance.

Vcc 3.3V Power for Group C. This power is used for DRAM interface signals during normal operation and suspend refresh. It must connect to 3.3V. The relative signals will output 3.3V and 5V input tolerance.

Vcc 5.0V Power for Group A and Group B. This pin supplies the 5V input tolerance circuit and the core power for the internal circuit except the suspend circuit.

Vcc 5.0V Power for Group C. This pin supplies the 5V input tolerance circuit and the core power for the internal suspend circuit.

Ground

Major Chipsets 2-9

2.1.4 Numerical Pin List

Pin

No.

Pin

Name

Pin

Type

A1 --

A2 PHLDAJ O

A3 AD3

A4 AD6

I/O

I/O

A5 AD8

A6 AD12

A7 PAR

A8 TRDYJ

I/O

I/O

I/O

I/O

A9 AD17

A10 AD22

A11 AD25

A12 AD30

A13 REQJ3

A14 GNTJ2

A15 GNTJ3

A16 MPD2

I

O

O

I/O

I/O

I/O

I/O

I/O

A17 MPD0

A18 MD61

A19 MD29

A20 MD62

B1 BEJ0

B2 PHLDJ

B3 AD2

B4 AD5

B5 AD7

B6 AD11

I/O

I/O

B7 CBEJ1 I/O

B8 DEVSELJ I/O

B9 AD16

B10 AD21

B11 AD24

B12 AD29

I/O

I/O

I/O

I/O

I

I

I/O

I/O

I/O

I/O

I/O

I/O

B13 REQJ2

B14 GNTJ1

B15 MPD5

B16 MPD1

B17 MD63

B18 MD27

I

O

I/O

I/O

I/O

I/O

2-10 Service Guide

B19 MD60

B20 MD28

C1 BEJ3

C2 BEJ2

C3 BEJ1

C4 AD4

C5 CBEJ0

C6 AD10

C7 AD15

C8 STOPJ

C9 CBEJ2

C10 AD20

C11 CBEJ3

C12 AD28

C13 REQJ1

C14 GNTJ0

C15 MPD4

C16 MD30

C17 MD25

C18 MD58

C19 MD26

C20 MD59

D1 BEJ6

D2 BEJ5

D3 BEJ4

D4 AD0

D5 AD1

D6 AD9

D7 AD14

D8 LOCKJ

I/O

I/O

D9 FRAMEJ I/O

D10 AD19 I/O

I

I/O

I/O

I/O

I

I

I/O

I/O

I/O

I/O

I/O

I/O

D11 AD23

D12 AD27

D13 REQJ0

D14 MPD7

D15 MPD3

D16 MD55

D17 MD23

D18 MD56

D19 MD24

I/O

I/O

I/O

I/O

I/O

I/O

I/O

I

I/O

I

O

I/O

I/O

I/O

I/O

I/O

I/O

I

I/O

I/O

I/O

I

I

I/O

I/O

Major Chipsets 2-11

D20 MD57

E1 DCJ

E2 HITMJ

E3 EADSJ

E4 BEJ7

E5 RSTJ I

I

E6 PCIMRQJ O

E7 AD13 I/O

I

I/O

I

O

E8 SERRJ

E9 IRDYJ

E10 AD18

E11 PCLKIN

E12 AD26

E13 AD31

E14 MPD6

E15 MD31

I/O

I/O

I/O

I/O

I/O

I/O

I

I/O

E16 MD20

E17 MD53

E18 MD21

E19 MD54

E20 MD22

F1 BRDYJ

I/O

O

F2 BOFFJ

F3 SMIACTJ I

O

I/O

I/O

I/O

I/O

F4 HLOCKJ I

F5 ADSJ I

F6 VCC_B

F14 VCC_C

P

P

F15 VCC_C

F16 MD50

F17 MD18

F18 MD51

P

I/O

I/O

I/O

F19 MD19

F20 MD52

I/O

I/O

G1 HD63

G2 CACHEJ I

I/O

G3 AHOLD

G4 KENJ

G5 NAJ

G6 VCC_A

G15 VCC_C

O

O

O

P

P

2-12 Service Guide

P

P

P

P

P

P

I/O

I/O

I/O

I/O

I/O

I/O

I/O

I/O

I/O

I/O

I/O

I/O

I/O

I/O

I/O

I/O

I/O

I/O

I/O

P

P

P

P

P

P

I

I

I/O

I/O

I/O

I/O

I/O

I/O

I/O

I/O

H16 MD45

H17 MD13

H18 MD46

H19 MD14

H20 MD47

J1 HD55

J2 HD56

J3 HD57

J4 HD58

J5 HD59

J8 GND

J9 GND

J10 GND

J11 GND

J12 GND

J13 GND

G16 MD15

G17 MD48

G18 MD16

G19 MD49

G20 MD17

H1 HD60

H2 HD61

H3 HD62

H4 WRJ

H5 MIOJ

H8 GND

H9 GND

H10 GND

H11 GND

H12 GND

H13 GND

J16 MD10

J17 MD43

J18 MD11

J19 MD44

J20 MD12

K1 HD51

K2 HD52

K3 HD53

K4 HD54

Major Chipsets 2-13

L5 HD50

L8 GND

L9 GND

L10 GND

L11 GND

L12 GND

L13 GND

L16 MD5

L17 MD38

L18 MD6

L19 MD39

L20 MD7

M1 HD41

M2 HD42

M3 HD43

M4 HD44

K5 HCLKIN I

K8 GND P

K9 GND

K10 GND

P

P

K11 GND

K12 GND

K13 GND

K16 MD40

P

P

P

I/O

K17 MD8

K18 MD41

K19 MD9

K20 MD42

L1 HD46

L2 HD47

L3 HD48

L4 HD49

I/O

I/O

I/O

I/O

I/O

I/O

I/O

I/O

M5 HD45

M8 GND

M9 GND

M10 GND

M11 GND

M12 GND

M13 GND

M16 MD35

M17 MD3

P

P

P

I/O

I/O

P

P

I/O

P

I/O

I/O

I/O

I/O

I/O

I/O

I/O

I/O

P

P

P

I/O

P

P

I/O

P

2-14 Service Guide

N17 GNTJ4

N18 MD1

N19 MD34

N20 MD2

P1 HD31

P2 HD32

P3 HD33

P4 HD34

P5 HD35

P6 VCC_A

P15 VCC_C

P16 32K

P17 SUSPEN

DJ

P18 MD32

M18 MD36

M19 MD4

M20 MD37

N1 HD36

N2 HD37

N3 HD38

N4 HD39

N5 HD40

N8 GND

N9 GND

N10 GND

N11 GND

N12 GND

N13 GND

N15 VDD5S

N16 REQJ4

P19 MD0

P20 MD33

R1 HD26

R2 HD27

R3 HD28

R4 HD29

R5 HD30

R6 VDD5

R7 VCC_A

R14 VCC_B

R15 VCC_C

I/O

I/O

I/O

I/O

I/O

I/O

I/O

P

P

I/O

P

P

I/O

I/O

I/O

I/O

O

I/O

I/O

I/O

I

I

P

I/O

P

P

P

P

I/O

P

P

P

P

I/O

I/O

I/O

I/O

I/O

I/O

I/O

I/O

Major Chipsets 2-15

I/O

I/O

I/O

I/O

O

I/O

I/O

I/O

I/O

I/O

O

O

O

O

O

I/O

I/O

I/O

O

O

O

I/O

O

O

O

I/O

O

O

O

I/O

I/O

I/O

I/O

O

I/O

I/O

I/O

O

O

O

O

T12 TWEJ

T13 MAA0

T14 MAA1

T15 TIO8

T16 TIO9

T17 TIO10

T18 RASJ1

T19 RASJ0

T20 CASJ6

U1 HD16

U2 HD17

U3 HD18

U4 HD19

U5 HD20

U6 HD1

U7 A13

R16 RASJ6

R17 RASJ7

R18 CASJ2

R19 CASJ7

R20 CASJ3

T1 HD21

T2 HD22

T3 HD23

T4 HD24

T5 HD25

T6 HD0

T7 A12

T8 A5

T9 GWEJ

T10 COEJ

T11 CADVJ

U8 A8

U9 CCSJ

U10 BWEJ

U11 CADSJ

U12 TIO0

U13 TIO1

U14 MAB0

U15 MAB1

U16 MA5

2-16 Service Guide

I/O

I/O

I/O

I/O

I/O

I/O

I/O

I/O

I/O

I/O

O

O

O

O

I/O

O

O

I/O

I/O

I/O

I/O

I/O

I/O

I/O

I/O

I/O

I/O

I/O

I/O

I/O

I/O

O

O

O

I/O

I/O

I/O

V15 MA2

V16 MA4

V17 MA8

V18 CASJ5

V19 CASJ1

V20 RASJ5

W1 HD12

W2 HD11

W3 HD10

W4 HD5

W5 HD2

W6 A18

W7 A15

W8 A11

W9 A7

W1

0

A30

W1

1

A31

A22 W1

2

W1

3

A21

U17 MWEJ

U18 RASJ4

U19 RASJ3

U20 RASJ2

V1 HD15

V2 HD14

V3 HD13

V4 HD6

V5 HD3

V6 A17

V7 A14

V8 A10

V9 A4

V10 A29

V11 A25

V12 A24

V13

7

A23

V14 TIO2

Major Chipsets 2-17

O

O

I/O

I/O

O

O

O

I/O

I/O

I/O

I/O

I/O

I/O

I/O

I/O

I/O

O

O

O

--

I/O

I/O

I/O

I/O

I/O

I/O

I/O

W1

4

W1

5

W1

6

W1

7

W1

8

TIO4

TIO6

MA3

MA7

MA10

W1

9

W2

0

CASJ0

CASJ4

Y1 HD9

Y2 HD8

Y3 HD7

Y4 HD4

Y5 A20

Y6 A19

Y7 A16

Y8 A9

Y9 A6

Y10 A3

Y11 A28

Y12 A26

Y13 A27

Y14 TIO3

Y15 TIO5

Y16 TIO7

Y17 MA6

Y18 MA9

Y19 MA11

Y20 --

2-18 Service Guide

2.2. M1533

The M1533 is a bridge between PCI and ISA bus, providing full PCI and ISA compatible functions.

This chip has Integrated System Peripherals (ISP) (2 x 82C59 and serial interrupt, 1 x 82C54), advanced features (Type F and Distributed DMA) in the DMA controller (2 x 82C54), PS/2 keyboard/mouse controller, two-channel dedicated IDE master controller with Ultra-33 specification,

System Management Bus (SMB), and two OpenHCI 1.0a USB ports. The ACPI (Advanced

Configuration and Power Interface) and PCI 2.1 (Delayed Transaction & Passive Release) specification have also been implemented. Furthermore, this chip supports the Advanced

Programmable Interrupt Controller (APIC) interface for Multiple-Processors system.

The M1533 also supports the deep flexible green function for the best green system. It can connect to the ALi Pentium North Bridge (M1521/M1531/M1541) and ALi Pentium Pro North Bridge (M1615) to provide the best system solution. One eight-byte bidirectional line buffer is provided for ISA/DMA master memory read/writes; one 32-bit wide posted write buffer is provided for PCI memory write &

I/O write (for audio) cycles to the ISA bus, to provide a PCI to ISA IRQ routing table, and level-to-edge trigger transfer.

The chip provides two extra IRQ lines and one programmable chip select for motherboard

Plug-and-Play functions. The interrupt lines can be routed to any of the available ISA interrupts.

The on-chip IDE controller supports two separate IDE connectors for up to four IDE devices providing an interface for IDE hard disks and CD ROMs. The Ultra 33 specification (that supports the 33 MB/second transfer rate) has been implemented at this IDE controller. The ATA bus pins and the buffer (read ahead and posted write) are all dedicated for separate channel to improve the performance of IDE master.

The M1533 supports Super Green function for Intel and Intel compatible CPUs. It implements SMI or SCI (System Controller Interrupt) to meet the ACPI specification. It also meets the requirement for OnNow design initiative. It also features powerful power management for power saving including On, Standby, Sleeping, SoftOff, and Mechanical Off states. To control the CPU power consumption, it provides CPU clock control (STPCLKJ). The STPCLKJ can be active (low) or inactive (high) in turn by throttling control. In addition, the M1533 offers the most flexible system clock design. It can be programmed to stop the CPU Clock, PCI Clock, the Clock cell, or to reduce the Clock frequency. The PBSRAM (Pipelined-burst SRAM) doze mode is also supported.

The M1533 is includes a PS/2 keyboard/mouse controller, SMBus, two OpenHCI 1.0a USB ports, and the dedicated GPIO (General Purpose Input/Output) pins. These components enable the chip to implement the best green and cost/performance system.

2.2.1 Features

Provides a bridge between the PCI bus and ISA bus for both Pentium and Pentium Pro systems

PCI interface

PCI master and slave interface

PCI master and slave initiated termination

PCI spec. 2.1 compliant (Delayed Transaction support)

Major Chipsets 2-19

Buffers control

8-byte bidirectional line buffers for DMA/ISA memory read/write cycles to PCI bus

32-bit posted write buffer for PCI memory write and I/O data write (for sound card) to

ISA bus

Provides steerable PCI interrupts for PCI device plug-and-play

Up to eight PCI interrupt routing

Level-to-edge trigger transfer

Enhanced DMA controller

Provides 7 programmable channels: 4 for 8-bit data size, 3 for 16-bit data size

32-bit

Provides compatible DMA transfers

Provides Type F transfers

Interrupt controller

Provides 14 interrupt channels

Independent programmable level/edge triggered channels

Counter/Timers

8254 compatible timers for System Timer, Refresh Request, Speaker Output Use

Distributed DMA supported

7 DMA Channels can be arbitrarily programmed as distributed channel

Serialized IRQ supported

Quiet/Continuous

Programmable (default 21) IRQ/DATA frames

Programmable START frame pulse width

Plug-and-Play port supported

One programmable chip select

Two steerable interrupt request lines

Built-in keyboard controller

Built-in PS/2/AT keyboard and PS/2 mouse controller

Supports up to 256-KB ROM size decoding

2-20 Service Guide

Supports positive/subtractive decode for ISA device

PMU features

Full-support for ACPI and OS directed power management

CPU SMM Legacy mode and SMI feature supported

Supports programmable STPCLKJ: throttle/CKONSTP/CKOFFSTP control

Supports I/O trap for I/O restart feature

PMU operation states :

On

Standby

Sleeping ( Power-On Suspend )

Suspend ( Suspend to DRAM)

Suspend to HDD

Soft

Mechanical

APM state detection and control logic supported

Global and local device power control logic

Ten Programmable Timers: Standby / LB / LLB / APMA / APMB / Global_Display /

Primary_IDE / Secondary_IDE / SIO&Audio / Programmable IO Region

Provides system activity and display activity monitorings, including:

Video

Audio

Hard

Floppy

Serial

Parallel

Keyboard

Six programmable I/O groups

Three programmable memory spaces

Provides hot plugging events detection

Major Chipsets 2-21

2-22

CRT

AC

Docking

Eject

Setup

Hot key press

Multiple external wakeup events of Standby mode

Power

Cover

Modem

RTC

EXTSW

DRQ2

Suspend wakeup detected

Hot

Modem

RTC

Cover

Docking

Power

USB

IRQ

EJECT

ACPWR

GPIO[19:16]

Two-level battery warning monitor

Thermal alarm supported

Service Guide

Clock generator control logic supported

CPUCLK stop control

PCICLK stop control

PLL stop control

Down frequency control

L2 cache power down and PCI CLKRUN control logic supported

21 general purpose input signals, 24 general purpose output signals, 20 general purpose input/output signals

16 external expandable general purpose inputs, 16 external expandable general purpose outputs

LCD

All registers readable/restorable for proper resume from Suspend state

Built-in PCI IDE controller

Supports Ultra 33 Synchronous DMA Mode transfers up to Mode 2 Timing (33

MB/sec)

Supports PIO Modes up to Mode 5 timings, and Multiword DMA Mode 0, 1 ,2 with independent timing of up to 4 drives

Integrated 10 x 32-bit read ahead & posted write buffers for each channel (total: 20

Dwords)

Dedicated pins of ATA interface for each channel

Supports tri-state IDE signals for swap bay

USB interface

One root hub with two USB ports based on OpenHCI 1.0a specification

Supports FS (12Mbits/sec) and LS (1.5Mbits/sec) serial transfer

Supports Legacy keyboard and mouse software with USB-based keyboard and mouse

SMBus interface

System Management Bus interface which meets the v1.0 specification

External APIC interface supported

328-pin (27mm x 27mm) BGA package

Major Chipsets 2-23

2.2.2 Pin Diagram

1

2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20

A

NC AD21 AD18

CBEJ2 STOPJ

AD14 AD9 AD5 AD0

SIDED7

SIDED10

SIDED2

SIDED15

SIDEAKJ SIDECS3J

PIDED6 PIDED10

PIDED3

NC NC

B

NC AD22 AD19 AD16

DEVSELJ

AD15 AD10 AD6 AD1

PHLDJ SIDED5 SIDED12 SIDED0

SIDEIRDY SIDECS1J PIDED9

PIDED11 PIDED13 PIDED2 PIDED14

C

CBEJ3 AD23 AD20 AD17

TRDYJ

CBEJ1 AD11 AD7 AD2

PHLDAJ SIDED9 SIDED3 SIDED14 SIDEIORJ SIDEA2 PIDED5 PIDED4 PIDED1 PIDED15PIDED0

D

AD26 AD25

AD24

PCIRSTJ

IRDYJ

PAR AD12

CBEJ0

AD3

CLKRUNJ

SIDED6 SIDED11

SIDED1

SIDEIOWJ

SIDEA0 PIDED8 PIDED12 PIDEA1 PIDEA0

PIDEA2

E

AD29 AD28 AD27

AD30

FRAMEJ

SERRJ AD13

AD8

AD4

PCICLK

SIDED8

SIDED4

SIDED13

SIDEDRQ

SIDEA1

PIDED7

PIDEAKJ

PIDECS1J

PIDECS3J INTR

F

USBCLK

GPO8 AD31 INTAJ

INTBJ VCC_B VCC_D

VCC_E

PIDEIOWJ PIDEIRDY

NMI SMIJ

IGNNEJ

G

USBP0- USBP0+

GPO4

INTCJ

INTDJ VCC_B

H

J

USBP1- USBP1+

SD7

RSTDRV

GPI3 GPO3 GPO2

IOCHKJ

GPI1 GPI0

M1533

GND GND GND GND GND GND

GND GND GND GND GND GND

GND GND GND GND GND GND

GND GND GND GND GND GND

VCC_3C PIDEDRQ PIDEIORJ CPURST A20MJ

INIT

IRQ13 STPCLK

SMBDATA

SMBCLK

RI

GPO1 GPO20

GPIO19

GPIO18 GPIO17

LLBJ

DOCKJ GPIO16

GPIO15 GPIO14

K

SD5

IRQ9 SD6

MSCLK

MSDATA

L

SD3

DREQ2 SD4 KBCLK

KBDATA

M

IOCHRDY

SD0

SD1 NOWSJ SD2

IRQ8J SUSTAT1J PWRBTNJ GPIO13

GPIO12

N

IOW J SA19

SMEMRJ

AEN SMEMWJ

GND GND GND GND GND GND

GND GND GND GND GND GND

PW G

HOTKEYJ

RSMRSTJ

LBJ

LID

VDD5S SIRQI SIRQII

OSC32KII OSC32KI

OSC32KO

P

SA16

DACKJ3

SA17

IORJ

SA18 VCC_A VCC_C

GPO19

GPO18

GPO23 GPO22

GPO21

R

DREQ1

SA14

DACKJ1

SA15

DREQ3 VDD5

VCC_A

Vcc_3A

VCC_A

GPO17

GPO16

GPO15

GPO14

GPO13

T

REFSHJ

SA13 IRQ6 IRQ4

DACKJ2

BALE LA23

LA20

DACKJ0

MEMWJ

DREQ6

ROMKBCSJ

RTCAS

RTCRW IRQ1I

GPO12GPO11 GPO10 GPO9

GPO7

U

SA12 IRQ7 IRQ5 IRQ3 TC

OSC14M

IRQ10

IRQ15

LA17

DREQ5

SD10 SD12

RTCDS

XD0 XD4

EJECT

GPIO11

GPO6

GPO5 GPO0

V

SYSCLK

SA10 SA8 SA5 SA2 M16J LA22 LA19

DREQ0

SD8

DACKJ7

SD13 SPKR XD1 XD5

ACPWR

GPI6

GPIO8

GPIO9 GPI010

W SA11 SA9 SA7 SA4 SA1

SBHEJ

IRQ11

IRQ14

MEMRJ

DACKJ6

SD11 SD14

SPLED

XD2 XD6

SETUPJ

GPI4 GPI7 GPI8

NC

Y

NC NC SA6 SA3 SA0 IO16J LA21 LA18

DACKJ5

SD9

DREQ7

SD15

EXTSW

XD3 XD7

THRMJ

CRT GPI2 GPI5 NC

TOP VIEW

Figure 2-2 M1533 Pin Diagram

2-24 Service Guide

2.2.3 Pin Descriptions

Pin Name Type

Clock & Reset Unit :

PWG

PCICLK

OSC14M

OSC32KI

OSC32KII

CLK32KO

USBCLK

I-Group C

Schmitt

I-Group B

I-Group A

I-Group C

I-Group C

O-Group C

2.4/2.4 mA

I-Group B

Description

Power-Good Input. This signal comes from the power supply to indicate that power is available and stable. The de-assertion of this input will enable the leakage control circuit between Soft-off (Suspend to Disk) resume circuit and no power circuit.

PCI Clock for Internal PCI Interface. This is an input PCI clock, it should always be running at ON, STANDBY, SLEEP (Power-On Suspend) state. When

CLKRUNJ is active, this clock should always keep on running. Internal PCI state machine and ISA state machine will use this clock.

14.318Mhz Clock Input. This input clock will be used for Power Management timer, M8254 timer, SM bus base frequency and ISA state machine.

32 Khz Oscillator Input1. This is a crystal input 1 from a 32.768 KHz Quartz

Crystal. The M1533 will generate the 32 KHz clock for the internal Suspend circuit and output the clock from the CLK32KO to North Bridge DRAM Suspend

Refresh Circuit. If a crystal is not used, an external 32 Khz clock input should connect to this pin.

32 Khz Oscillator Input2. This is a crystal input 2 from a 32.768 KHz Quartz

Crystal. The M1533 will generate the 32 KHz clock for the internal Suspend circuit and output the clock from the CLK32KO to North Bridge DRAM Suspend

Refresh Circuit. If a Crystal is not used, this pin should be floated.

32 KHz Clock Output for DRAM Refresh. At ON, STANDBY, SLEEP (Power

On Suspend), SUSPEND (Suspend to DRAM) states, the output will send to

Memory controller, to support DRAM refresh clock. At Soft off and Suspend to

Disk states, the output will drive low to avoid leakage current.

48 MHz USB Clock Input. This clock will send to USB state machine to generate USB signals.

PCI Bus Interface Unit :

PCIRSTJ O-Group B

AD[31:0]

12/16 mA

I/O

CBEJ[3:0]

Group B

12/16 mA

I/O

Group B

12/16 mA

FRAMEJ

TRDYJ

IRDYJ

I/O

Group B

12/16 mA

I/O

Group B

12/16 mA

I/O

Group B

12/16 mA

PCI Bus Reset. This is an output signal to reset the entire PCI Bus. This signal will be asserted during system reset and is a logic invert of RSTDRV.

Address and Data Multiplexed Bus. During the first clock of a PCI transaction,

AD[31:0] contain a physical address. During subsequent clocks, AD[31:0] contain data.

Bus Command and Byte enable. During address phase, CBEJ[3:0] define the

Bus Command. During data phase, CBEJ[3:0] define the Byte Enables.

Cycle Frame. Cycle Frame is driven by current initiator to indicate the beginning and duration of a PCI access.

Target Ready. Target Ready indicates the target's ability to complete the current data phase of the transaction.

Initiator Ready. Initiator Ready indicates the initiator’s ability to complete the current data phase of the transaction.

Major Chipsets 2-25

STOPJ

DEVSELJ

SERRJ

PAR

PHLDAJ

PHOLDJ

INTAJ_MI

INTBJS0

INTCJS1

INTDJS2

CPU interface :

INIT

CPURST

IGNNEJ

INTR

I/O

Group B

12/16 mA

I/O

Group B

12/16 mA

I-Group B

I/O

Group B

Schmitt

4/4 mA

I/O

Group B

Schmitt

4/4 mA

I/O

Group B

Schmitt

4/4 mA

Cycle stop request. Cycle Stop indicates the target is requesting the master to stop the current transaction.

Device Select. This signal indicates that the target device has decoded the address as its own cycle. This pin is an output pin when M1533 acts as a PCI slave has decoded address as its own cycle including subtractive decoding.

I/O

Group B

12/16 mA

I-Group B

O-Group B

4/4 mA

I-Group B

System Error. This signal may be pulsed active by any agent that detects a system error condition. When SERRJ is sampling low, M1533 will assert NMI to generate non-maskable interrupt to CPU.

Parity Signal. PAR is an Even Parity and is calculated on AD[31:0] and

CBEJ[3:0]. When M1533 acts as a PCI master, it drives PAR one PCI clock after address phase for read/write transaction and one PCI clock after data phase for write transaction. When the M1533 acts as a target, it drives PAR one PCI clock after data phase for PCI master read transaction.

PCI Bus Ownership Acknowledge. When PCI bus arbiter asserts this pin,

M1533 has owned the PCI bus.

PCI Bus Ownership Request. M1533 requests the ownership of the PCI bus from the PCI bus arbiter on the North Bridge. M1533 will assert this signal on behalf of the ISA Master, DMA Device, IDE Master, and the USB Master.

PCI INTA. PCI interrupt input A or PCI interrupt polling input. M1533 can support up to 8 PCI Interrupts routing by using a 74F181 to do the polling. This pin is a multi-function pin: it is an INTAJ when 4 PCI Interrupts are supported, or connects to the 74F181 encoded output to support the 8 PCI Interrupts polling mode.

PCI INTB. PCI interrupt input B or polling select_0 output. M1533 can support up to 8 PCI Interrupts routing by using a 74F181 to do the polling. This pin is a multi-function pin: it is an INTBJ when 4 PCI Interrupts are supported, or connects to the 74F181 selection input 0 to support the 8 PCI Interrupts polling mode.

PCI INTC. PCI interrupt input C or polling select_1 output. M1533 can support up to 8 PCI Interrupts routing by using a 74F181 to do the polling. This pin is a multi-function pin: it is the INTCJ when 4 PCI Interrupts are supported, or connects to the 74F181 selection input 1 to support the 8 PCI Interrupts polling mode.

PCI INTD. PCI interrupt input D or polling select_2 output. M1533 can support up to 8 PCI Interrupts routing by using a 74F181 to do the polling. This pin is a multi-function pin: it is the INTDJ when 4 PCI Interrupts are supported, or connects to the 74F181 selection input 2 to support the 8 PCI Interrupts polling mode.

O-Group E

2.4/2.4 mA

O-Group E

2.4/2.4 mA

O-Group E

2.4/2.4 mA

O-Group E

2.4/2.4 mA

CPU Initialize Interrupt. CPU cold & warm reset. When CPU is Pentium Pro, this signal is low active. Otherwise, this signal is high active. When power on,

KBC RC, port 92 RC, shutdown all will trigger INIT active.

CPU Cold Reset. When power turn on, this reset signal will be asserted, and then will become de-asserted until 4 ms after PWG becomes high.

Ignore Error. This pin is used as the ignore numeric coprocessor error.

Interrupt Request to CPU. This is the interrupt signal generated by the internal

8259 and should connect to CPU INTR as a maskable interrupt.

2-26 Service Guide

NMI O-Group E

2.4/2.4 mA

Non-maskable Interrupt to CPU. This is generated by the ISA Parity error

(IOCHKJ assertion), PCI Parity error or DRAM Parity error (SERRJ assertion), and the other internal error event. This output should connect to CPU NMI as a non-maskable interrupt.

CPU A20 Mask. This is the CPU Address line 20 mask signal.

A20MJ O-Group E

2.4/2.4 mA

I-Group E FERRJ/

IRQ13

Floating Point Error. FERRJ input to generate IRQ13. When Coprocessor interface is disabled through configuration register Index-43h bit 6 setting, the function of this pin is IRQ13.

ISA Bus Interface Unit :

IRQ[15:14], I/O

IRQ[11:9],

IRQ[7:3]

Group A

Schmitt

RSTDRV

SD[15:8]

9.6/9.6 mA

O-Group A

12/16 mA

I/O

XD[7:0]

Group A

12/12 mA

I/O

Group A

12/12 mA

SD[7:0]/

GPIO[7:0]

I/O

Group A

12/12 mA

Interrupt Request. The Interrupt Request lines are directly from the ISA Bus, from the PCI Interrupt Routing, or from the steerable Interrupt pins. The M1533 will also drive the interrupt pins if the source is not from the ISA bus to support the APIC interface.

ISA Bus reset. This output is used to reset the ISA Bus and the system device.

This pin will be active if the system reset is needed.

ISA High Byte Slot Data Bus. These pins should connect to the ISA High Byte

Slot Data Bus.

XD Data Bus. When the SD[7:0] pins are defined as the GPIO[7:0] pins, these pins can be used to drive SD[7:0] if TTL LS245 is used as a buffer. M1533 signal XDIR will control this buffer.

ISA Low Byte Slot Data Bus or General Purpose I/O. When external SD[7:0] bus is supported by the XD[7:0] bus through a LS245 TTL, these pins are used as the GPIO pins for green control. Otherwise, these pins are SD[7:0]. No external LS245 is required.

ISA Slot Address Bus A19-A17. These pins should connect to the ISA System

Address Bus.

SA[19:17]

SA[16:0]

SBHEJ

O-Group A

12/12 mA

I/O

Group A

12/12 mA

I/O

Group A

12/12 mA

ISA Slot Address Bus A16-A0. These pins should connect to the ISA System

Address Bus.

ISA Byte High Enable. This pin should connect to the ISA System Byte High

Enable pin.

LA[23:17] I/O

Group A

ISA Bus Interface Unit :

12/12 mA

IO16J

M16J

ISA Latched Address Bus. They are inputs during ISA master cycle and should connect to ISA Slot Latch Address Bus.

I -Group A ISA 16 Bit I/O Device Indicator. This is an input and will be driven by the device if the ISA I/O cycle is a 16-bit access.

I/O ISA 16 Bit Memory Device Indicator. This pin will be driven by the device or by the M1533 if the ISA Memory cycle is a 16-bit access.

Group A

12/20 mA

Major Chipsets 2-27

MEMRJ

MEMWJ

AEN

IOCHRDY

NOWSJ

IOCHKJ

SYSCLK

BALE

I/O

Group A

12/12 mA

I/O

Group A

12/12 mA

O-Group A

12/12 mA

I/O

Group A

12/20 mA

I-Group A

I-Group A

O-Group A

12/12 mA

O-Group A

12/12 mA

ISA Memory Read. This signal is an output when the M1533 is the ISA Bus master, or an input during ISA master cycle.

ISA Memory Write. This signal is an output when the M1533 is the ISA Bus master, or an input during ISA master cycle.

ISA I/O Address Enable. This signal will become active high during DMA cycle to prevent I/O device to decode DMA cycles as valid I/O cycles.

ISA System Ready. This signal is an output during ISA master cycle, or an input when the M1533 is the ISA Bus master.

ISA Zero Wait-State for Input. This input signal will terminate the CPU to ISA command instantly.

ISA Parity Error. M1533 will generate NMI to CPU when this signal is asserted.

ISA System Clock. This output is generated by the PCI clock and is used as the ISA system clock.

Bus Address Latch Enable. BALE will be asserted throughout DMA, ISA master , and the Refresh cycles. Otherwise, it will only assert half the SYSCLK before the ISA command is asserted.

ISA I/O Read. This signal is an input during ISA master cycle, and an output when the M1533 is the ISA Bus master.

IORJ

IOWJ

SMEMRJ

SMEMWJ

DREQ[7:5],

DREQ[3:0]

DACKJ[7:5],

DACKJ[3:0]

TC

I/O

Group A

12/16 mA

I/O

Group A

12/12 mA

O-Group A

12/12 mA

O-Group A

12/12 mA

I-Group A

Schmitt

O-Group A

9.6/9.6 mA

O-Group A

12/12 mA

REFSHJ I/O

Group A

12/20 mA

Miscellaneous Logic :

SPKR O-Group A

4/4 mA

ISA I/O write. This signal is an input during ISA master cycle, and an output when the M1533 is the ISA Bus master.

ISA System Memory Read. This signal indicates that the memory read command is below 1M Byte address.

ISA System Memory Write. This signal indicates that the memory write command is below 1M Byte address.

DMA Request Signals. These are inputs from the DMA Device or ISA Master

Request. The M1533 will combine the DMA request, ISA Master request, IDE

Bus Master request, and USB Master request to generate the PHOLDJ to the

PCI Arbiter.

DMA Acknowledge Signals. After the M1533 has got the PCI Bus grant

(PHLDAJ), the internal arbiter will assert the DMA acknowledge signal to the

DMA Device Request.

DMA End of Process. This signal will be asserted after the DMA Device has ended the transaction.

ISA Refresh Cycle. This signal is an input during ISA master cycle, and an output when the M1533 is the ISA Bus master.

Speaker Output. This pin is used to control the Speaker Output and should connect to the Speaker.

2-28 Service Guide

RTCAS

RTCRW

RTCDS

SPLED

ROMKBCSJ

SERIRQ/

GPI[2]

SIRQI

SIRQII

IRQ8J

XDIR/

GPO[12]

KBINH/

IRQ1I

IRQ1O/

GPO[13]

KBCLK/

GPI[9]

KBDATA/

GPI[10]

MSCLK/

GPI[11]

O-Group A

4/4 mA

O-Group A

4/4 mA

O-Group A

4/4 mA

O-Group A

4/4 mA

O-Group A

4/4 mA

B/I

Group A

12/16 mA

I-Group A

Schmitt

I-Group A

Schmitt

I-Group C

Schmitt

RTC Address Strobe. This pin is used as the RTC Address Strobe and should connect to the RTC.

RTC Write strobe. This pin is used as the RTC Read/Write Command and should connect to the RTC. The M1533 will drive the RTC command through dedicated pin instead of the 74F32 decode to save the system cost.

RTC Data Strobe. This pin is used as the RTC Data Strobe and should connect to the RTC.

Speed LED Output. This pin is used to control the Speed LED Output and should connect to LED.

ROM/Keyboard Chip Select. This pin is the ROM chip select and is the

Keyboard chip select also when internal KBC is disabled.

Serial Interrupt Request or General Purpose Input. This pin is used to support the serial interrupt protocol or as a General Purpose Input.

O-Group A

4/4 mA

I/O

Group A

Schmitt

12/24 mA

O-Group A

4/4 mA

I/O

Group A

Schmitt

12/24 mA

I/O

Group A

Schmitt

12/24 mA

I/O

Group A

Schmitt

12/24 mA

Steerable IRQ Input1. This is a steerable Interrupt input, M1533 will provide a

Routing Mechanism to route this Interrupt to any 8259 input.

Steerable IRQ Input2. This is a steerable Interrupt input, M1533 will provide a

Routing Mechanism to route this Interrupt to any 8259 input.

RTC Interrupt Input. This is the RTC Interrupt input. This pin belongs to the

Power Group C, and it can support the RTC Alarm function during Soft-off or

Suspend state.

XD Bus Direction Control or General Purpose Output. When external XD bus is designed on motherboard, this pin is X-bus direction control. Otherwise, this pin is a general purpose output.

Keyboard Inhibit or Interrupt One Input. This pin will be the Keyboard Inhibit input when internal KBC is enabled. Otherwise, it will be the IRQ1 input.

IRQ1 Output or General Purpose Output. When both external APIC and internal KBC are enabled, this pin is IRQ1 output. Otherwise, it is a general purpose output.

Keyboard Clock or General Purpose Input. This pin is the Keyboard interface

Clock when internal KBC is enabled. Otherwise, it is a general purpose input.

Keyboard data or General Purpose Input. KB interface DATA output when internal KBC is enabled. Otherwise, this pin is a general purpose input.

Mouse Clock or General Purpose Input. Mouse clock output when internal PS2

Keyboard is enabled. Otherwise, this pin is a general purpose input.

Major Chipsets 2-29

MSDATA/

IRQ12I

IRQ12O/

GPO[14]

IRQ0/

GPO[15]

APICREQJ/

GPI[8]

APICCSJ/

GPO[16]

APICGNTJ/

GPO[17]

BIOSA17/

GPO[19]

BIOSA16/

GPO[18]

PCSJ/

GPO[0]

IDE interface :

PIDE_DRQ

SIDE_DRQ

PIDE_AKJ

SIDE_AKJ

PIDE_RDY

SIDE_RDY

PIDEIORJ

SIDEIORJ

I/O

Group A

Schmitt

12/24 mA

O-Group A

4/4 mA

Mouse Data or Interrupt Line 12 Input. Mouse data output when internal PS2

Keyboard is enabled. Otherwise, this pin is the IRQ12 input.

O-Group A

4/4 mA

Interrupt Line 12 Output or General Purpose Output. When both external APIC and internal KBC are enabled, this pin is IRQ12 output. Otherwise, this pin is a general purpose output.

Interrupt Line 0 Output or General Purpose Output. This pin is the Interrupt request 0 output when external APIC mode is enabled. Otherwise this pin is a general purpose output.

I -Group A APIC Request Input or General Input. This pin connects to the APIC Chip

Request Line when external APIC mode is enabled. Otherwise, this pin is a general purpose input.

O-Group A

4/4 mA

O-Group A

4/4 mA

O-Group A

4/4 mA

O-Group A

4/4 mA

APIC Chip Select or General Purpose Output. This pin connects to the APIC

Chip Select Line when external APIC mode is enabled. Otherwise, this pin is a general purpose output.

APIC Grant Output or General Purpose Output. This pin connects to the APIC

Chip Grant Line when external APIC mode is enabled. Otherwise, this pin is a general purpose output.

ROM Address 17 or General Purpose Output. This pin is the ROM A17 control when 2M ROM is used, or it is a general purpose output.

ROM Address 17 or General Purpose Output. This pin is the ROM A16 control when 2M ROM is used, or it is a general purpose output.

O-Group A

4/4 mA

Programmable Chip Select or General Purpose Output. This pin can be selected as a Programmable Chip Select, or as a general purpose output.

I-Group D

I-Group D

O-Group D

9.6/9.6 mA

O-Group D

9.6/9.6 mA

I-Group D

I-Group D

O-Group D

12/12 mA

O-Group D

12/12 mA

Primary IDE DMA Request for IDE Master. This is the input pin from the

Primary Channel IDE DMA request to do the IDE Master Transfer.

Secondary IDE DMA Request for IDE Master. This is the input pin from the

Secondary Channel IDE DMA request to do the IDE Master Transfer.

Primary IDE DACKJ for IDE Master. This is the output pin to grant the Primary

Channel IDE DMA request to begin the IDE Master Transfer.

Secondary IDE DACKJ for IDE Master. This is the output pin to grant the

Secondary Channel IDE DMA request to begin the IDE Master Transfer.

Primary IDE Ready. This is the input pin from the Primary IDE Channel to indicate the IDE device is ready to terminate the IDE command. The IDE device can de-assert this input (logic 0) to expand the IDE command if the device is not ready.

Secondary IDE Ready. This is the input pin from the Secondary IDE Channel to indicate the IDE device is ready to terminate the IDE command. The IDE device can de-assert this input (logic 0) to expand the IDE command if the device is not ready.

Primary IDE IORJ Command. This is the IORJ command output pin to notify the Primary IDE device to assert the Read Data.

Secondary IDE IORJ Command. This is the IORJ command output pin to notify the Secondary IDE device to assert the Read Data.

2-30 Service Guide

PIDEIOWJ

SIDEIOWJ

PIDECS1J

PIDECS3J

SIDECS1J

SIDECS3J

PIDE_A[2:0]

SIDE_A[2:0]

PIDE_D[15:0]

SIDE_D[15:0]

O-Group D

9.6/9.6 mA

O-Group D

9.6/9.6 mA

I/O

Group D

9.6/9.6 mA

I/O

Group D

9.6/9.6 mA

Power Management Unit :

RSM_RSTJ I-Group C

SMIJ

Schmitt

O-Group E

4/4 mA

STPCLKJ

SLEEPJ/

GPO[20]

ZZ/

GPO[1]

O-Group E

4/4 mA

O-Group E

4/4 mA

O-Group E

4/4 mA

CLKRUNJ

CPU_STPJ/

GPO[2]

PCI_STPJ/

GPO[3]

O-Group D

12/12 mA

O-Group D

12/12 mA

O-Group D

9.6/9.6 mA

O-Group D

9.6/9.6 mA

O-Group D

9.6/9.6 mA

O-Group D

9.6/9.6 mA

I/O - Group

B

12/16 mA

O-Group B

4/4 mA

O-Group B

4/4 mA

Primary IDE IOWJ Command. This is the IOWJ command output pin to notify the Primary IDE device that the available Write Data is already asserted by

M1533.

Secondary IDE IOWJ Command. This is the IOWJ command output pin to notify the Secondary IDE device that the available Write Data is already asserted by M1533.

IDE Chip Select 1 for Secondary Channel 0. This is the Chip Select 1 command output pin to enable the Primary IDE device to watch the Read/Write

Command.

IDE Chip Select 3 for Secondary Channel 1. This is the Chip Select 3 command output pin to enable the Primary IDE device to watch the Read/Write

Command.

IDE Chip Select 1 for Primary Channel 0. This is the Chip Select 1 command output pin to enable the Secondary IDE device to watch the Read/Write

Command.

IDE Chip Select 3 for Primary Channel 1. This is the Chip Select 3 command output pin to enable the Secondary IDE device to watch the Read/Write

Command.

Primary IDE ATA Address Bus. These are the Address pins connected to

Primary Channel.

Secondary IDE ATA Address Bus. These are the Address pins connected to

Secondary Channel.

Primary IDE ATA Data Bus. These are the Data pins connected to Primary

Channel.

Secondary IDE ATA Data Bus. These are the Data pins connected to

Secondary Channel.

Resume Circuit Initial Reset Input. This input is used to initialize the resume circuit.

SMM Interrupt Output. This output should be connected to CPU SMM Interrupt input.

Stop CPU Internal Clock Output. This output is used to stop the CPU internal clock and should be connected to CPU STPCLKJ input.

Pentium PRO Sleep State or General Purpose Output. This output will force

Pentium PRO CPU to enter Sleep State, or as a general purpose output.

PBSRAM Power Saving Mode or General Purpose Output. This output is used to control L2 cache entering power saving mode, or as a general purpose output.

PCI Clock Stop Message Control. This pin is used to support PCI Clock Run function.

Clock Cell CPU Clock Stop or General Purpose Output. This output is used to stop the CPU Clock of the clock generator, or as a general purpose output.

Clock Cell PCI Clock Stop or General Purpose Output. This output is used to stop the PCI Clock of the clock generator, or as a general purpose output.

Major Chipsets 2-31

SUSTAT1J

SLOWDWN/

GPO[4]

AMSTATJ/

GPO[8]

PWRBTNJ

PCIREQJ/

GPI[3]

POSSTA/

GPI[4]

SQWO/

GPO[9]

OFF_PWR0/

GPO[21]

OFF_PWR1/

GPO[22]

OFF_PWR2/

GPO[23]

RI

LBJ

LLBJ

EXTSW

THRMJ

ACPWR

CRT

SETUPJ

2-32

O-Group C

4/4 mA

O-Group B

4/4 mA

Suspend Status for North Bridge. This output is used to notice the north bridge to control DRAM suspend refresh circuit.

Slow Down the Clock Generator Output or General Purpose Output. This output is used to control the Clock Generator to slow down the clock output, or as a general purpose output.

O-Group B

4/4 mA

I-Group C

Schmitt

APM State Control. It is asserted when HALT or STPGNT cycle is detected.

Power Button Input. This input is used to support the ACPI Power Button function.

I-Group B PCI Bus Request Event Input or General Purpose Input. This input comes from the North Bridge or external circuit to notice M1533 there is PCI request pending. This pin can also be programmed as a general purpose input.

I -Group A Force M1533 into Suspend Mode or General Purpose Input. This input can be used to force M1533 entering suspend mode, or as a general purpose input.

O-Group A

4/4 mA

O-Group C

4/4 mA

O-Group C

4/4 mA

O-Group C

4/4 mA

I -Group C

Schmitt

I -Group C

Schmitt

Square Wave Output or General Purpose Output. This output can be used to output Square Wave with 1Hz or 2Hz, or as a general purpose output.

Remove Clock Generator Power Control or General Purpose Output. This output can be used to remove the Clock Generator Power, or as a general purpose output.

Remove All Circuit Power Except Internal Suspend Circuit and External DRAM or General Purpose Output.

Remove All Circuit Power Except Internal Suspend Circuit or General Purpose

Output.

Ring-in or General Purpose Input. This input connects to Modem Ring-in input to support ACPI Ring-in function, or as a general purpose input.

I -Group C

Schmitt

I -Group A

Schmitt

I -Group A

Schmitt

I - Group A

Schmitt

First Battery Low Indication Input or General Purpose Input. This input can be used as the first stage battery low level indication, or as a general purpose input signal.

Last Battery Low Indication Input or General Purpose Input. This input can be used as the last battery low level indication, or as a general purpose input signal.

External Switch Event or General Purpose Input. EXTSW is a triggered input to the M1533 showing that an external device is requesting the system to enter power management mode. This signal also can be used optionally as a general purpose input signal.

Thermal Event Input or General Purpose Input. THRMJ is a triggered input to the M1533 showing that the external thermal detected circuits are requesting the system to enter power management mode. This signal also can be used optionally as a general purpose input signal.

Detect AC Adapter Plug-in or General Purpose Input. This is a triggered input showing that the AC adapter is plugged in or plugged out event. This triggered event can be used as a system management (or control ) interrupt source.

This signal also can be used optionally as a general purpose input signal.

I -Group A

Schmitt

Detect CRT Connector Plug-in or General Purpose Input. This signal represents whether the external CRT connector is plugged in/ plugged out, or used as a general purpose input.

I -Group A Setup Switch Input or General Purpose Input. This signal can be used as a setup switch triggered input for generating the power management interrupt event, or as a general purpose input signal.

Service Guide

EJECT

LID

HOTKEYJ

DOCKJ

VCSJ/

GPI[5]

FPVEE/

GPI[6]

CCFT/

GPO[5]

DISPLAY/

GPO[6]

CONTRAST/

GPO[7]

GPIORBJ/

GPO[10]

GPIOWB/

GPO[11]

GPIO[19:16]

GPIO[15:12]/

BATSEL[3:0]

GPIO[11:8]

USB interface :

USBP0+

USBP0-

I/O

Group C

Schmitt

4/4 mA

I/O

Group C

Schmitt

4/4 mA

I/O

Group A

Schmitt

4/4 mA

I -Group A External Eject SMIJ Trigger or General Purpose Input. This triggered input is used as an eject (undocking) event indicator, or as a general purpose input signal.

I -Group C Cover Switch Input or General Purpose Input. This signal is used to indicate if the system’s lid is open or closed, or as a general purpose input.

I -Group C

Schmitt

Hot Key Press Event Input or General Purpose Input. This input signal is used to indicate a hot key press event occurred or not, or as a general purpose input.

I-Group C

I-Group A

Docking Insert Event Input or General Purpose Input. This triggered input is used as a docking event indicator, or as a general purpose input signal.

VGA Activity Event Input or General Purpose Input. The VGA chip should set this signal to active low when an VGA memory access occurred. This active signal is used by the M1533 to reload the VGA monitor timer or to generate a system management event. This signal also can be used as a general purpose input.

I-Group A LCD Back Light VEE Input or General Purpose Input. This signal is used by the M1533 to generate DISPLAY and a programmable CCFT signals. This signal also can be used as a general purpose input.

O-Group A

4/4 mA

O-Group A

4/4 mA

O-Group A

4/4 mA

O-Group A

4/4 mA

O-Group A

4/4 mA

Back Light Control or General Purpose Output. This signal can be programmed to be a periodical wave controlled by the FPVEE signal or kept to static low level. This signal also can be used as a general purpose output.

LCD Display On/Off Control or General Purpose Output. This signal can be programmed to be a response controlled by the FPVEE signal, or it can also be used as general purpose output.

LCD Contrast Control or General Purpose Output. It is a 1KHz signal with programmable duty cycle and can be used to control LCD contrast. It can also be a general purpose output.

Input Event Latching into External Buffers Command or General Purpose

Output. This signal can be used as an external buffer(s) latching command for extended general inputs, or as a normal general purpose output signal.

Output Control Signal Latching into External Buffers Command or General

Purpose Output. This signal can be used as an external buffer(s) latching command for extended general outputs, or as a normal general purpose output signal.

General Purpose I/O Pins for Resume from Suspend Mode. These signals can be programmed as the inputs or outputs for the resume triggered events from the suspend mode.

General Purpose I/O Pins or SM Bus Battery Select. These signals can be used as the general purpose I/O pins, or as the external SMB battery select control signals.

General Purpose I/O Pins for Wake-up from Stand-by Mode. These signals can be programmed as the inputs or outputs for the wake-up triggered events from the standby mode.

I/O

Group B

Universal Serial Bus Port 0. These are the serial data pair for USB Port 0.

Major Chipsets 2-33

USBP1+

USBP1-

OVCRJ[1:0]/

GPI[1:0]

SM Bus signal :

SMBEVENTJ/

GPI[7]

SMBCLK

SMBDATA

Power Pins :

VCC_A

VCC_3A

VCC_B

VCC_C

VCC_3C

VCC_D

VCC_E

VDD_5

VDD_5S

Vss or Gnd

I/O

Group B

Universal Serial Bus Port 1. These are the serial data pair for USB Port 1.

I -Group B Over Current Detect Inputs or General Purpose Inputs. These two pins are used to monitor the USB Power Over Current, or as two general purpose inputs.

P

P

P

P

P

I-Group A

Schmitt

I/O-Group C

Schmitt

9.6/9.6 mA

I/O-Group C

Schmitt

9.6/9.6 mA

SM Bus Resume Event or General Purpose Input. This signal can be used as the SM Bus resume event indicator, or as a general purpose input.

SM Bus Clock. SM Bus clock signal should be combined with SM Bus data to carry information between the devices connected to the SM Bus.

SM Bus Data Line. SM Bus data signal should be combined with SM Bus clock to carry information between the devices connected to the SM Bus.

P

P

P

P

P

Vcc 3.3V or 5V for Power Group A. This power is used for ISA interface. If this power connects to 3.3V, the relative signals will output 3.3V and accept 5V input tolerance. If this power connects to 5V, the relative signals will output 5V

TTL and accept TTL input.

Vcc 3.3V for Power Group A. This power is used for ISA interface. If Vcc_A is selected as 3.3V, this power pin connects with Vcc_A to 3.3V power plane. If

Vcc_A is selected as 5V, this power pin should connect to 3.3V power plane to save power consumption.

Vcc 3.3V for Power Group B. This power is used for PCI interface. It must be connected to 3.3V. The relative signals will output 3.3V and 5V input tolerance.

Vcc 3.3V or 5V for Power Group C. This power is used for resume/ suspend control interface signals during normal operation and suspend periods. If this power is connected to 3.3V, the relative signals will output 3.3V and accept 5V input tolerance. If this power is connected to 5V, the relative signals will output

5V TTL and accept TTL input.

Vcc 3.3V for Power Group C. This power is used for Resume/Suspend Control interface. If Vcc_C is selected as 3.3V, this power pin connects with Vcc_C to

3.3V power plane. If Vcc_C is selected as 5V, this power pin should connect to

3.3V power plane to save power consumption.

Vcc 3.3V or 5V for Power Group D. This power is used for IDE interface. If this power is connected to 3.3V, the relative signals will output 3.3V and accept 5V input tolerance. If this power is connected to 5V, the relative signals will output

5V TTL and accept TTL input.

Vcc 3.3V or 2.5V for Power Group E. This power is used for CPU interface. If this power connects to 3.3V, the relative signals will output 3.3V and accept

3.3V input. If this power connects to 2.5V, the relative signals will output 2.5V

and accept 2.5V input.

Vcc 5.0V for core Power. It supplies the core power for the internal circuit except the suspend circuit.

Vcc 5.0V for Suspend/Resume Core Power. It supplies the core power for the internal suspend/resume circuit.

Ground.

2-34 Service Guide

2.2.4 Numerical Pin List

Pin

Name

PIDED6

PIDED10

PIDED3

--

--

--

AD22

AD19

AD16

DEVSELJ

AD15

AD10

AD6

AD1

PHOLDJ

SIDED5

--

AD21

AD18

CBEJ2

STOPJ

AD14

AD9

AD5

AD0

SIDED7

SIDED10

SIDED2

SIDED15

SIDEAKJ

SIDECS3J

SIDED12

SIDED0

SIDERDY

SIDECS1J

PIDED9

PIDED11

Pin

No.

B4

B5

B6

B7

B8

B9

B10

B11

A16

A17

A18

A19

A20

B1

B2

B3

B12

B13

B14

B15

B16

B17

A8

A9

A10

A11

A12

A13

A14

A15

A4

A5

A6

A7

A1

A2

A3

Pin

Type

I/O

I/O

O

I/O

I/O

I/O

I/O

I/O

-

-

I/O

I/O

I/O

I/O

-

I/O

I/O

I/O

I

O

I/O

I/O

I/O

I/O

O

O

I/O

I/O

I/O

I/O

--

I/O

I/O

I/O

I/O

I/O

I/O

Major Chipsets 2-35

Pin

Name

SIDEIORJ

SIDEA2

PIDED5

PIDED4

PIDED1

PIDED15

PIDED0

AD26

AD25

AD24

PCIRSTJ

IRDYJ

PAR

AD12

CBEJ0

AD3

PIDED13

PIDED2

PIDED14

CBEJ3

AD23

AD20

AD17

TRDYJ

CBEJ1

AD11

AD7

AD2

PHLDAJ

SIDED9

SIDED3

SIDED14

CLKRUNJ

SIDED6

SIDED11

SIDED1

SIDEIOWJ

SIDEA0

PIDED8

Pin

No.

D6

D7

D8

D9

D2

D3

D4

D5

C14

C15

C16

C17

C18

C19

C20

D1

D10

D11

D12

D13

D14

D15

D16

C6

C7

C8

C9

C10

C11

C12

C13

C2

C3

C4

C5

B18

B19

B20

C1

Pin

Type

I/O

I/O

I/O

I/O

I/O

I/O

O

I/O

I/O

I/O

I/O

I/O

O

O

I/O

I/O

I/O

I/O

I/O

I/O

O

O

I/O

I

I/O

I/O

I/O

I/O

I/O

I/O

I/O

I/O

I/O

I/O

I/O

I/O

I/O

I/O

I/O

2-36 Service Guide

Pin

Type

P

P

I

I/O

I

O

O

I/O

I/O

O

O

O

I/O

I/O

I

O

P

O

I

O

O

O

I/O

I

I/O

I/O

I/O

I

I/O

Type

I/O

I/O

I/O

I/O

I/O

I/O

O

O

O

Pin

No.

Pin

Name

F4

F5

F6

F14

E20

F1

F2

F3

E12

E13

E14

E15

E16

E17

E18

E19

F15

F16

F17

F18

F19

F20

G1

E1

E2

E3

E4

D17

D18

D19

D20

PIDED12

PIDEA1

PIDEA0

PIDEA2

AD29

AD28

AD27

AD30

E5

E6

E7

E8

FRAMEJ

SERRJ

AD13

AD8

E9

E10

AD4

PCICLK

Pin no.

Pin name

E11 SIDED8

VCC

PIDEIOWJ

PIDERDY

NMI

SMIJ

IGNNEJ

USBP0-

SIDED4

SIDED13

SIDEDRQ

SIDEA1

PIDED7

PIDEAKJ

PIDECS1J

PIDECS3J

INTR

USBCLK

GPO8

AD31

INTAJ

INTBJ

VCC

VCC

Major Chipsets 2-37

Pin

Name

GND

GND

GND

GND

GND

GND

GPO1

GND

GND

GND

GND

GND

GND

IRQ13

STPCLK

SMBDATA

SMBCLK

RI

SD7

RSTDRV

IOCHKJ

GPI1

GPI0

USBP0+

GPO4

INTCJ

INTDJ

VCC

VCC

PIDEDRQ

PIDEIORJ

CPURST

A20MJ

INIT

USBP1-

USBP1+

GPI3

GPO3

GPO2

Pin

No.

J2

J3

J4

J5

H18

H19

H20

J1

H8

H9

H10

H11

H12

H13

H16

H17

J8

J9

J10

J11

J12

J13

J16

H2

H3

H4

H5

G18

G19

G20

H1

G2

G3

G4

G5

G6

G15

G16

G17

Pin

Type

I

I

O

I/O

I/O

I/O

I

I/O

P

P

I/O

O

P

P

P

P

P

P

O

P

P

P

P

I

I/O

O

O

O

O

O

I/O

P

P

I

O

I/O

O

I/O

I/O

2-38 Service Guide

Pin

Name

DOCKJ

GPIO16

GPIO15

GPIO14

SD3

DREQ2

SD4

KBCLK

KBDATA

GND

GND

GND

GND

GND

GND

IRQ8J

GPO20

GPIO19

GPIO18

GPIO17

SD5

IRQ9

SD6

MSCLK

MSDATA

GND

GND

GND

GND

GND

GND

LLBJ

SUSTAT1J

PWRBTNJ

GPIO13

GPIO12

IOCHRDY

SD0

SD1

Pin

No.

L11

L12

L13

L16

L5

L8

L9

L10

L1

L2

L3

L4

K17

K18

K19

K20

L17

L18

L19

L20

M1

M2

M3

K5

K8

K9

K10

K11

K12

K13

K16

K1

K2

K3

K4

J17

J18

J19

J20

Pin

Type

I

P

P

P

P

P

I/O

P

I

I/O

I/O

I/O

I

I/O

I/O

I/O

I

O

I/O

I/O

I/O

I/O

I/O

I

P

P

P

P

P

I/O

P

I/O

I/O

I/O

O

O

I/O

I/O

I/O

Major Chipsets 2-39

Pin

Name

AEN

SMEMWJ

GND

GND

GND

GND

GND

GND

VDD5S

SIRQI

SIRQII

OSC32KII

OSC32KI

OSC32KO

SA16

DACKJ3

NOWSJ

SD2

GND

GND

GND

GND

GND

GND

PWG

HOTKEYJ

RSMRSTJ

LBJ

LID

IOWJ

SA19

SMEMRJ

SA17

IORJ

SA18

VCC

VCC

GPO19

GPO18

Pin

No.

N15

N16

N17

N18

N19

N20

P1

P2

N4

N5

N8

N9

N10

N11

N12

N13

P3

P4

P5

P6

P15

P16

P17

M16

M17

M18

M19

M20

N1

N2

N3

M4

M5

M8

M9

M10

M11

M12

M13

Pin

Type

I

O

I/O

O

I

I

I

P

P

P

P

P

P

P

O

O

P

O

O

O

I/O

O

P

I

I/O

O

O

I

I

I

I

P

P

P

P

P

P

I

I/O

2-40 Service Guide

Pin

Name

Pin

Type

VDD5

VCC

VCC

VCC

GPO17

GPO16

GPO15

GPO14

GPO23

GPO22

GPO21

DREQ1

SA14

DACKJ1

SA15

DREQ3

GPO13

REFSHJ

SA13

IRQ6

IRQ4

DACKJ2

BALE

LA23

LA20

DACKJ0

MEMWJ

DREQ6

ROMKBCSJ O

RTCAS O

RTCRW

IRQ1I

O

I/O

I/O

O

I

I/O

I/O

O

O

I/O

O

I/O

I/O

I/O

GPO12

GPO11

GPO10

GPO9

GPO7

SA12

IRQ7

O

O

O

O

O

I/O

I/O

O

O

O

O

P

P

P

P

I/O

O

I

I/O

O

O

I

O

Pin

No.

T12

T13

T14

T15

T8

T9

T10

T11

T4

T5

T6

T7

R20

T1

T2

T3

T16

T17

T18

T19

T20

U1

U2

R6

R7

R14

R15

R16

R17

R18

R19

R2

R3

R4

R5

P18

P19

P20

R1

Major Chipsets 2-41

Pin

Name

GPO5

GPO0

SYSCLK

SA10

SA8

SA5

SA2

M16J

LA22

LA19

DREQ0

SD8

DACKJ7

SD13

SPKR

XD1

SD10

SD12

RTCDS

XD0

XD4

EJECT

GPIO11

GPO6

IRQ5

IRQ3

TC

OSC14M

IRQ10

IRQ15

LA17

DREQ5

XD5

ACPWR

GPI6

GPIO8

GPIO9

GPIO10

SA11

Pin

No.

V7

V8

V9

V10

V11

V12

V13

V14

V3

V4

V5

V6

U19

U20

V1

V2

V15

V16

V17

V18

V19

V20

W1

U11

U12

U13

U14

U15

U16

U17

U18

U3

U4

U5

U6

U7

U8

U9

U10

Pin

Type

O

I/O

O

I/O

I/O

I/O

I

I/O

I/O

I/O

I/O

I/O

O

O

O

I/O

I

I/O

I

I/O

I/O

I/O

I/O

I

I/O

I/O

O

I/O

I/O

O

I/O

I/O

I/O

I

I/O

I/O

I/O

I

O

2-42 Service Guide

Pin

Name

--

--

GPI7

GPI8

--

SA6

SA3

SA0

IO16J

LA21

LA18

DACKJ5

SD9

DREQ7

SD15

EXTSW

SA9

SA7

SA4

SA1

SBHEJ

IRQ11

IRQ14

MEMRJ

DACKJ6

SD11

SD14

SPLED

XD2

XD6

SETUPJ

GPI4

XD3

XD7

THRMJ

CRT

GPI2

GPI5

--

Pin

No.

Y6

Y7

Y8

Y9

Y10

Y11

Y12

Y13

Y2

Y3

Y4

Y5

W18

W19

W20

Y1

Y14

Y15

Y16

Y17

Y18

Y19

Y20

W10

W11

W12

W13

W14

W15

W16

W17

W6

W7

W8

W9

W2

W3

W4

W5

Pin

Type

I

I/O

I

I/O

I

I/O

I/O

O

-

I/O

I/O

I/O

-

-

I

I

I

I

-

I

I

I/O

I/O

I

I

I/O

I/O

O

I/O

I/O

O

I/O

I/O

I/O

I/O

I/O

I/O

I/O

I/O

Major Chipsets 2-43

2-44 Service Guide

2.3. ATI 264GT

The mach64 3D RAGE™ (also known as the GT) is a 208-pin VLSI video graphics controller chip with built-in 3D coprocessor, GUI coprocessor, video scaler, color space converter, true-color palette DAC, and dual-clock synthesizer. This controller is 100% register-compatible with the IBM

VGA display adapter.

The GT supports synchronous graphics memory chips SDRAM/SGRAM. When combined with the

64-bit memory interface and memory clocks up to 63 MHz, the available bandwidth can reach

800 MB/sec. This increase in memory bandwidth allows for greater display resolutions and uncompromising video playback capabilities. The GT also supports DRAM and EDO DRAM.

Both footprint and pinout of the GT are backward compatible with the ATI-264CT (CT) and

ATI-264VT (VT).

2.3.1 Features

2.3.1.1 3D Accelerator

Complete 3D primitives - Points, Lines, Triangles, Trapezoids, and Rectangles

Full-screen or window double buffering for smooth animation

Flat and Gouraud shading

Dithering down from 24 bits per pixel (bpp) to 8 or 16 bpp 3D engine for smaller memory foot print

Texture mapping

Hardware perspective correction

Sub-pixel

Mip-mapping

Bi-linear and tri-linear filtering

Texture maps up to 1024 x 1024

Non-square texture maps

Alpha in texture map

Video textures using YUV format

3D effects

Alpha blending and alpha interpolation

Fogging and fog interpolation

Major Chipsets 2-45

Texture lighting modes

3D modes

ARGB32

ARGB16

RGB16

RGB8

Y8 grey scale

ARGB16

YUV444,

2.3.1.2 2D Accelerator

Hardware acceleration - Rectangle Fill, Line Draw, BitBlt, Polygon Fill, Panning/Scrolling, Bit

Masking, Monochrome Expansion, Scissoring, and full ROP support

Hardware cursor up to 64 x 64 x 2

Acceleration provided in 4/8/16/24/32-bpp modes. Packed pixel support (24 bpp) enables true color in 1-MB configuration

Game acceleration for Microsoft’s DirectDraw-Double Buffering, Virtual Sprites, Transparent

Blit, Masked Blit, and Context Chaining

2.3.1.3 Video Accelerator

Filtered horizontal and vertical scalers for TV-quality, full-screen video playback

Integrated video line buffers support filtered video scaling

Color interpolation during scaling for improved high resolution video quality

YUV to RGB color space conversion with support for both packed and planar

Graphics and video keying for effective overlay of video and graphics

AMC supports I

2

C interface for special applications (i.e., video tuner control)

Supports ATI Media Channel (AMC) 1.0 for additional video expansion capabilities

Support for 26-pin VESA compatible VGA Feature Connector (VFC) with a 1024 x 768 maximum resolution capability

2-46 Service Guide

2.3.1.4 General Features

First graphics controller to integrate 3D, 2D, and Video accelerators with palette DAC and dual-clock synthesizer in a single chip

24-bit, true-color palette DAC

Supports pixel clock rates to 1280 x 1024 resolution at 75-Hz refresh

Gamma correction for true WYSIWYG color

Full 24-bit palette

PCI Revision 2.0 bus for Plug-and-Play ease of use

Bi-endian support for compliance on a variety of processor platforms

32-level command FIFO assures fast response to host command transfers for maximum

CPU/host bus/controller efficiency and concurrent operation

Software interface including:

Programmable flat- or paged-memory model with enhanced host access to a linear frame buffer

32-bit wide read/writable memory mapped registers with optimized organization to reduce instruction overhead and raises performance

DDCI and DDC2B Plug-and-Play monitor support

Power management for full-VESA Display Power Management Signaling (DPMS) and EPA

Energy Star compliance. Also, register support for controller power reduction and DAC power down

Optional EEPROM for storing user-selectable configurations

Single-chip solution in 208-pin PQFP package, 0.511m, mixed 3.3V/5.0V

Supports Fast Page Mode DRAM and EDO DRAM at up to 63 MHz memory clock across a

64-bit memory interface

3D driver support

Microsoft Direct 3D including support for Reality Lab and OpenGL

Apple QuickDraw 3D and TinselTown 3D interface

ATI 3D RAGE DOS and Windows API

Intel

Easy-to-use Windows utilities

Major Chipsets 2-47

2.3.2 Block Diagrams

Figure 2-3 ATI 264GT Block Diagrams

2-48 Service Guide

2.3.3 Pin Diagram

Figure 2-4 ATI 264GT Pin Diagram

Major Chipsets 2-49

2.3.4 Signal Descriptions

Table 2- 2 Signal Type Definitions

Signal Type

O

1/0

Pwr

Gnd

A

#

Output pin

Bidirectional pin

Power pin

Ground pin

Analog pins

Active-low signal

Definition

Table 2- 3 ATI 264GT Signal Descriptions

Signal Pin Type Description

PCI Bus Interface Implementation (for 5V PCI interface support)

AD[31 :0]

C/BE#[3:0]

143:150,

153:154,

158:163,

174:181,

185:192

151,164,

173,184

I/O

I

Multiplexed-System Address or Data bits [31:0]

Multiplexed-Bus Command or Byte Enable bits 3:0. (BE# is active low)

CPUCLK

DEVSEL#

142

169

I

O

FRAME#

IDSEL

165

152 I

I

Bus Clock

Device Select indicates that the controller has decoded its address.

Frame is driven by the current bus master to indicate the beginning and duration of an access.

Initialization Device Select is used as a chip select during configuration read and write transactions.

INTR#

IRDY#

140

166

O

I

PAR

RESET#

STOP#

TRDY#

172

141

171

167

O

I

O

O

Interrupt Request-Level is triggered active low by default

Initiator Ready indicates that the bus master is able to complete the current data phase of the transaction

Parity. Even parity used

Bus Reset

Stop indicates the current target is requesting the master to stop the current transaction.

Target Ready indicates that the target agent is able to complete the current data phase of the transaction.

Signal Pin

Memory Interface

CAS#/WE#0 29

CS#3/WE#1 28

MA[9:0] 204:198, 196,

194:193

Type

O

O

O

Description

Write Strobe of the first and second MB of memory

Write Strobe of the third and fourth MB of memory

Memory Address bits 9:0

2-50 Service Guide

Table 2- 3

MD[31 :0]

MD[63:32]

OE#0

OE#1

RAS#0

CS#2

ATI 264GT Signal Descriptions

55:54, 50:40,

38, 36:30,

24:14,

92:90, 88:80,

77:65, 63, 61:56

205

207

3

206

I/O

I/O

O

O

O

O

Memory Data bits 31:0 of the first and third MB of memory

Memory Data bits 63:32 of the second and fourth MB of memory.

Output Enable of the first and second MB of memory

Output Enable of the third and fourth MB of memory

Row Address Strobe of the first and second MB of memory

Row Address Strobe of the third and fourth MB of memory

Column Address Strobe WE#[7:0] 4:9,11, 13 I/O

SDRAM Memory 128KBx16x2, and x32x2

CAS#/WE#

[1 :0]

MA[9:0]

28,29 O

O

MD[63:0]

OE#1

204:198,

196,194, 193

92:90, 88:80,

77:65, 63, 61

:54, 50:40, 38,

36:30, 24:14

205

I/O

O

OE#0

RAS#[1:0]

WE#[7:0]

207

3, 206

4:9,11, 13

O

O

O

DAC and Monitor Interface

R

G

120

121

B

COMP

HSYNC

VSYNC

RSET

VREF

122

124

129

128

123

125

Frequency Synthesizer Interface

MLOOP

PLOOP

XTALIN*

XTALOUT*

111

114

102

103

A

A

A

A

A

A

A

A

O

O

A

A

CAS[1:0]

MA[9:0]

AD[63:0]

WE# Command

MCLK

RAS[1:0]

DQM[7:0]

Red analog pixel data output to monitor

Green analog pixel data output to monitor

Blue analog pixel data output to monitor

Compensation pin for the DAC

Horizontal sync

Vertical sync

Current setting resistor for the DAC

DAC reference voltage

Memory Clock Loop filter

Pixel Clock Loop filter

14.31818-MHz crystal or TTL oscillator connection

14.31818-MHz crystal connection

*

For designs using external clock source (instead of a crystal): the input XTALIN is CMOS inverter with

Cjn = 0.5pF, and XTALOUT is not connected.

Major Chipsets 2-51

Table 2- 3 ATI 264GT Signal Descriptions

Optional ATI Media Channel Interface

BLANK# 135 0

DCLK

EDCLK

ESYNC

134

107

133

0

I

I

EVIDEO

PIXEL[7:0]

SA#

137

MASKO

132

93:100

117

25

I

0

I/O

I/O

I/O

Optional EEPROM Interface

Gl01

Gl02

Gl03

MD [46:32]

MD [63:56]

ROMCS#

109

116

136

72:65, 63, 61:56

92:90, 88:84

113

I/O

I/O

0

I/O

I/O

O

Blank signal

Pixel Clock output

Enable Pixel clock

Enable Sync

Enable Pixel data

Pixel data output

Serial l/O, Interrupt Request

Slave not ready

Pixel mask

EEPROM clock

EEPROM data l/O

EEPROM chip select

EPROM address bus

EPROM data bus

ROM chip select

Optional EEPROM Interface (Monitor ID for DDC Support)

GlO0

Gl04

108

138

I/O

I/O

DDC serial data

DDC serial clock

Power and Ground Pins

AVDD 126

AVSS

PVDD

PVSS

VCC

119

110, 115

112

10,27, 37,53,

62,78, 127,130,

157,195, 208

Power and Ground Pins

VEE 139,170, 183

VSS 1,2,12, 26,39,

51,52, 64,79,

101,105,

106,118,

131,155,

156,168,

182,197

PWR

GND

PWR

GND

PWR

PWR

GND

DAC analog power

DAC analog ground

PLL power

PLL ground

3.3V power

5.0V power

Ground

2-52 Service Guide

2.4.

µµµµ

PD481850 SGRAM

The mPD481850 is a synchronous graphics memory (SGRAM) organized as 131,072 words x 32 bits x 2 banks random access port.

This device can operate up to 100 MHz by using synchronous interface. Also, it has 8-column Block

Write function to improve capability in graphics system.

This product is packaged in 100-pin plastic QFP (14 ´ 20 mm).

2.4.1 Features

131,072 words x 32 bits x 2 banks memory

Synchronous interface (Fully synchronous DRAM with all input signals are latched at rising edge of clock)

Pulsed

Automatic precharge and controlled precharge commands

Ping-pong operation between the two internal memory banks

Up to 100 MHz operation frequency

Possible to assert random column address in every cycle

Dual internal banks controlled by A9 (Bank Address: BA)

Byte control using DQM0 to DQM3 signals both in read and write cycle

8-column Block Write (BW) function

Persistent write per bit (WPB) function

Wrap sequence: Sequential

Programmable burst length (1, 2, 4, 8 and full page)

Programmable CAS# latency (2 and 3)

Power Down operation and Clock Suspend operation

Auto refresh (CBR refresh) or self refresh capability

Single 3.3 V ± 0.3 V power supply

Major Chipsets 2-53

LVTTL compatible inputs and outputs

100-pin Plastic QFP (14 ´ 20 mm)

1,024 refresh cycles/16 ms

Burst termination by Precharge command

Burst termination by Burst stop command (in case of full-page burst)

2.4.2 Block Diagram

Figure 2- 1

µ

PD481850 Block Diagram

2-54 Service Guide

2.4.3 Pin Diagram

Figure 2- 2

µ

PD481850 Pin Diagram

Major Chipsets 2-55

2.4.4 Signal Descriptions

Table 2- 4

µ

PD481850 Signal Descriptions

Signal

CLK 55

Pin Type

Input

CKE

CS#

RAS#,

CAS#,

WE#

DSF

A0 - A8

A9

DQM0 -

DQM3

54

28

27,

62,

25

53

31-34, 47-50

29

23, 56, 24, 57

Input

Input

Input

Input

Input

Input

Input

Pin Descriptions

CLK is the master clock input. Other inputs signals are referenced to the CLK rising edge.

CKE determine validity of the next CLK (clock). If

CKE is high, the next CLK rising edge is valid; otherwise it is invalid. If the CLK rising edge is invalid, the internal clock is not asserted and the

µ

PD481850 suspends operation.

When the mPD481850 is not in burst mode and

CKE is negated, the device enters power down mode. During power down mode, CKE must remain low.

In Self refresh mode, low level on this pin is also used as part of the input command to specify Self refresh.

CS# low starts the command input cycle. When

CS# is high, commands are ignored but operations continue.

RAS#, CAS# and WE# have the same symbols on conventional DRAM but different functions.

For details, refer to the command table.

DSF is part of the inputs of graphics command of the

µ

PD481850. If DSF is inactive (Low level), mPD481850 operates as same as SDRAM.

Row Address is determined by A0 - A8 at the

CLK (clock) rising edge in the activate command cycle.

Column Address is determined by A0 - A7 at the

CLK rising edge in the read or write command cycle.

A8 defines the precharge mode. When A8 is high in the precharge command cycle, both banks are precharged; when A8 is low, only the bank selected by A9 is precharged.

When A8 high in read or write command cycle, the precharge start automatically after the burst access.

A9 is the bank address signal (BA). In command cycle, A9 low selects bank A and A9 high selects bank B.

DQM controls I/O buffers. DQM0 corresponds to the lowest byte (DQ0 to DQ7), DQM1 corresponds to DQ8 to DQ15, DQM2 corresponds to DQ16 to DQ23. DQM3 corresponds to DQ24 to DQ31.

In read mode, DQM controls the output buffers like a conventional OE pin.

DQM high and DQM low turn the output buffers off and on, respectively. The DQM latency for the

2-56 Service Guide

Table 2- 4

Signal

DQ0 -

DQ31

VCC

VSS

V

CC

Q

V

SS

Q

N.C.

µ

PD481850 Signal Descriptions

Pin Type

97, 98, 100, 1, 3, 4, 6,

7, 60, 61, 63, 64, 68,

69, 71, 72, 9, 10, 12,

13, 17, 18, 20, 21, 74,

75, 77, 78, 80, 80, 83,

84

15, 35, 65, 97

16, 46, 66, 85

2, 8, 14, 22, 59, 73, 79

5, 11, 19, 62, 70, 76,

82, 99

30, 36-45, 52, 58, 86-

95

Input/

Output

(Power supply)

Pin Descriptions

read is two clocks.

In write mode, DQM controls the word mask.

Input data is written to the memory cell if DQM is low but not if DQM is high. The DQM latency for the write is zero.

DQ pins have the same function as I/O pins on a conventional DRAM. These are normally 32-bit data bus and are used for inputting and outputting data.

Function as the mask data input pins in the special register set command. Write operations can be performed after Active command with

WPB (old mask data).

Functions as the column selection data input pin in the block write cycle.

VCC and VSS are power supply pins for internal circuits. VCCQ and VSSQ are power supply pins for the output buffers.

Non-connected

Major Chipsets 2-57

2.5. SMC 37C93xAPM

The SMC 37C93xAPM is an advanced high-performance multi-mode parallel port super I/O floppy disk controller.

2.5.1 Features

Compatible with ISA Plug-and-Play standard (version 1.0a)

8042 keyboard controller

2-K Proqram ROM

256-byte Data RAM

Asynchronous access to two data registers and one status register

Supports interrupt and pollinq access

8-bit timer counter

Real time clock

MC146818 and DS1287 compatible

256 bytes of battery-backed CMOS in two banks of 128 bytes

128 bytes of CMOS RAM lockable in 4 x 32 byte blocks

12 and 24-hour time format

Binary and BCD format

<1

µ a standby current (typ)

Intelligent auto-power management

2.88-MB super l/O floppy disk controller

Relocatable to 480 different addresses

13 IRQ options

Three DMA options

Licensed CMOS 765B floppy disk controller

Advanced digital data separator

Software and register compatible with SMC’s proprietary 82077AA compatible core

Sophisticated Power Control Circuitry (PCC) including multiple power-down modes for reduced power consumption

Game port select logic

Directly supports two floppy drives

24-mA AT bus drivers

2-58 Service Guide

Low-power CMOS design

Major Chipsets 2-59

Licensed CMOS 765B floppy disk controller core

Supports vertical recording format

16-byte data FIFO

100% IBM compatibility

Detects all overrun and underrun conditions

48-mA drivers and Schmitt Trigger inputs

DMA enable logic

Data rate and drive control registers

Enhanced digital data separator

Low-cost

No filter components required

2-Mbps, 1-Mbps, 500-Kbps, 300-Kbps, 250-Kbps data rates

Programmable pre-compensation modes

Serial ports

Relocatable to 480 different addresses

13 IRQ options

2 high-speed NS16C550 Compatible UARTs with send/receive 16-byte FIFOs

Programmable baud rate generator

Modem control circuitry including 230-K and 460-K baud

IrDA, HP-SIR, ASK-IR support

IDE interface

Relocatable to 480 different addresses

13 IRQ options

6 DMA options

2-channel/4-drive

On-chip decode and select logic compatible with IBM PC/XT and PC/AT embedded hard disk drives

Multi-mode parallel port with ChiProtect

Relocatable to 480 different addresses

2-60 Service Guide

2.5.2 Block Diagram

Figure 2-6 SMC 37C93xAPM Block Diagram

Major Chipsets 2-61

2.5.3 Pin Diagram

Figure 2-7 SMC 37C93xAPM Pin Diagram

2-62 Service Guide

2.5.4 Signal Descriptions

Table 2- 5 SMC 37C93xAPM Signal Descriptions

Type Signal Pin

Host Processor Interface

SD0 - SD7

SA0 - SA11

CS#

AEN

IOCHRDY

RESET_DRV

IRQ[1, 3:12, 14, 15]

DRQ[0:3]

DACK[0:3]#

TC

IOR#

IOW#

16CLK

CLOCKI

CLOCK1

CLOCK2

CLOCK3

72:79

41:52

53

70

90

80

67:61, 59:54

82,84,86,88

36

22

37

81, 83, 85, 87

89

68

69

38

39

Floppy Drive Interface

RDATA#

WGATE#

WDATA#

HDSEL#

DIR#

STEP#

DSKCHG#

DS[0:1]#

MTR[0:1]#

WPROT#

TR0#

INDEX#

DRVDEN[1:0]

MID[1:0]

9

10

18

5,6

7,4

17

12

11

13

16

15

14

3,2

19,20

Serial Port Interface

RXD1, RXD2

TXD1, TXD2

RTS1#, RTS2#

145, 155

146, 156

148, 158

Serial Port Interface

CTS1#, CTS2# 149, 159 I

IS

OD48

OD48

OD48

OD48

OD48

IS

OD48

OD48

IS

IS

IS

OD48

IS

I

I

I

I

O8SR

ICLK

O8SR

I

I

I/O24

I

OD24

IS

OD24

O24

O8SR

O8SR

I

O4

O4

Description

System Data Bus

System Address Bus

Chip Select / SA12

Address Enable

I/O Channel Ready

Reset Drive

Interrupt Requests

DMA Request

DMA Acknowledge

Terminal Count

I/O Read

I/O Write

16MHz Out

14.318MHz Clock Input

14.318MHz Clock Output 1

14.318MHz Clock Output 2

14.318MHz Clock Output 3

Read Disk Data

Write Gate

Write Data

Head Select ( 1 = side 0 )

Direction Control ( 1 = out )

Step Pulse

Disk Change

Drive Select 0, 1

Motor on Lines

Write Protected

Track 00

Index Pulse Input

Drive Density Select [1:0]

Media ID Inputs

Receive Data

Transmit Data

Request to Send

Clear to Send

Major Chipsets 2-63

Table 2- 5 SMC 37C93xAPM Signal Descriptions

Signal

DTR1#, DTR2#

DSR1#, DSR2#

DCD1#, DCD2#

RI1#, RI2#

Parallel Port Interface

PD0-PD7

SLCTIN#

INIT#

ALF#

STB#

BUSY

ACK#

PE

SLCT

ERROR#

Pin

150, 160

147, 157

152, 154

151, 153

IDE

IDE1_OE#

HDCS0#

HDCS1#

IOROP#

IOWOP#

A[2:0]

IDE1_IRQ

HDCS2

HDCS3

IDE2_IRQ

Real Time Clock

XTAL1

XTAL2

Vbat

122

124

121

Keyboard / Mouse

KDAT

KCLK

MDAT

91

92

93

Keyboard / Mouse

MCLK 94

Soft Power Management Interface

PowerOn# 33

23

24

25

30

31

32:34

26

27

28

29

144

128

129

127

138:131

140

141

143

126

142

I

I

I

O4

O4

O24

O24

O24

O24

O24

I

O24

I

O24

Type Description

Data Terminal Ready

Data Set Ready

Data Carrier Select

Ring Indicator

I

I

I/OP24 Port Data

OD24/OP24 Printer Select

OD24/OP24 Initiate Output

OD24/OP24 Auto Line Feed

I

I

I

OD24/OP24 Strobe Signal

Busy Signal

Acknowledge Handshake

Paper End

Printer Selected

Error at Printer

ICLK

OCLK

I/OD16P

I/OD16P

I/OD16P

I/OD16P

I/O24

IDE1 Enable

IDE1 Chip Select0

IDE1 Chip Select1

IOR Output

IOW Output

Address [2:0] Output

IDE Interrupt Request

IDE2 Chip Select 2 / SA13

IDE2 Chip Select 3 / SA14

IDE2 Interrupt Request / SA15

32-KHz Crystal Input

32-KHz Crystal Output

Battery Voltage

Keyboard Data

Keyboard Clock

Mouse Data

Mouse Clock

Power On

2-64 Service Guide

Table 2- 5

Signal

Button_In

SMC 37C93xAPM Signal Descriptions

34

Pin Type

I/O24

GP15

GP16

GP17

GP20

GP21

GP22

GP23

GP24

GP25

General Purpose I/O

GP10

GP11

GP12

GP13

GP14

BIOS Buffers

RD[0:7]

DOMCS#

104

105

106

107

108

109

110

96

97

98

99

100

102

103

111:118

119 I

I/O4

I/O4

I/O4

I/O4

I/O4

I/O4

I/O4

I/O4

I/O4

I/O4

I/O4

I/O24

I/O4

I/O4

I/O4

ROMOE# 120 I

Button Input

Description

IRQ In

IRQ In

WD Timer Output / IRRX

Power LED Output / IRTX

GPI/O, General Purpose Read Strobe

GPI/O, General Purpose Write Strobe

GPI/O, Joystick Read Strobe / JOYCS

GPI/O, Joystick Write Strobe

GPI/O, IDE2 Output Enable

GPI/O, Serial EEPROM Data In

GPI/O, Serial EEPROM Data Out

GPI/O, Serial EEPROM Clock

GPI/O, Serial EEPROM Enable

GPI/O, 8042 P21

ROM Bus (I/O to the SD bus)

ROM Chip Select

(only used for ROM)

ROM Output Enable (DIR)

(only used for ROM)

Power

VCC + 5V Supply Voltage

VTR

GND

21, 60, 101, 125,

139

32

1, 8, 40, 71, 95,

123, 130

Trickle Voltage Input

Ground

Major Chipsets 2-65

2.5.5 Multifunction Pins with GPI/O and Other Alternate Functions

Table 2- 6 Multifunction Pins with GPI/O and Other Alternate Functions

Pin

No.

25

26

30

19

20

23

24

Original

Function

Alternate

Function 1

MEDIA_ID1 GPI/O

MEDIA_ID0 GPI/O

IDE1_OE#

HDCS0#

GPI/O

GPI/O

HDCS1#

IDE1_IRQ

IOROP#

GPI/O

GPI/O

GPI/O

Alternate

Function 2

Alternate

Function 3

WDT

Buffer

Type

I/O8

I/O8

I/O4

I/O24

I/O24

I/O8

I/O24

Default Index

Register

GP4

GP4

GP4

GP4

GP4

GP4

GP4

31

33

IOWOP#

PowerOn#

GPI/O

GPI/O

Power LED

Output

SMI# I/O24

I/O24

Float

Float

High

High

High

Float

Float

34 Button_In

111 RD0

112 RD1

113 RD2

114 RD3

115 RD4

116 RD5

117 RD6

118 RD7

119 ROMCS#

120 ROMOE#

153 R12#

154 DCD2#

155 RXD2

156 TXD2

157 DSR2#

158 RTS2#

159 CTS2#

160 DTR2#

GPI/O

GPI/O

GPI/O

GPI/O

GPI/O

GPI/O

GPI/O

GPI/O

GPI/O

GPI/O

GPI/O

GPI/O

GPI/O

GPI/O

GPI/O

GPI/O

GPI/O

GPI/O

GPI/O

Power LED

Output

WDT

8042-P12

8042-P13

8042-P14

8042-P15

8042-P16

8042-P17

I/O24

I/O4

I/O4

I/O4

I/O4

I/O4

I/O4

I/O4

I/O4

I/O8

I/O8

I/O8

I/O8

I/O8

I/O8

I/O8

I/O8

I/O8

I/O8

GP4

GP5

GP5

GP6

GP6

GP6

GP6

GP6

GP6

RD6

(1) (4)

RD7

(1) (4)

ROMCS#

(1)

ROMOE#

(1)

GP6

GP6

GP5

GP5

Input (2) GP7

Input (2) GP7

Input (2) GP7

Input

(2) (4)

GP7

Input (2) GP7

Input

(2) (4)

GP7

Input (2) GP7

Input

(2) (4)

GP7

Float

Active low open collector output

Input

RD0

(1) (4)

RD1

(1) (4)

RD2

(1) (4)

RD3

(1) (4)

RD4

(1) (4)

RD5

(1) (4)

GPI/O

GP40

GP41

GP42

GP43

GP44

GP45

GP46

GP47

GP51

GP50

GP60

GP61

GP62

GP63

GP64

GP65

GP66

GP67

GP53

GP54

GP70

GP71

GP72

GP73

GP74

GP75

GP76

GP77

2-66 Service Guide

Pin

No.

96

97

98

27

28

29

53

Table 2- 6

99

Original

Function

HDCS2#

HDCS3#

IDE2_IRQ

CS/SA 12#

GPI/O

GPI/O

GPI/O

GPI/O

100 GPI/O

102 GPI/O

103 GPI/O

104 GPI/O

105 GPI/O

106 GPI/O

107 GPI/O

108 GPI/O

109 GPI/O

110 GPI/O

Multifunction Pins with GPI/O and Other Alternate Functions

Alternate

Function 1

SA13

SA14

SA15

Alternate

Function 2

Alternate

Function 3

Buffer

Type

I

I

I/O24

I/O24

I/O4

I/O4

I/O4

Default

Float

Float

Float

Input

Input

Input

Input

Index

Register

GP1

GP1

GP1

Serial

EEPROM

Data In

Serial

EEPROM

Data Out

Serial

EEPROM

Clock

Serial

EEPROM

Enable

8042 P21

IRQ in

IRQ in

WDT Timer

Output/IRR

X

Power LED

Output/IRTX

GP Address

Decode

GP Write

Strobe

Joy Read

Strobe

Joy Write

Strobe

IDE2 Output

Enable

IRQ13

JOYCS

8042 P20

AB_DATA

AB_CLK

I/O24

I/O4

I/O4

I/O4

I/O4

I/O4

I/O8/

OD8

(EN1)

I/O8/

OD8

(EN1)

I/O4

I/O4

I/O4

Input

Input

Input

Input

Input

Input

Input

Input

Input

Input

Input

GP1

GP1

GP1

GP1

GP1

GP2

GP2

GP2

GP2

GP2

GP2

GPI/O

GP10

GP11

GP12

GP13

GP14

GP15

GP16

GP17

GP20

GP21

GP22

GP23

GP24

GP25

Notes (1):

At power-up, RD0-RD7, ROMCS# and ROMOE# function as the XD Bus. To use RD0-RD7 for functions other than the XD Bus, ROMCS# must stay high until the reprogramming of RD0-RD7 is done.

(2):

These pins are input (high-z) until they are programmed for second serial port.

(3): This is the trickle voltage input pin for the FDC37C93XAPM.

(4): These pins cannot be programmed as open drain pins in their original function.

(5):

No pins in their original function can be programmed as inverted input or inverted output.

Major Chipsets 2-67

2.5.6 Buffer Type Descriptions

Table 2- 7 SMC 37C935 Buffer Type Descriptions

Buffer Type

I

IS

I/OD16P

I/O24

O4

O8SR

O24

OD24

OD48

OD24P

OP24

OCLK

ICLK

Description

Input TTL compatible

Input with Schmitt Trigger

Input/output, 19-mA sink, 90-uA pull-up

Input/output pin. 24-mA sink; 12-mA source

Output, 4-mA sink; 2.0-mA source

Output, 8-mA sink; 4.0-mA source with Slew Rate Limiting

Output, 24-mA sink; 12-mA source

Output, open drain; 24-mA sink

Output, open drain; 48-mA sink

Output, open drain; 24-mA sink, 4-mA source pull up

Output; 24-mA sink, 12-mA source

Clock output

Clock input

2-68 Service Guide

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