Lite End Multiport Repeater Interface Controller
TC3097-8
Preliminary Data Sheet
Lite End Multiport Repeater Interface Controller
Functionally conforms to Section 9 in the IEEE
802.3 specification.
9 network connection (ports) per chip including:
– 1 AUI PORT with fully compatible and drive capability (50m AUI cable).
– 8 TP PORT with fully compatible and drive capability (100m TP cable).
Cascadable for large multiple LEMRIC hub applications.
On-chip Elasticity buffer, Manchester encoder and decoder.
Separate partition state machine for each port.
Embeded LED output driver for each port partition status, each port link/receive status
(TP port), global jam status, and global jabber status. No external glue logic is required.
Embedded predistortion resistors for every TP port.
Build in power reset circuit, no extra glue logic required.
Crystal/Oscillater optional applicable.
Manchester code violation detection and reporting.
Support MAU Jabber Lockup Protection function.
Support Auto Partition/Reconnection function to isolate a faulty segment's collision activity.
Fully integrated Link Test logic with enable/disable option, conforming to the
10BASE-T standard.
Fully integrated polarity detect/correct logic with enable/disable option for per TP port.
Low power consumption; fully load < 900 mW.
CMOS device feature high integration with a single + 5V supply.
100-pin QFP package.
The TC3097 Lite End Multiport Repeater Interface
Controller (LEMRIC) may be used to implement an IEEE 802.3 multiport repeater unit. It fully satisfies the IEEE 802.3 repeater specification including the functions defined by the repeater, segment partition and jabber lockup protection state machines.
The LEMRIC has an on-chip phase-locked-loop
(PLL) for Manchester data decoding, a
Manchester encoder, and an Elasticity Buffer for preamble regeneration. In addition, it provides direct LED display driver pins for per port
LINK/RCV status, per port partition jabber status, global jam and jabber lockup status indications.
Each LEMRIC can connect up to 9 cable segments via its network interface ports. One port is fully Attachment Unit Interface (AUI) compatible and is able to connect to an external Medium
Attachment Unit (MAU) using the maximum length of AUI cable. The other 8 ports have integrated
10BASE-T transceivers. In addition, large repeater units may be constructed by cascading LEMRICs together over the Inter-LEMRIC bus.
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Copyright © 2003, IC Plus Corp.
July 21. 2003
TC3097-8-DS-R24
TC3097-8
Preliminary Data Sheet
Table Of Contents
Features ..............................................................................................................................................................1
General Description............................................................................................................................................1
Table Of Contents ...............................................................................................................................................2
1 Pin Description..........................................................................................................................................4
1.1
Config (pin 2 is connected to GND) ..................................................................................... 4
2 Principles Of Operation ............................................................................................................................7
2.1
Reset.................................................................................................................................... 7
2.2
Clock and data Recovery..................................................................................................... 7
2.3
Functional State diagrams ................................................................................................... 8
2.3.1
TP Port Auto-Partition State Diagram ..................................................................... 8
2.3.2
2.3.3
2.3.4
2.3.5
AUI Port Auto-Partition State Diagram.................................................................. 10
Global State Diagram............................................................................................ 12
Counters and Timers............................................................................................. 15
Automatic Preamble Regeneration....................................................................... 17
2.3.6
2.3.7
Inter-LEMRIC Bus Operation................................................................................ 19
Port Block functions .............................................................................................. 26
3 Absolute Maximum Ratings.................................................................................................................29
4 D.C. Characteristics................................................................................................................................29
5 Switching Characteristics .......................................................................................................................30
6 Package Detail ..........................................................................................................................................35
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Copyright © 2003, IC Plus Corp.
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TC3097-8-DS-R24
TC3097-8 Connection Diagram
Config (pin 2 is connected to GND)
TC3097-8
Preliminary Data Sheet
V
D
D
G
N
D
N
C
N
C
V
D
D
7
B
R
X
I I
7
R
X
A
T
X
O
7
R
B
T
X
O
7
R
A
G
N
D
V
D
D
I
6
R
X
B
I
6
R
X
A
T
R
O
6
R
B
T
R
O
6
R
A
I
5
R
X
B
I
5
R
X
A
T
X
O
5
R
B
T
X
O
5
R
A
G
N
D
V
D
D
I
4
R
X
B
R
X
I
4
A
O
4
T
X
R
B
T
X
O
4
R
A
V
D
D
N
C
N
C
N
C
G
N
D
TXO8RA
TXO8RB
RXI8A
RXI8B
VDD
TXO9RA
TXO9RB
RXI9A
RXI9B
GND
PALED1
PALED2
PALED3
PALED4
PALED5
PALED6
PALED7
PALED8
PALED9
GND
81
82
83
84
85
86
87
92
93
94
88
89
90
91
95
96
97
98
99
100
80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51
TC3097-8
100pin QFP
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30
39
38
37
36
35
34
33
32
31
45
44
43
42
41
40
50
49
48
47
46
TXO3RA
TXO3RB
VDD
RXI3B
RX1A
VDD
CD18
AGND
CD1A
CP1_0
VCO_I
AVDD
RXI3A
TXO2RA
TXO2RB
RXI2B
RXI2A
TX1B
TX1A
RX1B
V
D
D
G
N
D
C
O
L
E
D
L
R
L
E
D
1
B
L
J
A
E
D
L
E
L
R
D
3
L
E
L
R
D
2
L
E
L
R
D
5
L
E
L
R
D
4
L
R
L
E
D
7
L
R
L
E
D
6
L
E
L
R
D
9
L
R
L
E
D
8
G
N
D
I
R
E
Z
I
R
D
I
R
C
A
C
K
O
A
C
K
I
A
C
T
N
Z
X
N
A
Y
Z
C
O
L
N
Z T
Z
S
E
R
E
G
N
D
C
L
K
1
K
2
C
L
V
D
D S
T
T
E
1
S
T
T
E
3
S
T
T
E
4
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July 21. 2003
TC3097-8-DS-R24
TC3097-8
Preliminary Data Sheet
1 Pin Description
1.1 Config (pin 2 is connected to GND)
Pin No. Symbol I/O Description
Network Interface Pins
42, 46, 58,
64, 68, 74,
83, 88
RXI2A to RXI9A I Twisted-Pair Receive Input Positive
43, 47, 59,
65, 69, 75,
84, 89
RXI2B to RXI9B I Twisted-Pair Receive Input Negative
45, 50, 56,
62, 66, 72,
81, 86
TXO2RA to
TXO9RA
O Twisted-Pair Transmit Output Positive
44, 49, 57,
63, 67, 73,
82, 87
38
TXO2RB to
TXO9RB
RX1A
O Twisted-Pair Transmit Output Negative
I AUI Receive Input Positive
39
40
41
RX1B
TX1A
TX1B
34
36
Pin No.
CD1A
CD1B
Symbol
Power & Ground Pins
61, 71, 79 GND
I AUI Receive Input Negative
O AUI Receive Output Positive
O AUI Receive Output Negative
I AUI Collision Detect Input Positive
I AUI Collision Detect Input Negative
I/O
P
Description
Ground pins for TP port 1 to port 8 output pins.
P Power pins for TP port 1 to TP port 8 output pins. 48, 60, 70,
85
VDD
51, 90, 100 GND
37, 55, 76,
80
VDD
P
P
Ground pin for internal digital circuit of this device.
Power pin for internal digital circuit of this device.
2, 14, 24 GND
1, 27 VDD
35 AGND
AVDD 31
Pin No. Symbol
Inter-LEMRIC Bus Pins
19 ACKI
P Ground pins for digital output pins.
P Power pins for digital output pins.
P Ground pin for PLL decoder internal circuit.
P Power pin for PLL decoder internal circuit.
I/O Description
18 ACKO
ACKnowledge
Input to the network port’s arbitration chain.
ACKnowledge
Output from the network port’s arbitration chain.
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TC3097-8-DS-R24
TC3097-8
Preliminary Data Sheet
Pin No. Symbol
Inter-LEMRIC Bus Pins
16 IRD
I/O Description
15 IREZ
Inter-LEMRIC
When asserted as an output this signal provides a serial data stream in NRZ format.
This signal is asserted by a LEMRIC when it is receiving data from one of its network segments. The default condition of this signal is to be an input. In this state, it may be driven by other devices on the Inter-LEMRIC bus.
Inter-LEMRIC
When asserted as an output this signal provides an activity-framing enable for the serial data stream. The signal is asserted by a
LEMRIC when it is receiving data from one of its network segments.
The default condition of this signal is to be an input. In this state it may be driven by other devices on the inter-LEMRIC bus.
17 IRC
22 COLNZ
When asserted as an output this signal provides a clock signal for the serial data stream. Data (XIRD) is changed on the falling edge of the clock. The default condition of this signal is to be an input. When an input, XIRD is sampled on the rising edge of the clock. In this state it may be driven by other devices on the Inter-LEMRIC bus.
B,Z Collision on Port N:
This denotes that a collision is occurring on the port receiving the data packet (Port N). The default condition of this signal is to be an input. In this state it may be driven by the other devices on the
Inter-LEMRIC bus.
20
21
ACTNZ
AYXNZ
B,Z Activity on Port N:
This is a bi-directional signal. The LEMRIC asserts this signal when data or collision information is received from one of its network segments. The LEMRIC senses this signal when this or another LEMRIC in a multi-LEMRIC system is receiving data or collision information.
B,Z Activity on ANY Port Excluding Port N:
This is a bi-directional signal. The LEMRIC asserts this signal when a transmit collision is experienced or multiple ports have active collisions on their network segments.
The LEMRIC senses this signal when this LEMRIC or other LEMRICs in a multi-LEMRIC system are experiencing transmission collision or multiple ports have active collisions on their network segments.
Pin No. Symbol
LED Driver Pins
I/O Description
3 COLED O Collision LED (Active-Low):
This CMOS output indicates the status of the LEMRIC's any collision activity.
4 JABLED O Global Jabber LED (Active-Low):
This CMOS output indicates when the LEMRIC's watchdog timer begins to jab and stays active until end of the unjab wait period.
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TC3097-8-DS-R24
TC3097-8
Preliminary Data Sheet
Pin No. Symbol
LED Driver Pins
I/O Description
6-13 LRLED2
LRLED9 to O Link/Receive LED (active-Low):
This CMOS output goes active when the link integrity test is pass on LEMRIC's TP port network segment and blinks when this device is receiving from its link passing TP port segment.
5 LRLED1 O
This CMOS output is powered on active and blinking when this device is receiving from its AUI port network segment.
PALED9
O Port Partition Jabber LED (Active-Low):
This CMOS output goes active when the LEMRIC's network connection port is partitioned from its network segment and then goes inactive when its network connection port is reconnection from its network segment.
Pin No. Symbol I/O Description
TEST Support Pins
28
29
30
TEST1
TEST3
TEST4
B These pins are used to facilitate device testing. When not in test mode, these pins should be left open. [Note:] Pins TEST3 and
TEST4 can be used to modify the build in 10BASE-T operation.
TEST1 can be used to configure LED display mode (ICPLUS or
AMD compatible mode). Refer to port Block Function section for more details.
Pin No. Symbol
RESET & CLOCK Pins
23 RESETZ
I/O Description
25
26
CLK1
CLK2
Pin No. Symbol
Decoder Filer Pins
I Optional device Reset. A low on this pin causes the device to reset. RESET must be high for normal operation, when not used, please leave open.
I
O
System Clock. 20 MHz, 50% nominal, 40/60% worst case, duty cycle. The worst-case frequency tolerance and duty cycle limit the range over which the LEMRIC will operate correctly. However, since this clock is used for Manchester data transmission, jitter performance will degrade if clock sources with relatively large tolerances are used.
I/O Description
33 CP1_O
32 VCO_I
I Phase Lock Loop delay line external filter. This pin should be connected correctly with a capacitor to AVDD or causing the analog PLL of the device to be failed.
I Phase Lock Loop VCO external filter. This pin should be connected correctly with a RC filter circuit to AVDD or causing the analog PLL of the device to be failed.
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July 21. 2003
TC3097-8-DS-R24
TC3097-8
Preliminary Data Sheet
2 Principles Of Operation
2.1 Reset
The LEMRIC resets when XRESETZ (pin 25) is pulsed low. While reset, the LEMRIC ignores all energy and collision inputs, unjabs all ports, and initializes all timers, counters, and state machines. At the end of reset (XRESETZ goes high), all the LEDs are turned off and the XLRLED1 is turned on.
The minimum XRESETZ low pulse is one second to let the power on LED test visually distinguishable.
The LEMRIC is fully operational when it exits reset.
2.2 Clock and data Recovery
The clock and data recovery circuit (Manchester decoder) is a linear circuit, which it recovers the NRZ data and clock from the Manchester encoded serial data stream. Data from the active port is routed to the decoder and the recovered data is written into the FIFO.
1 0 1 0 0 1 1 0 1 0 1 1
Manchester
Data
NRZ
Data
NRZ
Clock
Figure 1. Manchester Data - NRZ Data Relationship
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July 21. 2003
TC3097-8-DS-R24
TC3097-8
Preliminary Data Sheet
2.3 Functional State diagrams
The following state diagrams describe the auto-partition and global state machines implemented in the
LEMRIC. The notation and variables used in each diagram are described below.
2.3.1 TP Port Auto-Partition State Diagram
A partitioning state machine is implemented for each TP port. Individual Tw5 and Tw6 timers and collision counters are implemented for each state machine.
2.3.1.1 State Diagram Notation and Variables.
=
&
Assign the right side constant or expression result to the left side variable.
Logical ”AND” operator.
+ Logical ”OR” operator when used in a state-exiting expression. Arithmetic addition when used otherwise.
Group term for logical evaluation. {[term]}
X
CC(X)
DIPresent(X) Carrier from the MAU on TP port X.
Values: Idle-Port carrier is not active.
Active-Port carrier is active.
Datain(X) TP port X carrier to the global state machine.
Values: Idle-Port carrier has been gated off by the partition state machine.
DIPresent(X)-Port carrier is passed on to the global state machine.
TEN(X)
Number identifier for the particular TP port.
Values: Integers from 1 to 8
Consecutive collision count for TP port X.
Values: Integers from 0 to 31
/COLN
Status of transmission to the MAU on TP port X.
Values: Idle-Not transmitting to the port MAU.
Active-Transmitting to the port MAU.
Inter-LEMRIC that is Port N or Port M collision.
Values: Idle-/COLN is not active.
Active-/COLN is active.
/ANYXN
Tw5
Tw6
Inter-LEMRIC that is not Port N or Port M collision.
Values: Idle-/ANYXN is not active.
Active-/ANYXN is active.
Enable Tw5 initializes and starts the PORT Tw5 timer. Tw5Done indicates that the timer has expired.
Enable Tw6 initializes and starts the port Tw6 timer. /Tw6Done indicates that the timer is running. Tw6Done indicates that the timer has expired.
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TC3097-8-DS-R24
TC3097-8
Preliminary Data Sheet
RESET
COUNT CLEAR - 0
CC(X) = 0
Datain(X) = DIPresent(X)
TEN(X) = Idle &
DIPresent(X)=Idle
PARTITION WAIT - 4
Datain(X) = Idle
TEN(X)=Idle &
DIPresent(X)=Idle
PARTITION HOLD - 5
Datain(X) = Idle
TEN(X)=Active +
DIPresent(X)=Active
COLLISION COUNT IDLE - 1
Datain(X) = DIPresent(X)
TEN(X)=Active +
DIPresent(X)=Active
WATCH FOR COLLISION - 2
Datain(X) = DIPresent(X)
Enable Tw5
DIPresent(X)=Idle &
TEN(X)=Idle &
/COLN,/ANYXN=Idle
{[TEN(X)=Active &
DIPresent(X)=Idle] +
[TEN(X)=Idle &
DIPresent(X)=Active]} &
Tw5Done &
/COLN,/ANYXN=Idle
[/COLN=Active +
/ANYXN=Active +
TEN(X)=Active] &
DIPresent(X)=Active
COLLISION COUNT INCREMENT - 3
CC(X) = CC(X) + 1
Datain(X) = DIPresent(X)
EnableTw6
CC(X) >= 31 +
[TEN(X)=Active &
DIPresent(X)=Active &
Tw6Done]
TEN(X)=Idle &
DIPresent(X)=Idle &
CC(X) < 31 & /Tw6Done
PARTITION COLLISION WATCH - 6
Datain(X) = Idle
EnableTw5
[/COLN=Active +
ANYXN=Active +
TEN(X)=Active] &
DIPresent(X)=Active
TEN(X)=Idle &
DIPresent(X)=Idle &
/COLN,/ANYXN=Idle
{[TEN(X)=Active & DIPresent(x)=Idle] +
[TEN(X)=Idle & DIPresent(X)=Active]} &
Tw5Done & /COLN, /ANYXN=Idle
WAIT TO RESTORE PORT - 7
Datain(X) = Idle
CC(X) = 0
TEN(X)=Idle & DIPresent(X)=Idle
Figure 2. Partition State Diagram for TP Port X
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TC3097-8-DS-R24
TC3097-8
Preliminary Data Sheet
2.3.2 AUI Port Auto-Partition State Diagram
A partition state machine is implemented for each AUI port. Individual Tw5 and Tw6 timers and collision counters are implemented for each state machine.
2.3.2.1 State Diagram Notation and Variables.
=
&
Assign the right side constant or expression result to the left side variable.
Logical ”AND” operator.
+
{[term]}
Y
Tw6
Logical ”OR” operator when used in a state-exiting expression. Arithmetic addition when used otherwise.
Group term for logical evaluation.
Number identifier for the particular AUI port.
Values: Integers 0 and 1 collision count for AUI port Y
Values: Integers from 0 to 31
DIPresent(Y) Carrier from the MAU on AUI port Y.
Values: Idle-Port carrier is not active.
Active-Port carrier is active.
Datain(Y) AUI port carrier to the global state machine.
Values: Idle-Port carrier has been gated off by the partition state machine.
DIPresent(Y)-Port carrier is passed on to the global state machine.
CIPresent(Y) Collision indication from the MAU on AUI Port Y.
Values: /SQE-Port collision is not active.
SQE-Port collision is active.
Collin(Y) AUI port collision to the global state machine.
Values: /SQE-Port collision has been gated off by the partition state machine.
CIPresent(Y)-Port collision is passed on to the global state machine.
/COLN
/ANYXN
Inter-LEMRIC that is Port N or Port M collision.
Values: Idle-/COLN is not active.
Active-/COLN is active.
Inter-LEMRIC that is not Port N or Port M collision.
Values: Idle-/ANYXN is not active.
Active-/ANYXN is active.
Tw5 Enable Tw5 initializes and starts the PORT Tw5 timer. Tw5Done indicates that the timer has expired.
Enable Tw6 initializes and starts the port Tw6 timer. /Tw6Done indicates that the timer is running. Tw6Done indicates that the timer has expired.
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TC3097-8-DS-R24
TC3097-8
Preliminary Data Sheet
RESET
COUNT CLEAR - 0
CC(Y) = 0
Datain(Y) = DIPresent(Y)
Collin(Y)=CIPresent(Y)
DIPresent(Y)=Idle
&
CIPresent(Y)=/SQE
PARTITION W AIT - 4
Datain(Y) = Idle
Collin(Y)=/SQE
DIPresent(Y)=Idle &
CIPresent(Y)=/SQE
COLLISION COUNT IDLE - 1
Datain(Y) = DIPresent(Y)
Collin(Y)=CIPresent(Y)
DIPresent(Y)=Active +
CIPresent(Y)=SQE
W ATCH FOR COLLISION - 2
Datain(Y) = DIPresent(Y)
Collin(Y)=CIPresent(Y)
EnableTw5
DIPresent(Y)=Idle &
CIPresent(Y)=/SQE &
/COLN,/ANYXN=Idle
DIPresent(Y)=Active &
CIPresent(Y)=/SQE &
Tw5Done &
/COLN,/ANYXN=Idle
{[/COLN=Active +
/ANYXN=Active] &
DIPresent(Y)=Active }
+
CIPresent(Y)=SQE
PARTITION HOLD - 5
Datain(Y) = Idle
Collin(Y)=/SQE
DIPresent(Y)=Active +
CIPresent(Y)=SQE
PARTITION COLLISION W ATCH - 6
Datain(Y) = Idle
Collin(Y)=/SQE
EnableTw5
/COLN=Active +
ANYXN=Active +
CIPresent(X)=SQE
CIPresent(Y)=Idle &
DIPresent(Y)=Idle &
/COLN,/ANYXN=Idle
COLLISION COUNT INCREMENT - 3
CC(Y) = CC(Y) + 1
Datain(Y) = DIPresent(Y)
Collin(Y)=CIPresent(Y)
EnableTw6
CC(Y) >= 31 +
[CIPresent(Y)=SQE &
Tw6Done]
DIPresent(Y)=Idle &
CIPresent(Y)=/SQE
CC(Y) < 31 & /Tw6Done
CIPresent(Y)=/SQE &
DIPresent(Y)=Active &
Tw5Done & /COLN, /ANYXN=Idle
W AIT TO RESTORE PORT - 7
Datain(Y) = Idle
Collin(Y)=/SQE
CC(Y) = 0
CIPresent(Y)=/SQE & DIPresent(Y)=Idle
Figure 3. Partition State Diagram for AUI Port Y
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TC3097-8
Preliminary Data Sheet
2.3.3 Global State Diagram
A single global state machine is implemented for the LEMRIC and operates independently of the auto-partition state machines. The machine state can be read externally on three pins when XRESETZ is high. The table below defines the values assigned to these pins for each state.
XTEST2/GS2 XTEST1/GS1 XTEST0/GS0 State State Name
2.3.3.1 State Diagram Notation and Variables.
=
&
Assign the right side constant or expression result to the left side variable.
Logical ”AND” operate.
+
:
<
{[term]}
Tw1
Datain(P)
Collin(P)
Logical ”OR” operator.
Denotes that a variable assignment expression follows.
Denotes assignment of the expression result following the arrow to the variable preceding the arrow.
Group term for logical evaluation.
Enable Tw1 initializes and start the global Tw1 timer. Tw1Done indicates that the timer has expired.
Tw2 Tw2Done indicates that the Tw2 timer has expired.
AllDatatSent Flag indicating that all the received bits have been sent.
OUT(P) Type of output the LEMRIC is sending to port P.
Values : Idle-The LEMRIC is not transmitting.
Data-The LEMRIC is sending Preamble, data or IDL to port P.
Jam-The LEMRIC is sending Jam to port P.
Status of port P carrier. All AUI and TP ports are considered.
Values : Idle-Port P carrier is not active.
Active-Port P carrier is active.
Status of AUI collision on port P.
Values : /SQE-Port P collision is not active.
SQE-Port P collision is active.
TT(P) Indicates the number of bits transmitted to port P.
Values : Positive integers.
Port(test) Function that returns the identifier of a port-passing test. For example, Port
(TPDatain=Active) returns an integer identifying the active TP port. If more than one port passes the test, Only one of the acceptable values is returned.
Values : Integers from 0 to 8
N N is defined by the Port function (see above). It identifies the port that caused an exit from the ldle state to the Send Data or Receive Collision states.
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M
ONLY1
>1
ANY
ANYXN
ANYXM
ALLXN
ALLXM
TC3097-8
Preliminary Data Sheet
M is defined by the Port function (see above). It identifies the single port that caused an exit from the Transmit Collision to the One Port Left state.
Values : Integers from 0 to 8.
General test, which is true if one and only one port is active due to carrier or collision. All
TP and AUI ports are considered.
General test, which is true if greater than one port is active due to carrier or collision. All
TP and AUI ports are considered.
General test, which is true if one or more ports are active due to carrier or collision. All TP and AUI ports are considered.
General test, which is true if any port other than port N, meets the test condition. For example, TT (ANYXN) < 96 is true if a port other than port N was soured with fewer than
96 bits. All TP and AUI ports are considered.
General test, which is true if any port other than port M, is active due to carrier or collision. All TP and AUI ports are considered.
General test, which is true if all ports other than port N meet the test condition. For example TT (ALLXN) > = 96 is true if all ports other than port N were soured with at least
96 bits. All TP and AUI ports are considered.
General test, which is true if all ports other than port M meet the test condition. All TP and
AUI ports considered.
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July 21. 2003
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Preliminary Data Sheet
Power On
START
BEGIN
UCT
IDLE
Out(ALL) = Idle
Datain(ANY) = Act. &
Collin(ALL) = /SQE
:[N <- Port ( Datain = Act. )]
Collin(ANY) = SQE :[ N <- Port ( Collin = SQE )
SEND PREAMBLE PATTERN
Out(ALLXN) = Preamble Pattern
Collin(N) = SQE + ( Datain(N) = Idle & Collin(ALL) = /SQE )
Collin(ANYXN) = SQE
TT(ALLXN) >= 62 & DataRdy &
Collin(ALL) = /SQE & Datain(N) = Act.
SEND TWO ONES
Out(ALLXN) = TwoOnes
Collin(ANYXN) = SQE
Collin(N) = SQE + ( Datain(N) = Idle & Collin(ALL) = /SQE )
TwoOnes Sent & Collin(ALL) = /SQE &
Datain(N) = Act.
SEND DATA
Out(ALLXN) = Data
Collin(N) = SQE + ( Datain(N) = Idle &
Collin(ALL) = /SQE & AllDataSent &
TT(ANYXN) < 96 )
Collin(ANYXN) = SQE
TRANSMIT COLLISION
Out(ALL) = Jam
Datain(N) = Idle & Collin(ALL) = /SQE &
TT(ALLXN) >= 96 & AllDataSent
Collin(ANYXN) = SQE
RECEIVE COLLISION
Out(ALLXN) = Jam
Collin(ALL) = /SQE & TT(ALL) >= 96 & Tw2Done
Collin(ONLY1) = SQE & TT(ALL) >= 96
:[ M <- Port ( Collin = SQE ) ]
ONE PORT LEFT
Out(ALLXM) = Jam
Collin(ANYXM)
= SQE
Datain(M) = Idle &
Collin(ALL) = /SQE &
Tw2Done
WAIT
StartTw1
Out(ALL) = Idle
Collin(ANY) = SQE +
Tw1Done
Figure 4. Global State Diagram for Multiple TP Ports and AUI Port
Datain(N) = Idle &
Collin(ALL) = /SQE &
TT(ALLXN) >= 96 &
Tw2Done
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Preliminary Data Sheet
2.3.4 Counters and Timers
The counters and timers specified on IEEE 802.3. Section 9, are implemented in the LEMRIC. The function and values chosen for each is described below.
2.3.4.1 Tw1
Tw1 is the wait timer for the “End of Transmit” recovery time and it is 8 bit-times in duration. It starts when the LEMRIC ends transmission of a packet and prevents the LEMRIC from receiving this transmission
(loop-back energy from the MAU) as a new receiving entity.
2.3.4.2 Tw2
Tw2 is the wait timer for the end of carrier recovery time and is 3 bit-times in duration. It starts when collision on AUI port has ended. Tw2 prevents the LEMRIC from premature detecting the true end-of-collision due to signal uncertainty on the segment at the end of a collision.
Refer to the following figure. If a collision (SQE) is detected on AUI segment, the Tw2 timer becomes armed. Tw2 begins timing when collision is idle (/SQE). After Tw2 is done, the timer remains idle until the next AUI collision.
RESET
IDLE
Tw2Done
Collin(ANY)=SQE
ARM
Tw2NotDone
Collin(ALL)=/SQE
Enable Tw2
TIMING
Tw2=Done
Figure 5. Tw2 State Diagram.
2.3.4.3 Tw3
Tw3 is the wait timer for length of continuous output and it has duration of 65536 bit-times . It starts when transmission of a packet begins. If Tw3 expires before the end of packet transmission, the LEMRIC enters the MAU jabber lockup protection condition and interrupts transmission for period Tw4. Refer to the figure 6 for further details.
2.3.4.4 Tw4
Tw4 is the wait timer for time to disable output for MAU jabber lockup protection and it has duration of 96 bit-times . It starts d when Tw3 expires. While Tw4 is active, transmission to all ports is disabled. The global state machine is reset to the idle state, the FIFO controller is also reset, and the clock recovery circuit continues to decode the incoming data stream. If the port is still active when Tw4 expires, the
LEMRIC will resume transmission beginning with preamble.
The MAU lockup LED (XJABLED) is turned on to indicates the suspension of transmission. Refer to the following figure.
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Preliminary Data Sheet
R E S E T
ID L E
D isa b le O u t= O F F
O U T (A N Y )= A ctive
O U T (A L L )= Id le
T IM E O U T P U T
D is a b le O u t = O F F
E n a b le T w 3
T w 3 = D o n e & O U T (A N Y )= A ctive
D IS A B L E O U T P U T
D isa b le O u t = O N
E n a b le T w 4
T w 4 = D o n e
F ig u re 6 . M A U ja b b e r L o c k u p P ro te c tio n S ta te D ia g ra m
2.3.4.5 Tw5
Tw5 is the auto-partition wait timer for length of packet without collision and it has duration of 512 bit-times. It starts when carrier (or collision on AUI ports) from a port becomes active. If a collision is detected before Tw5 expires, the collision count for that port is incremented and the port Tw6 timer will be started. Tw5 is also used in the auto-partition algorithm to exit the Partition collision Watch state. A separate Tw5 timer is implemented for each of the TP and AUI ports.
Refer to the auto-partition state diagrams for specific timer operation.
2.3.4.6 Tw6
Tw6 is the auto-partition wait timer for excessive length of collision and it has duration of 1024 bit-times.
It starts if a collision (multiple active port or SQE) is detected before Tw5 expires. If the collision condition persists when Tw6 expires. The energy and data from that port are partitioned (jabbed). A separate Tw6 timer is implemented for each of the TP and AUI ports.
Refer to the auto-partition state diagrams for specific timer operation.
2.3.4.7 Collision counter
The collision counter maintains the number of consecutive collisions for a particular port. If the collision limit is reached, the energy and data from that port are partitioned (jabbed). A separate collision counter with limit 31 is implemented for each of the TP and AUI ports.
2.3.4.8 Transmit Timer
The transmit timer counts the number of bits transmitted to a port. If the total number of bits transmitted is less than 96 (due to reception of a packet fragment), the LEMRIC will enter the Receive Collision global state and transmit Jam until the transmit timer reaches a count of 96. There by extending the bit stream to greater or equal to 96 bits time.
The transmit timer is cleared when the LEMRIC enters the Transmit Collision global state. This ensures that at least 96 bits of jam signals are transmitted to all ports before the LEMRIC exits the Transmit
Collision state. This also means that the LEMRIC will have transmitted more than 96 bits of jam signals to all but one port if the transmit collision state was entered from the Receive collision state. Refer to the following figure and the global state diagrams for transmit timer operation.
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RESET
TTIDLE
TT(X) = 0
OUT(X)=Active & Bit Transmitted
COUNTING
TT(X) = TT(X)+1
TC3097-8
Preliminary Data Sheet
HOLD
TT(X)
Bit Transmitted
OUT(X) = Idle+
Global Stats S - > Tcollision
Figure 7. Transmit Timer State Diagram for Port X.
2.3.5 Automatic Preamble Regeneration
Automatic preamble regeneration (APRG) prevents the preamble from shrinking as a packet is passed from repeater to repeater or station to station. This shrinking, or loss of bits, is due to the bit cost of determing the presence of carrier and synchronizing of the Manchester data for NRZ data and clock recovery. The LEMRIC compensates for the bit loss by transmitting greater or equal to 56 bits of preamble before sending the Start of Frame Delimiter (SFD) pattern.
2.3.5.1 APRG Circuit Operation
When carrier is detected, the LEMRIC begins sending preamble and searches for the SFD pattern in the recovered NRZ data. The delay from carrier transition to the first transmitted bit of preamble is four to five bit-times for AUI carrier and eight to nine bit-times for TP carrier. The LEMRIC begins to search for the eight-bit SFD pattern 15 to 16 bits after the carrier transition.
When the SFD pattern is detected, the data followed by the SFD is loaded into a 64-bit FIFO. After the preamble bits are sent, the SFD pattern will be sent next, and then finally the FIFO data will be transmitted. Since at least 56 bits of preamble must be sent, the FIFO must be of sufficient depth to store the data after the SFD pattern. A FIFO depth of 64 is chosen to allow the processing of packet with very few bits of preamble before SFD.
The FIFO watermark is achieved by reloading the FIFO with part of the SFD pattern. A preamble counter maintains the number of preamble bits transmitted, and is implemented such that the total count equals
56 plus the number of SFD bits not reloaded into the FIFO. For a watermark of four bits, the preamble counter counts to 60 (56 preamble bits plus the first four bits of SFD). The received packet must contain at least 16 preambles bits for the LEMRIC to detect SFD. There is no upper limit on the number of preamble bits received.
The latency of bits through the LEMRIC is inversely related to the number of preamble bits received.
That is the data in a packet with a small number (less than 56) of preamble bits must be stored (and therefore be held a longer period of time) until the full preamble can be regenerated.
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For a packet with a large number (greater or equal to 56) of preamble bits, the latency will approach the processing time of the LEMRIC (including watermark) to get a bit from the input through the FIFO to the output. If the number of preamble bits received is greater than 56, the LEMRIC will add up to four preamble bits to the packet for TP carrier and up to eight preamble bits for AUI carrier.
The leading edge of the first preamble bit transmitted by the LEMRIC, as seen on the line. Denotes the beginning of a 100 nanosecond positive (TTL logic one).
2.3.5.2 APRG State Diagram
The following state diagram describes the LEMRIC APRG operation. When carrier is detected, the
APRG circuit waits from four to noise bit-times and then begins sending preamble. The preamble counter
(PC) increments for each preamble bit sent. When the SFD pattern is detected (all eight bits), the data bits are loaded into the FIFO and the SFD pattern is sent. The error paths indicate some sort of packet abort, such as collision, Manchester code violation, FIFO error, or premature end of packet. The state diagram notation is similar to that of the global state diagram.
RESET
IDLE
OUT = Idle
PC = 0
Carrier
Error
PREAMBLE DELAY
OUT = Idle
Delay Complete
Error
LOOK FOR SFD
OUT = Preamble Bit
SFD Detected
: [FIFO < - Data after SFD]
COUNT
PC = PC + 1
Error
PREAMBLE COUNT
OUT = Preamble Bit
PC > = 60
OUT SFD
OUT = Remaining
SFD Bits
PC<60
COUNT
PC = PC + 1
Error
DATA
OUT = FIFO Data
Error+FIFO Empty
Figure 8. State Diagram for Automatic Preamble Regeneration
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Preliminary Data Sheet
2.3.6 Inter-LEMRIC Bus Operation
The Inter-LEMRIC Bus consists of eight signals. These signals implement a protocol, which may be used to connect multiple LEMRICs together. In this configuration, the logical function of a single repeater is maintained. The resulting multi-LEMRIC system is compliant to the IEEE 802.3 Repeater Specification and may connect serval hundred network segments. An example of a multi-LEMRIC system is shown as follow below:
/AC KI
A
BUS SIG N ALS
LEM RIC A
R X
A1
C D
A1
TX
A1
X
C
V
R
NETW O R K
S E G M EN T
B U S C O N TEN TS :
/C O LN
IR C
/IR E
IR D
/AN YXN
/AC TN
/AC KO
A
/AC KI
B
ADDITIO N AL
XC VR S
AN D
SEG M ENTS
LEM RIC B
R X
B1
C D
B1
TX
B1
X
C
V
R
NETW O R K
S E G M EN T
/AC KO
B
ADDITIO N AL
XC VR S
AN D
SEG M ENTS
Figure 9. M ULTI-LEM RICs System Topopogy
The Inter-LEMRIC bus connects multiple LEMRICs to realize the following operations:
Port N Identification (which port the repeater receives data from)
Port M Identification (which port is the last one experiencing a collision)
Data Transfer
RECEIVE COLLISION Identification
TRANSMIT COLLISION Identification
DISABLE OUTPUT (jabber protection)
The following tables briefly describe the operation of each bus signal, the conditions required for a
LEMRIC to assert a signal and which LEMRICs (in a multi-LEMRIC system) would monitor a signal:
ACKI
Function Input signal to the Inter-LEMRIC arbitration chain. This chain is employed to identify PORT N and PORT M.
Note: LEMRIC contains PORT N or PORT M, it may be identified by its
ACKO signal being low when its ACKI input is high.
Conditions required for a
LEMRIC to drive this signal
Not Applicable
LEMRIC Receiving the Signal This is dependent upon the method used to cascade LEMRICs, described in Section 1.3.6.2.
ACKO
Function Output signal from the Inter-LEMRIC arbitration chain.
Conditions required for a This is dependent upon the method used to cascade LEMRICs described
LEMRIC to drive this signal in Section 1.3.6.2.
LEMRIC Receiving the Signal Not applicable
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/ACTN
Function This signal denotes there is activity on PORT M.
Conditions required for a
LEMRIC to drive this signal
A LEMRIC must contain PORT N or PORT M.
Note: Although this signal normally has only one source asserting the signal active it is used in a wired-OR configuration.
LEMRIC Receiving the Signal This signal is monitored by all LEMRICs in the repeater system.
/ANYXN
Function This signal denotes that a repeater port that is not PORT N or PORT M is experiencing a collision.
Conditions required for a
LEMRIC to drive this signal
Any LEMRIC that satisfies the above condition.
Note : This bus line is used in a wired-OB configuration.
LEMRIC Receiving the Signal This signal is monitored by all LEMRICs in the repeater system.
/COLN
Function Denotes PORT N or PORT M is experiencing a collision.
Conditions required for a
LEMRIC to drive this signal
A LEMRIC must contain PORT N or PORT M.
LEMRIC Receiving the Signal The signal is monitored by all other LEMRICs in the repeater system.
/IRE
Function This signal acts as an activity-framing signal for the IRC and IRD signals.
Conditions required for a
LEMRIC to drive this signal
A LEMRIC must contain PORT N.
LEMRIC Receiving the Signal The signal is monitored by all other LEMRICs in the repeater system.
/IRD
Function Decoded serial data, in NRZ format, received from the network segment attached to PORT N.
Conditions required for a A LEMRIC must contain PORT N.
LEMRIC to drive this signal
LEMRIC Receiving the Signal The signal is monitored by all other LEMRICs in the repeater system.
/IRC
Function Clock signal associated with IRD and IRE.
Conditions required for a
LEMRIC to drive this signal
A LEMRIC must contain PORT N.
LEMRIC Receiving the Signal The signal is monitored by all other LEMRICs in the repeater system.
2.3.6.1 Methods of LEMRIC Cascading
In order to build multi-LEMRIC repeaters, PORT N and PORT M identification must be performed across all the LEMRICs in the system.
The top of the chain, the input to Port 1 is accessible to the user via the LEMRIC's /ACKI input pin. The output from the bottom of the chain becomes the /ACKO output pin. In a single LEMRIC system PORT N is defined as the port in the arbitration chain with receive or collision activity. PORT N identification is performed when the repeater is in the IDLE state. In order for the arbitration chain to function, all that needs to be done is to tie the /ACKI signal to a logic high state. In multi-LEMRIC systems there are two methods to propagate the arbitration chain between LEMRICs:
The first and most straightforward way is to extend the arbitration chain by daisy-chaining the
/ACKI-/ACKO signals between LEMRICs. In this approach one LEMRIC is placed at the top of the chain
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Preliminary Data Sheet
(its /ACKI input is tied high), then the /ACKO signal from this LEMRIC is send to the /ACKI input of the next LEMRIC and so on. This arrangement is simple to implement but it places some topological restrictions upon the repeater system. In particular, when the repeater is constructed using a backplane with removable printed circuit boards containing the LEMRICs, If one of the boards is removed then the
/ACKI-/ACKO chain will be broken and the repeater will not operate correctly.
The second method of PORT N or PORT M identification avoids this problem. This second technique relies on an external parallel arbiter, which monitors all of the LEMRIC's /ACKO signals and responds to the LEMRIC with the highest priority. In this scheme each LEMRIC is assigned with a priority level. One method of doing this is to assign a priority number, which reflects the position of a LEMRIC board on the repeater backplane (i.e., its slot number). When a LEMRIC experiences receive activity and the repeater system is in the IDLE state, the LEMRIC board will assert /ACKO. External arbitration logic drives the identification number onto an arbitration bus and the LEMRIC containing PORT N will be identified. An identical procedure is used in the TRANSMIT COLLISION state to identify PORT M. This parallel means of arbitration is not subject to the problems caused by missing boards (I. e., empty slots in the backplane).
The logic associated with asserting this arbitration vector in the various in the various packet repetition scenarios could be implemented in PAL or GAL type devices.
To perform PORT N or PORT M arbitration, both of the above methods employ the same signals: /ACKI,
/ACKO, and /ACTN.
The Inter-LEMRIC bus allows multi-LEMRIC operations to be performed in exactly the same manner as if there is only a single LEMRIC in the system. The simplest way to describe the operation of
Inter-LEMRIC bus is to see how it is used in a number of common packet repetition scenarios.
2.3.6.2 EXAMPLES OF PACKET REPETITION SCENARIOS
Data Repetition
The simplest packet operation performed over the Inter-LEMRIC Bus is data repetition. In this operation a data packet is received at one port and transmitted to all other segments.
The first task to be performed is PORT N identification. In situations where two or more ports simultaneously receive packets the Inter-LEMRIC bus operates by choosing one of the active ports and forcing the others to transmit data. This is done to faithfully follow the IEEE specification's allowed exit paths from the IDLE state (I. e., to the SEND PREAMBLE PATTERN or RECEIVE COLLISION states).
The packet begins with a preamble pattern derived from the LEMRIC's on chip jam/preamble generator.
The data received at PORT N is directed through the receiving multiplexer to the PLL decoder. Once phase lock has been achieved, the decoded data, in NRZ format, with its associated clock and enable signals are asserted onto to IRD, /IRE and IRC Inter-LEMRIC bus lines, This serial data stream is received from the bus by all LEMRICs in the repeater and directed to their Elasticity Buffers. Logic circuit monitors the data stream and look for the Start of Frame Delimiter (SFD).
When this has been detected data is loaded into the elasticity buffer for later transmission. This will occur when sufficient preamble has been transmitted and certain internal state machine operations have been fulfilled.
Figure 11 shows two LEMRICs, A and B, daisy-chained together with LEMRIC A positioned at the top of the chain. A packet is received at port B1 of LEMRIC B and is then repeated by the other ports in the system. Figure 12 shows the functional timing diagram for this packet repetition represented by the signals shown in figure 11. In this example only two ports in the system are shown, obviously the other port also repeat the packet. It also indicates the operation of the LEMRIC's state machines in so far as can be seen by observing the Inter-LEMRIC bus. For reference, the repeater's state transitions are shown in terms of the states defined by the IEEE specification. The location (I. e., which port it is) of
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PORT N is also shown. The following section describes the repeater and Inter-LEMRIC bus transitions shown in figure 10.
(NOTE1*)
RX
A1
CD
A1
(HIGH)
TX
A1
/ACKO
A
(HIGH)
RX
B1
CD
B1
(HIGH)
TX
B1
(HIGH)
/ACKO
B
/ACTN
/ANYXN (HIGH)
/COLN (HIGH)
/IRE
IRD
IRC
INTER-LEMRIC
BUS STATES
IDLE
PORT
ARB'
REPEAT IDLE
SEND PREAMBLE SEND SFD SEND
W AIT
IDLE REPEATER
STATES
IDLE
PORT N XX PORT B1 XX
NOTE 1:The activity shown on RX represents the transmitted signal on TX after being looped back by the attached
A1 A1
.
FIGURE 10. Data
The repeater is stimulated into activity by the data signal received by port B1. The LEMRICs in the system are alerted to forthcoming repeater operation by the falling edges on the /ACKI-/ACKO daisy chain and the
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/ACTN bus signal, following a defined start up delay the repeater moves to the SEND PREAMBLE state.
The LEMRIC system utilizes the start up delay to perform port arbitration. When packet transmission begins the LEMRIC system enters the REPEAT state. The expected, for normal packet repetition, sequence of repeater states, SEND PREAMBLE, SEND SFD and SEND DATA is followed but is not visible upon the Inter-LEMRIC bus. They are merged together into a single REPEAT state. This is also true for the
WAIT and IDLE states; they appear as a combined Inter-LEMRIC bus IDLE state.
Once a repeat operation has begun (I. e., the repeater leaves the IDLE state) it is required to transmit at least 96 bits of data or jam/preamble into its network segments.
If the duration of the received signal from PORT N is smaller than 96 bits, the repeater transitions to the
RECEIVE COLLISION state (described later). This behavior is known as fragment extension. After the packet data has been repeated, including the emptying of the LEMRICs' elasticity buffers, the LEMRIC performs the Tw1 transmit recovery operation. This is performed during the WAIT state shown in the repeater state diagram.
2.3.6.3 EXAMPLES OF PACKET REPETITION SCENARIOS
Receive Collisions
A receive collision is a collision which occurs on the network segment attached to PORT N (i.e., the collision is ”received” in a similar manner as a data packet is received and then repeated to the other network segments). The receiving collision propagation follows a similar sequence of operations as is found with data repetition:
An arbitration process is performed to find PORT N and a preamble/jam pattern is transmitted by the repeater's other ports. When PORT N detects a collision on its segment the /COLN Inter-LEMRIC bus signal is asserted. This forces all the LEMRICs in the system to transmit a preamble/jam pattern to their segments. This is important since they may be already transmitting data from their elasticity buffers. The repeater moves to the RECEIVE COLLISION state when the LEMRICs begin to transmit the jam pattern.
The repeater remains in this state until both the following conditions have been fulfilled:
1. At least 96 bits have been transmitted onto the network,
2. The activity has ended.
Under close examination the repeater specification reveals that the actual end of activity has its own permutations of conditions:
1. Collision and receive data signals may end simultaneously,
2. Receive data may appear to end before collision signals,
3. Receive data may continue for some time after the end of the collision signal.
Network segments using coaxial media may experience spurious gaps in segment activity when the collision signal goes inactive. This arises from the inter-action between the received and collision signal squelch circuits. Implemented in coaxial transceivers, and the properties of the coaxial cable itself. The repeater specification avoids propagation of these activity gaps by extending collision activity by the Tw2 wait time. Jam pattern transmission must be sustained throughout this period. After this, the repeater will move to the WAIT state unless there is a data signal being received by PORT N.
The functional timing diagram, figure 11, shows the operation of a repeater system during a receive collision. The system configuration is the same as earlier described and is shown in Figure 9.
The LEMRICs perform the same PORT N arbitration and data repetition operations as previously described. The system is notified of the receive collision on port B1 by the /COLN bus signal going active.
This is the signal, which informs the main state machines to output the jam pattern rather than the data held in the elasticity buffers. Once a collision has occurred the IRC, IRD and /IRE bus signals may become undefined. When the collision has ended and the Tw2 operation performed, the repeater moves to the WAIT state.
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RX
A1
CD
A1
TX
A1
/ACKO
B
RX
B1
CD
B1
TX
B1
/ACKO
B
/ACTN
(HIGH)
(HIGH)
(HIGH)
(HIGH)
/ANYXN (HIGH)
/COLN
/IRE
(HIGH)
IRD
IRC
IDLE
IDLE
PORT N XX
REPEAT
NOTE 1
RXCOL
RECEIVE COLLISION
PORT B1
IDLE
WAIT IDLE
XX
NOTE1 : SEND PREAMBLE, SEND SFD , SEND DATA
FIGURE 11. Receive Collision
2.3.6.4 EXAMPLES OF PACKET REPETITION SCENARIOS
Transmit Collisions
A transmit collision is a collision that is detected upon a segment to which the repeater system is transmitting. The state machine monitoring the colliding segment asserts the /ANYXN bus signal. The assertion of /ANYXN causes PORT M arbitration to begin. The repeater moves to the TRANSMIT
COLLISION state when the port, which had been PORT N starts to transmit a Manchester encoded 1 on to its network segment. While in the TRANSMIT COLLISION state all ports of the repeater must transmit the 1010... jam pattern and PORT M arbitration is performed. Each LEMRIC is obliged, by the IEEE specification, to ensure all of its ports transmit for at least 96 bits once the TRANSMIT COLLISION state has been entered. This transmit activity is enforced by the /ANYXN bus signal. While /ANYXN is active all LEMRIC ports will transmit jam. To ensure this situation lasts for at least 96 bits, the MSMs (Main state
Machine) inside the LEMRICs assert the /ANYXN signal throughout this period. After this period has elapsed, /ANYXN will only be asserted if there are multiple ports with active collisions on their network segments.
There are two possible ways for a repeater to leave the TRANSMIT COLLISION state. The most straightforward is when network activity (I. e., collisions and their Tw2 extensions) end before the 96-bits enforced period expires. Under these conditions the repeater system may be move directly to the WAIT state when 96 bits have been transmitted to all ports. If the MSM enforced period ends and there is still one port experiencing a collision the ONE PORT LEFT state is entered. This may be seen on the
Inter-LEMRIC bus when /ANYXN is reasserted and PORT M stops transmitting to its network segment.
In this circumstance the Inter-LEMRIC bus transitions to the RECEIVE COLLISION state. The repeater will remain in this state while PORT M's collision, Tw2 collision extension and any receive signals are present. When these conditions are not true, packet repetition finishes and the repeater enters the WAIT state.
Figure 12 shows a multi-LEMRIC system operating under transmit collision conditions. There are many different scenarios which occur during a transmit collision; this figure illustrates one of these. The
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Preliminary Data Sheet diagram begins with packet reception by port A1. Port B1 experiences a collision, since it is not PORT N it asserts /ANYXN. This alerts the MSMs in the system to switch from data to jam pattern transmission.
Port A1 is also monitoring the /ANYXN bus line. Its assertion forces A1 to relinquish its PORT N status, start transmission, stop asserting /ACTN and release its hold on the arbitration signals (/ACKO A and
/ACKI B). The first bit it transmits will be a Manchester encoded ”1” in the jam pattern.
Since port B1 is the only port with a collision, it attains PORT M status and stop asserting /ANYXN. It does however assert /ACTN, and exert its presence upon the arbitration chain (forces /ACKO B low).
The MSMs ensure that /ANYXN stays active and thus forces all of the ports, including PORT M, to transmit to their segments.
After some time, port A1 experience of the packet being received from port A1's segment plus the jam signal the repeater is now transmitting onto this segment. Two packets transmit as one segment, which results in a collision. PORT M now moves from B1 to A1. Port A1 fulfills the same criteria as B1 (I. e., it has an active collision on its segment), but in addition it is higher in the arbitration chain.
RX
A1
CD
A1
TX
A1
/ACKO
/ACKI
A
B
RX
B1
CD
B1
TX
B1
/ACKO
B
/ACTN
/ANYXN
/COLN
/IRE
IRD
IRC
INTER-LEMRIC
BUS STATES REPEAT
SEND DATA
TX TO ALL
TRANSMIT COLLISION
RXCOL
ONE PORT LEFT
IDLE
WAIT
PORT N
OR
PORT M
PORT A1
PORT N
XX PORT B1
PORT M
PORT A1
PORT M
XX
FIGURE 12. Transmit Collision
Eventually the collision on port B1 ends and the /ANYXN extension by the MSMs expires. There is only one collision on the network (this may be deduced since /ANYXN is inactive) so the repeater will move to the ONE PORT LEFT state. The LEMRIC system treats this state in a similar manner to a receive collision with PORT M fulfilling the role of the receiving port. The difference from a true receive collision is that the switch from packet data to the jam pattern has already been made (controlled by /ANYXN). Thus the state of /COLN has no effect upon repeater operation. In common with the operation of the RECEIVE
COLLISION state, the repeater remains in this condition until the collision and receive activity on PORT
M subside. The packet repetition operation completes when the Tw1 recovery time in the WAIT state has been performed.
2.3.6.5 EXAMPLES OF PACKET REPETITION SCENARIOS
Jabber Protection
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TC3097-8-DS-R24
TC3097-8
Preliminary Data Sheet
A repeater is required to disable transmit activity if the length of its current transmission reaches the jabber protect limit. This is defined by the IEEE specification's Tw3 time. The repeater disables output for a time period defined by the Tw4 specification, after this period normal operation may resume.
Figure 13 shows the effect of a jabber length packet upon a LEMRIC based repeater system. The
JABBER PROTECT state is entered from the SEND DATA state. While the Tw4 period is observed the
Inter-LEMRIC bus displays the IDLE state. This is misleading since new packet activity or continuous activity (as shown in the diagram) does not result in packet repetition. This may only occur when the Tw4 requirement has been satisfied.
RX
A1
CD
A1
TX
A1
/ACKO
/ACKI
RX
B1
CD
B1
TX
B1
/ACKO
B
/ACTN
(HIGH)
(HIGH)
(HIGH)
/ANYXN
(HIGH)
/COLN
/IRE
(HIGH)
IRD
IRC
INTER-LEMRIC
BUS STATES
SEND DATA
REPEAT
IDLE
+
PORT ARB
JABBER PROTECT
(NOTE 1*)
REPEAT
SEND PREAMBLE
PORT N
PORT A1 XX PORT A1
Note 1: The IEEE Specification does not have a jabber protect state defined in its main state diagram,this behavior is defined in an additional MAU Jabber Lockup
Protection state diagram.
FIGURE 13. Jabber Protect
2.3.7 Port Block functions
The LEMRIC has 8 port logic blocks (one for each network connection). In addition to the packet repetition operations already described, the port block performs two other functions:
1. The physical connection to the network segment (transceiver function).
2. It provides a means to protect the network from malfunctioning segments (segment partition).
2.3.7.1 TRANSCEIVER FUNCTIONS
The LEMRIC may connect to network segments in two ways:
1. Over AUI cable to transceiver boxes (Port 1)
2. To twisted pair cable via a simple interface.
The first method is only supported by LEMRIC Port 1 (the AUI port). The other is available on Ports 2 to 9.
The LEMRIC contains virtually all the digital and analog circuits required for connection to 10BASE-T network segments. The only optional additional active component is an external drive package. The connection for a LEMRIC port to a 10BASE-T segment is shown in figure 14. The diagram shows the components required to connect one of the LEMRIC's ports to a 10BASE-T segment (and lists a few module P/Ns and vendors). The major components are the integrated filter-transformer-choke module
(or discrete combination of these functions).
The operation of the 10BASE-T transceiver's logical functions may be modified by hardware reset control. The default mode of operation is for the transceiver to transmit and expect reception of link
Confidential. 26/35
Copyright © 2003, IC Plus Corp.
July 21. 2003
TC3097-8-DS-R24
TC3097-8
Preliminary Data Sheet pulses. This may be modified if the XTEST4 pin pulled down (pull down resistor is needed) before hardware reset operation. The port's transceiver will operate normally but will not transmit link pulses nor monitor their reception. Thus the entry to a link fail state and the associated modification of transceiver operation will not occur until another hardware reset and new logic setting on XTEST4 pin.
The on-chip 10BASE-T transceivers automatically detect and correct the polarity of the received data stream. This polarity detection scheme relies upon the polarity of the received link pulses and the end of packet waveform. Polarity detection and correction may be disable through XTEST3 pin pulled down by a resistor before hardware reset operation and the associated modification of transceiver operation will not occur until another hardware reset and new logic setting on XTEST3 pin.
When using external transceivers the user must perform collision detection and the other functions associated with an IEEE 802.3 Media Access Unit. Figure 15 shows the connection between a repeater port and a coaxial transceiver using the AUI type interface.
INTEGRATED
MODULE
TXORA TD+
LPF
TXORB
TD -
1:1
0.047 uF
COMMON
MODE
CHOKES
1:1
XRXI+ RD+
51 Ohm
LPF
XRXI-
RD-
51 Ohm
0.047 uF
Vendor
Pulse Engineering
Bel Fuse
Valor
Filter-Transformer-Choke Modules
PE65424,PE65434,PE65431
0556-2006-00,0556-2006-01
FL1010 (4 Channel),FL1012*,FL1020
* There is a single common mode choke on the transmit channel only.
FIGURE 14 . Port Connection to a 10BASE-T Segment and Some
Typical Filter-Transformer-Choke Modules
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Copyright © 2003, IC Plus Corp.
July 21. 2003
TC3097-8-DS-R24
120 Ohm
L
E
I
M
R
C
XTX1A
XTX1B
XCD1A
XCD1B
120 Ohm
59
Ohm
XRX1A
XRX1B
TC3097-8
Preliminary Data Sheet
59
Ohm
PULSE
X'FORM
DP8392
7
8
TX+
TX -
RR+
RR -
11
12
1K Ohm,1%
78 Ohm
1
2
CD+
CD -
1.5K Ohm x 4
3
6
RX+
RX -
4
VEE
5
13
VEE
VEE
CDS
RXI
TXO
16
14
15
BNC
CONNECTOR
15
HBE
GND
9
10
47 uF
+
1
24
12
13
IN
DC TO DC
CONVERTER
OUT
ISOLATED
GND
GND
10
15
11
14
0.01 uF
0.01 uF 1M Ohm
1/2 W
SPARK
GAP
FIGURE 15. Port Connection to a 10BASE2 Segment ( AUI Interface )
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Copyright © 2003, IC Plus Corp.
July 21. 2003
TC3097-8-DS-R24
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Preliminary Data Sheet
3 Absolute Maximum Ratings
Supply Voltage (VCC)
DC Input voltage (VIN)
DC Output Voltage (VOUT)
Ambient Temperature Under Bias
Storage Temperature Range (TSTG)
Operating Temperature Range
4.75V
-0.5V
-0.5V
0C
-40C
0C to to to to to to
5.25V
VCC+0.5V
VCC+0.5V
70C
125C
70C
Power Dissipation (PD) 250mW to 1150mW
4 D.C. Characteristics
Symbol
VOH
VOL
VIH
VIL
IIL
IIH
VDS
VRON
Description
Minimum High Level Output Voltage
Minimum Low Level Output Voltage
Minimum High Level Input Voltage
Maximum Low Level Input Voltage
Conditions
IOH=-4mA
IOL=8mA
VCC=5V
VCC=5V
Min. Max. Units
2.4 - V
-
2.0
VSS
0.4
VCC
0.8
V
V
V
Input Low Current
Input High current
VIN=1.0V
VIN=VCC
-
-
-0.5
20 uA uA
- mA
Differential Squelch Threshold (XRX1+-, +-190
XCD1+-)
Minimum Receive Squelch Threshold
(Twisted-Pair Port 2-9)
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Preliminary Data Sheet
5 Switching Characteristics
PORT ARBITRATION TIMING
ACKI
T1 T2
ACKO
Symbol
ackilackol T1
Number
ackihackoh T2
Parameter
ACKI Low to ACKO Low
ACKI High to ACKO High
Min
Note : Timing valid with no receive or collision activities.
RECEIVE TIMING-AUI PORTS
Receive activity propagation start up and end delays for ports in non 10BASE-T mode.
Max Units
220 ns
220 ns
RX
T5a T6a
ACTN
T3a T4a
ACKO
Symbol
rxaackol rxiackoh rxaactnl rxiactnh
Number
T3a
T4a
T5a
T6a
Parameter
RX Active to ACKO Low
RX Inactive to ACKO High (Note 1)
RX Active to ACTN Low
RX Inactive to ACTN High (Note 1)
Note : ACKI assumed high
Note 1 : This time includes EOP. & FIFO Data clear time.
RECEIVE TIMING-10BASE-T PORTS
Receive activity propagation start up and end delays for ports in 10BASE-T mode
Min
250
1900
250
1960
RX
Max Units
350
2000
350
2060 ns ns ns ns
T5t T6t
ACTN
T3t T4t
ACKO
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July 21. 2003
TC3097-8-DS-R24
TC3097-8
Preliminary Data Sheet
Symbol
rxaackol rxiackoh rxaactnl rxiactnh
Number
T3t
T4t
T5t
T6t
Parameter
RX Active to ACKO Low
RX Inactive to ACKO High (Note 1)
RX Active to ACTN Low
RX Inactive to ACTN High (Note 1)
Min
550
1300
550
1360
Note : ACKI assumed high.
Note 1 : This time includes EOP. & FIFO Data clear time.
TRANSMIT TIMING-AUI PORTS
Transmit activity propagation start up and end delays for ports in non 10BASE-T mode
CLOCK
Max Units
650
1400 ns ns
650
1460 ns ns
T16a
ACTN
T15a
TX
Symbol
actnltxa clkitxa
Number
T15a
T16a
Parameter
/ACTN Low to TX Active
CLOCK in to TX Active (Note 1)
Min
Note : ACKI assumed high.
Note 1 : Clock not drawn to scale.
TRANSMIT TIMING-10BASE-T PORTS
Receive activity propagation start up and end delays for ports in 10BASE-T mode
CLOCK
T16t
ACTN
T15t
Max Units
260 ns
270 ns
TX
Symbol
actnltxa clkitxa
Number
T15a
T16a
Parameter
/ACTN Low to TX Active
CLOCK in to TX Active (Note 1)
Min
Note : ACKI assumed high.
Note 1 : Clock not drawn to scale.
COLLISION TIMING-AUI PORTS
Collision activity propagation start up and end delays for ports in non 10BASE-T mode
Max Units
260 ns
270 ns
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Copyright © 2003, IC Plus Corp.
July 21. 2003
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TC3097-8
Preliminary Data Sheet
TRANSMIT COLLISION TIMING
ACKO
T29
CD
T30a
T31a
ANYXN
Symbol
cdiackoh cdaanyxnl cdianyxnh
Number
T29
T30a
T31a
Parameter
CD Inactive to ACKO High
CD Active to ANYXN Low
CD Inactive to ANYXN High (Notes 1,2)
Min
450
100
510
Max
550
200
610
Note 1 : TX collision extension has already been performed and no other port is driving /ANYXN.
Note 2 : Includes TW2.
RECEIVE COLLISION TIMING
Units
ns ns ns
CD
T32a T33a
COLN
T38
T39
DATA
JAM
TX
Symbol
cdacoina cdicolni colnljs colnhje
Number
T32a
T33a
T38
T39
Parameter
CD Active to /COLN Low
CD Inactive to /COLN High
/COLN Low to Start of JAM
/COLN High to End of JAM (Note 1)
Min
100
510
Max
200
610
Units
ns ns
300
350 ns ns
Note 1: Reception ended before /COLN goes high.
COLLISION TIMING-10BASE-T PORTS
Collision activity propagation start up and end delays for parts in 10BASE-T mode
TX
RX
T30t T31t
ANYXN
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Preliminary Data Sheet
Symbol
colaanyl colianyh
Number
T30t
T31t
Parameter
Collision Active to /ANYXN Low
Min
550
Collision inactive to /ANYXN High (Note 1) 360
Max
650
460
Units
ns ns
Note 1 : TX collision extension has already been performed and no other port is asserting /ANYXN.
COLLISION TIMING-ALL PORTS
ACTN
ACKI
T41
ANYXN
T34
T40
T35
DATA JAM
TX
Symbol
T34
T35
T40
T41
Number
anylmin anyhtxai anylsj ackihanyh
COLLISION TIMING-ALL PORTS
Parameter
/ANYXN Low Time
/ANYXN High to TX to All Inactive
/ANYXN Low to Start of JAM
ACKI High to /ANYXN High
ACTN
T36
ANYXN
Min Max Units
96
350
300
260 bits ns ns ns
TX
T37
TX one port left
Symbol
T36
T37
Number
actnntxi anyhtxoi
Parameter
/ACTN High to TX Inactive
/ANYXN High to TX ”One Port Left”
Inactive
Note : 96 bits of JAM have already been propagated.
Min Max Units
200 ns
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July 21. 2003
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Preliminary Data Sheet
INTER-LEMRIC BUS OUTPUT TIMING
T105
ACTN
T109
IRE
T110
T106 T103
IRC
T102 T101
IRD
T108
T107
Symbol
ircoh ircol ircoc actnolireol reolirca
Number
T101
T102
T103
T105
T106
Parameter
IRC Output High Time
IRC Output Low Time
IRC Output Cycle Time
/ACTN Output Low to /IRE Output Low
IRD Output Low to IRC Active irdov irdos
T107
T108
IRD Output valid from IRC
IRD Output Stable Valid Time ircohireh ircclks
T109
T110
IRC Output High to /IRE High
Number of IRCs after /IRE High
INTER-LEMRIC BUS INPUT TIMING
IRE
T116
IRC
T111
T114
T115
IRD ircil
Symbol
ircih irdisirc
Number
T111
T112
T114
Parameter
IRC input High Time
IRC input Low Time
IRD input setup to IRC irdihirc ircihireh
T115
T116
IRD input Hold from IRC
IRC Input High to /IRC High
Confidential. 34/35
Copyright © 2003, IC Plus Corp.
T112
90
50
5
Min
40
40
80
10
65
5
Max Units
60 ns
60
120
10
940 ns ns ns ns ns ns ns clocks
Min
30
30
10
10
25 75
Max Units
ns ns ns ns ns
July 21. 2003
TC3097-8-DS-R24
TC3097-8
Preliminary Data Sheet
He
E e b
0.13(0.005) M
A
2
A
1
Y
SYMBOL
e
Hd
D
E
A
1
A
2 b c
He
L
L
1
Y
MIN.
MILLIMETER
NOM.
MAX.
0.05
2.57
0.20
0.10
13.90
19.90
17.75
23.75
0.73
0.25
2.72
0.30
0.15
14.00
20.00
0.65
17.90
23.90
0.88
1.95
0.50
2.87
0.40
0.20
14.10
20.10
18.15
24.15
1.03
0
0.08
10
C
Note:For Exact Dimension,
Please use metric.
Inches are just approximation.
IC Plus Corp.
10F, No.47, Lane 2, Kwang-Fu Road, Sec. 2,
Hsin-Chu City, Taiwan 300, R.O.C.
4F, No. 106, Hsin-Tai-Wu Road, Sec.1,
Hsi-Chih, Taipei Hsien, Taiwan 221, R.O.C.
TEL : 886-3-575-0275 FAX : 886-3-575-0475 TEL : 886-2-2696-1669 FAX : 886-2-2696-2220
Website: www.icplus.com.tw
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TC3097-8-DS-R24
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