Page 1 KSO161 MULTIMEDIA VIDEO OVERVIEW 160

Page 1 KSO161 MULTIMEDIA VIDEO OVERVIEW 160
Kso16 | MULTIMEDIA VIDEO
OVERVIEW 180 OFF
The KS0161 multimedia audio chip represents the state - of - the - art in |
multimedia audio technology. KS0161 combines a high - quality 32 - voice
wavetable synthesizer, a powerful 16 - bit MPU, SoundBlaster ” and MPU-
401 compatibility, and full AD 1848 support into a single chip. The audio
performance of a typical KS0161 system compares favorably to the best
multimedia audio solutions available today, but ata fraction of the cost.
A typical KS0161 system provides 32 voices of 16 -bit, 44. 1Khz sample -
rate wavetavie synthesis, mono and stereo record and playback, Microsoft “
Business Audio” compatibility, MPU - 401 compatibility, SoundBlaster”
PCM compatibility, OPL2™ OPL3™ FM IC interface, a CD - ROM interface
and PC - - compatible joystick port.
FEATURES ORDERING INFORMATION
* High-quality 32-voice wavetable synthesizer Device | Package Temperate
* General MIDI compliant | | KS0161Q | T60-GFP-2828 | 70°C
* Three serial output channels for addition of o
optional audio effects processor APPLICATIONS
s Supports all common CDP D/A formats | |
» Supports up to 32Mbytes of sample memory * MULTIMEDIA AUDIO PRODUCTS
» Supports 8-bit; 16-bit and compressed samples » MUSICAL SYNTHESIZERS
Directly supports ROM, SRAMandDRAM « VIDEO GAME SOUND SYSTEMS
< Dual hardware-based Roland MPU-401 emulations | |
+ Enhanced Analog Devices AD-1848 interface for — RELATED PRODUCTS
digital record and playback
» Supports simultaneous record and playback = — KS0171- НМ 1MB Sample ROM
» 16-bit embedded CPU minimizes host PC overhead « KS0171 - 2M 2MB Sample ROM
e integrated MIDI UART » KM6264B/B/BL - L SK x 8 bit static RAM
* SoundBlaster DSP emulation with hareware ADPCM « KF353 / D/ S Dual Operational Amplifier
« integrated AT-bus CD-ROM interface |
+ ¡BM-compatible joystick interface
« 16-bit MIDI clock with 1uS resolution
» Fully sofware configurable
* Software-controlled SLEEP mode
e Easily adaptable to non-intel hosts
* Stand-alone mode for use without host PC
e Sequoia Development Group synthesizer firmware
s Comprehensive Software Developers Kit
» 160 pin PQFP package
209
XXAMSUNG
ELECTRONICS
KSo161 —
BLOCK DIAGRAM
_MULTIMEDIA VIDEO
— ELECTRONICS
TYPICAL APPLICATION
«пя ОЛ Эа ISOH
I 5120x416 ROM |
1Mx16 ROM |
— ELECTRONICS
Ksote1 0 MULTIMEDIA VIDEO
PIN ASSIGNMENT
1208-71 VDD
J CODRQ
[7] CDIRG
1 Coes
ISE] 1RQ12
— ¡nas
[1 IRQB
J NA
7 SLEEP
HO) BYTE
] MCLK
—] CAST
108€ —] CAST
EL) CABO"
7 RAS"
— WES"
т око
1003 VDD
TM
E MOS
‚| 3 ем
TT] MOHD.
1 MD12
E] MD13
— M4
[71 MDS
1 MAD
О
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8
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O
O
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5
us ИО | Ewan
waz cas co PE 7 MAZ2
HIOR* CO 155 | | —] BASO
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|
8
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ADD [*"'—
SOATS A.
SAT! LS
SDATZ 4
Вск 7
LRCLK CT
RXD I
VOD [— 342
31 77
AGND TY
SBXO Fa:
PXCI 20
смо с 8
MO CY
“OZ 7]
+03 RS
HOA TT
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HOE IL
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HRET C10
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2
ELECTRONICS
~ PIN ASSIGNMENT ( Continued )
Pin# | PinName | Pin# | PinName 14 |. Pin Nam Pina | Pin Name
a
ELECTRONICS
PIN DESCRIPTION
TY
erp Они
TP |
a MULTIMEDIA VID EO
ES Fo étre Bs TO These are the low 12 bt of ho Hosl PO address bas,
thasy plas hos,
fost Adc a Enable. This is the Host PC VO enable. AVS portions (ir
ras DMA cose) are © ignored ary time Us signal is high. For PC ap Hicati
To
"9.2
its [0:7]. These pins are normally connected to the
L Su vit Its Enable pin connected to HDBEN",
= то
— HIORDY
| ESTER sien Ти la the Host PO VO Ready signal. This signal I not normal
used. This signal will never be asserted for longer than than 12uSec. :
HIRO |
134.138,
142
PC application, these pins should be connected d ес
Host interrupt Requseis (67) Thess aro the Host F.C Interrupt 1 Srv
bdge-triggered signals to the Host PC. For maximum compatibility in a
plicati these should be programmed for active high operation. For
| lo any seven IRQ signals.
НОО
122,124,
126, 128,
| Master € Control register can be
Host DMA Requests [5:0] To ln TOO EM ignals.
dgramme: tó generate either active high or active
ı typical ai PC application, these should be
re
123,125, |
127, 128,
431,139
The Host Master Control gon [50] These ar re Fo PC
‘active low signals from the Host PC. In a typical PC application, # these should be
v ook mode ae signals.
accept either active high or
11
“Host PC Data Bus Buffer Enable. This oufput controls tre anal
12D ta othe 7aLS245
‘which buffers the Host PC data bus, This pi is driven low any time any enabled
on-board d peripheral is addressad for sn VO or DMA access.
ЕЕ - -
Oroso our signals are hd a a logie lou level while HRST is drven high them ow,
| the ombedd
| having to first write lo the Host Master Control register. This sugg
To mm 60T stand-alone applications, where no Host PCI is present, if
MPU and synthesizer will be immediately enabled; without a Host PC
= correctly,
that such configurations may use only static memory devices (ROM
This would permit the chip to be used, for example, to build a stand - alone MIDI
synthesizer.
— ELECTRONICS
214
KS0161 02 MULTIMEDIA VIDEO
| a НН - . вы " - Description. | ami —— - — 1
- ADCS" | 48 | O т Codec interface Chip: Select. This sio chip acid for Me external ci
a E | - veill be driver low any time the codec interface is enabled, and the Host PC
de A _makes an VO access within the address range configured for the codec. |
ADIRQ . | 49 | 1 1 “Codec Interface interrupt Request. This is the codec interrupt request input
| to the interrupt selection logic. The Host Codec Configuration registers can
| be programmed to accomodate either active high or active low requests from
| the codec. For use with an AD1848-compatible codec, this should be
| | do | ummed for active high operation. |
ADPDRQ 50 | 1 “Codec interface Playback DMA Request. This is the codec playback DMA
a Pt | request input to the DMA selection logic. The Host Codec Configuration
+ registers can be programmed to accept either an active high or active low
1 signal Nom the codec. For use with an AD1848-compatible codec, this should
| regranimos ‘for active high operation.
4 ayback DMA Acknowledge. This is the codes > playback
1 DMA acknowledge output from the DMA selection logic. The Host Codec
— Configuration registers can be programmed to generate either an active high
- | or active low signal to the codec. For use with an AD1848-compatible codec,
cy | this should be programmed for active tow operation. |
... ADCDRO "52 | 1 | Codec inierface Record DMA Request. This is the codec capture DMA
| 1 - request input to the DMA selection logic. The Host Codec Configuration
registers can be programmed to accept either an active high or active low
signal from the codec. For use with an AD1848-compatible codec, this should
ОНО | ‚ | be programmed for active high operation.
ADCDACK 53 | .O |-Codecinteríace Record DMA Acknowledge. This is the codec capture DMA
| + _ Ш acknowledge output from the DMA selection logic. The Host Codec —
| Configuration registers can be programmed to generate either an active high
| or active low signal to the codec, For use with an AD1848-compatible codec,
| this should be programmed for active low operation.
CD-ROM INTERFACE a a
cocs* 1 116 | O | CD-ROM Chip Select. Thisi is the chip select for the CD-ROM interface. it
| | will be driven low any time the CD-ROM interface is enabled, and the Host PC
— makes an O access within the address range configured for the CD-ROM
CDIRQ 117 | CD-ROM interrupt Request, This is the CD-ROM interrupt request input to
| the interrupt selection logic. The Host CD-ROM Configuration register can
| be programmed to accept either an active high or active low signal from the
"CD-ROM. For use with a Sony CD-ROM drive, this should be programmed
for active high operation. For use with a Mitsumi CD-ROM drive, this should
| | | be programmed for active tow operation.
CDDRQ 118 j CD-ROM DMA Request. This is the CD-ROM DMA request input to the DMA
selection logic. The Host CD-ROM Configuration register can be
programmed to accept either an active high or active low signal from the CD-
ROM. For use with any standard AT-bus CD-ROM, this should be
| programmed {or active high operation.
CDDACK 119 O | CD-ROM DMA Acknowledge. This is the CD-ROM DMA acknowledge output
from the DMA selection logic. The Host CD-ROM Configuration register can
be programmed to generate either an active high or active low signal to the
CD-ROM. For use with any standard AT-bus CD-ROM, this should be
programmed for active low operation.
215
ELECTRONICS
MULTIMEDIA VIDEO
Address Bis Bits 24:01. THs Te somal memory address
I “bus. ‘When accessing static memory devices (ROM/SRAM), these pins
| will contain a stable address throughout the entire memory cycle. When
accessing dynamic memory, pins MAJD:11] will contain the multiplexed
{ _DRAM address.
nory Data Bus Bit [15:0]. This is the external memory data bus.
jemory Upper Byte Write Enable. When this signal ls low during an
external memory access, H indicates that data bits MDf8:15] should be
102
- | written to the addressed memory device. |
‘Enable. When this signal is low during an
ory Lows Byte Wit
| extemal memory access, H indicates that deta bits MDYO-7] should be
: wikio 49 the addresse memory device.
103
y Row Address Strobe. This signal is the Row Address
ВЕ Strobe for all external DRAM. When a DRAM device is addressed, this
“signal will be driven low shortly after the row address has been placed on
| MA(0-11). It will also be driven low during ROM/SRAM cycles to provide
| CAS before: RAS afresh for any DRAM devices In the system.
СА5[3:0°
107.104
| 13:01 When a DRAM device is addressed, one of these signals will be
driver low shortly after the column address has been placed on MA[0-11).
It will also be driven tow during ROM/SRAM cycles to provide CAS-before-
— RAS refresh for any DRAM devices in the system. When a ROM or SRAM
| device is addressed, one of these signals will be drivan low shortly after the
| address has been | IC
on MAJ0:24].
‚ 108
1 Memory Clock. "MPU and synihesizer extemal memory assesses are: 1
This signal indicates which device currently has control of the
| memany bus. When tow, the MPU has control of the memory bus, when
1 high, the synthesizer has control of the memory bus.
~ OSC
"CLOCK INPUT _
42
16 5344 ME Osciliator Buffer Input. This input ve normaily be connected
to one side of a 16.9344MHz crystal, with a 20pF capacitor to ground. —
— desired, an extemally generated 16.9344MHz clock may be connected to
this pin instead. Note that due to internal analog circuitry, the chip may
not behave reliably if this clock input is not close to the design frequency.
Osco’
16.9344 MHz Oscillator Buffer Out. This input will normally be connected to
one side of a 16.9344MHz crystal, with a 20pF capacitor to ground. the
OSCI pin is being driven by an externally generated clock, this pin should be
tefl unconnected.
ELECTRONICS
To 216
Ksot61 ~~ MULTIMEDIA VIDEO
e EA Comveror Seal Dais [20 ear mo he reo coral da os
synthesizer core. Three outputs are provided so that one “dry”
channel, and two separate effects channels can be provided by an external
audio effects processor. In a minimum configuration, with no effects
external processor, SDATO would be connected to the data input of an
| external 16-bit stereo serial D/A converter, while SDAT[1:2] would be left
pi м ar tor Bit Clock. This is the bit clock for the exdernal serial D/A
© LRCLK 33 | oo D/A Converter LR Clock. This is he LR clock Tor the external serial D/A
a | | | converter for the synthesizer. |
217
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ELECTRONICS
E ara ri ea T°
KS0161 202 — MULTIMEDIA VIDEO
Ат Мале | Pin# ] Type | _— Description
“vos: 12 | 6 TorPi.2/0PL-3 Chip Select This pine a Tl docoded op selec fo |
| || comectiontoanortemal oPL2 oi OPL-3 FM 5 or, is
ble e the addition of an OPL-2 or OPL-3.
HXCR:0) | 16.13 | O Host External Control Bits [3:0]. These are general purpose digital output pins
LL | | which may be used to control any non-standard extemal peripherals or
| devices. These bits are controlled by the Host PC by writing to the Host
L- Indirect Address. Register.
PXC[4:0] 7 17 | o | MPU Extemal Control Bits [4:0]. These are general purpose digital output pins
Eo | which may be used to control any non-standard external peripherals or
| devices. These bits are controlled by the embedded MPU.
RXD T 39 | 1 _ —MIDI Receive Data. This is the TTL-lovel serial iápu to the 31 26 KBAUD
| МЮ! ЧАЯТ. Рог normal MIDI communication, this pin must be driven by an
— external opto-isolator from the current-loop MIDI line.
TXD 45 o TTL MIDI Transmit Data. This is the TTL-level serial output from the 31.25
kBAUD MIDI UART. For normal MIDI communication, this pin must drive an
-extemal voltage-lo-current converter to drive the current-laop MIDI line.
BAS(1:0] 47.46 | | | Board1D Select [1:0]. Under normal conditions, these pins may be
connected directly to GND. In this configuration, the base address of all on-
chip peripherals may be selected using the software base address selection
mechanism. litis desired ta run more than one board in a single machine,
these pins allow each of up to four boards to be given a unique ID by XORing
the low bits of the ID byte with these pins. Refer to the KS0161 Applications
1 Programmers Reference for mora details.
DWT* 109 O | MPU Data Wait Status. This signal will be driven low during any MPU data
read or write cycle.
BYTE 110 O | MPU Byte Memory Access Status. This signal will be driven high during any
MPU byte memory access.
SLEEP 111 O SLEEP Status. This signal will be driven high any time the embedded MPU
has placed the KS0161 chip in the SLEEP state,
NMI 112 ! - Non-Maskable Interrupt. — This is the non-maskable interrupt input to the
embedded MPU. This input is rising edge triggered. in normal use, this pin
should be tied to GND.
IRQS 113 | i interrupt Request 5. This is he level 5 interrupt request input to the
embedded MPU. In normal use, this pin should be tied to GND.
IRQS 114 i Interrupt Request 9. This is the level 9 interrupt request input to the
N embedded MPU. In normal use, this pin should be tied to GND.
RQ12 115 | interrupt Request 12. This is the level 12 interrupt request input to the
| | embedded MPU. In normal use, this pin should be tied to GND.
TEST 159 TEST Pin - Manufacturing Test Pin. For normal operation, this pin must be
tied to GND. Applying power to the device with this pin floating or tied to a
logic high level may cause permanent damage to the device.
218
ELECTRONICS
[Pin Name | PINE LIfe L | Description — _ J
| AVoo 33 | rv] | “Analog power Supply for Joystick interface. This pin should be conneciad
+ | - | to a clean +5V source. only digital Mon Is Svalahle, it should be
“isolated by a series resistance, and adequat Excessive
noise inroduced on this pin can cause etic operation ofthe on-chip
AGND A GND. “Analog ground for joystick interface. This pin should be conneciad lo a
- - - | clean-GND source. A suitable connectic would be a large trace .
| connected directly to the shell of the joystick DB-15 оплески
so Excossive noue Introduoed on tie pin can cause ere operation o the
ВЕ 100, 420, 140,
180 В 4
“Vss | 1,23,41,44,61, | GND | Digital ground.
| | 61, 101,121, 141 | ВЕ
219
ELECTRONICS
KSo0161
GENERAL DESCRIPTION
The KS0161 is a highly integrated multimedia audio chip,
designed to act as the core of a complete high -
low - cost multimedia audio system.
The hig consi e complet 32 - voice, 16 - bit, 44.1KHz
‘ sizor, « high - performance 16 - bit MPU,
compatibitie with established stasndard interfaces,
. With lts on = hip MPU, a KSO161 - based
audio board imposes absolutely minimal host MPU overhead. В
ts hardware - based MPU - 401, and SoundBlaster
emulations completely eliminate the memory overhead and
software compatibility and stability problems of TSR - based
emulations. The following sections give a brief description of
the major functional blocks of the KS0161.
Hour PC heruneaca
м necessary ISA bus interface logic is completely contained
- chip. This includes address decoding for all an - board
resource, control, DMA selection and control logic, IRQ
selection and control logic, and all interface configuration
logic. in most casas, the only required external component is
a single 74LS245 tranceiver to buffer the low byte the host
PC dala bus. All PC interface contral logic operates
completely asynchronously to the synthesizer / MPU logic.
АЙ оп - board resources are either I/O or DMA - mapped. Ali
VO addresses are decoded from bits 0 through 11 of the host
PCs address bus. Standard interfacing techniques are used
to provide a highly compatible, reliable interface.
Since the KS0161 supports a large number of peripherals
capable of using interrupis and DMA, very flexible and
efficient DMA and IRQ controllers ar provided. While it is
possible to select a diferent DMA channel and IRQ for almost
every peripheral, in general one or mors sourecs will be
combined into a smaller number of host DMA or IRQ
channels. in this case, the requests from all of the enabled
sources are automatically combined, and a single request is
presented to the host PC, Status and control registers are
provided so that the host PC can easily determine the source
of a request and handle it efficiently.
To allow easy adaptation to virtually any (non - intel ) host
bus, the polarities of most of the host interface signals are
programmable. For example, host bus DMA request and
acknowledge signals may be individually programmed lo be
active high or active low. Similarly, all host bus interrupt
request signals may be programmed to be active high, active
low, or edge triggered. internally, all interrupts, DMA requests
and DMA acknowledges are assumed to be active high. Each
individual input and output signal to / from the host bus may
be optionally inverted to insure the correct polarity at all
points both internally and externally.
ELECTRONICS
| Up to four “host
logic and: total software.
be either B - or 16 - bit.
MULTIMEDIA VIDEO
DMA. channels may bé ‘used
simultansoulsy : one for PCM record, one for PCM
playback, one for SoundBlaster emulation, and one for the
- ROM interface. Fore maximum performance, it is
most desirable to use 16 - bit DMA channeis at all times.
However, for compatibility with existing applications
software and commoniy avallable low - cost codecs, it is
‘also necessary to support 8 - bit DMA.channel musto
always used for SoundBlaster PCM transfers, data
transfers to / form the codec and CD - ROM interace may
Currently, however, no 16 - bit
codecs are available. Multiple interfaces may be directed to
the same DMA channel, but it is up to the applications or
driver software to arbitrate transfers such that no twe
devices attempt to actually transfer data simultaneously
over a single DMA channel. Use of a FIFO - buffered
codec, such as the Analog Devices AD - 1845 or Crystal
CS4231, is highly recommended for best DMA
performance. SoundBlaster DMA transfer are FIFO
buffered in the KSO1€1.
Up to five host IRQs may be simultaneously : one for PCM
record / playback one for SoundBlaster PCM emulation, two
for MPU - 401 emulation, and one for the CD - ROM
interface. These interrupts are separable for COMPE
with existing applications software, but may also all be
vectored to a single IRQ fo simplify “ native” applications
and drivers (i.e . Windows drivers ).
In a typical PC - based applications, the KS0161 starts up
in a passive state, and must be initialized by the post - PC
before normal operation begins. in general, the first step in
the initialization process would be to select the base port
address for each KS0161 in the system. Up to four KS0161
chips or boards may be operated simultaneously in a single
system. A simple sequence of write operations to the
joystick “reset” port allows each chip fo be individually
assigned to a different base address. Refer to the KS0161
Applications Programmers Reference for more details.
To support non - PC based applications, including stand -
alone applications where no host CPU is available, a
provision is made for starting the embedded MPU and
synthesizer directly from power - up. This is accomplished
by driving all four joystick interface button inputs to a logic
low level during the high -to - low transition of the hardware
reset signal.
MPU - 401 Interfaces
The primary interfaces for communicating MIDI data to /
from the host PC are a pair of MPU - 401 emulations. Each
of these provides the full hardware functionality, and partial
software functionality of a real MPU - 401, MPU - 401
UART mode is fully supported. The intelligent - mode
support currently provided is adequate to support virutally
all existing MPU - 401 applications.
220
KS0161
All hardware necessary to suppoet full “intelligent mode * |
present, allowing more complete intelligent ‘mode software
support to be added inthe future en hacer
a necessary.
The first MPU-401 interface [ used exclusively — for
communicating MIDI and command data between the PC and the
n-board synthesizer, The second is used primarily for
communicating MIDI data between the PC and external devices
connected to the on-board MIDI interface available through the
joystick connector on the card bracket. Normally, the MIDI
UART Is under the control of the embedded MPU, so that it can
provide FIFO buffering of MIDI data. - However, the UART
transmitter can also be directly connected to either MPU-401
emulation. This allows UART mode data transfers from the PC
to external MIDI devices to take place with no intervention on the
part of the MPU, although the MPU will still intarcey
MPU-401 command mode data and UART receive data. * в
also possible for the on-board synthesizer to dir
‘MIDI data from external sources, if desired, —
Unlike a real MPL-401, he emulations provide the tranemitter “decor
mone he a ap
can optional capability of ponerating rar
pin
enhanced performance. |
Conac Inrenracen
The codec interface provides. chip-select generation, software
DMA channel selection, and IRQ selection for any AD1848-
compatible codec. “Full-duplex” mode support is also provided,
although for this mode to be actually usable, use of a FIFO-
buffered codec such as the AD1845 or CS4231 is strongly
recommended. Two different VO decodes are provided, both
compatible with selections for the Microsoft Windows Sound
System. The codec capture and playback DMA requests and
acknowledges may be separately vectored to any of 6 host DMA
channels. Both 845 or CS4231 is strongly recommended.
Two different O decodes are provided, both compatible with
selections for the Microsoft Windows Sound System. The
codec capture and playback DMA requests and acknowledges
may
ns for the Microsoft Windocrosoft Windows Sound System. The
codec capture and playback DMA requests and acknowledges
may be separately veciored to any of 6 host DMA channels.
Both 8- andknowledges may be separately vectored to any of 6
host DMA channels. Both 8- and 16-bit DMA channels are
supported, allowing use of a codec with a 16-bit bus interface,
should such a pant become available in the future. The codec
interrupt may be vectored to any one of 7 host interrupt channels.
SOUNDBLASTER DSP EMULATION
SoundBlaster DSP emulation is provided using a combination of
dedicated hardware and firmware executed by the embedded
MPU. All SoundBlaster DSP functions are fully supported
except recording.
playback
SoundBlaster data to the 44.1 kHz synthesizer
“rate. “Direct” output mode is also supported.
MULTIMEDIA VIDEO
The hardware rogistors are fully implemented ith
KS0161, and the embedded
—. process all necessary Si A indi) aha . м
DMA mode. Bite playback le supporte fre
KS0161, using one voice of the synthesizer. ;
Sample
data Is brought info a 4-byle FIFO within KS0181 for
playback. To provide the best possible audio
quality, a synthesizer voice is used to interpolate the
SoundBlaster data to the 44.1 kHz synthesizer output
rate.
brought into a 4-byte FIFO within KSO161 for
: To provide the best poss.
quality, а synthesizer voice is used lo interpalate the
Although SoundBlaster ADPCM
st el upported.
Емагоско MPU
“Direct” output mode is also supported. is
| is nat widely used,
- there are a оон
In sharp contrast to most other low - cost multimedia
audio solutions currently available, the KS0161 does
— not rely on the host PC processor of an extemal
“microcontroller to drive the wavetabie
synthesizer.
Rather, the KS0161 contains a high - performance
purpose - built 16 - bit MPU incorporating such
advanced features as six different addressing modes,
a hardware multiplier, a barrel shifter, and a peak
execution rate of nearly 3 million instructions per
second. in additin to providing optimal synthesizer
audio quality, this reduces host PC CPU overhead.
The considerable memory overhead, compatibility
problems, and erratic audio quality associated with
TSR - based solutions are also completely
aliminated.
In addition to handling the myriad chores associated
with operating the wavetable synthesizer, the
embedded MPU is also responsible for performing
much of the work of SoundBlaster and MPU - 401
emulation. Unlike a purely hardware - based solution,
this makes possible future software updates to
support additional functionality, such as full MPU -
401 intelligent mode support. :
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— ELECTRONICS
221
к$0161 À MULTIMEDIA VIDEO
Зунтивация
The synthesizer isa high - performance 32 - voice, 18 - bit wavetable systems being offered today operate at sample
rates renging anywhere from 22-32KHz, the KS0161 performs al sample processing at full 44.1KHz. in addition,
sn: ; s 8 - and 16 - bit linesr
some other sy uppor ri daly 12 - - bit samples. The KS0161, on the other hand, suppe
samples, and 8 - „and 12 - bit compressed samples. This allows nearly optimal tradeoffs between sample size and
audio quality on a sample - by - sample size and audio quality on a sample - by - - sample basis in the design of the
sample set, resuling In the best possible sound quelly from a given total sample memory size. |
The specification for the synthesize are a follows: |
ELECTRONICS
— 222
JOYSTICK INTERFACE
An PC-compatible joystick interface is provided on-
chip, requiring only resistors, capacitors, and the
connector extematly.
SYSTEM TIMING AND CONTROL
All timing is derived from a 16.9344 MHz crystal
oscillator.
SAMPLE MEMORY INTERFACE
Each memory access cycle consists of 3 cycles of
the 18.9344 MHz master clock, or 177.15 nSec.
This is adequate to allow use of 150 nS ROM, and
80 nSec DRAM. The memory interface supports a
minimum of two and a maximum of four memory
devices, of which at least one must be either SRAM
or DRAM. in: ‘general the MPU will execute entirely
out of ROM, and most, if not all, synthesizer voices
О КОМ accesses by exscuting CAS ERAS
— refresh cycles or ait DRAM banks in parattet with all
ROM/SRAM accesses. For sysiems with ROM-
will also be playing primarily from ROM, altrougt
entirely RAM-based systems are also fully
supported. ROM memory accesses are exploited to
allow DRAM refresh to occur simu aneot
based samples, this scheme provides adequate
refresh for all DRAM in the system. For a totally
DRAM-based system, itis r y to allocate one
synthesizer voice to perform ORAM | refresh. Fora
combined ROM/DRAM system, as long as at least
two voices are playing samples from ROM at all
times, adequate refresh will be provided
automatically, otherwise one voice must be
dedicated to › providing DRAM refresh.
ELECTRONICS
o. 223
REGISTER DESCRIPTION
DIRECT - ADDRESSED REGISTERS
Do MPU - 401 À data.
MPU-401A Dura REGISTER —__
но | ose
as
:
{7:0} © MPU-401 A command.
MPU 401A STATUS gen E. ВЕ | o REAOMINTE
ADDRESS yemowe | BT7 | BIT6 | BT5 | rá | m3 | о вт2 | ered | вто
ll
mi
=
-
se
—
RXRDY Received Data Ready Status
0 = Received data is available in HMAD
1 = Received data is not available.
TXRDY Transmit Data Buffer Ready Status
0 = MPU - 401 is ready to receive next data/command in HMAD or HMAC
1 = MPU - 401 is not ready to receive next data/command
MPU401B Dara REGISTER READ/WRITE
ADDRESS | _ MNEMONIC er? | me BTS | er4 | ers | erz | avi | вто.
D{7:0} MPU - 401 B data.
C7 106 1065 1 C4 16 1 @ | or | co
C{7:01 MPU - 401 B command.
_MPU-AOB Srane REGISTER READ/WRITE
ADDRESS MNEMONIC ar7 | BIT6 er6 | ar4 | ara BT 2 art | aro
BASE + 3 "HMAC | RXRDY | TXRDY | 1 | 1 1 1 1
RXRDY Received Data Ready Status
0 = Received data is available in HMBD
1 = Received data is not available.
TXRDY Transmit Data Buffer Ready Status
— O=MPU-40fis ready to receive next data/command in HMBD or HMBC
1 = MPU - 401 is not ready to receive next data/command
224
ELECTRONICS
KS0161 MULTIMEDIA VIDEO
HIAJ3:0) Host Indirect Register Address. To access the indirect - addressed registers, the index of the desired
register must first be programmed here. The corresponding Indirect register may then be read or written
through the Host indirect Data register ( HID ).
HXC{3:0] Host External Control Bits. These bits are output directly to the HXC 3-0 pins. The Host External Control
Bits are general purpose, uncommitted digital output bits which may be used to control OEM - specific
external functions. lt is, therefore, important for applications programmers to preserve the state dl these
bits when writing to this register.
Hosr \номаст Regs: | | READ/WRITE
ADDRESS | MINEMOMC вт 7 BT | RTE &T4 | 8r3 | anr2 gr1 | вто
BASE +5 _HD- НЮ? | HDS | HIDS | HID4 | HID3 | MIDZ2 | HID1 | HIDO
HID(7:0] Host indirect Register Address. To access the indirect - addressed registers, the index of the desired
register must first be programmed imo the HIA register. The corresponding indirect tegister may then
be read or written through this register.
—SounB nes DSP Resey Recieter | READ/WRITE
ADDRESS | MNEMONC Mr? | ur6 | er5 BT 4 ard | amr? вт! | ero
226H — HSBRST X X X X X X X SBRST
SBRST SoundBlaster DSP Reset Control.
0 = Normal operation
1 = Reset SoundBlaster DSP
Acoress | Wwewowc | or7 | ere | s6 | sá | ers J av2 T ami [| eno
D[7:0] SoundBlaster DSP Receive Data
—ЗоиноВ, латря ОБР Веват Recieren_ READ/WRITE
Anpress | MuEmonc | ви 7 arg | BT6 | Biv4 BIT 3 er2 wr ary |
22CH HSBTD e7 1 ce C5 | e Tae C1 | co
C[7:0] SoundBlaster DSP Receive Data/Command
—SousByasgs DSP wy Ry READ/WRITE
ADDRESS | MNEMONC | | вт 7 _ar6 ars | вт4 Br3 | wr2 BIT 1 вто
22CH HSBTS TXRDY 1 1 1 1 1 1
TXRDY SoundBlaster DSP TXRDY Status
0 = DSP is ready to receive next data/command in HSBTD
1 = DSP is not ready to raceive next data/command
225
SAMSUNI
“ELECTRONICS
Ksoi61 | , MULTIMEDIA VIDEO
RXRDY SoundBiastor DSP RXRDY Status
0 = DSP data is not availabie
4 = DSP is available in HSBRD
226
— ELECTRONICS
KSo161 — MULTIMEDIA VIDEO _
INDIRECT - ADDRESSED REGISTER
Newer Sravos Remsen
je
"INDEX | Muemonic | er7 | 876
pe
ADIP Codec Interrupt Status
{7 Po codec imeriupt le pending
{m rupt is pe
COP CD-ROM interrupt Status a
0 = No CD-ROM imerrupt is pending
1= = CD-ROM interrupt is pending —
MCIP x
0 = No MIDI clock intesrupt is pending
o | _ 1 = MIDI clock intarrupt is pending
MBIP | -—— MPU-401B Interrupt Status a
0 = No MPU-401B interrupt pending
| 1 = MPU-4018 interrupt is pending
MAIP Ш | — MPU-401A interrupt Status
| | 0* NoMPU-401A interrupt is pending
12 MPU401A interrupt is pending
MPU-401 interrupts are cleared by salisfying the transmit or receive data request in the com
interface, or by clearing the corresponding interrupt enables in the MPU-401 Configuration Registers. The MIDI
Clock interrupt is cleared by toggling the MIDI clock enable bit (MCEN) in the Master Control Register (MCR) to 0.
When operating in Edge- Triggered Interrupt Mode, any writs to this register re-arms the interrupt controller, causing
a now Interrupt lo be issued If any interrupt requests are stil pending.
MPU-401A CONFIGURATION REGISTER | | READ/WRITE
INDEX Mwemorc | 87 | ove | вл5 | вл4 | rs | m2 | вп! BIT 0
1 | HMACFG RXIE TXE | o | 0 | 6 | 12 151. 150
RXIE MPU-401A Receive Interrupt Enable
0 = MPU-401A Receive interrupts disabled
1 = MPU-401A Receive interrupts enabled
TXIE MPU-401A Transmit Interrupt Enable
0 = MPU-401A Transmit interrupts disabled
1 = MP{U-401A Transmit interrupts enabled
1S[2:0] MPU-401A interrupt Select
000b = MPU-401A interrupts disabled
001b = MPU-401A uses Host IRQO
010b = MPU-401A uses Host IRQ1
_011b « MPU-401A uses Host IRQ2
100b = MPU-401A uses Host IRG3
1015 = MPU-4D1A uses Host IRQ4
1106 = MPU-401A uses Host IRQS5
111b = MPU-401A uses Host IRQ6
This register is cleared by a hardware or software reset. Note that for MPU-401 compatibility, bit 6 of this register
must be cleared, as a Roland MPU-401 provides only receive interrupts. When bits 0-2 are set to 000b, setting bit 6
or 7 will have no |
effect.
227
ELECTRONICS
MPU-401B CONFIGURATION REGISTER ao | . READIWRITE
INDEX | r3 | er2 | art | sro
я Е ТЕ”
1 = MPU401B Receive interrupts enabled
TXIE MPU-401B Transmit interrupt Enable
0 = MPU-4018 Transmit interrupts disabled
1 = MPU-401B Transmit interrupts enabled
IS[2:0] MPU-401B Interrupt Select |
000b = MPU-401B interrupts disabled
001b = MPU-401B uses Host IRGO
010b = MPU-401B uses Host IRQ1
011b = MPU-401B uses Host IRQ2
100b = MPU-4018 uses Host IRQ3
101b = MPU-401B uses Host IRQ4
110b = MPU-4018 uses Host IRQS
111b = MPU-401B uses Host IRQS
This register is cleared by a hardware of software rest. Note that for MPU-401 compatibility, bit 6 of this register must be
cleared, as a Roland MPU-401 provides only receive interrupts. When bits 0-2 are set to 0006, setting bit 6 or 7 will have no
effect.
CODEC CONFIGURATION REGISTER A : | О READ/WRITE
т CA ADPDO..
ADAS
ADCOf2:0] a. Codec Capture OMA Channel Select
000b => Capture DMA disabled _
001b => Capture uses Host DMA channel 0
010b => Capture uses Host DMA channel 1
011b => > Capture uses Host DMA channel 2
Capture uses Host DMA channel 3
101b => Capture uses Host DMA channel 4
110b => Capture uses Host DMA channel 5
111b => Capture DMA disabled
ADEN Codec Interface Enable
0 => Codec interface Disabled
| 1 => Codec Interface Enabled
ADPD{2:0} Codec Playback DMA Channel Select
000b => Playback DMA disabled
001b => Playback uses Host DMA channel 0
010b => Playback uses Host DMA channel 1
011b => Playback uses Host DMA channel 2
100b => Playback uses Host DMA channel 3
101b => Playback uses Host DMA channel 4
110b => Playback uses Host DMA channel 5
1116 => Playback DMA disabled
This register is cleared by a hardware reset, but is not affected by a software reset. When the ADEN bit is set to 0, none of the
other bite wil havo any effect.
228
ELECTRONICS
KS0161 MULTIMEDIA VIDEO |
BIT 2 Bit 1 вто
СОАКР CD-ROM DMA Acimontege Polriy Sole |
+= CD-ROM DMA à knowleg is active high
CDRQP CD-ROM DMA Request Polarity Select
0 = CD-ROM DMA request is active low
he : CD-ROM qe Polariy Select. active high
1 = Собьс СМА ackmonteno le activa high
ADRQP Codec DMA Request Polarity Select
0 = Codec DMA request is active low
1 = Codec DMA request is active high
| 1= Codec neu request ate high |
ADIS[2:0} Codec Interrupt Select
000b = Codec interrupts disabled
001b = Codec uses Host IRQO
010b = Codec uses Host IRQ1
011b = Codec uses Host IRQ2
100b = Codec uses Host IRQ3
101b = Codec uses Most IRQ4
110b = Codec uses Host ROS
111b = Codec uses Host IRQ6
This register is cieared by a hardware reset, but is not affected by a software reset. When the ADEN bit in HCCA is set to O,
none of the bits in this register will have any effect. For use with an AD1848-compatible codec, set ADIP to 0, ADROP to 1,
and ADAKP to D. For the Sony and Mitsurni CD-ROM interfaces, set CORQP to 1, and CDAKP to 0.
CD-ROM INTERFACE CONFIGURATION REGISTER = E. _ READ/WRITE
INDEX. | Muemonc 1 er7 | ere BTS CU | em0
5 | HCDC | _CDIP | Cois2 | as
СОР | CD-ROM Interrupt Request Polarity Select
0 => CD-ROM interrupt request is active low
1 => CD-ROM interrupt request is active high
CDIS[2:0] CD-ROM IRQ Select — —
000b => CD-ROM interrupt disabled
0015 => CO-ROM uses Host IRQO
010b => CD-ROM uses Host IRQ1
011b => CD-ROM uses Host IRQ2
100b => CD-ROM uses Host IRQ3
101b => CD-ROM uses Host IRQ4
110b => CD-ROM uses Host IRQS
111b => CD-ROM uses Host IRQS
CDEN CD-ROM Interface Enable
0 =» CD-ROM interface disabled
. 1 => CD-ROM interface enabled
229
ELECTRONICS
KSO161 ~~ © MULTIMEDIA VIDEO
ADISRY
010b = Codec uses Host IRQ
011b = Codec uses Host IRQ2
100b = Codec uses Host IRQ3
101b = Codec uses Host IRQ4
110b = Codec uses Host IRQS
111b = Codec uses Host {RQ6
This register is cleared by a hardware reset, but is not affected by a software reset, When the ADEN bit in HCCA is
set to 0, none of the bits in this register will have any effect. For use with an AD1846- |
0, ADROP to 1, and ADAKP to 0. For the Sony and Mitsumi CD-ROM interfaces, set CORQP fo 1, and CDAKP to
0.
CD-ROM INTERFACE CONFIGURATION REGISTER — ——— ___READ/WRITE
_INpEX | Mwemowc | BT 7 | ers | ord | e 71 | вл О
re MC]
СОР CD-ROM interrupt Request Polarity Select |
0 => CD-ROM interrupt request is active low
1 => CD-ROM interrupt request is active high
CDIS[2:0] CD-ROM IRQ Select
000b => CD-ROM Interrupt disabled
001b => CD-ROM uses Host IRQO -
010b => CD-ROM uses Most IRQ1
011b => CD-ROM uses Host IRQ2
100b => CD-ROM uses Host IRQ3
101b => CD-ROM uses Host IRQ4
110b => CD-ROM uses Host IRQS
o - 1» CD-ROM uses Host ROS
CODEN CD-ROM interface Enable
0 => CD-ROM interface disabled
1 => CD-ROM interface enabled
cosa
| 001b = “> > CD. ROM uses Host DMA channel 0
010b => CD-ROM uses Host DMA channel 1
011% => CD-ROM usos Host DMA channel 2
100b => CD-ROM uses Host DMA channel 3
1015 => CD-ROM uses Host DMA channel 4
110b => CD-ROM uses Host DMA channel 5
1115 => CD-ROM DMA disabled ©
This register is cleared a hardware reset, but is not affected by a software reset. When CDEN is set to 0, none of
the other bits in this register will have any effect. For the Sony CDU-314 interface, set CDIP to 0. For the Mitsumi
interface set CDIP to 1.
— 230
ELECTRONICS
SOUND MEMORY CONFIGURATION REGISTER A
MDC3 © Memory Device 3 Type
| 0 => Memory device 3 is ROM or SRAM
1 => Memory device 3 is DRAM
MDC2 Memory Device 2 Type
: 0 => Memory device 2 is ROM or SRAM
1 => Memory device 2 is DRAM
MDC1 Memory Device 1 Type
| a 0 => Memory device 1 is ROM or SRAM
| 1 => Memory device 1 is DRAM
MDCO Memory Device Type |
о 0 => Memory device 0 is ROM or SRAM
1-#> Memory device 0 is DRAM
This register is cleared by a hardware reset, but is not affected by a software reset. tn order for the memory interface circulty
fo operate correctly, the type of memory device connected to each device select line (CASO-CAS3) must be known.
Configuring a particular memory device as DRAM enables proper address MUXing, and CAS-bafore-RAS refresh.
SOUND MEMORY CONFIGURATION REGISTER B a - READ/WRITE
inpex | „MNEMONIC | er7 | er6 | впб | aTt4 | 83 aT2 | ert | вто
7 | tws | 03st — | st | D2so | 0151 | 0150 | 0051 | Dos:
D3S[1:0} o DRAM On CAS3 Size Select
00b => DRAM on CAS3 is 64K
01b => DRAM on CAS3 is 256K
10b => DRAM on CAS3 is 1M
= | 11b => DRAM on CAS3 is 4M
D2S{1:0} DRAM On CAS? Size Select _ _
| - 00b => DRAM on CAS? is 64K
01b => DRAM on CAS2 is 256K
10b => DRAM on CAS2 is tM
11b => DRAM on CAS2 is 4M
D1S[4:0} | DRAM on CAS1 Size Setect
006 => DRAM on CAS1 is 64K
01b => DRAM on CAS1 is 256K
10b => DRAM on CAS1 is IM
11b => DRAM on CAS1 is 4M
DOS[1:0] DRAM On CASO Size Select
00b => DRAM on CASO is 64K
01b => DRAM on CASO is 256K
10b => DRAM on CASO is 1M
11b => DRAM on CASO is 4M
This register is cleared by a hardware reset, but is not affected by a sofiware reset. For all memory devices
configured in HMCA as DRAM, it is essential that this register be programmed to reflect the correct device size to
allow proper address MUXing to take place. For memory devices configured in HMCA as ROM/SRAM, the
corresponding bits in this register are ignored.
231
ELECTRONICS
Kso161 __ MULTIMEDIA VIDEO
CDAS[1:0] CD-ROM Base Address/Size Select
005 => СО-КОМ at Base + 6 thru Base + 7
-Q1b => CD-ROM al Base + 8 thru Base + 15
10b => CD-ROM at Base + 16 thru Base + 31
11b=> CD-ROM at Base + 16 thru Base + 47
JSEN Joystick interface Enable |
— 0 => intemal joystick interface is disabled
| 1 => intemal joyStick interface is enabled
SBIS[1:0] SoundBlaster {RQ Select |
00 => SoundBlaster interrupt disabled
01 =» SoundBlaster uses Host IRQ1 (normally PC IRQ2)
10 => SoundBlaster uses Host IRQ2 (normally PC IRQS)
11 => SoundBlaster uses Host IRQ3 (normally PC IRQ7)
SBDS. o | SoundBlaster DMA Channel Select | |
‚ | 0=> SoundBlaster uses Host DMA channel O (°C DMA channel 1)
a sundBlaste ‘uses Host DMA channel 2 (PC DMA channel 3)
SBEN[1:0] | SoundBlaster Emulation Mode Select:
00b => SoundBlaster disabled
01b => SoundBlaster + extemal OPL-2 enabled
Bits 0-5 о! this register are cleared by a hardware of a software reset, Bits 6-7 are cleared only by a hardware reset.
The SBEN bits select the overall SoundBlaster emulation mode. ff SBEN=00b, then SoundBlaster emulation is
completely disabled, and any SoundBlaster O or DMA accessas will be ignored. This allows a real SoundBlaster
board to be used, if desired. For the remaining settings, the DSP emulation is enabled and the YCS pin is driven as
either an OPL-2 or OPL-3 chip select. The JSEN bit allows the internal joystick interface to be disabled so that a
more accurate, external interface may be usd instead. -
The CDAS bits allow the location and size of the CD-ROM address decode to be selected. The CD-ROM interface
may be selected to occupy 2, 8, 16 or 32 port addresses. This should be adequate to support any existing
CD-ROM interface or SCSI controller. The CD-ROM interface base address is always relative to the
KS0161 base address. Changing the KS0161 base address will cause the CD-ROM interface to be relocated
accordingly.
MASTER COMTROL REGISTER READIWRITE
INDEX MNEMONIC | вп? | er BTd | втз вт 2 art | вто _
9 1 HMC SRST TEST MOD1 MODO HAKP — HROP
SRST Software Reset
0 => Reset MPU and synthesizer
1 => MPU and synthesizer enabled
MIEN Master Interrupt Enable
0 => Host interrupts disabled
Ш 1 => Host interrupts enabled
MCEN о В MOI Clock: Interrupt Enable -
0 => MIDI clock interrupts disabled
1 => MIDI clock interrupts enabled
TEST Manufacturing Test - Always write as 0
-. 232
ELECTRONICS
KS0161 | MULTIMEDIA VIDEO
IMODI1:0j interrupt Mode Select
00b => Host interrupts are edge sensitive (sharable)
01b => Host interrupts are low level sensitive (sharable)
10b => Host interrupts are low level sensitive (non-sharable)
11b => Host interrupts are high level sensitive (non-sharable)
HAKP Host DMA Acknowledge Polarity Select
a 0 => Host DMA Acknowledge is active low
| - - 1 => Host DMA Acknowledge is active high
| 0 => Host DMA Request is active low
1 => Host DMA Request is active high
This register is cleared by a hardware reset. For the PC, HRQP should be set to 1, and HAKP should be set to 0.
Four different host interrupt interfaces are provided. In Edge Sensitive mode, when an interrupt occurs, a low pul
will be asserted on the host IRQ line. The IRQ lines are driven by tri-state drivers which are enabled only when
outputting the pulse. In this way, multiple boards may share the same IRQ line. When operating in this mode, Ris |
essential that each interrupt handler perform a write to the Host interrupt Status (HIS) register aftér issulng
of-interrupt (EOD to the host machine's interrupt controller. This will cause the interrupt interface to generate
another low pulse on the IRQ line if additional interrupts are still pending.
Í the Sharable Low Level Sensitive mode, Ihe selected IRQ ine fs again driven by a stats deve, che enabled В
only when an interrupt is pending. The selected IRQ line is held low until all pending interrupts
the drivers are enabled only lo drive the IRQ ine LOW, multiple boards may again share the same IRQ line. —
The Non-Sharable Low Level Sensitive and Non-Sharable High Level Sonsitive modes ALWAYS drive the selected
IRQ line, regardiess of whether there are pending intefrupts. Because of this, only a single board may use a given
IRQ line at any one time.
The TEST bit is used only for manufacturing (est, and must never be set to 1. The MCEN bit allows the MIDI clock
interrupt tc be enabled or disabled. The MID! clock is a 16-bit hardware timer with 1uS resolution, which is intended
for controlling MIDI output timing, but can be used for any software timing needs. Refer to the KS0161 Programmers
Reference Manual for details of how to set and use this timer. The MIEN bit, when set to 0, completely disables all
interrupis, regardless of the settings of the individual enables.
The SRST bit, when set to 0, places the embedded MPU, the synthesizer core, and most of the on-chip peripherals
in their reset state. This is exactly equivalent to a hardware reset, except those configuration registers which affect
the Host bus interface and memory configuration are not cleared, thus preserving the signal polarity, DMA and IRQ
selection, and memory device configurations.
ELECTRONICS
ELECTRICAL SPECIFICATION
ABSOLUTE MAXIMUM RATINGS ——
Vv
Vv
+ °C
Temp | | | 455 CA °C
1. Absolute maximum ratings are limiting values applied individually, while all other parameters are within specified operating
2. Functional operation under any of these conditions is not implied.
RECOMMENDED OPERATING CONDITIONS
| Ve | 48 | 80 | +528 | Хх
> — 284
SAMSUNG
ELECTRONICS
KSot61 MULTIMEDIA VIDEO
DC ELECTRICAL CHARACTERISTICS
40 .
est Ъ ‚ ' E
* AR input pins except TEST, JSX1-0, JSY1-0, BAS1-0, HRST, IRQ12, IRQS, IRQS and NM.
AC ELECTRICAL CHARACTERISTICS
235
ELECTRONICS
KSot61 _ MULTIMEDIA VIDEO
ROW/SRAM MEMORY INTERFACE TIMING
DRAM MEMROY INTERFACE TIMING
ELECTRONICS
KS0161 _
Audio Board Design & PCB Layout Guidelines
Overview
Proper analog circuit design and PCB layout are essential to
“achieving oplimun audio performance, as well as acceptable
EMI (FCCNDE) characteristics from PC audio boards, This
document outlines the basic guidelines that should be followed
to ensure acceptable performance in these critical areas. As a
reference, please refer to the evaluation board schematics and
PCB layout.
Design Overview
In order to achieve optimum audio performance, in terms of
signal-to-noise ratio, noise, floor, and distortion, always provide
separate analog and and digital supplies and grounds. All
digital components should be connected to VOD and GND,
directly from the PC bus connectors. Single-ended analog
circuitry, such as D/A converters, codecs, etc, should be
operated from a separate +5V supply which is focally regulated
down from the +12V supply available on the PC bus. All
operational amplifiers should be powered by filtered +12V
supplies derived from the +12V supplies avaitatble on the PC
bus. Operational amplifiers should never be operated from a
single-ended supply. This will not only reduce the dynamic
range and headroom, but also significantly degrade the signal-
to-noise ratio.
Handling Grounds
For optimum audio performance, it would be most desirable to
keep the analog and digital supplies and retums totally isolated
from one another. However, for the sake of EMI (FCC)
performance, it is generally necessary fo keep all supplies
closely coupled. Also, in a PC, there are a limited number of
supplies to work from, and only a single GND. These
conflicting requirements are best met by allowing the digital
and analog retums (GND & AGND) to be directly connected at
only a single location, preferably directly adjacent to the card
bracket. This single connection should be a substantial one, at
lsast 100-200 mils. This connection is indicated in the
Evaluation Board Schematics as a GNDSTRAP componednt.
AC coupling the retrums by means of 1-10nF capacitors
straddiing the perimeter of - the AGND/GND planes,
at intervals of no more than 1-1.5°, should provide the coupling
necessary to prevent EM: problems which can be caused by
the separate ground planes. The DB-15 connector shell must
be securely connected to the GND plane, and the connector
must be securely screwed to the bottom of the bracket, while
the top of the bracket should have a tab which is securely
screwed of riveted to the AGNO plane, thus referencing all
oulgoing signal lines to the (relatively) ciean chassis ground at
the bracket. in past designs, these techniques have
consistently resulted in a > 10d8 margin relative to the FCC
Ctass-B limits.
MULTIMEDIA VIDEO
in the analog section, it is desirable to have two AGND
planes, rather than a & y IND piano, and a single —
| . can be easily routed
tr traces, nce the cuenta wo very lon. Li
and do al signal and poner roting on he two mer
, to minimiza noise plekup from a mi.
In SMT designs, make layers 2 & 4 AGND planes, and
place as much routing as possible on layer 3,
minimizing expose roufing on layer 1. |
The AGND plane should completely underie all analog
codecs. There should be no VDD or GND routing, or
unecessary digital signal ruoting through te ares |
covered by the AGND plane. -
Analog Signal Routing
Proper component is essential to getting optimum
audio performance. All traces should be kept as short
and straight as possible. Avoid running traces parallel
to other traces for other than very short distances. Keep
any digital or clock traces as far as possible from AD
and D/A converters.
To minimiza noise pickup, all routing to op-amp inputs
should be kept as short as possible. Op-amp output
signals are far less critical, being driven by a relatively
low impedance source. Avoid routing op-amp input and
output signals near wach other to prevent feedback
problems. Also, be sure to follow the supply bypassing
guidelines below. never route an analog signal through
a digital area, or vice-versa.
Digital Signal Routing
Use of vias should be minimized, particularly on high
speed signals, such as clocks. For this reason, hand-
routing is striongly recommended, rather than using
an autorouter. Even the auto-routers available today will
use far more vias than an experienced hand-router. Qur
evaluation boards are all completely hand-routed. Keep
all un-buffared PC-bus signals as short as possible,
preferably no more than 1-2". Also rigorously avoid
passing digital signals over any splits in the planes.
Keep all crystals as close as possible to the other
components to which they are connected, and, if
possible,
surround their traces with GND traces. Never allow an
oscillator or clock signal to cross the GND/AGND plane
split! Securely attach, by soldering, the crystal case
to its associated ground plane, usually GND.
SAMSUNG
ELECTRONICS
«287
Supply Bypassing
In the digital section of the board, be sure no Vop pin is
more than about “1” from a bypass capacitor. In the
analog section, this may be relaxed somewhat, but try to
ensure that each supply pin Is within at least 1.5 - 2” of a
bypass copmehor: ro Joe igh and anal sections
a hen ham e opc e pi.
EMI Suppression
Adequate EMI suppression can most easily be achieved
through careful PCB layout, and the use of smal
bo wal Fou wd output signal poe we Si
( relatively ) low imped: More ( 1-1 10
of ) can be connected between these points and AGND
with no appreciable efect on places as close as possible
1 the connectors, and should be places as close as
possible to the connectors, and the traces leaving them
( goint to the conneclors ) should not pass near any un -
fikered traces which might couple - in unwanted high -
MULTIMEDIA VIL
EO
ELECTRONICS
238
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