LMP8646 Precision Current Limiter (Rev. B)
Sample &
Buy
Product
Folder
Support &
Community
Tools &
Software
Technical
Documents
LMP8646
SNOSC63B – FEBRUARY 2012 – REVISED DECEMBER 2014
LMP8646 Precision Current Limiter
1 Features
3 Description
•
•
•
•
•
•
•
The LMP8646 is a precision current limiter used to
improve the current limit accuracy of any switching or
linear regulator with an available feedback node.
1
•
Provides Circuit Protection and Current Limiting
Single Supply Operation
–2-V to 76-V Common-Mode Voltage Range
Variable Gain Set by External Resistor
Adjustable Bandwidth Set by External Capacitor
Buffered Output
3% Output Accuracy Achievable at VSENSE = 100
mV
Key Specifications:
– Supply Voltage Range 2.7 V to 12 V
– Output Current (Source) 0 to 5 mA
– Gain Accuracy 2.0% (max)
– Transconductance 200 μA/V
– Offset ±1 mV (Maximum)
– Quiescent Current 380 μA
– Input Bias 12 μA (Typical)
– PSRR 85 dB
– CMRR 95 dB
– Temperature Range −40°C to 125°C
– 6-Pin SOT Package
The LMP8646 accepts input signals with a commonmode voltage ranging from –2 V to 76 V. It has a
variable gain which is used to adjust the sense
current. The gain is configured with a single external
resistor, RG, providing a high level of flexibility and
accuracy up to 2%. The adjustable bandwidth, which
allows the device to be used with a variety of
applications, is configurable with a single external
capacitor in parallel with RG. In addition, the output is
buffered in order to provide a low output impedance.
The LMP8646 is an ideal choice for industrial,
automotive, telecommunications, and consumer
applications where circuit protection and improved
precision systems are required. The LMP8646 is
available in a 6-pin SOT package and can operate at
temperature range of −40°C to 125°C.
Device Information(1)
PART NUMBER
LMP8646
PACKAGE
BODY SIZE (NOM)
SOT (6)
2.90 mm × 1.60 mm
(1) For all available packages, see the orderable addendum at
the end of the datasheet.
2 Applications
•
•
•
•
•
High-Side and Low-Side Current Limit
Circuit Fault Protection
Battery and Supercap Charging
LED Constant Current Drive
Power Management
Typical Application
RON
CBST
RON
VIN
BST
VIN
ILIMIT
LOUT
CIN
CIN
VO_LOAD
SW
RSENSE
LM3102
SUPERCAP
COUT
VCC
V+
SS
+IN
CSS
+
-IN
RG
FB
LMP8646
V
-
-
V
CG
ROUT
RFBB
VOUT
RFBT
1
An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. PRODUCTION DATA.
LMP8646
SNOSC63B – FEBRUARY 2012 – REVISED DECEMBER 2014
www.ti.com
Table of Contents
1
2
3
4
5
6
7
Features ..................................................................
Applications ...........................................................
Description .............................................................
Revision History.....................................................
Pin Configuration and Functions .........................
Specifications.........................................................
1
1
1
2
3
4
6.1
6.2
6.3
6.4
6.5
6.6
6.7
6.8
4
4
4
4
5
6
7
8
Absolute Maximum Ratings ......................................
ESD Ratings..............................................................
Recommended Operating Conditions.......................
Thermal Information ..................................................
Electrical Characteristics: 2.7 V ................................
Electrical Characteristics: 5 V ...................................
Electrical Characteristics: 12 V .................................
Typical Characteristics ..............................................
Detailed Description ............................................ 13
7.1 Overview ................................................................. 13
7.2 Functional Block Diagram ....................................... 13
7.3 Feature Description................................................. 13
7.4 Device Functional Modes........................................ 15
8
Application and Implementation ........................ 17
8.1 Application Information............................................ 17
8.2 Typical Applications ................................................ 17
9 Power Supply Recommendations...................... 23
10 Layout................................................................... 23
10.1 Layout Guidelines ................................................. 23
10.2 Layout Example .................................................... 23
11 Device and Documentation Support ................. 24
11.1 Trademarks ........................................................... 24
11.2 Electrostatic Discharge Caution ............................ 24
11.3 Glossary ................................................................ 24
12 Mechanical, Packaging, and Orderable
Information ........................................................... 24
4 Revision History
NOTE: Page numbers for previous revisions may differ from page numbers in the current version.
Changes from Revision A (March 2013) to Revision B
•
Added Pin Configuration and Functions section, Handling Rating table, Feature Description section, Device
Functional Modes, Application and Implementation section, Power Supply Recommendations section, Layout
section, Device and Documentation Support section, and Mechanical, Packaging, and Orderable Information
section ................................................................................................................................................................................... 1
Changes from Original (March 2013) to Revision A
•
2
Page
Page
Changed layout of National Data Sheet to TI format ........................................................................................................... 22
Submit Documentation Feedback
Copyright © 2012–2014, Texas Instruments Incorporated
Product Folder Links: LMP8646
LMP8646
www.ti.com
SNOSC63B – FEBRUARY 2012 – REVISED DECEMBER 2014
5 Pin Configuration and Functions
DDC Package
6-Pin SOT
Top View
VOUT
V
-
+IN
1
2
LMP8646
3
+
6
V
5
RG
4
-IN
Pin Functions
PIN
DESCRIPTION
NAME
NO.
VOUT
1
Single-Ended Output Voltage
V-
2
Negative Supply Voltage. This pin should be connected to ground.
+IN
3
Positive Input
-IN
4
Negative Input
RG
5
External Gain Resistor. An external capacitance (CG) may be added in parallel with RG to limit the bandwidth.
+
6
Positive Supply Voltage
V
Submit Documentation Feedback
Copyright © 2012–2014, Texas Instruments Incorporated
Product Folder Links: LMP8646
3
LMP8646
SNOSC63B – FEBRUARY 2012 – REVISED DECEMBER 2014
www.ti.com
6 Specifications
6.1 Absolute Maximum Ratings
over operating free-air temperature range (unless otherwise noted) (1) (1)
MIN
MAX
UNIT
13.2
V
Supply Voltage (VS = V+ - V−)
Differential voltage +IN- (-IN)
Voltage at pins +IN, -IN
6
V
80
V
13.2
V
–6
Voltage at RG pin
-
Voltage at OUT pin
+
V
Junction Temperature (2)
Storage temperature range
–65
V
V
150
°C
150
°C
For soldering specifications see SNOA549
(1)
(2)
Absolute Maximum Ratings indicate limits beyond which damage to the device may occur. Recommended Operating Conditions indicate
conditions for which the device is intended to be functional, but specific performance is not ensured. For ensured specifications and the
test conditions, see the Electrical Characteristics: 2.7 V tables.
The maximum power dissipation must be derated at elevated temperatures and is dictated by TJ(MAX), θJA, and the ambient temperature,
TA. The maximum allowable power dissipation PDMAX = (TJ(MAX) - TA)/ θJA or the number given in Absolute Maximum Ratings, whichever
is lower.
6.2 ESD Ratings
VALUE
Human-body model (HBM), per
ANSI/ESDA/JEDEC JS-001 (1)
V(ESD)
(1)
(2)
Electrostatic discharge
Pins +IN and -IN
±4000
All pins except +IN and IN
±2000
Charged-device model (CDM), per JEDEC specification JESD22C101 (2)
±1250
Machine model
±250
UNIT
V
JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.
JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.
6.3 Recommended Operating Conditions
Supply Voltage (VS = V+ - V−)
Temperature Range
(1)
(1)
MIN
MAX
2.7
12
UNIT
V
–40
125
V
The maximum power dissipation must be derated at elevated temperatures and is dictated by TJ(MAX), θJA, and the ambient temperature,
TA. The maximum allowable power dissipation PDMAX = (TJ(MAX) - TA)/ θJA or the number given in Absolute Maximum Ratings, whichever
is lower.
6.4 Thermal Information
LMP8646
THERMAL METRIC
(1)
DDC
UNIT
6 PINS
RθJA
(1)
4
Junction-to-ambient thermal resistance
96
°C/W
For more information about traditional and new thermal metrics, see the IC Package Thermal Metrics application report, SPRA953.
Submit Documentation Feedback
Copyright © 2012–2014, Texas Instruments Incorporated
Product Folder Links: LMP8646
LMP8646
www.ti.com
SNOSC63B – FEBRUARY 2012 – REVISED DECEMBER 2014
6.5 Electrical Characteristics: 2.7 V
Unless otherwise specified, all limits ensured for at TA = 25°C, VS= (V+ – V-) = (2.7 V - 0 V) = 2.7 V, −2 V < VCM < 76 V, RG=
25 kΩ, RL = 10 kΩ. (1)
PARAMETER
VOFFSET
TEST CONDITIONS
Input Offset Voltage
VCM = 2.1 V
VCM = 2.1 V, –40°C ≤ TJ ≤ 125°C
TCVOS
Input Offset Voltage Drift (4) (5)
VCM = 2.1 V
IB
Input Bias Current (6)
VCM = 2.1 V
eni
Input Voltage Noise (5)
f > 10 kHz, RG = 5 kΩ
VSENSE
Max Input Sense Voltage (5)
VCM = 12 V, RG = 5 kΩ
Gain AV
Adjustable Gain Setting (5)
VCM = 12 V
Gm
Transconductance = 1/RIN
VCM = 2.1 V
PSRR
CMRR
–1
1
–1.7
1.7
1
VCM = 2.1 V, 2.7 V < V < 12 V
85
2.1 V < VCM < 76 V
95
–2 V <VCM < 2.1 V
55
dB
dB
Supply Current
VCM = 2.1 V
380
VCM = 2.1 V, –40°C ≤ TJ ≤ 125°C
2000
VCM = –2 V, –40°C ≤ TJ ≤ 125°C
(1)
(2)
(3)
(4)
(5)
(6)
(7)
VCM = 2.1 V, RG = 500 kΩ
Minimum Output Voltage
VCM = 2.1 V
Maximum Output Voltage
VS = VCM = 3.3 V, RG = 500 kΩ
Minimum Output Voltage
VS = VCM = 3.3 V, RG = 500 kΩ
Sourcing, VOUT= 600 mV, RG = 150 kΩ
(5)
V/µs
610
807
VCM = –2 V
Maximum Output Voltage
µA/V
140 ppm /°C
IS
Max Output Capacitance Load
V/V
2%
0.5
CLOAD
mV
100
3.4%
VCM = 5 V, CG = 4 pF, VSENSE from 25 mV
to 175 mV, CL = 30 pF, RL = 1MΩ
Output current (5)
μA
600
–2%
Slew Rate (7) (5)
IOUT
μV/°C
nV/√Hz
–3.4%
SR
VOUT
mV
200
+
Common-Mode Rejection Ratio
UNIT
20
120
−40°C to 125°C, VCM= 2.1 V
Power Supply Rejection Ratio
MAX (2)
7
VCM = 2.1 V, –40°C ≤ TJ ≤ 125°C
Gm drift (5)
TYP (3)
12
VCM = 2.1 V
Accuracy
MIN (2)
2500
uA
2700
1.1
V
20
mV
22
mV
1.6
V
5
mA
30
pF
Electrical Table values apply only for factory testing conditions at the temperature indicated. Factory testing conditions result in very
limited self-heating of the device such that TJ = TA. No assurance of parametric performance is indicated in the electrical tables under
conditions of internal self-heating where TJ > TA.
All limits are specified by testing, design, or statistical analysis.
Typical values represent the most likely parametric norm at the time of characterization. Actual typical values may vary over time and
will also depend on the application and configuration. The typical values are not tested and are not specified on shipped production
material.
Offset voltage temperature drift is determined by dividing the change in VOS at the temperature extremes by the total temperature
change.
This parameter is specified by design and/or characterization and is not tested in production.
Positive Bias Current corresponds to current flowing into the device.
The number specified is the average of rising and falling slew rates and measured at 90% to 10%.
Submit Documentation Feedback
Copyright © 2012–2014, Texas Instruments Incorporated
Product Folder Links: LMP8646
5
LMP8646
SNOSC63B – FEBRUARY 2012 – REVISED DECEMBER 2014
www.ti.com
6.6 Electrical Characteristics: 5 V
Unless otherwise specified, all limits ensured for at TA = 25°C, VS= V+-V-, V+ = 5 V, V− = 0 V, −2 V < VCM < 76 V, Rg= 25 kΩ,
RL = 10 kΩ. (1)
PARAMETER
VOFFSET
Input Offset Voltage
MIN (2)
TEST CONDITIONS
VCM = 2.1 V
VCM = 2.1 V, –40°C ≤ TJ ≤ 125°C
TYP (3)
–1
1
–1.7
1.7
TCVOS
Input Offset Voltage Drift (4) (5)
VCM = 2.1 V
IB
Input Bias Current (6)
VCM = 2.1 V
12.5
eni
Input Voltage Noise (5)
f > 10 kHz, RG = 5 kΩ
120
VSENSE(MAX)
Max Input Sense Voltage (5)
VCM = 12 V, RG = 5 kΩ
Gain AV
Adjustable Gain Setting (5)
VCM = 12 V
Gm
Transconductance = 1/RIN
VCM = 2.1 V
Accuracy
VCM = 2.1 V
7
–2%
2%
3.4%
Power Supply Rejection Ratio
VCM = 2.1 V, 2.7 V < V < 12 V,
85
Common-Mode Rejection Ratio
2.1 V <VCM < 76 V
95
–2 V < VCM < 2.1 V
55
dB
Slew Rate (7) (5)
VCM = 5 V, CG = 4 pF, VSENSE from 100 mV
to 500 mV, CL = 30 pF, RL= 1MΩ
0.5
IS
Supply Current
VCM = 2.1 V
450
VCM = 2.1 V, –40°C ≤ TJ ≤ 125°C
2100
VCM = –2 V, –40°C ≤ TJ ≤ 125°C
VCM = 2.1 V
Output current (5)
Sourcing, VOUT= 1.65 V, RG = 150 kΩ
CLOAD
Max Output Capacitance Load (5)
6
2800
uA
3030
Minimum Output Voltage
(5)
(6)
(7)
660
3.3
IOUT
(4)
V/µs
939
VCM = –2 V
(2)
(3)
V/V
dB
SR
(1)
μA
µA/V
–3.4%
CMRR
VCM = 5 V, RG= 500 kΩ
μV/°C
140 ppm /°C
+
Maximum Output Voltage
mV
mV
100
−40°C to 125°C, VCM= 2.1 V
UNIT
nV/√Hz
200
PSRR
VOUT
22
600
1
VCM = 2.1 V, –40°C ≤ TJ ≤ 125°C
Gm drift (5)
MAX (2)
V
22
mV
5
mA
30
pF
Electrical Table values apply only for factory testing conditions at the temperature indicated. Factory testing conditions result in very
limited self-heating of the device such that TJ = TA. No assurance of parametric performance is indicated in the electrical tables under
conditions of internal self-heating where TJ > TA.
All limits are specified by testing, design, or statistical analysis.
Typical values represent the most likely parametric norm at the time of characterization. Actual typical values may vary over time and
will also depend on the application and configuration. The typical values are not tested and are not specified on shipped production
material.
Offset voltage temperature drift is determined by dividing the change in VOS at the temperature extremes by the total temperature
change.
This parameter is specified by design and/or characterization and is not tested in production.
Positive Bias Current corresponds to current flowing into the device.
The number specified is the average of rising and falling slew rates and measured at 90% to 10%.
Submit Documentation Feedback
Copyright © 2012–2014, Texas Instruments Incorporated
Product Folder Links: LMP8646
LMP8646
www.ti.com
SNOSC63B – FEBRUARY 2012 – REVISED DECEMBER 2014
6.7 Electrical Characteristics: 12 V
Unless otherwise specified, all limits ensured for at TA = 25°C, VS= V+ - V-, V+ = 12 V, V− = 0 V, −2 V < VCM < 76 V, Rg= 25
kΩ, RL = 10 kΩ. (1)
PARAMETER
VOFFSET
Input Offset Voltage
TEST CONDITIONS
VCM = 2.1 V
VCM = 2.1 V, –40°C ≤ TJ ≤ 125°C
TCVOS
Input Offset Voltage Drift (4) (5)
VCM = 2.1 V
IB
Input Bias Current (6)
VCM = 2.1 V
eni
Input Voltage Noise (5)
f > 10 kHz, RG = 5 kΩ
VSENSE(MAX)
Max Input Sense Voltage (5)
VCM =12 V, RG = 5 kΩ
Gain AV
Adjustable Gain Setting (5)
VCM = 12 V
Gm
Transconductance = 1/RIN
VCM = 2.1 V
Accuracy
VCM = 2.1 V
TYP (3)
1
–1.7
1.7
+
2%
3.4%
140 ppm /°C
85
2.1 V < VCM < 76 V
95
–2 V < VCM < 2.1 V
55
dB
dB
SR
Slew Rate (7) (5)
VCM = 5 V, CG = 4 pF, VSENSE from 100 mV
to 500 mV, CL = 30 pF, RL=1 MΩ
0.6
IS
Supply Current
VCM = 2.1 V
555
VCM = 2.1 V, –40°C ≤ TJ ≤ 125°C
2200
= –2 V, –40°C ≤ TJ ≤ 125°C
VCM = 12 V, RG= 500 kΩ,
Minimum Output Voltage
VCM = 2.1 V
IOUT
Output current (5)
Sourcing, VOUT= 5.25 V, RG = 150 kΩ
CLOAD
Max Output Capacitance Load (5)
V/µs
845
1123
VCM = –2 V
Maximum Output Voltage
V/V
µA/V
–2%
VCM = 2.1 V, 2.7 V < V < 12 V
(5)
(6)
(7)
mV
100
–3.4%
Common-Mode Rejection Ratio
(4)
μA
nV/√Hz
200
Power Supply Rejection Ratio
(2)
(3)
μV/°C
600
1
CMRR
(1)
mV
23
120
−40°C to 125°C, VCM =2.1 V
CM
UNIT
7
PSRR
VOUT
MAX (2)
–1
13
VCM = 2.1 V, –40°C ≤ TJ ≤ 125°C
Gm drift (5)
MIN (2)
2900
uA
3110
10
V
24
mV
5
mA
30
pF
Electrical Table values apply only for factory testing conditions at the temperature indicated. Factory testing conditions result in very
limited self-heating of the device such that TJ = TA. No assurance of parametric performance is indicated in the electrical tables under
conditions of internal self-heating where TJ > TA.
All limits are specified by testing, design, or statistical analysis.
Typical values represent the most likely parametric norm at the time of characterization. Actual typical values may vary over time and
will also depend on the application and configuration. The typical values are not tested and are not specified on shipped production
material.
Offset voltage temperature drift is determined by dividing the change in VOS at the temperature extremes by the total temperature
change.
This parameter is specified by design and/or characterization and is not tested in production.
Positive Bias Current corresponds to current flowing into the device.
The number specified is the average of rising and falling slew rates and measured at 90% to 10%.
Submit Documentation Feedback
Copyright © 2012–2014, Texas Instruments Incorporated
Product Folder Links: LMP8646
7
LMP8646
SNOSC63B – FEBRUARY 2012 – REVISED DECEMBER 2014
www.ti.com
6.8 Typical Characteristics
Unless otherwise specified: TA = 25°C, VS= V+ - V-, VSENSE= +IN - (-IN), RL = 10 kΩ.
2400
3500
2184
3150
1968
2800
2450
1752
-40°C VCM = 2V
25°C
125°C
-40°C VCM = -2V
25°C
125°C
1536
1320
1104
888
IS (A)
IS (A)
3V
5V
12V
2100
1750
1400
1050
672
700
456
350
0
240
3
4
5
6
7 8 9 10 11 12 13
VS (V)
-3
Figure 1. Supply Curent vs. Supply Voltage for VCM = 2 V
-1
1
3
5
7
VCM (V)
9
11
13
Figure 2. Supply Current vs. VCM
100
VCM = 5V, Rg = 10 k:
80
90
CMRR (dB)
PSRR (dB)
VS = 5V, Rg = 10 kÖ
110
60
70
50
30
40
10
20
1
10
100
1k
10k
1
100k
10
FREQUENCY (Hz)
Figure 3. AC PSRR vs. Frequency
Vs = 5V
Vs = 12V
100k
1M
18
11
-114
4
GAIN (dB)
CMRR (dB)
10k
Figure 4. AC CMRR vs. Frequency
-111
-117
-120
-123
-3
-10
-17
-126
-24
-129
-31
-132
Rg = 50k
Rg = 25k
Rg = 10k
-38
-135
-45
40 44 48 52 56 60 64 68 72 76
VCM (V)
Figure 5. CMRR vs. High VCM
8
1k
25
-105
-108
100
FREQUENCY (Hz)
10
100
1k
10k
100k
FREQUENCY (Hz)
1M
Figure 6. Gain vs. Frequency (BW = 1kHz)
Submit Documentation Feedback
Copyright © 2012–2014, Texas Instruments Incorporated
Product Folder Links: LMP8646
LMP8646
www.ti.com
SNOSC63B – FEBRUARY 2012 – REVISED DECEMBER 2014
Typical Characteristics (continued)
Unless otherwise specified: TA = 25°C, VS= V+ - V-, VSENSE= +IN - (-IN), RL = 10 kΩ.
22
0.240
0.192
GAIN ACCURACY (%)
GAIN (dB)
12
2
Vs = 2.7V
Vs = 3.3V
0.144
0.096
0.048
0.000
-0.048
-8
-0.096
-18
-0.144
Rg = 50k
Rg = 25k
Rg = 10k
-0.192
-0.240
-28
10
100
1k
10k
100k
FREQUENCY (Hz)
1M
-2
Figure 7. Gain vs. Frequency (BW = 35 kHz)
Figure 8. Gain Accuracy vs. VCM
0.240
4.0
0.144
RG = 10k
RG = 25k
RG = 50k
3.6
Vs = 5V
Vs = 12V
3.2
0.096
2.8
VOUT (V)
GAIN ACCURACY (%)
0.192
6 14 22 30 38 46 54 62 70 78
VCM (V)
0.048
0.000
-0.048
2.4
2.0
1.6
-0.096
1.2
-0.144
0.8
-0.192
0.4
-0.240
0.0
-2
8
18
28 38 48
VCM (V)
58
68
78
0.1
Figure 9. Gain Accuracy vs. VCM
0.2
0.3
0.4
VSENSE (V)
0.5
0.6
Figure 10. VOUT vs. VSENSE
4.0
1.3
Vcm = 0V
Vcm = 5V, 12V
3.2
VOUT_MAX (V)
VOUT_MAX (V)
3.6
Vcm = 0V
Vcm = 5V
Vcm = 12V
1.2
1.1
1.0
0.9
0.8
2.8
2.4
2.0
1.6
0.7
1.2
0.6
0.8
0.4
0.5
0.0
0.4
0
2
4
6
8
GAIN
10
12
14
Figure 11. VOUT_MAX vs. Gain at Vs = 2.7 V
0
2
4
6
8
GAIN
10
12
14
Figure 12. VOUT_MAX vs. Gain at Vs = 5.0 V
Submit Documentation Feedback
Copyright © 2012–2014, Texas Instruments Incorporated
Product Folder Links: LMP8646
9
LMP8646
SNOSC63B – FEBRUARY 2012 – REVISED DECEMBER 2014
www.ti.com
Typical Characteristics (continued)
Unless otherwise specified: TA = 25°C, VS= V+ - V-, VSENSE= +IN - (-IN), RL = 10 kΩ.
1.80
12
VCM = 0V
VCM = 5V
VCM = 12V
1.74
1.68
VOUT_MAX (V)
VOUT_MAX (V)
10
8
6
4
1.62
1.56
1.50
1.44
1.38
1.32
2
1.26
0
1.20
0
2
4
6
8
GAIN
10
12
14
0
Figure 13. VOUT_MAX vs. Gain at Vs = 12 V
2
4
6
8
VS (V)
10
12
14
Figure 14. VOUT_MAX vs. VS at VCM = –2 V
2.1
VSENSE
Rg = 50k
Rg = 25k
Rg = 10k
VSENSE (100 mV/DIV)
VOUT_MAX (V)
2.0
1.9
1.8
1.7
1.6
1.5
1.4
VOUT (300 mV/DIV)
2.2
1.3
1.2
4
6
8
VS (V)
10
12
14
TIME (0.5 ms/DIV)
Figure 15. VOUT_MAX vs. VS at VCM = 2.1 V
10
VSENSE
Rg = 50k
Rg = 25k
Rg = 10k
VOUT (300 mV/DIV)
VSENSE (100 mV/DIV)
VSENSE
Rg = 50k
Rg = 25k
Rg = 10k
Figure 16. Large Step Response at BW = 1kHz
VOUT (30 mV/DIV)
2
VSENSE (10 mV/DIV)
0
TIME (20 s/DIV)
TIME (500 s/DIV)
Figure 17. Large Step Response at BW = 35 kHz
Figure 18. Small Step Response at BW = 1 kHz
Submit Documentation Feedback
Copyright © 2012–2014, Texas Instruments Incorporated
Product Folder Links: LMP8646
LMP8646
www.ti.com
SNOSC63B – FEBRUARY 2012 – REVISED DECEMBER 2014
Typical Characteristics (continued)
VSENSE
Rg = 50k
Rg = 25k
Rg = 10k
VOUT (30 mV/DIV)
VSENSE (10 mV/DIV)
VSENSE
Rg = 50k
Rg = 25k
Rg = 10k
VOUT (30 mV/DIV)
VSENSE (10 mV/DIV)
Unless otherwise specified: TA = 25°C, VS= V+ - V-, VSENSE= +IN - (-IN), RL = 10 kΩ.
TIME (20 s/DIV)
TIME (100 s/DIV)
Figure 19. Small Step Response at BW = 35 kHz
Figure 20. Settling Time (Rise) at 1 kHz
VSENSE
Rg = 50k
Rg = 25k
Rg = 10k
VOUT (30 mV/DIV)
VSENSE (10 mV/DIV)
VOUT (30 mV/DIV)
VSENSE (10 mV/DIV)
VSENSE
Rg = 50k
Rg = 25k
Rg = 10k
TIME (100 s/DIV)
TIME (5 s/DIV)
Figure 21. Settling Time (Fall) at 1 kHz
Figure 22. Settling Time (Rise) at 35 kHz
VOUT (500 mV/DIV)
VCM (5 V/DIV)
VSENSE
Rg = 50k
Rg = 25k
Rg = 10k
VOUT (200 mV/DIV)
VSENSE (10 mV/DIV)
VOUT
VCM
TIME (5 s/DIV)
TIME (0.2 ms/DIV)
Figure 23. Settling Time (Fall) at 35 kHz
Figure 24. Common-Mode Step Response (Rise) at 35 kHz
Submit Documentation Feedback
Copyright © 2012–2014, Texas Instruments Incorporated
Product Folder Links: LMP8646
11
LMP8646
SNOSC63B – FEBRUARY 2012 – REVISED DECEMBER 2014
www.ti.com
Typical Characteristics (continued)
Unless otherwise specified: TA = 25°C, VS= V+ - V-, VSENSE= +IN - (-IN), RL = 10 kΩ.
VCM (5 V/DIV)
VOUT (500 mV/DIV)
VOUT
VCM
TIME (0.2 ms/DIV)
Figure 25. Common-Mode Step Response (Fall) at 35 kHz
12
Submit Documentation Feedback
Copyright © 2012–2014, Texas Instruments Incorporated
Product Folder Links: LMP8646
LMP8646
www.ti.com
SNOSC63B – FEBRUARY 2012 – REVISED DECEMBER 2014
7 Detailed Description
7.1 Overview
The LMP8646 is a single-supply precision current limiter with variable gain selected through an external resistor
(RG) and a variable bandwidth selected through an external capacitor (CG) in parallel with RG. Its common-mode
of operation is –2 V to 76 V, and the LMP8646 has an buffered output to provide a low-output impedance. More
details of the LMP8646's functional description can be seen in the following subsections.
7.2 Functional Block Diagram
+
V
-IN
+IN
RIN
RIN
LMP8646
-
+
VOUT
+
-
V
RG
7.3 Feature Description
7.3.1 Theory of Operation
As seen from Figure 26, the sense current flowing through RSENSE develops a voltage drop equal to VSENSE. The
high impedance inputs of the amplifier does not conduct this current and the high open-loop gain of the sense
amplifier forces its noninverting input to the same voltage as the inverting input. In this way the voltage drop
across RIN matches VSENSE. The current IIN flowing through RIN has the following equation:
IIN = VSENSE/ RIN = RSENSE*ISENSE/RIN
where
•
IIN
flows
RIN = 1/Gm = 1/(200 µA/V) = 5 kOhm
entirely
across
the
external
gain
(1)
resistor
RG
to
develop
a
voltage
drop
equal
VRG = IIN*RG = (VSENSE/RIN) *RG = [(RSENSE*ISENSE) / RIN]*RG
to:
(2)
This voltage is buffered and showed at the output with a very low impedance allowing a very easy interface of
the LMP8646 with the feedback of many voltage regulators. This output voltage has the following equation:
VOUT =
VOUT =
VOUT =
VOUT =
VRG = [(RSENSE*ISENSE) / RIN]*RG
VSENSE* RG/RIN
VSENSE* RG/(5 kOhm)
VSENSE* Gain
(3)
(4)
(5)
where
•
Gain = RG/RIN
(6)
Submit Documentation Feedback
Copyright © 2012–2014, Texas Instruments Incorporated
Product Folder Links: LMP8646
13
LMP8646
SNOSC63B – FEBRUARY 2012 – REVISED DECEMBER 2014
www.ti.com
Feature Description (continued)
+ VSENSE
RSENSE
+
+IN
-
ISENSE
-IN
RIN
+
+
V
RIN
LMP8646
L
o
a
d
-
IIN
VOUT
VRG
+
-
V
RG
Figure 26. Current Monitor
7.3.1.1 Maximum Output Voltage, VOUT_MAX
The maximum output voltage, VOUT_MAX, depends on the supply voltage, VS = V+ - V-, and on the common-mode
voltage, VCM = (+IN + -IN) / 2.
The following subsections show three cases to calculate for VOUT_MAX.
7.3.1.1.1 Case 1: −2 V < VCM < 1.8 V, and VS > 2.7 V
If VS ≥ 5 V,
then VOUT_MAX = 1.3 V.
Else if Vs = 2.7 V,
then VOUT_MAX = 1.1 V.
7.3.1.1.2 Case 2: 1.8 V < VCM < VS, and VS > 3.3 V
In this case, VX is a fixed value that depends on the supply voltage. VX has the following values:
If VS = 12 V, then VX = 10 V.
Else if VS = 5 V, then VX = 3.3 V .
Else if VS = 2.7 V, then VX = 1.1 V.
If VX ≤ (VCM - VSENSE - 0.25) ,
then VOUT_MAX = VX.
Else,
VOUT_MAX = (VCM - VSENSE - 0.25).
For example, if VCM = 4 V, VS = 5 V (and thus VX = 3.3 V), VSENSE = 0.1 V, then VOUT_MAX = 3.3 V because 3.3 V
≤ (4 - 0.1 - 0.25).
7.3.1.1.3 Case 3: VCM > VS, and VS > 2.7 V
If VS = 12 V, then VOUT_MAX = 10 V.
Else if VS = 5 V, then VOUT_MAX = 3.3 V .
Else if VS = 2.7 V, then VOUT_MAX = 1.1 V.
14
Submit Documentation Feedback
Copyright © 2012–2014, Texas Instruments Incorporated
Product Folder Links: LMP8646
LMP8646
www.ti.com
SNOSC63B – FEBRUARY 2012 – REVISED DECEMBER 2014
7.4 Device Functional Modes
7.4.1 Output Accuracy
The output accuracy is the device error contributed by the LMP8646 based on its offset and gain errors. The
LMP8646 output accuracy has the following equations:
Output Accuracy =
VOUT_THEO - VOUT_CAL
VOUT_THEO
where VOUT_THEO = (VSENSE) x
and VOUT_CALC =
x 100(%)
RG
1/Gm
(VSENSE + VOFFSET) x RG
1/[Gm (1 + Gm_Accuracy)]
Output Accuracy Equations
(7)
For example, assume VSENSE = 100 mV, RG = 10 kOhm, and it is known that VOFFSET = 1 mV and Gm_Accuracy
= 2% (Electrical Characteristics Table), then the output accuracy can be calculated as:
VOUT_THEO = (100 mV) x
VOUT_CALC =
10 k:
= 0.2V
1/(200µ)
(100 mV + 1 mV) x 10 k:
1/[200µ (1 + 2/100)]
Output Accuracy =
= 0.20604V
0.2V - 0.20604V
x 100 = 3.02%
0.2V
Output Accuracy Example
(8)
In fact, as VSENSE decreases, the output accuracy worsens as seen in Figure 27. These equations provide a
valuable tool to estimate how the LMP8646 affects the overall system performance. Knowing this information
allows the system designer to pick the appropriate external resistances (RSENSE and RG) to adjust for the
tolerable system error. Examples of this tolerable system error can be seen in the next sections.
10.0
OUTPUT ACCURACY (%)
9.2
8.4
7.6
6.8
6.0
5.2
4.4
3.6
2.8
2.0
0.0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8
VSENSE (V)
Figure 27. Output Accuracy vs. VSENSE
7.4.2 Selection of the Sense Resistor, RSENSE
The accuracy of the current measurement also depends on the value of the shunt resistor RSENSE. Its value
depends on the application and is a compromise between small-signal accuracy and maximum permissible
voltage loss in the load line.
RSENSE is directly proportional to VSENSE through the equation RSENSE = (VSENSE) / (ISENSE). If VSENSE is small, then
there is a smaller voltage loss in the load line, but the output accuracy is worse because the LMP8646 offset
error will contribute more. Therefore, high values of RSENSE provide better output accuracy by minimizing the
effects of offset, while low values of RSENSE minimize the voltage loss in the load line. For most applications, best
performance is obtained with an RSENSE value that provides a VSENSE of 100 mV to 200 mV.
Submit Documentation Feedback
Copyright © 2012–2014, Texas Instruments Incorporated
Product Folder Links: LMP8646
15
LMP8646
SNOSC63B – FEBRUARY 2012 – REVISED DECEMBER 2014
www.ti.com
Device Functional Modes (continued)
7.4.2.1 RSENSE Consideration for System Error
The output accuracy described in the previous section talks about the error contributed just by the LMP8646. The
system error, however, consists of the errors contributed by the LMP8646 as well as other external resistors such
as RSENSE and RG. Let's rewrite the output accuracy equation for the system error assuming that RSENSE is nonideal and RG is ideal. This equation can be seen as:
System Error =
VOUT_THEO - VOUT_CAL
VOUT_THEO
where VOUT_THEO = (RSENSE x ISENSE) x
and VOUT_CALC =
x 100(%)
RG
1/Gm
[RSENSE (1+Tolerance) x ISENSE + VOFFSET] x RG
1/[Gm (1 + Gm_Accuracy)]
System Error Example Assuming RSENSE is Non-ideal and RG is Ideal
(9)
Continuing from the previous output accuracy example, we can calculate for the system error assuming that
RSENSE = 100 mOhm (with 1% tolerance), ISENSE = 1A, and RG = 10 kOhm. From the Electrical Characteristics
Table, it is also known that VOFFSET = 1 mV and Gm_Accuracy = 2%.
VOUT_THEO = (100 m: x 1A) x
VOUT_CALC =
10 k:
= 0.2V
1/(200µ)
[100 m: (1+1/100) x 1A + 1mV] x 10 k:
System Error =
1/[200µ (1 + 2/100)]
= 0.20808V
0.2V - 0.20808V
x 100 = 4.04%
0.2V
System Error Example Assuming RSENSE is Non-ideal and RG is Ideal
(10)
Because an RSENSE tolerance will increase the system error, we recommend selecting an RSENSE resistor with low
tolerance.
16
Submit Documentation Feedback
Copyright © 2012–2014, Texas Instruments Incorporated
Product Folder Links: LMP8646
LMP8646
www.ti.com
SNOSC63B – FEBRUARY 2012 – REVISED DECEMBER 2014
8 Application and Implementation
NOTE
Information in the following applications sections is not part of the TI component
specification, and TI does not warrant its accuracy or completeness. TI’s customers are
responsible for determining suitability of components for their purposes. Customers should
validate and test their design implementation to confirm system functionality.
8.1 Application Information
The LMP8646 can be driven by many different regulators with a feedback pin and connected to many different
types of loads such as capacititve and resistive. The following sections gives three typical applications of the
LMP8646.
8.2 Typical Applications
8.2.1 Application #1: Current Limiter With a Capacitive Load
CBST
33 nF
RON
RON
51.1 k:
VIN = 18V
CIN
2x10 PF
BST
ILIMIT = ICLOSE_LOOP = 1.5A
VIN
LOUT
10PH
CIN
0.1 PF
IOPEN_LOOP = 2.5A
VO_LOAD = 4.8V
SW
LM3102
COUT
47 PF
10 nF
VCC
RSENSE
55 m:
SUPERCAP
5F
V+ = 6V
5V
SS
+
+IN
-IN V
RG
50 k: R
G
LMP8646
V
0.8V
CSS
10 nF
FB
-
ROUT
160:
RFBB
2 k:
0.1 PF
& 10 PF
CG
1.8 nF
VOUT
RFBT
10 k:
Figure 28. SuperCap Application With LM3102 Regulator
8.2.1.1 Design Requirements
A supercap application requires a very high capacitive load to be charged. This example assumes the output
capacitor is 5F with a limited sense current at 1.5A. The LM3102 will provide the current to charge the supercap,
and the LMP8646 will monitor this current to make sure it does not exceed the desired 1.5A value.
8.2.1.2 Detailed Design Procedure
To limit the capacitor current, first connect the LMP8646 output to the feedback pin of the LM3102, as shown in
Figure 28. This feedback voltage at the FB pin is compared to a 0.8V internal reference. Any voltage above this
0.8V means the output current is above the desired value of 1.5A, and the LM3102 will reduce its output current
to maintain the desired 0.8V at the FB pin.
The following steps show the design procedures for this supercap application. In summary, the steps consist of
selecting the components for the voltage regulator, integrating the LMP8646 and selecting the proper values for
its gain, bandwidth, and output resistor, and adjusting these components to yield the desired performance.
Step 1: Choose the components for the Regulator.
Refer to the LM3102 evaluation board application note (AN-1646) to select the appropriate components for the
LM3102 voltage regulator.
Submit Documentation Feedback
Copyright © 2012–2014, Texas Instruments Incorporated
Product Folder Links: LMP8646
17
LMP8646
SNOSC63B – FEBRUARY 2012 – REVISED DECEMBER 2014
www.ti.com
Typical Applications (continued)
Step 2: Choose the sense resistor, RSENSE
RSENSE sets the voltage VSENSE between +IN and -IN and has the following equation:
RSENSE = VOUT / [(ILIMIT) * (RG / 5kOhm)]
(11)
In general, RSENSE depends on the output voltage, limit current, and gain. Refer to section Selection of the Sense
Resistor, RSENSE to choose the appropriate RSENSE value; this example uses 55 mOhm.
Step 3: Choose the gain resistor, RG, for LMP8646
RG is chosen from the limited sense current. As stated, VOUT = (RSENSE * ILIMIT) * (RG / 5kOhm). Since VOUT = VFB
= 0.8V, the limited sense current is 1.5A, and RSENSE is 55 mOhm, RG can be calculated as:
RG = (VOUT * 5 kOhm) / (RSENSE * ILIMIT)
RG = (0.8 * 5 kOhm) / (55 mOhm* 1.5A) = 50 kOhm (approximate)
(12)
(13)
Step 4: Choose the Bandwidth Capacitance, CG.
The product of CG and RG determines the bandwidth for the LMP8646. Refer to the Typical Performance
Characteristics plots to see the range for the LMP8646 bandwidth and gain. Since each application is very
unique, the LMP8646 bandwidth capacitance, CG, needs to be adjusted to fit the appropriate application.
Bench data has been collected for the supercap application with the LM3102 regulator, and we found that this
application works best for a bandwidth of 500 Hz to 3 kHz. Operating outside of this recommended bandwidth
range might create an undesirable load current ringing. We recommend choosing a bandwidth that is in the
middle of this range and using the equation CG = 1/(2*pi*RG*Bandwidth) to find CG. For example, if the bandwidth
is 1.75 kHz and RG is 50 kOhm, then CG is approximately 1.8 nF. After this selection, capture the plot for lLIMIT
and adjust CG until a desired load current plot is obtained.
Step 5: Calculate the Output Accuracy and Tolerable System Error
Since the LMP8646 is a precision current limiter, the output current accuracy is extremely important. This
accuracy is affected by the system error contributed by the LMP8646 device error and other errors contributed by
external resistances, such as RSENSE and RG.
In this application, VSENSE = ILIMIT * RSENSE = 1.5A * 55 mOhm = 0.0825V, and RG = 50 kOhm. From the Electrical
Characteristics Table, it is known that VOFFSET = 1 mV and Gm_Accuracy = 2%. Using the equations shown in
Equation 8, the output accuracy can be calculated as 3.24%.
After figuring out the LMP8646 output accuracy, choose a tolerable system error or the output current accuracy
that is bigger than the LMP8646 output accuracy. This tolerable system error will be labeled as IERROR, and it has
the equation IERROR = (IMAX - ILIMIT)/IMAX (%). In this example, we will choose an IERROR of 5%, which will be used
to calculate for ROUT shown in the next step.
Step 6: Choose the output resistor, ROUT
At start-up, the capacitor is not charged yet and thus the output voltage of the LM3102 is very small. Therefore,
at start-up, the output current is at its maximum (IMAX). When the output voltage is at its nominal, then the output
current will settle to the desired limited value. Because a large current error is not desired, ROUT needs to be
chosen to stabilize the loop with minimal initial start-up current error. Follow the equations and example below to
choose the appropriate value for ROUT to minimize this initial error.
As discussed in step 4, the allowable IERROR is 5%, where IERROR = (IMAX - ILIMIT)/IMAX (%). Therefore, the
maximum allowable current is calculated as: IMAX = ILIMIT (1+ IERROR) = 1.5A * (1 + 5/100) = 1.575 A.
Next, use Equation 14 below to calculate for ROUT:
ROUT = (IMAX * RSENSE * Gain ± VFB)
(VO_REG_MIN ± VFB)
VFB
±
RFBB
RFBT
(14)
For example, assume the minimum LM3102 output voltage, VO_REG_MIN, is 0.6V, then ROUT can be calculated as
ROUT = [1.575A * 55 mOhm * (49.9k / 5k) - 0.8] / [ (0.8 / 2k) - (0.6 - 0.8) / 10k] = 153.6 Ohm.
18
Submit Documentation Feedback
Copyright © 2012–2014, Texas Instruments Incorporated
Product Folder Links: LMP8646
LMP8646
www.ti.com
SNOSC63B – FEBRUARY 2012 – REVISED DECEMBER 2014
Typical Applications (continued)
Populate ROUT with a resistor that is as close as possible to 153.6 Ohm (this application uses 160 Ohm). If the
limited sense current has a gain error and is not 1.5A at any point in time, then adjust this ROUT value to obtain
the desired limit current.
We recommend that the value for ROUT is at least 50 Ohm.
Step 7: Adjusting Components
Capture the output current and output voltage plots and adjust the components as necessary. The most common
components to adjust are CG to decrease the current ripple and ROUT to get a low current error. An example
output current and voltage plot can be seen in Figure 29.
8.2.1.3 Application Curve
5
5
Vo_load
I_limit
4
3
CURRENT (A)
VOLTAGE (V)
4
3
I_max
I_limit
2
2
1
1
Vo_reg_min
0
0
-10
0
10
20
TIME (s)
30
40
Figure 29. SuperCap Application With LM3102 Regulator Plot
8.2.2 Application #2: Current Limiter With a Resistive Load
EN
RON
RON
32.4 k:
VIN = 18V
RENT
32.4 k:
EN
CIN
10 PF
VCLOSE_LOOP = 2 V
RENB
11.8 k:
VIN
ILIMIT =
ICLOSE_LOOP = 1A
VOUT
LMZ12003
CFF
0.022 PF
COUT
1 PF &
100 PF
RSENSE
50 m:
RLOAD
2:
5V
SS
CSS
0.022 PF
FB
RG
80 k:
0.8V
ROUT
50:
RFBB
3.6 k:
+IN
RG
-IN
LMP8646
V+
V-
CV+
1 PF
& 10 PF
CG
0.1 nF
VOUT
RFBT
10 k:
Figure 30. Resistive Load Application With LMZ12003 Regulator
Submit Documentation Feedback
Copyright © 2012–2014, Texas Instruments Incorporated
Product Folder Links: LMP8646
19
LMP8646
SNOSC63B – FEBRUARY 2012 – REVISED DECEMBER 2014
www.ti.com
Typical Applications (continued)
8.2.2.1 Design Requirements
This subsection describes the design process for a resistive load application with the LMZ12003 voltage
regulator as seen in Figure 30. To see the current limiting capability of the LMP8646, the open-loop current must
be greater than the close-loop current. An open-loop occurs when the LMP8646 output is not connected the
LMZ12003’s feedback pin. For this example, we will let the open-loop current to be 1.5A and the close-loop
current, ILIMIT, to be 1A.
8.2.2.2 Detailed Design Procedure
Step 1: Choose the components for the Regulator.
Refer to the LMZ12003 application note (AN-2031) to select the appropriate components for the LMZ12003.
Step 2: Choose the sense resistor, RSENSE
RSENSE sets the voltage VSENSE between +IN and -IN and has the following equation:
RSENSE = VOUT / [(ILIMIT) * (RG / 5kOhm)]
(15)
In general, RSENSE depends on the output voltage, limit current, and gain. Refer to section Selection of the Sense
Resistor, RSENSE to choose the appropriate RSENSE value; this example uses 50 mOhm.
Step 3: Choose the gain resistor, RG, for LMP8646
RG is chosen from ILIMIT. As stated, VOUT = (RSENSE * ILIMIT) * (RG / 5kOhm). Since VOUT = VFB = 0.8V, ILIMIT = 1A,
and RSENSE = 50 mOhm , RG can be calculated as:
RG = (VOUT * 5 kOhm) / (RSENSE * ILIMIT)
RG = (0.8 * 5 kOhm) / (50 mOhm* 1A) = 80 kOhm
(16)
(17)
Step 4: Choose the Bandwidth Capacitance, CG.
The product of CG and RG determines the bandwidth for the LMP8646. Refer to the Typical Performance
Characteristics plots to see the range for the LMP8646 bandwidth and gain. Since each application is very
unique, the LMP8646 bandwidth capacitance, CG, needs to be adjusted to fit the appropriate application.
Bench data has been collected for this resistive load application with the LMZ12003 regulator, and we found that
this application works best for a bandwidth of 2 kHz to 30 kHz. Operating anything less than this recommended
bandwidth might prevent the LMP8646 from quickly limiting the current. We recommend choosing a bandwidth
that is in the middle of this range and using the equation: CG = 1/(2*pi*RG*Bandwidth) to find CG (this example
uses a CG value of 0.1nF). After this selection, capture the load current plot and adjust CG until a desired output
current plot is obtained.
Step 5: Choose the output resistor, ROUT, for the LMP8646
ROUT plays a very small role in the overall system performance for the resistive load application. ROUT was
important in the supercap application because it affects the initial current error. Because current is directly
proportional to voltage for a resistive load, the output current is not large at start-up. The bigger the ROUT, the
longer it takes for the output voltage to reach its final value. We recommend that the value for ROUT is at least
50 Ohm, which is the chosen value for this example.
Step 6: Adjusting Components
Capture the output current and output voltage plots and adjust the components as necessary. The most common
component to adjust is CG for the bandwidth. An example of the output current and voltage plot can be seen in
Figure 31.
20
Submit Documentation Feedback
Copyright © 2012–2014, Texas Instruments Incorporated
Product Folder Links: LMP8646
LMP8646
www.ti.com
SNOSC63B – FEBRUARY 2012 – REVISED DECEMBER 2014
Typical Applications (continued)
8.2.2.3 Application Curve
2.20
2.0
I_limit
Vclose_loop
1.8
1.76
1.6
1.54
1.4
1.32
1.2
1.10
1.0
0.88
0.8
0.66
0.6
0.44
0.4
0.22
0.2
0.00
0.0
CURRENT (A)
VOLTAGE (V)
1.98
-0.030 -0.018 -0.006 0.006 0.018 0.030
TIME (s)
Figure 31. Plot for the Resistive Load Application With LMZ12003 Regulator Plot
8.2.3 Application #3: Current Limiter With a Low-Dropout Regulator and Resistive Load
VCLOSE_LOOP = 2 V
ILIMIT =
ICLOSE_LOOP = 1A
ENABLE
OUT
EN
R3
51.1 k:
VIN = 5V
RSENSE
58 m:
C3
10 PF
LP38501
RLOAD
2:
5V
IN
C1
10 PF
ADJ
RG
51.7 k:
0.6V
+IN
RG
-IN
LMP8646
V+
V-
CV+
1 PF
& 10 PF
CG
10 nF
ROUT
50:
RFBB
6.04 k:
VOUT
RFBT
19.1 k:
Figure 32. Resistive Load Application With LP38501 Regulator
8.2.3.1 Design Requirements
This next example is the same as the last example, except that the regulator is now a low-dropout regulator, the
LP38501, as seen in Figure 32. For this example, we will let the open-loop current to be 1.25A and the closeloop current, ILIMIT, to be 1A.
8.2.3.2 Detailed Design Procedure
Step 1: Choose the components for the Regulator.
Refer to the LP38501 application note (AN-1830) to select the appropriate components for the LP38501.
Step 2: Choose the sense resistor, RSENSE
RSENSE sets the voltage VSENSE between +IN and -IN and has the following equation:
RSENSE = VOUT / [(ILIMIT) * (RG / 5kOhm)]
(18)
In general, RSENSE depends on the output voltage, limit current, and gain. Refer to section Selection of the Sense
Resistor, RSENSE to choose the appropriate RSENSE value; this example uses 58 mOhm.
Step 3: Choose the gain resistor, RG, for LMP8646
Submit Documentation Feedback
Copyright © 2012–2014, Texas Instruments Incorporated
Product Folder Links: LMP8646
21
LMP8646
SNOSC63B – FEBRUARY 2012 – REVISED DECEMBER 2014
www.ti.com
Typical Applications (continued)
RG is chosen from ILIMIT. As stated, VOUT = (RSENSE * ILIMIT) * (RG / 5kOhm). Since VOUT = ADJ = 0.6V, ILIMIT = 1A,
and RSENSE = 58 mOhm , RG can be calculated as:
RG = (VOUT * 5 kOhm) / (RSENSE * ILIMIT)
RG = (0.6 * 5 kOhm) / (58 mOhm* 1A) = 51.7 kOhm
(19)
(20)
Step 4: Choose the Bandwidth Capacitance, CG.
The product of CG and RG determines the bandwidth for the LMP8646. Refer to the Typical Performance
Characteristics plots to see the range for the LMP8646 bandwidth and gain. Since each application is very
unique, the LMP8646 bandwidth capacitance, CG, needs to be adjusted to fit the appropriate application.
Bench data has been collected for this resistive load application with the LP38501 regulator, and we found that
this application works best for a bandwidth of 50 Hz to 300 Hz. Operating anything larger than this recommended
bandwidth might prevent the LMP8646 from quickly limiting the current. We recommend choosing a bandwidth
that is in the middle of this range and using the equation: CG = 1/(2*pi*RG*Bandwidth) to find CG (this example
uses a CG value of 10 nF). After this selection, capture the plot for ISENSE and adjust CG until a desired sense
current plot is obtained.
Step 5: Choose the output resistor, ROUT, for the LMP8646
ROUT plays a very small role in the overall system performance for the resistive load application. ROUT was
important in the supercap application because it affects the initial current error. Because current is directly
proportional to voltage for a resistive load, the output current is not large at start-up. The bigger the ROUT, the
longer it takes for the output voltage to reach its final value. We recommend that the value for ROUT is at least
50 Ohm, which is the value we used for this example.
Step 6: Adjusting Components
Capture the output current and output voltage plots and adjust the components as necessary. The most common
component to adjust is CG for the bandwidth. An example plot of the output current and voltage can be seen in
Figure 33.
8.2.3.3 Application Curve
2.5
2.5
2.0
2.0
1.5
1.5
1.0
1.0
0.5
0.5
0.0
0.0
CURRENT (A)
VOLTAGE (V)
Vclose_loop
I_limit
-10 10 30 50 70 90 110 130 150 170
TIME (ms)
Figure 33. Plot for the Resistive Load Application With the LP38501 LDO Regulator
22
Submit Documentation Feedback
Copyright © 2012–2014, Texas Instruments Incorporated
Product Folder Links: LMP8646
LMP8646
www.ti.com
SNOSC63B – FEBRUARY 2012 – REVISED DECEMBER 2014
9 Power Supply Recommendations
Source V+ with an external voltage as recommended in the electrical characteristics table. It is recommended to
place a 100nF ceramic bypass capacitor to ground as close to possible to the V+ pin. In addition, an electrolytic
or tantalum capacitor of 10μF is recommended. The bulk capacitor does not need to be in close vicinity with the
LMP8646 and could be close to the voltage source terminals or at the output of the voltage regulator powering
the LMP8646.
10 Layout
10.1 Layout Guidelines
•
•
•
In a 4-layer board design, the recommended layer stack order from top to bottom is: signal, power, ground,
and signal
Bypass capacitors should be placed in close proximity to the V+ pin
The trace for pins +IN and -IN should be big enough to handle the current running through it.
10.2 Layout Example
Figure 34. LMP8646 Evaluation Board Layout
Submit Documentation Feedback
Copyright © 2012–2014, Texas Instruments Incorporated
Product Folder Links: LMP8646
23
LMP8646
SNOSC63B – FEBRUARY 2012 – REVISED DECEMBER 2014
www.ti.com
11 Device and Documentation Support
11.1 Trademarks
All trademarks are the property of their respective owners.
11.2 Electrostatic Discharge Caution
These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam
during storage or handling to prevent electrostatic damage to the MOS gates.
11.3 Glossary
SLYZ022 — TI Glossary.
This glossary lists and explains terms, acronyms, and definitions.
12 Mechanical, Packaging, and Orderable Information
The following pages include mechanical, packaging, and orderable information. This information is the most
current data available for the designated devices. This data is subject to change without notice and revision of
this document. For browser-based versions of this data sheet, refer to the left-hand navigation.
24
Submit Documentation Feedback
Copyright © 2012–2014, Texas Instruments Incorporated
Product Folder Links: LMP8646
PACKAGE OPTION ADDENDUM
www.ti.com
28-Feb-2017
PACKAGING INFORMATION
Orderable Device
Status
(1)
Package Type Package Pins Package
Drawing
Qty
Eco Plan
Lead/Ball Finish
MSL Peak Temp
(2)
(6)
(3)
Op Temp (°C)
Device Marking
(4/5)
LMP8646MK/NOPB
ACTIVE
SOT-23-THIN
DDC
6
1000
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
-40 to 125
AK7A
LMP8646MKE/NOPB
ACTIVE
SOT-23-THIN
DDC
6
250
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
-40 to 125
AK7A
LMP8646MKX/NOPB
ACTIVE
SOT-23-THIN
DDC
6
3000
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
-40 to 125
AK7A
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability
information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that
lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between
the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight
in homogeneous material)
(3)
MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4)
There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5)
Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
(6)
Lead/Ball Finish - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead/Ball Finish values may wrap to two lines if the finish
value exceeds the maximum column width.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
Addendum-Page 1
Samples
PACKAGE OPTION ADDENDUM
www.ti.com
28-Feb-2017
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
Addendum-Page 2
PACKAGE MATERIALS INFORMATION
www.ti.com
3-Mar-2017
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device
Package Package Pins
Type Drawing
SPQ
Reel
Reel
A0
Diameter Width (mm)
(mm) W1 (mm)
B0
(mm)
K0
(mm)
P1
(mm)
LMP8646MK/NOPB
SOT23-THIN
DDC
6
1000
178.0
8.4
LMP8646MKE/NOPB
SOT23-THIN
DDC
6
250
178.0
LMP8646MKX/NOPB
SOT23-THIN
DDC
6
3000
178.0
3.2
3.2
1.4
4.0
8.0
Q3
8.4
3.2
3.2
1.4
4.0
8.0
Q3
8.4
3.2
3.2
1.4
4.0
8.0
Q3
Pack Materials-Page 1
W
Pin1
(mm) Quadrant
PACKAGE MATERIALS INFORMATION
www.ti.com
3-Mar-2017
*All dimensions are nominal
Device
Package Type
Package Drawing
Pins
SPQ
Length (mm)
Width (mm)
Height (mm)
LMP8646MK/NOPB
SOT-23-THIN
DDC
6
1000
210.0
185.0
35.0
LMP8646MKE/NOPB
SOT-23-THIN
DDC
6
250
210.0
185.0
35.0
LMP8646MKX/NOPB
SOT-23-THIN
DDC
6
3000
210.0
185.0
35.0
Pack Materials-Page 2
IMPORTANT NOTICE
Texas Instruments Incorporated (TI) reserves the right to make corrections, enhancements, improvements and other changes to its
semiconductor products and services per JESD46, latest issue, and to discontinue any product or service per JESD48, latest issue. Buyers
should obtain the latest relevant information before placing orders and should verify that such information is current and complete.
TI’s published terms of sale for semiconductor products (http://www.ti.com/sc/docs/stdterms.htm) apply to the sale of packaged integrated
circuit products that TI has qualified and released to market. Additional terms may apply to the use or sale of other types of TI products and
services.
Reproduction of significant portions of TI information in TI data sheets is permissible only if reproduction is without alteration and is
accompanied by all associated warranties, conditions, limitations, and notices. TI is not responsible or liable for such reproduced
documentation. Information of third parties may be subject to additional restrictions. Resale of TI products or services with statements
different from or beyond the parameters stated by TI for that product or service voids all express and any implied warranties for the
associated TI product or service and is an unfair and deceptive business practice. TI is not responsible or liable for any such statements.
Buyers and others who are developing systems that incorporate TI products (collectively, “Designers”) understand and agree that Designers
remain responsible for using their independent analysis, evaluation and judgment in designing their applications and that Designers have
full and exclusive responsibility to assure the safety of Designers' applications and compliance of their applications (and of all TI products
used in or for Designers’ applications) with all applicable regulations, laws and other applicable requirements. Designer represents that, with
respect to their applications, Designer has all the necessary expertise to create and implement safeguards that (1) anticipate dangerous
consequences of failures, (2) monitor failures and their consequences, and (3) lessen the likelihood of failures that might cause harm and
take appropriate actions. Designer agrees that prior to using or distributing any applications that include TI products, Designer will
thoroughly test such applications and the functionality of such TI products as used in such applications.
TI’s provision of technical, application or other design advice, quality characterization, reliability data or other services or information,
including, but not limited to, reference designs and materials relating to evaluation modules, (collectively, “TI Resources”) are intended to
assist designers who are developing applications that incorporate TI products; by downloading, accessing or using TI Resources in any
way, Designer (individually or, if Designer is acting on behalf of a company, Designer’s company) agrees to use any particular TI Resource
solely for this purpose and subject to the terms of this Notice.
TI’s provision of TI Resources does not expand or otherwise alter TI’s applicable published warranties or warranty disclaimers for TI
products, and no additional obligations or liabilities arise from TI providing such TI Resources. TI reserves the right to make corrections,
enhancements, improvements and other changes to its TI Resources. TI has not conducted any testing other than that specifically
described in the published documentation for a particular TI Resource.
Designer is authorized to use, copy and modify any individual TI Resource only in connection with the development of applications that
include the TI product(s) identified in such TI Resource. NO OTHER LICENSE, EXPRESS OR IMPLIED, BY ESTOPPEL OR OTHERWISE
TO ANY OTHER TI INTELLECTUAL PROPERTY RIGHT, AND NO LICENSE TO ANY TECHNOLOGY OR INTELLECTUAL PROPERTY
RIGHT OF TI OR ANY THIRD PARTY IS GRANTED HEREIN, including but not limited to any patent right, copyright, mask work right, or
other intellectual property right relating to any combination, machine, or process in which TI products or services are used. Information
regarding or referencing third-party products or services does not constitute a license to use such products or services, or a warranty or
endorsement thereof. Use of TI Resources may require a license from a third party under the patents or other intellectual property of the
third party, or a license from TI under the patents or other intellectual property of TI.
TI RESOURCES ARE PROVIDED “AS IS” AND WITH ALL FAULTS. TI DISCLAIMS ALL OTHER WARRANTIES OR
REPRESENTATIONS, EXPRESS OR IMPLIED, REGARDING RESOURCES OR USE THEREOF, INCLUDING BUT NOT LIMITED TO
ACCURACY OR COMPLETENESS, TITLE, ANY EPIDEMIC FAILURE WARRANTY AND ANY IMPLIED WARRANTIES OF
MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE, AND NON-INFRINGEMENT OF ANY THIRD PARTY INTELLECTUAL
PROPERTY RIGHTS. TI SHALL NOT BE LIABLE FOR AND SHALL NOT DEFEND OR INDEMNIFY DESIGNER AGAINST ANY CLAIM,
INCLUDING BUT NOT LIMITED TO ANY INFRINGEMENT CLAIM THAT RELATES TO OR IS BASED ON ANY COMBINATION OF
PRODUCTS EVEN IF DESCRIBED IN TI RESOURCES OR OTHERWISE. IN NO EVENT SHALL TI BE LIABLE FOR ANY ACTUAL,
DIRECT, SPECIAL, COLLATERAL, INDIRECT, PUNITIVE, INCIDENTAL, CONSEQUENTIAL OR EXEMPLARY DAMAGES IN
CONNECTION WITH OR ARISING OUT OF TI RESOURCES OR USE THEREOF, AND REGARDLESS OF WHETHER TI HAS BEEN
ADVISED OF THE POSSIBILITY OF SUCH DAMAGES.
Unless TI has explicitly designated an individual product as meeting the requirements of a particular industry standard (e.g., ISO/TS 16949
and ISO 26262), TI is not responsible for any failure to meet such industry standard requirements.
Where TI specifically promotes products as facilitating functional safety or as compliant with industry functional safety standards, such
products are intended to help enable customers to design and create their own applications that meet applicable functional safety standards
and requirements. Using products in an application does not by itself establish any safety features in the application. Designers must
ensure compliance with safety-related requirements and standards applicable to their applications. Designer may not use any TI products in
life-critical medical equipment unless authorized officers of the parties have executed a special contract specifically governing such use.
Life-critical medical equipment is medical equipment where failure of such equipment would cause serious bodily injury or death (e.g., life
support, pacemakers, defibrillators, heart pumps, neurostimulators, and implantables). Such equipment includes, without limitation, all
medical devices identified by the U.S. Food and Drug Administration as Class III devices and equivalent classifications outside the U.S.
TI may expressly designate certain products as completing a particular qualification (e.g., Q100, Military Grade, or Enhanced Product).
Designers agree that it has the necessary expertise to select the product with the appropriate qualification designation for their applications
and that proper product selection is at Designers’ own risk. Designers are solely responsible for compliance with all legal and regulatory
requirements in connection with such selection.
Designer will fully indemnify TI and its representatives against any damages, costs, losses, and/or liabilities arising out of Designer’s noncompliance with the terms and provisions of this Notice.
Mailing Address: Texas Instruments, Post Office Box 655303, Dallas, Texas 75265
Copyright © 2017, Texas Instruments Incorporated
Was this manual useful for you? yes no
Thank you for your participation!

* Your assessment is very important for improving the work of artificial intelligence, which forms the content of this project

Related manuals

Download PDF

advertising