SiI9233 HDMI Receiver with Repeater, Multi-channel

SiI9233 HDMI Receiver with Repeater, Multi-channel

SiI9233 HDMI Receiver with Repeater, Multichannel Audio, and Deep Color Output

Data Sheet

SiI-DS-1032-A

March 2016

Document #

SiI-DS-

1059-A03

SiI9233 HDMI Receiver with Repeater, Multi-channel Audio, and Deep Color Output

Data Sheet

Contents

1.

General Description ...................................................................................................................................................... 6

1.1.

Features ............................................................................................................................................................... 6

1.2.

Important Information ........................................................................................................................................ 6

1.3.

Overview ............................................................................................................................................................. 7

1.4.

Additional Features ............................................................................................................................................. 7

2.

System Applications ...................................................................................................................................................... 9

2.1.

Comparing SiI9233 with SiI9127, SiI9125 and SiI9135 ........................................................................................ 9

3.

Functional Description ................................................................................................................................................ 10

3.1.

TMDS Digital Cores ............................................................................................................................................ 11

3.1.1.

Active Port Detection and Selection ............................................................................................................. 11

3.2.

HDCP Decryption Engine/XOR Mask ................................................................................................................. 11

3.2.1.

HDCP Embedded Keys ................................................................................................................................... 11

3.3.

Data Input and Conversion ................................................................................................................................ 12

3.3.1.

Mode Control Logic ....................................................................................................................................... 12

3.3.2.

Video Data Conversion and Video Output .................................................................................................... 12

3.3.3.

Deep Color Support....................................................................................................................................... 13

3.3.4.

x.v.Color Support .......................................................................................................................................... 13

3.3.5.

Automatic Video Configuration .................................................................................................................... 15

3.4.

Audio Data Capture Logic .................................................................................................................................. 16

3.4.1.

S/PDIF ............................................................................................................................................................ 16

3.4.2.

I

2

S .................................................................................................................................................................. 16

3.4.3.

One-Bit Audio Input (DSD/SACD) .................................................................................................................. 16

3.4.4.

High-Bitrate Audio on HDMI ......................................................................................................................... 16

3.4.5.

Auto Audio Configuration ............................................................................................................................. 18

3.4.6.

Soft Mute ...................................................................................................................................................... 18

3.5.

Control and Configuration ................................................................................................................................. 19

3.5.1.

Register/Configuration Logic ........................................................................................................................ 19

3.5.2.

I

2

C Serial Ports ............................................................................................................................................... 19

3.5.3.

EDID FLASH and RAM Block .......................................................................................................................... 19

3.5.4.

CEC Interface ................................................................................................................................................. 19

3.5.5.

Standby and HDMI Port Power Supplies ....................................................................................................... 20

4.

Electrical Specifications .............................................................................................................................................. 21

4.1.

Absolute Maximum Conditions ......................................................................................................................... 21

4.2.

Normal Operating Conditions ........................................................................................................................... 22

4.3.

DC Specifications ............................................................................................................................................... 23

4.3.1.

Digital I/O Specifications ............................................................................................................................... 23

4.3.2.

DC Power Supply Pin Specifications .............................................................................................................. 24

4.4.

AC Specifications ............................................................................................................................................... 25

4.4.1.

TMDS Input Timings ...................................................................................................................................... 25

4.4.2.

Video Output Timings ................................................................................................................................... 26

4.4.3.

Audio Output Timings ................................................................................................................................... 26

4.4.4.

Miscellaneous Timings .................................................................................................................................. 28

4.4.5.

Interrupt Timings .......................................................................................................................................... 28

4.5.

Timing Diagrams ................................................................................................................................................ 29

4.5.1.

TMDS Input Timing Diagrams ....................................................................................................................... 29

4.5.2.

Power Supply Control Timings ...................................................................................................................... 30

4.5.3.

Reset Timings ................................................................................................................................................ 30

4.5.4.

Digital Video Output Timing Diagrams .......................................................................................................... 31

4.5.5.

Digital Audio Output Timings ........................................................................................................................ 32

4.6.

Calculating Setup and Hold Times for Video Bus .............................................................................................. 33

4.6.1.

24/30/36-Bit Mode ....................................................................................................................................... 33

4.6.2.

12/15/18-Bit Dual-Edge Mode ...................................................................................................................... 34

2

© 2008-2016 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal . All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice.

SiI-DS-1032-A

SiI9233 HDMI Receiver with Repeater, Multi-channel Audio, and Deep Color Output

Data Sheet

4.7.

Calculating Setup and Hold Times for I

2

S Audio Bus ......................................................................................... 35

5.

Pin Diagram and Descriptions ..................................................................................................................................... 36

5.1.

Pin Descriptions................................................................................................................................................. 37

5.1.1.

Digital Video Output Pins .............................................................................................................................. 37

5.1.2.

Digital Audio Output Pins .............................................................................................................................. 38

5.1.3.

Configuration/Programming Pins ................................................................................................................. 39

5.1.4.

HDMI Control Signal Pins .............................................................................................................................. 40

5.1.5.

Differential Signal Data Pins.......................................................................................................................... 41

5.1.6.

Power and Ground Pins ................................................................................................................................ 42

6.

Video Path .................................................................................................................................................................. 43

6.1.

HDMI Input Modes to SiI9233 Receiver Output Modes.................................................................................... 44

6.1.1.

HDMI RGB 4:4:4 Input Processing................................................................................................................. 45

6.1.2.

HDMI YCbCr 4:4:4 Input Processing .............................................................................................................. 46

6.1.3.

HDMI YCbCr 4:2:2 Input Processing .............................................................................................................. 47

6.2.

SiI9233 Receiver Output Mode Configuration .................................................................................................. 48

6.2.1.

RGB and YCbCr 4:4:4 Formats with Separate Syncs ..................................................................................... 49

6.2.2.

YC 4:2:2 Formats with Separate Syncs .......................................................................................................... 51

6.2.3.

YC 4:2:2 Formats with Embedded Syncs ....................................................................................................... 54

6.2.4.

YC Mux (4:2:2) Formats with Separate Syncs ............................................................................................... 57

6.2.5.

YC Mux 4:2:2 Formats with Embedded Syncs ............................................................................................... 59

7.

I

6.2.6.

2

12/15/18-Bit RGB and YCbCr 4:4:4 Formats with Separate Syncs ................................................................ 61

C Interfaces............................................................................................................................................................... 63

HDCP E-DDC / I

2

C Interface ............................................................................................................................... 63 7.1.

7.2.

Local I

2

7.3.

7.4.

C Interface ............................................................................................................................................. 64

Video Requirement for I

I

2

2

C Access ..................................................................................................................... 64

C Registers ...................................................................................................................................................... 64

8.

Hot Plug Detect CTS Requirement .............................................................................................................................. 65

9.

Design Recommendations .......................................................................................................................................... 66

9.1.

Power Control ................................................................................................................................................... 66

9.1.1.

Power Pin Current Demands......................................................................................................................... 66

9.2.

HDMI Receiver DDC Bus Protection .................................................................................................................. 67

9.3.

Decoupling Capacitors ...................................................................................................................................... 67

9.4.

ESD Protection .................................................................................................................................................. 67

9.5.

HDMI Receiver Layout ....................................................................................................................................... 68

9.6.

EMI Considerations ........................................................................................................................................... 69

9.7.

XTALIN Clock Required in All Designs ................................................................................................................ 70

9.7.1.

Description .................................................................................................................................................... 70

9.7.2.

Recommendation ......................................................................................................................................... 70

9.8.

Typical Circuit .................................................................................................................................................... 70

9.8.1.

Power Supply Decoupling ............................................................................................................................. 70

9.8.2.

HDMI Port Connections ................................................................................................................................ 71

9.8.3.

Digital Video Output Connections ................................................................................................................ 72

9.8.4.

Digital Audio Output Connections ................................................................................................................ 73

9.8.5.

Control Signal Connections ........................................................................................................................... 73

9.9.

Layout ................................................................................................................................................................ 74

9.9.1.

TMDS Input Port Connections ...................................................................................................................... 74

10.

Packaging ................................................................................................................................................................ 75

10.1.

ePad Enhancement ........................................................................................................................................... 75

10.2.

PCB Layout Guidelines ...................................................................................................................................... 75

10.3.

144-pin TQFP Package Dimensions ................................................................................................................... 76

10.4.

Marking Specification ........................................................................................................................................ 77

10.5.

Ordering Information ........................................................................................................................................ 77

Revision History .................................................................................................................................................................. 78

© 2008-2016 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal . All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice.

SiI-DS-1032-A 3

SiI9233 HDMI Receiver with Repeater, Multi-channel Audio, and Deep Color Output

Data Sheet

Figures

Figure 1.1. A/V Receiver Block Diagram ............................................................................................................................... 6

Figure 3.1. Functional Block Diagram ................................................................................................................................. 10

Figure 3.2. Default Video Processing Path .......................................................................................................................... 14

Figure 3.3: High Speed Data Transmission.......................................................................................................................... 16

Figure 3.4: High-Bitrate Stream Before and After Reassembly and Splitting ..................................................................... 17

Figure 3.5. High-Bitrate Stream After Splitting ................................................................................................................... 17

Figure 3.6. I

2

C Register Domains ........................................................................................................................................ 19

Figure 4.1. Audio Crystal Schematic for the SiI9233 Receiver ............................................................................................ 27

Figure 4.2. SCDT and CKDT Timing from DE or RXC Inactive/Active ................................................................................... 29

Figure 4.3. TMDS Channel-to-Channel Skew Timing .......................................................................................................... 29

Figure 4.4. Power Supply Sequencing ................................................................................................................................. 30

Figure 4.5. RESET# Minimum Timings................................................................................................................................. 30

Figure 4.6. Video Digital Output Transition Times .............................................................................................................. 31

Figure 4.7. Receiver Clock-to-Output Delay and Duty Cycle Limits .................................................................................... 31

Figure 4.8. I

2

S Output Timings ............................................................................................................................................ 32

Figure 4.9. S/PDIF Output Timings ...................................................................................................................................... 32

Figure 4.10. MCLK Timings .................................................................................................................................................. 32

Figure 4.11. 24/30/36-Bit Mode Receiver Output Setup and Hold Times .......................................................................... 33

Figure 4.12. 12/15/18-Bit Mode Receiver Output Setup and Hold Times .......................................................................... 34

Figure 5.1. Pin Diagram ....................................................................................................................................................... 36

Figure 5.2. Test Point VCCTP for VCC Noise Tolerance Spec .............................................................................................. 42

Figure 6.1. Receiver Video and Audio Data Processing Paths ............................................................................................ 43

Figure 6.2. HDMI RGB 4:4:4 Input to Video Output Transformations ................................................................................ 45

Figure 6.3. HDMI YCbCr 4:4:4 Input to Video Output Transformations ............................................................................. 46

Figure 6.4. HDMI YCbCr 4:2:2 Input to Video Output Transformations ............................................................................. 47

Figure 6.5. 4:4:4 Timing Diagram ........................................................................................................................................ 50

Figure 6.6. YC Timing Diagram ............................................................................................................................................ 53

Figure 6.7. YC 4:2:2 Embedded Sync Timing Diagram ........................................................................................................ 56

Figure 6.8. YC Mux 4:2:2 Timing Diagram ........................................................................................................................... 58

Figure 6.9. YC Mux 4:2:2 Embedded Sync Encoding Timing Diagram ................................................................................. 60

Figure 6.10. 18-Bit Output 4:4:4 Timing Diagram ............................................................................................................... 61

Figure 6.11. 15-Bit Output 4:4:4 Timing Diagram ............................................................................................................... 62

Figure 6.12. 12-Bit Output 4:4:4 Timing Diagram ............................................................................................................... 62

Figure 7.1. I

2

Figure 7.2. I

2

C Byte Read ..................................................................................................................................................... 63

C Byte Write .................................................................................................................................................... 63

Figure 7.3. Short Read Sequence ........................................................................................................................................ 63

Figure 8.1: HPD CTS Compliance Requirement Schematic ................................................................................................. 65

Figure 9.1. Decoupling and Bypass Capacitor Placement ................................................................................................... 67

Figure 9.2. Cut-out Reference Plane Dimensions ............................................................................................................... 68

Figure 9.3. HDMI to Receiver Routing – Top View .............................................................................................................. 69

Figure 9.4. Power Supply Decoupling and PLL Filtering Schematic .................................................................................... 70

Figure 9.5. HDMI Port Connections Schematic ................................................................................................................... 71

Figure 9.6. Digital Display Schematic .................................................................................................................................. 72

Figure 9.7. Audio Output Schematic ................................................................................................................................... 73

Figure 9.8. Controller Connections Schematic .................................................................................................................... 73

Figure 9.9. TMDS Input Signal Assignments ....................................................................................................................... 74

Figure 10.1. ePad Diagram .................................................................................................................................................. 75

Figure 10.2. 144-Pin TQFP Package Diagram ...................................................................................................................... 76

Figure 10.3. Marking Diagram ............................................................................................................................................ 77

4

© 2008-2016 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal . All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice.

SiI-DS-1032-A

SiI9233 HDMI Receiver with Repeater, Multi-channel Audio, and Deep Color Output

Data Sheet

Tables

Table 2.1. Summary of Features ........................................................................................................................................... 9

Table 3.1. Digital Video Output Formats ............................................................................................................................ 12

Table 3.2. Default Video Processing ................................................................................................................................... 14

Table 3.3. AVI InfoFrame Video Path Details ...................................................................................................................... 15

Table 3.4. Digital Output Formats Configurable through Auto Output Format Register ................................................... 15

Table 3.5. Supported MCLK Frequencies ............................................................................................................................ 16

Table 3.6. Maximum Audio Sampling Frequency for All Video Format Timings ................................................................ 18

Table 4.1. Calculation of 24/30/36-Bit Output Setup and Hold Times ............................................................................... 33

Table 4.2. Calculation of 12/15/18-Bit Output Setup and Hold Times ............................................................................... 34

Table 4.3. I

2

S Setup and Hold Time Calculations ................................................................................................................ 35

Table 6.1. Translating HDMI Formats to Output Formats .................................................................................................. 44

Table 6.2. Output Video Formats ....................................................................................................................................... 48

Table 6.3. 4:4:4 Mappings .................................................................................................................................................. 49

Table 6.4. YC 4:2:2 Separate Sync Pin Mappings ................................................................................................................ 51

Table 6.5. YC 4:2:2 (Pass Through Only) Separate Sync Pin Mapping ............................................................................... 52

Table 6.6. YC 4:2:2 Embedded Sync Pin Mappings ............................................................................................................. 54

Table 6.7. YC 4:2:2 (Pass Through Only) Embedded Sync Pin Mapping ............................................................................. 55

Table 6.8. YC Mux 4:2:2 Mappings ..................................................................................................................................... 57

Table 6.9. YC Mux 4:2:2 Embedded Sync Pin Mapping ...................................................................................................... 59

Table 6.10. 12/15/18-Bit Output 4:4:4 Mappings .............................................................................................................. 61

Table 7.1. Control of the Default I

2

C Addresses with the CI2CA Pin ................................................................................... 64

Table 9.1. Maximum Power Domain Currents versus Video Mode.................................................................................... 66

© 2008-2016 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal . All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice.

SiI-DS-1032-A 5

SiI9233 HDMI Receiver with Repeater, Multi-channel Audio, and Deep Color Output

Data Sheet

1. General Description

The SiI9233 from Lattice Semiconductor is a 4-port receiver that is fully compliant with the HDMI 1.3 standard. AV receivers that output to DTVs displaying

10/12-bit color depth can now provide the highest quality protected digital audio/video over a single cable. The SiI9233 receiver can receive deep color video up to 12-bit, 1080p at 60 Hz. Efficient color space conversion receives RGB or YCbCr video data and outputs either standard-definition or high-definition

RGB or YCbCr formats.

The Sil9233 receiver adds support for the extended gamut YCC or x.v.Color color space, which supports approximately 1.8 times the number of colors as the

RGB color space. The x.v.Color color space also makes full use of the range on the standard 8-bit resolution per pixel.

1.1.

Features

4-Port HDMI 1.3, HDCP 1.3, and DVI 1.0 compliant

Receiver

Integrated TMDS

®

core running at 25–225 MHz

36-bit digital video interface supports video processors:

 x.v.Color to extended RGB

36-bit RGB / YCbCr 4:4:4

16/20/24-bit YCbCr 4:2:2

8/10/12-bit YCbCr 4:2:2 (ITU BT.656)

Color Space Conversion for both RGB-to-YCbCr and YCbCr-to-RGB (both 601 and 709)

True 12-bit accurate output data using an internal14-bit wide processing path

Programmable drive strength from 2 mA to

14 mA.

Programmable output delay control to prevent simultaneous switching

1.2.

Important Information

See the Hot Plug Detect CTS Requirement

sections for important information regarding HDMI compliance testing

HDMI Port3

Connector

RPWR3 (5V)

TMDS3

DDC3

HPD3

HDMI Port2

Connector

HDMI Port1

Connector

RPWR2(5V)

TMDS2

DDC2

CEC

HPD2

RPWR1(5V)

TMDS1

DDC1

HPD1

HDMI Port0

Connector

CEC

RPWR0 (5V)

TMDS0

DDC0

SiI9233

Receiver

HPD0

Microcontroller

I

2

C

Digital Video

MCLK

SPDIF

I

2

S/

DSD

Video

Processor

SiI9134

Transmitter

Audio DSP

I 2 S

Audio

DAC

Speakers

Other Audio Sources

Figure 1.1. A/V Receiver Block Diagram

6

© 2008-2016 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal . All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice.

SiI-DS-1032-A

SiI9233 HDMI Receiver with Repeater, Multi-channel Audio, and Deep Color Output

Data Sheet

1.3.

Overview

The SiI9233 HDMI Receiver can send and receive up to two channels of uncompressed digital audio at 192 kHz.

Compressed streams are also supported through either the S/PDIF port or over I industry-standard I

2

2

S for DTS-HD and Dolby TrueHD. An

S port allows direct connection to low-cost audio DACs at up to 192 kHz. An S/PDIF port supports up to 192 kHz audio. Audio down-sampling allows the SiI9233 receiver to share the audio bus with a high-sample-rate audio DAC while down-sampling audio for an attached display that supports only lower rates.

The SiI9233 receiver provides additional integrated features to help lower system cost and provide enhanced features to the end consumer. The SiI9233 receiver integrates the Extended Display Identification Data (EDID) block, which is stored in embedded Non-Volatile Memory (NVM). This memory can be programmed at the time of manufacture using the local I

2

C bus, similar to how existing EEPROMs are programmed today. On board RAM can also be loaded with EDID data from the system microcontroller during power up or initialization if the NVM is not used. The EDID is reflected on each of the four HDMI ports through the DDC bus. Flexibility is built in to allow mixing different EDID formats in an application. This feature can eliminate up to four EDID ROMs while also saving board space.

The SiI9233 receiver provides a complete, simple solution to enabling Consumer Electronics Control (CEC) in a DTV. CEC is a single-wire bus that transmits remote control commands throughout a home network. The SiI9233 receiver integrates both an HDMI-compliant I/O and Lattice Semiconductor’s CEC API. The CEC I/O meets all HDMI compliance tests and eliminates the need for additional external components, again saving board space and reducing DTV BOM cost. The CEC API manages reception and transmission of all CEC signals according to the CEC protocol and makes the information available to the system microcontroller. This significantly lowers the system-level control by the system microcontroller, simplifying firmware overhead.

The SiI9233 receiver also incorporates a very robust standby power scheme. The standby power plane of the device is isolated from the rest of the device, and can be powered locally from an external +5 V standby power supply input to the device, or from the +5 V signal from one of the four HDMI connectors. This feature results in extremely low power consumption of the device when in standby mode, while both CEC and EDID are fully operational. Additionally, if using the NVM feature to store the EDID, only the +5 V power from the source device is needed to read the EDID, and the display can be completely unplugged from the AC power outlet.

The SiI9233 receiver also comes pre-programmed with HDCP keys. This set of keys simplifies the manufacturing process and lowers costs, while providing the highest level of HDCP key security.

Lattice Semiconductor’s HDMI Receivers use the latest generation of TMDS core technology, supporting dynamic cable equalization that automatically detects the appropriate equalization required for the incoming signal, offering the best support for long cable connections. These TMDS cores pass all HDMI compliance tests.

1.4.

Additional Features

Digital audio interface supports high-end audio systems:

DTS-HD and DolbyTrueHD high bit rate audio support

I

2

S output with 4 data signals for multi-channel formats

S/PDIF output supports PCM, Dolby Digital, DTS digital audio transmission (32-192 kHz Fs sample rate)

IEC60958 or IEC61937 compatible

Flexible, programmable I

2

S channel mapping

2:1 and 4:1 down-sampling to handle 96-kHz and 192-kHz audio streams.

Intelligent audio mute capabilities avoids pops and noise with automatic soft mute and unmute.

Integrated HDCP decryption engine for receiving protected audio and video content:

Pre-programmed HDCP keys provide highest level of key security and simplify manufacturing

Full support for HDCP repeaters (up to 16 attached downstream devices)

Built in HDCP self-test (BIST).

HDCP Repeater support.

Built-in Consumer Electronics Control (CEC)

HDMI-compliant CEC I/O simplifies design and lowers cost

Integrated CEC Programming Interface (CPI) lowers software overhead

Automatic Feature Abort response for unsupported commands

Automatic message retry on transmit.

Integrated EDID in non-volatile memory with optional registers to override EDID for each port.

© 2008-2016 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal . All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice.

SiI-DS-1032-A 7

SiI9233 HDMI Receiver with Repeater, Multi-channel Audio, and Deep Color Output

Data Sheet

Flexible power management

Separate Standby power pin

Standby power can be from HDMI +5V signal or locally

Extremely low standby power.

20 mm x 20 mm 144-pin TQFP package with ePad.

8

© 2008-2016 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal . All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice.

SiI-DS-1032-A

SiI9233 HDMI Receiver with Repeater, Multi-channel Audio, and Deep Color Output

Data Sheet

2. System Applications

The SiI9233 HDMI Receiver is designed for digital televisions that require support for HDMI v1.3 Deep Color. The

SiI9233 receiver supports the HDMI v1.3 specification and allows receipt of 10/12-bit color depth up to 1080p resolutions. A single SiI9233 receiver provides four HDMI input ports. The video output interfaces to a video processor

and the audio output can interface directly to an audio DAC or an audio DSP for further processing as shown in Figure

1.1.

2.1.

Comparing SiI9233 with SiI9127, SiI9125 and SiI9135

Table 2.1

summarizes the functional differences among the SiI9127, SiI9125, the SiI9135, and the SiI9233.

Table 2.1. Summary of Features

Feature

HDMI Input Connections

TMDS Input Ports 2

Color Depth

DDC Input Ports

Maximum TMDS Input Clock

Video Output

Digital Video Output Ports

SiI9125

8/10/12-bit

2

225 MHz

SiI9127

2

8/10/12-bit

2

225 MHz

SiI9135

2

8/10/12-bit

2

225 MHz

SiI9223

4

8/10/12-bit

4

225 MHz

SiI9233

4

8/10/12-bit

4

225 MHz

1 1 1 1 1

Maximum Output Pixel Clock

Maximum Output Bus Width

Audio Formats

165 MHz.

36

S/PDIF Output Ports

I2S Output

1

2 channel

DSD Output

High Bit Rate Audio Support

Compressed DTS-HD and Dolby

True-HD

2 channel

No

Maximum Audio Sample Rate (Fs) 192 kHz

Video Processing

Color Space Converter

Pixel Clock Divider

Digital Video Bus Mapping

Other Features

Local fixed I2C Device Address

165 MHz.

36

1

2 channel

NA

No

192 kHz

165 MHz.

36

1

8 channel

6 channel

Yes

192 kHz

165 MHz.

36

1

2 channel

NA

No

192 kHz

165 MHz.

36

1

8 channel

8 channel

Yes

192 kHz

RGB to/from

YCbCr

RGB to/from

YCbCr x.v.Color to RGB

RGB to/from

YCbCr

RGB to/from

YCbCr x.v.Color to RGB

RGB to/from

YCbCr x.v.Color to RGB

÷ 4, ÷ 2 ÷ 4, ÷ 2 ÷ 4, ÷ 2 ÷ 4, ÷ 2 ÷ 4, ÷ 2 swap Cb, Cr pins swap Cb, Cr pins swap Cb, Cr pins swap Cb, Cr pins swap Cb, Cr pins

Programmable I2C Device

Address

0x60/0x68 or

0x62/0x6A

NA

CEC

EDID

Package

No

No

HDCP Repeater Support No

Interlaced Format Detection Pin Yes

144-pin TQFP ePad

0x60/0x68 or

0x62/0x6A

0x64, 0xC0,

0xE0, 0xE6,

0x90

Yes

NVRAM

No

Yes

128-pin TQFP ePad

0x60/0x68 or

0x62/0x6A

NA

No

No

Yes

Yes

144-pin TQFP ePad

0x60/0x68 or

0x62/0x6A

0x64, 0xC0, 0xE0,

0xE6, 0x90

Yes

NVRAM

No

Yes

144-pin TQFP ePad

0x60/0x68 or

0x62/0x6A

0x64, 0xC0,

0xE0, 0xE6,

0x90

Yes

NVRAM

Yes

Yes

144-pin TQFP ePad

© 2008-2016 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal . All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice.

SiI-DS-1032-A 9

SiI9233 HDMI Receiver with Repeater, Multi-channel Audio, and Deep Color Output

Data Sheet

3. Functional Description

The SiI9233 receiver provides a complete solution for receiving HDMI-compliant digital audio and video. Specialized audio and video processing is available within the HDMI Receiver to add HDMI capability to consumer electronics such

as DTVs. Figure 3.1

shows the functional blocks of the chip.

CEC_A

DSDA0

DSDA1

DSDA2

DSDA3

DSCL0

DSCL1

DSCL2

DSCL3

Serial

Host

Interface

(DDC)

CEC

HDCP

Registers

SRAM

EDID

NVRAM

CSDA

CSCL

CI2CA

Serial

Host

Interface

(local)

RPI

Registers and State

Machine

Configuration and Status

Registers

R0XC+

R0XC-

R0X0+

R0X0-

R0X1+

R0X1-

R0X2+

R0X2-

R0XC+

R0XC-

R0X0+

R0X0-

R0X1+

R0X1-

R0X2+

R0X2-

R0XC+

R0XC-

R0X0+

R0X0-

R0X1+

R0X1-

R0X2+

R0X2-

R0XC+

R0XC-

R0X0+

R0X0-

R0X1+

R0X1-

R0X2+

R0X2-

HDMI

Receiver

Mux

SCDT

Logic

A/V Split

Video

HDCP

Unmask

HDMI

Decode

Audio

HDCP

Unmask

HDCP

Engine

Embedded

HDCP Keys

Hot Plug

Controller

Video Processing

Deep

Color

Color

Space

Converter

Up/Down

Sampling

Auto Video Configuration

Auto

Audio Processing

Audio Clock

Regeneration

APLL

Audio/

Exception

Video

Output

Format

Audio Output

S/PDIF

Output

I

2

S/

DSD

Output

CEC_D

HPD0

HPD1

HPD2

HPD3

INT

ODCK

Q[35:0]

DE

HSYNC

VSYNC

EVNODD

SPDIF

SCK/DCLK

WS

SD[3:0]

DR[3:0]

DR[3:0]

MUTEOUT

XTALIN

XTALOUT

MCLK

SCDT

R0PWR5V

R1PWR5V

R2PWR5V

R3PWR5V

RESET#

Reset

Logic

Figure 3.1. Functional Block Diagram

The SiI9233 receiver supports four HDMI input ports. Only one port can be active at any time.

© 2008-2016 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal . All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice.

10 SiI-DS-1032-A

SiI9233 HDMI Receiver with Repeater, Multi-channel Audio, and Deep Color Output

Data Sheet

3.1.

TMDS Digital Cores

The TMDS Digital core is the latest generation core that supports HDMI v1.3 and the ability to carry 10/12-bit color depth. The core can receive TMDS data at up to 225 MHz. Each core performs 10-to-8-bit TMDS decoding on the video data and 10-to-4 bit TMDS decoding on the audio data received from the three TMDS differential data lines along with a TMDS differential clock. The TMDS core can sense a stopped clock or stopped video and software can put the HDMI receiver into power-down mode.

3.1.1.

Active Port Detection and Selection

Only one port can be active at a time, under control of the HDMI Receiver’s firmware. Active TMDS signaling can arrive at all ports, but only one has internal circuitry enabled. The firmware in the display controls these states using register settings.

Other control signals are associated with the TMDS signals on each HDMI port. The HDMI Receiver can monitor the +5V supply from each attached host. The firmware can poll registers to check on which ports are connected. The firmware also controls functional connection to one of the four E-DDC buses, enabling one while disabling the others. An attached host determines the active status of an attached HDMI device by polling the E-DDC bus to the HDMI Receiver.

Refer to the SiI9223/9233/9127 HDMI Receivers Programmer’s Reference (SiI-PR-1019) for a complete description of port detection and selection.

3.2.

HDCP Decryption Engine/XOR Mask

The HDCP decryption engine contains all the necessary logic to decrypt the incoming audio and video data. The decryption process is entirely controlled by the host side microcontroller/microprocessor through a set sequence of register reads and writes through the DDC channel. Pre-programmed HDCP keys and a Key Selection Vector (KSV) stored in the on-chip non-volatile memory are used in the decryption process. A resulting calculated value is applied to an XOR mask during each clock cycle to decrypt the audio/video data.

The SiI9233 also contains all the necessary logic to support full HDCP repeaters. The KSV values of downstream devices

(up to 16 total) are written to the HDMI receiver through the local I

2

C bus (CSDA/CSCL). As defined in the HDCP specification, Vi is calculated and made available to the host on the DDC bus (DSDA/DSCL).

3.2.1.

HDCP Embedded Keys

The SiI9233 HDMI Receiver comes pre-programmed with a set of production HDCP keys stored on-chip in non-volatile memory. System manufacturers do not need to purchase key sets from the Digital-Content LLC. All purchasing, programming, and security for the HDCP keys is handled by Lattice Semiconductor. The pre-programmed HDCP keys provide the highest level of security, as keys cannot be read out of the device after they are programmed. Before receiving samples of the SiI9233 receiver, customers must sign the HDCP license agreement ( www.digital-cp.com

) or a special NDA with Lattice Semiconductor.

© 2008-2016 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal . All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice.

SiI-DS-1032-A 11

SiI9233 HDMI Receiver with Repeater, Multi-channel Audio, and Deep Color Output

Data Sheet

3.3.

Data Input and Conversion

3.3.1.

Mode Control Logic

The mode control logic determines if the decrypted data is video, audio, or auxiliary information and directs it to the appropriate logic block.

3.3.2.

Video Data Conversion and Video Output

The HDMI Receiver can output video in many different formats (see examples in Table 3.1

) and can process the video

data before it is sent, as shown in Figure 3.2

. It is possible to bypass each of the processing blocks by setting the

appropriate register bits.

Table 3.1. Digital Video Output Formats

Color

Space

RGB

Video

Format

4:4:4

YCbCr 4:4:4

Bus

Width

36

HSYNC/

VSYNC

Separate

Output Clock (MHz)

480i/576i

2, 3

480p XGA 720p 1080i

27 27 65 74.25 74.25

30

24

Separate

Separate

27

27

12/15/18 Separate 27

36 Separate 27

27

27

27

27

65

65

65

65

74.25 74.25

74.25 74.25

74.25 74.25

74.25 74.25

SXGA 1080p UXGA

Notes

108 148.5 162 —

108

108

108

148.5

148.5

148.5

162

162

162

4

4:2:2

30

24

Separate

Separate

27

27

12/15/18 Separate 27

16/20/24 Separate 27

27

27

27

27

65 74.25 74.25

65 74.25 74.25

65 74.25 74.25

— 74.25 74.25

108

108

148.5 162

148.5 162

148.5 162

4

16/20/24 Embedded 27

8/10/12 Separate 27

27

54

74.25 74.25

148.5 148.5

148.5 162

1

8/10/12 Embedded 27 54 — 148.5 148.5 — — 1

Notes:

1.

Embedded syncs use SAV/EAV coding.

2.

480i and 576i modes can output a 13.25 MHz clock using the internal clock divider.

3.

Output clock frequency depends on programming of internal registers. Differential TMDS clock is always 25 MHz or faster.

4.

Output clock supports 12/15/18-bit mode by using both edges.

3.3.2.1.

Color Range Scaling

The color range depends on the video format, according to the CEA-861D specification. In some applications the 8-bit input range uses the entire span of 0x00 (0) to 0xFF (255) values. In other applications the range is scaled narrower.

The HDMI Receiver cannot detect the incoming video data range and there is no required range specification in the

HDMI AVI packet. The HDMI Receiver chooses scaling depending on the detected video format. 10 and 12-bit color range scaling are both handled the same way. Refer to the SiI9223/9233/9127 HDMI Receivers Programmer’s Reference

(SiI-PR-1019) for more details.

When the HDMI Receiver outputs embedded syncs (SAV/EAV codes), it also limits the YCbCr data output values to 1 to

254.

3.3.2.2.

Up Sample / Down Sample

Additional logic can convert from 4:2:2 to 4:4:4 (8/10/12-bit) or from 4:4:4 (8/10/12-bit) to 4:2:2 YCbCr format. All processing is done with 14 bits of accuracy for true 12-bit data.

© 2008-2016 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal . All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice.

12 SiI-DS-1032-A

SiI9233 HDMI Receiver with Repeater, Multi-channel Audio, and Deep Color Output

Data Sheet

3.3.3.

Deep Color Support

The HDMI v1.3 specification introduces color depth modes greater than 24 bits, known as Deep Color modes, to the

HDMI system architecture. The Deep Color modes employ a new pixel packing scheme to enable the extra bits of higher color depth data to be carried over the existing TMDS data encoding scheme. Currently, three Deep Color modes are defined: 30-bit, 36-bit and 48-bit. The SiI9233 HDMI Receiver supports two of these three Deep Color modes: 30 and 36-bit modes. In addition, each Deep Color mode is supported to 1080p HD format.

For Deep Color modes, the TMDS clock is run faster than the pixel clock in order to create extra bandwidth for the additional bits of the higher color depth data. The increase in the TMDS clock is by the ratio of the pixel size to 24 bits, as follows:

30-bit mode: TMDS clock = 1.25x pixel clock (5:4)

36-bit mode: TMDS clock = 1.5x pixel clock (3:2)

Because the SiI9233 receiver supports 36-bit mode at 1080p, the highest TMDS clock rate it supports is 225 MHz. When in Deep Color mode, the transmitter periodically sends a General Control Packet with the current color depth and pixel packing phase information to the receiver. The SiI9233 receiver captures the color depth information in a register, which the firmware can then use to set the appropriate clock divider to recover the pixel clock and data.

3.3.4.

x.v.Color Support

The SiI9233 receiver adds support for the extended gamut x.v.Color color space; this extended format has roughly 1.8 times more colors than the RGB color space. The use of the x.v.Color color space is made possible because of the availability of LED and laser-based light sources for the next generation displays. This format also makes use of the full range of values (1 to 254) in an 8-bit space instead of 16 to 235 in the RGB format. The use of x.v.Color along with Deep

Color helps in reducing color banding and allows the display of a larger range of colors than is currently possible.

3.3.4.1.

Color Space Conversion

Color space converter (CSC) blocks are provided to convert RGB data to Standard-Definition (ITU.601) or High-

Definition (ITU.709) YCbCr formats, and vice-versa. To support the latest extended-gamut x.v.Color displays, the Sil9233 implements color space converter blocks to convert RGB data to extended-gamut Standard-Definition (ITU.601) or

High-Definition (ITU.709) x.v.Color formats, and vice-versa.

RGB to YCbCr

The RGB

YCbCr color space converter (CSC) can convert from video data RGB to standard definition

(ITU.601) or to high definition (ITU.709) YCbCr formats. The HDMI AVI packet defines the color space of the incoming video.

YCbCr to RGB The YCbCr

RGB color space converter is available to interface to MPEG decoders with RGB-only inputs. The CSC can convert from YCbCr in standard-definition (ITU.601) or high-definition (ITU.709) to RGB.

© 2008-2016 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal . All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice.

SiI-DS-1032-A 13

SiI9233 HDMI Receiver with Repeater, Multi-channel Audio, and Deep Color Output

Data Sheet

3.3.4.2.

Default Video Configuration

After hardware RESET, the HDMI Receiver chip is configured in its default mode. This mode is summarized in Table 3.2

.

For more details and for a complete register listing, refer to the SiI9223/9233/9127 HDMI Receivers Programmer’s

Reference (SiI-PR-1019).

Table 3.2. Default Video Processing

Video Control

HDCP Decryption

Color Space Conversion

Color Space Selection

Color Range Scaling

Upsampling/Downsampling

HSYNC & VSYNC Timing

Default after Hardware Reset

HDCP decryption is OFF

No color space conversion

BT.601 selected

No range scaling

No upsampling or downsampling

No inversions of HSYNC or VSYNC

Data Bit Width

Pixel Clock Replication

Uses 8-bit data

No pixel clock replication

1

1

Power Down Everything is powered down —

Notes:

1.

The HDMI Receiver assumes DVI mode after reset, which is RGB 24-bit 4:4:4 video with 0–255 range.

Note

1

1

1

TMDS HDCP

Widen to

14-Bits

RGB to

YCbCr bypass

Upsample

4:2:2 to

4:4:4 bypass

YCbCr

Range

Reduce bypass

Down

Sample

4:4:4 to

4:2:2 bypass xvYCC/

YCbCr to

RGB bypass

RGB

Range

Expand bypass

Dither

Module

Figure 3.2. Default Video Processing Path

Mux

656

Video

Timing

DE

HSYNC

VSYNC

ODCK

Q[35:0]

© 2008-2016 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal . All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice.

14 SiI-DS-1032-A

SiI9233 HDMI Receiver with Repeater, Multi-channel Audio, and Deep Color Output

Data Sheet

3.3.5.

Automatic Video Configuration

The SiI9233 receiver adds automatic video configuration to simplify the firmware’s task of updating the video path whenever the incoming video changes format. Bits in the HDMI Auxiliary Video Information (AVI) InfoFrame are used to reprogram the registers in the video path.

Table 3.3. AVI InfoFrame Video Path Details

AVI Byte 1 Bits [6:5] AVI Byte 2 Bits [7:6]

Y[1:0]

00

01

10

11

Color Space

RGB 4:4:4

YCbCr 4:2:2

YCbCr 4:4:4

Future

C[1:0]

00

01

10

11

Colorimetric

No Data

ITU 601

ITU 709

Extended Colorimetry

Information Valid

Notes on Table 3.3

1.

The Auto Video Configuration assumes that the AVI information is accurate. If information is not available, then the SiI9233 receiver must choose the video path based on measurement of the incoming resolution.

2.

Refer to EIA/CEA-861D Specification for details.

3.

The SiI9233 receiver can support only pixel replication modes 0b0000,

0b0001, and 0b0011. Other modes are unsupported and can result in unpredictable behavior.

0100

0101

0110

0111

1000

1001

AVI Byte 5 Bits [3:0]

PR[3:0]

0000

0001

0010

0011

Pixel Repetition

No repetition

Pixel sent 2 times

Pixel sent 3 times

Pixel sent 4 times

Pixel sent 5 times

Pixel sent 6 times

Pixel sent 7 times

Pixel sent 8 times

Pixel sent 9 times

Pixel sent 10 times

The format of the digital video output bus can be automatically configured to many different formats by programming the Auto Output Format Register. The available formats are listed in the table below. For detailed definitions of how to set this register, refer to the SiI9223/9233/9127 HDMI Receivers Programmer’s Reference (SiI-PR-1019).

Table 3.4. Digital Output Formats Configurable through Auto Output Format Register

Digital Output Formats

Color Width MUX

RGB

YCbCr

YCbCr

YCbCr

YCbCr

4:4:4

4:4:4

4:2:2

4:2:2

4:2:2

N

N

N

Y

Y

Sync

Sep.

Sep.

Sep.

Sep.

Emb.

© 2008-2016 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal . All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice.

SiI-DS-1032-A 15

SiI9233 HDMI Receiver with Repeater, Multi-channel Audio, and Deep Color Output

Data Sheet

3.4.

Audio Data Capture Logic

The SiI9233 receiver can output digital audio over S/PDIF, four I

2

S outputs, or eight one-bit audio outputs.

3.4.1.

S/PDIF

The S/PDIF stream can carry 2-channel uncompressed PCM data (IEC 60958) or a compressed bit stream for multichannel (IEC 61937) formats. The audio data capture logic forms the audio data into packets according to the HDMI specification. The S/PDIF output supports audio sampling rates from 32 to 192 kHz. A separate master clock output

(MCLK), coherent with the S/PDIF output, is provided for time-stamping purposes. Coherent means that the MCLK and

S/PDIF must have been created from the same clock source. This is typically done by using the original MCLK to strobe out the S/PDIF from the sourcing chip. There is no setup or hold timing requirement on an output with respect to

MCLK.

3.4.2.

I

2

S

The I

2

S bus format is programmable through registers, to allow interfacing with I

2

S audio DACs or audio DSPs with I

2

S inputs. Refer to the Programmer’s Reference for the different options on the I

2

S bus. Additionally, the MCLK (audio master clock) frequency is selectable to be an integer multiple of the audio sample rate F s

.

MCLK frequencies support various audio sample rates as shown in Table 3.5

.

Table 3.5. Supported MCLK Frequencies

Multiple of Fs Audio Sample Rate, Fs : I

2

S and S/PDIF Supported Rates

32 kHz 44.1 kHz 48 kHz 88.2 kHz

128

192

256

384

4.096 MHz

6.144 MHz

8.192 MHz

12.288 MHz

96 kHz 176.4 kHz 192 kHz

5.645 MHz

8.467 MHz

6.144 MHz

9.216 MHz

11.290 MHz 12.288 MHz 22.579 MHz 24.576 MHz

16.934 MHz 18.432 MHz 33.868 MHz 36.864 MHz

11.290 MHz 12.288 MHz 22.579 MHz 24.576 MHz 45.158 MHz 49.152 MHz

16.934 MHz 18.432 MHz 33.864 MHz 36.864 MHz

512

768

1024

1152

16.384 MHz

24.576 MHz

32.768 MHz

36.864 MHz

22.579 MHz 24.576 MHz 45.158 MHz 49.152 MHz

33.869 MHz 36.864 MHz

45.158 MHz 49.152 MHz

3.4.3.

One-Bit Audio Input (DSD/SACD)

DSD (direct stream digital) is an audio data format defined for SACD (Super Audio CD) applications. It consists of four data outputs for the left channel, four data outputs for the right channel, and a clock for up to 8-channel support. Onebit Audio supports 64*Fs, with Fs being either 44.1 kHz or 88.2 kHz.

The one bit audio outputs are synchronous to the positive edge of the DSD Clock. For one bit audio, the sampling information is carried in the Audio InfoFrame, instead of the Channel Status bits.

3.4.4.

High-Bitrate Audio on HDMI

The new high-bitrate compressed standards such as DTS-HD and Dolby TrueHD transmit data at bitrates as high as 18 to 24 Mbps. Because these bitrates are so high, DVD decoders and HDMI transmitters (as source devices), and DSP and

HDMI receivers (as sink devices) must carry the data using four I

2

S lines rather than using a single very-high-speed

S/PDIF or I

2

S bus (see Figure 3.3

).

Four I

2

S

Data Lines

Four I

2

S

Data Lines

MPEG Tx Rx DSP

Figure 3.3: High Speed Data Transmission

© 2008-2016 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal . All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice.

16 SiI-DS-1032-A

SiI9233 HDMI Receiver with Repeater, Multi-channel Audio, and Deep Color Output

Data Sheet

The high-bitrate audio stream is originally encoded as a single stream. To send it over four I

2

S lines, the DVD decoder needs to split this single stream into four streams. Because the single stream of data is being sent over four lines, the programmable ACR (Audio Clock Regeneration) rate is now four times the 96-kHz (384-kHz) or four times the 192-kHz

(768-kHz) sample rate.

Figure 3.4

shows the high-bitrate stream before it has been split into four I

2

S lines, and after it has been reassembled.

0 1 2 3 4 5

……….

N-1

N

16-Bits

0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15

Figure 3.4: High-Bitrate Stream Before and After Reassembly and Splitting

Figure 3.5

shows the same high-bitrate audio stream after being split into four I

2

S lines:

WS

Left Right Left Right

SD0

SD1

SD2

SD3

Sample 0 Sample 1 Sample 8 Sample 9

Sample 2

Sample 4

Sample 3

Sample 10

Sample 11

Sample 5 Sample 12 Sample 13

Sample 6 Sample 7 Sample 14 Sample 15

Figure 3.5. High-Bitrate Stream After Splitting

© 2008-2016 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal . All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice.

SiI-DS-1032-A 17

SiI9233 HDMI Receiver with Repeater, Multi-channel Audio, and Deep Color Output

Data Sheet

Table 3.6. Maximum Audio Sampling Frequency for All Video Format Timings

Description Format

Timing

Pixel

Repetition

Vertical Freq.

(Hz)

Max fs

8 ch (kHz)

4:2:2 and 4:4:4

24-bit

60 Hz Formats

VGA

480i

480i

240p

240p

640x480p

1440x480i

2880x480i

1440x240p

2880x240p none

2

4

2

4

480p

480p

480p

720p

1080i

1080p

50 Hz Formats

576i

576i

720x480p

1440x480p

2880x480p

1280x720p

1920x1080i none

2

4 none none

1920x1080p none

288p

288p

576p

576p

1440x576i

2880x576i

1440x288p

2880x288p

720x576p

1440x576p

576p

720p/50

1080i/50

1080p/50

1080p @ 24-30 Hz

2880x576p

1280x720p

4 none

1920x1080i none

1920x1080p none

2

4

2

4 none

2

1080p

1080p

1080p

1920x1080p none

1920x1080p none

1920x1080p none

50

50

50

50

50

50

50

50

50

50

59.94/60

59.94/60

59.94/60

59.94/60

59.94/60

59.94/60

59.94/60

59.94/60

59.94/60

59.94/60

59.94/60

24

25

29.97/30

48

192

48

96

192

192

192

192

Standard

192

192

192

Standard

48

48

192

48

192

48

96

192

192

192

192

Standard

48

192

4:4:4 Deep Color

(depth in bits)

48

192

48

96

192

192

192

192

10

192

192

192

48

96

192

192

192

192

10

48

192

10

48

48

192

48

192

48

192

48

96

192

192

192

192

12

192

192

192

48

96

192

192

192

192

12

48

192

12

48

48

192

48

192

Max fs

2 ch (kHz)

192

192

192

192

192

192

192

192

192

192

192

192

192

192

192

192

192

192

192

192

192

192

192

192

3.4.5.

Auto Audio Configuration

The SiI9233 receiver can control the audio output based on the current states of CablePlug, FIFO, Video, ECC, ACR, PLL,

InfoFrame, and HDMI. Audio output is enabled only when all necessary conditions are met. If any critical condition is missing, then the audio output is disabled automatically.

3.4.6.

Soft Mute

On command from a register bit or when automatically triggered with Automatic Audio Control (AAC), the SiI9233 receiver progressively reduces the audio data amplitude to mute the sound in a controlled manner. This feature is useful when there is an interruption to the HDMI audio stream (or an error) to prevent any audio pop from being sent to the I

2

S or S/PDIF outputs.

© 2008-2016 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal . All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice.

18 SiI-DS-1032-A

SiI9233 HDMI Receiver with Repeater, Multi-channel Audio, and Deep Color Output

Data Sheet

3.5.

Control and Configuration

3.5.1.

Register/Configuration Logic

The register/configuration logic block incorporates all the registers required for configuring and managing the features of the SiI9233 HDMI Receiver. These registers are used to perform HDCP authentication, audio/video/auxiliary format processing, CEA-861B

InfoFrame Packet format, and power-down control.

The registers are accessible from one of two serial ports.

The first port is the DDC port, which is connected through the HDMI cable to the HDMI host. It is used to control the

SiI9233 receiver from the host device for HDCP operation.

The second port is the local I

2

C port, which is used to control the SiI9233 receiver from the display device. This

is shown in Figure 3.6

. The Local Bus accesses the General

Registers and the Common Registers. The DDC Bus accesses the HDCP Operation registers and the Common

Registers.

Accessible from DDC

I

2

C Bus

HDCP Operation

Common Registers

General Registers

Video Processing

Audio Processing

InfoFrames

Repeater

Interrupts

Figure 3.6. I

2

C Register Domains

Accessible from Local

I

2

C Bus

3.5.2.

I

2

C Serial Ports

The SiI9233 provides 5 I

2

C serial interfaces: 4 DDC ports to communicate back to the HDMI or DVI hosts; one I

2

C port for initialization and control by a local microcontroller in the display. Each interface is 5-V tolerant.

3.5.2.1.

E-DDC Bus Interface to HDMI Host

The four DDC interfaces (DSDA0-3 and DSCL0-3) on the SiI9233 receiver are slave interfaces that can run up to 100 kHz.

Each interface is connected to one E-DDC bus and is used for reading the integrated EDID in addition to HDCP authentication.

The SiISiI9233 receiver is accessible on the E-DDC bus at device addresses 0xA0 for the EDID, and 0x74 for HDCP control. This feature is compliant with the HDCP 1.1 Specification.

3.5.3.

EDID FLASH and RAM Block

The EDID block consists of 1024 bytes of RAM. Each port has a block of 256 bytes of RAM for EDID data. This feature allows simultaneous reads of all ports from four different source devices that are connected to the SiI9233 receiver. In addition to the RAM, the EDID block contains 256 bytes of FLASH that is shared by all ports. As a result, the timing information must be identical among all the ports if the internal EDID is used. An additional area of FLASH contains unique CEC physical address and checksum values for each of the four ports. This feature allows simultaneous reads of all ports from four different source devices if they are connected and attempt an EDID read at the same time. If independent EDIDs are required on any of the ports, a CPU can externally load the 256 bytes of RAM for that port, by using the local I

2

C bus.

The internal EDID can be selected on a per-port basis using registers on the local I

2

C bus. For example, Port 0 and Port 1 can use the internal EDID, and Port 2 and Port 3 can use a discrete EEPROM for the EDID.

3.5.4.

CEC Interface

The Consumer Electronics Control (CEC) Interface block provides CEC electrically compliant signals between CEC devices and a CEC master. It allows products to meet the electrical specifications of CEC signaling by translating the

LVTTL signals of an external microcontroller (CEC host-side or Tx-side) to CEC signaling levels for CEC devices at the Rxside, and vice versa.

Additionally, a CEC controller compatible with the Lattice Semiconductor CEC Programming Interface (CPI) is included on-chip. This CEC controller has a high-level register interface accessible through the I

2

C interface which can be used to

© 2008-2016 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal . All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice.

SiI-DS-1032-A 19

SiI9233 HDMI Receiver with Repeater, Multi-channel Audio, and Deep Color Output

Data Sheet

send and receive CEC commands. This controller makes CEC control very easy and straightforward, and removes the burden of having a host CPU perform these low-level transactions on the CEC bus.

3.5.4.1.

I

2

C Interface to Display Controller

The Controller I

2

C interface (CSDA, CSCL) on the SiI9233 receiver is a slave interface capable of running up to 400 kHz.

This bus is used to configure the SiI9233 by reading/writing to the appropriate registers. The SiI9233 receiver is accessible on the local I

2

C bus at two device addresses. Refer to the SiI9223/9233/9127 HDMI Receivers Programmer’s

Reference (SiI-PR-1019) for more information.

3.5.5.

Standby and HDMI Port Power Supplies

The SiI9233 receiver incorporates a 5-volt standby power supply pin (SBVCC5) that can be used to supply power to the

EDID and CEC portions of the device when all other power supplies are turned off. This results in an extremely low power mode, but allows the EDID to be readable, and the CEC controller to be functional in this low power standby mode. No damage will occur to the device when in this mode.

If all power is off for the device, such as the TV being unplugged from the AC electrical outlet, the EDID can still be read from the source by using power from the HDMI connector +5V signal. In this case, an internal power MUX will automatically switch to the HDMI connector power to use for powering the EDID logic. In this mode, only the EDID block is functional, with all other functions of the device in power off mode. No damage will occur to the device in this mode.

© 2008-2016 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal . All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice.

20 SiI-DS-1032-A

SiI9233 HDMI Receiver with Repeater, Multi-channel Audio, and Deep Color Output

Data Sheet

4. Electrical Specifications

4.1.

Absolute Maximum Conditions

Symbol

IOVCC33

AVCC12

AVCC33

APVCC12

CVCC12

Parameter

I/O Pin Supply Voltage

TMDS Analog Supply Voltage

TMDS Analog Supply Voltage

Audio PLL Supply Voltage

Digital Core Supply Voltage

Min

–0.3

–0.3

–0.3

–0.3

–0.3

Typ

Max

4.0

1.9

4.0

1.9

1.9

Units Note

V

V

V

V

V

1, 2, 3

1, 2

1, 2

1, 2

1, 2

XTALVCC33

SBVCC5

ACR PLL Crystal Oscillator Supply Voltage

Standby Supply Voltage

–0.3

–0.3

4.0

5.7

V

V

1, 2

1,2

V

V

T

J

I

5V-Tolerant

T

STG

Input Voltage

Input Voltage on 5-V tolerant Pins

Junction Temperature

Storage Temperature

–0.3

–0.3

–65

IOVCC33 + 0.3

5.5

125

150

V

V

C

C

1, 2

5

Notes:

1.

Permanent device damage can occur if absolute maximum conditions are exceeded.

2.

Functional operation should be restricted to the conditions described under Normal Operating Conditions.

3.

Voltage undershoot or overshoot cannot exceed absolute maximum conditions.

4.

Refer to the SiI9233 Qualification Report for information on ESD performance.

5.

All VCCs must be powered to the device. If the device is unpowered and 5V is applied to these inputs, damage can occur.

© 2008-2016 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal . All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice.

SiI-DS-1032-A 21

SiI9233 HDMI Receiver with Repeater, Multi-channel Audio, and Deep Color Output

Data Sheet

4.2.

Normal Operating Conditions

Symbol

IOVCC33

AVCC12

AVCC33

APVCC12

CVCC12

XTALVCC33

SBVCC5

RxPWR5V

DIFF33

DIFF12

Parameter

I/O Pin Supply Voltage

TMDS Analog Supply Voltage

TMDS Analog Supply Voltage

Audio PLL Supply Voltage

Digital Core Supply Voltage

ACR PLL Crystal Oscillator Supply Voltage

Standby Supply Voltage

DDC I

2

C I/O Reference Voltage

Difference between two 3.3-V Power Pins

Difference between two 1.2-V Power Pins

Min Typ Max

3.13 3.3 3.47

1.14 1.2

3.13 3.3

1.14 1.2

1.14 1.2

3.13

4.75

4.75

3.3

5.0

5.00

1.26

3.47

1.26

1.26

3.47

5.25

5.25

1.0

1.0

Units

V

V

V

V

V

V

V

V

V

Note

1, 4

1, 6

3

2

4

4

4

DIFF3312 Difference between any 3.3-V and 1.2-V Pin –1.0 2.6 V 4, 5

V

CCN

T

A

 ja

Supply Voltage Noise

Ambient Temperature (with power applied)

Ambient Thermal Resistance (Theta JA)

0

25

100

70

27 mV

C

P-P

C/W

7

Notes:

1.

IOVCC33 and AVCC33 pins should be controlled from one power source.

2.

CVCC12 should be controlled from one power source.

3.

AVCC12 pin should be regulated.

4.

Power supply sequencing must guarantee that power pins stay within these limits of each other. See Figure 4.4

.

5.

No 1.2 V pin can be more than DIFF3312[min] higher than any 3.3 V pin. No 3.3 V pin can be more than DIFF3312[max] higher than any 1.2 V pin.

6.

The HDMI 1.0 Specification requires termination voltage (AVCC33) to be controlled to 3.3 V ±5%. The SiI9233 tolerates a wider range of ±300 mV.

7.

The supply voltage noise is measured at test point VCCTP in Figure 5.2

on page 42 . The ferrite bead provides filtering of

power supply noise. The figure is representative and applies to other VCC pins as well.

8.

Airflow at 0 m/s.

9.

The schematics on page 70 show decoupling and power supply regulation.

© 2008-2016 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal . All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice.

22 SiI-DS-1032-A

4.3.

DC Specifications

SiI9233 HDMI Receiver with Repeater, Multi-channel Audio, and Deep Color Output

Data Sheet

4.3.1.

Digital I/O Specifications

Symbol

V

IH

V

IL

V

TH+

V

TH-

Parameter

High-level Input Voltage

Low-level Input Voltage

Low to HIGH Threshold

RESET # Pin

HIGH to Low Threshold

RESET# Pin

Pin Type

3

LVTTL

LVTTL

Schmitt

Schmitt

Conditions

2

Min Typ Max Units Note

2.0

1.46 —

0.8

0.96

V

V

V

V

5

5

V

OH

V

OL

I

OL

V

ID

I

OD4

DDC V

TH+

Low to HIGH Threshold

DSDA0, DSDA1, DSCL0 and

DSCL1 pins.

DDC V

TH-

HIGH to Low Threshold

DSDA0, DSDA1, DSCL0 and

DSCL1 pins.

Local I

2

C V

TH+

Low to HIGH Threshold

CSCL and CSDA pins

Local I

2

C V

TH-

HIGH to Low Threshold

CSCL and CSDA pins

High-level Output Voltage

Low-level Output Voltage

Output Leakage Current

Differential Input Voltage

4mA Digital Output Drive

Schmitt

Schmitt

Schmitt

Schmitt

LVTTL

LVTTL

High Impedance –10 —

3.0

2.1

2.4

75

250

1.5

0.86

0.4

10

780

V

V

V

V

V

V

A mV

11, 13

11, 13

10

10

4

I

OD8

8mA Digital Output Drive

Output

Output

V

OUT

= 2.4 V

V

OUT

= 0.4 V

V

OUT

= 2.4 V

V

OUT

= 0.4 V

4

4

8

8

— mA mA mA mA

1, 6, 7

1, 6, 7

1, 6, 8

1, 6, 8

I

I

R

OD12

PD

OPD

12mA Digital Output Drive

Internal Pull Down Resistor

Output Pull Down Current

Output

Outputs

Outputs

V

OUT

= 2.4 V

V

OUT

= 0.4 V

IOVCC33=3.3 V

IOVCC33=3.6 V

12

12

25

— mA mA

50 110 kΩ

60 90

A

60 90

A

1, 6, 9

1, 6, 9

1, 12

1, 12

I

IPD

Input Pull Down Current Input IOVCC33=3.6 V — 1

Notes:

1.

These limits are guaranteed by design.

2.

Under normal operating conditions unless otherwise specified, including output pin loading C

L

= 10 pF.

3.

Refer to Pin Descriptions (beginning on page 21 ) for pin type designations for all package pins.

4.

Differential input voltage is a single-ended measurement, according to DVI Specification.

5.

6.

Schmitt trigger input pin thresholds V

TH+

and V

TH-

correspond to V

IH

and V

Minimum output drive specified at ambient = 70

C and IOVCC33 = 3.0 V. Typical output drive specified at ambient = 25

C and IOVCC33 = 3.3 V. Maximum output drive specified at ambient = 0

IL

, respectively.

C and IOVCC33 = 3.6 V.

7.

I

OD4

Output applies to pins SPDIF, SCK, WS, SD[3:0], DCLK, INT, and CSDA.

8.

I

OD8

Output applies to pins DE, HSYNC, VSYNC, Q[35:0].and MCLK.

9.

I

OD12

Output applies to pin ODCK.

10.

Note that the SPDIF output drives LVTTL levels, not the low-swing levels defined by IEC958.

11.

The SCL and SDA pins are not true open-drain buffers. When no VCC is applied to the chip, these pins can continue to draw a small current, and prevent the master IC from communicating with other devices on the I

2

C bus. Therefore, do not power-down the SiI9233 (remove VCC) unless the attached I

2

C bus is completely idle.

12.

The chip includes an internal pull-down resistor on many of the output pins. When tri-stated, these pins draw a pull down

13.

current according to this specification when the signal is driven HIGH by another source device.

With –10% IOVCC33 supply, the HIGH-to-LOW threshold on DDC and I

2

C bus is marginal. A –5% tolerance on the IOVCC33 power supply is recommended.

© 2008-2016 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal . All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice.

SiI-DS-1032-A 23

SiI9233 HDMI Receiver with Repeater, Multi-channel Audio, and Deep Color Output

Data Sheet

4.3.2.

DC Power Supply Pin Specifications

4.3.2.1.

Total Power versus Power-Down Modes

Typ

3

Max

3.3V

4

4

1.2V

0

SBVCC5

Units

mA

Notes

1, 6

Symbol Parameter

I

PDQ3

Complete

Power-Down

Current

Mode

A

Frequency

X

3.3V 1.2V SBVCC5

I

PDS

Sleep Powerdown Current

B 27 MHz

74.25 MHz

150 MHz

225 MHz

27 MHz

5

7

0

6

4

4

5

0

4

4

5

5

5

5

5 mA mA mA mA mA

2, 7

I

I

I

STBY

UNS

CCTD

Standby

Current

Unselected

Current

Full Power

Digital Out

Current

C

D

E

74.25 MHz

150 MHz

225 MHz

27 MHz

74.25 MHz

150 MHz

225 MHz

27 MHz

74.25 MHz

150 MHz

225 MHz

15

17

16

18

81

100

123

139

25

27

28

30

76

160 5

5

5

5

5

279

394

5

5

5

0

0

0

19

21

18

34

36

23 39

105 88

165 181 5

5

5

5

5

247

316

0

0

0

33

337

472

5

5

5

5

5

5 mA mA mA mA mA mA mA mA mA mA mA

2, 8

2, 8

2, 10

Notes:

1.

Power is not related to input TMDS clock (RxC) frequency because the selected TMDS port is powered down.

2.

Power is related to input TMDS clock (RxC) frequency at the selected TMDS port. Only one port can be selected.

3.

Typical power specifications measured with supplies at typical normal operating conditions; and a video pattern that combines gray scale, checkerboard and text.

4.

Maximum power limits measured with supplies at maximum normal operating conditions, minimum normal operating

5.

ambient temperature, and a video pattern with single-pixel vertical lines.

Registers are always accessible on local I

2

C (CSDA/CSCL) without active link clock.

6.

Power Down Mode A: Minimum power. Everything is powered off. Host sees no termination of TMDS signals on any of the four TMDS ports. I

2

C access is still available.

7.

Power Down Mode B: Powers down as in Mode C, but also powers down SCDT logic. CKDT state can be polled in register, but interrupts and the INT output pin are inactive. Host device can sense TMDS termination.

8.

Power Down Mode C: Power off to 3.3 V and 1.2 V supplies. Power on to SBVCC5 standby supply.

9.

Power Down Mode D: Monitor SCDT on selected TMDS port with outputs tri-stated. HDCP continues in the selected port, but the output of the HDMI Receiver can be connected to a shared bus.

10.

Digital Functional Mode E: Full Operation on one port with digital outputs

© 2008-2016 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal . All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice.

24 SiI-DS-1032-A

SiI9233 HDMI Receiver with Repeater, Multi-channel Audio, and Deep Color Output

Data Sheet

4.3.2.2.

Power-Down Mode Definitions

Mode 3.3V supply

1.2v supply

SBVCC5

A

Power

Down

ON ON ON

Description

Minimum power. Everything is powered off. Host sees no termination of

TMDS signals on any of the four TMDS ports. I

2

C access is still available.

B

Sleep

Mode

Power

C

Standby

Power

D

Unselected

Power

ON

OFF

ON

ON

OFF

ON

ON

ON

ON

Powers down as in Mode C, but also powers down SCDT logic. CKDT state can be polled in register, but interrupts and the INT output pin are inactive. Host device can sense TMDS termination.

Power off to 3.3 V and 1.2 V supplies. Power on to SBVCC5 standby supply.

Monitor SCDT on selected TMDS port with outputs tri-stated. HDCP continues in the selected port, but the output of the HDMI Receiver can be connected to a shared bus.

Full operation on one port with digital outputs.

E

Digital ON ON ON

Notes:

1.

PD Clks include PD_MCLK#, PD_XTAL#, PD_APLL# and PD_PCLK# all set to zero.

2.

PD Outs include PD_AO#, and PD_VO# all set to zero.

4.4.

AC Specifications

4.4.1.

TMDS Input Timings

Symbol Parameter

T

DPS

Intra-Pair Differential Input Skew

T

CCS

Channel to Channel Differential

Input Skew

Conditions

Min

Typ

Max Units Figure

T

BIT ps

T

CIP ns

Notes

2, 4

Figure 4.3

2, 3

F

RXC

T

RXC

T

IJIT

Differential Input Clock Frequency

Differential Input Clock Period

Differential Input Clock Jitter tolerance (0.3Tbit)

74.25 MHz

25

4.44

225

40

400

MHz ns ps

2, 5, 6

Notes:

1. Under normal operating conditions unless otherwise specified, including output pin loading of C

L

= 10 pF.

2. Guaranteed by design.

3. IDCK Period (refer to the applicable Lattice Semiconductor HDMI Transmitter Data Sheet).

4. 1/10 of IDCK Period (refer to the applicable Lattice Semiconductor HDMI Transmitter Data Sheet).

5. Jitter defined per HDMI Specification.

6. Jitter measured with Clock Recovery Unit per HDMI Specification. Actual jitter tolerance can be higher depending on the frequency of the jitter.

Refer to the SiI9223/9233/9127 HDMI Receivers Programmer’s Reference (SiI-PR-1019) for more details on controlling timing modes.

© 2008-2016 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal . All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice.

SiI-DS-1032-A 25

SiI9233 HDMI Receiver with Repeater, Multi-channel Audio, and Deep Color Output

Data Sheet

4.4.2.

Video Output Timings

4.4.2.1.

12/15/18-Bit Data Output Timings

Symbol Parameter

D

LHT

D

HLT

R

CIP

F

CIP

T

DUTY

T

CK2OUT

Low-to-High Rise Time Transition

High-to-Low Fall Time Transition

ODCK Cycle Time

ODCK Frequency

ODCK Duty Cycle

Clock-to-Output Delay

Conditions

C

L

= 10 pF

C

L

= 10 pF

C

L

= 10 pF

C

L

= 10 pF

C

L

= 10 pF

C

L

= 10 pF

Min

13

25

40%

0.8

Typ

Max

3

3

40

82.5

60%

3.8

Units Figure

ns ns ns

Figure 4.6

Figure 4.6

Figure 4.7

Notes

2

2

8

MHz

R

CIP ns

Figure 4.7

Figure 4.7

5

3

4.4.2.2.

16/20/24/30/36-Bit Data Output Timings

Symbol Parameter Conditions

D

LHT

D

HLT

T

DUTY

T

CK2OUT

R

CIP

Low-to-High Rise Time Transition

High-to-Low Fall Time Transition

ODCK Duty Cycle

ODCK-to-Output Delay

Output Clock

Cycle Time

SiI9233CTU

C

L

= 10 pF

C

L

= 10 pF

C

L

= 10 pF

C

L

= 10 pF

C

L

= 10 pF

F

CIP

Output Clock

Frequency

SiI9233CTU C

L

= 10 pF

Min

40%

0.92

6.06

25

Typ

Max

3

3

60%

2.9

40

165 ns

R

CIP ns ns

Units Figure

ns

Figure 4.6

Notes

2

Figure 4.6

2

Figure 4.7

3

Figure 4.7

Figure 4.7

5, 8

MHz

Figure 4.7

5

Notes:

1. Under normal operating conditions unless otherwise specified, including output pin loading of C

L

=10 pF.

2. Rise time and fall time specifications apply to HSYNC, VSYNC, DE, ODCK, EVNODD and Q[35:0].

3. Output clock duty cycle is independent of the differential input clock duty cycle. Duty cycle is a component of output setup and hold times.

4. See Table 4.2

on page 34 for calculation of worst case output setup and hold times.

5. All output timings are defined at the maximum operating ODCK frequency, F

CIP

, unless otherwise specified.

6. F

CIP

can be the same as F

RXC

or one-half of F

RXC

, depending on OCLKDIV setting. F color mode is being transmitted.

CIP can also be F

RXC

/1.25 or F

RXC

/1.5 if deep

7. R

CIP is the inverse of F

CIP

and is not a controlling specification.

8. Output skew specified when ODCK is programmed to divide-by-two mode.

4.4.3.

Audio Output Timings

4.4.3.1.

I

2

S Output Port Timings

Symbol

T tr

T

HC

T

LC

T

T

SU

HD

Parameter

SCK Clock Period (TX)

SCK Clock HIGH Time

SCK Clock LOW Time

Setup Time, SCK to SD/WS

Hold Time, SCK to SD/WS

Conditions

C

L

= 10 pF

C

L

= 10 pF

C

C

C

L

= 10 pF

L

= 10 pF

L

= 10 pF

Min

1.00

0.35

0.35

0.4T

TR

– 5

0.4T

TR

– 5

T

SCKDUTY

T

SCK2SD

T

AUDDLY

SCK Duty Cycle

SCK to SD or WS Delay

Audio Pipeline Delay

C

C

L

L

= 10 pF

= 10 pF

40%

–5

Notes:

1. Refer to Figure 4.8

. Meets timings in Philips I

2

S Specification.

2. Applies also to SDC-to-WS delay.

Typ

40

Max Units Figure

— T tr

Figure 4.8

Notes

1

T tr

T tr

1

1

— ns ns

1

1

60% T tr

+5

80 ns

µs —

1

2

© 2008-2016 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal . All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice.

26 SiI-DS-1032-A

SiI9233 HDMI Receiver with Repeater, Multi-channel Audio, and Deep Color Output

Data Sheet

4.4.3.2.

S/PDIF Output Port Timings

Symbol

T

SPCYC

F

SPDIF

T

SPDUTY

T

MCLKCYC

F

MCLK

T

MCLKDUTY

T

AUDDLY

Parameter

SPDIF Cycle Time

SPDIF Frequency

SPDIF Duty Cycle

MCLK Cycle Time

MCLK Frequency

MCLK Duty Cycle

Audio Pipeline Delay

Conditions

C

L

= 10 pF

C

L

= 10 pF

C

C

C

L

L

L

= 10 pF

= 10 pF

= 10 pF

Min

4

90%

20

4

40%

Typ

1.0

40

Max

24

110%

250

50

60%

80

Units

UI

MHz

UI ns

MHz

T

MCLKCYC

µs

Figure

Figure 4.9

Figure

4.10

Notes

1, 2

3

2, 5

1, 2, 4

1, 2, 4

2, 4

Notes:

1. Guaranteed by design.

2. Proportional to unit time (UI), according to sample rate.

3. SPDIF is not a true clock, but is generated from the internal 128Fs clock, for Fs from 128 to 512 kHz.

4. MCLK refers to MCLKOUT.

5. Intrinsic jitter on S/PDIF output can limit its use as an S/PDIF transmitter. The S/PDIF intrinsic jitter is approximately 0.1UI.

4.4.3.3.

Audio Crystal Timings

Symbol Parameter

F

XTAL

External Crystal Freq.

Conditions

Min

Typ

27

Max

Units

MHz

Figure Notes

Figure 4.1

1, 2

3.3 V

3

XTALVCC

5

XTALIN

SiI9233

18 pF

27MHz

1 M

4

XTALOUT

18 pF

Figure 4.1. Audio Crystal Schematic for the SiI9233 Receiver

Notes:

1. The HDMI Receiver has been fully characterized for optimum audio quality and CEC timing calibration using 27.000 MHz.

Use Citizen part number CSA309-27.000MABJ crystal or equivalent. A less expensive, but not fully characterized circuit, can use a TTL level clock source.

2. The XTALIN/XTALOUT pin pair must be driven with a clock in all applications.

© 2008-2016 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal . All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice.

SiI-DS-1032-A 27

SiI9233 HDMI Receiver with Repeater, Multi-channel Audio, and Deep Color Output

Data Sheet

4.4.4.

Miscellaneous Timings

Symbol Parameter

T

I2CDVD

SDA Data Valid delay from SCL falling edge

Conditions Min

C

L

= 400 pF —

Typ

Max

700

Units Figure

ns —

Notes

F

DDC

F

I

2

C

Speed on TMDS DDC Ports

Speed on Local I

2

C Port

T

RESET

RESET# Signal Low Time for valid reset

T

STARTUP

Startup time from power supplies valid

T

BKSVINIT

HDCP BKSV Load Time

C

L

= 400 pF —

C

L

= 400 pF —

50

100

400

100 kHz kHz

µs ms

Figure 4.5

2

3

5

— — — 2.2 ms — 4

Notes:

1. Under normal operating conditions unless otherwise specified, including output pin loading of C

L

= 10 pF.

2. DDC ports are limited to 100 kHz by the HDMI Specification, and meet I

2

C standard mode timings.

3. Local I

2

C port (CSCL/CSDA) meets standard mode I

2

C timing requirements to 400 kHz.

4. The time required to load the KSV values internal to the HDMI Receiver after a RESET# and the start of an active TMDS clock. An attached HDCP host device should not attempt to read the HDMI receiver BKSV values until after this time. The

T

BKSVINIT

Min and Max values are based on the maximum and minimum allowable XCLK frequencies. The loading of the

BKSV values requires a valid XCLK and TMDS clock.

5. T

STARTUP is the startup time required for the device to be operational once power is stable. This startup time is due to the on board voltage regulator for the EDID and CEC and a power on reset circuit.

4.4.5.

Interrupt Timings

4.4.5.1.

Interrupt Output Pin Timings

Symbol Parameter Conditions Min Typ Max Units Figure Notes

T

FSC

Link disabled (DE inactive) to SCDT LOW — — 0.15 40 ms

Figure 4.2

1, 2, 3, 8

T

HSC

T

CICD

T

CACD

T

INT

T

CIOD

T

CAOD

T

SRRF

Link enabled (DE active) to SCDT HIGH

RXC inactive to CKDT LOW

RXC active to CKDT HIGH

Response Time for INT from Input Change

RXC inactive to ODCK inactive

RXC active to ODCK active and stable

4

100

10

100

100

10

DE

µs

µs

µs ns ms

Figure 4.2

Figure 4.2

Figure 4.2

1, 2, 4, 8

1, 2, 8

1, 2, 8

1, 5, 8

1, 8

1, 6, 8

Delay from SCDT rising edge to Software

Reset falling edge

— — — 100 ms

Figure 4.5

7

Notes:

1. Guaranteed by design.

2. SCDT and CKDT are register bits in this device.

3. SCDT changes to LOW after DE is HIGH for approximately 4096 pixel clock cycles, or after DE is LOW for approximately

1,000,000 clock cycles. At 27 MHz pixel clock, this delay for DE HIGH is approximately 150 µs, and the delay for DE LOW is approximately 40 ms.

4. SCDT changes to HIGH when clock is active (T

CACD

) and at least 4 DE edges have been recognized. At 720p, the DE period is

22 µs, so SCDT responds approximately 50 µs after T

CACD

.

5.

The INT pin changes state after a change in input condition when the corresponding interrupt is enabled.

6.

7.

Output clock (ODCK) becomes active before it becomes stable. Use the SCDT signal as the indicator of stable video output timings, as this depends on decoding of DE signals with active RXC (see T

FSC

).

Software Reset must be asserted and then de-asserted within the specified maximum time after rising edge of Sync Detect

(SCDT). Access to both SWRST and SCDT can be limited by the speed of the I

2

C connection.

8.

SCDT is HIGH only when CKDT is also HIGH. When the HDMI Receiver is in a powered-down mode, the INT output pin indicates the current state of SCDT. Thus, a power-down HDMI Receiver signals a micro connected to the INT pin whenever

SCDT changes from LOW to HIGH or HIGH to LOW.

© 2008-2016 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal . All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice.

28 SiI-DS-1032-A

SiI9233 HDMI Receiver with Repeater, Multi-channel Audio, and Deep Color Output

Data Sheet

RXC

link clock active link clock inactive link clock active

CKDT

T

CICD

T

CACD

DE

Do not Care

T

FSC

T

HSC

SCDT

Figure 4.2. SCDT and CKDT Timing from DE or RXC Inactive/Active

Notes:

1. The SCDT shown in Figure 4.2

is a register bit. SCDT remains HIGH if DE is stuck in LOW while RXC remains active, but SCDT

changes to LOW if DE is stuck HIGH while RXC remains active.

2. The CKDT shown in Figure 4.2

is a register bit. CKDT changes to LOW whenever RXC stops, and changes to HIGH when RXC

starts. SCDT changes to LOW when CKDT changes to LOW.

3. SCDT changes to LOW when CKDT changes to LOW. SCDT changes to HIGH at T

HSC

after CKDT changes to HIGH.

4. The INT output pin changes state after the SCDT or CKDT register bit is set or cleared if those interrupts are enabled.

Refer to the SiI9223/9233/9127 HDMI Receivers Programmer’s Reference (SiI-PR-1019) for more details on controlling timing modes.

4.5.

Timing Diagrams

4.5.1.

TMDS Input Timing Diagrams

RX0

RX1

RX2

T

CCS

V

DIFF

= 0V

Figure 4.3. TMDS Channel-to-Channel Skew Timing

© 2008-2016 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal . All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice.

SiI-DS-1032-A 29

SiI9233 HDMI Receiver with Repeater, Multi-channel Audio, and Deep Color Output

Data Sheet

4.5.2.

Power Supply Control Timings

Power On Sequence maximum 3.3 V excursion

IOVCC33

AVCC33

XTALVCC33

DIFF33 max minimum 3.3 V excursion

DIFF3312 max maximum 3.3 V excursion

IOVCC33

AVCC33

XTALVCC33 minimum 3.3 V excursion maximum 1.2 V excursion

DIFF33 max maximum 1.2 V excursion

DIFF3312 max

AVCC12

CVCC12 minimum 1.2 V excursion

DIFF12 max

AVCC12

CVCC12 minimum 1.2 V excursion

DIFF12 max

Figure 4.4. Power Supply Sequencing

4.5.3.

Reset Timings

VCC max

VCC min

VCC

RESET#

Power Off Sequence

T

RESET

RESET#

T

RESET

Note that VCC must be stable between its limits for Normal

Operating Conditions for T

RESET

before RESET# is HIGH.

RESET# must be pulled LOW for T

RESET

before accessing registers. This can be done by holding RESET# LOW until T

RESET after stable power (at left); OR by pulling RESET# LOW from a

HIGH state (at right) for at least T

RESET

.

Figure 4.5. RESET# Minimum Timings

© 2008-2016 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal . All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice.

30 SiI-DS-1032-A

SiI9233 HDMI Receiver with Repeater, Multi-channel Audio, and Deep Color Output

Data Sheet

4.5.4.

Digital Video Output Timing Diagrams

4.5.4.1.

Output Transition Times

2.0V

2.0V

0.8V

0.8V

D

LHT

D

HLT

Figure 4.6. Video Digital Output Transition Times

4.5.4.2.

Output Clock to Output Data Delay

T

CYC

T

H

T

L

OCLKINV = 0

ODCK

OCLKINV = 1

ODCK

T

CKO(min)

T

CKO(max)

Q[35:0]

DE

HSYNC

VSYNC

T

CKO(min)

T

CKO(max)

Figure 4.7. Receiver Clock-to-Output Delay and Duty Cycle Limits

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SiI-DS-1032-A 31

SiI9233 HDMI Receiver with Repeater, Multi-channel Audio, and Deep Color Output

Data Sheet

4.5.5.

Digital Audio Output Timings

T

TR

T

SCKDUTY

SCK

WS

SD

Data Valid

T

SCK2SD_MAX

T

SU

T

HD

Data Valid

Figure 4.8. I

2

S Output Timings

T

SPCYC

, T

SPDUTY

T

SPCYC

, T

SPDUTY

T

SCK2SD_MIN

Data Valid

SPDIF

90%

50%

10%

Figure 4.9. S/PDIF Output Timings

MCLK

T

MCLKDUTY

T

MCLKCYC

50%

Figure 4.10. MCLK Timings

50%

© 2008-2016 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal . All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice.

32 SiI-DS-1032-A

SiI9233 HDMI Receiver with Repeater, Multi-channel Audio, and Deep Color Output

Data Sheet

4.6.

Calculating Setup and Hold Times for Video Bus

4.6.1.

24/30/36-Bit Mode

Output data is clocked out on one rising (or falling) edge of ODCK, and is then captured downstream using the same polarity ODCK edge one clock period later. The setup time of data to ODCK and hold time of ODCK to data are therefore

a function of the worst case ODCK to output delay, as shown in Figure 4.11

. The active rising ODCK edge is shown with

an arrowhead. For OCK_INV=1, reverse the logic.

T

CK2OUT

{max} T

SU

T

HD

T

CK2OUT

{min}

ODCK

Longest

Clk-to-Out

Shortest

Clk-to-Out

Q

DE

VSYNC

HSYNC

Data Valid Data Valid

Figure 4.11. 24/30/36-Bit Mode Receiver Output Setup and Hold Times

Table 4.1

shows minimum calculated setup and hold times for commonly used ODCK frequencies. The setup and hold

times apply to DE, VSYNC, HSYNC and Data output pins, with output load of 10pF. These are approximations. Hold time is not related to ODCK frequency.

Table 4.1. Calculation of 24/30/36-Bit Output Setup and Hold Times

24/30/36-

Bit Mode

Symbol

T

SU

Parameter

Setup Time to ODCK

= T

ODCK

-T

CK2OUT

{max}

T

HD

Hold Time from ODCK = T

CK2OUT

{min}

T

ODCK

27 MHz

74.25 MHz

27 MHz

37.0 ns

13.5 ns

37.0 ns

Min

33.2 ns

9.7 ns

0.8 ns

© 2008-2016 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal . All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice.

SiI-DS-1032-A 33

SiI9233 HDMI Receiver with Repeater, Multi-channel Audio, and Deep Color Output

Data Sheet

4.6.2.

12/15/18-Bit Dual-Edge Mode

Output data is clocked out on each edge of ODCK (both rising and falling), and is then captured downstream using the opposite ODCK edge. The setup time of data to ODCK is a function of the shortest duty cycle and the longest ODCK to output delay. The hold time does not depend on duty cycle (since every edge is used), and is a function only of the shortest ODCK to output delay.

T

SU

T

HD

ODCK

T

DUTY

{min}

T

CK2OUT

{max}

T

CK2OUT

{min}

Q

DE

VSYNC

HSYNC

Data Valid Data Valid

Figure 4.12. 12/15/18-Bit Mode Receiver Output Setup and Hold Times

Table 4.2

shows minimum calculated setup and hold times for commonly used ODCK frequencies, up to the maximum

allowed for 12/15/18-bit mode. The setup and hold times apply to DE, VSYNC, HSYNC and Data output pins, with output load of 10 pF. These are approximations. Hold time is not related to ODCK frequency.

Table 4.2. Calculation of 12/15/18-Bit Output Setup and Hold Times

12/15/18-

Bit Mode

Symbol Parameter

T

SU

Setup Time to ODCK

=T

ODCK

•T

DUTY

{min}-T

CK2OUT

{max}

T

HD

Hold Time from ODCK = T

CK2OUT

{min}

T

ODCK

27 MHz

74.25 MHz

27 MHz

37.0 ns

13.5 ns

37.0 ns

Min

34.1 ns

10.6 ns

0.8ns

© 2008-2016 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal . All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice.

34 SiI-DS-1032-A

SiI9233 HDMI Receiver with Repeater, Multi-channel Audio, and Deep Color Output

Data Sheet

4.7.

Calculating Setup and Hold Times for I

2

S Audio Bus

Valid serial data is available at T sck2sd

after the falling edge of the first SCK cycle, and then captured downstream using the active rising edge of SCK one clock period later. The setup time of data to SCK (T

SU

) and hold time of SCK to data

(T

HD

) are therefore a function of the worst case SCK-to-output data delay (Tsck2sd). Figure 4.8

illustrates this timing

relationship. Note that the active SCK edge (rising edge) is shown with an arrowhead. For a falling edge sampling clock, the logic is reversed.

Table 4.3

shows the setup and hold time calculation examples for various audio sample frequencies. The formula used

in these examples also applies when calculating the setup and hold times for other audio sampling frequencies.

Table 4.3. I

2

S Setup and Hold Time Calculations

Symbol

T

T

SU

HD

Parameter

Setup Time, SCK to SD/WS

= T

TR

– ( T

SCKDUTY

_

WORST

+ T

SCK

2

SD

_

MAX

)

= T

TR

– (0.6T

TR

+ 5ns )

= 0.4T

TR

– 5ns

Hold Time, SCK to SD/WS

= ( T

SCKDUTY

_

WORST

- T

= 0.4T

TR

– 5ns

SCK

2

SD

_

MIN

)

FWS (kHz)

32 kHz

44.1 kHz

48 kHz

96 kHz

192 kHz

32 kHz

44.1 kHz

48 kHz

96 kHz

192 kHz

Note: The sample calculations shown are based on WS=64 SCLK rising edges.

FSCLK (MHz)

2.048

2.822

3.072

6.144

12.288

2.048

2.822

3.072

6.144

12.288

Ttr

488 ns

354 ns

326 ns

163 ns

81 ns

488 ns

354 ns

326 ns

163 ns

81 ns

Min

190 ns

136 ns

125 ns

60 ns

27 ns

190 ns

136 ns

125 ns

60 ns

27 ns

© 2008-2016 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal . All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice.

SiI-DS-1032-A 35

SiI9233 HDMI Receiver with Repeater, Multi-channel Audio, and Deep Color Output

Data Sheet

5. Pin Diagram and Descriptions

Figure 5.1

shows the pin connections for the SiI9233 in the 144-pin TQFP package. Individual pin functions are described beginning on page 36.

25

26

27

28

21

22

23

24

18

19

20

14

15

16

17

32

33

34

35

29

30

31

36

7

8

9

10

11

12

13

4

5

6

1

2

3

RSVDNC

APVCC12

XTALVCC33

XTALOUT

XTALIN

XTALGND

IOVCC33

CVCC12

RSVDNC

RSVDNC

RSVDL

GPIO0/XCLKOUT

GPIO 1/SCDT

GPIO2/EVNODD

RSVDNC

GPIO4

GPIO5

RSVDNC

GPIO6/DL3

GPIO7/DR3

RESET#

INT

CSCL

CSDA

CI 2CA

CEC_ A

CEC_D

SBVCC5

R0PWR 5V

HPD 0

DSCL0

DSDA0

R1 PWR5V

HPD1

DSCL1

DSDA1

144-pin TQFP

(Top View )

90

89

88

87

86

85

84

83

82

81

80

79

78

77

76

75

74

73

108

107

106

105

104

103

102

101

100

99

98

97

96

95

94

93

92

91

Q13

Q14

Q15

Q16

Q17

ODCK

HSYNC

VSYNC

DE

Q3

Q4

Q5

Q6

CVCC 12

Q0

Q1

Q2

Q7

Q8

IOVCC 33

CVCC 12

Q9

Q10

Q11

Q12

AVCC33

GPIO3 / MUTEOUT

SPDIF/DL2

MCLK

SD3/DR2

SD2/DL1

SD1/DR1

SD0/DL0

SCK/DCLK

WS/DR0

IOVCC 33

Figure 5.1. Pin Diagram

© 2008-2016 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal . All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice.

36 SiI-DS-1032-A

5.1.

Pin Descriptions

SiI9233 HDMI Receiver with Repeater, Multi-channel Audio, and Deep Color Output

Data Sheet

5.1.1.

Digital Video Output Pins

Pin Name

Q0

Q1

Q10

Q11

Q12

Q13

Q14

Q15

Q16

Q17

Q2

Q3

Q4

Q5

Q6

Q7

Q8

Q9

Pin #

96

95

84

83

82

81

80

79

78

77

94

93

92

91

90

89

88

85

Strength Type

Programmable LVTTL

Dir

Output

Description

36-Bit Output Pixel Data Bus. The Q[35:0] bus is highly configurable using the various video configuration registers. It supports a wide array of output formats, including multiple RGB and

YCbCr bus formats. Using the appropriate bits in the PD_SYS2 register, the output drivers can be put into a high impedance (tri-state) mode. A weak, internal pull-down device brings each output to ground.

Q28

Q29

Q30

Q31

Q32

Q33

Q34

Q35

Q23

Q24

Q25

Q26

Q27

Q18

Q19

Q20

Q21

Q22

70

69

68

67

66

65

64

63

62

59

58

57

56

55

54

53

52

51

DE

HSYNC

73

75

Programmable LVTTL

Programmable LVTTL

Output

Output

Data Enable.

Horizontal Sync Output

VSYNC

GPIO2 / EVNODD

74

14

Programmable

8 mA

LVTTL

LVTTL

Output

Bi-Di

Vertical Sync Output

Programmable GPIO2 or Indicates Even or Odd

Field for Interlaced Formats.

Output Data Clock. ODCK 76 Programmable LVTTL Output

Notes:

1.

HSYNC and VSYNC outputs carry sync signals for both embedded and separate sync configurations.

© 2008-2016 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal . All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice.

SiI-DS-1032-A 37

SiI9233 HDMI Receiver with Repeater, Multi-channel Audio, and Deep Color Output

Data Sheet

2.

When transporting video data that uses fewer than 36 bits, the unused bits on the Q[] bus can still carry switching pixel data signals. Unused Q[35:0] bus pins should be unconnected, masked or ignored by downstream devices. For example,

carrying YCbCr 4:2:2 data with 16-bit width (see page 51), the bits Q[0] through Q[7] output switching signals.

3.

The output data bus, Q0 to Q35, can be wire-ORed to another device such that one device is always tri-stated. However, the Q0-Q35 pins do not have bus hold internal pull-up or pull-down resistors, and so cannot pull the bus HIGH or LOW when all connected devices are tri-stated.

4.

The drive strength of these pins can be programmed in 2-mA steps between 2 mA and 14 mA: Q[0:35], DE, HSYNC, VSYNC, and ODCK.

5.1.2.

Digital Audio Output Pins

Pin Name

XTALIN

XTALOUT

GPIO0 /

XCLKOUT

MCLK

SCK/DCLK

SD3/DR2

SD2/DL1

SD1/DR1

SD0/DL0

WS/DR0

Pin #

5

4

12

105

100

104

103

102

101

99

Strength Type

4 mA

4 mA

8 mA

4 mA

4 mA

4 mA

5-V tolerant

LVTTL

LVTTL

LVTTL

LVTTL

LVTTL

LVTTL

LVTTL

Dir Description

In Crystal Clock Input. Also allows LVTTL input.

Frequency required: 26-28.5 MHz

Out Crystal Clock Output

Bi-Di Programmable GPIO0 or additional Clock Output from crystal oscillator circuit

Bi-Di Audio Master Clock Output.

Out

I

2

S

Serial Clock Output.

Out I

2

S Serial Data Output / DSD Audio Output

Configurable to be shared with DSD.

SD0 = DSD Serial Left Ch0 Data Output

SD1 = DSD Serial Right Ch1 Data Output

SD2 = DSD Serial Left Ch1 Data Output

SD3 = DSD Serial Right Ch2 Data Output

Out

I

2

S

Word Select Output. DSD Serial Right Ch0

Data Output.

SPDIF/DL2

GPIO6/DL3

106

19

4 mA

4 mA

LVTTL

LVTTL

Out S/PDIF Audio Output. DSD Serial Left Channel 2 data output.

Bi-Di Programmable GPIO6. DSD Serial Left Channel 3 data output.

GPIO7/DR3

GPIO3/

MUTEOUT

20

107

4 mA

4 mA

LVTTL

LVTTL

Bi-Di Programmable GPIO7. DSD Serial Right Channel 3 data output.

Bi-Di Programmable GPIO3 or Mute Audio Output.

Signal to the external downstream audio device, audio DAC, etc. to mute audio output.

Note: The XTALIN pin can either be driven at LVTTL levels by a clock (leaving XTALOUT unconnected), or connected through a crystal

to XTALOUT. Refer to the schematic on page 73 .

© 2008-2016 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal . All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice.

38 SiI-DS-1032-A

SiI9233 HDMI Receiver with Repeater, Multi-channel Audio, and Deep Color Output

Data Sheet

5.1.3.

Configuration/Programming Pins

Pin Name

INT

Pin #

22

Strength Type

4 mA LVTTL

Dir Description

Out Interrupt Output. Configurable polarity and push-pull output. Multiple sources of interrupt can be enabled through the INT_EN register.

See Note 1.

RESET#

CSCL

CSDA

CI2CA

GPIO1/SCDT

GPIO4

GPIO5

RSVDNC

21

23

24

25

13

16

17

1, 9, 10, 15, 18,

46–49

3 mA

4 mA

4 mA

4 mA

Schmitt

Schmitt

Schmitt

LVTTL

LVTTL

LVTTL

LVTTL

In

In

Reset Pin. Active LOW. 5-V tolerant

Configuration/Status I

2

C Clock. 5-V tolerant. Chip configuration/status, CEA-861 support and downstream HDCP repeater-specific registers are accessed via this I

2

C port. True open drain, so does not pull to GND if power is not applied.

Bi-Di Configuration/Status I

2

C Data. 5-V tolerant. Chip configuration/status, CEA-861 support and

In downstream HDCP repeater-specific registers are accessed via this I

2

C port. True open drain, so does not pull to GND if power is not applied.

Local I

2

C Address Select. 5-V tolerant

Low = Addresses 0x60/0x68

High = Addresses 0x62/0x6A

Out Programmable GPIO1 or SCDT. Indicates Active Video at HDMI Input Port. Sync detection indicator.

Bi-Di Programmable GPIO4

Bi-Di

Programmable GPIO5

Reserved, must be left unconnected

RSVDL 11 — — In Reserved, must be tied to ground

Note: The INT pin can be programmed to be either a push-pull LVTTL output or an open-drain output.

© 2008-2016 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal . All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice.

SiI-DS-1032-A 39

SiI9233 HDMI Receiver with Repeater, Multi-channel Audio, and Deep Color Output

Data Sheet

5.1.4.

HDMI Control Signal Pins

Pin Name Pin # Strength Type

— SchmittOD DSCL0

DSCL1

DSCL2

DSCL3

DSDA0

DSDA1

DSDA2

DSDA3

HPD0

HPD1

HPD2

HPD3

R0PWR5V

R1PWR5V

R2PWR5V

R3PWR5V

CEC_A

29

33

37

41

30

34

38

42

26

32

36

40

44

31

35

39

43

3 mA

4 mA

SchmittOD

LVTTL

LVTTL

CEC compliant

5-V tolerant

Dir

In

Bi-Di

Out

In

Bi-Di

CEC_D

RSVDCEC

27

45

LVTTL

Schmitt

Bi-Di

Description

DDC I2C Clock for respective port. 5-V tolerant.

HDCP KSV, An and Ri values are exchanged over an

I2C port during authentication. True open drain, so does not pull to GND if power is not applied.

DDC I2C Data for respective port. 5-V tolerant.

HDCP KSV, An and Ri values are exchanged over an

I2C during authentication. True open drain, so does not pull to GND if power is not applied.

Hotplug output signal to HDMI connector for respective port. Indicates EDID is readable. See the

Hot Plug Detect CTS Requirement section for

important information.

5V power and port detection input for respective port. 5-V tolerant. Used to power internal EDID when device is not powered. See Note 1,2

HDMI compliant CEC I/O used to interface to CEC devices. This pin connects to the CEC signal of all

HDMI connectors in the system.

This pin has an internal pull-up resistor.

CEC interface to local system. True open-drain. An external pull-up is required. This pin typically connects to the local CPU.

Reserved

Note:

1. There is no power sequence requirement on RxPWR5V pins.

2. The operation condition of the RxPWR5V pins is 5 V ±5%.

© 2008-2016 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal . All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice.

40 SiI-DS-1032-A

SiI9233 HDMI Receiver with Repeater, Multi-channel Audio, and Deep Color Output

Data Sheet

5.1.5.

Differential Signal Data Pins

Pin Name Pin # Type

Analog

R3XC+

R3XC-

R3X0+

R3X0-

R3X1+

R3X1-

R3X2+

R3X2-

R2XC+

R2XC-

R2X0+

R2X0-

R2X1+

R2X1-

R2X2+

R2X2-

R0XC+

R0XC-

R0X0+

R0X0-

R0X1+

R0X1-

R0X2+

R0X2-

R1XC+

R1XC-

R1X0+

R1X0-

R1X1+

R1X1-

R1X2+

R1X2-

137

136

139

138

141

140

143

142

128

127

130

129

132

131

134

133

120

123

122

125

124

116

115

119

118

121

110

109

112

111

114

113

Analog

Analog

Analog

Analog

Analog

Analog

Analog

Description

TMDS Input Clock Pair.

TMDS Input Data Pairs.

TMDS Input Clock Pair.

TMDS Input Data Pairs.

TMDS Input Clock Pair.

TMDS Input Data Pairs.

TMDS Input Clock Pair.

TMDS Input Data Pairs.

HDMI Port 0

HDMI Port 1

HDMI Port 2

HDMI Port 3

© 2008-2016 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal . All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice.

SiI-DS-1032-A 41

SiI9233 HDMI Receiver with Repeater, Multi-channel Audio, and Deep Color Output

Data Sheet

5.1.6.

Power and Ground Pins

Pin Name

CVCC12

IOVCC33

AVCC33

AVCC12

APVCC12

XTALVCC33

XTALGND

SBVCC5

GND

Pin #

8, 60, 71, 86, 97

7, 61, 72, 87, 98

108, 126, 144

117, 135

2

3

6

28

50, ePad (bottom of package)

Type

Power

Power

Power

Power

Power

Power

Ground

Power

Ground

Description

Digital Logic VCC

Input/Output Pin VCC

TMDS Analog VCC 3.3V

TMDS Analog VCC 1.2V

Audio Clock Regeneration PLL Analog

VCC. Must be connected to 1.2V

Supply

1.2 V

3.3 V

3.3 V

1.2 V

1.2 V

Audio Clock Regeneration PLL Crystal

Oscillator Power. Must be connected to

3.3V

Audio Clock Regeneration ground

Standby power supply. All other supplies can be off with SBVCC5 on ePad must be soldered to ground

3.3 V

Ground

5 V

Ground

VCCTP

Parasitic

Resistor

0.56

0.1

F

Ferrite

0. 82

H,

150 mA +

10

F

0.1

F 1 nF

AVCC12

SiI9233

GND

Figure 5.2. Test Point VCCTP for VCC Noise Tolerance Spec

Notes:

1. The Ferrite (0.82

H, 150 mA) attenuates the PLL power supply noise at 10’s of KHz and above.

The optional parasitic resistor minimizes the peaking. The typical value used here is 0.56

. 1

 is the maximum

© 2008-2016 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal . All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice.

42 SiI-DS-1032-A

SiI9233 HDMI Receiver with Repeater, Multi-channel Audio, and Deep Color Output

Data Sheet

6. Video Path

The SiI9233 receiver accepts all valid HDMI input formats and can transform that video in a variety of ways to produce the proper video output format. The following pages describe how to control the video path formatting and how to assign output pins for each video output format.

TMDS HDCP

Widen to

14-Bits

InfoFrame

Packet

Processing

Audio

Processing

I2S Outputs

MCLK

SPDIF

SCK

WS

SD[3:0]

RGB to

YCbCr bypass

YCbCr

Range

Reduce bypass

Down

Sample

4:4:4 to

4:2:2 bypass

DSD Outputs

Note: DSD outputs are shared with SPDIF and

I2S signals

DCLK

DR[3:0]

DL[3:0]

Upsample

4:2:2 to

4:4:4 bypass xvYCC/

YCbCr to

RGB bypass

RGB

Range

Expand bypass

Dither

Module

Mux

656

Video

Timing

DE

HSYNC

VSYNC

ODCK

Q[35:0]

Figure 6.1. Receiver Video and Audio Data Processing Paths

The processing blocks in the figure above correspond to those shown in Figure 6.2

through Figure 6.4

.

© 2008-2016 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal . All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice.

SiI-DS-1032-A 43

SiI9233 HDMI Receiver with Repeater, Multi-channel Audio, and Deep Color Output

Data Sheet

6.1.

HDMI Input Modes to SiI9233 Receiver Output Modes

The HDMI link supports transport of video in any of three modes: RGB 4:4:4, YCbCr 4:4:4 or YCbCr 4:2:2. The flexible

video path in the SiI9233 allows reformatting of video data to a set of output modes. Table 6.1

lists the supported

transformations and points to the figure for each. In every case, the HDMI link itself carries separate syncs.

Table 6.1. Translating HDMI Formats to Output Formats

Output Format

Digital

Output

Syncs

RGB 4:4:4

Separate

YCbCr 4:4:4

Separate

YCbCr 4:2:2

Separate

RGB 4:4:4

Figure 6.2A Figure 6.2B Figure 6.2C

YCbCr

4:4:4

YCbCr

4:2:2

Figure 6.3A

Figure 6.4A

Figure 6.3B

Figure 6.4B

Figure 6.3C

Figure 6.4C

YCbCr 4:2:2 YC Mux

Embedded Separate

YC Mux

Embedded Note

Figure 6.2D Figure 6.2E Figure 6.2F

Figure 6.3D Figure 6.3E Figure 6.3F

Figure 6.4D Figure 6.4E Figure 6.4F

© 2008-2016 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal . All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice.

44 SiI-DS-1032-A

SiI9233 HDMI Receiver with Repeater, Multi-channel Audio, and Deep Color Output

Data Sheet

6.1.1.

HDMI RGB 4:4:4 Input Processing

TMDS and

HDCP

Decoding

Digital Out

Digital Out

TMDS and

HDCP

Decoding

RGBtoYCbCr

Color Range

Scaling

Color Range

Scaling

DownSampling

Digital Out

TMDS and

HDCP

Decoding

RGBtoYCbCr

Color Range

Scaling

DownSampling

Digital Out

TMDS and

HDCP

Decoding

RGBtoYCbCr

Embedded

Syncs

Color Range

Scaling

DownSampling

Digital Out

TMDS and

HDCP

Decoding

RGBtoYCbCr MUX YC

TMDS and

HDCP

Decoding

RGBtoYCbCr

Color Range

Scaling

Down

Sampling

Embedded

Syncs

MUX YC

Figure 6.2. HDMI RGB 4:4:4 Input to Video Output Transformations

Digital Out

A

B

C

D

E

F

© 2008-2016 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal . All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice.

SiI-DS-1032-A 45

SiI9233 HDMI Receiver with Repeater, Multi-channel Audio, and Deep Color Output

Data Sheet

6.1.2.

HDMI YCbCr 4:4:4 Input Processing

TMDS and

HDCP

Decoding

YCbCr to RGB

TMDS and

HDCP

Decoding

TMDS and

HDCP

Decoding

TMDS and

HDCP

Decoding

TMDS and

HDCP

Decoding

TMDS and

HDCP

Decoding

DownSampling

DownSampling

DownSampling

DownSampling

Embedded

Syncs

Embedded

Syncs

MUX YC

MUX YC

Figure 6.3. HDMI YCbCr 4:4:4 Input to Video Output Transformations

Digital Out

Digital Out

B

Digital Out

A

C

Digital Out

D

Digital Out

E

Digital Out

F

© 2008-2016 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal . All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice.

46 SiI-DS-1032-A

SiI9233 HDMI Receiver with Repeater, Multi-channel Audio, and Deep Color Output

Data Sheet

6.1.3.

HDMI YCbCr 4:2:2 Input Processing

Digital Out

TMDS and

HDCP

Decoding

Upsampling YCbCr to RGB

A

Digital Out

TMDS and

HDCP

Decoding

UpSampling

B

Digital Out

TMDS and

HDCP

Decoding

C

Digital Out

TMDS and

HDCP

Decoding

Embedded

Syncs

D

Digital Out

TMDS and

HDCP

Decoding

MUX YC

E

Digital Out

TMDS and

HDCP

Decoding

Embedded

Syncs

MUX YC

F

Figure 6.4. HDMI YCbCr 4:2:2 Input to Video Output Transformations

© 2008-2016 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal . All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice.

SiI-DS-1032-A 47

SiI9233 HDMI Receiver with Repeater, Multi-channel Audio, and Deep Color Output

Data Sheet

6.2.

SiI9233 Receiver Output Mode Configuration

The SiI9233 receiver supports multiple output data mappings. Some have separate control signals while some have embedded control signals. The selection of data mapping mode should be consistent at the pins and in the corresponding register settings. Refer to the SiI9223/9233/9127 HDMI Receivers Programmer’s Reference (SiI-PR-1019) for more details.

Table 6.2. Output Video Formats

Output Mode

RGB 4:4:4

Data Widths Pixel Replication

Syncs

24, 30, 36 1x Separate

YCbCr 4:4:4

YC 4:2:2 Sep. Syncs

YC 4:2:2 Sep. Syncs

YC 4:2:2 Emb. Syncs

YC MUX 4:2:2

YC MUX 4:2:2 Emb. Syncs

24, 30, 36

16, 20, 24

16, 20, 24

16, 20, 24

8, 10, 12

8, 10, 12

1x

1x

2x

1x

2x

2x

Separate

Separate

Separate

Embedded

Separate

Embedded

51

54

57

59

Page

49

49

51

Notes

3, 7

1. 3. 7

2, 3

2, 3, 8

2, 5

2, 4, 8

2, 5, 6, 8, 9

Notes:

1. YC 4:4:4 data contains one Cr, one Cb and one Y value for every pixel.

2. YC 4:2:2 data contains one Cr and one Cb value for every two pixels; and one Y value for every pixel.

3. These formats can be carried across the HDMI link. Refer to the HDMI Specification, Section 6.2.3. The link clock must be within the specified range of the SiI9233 receiver.

4. In YC MUX mode data is sent to one or two 8/10/12-bit channels.

5. YC MUX with embedded SAV/EAV signal.

6. Syncs are embedded using SAV/EAV codes.

7. A 2x clock can also be sent with 4:4:4 data.

8. When sending a 2x clock the HDMI source must also send AVI InfoFrames with an accurate pixel replication field. Refer to HDMI Spec 1.0, Section 6.4.

9. 2x clocking does not support YC 4:2:2 embedded Sync timings for 720p or 1080i, as the output clock frequency would exceed the range allowed for the SiI9233 receiver.

The SiI9233 receiver can output video in various formats on its parallel digital output bus. Some transformation of the data received over HDMI is necessary in some modes. Digital output is used with either 4:4:4 or 4:2:2 data.

The diagrams do not include separation of the audio and InfoFrame packets from the HDMI stream, which occurs immediately after the TMDS and (optional) HDCP decoding. The HDMI link always carries separate HSYNC and VSYNC and DE. Therefore the SAV/EAV sync encoder must be used whenever the output mode includes embedded sync.

The timing diagrams in Figure 6.5

through Figure 6.9

show only a representation of the DE, HSYNC and VSYNC timings.

These timings are specific to the video resolution, as defined by EIA/CEA-861B and other specs. The number of pixels shown per DE HIGH time is representative, to show the data formatting.

© 2008-2016 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal . All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice.

48 SiI-DS-1032-A

SiI9233 HDMI Receiver with Repeater, Multi-channel Audio, and Deep Color Output

Data Sheet

6.2.1.

RGB and YCbCr 4:4:4 Formats with Separate Syncs

The pixel clock runs at the pixel rate and a complete definition of each pixel is output on each clock. Figure 6.5

shows

RGB data. The same timing format is used for YCbCr 4:4:4 as listed in Table 6.3

.

Figure 6.5

shows timings with OCLKDIV

= 0 and OCKINV = 1.

Table 6.3. 4:4:4 Mappings

Pin 36-bit

Q25

Q26

Q27

Q28

Q29

Q30

Q31

Q32

Q33

Q17

Q18

Q19

Q20

Q21

Q22

Q23

Q24

Q8

Q9

Q10

Q11

Q12

Q13

Q14

Q15

Q16

Q4

Q5

Q6

Q7

Name

Q0

Q1

Q2

Q3

Q34

Q35

HSYNC

VSYNC

DE

HSYNC

VSYNC

DE

R6

R7

R8

R9

R1

R2

R3

R4

R5

R10

R11

G5

G6

G7

G8

G9

G10

G11

R0

G0

G1

G2

G3

G4

B8

B9

B10

B11

B4

B5

B6

B7

RGB

B0

B1

B2

B3

NC

Cr0

Cr1

Cr2

Cr3

Y7

Y8

Y9

NC

Y3

Y4

Y5

Y6

NC

NC

Y0

Y1

Y2

Cr4

Cr5

Cr6

Cr7

Cr8

Cr9

Cb2

Cb3

Cb4

Cb5

Cb6

Cb7

Cb8

Cb9

30-bit

YCbCr

NC

NC

Cb0

Cb1

NC

R0

R1

R2

R3

G7

G8

G9

NC

G3

G4

G5

G6

NC

NC

G0

G1

G2

R4

R5

R6

R7

R8

R9

B6

B7

B8

B9

B2

B3

B4

B5

30-bit

RGB

NC

NC

B0

B1

Cr1

Cr2

Cr3

Cr4

Cr5

Y9

Y10

Y11

Cr0

Y5

Y6

Y7

Y8

Y0

Y1

Y2

Y3

Y4

Cr6

Cr7

Cr8

Cr9

Cr10

Cr11

Cb4

Cb5

Cb6

Cb7

Cb8

Cb9

Cb10

Cb11

36-bit

YCbCr

Cb0

Cb1

Cb2

Cb3

HSYNC

VSYNC

DE

HSYNC

VSYNC

DE

HSYNC

VSYNC

DE

HSYNC

VSYNC

DE

HSYNC

VSYNC

DE

NC

NC

NC

R0

R1

G5

G6

G7

NC

G1

G2

G3

G4

NC

NC

NC

NC

G0

R2

R3

R4

R5

R6

R7

B4

B5

B6

B7

B0

B1

B2

B3

24-bit

RGB

NC

NC

NC

NC

NC

NC

NC

Cr0

Cr1

Y5

Y6

Y7

NC

Y1

Y2

Y3

Y4

NC

NC

NC

NC

Y0

Cr2

Cr3

Cr4

Cr5

Cr6

Cr7

Cb0

Cb1

Cb2

Cb3

Cb4

Cb5

Cb6

Cb7

24-bit

YCbCr

NC

NC

NC

NC

© 2008-2016 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal . All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice.

SiI-DS-1032-A 49

SiI9233 HDMI Receiver with Repeater, Multi-channel Audio, and Deep Color Output

Data Sheet

blank Pixel 0 Pixel 1 Pixel 2 Pixel 3 Pixel 4 Pixel n blank

Q[35:24] val R0 R1 R2 R3 R4 Rn val blank val blank val

Q[23:12] val G0 G1 G2 G3 G4 Gn val val val

Q[11:0]

ODCK val B0 B1 B2 B3 B4 Bn val val val

DE

HSYNC,

VSYNC

Figure 6.5. 4:4:4 Timing Diagram

Note: The val data is defined in various specifications to specific values. These values are controlled by setting the appropriate SiI9233 registers, because no pixel data is carried on HDMI during blanking.

© 2008-2016 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal . All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice.

50 SiI-DS-1032-A

SiI9233 HDMI Receiver with Repeater, Multi-channel Audio, and Deep Color Output

Data Sheet

6.2.2.

YC 4:2:2 Formats with Separate Syncs

The YC 4:2:2 formats output one pixel for every pixel clock period. A luminance (Y) value is sent for every pixel, but the chrominance values (Cb and Cr) are sent over two pixels. Pixel data can be 24-bit, 20-bit or 16-bit. HSYNC and VSYNC

are output separately on their own pins. The DE HIGH time must contain an even number of pixel clocks. Figure 6.6

shows timings with OCLKDIV = 0 and OCKINV = 1.

Table 6.4. YC 4:2:2 Separate Sync Pin Mappings

Q22

Q23

Q24

Q25

Q26

Q27

Q28

Q29

Q30

Q13

Q14

Q15

Q16

Q17

Q18

Q19

Q20

Q21

Q5

Q6

Q7

Q8

Q9

Q10

Q11

Q12

Pin

Name

Q0

Q1

Q2

Q3

Q4

Q31

Q32

Q33

Q34

Q35

HSYNC

VSYNC

DE

Cb3

Cb4

Cb5

Cb6

Cb7

HSYNC

VSYNC

DE

Y6

Y7

NC

NC

NC

NC

Cb0

Cb1

Cb2

Y2

Y3

Y4

Y5

NC

NC

NC

Y0

Y1

NC

NC

NC

NC

NC

NC

NC

NC

16-bit YC

Pixel #0

NC

NC

NC

NC

NC

NC

NC

Cr0

Cr1

Cr2

Y6

Y7

NC

NC

Y2

Y3

Y4

Y5

NC

NC

NC

Y0

Y1

NC

NC

NC

NC

NC

NC

NC

NC

Pixel #1

NC

NC

NC

NC

NC

Cr3

Cr4

Cr5

Cr6

Cr7

HSYNC

VSYNC

DE

Cr0

Cr1

Cr2

Cr3

Cr4

Y8

Y9

NC

NC

Y4

Y5

Y6

Y7

NC

Y0

Y1

Y2

Y3

NC

NC

NC

NC

NC

NC

NC

NC

Pixel #1

NC

NC

NC

NC

NC

Cr5

Cr6

Cr7

Cr8

Cr9

HSYNC

VSYNC

DE

Cb5

Cb6

Cb7

Cb8

Cb9

HSYNC

VSYNC

DE

Y8

Y9

NC

NC

Cb0

Cb1

Cb2

Cb3

Cb4

Y4

Y5

Y6

Y7

NC

Y0

Y1

Y2

Y3

NC

NC

NC

NC

NC

NC

NC

NC

20-bit YC

Pixel #0

NC

NC

NC

NC

NC

Cb7

Cb8

Cb9

Cb10

Cb11

HSYNC

VSYNC

DE

Y10

Y11

Cb0

Cb1

Cb2

Cb3

Cb4

Cb5

Cb6

Y6

Y7

Y8

Y9

Y1

Y2

Y3

Y4

Y5

NC

NC

NC

Y0

NC

NC

NC

NC

24-bit YC

Pixel #0

NC

NC

NC

NC

NC

Cr2

Cr3

Cr4

Cr5

Cr6

Y10

Y11

Cr0

Cr1

Y6

Y7

Y8

Y9

Y1

Y2

Y3

Y4

Y5

NC

NC

NC

Y0

NC

NC

NC

NC

Pixel #1

NC

NC

NC

NC

NC

Cr7

Cr8

Cr9

Cr10

Cr11

HSYNC

VSYNC

DE

© 2008-2016 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal . All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice.

SiI-DS-1032-A 51

SiI9233 HDMI Receiver with Repeater, Multi-channel Audio, and Deep Color Output

Data Sheet

Table 6.5. YC 4:2:2 (Pass Through Only) Separate Sync Pin Mapping

Y7

NC

NC

NC

NC

Cb0

Cb1

Cb2

Y2

Y3

Y4

Y5

Y6

NC

NC

Y0

Y1

NC

NC

NC

NC

NC

NC

NC

NC

NC

NC

NC

NC

16-bit YC

Pixel #0

NC

NC

Cb3

Cb4

Cb5

Cb6

Cb7

HSYNC

Q23

Q24

Q25

Q26

Q27

Q28

Q29

Q30

Q14

Q15

Q16

Q17

Q18

Q19

Q20

Q21

Q22

Q6

Q7

Q8

Q9

Q10

Q11

Q12

Q13

Q2

Q3

Q4

Q5

Pin

Name

Q0

Q1

Q31

Q32

Q33

Q34

Q35

HSYNC

Y9

NC

NC

NC

NC

Cb2

Cb3

Cb4

Y4

Y5

Y6

Y7

Y8

NC

NC

Y2

Y3

Y0

Y1

NC

NC

Cb0

Cb1

NC

NC

NC

NC

NC

NC

20-bit YC

Pixel #0

NC

NC

Cb5

Cb6

Cb7

Cb8

Cb9

HSYNC

NC

Cr0

Cr1

Cr2

Y7

NC

NC

NC

Y2

Y3

Y4

Y5

Y6

NC

NC

Y0

Y1

NC

NC

NC

NC

NC

NC

NC

NC

Pixel #1

NC

NC

NC

NC

NC

NC

Cr3

Cr4

Cr5

Cr6

Cr7

HSYNC

VSYNC

DE

VSYNC

DE

VSYNC

DE

VSYNC

DE

VSYNC

DE

VSYNC

DE

Note: This pin mapping is only valid when the input video format is YC 4:2:2 and the output video format is YC 4:2:2 also. No video processing block should be enabled when this pin mapping is used.

NC

Cr2

Cr3

Cr4

Y9

NC

NC

NC

Y4

Y5

Y6

Y7

Y8

NC

NC

Y2

Y3

Cr0

Cr1

NC

NC

Y0

Y1

NC

NC

Pixel #1

NC

NC

NC

NC

NC

NC

Cr5

Cr6

Cr7

Cr8

Cr9

HSYNC

Y11

NC

NC

NC

NC

Cb4

Cb5

Cb6

NC

NC

Y4

Y5

Y6

Y7

Y8

Y9

Y10

Y2

Y3

Cb0

Cb1

Cb2

Cb3

NC

NC

NC

NC

Y0

Y1

24-bit YC

Pixel #0

NC

NC

Cb7

Cb8

Cb9

Cb10

Cb11

HSYNC

NC

Cr4

Cr5

Cr6

Y11

NC

NC

NC

NC

NC

Y4

Y5

Y6

Y7

Y8

Y9

Y10

Cr7

Cr8

Cr9

Cr10

Cr11

HSYNC

VSYNC

DE

Cr2

Cr3

NC

NC

Y2

Y3

Cr0

Cr1

Pixel #1

NC

NC

NC

NC

Y0

Y1

© 2008-2016 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal . All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice.

52 SiI-DS-1032-A

SiI9233 HDMI Receiver with Repeater, Multi-channel Audio, and Deep Color Output

Data Sheet

Q[35:28] blank Pixel 0 Pixel 1 Pixel 2 Pixel 3 Pixel n-1 Pixel n val Cb0[11:4] Cr0[11:4] Cb2[11:4] Cr2[11:4] Cbn-1[11:4] Crn-1[11:4] val

Q[23:16]

Q[27:24]

Q[15:12] val val val

Y0[11:4] Y1[11:4] Y2[11:4] Y3[11:4] Yn-1[11:4] Yn[11:4]

Cb0[3:0] Cr0[3:0] Cb2[3:0] Cr2[3:0] Cbn-1[3:0] Crn-1 [3:0] val

Y0[3:0] Y1[3:0] Y2[3:0] Y3[3:0] Yn-1[3:0] Yn[3:0] val val val val val val

ODCK

DE

HSYNC,

VSYNC

Figure 6.6. YC Timing Diagram

Note: The val data is defined in various specifications to specific values. These values are controlled by setting the appropriate SiI9233 registers, because no pixel data is carried on HDMI during blanking.

© 2008-2016 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal . All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice.

SiI-DS-1032-A 53

SiI9233 HDMI Receiver with Repeater, Multi-channel Audio, and Deep Color Output

Data Sheet

6.2.3.

YC 4:2:2 Formats with Embedded Syncs

The YC 4:2:2 embedded sync format is identical to the previous format (YC 4:2:2), except that the syncs are embedded and

not separate. Pixel data can be 24-bit, 20-bit or 16-bit. DE is always output. Figure 6.7

shows the Start of Active Video

(SAV) preamble, the End of Active Video” (EAV) suffix, and shows timings with OCLKDIV = 0 and OCKINV = 1.

Table 6.6. YC 4:2:2 Embedded Sync Pin Mappings

Q23

Q24

Q25

Q26

Q27

Q28

Q29

Q30

Q31

Q15

Q16

Q17

Q18

Q19

Q20

Q21

Q22

Q32

Q33

Q34

Q35

HSYNC

VSYNC

DE

Q6

Q7

Q8

Q9

Q10

Q11

Q12

Q13

Q14

Q2

Q3

Q4

Q5

Pin

Name

Q0

Q1

Y7

NC

NC

NC

NC

Cb0

Cb1

Cb2

Cb3

Y3

Y4

Y5

Y6

NC

Y0

Y1

Y2

NC

NC

NC

NC

NC

NC

NC

NC

NC

NC

NC

NC

NC

16-bit YC

Pixel #0

NC

NC

Cb4

Cb5

Cb6

Cb7

Embedded

Embedded

Embedded

Cr0

Cr1

Cr2

Cr3

Y7

NC

NC

NC

NC

Y3

Y4

Y5

Y6

NC

Y0

Y1

Y2

NC

NC

NC

NC

NC

NC

NC

NC

NC

Pixel #1

NC

NC

NC

NC

NC

NC

Cr4

Cr5

Cr6

Cr7

Embedded

Embedded

Embedded

Y9

NC

NC

Cb0

Cb1

Cb2

Cb3

Cb4

Cb5

Y5

Y6

Y7

Y8

Y1

Y2

Y3

Y4

NC

NC

NC

NC

Y0

NC

NC

NC

NC

NC

NC

NC

NC

20-bit YC

Pixel #0

NC

NC

Cb6

Cb7

Cb8

Cb9

Embedded

Embedded

Embedded

Cr2

Cr3

Cr4

Cr5

Y9

NC

NC

Cr0

Cr1

Y5

Y6

Y7

Y8

Y1

Y2

Y3

Y4

NC

NC

NC

NC

Y0

NC

NC

NC

NC

Pixel #1

NC

NC

NC

NC

NC

NC

Cr6

Cr7

Cr8

Cr9

Embedded

Embedded

Embedded

Y11

Cb0

Cb1

Cb2

Cb3

Cb4

Cb5

Cb6

Cb7

Y3

Y4

Y5

Y6

Y7

Y8

Y9

Y10

NC

NC

Y0

Y1

Y2

NC

NC

NC

NC

NC

NC

NC

NC

24-bit YC

Pixel #0

NC

NC

Cb8

Cb9

Cb10

Cb11

Embedded

Embedded

Embedded

Cr4

Cr5

Cr6

Cr7

Y11

Cr0

Cr1

Cr2

Cr3

Y3

Y4

Y5

Y6

Y7

Y8

Y9

Y10

NC

NC

Y0

Y1

Y2

NC

NC

NC

NC

Pixel #1

NC

NC

NC

NC

NC

NC

Cr8

Cr9

Cr10

Cr11

Embedded

Embedded

Embedded

© 2008-2016 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal . All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice.

54 SiI-DS-1032-A

SiI9233 HDMI Receiver with Repeater, Multi-channel Audio, and Deep Color Output

Data Sheet

Table 6.7. YC 4:2:2 (Pass Through Only) Embedded Sync Pin Mapping

Y7

NC

NC

NC

NC

Cb0

Cb1

Cb2

Y2

Y3

Y4

Y5

Y6

NC

NC

Y0

Y1

NC

NC

NC

NC

NC

NC

NC

NC

NC

NC

NC

NC

16-bit YC

Pixel #0

NC

NC

Q23

Q24

Q25

Q26

Q27

Q28

Q29

Q30

Q14

Q15

Q16

Q17

Q18

Q19

Q20

Q21

Q22

Q6

Q7

Q8

Q9

Q10

Q11

Q12

Q13

Q2

Q3

Q4

Q5

Pin

Name

Q0

Q1

Pixel #1

NC

NC

NC

NC

NC

NC

NC

NC

NC

NC

NC

NC

NC

NC

NC

NC

Y0

Y1

Y2

Y3

Y4

Y5

Y6

Y7

NC

NC

NC

NC

Cr0

Cr1

Cr2

20-bit YC

Pixel #0

NC

NC

NC

NC

NC

NC

Y0

Y1

NC

NC

Cb0

Cb1

NC

NC

NC

NC

Y2

Y3

Y4

Y5

Y6

Y7

Y8

Y9

NC

NC

NC

NC

Cb2

Cb3

Cb4

Q31

Q32

Q33

Q34

Q35

HSYNC

Cb3

Cb4

Cb5

Cb6

Cb7

Embedded

Cr3

Cr4

Cr5

Cr6

Cr7

Embedded

Cb5

Cb6

Cb7

Cb8

Cb9

Embedded

Cr5

Cr6

Cr7

Cr8

Cr9

Embedded

Cb7

Cb8

Cb9

Cb10

Cb11

Embedded

VSYNC

DE

Embedded

Embedded

Embedded

Embedded

Embedded

Embedded

Embedded

Embedded

Embedded

Embedded

Note: This pin mapping is only valid when the input video format is YC 4:2:2 and the output video format is YC 4:2:2 also. No video processing block should be enabled when this pin mapping is used.

NC

Cr2

Cr3

Cr4

Y9

NC

NC

NC

Y4

Y5

Y6

Y7

Y8

NC

NC

Y2

Y3

Cr0

Cr1

NC

NC

Y0

Y1

NC

NC

Pixel #1

NC

NC

NC

NC

NC

NC

Y11

NC

NC

NC

NC

Cb4

Cb5

Cb6

NC

NC

Y4

Y5

Y6

Y7

Y8

Y9

Y10

Y2

Y3

Cb0

Cb1

Cb2

Cb3

NC

NC

NC

NC

Y0

Y1

24-bit YC

Pixel #0

NC

NC

NC

Cr4

Cr5

Cr6

Y11

NC

NC

NC

NC

NC

Y4

Y5

Y6

Y7

Y8

Y9

Y10

Cr2

Cr3

NC

NC

Y2

Y3

Cr0

Cr1

Pixel #1

NC

NC

NC

NC

Y0

Y1

Cr7

Cr8

Cr9

Cr10

Cr11

Embedded

Embedded

Embedded

© 2008-2016 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal . All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice.

SiI-DS-1032-A 55

SiI9233 HDMI Receiver with Repeater, Multi-channel Audio, and Deep Color Output

Data Sheet

Q[35:28]

Q[23:16]

Q[27:24]

Q[15:12]

ODCK

Active

Video val val val val

X

X

FF

FF

X

X

00

00

SAV

X

X

00

00

XY

Pixel0 Pixel1 Pixel2 Pixel3 Pixel n-1 Pixel n

Cb0[11:4] Cr0[11:4] Cb2[11:4] Cr2[11:4] Cbn-1[11:4] Crn-1[ 11:4] FF

X

X

XY Y0[11: 4] Y1[ 11: 4] Y2[11: 4] Y3[ 11:4] Yn-1[11:4] Yn[ 11:4]

Cb0[3: 0] Cr0[3:0] Cb2[3: 0] Cr2[3:0] Cbn-1[3:0] Crn-1[3:0]

FF

X

Y0[ 3:0] Y1[ 3:0] Y2[3:0] Y3[ 3:0] Yn-1[3: 0] Yn[3:0]

X

00

X

00

EAV

00

00

X

X X

XY

XY

X

X val val val val

Figure 6.7. YC 4:2:2 Embedded Sync Timing Diagram

Note: The val data is defined in various specifications to specific values. These values are controlled by setting the appropriate SiI9233 registers, because no pixel data is carried on HDMI during blanking. SAV/EAV codes appear as an 8bit field on both Q[35:28] (per SMPTE) and Q[23:16].

© 2008-2016 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal . All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice.

56 SiI-DS-1032-A

SiI9233 HDMI Receiver with Repeater, Multi-channel Audio, and Deep Color Output

Data Sheet

6.2.4.

YC Mux (4:2:2) Formats with Separate Syncs

The video data is multiplexed onto fewer pins than the mapping in Table 6.8

, but complete luminance (Y) and

chrominance (Cb and Cr) data is still provided for each pixel because the output pixel clock runs at twice the pixel rate.

Figure 6.8 shows the 24-bit mode. The 16- and 20-bit mappings use fewer output pins for the pixel data. Note the separate syncs. Figure 6.8

shows OCLKDIV = 0 and OCKINV = 1.

Table 6.8. YC Mux 4:2:2 Mappings

Pin

Name

8-bit

YCbCr

Q26

Q27

Q28

Q29

Q30

Q31

Q32

Q33

Q34

Q35

Q18

Q19

Q20

Q21

Q22

Q23

Q24

Q25

HSYNC

VSYNC

DE

Q9

Q10

Q11

Q12

Q13

Q14

Q15

Q16

Q17

Q5

Q6

Q7

Q8

Q0

Q1

Q2

Q3

Q4

NC

NC

NC

NC

NC

NC

NC

NC

NC

NC

D6

D7

NC

NC

D2

D3

D4

D5

HSYNC

VSYNC

DE

NC

NC

NC

D0

D1

NC

NC

NC

NC

NC

NC

NC

NC

NC

NC

NC

NC

NC

NC

NC

NC

NC

NC

D8

D9

NC

NC

D4

D5

D6

D7

NC

D0

D1

D2

D3

NC

NC

NC

NC

NC

NC

NC

NC

10-bit

YCbCr

NC

NC

NC

NC

NC

NC

NC

NC

NC

NC

HSYNC

VSYNC

DE

NC

NC

NC

NC

NC

D10

D11

NC

NC

D6

D7

D8

D9

D1

D2

D3

D4

D5

NC

NC

NC

D0

NC

NC

NC

NC

12-bit

YCbCr

NC

NC

NC

NC

NC

NC

NC

NC

NC

NC

HSYNC

VSYNC

DE

© 2008-2016 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal . All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice.

SiI-DS-1032-A 57

SiI9233 HDMI Receiver with Repeater, Multi-channel Audio, and Deep Color Output

Data Sheet

Pixel 0 Pixel 1

Q[35:24]

Q[11:0]

Q[23:16]

X val

X val

X val

X val

X val

X X X X X

Pixel 2

X X

Pixel 3

X

Cb0[11:4] Y0[11:4] Cr0[11:4] Y1[11:4] Cb2[11:4] Y2[11:4] Cr2[11:4] Y3[11:4]

Q[15:12] val val val val val

Cb0[3:0]

Y0[3:0]

Cr0[3:0]

Y1[3:0] Cb2[3:0] Y2[3:0] Cr2[3:0] Y3[3:0]

ODCK

DE

HSYNC

VSYNC

Figure 6.8. YC Mux 4:2:2 Timing Diagram

Note: The val data is defined in various specifications to specific values. These values are controlled by setting the appropriate SiI9233 registers, because no pixel data is carried on HDMI during blanking.

© 2008-2016 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal . All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice.

58 SiI-DS-1032-A

SiI9233 HDMI Receiver with Repeater, Multi-channel Audio, and Deep Color Output

Data Sheet

6.2.5.

YC Mux 4:2:2 Formats with Embedded Syncs

This mode is similar to that on page 57, but with embedded syncs. It is similar to YC 4:2:2 with embedded syncs, but

also multiplexes the luminance (Y) and chrominance (Cb and Cr) onto the same pins on alternating pixel clock cycles.

Normally this mode is used only for 480i, 480p, 576i and 576p modes. Output clock rate is half the pixel clock rate on the link. SAV code is shown before rise of DE. EAV follows the falling edge of DE. See the ITU-R BT.656 Specification.

480p, 54-MHz output can be achieved if the input differential clock is 54 MHz. Figure 6.9

shows OCLKDIV = 0 and

OCKINV = 1.

Table 6.9. YC Mux 4:2:2 Embedded Sync Pin Mapping

Q21

Q22

Q23

Q24

Q25

Q26

Q27

Q28

Q29

Q13

Q14

Q15

Q16

Q17

Q18

Q19

Q20

Q30

Q31

Q32

Q33

Q34

Q35

HSYNC

VSYNC

DE

Q4

Q5

Q6

Q7

Q8

Q9

Q10

Q11

Q12

Pin

Name

Q0

Q1

Q2

Q3

NC

NC

NC

NC

D5

D6

D7

NC

NC

D1

D2

D3

D4

NC

NC

NC

D0

NC

NC

NC

NC

NC

NC

NC

NC

NC

8-bit

YCbCr

NC

NC

NC

NC

NC

NC

NC

NC

NC

NC

Embedded

Embedded

Embedded

NC

NC

NC

NC

D7

D8

D9

NC

NC

D3

D4

D5

D6

NC

D0

D1

D2

NC

NC

NC

NC

NC

NC

NC

NC

NC

10-bit

YCbCr

NC

NC

NC

NC

NC

NC

NC

NC

NC

NC

Embedded

Embedded

Embedded

NC

NC

NC

NC

D9

D10

D11

NC

NC

D5

D6

D7

D8

D1

D2

D3

D4

NC

NC

NC

NC

D0

NC

NC

NC

NC

12-bit

YCbCr

NC

NC

NC

NC

NC

NC

NC

NC

NC

NC

Embedded

Embedded

Embedded

© 2008-2016 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal . All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice.

SiI-DS-1032-A 59

SiI9233 HDMI Receiver with Repeater, Multi-channel Audio, and Deep Color Output

Data Sheet

Q[35:24]

Q[11:0]

Q[23:16] val val

X

FF

X

SAV

X

00 00

X X

Pixel0

X X

Pixel1

X X

Pixel2

X X

Pixel3

X

XY Cb0[ 11:4] Y0[11:4] Cr0[11:4] Y1[11:4] Cb2[11:4] Y2[11:4] Cr2[11:4] Y3[11:4]

Q[15:12]

ODCK

Active

Video val X X X X

Cb0[3:0] Y0[3:0]

Cr0[3:0] Y1[3:0] Cb2[3:0] Y2[3:0] Cr2[3:0] Y3[3:0]

Figure 6.9. YC Mux 4:2:2 Embedded Sync Encoding Timing Diagram

Note: The val data is defined in various specifications to specific values. These values are controlled by setting the appropriate SiI9233 registers, because no pixel data is carried on HDMI during blanking. Refer to the

SiI9223/9233/9127 HDMI Receivers Programmer’s Reference (SiI-PR-1019) for details.

© 2008-2016 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal . All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice.

60 SiI-DS-1032-A

SiI9233 HDMI Receiver with Repeater, Multi-channel Audio, and Deep Color Output

Data Sheet

6.2.6.

12/15/18-Bit RGB and YCbCr 4:4:4 Formats with Separate Syncs

The output clock runs at the pixel rate and a complete definition of each pixel is output on each clock. One clock edge drives out half the pixel data on 12/15/18 pins. The opposite clock edge drives out the remaining half of the pixel data

on the same 12/15/18 pins. Figure 6.10

shows RGB data. The same timing format is used for YCbCr 4:4:4 as listed in the columns of Table 6.10

. Control signals (DE, HSYNC and VSYNC) change state with respect to the first edge of ODCK.

Table 6.10. 12/15/18-Bit Output 4:4:4 Mappings

24-bit

Pin RGB

Name

First

Edge

Second

Edge

YCbCr

First

Edge

Second

Edge

30-bit

RGB

First

Edge

Second

Edge

YCbCr

First

Edge

Second

Edge

36-bit

RGB

First

Edge

Second

Edge

YCbCr

First

Edge

Second

Edge

Q8

Q9

Q10

Q11

Q12

Q13

Q14

Q15

Q16

Q17

Q4

Q5

Q6

Q7

Q0

Q1

Q2

Q3

NC

NC

NC

NC

NC

NC

B0

B1

B2

B3

B4

B5

B6

B7

G0

G1

G2

G3

NC

NC

NC

NC

NC

NC

G4

G5

G6

G7

R0

R1

R2

R3

R4

R5

R6

R7

NC

NC

NC

NC

NC

NC

Cb0

Cb1

Cb2

Cb3

Cb4

Cb5

Cb6

Cb7

Y0

Y1

Y2

Y3

NC

NC

NC

NC

NC

NC

Y4

Y5

Y6

Y7

Cr0

Cr1

Cr2

Cr3

Cr4

Cr5

Cr6

Cr7

NC

NC

NC

B0

B1

B2

B3

B4

B5

B6

B7

B8

B9

G0

G1

G2

G3

G4

NC

NC

NC

G5

G6

G7

G8

G9

R0

R1

R2

R3

R4

R5

R6

R7

R8

R9

NC

NC

NC

Cb0

Cb1

Cb2

Cb3

Cb4

Cb5

Cb6

Cb7

Cb8

Cb9

Y0

Y1

Y2

Y3

Y4

NC

NC

NC

Y5

Y6

Y7

Y8

Y9

Cr0

Cr1

Cr2

Cr3

Cr4

Cr5

Cr6

Cr7

Cr8

Cr9

B0

B1

B2

B3

B4

B5

B6

B7

B8

B9

B10

B11

G0

G1

G2

G3

G4

G5

G6

G7

G8

G9

G10

G11

R0

R1

R2

R3

R4

R5

R6

R7

R8

R9

R10

R11

Cb0

Cb1

Cb2

Cb3

Cb4

Cb5

Cb6

Cb7

Cb8

Cb9

Cb10

Cb11

Y0

Y1

Y2

Y3

Y4

Y5

Y6

Y7

Y8

Y9

Y10

Y11

Cr0

Cr1

HSYNC HSYNC HSYNC HSYNC HSYNC HSYNC HSYNC HSYNC HSYNC HSYNC HSYNC HSYNC HSYNC

VSYNC VSYNC VSYNC VSYNC VSYNC VSYNC VSYNC VSYNC VSYNC VSYNC VSYNC VSYNC VSYNC

DE DE DE DE DE DE DE DE DE DE DE DE DE

Cr6

Cr7

Cr8

Cr9

Cr2

Cr3

Cr4

Cr5

Cr10

Cr11 blank Pixel 0 Pixel 1 Pixel 2 Pixel 3 blank blank blank

Q[17:12] val G0[5:0] R0[11:6] G1[5:0] R1[11:6] G2[5:0] R2[11:6] G3[5:0] R3[11:6] val val val val val val

Q[11:6]

Q[5:0]

ODCK

DE

HSYNC,

VSYNC val val

B0[11:6] R0[5:0] B1[11:6] R1[5:0] B2[11:6] R2[5:0] B3[11:6] R3[5:0]

B0[5:0] G0[11:6] B1[5:0] G1[11:6] B2[5:0] G2[11:6] B3[5:0] G3[11:6] val val val val val val val val val val val val

Figure 6.10. 18-Bit Output 4:4:4 Timing Diagram

© 2008-2016 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal . All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice.

SiI-DS-1032-A 61

SiI9233 HDMI Receiver with Repeater, Multi-channel Audio, and Deep Color Output

Data Sheet

Q[17:13] blank val

Pixel 0

G0[4:0] R0[9:5]

Pixel 1

G1[4:0] R1[9:5]

Pixel 2

G2[4:0] R2[9:5]

Pixel 3

G3[4:0] R3[9:5]

Q[12:8] val B0[9:5] R0[4:0] B1[9:5] R1[4:0] B2[9:5] R2[4:0] B3[9:5] R3[4:0]

Q[7:3]

ODCK

DE

HSYNC,

VSYNC val B0[4:0] G0[9:5] B1[4:0] G1[9:5] B2[4:0] G2[9:5] B3[4:0] G3[9:5] val blank val val val val val

Figure 6.11. 15-Bit Output 4:4:4 Timing Diagram

val val val blank val val val

Q[17:14] blank val

Pixel 0

G0[3:0] R0[7:4]

Pixel 1

G1[3:0] R1[7:4]

Pixel 2

G2[3:0] R2[7:4]

Pixel 3

G3[3:0] R3[7:4]

Q[13:10] val B0[7:4] R0[3:0] B1[7:4] R1[3:0] B2[7:4] R2[3:0] B3[7:4] R3[3:0]

Q[9:6]

ODCK

DE

HSYNC,

VSYNC val B0[3:0] G0[7:4] B1[3:0] G1[7:4] B2[3:0] G2[7:4] B3[3:0] G3[7:4] val blank val val val val val

Figure 6.12. 12-Bit Output 4:4:4 Timing Diagram

val val val blank val val val val val val blank val val val val val val blank val val val

© 2008-2016 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal . All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice.

62 SiI-DS-1032-A

7. I

2

C Interfaces

SiI9233 HDMI Receiver with Repeater, Multi-channel Audio, and Deep Color Output

Data Sheet

7.1.

HDCP E-DDC / I

2

C Interface

The HDCP protocol requires values to be exchanged between the video transmitter and video receiver. These values are exchanged over the DDC channel of the DVI interface. The E-DDC channel follows the I

2

C serial protocol. In a system design using an SiI9233 receiver, the SiI9233 device is the video Receiver and has a connection to the E-DDC bus with a slave address of 0x74 The I

2

C read operation is shown in Figure 7.1

, and the write operation in Figure 7.2

.

Bus Activity :

Master

Slave Address Register Address Slave Address

DSDA Line S S

A

C

K

A

C

K

Figure 7.1. I

2

C Byte Read

A

C

K

Data

No

A

C

K

P

Bus Activity :

Master

Slave Address Register Address Data

DSDA Line S P

A

C

K

Figure 7.2. I

2

C Byte Write

A

C

K

A

C

K

Multiple bytes can be transferred in each transaction, regardless of whether they are reads or writes. The operations

are similar to those in Figure 7.1

and Figure 7.2

except that there is more than one data phase. An ACK follow each byte

except the last byte in a read operation. Byte addresses increment, with the least significant byte transferred first, and the most significant byte last. See the I

2

C specification for more information.

There is also a “Short Read” format, designed to improve the efficiency of Ri register reads (which must be done every

two seconds while encryption is enabled). This transaction is shown in Figure 7.3

. Note that there is no register address

phase (only the slave address phase), because the register address is reset to 0x08 (Ri) after a hardware or software reset, and after the STOP condition on any preceding I

2

C transaction.

Ri Lsb Ri Msb

Bus Activity:

Master

DSDA Line

S

Slave Address

A

C

K

A

C

K

No

A

C

K

P

Figure 7.3. Short Read Sequence

© 2008-2016 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal . All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice.

SiI-DS-1032-A 63

SiI9233 HDMI Receiver with Repeater, Multi-channel Audio, and Deep Color Output

Data Sheet

7.2.

Local I

2

C Interface

The SiI9233 HDMI Receiver has a second I

2

C port accessible only to the controller in the display device. It is separate from the E-DDC bus. The HDMI Receiver is a slave device that responds to six binary I

2

C device addresses of seven bits each. This I

2

C interface only supports the read operation in Figure 7.1

, and the write operation in Figure 7.2

. It does not support the short read operation shown in Figure 7.3

. Note that the I

2

C data pin for the local I

2

C bus is CSDA, instead of the DSDA pin shown in these figures.

The local I

2

C interface on the SiI9233 receiver (pins CSCL and CSDA) is a slave interface that can run up to 400 kHz. This bus is used to configure and control the SiI9233 receiver by reading/writing to necessary registers.

The local I

2

C interface of the SiI9233 receiver consists of 6 separate I

2

C slave addresses. The SiI223 receiver will therefore appear as 6 separate devices on the I

2

C local bus. The first two of these addresses, used for HDMI Control and general low level register control, are fixed, and can only be set to one of two values by using the CI2CA pin. The other 3 addresses (used for CEC, EDID, and x.v.Color) have an I

2

C register programmable address mapped into the

HDMI Control register space, so the default value can be changed if there is a bus conflict with another device.

Table 7.1. Control of the Default I

2

C Addresses with the CI2CA Pin

HDMI Control and low level registers

(fixed)

X.V.Color Registers (programmable)

EDID Registers (programmable)

CEC Registers (programmable)

CI2CA=LOW

0x60 & 0x68

0x64

0xE0

0xC0

Ci2CA=HIGH

0x62 & 0x6A

0xE4

0xC4

The HDMI Control and low level registers are fixed after reset based on CI2CA pin and cannot be changed. The I

2

C slave address for the x.v.Color registers, EDID Control registers, and the CEC Control registers each have a register associated with them that allows the address to be changed. See the SiI9223/9233/9127 HDMI Receivers Programmer’s

Reference (SiI-PR-1019) for more information.

7.3.

Video Requirement for I

2

C Access

The SiI9233 receiver does not require an active video clock to access its registers from either the E-DDC port or the local I

2

C port. Read-Write registers can be written and then read back. Read-only registers that provide values for an active video or audio stream return indeterminate values if there is no video clock and no active syncs.

Use the SCDT and CKDT register bits to determine when active video is being received by the chip.

7.4.

I

2

C Registers

The register values that are exchanged over the HDMI DDC I

2

C serial interface with the SiI9233 for HDCP are described in the HDCP 1.0 Specification (February 2000) in Section 2.6 – HDCP Port. Refer to the SiI9223/9233/9127 HDMI

Receivers Programmer’s Reference (SiI-PR-1019) for details on these and all other SiI9233 registers.

© 2008-2016 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal . All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice.

64 SiI-DS-1032-A

SiI9233 HDMI Receiver with Repeater, Multi-channel Audio, and Deep Color Output

Data Sheet

8. Hot Plug Detect CTS Requirement

To comply with with HDMI Compliance Test Specification Test ID 8-11, HPD Output Resistance, the circuit shown in

Figure 8.1

must be added to each SiISiI9233 input port that is used in the design.

SiI9233

RnPWR5V

4.7 k

1 k

18

+5V

HDMI connector

Port n

19

HPD

MMBT3904

HPDn

10 k

MMBT3904

Figure 8.1: HPD CTS Compliance Requirement Schematic

© 2008-2016 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal . All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice.

SiI-DS-1032-A 65

SiI9233 HDMI Receiver with Repeater, Multi-channel Audio, and Deep Color Output

Data Sheet

9. Design Recommendations

The following information is provided as recommendations that are based on the experience of Lattice Semiconductor engineers and customers. If you choose to deviate from these recommendations for a particular application, Lattice

Semiconductor strongly suggests that you contact one of its technical representatives for an evaluation of the change.

9.1.

Power Control

The low-power standby state feature of the SiI9233 receiver provides a design option of leaving the chip always powered, as opposed to powering it on and off. Leaving the chip powered and using the PD# register bit to put it in a lower power state can result in faster system response time, depending on the system Vcc supply ramp-up delay.

9.1.1.

Power Pin Current Demands

The limits shown in Table 9.1

indicate the current demanded by each group of power pins on the SiI9233 device. These

limits were characterized at maximum VCC, 0 °C ambient temperature and for fast-fast silicon. Actual application current demands can be lower than these figures, and varies with video resolution and audio clock frequency.

Table 9.1. Maximum Power Domain Currents versus Video Mode

Mode ODCK (MHz)

480p 27.0

1080i 74.25

1080p 148.5

[email protected]

1

225

3.3V Power Domain Currents (mA)

IOVCC33 AVCC33 XTALVCC33

39 51 7

100

182

252

51

51

51

7

7

7

Mode

480p

ODCK (MHz)

27.0

1.2V Power Domain Currents (mA)

AVCC12

36

CVCC12

52

APVCC12

5

1080i 74.25

1080p 148.5

[email protected]

1

225

54

84

129

127

253

343

5

5

5

Notes:

1. Measured with 12-bits/pixel video data.

2. Measured with 192 kHz, 8-channel audio, except for 480p mode which used 48 kHz, 8-channel audio.

3. Measured with RGB input, vertical black-white/1-pixel stripe (Moire2) pattern, converting to YCbCr output (digital for

IOVCC33).

4. Only one core can be selected at a time. The TMDSxSEL register bit turns off the unselected core, except for the termination to AVCC33.

AVCC33 current includes 40 mA for the unselected TMDS core. Only 5 mA of this current is dissipated as power in the

HDMI Receiver; the remainder is dissipated in the HDMI transmitter. The AVCC33 current on the unselected core can be reduced to 5 mA by asserting the corresponding PD_TERMx# register bit.

© 2008-2016 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal . All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice.

66 SiI-DS-1032-A

SiI9233 HDMI Receiver with Repeater, Multi-channel Audio, and Deep Color Output

Data Sheet

9.2.

HDMI Receiver DDC Bus Protection

The I

2

C pins on the VESA DDC Specification (available at www.vesa.org

) defines the DDC interconnect bus to be a 5-V signaling path. The I

2

C pins on the HDMI Receiver chip are 5-V tolerant. And these pins are true open-drain I/O. The

pull-up resistors on the DDC bus should be pulled up using the 5-V supply from the HDMI connector. Refer to Figure 9.9

on page 74 .

9.3.

Decoupling Capacitors

Designers should include decoupling and bypass capacitors at each power pin in the layout. These are shown

schematically in Figure 9.4

on page 71 . Place these components as closely as possible to the SiI9233 pins and avoid

routing through vias. Figure 9.1

shows the various types of power pins on the HDMI Receiver.

VCC

C1 C2

L1

VCC

Ferrite

GND

C3

Via to GND

Figure 9.1. Decoupling and Bypass Capacitor Placement

9.4.

ESD Protection

The HDMI Receiver chip is designed to withstand electrostatic discharge to 2 kV. In applications where higher protection levels are required, ESD limiting components can be placed on the differential lines coming into the chip.

These components typically have a capacitive effect, reducing the signal quality at higher clock frequencies on the link.

Use of the lowest capacitance devices is suggested; in no case should the capacitance value exceed 5 pF.

Series resistors can be included on the TMDS lines (see Figure 9.9

on page 74 ) to counteract the impedance effects of

ESD protection diodes. The diodes typically lower the impedance because of their capacitance. The resistors raise the impedance to stay within the HDMI specification centered on a 100-Ω differential.

© 2008-2016 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal . All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice.

SiI-DS-1032-A 67

SiI9233 HDMI Receiver with Repeater, Multi-channel Audio, and Deep Color Output

Data Sheet

9.5.

HDMI Receiver Layout

The HDMI Receiver chip should be placed as closely as possible to the input connectors that carry the TMDS signals. For a system using industry-standard HDMI connectors (see www.hdmi.org

), the differential lines should be routed as directly as possible from connector to HDMI Receiver. Lattice Semiconductor HDMI receivers are tolerant of skews between differential pairs, so spiral skew compensation for path length differences is not required. Each differential pair should be routed together, minimizing the number of vias through which the signal lines are routed. The distance separating the two traces of the differential pair should be kept to a minimum.

In order to achieve the optimal input TMDS signal quality, please follow the layout guidelines below:

1. Lay out all differential pairs with controlled impedance of 100

differential.

2. Cut out all copper planes (ground and power) that are less than 45 mils underneath the TMDS traces near the HDMI receiver with dimensions as shown below.

0.3 inch

> 0.1 inch

HDMI Receiver

> 0.1 inch

Ground and Power plane cut-out for copper planes <45 mil separation from TMDS traces

Figure 9.2. Cut-out Reference Plane Dimensions

3. If ESD suppression devices or common mode chokes are used, place them near the HDMI connector, away from the HDMI Receiver IC. Do not place them over the ground and power plane cutout near the HDMI receiver.

© 2008-2016 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal . All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice.

68 SiI-DS-1032-A

SiI9233 HDMI Receiver with Repeater, Multi-channel Audio, and Deep Color Output

Data Sheet

DDC#0 DDC#1

+5V

PIN 19

PIN 1

HDMI Port

#0

Connector

HDMI Port

#1

Connector

PIN 19 text text text

10 text text text text text text text text text text text text text text

19

+5V

DDC#1

R1PWR5V

R0PWR5V text text text text text text text text text text text text text text text text text text text text text text text text text text text text text text text text text text text text

SiI9233 text

10 text text text text text text text text text

19 text text text text text text text

PIN 1

Drawing is not to exact scale. Refer to

HDMI connector specification for exact dimensions.

Figure 9.3. HDMI to Receiver Routing – Top View

Note the sixteen TMDS traces connected directly from the HDMI connectors (left) to the pins on the SiI9233 receiver

(right). Trace impedance should be 100

differential in each pair and 50

single-ended if possible. Trace width and pitch depends on the PCB construction. Not all connections are shown — the drawing demonstrates routing of TMDS

lines without crossovers, vias, or ESD protection. Refer also to Figure 9.9

.

9.6.

EMI Considerations

Electromagnetic interference is a function of board layout, shielding, HDMI Receiver component operating voltage, and frequency of operation, among other factors. When attempting to control emissions, do not place any passive components on the differential signal lines (aside from any essential ESD protection as described earlier). The differential signaling used in HDMI is inherently low in EMI as long as the routing recommendations noted in the

Receiver Layout section are followed.

The PCB ground plane should extend unbroken under as much of the HDMI Receiver chip and associated circuitry as possible, with all ground pins of the chip using a common ground.

© 2008-2016 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal . All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice.

SiI-DS-1032-A 69

SiI9233 HDMI Receiver with Repeater, Multi-channel Audio, and Deep Color Output

Data Sheet

9.7.

XTALIN Clock Required in All Designs

9.7.1.

Description

The SiI9233 receiver uses the clock at the XTALIN/XTALOUT pin pair to control the internal audio pipeline. This clock is also used to control the interrupt processing, the internal reading of HDCP keys and internal CEC timing calibration.

The XTALIN/XTALOUT pin pair must be driven with a clock in all applications, even when the design does not support audio processing. The clock frequency must be 27.000 MHz.

9.7.2.

Recommendation

For designs that do not support audio, the XTALIN pin can be connected to an ordinary 27-MHz LVTTL clock source, which is commonly available on HDMI sink designs. There is no requirement that this clock source be low jitter. The

XTALOUT pin can be left unconnected when XTALIN is driven with a LVTTL clock.

9.8.

Typical Circuit

Representative circuits for application of the SiI9233 HDMI Receiver chip are shown in Figure 9.4

through Figure 9.8

.

For a detailed review of your intended circuit implementation, contact your Lattice Semiconductor representative.

9.8.1.

Power Supply Decoupling

AVCC_3. 3V

Ferrite

220 @100MHz

AVCC33

+3.3V

0.1uF

10uF

0.1uF

0 .1uF

0.1uF

1nF 1nF

1nF

Place ceramic capacitors close to VCC pins .

GND

IOVCC33

+1. 2V

10uF 10uF

0. 1uF

0. 1uF

0.1uF

0.1uF

1nF 1nF 1nF 1nF 1nF

1nF

1nF

GND

Place ceramic capacitors close to VCC pins .

CVCC 12

10uF 10uF 0. 1uF 0. 1uF 0.1uF

0.1uF

1nF 1nF 1nF 1nF 1nF 1nF 1nF

GND

SiI9233

+1.2V

0.56

1%

Ferrite

0. 82uH, 150 mA

AVCC12

10uF

0.1uF

0. 1uF 0.1uF

1nF

+1.2V

1nF

Ferrite

[email protected] MHz

1nF

AGND

APVCC12

+3.3V

Ferrite

[email protected] MHz

XTALVCC33

+5V

SBVCC 5

Figure 9.4. Power Supply Decoupling and PLL Filtering Schematic

© 2008-2016 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal . All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice.

70 SiI-DS-1032-A

SiI9233 HDMI Receiver with Repeater, Multi-channel Audio, and Deep Color Output

Data Sheet

The ferrite on AVCC33 attenuates noise above 10 kHz. A parasitic resistor helps to minimize the peaking. An example device (surface mount, 0805 package) is part number MLF2012DR82 from TDK. A data sheet is available at www.tdk.co.jp

9.8.2.

HDMI Port Connections

RX2+ n

RX2- n

RX1+ n

RX1- n

RX0+ n

RX0- n

RXC+ n

RXC- n

HDMI

Connector

Port n

CEC n

HPD n

+5V n

47 k

47 k

See the Hot Plug Detect CEC

Requirement section for

important information.

RnX2+

RnX2-

RnX1+

RnX1-

RnX0+

RnX0-

RnXC+

RnXC-

CEC_A

HPDn

SiI9233

SCL n DSCLn

SDA n DSDAn

Figure 9.5. HDMI Port Connections Schematic

Note: Repeat the schematic for each HDMI input port on the SiI9233 receiver.

© 2008-2016 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal . All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice.

SiI-DS-1032-A 71

SiI9233 HDMI Receiver with Repeater, Multi-channel Audio, and Deep Color Output

Data Sheet

9.8.3.

Digital Video Output Connections

SiI9233

INT

102

DE

HSYNC

VSYNC

ODCK

Q 0

Q 1

Q 2

Q 3

Q 8

Q 9

Q10

Q11

Q 4

Q 5

Q 6

Q 7

19

9

8

7

3

2

1

144

15

14

13

10

20

21

5

16

Q17

Q18

Q19

Q20

Q21

Q22

Q23

Q12

Q13

Q14

Q15

Q16

135

134

133

132

141

140

139

138

129

128

127

126

123

122

121

120

117

116

115

114

111

110

109

108

Q24

Q25

Q26

Q27

Q28

Q29

Q30

Q31

Q32

Q33

Q34

Q35

33

33

33

33

33

33

33

33

33

Micro

33

Figure 9.6. Digital Display Schematic

The 3.3V to the level-shifters and pull-up resistors should be powered-down whenever the 3.3 V is powered-down on the HDMI Receiver itself.

The HDMI Receiver’s INT output can be connected as an interrupt to the microcontroller, or the microcontroller can poll register 0x70 (INTR_STATE) to determine if any of the enabled interrupts have occurred. Refer to the

SiI9223/9233/9127 HDMI Receivers Programmer’s Reference (SiI-PR-1019) for details. The HDMI Receiver’s VSYNC output can be connected to the micro if it is necessary to monitor the vertical refresh rate of the incoming video.

© 2008-2016 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal . All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice.

72 SiI-DS-1032-A

SiI9233 HDMI Receiver with Repeater, Multi-channel Audio, and Deep Color Output

Data Sheet

9.8.4.

Digital Audio Output Connections

+3.3V

Ferrite

0.1

F 0.01

F

18 pF

XTALVCC

SiI9233

XTALIN

SCK

WS

SD[3:0]

SPDIF

DCLK

DR[ 2:0]

DL[ 2:0]

MCLKOUT

MUTEOUT

18 pF

1 M

28.322

MHz

XTALOUT

Place crystal circuit as closely to package as possible.

Figure 9.7. Audio Output Schematic

9.8.5.

Control Signal Connections

+3.3V

33

SiI9233

CSDA

CSCL

EVEN/ODD Field

4.7

k

4.7

k

CSDA

CSCL

EVNODD

RSVDL

4.7 k

Microcontroller

GPIO

GPIO

GPIO

Sync status and interrupt bits may be polled through CSDA/CSCL I

2

C port.

RESET#

SCDT

INT

GPIO

Firmware monitors Hot Plug Detect signal to trigger EDID re-read and inhibit HDCP authentication attempts.

Figure 9.8. Controller Connections Schematic

HPD

HDMI

Connector

© 2008-2016 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal . All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice.

SiI-DS-1032-A 73

SiI9233 HDMI Receiver with Repeater, Multi-channel Audio, and Deep Color Output

Data Sheet

9.9.

Layout

Figure 9.9

shows an example of routing TMDS lines between the SiI9233 and the HDMI connector.

9.9.1.

TMDS Input Port Connections

DDC SCL

DDC SDA

Hot Plug

Detect

Connector

Shell

+5V Power

DDC Ground

Reserved NC

CEC

TMDS Clock-

TMDS Clock

Shield

TMDS

Clock+

Figure 9.9. TMDS Input Signal Assignments

TMDS Data 2+

TMDS Data 2-

TMDS Data 1+

TMDS Data 1-

TMDS Data 0+

TMDS Data 0-

TMDS Data Shield

TMDS Data Shield

TMDS Data Shield

© 2008-2016 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal . All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice.

74 SiI-DS-1032-A

10. Packaging

SiI9233 HDMI Receiver with Repeater, Multi-channel Audio, and Deep Color Output

Data Sheet

10.1.

ePad Enhancement

The SiI9233 receiver is packaged in a TQFP package with ePad that must be soldered to ground. The ePad dimensions

are shown in Figure 10.1

.

T1

ePad Dimensions

T1 ePad Height

T2 ePad Width

ΔT ePad tolerance typ max

4.064 4.214

4.445 4.595

±.15

All dimensions are in millimeters.

Center the ePad on the package center lines with the tolerance shown.

A clearance of at least 0.25mm should be designed on the PCB between the edge of the ePad and the inner edges of the lead pads to avoid any electrical shorts.

Tabs may have smaller dimensions than the maximums shown above, and may not appear at all, because minimum width and height are 0.0 mm.

Lattice Semiconductor requires that the ePad be soldered to the PCB and electrically grounded on the PCB. The ePad must not be electrically connected to any other voltage level except ground (GND).

Figure 10.1. ePad Diagram

10.2.

PCB Layout Guidelines

Refer to Lattice Semiconductor document PCB Layout Guidelines: Designing with Exposed Pads (SiI-AN-0129) for basic

PCB design guidelines when designing with thermally enhanced packages using the exposed pad. This application note is intended for use by PCB layout designers.

© 2008-2016 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal . All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice.

SiI-DS-1032-A 75

SiI9233 HDMI Receiver with Repeater, Multi-channel Audio, and Deep Color Output

Data Sheet

10.3.

144-pin TQFP Package Dimensions

JEDEC Package Code MS-026-AFB

A

Thickness

A1 Stand-off

A2 Body Thickness

D1

Body Size

E1

Body Size

D Footprint

E Footprint

D2

Lead Row Width

E2

Lead Row Width typ max

1.10 1.20

0.10 0.15

1.00 1.05

20.00 20.00

20.00 20.00

22.00 22.00

22.00 22.00

17.50 17.50

17.50 17.50

Lead Count

L1 Lead Length

L

Lead Foot b

Lead Width c

Lead Thickness

144

1.00

0.60 0.75

0.20 0.27

0.20 e Lead Pitch aaa Form Tolerance

0.50 0.50

0.20 0.20 bbb

Form Tolerance 0.20 0.20 ccc

Position Tolerance 0.08 0.08 ddd Position Tolerance 0.08 0.08

Dimensions in millimeters.

Overall thickness A=A1+A2.

Figure 10.2. 144-Pin TQFP Package Diagram

© 2008-2016 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal . All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice.

76 SiI-DS-1032-A

SiI9233 HDMI Receiver with Repeater, Multi-channel Audio, and Deep Color Output

Data Sheet

10.4.

Marking Specification

Drawing is not to scale and pin count shown is representative. Refer to specifics in Figure 10.2

on page 76 .

SiI9233CTU

LLLLLL.LL-L

YYWW

TTTTTTmmmr

Pin 1 location

Figure 10.3. Marking Diagram

10.5.

Ordering Information

Production Part Numbers:

SiI9233

TMDS Input Clock Range

25–225 MHz

The universal package may be used in lead-free and ordinary process lines.

Logo

Product Line

Silicon Image Part Number

Lot # (= Job#)

Date code

Trace code

Part Number

SiI9233CTU

© 2008-2016 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal . All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice.

SiI-DS-1032-A 77

SiI9233 HDMI Receiver with Repeater, Multi-channel Audio, and Deep Color Output

Data Sheet

Revision History

Revision A, March 2016

Updated to latest template.

Revision A, August 2008

First production release.

© 2008-2016 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal . All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice.

78 SiI-DS-1032-A

7 th

Floor, 111 SW 5 th

Avenue

Portland, OR 97204, USA

T 503.268.8000 www.latticesemi.com

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