Transcend TS16MLS64V6C Datasheet

Transcend TS16MLS64V6C Datasheet
168PIN PC133 Unbuffered DIMM
128MB with 8Mx16 CL3
TS16MLS64V6C
Description
Placement
The TS16MLS64V6C is a 16M x 64 bits Synchronous
Dynamic
RAM
high-density
for
PC-133.
The
TS16MLS64V6C consists of 8pcs CMOS 8Mx16 bits
Synchronous DRAMs in TSOP-II 400mil packages and
a 2048 bits serial EEPROM on a 168-pin printed circuit
board. The TS16MLS64V6C is a Dual In-Line Memory
Module and is intended for mounting into 168-pin edge
connector sockets.
Synchronous design allows precise cycle control with
A
the use of system clock. I/O transactions are possible
on every clock cycle. Range of operation frequencies,
programmable latencies allow the same device to be
useful for a variety of high bandwidth, high performance
B
memory system applications.
Features
• Performance Range: PC-133.
D
• Conformed to JEDEC Standard Spec.
E
• Burst Mode Operation.
H
G
• Auto and Self Refresh.
F
• CKE Power Down Mode.
• DQM Byte Masking (Read/Write)
• Serial Presence Detect (SPD) with serial EEPROM
PCB: 09-7130
• LVTTL compatible inputs and outputs.
• Single 3.3V ± 0.3V power supply.
• MRS cycle with address key programs.
Latency (Access from column address)
Burst Length (1,2,4,8 & Full Page)
Data Scramble (Sequential & Interleave)
• All inputs are sampled at the positive going edge of
the system clock.
Transcend information Inc.
C
E
1
I
168PIN PC133 Unbuffered DIMM
128MB with 8Mx16 CL3
TS16MLS64V6C
Dimensions
Side
Millimeters
Pin Identification
Inches
A
133.35±0.40
5.250±0.016
B
65.67000
2.585000
C
23.49000
0.925000
D
8.89000
0.350000
E
3.00000
0.118000
F
31.75±0.20
1.250±0.008
G
19.80000
0.788000
H
15.80
I
1.27±0.10
Symbol
Function
A0~A11
Address inputs
BA0~BA1
Select Bank
DQ0~DQ63
data inputs/outputs
CLK0, CLK2
Clock Input
CKE0
Clock Enable Input
/CS0,/CS2
Chip Select Input
0.622
/RAS
Row address strobe
0.050±0.004
/CAS
Column address strobe
/WE
Write Enable
DQM0~7
DQM
Vcc
Power Supply
Vss
Ground
SDA
Serial Address / Data I/O
SA0~2
Address in EEPROM
WP
Write protection
SCL
Serial Clock
NC
No Connection
(Refer Placement)
Transcend information Inc.
2
168PIN PC133 Unbuffered DIMM
128MB with 8Mx16 CL3
TS16MLS64V6C
Pinouts:
Pin
Pin
Pin
Pin
No
Name
No
Name
01
Vss
43
Vss
02
DQ0
44
NC
03
DQ1
45
/CS2
04
DQ2
46
DQM2
05
DQ3
47
DQM3
06
Vcc
48
NC
07
DQ4
49
Vcc
08
DQ5
50
NC
09
DQ6
51
NC
10
DQ7
52
*CB2
11
DQ8
53
*CB3
12
Vss
54
Vss
13
DQ9
55
DQ16
14
DQ10
56
DQ17
15
DQ11
57
DQ18
16
DQ12
58
DQ19
17
DQ13
59
Vcc
18
Vcc
60
DQ20
19
DQ14
61
NC
20
DQ15
62
*Vref
21
*CB0
63
*CKE1
22
*CB1
64
Vss
23
Vss
65
DQ21
24
NC
66
DQ22
25
NC
67
DQ23
26
Vcc
68
Vss
27
/WE
69
DQ24
28
DQM0
70
DQ25
29
DQM1
71
DQ26
30
/CS0
72
DQ27
31
NC
73
Vcc
32
Vss
74
DQ28
33
A0
75
DQ29
34
A2
76
DQ30
35
A4
77
DQ31
36
A6
78
Vss
37
A8
79
*CLK2
38
A10/AP
80
NC
39
BA1
81
NC
40
Vcc
82
SDA
41
Vcc
83
SCL
42
CLK0
84
Vcc
* Please refer Block Diagram
Transcend information Inc.
Pin
No
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
101
102
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
121
122
123
124
125
126
3
Pin
Name
Vss
DQ32
DQ33
DQ34
DQ35
Vcc
DQ36
DQ37
DQ38
DQ39
DQ40
Vss
DQ41
DQ42
DQ43
DQ44
DQ45
Vcc
DQ46
DQ47
*CB4
*CB5
Vss
NC
NC
Vcc
/CAS
DQM4
DQM5
*/CS1
/RAS
Vss
A1
A3
A5
A7
A9
BA0
A11
Vcc
*CLK1
*A12
Pin
No
127
128
129
130
131
132
133
134
135
136
137
138
139
140
141
142
143
144
145
146
147
148
149
150
151
152
153
154
155
156
157
158
159
160
161
162
163
164
165
166
167
168
Pin
Name
Vss
CKE0
*/CS3
DQM6
DQM7
*A13
Vcc
NC
NC
*CB6
*CB7
Vss
DQ48
DQ49
DQ50
DQ51
Vcc
DQ52
NC
*Vref
*REGE
Vss
DQ53
DQ54
DQ55
Vss
DQ56
DQ57
DQ58
DQ59
Vcc
DQ60
DQ61
DQ62
DQ63
Vss
*CLK3
NC
SA0
SA1
SA2
Vcc
168PIN PC133 Unbuffered DIMM
128MB with 8Mx16 CL3
TS16MLS64V6C
Block Diagram
CLK0
CLK
CKE0
CKE
/WE
/CS
/RAS
/CAS
/WE
8Mx16
SDRAM
/CS
CLK
CKE
CLK
CKE
/RAS
/CAS
/WE
8Mx16
SDRAM
/CS
CLK
CKE
UDQM
/CS
8Mx16
SDRAM
A0~A11,
BA0,BA1
DQ0~DQ15
LDQM
/WE
/CAS
UDQM
/WE
/CS0
/RAS
8Mx16
SDRAM
A0~A11,
BA0,BA1
DQ0~DQ15
LDQM
/CAS
UDQM
/RAS
/CAS
LDQM
/RAS
A0~A11,
BA0,BA1
DQ0~DQ15
UDQM
DQ0~DQ63
A0~A11,
BA0,BA1
DQ0~DQ15
LDQM
A0~A11,BA0,BA1
DQM4
DQM0
DQM5
DQM1
DQM6
DQM2
DQM7
DQM3
A0~A11,
BA0,BA1
A0~A11,
BA0,BA1
A0~A11,
BA0,BA1
A0~A11,
BA0,BA1
DQ0~DQ15
DQ0~DQ15
DQ0~DQ15
DQ0~DQ15
/CS2
CLK2
CLK
CKE
DQM5
DQM1
DQM4
DQM0
CLK
CKE
/WE
8Mx16
SDRAM
/CS
DQM6
DQM2
CLK
CKE
UDQM
/CS
/RAS
/CAS
LDQM
CKE
/WE
8Mx16
SDRAM
UDQM
CKE1
/RAS
/CAS
LDQM
CLK
/CS
UDQM
CLK1
/WE
8Mx16
SDRAM
LDQM
/CS
/CAS
UDQM
/WE
/CS1
/RAS
8Mx16
SDRAM
LDQM
/RAS
/CAS
DQM7
DQM3
/CS3
CLK3
SCL
Serial
EEPROM
SCL
SDA
A0
A1
SDA
A2
SA0 SA1 SA2
This technical information is based on industry standard data and tests believed to be reliable. However, Transcend makes no warranties, either expressed
or implied, as to its accuracy and assume no liability in connection with the use of this product. Transcend reserves the right to make changes in specifications
at any time without prior notice.
Transcend information Inc.
4
168PIN PC133 Unbuffered DIMM
128MB with 8Mx16 CL3
TS16MLS64V6C
ABSOLUTE MAXIMUM RATINGS
Parameter
Voltage on any pin relative to Vss
Voltage on VDD supply to Vss
Storage temperature
Power dissipation
Short circuit current
Mean time between failure
Temperature Humidity Burning
Temperature Cycling Test
Note:
Symbol
VIN, VOUT
VDD, VDDQ
TSTG
PD
IOS
MTBF
THB
TC
Value
-1.0~4.6
-1.0~4.6
-55~+150
8
50
50
85°C/85%, Static Stress
0°C ~ 125°C Cycling
Unit
V
V
°C
W
mA
year
°C-%
°C
Permanent device damage may occur if ABSOLUTE MAXIMUM RATINGS are exceeded.
Functional operation should be restricted to recommended operating condition.
Exposure to higher than recommended voltage for extended periods of time could affect device
reliability.
DC OPERATING CONDITIONS AND CHARACTERISTICS
Recommended operating conditions (Voltage referenced to Vss = 0V, TA = 0 to 70°C)
Parameter
Symbol
Min
Typ
Max
Unit
Supply voltage
VDD
3.0
3.3
3.6
V
Input high voltage
VIH
2.0
3.0
VDD+0.3
V
Input low voltage
VIL
-0.3
0
0.8
V
Output high voltage
VOH
2.4
V
Output low voltage
VOL
0.4
V
Input leakage current (Inputs)
IIL
-8
8
uA
Note:
Note
1
2
IOH=-2mA
IOL=2mA
3
1. VIH (max) = 5.6V AC. The overshoot voltage duration is ≤ 3ns.
2. VIL (min) = -2.0V AC. The undershoot voltage duration is ≤ 3ns.
3. Any input 0V ≤ VIN ≤ VDDQ.
Input leakage currents include Hi-Z output leakage for all bi-directional buffers with Tri-State outputs.
CAPACITANCE (TA = 25°C, f = 1MHz)
Parameter
Input capacitance (A0~A11, BA0~ BA1)
Input capacitance (/RAS, /CAS, /WE)
Input capacitance (CKE0~CKE1)
Input capacitance (CLK0~CLK3)
Input capacitance (/CS0~/CS3)
Input capacitance (DQM0~DQM7)
Data input/output capacitance (DQ0~DQ63)
Transcend information Inc.
Symbol
Min
Max
Unit
CIN1
CIN2
CIN3
CIN4
CIN5
CIN6
COUT
25
25
15
10
10
10
13
45
45
25
15
13
15
18
pF
pF
pF
pF
pF
pF
pF
5
168PIN PC133 Unbuffered DIMM
128MB with 8Mx16 CL3
TS16MLS64V6C
DC CHARACTERISTICS
(Recommended operating condition unless otherwise noted, TA = 0 to 70°C)
Parameter
Symbol
Test Condition
CAS Latency
Operating Current
(One Bank Active)
Burst Length =1
tRC≥tRC(min)
IOL=0mA
ICC1
ICC2P
Precharge Standby Current
ICC2PS
in power-down mode
ICC2N
Precharge Standby Current
in non power-down mode
ICC2NS
Value
Unit
Note
520
mA
1
CKE≤VIL(max), tCC=15ns
16
CKE & CLK≤VIL(max), tCC=∞
16
CKE≥VIH(min), /CS≥VIH(min), tCC=15ns
160
mA
Input signals are changed one time during 30ns
CKE≥VIH(min), CLK≤VIL(max), tCC=∞
mA
80
Input signals are stable
Active Standby Current
in power-down mode
ICC3P
CKE≤VIL(max), tCC=15ns
40
ICC3PS
CKE & CLK≤VIL(max), tCC=∞
40
ICC3N
Active Standby Current
in non power-down mode
(One Bank Active)
CKE≥VIH(min), /CS≥VIH(min), tCC=15ns
Input signals are changed one time during 30ns
ICC3NS
Operating Current
(Bust Mode)
ICC4
Refresh Current
ICC5
Self Refresh Current
ICC6
mA
240
mA
CKE≥VIH(min), CLK≤VIL(max), tCC=∞
Input signals are stable
200
IOL= 0 mA
Page Burst
tccD = 2CLKs
680
mA
tRC≥tRC(min)
920
mA
1
2
C
16
mA
L
6.4
Note: Module IDD was calculated on the basis of component IDD and can be differently measured according to DQ
loading cap.
Transcend information Inc.
CKE≤0.2V
6
168PIN PC133 Unbuffered DIMM
128MB with 8Mx16 CL3
TS16MLS64V6C
AC OPERATING TEST CONDITIONS (VDD = 3.3V±0.3V, TA = 0 to 70°C)
Parameter
AC Input levels (VIH/VIL)
Input timing measurement reference level
Input rise and fall time
Output timing measurement reference level
Output load condition
Value
Unit
2.4/0.4
V
1.4
V
tr/tf=1/1
ns
1.4
V
See Fig. 2
Vtt=1.4V
3.3V
50 Ohm
1200 Ohm
VOH (DC)=2.4V, IOH=-2mA
VOL (DC)=0.4V, I OL=2mA
Output
Output
Z0=50 Ohm
50pF
50pF
870 Ohm
(Fig. 2) AC Output Load Circuit
(Fig. 1) DC Output Load Circuit
OPERATING AC PARAMETER (AC operating conditions unless otherwise noted)
Parameter
Row active to row active delay
/RAS to /CAS delay
Row precharge time
Symbol
tRRD(min)
tRCD(min)
tRP(min)
tRAS(min)
tRAS(max)
tRC(min)
tRDL(min)
tDAL(min)
tCDL(min)
tBDL(min)
tCCD(min)
Row active time
Row cycle time
Last data in to row precharge
Last data in to Active delay
Last data in to new col. address delay
Last data in to burst stop
Col. address to col. address delay
Number of valid output data
Note:
CAS latency=3
Value
15
20
20
45
100
65
2
2CLK+tRP
1
1
1
Unit
ns
ns
ns
ns
us
ns
CLK
CLK
CLK
CLK
Note
1
1
1
1
2
ea
4
1. The minimum number of clock cycles is determined by dividing the minimum time required with
clock cycle time, and then rounding off to the next higher integer.
2. Minimum delay is required to complete write.
3. All parts allow every cycle column address change.
4. In case of row precharge interrupt, auto precharge and read burst stop.
Transcend information Inc.
7
1
2
2
2
3
168PIN PC133 Unbuffered DIMM
128MB with 8Mx16 CL3
TS16MLS64V6C
AC CHARACTERISTICS (AC operating conditions unless otherwise noted)
Refer to the individual component, not the whole module.
Parameter
CLK cycle time
CAS latency=3
tCC
CLK to valid
output delay
CAS latency=3
tSAC
Output data
hold time
CAS latency=3
CLK high pulse width
CLK low pulse width
Input setup time
Input hold time
CLK to output in Low-Z
CLK to output
in Hi-Z
Note:
Value
Symbol
tOH
Note
1000
ns
1
5.4
ns
1, 2
ns
2
ns
ns
ns
ns
ns
3
3
3
3
2
Max
7.5
3
tCH
tCL
tSS
tSH
tSLZ
CAS latency=3
Unit
Min
2.5
2.5
1.5
0.8
1
5.4
tSHZ
ns
1. Parameters depend on programmed CAS latency.
2. If clock rising time is longer than 1ns, (tr/2-0.5) ns should be added to the parameter.
3. Assumed input rise and fall time (tr & tf)= 1ns.
If tr & tf is longer than 1ns, transient time compensation should be considered,
i.e., [(tr + tf)/2-1]ns should be added to the parameter.
Transcend information Inc.
8
168PIN PC133 Unbuffered DIMM
128MB with 8Mx16 CL3
TS16MLS64V6C
SIMPLIFIED TRUTH TABLE
COMMAND
Register
CKEn-1 CKEn
Mode Register Set
Auto Refresh
Refresh
Self
Refresh
H
Entry
Exit
Bank Active & Row Addr.
Read &
Auto Precharge Disable
Column Address
Auto Precharge Enable
Write &
Auto Precharge Disable
Column Address
Auto Precharge Enable
Burst Stop
Precharge
H
Bank Selection
L
X
H
L
H
/CS
/RAS
/CAS
/WE
DQM
L
L
L
L
X
OP CODE
L
L
L
H
X
X
X
X
Entry
L
H
H
H
H
X
X
X
X
L
L
H
H
X
V
H
X
L
H
L
H
X
V
X
L
H
L
L
X
H
X
L
H
H
L
X
H
X
L
L
H
L
X
L
H
Entry
H
L
Precharge Power
Down Mode
L
DQM
H
No Operation Command
H
Note:
H
X
X
X
L
V
V
V
X
X
X
X
H
X
X
X
L
H
H
H
H
X
X
X
L
V
V
V
L
Exit
Exit
L
H
X
X
X
1,2
3
H
X
X
X
L
H
H
H
3
Column
Address
(A0~A8)
V
L
Column
Address
(A0~A8)
H
H
X
V
L
X
H
9
4
4, 5
4
4, 5
6
X
X
X
X
X
X
V
X
X
X
(V=Valid, X=Don’t Care, H=Logic High, L=Logic Low)
1. OP Code : Operand Code
A0~A11, BA0~BA1 : Program keys. (@MRS)
2. MRS can be issued only at both banks precharge state.
A new command can be issued after 2 CLK cycles of MRS.
3. Auto refresh functions are as same as CBR refresh of DRAM.
The automatically precharge without row precharge command is meant by “Auto”.
Auto/self refresh can be issued only at both banks precharge state.
4. BA0~BA1: Bank select address.
If both BA0 and BA1 are “Low” at read, write, row active and precharge, bank A is selected.
If both BA0 is “Low” and BA1 is “High” at read, write, row active and precharge, bank B is selected.
If both BA0 is “High” and BA1 is “Low” at read, write, row active and precharge, bank C is selected.
If both BA0 and BA1 are “High” at read, write, row active and precharge, bank D is selected.
If A10/AP is “High” at row precharge, BA0 and BA1 are ignored and both banks are selected.
5. During burst read or write with auto precharge, new read/write command can not be issued.
Another bank read/write command can be issued after the end of burst.
New row active of the associated bank can be issued at tRP after the end of burst.
6. Burst stop command is valid at every burst length.
7. DQM sampled at positive going edged of a CLK masks the data-in at the very CLK (Write DQM latency is 0),
but makes Hi-Z state the data-out of 2 CLK cycles after. (Read DQM latency is 2)
Transcend information Inc.
Note
Row Address
H
H
A11, A0~A9
3
H
Active Power
Down
A10/AP
3
Both Banks
Clock Suspend or
BA0,1
7
168PIN PC133 Unbuffered DIMM
128MB with 8Mx16 CL3
TS16MLS64V6C
Serial Presence Detect Specification
Serial Presence Detect
Byte No.
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
Function Described
# of Bytes Written into Serial Memory
Total # of Bytes of S.P.D Memory
Fundamental Memory Type
# of Row Addresses on this Assembly
# of Column Addresses on this Assembly
# of Module Banks on this Assembly
Data Width of this Assembly
Data Width Continuation
Voltage Interface Standard of this Assembly
SDRAM Cycle Time (highest CAS latency)
SDRAM Access from Clock (highest CL)
DIMM configuration type (non-parity, ECC)
Refresh Rate Type
Primary SDRAM Width
Error Checking SDRAM Width
Min Clock Delay Back to Back Random Address
Burst Lengths Supported
Number of banks on each SDRAM device
CAS # Latency
CS # Latency
Write Latency
SDRAM Module Attributes
SDRAM Device Attributes: General
Standard Specification
128bytes
256bytes
SDRAM
A0~A11
A0~A8
2 bank
64bits
0
LVTTL3.3V
7.5ns
5.4ns
None
15.625us/Self Refresh
X16
64bit
1 clock
1,2,4,8 & Full page
4 bank
2&3
0 clock
0 clock
Non Buffer
Prec All, Auto Prec, R/W
Burst
10ns
6ns
0
0
20
15
20
45
64MB
1.5ns
0.8ns
1.5ns
0.8ns
JEDEC2
97
Transcend
T
Vendor Part
80
08
04
0C
09
02
40
00
01
75
54
00
80
10
00
01
8F
04
06
01
01
00
0E
23
24
25
26
27
28
29
30
31
32
33
34
35
36-61
62
63
64-71
72
SDRAM Cycle Time (2nd highest CL)
SDRAM Access from Clock (2nd highest CL)
SDRAM Cycle Time (3rd highest CL)
SDRAM Access from Clock (3rd highest CL)
Minimum Row Precharge Time
Minimum Row Active to Row Activate
Minimum RAS to CAS Delay
Minimum RAS Pulse Width
Density of Each Bank on Module
Command/Address Setup Time
Command/Address Hold Time
Data Signal Setup Time
Data Signal Hold Time
Superset Information
SPD Data Revision Code
Checksum for Bytes 0-62
Manufacturers JEDEC ID Code per JEP-108E
Manufacturing Location
73-90
Manufacturers Part Number
TS16MLS64V6C
91-92
93-94
95-98
Revision Code
Manufacturing Date
Assembly Serial Number
By Manufacturer
A0
60
00
00
14
0F
14
2D
10
15
08
15
08
00
02
97
7F, 4F
54
54 53 31 36 4D 4C
53 36 34 56 36 43
20 20 20 20 20 20
0
Variable
By Manufacturer
Variable
Transcend information Inc.
10
168PIN PC133 Unbuffered DIMM
128MB with 8Mx16 CL3
TS16MLS64V6C
99-125
126
127
128~
Manufacturer Specific Data
Intel Specification Frequency
Intel Specification CAS# Latency/Clock Signal Support
Unused Storage Locations
Transcend information Inc.
11
100MHz
CL=2&3 Clock=0~3
Open
0
64
F6
FF
Was this manual useful for you? yes no
Thank you for your participation!

* Your assessment is very important for improving the work of artificial intelligence, which forms the content of this project

Download PDF

advertisement