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TS16MLS64V6C
Description
The TS16MLS64V6C is a 16M x 64 bits Synchronous
Dynamic RAM high-density for PC-133. The
TS16MLS64V6C consists of 8pcs CMOS 8Mx16 bits
Synchronous DRAMs in TSOP-II 400mil packages and a 2048 bits serial EEPROM on a 168-pin printed circuit board. The TS16MLS64V6C is a Dual In-Line Memory
Module and is intended for mounting into 168-pin edge connector sockets.
Synchronous design allows precise cycle control with the use of system clock. I/O transactions are possible on every clock cycle. Range of operation frequencies, programmable latencies allow the same device to be useful for a variety of high bandwidth, high performance memory system applications.
Features
• Performance Range: PC-133.
• Conformed to JEDEC Standard Spec.
• Burst Mode Operation.
• Auto and Self Refresh.
• CKE Power Down Mode.
• DQM Byte Masking (Read/Write)
• Serial Presence Detect (SPD) with serial EEPROM
• LVTTL compatible inputs and outputs.
• Single 3.3V ± 0.3V power supply.
• MRS cycle with address key programs.
Latency (Access from column address)
Burst Length (1,2,4,8 & Full Page)
Data Scramble (Sequential & Interleave)
• All inputs are sampled at the positive going edge of the system clock.
Transcend information Inc.
1
Placement
168PIN PC133 Unbuffered DIMM
128MB with 8Mx16 CL3
F
E
G
H
E
PCB: 09-7130
D
C
B
A
I
TS16MLS64V6C
Dimensions
Side Millimeters Inches
A 133.35
±0.40 5.250±0.016
B 65.67
000 2.585
000
C 23.49
000 0.925
000
D 8.89
000 0.350
000
E 3.00
000 0.118
000
F 31.75
±0.20 1.250
±0.008
G 19.80
000 0.788
000
H 15.80
I 1.27
±0.10
(Refer Placement)
0.622
0.050
±0.004
168PIN PC133 Unbuffered DIMM
128MB with 8Mx16 CL3
Pin Identification
Symbol Function
CLK0, CLK2
CKE0
/RAS
/CAS
Clock Input
Clock Enable Input
Row address strobe
Column address strobe
DQM0~7 DQM
Vss Ground
SDA
SA0~2
Serial Address / Data I/O
Address in EEPROM
Transcend information Inc.
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TS16MLS64V6C
Pinouts:
168PIN PC133 Unbuffered DIMM
128MB with 8Mx16 CL3
Pin
No
Pin
Name
Pin
No
Pin
Name
Pin
No
Pin
Name
Pin
No
Pin
Name
01 Vss
02 DQ0
03 DQ1
04 DQ2
05 DQ3
06 Vcc
07 DQ4
08 DQ5
43 Vss
44 NC
85 Vss 127 Vss
86 DQ32 128 CKE0
45 /CS2 87 DQ33 129 */CS3
46 DQM2 88 DQ34 130 DQM6
47 DQM3 89 DQ35 131 DQM7
48 NC 90 Vcc 132 *A13
49 Vcc
50 NC
91 DQ36
92 DQ37
133 Vcc
134 NC
09 DQ6
10 DQ7
11 DQ8
12 Vss
51 NC 93 DQ38 135 NC
52 *CB2 94 DQ39 136 *CB6
53 *CB3 95 DQ40 137 *CB7
54 Vss 96 Vss 138 Vss
13 DQ9 55 DQ16 97 DQ41 139 DQ48
14 DQ10 56 DQ17 98 DQ42 140 DQ49
15 DQ11 57 DQ18 99 DQ43 141 DQ50
16 DQ12 58 DQ19 100 DQ44 142 DQ51
17 DQ13 59 Vcc
18 Vcc 60 DQ20
101 DQ45
102 Vcc
143 Vcc
144 DQ52
19 DQ14 61 NC 103 DQ46 145 NC
20 DQ15 62 *Vref 104 DQ47 146 *Vref
21 *CB0
22 *CB1
23 Vss
24 NC
63 *CKE1 105 *CB4 147 *REGE
64 Vss 106 *CB5
65 DQ21 107 Vss
66 DQ22 108 NC
148 Vss
149 DQ53
150 DQ54
25 NC
26 Vcc
67 DQ23 109 NC
68 Vss 110 Vcc
151 DQ55
152 Vss
27 /WE 69 DQ24 111 /CAS 153 DQ56
28 DQM0 70 DQ25 112 DQM4 154 DQ57
29 DQM1 71 DQ26 113 DQM5 155 DQ58
30 /CS0 72 DQ27 114 */CS1 156 DQ59
31 NC
32 Vss
73 Vcc
74 DQ28
115 /RAS
116 Vss
157 Vcc
158 DQ60
33 A0
34 A2
35 A4
36 A6
75 DQ29 117 A1
76 DQ30 118 A3
77 DQ31 119 A5
78 Vss 120 A7
37 A8 79 *CLK2 121 A9
38 A10/AP 80 NC 122 BA0
39 BA1
40 Vcc
81 NC
82 SDA
123 A11
124 Vcc
159 DQ61
160 DQ62
161 DQ63
162 Vss
163 *CLK3
164 NC
165 SA0
166 SA1
41 Vcc 83 SCL 125 *CLK1 167 SA2
42 CLK0 84 Vcc 126 *A12 168 Vcc
* Please refer Block Diagram
Transcend information Inc.
3
TS16MLS64V6C
Block Diagram
A0~A11,BA0,BA1
DQ0~DQ63
/RAS
/CAS
/WE
/CS0
CLK0
CKE0
168PIN PC133 Unbuffered DIMM
128MB with 8Mx16 CL3
A0~A11,
BA0,BA1
DQ0~DQ15
/RAS
/CAS
/WE
/CS
8Mx16
SDRAM
CLK
CKE
DQM4
DQM0
A0~A11,
BA0,BA1
DQ0~DQ15
/RAS
/CAS
/WE
/CS
8Mx16
SDRAM
CLK
CKE
DQM5
DQM1
A0~A11,
BA0,BA1
DQ0~DQ15
/RAS
/CAS
/WE
/CS
8Mx16
SDRAM
CLK
CKE
DQM6
DQM2
A0~A11,
BA0,BA1
DQ0~DQ15
/RAS
/CAS
8Mx16
SDRAM
/WE
/CS
CLK
CKE
DQM7
DQM3
/CS2
CLK2
/CS1
CLK1
CKE1
A0~A11,
BA0,BA1
DQ0~DQ15
/RAS
/CAS
/WE
8Mx16
SDRAM
/CS
CLK
CKE
DQM4
DQM0
A0~A11,
BA0,BA1
DQ0~DQ15
/RAS
/CAS
/WE
8Mx16
SDRAM
/CS
CLK
CKE
DQM5
DQM1
A0~A11,
BA0,BA1
DQ0~DQ15
/RAS
/CAS
/WE
8Mx16
SDRAM
/CS
CLK
CKE
DQM6
DQM2
A0~A11,
BA0,BA1
DQ0~DQ15
/RAS
/CAS
8Mx16
SDRAM
/WE
/CS
CLK
CKE
DQM7
DQM3
/CS3
CLK3
SCL
Serial
EEPROM
SCL SDA SDA
A0 A1 A2
SA0 SA1 SA2
This technical information is based on industry standard data and tests believed to be reliable. However, Transcend makes no warranties, either expressed or implied, as to its accuracy and assume no liability in connection with the use of this product. Transcend reserves the right to make changes in specifications at any time without prior notice.
Transcend information Inc.
4
TS16MLS64V6C
ABSOLUTE MAXIMUM RATINGS
Parameter
Voltage on any pin relative to Vss
Voltage on V DD supply to Vss
Storage temperature
Power dissipation
Short circuit current
Mean time between failure
Temperature Humidity Burning
Temperature Cycling Test
168PIN PC133 Unbuffered DIMM
128MB with 8Mx16 CL3
Symbol Value
V IN , V OUT -1.0~4.6
Unit
V
V DD , V DDQ -1.0~4.6 V
T STG -55~+150 °C
P D 8 W
I OS 50 mA
MTBF
THB
TC
50
85 °C/85%, Static Stress
0 °C ~ 125°C Cycling year
°C-%
°C
Note: Permanent device damage may occur if ABSOLUTE MAXIMUM RATINGS are exceeded.
Functional operation should be restricted to recommended operating condition.
Exposure to higher than recommended voltage for extended periods of time could affect device reliability.
DC OPERATING CONDITIONS AND CHARACTERISTICS
Recommended operating conditions (Voltage referenced to Vss = 0V, T A = 0 to 70 °C)
Parameter
Supply voltage
Input high voltage
Input low voltage
Output high voltage
Output low voltage
Input leakage current (Inputs)
Symbol Min Typ Max Unit
V DD 3.0 3.3 3.6 V
V IH 2.0 3.0 +0.3 V
Note
1
V IL -0.3 0 0.8 V 2
V OH 2.4 - - V IOH=-2mA
V OL - - 0.4 V IOL=2mA
I IL -8 - 8 uA 3
Note: 1. V IH (max) = 5.6V AC. The overshoot voltage duration is ≤ 3ns.
2. V IL (min) = -2.0V AC. The undershoot voltage duration is ≤ 3ns.
3. Any input 0V ≤ V
IN
≤ V
DDQ.
Input leakage currents include Hi-Z output leakage for all bi-directional buffers with Tri-State outputs.
CAPACITANCE
(TA = 25 °C, f = 1MHz)
Parameter
Input capacitance (A 0 ~A 11 , BA 0 ~ BA 1 )
Input capacitance (/RAS, /CAS, /WE)
Input capacitance (CKE0~CKE1)
Input capacitance (CLK0~CLK3)
Input capacitance (/CS0~/CS3)
Input capacitance (DQM0~DQM7)
Data input/output capacitance (DQ0~DQ63)
Symbol
C IN1
C IN2
C IN3
C IN4
C IN5
C IN6
C OUT
Min
25
25
15
10
10
10
13
Max
45
45
25
15
13
15
18
Unit pF pF pF pF pF pF pF
Transcend information Inc.
5
TS16MLS64V6C
168PIN PC133 Unbuffered DIMM
128MB with 8Mx16 CL3
DC CHARACTERISTICS
(Recommended operating condition unless otherwise noted, T A = 0 to 70 °C)
Parameter Symbol Test Condition CAS Latency Value Unit Note
Operating Current
(One Bank Active)
Precharge Standby Current in power-down mode
I CC1
Burst Length =1 t RC
≥t
RC (min)
I OL =0mA
520 mA 1
I CC2 P CKE ≤V
IL( max), t CC =15ns 16
I CC2 PS CKE & CLK≤V IL( max), t CC =∞ 16
160
Precharge Standby Current in non power-down mode
I CC2 N CKE ≥V
IH( min), /CS ≥V
IH( min), t CC =15ns
Input signals are changed one time during 30ns
I CC2 NS CKE≥V IH( min), CLK ≤V
IL( max), t CC =∞
Input signals are stable
I CC3 P CKE ≤V
IL( max), t CC =15ns
Active Standby Current in power-down mode I CC3 PS CKE & CLK≤V IL( max), t CC =∞
I CC3 N
Active Standby Current in non power-down mode
(One Bank Active) I CC3
CKE ≥V
IH( min), /CS ≥V
IH( min), t CC =15ns
Input signals are changed one time during 30ns
NS CKE≥V
IH( min), CLK ≤V
Input signals are stable
IL( max), t CC =∞
80
40
40
240
200 mA mA mA
Operating Current
(Bust Mode)
I CC4
I OL= 0 mA
Page Burst tcc
D = 2CLKs t RC
≥t
RC (min)
680 mA
1
Refresh Current I CC5 920 mA
2
Self Refresh Current I CC6
CKE ≤0.2V
C 16
L 6.4 mA
Note: Module IDD was calculated on the basis of component IDD and can be differently measured according to DQ loading cap.
Transcend information Inc.
6
TS16MLS64V6C
168PIN PC133 Unbuffered DIMM
128MB with 8Mx16 CL3
AC OPERATING TEST CONDITIONS
(V DD = 3.3V
±0.3V, TA = 0 to 70°C)
Parameter Value Unit
AC Input levels (V IH /V IL ) 2.4/0.4
Input timing measurement reference level 1.4 V
Input rise and fall time
Output timing measurement reference level tr/tf=1/1
1.4 ns
V
Output load condition See Fig. 2
Vtt=1.4V
3.3V
50 Ohm
Output
870 Ohm
1200 Ohm
50pF
V
OH
(DC)=2.4V, I
OH
=-2mA
V
OL
(DC)=0.4V, I
OL
=2mA
Output Z0=50 Ohm
50pF
(Fig. 1) DC Output Load Circuit (Fig. 2) AC Output Load Circuit
OPERATING AC PARAMETER
(AC operating conditions unless otherwise noted)
Parameter
Row active to row active delay
Symbol Value Unit Note t RRD (min) 15 1
/RAS to /CAS delay t RCD (min) 20 1
Row precharge time
Row active time
Row cycle time
Last data in to row precharge
Last data in to Active delay
Last data in to new col. address delay
Last data in to burst stop
Col. address to col. address delay t RP (min) 20 1 t RAS (min) 45 1 t RAS (max) 100 t RC (min) 65 1 t RDL (min) 2 2 t DAL (min) 2CLK+tRP t CDL (min) 1 2 t BDL (min) 1 2 t CCD (min) 1 3
Number of valid output data CAS latency=3 2 ea 4
Note: 1. The minimum number of clock cycles is determined by dividing the minimum time required with
clock cycle time, and then rounding off to the next higher integer.
2. Minimum delay is required to complete write.
3. All parts allow every cycle column address change.
4. In case of row precharge interrupt, auto precharge and read burst stop.
Transcend information Inc.
7
TS16MLS64V6C
168PIN PC133 Unbuffered DIMM
128MB with 8Mx16 CL3
AC CHARACTERISTICS
(AC operating conditions unless otherwise noted)
Refer to the individual component, not the whole module.
Parameter Symbol
Value
Min Max
Unit Note
CLK cycle time t CC CAS latency=3 7.5 1000 ns 1
CLK to valid output delay
CAS latency=3 t SAC 5.4 2
Output data hold time
CLK high pulse width
CLK low pulse width
Input setup time
Input hold time
CLK to output in Low-Z
CLK to output in Hi-Z
CAS latency=3
CAS latency=3 t t t t t t t
OH
CH
CL
SS
SH
SLZ
SHZ
3
2.5
2.5 ns 2
1.5 ns 3
0.8 ns 3 ns 3 ns 3
1 ns 2
5.4 ns
Note: 1. Parameters depend on programmed CAS latency.
2. If clock rising time is longer than 1ns, (tr/2-0.5) ns should be added to the parameter.
3. Assumed input rise and fall time (tr & tf)= 1ns.
If tr & tf is longer than 1ns, transient time compensation should be considered,
i.e., [(tr + tf)/2-1]ns should be added to the parameter.
Transcend information Inc.
8
TS16MLS64V6C
SIMPLIFIED TRUTH TABLE
COMMAND CKEn-1 CKEn /CS /RAS /CAS /WE
Register Mode Register Set
168PIN PC133 Unbuffered DIMM
128MB with 8Mx16 CL3
DQM BA
0,1
A
10
/AP A
11
, A
0
~A
9
H X L L L L X
Note
1,2
Auto Refresh
Refresh
Self
Refresh
Entry
Exit
Bank Active & Row Addr.
Read & Auto Precharge Disable
Column Address Auto Precharge Enable
Write & Auto Precharge Disable
Column Address Auto Precharge Enable
Burst Stop
H
H
L
L L L H X X
X X
3
3
3
H X X X
L L H H X V Row Address
3
H X
H X L H L H X V
L 4
Address
H (A
0
~A
8
) 4, 5
H X L H L L X V
L 4
Address
H
(A
0
~A
8
)
4, 5
H X L H H L X X 6
Precharge
Bank Selection
Both Banks
Clock Suspend or
Active Power
Down
Precharge Power
Down Mode
Entry
Exit
H X L L H L X
V L
X H
H X X X
L V V V
X
X
X
L H H H
X
L V V V
X
X
No Operation Command X X
L H H H
(V=Valid, X=Don’t Care, H=Logic High, L=Logic Low)
Note: 1. OP Code : Operand Code
A 0 ~A 11 , BA 0 ~BA 1 : Program keys. (@MRS)
2. MRS can be issued only at both banks precharge state.
A new command can be issued after 2 CLK cycles of MRS.
3. Auto refresh functions are as same as CBR refresh of DRAM.
The automatically precharge without row precharge command is meant by “Auto”.
Auto/self refresh can be issued only at both banks precharge state.
4. BA
If A
0 ~BA
10
1 : Bank select address.
If both BA
If both BA
If both BA
If both BA
0
0
0
0 and BA and BA
1
1 are “Low” at read, write, row active and precharge, bank A is selected.
is “Low” and BA 1
is “High” and BA 1
is “High” at read, write, row active and precharge, bank B is selected.
is “Low” at read, write, row active and precharge, bank C is selected. are “High” at read, write, row active and precharge, bank D is selected.
/AP is “High” at row precharge, BA 0 and BA 1 are ignored and both banks are selected.
5. During burst read or write with auto precharge, new read/write command can not be issued.
Another bank read/write command can be issued after the end of burst.
New row active of the associated bank can be issued at tRP after the end of burst.
6. Burst stop command is valid at every burst length.
7. DQM sampled at positive going edged of a CLK masks the data-in at the very CLK (Write DQM latency is 0),
but makes Hi-Z state the data-out of 2 CLK cycles after. (Read DQM latency is 2)
Transcend information Inc.
9
TS16MLS64V6C
Serial Presence Detect Specification
168PIN PC133 Unbuffered DIMM
128MB with 8Mx16 CL3
Byte No.
0
1
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
Function Described
# of Bytes Written into Serial Memory
Total # of Bytes of S.P.D Memory
# of Row Addresses on this Assembly
# of Column Addresses on this Assembly
# of Module Banks on this Assembly
Data Width of this Assembly
Data Width Continuation
Voltage Interface Standard of this Assembly
SDRAM Cycle Time (highest CAS latency)
SDRAM Access from Clock (highest CL)
DIMM configuration type (non-parity, ECC)
Refresh Rate Type
Primary SDRAM Width
Error Checking SDRAM Width
Min Clock Delay Back to Back Random Address
Burst Lengths Supported
Number of banks on each SDRAM device
CAS # Latency
CS # Latency
Write Latency
SDRAM Module Attributes
SDRAM Device Attributes: General
23 SDRAM Cycle Time (2 nd highest CL)
24 SDRAM Access from Clock (2 nd highest CL)
25 SDRAM Cycle Time (3 rd highest CL)
26 SDRAM Access from Clock (3 rd highest CL)
27 Minimum Row Precharge Time
28 Minimum Row Active to Row Activate
29 Minimum RAS to CAS Delay
30 Minimum RAS Pulse Width
31 Density of Each Bank on Module
32 Command/Address Setup Time
33
34
35
Command/Address Hold Time
Data Signal Setup Time
Data Signal Hold Time
62 SPD Data Revision Code
63 Checksum for Bytes 0-62
Serial Presence Detect
64-71 Manufacturers JEDEC ID Code per JEP-108E
Standard Specification
128bytes
256bytes
SDRAM
A0~A11
A0~A8
2 bank
64bits
0
LVTTL3.3V
7.5ns
5.4ns
None
15.625us/Self Refresh
X16
64bit
1 clock
1,2,4,8 & Full page
4 bank
2&3
0 clock
0 clock
Non Buffer
Prec All, Auto Prec, R/W
Burst
10ns
6ns
0
0
20
15
20
45
64MB
1.5ns
0.8ns
1.5ns
0.8ns
-
JEDEC2
97
Transcend
T
73-90 Manufacturers Part Number
93-94 Manufacturing Date
95-98 Assembly Serial Number
TS16MLS64V6C
-
By Manufacturer
By Manufacturer
Vendor Part
80
08
04
0C
09
02
40
00
80
10
00
00
01
75
54
01
8F
04
06
01
01
00
0E
10
15
08
15
08
00
02
97
A0
60
00
00
14
0F
14
2D
7F, 4F
54
54 53 31 36 4D 4C
53 36 34 56 36 43
20 20 20 20 20 20
0
Variable
Variable
Transcend information Inc.
10
TS16MLS64V6C
126 Intel Specification Frequency
127 Intel Specification CAS# Latency/Clock Signal Support
128~ Unused Storage Locations
168PIN PC133 Unbuffered DIMM
128MB with 8Mx16 CL3
-
100MHz
CL=2&3 Clock=0~3
Open
0
64
F6
FF
Transcend information Inc.
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