Transcend TS32MLS64V8F2 Datasheet

Transcend TS32MLS64V8F2 Datasheet
168PIN PC100 Unbuffered DIMM
256MB With 32M X 8 CL2
TS32MLS64V8F2
Description
Placement
The TS32MLS64V8F2 is a 32M x 64bits Synchronous
Dynamic RAM high-density for PC-100 CL2. The
TS32MLS64V8F2 consists of 8pcs CMOS 32Mx8 bits
Synchronous DRAMs in TSOP-II 400mil packages and
a 2048 bits serial EEPROM on a 168-pin printed circuit
board. The TS32MLS64V8F2 is a Dual In-Line Memory
Module and is intended for mounting into 168-pin edge
connector sockets.
Synchronous design allows precise cycle control with
the use of system clock. I/O transactions are possible
on every clock cycle. Range of operation frequencies,
A
programmable latencies allow the same device to be
useful for a variety of high bandwidth, high performance
memory system applications.
Features
B
• Performance Range: PC-100 CL2
D
• Conformed to JEDEC Standard Spec.
• 33,554,432 words x 64 bits organization.
E
• Burst Mode Operation.
C
• Auto and Self Refresh.
• CKE Power Down Mode.
E
• DQM Byte Masking (Read/Write)
H
• Serial Presence Detect (SPD) with serial EEPROM
G
• LVTTL compatible inputs and outputs.
F
• Single 3.3V ± 0.3V power supply.
• MRS cycle with address key programs.
PCB: 09-7309
Latency (Access from column address)
Burst Length (1,2,4,8 & Full Page)
Data Sequence (Sequential & Interleave)
• All inputs are sampled at the positive going edge of
the system clock.
Transcend information Inc.
1
I
168PIN PC100 Unbuffered DIMM
256MB With 32M X 8 CL2
TS32MLS64V8F2
Dimensions
Pin Identification
Side
Millimeters
Inches
A
133.35±0.40
5.250±0.016
B
65.67000
2.585000
C
23.49000
0.925000
D
8.89000
0.350000
E
3.00000
0.118000
F
31.75±0.200
G
Symbol
Function
A0~A12, BA0, BA1 Address input
DQ0~DQ63
Data Input / Output.
CLK0, CLK2
Clock Input.
1.250±0.0080
CKE0
Clock Enable Input.
19.8000
0.788000
/CS0, /CS2
Chip Select Input.
H
15.80
0.622
I
1.27±0.10
0.050±0.004
/RAS
Row Address Strobe
/CAS
Column Address Strobe
/WE
Write Enable
DQM0~DQM7
Data (DQ) Mask
SA0~SA2
Address in EEPROM
SCL
Serial PD Clock
SDA
Serial PD Add/Data input/output
Vcc
+3.3 Volt Power Supply
Vss
Ground
NC
No Connection
(Refer Placement)
Transcend information Inc.
2
168PIN PC100 Unbuffered DIMM
256MB With 32M X 8 CL2
TS32MLS64V8F2
Pinouts:
Pin
No
01
02
03
04
05
06
07
08
09
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
Pin
Name
Vss
DQ0
DQ1
DQ2
DQ3
Vcc
DQ4
DQ5
DQ6
DQ7
DQ8
Vss
DQ9
DQ10
DQ11
DQ12
DQ13
Vcc
DQ14
DQ15
*CB0
*CB1
Vss
NC
NC
Vcc
/WE
DQM0
DQM1
/CS0
NC
Vss
A0
A2
A4
A6
A8
A10/AP
BA1
Vcc
Vcc
CLK0
Pin
No
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
Pin
Name
Vss
NC
/CS2
DQM2
DQM3
NC
Vcc
NC
NC
*CB2
*CB3
Vss
DQ16
DQ17
DQ18
DQ19
Vcc
DQ20
NC
*Vref
*CKE1
Vss
DQ21
DQ22
DQ23
Vss
DQ24
DQ25
DQ26
DQ27
Vcc
DQ28
DQ29
DQ30
DQ31
Vss
*CLK2
NC
NC
SDA
SCL
Vcc
Pin
No
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
101
102
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
121
122
123
124
125
126
*Please refer Block Diagram
Transcend information Inc.
3
Pin
Name
Vss
DQ32
DQ33
DQ34
DQ35
Vcc
DQ36
DQ37
DQ38
DQ39
DQ40
Vss
DQ41
DQ42
DQ43
DQ44
DQ45
Vcc
DQ46
DQ47
*CB4
*CB5
Vss
NC
NC
Vcc
/CAS
DQM4
DQM5
*/CS1
/RAS
Vss
A1
A3
A5
A7
A9
BA0
A11
Vcc
*CLK1
*A12
Pin
No
127
128
129
130
131
132
133
134
135
136
137
138
139
140
141
142
143
144
145
146
147
148
149
150
151
152
153
154
155
156
157
158
159
160
161
162
163
164
165
166
167
168
Pin
Name
Vss
CKE0
*/CS3
DQM6
DQM7
*A13
Vcc
NC
NC
*CB6
*CB7
Vss
DQ48
DQ49
DQ50
DQ51
Vcc
DQ52
NC
*Vref
*REGE
Vss
DQ53
DQ54
DQ55
Vss
DQ56
DQ57
DQ58
DQ59
Vcc
DQ60
DQ61
DQ62
DQ63
Vss
*CLK3
NC
SA0
SA1
SA2
Vcc
168PIN PC100 Unbuffered DIMM
256MB With 32M X 8 CL2
TS32MLS64V8F2
Block Diagram
/CS0
/CS
/CS
D39
D38
D37
D36
D35
D34
D33
D32
DQM0
DQ0
DQ1 U5
DQ2 32Mx8
DQ3 SDRAM
DQ4
DQ5
DQ6
DQ7
DQM
DQ0
U1
DQ1
DQ2 32Mx8
DQ3 SDRAM
DQ4
DQ5
DQ6
DQ7
DQM
D7
D6
D5
D4
D3
D2
D1
D0
DQM4
/CS
D47
D46
D45
D44
D43
D42
D41
D40
DQM1
DQ0
DQ1 U6
DQ2 32Mx8
DQ3 SDRAM
DQ4
DQ5
DQ6
DQ7
DQM
DQ0
DQ1
U2
DQ2 32Mx8
DQ3 SDRAM
DQ4
DQ5
DQ6
DQ7
DQM
D15
D14
D13
D12
D11
D10
D9
D8
/CS
A0~An,
BA0&1
U0~U7
/RAS
U0~U7
/CAS
U0~U7
/WE
U0~U7
CKE0
U0~U7
DQM5
10 ohm
Dn
/CS1
/CS
D55
D54
D53
D52
D51
D50
D49
D48
VDD
DQ0
U7
DQ1
DQ2 32Mx8
DQ3 SDRAM
DQ4
DQ5
DQ6
DQ7
one 0.33uF Capacitors
per each SDRAM
VSS
To all SDRAMs
U1/U3
DQM
DQ0
U3
DQ1
DQ2 32Mx8
DQ3 SDRAM
DQ4
DQ5
DQ6
DQ7
DQM
D23
D22
D21
D20
D19
D18
D17
D16
/CS
U5/U7
DQM6
DQM2
Every DQ
pin of
SDRAM
10 ohm
CLK 0/2
/CS
DQM3
D63
D62
D61
D60
D59
D58
D57
D56
DQ0
U8
DQ1
DQ2 32Mx8
DQ3 SDRAM
DQ4
DQ5
DQ6
DQ7
DQM
DQ0
U4
DQ1
DQ2 32Mx8
DQ3 SDRAM
DQ4
DQ5
DQ6
DQ7
DQM
D31
D30
D29
D28
D27
D26
D25
D24
U2/U4
/CS
DQM7
U6/U8
SCL
Serial EEPROM
SCL SDA
A0
A1
WP
SDA
A2
SA0 SA1 SA2
47k ohm
This technical information is based on industry standard data and tests believed to be reliable. However, Transcend makes no warranties, either expressed
or implied, as to its accuracy and assume no liability in connection with the use of this product. Transcend reserves the right to make changes in
specifications at any time without prior notice.
Transcend information Inc.
4
168PIN PC100 Unbuffered DIMM
256MB With 32M X 8 CL2
TS32MLS64V8F2
ABSOLUTE MAXIMUM RATINGS
Symbol
Value
Unit
Voltage on any pin relative to Vss
Parameter
VIN, VOUT
-1.0~4.6
V
Voltage on VDD supply to Vss
VDD, VDDQ
-1.0~4.6
V
TSTG
-55~+150
°C
Power dissipation
PD
8
W
Short circuit current
Operating Temperature
IOS
TA
50
0 ~ 70
mA
°C
Storage temperature
Note:
Permanent device damage may occur if ABSOLUTE MAXIMUM RATINGS are exceeded.
Functional operation should be restricted to recommended operating condition.
Exposure to higher than recommended voltage for extended periods of time could affect device
reliability.
DC OPERATING CONDITIONS AND CHARACTERISTICS
Recommended operating conditions (Voltage referenced to Vss = 0V, TA = 0 to 70°C)
Parameter
Symbol
Min
Typ
Max
Unit
Supply voltage
VDD
3.0
3.3
3.6
V
Input high voltage
VIH
2.0
3.0
VDD+0.3
V
1
Input low voltage
VIL
-0.3
0
0.8
V
2
Output high voltage
VOH
2.4
-
-
V
IOH=-2mA
Output low voltage
VOL
-
-
0.4
V
IOL=2mA
ILI
-8
-
8
uA
3
Input leakage current
Note
Note: 1. VIH (max) = 5.6V AC .The overshoot voltage duration is ≤ 3ns.
2. VIL (min) = -2.0V AC .The undershoot voltage duration is ≤ 3ns.
3. Any input 0V ≤ VIN ≤ VDDQ.
Input leakage currents include Hi-Z output leakage for all bi-directional buffers with Tri-State outputs.
Transcend information Inc.
5
168PIN PC100 Unbuffered DIMM
256MB With 32M X 8 CL2
TS32MLS64V8F2
CAPACITANCE (TA = 25°C, f = 1MHz)
Parameter
Symbol
Min
Max
Unit
Input capacitance (A0~A12, BA0~ BA1)
CIN1
40
60
pF
Input capacitance (/RAS, /CAS, /WE)
CIN2
40
60
pF
Input capacitance (CKE0)
CIN3
35
55
pF
Input capacitance (CLK0, CLK2)
CIN4
25
35
pF
Input capacitance (/CS0, /CS2)
CIN5
25
35
pF
Input capacitance (DQM0~DQM7)
CIN6
5
15
pF
COUT1
5
15
pF
Data input/output capacitance (DQ0~DQ63)
DC CHARACTERISTICS
(Recommended operating condition unless otherwise noted, TA = 0 to 70°C)
Parameter
Symbol
Test Condition
CAS Latency
Operating Current
(One Bank Active)
Precharge Standby Current ICC2P
in power-down mode
ICC2PS
ICC2N
Precharge Standby Current
in non power-down mode
Active Standby Current
in power-down mode
ICC2NS
Note
720
mA
1
CKE≤VIL(max), tCC=10ns
16
CKE & CLK≤VIL(max), tCC=∞
16
CKE≥VIH(min), /CS≥VIH(min), tCC=10ns
Input signals are changed one time during 30ns
CKE≥VIH(min), CLK≤VIL(max), tCC=∞
mA
160
mA
80
Input signals are stable
CKE≤VIL(max), tCC=10ns
48
ICC3PS
CKE & CLK≤VIL(max), tCC=∞
48
CKE≥VIH(min), /CS≥VIH(min), tCC=10ns
Input signals are changed one time during 30ns
mA
240
mA
ICC3NS
Operating Current
(Bust Mode)
ICC4
Refresh Current
ICC5
200
CKE≥VIH(min), CLK≤VIL(max), tCC=∞
Input signals are stable
IOL= 0 mA
Page Burst
tccD = 2CLKs
800
mA
1
tRC≥tRC(min)
1,520
mA
2
CKE≤0.2V
24
mA
Self Refresh Current
ICC6
Note 1. Measured with outputs open.
2. Refresh period is 64ms.
Transcend information Inc.
Unit
ICC3P
ICC3N
Active Standby Current
in non power-down mode
(One Bank Active)
Burst Length =1
tRC≥tRC(min)
IOL=0mA
ICC1
Value
6
2
168PIN PC100 Unbuffered DIMM
256MB With 32M X 8 CL2
TS32MLS64V8F2
AC OPERATING TEST CONDITIONS (VDD = 3.3V±0.3V, TA = 0 to 70°C)
Parameter
Value
AC Input levels (VIH/VIL)
Input timing measurement reference level
Input rise and fall time
Output timing measurement reference level
Output load condition
Unit
2.4/0.4
V
1.4
V
tr/tf=1/1
ns
1.4
V
See Fig. 2
Vtt=1.4V
3.3V
50 Ohm
1200 Ohm
Output
Output
VOH (DC)=2.4V, I OH=-2mA
VOL (DC)=0.4V, I OL=2mA
Z0=50 Ohm
50pF
50pF
870 Ohm
(Fig. 2) AC Output Load Circuit
(Fig. 1) DC Output Load Circuit
OPERATING AC PARAMETER (AC operating conditions unless otherwise noted)
Parameter
Symbol
Row active to row active delay
/RAS to /CAS delay
Row precharge time
Row cycle time
tRRD(min)
tRCD(min)
tRP(min)
tRAS(min)
tRAS(max)
tRC(min)
Last data in to new col. Address delay
Last data in to row precharge
Last data in to Active delay
Last data in to burst stop
Col. address to col. address delay
tCDL(min)
tRDL(min)
tDAL
tBDL(min)
tCCD(min)
Row active time
Number of valid
CAS latency=2
Value
Unit
Note
20
20
20
50
100
70
ns
ns
ns
ns
us
ns
1
1
1
1
1
2
2CLK+20ns
1
1
1
CLK
CLK
CLK
CLK
2
2
5
2
3
ea
4
output data
Note: 1. The minimum number of clock cycles is determined by dividing the minimum time required with
clock cycle time, and then rounding off to the next higher integer.
2. Minimum delay is required to complete write.
3. All parts allow every cycle column address change.
4. In case of row precharge interrupt, auto precharge and read burst stop.
5. For CL=2, tRDL=1CLK and tDAL=1CLK+20ns is also supported.
Transcend recommends tRDL=2CLK and tDAL=2CLK+20ns.
Transcend information Inc.
7
1
168PIN PC100 Unbuffered DIMM
256MB With 32M X 8 CL2
TS32MLS64V8F2
AC CHARACTERISTICS (AC operating conditions unless otherwise noted)
Refer to the individual component, not the whole module.
Parameter
CLK cycle time
Symbol
Value
Unit
Note
Min
Max
10
1000
ns
1
6
ns
1, 2
CAS latency=2
tCC
CAS latency=2
tSAC
CAS latency=2
tOH
3
ns
2
CLK high pulse width
tCH
3
ns
3
CLK low pulse width
tCL
3
ns
3
Input setup time
tSS
2
ns
3
Input hold time
tSH
1
ns
3
CLK to output in Low-Z
tSLZ
1
ns
2
CLK to valid
output delay
Output data
hold time
CLK to output
in Hi-Z
Note:
CAS latency=2
6
tSHZ
ns
1. Parameters depend on programmed CAS latency.
2. If clock rising time is longer than 1ns, (tr/2-0.5) ns should be added to the parameter.
3. Assumed input rise and fall time (tr & tf)= 1ns.
If tr & tf is longer than 1ns, transient time compensation should be considered,
i.e., [(tr + tf)/2-1]ns should be added to the parameter.
Transcend information Inc.
8
168PIN PC100 Unbuffered DIMM
256MB With 32M X 8 CL2
TS32MLS64V8F2
SIMPLIFIED TRUTH TABLE
COMMAND
CKEn-1 CKEn
Register
Mode Register Set
Refresh
Auto Refresh
Self
Refresh
Entry
Exit
Bank Active & Row Addr.
Read &
Column Address
Write &
Column Address
/RAS
/CAS
/WE
DQM
BA0,1
A10/AP
H
X
L
L
L
L
X
OP CODE
H
H
L
L
L
L
H
X
X
L
H
L
H
H
X
H
X
H
X
X
X
H
X
L
L
H
H
X
V
H
X
L
H
L
H
X
V
Auto Precharge Disable
Auto Precharge Enable
Bank Selection
Both Banks
Clock Suspend or Entry
Active Power
Down
Exit
H
X
L
H
L
L
X
H
X
L
H
H
L
X
H
X
H
L
L
H
H
L
Entry
L
H
L
H
X
X
X
L
V
V
V
X
X
X
X
H
X
X
X
L
H
H
H
H
X
X
X
L
V
V
V
H
L
X
X
H
X
H
X
L
V
V
X
1,2
3
3
3
3
L
H
L
H
X
L
H
Column
Address
(A0~A9)
Column
Address
(A0~A9)
4
4, 5
4
4, 5
6
X
X
X
X
X
H
X
H
H
X
V
X
7
X
X
X
H
(V=Valid, X=Don’t Care, H=Logic High, L=Logic Low)
Note: 1. OP Code: Operand Code
A0~A12, BA0~BA1: Program keys. (@MRS)
2. MRS can be issued only at both banks precharge state.
A new command can be issued after 2 CLK cycles of MRS.
3. Auto refresh functions are as same as CBR refresh of DRAM.
The automatically precharge without row precharge command is meant by “Auto”.
Auto/self refresh can be issued only at both banks precharge state.
4. BA0~BA1: Bank select address.
If both BA0 and BA1 are “Low” at read, write, row active and precharge, bank A is selected.
If both BA0 is “Low” and BA1 is “High” at read, write, row active and precharge, bank B is selected.
If both BA0 is “High” and BA1 is “Low” at read, write, row active and precharge, bank C is selected.
If both BA0 and BA1 are “High” at read, write, row active and precharge, bank D is selected.
If A10/AP is “High” at row precharge, BA0 and BA1 is ignored and both banks are selected.
5. During burst read or write with auto precharge, new read/write command cannot be issued.
Another bank read/write command can be issued after the end of burst.
New row active of the associated bank can be issued at tRP after the end of burst.
6. Burst stop command is valid at every burst length.
7. DQM sampled at positive going edged of a CLK masks the data-in at the very CLK (Write DQM latency is 0),
but makes Hi-Z state the data-out of 2 CLK cycles after. (Read DQM latency is 2)
Transcend information Inc.
Note
X
Exit
DQM
No Operation Command
L
A11, A12
A0~A9
Row Address
Auto Precharge Disable
Auto Precharge Enable
Burst Stop
Precharge
Precharge Power
Down Mode
/CS
9
168PIN PC100 Unbuffered DIMM
256MB With 32M X 8 CL2
TS32MLS64V8F2
Serial Presence Detect Specification
Serial Presence Detect
Byte No.
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
Function Described
# of Bytes Written into Serial Memory
Total # of Bytes of S.P.D Memory
Fundamental Memory Type
# of Row Addresses on this Assembly
# of Column Addresses on this Assembly
# of Module Banks on this Assembly
Data Width of this Assembly
Data Width Continuation
Voltage Interface Standard of this Assembly
SDRAM Cycle Time (highest CAS latency)
SDRAM Access from Clock (highest CL)
DIMM configuration type (non-parity, ECC)
Refresh Rate Type
Primary SDRAM Width
Error Checking SDRAM Width
Min Clock Delay Back to Back Random Address
Burst Lengths Supported
Number of banks on each SDRAM device
CAS # Latency
CS # Latency
Write Latency
SDRAM Module Attributes
SDRAM Device Attributes: General
nd
23
24
25
26
27
28
29
30
31
32
33
34
35
36-61
62
63
64-71
72
SDRAM Cycle Time (2 highest CL)
nd
SDRAM Access from Clock (2 highest CL)
rd
SDRAM Cycle Time (3 highest CL)
rd
SDRAM Access from Clock (3 highest CL)
Minimum Row Precharge Time
Minimum Row Active to Row Activate
Minimum RAS to CAS Delay
Minimum RAS Pulse Width
Density of Each Bank on Module
Command/Address Setup Time
Command/Address Hold Time
Data Signal Setup Time
Data Signal Hold Time
Superset Information
SPD Data Revision Code
Checksum for Bytes 0-62
Manufacturers JEDEC ID Code per JEP-108E
Manufacturing Location
73-90
Manufacturers Part Number
Transcend information Inc.
Standard Specification
128bytes
256bytes
SDRAM
A0~A12
A0~A9
1 bank
64bits
0
LVTTL3.3V
10ns
6ns
None
7.8us/Self Refresh
X8
1 clock
1,2,4,8 & Full page
4 bank
3,2
0 clock
0 clock
Non Buffer
Prec All, Auto Prec,
R/W Burst
10ns
6ns
0
0
20
20
20
50
256MB
2ns
1ns
2ns
1ns
Version 1.2
Transcend
T
TS32MLS64V8F2
10
Vendor Part
80
08
04
0D
0A
01
40
00
01
A0
60
00
82
08
00
01
8F
04
06
01
01
00
0E
A0
60
00
00
14
14
14
32
40
20
10
20
10
00
12
39
7F, 4F
54
54 53 33 32 4D 4C
53 36 34 56 38 46
32 20 20 20 20 20
168PIN PC100 Unbuffered DIMM
256MB With 32M X 8 CL2
TS32MLS64V8F2
91-92
93-94
95-98
99-125
126
127
128~
Revision Code
Manufacturing Date
Assembly Serial Number
Manufacturer Specific Data
Intel Specification Frequency
Intel Specification CAS# Latency/Clock Signal Support
Unused Storage Locations
Transcend information Inc.
11
By Manufacturer
By Manufacturer
100MHz
CL=2, 3 Clock=0,2
Open
0
Variable
Variable
0
64
A6
FF
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