Transcend | TS64MSS64V6F | Datasheet | Transcend 512MB SDRAM 144Pin SO-DIMM PC133 Unbuffer Non-ECC Memory

Transcend 512MB SDRAM 144Pin SO-DIMM PC133 Unbuffer Non-ECC Memory
144PIN PC133 Unbuffered SO-DIMM
512MB With 32Mx8 CL3
TS64MSS64V6F
Description
Pin Identification
Module (S.O.DIMM), mounted 16 pieces of 256-Mbit
Symbol
SDRAM sealed in TSOP package and 1 piece of serial
Function
EEPROM (2-kbit) for Presence Detect (PD). An outline of
A0~A12,BA0,BA1 Address input
the products is 144-pin Zig Zag Dual tabs socket type
DQ0~DQ63,
Data Input / Output.
compact and thin package. Therefore, they make high
CLK0,CLK1
Clock Input.
CKE0,CKE1
Clock Enable Input.
Decoupling capacitors are mounted beside TSOP on the
/CS0~/CS3
Chip Select Input.
module board. Note: Do not push the cover or drop the
/RAS
Row Address Strobe
/CAS
Column Address Strobe
/WE
Write Enable
DQM0~DQM7
Data (DQ) Mask
SA0~SA2
Address in EEPROM
• Burst Mode Operation.
SCL
Serial PD Clock
• Auto and Self Refresh.
SDA
Serial PD Add/Data input/output
Vcc
+3.3 Voltage Power Supply
Vss
Ground
NC
No Connection
density
mounting
possible
without
surface
mount
technology. They provide common data inputs and outputs.
modules in order to protect from mechanical defects, which
would be electrical defects.
Features
• Performance Range : PC-133
• Conformed to JEDEC Standard Spec.
• CKE Power Down Mode.
• DQM Byte Masking (Read/Write)
• Serial Presence Detect (SPD) with serial EEPROM
• LVTTL compatible inputs and outputs.
• Single 3.3V ± 0.3V power supply.
• MRS cycle with address key programs.
Latency (Access from column address)
Burst Length (1,2,4,8)
Data Sequence (Sequential & Interleave)
• All inputs are sampled at the positive going edge of
the system clock.
Transcend information Inc
1
144PIN PC133 Unbuffered SO-DIMM
512MB With 32Mx8 CL3
TS64MSS64V6F
Dimension :
B
D
A
C
F
G
H
PCB : 09-7265
Side
Millimeters
Inches
A
67.60
2.661
B
32.80
1.291
C
23.20
0.913
D
4.60
0.181
E
3.30
0.130
F
4.00
0.157
G
20.00
0.787
H
50.50
1.988
I
1.00 ± 0.100
Transcend information Inc
2
0.039 ± 0.004
E
I
144PIN PC133 Unbuffered SO-DIMM
512MB With 32Mx8 CL3
TS64MSS64V6F
Pinouts:
Pin
Pin
Pin Pin
No
Name
No Name
01
Vss
49
DQ13
03
DQ0
51
DQ14
05
DQ1
53
DQ15
07
DQ2
55
Vss
09
DQ3
57
*CB0
11
Vcc
59
*CB1
13
DQ4
61
CLK0
15
DQ5
63
Vcc
17
DQ6
65
/RAS
19
DQ7
67
/WE
21
Vss
69
/CS0
23
DQM0
71
*/CS1
25
DQM1
73
NC
27
Vcc
75
Vss
29
A0
77
*CB2
31
A1
79
*CB3
33
A2
81
Vcc
35
Vss
83
DQ16
37
DQ8
85
DQ17
39
DQ9
87
DQ18
41
DQ10
89
DQ19
43
DQ11
91
Vss
45
Vcc
93
DQ20
47
DQ12
95
DQ21
* Please refer Block Diagram
Pin
No
97
99
101
103
105
107
109
111
113
115
117
119
121
123
125
127
129
131
133
135
137
139
141
143
Pin
Name
DQ22
DQ23
Vcc
A6
A8
Vss
A9
A10
Vcc
DQM2
DQM3
Vss
DQ24
DQ25
DQ26
DQ27
Vcc
DQ28
DQ29
DQ30
DQ31
Vss
SDA
Vcc
Pin
No
02
04
06
08
10
12
14
16
18
20
22
24
26
28
30
32
34
36
38
40
42
44
46
48
Transcend information Inc
3
Pin
Name
Vss
DQ32
DQ33
DQ34
DQ35
Vcc
DQ36
DQ37
DQ38
DQ39
Vss
DQM4
DQM5
Vcc
A3
A4
A5
Vss
DQ40
DQ41
DQ42
DQ43
Vcc
DQ44
Pin
No
50
52
54
56
58
60
62
64
66
68
70
72
74
76
78
80
82
84
86
88
90
92
94
96
Pin
Name
DQ45
DQ46
DQ47
Vss
*CB4
*CB5
CKE0
Vcc
/CAS
*CKE1
*A12
*A13
*CLK1
Vss
*CB6
*CB7
Vcc
DQ48
DQ49
DQ50
DQ51
Vss
DQ52
DQ53
Pin
No
98
100
102
104
106
108
110
112
114
116
118
120
122
124
126
128
130
132
134
136
138
140
142
144
Pin
Name
DQ54
DQ55
Vcc
A7
BA0
Vss
*BA1
*A11
Vcc
DQM6
DQM7
Vss
DQ56
DQ57
DQ58
DQ59
Vcc
DQ60
DQ61
DQ62
DQ63
Vss
SCL
Vcc
144PIN PC133 Unbuffered SO-DIMM
512MB With 32Mx8 CL3
TS64MSS64V6F
Block Diagram
/CS
CLK
CKE
DQM
DQM3
A0~A12,BA0,1
DQ0~DQ7
/RAS
/CAS 32Mx8
/WE SDRAM
/CS
CLK
CKE
A0~A12,BA0,1
DQ0~DQ7
A0~A12,BA0,1
DQ0~DQ7
A0~A12,BA0,1
DQ0~DQ7
/RAS
/CAS 32Mx8
/WE SDRAM
/RAS
/CAS 32Mx8
/WE SDRAM
/CS
CLK
CKE
/RAS
/CAS 32Mx8
/WE SDRAM
/CS
CLK
CKE
DQM4
DQM5
DQM6
DQM7
A0~A12,BA0,1
DQ0~DQ7
/RAS
/CAS 32Mx8
/WE SDRAM
A0~A12,BA0,1
DQ0~DQ7
/RAS
/CAS 32Mx8
/WE SDRAM
A0~A12,BA0,1
DQ0~DQ7
/RAS
/CAS 32Mx8
/WE SDRAM
A0~A12,BA0,1
DQ0~DQ7
/RAS
/CAS 32Mx8
/WE SDRAM
/CS
CLK
CKE
/CS
CLK
CKE
/CS
CLK
CKE
/CS
CLK
CKE
DQM
DQM
DQM
DQM
/CS
CLK
CKE
DQM
DQM2
DQM
DQM1
DQM
DQM2
DQM3
A0~A12,BA0,1
DQ0~DQ7
/RAS
/CAS 32Mx8
/WE SDRAM
A0~A12,BA0,1
DQ0~DQ7
/RAS
/CAS 32Mx8
/WE SDRAM
A0~A12,BA0,1
DQ0~DQ7
/RAS
/CAS 32Mx8
/WE SDRAM
A0~A12,BA0,1
DQ0~DQ7
/RAS
/CAS 32Mx8
/WE SDRAM
/CS
CLK
CKE
/CS
CLK
/CS
CLK
/CS
CLK
CKE
CKE
DQM5
DQM4
EEPROM
SCL
SDA
SCL
A0
A1
CKE
DQM6
DQM
DQM1
DQM
DQM0
DQM
CKE1
/CS
CLK
CKE
DQM0
DQM
/CS1
/RAS
/CAS 32Mx8
/WE SDRAM
/CS
CLK
CKE
A0~A12,BA0,1
DQ0~DQ7
/RAS
/CAS 32Mx8
/WE SDRAM
DQM
/CS
CLK
CKE
A0~A12,BA0,1
DQ0~DQ7
DQM
A0~A12,BA0,1
DQ0~DQ7
/RAS
/CAS 32Mx8
/WE SDRAM
DQM
CLK1
A0~A12,BA0,1
DQ0~DQ7
/RAS
/CAS 32Mx8
/WE SDRAM
DQM
A0~A12
BA0~BA1
D0~D63
/RAS
/CAS
/WE
/CS0
CLK0
CKE0
DQM7
SDA
A2
This technical information is based on industry standard data and tests believed to be reliable. However , Transcend makes no warranties,
either expressed or implied, as to its accuracy and assumes no liability in connection with the use of this product. Transcend reserves the
right to make changes in specifications at any time without prior notice.
Transcend information Inc
4
144PIN PC133 Unbuffered SO-DIMM
512MB With 32Mx8 CL3
TS64MSS64V6F
ABSOLUTE MAXIMUM RATINGS
Parameter
Voltage on any pin relative to Vss
Voltage on VDD supply to Vss
Storage temperature
Power dissipation
Mean time between failure
Temperature Humidity Burning
Temperature Cycling Test
Note:
Symbol
VIN, VOUT
VDD, VDDQ
TSTG
PD
MTBF
THB
TC
Value
-1.0 to +4.6
-1.0 to +4.6
-55 to +150
16
50
85°C/85%, Static Stress
0°C ~ 125°C Cycling
Unit
V
V
°C
W
year
°C-%
°C
Permanent device damage may occur if ABSOLUTE MAXIMUM RATINGS are exceeded.
Functional operation should be restricted to recommended operating condition.
Exposure to higher than recommended voltage for extended periods of time could affect device
reliability.
DC OPERATING CONDITIONS AND CHARACTERISTICS
Recommended operating conditions (TA = 0 to 70°C)
Parameter
Symbol
Min
Input high voltage
VIH
2.0
Input low voltage
VIL
-0.3
Output high voltage
VOH
2.4
Output low voltage
VOL
Input leakage current
IIL
-10
output leakage current
IoL
-10
Typ
3.0
0
-
Max
VDD+0.3
0.8
0.4
10
10
Unit
V
V
V
V
uA
uA
Note
1
2
IOH=-2mA
IOL=2mA
3
-
Note: 1. VIH (max) = 2.0V AC .The overshoot voltage duration is ≤ 3ns.
2. VIL (min) = -2.0V AC .The undershoot voltage duration is ≤ 3ns.
3. Any input 0V ≤ VIN ≤ VDDQ.
Input leakage currents include Hi-Z output leakage for all bi-directional buffers with Tri-State outputs.
4. Dout is disabled, 0V ≤ VOUT ≤ VDDQ.
CAPACITANCE (VDD = 3.3V±0.3V, TA = 0°C~70°C)
Parameter
Symbol
Min
Max
Unit
Input capacitance (A0~A12, BA0, BA1)
CIN1
80
100
pF
Input capacitance (/RAS, /CAS, /WE)
CIN2
80
100
pF
Input capacitance (CKE0, CKE1)
CIN3
50
60
pF
Input capacitance (CLK0, CLK1)
CIN4
40
45
pF
Input capacitance (/CS0, /CS1)
CIN5
25
35
pF
Input capacitance (DQM0~DQM7)
CIN6
15
20
pF
COUT1
10
15
pF
Data input/output capacitance (DQ0~DQ63)
Transcend information Inc
5
144PIN PC133 Unbuffered SO-DIMM
512MB With 32Mx8 CL3
TS64MSS64V6F
DC CHARACTERISTICS
(Recommended operating condition unless otherwise noted, TA = 0 to 70°C)
Parameter
Symbol
Test Condition
Operating Current
ICC1
Burst Length =1
(One Bank Active)
tRC≥tRC(min)
IOL=0mA
Precharge Standby Current ICC2P
CKE≤VIL(max), tCC=10ns
in power-down mode
ICC2PS CKE & CLK≤VIL(max), tCC=∞
Precharge Standby Current ICC2N
in non power-down mode
CKE≥VIH(min), /CS≥VIH(min), tCC=10ns
Value (Typ)
1,200
Unit
mA
32
mA
Note
1
32
256
mA
Input signals are changed one time during 20ns
ICC2NS CKE≥VIH(min), CLK≤VIL(max), tCC=∞
224
Input signals are stable
Active Standby Current
in power-down mode
ICC3P
CKE≤VIL(max), tCC=10ns
96
ICC3PS
CKE & CLK≤VIL(max), tCC=∞
96
Active Standby Current
in non power-down mode
(One Bank Active)
ICC3N
CKE≥VIH(min), /CS≥VIH(min), tCC=10ns
480
mA
mA
Input singals are changed one time during 20ns
ICC3NS CKE≥VIH(min), CLK≤VIL(max), tCC=∞
400
Input signals are stable
Operating Current
(Bust Mode)
ICC4
Refresh Current
Self Refresh Current
Note:
ICC5
IOL= 0 mA
Page Burst
4Banks activated
tccD = 2CLKs
tRC≥tRC(min)
ICC6
CKE≤0.2V
mA
1
1,920
mA
1
80
mA
1,360
Module IDD was calculated on the basis of component IDD and can be differently measured according to
DQ loading cap.
Transcend information Inc
6
144PIN PC133 Unbuffered SO-DIMM
512MB With 32Mx8 CL3
TS64MSS64V6F
AC OPERATING TEST CONDITIONS (VDD = 3.3V ± 0.3V, TA = 0 to 65°C)
Parameter
AC Input levels (VIH/VIL)
Input timing measurement reference level
Input rise and fall time
Output timing measurement reference level
Output load condition
Value
2.4/0.4
1.4
tr/tf=1/1
1.4
See Fig. 2
Vtt=1.4V
3.3V
50 Ohm
1200 Ohm
VOH (DC)=2.4V, IOH=-2mA
VOL (DC)=0.4V, I OL=2mA
Output
870 Ohm
Unit
V
V
ns
V
Output
Z0=50 Ohm
50pF
50pF
(Fig. 2) AC Output Load Circuit
(Fig. 1) DC Output Load Circuit
OPERATING AC PARAMETER (AC operating conditions unless otherwise noted)
Parameter
Row active to row active delay
/RAS to /CAS delay
Row precharge time
Symbol
tRRD(min)
tRCD(min)
tRP(min)
tRAS(min)
tRAS(max)
tRC(min)
tCDL(min)
tDAL(min)
tRDL(min)
tBDL(min)
tCCD(min)
Value
Unit
Note
15
Ns
1
20
ns
1
20
ns
1
45
ns
1
Row active time
100
us
Row cycle time
@Operation
65
ns
1
Last data in to new col. address delay
2
CLK
2
Last data in to Active delay
2CLK+20ns
Last data in to row precharge
1
CLK
2
Last data in to burst stop
1
CLK
2
Col. address to col. address delay
1
CLK
3
Number of valid output data
2
ea
4
1. The minimum number of clock cycles is determined by dividing the minimum time required with clock
Note:
cycle time and then rounding off to the next higher integer.
2. Minimum delay is required to complete write.
3. All parts allow every cycle column address change.
4. In case of row precharge interrupt, auto precharge and read burst stop.
Transcend information Inc
7
144PIN PC133 Unbuffered SO-DIMM
512MB With 32Mx8 CL3
TS64MSS64V6F
AC Characteristics (TA = 0 to 65°C, VDD = 3.3V ± 0.3V, Vss= 0V)
Parameter
Symbol
tCK
tCKH
tCKL(min)
tAC
tOH
tLZ
tHZ
tAS, tCS, tDS, tCES
tCESP
tAH, tCH, tDH, tCEH
tRC
tRAS (min)
tRCD
tRP
tDPL
tRRD
tT (min)
tREF (max)
System clock cycle time
CK high pulse width
CK low pulse width
Access time from CK
Data-out hold time
CK to Data-out low impedance
CK to Data-out high impedance
Input setup time
CKE setup time for power down exit
Input hold time
Ref/Active to Ref/Active command period
Active to precharge command period
Active command to column command (same bank)
Precharge to active command period
Write recovery or data-in to precharge lead time
Active (a) to Active (b) command period
Transition time (rise and fall)
Refresh period
Note:
Value
Unit
Note
7.5
ns
1
2.5
ns
1
2.5
ns
1
5.4
ns
1,2
3.0
ns
1,2
0.0
ns
1,2
3.0
ns
1
1.5
ns
1
2.0
ns
1
0.8
ns
1
70.0
ns
1
45.0
ns
1
20.0
ns
1
20.0
ns
1
15.0
ns
1
15.0
ns
1
1.0
ns
64.0
ms
1. AC measurement assumes tT = 1ns. Reference level for timing of input signals is 1.5V.
2. Access time is measured at 1.5V. Load condition is CL = 50 pF
Transcend information Inc
8
144PIN PC133 Unbuffered SO-DIMM
512MB With 32Mx8 CL3
TS64MSS64V6F
SIMPLIFIED TRUTH TABLE
COMMAND
Register
CKEn-1 CKEn
Mode Register Set
Auto Refresh
Refresh
Self
Refresh
Entry
Exit
Bank Active & Row Addr.
Read &
Column Address
Write &
Column Address
Auto Precharge Disable
Auto Precharge Enable
Auto Precharge Disable
Auto Precharge Enable
Burst Stop
Precharge
Clock Suspend or
Active Power Down
/RAS
/CAS
/WE
DQM
BA0,1
A10/AP
H
X
L
L
L
L
X
OP CODE
H
H
L
L
L
L
H
X
X
L
H
L
H
H
X
H
X
H
X
X
X
H
X
L
L
H
H
X
V
H
X
L
H
L
H
X
V
H
X
L
H
L
L
X
H
X
L
H
H
L
X
Bank Selection
Both Banks
H
X
Entry
H
L
Exit
L
H
Entry
H
L
Precharge Power
Down Mode
L
L
H
L
H
X
X
X
L
V
V
V
X
X
X
X
H
X
X
X
L
H
H
H
H
X
X
X
L
V
V
V
X
V
V
X
A11,A12
A0~A9
Note
1,2
3
3
3
3
Row Address
L
H
L
H
X
L
H
4
Column
Address
(A0~A8)
4, 5
4
Column
Address
(A0~A8)
4, 5
6
X
X
X
X
X
X
Exit
L
DQM
H
No Operation Command
H
Note:
/CS
H
X
X
H
X
X
X
L
H
H
H
X
V
X
X
X
(V=Valid, X=Don’t Care, H=Logic High, L=Logic Low)
1. OP Code: Operand Code
A0~A12, BA0~BA1: Program keys. (@MRS)
2. MRS can be issued only at both banks precharge state.
A new command can be issued after 2 CLK cycles of MRS.
3. Auto refresh functions are as same as CBR refresh of DRAM.
The automatic precharge without row precharge command is meant by “Auto”.
Auto/self refresh can be issued only at both banks precharge state.
4. BA0~BA1: Bank select address.
If both BA0 and BA1 are “Low” at read, write, row active and precharge, bank A is selected.
If both BA0 is “Low” and BA1 is “High” at read, write, row active and precharge, bank B is selected.
If both BA0 is “High” and BA1 is “Low” at read, write, row active and precharge, bank C is selected.
If both BA0 and BA1 are “High” at read, write, row active and precharge, bank D is selected.
If A10/AP is “High” at row precharge, BA0 and BA1 is ignored and both banks are selected.
5. During burst read or write with auto precharge, new read/write command cannot be issued.
Another bank read/write command can be issued after the end of burst.
New row active of the associated bank can be issued at tRP after the end of burst.
6. Burst stop command is valid at every burst length.
7. DQM sampled at positive going edged of a CLK masks the data-in at the very CLK (Write DQM latency is 0),
but makes Hi-Z state the data-out of 2 CLK cycles after. (Read DQM latency is 2)
Transcend information Inc
9
7
144PIN PC133 Unbuffered SO-DIMM
512MB With 32Mx8 CL3
TS64MSS64V6F
Serial Presence Detect Specification
Serial Presence Detect
Byte No.
Function Described
Standard
Specification
Vendor Part
0
Number of Bytes Written into Serial Memory
128bytes
80
1
Total Number of Bytes of S.P.D Memory
256bytes
08
2
Fundamental Memory Type
SDRAM
04
3
Number of Row Addresses on this Assembly
13
0D
4
Number of Column Addresses on this Assembly
10
0A
5
Number of Module Banks on this Assembly
2 bank
02
6
Data Width of this Assembly
64bits
40
7
Data Width Continuation
-
00
8
Voltage Interface Standard of this Assembly
LVTTL3.3V
01
9
SDRAM Cycle Time (highest CAS latency)
7.5ns
75
10
SDRAM Access from Clock (highest CL)
5.4ns
54
11
DIMM configuration type (non-parity, ECC)
Non parity
00
7.8us/Self Refresh
82
X8
08
None
00
1 clock
01
1,2,4,8,full
8F
4 bank
04
2&3
06
12
Refresh Rate Type
13
Primary SDRAM Width
14
Error Checking SDRAM Width
15
Min Clock Delay Back to Back Random Address
16
Burst Lengths Supported
17
Number of banks on each SDRAM device
18
CAS Latency
19
CS Latency
0 clock
01
20
Write Latency
0 clock
01
21
SDRAM Module Attributes
Non Buffer
00
22
SDRAM Device Attributes : General
Prec All, Auto Prec,
R/W Burst
0E
23
SDRAM Cycle Time (2nd highest CL)
10ns
A0
6ns
60
24
nd
SDRAM Access from Clock (2 highest CL)
rd
25
SDRAM Cycle Time (3 highest CL)
-
00
26
SDRAM Access from Clock (3rd highest CL)
-
00
27
Minimum Row Precharge Time
20ns
14
28
Minimum Row Active to Row Activate
15ns
0F
29
Minimum RAS to CAS Delay
20ns
14
30
Minimum RAS Pulse Width
45ns
2D
31
Density of Each Bank on Module
1row of 256MB
40
32
Command/Address Setup Time
1.5ns
15
33
Command/Address Hold Time
0.8ns
08
Transcend information Inc
10
144PIN PC133 Unbuffered SO-DIMM
512MB With 32Mx8 CL3
TS64MSS64V6F
34
Data Signal Setup Time
1.5ns
15
35
Data Signal Hold Time
0.8ns
08
-
00
36-61
Superset Information
62
SPD Data Revision Code
JEDCE2
02
63
Checksum for Bytes 0-62
-
C3
Transcend
7F,4F
T
54
64-71
72
Manufacturers JEDEC ID Code per JEP-108E
Manufacturing Location
54 53 36 34 4D 53
73-90
Manufacturers Part Number
TS64MSS64V 6F
53 36 34 56 36 46
20 20 20 20 20 20
91-92
Revision Code
-
93-94
Manufacturing Date
By Manufacturer
Variable
95-98
Assembly Serial Number
By Manufacturer
Variable
99-125
Manufacturer Specific Data
-
0
126
Intel Specification Frequency
-
64
127
Intel Specification CAS# Latency/Clock Signal Support
CL=2, 3 Clock 0,1
F6
128~
Unused Storage Locations
Open
FF
Transcend information Inc
11
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