Transcend TS32MLS64V6G Datasheet

Transcend TS32MLS64V6G Datasheet
168PIN PC133 Unbuffered DIMM
256MB With 16Mx16 CL3
TS32MLS64V6G
Description
Placement
The TS32MLS64V6G is a 32M bit x 64 Synchronous
Dynamic
RAM
high-density
memory
modules.
The
TS32MLS64V6G consists of 8 piece of CMOS 16Mx16bits
Synchronous DRAMs in TFBGA 400mil packages and a
2048 bits serial EEPROM on a 168-pin printed circuit board.
The TS32MLS64V6G is a Dual In-Line Memory Module and
is intended for mounting into 168-pin edge connector
sockets.
Synchronous design allows precise cycle control with the
use of system clock. I/O transactions are possible on every
clock cycle. Range of operation frequencies, programmable
A
latencies allow the same device to be useful for a variety of
high
bandwidth,
high
performance
memory
system
applications.
B
Features
•
RoHS compliant products.
•
Performance Range: PC133.
•
Burst Mode Operation.
•
Auto and Self Refresh.
•
Serial Presence Detect (SPD) with serial
D
E
H
G
EEPROM
•
LVTTL compatible inputs and outputs.
•
Single 3.3V + 0.3V power supply.
•
MRS cycle with address key programs.
F
PCB: 09-2410
Latency (Access from column address)
Burst Length (1,2,4,8 & Full Page)
Data Scramble (Sequential & Interleave)
•
All inputs are sampled at the positive going edge
of the system clock.
Transcend information Inc.
C
E
1
I
168PIN PC133 Unbuffered DIMM
256MB With 16Mx16 CL3
TS32MLS64V6G
Pin Identification
Dimensions
Symbol
Function
Side
Millimeters
A
133.35±0.40
5.250±0.016
A0~A12
Address inputs
B
65.67000
2.585000
BA0, BA1
Select Bank
C
23.49000
0.925000
D
8.89000
0.350000
DQ0~DQ63
Data inputs/outputs
E
3.00000
0.118000
CLK0~3
Clock Input
F
22.225±0.200
0.875±0.00800
G
19.8000
0.788000
H
15.80
0.622
I
1.27±0.10
(Refer Placement)
Transcend information Inc.
Inches
CKE0, CKE1 Clock Enable Input
0.050±0.004
2
/CS0~3
Chip Select Input
/RAS
Row address strobe
/CAS
Column address strobe
/WE
Write Enable
DQM0~7
DQM
Vcc
Power Supply
Vss
Ground
SDA
Serial Address / Data I/O
SA0~2
Address in EEPROM
WP
Write protection
SCL
Serial Clock
NC
No Connection
168PIN PC133 Unbuffered DIMM
256MB With 16Mx16 CL3
TS32MLS64V6G
Pinouts:
Pin
Pin
Pin
No
Name
No
01
Vss
43
02
DQ0
44
03
DQ1
45
04
DQ2
46
05
DQ3
47
06
Vcc
48
07
DQ4
49
08
DQ5
50
09
DQ6
51
10
DQ7
52
11
DQ8
53
12
Vss
54
13
DQ9
55
14
DQ10
56
15
DQ11
57
16
DQ12
58
17
DQ13
59
18
Vcc
60
19
DQ14
61
20
DQ15
62
21
*CB0
63
22
*CB1
64
23
Vss
65
24
NC
66
25
NC
67
26
Vcc
68
27
/WE
69
28
DQM0
70
29
DQM1
71
30
/CS0
72
31
NC
73
32
Vss
74
33
A0
75
34
A2
76
35
A4
77
36
A6
78
37
A8
79
38
A10/AP
80
39
BA1
81
40
Vcc
82
41
Vcc
83
42
CLK0
84
*Please refer Block Diagram
Transcend information Inc.
Pin
Name
Vss
NC
/CS2
DQM2
DQM3
NC
Vcc
NC
NC
*CB2
*CB3
Vss
DQ16
DQ17
DQ18
DQ19
Vcc
DQ20
NC
*Vref
*CKE1
Vss
DQ21
DQ22
DQ23
Vss
DQ24
DQ25
DQ26
DQ27
Vcc
DQ28
DQ29
DQ30
DQ31
Vss
*CLK2
NC
NC
SDA
SCL
Vcc
3
Pin
No
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
101
102
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
121
122
123
124
125
126
Pin
Name
Vss
DQ32
DQ33
DQ34
DQ35
Vcc
DQ36
DQ37
DQ38
DQ39
DQ40
Vss
DQ41
DQ42
DQ43
DQ44
DQ45
Vcc
DQ46
DQ47
*CB4
*CB5
Vss
NC
NC
Vcc
/CAS
DQM4
DQM5
*/CS1
/RAS
Vss
A1
A3
A5
A7
A9
BA0
A11
Vcc
*CLK1
*A12
Pin
No
127
128
129
130
131
132
133
134
135
136
137
138
139
140
141
142
143
144
145
146
147
148
149
150
151
152
153
154
155
156
157
158
159
160
161
162
163
164
165
166
167
168
Pin
Name
Vss
CKE0
*/CS3
DQM6
DQM7
*A13
Vcc
NC
NC
*CB6
*CB7
Vss
DQ48
DQ49
DQ50
DQ51
Vcc
DQ52
NC
*Vref
*REGE
Vss
DQ53
DQ54
DQ55
Vss
DQ56
DQ57
DQ58
DQ59
Vcc
DQ60
DQ61
DQ62
DQ63
Vss
*CLK3
NC
SA0
SA1
SA2
Vcc
168PIN PC133 Unbuffered DIMM
256MB With 16Mx16 CL3
TS32MLS64V6G
Block Diagram
DQ0~DQ63
A0~A12,
BA0,BA1
DQ0~DQ15
A0~A12,
BA0,BA1
DQ0~DQ15
A0~A12,
BA0,BA1
DQ0~DQ15
A0~A12,
BA0,BA1
DQ0~DQ15
/RAS
/RAS
/RAS
/RAS
/RAS
/CS
/CS
CLK0
CLK
CKE0
CKE
CLK
CKE
CLK
CKE
/CAS
CLK
CKE
16Mx16
SDRAM
UDQM
/CS
UDQM
/CS
LDQM
/CS0
UDQM
/WE
/CAS
LDQM
16Mx16
/CAS
SDRAM
/WE
UDQM
16Mx16
/CAS
SDRAM
/WE
LDQM
/WE
16Mx16
/CAS
SDRAM
/WE
LDQM
A0~A12,BA0,BA1
DQM4
DQM0
DQM5
DQM1
DQM6
DQM2
DQM7
DQM3
A0~A12,
BA0,BA1
A0~A12,
BA0,BA1
A0~A12,
BA0,BA1
A0~A12,
BA0,BA1
DQ0~DQ15
DQ0~DQ15
DQ0~DQ15
DQ0~DQ15
/RAS
/RAS
/RAS
/RAS
/CS2
CLK2
/CS
CLK1
CLK
CKE1
CKE
CLK
CKE
DQM5
DQM1
DQM4
DQM0
CLK
CKE
DQM6
DQM2
CLK
CKE
16Mx16
SDRAM
UDQM
/CS
/CAS
LDQM
/CS
UDQM
/CS
LDQM
/CS1
UDQM
/WE
LDQM
16Mx16
/CAS
SDRAM
/WE
UDQM
16Mx16
/CAS
SDRAM
/WE
LDQM
16Mx16
/CAS
SDRAM
/WE
DQM7
DQM3
/CS3
CLK3
Serial
EEPROM
SCL
SCL
A0
SDA
WC
A1 A2
SDA
WP
SA0 SA1 SA2
This technical information is based on industry standard data and tests believed to be reliable. However, Transcend makes no warranties, either expressed
or implied, as to its accuracy and assume no liability in connection with the use of this product. Transcend reserves the right to make changes in specifications
at any time without prior notice.
Transcend information Inc.
4
168PIN PC133 Unbuffered DIMM
256MB With 16Mx16 CL3
TS32MLS64V6G
ABSOLUTE MAXIMUM RATINGS
Parameter
Symbol
Value
Unit
Voltage on any pin relative to Vss
VIN, VOUT
-1.0~4.6
V
Voltage on VDD supply relative to Vss
VDD, VDDQ
-1.0~4.6
V
°C
Storage temperature
TSTG
-55~+150
Power dissipation
PD
8
W
Short circuit current
LOS
50
mA
°C
Operating Temperature
TA
0~70
Note: Permanent device damage may occur if ABSOLUTE MAXIMUM RATINGS are exceeded.
Functional operation should be restricted to recommended operating condition.
Exposure to higher than recommended voltage for extended periods of time could affect device reliability.
DC OPERATING CONDITIONS AND CHARACTERISTICS
Recommended operating conditions (Voltage referenced to Vss = 0V, TA = 0 to 70 °C)
Parameter
Symbol
Min
Typ
Max
Unit
Supply voltage
VDD
3.0
3.3
3.6
V
Input high voltage
VIH
2.0
3.0
VDD+0.3
V
Input low voltage
VIL
-0.3
0
0.8
V
Output high voltage
VOH
2.4
V
Output low voltage
VOL
0.4
V
Input leakage current
ILI
-10
10
uA
Note
1
2
IOH = -2mA
IOL = 2mA
3
Note: 1. VIH (max) = 5.6V AC. The overshoot voltage duration is < 3ns.
2. VIL (min) = -2.0V AC. The undershoot voltage duration is < 3ns.
3. Any input 0V ≤ Vin ≤VDDQ.
Input leakage currents include Hi-Z output leakage for all bi-directional buffers with Tri-state output.
CAPACITANCE (VDD = 3.3V, TA = 23℃, f = 1MHz, VREF = 1.4V ± 200mV)
Parameter
Input capacitance (A0~A12, BA0~BA1)
Input capacitance (/RAS, /CAS, /WE)
Input capacitance (CKE0, CKE1)
Input capacitance (CLK0~CLK3)
Input capacitance (/CS0~/CS3)
Input capacitance (DQM0~DQM7)
Data input/output capacitance (DQ0~DQ63)
Symbol
Min
Max
Unit
CADD
CIN
CCKE
CCLK
CCS
CDQM
COUT
25
25
15
15
15
10
13
45
45
25
21
25
12
18
pF
pF
pF
pF
pF
pF
pF
DC CHARACTERISTICS
(Recommended operating condition unless otherwise noted, TA = 0 to 70°C)
Parameter
Symbol
Test Condition
Transcend information Inc.
5
Value
Unit
Note
168PIN PC133 Unbuffered DIMM
256MB With 16Mx16 CL3
TS32MLS64V6G
Operating Current
(One Bank Active)
Precharge Standby Current
in power-down mode
Precharge Standby Current
in non power-down mode
Burst Length =1
tRC≥tRC(min)
IOL=0mA
ICC2P CKE≤VIL(max), tCC=10ns
ICC1
520
16
ICC2PS CKE & CLK≤VIL(max), tCC=∞
16
ICC2N CKE≥VIH(min), /CS≥VIH(min), tCC=10ns
160
mA
1
mA
mA
Input signals are changed one time during 20ns
80
ICC2NS CKE≥VIH(min), CLK≤VIL(max), tCC=∞
Input signals are stable
Active Standby Current
in power-down mode
ICC3P CKE≤VIL(max), tCC=10ns
240
CKE≥VIH(min), /CS≥VIH(min), tCC=10ns
Input signals are changed one time during 20ns
ICC3NS
mA
48
ICC3PS CKE & CLK≤VIL(max), tCC=∞
ICC3N
Active Standby Current
in non power-down mode
(One Bank Active)
48
mA
200
CKE≥VIH(min), CLK≤VIL(max), tCC=∞
Input signals are stable
IOL= 0 mA
Page Burst
tccD = 2CLKs
680
Icc5
tRC ≤ tRC(min)
920
ICC6
CKE≤0.2V
Operating Current
(Burst Mode)
ICC4
Refresh current
Self Refresh Current
C
L
24
12
mA
1
mA
2
mA
Note: 1. Measured with outputs open.
2. Refresh period is 64 ms.
3. Unless otherwise noted, input swing level is CMOS (VIH / VIL=VDDQ / VSSQ)
AC OPERATING TEST CONDITIONS (VDD = 3.3V±0.3V, TA = 0 to 70°C)
Parameter
AC Input levels (VIH/VIL)
Transcend information Inc.
Value
2.4/0.4
6
Unit
V
168PIN PC133 Unbuffered DIMM
256MB With 16Mx16 CL3
TS32MLS64V6G
Input timing measurement reference level
Input rise and fall time
Output timing measurement reference level
Output load condition
1.4
tr/tf=1/1
1.4
See Fig. 2
Vtt=1.4V
3.3V
50 Ohm
1200 Ohm
Output
VOH (DC)=2.4V, IOH=-2mA
VOL (DC)=0.4V, I OL=2mA
Output
Z0=50 Ohm
50pF
50pF
870 Ohm
V
ns
V
(Fig. 2) AC Output Load Circuit
(Fig. 1) DC Output Load Circuit
OPERATING AC PARAMETER (AC operating conditions unless otherwise noted)
Parameter
Row active to row active delay
Symbol
tRRD(min)
Value
15
Unit
ns
Note
1
/RAS to /CAS delay
tRCD(min)
20
ns
1
Row precharge time
tRP(min)
20
ns
1
Row active time
tRAS(min)
45
ns
1
tRAS(max)
100
us
Row cycle time
tRC(min)
65
ns
1
Last data in to row precharge
tRDL(min)
2
CLK
2
Last data in to new col. address delay
tCDL(min)
1
CLK
2
Last data in to Active delay
tDAL
-
Last data in to burst stop
tBDL(min)
2CLK+tRP
1
CLK
2
Col. address to col. address delay
tCCD(min)
1
CLK
3
Number of valid output data
CAS latency=3
2
ea
Note: 1. The minimum number of clock cycles is determined by dividing the minimum time required with
clock cycle time, and then rounding off to the next higher integer.
2. Minimum delay is required to complete write.
3. All parts allow every cycle column address change.
4. In case of row precharge interrupt, auto precharge and read burst stop.
Transcend information Inc.
7
4
168PIN PC133 Unbuffered DIMM
256MB With 16Mx16 CL3
TS32MLS64V6G
AC CHARACTERISTICS (AC operating conditions unless otherwise noted)
Refer to the individual component, not the whole module.
Parameter
Symbol
CLK cycle time
tCC
CLK to valid
output delay
tSAC
Output data
hold time
tOH
CLK high pulse width
CLK low pulse width
Input setup time
Input hold time
CLK to output in Low-Z
tCH
tCL
tSS
tSH
tSLZ
CLK to output
in Hi-Z
tSHZ
Note:
Value
Unit
Note
1000
ns
1
5.4
ns
1, 2
ns
2
ns
ns
ns
ns
ns
3
3
3
3
2
Min
Max
7.5
3
2.5
2.5
1.5
0.8
1
5.4
ns
1. Parameters depend on programmed CAS latency.
2. If clock rising time is longer than 1ns, (tr/2-0.5) ns should be added to the parameter.
3. Assumed input rise and fall time (tr & tf)= 1ns.
If tr & tf is longer than 1ns, transient time compensation should be considered,
i.e., [(tr + tf)/2-1]ns should be added to the parameter.
Transcend information Inc.
8
168PIN PC133 Unbuffered DIMM
256MB With 16Mx16 CL3
TS32MLS64V6G
SIMPLIFIED TRUTH TABLE
COMMAND
Register
Mode Register Set
CKEn-1
CKEn
/CS
/RAS
/CAS
/WE
DQM
H
X
L
L
L
L
X
OP CODE
L
L
L
H
X
X
L
H
H
H
X
X
H
X
X
X
Auto Refresh
Entry
Refresh
Self
Refresh
Exit
Bank Active & Row Addr.
Read &
BA0,1
Auto Precharge Enable
Write &
Auto Precharge Disable
Column Address
Auto Precharge Enable
Burst Stop
L
L
H
Both Banks
Clock Suspend or
Active Power
Down
X
L
L
H
H
X
V
H
X
L
H
L
H
X
V
H
X
L
H
L
L
X
V
H
X
L
H
H
L
X
H
X
L
L
H
L
X
H
X
X
X
L
V
V
V
X
X
X
X
H
X
X
X
L
H
H
H
H
X
X
X
Exit
L
H
H
L
Precharge Power
Down Mode
Exit
L
H
L
DQM
No Operation Command
V
X
V
H
X
X
L
H
H
H
X
V
H
9
Column
Address
(A0~A8)
H
X
V
L
X
H
4
4, 5
4
4, 5
6
X
X
X
X
X
X
X
V
X
X
X
X
H
H
(V=Valid, X=Don’t Care, H=Logic High, L=Logic Low)
Note: 1. OP Code : Operand Code
A0~A12, BA0~BA1 : Program keys. (@MRS)
2. MRS can be issued only at all banks precharge state.
A new command can be issued after 2 CLK cycles of MRS.
3. Auto refresh functions are as same as CBR refresh of DRAM.
The automatically precharge without row precharge command is meant by “Auto”.
Auto/self refresh can be issued only at all banks precharge state.
4. BA0~BA1: Bank select address.
If both BA0 and BA1 are “Low” at read, write, row active and precharge, bank A is selected.
If both BA0 is “Low” and BA1 is “High” at read, write, row active and precharge, bank B is selected.
If both BA0 is “High” and BA1 is “Low” at read, write, row active and precharge, bank C is selected.
If both BA0 and BA1 are “High” at read, write, row active and precharge, bank D is selected.
If A10/AP is “High” at row precharge, BA0 and BA1 are ignored and all banks are selected.
5. During burst read or write with auto precharge, new read/write command can not be issued.
Another bank read/write command can be issued after the end of burst.
New row active of the associated bank can be issued at tRP after the end of burst.
6. Burst stop command is valid at every burst length.
7. DQM sampled at positive going edged of a CLK masks the data-in at the very CLK (Write DQM latency is 0),
but makes Hi-Z state the data-out of 2 CLK cycles after. (Read DQM latency is 2)
Transcend information Inc.
3
Column
Address
(A0~A8)
L
L
3
Row Address
L
H
Entry
1,2
3
H
Entry
Note
3
Bank Selection
Precharge
A11, A12,
A0~A9
H
H
Auto Precharge Disable
Column Address
A10/AP
7
168PIN PC133 Unbuffered DIMM
256MB With 16Mx16 CL3
TS32MLS64V6G
Serial Presence Detect Specification
Serial Presence Detect
Byte No.
Standard Specification
Vendor Part
0
# of Bytes Written into Serial Memory
128bytes
80
1
Total # of Bytes of S.P.D Memory
256bytes
08
2
Fundamental Memory Type
SDRAM
04
3
# of Row Addresses on this Assembly
A0~A12
0D
4
# of Column Addresses on this Assembly
A0~A8
09
5
# of Module Banks on this Assembly
2 banks
02
6
Data Width of this Assembly
64bits
40
7
Data Width Continuation
0
00
8
Voltage Interface Standard of this Assembly
LVTTL3.3V
01
9
SDRAM Cycle Time (highest CAS latency)
7.5ns
75
10
SDRAM Access from Clock (highest CL)
5.4ns
54
11
DIMM configuration type (non-parity, ECC)
DIMM
00
12
Refresh Rate Type
7.8us/Self Refresh
82
13
Primary SDRAM Width
X16
10
14
Error Checking SDRAM Width
0
00
15
Min Clock Delay Back to Back Random Address
1 clock
01
16
Burst Lengths Supported
1,2,4,8 & Full page
8F
17
Number of banks on each SDRAM device
4 bank
04
18
CAS # Latency
2,3
06
19
CS # Latency
0 clock
01
20
Write Latency
0 clock
01
21
SDRAM Module Attributes
Non Buffer
00
22
SDRAM Device Attributes: General
Prec All, Auto Prec, R/W
Burst
0E
23
SDRAM Cycle Time (2nd highest CL)
10ns
A0
6ns
60
-
00
-
00
24
25
Function Described
nd
SDRAM Access from Clock (2 highest CL)
rd
SDRAM Cycle Time (3 highest CL)
rd
26
SDRAM Access from Clock (3 highest CL)
27
Minimum Row Precharge Time
20ns
14
28
Minimum Row Active to Row Activate
15ns
0F
29
Minimum RAS to CAS Delay
20ns
14
30
Minimum RAS Pulse Width
45ns
2D
31
Density of Each Bank on Module
128MB
20
32
Command/Address Setup Time
1.5ns
15
33
Command/Address Hold Time
0.8ns
08
34
Data Signal Setup Time
1.5ns
15
35
Data Signal Hold Time
0.8ns
08
Transcend information Inc.
10
168PIN PC133 Unbuffered DIMM
256MB With 16Mx16 CL3
TS32MLS64V6G
36-61
Superset Information
-
00
62
SPD Data Revision Code
JEDEC2
02
63
Checksum for Bytes 0-62
AA
AA
Transcend
7F, 4F
T
54
64-71
72
Manufacturers JEDEC ID Code per JEP-108E
Manufacturing Location
54 53 33 32 4D 4C
73-90
Manufacturers Part Number
TS32MLS64V6G
53 36 34 56 36 47
20 20 20 20 20 20
91-92
Revision Code
-
0
93-94
Manufacturing Date
By Manufacturer
Variable
95-98
Assembly Serial Number
By Manufacturer
Variable
99-125
Manufacturer Specific Data
-
0
Intel Specification Frequency
-
64
126
127
Intel Specification CAS# Latency/Clock Signal Support
128~
Unused Storage Locations
Transcend information Inc.
11
CL=3 Clock=0~2
F6
Open
FF
Was this manual useful for you? yes no
Thank you for your participation!

* Your assessment is very important for improving the work of artificial intelligence, which forms the content of this project

Download PDF

advertisement